samsung update 1

476 files changed, 351869 insertions, 1774 deletions

diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index bb53de7..8298e84 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -66,6 +66,27 @@ config VIDEOBUF2_DMA_SG
 	select VIDEOBUF2_CORE
 	select VIDEOBUF2_MEMOPS
 	tristate
+
+choice
+prompt "Select Videobuf2 allocator"
+default VIDEOBUF2_CMA_PHYS
+config VIDEOBUF2_CMA_PHYS
+	bool "CMA_PHYS"
+	depends on CMA
+	select VIDEOBUF2_CORE
+	select VIDEOBUF2_MEMOPS
+	help
+	  Use videobuf2 CMA-phys allocator
+
+config VIDEOBUF2_ION
+	bool "Android ION"
+	depends on ION_EXYNOS
+	select VIDEOBUF2_CORE
+	select VIDEOBUF2_MEMOPS
+	help
+	  Use videobuf2 Android ION allocator
+endchoice
+
 #
 # Multimedia Video device configuration
 #
@@ -377,6 +398,302 @@ config VIDEO_VPX3220
 	  To compile this driver as a module, choose M here: the
 	  module will be called vpx3220.
 
+config VIDEO_S5K3H2
+        tristate "S5K3H2 supporting camera driver"
+	depends on VIDEO_V4L2 && (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS) && VIDEO_EXYNOS_FIMC_IS
+        ---help---
+          This driver supports S5K3H2 sensor.
+choice
+depends on VIDEO_S5K3H2
+prompt "MIPI Camera port for S5K3H2"
+default S5K3H2_CSI_C
+config S5K3H2_CSI_C
+	bool "CSI Camera A port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	help
+	  This enables support for CSI A port
+config S5K3H2_CSI_D
+	bool "CSI Camera B port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	help
+	  This enables support for CSI B port
+endchoice
+
+config VIDEO_S5K3H7
+        tristate "S5K3H7 supporting camera driver"
+	depends on VIDEO_V4L2 && (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS) && VIDEO_EXYNOS_FIMC_IS
+        ---help---
+          This driver supports S5K3H7 sensor.
+choice
+depends on VIDEO_S5K3H7
+prompt "MIPI Camera port for S5K3H7"
+default S5K3H7_CSI_C
+config S5K3H7_CSI_C
+	bool "CSI Camera A port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	help
+	  This enables support for CSI A port
+config S5K3H7_CSI_D
+	bool "CSI Camera B port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	help
+	  This enables support for CSI B port
+endchoice
+
+config VIDEO_S5K4E5
+        tristate "S5K4E5 supporting camera driver"
+	depends on VIDEO_V4L2 && ((VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS) && VIDEO_EXYNOS_FIMC_IS) || VIDEO_EXYNOS5_FIMC_IS 
+        ---help---
+          This driver supports S5K4E5 sensor.
+choice
+depends on VIDEO_S5K4E5
+prompt "MIPI Camera port for S5K4E5"
+default S5K4E5_CSI_C
+config S5K4E5_CSI_C
+	bool "CSI Camera A port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS || VIDEO_EXYNOS5_FIMC_IS)
+	help
+	  This enables support for CSI A port
+config S5K4E5_CSI_D
+	bool "CSI Camera B port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS || VIDEO_EXYNOS5_FIMC_IS)
+	help
+	  This enables support for CSI B port
+endchoice
+choice
+depends on (VIDEO_S5K4E5 && VIDEO_EXYNOS5_FIMC_IS)
+prompt "Camera position for S5K4E5"
+default S5K4E5_POSITION_REAR
+config S5K4E5_POSITION_FRONT
+	bool "front camera"
+	depends on VIDEO_EXYNOS5_FIMC_IS
+	help
+	  This set as front camera
+config S5K4E5_POSITION_REAR
+	bool "rear camera"
+	depends on VIDEO_EXYNOS5_FIMC_IS
+	help
+	  This set as rear camera
+endchoice
+
+config VIDEO_S5K6A3
+	tristate "S5K6A3 supporting camera driver"
+	depends on VIDEO_V4L2 && ((VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS) && VIDEO_EXYNOS_FIMC_IS) || VIDEO_EXYNOS5_FIMC_IS 
+	---help---
+	  This driver supports S5K6A3 sensor.
+choice
+depends on VIDEO_S5K6A3
+prompt "MIPI Camera port for S5K6A3"
+default S5K6A3_CSI_D
+config S5K6A3_CSI_C
+	bool "CSI Camera A port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS || VIDEO_EXYNOS5_FIMC_IS)
+	help
+	  This enables support for CSI A port
+config S5K6A3_CSI_D
+	bool "CSI Camera B port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS || VIDEO_EXYNOS5_FIMC_IS)
+	help
+	  This enalbes support for CSI B port
+endchoice
+choice
+depends on (VIDEO_S5K6A3 && VIDEO_EXYNOS5_FIMC_IS)
+prompt "Camera position for S5K6A3"
+default S5K6A3_POSITION_FRONT
+config S5K6A3_POSITION_FRONT
+	bool "front camera"
+	depends on VIDEO_EXYNOS5_FIMC_IS
+	help
+	  This set as front camera
+config S5K6A3_POSITION_REAR
+	bool "rear camera"
+	depends on VIDEO_EXYNOS5_FIMC_IS
+	help
+	  This set as rear camera
+endchoice
+
+config VIDEO_M5MO
+        tristate "M5MO supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+        ---help---
+          This driver supports M5MO SoC camera module
+
+config VIDEO_M9MO
+        tristate "M9MO supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+        ---help---
+          This driver supports M9MO SoC camera module
+
+config VIDEO_S5K5BAFX
+	tristate "S5K5BAFX supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+	---help---
+	  This driver supports S5K5BAFX SoC camera module
+
+config VIDEO_S5K5CCGX_COMMON
+	tristate "S5K5CCGX supporting camera driver"
+	depends on I2C && VIDEO_V4L2
+	---help---
+	  This driver supports S5K5CCGX SoC camera module
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_S5K5CCGX_P2
+	tristate "S5K5CCGX supporting camera driver for P2"
+	depends on VIDEO_S5K5CCGX_COMMON
+	---help---
+	  This driver supports S5K5CCGX SoC camera module
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_S5K5CCGX_P4W
+	tristate "S5K5CCGX supporting camera driver for P4W"
+	depends on VIDEO_S5K5CCGX_COMMON
+	---help---
+	  This driver supports S5K5CCGX SoC camera module
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_S5K5CCGX_P8
+	tristate "S5K5CCGX supporting camera driver for P8"
+	depends on VIDEO_S5K5CCGX_COMMON
+	---help---
+	  This driver supports S5K5CCGX SoC camera module
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_SR200PC20
+	tristate "SR200PC20 supporting camera driver"
+	depends on I2C && VIDEO_V4L2
+	---help---
+	  This driver supports SR200PC20 SoC camera module
+	  SR200PC20 camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_SR200PC20_P2
+	tristate "SR200PC20 supporting camera driver"
+	depends on VIDEO_SR200PC20
+	---help---
+	  This driver supports SR200PC20 SoC camera module
+	  SR200PC20 camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_SR200PC20_P4W
+	tristate "SR200PC20 supporting camera driver"
+	depends on VIDEO_SR200PC20
+	---help---
+	  This driver supports SR200PC20 SoC camera module.
+	  SR200PC20 camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_SR200PC20M
+	tristate "SR200PC20M supporting camera driver"
+	depends on I2C && VIDEO_V4L2
+	---help---
+	  This driver supports SR200PC20M SoC camera module
+	  SR200PC20M camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_ISX012
+	tristate "ISX012 supporting camera driver"
+	depends on I2C && VIDEO_V4L2
+	---help---
+	  This driver supports ISX012 SoC camera module
+	  ISX012 camera module is SONY camera sensor supporting 5M capture
+	  and Full-HD recording with 30 fps.
+
+config VIDEO_SLP_S5K4ECGX
+	tristate "S5K4ECGX supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+	---help---
+	  This driver supports S5K4ECGX SoC camera module
+
+config VIDEO_SLP_DB8131M
+	tristate "DB8131M supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+	---help---
+	  This driver supports DB8131M SoC camera module
+
+config VIDEO_S5K4BA
+	tristate "S5K4BA supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && (VIDEO_FIMC || VIDEO_SAMSUNG_S5P_FIMC) && !(VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	---help---
+	  This driver supports s5k4ba SoC camera module
+
+config VIDEO_S5K4EA
+	tristate "S5K4EA MIPI CSI-2 supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS)
+	---help---
+	  This driver supports s5k4ea SoC camera module with
+	  MIPI CSI-2 as well
+
+config VIDEO_S5C73M3
+	tristate "S5C73M3 MIPI CSI-2 supporting camera driver"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+	---help---
+	  This driver supports s5c73m3 ISP camera module with
+	  MIPI CSI-2 as well
+
+config VIDEO_S5C73M3_SPI
+	tristate "S5C73M3 SPI driver"
+	depends on SPI && (VIDEO_S5C73M3 || VIDEO_SLP_S5C73M3)
+	---help---
+	  This driver supports s5c73m3 SPI
+
+config VIDEO_SLP_S5C73M3
+	tristate "S5C73M3 MIPI CSI-2 supporting camera driver for slp"
+	depends on I2C && VIDEO_V4L2 && VIDEO_FIMC_MIPI
+	---help---
+	  This driver supports s5c73m3 ISP camera module with MIPI CSI-2 as well
+
+config VIDEO_IMPROVE_STREAMOFF
+	bool "Improve shtter lag"
+	depends on VIDEO_FIMC_MIPI
+	---help---
+	  This improve shutter lag as resulf of reducing steam off delay.
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+config VIDEO_HD_SUPPORT
+	bool "Support HD of S5K5CCGX module"
+	depends on VIDEO_S5K5CCGX_COMMON
+	---help---
+	  This improve shutter lag as resulf of reducing steam off delay
+	  S5K5CCGX camera module is manufactured by Silliconfile coporate
+	  and it's maximum resolution is 2MP.
+
+#source "drivers/media/video/m5mols/Kconfig"
+
+choice
+depends on VIDEO_S5K4BA || VIDEO_S5K4EA || VIDEO_M5MO || VIDEO_M5MOLS
+prompt "Select ITU / MIPI Camera port"
+default ITU_A
+config ITU_A
+	bool "ITU Camera A port"
+	depends on !(VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS ||\
+			VIDEO_EXYNOS_MIPI_CSIS)
+	help
+	  This enables support for ITU A port
+config ITU_B
+	bool "ITU Camera B port"
+	depends on !(VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS ||\
+			VIDEO_EXYNOS_MIPI_CSIS)
+	help
+	  This enables support for ITU B port
+config CSI_C
+	bool "CSI Camera A port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS ||\
+			VIDEO_EXYNOS_MIPI_CSIS)
+	help
+	  This enables support for CSI A port
+config CSI_D
+	bool "CSI Camera B port"
+	depends on (VIDEO_FIMC_MIPI || VIDEO_S5P_MIPI_CSIS ||\
+			VIDEO_EXYNOS_MIPI_CSIS)
+	help
+	  This enables support for CSI B port
+endchoice
+
 comment "Video and audio decoders"
 
 config VIDEO_SAA717X
@@ -961,6 +1278,59 @@ config VIDEO_S5P_MIPI_CSIS
 	  To compile this driver as a module, choose M here: the
 	  module will be called s5p-csis.
 
+config SAMSUNG_MFC_DRIVERS
+	bool "Samsung EXYNOS MFC driver"
+	---help---
+	  This is a v4l2 driver for Samsung EXYNOS4/EXYNOS5 MFC.
+
+if SAMSUNG_MFC_DRIVERS
+
+choice
+	prompt "Select MFC driver type"
+	default USE_LEGACY_MFC
+config USE_LEGACY_MFC
+	bool "Legacy style MFC"
+	depends on VIDEO_SAMSUNG && ARCH_EXYNOS4
+	select VIDEO_MFC5X
+	---help---
+	  Use MFC legacy style driver.
+
+config USE_V4L2_MFC
+	bool "V4L2 style MFC"
+	depends on VIDEO_V4L2 && PLAT_S5P
+	select VIDEO_SAMSUNG_S5P_MFC
+	select VIDEO_FIXED_MINOR_RANGES
+	---help---
+	  Use MFC V4L2 style driver.
+
+endchoice
+
+config VIDEO_SAMSUNG_S5P_MFC
+	bool
+	depends on USE_V4L2_MFC
+	select VIDEOBUF2_CORE
+	---help---
+	  MFC driver for V4L2.
+
+choice
+	prompt "MFC V4L2 Driver"
+	default S5P_MFC_V5
+	depends on USE_V4L2_MFC
+	---help---
+	  Select version of MFC driver
+
+config S5P_MFC_V5
+	bool "MFC 5.x"
+	---help---
+	  Use MFC 5.x V4L2 Driver
+
+config S5P_MFC_V6
+	bool "MFC 6.x"
+	---help---
+	  Use MFC 6.x V4L2 Driver
+endchoice
+endif
+
 #
 # USB Multimedia device configuration
 #
@@ -1031,6 +1401,10 @@ config USB_S2255
 	  This driver can be compiled as a module, called s2255drv.
 
 endif # V4L_USB_DRIVERS
+
+source "drivers/media/video/samsung/Kconfig"
+source "drivers/media/video/exynos/Kconfig"
+
 endif # VIDEO_CAPTURE_DRIVERS
 
 menuconfig V4L_MEM2MEM_DRIVERS
@@ -1055,5 +1429,6 @@ config VIDEO_MEM2MEM_TESTDEV
 	  This is a virtual test device for the memory-to-memory driver
 	  framework.
 
-
 endif # V4L_MEM2MEM_DRIVERS
+
+source "drivers/media/video/mhl/Kconfig"
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index f0fecd6..805f5fd 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -67,9 +67,30 @@ obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
 obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
 obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o
 obj-$(CONFIG_VIDEO_MT9V032) += mt9v032.o
+ifeq ($(CONFIG_VIDEO_SAMSUNG_S5P_FIMC),y)
+obj-$(CONFIG_VIDEO_S5K4BA) += s5k4ba2.o
+obj-$(CONFIG_VIDEO_S5K4EA) += s5k4ea2.o
+endif
+ifeq ($(CONFIG_VIDEO_FIMC),y)
+obj-$(CONFIG_VIDEO_S5K4BA) += s5k4ba.o
+obj-$(CONFIG_VIDEO_S5K4EA) += s5k4ea.o
+endif
+obj-$(CONFIG_VIDEO_M5MO)	+= m5mo.o
+obj-$(CONFIG_VIDEO_M9MO)	+= m9mo.o
+ifeq ($(CONFIG_MACH_PX),y)
+obj-$(CONFIG_VIDEO_S5K5BAFX)	+= s5k5bafx-v2.o
+else
+obj-$(CONFIG_VIDEO_S5K5BAFX)	+= s5k5bafx.o
+endif
+obj-$(CONFIG_VIDEO_S5K5CCGX_COMMON) 	+= s5k5ccgx.o
+obj-$(CONFIG_VIDEO_SR200PC20)	+= sr200pc20-p2.o
+obj-$(CONFIG_VIDEO_SR200PC20M)		+= sr200pc20m.o
 obj-$(CONFIG_VIDEO_SR030PC30)	+= sr030pc30.o
 obj-$(CONFIG_VIDEO_NOON010PC30)	+= noon010pc30.o
 obj-$(CONFIG_VIDEO_M5MOLS)	+= m5mols/
+obj-$(CONFIG_VIDEO_S5C73M3)	+= s5c73m3.o
+obj-$(CONFIG_VIDEO_ISX012)	+= isx012.o
+obj-$(CONFIG_VIDEO_S5C73M3_SPI)	+= s5c73m3_spi.o
 
 obj-$(CONFIG_SOC_CAMERA_IMX074)		+= imx074.o
 obj-$(CONFIG_SOC_CAMERA_MT9M001)	+= mt9m001.o
@@ -111,6 +132,8 @@ obj-$(CONFIG_VIDEO_TIMBERDALE)	+= timblogiw.o
 obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o
 obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o
 obj-$(CONFIG_VIDEOBUF_DMA_CONTIG) += videobuf-dma-contig.o
+obj-$(CONFIG_VIDEOBUF2_CMA_PHYS) += videobuf2-cma-phys.o
+obj-$(CONFIG_VIDEOBUF2_ION) += videobuf2-ion.o
 obj-$(CONFIG_VIDEOBUF_VMALLOC) += videobuf-vmalloc.o
 obj-$(CONFIG_VIDEOBUF_DVB) += videobuf-dvb.o
 obj-$(CONFIG_VIDEO_BTCX)  += btcx-risc.o
@@ -168,12 +191,15 @@ obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
 obj-$(CONFIG_VIDEO_OMAP1)		+= omap1_camera.o
 
 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) 	+= s5p-fimc/
+obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC)	+= s5p-mfc/
+obj-$(CONFIG_VIDEO_EXYNOS)		+= exynos/
 
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
 
 obj-$(CONFIG_VIDEO_SH_VOU)		+= sh_vou.o
 
 obj-$(CONFIG_VIDEO_AU0828) += au0828/
+obj-$(CONFIG_VIDEO_SAMSUNG)	+= samsung/
 
 obj-$(CONFIG_USB_VIDEO_CLASS)	+= uvc/
 obj-$(CONFIG_VIDEO_SAA7164)     += saa7164/
@@ -187,3 +213,6 @@ obj-$(CONFIG_ARCH_OMAP)	+= omap/
 EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
 EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
 EXTRA_CFLAGS += -Idrivers/media/common/tuners
+
+obj-$(CONFIG_SAMSUNG_MHL)	+= mhl/
+
diff --git a/drivers/media/video/exynos/Kconfig b/drivers/media/video/exynos/Kconfig
new file mode 100644
index 0000000..6188124
--- /dev/null
+++ b/drivers/media/video/exynos/Kconfig
@@ -0,0 +1,51 @@
+#
+# Exynos multimedia device drivers
+#
+config VIDEO_EXYNOS
+	bool "Exynos Multimedia Devices"
+	depends on ARCH_EXYNOS4 || ARCH_EXYNOS5
+	default n
+	select VIDEO_FIXED_MINOR_RANGES
+	help
+	  This is a representative exynos multimedia device.
+
+if VIDEO_EXYNOS
+
+config VIDEO_EXYNOS_MEMSIZE_FIMC_IS
+	int "Memory size in Kbytes for FIMC-IS"
+	depends on VIDEO_EXYNOS
+	default "10240"
+	help
+	  This is to assign memory used in FIMC-IS.
+
+	source "drivers/media/video/exynos/mdev/Kconfig"
+	source "drivers/media/video/exynos/fimc-lite/Kconfig"
+	source "drivers/media/video/exynos/mipi-csis/Kconfig"
+	source "drivers/media/video/exynos/tv/Kconfig"
+	source "drivers/media/video/exynos/rotator/Kconfig"
+if ARCH_EXYNOS4
+	source "drivers/media/video/exynos/fimc-is/Kconfig"
+endif
+
+if ARCH_EXYNOS5
+	source "drivers/media/video/exynos/gsc/Kconfig"
+	source "drivers/media/video/exynos/fimc-is-mc/Kconfig"
+endif
+config VIDEO_EXYNOS_MEMSIZE_FIMC_IS
+	int "Memory size in Kbytes for FIMC-IS"
+	depends on VIDEO_EXYNOS && (VIDEO_EXYNOS_FIMC_IS || VIDEO_EXYNOS5_FIMC_IS)
+	default "10240"
+	help
+	  This is to assign memory used in FIMC-IS.
+config VIDEO_EXYNOS_MEMSIZE_FIMC_IS_ISP
+	int "Memory size in kbytes for FIMC-IS ISP(bayer)"
+	depends on VIDEO_EXYNOS_FIMC_IS_BAYER
+	default "61000"
+	help
+	  This is to assign memory used in FIMC-IS ISP.
+endif
+
+config MEDIA_EXYNOS
+	bool
+	help
+	  Compile mdev to use exynos5 media device driver.
diff --git a/drivers/media/video/exynos/Makefile b/drivers/media/video/exynos/Makefile
new file mode 100644
index 0000000..ad6401f
--- /dev/null
+++ b/drivers/media/video/exynos/Makefile
@@ -0,0 +1,10 @@
+obj-$(CONFIG_EXYNOS_MEDIA_DEVICE)	+= mdev/
+obj-$(CONFIG_VIDEO_EXYNOS_MIPI_CSIS)	+= mipi-csis/
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_LITE)	+= fimc-lite/
+obj-$(CONFIG_VIDEO_EXYNOS_GSCALER)	+= gsc/
+obj-$(CONFIG_VIDEO_EXYNOS)		+= fimc-is/
+obj-$(CONFIG_VIDEO_EXYNOS5_FIMC_IS)	+= fimc-is-mc/
+obj-$(CONFIG_VIDEO_EXYNOS_TV)		+= tv/
+obj-$(CONFIG_VIDEO_EXYNOS)		+= rotator/
+
+EXTRA_CLAGS += -Idrivers/media/video
diff --git a/drivers/media/video/exynos/fimc-is-mc/Kconfig b/drivers/media/video/exynos/fimc-is-mc/Kconfig
new file mode 100644
index 0000000..d675d87
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/Kconfig
@@ -0,0 +1,7 @@
+config VIDEO_EXYNOS5_FIMC_IS
+	bool "Exynos FIMC-IS (Image Subsystem) driver"
+	depends on VIDEO_EXYNOS && ARCH_EXYNOS5
+	select MEDIA_EXYNOS
+	default n
+	help
+	  This is a v4l2 driver for exynos FIMC-IS device.
\ No newline at end of file
diff --git a/drivers/media/video/exynos/fimc-is-mc/Makefile b/drivers/media/video/exynos/fimc-is-mc/Makefile
new file mode 100644
index 0000000..f2f135a
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_VIDEO_EXYNOS5_FIMC_IS)	+= fimc-is-core.o fimc-is-vb2.o fimc-is-helper.o fimc-is-misc.o fimc-is-video.o
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-cmd.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-cmd.h
new file mode 100644
index 0000000..2119334
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-cmd.h
@@ -0,0 +1,171 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CMD_H
+#define FIMC_IS_CMD_H
+
+#define IS_COMMAND_VER 107 /* IS COMMAND VERSION 1.07 */
+
+enum is_cmd {
+	/* HOST -> IS */
+	HIC_PREVIEW_STILL = 0x1,
+	HIC_PREVIEW_VIDEO,
+	HIC_CAPTURE_STILL,
+	HIC_CAPTURE_VIDEO,
+	HIC_STREAM_ON,
+	HIC_STREAM_OFF,
+	HIC_SHOT,
+	HIC_SET_PARAMETER,
+	HIC_GET_PARAMETER,
+	HIC_SET_TUNE,
+	RESERVED1,
+	HIC_GET_STATUS,
+	/* SENSOR PART*/
+	HIC_OPEN_SENSOR,
+	HIC_CLOSE_SENSOR,
+	HIC_SIMMIAN_INIT,
+	HIC_SIMMIAN_WRITE,
+	HIC_SIMMIAN_READ,
+	HIC_POWER_DOWN,
+	HIC_GET_SET_FILE_ADDR,
+	HIC_LOAD_SET_FILE,
+	HIC_MSG_CONFIG,
+	HIC_MSG_TEST,
+	/* IS -> HOST */
+	IHC_GET_SENSOR_NUMBER = 0x1000,
+	/* Parameter1 : Address of space to copy a setfile */
+	/* Parameter2 : Space szie */
+	IHC_SET_SHOT_MARK,
+	/* PARAM1 : a frame number */
+	/* PARAM2 : confidence level(smile 0~100) */
+	/* PARMA3 : confidence level(blink 0~100) */
+	IHC_SET_FACE_MARK,
+	/* PARAM1 : coordinate count */
+	/* PARAM2 : coordinate buffer address */
+	IHC_FRAME_DONE,
+	/* PARAM1 : frame start number */
+	/* PARAM2 : frame count */
+	IHC_AA_DONE,
+	IHC_NOT_READY
+};
+
+enum is_reply {
+	ISR_DONE	= 0x2000,
+	ISR_NDONE
+};
+
+enum is_scenario_id {
+	ISS_PREVIEW_STILL,
+	ISS_PREVIEW_VIDEO,
+	ISS_CAPTURE_STILL,
+	ISS_CAPTURE_VIDEO,
+	ISS_END
+};
+
+struct is_setfile_header_element {
+	u32 binary_addr;
+	u32 binary_size;
+};
+
+struct is_setfile_header {
+	struct is_setfile_header_element isp[ISS_END];
+	struct is_setfile_header_element drc[ISS_END];
+	struct is_setfile_header_element fd[ISS_END];
+};
+
+#define HOST_SET_INT_BIT	0x00000001
+#define HOST_CLR_INT_BIT	0x00000001
+#define IS_SET_INT_BIT		0x00000001
+#define IS_CLR_INT_BIT		0x00000001
+
+#define HOST_SET_INTERRUPT(base)	(base->uiINTGR0 |= HOST_SET_INT_BIT)
+#define HOST_CLR_INTERRUPT(base)	(base->uiINTCR0 |= HOST_CLR_INT_BIT)
+#define IS_SET_INTERRUPT(base)		(base->uiINTGR1 |= IS_SET_INT_BIT)
+#define IS_CLR_INTERRUPT(base)		(base->uiINTCR1 |= IS_CLR_INT_BIT)
+
+struct is_common_reg {
+	u32 hicmd;
+	u32 hic_sensorid;
+	u32 hic_param1;
+	u32 hic_param2;
+	u32 hic_param3;
+	u32 hic_param4;
+
+	u32 reserved1[4];
+
+	u32 ihcmd;
+	u32 ihc_sensorid;
+	u32 ihc_param1;
+	u32 ihc_param2;
+	u32 ihc_param3;
+	u32 ihc_param4;
+
+	u32 reserved2[4];
+
+	u32 isp_sensor_id;
+	u32 isp_param1;
+	u32 isp_param2;
+	u32 isp_param3;
+	u32 isp_param4;
+	u32 reserved3[3];
+
+	u32 scc_sensor_id;
+	u32 scc_param1;
+	u32 scc_param2;
+	u32 scc_param3;
+	u32 scc_param4;
+	u32 reserved4[3];
+
+	u32 dnr_sensor_id;
+	u32 dnr_param1;
+	u32 dnr_param2;
+	u32 dnr_param3;
+	u32 dnr_param4;
+	u32 reserved5[3];
+
+	u32 scp_sensor_id;
+	u32 scp_param1;
+	u32 scp_param2;
+	u32 scp_param3;
+	u32 scp_param4;
+	u32 reserved6[15];
+};
+
+struct is_mcuctl_reg {
+	u32 mcuctl;
+	u32 bboar;
+
+	u32 intgr0;
+	u32 intcr0;
+	u32 intmr0;
+	u32 intsr0;
+	u32 intmsr0;
+
+	u32 intgr1;
+	u32 intcr1;
+	u32 intmr1;
+	u32 intsr1;
+	u32 intmsr1;
+
+	u32 intcr2;
+	u32 intmr2;
+	u32 intsr2;
+	u32 intmsr2;
+
+	u32 gpoctrl;
+	u32 cpoenctlr;
+	u32 gpictlr;
+
+	u32 pad[0xD];
+
+	struct is_common_reg common_reg;
+};
+#endif
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.c b/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.c
new file mode 100644
index 0000000..ede4544
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.c
@@ -0,0 +1,1988 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * exynos5 fimc-is core functions
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <mach/videonode.h>
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+#include <mach/dev.h>
+#endif
+#include <media/exynos_mc.h>
+#include <linux/cma.h>
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/scatterlist.h>
+#include <linux/videodev2_exynos_camera.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-helper.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-err.h"
+#include "fimc-is-misc.h"
+
+extern struct class *camera_class;
+struct device *camera_front = NULL; /*sys/class/camera/rear*/
+struct device *camera_rear = NULL; /*sys/class/camera/front*/
+EXPORT_SYMBOL(camera_rear);
+
+#if defined(CONFIG_VIDEOBUF2_ION)
+static void *is_vb_cookie;
+void *buf_start;
+
+#endif
+
+static struct fimc_is_dev *to_fimc_is_dev_from_front_dev
+				(struct fimc_is_front_dev *front_dev)
+{
+	return container_of(front_dev, struct fimc_is_dev, front);
+}
+
+static struct fimc_is_sensor_dev *to_fimc_is_sensor_dev
+				(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct fimc_is_sensor_dev, sd);
+}
+
+static struct fimc_is_front_dev *to_fimc_is_front_dev(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct fimc_is_front_dev, sd);
+}
+
+static struct fimc_is_back_dev *to_fimc_is_back_dev(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct fimc_is_back_dev, sd);
+}
+
+static int fimc_is_sensor_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void fimc_is_mem_cache_clean(const void *start_addr,
+					unsigned long size)
+{
+	unsigned long paddr;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+	/*
+	 * virtual & phsical addrees mapped directly, so we can convert
+	 * the address just using offset
+	 */
+	paddr = __pa((unsigned long)start_addr);
+	outer_clean_range(paddr, paddr + size);
+}
+
+void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	paddr = __pa((unsigned long)start_addr);
+	outer_inv_range(paddr, paddr + size);
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+}
+
+int fimc_is_init_mem(struct fimc_is_dev *dev)
+{
+	struct cma_info mem_info;
+	char			cma_name[16];
+	int err;
+
+	dbg("fimc_is_init_mem - ION\n");
+	sprintf(cma_name, "%s%d", "fimc_is", 0);
+	err = cma_info(&mem_info, &dev->pdev->dev, 0);
+	dbg("%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		dev_err(&dev->pdev->dev, "%s: get cma info failed\n", __func__);
+		return -EINVAL;
+	}
+	dev->mem.size = FIMC_IS_A5_MEM_SIZE;
+	dev->mem.base = (dma_addr_t)cma_alloc
+		(&dev->pdev->dev, cma_name, (size_t)dev->mem.size, 0);
+	dev->is_p_region =
+		(struct is_region *)(phys_to_virt(dev->mem.base +
+				FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE));
+	memset((void *)dev->is_p_region, 0,
+		(unsigned long)sizeof(struct is_region));
+	fimc_is_mem_cache_clean((void *)dev->is_p_region,
+				FIMC_IS_REGION_SIZE+1);
+
+	dbg("ctrl->mem.size = 0x%x\n", dev->mem.size);
+	dbg("ctrl->mem.base = 0x%x\n", dev->mem.base);
+
+	return 0;
+}
+#elif defined(CONFIG_VIDEOBUF2_ION)
+
+void fimc_is_mem_init_mem_cleanup(void *alloc_ctxes)
+{
+	vb2_ion_destroy_context(alloc_ctxes);
+}
+
+void fimc_is_mem_resume(void *alloc_ctxes)
+{
+	vb2_ion_attach_iommu(alloc_ctxes);
+}
+
+void fimc_is_mem_suspend(void *alloc_ctxes)
+{
+	vb2_ion_detach_iommu(alloc_ctxes);
+}
+
+int fimc_is_cache_flush(struct fimc_is_dev *dev,
+				const void *start_addr, unsigned long size)
+{
+	vb2_ion_sync_for_device(dev->mem.fw_cookie,
+		(unsigned long)start_addr - (unsigned long)dev->mem.kvaddr,
+			size, DMA_BIDIRECTIONAL);
+	return 0;
+}
+
+/* Allocate firmware */
+int fimc_is_alloc_firmware(struct fimc_is_dev *dev)
+{
+	void *fimc_is_bitproc_buf;
+	int ret;
+
+	dbg("Allocating memory for FIMC-IS firmware.\n");
+
+	fimc_is_bitproc_buf = vb2_ion_private_alloc(dev->alloc_ctx,
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+				SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF +
+				SIZE_3DNR_INTERNAL_BUF * NUM_3DNR_INTERNAL_BUF +
+				SIZE_ISP_INTERNAL_BUF * NUM_ISP_INTERNAL_BUF);
+	if (IS_ERR(fimc_is_bitproc_buf)) {
+		fimc_is_bitproc_buf = 0;
+		err("Allocating bitprocessor buffer failed\n");
+		return -ENOMEM;
+	}
+
+	ret = vb2_ion_dma_address(fimc_is_bitproc_buf, &dev->mem.dvaddr);
+	if ((ret < 0) || (dev->mem.dvaddr  & FIMC_IS_FW_BASE_MASK)) {
+		err("The base memory is not aligned to 64MB.\n");
+		vb2_ion_private_free(fimc_is_bitproc_buf);
+		dev->mem.dvaddr = 0;
+		fimc_is_bitproc_buf = 0;
+		return -EIO;
+	}
+	dbg("Device vaddr = %08x , size = %08x\n",
+				dev->mem.dvaddr, FIMC_IS_A5_MEM_SIZE);
+
+	dev->mem.kvaddr = vb2_ion_private_vaddr(fimc_is_bitproc_buf);
+	if (IS_ERR(dev->mem.kvaddr)) {
+		err("Bitprocessor memory remap failed\n");
+		vb2_ion_private_free(fimc_is_bitproc_buf);
+		dev->mem.dvaddr = 0;
+		fimc_is_bitproc_buf = 0;
+		return -EIO;
+	}
+	dbg("Virtual address for FW: %08lx\n",
+			(long unsigned int)dev->mem.kvaddr);
+	dev->mem.bitproc_buf = fimc_is_bitproc_buf;
+	dev->mem.fw_cookie = fimc_is_bitproc_buf;
+
+	is_vb_cookie = dev->mem.fw_cookie;
+	buf_start = dev->mem.kvaddr;
+	return 0;
+}
+
+void fimc_is_mem_cache_clean(const void *start_addr,
+				unsigned long size)
+{
+	off_t offset;
+
+	if (start_addr < buf_start) {
+		err("Start address error\n");
+		return;
+	}
+	size--;
+
+	offset = start_addr - buf_start;
+
+	vb2_ion_sync_for_device(is_vb_cookie, offset, size, DMA_TO_DEVICE);
+}
+
+void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	off_t offset;
+
+	if (start_addr < buf_start) {
+		err("Start address error\n");
+		return;
+	}
+
+	offset = start_addr - buf_start;
+
+	vb2_ion_sync_for_device(is_vb_cookie, offset, size, DMA_FROM_DEVICE);
+}
+
+int fimc_is_init_mem(struct fimc_is_dev *dev)
+{
+	int ret;
+
+	dbg("fimc_is_init_mem - ION\n");
+	ret = fimc_is_alloc_firmware(dev);
+	if (ret) {
+		err("Couldn't alloc for FIMC-IS firmware\n");
+		return -EINVAL;
+	}
+
+	memset(dev->mem.kvaddr, 0,
+		FIMC_IS_A5_MEM_SIZE +
+		SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+		SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF +
+		SIZE_3DNR_INTERNAL_BUF * NUM_3DNR_INTERNAL_BUF +
+		SIZE_ISP_INTERNAL_BUF * NUM_ISP_INTERNAL_BUF);
+
+	dev->is_p_region =
+		(struct is_region *)(dev->mem.kvaddr +
+			FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE);
+
+
+	dev->is_shared_region =
+		(struct is_share_region *)(dev->mem.kvaddr +
+				FIMC_IS_SHARED_REGION_ADDR);
+
+	dev->mem.dvaddr_odc = (unsigned char *)(dev->mem.dvaddr +
+						FIMC_IS_A5_MEM_SIZE);
+	dev->mem.kvaddr_odc = dev->mem.kvaddr + FIMC_IS_A5_MEM_SIZE;
+
+	dev->mem.dvaddr_dis = (unsigned char *)
+				(dev->mem.dvaddr +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF);
+	dev->mem.kvaddr_dis = dev->mem.kvaddr  +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF;
+
+	dev->mem.dvaddr_3dnr = (unsigned char *)
+				(dev->mem.dvaddr +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+				SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF);
+	dev->mem.kvaddr_3dnr = dev->mem.kvaddr +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+				SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF;
+
+	dev->mem.dvaddr_isp = (unsigned char *)
+				(dev->mem.dvaddr +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+				SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF +
+				SIZE_3DNR_INTERNAL_BUF * NUM_3DNR_INTERNAL_BUF);
+	dev->mem.kvaddr_isp = dev->mem.kvaddr +
+				FIMC_IS_A5_MEM_SIZE +
+				SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF +
+				SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF +
+				SIZE_3DNR_INTERNAL_BUF * NUM_3DNR_INTERNAL_BUF;
+
+	dev->mem.dvaddr_shared = (unsigned char *)dev->mem.dvaddr +
+			((unsigned char *)&dev->is_p_region->shared[0] -
+			dev->mem.kvaddr);
+	dev->mem.kvaddr_shared = dev->mem.kvaddr +
+			((unsigned char *)&dev->is_p_region->shared[0] -
+			dev->mem.kvaddr);
+
+	if (fimc_is_cache_flush(dev, (void *)dev->is_p_region, IS_PARAM_SIZE)) {
+		err("fimc_is_cache_flush-Err\n");
+		return -EINVAL;
+	}
+	dbg("fimc_is_init_mem3\n");
+	return 0;
+}
+#endif
+
+static int fimc_is_request_firmware(struct fimc_is_dev *dev)
+{
+	int ret;
+	struct firmware *fw_blob;
+
+	ret = request_firmware((const struct firmware **)&fw_blob,
+				FIMC_IS_FW, &dev->pdev->dev);
+	if (ret) {
+		dev_err(&dev->pdev->dev,
+			"could not load firmware (err=%d)\n", ret);
+		return -EINVAL;
+	}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+		memcpy((void *)phys_to_virt(dev->mem.base),
+				fw_blob->data, fw_blob->size);
+		fimc_is_mem_cache_clean((void *)phys_to_virt(dev->mem.base),
+							fw_blob->size + 1);
+#elif defined(CONFIG_VIDEOBUF2_ION)
+		if (dev->mem.bitproc_buf == 0) {
+			err("failed to load FIMC-IS F/W\n");
+		} else {
+			memcpy(dev->mem.kvaddr, fw_blob->data, fw_blob->size);
+			fimc_is_mem_cache_clean(
+				(void *)dev->mem.kvaddr, fw_blob->size + 1);
+		}
+#endif
+
+	dbg("FIMC_IS F/W loaded successfully - size:%d\n",
+						fw_blob->size);
+	release_firmware(fw_blob);
+
+	return ret;
+}
+
+int fimc_is_load_fw(struct  fimc_is_dev *dev)
+{
+	int ret;
+
+	dbg("%s\n", __func__);
+	if (test_bit(IS_ST_IDLE, &dev->state)) {
+		/* 1. Load IS firmware */
+		ret = fimc_is_request_firmware(dev);
+		if (ret) {
+			err("failed to fimc_is_request_firmware (%d)\n", ret);
+			return -EINVAL;
+		}
+
+		set_bit(IS_ST_PWR_ON, &dev->state);
+
+		/* 3. A5 power on */
+		clear_bit(IS_ST_FW_DOWNLOADED, &dev->state);
+		fimc_is_hw_a5_power(dev, 1);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_FW_DOWNLOADED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			err("wait timeout A5 power on: %s\n", __func__);
+			return -EINVAL;
+		}
+		dbg("fimc_is_load_fw end\n");
+	} else {
+		dbg("IS FW was loaded before\n");
+	}
+	return 0;
+}
+
+static int fimc_is_load_setfile(struct fimc_is_dev *dev)
+{
+	int ret;
+	struct firmware *fw_blob;
+
+	ret = request_firmware((const struct firmware **)&fw_blob,
+				FIMC_IS_SETFILE, &dev->pdev->dev);
+	if (ret) {
+		dev_err(&dev->pdev->dev,
+			"could not load firmware (err=%d)\n", ret);
+		return -EINVAL;
+	}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	memcpy((void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+		fw_blob->data, fw_blob->size);
+	fimc_is_mem_cache_clean(
+		(void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+		fw_blob->size + 1);
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	if (dev->mem.bitproc_buf == 0) {
+		err("failed to load setfile\n");
+	} else {
+		memcpy((dev->mem.kvaddr + dev->setfile.base),
+					fw_blob->data, fw_blob->size);
+		fimc_is_mem_cache_clean(
+				(void *)(dev->mem.kvaddr + dev->setfile.base),
+				fw_blob->size + 1);
+	}
+#endif
+	dev->setfile.state = 1;
+	dbg("FIMC_IS setfile loaded successfully - size:%d\n",
+							fw_blob->size);
+	release_firmware(fw_blob);
+
+	dbg("A5 mem base  = 0x%08x\n", dev->mem.base);
+	dbg("Setfile base  = 0x%08x\n", dev->setfile.base);
+
+	return ret;
+}
+
+int fimc_is_init_set(struct fimc_is_dev *dev , u32 val)
+{
+	int ret;
+	struct flite_frame f_frame;
+#ifdef FIMC_IS_A5_DEBUG_ON
+	unsigned long debug_device = 0;
+#endif
+
+	fimc_is_hw_diable_wdt(dev);
+	dev->sensor.sensor_type = val;
+	dev->sensor.id_dual = 0;
+	dev->setfile.sub_index = 0;
+
+	dbg("fimc_is_init\n");
+	if (test_bit(IS_ST_FW_DOWNLOADED, &dev->state)) {
+		/* Init sequence 1: Open sensor */
+		dbg("v4l2 : open sensor : %d\n", val);
+
+		/* set mipi & fimclite */
+		f_frame.o_width =
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width + 16;
+		f_frame.o_height =
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height + 12;
+		f_frame.offs_h = 0;
+		f_frame.offs_v = 0;
+		f_frame.width =
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width + 16;
+		f_frame.height =
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height + 12;
+
+		/*start mipi & fimclite*/
+		dbg("start fimclite(pos:%d) (port:%d)\n",
+		dev->sensor.id_position,
+		dev->pdata->sensor_info[dev->sensor.id_position]->flite_id);
+
+		start_fimc_lite(dev->pdata->
+				sensor_info[dev->sensor.id_position]->
+				flite_id, &f_frame);
+		mdelay(10);
+		dbg("start mipi (pos:%d) (port:%d)\n",
+			dev->sensor.id_position,
+			dev->pdata->
+			sensor_info[dev->sensor.id_position]->csi_id);
+		start_mipi_csi(dev->pdata->
+				sensor_info[dev->sensor.id_position]->
+				csi_id, &f_frame);
+
+		clear_bit(IS_ST_OPEN_SENSOR, &dev->state);
+		fimc_is_hw_open_sensor(dev, dev->sensor.id_dual, val);
+
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_OPEN_SENSOR, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		if (dev->is_p_region->shared[MAX_SHARED_COUNT-1]
+							!= MAGIC_NUMBER)
+			dev_err(&dev->pdev->dev, "MAGIC NUMBER error\n");
+
+		dbg("v4l2 : setfile address\n");
+		fimc_is_hw_get_setfile_addr(dev);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_SETFILE_LOADED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			err("wait timeout - get setfile address\n");
+			/*fimc_is_hw_set_low_poweroff(dev, true);*/
+			return -EINVAL;
+		}
+
+		fimc_is_load_setfile(dev);
+		dbg(" fimc_is_load_setfile end\n");
+		clear_bit(IS_ST_SETFILE_LOADED, &dev->state);
+
+		fimc_is_hw_load_setfile(dev);
+
+		ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_SETFILE_LOADED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			err("wait timeout - get setfile address\n");
+			/*fimc_is_hw_set_low_poweroff(dev, true);*/
+			return -EINVAL;
+		}
+
+		dbg("v4l2 : Load set file end\n");
+		/* Debug only */
+		dbg("Parameter region addr = 0x%08x\n",
+			(unsigned int)(dev->is_p_region));
+		dev->frame_count = 0;
+
+		dbg("Stream Off\n");
+		clear_bit(IS_ST_STREAM_OFF, &dev->state);
+		fimc_is_hw_set_stream(dev, 0); /*stream off */
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_RUN, &dev->state);
+
+		/* 1. */
+		dbg("Default setting : preview_still\n");
+		dev->scenario_id = ISS_PREVIEW_STILL;
+		fimc_is_hw_set_init(dev);
+		fimc_is_hw_change_size(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+
+		/* 1 */
+		set_bit(IS_ST_INIT_PREVIEW_STILL, &dev->state);
+		fimc_is_hw_set_param(dev);
+
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+#ifdef FIMC_IS_A5_DEBUG_ON
+		/*set_bit(FIMC_IS_DEBUG_MAIN, &debug_device);
+		set_bit(FIMC_IS_DEBUG_EC, &debug_device);
+		set_bit(FIMC_IS_DEBUG_SENSOR, &debug_device);
+		set_bit(FIMC_IS_DEBUG_ISP, &debug_device);
+		set_bit(FIMC_IS_DEBUG_DRC, &debug_device);
+		set_bit(FIMC_IS_DEBUG_FD, &debug_device);
+		set_bit(FIMC_IS_DEBUG_SDK, &debug_device);
+		set_bit(FIMC_IS_DEBUG_SCALERC, &debug_device);
+		set_bit(FIMC_IS_DEBUG_ODC, &debug_device);
+		set_bit(FIMC_IS_DEBUG_TDNR, &debug_device);
+		set_bit(FIMC_IS_DEBUG_SCALERP, &debug_device);
+		set_bit(FIMC_IS_DEBUG_DIS, &debug_device);
+		*/
+
+		fimc_is_hw_set_debug_level(dev, FIMC_IS_DEBUG_UART,
+					debug_device, FIMC_IS_DEBUG_LEVEL);
+#endif
+		clear_bit(IS_ST_STREAM_OFF, &dev->state);
+		set_bit(IS_ST_RUN, &dev->state);
+
+		dbg("Init sequence completed!! Ready to use\n");
+	}
+
+	return 0;
+}
+
+static int fimc_is_front_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct fimc_is_front_dev *front_dev = to_fimc_is_front_dev(sd);
+	struct fimc_is_dev *isp = to_fimc_is_dev_from_front_dev(front_dev);
+	int ret;
+
+	if (enable) {
+		printk(KERN_INFO "fimc_is_front_s_stream : ON\n");
+	} else {
+		printk(KERN_INFO "fimc_is_front_s_stream : OFF\n");
+		fimc_is_hw_subip_poweroff(isp);
+		ret = wait_event_timeout(isp->irq_queue,
+			!test_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		fimc_is_hw_a5_power(isp, 0);
+		isp->state = 0;
+		isp->pipe_state = 0;
+		stop_mipi_csi(isp->pdata->sensor_info[0]->csi_id);
+		stop_mipi_csi(isp->pdata->sensor_info[1]->csi_id);
+		stop_fimc_lite(isp->pdata->sensor_info[0]->flite_id);
+		stop_fimc_lite(isp->pdata->sensor_info[1]->flite_id);
+
+		if (isp->pdata->clk_off) {
+			/* isp->pdata->clk_off(isp->pdev); */
+		} else {
+			err("#### failed to Clock On ####\n");
+			return -EINVAL;
+		}
+		set_bit(IS_ST_IDLE , &isp->state);
+		dbg("state(%d), pipe_state(%d)\n",
+			(int)isp->state, (int)isp->pipe_state);
+	}
+
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_get_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_set_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_get_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_set_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_get_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_set_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_get_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_set_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_get_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_set_fmt(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_format *fmt)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_get_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_set_crop(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh,
+					struct v4l2_subdev_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_s_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_g_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_s_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_g_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+static int fimc_is_back_s_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_g_ctrl(struct v4l2_subdev *sd,
+				struct v4l2_control *ctrl)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static struct v4l2_subdev_pad_ops fimc_is_sensor_pad_ops = {
+	.get_fmt	= fimc_is_sensor_subdev_get_fmt,
+	.set_fmt	= fimc_is_sensor_subdev_set_fmt,
+	.get_crop	= fimc_is_sensor_subdev_get_crop,
+	.set_crop	= fimc_is_sensor_subdev_set_crop,
+};
+
+static struct v4l2_subdev_pad_ops fimc_is_front_pad_ops = {
+	.get_fmt	= fimc_is_front_subdev_get_fmt,
+	.set_fmt	= fimc_is_front_subdev_set_fmt,
+	.get_crop	= fimc_is_front_subdev_get_crop,
+	.set_crop	= fimc_is_front_subdev_set_crop,
+};
+
+static struct v4l2_subdev_pad_ops fimc_is_back_pad_ops = {
+	.get_fmt	= fimc_is_back_subdev_get_fmt,
+	.set_fmt	= fimc_is_back_subdev_set_fmt,
+	.get_crop	= fimc_is_back_subdev_get_crop,
+	.set_crop	= fimc_is_back_subdev_set_crop,
+};
+
+static struct v4l2_subdev_video_ops fimc_is_sensor_video_ops = {
+	.s_stream	= fimc_is_sensor_s_stream,
+};
+
+static struct v4l2_subdev_video_ops fimc_is_front_video_ops = {
+	.s_stream	= fimc_is_front_s_stream,
+};
+
+static struct v4l2_subdev_video_ops fimc_is_back_video_ops = {
+	.s_stream	= fimc_is_back_s_stream,
+};
+
+static struct v4l2_subdev_core_ops fimc_is_sensor_core_ops = {
+	.s_ctrl	= fimc_is_sensor_s_ctrl,
+	.g_ctrl = fimc_is_sensor_g_ctrl,
+};
+
+static struct v4l2_subdev_core_ops fimc_is_front_core_ops = {
+	.s_ctrl	= fimc_is_front_s_ctrl,
+	.g_ctrl = fimc_is_front_g_ctrl,
+};
+
+static struct v4l2_subdev_core_ops fimc_is_back_core_ops = {
+	.s_ctrl	= fimc_is_back_s_ctrl,
+	.g_ctrl = fimc_is_back_g_ctrl,
+};
+
+static struct v4l2_subdev_ops fimc_is_sensor_subdev_ops = {
+	.pad	= &fimc_is_sensor_pad_ops,
+	.video	= &fimc_is_sensor_video_ops,
+	.core	= &fimc_is_sensor_core_ops,
+};
+
+static struct v4l2_subdev_ops fimc_is_front_subdev_ops = {
+	.pad	= &fimc_is_front_pad_ops,
+	.video	= &fimc_is_front_video_ops,
+	.core	= &fimc_is_front_core_ops,
+};
+
+static struct v4l2_subdev_ops fimc_is_back_subdev_ops = {
+	.pad	= &fimc_is_back_pad_ops,
+	.video	= &fimc_is_back_video_ops,
+	.core	= &fimc_is_back_core_ops,
+};
+
+static int fimc_is_sensor_init_formats(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_close(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_sensor_subdev_registered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static void fimc_is_sensor_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_front_init_formats(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_close(struct v4l2_subdev *sd,
+					 struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_subdev_registered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static void fimc_is_front_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_back_init_formats(struct v4l2_subdev *sd,
+					 struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_close(struct v4l2_subdev *sd,
+					struct v4l2_subdev_fh *fh)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_subdev_registered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static void fimc_is_back_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	dbg("%s\n", __func__);
+}
+
+static const struct v4l2_subdev_internal_ops
+			fimc_is_sensor_v4l2_internal_ops = {
+	.open = fimc_is_sensor_init_formats,
+	.close = fimc_is_sensor_subdev_close,
+	.registered = fimc_is_sensor_subdev_registered,
+	.unregistered = fimc_is_sensor_subdev_unregistered,
+};
+
+static const struct v4l2_subdev_internal_ops fimc_is_front_v4l2_internal_ops = {
+	.open = fimc_is_front_init_formats,
+	.close = fimc_is_front_subdev_close,
+	.registered = fimc_is_front_subdev_registered,
+	.unregistered = fimc_is_front_subdev_unregistered,
+};
+
+static const struct v4l2_subdev_internal_ops fimc_is_back_v4l2_internal_ops = {
+	.open = fimc_is_back_init_formats,
+	.close = fimc_is_back_subdev_close,
+	.registered = fimc_is_back_subdev_registered,
+	.unregistered = fimc_is_back_subdev_unregistered,
+};
+
+static int fimc_is_sensor_link_setup(struct media_entity *entity,
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct fimc_is_sensor_dev *fimc_is_sensor = to_fimc_is_sensor_dev(sd);
+
+	dbg("++%s\n", __func__);
+	dbg("local->index : %d\n", local->index);
+	dbg("media_entity_type(remote->entity) : %d\n",
+				media_entity_type(remote->entity));
+
+	switch (local->index | media_entity_type(remote->entity)) {
+	case FIMC_IS_SENSOR_PAD_SOURCE_FRONT | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_sensor->output = FIMC_IS_SENSOR_OUTPUT_FRONT;
+		else
+			fimc_is_sensor->output = FIMC_IS_SENSOR_OUTPUT_NONE;
+		break;
+
+	default:
+		v4l2_err(sd, "%s : ERR link\n", __func__);
+		return -EINVAL;
+	}
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_front_link_setup(struct media_entity *entity,
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct fimc_is_front_dev *fimc_is_front = to_fimc_is_front_dev(sd);
+
+	dbg("++%s\n", __func__);
+	dbg("local->index : %d\n", local->index);
+
+	switch (local->index | media_entity_type(remote->entity)) {
+	case FIMC_IS_FRONT_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
+		dbg("fimc_is_front sink pad\n");
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			if (fimc_is_front->input
+				!= FIMC_IS_FRONT_INPUT_NONE) {
+				dbg("BUSY\n");
+				return -EBUSY;
+			}
+			if (remote->index == FIMC_IS_SENSOR_PAD_SOURCE_FRONT)
+				fimc_is_front->input
+					= FIMC_IS_FRONT_INPUT_SENSOR;
+		} else {
+			fimc_is_front->input = FIMC_IS_FRONT_INPUT_NONE;
+		}
+		break;
+
+	case FIMC_IS_FRONT_PAD_SOURCE_BACK | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_front->output |= FIMC_IS_FRONT_OUTPUT_BACK;
+		else
+			fimc_is_front->output = FIMC_IS_FRONT_OUTPUT_NONE;
+		break;
+
+	case FIMC_IS_FRONT_PAD_SOURCE_BAYER | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_front->output |= FIMC_IS_FRONT_OUTPUT_BAYER;
+		else
+			fimc_is_front->output = FIMC_IS_FRONT_OUTPUT_NONE;
+		break;
+	case FIMC_IS_FRONT_PAD_SOURCE_SCALERC | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_front->output |= FIMC_IS_FRONT_OUTPUT_SCALERC;
+		else
+			fimc_is_front->output = FIMC_IS_FRONT_OUTPUT_NONE;
+		break;
+
+	default:
+		v4l2_err(sd, "%s : ERR link\n", __func__);
+		return -EINVAL;
+	}
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_back_link_setup(struct media_entity *entity,
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct fimc_is_back_dev *fimc_is_back = to_fimc_is_back_dev(sd);
+
+	dbg("++%s\n", __func__);
+	switch (local->index | media_entity_type(remote->entity)) {
+	case FIMC_IS_BACK_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
+		dbg("fimc_is_back sink pad\n");
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			if (fimc_is_back->input != FIMC_IS_BACK_INPUT_NONE) {
+				dbg("BUSY\n");
+				return -EBUSY;
+			}
+			if (remote->index == FIMC_IS_FRONT_PAD_SOURCE_BACK)
+				fimc_is_back->input = FIMC_IS_BACK_INPUT_FRONT;
+		} else {
+			fimc_is_back->input = FIMC_IS_FRONT_INPUT_NONE;
+		}
+		break;
+	case FIMC_IS_BACK_PAD_SOURCE_3DNR | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_back->output |= FIMC_IS_BACK_OUTPUT_3DNR;
+		else
+			fimc_is_back->output = FIMC_IS_FRONT_OUTPUT_NONE;
+		break;
+	case FIMC_IS_BACK_PAD_SOURCE_SCALERP | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			fimc_is_back->output |= FIMC_IS_BACK_OUTPUT_SCALERP;
+		else
+			fimc_is_back->output = FIMC_IS_FRONT_OUTPUT_NONE;
+		break;
+	default:
+		v4l2_err(sd, "%s : ERR link\n", __func__);
+		return -EINVAL;
+	}
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+static const struct media_entity_operations fimc_is_sensor_media_ops = {
+	.link_setup = fimc_is_sensor_link_setup,
+};
+
+static const struct media_entity_operations fimc_is_front_media_ops = {
+	.link_setup = fimc_is_front_link_setup,
+};
+
+static const struct media_entity_operations fimc_is_back_media_ops = {
+	.link_setup = fimc_is_back_link_setup,
+};
+
+int fimc_is_pipeline_s_stream_preview(struct media_entity *start_entity, int on)
+{
+	struct media_pad *pad = &start_entity->pads[0];
+	struct v4l2_subdev *back_sd;
+	struct v4l2_subdev *front_sd;
+	struct v4l2_subdev *sensor_sd;
+	int	ret;
+
+	dbg("--%s\n", __func__);
+
+	pad = media_entity_remote_source(pad);
+	if (media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV
+			|| pad == NULL)
+		dbg("cannot find back entity\n");
+
+	back_sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	pad = &pad->entity->pads[0];
+
+	pad = media_entity_remote_source(pad);
+	if (media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV
+			|| pad == NULL)
+		dbg("cannot find front entity\n");
+
+	front_sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	pad = &pad->entity->pads[0];
+
+	pad = media_entity_remote_source(pad);
+	if (media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV
+			|| pad == NULL)
+		dbg("cannot find sensor entity\n");
+
+	sensor_sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	if (on) {
+
+		ret = v4l2_subdev_call(sensor_sd, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+
+		ret = v4l2_subdev_call(front_sd, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+
+		ret = v4l2_subdev_call(back_sd, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+
+	} else {
+		ret = v4l2_subdev_call(back_sd, video, s_stream, 0);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(front_sd, video, s_stream, 0);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(sensor_sd, video, s_stream, 0);
+	}
+
+	return ret == -ENOIOCTLCMD ? 0 : ret;
+}
+
+
+static int fimc_is_suspend(struct device *dev)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_resume(struct device *dev)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct fimc_is_dev *isp
+		= (struct fimc_is_dev *)platform_get_drvdata(pdev);
+
+	return fimc_is_hw_a5_power_off(isp);
+}
+
+static int fimc_is_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct fimc_is_dev *isp
+		= (struct fimc_is_dev *)platform_get_drvdata(pdev);
+
+	return fimc_is_hw_a5_power_on(isp);
+}
+
+static int fimc_is_get_md_callback(struct device *dev, void *p)
+{
+	struct exynos_md **md_list = p;
+	struct exynos_md *md = NULL;
+
+	md = dev_get_drvdata(dev);
+
+	if (md)
+		*(md_list + md->id) = md;
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct exynos_md *fimc_is_get_md(enum mdev_node node)
+{
+	struct device_driver *drv;
+	struct exynos_md *md[MDEV_MAX_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(MDEV_MODULE_NAME, &platform_bus_type);
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &md[0],
+				     fimc_is_get_md_callback);
+	put_driver(drv);
+
+	return ret ? NULL : md[node];
+
+}
+
+static unsigned int fimc_is_get_intr_position(unsigned int intr_status)
+{
+	int i;
+
+	for (i = 0; i < 5; i++)
+		if (intr_status & (1<<i))
+			return i;
+
+	return 0;
+}
+
+static irqreturn_t fimc_is_irq_handler(int irq, void *dev_id)
+{
+	struct fimc_is_dev *dev = dev_id;
+	int buf_index;
+	unsigned int intr_status, intr_pos;
+
+	intr_status = readl(dev->regs + INTSR1);
+	intr_pos = fimc_is_get_intr_position(intr_status);
+
+	if (intr_pos == INTR_GENERAL) {
+		dev->i2h_cmd.cmd = readl(dev->regs + ISSR10);
+
+		/* Read ISSR10 ~ ISSR15 */
+		switch (dev->i2h_cmd.cmd) {
+		case IHC_GET_SENSOR_NUMBER:
+			dbg("IHC_GET_SENSOR_NUMBER\n");
+			fimc_is_hw_get_param(dev, 1);
+			dbg("ISP - FW version - %d\n", dev->i2h_cmd.arg[0]);
+			dev->fw.ver = dev->i2h_cmd.arg[0];
+			fimc_is_hw_wait_intmsr0_intmsd0(dev);
+			fimc_is_hw_set_sensor_num(dev);
+			break;
+		case IHC_SET_SHOT_MARK:
+			fimc_is_hw_get_param(dev, 3);
+			break;
+		case IHC_SET_FACE_MARK:
+			fimc_is_hw_get_param(dev, 2);
+			break;
+		case IHC_NOT_READY:
+			break;
+		case IHC_AA_DONE:
+			fimc_is_hw_get_param(dev, 3);
+			break;
+		case ISR_DONE:
+			fimc_is_hw_get_param(dev, 3);
+			break;
+		case ISR_NDONE:
+			fimc_is_hw_get_param(dev, 4);
+
+			/* fimc_is_fw_clear_insr1(dev); */
+			break;
+		}
+		/* Just clear the interrupt pending bits. */
+		fimc_is_fw_clear_irq1(dev, intr_pos);
+
+		switch (dev->i2h_cmd.cmd) {
+		case IHC_GET_SENSOR_NUMBER:
+			fimc_is_hw_set_intgr0_gd0(dev);
+			set_bit(IS_ST_FW_DOWNLOADED, &dev->state);
+			break;
+		case IHC_SET_SHOT_MARK:
+			break;
+		case IHC_SET_FACE_MARK:
+			dbg("IHC_SET_FACE_MARK - %d, %d\n",
+					dev->i2h_cmd.arg[0],
+			dev->i2h_cmd.arg[1]);
+			dev->fd_header.count = dev->i2h_cmd.arg[0];
+			dev->fd_header.index = dev->i2h_cmd.arg[1];
+			/* Implementation of AF with face */
+			if (dev->af.mode == IS_FOCUS_MODE_CONTINUOUS &&
+					dev->af.af_state == FIMC_IS_AF_LOCK) {
+				fimc_is_af_face(dev);
+			} else if (dev->af.mode == IS_FOCUS_MODE_FACEDETECT) {
+				/* Using face information once only */
+				fimc_is_af_face(dev);
+				dev->af.mode = IS_FOCUS_MODE_IDLE;
+			}
+			break;
+		case IHC_AA_DONE:
+			switch (dev->i2h_cmd.arg[0]) {
+			/* SEARCH: Occurs when search is
+			 * requested at continuous AF */
+			case 2:
+				break;
+			/* INFOCUS: Occurs when focus is found. */
+			case 3:
+				if (dev->af.af_state == FIMC_IS_AF_RUNNING)
+					dev->af.af_state = FIMC_IS_AF_LOCK;
+				dev->af.af_lock_state = 0x2;
+				break;
+			/* OUTOFFOCUS: Occurs when focus is not found. */
+			case 4:
+				if (dev->af.af_state == FIMC_IS_AF_RUNNING)
+					dev->af.af_state = FIMC_IS_AF_LOCK;
+				dev->af.af_lock_state = 0x1;
+				break;
+			}
+			break;
+		case IHC_NOT_READY:
+			err("Init Sequnce Error- IS will be turned off!!");
+			break;
+		case ISR_DONE:
+			dbg("ISR_DONE - %d\n", dev->i2h_cmd.arg[0]);
+			switch (dev->i2h_cmd.arg[0]) {
+			case HIC_PREVIEW_STILL:
+			case HIC_PREVIEW_VIDEO:
+			case HIC_CAPTURE_STILL:
+			case HIC_CAPTURE_VIDEO:
+				if (test_and_clear_bit(IS_ST_CHANGE_MODE,
+					&dev->state)) {
+					dev->sensor.offset_x
+						= dev->i2h_cmd.arg[1];
+					dev->sensor.offset_y
+						= dev->i2h_cmd.arg[2];
+					set_bit(IS_ST_CHANGE_MODE_DONE,
+						&dev->state);
+				}
+				break;
+			case HIC_STREAM_ON:
+				clear_bit(IS_ST_CHANGE_MODE_DONE, &dev->state);
+				set_bit(IS_ST_STREAM_ON, &dev->state);
+				break;
+			case HIC_STREAM_OFF:
+				set_bit(IS_ST_STREAM_OFF, &dev->state);
+				set_bit(IS_ST_RUN, &dev->state);
+				break;
+			case HIC_SET_PARAMETER:
+				dev->p_region_index1 = 0;
+				dev->p_region_index2 = 0;
+				atomic_set(&dev->p_region_num, 0);
+
+				/* FW bug - should be removed*/
+				if (dev->i2h_cmd.arg[1] == 0 &&
+					dev->i2h_cmd.arg[2] == 0)
+					break;
+
+				set_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+
+				if (test_bit(PARAM_ISP_AA,
+					(void *)&dev->i2h_cmd.arg[1]) &&
+					(dev->af.af_state
+					== FIMC_IS_AF_SETCONFIG)) {
+					dev->af.af_state = FIMC_IS_AF_RUNNING;
+				} else if (test_bit(PARAM_ISP_AA,
+					(void *)&dev->i2h_cmd.arg[1]) &&
+					dev->af.af_state == FIMC_IS_AF_ABORT) {
+					dev->af.af_state = FIMC_IS_AF_IDLE;
+				}
+
+				if (test_bit(IS_ST_INIT_PREVIEW_STILL,
+					&dev->state))
+					set_bit(IS_ST_INIT_PREVIEW_VIDEO,
+						&dev->state);
+				else {
+					clear_bit(IS_ST_SET_PARAM, &dev->state);
+					set_bit(IS_ST_RUN, &dev->state);
+				}
+				break;
+
+			case HIC_GET_PARAMETER:
+				break;
+			case HIC_SET_TUNE:
+				break;
+			case HIC_GET_STATUS:
+				break;
+			case HIC_OPEN_SENSOR:
+				set_bit(IS_ST_OPEN_SENSOR, &dev->state);
+				dbg("reply HIC_OPEN_SENSOR");
+				break;
+			case HIC_CLOSE_SENSOR:
+				clear_bit(IS_ST_OPEN_SENSOR, &dev->state);
+				dev->sensor.id_dual = 0;
+				break;
+			case HIC_POWER_DOWN:
+				clear_bit(FIMC_IS_PWR_ST_POWER_ON_OFF,
+								&dev->power);
+				break;
+			case HIC_GET_SET_FILE_ADDR:
+				dev->setfile.base = dev->i2h_cmd.arg[1];
+				set_bit(IS_ST_SETFILE_LOADED, &dev->state);
+				break;
+			case HIC_LOAD_SET_FILE:
+				set_bit(IS_ST_SETFILE_LOADED, &dev->state);
+			}
+			break;
+		case ISR_NDONE:
+			err("ISR_NDONE - %d: %d\n", dev->i2h_cmd.arg[0],
+				dev->i2h_cmd.arg[1]);
+
+			switch (dev->i2h_cmd.arg[1]) {
+			case IS_ERROR_SET_PARAMETER:
+				fimc_is_mem_cache_inv((void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				break;
+			}
+
+			break;
+		}
+	} else if (intr_pos == INTR_FRAME_DONE_ISP) {
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR20);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR21);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR22);
+		fimc_is_fw_clear_irq1(dev, intr_pos);
+
+		buf_index =  dev->i2h_cmd.arg[2];
+		dbg("Bayer returned buf index : %d\n", buf_index);
+		vb2_buffer_done(dev->video[FIMC_IS_VIDEO_NUM_BAYER].
+				vbq.bufs[buf_index], VB2_BUF_STATE_DONE);
+		fimc_is_hw_update_bufmask(dev, FIMC_IS_VIDEO_NUM_BAYER);
+	} else if (intr_pos == INTR_FRAME_DONE_SCALERC) {
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR28);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR29);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR30);
+		fimc_is_fw_clear_irq1(dev, intr_pos);
+
+		buf_index =  dev->i2h_cmd.arg[2];
+		dbg("ScalerC returned buf index : %d\n", buf_index);
+		vb2_buffer_done(dev->video[FIMC_IS_VIDEO_NUM_SCALERC].
+				vbq.bufs[buf_index], VB2_BUF_STATE_DONE);
+		fimc_is_hw_update_bufmask(dev, FIMC_IS_VIDEO_NUM_SCALERC);
+	} else if (intr_pos == INTR_FRAME_DONE_TDNR) {
+
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR36);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR37);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR38);
+		fimc_is_fw_clear_irq1(dev, intr_pos);
+
+		buf_index =  dev->i2h_cmd.arg[2];
+		dbg("3DNR returned buf index : %d\n", buf_index);
+		vb2_buffer_done(dev->video[FIMC_IS_VIDEO_NUM_3DNR].
+				vbq.bufs[buf_index], VB2_BUF_STATE_DONE);
+		fimc_is_hw_update_bufmask(dev, FIMC_IS_VIDEO_NUM_3DNR);
+	} else if (intr_pos == INTR_FRAME_DONE_SCALERP) {
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR44);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR45);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR46);
+		fimc_is_fw_clear_irq1(dev, intr_pos);
+
+#ifdef DZOOM_EVT0
+		set_bit(IS_ST_SCALERP_FRAME_DONE, &dev->state);
+#endif
+		buf_index =  dev->i2h_cmd.arg[2];
+		dbg("ScalerP returned buf index : %d\n", buf_index);
+		vb2_buffer_done(dev->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				vbq.bufs[buf_index], VB2_BUF_STATE_DONE);
+		fimc_is_hw_update_bufmask(dev, FIMC_IS_VIDEO_NUM_SCALERP);
+	}
+	wake_up(&dev->irq_queue);
+
+	return IRQ_HANDLED;
+}
+
+static ssize_t s5k4e5_camera_rear_camtype_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "SLSI_S5K4E5_FIMC_IS";
+
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t s5k4e5_camera_rear_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "S5K4E5";
+	return sprintf(buf, "%s %s\n", type, type);
+
+}
+
+static ssize_t s5k6a3_camera_front_camtype_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "SLSI_S5K6A3_FIMC_IS";
+
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t s5k6a3_camera_front_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "S5K6A3";
+	return sprintf(buf, "%s %s\n", type, type);
+
+}
+
+static DEVICE_ATTR(rear_camtype, S_IWUSR|S_IWGRP|S_IROTH,
+		s5k4e5_camera_rear_camtype_show, NULL);
+static DEVICE_ATTR(rear_camfw, S_IWUSR|S_IWGRP|S_IROTH, s5k4e5_camera_rear_camfw_show, NULL);
+
+static DEVICE_ATTR(front_camtype, S_IWUSR|S_IWGRP|S_IROTH,
+		s5k6a3_camera_front_camtype_show, NULL);
+static DEVICE_ATTR(front_camfw, S_IWUSR|S_IWGRP|S_IROTH, s5k6a3_camera_front_camfw_show, NULL);
+
+static int fimc_is_probe(struct platform_device *pdev)
+{
+	struct resource *mem_res;
+	struct resource *regs_res;
+	struct fimc_is_dev *isp;
+	int ret = -ENODEV;
+	struct vb2_queue *scalerc_q;
+	struct vb2_queue *scalerp_q;
+	struct vb2_queue *dnr_q;
+	struct vb2_queue *bayer_q;
+
+	dbg("fimc_is_front_probe\n");
+
+	isp = kzalloc(sizeof(struct fimc_is_dev), GFP_KERNEL);
+	if (!isp)
+		return -ENOMEM;
+
+	isp->pdev = pdev;
+	isp->pdata = pdev->dev.platform_data;
+	isp->id = pdev->id;
+	isp->pipe_state = 0;
+
+	set_bit(FIMC_IS_STATE_IDLE, &isp->pipe_state);
+	set_bit(IS_ST_IDLE , &isp->state);
+
+	init_waitqueue_head(&isp->irq_queue);
+	spin_lock_init(&isp->slock);
+	mutex_init(&isp->vb_lock);
+	mutex_init(&isp->lock);
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "Failed to get io memory region\n");
+		goto p_err1;
+	}
+
+	regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
+				      pdev->name);
+	if (!regs_res) {
+		dev_err(&pdev->dev, "Failed to request io memory region\n");
+		goto p_err1;
+	}
+
+	isp->regs_res = regs_res;
+	isp->regs = ioremap(mem_res->start, resource_size(mem_res));
+	if (!isp->regs) {
+		dev_err(&pdev->dev, "Failed to remap io region\n");
+		goto p_err2;
+	}
+
+	isp->mdev = fimc_is_get_md(MDEV_ISP);
+	if (IS_ERR_OR_NULL(isp->mdev))
+		goto p_err3;
+
+	dbg("fimc_is_front->mdev : 0x%p\n", isp->mdev);
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	isp->vb2 = &fimc_is_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	isp->vb2 = &fimc_is_vb2_ion;
+#endif
+
+	isp->irq = platform_get_irq(pdev, 0);
+	if (isp->irq < 0) {
+		dev_err(&pdev->dev, "Failed to get irq\n");
+		goto p_err3;
+	}
+
+	ret = request_irq(isp->irq, fimc_is_irq_handler,
+				0, dev_name(&pdev->dev), isp);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq failed\n");
+		goto p_err3;
+	}
+
+	/*sensor entity*/
+	v4l2_subdev_init(&isp->sensor.sd, &fimc_is_sensor_subdev_ops);
+	isp->sensor.sd.owner = THIS_MODULE;
+	isp->sensor.sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(isp->sensor.sd.name, sizeof(isp->sensor.sd.name), "%s\n",
+					FIMC_IS_SENSOR_ENTITY_NAME);
+
+	isp->sensor.pads.flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&isp->sensor.sd.entity, 1,
+				&isp->sensor.pads, 0);
+	if (ret < 0)
+		goto p_err3;
+
+	fimc_is_sensor_init_formats(&isp->sensor.sd, NULL);
+
+	isp->sensor.sd.internal_ops = &fimc_is_sensor_v4l2_internal_ops;
+	isp->sensor.sd.entity.ops = &fimc_is_sensor_media_ops;
+
+	ret = v4l2_device_register_subdev(&isp->mdev->v4l2_dev,
+						&isp->sensor.sd);
+	if (ret)
+		goto p_err3;
+	/* This allows to retrieve the platform device id by the host driver */
+	v4l2_set_subdevdata(&isp->sensor.sd, pdev);
+
+
+	/*front entity*/
+	v4l2_subdev_init(&isp->front.sd, &fimc_is_front_subdev_ops);
+	isp->front.sd.owner = THIS_MODULE;
+	isp->front.sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(isp->front.sd.name, sizeof(isp->front.sd.name), "%s\n",
+					FIMC_IS_FRONT_ENTITY_NAME);
+
+	isp->front.pads[FIMC_IS_FRONT_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	isp->front.pads[FIMC_IS_FRONT_PAD_SOURCE_BACK].flags
+							= MEDIA_PAD_FL_SOURCE;
+	isp->front.pads[FIMC_IS_FRONT_PAD_SOURCE_BAYER].flags
+							= MEDIA_PAD_FL_SOURCE;
+	isp->front.pads[FIMC_IS_FRONT_PAD_SOURCE_SCALERC].flags
+							= MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&isp->front.sd.entity, FIMC_IS_FRONT_PADS_NUM,
+				isp->front.pads, 0);
+	if (ret < 0)
+		goto p_err3;
+
+	fimc_is_front_init_formats(&isp->front.sd, NULL);
+
+	isp->front.sd.internal_ops = &fimc_is_front_v4l2_internal_ops;
+	isp->front.sd.entity.ops = &fimc_is_front_media_ops;
+
+	ret = v4l2_device_register_subdev(&isp->mdev->v4l2_dev,
+							&isp->front.sd);
+	if (ret)
+		goto p_err3;
+	/* This allows to retrieve the platform device id by the host driver */
+	v4l2_set_subdevdata(&isp->front.sd, pdev);
+
+
+	/*back entity*/
+	v4l2_subdev_init(&isp->back.sd, &fimc_is_back_subdev_ops);
+	isp->back.sd.owner = THIS_MODULE;
+	isp->back.sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(isp->back.sd.name, sizeof(isp->back.sd.name), "%s\n",
+					FIMC_IS_BACK_ENTITY_NAME);
+
+	isp->back.pads[FIMC_IS_BACK_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	isp->back.pads[FIMC_IS_BACK_PAD_SOURCE_3DNR].flags
+							= MEDIA_PAD_FL_SOURCE;
+	isp->back.pads[FIMC_IS_BACK_PAD_SOURCE_SCALERP].flags
+							= MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&isp->back.sd.entity, FIMC_IS_BACK_PADS_NUM,
+				isp->back.pads, 0);
+	if (ret < 0)
+		goto p_err3;
+
+	fimc_is_front_init_formats(&isp->back.sd, NULL);
+
+	isp->back.sd.internal_ops = &fimc_is_back_v4l2_internal_ops;
+	isp->back.sd.entity.ops = &fimc_is_back_media_ops;
+
+	ret = v4l2_device_register_subdev(&isp->mdev->v4l2_dev, &isp->back.sd);
+	if (ret)
+		goto p_err3;
+
+	v4l2_set_subdevdata(&isp->back.sd, pdev);
+
+	/*front video entity - scalerC */
+	snprintf(isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.name,
+			sizeof(isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.name),
+			"%s", FIMC_IS_VIDEO_SCALERC_NAME);
+
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.fops
+					= &fimc_is_scalerc_video_fops;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.ioctl_ops
+					= &fimc_is_scalerc_video_ioctl_ops;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.v4l2_dev
+						= &isp->mdev->v4l2_dev;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.minor = -1;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.release
+						= video_device_release;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.lock	= &isp->vb_lock;
+	video_set_drvdata(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd, isp);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].dev = isp;
+
+	scalerc_q = &isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq;
+	memset(scalerc_q, 0, sizeof(*scalerc_q));
+	scalerc_q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	scalerc_q->io_modes = VB2_MMAP | VB2_USERPTR;
+	scalerc_q->drv_priv = &isp->video[FIMC_IS_VIDEO_NUM_SCALERC];
+	scalerc_q->ops = &fimc_is_scalerc_qops;
+	scalerc_q->mem_ops = isp->vb2->ops;
+
+	vb2_queue_init(scalerc_q);
+
+	ret = video_register_device(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd,
+			VFL_TYPE_GRABBER,
+			FIMC_IS_VIDEO_NUM_SCALERC+EXYNOS_VIDEONODE_FIMC_IS);
+	dbg("scalerC minor : %d\n",
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.minor);
+	if (ret) {
+		err("Failed to register ScalerC video device\n");
+		goto p_err3;
+	}
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].pads.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+				vd.entity, 1,
+				&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].pads, 0);
+	if (ret) {
+		err("Failed to media_entity_init ScalerC video device\n");
+		goto p_err3;
+	}
+
+	/* back video entity - scalerP*/
+	snprintf(isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.name,
+			sizeof(isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.name),
+			"%s", FIMC_IS_VIDEO_SCALERP_NAME);
+
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.fops
+					= &fimc_is_scalerp_video_fops;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.ioctl_ops
+					= &fimc_is_scalerp_video_ioctl_ops;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.v4l2_dev
+					= &isp->mdev->v4l2_dev;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.minor = -1;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.release = video_device_release;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.lock = &isp->vb_lock;
+	video_set_drvdata(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd, isp);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].dev = isp;
+
+	scalerp_q = &isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq;
+	memset(scalerp_q, 0, sizeof(*scalerp_q));
+	scalerp_q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	scalerp_q->io_modes = VB2_MMAP | VB2_USERPTR;
+	scalerp_q->drv_priv = &isp->video[FIMC_IS_VIDEO_NUM_SCALERP];
+	scalerp_q->ops = &fimc_is_scalerp_qops;
+	scalerp_q->mem_ops = isp->vb2->ops;
+
+	vb2_queue_init(scalerp_q);
+
+	ret = video_register_device(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd,
+				VFL_TYPE_GRABBER,
+				FIMC_IS_VIDEO_NUM_SCALERP
+				+ EXYNOS_VIDEONODE_FIMC_IS);
+	dbg("scalerP minor : %d\n",
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.minor);
+	if (ret) {
+		err("Failed to register ScalerP video device\n");
+		goto p_err3;
+	}
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].pads.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				vd.entity, 1,
+				&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].pads, 0);
+	if (ret) {
+		err("Failed to media_entity_init ScalerP video device\n");
+		goto p_err3;
+	}
+
+	/*back video entity - 3DNR */
+	snprintf(isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.name,
+			sizeof(isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.name),
+			"%s", FIMC_IS_VIDEO_3DNR_NAME);
+
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.fops
+						= &fimc_is_3dnr_video_fops;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.ioctl_ops
+						= &fimc_is_3dnr_video_ioctl_ops;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.v4l2_dev
+						= &isp->mdev->v4l2_dev;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.minor = -1;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.release
+						= video_device_release;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.lock = &isp->vb_lock;
+	video_set_drvdata(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd, isp);
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].dev = isp;
+
+	dnr_q = &isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq;
+	memset(dnr_q, 0, sizeof(*dnr_q));
+	dnr_q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	dnr_q->io_modes = VB2_MMAP | VB2_USERPTR;
+	dnr_q->drv_priv = &isp->video[FIMC_IS_VIDEO_NUM_3DNR];
+	dnr_q->ops = &fimc_is_3dnr_qops;
+	dnr_q->mem_ops = isp->vb2->ops;
+
+	vb2_queue_init(dnr_q);
+
+	ret = video_register_device(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd,
+				VFL_TYPE_GRABBER,
+				FIMC_IS_VIDEO_NUM_3DNR
+				+ EXYNOS_VIDEONODE_FIMC_IS);
+	dbg("3DNR minor : %d\n", isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.minor);
+	if (ret) {
+		err("Failed to register 3DNR video device\n");
+		goto p_err3;
+	}
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].pads.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.entity,
+				1, &isp->video[FIMC_IS_VIDEO_NUM_3DNR].pads, 0);
+	if (ret) {
+		err("Failed to media_entity_init 3DNR video device\n");
+		goto p_err3;
+	}
+
+	/* back video entity - bayer*/
+	snprintf(isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.name,
+			sizeof(isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.name),
+			"%s", FIMC_IS_VIDEO_BAYER_NAME);
+
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.fops
+					= &fimc_is_bayer_video_fops;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.ioctl_ops
+					= &fimc_is_bayer_video_ioctl_ops;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.v4l2_dev	= &isp->mdev->v4l2_dev;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.minor	= -1;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.release	= video_device_release;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.lock	= &isp->vb_lock;
+	video_set_drvdata(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd, isp);
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].dev = isp;
+
+	bayer_q = &isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq;
+	memset(bayer_q, 0, sizeof(*bayer_q));
+	bayer_q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	bayer_q->io_modes = VB2_MMAP | VB2_USERPTR;
+	bayer_q->drv_priv = &isp->video[FIMC_IS_VIDEO_NUM_BAYER];
+	bayer_q->ops = &fimc_is_bayer_qops;
+	bayer_q->mem_ops = isp->vb2->ops;
+
+	vb2_queue_init(bayer_q);
+
+	ret = video_register_device(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd,
+				VFL_TYPE_GRABBER,
+				FIMC_IS_VIDEO_NUM_BAYER
+				+ EXYNOS_VIDEONODE_FIMC_IS);
+	dbg("scalerP minor : %d\n",
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.minor);
+	if (ret) {
+		err("Failed to register ScalerP video device\n");
+		goto p_err3;
+	}
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].pads.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vd.entity,
+			1, &isp->video[FIMC_IS_VIDEO_NUM_BAYER].pads, 0);
+	if (ret) {
+		err("Failed to media_entity_init ScalerP video device\n");
+		goto p_err3;
+	}
+
+	platform_set_drvdata(pdev, isp);
+
+	/* create link */
+	ret = media_entity_create_link(
+			&isp->sensor.sd.entity, FIMC_IS_SENSOR_PAD_SOURCE_FRONT,
+			&isp->front.sd.entity, FIMC_IS_FRONT_PAD_SINK, 0);
+	if (ret < 0) {
+		err("failed link creation from sensor to front\n");
+		goto p_err3;
+	}
+
+	ret = media_entity_create_link(
+			&isp->front.sd.entity, FIMC_IS_FRONT_PAD_SOURCE_BACK,
+			&isp->back.sd.entity, FIMC_IS_BACK_PAD_SINK, 0);
+	if (ret < 0) {
+		err("failed link creation from front to back\n");
+		goto p_err3;
+	}
+
+	ret = media_entity_create_link(
+			&isp->front.sd.entity, FIMC_IS_FRONT_PAD_SOURCE_SCALERC,
+			&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vd.entity, 0, 0);
+
+	if (ret < 0) {
+		err("failed link creation from front to scalerC video\n");
+		goto p_err3;
+	}
+
+	ret = media_entity_create_link(
+			&isp->back.sd.entity, FIMC_IS_BACK_PAD_SOURCE_SCALERP,
+			&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vd.entity, 0, 0);
+
+	if (ret < 0) {
+		err("failed link creation from back to scalerP video\n");
+		goto p_err3;
+	}
+
+	ret = media_entity_create_link(
+			&isp->back.sd.entity, FIMC_IS_BACK_PAD_SOURCE_3DNR,
+			&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vd.entity, 0, 0);
+
+	if (ret < 0) {
+		err("failed link creation from back to 3DNR video\n");
+		goto p_err3;
+	}
+
+	/* register subdev nodes*/
+	ret = v4l2_device_register_subdev_nodes(&isp->mdev->v4l2_dev);
+	if (ret)
+		err("v4l2_device_register_subdev_nodes failed\n");
+
+	/* init vb2*/
+	isp->alloc_ctx = isp->vb2->init(isp);
+	if (IS_ERR(isp->alloc_ctx)) {
+		ret = PTR_ERR(isp->alloc_ctx);
+		goto p_err1;
+	}
+
+	/* init memory*/
+	ret = fimc_is_init_mem(isp);
+	if (ret) {
+		dbg("failed to fimc_is_init_mem (%d)\n", ret);
+		goto p_err3;
+	}
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	isp->bus_dev = dev_get("exynos-busfreq");
+	mutex_init(&isp->busfreq_lock);
+	isp->busfreq_num = 0;
+#endif
+
+	/*init gpio : should be moved to stream_on */
+	if (isp->pdata->cfg_gpio) {
+		isp->pdata->cfg_gpio(isp->pdev);
+	} else {
+		dev_err(&isp->pdev->dev, "failed to init GPIO config\n");
+		goto p_err3;
+	}
+
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	pm_runtime_enable(&pdev->dev);
+#endif
+
+	if (camera_rear == NULL)
+		camera_rear = device_create(camera_class, NULL, 0, NULL, "rear");
+	if (camera_front == NULL)
+		camera_front = device_create(camera_class, NULL, 0, NULL, "front");
+	if (IS_ERR(camera_rear) || IS_ERR(camera_front)) {
+		printk(KERN_ERR "failed to create device!\n");
+	} else {
+		if (device_create_file(camera_front, &dev_attr_front_camtype) < 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_front_camtype.attr.name);
+		}
+		if (device_create_file(camera_front, &dev_attr_front_camfw) < 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_front_camfw.attr.name);
+		}
+		if (device_create_file(camera_rear, &dev_attr_rear_camtype) < 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_rear_camtype.attr.name);
+		}
+		if (device_create_file(camera_rear, &dev_attr_rear_camfw) < 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_rear_camfw.attr.name);
+		}
+	}
+
+	dbg("%s : fimc_is_front_%d probe success\n", __func__, pdev->id);
+	return 0;
+
+p_err3:
+	iounmap(isp->regs);
+p_err2:
+	release_mem_region(regs_res->start, resource_size(regs_res));
+p_err1:
+	kfree(isp);
+	return ret;
+}
+
+static int fimc_is_remove(struct platform_device *pdev)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static const struct dev_pm_ops fimc_is_pm_ops = {
+	.suspend		= fimc_is_suspend,
+	.resume			= fimc_is_resume,
+	.runtime_suspend	= fimc_is_runtime_suspend,
+	.runtime_resume		= fimc_is_runtime_resume,
+};
+
+static struct platform_driver fimc_is_driver = {
+	.probe		= fimc_is_probe,
+	.remove	= __devexit_p(fimc_is_remove),
+	.driver = {
+		.name	= FIMC_IS_MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &fimc_is_pm_ops,
+	}
+};
+
+static int __init fimc_is_init(void)
+{
+	int ret = platform_driver_register(&fimc_is_driver);
+	if (ret)
+		err("platform_driver_register failed: %d\n", ret);
+	return ret;
+}
+
+static void __exit fimc_is_exit(void)
+{
+	platform_driver_unregister(&fimc_is_driver);
+}
+module_init(fimc_is_init);
+module_exit(fimc_is_exit);
+
+MODULE_AUTHOR("Jiyoung Shin<idon.shin@samsung.com>");
+MODULE_DESCRIPTION("Exynos FIMC_IS front end driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.h
new file mode 100644
index 0000000..18f0a34
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-core.h
@@ -0,0 +1,519 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CORE_H
+#define FIMC_IS_CORE_H
+
+/*#define DEBUG 1*/
+#define FRAME_RATE_ENABLE	1
+/*#define ODC_ENABLE	1*/
+/*#define TDNR_ENABLE	1*/
+/*#define DZOOM_ENABLE	1*/
+/*#define DIS_ENABLE	1*/
+
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mediabus.h>
+#include <media/exynos_fimc_is.h>
+#include <media/v4l2-ioctl.h>
+#include <media/exynos_mc.h>
+#include <media/videobuf2-core.h>
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+#include "fimc-is-param.h"
+
+#define FIMC_IS_MODULE_NAME			"exynos5-fimc-is"
+#define FIMC_IS_SENSOR_ENTITY_NAME		"exynos5-fimc-is-sensor"
+#define FIMC_IS_FRONT_ENTITY_NAME		"exynos5-fimc-is-front"
+#define FIMC_IS_BACK_ENTITY_NAME		"exynos5-fimc-is-back"
+#define FIMC_IS_VIDEO_BAYER_NAME		"exynos5-fimc-is-bayer"
+#define FIMC_IS_VIDEO_SCALERC_NAME		"exynos5-fimc-is-scalerc"
+#define FIMC_IS_VIDEO_3DNR_NAME			"exynos5-fimc-is-3dnr"
+#define FIMC_IS_VIDEO_SCALERP_NAME		"exynos5-fimc-is-scalerp"
+
+#define FIMC_IS_DEBUG_LEVEL			(3)
+/*#define FIMC_IS_A5_DEBUG_ON			(1)*/
+
+#define MAX_I2H_ARG				(4)
+
+#define FIMC_IS_FW				"fimc_is_fw.bin"
+#define FIMC_IS_SETFILE				"setfile.bin"
+
+#define FIMC_IS_SHUTDOWN_TIMEOUT		(10*HZ)
+#define FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR		(3*HZ)
+
+#define FIMC_IS_A5_MEM_SIZE			(0x00A00000)
+#define FIMC_IS_REGION_SIZE			(0x5000)
+#define FIMC_IS_SETFILE_SIZE			(0xc0d8)
+#define DRC_SETFILE_SIZE			(0x140)
+#define FD_SETFILE_SIZE				(0x88*2)
+#define FIMC_IS_FW_BASE_MASK			((1 << 26) - 1)
+#define FIMC_IS_TDNR_MEM_SIZE			(1920*1080*4)
+#define FIMC_IS_DEBUG_REGION_ADDR		(0x00840000)
+#define FIMC_IS_SHARED_REGION_ADDR		(0x008C0000)
+
+#define FIMC_IS_MAX_BUF_NUM			(16)
+#define FIMC_IS_MAX_BUf_PLANE_NUM		(3)
+
+#define FIMC_IS_SENSOR_MAX_ENTITIES		(1)
+#define FIMC_IS_SENSOR_PAD_SOURCE_FRONT	(0)
+#define FIMC_IS_SENSOR_PADS_NUM		(1)
+
+#define FIMC_IS_FRONT_MAX_ENTITIES		(1)
+#define FIMC_IS_FRONT_PAD_SINK			(0)
+#define FIMC_IS_FRONT_PAD_SOURCE_BACK		(1)
+#define FIMC_IS_FRONT_PAD_SOURCE_BAYER		(2)
+#define FIMC_IS_FRONT_PAD_SOURCE_SCALERC	(3)
+#define FIMC_IS_FRONT_PADS_NUM			(4)
+
+#define FIMC_IS_BACK_MAX_ENTITIES		(1)
+#define FIMC_IS_BACK_PAD_SINK			(0)
+#define FIMC_IS_BACK_PAD_SOURCE_3DNR		(1)
+#define FIMC_IS_BACK_PAD_SOURCE_SCALERP	(2)
+#define FIMC_IS_BACK_PADS_NUM			(3)
+
+#define MAX_ISP_INTERNAL_BUF_WIDTH		(2560)  /* 4808 in HW */
+#define MAX_ISP_INTERNAL_BUF_HEIGHT		(1920)  /* 3356 in HW */
+#define SIZE_ISP_INTERNAL_BUF \
+	(MAX_ISP_INTERNAL_BUF_WIDTH * MAX_ISP_INTERNAL_BUF_HEIGHT * 3)
+
+#define MAX_ODC_INTERNAL_BUF_WIDTH		(2560)  /* 4808 in HW */
+#define MAX_ODC_INTERNAL_BUF_HEIGHT		(1920)  /* 3356 in HW */
+#define SIZE_ODC_INTERNAL_BUF \
+	(MAX_ODC_INTERNAL_BUF_WIDTH * MAX_ODC_INTERNAL_BUF_HEIGHT * 3)
+
+#define MAX_DIS_INTERNAL_BUF_WIDTH		(2400)
+#define MAX_DIS_INTERNAL_BUF_HEIGHT		(1360)
+#define SIZE_DIS_INTERNAL_BUF \
+	(MAX_DIS_INTERNAL_BUF_WIDTH * MAX_DIS_INTERNAL_BUF_HEIGHT * 2)
+
+#define MAX_3DNR_INTERNAL_BUF_WIDTH		(1920)
+#define MAX_3DNR_INTERNAL_BUF_HEIGHT		(1088)
+#define SIZE_3DNR_INTERNAL_BUF \
+	(MAX_3DNR_INTERNAL_BUF_WIDTH * MAX_3DNR_INTERNAL_BUF_HEIGHT * 2)
+
+#define NUM_ISP_INTERNAL_BUF			(3)
+#define NUM_ODC_INTERNAL_BUF			(2)
+#define NUM_DIS_INTERNAL_BUF			(3)
+#define NUM_3DNR_INTERNAL_BUF			(2)
+
+#define is_af_use(dev)				((dev->af.use_af) ? 1 : 0)
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+#define FIMC_IS_FREQ_MIF		(800)
+#define FIMC_IS_FREQ_INT		(267)
+#endif
+
+#define err(fmt, args...) \
+	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+
+#ifdef DEBUG
+#define dbg(fmt, args...) \
+	printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define dbg(fmt, args...)
+#endif
+
+enum fimc_is_debug_device {
+	FIMC_IS_DEBUG_MAIN = 0,
+	FIMC_IS_DEBUG_EC,
+	FIMC_IS_DEBUG_SENSOR,
+	FIMC_IS_DEBUG_ISP,
+	FIMC_IS_DEBUG_DRC,
+	FIMC_IS_DEBUG_FD,
+	FIMC_IS_DEBUG_SDK,
+	FIMC_IS_DEBUG_SCALERC,
+	FIMC_IS_DEBUG_ODC,
+	FIMC_IS_DEBUG_DIS,
+	FIMC_IS_DEBUG_TDNR,
+	FIMC_IS_DEBUG_SCALERP
+};
+
+enum fimc_is_debug_target {
+	FIMC_IS_DEBUG_UART = 0,
+	FIMC_IS_DEBUG_MEMORY,
+	FIMC_IS_DEBUG_DCC3
+};
+
+enum fimc_is_sensor_output_entity {
+	FIMC_IS_SENSOR_OUTPUT_NONE = 0,
+	FIMC_IS_SENSOR_OUTPUT_FRONT,
+};
+
+enum fimc_is_front_input_entity {
+	FIMC_IS_FRONT_INPUT_NONE = 0,
+	FIMC_IS_FRONT_INPUT_SENSOR,
+};
+
+enum fimc_is_front_output_entity {
+	FIMC_IS_FRONT_OUTPUT_NONE = 0,
+	FIMC_IS_FRONT_OUTPUT_BACK,
+	FIMC_IS_FRONT_OUTPUT_BAYER,
+	FIMC_IS_FRONT_OUTPUT_SCALERC,
+};
+
+enum fimc_is_back_input_entity {
+	FIMC_IS_BACK_INPUT_NONE = 0,
+	FIMC_IS_BACK_INPUT_FRONT,
+};
+
+enum fimc_is_back_output_entity {
+	FIMC_IS_BACK_OUTPUT_NONE = 0,
+	FIMC_IS_BACK_OUTPUT_3DNR,
+	FIMC_IS_BACK_OUTPUT_SCALERP,
+};
+
+enum fimc_is_front_state {
+	FIMC_IS_FRONT_ST_POWERED = 0,
+	FIMC_IS_FRONT_ST_STREAMING,
+	FIMC_IS_FRONT_ST_SUSPENDED,
+};
+
+enum fimc_is_video_dev_num {
+	FIMC_IS_VIDEO_NUM_BAYER = 0,
+	FIMC_IS_VIDEO_NUM_SCALERC,
+	FIMC_IS_VIDEO_NUM_3DNR,
+	FIMC_IS_VIDEO_NUM_SCALERP,
+	FIMC_IS_VIDEO_MAX_NUM,
+};
+
+enum fimc_is_pipe_state {
+	FIMC_IS_STATE_IDLE = 0,
+	FIMC_IS_STATE_FW_DOWNLOADED,
+	FIMC_IS_STATE_SENSOR_INITIALIZED,
+	FIMC_IS_STATE_HW_STREAM_ON,
+	FIMC_IS_STATE_SCALERC_STREAM_ON,
+	FIMC_IS_STATE_SCALERP_STREAM_ON,
+	FIMC_IS_STATE_3DNR_STREAM_ON,
+	FIMC_IS_STATE_BAYER_STREAM_ON,
+	FIMC_IS_STATE_SCALERC_BUFFER_PREPARED,
+	FIMC_IS_STATE_SCALERP_BUFFER_PREPARED,
+	FIMC_IS_STATE_3DNR_BUFFER_PREPARED,
+	FIMC_IS_STATE_BAYER_BUFFER_PREPARED,
+
+};
+
+enum fimc_is_state {
+	IS_ST_IDLE = 0,
+	IS_ST_PWR_ON,
+	IS_ST_FW_DOWNLOADED,
+	IS_ST_OPEN_SENSOR,
+	IS_ST_SETFILE_LOADED,
+	IS_ST_INIT_PREVIEW_STILL,
+	IS_ST_INIT_PREVIEW_VIDEO,
+	IS_ST_INIT_CAPTURE_STILL,
+	IS_ST_INIT_CAPTURE_VIDEO,
+	IS_ST_RUN,
+	IS_ST_STREAM_ON,
+	IS_ST_STREAM_OFF,
+	IS_ST_CHANGE_MODE,
+	IS_ST_SET_PARAM,
+	IS_ST_PEND,
+	IS_ST_BLOCKED,
+	IS_ST_CHANGE_MODE_DONE,
+	IS_ST_SCALERP_FRAME_DONE,
+	IS_ST_BLOCK_CMD_CLEARED,
+	IS_ST_SCALERP_MASK_DONE,
+	IS_ST_SCALERC_MASK_DONE,
+	IS_ST_TDNR_MASK_DONE,
+	IS_ST_END,
+};
+
+enum af_state {
+	FIMC_IS_AF_IDLE		= 0,
+	FIMC_IS_AF_SETCONFIG	= 1,
+	FIMC_IS_AF_RUNNING	= 2,
+	FIMC_IS_AF_LOCK		= 3,
+	FIMC_IS_AF_ABORT	= 4,
+};
+
+enum af_lock_state {
+	FIMC_IS_AF_UNLOCKED	= 0,
+	FIMC_IS_AF_LOCKED	= 0x02
+};
+
+enum ae_lock_state {
+	FIMC_IS_AE_UNLOCKED	= 0,
+	FIMC_IS_AE_LOCKED	= 1
+};
+
+enum awb_lock_state {
+	FIMC_IS_AWB_UNLOCKED	= 0,
+	FIMC_IS_AWB_LOCKED	= 1
+};
+
+enum sensor_list {
+	SENSOR_S5K3H2_CSI_A	= 1,
+	SENSOR_S5K6A3_CSI_A	= 2,
+	SENSOR_S5K4E5_CSI_A	= 3,
+	SENSOR_S5K3H7_CSI_A	= 4,
+	SENSOR_S5K3H2_CSI_B	= 101,
+	SENSOR_S5K6A3_CSI_B	= 102,
+	SENSOR_S5K4E5_CSI_B	= 103,
+	SENSOR_S5K3H7_CSI_B	= 104,
+};
+
+enum fimc_is_power {
+	FIMC_IS_PWR_ST_BASE = 0,
+	FIMC_IS_PWR_ST_POWER_ON_OFF,
+	FIMC_IS_PWR_ST_STREAMING,
+	FIMC_IS_PWR_ST_SUSPENDED,
+	FIMC_IS_PWR_ST_RESUMED,
+};
+
+struct fimc_is_dev;
+
+struct fimc_is_fmt {
+	enum v4l2_mbus_pixelcode mbus_code;
+	char	*name;
+	u32	pixelformat;
+	u16	num_planes;
+};
+
+struct fimc_is_frame {
+	struct fimc_is_fmt		format;
+	u16	width;
+	u16 height;
+};
+
+struct fimc_is_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct fimc_is_dev *isp);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+};
+
+struct fimc_is_sensor_dev {
+	struct v4l2_subdev		sd;
+	struct media_pad		pads;
+	struct v4l2_mbus_framefmt	mbus_fmt;
+	enum fimc_is_sensor_output_entity	output;
+	int id_dual;			/* for dual camera scenario */
+	int id_position;		/* 0 : rear camera, 1: front camera */
+	enum sensor_list sensor_type;
+	u32 width;
+	u32 height;
+	u32 offset_x;
+	u32 offset_y;
+	int framerate_update;
+};
+
+struct fimc_is_front_dev {
+	struct v4l2_subdev		sd;
+	struct media_pad		pads[FIMC_IS_FRONT_PADS_NUM];
+	struct v4l2_mbus_framefmt	mbus_fmt[FIMC_IS_FRONT_PADS_NUM];
+	enum fimc_is_front_input_entity	input;
+	enum fimc_is_front_output_entity	output;
+	u32 width;
+	u32 height;
+
+};
+
+struct fimc_is_back_dev {
+	struct v4l2_subdev		sd;
+	struct media_pad		pads[FIMC_IS_BACK_PADS_NUM];
+	struct v4l2_mbus_framefmt	mbus_fmt[FIMC_IS_BACK_PADS_NUM];
+	enum fimc_is_back_input_entity	input;
+	enum fimc_is_back_output_entity	output;
+	int	dis_on;
+	int	odc_on;
+	int	tdnr_on;
+	u32 width;
+	u32 height;
+	u32 dis_width;
+	u32 dis_height;
+};
+
+struct fimc_is_video_dev {
+	struct video_device		vd;
+	struct media_pad		pads;
+	struct vb2_queue		vbq;
+	struct fimc_is_dev			*dev;
+	struct fimc_is_frame	frame;
+	unsigned int			num_buf;
+	unsigned int			buf_ref_cnt;
+	unsigned int			buf_mask;
+
+	dma_addr_t buf[FIMC_IS_MAX_BUF_NUM][FIMC_IS_MAX_BUf_PLANE_NUM];
+};
+
+struct is_meminfo {
+	dma_addr_t	base;		/* buffer base */
+	size_t		size;		/* total length */
+	dma_addr_t	vaddr_base;	/* buffer base */
+	dma_addr_t	vaddr_curr;	/* current addr */
+	void		*bitproc_buf;
+	size_t		dvaddr;
+	unsigned char	*kvaddr;
+	unsigned char	*dvaddr_shared;
+	unsigned char	*kvaddr_shared;
+	unsigned char	*dvaddr_odc;
+	unsigned char	*kvaddr_odc;
+	unsigned char	*dvaddr_dis;
+	unsigned char	*kvaddr_dis;
+	unsigned char	*dvaddr_3dnr;
+	unsigned char	*kvaddr_3dnr;
+	unsigned char	*dvaddr_isp;
+	unsigned char	*kvaddr_isp;
+	void		*fw_cookie;
+
+};
+
+struct is_fw {
+	const struct firmware	*info;
+	int			state;
+	int			ver;
+};
+
+struct is_setfile {
+	const struct firmware	*info;
+	int			state;
+	u32			sub_index;
+	u32			base;
+	u32			size;
+};
+
+struct is_to_host_cmd {
+	u32	cmd;
+	u32	sensor_id;
+	u16	num_valid_args;
+	u32	arg[MAX_I2H_ARG];
+};
+
+struct is_fd_result_header {
+	u32 offset;
+	u32 count;
+	u32 index;
+	u32 target_addr;
+	s32 width;
+	s32 height;
+};
+
+struct is_af_info {
+	u16 mode;
+	u32 af_state;
+	u32 af_lock_state;
+	u32 ae_lock_state;
+	u32 awb_lock_state;
+	u16 pos_x;
+	u16 pos_y;
+	u16 prev_pos_x;
+	u16 prev_pos_y;
+	u16 use_af;
+};
+
+struct flite_frame {
+	u32 o_width;
+	u32 o_height;
+	u32 width;
+	u32 height;
+	u32 offs_h;
+	u32 offs_v;
+};
+
+struct fimc_is_dev {
+	struct platform_device			*pdev;
+	struct exynos5_platform_fimc_is		*pdata; /* depended on isp */
+	struct exynos_md			*mdev;
+	spinlock_t				slock;
+	struct mutex				vb_lock;
+	struct mutex				lock;
+
+	struct fimc_is_sensor_dev		sensor;
+	struct fimc_is_front_dev		front;
+	struct fimc_is_back_dev			back;
+	/* 0-bayer, 1-scalerC, 2-3DNR, 3-scalerP */
+	struct fimc_is_video_dev		video[FIMC_IS_VIDEO_MAX_NUM];
+	struct vb2_alloc_ctx			*alloc_ctx;
+
+	struct resource				*regs_res;
+	void __iomem				*regs;
+	int					irq;
+	unsigned long				state;
+	unsigned long				power;
+	unsigned long				pipe_state;
+	wait_queue_head_t			irq_queue;
+	u32					id;
+	struct is_fw				fw;
+	struct is_setfile			setfile;
+	struct is_meminfo			mem;
+	struct is_to_host_cmd			i2h_cmd;
+	struct is_fd_result_header		fd_header;
+
+	/* Shared parameter region */
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	struct device				*bus_dev;
+	struct mutex				busfreq_lock;
+	int					busfreq_num;
+#endif
+	atomic_t				p_region_num;
+	unsigned long				p_region_index1;
+	unsigned long				p_region_index2;
+	struct is_region			*is_p_region;
+	struct is_share_region		*is_shared_region;
+	u32					scenario_id;
+	u32					frame_count;
+	u32					sensor_num;
+	struct is_af_info			af;
+	int					low_power_mode;
+
+	const struct fimc_is_vb2		*vb2;
+};
+
+extern const struct v4l2_file_operations fimc_is_bayer_video_fops;
+extern const struct v4l2_ioctl_ops fimc_is_bayer_video_ioctl_ops;
+extern const struct vb2_ops fimc_is_bayer_qops;
+
+extern const struct v4l2_file_operations fimc_is_scalerc_video_fops;
+extern const struct v4l2_ioctl_ops fimc_is_scalerc_video_ioctl_ops;
+extern const struct vb2_ops fimc_is_scalerc_qops;
+
+extern const struct v4l2_file_operations fimc_is_scalerp_video_fops;
+extern const struct v4l2_ioctl_ops fimc_is_scalerp_video_ioctl_ops;
+extern const struct vb2_ops fimc_is_scalerp_qops;
+
+extern const struct v4l2_file_operations fimc_is_3dnr_video_fops;
+extern const struct v4l2_ioctl_ops fimc_is_3dnr_video_ioctl_ops;
+extern const struct vb2_ops fimc_is_3dnr_qops;
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct fimc_is_vb2 fimc_is_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct fimc_is_vb2 fimc_is_vb2_ion;
+#endif
+
+void fimc_is_mem_suspend(void *alloc_ctxes);
+void fimc_is_mem_resume(void *alloc_ctxes);
+void fimc_is_mem_cache_clean(const void *start_addr, unsigned long size);
+void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size);
+int fimc_is_pipeline_s_stream_preview
+	(struct media_entity *start_entity, int on);
+int fimc_is_init_set(struct fimc_is_dev *dev , u32 val);
+int fimc_is_load_fw(struct fimc_is_dev *dev);
+
+#endif /* FIMC_IS_CORE_H_ */
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-err.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-err.h
new file mode 100644
index 0000000..792e7ee
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-err.h
@@ -0,0 +1,214 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_ERR_H
+#define FIMC_IS_ERR_H
+
+#define IS_ERROR_VER 007 /* IS ERROR VERSION 0.07 */
+
+#define IS_ERROR_SUCCESS		0
+/* General 1 ~ 100 */
+#define IS_ERROR_INVALID_PARAMETER	(IS_ERROR_SUCCESS + 1)
+#define IS_ERROR_INVALID_COMMAND	(IS_ERROR_INVALID_PARAMETER + 1)
+#define IS_ERROR_REQUEST_FAIL		(IS_ERROR_INVALID_COMMAND + 1)
+#define IS_ERROR_INVALID_SCENARIO	(IS_ERROR_REQUEST_FAIL + 1)
+#define IS_ERROR_INVALID_SENSORID	(IS_ERROR_INVALID_SCENARIO+1)
+#define IS_ERROR_INVALID_STATE		(IS_ERROR_INVALID_SENSORID+1)
+#define IS_ERROR_BUSY			(IS_ERROR_INVALID_STATE + 1)
+#define IS_ERROR_SET_PARAMETER		(IS_ERROR_BUSY + 1)
+#define IS_ERROR_INVALID_PATH		(IS_ERROR_SET_PARAMETER + 1)
+#define IS_ERROR_TIME_OUT		(IS_ERROR_INVALID_PATH + 1)
+#define IS_ERROR_OPEN_SENSOR_FAIL	(IS_ERROR_TIME_OUT + 1)
+#define IS_ERROR_ENTRY_MSG_THREAD_DOWN	(IS_ERROR_OPEN_SENSOR_FAIL + 1)
+#define IS_ERROR_ENTRY_MSG_IS_MISSING	(IS_ERROR_ENTRY_MSG_THREAD_DOWN + 1)
+#define IS_ERROR_NO_MSG_IS_RECEIVED	(IS_ERROR_ENTRY_MSG_IS_MISSING + 1)
+#define IS_ERROR_SENSOR_MSG_FAIL	(IS_ERROR_NO_MSG_IS_RECEIVED + 1)
+#define IS_ERROR_ISP_MSG_FAIL		(IS_ERROR_SENSOR_MSG_FAIL + 1)
+#define IS_ERROR_DRC_MSG_FAIL		(IS_ERROR_ISP_MSG_FAIL + 1)
+#define IS_ERROR_LHFD_MSG_FAIL		(IS_ERROR_DRC_MSG_FAIL + 1)
+#define IS_ERROR_UNKNOWN		1000
+
+/* Sensor 100 ~ 200 */
+#define IS_ERROR_SENSOR_PWRDN_FAIL	100
+
+/* ISP 200 ~ 300 */
+#define IS_ERROR_ISP_PWRDN_FAIL		200
+#define IS_ERROR_ISP_MULTIPLE_INPUT	(IS_ERROR_ISP_PWRDN_FAIL+1)
+#define IS_ERROR_ISP_ABSENT_INPUT	(IS_ERROR_ISP_MULTIPLE_INPUT+1)
+#define IS_ERROR_ISP_ABSENT_OUTPUT	(IS_ERROR_ISP_ABSENT_INPUT+1)
+#define IS_ERROR_ISP_NONADJACENT_OUTPUT	(IS_ERROR_ISP_ABSENT_OUTPUT+1)
+#define IS_ERROR_ISP_FORMAT_MISMATCH	(IS_ERROR_ISP_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_ISP_WIDTH_MISMATCH	(IS_ERROR_ISP_FORMAT_MISMATCH+1)
+#define IS_ERROR_ISP_HEIGHT_MISMATCH	(IS_ERROR_ISP_WIDTH_MISMATCH+1)
+#define IS_ERROR_ISP_BITWIDTH_MISMATCH	(IS_ERROR_ISP_HEIGHT_MISMATCH+1)
+#define IS_ERROR_ISP_FRAME_END_TIME_OUT	(IS_ERROR_ISP_BITWIDTH_MISMATCH+1)
+
+/* DRC 300 ~ 400 */
+#define IS_ERROR_DRC_PWRDN_FAIL		300
+#define IS_ERROR_DRC_MULTIPLE_INPUT	(IS_ERROR_DRC_PWRDN_FAIL+1)
+#define IS_ERROR_DRC_ABSENT_INPUT	(IS_ERROR_DRC_MULTIPLE_INPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_INTPUT	(IS_ERROR_DRC_ABSENT_INPUT+1)
+#define IS_ERROR_DRC_ABSENT_OUTPUT	(IS_ERROR_DRC_NONADJACENT_INTPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_OUTPUT	(IS_ERROR_DRC_ABSENT_OUTPUT+1)
+#define IS_ERROR_DRC_FORMAT_MISMATCH	(IS_ERROR_DRC_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_DRC_WIDTH_MISMATCH	(IS_ERROR_DRC_FORMAT_MISMATCH+1)
+#define IS_ERROR_DRC_HEIGHT_MISMATCH	(IS_ERROR_DRC_WIDTH_MISMATCH+1)
+#define IS_ERROR_DRC_BITWIDTH_MISMATCH	(IS_ERROR_DRC_HEIGHT_MISMATCH+1)
+#define IS_ERROR_DRC_FRAME_END_TIME_OUT	(IS_ERROR_DRC_BITWIDTH_MISMATCH+1)
+
+/* FD 400 ~ 500 */
+#define IS_ERROR_FD_PWRDN_FAIL		400
+#define IS_ERROR_FD_MULTIPLE_INPUT	(IS_ERROR_FD_PWRDN_FAIL+1)
+#define IS_ERROR_FD_ABSENT_INPUT	(IS_ERROR_FD_MULTIPLE_INPUT+1)
+#define IS_ERROR_FD_NONADJACENT_INPUT	(IS_ERROR_FD_ABSENT_INPUT+1)
+#define IS_ERROR_LHFD_FRAME_END_TIME_OUT \
+					(IS_ERROR_FD_NONADJACENT_INPUT+1)
+
+/* Set parameter error enum */
+enum error {
+	/* Common error (0~99) */
+	ERROR_COMMON_NO			= 0,
+	ERROR_COMMON_CMD		= 1,	/* Invalid command*/
+	ERROR_COMMON_PARAMETER		= 2,	/* Invalid parameter*/
+	/* setfile is not loaded before adjusting */
+	ERROR_COMMON_SETFILE_LOAD	= 3,
+	/* setfile is not Adjusted before runnng. */
+	ERROR_COMMON_SETFILE_ADJUST	= 4,
+	/* index of setfile is not valid. */
+	ERROR_COMMON_SETFILE_INDEX = 5,
+	/* Input path can be changed in ready state(stop) */
+	ERROR_COMMON_INPUT_PATH		= 6,
+	/* IP can not start if input path is not set */
+	ERROR_COMMON_INPUT_INIT		= 7,
+	/* Output path can be changed in ready state(stop) */
+	ERROR_COMMON_OUTPUT_PATH	= 8,
+	/* IP can not start if output path is not set */
+	ERROR_COMMON_OUTPUT_INIT	= 9,
+
+	ERROR_CONTROL_NO		= ERROR_COMMON_NO,
+	ERROR_CONTROL_BYPASS		= 11,	/* Enable or Disable */
+	ERROR_CONTROL_BUF		= 12,	/* invalid buffer info */
+
+	ERROR_OTF_INPUT_NO		= ERROR_COMMON_NO,
+	/* invalid command */
+	ERROR_OTF_INPUT_CMD		= 21,
+	/* invalid format  (DRC: YUV444, FD: YUV444, 422, 420) */
+	ERROR_OTF_INPUT_FORMAT		= 22,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_OTF_INPUT_WIDTH		= 23,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_OTF_INPUT_HEIGHT		= 24,
+	/* invalid bit-width (DRC: 8~12bits, FD: 8bit) */
+	ERROR_OTF_INPUT_BIT_WIDTH	= 25,
+	/* invalid frame time for ISP */
+	ERROR_OTF_INPUT_USER_FRAMETILE = 26,
+
+	ERROR_DMA_INPUT_NO		= ERROR_COMMON_NO,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_DMA_INPUT_WIDTH		= 31,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_DMA_INPUT_HEIGHT		= 32,
+	/* invalid format (DRC: YUV444 or YUV422, FD: YUV444, 422, 420) */
+	ERROR_DMA_INPUT_FORMAT		= 33,
+	/* invalid bit-width (DRC: 8~12bit, FD: 8bit) */
+	ERROR_DMA_INPUT_BIT_WIDTH	= 34,
+	/* invalid order(DRC: YYCbCrorYCbYCr, FD:NO,YYCbCr,YCbYCr,CbCr,CrCb) */
+	ERROR_DMA_INPUT_ORDER		= 35,
+	/* invalid palne (DRC: 3, FD: 1, 2, 3) */
+	ERROR_DMA_INPUT_PLANE		= 36,
+
+	ERROR_OTF_OUTPUT_NO		= ERROR_COMMON_NO,
+	/* invalid width (DRC: 128~8192) */
+	ERROR_OTF_OUTPUT_WIDTH		= 41,
+	/* invalid height (DRC: 64~8192) */
+	ERROR_OTF_OUTPUT_HEIGHT		= 42,
+	/* invalid format (DRC: YUV444) */
+	ERROR_OTF_OUTPUT_FORMAT		= 43,
+	/* invalid bit-width (DRC: 8~12bits) */
+	ERROR_OTF_OUTPUT_BIT_WIDTH	= 44,
+
+	ERROR_DMA_OUTPUT_NO		= ERROR_COMMON_NO,
+	ERROR_DMA_OUTPUT_WIDTH		= 51,	/* invalid width */
+	ERROR_DMA_OUTPUT_HEIGHT		= 52,	/* invalid height */
+	ERROR_DMA_OUTPUT_FORMAT		= 53,	/* invalid format */
+	ERROR_DMA_OUTPUT_BIT_WIDTH	= 54,	/* invalid bit-width */
+	ERROR_DMA_OUTPUT_PLANE		= 55,	/* invalid plane */
+	ERROR_DMA_OUTPUT_ORDER		= 56,	/* invalid order */
+	ERROR_DMA_OUTPUT_BUF		= 57,	/* invalid buffer info */
+
+	ERROR_GLOBAL_SHOTMODE_NO	= ERROR_COMMON_NO,
+
+	/* SENSOR Error(100~199) */
+	ERROR_SENSOR_NO			= ERROR_COMMON_NO,
+	ERROR_SENSOR_I2C_FAIL		= 101,
+	ERROR_SENSOR_INVALID_FRAMERATE,
+	ERROR_SENSOR_INVALID_EXPOSURETIME,
+	ERROR_SENSOR_INVALID_SIZE,
+	ERROR_SENSOR_ACTURATOR_INIT_FAIL,
+	ERROR_SENSOR_INVALID_AF_POS,
+	ERROR_SENSOR_UNSUPPORT_FUNC,
+	ERROR_SENSOR_UNSUPPORT_PERI,
+	ERROR_SENSOR_UNSUPPORT_AF,
+	ERROR_SENSOR_STOP_FAIL,
+
+	/* ISP Error (200~299) */
+	ERROR_ISP_AF_NO			= ERROR_COMMON_NO,
+	ERROR_ISP_AF_BUSY		= 201,
+	ERROR_ISP_AF_INVALID_COMMAND	= 202,
+	ERROR_ISP_AF_INVALID_MODE	= 203,
+	ERROR_ISP_FLASH_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_AWB_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_IMAGE_EFFECT_NO	= ERROR_COMMON_NO,
+	ERROR_ISP_ISO_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_ADJUST_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_METERING_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_AFC_NO		= ERROR_COMMON_NO,
+
+	/* DRC Error (300~399) */
+
+	/* FD Error  (400~499) */
+	ERROR_FD_NO					= ERROR_COMMON_NO,
+	/* Invalid max number (1~16) */
+	ERROR_FD_CONFIG_MAX_NUMBER_STATE		= 401,
+	ERROR_FD_CONFIG_MAX_NUMBER_INVALID		= 402,
+	ERROR_FD_CONFIG_YAW_ANGLE_STATE			= 403,
+	ERROR_FD_CONFIG_YAW_ANGLE_INVALID		= 404,
+	ERROR_FD_CONFIG_ROLL_ANGLE_STATE		= 405,
+	ERROR_FD_CONFIG_ROLL_ANGLE_INVALID		= 406,
+	ERROR_FD_CONFIG_SMILE_MODE_INVALID		= 407,
+	ERROR_FD_CONFIG_BLINK_MODE_INVALID		= 408,
+	ERROR_FD_CONFIG_EYES_DETECT_INVALID		= 409,
+	ERROR_FD_CONFIG_MOUTH_DETECT_INVALID		= 410,
+	ERROR_FD_CONFIG_ORIENTATION_STATE		= 411,
+	ERROR_FD_CONFIG_ORIENTATION_INVALID		= 412,
+	ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID	= 413,
+	/* PARAM_FdResultStr can be only applied
+	 * in ready-state or stream off */
+	ERROR_FD_RESULT				= 414,
+	/* PARAM_FdModeStr can be only applied
+	 * in ready-state or stream off */
+	ERROR_FD_MODE					= 415,
+
+	/*SCALER ERR(500~599)*/
+	ERROR_SCALER_NO			= ERROR_COMMON_NO,
+	ERROR_SCALER_DMA_OUTSEL		= 501,
+	ERROR_SCALER_H_RATIO			= 502,
+	ERROR_SCALER_V_RATIO			= 503,
+	ERROR_SCALER_FRAME_BUFFER_SEQ		= 504,
+
+	ERROR_SCALER_IMAGE_EFFECT		= 510,
+
+	ERROR_SCALER_ROTATE			= 520,
+	ERROR_SCALER_FLIP			= 521,
+
+};
+
+#endif
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.c b/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.c
new file mode 100644
index 0000000..3f6ca2b
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.c
@@ -0,0 +1,2237 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * exynos5 fimc-is helper functions
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <media/exynos_fimc_is.h>
+
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-param.h"
+#include "fimc-is-err.h"
+#include "fimc-is-helper.h"
+#include "fimc-is-misc.h"
+
+
+
+/*
+Default setting values
+*/
+static const struct sensor_param init_val_sensor_preview_still = {
+	.frame_rate = {
+		.frame_rate = DEFAULT_PREVIEW_STILL_FRAMERATE,
+	},
+};
+
+static const struct isp_param init_val_isp_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_BAYER,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 33333,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0,
+		.height = 0,
+		.format = 0,
+		.bitwidth = 0,
+		.plane = 0,
+		.order = 0,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = 0,
+		.scene = 0,
+		.sleep = 0,
+		.face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NO,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NO,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NO,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NO,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NO,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NO,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.err = ISP_METERING_ERROR_NO,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma1_output = {
+#ifdef DZOOM_EVT0
+		.cmd = DMA_OUTPUT_COMMAND_ENABLE,
+		.dma_out_mask = 0xFFFFFFFF,
+#else
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.dma_out_mask = 0,
+#endif
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_INPUT_FORMAT_YUV444,
+		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_INPUT_PLANE_1,
+		.order = DMA_INPUT_ORDER_YCbCr,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_BAYER,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_GB_BG,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xFFFFFFFF,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct drc_param init_val_drc_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_INPUT_FORMAT_YUV444,
+		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_INPUT_PLANE_1,
+		.order = DMA_INPUT_ORDER_YCbCr,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct scalerc_param init_val_scalerc_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.effect = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.input_crop = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_STILL_CROP_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_STILL_CROP_HEIGHT,
+		.in_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.in_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.out_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.out_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.err = 0,
+	},
+	.output_crop = {
+		.cmd = OTF_INPUT_COMMAND_DISABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV422,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV422,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_CrYCbY,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.reserved[0] = 2, /* unscaled*/
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct odc_param init_val_odc_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV422,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct dis_param init_val_dis_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV422,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+static const struct tdnr_param init_val_tdnr_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.frame = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV420,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_2,
+		.order = DMA_OUTPUT_ORDER_CbCr,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct scalerp_param init_val_scalerp_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.effect = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.input_crop = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.in_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.in_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.out_width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.out_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.err = 0,
+	},
+	.output_crop = {
+		.cmd = OTF_INPUT_COMMAND_DISABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.crop_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV420,
+		.err = 0,
+	},
+	.rotation = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.flip = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV420,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_OUTPUT_ORDER_NO,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct fd_param init_val_fd_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = 5,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NO,
+	},
+};
+
+/*
+ Group 1. Interrupt
+*/
+void fimc_is_hw_set_intgr0_gd0(struct fimc_is_dev *dev)
+{
+	writel(INTGR0_INTGD0, dev->regs + INTGR0);
+}
+
+int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + INTSR0);
+	u32 status = INTSR0_GET_INTSD0(cfg);
+	while (status) {
+		cfg = readl(dev->regs + INTSR0);
+		status = INTSR0_GET_INTSD0(cfg);
+	}
+	return 0;
+}
+
+int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + INTMSR0);
+	u32 status = INTMSR0_GET_INTMSD0(cfg);
+	while (status) {
+		cfg = readl(dev->regs + INTMSR0);
+		status = INTMSR0_GET_INTMSD0(cfg);
+	}
+	return 0;
+}
+
+int fimc_is_fw_clear_irq1(struct fimc_is_dev *dev, unsigned int intr_pos)
+{
+	writel((1<<intr_pos), dev->regs + INTCR1);
+	return 0;
+}
+
+int fimc_is_fw_clear_irq1_all(struct fimc_is_dev *dev)
+{
+	writel(0xFF, dev->regs + INTCR1);
+	return 0;
+}
+int fimc_is_fw_clear_irq2(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + INTSR2);
+
+	writel(cfg, dev->regs + INTCR2);
+	return 0;
+}
+
+int fimc_is_fw_clear_insr1(struct fimc_is_dev *dev)
+{
+
+	writel(0, dev->regs + INTGR1);
+	return 0;
+}
+
+/*
+ Group 2. Common
+*/
+int fimc_is_hw_get_sensor_type(enum exynos5_sensor_id sensor_id,
+				enum exynos5_flite_id flite_id)
+{
+	int id = sensor_id;
+
+	if (flite_id == FLITE_ID_A)
+		id = sensor_id;
+	else if (flite_id == FLITE_ID_B)
+		id = sensor_id + 100;
+
+	return id;
+}
+
+int fimc_is_hw_get_sensor_max_framerate(struct fimc_is_dev *dev)
+{
+	int max_framerate = 0;
+	switch (dev->sensor.sensor_type) {
+	case SENSOR_S5K3H2_CSI_A:
+	case SENSOR_S5K3H2_CSI_B:
+		max_framerate = 15;
+		break;
+	case SENSOR_S5K3H7_CSI_A:
+	case SENSOR_S5K3H7_CSI_B:
+		max_framerate = 30;
+		break;
+	case SENSOR_S5K6A3_CSI_A:
+	case SENSOR_S5K6A3_CSI_B:
+		max_framerate = 30;
+		break;
+	case SENSOR_S5K4E5_CSI_A:
+	case SENSOR_S5K4E5_CSI_B:
+		max_framerate = 30;
+		break;
+	default:
+		max_framerate = 15;
+	}
+	return max_framerate;
+}
+
+void fimc_is_hw_open_sensor(struct fimc_is_dev *dev, u32 id, u32 sensor_index)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_OPEN_SENSOR, dev->regs + ISSR0);
+	writel(id, dev->regs + ISSR1);
+	switch (sensor_index) {
+	case SENSOR_S5K3H2_CSI_A:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_A;
+		writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		break;
+	case SENSOR_S5K3H2_CSI_B:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_B;
+		writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		break;
+	case SENSOR_S5K6A3_CSI_A:
+		dev->af.use_af = 0;
+		dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_A;
+		writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		break;
+	case SENSOR_S5K6A3_CSI_B:
+		dev->af.use_af = 0;
+		dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_B;
+		writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		break;
+	case SENSOR_S5K4E5_CSI_A:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_A;
+		writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		break;
+	case SENSOR_S5K4E5_CSI_B:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_B;
+		writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		break;
+	}
+	/* Parameter3 : Scenario ID(Initial Scenario) */
+	writel(ISS_PREVIEW_STILL, dev->regs + ISSR4);
+	fimc_is_hw_set_intgr0_gd0(dev);
+
+}
+
+void fimc_is_hw_close_sensor(struct fimc_is_dev *dev, u32 id)
+{
+	if (dev->sensor.id_dual == id) {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_CLOSE_SENSOR, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		writel(dev->sensor.id_dual, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	}
+}
+
+void fimc_is_hw_diable_wdt(struct fimc_is_dev *dev)
+{
+	writel(0x0, dev->regs + WDT);
+}
+
+void fimc_is_hw_set_low_poweroff(struct fimc_is_dev *dev, int on)
+{
+	if (on) {
+		printk(KERN_INFO "Set low poweroff mode\n");
+		__raw_writel(0x0, PMUREG_ISP_ARM_OPTION);
+		__raw_writel(0x1CF82000, PMUREG_ISP_LOW_POWER_OFF);
+		dev->low_power_mode = true;
+	} else {
+		if (dev->low_power_mode) {
+			printk(KERN_INFO "Clear low poweroff mode\n");
+			__raw_writel(0xFFFFFFFF, PMUREG_ISP_ARM_OPTION);
+			__raw_writel(0x8, PMUREG_ISP_LOW_POWER_OFF);
+		}
+		dev->low_power_mode = false;
+	}
+}
+
+void fimc_is_hw_subip_poweroff(struct fimc_is_dev *dev)
+{
+	/* 1. Make FIMC-IS power-off state */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_POWER_DOWN, dev->regs + ISSR0);
+	writel(dev->sensor.id_dual, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+int fimc_is_hw_a5_power_on(struct fimc_is_dev *isp)
+{
+	u32 cfg;
+	u32 timeout;
+
+	mutex_lock(&isp->lock);
+
+	if (isp->low_power_mode)
+		fimc_is_hw_set_low_poweroff(isp, false);
+
+	dbg("%s\n", __func__);
+
+	writel(0x7, PMUREG_ISP_CONFIGURATION);
+	timeout = 1000;
+	while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7) != 0x7) {
+		if (timeout == 0)
+			err("A5 power on failed1\n");
+		timeout--;
+		udelay(1);
+	}
+
+	enable_mipi();
+
+	/* init Clock */
+	if (isp->pdata->clk_cfg) {
+		isp->pdata->clk_cfg(isp->pdev);
+	} else {
+		dev_err(&isp->pdev->dev, "failed to config clock\n");
+		goto done;
+	}
+
+	if (isp->pdata->clk_on) {
+		isp->pdata->clk_on(isp->pdev);
+	} else {
+		dev_err(&isp->pdev->dev, "failed to clock on\n");
+		goto done;
+	}
+
+	/* 1. A5 start address setting */
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	cfg = isp->mem.base;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	cfg = isp->mem.dvaddr;
+	if (isp->alloc_ctx)
+		fimc_is_mem_resume(isp->alloc_ctx);
+#endif
+
+	dbg("mem.base(dvaddr) : 0x%08x\n", cfg);
+	dbg("mem.base(kvaddr) : 0x%08x\n", (unsigned int)isp->mem.kvaddr);
+	writel(cfg, isp->regs + BBOAR);
+
+	/* 2. A5 power on*/
+	writel(0x1, PMUREG_ISP_ARM_CONFIGURATION);
+
+	/* 3. enable A5 */
+	writel(0x00018000, PMUREG_ISP_ARM_OPTION);
+	timeout = 1000;
+	while ((__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) != 0x1) {
+		if (timeout == 0)
+			err("A5 power on failed2\n");
+		timeout--;
+		udelay(1);
+	}
+
+	/* HACK : fimc_is_irq_handler() cannot
+	 * set 1 on FIMC_IS_PWR_ST_POWER_ON_OFF */
+	set_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power);
+
+done:
+	mutex_unlock(&isp->lock);
+	return 0;
+}
+
+int fimc_is_hw_a5_power_off(struct fimc_is_dev *isp)
+{
+	u32 timeout;
+
+	dbg("%s\n", __func__);
+
+	mutex_lock(&isp->lock);
+
+#if defined(CONFIG_VIDEOBUF2_ION)
+	if (isp->alloc_ctx)
+		fimc_is_mem_suspend(isp->alloc_ctx);
+#endif
+
+	if (isp->pdata->clk_off) {
+		isp->pdata->clk_off(isp->pdev);
+	} else {
+		dev_err(&isp->pdev->dev, "failed to clock on\n");
+		goto done;
+	}
+	/* 1. disable A5 */
+	writel(0x0, PMUREG_ISP_ARM_OPTION);
+
+	/* 2. A5 power off*/
+	writel(0x0, PMUREG_ISP_ARM_CONFIGURATION);
+
+	/* 3. Check A5 power off status register */
+	timeout = 1000;
+	while (__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) {
+		if (timeout == 0)
+			err("A5 power off failed\n");
+		timeout--;
+		udelay(1);
+	}
+
+	/* 4. ISP Power down mode (LOWPWR) */
+	writel(0x0, PMUREG_CMU_RESET_ISP_SYS_PWR_REG);
+
+	writel(0x0, PMUREG_ISP_CONFIGURATION);
+
+	timeout = 1000;
+	while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7)) {
+		if (timeout == 0) {
+			err("ISP power off failed --> Retry\n");
+			/* Retry */
+			__raw_writel(0x1CF82000, PMUREG_ISP_LOW_POWER_OFF);
+			timeout = 1000;
+			while ((__raw_readl(PMUREG_ISP_STATUS) & 0x7)) {
+				if (timeout == 0)
+					err("ISP power off failed\n");
+				timeout--;
+				udelay(1);
+			}
+		}
+		timeout--;
+		udelay(1);
+	}
+
+done:
+	mutex_unlock(&isp->lock);
+	return 0;
+}
+
+void fimc_is_hw_a5_power(struct fimc_is_dev *isp, int on)
+{
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	struct device *dev = &isp->pdev->dev;
+#endif
+
+	printk(KERN_INFO "%s(%d)\n", __func__, on);
+
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	if (on)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_put_sync(dev);
+#else
+	if (on)
+		fimc_is_hw_a5_power_on(isp);
+	else
+		fimc_is_hw_a5_power_off(isp);
+#endif
+}
+
+void fimc_is_hw_set_sensor_num(struct fimc_is_dev *dev)
+{
+	u32 cfg;
+	writel(ISR_DONE, dev->regs + ISSR0);
+	cfg = dev->sensor.id_dual;
+	writel(cfg, dev->regs + ISSR1);
+	/* param 1 */
+	writel(IHC_GET_SENSOR_NUMBER, dev->regs + ISSR2);
+	/* param 2 */
+	cfg = dev->sensor_num;
+	writel(cfg, dev->regs + ISSR3);
+}
+
+void fimc_is_hw_get_setfile_addr(struct fimc_is_dev *dev)
+{
+	/* 1. Get FIMC-IS setfile address */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_GET_SET_FILE_ADDR, dev->regs + ISSR0);
+	writel(dev->sensor.id_dual, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+void fimc_is_hw_load_setfile(struct fimc_is_dev *dev)
+{
+	/* 1. Make FIMC-IS power-off state */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_LOAD_SET_FILE, dev->regs + ISSR0);
+	writel(dev->sensor.id_dual, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+int fimc_is_hw_get_sensor_num(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + ISSR11);
+	if (dev->sensor_num == cfg)
+		return 0;
+	else
+		return cfg;
+}
+
+void fimc_is_hw_set_debug_level(struct fimc_is_dev *dev,
+				int target,
+				int module,
+				int level)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_MSG_CONFIG, dev->regs + ISSR0);
+	writel(dev->sensor.id_dual, dev->regs + ISSR1);
+
+	writel(target, dev->regs + ISSR2);
+	writel(module, dev->regs + ISSR3);
+	writel(level, dev->regs + ISSR4);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+int fimc_is_hw_set_param(struct fimc_is_dev *dev)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_SET_PARAMETER, dev->regs + ISSR0);
+	writel(dev->sensor.id_dual, dev->regs + ISSR1);
+
+	writel(dev->scenario_id, dev->regs + ISSR2);
+
+	writel(atomic_read(&dev->p_region_num), dev->regs + ISSR3);
+	writel(dev->p_region_index1, dev->regs + ISSR4);
+	writel(dev->p_region_index2, dev->regs + ISSR5);
+	dbg("### set param\n");
+	dbg("cmd :0x%08x\n", HIC_SET_PARAMETER);
+	dbg("senorID :0x%08x\n", dev->sensor.id_dual);
+	dbg("parma1 :0x%08x\n", dev->scenario_id);
+	dbg("parma2 :0x%08x\n", atomic_read(&dev->p_region_num));
+	dbg("parma3 :0x%08x\n", (unsigned int)dev->p_region_index1);
+	dbg("parma4 :0x%08x\n", (unsigned int)dev->p_region_index2);
+
+	fimc_is_hw_set_intgr0_gd0(dev);
+	return 0;
+}
+
+int fimc_is_hw_update_bufmask(struct fimc_is_dev *dev, unsigned int dev_num)
+{
+	int buf_mask;
+	int i = 0;
+	int cnt = 0;
+
+	buf_mask = dev->video[dev_num].buf_mask;
+
+	for (i = 0; i < 16; i++) {
+		if (((buf_mask & (1 << i)) >> i) == 1)
+			cnt++;
+	}
+	dbg("dev_num: %u, buf_mask: %#x, cnt: %d\n", dev_num, buf_mask, cnt);
+
+	if (cnt == 1) {
+		err("ERR: Not enough buffers[dev_num: %u, buf_mask: %#x]\n",
+							dev_num, buf_mask);
+		goto done;
+	}
+
+	switch (dev_num) {
+	case 0: /* Bayer */
+		if (readl(dev->regs + ISSR23) != 0x0)
+			dbg("WARN: Bayer buffer mask is unchecked\n");
+
+		writel(buf_mask, dev->regs + ISSR23);
+		break;
+	case 1:  /* Scaler-C */
+		if (readl(dev->regs + ISSR31) != 0x0)
+			dbg("WARN: Scaler-C buffer mask is unchecked\n");
+
+		writel(buf_mask, dev->regs + ISSR31);
+		break;
+	case 2: /* 3DNR */
+		if (readl(dev->regs + ISSR39) != 0x0)
+			dbg("WARN: 3DNR buffer mask is unchecked\n");
+
+		writel(buf_mask, dev->regs + ISSR39);
+		break;
+	case 3: /* Scaler-P */
+		if (readl(dev->regs + ISSR47) != 0x0)
+			dbg("WARN: Scaler-P buffer mask is unchecked\n");
+
+		writel(buf_mask, dev->regs + ISSR47);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+done:
+	return 0;
+}
+
+int fimc_is_hw_get_param(struct fimc_is_dev *dev, u16 offset)
+{
+	dev->i2h_cmd.num_valid_args = offset;
+	switch (offset) {
+	case 1:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = 0;
+		dev->i2h_cmd.arg[2] = 0;
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 2:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = 0;
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 3:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 4:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
+		dev->i2h_cmd.arg[3] = readl(dev->regs + ISSR15);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void fimc_is_hw_set_stream(struct fimc_is_dev *dev, int on)
+{
+	if (on) {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_STREAM_ON, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	} else {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_STREAM_OFF, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	}
+}
+
+void fimc_is_hw_change_mode(struct fimc_is_dev *dev, int val)
+{
+	switch (val) {
+	case IS_MODE_PREVIEW_STILL:
+		dev->scenario_id = ISS_PREVIEW_STILL;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		writel(HIC_PREVIEW_STILL, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_PREVIEW_VIDEO:
+		dev->scenario_id = ISS_PREVIEW_VIDEO;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		writel(HIC_PREVIEW_VIDEO, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_CAPTURE_STILL:
+		dev->scenario_id = ISS_CAPTURE_STILL;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		writel(HIC_CAPTURE_STILL, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_CAPTURE_VIDEO:
+		dev->scenario_id = ISS_CAPTURE_VIDEO;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		writel(HIC_CAPTURE_VIDEO, dev->regs + ISSR0);
+		writel(dev->sensor.id_dual, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	}
+}
+/*
+ Group 3. Initial setting
+*/
+void fimc_is_hw_set_init(struct fimc_is_dev *dev)
+{
+	u32 length;
+
+
+	IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 0);
+	IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SENSOR_SET_FRAME_RATE(dev, DEFAULT_PREVIEW_STILL_FRAMERATE);
+	IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+	IS_INC_PARAM_NUM(dev);
+	/* ISP */
+	IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+		init_val_isp_preview_still.control.cmd);
+	IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_isp_preview_still.control.bypass);
+	IS_ISP_SET_PARAM_CONTROL_ERR(dev,
+		init_val_isp_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_isp_preview_still.otf_input.cmd);
+	IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_isp_preview_still.otf_input.width);
+	IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_isp_preview_still.otf_input.height);
+	dev->sensor.width =
+		init_val_isp_preview_still.otf_input.width;
+	dev->sensor.width =
+		init_val_isp_preview_still.otf_input.height;
+	IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_isp_preview_still.otf_input.format);
+	IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_isp_preview_still.otf_input.bitwidth);
+	IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_isp_preview_still.otf_input.order);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
+		init_val_isp_preview_still.otf_input.crop_offset_x);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
+		init_val_isp_preview_still.otf_input.crop_offset_y);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
+		init_val_isp_preview_still.otf_input.crop_width);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
+		init_val_isp_preview_still.otf_input.crop_height);
+	IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
+		init_val_isp_preview_still.otf_input.frametime_min);
+	IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+		init_val_isp_preview_still.otf_input.frametime_max);
+	IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_isp_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
+		init_val_isp_preview_still.dma1_input.cmd);
+	IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
+		init_val_isp_preview_still.dma1_input.width);
+	IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
+		init_val_isp_preview_still.dma1_input.height);
+	IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
+		init_val_isp_preview_still.dma1_input.format);
+	IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
+		init_val_isp_preview_still.dma1_input.bitwidth);
+	IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
+		init_val_isp_preview_still.dma1_input.plane);
+	IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
+		init_val_isp_preview_still.dma1_input.order);
+	IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
+		init_val_isp_preview_still.dma1_input.buffer_number);
+	IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
+		init_val_isp_preview_still.dma1_input.buffer_address);
+	IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
+		init_val_isp_preview_still.dma1_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
+		init_val_isp_preview_still.dma2_input.cmd);
+	IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
+		init_val_isp_preview_still.dma2_input.width);
+	IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
+		init_val_isp_preview_still.dma2_input.height);
+	IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
+		init_val_isp_preview_still.dma2_input.format);
+	IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
+		init_val_isp_preview_still.dma2_input.bitwidth);
+	IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
+		init_val_isp_preview_still.dma2_input.plane);
+	IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
+		init_val_isp_preview_still.dma2_input.order);
+	IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
+		init_val_isp_preview_still.dma2_input.buffer_number);
+	IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
+		init_val_isp_preview_still.dma2_input.buffer_address);
+	IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
+		init_val_isp_preview_still.dma2_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_AA_CMD(dev,
+		init_val_isp_preview_still.aa.cmd);
+	IS_ISP_SET_PARAM_AA_TARGET(dev,
+		init_val_isp_preview_still.aa.target);
+	IS_ISP_SET_PARAM_AA_MODE(dev,
+		init_val_isp_preview_still.aa.mode);
+	IS_ISP_SET_PARAM_AA_FACE(dev,
+		init_val_isp_preview_still.aa.face);
+	IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
+		init_val_isp_preview_still.aa.touch_x);
+	IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
+		init_val_isp_preview_still.aa.touch_y);
+	IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
+		init_val_isp_preview_still.aa.manual_af_setting);
+	IS_ISP_SET_PARAM_AA_ERR(dev,
+		init_val_isp_preview_still.aa.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_FLASH_CMD(dev,
+		init_val_isp_preview_still.flash.cmd);
+	IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
+		init_val_isp_preview_still.flash.redeye);
+	IS_ISP_SET_PARAM_FLASH_ERR(dev,
+		init_val_isp_preview_still.flash.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_AWB_CMD(dev,
+		init_val_isp_preview_still.awb.cmd);
+	IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+		init_val_isp_preview_still.awb.illumination);
+	IS_ISP_SET_PARAM_AWB_ERR(dev,
+		init_val_isp_preview_still.awb.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+		init_val_isp_preview_still.effect.cmd);
+	IS_ISP_SET_PARAM_EFFECT_ERR(dev,
+		init_val_isp_preview_still.effect.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_ISO_CMD(dev,
+		init_val_isp_preview_still.iso.cmd);
+	IS_ISP_SET_PARAM_ISO_VALUE(dev,
+		init_val_isp_preview_still.iso.value);
+	IS_ISP_SET_PARAM_ISO_ERR(dev,
+		init_val_isp_preview_still.iso.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+		init_val_isp_preview_still.adjust.cmd);
+	IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
+		init_val_isp_preview_still.adjust.contrast);
+	IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
+		init_val_isp_preview_still.adjust.saturation);
+	IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
+		init_val_isp_preview_still.adjust.sharpness);
+	IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
+		init_val_isp_preview_still.adjust.exposure);
+	IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
+		init_val_isp_preview_still.adjust.brightness);
+	IS_ISP_SET_PARAM_ADJUST_HUE(dev,
+		init_val_isp_preview_still.adjust.hue);
+	IS_ISP_SET_PARAM_ADJUST_ERR(dev,
+		init_val_isp_preview_still.adjust.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_METERING_CMD(dev,
+		init_val_isp_preview_still.metering.cmd);
+	IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
+		init_val_isp_preview_still.metering.win_pos_x);
+	IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
+		init_val_isp_preview_still.metering.win_pos_y);
+	IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+		init_val_isp_preview_still.metering.win_width);
+	IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+		init_val_isp_preview_still.metering.win_height);
+	IS_ISP_SET_PARAM_METERING_ERR(dev,
+		init_val_isp_preview_still.metering.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_AFC_CMD(dev,
+		init_val_isp_preview_still.afc.cmd);
+	IS_ISP_SET_PARAM_AFC_MANUAL(dev,
+		init_val_isp_preview_still.afc.manual);
+	IS_ISP_SET_PARAM_AFC_ERR(dev,
+		init_val_isp_preview_still.afc.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_isp_preview_still.otf_output.cmd);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_isp_preview_still.otf_output.width);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_isp_preview_still.otf_output.height);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_isp_preview_still.otf_output.format);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_isp_preview_still.otf_output.bitwidth);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_isp_preview_still.otf_output.order);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_isp_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
+		init_val_isp_preview_still.dma1_output.cmd);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+		init_val_isp_preview_still.dma1_output.width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+		init_val_isp_preview_still.dma1_output.height);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
+		init_val_isp_preview_still.dma1_output.format);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
+		init_val_isp_preview_still.dma1_output.bitwidth);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
+		init_val_isp_preview_still.dma1_output.plane);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
+		init_val_isp_preview_still.dma1_output.order);
+#ifdef DZOOM_EVT0
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+		1);
+	dev->is_p_region->shared[100] = (u32)dev->mem.dvaddr_isp;
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+		(u32)dev->mem.dvaddr_shared + 100*sizeof(u32));
+	dbg("ISP buf daddr : 0x%08x\n", dev->mem.dvaddr_isp);
+	dbg("ISP buf kaddr : 0x%08x\n", dev->mem.kvaddr_isp);
+#else
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+		init_val_isp_preview_still.dma1_output.buffer_number);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+		init_val_isp_preview_still.dma1_output.buffer_address);
+#endif
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_MASK(dev,
+		init_val_isp_preview_still.dma1_output.dma_out_mask);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
+		init_val_isp_preview_still.dma1_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
+		init_val_isp_preview_still.dma2_output.cmd);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+		init_val_isp_preview_still.dma2_output.width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+		init_val_isp_preview_still.dma2_output.height);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
+		init_val_isp_preview_still.dma2_output.format);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
+		init_val_isp_preview_still.dma2_output.bitwidth);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
+		init_val_isp_preview_still.dma2_output.plane);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
+		init_val_isp_preview_still.dma2_output.order);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
+		init_val_isp_preview_still.dma2_output.buffer_number);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
+		init_val_isp_preview_still.dma2_output.buffer_address);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_MASK(dev,
+		init_val_isp_preview_still.dma2_output.dma_out_mask);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
+		init_val_isp_preview_still.dma2_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* DRC */
+	IS_DRC_SET_PARAM_CONTROL_CMD(dev,
+		init_val_drc_preview_still.control.cmd);
+	IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_drc_preview_still.control.bypass);
+	IS_DRC_SET_PARAM_CONTROL_ERR(dev,
+		init_val_drc_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+	IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_drc_preview_still.otf_input.cmd);
+	IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_drc_preview_still.otf_input.width);
+	IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_drc_preview_still.otf_input.height);
+	IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_drc_preview_still.otf_input.format);
+	IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_drc_preview_still.otf_input.bitwidth);
+	IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_drc_preview_still.otf_input.order);
+	IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_drc_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
+		init_val_drc_preview_still.dma_input.cmd);
+	IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+		init_val_drc_preview_still.dma_input.width);
+	IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+		init_val_drc_preview_still.dma_input.height);
+	IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
+		init_val_drc_preview_still.dma_input.format);
+	IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+		init_val_drc_preview_still.dma_input.bitwidth);
+	IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
+		init_val_drc_preview_still.dma_input.plane);
+	IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
+		init_val_drc_preview_still.dma_input.order);
+	IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+		init_val_drc_preview_still.dma_input.buffer_number);
+	IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+		init_val_drc_preview_still.dma_input.buffer_address);
+	IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
+		init_val_drc_preview_still.dma_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_drc_preview_still.otf_output.cmd);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_drc_preview_still.otf_output.width);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_drc_preview_still.otf_output.height);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_drc_preview_still.otf_output.format);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_drc_preview_still.otf_output.bitwidth);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_drc_preview_still.otf_output.order);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_drc_preview_still.otf_output.err);
+	length = init_val_drc_preview_still.otf_output.width*
+			init_val_drc_preview_still.otf_output.height;
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* SCALER-C Macros */
+	IS_SCALERC_SET_PARAM_CONTROL_CMD(dev,
+		init_val_scalerc_preview_still.control.cmd);
+	IS_SCALERC_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_scalerc_preview_still.control.bypass);
+	IS_SCALERC_SET_PARAM_CONTROL_ERR(dev,
+		init_val_scalerc_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_scalerc_preview_still.otf_input.cmd);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_scalerc_preview_still.otf_input.width);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_scalerc_preview_still.otf_input.height);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_scalerc_preview_still.otf_input.format);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_scalerc_preview_still.otf_input.bitwidth);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_scalerc_preview_still.otf_input.order);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_scalerc_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_EFFECT_CMD(dev,
+		init_val_scalerc_preview_still.effect.cmd);
+	IS_SCALERC_SET_PARAM_EFFECT_ERR(dev,
+		init_val_scalerc_preview_still.effect.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_IMAGE_EFFECT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_INPUT_CROP_CMD(dev,
+		init_val_scalerc_preview_still.input_crop.cmd);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev,
+		init_val_scalerc_preview_still.input_crop.pos_x);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev,
+		init_val_scalerc_preview_still.input_crop.pos_y);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev,
+		init_val_scalerc_preview_still.input_crop.crop_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev,
+		init_val_scalerc_preview_still.input_crop.crop_height);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
+		init_val_scalerc_preview_still.input_crop.in_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
+		init_val_scalerc_preview_still.input_crop.in_height);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
+		init_val_scalerc_preview_still.input_crop.out_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
+		init_val_scalerc_preview_still.input_crop.out_height);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_ERR(dev,
+		init_val_scalerc_preview_still.input_crop.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_INPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_CMD(dev,
+		init_val_scalerc_preview_still.output_crop.cmd);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_X(dev,
+		init_val_scalerc_preview_still.output_crop.pos_x);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_Y(dev,
+		init_val_scalerc_preview_still.output_crop.pos_y);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
+		init_val_scalerc_preview_still.output_crop.crop_width);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
+		init_val_scalerc_preview_still.output_crop.crop_height);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROPG_FORMAT(dev,
+		init_val_scalerc_preview_still.output_crop.format);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_ERR(dev,
+		init_val_scalerc_preview_still.output_crop.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OUTPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_scalerc_preview_still.otf_output.cmd);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_scalerc_preview_still.otf_output.width);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_scalerc_preview_still.otf_output.height);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_scalerc_preview_still.otf_output.format);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_scalerc_preview_still.otf_output.bitwidth);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_scalerc_preview_still.otf_output.order);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_scalerc_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(dev,
+		init_val_scalerc_preview_still.dma_output.cmd);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		init_val_scalerc_preview_still.dma_output.width);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		init_val_scalerc_preview_still.dma_output.height);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
+		init_val_scalerc_preview_still.dma_output.format);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
+		init_val_scalerc_preview_still.dma_output.bitwidth);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_PLANE(dev,
+		init_val_scalerc_preview_still.dma_output.plane);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_ORDER(dev,
+		init_val_scalerc_preview_still.dma_output.order);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
+		init_val_scalerc_preview_still.dma_output.buffer_number);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
+		init_val_scalerc_preview_still.dma_output.buffer_address);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_MASK(dev,
+		(0xff&0xffffffff));
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
+		init_val_scalerc_preview_still.dma_output.reserved[0]);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_ERR(dev,
+		init_val_scalerc_preview_still.dma_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* ODC Macros */
+	IS_ODC_SET_PARAM_CONTROL_CMD(dev,
+		init_val_odc_preview_still.control.cmd);
+	IS_ODC_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_odc_preview_still.control.bypass);
+	IS_ODC_SET_PARAM_CONTROL_ERR(dev,
+		init_val_odc_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ODC_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_odc_preview_still.otf_input.cmd);
+	IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_odc_preview_still.otf_input.width);
+	IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_odc_preview_still.otf_input.height);
+	IS_ODC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_odc_preview_still.otf_input.format);
+	IS_ODC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_odc_preview_still.otf_input.bitwidth);
+	IS_ODC_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_odc_preview_still.otf_input.order);
+	IS_ODC_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_odc_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ODC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_odc_preview_still.otf_output.cmd);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_odc_preview_still.otf_output.width);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_odc_preview_still.otf_output.height);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_odc_preview_still.otf_output.format);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_odc_preview_still.otf_output.bitwidth);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_odc_preview_still.otf_output.order);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_odc_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* DIS Macros */
+	IS_DIS_SET_PARAM_CONTROL_CMD(dev,
+		init_val_dis_preview_still.control.cmd);
+	IS_DIS_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_dis_preview_still.control.bypass);
+	IS_DIS_SET_PARAM_CONTROL_ERR(dev,
+		init_val_dis_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DIS_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_dis_preview_still.otf_input.cmd);
+	IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_dis_preview_still.otf_input.width);
+	IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_dis_preview_still.otf_input.height);
+	IS_DIS_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_dis_preview_still.otf_input.format);
+	IS_DIS_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_dis_preview_still.otf_input.bitwidth);
+	IS_DIS_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_dis_preview_still.otf_input.order);
+	IS_DIS_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_dis_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DIS_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_dis_preview_still.otf_output.cmd);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_dis_preview_still.otf_output.width);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_dis_preview_still.otf_output.height);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_dis_preview_still.otf_output.format);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_dis_preview_still.otf_output.bitwidth);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_dis_preview_still.otf_output.order);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_dis_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* TDNR Macros */
+	IS_TDNR_SET_PARAM_CONTROL_CMD(dev,
+		init_val_tdnr_preview_still.control.cmd);
+	IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_tdnr_preview_still.control.bypass);
+	IS_TDNR_SET_PARAM_CONTROL_ERR(dev,
+		init_val_tdnr_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_tdnr_preview_still.otf_input.cmd);
+	IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_tdnr_preview_still.otf_input.width);
+	IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_tdnr_preview_still.otf_input.height);
+	IS_TDNR_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_tdnr_preview_still.otf_input.format);
+	IS_TDNR_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_tdnr_preview_still.otf_input.bitwidth);
+	IS_TDNR_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_tdnr_preview_still.otf_input.order);
+	IS_TDNR_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_tdnr_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_FRAME_CMD(dev,
+		init_val_tdnr_preview_still.frame.cmd);
+	IS_TDNR_SET_PARAM_FRAME_ERR(dev,
+		init_val_tdnr_preview_still.frame.err);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_1ST_FRAME);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_tdnr_preview_still.otf_output.cmd);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_tdnr_preview_still.otf_output.width);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_tdnr_preview_still.otf_output.height);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_tdnr_preview_still.otf_output.format);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_tdnr_preview_still.otf_output.bitwidth);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_tdnr_preview_still.otf_output.order);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_tdnr_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(dev,
+		init_val_tdnr_preview_still.dma_output.cmd);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		init_val_tdnr_preview_still.dma_output.width);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		init_val_tdnr_preview_still.dma_output.height);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
+		init_val_tdnr_preview_still.dma_output.format);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
+		init_val_tdnr_preview_still.dma_output.bitwidth);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_PLANE(dev,
+		init_val_tdnr_preview_still.dma_output.plane);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_ORDER(dev,
+		init_val_tdnr_preview_still.dma_output.order);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
+		init_val_tdnr_preview_still.dma_output.buffer_number);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
+		init_val_tdnr_preview_still.dma_output.buffer_address);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_MASK(dev,
+		(0xff&0xffffffff));
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_ERR(dev,
+		init_val_tdnr_preview_still.dma_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* SCALER-P Macros */
+	IS_SCALERP_SET_PARAM_CONTROL_CMD(dev,
+		init_val_scalerp_preview_still.control.cmd);
+	IS_SCALERP_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_scalerp_preview_still.control.bypass);
+	IS_SCALERP_SET_PARAM_CONTROL_ERR(dev,
+		init_val_scalerp_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_scalerp_preview_still.otf_input.cmd);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_scalerp_preview_still.otf_input.width);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_scalerp_preview_still.otf_input.height);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_scalerp_preview_still.otf_input.format);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_scalerp_preview_still.otf_input.bitwidth);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_scalerp_preview_still.otf_input.order);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_scalerp_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_EFFECT_CMD(dev,
+		init_val_scalerp_preview_still.effect.cmd);
+	IS_SCALERP_SET_PARAM_EFFECT_ERR(dev,
+		init_val_scalerp_preview_still.effect.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_IMAGE_EFFECT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_INPUT_CROP_CMD(dev,
+		init_val_scalerp_preview_still.input_crop.cmd);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_POS_X(dev,
+		init_val_scalerp_preview_still.input_crop.pos_x);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_POS_Y(dev,
+		init_val_scalerp_preview_still.input_crop.pos_y);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev,
+		init_val_scalerp_preview_still.input_crop.crop_width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev,
+		init_val_scalerp_preview_still.input_crop.crop_height);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
+		init_val_scalerp_preview_still.input_crop.in_width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
+		init_val_scalerp_preview_still.input_crop.in_height);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
+		init_val_scalerp_preview_still.input_crop.out_width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
+		init_val_scalerp_preview_still.input_crop.out_height);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_ERR(dev,
+		init_val_scalerp_preview_still.input_crop.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_INPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_CMD(dev,
+		init_val_scalerp_preview_still.output_crop.cmd);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_X(dev,
+		init_val_scalerp_preview_still.output_crop.pos_x);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_Y(dev,
+		init_val_scalerp_preview_still.output_crop.pos_y);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
+		init_val_scalerp_preview_still.output_crop.crop_width);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
+		init_val_scalerp_preview_still.output_crop.crop_height);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROPG_FORMAT(dev,
+		init_val_scalerp_preview_still.output_crop.format);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_ERR(dev,
+		init_val_scalerp_preview_still.output_crop.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OUTPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_ROTATION_CMD(dev,
+		init_val_scalerp_preview_still.rotation.cmd);
+	IS_SCALERP_SET_PARAM_ROTATION_ERR(dev,
+		init_val_scalerp_preview_still.rotation.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_ROTATION);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_FLIP_CMD(dev,
+		init_val_scalerp_preview_still.flip.cmd);
+	IS_SCALERP_SET_PARAM_FLIP_ERR(dev,
+		init_val_scalerp_preview_still.flip.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_FLIP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+		init_val_scalerp_preview_still.otf_output.cmd);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		init_val_scalerp_preview_still.otf_output.width);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		init_val_scalerp_preview_still.otf_output.height);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+		init_val_scalerp_preview_still.otf_output.format);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+		init_val_scalerp_preview_still.otf_output.bitwidth);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+		init_val_scalerp_preview_still.otf_output.order);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+		init_val_scalerp_preview_still.otf_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(dev,
+		init_val_scalerp_preview_still.dma_output.cmd);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		init_val_scalerp_preview_still.dma_output.width);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		init_val_scalerp_preview_still.dma_output.height);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_FORMAT(dev,
+		init_val_scalerp_preview_still.dma_output.format);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev,
+		init_val_scalerp_preview_still.dma_output.bitwidth);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_PLANE(dev,
+		init_val_scalerp_preview_still.dma_output.plane);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_ORDER(dev,
+		init_val_scalerp_preview_still.dma_output.order);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev,
+		init_val_scalerp_preview_still.dma_output.buffer_number);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev,
+		init_val_scalerp_preview_still.dma_output.buffer_address);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_MASK(dev,
+		(0xff&0xffffffff));
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_ERR(dev,
+		init_val_scalerp_preview_still.dma_output.err);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* FD */
+	IS_FD_SET_PARAM_CONTROL_CMD(dev,
+		init_val_fd_preview_still.control.cmd);
+	IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
+		init_val_fd_preview_still.control.bypass);
+	IS_FD_SET_PARAM_CONTROL_ERR(dev,
+		init_val_fd_preview_still.control.err);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+	IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
+		init_val_fd_preview_still.otf_input.cmd);
+	IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		init_val_fd_preview_still.otf_input.width);
+	IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		init_val_fd_preview_still.otf_input.height);
+	IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
+		init_val_fd_preview_still.otf_input.format);
+	IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+		init_val_fd_preview_still.otf_input.bitwidth);
+	IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
+		init_val_fd_preview_still.otf_input.order);
+	IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
+		init_val_fd_preview_still.otf_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
+		init_val_fd_preview_still.dma_input.cmd);
+	IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
+		init_val_fd_preview_still.dma_input.width);
+	IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+		init_val_fd_preview_still.dma_input.height);
+	IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
+		init_val_fd_preview_still.dma_input.format);
+	IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+		init_val_fd_preview_still.dma_input.bitwidth);
+	IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
+		init_val_fd_preview_still.dma_input.plane);
+	IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
+		init_val_fd_preview_still.dma_input.order);
+	IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+		init_val_fd_preview_still.dma_input.buffer_number);
+	IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+		init_val_fd_preview_still.dma_input.buffer_address);
+	IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
+		init_val_fd_preview_still.dma_input.err);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+		init_val_fd_preview_still.config.cmd);
+	IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
+		init_val_fd_preview_still.config.max_number);
+	IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
+		init_val_fd_preview_still.config.roll_angle);
+	IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
+		init_val_fd_preview_still.config.yaw_angle);
+	IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
+		init_val_fd_preview_still.config.smile_mode);
+	IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
+		init_val_fd_preview_still.config.blink_mode);
+	IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
+		init_val_fd_preview_still.config.eye_detect);
+	IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
+		init_val_fd_preview_still.config.mouth_detect);
+	IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
+		init_val_fd_preview_still.config.orientation);
+	IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
+		init_val_fd_preview_still.config.orientation_value);
+	IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
+		init_val_fd_preview_still.config.err);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+	IS_INC_PARAM_NUM(dev);
+}
+
+int fimc_is_hw_change_size(struct fimc_is_dev *dev)
+{
+	u32 front_width, front_height, back_width, back_height;
+	u32 dis_width, dis_height;
+	u32 crop_width = 0, crop_height = 0, crop_x = 0, crop_y = 0;
+	u32 front_crop_ratio, back_crop_ratio;
+
+	/* ISP */
+	IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* DRC */
+	IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* ScalerC */
+	front_width = dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width;
+	front_height = dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height;
+
+	back_width = dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width;
+	back_height = dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height;
+
+	IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		front_width);
+	IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		front_height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
+		front_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
+		front_height);
+
+	front_crop_ratio = front_width * 1000 / front_height;
+	back_crop_ratio = back_width * 1000 / back_height;
+
+	if (front_crop_ratio == back_crop_ratio) {
+		crop_width = front_width;
+		crop_height = front_height;
+
+	} else if (front_crop_ratio < back_crop_ratio) {
+		crop_width = front_width;
+		crop_height = (front_width
+				* (1000 * 100 / back_crop_ratio)) / 100;
+		crop_width = ALIGN(crop_width, 8);
+		crop_height = ALIGN(crop_height, 8);
+
+	} else if (front_crop_ratio > back_crop_ratio) {
+		crop_height = front_height;
+		crop_width = (front_height
+				* (back_crop_ratio * 100 / 1000)) / 100 ;
+		crop_width = ALIGN(crop_width, 8);
+		crop_height = ALIGN(crop_height, 8);
+	}
+
+	if (dev->back.dis_on) {
+		dis_width = back_width * 125 / 100;
+		dis_height = back_height * 125 / 100;
+	} else {
+		dis_width = back_width;
+		dis_height = back_height;
+	}
+
+	IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
+		crop_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
+		crop_height);
+
+	dbg("calulate crop size\n");
+	dbg("front w: %d front h: %d\n", front_width, front_height);
+	dbg("dis w: %d dis h: %d\n", dis_width, dis_height);
+	dbg("back w: %d back h: %d\n", back_width, back_height);
+
+	dbg("front_crop_ratio: %d back_crop_ratio: %d\n",
+			front_crop_ratio, back_crop_ratio);
+
+	crop_x = (front_width - crop_width) / 2;
+	crop_y = (front_height - crop_height) / 2;
+	crop_x &= 0xffe;
+	crop_y &= 0xffe;
+
+	dev->sensor.width = front_width;
+	dev->sensor.height = front_height;
+	dev->front.width = front_width;
+	dev->front.height = front_height;
+	dev->back.width = back_width;
+	dev->back.height = back_height;
+	dev->back.dis_width = dis_width;
+	dev->back.dis_height = dis_height;
+
+	dbg("crop w: %d crop h: %d\n", crop_width, crop_height);
+	dbg("crop x: %d crop y: %d\n", crop_x, crop_y);
+
+	IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev,
+		crop_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev,
+		crop_height);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev,
+		crop_x);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev,
+		crop_y);
+
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_INPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
+		dis_width);
+	IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
+		dis_height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OUTPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		dis_width);
+	IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		dis_height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		front_width);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		front_height);
+	if((front_width != dis_width) || (front_height != dis_height))
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
+			2);  /* unscaled image */
+	else
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev,
+			1); /* scaled image */
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* ODC */
+	IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		dis_width);
+	IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		dis_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		dis_width);
+	IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		dis_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* DIS */
+	IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		dis_width);
+	IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		dis_height);
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		back_width);
+	IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		back_height);
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* 3DNR */
+	IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		back_width);
+	IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		back_height);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		back_width);
+	IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		back_height);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		back_width);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		back_height);
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* ScalerP */
+	IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		back_width);
+	IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		back_height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev,
+		back_width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev,
+		back_height);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev,
+		back_width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev,
+		back_height);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
+	IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_INPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
+	IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OUTPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
+	IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERP_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	/* FD */
+	IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width);
+	IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	return 0;
+}
+
+void fimc_is_hw_set_default_size(struct fimc_is_dev *dev, int  sensor_id)
+{
+	switch (sensor_id) {
+	case SENSOR_NAME_S5K6A3:
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
+			DEFAULT_6A3_STILLSHOT_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
+			DEFAULT_6A3_STILLSHOT_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
+			DEFAULT_6A3_PREVIEW_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
+			DEFAULT_6A3_PREVIEW_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
+			DEFAULT_6A3_VIDEO_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
+			DEFAULT_6A3_VIDEO_HEIGHT;
+		break;
+	case SENSOR_NAME_S5K4E5:
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
+			DEFAULT_4E5_STILLSHOT_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
+			DEFAULT_4E5_STILLSHOT_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
+			DEFAULT_4E5_PREVIEW_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
+			DEFAULT_4E5_PREVIEW_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
+			DEFAULT_4E5_VIDEO_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
+			DEFAULT_4E5_VIDEO_HEIGHT;
+		break;
+	default:
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width =
+			DEFAULT_CAPTURE_STILL_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height =
+			DEFAULT_CAPTURE_STILL_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width =
+			DEFAULT_PREVIEW_STILL_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height =
+			DEFAULT_PREVIEW_STILL_HEIGHT;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width =
+			DEFAULT_CAPTURE_VIDEO_WIDTH;
+		dev->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height =
+			DEFAULT_CAPTURE_VIDEO_HEIGHT;
+		break;
+	}
+}
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.h
new file mode 100644
index 0000000..906da02
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-helper.h
@@ -0,0 +1,81 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_HELPER_H
+#define FIMC_IS_HELPER_H
+
+#include "fimc-is-core.h"
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH		(1280) /* sensor margin : 16 */
+#define DEFAULT_PREVIEW_STILL_HEIGHT		(720) /* sensor margin : 12 */
+#define DEFAULT_CAPTURE_VIDEO_WIDTH		(1920)
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT		(1080)
+#define DEFAULT_CAPTURE_STILL_WIDTH		(2560)
+#define DEFAULT_CAPTURE_STILL_HEIGHT		(1920)
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH	(2560)
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT	(1440)
+#define DEFAULT_PREVIEW_VIDEO_WIDTH		(640)
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT		(480)
+
+#define DEFAULT_4E5_PREVIEW_WIDTH		(1920)	/* sensor margin : 16 */
+#define DEFAULT_4E5_PREVIEW_HEIGHT		(1080)	/* sensor margin : 12 */
+#define DEFAULT_4E5_VIDEO_WIDTH			(1920)
+#define DEFAULT_4E5_VIDEO_HEIGHT		(1080)
+#define DEFAULT_4E5_STILLSHOT_WIDTH		(2560)
+#define DEFAULT_4E5_STILLSHOT_HEIGHT		(1920)
+
+#define DEFAULT_6A3_PREVIEW_WIDTH		(1280)	/* sensor margin : 16 */
+#define DEFAULT_6A3_PREVIEW_HEIGHT		(720)	/* sensor margin : 12 */
+#define DEFAULT_6A3_VIDEO_WIDTH			(1280)
+#define DEFAULT_6A3_VIDEO_HEIGHT		(720)
+#define DEFAULT_6A3_STILLSHOT_WIDTH		(1280)
+#define DEFAULT_6A3_STILLSHOT_HEIGHT		(720)
+
+#define DEFAULT_PREVIEW_STILL_FRAMERATE		(30)
+#define DEFAULT_CAPTURE_STILL_FRAMERATE		(15)
+#define DEFAULT_PREVIEW_VIDEO_FRAMERATE		(30)
+#define DEFAULT_CAPTURE_VIDEO_FRAMERATE		(30)
+
+int  fimc_is_fw_clear_irq2(struct fimc_is_dev *dev);
+int  fimc_is_fw_clear_irq1_all(struct fimc_is_dev *dev);
+int  fimc_is_fw_clear_irq1(struct fimc_is_dev *dev, unsigned int intr_pos);
+void fimc_is_hw_set_sensor_num(struct fimc_is_dev *dev);
+void fimc_is_hw_get_setfile_addr(struct fimc_is_dev *dev);
+void fimc_is_hw_load_setfile(struct fimc_is_dev *dev);
+int  fimc_is_hw_get_sensor_num(struct fimc_is_dev *dev);
+int  fimc_is_hw_set_param(struct fimc_is_dev *dev);
+int  fimc_is_hw_update_bufmask(struct fimc_is_dev *dev, unsigned int dev_num);
+int  fimc_is_hw_get_param(struct fimc_is_dev *dev, u16 offset);
+void fimc_is_hw_set_intgr0_gd0(struct fimc_is_dev *dev);
+int  fimc_is_hw_wait_intsr0_intsd0(struct fimc_is_dev *dev);
+int  fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is_dev *dev);
+void fimc_is_hw_a5_power(struct fimc_is_dev *dev, int on);
+int  fimc_is_hw_a5_power_on(struct fimc_is_dev *dev);
+int  fimc_is_hw_a5_power_off(struct fimc_is_dev *dev);
+void fimc_is_hw_open_sensor(struct fimc_is_dev *dev, u32 id, u32 sensor_index);
+void fimc_is_hw_set_stream(struct fimc_is_dev *dev, int on);
+void fimc_is_hw_set_debug_level(struct fimc_is_dev *dev,
+				int target, int module, int level);
+void fimc_is_hw_set_init(struct fimc_is_dev *dev);
+void fimc_is_hw_change_mode(struct fimc_is_dev *dev, int val);
+void fimc_is_hw_set_lite(struct fimc_is_dev *dev, u32 width, u32 height);
+void fimc_is_hw_diable_wdt(struct fimc_is_dev *dev);
+void fimc_is_hw_set_low_poweroff(struct fimc_is_dev *dev, int on);
+void fimc_is_hw_subip_poweroff(struct fimc_is_dev *dev);
+int  fimc_is_fw_clear_insr1(struct fimc_is_dev *dev);
+int  fimc_is_hw_get_sensor_type(enum exynos5_sensor_id sensor_id,
+				enum exynos5_flite_id flite_id);
+int  fimc_is_hw_get_sensor_max_framerate(struct fimc_is_dev *dev);
+int  fimc_is_hw_change_size(struct fimc_is_dev *dev);
+void fimc_is_hw_set_default_size(struct fimc_is_dev *dev, int  sensor_id);
+#endif
+
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.c b/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.c
new file mode 100644
index 0000000..773a2ba
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.c
@@ -0,0 +1,3319 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * exynos5 fimc-is misc functions(mipi, fimc-lite control)
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <linux/jiffies.h>
+
+#include <media/v4l2-subdev.h>
+#include <media/exynos_fimc_is.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-helper.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-err.h"
+#include "fimc-is-misc.h"
+
+/* PMU for FIMC-IS*/
+#define FIMCLITE0_REG_BASE	(S5P_VA_FIMCLITE0)  /* phy : 0x13c0_0000 */
+#define FIMCLITE1_REG_BASE	(S5P_VA_FIMCLITE1)  /* phy : 0x13c1_0000 */
+#define MIPICSI0_REG_BASE	(S5P_VA_MIPICSI0)   /* phy : 0x13c2_0000 */
+#define MIPICSI1_REG_BASE	(S5P_VA_MIPICSI1)   /* phy : 0x13c3_0000 */
+#define FIMCLITE2_REG_BASE	(S5P_VA_FIMCLITE2)  /* phy : 0x13c9_0000 */
+
+#define FLITE_MAX_RESET_READY_TIME	(20) /* 100ms */
+#define FLITE_MAX_WIDTH_SIZE		(8192)
+#define FLITE_MAX_HEIGHT_SIZE		(8192)
+
+
+/*FIMCLite*/
+/* Camera Source size */
+#define FLITE_REG_CISRCSIZE				(0x00)
+#define FLITE_REG_CISRCSIZE_SIZE_H(x)			((x) << 16)
+#define FLITE_REG_CISRCSIZE_SIZE_V(x)			((x) << 0)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR		(0 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB		(1 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY		(2 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY		(3 << 14)
+
+/* Global control */
+#define FLITE_REG_CIGCTRL				0x04
+#define FLITE_REG_CIGCTRL_YUV422_1P			(0x1E << 24)
+#define FLITE_REG_CIGCTRL_RAW8				(0x2A << 24)
+#define FLITE_REG_CIGCTRL_RAW10				(0x2B << 24)
+#define FLITE_REG_CIGCTRL_RAW12				(0x2C << 24)
+#define FLITE_REG_CIGCTRL_RAW14				(0x2D << 24)
+
+/* User defined formats. x = 0...0xF. */
+#define FLITE_REG_CIGCTRL_USER(x)			(0x30 + x - 1)
+#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE		(1 << 21)
+#define FLITE_REG_CIGCTRL_ODMA_DISABLE			(1 << 20)
+#define FLITE_REG_CIGCTRL_SWRST_REQ			(1 << 19)
+#define FLITE_REG_CIGCTRL_SWRST_RDY			(1 << 18)
+#define FLITE_REG_CIGCTRL_SWRST				(1 << 17)
+#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR		(1 << 15)
+#define FLITE_REG_CIGCTRL_INVPOLPCLK			(1 << 14)
+#define FLITE_REG_CIGCTRL_INVPOLVSYNC			(1 << 13)
+#define FLITE_REG_CIGCTRL_INVPOLHREF			(1 << 12)
+#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE		(0 << 8)
+#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_DISABLE		(1 << 8)
+#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_ENABLE		(0 << 7)
+#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_DISABLE		(1 << 7)
+#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_ENABLE		(0 << 6)
+#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE		(1 << 6)
+#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_ENABLE		(0 << 5)
+#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_DISABLE		(1 << 5)
+#define FLITE_REG_CIGCTRL_SELCAM_MIPI			(1 << 3)
+
+/* Image Capture Enable */
+#define FLITE_REG_CIIMGCPT				(0x08)
+#define FLITE_REG_CIIMGCPT_IMGCPTEN			(1 << 31)
+#define FLITE_REG_CIIMGCPT_CPT_FREN			(1 << 25)
+#define FLITE_REG_CIIMGCPT_CPT_FRPTR(x)			((x) << 19)
+#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT		(1 << 18)
+#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN			(0 << 18)
+#define FLITE_REG_CIIMGCPT_CPT_FRCNT(x)			((x) << 10)
+
+/* Capture Sequence */
+#define FLITE_REG_CICPTSEQ				(0x0C)
+#define FLITE_REG_CPT_FRSEQ(x)				((x) << 0)
+
+/* Camera Window Offset */
+#define FLITE_REG_CIWDOFST				(0x10)
+#define FLITE_REG_CIWDOFST_WINOFSEN			(1 << 31)
+#define FLITE_REG_CIWDOFST_CLROVIY			(1 << 31)
+#define FLITE_REG_CIWDOFST_WINHOROFST(x)		((x) << 16)
+#define FLITE_REG_CIWDOFST_HOROFF_MASK			(0x1fff << 16)
+#define FLITE_REG_CIWDOFST_CLROVFICB			(1 << 15)
+#define FLITE_REG_CIWDOFST_CLROVFICR			(1 << 14)
+#define FLITE_REG_CIWDOFST_WINVEROFST(x)		((x) << 0)
+#define FLITE_REG_CIWDOFST_VEROFF_MASK			(0x1fff << 0)
+
+/* Cmaera Window Offset2 */
+#define FLITE_REG_CIWDOFST2				(0x14)
+#define FLITE_REG_CIWDOFST2_WINHOROFST2(x)		((x) << 16)
+#define FLITE_REG_CIWDOFST2_WINVEROFST2(x)		((x) << 0)
+
+/* Camera Output DMA Format */
+#define FLITE_REG_CIODMAFMT				(0x18)
+#define FLITE_REG_CIODMAFMT_1D_DMA			(1 << 15)
+#define FLITE_REG_CIODMAFMT_2D_DMA			(0 << 15)
+#define FLITE_REG_CIODMAFMT_PACK12			(1 << 14)
+#define FLITE_REG_CIODMAFMT_NORMAL			(0 << 14)
+#define FLITE_REG_CIODMAFMT_CRYCBY			(0 << 4)
+#define FLITE_REG_CIODMAFMT_CBYCRY			(1 << 4)
+#define FLITE_REG_CIODMAFMT_YCRYCB			(2 << 4)
+#define FLITE_REG_CIODMAFMT_YCBYCR			(3 << 4)
+
+/* Camera Output Canvas */
+#define FLITE_REG_CIOCAN				(0x20)
+#define FLITE_REG_CIOCAN_OCAN_V(x)			((x) << 16)
+#define FLITE_REG_CIOCAN_OCAN_H(x)			((x) << 0)
+
+/* Camera Output DMA Offset */
+#define FLITE_REG_CIOOFF				(0x24)
+#define FLITE_REG_CIOOFF_OOFF_V(x)			((x) << 16)
+#define FLITE_REG_CIOOFF_OOFF_H(x)			((x) << 0)
+
+/* Camera Output DMA Address */
+#define FLITE_REG_CIOSA					(0x30)
+#define FLITE_REG_CIOSA_OSA(x)				((x) << 0)
+
+/* Camera Status */
+#define FLITE_REG_CISTATUS				(0x40)
+#define FLITE_REG_CISTATUS_MIPI_VVALID			(1 << 22)
+#define FLITE_REG_CISTATUS_MIPI_HVALID			(1 << 21)
+#define FLITE_REG_CISTATUS_MIPI_DVALID			(1 << 20)
+#define FLITE_REG_CISTATUS_ITU_VSYNC			(1 << 14)
+#define FLITE_REG_CISTATUS_ITU_HREFF			(1 << 13)
+#define FLITE_REG_CISTATUS_OVFIY			(1 << 10)
+#define FLITE_REG_CISTATUS_OVFICB			(1 << 9)
+#define FLITE_REG_CISTATUS_OVFICR			(1 << 8)
+#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW		(1 << 7)
+#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND		(1 << 6)
+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART		(1 << 5)
+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND		(1 << 4)
+#define FLITE_REG_CISTATUS_IRQ_CAM			(1 << 0)
+#define FLITE_REG_CISTATUS_IRQ_MASK			(0xf << 4)
+
+/* Camera Status2 */
+#define FLITE_REG_CISTATUS2				(0x44)
+#define FLITE_REG_CISTATUS2_LASTCAPEND			(1 << 1)
+#define FLITE_REG_CISTATUS2_FRMEND			(1 << 0)
+
+/* Qos Threshold */
+#define FLITE_REG_CITHOLD				(0xF0)
+#define FLITE_REG_CITHOLD_W_QOS_EN			(1 << 30)
+#define FLITE_REG_CITHOLD_WTH_QOS(x)			((x) << 0)
+
+/* Camera General Purpose */
+#define FLITE_REG_CIGENERAL				(0xFC)
+#define FLITE_REG_CIGENERAL_CAM_A			(0 << 0)
+#define FLITE_REG_CIGENERAL_CAM_B			(1 << 0)
+
+
+/*MIPI*/
+/* CSIS global control */
+#define S5PCSIS_CTRL					(0x00)
+#define S5PCSIS_CTRL_DPDN_DEFAULT			(0 << 31)
+#define S5PCSIS_CTRL_DPDN_SWAP				(1 << 31)
+#define S5PCSIS_CTRL_ALIGN_32BIT			(1 << 20)
+#define S5PCSIS_CTRL_UPDATE_SHADOW			(1 << 16)
+#define S5PCSIS_CTRL_WCLK_EXTCLK			(1 << 8)
+#define S5PCSIS_CTRL_RESET				(1 << 4)
+#define S5PCSIS_CTRL_ENABLE				(1 << 0)
+
+/* D-PHY control */
+#define S5PCSIS_DPHYCTRL				(0x04)
+#define S5PCSIS_DPHYCTRL_HSS_MASK			(0x1f << 27)
+#define S5PCSIS_DPHYCTRL_ENABLE				(0x7 << 0)
+
+#define S5PCSIS_CONFIG					(0x08)
+#define S5PCSIS_CFG_FMT_YCBCR422_8BIT			(0x1e << 2)
+#define S5PCSIS_CFG_FMT_RAW8				(0x2a << 2)
+#define S5PCSIS_CFG_FMT_RAW10				(0x2b << 2)
+#define S5PCSIS_CFG_FMT_RAW12				(0x2c << 2)
+/* User defined formats, x = 1...4 */
+#define S5PCSIS_CFG_FMT_USER(x)				((0x30 + x - 1) << 2)
+#define S5PCSIS_CFG_FMT_MASK				(0x3f << 2)
+#define S5PCSIS_CFG_NR_LANE_MASK			(3)
+
+/* Interrupt mask. */
+#define S5PCSIS_INTMSK					(0x10)
+#define S5PCSIS_INTMSK_EN_ALL				(0xfc00103f)
+#define S5PCSIS_INTSRC					(0x14)
+
+/* Pixel resolution */
+#define S5PCSIS_RESOL					(0x2c)
+#define CSIS_MAX_PIX_WIDTH				(0xffff)
+#define CSIS_MAX_PIX_HEIGHT				(0xffff)
+
+static void flite_hw_set_cam_source_size(unsigned long flite_reg_base,
+					struct flite_frame *f_frame)
+{
+	u32 cfg = 0;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CISRCSIZE);
+
+	cfg |= FLITE_REG_CISRCSIZE_SIZE_H(f_frame->o_width);
+	cfg |= FLITE_REG_CISRCSIZE_SIZE_V(f_frame->o_height);
+
+	writel(cfg, flite_reg_base + FLITE_REG_CISRCSIZE);
+
+	cfg = readl(flite_reg_base + FLITE_REG_CIOCAN);
+	cfg |= FLITE_REG_CIOCAN_OCAN_H(f_frame->o_width);
+	cfg |= FLITE_REG_CIOCAN_OCAN_V(f_frame->o_height);
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIOCAN);
+}
+
+static void flite_hw_set_cam_channel(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+
+	if (flite_reg_base == (unsigned long)FIMCLITE0_REG_BASE) {
+		cfg = FLITE_REG_CIGENERAL_CAM_A;
+		writel(cfg, FIMCLITE0_REG_BASE + FLITE_REG_CIGENERAL);
+		writel(cfg, FIMCLITE1_REG_BASE + FLITE_REG_CIGENERAL);
+		writel(cfg, FIMCLITE2_REG_BASE + FLITE_REG_CIGENERAL);
+	} else {
+		cfg = FLITE_REG_CIGENERAL_CAM_B;
+		writel(cfg, FIMCLITE0_REG_BASE + FLITE_REG_CIGENERAL);
+		writel(cfg, FIMCLITE1_REG_BASE + FLITE_REG_CIGENERAL);
+		writel(cfg, FIMCLITE2_REG_BASE + FLITE_REG_CIGENERAL);
+	}
+}
+
+static void flite_hw_set_capture_start(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CIIMGCPT);
+	cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIIMGCPT);
+}
+
+static void flite_hw_set_capture_stop(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CIIMGCPT);
+	cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIIMGCPT);
+}
+
+static int flite_hw_set_source_format(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_RAW10;
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+
+	return 0;
+}
+
+static void flite_hw_set_output_dma(unsigned long flite_reg_base, bool enable)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+
+	if (enable)
+		cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE;
+	else
+		cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+
+/* will use for pattern generation testing
+static void flite_hw_set_test_pattern_enable(void)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+*/
+
+static void flite_hw_set_config_irq(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+	cfg &= ~(FLITE_REG_CIGCTRL_INVPOLPCLK | FLITE_REG_CIGCTRL_INVPOLVSYNC
+			| FLITE_REG_CIGCTRL_INVPOLHREF);
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+
+static void flite_hw_set_interrupt_source(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+
+static void flite_hw_set_interrupt_starten0_disable
+					(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+
+static void flite_hw_set_camera_type(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+	cfg = readl(flite_reg_base + FLITE_REG_CIGCTRL);
+
+	cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIGCTRL);
+}
+
+static void flite_hw_set_window_offset(unsigned long flite_reg_base,
+					struct flite_frame *f_frame)
+{
+	u32 cfg = 0;
+	u32 hoff2, voff2;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CIWDOFST);
+	cfg &= ~(FLITE_REG_CIWDOFST_HOROFF_MASK |
+		FLITE_REG_CIWDOFST_VEROFF_MASK);
+	cfg |= FLITE_REG_CIWDOFST_WINOFSEN |
+		FLITE_REG_CIWDOFST_WINHOROFST(f_frame->offs_h) |
+		FLITE_REG_CIWDOFST_WINVEROFST(f_frame->offs_v);
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIWDOFST);
+
+	hoff2 = f_frame->o_width - f_frame->width - f_frame->offs_h;
+	voff2 = f_frame->o_height - f_frame->height - f_frame->offs_v;
+	cfg = FLITE_REG_CIWDOFST2_WINHOROFST2(hoff2) |
+		FLITE_REG_CIWDOFST2_WINVEROFST2(voff2);
+
+	writel(cfg, flite_reg_base + FLITE_REG_CIWDOFST2);
+}
+
+static void flite_hw_set_last_capture_end_clear(unsigned long flite_reg_base)
+{
+	u32 cfg = 0;
+
+	cfg = readl(flite_reg_base + FLITE_REG_CISTATUS2);
+	cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;
+
+	writel(cfg, flite_reg_base + FLITE_REG_CISTATUS2);
+}
+
+static void s5pcsis_enable_interrupts(unsigned long mipi_reg_base, bool on)
+{
+	u32 val = readl(mipi_reg_base + S5PCSIS_INTMSK);
+
+	val = on ? val | S5PCSIS_INTMSK_EN_ALL :
+		   val & ~S5PCSIS_INTMSK_EN_ALL;
+	writel(val, mipi_reg_base + S5PCSIS_INTMSK);
+}
+
+static void s5pcsis_reset(unsigned long mipi_reg_base)
+{
+	u32 val = readl(mipi_reg_base + S5PCSIS_CTRL);
+
+	writel(val | S5PCSIS_CTRL_RESET, mipi_reg_base + S5PCSIS_CTRL);
+	udelay(10);
+}
+
+static void s5pcsis_system_enable(unsigned long mipi_reg_base, int on)
+{
+	u32 val;
+
+	val = readl(mipi_reg_base + S5PCSIS_CTRL);
+	if (on) {
+		val |= S5PCSIS_CTRL_ENABLE;
+		val |= S5PCSIS_CTRL_WCLK_EXTCLK;
+	} else
+		val &= ~S5PCSIS_CTRL_ENABLE;
+	writel(val, mipi_reg_base + S5PCSIS_CTRL);
+
+	val = readl(mipi_reg_base + S5PCSIS_DPHYCTRL);
+	if (on)
+		val |= S5PCSIS_DPHYCTRL_ENABLE;
+	else
+		val &= ~S5PCSIS_DPHYCTRL_ENABLE;
+	writel(val, mipi_reg_base + S5PCSIS_DPHYCTRL);
+}
+
+/* Called with the state.lock mutex held */
+static void __s5pcsis_set_format(unsigned long mipi_reg_base,
+				struct flite_frame *f_frame)
+{
+	u32 val;
+
+	/* Color format */
+	val = readl(mipi_reg_base + S5PCSIS_CONFIG);
+	val = (val & ~S5PCSIS_CFG_FMT_MASK) | S5PCSIS_CFG_FMT_RAW10;
+	writel(val, mipi_reg_base + S5PCSIS_CONFIG);
+
+	/* Pixel resolution */
+	val = (f_frame->o_width << 16) | f_frame->o_height;
+	writel(val, mipi_reg_base + S5PCSIS_RESOL);
+}
+
+static void s5pcsis_set_hsync_settle(unsigned long mipi_reg_base)
+{
+	u32 val = readl(mipi_reg_base + S5PCSIS_DPHYCTRL);
+
+	val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (0x6 << 28);
+	writel(val, mipi_reg_base + S5PCSIS_DPHYCTRL);
+}
+
+static void s5pcsis_set_params(unsigned long mipi_reg_base,
+				struct flite_frame *f_frame)
+{
+	u32 val;
+
+	val = readl(mipi_reg_base + S5PCSIS_CONFIG);
+	val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (2 - 1);
+	writel(val, mipi_reg_base + S5PCSIS_CONFIG);
+
+	__s5pcsis_set_format(mipi_reg_base, f_frame);
+	s5pcsis_set_hsync_settle(mipi_reg_base);
+
+	val = readl(mipi_reg_base + S5PCSIS_CTRL);
+	val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
+
+	/* Not using external clock. */
+	val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
+
+	writel(val, mipi_reg_base + S5PCSIS_CTRL);
+
+	/* Update the shadow register. */
+	val = readl(mipi_reg_base + S5PCSIS_CTRL);
+	writel(val | S5PCSIS_CTRL_UPDATE_SHADOW, mipi_reg_base + S5PCSIS_CTRL);
+}
+
+int start_fimc_lite(int channel, struct flite_frame *f_frame)
+{
+	unsigned long base_reg = (unsigned long)FIMCLITE0_REG_BASE;
+
+	if (channel == FLITE_ID_A)
+		base_reg = (unsigned long)FIMCLITE0_REG_BASE;
+	else if (channel == FLITE_ID_B)
+		base_reg = (unsigned long)FIMCLITE1_REG_BASE;
+
+	flite_hw_set_cam_channel(base_reg);
+	flite_hw_set_cam_source_size(base_reg, f_frame);
+	flite_hw_set_camera_type(base_reg);
+	flite_hw_set_source_format(base_reg);
+	flite_hw_set_output_dma(base_reg, false);
+
+	flite_hw_set_interrupt_source(base_reg);
+	flite_hw_set_interrupt_starten0_disable(base_reg);
+	flite_hw_set_config_irq(base_reg);
+	flite_hw_set_window_offset(base_reg, f_frame);
+	/* flite_hw_set_test_pattern_enable(); */
+
+	flite_hw_set_last_capture_end_clear(base_reg);
+	flite_hw_set_capture_start(base_reg);
+
+	return 0;
+}
+
+int stop_fimc_lite(int channel)
+{
+	unsigned long base_reg = (unsigned long)FIMCLITE0_REG_BASE;
+
+	if (channel == FLITE_ID_A)
+		base_reg = (unsigned long)FIMCLITE0_REG_BASE;
+	else if (channel == FLITE_ID_B)
+		base_reg = (unsigned long)FIMCLITE1_REG_BASE;
+
+	flite_hw_set_capture_stop(base_reg);
+	return 0;
+}
+
+int enable_mipi(void)
+{
+	void __iomem *addr;
+	u32 cfg;
+
+	addr = S5P_MIPI_DPHY_CONTROL(0);
+
+	cfg = __raw_readl(addr);
+	cfg = (cfg | S5P_MIPI_DPHY_SRESETN);
+	__raw_writel(cfg, addr);
+
+	if (1) {
+		cfg |= S5P_MIPI_DPHY_ENABLE;
+	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | S5P_MIPI_DPHY_MRESETN)
+			& (~S5P_MIPI_DPHY_SRESETN))) {
+		cfg &= ~S5P_MIPI_DPHY_ENABLE;
+	}
+
+	__raw_writel(cfg, addr);
+
+
+	addr = S5P_MIPI_DPHY_CONTROL(1);
+
+	cfg = __raw_readl(addr);
+	cfg = (cfg | S5P_MIPI_DPHY_SRESETN);
+	__raw_writel(cfg, addr);
+
+	if (1) {
+		cfg |= S5P_MIPI_DPHY_ENABLE;
+	} else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | S5P_MIPI_DPHY_MRESETN)
+			& (~S5P_MIPI_DPHY_SRESETN))) {
+		cfg &= ~S5P_MIPI_DPHY_ENABLE;
+	}
+
+	__raw_writel(cfg, addr);
+	return 0;
+
+}
+
+int start_mipi_csi(int channel, struct flite_frame *f_frame)
+{
+	unsigned long base_reg = (unsigned long)MIPICSI0_REG_BASE;
+
+	if (channel == CSI_ID_A)
+		base_reg = (unsigned long)MIPICSI0_REG_BASE;
+	else if (channel == CSI_ID_B)
+		base_reg = (unsigned long)MIPICSI1_REG_BASE;
+
+	s5pcsis_reset(base_reg);
+	s5pcsis_set_params(base_reg, f_frame);
+	s5pcsis_system_enable(base_reg, true);
+	s5pcsis_enable_interrupts(base_reg, true);
+
+	return 0;
+}
+
+int stop_mipi_csi(int channel)
+{
+	unsigned long base_reg = (unsigned long)MIPICSI0_REG_BASE;
+
+	if (channel == CSI_ID_A)
+		base_reg = (unsigned long)MIPICSI0_REG_BASE;
+	else if (channel == CSI_ID_B)
+		base_reg = (unsigned long)MIPICSI1_REG_BASE;
+
+	s5pcsis_enable_interrupts(base_reg, false);
+	s5pcsis_system_enable(base_reg, false);
+
+	return 0;
+}
+
+/*
+* will be move to setting file
+*/
+
+int fimc_is_ctrl_odc(struct fimc_is_dev *dev, int value)
+{
+	int ret;
+
+	if (value == CAMERA_ODC_ON) {
+		/* buffer addr setting */
+		dev->back.odc_on = 1;
+		dev->is_p_region->shared[250] = (u32)dev->mem.dvaddr_odc;
+
+		IS_ODC_SET_PARAM_CONTROL_BUFFERNUM(dev,
+			SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF);
+		IS_ODC_SET_PARAM_CONTROL_BUFFERADDR(dev,
+			(u32)dev->mem.dvaddr_shared + 250 * sizeof(u32));
+		IS_ODC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+
+	} else if (value == CAMERA_ODC_OFF) {
+		dev->back.odc_on = 0;
+		IS_ODC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+	} else {
+		err("invalid ODC setting\n");
+		return -1;
+	}
+
+	if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &dev->state);
+		fimc_is_hw_set_stream(dev, 0); /*stream off */
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			if (!ret)
+				err("s_power off failed!!\n");
+			return -EBUSY;
+		}
+	}
+
+	IS_SET_PARAM_BIT(dev, PARAM_ODC_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+
+	dev->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&dev->state);
+	clear_bit(IS_ST_INIT_CAPTURE_STILL, &dev->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state);
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+
+	if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		fimc_is_hw_change_mode(dev, IS_MODE_PREVIEW_STILL);
+		ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_CHANGE_MODE_DONE, &dev->state),
+				(3*HZ)/*FIMC_IS_SHUTDOWN_TIMEOUT*/);
+
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		clear_bit(IS_ST_STREAM_ON, &dev->state);
+		fimc_is_hw_set_stream(dev, 1);
+
+		ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_STREAM_ON, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+	}
+	clear_bit(IS_ST_STREAM_ON, &dev->state);
+
+	return 0;
+}
+
+int fimc_is_ctrl_dis(struct fimc_is_dev *dev, int value)
+{
+	int ret;
+
+	if (value == CAMERA_DIS_ON) {
+		/* buffer addr setting */
+		dev->back.dis_on = 1;
+		dev->is_p_region->shared[300] = (u32)dev->mem.dvaddr_dis;
+
+		IS_DIS_SET_PARAM_CONTROL_BUFFERNUM(dev,
+			SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF);
+		IS_DIS_SET_PARAM_CONTROL_BUFFERADDR(dev,
+			(u32)dev->mem.dvaddr_shared + 300 * sizeof(u32));
+		IS_DIS_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+	} else if (value == CAMERA_DIS_OFF) {
+		dev->back.dis_on = 0;
+		IS_DIS_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+	} else {
+		err("invalid DIS setting\n");
+		return -1;
+	}
+
+	if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &dev->state);
+		fimc_is_hw_set_stream(dev, 0); /*stream off */
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			if (!ret)
+				err("s_power off failed!!\n");
+			return -EBUSY;
+		}
+	}
+
+	IS_SET_PARAM_BIT(dev, PARAM_DIS_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	fimc_is_hw_change_size(dev);
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+
+	dev->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&dev->state);
+	clear_bit(IS_ST_INIT_CAPTURE_STILL, &dev->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state);
+	fimc_is_hw_set_param(dev);
+#ifdef DIS_ENABLE
+	/* FW bug - should be wait */
+	ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"set param wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+#endif
+
+	if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+		clear_bit(IS_ST_RUN, &dev->state);
+		set_bit(IS_ST_CHANGE_MODE, &dev->state);
+		fimc_is_hw_change_mode(dev, IS_MODE_PREVIEW_STILL);
+		ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_CHANGE_MODE_DONE, &dev->state),
+				(3*HZ)/*FIMC_IS_SHUTDOWN_TIMEOUT*/);
+
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		clear_bit(IS_ST_STREAM_ON, &dev->state);
+		fimc_is_hw_set_stream(dev, 1);
+
+		ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_STREAM_ON, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			dev_err(&dev->pdev->dev,
+				"stream on wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &dev->state);
+	}
+
+	return 0;
+}
+
+int fimc_is_ctrl_3dnr(struct fimc_is_dev *dev, int value)
+{
+	int ret;
+
+	if (value == CAMERA_3DNR_ON) {
+		/* buffer addr setting */
+		dev->back.tdnr_on = 1;
+		dev->is_p_region->shared[350] = (u32)dev->mem.dvaddr_3dnr;
+		dbg("3dnr buf:0x%08x size : 0x%08x\n",
+			dev->is_p_region->shared[350],
+			SIZE_3DNR_INTERNAL_BUF*NUM_3DNR_INTERNAL_BUF);
+
+		IS_TDNR_SET_PARAM_CONTROL_BUFFERNUM(dev,
+			SIZE_3DNR_INTERNAL_BUF * NUM_3DNR_INTERNAL_BUF);
+		IS_TDNR_SET_PARAM_CONTROL_BUFFERADDR(dev,
+			(u32)dev->mem.dvaddr_shared + 350 * sizeof(u32));
+		IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+
+	} else if (value == CAMERA_3DNR_OFF) {
+		dbg("disable 3DNR\n");
+		dev->back.tdnr_on = 0;
+		IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+	} else {
+		err("invalid ODC setting\n");
+		return -1;
+	}
+
+	dbg("IS_ST_STREAM_OFF\n");
+	clear_bit(IS_ST_STREAM_OFF, &dev->state);
+	fimc_is_hw_set_stream(dev, 0); /*stream off */
+	ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_STREAM_OFF, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		if (!ret)
+			err("s_power off failed!!\n");
+		return -EBUSY;
+	}
+
+	IS_SET_PARAM_BIT(dev, PARAM_TDNR_CONTROL);
+	IS_INC_PARAM_NUM(dev);
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+
+	dev->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&dev->state);
+	clear_bit(IS_ST_INIT_CAPTURE_STILL, &dev->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state);
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS change mode\n");
+	clear_bit(IS_ST_RUN, &dev->state);
+	set_bit(IS_ST_CHANGE_MODE, &dev->state);
+	fimc_is_hw_change_mode(dev, IS_MODE_PREVIEW_STILL);
+	ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_CHANGE_MODE_DONE, &dev->state),
+			(3*HZ)/*FIMC_IS_SHUTDOWN_TIMEOUT*/);
+
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"Mode change timeout:%s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS_ST_STREAM_ON\n");
+	clear_bit(IS_ST_STREAM_ON, &dev->state);
+	fimc_is_hw_set_stream(dev, 1);
+
+	ret = wait_event_timeout(dev->irq_queue,
+	test_bit(IS_ST_STREAM_ON, &dev->state),
+	FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	clear_bit(IS_ST_STREAM_ON, &dev->state);
+
+	return 0;
+}
+
+int fimc_is_digital_zoom(struct fimc_is_dev *dev, int value)
+{
+	u32 back_width, back_height;
+	u32 crop_width, crop_height, crop_x, crop_y;
+	u32 zoom;
+	int ret;
+
+	if (dev->back.dis_on) {
+		back_width = dev->back.dis_width;
+		back_height = dev->back.dis_height;
+	} else {
+		back_width = dev->back.width;
+		back_height = dev->back.height;
+	}
+
+	zoom = value+10;
+
+	crop_width = back_width*10/zoom;
+	crop_height = back_height*10/zoom;
+
+	crop_width &= 0xffe;
+	crop_height &= 0xffe;
+
+	crop_x = (back_width - crop_width)/2;
+	crop_y = (back_height - crop_height)/2;
+
+	crop_x &= 0xffe;
+	crop_y &= 0xffe;
+
+	dbg("crop_width : %d crop_height: %d\n", crop_width, crop_height);
+	dbg("crop_x:%d crop_y: %d\n", crop_x, crop_y);
+
+	IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev,
+		crop_width);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev,
+		crop_height);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev,
+		crop_x);
+	IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev,
+		crop_y);
+	IS_SET_PARAM_BIT(dev, PARAM_SCALERC_INPUT_CROP);
+	IS_INC_PARAM_NUM(dev);
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+
+	dev->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&dev->state);
+	clear_bit(IS_ST_INIT_CAPTURE_STILL, &dev->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state);
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	return 0;
+}
+
+
+int fimc_is_v4l2_isp_scene_mode(struct fimc_is_dev *dev, int mode)
+{
+	int ret = 0;
+	switch (mode) {
+	case SCENE_MODE_NONE:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+				ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_PORTRAIT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -1);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -1);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_LANDSCAPE:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_MATRIX);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_SPORTS:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 400);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_PARTY_INDOOR:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 200);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_BEACH_SNOW:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 50);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_SUNSET:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+				ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_DUSK_DAWN:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+				ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_FLUORESCENT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_FALL_COLOR:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_NIGHTSHOT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_BACK_LIGHT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	/* FIXME add with SCENE_MODE_BACK_LIGHT (FLASH mode) */
+	case SCENE_MODE_FIREWORKS:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 50);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_TEXT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_CANDLE_LIGHT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_af_face(struct fimc_is_dev *dev)
+{
+	int ret = 0, max_confidence = 0, i = 0;
+	int width, height;
+	u32 touch_x = 0, touch_y = 0;
+
+	for (i = dev->fd_header.index;
+		i < (dev->fd_header.index + dev->fd_header.count); i++) {
+		if (max_confidence < dev->is_p_region->face[i].confidence) {
+			max_confidence = dev->is_p_region->face[i].confidence;
+			touch_x = dev->is_p_region->face[i].face.offset_x +
+				(dev->is_p_region->face[i].face.width / 2);
+			touch_y = dev->is_p_region->face[i].face.offset_y +
+				(dev->is_p_region->face[i].face.height / 2);
+		}
+	}
+	width = dev->sensor.width;
+	height = dev->sensor.height;
+	touch_x = 1024 *  touch_x / (u32)width;
+	touch_y = 1024 *  touch_y / (u32)height;
+
+	if ((touch_x == 0) || (touch_y == 0) || (max_confidence < 50))
+		return ret;
+
+	if (dev->af.prev_pos_x == 0 && dev->af.prev_pos_y == 0) {
+		dev->af.prev_pos_x = touch_x;
+		dev->af.prev_pos_y = touch_y;
+	} else {
+		if (abs(dev->af.prev_pos_x - touch_x) < 100 &&
+			abs(dev->af.prev_pos_y - touch_y) < 100) {
+			return ret;
+		}
+		dbg("AF Face level = %d\n", max_confidence);
+		dbg("AF Face = <%d, %d>\n", touch_x, touch_y);
+		dbg("AF Face = prev <%d, %d>\n",
+				dev->af.prev_pos_x, dev->af.prev_pos_y);
+		dev->af.prev_pos_x = touch_x;
+		dev->af.prev_pos_y = touch_y;
+	}
+
+	IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+	IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+	IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_TOUCH);
+	IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+	IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+	IS_ISP_SET_PARAM_AA_TOUCH_X(dev, touch_x);
+	IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, touch_y);
+	IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+	IS_INC_PARAM_NUM(dev);
+	dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	fimc_is_hw_set_param(dev);
+
+	return ret;
+}
+
+int fimc_is_v4l2_af_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case FOCUS_MODE_AUTO:
+		dev->af.mode = IS_FOCUS_MODE_AUTO;
+		break;
+	case FOCUS_MODE_MACRO:
+		dev->af.mode = IS_FOCUS_MODE_MACRO;
+		break;
+	case FOCUS_MODE_INFINITY:
+		dev->af.mode = IS_FOCUS_MODE_INFINITY;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_MANUAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case FOCUS_MODE_CONTINOUS:
+		dev->af.mode = IS_FOCUS_MODE_CONTINUOUS;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_CONTINUOUS);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		dev->af.prev_pos_x = 0;
+		dev->af.prev_pos_y = 0;
+		break;
+	case FOCUS_MODE_TOUCH:
+		dev->af.mode = IS_FOCUS_MODE_TOUCH;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_TOUCH);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, dev->af.pos_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, dev->af.pos_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		break;
+	case FOCUS_MODE_FACEDETECT:
+		dev->af.mode = IS_FOCUS_MODE_FACEDETECT;
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		dev->af.prev_pos_x = 0;
+		dev->af.prev_pos_y = 0;
+		break;
+	default:
+		return ret;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_af_start_stop(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case AUTO_FOCUS_OFF:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_IDLE;
+		} else {
+			if (dev->af.af_state == FIMC_IS_AF_IDLE)
+				return ret;
+			/* Abort or lock AF */
+			dev->af.af_state = FIMC_IS_AF_ABORT;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			switch (dev->af.mode) {
+			case IS_FOCUS_MODE_AUTO:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_SINGLE);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+					break;
+			case IS_FOCUS_MODE_MACRO:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_SINGLE);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_MACRO);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue,
+				(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			case IS_FOCUS_MODE_CONTINUOUS:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_CONTINUOUS);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+						ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue,
+				(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			default:
+				/* If other AF mode, there is no
+				cancelation process*/
+				break;
+			}
+			dev->af.mode = IS_FOCUS_MODE_IDLE;
+		}
+		break;
+	case AUTO_FOCUS_ON:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = FIMC_IS_AF_LOCKED;
+			dev->is_shared_region->af_status = 1;
+			fimc_is_mem_cache_clean((void *)IS_SHARED(dev),
+			(unsigned long)(sizeof(struct is_share_region)));
+		} else {
+			dev->af.af_lock_state = 0;
+			dev->af.ae_lock_state = 0;
+			dev->af.awb_lock_state = 0;
+			dev->is_shared_region->af_status = 0;
+			fimc_is_mem_cache_clean((void *)IS_SHARED(dev),
+			(unsigned long)(sizeof(struct is_share_region)));
+			IS_ISP_SET_PARAM_AA_CMD(dev,
+			ISP_AA_COMMAND_START);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			switch (dev->af.mode) {
+			case IS_FOCUS_MODE_AUTO:
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				dev->af.af_state =
+						FIMC_IS_AF_SETCONFIG;
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue,
+				(dev->af.af_state == FIMC_IS_AF_RUNNING), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			case IS_FOCUS_MODE_MACRO:
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_MACRO);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				dev->af.af_state =
+						FIMC_IS_AF_SETCONFIG;
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue,
+				(dev->af.af_state == FIMC_IS_AF_RUNNING), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_touch_af_start_stop(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case TOUCH_AF_STOP:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_IDLE;
+		} else {
+			if (dev->af.af_state == FIMC_IS_AF_IDLE)
+				return ret;
+			/* Abort or lock CAF */
+			dev->af.af_state = FIMC_IS_AF_ABORT;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+
+			IS_ISP_SET_PARAM_AA_MODE(dev,
+				ISP_AF_MODE_TOUCH);
+			IS_ISP_SET_PARAM_AA_SCENE(dev,
+				ISP_AF_SCENE_NORMAL);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev,
+				ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean(
+				(void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+			(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+			if (!ret) {
+				dev_err(&dev->pdev->dev,
+				"Focus change timeout:%s\n", __func__);
+				return -EBUSY;
+			}
+		}
+		break;
+	case TOUCH_AF_START:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = FIMC_IS_AF_LOCKED;
+			dev->is_shared_region->af_status = 1;
+			fimc_is_mem_cache_clean((void *)IS_SHARED(dev),
+			(unsigned long)(sizeof(struct is_share_region)));
+		} else {
+			dev->af.mode = IS_FOCUS_MODE_TOUCH;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_TOUCH);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, dev->af.pos_x);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, dev->af.pos_y);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+			IS_INC_PARAM_NUM(dev);
+			dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(dev);
+			dev->af.af_lock_state = 0;
+			dev->af.ae_lock_state = 0;
+			dev->af.awb_lock_state = 0;
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_caf_start_stop(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case CAF_STOP:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_IDLE;
+		} else {
+			if (dev->af.af_state == FIMC_IS_AF_IDLE)
+				return ret;
+			/* Abort or lock CAF */
+			dev->af.af_state = FIMC_IS_AF_ABORT;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+
+			IS_ISP_SET_PARAM_AA_MODE(dev,
+				ISP_AF_MODE_CONTINUOUS);
+			IS_ISP_SET_PARAM_AA_SCENE(dev,
+				ISP_AF_SCENE_NORMAL);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev,
+				ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean(
+				(void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+			(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+			if (!ret) {
+				dev_err(&dev->pdev->dev,
+				"Focus change timeout:%s\n", __func__);
+				return -EBUSY;
+			}
+		}
+		break;
+	case CAF_START:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = FIMC_IS_AF_LOCKED;
+			dev->is_shared_region->af_status = 1;
+			fimc_is_mem_cache_clean((void *)IS_SHARED(dev),
+			(unsigned long)(sizeof(struct is_share_region)));
+		} else {
+			dev->af.mode = IS_FOCUS_MODE_CONTINUOUS;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_CONTINUOUS);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+			IS_INC_PARAM_NUM(dev);
+			dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(dev);
+			dev->af.af_lock_state = 0;
+			dev->af.ae_lock_state = 0;
+			dev->af.awb_lock_state = 0;
+			dev->af.prev_pos_x = 0;
+			dev->af.prev_pos_y = 0;
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_iso(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case ISO_AUTO:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		break;
+	case ISO_100:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 100);
+		break;
+	case ISO_200:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 200);
+		break;
+	case ISO_400:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 400);
+		break;
+	case ISO_800:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 800);
+		break;
+	case ISO_1600:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 1600);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= ISO_AUTO && value < ISO_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_effect(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_IMAGE_EFFECT_DISABLE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_DISABLE);
+		break;
+	case IS_IMAGE_EFFECT_MONOCHROME:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_MONOCHROME);
+		break;
+	case IS_IMAGE_EFFECT_NEGATIVE_MONO:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_MONO);
+		break;
+	case IS_IMAGE_EFFECT_NEGATIVE_COLOR:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_COLOR);
+		break;
+	case IS_IMAGE_EFFECT_SEPIA:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_SEPIA);
+		break;
+	}
+	/* only ISP effect in Pegasus */
+	if (value >= 0 && value < 5) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_effect_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IMAGE_EFFECT_NONE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_DISABLE);
+		break;
+	case IMAGE_EFFECT_BNW:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_MONOCHROME);
+		break;
+	case IMAGE_EFFECT_NEGATIVE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_COLOR);
+		break;
+	case IMAGE_EFFECT_SEPIA:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_SEPIA);
+		break;
+	default:
+		return ret;
+	}
+	/* only ISP effect in Pegasus */
+	if (value > IMAGE_EFFECT_BASE && value < IMAGE_EFFECT_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_flash_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case FLASH_MODE_OFF:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	case FLASH_MODE_AUTO:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		break;
+	case FLASH_MODE_ON:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_MANUALON);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	case FLASH_MODE_TORCH:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_TORCH);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	default:
+		return ret;
+	}
+	if (value > FLASH_MODE_BASE && value < FLASH_MODE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_awb_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_AWB_AUTO:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, 0);
+		break;
+	case IS_AWB_DAYLIGHT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		break;
+	case IS_AWB_CLOUDY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_CLOUDY);
+		break;
+	case IS_AWB_TUNGSTEN:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_TUNGSTEN);
+		break;
+	case IS_AWB_FLUORESCENT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_FLUORESCENT);
+		break;
+	}
+	if (value >= IS_AWB_AUTO && value < IS_AWB_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_awb_mode_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case WHITE_BALANCE_AUTO:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, 0);
+		break;
+	case WHITE_BALANCE_SUNNY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		break;
+	case WHITE_BALANCE_CLOUDY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_CLOUDY);
+		break;
+	case WHITE_BALANCE_TUNGSTEN:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_TUNGSTEN);
+		break;
+	case WHITE_BALANCE_FLUORESCENT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_FLUORESCENT);
+		break;
+	}
+	if (value > WHITE_BALANCE_BASE && value < WHITE_BALANCE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_contrast(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_CONTRAST_AUTO:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_AUTO);
+		break;
+	case IS_CONTRAST_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -2);
+		break;
+	case IS_CONTRAST_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -1);
+		break;
+	case IS_CONTRAST_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		break;
+	case IS_CONTRAST_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		break;
+	case IS_CONTRAST_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_CONTRAST_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_contrast_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case CONTRAST_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -2);
+		break;
+	case CONTRAST_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -1);
+		break;
+	case CONTRAST_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		break;
+	case CONTRAST_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		break;
+	case CONTRAST_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < CONTRAST_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_saturation(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case SATURATION_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -2);
+		break;
+	case SATURATION_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -1);
+		break;
+	case SATURATION_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		break;
+	case SATURATION_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 1);
+		break;
+	case SATURATION_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < SATURATION_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_sharpness(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+
+	switch (value) {
+	case SHARPNESS_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -2);
+		break;
+	case SHARPNESS_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -1);
+		break;
+	case SHARPNESS_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		break;
+	case SHARPNESS_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 1);
+		break;
+	case SHARPNESS_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < SHARPNESS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_exposure(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_EXPOSURE_MINUS_4:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -4);
+		break;
+	case IS_EXPOSURE_MINUS_3:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -3);
+		break;
+	case IS_EXPOSURE_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -2);
+		break;
+	case IS_EXPOSURE_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -1);
+		break;
+	case IS_EXPOSURE_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		break;
+	case IS_EXPOSURE_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		break;
+	case IS_EXPOSURE_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 2);
+		break;
+	case IS_EXPOSURE_PLUS_3:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 3);
+		break;
+	case IS_EXPOSURE_PLUS_4:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 4);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_EXPOSURE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_exposure_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	if (value >= -4 && value < 5) {
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_brightness(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_BRIGHTNESS_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, -2);
+		break;
+	case IS_BRIGHTNESS_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, -1);
+		break;
+	case IS_BRIGHTNESS_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		break;
+	case IS_BRIGHTNESS_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 1);
+		break;
+	case IS_BRIGHTNESS_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 2);
+		break;
+	}
+	if (value >= 0 && value < IS_BRIGHTNESS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_hue(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_HUE_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, -2);
+		break;
+	case IS_HUE_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, -1);
+		break;
+	case IS_HUE_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		break;
+	case IS_HUE_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 1);
+		break;
+	case IS_HUE_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= IS_HUE_MINUS_2 && value < IS_HUE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_metering(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_METERING_AVERAGE:
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		break;
+	case IS_METERING_SPOT:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_SPOT);
+		break;
+	case IS_METERING_MATRIX:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_MATRIX);
+		break;
+	case IS_METERING_CENTER:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_CENTER);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_METERING_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_metering_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case METERING_CENTER:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_CENTER);
+		break;
+	case METERING_SPOT:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_SPOT);
+		break;
+	case METERING_MATRIX:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_MATRIX);
+		break;
+	default:
+		return ret;
+	}
+	if (value > METERING_BASE && value < METERING_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_afc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_AFC_DISABLE:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case IS_AFC_AUTO:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case IS_AFC_MANUAL_50HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_50HZ);
+		break;
+	case IS_AFC_MANUAL_60HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_60HZ);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_AFC_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_isp_afc_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case ANTI_BANDING_OFF:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case ANTI_BANDING_AUTO:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case ANTI_BANDING_50HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_50HZ);
+		break;
+	case ANTI_BANDING_60HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_60HZ);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= ANTI_BANDING_OFF && value <= ANTI_BANDING_60HZ) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_fd_angle_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_FD_ROLL_ANGLE_BASIC:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ROLL_ANGLE);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_YAW_ANGLE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_YAW_ANGLE);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_SMILE_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_SMILE_MODE);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_BLINK_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_BLINK_MODE);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_EYE_DETECT_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_EYES_DETECT);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_MOUTH_DETECT_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_MOUTH_DETECT);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_ORIENTATION_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ORIENTATION);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_ORIENTATION:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_frame_rate(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+
+	switch (value) {
+	case 0: /* AUTO Mode */
+		IS_SENSOR_SET_FRAME_RATE(dev, 30);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout 1 : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout 2: %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 66666);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout 3: %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout 4: %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	default:
+		IS_SENSOR_SET_FRAME_RATE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout 1 : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout 2: %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+							(u32)(1000000/value));
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout 3: %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(FIMC_IS_STATE_HW_STREAM_ON, &dev->pipe_state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout 4: %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+	}
+	return 0;
+}
+
+int fimc_is_v4l2_ae_awb_lockunlock(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case AE_UNLOCK_AWB_UNLOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_LOCK_AWB_UNLOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_UNLOCK_AWB_LOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_LOCK_AWB_LOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_set_isp(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_ISP_BYPASS_DISABLE:
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+		break;
+	case IS_ISP_BYPASS_ENABLE:
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_ISP_BYPASS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_set_drc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_DRC_BYPASS_DISABLE:
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	case IS_DRC_BYPASS_ENABLE:
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_DRC_BYPASS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_cmd_isp(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_ISP_COMMAND_STOP:
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_ISP_COMMAND_START:
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_cmd_drc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_DRC_COMMAND_STOP:
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_DRC_COMMAND_START:
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_cmd_fd(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_FD_COMMAND_STOP:
+		dbg("IS_FD_COMMAND_STOP\n");
+		IS_FD_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_FD_COMMAND_START:
+		dbg("IS_FD_COMMAND_START\n");
+		IS_FD_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+int fimc_is_v4l2_shot_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+
+	dbg("%s\n", __func__);
+	IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, value);
+	IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+	IS_INC_PARAM_NUM(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	fimc_is_hw_set_param(dev);
+	return ret;
+}
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.h
new file mode 100644
index 0000000..247795c
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-misc.h
@@ -0,0 +1,57 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_MISC_H
+#define FIMC_IS_MISC_H
+
+int enable_mipi(void);
+int start_fimc_lite(int channel, struct flite_frame *f_frame);
+int stop_fimc_lite(int channel);
+int start_mipi_csi(int channel, struct flite_frame *f_frame);
+int stop_mipi_csi(int channel);
+
+int fimc_is_digital_zoom(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_af_start_stop(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_touch_af_start_stop(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_caf_start_stop(struct fimc_is_dev *dev, int value);
+int fimc_is_ctrl_odc(struct fimc_is_dev *dev, int value);
+int fimc_is_ctrl_dis(struct fimc_is_dev *dev, int value);
+int fimc_is_ctrl_3dnr(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_scene_mode(struct fimc_is_dev *dev, int mode);
+int fimc_is_af_face(struct fimc_is_dev *dev);
+int fimc_is_v4l2_af_mode(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_iso(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_effect(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_effect_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_flash_mode(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_awb_mode(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_awb_mode_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_contrast(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_contrast_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_saturation(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_sharpness(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_exposure(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_exposure_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_brightness(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_hue(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_metering(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_metering_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_afc(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_isp_afc_legacy(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_fd_angle_mode(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_frame_rate(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_ae_awb_lockunlock(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_set_isp(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_set_drc(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_cmd_isp(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_cmd_drc(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_cmd_fd(struct fimc_is_dev *dev, int value);
+int fimc_is_v4l2_shot_mode(struct fimc_is_dev *dev, int value);
+#endif/*FIMC_IS_MISC_H*/
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-param.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-param.h
new file mode 100644
index 0000000..7c79af7
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-param.h
@@ -0,0 +1,2054 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_PARAMS_H
+#define FIMC_IS_PARAMS_H
+
+#define IS_REGION_VER 121  /* IS REGION VERSION 1.15 */
+
+/* MACROs */
+#define IS_SET_PARAM_BIT(dev, num) \
+	(num >= 32 ? set_bit((num-32), &dev->p_region_index2) \
+		: set_bit(num, &dev->p_region_index1))
+#define IS_INC_PARAM_NUM(dev)		atomic_inc(&dev->p_region_num)
+
+#define IS_PARAM_GLOBAL(dev)		(dev->is_p_region->parameter.global)
+#define IS_PARAM_ISP(dev)		(dev->is_p_region->parameter.isp)
+#define IS_PARAM_DRC(dev)		(dev->is_p_region->parameter.drc)
+#define IS_PARAM_FD(dev)		(dev->is_p_region->parameter.fd)
+#define IS_HEADER(dev)			(dev->is_p_region->header)
+#define IS_FACE(dev)			(dev->is_p_region->face)
+#define IS_SHARED(dev)			(dev->is_shared_region)
+#define IS_PARAM_SIZE			(FIMC_IS_REGION_SIZE + 1)
+
+/* Global control */
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, x) \
+		(dev->is_p_region->parameter.global.shotmode.cmd = x)
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_SKIPFRAMES(dev, x) \
+		(dev->is_p_region->parameter.global.shotmode.skip_frames = x)
+
+/* Sensor control */
+#define IS_SENSOR_SET_FRAME_RATE(dev, x) \
+		(dev->is_p_region->parameter.sensor.frame_rate.frame_rate = x)
+
+/* ISP Macros */
+#define IS_ISP_SET_PARAM_CONTROL_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.control.cmd = x)
+#define IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, x) \
+		(dev->is_p_region->parameter.isp.control.bypass = x)
+#define IS_ISP_SET_PARAM_CONTROL_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.control.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.format = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.order = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_offset_x = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_offset_y = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.frametime_min = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.frametime_max = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.err = x)
+
+#define IS_ISP_SET_PARAM_AA_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.cmd = x)
+#define IS_ISP_SET_PARAM_AA_TARGET(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.target = x)
+#define IS_ISP_SET_PARAM_AA_MODE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.mode = x)
+#define IS_ISP_SET_PARAM_AA_SCENE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.scene = x)
+#define IS_ISP_SET_PARAM_AA_SLEEP(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.sleep = x)
+#define IS_ISP_SET_PARAM_AA_FACE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.face = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_X(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.touch_x = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.touch_y = x)
+#define IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.manual_af_setting = x)
+#define IS_ISP_SET_PARAM_AA_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.err = x)
+
+#define IS_ISP_SET_PARAM_FLASH_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.cmd = x)
+#define IS_ISP_SET_PARAM_FLASH_REDEYE(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.redeye = x)
+#define IS_ISP_SET_PARAM_FLASH_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.err = x)
+
+#define IS_ISP_SET_PARAM_AWB_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.cmd = x)
+#define IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.illumination = x)
+#define IS_ISP_SET_PARAM_AWB_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.err = x)
+
+#define IS_ISP_SET_PARAM_EFFECT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.effect.cmd = x)
+#define IS_ISP_SET_PARAM_EFFECT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.effect.err = x)
+
+#define IS_ISP_SET_PARAM_ISO_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.cmd = x)
+#define IS_ISP_SET_PARAM_ISO_VALUE(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.value = x)
+#define IS_ISP_SET_PARAM_ISO_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.err = x)
+
+#define IS_ISP_SET_PARAM_ADJUST_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.cmd = x)
+#define IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.contrast = x)
+#define IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.saturation = x)
+#define IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.sharpness = x)
+#define IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.exposure = x)
+#define IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.brightness = x)
+#define IS_ISP_SET_PARAM_ADJUST_HUE(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.hue = x)
+#define IS_ISP_SET_PARAM_ADJUST_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.err = x)
+
+#define IS_ISP_SET_PARAM_METERING_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.cmd = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_pos_x = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_pos_y = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_width = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_height = x)
+#define IS_ISP_SET_PARAM_METERING_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.err = x)
+
+#define IS_ISP_SET_PARAM_AFC_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.cmd = x)
+#define IS_ISP_SET_PARAM_AFC_MANUAL(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.manual = x)
+#define IS_ISP_SET_PARAM_AFC_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.width = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.height = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.format = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.order = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev, x) \
+	(dev->is_p_region->parameter.isp.dma1_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_MASK(dev, x) \
+	(dev->is_p_region->parameter.isp.dma1_output.dma_out_mask = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_MASK(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.dma_out_mask = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_DMA_DONE(dev, x) \
+	(dev->is_p_region->parameter.isp.dma2_output.notify_dma_done = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.err = x)
+
+/* DRC Macros */
+#define IS_DRC_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.control.cmd = x)
+#define IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.drc.control.bypass = x)
+#define IS_DRC_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.control.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.width = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.height = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.format = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.order = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.err = x)
+
+#define IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.cmd = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.width = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.height = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.format = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.plane = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.order = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.drc.dma_input.buffer_number = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.drc.dma_input.buffer_address = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.width = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.height = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.format = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.order = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.err = x)
+
+/* SCALER-C Macros */
+#define IS_SCALERC_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.control.cmd = x)
+#define IS_SCALERC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.scalerc.control.bypass = x)
+#define IS_SCALERC_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.control.err = x)
+
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.cmd = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.width = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.height = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.format = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.order = x)
+#define IS_SCALERC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_input.err = x)
+
+#define IS_SCALERC_SET_PARAM_EFFECT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.effect.cmd = x)
+#define IS_SCALERC_SET_PARAM_EFFECT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.effect.err = x)
+
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.cmd = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_POS_X(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.pos_x = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_POS_Y(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.pos_y = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.crop_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.crop_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_IN_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.in_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.in_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.out_width = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.out_height = x)
+#define IS_SCALERC_SET_PARAM_INPUT_CROP_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.input_crop.err = x)
+
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.cmd = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_X(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.pos_x = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_POS_Y(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.pos_y = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.crop_width = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.crop_height = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROPG_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.format = x)
+#define IS_SCALERC_SET_PARAM_OUTPUT_CROP_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.output_crop.err = x)
+
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.cmd = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.width = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.height = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.format = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.order = x)
+#define IS_SCALERC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.otf_output.err = x)
+
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.cmd = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.width = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.height = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.format = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.bitwidth = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.plane = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.order = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.buffer_number = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.buffer_address = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.dma_out_mask = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_OUTPATH(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.reserved[0] = x)
+#define IS_SCALERC_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerc.dma_output.err = x)
+
+/* ODC Macros */
+#define IS_ODC_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.odc.control.cmd = x)
+#define IS_ODC_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.odc.control.buffer_number = x)
+#define IS_ODC_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.odc.control.buffer_address = x)
+#define IS_ODC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.odc.control.bypass = x)
+#define IS_ODC_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.odc.control.err = x)
+
+#define IS_ODC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.cmd = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.width = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.height = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.format = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.bitwidth = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.order = x)
+#define IS_ODC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_input.err = x)
+
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.cmd = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.width = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.height = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.format = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.bitwidth = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.order = x)
+#define IS_ODC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.odc.otf_output.err = x)
+
+/* DIS Macros */
+#define IS_DIS_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.dis.control.cmd = x)
+#define IS_DIS_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.dis.control.buffer_number = x)
+#define IS_DIS_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.dis.control.buffer_address = x)
+#define IS_DIS_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.dis.control.bypass = x)
+#define IS_DIS_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.dis.control.err = x)
+
+#define IS_DIS_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.cmd = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.width = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.height = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.format = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.bitwidth = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.order = x)
+#define IS_DIS_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_input.err = x)
+
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.cmd = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.width = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.height = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.format = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.bitwidth = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.order = x)
+#define IS_DIS_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.dis.otf_output.err = x)
+
+/* TDNR Macros */
+#define IS_TDNR_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.tdnr.control.cmd = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.tdnr.control.bypass = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.tdnr.control.buffer_number = x)
+#define IS_TDNR_SET_PARAM_CONTROL_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.control.buffer_address = x)
+#define IS_TDNR_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.control.err = x)
+
+#define IS_TDNR_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.cmd = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.width = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.height = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.format = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.bitwidth = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.order = x)
+#define IS_TDNR_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_input.err = x)
+
+#define IS_TDNR_SET_PARAM_FRAME_CMD(dev, x) \
+	(dev->is_p_region->parameter.tdnr.frame.cmd = x)
+#define IS_TDNR_SET_PARAM_FRAME_ERR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.frame.err = x)
+
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.cmd = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.width = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.height = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.format = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.bitwidth = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.order = x)
+#define IS_TDNR_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.otf_output.err = x)
+
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.cmd = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.width = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.height = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.format = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.bitwidth = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.plane = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.order = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.buffer_number = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.buffer_address = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.dma_out_mask = x)
+#define IS_TDNR_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.tdnr.dma_output.err = x)
+
+/* SCALER-P Macros */
+#define IS_SCALERP_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.control.cmd = x)
+#define IS_SCALERP_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.scalerp.control.bypass = x)
+#define IS_SCALERP_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.control.err = x)
+
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.cmd = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.width = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.height = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.format = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.order = x)
+#define IS_SCALERP_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_input.err = x)
+
+#define IS_SCALERP_SET_PARAM_EFFECT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.effect.cmd = x)
+#define IS_SCALERP_SET_PARAM_EFFECT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.effect.err = x)
+
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.cmd = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_POS_X(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.pos_x = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_POS_Y(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.pos_y = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.crop_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.crop_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_IN_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.in_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_IN_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.in_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.out_width = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_OUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.out_height = x)
+#define IS_SCALERP_SET_PARAM_INPUT_CROP_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.input_crop.err = x)
+
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.cmd = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_X(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.pos_x = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_POS_Y(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.pos_y = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.crop_width = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_CROP_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.crop_height = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROPG_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.format = x)
+#define IS_SCALERP_SET_PARAM_OUTPUT_CROP_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.output_crop.err = x)
+
+#define IS_SCALERP_SET_PARAM_ROTATION_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.rotation.cmd = x)
+#define IS_SCALERP_SET_PARAM_ROTATION_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.rotation.err = x)
+
+#define IS_SCALERP_SET_PARAM_FLIP_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.flip.cmd = x)
+#define IS_SCALERP_SET_PARAM_FLIP_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.flip.err = x)
+
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.cmd = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.width = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.height = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.format = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.order = x)
+#define IS_SCALERP_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.otf_output.err = x)
+
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.cmd = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.width = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.height = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.format = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.bitwidth = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.plane = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.order = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.buffer_number = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.buffer_address = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_MASK(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.dma_out_mask = x)
+#define IS_SCALERP_SET_PARAM_DMA_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.scalerp.dma_output.err = x)
+
+/* FD Macros */
+#define IS_FD_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.control.cmd = x)
+#define IS_FD_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.fd.control.bypass = x)
+#define IS_FD_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.control.err = x)
+
+#define IS_FD_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.cmd = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.width = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.height = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.format = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.bitwidth = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.order = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.err = x)
+
+#define IS_FD_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.cmd = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.width = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.height = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.format = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.bitwidth = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.plane = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.order = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.buffer_number = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.buffer_address = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.err = x)
+
+#define IS_FD_SET_PARAM_FD_CONFIG_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.config.cmd = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev, x) \
+	(dev->is_p_region->parameter.fd.config.max_number = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.roll_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.yaw_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.smile_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.blink_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev, x) \
+	(dev->is_p_region->parameter.fd.config.eye_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev, x) \
+	(dev->is_p_region->parameter.fd.config.mouth_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev, x) \
+	(dev->is_p_region->parameter.fd.config.orientation = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.orientation_value = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.config.err = x)
+
+#ifndef BIT0
+#define  BIT0     0x00000001
+#define  BIT1     0x00000002
+#define  BIT2     0x00000004
+#define  BIT3     0x00000008
+#define  BIT4     0x00000010
+#define  BIT5     0x00000020
+#define  BIT6     0x00000040
+#define  BIT7     0x00000080
+#define  BIT8     0x00000100
+#define  BIT9     0x00000200
+#define  BIT10    0x00000400
+#define  BIT11    0x00000800
+#define  BIT12    0x00001000
+#define  BIT13    0x00002000
+#define  BIT14    0x00004000
+#define  BIT15    0x00008000
+#define  BIT16    0x00010000
+#define  BIT17    0x00020000
+#define  BIT18    0x00040000
+#define  BIT19    0x00080000
+#define  BIT20    0x00100000
+#define  BIT21    0x00200000
+#define  BIT22    0x00400000
+#define  BIT23    0x00800000
+#define  BIT24    0x01000000
+#define  BIT25    0x02000000
+#define  BIT26    0x04000000
+#define  BIT27    0x08000000
+#define  BIT28    0x10000000
+#define  BIT29    0x20000000
+#define  BIT30    0x40000000
+#define  BIT31    0x80000000
+#define  BIT32    0x0000000100000000ULL
+#define  BIT33    0x0000000200000000ULL
+#define  BIT34    0x0000000400000000ULL
+#define  BIT35    0x0000000800000000ULL
+#define  BIT36    0x0000001000000000ULL
+#define  BIT37    0x0000002000000000ULL
+#define  BIT38    0x0000004000000000ULL
+#define  BIT39    0x0000008000000000ULL
+#define  BIT40    0x0000010000000000ULL
+#define  BIT41    0x0000020000000000ULL
+#define  BIT42    0x0000040000000000ULL
+#define  BIT43    0x0000080000000000ULL
+#define  BIT44    0x0000100000000000ULL
+#define  BIT45    0x0000200000000000ULL
+#define  BIT46    0x0000400000000000ULL
+#define  BIT47    0x0000800000000000ULL
+#define  BIT48    0x0001000000000000ULL
+#define  BIT49    0x0002000000000000ULL
+#define  BIT50    0x0004000000000000ULL
+#define  BIT51    0x0008000000000000ULL
+#define  BIT52    0x0010000000000000ULL
+#define  BIT53    0x0020000000000000ULL
+#define  BIT54    0x0040000000000000ULL
+#define  BIT55    0x0080000000000000ULL
+#define  BIT56    0x0100000000000000ULL
+#define  BIT57    0x0200000000000000ULL
+#define  BIT58    0x0400000000000000ULL
+#define  BIT59    0x0800000000000000ULL
+#define  BIT60    0x1000000000000000ULL
+#define  BIT61    0x2000000000000000ULL
+#define  BIT62    0x4000000000000000ULL
+#define  BIT63    0x8000000000000000ULL
+#define  INC_BIT(bit) (bit<<1)
+#define  INC_NUM(bit) (bit + 1)
+#endif
+
+#define MAGIC_NUMBER 0x01020304
+
+#define PARAMETER_MAX_SIZE    64  /* in byte */
+#define PARAMETER_MAX_MEMBER  (PARAMETER_MAX_SIZE/4)
+
+enum is_entry {
+	ENTRY_GLOBAL,
+	ENTRY_BUFFER,
+	ENTRY_SENSOR,
+	ENTRY_ISP,
+	ENTRY_DRC,
+	ENTRY_SCALERC,
+	ENTRY_ODC,
+	ENTRY_DIS,
+	ENTRY_TDNR,
+	ENTRY_SCALERP,
+	ENTRY_LHFD, /* 10 */
+	ENTRY_END
+};
+
+enum is_param_set_bit {
+	PARAM_GLOBAL_SHOTMODE = 0,
+	PARAM_SENSOR_CONTROL,
+	PARAM_SENSOR_OTF_INPUT,
+	PARAM_SENSOR_OTF_OUTPUT,
+	PARAM_SENSOR_FRAME_RATE,
+	PARAM_SENSOR_DMA_OUTPUT,
+	PARAM_BUFFER_CONTROL,
+	PARAM_BUFFER_OTF_INPUT,
+	PARAM_BUFFER_OTF_OUTPUT,
+	PARAM_ISP_CONTROL,
+	PARAM_ISP_OTF_INPUT = 10,
+	PARAM_ISP_DMA1_INPUT,
+	PARAM_ISP_DMA2_INPUT,
+	PARAM_ISP_AA,
+	PARAM_ISP_FLASH,
+	PARAM_ISP_AWB,
+	PARAM_ISP_IMAGE_EFFECT,
+	PARAM_ISP_ISO,
+	PARAM_ISP_ADJUST,
+	PARAM_ISP_METERING,
+	PARAM_ISP_AFC = 20,
+	PARAM_ISP_OTF_OUTPUT,
+	PARAM_ISP_DMA1_OUTPUT,
+	PARAM_ISP_DMA2_OUTPUT,
+	PARAM_DRC_CONTROL,
+	PARAM_DRC_OTF_INPUT,
+	PARAM_DRC_DMA_INPUT,
+	PARAM_DRC_OTF_OUTPUT,
+	PARAM_SCALERC_CONTROL,
+	PARAM_SCALERC_OTF_INPUT,
+	PARAM_SCALERC_IMAGE_EFFECT = 30,
+	PARAM_SCALERC_INPUT_CROP,
+	PARAM_SCALERC_OUTPUT_CROP,
+	PARAM_SCALERC_OTF_OUTPUT,
+	PARAM_SCALERC_DMA_OUTPUT = 34,
+	PARAM_ODC_CONTROL,
+	PARAM_ODC_OTF_INPUT,
+	PARAM_ODC_OTF_OUTPUT,
+	PARAM_DIS_CONTROL,
+	PARAM_DIS_OTF_INPUT,
+	PARAM_DIS_OTF_OUTPUT = 40,
+	PARAM_TDNR_CONTROL,
+	PARAM_TDNR_OTF_INPUT,
+	PARAM_TDNR_1ST_FRAME,
+	PARAM_TDNR_OTF_OUTPUT,
+	PARAM_TDNR_DMA_OUTPUT,
+	PARAM_SCALERP_CONTROL,
+	PARAM_SCALERP_OTF_INPUT,
+	PARAM_SCALERP_IMAGE_EFFECT,
+	PARAM_SCALERP_INPUT_CROP,
+	PARAM_SCALERP_OUTPUT_CROP = 50,
+	PARAM_SCALERP_ROTATION,
+	PARAM_SCALERP_FLIP,
+	PARAM_SCALERP_OTF_OUTPUT,
+	PARAM_SCALERP_DMA_OUTPUT,
+	PARAM_FD_CONTROL,
+	PARAM_FD_OTF_INPUT,
+	PARAM_FD_DMA_INPUT,
+	PARAM_FD_CONFIG = 58,
+	PARAM_END,
+};
+
+#define ADDRESS_TO_OFFSET(start, end)	((uint32)end - (uint32)start)
+#define OFFSET_TO_NUM(offset)		((offset)>>6)
+#define IS_OFFSET_LOWBIT(offset)	(OFFSET_TO_NUM(offset) >= \
+						32 ? false : true)
+#define OFFSET_TO_BIT(offset) \
+		{(IS_OFFSET_LOWBIT(offset) ? (1<<OFFSET_TO_NUM(offset)) \
+			: (1<<(OFFSET_TO_NUM(offset)-32))}
+#define LOWBIT_OF_NUM(num)		(num >= 32 ? 0 : BIT0<<num)
+#define HIGHBIT_OF_NUM(num)		(num >= 32 ? BIT0<<(num-32) : 0)
+
+/* 0~31 */
+#define PARAM_GLOBAL_SHOTMODE		0
+#define PARAM_SENSOR_CONTROL		INC_NUM(PARAM_GLOBAL_SHOTMODE)
+#define PARAM_SENSOR_OTF_INPUT		INC_NUM(PARAM_SENSOR_CONTROL)
+#define PARAM_SENSOR_OTF_OUTPUT		INC_NUM(PARAM_SENSOR_OTF_INPUT)
+#define PARAM_SENSOR_FRAME_RATE		INC_NUM(PARAM_SENSOR_OTF_OUTPUT)
+#define PARAM_SENSOR_DMA_OUTPUT		INC_NUM(PARAM_SENSOR_FRAME_RATE)
+#define PARAM_BUFFER_CONTROL		INC_NUM(PARAM_SENSOR_DMA_OUTPUT)
+#define PARAM_BUFFER_OTF_INPUT		INC_NUM(PARAM_BUFFER_CONTROL)
+#define PARAM_BUFFER_OTF_OUTPUT		INC_NUM(PARAM_BUFFER_OTF_INPUT)
+#define PARAM_ISP_CONTROL		INC_NUM(PARAM_BUFFER_OTF_OUTPUT)
+#define PARAM_ISP_OTF_INPUT		INC_NUM(PARAM_ISP_CONTROL)
+#define PARAM_ISP_DMA1_INPUT		INC_NUM(PARAM_ISP_OTF_INPUT)
+#define PARAM_ISP_DMA2_INPUT		INC_NUM(PARAM_ISP_DMA1_INPUT)
+#define PARAM_ISP_AA			INC_NUM(PARAM_ISP_DMA2_INPUT)
+#define PARAM_ISP_FLASH			INC_NUM(PARAM_ISP_AA)
+#define PARAM_ISP_AWB			INC_NUM(PARAM_ISP_FLASH)
+#define PARAM_ISP_IMAGE_EFFECT		INC_NUM(PARAM_ISP_AWB)
+#define PARAM_ISP_ISO			INC_NUM(PARAM_ISP_IMAGE_EFFECT)
+#define PARAM_ISP_ADJUST		INC_NUM(PARAM_ISP_ISO)
+#define PARAM_ISP_METERING		INC_NUM(PARAM_ISP_ADJUST)
+#define PARAM_ISP_AFC			INC_NUM(PARAM_ISP_METERING)
+#define PARAM_ISP_OTF_OUTPUT		INC_NUM(PARAM_ISP_AFC)
+#define PARAM_ISP_DMA1_OUTPUT		INC_NUM(PARAM_ISP_OTF_OUTPUT)
+#define PARAM_ISP_DMA2_OUTPUT		INC_NUM(PARAM_ISP_DMA1_OUTPUT)
+#define PARAM_DRC_CONTROL		INC_NUM(PARAM_ISP_DMA2_OUTPUT)
+#define PARAM_DRC_OTF_INPUT		INC_NUM(PARAM_DRC_CONTROL)
+#define PARAM_DRC_DMA_INPUT		INC_NUM(PARAM_DRC_OTF_INPUT)
+#define PARAM_DRC_OTF_OUTPUT		INC_NUM(PARAM_DRC_DMA_INPUT)
+#define PARAM_SCALERC_CONTROL		INC_NUM(PARAM_DRC_OTF_OUTPUT)
+#define PARAM_SCALERC_OTF_INPUT		INC_NUM(PARAM_SCALERC_CONTROL)
+#define PARAM_SCALERC_IMAGE_EFFECT	INC_NUM(PARAM_SCALERC_OTF_INPUT)
+#define PARAM_SCALERC_INPUT_CROP	INC_NUM(PARAM_SCALERC_IMAGE_EFFECT)
+#define PARAM_SCALERC_OUTPUT_CROP	INC_NUM(PARAM_SCALERC_INPUT_CROP)
+#define PARAM_SCALERC_OTF_OUTPUT	INC_NUM(PARAM_SCALERC_OUTPUT_CROP)
+
+/* 32~63 */
+#define PARAM_SCALERC_DMA_OUTPUT	INC_NUM(PARAM_SCALERC_OTF_OUTPUT)
+#define PARAM_ODC_CONTROL		INC_NUM(PARAM_SCALERC_DMA_OUTPUT)
+#define PARAM_ODC_OTF_INPUT		INC_NUM(PARAM_ODC_CONTROL)
+#define PARAM_ODC_OTF_OUTPUT		INC_NUM(PARAM_ODC_OTF_INPUT)
+#define PARAM_DIS_CONTROL		INC_NUM(PARAM_ODC_OTF_OUTPUT)
+#define PARAM_DIS_OTF_INPUT		INC_NUM(PARAM_DIS_CONTROL)
+#define PARAM_DIS_OTF_OUTPUT		INC_NUM(PARAM_DIS_OTF_INPUT)
+#define PARAM_TDNR_CONTROL		INC_NUM(PARAM_DIS_OTF_OUTPUT)
+#define PARAM_TDNR_OTF_INPUT		INC_NUM(PARAM_TDNR_CONTROL)
+#define PARAM_TDNR_1ST_FRAME		INC_NUM(PARAM_TDNR_OTF_INPUT)
+#define PARAM_TDNR_OTF_OUTPUT		INC_NUM(PARAM_TDNR_1ST_FRAME)
+#define PARAM_TDNR_DMA_OUTPUT		INC_NUM(PARAM_TDNR_OTF_OUTPUT)
+#define PARAM_SCALERP_CONTROL		INC_NUM(PARAM_TDNR_DMA_OUTPUT)
+#define PARAM_SCALERP_OTF_INPUT		INC_NUM(PARAM_SCALERP_CONTROL)
+#define PARAM_SCALERP_IMAGE_EFFECT	INC_NUM(PARAM_SCALERP_OTF_INPUT)
+#define PARAM_SCALERP_INPUT_CROP	INC_NUM(PARAM_SCALERP_IMAGE_EFFECT)
+#define PARAM_SCALERP_OUTPUT_CROP	INC_NUM(PARAM_SCALERP_INPUT_CROP)
+#define PARAM_SCALERP_ROTATION		INC_NUM(PARAM_SCALERP_OUTPUT_CROP)
+#define PARAM_SCALERP_FLIP		INC_NUM(PARAM_SCALERP_ROTATION)
+#define PARAM_SCALERP_OTF_OUTPUT	INC_NUM(PARAM_SCALERP_FLIP)
+#define PARAM_SCALERP_DMA_OUTPUT	INC_NUM(PARAM_SCALERP_OTF_OUTPUT)
+#define PARAM_FD_CONTROL		INC_NUM(PARAM_SCALERP_DMA_OUTPUT)
+#define PARAM_FD_OTF_INPUT		INC_NUM(PARAM_FD_CONTROL)
+#define PARAM_FD_DMA_INPUT		INC_NUM(PARAM_FD_OTF_INPUT)
+#define PARAM_FD_CONFIG			INC_NUM(PARAM_FD_DMA_INPUT)
+#define PARAM_END			INC_NUM(PARAM_FD_CONFIG)
+
+#define PARAM_STRNUM_GLOBAL		(PARAM_GLOBAL_SHOTMODE)
+#define PARAM_RANGE_GLOBAL		1
+#define PARAM_STRNUM_SENSOR		(PARAM_SENSOR_BYPASS)
+#define PARAM_RANGE_SENSOR		5
+#define PARAM_STRNUM_BUFFER		(PARAM_BUFFER_BYPASS)
+#define PARAM_RANGE_BUFFER		3
+#define PARAM_STRNUM_ISP		(PARAM_ISP_BYPASS)
+#define PARAM_RANGE_ISP			15
+#define PARAM_STRNUM_DRC		(PARAM_DRC_BYPASS)
+#define PARAM_RANGE_DRC			4
+#define PARAM_STRNUM_SCALERC		(PARAM_SCALERC_BYPASS)
+#define PARAM_RANGE_SCALERC		7
+#define PARAM_STRNUM_ODC		(PARAM_ODC_BYPASS)
+#define PARAM_RANGE_ODC			3
+#define PARAM_STRNUM_DIS		(PARAM_DIS_BYPASS)
+#define PARAM_RANGE_DIS			3
+#define PARAM_STRNUM_TDNR		(PARAM_TDNR_BYPASS)
+#define PARAM_RANGE_TDNR		5
+#define PARAM_STRNUM_SCALERP		(PARAM_SCALERP_BYPASS)
+#define PARAM_RANGE_SCALERP		9
+#define PARAM_STRNUM_LHFD		(PARAM_FD_BYPASS)
+#define PARAM_RANGE_LHFD		4
+
+#define PARAM_LOW_MASK		(0xFFFFFFFF)
+#define PARAM_HIGH_MASK		(0x07FFFFFF)
+
+/* Enumerations
+*
+*/
+/* ----------------------  INTR map-------------------------------- */
+enum interrupt_map {
+	INTR_GENERAL = 0,
+	INTR_FRAME_DONE_ISP = 1,
+	INTR_FRAME_DONE_SCALERC = 2,
+	INTR_FRAME_DONE_TDNR = 3,
+	INTR_FRAME_DONE_SCALERP = 4
+};
+
+/* ----------------------  Input  ----------------------------------- */
+enum control_command {
+	CONTROL_COMMAND_STOP	= 0,
+	CONTROL_COMMAND_START	= 1
+};
+
+enum bypass_command {
+	CONTROL_BYPASS_DISABLE		= 0,
+	CONTROL_BYPASS_ENABLE		= 1
+};
+
+enum control_error {
+	CONTROL_ERROR_NO		= 0
+};
+
+enum otf_input_command {
+	OTF_INPUT_COMMAND_DISABLE	= 0,
+	OTF_INPUT_COMMAND_ENABLE	= 1
+};
+
+enum otf_input_format {
+	OTF_INPUT_FORMAT_BAYER		= 0, /* 1 Channel */
+	OTF_INPUT_FORMAT_YUV444		= 1, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV422		= 2, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV420		= 3, /* 3 Channel */
+	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
+	OTF_INPUT_FORMAT_BAYER_DMA	= 11,
+};
+
+enum otf_input_bitwidth {
+	OTF_INPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_INPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_INPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_INPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_INPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_input_order {
+	OTF_INPUT_ORDER_BAYER_GR_BG	= 0,
+};
+
+enum otf_intput_error {
+	OTF_INPUT_ERROR_NO		= 0 /* Input setting is done */
+};
+
+enum dma_input_command {
+	DMA_INPUT_COMMAND_DISABLE	= 0,
+	DMA_INPUT_COMMAND_ENABLE	= 1,
+	DMA_INPUT_COMMAND_BUF_MNGR	= 2,
+	DMA_INPUT_COMMAND_RUN_SINGLE	= 3,
+};
+
+enum dma_inut_format {
+	DMA_INPUT_FORMAT_BAYER		= 0,
+	DMA_INPUT_FORMAT_YUV444		= 1,
+	DMA_INPUT_FORMAT_YUV422		= 2,
+	DMA_INPUT_FORMAT_YUV420		= 3,
+};
+
+enum dma_input_bitwidth {
+	DMA_INPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_INPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_INPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_INPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_INPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_input_plane {
+	DMA_INPUT_PLANE_3	= 3,
+	DMA_INPUT_PLANE_2	= 2,
+	DMA_INPUT_PLANE_1	= 1
+};
+
+enum dma_input_order {
+	/* (for DMA_INPUT_PLANE_3) */
+	DMA_INPUT_ORDER_NO	= 0,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CbCr	= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CrCb	= 2,
+	/* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
+	DMA_INPUT_ORDER_YCbCr	= 3,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YYCbCr	= 4,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCbYCr	= 5,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCrYCb	= 6,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CbYCrY	= 7,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CrYCbY	= 8,
+	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
+	DMA_INPUT_ORDER_GR_BG	= 9
+};
+
+enum dma_input_error {
+	DMA_INPUT_ERROR_NO	= 0 /*  DMA input setting is done */
+};
+
+/* ----------------------  Output  ----------------------------------- */
+enum otf_output_crop {
+	OTF_OUTPUT_CROP_DISABLE		= 0,
+	OTF_OUTPUT_CROP_ENABLE		= 1
+};
+
+enum otf_output_command {
+	OTF_OUTPUT_COMMAND_DISABLE	= 0,
+	OTF_OUTPUT_COMMAND_ENABLE	= 1
+};
+
+enum orf_output_format {
+	OTF_OUTPUT_FORMAT_YUV444	= 1,
+	OTF_OUTPUT_FORMAT_YUV422	= 2,
+	OTF_OUTPUT_FORMAT_YUV420	= 3,
+	OTF_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum otf_output_bitwidth {
+	OTF_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_output_order {
+	OTF_OUTPUT_ORDER_BAYER_GR_BG	= 0,
+};
+
+enum otf_output_error {
+	OTF_OUTPUT_ERROR_NO = 0 /* Output Setting is done */
+};
+
+enum dma_output_command {
+	DMA_OUTPUT_COMMAND_DISABLE	= 0,
+	DMA_OUTPUT_COMMAND_ENABLE	= 1,
+	DMA_OUTPUT_COMMAND_BUF_MNGR	= 2,
+	DMA_OUTPUT_UPDATE_MASK_BITS	= 3
+};
+
+enum dma_output_format {
+	DMA_OUTPUT_FORMAT_BAYER		= 0,
+	DMA_OUTPUT_FORMAT_YUV444	= 1,
+	DMA_OUTPUT_FORMAT_YUV422	= 2,
+	DMA_OUTPUT_FORMAT_YUV420	= 3,
+	DMA_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum dma_output_bitwidth {
+	DMA_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_output_plane {
+	DMA_OUTPUT_PLANE_3		= 3,
+	DMA_OUTPUT_PLANE_2		= 2,
+	DMA_OUTPUT_PLANE_1		= 1
+};
+
+enum dma_output_order {
+	DMA_OUTPUT_ORDER_NO		= 0,
+	/* (for DMA_OUTPUT_PLANE_3) */
+	DMA_OUTPUT_ORDER_CbCr		= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_CrCb		= 2,
+	/* (only valid at DMA_OUTPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_YYCbCr		= 3,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCbYCr		= 4,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCrYCb		= 5,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbYCrY		= 6,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrYCbY		= 7,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCbCr		= 8,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrYCb		= 9,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrCbY		= 10,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbYCr		= 11,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCrCb		= 12,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbCrY		= 13,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_BGR		= 14,
+	/* (only valid at DMA_OUTPUT_FORMAT_RGB) */
+	DMA_OUTPUT_ORDER_GB_BG		= 15
+	/* (only valid at DMA_OUTPUT_FORMAT_BAYER) */
+};
+
+enum dma_output_notify_dma_done {
+	DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	= 0,
+	DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE	= 1,
+};
+
+enum dma_output_error {
+	DMA_OUTPUT_ERROR_NO		= 0 /* DMA output setting is done */
+};
+
+/* ----------------------  Global  ----------------------------------- */
+enum global_shotmode_error {
+	GLOBAL_SHOTMODE_ERROR_NO	= 0 /* shot-mode setting is done */
+};
+
+/* -------------------------  AA  ------------------------------------ */
+enum isp_lock_command {
+	ISP_AA_COMMAND_START	= 0,
+	ISP_AA_COMMAND_STOP	= 1
+};
+
+enum isp_lock_target {
+	ISP_AA_TARGET_AF	= 1,
+	ISP_AA_TARGET_AE	= 2,
+	ISP_AA_TARGET_AWB	= 4
+};
+
+enum isp_af_mode {
+	ISP_AF_MODE_MANUAL		= 0,
+	ISP_AF_MODE_SINGLE		= 1,
+	ISP_AF_MODE_CONTINUOUS		= 2,
+	ISP_AF_MODE_TOUCH		= 3,
+	ISP_AF_MODE_SLEEP		= 4,
+	ISP_AF_MODE_INIT		= 5,
+	ISP_AF_MODE_SET_CENTER_WINDOW	= 6,
+	ISP_AF_MODE_SET_TOUCH_WINDOW	= 7,
+	ISP_AF_SET_FACE_WINDOW		= 8
+};
+
+enum isp_af_face {
+	ISP_AF_FACE_DISABLE		= 0,
+	ISP_AF_FACE_ENABLE		= 1
+};
+
+enum isp_af_scene {
+	ISP_AF_SCENE_NORMAL		= 0,
+	ISP_AF_SCENE_MACRO		= 1
+};
+
+enum isp_af_sleep {
+	ISP_AF_SLEEP_OFF		= 0,
+	ISP_AF_SLEEP_ON			= 1
+};
+
+enum isp_af_continuous {
+	ISP_AF_CONTINUOUS_DISABLE	= 0,
+	ISP_AF_CONTINUOUS_ENABLE	= 1
+};
+
+enum isp_af_error {
+	ISP_AF_ERROR_NO			= 0, /* AF mode change is done */
+	ISP_AF_EROOR_NO_LOCK_DONE	= 1  /* AF lock is done */
+};
+
+/* -------------------------  Flash  ------------------------------------- */
+enum isp_flash_command {
+	ISP_FLASH_COMMAND_DISABLE	= 0 ,
+	ISP_FLASH_COMMAND_MANUALON	= 1, /* (forced flash) */
+	ISP_FLASH_COMMAND_AUTO		= 2,
+	ISP_FLASH_COMMAND_TORCH		= 3  /* 3 sec */
+};
+
+enum isp_flash_redeye {
+	ISP_FLASH_REDEYE_DISABLE	= 0,
+	ISP_FLASH_REDEYE_ENABLE		= 1
+};
+
+enum isp_flash_error {
+	ISP_FLASH_ERROR_NO		= 0 /* Flash setting is done */
+};
+
+/* --------------------------  AWB  ------------------------------------ */
+enum isp_awb_command {
+	ISP_AWB_COMMAND_AUTO		= 0,
+	ISP_AWB_COMMAND_ILLUMINATION	= 1,
+	ISP_AWB_COMMAND_MANUAL	= 2
+};
+
+enum isp_awb_illumination {
+	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
+	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
+	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
+	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
+};
+
+enum isp_awb_error {
+	ISP_AWB_ERROR_NO		= 0 /* AWB setting is done */
+};
+
+/* --------------------------  Effect  ----------------------------------- */
+enum isp_imageeffect_command {
+	ISP_IMAGE_EFFECT_DISABLE		= 0,
+	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
+	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
+	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
+	ISP_IMAGE_EFFECT_SEPIA			= 4
+};
+
+enum isp_imageeffect_error {
+	ISP_IMAGE_EFFECT_ERROR_NO	= 0 /* Image effect setting is done */
+};
+
+/* ---------------------------  ISO  ------------------------------------ */
+enum isp_iso_command {
+	ISP_ISO_COMMAND_AUTO		= 0,
+	ISP_ISO_COMMAND_MANUAL		= 1
+};
+
+enum iso_error {
+	ISP_ISO_ERROR_NO		= 0 /* ISO setting is done */
+};
+
+/* --------------------------  Adjust  ----------------------------------- */
+enum iso_adjust_command {
+	ISP_ADJUST_COMMAND_AUTO			= 0,
+	ISP_ADJUST_COMMAND_MANUAL_CONTRAST	= (1 << 0),
+	ISP_ADJUST_COMMAND_MANUAL_SATURATION	= (1 << 1),
+	ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	= (1 << 2),
+	ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	= (1 << 3),
+	ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	= (1 << 4),
+	ISP_ADJUST_COMMAND_MANUAL_HUE		= (1 << 5),
+	ISP_ADJUST_COMMAND_MANUAL_ALL		= 0x7F
+};
+
+enum isp_adjust_error {
+	ISP_ADJUST_ERROR_NO		= 0 /* Adjust setting is done */
+};
+
+/* -------------------------  Metering  ---------------------------------- */
+enum isp_metering_command {
+	ISP_METERING_COMMAND_AVERAGE	= 0,
+	ISP_METERING_COMMAND_SPOT	= 1,
+	ISP_METERING_COMMAND_MATRIX	= 2,
+	ISP_METERING_COMMAND_CENTER	= 3
+};
+
+enum isp_metering_error {
+	ISP_METERING_ERROR_NO	= 0 /* Metering setting is done */
+};
+
+/* --------------------------  AFC  ----------------------------------- */
+enum isp_afc_command {
+	ISP_AFC_COMMAND_DISABLE		= 0,
+	ISP_AFC_COMMAND_AUTO		= 1,
+	ISP_AFC_COMMAND_MANUAL		= 2
+};
+
+enum isp_afc_manual {
+	ISP_AFC_MANUAL_50HZ		= 50,
+	ISP_AFC_MANUAL_60HZ		= 60
+};
+
+enum isp_afc_error {
+	ISP_AFC_ERROR_NO	= 0 /* AFC setting is done */
+};
+
+enum isp_scene_command {
+	ISP_SCENE_NONE		= 0,
+	ISP_SCENE_PORTRAIT	= 1,
+	ISP_SCENE_LANDSCAPE     = 2,
+	ISP_SCENE_SPORTS        = 3,
+	ISP_SCENE_PARTYINDOOR	= 4,
+	ISP_SCENE_BEACHSNOW	= 5,
+	ISP_SCENE_SUNSET	= 6,
+	ISP_SCENE_DAWN		= 7,
+	ISP_SCENE_FALL		= 8,
+	ISP_SCENE_NIGHT		= 9,
+	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
+	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
+	ISP_SCENE_FIRE			= 12,
+	ISP_SCENE_TEXT			= 13,
+	ISP_SCENE_CANDLE		= 14
+};
+
+/* --------------------------  Scaler  --------------------------------- */
+enum scaler_imageeffect_command {
+	SCALER_IMAGE_EFFECT_COMMNAD_DISABLE	= 0,
+	SCALER_IMAGE_EFFECT_COMMNAD_SEPIA_CB	= 1,
+	SCALER_IMAGE_EFFECT_COMMAND_SEPIA_CR	= 2,
+	SCALER_IMAGE_EFFECT_COMMAND_NEGATIVE	= 3,
+	SCALER_IMAGE_EFFECT_COMMAND_ARTFREEZE	= 4,
+	SCALER_IMAGE_EFFECT_COMMAND_EMBOSSING	= 5,
+	SCALER_IMAGE_EFFECT_COMMAND_SILHOUETTE	= 6
+};
+
+enum scaler_imageeffect_error {
+	SCALER_IMAGE_EFFECT_ERROR_NO		= 0
+};
+
+enum scaler_crop_command {
+	SCALER_CROP_COMMAND_DISABLE		= 0,
+	SCALER_CROP_COMMAND_ENABLE		= 1
+};
+
+enum scaler_crop_error {
+	SCALER_CROP_ERROR_NO			= 0 /* crop setting is done */
+};
+
+enum scaler_scaling_command {
+	SCALER_SCALING_COMMNAD_DISABLE		= 0,
+	SCALER_SCALING_COMMAND_UP		= 1,
+	SCALER_SCALING_COMMAND_DOWN		= 2
+};
+
+enum scaler_scaling_error {
+	SCALER_SCALING_ERROR_NO			= 0
+};
+
+enum scaler_rotation_command {
+	SCALER_ROTATION_COMMAND_DISABLE		= 0,
+	SCALER_ROTATION_COMMAND_CLOCKWISE90	= 1
+};
+
+enum scaler_rotation_error {
+	SCALER_ROTATION_ERROR_NO		= 0
+};
+
+enum scaler_flip_command {
+	SCALER_FLIP_COMMAND_NORMAL		= 0,
+	SCALER_FLIP_COMMAND_X_MIRROR		= 1,
+	SCALER_FLIP_COMMAND_Y_MIRROR		= 2,
+	SCALER_FLIP_COMMAND_XY_MIRROR		= 3 /* (180 rotation) */
+};
+
+enum scaler_flip_error {
+	SCALER_FLIP_ERROR_NO			= 0 /* flip setting is done */
+};
+
+/* --------------------------  3DNR  ----------------------------------- */
+enum tdnr_1st_frame_command {
+	TDNR_1ST_FRAME_COMMAND_NOPROCESSING	= 0,
+	TDNR_1ST_FRAME_COMMAND_2DNR		= 1
+};
+
+enum tdnr_1st_frame_error {
+	TDNR_1ST_FRAME_ERROR_NO			= 0
+		/*1st frame setting is done*/
+};
+
+/* ----------------------------  FD  ------------------------------------- */
+enum fd_config_command {
+	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
+	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
+	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
+	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
+	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
+	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
+	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
+	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
+	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
+};
+
+enum fd_config_roll_angle {
+	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
+	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
+	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
+};
+
+enum fd_config_yaw_angle {
+	FD_CONFIG_YAW_ANGLE_0			= 0,
+	FD_CONFIG_YAW_ANGLE_45			= 1,
+	FD_CONFIG_YAW_ANGLE_90			= 2,
+	FD_CONFIG_YAW_ANGLE_45_90		= 3,
+};
+
+enum fd_config_smile_mode {
+	FD_CONFIG_SMILE_MODE_DISABLE		= 0,
+	FD_CONFIG_SMILE_MODE_ENABLE		= 1
+};
+
+enum fd_config_blink_mode {
+	FD_CONFIG_BLINK_MODE_DISABLE		= 0,
+	FD_CONFIG_BLINK_MODE_ENABLE		= 1
+};
+
+enum fd_config_eye_result {
+	FD_CONFIG_EYES_DETECT_DISABLE		= 0,
+	FD_CONFIG_EYES_DETECT_ENABLE		= 1
+};
+
+enum fd_config_mouth_result {
+	FD_CONFIG_MOUTH_DETECT_DISABLE		= 0,
+	FD_CONFIG_MOUTH_DETECT_ENABLE		= 1
+};
+
+enum fd_config_orientation {
+	FD_CONFIG_ORIENTATION_DISABLE		= 0,
+	FD_CONFIG_ORIENTATION_ENABLE		= 1
+};
+
+struct param_control {
+	u32	cmd;
+	u32	bypass;
+	u32 buffer_address;
+	u32 buffer_number;
+	u32 first_drop_frame;
+	u32 run_mode;			/* 0: continuous, 1: single */
+	u32	reserved[PARAMETER_MAX_MEMBER-7];
+	u32	err;
+};
+
+struct param_otf_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	crop_width;
+	u32	crop_height;
+	u32	frametime_min;
+	u32	frametime_max;
+	u32	reserved[PARAMETER_MAX_MEMBER-13];
+	u32	err;
+};
+
+struct param_dma_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	reserved[PARAMETER_MAX_MEMBER-10];
+	u32	err;
+};
+
+struct param_otf_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	reserved[PARAMETER_MAX_MEMBER-7];
+	u32	err;
+};
+
+struct param_dma_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	notify_dma_done;
+	u32	dma_out_mask;
+	u32	reserved[PARAMETER_MAX_MEMBER-12];
+	u32	err;
+};
+
+struct param_global_shotmode {
+	u32	cmd;
+	u32	skip_frames;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_sensor_framerate {
+	u32	frame_rate;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_aa {
+	u32	cmd;
+	u32	target;
+	u32	mode;
+	u32	scene;
+	u32	sleep;
+	u32	face;
+	u32	touch_x;
+	u32	touch_y;
+	u32	manual_af_setting;
+	u32	reserved[PARAMETER_MAX_MEMBER-10];
+	u32	err;
+};
+struct param_isp_flash {
+	u32	cmd;
+	u32	redeye;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_awb {
+	u32	cmd;
+	u32	illumination;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_imageeffect {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_iso {
+	u32	cmd;
+	u32	value;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_adjust {
+	u32	cmd;
+	s32	contrast;
+	s32	saturation;
+	s32	sharpness;
+	s32	exposure;
+	s32	brightness;
+	s32	hue;
+	u32	reserved[PARAMETER_MAX_MEMBER-8];
+	u32	err;
+};
+
+struct param_isp_metering {
+	u32	cmd;
+	u32	win_pos_x;
+	u32	win_pos_y;
+	u32	win_width;
+	u32	win_height;
+	u32	reserved[PARAMETER_MAX_MEMBER-6];
+	u32	err;
+};
+
+struct param_isp_afc {
+	u32	cmd;
+	u32	manual;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_scaler_imageeffect {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_scaler_input_crop {
+	u32  cmd;
+	u32  pos_x;
+	u32  pos_y;
+	u32  crop_width;
+	u32  crop_height;
+	u32  in_width;
+	u32  in_height;
+	u32  out_width;
+	u32  out_height;
+	u32  reserved[PARAMETER_MAX_MEMBER-10];
+	u32  err;
+};
+
+struct param_scaler_output_crop {
+	u32  cmd;
+	u32  pos_x;
+	u32  pos_y;
+	u32  crop_width;
+	u32  crop_height;
+	u32  format;
+	u32  reserved[PARAMETER_MAX_MEMBER-7];
+	u32  err;
+};
+
+struct param_scaler_rotation {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_scaler_flip {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_3dnr_1stframe {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_fd_config {
+	u32	cmd;
+	u32	max_number;
+	u32	roll_angle;
+	u32	yaw_angle;
+	s32	smile_mode;
+	s32	blink_mode;
+	u32	eye_detect;
+	u32	mouth_detect;
+	u32	orientation;
+	u32	orientation_value;
+	u32	reserved[PARAMETER_MAX_MEMBER-11];
+	u32	err;
+};
+
+struct global_param {
+	struct param_global_shotmode	shotmode; /* 0 */
+};
+
+/* To be added */
+struct sensor_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+	struct param_sensor_framerate	frame_rate;
+	struct param_dma_output		dma_output;
+};
+
+struct buffer_param {
+	struct param_control	control;
+	struct param_otf_input	otf_input;
+	struct param_otf_output	otf_output;
+};
+
+struct isp_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma1_input;
+	struct param_dma_input		dma2_input;
+	struct param_isp_aa		aa;
+	struct param_isp_flash		flash;
+	struct param_isp_awb		awb;
+	struct param_isp_imageeffect	effect;
+	struct param_isp_iso		iso;
+	struct param_isp_adjust		adjust;
+	struct param_isp_metering	metering;
+	struct param_isp_afc		afc;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma1_output;
+	struct param_dma_output		dma2_output;
+};
+
+struct drc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma_input;
+	struct param_otf_output		otf_output;
+};
+
+struct scalerc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_scaler_imageeffect	effect;
+	struct param_scaler_input_crop	input_crop;
+	struct param_scaler_output_crop	 output_crop;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma_output;
+};
+
+struct odc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct dis_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct tdnr_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_3dnr_1stframe	frame;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma_output;
+};
+
+struct scalerp_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_scaler_imageeffect		effect;
+	struct param_scaler_input_crop	input_crop;
+	struct param_scaler_output_crop	 output_crop;
+	struct param_scaler_rotation		rotation;
+	struct param_scaler_flip		flip;
+	struct param_otf_output			otf_output;
+	struct param_dma_output			dma_output;
+};
+
+struct fd_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_dma_input			dma_input;
+	struct param_fd_config			config;
+};
+
+struct is_param_region {
+	struct global_param	global;
+	struct sensor_param	sensor;
+	struct buffer_param	buf;
+	struct isp_param	isp;
+	struct drc_param	drc;
+	struct scalerc_param	scalerc;
+	struct odc_param	odc;
+	struct dis_param	dis;
+	struct tdnr_param	tdnr;
+	struct scalerp_param	scalerp;
+	struct fd_param		fd;
+};
+
+#define	NUMBER_OF_GAMMA_CURVE_POINTS	32
+
+struct is_sensor_tune {
+	u32 exposure;
+	u32 analog_gain;
+	u32 frame_rate;
+	u32 actuator_pos;
+};
+
+struct is_tune_gammacurve {
+	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
+};
+
+struct is_isp_tune {
+	/* Brightness level : range 0~100, default : 7 */
+	u32 brightness_level;
+	/* Contrast level : range -127~127, default : 0 */
+	s32 contrast_level;
+	/* Saturation level : range -127~127, default : 0 */
+	s32 saturation_level;
+	s32 gamma_level;
+	struct is_tune_gammacurve gamma_curve[4];
+	/* Hue : range -127~127, default : 0 */
+	s32 hue;
+	/* Sharpness blur : range -127~127, default : 0 */
+	s32 sharpness_blur;
+	/* Despeckle : range -127~127, default : 0 */
+	s32 despeckle;
+	/* Edge color supression : range -127~127, default : 0 */
+	s32 edge_color_supression;
+	/* Noise reduction : range -127~127, default : 0 */
+	s32 noise_reduction;
+	/* (32*4 + 9)*4 = 548 bytes */
+};
+
+struct is_tune_region {
+	struct is_sensor_tune sensor_tune;
+	struct is_isp_tune isp_tune;
+};
+
+struct rational_t {
+	u32 num;
+	u32 den;
+};
+
+struct srational_t {
+	s32 num;
+	s32 den;
+};
+
+#define FLASH_FIRED_SHIFT	0
+#define FLASH_NOT_FIRED		0
+#define FLASH_FIRED		1
+
+#define FLASH_STROBE_SHIFT				1
+#define FLASH_STROBE_NO_DETECTION			0
+#define FLASH_STROBE_RESERVED				1
+#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED		2
+#define FLASH_STROBE_RETURN_LIGHT_DETECTED		3
+
+#define FLASH_MODE_SHIFT			3
+#define FLASH_MODE_UNKNOWN			0
+#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
+#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
+#define FLASH_MODE_AUTO_MODE			3
+
+#define FLASH_FUNCTION_SHIFT		5
+#define FLASH_FUNCTION_PRESENT		0
+#define FLASH_FUNCTION_NONE		1
+
+#define FLASH_RED_EYE_SHIFT		6
+#define FLASH_RED_EYE_DISABLED		0
+#define FLASH_RED_EYE_SUPPORTED		1
+
+enum apex_aperture_value {
+	F1_0		= 0,
+	F1_4		= 1,
+	F2_0		= 2,
+	F2_8		= 3,
+	F4_0		= 4,
+	F5_6		= 5,
+	F8_9		= 6,
+	F11_0		= 7,
+	F16_0		= 8,
+	F22_0		= 9,
+	F32_0		= 10,
+};
+
+struct exif_attribute {
+	struct rational_t exposure_time;
+	struct srational_t shutter_speed;
+	u32 iso_speed_rating;
+	u32 flash;
+	struct srational_t brightness;
+};
+
+struct is_frame_header {
+	u32 valid;
+	u32 bad_mark;
+	u32 captured;
+	u32 frame_number;
+	struct exif_attribute	exif;
+};
+
+struct is_fd_rect {
+	u32 offset_x;
+	u32 offset_y;
+	u32 width;
+	u32 height;
+};
+
+struct is_face_marker {
+	u32	frame_number;
+	struct is_fd_rect face;
+	struct is_fd_rect left_eye;
+	struct is_fd_rect right_eye;
+	struct is_fd_rect mouth;
+	u32	roll_angle;
+	u32  yaw_angle;
+	u32	confidence;
+	u32	smile_level;
+	u32	blink_level;
+};
+
+#define MAX_FRAME_COUNT		8
+#define MAX_FRAME_COUNT_PREVIEW	4
+#define MAX_FRAME_COUNT_CAPTURE	1
+#define MAX_FACE_COUNT		16
+
+#define MAX_SHARED_COUNT	500
+
+struct is_region {
+	struct is_param_region	parameter;
+	struct is_tune_region	tune;
+	struct is_frame_header	header[MAX_FRAME_COUNT];
+	struct is_face_marker	face[MAX_FACE_COUNT];
+	u32			shared[MAX_SHARED_COUNT];
+};
+
+struct is_debug_frame_descriptor {
+	u32	sensor_frame_time;
+	u32	sensor_exposure_time;
+	u32	sensor_analog_gain;
+	u32	req_lei;
+};
+
+#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM	(30 * 20)	/* 600 frame */
+#define MAX_VERSION_DISPLAY_BUF		(32)
+
+struct is_share_region {
+	u32	frame_time;
+	u32	exposure_time;
+	u32	analog_gain;
+
+	u32	r_gain;
+	u32	g_gain;
+	u32	b_gain;
+
+	u32	af_position;
+	u32	af_status;
+	u32  	af_scene_type;
+
+	u32	frame_descp_onoff_control;
+	u32	frame_descp_update_done;
+	u32	frame_descp_idx;
+	u32  	frame_descp_max_idx;
+
+	struct is_debug_frame_descriptor
+		dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
+
+	u32 	chip_id;
+	u32 	chip_rev_no;
+	u8	ispfw_version_no[MAX_VERSION_DISPLAY_BUF];
+	u8	ispfw_version_date[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_version_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_revsion_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_version_date[MAX_VERSION_DISPLAY_BUF];
+};
+
+struct is_debug_control {
+	u32 uiWritePoint;	/* 0~500KB boundary*/
+	u32 uiAssertFlag;	/* 0:Not Inovked, 1:Invoked*/
+	u32 uiPAbortFlag;	/* 0:Not Inovked, 1:Invoked*/
+	u32 uiDAbortFlag;	/* 0:Not Inovked, 1:Invoked*/
+	u32 uiPDReadyFlag;	/* 0:Normal, 1:EnterIdle(Ready to power down)*/
+	u32 uiISPFrameErr;	/* Frame Error Count.*/
+	u32 uiDRCFrameErr;	/* Frame Error Count.*/
+	u32 uiSCCFrameErr;	/* Frame Error Count.*/
+	u32 uiODCFrameErr;	/* Frame Error Count.*/
+	u32 uiDISFrameErr;	/* Frame Error Count.*/
+	u32 uiTDNRFrameErr;	/* Frame Error Count.*/
+	u32 uiSCPFrameErr;	/* Frame Error Count.*/
+	u32 uiFDFrameErr;	/* Frame Error Count.*/
+	u32 uiISPFrameDrop;	/* Frame Drop Count.*/
+	u32 uiDRCFrameDrop;	/* Frame Drop Count.*/
+	u32 uiDISFrameDrop;	/* Frame Drop Count.*/
+};
+
+#endif
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-regs.h b/drivers/media/video/exynos/fimc-is-mc/fimc-is-regs.h
new file mode 100644
index 0000000..4883bc0
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-regs.h
@@ -0,0 +1,353 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+#include <mach/map.h>
+
+/* WDT_ISP register */
+#define WDT			0x00170000
+/* MCUCTL register */
+#define MCUCTL			0x00180000
+/* MCU Controller Register */
+#define MCUCTLR				(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)	((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)	((x) << 12)
+#define MCUCTLR_MSWRST			(1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR				(MCUCTL+0x04)
+#define BBOAR_BBOA(x)			((x) << 0)
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0				(MCUCTL+0x08)
+#define INTGR0_INTGC9			(1 << 25)
+#define INTGR0_INTGC8			(1 << 24)
+#define INTGR0_INTGC7			(1 << 23)
+#define INTGR0_INTGC6			(1 << 22)
+#define INTGR0_INTGC5			(1 << 21)
+#define INTGR0_INTGC4			(1 << 20)
+#define INTGR0_INTGC3			(1 << 19)
+#define INTGR0_INTGC2			(1 << 18)
+#define INTGR0_INTGC1			(1 << 17)
+#define INTGR0_INTGC0			(1 << 16)
+#define INTGR0_INTGD5			(1 << 5)
+#define INTGR0_INTGD4			(1 << 4)
+#define INTGR0_INTGD3			(1 << 3)
+#define INTGR0_INTGD2			(1 << 2)
+#define INTGR0_INTGD1			(1 << 1)
+#define INTGR0_INTGD0			(1 << 0)
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0				(MCUCTL+0x0c)
+#define INTCR0_INTCC9			(1 << 25)
+#define INTCR0_INTCC8			(1 << 24)
+#define INTCR0_INTCC7			(1 << 23)
+#define INTCR0_INTCC6			(1 << 22)
+#define INTCR0_INTCC5			(1 << 21)
+#define INTCR0_INTCC4			(1 << 20)
+#define INTCR0_INTCC3			(1 << 19)
+#define INTCR0_INTCC2			(1 << 18)
+#define INTCR0_INTCC1			(1 << 17)
+#define INTCR0_INTCC0			(1 << 16)
+#define INTCR0_INTCD5			(1 << 5)
+#define INTCR0_INTCD4			(1 << 4)
+#define INTCR0_INTCD3			(1 << 3)
+#define INTCR0_INTCD2			(1 << 2)
+#define INTCR0_INTCD1			(1 << 1)
+#define INTCR0_INTCD0			(1 << 0)
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0				(MCUCTL+0x10)
+#define INTMR0_INTMC9			(1 << 25)
+#define INTMR0_INTMC8			(1 << 24)
+#define INTMR0_INTMC7			(1 << 23)
+#define INTMR0_INTMC6			(1 << 22)
+#define INTMR0_INTMC5			(1 << 21)
+#define INTMR0_INTMC4			(1 << 20)
+#define INTMR0_INTMC3			(1 << 19)
+#define INTMR0_INTMC2			(1 << 18)
+#define INTMR0_INTMC1			(1 << 17)
+#define INTMR0_INTMC0			(1 << 16)
+#define INTMR0_INTMD5			(1 << 5)
+#define INTMR0_INTMD4			(1 << 4)
+#define INTMR0_INTMD3			(1 << 3)
+#define INTMR0_INTMD2			(1 << 2)
+#define INTMR0_INTMD1			(1 << 1)
+#define INTMR0_INTMD0			(1 << 0)
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0				(MCUCTL+0x14)
+#define INTSR0_GET_INTSD0(x)		(((x) >> 0) & 0x1)
+#define INTSR0_GET_INTSD1(x)		(((x) >> 1) & 0x1)
+#define INTSR0_GET_INTSD2(x)		(((x) >> 2) & 0x1)
+#define INTSR0_GET_INTSD3(x)		(((x) >> 3) & 0x1)
+#define INTSR0_GET_INTSD4(x)		(((x) >> 4) & 0x1)
+#define INTSR0_GET_INTSC0(x)		(((x) >> 16) & 0x1)
+#define INTSR0_GET_INTSC1(x)		(((x) >> 17) & 0x1)
+#define INTSR0_GET_INTSC2(x)		(((x) >> 18) & 0x1)
+#define INTSR0_GET_INTSC3(x)		(((x) >> 19) & 0x1)
+#define INTSR0_GET_INTSC4(x)		(((x) >> 20) & 0x1)
+#define INTSR0_GET_INTSC5(x)		(((x) >> 21) & 0x1)
+#define INTSR0_GET_INTSC6(x)		(((x) >> 22) & 0x1)
+#define INTSR0_GET_INTSC7(x)		(((x) >> 23) & 0x1)
+#define INTSR0_GET_INTSC8(x)		(((x) >> 24) & 0x1)
+#define INTSR0_GET_INTSC9(x)		(((x) >> 25) & 0x1)
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0				(MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD0(x)		(((x) >> 0) & 0x1)
+#define INTMSR0_GET_INTMSD1(x)		(((x) >> 1) & 0x1)
+#define INTMSR0_GET_INTMSD2(x)		(((x) >> 2) & 0x1)
+#define INTMSR0_GET_INTMSD3(x)		(((x) >> 3) & 0x1)
+#define INTMSR0_GET_INTMSD4(x)		(((x) >> 4) & 0x1)
+#define INTMSR0_GET_INTMSC0(x)		(((x) >> 16) & 0x1)
+#define INTMSR0_GET_INTMSC1(x)		(((x) >> 17) & 0x1)
+#define INTMSR0_GET_INTMSC2(x)		(((x) >> 18) & 0x1)
+#define INTMSR0_GET_INTMSC3(x)		(((x) >> 19) & 0x1)
+#define INTMSR0_GET_INTMSC4(x)		(((x) >> 20) & 0x1)
+#define INTMSR0_GET_INTMSC5(x)		(((x) >> 21) & 0x1)
+#define INTMSR0_GET_INTMSC6(x)		(((x) >> 22) & 0x1)
+#define INTMSR0_GET_INTMSC7(x)		(((x) >> 23) & 0x1)
+#define INTMSR0_GET_INTMSC8(x)		(((x) >> 24) & 0x1)
+#define INTMSR0_GET_INTMSC9(x)		(((x) >> 25) & 0x1)
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1				(MCUCTL+0x1c)
+#define INTGR1_INTGC9			(1 << 9)
+#define INTGR1_INTGC8			(1 << 8)
+#define INTGR1_INTGC7			(1 << 7)
+#define INTGR1_INTGC6			(1 << 6)
+#define INTGR1_INTGC5			(1 << 5)
+#define INTGR1_INTGC4			(1 << 4)
+#define INTGR1_INTGC3			(1 << 3)
+#define INTGR1_INTGC2			(1 << 2)
+#define INTGR1_INTGC1			(1 << 1)
+#define INTGR1_INTGC0			(1 << 0)
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1				(MCUCTL+0x20)
+#define INTCR1_INTCC9			(1 << 9)
+#define INTCR1_INTCC8			(1 << 8)
+#define INTCR1_INTCC7			(1 << 7)
+#define INTCR1_INTCC6			(1 << 6)
+#define INTCR1_INTCC5			(1 << 5)
+#define INTCR1_INTCC4			(1 << 4)
+#define INTCR1_INTCC3			(1 << 3)
+#define INTCR1_INTCC2			(1 << 2)
+#define INTCR1_INTCC1			(1 << 1)
+#define INTCR1_INTCC0			(1 << 0)
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1				(MCUCTL+0x24)
+#define INTMR1_INTMC9			(1 << 9)
+#define INTMR1_INTMC8			(1 << 8)
+#define INTMR1_INTMC7			(1 << 7)
+#define INTMR1_INTMC6			(1 << 6)
+#define INTMR1_INTMC5			(1 << 5)
+#define INTMR1_INTMC4			(1 << 4)
+#define INTMR1_INTMC3			(1 << 3)
+#define INTMR1_INTMC2			(1 << 2)
+#define INTMR1_INTMC1			(1 << 1)
+#define INTMR1_INTMC0			(1 << 0)
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1				(MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1				(MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2				(MCUCTL+0x30)
+#define INTCR2_INTCC21			(1 << 21)
+#define INTCR2_INTCC20			(1 << 20)
+#define INTCR2_INTCC19			(1 << 19)
+#define INTCR2_INTCC18			(1 << 18)
+#define INTCR2_INTCC17			(1 << 17)
+#define INTCR2_INTCC16			(1 << 16)
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2				(MCUCTL+0x34)
+#define INTMR2_INTMCIS25		(1 << 25)
+#define INTMR2_INTMCIS24		(1 << 24)
+#define INTMR2_INTMCIS23		(1 << 23)
+#define INTMR2_INTMCIS22		(1 << 22)
+#define INTMR2_INTMCIS21		(1 << 21)
+#define INTMR2_INTMCIS20		(1 << 20)
+#define INTMR2_INTMCIS19		(1 << 19)
+#define INTMR2_INTMCIS18		(1 << 18)
+#define INTMR2_INTMCIS17		(1 << 17)
+#define INTMR2_INTMCIS16		(1 << 16)
+#define INTMR2_INTMCIS15		(1 << 15)
+#define INTMR2_INTMCIS14		(1 << 14)
+#define INTMR2_INTMCIS13		(1 << 13)
+#define INTMR2_INTMCIS12		(1 << 12)
+#define INTMR2_INTMCIS11		(1 << 11)
+#define INTMR2_INTMCIS10		(1 << 10)
+#define INTMR2_INTMCIS9			(1 << 9)
+#define INTMR2_INTMCIS8			(1 << 8)
+#define INTMR2_INTMCIS7			(1 << 7)
+#define INTMR2_INTMCIS6			(1 << 6)
+#define INTMR2_INTMCIS5			(1 << 5)
+#define INTMR2_INTMCIS4			(1 << 4)
+#define INTMR2_INTMCIS3			(1 << 3)
+#define INTMR2_INTMCIS2			(1 << 2)
+#define INTMR2_INTMCIS1			(1 << 1)
+#define INTMR2_INTMCIS0			(1 << 0)
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2				(MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2				(MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR				(MCUCTL+0x40)
+#define GPOCTLR_GPOG17(x)		((x) << 17)
+#define GPOCTLR_GPOG16(x)		((x) << 16)
+#define GPOCTLR_GPOG15(x)		((x) << 15)
+#define GPOCTLR_GPOG14(x)		((x) << 14)
+#define GPOCTLR_GPOG13(x)		((x) << 13)
+#define GPOCTLR_GPOG12(x)		((x) << 12)
+#define GPOCTLR_GPOG11(x)		((x) << 11)
+#define GPOCTLR_GPOG10(x)		((x) << 10)
+#define GPOCTLR_GPOG9(x)		((x) << 9)
+#define GPOCTLR_GPOG8(x)		((x) << 8)
+#define GPOCTLR_GPOG7(x)		((x) << 7)
+#define GPOCTLR_GPOG6(x)		((x) << 6)
+#define GPOCTLR_GPOG5(x)		((x) << 5)
+#define GPOCTLR_GPOG4(x)		((x) << 4)
+#define GPOCTLR_GPOG3(x)		((x) << 3)
+#define GPOCTLR_GPOG2(x)		((x) << 2)
+#define GPOCTLR_GPOG1(x)		((x) << 1)
+#define GPOCTLR_GPOG0(x)		((x) << 0)
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR			(MCUCTL+0x44)
+#define GPOENCTLR_GPOEN17(x)		((x) << 17)
+#define GPOENCTLR_GPOEN16(x)		((x) << 16)
+#define GPOENCTLR_GPOEN15(x)		((x) << 15)
+#define GPOENCTLR_GPOEN14(x)		((x) << 14)
+#define GPOENCTLR_GPOEN13(x)		((x) << 13)
+#define GPOENCTLR_GPOEN12(x)		((x) << 12)
+#define GPOENCTLR_GPOEN11(x)		((x) << 11)
+#define GPOENCTLR_GPOEN10(x)		((x) << 10)
+#define GPOENCTLR_GPOEN9(x)		((x) << 9)
+#define GPOENCTLR_GPOEN8(x)		((x) << 8)
+#define GPOENCTLR_GPOEN7(x)		((x) << 7)
+#define GPOENCTLR_GPOEN6(x)		((x) << 6)
+#define GPOENCTLR_GPOEN5(x)		((x) << 5)
+#define GPOENCTLR_GPOEN4(x)		((x) << 4)
+#define GPOENCTLR_GPOEN3(x)		((x) << 3)
+#define GPOENCTLR_GPOEN2(x)		((x) << 2)
+#define GPOENCTLR_GPOEN1(x)		((x) << 1)
+#define GPOENCTLR_GPOEN0(x)		((x) << 0)
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR				(MCUCTL+0x48)
+/* IS Shared Register 0 between ISP CPU and HOST CPU */
+#define ISSR0			(MCUCTL+0x80)
+/* Command Host -> IS */
+/* IS Shared Register 1 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR1			(MCUCTL+0x84)
+/* IS Shared Register 2 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR2			(MCUCTL+0x88)
+/* IS Shared Register 3 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR3			(MCUCTL+0x8c)
+/* IS Shared Register 4 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR4			(MCUCTL+0x90)
+/* IS Shared Register 5 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR5			(MCUCTL+0x94)
+#define ISSR6			(MCUCTL+0x98)
+#define ISSR7			(MCUCTL+0x9c)
+#define ISSR8			(MCUCTL+0xa0)
+#define ISSR9			(MCUCTL+0xa4)
+/* IS Shared Register 10 between ISP CPU and HOST CPU */
+/* Command IS -> Host */
+#define ISSR10			(MCUCTL+0xa8)
+/* IS Shared Register 11 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR11			(MCUCTL+0xac)
+/* IS Shared Register 12 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR12			(MCUCTL+0xb0)
+/* IS Shared Register 13 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR13			(MCUCTL+0xb4)
+/* IS Shared Register 14 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR14			(MCUCTL+0xb8)
+/* IS Shared Register 15 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR15			(MCUCTL+0xbc)
+#define ISSR16			(MCUCTL+0xc0)
+#define ISSR17			(MCUCTL+0xc4)
+#define ISSR18			(MCUCTL+0xc8)
+#define ISSR19			(MCUCTL+0xcc)
+/* IS Shared Register 20 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : SENSOR ID */
+#define ISSR20			(MCUCTL+0xd0)
+/* IS Shared Register 21 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : PARAMETER 1 */
+#define ISSR21			(MCUCTL+0xd4)
+#define ISSR22			(MCUCTL+0xd8)
+#define ISSR23			(MCUCTL+0xdc)
+/* IS Shared Register 24 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : SENSOR ID */
+#define ISSR24			(MCUCTL+0xe0)
+/* IS Shared Register 25 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : PARAMETER 1 */
+#define ISSR25			(MCUCTL+0xe4)
+#define ISSR26			(MCUCTL+0xe8)
+#define ISSR27			(MCUCTL+0xec)
+/* IS Shared Register 28 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : SENSOR ID */
+#define ISSR28			(MCUCTL+0xf0)
+/* IS Shared Register 29 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : PARAMETER 1 */
+#define ISSR29			(MCUCTL+0xf4)
+#define ISSR30			(MCUCTL+0xf8)
+#define ISSR31			(MCUCTL+0xfc)
+/* IS Shared Register 32 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : SENSOR ID */
+#define ISSR32			(MCUCTL+0x100)
+/* IS Shared Register 33 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : PARAMETER 1 */
+#define ISSR33			(MCUCTL+0x104)
+#define ISSR34			(MCUCTL+0x108)
+#define ISSR35			(MCUCTL+0x10c)
+#define ISSR36			(MCUCTL+0x110)
+#define ISSR37			(MCUCTL+0x114)
+#define ISSR38			(MCUCTL+0x118)
+#define ISSR39			(MCUCTL+0x11c)
+#define ISSR40			(MCUCTL+0x120)
+#define ISSR41			(MCUCTL+0x124)
+#define ISSR42			(MCUCTL+0x128)
+#define ISSR43			(MCUCTL+0x12c)
+#define ISSR44			(MCUCTL+0x130)
+#define ISSR45			(MCUCTL+0x134)
+#define ISSR46			(MCUCTL+0x138)
+#define ISSR47			(MCUCTL+0x13c)
+#define ISSR48			(MCUCTL+0x140)
+#define ISSR49			(MCUCTL+0x144)
+#define ISSR50			(MCUCTL+0x148)
+#define ISSR51			(MCUCTL+0x14c)
+#define ISSR52			(MCUCTL+0x150)
+#define ISSR53			(MCUCTL+0x154)
+#define ISSR54			(MCUCTL+0x158)
+#define ISSR55			(MCUCTL+0x15c)
+#define ISSR56			(MCUCTL+0x160)
+#define ISSR57			(MCUCTL+0x164)
+#define ISSR58			(MCUCTL+0x168)
+#define ISSR59			(MCUCTL+0x16c)
+#define ISSR60			(MCUCTL+0x170)
+#define ISSR61			(MCUCTL+0x174)
+#define ISSR62			(MCUCTL+0x178)
+#define ISSR63			(MCUCTL+0x17c)
+
+/* PMU for FIMC-IS*/
+#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG	(S5P_VA_PMU  + 0x1584)
+#define PMUREG_ISP_ARM_CONFIGURATION		(S5P_VA_PMU  + 0x2280)
+#define PMUREG_ISP_ARM_STATUS			(S5P_VA_PMU  + 0x2284)
+#define PMUREG_ISP_ARM_OPTION			(S5P_VA_PMU  + 0x2288)
+#define PMUREG_ISP_LOW_POWER_OFF		(S5P_VA_PMU  + 0x0004)
+#define PMUREG_ISP_CONFIGURATION		(S5P_VA_PMU  + 0x4020)
+#define PMUREG_ISP_STATUS				(S5P_VA_PMU  + 0x4024)
+
+#endif
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-vb2.c b/drivers/media/video/exynos/fimc-is-mc/fimc-is-vb2.c
new file mode 100644
index 0000000..33b034d
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-vb2.c
@@ -0,0 +1,79 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * exynos5 fimc-is misc functions(mipi, fimc-lite control)
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <media/videobuf2-core.h>
+#include <linux/platform_device.h>
+#include "fimc-is-core.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *fimc_is_cma_init(struct fimc_is_dev *isp)
+{
+	return vb2_cma_phys_init(&isp->pdev->dev, NULL, 0, false);
+}
+
+int fimc_is_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void fimc_is_cma_suspend(void *alloc_ctx) {}
+void fimc_is_cma_set_cacheable(void *alloc_ctx, bool cacheable) {}
+
+int fimc_is_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct fimc_is_vb2 fimc_is_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= fimc_is_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= fimc_is_cma_resume,
+	.suspend	= fimc_is_cma_suspend,
+	.cache_flush	= fimc_is_cma_cache_flush,
+	.set_cacheable	= fimc_is_cma_set_cacheable,
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+static void *fimc_is_ion_init(struct fimc_is_dev *isp)
+{
+	return vb2_ion_create_context(&isp->pdev->dev, SZ_4K,
+					VB2ION_CTX_IOMMU | VB2ION_CTX_VMCONTIG);
+}
+
+static unsigned long plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+
+const struct fimc_is_vb2 fimc_is_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= fimc_is_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+};
+#endif
+
diff --git a/drivers/media/video/exynos/fimc-is-mc/fimc-is-video.c b/drivers/media/video/exynos/fimc-is-mc/fimc-is-video.c
new file mode 100644
index 0000000..7b54835
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is-mc/fimc-is-video.c
@@ -0,0 +1,3413 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * exynos5 fimc-is video functions
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <mach/videonode.h>
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+#include <mach/dev.h>
+#endif
+#include <media/exynos_mc.h>
+#include <linux/cma.h>
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/scatterlist.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/v4l2-mediabus.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-helper.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-err.h"
+#include "fimc-is-misc.h"
+
+static struct fimc_is_fmt fimc_is_formats[] = {
+	 {
+		.name		= "YUV 4:2:2 packed, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+		.num_planes	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_YUYV8_2X8,
+	}, {
+		.name		= "YUV 4:2:2 packed, CbYCrY",
+		.pixelformat	= V4L2_PIX_FMT_UYVY,
+		.num_planes	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_UYVY8_2X8,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV422P,
+		.num_planes	= 1,
+	}, {
+		.name		= "YUV 4:2:0 planar, YCbCr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420,
+		.num_planes	= 1,
+	}, {
+		.name		= "YUV 4:2:0 planar, YCbCr",
+		.pixelformat	= V4L2_PIX_FMT_YVU420,
+		.num_planes	= 1,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12,
+		.num_planes	= 1,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21,
+		.num_planes	= 1,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12M,
+		.num_planes	= 2,
+	}, {
+		.name		= "YVU 4:2:0 non-contiguous 2-planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21M,
+		.num_planes	= 2,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420M,
+		.num_planes	= 3,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cr/Cb",
+		.pixelformat	= V4L2_PIX_FMT_YVU420M,
+		.num_planes	= 3,
+	}, {
+		.name		= "BAYER 10 bit",
+		.pixelformat	= V4L2_PIX_FMT_SBGGR10,
+		.num_planes	= 1,
+	}, {
+		.name		= "BAYER 12 bit",
+		.pixelformat	= V4L2_PIX_FMT_SBGGR12,
+		.num_planes	= 1,
+	},
+};
+
+
+static struct fimc_is_fmt *find_format(u32 *pixelformat,
+					u32 *mbus_code,
+					int index)
+{
+	struct fimc_is_fmt *fmt, *def_fmt = NULL;
+	unsigned int i;
+
+	if (index >= ARRAY_SIZE(fimc_is_formats))
+		return NULL;
+
+	for (i = 0; i < ARRAY_SIZE(fimc_is_formats); ++i) {
+		fmt = &fimc_is_formats[i];
+		if (pixelformat && fmt->pixelformat == *pixelformat)
+			return fmt;
+		if (mbus_code && fmt->mbus_code == *mbus_code)
+			return fmt;
+		if (index == i)
+			def_fmt = fmt;
+	}
+	return def_fmt;
+
+}
+
+static void set_plane_size(struct fimc_is_frame *frame, unsigned long sizes[])
+{
+	dbg(" ");
+	switch (frame->format.pixelformat) {
+	case V4L2_PIX_FMT_YUYV:
+		dbg("V4L2_PIX_FMT_YUYV(w:%d)(h:%d)\n",
+				frame->width, frame->height);
+		sizes[0] =  frame->width*frame->height*2;
+		break;
+	case V4L2_PIX_FMT_NV12M:
+		dbg("V4L2_PIX_FMT_NV12M(w:%d)(h:%d)\n",
+				frame->width, frame->height);
+		sizes[0] =  frame->width*frame->height;
+		sizes[1] =  frame->width*frame->height/2;
+		break;
+	case V4L2_PIX_FMT_YVU420M:
+		dbg("V4L2_PIX_FMT_YVU420M(w:%d)(h:%d)\n",
+				frame->width, frame->height);
+		sizes[0] =  frame->width*frame->height;
+		sizes[1] =  frame->width*frame->height/4;
+		sizes[2] =  frame->width*frame->height/4;
+		break;
+	case  V4L2_PIX_FMT_SBGGR10:
+		dbg("V4L2_PIX_FMT_SBGGR10(w:%d)(h:%d)\n",
+				frame->width, frame->height);
+		sizes[0] =  frame->width*frame->height*2;
+		break;
+	case V4L2_PIX_FMT_SBGGR12:
+		dbg("V4L2_PIX_FMT_SBGGR12(w:%d)(h:%d)\n",
+				frame->width, frame->height);
+		sizes[0] =  frame->width*frame->height*2;
+		break;
+	}
+}
+
+/*************************************************************************/
+/* video file opertation */
+/************************************************************************/
+
+static int fimc_is_scalerc_video_open(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	mutex_lock(&isp->busfreq_lock);
+	isp->busfreq_num++;
+	if (isp->busfreq_num == 1) {
+		dev_lock(isp->bus_dev, &isp->pdev->dev,
+			(FIMC_IS_FREQ_MIF * 1000) + FIMC_IS_FREQ_INT);
+		dbg("busfreq locked on <%d/%d>MHz\n",
+			FIMC_IS_FREQ_MIF, FIMC_IS_FREQ_INT);
+	}
+	mutex_unlock(&isp->busfreq_lock);
+#endif
+
+	dbg("%s\n", __func__);
+	file->private_data = &isp->video[FIMC_IS_VIDEO_NUM_SCALERC];
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf = 0;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_ref_cnt = 0;
+
+	if (!test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state)) {
+		isp->sensor_num = 1;
+		printk(KERN_INFO "++++ IS load fw (Scaler C open)\n");
+		mutex_unlock(&isp->lock);
+		fimc_is_load_fw(isp);
+
+		set_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+		printk(KERN_INFO "---- IS load fw (Scaler C open)\n");
+	} else {
+		mutex_unlock(&isp->lock);
+	}
+
+	clear_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state);
+	return 0;
+
+}
+
+static int fimc_is_scalerc_video_close(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret;
+
+	dbg("%s\n", __func__);
+	vb2_queue_release(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq);
+
+	mutex_lock(&isp->lock);
+	if (!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state)) {
+
+		printk(KERN_INFO "++++ IS local power off (Scaler C close)\n");
+		mutex_unlock(&isp->lock);
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+		fimc_is_hw_subip_poweroff(isp);
+		ret = wait_event_timeout(isp->irq_queue,
+			!test_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout FIMC_IS_PWR_ST_POWER_ON_OFF\n");
+			fimc_is_hw_set_low_poweroff(isp, true);
+			clear_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power);
+			ret = 0;
+		}
+
+		dbg("stop flite & mipi (pos:%d) (port:%d)\n",
+			isp->sensor.id_position,
+			isp->pdata->
+			sensor_info[isp->sensor.id_position]->flite_id);
+		stop_fimc_lite(isp->pdata->
+			sensor_info[isp->sensor.id_position]->flite_id);
+		stop_mipi_csi(isp->pdata->
+			sensor_info[isp->sensor.id_position]->csi_id);
+
+		fimc_is_hw_a5_power(isp, 0);
+		clear_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+		printk(KERN_INFO "---- IS local power off (Scaler C close)\n");
+	} else {
+		mutex_unlock(&isp->lock);
+	}
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	mutex_lock(&isp->busfreq_lock);
+	if (isp->busfreq_num == 1) {
+		dev_unlock(isp->bus_dev, &isp->pdev->dev);
+		printk(KERN_DEBUG "busfreq locked off\n");
+	}
+	isp->busfreq_num--;
+	if (isp->busfreq_num < 0)
+		isp->busfreq_num = 0;
+	mutex_unlock(&isp->busfreq_lock);
+#endif
+
+	return 0;
+}
+
+static unsigned int fimc_is_scalerc_video_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_poll(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq, file, wait);
+
+}
+
+static int fimc_is_scalerc_video_mmap(struct file *file,
+					struct vm_area_struct *vma)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_mmap(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq, vma);
+
+}
+
+/*************************************************************************/
+/* video ioctl operation						*/
+/************************************************************************/
+
+static int fimc_is_scalerc_video_querycap(struct file *file, void *fh,
+						struct v4l2_capability *cap)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	strncpy(cap->driver, isp->pdev->name, sizeof(cap->driver) - 1);
+
+	dbg("(devname : %s)\n", cap->driver);
+	strncpy(cap->card, isp->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING
+				| V4L2_CAP_VIDEO_CAPTURE
+				| V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int fimc_is_scalerc_video_enum_fmt_mplane(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_get_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_set_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pix;
+	struct fimc_is_fmt *frame;
+
+	dbg("%s\n", __func__);
+
+	pix = &format->fmt.pix_mp;
+	frame = find_format(&pix->pixelformat, NULL, 0);
+
+	if (!frame)
+		return -EINVAL;
+
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.format.pixelformat
+							= frame->pixelformat;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.format.mbus_code
+							= frame->mbus_code;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.format.num_planes
+							= frame->num_planes;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.width = pix->width;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.height = pix->height;
+	dbg("num_planes : %d\n", frame->num_planes);
+	dbg("width : %d\n", pix->width);
+	dbg("height : %d\n", pix->height);
+
+	return 0;
+}
+
+static int fimc_is_scalerc_video_try_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_cropcap(struct file *file, void *fh,
+						struct v4l2_cropcap *cropcap)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_get_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_set_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_reqbufs(struct file *file, void *priv,
+					struct v4l2_requestbuffers *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("(buf->count : %d)\n", buf->count);
+
+	ret = vb2_reqbufs(&video->vbq, buf);
+	if (!ret)
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf = buf->count;
+
+	if (buf->count == 0)
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_ref_cnt = 0;
+	dbg("(num_buf : %d)\n",
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf);
+
+	return ret;
+}
+
+static int fimc_is_scalerc_video_querybuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+
+	dbg("%s\n", __func__);
+	ret = vb2_querybuf(&video->vbq, buf);
+
+	return ret;
+}
+
+static int fimc_is_scalerc_video_qbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	if (test_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED, &isp->pipe_state)) {
+		video->buf_mask |= (1<<buf->index);
+		IS_INC_PARAM_NUM(isp);
+
+		dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+	} else
+		dbg("index(%d)\n", buf->index);
+
+	vb_ret = vb2_qbuf(&video->vbq, buf);
+
+	return vb_ret;
+}
+
+static int fimc_is_scalerc_video_dqbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	vb_ret = vb2_dqbuf(&video->vbq, buf, file->f_flags & O_NONBLOCK);
+
+	video->buf_mask &= ~(1<<buf->index);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_mask = video->buf_mask;
+
+	dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+
+	return vb_ret;
+}
+
+static int fimc_is_scalerc_video_streamon(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamon(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq, type);
+}
+
+static int fimc_is_scalerc_video_streamoff(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamoff(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].vbq, type);
+}
+
+static int fimc_is_scalerc_video_enum_input(struct file *file, void *priv,
+						struct v4l2_input *input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+			= isp->pdata->sensor_info[input->index];
+
+	dbg("index(%d) sensor(%s)\n",
+		input->index, sensor_info->sensor_name);
+	dbg("pos(%d) sensor_id(%d)\n",
+		sensor_info->sensor_position, sensor_info->sensor_id);
+	dbg("csi_id(%d) flite_id(%d)\n",
+		sensor_info->csi_id, sensor_info->flite_id);
+	dbg("i2c_ch(%d)\n", sensor_info->i2c_channel);
+
+	if (input->index >= FIMC_IS_MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(input->name, sensor_info->sensor_name,
+					FIMC_IS_MAX_SENSOR_NAME_LEN);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_g_input(struct file *file, void *priv,
+						unsigned int *input)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerc_video_s_input(struct file *file, void *priv,
+						unsigned int input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+			= isp->pdata->sensor_info[input];
+
+	isp->sensor.id_position = input;
+	isp->sensor.sensor_type
+		= fimc_is_hw_get_sensor_type(sensor_info->sensor_id,
+						sensor_info->flite_id);
+
+	fimc_is_hw_set_default_size(isp, sensor_info->sensor_id);
+
+	dbg("sensor info : pos(%d) type(%d)\n", input, isp->sensor.sensor_type);
+
+
+	return 0;
+}
+
+const struct v4l2_file_operations fimc_is_scalerc_video_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_is_scalerc_video_open,
+	.release	= fimc_is_scalerc_video_close,
+	.poll		= fimc_is_scalerc_video_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= fimc_is_scalerc_video_mmap,
+};
+
+const struct v4l2_ioctl_ops fimc_is_scalerc_video_ioctl_ops = {
+	.vidioc_querycap		= fimc_is_scalerc_video_querycap,
+	.vidioc_enum_fmt_vid_cap_mplane
+				= fimc_is_scalerc_video_enum_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane
+				= fimc_is_scalerc_video_get_format_mplane,
+	.vidioc_s_fmt_vid_cap_mplane
+				= fimc_is_scalerc_video_set_format_mplane,
+	.vidioc_try_fmt_vid_cap_mplane
+				= fimc_is_scalerc_video_try_format_mplane,
+	.vidioc_cropcap			= fimc_is_scalerc_video_cropcap,
+	.vidioc_g_crop			= fimc_is_scalerc_video_get_crop,
+	.vidioc_s_crop			= fimc_is_scalerc_video_set_crop,
+	.vidioc_reqbufs			= fimc_is_scalerc_video_reqbufs,
+	.vidioc_querybuf		= fimc_is_scalerc_video_querybuf,
+	.vidioc_qbuf			= fimc_is_scalerc_video_qbuf,
+	.vidioc_dqbuf			= fimc_is_scalerc_video_dqbuf,
+	.vidioc_streamon		= fimc_is_scalerc_video_streamon,
+	.vidioc_streamoff		= fimc_is_scalerc_video_streamoff,
+	.vidioc_enum_input		= fimc_is_scalerc_video_enum_input,
+	.vidioc_g_input			= fimc_is_scalerc_video_g_input,
+	.vidioc_s_input			= fimc_is_scalerc_video_s_input,
+};
+
+static int fimc_is_scalerc_queue_setup(struct vb2_queue *vq,
+			unsigned int *num_buffers,
+			unsigned int *num_planes, unsigned long sizes[],
+			void *allocators[])
+{
+
+	struct fimc_is_video_dev *video = vq->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int i;
+
+
+	*num_planes = isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+					frame.format.num_planes;
+	set_plane_size(&isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame, sizes);
+
+	for (i = 0; i < *num_planes; i++)
+		allocators[i] =  isp->alloc_ctx;
+
+	dbg("(num_planes : %d)(size : %d)\n", (int)*num_planes, (int)sizes[0]);
+	return 0;
+}
+static int fimc_is_scalerc_buffer_prepare(struct vb2_buffer *vb)
+{
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+
+static inline void fimc_is_scalerc_lock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static inline void fimc_is_scalerc_unlock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_scalerc_start_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+	int i, j;
+	int buf_index;
+
+	dbg("(pipe_state : %d)\n", (int)isp->pipe_state);
+
+	if (test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+
+		dbg("IS change mode\n");
+		set_bit(IS_ST_CHANGE_MODE, &isp->state);
+		fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_CHANGE_MODE_DONE,
+			&isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED,
+			&isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		dbg("IS Stream On");
+		fimc_is_hw_set_stream(isp, 1);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_ON, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+		set_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+
+		/* buffer addr setting */
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+							num_buf; i++)
+			for (j = 0; j < isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+						frame.format.num_planes; j++) {
+				buf_index
+				= i * isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+						frame.format.num_planes + j;
+
+				dbg("(%d)set buf(%d:%d) = 0x%08x\n",
+					buf_index, i, j,
+					isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+					buf[i][j]);
+
+				isp->is_p_region->shared[447+buf_index]
+					= isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+								buf[i][j];
+		}
+
+		dbg("buf_num:%d buf_plane:%d shared[447] : 0x%p\n",
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+			frame.format.num_planes,
+			isp->mem.kvaddr_shared + 447 * sizeof(u32));
+
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+							num_buf; i++)
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_mask
+								|= (1 << i);
+
+		dbg("initial buffer mask : 0x%08x\n",
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_mask);
+
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(isp,
+			DMA_OUTPUT_COMMAND_ENABLE);
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_MASK(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_mask);
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf);
+		IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+			(u32)isp->mem.dvaddr_shared + 447*sizeof(u32));
+
+		IS_SET_PARAM_BIT(isp, PARAM_SCALERC_DMA_OUTPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state);
+	}
+	return 0;
+}
+
+static int fimc_is_scalerc_stop_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+
+	clear_bit(IS_ST_STREAM_OFF, &isp->state);
+	fimc_is_hw_set_stream(isp, 0);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_OFF, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+		if (!ret)
+			err("s_power off failed!!\n");
+		return -EBUSY;
+	}
+
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_CMD(isp,
+		DMA_OUTPUT_COMMAND_DISABLE);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+		0);
+	IS_SCALERC_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+		0);
+
+	IS_SET_PARAM_BIT(isp, PARAM_SCALERC_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(isp);
+
+	fimc_is_mem_cache_clean((void *)isp->is_p_region,
+		IS_PARAM_SIZE);
+
+	isp->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+	fimc_is_hw_set_param(isp);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout 2: %s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS change mode\n");
+	clear_bit(IS_ST_RUN, &isp->state);
+	set_bit(IS_ST_CHANGE_MODE, &isp->state);
+	fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_CHANGE_MODE_DONE, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"Mode change timeout:%s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS Stream On");
+	fimc_is_hw_set_stream(isp, 1);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_ON, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+	if (!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &isp->state);
+
+		fimc_is_hw_set_stream(isp, 0);
+		dbg("IS Stream Off");
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout4 : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	clear_bit(IS_ST_RUN, &isp->state);
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+	clear_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED, &isp->pipe_state);
+	clear_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state);
+
+	return 0;
+}
+
+static void fimc_is_scalerc_buffer_queue(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	unsigned int i;
+
+	dbg("%s\n", __func__);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERC].frame.format.num_planes
+							= vb->num_planes;
+
+	if (!test_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED,
+					&isp->pipe_state)) {
+		for (i = 0; i < vb->num_planes; i++) {
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+				buf[vb->v4l2_buf.index][i]
+				= isp->vb2->plane_addr(vb, i);
+
+			dbg("index(%d)(%d) deviceVaddr(0x%08x)\n",
+				vb->v4l2_buf.index, i,
+				isp->video[FIMC_IS_VIDEO_NUM_SCALERC].
+				buf[vb->v4l2_buf.index][i]);
+		}
+
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_ref_cnt++;
+
+		if (isp->video[FIMC_IS_VIDEO_NUM_SCALERC].num_buf
+			== isp->video[FIMC_IS_VIDEO_NUM_SCALERC].buf_ref_cnt)
+			set_bit(FIMC_IS_STATE_SCALERC_BUFFER_PREPARED,
+				&isp->pipe_state);
+	}
+
+	if (!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state))
+		fimc_is_scalerc_start_streaming(vb->vb2_queue);
+
+	return;
+}
+
+const struct vb2_ops fimc_is_scalerc_qops = {
+	.queue_setup		= fimc_is_scalerc_queue_setup,
+	.buf_prepare		= fimc_is_scalerc_buffer_prepare,
+	.buf_queue		= fimc_is_scalerc_buffer_queue,
+	.wait_prepare		= fimc_is_scalerc_unlock,
+	.wait_finish		= fimc_is_scalerc_lock,
+	.start_streaming	= fimc_is_scalerc_start_streaming,
+	.stop_streaming	= fimc_is_scalerc_stop_streaming,
+};
+
+/*************************************************************************/
+/* video file opertation						 */
+/************************************************************************/
+
+static int fimc_is_scalerp_video_open(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	mutex_lock(&isp->busfreq_lock);
+	isp->busfreq_num++;
+	if (isp->busfreq_num == 1) {
+		dev_lock(isp->bus_dev, &isp->pdev->dev,
+			(FIMC_IS_FREQ_MIF * 1000) + FIMC_IS_FREQ_INT);
+		dbg("busfreq locked on <%d/%d>MHz\n",
+			FIMC_IS_FREQ_MIF, FIMC_IS_FREQ_INT);
+	}
+	mutex_unlock(&isp->busfreq_lock);
+#endif
+
+	dbg("%s\n", __func__);
+	file->private_data = &isp->video[FIMC_IS_VIDEO_NUM_SCALERP];
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf = 0;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_ref_cnt = 0;
+
+	mutex_lock(&isp->lock);
+	if (!test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state)) {
+		isp->sensor_num = 1;
+		printk(KERN_INFO "++++ IS load fw (Scaler P open)\n");
+		mutex_unlock(&isp->lock);
+		fimc_is_load_fw(isp);
+
+		set_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+		printk(KERN_INFO "---- IS load fw (Scaler P open)\n");
+	} else {
+		mutex_unlock(&isp->lock);
+	}
+
+	clear_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state);
+	return 0;
+
+}
+
+static int fimc_is_scalerp_video_close(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret;
+
+	dbg("%s\n", __func__);
+	vb2_queue_release(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq);
+
+	mutex_lock(&isp->lock);
+	if (!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state)) {
+
+		printk(KERN_INFO "++++ IS local power off (Scaler P close)\n");
+		mutex_unlock(&isp->lock);
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+		fimc_is_hw_subip_poweroff(isp);
+		ret = wait_event_timeout(isp->irq_queue,
+			!test_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout FIMC_IS_PWR_ST_POWER_ON_OFF\n");
+			fimc_is_hw_set_low_poweroff(isp, true);
+			clear_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power);
+			ret = 0;
+		}
+
+		dbg("staop flite & mipi (pos:%d) (port:%d)\n",
+			isp->sensor.id_position,
+			isp->pdata->
+			sensor_info[isp->sensor.id_position]->flite_id);
+		stop_fimc_lite(isp->pdata->
+			sensor_info[isp->sensor.id_position]->flite_id);
+		stop_mipi_csi(isp->pdata->
+			sensor_info[isp->sensor.id_position]->csi_id);
+
+		fimc_is_hw_a5_power(isp, 0);
+		clear_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+		printk(KERN_INFO "---- IS local power off (Scaler P close)\n");
+	} else {
+		mutex_unlock(&isp->lock);
+	}
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	mutex_lock(&isp->busfreq_lock);
+	if (isp->busfreq_num == 1) {
+		dev_unlock(isp->bus_dev, &isp->pdev->dev);
+		printk(KERN_DEBUG "busfreq locked off\n");
+	}
+	isp->busfreq_num--;
+	if (isp->busfreq_num < 0)
+		isp->busfreq_num = 0;
+	mutex_unlock(&isp->busfreq_lock);
+#endif
+
+	return 0;
+
+}
+
+static unsigned int fimc_is_scalerp_video_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_poll(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq, file, wait);
+
+}
+
+static int fimc_is_scalerp_video_mmap(struct file *file,
+					struct vm_area_struct *vma)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_mmap(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq, vma);
+
+}
+
+/*************************************************************************/
+/* video ioctl operation						*/
+/************************************************************************/
+
+static int fimc_is_scalerp_video_querycap(struct file *file, void *fh,
+						struct v4l2_capability *cap)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	strncpy(cap->driver, isp->pdev->name, sizeof(cap->driver) - 1);
+
+	dbg("%s(devname : %s)\n", __func__, cap->driver);
+	strncpy(cap->card, isp->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING
+					| V4L2_CAP_VIDEO_CAPTURE
+					| V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int fimc_is_scalerp_video_enum_fmt_mplane(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_get_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_set_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pix;
+	struct fimc_is_fmt *frame;
+
+	dbg("%s\n", __func__);
+
+	pix = &format->fmt.pix_mp;
+	frame = find_format(&pix->pixelformat, NULL, 0);
+
+	if (!frame)
+		return -EINVAL;
+
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.format.pixelformat
+							= frame->pixelformat;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.format.mbus_code
+							= frame->mbus_code;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.format.num_planes
+							= frame->num_planes;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.width = pix->width;
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.height = pix->height;
+	dbg("num_planes : %d\n", frame->num_planes);
+	dbg("width : %d\n", pix->width);
+	dbg("height : %d\n", pix->height);
+
+	return 0;
+}
+
+static int fimc_is_scalerp_video_try_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_cropcap(struct file *file, void *fh,
+						struct v4l2_cropcap *cropcap)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_get_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_set_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_reqbufs(struct file *file, void *priv,
+					struct v4l2_requestbuffers *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("(buf->count : %d)\n", buf->count);
+	ret = vb2_reqbufs(&video->vbq, buf);
+	if (!ret)
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf = buf->count;
+
+	if (buf->count == 0)
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_ref_cnt = 0;
+
+	dbg("(num_buf | %d)\n",
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf);
+
+	return ret;
+}
+
+static int fimc_is_scalerp_video_querybuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+
+	dbg("%s\n", __func__);
+	ret = vb2_querybuf(&video->vbq, buf);
+
+	return ret;
+}
+
+static int fimc_is_scalerp_video_qbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	if (test_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED, &isp->pipe_state)) {
+		video->buf_mask |= (1<<buf->index);
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask
+						= video->buf_mask;
+
+		dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+	} else
+		dbg("index(%d)\n", buf->index);
+
+	vb_ret = vb2_qbuf(&video->vbq, buf);
+
+	return vb_ret;
+}
+
+static int fimc_is_scalerp_video_dqbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	vb_ret = vb2_dqbuf(&video->vbq, buf, file->f_flags & O_NONBLOCK);
+
+	video->buf_mask &= ~(1<<buf->index);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask = video->buf_mask;
+
+	dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+
+	return vb_ret;
+}
+
+static int fimc_is_scalerp_video_streamon(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamon(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq, type);
+}
+
+static int fimc_is_scalerp_video_streamoff(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamoff(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].vbq, type);
+}
+
+static int fimc_is_scalerp_video_enum_input(struct file *file, void *priv,
+						struct v4l2_input *input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+			= isp->pdata->sensor_info[input->index];
+
+	dbg("index(%d) sensor(%s)\n",
+		input->index, sensor_info->sensor_name);
+	dbg("pos(%d) sensor_id(%d)\n",
+		sensor_info->sensor_position, sensor_info->sensor_id);
+	dbg("csi_id(%d) flite_id(%d)\n",
+		sensor_info->csi_id, sensor_info->flite_id);
+	dbg("i2c_ch(%d)\n", sensor_info->i2c_channel);
+
+	if (input->index >= FIMC_IS_MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(input->name, sensor_info->sensor_name,
+					FIMC_IS_MAX_SENSOR_NAME_LEN);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_g_input(struct file *file, void *priv,
+						unsigned int *input)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_scalerp_video_s_input(struct file *file, void *priv,
+					unsigned int input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+			= isp->pdata->sensor_info[input];
+
+	isp->sensor.id_position = input;
+	isp->sensor.sensor_type
+		= fimc_is_hw_get_sensor_type(sensor_info->sensor_id,
+					sensor_info->flite_id);
+
+	fimc_is_hw_set_default_size(isp, sensor_info->sensor_id);
+	printk(KERN_INFO "fimc_is_init_set - %d\n", isp->sensor.sensor_type);
+	fimc_is_init_set(isp, isp->sensor.sensor_type);
+
+	dbg("sensor info : pos(%d) type(%d)\n", input, isp->sensor.sensor_type);
+
+
+	return 0;
+}
+static int fimc_is_scalerp_video_g_ctrl(struct file *file, void *priv,
+					struct v4l2_control *ctrl)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret = 0;
+
+	switch (ctrl->id) {
+	/* EXIF information */
+	case V4L2_CID_IS_CAMERA_EXIF_EXPTIME:
+	case V4L2_CID_CAMERA_EXIF_EXPTIME: /* Exposure Time */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = isp->is_p_region->header[0].
+			exif.exposure_time.den;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_FLASH:
+	case V4L2_CID_CAMERA_EXIF_FLASH: /* Flash */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = isp->is_p_region->header[0].exif.flash;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_ISO:
+	case V4L2_CID_CAMERA_EXIF_ISO: /* ISO Speed Rating */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = isp->is_p_region->header[0].
+			exif.iso_speed_rating;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_SHUTTERSPEED:
+	case V4L2_CID_CAMERA_EXIF_TV: /* Shutter Speed */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		/* Exposure time = shutter speed by FW */
+		ctrl->value = isp->is_p_region->header[0].
+			exif.exposure_time.den;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_BRIGHTNESS:
+	case V4L2_CID_CAMERA_EXIF_BV: /* Brightness */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = isp->is_p_region->header[0].exif.brightness.num;
+		break;
+	case V4L2_CID_CAMERA_EXIF_EBV: /* exposure bias */
+		fimc_is_mem_cache_inv((void *)IS_HEADER(isp),
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = isp->is_p_region->header[0].exif.brightness.den;
+		break;
+	/* Get x and y offset of sensor  */
+	case V4L2_CID_IS_GET_SENSOR_OFFSET_X:
+		ctrl->value = isp->sensor.offset_x;
+		break;
+	case V4L2_CID_IS_GET_SENSOR_OFFSET_Y:
+		ctrl->value = isp->sensor.offset_y;
+		break;
+	case V4L2_CID_IS_FD_GET_DATA:
+		ctrl->value = isp->fd_header.count;
+		fimc_is_mem_cache_inv((void *)IS_FACE(isp),
+		(unsigned long)(sizeof(struct is_face_marker)*MAX_FACE_COUNT));
+		memcpy((void *)isp->fd_header.target_addr,
+			&isp->is_p_region->face[isp->fd_header.index],
+			(sizeof(struct is_face_marker)*isp->fd_header.count));
+		break;
+	/* AF result */
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		if (!is_af_use(isp))
+			ctrl->value = 0x02;
+		else
+			ctrl->value = isp->af.af_lock_state;
+		break;
+	/* F/W debug region address */
+	case V4L2_CID_IS_FW_DEBUG_REGION_ADDR:
+		ctrl->value = isp->mem.base + FIMC_IS_DEBUG_REGION_ADDR;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return ret;
+}
+
+static int fimc_is_g_ext_ctrls_handler(struct fimc_is_dev *dev,
+	struct v4l2_ext_control *ctrl, int index)
+{
+	int ret = 0;
+	switch (ctrl->id) {
+	/* Face Detection CID handler */
+	/* 1. Overall information */
+	case V4L2_CID_IS_FD_GET_FACE_COUNT:
+		ctrl->value = dev->fd_header.count;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_FRAME_NUMBER:
+		if (dev->fd_header.offset < dev->fd_header.count) {
+			ctrl->value =
+				dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].frame_number;
+		} else {
+			ctrl->value = 0;
+			return -255;
+		}
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_CONFIDENCE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].confidence;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_SMILE_LEVEL:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].smile_level;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BLINK_LEVEL:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].blink_level;
+		break;
+	/* 2. Face information */
+	case V4L2_CID_IS_FD_GET_FACE_TOPLEFT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.offset_x;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_TOPLEFT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.offset_y;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BOTTOMRIGHT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.width;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BOTTOMRIGHT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].face.height;
+		break;
+	/* 3. Left eye information */
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_TOPLEFT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.offset_x;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_TOPLEFT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.offset_y;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_BOTTOMRIGHT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.width;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_BOTTOMRIGHT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].left_eye.height;
+		break;
+	/* 4. Right eye information */
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_TOPLEFT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.offset_x;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_TOPLEFT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.offset_y;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_BOTTOMRIGHT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.width;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_BOTTOMRIGHT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].right_eye.height;
+		break;
+	/* 5. Mouth eye information */
+	case V4L2_CID_IS_FD_GET_MOUTH_TOPLEFT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].mouth.offset_x;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_TOPLEFT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.offset_y;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_BOTTOMRIGHT_X:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].mouth.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].mouth.width;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_BOTTOMRIGHT_Y:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].mouth.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+			+ dev->fd_header.offset].mouth.height;
+		break;
+	/* 6. Angle information */
+	case V4L2_CID_IS_FD_GET_ANGLE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].roll_angle;
+		break;
+	case V4L2_CID_IS_FD_GET_YAW_ANGLE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].yaw_angle;
+		break;
+	/* 7. Update next face information */
+	case V4L2_CID_IS_FD_GET_NEXT:
+		dev->fd_header.offset++;
+		break;
+	default:
+		return 255;
+		break;
+	}
+	return ret;
+}
+
+static int fimc_is_scalerp_video_g_ext_ctrl(struct file *file, void *priv,
+					struct v4l2_ext_controls *ctrls)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct v4l2_ext_control *ctrl;
+	int i, ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&isp->slock, flags);
+	ctrl = ctrls->controls;
+	if (!ctrls->ctrl_class == V4L2_CTRL_CLASS_CAMERA)
+		return -EINVAL;
+
+	fimc_is_mem_cache_inv((void *)IS_FACE(isp),
+		(unsigned long)(sizeof(struct is_face_marker)*MAX_FACE_COUNT));
+
+	isp->fd_header.offset = 0;
+
+	isp->fd_header.width = (s32)isp->sensor.width ;
+	isp->fd_header.height = (s32)isp->sensor.height ;
+
+	for (i = 0; i < ctrls->count; i++) {
+		ctrl = ctrls->controls + i;
+		ret = fimc_is_g_ext_ctrls_handler(isp, ctrl, i);
+		if (ret > 0) {
+			ctrls->error_idx = i;
+			break;
+		} else if (ret < 0) {
+			ret = 0;
+			break;
+		}
+	}
+
+	isp->fd_header.index = 0;
+	isp->fd_header.count = 0;
+	spin_unlock_irqrestore(&isp->slock, flags);
+	return ret;
+}
+
+static int fimc_is_scalerp_video_s_ctrl(struct file *file, void *priv,
+					struct v4l2_control *ctrl)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret = 0;
+
+	dbg("fimc_is_scalerp_video_s_ctrl(%d)(%d)\n", ctrl->id, ctrl->value);
+	switch (ctrl->id) {
+	case V4L2_CID_IS_CAMERA_SHOT_MODE_NORMAL:
+		ret = fimc_is_v4l2_shot_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_FRAME_RATE:
+#ifdef FRAME_RATE_ENABLE
+		/* FW partially supported it */
+		ret = fimc_is_v4l2_frame_rate(isp, ctrl->value);
+#else
+		err("ERR(%s) disabled FRAME_RATE\n", __func__);
+#endif
+		break;
+	/* Focus */
+	case V4L2_CID_IS_CAMERA_OBJECT_POSITION_X:
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		isp->af.pos_x = ctrl->value;
+		break;
+	case V4L2_CID_IS_CAMERA_OBJECT_POSITION_Y:
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		isp->af.pos_y = ctrl->value;
+		break;
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		ret = fimc_is_v4l2_af_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		ret = fimc_is_v4l2_af_start_stop(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		ret = fimc_is_v4l2_touch_af_start_stop(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_CAF_START_STOP:
+		ret = fimc_is_v4l2_caf_start_stop(isp, ctrl->value);
+		break;
+	/* AWB, AE Lock/Unlock */
+	case V4L2_CID_CAMERA_AEAWB_LOCK_UNLOCK:
+		ret = fimc_is_v4l2_ae_awb_lockunlock(isp, ctrl->value);
+		break;
+	/* FLASH */
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		ret = fimc_is_v4l2_isp_flash_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_AWB_MODE:
+		ret = fimc_is_v4l2_awb_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		ret = fimc_is_v4l2_awb_mode_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_EFFECT:
+		ret = fimc_is_v4l2_isp_effect_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_IMAGE_EFFECT:
+		ret = fimc_is_v4l2_isp_effect(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_ISO:
+	case V4L2_CID_CAMERA_ISO:
+		ret = fimc_is_v4l2_isp_iso(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_CONTRAST:
+		ret = fimc_is_v4l2_isp_contrast_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_CONTRAST:
+		ret = fimc_is_v4l2_isp_contrast(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_SATURATION:
+	case V4L2_CID_CAMERA_SATURATION:
+		ret = fimc_is_v4l2_isp_saturation(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_SHARPNESS:
+	case V4L2_CID_CAMERA_SHARPNESS:
+		ret = fimc_is_v4l2_isp_sharpness(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_EXPOSURE:
+		ret = fimc_is_v4l2_isp_exposure(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		ret = fimc_is_v4l2_isp_exposure_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_BRIGHTNESS:
+		ret = fimc_is_v4l2_isp_brightness(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_HUE:
+		ret = fimc_is_v4l2_isp_hue(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_METERING:
+		ret = fimc_is_v4l2_isp_metering_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING:
+		ret = fimc_is_v4l2_isp_metering(isp, ctrl->value);
+		break;
+	/* Ony valid at SPOT Mode */
+	case V4L2_CID_IS_CAMERA_METERING_POSITION_X:
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_POSITION_Y:
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_WINDOW_X:
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_WINDOW_Y:
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		ret = fimc_is_v4l2_isp_afc_legacy(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_AFC_MODE:
+		ret = fimc_is_v4l2_isp_afc(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_FD_SET_MAX_FACE_NUMBER:
+		/* TODO */
+		/*
+		if (ctrl->value >= 0) {
+			IS_FD_SET_PARAM_FD_CONFIG_CMD(isp,
+				FD_CONFIG_COMMAND_MAXIMUM_NUMBER);
+			IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(isp, ctrl->value);
+			IS_SET_PARAM_BIT(isp, PARAM_FD_CONFIG);
+			IS_INC_PARAM_NUM(isp);
+			fimc_is_mem_cache_clean((void *)isp->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(isp);
+		}
+		*/
+		break;
+	case V4L2_CID_IS_FD_SET_ROLL_ANGLE:
+		ret = fimc_is_v4l2_fd_angle_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_FD_SET_DATA_ADDRESS:
+		isp->fd_header.target_addr = ctrl->value;
+		break;
+	case V4L2_CID_IS_SET_ISP:
+		ret = fimc_is_v4l2_set_isp(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_SET_DRC:
+		ret = fimc_is_v4l2_set_drc(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_ISP:
+		ret = fimc_is_v4l2_cmd_isp(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_DRC:
+		ret = fimc_is_v4l2_cmd_drc(isp, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_FD:
+		ret = fimc_is_v4l2_cmd_fd(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		ret = fimc_is_v4l2_isp_scene_mode(isp, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_VT_MODE:
+		isp->setfile.sub_index = ctrl->value;
+		if (ctrl->value == 1)
+			printk(KERN_INFO "VT mode is selected\n");
+		break;
+	case V4L2_CID_CAMERA_SET_ODC:
+#ifdef ODC_ENABLE
+		ret = fimc_is_ctrl_odc(isp, ctrl->value);
+#else
+		err("ERR(%s) disabled ODC\n", __func__);
+#endif
+		break;
+	case V4L2_CID_CAMERA_SET_3DNR:
+#ifdef TDNR_ENABLE
+		ret = fimc_is_ctrl_3dnr(isp, ctrl->value);
+#else
+		err("ERR(%s) disabled 3DNR\n", __func__);
+#endif
+		break;
+	case V4L2_CID_CAMERA_ZOOM:
+#ifdef DZOOM_ENABLE
+		/* FW partially supported it */
+		ret = fimc_is_digital_zoom(isp, ctrl->value);
+#else
+		err("ERR(%s) disabled DZOOM\n", __func__);
+#endif
+		break;
+	case V4L2_CID_CAMERA_SET_DIS:
+#ifdef DIS_ENABLE
+		/* FW partially supported it */
+		ret = fimc_is_ctrl_dis(isp, ctrl->value);
+#else
+		err("ERR(%s) disabled DIS\n", __func__);
+#endif
+		break;
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		break;
+	default:
+		err("Invalid control\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+const struct v4l2_file_operations fimc_is_scalerp_video_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_is_scalerp_video_open,
+	.release	= fimc_is_scalerp_video_close,
+	.poll		= fimc_is_scalerp_video_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= fimc_is_scalerp_video_mmap,
+};
+
+const struct v4l2_ioctl_ops fimc_is_scalerp_video_ioctl_ops = {
+	.vidioc_querycap		= fimc_is_scalerp_video_querycap,
+	.vidioc_enum_fmt_vid_cap_mplane
+			= fimc_is_scalerp_video_enum_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane
+			= fimc_is_scalerp_video_get_format_mplane,
+	.vidioc_s_fmt_vid_cap_mplane
+			= fimc_is_scalerp_video_set_format_mplane,
+	.vidioc_try_fmt_vid_cap_mplane
+			= fimc_is_scalerp_video_try_format_mplane,
+	.vidioc_cropcap			= fimc_is_scalerp_video_cropcap,
+	.vidioc_g_crop			= fimc_is_scalerp_video_get_crop,
+	.vidioc_s_crop			= fimc_is_scalerp_video_set_crop,
+	.vidioc_reqbufs			= fimc_is_scalerp_video_reqbufs,
+	.vidioc_querybuf		= fimc_is_scalerp_video_querybuf,
+	.vidioc_qbuf			= fimc_is_scalerp_video_qbuf,
+	.vidioc_dqbuf			= fimc_is_scalerp_video_dqbuf,
+	.vidioc_streamon		= fimc_is_scalerp_video_streamon,
+	.vidioc_streamoff		= fimc_is_scalerp_video_streamoff,
+	.vidioc_enum_input		= fimc_is_scalerp_video_enum_input,
+	.vidioc_g_input			= fimc_is_scalerp_video_g_input,
+	.vidioc_s_input			= fimc_is_scalerp_video_s_input,
+	.vidioc_g_ctrl			= fimc_is_scalerp_video_g_ctrl,
+	.vidioc_s_ctrl			= fimc_is_scalerp_video_s_ctrl,
+	.vidioc_g_ext_ctrls		= fimc_is_scalerp_video_g_ext_ctrl,
+};
+
+static int fimc_is_scalerp_queue_setup(struct vb2_queue *vq,
+			unsigned int *num_buffers,
+			unsigned int *num_planes,
+			unsigned long sizes[],
+			void *allocators[])
+{
+
+	struct fimc_is_video_dev *video = vq->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int i;
+
+
+	*num_planes = isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+					frame.format.num_planes;
+	set_plane_size(&isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame, sizes);
+
+	for (i = 0; i < *num_planes; i++)
+		allocators[i] =  isp->alloc_ctx;
+
+	dbg("(num_planes : %d)(size : %d)\n", (int)*num_planes, (int)sizes[0]);
+
+	return 0;
+}
+static int fimc_is_scalerp_buffer_prepare(struct vb2_buffer *vb)
+{
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+
+static inline void fimc_is_scalerp_lock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static inline void fimc_is_scalerp_unlock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_scalerp_start_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+	int i, j;
+	int buf_index;
+
+	dbg("%s(pipe_state : %d)\n", __func__, (int)isp->pipe_state);
+
+	if (test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+
+		dbg("IS change mode\n");
+		clear_bit(IS_ST_RUN, &isp->state);
+		set_bit(IS_ST_CHANGE_MODE, &isp->state);
+		fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_CHANGE_MODE_DONE,
+			&isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED,
+			&isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		dbg("IS Stream On");
+		fimc_is_hw_set_stream(isp, 1);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_ON, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+		set_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+
+		/* buffer addr setting */
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				num_buf; i++)
+			for (j = 0; j < isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+					frame.format.num_planes; j++) {
+				buf_index = i*isp->
+					video[FIMC_IS_VIDEO_NUM_SCALERP].
+					frame.format.num_planes + j;
+
+				dbg("(%d)set buf(%d:%d) = 0x%08x\n",
+					buf_index, i, j,
+					isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+					buf[i][j]);
+
+				isp->is_p_region->shared[400+buf_index]
+					= isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+					buf[i][j];
+		}
+
+		dbg("buf_num:%d buf_plane:%d shared[400] : 0x%p\n",
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+			frame.format.num_planes,
+			isp->mem.kvaddr_shared + 400 * sizeof(u32));
+
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask = 0;
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				num_buf; i++)
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask
+								|= (1 << i);
+		dbg("initial buffer mask : 0x%08x\n",
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask);
+
+		IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(isp,
+			DMA_OUTPUT_COMMAND_ENABLE);
+		IS_SCALERP_SET_PARAM_DMA_OUTPUT_MASK(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_mask);
+		IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf);
+		IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+			(u32)isp->mem.dvaddr_shared + 400*sizeof(u32));
+		IS_SET_PARAM_BIT(isp, PARAM_SCALERP_DMA_OUTPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state);
+
+#ifdef DZOOM_EVT0
+		printk(KERN_INFO "DZOOM_EVT0 is enabled\n");
+		clear_bit(IS_ST_SCALERP_FRAME_DONE, &isp->state);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_SCALERP_FRAME_DONE, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		dbg("DRC stop\n");
+		IS_DRC_SET_PARAM_CONTROL_CMD(isp,
+			CONTROL_COMMAND_STOP);
+		IS_SET_PARAM_BIT(isp, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(isp);
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		dbg("DRC change path\n");
+		IS_DRC_SET_PARAM_OTF_INPUT_CMD(isp,
+			OTF_INPUT_COMMAND_DISABLE);
+		IS_SET_PARAM_BIT(isp, PARAM_DRC_OTF_INPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		IS_DRC_SET_PARAM_DMA_INPUT_CMD(isp,
+			DMA_INPUT_COMMAND_ENABLE);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(isp,
+			1);
+		isp->is_p_region->shared[100] = (u32)isp->mem.dvaddr_isp;
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(isp,
+			(u32)isp->mem.dvaddr_shared + 100*sizeof(u32));
+		dbg("isp phy addr : 0x%08x\n",
+			(long unsigned int)virt_to_phys(isp->mem.kvaddr_isp));
+		dbg("isp dvaddr : 0x%08x\n",
+			(long unsigned int)isp->mem.dvaddr_isp);
+		IS_SET_PARAM_BIT(isp, PARAM_DRC_DMA_INPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		dbg("DRC start\n");
+		IS_DRC_SET_PARAM_CONTROL_CMD(isp,
+			CONTROL_COMMAND_START);
+		IS_SET_PARAM_BIT(isp, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(isp);
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+#endif
+	}
+
+	return 0;
+}
+
+static int fimc_is_scalerp_stop_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+
+
+	clear_bit(IS_ST_STREAM_OFF, &isp->state);
+	fimc_is_hw_set_stream(isp, 0);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_OFF, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		if (!ret)
+			err("s_power off failed!!\n");
+		return -EBUSY;
+	}
+
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_CMD(isp,
+		DMA_OUTPUT_COMMAND_DISABLE);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+		0);
+	IS_SCALERP_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+		0);
+
+	IS_SET_PARAM_BIT(isp, PARAM_SCALERP_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(isp);
+
+	fimc_is_mem_cache_clean((void *)isp->is_p_region,
+		IS_PARAM_SIZE);
+
+	isp->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+	fimc_is_hw_set_param(isp);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout 2: %s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS change mode\n");
+	clear_bit(IS_ST_RUN, &isp->state);
+	set_bit(IS_ST_CHANGE_MODE, &isp->state);
+	fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_CHANGE_MODE_DONE, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"Mode change timeout:%s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS Stream On\n");
+	fimc_is_hw_set_stream(isp, 1);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_ON, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+	if (!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &isp->state);
+		dbg("IS Stream Off");
+		fimc_is_hw_set_stream(isp, 0);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout 4: %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+	clear_bit(IS_ST_RUN, &isp->state);
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+	clear_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED, &isp->pipe_state);
+	clear_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state);
+
+	isp->setfile.sub_index = 0;
+
+	return 0;
+}
+
+static void fimc_is_scalerp_buffer_queue(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	unsigned int i;
+
+	dbg("%s\n", __func__);
+	isp->video[FIMC_IS_VIDEO_NUM_SCALERP].frame.format.num_planes
+							= vb->num_planes;
+
+	if (!test_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED,
+							&isp->pipe_state)) {
+		for (i = 0; i < vb->num_planes; i++) {
+			isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				buf[vb->v4l2_buf.index][i]
+				= isp->vb2->plane_addr(vb, i);
+			dbg("index(%d)(%d) deviceVaddr(0x%08x)\n",
+				vb->v4l2_buf.index, i,
+				isp->video[FIMC_IS_VIDEO_NUM_SCALERP].
+				buf[vb->v4l2_buf.index][i]);
+		}
+
+		isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_ref_cnt++;
+
+		if (isp->video[FIMC_IS_VIDEO_NUM_SCALERP].num_buf
+			== isp->video[FIMC_IS_VIDEO_NUM_SCALERP].buf_ref_cnt) {
+			set_bit(FIMC_IS_STATE_SCALERP_BUFFER_PREPARED,
+				&isp->pipe_state);
+			dbg("FIMC_IS_STATE_SCALERP_BUFFER_PREPARED\n");
+		}
+	}
+
+	if (!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state))
+		fimc_is_scalerp_start_streaming(vb->vb2_queue);
+
+	return;
+}
+
+const struct vb2_ops fimc_is_scalerp_qops = {
+	.queue_setup		= fimc_is_scalerp_queue_setup,
+	.buf_prepare		= fimc_is_scalerp_buffer_prepare,
+	.buf_queue		= fimc_is_scalerp_buffer_queue,
+	.wait_prepare		= fimc_is_scalerp_unlock,
+	.wait_finish		= fimc_is_scalerp_lock,
+	.start_streaming	= fimc_is_scalerp_start_streaming,
+	.stop_streaming	= fimc_is_scalerp_stop_streaming,
+};
+
+
+/*************************************************************************/
+/* video file opertation						 */
+/************************************************************************/
+
+static int fimc_is_3dnr_video_open(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+#if defined(CONFIG_BUSFREQ_OPP) && defined(CONFIG_CPU_EXYNOS5250)
+	mutex_lock(&isp->busfreq_lock);
+	isp->busfreq_num++;
+	if (isp->busfreq_num == 1) {
+		dev_lock(isp->bus_dev, &isp->pdev->dev,
+			(FIMC_IS_FREQ_MIF * 1000) + FIMC_IS_FREQ_INT);
+		dbg("busfreq locked on <%d/%d>MHz\n",
+			FIMC_IS_FREQ_MIF, FIMC_IS_FREQ_INT);
+	}
+	mutex_unlock(&isp->busfreq_lock);
+#endif
+
+	dbg("%s\n", __func__);
+	file->private_data = &isp->video[FIMC_IS_VIDEO_NUM_3DNR];
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf = 0;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_ref_cnt = 0;
+
+	clear_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state);
+	return 0;
+
+}
+
+static int fimc_is_3dnr_video_close(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret = 0;
+
+	dbg("%s\n", __func__);
+	vb2_queue_release(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq);
+
+	return ret;
+}
+
+static unsigned int fimc_is_3dnr_video_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_poll(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq, file, wait);
+
+}
+
+static int fimc_is_3dnr_video_mmap(struct file *file,
+					struct vm_area_struct *vma)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_mmap(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq, vma);
+
+}
+
+/*************************************************************************/
+/* video ioctl operation						*/
+/************************************************************************/
+
+static int fimc_is_3dnr_video_querycap(struct file *file, void *fh,
+					struct v4l2_capability *cap)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	strncpy(cap->driver, isp->pdev->name, sizeof(cap->driver) - 1);
+
+	dbg("%s(devname : %s)\n", __func__, cap->driver);
+	strncpy(cap->card, isp->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING
+				| V4L2_CAP_VIDEO_CAPTURE
+				| V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int fimc_is_3dnr_video_enum_fmt_mplane(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_get_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_set_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pix;
+	struct fimc_is_fmt *frame;
+
+	dbg("%s\n", __func__);
+
+	pix = &format->fmt.pix_mp;
+	frame = find_format(&pix->pixelformat, NULL, 0);
+
+	if (!frame)
+		return -EINVAL;
+
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.format.pixelformat
+						= frame->pixelformat;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.format.mbus_code
+						= frame->mbus_code;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.format.num_planes
+						= frame->num_planes;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.width = pix->width;
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.height = pix->height;
+	dbg("num_planes : %d\n", frame->num_planes);
+	dbg("width : %d\n", pix->width);
+	dbg("height : %d\n", pix->height);
+
+	return 0;
+}
+
+static int fimc_is_3dnr_video_try_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_cropcap(struct file *file, void *fh,
+						struct v4l2_cropcap *cropcap)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_get_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_set_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_reqbufs(struct file *file, void *priv,
+					struct v4l2_requestbuffers *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	ret = vb2_reqbufs(&video->vbq, buf);
+	if (!ret)
+		isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf = buf->count;
+
+	if (buf->count == 0)
+		isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_ref_cnt = 0;
+
+	dbg("%s(num_buf | %d)\n", __func__,
+		isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf);
+
+	return ret;
+}
+
+static int fimc_is_3dnr_video_querybuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+
+	dbg("%s\n", __func__);
+	ret = vb2_querybuf(&video->vbq, buf);
+
+	return ret;
+}
+
+static int fimc_is_3dnr_video_qbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	if (test_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED, &isp->pipe_state)) {
+		video->buf_mask |= (1<<buf->index);
+		isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_mask = video->buf_mask;
+
+		dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+	} else {
+		dbg("%s :: index(%d)\n", __func__, buf->index);
+	}
+	vb_ret = vb2_qbuf(&video->vbq, buf);
+
+	return vb_ret;
+}
+
+static int fimc_is_3dnr_video_dqbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	vb_ret = vb2_dqbuf(&video->vbq, buf, file->f_flags & O_NONBLOCK);
+
+	video->buf_mask &= ~(1<<buf->index);
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_mask = video->buf_mask;
+
+	dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+
+	return vb_ret;
+}
+
+static int fimc_is_3dnr_video_streamon(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamon(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq, type);
+}
+
+static int fimc_is_3dnr_video_streamoff(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamoff(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].vbq, type);
+}
+
+static int fimc_is_3dnr_video_enum_input(struct file *file, void *priv,
+						struct v4l2_input *input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+				= isp->pdata->sensor_info[input->index];
+
+	dbg("index(%d) sensor(%s)\n",
+		input->index, sensor_info->sensor_name);
+	dbg("pos(%d) sensor_id(%d)\n",
+		sensor_info->sensor_position, sensor_info->sensor_id);
+	dbg("csi_id(%d) flite_id(%d)\n",
+		sensor_info->csi_id, sensor_info->flite_id);
+	dbg("i2c_ch(%d)\n", sensor_info->i2c_channel);
+
+	if (input->index >= FIMC_IS_MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(input->name, sensor_info->sensor_name,
+					FIMC_IS_MAX_SENSOR_NAME_LEN);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_g_input(struct file *file, void *priv,
+						unsigned int *input)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_3dnr_video_s_input(struct file *file, void *priv,
+						unsigned int input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+			= isp->pdata->sensor_info[input];
+
+	isp->sensor.id_position = input;
+	isp->sensor.sensor_type
+		= fimc_is_hw_get_sensor_type(sensor_info->sensor_id,
+						sensor_info->flite_id);
+
+	fimc_is_hw_set_default_size(isp, sensor_info->sensor_id);
+
+	dbg("sensor info : pos(%d) type(%d)\n", input, isp->sensor.sensor_type);
+
+
+	return 0;
+}
+
+const struct v4l2_file_operations fimc_is_3dnr_video_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_is_3dnr_video_open,
+	.release	= fimc_is_3dnr_video_close,
+	.poll		= fimc_is_3dnr_video_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= fimc_is_3dnr_video_mmap,
+};
+
+const struct v4l2_ioctl_ops fimc_is_3dnr_video_ioctl_ops = {
+	.vidioc_querycap		= fimc_is_3dnr_video_querycap,
+	.vidioc_enum_fmt_vid_cap_mplane	= fimc_is_3dnr_video_enum_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= fimc_is_3dnr_video_get_format_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= fimc_is_3dnr_video_set_format_mplane,
+	.vidioc_try_fmt_vid_cap_mplane	= fimc_is_3dnr_video_try_format_mplane,
+	.vidioc_cropcap			= fimc_is_3dnr_video_cropcap,
+	.vidioc_g_crop			= fimc_is_3dnr_video_get_crop,
+	.vidioc_s_crop			= fimc_is_3dnr_video_set_crop,
+	.vidioc_reqbufs			= fimc_is_3dnr_video_reqbufs,
+	.vidioc_querybuf		= fimc_is_3dnr_video_querybuf,
+	.vidioc_qbuf			= fimc_is_3dnr_video_qbuf,
+	.vidioc_dqbuf			= fimc_is_3dnr_video_dqbuf,
+	.vidioc_streamon		= fimc_is_3dnr_video_streamon,
+	.vidioc_streamoff		= fimc_is_3dnr_video_streamoff,
+	.vidioc_enum_input		= fimc_is_3dnr_video_enum_input,
+	.vidioc_g_input			= fimc_is_3dnr_video_g_input,
+	.vidioc_s_input			= fimc_is_3dnr_video_s_input,
+};
+
+static int fimc_is_3dnr_queue_setup(struct vb2_queue *vq,
+			unsigned int *num_buffers,
+			unsigned int *num_planes,
+			unsigned long sizes[],
+			void *allocators[])
+{
+
+	struct fimc_is_video_dev *video = vq->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int i;
+
+	*num_planes = isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+			frame.format.num_planes;
+	set_plane_size(&isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame, sizes);
+
+	for (i = 0; i < *num_planes; i++)
+		allocators[i] =  isp->alloc_ctx;
+
+	dbg("(num_planes : %d)(size : %d)\n", (int)*num_planes, (int)sizes[0]);
+
+	return 0;
+}
+
+static int fimc_is_3dnr_buffer_prepare(struct vb2_buffer *vb)
+{
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+static inline void fimc_is_3dnr_lock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static inline void fimc_is_3dnr_unlock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_3dnr_start_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+	int i, j;
+	int buf_index;
+
+	dbg("%s(pipe_state : %d)\n", __func__, (int)isp->pipe_state);
+
+	if (test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+
+		dbg("IS_ST_CHANGE_MODE\n");
+		set_bit(IS_ST_CHANGE_MODE, &isp->state);
+		fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_CHANGE_MODE_DONE,
+			&isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED,
+			&isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		dbg("IS Stream On\n");
+		fimc_is_hw_set_stream(isp, 1);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_ON, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+		set_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+		/* buffer addr setting */
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf; i++)
+			for (j = 0; j < isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+					frame.format.num_planes; j++) {
+				buf_index
+				= i * isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+						frame.format.num_planes + j;
+				dbg("(%d)set buf(%d:%d) = 0x%08x\n",
+					buf_index, i, j,
+					isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+					buf[i][j]);
+				isp->is_p_region->shared[350+buf_index]
+				= isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf[i][j];
+		}
+
+		dbg("buf_num:%d buf_plane:%d shared[350] : 0x%p\n",
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf,
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+			frame.format.num_planes,
+			isp->mem.kvaddr_shared + 350 * sizeof(u32));
+		for (i = 0; i < isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf; i++)
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_mask |= (1 << i);
+		dbg("initial buffer mask : 0x%08x\n",
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_mask);
+
+		IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(isp,
+			DMA_OUTPUT_COMMAND_ENABLE);
+		IS_TDNR_SET_PARAM_DMA_OUTPUT_MASK(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_mask);
+		IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf);
+		IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+			(u32)isp->mem.dvaddr_shared + 350*sizeof(u32));
+
+		IS_SET_PARAM_BIT(isp, PARAM_TDNR_DMA_OUTPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state);
+	}
+
+	return 0;
+}
+
+static int fimc_is_3dnr_stop_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+
+
+
+	clear_bit(IS_ST_STREAM_OFF, &isp->state);
+	fimc_is_hw_set_stream(isp, 0);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_OFF, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		if (!ret)
+			err("s_power off failed!!\n");
+		return -EBUSY;
+	}
+
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_CMD(isp,
+		DMA_OUTPUT_COMMAND_DISABLE);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERNUM(isp,
+		0);
+	IS_TDNR_SET_PARAM_DMA_OUTPUT_BUFFERADDR(isp,
+		0);
+
+	IS_SET_PARAM_BIT(isp, PARAM_TDNR_DMA_OUTPUT);
+	IS_INC_PARAM_NUM(isp);
+
+	fimc_is_mem_cache_clean((void *)isp->is_p_region,
+		IS_PARAM_SIZE);
+
+	isp->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+	fimc_is_hw_set_param(isp);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout 1: %s\n", __func__);
+		return -EBUSY;
+	}
+
+
+	dbg("IS change mode\n");
+	clear_bit(IS_ST_RUN, &isp->state);
+	set_bit(IS_ST_CHANGE_MODE, &isp->state);
+	fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_CHANGE_MODE_DONE, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"Mode change timeout:%s\n", __func__);
+		return -EBUSY;
+	}
+
+	dbg("IS Stream On");
+	fimc_is_hw_set_stream(isp, 1);
+
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_STREAM_ON, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+
+	if (!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &isp->state);
+		fimc_is_hw_set_stream(isp, 0);
+		dbg("IS Stream Off");
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout 4: %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	clear_bit(IS_ST_RUN, &isp->state);
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+	clear_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED, &isp->pipe_state);
+	clear_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state);
+
+
+	return 0;
+}
+
+static void fimc_is_3dnr_buffer_queue(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	unsigned int i;
+
+	dbg("%s\n", __func__);
+	isp->video[FIMC_IS_VIDEO_NUM_3DNR].frame.format.num_planes
+						= vb->num_planes;
+
+	if (!test_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED, &isp->pipe_state)) {
+		for (i = 0; i < vb->num_planes; i++) {
+			isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+				buf[vb->v4l2_buf.index][i]
+				= isp->vb2->plane_addr(vb, i);
+			dbg("index(%d)(%d) deviceVaddr(0x%08x)\n",
+				vb->v4l2_buf.index, i,
+				isp->video[FIMC_IS_VIDEO_NUM_3DNR].
+				buf[vb->v4l2_buf.index][i]);
+		}
+
+		isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_ref_cnt++;
+
+		if (isp->video[FIMC_IS_VIDEO_NUM_3DNR].num_buf
+			== isp->video[FIMC_IS_VIDEO_NUM_3DNR].buf_ref_cnt)
+			set_bit(FIMC_IS_STATE_3DNR_BUFFER_PREPARED,
+				&isp->pipe_state);
+	}
+
+	if (!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state))
+		fimc_is_3dnr_start_streaming(vb->vb2_queue);
+
+	return;
+}
+
+const struct vb2_ops fimc_is_3dnr_qops = {
+	.queue_setup		= fimc_is_3dnr_queue_setup,
+	.buf_prepare		= fimc_is_3dnr_buffer_prepare,
+	.buf_queue		= fimc_is_3dnr_buffer_queue,
+	.wait_prepare		= fimc_is_3dnr_unlock,
+	.wait_finish		= fimc_is_3dnr_lock,
+	.start_streaming	= fimc_is_3dnr_start_streaming,
+	.stop_streaming	= fimc_is_3dnr_stop_streaming,
+};
+
+
+/*************************************************************************/
+/* video file opertation						 */
+/************************************************************************/
+
+static int fimc_is_bayer_video_open(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	file->private_data = &isp->video[FIMC_IS_VIDEO_NUM_BAYER];
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf = 0;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt = 0;
+
+	if (!test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state)) {
+		isp->sensor_num = 1;
+
+		fimc_is_load_fw(isp);
+
+		set_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	clear_bit(FIMC_IS_STATE_BAYER_STREAM_ON, &isp->pipe_state);
+	fimc_is_fw_clear_irq1_all(isp);
+	return 0;
+
+}
+
+static int fimc_is_bayer_video_close(struct file *file)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	int ret;
+
+	dbg("%s\n", __func__);
+	vb2_queue_release(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq);
+
+	if (!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_3DNR_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->power)) {
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+		fimc_is_hw_subip_poweroff(isp);
+
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			!test_bit(FIMC_IS_PWR_ST_POWER_ON_OFF, &isp->power),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		mutex_unlock(&isp->lock);
+
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			ret = -EINVAL;
+		}
+
+		dbg("staop flite & mipi (pos:%d) (port:%d)\n",
+			isp->sensor.id_position,
+			isp->pdata->
+			sensor_info[isp->sensor.id_position]->flite_id);
+
+		stop_fimc_lite(isp->pdata->
+				sensor_info[isp->sensor.id_position]->flite_id);
+		stop_mipi_csi(isp->pdata->
+				sensor_info[isp->sensor.id_position]->csi_id);
+
+		fimc_is_hw_a5_power(isp, 0);
+		clear_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state);
+	}
+	return 0;
+
+}
+
+static unsigned int fimc_is_bayer_video_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_poll(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, file, wait);
+
+}
+
+static int fimc_is_bayer_video_mmap(struct file *file,
+					struct vm_area_struct *vma)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_mmap(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, vma);
+
+}
+
+/*************************************************************************/
+/* video ioctl operation						*/
+/************************************************************************/
+
+static int fimc_is_bayer_video_querycap(struct file *file, void *fh,
+					struct v4l2_capability *cap)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	strncpy(cap->driver, isp->pdev->name, sizeof(cap->driver) - 1);
+
+	dbg("%s(devname : %s)\n", __func__, cap->driver);
+	strncpy(cap->card, isp->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING
+				| V4L2_CAP_VIDEO_CAPTURE
+				| V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int fimc_is_bayer_video_enum_fmt_mplane(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_get_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_set_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pix;
+	struct fimc_is_fmt *frame;
+
+	dbg("%s\n", __func__);
+
+	pix = &format->fmt.pix_mp;
+	frame = find_format(&pix->pixelformat, NULL, 0);
+
+	if (!frame)
+		return -EINVAL;
+
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.format.pixelformat
+							= frame->pixelformat;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.format.mbus_code
+							= frame->mbus_code;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.format.num_planes
+							= frame->num_planes;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.width = pix->width;
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.height = pix->height;
+	dbg("num_planes : %d\n", frame->num_planes);
+	dbg("width : %d\n", pix->width);
+	dbg("height : %d\n", pix->height);
+
+	return 0;
+}
+
+static int fimc_is_bayer_video_try_format_mplane(struct file *file, void *fh,
+						struct v4l2_format *format)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_cropcap(struct file *file, void *fh,
+						struct v4l2_cropcap *cropcap)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_get_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_set_crop(struct file *file, void *fh,
+						struct v4l2_crop *crop)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_reqbufs(struct file *file, void *priv,
+					struct v4l2_requestbuffers *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	ret = vb2_reqbufs(&video->vbq, buf);
+	if (!ret)
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf = buf->count;
+
+	if (buf->count == 0)
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt = 0;
+
+	dbg("%s(num_buf | %d)\n", __func__,
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf);
+
+	return ret;
+}
+
+static int fimc_is_bayer_video_querybuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int ret;
+	struct fimc_is_video_dev *video = file->private_data;
+
+	dbg("%s\n", __func__);
+	ret = vb2_querybuf(&video->vbq, buf);
+
+	return ret;
+}
+
+static int fimc_is_bayer_video_qbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	if (test_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED, &isp->pipe_state)) {
+		video->buf_mask |= (1<<buf->index);
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_mask = video->buf_mask;
+
+		dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+	} else {
+		dbg("index(%d)\n", buf->index);
+	}
+	vb_ret = vb2_qbuf(&video->vbq, buf);
+
+	return vb_ret;
+}
+
+static int fimc_is_bayer_video_dqbuf(struct file *file, void *priv,
+						struct v4l2_buffer *buf)
+{
+	int vb_ret;
+	struct fimc_is_video_dev *video = file->private_data;
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	vb_ret = vb2_dqbuf(&video->vbq, buf, file->f_flags & O_NONBLOCK);
+
+	video->buf_mask &= ~(1<<buf->index);
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_mask = video->buf_mask;
+
+	dbg("index(%d) mask(0x%08x)\n", buf->index, video->buf_mask);
+
+	return vb_ret;
+}
+
+static int fimc_is_bayer_video_streamon(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamon(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, type);
+}
+
+static int fimc_is_bayer_video_streamoff(struct file *file, void *priv,
+						enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+
+	dbg("%s\n", __func__);
+	return vb2_streamoff(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, type);
+}
+
+static int fimc_is_bayer_video_enum_input(struct file *file, void *priv,
+						struct v4l2_input *input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+				= isp->pdata->sensor_info[input->index];
+
+	dbg("index(%d) sensor(%s)\n",
+		input->index, sensor_info->sensor_name);
+	dbg("pos(%d) sensor_id(%d)\n",
+		sensor_info->sensor_position, sensor_info->sensor_id);
+	dbg("csi_id(%d) flite_id(%d)\n",
+		sensor_info->csi_id, sensor_info->flite_id);
+	dbg("i2c_ch(%d)\n", sensor_info->i2c_channel);
+
+	if (input->index >= FIMC_IS_MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(input->name, sensor_info->sensor_name,
+					FIMC_IS_MAX_SENSOR_NAME_LEN);
+	return 0;
+}
+
+static int fimc_is_bayer_video_g_input(struct file *file, void *priv,
+						unsigned int *input)
+{
+	dbg("%s\n", __func__);
+	return 0;
+}
+
+static int fimc_is_bayer_video_s_input(struct file *file, void *priv,
+						unsigned int input)
+{
+	struct fimc_is_dev *isp = video_drvdata(file);
+	struct exynos5_fimc_is_sensor_info *sensor_info
+				= isp->pdata->sensor_info[input];
+
+	isp->sensor.id_position = input;
+	isp->sensor.sensor_type
+		= fimc_is_hw_get_sensor_type(sensor_info->sensor_id,
+						sensor_info->flite_id);
+
+	fimc_is_hw_set_default_size(isp, sensor_info->sensor_id);
+
+	dbg("sensor info : pos(%d) type(%d)\n", input, isp->sensor.sensor_type);
+
+
+	return 0;
+}
+
+const struct v4l2_file_operations fimc_is_bayer_video_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_is_bayer_video_open,
+	.release	= fimc_is_bayer_video_close,
+	.poll		= fimc_is_bayer_video_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= fimc_is_bayer_video_mmap,
+};
+
+const struct v4l2_ioctl_ops fimc_is_bayer_video_ioctl_ops = {
+	.vidioc_querycap		= fimc_is_bayer_video_querycap,
+	.vidioc_enum_fmt_vid_cap_mplane	= fimc_is_bayer_video_enum_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= fimc_is_bayer_video_get_format_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= fimc_is_bayer_video_set_format_mplane,
+	.vidioc_try_fmt_vid_cap_mplane	= fimc_is_bayer_video_try_format_mplane,
+	.vidioc_cropcap			= fimc_is_bayer_video_cropcap,
+	.vidioc_g_crop			= fimc_is_bayer_video_get_crop,
+	.vidioc_s_crop			= fimc_is_bayer_video_set_crop,
+	.vidioc_reqbufs			= fimc_is_bayer_video_reqbufs,
+	.vidioc_querybuf		= fimc_is_bayer_video_querybuf,
+	.vidioc_qbuf			= fimc_is_bayer_video_qbuf,
+	.vidioc_dqbuf			= fimc_is_bayer_video_dqbuf,
+	.vidioc_streamon		= fimc_is_bayer_video_streamon,
+	.vidioc_streamoff		= fimc_is_bayer_video_streamoff,
+	.vidioc_enum_input		= fimc_is_bayer_video_enum_input,
+	.vidioc_g_input			= fimc_is_bayer_video_g_input,
+	.vidioc_s_input			= fimc_is_bayer_video_s_input,
+};
+
+static int fimc_is_bayer_queue_setup(struct vb2_queue *vq,
+			unsigned int *num_buffers,
+			unsigned int *num_planes,
+			unsigned long sizes[],
+			void *allocators[])
+{
+
+	struct fimc_is_video_dev *video = vq->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int i;
+
+	*num_planes = isp->video[FIMC_IS_VIDEO_NUM_BAYER].
+					frame.format.num_planes;
+	set_plane_size(&isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame, sizes);
+
+	for (i = 0; i < *num_planes; i++)
+		allocators[i] =  isp->alloc_ctx;
+
+	dbg("(num_planes : %d)(size : %d)\n", (int)*num_planes, (int)sizes[0]);
+
+	return 0;
+}
+
+static int fimc_is_bayer_buffer_prepare(struct vb2_buffer *vb)
+{
+	dbg("--%s\n", __func__);
+	return 0;
+}
+
+static inline void fimc_is_bayer_lock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static inline void fimc_is_bayer_unlock(struct vb2_queue *vq)
+{
+	dbg("%s\n", __func__);
+}
+
+static int fimc_is_bayer_start_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+	int i, j;
+	int buf_index;
+
+	dbg("%s(pipe_state : %d)\n", __func__, (int)isp->pipe_state);
+
+	if (test_bit(FIMC_IS_STATE_FW_DOWNLOADED, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED,
+						&isp->pipe_state)) {
+
+		dbg("IS_ST_CHANGE_MODE\n");
+		set_bit(IS_ST_CHANGE_MODE, &isp->state);
+		fimc_is_hw_change_mode(isp, IS_MODE_PREVIEW_STILL);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_CHANGE_MODE_DONE,
+			&isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"Mode change timeout:%s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED,
+			&isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state)) {
+		dbg("IS Stream On\n");
+		fimc_is_hw_set_stream(isp, 1);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_ON, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &isp->state);
+
+		set_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	if (test_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state) &&
+		test_bit(FIMC_IS_STATE_SENSOR_INITIALIZED, &isp->pipe_state)) {
+		/* buffer addr setting */
+		for (i = 0; i < isp->
+			video[FIMC_IS_VIDEO_NUM_BAYER].num_buf; i++)
+			for (j = 0; j < isp->video[FIMC_IS_VIDEO_NUM_BAYER].
+						frame.format.num_planes; j++) {
+				buf_index = i * isp->
+					video[FIMC_IS_VIDEO_NUM_BAYER].
+					frame.format.num_planes + j;
+
+				dbg("(%d)set buf(%d:%d) = 0x%08x\n",
+					buf_index, i, j,
+					isp->video[FIMC_IS_VIDEO_NUM_BAYER].
+					buf[i][j]);
+
+				isp->is_p_region->shared[116 + buf_index]
+				= isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf[i][j];
+		}
+
+		dbg("buf_num:%d buf_plane:%d shared[116] : 0x%p\n",
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf,
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.format.num_planes,
+		isp->mem.kvaddr_shared + 116 * sizeof(u32));
+
+		for (i = 0; i < isp->
+			video[FIMC_IS_VIDEO_NUM_BAYER].num_buf; i++)
+			isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_mask
+							|= (1 << i);
+
+		dbg("initial buffer mask : 0x%08x\n",
+			isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_mask);
+
+
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(isp,
+			DMA_OUTPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_MASK(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_mask);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(isp,
+			isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(isp,
+			(u32)isp->mem.dvaddr_shared + 116 * sizeof(u32));
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(isp,
+			(u32)isp->mem.dvaddr_shared + 116 * sizeof(u32));
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_DMA_DONE(isp,
+			DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE);
+
+		IS_SET_PARAM_BIT(isp, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(isp);
+
+		fimc_is_mem_cache_clean((void *)isp->is_p_region,
+			IS_PARAM_SIZE);
+
+		isp->scenario_id = ISS_PREVIEW_STILL;
+		set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+		clear_bit(IS_ST_INIT_CAPTURE_STILL, &isp->state);
+		clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+		fimc_is_hw_set_param(isp);
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+
+		set_bit(FIMC_IS_STATE_BAYER_STREAM_ON, &isp->pipe_state);
+	}
+
+	return 0;
+}
+
+static int fimc_is_bayer_stop_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = q->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	int ret;
+
+
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(isp,
+			DMA_OUTPUT_COMMAND_DISABLE);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(isp,
+		0);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(isp,
+		0);
+
+	IS_SET_PARAM_BIT(isp, PARAM_ISP_DMA2_OUTPUT);
+	IS_INC_PARAM_NUM(isp);
+
+	fimc_is_mem_cache_clean((void *)isp->is_p_region,
+		IS_PARAM_SIZE);
+
+	isp->scenario_id = ISS_PREVIEW_STILL;
+	set_bit(IS_ST_INIT_PREVIEW_STILL,	&isp->state);
+	clear_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state);
+	fimc_is_hw_set_param(isp);
+	mutex_lock(&isp->lock);
+	ret = wait_event_timeout(isp->irq_queue,
+		test_bit(IS_ST_INIT_PREVIEW_VIDEO, &isp->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	mutex_unlock(&isp->lock);
+	if (!ret) {
+		dev_err(&isp->pdev->dev,
+			"wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+
+
+	if (!test_bit(FIMC_IS_STATE_SCALERC_STREAM_ON, &isp->pipe_state) &&
+		!test_bit(FIMC_IS_STATE_SCALERP_STREAM_ON, &isp->pipe_state)) {
+		clear_bit(IS_ST_STREAM_OFF, &isp->state);
+		fimc_is_hw_set_stream(isp, 0);
+		dbg("IS Stream Off");
+		mutex_lock(&isp->lock);
+		ret = wait_event_timeout(isp->irq_queue,
+			test_bit(IS_ST_STREAM_OFF, &isp->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT);
+		mutex_unlock(&isp->lock);
+		if (!ret) {
+			dev_err(&isp->pdev->dev,
+				"wait timeout : %s\n", __func__);
+			return -EBUSY;
+		}
+		clear_bit(FIMC_IS_STATE_HW_STREAM_ON, &isp->pipe_state);
+	}
+
+	clear_bit(IS_ST_RUN, &isp->state);
+	clear_bit(IS_ST_STREAM_ON, &isp->state);
+	clear_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED, &isp->pipe_state);
+	clear_bit(FIMC_IS_STATE_BAYER_STREAM_ON, &isp->pipe_state);
+
+
+	return 0;
+}
+
+static void fimc_is_bayer_buffer_queue(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev	*isp = video->dev;
+	unsigned int i;
+
+	dbg("%s\n", __func__);
+	isp->video[FIMC_IS_VIDEO_NUM_BAYER].frame.format.num_planes
+							= vb->num_planes;
+
+	if (!test_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED, &isp->pipe_state)) {
+		for (i = 0; i < vb->num_planes; i++) {
+			isp->video[FIMC_IS_VIDEO_NUM_BAYER].
+			buf[vb->v4l2_buf.index][i]
+				= isp->vb2->plane_addr(vb, i);
+
+			dbg("index(%d)(%d) deviceVaddr(0x%08x)\n",
+				vb->v4l2_buf.index, i,
+				isp->video[FIMC_IS_VIDEO_NUM_BAYER].
+				buf[vb->v4l2_buf.index][i]);
+		}
+
+		isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt++;
+
+		if (isp->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf
+			== isp->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt)
+			set_bit(FIMC_IS_STATE_BAYER_BUFFER_PREPARED,
+						&isp->pipe_state);
+	}
+
+	if (!test_bit(FIMC_IS_STATE_BAYER_STREAM_ON, &isp->pipe_state))
+		fimc_is_bayer_start_streaming(vb->vb2_queue);
+
+	return;
+}
+
+const struct vb2_ops fimc_is_bayer_qops = {
+	.queue_setup		= fimc_is_bayer_queue_setup,
+	.buf_prepare		= fimc_is_bayer_buffer_prepare,
+	.buf_queue		= fimc_is_bayer_buffer_queue,
+	.wait_prepare		= fimc_is_bayer_unlock,
+	.wait_finish		= fimc_is_bayer_lock,
+	.start_streaming	= fimc_is_bayer_start_streaming,
+	.stop_streaming	= fimc_is_bayer_stop_streaming,
+};
+
diff --git a/drivers/media/video/exynos/fimc-is/Kconfig b/drivers/media/video/exynos/fimc-is/Kconfig
new file mode 100644
index 0000000..28e7413
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/Kconfig
@@ -0,0 +1,12 @@
+config VIDEO_EXYNOS_FIMC_IS
+	bool "Exynos FIMC-IS (Image Subsystem) driver"
+	depends on VIDEO_EXYNOS && ARCH_EXYNOS4
+	default n
+	help
+	  This is a v4l2 subdev driver for samsung FIMC-IS device.
+config VIDEO_EXYNOS_FIMC_IS_BAYER
+	bool "Enable FIMC-IS bayer write"
+	depends on VIDEO_EXYNOS_FIMC_IS
+	default n
+	help
+	  Enable to write bayer output image.
diff --git a/drivers/media/video/exynos/fimc-is/Makefile b/drivers/media/video/exynos/fimc-is/Makefile
new file mode 100644
index 0000000..fb28f96
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS) := fimc-is-core.o fimc-is-v4l2.o fimc-is-helper.o fimc-is-err.o fimc-is-mem.o 
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER) += fimc-is-vb2.o fimc-is-video.o
+EXTRA_CFLAGS += -Idrivers/media/video
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-cmd.h b/drivers/media/video/exynos/fimc-is/fimc-is-cmd.h
new file mode 100644
index 0000000..1515a7f
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-cmd.h
@@ -0,0 +1,170 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Command list
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CMD_H_
+#define FIMC_IS_CMD_H_
+
+#define IS_COMMAND_VER 110 /* IS COMMAND VERSION 1.10 */
+
+enum is_cmd {
+	/* HOST -> IS */
+	HIC_PREVIEW_STILL = 0x1,
+	HIC_PREVIEW_VIDEO,
+	HIC_CAPTURE_STILL,
+	HIC_CAPTURE_VIDEO,
+	HIC_STREAM_ON,
+	HIC_STREAM_OFF,
+	HIC_SET_PARAMETER,
+	HIC_GET_PARAMETER,
+	HIC_SET_TUNE,
+	RESERVED1,
+	HIC_GET_STATUS,
+	/* SENSOR PART*/
+	HIC_OPEN_SENSOR,
+	HIC_CLOSE_SENSOR,
+	HIC_SIMMIAN_INIT,
+	HIC_SIMMIAN_WRITE,
+	HIC_SIMMIAN_READ,
+	HIC_POWER_DOWN,
+	HIC_GET_SET_FILE_ADDR,
+	HIC_LOAD_SET_FILE,
+	HIC_MSG_CONFIG,
+	HIC_MSG_TEST,
+	/* IS -> HOST */
+	IHC_GET_SENSOR_NUMBER = 0x1000,
+	IHC_SET_SHOT_MARK,
+	/* PARAM1 : a frame number */
+	/* PARAM2 : confidence level(smile 0~100) */
+	/* PARMA3 : confidence level(blink 0~100) */
+	IHC_SET_FACE_MARK,
+	/* PARAM1 : coordinate count */
+	/* PARAM2 : coordinate buffer address */
+	IHC_FRAME_DONE,
+	/* PARAM1 : frame start number */
+	/* PARAM2 : frame count */
+	IHC_AA_DONE,
+	IHC_NOT_READY
+};
+
+enum is_reply {
+	ISR_DONE	= 0x2000,
+	ISR_NDONE
+};
+
+enum is_scenario_id {
+	ISS_PREVIEW_STILL,
+	ISS_PREVIEW_VIDEO,
+	ISS_CAPTURE_STILL,
+	ISS_CAPTURE_VIDEO,
+	ISS_END
+};
+
+enum is_sub_scenario_id {
+	ISS_SUB_SCENARIO_DEFAULT = 0,
+	ISS_SUB_PS_VTCALL = 1,
+	ISS_SUB_CS_VTCALL = 2,
+	ISS_SUB_PV_VTCALL = 3,
+	ISS_SUB_CV_VTCALL = 4,
+	ISS_SUB_END
+};
+
+struct is_get_capability {
+	u32 support_af;
+	u32 iso_gain;
+	u32 aperture;
+	u32 min_exposure;
+	u32 max_exposure;
+	u32 min_gain;
+	u32 max_gain;
+};
+
+#define HOST_SET_INT_BIT	0x00000001
+#define HOST_CLR_INT_BIT	0x00000001
+#define IS_SET_INT_BIT		0x00000001
+#define IS_CLR_INT_BIT		0x00000001
+
+#define HOST_SET_INTERRUPT(base)	(base->uiINTGR0 |= HOST_SET_INT_BIT)
+#define HOST_CLR_INTERRUPT(base)	(base->uiINTCR0 |= HOST_CLR_INT_BIT)
+#define IS_SET_INTERRUPT(base)		(base->uiINTGR1 |= IS_SET_INT_BIT)
+#define IS_CLR_INTERRUPT(base)		(base->uiINTCR1 |= IS_CLR_INT_BIT)
+
+struct is_common_reg {
+	u32 hicmd;
+	u32 hic_sensorid;
+	u32 hic_param1;
+	u32 hic_param2;
+	u32 hic_param3;
+	u32 hic_param4;
+
+	u32 reserved1[4];
+
+	u32 ihcmd;
+	u32 ihc_sensorid;
+	u32 ihc_param1;
+	u32 ihc_param2;
+	u32 ihc_param3;
+	u32 ihc_param4;
+
+	u32 reserved2[4];
+
+	u32 isp_sensor_id;
+	u32 isp_param1;
+	u32 isp_param2;
+	u32 reserved3[1];
+
+	u32 scc_sensor_id;
+	u32 scc_param1;
+	u32 scc_param2;
+	u32 reserved4[1];
+
+	u32 dnr_sensor_id;
+	u32 dnr_param1;
+	u32 dnr_param2;
+	u32 reserved5[1];
+
+	u32 scp_sensor_id;
+	u32 scp_param1;
+	u32 scp_param2;
+	u32 reserved6[29];
+};
+
+struct is_mcuctl_reg {
+	u32 mcuctl;
+	u32 bboar;
+
+	u32 intgr0;
+	u32 intcr0;
+	u32 intmr0;
+	u32 intsr0;
+	u32 intmsr0;
+
+	u32 intgr1;
+	u32 intcr1;
+	u32 intmr1;
+	u32 intsr1;
+	u32 intmsr1;
+
+	u32 intcr2;
+	u32 intmr2;
+	u32 intsr2;
+	u32 intmsr2;
+
+	u32 gpoctrl;
+	u32 cpoenctlr;
+	u32 gpictlr;
+
+	u32 pad[0xD];
+
+	struct is_common_reg common_reg;
+};
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-core.c b/drivers/media/video/exynos/fimc-is/fimc-is-core.c
new file mode 100644
index 0000000..59da8d1
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-core.c
@@ -0,0 +1,666 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * main platform driver interface
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+
+#include <linux/cma.h>
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <media/videobuf2-core.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-err.h"
+
+extern struct class *camera_class;
+struct device *s5k6a3_dev; /*sys/class/camera/front*/
+
+struct fimc_is_dev *to_fimc_is_dev(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct fimc_is_dev, sd);
+}
+
+static void fimc_is_irq_handler_general(struct fimc_is_dev *dev)
+{
+	/* Read ISSR10 ~ ISSR15 */
+	dev->i2h_cmd.cmd = readl(dev->regs + ISSR10);
+
+	switch (dev->i2h_cmd.cmd) {
+	case IHC_GET_SENSOR_NUMBER:
+		dbg("IHC_GET_SENSOR_NUMBER\n");
+		fimc_is_hw_get_param(dev, 1);
+			dbg("ISP - FW version - %d\n", dev->i2h_cmd.arg[0]);
+		dev->fw.ver = dev->i2h_cmd.arg[0];
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		fimc_is_hw_set_sensor_num(dev);
+		break;
+	case IHC_SET_SHOT_MARK:
+		fimc_is_hw_get_param(dev, 3);
+		break;
+	case IHC_SET_FACE_MARK:
+		fimc_is_hw_get_param(dev, 2);
+		break;
+	case IHC_FRAME_DONE:
+		fimc_is_hw_get_param(dev, 2);
+		break;
+	case IHC_NOT_READY:
+		break;
+	case IHC_AA_DONE:
+		fimc_is_hw_get_param(dev, 3);
+		break;
+	case ISR_DONE:
+		fimc_is_hw_get_param(dev, 3);
+		break;
+	case ISR_NDONE:
+		fimc_is_hw_get_param(dev, 4);
+		break;
+	}
+
+	/* Just clear the interrupt pending bits. */
+	fimc_is_fw_clear_irq1(dev, INTR_GENERAL);
+
+	switch (dev->i2h_cmd.cmd) {
+	case IHC_GET_SENSOR_NUMBER:
+		fimc_is_hw_set_intgr0_gd0(dev);
+		set_bit(IS_ST_FW_LOADED, &dev->state);
+		break;
+	case IHC_SET_SHOT_MARK:
+		break;
+	case IHC_SET_FACE_MARK:
+		dev->fd_header.count = dev->i2h_cmd.arg[0];
+		dev->fd_header.index = dev->i2h_cmd.arg[1];
+		/* Implementation of AF with face */
+		if (dev->af.mode == IS_FOCUS_MODE_CONTINUOUS &&
+				dev->af.af_state == FIMC_IS_AF_LOCK) {
+			fimc_is_af_face(dev);
+		} else if (dev->af.mode == IS_FOCUS_MODE_FACEDETECT) {
+			/* Using face information once only */
+			fimc_is_af_face(dev);
+			dev->af.mode = IS_FOCUS_MODE_IDLE;
+		}
+		break;
+	case IHC_FRAME_DONE:
+		break;
+	case IHC_AA_DONE:
+		dbg("AA_DONE - %d, %d, %d\n", dev->i2h_cmd.arg[0],
+			dev->i2h_cmd.arg[1], dev->i2h_cmd.arg[2]);
+		switch (dev->i2h_cmd.arg[0]) {
+		/* SEARCH: Occurs when search is requested at continuous AF */
+		case 2:
+			break;
+		/* INFOCUS: Occurs when focus is found. */
+		case 3:
+			if (dev->af.af_state == FIMC_IS_AF_RUNNING)
+				dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = 0x2;
+			break;
+		/* OUTOFFOCUS: Occurs when focus is not found. */
+		case 4:
+			if (dev->af.af_state == FIMC_IS_AF_RUNNING)
+				dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = 0x1;
+			break;
+		}
+		break;
+	case IHC_NOT_READY:
+		err("Init Sequnce Error- IS will be turned off!!");
+		break;
+	case ISR_DONE:
+		dbg("ISR_DONE - %d\n", dev->i2h_cmd.arg[0]);
+		switch (dev->i2h_cmd.arg[0]) {
+		case HIC_PREVIEW_STILL:
+		case HIC_PREVIEW_VIDEO:
+		case HIC_CAPTURE_STILL:
+		case HIC_CAPTURE_VIDEO:
+			set_bit(IS_ST_CHANGE_MODE, &dev->state);
+			/* Get CAC margin */
+			dev->sensor.offset_x = dev->i2h_cmd.arg[1];
+			dev->sensor.offset_y = dev->i2h_cmd.arg[2];
+			break;
+		case HIC_STREAM_ON:
+			clear_bit(IS_ST_STREAM_OFF, &dev->state);
+			set_bit(IS_ST_STREAM_ON, &dev->state);
+			break;
+		case HIC_STREAM_OFF:
+			clear_bit(IS_ST_STREAM_ON, &dev->state);
+			set_bit(IS_ST_STREAM_OFF, &dev->state);
+			break;
+		case HIC_SET_PARAMETER:
+			dev->p_region_index1 = 0;
+			dev->p_region_index2 = 0;
+			atomic_set(&dev->p_region_num, 0);
+			set_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+
+			if (dev->af.af_state == FIMC_IS_AF_SETCONFIG)
+				dev->af.af_state = FIMC_IS_AF_RUNNING;
+			else if (dev->af.af_state == FIMC_IS_AF_ABORT)
+				dev->af.af_state = FIMC_IS_AF_IDLE;
+			break;
+		case HIC_GET_PARAMETER:
+			break;
+		case HIC_SET_TUNE:
+			break;
+		case HIC_GET_STATUS:
+			break;
+		case HIC_OPEN_SENSOR:
+			set_bit(IS_ST_OPEN_SENSOR, &dev->state);
+			printk(KERN_INFO "FIMC-IS Lane= %d, Settle line= %d\n",
+				dev->i2h_cmd.arg[2], dev->i2h_cmd.arg[1]);
+			break;
+		case HIC_CLOSE_SENSOR:
+			clear_bit(IS_ST_OPEN_SENSOR, &dev->state);
+			dev->sensor.id = 0;
+			break;
+		case HIC_MSG_TEST:
+			dbg("Config MSG level was done\n");
+			break;
+		case HIC_POWER_DOWN:
+			set_bit(IS_PWR_SUB_IP_POWER_OFF, &dev->power);
+			break;
+		case HIC_GET_SET_FILE_ADDR:
+			dev->setfile.base = dev->i2h_cmd.arg[1];
+			set_bit(IS_ST_SETFILE_LOADED, &dev->state);
+			break;
+		case HIC_LOAD_SET_FILE:
+			set_bit(IS_ST_SETFILE_LOADED, &dev->state);
+			break;
+		}
+		break;
+	case ISR_NDONE:
+		err("ISR_NDONE - %d: 0x%08x\n", dev->i2h_cmd.arg[0],
+			dev->i2h_cmd.arg[1]);
+		fimc_is_print_err_number(dev->i2h_cmd.arg[1]);
+		switch (dev->i2h_cmd.arg[1]) {
+		case IS_ERROR_SET_PARAMETER:
+			fimc_is_mem_cache_inv((void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_param_err_checker(dev);
+			break;
+		}
+	}
+}
+
+static void fimc_is_irq_handler_isp(struct fimc_is_dev *dev)
+{
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+	int buf_index;
+#endif
+	/* INTR_FRAME_DONE_ISP */
+	dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR20);
+	dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR21);
+	fimc_is_fw_clear_irq1(dev, INTR_FRAME_DONE_ISP);
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+	buf_index = (dev->i2h_cmd.arg[1] - 1)
+				% dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf;
+	vb2_buffer_done(dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq.bufs[buf_index],
+			VB2_BUF_STATE_DONE);
+#endif
+}
+
+static irqreturn_t fimc_is_irq_handler1(int irq, void *dev_id)
+{
+	struct fimc_is_dev *dev = dev_id;
+	unsigned int intr_status;
+
+	intr_status = readl(dev->regs + INTSR1);
+
+	/* INTR_GENERAL */
+	if (intr_status & BIT0)
+		fimc_is_irq_handler_general(dev);
+	else if (intr_status & BIT1)
+		fimc_is_irq_handler_isp(dev);
+	wake_up(&dev->irq_queue1);
+	return IRQ_HANDLED;
+}
+
+static ssize_t s5k6a3_camera_front_camtype_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "SLSI_S5K6A3_FIMC_IS";
+
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t s5k6a3_camera_front_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[] = "S5K6A3";
+	return sprintf(buf, "%s %s\n", type, type);
+
+}
+
+static DEVICE_ATTR(front_camtype, S_IRUGO,
+		s5k6a3_camera_front_camtype_show, NULL);
+static DEVICE_ATTR(front_camfw, S_IRUGO, s5k6a3_camera_front_camfw_show, NULL);
+
+static int fimc_is_probe(struct platform_device *pdev)
+{
+	struct exynos4_platform_fimc_is *pdata;
+	struct resource *mem_res;
+	struct resource *regs_res;
+	struct fimc_is_dev *dev;
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+	struct v4l2_device *v4l2_dev;
+	struct vb2_queue *isp_q;
+#endif
+	int ret = -ENODEV;
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "Not enough memory for FIMC-IS device.\n");
+		return -ENOMEM;
+	}
+	mutex_init(&dev->lock);
+	spin_lock_init(&dev->slock);
+	init_waitqueue_head(&dev->irq_queue1);
+
+	dev->pdev = pdev;
+	if (!dev->pdev) {
+		dev_err(&pdev->dev, "No platform data specified\n");
+		goto p_err_info;
+	}
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "Platform data not set\n");
+		goto p_err_info;
+	}
+	dev->pdata = pdata;
+	/*
+	 * I/O remap
+	*/
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "Failed to get io memory region\n");
+		ret = -ENOENT;
+		goto p_err_info;
+	}
+
+	regs_res = request_mem_region(mem_res->start,
+		resource_size(mem_res), pdev->name);
+	if (!regs_res) {
+		dev_err(&pdev->dev, "Failed to request io memory region\n");
+		ret = -ENOENT;
+		goto p_err_info;
+	}
+	dev->regs_res = regs_res;
+
+	dev->regs = ioremap(mem_res->start, resource_size(mem_res));
+	if (!dev->regs) {
+		dev_err(&pdev->dev, "Failed to remap io region\n");
+		ret = -ENXIO;
+		goto p_err_req_region;
+	}
+
+	/*
+	 * initialize IRQ , FIMC-IS IRQ : ISP[0] -> SPI[90] , ISP[1] -> SPI[95]
+	*/
+	dev->irq1 = platform_get_irq(pdev, 0);
+	if (dev->irq1 < 0) {
+		ret = dev->irq1;
+		dev_err(&pdev->dev, "Failed to get irq\n");
+		goto p_err_get_irq;
+	}
+
+	ret = request_irq(dev->irq1, fimc_is_irq_handler1,
+		IRQF_DISABLED, dev_name(&pdev->dev), dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to allocate irq (%d)\n", ret);
+		goto p_err_req_irq;
+	}
+
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+	/* Init v4l2 device (ISP) */
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	dev->vb2 = &fimc_is_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	dev->vb2 = &fimc_is_vb2_ion;
+#endif
+
+	/* Init and register V4L2 device */
+	v4l2_dev = &dev->video[FIMC_IS_VIDEO_NUM_BAYER].v4l2_dev;
+	if (!v4l2_dev->name[0])
+		snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
+			 "%s.isp", dev_name(&dev->pdev->dev));
+	ret = v4l2_device_register(NULL, v4l2_dev);
+
+	snprintf(dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.name,
+			sizeof(dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.name),
+			"%s", "exynos4-fimc-is-bayer");
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.fops		=
+						&fimc_is_isp_video_fops;
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.ioctl_ops	=
+						&fimc_is_isp_video_ioctl_ops;
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.minor		= -1;
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.release		=
+						video_device_release;
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.lock		=
+						&dev->lock;
+	video_set_drvdata(&dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd, dev);
+	dev->video[FIMC_IS_VIDEO_NUM_BAYER].dev = dev;
+
+	isp_q = &dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq;
+	memset(isp_q, 0, sizeof(*isp_q));
+	isp_q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	isp_q->io_modes = VB2_MMAP | VB2_USERPTR;
+	isp_q->drv_priv = &dev->video[FIMC_IS_VIDEO_NUM_BAYER];
+	isp_q->ops = &fimc_is_isp_qops;
+	isp_q->mem_ops = dev->vb2->ops;
+
+	vb2_queue_init(isp_q);
+
+	ret = video_register_device(&dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd,
+							VFL_TYPE_GRABBER, 30);
+	if (ret) {
+		v4l2_err(v4l2_dev, "Failed to register video device\n");
+		goto err_vd_reg;
+	}
+
+	printk(KERN_INFO "FIMC-IS Video node :: ISP %d minor : %d\n",
+		dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.num,
+		dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd.minor);
+#endif
+	/*
+	 * initialize memory manager
+	*/
+	ret = fimc_is_init_mem_mgr(dev);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"failed to fimc_is_init_mem_mgr (%d)\n", ret);
+		goto p_err_init_mem;
+	}
+	dbg("Parameter region = 0x%08x\n", (unsigned int)dev->is_p_region);
+
+	/*
+	 * Get related clock for FIMC-IS
+	*/
+	if (dev->pdata->clk_get) {
+		dev->pdata->clk_get(pdev);
+	} else {
+		err("#### failed to Get Clock####\n");
+		goto p_err_init_mem;
+	}
+	/* Init v4l2 sub device */
+	v4l2_subdev_init(&dev->sd, &fimc_is_subdev_ops);
+	dev->sd.owner = THIS_MODULE;
+	strcpy(dev->sd.name, MODULE_NAME);
+	v4l2_set_subdevdata(&dev->sd, pdev);
+
+	platform_set_drvdata(pdev, &dev->sd);
+
+	pm_runtime_enable(&pdev->dev);
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* To lock bus frequency in OPP mode */
+	dev->bus_dev = dev_get("exynos-busfreq");
+#endif
+	dev->power = 0;
+	dev->state = 0;
+	dev->sensor_num = FIMC_IS_SENSOR_NUM;
+	dev->sensor.id = 0;
+	dev->p_region_index1 = 0;
+	dev->p_region_index2 = 0;
+	dev->sensor.offset_x = 16;
+	dev->sensor.offset_y = 12;
+	dev->sensor.framerate_update = false;
+	atomic_set(&dev->p_region_num, 0);
+	set_bit(IS_ST_IDLE, &dev->state);
+	set_bit(IS_PWR_ST_POWEROFF, &dev->power);
+	dev->af.af_state = FIMC_IS_AF_IDLE;
+	dev->af.mode = IS_FOCUS_MODE_IDLE;
+	dev->low_power_mode = false;
+	dev->fw.state = 0;
+	dev->setfile.state = 0;
+
+	s5k6a3_dev = device_create(camera_class, NULL, 0, NULL, "front");
+	if (IS_ERR(s5k6a3_dev)) {
+		printk(KERN_ERR "failed to create device!\n");
+	} else {
+		if (device_create_file(s5k6a3_dev, &dev_attr_front_camtype)
+				< 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_front_camtype.attr.name);
+		}
+		if (device_create_file(s5k6a3_dev, &dev_attr_front_camfw) < 0) {
+			printk(KERN_ERR "failed to create device file, %s\n",
+				dev_attr_front_camfw.attr.name);
+		}
+	}
+	printk(KERN_INFO "FIMC-IS probe completed\n");
+	return 0;
+
+p_err_init_mem:
+	free_irq(dev->irq1, dev);
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+err_vd_reg:
+	video_device_release(&dev->video[FIMC_IS_VIDEO_NUM_BAYER].vd);
+#endif
+p_err_req_irq:
+p_err_get_irq:
+	iounmap(dev->regs);
+p_err_req_region:
+	release_mem_region(regs_res->start, resource_size(regs_res));
+p_err_info:
+	dev_err(&dev->pdev->dev, "failed to install\n");
+	kfree(dev);
+	return ret;
+}
+
+static int fimc_is_remove(struct platform_device *pdev)
+{
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+
+	if (dev->pdata->clk_put)
+		dev->pdata->clk_put(pdev);
+	else
+		err("#### failed to Put Clock####\n");
+
+#if defined(CONFIG_VIDEOBUF2_ION)
+	fimc_is_mem_init_mem_cleanup(dev->alloc_ctx);
+#endif
+	kfree(dev);
+	return 0;
+}
+
+static int fimc_is_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+	int ret = 0;
+
+	printk(KERN_INFO "FIMC_IS suspend\n");
+	if (!test_bit(IS_ST_INIT_DONE, &is_dev->state)) {
+		printk(KERN_INFO "FIMC_IS suspend end\n");
+		return 0;
+	}
+	/* If stream was not stopped, stop streaming */
+	if (!test_bit(IS_ST_STREAM_OFF, &is_dev->state)) {
+		err("Not stream off state\n");
+		clear_bit(IS_ST_STREAM_OFF, &is_dev->state);
+		fimc_is_hw_set_stream(is_dev, false);
+		ret = wait_event_timeout(is_dev->irq_queue1,
+				test_bit(IS_ST_STREAM_OFF, &is_dev->state),
+				(HZ));
+		if (!ret) {
+			err("wait timeout : Stream off\n");
+			fimc_is_hw_set_low_poweroff(is_dev, true);
+		}
+	}
+	/* If the power is not off state, turn off the power */
+	if (!test_bit(IS_PWR_ST_POWEROFF, &is_dev->power)) {
+		err("Not power off state\n");
+		if (!test_bit(IS_PWR_SUB_IP_POWER_OFF, &is_dev->power)) {
+			fimc_is_hw_subip_poweroff(is_dev);
+			ret = wait_event_timeout(is_dev->irq_queue1,
+				test_bit(IS_PWR_SUB_IP_POWER_OFF,
+				&is_dev->power), FIMC_IS_SHUTDOWN_TIMEOUT);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				fimc_is_hw_set_low_poweroff(is_dev, true);
+			}
+		}
+		fimc_is_hw_a5_power(is_dev, 0);
+		pm_runtime_put_sync(dev);
+
+		is_dev->sensor.id = 0;
+		is_dev->p_region_index1 = 0;
+		is_dev->p_region_index2 = 0;
+		atomic_set(&is_dev->p_region_num, 0);
+		is_dev->state = 0;
+		set_bit(IS_ST_IDLE, &is_dev->state);
+		is_dev->power = 0;
+		is_dev->af.af_state = FIMC_IS_AF_IDLE;
+		set_bit(IS_PWR_ST_POWEROFF, &is_dev->power);
+	}
+	printk(KERN_INFO "FIMC_IS suspend end\n");
+	return 0;
+}
+
+static int fimc_is_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+
+	printk(KERN_INFO "FIMC_IS resume\n");
+	mutex_lock(&is_dev->lock);
+	mutex_unlock(&is_dev->lock);
+	printk(KERN_INFO "FIMC_IS resume end\n");
+	return 0;
+}
+
+static int fimc_is_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+
+	printk(KERN_INFO "FIMC_IS runtime suspend\n");
+	if (is_dev->pdata->clk_off) {
+		is_dev->pdata->clk_off(pdev);
+	} else {
+		printk(KERN_ERR "#### failed to Clock OFF ####\n");
+		return -EINVAL;
+	}
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* Unlock bus frequency */
+	dev_unlock(is_dev->bus_dev, dev);
+#endif
+#if defined(CONFIG_VIDEOBUF2_ION)
+	if (is_dev->alloc_ctx)
+		fimc_is_mem_suspend(is_dev->alloc_ctx);
+#endif
+	mutex_lock(&is_dev->lock);
+	clear_bit(IS_PWR_ST_POWERON, &is_dev->power);
+	set_bit(IS_PWR_ST_POWEROFF, &is_dev->power);
+	mutex_unlock(&is_dev->lock);
+	printk(KERN_INFO "FIMC_IS runtime suspend end\n");
+	return 0;
+}
+
+static int fimc_is_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+
+	printk(KERN_INFO "FIMC_IS runtime resume\n");
+	if (is_dev->pdata->clk_cfg) {
+		is_dev->pdata->clk_cfg(pdev);
+	} else {
+		printk(KERN_ERR "#### failed to Clock CONFIG ####\n");
+		return -EINVAL;
+	}
+	if (is_dev->pdata->clk_on) {
+		is_dev->pdata->clk_on(pdev);
+	} else {
+		printk(KERN_ERR "#### failed to Clock On ####\n");
+		return -EINVAL;
+	}
+	is_dev->frame_count = 0;
+#if defined(CONFIG_VIDEOBUF2_ION)
+	if (is_dev->alloc_ctx)
+		fimc_is_mem_resume(is_dev->alloc_ctx);
+#endif
+	mutex_lock(&is_dev->lock);
+	clear_bit(IS_PWR_ST_POWEROFF, &is_dev->power);
+	clear_bit(IS_PWR_SUB_IP_POWER_OFF, &is_dev->power);
+	set_bit(IS_PWR_ST_POWERON, &is_dev->power);
+	mutex_unlock(&is_dev->lock);
+	printk(KERN_INFO "FIMC_IS runtime resume end\n");
+	return 0;
+}
+
+static const struct dev_pm_ops fimc_is_pm_ops = {
+	.suspend	 = fimc_is_suspend,
+	.resume		 = fimc_is_resume,
+	.runtime_suspend = fimc_is_runtime_suspend,
+	.runtime_resume	 = fimc_is_runtime_resume,
+};
+
+static struct platform_driver fimc_is_driver = {
+	.probe		= fimc_is_probe,
+	.remove		= fimc_is_remove,
+	.driver		= {
+		.name	= MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &fimc_is_pm_ops,
+	},
+};
+
+static int __init fimc_is_init(void)
+{
+	int ret;
+	ret = platform_driver_register(&fimc_is_driver);
+	if (ret)
+		err("platform_driver_register failed: %d\n", ret);
+	return ret;
+}
+
+static void __exit fimc_is_exit(void)
+{
+	platform_driver_unregister(&fimc_is_driver);
+}
+
+module_init(fimc_is_init);
+module_exit(fimc_is_exit);
+
+MODULE_AUTHOR("Younghwan Joo, <yhwan.joo@samsung.com>");
+MODULE_DESCRIPTION("Exynos4 series FIMC-IS slave driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-core.h b/drivers/media/video/exynos/fimc-is/fimc-is-core.h
new file mode 100644
index 0000000..1309e96
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-core.h
@@ -0,0 +1,473 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Driver internal Header
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CORE_H_
+#define FIMC_IS_CORE_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/workqueue.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+#include <media/exynos_fimc_is.h>
+#include <mach/dev.h>
+
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-cma-phys.h>
+#define MODULE_NAME	"exynos4-fimc-is"
+
+#define MAX_I2H_ARG 12
+#define NUM_FIMC_IS_CLOCKS 1
+
+#define FIMC_IS_MAX_BUF_NUM		8
+#define FIMC_IS_MAX_BUf_PLANE_NUM	3
+#define FIMC_IS_SENSOR_NUM	2
+
+/* Time - out definitions */
+#define FIMC_IS_SHUTDOWN_TIMEOUT	(3*HZ)
+#define FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR	(HZ)
+#define FIMC_IS_SHUTDOWN_TIMEOUT_AF	(3*HZ)
+/* Memory definitions */
+#define FIMC_IS_MEM_FW			"f"
+#define FIMC_IS_MEM_ISP_BUF		"i"
+
+#define FIMC_IS_A5_MEM_SIZE		0x00A00000
+#define FIMC_IS_REGION_SIZE		0x5000
+
+#define FIMC_IS_DEBUG_REGION_ADDR	0x00840000
+#define FIMC_IS_SHARED_REGION_ADDR	0x008C0000
+#define FIMC_IS_FW_INFO_LENGTH		32
+#define FIMC_IS_FW_VERSION_LENGTH	7
+#define FIMC_IS_SETFILE_INFO_LENGTH	39
+
+#define FIMC_IS_EXTRA_MEM_SIZE	(FIMC_IS_EXTRA_FW_SIZE +	\
+				 FIMC_IS_EXTRA_SETFILE_SIZE +	\
+				 0x1000)
+#define FIMC_IS_EXTRA_FW_SIZE		0x180000
+#define FIMC_IS_EXTRA_SETFILE_SIZE	0x4B000
+
+#define GED_FD_RANGE			1000
+
+#define BUS_LOCK_FREQ_L0	400200
+#define BUS_LOCK_FREQ_L1	267200
+#define BUS_LOCK_FREQ_L2	267160
+#define BUS_LOCK_FREQ_L3	160160
+#define BUS_LOCK_FREQ_L4	133133
+#define BUS_LOCK_FREQ_L5	100100
+
+/* A5 debug message setting */
+#define FIMC_IS_DEBUG_MSG	0x3F
+#define FIMC_IS_DEBUG_LEVEL	3
+
+#define SDCARD_FW
+
+#ifdef SDCARD_FW
+#define FIMC_IS_FW_SDCARD	"/sdcard/fimc_is_fw.bin"
+#define FIMC_IS_SETFILE_SDCARD	"/sdcard/setfile.bin"
+#endif
+#define FIMC_IS_FW		"fimc_is_fw.bin"
+#define FIMC_IS_SETFILE		"setfile.bin"
+
+#define FIMC_IS_MSG_FILE	"/sdcard/fimc_is_msg_dump.txt"
+
+#define err(fmt, args...) \
+	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+
+#ifdef DEBUG
+#define dbg(fmt, args...) \
+	printk(KERN_INFO "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define dbg(fmt, args...)
+#endif
+
+#define is_af_use(dev)		((dev->af.use_af) ? 1 : 0)
+
+/*
+Default setting values
+*/
+#define DEFAULT_PREVIEW_STILL_WIDTH	640
+#define DEFAULT_PREVIEW_STILL_HEIGHT	480
+#define DEFAULT_CAPTURE_STILL_WIDTH	640
+#define DEFAULT_CAPTURE_STILL_HEIGHT	480
+#define DEFAULT_PREVIEW_VIDEO_WIDTH	640
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT	480
+#define DEFAULT_CAPTURE_VIDEO_WIDTH	640
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT	480
+
+#define DEFAULT_PREVIEW_STILL_FRAMERATE	30
+#define DEFAULT_CAPTURE_STILL_FRAMERATE	15
+#define DEFAULT_PREVIEW_VIDEO_FRAMERATE	30
+#define DEFAULT_CAPTURE_VIDEO_FRAMERATE	30
+
+enum fimc_is_state_flag {
+	IS_ST_IDLE,
+	IS_ST_FW_LOADED,
+	IS_ST_A5_PWR_ON,
+	IS_ST_OPEN_SENSOR,
+	IS_ST_SETFILE_LOADED,
+	IS_ST_INIT_DONE,
+	IS_ST_STREAM_ON,
+	IS_ST_STREAM_OFF,
+	IS_ST_CHANGE_MODE,
+	IS_ST_BLOCK_CMD_CLEARED,
+	IS_ST_SET_ZOOM,
+	IS_ST_END
+};
+
+enum fimc_is_power {
+	IS_PWR_ST_POWEROFF,
+	IS_PWR_ST_POWERON,
+	IS_PWR_SUB_IP_POWER_OFF,
+	IS_PWR_END
+};
+
+enum fimc_is_clk {
+	FIMC_IS_CLK_BUS,
+	FIMC_IS_CLK_GATE,
+};
+
+enum sensor_list {
+	SENSOR_S5K3H2_CSI_A	= 1,
+	SENSOR_S5K6A3_CSI_A	= 2,
+	SENSOR_S5K4E5_CSI_A	= 3,
+	SENSOR_S5K3H7_CSI_A	= 4,
+	SENSOR_S5K3H2_CSI_B	= 101,
+	SENSOR_S5K6A3_CSI_B	= 102,
+	SENSOR_S5K4E5_CSI_B	= 103,
+	SENSOR_S5K3H7_CSI_B	= 104,
+	/* Custom mode */
+	SENSOR_S5K6A3_CSI_B_CUSTOM	= 200,
+};
+
+enum sensor_name {
+	SENSOR_NAME_S5K3H2	= 1,
+	SENSOR_NAME_S5K6A3	= 2,
+	SENSOR_NAME_S5K4E5	= 3,
+	SENSOR_NAME_S5K3H7	= 4,
+	SENSOR_NAME_CUSTOM	= 5,
+	SENSOR_NAME_END
+};
+
+enum sensor_channel {
+	SENSOR_CONTROL_I2C0	= 0,
+	SENSOR_CONTROL_I2C1	= 1
+};
+
+enum af_state {
+	FIMC_IS_AF_IDLE		= 0,
+	FIMC_IS_AF_SETCONFIG	= 1,
+	FIMC_IS_AF_RUNNING	= 2,
+	FIMC_IS_AF_LOCK		= 3,
+	FIMC_IS_AF_ABORT	= 4,
+	FIMC_IS_AF_FAILED	= 5,
+};
+
+enum af_lock_state {
+	FIMC_IS_AF_UNLOCKED	= 0,
+	FIMC_IS_AF_LOCKED	= 0x02
+};
+
+enum ae_lock_state {
+	FIMC_IS_AE_UNLOCKED	= 0,
+	FIMC_IS_AE_LOCKED	= 1
+};
+
+enum awb_lock_state {
+	FIMC_IS_AWB_UNLOCKED	= 0,
+	FIMC_IS_AWB_LOCKED	= 1
+};
+
+enum fimc_is_video_dev_num {
+	FIMC_IS_VIDEO_NUM_BAYER = 0,
+	FIMC_IS_VIDEO_MAX_NUM,
+};
+
+enum fimc_is_video_vb2_flag {
+	FIMC_IS_STATE_IDLE		= 0,
+	FIMC_IS_STATE_READY,
+	FIMC_IS_STATE_ISP_STREAM_ON,
+	FIMC_IS_STATE_ISP_STREAM_OFF,
+	FIMC_IS_STATE_ISP_BUFFER_PREPARED,
+};
+
+struct is_meminfo {
+	dma_addr_t	base;		/* buffer base */
+	size_t		size;		/* total length */
+	dma_addr_t	vaddr_base;		/* buffer base */
+	dma_addr_t	vaddr_curr;		/* current addr */
+
+	void		*bitproc_buf;
+	size_t		dvaddr;
+	unsigned char	*kvaddr;
+	struct vb2_buffer	vb2_buf;
+	dma_addr_t	fw_ref_base;
+	dma_addr_t	setfile_ref_base;
+};
+
+struct is_fw {
+	const struct firmware	*info;
+	int			state;
+	int			ver;
+	char			fw_info[FIMC_IS_FW_INFO_LENGTH];
+	char			setfile_info[FIMC_IS_SETFILE_INFO_LENGTH];
+	char			fw_version[FIMC_IS_FW_VERSION_LENGTH];
+	size_t			size;
+};
+
+struct is_setfile {
+	const struct firmware	*info;
+	int			state;
+	u32			sub_index;
+	u32			base;
+	size_t			size;
+};
+
+struct is_to_host_cmd {
+	u32	cmd;
+	u32	sensor_id;
+	u16	num_valid_args;
+	u32	arg[MAX_I2H_ARG];
+};
+
+struct host_to_is_cmd {
+	u16	cmd_type;
+	u32	entry_id;
+};
+
+struct is_sensor {
+	int id;
+	enum sensor_list sensor_type;
+	u32 width_prev;
+	u32 height_prev;
+	u32 width_prev_cam;
+	u32 height_prev_cam;
+	u32 width_cap;
+	u32 height_cap;
+	u32 width_cam;
+	u32 height_cam;
+	u32 offset_x;
+	u32 offset_y;
+	u32 zoom_out_width;
+	u32 zoom_out_height;
+	u32 frametime_max_prev;
+	u32 frametime_max_prev_cam;
+	u32 frametime_max_cap;
+	u32 frametime_max_cam;
+	int framerate_update;
+};
+
+struct is_fd_result_header {
+	u32 offset;
+	u32 count;
+	u32 index;
+	u32 target_addr;
+	s32 width;
+	s32 height;
+};
+
+struct is_af_info {
+	u16 mode;
+	u32 af_state;
+	u32 af_lock_state;
+	u32 ae_lock_state;
+	u32 awb_lock_state;
+	u16 pos_x;
+	u16 pos_y;
+	u16 prev_pos_x;
+	u16 prev_pos_y;
+	u16 use_af;
+};
+
+struct fimc_is_dev;
+
+struct fimc_is_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct fimc_is_dev *is_dev);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+};
+
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+struct fimc_is_fmt {
+	enum v4l2_mbus_pixelcode mbus_code;
+	char	*name;
+	u32	fourcc;
+	u16	flags;
+};
+
+struct fimc_is_video_dev {
+	struct video_device		vd;
+	struct vb2_queue		vbq;
+	struct fimc_is_dev		*dev;
+	struct v4l2_device		v4l2_dev;
+	unsigned int			num_buf;
+	unsigned int			num_plane;
+	unsigned int			buf_ref_cnt;
+	unsigned long			plane_size[FIMC_IS_MAX_BUf_PLANE_NUM];
+	dma_addr_t buf[FIMC_IS_MAX_BUF_NUM][FIMC_IS_MAX_BUf_PLANE_NUM];
+};
+#endif
+
+struct fimc_is_dev {
+	spinlock_t			slock;
+	struct mutex			lock;
+	unsigned long			state;
+	struct platform_device		*pdev;
+	struct exynos4_platform_fimc_is	*pdata;
+	u32				scenario_id;
+	u32				frame_count;
+
+	struct is_sensor		sensor;
+	u32				sensor_num;
+	struct is_af_info		af;
+
+	u16				num_clocks;
+	struct clk			*clock[NUM_FIMC_IS_CLOCKS];
+	void __iomem			*regs;
+	struct resource			*regs_res;
+
+	int				irq1;
+	wait_queue_head_t		irq_queue1;
+	struct is_to_host_cmd		i2h_cmd;
+	struct host_to_is_cmd		h2i_cmd;
+
+	unsigned long			power;
+
+	struct is_fw			fw;
+	struct is_setfile		setfile;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	struct is_meminfo		mem;		/* for reserved mem */
+	struct is_fd_result_header	fd_header;
+
+	struct v4l2_subdev		sd;
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+	struct fimc_is_video_dev	video[FIMC_IS_VIDEO_MAX_NUM];
+	const struct fimc_is_vb2	*vb2;
+	unsigned long			vb_state;
+#endif
+	struct device			*bus_dev;
+	int				low_power_mode;
+	/* Shared parameter region */
+	atomic_t			p_region_num;
+	unsigned long			p_region_index1;
+	unsigned long			p_region_index2;
+	struct is_region		*is_p_region;
+	struct is_share_region		*is_shared_region;
+};
+
+static inline void fimc_is_state_lock_set(u32 state, struct fimc_is_dev *dev)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->slock, flags);
+	dev->state |= state;
+	spin_unlock_irqrestore(&dev->slock, flags);
+}
+
+static inline bool fimc_is_state_is_set(u32 mask, struct fimc_is_dev *dev)
+{
+	unsigned long flags;
+	bool ret;
+
+	spin_lock_irqsave(&dev->slock, flags);
+	ret = (dev->state & mask) == mask;
+	spin_unlock_irqrestore(&dev->slock, flags);
+	return ret;
+}
+
+extern const struct v4l2_subdev_ops fimc_is_subdev_ops;
+extern struct is_region is_p_region;
+
+extern int fimc_is_fw_clear_irq2(struct fimc_is_dev *dev);
+extern int fimc_is_fw_clear_irq1(struct fimc_is_dev *dev,
+						unsigned int intr_pos);
+extern void fimc_is_hw_set_sensor_num(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_sensor_num(struct fimc_is_dev *dev);
+extern void fimc_is_hw_get_setfile_addr(struct fimc_is_dev *dev);
+extern void fimc_is_hw_load_setfile(struct fimc_is_dev *dev);
+extern int fimc_is_hw_set_param(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_param(struct fimc_is_dev *dev, u16 offset);
+extern void fimc_is_hw_set_intgr0_gd0(struct fimc_is_dev *dev);
+extern int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is_dev *dev);
+extern int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is_dev *dev);
+extern void fimc_is_hw_a5_power(struct fimc_is_dev *dev, int on);
+extern int fimc_is_hw_io_init(struct fimc_is_dev *dev);
+extern void fimc_is_hw_open_sensor(struct fimc_is_dev *dev,
+					u32 id, u32 sensor_index);
+extern void fimc_is_hw_close_sensor(struct fimc_is_dev *dev, u32 id);
+extern void fimc_is_hw_set_stream(struct fimc_is_dev *dev, int on);
+extern void fimc_is_hw_set_init(struct fimc_is_dev *dev);
+extern void fimc_is_hw_change_mode(struct fimc_is_dev *dev, int val);
+extern void fimc_is_hw_set_lite(struct fimc_is_dev *dev, u32 width, u32 height);
+extern void fimc_is_hw_subip_poweroff(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_sensor_max_framerate(struct fimc_is_dev *dev);
+extern void fimc_is_hw_set_debug_level(struct fimc_is_dev *dev, int level1,
+								int level2);
+extern int fimc_is_hw_set_tune(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_sensor_size_width(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_sensor_size_height(struct fimc_is_dev *dev);
+extern int fimc_is_hw_get_sensor_format(struct fimc_is_dev *dev);
+extern void fimc_is_hw_set_low_poweroff(struct fimc_is_dev *dev, int on);
+
+extern int fimc_is_af_face(struct fimc_is_dev *dev);
+
+extern int fimc_is_s_power(struct v4l2_subdev *sd, int on);
+
+extern void fimc_is_param_err_checker(struct fimc_is_dev *dev);
+extern void fimc_is_print_err_number(u32 num_err);
+
+extern int fimc_is_init_mem_mgr(struct fimc_is_dev *dev);
+extern void *fimc_is_mem_init(struct device *dev);
+extern int fimc_is_alloc_firmware(struct fimc_is_dev *dev);
+extern void fimc_is_mem_resume(void *alloc_ctxes);
+extern void fimc_is_mem_suspend(void *alloc_ctxes);
+extern void fimc_is_mem_init_mem_cleanup(void *alloc_ctxes);
+extern void fimc_is_mem_cache_clean(const void *start_addr, unsigned long size);
+extern void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size);
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct fimc_is_vb2 fimc_is_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct fimc_is_vb2 fimc_is_vb2_ion;
+#endif
+extern const struct vb2_ops fimc_is_isp_qops;
+extern const struct v4l2_file_operations fimc_is_isp_video_fops;
+extern const struct v4l2_ioctl_ops fimc_is_isp_video_ioctl_ops;
+struct fimc_is_dev *to_fimc_is_dev(struct v4l2_subdev *sdev);
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-err.c b/drivers/media/video/exynos/fimc-is/fimc-is-err.c
new file mode 100644
index 0000000..a6f0c8f
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-err.c
@@ -0,0 +1,471 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Error log interface functions
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-err.h"
+
+void fimc_is_print_param_err_name(u32 err)
+{
+	switch (err) {
+	/* Common error */
+	case ERROR_COMMON_CMD:
+		printk(KERN_ERR
+			"ERROR_COMMON_CMD : Invalid Command Error!!\n");
+		break;
+	case ERROR_COMMON_PARAMETER:
+		printk(KERN_ERR
+		"ERROR_COMMON_PARAMETER : Invalid Parameter Error!!\n");
+		break;
+	case ERROR_COMMON_SETFILE_LOAD:
+		printk(KERN_ERR
+		"ERROR_COMMON_SETFILE_LOAD : Illegal Setfile Loading!!\n");
+		break;
+	case ERROR_COMMON_SETFILE_ADJUST:
+		printk(KERN_ERR
+		"ERROR_COMMON_SETFILE_ADJUST : Setfile isn't adjusted!!\n");
+		break;
+	case ERROR_COMMON_SETFILE_INDEX:
+		printk(KERN_ERR
+		"ERROR_COMMON_SETFILE_INDEX : Index of setfile is not valid (0~MAX_SETFILE_NUM-1)!!\n");
+		break;
+	case ERROR_COMMON_INPUT_PATH:
+		printk(KERN_ERR
+		"ERROR_COMMON_INPUT_PATH : Input path can be changed in ready state!!\n");
+		break;
+	case ERROR_COMMON_INPUT_INIT:
+		printk(KERN_ERR
+		"ERROR_COMMON_INPUT_INIT : IP can not start if input path is not set!!\n");
+		break;
+	case ERROR_COMMON_OUTPUT_PATH:
+		printk(KERN_ERR
+		"ERROR_COMMON_OUTPUT_PATH : Output path can be changed in ready state (stop)!!\n");
+		break;
+	case ERROR_COMMON_OUTPUT_INIT:
+		printk(KERN_ERR
+		"ERROR_COMMON_OUTPUT_INIT : IP can not start if output path is not set!!\n");
+		break;
+	case ERROR_CONTROL_BYPASS:
+		printk(KERN_ERR "ERROR_CONTROL_BYPASS!!\n");
+		break;
+	case ERROR_OTF_INPUT_FORMAT:
+		printk(KERN_ERR
+		"ERROR_OTF_INPUT_FORMAT!! : invalid format  (DRC: YUV444, FD: YUV444, 422, 420)\n");
+		break;
+	case ERROR_OTF_INPUT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_OTF_INPUT_WIDTH!! : invalid width (DRC: 128~8192, FD: 32~8190)\n");
+		break;
+	case ERROR_OTF_INPUT_HEIGHT:
+		printk(KERN_ERR
+		"ERROR_OTF_INPUT_HEIGHT!! : invalid bit-width (DRC: 8~12bits, FD: 8bit)\n");
+		break;
+	case ERROR_OTF_INPUT_BIT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_OTF_INPUT_BIT_WIDTH!! : invalid bit-width (DRC: 8~12bits, FD: 8bit)\n");
+		break;
+	case ERROR_DMA_INPUT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_WIDTH!! : invalid width (DRC: 128~8192, FD: 32~8190)\n");
+		break;
+	case ERROR_DMA_INPUT_HEIGHT:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_HEIGHT!! : invalid height (DRC: 64~8192, FD: 16~8190)\n");
+		break;
+	case ERROR_DMA_INPUT_FORMAT:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_FORMAT!! : invalid format (DRC: YUV444 or YUV422, FD: YUV444,422,420)\n");
+		break;
+	case ERROR_DMA_INPUT_BIT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_BIT_WIDTH!! : invalid bit-width (DRC: 8~12bits, FD: 8bit)\n");
+		break;
+	case ERROR_DMA_INPUT_ORDER:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_ORDER!! : invalid order(DRC: YYCbCrorYCbYCr,FD:NO,YYCbCr,YCbYCr,CbCr,CrCb)\n");
+		break;
+	case ERROR_DMA_INPUT_PLANE:
+		printk(KERN_ERR
+		"ERROR_DMA_INPUT_PLANE!! : invalid palne (DRC: 3, FD: 1, 2, 3)\n");
+		break;
+	case ERROR_OTF_OUTPUT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_OTF_OUTPUT_WIDTH!! : invalid width (DRC: 128~8192)\n");
+		break;
+	case ERROR_OTF_OUTPUT_HEIGHT:
+		printk(KERN_ERR
+		"ERROR_OTF_OUTPUT_HEIGHT!! : invalid height (DRC: 64~8192)\n");
+		break;
+	case ERROR_OTF_OUTPUT_FORMAT:
+		printk(KERN_ERR
+		"ERROR_OTF_OUTPUT_FORMAT!! : invalid format (DRC: YUV444)\n");
+		break;
+	case ERROR_OTF_OUTPUT_BIT_WIDTH:
+		printk(KERN_ERR
+		"ERROR_OTF_OUTPUT_BIT_WIDTH!! : invalid bit-width (DRC: 8~12bits, FD: 8bit)\n");
+		break;
+	case ERROR_DMA_OUTPUT_WIDTH:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_WIDTH!!\n");
+		break;
+	case ERROR_DMA_OUTPUT_HEIGHT:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_HEIGHT!!\n");
+		break;
+	case ERROR_DMA_OUTPUT_FORMAT:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_FORMAT!!\n");
+		break;
+	case ERROR_DMA_OUTPUT_BIT_WIDTH:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_BIT_WIDTH!!\n");
+		break;
+	case ERROR_DMA_OUTPUT_PLANE:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_PLANE!!\n");
+		break;
+	case ERROR_DMA_OUTPUT_ORDER:
+		printk(KERN_ERR "ERROR_DMA_OUTPUT_ORDER!!\n");
+		break;
+	/* SENSOR Error(100~199) */
+	case ERROR_SENSOR_I2C_FAIL:
+		printk(KERN_ERR "ERROR_SENSOR_I2C_FAIL!!\n");
+		break;
+	case ERROR_SENSOR_INVALID_FRAMERATE:
+		printk(KERN_ERR "ERROR_SENSOR_INVALID_FRAMERATE!!\n");
+		break;
+	case ERROR_SENSOR_INVALID_EXPOSURETIME:
+		printk(KERN_ERR "ERROR_SENSOR_INVALID_EXPOSURETIME!!\n");
+		break;
+	case ERROR_SENSOR_INVALID_SIZE:
+		printk(KERN_ERR "ERROR_SENSOR_INVALID_SIZE!!\n");
+		break;
+	case ERROR_SENSOR_INVALID_SETTING:
+		printk(KERN_ERR "ERROR_SENSOR_INVALID_SETTING!!\n");
+		break;
+	case ERROR_SENSOR_ACTURATOR_INIT_FAIL:
+		printk(KERN_ERR "ERROR_SENSOR_ACTURATOR_INIT_FAIL!!\n");
+		break;
+	case ERROR_SENSOR_INVALID_AF_POS:
+		printk(KERN_ERR "ERROR_SENSOR_INVALID_AF_POS!!\n");
+		break;
+	case ERROR_SENSOR_UNSUPPORT_FUNC:
+		printk(KERN_ERR "ERROR_SENSOR_UNSUPPORT_FUNC!!\n");
+		break;
+	case ERROR_SENSOR_UNSUPPORT_PERI:
+		printk(KERN_ERR "ERROR_SENSOR_UNSUPPORT_PERI!!\n");
+		break;
+	case ERROR_SENSOR_UNSUPPORT_AF:
+		printk(KERN_ERR "ERROR_SENSOR_UNSUPPORT_AF!!\n");
+		break;
+	/* ISP Error (200~299) */
+	case ERROR_ISP_AF_BUSY:
+		printk(KERN_ERR "ERROR_ISP_AF_BUSY!!\n");
+		break;
+	case ERROR_ISP_AF_INVALID_COMMAND:
+		printk(KERN_ERR "ERROR_ISP_AF_INVALID_COMMAND!!\n");
+		break;
+	case ERROR_ISP_AF_INVALID_MODE:
+		printk(KERN_ERR "ERROR_ISP_AF_INVALID_MODE!!\n");
+		break;
+	/* DRC Error (300~399) */
+	/* FD Error  (400~499) */
+	case ERROR_FD_CONFIG_MAX_NUMBER_STATE:
+		printk(KERN_ERR "ERROR_FD_CONFIG_MAX_NUMBER_STATE!!\n");
+		break;
+	case ERROR_FD_CONFIG_MAX_NUMBER_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_MAX_NUMBER_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_YAW_ANGLE_STATE:
+		printk(KERN_ERR "ERROR_FD_CONFIG_YAW_ANGLE_STATE!!\n");
+		break;
+	case ERROR_FD_CONFIG_YAW_ANGLE_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_YAW_ANGLE_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_ROLL_ANGLE_STATE:
+		printk(KERN_ERR "ERROR_FD_CONFIG_ROLL_ANGLE_STATE!!\n");
+		break;
+	case ERROR_FD_CONFIG_ROLL_ANGLE_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_ROLL_ANGLE_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_SMILE_MODE_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_SMILE_MODE_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_BLINK_MODE_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_BLINK_MODE_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_EYES_DETECT_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_EYES_DETECT_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_MOUTH_DETECT_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_MOUTH_DETECT_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_ORIENTATION_STATE:
+		printk(KERN_ERR "ERROR_FD_CONFIG_ORIENTATION_STATE!!\n");
+		break;
+	case ERROR_FD_CONFIG_ORIENTATION_INVALID:
+		printk(KERN_ERR "ERROR_FD_CONFIG_ORIENTATION_INVALID!!\n");
+		break;
+	case ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID:
+		printk(KERN_ERR
+			"ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID!!\n");
+		break;
+	case ERROR_FD_RESULT:
+		printk(KERN_ERR "ERROR_FD_RESULT!!\n");
+		break;
+	case ERROR_FD_MODE:
+		printk(KERN_ERR "ERROR_FD_MODE!!\n");
+		break;
+	default:
+		break;
+	}
+}
+
+void fimc_is_param_err_checker(struct fimc_is_dev *dev)
+{
+	/* Golbal */
+	if (dev->is_p_region->parameter.global.shotmode.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.global.shotmode.err);
+	/* Sensor */
+	if (dev->is_p_region->parameter.sensor.control.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.sensor.control.err);
+	if (dev->is_p_region->parameter.sensor.frame_rate.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.sensor.frame_rate.err);
+	if (dev->is_p_region->parameter.sensor.otf_output.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.sensor.otf_output.err);
+	/* ISP */
+	if (dev->is_p_region->parameter.isp.control.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.control.err);
+	if (dev->is_p_region->parameter.isp.otf_input.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.otf_input.err);
+	if (dev->is_p_region->parameter.isp.dma1_input.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.dma1_input.err);
+	if (dev->is_p_region->parameter.isp.dma2_input.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.dma2_input.err);
+	if (dev->is_p_region->parameter.isp.aa.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.aa.err);
+	if (dev->is_p_region->parameter.isp.flash.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.flash.err);
+	if (dev->is_p_region->parameter.isp.awb.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.awb.err);
+	if (dev->is_p_region->parameter.isp.effect.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.effect.err);
+	if (dev->is_p_region->parameter.isp.iso.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.iso.err);
+	if (dev->is_p_region->parameter.isp.adjust.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.adjust.err);
+	if (dev->is_p_region->parameter.isp.metering.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.metering.err);
+	if (dev->is_p_region->parameter.isp.afc.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.isp.afc.err);
+	/* FD */
+	if (dev->is_p_region->parameter.fd.control.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.fd.control.err);
+	if (dev->is_p_region->parameter.fd.otf_input.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.fd.otf_input.err);
+	if (dev->is_p_region->parameter.fd.config.err)
+		fimc_is_print_param_err_name(
+			dev->is_p_region->parameter.fd.config.err);
+}
+
+void fimc_is_print_err_number(u32 num_err)
+{
+	if ((num_err & IS_ERROR_TIME_OUT_FLAG)) {
+		printk(KERN_ERR "IS_ERROR_TIME_OUT !!\n");
+		num_err -= IS_ERROR_TIME_OUT_FLAG;
+	}
+
+	switch (num_err) {
+	/* General */
+	case IS_ERROR_INVALID_COMMAND:
+		printk(KERN_ERR "IS_ERROR_INVALID_COMMAND !!\n");
+		break;
+	case IS_ERROR_REQUEST_FAIL:
+		printk(KERN_ERR "IS_ERROR_REQUEST_FAIL !!\n");
+		break;
+	case IS_ERROR_INVALID_SCENARIO:
+		printk(KERN_ERR "IS_ERROR_INVALID_SCENARIO !!\n");
+		break;
+	case IS_ERROR_INVALID_SENSORID:
+		printk(KERN_ERR "IS_ERROR_INVALID_SENSORID !!\n");
+		break;
+	case IS_ERROR_INVALID_MODE_CHANGE:
+		printk(KERN_ERR "IS_ERROR_INVALID_MODE_CHANGE !!\n");
+		break;
+	case IS_ERROR_INVALID_MAGIC_NUMBER:
+		printk(KERN_ERR "IS_ERROR_INVALID_MAGIC_NUMBER !!\n");
+		break;
+	case IS_ERROR_INVALID_SETFILE_HDR:
+		printk(KERN_ERR "IS_ERROR_INVALID_SETFILE_HDR !!\n");
+		break;
+	case IS_ERROR_BUSY:
+		printk(KERN_ERR "IS_ERROR_BUSY !!\n");
+		break;
+	case IS_ERROR_SET_PARAMETER:
+		printk(KERN_ERR "IS_ERROR_SET_PARAMETER !!\n");
+		break;
+	case IS_ERROR_INVALID_PATH:
+		printk(KERN_ERR "IS_ERROR_INVALID_PATH !!\n");
+		break;
+	case IS_ERROR_OPEN_SENSOR_FAIL:
+		printk(KERN_ERR "IS_ERROR_OPEN_SENSOR_FAIL !!\n");
+		break;
+	case IS_ERROR_ENTRY_MSG_THREAD_DOWN:
+		printk(KERN_ERR "IS_ERROR_ENTRY_MSG_THREAD_DOWN !!\n");
+		break;
+	case IS_ERROR_ISP_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_ISP_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_DRC_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_DRC_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_SCALERC_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_SCALERC_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_ODC_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_ODC_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_DIS_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_DIS_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_TDNR_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_TDNR_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_SCALERP_FRAME_END_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_SCALERP_FRAME_END_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_WAIT_STREAM_OFF_NOT_DONE:
+		printk(KERN_ERR "IS_ERROR_WAIT_STREAM_OFF_NOT_DONE !!\n");
+		break;
+	case IS_ERROR_NO_MSG_IS_RECEIVED:
+		printk(KERN_ERR "IS_ERROR_NO_MSG_IS_RECEIVED !!\n");
+		break;
+	case IS_ERROR_SENSOR_MSG_FAIL:
+		printk(KERN_ERR "IS_ERROR_SENSOR_MSG_FAIL !!\n");
+		break;
+	case IS_ERROR_ISP_MSG_FAIL:
+		printk(KERN_ERR "IS_ERROR_ISP_MSG_FAIL !!\n");
+		break;
+	case IS_ERROR_DRC_MSG_FAIL:
+		printk(KERN_ERR "IS_ERROR_DRC_MSG_FAIL !!\n");
+		break;
+	case IS_ERROR_LHFD_MSG_FAIL:
+		printk(KERN_ERR "IS_ERROR_LHFD_MSG_FAIL !!\n");
+		break;
+	case IS_ERROR_UNKNOWN:
+		printk(KERN_ERR "IS_ERROR_UNKNOWN !!\n");
+		break;
+	/* Sensor */
+	case IS_ERROR_SENSOR_PWRDN_FAIL:
+		printk(KERN_ERR "IS_ERROR_SENSOR_PWRDN_FAIL !!\n");
+		break;
+	/* ISP */
+	case IS_ERROR_ISP_PWRDN_FAIL:
+		printk(KERN_ERR "IS_ERROR_ISP_PWRDN_FAIL !!\n");
+		break;
+	case IS_ERROR_ISP_MULTIPLE_INPUT:
+		printk(KERN_ERR "IS_ERROR_ISP_MULTIPLE_INPUT !!\n");
+		break;
+	case IS_ERROR_ISP_ABSENT_INPUT:
+		printk(KERN_ERR "IS_ERROR_ISP_ABSENT_INPUT !!\n");
+		break;
+	case IS_ERROR_ISP_ABSENT_OUTPUT:
+		printk(KERN_ERR "IS_ERROR_ISP_ABSENT_OUTPUT !!\n");
+		break;
+	case IS_ERROR_ISP_NONADJACENT_OUTPUT:
+		printk(KERN_ERR "IS_ERROR_ISP_NONADJACENT_OUTPUT !!\n");
+		break;
+	case IS_ERROR_ISP_FORMAT_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_ISP_FORMAT_MISMATCH !!\n");
+		break;
+	case IS_ERROR_ISP_WIDTH_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_ISP_WIDTH_MISMATCH !!\n");
+		break;
+	case IS_ERROR_ISP_HEIGHT_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_ISP_HEIGHT_MISMATCH !!\n");
+		break;
+	case IS_ERROR_ISP_BITWIDTH_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_ISP_BITWIDTH_MISMATCH !!\n");
+		break;
+	case IS_ERROR_ISP_FRAME_END_TIME_OUT:
+		printk(KERN_ERR "IS_ERROR_ISP_FRAME_END_TIME_OUT !!\n");
+		break;
+	/* DRC */
+	case IS_ERROR_DRC_PWRDN_FAIL:
+		printk(KERN_ERR "IS_ERROR_DRC_PWRDN_FAIL !!\n");
+		break;
+	case IS_ERROR_DRC_MULTIPLE_INPUT:
+		printk(KERN_ERR "IS_ERROR_DRC_MULTIPLE_INPUT !!\n");
+		break;
+	case IS_ERROR_DRC_ABSENT_INPUT:
+		printk(KERN_ERR "IS_ERROR_DRC_ABSENT_INPUT !!\n");
+		break;
+	case IS_ERROR_DRC_NONADJACENT_INPUT:
+		printk(KERN_ERR "IS_ERROR_DRC_NONADJACENT_INPUT !!\n");
+		break;
+	case IS_ERROR_DRC_ABSENT_OUTPUT:
+		printk(KERN_ERR "IS_ERROR_DRC_ABSENT_OUTPUT !!\n");
+		break;
+	case IS_ERROR_DRC_NONADJACENT_OUTPUT:
+		printk(KERN_ERR "IS_ERROR_DRC_NONADJACENT_OUTPUT !!\n");
+		break;
+	case IS_ERROR_DRC_FORMAT_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_DRC_FORMAT_MISMATCH !!\n");
+		break;
+	case IS_ERROR_DRC_WIDTH_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_DRC_WIDTH_MISMATCH !!\n");
+		break;
+	case IS_ERROR_DRC_HEIGHT_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_DRC_HEIGHT_MISMATCH !!\n");
+		break;
+	case IS_ERROR_DRC_BITWIDTH_MISMATCH:
+		printk(KERN_ERR "IS_ERROR_DRC_BITWIDTH_MISMATCH !!\n");
+		break;
+	case IS_ERROR_DRC_FRAME_END_TIME_OUT:
+		printk(KERN_ERR "IS_ERROR_DRC_FRAME_END_TIME_OUT !!\n");
+		break;
+	/* FD */
+	case IS_ERROR_FD_PWRDN_FAIL:
+		printk(KERN_ERR "IS_ERROR_FD_PWRDN_FAIL !!\n");
+		break;
+	case IS_ERROR_FD_MULTIPLE_INPUT:
+		printk(KERN_ERR "IS_ERROR_FD_MULTIPLE_INPUT !!\n");
+		break;
+	case IS_ERROR_FD_ABSENT_INPUT:
+		printk(KERN_ERR "IS_ERROR_FD_ABSENT_INPUT !!\n");
+		break;
+	case IS_ERROR_FD_NONADJACENT_INPUT:
+		printk(KERN_ERR "IS_ERROR_FD_NONADJACENT_INPUT !!\n");
+		break;
+	case IS_ERROR_LHFD_FRAME_END_TIME_OUT:
+		printk(KERN_ERR "IS_ERROR_LHFD_FRAME_END_TIME_OUT !!\n");
+		break;
+	}
+}
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-err.h b/drivers/media/video/exynos/fimc-is/fimc-is-err.h
new file mode 100644
index 0000000..b799dff
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-err.h
@@ -0,0 +1,249 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Error number description
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef FIMC_IS_ERR_H_
+#define FIMC_IS_ERR_H_
+
+#define IS_ERROR_VER 011 /* IS ERROR VERSION 0.11 */
+
+#define IS_ERROR_SUCCESS		0
+/* General 1 ~ 100 */
+#define IS_ERROR_INVALID_COMMAND	(IS_ERROR_SUCCESS + 1)
+#define IS_ERROR_REQUEST_FAIL		(IS_ERROR_INVALID_COMMAND + 1)
+#define IS_ERROR_INVALID_SCENARIO	(IS_ERROR_REQUEST_FAIL + 1)
+#define IS_ERROR_INVALID_SENSORID	(IS_ERROR_INVALID_SCENARIO+1)
+#define IS_ERROR_INVALID_MODE_CHANGE    (IS_ERROR_INVALID_SENSORID+1)
+#define IS_ERROR_INVALID_MAGIC_NUMBER	(IS_ERROR_INVALID_MODE_CHANGE+1)
+#define IS_ERROR_INVALID_SETFILE_HDR	(IS_ERROR_INVALID_MAGIC_NUMBER+1)
+#define IS_ERROR_BUSY			(IS_ERROR_INVALID_SETFILE_HDR + 1)
+#define IS_ERROR_SET_PARAMETER		(IS_ERROR_BUSY + 1)
+#define IS_ERROR_INVALID_PATH		(IS_ERROR_SET_PARAMETER + 1)
+#define IS_ERROR_OPEN_SENSOR_FAIL	(IS_ERROR_INVALID_PATH + 1)
+#define IS_ERROR_ENTRY_MSG_THREAD_DOWN		\
+					(IS_ERROR_OPEN_SENSOR_FAIL + 1)
+#define IS_ERROR_ISP_FRAME_END_NOT_DONE		\
+					(IS_ERROR_ENTRY_MSG_THREAD_DOWN + 1)
+#define IS_ERROR_DRC_FRAME_END_NOT_DONE		\
+					(IS_ERROR_ISP_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_SCALERC_FRAME_END_NOT_DONE	\
+					(IS_ERROR_DRC_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_ODC_FRAME_END_NOT_DONE		\
+				(IS_ERROR_SCALERC_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_DIS_FRAME_END_NOT_DONE		\
+				(IS_ERROR_ODC_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_TDNR_FRAME_END_NOT_DONE	\
+				(IS_ERROR_DIS_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_SCALERP_FRAME_END_NOT_DONE	\
+				(IS_ERROR_TDNR_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_WAIT_STREAM_OFF_NOT_DONE	\
+				(IS_ERROR_SCALERP_FRAME_END_NOT_DONE + 1)
+#define IS_ERROR_NO_MSG_IS_RECEIVED	(IS_ERROR_WAIT_STREAM_OFF_NOT_DONE + 1)
+#define IS_ERROR_SENSOR_MSG_FAIL	(IS_ERROR_NO_MSG_IS_RECEIVED + 1)
+#define IS_ERROR_ISP_MSG_FAIL		(IS_ERROR_SENSOR_MSG_FAIL + 1)
+#define IS_ERROR_DRC_MSG_FAIL		(IS_ERROR_ISP_MSG_FAIL + 1)
+#define IS_ERROR_SCALERC_MSG_FAIL	(IS_ERROR_DRC_MSG_FAIL + 1)
+#define IS_ERROR_ODC_MSG_FAIL		(IS_ERROR_SCALERC_MSG_FAIL + 1)
+#define IS_ERROR_DIS_MSG_FAIL		(IS_ERROR_ODC_MSG_FAIL + 1)
+#define IS_ERROR_TDNR_MSG_FAIL		(IS_ERROR_DIS_MSG_FAIL + 1)
+#define IS_ERROR_SCALERP_MSG_FAIL	(IS_ERROR_TDNR_MSG_FAIL + 1)
+#define IS_ERROR_LHFD_MSG_FAIL		(IS_ERROR_DRC_MSG_FAIL + 1)
+#define IS_ERROR_LHFD_INTERNAL_STOP	(IS_ERROR_LHFD_MSG_FAIL + 1)
+#define IS_ERROR_UNKNOWN		1000
+#define IS_ERROR_TIME_OUT_FLAG		0x80000000
+
+/* Sensor 100 ~ 200 */
+#define IS_ERROR_SENSOR_PWRDN_FAIL	100
+#define IS_ERROR_SENSOR_STREAM_ON_FAIL	(IS_ERROR_SENSOR_PWRDN_FAIL + 1)
+#define IS_ERROR_SENSOR_STREAM_OFF_FAIL	(IS_ERROR_SENSOR_STREAM_ON_FAIL + 1)
+
+/* ISP 200 ~ 300 */
+#define IS_ERROR_ISP_PWRDN_FAIL		200
+#define IS_ERROR_ISP_MULTIPLE_INPUT	(IS_ERROR_ISP_PWRDN_FAIL+1)
+#define IS_ERROR_ISP_ABSENT_INPUT	(IS_ERROR_ISP_MULTIPLE_INPUT+1)
+#define IS_ERROR_ISP_ABSENT_OUTPUT	(IS_ERROR_ISP_ABSENT_INPUT+1)
+#define IS_ERROR_ISP_NONADJACENT_OUTPUT	(IS_ERROR_ISP_ABSENT_OUTPUT+1)
+#define IS_ERROR_ISP_FORMAT_MISMATCH	(IS_ERROR_ISP_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_ISP_WIDTH_MISMATCH	(IS_ERROR_ISP_FORMAT_MISMATCH+1)
+#define IS_ERROR_ISP_HEIGHT_MISMATCH	(IS_ERROR_ISP_WIDTH_MISMATCH+1)
+#define IS_ERROR_ISP_BITWIDTH_MISMATCH	(IS_ERROR_ISP_HEIGHT_MISMATCH+1)
+#define IS_ERROR_ISP_FRAME_END_TIME_OUT	(IS_ERROR_ISP_BITWIDTH_MISMATCH+1)
+
+/* DRC 300 ~ 400 */
+#define IS_ERROR_DRC_PWRDN_FAIL		300
+#define IS_ERROR_DRC_MULTIPLE_INPUT	(IS_ERROR_DRC_PWRDN_FAIL+1)
+#define IS_ERROR_DRC_ABSENT_INPUT	(IS_ERROR_DRC_MULTIPLE_INPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_INPUT	(IS_ERROR_DRC_ABSENT_INPUT+1)
+#define IS_ERROR_DRC_ABSENT_OUTPUT	(IS_ERROR_DRC_NONADJACENT_INPUT+1)
+#define IS_ERROR_DRC_NONADJACENT_OUTPUT	(IS_ERROR_DRC_ABSENT_OUTPUT+1)
+#define IS_ERROR_DRC_FORMAT_MISMATCH	(IS_ERROR_DRC_NONADJACENT_OUTPUT+1)
+#define IS_ERROR_DRC_WIDTH_MISMATCH	(IS_ERROR_DRC_FORMAT_MISMATCH+1)
+#define IS_ERROR_DRC_HEIGHT_MISMATCH	(IS_ERROR_DRC_WIDTH_MISMATCH+1)
+#define IS_ERROR_DRC_BITWIDTH_MISMATCH	(IS_ERROR_DRC_HEIGHT_MISMATCH+1)
+#define IS_ERROR_DRC_FRAME_END_TIME_OUT	(IS_ERROR_DRC_BITWIDTH_MISMATCH+1)
+
+/* SCALERC 400 ~ 500 */
+#define IS_ERROR_SCALERC_PWRDN_FAIL	400
+
+/* ODC 500 ~ 600 */
+#define IS_ERROR_ODC_PWRDN_FAIL		500
+
+/* DIS 600 ~ 700 */
+#define IS_ERROR_DIS_PWRDN_FAIL		600
+
+/* TDNR 700 ~ 800 */
+#define IS_ERROR_TDNR_PWRDN_FAIL	700
+
+/* SCALERC 800 ~ 900 */
+#define IS_ERROR_SCALERP_PWRDN_FAIL	800
+
+/* FD 900 ~ 1000 */
+#define IS_ERROR_FD_PWRDN_FAIL		900
+#define IS_ERROR_FD_MULTIPLE_INPUT	(IS_ERROR_FD_PWRDN_FAIL+1)
+#define IS_ERROR_FD_ABSENT_INPUT	(IS_ERROR_FD_MULTIPLE_INPUT+1)
+#define IS_ERROR_FD_NONADJACENT_INPUT	(IS_ERROR_FD_ABSENT_INPUT+1)
+#define IS_ERROR_LHFD_FRAME_END_TIME_OUT \
+					(IS_ERROR_FD_NONADJACENT_INPUT+1)
+
+/* Set parameter error enum */
+enum error {
+	/* Common error (0~99) */
+	ERROR_COMMON_NO			= 0,
+	ERROR_COMMON_CMD		= 1,	/* Invalid command*/
+	ERROR_COMMON_PARAMETER		= 2,	/* Invalid parameter*/
+	/* setfile is not loaded before adjusting */
+	ERROR_COMMON_SETFILE_LOAD	= 3,
+	/* setfile is not Adjusted before runnng. */
+	ERROR_COMMON_SETFILE_ADJUST	= 4,
+	/* Index of setfile is not valid (0~MAX_SETFILE_NUM-1) */
+	ERROR_COMMON_SETFILE_INDEX	= 5,
+	/* Input path can be changed in ready state(stop) */
+	ERROR_COMMON_INPUT_PATH		= 6,
+	/* IP can not start if input path is not set */
+	ERROR_COMMON_INPUT_INIT		= 7,
+	/* Output path can be changed in ready state (stop) */
+	ERROR_COMMON_OUTPUT_PATH	= 8,
+	/* IP can not start if output path is not set */
+	ERROR_COMMON_OUTPUT_INIT	= 9,
+
+	ERROR_CONTROL_NO		= ERROR_COMMON_NO,
+	ERROR_CONTROL_BYPASS		= 11,	/* Enable or Disable */
+
+	ERROR_OTF_INPUT_NO		= ERROR_COMMON_NO,
+	ERROR_OTF_INPUT_CMD		= 21,
+	/* invalid format  (DRC: YUV444, FD: YUV444, 422, 420) */
+	ERROR_OTF_INPUT_FORMAT		= 22,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_OTF_INPUT_WIDTH		= 23,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_OTF_INPUT_HEIGHT		= 24,
+	/* invalid bit-width (DRC: 8~12bits, FD: 8bit) */
+	ERROR_OTF_INPUT_BIT_WIDTH	= 25,
+	/* invalid FrameTime for ISP */
+	ERROR_OTF_INPUT_USER_FRAMETIIME	= 26,
+
+	ERROR_DMA_INPUT_NO		= ERROR_COMMON_NO,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_DMA_INPUT_WIDTH		= 31,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_DMA_INPUT_HEIGHT		= 32,
+	/* invalid format (DRC: YUV444 or YUV422, FD: YUV444, 422, 420) */
+	ERROR_DMA_INPUT_FORMAT		= 33,
+	/* invalid bit-width (DRC: 8~12bit, FD: 8bit) */
+	ERROR_DMA_INPUT_BIT_WIDTH	= 34,
+	/* invalid order(DRC: YYCbCrorYCbYCr, FD:NO,YYCbCr,YCbYCr,CbCr,CrCb) */
+	ERROR_DMA_INPUT_ORDER		= 35,
+	/* invalid palne (DRC: 3, FD: 1, 2, 3) */
+	ERROR_DMA_INPUT_PLANE		= 36,
+
+	ERROR_OTF_OUTPUT_NO		= ERROR_COMMON_NO,
+	/* invalid width (DRC: 128~8192) */
+	ERROR_OTF_OUTPUT_WIDTH		= 41,
+	/* invalid height (DRC: 64~8192) */
+	ERROR_OTF_OUTPUT_HEIGHT		= 42,
+	/* invalid format (DRC: YUV444) */
+	ERROR_OTF_OUTPUT_FORMAT		= 43,
+	/* invalid bit-width (DRC: 8~12bits) */
+	ERROR_OTF_OUTPUT_BIT_WIDTH	= 44,
+
+	ERROR_DMA_OUTPUT_NO		= ERROR_COMMON_NO,
+	ERROR_DMA_OUTPUT_WIDTH		= 51,	/* invalid width */
+	ERROR_DMA_OUTPUT_HEIGHT		= 52,	/* invalid height */
+	ERROR_DMA_OUTPUT_FORMAT		= 53,	/* invalid format */
+	ERROR_DMA_OUTPUT_BIT_WIDTH	= 54,	/* invalid bit-width */
+	ERROR_DMA_OUTPUT_PLANE		= 55,	/* invalid plane */
+	ERROR_DMA_OUTPUT_ORDER		= 56,	/* invalid order */
+
+	ERROR_GLOBAL_SHOTMODE_NO	= ERROR_COMMON_NO,
+
+	/* SENSOR Error(100~199) */
+	ERROR_SENSOR_NO			= ERROR_COMMON_NO,
+	ERROR_SENSOR_I2C_FAIL		= 101,
+	ERROR_SENSOR_INVALID_FRAMERATE,
+	ERROR_SENSOR_INVALID_EXPOSURETIME,
+	ERROR_SENSOR_INVALID_SIZE,
+	ERROR_SENSOR_INVALID_SETTING,
+	ERROR_SENSOR_ACTURATOR_INIT_FAIL,
+	ERROR_SENSOR_INVALID_AF_POS,
+	ERROR_SENSOR_UNSUPPORT_FUNC,
+	ERROR_SENSOR_UNSUPPORT_PERI,
+	ERROR_SENSOR_UNSUPPORT_AF,
+
+	/* ISP Error (200~299) */
+	ERROR_ISP_AF_NO			= ERROR_COMMON_NO,
+	ERROR_ISP_AF_BUSY		= 201,
+	ERROR_ISP_AF_INVALID_COMMAND	= 202,
+	ERROR_ISP_AF_INVALID_MODE	= 203,
+	ERROR_ISP_FLASH_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_AWB_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_IMAGE_EFFECT_NO	= ERROR_COMMON_NO,
+	ERROR_ISP_ISO_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_ADJUST_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_METERING_NO		= ERROR_COMMON_NO,
+	ERROR_ISP_AFC_NO		= ERROR_COMMON_NO,
+
+	/* DRC Error (300~399) */
+
+	/* FD Error  (400~499) */
+	ERROR_FD_NO					= ERROR_COMMON_NO,
+	/* Invalid max number (1~16) */
+	ERROR_FD_CONFIG_MAX_NUMBER_STATE		= 401,
+	ERROR_FD_CONFIG_MAX_NUMBER_INVALID		= 402,
+	ERROR_FD_CONFIG_YAW_ANGLE_STATE			= 403,
+	ERROR_FD_CONFIG_YAW_ANGLE_INVALID		= 404,
+	ERROR_FD_CONFIG_ROLL_ANGLE_STATE		= 405,
+	ERROR_FD_CONFIG_ROLL_ANGLE_INVALID		= 406,
+	ERROR_FD_CONFIG_SMILE_MODE_INVALID		= 407,
+	ERROR_FD_CONFIG_BLINK_MODE_INVALID		= 408,
+	ERROR_FD_CONFIG_EYES_DETECT_INVALID		= 409,
+	ERROR_FD_CONFIG_MOUTH_DETECT_INVALID		= 410,
+	ERROR_FD_CONFIG_ORIENTATION_STATE		= 411,
+	ERROR_FD_CONFIG_ORIENTATION_INVALID		= 412,
+	ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID	= 413,
+	ERROR_FD_RESULT			= 414,	/* PARAM_FdResultStr can
+						be only applied in ready-state
+						or stream off */
+	ERROR_FD_MODE			= 415,	/* PARAM_FdModeStr can be only
+						applied in ready-state or
+						stream off */
+	/* Scaler Error  (500 ~ 599) */
+	ERROR_SCALER_NO					= ERROR_COMMON_NO,
+	ERROR_SCALER_DMA_OUTSEL				= 501,
+	ERROR_SCALER_H_RATIO				= 502,
+	ERROR_SCALER_V_RATIO				= 503,
+
+	ERROR_SCALER_IMAGE_EFFECT			= 510,
+
+	ERROR_SCALER_ROTATE				= 520,
+	ERROR_SCALER_FLIP				= 521,
+};
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-helper.c b/drivers/media/video/exynos/fimc-is/fimc-is-helper.c
new file mode 100644
index 0000000..ef0d163
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-helper.c
@@ -0,0 +1,2940 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * exynos4 fimc-is helper functions
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <plat/gpio-cfg.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-param.h"
+#include "fimc-is-err.h"
+
+static const struct sensor_param init_val_sensor_preview_still = {
+	.frame_rate = {
+		.frame_rate = DEFAULT_PREVIEW_STILL_FRAMERATE,
+	},
+};
+
+static const struct isp_param init_val_isp_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+#ifndef ISP_STRGEN
+		.format = OTF_INPUT_FORMAT_BAYER,
+#else
+		.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER,
+#endif
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 66666,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = 0,
+		.scene = 0,
+		.sleep = 0,
+		.face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NO,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NO,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NO,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NO,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NO,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NO,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.win_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.err = ISP_METERING_ERROR_NO,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma1_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV422,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_INPUT_ORDER_NO,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_BAYER,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_10BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_GB_BG,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct drc_param init_val_drc_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct fd_param init_val_fd_preview_still = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = 5,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NO,
+	},
+};
+
+static const struct sensor_param init_val_sensor_capture = {
+	.frame_rate = {
+		.frame_rate = DEFAULT_CAPTURE_STILL_FRAMERATE,
+	},
+};
+
+static const struct isp_param init_val_isp_capture = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+#ifndef ISP_STRGEN
+		.format = OTF_INPUT_FORMAT_BAYER,
+#else
+		.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER,
+#endif
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 66666,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = 0,
+		.scene = 0,
+		.sleep = 0,
+		.face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NO,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NO,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NO,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NO,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NO,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NO,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.err = ISP_METERING_ERROR_NO,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma1_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct drc_param init_val_drc_capture = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct fd_param init_val_fd_capture = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		/* in FD case , bypass is not available */
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = 5,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NO,
+	},
+};
+
+static const struct sensor_param init_val_sensor_preview_video = {
+	.frame_rate = {
+		.frame_rate = DEFAULT_PREVIEW_VIDEO_FRAMERATE,
+	},
+};
+
+static const struct isp_param init_val_isp_preview_video = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+#ifndef ISP_STRGEN
+		.format = OTF_INPUT_FORMAT_BAYER,
+#else
+		.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER,
+#endif
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 33333,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = 0,
+		.scene = 0,
+		.sleep = 0,
+		.face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NO,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NO,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NO,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NO,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NO,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NO,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.win_height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.err = ISP_METERING_ERROR_NO,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma1_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV422,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_INPUT_ORDER_NO,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_BAYER,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_10BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_GB_BG,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct drc_param init_val_drc_preview_video = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct fd_param init_val_fd_preview_video = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_VIDEO_WIDTH,
+		.height = DEFAULT_PREVIEW_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = 5,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NO,
+	},
+};
+
+
+static const struct sensor_param init_val_sensor_camcording = {
+	.frame_rate = {
+		.frame_rate = DEFAULT_CAPTURE_VIDEO_FRAMERATE,
+	},
+};
+
+static const struct isp_param init_val_isp_camcording = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+#ifndef ISP_STRGEN
+		.format = OTF_INPUT_FORMAT_BAYER,
+#else
+		.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER,
+#endif
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 33333,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = 0,
+		.scene = 0,
+		.sleep = 0,
+		.face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NO,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NO,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NO,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NO,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NO,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NO,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.win_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.err = ISP_METERING_ERROR_NO,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NO,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+	.dma1_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV422,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_INPUT_ORDER_NO,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_BAYER,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_10BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_GB_BG,
+		.buffer_number = 1,
+		.buffer_address = 0x501D0000,
+		.err = DMA_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct drc_param init_val_drc_camcording = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_OUTPUT_ERROR_NO,
+	},
+};
+
+static const struct fd_param init_val_fd_camcording = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NO,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NO,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = 5,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NO,
+	},
+};
+/*
+ Group 1. Interrupt
+*/
+void fimc_is_hw_set_intgr0_gd0(struct fimc_is_dev *dev)
+{
+	writel(INTGR0_INTGD0, dev->regs + INTGR0);
+}
+
+int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is_dev *dev)
+{
+	u32 timeout;
+	u32 cfg = readl(dev->regs + INTSR0);
+	u32 status = INTSR0_GET_INTSD0(cfg);
+	timeout = 50000;
+
+	while (status) {
+
+		printk(KERN_INFO "%s check status \n", __func__);
+		cfg = readl(dev->regs + INTSR0);
+		status = INTSR0_GET_INTSD0(cfg);
+		if (timeout == 0) {
+			printk(KERN_INFO "%s check status failed..\n", __func__);
+			return -1;
+		}
+		timeout--;
+		udelay(1);
+	}
+	return 0;
+}
+
+int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is_dev *dev)
+{
+	u32 timeout;
+	u32 cfg = readl(dev->regs + INTMSR0);
+	u32 status = INTMSR0_GET_INTMSD0(cfg);
+
+	timeout = 50000;
+
+	while (status) {
+		printk(KERN_INFO "%s check status \n", __func__);
+
+		cfg = readl(dev->regs + INTMSR0);
+		status = INTMSR0_GET_INTMSD0(cfg);
+		if (timeout == 0) {
+			printk(KERN_INFO "%s check status failed..\n", __func__);
+			return -1;
+		}
+		timeout--;
+		udelay(1);
+	}
+	return 0;
+}
+
+int fimc_is_fw_clear_irq1(struct fimc_is_dev *dev, unsigned int intr_pos)
+{
+	writel((1<<intr_pos), dev->regs + INTCR1);
+	return 0;
+}
+
+int fimc_is_fw_clear_irq2(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + INTSR2);
+
+	writel(cfg, dev->regs + INTCR2);
+	return 0;
+}
+
+/*
+ Group 2. Common
+*/
+int fimc_is_hw_get_sensor_size_width(struct fimc_is_dev *dev)
+{
+	int width = 0;
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		width = dev->sensor.width_prev;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		width = dev->sensor.width_prev_cam;
+		break;
+	case ISS_CAPTURE_STILL:
+		width = dev->sensor.width_cap;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		width = dev->sensor.width_cam;
+		break;
+	default:
+		break;
+	}
+	return width;
+}
+
+int fimc_is_hw_get_sensor_size_height(struct fimc_is_dev *dev)
+{
+	int height = 0;
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		height = dev->sensor.height_prev;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		height = dev->sensor.height_prev_cam;
+		break;
+	case ISS_CAPTURE_STILL:
+		height = dev->sensor.height_cap;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		height = dev->sensor.height_cam;
+		break;
+	default:
+		break;
+	}
+	return height;
+}
+
+int fimc_is_hw_get_sensor_format(struct fimc_is_dev *dev)
+{
+	int format = 0;
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		format = init_val_isp_preview_still.otf_input.format;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		format = init_val_isp_preview_video.otf_input.format;
+		break;
+	case ISS_CAPTURE_STILL:
+		format = init_val_isp_capture.otf_input.format;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		format = init_val_isp_camcording.otf_input.format;
+		break;
+	default:
+		break;
+	}
+	return format;
+}
+
+int fimc_is_hw_get_sensor_max_framerate(struct fimc_is_dev *dev)
+{
+	int max_framerate = 0;
+	switch (dev->sensor.sensor_type) {
+	case SENSOR_S5K3H2_CSI_A:
+	case SENSOR_S5K3H2_CSI_B:
+		max_framerate = 15;
+		break;
+	case SENSOR_S5K3H7_CSI_A:
+	case SENSOR_S5K3H7_CSI_B:
+		max_framerate = 15;
+		break;
+	case SENSOR_S5K6A3_CSI_A:
+	case SENSOR_S5K6A3_CSI_B:
+		max_framerate = 30;
+		break;
+	case SENSOR_S5K4E5_CSI_A:
+	case SENSOR_S5K4E5_CSI_B:
+		max_framerate = 30;
+		break;
+	default:
+		max_framerate = 15;
+	}
+	return max_framerate;
+}
+
+void fimc_is_hw_open_sensor(struct fimc_is_dev *dev, u32 id, u32 sensor_index)
+{
+	struct sensor_open_extended *sensor_ext = NULL;
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_OPEN_SENSOR, dev->regs + ISSR0);
+	writel(id, dev->regs + ISSR1);
+	switch (sensor_index) {
+	case SENSOR_S5K3H2_CSI_A:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_A;
+		writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		writel(0x0, dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K3H2_CSI_B:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H2_CSI_B;
+		writel(SENSOR_NAME_S5K3H2, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		writel(0x0, dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K6A3_CSI_A:
+		sensor_ext = (struct sensor_open_extended *)
+						&dev->is_p_region->shared;
+		sensor_ext->actuator_type = 0;
+		sensor_ext->mclk = 0;
+		sensor_ext->mipi_lane_num = 0;
+		sensor_ext->mipi_speed = 0;
+		sensor_ext->fast_open_sensor = 0;
+		sensor_ext->self_calibration_mode = 1;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		dev->af.use_af = 0;
+		dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_A;
+		writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		writel(virt_to_phys(sensor_ext), dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K6A3_CSI_B:
+		sensor_ext = (struct sensor_open_extended *)
+						&dev->is_p_region->shared;
+		sensor_ext->actuator_type = 0;
+		sensor_ext->mclk = 0;
+		sensor_ext->mipi_lane_num = 0;
+		sensor_ext->mipi_speed = 0;
+		sensor_ext->fast_open_sensor = 0;
+		sensor_ext->self_calibration_mode = 1;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		dev->af.use_af = 0;
+		dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_B;
+		writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		writel(virt_to_phys(sensor_ext), dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K3H7_CSI_A:
+		sensor_ext = (struct sensor_open_extended *)
+						&dev->is_p_region->shared;
+		sensor_ext->actuator_type = 3;
+		sensor_ext->mclk = 0;
+		sensor_ext->mipi_lane_num = 0;
+		sensor_ext->mipi_speed = 0;
+		sensor_ext->fast_open_sensor = 0;
+		sensor_ext->self_calibration_mode = 0;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H7_CSI_A;
+		writel(SENSOR_NAME_S5K3H7, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		writel(virt_to_phys(sensor_ext), dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K3H7_CSI_B:
+		sensor_ext = (struct sensor_open_extended *)
+						&dev->is_p_region->shared;
+		sensor_ext->actuator_type = 3;
+		sensor_ext->mclk = 0;
+		sensor_ext->mipi_lane_num = 0;
+		sensor_ext->mipi_speed = 0;
+		sensor_ext->fast_open_sensor = 0;
+		sensor_ext->self_calibration_mode = 0;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K3H7_CSI_B;
+		writel(SENSOR_NAME_S5K3H7, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		writel(virt_to_phys(sensor_ext), dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K4E5_CSI_A:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_A;
+		writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C0, dev->regs + ISSR3);
+		writel(0x0, dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K4E5_CSI_B:
+		dev->af.use_af = 1;
+		dev->sensor.sensor_type = SENSOR_S5K4E5_CSI_B;
+		writel(SENSOR_NAME_S5K4E5, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		writel(0x0, dev->regs + ISSR4);
+		break;
+	case SENSOR_S5K6A3_CSI_B_CUSTOM:
+		sensor_ext = (struct sensor_open_extended *)
+						&dev->is_p_region->shared;
+		sensor_ext->actuator_type = 0;
+		sensor_ext->mclk = 0;
+		sensor_ext->mipi_lane_num = 0;
+		sensor_ext->mipi_speed = 0;
+		sensor_ext->fast_open_sensor = 6;
+		sensor_ext->self_calibration_mode = 1;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		dev->af.use_af = 0;
+		dev->sensor.sensor_type = SENSOR_S5K6A3_CSI_B;
+		writel(SENSOR_NAME_S5K6A3, dev->regs + ISSR2);
+		writel(SENSOR_CONTROL_I2C1, dev->regs + ISSR3);
+		writel(virt_to_phys(sensor_ext), dev->regs + ISSR4);
+		break;
+	}
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+void fimc_is_hw_close_sensor(struct fimc_is_dev *dev, u32 id)
+{
+	if (dev->sensor.id == id) {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_CLOSE_SENSOR, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(dev->sensor.id, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	}
+}
+
+void fimc_is_hw_get_setfile_addr(struct fimc_is_dev *dev)
+{
+	/* 1. Get FIMC-IS setfile address */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_GET_SET_FILE_ADDR, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+void fimc_is_hw_load_setfile(struct fimc_is_dev *dev)
+{
+	/* 1. Make FIMC-IS power-off state */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_LOAD_SET_FILE, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+int fimc_is_hw_io_init(struct fimc_is_dev *dev)
+{
+	struct platform_device *pdev = to_platform_device(&dev->pdev->dev);
+	if (dev->pdata->cfg_gpio) {
+		dev->pdata->cfg_gpio(pdev);
+	} else {
+		printk(KERN_ERR "#### failed to Config GPIO ####\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+void fimc_is_hw_set_low_poweroff(struct fimc_is_dev *dev, int on)
+{
+	if (on) {
+		printk(KERN_INFO "Set low poweroff mode\n");
+		if (!dev->low_power_mode) {
+			__raw_writel(0x0, PMUREG_ISP_ARM_OPTION);
+			__raw_writel(0x47C8, PMUREG_ISP_LOW_POWER_OFF);
+			dev->low_power_mode = true;
+		}
+	} else {
+		if (dev->low_power_mode) {
+			printk(KERN_INFO "Clear low poweroff mode\n");
+			__raw_writel(0xFFFFFFFF, PMUREG_ISP_ARM_OPTION);
+			__raw_writel(0x8, PMUREG_ISP_LOW_POWER_OFF);
+		}
+		dev->low_power_mode = false;
+	}
+}
+
+void fimc_is_hw_subip_poweroff(struct fimc_is_dev *dev)
+{
+	/* 1. Make FIMC-IS power-off state */
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_POWER_DOWN, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+void fimc_is_hw_a5_power(struct fimc_is_dev *dev, int on)
+{
+	u32 cfg;
+	u32 timeout;
+	printk(KERN_INFO "%s++ %d \n", __func__, on);
+
+	if (on) {
+		/* watchdog disable */
+		printk(KERN_INFO "%s on 1. watchdog disable\n", __func__);
+		writel(0x0, dev->regs + WDT);
+		/* 1. A5 start address setting */
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+		cfg = dev->mem.base;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+		cfg = dev->mem.dvaddr;
+#endif
+		printk(KERN_INFO "%s on 2. access BBOAR\n", __func__);
+		writel(cfg, dev->regs + BBOAR);
+		/* 2. A5 power on*/
+		printk(KERN_INFO "%s on 3. access PMUREG_ISP_ARM_CONFIGURATION\n", __func__);
+		writel(0x1, PMUREG_ISP_ARM_CONFIGURATION);
+		/* 3. enable A5 */
+		printk(KERN_INFO "%s on 4. access PMUREG_ISP_ARM_OPTION\n", __func__);
+		writel(0x00018000, PMUREG_ISP_ARM_OPTION);
+		printk(KERN_INFO "%s on 5. complete\n", __func__);
+	} else {
+		/* 1. disable A5 */
+		printk(KERN_INFO "%s off 1. access PMUREG_ISP_ARM_OPTION\n", __func__);
+		if (dev->low_power_mode) {
+			/* Low power mode */
+			printk(KERN_INFO "%s off ?!?! Low power mode (Option 0)\n", __func__);
+			writel(0x0, PMUREG_ISP_ARM_OPTION);
+		} else {
+			writel(0x10000, PMUREG_ISP_ARM_OPTION);
+		}
+		/* 2. A5 power off*/
+		printk(KERN_INFO "%s off 2. access PMUREG_ISP_ARM_CONFIGURATION\n", __func__);
+		writel(0x0, PMUREG_ISP_ARM_CONFIGURATION);
+		/* 3. Check A5 power off status register */
+		printk(KERN_INFO "%s off 3. check A5 power off status\n", __func__);
+		timeout = 1000;
+		while (__raw_readl(PMUREG_ISP_ARM_STATUS) & 0x1) {
+			if (timeout == 0) {
+				printk(KERN_ERR "%s Low power off\n", __func__);
+				fimc_is_hw_set_low_poweroff(dev, true);
+			}
+			printk(KERN_INFO "%s Wait A5 power off\n", __func__);
+			timeout--;
+			udelay(1);
+		}
+		printk(KERN_INFO "%s off 4. complete\n", __func__);
+	}
+	printk(KERN_INFO "%s --\n", __func__);
+}
+
+void fimc_is_hw_set_sensor_num(struct fimc_is_dev *dev)
+{
+	u32 cfg;
+	writel(ISR_DONE, dev->regs + ISSR0);
+	cfg = dev->sensor.id;
+	writel(cfg, dev->regs + ISSR1);
+	/* param 1 */
+	writel(IHC_GET_SENSOR_NUMBER, dev->regs + ISSR2);
+	/* param 2 */
+	cfg = dev->sensor_num;
+	writel(cfg, dev->regs + ISSR3);
+}
+
+int fimc_is_hw_get_sensor_num(struct fimc_is_dev *dev)
+{
+	u32 cfg = readl(dev->regs + ISSR11);
+	if (dev->sensor_num == cfg)
+		return 0;
+	else
+		return cfg;
+}
+
+int fimc_is_hw_set_param(struct fimc_is_dev *dev)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_SET_PARAMETER, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+
+	writel(dev->scenario_id, dev->regs + ISSR2);
+
+	writel(atomic_read(&dev->p_region_num), dev->regs + ISSR3);
+	writel(dev->p_region_index1, dev->regs + ISSR4);
+	writel(dev->p_region_index2, dev->regs + ISSR5);
+	fimc_is_hw_set_intgr0_gd0(dev);
+	return 0;
+}
+
+int fimc_is_hw_set_tune(struct fimc_is_dev *dev)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_SET_TUNE, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+
+	writel(dev->h2i_cmd.entry_id, dev->regs + ISSR2);
+
+	fimc_is_hw_set_intgr0_gd0(dev);
+	return 0;
+}
+
+int fimc_is_hw_get_param(struct fimc_is_dev *dev, u16 offset)
+{
+	dev->i2h_cmd.num_valid_args = offset;
+	switch (offset) {
+	case 1:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = 0;
+		dev->i2h_cmd.arg[2] = 0;
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 2:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = 0;
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 3:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
+		dev->i2h_cmd.arg[3] = 0;
+		break;
+	case 4:
+		dev->i2h_cmd.arg[0] = readl(dev->regs + ISSR12);
+		dev->i2h_cmd.arg[1] = readl(dev->regs + ISSR13);
+		dev->i2h_cmd.arg[2] = readl(dev->regs + ISSR14);
+		dev->i2h_cmd.arg[3] = readl(dev->regs + ISSR15);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void fimc_is_hw_set_debug_level(struct fimc_is_dev *dev, int level1, int level2)
+{
+	fimc_is_hw_wait_intmsr0_intmsd0(dev);
+	writel(HIC_MSG_CONFIG, dev->regs + ISSR0);
+	writel(dev->sensor.id, dev->regs + ISSR1);
+
+	writel(0, dev->regs + ISSR2);
+	writel(level1, dev->regs + ISSR3);
+	writel(level2, dev->regs + ISSR4);
+	fimc_is_hw_set_intgr0_gd0(dev);
+}
+
+void fimc_is_hw_set_stream(struct fimc_is_dev *dev, int on)
+{
+	if (on) {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_STREAM_ON, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(0, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	} else {
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_STREAM_OFF, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		fimc_is_hw_set_intgr0_gd0(dev);
+	}
+}
+
+void fimc_is_hw_change_mode(struct fimc_is_dev *dev, int val)
+{
+	switch (val) {
+	case IS_MODE_PREVIEW_STILL:
+		dev->scenario_id = ISS_PREVIEW_STILL;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_PREVIEW_STILL, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(dev->setfile.sub_index, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_PREVIEW_VIDEO:
+		dev->scenario_id = ISS_PREVIEW_VIDEO;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_PREVIEW_VIDEO, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(dev->setfile.sub_index, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_CAPTURE_STILL:
+		dev->scenario_id = ISS_CAPTURE_STILL;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_CAPTURE_STILL, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(dev->setfile.sub_index, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	case IS_MODE_CAPTURE_VIDEO:
+		dev->scenario_id = ISS_CAPTURE_VIDEO;
+		fimc_is_hw_wait_intmsr0_intmsd0(dev);
+		writel(HIC_CAPTURE_VIDEO, dev->regs + ISSR0);
+		writel(dev->sensor.id, dev->regs + ISSR1);
+		writel(dev->setfile.sub_index, dev->regs + ISSR2);
+		fimc_is_hw_set_intgr0_gd0(dev);
+		break;
+	}
+}
+/*
+ Group 3. Initial setting
+*/
+void fimc_is_hw_set_init(struct fimc_is_dev *dev)
+{
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		dev->sensor.frametime_max_prev =
+			init_val_isp_preview_still.otf_input.frametime_max;
+		IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 1);
+		IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+		IS_INC_PARAM_NUM(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev,
+			fimc_is_hw_get_sensor_max_framerate(dev));
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		/* ISP */
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+			init_val_isp_preview_still.control.cmd);
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_isp_preview_still.control.bypass);
+		IS_ISP_SET_PARAM_CONTROL_ERR(dev,
+			init_val_isp_preview_still.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_isp_preview_still.otf_input.cmd);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_isp_preview_still.otf_input.width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_isp_preview_still.otf_input.height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_isp_preview_still.otf_input.format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_isp_preview_still.otf_input.bitwidth);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_isp_preview_still.otf_input.order);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
+			init_val_isp_preview_still.otf_input.crop_offset_x);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
+			init_val_isp_preview_still.otf_input.crop_offset_y);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
+			init_val_isp_preview_still.otf_input.crop_width);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
+			init_val_isp_preview_still.otf_input.crop_height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
+			init_val_isp_preview_still.otf_input.frametime_min);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+			init_val_isp_preview_still.otf_input.frametime_max);
+		IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_isp_preview_still.otf_input.err);
+		dev->sensor.width_prev =
+			init_val_isp_preview_still.otf_input.width;
+		dev->sensor.height_prev =
+			init_val_isp_preview_still.otf_input.height;
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
+			init_val_isp_preview_still.dma1_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
+			init_val_isp_preview_still.dma1_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
+			init_val_isp_preview_still.dma1_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
+			init_val_isp_preview_still.dma1_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
+			init_val_isp_preview_still.dma1_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
+			init_val_isp_preview_still.dma1_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
+			init_val_isp_preview_still.dma1_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
+			init_val_isp_preview_still.dma1_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
+			init_val_isp_preview_still.dma1_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
+			init_val_isp_preview_still.dma1_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
+			init_val_isp_preview_still.dma2_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
+			init_val_isp_preview_still.dma2_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
+			init_val_isp_preview_still.dma2_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
+			init_val_isp_preview_still.dma2_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
+			init_val_isp_preview_still.dma2_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
+			init_val_isp_preview_still.dma2_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
+			init_val_isp_preview_still.dma2_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
+			init_val_isp_preview_still.dma2_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
+			init_val_isp_preview_still.dma2_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
+			init_val_isp_preview_still.dma2_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev,
+				init_val_isp_preview_still.aa.cmd);
+		IS_ISP_SET_PARAM_AA_TARGET(dev,
+				init_val_isp_preview_still.aa.target);
+		IS_ISP_SET_PARAM_AA_MODE(dev,
+				init_val_isp_preview_still.aa.mode);
+		IS_ISP_SET_PARAM_AA_FACE(dev,
+				init_val_isp_preview_still.aa.face);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
+			init_val_isp_preview_still.aa.touch_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
+			init_val_isp_preview_still.aa.touch_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
+			init_val_isp_preview_still.aa.manual_af_setting);
+		IS_ISP_SET_PARAM_AA_ERR(dev,
+			init_val_isp_preview_still.aa.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_FLASH_CMD(dev,
+			init_val_isp_preview_still.flash.cmd);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
+			init_val_isp_preview_still.flash.redeye);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev,
+			init_val_isp_preview_still.flash.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+			init_val_isp_preview_still.awb.cmd);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			init_val_isp_preview_still.awb.illumination);
+		IS_ISP_SET_PARAM_AWB_ERR(dev,
+			init_val_isp_preview_still.awb.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			init_val_isp_preview_still.effect.cmd);
+		IS_ISP_SET_PARAM_EFFECT_ERR(dev,
+			init_val_isp_preview_still.effect.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ISO_CMD(dev,
+			init_val_isp_preview_still.iso.cmd);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev,
+			init_val_isp_preview_still.iso.value);
+		IS_ISP_SET_PARAM_ISO_ERR(dev,
+			init_val_isp_preview_still.iso.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+			init_val_isp_preview_still.adjust.cmd);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
+			init_val_isp_preview_still.adjust.contrast);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
+			init_val_isp_preview_still.adjust.saturation);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
+			init_val_isp_preview_still.adjust.sharpness);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
+			init_val_isp_preview_still.adjust.exposure);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
+			init_val_isp_preview_still.adjust.brightness);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev,
+			init_val_isp_preview_still.adjust.hue);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev,
+			init_val_isp_preview_still.adjust.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			init_val_isp_preview_still.metering.cmd);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
+			init_val_isp_preview_still.metering.win_pos_x);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
+			init_val_isp_preview_still.metering.win_pos_y);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+			init_val_isp_preview_still.metering.win_width);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+			init_val_isp_preview_still.metering.win_height);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			init_val_isp_preview_still.metering.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AFC_CMD(dev,
+			init_val_isp_preview_still.afc.cmd);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev,
+			init_val_isp_preview_still.afc.manual);
+		IS_ISP_SET_PARAM_AFC_ERR(dev,
+			init_val_isp_preview_still.afc.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_isp_preview_still.otf_output.cmd);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_isp_preview_still.otf_output.width);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_isp_preview_still.otf_output.height);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_isp_preview_still.otf_output.format);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_isp_preview_still.otf_output.bitwidth);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_isp_preview_still.otf_output.order);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_isp_preview_still.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
+			init_val_isp_preview_still.dma1_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+			init_val_isp_preview_still.dma1_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+			init_val_isp_preview_still.dma1_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
+			init_val_isp_preview_still.dma1_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
+			init_val_isp_preview_still.dma1_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
+			init_val_isp_preview_still.dma1_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
+			init_val_isp_preview_still.dma1_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+			init_val_isp_preview_still.dma1_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+			init_val_isp_preview_still.dma1_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
+			init_val_isp_preview_still.dma1_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
+			init_val_isp_preview_still.dma2_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+			init_val_isp_preview_still.dma2_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+			init_val_isp_preview_still.dma2_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
+			init_val_isp_preview_still.dma2_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
+			init_val_isp_preview_still.dma2_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
+			init_val_isp_preview_still.dma2_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
+			init_val_isp_preview_still.dma2_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
+			init_val_isp_preview_still.dma2_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
+			init_val_isp_preview_still.dma2_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
+			init_val_isp_preview_still.dma2_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* DRC */
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev,
+			init_val_drc_preview_still.control.cmd);
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_drc_preview_still.control.bypass);
+		IS_DRC_SET_PARAM_CONTROL_ERR(dev,
+			init_val_drc_preview_still.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_drc_preview_still.otf_input.cmd);
+		IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_drc_preview_still.otf_input.width);
+		IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_drc_preview_still.otf_input.height);
+		IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_drc_preview_still.otf_input.format);
+		IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_drc_preview_still.otf_input.bitwidth);
+		IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_drc_preview_still.otf_input.order);
+		IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_drc_preview_still.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_drc_preview_still.dma_input.cmd);
+		IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_drc_preview_still.dma_input.width);
+		IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_drc_preview_still.dma_input.height);
+		IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_drc_preview_still.dma_input.format);
+		IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_drc_preview_still.dma_input.bitwidth);
+		IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_drc_preview_still.dma_input.plane);
+		IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_drc_preview_still.dma_input.order);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_drc_preview_still.dma_input.buffer_number);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_drc_preview_still.dma_input.buffer_address);
+		IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_drc_preview_still.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_drc_preview_still.otf_output.cmd);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_drc_preview_still.otf_output.width);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_drc_preview_still.otf_output.height);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_drc_preview_still.otf_output.format);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_drc_preview_still.otf_output.bitwidth);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_drc_preview_still.otf_output.order);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_drc_preview_still.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* FD */
+		IS_FD_SET_PARAM_CONTROL_CMD(dev,
+			init_val_fd_preview_still.control.cmd);
+		IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_fd_preview_still.control.bypass);
+		IS_FD_SET_PARAM_CONTROL_ERR(dev,
+			init_val_fd_preview_still.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_fd_preview_still.otf_input.cmd);
+		IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_fd_preview_still.otf_input.width);
+		IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_fd_preview_still.otf_input.height);
+		IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_fd_preview_still.otf_input.format);
+		IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_fd_preview_still.otf_input.bitwidth);
+		IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_fd_preview_still.otf_input.order);
+		IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_fd_preview_still.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_fd_preview_still.dma_input.cmd);
+		IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_fd_preview_still.dma_input.width);
+		IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_fd_preview_still.dma_input.height);
+		IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_fd_preview_still.dma_input.format);
+		IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_fd_preview_still.dma_input.bitwidth);
+		IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_fd_preview_still.dma_input.plane);
+		IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_fd_preview_still.dma_input.order);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_fd_preview_still.dma_input.buffer_number);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_fd_preview_still.dma_input.buffer_address);
+		IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_fd_preview_still.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			init_val_fd_preview_still.config.cmd);
+		IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
+			init_val_fd_preview_still.config.max_number);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
+			init_val_fd_preview_still.config.roll_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
+			init_val_fd_preview_still.config.yaw_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
+			init_val_fd_preview_still.config.smile_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
+			init_val_fd_preview_still.config.blink_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
+			init_val_fd_preview_still.config.eye_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
+			init_val_fd_preview_still.config.mouth_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
+			init_val_fd_preview_still.config.orientation);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
+			init_val_fd_preview_still.config.orientation_value);
+		IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
+			init_val_fd_preview_still.config.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		break;
+	case ISS_PREVIEW_VIDEO:
+		dev->sensor.frametime_max_prev_cam =
+			init_val_isp_preview_video.otf_input.frametime_max;
+		IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 1);
+		IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+		IS_INC_PARAM_NUM(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, DEFAULT_PREVIEW_VIDEO_FRAMERATE);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		/* ISP */
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+			init_val_isp_preview_video.control.cmd);
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_isp_preview_video.control.bypass);
+		IS_ISP_SET_PARAM_CONTROL_ERR(dev,
+			init_val_isp_preview_video.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_isp_preview_video.otf_input.cmd);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_isp_preview_video.otf_input.width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_isp_preview_video.otf_input.height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_isp_preview_video.otf_input.format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_isp_preview_video.otf_input.bitwidth);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_isp_preview_video.otf_input.order);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
+			init_val_isp_preview_video.otf_input.crop_offset_x);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
+			init_val_isp_preview_video.otf_input.crop_offset_y);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
+			init_val_isp_preview_video.otf_input.crop_width);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
+			init_val_isp_preview_video.otf_input.crop_height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
+			init_val_isp_preview_video.otf_input.frametime_min);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+			init_val_isp_preview_video.otf_input.frametime_max);
+		IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_isp_preview_video.otf_input.err);
+		dev->sensor.width_prev_cam =
+			init_val_isp_preview_video.otf_input.width;
+		dev->sensor.height_prev_cam =
+			init_val_isp_preview_video.otf_input.height;
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
+			init_val_isp_preview_video.dma1_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
+			init_val_isp_preview_video.dma1_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
+			init_val_isp_preview_video.dma1_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
+			init_val_isp_preview_video.dma1_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
+			init_val_isp_preview_video.dma1_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
+			init_val_isp_preview_video.dma1_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
+			init_val_isp_preview_video.dma1_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
+			init_val_isp_preview_video.dma1_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
+			init_val_isp_preview_video.dma1_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
+			init_val_isp_preview_video.dma1_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
+			init_val_isp_preview_video.dma2_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
+			init_val_isp_preview_video.dma2_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
+			init_val_isp_preview_video.dma2_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
+			init_val_isp_preview_video.dma2_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
+			init_val_isp_preview_video.dma2_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
+			init_val_isp_preview_video.dma2_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
+			init_val_isp_preview_video.dma2_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
+			init_val_isp_preview_video.dma2_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
+			init_val_isp_preview_video.dma2_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
+			init_val_isp_preview_video.dma2_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev,
+			init_val_isp_preview_video.aa.cmd);
+		IS_ISP_SET_PARAM_AA_TARGET(dev,
+			init_val_isp_preview_video.aa.target);
+		IS_ISP_SET_PARAM_AA_MODE(dev,
+			init_val_isp_preview_video.aa.mode);
+		IS_ISP_SET_PARAM_AA_FACE(dev,
+			init_val_isp_preview_video.aa.face);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
+			init_val_isp_preview_video.aa.touch_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
+			init_val_isp_preview_video.aa.touch_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
+			init_val_isp_preview_video.aa.manual_af_setting);
+		IS_ISP_SET_PARAM_AA_ERR(dev,
+			init_val_isp_preview_video.aa.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_FLASH_CMD(dev,
+			init_val_isp_preview_video.flash.cmd);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
+			init_val_isp_preview_video.flash.redeye);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev,
+			init_val_isp_preview_video.flash.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+			init_val_isp_preview_video.awb.cmd);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			init_val_isp_preview_video.awb.illumination);
+		IS_ISP_SET_PARAM_AWB_ERR(dev,
+			init_val_isp_preview_video.awb.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			init_val_isp_preview_video.effect.cmd);
+		IS_ISP_SET_PARAM_EFFECT_ERR(dev,
+			init_val_isp_preview_video.effect.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ISO_CMD(dev,
+			init_val_isp_preview_video.iso.cmd);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev,
+			init_val_isp_preview_video.iso.value);
+		IS_ISP_SET_PARAM_ISO_ERR(dev,
+			init_val_isp_preview_video.iso.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+			init_val_isp_preview_video.adjust.cmd);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
+			init_val_isp_preview_video.adjust.contrast);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
+			init_val_isp_preview_video.adjust.saturation);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
+			init_val_isp_preview_video.adjust.sharpness);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
+			init_val_isp_preview_video.adjust.exposure);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
+			init_val_isp_preview_video.adjust.brightness);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev,
+			init_val_isp_preview_video.adjust.hue);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev,
+			init_val_isp_preview_video.adjust.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			init_val_isp_preview_video.metering.cmd);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
+			init_val_isp_preview_video.metering.win_pos_x);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
+			init_val_isp_preview_video.metering.win_pos_y);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+			init_val_isp_preview_video.metering.win_width);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+			init_val_isp_preview_video.metering.win_height);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			init_val_isp_preview_video.metering.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AFC_CMD(dev,
+			init_val_isp_preview_video.afc.cmd);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev,
+			init_val_isp_preview_video.afc.manual);
+		IS_ISP_SET_PARAM_AFC_ERR(dev,
+			init_val_isp_preview_video.afc.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_isp_preview_video.otf_output.cmd);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_isp_preview_video.otf_output.width);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_isp_preview_video.otf_output.height);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_isp_preview_video.otf_output.format);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_isp_preview_video.otf_output.bitwidth);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_isp_preview_video.otf_output.order);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_isp_preview_video.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
+			init_val_isp_preview_video.dma1_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+			init_val_isp_preview_video.dma1_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+			init_val_isp_preview_video.dma1_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
+			init_val_isp_preview_video.dma1_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
+			init_val_isp_preview_video.dma1_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
+			init_val_isp_preview_video.dma1_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
+			init_val_isp_preview_video.dma1_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+			init_val_isp_preview_video.dma1_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+			init_val_isp_preview_video.dma1_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
+			init_val_isp_preview_video.dma1_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
+			init_val_isp_preview_video.dma2_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+			init_val_isp_preview_video.dma2_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+			init_val_isp_preview_video.dma2_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
+			init_val_isp_preview_video.dma2_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
+			init_val_isp_preview_video.dma2_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
+			init_val_isp_preview_video.dma2_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
+			init_val_isp_preview_video.dma2_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
+			init_val_isp_preview_video.dma2_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
+			init_val_isp_preview_video.dma2_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
+			init_val_isp_preview_video.dma2_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* DRC */
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev,
+			init_val_drc_preview_video.control.cmd);
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_drc_preview_video.control.bypass);
+		IS_DRC_SET_PARAM_CONTROL_ERR(dev,
+			init_val_drc_preview_video.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_drc_preview_video.otf_input.cmd);
+		IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_drc_preview_video.otf_input.width);
+		IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_drc_preview_video.otf_input.height);
+		IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_drc_preview_video.otf_input.format);
+		IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_drc_preview_video.otf_input.bitwidth);
+		IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_drc_preview_video.otf_input.order);
+		IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_drc_preview_video.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_drc_preview_video.dma_input.cmd);
+		IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_drc_preview_video.dma_input.width);
+		IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_drc_preview_video.dma_input.height);
+		IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_drc_preview_video.dma_input.format);
+		IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_drc_preview_video.dma_input.bitwidth);
+		IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_drc_preview_video.dma_input.plane);
+		IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_drc_preview_video.dma_input.order);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_drc_preview_video.dma_input.buffer_number);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_drc_preview_video.dma_input.buffer_address);
+		IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_drc_preview_video.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_drc_preview_video.otf_output.cmd);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_drc_preview_video.otf_output.width);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_drc_preview_video.otf_output.height);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_drc_preview_video.otf_output.format);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_drc_preview_video.otf_output.bitwidth);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_drc_preview_video.otf_output.order);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_drc_preview_video.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* FD */
+		IS_FD_SET_PARAM_CONTROL_CMD(dev,
+			init_val_fd_preview_video.control.cmd);
+		IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_fd_preview_video.control.bypass);
+		IS_FD_SET_PARAM_CONTROL_ERR(dev,
+			init_val_fd_preview_video.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_fd_preview_video.otf_input.cmd);
+		IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_fd_preview_video.otf_input.width);
+		IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_fd_preview_video.otf_input.height);
+		IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_fd_preview_video.otf_input.format);
+		IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_fd_preview_video.otf_input.bitwidth);
+		IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_fd_preview_video.otf_input.order);
+		IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_fd_preview_video.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_fd_preview_video.dma_input.cmd);
+		IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_fd_preview_video.dma_input.width);
+		IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_fd_preview_video.dma_input.height);
+		IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_fd_preview_video.dma_input.format);
+		IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_fd_preview_video.dma_input.bitwidth);
+		IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_fd_preview_video.dma_input.plane);
+		IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_fd_preview_video.dma_input.order);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_fd_preview_video.dma_input.buffer_number);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_fd_preview_video.dma_input.buffer_address);
+		IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_fd_preview_video.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			init_val_fd_preview_video.config.cmd);
+		IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
+			init_val_fd_preview_video.config.max_number);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
+			init_val_fd_preview_video.config.roll_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
+			init_val_fd_preview_video.config.yaw_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
+			init_val_fd_preview_video.config.smile_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
+			init_val_fd_preview_video.config.blink_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
+			init_val_fd_preview_video.config.eye_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
+			init_val_fd_preview_video.config.mouth_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
+			init_val_fd_preview_video.config.orientation);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
+			init_val_fd_preview_video.config.orientation_value);
+		IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
+			init_val_fd_preview_video.config.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		break;
+
+	case ISS_CAPTURE_STILL:
+		dev->sensor.frametime_max_cap =
+			init_val_isp_capture.otf_input.frametime_max;
+		IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 1);
+		IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+		IS_INC_PARAM_NUM(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, DEFAULT_CAPTURE_STILL_FRAMERATE);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		/* ISP */
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+			init_val_isp_capture.control.cmd);
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_isp_capture.control.bypass);
+		IS_ISP_SET_PARAM_CONTROL_ERR(dev,
+			init_val_isp_capture.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_isp_capture.otf_input.cmd);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_isp_capture.otf_input.width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_isp_capture.otf_input.height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_isp_capture.otf_input.format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_isp_capture.otf_input.bitwidth);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_isp_capture.otf_input.order);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
+			init_val_isp_capture.otf_input.crop_offset_x);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
+			init_val_isp_capture.otf_input.crop_offset_y);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
+			init_val_isp_capture.otf_input.crop_width);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
+			init_val_isp_capture.otf_input.crop_height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
+			init_val_isp_capture.otf_input.frametime_min);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+			init_val_isp_capture.otf_input.frametime_max);
+		IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_isp_capture.otf_input.err);
+		dev->sensor.width_cap =
+			init_val_isp_capture.otf_input.width;
+		dev->sensor.height_cap =
+			init_val_isp_capture.otf_input.height;
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
+			init_val_isp_capture.dma1_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
+			init_val_isp_capture.dma1_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
+			init_val_isp_capture.dma1_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
+			init_val_isp_capture.dma1_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
+			init_val_isp_capture.dma1_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
+			init_val_isp_capture.dma1_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
+			init_val_isp_capture.dma1_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
+			init_val_isp_capture.dma1_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
+			init_val_isp_capture.dma1_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
+			init_val_isp_capture.dma1_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
+			init_val_isp_capture.dma2_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
+			init_val_isp_capture.dma2_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
+			init_val_isp_capture.dma2_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
+			init_val_isp_capture.dma2_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
+			init_val_isp_capture.dma2_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
+			init_val_isp_capture.dma2_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
+			init_val_isp_capture.dma2_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
+			init_val_isp_capture.dma2_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
+			init_val_isp_capture.dma2_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
+			init_val_isp_capture.dma2_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, init_val_isp_capture.aa.cmd);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, init_val_isp_capture.aa.target);
+		IS_ISP_SET_PARAM_AA_MODE(dev, init_val_isp_capture.aa.mode);
+		IS_ISP_SET_PARAM_AA_FACE(dev, init_val_isp_capture.aa.face);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
+			init_val_isp_capture.aa.touch_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
+			init_val_isp_capture.aa.touch_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
+			init_val_isp_capture.aa.manual_af_setting);
+		IS_ISP_SET_PARAM_AA_ERR(dev, init_val_isp_capture.aa.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_FLASH_CMD(dev,
+			init_val_isp_capture.flash.cmd);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
+			init_val_isp_capture.flash.redeye);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev,
+			init_val_isp_capture.flash.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AWB_CMD(dev, init_val_isp_capture.awb.cmd);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			init_val_isp_capture.awb.illumination);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, init_val_isp_capture.awb.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			init_val_isp_capture.effect.cmd);
+		IS_ISP_SET_PARAM_EFFECT_ERR(dev,
+			init_val_isp_capture.effect.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ISO_CMD(dev,
+			init_val_isp_capture.iso.cmd);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev,
+			init_val_isp_capture.iso.value);
+		IS_ISP_SET_PARAM_ISO_ERR(dev,
+			init_val_isp_capture.iso.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+			init_val_isp_capture.adjust.cmd);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
+			init_val_isp_capture.adjust.contrast);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
+			init_val_isp_capture.adjust.saturation);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
+			init_val_isp_capture.adjust.sharpness);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
+			init_val_isp_capture.adjust.exposure);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
+			init_val_isp_capture.adjust.brightness);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev,
+			init_val_isp_capture.adjust.hue);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev,
+			init_val_isp_capture.adjust.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			init_val_isp_capture.metering.cmd);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
+			init_val_isp_capture.metering.win_pos_x);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
+			init_val_isp_capture.metering.win_pos_y);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+			init_val_isp_capture.metering.win_width);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+			init_val_isp_capture.metering.win_height);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			init_val_isp_capture.metering.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AFC_CMD(dev, init_val_isp_capture.afc.cmd);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev,
+			init_val_isp_capture.afc.manual);
+		IS_ISP_SET_PARAM_AFC_ERR(dev, init_val_isp_capture.afc.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_isp_capture.otf_output.cmd);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_isp_capture.otf_output.width);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_isp_capture.otf_output.height);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_isp_capture.otf_output.format);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_isp_capture.otf_output.bitwidth);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_isp_capture.otf_output.order);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_isp_capture.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
+			init_val_isp_capture.dma1_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+			init_val_isp_capture.dma1_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+			init_val_isp_capture.dma1_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
+			init_val_isp_capture.dma1_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
+			init_val_isp_capture.dma1_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
+			init_val_isp_capture.dma1_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
+			init_val_isp_capture.dma1_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+			init_val_isp_capture.dma1_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+			init_val_isp_capture.dma1_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
+			init_val_isp_capture.dma1_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
+			init_val_isp_capture.dma2_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+			init_val_isp_capture.dma2_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+			init_val_isp_capture.dma2_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
+			init_val_isp_capture.dma2_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
+			init_val_isp_capture.dma2_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
+			init_val_isp_capture.dma2_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
+			init_val_isp_capture.dma2_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
+			init_val_isp_capture.dma2_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
+			init_val_isp_capture.dma2_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
+			init_val_isp_capture.dma2_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* DRC */
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev,
+			init_val_drc_capture.control.cmd);
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_drc_capture.control.bypass);
+		IS_DRC_SET_PARAM_CONTROL_ERR(dev,
+			init_val_drc_capture.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_drc_capture.otf_input.cmd);
+		IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_drc_capture.otf_input.width);
+		IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_drc_capture.otf_input.height);
+		IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_drc_capture.otf_input.format);
+		IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_drc_capture.otf_input.bitwidth);
+		IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_drc_capture.otf_input.order);
+		IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_drc_capture.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_drc_capture.dma_input.cmd);
+		IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_drc_capture.dma_input.width);
+		IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_drc_capture.dma_input.height);
+		IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_drc_capture.dma_input.format);
+		IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_drc_capture.dma_input.bitwidth);
+		IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_drc_capture.dma_input.plane);
+		IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_drc_capture.dma_input.order);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_drc_capture.dma_input.buffer_number);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_drc_capture.dma_input.buffer_address);
+		IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_drc_capture.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_drc_capture.otf_output.cmd);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_drc_capture.otf_output.width);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_drc_capture.otf_output.height);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_drc_capture.otf_output.format);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_drc_capture.otf_output.bitwidth);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_drc_capture.otf_output.order);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_drc_capture.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* FD */
+		IS_FD_SET_PARAM_CONTROL_CMD(dev,
+			init_val_fd_capture.control.cmd);
+		IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_fd_capture.control.bypass);
+		IS_FD_SET_PARAM_CONTROL_ERR(dev,
+			init_val_fd_capture.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_fd_capture.otf_input.cmd);
+		IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_fd_capture.otf_input.width);
+		IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_fd_capture.otf_input.height);
+		IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_fd_capture.otf_input.format);
+		IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_fd_capture.otf_input.bitwidth);
+		IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_fd_capture.otf_input.order);
+		IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_fd_capture.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_fd_capture.dma_input.cmd);
+		IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_fd_capture.dma_input.width);
+		IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_fd_capture.dma_input.height);
+		IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_fd_capture.dma_input.format);
+		IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_fd_capture.dma_input.bitwidth);
+		IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_fd_capture.dma_input.plane);
+		IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_fd_capture.dma_input.order);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_fd_capture.dma_input.buffer_number);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_fd_capture.dma_input.buffer_address);
+		IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_fd_capture.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			init_val_fd_capture.config.cmd);
+		IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
+			init_val_fd_capture.config.max_number);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
+			init_val_fd_capture.config.roll_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
+			init_val_fd_capture.config.yaw_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
+			init_val_fd_capture.config.smile_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
+			init_val_fd_capture.config.blink_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
+			init_val_fd_capture.config.eye_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
+			init_val_fd_capture.config.mouth_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
+			init_val_fd_capture.config.orientation);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
+			init_val_fd_capture.config.orientation_value);
+		IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
+			init_val_fd_capture.config.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		break;
+
+	case ISS_CAPTURE_VIDEO:
+		dev->sensor.frametime_max_cam =
+			init_val_isp_camcording.otf_input.frametime_max;
+		IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, 1);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, DEFAULT_CAPTURE_VIDEO_FRAMERATE);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		/* ISP */
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+			init_val_isp_camcording.control.cmd);
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_isp_camcording.control.bypass);
+		IS_ISP_SET_PARAM_CONTROL_ERR(dev,
+			init_val_isp_camcording.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_isp_camcording.otf_input.cmd);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_isp_camcording.otf_input.width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_isp_camcording.otf_input.height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_isp_camcording.otf_input.format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_isp_camcording.otf_input.bitwidth);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_isp_camcording.otf_input.order);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev,
+			init_val_isp_camcording.otf_input.crop_offset_x);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev,
+			init_val_isp_camcording.otf_input.crop_offset_y);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev,
+			init_val_isp_camcording.otf_input.crop_width);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev,
+			init_val_isp_camcording.otf_input.crop_height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev,
+			init_val_isp_camcording.otf_input.frametime_min);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+			init_val_isp_camcording.otf_input.frametime_max);
+		IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_isp_camcording.otf_input.err);
+		dev->sensor.width_cam =
+			init_val_isp_camcording.otf_input.width;
+		dev->sensor.height_cam =
+			init_val_isp_camcording.otf_input.height;
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev,
+			init_val_isp_camcording.dma1_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev,
+			init_val_isp_camcording.dma1_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev,
+			init_val_isp_camcording.dma1_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev,
+			init_val_isp_camcording.dma1_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev,
+			init_val_isp_camcording.dma1_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev,
+			init_val_isp_camcording.dma1_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev,
+			init_val_isp_camcording.dma1_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev,
+			init_val_isp_camcording.dma1_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev,
+			init_val_isp_camcording.dma1_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev,
+			init_val_isp_camcording.dma1_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev,
+			init_val_isp_camcording.dma2_input.cmd);
+		IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev,
+			init_val_isp_camcording.dma2_input.width);
+		IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev,
+			init_val_isp_camcording.dma2_input.height);
+		IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev,
+			init_val_isp_camcording.dma2_input.format);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev,
+			init_val_isp_camcording.dma2_input.bitwidth);
+		IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev,
+			init_val_isp_camcording.dma2_input.plane);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev,
+			init_val_isp_camcording.dma2_input.order);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev,
+			init_val_isp_camcording.dma2_input.buffer_number);
+		IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev,
+			init_val_isp_camcording.dma2_input.buffer_address);
+		IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev,
+			init_val_isp_camcording.dma2_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, init_val_isp_camcording.aa.cmd);
+		IS_ISP_SET_PARAM_AA_TARGET(dev,
+			init_val_isp_camcording.aa.target);
+		IS_ISP_SET_PARAM_AA_MODE(dev, init_val_isp_camcording.aa.mode);
+		IS_ISP_SET_PARAM_AA_FACE(dev, init_val_isp_camcording.aa.face);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev,
+			init_val_isp_camcording.aa.touch_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev,
+			init_val_isp_camcording.aa.touch_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev,
+			init_val_isp_camcording.aa.manual_af_setting);
+		IS_ISP_SET_PARAM_AA_ERR(dev, init_val_isp_camcording.aa.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_FLASH_CMD(dev,
+			init_val_isp_camcording.flash.cmd);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev,
+			init_val_isp_camcording.flash.redeye);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev,
+			init_val_isp_camcording.flash.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AWB_CMD(dev, init_val_isp_camcording.awb.cmd);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			init_val_isp_camcording.awb.illumination);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, init_val_isp_camcording.awb.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			init_val_isp_camcording.effect.cmd);
+		IS_ISP_SET_PARAM_EFFECT_ERR(dev,
+			init_val_isp_camcording.effect.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ISO_CMD(dev,
+			init_val_isp_camcording.iso.cmd);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev,
+			init_val_isp_camcording.iso.value);
+		IS_ISP_SET_PARAM_ISO_ERR(dev,
+			init_val_isp_camcording.iso.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+			init_val_isp_camcording.adjust.cmd);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev,
+			init_val_isp_camcording.adjust.contrast);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev,
+			init_val_isp_camcording.adjust.saturation);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev,
+			init_val_isp_camcording.adjust.sharpness);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev,
+			init_val_isp_camcording.adjust.exposure);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev,
+			init_val_isp_camcording.adjust.brightness);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev,
+			init_val_isp_camcording.adjust.hue);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev,
+			init_val_isp_camcording.adjust.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			init_val_isp_camcording.metering.cmd);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev,
+			init_val_isp_camcording.metering.win_pos_x);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev,
+			init_val_isp_camcording.metering.win_pos_y);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev,
+			init_val_isp_camcording.metering.win_width);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev,
+			init_val_isp_camcording.metering.win_height);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			init_val_isp_camcording.metering.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_AFC_CMD(dev, init_val_isp_camcording.afc.cmd);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev,
+			init_val_isp_camcording.afc.manual);
+		IS_ISP_SET_PARAM_AFC_ERR(dev, init_val_isp_camcording.afc.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_isp_camcording.otf_output.cmd);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_isp_camcording.otf_output.width);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_isp_camcording.otf_output.height);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_isp_camcording.otf_output.format);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_isp_camcording.otf_output.bitwidth);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_isp_camcording.otf_output.order);
+		IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_isp_camcording.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev,
+			init_val_isp_camcording.dma1_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev,
+			init_val_isp_camcording.dma1_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev,
+			init_val_isp_camcording.dma1_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev,
+			init_val_isp_camcording.dma1_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev,
+			init_val_isp_camcording.dma1_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev,
+			init_val_isp_camcording.dma1_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev,
+			init_val_isp_camcording.dma1_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev,
+			init_val_isp_camcording.dma1_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev,
+			init_val_isp_camcording.dma1_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev,
+			init_val_isp_camcording.dma1_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev,
+			init_val_isp_camcording.dma2_output.cmd);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev,
+			init_val_isp_camcording.dma2_output.width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev,
+			init_val_isp_camcording.dma2_output.height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev,
+			init_val_isp_camcording.dma2_output.format);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev,
+			init_val_isp_camcording.dma2_output.bitwidth);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev,
+			init_val_isp_camcording.dma2_output.plane);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev,
+			init_val_isp_camcording.dma2_output.order);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev,
+			init_val_isp_camcording.dma2_output.buffer_number);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev,
+			init_val_isp_camcording.dma2_output.buffer_address);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev,
+			init_val_isp_camcording.dma2_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* DRC */
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev,
+			init_val_drc_camcording.control.cmd);
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_drc_camcording.control.bypass);
+		IS_DRC_SET_PARAM_CONTROL_ERR(dev,
+			init_val_drc_camcording.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_drc_camcording.otf_input.cmd);
+		IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_drc_camcording.otf_input.width);
+		IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_drc_camcording.otf_input.height);
+		IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_drc_camcording.otf_input.format);
+		IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_drc_camcording.otf_input.bitwidth);
+		IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_drc_camcording.otf_input.order);
+		IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_drc_camcording.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_drc_camcording.dma_input.cmd);
+		IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_drc_camcording.dma_input.width);
+		IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_drc_camcording.dma_input.height);
+		IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_drc_camcording.dma_input.format);
+		IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_drc_camcording.dma_input.bitwidth);
+		IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_drc_camcording.dma_input.plane);
+		IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_drc_camcording.dma_input.order);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_drc_camcording.dma_input.buffer_number);
+		IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_drc_camcording.dma_input.buffer_address);
+		IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_drc_camcording.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev,
+			init_val_drc_camcording.otf_output.cmd);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev,
+			init_val_drc_camcording.otf_output.width);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev,
+			init_val_drc_camcording.otf_output.height);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev,
+			init_val_drc_camcording.otf_output.format);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev,
+			init_val_drc_camcording.otf_output.bitwidth);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev,
+			init_val_drc_camcording.otf_output.order);
+		IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev,
+			init_val_drc_camcording.otf_output.err);
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+		IS_INC_PARAM_NUM(dev);
+
+		/* FD */
+		IS_FD_SET_PARAM_CONTROL_CMD(dev,
+			init_val_fd_camcording.control.cmd);
+		IS_FD_SET_PARAM_CONTROL_BYPASS(dev,
+			init_val_fd_camcording.control.bypass);
+		IS_FD_SET_PARAM_CONTROL_ERR(dev,
+			init_val_fd_camcording.control.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_OTF_INPUT_CMD(dev,
+			init_val_fd_camcording.otf_input.cmd);
+		IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev,
+			init_val_fd_camcording.otf_input.width);
+		IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev,
+			init_val_fd_camcording.otf_input.height);
+		IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev,
+			init_val_fd_camcording.otf_input.format);
+		IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+			init_val_fd_camcording.otf_input.bitwidth);
+		IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev,
+			init_val_fd_camcording.otf_input.order);
+		IS_FD_SET_PARAM_OTF_INPUT_ERR(dev,
+			init_val_fd_camcording.otf_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_DMA_INPUT_CMD(dev,
+			init_val_fd_camcording.dma_input.cmd);
+		IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev,
+			init_val_fd_camcording.dma_input.width);
+		IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev,
+			init_val_fd_camcording.dma_input.height);
+		IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev,
+			init_val_fd_camcording.dma_input.format);
+		IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev,
+			init_val_fd_camcording.dma_input.bitwidth);
+		IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev,
+			init_val_fd_camcording.dma_input.plane);
+		IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev,
+			init_val_fd_camcording.dma_input.order);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev,
+			init_val_fd_camcording.dma_input.buffer_number);
+		IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev,
+			init_val_fd_camcording.dma_input.buffer_address);
+		IS_FD_SET_PARAM_DMA_INPUT_ERR(dev,
+			init_val_fd_camcording.dma_input.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_DMA_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			init_val_fd_camcording.config.cmd);
+		IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev,
+			init_val_fd_camcording.config.max_number);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev,
+			init_val_fd_camcording.config.roll_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev,
+			init_val_fd_camcording.config.yaw_angle);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev,
+			init_val_fd_camcording.config.smile_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev,
+			init_val_fd_camcording.config.blink_mode);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev,
+			init_val_fd_camcording.config.eye_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev,
+			init_val_fd_camcording.config.mouth_detect);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev,
+			init_val_fd_camcording.config.orientation);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev,
+			init_val_fd_camcording.config.orientation_value);
+		IS_FD_SET_PARAM_FD_CONFIG_ERR(dev,
+			init_val_fd_camcording.config.err);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		break;
+	}
+}
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-mem.c b/drivers/media/video/exynos/fimc-is/fimc-is-mem.c
new file mode 100644
index 0000000..11370b6
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-mem.c
@@ -0,0 +1,333 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * v4l2 subdev driver interface
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/cma.h>
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#include <media/videobuf2-core.h>
+#include <asm/cacheflush.h>
+#include <media/videobuf2-cma-phys.h>
+#if defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+#include "fimc-is-core.h"
+#include "fimc-is-param.h"
+
+#if defined(CONFIG_VIDEOBUF2_ION)
+#define	FIMC_IS_ION_NAME	"exynos4-fimc-is"
+#define FIMC_IS_FW_BASE_MASK		((1 << 26) - 1)
+
+struct vb2_buffer *is_vb;
+void *buf_start;
+
+struct vb2_ion_conf {
+	struct device		*dev;
+	const char		*name;
+
+	struct ion_client	*client;
+
+	unsigned long		align;
+	bool			contig;
+	bool			sharable;
+	bool			cacheable;
+	bool			use_mmu;
+	atomic_t		mmu_enable;
+
+	spinlock_t		slock;
+};
+
+struct vb2_ion_buf {
+	struct vm_area_struct		*vma;
+	struct vb2_ion_conf		*conf;
+	struct vb2_vmarea_handler	handler;
+
+	struct ion_handle		*handle;	/* Kernel space */
+	int				fd;		/* User space */
+
+	dma_addr_t			kva;
+	dma_addr_t			dva;
+	size_t				offset;
+	unsigned long			size;
+
+	struct scatterlist		*sg;
+	int				nents;
+
+	atomic_t			ref;
+
+	bool				cacheable;
+};
+#endif
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void fimc_is_mem_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+	/*
+	 * virtual & phsical addrees mapped directly, so we can convert
+	 * the address just using offset
+	 */
+	paddr = __pa((unsigned long)start_addr);
+	outer_clean_range(paddr, paddr + size);
+}
+
+void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	paddr = __pa((unsigned long)start_addr);
+	outer_inv_range(paddr, paddr + size);
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+}
+
+int fimc_is_init_mem_mgr(struct fimc_is_dev *dev)
+{
+	struct cma_info mem_info;
+	int err;
+
+	/* Alloc FW memory */
+	err = cma_info(&mem_info, &dev->pdev->dev, FIMC_IS_MEM_FW);
+	if (err) {
+		dev_err(&dev->pdev->dev, "%s: get cma info failed\n", __func__);
+		return -EINVAL;
+	}
+	printk(KERN_INFO "%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	dev->mem.size = mem_info.total_size;
+	dev->mem.base = (dma_addr_t)cma_alloc
+		(&dev->pdev->dev, FIMC_IS_MEM_FW, (size_t)dev->mem.size, 0);
+	dev->is_p_region =
+		(struct is_region *)(phys_to_virt(dev->mem.base +
+				FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE));
+	dev->is_shared_region =
+		(struct is_share_region *)(phys_to_virt(dev->mem.base +
+				FIMC_IS_SHARED_REGION_ADDR));
+	memset((void *)dev->is_p_region, 0,
+		(unsigned long)sizeof(struct is_region));
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	printk(KERN_INFO "ctrl->mem.base = 0x%x\n", dev->mem.base);
+	printk(KERN_INFO "ctrl->mem.size = 0x%x\n", dev->mem.size);
+
+	if (dev->mem.size >= (FIMC_IS_A5_MEM_SIZE + FIMC_IS_EXTRA_MEM_SIZE)) {
+		dev->mem.fw_ref_base =
+				dev->mem.base + FIMC_IS_A5_MEM_SIZE + 0x1000;
+		dev->mem.setfile_ref_base =
+				dev->mem.base + FIMC_IS_A5_MEM_SIZE + 0x1000
+						+ FIMC_IS_EXTRA_FW_SIZE;
+		printk(KERN_INFO "ctrl->mem.fw_ref_base = 0x%x\n",
+							dev->mem.fw_ref_base);
+		printk(KERN_INFO "ctrl->mem.setfile_ref_base = 0x%x\n",
+						dev->mem.setfile_ref_base);
+	} else {
+		dev->mem.fw_ref_base = 0;
+		dev->mem.setfile_ref_base = 0;
+	}
+#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER
+	err = cma_info(&mem_info, &dev->pdev->dev, FIMC_IS_MEM_ISP_BUF);
+	printk(KERN_INFO "%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		dev_err(&dev->pdev->dev, "%s: get cma info failed\n", __func__);
+		return -EINVAL;
+	}
+	dev->alloc_ctx = dev->vb2->init(dev);
+	if (IS_ERR(dev->alloc_ctx))
+		return PTR_ERR(dev->alloc_ctx);
+#endif
+	return 0;
+}
+
+#elif defined(CONFIG_VIDEOBUF2_ION)
+struct vb2_mem_ops *fimc_is_mem_ops(void)
+{
+	return (struct vb2_mem_ops *)&vb2_ion_memops;
+}
+
+void *fimc_is_mem_init(struct device *dev)
+{
+	struct vb2_ion vb2_ion;
+	void **alloc_ctxes;
+	struct vb2_drv vb2_drv = {0, };
+
+	/* TODO */
+	vb2_ion.name = FIMC_IS_ION_NAME;
+	vb2_ion.dev = dev;
+	vb2_ion.cacheable = true;
+	vb2_ion.align = SZ_4K;
+	vb2_ion.contig = false;
+	vb2_drv.use_mmu = true;
+
+	alloc_ctxes = (void **)vb2_ion_init(&vb2_ion, &vb2_drv);
+	return alloc_ctxes;
+}
+
+void fimc_is_mem_init_mem_cleanup(void *alloc_ctxes)
+{
+	vb2_ion_cleanup(alloc_ctxes);
+}
+
+void fimc_is_mem_resume(void *alloc_ctxes)
+{
+	vb2_ion_resume(alloc_ctxes);
+}
+
+void fimc_is_mem_suspend(void *alloc_ctxes)
+{
+	vb2_ion_suspend(alloc_ctxes);
+}
+
+int fimc_is_cache_flush(struct vb2_buffer *vb,
+				const void *start_addr, unsigned long size)
+{
+	return vb2_ion_cache_flush(vb, 1);
+}
+
+int fimc_is_cache_inv(struct vb2_buffer *vb,
+				const void *start_addr, unsigned long size)
+{
+	return vb2_ion_cache_inv(vb, 1);
+}
+
+/* Allocate firmware */
+int fimc_is_alloc_firmware(struct fimc_is_dev *dev)
+{
+	void *fimc_is_bitproc_buf;
+	dbg("Allocating memory for FIMC-IS firmware.\n");
+	fimc_is_bitproc_buf =
+		vb2_ion_memops.alloc(dev->alloc_ctx_fw, FIMC_IS_A5_MEM_SIZE);
+	if (IS_ERR(fimc_is_bitproc_buf)) {
+		fimc_is_bitproc_buf = 0;
+		printk(KERN_ERR "Allocating bitprocessor buffer failed\n");
+		return -ENOMEM;
+	}
+
+	dev->mem.dvaddr = (size_t)vb2_ion_memops.cookie(fimc_is_bitproc_buf);
+	if (dev->mem.dvaddr  & FIMC_IS_FW_BASE_MASK) {
+		err("The base memory is not aligned to 64MB.\n");
+		vb2_ion_memops.put(fimc_is_bitproc_buf);
+		dev->mem.dvaddr = 0;
+		fimc_is_bitproc_buf = 0;
+		return -EIO;
+	}
+	dbg("Device vaddr = %08x , size = %08x\n",
+				dev->mem.dvaddr, FIMC_IS_A5_MEM_SIZE);
+
+	dev->mem.kvaddr = vb2_ion_memops.vaddr(fimc_is_bitproc_buf);
+	if (!dev->mem.kvaddr) {
+		err("Bitprocessor memory remap failed\n");
+		vb2_ion_memops.put(fimc_is_bitproc_buf);
+		dev->mem.dvaddr = 0;
+		fimc_is_bitproc_buf = 0;
+		return -EIO;
+	}
+	dbg("Virtual address for FW: %08lx\n",
+			(long unsigned int)dev->mem.kvaddr);
+	dbg("Physical address for FW: %08lx\n",
+			(long unsigned int)virt_to_phys(dev->mem.kvaddr));
+	dev->mem.bitproc_buf = fimc_is_bitproc_buf;
+	dev->mem.vb2_buf.planes[0].mem_priv = fimc_is_bitproc_buf;
+
+	is_vb = &dev->mem.vb2_buf;
+	buf_start = dev->mem.kvaddr;
+	return 0;
+}
+
+void fimc_is_mem_cache_clean(const void *start_addr, unsigned long size)
+{
+	struct vb2_ion_buf *buf;
+	struct scatterlist *sg;
+	int i;
+	off_t offset;
+
+	if (start_addr < buf_start) {
+		err("Start address error\n");
+		return;
+	}
+	size--;
+
+	offset = start_addr - buf_start;
+
+	buf = (struct vb2_ion_buf *)is_vb->planes[0].mem_priv;
+	dma_sync_sg_for_device(buf->conf->dev, buf->sg, buf->nents,
+							DMA_BIDIRECTIONAL);
+}
+
+void fimc_is_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	struct vb2_ion_buf *buf;
+	struct scatterlist *sg;
+	int i;
+	off_t offset;
+
+	if (start_addr < buf_start) {
+		err("Start address error\n");
+		return;
+	}
+
+	offset = start_addr - buf_start;
+
+	buf = (struct vb2_ion_buf *)is_vb->planes[0].mem_priv;
+	for_each_sg(buf->sg, sg, buf->nents, i) {
+		phys_addr_t start, end;
+
+		if (offset >= sg_dma_len(sg)) {
+			offset -= sg_dma_len(sg);
+			continue;
+		}
+
+		start = sg_phys(sg);
+		end = start + sg_dma_len(sg);
+
+		dmac_flush_range(phys_to_virt(start),
+				 phys_to_virt(end));
+		outer_flush_range(start, end);	/* L2 */
+		if (size == 0)
+			break;
+	}
+}
+
+int fimc_is_init_mem_mgr(struct fimc_is_dev *dev)
+{
+	int ret;
+	dev->alloc_ctx_fw = (struct vb2_alloc_ctx *)
+			fimc_is_mem_init(&dev->pdev->dev);
+	if (IS_ERR(dev->alloc_ctx_fw)) {
+		err("Couldn't prepare allocator FW ctx.\n");
+		return PTR_ERR(dev->alloc_ctx_fw);
+	}
+	ret = fimc_is_alloc_firmware(dev);
+	if (ret) {
+		err("Couldn't alloc for FIMC-IS firmware\n");
+		return -EINVAL;
+	}
+	memset(dev->mem.kvaddr, 0, FIMC_IS_A5_MEM_SIZE);
+	dev->is_p_region =
+		(struct is_region *)(dev->mem.kvaddr +
+			FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE);
+	if (fimc_is_cache_flush(&dev->mem.vb2_buf,
+			(void *)dev->is_p_region, IS_PARAM_SIZE)) {
+		err("fimc_is_cache_flush-Err\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-param.h b/drivers/media/video/exynos/fimc-is/fimc-is-param.h
new file mode 100644
index 0000000..9383c4a
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-param.h
@@ -0,0 +1,1701 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Parameter region
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef FIMC_IS_PARAMS_H_
+#define FIMC_IS_PARAMS_H_
+
+#define IS_REGION_VER 122  /* IS REGION VERSION 1.22 */
+
+/* MACROs */
+#define IS_SET_PARAM_BIT(dev, num) \
+	(num >= 32 ? set_bit((num-32), &dev->p_region_index2) \
+		: set_bit(num, &dev->p_region_index1))
+#define IS_INC_PARAM_NUM(dev)		atomic_inc(&dev->p_region_num)
+
+#define IS_PARAM_GLOBAL		(dev->is_p_region->parameter.global)
+#define IS_PARAM_ISP		(dev->is_p_region->parameter.isp)
+#define IS_PARAM_DRC		(dev->is_p_region->parameter.drc)
+#define IS_PARAM_FD		(dev->is_p_region->parameter.fd)
+#define IS_HEADER		(dev->is_p_region->header)
+#define IS_FACE			(dev->is_p_region->face)
+#define IS_SHARED		(dev->is_shared_region)
+#define IS_PARAM_SIZE		(FIMC_IS_REGION_SIZE+1)
+
+/* Global control */
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, x) \
+		(dev->is_p_region->parameter.global.shotmode.cmd = x)
+#define IS_SET_PARAM_GLOBAL_SHOTMODE_SKIPFRAMES(dev, x) \
+		(dev->is_p_region->parameter.global.shotmode.skip_frames = x)
+
+/* Sensor control */
+#define IS_SENSOR_SET_FRAME_RATE(dev, x) \
+		(dev->is_p_region->parameter.sensor.frame_rate.frame_rate = x)
+
+/* ISP Macros */
+#define IS_ISP_SET_PARAM_CONTROL_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.control.cmd = x)
+#define IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, x) \
+		(dev->is_p_region->parameter.isp.control.bypass = x)
+#define IS_ISP_SET_PARAM_CONTROL_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.control.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.format = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.order = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_offset_x = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_offset_y = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_width = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.crop_height = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.frametime_min = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.frametime_max = x)
+#define IS_ISP_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT1_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT1_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_input.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_INPUT2_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.width = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.height = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.format = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.plane = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.order = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_INPUT2_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_input.err = x)
+
+#define IS_ISP_SET_PARAM_AA_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.cmd = x)
+#define IS_ISP_SET_PARAM_AA_TARGET(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.target = x)
+#define IS_ISP_SET_PARAM_AA_MODE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.mode = x)
+#define IS_ISP_SET_PARAM_AA_SCENE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.scene = x)
+#define IS_ISP_SET_PARAM_AA_SLEEP(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.sleep = x)
+#define IS_ISP_SET_PARAM_AA_FACE(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.face = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_X(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.touch_x = x)
+#define IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.touch_y = x)
+#define IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.manual_af_setting = x)
+#define IS_ISP_SET_PARAM_AA_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.aa.err = x)
+
+#define IS_ISP_SET_PARAM_FLASH_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.cmd = x)
+#define IS_ISP_SET_PARAM_FLASH_REDEYE(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.redeye = x)
+#define IS_ISP_SET_PARAM_FLASH_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.flash.err = x)
+
+#define IS_ISP_SET_PARAM_AWB_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.cmd = x)
+#define IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.illumination = x)
+#define IS_ISP_SET_PARAM_AWB_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.awb.err = x)
+
+#define IS_ISP_SET_PARAM_EFFECT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.effect.cmd = x)
+#define IS_ISP_SET_PARAM_EFFECT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.effect.err = x)
+
+#define IS_ISP_SET_PARAM_ISO_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.cmd = x)
+#define IS_ISP_SET_PARAM_ISO_VALUE(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.value = x)
+#define IS_ISP_SET_PARAM_ISO_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.iso.err = x)
+
+#define IS_ISP_SET_PARAM_ADJUST_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.cmd = x)
+#define IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.contrast = x)
+#define IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.saturation = x)
+#define IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.sharpness = x)
+#define IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.exposure = x)
+#define IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.brightness = x)
+#define IS_ISP_SET_PARAM_ADJUST_HUE(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.hue = x)
+#define IS_ISP_SET_PARAM_ADJUST_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.adjust.err = x)
+
+#define IS_ISP_SET_PARAM_METERING_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.cmd = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_pos_x = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_pos_y = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_width = x)
+#define IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.win_height = x)
+#define IS_ISP_SET_PARAM_METERING_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.metering.err = x)
+
+#define IS_ISP_SET_PARAM_AFC_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.cmd = x)
+#define IS_ISP_SET_PARAM_AFC_MANUAL(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.manual = x)
+#define IS_ISP_SET_PARAM_AFC_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.afc.err = x)
+
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.cmd = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.width = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.height = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.format = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.order = x)
+#define IS_ISP_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.otf_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_NUMBER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_BUFFER_ADDRESS(dev, x) \
+	(dev->is_p_region->parameter.isp.dma1_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_NODIFY_DMA_DONE(dev, x) \
+	(dev->is_p_region->parameter.isp.dma1_output.notify_dma_done = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT1_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma1_output.err = x)
+
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.cmd = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.width = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.height = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.format = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.bitwidth = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.plane = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.order = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.buffer_number = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.buffer_address = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_NODIFY_DMA_DONE(dev, x) \
+	(dev->is_p_region->parameter.isp.dma2_output.notify_dma_done = x)
+#define IS_ISP_SET_PARAM_DMA_OUTPUT2_ERR(dev, x) \
+		(dev->is_p_region->parameter.isp.dma2_output.err = x)
+
+/* DRC Macros */
+#define IS_DRC_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.control.cmd = x)
+#define IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.drc.control.bypass = x)
+#define IS_DRC_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.control.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.width = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.height = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.format = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.order = x)
+#define IS_DRC_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_input.err = x)
+
+#define IS_DRC_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.cmd = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.width = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.height = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.format = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.bitwidth = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.plane = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.order = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.drc.dma_input.buffer_number = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.drc.dma_input.buffer_address = x)
+#define IS_DRC_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.dma_input.err = x)
+
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.cmd = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.width = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.height = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.format = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.bitwidth = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.order = x)
+#define IS_DRC_SET_PARAM_OTF_OUTPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.drc.otf_output.err = x)
+
+#define IS_DRC_GET_PARAM_OTF_OUTPUT_WIDTH(dev, x) \
+	(x = dev->is_p_region->parameter.drc.otf_output.width)
+#define IS_DRC_GET_PARAM_OTF_OUTPUT_HEIGHT(dev, x) \
+	(x = dev->is_p_region->parameter.drc.otf_output.height)
+/* FD Macros */
+#define IS_FD_SET_PARAM_CONTROL_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.control.cmd = x)
+#define IS_FD_SET_PARAM_CONTROL_BYPASS(dev, x) \
+	(dev->is_p_region->parameter.fd.control.bypass = x)
+#define IS_FD_SET_PARAM_CONTROL_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.control.err = x)
+
+#define IS_FD_SET_PARAM_OTF_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.cmd = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.width = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.height = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.format = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.bitwidth = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.order = x)
+#define IS_FD_SET_PARAM_OTF_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.otf_input.err = x)
+
+#define IS_FD_SET_PARAM_DMA_INPUT_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.cmd = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_WIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.width = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_HEIGHT(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.height = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_FORMAT(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.format = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BITWIDTH(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.bitwidth = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_PLANE(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.plane = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ORDER(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.order = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERNUM(dev, x) \
+		(dev->is_p_region->parameter.fd.dma_input.buffer_number = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_BUFFERADDR(dev, x) \
+		(dev->is_p_region->parameter.fd.dma_input.buffer_address = x)
+#define IS_FD_SET_PARAM_DMA_INPUT_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.dma_input.err = x)
+
+#define IS_FD_SET_PARAM_FD_CONFIG_CMD(dev, x) \
+	(dev->is_p_region->parameter.fd.config.cmd = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev, x) \
+	(dev->is_p_region->parameter.fd.config.max_number = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.roll_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.yaw_angle = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.smile_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.blink_mode = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev, x) \
+	(dev->is_p_region->parameter.fd.config.eye_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev, x) \
+	(dev->is_p_region->parameter.fd.config.mouth_detect = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev, x) \
+	(dev->is_p_region->parameter.fd.config.orientation = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev, x) \
+	(dev->is_p_region->parameter.fd.config.orientation_value = x)
+#define IS_FD_SET_PARAM_FD_CONFIG_ERR(dev, x) \
+	(dev->is_p_region->parameter.fd.config.err = x)
+
+#define IS_SENSOR_SET_TUNE_EXPOSURE(dev, x) \
+	(dev->is_p_region->tune.sensor.exposure = x)
+#define IS_SENSOR_SET_TUNE_ANALOG_GAIN(dev, x) \
+	(dev->is_p_region->tune.sensor.analog_gain = x)
+#define IS_SENSOR_SET_TUNE_FRAME_RATE(dev, x) \
+	(dev->is_p_region->tune.sensor.frame_rate = x)
+#define IS_SENSOR_SET_TUNE_ACTUATOR_POSITION(dev, x) \
+	(dev->is_p_region->tune.sensor.actuator_position = x)
+
+#ifndef BIT0
+#define  BIT0     0x00000001
+#define  BIT1     0x00000002
+#define  BIT2     0x00000004
+#define  BIT3     0x00000008
+#define  BIT4     0x00000010
+#define  BIT5     0x00000020
+#define  BIT6     0x00000040
+#define  BIT7     0x00000080
+#define  BIT8     0x00000100
+#define  BIT9     0x00000200
+#define  BIT10    0x00000400
+#define  BIT11    0x00000800
+#define  BIT12    0x00001000
+#define  BIT13    0x00002000
+#define  BIT14    0x00004000
+#define  BIT15    0x00008000
+#define  BIT16    0x00010000
+#define  BIT17    0x00020000
+#define  BIT18    0x00040000
+#define  BIT19    0x00080000
+#define  BIT20    0x00100000
+#define  BIT21    0x00200000
+#define  BIT22    0x00400000
+#define  BIT23    0x00800000
+#define  BIT24    0x01000000
+#define  BIT25    0x02000000
+#define  BIT26    0x04000000
+#define  BIT27    0x08000000
+#define  BIT28    0x10000000
+#define  BIT29    0x20000000
+#define  BIT30    0x40000000
+#define  BIT31    0x80000000
+#define  BIT32    0x0000000100000000ULL
+#define  BIT33    0x0000000200000000ULL
+#define  BIT34    0x0000000400000000ULL
+#define  BIT35    0x0000000800000000ULL
+#define  BIT36    0x0000001000000000ULL
+#define  BIT37    0x0000002000000000ULL
+#define  BIT38    0x0000004000000000ULL
+#define  BIT39    0x0000008000000000ULL
+#define  BIT40    0x0000010000000000ULL
+#define  BIT41    0x0000020000000000ULL
+#define  BIT42    0x0000040000000000ULL
+#define  BIT43    0x0000080000000000ULL
+#define  BIT44    0x0000100000000000ULL
+#define  BIT45    0x0000200000000000ULL
+#define  BIT46    0x0000400000000000ULL
+#define  BIT47    0x0000800000000000ULL
+#define  BIT48    0x0001000000000000ULL
+#define  BIT49    0x0002000000000000ULL
+#define  BIT50    0x0004000000000000ULL
+#define  BIT51    0x0008000000000000ULL
+#define  BIT52    0x0010000000000000ULL
+#define  BIT53    0x0020000000000000ULL
+#define  BIT54    0x0040000000000000ULL
+#define  BIT55    0x0080000000000000ULL
+#define  BIT56    0x0100000000000000ULL
+#define  BIT57    0x0200000000000000ULL
+#define  BIT58    0x0400000000000000ULL
+#define  BIT59    0x0800000000000000ULL
+#define  BIT60    0x1000000000000000ULL
+#define  BIT61    0x2000000000000000ULL
+#define  BIT62    0x4000000000000000ULL
+#define  BIT63    0x8000000000000000ULL
+#define  INC_BIT(bit) (bit<<1)
+#define  INC_NUM(bit) (bit + 1)
+#endif
+
+#define MAGIC_NUMBER 0x01020304
+
+#define PARAMETER_MAX_SIZE    64  /* in byte */
+#define PARAMETER_MAX_MEMBER  (PARAMETER_MAX_SIZE/4)
+
+enum is_entry {
+	ENTRY_GLOBAL,
+	ENTRY_SENSOR,
+	ENTRY_BUFFER,
+	ENTRY_ISP,
+	ENTRY_DRC,
+	ENTRY_SCALERC,
+	ENTRY_ODC,
+	ENTRY_DIS,
+	ENTRY_TDNR,
+	ENTRY_SCALERP,
+	ENTRY_LHFD, /* 10 */
+	ENTRY_END
+};
+
+enum is_param_set_bit {
+	PARAM_GLOBAL_SHOTMODE = 0,
+	PARAM_SENSOR_CONTROL,
+	PARAM_SENSOR_OTF_OUTPUT,
+	PARAM_SENSOR_FRAME_RATE,
+	PARAM_BUFFER_CONTROL,
+	PARAM_BUFFER_OTF_INPUT,
+	PARAM_BUFFER_OTF_OUTPUT,
+	PARAM_ISP_CONTROL,
+	PARAM_ISP_OTF_INPUT,
+	PARAM_ISP_DMA1_INPUT,
+	PARAM_ISP_DMA2_INPUT = 10,
+	PARAM_ISP_AA,
+	PARAM_ISP_FLASH,
+	PARAM_ISP_AWB,
+	PARAM_ISP_IMAGE_EFFECT,
+	PARAM_ISP_ISO,
+	PARAM_ISP_ADJUST,
+	PARAM_ISP_METERING,
+	PARAM_ISP_AFC,
+	PARAM_ISP_OTF_OUTPUT,
+	PARAM_ISP_DMA1_OUTPUT = 20,
+	PARAM_ISP_DMA2_OUTPUT,
+	PARAM_DRC_CONTROL,
+	PARAM_DRC_OTF_INPUT,
+	PARAM_DRC_DMA_INPUT,
+	PARAM_DRC_OTF_OUTPUT,
+	PARAM_SCALERC_CONTROL,
+	PARAM_SCALERC_OTF_INPUT,
+	PARAM_SCALERC_IMAGE_EFFECT,
+	PARAM_SCALERC_INPUT_CROP,
+	PARAM_SCALERC_OUTPUT_CROP = 30,
+	PARAM_SCALERC_OTF_OUTPUT,
+	PARAM_SCALERC_DMA_OUTPUT = 32,
+	PARAM_ODC_CONTROL,
+	PARAM_ODC_OTF_INPUT,
+	PARAM_ODC_OTF_OUTPUT,
+	PARAM_DIS_CONTROL,
+	PARAM_DIS_OTF_INPUT,
+	PARAM_DIS_OTF_OUTPUT,
+	PARAM_TDNR_CONTROL,
+	PARAM_TDNR_OTF_INPUT = 40,
+	PARAM_TDNR_1ST_FRAME,
+	PARAM_TDNR_OTF_OUTPUT,
+	PARAM_TDNR_DMA_OUTPUT,
+	PARAM_SCALERP_CONTROL,
+	PARAM_SCALERP_OTF_INPUT,
+	PARAM_SCALERP_IMAGE_EFFECT,
+	PARAM_SCALERP_INPUT_CROP,
+	PARAM_SCALERP_OUTPUT_CROP,
+	PARAM_SCALERP_ROTATION,
+	PARAM_SCALERP_FLIP = 50,
+	PARAM_SCALERP_OTF_OUTPUT,
+	PARAM_SCALERP_DMA_OUTPUT,
+	PARAM_FD_CONTROL,
+	PARAM_FD_OTF_INPUT,
+	PARAM_FD_DMA_INPUT,
+	PARAM_FD_CONFIG = 56,
+	PARAM_END,
+};
+
+#define ADDRESS_TO_OFFSET(start, end)	((uint32)end - (uint32)start)
+#define OFFSET_TO_NUM(offset)		((offset)>>6)
+#define IS_OFFSET_LOWBIT(offset)	(OFFSET_TO_NUM(offset) >= \
+						32 ? false : true)
+#define OFFSET_TO_BIT(offset) \
+		(IS_OFFSET_LOWBIT(offset) ? (1<<OFFSET_TO_NUM(offset)) \
+			: (1<<(OFFSET_TO_NUM(offset)-32))
+#define LOWBIT_OF_NUM(num)		(num >= 32 ? 0 : BIT0<<num)
+#define HIGHBIT_OF_NUM(num)		(num >= 32 ? BIT0<<(num-32) : 0)
+
+/* 0~31 */
+#define PARAM_GLOBAL_SHOTMODE		0
+#define PARAM_SENSOR_CONTROL		INC_NUM(PARAM_GLOBAL_SHOTMODE)
+#define PARAM_SENSOR_OTF_OUTPUT		INC_NUM(PARAM_SENSOR_CONTROL)
+#define PARAM_SENSOR_FRAME_RATE		INC_NUM(PARAM_SENSOR_OTF_OUTPUT)
+#define PARAM_BUFFER_CONTROL		INC_NUM(PARAM_SENSOR_FRAME_RATE)
+#define PARAM_BUFFER_OTF_INPUT		INC_NUM(PARAM_BUFFER_CONTROL)
+#define PARAM_BUFFER_OTF_OUTPUT		INC_NUM(PARAM_BUFFER_OTF_INPUT)
+#define PARAM_ISP_CONTROL		INC_NUM(PARAM_BUFFER_OTF_OUTPUT)
+#define PARAM_ISP_OTF_INPUT		INC_NUM(PARAM_ISP_CONTROL)
+#define PARAM_ISP_DMA1_INPUT		INC_NUM(PARAM_ISP_OTF_INPUT)
+#define PARAM_ISP_DMA2_INPUT		INC_NUM(PARAM_ISP_DMA1_INPUT)
+#define PARAM_ISP_AA			INC_NUM(PARAM_ISP_DMA2_INPUT)
+#define PARAM_ISP_FLASH			INC_NUM(PARAM_ISP_AA)
+#define PARAM_ISP_AWB			INC_NUM(PARAM_ISP_FLASH)
+#define PARAM_ISP_IMAGE_EFFECT		INC_NUM(PARAM_ISP_AWB)
+#define PARAM_ISP_ISO			INC_NUM(PARAM_ISP_IMAGE_EFFECT)
+#define PARAM_ISP_ADJUST		INC_NUM(PARAM_ISP_ISO)
+#define PARAM_ISP_METERING		INC_NUM(PARAM_ISP_ADJUST)
+#define PARAM_ISP_AFC			INC_NUM(PARAM_ISP_METERING)
+#define PARAM_ISP_OTF_OUTPUT		INC_NUM(PARAM_ISP_AFC)
+#define PARAM_ISP_DMA1_OUTPUT		INC_NUM(PARAM_ISP_OTF_OUTPUT)
+#define PARAM_ISP_DMA2_OUTPUT		INC_NUM(PARAM_ISP_DMA1_OUTPUT)
+#define PARAM_DRC_CONTROL		INC_NUM(PARAM_ISP_DMA2_OUTPUT)
+#define PARAM_DRC_OTF_INPUT		INC_NUM(PARAM_DRC_CONTROL)
+#define PARAM_DRC_DMA_INPUT		INC_NUM(PARAM_DRC_OTF_INPUT)
+#define PARAM_DRC_OTF_OUTPUT		INC_NUM(PARAM_DRC_DMA_INPUT)
+#define PARAM_SCALERC_CONTROL		INC_NUM(PARAM_DRC_OTF_OUTPUT)
+#define PARAM_SCALERC_OTF_INPUT		INC_NUM(PARAM_SCALERC_CONTROL)
+#define PARAM_SCALERC_IMAGE_EFFECT	INC_NUM(PARAM_SCALERC_OTF_INPUT)
+#define PARAM_SCALERC_INPUT_CROP	INC_NUM(PARAM_SCALERC_IMAGE_EFFECT)
+#define PARAM_SCALERC_OUTPUT_CROP	INC_NUM(PARAM_SCALERC_INPUT_CROP)
+#define PARAM_SCALERC_OTF_OUTPUT	INC_NUM(PARAM_SCALERC_OUTPUT_CROP)
+
+/* 32~63 */
+#define PARAM_SCALERC_DMA_OUTPUT	INC_NUM(PARAM_SCALERC_OTF_OUTPUT)
+#define PARAM_ODC_CONTROL		INC_NUM(PARAM_SCALERC_DMA_OUTPUT)
+#define PARAM_ODC_OTF_INPUT		INC_NUM(PARAM_ODC_CONTROL)
+#define PARAM_ODC_OTF_OUTPUT		INC_NUM(PARAM_ODC_OTF_INPUT)
+#define PARAM_DIS_CONTROL		INC_NUM(PARAM_ODC_OTF_OUTPUT)
+#define PARAM_DIS_OTF_INPUT		INC_NUM(PARAM_DIS_CONTROL)
+#define PARAM_DIS_OTF_OUTPUT		INC_NUM(PARAM_DIS_OTF_INPUT)
+#define PARAM_TDNR_CONTROL		INC_NUM(PARAM_DIS_OTF_OUTPUT)
+#define PARAM_TDNR_OTF_INPUT		INC_NUM(PARAM_TDNR_CONTROL)
+#define PARAM_TDNR_1ST_FRAME		INC_NUM(PARAM_TDNR_OTF_INPUT)
+#define PARAM_TDNR_OTF_OUTPUT		INC_NUM(PARAM_TDNR_1ST_FRAME)
+#define PARAM_TDNR_DMA_OUTPUT		INC_NUM(PARAM_TDNR_OTF_OUTPUT)
+#define PARAM_SCALERP_CONTROL		INC_NUM(PARAM_TDNR_DMA_OUTPUT)
+#define PARAM_SCALERP_OTF_INPUT		INC_NUM(PARAM_SCALERP_CONTROL)
+#define PARAM_SCALERP_IMAGE_EFFECT	INC_NUM(PARAM_SCALERP_OTF_INPUT)
+#define PARAM_SCALERP_INPUT_CROP	INC_NUM(PARAM_SCALERP_IMAGE_EFFECT)
+#define PARAM_SCALERP_OUTPUT_CROP	INC_NUM(PARAM_SCALERP_INPUT_CROP)
+#define PARAM_SCALERP_ROTATION		INC_NUM(PARAM_SCALERP_OUTPUT_CROP)
+#define PARAM_SCALERP_FLIP		INC_NUM(PARAM_SCALERP_ROTATION)
+#define PARAM_SCALERP_OTF_OUTPUT	INC_NUM(PARAM_SCALERP_FLIP)
+#define PARAM_SCALERP_DMA_OUTPUT	INC_NUM(PARAM_SCALERP_OTF_OUTPUT)
+#define PARAM_FD_CONTROL		INC_NUM(PARAM_SCALERP_DMA_OUTPUT)
+#define PARAM_FD_OTF_INPUT		INC_NUM(PARAM_FD_CONTROL)
+#define PARAM_FD_DMA_INPUT		INC_NUM(PARAM_FD_OTF_INPUT)
+#define PARAM_FD_CONFIG			INC_NUM(PARAM_FD_DMA_INPUT)
+#define PARAM_END			INC_NUM(PARAM_FD_CONFIG)
+
+#define PARAM_STRNUM_GLOBAL		(PARAM_GLOBAL_SHOTMODE)
+#define PARAM_RANGE_GLOBAL		1
+#define PARAM_STRNUM_SENSOR		(PARAM_SENSOR_BYPASS)
+#define PARAM_RANGE_SENSOR		3
+#define PARAM_STRNUM_BUFFER		(PARAM_BUFFER_BYPASS)
+#define PARAM_RANGE_BUFFER		3
+#define PARAM_STRNUM_ISP		(PARAM_ISP_BYPASS)
+#define PARAM_RANGE_ISP			15
+#define PARAM_STRNUM_DRC		(PARAM_DRC_BYPASS)
+#define PARAM_RANGE_DRC			4
+#define PARAM_STRNUM_SCALERC		(PARAM_SCALERC_BYPASS)
+#define PARAM_RANGE_SCALERC		7
+#define PARAM_STRNUM_ODC		(PARAM_ODC_BYPASS)
+#define PARAM_RANGE_ODC			3
+#define PARAM_STRNUM_DIS		(PARAM_DIS_BYPASS)
+#define PARAM_RANGE_DIS			3
+#define PARAM_STRNUM_TDNR		(PARAM_TDNR_BYPASS)
+#define PARAM_RANGE_TDNR		5
+#define PARAM_STRNUM_SCALERP		(PARAM_SCALERP_BYPASS)
+#define PARAM_RANGE_SCALERP		9
+#define PARAM_STRNUM_LHFD		(PARAM_FD_BYPASS)
+#define PARAM_RANGE_LHFD		4
+
+/* Enumerations
+*
+*/
+/* ----------------------  INTR map-------------------------------- */
+enum interrupt_map {
+	INTR_GENERAL = 0,
+	INTR_FRAME_DONE_ISP = 1,
+	INTR_FRAME_DONE_SCALERC = 2,
+	INTR_FRAME_DONE_TDNR = 3,
+	INTR_FRAME_DONE_SCALERP = 4
+};
+
+/* ----------------------  Input  ----------------------------------- */
+enum control_command {
+	CONTROL_COMMAND_STOP	= 0,
+	CONTROL_COMMAND_START	= 1
+};
+
+enum bypass_command {
+	CONTROL_BYPASS_DISABLE		= 0,
+	CONTROL_BYPASS_ENABLE		= 1
+};
+
+enum control_error {
+	CONTROL_ERROR_NO			= 0
+};
+
+enum otf_input_command {
+	OTF_INPUT_COMMAND_DISABLE	= 0,
+	OTF_INPUT_COMMAND_ENABLE	= 1
+};
+
+enum otf_input_format {
+	OTF_INPUT_FORMAT_BAYER		= 0, /* 1 Channel */
+	OTF_INPUT_FORMAT_YUV444		= 1, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV422		= 2, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV420		= 3, /* 3 Channel */
+	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
+	OTF_INPUT_FORMAT_BAYER_DMA	= 11,
+};
+
+enum otf_input_bitwidth {
+	OTF_INPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_INPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_INPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_INPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_INPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_input_order {
+	OTF_INPUT_ORDER_BAYER_GR_BG         = 0,
+};
+
+enum otf_intput_error {
+	OTF_INPUT_ERROR_NO		= 0 /* Input setting is done */
+};
+
+enum dma_input_command {
+	DMA_INPUT_COMMAND_DISABLE	= 0,
+	DMA_INPUT_COMMAND_ENABLE	= 1
+};
+
+enum dma_inut_format {
+	DMA_INPUT_FORMAT_BAYER		= 0,
+	DMA_INPUT_FORMAT_YUV444		= 1,
+	DMA_INPUT_FORMAT_YUV422		= 2,
+	DMA_INPUT_FORMAT_YUV420		= 3,
+};
+
+enum dma_input_bitwidth {
+	DMA_INPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_INPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_INPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_INPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_INPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_input_plane {
+	DMA_INPUT_PLANE_3	= 3,
+	DMA_INPUT_PLANE_2	= 2,
+	DMA_INPUT_PLANE_1	= 1
+};
+
+enum dma_input_order {
+	/* (for DMA_INPUT_PLANE_3) */
+	DMA_INPUT_ORDER_NO	= 0,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CbCr	= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CrCb	= 2,
+	/* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
+	DMA_INPUT_ORDER_YCbCr	= 3,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YYCbCr	= 4,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCbYCr	= 5,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCrYCb	= 6,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CbYCrY	= 7,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CrYCbY	= 8,
+	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
+	DMA_INPUT_ORDER_GR_BG	= 9
+};
+
+enum dma_input_error {
+	DMA_INPUT_ERROR_NO	= 0 /*  DMA input setting is done */
+};
+
+/* ----------------------  Output  ----------------------------------- */
+enum otf_output_crop {
+	OTF_OUTPUT_CROP_DISABLE		= 0,
+	OTF_OUTPUT_CROP_ENABLE		= 1
+};
+
+enum otf_output_command {
+	OTF_OUTPUT_COMMAND_DISABLE	= 0,
+	OTF_OUTPUT_COMMAND_ENABLE	= 1
+};
+
+enum orf_output_format {
+	OTF_OUTPUT_FORMAT_YUV444	= 1,
+	OTF_OUTPUT_FORMAT_YUV422	= 2,
+	OTF_OUTPUT_FORMAT_YUV420	= 3,
+	OTF_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum otf_output_bitwidth {
+	OTF_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_output_order {
+	OTF_OUTPUT_ORDER_BAYER_GR_BG         = 0,
+};
+
+enum otf_output_error {
+	OTF_OUTPUT_ERROR_NO = 0 /* Output Setting is done */
+};
+
+enum dma_output_command {
+	DMA_OUTPUT_COMMAND_DISABLE	= 0,
+	DMA_OUTPUT_COMMAND_ENABLE	= 1
+};
+
+enum dma_output_format {
+	DMA_OUTPUT_FORMAT_BAYER		= 0,
+	DMA_OUTPUT_FORMAT_YUV444	= 1,
+	DMA_OUTPUT_FORMAT_YUV422	= 2,
+	DMA_OUTPUT_FORMAT_YUV420	= 3,
+	DMA_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum dma_output_bitwidth {
+	DMA_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_output_plane {
+	DMA_OUTPUT_PLANE_3		= 3,
+	DMA_OUTPUT_PLANE_2		= 2,
+	DMA_OUTPUT_PLANE_1		= 1
+};
+
+enum dma_output_order {
+	DMA_OUTPUT_ORDER_NO		= 0,
+	/* (for DMA_OUTPUT_PLANE_3) */
+	DMA_OUTPUT_ORDER_CbCr		= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_CrCb		= 2,
+	/* (only valid at DMA_OUTPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_YYCbCr		= 3,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCbYCr		= 4,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCrYCb		= 5,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbYCrY		= 6,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrYCbY		= 7,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCbCr		= 8,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrYCb		= 9,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CrCbY		= 10,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbYCr		= 11,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCrCb		= 12,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CbCrY		= 13,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_BGR		= 14,
+	/* (only valid at DMA_OUTPUT_FORMAT_RGB) */
+	DMA_OUTPUT_ORDER_GB_BG		= 15
+	/* (only valid at DMA_OUTPUT_FORMAT_BAYER) */
+};
+
+enum dma_output_notify_dma_done {
+	DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	= 0,
+	DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE	= 1,
+};
+
+enum dma_output_error {
+	DMA_OUTPUT_ERROR_NO		= 0 /* DMA output setting is done */
+};
+
+/* ----------------------  Global  ----------------------------------- */
+enum global_shotmode_error {
+	GLOBAL_SHOTMODE_ERROR_NO	= 0 /* shot-mode setting is done */
+};
+
+/* -------------------------  AA  ------------------------------------ */
+enum isp_lock_command {
+	ISP_AA_COMMAND_START	= 0,
+	ISP_AA_COMMAND_STOP	= 1
+};
+
+enum isp_lock_target {
+	ISP_AA_TARGET_AF	= 1,
+	ISP_AA_TARGET_AE	= 2,
+	ISP_AA_TARGET_AWB	= 4
+};
+
+enum isp_af_mode {
+	ISP_AF_MODE_MANUAL		= 0,
+	ISP_AF_MODE_SINGLE		= 1,
+	ISP_AF_MODE_CONTINUOUS		= 2,
+	ISP_AF_MODE_TOUCH		= 3,
+	ISP_AF_MODE_SLEEP		= 4,
+	ISP_AF_MODE_INIT		= 5,
+	ISP_AF_MODE_SET_CENTER_WINDOW	= 6,
+	ISP_AF_MODE_SET_TOUCH_WINDOW	= 7
+};
+
+enum isp_af_face {
+	ISP_AF_FACE_DISABLE		= 0,
+	ISP_AF_FACE_ENABLE		= 1
+};
+
+enum isp_af_scene {
+	ISP_AF_SCENE_NORMAL		= 0,
+	ISP_AF_SCENE_MACRO		= 1
+};
+
+enum isp_af_sleep {
+	ISP_AF_SLEEP_OFF		= 0,
+	ISP_AF_SLEEP_ON			= 1
+};
+
+enum isp_af_continuous {
+	ISP_AF_CONTINUOUS_DISABLE	= 0,
+	ISP_AF_CONTINUOUS_ENABLE	= 1
+};
+
+enum isp_af_error {
+	ISP_AF_ERROR_NO			= 0, /* AF mode change is done */
+	ISP_AF_EROOR_NO_LOCK_DONE	= 1  /* AF lock is done */
+};
+
+/* -------------------------  Flash  ------------------------------------- */
+enum isp_flash_command {
+	ISP_FLASH_COMMAND_DISABLE	= 0 ,
+	ISP_FLASH_COMMAND_MANUALON	= 1, /* (forced flash) */
+	ISP_FLASH_COMMAND_AUTO		= 2,
+	ISP_FLASH_COMMAND_TORCH		= 3  /* 3 sec */
+};
+
+enum isp_flash_redeye {
+	ISP_FLASH_REDEYE_DISABLE	= 0,
+	ISP_FLASH_REDEYE_ENABLE		= 1
+};
+
+enum isp_flash_error {
+	ISP_FLASH_ERROR_NO		= 0 /* Flash setting is done */
+};
+
+/* --------------------------  AWB  ------------------------------------ */
+enum isp_awb_command {
+	ISP_AWB_COMMAND_AUTO		= 0,
+	ISP_AWB_COMMAND_ILLUMINATION	= 1,
+	ISP_AWB_COMMAND_MANUAL		= 2
+};
+
+enum isp_awb_illumination {
+	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
+	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
+	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
+	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
+};
+
+enum isp_awb_error {
+	ISP_AWB_ERROR_NO		= 0 /* AWB setting is done */
+};
+
+/* --------------------------  Effect  ----------------------------------- */
+enum isp_imageeffect_command {
+	ISP_IMAGE_EFFECT_DISABLE		= 0,
+	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
+	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
+	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
+	ISP_IMAGE_EFFECT_SEPIA			= 4
+};
+
+enum isp_imageeffect_error {
+	ISP_IMAGE_EFFECT_ERROR_NO	= 0 /* Image effect setting is done */
+};
+
+/* ---------------------------  ISO  ------------------------------------ */
+enum isp_iso_command {
+	ISP_ISO_COMMAND_AUTO		= 0,
+	ISP_ISO_COMMAND_MANUAL		= 1
+};
+
+enum iso_error {
+	ISP_ISO_ERROR_NO		= 0 /* ISO setting is done */
+};
+
+/* --------------------------  Adjust  ----------------------------------- */
+enum iso_adjust_command {
+	ISP_ADJUST_COMMAND_AUTO			= 0,
+	ISP_ADJUST_COMMAND_MANUAL_CONTRAST	= (1 << 0),
+	ISP_ADJUST_COMMAND_MANUAL_SATURATION	= (1 << 1),
+	ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	= (1 << 2),
+	ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	= (1 << 3),
+	ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	= (1 << 4),
+	ISP_ADJUST_COMMAND_MANUAL_HUE		= (1 << 5),
+	ISP_ADJUST_COMMAND_MANUAL_ALL		= 0x7F,
+};
+
+enum isp_adjust_error {
+	ISP_ADJUST_ERROR_NO		= 0 /* Adjust setting is done */
+};
+
+/* -------------------------  Metering  ---------------------------------- */
+enum isp_metering_command {
+	ISP_METERING_COMMAND_AVERAGE	= 0,
+	ISP_METERING_COMMAND_SPOT	= 1,
+	ISP_METERING_COMMAND_MATRIX	= 2,
+	ISP_METERING_COMMAND_CENTER	= 3
+};
+
+enum isp_metering_error {
+	ISP_METERING_ERROR_NO	= 0 /* Metering setting is done */
+};
+
+/* --------------------------  AFC  ----------------------------------- */
+enum isp_afc_command {
+	ISP_AFC_COMMAND_DISABLE		= 0,
+	ISP_AFC_COMMAND_AUTO		= 1,
+	ISP_AFC_COMMAND_MANUAL		= 2
+};
+
+enum isp_afc_manual {
+	ISP_AFC_MANUAL_50HZ		= 50,
+	ISP_AFC_MANUAL_60HZ		= 60
+};
+
+/* ------------------------  SCENE MODE--------------------------------- */
+enum isp_scene_mode {
+	ISP_SCENE_NONE			= 0,
+	ISP_SCENE_PORTRAIT		= 1,
+	ISP_SCENE_LANDSCAPE		= 2,
+	ISP_SCENE_SPORTS		= 3,
+	ISP_SCENE_PARTYINDOOR		= 4,
+	ISP_SCENE_BEACHSNOW		= 5,
+	ISP_SCENE_SUNSET		= 6,
+	ISP_SCENE_DAWN			= 7,
+	ISP_SCENE_FALL			= 8,
+	ISP_SCENE_NIGHT			= 9,
+	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
+	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
+	ISP_SCENE_FIRE			= 12,
+	ISP_SCENE_TEXT			= 13,
+	ISP_SCENE_CANDLE		= 14
+};
+
+enum isp_afc_error {
+	ISP_AFC_ERROR_NO	= 0 /* AFC setting is done */
+};
+
+/* --------------------------  Scaler  --------------------------------- */
+enum scaler_imageeffect_command {
+	SCALER_IMAGE_EFFECT_COMMNAD_DISABLE	= 0,
+	SCALER_IMAGE_EFFECT_COMMNAD_ARBITRARY	= 1,
+	SCALER_IMAGE_EFFECT_COMMAND_NEGATIVE	= 2,
+	SCALER_IMAGE_EFFECT_COMMAND_ARTFREEZE	= 3,
+	SCALER_IMAGE_EFFECT_COMMAND_EMBOSSING	= 4,
+	SCALER_IMAGE_EFFECT_COMMAND_SILHOUETTE	= 5
+};
+
+enum scaler_imageeffect_error {
+	SCALER_IMAGE_EFFECT_ERROR_NO		= 0
+};
+
+enum scaler_crop_command {
+	SCALER_CROP_COMMAND_DISABLE		= 0,
+	SCALER_CROP_COMMAND_ENABLE		= 1
+};
+
+enum scaler_crop_error {
+	SCALER_CROP_ERROR_NO			= 0 /* crop setting is done */
+};
+
+enum scaler_scaling_command {
+	SCALER_SCALING_COMMNAD_DISABLE		= 0,
+	SCALER_SCALING_COMMAND_UP		= 1,
+	SCALER_SCALING_COMMAND_DOWN		= 2
+};
+
+enum scaler_dma_out_sel {
+	SCALER_DMA_OUT_IMAGE_EFFECT		= 0,
+	SCALER_DMA_OUT_SCALED			= 1,
+	SCALER_DMA_OUT_UNSCALED			= 2
+};
+
+enum scaler_scaling_error {
+	SCALER_SCALING_ERROR_NO			= 0
+};
+
+
+enum scaler_rotation_command {
+	SCALER_ROTATION_COMMAND_DISABLE		= 0,
+	SCALER_ROTATION_COMMAND_CLOCKWISE90	= 1
+};
+
+enum scaler_rotation_error {
+	SCALER_ROTATION_ERROR_NO		= 0
+};
+
+enum scaler_flip_command {
+	SCALER_FLIP_COMMAND_NORMAL		= 0,
+	SCALER_FLIP_COMMAND_X_MIRROR		= 1,
+	SCALER_FLIP_COMMAND_Y_MIRROR		= 2,
+	SCALER_FLIP_COMMAND_XY_MIRROR		= 3 /* (180 rotation) */
+};
+
+enum scaler_flip_error {
+	SCALER_FLIP_ERROR_NO			= 0 /* flip setting is done */
+};
+
+/* --------------------------  3DNR  ----------------------------------- */
+enum tdnr_1st_frame_command {
+	TDNR_1ST_FRAME_COMMAND_NOPROCESSING	= 0,
+	TDNR_1ST_FRAME_COMMAND_2DNR		= 1
+};
+
+enum tdnr_1st_frame_error {
+	TDNR_1ST_FRAME_ERROR_NO			= 0
+		/*1st frame setting is done*/
+};
+
+/* ----------------------------  FD  ------------------------------------- */
+enum fd_config_command {
+	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
+	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
+	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
+	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
+	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
+	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
+	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
+	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
+	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
+};
+
+enum fd_config_roll_angle {
+	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
+	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
+	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
+};
+
+enum fd_config_yaw_angle {
+	FD_CONFIG_YAW_ANGLE_0			= 0,
+	FD_CONFIG_YAW_ANGLE_45			= 1,
+	FD_CONFIG_YAW_ANGLE_90			= 2,
+	FD_CONFIG_YAW_ANGLE_45_90		= 3,
+};
+
+enum fd_config_smile_mode {
+	FD_CONFIG_SMILE_MODE_DISABLE		= 0,
+	FD_CONFIG_SMILE_MODE_ENABLE		= 1
+};
+
+enum fd_config_blink_mode {
+	FD_CONFIG_BLINK_MODE_DISABLE		= 0,
+	FD_CONFIG_BLINK_MODE_ENABLE		= 1
+};
+
+enum fd_config_eye_result {
+	FD_CONFIG_EYES_DETECT_DISABLE		= 0,
+	FD_CONFIG_EYES_DETECT_ENABLE		= 1
+};
+
+enum fd_config_mouth_result {
+	FD_CONFIG_MOUTH_DETECT_DISABLE		= 0,
+	FD_CONFIG_MOUTH_DETECT_ENABLE		= 1
+};
+
+enum fd_config_orientation {
+	FD_CONFIG_ORIENTATION_DISABLE		= 0,
+	FD_CONFIG_ORIENTATION_ENABLE		= 1
+};
+
+struct param_control {
+	u32	cmd;
+	u32	bypass;
+	u32	buffer_address;
+	u32	buffer_size;
+	u32	first_drop_frames; /* only valid at ISP */
+	u32	reserved[PARAMETER_MAX_MEMBER-6];
+	u32	err;
+};
+
+struct param_otf_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	crop_width;
+	u32	crop_height;
+	u32	frametime_min;
+	u32	frametime_max;
+	u32	reserved[PARAMETER_MAX_MEMBER-13];
+	u32	err;
+};
+
+struct param_dma_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	reserved[PARAMETER_MAX_MEMBER-10];
+	u32	err;
+};
+
+struct param_otf_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	reserved[PARAMETER_MAX_MEMBER-7];
+	u32	err;
+};
+
+struct param_dma_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	notify_dma_done;
+	u32	reserved[PARAMETER_MAX_MEMBER-11];
+	u32	err;
+};
+
+struct param_global_shotmode {
+	u32	cmd;
+	u32	skip_frames;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_sensor_framerate {
+	u32	frame_rate;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_aa {
+	u32	cmd;
+	u32	target;
+	u32	mode;
+	u32	scene;
+	u32	sleep;
+	u32	face;
+	u32	touch_x;
+	u32	touch_y;
+	u32	manual_af_setting;
+	u32	reserved[PARAMETER_MAX_MEMBER-10];
+	u32	err;
+};
+
+struct param_isp_flash {
+	u32	cmd;
+	u32	redeye;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_awb {
+	u32	cmd;
+	u32	illumination;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_imageeffect {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_iso {
+	u32	cmd;
+	u32	value;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_adjust {
+	u32	cmd;
+	s32	contrast;
+	s32	saturation;
+	s32	sharpness;
+	s32	exposure;
+	s32	brightness;
+	s32	hue;
+	u32	reserved[PARAMETER_MAX_MEMBER-8];
+	u32	err;
+};
+
+struct param_isp_metering {
+	u32	cmd;
+	u32	win_pos_x;
+	u32	win_pos_y;
+	u32	win_width;
+	u32	win_height;
+	u32	reserved[PARAMETER_MAX_MEMBER-6];
+	u32	err;
+};
+
+struct param_isp_afc {
+	u32	cmd;
+	u32	manual;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_scaler_imageeffect {
+	u32	cmd;
+	u32	arbitrary_cb;
+	u32	arbitrary_cr;
+	u32	reserved[PARAMETER_MAX_MEMBER-4];
+	u32	err;
+};
+
+struct param_scaler_input_crop {
+	u32	cmd;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	crop_width;
+	u32	crop_height;
+	u32	in_width;
+	u32	in_height;
+	u32	out_width;
+	u32	out_height;
+	u32	reserved[PARAMETER_MAX_MEMBER-10];
+	u32	err;
+};
+
+struct param_scaler_output_crop {
+	u32	cmd;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	crop_width;
+	u32	crop_height;
+	u32	out_format;
+	u32	reserved[PARAMETER_MAX_MEMBER-7];
+	u32	err;
+};
+
+struct param_scaler_rotation {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_scaler_flip {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_3dnr_1stframe {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_fd_config {
+	u32	cmd;
+	u32	max_number;
+	u32	roll_angle;
+	u32	yaw_angle;
+	u32	smile_mode;
+	u32	blink_mode;
+	u32	eye_detect;
+	u32	mouth_detect;
+	u32	orientation;
+	u32	orientation_value;
+	u32	reserved[PARAMETER_MAX_MEMBER-11];
+	u32	err;
+};
+
+struct global_param {
+	struct param_global_shotmode	shotmode; /* 0 */
+};
+
+/* To be added */
+struct sensor_param {
+	struct param_control		control;
+	struct param_otf_output		otf_output;
+	struct param_sensor_framerate	frame_rate;
+};
+
+struct buffer_param {
+	struct param_control	control;
+	struct param_otf_input	otf_input;
+	struct param_otf_output	otf_output;
+};
+
+struct isp_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma1_input;
+	struct param_dma_input		dma2_input;
+	struct param_isp_aa		aa;
+	struct param_isp_flash		flash;
+	struct param_isp_awb		awb;
+	struct param_isp_imageeffect	effect;
+	struct param_isp_iso		iso;
+	struct param_isp_adjust		adjust;
+	struct param_isp_metering	metering;
+	struct param_isp_afc		afc;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma1_output;
+	struct param_dma_output		dma2_output;
+};
+
+struct drc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma_input;
+	struct param_otf_output		otf_output;
+};
+
+struct scalerc_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_scaler_imageeffect		effect;
+	struct param_scaler_input_crop		input_crop;
+	struct param_scaler_output_crop		output_crop;
+	struct param_otf_output			otf_output;
+	struct param_dma_output			dma_output;
+};
+
+struct odc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct dis_param {
+	struct param_control		control;
+	struct param_otf_output		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct tdnr_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_3dnr_1stframe	frame;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma_output;
+};
+
+struct scalerp_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_scaler_imageeffect		effect;
+	struct param_scaler_input_crop		input_crop;
+	struct param_scaler_output_crop		output_crop;
+	struct param_scaler_rotation		rotation;
+	struct param_scaler_flip		flip;
+	struct param_otf_output			otf_output;
+	struct param_dma_output			dma_output;
+};
+
+struct fd_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_dma_input			dma_input;
+	struct param_fd_config			config;
+};
+
+struct is_param_region {
+	struct global_param	global;
+	struct sensor_param	sensor;
+	struct buffer_param	buf;
+	struct isp_param	isp;
+	struct drc_param	drc;
+	struct scalerc_param	scalerc;
+	struct odc_param	odc;
+	struct dis_param	dis;
+	struct tdnr_param	tdnr;
+	struct scalerp_param	scalerp;
+	struct fd_param		fd;
+};
+
+#define	NUMBER_OF_GAMMA_CURVE_POINTS	32
+
+struct is_tune_sensor {
+	u32 exposure;
+	u32 analog_gain;
+	u32 frame_rate;
+	u32 actuator_position;
+};
+
+struct is_tune_gammacurve {
+	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
+};
+
+struct is_tune_isp {
+	/* Brightness level : range 0~100, default : 7 */
+	u32 brightness_level;
+	/* Contrast level : range -127~127, default : 0 */
+	s32 contrast_level;
+	/* Saturation level : range -127~127, default : 0 */
+	s32 saturation_level;
+	s32 gamma_level;
+	struct is_tune_gammacurve gamma_curve[4];
+	/* Hue : range -127~127, default : 0 */
+	s32 hue;
+	/* Sharpness blur : range -127~127, default : 0 */
+	s32 sharpness_blur;
+	/* Despeckle : range -127~127, default : 0 */
+	s32 despeckle;
+	/* Edge color supression : range -127~127, default : 0 */
+	s32 edge_color_supression;
+	/* Noise reduction : range -127~127, default : 0 */
+	s32 noise_reduction;
+	/* (32*4 + 9)*4 = 548 bytes */
+};
+
+struct is_tune_region {
+	struct is_tune_sensor sensor;
+	struct is_tune_isp isp;
+};
+
+struct rational_t {
+	u32 num;
+	u32 den;
+};
+
+struct srational_t {
+	s32 num;
+	s32 den;
+};
+
+#define FLASH_FIRED_SHIFT	0
+#define FLASH_NOT_FIRED		0
+#define FLASH_FIRED		1
+
+#define FLASH_STROBE_SHIFT				1
+#define FLASH_STROBE_NO_DETECTION			0
+#define FLASH_STROBE_RESERVED				1
+#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED		2
+#define FLASH_STROBE_RETURN_LIGHT_DETECTED		3
+
+#define FLASH_MODE_SHIFT			3
+#define FLASH_MODE_UNKNOWN			0
+#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
+#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
+#define FLASH_MODE_AUTO_MODE			3
+
+#define FLASH_FUNCTION_SHIFT		5
+#define FLASH_FUNCTION_PRESENT		0
+#define FLASH_FUNCTION_NONE		1
+
+#define FLASH_RED_EYE_SHIFT		6
+#define FLASH_RED_EYE_DISABLED		0
+#define FLASH_RED_EYE_SUPPORTED		1
+
+enum apex_aperture_value {
+	F1_0		= 0,
+	F1_4		= 1,
+	F2_0		= 2,
+	F2_8		= 3,
+	F4_0		= 4,
+	F5_6		= 5,
+	F8_9		= 6,
+	F11_0		= 7,
+	F16_0		= 8,
+	F22_0		= 9,
+	F32_0		= 10,
+};
+
+struct exif_attribute {
+	struct rational_t exposure_time;
+	struct srational_t shutter_speed;
+	u32 iso_speed_rating;
+	u32 flash;
+	struct srational_t brightness;
+};
+
+struct is_frame_header {
+	u32 valid;
+	u32 bad_mark;
+	u32 captured;
+	u32 frame_number;
+	struct exif_attribute	exif;
+};
+
+struct is_fd_rect {
+	u32 offset_x;
+	u32 offset_y;
+	u32 width;
+	u32 height;
+};
+
+struct is_face_marker {
+	u32	frame_number;
+	struct is_fd_rect face;
+	struct is_fd_rect left_eye;
+	struct is_fd_rect right_eye;
+	struct is_fd_rect mouth;
+	u32	roll_angle;
+	u32	yaw_angle;
+	u32	confidence;
+	s32	smile_level;
+	s32	blink_level;
+};
+
+#define MAX_FRAME_COUNT		8
+#define MAX_FRAME_COUNT_PREVIEW	4
+#define MAX_FRAME_COUNT_CAPTURE	1
+#define MAX_FACE_COUNT		16
+
+#define MAX_SHARED_COUNT	500
+
+struct is_region {
+	struct is_param_region	parameter;
+	struct is_tune_region	tune;
+	struct is_frame_header	header[MAX_FRAME_COUNT];
+	struct is_face_marker	face[MAX_FACE_COUNT];
+	u32			shared[MAX_SHARED_COUNT];
+};
+
+struct is_debug_frame_descriptor {
+	u32	sensor_frame_time;
+	u32	sensor_exposure_time;
+	s32	sensor_analog_gain;
+	/* monitor for AA */
+	u32	req_lei;
+
+	u32	next_next_lei_exp;
+	u32	next_next_lei_a_gain;
+	u32	next_next_lei_d_gain;
+	u32	next_next_lei_statlei;
+	u32	next_next_lei_lei;
+
+	u32	dummy0;
+};
+
+#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM	(30*20)	/* 600 frames */
+#define MAX_VERSION_DISPLAY_BUF	32
+
+struct is_share_region {
+	u32	frame_time;
+	u32	exposure_time;
+	s32	analog_gain;
+
+	u32	r_gain;
+	u32	g_gain;
+	u32	b_gain;
+
+	u32	af_position;
+	u32	af_status;
+	/* 0 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_NOMESSAGE */
+	/* 1 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_REACHED */
+	/* 2 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_UNABLETOREACH */
+	/* 3 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_LOST */
+	/* default : unknown */
+	u32	af_scene_type;
+
+	u32	frame_descp_onoff_control;
+	u32	frame_descp_update_done;
+	u32	frame_descp_idx;
+	u32	frame_descp_max_idx;
+	struct is_debug_frame_descriptor
+		dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
+
+	u32	chip_id;
+	u32	chip_rev_no;
+	u8	isp_fw_ver_no[MAX_VERSION_DISPLAY_BUF];
+	u8	isp_fw_ver_date[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_ver_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_rev_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_rev_date[MAX_VERSION_DISPLAY_BUF];
+};
+
+struct is_debug_control {
+	u32 write_point;	/* 0~ 500KB boundary */
+	u32 assert_flag;	/* 0: Not invoked, 1: Invoked */
+	u32 pabort_flag;	/* 0: Not invoked, 1: Invoked */
+	u32 dabort_flag;	/* 0: Not invoked, 1: Invoked */
+};
+
+struct sensor_open_extended {
+	u32 actuator_type;
+	u32 mclk;
+	u32 mipi_lane_num;
+	u32 mipi_speed;
+	/* Skip setfile loading when fast_open_sensor is not 0 */
+	u32 fast_open_sensor;
+	/* Activatiing sensor self calibration mode (6A3) */
+	u32 self_calibration_mode;
+};
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-regs.h b/drivers/media/video/exynos/fimc-is/fimc-is-regs.h
new file mode 100644
index 0000000..15db064
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-regs.h
@@ -0,0 +1,354 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * Register map
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H_
+#define FIMC_IS_REGS_H_
+
+#include <mach/map.h>
+
+/* WDT_ISP register */
+#define WDT			0x00170000
+/* MCUCTL register */
+#define MCUCTL			0x00180000
+/* MCU Controller Register */
+#define MCUCTLR				(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)	((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)	((x) << 12)
+#define MCUCTLR_MSWRST			(1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR				(MCUCTL+0x04)
+#define BBOAR_BBOA(x)			((x) << 0)
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0				(MCUCTL+0x08)
+#define INTGR0_INTGC9			(1 << 25)
+#define INTGR0_INTGC8			(1 << 24)
+#define INTGR0_INTGC7			(1 << 23)
+#define INTGR0_INTGC6			(1 << 22)
+#define INTGR0_INTGC5			(1 << 21)
+#define INTGR0_INTGC4			(1 << 20)
+#define INTGR0_INTGC3			(1 << 19)
+#define INTGR0_INTGC2			(1 << 18)
+#define INTGR0_INTGC1			(1 << 17)
+#define INTGR0_INTGC0			(1 << 16)
+#define INTGR0_INTGD5			(1 << 5)
+#define INTGR0_INTGD4			(1 << 4)
+#define INTGR0_INTGD3			(1 << 3)
+#define INTGR0_INTGD2			(1 << 2)
+#define INTGR0_INTGD1			(1 << 1)
+#define INTGR0_INTGD0			(1 << 0)
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0				(MCUCTL+0x0c)
+#define INTCR0_INTCC9			(1 << 25)
+#define INTCR0_INTCC8			(1 << 24)
+#define INTCR0_INTCC7			(1 << 23)
+#define INTCR0_INTCC6			(1 << 22)
+#define INTCR0_INTCC5			(1 << 21)
+#define INTCR0_INTCC4			(1 << 20)
+#define INTCR0_INTCC3			(1 << 19)
+#define INTCR0_INTCC2			(1 << 18)
+#define INTCR0_INTCC1			(1 << 17)
+#define INTCR0_INTCC0			(1 << 16)
+#define INTCR0_INTCD5			(1 << 5)
+#define INTCR0_INTCD4			(1 << 4)
+#define INTCR0_INTCD3			(1 << 3)
+#define INTCR0_INTCD2			(1 << 2)
+#define INTCR0_INTCD1			(1 << 1)
+#define INTCR0_INTCD0			(1 << 0)
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0				(MCUCTL+0x10)
+#define INTMR0_INTMC9			(1 << 25)
+#define INTMR0_INTMC8			(1 << 24)
+#define INTMR0_INTMC7			(1 << 23)
+#define INTMR0_INTMC6			(1 << 22)
+#define INTMR0_INTMC5			(1 << 21)
+#define INTMR0_INTMC4			(1 << 20)
+#define INTMR0_INTMC3			(1 << 19)
+#define INTMR0_INTMC2			(1 << 18)
+#define INTMR0_INTMC1			(1 << 17)
+#define INTMR0_INTMC0			(1 << 16)
+#define INTMR0_INTMD5			(1 << 5)
+#define INTMR0_INTMD4			(1 << 4)
+#define INTMR0_INTMD3			(1 << 3)
+#define INTMR0_INTMD2			(1 << 2)
+#define INTMR0_INTMD1			(1 << 1)
+#define INTMR0_INTMD0			(1 << 0)
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0				(MCUCTL+0x14)
+#define INTSR0_GET_INTSD0(x)		(((x) >> 0) & 0x1)
+#define INTSR0_GET_INTSD1(x)		(((x) >> 1) & 0x1)
+#define INTSR0_GET_INTSD2(x)		(((x) >> 2) & 0x1)
+#define INTSR0_GET_INTSD3(x)		(((x) >> 3) & 0x1)
+#define INTSR0_GET_INTSD4(x)		(((x) >> 4) & 0x1)
+#define INTSR0_GET_INTSC0(x)		(((x) >> 16) & 0x1)
+#define INTSR0_GET_INTSC1(x)		(((x) >> 17) & 0x1)
+#define INTSR0_GET_INTSC2(x)		(((x) >> 18) & 0x1)
+#define INTSR0_GET_INTSC3(x)		(((x) >> 19) & 0x1)
+#define INTSR0_GET_INTSC4(x)		(((x) >> 20) & 0x1)
+#define INTSR0_GET_INTSC5(x)		(((x) >> 21) & 0x1)
+#define INTSR0_GET_INTSC6(x)		(((x) >> 22) & 0x1)
+#define INTSR0_GET_INTSC7(x)		(((x) >> 23) & 0x1)
+#define INTSR0_GET_INTSC8(x)		(((x) >> 24) & 0x1)
+#define INTSR0_GET_INTSC9(x)		(((x) >> 25) & 0x1)
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0				(MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD0(x)		(((x) >> 0) & 0x1)
+#define INTMSR0_GET_INTMSD1(x)		(((x) >> 1) & 0x1)
+#define INTMSR0_GET_INTMSD2(x)		(((x) >> 2) & 0x1)
+#define INTMSR0_GET_INTMSD3(x)		(((x) >> 3) & 0x1)
+#define INTMSR0_GET_INTMSD4(x)		(((x) >> 4) & 0x1)
+#define INTMSR0_GET_INTMSC0(x)		(((x) >> 16) & 0x1)
+#define INTMSR0_GET_INTMSC1(x)		(((x) >> 17) & 0x1)
+#define INTMSR0_GET_INTMSC2(x)		(((x) >> 18) & 0x1)
+#define INTMSR0_GET_INTMSC3(x)		(((x) >> 19) & 0x1)
+#define INTMSR0_GET_INTMSC4(x)		(((x) >> 20) & 0x1)
+#define INTMSR0_GET_INTMSC5(x)		(((x) >> 21) & 0x1)
+#define INTMSR0_GET_INTMSC6(x)		(((x) >> 22) & 0x1)
+#define INTMSR0_GET_INTMSC7(x)		(((x) >> 23) & 0x1)
+#define INTMSR0_GET_INTMSC8(x)		(((x) >> 24) & 0x1)
+#define INTMSR0_GET_INTMSC9(x)		(((x) >> 25) & 0x1)
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1				(MCUCTL+0x1c)
+#define INTGR1_INTGC9			(1 << 9)
+#define INTGR1_INTGC8			(1 << 8)
+#define INTGR1_INTGC7			(1 << 7)
+#define INTGR1_INTGC6			(1 << 6)
+#define INTGR1_INTGC5			(1 << 5)
+#define INTGR1_INTGC4			(1 << 4)
+#define INTGR1_INTGC3			(1 << 3)
+#define INTGR1_INTGC2			(1 << 2)
+#define INTGR1_INTGC1			(1 << 1)
+#define INTGR1_INTGC0			(1 << 0)
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1				(MCUCTL+0x20)
+#define INTCR1_INTCC9			(1 << 9)
+#define INTCR1_INTCC8			(1 << 8)
+#define INTCR1_INTCC7			(1 << 7)
+#define INTCR1_INTCC6			(1 << 6)
+#define INTCR1_INTCC5			(1 << 5)
+#define INTCR1_INTCC4			(1 << 4)
+#define INTCR1_INTCC3			(1 << 3)
+#define INTCR1_INTCC2			(1 << 2)
+#define INTCR1_INTCC1			(1 << 1)
+#define INTCR1_INTCC0			(1 << 0)
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1				(MCUCTL+0x24)
+#define INTMR1_INTMC9			(1 << 9)
+#define INTMR1_INTMC8			(1 << 8)
+#define INTMR1_INTMC7			(1 << 7)
+#define INTMR1_INTMC6			(1 << 6)
+#define INTMR1_INTMC5			(1 << 5)
+#define INTMR1_INTMC4			(1 << 4)
+#define INTMR1_INTMC3			(1 << 3)
+#define INTMR1_INTMC2			(1 << 2)
+#define INTMR1_INTMC1			(1 << 1)
+#define INTMR1_INTMC0			(1 << 0)
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1				(MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1				(MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2				(MCUCTL+0x30)
+#define INTCR2_INTCC21			(1 << 21)
+#define INTCR2_INTCC20			(1 << 20)
+#define INTCR2_INTCC19			(1 << 19)
+#define INTCR2_INTCC18			(1 << 18)
+#define INTCR2_INTCC17			(1 << 17)
+#define INTCR2_INTCC16			(1 << 16)
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2				(MCUCTL+0x34)
+#define INTMR2_INTMCIS25		(1 << 25)
+#define INTMR2_INTMCIS24		(1 << 24)
+#define INTMR2_INTMCIS23		(1 << 23)
+#define INTMR2_INTMCIS22		(1 << 22)
+#define INTMR2_INTMCIS21		(1 << 21)
+#define INTMR2_INTMCIS20		(1 << 20)
+#define INTMR2_INTMCIS19		(1 << 19)
+#define INTMR2_INTMCIS18		(1 << 18)
+#define INTMR2_INTMCIS17		(1 << 17)
+#define INTMR2_INTMCIS16		(1 << 16)
+#define INTMR2_INTMCIS15		(1 << 15)
+#define INTMR2_INTMCIS14		(1 << 14)
+#define INTMR2_INTMCIS13		(1 << 13)
+#define INTMR2_INTMCIS12		(1 << 12)
+#define INTMR2_INTMCIS11		(1 << 11)
+#define INTMR2_INTMCIS10		(1 << 10)
+#define INTMR2_INTMCIS9			(1 << 9)
+#define INTMR2_INTMCIS8			(1 << 8)
+#define INTMR2_INTMCIS7			(1 << 7)
+#define INTMR2_INTMCIS6			(1 << 6)
+#define INTMR2_INTMCIS5			(1 << 5)
+#define INTMR2_INTMCIS4			(1 << 4)
+#define INTMR2_INTMCIS3			(1 << 3)
+#define INTMR2_INTMCIS2			(1 << 2)
+#define INTMR2_INTMCIS1			(1 << 1)
+#define INTMR2_INTMCIS0			(1 << 0)
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2				(MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2				(MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR				(MCUCTL+0x40)
+#define GPOCTLR_GPOG17(x)		((x) << 17)
+#define GPOCTLR_GPOG16(x)		((x) << 16)
+#define GPOCTLR_GPOG15(x)		((x) << 15)
+#define GPOCTLR_GPOG14(x)		((x) << 14)
+#define GPOCTLR_GPOG13(x)		((x) << 13)
+#define GPOCTLR_GPOG12(x)		((x) << 12)
+#define GPOCTLR_GPOG11(x)		((x) << 11)
+#define GPOCTLR_GPOG10(x)		((x) << 10)
+#define GPOCTLR_GPOG9(x)		((x) << 9)
+#define GPOCTLR_GPOG8(x)		((x) << 8)
+#define GPOCTLR_GPOG7(x)		((x) << 7)
+#define GPOCTLR_GPOG6(x)		((x) << 6)
+#define GPOCTLR_GPOG5(x)		((x) << 5)
+#define GPOCTLR_GPOG4(x)		((x) << 4)
+#define GPOCTLR_GPOG3(x)		((x) << 3)
+#define GPOCTLR_GPOG2(x)		((x) << 2)
+#define GPOCTLR_GPOG1(x)		((x) << 1)
+#define GPOCTLR_GPOG0(x)		((x) << 0)
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR			(MCUCTL+0x44)
+#define GPOENCTLR_GPOEN17(x)		((x) << 17)
+#define GPOENCTLR_GPOEN16(x)		((x) << 16)
+#define GPOENCTLR_GPOEN15(x)		((x) << 15)
+#define GPOENCTLR_GPOEN14(x)		((x) << 14)
+#define GPOENCTLR_GPOEN13(x)		((x) << 13)
+#define GPOENCTLR_GPOEN12(x)		((x) << 12)
+#define GPOENCTLR_GPOEN11(x)		((x) << 11)
+#define GPOENCTLR_GPOEN10(x)		((x) << 10)
+#define GPOENCTLR_GPOEN9(x)		((x) << 9)
+#define GPOENCTLR_GPOEN8(x)		((x) << 8)
+#define GPOENCTLR_GPOEN7(x)		((x) << 7)
+#define GPOENCTLR_GPOEN6(x)		((x) << 6)
+#define GPOENCTLR_GPOEN5(x)		((x) << 5)
+#define GPOENCTLR_GPOEN4(x)		((x) << 4)
+#define GPOENCTLR_GPOEN3(x)		((x) << 3)
+#define GPOENCTLR_GPOEN2(x)		((x) << 2)
+#define GPOENCTLR_GPOEN1(x)		((x) << 1)
+#define GPOENCTLR_GPOEN0(x)		((x) << 0)
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR				(MCUCTL+0x48)
+/* IS Shared Register 0 between ISP CPU and HOST CPU */
+#define ISSR0			(MCUCTL+0x80)
+/* Command Host -> IS */
+/* IS Shared Register 1 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR1			(MCUCTL+0x84)
+/* IS Shared Register 2 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR2			(MCUCTL+0x88)
+/* IS Shared Register 3 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR3			(MCUCTL+0x8c)
+/* IS Shared Register 4 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR4			(MCUCTL+0x90)
+/* IS Shared Register 5 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR5			(MCUCTL+0x94)
+#define ISSR6			(MCUCTL+0x98)
+#define ISSR7			(MCUCTL+0x9c)
+#define ISSR8			(MCUCTL+0xa0)
+#define ISSR9			(MCUCTL+0xa4)
+/* IS Shared Register 10 between ISP CPU and HOST CPU */
+/* Command IS -> Host */
+#define ISSR10			(MCUCTL+0xa8)
+/* IS Shared Register 11 between ISP CPU and HOST CPU */
+/* Sensor ID for Command */
+#define ISSR11			(MCUCTL+0xac)
+/* IS Shared Register 12 between ISP CPU and HOST CPU */
+/* Parameter 1 */
+#define ISSR12			(MCUCTL+0xb0)
+/* IS Shared Register 13 between ISP CPU and HOST CPU */
+/* Parameter 2 */
+#define ISSR13			(MCUCTL+0xb4)
+/* IS Shared Register 14 between ISP CPU and HOST CPU */
+/* Parameter 3 */
+#define ISSR14			(MCUCTL+0xb8)
+/* IS Shared Register 15 between ISP CPU and HOST CPU */
+/* Parameter 4 */
+#define ISSR15			(MCUCTL+0xbc)
+#define ISSR16			(MCUCTL+0xc0)
+#define ISSR17			(MCUCTL+0xc4)
+#define ISSR18			(MCUCTL+0xc8)
+#define ISSR19			(MCUCTL+0xcc)
+/* IS Shared Register 20 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : SENSOR ID */
+#define ISSR20			(MCUCTL+0xd0)
+/* IS Shared Register 21 between ISP CPU and HOST CPU */
+/* ISP_FRAME_DONE : PARAMETER 1 */
+#define ISSR21			(MCUCTL+0xd4)
+#define ISSR22			(MCUCTL+0xd8)
+#define ISSR23			(MCUCTL+0xdc)
+/* IS Shared Register 24 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : SENSOR ID */
+#define ISSR24			(MCUCTL+0xe0)
+/* IS Shared Register 25 between ISP CPU and HOST CPU */
+/* SCALERC_FRAME_DONE : PARAMETER 1 */
+#define ISSR25			(MCUCTL+0xe4)
+#define ISSR26			(MCUCTL+0xe8)
+#define ISSR27			(MCUCTL+0xec)
+/* IS Shared Register 28 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : SENSOR ID */
+#define ISSR28			(MCUCTL+0xf0)
+/* IS Shared Register 29 between ISP CPU and HOST CPU */
+/* 3DNR_FRAME_DONE : PARAMETER 1 */
+#define ISSR29			(MCUCTL+0xf4)
+#define ISSR30			(MCUCTL+0xf8)
+#define ISSR31			(MCUCTL+0xfc)
+/* IS Shared Register 32 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : SENSOR ID */
+#define ISSR32			(MCUCTL+0x100)
+/* IS Shared Register 33 between ISP CPU and HOST CPU */
+/* SCALERP_FRAME_DONE : PARAMETER 1 */
+#define ISSR33			(MCUCTL+0x104)
+#define ISSR34			(MCUCTL+0x108)
+#define ISSR35			(MCUCTL+0x10c)
+#define ISSR36			(MCUCTL+0x110)
+#define ISSR37			(MCUCTL+0x114)
+#define ISSR38			(MCUCTL+0x118)
+#define ISSR39			(MCUCTL+0x11c)
+#define ISSR40			(MCUCTL+0x120)
+#define ISSR41			(MCUCTL+0x124)
+#define ISSR42			(MCUCTL+0x128)
+#define ISSR43			(MCUCTL+0x12c)
+#define ISSR44			(MCUCTL+0x130)
+#define ISSR45			(MCUCTL+0x134)
+#define ISSR46			(MCUCTL+0x138)
+#define ISSR47			(MCUCTL+0x13c)
+#define ISSR48			(MCUCTL+0x140)
+#define ISSR49			(MCUCTL+0x144)
+#define ISSR50			(MCUCTL+0x148)
+#define ISSR51			(MCUCTL+0x14c)
+#define ISSR52			(MCUCTL+0x150)
+#define ISSR53			(MCUCTL+0x154)
+#define ISSR54			(MCUCTL+0x158)
+#define ISSR55			(MCUCTL+0x15c)
+#define ISSR56			(MCUCTL+0x160)
+#define ISSR57			(MCUCTL+0x164)
+#define ISSR58			(MCUCTL+0x168)
+#define ISSR59			(MCUCTL+0x16c)
+#define ISSR60			(MCUCTL+0x170)
+#define ISSR61			(MCUCTL+0x174)
+#define ISSR62			(MCUCTL+0x178)
+#define ISSR63			(MCUCTL+0x17c)
+
+/* PMU for FIMC-IS*/
+#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG	(S5P_VA_PMU  + 0x1174)
+#define PMUREG_ISP_ARM_CONFIGURATION		(S5P_VA_PMU  + 0x2280)
+#define PMUREG_ISP_ARM_STATUS			(S5P_VA_PMU  + 0x2284)
+#define PMUREG_ISP_ARM_OPTION			(S5P_VA_PMU  + 0x2288)
+#define PMUREG_ISP_LOW_POWER_OFF		(S5P_VA_PMU  + 0x0004)
+#define PMUREG_ISP_ARM_SYS			(S5P_VA_PMU  + 0x1050)
+#define PMUREG_CMU_SYSCLK_ISP_SYS_PWR_REG	(S5P_VA_PMU  + 0x13B8)
+#endif
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-v4l2.c b/drivers/media/video/exynos/fimc-is/fimc-is-v4l2.c
new file mode 100644
index 0000000..aa60198
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-v4l2.c
@@ -0,0 +1,4653 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * v4l2 subdev driver interface
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/workqueue.h>
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-err.h"
+
+/* Binary load functions */
+static int fimc_is_request_firmware(struct fimc_is_dev *dev)
+{
+	int ret;
+	struct firmware *fw_blob;
+	u8 *buf = NULL;
+#ifdef SDCARD_FW
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	ret = 0;
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	fp = filp_open(FIMC_IS_FW_SDCARD, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		dbg("failed to open %s\n", FIMC_IS_FW_SDCARD);
+		goto request_fw;
+	}
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+	dbg("start, file path %s, size %ld Bytes\n", FIMC_IS_FW_SDCARD, fsize);
+	buf = vmalloc(fsize);
+	if (!buf) {
+		err("failed to allocate memory\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+	nread = vfs_read(fp, (char __user *)buf, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		err("failed to read firmware file, %ld Bytes\n", nread);
+		ret = -EIO;
+		goto out;
+	}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	memcpy((void *)phys_to_virt(dev->mem.base), (void *)buf, fsize);
+	fimc_is_mem_cache_clean((void *)phys_to_virt(dev->mem.base),
+		fsize + 1);
+	if (dev->mem.fw_ref_base > 0) {
+		memcpy((void *)phys_to_virt(dev->mem.fw_ref_base),
+							(void *)buf, fsize);
+		fimc_is_mem_cache_clean(
+			(void *)phys_to_virt(dev->mem.fw_ref_base), fsize + 1);
+		dev->fw.size = fsize;
+	}
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	if (dev->mem.bitproc_buf == 0) {
+		err("failed to load FIMC-IS F/W, FIMC-IS will not working\n");
+	} else {
+		memcpy(dev->mem.kvaddr, (void *)buf, fsize);
+		fimc_is_mem_cache_clean((void *)dev->mem.kvaddr, fsize + 1);
+	}
+#endif
+	vfs_llseek(fp, -FIMC_IS_FW_VERSION_LENGTH, SEEK_END);
+	vfs_read(fp, (char __user *)dev->fw.fw_version,
+				(FIMC_IS_FW_VERSION_LENGTH - 1), &fp->f_pos);
+	dev->fw.fw_version[FIMC_IS_FW_VERSION_LENGTH - 1] = '\0';
+	vfs_llseek(fp, -(FIMC_IS_FW_INFO_LENGTH +
+				FIMC_IS_FW_VERSION_LENGTH - 1), SEEK_END);
+	vfs_read(fp, (char __user *)dev->fw.fw_info,
+					(FIMC_IS_FW_INFO_LENGTH-1), &fp->f_pos);
+	dev->fw.fw_info[FIMC_IS_FW_INFO_LENGTH - 1] = '\0';
+	dev->fw.state = 1;
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+#endif
+		ret = request_firmware((const struct firmware **)&fw_blob,
+					FIMC_IS_FW, &dev->pdev->dev);
+		if (ret) {
+			dev_err(&dev->pdev->dev,
+				"could not load firmware (err=%d)\n", ret);
+			return -EINVAL;
+		}
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+		memcpy((void *)phys_to_virt(dev->mem.base),
+				fw_blob->data, fw_blob->size);
+		fimc_is_mem_cache_clean((void *)phys_to_virt(dev->mem.base),
+							fw_blob->size + 1);
+		if (dev->mem.fw_ref_base > 0) {
+			memcpy((void *)phys_to_virt(dev->mem.fw_ref_base),
+						fw_blob->data, fw_blob->size);
+			fimc_is_mem_cache_clean(
+				(void *)phys_to_virt(dev->mem.fw_ref_base),
+				fw_blob->size + 1);
+			dev->fw.size = fw_blob->size;
+		}
+#elif defined(CONFIG_VIDEOBUF2_ION)
+		if (dev->mem.bitproc_buf == 0) {
+			err("failed to load FIMC-IS F/W\n");
+			return -EINVAL;
+		} else {
+			memcpy(dev->mem.kvaddr, fw_blob->data, fw_blob->size);
+			fimc_is_mem_cache_clean(
+				(void *)dev->mem.kvaddr, fw_blob->size + 1);
+			dbg(
+		"FIMC_IS F/W loaded successfully - size:%d\n", fw_blob->size);
+		}
+#endif
+		memcpy((void *)dev->fw.fw_info,
+			(fw_blob->data + fw_blob->size -
+			(FIMC_IS_FW_INFO_LENGTH + FIMC_IS_FW_VERSION_LENGTH-1)),
+			(FIMC_IS_FW_INFO_LENGTH - 1));
+		dev->fw.fw_info[FIMC_IS_FW_INFO_LENGTH - 1] = '\0';
+		memcpy((void *)dev->fw.fw_version,
+			(fw_blob->data + fw_blob->size -
+				FIMC_IS_FW_VERSION_LENGTH),
+					(FIMC_IS_FW_VERSION_LENGTH - 1));
+		dev->fw.fw_version[FIMC_IS_FW_VERSION_LENGTH - 1] = '\0';
+		dev->fw.state = 1;
+		dbg("FIMC_IS F/W loaded successfully - size:%d\n",
+							fw_blob->size);
+		release_firmware(fw_blob);
+#ifdef SDCARD_FW
+	}
+#endif
+
+out:
+#ifdef SDCARD_FW
+	if (!fw_requested) {
+		vfree(buf);
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	}
+#endif
+	printk(KERN_INFO "FIMC_IS FW loaded = 0x%08x\n", dev->mem.base);
+	return ret;
+}
+
+static int fimc_is_load_setfile(struct fimc_is_dev *dev)
+{
+	int ret;
+	struct firmware *fw_blob;
+	u8 *buf = NULL;
+#ifdef SDCARD_FW
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	ret = 0;
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	fp = filp_open(FIMC_IS_SETFILE_SDCARD, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		dbg("failed to open %s\n", FIMC_IS_SETFILE_SDCARD);
+		goto request_fw;
+	}
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+	dbg("start, file path %s, size %ld Bytes\n",
+		FIMC_IS_SETFILE_SDCARD, fsize);
+	buf = vmalloc(fsize);
+	if (!buf) {
+		err("failed to allocate memory\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+	nread = vfs_read(fp, (char __user *)buf, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		err("failed to read firmware file, %ld Bytes\n", nread);
+		ret = -EIO;
+		goto out;
+	}
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	memcpy((void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+							(void *)buf, fsize);
+	fimc_is_mem_cache_clean(
+		(void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+		fsize + 1);
+	if (dev->mem.setfile_ref_base > 0) {
+		memcpy((void *)phys_to_virt(dev->mem.setfile_ref_base),
+							(void *)buf, fsize);
+		fimc_is_mem_cache_clean(
+			(void *)phys_to_virt(dev->mem.setfile_ref_base),
+			fsize + 1);
+		dev->setfile.size = fsize;
+	}
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	if (dev->mem.bitproc_buf == 0) {
+		err("failed to load FIMC-IS F/W, FIMC-IS will not working\n");
+	} else {
+		memcpy((dev->mem.kvaddr + dev->setfile.base),
+						(void *)buf, fsize);
+		fimc_is_mem_cache_clean((void *)dev->mem.kvaddr, fsize + 1);
+		dbg("FIMC_IS Setfile loaded successfully - size:%ld\n", fsize);
+	}
+#endif
+	vfs_llseek(fp, -FIMC_IS_SETFILE_INFO_LENGTH, SEEK_END);
+	vfs_read(fp, (char __user *)dev->fw.setfile_info,
+				FIMC_IS_SETFILE_INFO_LENGTH, &fp->f_pos);
+	dev->setfile.state = 1;
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+#endif
+		ret = request_firmware((const struct firmware **)&fw_blob,
+					FIMC_IS_SETFILE, &dev->pdev->dev);
+		if (ret) {
+			dev_err(&dev->pdev->dev,
+				"could not load firmware (err=%d)\n", ret);
+			return -EINVAL;
+		}
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+		memcpy((void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+			fw_blob->data, fw_blob->size);
+		fimc_is_mem_cache_clean(
+			(void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+			fw_blob->size + 1);
+		if (dev->mem.setfile_ref_base > 0) {
+			memcpy((void *)phys_to_virt(dev->mem.setfile_ref_base),
+					fw_blob->data, fw_blob->size);
+			fimc_is_mem_cache_clean(
+				(void *)phys_to_virt(dev->mem.setfile_ref_base),
+				fw_blob->size + 1);
+			dev->setfile.size = fw_blob->size;
+		}
+#elif defined(CONFIG_VIDEOBUF2_ION)
+		if (dev->mem.bitproc_buf == 0) {
+			err("failed to load FIMC-IS F/W\n");
+			return -EINVAL;
+		} else {
+			memcpy((dev->mem.kvaddr + dev->setfile.base),
+						fw_blob->data, fw_blob->size);
+			fimc_is_mem_cache_clean((void *)dev->mem.kvaddr,
+						fw_blob->size + 1);
+			dbg(
+		"FIMC_IS F/W loaded successfully - size:%d\n", fw_blob->size);
+		}
+#endif
+		memcpy((void *)dev->fw.setfile_info,
+			(fw_blob->data + fw_blob->size -
+				FIMC_IS_SETFILE_INFO_LENGTH),
+				(FIMC_IS_SETFILE_INFO_LENGTH - 1));
+		dev->fw.setfile_info[FIMC_IS_SETFILE_INFO_LENGTH - 1] = '\0';
+		dev->setfile.state = 1;
+		dbg("FIMC_IS setfile loaded successfully - size:%d\n",
+								fw_blob->size);
+		release_firmware(fw_blob);
+#ifdef SDCARD_FW
+	}
+#endif
+
+	dbg("A5 mem base  = 0x%08x\n", dev->mem.base);
+	dbg("Setfile base  = 0x%08x\n", dev->setfile.base);
+out:
+#ifdef SDCARD_FW
+	if (!fw_requested) {
+		vfree(buf);
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	}
+#endif
+	return ret;
+}
+
+/* v4l2 subdev core operations
+*/
+static int fimc_is_load_fw(struct v4l2_subdev *sd)
+{
+	int ret = 0;
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	dbg("+++ fimc_is_load_fw\n");
+	if (!test_bit(IS_ST_IDLE, &dev->state)) {
+		err("FW was already loaded!!\n");
+		return ret;
+	}
+	/* 1. Load IS firmware */
+	if (dev->fw.state && (dev->mem.fw_ref_base > 0)) {
+		memcpy((void *)phys_to_virt(dev->mem.base),
+			(void *)phys_to_virt(dev->mem.fw_ref_base),
+			dev->fw.size);
+		fimc_is_mem_cache_clean((void *)phys_to_virt(dev->mem.base),
+							dev->fw.size + 1);
+	} else {
+		ret = fimc_is_request_firmware(dev);
+		if (ret) {
+			err("failed to fimc_is_request_firmware (%d)\n", ret);
+			return -EINVAL;
+		}
+	}
+	/* 2. Init GPIO (UART) */
+	ret = fimc_is_hw_io_init(dev);
+	if (ret) {
+		dev_err(&dev->pdev->dev, "failed to init GPIO config\n");
+		return -EINVAL;
+	}
+	/* 3. Chip ID and Revision */
+	dev->is_shared_region->chip_id = 0xe4412;
+	dev->is_shared_region->chip_rev_no = 1;
+	fimc_is_mem_cache_clean((void *)IS_SHARED,
+		(unsigned long)(sizeof(struct is_share_region)));
+	/* 4. A5 power on */
+	fimc_is_hw_a5_power(dev, 1);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_FW_LOADED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"wait timeout A5 power on: %s\n", __func__);
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	clear_bit(IS_ST_IDLE, &dev->state);
+	dbg("--- fimc_is_load_fw end\n");
+	printk(KERN_INFO "FIMC-IS FW info = %s\n", dev->fw.fw_info);
+	printk(KERN_INFO "FIMC-IS FW ver = %s\n", dev->fw.fw_version);
+	return ret;
+}
+
+int fimc_is_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+	struct device *dev = &is_dev->pdev->dev;
+	int ret = 0;
+
+	printk(KERN_INFO "%s++ %d\n", __func__, on);
+	if (on) {
+		if (test_bit(IS_PWR_ST_POWERON, &is_dev->power)) {
+			err("FIMC-IS was already power on state!!\n");
+			return ret;
+		}
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+		/* lock bus frequency */
+		dev_lock(is_dev->bus_dev, dev, BUS_LOCK_FREQ_L0);
+#endif
+		fimc_is_hw_set_low_poweroff(is_dev, false);
+		ret = pm_runtime_get_sync(dev);
+		set_bit(IS_ST_A5_PWR_ON, &is_dev->state);
+	} else {
+		if (test_bit(IS_PWR_ST_POWEROFF, &is_dev->power)) {
+			err("FIMC-IS was already power off state!!\n");
+			err("Close sensor - %d\n", is_dev->sensor.id);
+			fimc_is_hw_close_sensor(is_dev, 0);
+			printk(KERN_INFO "%s Wait close sensor interrupt\n", __func__);
+			ret = wait_event_timeout(is_dev->irq_queue1,
+				!test_bit(IS_ST_OPEN_SENSOR,
+				&is_dev->power), FIMC_IS_SHUTDOWN_TIMEOUT);
+			if (!ret) {
+				err("Timeout-close sensor:%s\n", __func__);
+				fimc_is_hw_set_low_poweroff(is_dev, true);
+			} else {
+				is_dev->p_region_index1 = 0;
+				is_dev->p_region_index2 = 0;
+				atomic_set(&is_dev->p_region_num, 0);
+				printk(KERN_INFO "%s already power off return\n", __func__);
+				return ret;
+			}
+		}
+
+		printk(KERN_INFO "%s sub ip power off ++\n", __func__);
+
+		if (!test_bit(IS_PWR_SUB_IP_POWER_OFF, &is_dev->power)) {
+			printk(KERN_INFO "%s Sub ip is alive\n", __func__);
+			fimc_is_hw_subip_poweroff(is_dev);
+			printk(KERN_INFO "%s Wait Sub ip power off\n", __func__);
+			ret = wait_event_timeout(is_dev->irq_queue1,
+				test_bit(IS_PWR_SUB_IP_POWER_OFF,
+				&is_dev->power), FIMC_IS_SHUTDOWN_TIMEOUT);
+			if (!ret) {
+				err("%s wait timeout\n", __func__);
+				fimc_is_hw_set_low_poweroff(is_dev, true);
+			}
+		} else
+			printk(KERN_INFO "%s sub ip was already power off state!!\n", __func__);
+
+		printk(KERN_INFO "%s sub ip power off --\n", __func__);
+
+		fimc_is_hw_a5_power(is_dev, 0);
+		printk(KERN_INFO "A5 power off\n");
+		ret = pm_runtime_put_sync(dev);
+
+		is_dev->sensor.id = 0;
+		is_dev->sensor.framerate_update = false;
+		is_dev->p_region_index1 = 0;
+		is_dev->p_region_index2 = 0;
+		atomic_set(&is_dev->p_region_num, 0);
+		is_dev->state = 0;
+		set_bit(IS_ST_IDLE, &is_dev->state);
+		is_dev->power = 0;
+		is_dev->af.af_state = FIMC_IS_AF_IDLE;
+		is_dev->af.mode = IS_FOCUS_MODE_IDLE;
+		set_bit(IS_PWR_ST_POWEROFF, &is_dev->power);
+	}
+	printk(KERN_INFO "%s --\n", __func__);
+
+	return ret;
+}
+
+static int fimc_is_init_set(struct v4l2_subdev *sd, u32 val)
+{
+	int ret = 0;
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	dev->sensor.sensor_type = val;
+	dev->sensor.id = 0;
+	dbg("fimc_is_init\n");
+	if (!test_bit(IS_ST_A5_PWR_ON, &dev->state)) {
+		err("A5 is not power on state!!\n");
+		return -EINVAL;
+	}
+	/* Init sequence 1: Open sensor */
+	dbg("v4l2 : open sensor : %d\n", val);
+	fimc_is_hw_open_sensor(dev, dev->sensor.id, val);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_OPEN_SENSOR, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("wait timeout - open sensor\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	/* Init sequence 2: Load setfile */
+	/* Get setfile address */
+	dbg("v4l2 : setfile address\n");
+	fimc_is_hw_get_setfile_addr(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_SETFILE_LOADED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("wait timeout - get setfile address\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	dbg("v4l2 : load setfile\n");
+	if (dev->setfile.state && (dev->mem.setfile_ref_base > 0)) {
+		memcpy((void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+			(void *)phys_to_virt(dev->mem.setfile_ref_base),
+			dev->setfile.size);
+		fimc_is_mem_cache_clean(
+			(void *)phys_to_virt(dev->mem.base + dev->setfile.base),
+			dev->setfile.size + 1);
+	} else {
+		fimc_is_load_setfile(dev);
+	}
+	clear_bit(IS_ST_SETFILE_LOADED, &dev->state);
+	fimc_is_hw_load_setfile(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_SETFILE_LOADED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("wait timeout - get setfile address\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	printk(KERN_INFO "FIMC-IS Setfile info = %s\n", dev->fw.setfile_info);
+	dbg("v4l2 : Load set file end\n");
+	/* Check magic number */
+	if (dev->is_p_region->shared[MAX_SHARED_COUNT-1] != MAGIC_NUMBER)
+		err("!!! MAGIC NUMBER ERROR !!!\n");
+	/* Display region information (DEBUG only) */
+	dbg("Parameter region addr = 0x%08x\n", virt_to_phys(dev->is_p_region));
+	dbg("ISP region addr = 0x%08x\n",
+				virt_to_phys(&dev->is_p_region->parameter.isp));
+	dbg("Shared region addr = 0x%08x\n",
+				virt_to_phys(&dev->is_p_region->shared));
+	dev->frame_count = 0;
+	dev->setfile.sub_index = 0;
+	/* Init sequence 3: Stream off */
+	dbg("Stream Off\n");
+	clear_bit(IS_ST_STREAM_OFF, &dev->state);
+	fimc_is_hw_set_stream(dev, 0); /*stream off */
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_STREAM_OFF, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("wait timeout - stream off\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	/* Init sequence 4: Set init value - PREVIEW_STILL mode */
+	dbg("Default setting : preview_still\n");
+	dev->scenario_id = ISS_PREVIEW_STILL;
+	fimc_is_hw_set_init(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state); /* BLOCK I/F Mode*/
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+	if (!ret) {
+		err("wait timeout : init values (PREVIEW_STILL)\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	/* Init sequence 5: Set init value - PREVIEW_VIDEO mode */
+	dbg("Default setting : preview_video\n");
+	dev->scenario_id = ISS_PREVIEW_VIDEO;
+	fimc_is_hw_set_init(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state); /* BLOCK I/F Mode*/
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+	if (!ret) {
+		err("wait timeout : init values (PREVIEW_VIDEO)\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	/* Init sequence 6: Set init value - CAPTURE_STILL mode */
+	dbg("Default setting : capture_still\n");
+	dev->scenario_id = ISS_CAPTURE_STILL;
+	fimc_is_hw_set_init(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state); /* BLOCK I/F Mode*/
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+	if (!ret) {
+		err("wait timeout : init values (CAPTURE_STILL)\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	/* Init sequence 6: Set init value - CAPTURE_VIDEO mode */
+	dbg("Default setting : capture_video\n");
+	dev->scenario_id = ISS_CAPTURE_VIDEO;
+	fimc_is_hw_set_init(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state); /* BLOCK I/F Mode*/
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+	if (!ret) {
+		err("wait timeout : init values (CAPTURE_VIDEO)\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	set_bit(IS_ST_INIT_DONE, &dev->state);
+	dbg("Init sequence completed!! Ready to use\n");
+#ifdef MSG_CONFIG_COTROL
+	fimc_is_hw_set_debug_level(dev, FIMC_IS_DEBUG_MSG, FIMC_IS_DEBUG_LEVEL);
+#endif
+	return ret;
+}
+
+static int fimc_is_reset(struct v4l2_subdev *sd, u32 val)
+{
+	struct fimc_is_dev *is_dev = to_fimc_is_dev(sd);
+	struct device *dev = &is_dev->pdev->dev;
+	int ret = 0;
+
+	dbg("fimc_is_reset\n");
+	if (!val)
+		return -EINVAL;
+	dbg("hard reset start\n");
+	/* Power off */
+	fimc_is_hw_subip_poweroff(is_dev);
+	ret = wait_event_timeout(is_dev->irq_queue1,
+		test_bit(IS_PWR_SUB_IP_POWER_OFF, &is_dev->power), (HZ));
+	fimc_is_hw_a5_power(is_dev, 0);
+	dbg("A5 power off\n");
+	fimc_is_hw_set_low_poweroff(is_dev, true);
+	ret = pm_runtime_put_sync(dev);
+
+	is_dev->sensor.id = 0;
+	is_dev->p_region_index1 = 0;
+	is_dev->p_region_index2 = 0;
+	atomic_set(&is_dev->p_region_num, 0);
+	is_dev->state = 0;
+	set_bit(IS_ST_IDLE, &is_dev->state);
+	is_dev->power = 0;
+	is_dev->af.af_state = FIMC_IS_AF_IDLE;
+	is_dev->af.mode = IS_FOCUS_MODE_IDLE;
+	set_bit(IS_PWR_ST_POWEROFF, &is_dev->power);
+	/* Restart */
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_lock(is_dev->bus_dev, dev, BUS_LOCK_FREQ_L0);
+#endif
+	fimc_is_hw_set_low_poweroff(is_dev, false);
+	ret = pm_runtime_get_sync(dev);
+	set_bit(IS_ST_A5_PWR_ON, &is_dev->state);
+	/* Re- init */
+	ret = fimc_is_init_set(sd, is_dev->sensor.sensor_type);
+	return 0;
+}
+
+static int fimc_is_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	int ret = 0;
+	int i, max, tmp = 0;
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+
+	switch (ctrl->id) {
+	/* EXIF information */
+	case V4L2_CID_IS_CAMERA_EXIF_EXPTIME:
+	case V4L2_CID_CAMERA_EXIF_EXPTIME: /* Exposure Time */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = dev->is_p_region->header[0].
+			exif.exposure_time.den;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_FLASH:
+	case V4L2_CID_CAMERA_EXIF_FLASH: /* Flash */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = dev->is_p_region->header[0].exif.flash;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_ISO:
+	case V4L2_CID_CAMERA_EXIF_ISO: /* ISO Speed Rating */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = dev->is_p_region->header[0].
+			exif.iso_speed_rating;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_SHUTTERSPEED:
+	case V4L2_CID_CAMERA_EXIF_TV: /* Shutter Speed */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		/* Exposure time = shutter speed by FW */
+		ctrl->value = dev->is_p_region->header[0].
+			exif.exposure_time.den;
+		break;
+	case V4L2_CID_IS_CAMERA_EXIF_BRIGHTNESS:
+	case V4L2_CID_CAMERA_EXIF_BV: /* Brightness */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = dev->is_p_region->header[0].exif.brightness.num;
+		break;
+	case V4L2_CID_CAMERA_EXIF_EBV: /* exposure bias */
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value = dev->is_p_region->header[0].exif.brightness.den;
+		break;
+	/* Get x and y offset of sensor  */
+	case V4L2_CID_IS_GET_SENSOR_OFFSET_X:
+		ctrl->value = dev->sensor.offset_x;
+		break;
+	case V4L2_CID_IS_GET_SENSOR_OFFSET_Y:
+		ctrl->value = dev->sensor.offset_y;
+		break;
+	/* Get current sensor size  */
+	case V4L2_CID_IS_GET_SENSOR_WIDTH:
+		switch (dev->scenario_id) {
+		case ISS_PREVIEW_STILL:
+			ctrl->value = dev->sensor.width_prev;
+			break;
+		case ISS_PREVIEW_VIDEO:
+			ctrl->value = dev->sensor.width_prev_cam;
+			break;
+		case ISS_CAPTURE_STILL:
+			ctrl->value = dev->sensor.width_cap;
+			break;
+		case ISS_CAPTURE_VIDEO:
+			ctrl->value = dev->sensor.width_cam;
+			break;
+		}
+		break;
+	case V4L2_CID_IS_GET_SENSOR_HEIGHT:
+		switch (dev->scenario_id) {
+		case ISS_PREVIEW_STILL:
+			ctrl->value = dev->sensor.height_prev;
+			break;
+		case ISS_PREVIEW_VIDEO:
+			ctrl->value = dev->sensor.height_prev_cam;
+			break;
+		case ISS_CAPTURE_STILL:
+			ctrl->value = dev->sensor.height_cap;
+			break;
+		case ISS_CAPTURE_VIDEO:
+			ctrl->value = dev->sensor.height_cam;
+			break;
+		}
+		break;
+	/* Get information related to frame management  */
+	case V4L2_CID_IS_GET_FRAME_VALID:
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		if ((dev->scenario_id == ISS_PREVIEW_STILL) ||
+			(dev->scenario_id == ISS_PREVIEW_VIDEO)) {
+			ctrl->value = dev->is_p_region->header
+			[dev->frame_count%MAX_FRAME_COUNT_PREVIEW].valid;
+		} else {
+			ctrl->value = dev->is_p_region->header[0].valid;
+		}
+		break;
+	case V4L2_CID_IS_GET_FRAME_BADMARK:
+		break;
+	case V4L2_CID_IS_GET_FRAME_NUMBER:
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		if ((dev->scenario_id == ISS_PREVIEW_STILL) ||
+			(dev->scenario_id == ISS_PREVIEW_VIDEO)) {
+			ctrl->value =
+				dev->is_p_region->header
+				[dev->frame_count%MAX_FRAME_COUNT_PREVIEW].
+				frame_number;
+		} else {
+			ctrl->value =
+				dev->is_p_region->header[0].frame_number;
+		}
+		break;
+	case V4L2_CID_IS_GET_LOSTED_FRAME_NUMBER:
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		if (dev->scenario_id == ISS_CAPTURE_STILL) {
+			ctrl->value =
+				dev->is_p_region->header[0].frame_number;
+		} else if (dev->scenario_id == ISS_CAPTURE_VIDEO) {
+			ctrl->value =
+				dev->is_p_region->header[0].frame_number + 1;
+		} else {
+			max = dev->is_p_region->header[0].frame_number;
+			for (i = 1; i < MAX_FRAME_COUNT_PREVIEW; i++) {
+				if (max <
+				dev->is_p_region->header[i].frame_number)
+					max =
+				dev->is_p_region->header[i].frame_number;
+			}
+			ctrl->value = max;
+		}
+		dev->frame_count = ctrl->value;
+		break;
+	case V4L2_CID_IS_GET_FRAME_CAPTURED:
+		fimc_is_mem_cache_inv((void *)IS_HEADER,
+			(unsigned long)(sizeof(struct is_frame_header)*4));
+		ctrl->value =
+			dev->is_p_region->header
+			[dev->frame_count%MAX_FRAME_COUNT_PREVIEW].captured;
+		break;
+	case V4L2_CID_IS_FD_GET_DATA:
+		ctrl->value = dev->fd_header.count;
+		fimc_is_mem_cache_inv((void *)IS_FACE,
+		(unsigned long)(sizeof(struct is_face_marker)*MAX_FACE_COUNT));
+		memcpy((void *)dev->fd_header.target_addr,
+			&dev->is_p_region->face[dev->fd_header.index],
+			(sizeof(struct is_face_marker)*dev->fd_header.count));
+		break;
+	/* AF result */
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		if (!is_af_use(dev))
+			ctrl->value = 0x02;
+		else
+			ctrl->value = dev->af.af_lock_state;
+		break;
+	case V4L2_CID_IS_ZOOM_STATE:
+		if (test_bit(IS_ST_SET_ZOOM, &dev->state))
+			ctrl->value = 1;
+		else
+			ctrl->value  = 0;
+		break;
+	case V4L2_CID_IS_ZOOM_MAX_LEVEL:
+		switch (dev->scenario_id) {
+		case ISS_PREVIEW_STILL:
+			tmp = dev->sensor.width_prev;
+			break;
+		case ISS_PREVIEW_VIDEO:
+			tmp = dev->sensor.width_prev_cam;
+			break;
+		case ISS_CAPTURE_STILL:
+			tmp = dev->sensor.width_cap;
+			break;
+		case ISS_CAPTURE_VIDEO:
+			tmp = dev->sensor.width_cam;
+			break;
+		}
+		i = 0;
+		while ((tmp - (16*i)) > (tmp/4) && (tmp - (16*i)) > 200)
+			i++;
+		ctrl->value = i;
+		break;
+	/* F/W debug region address */
+	case V4L2_CID_IS_FW_DEBUG_REGION_ADDR:
+		ctrl->value = dev->mem.base + FIMC_IS_DEBUG_REGION_ADDR;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_digital_zoom(struct fimc_is_dev *dev, int zoom_factor)
+{
+	u32 ori_width = 0, ori_height = 0;
+	u32 crop_offset_x = 0, crop_offset_y = 0;
+	u32 crop_width = 0, crop_height = 0;
+	u32 mode = 0;
+	int tmp, ret = 0;
+
+	clear_bit(IS_ST_SET_ZOOM, &dev->state);
+
+	/* 1. Get current width and height */
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		mode = IS_MODE_PREVIEW_STILL;
+		ori_width = dev->sensor.width_prev;
+		ori_height = dev->sensor.height_prev;
+		tmp = fimc_is_hw_get_sensor_max_framerate(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, tmp);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		break;
+	case ISS_PREVIEW_VIDEO:
+		mode = IS_MODE_PREVIEW_VIDEO;
+		ori_width = dev->sensor.width_prev_cam;
+		ori_height = dev->sensor.height_prev_cam;
+		break;
+	case ISS_CAPTURE_STILL:
+		mode = IS_MODE_CAPTURE_STILL;
+		ori_width = dev->sensor.width_cap;
+		ori_height = dev->sensor.height_cap;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		mode = IS_MODE_CAPTURE_VIDEO;
+		ori_width = dev->sensor.width_cam;
+		ori_height = dev->sensor.height_cam;
+		break;
+	}
+
+	/* calculate the offset and size */
+	if (!zoom_factor) {
+		crop_offset_x = 0;
+		crop_offset_y = 0;
+		crop_width = 0;
+		crop_height = 0;
+		dev->sensor.zoom_out_width = ori_width;
+		dev->sensor.zoom_out_height = ori_height;
+	} else {
+		crop_width = ori_width - (16 * zoom_factor);
+		crop_height = (crop_width * ori_height) / ori_width;
+		/* bayer crop contraint */
+		switch (crop_height%4) {
+		case 1:
+			crop_height--;
+			break;
+		case 2:
+			crop_height += 2;
+			break;
+		case 3:
+			crop_height++;
+			break;
+		}
+		if ((crop_height < (ori_height / 4)) ||
+			(crop_width < (ori_width / 4))) {
+			crop_width = ori_width/4;
+			crop_height = ori_height/4;
+		}
+		crop_offset_x = (ori_width - crop_width)/2;
+		crop_offset_y = (ori_height - crop_height)/2;
+		dev->sensor.zoom_out_width = crop_width;
+		dev->sensor.zoom_out_height = crop_height;
+	}
+
+	dbg("Zoom out offset = %d, %d\n", crop_offset_x, crop_offset_y);
+	dbg("Zoom out = %d, %d\n", dev->sensor.zoom_out_width,
+					dev->sensor.zoom_out_height);
+
+	/* 2. stream off */
+	clear_bit(IS_ST_STREAM_ON, &dev->state);
+	fimc_is_hw_set_stream(dev, 0);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_STREAM_OFF, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev, "wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	clear_bit(IS_ST_STREAM_OFF, &dev->state);
+
+	/* 3. update input and output size of ISP,DRC and FD */
+	IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+	IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, ori_width);
+	IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, ori_height);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, crop_offset_x);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, crop_offset_y);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, crop_width);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, crop_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_CMD(dev, OTF_OUTPUT_COMMAND_ENABLE);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	/* DRC input / output*/
+	IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	/* FD input / output*/
+	IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, dev->sensor.zoom_out_width);
+	IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, dev->sensor.zoom_out_height);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	/* 4. Set parameter */
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+	fimc_is_hw_set_param(dev);
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev, "wait timeout : %s\n", __func__);
+		return -EBUSY;
+	}
+	/* 5. Mode change for getting CAC margin */
+	clear_bit(IS_ST_CHANGE_MODE, &dev->state);
+	fimc_is_hw_change_mode(dev, mode);
+	ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_CHANGE_MODE, &dev->state),
+				FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		dev_err(&dev->pdev->dev,
+			"Mode change timeout:%s\n", __func__);
+		return -EBUSY;
+	}
+	set_bit(IS_ST_SET_ZOOM, &dev->state);
+	return 0;
+}
+
+static int fimc_is_v4l2_isp_scene_mode(struct fimc_is_dev *dev, int mode)
+{
+	int ret = 0;
+	switch (mode) {
+	case SCENE_MODE_NONE:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+				ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_PORTRAIT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -1);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -1);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_LANDSCAPE:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_MATRIX);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_SPORTS:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 400);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_PARTY_INDOOR:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 200);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_BEACH_SNOW:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 50);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_SUNSET:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev, ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+				ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_DUSK_DAWN:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev,
+				ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_FLUORESCENT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_FALL_COLOR:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_NIGHTSHOT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_BACK_LIGHT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	/* FIXME add with SCENE_MODE_BACK_LIGHT (FLASH mode) */
+	case SCENE_MODE_FIREWORKS:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 50);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+				ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_TEXT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+			ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 2);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+		IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case SCENE_MODE_CANDLE_LIGHT:
+		/* ISO */
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		IS_ISP_SET_PARAM_ISO_ERR(dev, ISP_ISO_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		/* Metering */
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_METERING_ERR(dev,
+				ISP_METERING_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		/* AWB */
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_DAYLIGHT);
+		IS_ISP_SET_PARAM_AWB_ERR(dev, ISP_AWB_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		/* Adjust */
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_MANUAL_ALL);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_ERR(dev, ISP_ADJUST_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		/* Flash */
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_ERR(dev, ISP_FLASH_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		/* AF */
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+		IS_ISP_SET_PARAM_AA_SCENE(dev, ISP_AF_SCENE_NORMAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_ISP_SET_PARAM_AA_ERR(dev, ISP_AF_ERROR_NO);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+int fimc_is_wait_af_done(struct fimc_is_dev *dev)
+{
+	unsigned long timeo = jiffies + 600; /* timeout of 3sec */
+
+	while (time_before(jiffies, timeo)) {
+		fimc_is_mem_cache_inv((void *)IS_SHARED,
+			(unsigned long)(sizeof(struct is_share_region)));
+		if (dev->is_shared_region->af_status) {
+			dbg("AF done : %d ms\n",
+				jiffies_to_msecs(jiffies - timeo + 600));
+			return 0;
+		}
+		msleep(20);
+	}
+	err("AF wait time out: %d ms\n",
+		jiffies_to_msecs(jiffies - timeo + 600));
+
+	return 0;
+}
+
+int fimc_is_af_face(struct fimc_is_dev *dev)
+{
+	int ret = 0, max_confidence = 0, i = 0;
+	int width, height;
+	u32 touch_x = 0, touch_y = 0;
+
+	for (i = dev->fd_header.index;
+		i < (dev->fd_header.index + dev->fd_header.count); i++) {
+		if (max_confidence < dev->is_p_region->face[i].confidence) {
+			max_confidence = dev->is_p_region->face[i].confidence;
+			touch_x = dev->is_p_region->face[i].face.offset_x +
+				(dev->is_p_region->face[i].face.width / 2);
+			touch_y = dev->is_p_region->face[i].face.offset_y +
+				(dev->is_p_region->face[i].face.height / 2);
+		}
+	}
+	width = fimc_is_hw_get_sensor_size_width(dev);
+	height = fimc_is_hw_get_sensor_size_height(dev);
+	touch_x = 1024 *  touch_x / (u32)width;
+	touch_y = 1024 *  touch_y / (u32)height;
+
+	if ((touch_x == 0) || (touch_y == 0) || (max_confidence < 50))
+		return ret;
+
+	if (dev->af.prev_pos_x == 0 && dev->af.prev_pos_y == 0) {
+		dev->af.prev_pos_x = touch_x;
+		dev->af.prev_pos_y = touch_y;
+	} else {
+		if (abs(dev->af.prev_pos_x - touch_x) < 100 &&
+			abs(dev->af.prev_pos_y - touch_y) < 100) {
+			return ret;
+		}
+		dbg("AF Face level = %d\n", max_confidence);
+		dbg("AF Face = <%d, %d>\n", touch_x, touch_y);
+		dbg("AF Face = prev <%d, %d>\n",
+				dev->af.prev_pos_x, dev->af.prev_pos_y);
+		dev->af.prev_pos_x = touch_x;
+		dev->af.prev_pos_y = touch_y;
+	}
+
+	IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+	IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+	IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_TOUCH);
+	IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+	IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+	IS_ISP_SET_PARAM_AA_TOUCH_X(dev, touch_x);
+	IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, touch_y);
+	IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+	IS_INC_PARAM_NUM(dev);
+	dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	fimc_is_hw_set_param(dev);
+
+	return ret;
+}
+
+static int fimc_is_v4l2_af_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case FOCUS_MODE_AUTO:
+		dev->af.mode = IS_FOCUS_MODE_AUTO;
+		break;
+	case FOCUS_MODE_MACRO:
+		dev->af.mode = IS_FOCUS_MODE_MACRO;
+		break;
+	case FOCUS_MODE_INFINITY:
+		dev->af.mode = IS_FOCUS_MODE_INFINITY;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_MANUAL);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case FOCUS_MODE_CONTINOUS:
+		dev->af.mode = IS_FOCUS_MODE_CONTINUOUS;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_CONTINUOUS);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		dev->af.prev_pos_x = 0;
+		dev->af.prev_pos_y = 0;
+		break;
+	case FOCUS_MODE_TOUCH:
+		dev->af.mode = IS_FOCUS_MODE_TOUCH;
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+		IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_TOUCH);
+		IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+		IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+		IS_ISP_SET_PARAM_AA_TOUCH_X(dev, dev->af.pos_x);
+		IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, dev->af.pos_y);
+		IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		dev->af.af_state = FIMC_IS_AF_SETCONFIG;
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		break;
+	case FOCUS_MODE_FACEDETECT:
+		dev->af.mode = IS_FOCUS_MODE_FACEDETECT;
+		dev->af.af_lock_state = 0;
+		dev->af.ae_lock_state = 0;
+		dev->af.awb_lock_state = 0;
+		dev->af.prev_pos_x = 0;
+		dev->af.prev_pos_y = 0;
+		break;
+	default:
+		return ret;
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_af_start_stop(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case AUTO_FOCUS_OFF:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_IDLE;
+		} else {
+			if (dev->af.af_state == FIMC_IS_AF_IDLE)
+				return ret;
+			/* Abort or lock AF */
+			dev->af.af_state = FIMC_IS_AF_ABORT;
+			IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			switch (dev->af.mode) {
+			case IS_FOCUS_MODE_AUTO:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_SINGLE);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+					break;
+			case IS_FOCUS_MODE_MACRO:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_SINGLE);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_MACRO);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+					ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue1,
+				(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			case IS_FOCUS_MODE_CONTINUOUS:
+				IS_ISP_SET_PARAM_AA_MODE(dev,
+					ISP_AF_MODE_CONTINUOUS);
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_ISP_SET_PARAM_AA_SLEEP(dev,
+						ISP_AF_SLEEP_OFF);
+				IS_ISP_SET_PARAM_AA_FACE(dev,
+					ISP_AF_FACE_DISABLE);
+				IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+				IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+				IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue1,
+				(dev->af.af_state == FIMC_IS_AF_IDLE), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			default:
+				/* If other AF mode, there is no
+				cancelation process*/
+				break;
+			}
+			dev->af.mode = IS_FOCUS_MODE_IDLE;
+		}
+		break;
+	case AUTO_FOCUS_ON:
+		if (!is_af_use(dev)) {
+			/* 6A3 can't support AF */
+			dev->af.af_state = FIMC_IS_AF_LOCK;
+			dev->af.af_lock_state = FIMC_IS_AF_LOCKED;
+			dev->is_shared_region->af_status = 1;
+			fimc_is_mem_cache_clean((void *)IS_SHARED,
+			(unsigned long)(sizeof(struct is_share_region)));
+		} else {
+			dev->af.af_lock_state = 0;
+			dev->af.ae_lock_state = 0;
+			dev->af.awb_lock_state = 0;
+			dev->is_shared_region->af_status = 0;
+			fimc_is_mem_cache_clean((void *)IS_SHARED,
+			(unsigned long)(sizeof(struct is_share_region)));
+			IS_ISP_SET_PARAM_AA_CMD(dev,
+			ISP_AA_COMMAND_START);
+			IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AF);
+			IS_ISP_SET_PARAM_AA_MODE(dev, ISP_AF_MODE_SINGLE);
+			IS_ISP_SET_PARAM_AA_SLEEP(dev, ISP_AF_SLEEP_OFF);
+			IS_ISP_SET_PARAM_AA_FACE(dev, ISP_AF_FACE_DISABLE);
+			IS_ISP_SET_PARAM_AA_TOUCH_X(dev, 0);
+			IS_ISP_SET_PARAM_AA_TOUCH_Y(dev, 0);
+			IS_ISP_SET_PARAM_AA_MANUAL_AF(dev, 0);
+			switch (dev->af.mode) {
+			case IS_FOCUS_MODE_AUTO:
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_NORMAL);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				dev->af.af_state =
+						FIMC_IS_AF_SETCONFIG;
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue1,
+				(dev->af.af_state == FIMC_IS_AF_RUNNING), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			case IS_FOCUS_MODE_MACRO:
+				IS_ISP_SET_PARAM_AA_SCENE(dev,
+					ISP_AF_SCENE_MACRO);
+				IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+				IS_INC_PARAM_NUM(dev);
+				dev->af.af_state =
+						FIMC_IS_AF_SETCONFIG;
+				fimc_is_mem_cache_clean(
+					(void *)dev->is_p_region,
+					IS_PARAM_SIZE);
+				fimc_is_hw_set_param(dev);
+				ret = wait_event_timeout(dev->irq_queue1,
+				(dev->af.af_state == FIMC_IS_AF_RUNNING), HZ/5);
+				if (!ret) {
+					dev_err(&dev->pdev->dev,
+					"Focus change timeout:%s\n", __func__);
+					return -EBUSY;
+				}
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_iso(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case ISO_AUTO:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 0);
+		break;
+	case ISO_100:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 100);
+		break;
+	case ISO_200:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 200);
+		break;
+	case ISO_400:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 400);
+		break;
+	case ISO_800:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 800);
+		break;
+	case ISO_1600:
+		IS_ISP_SET_PARAM_ISO_CMD(dev, ISP_ISO_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_ISO_VALUE(dev, 1600);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= ISO_AUTO && value < ISO_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ISO);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_effect(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_IMAGE_EFFECT_DISABLE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_DISABLE);
+		break;
+	case IS_IMAGE_EFFECT_MONOCHROME:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_MONOCHROME);
+		break;
+	case IS_IMAGE_EFFECT_NEGATIVE_MONO:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_MONO);
+		break;
+	case IS_IMAGE_EFFECT_NEGATIVE_COLOR:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_COLOR);
+		break;
+	case IS_IMAGE_EFFECT_SEPIA:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_SEPIA);
+		break;
+	}
+	/* only ISP effect in Pegasus */
+	if (value >= 0 && value < 5) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_effect_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IMAGE_EFFECT_NONE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_DISABLE);
+		break;
+	case IMAGE_EFFECT_BNW:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_MONOCHROME);
+		break;
+	case IMAGE_EFFECT_NEGATIVE:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev,
+			ISP_IMAGE_EFFECT_NEGATIVE_COLOR);
+		break;
+	case IMAGE_EFFECT_SEPIA:
+		IS_ISP_SET_PARAM_EFFECT_CMD(dev, ISP_IMAGE_EFFECT_SEPIA);
+		break;
+	default:
+		return ret;
+	}
+	/* only ISP effect in Pegasus */
+	if (value > IMAGE_EFFECT_BASE && value < IMAGE_EFFECT_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_IMAGE_EFFECT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return 0;
+		}
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_flash_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case FLASH_MODE_OFF:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	case FLASH_MODE_AUTO:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_ENABLE);
+		break;
+	case FLASH_MODE_ON:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_MANUALON);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	case FLASH_MODE_TORCH:
+		IS_ISP_SET_PARAM_FLASH_CMD(dev, ISP_FLASH_COMMAND_TORCH);
+		IS_ISP_SET_PARAM_FLASH_REDEYE(dev, ISP_FLASH_REDEYE_DISABLE);
+		break;
+	default:
+		return ret;
+	}
+	if (value > FLASH_MODE_BASE && value < FLASH_MODE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_FLASH);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_awb_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_AWB_AUTO:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, 0);
+		break;
+	case IS_AWB_DAYLIGHT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		break;
+	case IS_AWB_CLOUDY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_CLOUDY);
+		break;
+	case IS_AWB_TUNGSTEN:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_TUNGSTEN);
+		break;
+	case IS_AWB_FLUORESCENT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_FLUORESCENT);
+		break;
+	}
+	if (value >= IS_AWB_AUTO && value < IS_AWB_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_awb_mode_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case WHITE_BALANCE_AUTO:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, 0);
+		break;
+	case WHITE_BALANCE_SUNNY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_DAYLIGHT);
+		break;
+	case WHITE_BALANCE_CLOUDY:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+				ISP_AWB_ILLUMINATION_CLOUDY);
+		break;
+	case WHITE_BALANCE_TUNGSTEN:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_TUNGSTEN);
+		break;
+	case WHITE_BALANCE_FLUORESCENT:
+		IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_ILLUMINATION);
+		IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev,
+			ISP_AWB_ILLUMINATION_FLUORESCENT);
+		break;
+	}
+	if (value > WHITE_BALANCE_BASE && value < WHITE_BALANCE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return 0;
+		}
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_contrast(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_CONTRAST_AUTO:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev, ISP_ADJUST_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		break;
+	case IS_CONTRAST_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -2);
+		break;
+	case IS_CONTRAST_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -1);
+		break;
+	case IS_CONTRAST_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		break;
+	case IS_CONTRAST_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		break;
+	case IS_CONTRAST_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_CONTRAST_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_contrast_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case CONTRAST_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -2);
+		break;
+	case CONTRAST_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, -1);
+		break;
+	case CONTRAST_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 0);
+		break;
+	case CONTRAST_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 1);
+		break;
+	case CONTRAST_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_CONTRAST);
+		IS_ISP_SET_PARAM_ADJUST_CONTRAST(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < CONTRAST_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_saturation(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case SATURATION_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -2);
+		break;
+	case SATURATION_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, -1);
+		break;
+	case SATURATION_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 0);
+		break;
+	case SATURATION_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 1);
+		break;
+	case SATURATION_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SATURATION);
+		IS_ISP_SET_PARAM_ADJUST_SATURATION(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < SATURATION_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_sharpness(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+
+	switch (value) {
+	case SHARPNESS_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -2);
+		break;
+	case SHARPNESS_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, -1);
+		break;
+	case SHARPNESS_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 0);
+		break;
+	case SHARPNESS_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 1);
+		break;
+	case SHARPNESS_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_SHARPNESS);
+		IS_ISP_SET_PARAM_ADJUST_SHARPNESS(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < SHARPNESS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_exposure(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_EXPOSURE_MINUS_4:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -4);
+		break;
+	case IS_EXPOSURE_MINUS_3:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -3);
+		break;
+	case IS_EXPOSURE_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -2);
+		break;
+	case IS_EXPOSURE_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, -1);
+		break;
+	case IS_EXPOSURE_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+		break;
+	case IS_EXPOSURE_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 1);
+		break;
+	case IS_EXPOSURE_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 2);
+		break;
+	case IS_EXPOSURE_PLUS_3:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 3);
+		break;
+	case IS_EXPOSURE_PLUS_4:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 4);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_EXPOSURE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_exposure_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	if (value >= -4 && value < 5) {
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+		IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_brightness(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_BRIGHTNESS_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, -2);
+		break;
+	case IS_BRIGHTNESS_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, -1);
+		break;
+	case IS_BRIGHTNESS_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 0);
+		break;
+	case IS_BRIGHTNESS_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 1);
+		break;
+	case IS_BRIGHTNESS_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS);
+		IS_ISP_SET_PARAM_ADJUST_BRIGHTNESS(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_BRIGHTNESS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_hue(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_HUE_MINUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, -2);
+		break;
+	case IS_HUE_MINUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, -1);
+		break;
+	case IS_HUE_DEFAULT:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 0);
+		break;
+	case IS_HUE_PLUS_1:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 1);
+		break;
+	case IS_HUE_PLUS_2:
+		IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_HUE);
+		IS_ISP_SET_PARAM_ADJUST_HUE(dev, 2);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= IS_HUE_MINUS_2 && value < IS_HUE_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_metering(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_METERING_AVERAGE:
+		IS_ISP_SET_PARAM_METERING_CMD(dev,
+			ISP_METERING_COMMAND_AVERAGE);
+		break;
+	case IS_METERING_SPOT:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_SPOT);
+		break;
+	case IS_METERING_MATRIX:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_MATRIX);
+		break;
+	case IS_METERING_CENTER:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_CENTER);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_METERING_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_metering_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case METERING_CENTER:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_CENTER);
+		break;
+	case METERING_SPOT:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_SPOT);
+		break;
+	case METERING_MATRIX:
+		IS_ISP_SET_PARAM_METERING_CMD(dev, ISP_METERING_COMMAND_MATRIX);
+		break;
+	default:
+		return ret;
+	}
+	if (value > METERING_BASE && value < METERING_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_METERING);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_afc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_AFC_DISABLE:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case IS_AFC_AUTO:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case IS_AFC_MANUAL_50HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_50HZ);
+		break;
+	case IS_AFC_MANUAL_60HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_60HZ);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_AFC_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_isp_afc_legacy(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case ANTI_BANDING_OFF:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case ANTI_BANDING_AUTO:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_AUTO);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, 0);
+		break;
+	case ANTI_BANDING_50HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_50HZ);
+		break;
+	case ANTI_BANDING_60HZ:
+		IS_ISP_SET_PARAM_AFC_CMD(dev, ISP_AFC_COMMAND_MANUAL);
+		IS_ISP_SET_PARAM_AFC_MANUAL(dev, ISP_AFC_MANUAL_60HZ);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= ANTI_BANDING_OFF && value <= ANTI_BANDING_60HZ) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AFC);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_fd_angle_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_FD_ROLL_ANGLE_BASIC:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ROLL_ANGLE);
+		IS_FD_SET_PARAM_FD_CONFIG_ROLL_ANGLE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_YAW_ANGLE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_YAW_ANGLE);
+		IS_FD_SET_PARAM_FD_CONFIG_YAW_ANGLE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_SMILE_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_SMILE_MODE);
+		IS_FD_SET_PARAM_FD_CONFIG_SMILE_MODE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_BLINK_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_BLINK_MODE);
+		IS_FD_SET_PARAM_FD_CONFIG_BLINK_MODE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_EYE_DETECT_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_EYES_DETECT);
+		IS_FD_SET_PARAM_FD_CONFIG_EYE_DETECT(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_MOUTH_DETECT_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_MOUTH_DETECT);
+		IS_FD_SET_PARAM_FD_CONFIG_MOUTH_DETECT(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_ORIENTATION_MODE:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ORIENTATION);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case V4L2_CID_IS_FD_SET_ORIENTATION:
+		IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE);
+		IS_FD_SET_PARAM_FD_CONFIG_ORIENTATION_VALUE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_frame_rate(struct fimc_is_dev *dev, int value)
+{
+	int i, ret = 0;
+	int width, height, format;
+
+	width = fimc_is_hw_get_sensor_size_width(dev);
+	height = fimc_is_hw_get_sensor_size_height(dev);
+	format = fimc_is_hw_get_sensor_format(dev);
+	dev->sensor.framerate_update = true;
+
+	switch (value) {
+	case FRAME_RATE_AUTO: /* FRAME_RATE_AUTO */
+		i = fimc_is_hw_get_sensor_max_framerate(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, i);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 66666);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	case FRAME_RATE_7: /* FRAME_RATE_7 */
+		IS_SENSOR_SET_FRAME_RATE(dev, 7);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 124950);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	case FRAME_RATE_15: /* FRAME_RATE_15 */
+		IS_SENSOR_SET_FRAME_RATE(dev, 15);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 66666);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	case FRAME_RATE_20: /* FRAME_RATE_20 */
+		IS_SENSOR_SET_FRAME_RATE(dev, 20);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 50000);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	case FRAME_RATE_30: /* FRAME_RATE_30 */
+		IS_SENSOR_SET_FRAME_RATE(dev, 30);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 33333);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	case FRAME_RATE_60: /* FRAME_RATE_60 */
+		IS_SENSOR_SET_FRAME_RATE(dev, 60);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 16666);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	default:
+		IS_SENSOR_SET_FRAME_RATE(dev, value);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+							(u32)(1000000/value));
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		break;
+	}
+
+	return ret;
+}
+
+static int fimc_is_v4l2_ae_awb_lockunlock(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case AE_UNLOCK_AWB_UNLOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_LOCK_AWB_UNLOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_UNLOCK_AWB_LOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_START);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	case AE_LOCK_AWB_LOCK:
+		IS_ISP_SET_PARAM_AA_CMD(dev, ISP_AA_COMMAND_STOP);
+		IS_ISP_SET_PARAM_AA_TARGET(dev, ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_AA);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_set_isp(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_ISP_BYPASS_DISABLE:
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+		break;
+	case IS_ISP_BYPASS_ENABLE:
+		IS_ISP_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_ISP_BYPASS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_set_drc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_DRC_BYPASS_DISABLE:
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_DISABLE);
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	case IS_DRC_BYPASS_ENABLE:
+		IS_DRC_SET_PARAM_CONTROL_BYPASS(dev, CONTROL_BYPASS_ENABLE);
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_DRC_BYPASS_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_cmd_isp(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_ISP_COMMAND_STOP:
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_ISP_COMMAND_START:
+		IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	default:
+		return ret;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_cmd_drc(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_DRC_COMMAND_STOP:
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_DRC_COMMAND_START:
+		IS_DRC_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_DRC_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_cmd_fd(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	switch (value) {
+	case IS_FD_COMMAND_STOP:
+		dbg("IS_FD_COMMAND_STOP\n");
+		IS_FD_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+		break;
+	case IS_FD_COMMAND_START:
+		dbg("IS_FD_COMMAND_START\n");
+		IS_FD_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_START);
+		break;
+	}
+	if (value >= 0 && value < IS_ISP_COMMAND_MAX) {
+		IS_SET_PARAM_BIT(dev, PARAM_FD_CONTROL);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(dev);
+	}
+	return ret;
+}
+
+static int fimc_is_v4l2_shot_mode(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	IS_SET_PARAM_GLOBAL_SHOTMODE_CMD(dev, value);
+	IS_SET_PARAM_BIT(dev, PARAM_GLOBAL_SHOTMODE);
+	IS_INC_PARAM_NUM(dev);
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	fimc_is_hw_set_param(dev);
+	return ret;
+}
+
+static int fimc_is_v4l2_mode_change(struct fimc_is_dev *dev, int value)
+{
+	int ret = 0;
+	if (!test_bit(IS_ST_INIT_DONE, &dev->state)) {
+		err("Not init done state!!\n");
+		return -EINVAL;
+	}
+	clear_bit(IS_ST_CHANGE_MODE, &dev->state);
+	fimc_is_hw_change_mode(dev, value);
+	ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_CHANGE_MODE, &dev->state),
+						FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("Mode change timeout !!\n");
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	printk(KERN_INFO "CAC margin - %d, %d\n", dev->sensor.offset_x,
+							dev->sensor.offset_y);
+	return ret;
+}
+
+static int fimc_is_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	int ret = 0;
+	int i;
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+
+	switch (ctrl->id) {
+	case V4L2_CID_IS_S_SCENARIO_MODE:
+		ret = fimc_is_v4l2_mode_change(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_S_FORMAT_SCENARIO:
+		/* Set default value between still and video mode change */
+		/* This is optional part */
+		if ((dev->scenario_id + ctrl->value) == 1) {
+			IS_ISP_SET_PARAM_AWB_CMD(dev, ISP_AWB_COMMAND_AUTO);
+			IS_ISP_SET_PARAM_AWB_ILLUMINATION(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_AWB);
+			IS_INC_PARAM_NUM(dev);
+			IS_ISP_SET_PARAM_ADJUST_CMD(dev,
+					ISP_ADJUST_COMMAND_MANUAL_EXPOSURE);
+			IS_ISP_SET_PARAM_ADJUST_EXPOSURE(dev, 0);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_ADJUST);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		switch (ctrl->value) {
+		case IS_MODE_PREVIEW_STILL:
+			dev->scenario_id = ISS_PREVIEW_STILL;
+			break;
+		case IS_MODE_PREVIEW_VIDEO:
+			dev->scenario_id = ISS_PREVIEW_VIDEO;
+			break;
+		case IS_MODE_CAPTURE_STILL:
+			dev->scenario_id = ISS_CAPTURE_STILL;
+			break;
+		case IS_MODE_CAPTURE_VIDEO:
+			dev->scenario_id = ISS_CAPTURE_VIDEO;
+			break;
+		default:
+			return -EBUSY;
+		}
+		break;
+	case V4L2_CID_IS_CAMERA_SHOT_MODE_NORMAL:
+		ret = fimc_is_v4l2_shot_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_FRAME_RATE:
+		ret = fimc_is_v4l2_frame_rate(dev, ctrl->value);
+		break;
+	/* Focus */
+	case V4L2_CID_IS_CAMERA_OBJECT_POSITION_X:
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		dev->af.pos_x = ctrl->value;
+		break;
+	case V4L2_CID_IS_CAMERA_OBJECT_POSITION_Y:
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		dev->af.pos_y = ctrl->value;
+		break;
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		ret = fimc_is_v4l2_af_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		ret = fimc_is_v4l2_af_start_stop(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		switch (ctrl->value) {
+		case TOUCH_AF_STOP:
+			break;
+		case TOUCH_AF_START:
+			break;
+		default:
+			break;
+		}
+		break;
+	case V4L2_CID_CAMERA_CAF_START_STOP:
+		switch (ctrl->value) {
+		case CAF_STOP:
+			break;
+		case CAF_START:
+			break;
+		default:
+			break;
+		}
+		break;
+	/* AWB, AE Lock/Unlock */
+	case V4L2_CID_CAMERA_AEAWB_LOCK_UNLOCK:
+		ret = fimc_is_v4l2_ae_awb_lockunlock(dev, ctrl->value);
+		break;
+	/* FLASH */
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		ret = fimc_is_v4l2_isp_flash_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_AWB_MODE:
+		ret = fimc_is_v4l2_awb_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		ret = fimc_is_v4l2_awb_mode_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_EFFECT:
+		ret = fimc_is_v4l2_isp_effect_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_IMAGE_EFFECT:
+		ret = fimc_is_v4l2_isp_effect(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_ISO:
+	case V4L2_CID_CAMERA_ISO:
+		ret = fimc_is_v4l2_isp_iso(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_CONTRAST:
+		ret = fimc_is_v4l2_isp_contrast_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_CONTRAST:
+		ret = fimc_is_v4l2_isp_contrast(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_SATURATION:
+	case V4L2_CID_CAMERA_SATURATION:
+		ret = fimc_is_v4l2_isp_saturation(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_SHARPNESS:
+	case V4L2_CID_CAMERA_SHARPNESS:
+		ret = fimc_is_v4l2_isp_sharpness(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_EXPOSURE:
+		ret = fimc_is_v4l2_isp_exposure(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		ret = fimc_is_v4l2_isp_exposure_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_BRIGHTNESS:
+		ret = fimc_is_v4l2_isp_brightness(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_HUE:
+		ret = fimc_is_v4l2_isp_hue(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_METERING:
+		ret = fimc_is_v4l2_isp_metering_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING:
+		ret = fimc_is_v4l2_isp_metering(dev, ctrl->value);
+		break;
+	/* Ony valid at SPOT Mode */
+	case V4L2_CID_IS_CAMERA_METERING_POSITION_X:
+		IS_ISP_SET_PARAM_METERING_WIN_POS_X(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_POSITION_Y:
+		IS_ISP_SET_PARAM_METERING_WIN_POS_Y(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_WINDOW_X:
+		IS_ISP_SET_PARAM_METERING_WIN_WIDTH(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_METERING_WINDOW_Y:
+		IS_ISP_SET_PARAM_METERING_WIN_HEIGHT(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		ret = fimc_is_v4l2_isp_afc_legacy(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CAMERA_AFC_MODE:
+		ret = fimc_is_v4l2_isp_afc(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_FD_SET_MAX_FACE_NUMBER:
+		if (ctrl->value >= 0) {
+			IS_FD_SET_PARAM_FD_CONFIG_CMD(dev,
+				FD_CONFIG_COMMAND_MAXIMUM_NUMBER);
+			IS_FD_SET_PARAM_FD_CONFIG_MAX_NUMBER(dev, ctrl->value);
+			IS_SET_PARAM_BIT(dev, PARAM_FD_CONFIG);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+				IS_PARAM_SIZE);
+			fimc_is_hw_set_param(dev);
+		}
+		break;
+	case V4L2_CID_IS_FD_SET_ROLL_ANGLE:
+		ret = fimc_is_v4l2_fd_angle_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_FD_SET_DATA_ADDRESS:
+		dev->fd_header.target_addr = ctrl->value;
+		break;
+	case V4L2_CID_IS_SET_ISP:
+		ret = fimc_is_v4l2_set_isp(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_SET_DRC:
+		ret = fimc_is_v4l2_set_drc(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_ISP:
+		ret = fimc_is_v4l2_cmd_isp(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_DRC:
+		ret = fimc_is_v4l2_cmd_drc(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_CMD_FD:
+		ret = fimc_is_v4l2_cmd_fd(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_SET_FRAME_NUMBER:
+		dev->frame_count = ctrl->value + 1;
+		dev->is_p_region->header[0].valid = 0;
+		dev->is_p_region->header[1].valid = 0;
+		dev->is_p_region->header[2].valid = 0;
+		dev->is_p_region->header[3].valid = 0;
+		fimc_is_mem_cache_clean((void *)IS_HEADER, IS_PARAM_SIZE);
+		break;
+	case V4L2_CID_IS_SET_FRAME_VALID:
+		if ((dev->scenario_id == ISS_CAPTURE_STILL)
+			|| (dev->scenario_id == ISS_CAPTURE_VIDEO)) {
+			dev->is_p_region->header[0].valid = ctrl->value;
+			dev->is_p_region->header[0].bad_mark = ctrl->value;
+			dev->is_p_region->header[0].captured = ctrl->value;
+		} else {
+			dev->is_p_region->header[dev->frame_count%
+				MAX_FRAME_COUNT_PREVIEW].valid = ctrl->value;
+			dev->is_p_region->header[dev->frame_count%
+			MAX_FRAME_COUNT_PREVIEW].bad_mark = ctrl->value;
+			dev->is_p_region->header[dev->frame_count%
+			MAX_FRAME_COUNT_PREVIEW].captured = ctrl->value;
+		}
+		dev->frame_count++;
+		fimc_is_mem_cache_clean((void *)IS_HEADER, IS_PARAM_SIZE);
+		break;
+	case V4L2_CID_IS_SET_FRAME_BADMARK:
+		break;
+	case V4L2_CID_IS_SET_FRAME_CAPTURED:
+		break;
+	case V4L2_CID_IS_CLEAR_FRAME_NUMBER:
+		if (dev->scenario_id == ISS_CAPTURE_STILL) {
+			dev->is_p_region->header[0].valid = 0;
+			dev->is_p_region->header[0].bad_mark = 0;
+			dev->is_p_region->header[0].captured = 0;
+		} else if (dev->scenario_id == ISS_CAPTURE_VIDEO) {
+			dev->is_p_region->header[0].valid = 0;
+			dev->is_p_region->header[0].bad_mark = 0;
+			dev->is_p_region->header[0].captured = 0;
+		} else {
+			for (i = 0; i < MAX_FRAME_COUNT_PREVIEW; i++) {
+				if (dev->is_p_region->header[i].frame_number <
+					dev->frame_count) {
+					dev->is_p_region->header[i].valid = 0;
+					dev->is_p_region->header[i].
+						bad_mark = 0;
+					dev->is_p_region->header[i].
+						captured = 0;
+				}
+			}
+		}
+		fimc_is_mem_cache_clean((void *)IS_HEADER, IS_PARAM_SIZE);
+		break;
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		ret = fimc_is_v4l2_isp_scene_mode(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_ZOOM:
+		ret = fimc_is_v4l2_digital_zoom(dev, ctrl->value);
+		break;
+	case V4L2_CID_CAMERA_VT_MODE:
+		dev->setfile.sub_index = ctrl->value;
+		printk(KERN_INFO "VT mode(%d) is selected\n",
+						dev->setfile.sub_index);
+		break;
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		break;
+	default:
+		dbg("Invalid control\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_is_g_ext_ctrls_handler(struct fimc_is_dev *dev,
+	struct v4l2_ext_control *ctrl, int index)
+{
+	int ret = 0;
+	u32 tmp = 0;
+	switch (ctrl->id) {
+	/* Face Detection CID handler */
+	/* 1. Overall information */
+	case V4L2_CID_IS_FD_GET_FACE_COUNT:
+		ctrl->value = dev->fd_header.count;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_FRAME_NUMBER:
+		if (dev->fd_header.offset < dev->fd_header.count) {
+			ctrl->value =
+				dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].frame_number;
+		} else {
+			ctrl->value = 0;
+			return -255;
+		}
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_CONFIDENCE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].confidence;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_SMILE_LEVEL:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].smile_level;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BLINK_LEVEL:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].blink_level;
+		break;
+	/* 2. Face information */
+	case V4L2_CID_IS_FD_GET_FACE_TOPLEFT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.offset_x;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_TOPLEFT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.offset_y;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BOTTOMRIGHT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.width;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_FACE_BOTTOMRIGHT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+					+ dev->fd_header.offset].face.height;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	/* 3. Left eye information */
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_TOPLEFT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.offset_x;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_TOPLEFT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.offset_y;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_BOTTOMRIGHT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.width;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_LEFT_EYE_BOTTOMRIGHT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].left_eye.height;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	/* 4. Right eye information */
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_TOPLEFT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.offset_x;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_TOPLEFT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.offset_y;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_BOTTOMRIGHT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.width;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_RIGHT_EYE_BOTTOMRIGHT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].right_eye.height;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	/* 5. Mouth eye information */
+	case V4L2_CID_IS_FD_GET_MOUTH_TOPLEFT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.offset_x;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_TOPLEFT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.offset_y;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_BOTTOMRIGHT_X:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.offset_x
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.width;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.width;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	case V4L2_CID_IS_FD_GET_MOUTH_BOTTOMRIGHT_Y:
+		tmp = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.offset_y
+			+ dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].mouth.height;
+		tmp = (tmp * 2 * GED_FD_RANGE) /  dev->fd_header.height;
+		ctrl->value = (s32)tmp - GED_FD_RANGE;
+		break;
+	/* 6. Angle information */
+	case V4L2_CID_IS_FD_GET_ANGLE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].roll_angle;
+		break;
+	case V4L2_CID_IS_FD_GET_YAW_ANGLE:
+		ctrl->value = dev->is_p_region->face[dev->fd_header.index
+				+ dev->fd_header.offset].yaw_angle;
+		break;
+	/* 7. Update next face information */
+	case V4L2_CID_IS_FD_GET_NEXT:
+		dev->fd_header.offset++;
+		break;
+	case V4L2_CID_CAM_SENSOR_FW_VER:
+		strcpy(ctrl->string, dev->fw.fw_version);
+		break;
+	default:
+		return 255;
+		break;
+	}
+	return ret;
+}
+
+static int fimc_is_g_ext_ctrls(struct v4l2_subdev *sd,
+	struct v4l2_ext_controls *ctrls)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	struct v4l2_ext_control *ctrl;
+	int i, ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->slock, flags);
+	ctrl = ctrls->controls;
+	if (ctrls->ctrl_class != V4L2_CTRL_CLASS_CAMERA)
+		return -EINVAL;
+
+	fimc_is_mem_cache_inv((void *)IS_FACE,
+		(unsigned long)(sizeof(struct is_face_marker)*MAX_FACE_COUNT));
+
+	dev->fd_header.offset = 0;
+	/* get width and height at the current scenario */
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		dev->fd_header.width = (s32)dev->sensor.width_prev;
+		dev->fd_header.height = (s32)dev->sensor.height_prev;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		dev->fd_header.width = (s32)dev->sensor.width_prev_cam;
+		dev->fd_header.height = (s32)dev->sensor.height_prev_cam;
+		break;
+	case ISS_CAPTURE_STILL:
+		dev->fd_header.width = (s32)dev->sensor.width_cap;
+		dev->fd_header.height = (s32)dev->sensor.height_cap;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		dev->fd_header.width = (s32)dev->sensor.width_cam;
+		dev->fd_header.height = (s32)dev->sensor.height_cam;
+		break;
+	}
+	for (i = 0; i < ctrls->count; i++) {
+		ctrl = ctrls->controls + i;
+		ret = fimc_is_g_ext_ctrls_handler(dev, ctrl, i);
+		if (ret > 0) {
+			ctrls->error_idx = i;
+			break;
+		} else if (ret < 0) {
+			ret = 0;
+			break;
+		}
+	}
+
+	dev->fd_header.index = 0;
+	dev->fd_header.count = 0;
+	spin_unlock_irqrestore(&dev->slock, flags);
+	return ret;
+}
+
+static int fimc_is_s_ext_ctrls_handler(struct fimc_is_dev *dev,
+	struct v4l2_ext_control *ctrl)
+{
+	switch (ctrl->id) {
+	case V4L2_CID_IS_TUNE_SEL_ENTRY:
+		dev->h2i_cmd.entry_id = (0x1 << ctrl->value);
+		break;
+	case V4L2_CID_IS_TUNE_SENSOR_EXPOSURE:
+		IS_SENSOR_SET_TUNE_EXPOSURE(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_TUNE_SENSOR_ANALOG_GAIN:
+		IS_SENSOR_SET_TUNE_ANALOG_GAIN(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_TUNE_SENSOR_FRAME_RATE:
+		IS_SENSOR_SET_TUNE_FRAME_RATE(dev, ctrl->value);
+		break;
+	case V4L2_CID_IS_TUNE_SENSOR_ACTUATOR_POS:
+		if (!is_af_use(dev))
+			IS_SENSOR_SET_TUNE_ACTUATOR_POSITION(dev, 0);
+		else
+			IS_SENSOR_SET_TUNE_ACTUATOR_POSITION(dev, ctrl->value);
+		break;
+	default:
+		dbg("Invalid control\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int fimc_is_s_ext_ctrls(struct v4l2_subdev *sd,
+	struct v4l2_ext_controls *ctrls)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int i, ret = 0;
+
+	dbg("S_EXT_CTRLS - %d\n", ctrls->count);
+	if (ctrls->ctrl_class != V4L2_CTRL_CLASS_CAMERA)
+		return -EINVAL;
+
+	dev->h2i_cmd.cmd_type = 0;
+	dev->h2i_cmd.entry_id = 0;
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		ret = fimc_is_s_ext_ctrls_handler(dev, ctrl);
+		if (ret) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	fimc_is_hw_set_tune(dev);
+
+	return ret;
+}
+
+/* v4l2 subdev video operations
+*/
+static int fimc_is_try_mbus_fmt(struct v4l2_subdev *sd,
+struct v4l2_mbus_framefmt *mf)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	dbg("fimc_is_try_mbus_fmt - %d, %d\n", mf->width, mf->height);
+	switch (dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		dev->sensor.width_prev = mf->width;
+		dev->sensor.height_prev = mf->height;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		dev->sensor.width_prev_cam = mf->width;
+		dev->sensor.height_prev_cam = mf->height;
+		break;
+	case ISS_CAPTURE_STILL:
+		dev->sensor.width_cap = mf->width;
+		dev->sensor.height_cap = mf->height;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		dev->sensor.width_cam = mf->width;
+		dev->sensor.height_cam = mf->height;
+		break;
+	}
+	/* for otf, only one image format is available */
+	IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, mf->height);
+
+	IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, mf->width);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, mf->height);
+
+	IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	return 0;
+}
+
+static int fimc_is_g_mbus_fmt(struct v4l2_subdev *sd,
+	struct v4l2_mbus_framefmt *mf)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	dbg("fimc_is_g_mbus_fmt\n");
+	/* for otf, only one image format is available */
+	IS_DRC_GET_PARAM_OTF_OUTPUT_WIDTH(dev, mf->width);
+	IS_DRC_GET_PARAM_OTF_OUTPUT_HEIGHT(dev, mf->height);
+	mf->code = V4L2_MBUS_FMT_YUYV8_2X8;
+	mf->field = 0;
+	return 0;
+}
+
+static int fimc_is_s_mbus_fmt(struct v4l2_subdev *sd,
+	struct v4l2_mbus_framefmt *mf)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	int ret = 0, format;
+	u32 frametime_max = 0;
+
+	printk(KERN_INFO "FIMC-IS s_fmt = %d,%d\n", mf->width, mf->height);
+	/* scenario ID setting */
+	switch (mf->field) {
+	case 0:
+		dev->scenario_id = ISS_PREVIEW_STILL;
+		dev->sensor.width_prev = mf->width;
+		dev->sensor.height_prev = mf->height;
+		if (!dev->sensor.framerate_update)
+			frametime_max = dev->sensor.frametime_max_prev;
+		break;
+	case 1:
+		dev->scenario_id = ISS_PREVIEW_VIDEO;
+		dev->sensor.width_prev_cam = mf->width;
+		dev->sensor.height_prev_cam = mf->height;
+		if (!dev->sensor.framerate_update)
+			frametime_max = dev->sensor.frametime_max_prev_cam;
+		break;
+	case 2:
+		dev->scenario_id = ISS_CAPTURE_STILL;
+		dev->sensor.width_cap = mf->width;
+		dev->sensor.height_cap = mf->height;
+		if (!dev->sensor.framerate_update)
+			frametime_max = dev->sensor.frametime_max_cap;
+		break;
+	case 3:
+		dev->scenario_id = ISS_CAPTURE_VIDEO;
+		dev->sensor.width_cam = mf->width;
+		dev->sensor.height_cam = mf->height;
+		if (!dev->sensor.framerate_update)
+			frametime_max = dev->sensor.frametime_max_cam;
+		break;
+	default:
+		return ret;
+	}
+
+	format = fimc_is_hw_get_sensor_format(dev);
+	/* 1. ISP input / output*/
+	IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+	IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev, OTF_INPUT_BIT_WIDTH_10BIT);
+	IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev, OTF_INPUT_ORDER_BAYER_GR_BG);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+	IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+	if (!dev->sensor.framerate_update) {
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, frametime_max);
+	}
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT1_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA1_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(dev, mf->width);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_ISP_DMA2_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	/* 2. DRC input / output*/
+	IS_DRC_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_DRC_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_WIDTH(dev, mf->width);
+	IS_DRC_SET_PARAM_OTF_OUTPUT_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_DRC_OTF_OUTPUT);
+	IS_INC_PARAM_NUM(dev);
+	/* 3. FD input / output*/
+	IS_FD_SET_PARAM_OTF_INPUT_WIDTH(dev, mf->width);
+	IS_FD_SET_PARAM_OTF_INPUT_HEIGHT(dev, mf->height);
+	IS_SET_PARAM_BIT(dev, PARAM_FD_OTF_INPUT);
+	IS_INC_PARAM_NUM(dev);
+
+	fimc_is_mem_cache_clean((void *)dev->is_p_region, IS_PARAM_SIZE);
+	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+	fimc_is_hw_set_param(dev);
+	/* Below sequence is for preventing system hang
+		due to size mis-match */
+	ret = wait_event_timeout(dev->irq_queue1,
+		test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+		FIMC_IS_SHUTDOWN_TIMEOUT);
+	if (!ret) {
+		err("wait timeout : Set format - %d, %d\n",
+						mf->width, mf->height);
+		fimc_is_hw_set_low_poweroff(dev, true);
+		return -EINVAL;
+	}
+	dev->sensor.framerate_update = false;
+	return 0;
+}
+
+static int fimc_is_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	int ret = 0;
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+
+	if (enable) {
+		dbg("IS Stream On\n");
+		if (!test_bit(IS_ST_INIT_DONE, &dev->state)) {
+			err("Not ready state!!\n");
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_ON, &dev->state);
+		fimc_is_hw_set_stream(dev, enable);
+		ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_STREAM_ON, &dev->state),
+				FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			err("wait timeout : Stream on\n");
+			fimc_is_hw_set_low_poweroff(dev, true);
+			return -EINVAL;
+		}
+	} else {
+		dbg("IS Stream Off\n");
+		if (!test_bit(IS_ST_INIT_DONE, &dev->state)) {
+			err("Not ready state!!\n");
+			return -EBUSY;
+		}
+		clear_bit(IS_ST_STREAM_OFF, &dev->state);
+		fimc_is_hw_set_stream(dev, enable);
+		ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_STREAM_OFF, &dev->state),
+						FIMC_IS_SHUTDOWN_TIMEOUT);
+		if (!ret) {
+			err("wait timeout : Stream off\n");
+			printk(KERN_ERR "Low power off\n");
+			fimc_is_hw_set_low_poweroff(dev, true);
+			return -EINVAL;
+		}
+		dev->setfile.sub_index = 0;
+	}
+	return ret;
+}
+
+static int fimc_is_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct fimc_is_dev *dev = to_fimc_is_dev(sd);
+	u32 fps = 0;
+	int width, height, format;
+	int i, ret = 0;
+
+	if (a->parm.capture.timeperframe.numerator == 0)
+		fps = 0; /* prevent divide-by-0 error case */
+	else
+		fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	if (!test_bit(IS_ST_INIT_DONE, &dev->state)) {
+		printk(KERN_ERR "FIMC_IS ins not ready!!\n");
+		return -EBUSY;
+	}
+
+	width = fimc_is_hw_get_sensor_size_width(dev);
+	height = fimc_is_hw_get_sensor_size_height(dev);
+	format = fimc_is_hw_get_sensor_format(dev);
+	dev->sensor.framerate_update = true;
+	if (fps > 0) {
+		IS_SENSOR_SET_FRAME_RATE(dev, fps);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+			FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev,
+							(u32)(1000000/fps));
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+	} else {
+		/* Auto mode */
+		i = fimc_is_hw_get_sensor_max_framerate(dev);
+		IS_SENSOR_SET_FRAME_RATE(dev, i);
+		IS_SET_PARAM_BIT(dev, PARAM_SENSOR_FRAME_RATE);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev, CONTROL_COMMAND_STOP);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+		IS_ISP_SET_PARAM_OTF_INPUT_CMD(dev, OTF_INPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_OTF_INPUT_WIDTH(dev, width);
+		IS_ISP_SET_PARAM_OTF_INPUT_HEIGHT(dev, height);
+		IS_ISP_SET_PARAM_OTF_INPUT_FORMAT(dev, format);
+		IS_ISP_SET_PARAM_OTF_INPUT_BITWIDTH(dev,
+						OTF_INPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_OTF_INPUT_ORDER(dev,
+						OTF_INPUT_ORDER_BAYER_GR_BG);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_X(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_OFFSET_Y(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_WIDTH(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_CROP_HEIGHT(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MIN(dev, 0);
+		IS_ISP_SET_PARAM_OTF_INPUT_FRAMETIME_MAX(dev, 66666);
+		IS_SET_PARAM_BIT(dev, PARAM_ISP_OTF_INPUT);
+		IS_INC_PARAM_NUM(dev);
+		fimc_is_mem_cache_clean((void *)dev->is_p_region,
+							IS_PARAM_SIZE);
+		clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+		fimc_is_hw_set_param(dev);
+		ret = wait_event_timeout(dev->irq_queue1,
+			test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+		if (!ret) {
+			err("wait timeout : %s\n", __func__);
+			return -EINVAL;
+		}
+		if (test_bit(IS_ST_STREAM_ON, &dev->state)) {
+			IS_ISP_SET_PARAM_CONTROL_CMD(dev,
+						CONTROL_COMMAND_START);
+			IS_SET_PARAM_BIT(dev, PARAM_ISP_CONTROL);
+			IS_INC_PARAM_NUM(dev);
+			fimc_is_mem_cache_clean((void *)dev->is_p_region,
+								IS_PARAM_SIZE);
+			clear_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state);
+			fimc_is_hw_set_param(dev);
+			ret = wait_event_timeout(dev->irq_queue1,
+				test_bit(IS_ST_BLOCK_CMD_CLEARED, &dev->state),
+					FIMC_IS_SHUTDOWN_TIMEOUT_SENSOR);
+			if (!ret) {
+				err("wait timeout : %s\n", __func__);
+				return -EINVAL;
+			}
+		}
+	}
+	return ret;
+}
+
+const struct v4l2_subdev_core_ops fimc_is_core_ops = {
+	.load_fw = fimc_is_load_fw,
+	.init = fimc_is_init_set,
+	.reset = fimc_is_reset,
+	.s_power = fimc_is_s_power,
+	.g_ctrl = fimc_is_g_ctrl,
+	.s_ctrl = fimc_is_s_ctrl,
+	.g_ext_ctrls = fimc_is_g_ext_ctrls,
+	.s_ext_ctrls = fimc_is_s_ext_ctrls,
+};
+
+const struct v4l2_subdev_video_ops fimc_is_video_ops = {
+	.try_mbus_fmt	= fimc_is_try_mbus_fmt,
+	.g_mbus_fmt	= fimc_is_g_mbus_fmt,
+	.s_mbus_fmt	= fimc_is_s_mbus_fmt,
+	.s_stream	= fimc_is_s_stream,
+	.s_parm		= fimc_is_s_parm,
+};
+
+const struct v4l2_subdev_ops fimc_is_subdev_ops = {
+	.core	= &fimc_is_core_ops,
+	.video	= &fimc_is_video_ops,
+};
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-vb2.c b/drivers/media/video/exynos/fimc-is/fimc-is-vb2.c
new file mode 100644
index 0000000..0038902
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-vb2.c
@@ -0,0 +1,85 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS video buffer2 interface
+ *
+ * main platform driver interface
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <media/videobuf2-core.h>
+#include <linux/platform_device.h>
+#include "fimc-is-core.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *fimc_is_cma_init(struct fimc_is_dev *isp)
+{
+	return vb2_cma_phys_init(&isp->pdev->dev,
+				FIMC_IS_MEM_ISP_BUF, 0, false);
+}
+
+int fimc_is_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void fimc_is_cma_suspend(void *alloc_ctx) {}
+void fimc_is_cma_set_cacheable(void *alloc_ctx, bool cacheable) {}
+
+int fimc_is_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct fimc_is_vb2 fimc_is_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= fimc_is_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= fimc_is_cma_resume,
+	.suspend	= fimc_is_cma_suspend,
+	.cache_flush	= fimc_is_cma_cache_flush,
+	.set_cacheable	= fimc_is_cma_set_cacheable,
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *fimc_is_ion_init(struct fimc_is_dev *isp)
+{
+	struct vb2_ion vb2_ion;
+	struct vb2_drv vb2_drv = {0, };
+	char ion_name[16] = {0,};
+
+	vb2_ion.dev = &isp->pdev->dev;
+	sprintf(ion_name, "exynos5-fimc-is");
+	vb2_ion.name = ion_name;
+	vb2_ion.contig = true;
+	vb2_ion.cacheable = true;
+	vb2_ion.align = SZ_4K;
+
+	vb2_drv.use_mmu = true;
+
+	return vb2_ion_init(&vb2_ion, &vb2_drv);
+}
+
+const struct fimc_is_vb2 fimc_is_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= fimc_is_ion_init,
+	.cleanup	= vb2_ion_cleanup,
+	.plane_addr	= vb2_ion_plane_dvaddr,
+	.resume		= vb2_ion_resume,
+	.suspend	= vb2_ion_suspend,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cacheable,
+	.set_sharable	= vb2_ion_set_sharable,
+	.get_kvaddr	= vb2_ion_plane_kvaddr,
+};
+#endif
+
diff --git a/drivers/media/video/exynos/fimc-is/fimc-is-video.c b/drivers/media/video/exynos/fimc-is/fimc-is-video.c
new file mode 100644
index 0000000..85080af
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-is/fimc-is-video.c
@@ -0,0 +1,596 @@
+/*
+ * Samsung Exynos4 SoC series FIMC-IS slave interface driver
+ *
+ * v4l2 subdev driver interface
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * Contact: Younghwan Joo, <yhwan.joo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/workqueue.h>
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+
+#include "fimc-is-core.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-param.h"
+#include "fimc-is-cmd.h"
+
+#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS_BAYER)
+#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
+
+static struct fimc_is_fmt fimc_is_formats[] = {
+	{
+		.name	= "Bayer10",
+		.fourcc	= V4L2_PIX_FMT_SGRBG10,
+		.flags = 1,
+	}, {
+		.name	= "Bayer12",
+		.fourcc	= V4L2_PIX_FMT_SGRBG12,
+		.flags = 1,
+	}, {
+		.name	= "Bayer14",
+		.fourcc	= V4L2_PIX_FMT_SGRBG14,
+		.flags = 1,
+	},
+};
+
+/************************************************************************/
+/* video file opertation						*/
+/************************************************************************/
+static int fimc_is_isp_open(struct file *file)
+{
+	struct fimc_is_dev *is_dev;
+
+	dbg("FIMC_IS_IS_OPEN\n");
+	is_dev = video_drvdata(file);
+	file->private_data = &is_dev->video[FIMC_IS_VIDEO_NUM_BAYER];
+	dbg("pid: %d, state: 0x%lx", task_pid_nr(current), is_dev->power);
+
+	is_dev->vb_state = FIMC_IS_STATE_IDLE;
+	/* Check FIMC-IS ready */
+	if (!test_bit(IS_ST_INIT_DONE, &is_dev->state))
+		return -EINVAL;
+
+	set_bit(FIMC_IS_STATE_READY, &is_dev->vb_state);
+	return 0;
+}
+
+static int fimc_is_isp_close(struct file *file)
+{
+	struct fimc_is_dev *is_dev;
+
+	dbg("(FIMC-IS cap_fops)\n");
+	is_dev = video_drvdata(file);
+
+	dbg("pid: %d, state: 0x%lx", task_pid_nr(current), is_dev->power);
+
+	/* If FIMC-ISP dma output is still running,
+				must be stopped before closing */
+	vb2_queue_release(&is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq);
+	return 0;
+}
+
+static unsigned int fimc_is_isp_poll(struct file *file,
+					struct poll_table_struct *wait)
+{
+	struct fimc_is_dev *is_dev;
+
+	is_dev = video_drvdata(file);
+	return vb2_poll(&is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq,
+								file, wait);
+}
+
+static int fimc_is_isp_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct fimc_is_dev *is_dev;
+
+	dbg("(FIMC-IS cap_fops)\n");
+	is_dev = video_drvdata(file);
+	return vb2_mmap(&is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, vma);
+}
+
+/* video device file operations */
+const struct v4l2_file_operations fimc_is_isp_video_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_is_isp_open,
+	.release	= fimc_is_isp_close,
+	.poll		= fimc_is_isp_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= fimc_is_isp_mmap,
+};
+
+/************************************************************************/
+/* video ioctl operation						*/
+/************************************************************************/
+static int fimc_is_isp_video_querycap(struct file *file, void *priv,
+					struct v4l2_capability *cap)
+{
+	struct fimc_is_dev *is_dev = video_drvdata(file);
+
+	strncpy(cap->driver, is_dev->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, is_dev->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE
+						| V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+	return 0;
+}
+
+static int fimc_is_isp_video_enum_input(struct file *file, void *priv,
+				  struct v4l2_input *input)
+{
+	int ret = 0;
+
+	if (input->index >= FIMC_IS_SENSOR_NUM)
+		return -EINVAL;
+
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+	strncpy(input->name, "ISP Camera", 32);
+	return ret;
+}
+
+static int fimc_is_isp_video_s_input(struct file *file, void *priv,
+				  unsigned int i)
+{
+	int ret = 0;
+
+	dbg("fimc_is_isp_video_s_input\n");
+	return ret;
+}
+
+int fimc_is_isp_video_enum_fmt_mplane(struct file *file, void *priv,
+				struct v4l2_fmtdesc *f)
+{
+	struct fimc_is_fmt *fmt;
+
+	if (f->index >= ARRAY_SIZE(fimc_is_formats))
+		return -EINVAL;
+
+	fmt = &fimc_is_formats[f->index];
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+int fimc_is_isp_video_g_fmt_mplane(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct fimc_is_dev *is_dev;
+	dbg("fimc_is_isp_video_g_fmt_mplane\n");
+
+	is_dev = video_drvdata(file);
+
+	switch (is_dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		f->fmt.pix.width = is_dev->sensor.width_prev;
+		f->fmt.pix.height = is_dev->sensor.height_prev;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		f->fmt.pix.width = is_dev->sensor.width_prev_cam;
+		f->fmt.pix.height = is_dev->sensor.height_prev_cam;
+		break;
+	case ISS_CAPTURE_STILL:
+		f->fmt.pix.width = is_dev->sensor.width_cap;
+		f->fmt.pix.height = is_dev->sensor.height_cap;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		f->fmt.pix.width = is_dev->sensor.width_cam;
+		f->fmt.pix.height = is_dev->sensor.height_cam;
+		break;
+	default:
+		f->fmt.pix.width = 0;
+		f->fmt.pix.height = 0;
+		break;
+	}
+
+	f->fmt.pix.field	= V4L2_FIELD_NONE;
+	/* FIXME */
+	f->fmt.pix.pixelformat	= V4L2_PIX_FMT_SGRBG12;
+	return 0;
+}
+
+static int fimc_is_isp_video_s_fmt_mplane(struct file *file, void *priv,
+				 struct v4l2_format *f)
+{
+	struct fimc_is_dev *is_dev;
+	struct v4l2_pix_format_mplane *pix;
+	u32 width = 0, height = 0;
+	int i, ret = 0;
+	int size_mismatch_flg = 0;
+
+	dbg("fimc_is_video_s_fmt_mplane\n");
+	is_dev = video_drvdata(file);
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE
+		&& f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	pix = &f->fmt.pix_mp;
+	switch (f->fmt.pix.pixelformat) {
+	case V4L2_PIX_FMT_SGRBG10:
+		width = pix->width - is_dev->sensor.offset_x;
+		height = pix->height - is_dev->sensor.offset_y;
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(is_dev,
+						DMA_OUTPUT_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(is_dev, width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(is_dev, height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(is_dev,
+						DMA_OUTPUT_FORMAT_BAYER);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(is_dev,
+						DMA_OUTPUT_BIT_WIDTH_10BIT);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(is_dev, DMA_OUTPUT_PLANE_1);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(is_dev,
+						DMA_OUTPUT_ORDER_GB_BG);
+		break;
+	case V4L2_PIX_FMT_SGRBG12:
+		width = pix->width;
+		height = pix->height;
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(is_dev,
+						DMA_OUTPUT_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(is_dev, width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(is_dev, height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(is_dev,
+						DMA_OUTPUT_FORMAT_BAYER);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(is_dev,
+						DMA_OUTPUT_BIT_WIDTH_12BIT);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(is_dev, DMA_OUTPUT_PLANE_1);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(is_dev,
+						DMA_OUTPUT_ORDER_GB_BG);
+		break;
+	case V4L2_PIX_FMT_SGRBG14:
+		width = pix->width - is_dev->sensor.offset_x;
+		height = pix->height - is_dev->sensor.offset_y;
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(is_dev,
+						DMA_OUTPUT_COMMAND_DISABLE);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_WIDTH(is_dev, width);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_HEIGHT(is_dev, height);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_FORMAT(is_dev,
+						DMA_OUTPUT_FORMAT_BAYER);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BITWIDTH(is_dev,
+						DMA_OUTPUT_BIT_WIDTH_14BIT);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_PLANE(is_dev, DMA_OUTPUT_PLANE_1);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_ORDER(is_dev,
+						DMA_OUTPUT_ORDER_GB_BG);
+		break;
+	}
+
+	switch (is_dev->scenario_id) {
+	case ISS_PREVIEW_STILL:
+		if (width != is_dev->sensor.width_prev ||
+			height != is_dev->sensor.height_prev)
+			size_mismatch_flg = 1;
+		break;
+	case ISS_PREVIEW_VIDEO:
+		if (width != is_dev->sensor.width_prev_cam ||
+			height != is_dev->sensor.height_prev_cam)
+			size_mismatch_flg = 1;
+		break;
+	case ISS_CAPTURE_STILL:
+		if (width != is_dev->sensor.width_cap ||
+			height != is_dev->sensor.height_cap)
+			size_mismatch_flg = 1;
+		break;
+	case ISS_CAPTURE_VIDEO:
+		if (width != is_dev->sensor.width_cam ||
+			height != is_dev->sensor.height_cam)
+			size_mismatch_flg = 1;
+		break;
+	default:
+		break;
+	}
+	if (size_mismatch_flg)
+		err(" Size mismatching - ISP otfoutput and ISP bayer output\n");
+
+	is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane = pix->num_planes;
+	for (i = 0; i < pix->num_planes; i++) {
+		is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].plane_size[i] =
+						pix->plane_fmt[i].sizeimage;
+	}
+
+	dbg("S_FMT : %d,%d - %d\n", width, height, pix->num_planes);
+	return ret;
+}
+
+static int fimc_is_isp_video_g_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	int ret = 0;
+
+	dbg("fimc_is_isp_video_g_ctrl\n");
+	return ret;
+}
+
+static int fimc_is_isp_video_s_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	int ret = 0;
+
+	dbg("fimc_is_isp_video_s_ctrl\n");
+	return ret;
+}
+
+static int fimc_is_isp_video_reqbufs(struct file *file, void *priv,
+			    struct v4l2_requestbuffers *buf)
+{
+	struct fimc_is_dev *is_dev = video_drvdata(file);
+	struct fimc_is_video_dev *video = file->private_data;
+	int ret;
+
+	ret = vb2_reqbufs(&video->vbq, buf);
+
+	if (!ret)
+		is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf = buf->count;
+
+	if (buf->count == 0)
+		is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt = 0;
+	printk(KERN_INFO "%s(num_buf : %d)\n", __func__,
+		is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf);
+	return ret;
+}
+
+static int fimc_is_isp_video_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_is_video_dev *video = file->private_data;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+	return vb2_querybuf(&video->vbq, buf);
+}
+
+static int fimc_is_isp_video_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct fimc_is_video_dev *video = file->private_data;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+	return vb2_qbuf(&video->vbq, buf);
+}
+
+static int fimc_is_isp_video_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_is_video_dev *video = file->private_data;
+
+	printk(KERN_DEBUG "%s\n", __func__);
+	return vb2_dqbuf(&video->vbq, buf, file->f_flags & O_NONBLOCK);
+}
+
+static int fimc_is_isp_video_streamon(struct file *file, void *priv,
+			     enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *is_dev = video_drvdata(file);
+
+	printk(KERN_DEBUG "%s\n", __func__);
+	return vb2_streamon(&is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, type);
+}
+
+static int fimc_is_isp_video_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct fimc_is_dev *is_dev = video_drvdata(file);
+
+	printk(KERN_DEBUG "%s\n", __func__);
+	return vb2_streamoff(&is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].vbq, type);
+}
+
+const struct v4l2_ioctl_ops fimc_is_isp_video_ioctl_ops = {
+	.vidioc_querycap		= fimc_is_isp_video_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= fimc_is_isp_video_enum_fmt_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= fimc_is_isp_video_s_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= fimc_is_isp_video_g_fmt_mplane,
+
+	.vidioc_reqbufs			= fimc_is_isp_video_reqbufs,
+	.vidioc_querybuf		= fimc_is_isp_video_querybuf,
+
+	.vidioc_qbuf			= fimc_is_isp_video_qbuf,
+	.vidioc_dqbuf			= fimc_is_isp_video_dqbuf,
+
+	.vidioc_streamon		= fimc_is_isp_video_streamon,
+	.vidioc_streamoff		= fimc_is_isp_video_streamoff,
+
+	.vidioc_g_ctrl			= fimc_is_isp_video_g_ctrl,
+	.vidioc_s_ctrl			= fimc_is_isp_video_s_ctrl,
+
+	.vidioc_enum_input		= fimc_is_isp_video_enum_input,
+	.vidioc_s_input			= fimc_is_isp_video_s_input,
+};
+
+static int fimc_is_isp_queue_setup(struct vb2_queue *vq,
+			unsigned int *num_buffers, unsigned int *num_planes,
+			unsigned long sizes[], void *allocators[])
+{
+	struct fimc_is_video_dev *video = vq->drv_priv;
+	struct fimc_is_dev	*is_dev = video->dev;
+	int i;
+
+	*num_planes = is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane;
+
+	for (i = 0; i < *num_planes; i++) {
+		sizes[i] = is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].plane_size[i];
+		allocators[i] =  is_dev->alloc_ctx;
+	}
+
+	dbg("%s(num_planes : %d)(size : %d)\n", __func__, (int)*num_planes,
+								(int)sizes[0]);
+
+	return 0;
+}
+
+static int fimc_is_isp_buf_prepare(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev *is_dev = video->dev;
+	unsigned long size;
+	int i;
+
+	for (i = 0; i < is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane; i++) {
+		size = is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].plane_size[i];
+
+		if (vb2_plane_size(vb, i) < size) {
+			err("User buffer too small(%ld < %ld)\n",
+					 vb2_plane_size(vb, i), size);
+			return -EINVAL;
+		}
+
+		vb2_set_plane_payload(vb, i, size);
+	}
+
+	return 0;
+}
+
+static void fimc_is_isp_lock(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = vb2_get_drv_priv(q);
+	struct fimc_is_dev	*is_dev = video->dev;
+	mutex_lock(&is_dev->lock);
+}
+
+static void fimc_is_isp_unlock(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = vb2_get_drv_priv(q);
+	struct fimc_is_dev	*is_dev = video->dev;
+	mutex_unlock(&is_dev->lock);
+}
+
+static int fimc_is_isp_start_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = vb2_get_drv_priv(q);
+	struct fimc_is_dev	*is_dev = video->dev;
+	int i, j;
+	int buf_num, buf_plane, buf_index;
+
+	if (test_bit(FIMC_IS_STATE_ISP_BUFFER_PREPARED, &is_dev->vb_state) &&
+		!test_bit(FIMC_IS_STATE_ISP_STREAM_ON, &is_dev->vb_state)) {
+
+		dbg("Start streaming!!\n");
+		/* buffer addr setting */
+		buf_num = is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf;
+		buf_plane = is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane;
+		for (i = 0; i < buf_num; i++)
+			for (j = 0; j < buf_plane; j++) {
+				buf_index = i*buf_plane + j;
+				printk(KERN_INFO "(%d)set buf(%d:%d)= 0x%08x\n"
+					, buf_index, i, j,
+			is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].buf[i][j]);
+				is_dev->is_p_region->shared[32+buf_index]
+			= is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].buf[i][j];
+			}
+
+		printk(KERN_INFO "buf_num:%d buf_plane:%d shared[32]: 0x%08x\n",
+			is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf,
+			is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane,
+			virt_to_phys(is_dev->is_p_region->shared) +
+							32*sizeof(u32));
+
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(is_dev,
+					DMA_OUTPUT_COMMAND_ENABLE);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_NUMBER(is_dev,
+				is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf);
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_BUFFER_ADDRESS(is_dev,
+				(u32)virt_to_phys(is_dev->is_p_region->shared)
+				+ 32 * sizeof(u32));
+		IS_ISP_SET_PARAM_DMA_OUTPUT2_NODIFY_DMA_DONE(is_dev,
+				DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE);
+		IS_SET_PARAM_BIT(is_dev, PARAM_ISP_DMA2_OUTPUT);
+		IS_INC_PARAM_NUM(is_dev);
+
+		fimc_is_mem_cache_clean((void *)is_dev->is_p_region,
+			IS_PARAM_SIZE);
+		fimc_is_hw_set_param(is_dev);
+		set_bit(FIMC_IS_STATE_ISP_STREAM_ON, &is_dev->vb_state);
+	}
+	return 0;
+}
+
+static void fimc_is_isp_buf_queue(struct vb2_buffer *vb)
+{
+	struct fimc_is_video_dev *video = vb->vb2_queue->drv_priv;
+	struct fimc_is_dev *is_dev = video->dev;
+#if defined(CONFIG_VIDEOBUF2_ION)
+	dma_addr_t kvaddr;
+#endif
+	unsigned int i;
+
+	if (is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_plane != vb->num_planes)
+		return;
+
+	if (!test_bit(FIMC_IS_STATE_ISP_BUFFER_PREPARED, &is_dev->vb_state)) {
+		for (i = 0; i < vb->num_planes; i++) {
+			is_dev->video[FIMC_IS_VIDEO_NUM_BAYER]
+				.buf[vb->v4l2_buf.index][i] =
+						is_dev->vb2->plane_addr(vb, i);
+			dbg("index(%d)(%d) deviceVaddr(0x%08x)\n",
+				vb->v4l2_buf.index, i,
+				is_dev->video[FIMC_IS_VIDEO_NUM_BAYER]
+						.buf[vb->v4l2_buf.index][i]);
+		}
+
+		is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt++;
+
+		if (is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].num_buf ==
+			is_dev->video[FIMC_IS_VIDEO_NUM_BAYER].buf_ref_cnt)
+			set_bit(FIMC_IS_STATE_ISP_BUFFER_PREPARED,
+							&is_dev->vb_state);
+	}
+
+	if (!test_bit(FIMC_IS_STATE_ISP_STREAM_ON, &is_dev->vb_state))
+		fimc_is_isp_start_streaming(vb->vb2_queue);
+}
+
+static int fimc_is_isp_stop_streaming(struct vb2_queue *q)
+{
+	struct fimc_is_video_dev *video = vb2_get_drv_priv(q);
+	struct fimc_is_dev	*is_dev = video->dev;
+
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_CMD(is_dev, DMA_OUTPUT_COMMAND_DISABLE);
+	IS_ISP_SET_PARAM_DMA_OUTPUT2_NODIFY_DMA_DONE(is_dev,
+					DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE);
+	IS_SET_PARAM_BIT(is_dev, PARAM_ISP_DMA2_OUTPUT);
+	IS_INC_PARAM_NUM(is_dev);
+
+	fimc_is_mem_cache_clean((void *)is_dev->is_p_region,
+			IS_PARAM_SIZE);
+	fimc_is_hw_set_param(is_dev);
+
+	clear_bit(FIMC_IS_STATE_ISP_STREAM_ON, &is_dev->vb_state);
+	clear_bit(FIMC_IS_STATE_ISP_BUFFER_PREPARED, &is_dev->vb_state);
+	return 0;
+}
+
+const struct vb2_ops fimc_is_isp_qops = {
+	.queue_setup	 = fimc_is_isp_queue_setup,
+	.buf_prepare	 = fimc_is_isp_buf_prepare,
+	.buf_queue	 = fimc_is_isp_buf_queue,
+	.wait_prepare	 = fimc_is_isp_unlock,
+	.wait_finish	 = fimc_is_isp_lock,
+	.start_streaming = fimc_is_isp_start_streaming,
+	.stop_streaming	 = fimc_is_isp_stop_streaming,
+};
+#endif
diff --git a/drivers/media/video/exynos/fimc-lite/Kconfig b/drivers/media/video/exynos/fimc-lite/Kconfig
new file mode 100644
index 0000000..703e035
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/Kconfig
@@ -0,0 +1,18 @@
+config VIDEO_EXYNOS_FIMC_LITE
+	bool "Exynos Camera Interface(FIMC-Lite) driver"
+	depends on VIDEO_EXYNOS && (ARCH_EXYNOS4 || ARCH_EXYNOS5)
+	select MEDIA_EXYNOS
+	default n
+	help
+	  This is a v4l2 driver for exynos camera interface device.
+
+if VIDEO_EXYNOS_FIMC_LITE && VIDEOBUF2_CMA_PHYS
+comment "Reserved memory configurations"
+config VIDEO_SAMSUNG_MEMSIZE_FLITE0
+	int "Memory size in kbytes for FLITE0"
+	default "10240"
+
+config VIDEO_SAMSUNG_MEMSIZE_FLITE1
+	int "Memory size in kbytes for FLITE1"
+	default "10240"
+endif
diff --git a/drivers/media/video/exynos/fimc-lite/Makefile b/drivers/media/video/exynos/fimc-lite/Makefile
new file mode 100644
index 0000000..256d8d9
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/Makefile
@@ -0,0 +1,6 @@
+ifeq ($(CONFIG_ARCH_EXYNOS5),y)
+fimc-lite-objs := fimc-lite-core.o fimc-lite-reg.o fimc-lite-vb2.o
+else
+fimc-lite-objs := fimc-lite-core.o fimc-lite-reg.o
+endif
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_LITE)	+= fimc-lite.o
diff --git a/drivers/media/video/exynos/fimc-lite/fimc-lite-core.c b/drivers/media/video/exynos/fimc-lite/fimc-lite-core.c
new file mode 100644
index 0000000..eddbf1d
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/fimc-lite-core.c
@@ -0,0 +1,2203 @@
+/*
+ * Register interface file for Samsung Camera Interface (FIMC-Lite) driver
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+#include <mach/videonode.h>
+#include <media/exynos_mc.h>
+#endif
+#include "fimc-lite-core.h"
+
+#define MODULE_NAME			"exynos-fimc-lite"
+#define DEFAULT_FLITE_SINK_WIDTH	800
+#define DEFAULT_FLITE_SINK_HEIGHT	480
+#define CAMIF_TOP_CLK			"camif_top"
+
+static struct flite_fmt flite_formats[] = {
+	{
+		.name		= "YUV422 8-bit 1 plane(UYVY)",
+		.pixelformat	= V4L2_PIX_FMT_UYVY,
+		.depth		= { 16 },
+		.code		= V4L2_MBUS_FMT_UYVY8_2X8,
+		.fmt_reg	= FLITE_REG_CIGCTRL_YUV422_1P,
+		.is_yuv		= 1,
+	}, {
+		.name		= "YUV422 8-bit 1 plane(VYUY)",
+		.pixelformat	= V4L2_PIX_FMT_VYUY,
+		.depth		= { 16 },
+		.code		= V4L2_MBUS_FMT_VYUY8_2X8,
+		.fmt_reg	= FLITE_REG_CIGCTRL_YUV422_1P,
+		.is_yuv		= 1,
+	}, {
+		.name		= "YUV422 8-bit 1 plane(YUYV)",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+		.depth		= { 16 },
+		.code		= V4L2_MBUS_FMT_YUYV8_2X8,
+		.fmt_reg	= FLITE_REG_CIGCTRL_YUV422_1P,
+		.is_yuv		= 1,
+	}, {
+		.name		= "YUV422 8-bit 1 plane(YVYU)",
+		.pixelformat	= V4L2_PIX_FMT_YVYU,
+		.depth		= { 16 },
+		.code		= V4L2_MBUS_FMT_YVYU8_2X8,
+		.fmt_reg	= FLITE_REG_CIGCTRL_YUV422_1P,
+		.is_yuv		= 1,
+	}, {
+		.name		= "RAW8(GRBG)",
+		.pixelformat	= V4L2_PIX_FMT_SGRBG8,
+		.depth		= { 8 },
+		.code		= V4L2_MBUS_FMT_SGRBG8_1X8,
+		.fmt_reg	= FLITE_REG_CIGCTRL_RAW8,
+		.is_yuv		= 0,
+	}, {
+		.name		= "RAW10(GRBG)",
+		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
+		.depth		= { 10 },
+		.code		= V4L2_MBUS_FMT_SGRBG10_1X10,
+		.fmt_reg	= FLITE_REG_CIGCTRL_RAW10,
+		.is_yuv		= 0,
+	}, {
+		.name		= "RAW12(GRBG)",
+		.pixelformat	= V4L2_PIX_FMT_SGRBG12,
+		.depth		= { 12 },
+		.code		= V4L2_MBUS_FMT_SGRBG12_1X12,
+		.fmt_reg	= FLITE_REG_CIGCTRL_RAW12,
+		.is_yuv		= 0,
+	}, {
+		.name		= "User Defined(JPEG)",
+		.code		= V4L2_MBUS_FMT_JPEG_1X8,
+		.depth		= { 8 },
+		.fmt_reg	= FLITE_REG_CIGCTRL_USER(1),
+		.is_yuv		= 0,
+	},
+};
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+static struct flite_variant variant = {
+	.max_w			= 8192,
+	.max_h			= 8192,
+	.align_win_offs_w	= 2,
+	.align_out_w		= 8,
+	.align_out_offs_w	= 8,
+};
+
+static struct flite_fmt *get_format(int index)
+{
+	return &flite_formats[index];
+}
+
+static struct flite_fmt *find_format(u32 *pixelformat, u32 *mbus_code, int index)
+{
+	struct flite_fmt *fmt, *def_fmt = NULL;
+	unsigned int i;
+
+	if (index >= ARRAY_SIZE(flite_formats))
+		return NULL;
+
+	for (i = 0; i < ARRAY_SIZE(flite_formats); ++i) {
+		fmt = get_format(i);
+		if (pixelformat && fmt->pixelformat == *pixelformat)
+			return fmt;
+		if (mbus_code && fmt->code == *mbus_code)
+			return fmt;
+		if (index == i)
+			def_fmt = fmt;
+	}
+	return def_fmt;
+
+}
+#endif
+
+inline struct flite_fmt const *find_flite_format(struct v4l2_mbus_framefmt *mf)
+{
+	int num_fmt = ARRAY_SIZE(flite_formats);
+
+	while (num_fmt--)
+		if (mf->code == flite_formats[num_fmt].code)
+			break;
+	if (num_fmt < 0)
+		return NULL;
+
+	return &flite_formats[num_fmt];
+}
+
+static int flite_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct flite_fmt const *f_fmt = find_flite_format(mf);
+	struct flite_frame *f_frame = &flite->s_frame;
+
+	flite_dbg("w: %d, h: %d", mf->width, mf->height);
+
+	if (unlikely(!f_fmt)) {
+		flite_err("f_fmt is null");
+		return -EINVAL;
+	}
+
+	flite->mbus_fmt = *mf;
+
+	/*
+	 * These are the datas from fimc
+	 * If you want to crop the image, you can use s_crop
+	 */
+	f_frame->o_width = mf->width;
+	f_frame->o_height = mf->height;
+	f_frame->width = mf->width;
+	f_frame->height = mf->height;
+	f_frame->offs_h = 0;
+	f_frame->offs_v = 0;
+
+	return 0;
+}
+
+static int flite_g_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	mf = &flite->mbus_fmt;
+
+	return 0;
+}
+
+static int flite_subdev_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *cc)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct flite_frame *f;
+
+	f = &flite->s_frame;
+
+	cc->bounds.left		= 0;
+	cc->bounds.top		= 0;
+	cc->bounds.width	= f->o_width;
+	cc->bounds.height	= f->o_height;
+	cc->defrect		= cc->bounds;
+
+	return 0;
+}
+
+static int flite_subdev_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *crop)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct flite_frame *f;
+
+	f = &flite->s_frame;
+
+	crop->c.left	= f->offs_h;
+	crop->c.top	= f->offs_v;
+	crop->c.width	= f->width;
+	crop->c.height	= f->height;
+
+	return 0;
+}
+
+static int flite_subdev_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *crop)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct flite_frame *f;
+
+	f = &flite->s_frame;
+
+	if (crop->c.left + crop->c.width > f->o_width) {
+		flite_err("Unsupported crop width");
+		return -EINVAL;
+	}
+	if (crop->c.top + crop->c.height > f->o_height) {
+		flite_err("Unsupported crop height");
+		return -EINVAL;
+	}
+
+	f->width = crop->c.width;
+	f->height = crop->c.height;
+	f->offs_h = crop->c.left;
+	f->offs_v = crop->c.top;
+
+	flite_dbg("width : %d, height : %d, offs_h : %d, off_v : %dn",
+			f->width, f->height, f->offs_h, f->offs_v);
+
+	return 0;
+}
+
+static int flite_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	u32 index = flite->pdata->active_cam_index;
+	struct s3c_platform_camera *cam = NULL;
+	u32 int_src = 0;
+	unsigned long flags;
+	int ret = 0;
+
+	if (!(flite->output & FLITE_OUTPUT_MEM)) {
+		if (enable)
+			flite_hw_reset(flite);
+		cam = flite->pdata->cam[index];
+	}
+
+	spin_lock_irqsave(&flite->slock, flags);
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	if (test_bit(FLITE_ST_SUSPEND, &flite->state))
+		goto s_stream_unlock;
+#endif
+
+	if (enable) {
+		flite_hw_set_cam_channel(flite);
+		flite_hw_set_cam_source_size(flite);
+
+		if (!(flite->output & FLITE_OUTPUT_MEM)) {
+			flite_info("@local out start@");
+			flite_hw_set_camera_type(flite, cam);
+			flite_hw_set_config_irq(flite, cam);
+			if (IS_ERR_OR_NULL(cam)) {
+				flite_err("cam is null");
+				goto s_stream_unlock;
+			}
+			if (cam->use_isp)
+				flite_hw_set_output_dma(flite, false);
+
+			if (soc_is_exynos5250_rev1)
+				flite_hw_set_output_gscaler(flite, true);
+
+			int_src = FLITE_REG_CIGCTRL_IRQ_OVFEN0_ENABLE |
+				FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE |
+				FLITE_REG_CIGCTRL_IRQ_ENDEN0_DISABLE |
+				FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE;
+		} else {
+			flite_info("@mem out start@");
+			flite_hw_set_sensor_type(flite);
+			flite_hw_set_inverse_polarity(flite);
+			set_bit(FLITE_ST_PEND, &flite->state);
+			flite_hw_set_output_dma(flite, true);
+			int_src = FLITE_REG_CIGCTRL_IRQ_OVFEN0_ENABLE |
+				FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE |
+				FLITE_REG_CIGCTRL_IRQ_ENDEN0_ENABLE |
+				FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE;
+			flite_hw_set_out_order(flite);
+			flite_hw_set_output_size(flite);
+			flite_hw_set_dma_offset(flite);
+		}
+		ret = flite_hw_set_source_format(flite);
+		if (unlikely(ret < 0))
+			goto s_stream_unlock;
+
+		flite_hw_set_interrupt_source(flite, int_src);
+		flite_hw_set_window_offset(flite);
+		flite_hw_set_capture_start(flite);
+
+		set_bit(FLITE_ST_STREAM, &flite->state);
+	} else {
+		if (test_bit(FLITE_ST_STREAM, &flite->state)) {
+			flite_hw_set_capture_stop(flite);
+			spin_unlock_irqrestore(&flite->slock, flags);
+#if defined(CONFIG_ARCH_EXYNOS4)
+			clear_bit(FLITE_ST_STREAM, &flite->state);
+#else
+			ret = wait_event_timeout(flite->irq_queue,
+			!test_bit(FLITE_ST_STREAM, &flite->state), HZ/20); /* 50 ms */
+			if (unlikely(!ret)) {
+				v4l2_err(sd, "wait timeout\n");
+				ret = -EBUSY;
+			}
+#endif
+		return ret;
+		} else {
+			goto s_stream_unlock;
+		}
+	}
+s_stream_unlock:
+	spin_unlock_irqrestore(&flite->slock, flags);
+	return ret;
+}
+
+static irqreturn_t flite_irq_handler(int irq, void *priv)
+{
+	struct flite_dev *flite = priv;
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	struct flite_buffer *buf;
+#endif
+	u32 int_src = 0;
+	printk(KERN_INFO "flite interrupt\n");
+
+	flite_hw_get_int_src(flite, &int_src);
+	flite_hw_clear_irq(flite);
+
+	spin_lock(&flite->slock);
+
+	switch (int_src & FLITE_REG_CISTATUS_IRQ_MASK) {
+	case FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW:
+		clear_bit(FLITE_ST_RUN, &flite->state);
+		flite_err("overflow generated");
+		break;
+	case FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND:
+		flite_hw_set_last_capture_end_clear(flite);
+		flite_info("last capture end");
+		clear_bit(FLITE_ST_STREAM, &flite->state);
+		wake_up(&flite->irq_queue);
+		break;
+	case FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART:
+		flite_dbg("frame start");
+		break;
+	case FLITE_REG_CISTATUS_IRQ_SRC_FRMEND:
+		set_bit(FLITE_ST_RUN, &flite->state);
+		flite_dbg("frame end");
+		break;
+	}
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	if (flite->output & FLITE_OUTPUT_MEM) {
+		if (!list_empty(&flite->active_buf_q)) {
+			buf = active_queue_pop(flite);
+			if (!test_bit(FLITE_ST_RUN, &flite->state)) {
+				flite_info("error interrupt");
+				vb2_buffer_done(&buf->vb,
+						VB2_BUF_STATE_ERROR);
+				goto unlock;
+			}
+			vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE);
+			flite_dbg("done_index : %d", buf->vb.v4l2_buf.index);
+		}
+		if (!list_empty(&flite->pending_buf_q)) {
+			buf = pending_queue_pop(flite);
+			flite_hw_set_output_addr(flite, &buf->paddr,
+					buf->vb.v4l2_buf.index);
+			active_queue_add(flite, buf);
+		}
+		if (flite->active_buf_cnt == 0)
+			clear_bit(FLITE_ST_RUN, &flite->state);
+	}
+unlock:
+#endif
+	spin_unlock(&flite->slock);
+
+	return IRQ_HANDLED;
+}
+
+static int flite_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	int ret = 0;
+
+	if (on) {
+		if (!test_bit(FLITE_ST_POWER, &flite->state)) {
+			pm_runtime_get_sync(&flite->pdev->dev);
+			set_bit(FLITE_ST_POWER, &flite->state);
+		}
+	} else {
+		if (test_bit(FLITE_ST_POWER, &flite->state)) {
+			pm_runtime_put_sync(&flite->pdev->dev);
+			clear_bit(FLITE_ST_POWER, &flite->state);
+		}
+	}
+
+	return ret;
+}
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+static int flite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
+				       struct v4l2_subdev_fh *fh,
+				       struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->index >= ARRAY_SIZE(flite_formats))
+		return -EINVAL;
+
+	code->code = flite_formats[code->index].code;
+
+	return 0;
+}
+
+static struct v4l2_mbus_framefmt *__flite_get_format(
+		struct flite_dev *flite, struct v4l2_subdev_fh *fh,
+		u32 pad, enum v4l2_subdev_format_whence which)
+{
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
+	else
+		return &flite->mbus_fmt;
+}
+
+static void flite_try_format(struct flite_dev *flite, struct v4l2_subdev_fh *fh,
+			     struct v4l2_mbus_framefmt *fmt,
+			     enum v4l2_subdev_format_whence which)
+{
+	struct flite_fmt const *ffmt;
+	struct flite_frame *f = &flite->s_frame;
+	ffmt = find_flite_format(fmt);
+	if (ffmt == NULL)
+		ffmt = &flite_formats[1];
+
+	fmt->code = ffmt->code;
+	fmt->width = clamp_t(u32, fmt->width, 1, variant.max_w);
+	fmt->height = clamp_t(u32, fmt->height, 1, variant.max_h);
+
+	f->offs_h = f->offs_v = 0;
+	f->width = f->o_width = fmt->width;
+	f->height = f->o_height = fmt->height;
+
+	fmt->colorspace = V4L2_COLORSPACE_JPEG;
+	fmt->field = V4L2_FIELD_NONE;
+}
+
+static int flite_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+				struct v4l2_subdev_format *fmt)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	mf = __flite_get_format(flite, fh, fmt->pad, fmt->which);
+	if (mf == NULL) {
+		flite_err("__flite_get_format is null");
+		return -EINVAL;
+	}
+
+	fmt->format = *mf;
+
+	if (fmt->pad != FLITE_PAD_SINK) {
+		struct flite_frame *f = &flite->s_frame;
+		fmt->format.width = f->width;
+		fmt->format.height = f->height;
+	}
+
+	return 0;
+}
+
+static int flite_subdev_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+				struct v4l2_subdev_format *fmt)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	if (fmt->pad != FLITE_PAD_SINK)
+		return -EPERM;
+
+	mf = __flite_get_format(flite, fh, fmt->pad, fmt->which);
+	if (mf == NULL) {
+		flite_err("__flite_get_format is null");
+		return -EINVAL;
+	}
+
+	flite_try_format(flite, fh, &fmt->format, fmt->which);
+	*mf = fmt->format;
+
+	return 0;
+}
+
+static void flite_try_crop(struct flite_dev *flite, struct v4l2_subdev_crop *crop)
+{
+	struct flite_frame *f_frame = flite_get_frame(flite, crop->pad);
+
+	u32 max_left = f_frame->o_width - crop->rect.width;
+	u32 max_top = f_frame->o_height - crop->rect.height;
+	u32 crop_max_w = f_frame->o_width - crop->rect.left;
+	u32 crop_max_h = f_frame->o_height - crop->rect.top;
+
+	crop->rect.left = clamp_t(u32, crop->rect.left, 0, max_left);
+	crop->rect.top = clamp_t(u32, crop->rect.top, 0, max_top);
+	crop->rect.width = clamp_t(u32, crop->rect.width, 2, crop_max_w);
+	crop->rect.height = clamp_t(u32, crop->rect.height, 1, crop_max_h);
+}
+
+static int __flite_get_crop(struct flite_dev *flite, struct v4l2_subdev_fh *fh,
+			    unsigned int pad, enum v4l2_subdev_format_whence which,
+			    struct v4l2_rect *crop)
+{
+	struct flite_frame *frame = &flite->s_frame;
+
+	if (which == V4L2_SUBDEV_FORMAT_TRY) {
+		crop = v4l2_subdev_get_try_crop(fh, pad);
+	} else {
+		crop->left = frame->offs_h;
+		crop->top = frame->offs_v;
+		crop->width = frame->width;
+		crop->height = frame->height;
+	}
+
+	return 0;
+}
+
+static int flite_subdev_get_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+				 struct v4l2_subdev_crop *crop)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct v4l2_rect fcrop;
+
+	fcrop.left = fcrop.top = fcrop.width = fcrop.height = 0;
+
+	if (crop->pad != FLITE_PAD_SINK) {
+		flite_err("crop is supported only sink pad");
+		return -EINVAL;
+	}
+
+	__flite_get_crop(flite, fh, crop->pad, crop->which, &fcrop);
+	crop->rect = fcrop;
+
+	return 0;
+}
+
+static int flite_subdev_set_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+				 struct v4l2_subdev_crop *crop)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct flite_frame *f_frame = flite_get_frame(flite, crop->pad);
+
+	if (!(flite->output & FLITE_OUTPUT_MEM) && (crop->pad != FLITE_PAD_SINK)) {
+		flite_err("crop is supported only sink pad");
+		return -EINVAL;
+	}
+
+	flite_try_crop(flite, crop);
+
+	if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		f_frame->offs_h = crop->rect.left;
+		f_frame->offs_v = crop->rect.top;
+		f_frame->width = crop->rect.width;
+		f_frame->height = crop->rect.height;
+	}
+
+	return 0;
+}
+
+static int flite_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+	struct v4l2_subdev_format format;
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	if (!test_bit(FLITE_ST_SUBDEV_OPEN, &flite->state)) {
+		flite->s_frame.fmt = get_format(2);
+		memset(&format, 0, sizeof(format));
+		format.pad = FLITE_PAD_SINK;
+		format.which = fh ?
+			V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
+		format.format.code = flite->s_frame.fmt->code;
+		format.format.width = DEFAULT_FLITE_SINK_WIDTH;
+		format.format.height = DEFAULT_FLITE_SINK_HEIGHT;
+
+		flite_subdev_set_fmt(sd, fh, &format);
+
+		flite->d_frame.fmt = get_format(2);
+		set_bit(FLITE_ST_SUBDEV_OPEN, &flite->state);
+	}
+
+	return 0;
+}
+
+static int flite_subdev_close(struct v4l2_subdev *sd,
+			      struct v4l2_subdev_fh *fh)
+{
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	flite_info("");
+	clear_bit(FLITE_ST_SUBDEV_OPEN, &flite->state);
+	return 0;
+}
+
+static int flite_subdev_registered(struct v4l2_subdev *sd)
+{
+	flite_dbg("");
+	return 0;
+}
+
+static void flite_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	flite_dbg("");
+}
+
+static const struct v4l2_subdev_internal_ops flite_v4l2_internal_ops = {
+	.open = flite_init_formats,
+	.close = flite_subdev_close,
+	.registered = flite_subdev_registered,
+	.unregistered = flite_subdev_unregistered,
+};
+
+static int flite_link_setup(struct media_entity *entity,
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	switch (local->index | media_entity_type(remote->entity)) {
+	case FLITE_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			flite_info("sink link enabled");
+			if (flite->input != FLITE_INPUT_NONE) {
+				flite_err("link is busy");
+				return -EBUSY;
+			}
+			if (remote->index == CSIS_PAD_SOURCE)
+				flite->input = FLITE_INPUT_CSIS;
+			else
+				flite->input = FLITE_INPUT_SENSOR;
+		} else {
+			flite_info("sink link disabled");
+			flite->input = FLITE_INPUT_NONE;
+		}
+		break;
+
+	case FLITE_PAD_SOURCE_PREV | MEDIA_ENT_T_V4L2_SUBDEV: /* fall through */
+	case FLITE_PAD_SOURCE_CAMCORD | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			flite_info("source link enabled");
+			flite->output |= FLITE_OUTPUT_GSC;
+		} else {
+			flite_info("source link disabled");
+			flite->output &= ~FLITE_OUTPUT_GSC;
+		}
+		break;
+	case FLITE_PAD_SOURCE_MEM | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			flite_info("source link enabled");
+			flite->output |= FLITE_OUTPUT_MEM;
+		} else {
+			flite_info("source link disabled");
+			flite->output &= ~FLITE_OUTPUT_MEM;
+		}
+		break;
+	default:
+		flite_err("ERR link");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct media_entity_operations flite_media_ops = {
+	.link_setup = flite_link_setup,
+};
+
+static struct v4l2_subdev_pad_ops flite_pad_ops = {
+	.enum_mbus_code = flite_subdev_enum_mbus_code,
+	.get_fmt	= flite_subdev_get_fmt,
+	.set_fmt	= flite_subdev_set_fmt,
+	.get_crop	= flite_subdev_get_crop,
+	.set_crop	= flite_subdev_set_crop,
+};
+
+static void flite_pipeline_prepare(struct flite_dev *flite, struct media_entity *me)
+{
+	struct media_entity_graph graph;
+	struct v4l2_subdev *sd;
+
+	media_entity_graph_walk_start(&graph, me);
+
+	while ((me = media_entity_graph_walk_next(&graph))) {
+		flite_info("me->name : %s", me->name);
+		if (media_entity_type(me) != MEDIA_ENT_T_V4L2_SUBDEV)
+			continue;
+		sd = media_entity_to_v4l2_subdev(me);
+		switch (sd->grp_id) {
+		case FLITE_GRP_ID:
+			flite->pipeline.flite = sd;
+			break;
+		case SENSOR_GRP_ID:
+			flite->pipeline.sensor = sd;
+			break;
+		case CSIS_GRP_ID:
+			flite->pipeline.csis = sd;
+			break;
+		default:
+			flite_warn("Another link's group id");
+			break;
+		}
+	}
+
+	flite_info("flite->pipeline.flite : 0x%p", flite->pipeline.flite);
+	flite_info("flite->pipeline.sensor : 0x%p", flite->pipeline.sensor);
+	flite_info("flite->pipeline.csis : 0x%p", flite->pipeline.csis);
+}
+
+static void flite_set_cam_clock(struct flite_dev *flite, bool on)
+{
+	struct v4l2_subdev *sd = flite->pipeline.sensor;
+
+	clk_enable(flite->gsc_clk);
+	if (flite->pipeline.sensor) {
+		struct flite_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
+		on ? clk_enable(s_info->camclk) : clk_disable(s_info->camclk);
+	}
+}
+
+static int __subdev_set_power(struct v4l2_subdev *sd, int on)
+{
+	int *use_count;
+	int ret;
+
+	if (sd == NULL)
+		return -ENXIO;
+
+	use_count = &sd->entity.use_count;
+	if (on && (*use_count)++ > 0)
+		return 0;
+	else if (!on && (*use_count == 0 || --(*use_count) > 0))
+		return 0;
+	ret = v4l2_subdev_call(sd, core, s_power, on);
+
+	return ret != -ENOIOCTLCMD ? ret : 0;
+}
+
+static int flite_pipeline_s_power(struct flite_dev *flite, int state)
+{
+	int ret = 0;
+
+	if (!flite->pipeline.sensor)
+		return -ENXIO;
+
+	if (state) {
+		ret = __subdev_set_power(flite->pipeline.flite, 1);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(flite->pipeline.csis, 1);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(flite->pipeline.sensor, 1);
+	} else {
+		ret = __subdev_set_power(flite->pipeline.flite, 0);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(flite->pipeline.sensor, 0);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(flite->pipeline.csis, 0);
+	}
+	return ret == -ENXIO ? 0 : ret;
+}
+
+static int __flite_pipeline_initialize(struct flite_dev *flite,
+					 struct media_entity *me, bool prep)
+{
+	int ret = 0;
+
+	if (prep)
+		flite_pipeline_prepare(flite, me);
+
+	if (!flite->pipeline.sensor)
+		return -EINVAL;
+
+	flite_set_cam_clock(flite, true);
+
+	if (flite->pipeline.sensor)
+		ret = flite_pipeline_s_power(flite, 1);
+
+	return ret;
+}
+
+static int flite_pipeline_initialize(struct flite_dev *flite,
+				struct media_entity *me, bool prep)
+{
+	int ret;
+
+	mutex_lock(&me->parent->graph_mutex);
+	ret =  __flite_pipeline_initialize(flite, me, prep);
+	mutex_unlock(&me->parent->graph_mutex);
+
+	return ret;
+}
+
+static int flite_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct flite_dev *flite = ctrl_to_dev(ctrl);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CACHEABLE:
+		user_to_drv(flite->flite_ctrls.cacheable, ctrl->val);
+		break;
+	default:
+		flite_err("unsupported ctrl id");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+const struct v4l2_ctrl_ops flite_ctrl_ops = {
+	.s_ctrl = flite_s_ctrl,
+};
+
+static const struct v4l2_ctrl_config flite_custom_ctrl[] = {
+	{
+		.ops = &flite_ctrl_ops,
+		.id = V4L2_CID_CACHEABLE,
+		.name = "Set cacheable",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = 1,
+		.def = true,
+	},
+};
+
+static int flite_ctrls_create(struct flite_dev *flite)
+{
+	if (flite->ctrls_rdy)
+		return 0;
+
+	v4l2_ctrl_handler_init(&flite->ctrl_handler, FLITE_MAX_CTRL_NUM);
+	flite->flite_ctrls.cacheable = v4l2_ctrl_new_custom(&flite->ctrl_handler,
+					&flite_custom_ctrl[0], NULL);
+	flite->ctrls_rdy = flite->ctrl_handler.error == 0;
+
+	if (flite->ctrl_handler.error) {
+		int err = flite->ctrl_handler.error;
+		v4l2_ctrl_handler_free(&flite->ctrl_handler);
+		flite_err("Failed to flite control hander create");
+		return err;
+	}
+
+	return 0;
+}
+
+static void flite_ctrls_delete(struct flite_dev *flite)
+{
+	if (flite->ctrls_rdy) {
+		v4l2_ctrl_handler_free(&flite->ctrl_handler);
+		flite->ctrls_rdy = false;
+	}
+}
+
+static int flite_open(struct file *file)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	int ret = v4l2_fh_open(file);
+
+	if (ret)
+		return ret;
+
+	if (test_bit(FLITE_ST_OPEN, &flite->state)) {
+		v4l2_fh_release(file);
+		return -EBUSY;
+	}
+
+	set_bit(FLITE_ST_OPEN, &flite->state);
+
+	if (++flite->refcnt == 1) {
+		ret = flite_pipeline_initialize(flite, &flite->vfd->entity, true);
+		if (ret < 0) {
+			flite_err("flite pipeline initialization failed\n");
+			goto err;
+		}
+
+		ret = flite_ctrls_create(flite);
+		if (ret) {
+			flite_err("failed to create controls\n");
+			goto err;
+		}
+
+	}
+
+	flite_info("pid: %d, state: 0x%lx", task_pid_nr(current), flite->state);
+
+	return 0;
+
+err:
+	v4l2_fh_release(file);
+	clear_bit(FLITE_ST_OPEN, &flite->state);
+	return ret;
+}
+
+int __flite_pipeline_shutdown(struct flite_dev *flite)
+{
+	int ret = 0;
+
+	if (flite->pipeline.sensor)
+		ret = flite_pipeline_s_power(flite, 0);
+
+	if (ret && ret != -ENXIO)
+		flite_set_cam_clock(flite, false);
+
+	flite->pipeline.flite = NULL;
+	flite->pipeline.csis = NULL;
+	flite->pipeline.sensor = NULL;
+
+	return ret == -ENXIO ? 0 : ret;
+}
+
+int flite_pipeline_shutdown(struct flite_dev *flite)
+{
+	struct media_entity *me = &flite->vfd->entity;
+	int ret;
+
+	mutex_lock(&me->parent->graph_mutex);
+	ret = __flite_pipeline_shutdown(flite);
+	mutex_unlock(&me->parent->graph_mutex);
+
+	return ret;
+}
+
+static int flite_close(struct file *file)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct flite_buffer *buf;
+
+	flite_info("pid: %d, state: 0x%lx", task_pid_nr(current), flite->state);
+
+	if (--flite->refcnt == 0) {
+		clear_bit(FLITE_ST_OPEN, &flite->state);
+		flite_info("FIMC-LITE h/w disable control");
+		flite_hw_set_capture_stop(flite);
+		clear_bit(FLITE_ST_STREAM, &flite->state);
+		flite_pipeline_shutdown(flite);
+		clear_bit(FLITE_ST_SUSPEND, &flite->state);
+	}
+
+	if (flite->refcnt == 0) {
+		while (!list_empty(&flite->pending_buf_q)) {
+			flite_info("clean pending q");
+			buf = pending_queue_pop(flite);
+			vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+		}
+
+		while (!list_empty(&flite->active_buf_q)) {
+			flite_info("clean active q");
+			buf = active_queue_pop(flite);
+			vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+		}
+		vb2_queue_release(&flite->vbq);
+		flite_ctrls_delete(flite);
+	}
+
+	return v4l2_fh_release(file);
+}
+
+static unsigned int flite_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	return vb2_poll(&flite->vbq, file, wait);
+}
+
+static int flite_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	return vb2_mmap(&flite->vbq, vma);
+}
+
+/*
+ * videobuf2 operations
+ */
+
+int flite_pipeline_s_stream(struct flite_dev *flite, int on)
+{
+	struct flite_pipeline *p = &flite->pipeline;
+	int ret = 0;
+
+	if (!p->sensor)
+		return -ENODEV;
+
+	if (on) {
+		ret = v4l2_subdev_call(p->flite, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(p->csis, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(p->sensor, video, s_stream, 1);
+	} else {
+		ret = v4l2_subdev_call(p->sensor, video, s_stream, 0);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(p->csis, video, s_stream, 0);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		ret = v4l2_subdev_call(p->flite, video, s_stream, 0);
+	}
+
+	return ret == -ENOIOCTLCMD ? 0 : ret;
+}
+
+static int flite_start_streaming(struct vb2_queue *q)
+{
+	struct flite_dev *flite = q->drv_priv;
+
+	flite_hw_reset(flite);
+	if (soc_is_exynos5250_rev1) {
+		flite_info("");
+		flite_hw_set_framecnt_seq_masking(flite, flite->reqbufs_cnt);
+	}
+
+	flite->active_buf_cnt = 0;
+	flite->pending_buf_cnt = 0;
+
+	flite->mdev->is_flite_on= true;
+	return 0;
+}
+
+static int flite_state_cleanup(struct flite_dev *flite)
+{
+	unsigned long flags;
+	bool streaming;
+
+	spin_lock_irqsave(&flite->slock, flags);
+	streaming = flite->state & (1 << FLITE_ST_PIPE_STREAM);
+
+	flite->state &= ~(1 << FLITE_ST_RUN | 1 << FLITE_ST_STREAM |
+			1 << FLITE_ST_PIPE_STREAM | 1 << FLITE_ST_PEND);
+
+	set_bit(FLITE_ST_SUSPEND, &flite->state);
+	spin_unlock_irqrestore(&flite->slock, flags);
+
+	if (streaming)
+		return flite_pipeline_s_stream(flite, 0);
+	else
+		return 0;
+}
+
+static int flite_stop_capture(struct flite_dev *flite)
+{
+	if (!flite_active(flite)) {
+		flite_warn("already stopped\n");
+		return 0;
+	}
+	flite_info("FIMC-Lite H/W disable control");
+	flite_hw_set_capture_stop(flite);
+	clear_bit(FLITE_ST_STREAM, &flite->state);
+
+	return flite_state_cleanup(flite);
+}
+
+static int flite_stop_streaming(struct vb2_queue *q)
+{
+	struct flite_dev *flite = q->drv_priv;
+
+	if (!flite_active(flite))
+		return -EINVAL;
+
+	flite->mdev->is_flite_on= false;
+
+	return flite_stop_capture(flite);
+}
+
+static u32 get_plane_size(struct flite_frame *frame, unsigned int plane)
+{
+	if (!frame) {
+		flite_err("frame is null");
+		return 0;
+	}
+
+	return frame->payload;
+}
+
+static int flite_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+		       unsigned int *num_planes, unsigned long sizes[],
+		       void *allocators[])
+{
+	struct flite_dev *flite = vq->drv_priv;
+	struct flite_fmt *fmt = flite->d_frame.fmt;
+
+	if (!fmt)
+		return -EINVAL;
+
+	*num_planes = 1;
+
+	sizes[0] = get_plane_size(&flite->d_frame, 0);
+	allocators[0] = flite->alloc_ctx;
+
+	return 0;
+}
+
+static int flite_buf_prepare(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct flite_dev *flite = vq->drv_priv;
+	struct flite_frame *frame = &flite->d_frame;
+	unsigned long size;
+
+	if (frame->fmt == NULL)
+		return -EINVAL;
+
+	size = frame->payload;
+
+	if (vb2_plane_size(vb, 0) < size) {
+		v4l2_err(flite->vfd, "User buffer too small (%ld < %ld)\n",
+			 vb2_plane_size(vb, 0), size);
+		return -EINVAL;
+	}
+	vb2_set_plane_payload(vb, 0, size);
+
+	if (frame->cacheable)
+		flite->vb2->cache_flush(vb, 1);
+
+	return 0;
+}
+
+/* The color format (nr_comp, num_planes) must be already configured. */
+int flite_prepare_addr(struct flite_dev *flite, struct vb2_buffer *vb,
+		     struct flite_frame *frame, struct flite_addr *addr)
+{
+	if (IS_ERR(vb) || IS_ERR(frame)) {
+		flite_err("Invalid argument");
+		return -EINVAL;
+	}
+
+	addr->y = flite->vb2->plane_addr(vb, 0);
+
+	flite_dbg("ADDR: y= 0x%X", addr->y);
+
+	return 0;
+}
+
+
+static void flite_buf_queue(struct vb2_buffer *vb)
+{
+	struct flite_buffer *buf = container_of(vb, struct flite_buffer, vb);
+	struct flite_dev *flite = vb2_get_drv_priv(vb->vb2_queue);
+	int min_bufs;
+	unsigned long flags;
+
+	spin_lock_irqsave(&flite->slock, flags);
+	flite_prepare_addr(flite, &buf->vb, &flite->d_frame, &buf->paddr);
+
+	min_bufs = flite->reqbufs_cnt > 1 ? 2 : 1;
+
+	if (flite->active_buf_cnt < FLITE_MAX_OUT_BUFS) {
+		active_queue_add(flite, buf);
+		flite_hw_set_output_addr(flite, &buf->paddr, vb->v4l2_buf.index);
+	} else {
+		pending_queue_add(flite, buf);
+	}
+
+	if (vb2_is_streaming(&flite->vbq) &&
+		(available_buf_cnt(flite) >= min_bufs) &&
+		!test_bit(FLITE_ST_STREAM, &flite->state)) {
+		if (!test_and_set_bit(FLITE_ST_PIPE_STREAM, &flite->state)) {
+			spin_unlock_irqrestore(&flite->slock, flags);
+			flite_pipeline_s_stream(flite, 1);
+			return;
+		}
+
+		if (!test_bit(FLITE_ST_STREAM, &flite->state)) {
+			flite_info("G-Scaler h/w enable control");
+			flite_hw_set_capture_start(flite);
+			set_bit(FLITE_ST_STREAM, &flite->state);
+		}
+	}
+	spin_unlock_irqrestore(&flite->slock, flags);
+
+	return;
+}
+
+static struct vb2_ops flite_qops = {
+	.queue_setup		= flite_queue_setup,
+	.buf_prepare		= flite_buf_prepare,
+	.buf_queue		= flite_buf_queue,
+	.wait_prepare		= flite_unlock,
+	.wait_finish		= flite_lock,
+	.start_streaming	= flite_start_streaming,
+	.stop_streaming		= flite_stop_streaming,
+};
+
+/*
+ * The video node ioctl operations
+ */
+static int flite_vidioc_querycap(struct file *file, void *priv,
+				       struct v4l2_capability *cap)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	strncpy(cap->driver, flite->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, flite->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int flite_enum_fmt_mplane(struct file *file, void *priv,
+					struct v4l2_fmtdesc *f)
+{
+	struct flite_fmt *fmt;
+
+	fmt = find_format(NULL, NULL, f->index);
+	if (!fmt)
+		return -EINVAL;
+
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->pixelformat;
+
+	return 0;
+}
+
+static int flite_try_fmt_mplane(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+	struct flite_fmt *fmt;
+	u32 max_w, max_h, mod_x, mod_y;
+	u32 min_w, min_h, tmp_w, tmp_h;
+	int i;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	flite_dbg("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
+
+	fmt = find_format(&pix_mp->pixelformat, NULL, 0);
+	if (!fmt) {
+		flite_err("pixelformat format (0x%X) invalid\n", pix_mp->pixelformat);
+		return -EINVAL;
+	}
+
+	max_w = variant.max_w;
+	max_h = variant.max_h;
+	min_w = min_h = mod_y = 0;
+
+	if (fmt->is_yuv)
+		mod_x = ffs(variant.align_out_w / 2) - 1;
+	else
+		mod_x = ffs(variant.align_out_w) - 1;
+
+	flite_dbg("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
+	     mod_x, mod_y, max_w, max_h);
+	/* To check if image size is modified to adjust parameter against
+	   hardware abilities */
+	tmp_w = pix_mp->width;
+	tmp_h = pix_mp->height;
+
+	v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
+		&pix_mp->height, min_h, max_h, mod_y, 0);
+	if (tmp_w != pix_mp->width || tmp_h != pix_mp->height)
+		flite_info("Image size has been modified from %dx%d to %dx%d",
+			 tmp_w, tmp_h, pix_mp->width, pix_mp->height);
+
+	pix_mp->num_planes = 1;
+
+	for (i = 0; i < pix_mp->num_planes; ++i) {
+		int bpl = (pix_mp->width * fmt->depth[i]) >> 3;
+		pix_mp->plane_fmt[i].bytesperline = bpl;
+		pix_mp->plane_fmt[i].sizeimage = bpl * pix_mp->height;
+
+		flite_dbg("[%d]: bpl: %d, sizeimage: %d",
+		    i, bpl, pix_mp->plane_fmt[i].sizeimage);
+	}
+
+	return 0;
+}
+
+void flite_set_frame_size(struct flite_frame *frame, int width, int height)
+{
+	frame->o_width	= width;
+	frame->o_height	= height;
+	frame->width = width;
+	frame->height = height;
+	frame->offs_h = 0;
+	frame->offs_v = 0;
+}
+
+static int flite_s_fmt_mplane(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct flite_frame *frame;
+	struct v4l2_pix_format_mplane *pix;
+	int ret = 0;
+
+	ret = flite_try_fmt_mplane(file, fh, f);
+	if (ret)
+		return ret;
+
+	if (vb2_is_streaming(&flite->vbq)) {
+		flite_err("queue (%d) busy", f->type);
+		return -EBUSY;
+	}
+
+	frame = &flite->d_frame;
+
+	pix = &f->fmt.pix_mp;
+	frame->fmt = find_format(&pix->pixelformat, NULL, 0);
+	if (!frame->fmt)
+		return -EINVAL;
+
+	frame->payload = pix->plane_fmt[0].bytesperline * pix->height;
+	flite_set_frame_size(frame, pix->width, pix->height);
+
+	flite_info("f_w: %d, f_h: %d", frame->o_width, frame->o_height);
+
+	return 0;
+}
+
+static int flite_g_fmt_mplane(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct flite_frame *frame;
+	struct v4l2_pix_format_mplane *pix_mp;
+	int i;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	frame = &flite->d_frame;
+
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	pix_mp = &f->fmt.pix_mp;
+
+	pix_mp->width		= frame->o_width;
+	pix_mp->height		= frame->o_height;
+	pix_mp->field		= V4L2_FIELD_NONE;
+	pix_mp->pixelformat	= frame->fmt->pixelformat;
+	pix_mp->colorspace	= V4L2_COLORSPACE_JPEG;
+	pix_mp->num_planes	= 1;
+
+	for (i = 0; i < pix_mp->num_planes; ++i) {
+		pix_mp->plane_fmt[i].bytesperline = (frame->o_width *
+			frame->fmt->depth[i]) / 8;
+		pix_mp->plane_fmt[i].sizeimage = pix_mp->plane_fmt[i].bytesperline *
+			frame->o_height;
+	}
+
+	return 0;
+}
+
+static int flite_reqbufs(struct file *file, void *priv,
+			    struct v4l2_requestbuffers *reqbufs)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct flite_frame *frame;
+	int ret;
+
+	frame = &flite->d_frame;
+	frame->cacheable = flite->flite_ctrls.cacheable->val;
+	flite->vb2->set_cacheable(flite->alloc_ctx, frame->cacheable);
+
+	ret = vb2_reqbufs(&flite->vbq, reqbufs);
+	if (!ret)
+		flite->reqbufs_cnt = reqbufs->count;
+
+	return ret;
+}
+
+static int flite_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	return vb2_querybuf(&flite->vbq, buf);
+}
+
+static int flite_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	return vb2_qbuf(&flite->vbq, buf);
+}
+
+static int flite_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct flite_dev *flite = video_drvdata(file);
+
+	return vb2_dqbuf(&flite->vbq, buf, file->f_flags & O_NONBLOCK);
+}
+
+static int flite_link_validate(struct flite_dev *flite)
+{
+	struct v4l2_subdev_format sink_fmt, src_fmt;
+	struct v4l2_subdev *sd;
+	struct media_pad *pad;
+	int ret;
+
+	/* Get the source pad connected with flite-video */
+	pad =  media_entity_remote_source(&flite->vd_pad);
+	if (pad == NULL)
+		return -EPIPE;
+	/* Get the subdev of source pad */
+	sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	while (1) {
+		/* Find sink pad of the subdev*/
+		pad = &sd->entity.pads[0];
+		if (!(pad->flags & MEDIA_PAD_FL_SINK))
+			break;
+		if (sd == flite->sd_flite) {
+			struct flite_frame *f = &flite->s_frame;
+			sink_fmt.format.width = f->o_width;
+			sink_fmt.format.height = f->o_height;
+			sink_fmt.format.code = f->fmt ? f->fmt->code : 0;
+		} else {
+			sink_fmt.pad = pad->index;
+			sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+			ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
+			if (ret < 0 && ret != -ENOIOCTLCMD) {
+				flite_err("failed %s subdev get_fmt", sd->name);
+				return -EPIPE;
+			}
+		}
+		flite_info("sink sd name : %s", sd->name);
+		/* Get the source pad connected with remote sink pad */
+		pad = media_entity_remote_source(pad);
+		if (pad == NULL ||
+		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
+			break;
+
+		/* Get the subdev of source pad */
+		sd = media_entity_to_v4l2_subdev(pad->entity);
+		flite_info("source sd name : %s", sd->name);
+
+		src_fmt.pad = pad->index;
+		src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+		ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
+		if (ret < 0 && ret != -ENOIOCTLCMD) {
+			flite_err("failed %s subdev get_fmt", sd->name);
+			return -EPIPE;
+		}
+
+		flite_info("src_width : %d, src_height : %d, src_code : %d",
+			src_fmt.format.width, src_fmt.format.height,
+			src_fmt.format.code);
+		flite_info("sink_width : %d, sink_height : %d, sink_code : %d",
+			sink_fmt.format.width, sink_fmt.format.height,
+			sink_fmt.format.code);
+
+		if (src_fmt.format.width != sink_fmt.format.width ||
+		    src_fmt.format.height != sink_fmt.format.height ||
+		    src_fmt.format.code != sink_fmt.format.code) {
+			flite_err("mismatch sink and source");
+			return -EPIPE;
+		}
+	}
+
+	return 0;
+}
+static int flite_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct flite_pipeline *p = &flite->pipeline;
+	int ret;
+
+	if (flite_active(flite))
+		return -EBUSY;
+
+	if (p->sensor) {
+		media_entity_pipeline_start(&p->sensor->entity, p->pipe);
+	} else {
+		flite_err("Error pipeline");
+		return -EPIPE;
+	}
+
+	ret = flite_link_validate(flite);
+	if (ret)
+		return ret;
+
+	return vb2_streamon(&flite->vbq, type);
+}
+
+static int flite_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct v4l2_subdev *sd = flite->pipeline.sensor;
+	int ret;
+
+	ret = vb2_streamoff(&flite->vbq, type);
+	if (ret == 0)
+		media_entity_pipeline_stop(&sd->entity);
+	return ret;
+}
+
+static int flite_enum_input(struct file *file, void *priv,
+			       struct v4l2_input *i)
+{
+	struct flite_dev *flite = video_drvdata(file);
+	struct exynos_platform_flite *pdata = flite->pdata;
+	struct exynos_isp_info *isp_info;
+
+	if (i->index >= MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	isp_info = pdata->isp_info[i->index];
+	if (isp_info == NULL)
+		return -EINVAL;
+
+	i->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(i->name, isp_info->board_info->type, 32);
+
+	return 0;
+
+}
+
+static int flite_s_input(struct file *file, void *priv, unsigned int i)
+{
+	return i == 0 ? 0 : -EINVAL;
+}
+
+static int flite_g_input(struct file *file, void *priv, unsigned int *i)
+{
+	*i = 0;
+	return 0;
+}
+
+
+static const struct v4l2_ioctl_ops flite_capture_ioctl_ops = {
+	.vidioc_querycap		= flite_vidioc_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= flite_enum_fmt_mplane,
+	.vidioc_try_fmt_vid_cap_mplane	= flite_try_fmt_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= flite_s_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= flite_g_fmt_mplane,
+
+	.vidioc_reqbufs			= flite_reqbufs,
+	.vidioc_querybuf		= flite_querybuf,
+
+	.vidioc_qbuf			= flite_qbuf,
+	.vidioc_dqbuf			= flite_dqbuf,
+
+	.vidioc_streamon		= flite_streamon,
+	.vidioc_streamoff		= flite_streamoff,
+
+	.vidioc_enum_input		= flite_enum_input,
+	.vidioc_s_input			= flite_s_input,
+	.vidioc_g_input			= flite_g_input,
+};
+
+static const struct v4l2_file_operations flite_fops = {
+	.owner		= THIS_MODULE,
+	.open		= flite_open,
+	.release	= flite_close,
+	.poll		= flite_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= flite_mmap,
+};
+
+static int flite_config_camclk(struct flite_dev *flite,
+		struct exynos_isp_info *isp_info, int i)
+{
+	struct clk *camclk;
+	struct clk *srclk;
+
+	camclk = clk_get(&flite->pdev->dev, isp_info->cam_clk_name);
+	if (IS_ERR_OR_NULL(camclk)) {
+		flite_err("failed to get cam clk");
+		return -ENXIO;
+	}
+	flite->sensor[i].camclk = camclk;
+
+	srclk = clk_get(&flite->pdev->dev, isp_info->cam_srclk_name);
+	if (IS_ERR_OR_NULL(srclk)) {
+		clk_put(camclk);
+		flite_err("failed to get cam source clk\n");
+		return -ENXIO;
+	}
+	clk_set_parent(camclk, srclk);
+	clk_set_rate(camclk, isp_info->clk_frequency);
+	clk_put(srclk);
+
+	flite->gsc_clk = clk_get(&flite->pdev->dev, "gscl");
+	if (IS_ERR_OR_NULL(flite->gsc_clk)) {
+		flite_err("failed to get gscl clk");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
+static struct v4l2_subdev *flite_register_sensor(struct flite_dev *flite,
+		int i)
+{
+	struct exynos_platform_flite *pdata = flite->pdata;
+	struct exynos_isp_info *isp_info = pdata->isp_info[i];
+	struct exynos_md *mdev = flite->mdev;
+	struct i2c_adapter *adapter;
+	struct v4l2_subdev *sd = NULL;
+
+	adapter = i2c_get_adapter(isp_info->i2c_bus_num);
+	if (!adapter)
+		return NULL;
+	sd = v4l2_i2c_new_subdev_board(&mdev->v4l2_dev, adapter,
+				       isp_info->board_info, NULL);
+	if (IS_ERR_OR_NULL(sd)) {
+		v4l2_err(&mdev->v4l2_dev, "Failed to acquire subdev\n");
+		return NULL;
+	}
+	v4l2_set_subdev_hostdata(sd, &flite->sensor[i]);
+	sd->grp_id = SENSOR_GRP_ID;
+
+	v4l2_info(&mdev->v4l2_dev, "Registered sensor subdevice %s\n",
+		  isp_info->board_info->type);
+
+	return sd;
+}
+
+static int flite_register_sensor_entities(struct flite_dev *flite)
+{
+	struct exynos_platform_flite *pdata = flite->pdata;
+	u32 num_clients = pdata->num_clients;
+	int i;
+
+	for (i = 0; i < num_clients; i++) {
+		flite->sensor[i].pdata = pdata->isp_info[i];
+		flite->sensor[i].sd = flite_register_sensor(flite, i);
+		if (IS_ERR_OR_NULL(flite->sensor[i].sd)) {
+			flite_err("failed to get register sensor");
+			return -EINVAL;
+		}
+		flite->mdev->sensor_sd[i] = flite->sensor[i].sd;
+	}
+
+	return 0;
+}
+
+static int flite_create_subdev(struct flite_dev *flite, struct v4l2_subdev *sd)
+{
+	struct v4l2_device *v4l2_dev;
+	int ret;
+
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+	flite->pads[FLITE_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	flite->pads[FLITE_PAD_SOURCE_PREV].flags = MEDIA_PAD_FL_SOURCE;
+	flite->pads[FLITE_PAD_SOURCE_CAMCORD].flags = MEDIA_PAD_FL_SOURCE;
+	flite->pads[FLITE_PAD_SOURCE_MEM].flags = MEDIA_PAD_FL_SOURCE;
+
+	ret = media_entity_init(&sd->entity, FLITE_PADS_NUM,
+				flite->pads, 0);
+	if (ret)
+		goto err_ent;
+
+	sd->internal_ops = &flite_v4l2_internal_ops;
+	sd->entity.ops = &flite_media_ops;
+	sd->grp_id = FLITE_GRP_ID;
+	v4l2_dev = &flite->mdev->v4l2_dev;
+	flite->mdev->flite_sd[flite->id] = sd;
+
+	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+	if (ret)
+		goto err_sub;
+
+	flite_init_formats(sd, NULL);
+
+	return 0;
+
+err_sub:
+	media_entity_cleanup(&sd->entity);
+err_ent:
+	return ret;
+}
+
+static int flite_create_link(struct flite_dev *flite)
+{
+	struct media_entity *source, *sink;
+	struct exynos_platform_flite *pdata = flite->pdata;
+	struct exynos_isp_info *isp_info;
+	u32 num_clients = pdata->num_clients;
+	int ret, i;
+	enum cam_port id;
+
+	/* FIMC-LITE-SUBDEV ------> FIMC-LITE-VIDEO (Always link enable) */
+	source = &flite->sd_flite->entity;
+	sink = &flite->vfd->entity;
+	if (source && sink) {
+		ret = media_entity_create_link(source, FLITE_PAD_SOURCE_MEM, sink,
+				0, 0);
+		if (ret) {
+			flite_err("failed link flite-subdev to flite-video\n");
+			return ret;
+		}
+	}
+	/* link sensor to mipi-csis */
+	for (i = 0; i < num_clients; i++) {
+		isp_info = pdata->isp_info[i];
+		id = isp_info->cam_port;
+		switch (isp_info->bus_type) {
+		case CAM_TYPE_ITU:
+			/*	SENSOR ------> FIMC-LITE	*/
+			source = &flite->sensor[i].sd->entity;
+			sink = &flite->sd_flite->entity;
+			if (source && sink) {
+				ret = media_entity_create_link(source, 0,
+					      sink, FLITE_PAD_SINK, 0);
+				if (ret) {
+					flite_err("failed link sensor to flite\n");
+					return ret;
+				}
+			}
+			break;
+		case CAM_TYPE_MIPI:
+			/*	SENSOR ------> MIPI-CSI2	*/
+			source = &flite->sensor[i].sd->entity;
+			sink = &flite->sd_csis->entity;
+			if (source && sink) {
+				ret = media_entity_create_link(source, 0,
+					      sink, CSIS_PAD_SINK, 0);
+				if (ret) {
+					flite_err("failed link sensor to csis\n");
+					return ret;
+				}
+			}
+			/*	MIPI-CSI2 ------> FIMC-LITE	*/
+			source = &flite->sd_csis->entity;
+			sink = &flite->sd_flite->entity;
+			if (source && sink) {
+				ret = media_entity_create_link(source,
+						CSIS_PAD_SOURCE,
+						sink, FLITE_PAD_SINK, 0);
+				if (ret) {
+					flite_err("failed link csis to flite\n");
+					return ret;
+				}
+			}
+			break;
+		}
+	}
+
+	flite->input = FLITE_INPUT_NONE;
+	flite->output = FLITE_OUTPUT_NONE;
+
+	return 0;
+}
+static int flite_register_video_device(struct flite_dev *flite)
+{
+	struct video_device *vfd;
+	struct vb2_queue *q;
+	int ret = -ENOMEM;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		printk("Failed to allocate video device\n");
+		return ret;
+	}
+
+	snprintf(vfd->name, sizeof(vfd->name), "%s", dev_name(&flite->pdev->dev));
+
+	vfd->fops	= &flite_fops;
+	vfd->ioctl_ops	= &flite_capture_ioctl_ops;
+	vfd->v4l2_dev	= &flite->mdev->v4l2_dev;
+	vfd->minor	= -1;
+	vfd->release	= video_device_release;
+	vfd->lock	= &flite->lock;
+	video_set_drvdata(vfd, flite);
+
+	flite->vfd = vfd;
+	flite->refcnt = 0;
+	flite->reqbufs_cnt  = 0;
+	INIT_LIST_HEAD(&flite->active_buf_q);
+	INIT_LIST_HEAD(&flite->pending_buf_q);
+
+	q = &flite->vbq;
+	memset(q, 0, sizeof(*q));
+	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	q->io_modes = VB2_MMAP | VB2_USERPTR;
+	q->drv_priv = flite;
+	q->ops = &flite_qops;
+	q->mem_ops = flite->vb2->ops;
+
+	vb2_queue_init(q);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER,
+				    EXYNOS_VIDEONODE_FLITE(flite->id));
+	if (ret) {
+		flite_err("failed to register video device");
+		goto err_vfd_alloc;
+	}
+
+	flite->vd_pad.flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&vfd->entity, 1, &flite->vd_pad, 0);
+	if (ret) {
+		flite_err("failed to initialize entity");
+		goto err_unreg_video;
+	}
+
+	vfd->ctrl_handler = &flite->ctrl_handler;
+	flite_dbg("flite video-device driver registered as /dev/video%d", vfd->num);
+
+	return 0;
+
+err_unreg_video:
+	video_unregister_device(vfd);
+err_vfd_alloc:
+	video_device_release(vfd);
+
+	return ret;
+}
+
+static int flite_get_md_callback(struct device *dev, void *p)
+{
+	struct exynos_md **md_list = p;
+	struct exynos_md *md = NULL;
+
+	md = dev_get_drvdata(dev);
+
+	if (md)
+		*(md_list + md->id) = md;
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct exynos_md *flite_get_capture_md(enum mdev_node node)
+{
+	struct device_driver *drv;
+	struct exynos_md *md[MDEV_MAX_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(MDEV_MODULE_NAME, &platform_bus_type);
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &md[0],
+				     flite_get_md_callback);
+	put_driver(drv);
+
+	return ret ? NULL : md[node];
+
+}
+
+static void flite_destroy_subdev(struct flite_dev *flite)
+{
+	struct v4l2_subdev *sd = flite->sd_flite;
+
+	if (!sd)
+		return;
+	media_entity_cleanup(&sd->entity);
+	v4l2_device_unregister_subdev(sd);
+	kfree(sd);
+	sd = NULL;
+}
+
+void flite_unregister_device(struct flite_dev *flite)
+{
+	struct video_device *vfd = flite->vfd;
+
+	if (vfd) {
+		media_entity_cleanup(&vfd->entity);
+		/* Can also be called if video device was
+		   not registered */
+		video_unregister_device(vfd);
+	}
+	flite_destroy_subdev(flite);
+}
+#endif
+
+static int flite_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	printk(KERN_INFO "%s\n", __func__);
+
+	if (test_bit(FLITE_ST_STREAM, &flite->state)) {
+		printk(KERN_INFO "%s flite_s_stream\n", __func__);
+		flite_s_stream(sd, false);
+	}
+	if (test_bit(FLITE_ST_POWER, &flite->state)) {
+		printk(KERN_INFO "%s flite_s_power\n", __func__);
+		flite_s_power(sd, false);
+	}
+
+	set_bit(FLITE_ST_SUSPEND, &flite->state);
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+static int flite_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+
+	printk(KERN_INFO "%s\n", __func__);
+	if (test_bit(FLITE_ST_POWER, &flite->state)) {
+		printk(KERN_INFO "%s flite_s_power\n", __func__);
+		flite_s_power(sd, true);
+	}
+
+	clear_bit(FLITE_ST_SUSPEND, &flite->state);
+
+	if (test_bit(FLITE_ST_STREAM, &flite->state)) {
+		printk(KERN_INFO "%s flite_s_stream\n", __func__);
+		flite_s_stream(sd, true);
+	}
+
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+static int flite_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	unsigned long flags;
+
+	printk(KERN_INFO "%s\n", __func__);
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	flite->vb2->suspend(flite->alloc_ctx);
+	clk_disable(flite->camif_clk);
+#endif
+	spin_lock_irqsave(&flite->slock, flags);
+	set_bit(FLITE_ST_SUSPEND, &flite->state);
+	spin_unlock_irqrestore(&flite->slock, flags);
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+static int flite_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	unsigned long flags;
+
+	printk(KERN_INFO "%s\n", __func__);
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	clk_enable(flite->camif_clk);
+	flite->vb2->resume(flite->alloc_ctx);
+#endif
+	spin_lock_irqsave(&flite->slock, flags);
+	clear_bit(FLITE_ST_SUSPEND, &flite->state);
+	spin_unlock_irqrestore(&flite->slock, flags);
+
+	printk(KERN_INFO "%s--\n", __func__);
+	return 0;
+}
+
+static struct v4l2_subdev_core_ops flite_core_ops = {
+	.s_power = flite_s_power,
+};
+
+static struct v4l2_subdev_video_ops flite_video_ops = {
+	.g_mbus_fmt	= flite_g_mbus_fmt,
+	.s_mbus_fmt	= flite_s_mbus_fmt,
+	.s_stream	= flite_s_stream,
+	.cropcap	= flite_subdev_cropcap,
+	.g_crop		= flite_subdev_g_crop,
+	.s_crop		= flite_subdev_s_crop,
+};
+
+static struct v4l2_subdev_ops flite_subdev_ops = {
+	.core	= &flite_core_ops,
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	.pad	= &flite_pad_ops,
+#endif
+	.video	= &flite_video_ops,
+};
+
+static int flite_probe(struct platform_device *pdev)
+{
+	struct resource *mem_res;
+	struct resource *regs_res;
+	struct flite_dev *flite;
+	struct v4l2_subdev *sd;
+	int ret = -ENODEV;
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	struct exynos_isp_info *isp_info;
+	int i;
+#endif
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "platform data is NULL\n");
+		return -EINVAL;
+	}
+
+	flite = kzalloc(sizeof(struct flite_dev), GFP_KERNEL);
+	if (!flite)
+		return -ENOMEM;
+
+	flite->pdev = pdev;
+	flite->pdata = pdev->dev.platform_data;
+
+	flite->id = pdev->id;
+
+	init_waitqueue_head(&flite->irq_queue);
+	spin_lock_init(&flite->slock);
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "Failed to get io memory region\n");
+		goto err_flite;
+	}
+
+	regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
+				      pdev->name);
+	if (!regs_res) {
+		dev_err(&pdev->dev, "Failed to request io memory region\n");
+		goto err_resource;
+	}
+
+	flite->regs_res = regs_res;
+	flite->regs = ioremap(mem_res->start, resource_size(mem_res));
+	if (!flite->regs) {
+		dev_err(&pdev->dev, "Failed to remap io region\n");
+		goto err_reg_region;
+	}
+
+	flite->irq = platform_get_irq(pdev, 0);
+	if (flite->irq < 0) {
+		dev_err(&pdev->dev, "Failed to get irq\n");
+		goto err_reg_unmap;
+	}
+
+	ret = request_irq(flite->irq, flite_irq_handler, 0, dev_name(&pdev->dev), flite);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq failed\n");
+		goto err_reg_unmap;
+	}
+
+	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
+	if (!sd)
+	       goto err_irq;
+	v4l2_subdev_init(sd, &flite_subdev_ops);
+	snprintf(sd->name, sizeof(sd->name), "flite-subdev.%d", flite->id);
+
+	flite->sd_flite = sd;
+	v4l2_set_subdevdata(flite->sd_flite, flite);
+	if (soc_is_exynos4212() || soc_is_exynos4412())
+		v4l2_set_subdev_hostdata(sd, pdev);
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	flite->vb2 = &flite_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	flite->vb2 = &flite_vb2_ion;
+#endif
+	mutex_init(&flite->lock);
+	flite->mdev = flite_get_capture_md(MDEV_CAPTURE);
+	if (IS_ERR_OR_NULL(flite->mdev))
+		goto err_irq;
+
+	flite_dbg("mdev = 0x%08x", (u32)flite->mdev);
+
+	ret = flite_register_video_device(flite);
+	if (ret)
+		goto err_irq;
+
+	/* Get mipi-csis subdev ptr using mdev */
+	flite->sd_csis = flite->mdev->csis_sd[flite->id];
+
+	for (i = 0; i < flite->pdata->num_clients; i++) {
+		isp_info = flite->pdata->isp_info[i];
+		ret = flite_config_camclk(flite, isp_info, i);
+		if (ret) {
+			flite_err("failed setup cam clk");
+			goto err_vfd_alloc;
+		}
+	}
+
+	ret = flite_register_sensor_entities(flite);
+	if (ret) {
+		flite_err("failed register sensor entities");
+		goto err_clk;
+	}
+
+	ret = flite_create_subdev(flite, sd);
+	if (ret) {
+		flite_err("failed create subdev");
+		goto err_clk;
+	}
+
+	ret = flite_create_link(flite);
+	if (ret) {
+		flite_err("failed create link");
+		goto err_entity;
+	}
+
+	flite->alloc_ctx = flite->vb2->init(flite);
+	if (IS_ERR(flite->alloc_ctx)) {
+		ret = PTR_ERR(flite->alloc_ctx);
+		goto err_entity;
+	}
+
+	flite->camif_clk = clk_get(&flite->pdev->dev, CAMIF_TOP_CLK);
+	if (IS_ERR(flite->camif_clk)) {
+		flite_err("failed to get flite.%d clock", flite->id);
+		goto err_entity;
+	}
+	flite->mdev->is_flite_on= false;
+#endif
+	platform_set_drvdata(flite->pdev, flite->sd_flite);
+	pm_runtime_enable(&pdev->dev);
+
+	flite_info("FIMC-LITE%d probe success", pdev->id);
+
+	return 0;
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+err_entity:
+	media_entity_cleanup(&sd->entity);
+err_clk:
+	for (i = 0; i < flite->pdata->num_clients; i++)
+		clk_put(flite->sensor[i].camclk);
+err_vfd_alloc:
+	media_entity_cleanup(&flite->vfd->entity);
+	video_device_release(flite->vfd);
+#endif
+err_irq:
+	free_irq(flite->irq, flite);
+err_reg_unmap:
+	iounmap(flite->regs);
+err_reg_region:
+	release_mem_region(regs_res->start, resource_size(regs_res));
+err_resource:
+	release_resource(regs_res);
+	kfree(regs_res);
+err_flite:
+	kfree(flite);
+	return ret;
+}
+
+static int flite_remove(struct platform_device *pdev)
+{
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct flite_dev *flite = v4l2_get_subdevdata(sd);
+	struct resource *res = flite->regs_res;
+
+	flite_s_power(flite->sd_flite, 0);
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	flite_subdev_close(sd, NULL);
+	flite_unregister_device(flite);
+	flite->vb2->cleanup(flite->alloc_ctx);
+#endif
+	pm_runtime_disable(&pdev->dev);
+	free_irq(flite->irq, flite);
+	iounmap(flite->regs);
+	release_mem_region(res->start, resource_size(res));
+	kfree(flite);
+
+	return 0;
+}
+
+
+static const struct dev_pm_ops flite_pm_ops = {
+	.suspend		= flite_suspend,
+	.resume			= flite_resume,
+	.runtime_suspend	= flite_runtime_suspend,
+	.runtime_resume		= flite_runtime_resume,
+};
+
+static struct platform_driver flite_driver = {
+	.probe		= flite_probe,
+	.remove	= __devexit_p(flite_remove),
+	.driver = {
+		.name	= MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &flite_pm_ops,
+	}
+};
+
+static int __init flite_init(void)
+{
+	int ret = platform_driver_register(&flite_driver);
+	if (ret)
+		flite_err("platform_driver_register failed: %d", ret);
+	return ret;
+}
+
+static void __exit flite_exit(void)
+{
+	platform_driver_unregister(&flite_driver);
+}
+module_init(flite_init);
+module_exit(flite_exit);
+
+MODULE_AUTHOR("Sky Kang<sungchun.kang@samsung.com>");
+MODULE_DESCRIPTION("Exynos FIMC-Lite driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/fimc-lite/fimc-lite-core.h b/drivers/media/video/exynos/fimc-lite/fimc-lite-core.h
new file mode 100644
index 0000000..2c46c8b
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/fimc-lite-core.h
@@ -0,0 +1,360 @@
+/*
+ * Register interface file for Samsung Camera Interface (FIMC-Lite) driver
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef FLITE_CORE_H_
+#define FLITE_CORE_H_
+
+/* #define DEBUG */
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mediabus.h>
+#include <media/exynos_flite.h>
+#include <media/v4l2-ioctl.h>
+#ifdef CONFIG_ARCH_EXYNOS5
+#include <media/exynos_mc.h>
+#endif
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+#include <plat/cpu.h>
+
+#include "fimc-lite-reg.h"
+
+#define flite_info(fmt, args...) \
+	printk(KERN_INFO "[INFO]%s:%d: "fmt "\n", __func__, __LINE__, ##args)
+#define flite_err(fmt, args...) \
+	printk(KERN_ERR "[ERROR]%s:%d: "fmt "\n", __func__, __LINE__, ##args)
+#define flite_warn(fmt, args...) \
+	printk(KERN_WARNING "[WARNNING]%s:%d: "fmt "\n", __func__, __LINE__, ##args)
+
+#ifdef DEBUG
+#define flite_dbg(fmt, args...) \
+	printk(KERN_DEBUG "[DEBUG]%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define flite_dbg(fmt, args...)
+#endif
+
+#define FLITE_MAX_RESET_READY_TIME	20 /* 100ms */
+#define FLITE_MAX_CTRL_NUM		1
+#define FLITE_MAX_OUT_BUFS (soc_is_exynos5250_rev1 ? flite->reqbufs_cnt	: 1)
+#ifdef CONFIG_ARCH_EXYNOS4
+#define FLITE_MAX_MBUS_NUM		1
+#endif
+
+enum flite_input_entity {
+	FLITE_INPUT_NONE,
+	FLITE_INPUT_SENSOR,
+	FLITE_INPUT_CSIS,
+};
+
+enum flite_output_entity {
+	FLITE_OUTPUT_NONE = (1 << 0),
+	FLITE_OUTPUT_GSC = (1 << 1),
+	FLITE_OUTPUT_MEM = (1 << 2),
+};
+
+enum flite_out_path {
+	FLITE_ISP,
+	FLITE_DMA,
+};
+
+enum flite_state {
+	FLITE_ST_OPEN,
+	FLITE_ST_SUBDEV_OPEN,
+	FLITE_ST_POWER,
+	FLITE_ST_STREAM,
+	FLITE_ST_SUSPEND,
+	FLITE_ST_RUN,
+	FLITE_ST_PIPE_STREAM,
+	FLITE_ST_PEND,
+};
+
+#define flite_active(dev) test_bit(FLITE_ST_RUN, &(dev)->state)
+#define ctrl_to_dev(__ctrl) \
+	container_of((__ctrl)->handler, struct flite_dev, ctrl_handler)
+#define flite_get_frame(flite, pad)\
+	((pad == FLITE_PAD_SINK) ? &flite->s_frame : &flite->d_frame)
+
+#define available_buf_cnt(dev) (soc_is_exynos5250_rev1 ? \
+				dev->active_buf_cnt : dev->pending_buf_cnt)
+struct flite_variant {
+	u16 max_w;
+	u16 max_h;
+	u16 align_win_offs_w;
+	u16 align_out_w;
+	u16 align_out_offs_w;
+};
+
+/**
+  * struct flite_fmt - driver's color format data
+  * @name :	format description
+  * @code :	Media Bus pixel code
+  * @fmt_reg :	H/W bit for setting format
+  */
+struct flite_fmt {
+	char				*name;
+	u32				pixelformat;
+	enum v4l2_mbus_pixelcode	code;
+	u32				fmt_reg;
+	u32				is_yuv;
+	u8				depth[VIDEO_MAX_PLANES];
+};
+
+struct flite_addr {
+	dma_addr_t	y;
+};
+
+/**
+ * struct flite_frame - source/target frame properties
+ * @o_width:	buffer width as set by S_FMT
+ * @o_height:	buffer height as set by S_FMT
+ * @width:	image pixel width
+ * @height:	image pixel weight
+ * @offs_h:	image horizontal pixel offset
+ * @offs_v:	image vertical pixel offset
+ */
+
+/*
+		o_width
+	---------------------
+	|    width(cropped) |
+	|	-----	    |
+	|offs_h |   |	    |
+	|	-----	    |
+	|		    |
+	---------------------
+ */
+struct flite_frame {
+	u32 o_width;
+	u32 o_height;
+	u32 width;
+	u32 height;
+	u32 offs_h;
+	u32 offs_v;
+	unsigned long payload;
+	struct flite_addr addr;
+	struct flite_fmt *fmt;
+	bool cacheable;
+};
+
+struct flite_pipeline {
+	struct media_pipeline *pipe;
+	struct v4l2_subdev *flite;
+	struct v4l2_subdev *csis;
+	struct v4l2_subdev *sensor;
+};
+
+struct flite_sensor_info {
+	struct exynos_isp_info *pdata;
+	struct v4l2_subdev *sd;
+	struct clk *camclk;
+};
+
+struct flite_ctrls {
+	struct v4l2_ctrl	*cacheable;
+};
+/**
+  * struct flite_dev - top structure of FIMC-Lite device
+  * @pdev :	pointer to the FIMC-Lite platform device
+  * @lock :	the mutex protecting this data structure
+  * @sd :	subdevice pointer of FIMC-Lite
+  * @fmt :	Media bus format of FIMC-Lite
+  * @regs_res :	ioremapped regs of FIMC-Lite
+  * @regs :	SFR of FIMC-Lite
+  */
+struct flite_dev {
+	struct platform_device		*pdev;
+	struct exynos_platform_flite	*pdata; /* depended on isp */
+	spinlock_t			slock;
+	struct v4l2_subdev		*sd_flite;
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+	struct exynos_md		*mdev;
+	struct v4l2_subdev		*sd_csis;
+	struct flite_sensor_info	sensor[SENSOR_MAX_ENTITIES];
+	struct media_pad		pads[FLITE_PADS_NUM];
+	struct media_pad		vd_pad;
+	struct flite_frame		d_frame;
+	struct mutex			lock;
+	struct video_device		*vfd;
+	int				refcnt;
+	u32				reqbufs_cnt;
+	struct vb2_queue		vbq;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	const struct flite_vb2		*vb2;
+	struct flite_pipeline		pipeline;
+	struct v4l2_ctrl_handler	ctrl_handler;
+	struct flite_ctrls		flite_ctrls;
+	bool				ctrls_rdy;
+	struct list_head		pending_buf_q;
+	struct list_head		active_buf_q;
+	int				active_buf_cnt;
+	int				pending_buf_cnt;
+	int				buf_index;
+	struct clk			*gsc_clk;
+	struct clk			*camif_clk;
+#endif
+	struct v4l2_mbus_framefmt	mbus_fmt;
+	struct flite_frame		s_frame;
+	struct resource			*regs_res;
+	void __iomem			*regs;
+	int				irq;
+	unsigned long			state;
+	u32				out_path;
+	wait_queue_head_t		irq_queue;
+	u32				id;
+	enum flite_input_entity		input;
+	enum flite_output_entity	output;
+};
+
+struct flite_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct flite_dev *flite);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+	void (*set_sharable)(void *alloc_ctx, bool sharable);
+};
+
+struct flite_buffer {
+	struct vb2_buffer	vb;
+	struct list_head	list;
+	struct flite_addr	paddr;
+	int			index;
+};
+/* fimc-reg.c */
+void flite_hw_set_cam_source_size(struct flite_dev *dev);
+void flite_hw_set_cam_channel(struct flite_dev *dev);
+void flite_hw_set_camera_type(struct flite_dev *dev, struct s3c_platform_camera *cam);
+int flite_hw_set_source_format(struct flite_dev *dev);
+void flite_hw_set_output_dma(struct flite_dev *dev, bool enable);
+void flite_hw_set_output_gscaler(struct flite_dev *dev, bool enable);
+void flite_hw_set_output_isp(struct flite_dev *dev, bool enable);
+void flite_hw_set_interrupt_source(struct flite_dev *dev, u32 source);
+void flite_hw_set_config_irq(struct flite_dev *dev, struct s3c_platform_camera *cam);
+void flite_hw_set_window_offset(struct flite_dev *dev);
+void flite_hw_set_capture_start(struct flite_dev *dev);
+void flite_hw_set_capture_stop(struct flite_dev *dev);
+void flite_hw_reset(struct flite_dev *dev);
+void flite_hw_set_last_capture_end_clear(struct flite_dev *dev);
+void flite_hw_set_inverse_polarity(struct flite_dev *dev);
+void flite_hw_set_sensor_type(struct flite_dev *dev);
+void flite_hw_set_out_order(struct flite_dev *dev);
+void flite_hw_set_output_size(struct flite_dev *dev);
+void flite_hw_set_dma_offset(struct flite_dev *dev);
+void flite_hw_set_framecnt_seq_masking(struct flite_dev *dev, u32 buf_cnt);
+void flite_hw_set_output_addr(struct flite_dev *dev, struct flite_addr *addr,
+							int index);
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct flite_vb2 flite_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct flite_vb2 flite_vb2_ion;
+#endif
+
+/* inline function for performance-sensitive region */
+static inline void flite_hw_clear_irq(struct flite_dev *dev)
+{
+	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);
+	cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM;
+	writel(cfg, dev->regs + FLITE_REG_CISTATUS);
+}
+
+static inline void flite_hw_get_int_src(struct flite_dev *dev, u32 *src)
+{
+	*src = readl(dev->regs + FLITE_REG_CISTATUS);
+	*src &= FLITE_REG_CISTATUS_IRQ_MASK;
+}
+
+static inline void user_to_drv(struct v4l2_ctrl *ctrl, s32 value)
+{
+	ctrl->cur.val = ctrl->val = value;
+}
+
+inline struct flite_fmt const *find_flite_format(struct v4l2_mbus_framefmt *mf);
+
+/*
+ * Add buf to the capture active buffers queue.
+ * Locking: Need to be called with fimc_dev::slock held.
+ */
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+static inline void active_queue_add(struct flite_dev *flite,
+				    struct flite_buffer *buf)
+{
+	list_add_tail(&buf->list, &flite->active_buf_q);
+	flite->active_buf_cnt++;
+}
+
+/*
+ * Pop a video buffer from the capture active buffers queue
+ * Locking: Need to be called with fimc_dev::slock held.
+ */
+static inline struct flite_buffer *active_queue_pop(struct flite_dev *flite)
+{
+	struct flite_buffer *buf;
+
+	buf = list_entry(flite->active_buf_q.next, struct flite_buffer, list);
+	list_del(&buf->list);
+	flite->active_buf_cnt--;
+
+	return buf;
+}
+
+/* Add video buffer to the capture pending buffers queue */
+static inline void pending_queue_add(struct flite_dev *flite,
+					  struct flite_buffer *buf)
+{
+	list_add_tail(&buf->list, &flite->pending_buf_q);
+	flite->pending_buf_cnt++;
+}
+
+/* Add video buffer to the capture pending buffers queue */
+static inline struct flite_buffer *pending_queue_pop(struct flite_dev *flite)
+{
+	struct flite_buffer *buf;
+
+	buf = list_entry(flite->pending_buf_q.next, struct flite_buffer, list);
+	list_del(&buf->list);
+	flite->pending_buf_cnt--;
+
+	return buf;
+}
+
+static inline void flite_lock(struct vb2_queue *vq)
+{
+	struct flite_dev *flite = vb2_get_drv_priv(vq);
+	mutex_lock(&flite->lock);
+}
+
+static inline void flite_unlock(struct vb2_queue *vq)
+{
+	struct flite_dev *flite = vb2_get_drv_priv(vq);
+	mutex_unlock(&flite->lock);
+}
+#endif
+#endif /* FLITE_CORE_H */
diff --git a/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.c b/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.c
new file mode 100644
index 0000000..e8bf87e
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.c
@@ -0,0 +1,423 @@
+/*
+ * Register interface file for Samsung Camera Interface (FIMC-Lite) driver
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <media/exynos_flite.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+
+#include "fimc-lite-core.h"
+
+static int reg_debug;
+module_param(reg_debug, int, 0644);
+MODULE_PARM_DESC(reg_debug, "Enable module debug trace. Set to 1 to enable.");
+
+void flite_hw_set_cam_source_size(struct flite_dev *dev)
+{
+	struct flite_frame *f_frame =  &dev->s_frame;
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
+
+	cfg |= FLITE_REG_CISRCSIZE_SIZE_H(f_frame->o_width);
+	cfg |= FLITE_REG_CISRCSIZE_SIZE_V(f_frame->o_height);
+
+	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
+}
+
+void flite_hw_set_cam_channel(struct flite_dev *dev)
+{
+	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);
+
+	cfg &= ~FLITE_REG_CIGENERAL0_MASK;
+	if (dev->id == 0)
+		cfg |= FLITE_REG_CIGENERAL0_CAM_A;
+	else if (dev->id == 1)
+		cfg |= FLITE_REG_CIGENERAL0_CAM_B;
+	else
+		cfg |= FLITE_REG_CIGENERAL0_CAM_C;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);
+}
+
+void flite_hw_reset(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+	unsigned long timeo = jiffies + FLITE_MAX_RESET_READY_TIME;
+
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+
+	do {
+		if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)
+			break;
+		usleep_range(1000, 5000);
+	} while (time_before(jiffies, timeo));
+
+	flite_dbg("wait time : %d ms",
+		jiffies_to_msecs(jiffies - timeo + FLITE_MAX_RESET_READY_TIME));
+
+	cfg |= FLITE_REG_CIGCTRL_SWRST;
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+/* Support only FreeRun mode
+ * If output DMA is supported, I will implement one shot mode
+ * with Cpt_FrCnt and Cpt_FrEn
+ */
+
+void flite_hw_set_capture_start(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
+	cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;
+
+	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
+}
+
+void flite_hw_set_capture_stop(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
+	cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;
+
+	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
+
+	if (soc_is_exynos4212() || soc_is_exynos4412())
+		clear_bit(FLITE_ST_STREAM, &dev->state);
+}
+
+int flite_hw_set_source_format(struct flite_dev *dev)
+{
+	struct v4l2_mbus_framefmt *mbus_fmt = &dev->mbus_fmt;
+	struct flite_fmt const *f_fmt = find_flite_format(mbus_fmt);
+	u32 cfg = 0;
+
+	if (!f_fmt) {
+		flite_err("f_fmt is null");
+		return -EINVAL;
+	}
+
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg |= f_fmt->fmt_reg;
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+
+	if (f_fmt->is_yuv) {
+		cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
+
+		switch (f_fmt->code) {
+		case V4L2_MBUS_FMT_YUYV8_2X8:
+			cfg |= FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR;
+			break;
+		case V4L2_MBUS_FMT_YVYU8_2X8:
+			cfg |= FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB;
+			break;
+		case V4L2_MBUS_FMT_UYVY8_2X8:
+			cfg |= FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY;
+			break;
+		case V4L2_MBUS_FMT_VYUY8_2X8:
+			cfg |= FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY;
+			break;
+		default:
+			flite_err("not supported mbus code");
+			return -EINVAL;
+		}
+		writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
+	}
+	return 0;
+}
+
+void flite_hw_set_shadow_mask(struct flite_dev *dev, bool enable)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (enable)
+		cfg &= ~FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE;
+	else
+		cfg |= FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_output_dma(struct flite_dev *dev, bool enable)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (enable)
+		cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE;
+	else
+		cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_output_gscaler(struct flite_dev *dev, bool enable)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (enable)
+		cfg &= ~FLITE_REG_CIGCTRL_OUT_GSCL_ENABLE;
+	else
+		cfg |= FLITE_REG_CIGCTRL_OUT_GSCL_ENABLE;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_output_isp(struct flite_dev *dev, bool enable)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (enable)
+		cfg &= ~FLITE_REG_CIGCTRL_OUT_LOCAL_ENABLE;
+	else
+		cfg |= FLITE_REG_CIGCTRL_OUT_LOCAL_ENABLE;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_test_pattern_enable(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_config_irq(struct flite_dev *dev, struct s3c_platform_camera *cam)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg &= ~(FLITE_REG_CIGCTRL_INVPOLPCLK | FLITE_REG_CIGCTRL_INVPOLVSYNC
+			| FLITE_REG_CIGCTRL_INVPOLHREF);
+
+	if (cam->inv_pclk)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;
+	if (cam->inv_vsync)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;
+	if (cam->inv_href)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_interrupt_source(struct flite_dev *dev, u32 source)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg |= source;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_camera_type(struct flite_dev *dev, struct s3c_platform_camera *cam)
+{
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (cam->type == CAM_TYPE_ITU)
+		cfg &= ~FLITE_REG_CIGCTRL_SELCAM_MIPI;
+	else
+		cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_window_offset(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+	u32 hoff2, voff2;
+	struct flite_frame *f_frame = &dev->s_frame;
+
+	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);
+	cfg &= ~(FLITE_REG_CIWDOFST_HOROFF_MASK |
+		FLITE_REG_CIWDOFST_VEROFF_MASK);
+	cfg |= FLITE_REG_CIWDOFST_WINOFSEN |
+		FLITE_REG_CIWDOFST_WINHOROFST(f_frame->offs_h) |
+		FLITE_REG_CIWDOFST_WINVEROFST(f_frame->offs_v);
+
+	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
+
+	hoff2 = f_frame->o_width - f_frame->width - f_frame->offs_h;
+	voff2 = f_frame->o_height - f_frame->height - f_frame->offs_v;
+	cfg = FLITE_REG_CIWDOFST2_WINHOROFST2(hoff2) |
+		FLITE_REG_CIWDOFST2_WINVEROFST2(voff2);
+
+	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
+}
+
+void flite_hw_set_last_capture_end_clear(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CISTATUS2);
+	cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;
+
+	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
+}
+
+#if defined(CONFIG_MEDIA_CONTROLLER) && defined(CONFIG_ARCH_EXYNOS5)
+void flite_hw_set_inverse_polarity(struct flite_dev *dev)
+{
+	struct v4l2_subdev *sd = dev->pipeline.sensor;
+	struct flite_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+	cfg &= ~(FLITE_REG_CIGCTRL_INVPOLPCLK | FLITE_REG_CIGCTRL_INVPOLVSYNC
+			| FLITE_REG_CIGCTRL_INVPOLHREF);
+
+	if (s_info->pdata->flags & CAM_CLK_INV_PCLK)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;
+	if (s_info->pdata->flags & CAM_CLK_INV_VSYNC)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;
+	if (s_info->pdata->flags & CAM_CLK_INV_HREF)
+		cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_set_sensor_type(struct flite_dev *dev)
+{
+	struct v4l2_subdev *sd = dev->pipeline.sensor;
+	struct flite_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
+	u32 cfg = 0;
+	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+
+	if (s_info->pdata->bus_type == CAM_TYPE_ITU)
+		cfg &= ~FLITE_REG_CIGCTRL_SELCAM_MIPI;
+	else
+		cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
+
+	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+
+}
+
+void flite_hw_set_dma_offset(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+	struct flite_frame *f_frame = &dev->d_frame;
+	cfg = readl(dev->regs + FLITE_REG_CIOOFF);
+	cfg |= FLITE_REG_CIOOFF_OOFF_H(f_frame->offs_h) |
+		FLITE_REG_CIOOFF_OOFF_V(f_frame->offs_v);
+
+	writel(cfg, dev->regs + FLITE_REG_CIOOFF);
+}
+
+void flite_hw_set_framecnt_seq(struct flite_dev *dev, u32 index, u32 enable)
+{
+	u32 cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
+	u32 mask = (1 << index);
+
+	cfg &= (~mask);
+	cfg |= (enable << index);
+
+	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
+}
+
+void flite_hw_set_framecnt_seq_masking(struct flite_dev *dev, u32 buf_cnt)
+{
+	u32 cfg = 0;
+	int mask = buf_cnt - 1;
+
+	do {
+		cfg |= (1 << mask);
+		mask--;
+	} while (mask >= 0);
+
+	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
+}
+
+int flite_hw_get_framecnt_before(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CISTATUS3);
+	cfg &= FLITE_REG_CISTATUS3_FRAMECNT_BEFORE;
+
+	return cfg >> 7;
+}
+
+int flite_hw_get_framecnt_present(struct flite_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CISTATUS3);
+	cfg &= FLITE_REG_CISTATUS3_FRAMECNT_BEFORE;
+
+	return cfg;
+}
+
+void flite_hw_set_output_addr(struct flite_dev *dev,
+			     struct flite_addr *addr, int index)
+{
+	flite_dbg("dst_buf[%d]: 0x%X", index, addr->y);
+
+	if (soc_is_exynos5250_rev1) {
+		writel(addr->y, dev->regs + FLITE_REG_CIOSA(index));
+	} else {
+		writel(addr->y, dev->regs + FLITE_REG_CIOSA(0));
+	}
+}
+
+void flite_hw_set_out_order(struct flite_dev *dev)
+{
+	struct flite_frame *frame = &dev->d_frame;
+	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
+	if (frame->fmt->is_yuv) {
+		switch (frame->fmt->code) {
+		case V4L2_MBUS_FMT_UYVY8_2X8:
+			cfg |= FLITE_REG_CIODMAFMT_CBYCRY;
+			break;
+		case V4L2_MBUS_FMT_VYUY8_2X8:
+			cfg |= FLITE_REG_CIODMAFMT_CRYCBY;
+			break;
+		case V4L2_MBUS_FMT_YUYV8_2X8:
+			cfg |= FLITE_REG_CIODMAFMT_YCBYCR;
+			break;
+		case V4L2_MBUS_FMT_YVYU8_2X8:
+			cfg |= FLITE_REG_CIODMAFMT_YCRYCB;
+			break;
+		default:
+			flite_err("not supported mbus_code");
+			break;
+
+		}
+	}
+	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);
+}
+
+void flite_hw_set_output_size(struct flite_dev *dev)
+{
+	struct flite_frame *f_frame =  &dev->d_frame;
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + FLITE_REG_CIOCAN);
+
+	cfg |= FLITE_REG_CIOCAN_OCAN_V(f_frame->o_height);
+	cfg |= FLITE_REG_CIOCAN_OCAN_H(f_frame->o_width);
+
+	writel(cfg, dev->regs + FLITE_REG_CIOCAN);
+}
+#else
+void flite_hw_set_inverse_polarity(struct flite_dev *dev) {}
+void flite_hw_set_sensor_type(struct flite_dev *dev) {}
+void flite_hw_set_dma_offset(struct flite_dev *dev) {}
+void flite_hw_set_output_addr(struct flite_dev *dev,
+			struct flite_addr *addr, int index) {}
+void flite_hw_set_out_order(struct flite_dev *dev) {}
+void flite_hw_set_output_size(struct flite_dev *dev) {}
+#endif
diff --git a/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.h b/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.h
new file mode 100644
index 0000000..59dde15
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/fimc-lite-reg.h
@@ -0,0 +1,156 @@
+/*
+ * Register interface file for Samsung Camera Interface (FIMC-Lite) driver
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef FIMC_LITE_REG_H_
+#define FIMC_LITE_REG_H_
+
+/* Camera Source size */
+#define FLITE_REG_CISRCSIZE				0x00
+#define FLITE_REG_CISRCSIZE_SIZE_H(x)			((x) << 16)
+#define FLITE_REG_CISRCSIZE_SIZE_V(x)			((x) << 0)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR		(0 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB		(1 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY		(2 << 14)
+#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY		(3 << 14)
+
+/* Global control */
+#define FLITE_REG_CIGCTRL				0x04
+#define FLITE_REG_CIGCTRL_OUT_GSCL_ENABLE		(1 << 30)
+#define FLITE_REG_CIGCTRL_YUV422_1P			(0x1E << 24)
+#define FLITE_REG_CIGCTRL_RAW8				(0x2A << 24)
+#define FLITE_REG_CIGCTRL_RAW10				(0x2B << 24)
+#define FLITE_REG_CIGCTRL_RAW12				(0x2C << 24)
+#define FLITE_REG_CIGCTRL_RAW14				(0x2D << 24)
+/* User defined formats. x = 0...0xF. */
+#define FLITE_REG_CIGCTRL_USER(x)			(0x30 + x - 1)
+#define FLITE_REG_CIGCTRL_OUT_LOCAL_ENABLE		(1 << 22)
+#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE		(1 << 21)
+#define FLITE_REG_CIGCTRL_ODMA_DISABLE			(1 << 20)
+#define FLITE_REG_CIGCTRL_SWRST_REQ			(1 << 19)
+#define FLITE_REG_CIGCTRL_SWRST_RDY			(1 << 18)
+#define FLITE_REG_CIGCTRL_SWRST				(1 << 17)
+#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR		(1 << 15)
+#define FLITE_REG_CIGCTRL_INVPOLPCLK			(1 << 14)
+#define FLITE_REG_CIGCTRL_INVPOLVSYNC			(1 << 13)
+#define FLITE_REG_CIGCTRL_INVPOLHREF			(1 << 12)
+#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE		(0 << 8)
+#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_DISABLE		(1 << 8)
+#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_ENABLE		(0 << 7)
+#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_DISABLE		(1 << 7)
+#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_ENABLE		(0 << 6)
+#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE		(1 << 6)
+#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_ENABLE		(0 << 5)
+#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_DISABLE		(1 << 5)
+#define FLITE_REG_CIGCTRL_SELCAM_MIPI			(1 << 3)
+
+/* Image Capture Enable */
+#define FLITE_REG_CIIMGCPT				0x08
+#define FLITE_REG_CIIMGCPT_IMGCPTEN			(1 << 31)
+#define FLITE_REG_CIIMGCPT_CPT_FREN			(1 << 25)
+#define FLITE_REG_CIIMGCPT_CPT_FRPTR(x)			((x) << 19)
+#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT		(1 << 18)
+#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN			(0 << 18)
+#define FLITE_REG_CIIMGCPT_CPT_FRCNT(x)			((x) << 10)
+
+/* Capture Sequence */
+#define FLITE_REG_CICPTSEQ				0x0C
+#define FLITE_REG_CPT_FRSEQ(x)				((x) << 0)
+
+/* Camera Window Offset */
+#define FLITE_REG_CIWDOFST				0x10
+#define FLITE_REG_CIWDOFST_WINOFSEN			(1 << 31)
+#define FLITE_REG_CIWDOFST_CLROVIY			(1 << 31)
+#define FLITE_REG_CIWDOFST_WINHOROFST(x)		((x) << 16)
+#define FLITE_REG_CIWDOFST_HOROFF_MASK			(0x1fff << 16)
+#define FLITE_REG_CIWDOFST_CLROVFICB			(1 << 15)
+#define FLITE_REG_CIWDOFST_CLROVFICR			(1 << 14)
+#define FLITE_REG_CIWDOFST_WINVEROFST(x)		((x) << 0)
+#define FLITE_REG_CIWDOFST_VEROFF_MASK			(0x1fff << 0)
+
+/* Cmaera Window Offset2 */
+#define FLITE_REG_CIWDOFST2				0x14
+#define FLITE_REG_CIWDOFST2_WINHOROFST2(x)		((x) << 16)
+#define FLITE_REG_CIWDOFST2_WINVEROFST2(x)		((x) << 0)
+
+/* Camera Output DMA Format */
+#define FLITE_REG_CIODMAFMT				0x18
+#define FLITE_REG_CIODMAFMT_1D_DMA			(1 << 15)
+#define FLITE_REG_CIODMAFMT_2D_DMA			(0 << 15)
+#define FLITE_REG_CIODMAFMT_PACK12			(1 << 14)
+#define FLITE_REG_CIODMAFMT_NORMAL			(0 << 14)
+#define FLITE_REG_CIODMAFMT_CRYCBY			(0 << 4)
+#define FLITE_REG_CIODMAFMT_CBYCRY			(1 << 4)
+#define FLITE_REG_CIODMAFMT_YCRYCB			(2 << 4)
+#define FLITE_REG_CIODMAFMT_YCBYCR			(3 << 4)
+
+/* Camera Output Canvas */
+#define FLITE_REG_CIOCAN				0x20
+#define FLITE_REG_CIOCAN_OCAN_V(x)			((x) << 16)
+#define FLITE_REG_CIOCAN_OCAN_H(x)			((x) << 0)
+
+/* Camera Output DMA Offset */
+#define FLITE_REG_CIOOFF				0x24
+#define FLITE_REG_CIOOFF_OOFF_V(x)			((x) << 16)
+#define FLITE_REG_CIOOFF_OOFF_H(x)			((x) << 0)
+
+/* Camera Status */
+#define FLITE_REG_CISTATUS				0x40
+#define FLITE_REG_CISTATUS_MIPI_VVALID			(1 << 22)
+#define FLITE_REG_CISTATUS_MIPI_HVALID			(1 << 21)
+#define FLITE_REG_CISTATUS_MIPI_DVALID			(1 << 20)
+#define FLITE_REG_CISTATUS_ITU_VSYNC			(1 << 14)
+#define FLITE_REG_CISTATUS_ITU_HREFF			(1 << 13)
+#define FLITE_REG_CISTATUS_OVFIY			(1 << 10)
+#define FLITE_REG_CISTATUS_OVFICB			(1 << 9)
+#define FLITE_REG_CISTATUS_OVFICR			(1 << 8)
+#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW		(1 << 7)
+#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND		(1 << 6)
+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART		(1 << 5)
+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND		(1 << 4)
+#define FLITE_REG_CISTATUS_IRQ_CAM			(1 << 0)
+#define FLITE_REG_CISTATUS_IRQ_MASK			(0xf << 4)
+
+/* Camera Status2 */
+#define FLITE_REG_CISTATUS2				0x44
+#define FLITE_REG_CISTATUS2_LASTCAPEND			(1 << 1)
+#define FLITE_REG_CISTATUS2_FRMEND			(1 << 0)
+
+/* Camera Status3 */
+#define FLITE_REG_CISTATUS3				0x48
+#define FLITE_REG_CISTATUS3_FRAMECNT_BEFORE		(0x3F << 7)
+#define FLITE_REG_CISTATUS3_FRAMECNT_PRESENT		(0x3F << 0)
+
+/* Camera Status4 */
+#define FLITE_REG_CISTATUS4				0x4C
+#define FLITE_REG_CISTATUS4_VSYNC_CNT			0x0
+/* Qos Threshold */
+#define FLITE_REG_CITHOLD				0xF0
+#define FLITE_REG_CITHOLD_W_QOS_EN			(1 << 30)
+#define FLITE_REG_CITHOLD_WTH_QOS(x)			((x) << 0)
+
+/* Camera General Purpose */
+#define FLITE_REG_CIGENERAL				0xFC
+#define FLITE_REG_CIGENERAL0_MASK			0x3
+#define FLITE_REG_CIGENERAL0_CAM_A			(0 << 0)
+#define FLITE_REG_CIGENERAL0_CAM_B			(1 << 0)
+#define FLITE_REG_CIGENERAL0_CAM_C			(2 << 0)
+
+/* Camera Frame Count Sequence */
+#define FLITE_REG_CIFCNTSEQ				0x100
+
+/* Version Info */
+#define FLITE_REG_CIVERINFO				0x104
+
+/* Camera Output DMA Address (0~31)*/
+#define FLITE_REG_CIOSA(n)				(n ? \
+							0x1FC + (n * 0x4) : \
+							0x30)
+
+#endif /* FIMC_LITE_REG_H */
diff --git a/drivers/media/video/exynos/fimc-lite/fimc-lite-vb2.c b/drivers/media/video/exynos/fimc-lite/fimc-lite-vb2.c
new file mode 100644
index 0000000..0051fbc
--- /dev/null
+++ b/drivers/media/video/exynos/fimc-lite/fimc-lite-vb2.c
@@ -0,0 +1,71 @@
+/* linux/drivers/media/video/exynos/flite-vb2.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Videobuf2 allocator operations file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include "fimc-lite-core.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *flite_cma_init(struct flite_dev *flite)
+{
+	return vb2_cma_phys_init(&flite->pdev->dev, NULL, 0, false);
+}
+
+int flite_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void flite_cma_suspend(void *alloc_ctx) {}
+void flite_cma_set_cacheable(void *alloc_ctx, bool cacheable) {}
+
+int flite_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct flite_vb2 flite_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= flite_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= flite_cma_resume,
+	.suspend	= flite_cma_suspend,
+	.cache_flush	= flite_cma_cache_flush,
+	.set_cacheable	= flite_cma_set_cacheable,
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *flite_ion_init(struct flite_dev *flite)
+{
+	return vb2_ion_create_context(&flite->pdev->dev, SZ_4K,
+		VB2ION_CTX_VMCONTIG | VB2ION_CTX_IOMMU | VB2ION_CTX_UNCACHED);
+}
+
+static unsigned long flite_vb2_plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+
+const struct flite_vb2 flite_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= flite_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= flite_vb2_plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+};
+#endif
diff --git a/drivers/media/video/exynos/gsc/Kconfig b/drivers/media/video/exynos/gsc/Kconfig
new file mode 100644
index 0000000..8d8b49d
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/Kconfig
@@ -0,0 +1,28 @@
+config VIDEO_EXYNOS_GSCALER
+	bool "Exynos G-Scaler driver"
+	depends on VIDEO_EXYNOS
+	select MEDIA_EXYNOS
+	select V4L2_MEM2MEM_DEV
+	default n
+	help
+	  This is a v4l2 driver for exynos G-Scaler device.
+
+if VIDEO_EXYNOS_GSCALER && VIDEOBUF2_CMA_PHYS
+comment "Reserved memory configurations"
+config VIDEO_SAMSUNG_MEMSIZE_GSC0
+	int "Memory size in kbytes for GSC0"
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_GSC1
+	int "Memory size in kbytes for GSC1"
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_GSC2
+	int "Memory size in kbytes for GSC2"
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_GSC3
+	int "Memory size in kbytes for GSC3"
+	default "5120"
+endif
+
diff --git a/drivers/media/video/exynos/gsc/Makefile b/drivers/media/video/exynos/gsc/Makefile
new file mode 100644
index 0000000..488ca2c
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/Makefile
@@ -0,0 +1,2 @@
+gsc-objs := gsc-core.o gsc-vb2.o gsc-m2m.o gsc-output.o gsc-capture.o gsc-regs.o coef.o
+obj-$(CONFIG_VIDEO_EXYNOS_GSCALER)	+= gsc.o
diff --git a/drivers/media/video/exynos/gsc/coef.c b/drivers/media/video/exynos/gsc/coef.c
new file mode 100644
index 0000000..9fb9137
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/coef.c
@@ -0,0 +1,275 @@
+/* linux/drivers/media/video/exynos/gsc/coef.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * G-scaler poly-phase filter coefficients
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/types.h>
+#include "gsc-core.h"
+
+/* 8-tap Filter Coefficient */
+const int h_coef_8t[7][16][8] = {
+	{	/* Ratio <= 65536 (~8:8) */
+		{  0,  0,   0, 128,   0,   0,  0,  0 },/* 0 */
+		{ -1,  2,  -6, 127,   7,  -2,  1,  0 },/* 1 */
+		{ -1,  4, -12, 125,  16,  -5,  1,  0 },/* 2 */
+		{ -1,  5, -15, 120,  25,  -8,  2,  0 },/* 3 */
+		{ -1,  6, -18, 114,  35, -10,  3, -1 },/* 4 */
+		{ -1,  6, -20, 107,  46, -13,  4, -1 },/* 5 */
+		{ -2,  7, -21,  99,  57, -16,  5, -1 },/* 6 */
+		{ -1,  6, -20,  89,  68, -18,  5, -1 },/* 7 */
+		{ -1,  6, -20,  79,  79, -20,  6, -1 },/* 8 */
+		{ -1,  5, -18,  68,  89, -20,  6, -1 },/* 9 */
+		{ -1,  5, -16,  57,  99, -21,  7, -2 },/* 10 */
+		{ -1,  4, -13,  46, 107, -20,  6, -1 },/* 11 */
+		{ -1,  3, -10,  35, 114, -18,  6, -1 },/* 12 */
+		{  0,  2,  -8,  25, 120, -15,  5, -1 },/* 13 */
+		{  0,  1,  -5,  16, 125, -12,  4, -1 },/* 14 */
+		{  0,  1,  -2,   7, 127,  -6,  2, -1 } /* 15 */
+	},
+	{	/* 65536 < Ratio <= 74898 (~8:7) */
+		{  3, -8,  14, 111,  13,  -8,  3,  0 },/* 0 */
+		{  2, -6,   7, 112,  21, -10,  3, -1 },/* 1 */
+		{  2, -4,   1, 110,  28, -12,  4, -1 },/* 2 */
+		{  1, -2,  -3, 106,  36, -13,  4, -1 },/* 3 */
+		{  1, -1,  -7, 103,  44, -15,  4, -1 },/* 4 */
+		{  1,  1, -11,  97,  53, -16,  4, -1 },/* 5 */
+		{  0,  2, -13,  91,  61, -16,  4, -1 },/* 6 */
+		{  0,  3, -15,  85,  69, -17,  4, -1 },/* 7 */
+		{  0,  3, -16,  77,  77, -16,  3,  0 },/* 8 */
+		{ -1,  4, -17,  69,  85, -15,  3,  0 },/* 9 */
+		{ -1,  4, -16,  61,  91, -13,  2,  0 },/* 10 */
+		{ -1,  4, -16,  53,  97, -11,  1,  1 },/* 11 */
+		{ -1,  4, -15,  44, 103,  -7, -1,  1 },/* 12 */
+		{ -1,  4, -13,  36, 106,  -3, -2,  1 },/* 13 */
+		{ -1,  4, -12,  28, 110,   1, -4,  2 },/* 14 */
+		{ -1,  3, -10,  21, 112,   7, -6,  2 } /* 15 */
+	},
+	{	/* 74898 < Ratio <= 87381 (~8:6) */
+		{ 2, -11,  25,  96, 25, -11,   2,  0 },/* 0 */
+		{ 2, -10,  19,  96, 31, -12,   2,  0 },/* 1 */
+		{ 2,  -9,  14,  94, 37, -12,   2,  0 },/* 2 */
+		{ 2,  -8,  10,  92, 43, -12,   1,  0 },/* 3 */
+		{ 2,  -7,   5,  90, 49, -12,   1,  0 },/* 4 */
+		{ 2,  -5,   1,  86, 55, -12,   0,  1 },/* 5 */
+		{ 2,  -4,  -2,  82, 61, -11,  -1,  1 },/* 6 */
+		{ 1,  -3,  -5,  77, 67,  -9,  -1,  1 },/* 7 */
+		{ 1,  -2,  -7,  72, 72,  -7,  -2,  1 },/* 8 */
+		{ 1,  -1,  -9,  67, 77,  -5,  -3,  1 },/* 9 */
+		{ 1,  -1, -11,  61, 82,  -2,  -4,  2 },/* 10 */
+		{ 1,   0, -12,  55, 86,   1,  -5,  2 },/* 11 */
+		{ 0,   1, -12,  49, 90,   5,  -7,  2 },/* 12 */
+		{ 0,   1, -12,  43, 92,  10,  -8,  2 },/* 13 */
+		{ 0,   2, -12,  37, 94,  14,  -9,  2 },/* 14 */
+		{ 0,   2, -12,  31, 96,  19, -10,  2 } /* 15 */
+	},
+	{	/* 87381 < Ratio <= 104857 (~8:5) */
+		{ -1,  -8, 33,  80, 33,  -8,  -1,  0 },/* 0 */
+		{ -1,  -8, 28,  80, 37,  -7,  -2,  1 },/* 1 */
+		{  0,  -8, 24,  79, 41,  -7,  -2,  1 },/* 2 */
+		{  0,  -8, 20,  78, 46,  -6,  -3,  1 },/* 3 */
+		{  0,  -8, 16,  76, 50,  -4,  -3,  1 },/* 4 */
+		{  0,  -7, 13,  74, 54,  -3,  -4,  1 },/* 5 */
+		{  1,  -7, 10,  71, 58,  -1,  -5,  1 },/* 6 */
+		{  1,  -6,  6,  68, 62,   1,  -5,  1 },/* 7 */
+		{  1,  -6,  4,  65, 65,   4,  -6,  1 },/* 8 */
+		{  1,  -5,  1,  62, 68,   6,  -6,  1 },/* 9 */
+		{  1,  -5, -1,  58, 71,  10,  -7,  1 },/* 10 */
+		{  1,  -4, -3,  54, 74,  13,  -7,  0 },/* 11 */
+		{  1,  -3, -4,  50, 76,  16,  -8,  0 },/* 12 */
+		{  1,  -3, -6,  46, 78,  20,  -8,  0 },/* 13 */
+		{  1,  -2, -7,  41, 79,  24,  -8,  0 },/* 14 */
+		{  1,  -2, -7,  37, 80,  28,  -8, -1 } /* 15 */
+	},
+	{	/* 104857 < Ratio <= 131072 (~8:4) */
+		{ -3,   0, 35,  64, 35,   0,  -3,  0 },/* 0 */
+		{ -3,  -1, 32,  64, 38,   1,  -3,  0 },/* 1 */
+		{ -2,  -2, 29,  63, 41,   2,  -3,  0 },/* 2 */
+		{ -2,  -3, 27,  63, 43,   4,  -4,  0 },/* 3 */
+		{ -2,  -3, 24,  61, 46,   6,  -4,  0 },/* 4 */
+		{ -2,  -3, 21,  60, 49,   7,  -4,  0 },/* 5 */
+		{ -1,  -4, 19,  59, 51,   9,  -4, -1 },/* 6 */
+		{ -1,  -4, 16,  57, 53,  12,  -4, -1 },/* 7 */
+		{ -1,  -4, 14,  55, 55,  14,  -4, -1 },/* 8 */
+		{ -1,  -4, 12,  53, 57,  16,  -4, -1 },/* 9 */
+		{ -1,  -4,  9,  51, 59,  19,  -4, -1 },/* 10 */
+		{  0,  -4,  7,  49, 60,  21,  -3, -2 },/* 11 */
+		{  0,  -4,  6,  46, 61,  24,  -3, -2 },/* 12 */
+		{  0,  -4,  4,  43, 63,  27,  -3, -2 },/* 13 */
+		{  0,  -3,  2,  41, 63,  29,  -2, -2 },/* 14 */
+		{  0,  -3,  1,  38, 64,  32,  -1, -3 } /* 15 */
+	},
+	{	/* 131072 < Ratio <= 174762 (~8:3) */
+		{ -1,   8, 33,  48, 33,   8,  -1,  0 },/* 0 */
+		{ -1,   7, 31,  49, 35,   9,  -1, -1 },/* 1 */
+		{ -1,   6, 30,  49, 36,  10,  -1, -1 },/* 2 */
+		{ -1,   5, 28,  48, 38,  12,  -1, -1 },/* 3 */
+		{ -1,   4, 26,  48, 39,  13,   0, -1 },/* 4 */
+		{ -1,   3, 24,  47, 41,  15,   0, -1 },/* 5 */
+		{ -1,   2, 23,  47, 42,  16,   0, -1 },/* 6 */
+		{ -1,   2, 21,  45, 43,  18,   1, -1 },/* 7 */
+		{ -1,   1, 19,  45, 45,  19,   1, -1 },/* 8 */
+		{ -1,   1, 18,  43, 45,  21,   2, -1 },/* 9 */
+		{ -1,   0, 16,  42, 47,  23,   2, -1 },/* 10 */
+		{ -1,   0, 15,  41, 47,  24,   3, -1 },/* 11 */
+		{ -1,   0, 13,  39, 48,  26,   4, -1 },/* 12 */
+		{ -1,  -1, 12,  38, 48,  28,   5, -1 },/* 13 */
+		{ -1,  -1, 10,  36, 49,  30,   6, -1 },/* 14 */
+		{ -1,  -1,  9,  35, 49,  31,   7, -1 } /* 15 */
+	},
+	{	/* 174762 < Ratio <= 262144 (~8:2) */
+		{  2,  13, 30,  38, 30,  13,   2,  0 },/* 0 */
+		{  2,  12, 29,  38, 30,  14,   3,  0 },/* 1 */
+		{  2,  11, 28,  38, 31,  15,   3,  0 },/* 2 */
+		{  2,  10, 26,  38, 32,  16,   4,  0 },/* 3 */
+		{  1,  10, 26,  37, 33,  17,   4,  0 },/* 4 */
+		{  1,   9, 24,  37, 34,  18,   5,  0 },/* 5 */
+		{  1,   8, 24,  37, 34,  19,   5,  0 },/* 6 */
+		{  1,   7, 22,  36, 35,  20,   6,  1 },/* 7 */
+		{  1,   6, 21,  36, 36,  21,   6,  1 },/* 8 */
+		{  1,   6, 20,  35, 36,  22,   7,  1 },/* 9 */
+		{  0,   5, 19,  34, 37,  24,   8,  1 },/* 10 */
+		{  0,   5, 18,  34, 37,  24,   9,  1 },/* 11 */
+		{  0,   4, 17,  33, 37,  26,  10,  1 },/* 12 */
+		{  0,   4, 16,  32, 38,  26,  10,  2 },/* 13 */
+		{  0,   3, 15,  31, 38,  28,  11,  2 },/* 14 */
+		{  0,   3, 14,  30, 38,  29,  12,  2 } /* 15 */
+	}
+};
+
+/* 4-tap Filter Coefficient */
+const int v_coef_4t[7][16][4] = {
+	{	/* Ratio <= 65536 (~8:8) */
+		{  0, 128,   0,  0 },/* 0 */
+		{ -4, 127,   5,  0 },/* 1 */
+		{ -6, 124,  11, -1 },/* 2 */
+		{ -8, 118,  19, -1 },/* 3 */
+		{ -8, 111,  27, -2 },/* 4 */
+		{ -8, 102,  37, -3 },/* 5 */
+		{ -8,  92,  48, -4 },/* 6 */
+		{ -7,  81,  59, -5 },/* 7 */
+		{ -6,  70,  70, -6 },/* 8 */
+		{ -5,  59,  81, -7 },/* 9 */
+		{ -4,  48,  92, -8 },/* 10 */
+		{ -3,  37, 102, -8 },/* 11 */
+		{ -2,  27, 111, -8 },/* 12 */
+		{ -1,  19, 118, -8 },/* 13 */
+		{ -1,  11, 124, -6 },/* 14 */
+		{  0,   5, 127, -4 } /* 15 */
+	},
+	{	/* 65536 < Ratio <= 74898 (~8:7) */
+		{  8, 112,   8,  0 },/* 0 */
+		{  4, 111,  14, -1 },/* 1 */
+		{  1, 109,  20, -2 },/* 2 */
+		{ -2, 105,  27, -2 },/* 3 */
+		{ -3, 100,  34, -3 },/* 4 */
+		{ -5,  93,  43, -3 },/* 5 */
+		{ -5,  86,  51, -4 },/* 6 */
+		{ -5,  77,  60, -4 },/* 7 */
+		{ -5,  69,  69, -5 },/* 8 */
+		{ -4,  60,  77, -5 },/* 9 */
+		{ -4,  51,  86, -5 },/* 10 */
+		{ -3,  43,  93, -5 },/* 11 */
+		{ -3,  34, 100, -3 },/* 12 */
+		{ -2,  27, 105, -2 },/* 13 */
+		{ -2,  20, 109,  1 },/* 14 */
+		{ -1,  14, 111,  4 } /* 15 */
+	},
+	{	/* 74898 < Ratio <= 87381 (~8:6) */
+		{ 16,  96,  16,  0 },/* 0 */
+		{ 12,  97,  21, -2 },/* 1 */
+		{  8,  96,  26, -2 },/* 2 */
+		{  5,  93,  32, -2 },/* 3 */
+		{  2,  89,  39, -2 },/* 4 */
+		{  0,  84,  46, -2 },/* 5 */
+		{ -1,  79,  53, -3 },/* 6 */
+		{ -2,  73,  59, -2 },/* 7 */
+		{ -2,  66,  66, -2 },/* 8 */
+		{ -2,  59,  73, -2 },/* 9 */
+		{ -3,  53,  79, -1 },/* 10 */
+		{ -2,  46,  84,  0 },/* 11 */
+		{ -2,  39,  89,  2 },/* 12 */
+		{ -2,  32,  93,  5 },/* 13 */
+		{ -2,  26,  96,  8 },/* 14 */
+		{ -2,  21,  97, 12 } /* 15 */
+	},
+	{	/* 87381 < Ratio <= 104857 (~8:5) */
+		{ 22,  84,  22,  0 },/* 0 */
+		{ 18,  85,  26, -1 },/* 1 */
+		{ 14,  84,  31, -1 },/* 2 */
+		{ 11,  82,  36, -1 },/* 3 */
+		{  8,  79,  42, -1 },/* 4 */
+		{  6,  76,  47, -1 },/* 5 */
+		{  4,  72,  52,  0 },/* 6 */
+		{  2,  68,  58,  0 },/* 7 */
+		{  1,  63,  63,  1 },/* 8 */
+		{  0,  58,  68,  2 },/* 9 */
+		{  0,  52,  72,  4 },/* 10 */
+		{ -1,  47,  76,  6 },/* 11 */
+		{ -1,  42,  79,  8 },/* 12 */
+		{ -1,  36,  82, 11 },/* 13 */
+		{ -1,  31,  84, 14 },/* 14 */
+		{ -1,  26,  85, 18 } /* 15 */
+	},
+	{	/* 104857 < Ratio <= 131072 (~8:4) */
+		{ 26,  76,  26,  0 },/* 0 */
+		{ 22,  76,  30,  0 },/* 1 */
+		{ 19,  75,  34,  0 },/* 2 */
+		{ 16,  73,  38,  1 },/* 3 */
+		{ 13,  71,  43,  1 },/* 4 */
+		{ 10,  69,  47,  2 },/* 5 */
+		{  8,  66,  51,  3 },/* 6 */
+		{  6,  63,  55,  4 },/* 7 */
+		{  5,  59,  59,  5 },/* 8 */
+		{  4,  55,  63,  6 },/* 9 */
+		{  3,  51,  66,  8 },/* 10 */
+		{  2,  47,  69, 10 },/* 11 */
+		{  1,  43,  71, 13 },/* 12 */
+		{  1,  38,  73, 16 },/* 13 */
+		{  0,  34,  75, 19 },/* 14 */
+		{  0,  30,  76, 22 } /* 15 */
+	},
+	{	/* 131072 < Ratio <= 174762 (~8:3) */
+		{ 29,  70,  29,  0 },/* 0 */
+		{ 26,  68,  32,  2 },/* 1 */
+		{ 23,  67,  36,  2 },/* 2 */
+		{ 20,  66,  39,  3 },/* 3 */
+		{ 17,  65,  43,  3 },/* 4 */
+		{ 15,  63,  46,  4 },/* 5 */
+		{ 12,  61,  50,  5 },/* 6 */
+		{ 10,  58,  53,  7 },/* 7 */
+		{  8,  56,  56,  8 },/* 8 */
+		{  7,  53,  58, 10 },/* 9 */
+		{  5,  50,  61, 12 },/* 10 */
+		{  4,  46,  63, 15 },/* 11 */
+		{  3,  43,  65, 17 },/* 12 */
+		{  3,  39,  66, 20 },/* 13 */
+		{  2,  36,  67, 23 },/* 14 */
+		{  2,  32,  68, 26 } /* 15 */
+	},
+	{	/* 174762 < Ratio <= 262144 (~8:2) */
+		{ 32,  64,  32,  0 },/* 0 */
+		{ 28,  63,  34,  3 },/* 1 */
+		{ 25,  62,  37,  4 },/* 2 */
+		{ 22,  62,  40,  4 },/* 3 */
+		{ 19,  61,  43,  5 },/* 4 */
+		{ 17,  59,  46,  6 },/* 5 */
+		{ 15,  58,  48,  7 },/* 6 */
+		{ 13,  55,  51,  9 },/* 7 */
+		{ 11,  53,  53, 11 },/* 8 */
+		{  9,  51,  55, 13 },/* 9 */
+		{  7,  48,  58, 15 },/* 10 */
+		{  6,  46,  59, 17 },/* 11 */
+		{  5,  43,  61, 19 },/* 12 */
+		{  4,  40,  62, 22 },/* 13 */
+		{  4,  37,  62, 25 },/* 14 */
+		{  3,  34,  63, 28 } /* 15 */
+	}
+};
diff --git a/drivers/media/video/exynos/gsc/gsc-capture.c b/drivers/media/video/exynos/gsc/gsc-capture.c
new file mode 100644
index 0000000..5e1eb2b
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-capture.c
@@ -0,0 +1,1653 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-capture.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series G-scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/i2c.h>
+#include <media/v4l2-ioctl.h>
+#include <media/exynos_gscaler.h>
+
+#include "gsc-core.h"
+
+static int gsc_capture_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+		       unsigned int *num_planes, unsigned long sizes[],
+		       void *allocators[])
+{
+	struct gsc_ctx *ctx = vq->drv_priv;
+	struct gsc_fmt *fmt = ctx->d_frame.fmt;
+	int i;
+
+	if (!fmt)
+		return -EINVAL;
+
+	*num_planes = fmt->num_planes;
+
+	for (i = 0; i < fmt->num_planes; i++) {
+		sizes[i] = get_plane_size(&ctx->d_frame, i);
+		allocators[i] = ctx->gsc_dev->alloc_ctx;
+	}
+	vb2_queue_init(vq);
+
+	return 0;
+}
+static int gsc_capture_buf_prepare(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct gsc_ctx *ctx = vq->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	int i;
+
+	if (frame->fmt == NULL)
+		return -EINVAL;
+
+	for (i = 0; i < frame->fmt->num_planes; i++) {
+		unsigned long size = frame->payload[i];
+
+		if (vb2_plane_size(vb, i) < size) {
+			v4l2_err(ctx->gsc_dev->cap.vfd,
+				 "User buffer too small (%ld < %ld)\n",
+				 vb2_plane_size(vb, i), size);
+			return -EINVAL;
+		}
+		vb2_set_plane_payload(vb, i, size);
+	}
+
+	if (frame->cacheable)
+		gsc->vb2->cache_flush(vb, frame->fmt->num_planes);
+
+	return 0;
+}
+
+int gsc_cap_pipeline_s_stream(struct gsc_dev *gsc, int on)
+{
+	struct gsc_pipeline *p = &gsc->pipeline;
+	int ret = 0;
+
+	if ((!p->sensor || !p->flite) && (!p->disp))
+		return -ENODEV;
+
+	if (on) {
+		gsc_info("start stream");
+		ret = v4l2_subdev_call(p->sd_gsc, video, s_stream, 1);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+		if (p->disp) {
+			ret = v4l2_subdev_call(p->disp, video, s_stream, 1);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+		} else {
+			ret = v4l2_subdev_call(p->flite, video, s_stream, 1);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+			ret = v4l2_subdev_call(p->csis, video, s_stream, 1);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+			ret = v4l2_subdev_call(p->sensor, video, s_stream, 1);
+		}
+	} else {
+		gsc_info("stop stream");
+		if (p->disp) {
+			ret = v4l2_subdev_call(p->disp, video, s_stream, 0);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+		} else {
+			ret = v4l2_subdev_call(p->sensor, video, s_stream, 0);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+			ret = v4l2_subdev_call(p->csis, video, s_stream, 0);
+			if (ret < 0 && ret != -ENOIOCTLCMD)
+				return ret;
+			ret = v4l2_subdev_call(p->flite, video, s_stream, 0);
+		}
+
+		ret = v4l2_subdev_call(p->sd_gsc, video, s_stream, 0);
+		if (ret < 0 && ret != -ENOIOCTLCMD)
+			return ret;
+	}
+
+	return ret == -ENOIOCTLCMD ? 0 : ret;
+}
+
+static int gsc_capture_set_addr(struct vb2_buffer *vb)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret;
+
+	ret = gsc_prepare_addr(ctx, vb, &ctx->d_frame, &ctx->d_frame.addr);
+	if (ret) {
+		gsc_err("Prepare G-Scaler address failed\n");
+		return -EINVAL;
+	}
+
+	gsc_hw_set_output_addr(gsc, &ctx->d_frame.addr, vb->v4l2_buf.index);
+
+	return 0;
+}
+
+static void gsc_capture_buf_queue(struct vb2_buffer *vb)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_capture_device *cap = &gsc->cap;
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	int min_bufs, ret;
+	unsigned long flags;
+
+	spin_lock_irqsave(&gsc->slock, flags);
+	ret = gsc_capture_set_addr(vb);
+	if (ret)
+		gsc_err("Failed to prepare output addr");
+
+	gsc_hw_set_output_buf_masking(gsc, vb->v4l2_buf.index, 0);
+
+	min_bufs = cap->reqbufs_cnt > 1 ? 2 : 1;
+
+	if (vb2_is_streaming(&cap->vbq) &&
+		(gsc_hw_get_nr_unmask_bits(gsc) >= min_bufs) &&
+		!test_bit(ST_CAPT_STREAM, &gsc->state)) {
+		if (!test_and_set_bit(ST_CAPT_PIPE_STREAM, &gsc->state)) {
+			spin_unlock_irqrestore(&gsc->slock, flags);
+			if (!mdev->is_flite_on)
+				gsc_cap_pipeline_s_stream(gsc, 1);
+			else
+				v4l2_subdev_call(gsc->cap.sd_cap, video,
+							s_stream, 1);
+			return;
+		}
+
+		if (!test_bit(ST_CAPT_STREAM, &gsc->state)) {
+			gsc_info("G-Scaler h/w enable control");
+			gsc_hw_enable_control(gsc, true);
+			set_bit(ST_CAPT_STREAM, &gsc->state);
+		}
+	}
+	spin_unlock_irqrestore(&gsc->slock, flags);
+
+	return;
+}
+
+static int gsc_capture_get_scaler_factor(u32 src, u32 tar, u32 *ratio)
+{
+	u32 sh = 3;
+	tar *= 4;
+	if (tar >= src) {
+		*ratio = 1;
+		return 0;
+	}
+
+	while (--sh) {
+		u32 tmp = 1 << sh;
+		if (src >= tar * tmp)
+			*ratio = sh;
+	}
+	return 0;
+}
+
+static int gsc_capture_scaler_info(struct gsc_ctx *ctx)
+{
+	struct gsc_frame *s_frame = &ctx->s_frame;
+	struct gsc_frame *d_frame = &ctx->d_frame;
+	struct gsc_scaler *sc = &ctx->scaler;
+
+	gsc_capture_get_scaler_factor(s_frame->crop.width, d_frame->crop.width,
+				      &sc->pre_hratio);
+	gsc_capture_get_scaler_factor(s_frame->crop.height, d_frame->crop.width,
+				      &sc->pre_vratio);
+
+	sc->main_hratio = (s_frame->crop.width << 16) / d_frame->crop.width;
+	sc->main_vratio = (s_frame->crop.height << 16) / d_frame->crop.height;
+
+	gsc_info("src width : %d, src height : %d, dst width : %d,\
+		dst height : %d", s_frame->crop.width, s_frame->crop.height,\
+		d_frame->crop.width, d_frame->crop.height);
+	gsc_info("pre_hratio : 0x%x, pre_vratio : 0x%x, main_hratio : 0x%lx,\
+			main_vratio : 0x%lx", sc->pre_hratio,\
+			sc->pre_vratio, sc->main_hratio, sc->main_vratio);
+
+	return 0;
+}
+
+static int gsc_capture_subdev_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct gsc_capture_device *cap = &gsc->cap;
+	struct gsc_ctx *ctx = cap->ctx;
+
+	if (enable) {
+		gsc_info("start");
+		gsc_hw_set_frm_done_irq_mask(gsc, false);
+		gsc_hw_set_overflow_irq_mask(gsc, false);
+		gsc_hw_set_one_frm_mode(gsc, false);
+		gsc_hw_set_gsc_irq_enable(gsc, true);
+
+		if (gsc->pipeline.disp)
+			gsc_hw_set_sysreg_writeback(ctx);
+		else
+			gsc_hw_set_pxlasync_camif_lo_mask(gsc, true);
+
+		gsc_hw_set_input_path(ctx);
+		gsc_hw_set_in_size(ctx);
+		gsc_hw_set_in_image_format(ctx);
+		gsc_hw_set_output_path(ctx);
+		gsc_hw_set_out_size(ctx);
+		gsc_hw_set_out_image_format(ctx);
+		gsc_hw_set_global_alpha(ctx);
+
+		gsc_capture_scaler_info(ctx);
+		gsc_hw_set_prescaler(ctx);
+		gsc_hw_set_mainscaler(ctx);
+		gsc_hw_set_h_coef(ctx);
+		gsc_hw_set_v_coef(ctx);
+
+		set_bit(ST_CAPT_PEND, &gsc->state);
+
+		gsc_hw_enable_control(gsc, true);
+		set_bit(ST_CAPT_STREAM, &gsc->state);
+	} else {
+		gsc_info("stop");
+	}
+
+	return 0;
+}
+
+static int gsc_capture_start_streaming(struct vb2_queue *q)
+{
+	struct gsc_ctx *ctx = q->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_capture_device *cap = &gsc->cap;
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	int min_bufs;
+
+	gsc_hw_set_sw_reset(gsc);
+	gsc_wait_reset(gsc);
+	gsc_hw_set_output_buf_mask_all(gsc);
+
+	min_bufs = cap->reqbufs_cnt > 1 ? 2 : 1;
+	if ((gsc_hw_get_nr_unmask_bits(gsc) >= min_bufs) &&
+		!test_bit(ST_CAPT_STREAM, &gsc->state)) {
+		if (!test_and_set_bit(ST_CAPT_PIPE_STREAM, &gsc->state)) {
+			gsc_info("");
+			if (!mdev->is_flite_on)
+				gsc_cap_pipeline_s_stream(gsc, 1);
+			else
+				v4l2_subdev_call(gsc->cap.sd_cap, video,
+							s_stream, 1);
+		}
+	}
+
+	return 0;
+}
+
+static int gsc_capture_state_cleanup(struct gsc_dev *gsc)
+{
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	unsigned long flags;
+	bool streaming;
+
+	spin_lock_irqsave(&gsc->slock, flags);
+	streaming = gsc->state & (1 << ST_CAPT_PIPE_STREAM);
+
+	gsc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_STREAM |
+			1 << ST_CAPT_PIPE_STREAM | 1 << ST_CAPT_PEND);
+
+	spin_unlock_irqrestore(&gsc->slock, flags);
+
+	if (streaming) {
+		if (!mdev->is_flite_on)
+			return gsc_cap_pipeline_s_stream(gsc, 0);
+		else
+			return v4l2_subdev_call(gsc->cap.sd_cap, video,
+							s_stream, 0);
+	} else {
+		return 0;
+	}
+}
+
+static int gsc_cap_stop_capture(struct gsc_dev *gsc)
+{
+	int ret;
+	if (!gsc_cap_active(gsc)) {
+		gsc_warn("already stopped\n");
+		return 0;
+	}
+	gsc_info("G-Scaler h/w disable control");
+	gsc_hw_enable_control(gsc, false);
+	clear_bit(ST_CAPT_STREAM, &gsc->state);
+	ret = gsc_wait_stop(gsc);
+	if (ret) {
+		gsc_err("GSCALER_OP_STATUS is operating\n");
+		return ret;
+	}
+
+	return gsc_capture_state_cleanup(gsc);
+}
+
+static int gsc_capture_stop_streaming(struct vb2_queue *q)
+{
+	struct gsc_ctx *ctx = q->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+
+	if (!gsc_cap_active(gsc))
+		return -EINVAL;
+
+	return gsc_cap_stop_capture(gsc);
+}
+
+static struct vb2_ops gsc_capture_qops = {
+	.queue_setup		= gsc_capture_queue_setup,
+	.buf_prepare		= gsc_capture_buf_prepare,
+	.buf_queue		= gsc_capture_buf_queue,
+	.wait_prepare		= gsc_unlock,
+	.wait_finish		= gsc_lock,
+	.start_streaming	= gsc_capture_start_streaming,
+	.stop_streaming		= gsc_capture_stop_streaming,
+};
+
+/*
+ * The video node ioctl operations
+ */
+static int gsc_vidioc_querycap_capture(struct file *file, void *priv,
+				       struct v4l2_capability *cap)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	strncpy(cap->driver, gsc->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, gsc->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+
+	return 0;
+}
+
+static int gsc_capture_enum_fmt_mplane(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	return gsc_enum_fmt_mplane(f);
+}
+
+static int gsc_capture_try_fmt_mplane(struct file *file, void *fh,
+				   struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	return gsc_try_fmt_mplane(gsc->cap.ctx, f);
+}
+
+static int gsc_capture_s_fmt_mplane(struct file *file, void *fh,
+				 struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	struct gsc_frame *frame;
+	struct v4l2_pix_format_mplane *pix;
+	int i, ret = 0;
+
+	ret = gsc_capture_try_fmt_mplane(file, fh, f);
+	if (ret)
+		return ret;
+
+	if (vb2_is_streaming(&gsc->cap.vbq)) {
+		gsc_err("queue (%d) busy", f->type);
+		return -EBUSY;
+	}
+
+	frame = &ctx->d_frame;
+
+	pix = &f->fmt.pix_mp;
+	frame->fmt = find_format(&pix->pixelformat, NULL, 0);
+	if (!frame->fmt)
+		return -EINVAL;
+
+	for (i = 0; i < frame->fmt->nr_comp; i++)
+		frame->payload[i] =
+			pix->plane_fmt[i].bytesperline * pix->height;
+
+	gsc_set_frame_size(frame, pix->width, pix->height);
+
+	gsc_info("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
+
+	return 0;
+}
+
+static int gsc_capture_g_fmt_mplane(struct file *file, void *fh,
+				 struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	return gsc_g_fmt_mplane(ctx, f);
+}
+
+static int gsc_capture_reqbufs(struct file *file, void *priv,
+			    struct v4l2_requestbuffers *reqbufs)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_capture_device *cap = &gsc->cap;
+	struct gsc_frame *frame;
+	int ret;
+
+	frame = ctx_get_frame(cap->ctx, reqbufs->type);
+	frame->cacheable = cap->ctx->gsc_ctrls.cacheable->val;
+	gsc->vb2->set_cacheable(gsc->alloc_ctx, frame->cacheable);
+
+	ret = vb2_reqbufs(&cap->vbq, reqbufs);
+	if (!ret)
+		cap->reqbufs_cnt = reqbufs->count;
+
+	return ret;
+
+}
+
+static int gsc_capture_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_capture_device *cap = &gsc->cap;
+
+	return vb2_querybuf(&cap->vbq, buf);
+}
+
+static int gsc_capture_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_capture_device *cap = &gsc->cap;
+
+	return vb2_qbuf(&cap->vbq, buf);
+}
+
+static int gsc_capture_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	return vb2_dqbuf(&gsc->cap.vbq, buf,
+		file->f_flags & O_NONBLOCK);
+}
+
+static int gsc_capture_cropcap(struct file *file, void *fh,
+			    struct v4l2_cropcap *cr)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+
+	if (cr->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	cr->bounds.left		= 0;
+	cr->bounds.top		= 0;
+	cr->bounds.width	= ctx->d_frame.f_width;
+	cr->bounds.height	= ctx->d_frame.f_height;
+	cr->defrect		= cr->bounds;
+
+	return 0;
+}
+
+static int gsc_capture_enum_input(struct file *file, void *priv,
+			       struct v4l2_input *i)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct exynos_platform_gscaler *pdata = gsc->pdata;
+	struct exynos_isp_info *isp_info;
+
+	if (i->index >= MAX_CAMIF_CLIENTS)
+		return -EINVAL;
+
+	isp_info = pdata->isp_info[i->index];
+	if (isp_info == NULL)
+		return -EINVAL;
+
+	i->type = V4L2_INPUT_TYPE_CAMERA;
+
+	strncpy(i->name, isp_info->board_info->type, 32);
+
+	return 0;
+}
+
+static int gsc_capture_s_input(struct file *file, void *priv, unsigned int i)
+{
+	return i == 0 ? 0 : -EINVAL;
+}
+
+static int gsc_capture_g_input(struct file *file, void *priv, unsigned int *i)
+{
+	*i = 0;
+	return 0;
+}
+
+int gsc_capture_ctrls_create(struct gsc_dev *gsc)
+{
+	int ret;
+
+	if (WARN_ON(gsc->cap.ctx == NULL))
+		return -ENXIO;
+	if (gsc->cap.ctx->ctrls_rdy)
+		return 0;
+	ret = gsc_ctrls_create(gsc->cap.ctx);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void gsc_cap_pipeline_prepare(struct gsc_dev *gsc, struct media_entity *me)
+{
+	struct media_entity_graph graph;
+	struct v4l2_subdev *sd;
+
+	media_entity_graph_walk_start(&graph, me);
+
+	while ((me = media_entity_graph_walk_next(&graph))) {
+		gsc_info("me->name : %s", me->name);
+		if (media_entity_type(me) != MEDIA_ENT_T_V4L2_SUBDEV)
+			continue;
+		sd = media_entity_to_v4l2_subdev(me);
+
+		switch (sd->grp_id) {
+		case GSC_CAP_GRP_ID:
+			gsc->pipeline.sd_gsc = sd;
+			break;
+		case FLITE_GRP_ID:
+			gsc->pipeline.flite = sd;
+			break;
+		case SENSOR_GRP_ID:
+			gsc->pipeline.sensor = sd;
+			break;
+		case CSIS_GRP_ID:
+			gsc->pipeline.csis = sd;
+			break;
+		case FIMD_GRP_ID:
+			gsc->pipeline.disp = sd;
+			break;
+		default:
+			gsc_err("Unsupported group id");
+			break;
+		}
+	}
+
+	gsc_info("gsc->pipeline.sd_gsc : 0x%p", gsc->pipeline.sd_gsc);
+	gsc_info("gsc->pipeline.flite : 0x%p", gsc->pipeline.flite);
+	gsc_info("gsc->pipeline.sensor : 0x%p", gsc->pipeline.sensor);
+	gsc_info("gsc->pipeline.csis : 0x%p", gsc->pipeline.csis);
+	gsc_info("gsc->pipeline.disp : 0x%p", gsc->pipeline.disp);
+}
+
+static int __subdev_set_power(struct v4l2_subdev *sd, int on)
+{
+	int *use_count;
+	int ret;
+
+	if (sd == NULL)
+		return -ENXIO;
+
+	use_count = &sd->entity.use_count;
+	if (on && (*use_count)++ > 0)
+		return 0;
+	else if (!on && (*use_count == 0 || --(*use_count) > 0))
+		return 0;
+	ret = v4l2_subdev_call(sd, core, s_power, on);
+
+	return ret != -ENOIOCTLCMD ? ret : 0;
+}
+
+int gsc_cap_pipeline_s_power(struct gsc_dev *gsc, int state)
+{
+	int ret = 0;
+
+	if (!gsc->pipeline.sensor || !gsc->pipeline.flite)
+		return -ENXIO;
+
+	if (state) {
+		ret = __subdev_set_power(gsc->pipeline.flite, 1);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(gsc->pipeline.csis, 1);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(gsc->pipeline.sensor, 1);
+	} else {
+		ret = __subdev_set_power(gsc->pipeline.flite, 0);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(gsc->pipeline.sensor, 0);
+		if (ret && ret != -ENXIO)
+			return ret;
+		ret = __subdev_set_power(gsc->pipeline.csis, 0);
+	}
+	return ret == -ENXIO ? 0 : ret;
+}
+
+static void gsc_set_cam_clock(struct gsc_dev *gsc, bool on)
+{
+	struct v4l2_subdev *sd = NULL;
+	struct gsc_sensor_info *s_info = NULL;
+
+	if (gsc->pipeline.sensor) {
+		sd = gsc->pipeline.sensor;
+		s_info = v4l2_get_subdev_hostdata(sd);
+	}
+	if (on) {
+		clk_enable(gsc->clock);
+		if (gsc->pipeline.sensor)
+			clk_enable(s_info->camclk);
+	} else {
+		clk_disable(gsc->clock);
+		if (gsc->pipeline.sensor)
+			clk_disable(s_info->camclk);
+	}
+}
+
+static int __gsc_cap_pipeline_initialize(struct gsc_dev *gsc,
+					 struct media_entity *me, bool prep)
+{
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	int ret = 0;
+
+	if (prep) {
+		gsc_cap_pipeline_prepare(gsc, me);
+		if ((!gsc->pipeline.sensor || !gsc->pipeline.flite) &&
+				!gsc->pipeline.disp)
+			return -EINVAL;
+	}
+
+	gsc_set_cam_clock(gsc, true);
+
+	if (!mdev->is_flite_on && gsc->pipeline.sensor && gsc->pipeline.flite)
+		ret = gsc_cap_pipeline_s_power(gsc, 1);
+
+	return ret;
+}
+
+int gsc_cap_pipeline_initialize(struct gsc_dev *gsc, struct media_entity *me,
+				bool prep)
+{
+	int ret;
+
+	mutex_lock(&me->parent->graph_mutex);
+	ret =  __gsc_cap_pipeline_initialize(gsc, me, prep);
+	mutex_unlock(&me->parent->graph_mutex);
+
+	return ret;
+}
+static int gsc_capture_open(struct file *file)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	int ret = v4l2_fh_open(file);
+
+	if (ret)
+		return ret;
+
+	if (gsc_m2m_opened(gsc) || gsc_out_opened(gsc) || gsc_cap_opened(gsc)) {
+		v4l2_fh_release(file);
+		return -EBUSY;
+	}
+
+	set_bit(ST_CAPT_OPEN, &gsc->state);
+
+	pm_runtime_get_sync(&gsc->pdev->dev);
+
+	if (++gsc->cap.refcnt == 1) {
+		ret = gsc_cap_pipeline_initialize(gsc, &gsc->cap.vfd->entity, true);
+		if (ret < 0) {
+			gsc_err("gsc pipeline initialization failed\n");
+			goto err;
+		}
+
+		ret = gsc_capture_ctrls_create(gsc);
+		if (ret) {
+			gsc_err("failed to create controls\n");
+			goto err;
+		}
+	}
+
+	gsc_info("pid: %d, state: 0x%lx", task_pid_nr(current), gsc->state);
+
+	return 0;
+
+err:
+	pm_runtime_put_sync(&gsc->pdev->dev);
+	v4l2_fh_release(file);
+	clear_bit(ST_CAPT_OPEN, &gsc->state);
+	return ret;
+}
+
+int __gsc_cap_pipeline_shutdown(struct gsc_dev *gsc)
+{
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	int ret = 0;
+
+	if (!mdev->is_flite_on && gsc->pipeline.sensor && gsc->pipeline.flite)
+		ret = gsc_cap_pipeline_s_power(gsc, 0);
+
+	if (ret && ret != -ENXIO)
+		gsc_set_cam_clock(gsc, false);
+
+	gsc->pipeline.sd_gsc= NULL;
+	gsc->pipeline.disp= NULL;
+	gsc->pipeline.flite = NULL;
+	gsc->pipeline.csis = NULL;
+	gsc->pipeline.sensor = NULL;
+
+	return ret == -ENXIO ? 0 : ret;
+}
+
+int gsc_cap_pipeline_shutdown(struct gsc_dev *gsc)
+{
+	struct media_entity *me = &gsc->cap.vfd->entity;
+	int ret;
+
+	mutex_lock(&me->parent->graph_mutex);
+	ret = __gsc_cap_pipeline_shutdown(gsc);
+	mutex_unlock(&me->parent->graph_mutex);
+
+	return ret;
+}
+
+static int gsc_capture_close(struct file *file)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	gsc_info("pid: %d, state: 0x%lx", task_pid_nr(current), gsc->state);
+
+	if (--gsc->cap.refcnt == 0) {
+		clear_bit(ST_CAPT_OPEN, &gsc->state);
+		gsc_info("G-Scaler h/w disable control");
+		gsc_hw_enable_control(gsc, false);
+		clear_bit(ST_CAPT_STREAM, &gsc->state);
+		gsc_cap_pipeline_shutdown(gsc);
+	}
+
+	pm_runtime_put(&gsc->pdev->dev);
+
+	if (gsc->cap.refcnt == 0) {
+		vb2_queue_release(&gsc->cap.vbq);
+		gsc_ctrls_delete(gsc->cap.ctx);
+	}
+
+	return v4l2_fh_release(file);
+}
+
+static unsigned int gsc_capture_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_poll(&gsc->cap.vbq, file, wait);
+}
+
+static int gsc_capture_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_mmap(&gsc->cap.vbq, vma);
+}
+
+static int gsc_cap_link_validate(struct gsc_dev *gsc)
+{
+	struct gsc_capture_device *cap = &gsc->cap;
+	struct v4l2_subdev_format sink_fmt, src_fmt;
+	struct v4l2_subdev *sd;
+	struct media_pad *pad;
+	int ret;
+
+	/* Get the source pad connected with gsc-video */
+	pad =  media_entity_remote_source(&cap->vd_pad);
+	if (pad == NULL)
+		return -EPIPE;
+	/* Get the subdev of source pad */
+	sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	while (1) {
+		/* Find sink pad of the subdev*/
+		pad = &sd->entity.pads[0];
+		if (!(pad->flags & MEDIA_PAD_FL_SINK))
+			break;
+		if (sd == cap->sd_cap) {
+			struct gsc_frame *gf = &cap->ctx->s_frame;
+			sink_fmt.format.width = gf->crop.width;
+			sink_fmt.format.height = gf->crop.height;
+			sink_fmt.format.code = gf->fmt ? gf->fmt->mbus_code : 0;
+		} else {
+			sink_fmt.pad = pad->index;
+			sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+			ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
+			if (ret < 0 && ret != -ENOIOCTLCMD) {
+				gsc_err("failed %s subdev get_fmt", sd->name);
+				return -EPIPE;
+			}
+		}
+		gsc_info("sink sd name : %s", sd->name);
+		/* Get the source pad connected with remote sink pad */
+		pad = media_entity_remote_source(pad);
+		if (pad == NULL ||
+		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
+			break;
+
+		/* Get the subdev of source pad */
+		sd = media_entity_to_v4l2_subdev(pad->entity);
+		gsc_info("source sd name : %s", sd->name);
+
+		src_fmt.pad = pad->index;
+		src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+		ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
+		if (ret < 0 && ret != -ENOIOCTLCMD) {
+			gsc_err("failed %s subdev get_fmt", sd->name);
+			return -EPIPE;
+		}
+
+		gsc_info("src_width : %d, src_height : %d, src_code : %d",
+			src_fmt.format.width, src_fmt.format.height,
+			src_fmt.format.code);
+		gsc_info("sink_width : %d, sink_height : %d, sink_code : %d",
+			sink_fmt.format.width, sink_fmt.format.height,
+			sink_fmt.format.code);
+
+		if (src_fmt.format.width != sink_fmt.format.width ||
+		    src_fmt.format.height != sink_fmt.format.height ||
+		    src_fmt.format.code != sink_fmt.format.code) {
+			gsc_err("mismatch sink and source");
+			return -EPIPE;
+		}
+	}
+
+	return 0;
+}
+
+static int gsc_capture_streamon(struct file *file, void *priv,
+				enum v4l2_buf_type type)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_pipeline *p = &gsc->pipeline;
+	int ret;
+
+	if (gsc_cap_active(gsc))
+		return -EBUSY;
+
+	if (p->disp)
+		media_entity_pipeline_start(&p->disp->entity, p->pipe);
+	else if (p->sensor)
+		media_entity_pipeline_start(&p->sensor->entity, p->pipe);
+
+	ret = gsc_cap_link_validate(gsc);
+	if (ret)
+		return ret;
+
+	return vb2_streamon(&gsc->cap.vbq, type);
+}
+
+static int gsc_capture_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct v4l2_subdev *sd;
+	struct gsc_pipeline *p = &gsc->pipeline;
+	int ret;
+
+	if (p->disp) {
+		sd = gsc->pipeline.disp;
+	} else if (p->sensor) {
+		sd = gsc->pipeline.sensor;
+	} else {
+		gsc_err("Error pipeline");
+		return -EPIPE;
+	}
+
+	ret = vb2_streamoff(&gsc->cap.vbq, type);
+	if (ret == 0) {
+		if (p->disp)
+			media_entity_pipeline_stop(&p->disp->entity);
+		else if (p->sensor)
+			media_entity_pipeline_stop(&p->sensor->entity);
+	}
+
+	return ret;
+}
+
+static struct v4l2_subdev *gsc_cap_remote_subdev(struct gsc_dev *gsc, u32 *pad)
+{
+	struct media_pad *remote;
+
+	remote = media_entity_remote_source(&gsc->cap.vd_pad);
+
+	if (remote == NULL ||
+	    media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
+		return NULL;
+
+	if (pad)
+		*pad = remote->index;
+
+	return media_entity_to_v4l2_subdev(remote->entity);
+}
+
+static int gsc_capture_g_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct v4l2_subdev *subdev;
+	struct v4l2_subdev_crop subdev_crop;
+	int ret;
+
+	subdev = gsc_cap_remote_subdev(gsc, NULL);
+	if (subdev == NULL)
+		return -EINVAL;
+
+	/* Try the get crop operation first and fallback to get format if not
+	 * implemented.
+	 */
+	subdev_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+	subdev_crop.pad = GSC_PAD_SOURCE;
+	ret = v4l2_subdev_call(subdev, pad, get_crop, NULL, &subdev_crop);
+	if (ret < 0)
+		return ret == -ENOIOCTLCMD ? -EINVAL : ret;
+
+	crop->c.left = subdev_crop.rect.left;
+	crop->c.top = subdev_crop.rect.top;
+	crop->c.width = subdev_crop.rect.width;
+	crop->c.height = subdev_crop.rect.height;
+
+	return 0;
+}
+
+static int gsc_capture_s_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct v4l2_subdev *subdev;
+	struct v4l2_subdev_crop subdev_crop;
+	int ret;
+
+	subdev = gsc_cap_remote_subdev(gsc, NULL);
+	if (subdev == NULL)
+		return -EINVAL;
+
+	subdev_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+	subdev_crop.pad = GSC_PAD_SOURCE;
+	subdev_crop.rect.left = crop->c.left;
+	subdev_crop.rect.top = crop->c.top;
+	subdev_crop.rect.width = crop->c.width;
+	subdev_crop.rect.height = crop->c.height;
+
+	ret = v4l2_subdev_call(subdev, pad, set_crop, NULL, &subdev_crop);
+
+	return ret == -ENOIOCTLCMD ? -EINVAL : ret;
+}
+
+
+static const struct v4l2_ioctl_ops gsc_capture_ioctl_ops = {
+	.vidioc_querycap		= gsc_vidioc_querycap_capture,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= gsc_capture_enum_fmt_mplane,
+	.vidioc_try_fmt_vid_cap_mplane	= gsc_capture_try_fmt_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= gsc_capture_s_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= gsc_capture_g_fmt_mplane,
+
+	.vidioc_reqbufs			= gsc_capture_reqbufs,
+	.vidioc_querybuf		= gsc_capture_querybuf,
+
+	.vidioc_qbuf			= gsc_capture_qbuf,
+	.vidioc_dqbuf			= gsc_capture_dqbuf,
+
+	.vidioc_streamon		= gsc_capture_streamon,
+	.vidioc_streamoff		= gsc_capture_streamoff,
+
+	.vidioc_g_crop			= gsc_capture_g_crop,
+	.vidioc_s_crop			= gsc_capture_s_crop,
+	.vidioc_cropcap			= gsc_capture_cropcap,
+
+	.vidioc_enum_input		= gsc_capture_enum_input,
+	.vidioc_s_input			= gsc_capture_s_input,
+	.vidioc_g_input			= gsc_capture_g_input,
+};
+
+static const struct v4l2_file_operations gsc_capture_fops = {
+	.owner		= THIS_MODULE,
+	.open		= gsc_capture_open,
+	.release	= gsc_capture_close,
+	.poll		= gsc_capture_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= gsc_capture_mmap,
+};
+
+/*
+ * __gsc_cap_get_format - helper function for getting gscaler format
+ * @res   : pointer to resizer private structure
+ * @pad   : pad number
+ * @fh    : V4L2 subdev file handle
+ * @which : wanted subdev format
+ * return zero
+ */
+static struct v4l2_mbus_framefmt *__gsc_cap_get_format(struct gsc_dev *gsc,
+				struct v4l2_subdev_fh *fh, unsigned int pad,
+				enum v4l2_subdev_format_whence which)
+{
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return v4l2_subdev_get_try_format(fh, pad);
+	else
+		return &gsc->cap.mbus_fmt[pad];
+}
+static void gsc_cap_check_limit_size(struct gsc_dev *gsc, unsigned int pad,
+				   struct v4l2_mbus_framefmt *fmt)
+{
+	struct gsc_variant *variant = gsc->variant;
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	u32 min_w, min_h, max_w, max_h;
+
+	switch (pad) {
+	case GSC_PAD_SINK:
+		if (gsc_cap_opened(gsc) &&
+		    (ctx->gsc_ctrls.rotate->val == 90 ||
+		    ctx->gsc_ctrls.rotate->val == 270)) {
+			min_w = variant->pix_min->real_w;
+			min_h = variant->pix_min->real_h;
+			max_w = variant->pix_max->real_rot_en_w;
+			max_h = variant->pix_max->real_rot_en_h;
+		} else {
+			min_w = variant->pix_min->real_w;
+			min_h = variant->pix_min->real_h;
+			max_w = variant->pix_max->real_rot_dis_w;
+			max_h = variant->pix_max->real_rot_dis_h;
+		}
+		break;
+
+	case GSC_PAD_SOURCE:
+		min_w = variant->pix_min->target_rot_dis_w;
+		min_h = variant->pix_min->target_rot_dis_h;
+		max_w = variant->pix_max->target_rot_dis_w;
+		max_h = variant->pix_max->target_rot_dis_h;
+		break;
+	default:
+		gsc_err("unsupported pad");
+		return;
+	}
+
+	fmt->width = clamp_t(u32, fmt->width, min_w, max_w);
+	fmt->height = clamp_t(u32, fmt->height , min_h, max_h);
+}
+static void gsc_cap_try_format(struct gsc_dev *gsc,
+			       struct v4l2_subdev_fh *fh, unsigned int pad,
+			       struct v4l2_mbus_framefmt *fmt,
+			       enum v4l2_subdev_format_whence which)
+{
+	struct gsc_fmt *gfmt;
+
+	gfmt = find_format(NULL, &fmt->code, 0);
+	WARN_ON(!gfmt);
+
+	if (pad == GSC_PAD_SINK) {
+		struct gsc_ctx *ctx = gsc->cap.ctx;
+		struct gsc_frame *frame = &ctx->s_frame;
+
+		frame->fmt = gfmt;
+	}
+
+	gsc_cap_check_limit_size(gsc, pad, fmt);
+
+	fmt->colorspace = V4L2_COLORSPACE_JPEG;
+	fmt->field = V4L2_FIELD_NONE;
+}
+
+static int gsc_capture_subdev_set_fmt(struct v4l2_subdev *sd,
+				      struct v4l2_subdev_fh *fh,
+				      struct v4l2_subdev_format *fmt)
+{
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct v4l2_mbus_framefmt *mf;
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	struct gsc_frame *frame;
+
+	mf = __gsc_cap_get_format(gsc, fh, fmt->pad, fmt->which);
+	if (mf == NULL)
+		return -EINVAL;
+
+	gsc_cap_try_format(gsc, fh, fmt->pad, &fmt->format, fmt->which);
+	*mf = fmt->format;
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
+		return 0;
+
+	frame = gsc_capture_get_frame(ctx, fmt->pad);
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		frame->crop.left = 0;
+		frame->crop.top = 0;
+		frame->f_width = mf->width;
+		frame->f_height = mf->height;
+		frame->crop.width = mf->width;
+		frame->crop.height = mf->height;
+	}
+	gsc_dbg("offs_h : %d, offs_v : %d, f_width : %d, f_height :%d,\
+				width : %d, height : %d", frame->crop.left,\
+				frame->crop.top, frame->f_width,
+				frame->f_height,\
+				frame->crop.width, frame->crop.height);
+
+	return 0;
+}
+
+static int gsc_capture_subdev_get_fmt(struct v4l2_subdev *sd,
+				      struct v4l2_subdev_fh *fh,
+				      struct v4l2_subdev_format *fmt)
+{
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	mf = __gsc_cap_get_format(gsc, fh, fmt->pad, fmt->which);
+	if (mf == NULL)
+		return -EINVAL;
+
+	fmt->format = *mf;
+
+	return 0;
+}
+
+static int __gsc_cap_get_crop(struct gsc_dev *gsc, struct v4l2_subdev_fh *fh,
+			      unsigned int pad, enum v4l2_subdev_format_whence which,
+				struct v4l2_rect *crop)
+{
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	struct gsc_frame *frame = gsc_capture_get_frame(ctx, pad);
+
+	if (which == V4L2_SUBDEV_FORMAT_TRY) {
+		crop = v4l2_subdev_get_try_crop(fh, pad);
+	} else {
+		crop->left = frame->crop.left;
+		crop->top = frame->crop.top;
+		crop->width = frame->crop.width;
+		crop->height = frame->crop.height;
+	}
+
+	return 0;
+}
+
+static void gsc_cap_try_crop(struct gsc_dev *gsc, struct v4l2_rect *crop,
+				u32 pad)
+{
+	struct gsc_variant *variant = gsc->variant;
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	struct gsc_frame *frame = gsc_capture_get_frame(ctx, pad);
+
+	u32 crop_min_w = variant->pix_min->target_rot_dis_w;
+	u32 crop_min_h = variant->pix_min->target_rot_dis_h;
+	u32 crop_max_w = frame->f_width;
+	u32 crop_max_h = frame->f_height;
+
+	crop->left = clamp_t(u32, crop->left, 0, crop_max_w - crop_min_w);
+	crop->top = clamp_t(u32, crop->top, 0, crop_max_h - crop_min_h);
+	crop->width = clamp_t(u32, crop->width, crop_min_w, crop_max_w);
+	crop->height = clamp_t(u32, crop->height, crop_min_h, crop_max_h);
+}
+
+static int gsc_capture_subdev_set_crop(struct v4l2_subdev *sd,
+				       struct v4l2_subdev_fh *fh,
+				       struct v4l2_subdev_crop *crop)
+{
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+	struct gsc_frame *frame = gsc_capture_get_frame(ctx, crop->pad);
+
+	gsc_cap_try_crop(gsc, &crop->rect, crop->pad);
+
+	if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+		frame->crop = crop->rect;
+
+	return 0;
+}
+
+static int gsc_capture_subdev_get_crop(struct v4l2_subdev *sd,
+				       struct v4l2_subdev_fh *fh,
+				       struct v4l2_subdev_crop *crop)
+{
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct v4l2_rect gcrop = {0, };
+
+	__gsc_cap_get_crop(gsc, fh, crop->pad, crop->which, &gcrop);
+	crop->rect = gcrop;
+
+	return 0;
+}
+
+static struct v4l2_subdev_pad_ops gsc_cap_subdev_pad_ops = {
+	.get_fmt = gsc_capture_subdev_get_fmt,
+	.set_fmt = gsc_capture_subdev_set_fmt,
+	.get_crop = gsc_capture_subdev_get_crop,
+	.set_crop = gsc_capture_subdev_set_crop,
+};
+
+static struct v4l2_subdev_video_ops gsc_cap_subdev_video_ops = {
+	.s_stream = gsc_capture_subdev_s_stream,
+};
+
+static struct v4l2_subdev_ops gsc_cap_subdev_ops = {
+	.pad = &gsc_cap_subdev_pad_ops,
+	.video = &gsc_cap_subdev_video_ops,
+};
+
+static int gsc_capture_init_formats(struct v4l2_subdev *sd,
+				    struct v4l2_subdev_fh *fh)
+{
+	struct v4l2_subdev_format format;
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct gsc_ctx *ctx = gsc->cap.ctx;
+
+	ctx->s_frame.fmt = get_format(2);
+	memset(&format, 0, sizeof(format));
+	format.pad = GSC_PAD_SINK;
+	format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
+	format.format.code = ctx->s_frame.fmt->mbus_code;
+	format.format.width = DEFAULT_GSC_SINK_WIDTH;
+	format.format.height = DEFAULT_GSC_SINK_HEIGHT;
+	gsc_capture_subdev_set_fmt(sd, fh, &format);
+
+	/* G-scaler should not propagate, because it is possible that sink
+	 * format different from source format. But the operation of source pad
+	 * is not needed.
+	 */
+	ctx->d_frame.fmt = get_format(2);
+
+	return 0;
+}
+
+static int gsc_capture_subdev_close(struct v4l2_subdev *sd,
+				    struct v4l2_subdev_fh *fh)
+{
+	gsc_dbg("");
+
+	return 0;
+}
+
+static int gsc_capture_subdev_registered(struct v4l2_subdev *sd)
+{
+	gsc_dbg("");
+
+	return 0;
+}
+
+static void gsc_capture_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	gsc_dbg("");
+}
+
+static const struct v4l2_subdev_internal_ops gsc_cap_v4l2_internal_ops = {
+	.open = gsc_capture_init_formats,
+	.close = gsc_capture_subdev_close,
+	.registered = gsc_capture_subdev_registered,
+	.unregistered = gsc_capture_subdev_unregistered,
+};
+
+static int gsc_capture_link_setup(struct media_entity *entity,
+				  const struct media_pad *local,
+				  const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct gsc_dev *gsc = v4l2_get_subdevdata(sd);
+	struct gsc_capture_device *cap = &gsc->cap;
+
+	switch (local->index | media_entity_type(remote->entity)) {
+	case GSC_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			gsc_info("local to gsc-subdev link enable");
+			if (cap->input != 0)
+				return -EBUSY;
+			/* Write-Back link enabled */
+			if (!strcmp(remote->entity->name, FIMD_MODULE_NAME)) {
+				gsc->cap.sd_disp =
+					media_entity_to_v4l2_subdev(remote->entity);
+				gsc->cap.sd_disp->grp_id = FIMD_GRP_ID;
+				cap->ctx->in_path = GSC_WRITEBACK;
+				cap->input = GSC_IN_FIMD_WRITEBACK;
+			} else if (remote->index == FLITE_PAD_SOURCE_PREV) {
+				cap->ctx->in_path = GSC_CAMERA;
+				cap->input = GSC_IN_FLITE_PREVIEW;
+			} else {
+				cap->ctx->in_path = GSC_CAMERA;
+				cap->input = GSC_IN_FLITE_CAMCORDING;
+			}
+		} else {
+			if (cap->input == GSC_IN_FIMD_WRITEBACK)
+				gsc->pipeline.disp = NULL;
+			else if ((cap->input == GSC_IN_FLITE_PREVIEW) ||
+				(cap->input == GSC_IN_FLITE_CAMCORDING))
+				gsc->pipeline.flite = NULL;
+			gsc_info("local to gsc-subdev link disable");
+			cap->input = GSC_IN_NONE;
+		}
+		break;
+	case GSC_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
+		if (flags & MEDIA_LNK_FL_ENABLED)
+			gsc_info("gsc-subdev to gsc-video link enable");
+		else
+			gsc_info("gsc-subdev to gsc-video link disable");
+		break;
+	}
+
+	return 0;
+}
+
+static const struct media_entity_operations gsc_cap_media_ops = {
+	.link_setup = gsc_capture_link_setup,
+};
+
+static int gsc_capture_create_subdev(struct gsc_dev *gsc)
+{
+	struct v4l2_device *v4l2_dev;
+	struct v4l2_subdev *sd;
+	int ret;
+
+	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
+	if (!sd)
+	       return -ENOMEM;
+
+	v4l2_subdev_init(sd, &gsc_cap_subdev_ops);
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(sd->name, sizeof(sd->name), "gsc-cap-subdev.%d", gsc->id);
+
+	gsc->cap.sd_pads[GSC_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	gsc->cap.sd_pads[GSC_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&sd->entity, GSC_PADS_NUM,
+				gsc->cap.sd_pads, 0);
+	if (ret)
+		goto err_ent;
+
+	sd->internal_ops = &gsc_cap_v4l2_internal_ops;
+	sd->entity.ops = &gsc_cap_media_ops;
+	sd->grp_id = GSC_CAP_GRP_ID;
+	v4l2_dev = &gsc->mdev[MDEV_CAPTURE]->v4l2_dev;
+
+	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+	if (ret)
+		goto err_sub;
+
+	gsc->mdev[MDEV_CAPTURE]->gsc_cap_sd[gsc->id] = sd;
+	gsc->cap.sd_cap = sd;
+	v4l2_set_subdevdata(sd, gsc);
+	gsc_capture_init_formats(sd, NULL);
+
+	return 0;
+
+err_sub:
+	media_entity_cleanup(&sd->entity);
+err_ent:
+	kfree(sd);
+	return ret;
+}
+
+static int gsc_capture_create_link(struct gsc_dev *gsc)
+{
+	struct media_entity *source, *sink;
+	struct exynos_platform_gscaler *pdata = gsc->pdata;
+	struct exynos_isp_info *isp_info;
+	u32 num_clients = pdata->num_clients;
+	int ret, i;
+	enum cam_port id;
+
+	/* GSC-SUBDEV ------> GSC-VIDEO (Always link enable) */
+	source = &gsc->cap.sd_cap->entity;
+	sink = &gsc->cap.vfd->entity;
+	if (source && sink) {
+		ret = media_entity_create_link(source, GSC_PAD_SOURCE, sink, 0, 0);
+		if (ret) {
+			gsc_err("failed link flite to gsc\n");
+			return ret;
+		}
+	}
+	for (i = 0; i < num_clients; i++) {
+		isp_info = pdata->isp_info[i];
+		id = isp_info->cam_port;
+		/* FIMC-LITE ------> GSC-SUBDEV (ITU & MIPI common) */
+		source = &gsc->cap.sd_flite[id]->entity;
+		sink = &gsc->cap.sd_cap->entity;
+		if (source && sink) {
+			if (pdata->cam_preview)
+				ret = media_entity_create_link(source,
+						FLITE_PAD_SOURCE_PREV,
+						sink, GSC_PAD_SINK, 0);
+			if (!ret && pdata->cam_camcording)
+				ret = media_entity_create_link(source,
+						FLITE_PAD_SOURCE_CAMCORD,
+						sink, GSC_PAD_SINK, 0);
+			if (ret) {
+				gsc_err("failed link flite to gsc\n");
+				return ret;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static struct v4l2_subdev *gsc_cap_register_sensor(struct gsc_dev *gsc, int i)
+{
+	struct exynos_md *mdev = gsc->mdev[MDEV_CAPTURE];
+	struct v4l2_subdev *sd = NULL;
+
+	sd = mdev->sensor_sd[i];
+	if (!sd)
+		return NULL;
+
+	v4l2_set_subdev_hostdata(sd, &gsc->cap.sensor[i]);
+
+	return sd;
+}
+
+static int gsc_cap_register_sensor_entities(struct gsc_dev *gsc)
+{
+	struct exynos_platform_gscaler *pdata = gsc->pdata;
+	u32 num_clients = pdata->num_clients;
+	int i;
+
+	for (i = 0; i < num_clients; i++) {
+		gsc->cap.sensor[i].pdata = pdata->isp_info[i];
+		gsc->cap.sensor[i].sd = gsc_cap_register_sensor(gsc, i);
+		if (IS_ERR_OR_NULL(gsc->cap.sensor[i].sd)) {
+			gsc_err("failed to get register sensor");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int gsc_cap_config_camclk(struct gsc_dev *gsc,
+		struct exynos_isp_info *isp_info, int i)
+{
+	struct gsc_capture_device *gsc_cap = &gsc->cap;
+	struct clk *camclk;
+	struct clk *srclk;
+
+	camclk = clk_get(&gsc->pdev->dev, isp_info->cam_clk_name);
+	if (IS_ERR_OR_NULL(camclk)) {
+		gsc_err("failed to get cam clk");
+		return -ENXIO;
+	}
+	gsc_cap->sensor[i].camclk = camclk;
+
+	srclk = clk_get(&gsc->pdev->dev, isp_info->cam_srclk_name);
+	if (IS_ERR_OR_NULL(srclk)) {
+		clk_put(camclk);
+		gsc_err("failed to get cam source clk\n");
+		return -ENXIO;
+	}
+	clk_set_parent(camclk, srclk);
+	clk_set_rate(camclk, isp_info->clk_frequency);
+	clk_put(srclk);
+
+	return 0;
+}
+
+int gsc_register_capture_device(struct gsc_dev *gsc)
+{
+	struct video_device *vfd;
+	struct gsc_capture_device *gsc_cap;
+	struct gsc_ctx *ctx;
+	struct vb2_queue *q;
+	struct exynos_platform_gscaler *pdata = gsc->pdata;
+	struct exynos_isp_info *isp_info;
+	int ret = -ENOMEM;
+	int i;
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	ctx->gsc_dev	 = gsc;
+	ctx->in_path	 = GSC_CAMERA;
+	ctx->out_path	 = GSC_DMA;
+	ctx->state	 = GSC_CTX_CAP;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		printk("Failed to allocate video device\n");
+		goto err_ctx_alloc;
+	}
+
+	snprintf(vfd->name, sizeof(vfd->name), "%s.capture",
+		 dev_name(&gsc->pdev->dev));
+
+	vfd->fops	= &gsc_capture_fops;
+	vfd->ioctl_ops	= &gsc_capture_ioctl_ops;
+	vfd->v4l2_dev	= &gsc->mdev[MDEV_CAPTURE]->v4l2_dev;
+	vfd->minor	= -1;
+	vfd->release	= video_device_release;
+	vfd->lock	= &gsc->lock;
+	video_set_drvdata(vfd, gsc);
+
+	gsc_cap	= &gsc->cap;
+	gsc_cap->vfd = vfd;
+	gsc_cap->refcnt = 0;
+	gsc_cap->active_buf_cnt = 0;
+	gsc_cap->reqbufs_cnt  = 0;
+
+	spin_lock_init(&ctx->slock);
+	gsc_cap->ctx = ctx;
+
+	q = &gsc->cap.vbq;
+	memset(q, 0, sizeof(*q));
+	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	q->io_modes = VB2_MMAP | VB2_USERPTR;
+	q->drv_priv = gsc->cap.ctx;
+	q->ops = &gsc_capture_qops;
+	q->mem_ops = gsc->vb2->ops;
+
+	vb2_queue_init(q);
+
+	/* Get mipi-csis and fimc-lite subdev ptr using mdev */
+	for (i = 0; i < FLITE_MAX_ENTITIES; i++)
+		gsc->cap.sd_flite[i] = gsc->mdev[MDEV_CAPTURE]->flite_sd[i];
+
+	for (i = 0; i < CSIS_MAX_ENTITIES; i++)
+		gsc->cap.sd_csis[i] = gsc->mdev[MDEV_CAPTURE]->csis_sd[i];
+
+	for (i = 0; i < pdata->num_clients; i++) {
+		isp_info = pdata->isp_info[i];
+		ret = gsc_cap_config_camclk(gsc, isp_info, i);
+		if (ret) {
+			gsc_err("failed setup cam clk");
+			goto err_ctx_alloc;
+		}
+	}
+
+	ret = gsc_cap_register_sensor_entities(gsc);
+	if (ret) {
+		gsc_err("failed register sensor entities");
+		goto err_clk;
+	}
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER,
+				    EXYNOS_VIDEONODE_GSC_CAP(gsc->id));
+	if (ret) {
+		gsc_err("failed to register video device");
+		goto err_clk;
+	}
+
+	gsc->cap.vd_pad.flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&vfd->entity, 1, &gsc->cap.vd_pad, 0);
+	if (ret) {
+		gsc_err("failed to initialize entity");
+		goto err_ent;
+	}
+
+	ret = gsc_capture_create_subdev(gsc);
+	if (ret) {
+		gsc_err("failed create subdev");
+		goto err_sd_reg;
+	}
+
+	ret = gsc_capture_create_link(gsc);
+	if (ret) {
+		gsc_err("failed create link");
+		goto err_sd_reg;
+	}
+
+	vfd->ctrl_handler = &ctx->ctrl_handler;
+	gsc_dbg("gsc capture driver registered as /dev/video%d", vfd->num);
+
+	return 0;
+
+err_sd_reg:
+	media_entity_cleanup(&vfd->entity);
+err_ent:
+	video_device_release(vfd);
+err_clk:
+	for (i = 0; i < pdata->num_clients; i++)
+		clk_put(gsc_cap->sensor[i].camclk);
+err_ctx_alloc:
+	kfree(ctx);
+
+	return ret;
+}
+
+static void gsc_capture_destroy_subdev(struct gsc_dev *gsc)
+{
+	struct v4l2_subdev *sd = gsc->cap.sd_cap;
+
+	if (!sd)
+		return;
+	media_entity_cleanup(&sd->entity);
+	v4l2_device_unregister_subdev(sd);
+	kfree(sd);
+	sd = NULL;
+}
+
+void gsc_unregister_capture_device(struct gsc_dev *gsc)
+{
+	struct video_device *vfd = gsc->cap.vfd;
+
+	if (vfd) {
+		media_entity_cleanup(&vfd->entity);
+		/* Can also be called if video device was
+		   not registered */
+		video_unregister_device(vfd);
+	}
+	gsc_capture_destroy_subdev(gsc);
+	kfree(gsc->cap.ctx);
+	gsc->cap.ctx = NULL;
+}
+
diff --git a/drivers/media/video/exynos/gsc/gsc-core.c b/drivers/media/video/exynos/gsc/gsc-core.c
new file mode 100644
index 0000000..d6096e2
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-core.c
@@ -0,0 +1,1674 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-core.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series G-scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <media/v4l2-ioctl.h>
+#include <plat/sysmmu.h>
+
+#include "gsc-core.h"
+#define GSC_CLOCK_GATE_NAME		"gscl"
+
+int gsc_dbg = 6;
+module_param(gsc_dbg, int, 0644);
+
+static struct gsc_fmt gsc_formats[] = {
+	{
+		.name		= "RGB565",
+		.pixelformat	= V4L2_PIX_FMT_RGB565X,
+		.depth		= { 16 },
+		.num_planes	= 1,
+		.nr_comp	= 1,
+	}, {
+		.name		= "XRGB-8-8-8-8, 32 bpp",
+		.pixelformat	= V4L2_PIX_FMT_RGB32,
+		.depth		= { 32 },
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_XRGB8888_4X8_LE,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_YUYV8_2X8,
+	}, {
+		.name		= "YUV 4:2:2 packed, CbYCrY",
+		.pixelformat	= V4L2_PIX_FMT_UYVY,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_C,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_UYVY8_2X8,
+	}, {
+		.name		= "YUV 4:2:2 packed, CrYCbY",
+		.pixelformat	= V4L2_PIX_FMT_VYUY,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_C,
+		.corder		= GSC_CRCB,
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_VYUY8_2X8,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCrYCb",
+		.pixelformat	= V4L2_PIX_FMT_YVYU,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CRCB,
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_YVYU8_2X8,
+	}, {
+		.name		= "YUV 4:4:4 planar, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUV32,
+		.depth		= { 32 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_YUV8_1X24,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV422P,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 3,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV16,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV61,
+		.depth		= { 16 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CRCB,
+		.num_planes	= 1,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YUV 4:2:0 planar, YCbCr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420,
+		.depth		= { 12 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 3,
+	}, {
+		.name		= "YUV 4:2:0 planar, YCbCr",
+		.pixelformat	= V4L2_PIX_FMT_YVU420,
+		.depth		= { 12 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 3,
+
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12,
+		.depth		= { 12 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 1,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21,
+		.depth		= { 12 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CRCB,
+		.num_planes	= 1,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12M,
+		.depth		= { 8, 4 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 2,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YVU 4:2:0 non-contiguous 2-planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21M,
+		.depth		= { 8, 4 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CRCB,
+		.num_planes	= 2,
+		.nr_comp	= 2,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420M,
+		.depth		= { 8, 2, 2 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 3,
+		.nr_comp	= 3,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cr/Cb",
+		.pixelformat	= V4L2_PIX_FMT_YVU420M,
+		.depth		= { 8, 2, 2 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CRCB,
+		.num_planes	= 3,
+		.nr_comp	= 3,
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
+		.pixelformat	= V4L2_PIX_FMT_NV12MT_16X16,
+		.depth		= { 8, 4 },
+		.yorder		= GSC_LSB_Y,
+		.corder		= GSC_CBCR,
+		.num_planes	= 2,
+		.nr_comp	= 2,
+	},
+};
+
+struct gsc_fmt *get_format(int index)
+{
+	return &gsc_formats[index];
+}
+
+struct gsc_fmt *find_format(u32 *pixelformat, u32 *mbus_code, int index)
+{
+	struct gsc_fmt *fmt, *def_fmt = NULL;
+	unsigned int i;
+
+	if (index >= ARRAY_SIZE(gsc_formats))
+		return NULL;
+
+	for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) {
+		fmt = get_format(i);
+		if (pixelformat && fmt->pixelformat == *pixelformat)
+			return fmt;
+		if (mbus_code && fmt->mbus_code == *mbus_code)
+			return fmt;
+		if (index == i)
+			def_fmt = fmt;
+	}
+	return def_fmt;
+
+}
+
+void gsc_set_frame_size(struct gsc_frame *frame, int width, int height)
+{
+	frame->f_width	= width;
+	frame->f_height	= height;
+	frame->crop.width = width;
+	frame->crop.height = height;
+	frame->crop.left = 0;
+	frame->crop.top = 0;
+}
+
+int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst, u32 *ratio)
+{
+	if ((dst > src) || (dst >= src / var->poly_sc_down_max)) {
+		*ratio = 1;
+		return 0;
+	}
+
+	if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) {
+		gsc_err("scale ratio exceeded maximun scale down ratio(1/16)");
+		return -EINVAL;
+	}
+
+	*ratio = (dst > (src / 8)) ? 2 : 4;
+
+	return 0;
+}
+
+void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh)
+{
+	if (hratio == 4 && vratio == 4)
+		*sh = 4;
+	else if ((hratio == 4 && vratio == 2) ||
+		 (hratio == 2 && vratio == 4))
+		*sh = 3;
+	else if ((hratio == 4 && vratio == 1) ||
+		 (hratio == 1 && vratio == 4) ||
+		 (hratio == 2 && vratio == 2))
+		*sh = 2;
+	else if (hratio == 1 && vratio == 1)
+		*sh = 0;
+	else
+		*sh = 1;
+}
+
+void gsc_check_src_scale_info(struct gsc_variant *var, struct gsc_frame *s_frame,
+			      u32 *wratio, u32 tx, u32 ty, u32 *hratio, int rot)
+{
+	int remainder = 0, walign, halign;
+	int poly_sc_walign, poly_sc_halign;
+
+	poly_sc_walign = var->pix_align->real_w;
+	poly_sc_halign = var->pix_align->real_h;
+
+	if (is_yuv420(s_frame->fmt->pixelformat)) {
+		walign = *wratio << poly_sc_walign;
+		halign = *hratio << poly_sc_halign;
+	} else if (is_yuv422(s_frame->fmt->pixelformat)) {
+		walign = *wratio << poly_sc_walign;
+		if (soc_is_exynos5250_rev1 && (rot == 90 || rot == 270))
+			halign = *hratio << poly_sc_halign;
+		else
+			halign = *hratio << (poly_sc_halign - 1);
+	} else {
+		if (soc_is_exynos5250_rev1 && (rot == 90 || rot == 270)) {
+			walign = *wratio << poly_sc_walign;
+			halign = *hratio << poly_sc_halign;
+		} else {
+			walign = *wratio << (poly_sc_walign - 1);
+			halign = *hratio << (poly_sc_halign - 1);
+		}
+	}
+
+	remainder = s_frame->crop.width % walign;
+	if (remainder) {
+		s_frame->crop.width -= remainder;
+		gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio);
+		gsc_info("cropped src width size is recalculated from %d to %d",
+			s_frame->crop.width + remainder, s_frame->crop.width);
+	}
+
+	remainder = s_frame->crop.height % halign;
+	if (remainder) {
+		s_frame->crop.height -= remainder;
+		gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio);
+		gsc_info("cropped src height size is recalculated from %d to %d",
+			s_frame->crop.height + remainder, s_frame->crop.height);
+	}
+}
+
+int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f)
+{
+	struct gsc_fmt *fmt;
+
+	fmt = find_format(NULL, NULL, f->index);
+	if (!fmt)
+		return -EINVAL;
+
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->pixelformat;
+
+	return 0;
+}
+
+u32 get_plane_size(struct gsc_frame *frame, unsigned int plane)
+{
+	if (!frame || plane >= frame->fmt->num_planes) {
+		gsc_err("Invalid argument");
+		return 0;
+	}
+
+	return frame->payload[plane];
+}
+
+u32 get_plane_info(struct gsc_frame frm, u32 addr, u32 *index)
+{
+	if (frm.addr.y == addr) {
+		*index = 0;
+		return frm.addr.y;
+	} else if (frm.addr.cb == addr) {
+		*index = 1;
+		return frm.addr.cb;
+	} else if (frm.addr.cr == addr) {
+		*index = 2;
+		return frm.addr.cr;
+	} else {
+		gsc_err("Plane address is wrong");
+		return -EINVAL;
+	}
+}
+
+void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame frm)
+{
+	u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len;
+	f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0;
+
+	f_chk_addr = frm.addr.y;
+	f_chk_len = frm.payload[0];
+	if (frm.fmt->num_planes == 2) {
+		s_chk_addr = frm.addr.cb;
+		s_chk_len = frm.payload[1];
+	} else if (frm.fmt->num_planes == 3) {
+		u32 low_addr, low_plane, mid_addr, mid_plane, high_addr, high_plane;
+		u32 t_min, t_max;
+
+		t_min = min3(frm.addr.y, frm.addr.cb, frm.addr.cr);
+		low_addr = get_plane_info(frm, t_min, &low_plane);
+		t_max = max3(frm.addr.y, frm.addr.cb, frm.addr.cr);
+		high_addr = get_plane_info(frm, t_max, &high_plane);
+
+		mid_plane = 3 - (low_plane + high_plane);
+		if (mid_plane == 0)
+			mid_addr = frm.addr.y;
+		else if (mid_plane == 1)
+			mid_addr = frm.addr.cb;
+		else if (mid_plane == 2)
+			mid_addr = frm.addr.cr;
+		else
+			return;
+
+		f_chk_addr = low_addr;
+		if (mid_addr + frm.payload[mid_plane] - low_addr >
+		    high_addr + frm.payload[high_plane] - mid_addr) {
+			f_chk_len = frm.payload[low_plane];
+			s_chk_addr = mid_addr;
+			s_chk_len = high_addr + frm.payload[high_plane] - mid_addr;
+		} else {
+			f_chk_len = mid_addr + frm.payload[mid_plane] - low_addr;
+			s_chk_addr = high_addr;
+			s_chk_len = frm.payload[high_plane];
+		}
+	}
+	exynos_sysmmu_set_prefbuf(&gsc->pdev->dev, f_chk_addr, f_chk_len,
+			       s_chk_addr, s_chk_len);
+	gsc_dbg("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n",
+		f_chk_addr, f_chk_len, s_chk_addr, s_chk_len);
+}
+
+int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_variant *variant = gsc->variant;
+	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+	struct gsc_fmt *fmt;
+	u32 max_w, max_h, mod_x, mod_y;
+	u32 min_w, min_h, tmp_w, tmp_h;
+	int i;
+
+	gsc_dbg("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
+
+	fmt = find_format(&pix_mp->pixelformat, NULL, 0);
+	if (!fmt) {
+		gsc_err("pixelformat format (0x%X) invalid\n", pix_mp->pixelformat);
+		return -EINVAL;
+	}
+
+	if (pix_mp->field == V4L2_FIELD_ANY)
+		pix_mp->field = V4L2_FIELD_NONE;
+	else if (pix_mp->field != V4L2_FIELD_NONE) {
+		gsc_err("Not supported field order(%d)\n", pix_mp->field);
+		return -EINVAL;
+	}
+
+	max_w = variant->pix_max->target_rot_dis_w;
+	max_h = variant->pix_max->target_rot_dis_h;
+	if (V4L2_TYPE_IS_OUTPUT(f->type)) {
+		mod_x = ffs(variant->pix_align->org_w) - 1;
+		if (is_yuv420(fmt->pixelformat))
+			mod_y = ffs(variant->pix_align->org_h) - 1;
+		else
+			mod_y = ffs(variant->pix_align->org_h) - 2;
+		min_w = variant->pix_min->org_w;
+		min_h = variant->pix_min->org_h;
+	} else {
+		mod_x = ffs(variant->pix_align->org_w) - 1;
+		if (is_yuv420(fmt->pixelformat))
+			mod_y = ffs(variant->pix_align->org_h) - 1;
+		else
+			mod_y = ffs(variant->pix_align->org_h) - 2;
+		min_w = variant->pix_min->target_rot_dis_w;
+		min_h = variant->pix_min->target_rot_dis_h;
+	}
+	gsc_dbg("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
+	     mod_x, mod_y, max_w, max_h);
+	/* To check if image size is modified to adjust parameter against
+	   hardware abilities */
+	tmp_w = pix_mp->width;
+	tmp_h = pix_mp->height;
+
+	v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
+		&pix_mp->height, min_h, max_h, mod_y, 0);
+	if (tmp_w != pix_mp->width || tmp_h != pix_mp->height) {
+		gsc_dbg("Image size has been modified from %dx%d to %dx%d",
+			 tmp_w, tmp_h, pix_mp->width, pix_mp->height);
+	}
+
+	pix_mp->num_planes = fmt->num_planes;
+
+	if (ctx->gsc_ctrls.csc_eq_mode->val)
+		ctx->gsc_ctrls.csc_eq->val =
+			(pix_mp->width >= 1280) ? 1 : 0;
+	if (ctx->gsc_ctrls.csc_eq->val) /* HD */
+		pix_mp->colorspace = V4L2_COLORSPACE_REC709;
+	else	/* SD */
+		pix_mp->colorspace = V4L2_COLORSPACE_SMPTE170M;
+
+
+	for (i = 0; i < pix_mp->num_planes; ++i) {
+		int bpl = (pix_mp->width * fmt->depth[i]) >> 3;
+		pix_mp->plane_fmt[i].bytesperline = bpl;
+		pix_mp->plane_fmt[i].sizeimage = bpl * pix_mp->height;
+
+		gsc_dbg("[%d]: bpl: %d, sizeimage: %d",
+		    i, bpl, pix_mp->plane_fmt[i].sizeimage);
+	}
+
+	return 0;
+}
+
+int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
+{
+	struct gsc_frame *frame;
+	struct v4l2_pix_format_mplane *pix_mp;
+	int i;
+
+	frame = ctx_get_frame(ctx, f->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	pix_mp = &f->fmt.pix_mp;
+
+	pix_mp->width		= frame->f_width;
+	pix_mp->height		= frame->f_height;
+	pix_mp->field		= V4L2_FIELD_NONE;
+	pix_mp->pixelformat	= frame->fmt->pixelformat;
+	pix_mp->colorspace	= V4L2_COLORSPACE_JPEG;
+	pix_mp->num_planes	= frame->fmt->num_planes;
+
+	for (i = 0; i < pix_mp->num_planes; ++i) {
+		pix_mp->plane_fmt[i].bytesperline = (frame->f_width *
+			frame->fmt->depth[i]) / 8;
+		pix_mp->plane_fmt[i].sizeimage = pix_mp->plane_fmt[i].bytesperline *
+			frame->f_height;
+	}
+
+	return 0;
+}
+
+void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h)
+{
+	if (tmp_w != *w || tmp_h != *h) {
+		gsc_info("Image cropped size has been modified from %dx%d to %dx%d",
+				*w, *h, tmp_w, tmp_h);
+		*w = tmp_w;
+		*h = tmp_h;
+	}
+}
+
+int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
+{
+	struct gsc_frame *frame;
+
+	frame = ctx_get_frame(ctx, cr->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	memcpy(&cr->c, &frame->crop, sizeof(struct v4l2_rect));
+
+	return 0;
+}
+
+int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
+{
+	struct gsc_frame *f;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_variant *variant = gsc->variant;
+	u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h;
+	u32 min_w, min_h, max_w, max_h;
+
+	if (cr->c.top < 0 || cr->c.left < 0) {
+		gsc_err("doesn't support negative values for top & left\n");
+		return -EINVAL;
+	}
+	gsc_dbg("user put w: %d, h: %d", cr->c.width, cr->c.height);
+
+	if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		f = &ctx->d_frame;
+	else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		f = &ctx->s_frame;
+	else
+		return -EINVAL;
+
+	max_w = f->f_width;
+	max_h = f->f_height;
+	tmp_w = cr->c.width;
+	tmp_h = cr->c.height;
+
+	if (V4L2_TYPE_IS_OUTPUT(cr->type)) {
+		if ((is_yuv422(f->fmt->pixelformat) && f->fmt->nr_comp == 1) ||
+		    is_rgb(f->fmt->pixelformat))
+			min_w = 32;
+		else
+			min_w = 64;
+		if ((is_yuv422(f->fmt->pixelformat) && f->fmt->nr_comp == 3) ||
+		    is_yuv420(f->fmt->pixelformat))
+			min_h = 32;
+		else
+			min_h = 16;
+	} else {
+		if (is_yuv420(f->fmt->pixelformat) ||
+		    is_yuv422(f->fmt->pixelformat))
+			mod_x = ffs(variant->pix_align->target_w) - 1;
+		if (is_yuv420(f->fmt->pixelformat))
+			mod_y = ffs(variant->pix_align->target_h) - 1;
+		if (ctx->gsc_ctrls.rotate->val == 90 ||
+		    ctx->gsc_ctrls.rotate->val == 270) {
+			max_w = f->f_height;
+			max_h = f->f_width;
+			min_w = variant->pix_min->target_rot_en_w;
+			min_h = variant->pix_min->target_rot_en_h;
+			tmp_w = cr->c.height;
+			tmp_h = cr->c.width;
+		} else {
+			min_w = variant->pix_min->target_rot_dis_w;
+			min_h = variant->pix_min->target_rot_dis_h;
+		}
+	}
+	gsc_dbg("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d,\
+		tmp_w : %d, tmp_h : %d",
+		mod_x, mod_y, min_w, min_h, tmp_w, tmp_h);
+
+	v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x,
+			      &tmp_h, min_h, max_h, mod_y, 0);
+
+	if (!V4L2_TYPE_IS_OUTPUT(cr->type) &&
+	    (ctx->gsc_ctrls.rotate->val == 90 ||
+	    ctx->gsc_ctrls.rotate->val == 270)) {
+		gsc_check_crop_change(tmp_h, tmp_w, &cr->c.width, &cr->c.height);
+	} else {
+		gsc_check_crop_change(tmp_w, tmp_h, &cr->c.width, &cr->c.height);
+	}
+
+	/* adjust left/top if cropping rectangle is out of bounds */
+	/* Need to add code to algin left value with 2's multiple */
+	if (cr->c.left + tmp_w > max_w)
+		cr->c.left = max_w - tmp_w;
+	if (cr->c.top + tmp_h > max_h)
+		cr->c.top = max_h - tmp_h;
+
+	if (is_yuv420(f->fmt->pixelformat) || is_yuv422(f->fmt->pixelformat))
+		if (cr->c.left % 2)
+			cr->c.left -= 1;
+
+	gsc_dbg("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
+	    cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h);
+
+	return 0;
+}
+
+int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
+			   int dh, int rot, int out_path)
+{
+	int tmp_w, tmp_h, sc_down_max;
+	sc_down_max =
+		(out_path == GSC_DMA) ? var->sc_down_max : var->local_sc_down;
+
+	if (rot == 90 || rot == 270) {
+		tmp_w = dh;
+		tmp_h = dw;
+	} else {
+		tmp_w = dw;
+		tmp_h = dh;
+	}
+
+	if ((sw > (tmp_w * sc_down_max)) ||
+	    (sh > (tmp_h * sc_down_max)) ||
+	    (tmp_w > (sw * var->sc_up_max)) ||
+	    (tmp_h > (sh * var->sc_up_max)))
+		return -EINVAL;
+
+	return 0;
+}
+
+int gsc_set_scaler_info(struct gsc_ctx *ctx)
+{
+	struct gsc_scaler *sc = &ctx->scaler;
+	struct gsc_frame *s_frame = &ctx->s_frame;
+	struct gsc_frame *d_frame = &ctx->d_frame;
+	struct gsc_variant *variant = ctx->gsc_dev->variant;
+	int tx, ty, rot;
+	int ret;
+
+	rot = ctx->gsc_ctrls.rotate->val;
+
+	ret = gsc_check_scaler_ratio(variant, s_frame->crop.width,
+		s_frame->crop.height, d_frame->crop.width, d_frame->crop.height,
+		ctx->gsc_ctrls.rotate->val, ctx->out_path);
+	if (ret) {
+		gsc_err("out of scaler range");
+		return ret;
+	}
+
+	if (rot == 90 || rot == 270) {
+		ty = d_frame->crop.width;
+		tx = d_frame->crop.height;
+	} else {
+		tx = d_frame->crop.width;
+		ty = d_frame->crop.height;
+	}
+
+	ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width,
+				      tx, &sc->pre_hratio);
+	if (ret) {
+		gsc_err("Horizontal scale ratio is out of range");
+		return ret;
+	}
+
+	ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height,
+				      ty, &sc->pre_vratio);
+	if (ret) {
+		gsc_err("Vertical scale ratio is out of range");
+		return ret;
+	}
+
+	gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio,
+				 tx, ty, &sc->pre_vratio, rot);
+
+	gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
+				   &sc->pre_shfactor);
+
+	sc->main_hratio = (s_frame->crop.width << 16) / tx;
+	sc->main_vratio = (s_frame->crop.height << 16) / ty;
+
+	gsc_dbg("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d",
+		s_frame->crop.width, s_frame->crop.height, tx, ty);
+	gsc_dbg("scaler ratio info : pre_shfactor : %d, pre_h : %d, pre_v :%d,\
+		main_h : %ld, main_v : %ld", sc->pre_shfactor, sc->pre_hratio,
+		sc->pre_vratio, sc->main_hratio, sc->main_vratio);
+
+	return 0;
+}
+
+int gsc_pipeline_s_stream(struct gsc_dev *gsc, bool on)
+{
+	struct gsc_pipeline *p = &gsc->pipeline;
+	struct exynos_entity_data md_data;
+	int ret = 0;
+
+	/* If gscaler subdev calls the mixer's s_stream, the gscaler must
+	   inform the mixer subdev pipeline started from gscaler */
+	if (!strncmp(p->disp->name, MXR_SUBDEV_NAME,
+				sizeof(MXR_SUBDEV_NAME) - 1)) {
+		md_data.mxr_data_from = FROM_GSC_SD;
+		v4l2_set_subdevdata(p->disp, &md_data);
+	}
+
+	ret = v4l2_subdev_call(p->disp, video, s_stream, on);
+	if (ret)
+		gsc_err("Display s_stream on failed\n");
+
+	return ret;
+}
+
+int gsc_out_link_validate(const struct media_pad *source,
+			  const struct media_pad *sink)
+{
+	struct v4l2_subdev_format src_fmt;
+	struct v4l2_subdev_crop dst_crop;
+	struct v4l2_subdev *sd;
+	struct gsc_dev *gsc;
+	struct gsc_frame *f;
+	int ret;
+
+	if (media_entity_type(source->entity) != MEDIA_ENT_T_V4L2_SUBDEV ||
+	    media_entity_type(sink->entity) != MEDIA_ENT_T_V4L2_SUBDEV) {
+		gsc_err("media entity type isn't subdev\n");
+		return 0;
+	}
+
+	sd = media_entity_to_v4l2_subdev(source->entity);
+	gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	f = &gsc->out.ctx->d_frame;
+
+	src_fmt.format.width = f->crop.width;
+	src_fmt.format.height = f->crop.height;
+	src_fmt.format.code = f->fmt->mbus_code;
+
+	sd = media_entity_to_v4l2_subdev(sink->entity);
+	/* To check if G-Scaler destination size and Mixer destinatin size
+	   are the same */
+	dst_crop.pad = sink->index;
+	dst_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+	ret = v4l2_subdev_call(sd, pad, get_crop, NULL, &dst_crop);
+	if (ret < 0 && ret != -ENOIOCTLCMD) {
+		gsc_err("subdev get_fmt is failed\n");
+		return -EPIPE;
+	}
+
+	if (src_fmt.format.width != dst_crop.rect.width ||
+	    src_fmt.format.height != dst_crop.rect.height) {
+		gsc_err("sink and source format is different\
+			src_fmt.w = %d, src_fmt.h = %d,\
+			dst_crop.w = %d, dst_crop.h = %d, rotation = %d",
+			src_fmt.format.width, src_fmt.format.height,
+			dst_crop.rect.width, dst_crop.rect.height,
+			gsc->out.ctx->gsc_ctrls.rotate->val);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * Set alpha blending for all layers of mixer when gscaler is connected
+ * to mixer only
+ */
+static int gsc_s_ctrl_to_mxr(struct v4l2_ctrl *ctrl)
+{
+	struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
+	struct media_pad *pad = &ctx->gsc_dev->out.sd_pads[GSC_PAD_SOURCE];
+	struct v4l2_subdev *sd, *gsc_sd;
+	struct v4l2_control control;
+
+	pad = media_entity_remote_source(pad);
+	if (IS_ERR(pad)) {
+		gsc_err("No sink pad conncted with a gscaler source pad");
+		return PTR_ERR(pad);
+	}
+
+	sd = media_entity_to_v4l2_subdev(pad->entity);
+	gsc_sd = ctx->gsc_dev->out.sd;
+	gsc_dbg("%s is connected to %s\n", gsc_sd->name, sd->name);
+	if (strcmp(sd->name, "s5p-mixer0") && strcmp(sd->name, "s5p-mixer1")) {
+		gsc_err("%s is not connected to mixer\n", gsc_sd->name);
+		return -ENODEV;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_TV_LAYER_BLEND_ENABLE:
+	case V4L2_CID_TV_LAYER_BLEND_ALPHA:
+	case V4L2_CID_TV_PIXEL_BLEND_ENABLE:
+	case V4L2_CID_TV_CHROMA_ENABLE:
+	case V4L2_CID_TV_CHROMA_VALUE:
+	case V4L2_CID_TV_LAYER_PRIO:
+		control.id = ctrl->id;
+		control.value = ctrl->val;
+		v4l2_subdev_call(sd, core, s_ctrl, &control);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * V4L2 controls handling
+ */
+static int gsc_g_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+
+	switch (ctrl->id) {
+	case V4L2_CID_M2M_CTX_NUM:
+		update_ctrl_value(ctx->gsc_ctrls.m2m_ctx_num, gsc->m2m.refcnt);
+		break;
+
+	default:
+		gsc_err("Invalid control\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int gsc_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
+	int ret;
+
+	switch (ctrl->id) {
+	case V4L2_CID_HFLIP:
+		update_ctrl_value(ctx->gsc_ctrls.hflip, ctrl->val);
+		break;
+
+	case V4L2_CID_VFLIP:
+		update_ctrl_value(ctx->gsc_ctrls.vflip, ctrl->val);
+		break;
+
+	case V4L2_CID_ROTATE:
+		update_ctrl_value(ctx->gsc_ctrls.rotate, ctrl->val);
+		break;
+
+	case V4L2_CID_GLOBAL_ALPHA:
+		update_ctrl_value(ctx->gsc_ctrls.global_alpha, ctrl->val);
+		break;
+
+	case V4L2_CID_CACHEABLE:
+		update_ctrl_value(ctx->gsc_ctrls.cacheable, ctrl->val);
+		break;
+
+	case V4L2_CID_CSC_EQ_MODE:
+		update_ctrl_value(ctx->gsc_ctrls.csc_eq_mode, ctrl->val);
+		break;
+
+	case V4L2_CID_CSC_EQ:
+		update_ctrl_value(ctx->gsc_ctrls.csc_eq, ctrl->val);
+		break;
+
+	case V4L2_CID_CSC_RANGE:
+		update_ctrl_value(ctx->gsc_ctrls.csc_range, ctrl->val);
+		break;
+
+	case V4L2_CID_USE_SYSMMU:
+		update_ctrl_value(ctx->gsc_ctrls.use_sysmmu, ctrl->val);
+		break;
+
+	default:
+		ret = gsc_s_ctrl_to_mxr(ctrl);
+		if (ret) {
+			gsc_err("Invalid control\n");
+			return ret;
+		}
+	}
+
+	if (gsc_m2m_opened(ctx->gsc_dev))
+		gsc_ctx_state_lock_set(GSC_PARAMS, ctx);
+
+	return 0;
+}
+
+const struct v4l2_ctrl_ops gsc_ctrl_ops = {
+	.g_volatile_ctrl = gsc_g_ctrl,
+	.s_ctrl = gsc_s_ctrl,
+};
+
+static const struct v4l2_ctrl_config gsc_custom_ctrl[] = {
+	{
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_GLOBAL_ALPHA,
+		.name = "Set RGB alpha",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = 255,
+		.step = 1,
+		.def = 0,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_CACHEABLE,
+		.name = "Set cacheable",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = 1,
+		.def = true,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_LAYER_BLEND_ENABLE,
+		.name = "Enable layer alpha blending",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_LAYER_BLEND_ALPHA,
+		.name = "Set alpha for layer blending",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.min = 0,
+		.max = 255,
+		.step = 1,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_PIXEL_BLEND_ENABLE,
+		.name = "Enable pixel alpha blending",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_CHROMA_ENABLE,
+		.name = "Enable chromakey",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_CHROMA_VALUE,
+		.name = "Set chromakey value",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.min = 0,
+		.max = 255,
+		.step = 1,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_TV_LAYER_PRIO,
+		.name = "Set layer priority",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.min = 0,
+		.max = 15,
+		.def = 1,
+		.step = 1,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_CSC_EQ_MODE,
+		.name = "Set CSC equation mode",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = DEFAULT_CSC_EQ,
+		.def = DEFAULT_CSC_EQ,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_CSC_EQ,
+		.name = "Set CSC equation",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.step = 1,
+		.max = 8,
+		.def = V4L2_COLORSPACE_REC709,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_CSC_RANGE,
+		.name = "Set CSC range",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = DEFAULT_CSC_RANGE,
+		.def = DEFAULT_CSC_RANGE,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_M2M_CTX_NUM,
+		.name = "Get number of m2m context",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.step = 1,
+		.min = 0,
+		.max = 255,
+		.def = 0,
+		.is_volatile = 1,
+	}, {
+		.ops = &gsc_ctrl_ops,
+		.id = V4L2_CID_USE_SYSMMU,
+		.name = "set the use of sysmmu",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = DEFAULT_USE_SYSMMU,
+		.def = DEFAULT_USE_SYSMMU,
+	},
+};
+
+int gsc_ctrls_create(struct gsc_ctx *ctx)
+{
+	if (ctx->ctrls_rdy) {
+		gsc_err("Control handler of this context was created already");
+		return 0;
+	}
+
+	v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM);
+
+	ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
+	ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
+	ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
+	ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[0], NULL);
+	ctx->gsc_ctrls.cacheable = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[1], NULL);
+	/* for mixer control */
+	ctx->gsc_ctrls.layer_blend_en = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[2], NULL);
+	ctx->gsc_ctrls.layer_alpha = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[3], NULL);
+	ctx->gsc_ctrls.pixel_blend_en = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[4], NULL);
+	ctx->gsc_ctrls.chroma_en = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[5], NULL);
+	ctx->gsc_ctrls.chroma_val = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[6], NULL);
+	ctx->gsc_ctrls.prio = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[7], NULL);
+
+	/* for CSC equation */
+	ctx->gsc_ctrls.csc_eq_mode = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[8], NULL);
+	ctx->gsc_ctrls.csc_eq = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[9], NULL);
+	ctx->gsc_ctrls.csc_range = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[10], NULL);
+	ctx->gsc_ctrls.m2m_ctx_num = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[11], NULL);
+
+	ctx->gsc_ctrls.use_sysmmu = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
+					&gsc_custom_ctrl[12], NULL);
+
+	ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
+
+	if (ctx->ctrl_handler.error) {
+		int err = ctx->ctrl_handler.error;
+		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+		gsc_err("Failed to gscaler control hander create");
+		return err;
+	}
+
+	return 0;
+}
+
+void gsc_ctrls_delete(struct gsc_ctx *ctx)
+{
+	if (ctx->ctrls_rdy) {
+		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+		ctx->ctrls_rdy = false;
+	}
+}
+
+/* The color format (nr_comp, num_planes) must be already configured. */
+int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
+		     struct gsc_frame *frame, struct gsc_addr *addr)
+{
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret = 0;
+	u32 pix_size;
+
+	if (IS_ERR(vb) || IS_ERR(frame)) {
+		gsc_err("Invalid argument");
+		return -EINVAL;
+	}
+
+	pix_size = frame->f_width * frame->f_height;
+
+	gsc_dbg("num_planes= %d, nr_comp= %d, pix_size= %d",
+		frame->fmt->num_planes, frame->fmt->nr_comp, pix_size);
+
+	if (!gsc->vb2->use_sysmmu) {
+		WARN_ON(vb2_ion_phys_address(
+			vb2_plane_cookie(vb, 0),
+			&addr->y) != 0);
+	} else
+		addr->y = gsc->vb2->plane_addr(vb, 0);
+
+	if (frame->fmt->num_planes == 1) {
+		switch (frame->fmt->nr_comp) {
+		case 1:
+			addr->cb = 0;
+			addr->cr = 0;
+			break;
+		case 2:
+			/* decompose Y into Y/Cb */
+			addr->cb = (dma_addr_t)(addr->y + pix_size);
+			addr->cr = 0;
+			break;
+		case 3:
+			addr->cb = (dma_addr_t)(addr->y + pix_size);
+			addr->cr = (dma_addr_t)(addr->cb + (pix_size >> 2));
+			break;
+		default:
+			gsc_err("Invalid the number of color planes");
+			return -EINVAL;
+		}
+	} else {
+		if (frame->fmt->num_planes >= 2) {
+			if (!gsc->vb2->use_sysmmu) {
+				WARN_ON(vb2_ion_phys_address(
+					vb2_plane_cookie(vb, 1),
+					&addr->cb) != 0);
+			} else
+				addr->cb = gsc->vb2->plane_addr(vb, 1);
+		}
+
+		if (frame->fmt->num_planes == 3) {
+			if (!gsc->vb2->use_sysmmu) {
+				WARN_ON(vb2_ion_phys_address(
+					vb2_plane_cookie(vb, 2),
+					&addr->cr) != 0);
+			} else
+				addr->cr = gsc->vb2->plane_addr(vb, 2);
+		}
+	}
+
+	gsc_dbg("ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
+		addr->y, addr->cb, addr->cr, ret);
+
+	return ret;
+}
+
+void gsc_cap_irq_handler(struct gsc_dev *gsc)
+{
+	int done_index;
+
+	done_index = gsc_hw_get_done_output_buf_index(gsc);
+	gsc_dbg("done_index : %d", done_index);
+	if (done_index < 0) {
+		gsc_err("All buffers are masked\n");
+		return;
+	}
+	test_bit(ST_CAPT_RUN, &gsc->state) ? :
+		set_bit(ST_CAPT_RUN, &gsc->state);
+	vb2_buffer_done(gsc->cap.vbq.bufs[done_index], VB2_BUF_STATE_DONE);
+}
+
+static irqreturn_t gsc_irq_handler(int irq, void *priv)
+{
+	struct gsc_dev *gsc = priv;
+	int gsc_irq;
+
+	gsc_irq = gsc_hw_get_irq_status(gsc);
+	gsc_hw_clear_irq(gsc, gsc_irq);
+
+	if (gsc_irq == GSC_OR_IRQ) {
+		gsc_err("Local path input over-run interrupt has occurred!");
+		return IRQ_HANDLED;
+	}
+
+	spin_lock(&gsc->slock);
+
+	if (test_and_clear_bit(ST_M2M_RUN, &gsc->state)) {
+		struct vb2_buffer *src_vb, *dst_vb;
+		struct gsc_ctx *ctx =
+			v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
+
+		gsc_clock_gating(gsc, GSC_CLK_OFF);
+		if (!ctx || !ctx->m2m_ctx)
+			goto isr_unlock;
+
+		del_timer(&ctx->op_timer);
+		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+		if (src_vb && dst_vb) {
+			v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
+			v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
+
+			if (test_and_clear_bit(ST_STOP_REQ, &gsc->state))
+				wake_up(&gsc->irq_queue);
+			else
+				v4l2_m2m_job_finish(gsc->m2m.m2m_dev, ctx->m2m_ctx);
+
+			/* wake_up job_abort, stop_streaming */
+			spin_lock(&ctx->slock);
+			if (ctx->state & GSC_CTX_STOP_REQ) {
+				ctx->state &= ~GSC_CTX_STOP_REQ;
+				wake_up(&gsc->irq_queue);
+			}
+			spin_unlock(&ctx->slock);
+		}
+		pm_runtime_put(&gsc->pdev->dev);
+	} else if (test_bit(ST_OUTPUT_STREAMON, &gsc->state)) {
+		if (!list_empty(&gsc->out.active_buf_q) &&
+		    !list_is_singular(&gsc->out.active_buf_q)) {
+			struct gsc_input_buf *done_buf;
+			done_buf = active_queue_pop(&gsc->out, gsc);
+
+			if (done_buf->idx != gsc_hw_get_curr_in_buf_idx(gsc)) {
+				gsc_hw_set_input_buf_masking(gsc, done_buf->idx, true);
+				vb2_buffer_done(&done_buf->vb, VB2_BUF_STATE_DONE);
+				list_del(&done_buf->list);
+			}
+		}
+	} else if (test_bit(ST_CAPT_PEND, &gsc->state)) {
+		gsc_cap_irq_handler(gsc);
+	}
+
+isr_unlock:
+	spin_unlock(&gsc->slock);
+	return IRQ_HANDLED;
+}
+
+static int gsc_get_media_info(struct device *dev, void *p)
+{
+	struct exynos_md **mdev = p;
+	struct platform_device *pdev = to_platform_device(dev);
+
+	mdev[pdev->id] = dev_get_drvdata(dev);
+	if (!mdev[pdev->id])
+		return -ENODEV;
+
+	return 0;
+}
+
+void gsc_clock_gating(struct gsc_dev *gsc, enum gsc_clk_status status)
+{
+	int clk_cnt;
+
+	if (status == GSC_CLK_ON) {
+		clk_cnt = atomic_inc_return(&gsc->clk_cnt);
+		if (clk_cnt == 1) {
+			clk_enable(gsc->clock);
+			if (gsc->vb2->use_sysmmu)
+				gsc->vb2->resume(gsc->alloc_ctx);
+			set_bit(ST_PWR_ON, &gsc->state);
+		}
+	} else if (status == GSC_CLK_OFF) {
+		clk_cnt = atomic_dec_return(&gsc->clk_cnt);
+		if (clk_cnt == 0) {
+			if (gsc->vb2->use_sysmmu)
+				gsc->vb2->suspend(gsc->alloc_ctx);
+			clk_disable(gsc->clock);
+			clear_bit(ST_PWR_ON, &gsc->state);
+		} else if (clk_cnt < 0) {
+			gsc_err("clock count is out of range");
+			atomic_set(&gsc->clk_cnt, 0);
+		}
+	}
+}
+
+static int gsc_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gsc_dev *gsc = (struct gsc_dev *)platform_get_drvdata(pdev);
+
+	if (!gsc_m2m_opened(gsc))
+		gsc_clock_gating(gsc, GSC_CLK_OFF);
+	else
+		gsc->m2m.ctx = NULL;
+
+	return 0;
+}
+
+static int gsc_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gsc_dev *gsc = (struct gsc_dev *)platform_get_drvdata(pdev);
+
+	if (!gsc_m2m_opened(gsc))
+		gsc_clock_gating(gsc, GSC_CLK_ON);
+
+	return 0;
+}
+
+static void gsc_pm_runtime_enable(struct device *dev)
+{
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_enable(dev);
+#else
+	gsc_runtime_resume(dev);
+#endif
+}
+
+static void gsc_pm_runtime_disable(struct device *dev)
+{
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(dev);
+#else
+	gsc_runtime_suspend(dev);
+#endif
+}
+
+static int gsc_probe(struct platform_device *pdev)
+{
+	struct gsc_dev *gsc;
+	struct resource *res;
+	struct gsc_driverdata *drv_data;
+	struct device_driver *driver;
+	struct exynos_md *mdev[MDEV_MAX_NUM] = {NULL,};
+	int ret = 0;
+
+	dev_dbg(&pdev->dev, "%s():\n", __func__);
+	drv_data = (struct gsc_driverdata *)
+		platform_get_device_id(pdev)->driver_data;
+
+	if (pdev->id >= drv_data->num_entities) {
+		dev_err(&pdev->dev, "Invalid platform device id: %d\n",
+			pdev->id);
+		return -EINVAL;
+	}
+
+	gsc = kzalloc(sizeof(struct gsc_dev), GFP_KERNEL);
+	if (!gsc)
+		return -ENOMEM;
+
+	gsc->id = pdev->id;
+	gsc->variant = drv_data->variant[gsc->id];
+	gsc->pdev = pdev;
+	gsc->pdata = pdev->dev.platform_data;
+
+	init_waitqueue_head(&gsc->irq_queue);
+	spin_lock_init(&gsc->slock);
+	mutex_init(&gsc->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to find the registers\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	gsc->regs_res = request_mem_region(res->start, resource_size(res),
+			dev_name(&pdev->dev));
+	if (!gsc->regs_res) {
+		dev_err(&pdev->dev, "failed to obtain register region\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	gsc->regs = ioremap(res->start, resource_size(res));
+	if (!gsc->regs) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENXIO;
+		goto err_req_region;
+	}
+
+	/* Get Gscaler clock */
+	gsc->clock = clk_get(&gsc->pdev->dev, GSC_CLOCK_GATE_NAME);
+	if (IS_ERR(gsc->clock)) {
+		gsc_err("failed to get gscaler.%d clock", gsc->id);
+		goto err_regs_unmap;
+	}
+	clk_put(gsc->clock);
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get IRQ resource\n");
+		ret = -ENXIO;
+		goto err_regs_unmap;
+	}
+	gsc->irq = res->start;
+
+	ret = request_irq(gsc->irq, gsc_irq_handler, 0, pdev->name, gsc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
+		goto err_regs_unmap;
+	}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	gsc->vb2 = &gsc_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	gsc->vb2 = &gsc_vb2_ion;
+#endif
+
+	platform_set_drvdata(pdev, gsc);
+
+	ret = gsc_register_m2m_device(gsc);
+	if (ret)
+		goto err_irq;
+
+	/* find media device */
+	driver = driver_find(MDEV_MODULE_NAME, &platform_bus_type);
+	if (!driver)
+		goto err_irq;
+
+	ret = driver_for_each_device(driver, NULL, &mdev[0],
+			gsc_get_media_info);
+	put_driver(driver);
+	if (ret)
+		goto err_irq;
+
+	gsc->mdev[MDEV_OUTPUT] = mdev[MDEV_OUTPUT];
+	gsc->mdev[MDEV_CAPTURE] = mdev[MDEV_CAPTURE];
+
+	gsc_dbg("mdev->mdev[%d] = 0x%08x, mdev->mdev[%d] = 0x%08x",
+		 MDEV_OUTPUT, (u32)gsc->mdev[MDEV_OUTPUT], MDEV_CAPTURE,
+		 (u32)gsc->mdev[MDEV_CAPTURE]);
+
+	ret = gsc_register_output_device(gsc);
+	if (ret)
+		goto err_irq;
+
+	if (gsc->pdata)	{
+		ret = gsc_register_capture_device(gsc);
+		if (ret)
+			goto err_irq;
+	}
+
+	gsc->alloc_ctx = gsc->vb2->init(gsc);
+	if (IS_ERR(gsc->alloc_ctx)) {
+		ret = PTR_ERR(gsc->alloc_ctx);
+		goto err_irq;
+	}
+	gsc_pm_runtime_enable(&pdev->dev);
+
+	gsc_info("gsc-%d registered successfully", gsc->id);
+
+	return 0;
+
+err_irq:
+	free_irq(gsc->irq, gsc);
+err_regs_unmap:
+	iounmap(gsc->regs);
+err_req_region:
+	release_resource(gsc->regs_res);
+	kfree(gsc->regs_res);
+err_info:
+	kfree(gsc);
+
+	return ret;
+}
+
+static int __devexit gsc_remove(struct platform_device *pdev)
+{
+	struct gsc_dev *gsc =
+		(struct gsc_dev *)platform_get_drvdata(pdev);
+
+	free_irq(gsc->irq, gsc);
+
+	gsc_unregister_m2m_device(gsc);
+	gsc_unregister_output_device(gsc);
+	gsc_unregister_capture_device(gsc);
+
+	gsc->vb2->cleanup(gsc->alloc_ctx);
+	gsc_pm_runtime_disable(&pdev->dev);
+
+	iounmap(gsc->regs);
+	release_resource(gsc->regs_res);
+	kfree(gsc->regs_res);
+	kfree(gsc);
+
+	dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
+	return 0;
+}
+
+static int gsc_suspend(struct device *dev)
+{
+	struct platform_device *pdev;
+	struct gsc_dev *gsc;
+	int ret = 0;
+
+	pdev = to_platform_device(dev);
+	gsc = (struct gsc_dev *)platform_get_drvdata(pdev);
+
+	if (gsc_m2m_run(gsc)) {
+		set_bit(ST_STOP_REQ, &gsc->state);
+		ret = wait_event_timeout(gsc->irq_queue,
+				!test_bit(ST_STOP_REQ, &gsc->state),
+				GSC_SHUTDOWN_TIMEOUT);
+		if (ret == 0)
+			dev_err(&gsc->pdev->dev, "wait timeout : %s\n",
+				__func__);
+	}
+	if (gsc_cap_active(gsc)) {
+		gsc_err("capture device is running!!");
+		return -EINVAL;
+	}
+
+	pm_runtime_put_sync(dev);
+
+	return ret;
+}
+
+static int gsc_resume(struct device *dev)
+{
+	struct platform_device *pdev;
+	struct gsc_driverdata *drv_data;
+	struct gsc_dev *gsc;
+	struct gsc_ctx *ctx;
+
+	pdev = to_platform_device(dev);
+	gsc = (struct gsc_dev *)platform_get_drvdata(pdev);
+	drv_data = (struct gsc_driverdata *)
+		platform_get_device_id(pdev)->driver_data;
+
+	pm_runtime_get_sync(dev);
+	if (gsc_m2m_opened(gsc)) {
+		ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
+		if (ctx != NULL) {
+			gsc->m2m.ctx = NULL;
+			v4l2_m2m_job_finish(gsc->m2m.m2m_dev, ctx->m2m_ctx);
+		}
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops gsc_pm_ops = {
+	.suspend		= gsc_suspend,
+	.resume			= gsc_resume,
+	.runtime_suspend	= gsc_runtime_suspend,
+	.runtime_resume		= gsc_runtime_resume,
+};
+
+struct gsc_pix_max gsc_v_max = {
+	.org_scaler_bypass_w	= 8192,
+	.org_scaler_bypass_h	= 8192,
+	.org_scaler_input_w	= 4800,
+	.org_scaler_input_h	= 3344,
+	.real_rot_dis_w		= 4800,
+	.real_rot_dis_h		= 3344,
+	.real_rot_en_w		= 2047,
+	.real_rot_en_h		= 2047,
+	.target_rot_dis_w	= 4800,
+	.target_rot_dis_h	= 3344,
+	.target_rot_en_w	= 2016,
+	.target_rot_en_h	= 2016,
+};
+
+struct gsc_pix_min gsc_v_min[2] = {
+	[0] = {
+		.org_w			= 64,
+		.org_h			= 32,
+		.real_w			= 64,
+		.real_h			= 32,
+		.target_rot_dis_w	= 64,
+		.target_rot_dis_h	= 32,
+		.target_rot_en_w	= 32,
+		.target_rot_en_h	= 16,
+	},
+	[1] = {
+		.org_w			= 16,
+		.org_h			= 8,
+		.real_w			= 16,
+		.real_h			= 16,
+		.target_rot_dis_w	= 16,
+		.target_rot_dis_h	= 8,
+		.target_rot_en_w	= 16,
+		.target_rot_en_h	= 8,
+	},
+};
+
+struct gsc_pix_align gsc_v_align[2] = {
+	[0] = {
+		.org_h			= 16,
+		.org_w			= 16, /* yuv420 : 16, others : 8 */
+		.offset_h		= 2,  /* yuv420/422 : 2, others : 1 */
+		.real_w			= 2, /* yuv420/422 : 4~16, others : 2~8 */
+		.real_h			= 2, /* yuv420 : 4~16, others : 1 */
+		.target_w		= 2,  /* yuv420/422 : 2, others : 1 */
+		.target_h		= 2,  /* yuv420 : 2, others : 1 */
+	},
+	[1] = {
+		.org_h			= 16,
+		.org_w			= 16, /* yuv420 : 16, others : 8 */
+		.offset_h		= 2,  /* yuv420/422 : 2, others : 1 */
+		.real_w			= 1,  /* yuv420/422 : 2~8, others : 1~4 */
+		.real_h			= 1,  /* yuv420 : 2~8, others : 1~4 */
+		.target_w		= 2,  /* yuv420/422 : 2, others : 1 */
+		.target_h		= 2,  /* yuv420 : 2, others : 1 */
+	},
+};
+
+struct gsc_variant gsc_v_100_variant = {
+	.pix_max		= &gsc_v_max,
+	.pix_min		= &gsc_v_min[0],
+	.pix_align		= &gsc_v_align[0],
+	.in_buf_cnt		= 8,
+	.out_buf_cnt		= 16,
+	.sc_up_max		= 8,
+	.sc_down_max		= 16,
+	.poly_sc_down_max	= 4,
+	.pre_sc_down_max	= 4,
+	.local_sc_down		= 2,
+};
+
+struct gsc_variant gsc_v_200_variant = {
+	.pix_max		= &gsc_v_max,
+	.pix_min		= &gsc_v_min[1],
+	.pix_align		= &gsc_v_align[1],
+	.in_buf_cnt		= 4,
+	.out_buf_cnt		= 16,
+	.sc_up_max		= 8,
+	.sc_down_max		= 16,
+	.poly_sc_down_max	= 4,
+	.pre_sc_down_max	= 4,
+	.local_sc_down		= 4,
+};
+
+static struct gsc_driverdata gsc_v_100_drvdata = {
+	.variant = {
+		[0] = &gsc_v_100_variant,
+		[1] = &gsc_v_100_variant,
+		[2] = &gsc_v_100_variant,
+		[3] = &gsc_v_100_variant,
+	},
+	.num_entities = 4,
+};
+
+static struct gsc_driverdata gsc_v_200_drvdata = {
+	.variant = {
+		[0] = &gsc_v_200_variant,
+		[1] = &gsc_v_200_variant,
+		[2] = &gsc_v_200_variant,
+		[3] = &gsc_v_200_variant,
+	},
+	.num_entities = 4,
+};
+
+static struct platform_device_id gsc_driver_ids[] = {
+	{
+		.name		= "exynos-gsc",
+		.driver_data	= (unsigned long)&gsc_v_100_drvdata,
+	},
+	{
+		.name		= "exynos5250-gsc",
+		.driver_data	= (unsigned long)&gsc_v_200_drvdata,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(platform, gsc_driver_ids);
+
+static struct platform_driver gsc_driver = {
+	.probe		= gsc_probe,
+	.remove	= __devexit_p(gsc_remove),
+	.id_table	= gsc_driver_ids,
+	.driver = {
+		.name	= GSC_MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &gsc_pm_ops,
+	}
+};
+
+static int __init gsc_init(void)
+{
+	int ret = platform_driver_register(&gsc_driver);
+	if (ret)
+		gsc_err("platform_driver_register failed: %d\n", ret);
+	return ret;
+}
+
+static void __exit gsc_exit(void)
+{
+	platform_driver_unregister(&gsc_driver);
+}
+
+module_init(gsc_init);
+module_exit(gsc_exit);
+
+MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>");
+MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/gsc/gsc-core.h b/drivers/media/video/exynos/gsc/gsc-core.h
new file mode 100644
index 0000000..25fee4a
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-core.h
@@ -0,0 +1,828 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * header file for Samsung EXYNOS5 SoC series G-scaler driver
+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef GSC_CORE_H_
+#define GSC_CORE_H_
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <mach/videonode.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+#include <media/exynos_mc.h>
+#include <media/exynos_gscaler.h>
+#include "regs-gsc.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+extern const int h_coef_8t[7][16][8];
+extern const int v_coef_4t[7][16][4];
+extern int gsc_dbg;
+
+#define gsc_info(fmt, args...)						\
+	do {								\
+		if (gsc_dbg >= 6)						\
+			printk(KERN_INFO "[INFO]%s:%d: "fmt "\n",	\
+				__func__, __LINE__, ##args);		\
+	} while (0)
+
+#define gsc_err(fmt, args...)						\
+	do {								\
+		if (gsc_dbg >= 3)						\
+			printk(KERN_ERR "[ERROR]%s:%d: "fmt "\n",	\
+				__func__, __LINE__, ##args);		\
+	} while (0)
+
+#define gsc_warn(fmt, args...)						\
+	do {								\
+		if (gsc_dbg >= 4)						\
+			printk(KERN_WARNING "[WARN]%s:%d: "fmt "\n",	\
+				__func__, __LINE__, ##args);		\
+	} while (0)
+
+#define gsc_dbg(fmt, args...)						\
+	do {								\
+		if (gsc_dbg >= 7)						\
+			printk(KERN_DEBUG "[DEBUG]%s:%d: "fmt "\n",	\
+				__func__, __LINE__, ##args);		\
+	} while (0)
+
+#define GSC_MAX_CLOCKS			3
+#define GSC_SHUTDOWN_TIMEOUT		((100*HZ)/1000)
+#define GSC_MAX_DEVS			4
+#define WORKQUEUE_NAME_SIZE		32
+#define FIMD_NAME_SIZE			32
+#define GSC_M2M_BUF_NUM			0
+#define GSC_OUT_BUF_MAX			2
+#define GSC_MAX_CTRL_NUM		16
+#define GSC_OUT_MAX_MASK_NUM		7
+#define GSC_OUT_DEF_SRC			15
+#define GSC_OUT_DEF_DST			7
+#define DEFAULT_GSC_SINK_WIDTH		800
+#define DEFAULT_GSC_SINK_HEIGHT		480
+#define DEFAULT_GSC_SOURCE_WIDTH	800
+#define DEFAULT_GSC_SOURCE_HEIGHT	480
+#define DEFAULT_CSC_EQ			1
+#define DEFAULT_CSC_RANGE		1
+#define DEFAULT_USE_SYSMMU		1
+
+#define GSC_LAST_DEV_ID			3
+#define GSC_PAD_SINK			0
+#define GSC_PAD_SOURCE			1
+#define GSC_PADS_NUM			2
+
+#define	GSC_PARAMS			(1 << 0)
+#define	GSC_SRC_FMT			(1 << 1)
+#define	GSC_DST_FMT			(1 << 2)
+#define	GSC_CTX_M2M			(1 << 3)
+#define	GSC_CTX_OUTPUT			(1 << 4)
+#define	GSC_CTX_START			(1 << 5)
+#define	GSC_CTX_STOP_REQ		(1 << 6)
+#define	GSC_CTX_CAP			(1 << 10)
+
+#define GSC_SC_UP_MAX_RATIO		65536
+#define GSC_SC_DOWN_RATIO_7_8		74898
+#define GSC_SC_DOWN_RATIO_6_8		87381
+#define GSC_SC_DOWN_RATIO_5_8		104857
+#define GSC_SC_DOWN_RATIO_4_8		131072
+#define GSC_SC_DOWN_RATIO_3_8		174762
+#define GSC_SC_DOWN_RATIO_2_8		262144
+
+enum gsc_dev_flags {
+	/* for global */
+	ST_PWR_ON,
+	ST_STOP_REQ,
+	/* for m2m node */
+	ST_M2M_OPEN,
+	ST_M2M_RUN,
+	/* for output node */
+	ST_OUTPUT_OPEN,
+	ST_OUTPUT_STREAMON,
+	/* for capture node */
+	ST_CAPT_OPEN,
+	ST_CAPT_PEND,
+	ST_CAPT_RUN,
+	ST_CAPT_STREAM,
+	ST_CAPT_PIPE_STREAM,
+	ST_CAPT_SUSPENDED,
+	ST_CAPT_SHUT,
+	ST_CAPT_APPLY_CFG,
+	ST_CAPT_JPEG,
+};
+
+enum gsc_cap_input_entity {
+	GSC_IN_NONE,
+	GSC_IN_FLITE_PREVIEW,
+	GSC_IN_FLITE_CAMCORDING,
+	GSC_IN_FIMD_WRITEBACK,
+};
+
+enum gsc_irq {
+	GSC_OR_IRQ = 17,
+	GSC_DONE_IRQ = 16,
+};
+
+enum gsc_clk_status {
+	GSC_CLK_OFF,
+	GSC_CLK_ON,
+};
+
+/**
+ * enum gsc_datapath - the path of data used for gscaler
+ * @GSC_CAMERA: from camera
+ * @GSC_DMA: from/to DMA
+ * @GSC_LOCAL: to local path
+ * @GSC_WRITEBACK: from FIMD
+ */
+enum gsc_datapath {
+	GSC_CAMERA = 0x1,
+	GSC_DMA,
+	GSC_MIXER,
+	GSC_FIMD,
+	GSC_WRITEBACK,
+};
+
+enum gsc_yuv_fmt {
+	GSC_LSB_Y = 0x10,
+	GSC_LSB_C,
+	GSC_CBCR = 0x20,
+	GSC_CRCB,
+};
+
+#define fh_to_ctx(__fh) container_of(__fh, struct gsc_ctx, fh)
+
+#define is_rgb(img) ((img == V4L2_PIX_FMT_RGB565X) | (img == V4L2_PIX_FMT_RGB32))
+#define is_yuv422(img) ((img == V4L2_PIX_FMT_YUYV) | (img == V4L2_PIX_FMT_UYVY) | \
+		     (img == V4L2_PIX_FMT_VYUY) | (img == V4L2_PIX_FMT_YVYU) | \
+		     (img == V4L2_PIX_FMT_YUV422P) | (img == V4L2_PIX_FMT_NV16) | \
+		     (img == V4L2_PIX_FMT_NV61))
+#define is_yuv420(img) ((img == V4L2_PIX_FMT_YUV420) | (img == V4L2_PIX_FMT_YVU420) | \
+		     (img == V4L2_PIX_FMT_NV12) | (img == V4L2_PIX_FMT_NV21) | \
+		     (img == V4L2_PIX_FMT_NV12M) | (img == V4L2_PIX_FMT_NV21M) | \
+		     (img == V4L2_PIX_FMT_YUV420M) | (img == V4L2_PIX_FMT_YVU420M) | \
+		     (img == V4L2_PIX_FMT_NV12MT_16X16))
+#define is_AYV12(img) (img == V4L2_PIX_FMT_YVU420M)
+
+#define gsc_m2m_run(dev) test_bit(ST_M2M_RUN, &(dev)->state)
+#define gsc_m2m_opened(dev) test_bit(ST_M2M_OPEN, &(dev)->state)
+#define gsc_out_run(dev) test_bit(ST_OUTPUT_STREAMON, &(dev)->state)
+#define gsc_out_opened(dev) test_bit(ST_OUTPUT_OPEN, &(dev)->state)
+#define gsc_cap_opened(dev) test_bit(ST_CAPT_OPEN, &(dev)->state)
+#define gsc_cap_active(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
+
+#define ctrl_to_ctx(__ctrl) \
+	container_of((__ctrl)->handler, struct gsc_ctx, ctrl_handler)
+#define entity_data_to_gsc(data) \
+	container_of(data, struct gsc_dev, md_data)
+#define gsc_capture_get_frame(ctx, pad)\
+	((pad == GSC_PAD_SINK) ? &ctx->s_frame : &ctx->d_frame)
+/**
+ * struct gsc_fmt - the driver's internal color format data
+ * @mbus_code: Media Bus pixel code, -1 if not applicable
+ * @name: format description
+ * @pixelformat: the fourcc code for this format, 0 if not applicable
+ * @yorder: Y/C order
+ * @corder: Chrominance order control
+ * @num_planes: number of physically non-contiguous data planes
+ * @nr_comp: number of physically contiguous data planes
+ * @depth: per plane driver's private 'number of bits per pixel'
+ * @flags: flags indicating which operation mode format applies to
+ */
+struct gsc_fmt {
+	enum v4l2_mbus_pixelcode mbus_code;
+	char	*name;
+	u32	pixelformat;
+	u32	yorder;
+	u32	corder;
+	u16	num_planes;
+	u16	nr_comp;
+	u8	depth[VIDEO_MAX_PLANES];
+	u32	flags;
+};
+
+/**
+ * struct gsc_input_buf - the driver's video buffer
+ * @vb:	videobuf2 buffer
+ * @list : linked list structure for buffer queue
+ * @idx : index of G-Scaler input buffer
+ */
+struct gsc_input_buf {
+	struct vb2_buffer	vb;
+	struct list_head	list;
+	int			idx;
+};
+
+/**
+ * struct gsc_addr - the G-Scaler physical address set
+ * @y:	 luminance plane address
+ * @cb:	 Cb plane address
+ * @cr:	 Cr plane address
+ */
+struct gsc_addr {
+	dma_addr_t	y;
+	dma_addr_t	cb;
+	dma_addr_t	cr;
+};
+
+/* struct gsc_ctrls - the G-Scaler control set
+ * @rotate: rotation degree
+ * @hflip: horizontal flip
+ * @vflip: vertical flip
+ * @global_alpha: the alpha value of current frame
+ * @cacheable: cacheability of current frame
+ * @layer_blend_en: enable mixer layer alpha blending
+ * @layer_alpha: set alpha value for mixer layer
+ * @pixel_blend_en: enable mixer pixel alpha blending
+ * @chroma_en: enable chromakey
+ * @chroma_val:	set value for chromakey
+ * @csc_eq_mode: mode to select csc equation of current frame
+ * @csc_eq: csc equation of current frame
+ * @csc_range: csc range of current frame
+ */
+struct gsc_ctrls {
+	struct v4l2_ctrl	*rotate;
+	struct v4l2_ctrl	*hflip;
+	struct v4l2_ctrl	*vflip;
+	struct v4l2_ctrl	*global_alpha;
+	struct v4l2_ctrl	*cacheable;
+	struct v4l2_ctrl	*layer_blend_en;
+	struct v4l2_ctrl	*layer_alpha;
+	struct v4l2_ctrl	*pixel_blend_en;
+	struct v4l2_ctrl	*chroma_en;
+	struct v4l2_ctrl	*chroma_val;
+	struct v4l2_ctrl	*prio;
+	struct v4l2_ctrl	*csc_eq_mode;
+	struct v4l2_ctrl	*csc_eq;
+	struct v4l2_ctrl	*csc_range;
+	struct v4l2_ctrl	*m2m_ctx_num;
+	struct v4l2_ctrl	*use_sysmmu;
+};
+
+/**
+ * struct gsc_scaler - the configuration data for G-Scaler inetrnal scaler
+ * @pre_shfactor:	pre sclaer shift factor
+ * @pre_hratio:		horizontal ratio of the prescaler
+ * @pre_vratio:		vertical ratio of the prescaler
+ * @main_hratio:	the main scaler's horizontal ratio
+ * @main_vratio:	the main scaler's vertical ratio
+ */
+struct gsc_scaler {
+	u32	pre_shfactor;
+	u32	pre_hratio;
+	u32	pre_vratio;
+	unsigned long main_hratio;
+	unsigned long main_vratio;
+};
+
+struct gsc_dev;
+
+struct gsc_ctx;
+
+/**
+ * struct gsc_frame - source/target frame properties
+ * @f_width:	SRC : SRCIMG_WIDTH, DST : OUTPUTDMA_WHOLE_IMG_WIDTH
+ * @f_height:	SRC : SRCIMG_HEIGHT, DST : OUTPUTDMA_WHOLE_IMG_HEIGHT
+ * @crop:	cropped(source)/scaled(destination) size
+ * @payload:	image size in bytes (w x h x bpp)
+ * @addr:	image frame buffer physical addresses
+ * @fmt:	G-scaler color format pointer
+ * @cacheable:	frame's cacheability
+ * @alph:	frame's alpha value
+ */
+struct gsc_frame {
+	u32	f_width;
+	u32	f_height;
+	struct v4l2_rect	crop;
+	unsigned long payload[VIDEO_MAX_PLANES];
+	struct gsc_addr		addr;
+	struct gsc_fmt		*fmt;
+	bool			cacheable;
+	u8	alpha;
+};
+
+struct gsc_sensor_info {
+	struct exynos_isp_info *pdata;
+	struct v4l2_subdev *sd;
+	struct clk *camclk;
+};
+
+struct gsc_capture_device {
+	struct gsc_ctx			*ctx;
+	struct video_device		*vfd;
+	struct v4l2_subdev		*sd_cap;
+	struct v4l2_subdev		*sd_disp;
+	struct v4l2_subdev		*sd_flite[FLITE_MAX_ENTITIES];
+	struct v4l2_subdev		*sd_csis[CSIS_MAX_ENTITIES];
+	struct gsc_sensor_info		sensor[SENSOR_MAX_ENTITIES];
+	struct media_pad		vd_pad;
+	struct media_pad		sd_pads[GSC_PADS_NUM];
+	struct v4l2_mbus_framefmt	mbus_fmt[GSC_PADS_NUM];
+	struct vb2_queue		vbq;
+	int				active_buf_cnt;
+	int				buf_index;
+	int				input_index;
+	int				refcnt;
+	u32				frame_cnt;
+	u32				reqbufs_cnt;
+	enum gsc_cap_input_entity	input;
+	u32				cam_index;
+	bool				user_subdev_api;
+};
+
+/**
+ * struct gsc_output_device - v4l2 output device data
+ * @vfd: the video device node for v4l2 output mode
+ * @alloc_ctx: v4l2 memory-to-memory device data
+ * @ctx: hardware context data
+ * @sd: v4l2 subdev pointer of gscaler
+ * @vbq: videobuf2 queue of gscaler output device
+ * @vb_pad: the pad of gscaler video entity
+ * @sd_pads: pads of gscaler subdev entity
+ * @active_buf_q: linked list structure of input buffer
+ * @req_cnt: the number of requested buffer
+ */
+struct gsc_output_device {
+	struct video_device	*vfd;
+	struct vb2_alloc_ctx	*alloc_ctx;
+	struct gsc_ctx		*ctx;
+	struct v4l2_subdev	*sd;
+	struct vb2_queue	vbq;
+	struct media_pad	vd_pad;
+	struct media_pad	sd_pads[GSC_PADS_NUM];
+	struct list_head	active_buf_q;
+	int			req_cnt;
+};
+
+/**
+ * struct gsc_m2m_device - v4l2 memory-to-memory device data
+ * @vfd: the video device node for v4l2 m2m mode
+ * @m2m_dev: v4l2 memory-to-memory device data
+ * @ctx: hardware context data
+ * @refcnt: the reference counter
+ */
+struct gsc_m2m_device {
+	struct video_device	*vfd;
+	struct v4l2_m2m_dev	*m2m_dev;
+	struct gsc_ctx		*ctx;
+	int			refcnt;
+};
+
+/**
+ *  struct gsc_pix_max - image pixel size limits in various IP configurations
+ *
+ *  @org_scaler_bypass_w: max pixel width when the scaler is disabled
+ *  @org_scaler_bypass_h: max pixel height when the scaler is disabled
+ *  @org_scaler_input_w: max pixel width when the scaler is enabled
+ *  @org_scaler_input_h: max pixel height when the scaler is enabled
+ *  @real_rot_dis_w: max pixel src cropped height with the rotator is off
+ *  @real_rot_dis_h: max pixel src croppped width with the rotator is off
+ *  @real_rot_en_w: max pixel src cropped width with the rotator is on
+ *  @real_rot_en_h: max pixel src cropped height with the rotator is on
+ *  @target_rot_dis_w: max pixel dst scaled width with the rotator is off
+ *  @target_rot_dis_h: max pixel dst scaled height with the rotator is off
+ *  @target_rot_en_w: max pixel dst scaled width with the rotator is on
+ *  @target_rot_en_h: max pixel dst scaled height with the rotator is on
+ */
+struct gsc_pix_max {
+	u16 org_scaler_bypass_w;
+	u16 org_scaler_bypass_h;
+	u16 org_scaler_input_w;
+	u16 org_scaler_input_h;
+	u16 real_rot_dis_w;
+	u16 real_rot_dis_h;
+	u16 real_rot_en_w;
+	u16 real_rot_en_h;
+	u16 target_rot_dis_w;
+	u16 target_rot_dis_h;
+	u16 target_rot_en_w;
+	u16 target_rot_en_h;
+};
+
+/**
+ *  struct gsc_pix_min - image pixel size limits in various IP configurations
+ *
+ *  @org_w: minimum source pixel width
+ *  @org_h: minimum source pixel height
+ *  @real_w: minimum input crop pixel width
+ *  @real_h: minimum input crop pixel height
+ *  @target_rot_dis_w: minimum output scaled pixel height when rotator is off
+ *  @target_rot_dis_h: minimum output scaled pixel height when rotator is off
+ *  @target_rot_en_w: minimum output scaled pixel height when rotator is on
+ *  @target_rot_en_h: minimum output scaled pixel height when rotator is on
+ */
+struct gsc_pix_min {
+	u16 org_w;
+	u16 org_h;
+	u16 real_w;
+	u16 real_h;
+	u16 target_rot_dis_w;
+	u16 target_rot_dis_h;
+	u16 target_rot_en_w;
+	u16 target_rot_en_h;
+};
+
+struct gsc_pix_align {
+	u16 org_h;
+	u16 org_w;
+	u16 offset_h;
+	u16 real_w;
+	u16 real_h;
+	u16 target_w;
+	u16 target_h;
+};
+
+/**
+ * struct gsc_variant - G-Scaler variant information
+ */
+struct gsc_variant {
+	struct gsc_pix_max *pix_max;
+	struct gsc_pix_min *pix_min;
+	struct gsc_pix_align *pix_align;
+	u16		in_buf_cnt;
+	u16		out_buf_cnt;
+	u16		sc_up_max;
+	u16		sc_down_max;
+	u16		poly_sc_down_max;
+	u16		pre_sc_down_max;
+	u16		local_sc_down;
+};
+
+/**
+ * struct gsc_driverdata - per device type driver data for init time.
+ *
+ * @variant: the variant information for this driver.
+ * @num_entities: the number of g-scalers
+ */
+struct gsc_driverdata {
+	struct gsc_variant *variant[GSC_MAX_DEVS];
+	int		num_entities;
+};
+
+struct gsc_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct gsc_dev *gsc);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+	bool use_sysmmu;
+};
+
+struct gsc_pipeline {
+	struct media_pipeline *pipe;
+	struct v4l2_subdev *sd_gsc;
+	struct v4l2_subdev *disp;
+	struct v4l2_subdev *flite;
+	struct v4l2_subdev *csis;
+	struct v4l2_subdev *sensor;
+};
+
+/**
+ * struct gsc_dev - abstraction for G-Scaler entity
+ * @slock:	the spinlock protecting this data structure
+ * @lock:	the mutex protecting this data structure
+ * @pdev:	pointer to the G-Scaler platform device
+ * @variant:	the IP variant information
+ * @id:		g_scaler device index (0..GSC_MAX_DEVS)
+ * @regs:	the mapped hardware registers
+ * @regs_res:	the resource claimed for IO registers
+ * @irq:	G-scaler interrupt number
+ * @irq_queue:	interrupt handler waitqueue
+ * @m2m:	memory-to-memory V4L2 device information
+ * @out:	memory-to-local V4L2 output device information
+ * @state:	flags used to synchronize m2m and capture mode operation
+ * @alloc_ctx:	videobuf2 memory allocator context
+ * @vb2:	videobuf2 memory allocator call-back functions
+ * @mdev:	pointer to exynos media device
+ * @pipeline:	pointer to subdevs that are connected with gscaler
+ */
+struct gsc_dev {
+	spinlock_t			slock;
+	struct mutex			lock;
+	struct platform_device		*pdev;
+	struct gsc_variant		*variant;
+	u16				id;
+	struct clk			*clock;
+	atomic_t			clk_cnt;
+	void __iomem			*regs;
+	struct resource			*regs_res;
+	int				irq;
+	wait_queue_head_t		irq_queue;
+	struct work_struct		work_struct;
+	struct gsc_m2m_device		m2m;
+	struct gsc_output_device	out;
+	struct gsc_capture_device	cap;
+	struct exynos_platform_gscaler	*pdata;
+	unsigned long			state;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	const struct gsc_vb2		*vb2;
+	struct exynos_md		*mdev[2];
+	struct gsc_pipeline		pipeline;
+	struct exynos_entity_data	md_data;
+};
+
+/**
+ * gsc_ctx - the device context data
+ * @slock:		spinlock protecting this data structure
+ * @s_frame:		source frame properties
+ * @d_frame:		destination frame properties
+ * @in_path:		input mode (DMA or camera)
+ * @out_path:		output mode (DMA or FIFO)
+ * @scaler:		image scaler properties
+ * @flags:		additional flags for image conversion
+ * @state:		flags to keep track of user configuration
+ * @gsc_dev:		the g-scaler device this context applies to
+ * @m2m_ctx:		memory-to-memory device context
+ * @fh:                 v4l2 file handle
+ * @ctrl_handler:       v4l2 controls handler
+ * @ctrls_rdy:          true if the control handler is initialized
+ * @gsc_ctrls		G-Scaler control set
+ * @m2m_ctx:		memory-to-memory device context
+ */
+struct gsc_ctx {
+	spinlock_t		slock;
+	struct gsc_frame	s_frame;
+	struct gsc_frame	d_frame;
+	enum gsc_datapath	in_path;
+	enum gsc_datapath	out_path;
+	struct gsc_scaler	scaler;
+	u32			flags;
+	u32			state;
+	struct gsc_dev		*gsc_dev;
+	struct v4l2_m2m_ctx	*m2m_ctx;
+	struct v4l2_fh		fh;
+	struct v4l2_ctrl_handler ctrl_handler;
+	struct gsc_ctrls	gsc_ctrls;
+	struct timer_list	op_timer;
+	bool			ctrls_rdy;
+};
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct gsc_vb2 gsc_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct gsc_vb2 gsc_vb2_ion;
+#endif
+
+void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame frm);
+void gsc_clock_gating(struct gsc_dev *gsc, enum gsc_clk_status status);
+void gsc_clk_release(struct gsc_dev *gsc);
+int gsc_register_m2m_device(struct gsc_dev *gsc);
+void gsc_unregister_m2m_device(struct gsc_dev *gsc);
+int gsc_register_output_device(struct gsc_dev *gsc);
+void gsc_unregister_output_device(struct gsc_dev *gsc);
+int gsc_register_capture_device(struct gsc_dev *gsc);
+void gsc_unregister_capture_device(struct gsc_dev *gsc);
+
+u32 get_plane_size(struct gsc_frame *fr, unsigned int plane);
+char gsc_total_fmts(void);
+struct gsc_fmt *get_format(int index);
+struct gsc_fmt *find_format(u32 *pixelformat, u32 *mbus_code, int index);
+int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f);
+int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f);
+void gsc_set_frame_size(struct gsc_frame *frame, int width, int height);
+int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f);
+void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h);
+int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr);
+int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr);
+int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst, u32 *ratio);
+void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh);
+void gsc_check_src_scale_info(struct gsc_variant *var, struct gsc_frame *s_frame,
+			      u32 *wratio, u32 tx, u32 ty, u32 *hratio, int rot);
+int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
+			   int dh, int rot, int out_path);
+int gsc_set_scaler_info(struct gsc_ctx *ctx);
+int gsc_ctrls_create(struct gsc_ctx *ctx);
+void gsc_ctrls_delete(struct gsc_ctx *ctx);
+int gsc_out_hw_set(struct gsc_ctx *ctx);
+int gsc_out_set_in_addr(struct gsc_dev *gsc, struct gsc_ctx *ctx,
+		   struct gsc_input_buf *buf, int index);
+int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
+		     struct gsc_frame *frame, struct gsc_addr *addr);
+int gsc_out_link_validate(const struct media_pad *source,
+			  const struct media_pad *sink);
+int gsc_pipeline_s_stream(struct gsc_dev *gsc, bool on);
+
+static inline void gsc_ctx_state_lock_set(u32 state, struct gsc_ctx *ctx)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctx->slock, flags);
+	ctx->state |= state;
+	spin_unlock_irqrestore(&ctx->slock, flags);
+}
+
+static inline void gsc_ctx_state_lock_clear(u32 state, struct gsc_ctx *ctx)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctx->slock, flags);
+	ctx->state &= ~state;
+	spin_unlock_irqrestore(&ctx->slock, flags);
+}
+
+static inline int get_win_num(struct gsc_dev *dev)
+{
+	return (dev->id == 3) ? 2 : dev->id;
+}
+
+static inline int is_tiled(struct gsc_fmt *fmt)
+{
+	return fmt->pixelformat == V4L2_PIX_FMT_NV12MT_16X16;
+}
+
+static inline int is_output(enum v4l2_buf_type type)
+{
+	return (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||
+		type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ? 1 : 0;
+}
+
+static inline void gsc_hw_enable_control(struct gsc_dev *dev, bool on)
+{
+	u32 cfg = readl(dev->regs + GSC_ENABLE);
+
+	if (on)
+		cfg |= GSC_ENABLE_ON;
+	else
+		cfg &= ~GSC_ENABLE_ON;
+
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+static inline int gsc_hw_get_curr_in_buf_idx(struct gsc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	return GSC_IN_CURR_GET_INDEX(cfg);
+}
+
+static inline int gsc_hw_get_irq_status(struct gsc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + GSC_IRQ);
+	if (cfg & (1 << GSC_OR_IRQ))
+		return GSC_OR_IRQ;
+	else
+		return GSC_DONE_IRQ;
+
+}
+
+static inline void gsc_hw_clear_irq(struct gsc_dev *dev, int irq)
+{
+	u32 cfg = readl(dev->regs + GSC_IRQ);
+	if (irq == GSC_OR_IRQ)
+		cfg |= GSC_IRQ_STATUS_OR_IRQ;
+	else if (irq == GSC_DONE_IRQ)
+		cfg |= GSC_IRQ_STATUS_OR_FRM_DONE;
+	writel(cfg, dev->regs + GSC_IRQ);
+}
+
+static inline void gsc_lock(struct vb2_queue *vq)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_lock(&ctx->gsc_dev->lock);
+}
+
+static inline void gsc_unlock(struct vb2_queue *vq)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_unlock(&ctx->gsc_dev->lock);
+}
+
+static inline bool gsc_ctx_state_is_set(u32 mask, struct gsc_ctx *ctx)
+{
+	unsigned long flags;
+	bool ret;
+
+	spin_lock_irqsave(&ctx->slock, flags);
+	ret = (ctx->state & mask) == mask;
+	spin_unlock_irqrestore(&ctx->slock, flags);
+	return ret;
+}
+
+static inline struct gsc_frame *ctx_get_frame(struct gsc_ctx *ctx,
+					      enum v4l2_buf_type type)
+{
+	struct gsc_frame *frame;
+
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
+		frame = &ctx->s_frame;
+	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
+		frame = &ctx->d_frame;
+	} else {
+		gsc_err("Wrong buffer/video queue type (%d)", type);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return frame;
+}
+
+static inline struct gsc_input_buf *
+active_queue_pop(struct gsc_output_device *vid_out, struct gsc_dev *dev)
+{
+	struct gsc_input_buf *buf;
+
+	buf = list_entry(vid_out->active_buf_q.next, struct gsc_input_buf, list);
+	return buf;
+}
+
+static inline void active_queue_push(struct gsc_output_device *vid_out,
+				     struct gsc_input_buf *buf, struct gsc_dev *dev)
+{
+	list_add_tail(&buf->list, &vid_out->active_buf_q);
+}
+
+static inline struct gsc_dev *entity_to_gsc(struct media_entity *me)
+{
+	struct v4l2_subdev *sd;
+
+	sd = container_of(me, struct v4l2_subdev, entity);
+	return entity_data_to_gsc(v4l2_get_subdevdata(sd));
+}
+
+static inline void update_ctrl_value(struct v4l2_ctrl *ctrl, s32 value)
+{
+	ctrl->cur.val = ctrl->val = value;
+}
+
+static inline void update_use_sysmmu(const struct gsc_vb2 *vb2,
+				     struct v4l2_ctrl *ctrl)
+{
+	bool *use_sysmmu = (bool *)&vb2->use_sysmmu;
+	*use_sysmmu = ctrl->cur.val;
+}
+
+void gsc_hw_set_sw_reset(struct gsc_dev *dev);
+void gsc_hw_set_one_frm_mode(struct gsc_dev *dev, bool mask);
+void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask);
+void gsc_hw_set_overflow_irq_mask(struct gsc_dev *dev, bool mask);
+void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask);
+void gsc_hw_set_input_buf_mask_all(struct gsc_dev *dev);
+void gsc_hw_set_output_buf_mask_all(struct gsc_dev *dev);
+void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
+void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
+void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr, int index);
+void gsc_hw_set_output_addr(struct gsc_dev *dev, struct gsc_addr *addr, int index);
+void gsc_hw_set_freerun_clock_mode(struct gsc_dev *dev, bool mask);
+void gsc_hw_set_input_path(struct gsc_ctx *ctx);
+void gsc_hw_set_in_size(struct gsc_ctx *ctx);
+void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx);
+void gsc_hw_set_in_image_format(struct gsc_ctx *ctx);
+void gsc_hw_set_output_path(struct gsc_ctx *ctx);
+void gsc_hw_set_out_size(struct gsc_ctx *ctx);
+void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx);
+void gsc_hw_set_out_image_format(struct gsc_ctx *ctx);
+void gsc_hw_set_prescaler(struct gsc_ctx *ctx);
+void gsc_hw_set_mainscaler(struct gsc_ctx *ctx);
+void gsc_hw_set_rotation(struct gsc_ctx *ctx);
+void gsc_hw_set_global_alpha(struct gsc_ctx *ctx);
+void gsc_hw_set_sfr_update(struct gsc_ctx *ctx);
+void gsc_hw_set_local_dst(int id, int out, bool on);
+void gsc_hw_set_mixer(void);
+void gsc_hw_set_sysreg_writeback(struct gsc_ctx *ctx);
+void gsc_hw_set_pxlasync_camif_lo_mask(struct gsc_dev *dev, bool on);
+void gsc_hw_set_h_coef(struct gsc_ctx *ctx);
+void gsc_hw_set_v_coef(struct gsc_ctx *ctx);
+void gsc_hw_set_in_pingpong_update(struct gsc_dev *dev);
+void gsc_hw_set_in_chrom_stride(struct gsc_ctx *ctx);
+void gsc_hw_set_out_chrom_stride(struct gsc_ctx *ctx);
+void gsc_hw_set_fire_bit_sync_mode(struct gsc_dev *dev, bool mask);
+
+int gsc_hw_get_input_buf_mask_status(struct gsc_dev *dev);
+int gsc_hw_get_done_input_buf_index(struct gsc_dev *dev);
+int gsc_hw_get_done_output_buf_index(struct gsc_dev *dev);
+int gsc_hw_get_nr_unmask_bits(struct gsc_dev *dev);
+int gsc_hw_get_mxr_path_status(void);
+int gsc_wait_reset(struct gsc_dev *dev);
+int gsc_wait_operating(struct gsc_dev *dev);
+int gsc_wait_stop(struct gsc_dev *dev);
+
+void gsc_disp_fifo_sw_reset(struct gsc_dev *dev);
+void gsc_pixelasync_sw_reset(struct gsc_dev *dev);
+
+
+#endif /* GSC_CORE_H_ */
diff --git a/drivers/media/video/exynos/gsc/gsc-m2m.c b/drivers/media/video/exynos/gsc/gsc-m2m.c
new file mode 100644
index 0000000..8b415bc
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-m2m.c
@@ -0,0 +1,750 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-m2m.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series G-scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <media/v4l2-ioctl.h>
+
+#include "gsc-core.h"
+
+static int gsc_ctx_stop_req(struct gsc_ctx *ctx)
+{
+	struct gsc_ctx *curr_ctx;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret = 0;
+
+	curr_ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
+	if (!gsc_m2m_run(gsc) || (curr_ctx != ctx))
+		return 0;
+	ctx->state |= GSC_CTX_STOP_REQ;
+	ret = wait_event_timeout(gsc->irq_queue,
+			!gsc_ctx_state_is_set(GSC_CTX_STOP_REQ, ctx),
+			GSC_SHUTDOWN_TIMEOUT);
+	if (!ret)
+		ret = -EBUSY;
+
+	return ret;
+}
+
+static int gsc_m2m_stop_streaming(struct vb2_queue *q)
+{
+	struct gsc_ctx *ctx = q->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret;
+
+	ret = gsc_ctx_stop_req(ctx);
+	/* FIXME: need to add v4l2_m2m_job_finish(fail) if ret is timeout */
+	if (ret < 0)
+		dev_err(&gsc->pdev->dev, "wait timeout : %s\n", __func__);
+
+	v4l2_m2m_get_next_job(gsc->m2m.m2m_dev, ctx->m2m_ctx);
+
+	return 0;
+}
+
+static void gsc_m2m_job_abort(void *priv)
+{
+	struct gsc_ctx *ctx = priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret;
+
+	ret = gsc_ctx_stop_req(ctx);
+	/* FIXME: need to add v4l2_m2m_job_finish(fail) if ret is timeout */
+	if (ret < 0)
+		dev_err(&gsc->pdev->dev, "wait timeout : %s\n", __func__);
+
+	v4l2_m2m_get_next_job(gsc->m2m.m2m_dev, ctx->m2m_ctx);
+}
+
+int gsc_fill_addr(struct gsc_ctx *ctx)
+{
+	struct gsc_frame *s_frame, *d_frame;
+	struct vb2_buffer *vb = NULL;
+	int ret = 0;
+
+	s_frame = &ctx->s_frame;
+	d_frame = &ctx->d_frame;
+
+	vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
+	ret = gsc_prepare_addr(ctx, vb, s_frame, &s_frame->addr);
+	if (ret)
+		return ret;
+
+	vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
+	ret = gsc_prepare_addr(ctx, vb, d_frame, &d_frame->addr);
+
+	return ret;
+}
+
+void gsc_op_timer_handler(unsigned long arg)
+{
+	struct gsc_ctx *ctx = (struct gsc_ctx *)arg;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct vb2_buffer *src_vb, *dst_vb;
+
+	clear_bit(ST_M2M_RUN, &gsc->state);
+	gsc_clock_gating(gsc, GSC_CLK_OFF);
+	pm_runtime_put_sync(&gsc->pdev->dev);
+
+	src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+	dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+	if (src_vb && dst_vb) {
+		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
+		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
+	}
+	gsc_err("GSCALER interrupt hasn't been triggered");
+	gsc_err("erro ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
+}
+
+static void gsc_m2m_device_run(void *priv)
+{
+	struct gsc_ctx *ctx = priv;
+	struct gsc_dev *gsc;
+	unsigned long flags;
+	int ret;
+	bool is_set = false;
+
+	if (WARN(!ctx, "null hardware context\n"))
+		return;
+
+	gsc = ctx->gsc_dev;
+	pm_runtime_get_sync(&gsc->pdev->dev);
+	gsc_clock_gating(gsc, GSC_CLK_ON);
+
+	spin_lock_irqsave(&ctx->slock, flags);
+	/* Reconfigure hardware if the context has changed. */
+	if (gsc->m2m.ctx != ctx) {
+		gsc_dbg("gsc->m2m.ctx = 0x%p, current_ctx = 0x%p",
+			  gsc->m2m.ctx, ctx);
+		ctx->state |= GSC_PARAMS;
+		gsc->m2m.ctx = ctx;
+	}
+
+	is_set = (ctx->state & GSC_CTX_STOP_REQ) ? 1 : 0;
+	ctx->state &= ~GSC_CTX_STOP_REQ;
+	if (is_set) {
+		wake_up(&gsc->irq_queue);
+		goto put_device;
+	}
+
+	ret = gsc_fill_addr(ctx);
+	if (ret) {
+		gsc_err("Wrong address");
+		goto put_device;
+	}
+
+	if (gsc->vb2->use_sysmmu)
+		gsc_set_prefbuf(gsc, ctx->s_frame);
+
+	if (ctx->state & GSC_PARAMS) {
+		if (soc_is_exynos5250_rev1) {
+			gsc_hw_set_sw_reset(gsc);
+			ret = gsc_wait_reset(gsc);
+			if (ret < 0) {
+				gsc_err("gscaler s/w reset timeout");
+				goto put_device;
+			}
+		}
+		gsc_hw_set_input_buf_masking(gsc, GSC_M2M_BUF_NUM, false);
+		gsc_hw_set_output_buf_masking(gsc, GSC_M2M_BUF_NUM, false);
+		gsc_hw_set_frm_done_irq_mask(gsc, false);
+		gsc_hw_set_gsc_irq_enable(gsc, true);
+		gsc_hw_set_one_frm_mode(gsc, true);
+		gsc_hw_set_freerun_clock_mode(gsc, false);
+
+		if (gsc_set_scaler_info(ctx)) {
+			gsc_err("Scaler setup error");
+			goto put_device;
+		}
+
+		gsc_hw_set_input_path(ctx);
+		gsc_hw_set_in_size(ctx);
+		gsc_hw_set_in_image_format(ctx);
+
+		gsc_hw_set_output_path(ctx);
+		gsc_hw_set_out_size(ctx);
+		gsc_hw_set_out_image_format(ctx);
+
+		gsc_hw_set_prescaler(ctx);
+		gsc_hw_set_mainscaler(ctx);
+		gsc_hw_set_h_coef(ctx);
+		gsc_hw_set_v_coef(ctx);
+		gsc_hw_set_rotation(ctx);
+		gsc_hw_set_global_alpha(ctx);
+	}
+	/* When you update SFRs in the middle of operating
+	gsc_hw_set_sfr_update(ctx);
+	*/
+	gsc_hw_set_input_addr(gsc, &ctx->s_frame.addr, GSC_M2M_BUF_NUM);
+	gsc_hw_set_output_addr(gsc, &ctx->d_frame.addr, GSC_M2M_BUF_NUM);
+
+	ctx->state &= ~GSC_PARAMS;
+
+	if (!test_and_set_bit(ST_M2M_RUN, &gsc->state)) {
+		/* One frame mode sequence
+		 GSCALER_ON on -> GSCALER_OP_STATUS is operating ->
+		 GSCALER_ON off */
+		gsc_hw_enable_control(gsc, true);
+		ret = gsc_wait_operating(gsc);
+		if (ret < 0) {
+			gsc_err("gscaler wait operating timeout");
+			goto put_device;
+		}
+		if (!soc_is_exynos5250_rev1)
+			gsc_hw_enable_control(gsc, false);
+	}
+
+	ctx->op_timer.expires = (jiffies + 2 * HZ);
+	add_timer(&ctx->op_timer);
+
+	spin_unlock_irqrestore(&ctx->slock, flags);
+	return;
+
+put_device:
+	ctx->state &= ~GSC_PARAMS;
+	spin_unlock_irqrestore(&ctx->slock, flags);
+	pm_runtime_put_sync(&gsc->pdev->dev);
+}
+
+static int gsc_m2m_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+			       unsigned int *num_planes, unsigned long sizes[],
+			       void *allocators[])
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vq);
+	struct gsc_frame *frame;
+	int i;
+
+	frame = ctx_get_frame(ctx, vq->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	if (!frame->fmt)
+		return -EINVAL;
+
+	*num_planes = frame->fmt->num_planes;
+	for (i = 0; i < frame->fmt->num_planes; i++) {
+		sizes[i] = get_plane_size(frame, i);
+		allocators[i] = ctx->gsc_dev->alloc_ctx;
+	}
+	return 0;
+}
+
+static int gsc_m2m_buf_prepare(struct vb2_buffer *vb)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_frame *frame;
+	int i;
+
+	frame = ctx_get_frame(ctx, vb->vb2_queue->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	if (!V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
+		for (i = 0; i < frame->fmt->num_planes; i++)
+			vb2_set_plane_payload(vb, i, frame->payload[i]);
+	}
+
+	if (frame->cacheable)
+		gsc->vb2->cache_flush(vb, frame->fmt->num_planes);
+
+	return 0;
+}
+
+static void gsc_m2m_buf_queue(struct vb2_buffer *vb)
+{
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	gsc_dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
+
+	if (ctx->m2m_ctx)
+		v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
+}
+
+struct vb2_ops gsc_m2m_qops = {
+	.queue_setup	 = gsc_m2m_queue_setup,
+	.buf_prepare	 = gsc_m2m_buf_prepare,
+	.buf_queue	 = gsc_m2m_buf_queue,
+	.wait_prepare	 = gsc_unlock,
+	.wait_finish	 = gsc_lock,
+	.stop_streaming	 = gsc_m2m_stop_streaming,
+};
+
+static int gsc_m2m_querycap(struct file *file, void *fh,
+			   struct v4l2_capability *cap)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+
+	strncpy(cap->driver, gsc->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, gsc->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
+		V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+
+	return 0;
+}
+
+static int gsc_m2m_enum_fmt_mplane(struct file *file, void *priv,
+				struct v4l2_fmtdesc *f)
+{
+	return gsc_enum_fmt_mplane(f);
+}
+
+static int gsc_m2m_g_fmt_mplane(struct file *file, void *fh,
+			     struct v4l2_format *f)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+
+	if ((f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) &&
+	    (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
+		return -EINVAL;
+
+	return gsc_g_fmt_mplane(ctx, f);
+}
+
+static int gsc_m2m_try_fmt_mplane(struct file *file, void *fh,
+				  struct v4l2_format *f)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+
+	if ((f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) &&
+	    (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
+		return -EINVAL;
+
+	return gsc_try_fmt_mplane(ctx, f);
+}
+
+static int gsc_m2m_s_fmt_mplane(struct file *file, void *fh,
+				 struct v4l2_format *f)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	struct vb2_queue *vq;
+	struct gsc_frame *frame;
+	struct v4l2_pix_format_mplane *pix;
+	int i, ret = 0;
+
+	ret = gsc_m2m_try_fmt_mplane(file, fh, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+
+	if (vb2_is_streaming(vq)) {
+		gsc_err("queue (%d) busy", f->type);
+		return -EBUSY;
+	}
+
+	if (V4L2_TYPE_IS_OUTPUT(f->type)) {
+		frame = &ctx->s_frame;
+	} else {
+		frame = &ctx->d_frame;
+	}
+
+	pix = &f->fmt.pix_mp;
+	frame->fmt = find_format(&pix->pixelformat, NULL, 0);
+	if (!frame->fmt)
+		return -EINVAL;
+
+	for (i = 0; i < frame->fmt->num_planes; i++)
+		frame->payload[i] = pix->plane_fmt[i].sizeimage;
+
+	gsc_set_frame_size(frame, pix->width, pix->height);
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		gsc_ctx_state_lock_set(GSC_PARAMS | GSC_DST_FMT, ctx);
+	else
+		gsc_ctx_state_lock_set(GSC_PARAMS | GSC_SRC_FMT, ctx);
+
+	gsc_dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
+
+	return 0;
+}
+
+static int gsc_m2m_reqbufs(struct file *file, void *fh,
+			  struct v4l2_requestbuffers *reqbufs)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_frame *frame;
+	u32 max_cnt;
+
+	max_cnt = (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
+		gsc->variant->in_buf_cnt : gsc->variant->out_buf_cnt;
+
+	if (reqbufs->count > max_cnt)
+		return -EINVAL;
+	else if (reqbufs->count == 0) {
+		if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+			gsc_ctx_state_lock_clear(GSC_SRC_FMT, ctx);
+		else
+			gsc_ctx_state_lock_clear(GSC_DST_FMT, ctx);
+	}
+
+	update_use_sysmmu(gsc->vb2, ctx->gsc_ctrls.use_sysmmu);
+	frame = ctx_get_frame(ctx, reqbufs->type);
+	frame->cacheable = ctx->gsc_ctrls.cacheable->val;
+	gsc->vb2->set_cacheable(gsc->alloc_ctx, frame->cacheable);
+
+	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
+}
+
+static int gsc_m2m_querybuf(struct file *file, void *fh,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
+}
+
+static int gsc_m2m_qbuf(struct file *file, void *fh,
+			  struct v4l2_buffer *buf)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int gsc_m2m_dqbuf(struct file *file, void *fh,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int gsc_m2m_streamon(struct file *file, void *fh,
+			   enum v4l2_buf_type type)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+
+	/* The source and target color format need to be set */
+	if (V4L2_TYPE_IS_OUTPUT(type)) {
+		if (!gsc_ctx_state_is_set(GSC_SRC_FMT, ctx))
+			return -EINVAL;
+	} else if (!gsc_ctx_state_is_set(GSC_DST_FMT, ctx)) {
+		return -EINVAL;
+	}
+
+	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
+}
+
+static int gsc_m2m_streamoff(struct file *file, void *fh,
+			    enum v4l2_buf_type type)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
+}
+
+static int gsc_m2m_cropcap(struct file *file, void *fh,
+			struct v4l2_cropcap *cr)
+{
+	struct gsc_frame *frame;
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+
+	frame = ctx_get_frame(ctx, cr->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	cr->bounds.left		= 0;
+	cr->bounds.top		= 0;
+	cr->bounds.width	= frame->f_width;
+	cr->bounds.height	= frame->f_height;
+	cr->defrect		= cr->bounds;
+
+	return 0;
+}
+
+static int gsc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+
+	return gsc_g_crop(ctx, cr);
+}
+
+static int gsc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(fh);
+	struct gsc_variant *variant = ctx->gsc_dev->variant;
+	struct gsc_frame *f;
+	int ret;
+
+	ret = gsc_try_crop(ctx, cr);
+	if (ret)
+		return ret;
+
+	f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
+		&ctx->s_frame : &ctx->d_frame;
+
+	/* Check to see if scaling ratio is within supported range */
+	if (gsc_ctx_state_is_set(GSC_DST_FMT | GSC_SRC_FMT, ctx)) {
+		if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+			ret = gsc_check_scaler_ratio(variant, cr->c.width,
+					cr->c.height, ctx->d_frame.crop.width,
+					ctx->d_frame.crop.height,
+					ctx->gsc_ctrls.rotate->val, ctx->out_path);
+		} else {
+			ret = gsc_check_scaler_ratio(variant, ctx->s_frame.crop.width,
+					ctx->s_frame.crop.height, cr->c.width,
+					cr->c.height, ctx->gsc_ctrls.rotate->val,
+					ctx->out_path);
+		}
+		if (ret) {
+			gsc_err("Out of scaler range");
+			return -EINVAL;
+		}
+	}
+
+	f->crop.left = cr->c.left;
+	f->crop.top = cr->c.top;
+	f->crop.width  = cr->c.width;
+	f->crop.height = cr->c.height;
+
+	gsc_ctx_state_lock_set(GSC_PARAMS, ctx);
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops gsc_m2m_ioctl_ops = {
+	.vidioc_querycap		= gsc_m2m_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= gsc_m2m_enum_fmt_mplane,
+	.vidioc_enum_fmt_vid_out_mplane	= gsc_m2m_enum_fmt_mplane,
+
+	.vidioc_g_fmt_vid_cap_mplane	= gsc_m2m_g_fmt_mplane,
+	.vidioc_g_fmt_vid_out_mplane	= gsc_m2m_g_fmt_mplane,
+
+	.vidioc_try_fmt_vid_cap_mplane	= gsc_m2m_try_fmt_mplane,
+	.vidioc_try_fmt_vid_out_mplane	= gsc_m2m_try_fmt_mplane,
+
+	.vidioc_s_fmt_vid_cap_mplane	= gsc_m2m_s_fmt_mplane,
+	.vidioc_s_fmt_vid_out_mplane	= gsc_m2m_s_fmt_mplane,
+
+	.vidioc_reqbufs			= gsc_m2m_reqbufs,
+	.vidioc_querybuf		= gsc_m2m_querybuf,
+
+	.vidioc_qbuf			= gsc_m2m_qbuf,
+	.vidioc_dqbuf			= gsc_m2m_dqbuf,
+
+	.vidioc_streamon		= gsc_m2m_streamon,
+	.vidioc_streamoff		= gsc_m2m_streamoff,
+
+	.vidioc_g_crop			= gsc_m2m_g_crop,
+	.vidioc_s_crop			= gsc_m2m_s_crop,
+	.vidioc_cropcap			= gsc_m2m_cropcap
+
+};
+
+static int queue_init(void *priv, struct vb2_queue *src_vq,
+		      struct vb2_queue *dst_vq)
+{
+	struct gsc_ctx *ctx = priv;
+	int ret;
+
+	memset(src_vq, 0, sizeof(*src_vq));
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	src_vq->drv_priv = ctx;
+	src_vq->ops = &gsc_m2m_qops;
+	src_vq->mem_ops = ctx->gsc_dev->vb2->ops;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	memset(dst_vq, 0, sizeof(*dst_vq));
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	dst_vq->drv_priv = ctx;
+	dst_vq->ops = &gsc_m2m_qops;
+	dst_vq->mem_ops = ctx->gsc_dev->vb2->ops;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+
+	return vb2_queue_init(dst_vq);
+}
+
+static int gsc_m2m_open(struct file *file)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = NULL;
+	int ret;
+
+	gsc_dbg("pid: %d, state: 0x%lx", task_pid_nr(current), gsc->state);
+
+	if (gsc_out_opened(gsc) || gsc_cap_opened(gsc))
+		return -EBUSY;
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	v4l2_fh_init(&ctx->fh, gsc->m2m.vfd);
+	ret = gsc_ctrls_create(ctx);
+	if (ret)
+		goto error_fh;
+
+	/* Use separate control handler per file handle */
+	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+	file->private_data = &ctx->fh;
+	v4l2_fh_add(&ctx->fh);
+
+	ctx->gsc_dev = gsc;
+	/* Default color format */
+	ctx->s_frame.fmt = get_format(0);
+	ctx->d_frame.fmt = get_format(0);
+	/* Setup the device context for mem2mem mode. */
+	ctx->state |= GSC_CTX_M2M;
+	ctx->flags = 0;
+	ctx->in_path = GSC_DMA;
+	ctx->out_path = GSC_DMA;
+	spin_lock_init(&ctx->slock);
+	init_timer(&ctx->op_timer);
+	ctx->op_timer.data = (unsigned long)ctx;
+	ctx->op_timer.function = gsc_op_timer_handler;
+
+	ctx->m2m_ctx = v4l2_m2m_ctx_init(gsc->m2m.m2m_dev, ctx, queue_init);
+	if (IS_ERR(ctx->m2m_ctx)) {
+		gsc_err("Failed to initialize m2m context");
+		ret = PTR_ERR(ctx->m2m_ctx);
+		goto error_fh;
+	}
+
+	if (gsc->m2m.refcnt++ == 0)
+		set_bit(ST_M2M_OPEN, &gsc->state);
+
+	gsc_dbg("gsc m2m driver is opened, ctx(0x%p)", ctx);
+	return 0;
+
+error_fh:
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+	kfree(ctx);
+	return ret;
+}
+
+static int gsc_m2m_release(struct file *file)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(file->private_data);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+
+	gsc_dbg("pid: %d, state: 0x%lx, refcnt= %d",
+		task_pid_nr(current), gsc->state, gsc->m2m.refcnt);
+
+	v4l2_m2m_ctx_release(ctx->m2m_ctx);
+	gsc_ctrls_delete(ctx);
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+
+	if (--gsc->m2m.refcnt <= 0)
+		clear_bit(ST_M2M_OPEN, &gsc->state);
+	kfree(ctx);
+	return 0;
+}
+
+static unsigned int gsc_m2m_poll(struct file *file,
+				     struct poll_table_struct *wait)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(file->private_data);
+
+	return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
+}
+
+
+static int gsc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct gsc_ctx *ctx = fh_to_ctx(file->private_data);
+
+	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
+}
+static const struct v4l2_file_operations gsc_m2m_fops = {
+	.owner		= THIS_MODULE,
+	.open		= gsc_m2m_open,
+	.release	= gsc_m2m_release,
+	.poll		= gsc_m2m_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= gsc_m2m_mmap,
+};
+
+static struct v4l2_m2m_ops gsc_m2m_ops = {
+	.device_run	= gsc_m2m_device_run,
+	.job_abort	= gsc_m2m_job_abort,
+};
+
+int gsc_register_m2m_device(struct gsc_dev *gsc)
+{
+	struct video_device *vfd;
+	struct platform_device *pdev;
+	int ret = 0;
+
+	if (!gsc)
+		return -ENODEV;
+
+	pdev = gsc->pdev;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		dev_err(&pdev->dev, "Failed to allocate video device\n");
+		return -ENOMEM;
+	}
+
+	vfd->fops	= &gsc_m2m_fops;
+	vfd->ioctl_ops	= &gsc_m2m_ioctl_ops;
+	vfd->release	= video_device_release;
+	vfd->lock	= &gsc->lock;
+	snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
+
+	video_set_drvdata(vfd, gsc);
+
+	gsc->m2m.vfd = vfd;
+	gsc->m2m.m2m_dev = v4l2_m2m_init(&gsc_m2m_ops);
+	if (IS_ERR(gsc->m2m.m2m_dev)) {
+		dev_err(&pdev->dev, "failed to initialize v4l2-m2m device\n");
+		ret = PTR_ERR(gsc->m2m.m2m_dev);
+		goto err_m2m_r1;
+	}
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER,
+				    EXYNOS_VIDEONODE_GSC_M2M(gsc->id));
+	if (ret) {
+		dev_err(&pdev->dev,
+			 "%s(): failed to register video device\n", __func__);
+		goto err_m2m_r2;
+	}
+
+	gsc_dbg("gsc m2m driver registered as /dev/video%d", vfd->num);
+
+	return 0;
+
+err_m2m_r2:
+	v4l2_m2m_release(gsc->m2m.m2m_dev);
+err_m2m_r1:
+	video_device_release(gsc->m2m.vfd);
+
+	return ret;
+}
+
+void gsc_unregister_m2m_device(struct gsc_dev *gsc)
+{
+	if (gsc)
+		v4l2_m2m_release(gsc->m2m.m2m_dev);
+}
diff --git a/drivers/media/video/exynos/gsc/gsc-output.c b/drivers/media/video/exynos/gsc/gsc-output.c
new file mode 100644
index 0000000..d926a60
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-output.c
@@ -0,0 +1,1075 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-output.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series G-scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <media/v4l2-ioctl.h>
+
+#include "gsc-core.h"
+
+int gsc_out_hw_reset_off (struct gsc_dev *gsc)
+{
+	int ret;
+
+	if (!soc_is_exynos5250_rev1) {
+		gsc_hw_set_sw_reset(gsc);
+		ret = gsc_wait_reset(gsc);
+		if (ret < 0) {
+			gsc_err("gscaler s/w reset timeout");
+			return ret;
+		}
+		gsc_disp_fifo_sw_reset(gsc);
+		gsc_pixelasync_sw_reset(gsc);
+	}
+	gsc_hw_enable_control(gsc, false);
+	ret = gsc_wait_stop(gsc);
+	if (ret < 0) {
+		gsc_err("gscaler stop timeout");
+		return ret;
+	}
+
+	return 0;
+}
+
+int gsc_out_hw_set(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret = 0;
+
+	ret = gsc_set_scaler_info(ctx);
+	if (ret) {
+		gsc_err("Scaler setup error");
+		return ret;
+	}
+
+	gsc_hw_set_mixer();
+	if (soc_is_exynos5250_rev1) {
+		gsc_hw_set_sw_reset(gsc);
+		ret = gsc_wait_reset(gsc);
+		if (ret < 0) {
+			gsc_err("gscaler s/w reset timeout");
+			return ret;
+		}
+	}
+
+	if (gsc_hw_get_mxr_path_status())
+		gsc_hw_set_fire_bit_sync_mode(gsc, true);
+	else
+		gsc_hw_set_fire_bit_sync_mode(gsc, false);
+	gsc_hw_set_frm_done_irq_mask(gsc, false);
+	gsc_hw_set_gsc_irq_enable(gsc, true);
+	gsc_hw_set_one_frm_mode(gsc, false);
+	gsc_hw_set_freerun_clock_mode(gsc, true);
+
+	gsc_hw_set_input_path(ctx);
+	gsc_hw_set_in_size(ctx);
+	gsc_hw_set_in_image_format(ctx);
+
+	gsc_hw_set_output_path(ctx);
+	gsc_hw_set_out_size(ctx);
+	gsc_hw_set_out_image_format(ctx);
+
+	gsc_hw_set_prescaler(ctx);
+	gsc_hw_set_mainscaler(ctx);
+	gsc_hw_set_h_coef(ctx);
+	gsc_hw_set_v_coef(ctx);
+	gsc_hw_set_rotation(ctx);
+	gsc_hw_set_global_alpha(ctx);
+	gsc_hw_set_input_buf_mask_all(gsc);
+
+	return 0;
+}
+
+static void gsc_subdev_try_crop(struct gsc_dev *gsc, struct v4l2_rect *cr)
+{
+	struct gsc_variant *variant = gsc->variant;
+	u32 max_w, max_h, min_w, min_h;
+	u32 tmp_w, tmp_h;
+
+	if (gsc->out.ctx->gsc_ctrls.rotate->val == 90 ||
+		gsc->out.ctx->gsc_ctrls.rotate->val == 270) {
+		max_w = variant->pix_max->target_rot_en_w;
+		max_h = variant->pix_max->target_rot_en_h;
+		min_w = variant->pix_min->target_rot_en_w;
+		min_h = variant->pix_min->target_rot_en_h;
+		tmp_w = cr->height;
+		tmp_h = cr->width;
+	} else {
+		max_w = variant->pix_max->target_rot_dis_w;
+		max_h = variant->pix_max->target_rot_dis_h;
+		min_w = variant->pix_min->target_rot_dis_w;
+		min_h = variant->pix_min->target_rot_dis_h;
+		tmp_w = cr->width;
+		tmp_h = cr->height;
+	}
+
+	gsc_dbg("min_w: %d, min_h: %d, max_w: %d, max_h = %d",
+	     min_w, min_h, max_w, max_h);
+
+	v4l_bound_align_image(&tmp_w, min_w, max_w, 0,
+			      &tmp_h, min_h, max_h, 0, 0);
+
+	if (gsc->out.ctx->gsc_ctrls.rotate->val == 90 ||
+	    gsc->out.ctx->gsc_ctrls.rotate->val == 270)
+		gsc_check_crop_change(tmp_h, tmp_w, &cr->width, &cr->height);
+	else
+		gsc_check_crop_change(tmp_w, tmp_h, &cr->width, &cr->height);
+
+	gsc_dbg("Aligned l:%d, t:%d, w:%d, h:%d", cr->left, cr->top,
+		cr->width, cr->height);
+}
+
+static int gsc_subdev_get_fmt(struct v4l2_subdev *sd,
+			      struct v4l2_subdev_fh *fh,
+			      struct v4l2_subdev_format *fmt)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct v4l2_mbus_framefmt *mf = &fmt->format;
+	struct gsc_frame *f;
+
+	if (fmt->pad == GSC_PAD_SINK) {
+		gsc_err("Sink pad get_fmt is not supported");
+		return 0;
+	}
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+		fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
+		return 0;
+	}
+
+	f = &ctx->d_frame;
+	mf->code = f->fmt->mbus_code;
+	mf->width = f->f_width;
+	mf->height = f->f_height;
+	mf->colorspace = V4L2_COLORSPACE_JPEG;
+
+	return 0;
+}
+
+static int gsc_subdev_set_fmt(struct v4l2_subdev *sd,
+			       struct v4l2_subdev_fh *fh,
+			       struct v4l2_subdev_format *fmt)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	struct v4l2_mbus_framefmt *mf;
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct gsc_frame *f;
+
+	gsc_dbg("pad%d: code: 0x%x, %dx%d",
+	    fmt->pad, fmt->format.code, fmt->format.width, fmt->format.height);
+
+	if (fmt->pad == GSC_PAD_SINK) {
+		gsc_err("Sink pad set_fmt is not supported");
+		return 0;
+	}
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+		mf = v4l2_subdev_get_try_format(fh, fmt->pad);
+		mf->width = fmt->format.width;
+		mf->height = fmt->format.height;
+		mf->code = fmt->format.code;
+		mf->colorspace = V4L2_COLORSPACE_JPEG;
+	} else {
+		f = &ctx->d_frame;
+		gsc_set_frame_size(f, fmt->format.width, fmt->format.height);
+		f->fmt = find_format(NULL, &fmt->format.code, 0);
+		ctx->state |= GSC_DST_FMT;
+	}
+
+	return 0;
+}
+
+static int gsc_subdev_get_crop(struct v4l2_subdev *sd,
+				struct v4l2_subdev_fh *fh,
+				struct v4l2_subdev_crop *crop)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct v4l2_rect *r = &crop->rect;
+	struct gsc_frame *f;
+
+	if (crop->pad == GSC_PAD_SINK) {
+		gsc_err("Sink pad get_crop is not supported");
+		return 0;
+	}
+
+	if (crop->which == V4L2_SUBDEV_FORMAT_TRY) {
+		crop->rect = *v4l2_subdev_get_try_crop(fh, crop->pad);
+		return 0;
+	}
+
+	f = &ctx->d_frame;
+	r->left	  = f->crop.left;
+	r->top	  = f->crop.top;
+	r->width  = f->crop.width;
+	r->height = f->crop.height;
+
+	gsc_dbg("f:%p, pad%d: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d",
+	    f, crop->pad, r->left, r->top, r->width, r->height,
+	    f->f_width, f->f_height);
+
+	return 0;
+}
+
+static int gsc_subdev_set_crop(struct v4l2_subdev *sd,
+				struct v4l2_subdev_fh *fh,
+				struct v4l2_subdev_crop *crop)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct v4l2_rect *r;
+	struct gsc_frame *f;
+
+	gsc_dbg("(%d,%d)/%dx%d", crop->rect.left, crop->rect.top, crop->rect.width, crop->rect.height);
+
+	if (crop->pad == GSC_PAD_SINK) {
+		gsc_err("Sink pad set_fmt is not supported\n");
+		return 0;
+	}
+
+	if (crop->which == V4L2_SUBDEV_FORMAT_TRY) {
+		r = v4l2_subdev_get_try_crop(fh, crop->pad);
+		r->left = crop->rect.left;
+		r->top = crop->rect.top;
+		r->width = crop->rect.width;
+		r->height = crop->rect.height;
+	} else {
+		f = &ctx->d_frame;
+		f->crop.left = crop->rect.left;
+		f->crop.top = crop->rect.top;
+		f->crop.width = crop->rect.width;
+		f->crop.height = crop->rect.height;
+		if (f->crop.width % 2)
+			f->crop.width -= 1;
+	}
+
+	gsc_dbg("pad%d: (%d,%d)/%dx%d", crop->pad, crop->rect.left, crop->rect.top,
+	    crop->rect.width, crop->rect.height);
+
+	return 0;
+}
+
+static int gsc_subdev_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	int ret;
+
+	if (enable) {
+		pm_runtime_get_sync(&gsc->pdev->dev);
+		ret = gsc_out_hw_set(gsc->out.ctx);
+		if (ret) {
+			gsc_err("GSC H/W setting is failed");
+			return -EINVAL;
+		}
+	} else {
+		INIT_LIST_HEAD(&gsc->out.active_buf_q);
+		clear_bit(ST_OUTPUT_STREAMON, &gsc->state);
+		pm_runtime_put_sync(&gsc->pdev->dev);
+	}
+
+	return 0;
+}
+
+static struct v4l2_subdev_pad_ops gsc_subdev_pad_ops = {
+	.get_fmt = gsc_subdev_get_fmt,
+	.set_fmt = gsc_subdev_set_fmt,
+	.get_crop = gsc_subdev_get_crop,
+	.set_crop = gsc_subdev_set_crop,
+};
+
+static struct v4l2_subdev_video_ops gsc_subdev_video_ops = {
+	.s_stream = gsc_subdev_s_stream,
+};
+
+static struct v4l2_subdev_ops gsc_subdev_ops = {
+	.pad = &gsc_subdev_pad_ops,
+	.video = &gsc_subdev_video_ops,
+};
+
+static int gsc_out_power_off(struct v4l2_subdev *sd)
+{
+	struct gsc_dev *gsc = entity_data_to_gsc(v4l2_get_subdevdata(sd));
+	int ret;
+
+	ret = gsc_out_hw_reset_off(gsc);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static struct exynos_media_ops gsc_out_link_callback = {
+	.power_off = gsc_out_power_off,
+};
+
+/*
+ * The video node ioctl operations
+ */
+static int gsc_output_querycap(struct file *file, void *priv,
+					struct v4l2_capability *cap)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	strncpy(cap->driver, gsc->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, gsc->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+
+	return 0;
+}
+
+static int gsc_output_enum_fmt_mplane(struct file *file, void *priv,
+				struct v4l2_fmtdesc *f)
+{
+	return gsc_enum_fmt_mplane(f);
+}
+
+static int gsc_output_try_fmt_mplane(struct file *file, void *fh,
+			       struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	if (!is_output(f->type)) {
+		gsc_err("Not supported buffer type");
+		return -EINVAL;
+	}
+
+	return gsc_try_fmt_mplane(gsc->out.ctx, f);
+}
+
+static int gsc_output_s_fmt_mplane(struct file *file, void *fh,
+				 struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct gsc_frame *frame;
+	struct v4l2_pix_format_mplane *pix;
+	int i, ret = 0;
+
+	ret = gsc_output_try_fmt_mplane(file, fh, f);
+	if (ret) {
+		gsc_err("Invalid argument");
+		return ret;
+	}
+
+	if (vb2_is_streaming(&gsc->out.vbq)) {
+		gsc_err("queue (%d) busy", f->type);
+		return -EBUSY;
+	}
+
+	frame = &ctx->s_frame;
+
+	pix = &f->fmt.pix_mp;
+	frame->fmt = find_format(&pix->pixelformat, NULL, 0);
+	if (!frame->fmt) {
+		gsc_err("Not supported pixel format");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < frame->fmt->num_planes; i++)
+		frame->payload[i] = pix->plane_fmt[i].sizeimage;
+
+	gsc_set_frame_size(frame, pix->width, pix->height);
+
+	ctx->state |= GSC_SRC_FMT;
+
+	gsc_dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
+
+	return 0;
+}
+
+static int gsc_output_g_fmt_mplane(struct file *file, void *fh,
+			     struct v4l2_format *f)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->out.ctx;
+
+	if (!is_output(f->type)) {
+		gsc_err("Not supported buffer type");
+		return -EINVAL;
+	}
+
+	return gsc_g_fmt_mplane(ctx, f);
+}
+
+static int gsc_output_reqbufs(struct file *file, void *priv,
+			    struct v4l2_requestbuffers *reqbufs)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_output_device *out = &gsc->out;
+	struct gsc_frame *frame;
+	int ret;
+
+	if (reqbufs->count > gsc->variant->in_buf_cnt) {
+		gsc_err("Requested count exceeds maximun count of input buffer");
+		return -EINVAL;
+	} else if (reqbufs->count == 0)
+		gsc_ctx_state_lock_clear(GSC_SRC_FMT | GSC_DST_FMT,
+					 out->ctx);
+
+	frame = ctx_get_frame(out->ctx, reqbufs->type);
+	update_use_sysmmu(gsc->vb2, out->ctx->gsc_ctrls.use_sysmmu);
+	frame->cacheable = out->ctx->gsc_ctrls.cacheable->val;
+	gsc->vb2->set_cacheable(gsc->alloc_ctx, frame->cacheable);
+	ret = vb2_reqbufs(&out->vbq, reqbufs);
+	if (ret)
+		return ret;
+	out->req_cnt = reqbufs->count;
+
+	return ret;
+}
+
+static int gsc_output_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_output_device *out = &gsc->out;
+
+	return vb2_querybuf(&out->vbq, buf);
+}
+
+static int gsc_output_streamon(struct file *file, void *priv,
+			     enum v4l2_buf_type type)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_output_device *out = &gsc->out;
+	struct media_pad *sink_pad;
+	int ret;
+
+	sink_pad = media_entity_remote_source(&out->sd_pads[GSC_PAD_SOURCE]);
+	if (IS_ERR(sink_pad)) {
+		gsc_err("No sink pad conncted with a gscaler source pad");
+		return PTR_ERR(sink_pad);
+	}
+
+	ret = gsc_out_link_validate(&out->sd_pads[GSC_PAD_SOURCE], sink_pad);
+	if (ret) {
+		gsc_err("Output link validation is failed");
+		return ret;
+	}
+
+	media_entity_pipeline_start(&out->vfd->entity, gsc->pipeline.pipe);
+
+	return vb2_streamon(&gsc->out.vbq, type);
+}
+
+static int gsc_output_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_streamoff(&gsc->out.vbq, type);
+}
+
+static int gsc_output_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_output_device *out = &gsc->out;
+
+	return vb2_qbuf(&out->vbq, buf);
+}
+
+static int gsc_output_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_dqbuf(&gsc->out.vbq, buf,
+			 file->f_flags & O_NONBLOCK);
+}
+
+static int gsc_output_cropcap(struct file *file, void *fh,
+				struct v4l2_cropcap *cr)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->out.ctx;
+
+	if (!is_output(cr->type)) {
+		gsc_err("Not supported buffer type");
+		return -EINVAL;
+	}
+
+	cr->bounds.left		= 0;
+	cr->bounds.top		= 0;
+	cr->bounds.width	= ctx->s_frame.f_width;
+	cr->bounds.height	= ctx->s_frame.f_height;
+	cr->defrect		= cr->bounds;
+
+	return 0;
+
+}
+
+static int gsc_output_g_crop(struct file *file, void *fh,
+			     struct v4l2_crop *cr)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	if (!is_output(cr->type)) {
+		gsc_err("Not supported buffer type");
+		return -EINVAL;
+	}
+
+	return gsc_g_crop(gsc->out.ctx, cr);
+}
+
+static int gsc_output_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	struct gsc_ctx *ctx = gsc->out.ctx;
+	struct gsc_variant *variant = gsc->variant;
+	struct gsc_frame *f;
+	unsigned int mask = GSC_DST_FMT | GSC_SRC_FMT;
+	int ret;
+
+	if (!is_output(cr->type)) {
+		gsc_err("Not supported buffer type");
+		return -EINVAL;
+	}
+
+	ret = gsc_try_crop(ctx, cr);
+	if (ret)
+		return ret;
+
+	f = &ctx->s_frame;
+
+	/* Check to see if scaling ratio is within supported range */
+	if ((ctx->state & (GSC_DST_FMT | GSC_SRC_FMT)) == mask) {
+		ret = gsc_check_scaler_ratio(variant, f->crop.width,
+				f->crop.height, ctx->d_frame.crop.width,
+				ctx->d_frame.crop.height,
+				ctx->gsc_ctrls.rotate->val, ctx->out_path);
+		if (ret) {
+			gsc_err("Out of scaler range");
+			return -EINVAL;
+		}
+		gsc_subdev_try_crop(gsc, &ctx->d_frame.crop);
+	}
+
+	f->crop.left = cr->c.left;
+	f->crop.top = cr->c.top;
+	f->crop.width  = cr->c.width;
+	f->crop.height = cr->c.height;
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops gsc_output_ioctl_ops = {
+	.vidioc_querycap		= gsc_output_querycap,
+	.vidioc_enum_fmt_vid_out_mplane	= gsc_output_enum_fmt_mplane,
+
+	.vidioc_try_fmt_vid_out_mplane	= gsc_output_try_fmt_mplane,
+	.vidioc_s_fmt_vid_out_mplane	= gsc_output_s_fmt_mplane,
+	.vidioc_g_fmt_vid_out_mplane	= gsc_output_g_fmt_mplane,
+
+	.vidioc_reqbufs			= gsc_output_reqbufs,
+	.vidioc_querybuf		= gsc_output_querybuf,
+
+	.vidioc_qbuf			= gsc_output_qbuf,
+	.vidioc_dqbuf			= gsc_output_dqbuf,
+
+	.vidioc_streamon		= gsc_output_streamon,
+	.vidioc_streamoff		= gsc_output_streamoff,
+
+	.vidioc_g_crop			= gsc_output_g_crop,
+	.vidioc_s_crop			= gsc_output_s_crop,
+	.vidioc_cropcap			= gsc_output_cropcap,
+};
+
+static int gsc_out_video_s_stream(struct gsc_dev *gsc, int enable)
+{
+	struct gsc_output_device *out = &gsc->out;
+	struct media_pad *sink_pad;
+	struct v4l2_subdev *sd;
+	int ret = 0;
+
+	sink_pad = media_entity_remote_source(&out->vd_pad);
+	if (IS_ERR(sink_pad)) {
+		gsc_err("No sink pad conncted with a gscaler video source pad");
+		return PTR_ERR(sink_pad);
+	}
+	sd = media_entity_to_v4l2_subdev(sink_pad->entity);
+	ret = v4l2_subdev_call(sd, video, s_stream, enable);
+	if (ret)
+		gsc_err("G-Scaler subdev s_stream[%d] failed", enable);
+
+	return ret;
+}
+
+static int gsc_out_start_streaming(struct vb2_queue *q)
+{
+	struct gsc_ctx *ctx = q->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+
+	return gsc_out_video_s_stream(gsc, 1);
+}
+
+static int gsc_out_stop_streaming(struct vb2_queue *q)
+{
+	struct gsc_ctx *ctx = q->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	int ret = 0;
+
+	ret = gsc_pipeline_s_stream(gsc, false);
+	if (ret)
+		return ret;
+
+	if (ctx->out_path == GSC_FIMD) {
+		gsc_hw_enable_control(gsc, false);
+		ret = gsc_wait_stop(gsc);
+		if (ret < 0)
+			return ret;
+	}
+	gsc_hw_set_input_buf_mask_all(gsc);
+
+	/* TODO: Add gscaler clock off function */
+	ret = gsc_out_video_s_stream(gsc, 0);
+	if (ret) {
+		gsc_err("G-Scaler video s_stream off failed");
+		return ret;
+	}
+	media_entity_pipeline_stop(&gsc->out.vfd->entity);
+
+	return ret;
+}
+
+static int gsc_out_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+		       unsigned int *num_planes, unsigned long sizes[],
+		       void *allocators[])
+{
+	struct gsc_ctx *ctx = vq->drv_priv;
+	struct gsc_fmt *fmt = ctx->s_frame.fmt;
+	int i;
+
+	if (IS_ERR(fmt)) {
+		gsc_err("Invalid source format");
+		return PTR_ERR(fmt);
+	}
+
+	*num_planes = fmt->num_planes;
+
+	for (i = 0; i < fmt->num_planes; i++) {
+		sizes[i] = get_plane_size(&ctx->s_frame, i);
+		allocators[i] = ctx->gsc_dev->alloc_ctx;
+	}
+	vb2_queue_init(vq);
+
+	return 0;
+}
+
+static int gsc_out_buffer_prepare(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct gsc_ctx *ctx = vq->drv_priv;
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->s_frame;
+
+	if (!ctx->s_frame.fmt || !is_output(vq->type)) {
+		gsc_err("Invalid argument");
+		return -EINVAL;
+	}
+
+	if (ctx->s_frame.cacheable)
+		gsc->vb2->cache_flush(vb, frame->fmt->num_planes);
+
+	return 0;
+}
+
+int gsc_out_set_in_addr(struct gsc_dev *gsc, struct gsc_ctx *ctx,
+			struct gsc_input_buf *buf, int index)
+{
+	int ret;
+
+	ret = gsc_prepare_addr(ctx, &buf->vb, &ctx->s_frame, &ctx->s_frame.addr);
+	if (ret) {
+		gsc_err("Fail to prepare G-Scaler address");
+		return -EINVAL;
+	}
+	gsc_hw_set_input_addr(gsc, &ctx->s_frame.addr, index);
+	active_queue_push(&gsc->out, buf, gsc);
+	buf->idx = index;
+
+	return 0;
+}
+
+static void gsc_out_buffer_queue(struct vb2_buffer *vb)
+{
+	struct gsc_input_buf *buf
+		= container_of(vb, struct gsc_input_buf, vb);
+	struct vb2_queue *q = vb->vb2_queue;
+	struct gsc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct gsc_dev *gsc = ctx->gsc_dev;
+	unsigned long flags;
+	int ret;
+
+	if (gsc->out.req_cnt >= atomic_read(&q->queued_count)) {
+		spin_lock_irqsave(&gsc->slock, flags);
+		ret = gsc_out_set_in_addr(gsc, ctx, buf, vb->v4l2_buf.index);
+		if (ret) {
+			gsc_err("Failed to prepare G-Scaler address");
+			spin_unlock_irqrestore(&gsc->slock, flags);
+			return;
+		}
+		gsc_hw_set_input_buf_masking(gsc, vb->v4l2_buf.index, false);
+		gsc_hw_set_in_pingpong_update(gsc);
+		spin_unlock_irqrestore(&gsc->slock, flags);
+	} else {
+		gsc_err("All requested buffers have been queued already");
+		return;
+	}
+
+	if (!test_and_set_bit(ST_OUTPUT_STREAMON, &gsc->state)) {
+		gsc_hw_enable_control(gsc, true);
+		ret = gsc_wait_operating(gsc);
+		if (ret < 0) {
+			gsc_err("wait operation timeout");
+			return;
+		}
+		gsc_pipeline_s_stream(gsc, true);
+	}
+}
+
+static struct vb2_ops gsc_output_qops = {
+	.queue_setup		= gsc_out_queue_setup,
+	.buf_prepare		= gsc_out_buffer_prepare,
+	.buf_queue		= gsc_out_buffer_queue,
+	.wait_prepare		= gsc_unlock,
+	.wait_finish		= gsc_lock,
+	.start_streaming	= gsc_out_start_streaming,
+	.stop_streaming		= gsc_out_stop_streaming,
+};
+
+static int gsc_out_link_setup(struct media_entity *entity,
+			   const struct media_pad *local,
+			   const struct media_pad *remote, u32 flags)
+{
+	if (media_entity_type(entity) != MEDIA_ENT_T_V4L2_SUBDEV)
+		return 0;
+
+	if (local->flags == MEDIA_PAD_FL_SOURCE) {
+		struct gsc_dev *gsc = entity_to_gsc(entity);
+		struct v4l2_subdev *sd;
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			if (gsc->pipeline.disp == NULL) {
+				/* Gscaler 0 --> Winwow 0, Gscaler 1 --> Window 1,
+				   Gscaler 2 --> Window 2, Gscaler 3 --> Window 2 */
+				char name[FIMD_NAME_SIZE];
+				sprintf(name, "%s%d", FIMD_ENTITY_NAME, get_win_num(gsc));
+				sd = media_entity_to_v4l2_subdev(remote->entity);
+				gsc->pipeline.disp = sd;
+				if (!strcmp(sd->name, name)) {
+					gsc->out.ctx->out_path = GSC_FIMD;
+					gsc_hw_set_local_dst(gsc->id, GSC_FIMD, true);
+				} else {
+					gsc->out.ctx->out_path = GSC_MIXER;
+					gsc_hw_set_local_dst(gsc->id, GSC_MIXER, true);
+				}
+			} else
+				gsc_err("G-Scaler source pad was linked already");
+		} else if (!(flags & ~MEDIA_LNK_FL_ENABLED)) {
+			if (gsc->pipeline.disp != NULL) {
+				if (gsc->out.ctx->out_path == GSC_FIMD) {
+					gsc_hw_set_local_dst(gsc->id,
+							     GSC_FIMD, false);
+				} else {
+					gsc_hw_set_local_dst(gsc->id,
+							     GSC_MIXER, false);
+				}
+				gsc->pipeline.disp = NULL;
+				gsc->out.ctx->out_path = 0;
+			} else
+				gsc_err("G-Scaler source pad was unlinked already");
+		}
+	}
+
+	return 0;
+}
+
+static const struct media_entity_operations gsc_out_media_ops = {
+	.link_setup = gsc_out_link_setup,
+};
+
+int gsc_output_ctrls_create(struct gsc_dev *gsc)
+{
+	int ret;
+
+	ret = gsc_ctrls_create(gsc->out.ctx);
+	if (ret) {
+		gsc_err("Failed to create controls of G-Scaler");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int gsc_output_open(struct file *file)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+	int ret = v4l2_fh_open(file);
+
+	if (ret)
+		return ret;
+
+	gsc_dbg("pid: %d, state: 0x%lx", task_pid_nr(current), gsc->state);
+
+	/* Return if the corresponding mem2mem/output/capture video node
+	   is already opened. */
+	if (gsc_m2m_opened(gsc) || gsc_cap_opened(gsc) || gsc_out_opened(gsc)) {
+		gsc_err("G-Scaler%d has been opened already", gsc->id);
+		return -EBUSY;
+	}
+
+	if (WARN_ON(gsc->out.ctx == NULL)) {
+		gsc_err("G-Scaler output context is NULL");
+		return -ENXIO;
+	}
+
+	set_bit(ST_OUTPUT_OPEN, &gsc->state);
+
+	ret = gsc_ctrls_create(gsc->out.ctx);
+	if (ret < 0) {
+		v4l2_fh_release(file);
+		clear_bit(ST_OUTPUT_OPEN, &gsc->state);
+		return ret;
+	}
+
+	return ret;
+}
+
+static int gsc_output_close(struct file *file)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	gsc_dbg("pid: %d, state: 0x%lx", task_pid_nr(current), gsc->state);
+
+	clear_bit(ST_OUTPUT_OPEN, &gsc->state);
+	vb2_queue_release(&gsc->out.vbq);
+	gsc_ctrls_delete(gsc->out.ctx);
+	v4l2_fh_release(file);
+
+	return 0;
+}
+
+static unsigned int gsc_output_poll(struct file *file,
+				      struct poll_table_struct *wait)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_poll(&gsc->out.vbq, file, wait);
+}
+
+static int gsc_output_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct gsc_dev *gsc = video_drvdata(file);
+
+	return vb2_mmap(&gsc->out.vbq, vma);
+}
+
+static const struct v4l2_file_operations gsc_output_fops = {
+	.owner		= THIS_MODULE,
+	.open		= gsc_output_open,
+	.release	= gsc_output_close,
+	.poll		= gsc_output_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= gsc_output_mmap,
+};
+
+static int gsc_create_link(struct gsc_dev *gsc)
+{
+	struct media_entity *source, *sink;
+	int ret;
+
+	source = &gsc->out.vfd->entity;
+	sink = &gsc->out.sd->entity;
+	ret = media_entity_create_link(source, 0, sink, GSC_PAD_SINK,
+				       MEDIA_LNK_FL_IMMUTABLE |
+				       MEDIA_LNK_FL_ENABLED);
+	if (ret) {
+		gsc_err("Failed to create link between G-Scaler vfd and subdev");
+		return ret;
+	}
+
+	return 0;
+}
+
+
+static int gsc_create_subdev(struct gsc_dev *gsc)
+{
+	struct v4l2_subdev *sd;
+	int ret;
+
+	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
+	if (!sd)
+	       return -ENOMEM;
+
+	v4l2_subdev_init(sd, &gsc_subdev_ops);
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(sd->name, sizeof(sd->name), "%s.%d", GSC_SUBDEV_NAME, gsc->id);
+
+	gsc->out.sd_pads[GSC_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	gsc->out.sd_pads[GSC_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&sd->entity, GSC_PADS_NUM,
+				gsc->out.sd_pads, 0);
+	if (ret) {
+		gsc_err("Failed to initialize the G-Scaler media entity");
+		goto error;
+	}
+
+	sd->entity.ops = &gsc_out_media_ops;
+	ret = v4l2_device_register_subdev(&gsc->mdev[MDEV_OUTPUT]->v4l2_dev, sd);
+	if (ret) {
+		media_entity_cleanup(&sd->entity);
+		goto error;
+	}
+	gsc->mdev[MDEV_OUTPUT]->gsc_sd[gsc->id] = sd;
+	gsc_dbg("gsc_sd[%d] = 0x%08x\n", gsc->id,
+			(u32)gsc->mdev[MDEV_OUTPUT]->gsc_sd[gsc->id]);
+	gsc->out.sd = sd;
+	gsc->md_data.media_ops = &gsc_out_link_callback;
+	v4l2_set_subdevdata(sd, &gsc->md_data);
+
+	return 0;
+error:
+	kfree(sd);
+	return ret;
+}
+
+int gsc_register_output_device(struct gsc_dev *gsc)
+{
+	struct video_device *vfd;
+	struct gsc_output_device *gsc_out;
+	struct gsc_ctx *ctx;
+	struct vb2_queue *q;
+	int ret = -ENOMEM;
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	ctx->gsc_dev	 = gsc;
+	ctx->s_frame.fmt = get_format(GSC_OUT_DEF_SRC);
+	ctx->d_frame.fmt = get_format(GSC_OUT_DEF_DST);
+	ctx->in_path	 = GSC_DMA;
+	ctx->state	 = GSC_CTX_OUTPUT;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		gsc_err("Failed to allocate video device");
+		goto err_ctx_alloc;
+	}
+
+	snprintf(vfd->name, sizeof(vfd->name), "%s.output",
+		 dev_name(&gsc->pdev->dev));
+
+
+	vfd->fops	= &gsc_output_fops;
+	vfd->ioctl_ops	= &gsc_output_ioctl_ops;
+	vfd->v4l2_dev	= &gsc->mdev[MDEV_OUTPUT]->v4l2_dev;
+	vfd->release	= video_device_release;
+	vfd->lock	= &gsc->lock;
+	video_set_drvdata(vfd, gsc);
+
+	gsc_out	= &gsc->out;
+	gsc_out->vfd = vfd;
+
+	INIT_LIST_HEAD(&gsc_out->active_buf_q);
+	spin_lock_init(&ctx->slock);
+	gsc_out->ctx = ctx;
+
+	q = &gsc->out.vbq;
+	memset(q, 0, sizeof(*q));
+	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	q->io_modes = VB2_MMAP | VB2_USERPTR;
+	q->drv_priv = gsc->out.ctx;
+	q->ops = &gsc_output_qops;
+	q->mem_ops = gsc->vb2->ops;;
+	q->buf_struct_size = sizeof(struct gsc_input_buf);
+
+	vb2_queue_init(q);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER,
+				    EXYNOS_VIDEONODE_GSC_OUT(gsc->id));
+	if (ret) {
+		gsc_err("Failed to register video device");
+		goto err_ent;
+	}
+
+	gsc->out.vd_pad.flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&vfd->entity, 1, &gsc->out.vd_pad, 0);
+	if (ret)
+		goto err_ent;
+
+	ret = gsc_create_subdev(gsc);
+	if (ret)
+		goto err_sd_reg;
+
+	ret = gsc_create_link(gsc);
+	if (ret)
+		goto err_sd_reg;
+
+	vfd->ctrl_handler = &ctx->ctrl_handler;
+	gsc_dbg("gsc output driver registered as /dev/video%d, ctx(0x%08x)",
+		vfd->num, (u32)ctx);
+	return 0;
+
+err_sd_reg:
+	media_entity_cleanup(&vfd->entity);
+err_ent:
+	video_device_release(vfd);
+err_ctx_alloc:
+	kfree(ctx);
+	return ret;
+}
+
+static void gsc_destroy_subdev(struct gsc_dev *gsc)
+{
+	struct v4l2_subdev *sd = gsc->out.sd;
+
+	if (!sd)
+		return;
+	media_entity_cleanup(&sd->entity);
+	v4l2_device_unregister_subdev(sd);
+	kfree(sd);
+	sd = NULL;
+}
+
+void gsc_unregister_output_device(struct gsc_dev *gsc)
+{
+	struct video_device *vfd = gsc->out.vfd;
+
+	if (vfd) {
+		media_entity_cleanup(&vfd->entity);
+		/* Can also be called if video device was
+		   not registered */
+		video_unregister_device(vfd);
+	}
+	gsc_destroy_subdev(gsc);
+	kfree(gsc->out.ctx);
+	gsc->out.ctx = NULL;
+}
diff --git a/drivers/media/video/exynos/gsc/gsc-regs.c b/drivers/media/video/exynos/gsc/gsc-regs.c
new file mode 100644
index 0000000..f357a1d
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-regs.c
@@ -0,0 +1,844 @@
+/* linux/drivers/media/video/exynos/gsc/gsc-regs.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series G-scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <mach/map.h>
+#include "gsc-core.h"
+
+void gsc_hw_set_sw_reset(struct gsc_dev *dev)
+{
+	u32 cfg = 0;
+
+	cfg |= GSC_SW_RESET_SRESET;
+	writel(cfg, dev->regs + GSC_SW_RESET);
+}
+
+void gsc_disp_fifo_sw_reset(struct gsc_dev *dev)
+{
+	u32 cfg = readl(SYSREG_DISP1BLK_CFG);
+	/* DISPBLK1 FIFO S/W reset sequence
+	   set FIFORST_DISP1 as 0 then, set FIFORST_DISP1 as 1 again */
+	cfg &= ~FIFORST_DISP1;
+	writel(cfg, SYSREG_DISP1BLK_CFG);
+	cfg |= FIFORST_DISP1;
+	writel(cfg, SYSREG_DISP1BLK_CFG);
+}
+
+void gsc_pixelasync_sw_reset(struct gsc_dev *dev)
+{
+	u32 cfg = readl(SYSREG_GSCBLK_CFG0);
+	/* GSCBLK Pixel asyncy FIFO S/W reset sequence
+	   set PXLASYNC_SW_RESET as 0 then, set PXLASYNC_SW_RESET as 1 again */
+	cfg &= ~GSC_PXLASYNC_RST(dev->id);
+	writel(cfg, SYSREG_GSCBLK_CFG0);
+	cfg |= GSC_PXLASYNC_RST(dev->id);
+	writel(cfg, SYSREG_GSCBLK_CFG0);
+}
+
+int gsc_wait_reset(struct gsc_dev *dev)
+{
+	unsigned long timeo = jiffies + 10; /* timeout of 50ms */
+	u32 cfg;
+
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(dev->regs + GSC_SW_RESET);
+		if (!cfg)
+			return 0;
+		usleep_range(10, 20);
+	}
+	gsc_dbg("wait time : %d ms", jiffies_to_msecs(jiffies - timeo + 20));
+
+	return -EBUSY;
+}
+
+int gsc_wait_operating(struct gsc_dev *dev)
+{
+	unsigned long timeo = jiffies + 10; /* timeout of 50ms */
+	u32 cfg;
+
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(dev->regs + GSC_ENABLE);
+		if (cfg & GSC_ENABLE_OP_STATUS)
+			return 0;
+		usleep_range(10, 20);
+	}
+	gsc_dbg("wait time : %d ms", jiffies_to_msecs(jiffies - timeo + 20));
+
+	return -EBUSY;
+}
+
+int gsc_wait_stop(struct gsc_dev *dev)
+{
+	unsigned long timeo = jiffies + 10; /* timeout of 50ms */
+	u32 cfg;
+
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(dev->regs + GSC_ENABLE);
+		if (!(cfg & GSC_ENABLE_OP_STATUS))
+			return 0;
+		usleep_range(10, 20);
+	}
+	gsc_dbg("wait time : %d ms", jiffies_to_msecs(jiffies - timeo + 20));
+
+	return -EBUSY;
+}
+
+void gsc_hw_set_in_chrom_stride(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->s_frame;
+	u32 chrom_size, cfg;
+
+	cfg = readl(dev->regs + GSC_IN_CON);
+	cfg |= GSC_IN_CHROM_STRIDE_SEPAR;
+	writel(cfg, dev->regs + GSC_IN_CON);
+
+	cfg &= ~GSC_IN_CHROM_STRIDE_MASK;
+	chrom_size = ALIGN(frame->f_width / 2, 16) * 2;
+	cfg = GSC_IN_CHROM_STRIDE_VALUE(chrom_size);
+	writel(cfg, dev->regs + GSC_IN_CHROM_STRIDE);
+}
+
+void gsc_hw_set_out_chrom_stride(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	u32 chrom_size, cfg;
+
+	cfg = readl(dev->regs + GSC_OUT_CON);
+	cfg |= GSC_OUT_CHROM_STRIDE_SEPAR;
+	writel(cfg, dev->regs + GSC_OUT_CON);
+
+	cfg &= ~GSC_OUT_CHROM_STRIDE_MASK;
+	chrom_size = ALIGN(frame->f_width / 2, 16) * 2;
+	cfg = GSC_OUT_CHROM_STRIDE_VALUE(chrom_size);
+	writel(cfg, dev->regs + GSC_OUT_CHROM_STRIDE);
+}
+
+void gsc_hw_set_in_pingpong_update(struct gsc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + GSC_ENABLE);
+	cfg |= GSC_ENABLE_IN_PP_UPDATE;
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+void gsc_hw_set_one_frm_mode(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_ENABLE);
+	cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK);
+	if (mask)
+		cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+void gsc_hw_set_fire_bit_sync_mode(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_ENABLE);
+	cfg &= ~(GSC_ENABLE_PP_UPDATE_MODE_MASK);
+	if (mask)
+		cfg |= GSC_ENABLE_PP_UPDATE_FIRE_MODE;
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+int gsc_hw_get_mxr_path_status(void)
+{
+	int i, cnt = 0;
+
+	u32 cfg = readl(SYSREG_GSCBLK_CFG0);
+	for(i = 0; i < GSC_MAX_DEVS; i++) {
+		if (cfg & GSC_OUT_DST_MXR_SEL(i))
+			cnt++;
+	}
+	return (cnt > 2) ? 1 : 0;
+}
+
+int gsc_hw_get_input_buf_mask_status(struct gsc_dev *dev)
+{
+	u32 cfg, status, bits = 0;
+
+	cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	status = cfg & GSC_IN_BASE_ADDR_MASK;
+	while (status) {
+		status = status & (status - 1);
+		bits++;
+	}
+	return bits;
+}
+
+int gsc_hw_get_done_input_buf_index(struct gsc_dev *dev)
+{
+	u32 cfg, curr_index, i;
+
+	cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	curr_index = GSC_IN_CURR_GET_INDEX(cfg);
+	for (i = curr_index; i > 1; i--) {
+		if (cfg ^ (1 << (i - 2)))
+			return i - 2;
+	}
+
+	for (i = dev->variant->in_buf_cnt; i > curr_index; i--) {
+		if (cfg ^ (1 << (i - 1)))
+			return i - 1;
+	}
+
+	return curr_index - 1;
+}
+
+int gsc_hw_get_done_output_buf_index(struct gsc_dev *dev)
+{
+	u32 cfg, curr_index, done_buf_index;
+	unsigned long state_mask;
+	u32 reqbufs_cnt = dev->cap.reqbufs_cnt;
+
+	cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
+	gsc_dbg("curr_index : %d", curr_index);
+	state_mask = cfg & GSC_OUT_BASE_ADDR_MASK;
+
+	done_buf_index = (curr_index == 0) ? reqbufs_cnt - 1 : curr_index - 1;
+
+	do {
+		/* Test done_buf_index whether masking or not */
+		if (test_bit(done_buf_index, &state_mask))
+			done_buf_index = (done_buf_index == 0) ?
+				reqbufs_cnt - 1 : done_buf_index - 1;
+		else
+			return done_buf_index;
+	} while (done_buf_index != curr_index);
+
+	return -EBUSY;
+}
+
+void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IRQ);
+	if (mask)
+		cfg |= GSC_IRQ_FRMDONE_MASK;
+	else
+		cfg &= ~GSC_IRQ_FRMDONE_MASK;
+	writel(cfg, dev->regs + GSC_IRQ);
+}
+
+void gsc_hw_set_overflow_irq_mask(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IRQ);
+	if (mask)
+		cfg |= GSC_IRQ_OR_MASK;
+	else
+		cfg &= ~GSC_IRQ_OR_MASK;
+	writel(cfg, dev->regs + GSC_IRQ);
+}
+
+void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IRQ);
+	if (mask)
+		cfg |= GSC_IRQ_ENABLE;
+	else
+		cfg &= ~GSC_IRQ_ENABLE;
+	writel(cfg, dev->regs + GSC_IRQ);
+}
+
+void gsc_hw_set_input_buf_mask_all(struct gsc_dev *dev)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	cfg |= GSC_IN_BASE_ADDR_MASK;
+	cfg |= GSC_IN_BASE_ADDR_PINGPONG(dev->variant->in_buf_cnt);
+
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
+}
+
+void gsc_hw_set_output_buf_mask_all(struct gsc_dev *dev)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	cfg |= GSC_OUT_BASE_ADDR_MASK;
+	cfg |= GSC_OUT_BASE_ADDR_PINGPONG(dev->variant->out_buf_cnt);
+
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
+}
+
+void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift,
+				bool enable)
+{
+	u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	u32 mask = 1 << shift;
+
+	cfg &= (~mask);
+	cfg |= enable << shift;
+
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
+	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
+}
+
+void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift,
+				bool enable)
+{
+	u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	u32 mask = 1 << shift;
+
+	cfg &= (~mask);
+	cfg |= enable << shift;
+
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
+	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
+}
+
+int gsc_hw_get_nr_unmask_bits(struct gsc_dev *dev)
+{
+	u32 bits = 0;
+	u32 mask_bits = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
+	mask_bits &= GSC_OUT_BASE_ADDR_MASK;
+
+	while (mask_bits) {
+		mask_bits = mask_bits & (mask_bits - 1);
+		bits++;
+	}
+	bits = 16 - bits;
+
+	return bits;
+}
+
+void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr,
+				int index)
+{
+	gsc_dbg("src_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", index,
+		addr->y, addr->cb, addr->cr);
+	writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index));
+	writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index));
+	writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index));
+
+}
+
+void gsc_hw_set_output_addr(struct gsc_dev *dev,
+			     struct gsc_addr *addr, int index)
+{
+	gsc_dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
+			index, addr->y, addr->cb, addr->cr);
+	writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index));
+	writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index));
+	writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index));
+}
+
+void gsc_hw_set_freerun_clock_mode(struct gsc_dev *dev, bool mask)
+{
+	u32 cfg = readl(dev->regs + GSC_ENABLE);
+
+	cfg &= ~(GSC_ENABLE_CLK_GATE_MODE_MASK);
+	if (mask)
+		cfg |= GSC_ENABLE_CLK_GATE_MODE_FREE;
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+void gsc_hw_set_input_path(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+
+	u32 cfg = readl(dev->regs + GSC_IN_CON);
+	cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
+
+	if (ctx->in_path == GSC_DMA) {
+		cfg |= GSC_IN_PATH_MEMORY;
+	} else {
+		cfg |= GSC_IN_PATH_LOCAL;
+		if (ctx->in_path == GSC_WRITEBACK) {
+			cfg |= GSC_IN_LOCAL_FIMD_WB;
+		} else {
+			struct v4l2_subdev *sd = dev->pipeline.sensor;
+			struct gsc_sensor_info *s_info =
+				v4l2_get_subdev_hostdata(sd);
+			if (s_info->pdata->cam_port == CAM_PORT_A)
+				cfg |= GSC_IN_LOCAL_CAM0;
+			else
+				cfg |= GSC_IN_LOCAL_CAM1;
+		}
+	}
+
+	writel(cfg, dev->regs + GSC_IN_CON);
+}
+
+void gsc_hw_set_in_size(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->s_frame;
+	u32 cfg;
+
+	/* Set input pixel offset */
+	cfg = GSC_SRCIMG_OFFSET_X(frame->crop.left);
+	cfg |= GSC_SRCIMG_OFFSET_Y(frame->crop.top);
+	writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
+
+	/* Set input original size */
+	cfg = GSC_SRCIMG_WIDTH(frame->f_width);
+	cfg |= GSC_SRCIMG_HEIGHT(frame->f_height);
+	writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
+
+	/* Set input cropped size */
+	cfg = GSC_CROPPED_WIDTH(frame->crop.width);
+	cfg |= GSC_CROPPED_HEIGHT(frame->crop.height);
+	writel(cfg, dev->regs + GSC_CROPPED_SIZE);
+}
+
+void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->s_frame;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IN_CON);
+	if (ctx->gsc_ctrls.csc_eq->val) {
+		if (ctx->gsc_ctrls.csc_range->val)
+			cfg |= GSC_IN_RGB_HD_WIDE;
+		else
+			cfg |= GSC_IN_RGB_HD_NARROW;
+	} else {
+		if (ctx->gsc_ctrls.csc_range->val)
+			cfg |= GSC_IN_RGB_SD_WIDE;
+		else
+			cfg |= GSC_IN_RGB_SD_NARROW;
+	}
+
+	if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
+		cfg |= GSC_IN_RGB565;
+	else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
+		cfg |= GSC_IN_XRGB8888;
+
+	writel(cfg, dev->regs + GSC_IN_CON);
+}
+
+void gsc_hw_set_in_image_format(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->s_frame;
+	u32 i, depth = 0;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IN_CON);
+	cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
+		 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
+		 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
+		 GSC_IN_CHROM_STRIDE_SEL_MASK);
+	writel(cfg, dev->regs + GSC_IN_CON);
+
+	if (is_rgb(frame->fmt->pixelformat)) {
+		gsc_hw_set_in_image_rgb(ctx);
+		return;
+	}
+	for (i = 0; i < frame->fmt->num_planes; i++)
+		depth += frame->fmt->depth[i];
+
+	switch (frame->fmt->nr_comp) {
+	case 1:
+		cfg |= GSC_IN_YUV422_1P;
+		if (frame->fmt->yorder == GSC_LSB_Y)
+			cfg |= GSC_IN_YUV422_1P_ORDER_LSB_Y;
+		else
+			cfg |= GSC_IN_YUV422_1P_OEDER_LSB_C;
+		if (frame->fmt->corder == GSC_CBCR)
+			cfg |= GSC_IN_CHROMA_ORDER_CBCR;
+		else
+			cfg |= GSC_IN_CHROMA_ORDER_CRCB;
+		break;
+	case 2:
+		if (depth == 12)
+			cfg |= GSC_IN_YUV420_2P;
+		else
+			cfg |= GSC_IN_YUV422_2P;
+		if (frame->fmt->corder == GSC_CBCR)
+			cfg |= GSC_IN_CHROMA_ORDER_CBCR;
+		else
+			cfg |= GSC_IN_CHROMA_ORDER_CRCB;
+		break;
+	case 3:
+		if (depth == 12)
+			cfg |= GSC_IN_YUV420_3P;
+		else
+			cfg |= GSC_IN_YUV422_3P;
+		break;
+	};
+
+	if (is_AYV12(frame->fmt->pixelformat))
+		gsc_hw_set_in_chrom_stride(ctx);
+
+	if (is_tiled(frame->fmt))
+		cfg |= GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE;
+
+	writel(cfg, dev->regs + GSC_IN_CON);
+}
+
+void gsc_hw_set_output_path(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+
+	u32 cfg = readl(dev->regs + GSC_OUT_CON);
+	cfg &= ~GSC_OUT_PATH_MASK;
+
+	if (ctx->out_path == GSC_DMA)
+		cfg |= GSC_OUT_PATH_MEMORY;
+	else
+		cfg |= GSC_OUT_PATH_LOCAL;
+
+	writel(cfg, dev->regs + GSC_OUT_CON);
+}
+
+void gsc_hw_set_out_size(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	u32 cfg;
+
+	/* Set output original size */
+	if (ctx->out_path == GSC_DMA) {
+		cfg = GSC_DSTIMG_OFFSET_X(frame->crop.left);
+		cfg |= GSC_DSTIMG_OFFSET_Y(frame->crop.top);
+		writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
+
+		cfg = GSC_DSTIMG_WIDTH(frame->f_width);
+		cfg |= GSC_DSTIMG_HEIGHT(frame->f_height);
+		writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
+	}
+
+	/* Set output scaled size */
+	if (ctx->gsc_ctrls.rotate->val == 90 ||
+	    ctx->gsc_ctrls.rotate->val == 270) {
+		cfg = GSC_SCALED_WIDTH(frame->crop.height);
+		cfg |= GSC_SCALED_HEIGHT(frame->crop.width);
+	} else {
+		cfg = GSC_SCALED_WIDTH(frame->crop.width);
+		cfg |= GSC_SCALED_HEIGHT(frame->crop.height);
+	}
+	writel(cfg, dev->regs + GSC_SCALED_SIZE);
+}
+
+void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_OUT_CON);
+	if (ctx->gsc_ctrls.csc_eq->val) {
+		if (ctx->gsc_ctrls.csc_range->val)
+			cfg |= GSC_OUT_RGB_HD_WIDE;
+		else
+			cfg |= GSC_OUT_RGB_HD_NARROW;
+	} else {
+		if (ctx->gsc_ctrls.csc_range->val)
+			cfg |= GSC_OUT_RGB_SD_WIDE;
+		else
+			cfg |= GSC_OUT_RGB_SD_NARROW;
+	}
+
+	if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
+		cfg |= GSC_OUT_RGB565;
+	else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
+		cfg |= GSC_OUT_XRGB8888;
+
+	writel(cfg, dev->regs + GSC_OUT_CON);
+}
+
+void gsc_hw_set_out_image_format(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	u32 i, depth = 0;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_OUT_CON);
+	cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
+		 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
+		 GSC_OUT_TILE_TYPE_MASK | GSC_OUT_TILE_MODE |
+		 GSC_OUT_CHROM_STRIDE_SEL_MASK);
+	writel(cfg, dev->regs + GSC_OUT_CON);
+
+	if (is_rgb(frame->fmt->pixelformat)) {
+		gsc_hw_set_out_image_rgb(ctx);
+		return;
+	}
+
+	if (ctx->out_path != GSC_DMA) {
+		cfg |= GSC_OUT_YUV444;
+		goto end_set;
+	}
+
+	for (i = 0; i < frame->fmt->num_planes; i++)
+		depth += frame->fmt->depth[i];
+
+	switch (frame->fmt->nr_comp) {
+	case 1:
+		cfg |= GSC_OUT_YUV422_1P;
+		if (frame->fmt->yorder == GSC_LSB_Y)
+			cfg |= GSC_OUT_YUV422_1P_ORDER_LSB_Y;
+		else
+			cfg |= GSC_OUT_YUV422_1P_OEDER_LSB_C;
+		if (frame->fmt->corder == GSC_CBCR)
+			cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
+		else
+			cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
+		break;
+	case 2:
+		if (depth == 12)
+			cfg |= GSC_OUT_YUV420_2P;
+		else
+			cfg |= GSC_OUT_YUV422_2P;
+		if (frame->fmt->corder == GSC_CBCR)
+			cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
+		else
+			cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
+		break;
+	case 3:
+		cfg |= GSC_OUT_YUV420_3P;
+		break;
+	};
+
+	if (is_AYV12(frame->fmt->pixelformat))
+		gsc_hw_set_out_chrom_stride(ctx);
+
+	if (is_tiled(frame->fmt))
+		cfg |= GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE;
+
+end_set:
+	writel(cfg, dev->regs + GSC_OUT_CON);
+}
+
+void gsc_hw_set_prescaler(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_scaler *sc = &ctx->scaler;
+	u32 cfg;
+
+	cfg = GSC_PRESC_SHFACTOR(sc->pre_shfactor);
+	cfg |= GSC_PRESC_H_RATIO(sc->pre_hratio);
+	cfg |= GSC_PRESC_V_RATIO(sc->pre_vratio);
+	writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
+}
+
+void gsc_hw_set_mainscaler(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_scaler *sc = &ctx->scaler;
+	u32 cfg;
+
+	cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
+	writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
+
+	cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
+	writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
+}
+
+void gsc_hw_set_rotation(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_IN_CON);
+	cfg &= ~GSC_IN_ROT_MASK;
+
+	switch (ctx->gsc_ctrls.rotate->val) {
+	case 270:
+		cfg |= GSC_IN_ROT_270;
+		break;
+	case 180:
+		cfg |= GSC_IN_ROT_180;
+		break;
+	case 90:
+		if (ctx->gsc_ctrls.hflip->val)
+			cfg |= GSC_IN_ROT_90_XFLIP;
+		else if (ctx->gsc_ctrls.vflip->val)
+			cfg |= GSC_IN_ROT_90_YFLIP;
+		else
+			cfg |= GSC_IN_ROT_90;
+		break;
+	case 0:
+		if (ctx->gsc_ctrls.hflip->val)
+			cfg |= GSC_IN_ROT_XFLIP;
+		else if (ctx->gsc_ctrls.vflip->val)
+			cfg |= GSC_IN_ROT_YFLIP;
+	}
+
+	writel(cfg, dev->regs + GSC_IN_CON);
+}
+
+void gsc_hw_set_global_alpha(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	struct gsc_frame *frame = &ctx->d_frame;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_OUT_CON);
+	cfg &= ~GSC_OUT_GLOBAL_ALPHA_MASK;
+
+	if (!is_rgb(frame->fmt->pixelformat)) {
+		gsc_dbg("Not a RGB format");
+		return;
+	}
+
+	cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val);
+	writel(cfg, dev->regs + GSC_OUT_CON);
+}
+
+void gsc_hw_set_sfr_update(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+	u32 cfg;
+
+	cfg = readl(dev->regs + GSC_ENABLE);
+	cfg |= GSC_ENABLE_SFR_UPDATE;
+	writel(cfg, dev->regs + GSC_ENABLE);
+}
+
+void gsc_hw_set_mixer(void)
+{
+	u32 cfg = readl(SYSREG_DISP1BLK_CFG);
+
+	cfg |= (GSC_OUT_MIXER0_GSC3);
+
+	writel(cfg, SYSREG_DISP1BLK_CFG);
+}
+
+void gsc_hw_set_local_dst(int id, int out, bool on)
+{
+	u32 cfg = readl(SYSREG_GSCBLK_CFG0);
+
+	if (out == GSC_FIMD) {
+		if (on)
+			cfg |= GSC_OUT_DST_FIMD_SEL(id);
+		else
+			cfg &= ~(GSC_OUT_DST_FIMD_SEL(id));
+	} else if (out == GSC_MIXER) {
+		if (on)
+			cfg |= GSC_OUT_DST_MXR_SEL(id);
+		else
+			cfg &= ~(GSC_OUT_DST_MXR_SEL(id));
+	}
+	writel(cfg, SYSREG_GSCBLK_CFG0);
+}
+
+void gsc_hw_set_sysreg_writeback(struct gsc_ctx *ctx)
+{
+	struct gsc_dev *dev = ctx->gsc_dev;
+
+	u32 cfg = readl(SYSREG_GSCBLK_CFG1);
+
+	cfg &= ~GSC_BLK_SW_RESET_WB_DEST(dev->id);
+	writel(cfg, SYSREG_GSCBLK_CFG1);
+
+	cfg |= GSC_BLK_DISP1WB_DEST(dev->id);
+	cfg |= GSC_BLK_GSCL_WB_IN_SRC_SEL(dev->id);
+	cfg |= GSC_BLK_SW_RESET_WB_DEST(dev->id);
+
+	writel(cfg, SYSREG_GSCBLK_CFG1);
+}
+
+void gsc_hw_set_pxlasync_camif_lo_mask(struct gsc_dev *dev, bool on)
+{
+	u32 cfg = 0;
+
+	if (dev->id == 3) {
+		cfg = readl(SYSREG_GSCBLK_CFG0);
+		if (on)
+			cfg |= PXLASYNC_LO_MASK_CAMIF_TOP;
+		else
+			cfg &= ~(PXLASYNC_LO_MASK_CAMIF_TOP);
+		writel(cfg, SYSREG_GSCBLK_CFG0);
+	} else {
+		cfg = readl(SYSREG_GSCBLK_CFG2);
+		if (on)
+			cfg |= PXLASYNC_LO_MASK_CAMIF_GSCL(dev->id);
+		else
+			cfg &= ~PXLASYNC_LO_MASK_CAMIF_GSCL(dev->id);
+		writel(cfg, SYSREG_GSCBLK_CFG2);
+	}
+}
+
+void gsc_hw_set_h_coef(struct gsc_ctx *ctx)
+{
+	struct gsc_scaler *sc = &ctx->scaler;
+	struct gsc_dev *dev = ctx->gsc_dev;
+	int i, j, k, sc_ratio = 0;
+
+	if (sc->main_hratio <= GSC_SC_UP_MAX_RATIO)
+		sc_ratio = 0;
+	else if (sc->main_hratio <= GSC_SC_DOWN_RATIO_7_8)
+		sc_ratio = 1;
+	else if (sc->main_hratio <= GSC_SC_DOWN_RATIO_6_8)
+		sc_ratio = 2;
+	else if (sc->main_hratio <= GSC_SC_DOWN_RATIO_5_8)
+		sc_ratio = 3;
+	else if (sc->main_hratio <= GSC_SC_DOWN_RATIO_4_8)
+		sc_ratio = 4;
+	else if (sc->main_hratio <= GSC_SC_DOWN_RATIO_3_8)
+		sc_ratio = 5;
+	else
+		sc_ratio = 6;
+
+	for(i = 0; i < 9; i++) {
+		for(j = 0; j < 8; j++) {
+			for(k = 0; k < 3; k++) {
+				writel(h_coef_8t[sc_ratio][i][j],
+				       dev->regs + GSC_HCOEF(i, j, k));
+			}
+		}
+	}
+}
+
+void gsc_hw_set_v_coef(struct gsc_ctx *ctx)
+{
+	struct gsc_scaler *sc = &ctx->scaler;
+	struct gsc_dev *dev = ctx->gsc_dev;
+	int i, j, k, sc_ratio = 0;
+
+	if (sc->main_vratio <= GSC_SC_UP_MAX_RATIO)
+		sc_ratio = 0;
+	else if (sc->main_vratio <= GSC_SC_DOWN_RATIO_7_8)
+		sc_ratio = 1;
+	else if (sc->main_vratio <= GSC_SC_DOWN_RATIO_6_8)
+		sc_ratio = 2;
+	else if (sc->main_vratio <= GSC_SC_DOWN_RATIO_5_8)
+		sc_ratio = 3;
+	else if (sc->main_vratio <= GSC_SC_DOWN_RATIO_4_8)
+		sc_ratio = 4;
+	else if (sc->main_vratio <= GSC_SC_DOWN_RATIO_3_8)
+		sc_ratio = 5;
+	else
+		sc_ratio = 6;
+
+	for(i = 0; i < 9; i++) {
+		for(j = 0; j < 4; j++) {
+			for(k = 0; k < 3; k++) {
+				writel(v_coef_4t[sc_ratio][i][j],\
+				       dev->regs + GSC_VCOEF(i, j, k));
+			}
+		}
+	}
+}
diff --git a/drivers/media/video/exynos/gsc/gsc-vb2.c b/drivers/media/video/exynos/gsc/gsc-vb2.c
new file mode 100644
index 0000000..7f5e36d
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/gsc-vb2.c
@@ -0,0 +1,72 @@
+/* linux/drivers/media/video/exynos/gsc-vb2.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Videobuf2 allocator operations file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include "gsc-core.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *gsc_cma_init(struct gsc_dev *gsc)
+{
+	return vb2_cma_phys_init(&gsc->pdev->dev, NULL, 0, false);
+}
+
+int gsc_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void gsc_cma_suspend(void *alloc_ctx) {}
+void gsc_cma_set_cacheable(void *alloc_ctx, bool cacheable) {}
+
+int gsc_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct gsc_vb2 gsc_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= gsc_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= gsc_cma_resume,
+	.suspend	= gsc_cma_suspend,
+	.cache_flush	= gsc_cma_cache_flush,
+	.set_cacheable	= gsc_cma_set_cacheable,
+	.use_sysmmu	= false;
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *gsc_ion_init(struct gsc_dev *gsc)
+{
+	return vb2_ion_create_context(&gsc->pdev->dev, SZ_4K,
+		VB2ION_CTX_VMCONTIG | VB2ION_CTX_IOMMU | VB2ION_CTX_UNCACHED);
+}
+
+static unsigned long gsc_vb2_plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+const struct gsc_vb2 gsc_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= gsc_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= gsc_vb2_plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+	.use_sysmmu	= true,
+};
+#endif
diff --git a/drivers/media/video/exynos/gsc/regs-gsc.h b/drivers/media/video/exynos/gsc/regs-gsc.h
new file mode 100644
index 0000000..580203e
--- /dev/null
+++ b/drivers/media/video/exynos/gsc/regs-gsc.h
@@ -0,0 +1,304 @@
+/* linux/drivers/media/video/exynos/gsc/regs-gsc.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Register definition file for Samsung G-Scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef REGS_GSC_H_
+#define REGS_GSC_H_
+
+/* SYSCON. GSCBLK_CFG */
+#include <plat/map-base.h>
+#include <plat/cpu.h>
+#define SYSREG_DISP1BLK_CFG		(S3C_VA_SYS + 0x0214)
+#define FIFORST_DISP1			(1 << 23)
+#define GSC_OUT_MIXER0			(1 << 7)
+#define GSC_OUT_MIXER0_GSC3		(3 << 5)
+#define SYSREG_GSCBLK_CFG0		(S3C_VA_SYS + 0x0220)
+#define GSC_OUT_DST_FIMD_SEL(x)		(1 << (8 + 2 *(x)))
+#define GSC_OUT_DST_MXR_SEL(x)		(2 << (8 + 2 *(x)))
+#define GSC_PXLASYNC_RST(x)		(1 << (x))
+#define PXLASYNC_LO_MASK_CAMIF_TOP	(1 << 20)
+#define SYSREG_GSCBLK_CFG1		(S3C_VA_SYS + 0x0224)
+#define GSC_BLK_DISP1WB_DEST(x)		(x << 10)
+#define GSC_BLK_SW_RESET_WB_DEST(x)	(1 << (18 + x))
+#define GSC_BLK_GSCL_WB_IN_SRC_SEL(x)	(1 << (2 * x))
+#define SYSREG_GSCBLK_CFG2		(S3C_VA_SYS + 0x2000)
+#define PXLASYNC_LO_MASK_CAMIF_GSCL(x)	(1 << (x))
+
+/* G-Scaler enable */
+#define GSC_ENABLE			0x00
+#define GSC_ENABLE_PP_UPDATE_TIME_MASK	(1 << 9)
+#define GSC_ENABLE_PP_UPDATE_TIME_CURR	(0 << 9)
+#define GSC_ENABLE_PP_UPDATE_TIME_EOPAS	(1 << 9)
+#define GSC_ENABLE_CLK_GATE_MODE_MASK	(1 << 8)
+#define GSC_ENABLE_CLK_GATE_MODE_FREE	(1 << 8)
+#define GSC_ENABLE_IPC_MODE_MASK	(1 << 7)
+#define GSC_ENABLE_NORM_MODE		(0 << 7)
+#define GSC_ENABLE_IPC_MODE		(1 << 7)
+#define GSC_ENABLE_PP_UPDATE_MODE_MASK	(1 << 6)
+#define GSC_ENABLE_PP_UPDATE_FIRE_MODE	(1 << 6)
+#define GSC_ENABLE_IN_PP_UPDATE		(1 << 5)
+#define GSC_ENABLE_ON_CLEAR_MASK	(1 << 4)
+#define GSC_ENABLE_ON_CLEAR_ONESHOT	(1 << 4)
+#define GSC_ENABLE_QOS_ENABLE		(1 << 3)
+#define GSC_ENABLE_OP_STATUS		(1 << 2)
+#define GSC_ENABLE_SFR_UPDATE		(1 << 1)
+#define GSC_ENABLE_ON			(1 << 0)
+
+/* G-Scaler S/W reset */
+#define GSC_SW_RESET			0x04
+#define GSC_SW_RESET_SRESET		(1 << 0)
+
+/* G-Scaler IRQ */
+#define GSC_IRQ				0x08
+#define GSC_IRQ_STATUS_OR_IRQ		(1 << 17)
+#define GSC_IRQ_STATUS_OR_FRM_DONE	(1 << 16)
+#define GSC_IRQ_OR_MASK			(1 << 2)
+#define GSC_IRQ_FRMDONE_MASK		(1 << 1)
+#define GSC_IRQ_ENABLE			(1 << 0)
+
+/* G-Scaler input control */
+#define GSC_IN_CON			0x10
+#define GSC_IN_CHROM_STRIDE_SEL_MASK	(1 << 20)
+#define GSC_IN_CHROM_STRIDE_SEPAR	(1 << 20)
+#define GSC_IN_RB_SWAP_MASK		(1 << 19)
+#define GSC_IN_RB_SWAP			(1 << 19)
+#define GSC_IN_ROT_MASK			(7 << 16)
+#define GSC_IN_ROT_270			(7 << 16)
+#define GSC_IN_ROT_90_YFLIP		(6 << 16)
+#define GSC_IN_ROT_90_XFLIP		(5 << 16)
+#define GSC_IN_ROT_90			(4 << 16)
+#define GSC_IN_ROT_180			(3 << 16)
+#define GSC_IN_ROT_YFLIP		(2 << 16)
+#define GSC_IN_ROT_XFLIP		(1 << 16)
+#define GSC_IN_RGB_TYPE_MASK		(3 << 14)
+#define GSC_IN_RGB_HD_WIDE		(3 << 14)
+#define GSC_IN_RGB_HD_NARROW		(2 << 14)
+#define GSC_IN_RGB_SD_WIDE		(1 << 14)
+#define GSC_IN_RGB_SD_NARROW		(0 << 14)
+#define GSC_IN_YUV422_1P_ORDER_MASK	(1 << 13)
+#define GSC_IN_YUV422_1P_ORDER_LSB_Y	(0 << 13)
+#define GSC_IN_YUV422_1P_OEDER_LSB_C	(1 << 13)
+#define GSC_IN_CHROMA_ORDER_MASK	(1 << 12)
+#define GSC_IN_CHROMA_ORDER_CBCR	(0 << 12)
+#define GSC_IN_CHROMA_ORDER_CRCB	(1 << 12)
+#define GSC_IN_FORMAT_MASK		(7 << 8)
+#define GSC_IN_XRGB8888			(0 << 8)
+#define GSC_IN_RGB565			(1 << 8)
+#define GSC_IN_YUV420_2P		(2 << 8)
+#define GSC_IN_YUV420_3P		(3 << 8)
+#define GSC_IN_YUV422_1P		(4 << 8)
+#define GSC_IN_YUV422_2P		(5 << 8)
+#define GSC_IN_YUV422_3P		(6 << 8)
+#define GSC_IN_TILE_TYPE_MASK		(1 << 4)
+#define GSC_IN_TILE_C_16x8		(0 << 4)
+#define GSC_IN_TILE_C_16x16		(1 << 4)
+#define GSC_IN_TILE_MODE		(1 << 3)
+#define GSC_IN_LOCAL_SEL_MASK		(3 << 1)
+#define GSC_IN_LOCAL_CAM3		(3 << 1)
+#define GSC_IN_LOCAL_FIMD_WB		(2 << 1)
+#define GSC_IN_LOCAL_CAM1		(1 << 1)
+#define GSC_IN_LOCAL_CAM0		(0 << 1)
+#define GSC_IN_PATH_MASK		(1 << 0)
+#define GSC_IN_PATH_LOCAL		(1 << 0)
+#define GSC_IN_PATH_MEMORY		(0 << 0)
+
+/* G-Scaler source image size */
+#define GSC_SRCIMG_SIZE			0x14
+#define GSC_SRCIMG_HEIGHT_MASK		(0x1fff << 16)
+#define GSC_SRCIMG_HEIGHT(x)		((x) << 16)
+#define GSC_SRCIMG_WIDTH_MASK		(0x3fff << 0)
+#define GSC_SRCIMG_WIDTH(x)		((x) << 0)
+
+/* G-Scaler source image offset */
+#define GSC_SRCIMG_OFFSET		0x18
+#define GSC_SRCIMG_OFFSET_Y_MASK	(0x1fff << 16)
+#define GSC_SRCIMG_OFFSET_Y(x)		((x) << 16)
+#define GSC_SRCIMG_OFFSET_X_MASK	(0x1fff << 0)
+#define GSC_SRCIMG_OFFSET_X(x)		((x) << 0)
+
+/* G-Scaler cropped source image size */
+#define GSC_CROPPED_SIZE		0x1C
+#define GSC_CROPPED_HEIGHT_MASK		(0x1fff << 16)
+#define GSC_CROPPED_HEIGHT(x)		((x) << 16)
+#define GSC_CROPPED_WIDTH_MASK		(0x1fff << 0)
+#define GSC_CROPPED_WIDTH(x)		((x) << 0)
+
+/* G-Scaler output control */
+#define GSC_OUT_CON			0x20
+#define GSC_OUT_GLOBAL_ALPHA_MASK	(0xff << 24)
+#define GSC_OUT_GLOBAL_ALPHA(x)		((x) << 24)
+#define GSC_OUT_CHROM_STRIDE_SEL_MASK	(1 << 13)
+#define GSC_OUT_CHROM_STRIDE_SEPAR	(1 << 13)
+#define GSC_OUT_RB_SWAP_MASK		(1 << 12)
+#define GSC_OUT_RB_SWAP			(1 << 12)
+#define GSC_OUT_RGB_TYPE_MASK		(3 << 10)
+#define GSC_OUT_RGB_HD_NARROW		(3 << 10)
+#define GSC_OUT_RGB_HD_WIDE		(2 << 10)
+#define GSC_OUT_RGB_SD_NARROW		(1 << 10)
+#define GSC_OUT_RGB_SD_WIDE		(0 << 10)
+#define GSC_OUT_YUV422_1P_ORDER_MASK	(1 << 9)
+#define GSC_OUT_YUV422_1P_ORDER_LSB_Y	(0 << 9)
+#define GSC_OUT_YUV422_1P_OEDER_LSB_C	(1 << 9)
+#define GSC_OUT_CHROMA_ORDER_MASK	(1 << 8)
+#define GSC_OUT_CHROMA_ORDER_CBCR	(0 << 8)
+#define GSC_OUT_CHROMA_ORDER_CRCB	(1 << 8)
+#define GSC_OUT_FORMAT_MASK		(7 << 4)
+#define GSC_OUT_XRGB8888		(0 << 4)
+#define GSC_OUT_RGB565			(1 << 4)
+#define GSC_OUT_YUV420_2P		(2 << 4)
+#define GSC_OUT_YUV420_3P		(3 << 4)
+#define GSC_OUT_YUV422_1P		(4 << 4)
+#define GSC_OUT_YUV422_2P		(5 << 4)
+#define GSC_OUT_YUV444			(7 << 4)
+#define GSC_OUT_TILE_TYPE_MASK		(1 << 2)
+#define GSC_OUT_TILE_C_16x8		(0 << 2)
+#define GSC_OUT_TILE_C_16x16		(1 << 2)
+#define GSC_OUT_TILE_MODE		(1 << 1)
+#define GSC_OUT_PATH_MASK		(1 << 0)
+#define GSC_OUT_PATH_LOCAL		(1 << 0)
+#define GSC_OUT_PATH_MEMORY		(0 << 0)
+
+/* G-Scaler scaled destination image size */
+#define GSC_SCALED_SIZE			0x24
+#define GSC_SCALED_HEIGHT_MASK		(0x1fff << 16)
+#define GSC_SCALED_HEIGHT(x)		((x) << 16)
+#define GSC_SCALED_WIDTH_MASK		(0x1fff << 0)
+#define GSC_SCALED_WIDTH(x)		((x) << 0)
+
+/* G-Scaler pre scale ratio */
+#define GSC_PRE_SCALE_RATIO		0x28
+#define GSC_PRESC_SHFACTOR_MASK		(7 << 28)
+#define GSC_PRESC_SHFACTOR(x)		((x) << 28)
+#define GSC_PRESC_V_RATIO_MASK		(7 << 16)
+#define GSC_PRESC_V_RATIO(x)		((x) << 16)
+#define GSC_PRESC_H_RATIO_MASK		(7 << 0)
+#define GSC_PRESC_H_RATIO(x)		((x) << 0)
+
+/* G-Scaler main scale horizontal ratio */
+#define GSC_MAIN_H_RATIO		0x2C
+#define GSC_MAIN_H_RATIO_MASK		(0xfffff << 0)
+#define GSC_MAIN_H_RATIO_VALUE(x)	((x) << 0)
+
+/* G-Scaler main scale vertical ratio */
+#define GSC_MAIN_V_RATIO		0x30
+#define GSC_MAIN_V_RATIO_MASK		(0xfffff << 0)
+#define GSC_MAIN_V_RATIO_VALUE(x)	((x) << 0)
+
+/* G-Scaler input chrominance stride */
+#define GSC_IN_CHROM_STRIDE		0x3C
+#define GSC_IN_CHROM_STRIDE_MASK	(0x3fff << 0)
+#define GSC_IN_CHROM_STRIDE_VALUE(x)	((x) << 0)
+
+/* G-Scaler destination image size */
+#define GSC_DSTIMG_SIZE			0x40
+#define GSC_DSTIMG_HEIGHT_MASK		(0x1fff << 16)
+#define GSC_DSTIMG_HEIGHT(x)		((x) << 16)
+#define GSC_DSTIMG_WIDTH_MASK		(0x1fff << 0)
+#define GSC_DSTIMG_WIDTH(x)		((x) << 0)
+
+/* G-Scaler destination image offset */
+#define GSC_DSTIMG_OFFSET		0x44
+#define GSC_DSTIMG_OFFSET_Y_MASK	(0x1fff << 16)
+#define GSC_DSTIMG_OFFSET_Y(x)		((x) << 16)
+#define GSC_DSTIMG_OFFSET_X_MASK	(0x1fff << 0)
+#define GSC_DSTIMG_OFFSET_X(x)		((x) << 0)
+
+/* G-Scaler output chrominance stride */
+#define GSC_OUT_CHROM_STRIDE		0x48
+#define GSC_OUT_CHROM_STRIDE_MASK	(0x3fff << 0)
+#define GSC_OUT_CHROM_STRIDE_VALUE(x)	((x) << 0)
+
+/* G-Scaler input y address mask */
+#define GSC_IN_BASE_ADDR_Y_MASK		0x4C
+/* G-Scaler input y base address */
+#define GSC_IN_BASE_ADDR_Y(n)		(0x50 + (n) * 0x4)
+/* G-Scaler input y base current address */
+#define GSC_IN_BASE_ADDR_Y_CUR(n)	(0x60 + (n) * 0x4)
+
+/* G-Scaler input cb address mask */
+#define GSC_IN_BASE_ADDR_CB_MASK	0x7C
+/* G-Scaler input cb base address */
+#define GSC_IN_BASE_ADDR_CB(n)		(0x80 + (n) * 0x4)
+/* G-Scaler input cb base current address */
+#define GSC_IN_BASE_ADDR_CB_CUR(n)	(0x90 + (n) * 0x4)
+
+/* G-Scaler input cr address mask */
+#define GSC_IN_BASE_ADDR_CR_MASK	0xAC
+/* G-Scaler input cr base address */
+#define GSC_IN_BASE_ADDR_CR(n)		(0xB0 + (n) * 0x4)
+/* G-Scaler input cr base current address */
+#define GSC_IN_BASE_ADDR_CR_CUR(n)	(0xC0 + (n) * 0x4)
+
+/* G-Scaler input address mask */
+#define GSC_EVT0_IN_CURR_ADDR_INDEX_SHIFT	12
+#define GSC_EVT0_IN_BASE_ADDR_PP_SHIFT		8
+#define GSC_EVT1_IN_CURR_ADDR_INDEX_SHIFT	24
+#define GSC_EVT1_IN_BASE_ADDR_PP_SHIFT		16
+#define GSC_IN_CURR_ADDR_INDEX		((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) ? \
+					(0xf << GSC_EVT1_IN_CURR_ADDR_INDEX_SHIFT) : \
+					(0xf << GSC_EVT0_IN_CURR_ADDR_INDEX_SHIFT))
+#define GSC_IN_CURR_GET_INDEX(x)	((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) ? \
+					((x) >> GSC_EVT1_IN_CURR_ADDR_INDEX_SHIFT) : \
+					((x) >> GSC_EVT0_IN_CURR_ADDR_INDEX_SHIFT))
+#define GSC_IN_BASE_ADDR_PINGPONG(x)	((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) ? \
+					((x) << GSC_EVT1_IN_BASE_ADDR_PP_SHIFT) : \
+					((x) << GSC_EVT0_IN_BASE_ADDR_PP_SHIFT))
+#define GSC_IN_BASE_ADDR_MASK		(0xff << 0)
+
+/* G-Scaler output y address mask */
+#define GSC_OUT_BASE_ADDR_Y_MASK	0x10C
+/* G-Scaler output y base address */
+#define GSC_OUT_BASE_ADDR_Y(n)		(0x110 + (n) * 0x4)
+
+/* G-Scaler output cb address mask */
+#define GSC_OUT_BASE_ADDR_CB_MASK	0x15C
+/* G-Scaler output cb base address */
+#define GSC_OUT_BASE_ADDR_CB(n)		(0x160 + (n) * 0x4)
+
+/* G-Scaler output cr address mask */
+#define GSC_OUT_BASE_ADDR_CR_MASK	0x1AC
+/* G-Scaler output cr base address */
+#define GSC_OUT_BASE_ADDR_CR(n)		(0x1B0 + (n) * 0x4)
+
+/* G-Scaler output address mask */
+#define GSC_OUT_CURR_ADDR_INDEX		(0xf << 24)
+#define GSC_OUT_CURR_GET_INDEX(x)	((x) >> 24)
+#define GSC_OUT_BASE_ADDR_PINGPONG(x)	((x) << 16)
+#define GSC_OUT_BASE_ADDR_MASK		(0xffff << 0)
+
+/* G-Scaler horizontal scaling filter */
+#define GSC_HCOEF(n, s, x)	(0x300 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
+
+/* G-Scaler vertical scaling filter */
+#define GSC_VCOEF(n, s, x)	(0x200 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
+
+/* G-Scaler BUS control */
+#define GSC_BUSCON			0xA78
+#define GSC_BUSCON_INT_TIME_MASK	(1 << 8)
+#define GSC_BUSCON_INT_DATA_TRANS	(0 << 8)
+#define GSC_BUSCON_INT_AXI_RESPONSE	(1 << 8)
+#define GSC_BUSCON_AWCACHE(x)		((x) << 4)
+#define GSC_BUSCON_ARCACHE(x)		((x) << 0)
+
+/* G-Scaler V position */
+#define GSC_VPOSITION			0xA7C
+#define GSC_VPOS_F(x)			((x) << 0)
+
+
+/* G-Scaler clock initial count */
+#define GSC_CLK_INIT_COUNT		0xC00
+#define GSC_CLK_GATE_MODE_INIT_CNT(x)	((x) << 0)
+
+/* G-Scaler clock snoop count */
+#define GSC_CLK_SNOOP_COUNT		0xC04
+#define GSC_CLK_GATE_MODE_SNOOP_CNT(x)	((x) << 0)
+
+#endif /* REGS_GSC_H_ */
diff --git a/drivers/media/video/exynos/mdev/Kconfig b/drivers/media/video/exynos/mdev/Kconfig
new file mode 100644
index 0000000..15134b0
--- /dev/null
+++ b/drivers/media/video/exynos/mdev/Kconfig
@@ -0,0 +1,8 @@
+config EXYNOS_MEDIA_DEVICE
+	bool
+	depends on MEDIA_EXYNOS
+	select MEDIA_CONTROLLER
+	select VIDEO_V4L2_SUBDEV_API
+	default y
+	help
+	  This is a v4l2 driver for exynos media device.
diff --git a/drivers/media/video/exynos/mdev/Makefile b/drivers/media/video/exynos/mdev/Makefile
new file mode 100644
index 0000000..175a4bc
--- /dev/null
+++ b/drivers/media/video/exynos/mdev/Makefile
@@ -0,0 +1,2 @@
+mdev-objs := exynos-mdev.o
+obj-$(CONFIG_EXYNOS_MEDIA_DEVICE)	+= mdev.o
diff --git a/drivers/media/video/exynos/mdev/exynos-mdev.c b/drivers/media/video/exynos/mdev/exynos-mdev.c
new file mode 100644
index 0000000..a76e7c3
--- /dev/null
+++ b/drivers/media/video/exynos/mdev/exynos-mdev.c
@@ -0,0 +1,115 @@
+/* drviers/media/video/exynos/mdev/exynos-mdev.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 SoC series media device driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <media/v4l2-ctrls.h>
+#include <media/media-device.h>
+#include <media/exynos_mc.h>
+
+static int __devinit mdev_probe(struct platform_device *pdev)
+{
+	struct v4l2_device *v4l2_dev;
+	struct exynos_md *mdev;
+	int ret;
+
+	mdev = kzalloc(sizeof(struct exynos_md), GFP_KERNEL);
+	if (!mdev)
+		return -ENOMEM;
+
+	mdev->id = pdev->id;
+	mdev->pdev = pdev;
+	spin_lock_init(&mdev->slock);
+
+	snprintf(mdev->media_dev.model, sizeof(mdev->media_dev.model), "%s%d",
+		 dev_name(&pdev->dev), mdev->id);
+
+	mdev->media_dev.dev = &pdev->dev;
+
+	v4l2_dev = &mdev->v4l2_dev;
+	v4l2_dev->mdev = &mdev->media_dev;
+	snprintf(v4l2_dev->name, sizeof(v4l2_dev->name), "%s",
+		 dev_name(&pdev->dev));
+
+	ret = v4l2_device_register(&pdev->dev, &mdev->v4l2_dev);
+	if (ret < 0) {
+		v4l2_err(v4l2_dev, "Failed to register v4l2_device: %d\n", ret);
+		goto err_v4l2_reg;
+	}
+	ret = media_device_register(&mdev->media_dev);
+	if (ret < 0) {
+		v4l2_err(v4l2_dev, "Failed to register media device: %d\n", ret);
+		goto err_mdev_reg;
+	}
+
+	platform_set_drvdata(pdev, mdev);
+	v4l2_info(v4l2_dev, "Media%d[0x%08x] was registered successfully\n",
+		  mdev->id, (unsigned int)mdev);
+	return 0;
+
+err_mdev_reg:
+	v4l2_device_unregister(&mdev->v4l2_dev);
+err_v4l2_reg:
+	kfree(mdev);
+	return ret;
+}
+
+static int __devexit mdev_remove(struct platform_device *pdev)
+{
+	struct exynos_md *mdev = platform_get_drvdata(pdev);
+
+	if (!mdev)
+		return 0;
+	media_device_unregister(&mdev->media_dev);
+	v4l2_device_unregister(&mdev->v4l2_dev);
+	kfree(mdev);
+	return 0;
+}
+
+static struct platform_driver mdev_driver = {
+	.probe		= mdev_probe,
+	.remove		= __devexit_p(mdev_remove),
+	.driver = {
+		.name	= MDEV_MODULE_NAME,
+		.owner	= THIS_MODULE,
+	}
+};
+
+int __init mdev_init(void)
+{
+	int ret = platform_driver_register(&mdev_driver);
+	if (ret)
+		err("platform_driver_register failed: %d\n", ret);
+	return ret;
+}
+
+void __exit mdev_exit(void)
+{
+	platform_driver_unregister(&mdev_driver);
+}
+
+module_init(mdev_init);
+module_exit(mdev_exit);
+
+MODULE_AUTHOR("Hyunwoong Kim <khw0178.kim@samsung.com>");
+MODULE_DESCRIPTION("EXYNOS5 SoC series media device driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/mipi-csis/Kconfig b/drivers/media/video/exynos/mipi-csis/Kconfig
new file mode 100644
index 0000000..9dd0e74
--- /dev/null
+++ b/drivers/media/video/exynos/mipi-csis/Kconfig
@@ -0,0 +1,8 @@
+config VIDEO_EXYNOS_MIPI_CSIS
+	bool "Exynos MIPI-CSIS driver"
+	depends on VIDEO_EXYNOS && VIDEO_EXYNOS_FIMC_LITE &&\
+		(ARCH_EXYNOS4 || ARCH_EXYNOS5)
+	select MEDIA_EXYNOS
+	default n
+	help
+	  This is a v4l2 driver for exynos mipi-csis interface device.
diff --git a/drivers/media/video/exynos/mipi-csis/Makefile b/drivers/media/video/exynos/mipi-csis/Makefile
new file mode 100644
index 0000000..1e64df7
--- /dev/null
+++ b/drivers/media/video/exynos/mipi-csis/Makefile
@@ -0,0 +1,2 @@
+exynos-mipi-csis-objs := mipi-csis.o
+obj-$(CONFIG_VIDEO_EXYNOS_MIPI_CSIS)	+= mipi-csis.o
diff --git a/drivers/media/video/exynos/mipi-csis/mipi-csis.c b/drivers/media/video/exynos/mipi-csis/mipi-csis.c
new file mode 100644
index 0000000..39f780d
--- /dev/null
+++ b/drivers/media/video/exynos/mipi-csis/mipi-csis.c
@@ -0,0 +1,889 @@
+/*
+ * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
+ *
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <media/exynos_mc.h>
+#include <plat/mipi_csis.h>
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Debug level (0-1)");
+
+#define MODULE_NAME			"s5p-mipi-csis"
+#define DEFAULT_CSIS_SINK_WIDTH		800
+#define DEFAULT_CSIS_SINK_HEIGHT	480
+#define CLK_NAME_SIZE			20
+
+enum csis_input_entity {
+	CSIS_INPUT_NONE,
+	CSIS_INPUT_SENSOR,
+};
+
+enum csis_output_entity {
+	CSIS_OUTPUT_NONE,
+	CSIS_OUTPUT_FLITE,
+};
+
+#define CSIS0_MAX_LANES		4
+#define CSIS1_MAX_LANES		2
+/* Register map definition */
+
+/* CSIS global control */
+#define S5PCSIS_CTRL			0x00
+#define S5PCSIS_CTRL_DPDN_DEFAULT	(0 << 31)
+#define S5PCSIS_CTRL_DPDN_SWAP		(1 << 31)
+#define S5PCSIS_CTRL_ALIGN_32BIT	(1 << 20)
+#define S5PCSIS_CTRL_UPDATE_SHADOW	(1 << 16)
+#define S5PCSIS_CTRL_WCLK_EXTCLK	(1 << 8)
+#define S5PCSIS_CTRL_RESET		(1 << 4)
+#define S5PCSIS_CTRL_ENABLE		(1 << 0)
+
+/* D-PHY control */
+#define S5PCSIS_DPHYCTRL		0x04
+#define S5PCSIS_DPHYCTRL_HSS_MASK	(0x1f << 27)
+#define S5PCSIS_DPHYCTRL_ENABLE		(0x1f << 0)
+
+#define S5PCSIS_CONFIG			0x08
+#define S5PCSIS_CFG_FMT_YCBCR422_8BIT	(0x1e << 2)
+#define S5PCSIS_CFG_FMT_RAW8		(0x2a << 2)
+#define S5PCSIS_CFG_FMT_RAW10		(0x2b << 2)
+#define S5PCSIS_CFG_FMT_RAW12		(0x2c << 2)
+/* User defined formats, x = 1...4 */
+#define S5PCSIS_CFG_FMT_USER(x)		((0x30 + x - 1) << 2)
+#define S5PCSIS_CFG_FMT_MASK		(0x3f << 2)
+#define S5PCSIS_CFG_NR_LANE_MASK	3
+
+/* Interrupt mask. */
+#define S5PCSIS_INTMSK			0x10
+#define S5PCSIS_INTMSK_EN_ALL		0xf000103f
+#define S5PCSIS_INTSRC			0x14
+
+/* Pixel resolution */
+#define S5PCSIS_RESOL			0x2c
+#define CSIS_MAX_PIX_WIDTH		0xffff
+#define CSIS_MAX_PIX_HEIGHT		0xffff
+#define CSIS_SRC_CLK			"mout_mpll_user"
+
+enum {
+	CSIS_CLK_MUX,
+	CSIS_CLK_GATE,
+};
+
+static char *csi_clock_name[] = {
+	[CSIS_CLK_MUX]  = "sclk_gscl_wrap",
+	[CSIS_CLK_GATE] = "gscl_wrap",
+};
+#define NUM_CSIS_CLOCKS	ARRAY_SIZE(csi_clock_name)
+
+enum {
+	ST_POWERED	= 1,
+	ST_STREAMING	= 2,
+	ST_SUSPENDED	= 4,
+};
+
+/**
+ * struct csis_state - the driver's internal state data structure
+ * @lock: mutex serializing the subdev and power management operations,
+ *        protecting @format and @flags members
+ * @pads: CSIS pads array
+ * @sd: v4l2_subdev associated with CSIS device instance
+ * @pdev: CSIS platform device
+ * @regs_res: requested I/O register memory resource
+ * @regs: mmaped I/O registers memory
+ * @clock: CSIS clocks
+ * @irq: requested s5p-mipi-csis irq number
+ * @flags: the state variable for power and streaming control
+ * @csis_fmt: current CSIS pixel format
+ * @format: common media bus format for the source and sink pad
+ */
+struct csis_state {
+	struct mutex lock;
+	struct media_pad pads[CSIS_PADS_NUM];
+	struct exynos_md *mdev;
+	struct v4l2_subdev sd;
+	struct platform_device *pdev;
+	struct resource *regs_res;
+	void __iomem *regs;
+	struct clk *clock[NUM_CSIS_CLOCKS];
+	int irq;
+	struct regulator *supply;
+	u32 flags;
+	const struct csis_pix_format *csis_fmt;
+	struct v4l2_mbus_framefmt format;
+	enum csis_input_entity		input;
+	enum csis_output_entity		output;
+};
+
+/**
+ * struct csis_pix_format - CSIS pixel format description
+ * @pix_width_alignment: horizontal pixel alignment, width will be
+ *                       multiple of 2^pix_width_alignment
+ * @code: corresponding media bus code
+ * @fmt_reg: S5PCSIS_CONFIG register value
+ */
+struct csis_pix_format {
+	unsigned int pix_width_alignment;
+	enum v4l2_mbus_pixelcode code;
+	u32 fmt_reg;
+};
+
+static const struct csis_pix_format s5pcsis_formats[] = {
+	{
+		.code = V4L2_MBUS_FMT_YUYV8_2X8,
+		.fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
+	}, {
+		.code = V4L2_MBUS_FMT_JPEG_1X8,
+		.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
+	},
+};
+
+#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
+#define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
+
+static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct csis_state, sd);
+}
+
+static const struct csis_pix_format *find_csis_format(
+	struct v4l2_mbus_framefmt *mf)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
+		if (mf->code == s5pcsis_formats[i].code)
+			return &s5pcsis_formats[i];
+	return NULL;
+}
+
+static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
+{
+	u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
+
+	val = on ? val | S5PCSIS_INTMSK_EN_ALL :
+		   val & ~S5PCSIS_INTMSK_EN_ALL;
+	s5pcsis_write(state, S5PCSIS_INTMSK, val);
+}
+
+static void s5pcsis_reset(struct csis_state *state)
+{
+	u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
+
+	s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
+	udelay(10);
+}
+
+static void s5pcsis_system_enable(struct csis_state *state, int on)
+{
+	u32 val;
+
+	val = s5pcsis_read(state, S5PCSIS_CTRL);
+	if (on)
+		val |= S5PCSIS_CTRL_ENABLE;
+	else
+		val &= ~S5PCSIS_CTRL_ENABLE;
+	s5pcsis_write(state, S5PCSIS_CTRL, val);
+
+	val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
+	if (on)
+		val |= S5PCSIS_DPHYCTRL_ENABLE;
+	else
+		val &= ~S5PCSIS_DPHYCTRL_ENABLE;
+	s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
+}
+
+/* Called with the state.lock mutex held */
+static void __s5pcsis_set_format(struct csis_state *state)
+{
+	struct v4l2_mbus_framefmt *mf = &state->format;
+	u32 val;
+
+	v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
+		 mf->code, mf->width, mf->height);
+
+	/* Color format */
+	val = s5pcsis_read(state, S5PCSIS_CONFIG);
+	val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
+	s5pcsis_write(state, S5PCSIS_CONFIG, val);
+
+	/* Pixel resolution */
+	val = (mf->width << 16) | mf->height;
+	s5pcsis_write(state, S5PCSIS_RESOL, val);
+}
+
+static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
+{
+	u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
+
+	val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
+	s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
+}
+
+static void s5pcsis_set_params(struct csis_state *state)
+{
+	struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
+	u32 val;
+
+	val = s5pcsis_read(state, S5PCSIS_CONFIG);
+	val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
+	s5pcsis_write(state, S5PCSIS_CONFIG, val);
+
+	__s5pcsis_set_format(state);
+	s5pcsis_set_hsync_settle(state, pdata->hs_settle);
+
+	val = s5pcsis_read(state, S5PCSIS_CTRL);
+	if (pdata->alignment == 32)
+		val |= S5PCSIS_CTRL_ALIGN_32BIT;
+	else /* 24-bits */
+		val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
+	/* using external clock. */
+	val |= S5PCSIS_CTRL_WCLK_EXTCLK;
+	s5pcsis_write(state, S5PCSIS_CTRL, val);
+
+	/* Update the shadow register. */
+	val = s5pcsis_read(state, S5PCSIS_CTRL);
+	s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
+}
+
+static void s5pcsis_clk_put(struct csis_state *state)
+{
+	int i;
+
+	for (i = 0; i < NUM_CSIS_CLOCKS; i++)
+		if (!IS_ERR_OR_NULL(state->clock[i]))
+			clk_put(state->clock[i]);
+}
+
+static int s5pcsis_clk_get(struct csis_state *state)
+{
+	struct device *dev = &state->pdev->dev;
+	int i;
+	char clk_name[CLK_NAME_SIZE];
+
+	for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
+		sprintf(clk_name, "%s%d", csi_clock_name[i], state->pdev->id);
+		state->clock[i] = clk_get(dev, clk_name);
+		if (IS_ERR(state->clock[i])) {
+			s5pcsis_clk_put(state);
+			dev_err(dev, "failed to get clock: %s\n",
+				csi_clock_name[i]);
+			return -ENXIO;
+		}
+	}
+	return 0;
+}
+
+static int s5pcsis_resume(struct device *dev);
+static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct csis_state *state = sd_to_csis_state(sd);
+	struct device *dev = &state->pdev->dev;
+
+	if (on) {
+#ifndef CONFIG_PM_RUNTIME
+		return s5pcsis_resume(dev);
+#else
+		return pm_runtime_get_sync(dev);
+#endif
+	}
+
+	return pm_runtime_put_sync(dev);
+}
+
+static void s5pcsis_start_stream(struct csis_state *state)
+{
+	s5pcsis_reset(state);
+	s5pcsis_set_params(state);
+	s5pcsis_system_enable(state, true);
+	s5pcsis_enable_interrupts(state, true);
+}
+
+static void s5pcsis_stop_stream(struct csis_state *state)
+{
+	s5pcsis_enable_interrupts(state, false);
+	s5pcsis_system_enable(state, false);
+}
+
+/* v4l2_subdev operations */
+static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct csis_state *state = sd_to_csis_state(sd);
+	int ret = 0;
+
+	v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
+		 __func__, enable, state->flags);
+
+	if (enable) {
+		ret = pm_runtime_get_sync(&state->pdev->dev);
+		if (ret && ret != 1)
+			return ret;
+	}
+	mutex_lock(&state->lock);
+	if (enable) {
+		if (state->flags & ST_SUSPENDED) {
+			ret = -EBUSY;
+			goto unlock;
+		}
+		s5pcsis_start_stream(state);
+		state->flags |= ST_STREAMING;
+	} else {
+		s5pcsis_stop_stream(state);
+		state->flags &= ~ST_STREAMING;
+	}
+unlock:
+	mutex_unlock(&state->lock);
+	if (!enable)
+		pm_runtime_put(&state->pdev->dev);
+
+	return ret == 1 ? 0 : ret;
+}
+
+static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
+				  struct v4l2_subdev_fh *fh,
+				  struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->index >= ARRAY_SIZE(s5pcsis_formats))
+		return -EINVAL;
+
+	code->code = s5pcsis_formats[code->index].code;
+	return 0;
+}
+
+static struct csis_pix_format const *s5pcsis_try_format(
+	struct v4l2_mbus_framefmt *mf)
+{
+	struct csis_pix_format const *csis_fmt;
+
+	csis_fmt = find_csis_format(mf);
+	if (csis_fmt == NULL)
+		csis_fmt = &s5pcsis_formats[0];
+
+	mf->code = csis_fmt->code;
+	v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
+			      csis_fmt->pix_width_alignment,
+			      &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
+			      0);
+	return csis_fmt;
+}
+
+static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
+		struct csis_state *state, struct v4l2_subdev_fh *fh,
+		u32 pad, enum v4l2_subdev_format_whence which)
+{
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
+
+	return &state->format;
+}
+
+static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+			   struct v4l2_subdev_format *fmt)
+{
+	struct csis_state *state = sd_to_csis_state(sd);
+	struct csis_pix_format const *csis_fmt;
+	struct v4l2_mbus_framefmt *mf;
+
+	mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
+
+	if (fmt->pad == CSIS_PAD_SOURCE) {
+		if (mf) {
+			mutex_lock(&state->lock);
+			fmt->format = *mf;
+			mutex_unlock(&state->lock);
+		}
+		return 0;
+	}
+	csis_fmt = s5pcsis_try_format(&fmt->format);
+	if (mf) {
+		mutex_lock(&state->lock);
+		*mf = fmt->format;
+		if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+			state->csis_fmt = csis_fmt;
+		mutex_unlock(&state->lock);
+	}
+	return 0;
+}
+
+static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+			   struct v4l2_subdev_format *fmt)
+{
+	struct csis_state *state = sd_to_csis_state(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
+		return -EINVAL;
+
+	mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
+	if (!mf)
+		return -EINVAL;
+
+	mutex_lock(&state->lock);
+	fmt->format = *mf;
+	mutex_unlock(&state->lock);
+
+	return 0;
+}
+
+static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
+	.s_power = s5pcsis_s_power,
+};
+
+static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
+	.enum_mbus_code = s5pcsis_enum_mbus_code,
+	.get_fmt = s5pcsis_get_fmt,
+	.set_fmt = s5pcsis_set_fmt,
+};
+
+static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
+	.s_stream = s5pcsis_s_stream,
+};
+
+static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
+	.core = &s5pcsis_core_ops,
+	.pad = &s5pcsis_pad_ops,
+	.video = &s5pcsis_video_ops,
+};
+
+static int s5pcsis_init_formats(struct v4l2_subdev *sd,
+				struct v4l2_subdev_fh *fh)
+{
+	struct v4l2_subdev_format format;
+
+	memset(&format, 0, sizeof(format));
+	format.pad = CSIS_PAD_SINK;
+	format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
+	format.format.code = s5pcsis_formats[0].code;
+	format.format.width = DEFAULT_CSIS_SINK_WIDTH;
+	format.format.height = DEFAULT_CSIS_SINK_HEIGHT;
+	s5pcsis_set_fmt(sd, fh, &format);
+
+	return 0;
+}
+
+static int s5pcsis_subdev_close(struct v4l2_subdev *sd,
+				struct v4l2_subdev_fh *fh)
+{
+	v4l2_info(sd, "%s\n", __func__);
+	return 0;
+}
+
+static int s5pcsis_subdev_registered(struct v4l2_subdev *sd)
+{
+	v4l2_dbg(1, debug, sd, "%s\n", __func__);
+	return 0;
+}
+
+static void s5pcsis_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	v4l2_dbg(1, debug, sd, "%s\n", __func__);
+}
+
+static const struct v4l2_subdev_internal_ops s5pcsis_v4l2_internal_ops = {
+	.open = s5pcsis_init_formats,
+	.close = s5pcsis_subdev_close,
+	.registered = s5pcsis_subdev_registered,
+	.unregistered = s5pcsis_subdev_unregistered,
+};
+
+static int s5pcsis_link_setup(struct media_entity *entity,
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
+{
+	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
+	struct csis_state *state = sd_to_csis_state(sd);
+
+	switch (local->index | media_entity_type(remote->entity)) {
+	case CSIS_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			v4l2_info(sd, "%s : sink link enabled\n", __func__);
+			state->input = CSIS_INPUT_SENSOR;
+		} else {
+			v4l2_info(sd, "%s : sink link disabled\n", __func__);
+			state->input = CSIS_INPUT_NONE;
+		}
+		break;
+
+	case CSIS_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
+		if (flags & MEDIA_LNK_FL_ENABLED) {
+			v4l2_info(sd, "%s : source link enabled\n", __func__);
+			state->output = CSIS_OUTPUT_FLITE;
+		} else {
+			v4l2_info(sd, "%s : source link disabled\n", __func__);
+			state->output = CSIS_OUTPUT_NONE;
+		}
+		break;
+
+	default:
+		v4l2_err(sd, "%s : ERR link\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct media_entity_operations s5pcsis_media_ops = {
+	.link_setup = s5pcsis_link_setup,
+};
+
+static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
+{
+	struct csis_state *state = dev_id;
+	u32 val;
+
+	/* Just clear the interrupt pending bits. */
+	val = s5pcsis_read(state, S5PCSIS_INTSRC);
+	s5pcsis_write(state, S5PCSIS_INTSRC, val);
+
+	v4l2_info(&state->sd, "%s : error : 0x%x\n", __func__, val);
+
+	return IRQ_HANDLED;
+}
+
+static int csis_get_md_callback(struct device *dev, void *p)
+{
+	struct exynos_md **md_list = p;
+	struct exynos_md *md = NULL;
+
+	md = dev_get_drvdata(dev);
+
+	if (md)
+		*(md_list + md->id) = md;
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct exynos_md *csis_get_capture_md(enum mdev_node node)
+{
+	struct device_driver *drv;
+	struct exynos_md *md[MDEV_MAX_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(MDEV_MODULE_NAME, &platform_bus_type);
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &md[0],
+				     csis_get_md_callback);
+	put_driver(drv);
+
+	return ret ? NULL : md[node];
+
+}
+
+static int __devinit s5pcsis_probe(struct platform_device *pdev)
+{
+	struct s5p_platform_mipi_csis *pdata;
+	struct resource *mem_res;
+	struct resource *regs_res;
+	struct csis_state *state;
+	int ret = -ENOMEM;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	mutex_init(&state->lock);
+	state->pdev = pdev;
+
+	pdata = pdev->dev.platform_data;
+	if (pdata == NULL || pdata->phy_enable == NULL) {
+		dev_err(&pdev->dev, "Platform data not fully specified\n");
+		goto e_free;
+	}
+
+	if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
+	    pdata->lanes > CSIS0_MAX_LANES) {
+		ret = -EINVAL;
+		dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
+			pdata->lanes);
+		goto e_free;
+	}
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "Failed to get IO memory region\n");
+		goto e_free;
+	}
+
+	regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
+				      pdev->name);
+	if (!regs_res) {
+		dev_err(&pdev->dev, "Failed to request IO memory region\n");
+		goto e_free;
+	}
+	state->regs_res = regs_res;
+
+	state->regs = ioremap(mem_res->start, resource_size(mem_res));
+	if (!state->regs) {
+		dev_err(&pdev->dev, "Failed to remap IO region\n");
+		goto e_reqmem;
+	}
+
+	ret = s5pcsis_clk_get(state);
+	if (ret)
+		goto e_unmap;
+
+	clk_enable(state->clock[CSIS_CLK_MUX]);
+	if (pdata->clk_rate) {
+		struct clk *srclk;
+		srclk = clk_get(&state->pdev->dev, CSIS_SRC_CLK);
+		if (IS_ERR_OR_NULL(srclk)) {
+			dev_err(&state->pdev->dev, "failed to get csis src clk\n");
+			goto e_unmap;
+		}
+		clk_set_parent(state->clock[CSIS_CLK_MUX], srclk);
+		clk_put(srclk);
+		clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
+	} else {
+		dev_WARN(&pdev->dev, "No clock frequency specified!\n");
+	}
+
+	state->irq = platform_get_irq(pdev, 0);
+	if (state->irq < 0) {
+		ret = state->irq;
+		dev_err(&pdev->dev, "Failed to get irq\n");
+		goto e_clkput;
+	}
+
+	if (!pdata->fixed_phy_vdd) {
+		state->supply = regulator_get(&pdev->dev, "mipi_csi");
+		if (IS_ERR(state->supply)) {
+			ret = PTR_ERR(state->supply);
+			state->supply = NULL;
+			goto e_clkput;
+		}
+	}
+
+	ret = request_irq(state->irq, s5pcsis_irq_handler, 0,
+			  dev_name(&pdev->dev), state);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq failed\n");
+		goto e_regput;
+	}
+
+	v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
+	state->sd.owner = THIS_MODULE;
+	state->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d\n",
+					MODULE_NAME, pdev->id);
+
+	state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&state->sd.entity,
+				CSIS_PADS_NUM, state->pads, 0);
+	if (ret < 0)
+		goto e_irqfree;
+
+	s5pcsis_init_formats(&state->sd, NULL);
+
+	state->sd.internal_ops = &s5pcsis_v4l2_internal_ops;
+	state->sd.entity.ops = &s5pcsis_media_ops;
+
+	state->mdev = csis_get_capture_md(MDEV_CAPTURE);
+	if (IS_ERR_OR_NULL(state->mdev))
+		goto e_irqfree;
+
+	state->mdev->csis_sd[pdev->id] = &state->sd;
+	state->sd.grp_id = CSIS_GRP_ID;
+	ret = v4l2_device_register_subdev(&state->mdev->v4l2_dev, &state->sd);
+	if (ret)
+		goto e_irqfree;
+	/* This allows to retrieve the platform device id by the host driver */
+	v4l2_set_subdevdata(&state->sd, pdev);
+
+	/* .. and a pointer to the subdev. */
+	platform_set_drvdata(pdev, &state->sd);
+
+	state->flags = ST_SUSPENDED;
+	pm_runtime_enable(&pdev->dev);
+
+	v4l2_info(&state->sd, "%s : csis%d probe success\n", __func__, pdev->id);
+	return 0;
+
+e_irqfree:
+	free_irq(state->irq, state);
+e_regput:
+	if (state->supply)
+		regulator_put(state->supply);
+e_clkput:
+	clk_disable(state->clock[CSIS_CLK_MUX]);
+	s5pcsis_clk_put(state);
+e_unmap:
+	iounmap(state->regs);
+e_reqmem:
+	release_mem_region(regs_res->start, resource_size(regs_res));
+e_free:
+	kfree(state);
+	return ret;
+}
+
+static int s5pcsis_suspend(struct device *dev)
+{
+	struct s5p_platform_mipi_csis *pdata = dev->platform_data;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct csis_state *state = sd_to_csis_state(sd);
+	int ret = 0;
+
+	v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
+		 __func__, state->flags);
+
+	mutex_lock(&state->lock);
+	if (state->flags & ST_POWERED) {
+		s5pcsis_stop_stream(state);
+		ret = pdata->phy_enable(state->pdev, false);
+		if (ret)
+			goto unlock;
+		if (state->supply) {
+			ret = regulator_disable(state->supply);
+			if (ret)
+				goto unlock;
+		}
+		clk_disable(state->clock[CSIS_CLK_GATE]);
+		state->flags &= ~ST_POWERED;
+	}
+	state->flags |= ST_SUSPENDED;
+ unlock:
+	mutex_unlock(&state->lock);
+	return ret ? -EAGAIN : 0;
+}
+
+static int s5pcsis_resume(struct device *dev)
+{
+	struct s5p_platform_mipi_csis *pdata = dev->platform_data;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct csis_state *state = sd_to_csis_state(sd);
+	int ret = 0;
+
+	v4l2_info(sd, "%s: flags: 0x%x\n", __func__, state->flags);
+
+	mutex_lock(&state->lock);
+	if (!(state->flags & ST_SUSPENDED))
+		goto unlock;
+
+	if (!(state->flags & ST_POWERED)) {
+		if (state->supply)
+			ret = regulator_enable(state->supply);
+		if (ret)
+			goto unlock;
+
+		ret = pdata->phy_enable(state->pdev, true);
+		if (!ret) {
+			state->flags |= ST_POWERED;
+		} else if (state->supply) {
+			regulator_disable(state->supply);
+			goto unlock;
+		}
+		clk_enable(state->clock[CSIS_CLK_GATE]);
+	}
+	if (state->flags & ST_STREAMING)
+		s5pcsis_start_stream(state);
+
+	state->flags &= ~ST_SUSPENDED;
+ unlock:
+	mutex_unlock(&state->lock);
+	return ret ? -EAGAIN : 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int s5pcsis_pm_suspend(struct device *dev)
+{
+	return s5pcsis_suspend(dev);
+}
+
+static int s5pcsis_pm_resume(struct device *dev)
+{
+	int ret;
+
+	ret = s5pcsis_resume(dev);
+
+	if (!ret) {
+		pm_runtime_disable(dev);
+		ret = pm_runtime_set_active(dev);
+		pm_runtime_enable(dev);
+	}
+
+	return ret;
+}
+#endif
+
+static int __devexit s5pcsis_remove(struct platform_device *pdev)
+{
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct csis_state *state = sd_to_csis_state(sd);
+	struct resource *res = state->regs_res;
+
+	pm_runtime_disable(&pdev->dev);
+	s5pcsis_suspend(&pdev->dev);
+	clk_disable(state->clock[CSIS_CLK_MUX]);
+	pm_runtime_set_suspended(&pdev->dev);
+
+	s5pcsis_clk_put(state);
+	if (state->supply)
+		regulator_put(state->supply);
+
+	media_entity_cleanup(&state->sd.entity);
+	free_irq(state->irq, state);
+	iounmap(state->regs);
+	release_mem_region(res->start, resource_size(res));
+	kfree(state);
+
+	return 0;
+}
+
+static const struct dev_pm_ops s5pcsis_pm_ops = {
+	SET_RUNTIME_PM_OPS(s5pcsis_suspend, s5pcsis_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_pm_suspend, s5pcsis_pm_resume)
+};
+
+static struct platform_driver s5pcsis_driver = {
+	.probe		= s5pcsis_probe,
+	.remove		= __devexit_p(s5pcsis_remove),
+	.driver		= {
+		.name	= MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &s5pcsis_pm_ops,
+	},
+};
+
+static int __init s5pcsis_init(void)
+{
+	return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe);
+}
+
+static void __exit s5pcsis_exit(void)
+{
+	platform_driver_unregister(&s5pcsis_driver);
+}
+
+module_init(s5pcsis_init);
+module_exit(s5pcsis_exit);
+
+MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
+MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/rotator/Kconfig b/drivers/media/video/exynos/rotator/Kconfig
new file mode 100644
index 0000000..b9a29cd
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/Kconfig
@@ -0,0 +1,12 @@
+config VIDEO_EXYNOS_ROTATOR
+	bool "EXYNOS Image Rotator Driver"
+	depends on VIDEO_EXYNOS && (ARCH_EXYNOS4 || ARCH_EXYNOS5)
+	select V4L2_MEM2MEM_DEV
+	default n
+	help
+	  This is a v4l2 driver for EXYNOS Image Rotator device.
+
+config VIDEO_SAMSUNG_MEMSIZE_ROT
+	int "Memory size in kbytes for ROTATOR"
+	depends on VIDEO_EXYNOS_ROTATOR
+	default "9216"
diff --git a/drivers/media/video/exynos/rotator/Makefile b/drivers/media/video/exynos/rotator/Makefile
new file mode 100644
index 0000000..6ad0d73
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2012 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com
+#
+# Licensed under GPLv2
+#
+
+rotator-objs := rotator-core.o rotator-regs.o rotator-vb2.o
+obj-$(CONFIG_VIDEO_EXYNOS_ROTATOR)	+= rotator.o
diff --git a/drivers/media/video/exynos/rotator/rotator-core.c b/drivers/media/video/exynos/rotator/rotator-core.c
new file mode 100644
index 0000000..5789de2
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/rotator-core.c
@@ -0,0 +1,1353 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Core file for Samsung EXYNOS Image Rotator driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/version.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+#include <mach/videonode.h>
+
+#include "rotator.h"
+
+int log_level;
+module_param_named(log_level, log_level, uint, 0644);
+
+static struct rot_fmt rot_formats[] = {
+	{
+		.name		= "RGB565",
+		.pixelformat	= V4L2_PIX_FMT_RGB565,
+		.num_planes	= 1,
+		.num_comp	= 1,
+		.bitperpixel	= { 16 },
+	}, {
+		.name		= "XRGB-8888, 32 bpp",
+		.pixelformat	= V4L2_PIX_FMT_RGB32,
+		.num_planes	= 1,
+		.num_comp	= 1,
+		.bitperpixel	= { 32 },
+	}, {
+		.name		= "YUV 4:2:2 packed, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+		.num_planes	= 1,
+		.num_comp	= 1,
+		.bitperpixel	= { 16 },
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12M,
+		.num_planes	= 2,
+		.num_comp	= 2,
+		.bitperpixel	= { 8, 4 },
+	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420M,
+		.num_planes	= 3,
+		.num_comp	= 3,
+		.bitperpixel	= { 8, 2, 2 },
+	},
+};
+
+/* Find the matches format */
+static struct rot_fmt *rot_find_format(struct v4l2_format *f)
+{
+	struct rot_fmt *rot_fmt;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(rot_formats); ++i) {
+		rot_fmt = &rot_formats[i];
+		if (rot_fmt->pixelformat == f->fmt.pix_mp.pixelformat)
+			return &rot_formats[i];
+	}
+
+	return NULL;
+}
+
+static void rot_bound_align_image(struct rot_ctx *ctx, struct rot_fmt *rot_fmt,
+			   u32 *width, u32 *height)
+{
+	struct exynos_rot_variant *variant = ctx->rot_dev->variant;
+	struct exynos_rot_size_limit *limit = NULL;
+
+	switch (rot_fmt->pixelformat) {
+	case V4L2_PIX_FMT_YUV420M:
+		limit = &variant->limit_yuv420_3p;
+		break;
+	case V4L2_PIX_FMT_NV12M:
+		limit = &variant->limit_yuv420_2p;
+		break;
+	case V4L2_PIX_FMT_YUYV:
+		limit = &variant->limit_yuv422;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+		limit =	&variant->limit_rgb565;
+		break;
+	case V4L2_PIX_FMT_RGB32:
+		limit = &variant->limit_rgb888;
+		break;
+	default:
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"not supported format values\n");
+		return;
+	}
+
+	/* Bound an image to have width and height in limit */
+	v4l_bound_align_image(width, limit->min_x, limit->max_x,
+			limit->align, height, limit->min_y,
+			limit->max_y, limit->align, 0);
+}
+
+static void rot_adjust_pixminfo(struct rot_ctx *ctx, struct rot_frame *frame,
+			 struct v4l2_pix_format_mplane *pixm)
+{
+	struct rot_frame *rot_frame;
+
+	if (frame == &ctx->s_frame) {
+		if (test_bit(CTX_DST, &ctx->flags)) {
+			rot_frame = &ctx->d_frame;
+			pixm->pixelformat = rot_frame->rot_fmt->pixelformat;
+		}
+		set_bit(CTX_SRC, &ctx->flags);
+	} else if (frame == &ctx->d_frame) {
+		if (test_bit(CTX_SRC, &ctx->flags)) {
+			rot_frame = &ctx->s_frame;
+			pixm->pixelformat = rot_frame->rot_fmt->pixelformat;
+		}
+		set_bit(CTX_DST, &ctx->flags);
+	}
+}
+
+static int rot_v4l2_querycap(struct file *file, void *fh,
+			     struct v4l2_capability *cap)
+{
+	strncpy(cap->driver, MODULE_NAME, sizeof(cap->driver) - 1);
+	strncpy(cap->card, MODULE_NAME, sizeof(cap->card) - 1);
+
+	cap->bus_info[0] = 0;
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+
+	return 0;
+}
+
+static int rot_v4l2_enum_fmt_mplane(struct file *file, void *fh,
+			     struct v4l2_fmtdesc *f)
+{
+	struct rot_fmt *rot_fmt;
+
+	if (f->index >= ARRAY_SIZE(rot_formats))
+		return -EINVAL;
+
+	rot_fmt = &rot_formats[f->index];
+	strncpy(f->description, rot_fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = rot_fmt->pixelformat;
+
+	return 0;
+}
+
+static int rot_v4l2_g_fmt_mplane(struct file *file, void *fh,
+			  struct v4l2_format *f)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_fmt *rot_fmt;
+	struct rot_frame *frame;
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	int i;
+
+	frame = ctx_get_frame(ctx, f->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	rot_fmt = frame->rot_fmt;
+
+	pixm->width		= frame->pix_mp.width;
+	pixm->height		= frame->pix_mp.height;
+	pixm->pixelformat	= frame->pix_mp.pixelformat;
+	pixm->field		= V4L2_FIELD_NONE;
+	pixm->num_planes	= frame->rot_fmt->num_planes;
+	pixm->colorspace	= 0;
+
+	for (i = 0; i < pixm->num_planes; ++i) {
+		pixm->plane_fmt[i].bytesperline = (pixm->width *
+				rot_fmt->bitperpixel[i]) >> 3;
+		pixm->plane_fmt[i].sizeimage = pixm->plane_fmt[i].bytesperline
+				* pixm->height;
+
+		v4l2_dbg(1, log_level, &ctx->rot_dev->m2m.v4l2_dev,
+				"[%d] plane: bytesperline %d, sizeimage %d\n",
+				i, pixm->plane_fmt[i].bytesperline,
+				pixm->plane_fmt[i].sizeimage);
+	}
+
+	return 0;
+}
+
+static int rot_v4l2_try_fmt_mplane(struct file *file, void *fh,
+			    struct v4l2_format *f)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_fmt *rot_fmt;
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	int i;
+
+	if (!V4L2_TYPE_IS_MULTIPLANAR(f->type)) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"not supported v4l2 type\n");
+		return -EINVAL;
+	}
+
+	rot_fmt = rot_find_format(f);
+	if (!rot_fmt) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"not supported format type\n");
+		return -EINVAL;
+	}
+
+	rot_bound_align_image(ctx, rot_fmt, &pixm->width, &pixm->height);
+
+	pixm->num_planes = rot_fmt->num_planes;
+	pixm->colorspace = 0;
+
+	for (i = 0; i < pixm->num_planes; ++i) {
+		pixm->plane_fmt[i].bytesperline = (pixm->width *
+				rot_fmt->bitperpixel[i]) >> 3;
+		pixm->plane_fmt[i].sizeimage = pixm->plane_fmt[i].bytesperline
+				* pixm->height;
+
+		v4l2_dbg(1, log_level, &ctx->rot_dev->m2m.v4l2_dev,
+				"[%d] plane: bytesperline %d, sizeimage %d\n",
+				i, pixm->plane_fmt[i].bytesperline,
+				pixm->plane_fmt[i].sizeimage);
+	}
+
+	return 0;
+}
+
+static int rot_v4l2_s_fmt_mplane(struct file *file, void *fh,
+				 struct v4l2_format *f)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+	struct rot_frame *frame;
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	int i, ret = 0;
+
+	if (vb2_is_streaming(vq)) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev, "device is busy\n");
+		return -EBUSY;
+	}
+
+	ret = rot_v4l2_try_fmt_mplane(file, fh, f);
+	if (ret < 0)
+		return ret;
+
+	frame = ctx_get_frame(ctx, f->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	set_bit(CTX_PARAMS, &ctx->flags);
+
+	frame->rot_fmt = rot_find_format(f);
+	if (!frame->rot_fmt) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"not supported format values\n");
+		return -EINVAL;
+	}
+
+	rot_adjust_pixminfo(ctx, frame, pixm);
+
+	frame->pix_mp.pixelformat = pixm->pixelformat;
+	frame->pix_mp.width	= pixm->width;
+	frame->pix_mp.height	= pixm->height;
+
+	/*
+	 * Shouldn't call s_crop or g_crop before called g_fmt or s_fmt.
+	 * Let's assume that we can keep the order.
+	 */
+	frame->crop.width	= pixm->width;
+	frame->crop.height	= pixm->height;
+
+	for (i = 0; i < frame->rot_fmt->num_planes; ++i)
+		frame->bytesused[i] = (pixm->width * pixm->height *
+				frame->rot_fmt->bitperpixel[i]) >> 3;
+
+	return 0;
+}
+
+static int rot_v4l2_reqbufs(struct file *file, void *fh,
+			    struct v4l2_requestbuffers *reqbufs)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_dev *rot = ctx->rot_dev;
+	struct rot_frame *frame;
+
+	frame = ctx_get_frame(ctx, reqbufs->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	if (frame == &ctx->s_frame)
+		clear_bit(CTX_SRC, &ctx->flags);
+	else if (frame == &ctx->d_frame)
+		clear_bit(CTX_DST, &ctx->flags);
+
+	rot->vb2->set_cacheable(rot->alloc_ctx, ctx->cacheable);
+
+	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
+}
+
+static int rot_v4l2_querybuf(struct file *file, void *fh,
+			     struct v4l2_buffer *buf)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
+}
+
+static int rot_v4l2_qbuf(struct file *file, void *fh,
+			 struct v4l2_buffer *buf)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int rot_v4l2_dqbuf(struct file *file, void *fh,
+			  struct v4l2_buffer *buf)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int rot_v4l2_streamon(struct file *file, void *fh,
+			     enum v4l2_buf_type type)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
+}
+
+static int rot_v4l2_streamoff(struct file *file, void *fh,
+			      enum v4l2_buf_type type)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
+}
+
+static int rot_v4l2_cropcap(struct file *file, void *fh,
+			    struct v4l2_cropcap *cr)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_frame *frame;
+
+	frame = ctx_get_frame(ctx, cr->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	cr->bounds.left		= 0;
+	cr->bounds.top		= 0;
+	cr->bounds.width	= frame->pix_mp.width;
+	cr->bounds.height	= frame->pix_mp.height;
+	cr->defrect		= cr->bounds;
+
+	return 0;
+}
+
+static int rot_v4l2_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_frame *frame;
+
+	frame = ctx_get_frame(ctx, cr->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	cr->c = frame->crop;
+
+	return 0;
+}
+
+static int rot_v4l2_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(fh);
+	struct rot_frame *frame;
+	struct v4l2_pix_format_mplane *pixm;
+	int i;
+
+	frame = ctx_get_frame(ctx, cr->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	if (!test_bit(CTX_PARAMS, &ctx->flags)) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"color format is not set\n");
+		return -EINVAL;
+	}
+
+	if (cr->c.left < 0 || cr->c.top < 0 ||
+			cr->c.width < 0 || cr->c.height < 0) {
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"crop value is negative\n");
+		return -EINVAL;
+	}
+
+	pixm = &frame->pix_mp;
+	rot_bound_align_image(ctx, frame->rot_fmt, &cr->c.width, &cr->c.height);
+
+	/* Adjust left/top if cropping rectangle is out of bounds */
+	if (cr->c.left + cr->c.width > pixm->width) {
+		dev_warn(ctx->rot_dev->dev,
+			"out of bound left cropping size:left %d, width %d\n",
+			cr->c.left, cr->c.width);
+		cr->c.left = pixm->width - cr->c.width;
+	}
+	if (cr->c.top + cr->c.height > pixm->height) {
+		dev_warn(ctx->rot_dev->dev,
+			"out of bound top cropping size:top %d, height %d\n",
+			cr->c.top, cr->c.height);
+		cr->c.top = pixm->height - cr->c.height;
+	}
+
+	frame->crop = cr->c;
+
+	for (i = 0; i < frame->rot_fmt->num_planes; ++i)
+		frame->bytesused[i] = (cr->c.width * cr->c.height *
+				frame->rot_fmt->bitperpixel[i]) >> 3;
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops rot_v4l2_ioctl_ops = {
+	.vidioc_querycap		= rot_v4l2_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= rot_v4l2_enum_fmt_mplane,
+	.vidioc_enum_fmt_vid_out_mplane	= rot_v4l2_enum_fmt_mplane,
+
+	.vidioc_g_fmt_vid_cap_mplane	= rot_v4l2_g_fmt_mplane,
+	.vidioc_g_fmt_vid_out_mplane	= rot_v4l2_g_fmt_mplane,
+
+	.vidioc_try_fmt_vid_cap_mplane	= rot_v4l2_try_fmt_mplane,
+	.vidioc_try_fmt_vid_out_mplane	= rot_v4l2_try_fmt_mplane,
+
+	.vidioc_s_fmt_vid_cap_mplane	= rot_v4l2_s_fmt_mplane,
+	.vidioc_s_fmt_vid_out_mplane	= rot_v4l2_s_fmt_mplane,
+
+	.vidioc_reqbufs			= rot_v4l2_reqbufs,
+	.vidioc_querybuf		= rot_v4l2_querybuf,
+
+	.vidioc_qbuf			= rot_v4l2_qbuf,
+	.vidioc_dqbuf			= rot_v4l2_dqbuf,
+
+	.vidioc_streamon		= rot_v4l2_streamon,
+	.vidioc_streamoff		= rot_v4l2_streamoff,
+
+	.vidioc_g_crop			= rot_v4l2_g_crop,
+	.vidioc_s_crop			= rot_v4l2_s_crop,
+	.vidioc_cropcap			= rot_v4l2_cropcap
+};
+
+static int rot_ctx_stop_req(struct rot_ctx *ctx)
+{
+	struct rot_ctx *curr_ctx;
+	struct rot_dev *rot = ctx->rot_dev;
+	int ret = 0;
+
+	curr_ctx = v4l2_m2m_get_curr_priv(rot->m2m.m2m_dev);
+	if (!test_bit(CTX_RUN, &ctx->flags) || (curr_ctx != ctx))
+		return 0;
+
+	set_bit(CTX_ABORT, &ctx->flags);
+
+	ret = wait_event_timeout(rot->wait,
+			!test_bit(CTX_RUN, &ctx->flags), ROT_TIMEOUT);
+
+	/* TODO: How to handle case of timeout event */
+	if (ret == 0) {
+		dev_err(rot->dev, "device failed to stop request\n");
+		ret = -EBUSY;
+	}
+
+	return ret;
+}
+
+static int rot_vb2_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+			       unsigned int *num_planes, unsigned long sizes[],
+			       void *alloc_ctxs[])
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vq);
+	struct rot_frame *frame;
+	int i;
+
+	frame = ctx_get_frame(ctx, vq->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	/* Get number of planes from format_list in driver */
+	*num_planes = frame->rot_fmt->num_planes;
+	for (i = 0; i < frame->rot_fmt->num_planes; i++) {
+		sizes[i] = (frame->pix_mp.width * frame->pix_mp.height *
+				frame->rot_fmt->bitperpixel[i]) >> 3;
+		alloc_ctxs[i] = ctx->rot_dev->alloc_ctx;
+	}
+
+	return 0;
+}
+
+static int rot_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct rot_frame *frame;
+	int i;
+
+	frame = ctx_get_frame(ctx, vb->vb2_queue->type);
+	if (IS_ERR(frame))
+		return PTR_ERR(frame);
+
+	if (!V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
+		for (i = 0; i < frame->rot_fmt->num_planes; i++)
+			vb2_set_plane_payload(vb, i, frame->bytesused[i]);
+	}
+
+	if (ctx->cacheable)
+		ctx->rot_dev->vb2->cache_flush(vb, frame->rot_fmt->num_planes);
+
+	return 0;
+}
+
+static void rot_vb2_buf_queue(struct vb2_buffer *vb)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (ctx->m2m_ctx)
+		v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
+}
+
+static void rot_vb2_lock(struct vb2_queue *vq)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_lock(&ctx->rot_dev->lock);
+}
+
+static void rot_vb2_unlock(struct vb2_queue *vq)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_unlock(&ctx->rot_dev->lock);
+}
+
+static int rot_vb2_start_streaming(struct vb2_queue *vq)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vq);
+	set_bit(CTX_STREAMING, &ctx->flags);
+
+	return 0;
+}
+
+static int rot_vb2_stop_streaming(struct vb2_queue *vq)
+{
+	struct rot_ctx *ctx = vb2_get_drv_priv(vq);
+	struct rot_dev *rot = ctx->rot_dev;
+	int ret;
+
+	ret = rot_ctx_stop_req(ctx);
+	if (ret < 0)
+		dev_err(ctx->rot_dev->dev, "wait timeout\n");
+
+	clear_bit(CTX_STREAMING, &ctx->flags);
+	v4l2_m2m_get_next_job(rot->m2m.m2m_dev, ctx->m2m_ctx);
+
+	return ret;
+}
+
+static struct vb2_ops rot_vb2_ops = {
+	.queue_setup		 = rot_vb2_queue_setup,
+	.buf_prepare		 = rot_vb2_buf_prepare,
+	.buf_queue		 = rot_vb2_buf_queue,
+	.wait_finish		 = rot_vb2_lock,
+	.wait_prepare		 = rot_vb2_unlock,
+	.start_streaming	 = rot_vb2_start_streaming,
+	.stop_streaming		 = rot_vb2_stop_streaming,
+};
+
+static int queue_init(void *priv, struct vb2_queue *src_vq,
+		      struct vb2_queue *dst_vq)
+{
+	struct rot_ctx *ctx = priv;
+	int ret;
+
+	memset(src_vq, 0, sizeof(*src_vq));
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	src_vq->ops = &rot_vb2_ops;
+	src_vq->mem_ops = ctx->rot_dev->vb2->ops;
+	src_vq->drv_priv = ctx;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	memset(dst_vq, 0, sizeof(*dst_vq));
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	dst_vq->ops = &rot_vb2_ops;
+	dst_vq->mem_ops = ctx->rot_dev->vb2->ops;
+	dst_vq->drv_priv = ctx;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+
+	return vb2_queue_init(dst_vq);
+}
+
+static int rot_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct rot_ctx *ctx;
+
+	rot_dbg("ctrl ID:%d, value:%d\n", ctrl->id, ctrl->val);
+	ctx = container_of(ctrl->handler, struct rot_ctx, ctrl_handler);
+
+	switch (ctrl->id) {
+	case V4L2_CID_VFLIP:
+		if (ctrl->val)
+			ctx->flip |= ROT_VFLIP;
+		else
+			ctx->flip &= ~ROT_VFLIP;
+		break;
+	case V4L2_CID_HFLIP:
+		if (ctrl->val)
+			ctx->flip |= ROT_HFLIP;
+		else
+			ctx->flip &= ~ROT_HFLIP;
+		break;
+	case V4L2_CID_ROTATE:
+		ctx->rotation = ctrl->val;
+		break;
+	case V4L2_CID_CACHEABLE:
+		ctx->cacheable = (bool)ctrl->val;
+		break;
+	}
+
+	return 0;
+}
+
+static const struct v4l2_ctrl_ops rot_ctrl_ops = {
+	.s_ctrl = rot_s_ctrl,
+};
+
+static const struct v4l2_ctrl_config rot_custom_ctrl[] = {
+	{
+		.ops = &rot_ctrl_ops,
+		.id = V4L2_CID_CACHEABLE,
+		.name = "set cacheable",
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = 1,
+		.def = true,
+	}
+};
+
+static int rot_add_ctrls(struct rot_ctx *ctx)
+{
+	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
+			V4L2_CID_VFLIP, 0, 1, 1, 0);
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
+			V4L2_CID_HFLIP, 0, 1, 1, 0);
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
+			V4L2_CID_ROTATE, 0, 270, 90, 0);
+	v4l2_ctrl_new_custom(&ctx->ctrl_handler, &rot_custom_ctrl[0], NULL);
+
+	if (ctx->ctrl_handler.error) {
+		int err = ctx->ctrl_handler.error;
+		v4l2_err(&ctx->rot_dev->m2m.v4l2_dev,
+				"v4l2_ctrl_handler_init failed\n");
+		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+		return err;
+	}
+
+	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
+
+	return 0;
+}
+
+static int rot_open(struct file *file)
+{
+	struct rot_dev *rot = video_drvdata(file);
+	struct rot_ctx *ctx;
+	int ret;
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx) {
+		dev_err(rot->dev, "no memory for open context\n");
+		return -ENOMEM;
+	}
+
+	atomic_inc(&rot->m2m.in_use);
+	ctx->rot_dev = rot;
+
+	v4l2_fh_init(&ctx->fh, rot->m2m.vfd);
+	ret = rot_add_ctrls(ctx);
+	if (ret)
+		goto err_fh;
+
+	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+	file->private_data = &ctx->fh;
+	v4l2_fh_add(&ctx->fh);
+
+	/* Default color format */
+	ctx->s_frame.rot_fmt = &rot_formats[0];
+	ctx->d_frame.rot_fmt = &rot_formats[0];
+	init_waitqueue_head(&rot->wait);
+	spin_lock_init(&ctx->slock);
+
+	/* Setup the device context for mem2mem mode. */
+	ctx->m2m_ctx = v4l2_m2m_ctx_init(rot->m2m.m2m_dev, ctx, queue_init);
+	if (IS_ERR(ctx->m2m_ctx)) {
+		ret = -EINVAL;
+		goto err_ctx;
+	}
+
+	return 0;
+
+err_ctx:
+	v4l2_fh_del(&ctx->fh);
+err_fh:
+	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+	v4l2_fh_exit(&ctx->fh);
+	atomic_dec(&rot->m2m.in_use);
+	kfree(ctx);
+
+	return ret;
+}
+
+static int rot_release(struct file *file)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(file->private_data);
+	struct rot_dev *rot = ctx->rot_dev;
+
+	rot_dbg("refcnt= %d", atomic_read(&rot->m2m.in_use));
+
+	v4l2_m2m_ctx_release(ctx->m2m_ctx);
+	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+	atomic_dec(&rot->m2m.in_use);
+	kfree(ctx);
+
+	return 0;
+}
+
+static unsigned int rot_poll(struct file *file,
+			     struct poll_table_struct *wait)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(file->private_data);
+
+	return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
+}
+
+static int rot_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct rot_ctx *ctx = fh_to_rot_ctx(file->private_data);
+
+	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
+}
+
+static const struct v4l2_file_operations rot_v4l2_fops = {
+	.owner		= THIS_MODULE,
+	.open		= rot_open,
+	.release	= rot_release,
+	.poll		= rot_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= rot_mmap,
+};
+
+static void rot_clock_gating(struct rot_dev *rot, enum rot_clk_status status)
+{
+	int clk_cnt;
+
+	if (status == ROT_CLK_ON) {
+		clk_cnt = atomic_inc_return(&rot->clk_cnt);
+		if (clk_cnt == 1) {
+			clk_enable(rot->clock);
+			rot->vb2->resume(rot->alloc_ctx);
+		}
+	} else if (status == ROT_CLK_OFF) {
+		clk_cnt = atomic_dec_return(&rot->clk_cnt);
+		if (clk_cnt == 0) {
+			rot->vb2->suspend(rot->alloc_ctx);
+			clk_disable(rot->clock);
+		} else if (clk_cnt < 0) {
+			dev_err(rot->dev, "rotator clock control is wrong!!\n");
+			atomic_set(&rot->clk_cnt, 0);
+		}
+	}
+}
+
+static void rot_watchdog(unsigned long arg)
+{
+	struct rot_dev *rot = (struct rot_dev *)arg;
+	struct rot_ctx *ctx;
+	unsigned long flags;
+	struct vb2_buffer *src_vb, *dst_vb;
+
+	rot_dbg("timeout watchdog\n");
+	if (atomic_read(&rot->wdt.cnt) >= ROT_WDT_CNT) {
+		rot_clock_gating(rot, ROT_CLK_OFF);
+
+		rot_dbg("wakeup blocked process\n");
+		atomic_set(&rot->wdt.cnt, 0);
+		clear_bit(DEV_RUN, &rot->state);
+
+		ctx = v4l2_m2m_get_curr_priv(rot->m2m.m2m_dev);
+		if (!ctx || !ctx->m2m_ctx) {
+			dev_err(rot->dev, "current ctx is NULL\n");
+			return;
+		}
+		spin_lock_irqsave(&rot->slock, flags);
+		clear_bit(CTX_RUN, &ctx->flags);
+		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+
+		if (src_vb && dst_vb) {
+			v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
+			v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
+
+			v4l2_m2m_job_finish(rot->m2m.m2m_dev, ctx->m2m_ctx);
+		}
+		spin_unlock_irqrestore(&rot->slock, flags);
+		return;
+	}
+
+	if (test_bit(DEV_RUN, &rot->state)) {
+		atomic_inc(&rot->wdt.cnt);
+		dev_err(rot->dev, "rotator is still running\n");
+		rot->wdt.timer.expires = jiffies + ROT_TIMEOUT;
+		add_timer(&rot->wdt.timer);
+	} else {
+		rot_dbg("rotator finished job\n");
+	}
+}
+
+static irqreturn_t rot_irq_handler(int irq, void *priv)
+{
+	struct rot_dev *rot = priv;
+	struct rot_ctx *ctx;
+	struct vb2_buffer *src_vb, *dst_vb;
+	unsigned int irq_src;
+
+	spin_lock(&rot->slock);
+
+	clear_bit(DEV_RUN, &rot->state);
+	if (timer_pending(&rot->wdt.timer))
+		del_timer(&rot->wdt.timer);
+
+	rot_hwget_irq_src(rot, &irq_src);
+	rot_hwset_irq_clear(rot, &irq_src);
+
+	if (irq_src != ISR_PEND_DONE) {
+		dev_err(rot->dev, "####################\n");
+		dev_err(rot->dev, "Illegal SFR configuration\n");
+		dev_err(rot->dev, "The result might be wrong\n");
+		dev_err(rot->dev, "####################\n");
+		rot_dump_registers(rot);
+	}
+
+	rot_clock_gating(rot, ROT_CLK_OFF);
+
+	ctx = v4l2_m2m_get_curr_priv(rot->m2m.m2m_dev);
+	if (!ctx || !ctx->m2m_ctx) {
+		dev_err(rot->dev, "current ctx is NULL\n");
+		goto isr_unlock;
+	}
+
+	clear_bit(CTX_RUN, &ctx->flags);
+
+	src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+	dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+
+	if (src_vb && dst_vb) {
+		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
+		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
+
+		if (test_bit(DEV_SUSPEND, &rot->state)) {
+			rot_dbg("wake up blocked process by suspend\n");
+			wake_up(&rot->wait);
+		} else {
+			v4l2_m2m_job_finish(rot->m2m.m2m_dev, ctx->m2m_ctx);
+		}
+
+		/* Wake up from CTX_ABORT state */
+		if (test_and_clear_bit(CTX_ABORT, &ctx->flags))
+			wake_up(&rot->wait);
+	} else {
+		dev_err(rot->dev, "failed to get the buffer done\n");
+	}
+
+isr_unlock:
+	spin_unlock(&rot->slock);
+
+	return IRQ_HANDLED;
+}
+
+static void rot_get_bufaddr(struct rot_dev *rot, struct vb2_buffer *vb,
+		     struct rot_frame *frame, struct rot_addr *addr)
+{
+	unsigned int pix_size;
+
+	pix_size = frame->pix_mp.width * frame->pix_mp.height;
+
+	addr->y = rot->vb2->plane_addr(vb, 0);
+	addr->cb = 0;
+	addr->cr = 0;
+
+	switch (frame->rot_fmt->num_comp) {
+	case 2:
+		if (frame->rot_fmt->num_planes == 1)
+			addr->cb = addr->y + pix_size;
+		else if (frame->rot_fmt->num_planes == 2)
+			addr->cb = rot->vb2->plane_addr(vb, 1);
+		break;
+	case 3:
+		if (frame->rot_fmt->num_planes == 3) {
+			addr->cb = rot->vb2->plane_addr(vb, 1);
+			addr->cr = rot->vb2->plane_addr(vb, 2);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static void rot_set_frame_addr(struct rot_ctx *ctx)
+{
+	struct vb2_buffer *vb;
+	struct rot_frame *s_frame, *d_frame;
+	struct rot_dev *rot = ctx->rot_dev;
+
+	s_frame = &ctx->s_frame;
+	d_frame = &ctx->d_frame;
+
+	/* set source buffer address */
+	vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
+	rot_get_bufaddr(rot, vb, s_frame, &s_frame->addr);
+
+	rot_hwset_src_addr(rot, s_frame->addr.y, ROT_ADDR_Y);
+	rot_hwset_src_addr(rot, s_frame->addr.cb, ROT_ADDR_CB);
+	rot_hwset_src_addr(rot, s_frame->addr.cr, ROT_ADDR_CR);
+
+	/* set destination buffer address */
+	vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
+	rot_get_bufaddr(rot, vb, d_frame, &d_frame->addr);
+
+	rot_hwset_dst_addr(rot, d_frame->addr.y, ROT_ADDR_Y);
+	rot_hwset_dst_addr(rot, d_frame->addr.cb, ROT_ADDR_CB);
+	rot_hwset_dst_addr(rot, d_frame->addr.cr, ROT_ADDR_CR);
+}
+
+static void rot_mapping_flip(struct rot_ctx *ctx, u32 *degree, u32 *flip)
+{
+	*degree = ctx->rotation;
+	*flip = ctx->flip;
+
+	if (ctx->flip == (ROT_VFLIP | ROT_HFLIP)) {
+		*flip = ROT_NOFLIP;
+		switch (ctx->rotation) {
+		case 0:
+			*degree = 180;
+			break;
+		case 90:
+			*degree = 270;
+			break;
+		case 180:
+			*degree = 0;
+			break;
+		case 270:
+			*degree = 90;
+			break;
+		}
+	}
+}
+
+static void rot_m2m_device_run(void *priv)
+{
+	struct rot_ctx *ctx = priv;
+	struct rot_frame *s_frame, *d_frame;
+	struct rot_dev *rot;
+	unsigned long flags;
+	u32 degree = 0, flip = 0;
+
+	spin_lock_irqsave(&ctx->slock, flags);
+
+	rot = ctx->rot_dev;
+
+	if (test_bit(DEV_RUN, &rot->state)) {
+		dev_err(rot->dev, "Rotator is already in progress\n");
+		goto run_unlock;
+	}
+
+	if (test_bit(DEV_SUSPEND, &rot->state)) {
+		dev_err(rot->dev, "Rotator is in suspend state\n");
+		goto run_unlock;
+	}
+
+	if (test_bit(CTX_ABORT, &ctx->flags)) {
+		rot_dbg("aborted rot device run\n");
+		goto run_unlock;
+	}
+
+	rot_clock_gating(rot, ROT_CLK_ON);
+
+	s_frame = &ctx->s_frame;
+	d_frame = &ctx->d_frame;
+
+	/* Configuration rotator registers */
+	rot_hwset_image_format(rot, s_frame->rot_fmt->pixelformat);
+	rot_mapping_flip(ctx, &degree, &flip);
+	rot_hwset_flip(rot, flip);
+	rot_hwset_rotation(rot, degree);
+
+	rot_hwset_src_imgsize(rot, s_frame);
+	rot_hwset_dst_imgsize(rot, d_frame);
+
+	rot_hwset_src_crop(rot, &s_frame->crop);
+	rot_hwset_dst_crop(rot, &d_frame->crop);
+
+	rot_set_frame_addr(ctx);
+
+	/* Enable rotator interrupt */
+	rot_hwset_irq_frame_done(rot, 1);
+	rot_hwset_irq_illegal_config(rot, 1);
+
+	set_bit(DEV_RUN, &rot->state);
+	set_bit(CTX_RUN, &ctx->flags);
+
+	/* Start rotate operation */
+	rot_hwset_start(rot);
+
+	/* Start watchdog timer */
+	rot->wdt.timer.expires = jiffies + ROT_TIMEOUT;
+	if (timer_pending(&rot->wdt.timer) == 0)
+		add_timer(&rot->wdt.timer);
+	else
+		mod_timer(&rot->wdt.timer, rot->wdt.timer.expires);
+
+run_unlock:
+	spin_unlock_irqrestore(&ctx->slock, flags);
+}
+
+static void rot_m2m_job_abort(void *priv)
+{
+	struct rot_ctx *ctx = priv;
+	struct rot_dev *rot = ctx->rot_dev;
+	int ret;
+
+	ret = rot_ctx_stop_req(ctx);
+	if (ret < 0)
+		dev_err(ctx->rot_dev->dev, "wait timeout\n");
+
+	v4l2_m2m_get_next_job(rot->m2m.m2m_dev, ctx->m2m_ctx);
+}
+
+static struct v4l2_m2m_ops rot_m2m_ops = {
+	.device_run	= rot_m2m_device_run,
+	.job_abort	= rot_m2m_job_abort,
+};
+
+static int rot_register_m2m_device(struct rot_dev *rot)
+{
+	struct v4l2_device *v4l2_dev;
+	struct device *dev;
+	struct video_device *vfd;
+	int ret = 0;
+
+	if (!rot)
+		return -ENODEV;
+
+	dev = rot->dev;
+	v4l2_dev = &rot->m2m.v4l2_dev;
+
+	snprintf(v4l2_dev->name, sizeof(v4l2_dev->name), "%s.m2m",
+			MODULE_NAME);
+
+	ret = v4l2_device_register(dev, v4l2_dev);
+	if (ret) {
+		dev_err(rot->dev, "failed to register v4l2 device\n");
+		return ret;
+	}
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		dev_err(rot->dev, "failed to allocate video device\n");
+		goto err_v4l2_dev;
+	}
+
+	vfd->fops	= &rot_v4l2_fops;
+	vfd->ioctl_ops	= &rot_v4l2_ioctl_ops;
+	vfd->release	= video_device_release;
+	snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", MODULE_NAME);
+
+	video_set_drvdata(vfd, rot);
+
+	rot->m2m.vfd = vfd;
+	rot->m2m.m2m_dev = v4l2_m2m_init(&rot_m2m_ops);
+	if (IS_ERR(rot->m2m.m2m_dev)) {
+		dev_err(rot->dev, "failed to initialize v4l2-m2m device\n");
+		ret = PTR_ERR(rot->m2m.m2m_dev);
+		goto err_dev_alloc;
+	}
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER,
+						EXYNOS_VIDEONODE_ROTATOR);
+	if (ret) {
+		dev_err(rot->dev, "failed to register video device\n");
+		goto err_m2m_dev;
+	}
+
+	return 0;
+
+err_m2m_dev:
+	v4l2_m2m_release(rot->m2m.m2m_dev);
+err_dev_alloc:
+	video_device_release(rot->m2m.vfd);
+err_v4l2_dev:
+	v4l2_device_unregister(v4l2_dev);
+
+	return ret;
+}
+
+static int rot_suspend(struct device *dev)
+{
+	struct rot_dev *rot = dev_get_drvdata(dev);
+	int ret;
+
+	set_bit(DEV_SUSPEND, &rot->state);
+
+	ret = wait_event_timeout(rot->wait,
+			!test_bit(DEV_RUN, &rot->state), ROT_TIMEOUT);
+	if (ret == 0)
+		dev_err(rot->dev, "wait timeout\n");
+
+	return 0;
+}
+
+static int rot_resume(struct device *dev)
+{
+	struct rot_dev *rot = dev_get_drvdata(dev);
+
+	clear_bit(DEV_SUSPEND, &rot->state);
+
+	return 0;
+}
+
+static const struct dev_pm_ops rot_pm_ops = {
+	.suspend		= rot_suspend,
+	.resume			= rot_resume,
+};
+
+static int rot_probe(struct platform_device *pdev)
+{
+	struct exynos_rot_driverdata *drv_data;
+	struct rot_dev *rot;
+	struct resource *res;
+	int variant_num, ret = 0;
+
+	dev_info(&pdev->dev, "++%s\n", __func__);
+	drv_data = (struct exynos_rot_driverdata *)
+			platform_get_device_id(pdev)->driver_data;
+
+	if (pdev->id >= drv_data->nr_dev) {
+		dev_err(&pdev->dev, "Invalid platform device id\n");
+		return -EINVAL;
+	}
+
+	rot = devm_kzalloc(&pdev->dev, sizeof(struct rot_dev), GFP_KERNEL);
+	if (!rot) {
+		dev_err(&pdev->dev, "no memory for rotator device\n");
+		return -ENOMEM;
+	}
+
+	rot->dev = &pdev->dev;
+	rot->id = pdev->id;
+	variant_num = (rot->id < 0) ? 0 : rot->id;
+	rot->variant = drv_data->variant[variant_num];
+
+	spin_lock_init(&rot->slock);
+
+	/* Get memory resource and map SFR region. */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to find the registers\n");
+		return -ENXIO;
+
+	}
+
+	rot->regs_res = request_mem_region(res->start, resource_size(res),
+			dev_name(&pdev->dev));
+	if (!rot->regs_res) {
+		dev_err(&pdev->dev, "failed to claim register region\n");
+		return -ENOENT;
+	}
+
+	rot->regs = ioremap(res->start, resource_size(res));
+	if (!rot->regs) {
+		dev_err(&pdev->dev, "failed to map register\n");
+		ret = -ENXIO;
+		goto err_req_region;
+	}
+
+	/* Get IRQ resource and register IRQ handler. */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get IRQ resource\n");
+		ret = -ENXIO;
+		goto err_ioremap;
+	}
+
+	ret = devm_request_irq(&pdev->dev, res->start, rot_irq_handler, 0,
+			pdev->name, rot);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to install irq\n");
+		goto err_ioremap;
+	}
+
+	atomic_set(&rot->wdt.cnt, 0);
+	setup_timer(&rot->wdt.timer, rot_watchdog, (unsigned long)rot);
+
+	rot->clock = clk_get(rot->dev, "rotator");
+	if (IS_ERR(rot->clock)) {
+		dev_err(&pdev->dev, "failed to get clock for rotator\n");
+		goto err_ioremap;
+	}
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	rot->vb2 = &rot_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	rot->vb2 = &rot_vb2_ion;
+#endif
+
+	rot->alloc_ctx = rot->vb2->init(rot);
+	platform_set_drvdata(pdev, rot);
+
+	ret = rot_register_m2m_device(rot);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register m2m device\n");
+		ret = -EPERM;
+		goto err_clk;
+	}
+	dev_info(&pdev->dev, "rotator registered successfully\n");
+
+	return 0;
+
+err_clk:
+	clk_put(rot->clock);
+err_ioremap:
+	iounmap(rot->regs);
+err_req_region:
+	release_mem_region(rot->regs_res->start,
+			resource_size(rot->regs_res));
+	return ret;
+}
+
+static int rot_remove(struct platform_device *pdev)
+{
+	struct rot_dev *rot = platform_get_drvdata(pdev);
+
+	clk_put(rot->clock);
+
+	if (timer_pending(&rot->wdt.timer))
+		del_timer(&rot->wdt.timer);
+
+	release_mem_region(rot->regs_res->start,
+			resource_size(rot->regs_res));
+
+	return 0;
+}
+
+static struct exynos_rot_variant rot_variant_exynos = {
+	.limit_rgb565 = {
+		.min_x = 16,
+		.min_y = 16,
+		.max_x = SZ_16K,
+		.max_y = SZ_16K,
+		.align = 2,
+	},
+	.limit_rgb888 = {
+		.min_x = 8,
+		.min_y = 8,
+		.max_x = SZ_8K,
+		.max_y = SZ_8K,
+		.align = 2,
+	},
+	.limit_yuv422 = {
+		.min_x = 16,
+		.min_y = 16,
+		.max_x = SZ_16K,
+		.max_y = SZ_16K,
+		.align = 2,
+	},
+	.limit_yuv420_2p = {
+		.min_x = 32,
+		.min_y = 32,
+		.max_x = SZ_32K,
+		.max_y = SZ_32K,
+		.align = 3,
+	},
+	.limit_yuv420_3p = {
+		.min_x = 64,
+		.min_y = 32,
+		.max_x = SZ_32K,
+		.max_y = SZ_32K,
+		.align = 4,
+	},
+};
+
+static struct exynos_rot_driverdata rot_drvdata_exynos = {
+	.variant = {
+		[0] = &rot_variant_exynos,
+	},
+	.nr_dev = 1,
+};
+
+static struct platform_device_id rot_driver_ids[] = {
+	{
+		.name		= MODULE_NAME,
+		.driver_data	= (unsigned long)&rot_drvdata_exynos,
+	},
+	{},
+};
+
+static struct platform_driver rot_driver = {
+	.probe		= rot_probe,
+	.remove		= rot_remove,
+	.id_table	= rot_driver_ids,
+	.driver = {
+		.name	= MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &rot_pm_ops,
+	}
+};
+
+static int __init rot_init(void)
+{
+	return platform_driver_register(&rot_driver);
+}
+
+static void __exit rot_exit(void)
+{
+	platform_driver_unregister(&rot_driver);
+}
+
+module_init(rot_init);
+module_exit(rot_exit);
+
+MODULE_AUTHOR("Sunyoung, Kang <sy0816.kang@samsung.com>");
+MODULE_AUTHOR("Ayoung, Sim <a.sim@samsung.com>");
+MODULE_DESCRIPTION("Exynos Image Rotator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/rotator/rotator-regs.c b/drivers/media/video/exynos/rotator/rotator-regs.c
new file mode 100644
index 0000000..9f983bf
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/rotator-regs.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Register interface file for Exynos Rotator driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "rotator.h"
+
+void rot_hwset_irq_frame_done(struct rot_dev *rot, u32 enable)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONFIG);
+
+	if (enable)
+		cfg |= ROTATOR_CONFIG_IRQ_DONE;
+	else
+		cfg &= ~ROTATOR_CONFIG_IRQ_DONE;
+
+	writel(cfg, rot->regs + ROTATOR_CONFIG);
+}
+
+void rot_hwset_irq_illegal_config(struct rot_dev *rot, u32 enable)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONFIG);
+
+	if (enable)
+		cfg |= ROTATOR_CONFIG_IRQ_ILLEGAL;
+	else
+		cfg &= ~ROTATOR_CONFIG_IRQ_ILLEGAL;
+
+	writel(cfg, rot->regs + ROTATOR_CONFIG);
+}
+
+int rot_hwset_image_format(struct rot_dev *rot, u32 pixelformat)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONTROL);
+	cfg &= ~ROTATOR_CONTROL_FMT_MASK;
+
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_YUV420M:
+		cfg |= ROTATOR_CONTROL_FMT_YCBCR420_3P;
+		break;
+	case V4L2_PIX_FMT_NV12M:
+		cfg |= ROTATOR_CONTROL_FMT_YCBCR420_2P;
+		break;
+	case V4L2_PIX_FMT_YUYV:
+		cfg |= ROTATOR_CONTROL_FMT_YCBCR422;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+		cfg |= ROTATOR_CONTROL_FMT_RGB565;
+		break;
+	case V4L2_PIX_FMT_RGB32:
+		cfg |= ROTATOR_CONTROL_FMT_RGB888;
+		break;
+	default:
+		dev_err(rot->dev, "invalid pixelformat type\n");
+		return -EINVAL;
+	}
+	writel(cfg, rot->regs + ROTATOR_CONTROL);
+	return 0;
+}
+
+void rot_hwset_flip(struct rot_dev *rot, u32 direction)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONTROL);
+	cfg &= ~ROTATOR_CONTROL_FLIP_MASK;
+
+	if (direction == ROT_VFLIP)
+		cfg |= ROTATOR_CONTROL_FLIP_V;
+	else if (direction == ROT_HFLIP)
+		cfg |= ROTATOR_CONTROL_FLIP_H;
+
+	writel(cfg, rot->regs + ROTATOR_CONTROL);
+}
+
+void rot_hwset_rotation(struct rot_dev *rot, int degree)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONTROL);
+	cfg &= ~ROTATOR_CONTROL_ROT_MASK;
+
+	if (degree == 90)
+		cfg |= ROTATOR_CONTROL_ROT_90;
+	else if (degree == 180)
+		cfg |= ROTATOR_CONTROL_ROT_180;
+	else if (degree == 270)
+		cfg |= ROTATOR_CONTROL_ROT_270;
+
+	writel(cfg, rot->regs + ROTATOR_CONTROL);
+}
+
+void rot_hwset_start(struct rot_dev *rot)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_CONTROL);
+
+	cfg |= ROTATOR_CONTROL_START;
+
+	writel(cfg, rot->regs + ROTATOR_CONTROL);
+}
+
+void rot_hwset_src_addr(struct rot_dev *rot, dma_addr_t addr, u32 comp)
+{
+	writel(addr, rot->regs + ROTATOR_SRC_IMG_ADDR(comp));
+}
+
+void rot_hwset_dst_addr(struct rot_dev *rot, dma_addr_t addr, u32 comp)
+{
+	writel(addr, rot->regs + ROTATOR_DST_IMG_ADDR(comp));
+}
+
+void rot_hwset_src_imgsize(struct rot_dev *rot, struct rot_frame *frame)
+{
+	unsigned long cfg;
+
+	cfg = ROTATOR_SRCIMG_YSIZE(frame->pix_mp.height) |
+		ROTATOR_SRCIMG_XSIZE(frame->pix_mp.width);
+
+	writel(cfg, rot->regs + ROTATOR_SRCIMG);
+
+	cfg = ROTATOR_SRCROT_YSIZE(frame->pix_mp.height) |
+		ROTATOR_SRCROT_XSIZE(frame->pix_mp.width);
+
+	writel(cfg, rot->regs + ROTATOR_SRCROT);
+}
+
+void rot_hwset_src_crop(struct rot_dev *rot, struct v4l2_rect *rect)
+{
+	unsigned long cfg;
+
+	cfg = ROTATOR_SRC_Y(rect->top) |
+		ROTATOR_SRC_X(rect->left);
+
+	writel(cfg, rot->regs + ROTATOR_SRC);
+
+	cfg = ROTATOR_SRCROT_YSIZE(rect->height) |
+		ROTATOR_SRCROT_XSIZE(rect->width);
+
+	writel(cfg, rot->regs + ROTATOR_SRCROT);
+}
+
+void rot_hwset_dst_imgsize(struct rot_dev *rot, struct rot_frame *frame)
+{
+	unsigned long cfg;
+
+	cfg = ROTATOR_DSTIMG_YSIZE(frame->pix_mp.height) |
+		ROTATOR_DSTIMG_XSIZE(frame->pix_mp.width);
+
+	writel(cfg, rot->regs + ROTATOR_DSTIMG);
+}
+
+void rot_hwset_dst_crop(struct rot_dev *rot, struct v4l2_rect *rect)
+{
+	unsigned long cfg;
+
+	cfg =  ROTATOR_DST_Y(rect->top) |
+		ROTATOR_DST_X(rect->left);
+
+	writel(cfg, rot->regs + ROTATOR_DST);
+}
+
+void rot_hwget_irq_src(struct rot_dev *rot, enum rot_irq_src *irq)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_STATUS);
+	cfg = ROTATOR_STATUS_IRQ(cfg);
+
+	if (cfg == 1)
+		*irq = ISR_PEND_DONE;
+	else if (cfg == 2)
+		*irq = ISR_PEND_ILLEGAL;
+}
+
+void rot_hwset_irq_clear(struct rot_dev *rot, enum rot_irq_src *irq)
+{
+	unsigned long cfg = readl(rot->regs + ROTATOR_STATUS);
+	cfg |= ROTATOR_STATUS_IRQ_PENDING((u32)irq);
+
+	writel(cfg, rot->regs + ROTATOR_STATUS);
+}
+
+void rot_hwget_status(struct rot_dev *rot, enum rot_status *state)
+{
+	unsigned long cfg;
+
+	cfg = readl(rot->regs + ROTATOR_STATUS);
+	cfg &= ROTATOR_STATUS_MASK;
+
+	switch (cfg) {
+	case 0:
+		*state = ROT_IDLE;
+		break;
+	case 1:
+		*state = ROT_RESERVED;
+		break;
+	case 2:
+		*state = ROT_RUNNING;
+		break;
+	case 3:
+		*state = ROT_RUNNING_REMAIN;
+		break;
+	};
+}
+
+void rot_dump_registers(struct rot_dev *rot)
+{
+	unsigned int tmp, i;
+
+	rot_dbg("dump rotator registers\n");
+	for (i = 0; i <= ROTATOR_DST; i += 0x4) {
+		tmp = readl(rot->regs + i);
+		rot_dbg("0x%08x: 0x%08x", i, tmp);
+	}
+}
diff --git a/drivers/media/video/exynos/rotator/rotator-regs.h b/drivers/media/video/exynos/rotator/rotator-regs.h
new file mode 100644
index 0000000..a603417
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/rotator-regs.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Register header file for Exynos Rotator driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Configuration */
+#define ROTATOR_CONFIG				0x00
+#define ROTATOR_CONFIG_IRQ_ILLEGAL		(1 << 9)
+#define ROTATOR_CONFIG_IRQ_DONE			(1 << 8)
+
+/* Image0 Control */
+#define ROTATOR_CONTROL				0x10
+#define ROTATOR_CONTROL_PATTERN_WRITE		(1 << 16)
+#define ROTATOR_CONTROL_FMT_YCBCR420_3P		(0 << 8)
+#define ROTATOR_CONTROL_FMT_YCBCR420_2P		(1 << 8)
+#define ROTATOR_CONTROL_FMT_YCBCR422		(3 << 8)
+#define ROTATOR_CONTROL_FMT_RGB565		(4 << 8)
+#define ROTATOR_CONTROL_FMT_RGB888		(6 << 8)
+#define ROTATOR_CONTROL_FMT_MASK		(7 << 8)
+#define ROTATOR_CONTROL_FLIP_V			(2 << 6)
+#define ROTATOR_CONTROL_FLIP_H			(3 << 6)
+#define ROTATOR_CONTROL_FLIP_MASK		(3 << 6)
+#define ROTATOR_CONTROL_ROT_90			(1 << 4)
+#define ROTATOR_CONTROL_ROT_180			(2 << 4)
+#define ROTATOR_CONTROL_ROT_270			(3 << 4)
+#define ROTATOR_CONTROL_ROT_MASK		(3 << 4)
+#define ROTATOR_CONTROL_START			(1 << 0)
+
+/* Status */
+#define ROTATOR_STATUS				0x20
+#define ROTATOR_STATUS_IRQ_PENDING(x)		(1 << (x))
+#define ROTATOR_STATUS_IRQ(x)			(((x) >> 8) & 0x3)
+#define ROTATOR_STATUS_MASK			(3 << 0)
+
+/* Sourc Image Base Address */
+#define ROTATOR_SRC_IMG_ADDR(n)			(0x30 + ((n) << 2))
+
+/* Source Image X,Y Size */
+#define ROTATOR_SRCIMG				0x3c
+#define ROTATOR_SRCIMG_YSIZE(x)			((x) << 16)
+#define ROTATOR_SRCIMG_XSIZE(x)			((x) << 0)
+
+/* Source Image X,Y Coordinates */
+#define ROTATOR_SRC				0x40
+#define ROTATOR_SRC_Y(x)			((x) << 16)
+#define ROTATOR_SRC_X(x)			((x) << 0)
+
+/* Source Image Rotation Size */
+#define ROTATOR_SRCROT				0x44
+#define ROTATOR_SRCROT_YSIZE(x)			((x) << 16)
+#define ROTATOR_SRCROT_XSIZE(x)			((x) << 0)
+
+/* Destination Image Base Address */
+#define ROTATOR_DST_IMG_ADDR(n)			(0x50 + ((n) << 2))
+
+/* Destination Image X,Y Size */
+#define ROTATOR_DSTIMG				0x5c
+#define ROTATOR_DSTIMG_YSIZE(x)			((x) << 16)
+#define ROTATOR_DSTIMG_XSIZE(x)			((x) << 0)
+
+/* Destination Image X,Y Coordinates */
+#define ROTATOR_DST				0x60
+#define ROTATOR_DST_Y(x)			((x) << 16)
+#define ROTATOR_DST_X(x)			((x) << 0)
diff --git a/drivers/media/video/exynos/rotator/rotator-vb2.c b/drivers/media/video/exynos/rotator/rotator-vb2.c
new file mode 100644
index 0000000..0b56efb
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/rotator-vb2.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Videobuf2 bridge driver file for EXYNOS Image Rotator driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include "rotator.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *rot_cma_init(struct rot_dev *rot)
+{
+	return vb2_cma_phys_init(rot->dev, NULL, 0, false);
+}
+
+int rot_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void rot_cma_suspend(void *alloc_ctx) {}
+void rot_cma_set_cacheable(void *alloc_ctx, bool cacheable) {}
+int rot_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no) { return 0; }
+
+const struct rot_vb2 rot_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= rot_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= rot_cma_resume,
+	.suspend	= rot_cma_suspend,
+	.cache_flush	= rot_cma_cache_flush,
+	.set_cacheable	= rot_cma_set_cacheable,
+};
+
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *rot_ion_init(struct rot_dev *rot)
+{
+	return vb2_ion_create_context(rot->dev, SZ_1M,
+		VB2ION_CTX_PHCONTIG | VB2ION_CTX_IOMMU | VB2ION_CTX_UNCACHED);
+}
+
+static unsigned long rot_vb2_plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dma_addr = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dma_addr) != 0);
+
+	return (unsigned long)dma_addr;
+}
+
+const struct rot_vb2 rot_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= rot_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= rot_vb2_plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+};
+#endif
diff --git a/drivers/media/video/exynos/rotator/rotator.h b/drivers/media/video/exynos/rotator/rotator.h
new file mode 100644
index 0000000..158b3e4
--- /dev/null
+++ b/drivers/media/video/exynos/rotator/rotator.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Header file for Exynos Rotator driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef ROTATOR__H_
+#define ROTATOR__H_
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+
+#include "rotator-regs.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+extern int log_level;
+
+#define rot_dbg(fmt, args...)						\
+	do {								\
+		if (log_level)						\
+			printk(KERN_DEBUG "[%s:%d] "			\
+			fmt, __func__, __LINE__, ##args);		\
+	} while (0)
+
+/* Time to wait for frame done interrupt */
+#define ROT_TIMEOUT		(2 * HZ)
+#define ROT_WDT_CNT		5
+#define MODULE_NAME		"exynos-rot"
+#define ROT_MAX_DEVS		1
+
+/* Address index */
+#define ROT_ADDR_RGB		0
+#define ROT_ADDR_Y		0
+#define ROT_ADDR_CB		1
+#define ROT_ADDR_CBCR		1
+#define ROT_ADDR_CR		2
+
+/* Rotator flip direction */
+#define ROT_NOFLIP	(1 << 0)
+#define ROT_VFLIP	(1 << 1)
+#define ROT_HFLIP	(1 << 2)
+
+/* Rotator hardware device state */
+#define DEV_RUN		(1 << 0)
+#define DEV_SUSPEND	(1 << 1)
+
+/* Rotator m2m context state */
+#define CTX_PARAMS	(1 << 0)
+#define CTX_STREAMING	(1 << 1)
+#define CTX_RUN		(1 << 2)
+#define CTX_ABORT	(1 << 3)
+#define CTX_SRC		(1 << 4)
+#define CTX_DST		(1 << 5)
+
+enum rot_irq_src {
+	ISR_PEND_DONE = 8,
+	ISR_PEND_ILLEGAL = 9,
+};
+
+enum rot_status {
+	ROT_IDLE,
+	ROT_RESERVED,
+	ROT_RUNNING,
+	ROT_RUNNING_REMAIN,
+};
+
+enum rot_clk_status {
+	ROT_CLK_ON,
+	ROT_CLK_OFF,
+};
+/*
+ * struct exynos_rot_size_limit - Rotator variant size  information
+ *
+ * @min_x: minimum pixel x size
+ * @min_y: minimum pixel y size
+ * @max_x: maximum pixel x size
+ * @max_y: maximum pixel y size
+ */
+struct exynos_rot_size_limit {
+	u32 min_x;
+	u32 min_y;
+	u32 max_x;
+	u32 max_y;
+	u32 align;
+};
+
+struct exynos_rot_variant {
+	struct exynos_rot_size_limit limit_rgb565;
+	struct exynos_rot_size_limit limit_rgb888;
+	struct exynos_rot_size_limit limit_yuv422;
+	struct exynos_rot_size_limit limit_yuv420_2p;
+	struct exynos_rot_size_limit limit_yuv420_3p;
+};
+
+/*
+ * struct exynos_rot_driverdata - per device type driver data for init time.
+ *
+ * @variant: the variant information for this driver.
+ * @nr_dev: number of devices available in SoC
+ */
+struct exynos_rot_driverdata {
+	struct exynos_rot_variant	*variant[ROT_MAX_DEVS];
+	int				nr_dev;
+};
+
+/**
+ * struct rot_fmt - the driver's internal color format data
+ * @name: format description
+ * @pixelformat: the fourcc code for this format, 0 if not applicable
+ * @num_planes: number of physically non-contiguous data planes
+ * @num_comp: number of color components(ex. RGB, Y, Cb, Cr)
+ * @bitperpixel: bits per pixel
+ */
+struct rot_fmt {
+	char	*name;
+	u32	pixelformat;
+	u16	num_planes;
+	u16	num_comp;
+	u32	bitperpixel[VIDEO_MAX_PLANES];
+};
+
+struct rot_addr {
+	dma_addr_t	y;
+	dma_addr_t	cb;
+	dma_addr_t	cr;
+};
+
+/*
+ * struct rot_frame - source/target frame properties
+ * @fmt:	buffer format(like virtual screen)
+ * @crop:	image size / position
+ * @addr:	buffer start address(access using ROT_ADDR_XXX)
+ * @bytesused:	image size in bytes (w x h x bpp)
+ */
+struct rot_frame {
+	struct rot_fmt			*rot_fmt;
+	struct v4l2_pix_format_mplane	pix_mp;
+	struct v4l2_rect		crop;
+	struct rot_addr			addr;
+	unsigned long			bytesused[VIDEO_MAX_PLANES];
+};
+
+/*
+ * struct rot_m2m_device - v4l2 memory-to-memory device data
+ * @v4l2_dev: v4l2 device
+ * @vfd: the video device node
+ * @m2m_dev: v4l2 memory-to-memory device data
+ * @in_use: the open count
+ */
+struct rot_m2m_device {
+	struct v4l2_device	v4l2_dev;
+	struct video_device	*vfd;
+	struct v4l2_m2m_dev	*m2m_dev;
+	atomic_t		in_use;
+};
+
+struct rot_wdt {
+	struct timer_list	timer;
+	atomic_t		cnt;
+};
+
+struct rot_ctx;
+struct rot_vb2;
+
+/*
+ * struct rot_dev - the abstraction for Rotator device
+ * @dev:	pointer to the Rotator device
+ * @pdata:	pointer to the device platform data
+ * @variant:	the IP variant information
+ * @m2m:	memory-to-memory V4L2 device information
+ * @id:		Rotator device index (0..ROT_MAX_DEVS)
+ * @clock:	clock required for Rotator operation
+ * @regs:	the mapped hardware registers
+ * @regs_res:	the resource claimed for IO registers
+ * @wait:	interrupt handler waitqueue
+ * @ws:		work struct
+ * @state:	device state flags
+ * @alloc_ctx:	videobuf2 memory allocator context
+ * @rot_vb2:	videobuf2 memory allocator callbacks
+ * @slock:	the spinlock protecting this data structure
+ * @lock:	the mutex protecting this data structure
+ * @wdt:	watchdog timer information
+ * @clk_cnt:	rotator clock on/off count
+ */
+struct rot_dev {
+	struct device			*dev;
+	struct exynos_platform_rot	*pdata;
+	struct exynos_rot_variant	*variant;
+	struct rot_m2m_device		m2m;
+	int				id;
+	struct clk			*clock;
+	void __iomem			*regs;
+	struct resource			*regs_res;
+	wait_queue_head_t		wait;
+	unsigned long			state;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	const struct rot_vb2		*vb2;
+	spinlock_t			slock;
+	struct mutex			lock;
+	struct rot_wdt			wdt;
+	atomic_t			clk_cnt;
+};
+
+/*
+ * rot_ctx - the abstration for Rotator open context
+ * @rot_dev:		the Rotator device this context applies to
+ * @m2m_ctx:		memory-to-memory device context
+ * @frame:		source frame properties
+ * @ctrl_handler:	v4l2 controls handler
+ * @fh:			v4l2 file handle
+ * @rotation:		image clockwise rotation in degrees
+ * @flip:		image flip mode
+ * @state:		context state flags
+ * @slock:		spinlock protecting this data structure
+ */
+struct rot_ctx {
+	struct rot_dev			*rot_dev;
+	struct v4l2_m2m_ctx		*m2m_ctx;
+	struct rot_frame		s_frame;
+	struct rot_frame		d_frame;
+	struct v4l2_ctrl_handler	ctrl_handler;
+	struct v4l2_fh			fh;
+	int				rotation;
+	u32				flip;
+	unsigned long			flags;
+	spinlock_t			slock;
+	bool				cacheable;
+};
+
+struct rot_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct rot_dev *rot);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+};
+
+static inline struct rot_frame *ctx_get_frame(struct rot_ctx *ctx,
+						enum v4l2_buf_type type)
+{
+	struct rot_frame *frame;
+
+	if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
+		if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+			frame = &ctx->s_frame;
+		else
+			frame = &ctx->d_frame;
+	} else {
+		dev_err(ctx->rot_dev->dev,
+				"Wrong V4L2 buffer type %d\n", type);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return frame;
+}
+
+#define fh_to_rot_ctx(__fh)	container_of(__fh, struct rot_ctx, fh)
+
+void rot_hwset_irq_frame_done(struct rot_dev *rot, u32 enable);
+void rot_hwset_irq_illegal_config(struct rot_dev *rot, u32 enable);
+int rot_hwset_image_format(struct rot_dev *rot, u32 pixelformat);
+void rot_hwset_flip(struct rot_dev *rot, u32 direction);
+void rot_hwset_rotation(struct rot_dev *rot, int degree);
+void rot_hwset_start(struct rot_dev *rot);
+void rot_hwset_src_addr(struct rot_dev *rot, dma_addr_t addr, u32 comp);
+void rot_hwset_dst_addr(struct rot_dev *rot, dma_addr_t addr, u32 comp);
+void rot_hwset_src_imgsize(struct rot_dev *rot, struct rot_frame *frame);
+void rot_hwset_src_crop(struct rot_dev *rot, struct v4l2_rect *rect);
+void rot_hwset_dst_imgsize(struct rot_dev *rot, struct rot_frame *frame);
+void rot_hwset_dst_crop(struct rot_dev *rot, struct v4l2_rect *rect);
+void rot_hwget_irq_src(struct rot_dev *rot, enum rot_irq_src *irq);
+void rot_hwset_irq_clear(struct rot_dev *rot, enum rot_irq_src *irq);
+void rot_hwget_status(struct rot_dev *rot, enum rot_status *state);
+void rot_dump_registers(struct rot_dev *rot);
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct rot_vb2 rot_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct rot_vb2 rot_vb2_ion;
+#endif
+
+#endif /* ROTATOR__H_ */
diff --git a/drivers/media/video/exynos/tv/Kconfig b/drivers/media/video/exynos/tv/Kconfig
new file mode 100644
index 0000000..becd639
--- /dev/null
+++ b/drivers/media/video/exynos/tv/Kconfig
@@ -0,0 +1,119 @@
+# drivers/media/video/s5p-tv/Kconfig
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+# Tomasz Stanislawski <t.stanislaws@samsung.com>
+#
+# Licensed under GPL
+
+config VIDEO_EXYNOS_TV
+	bool "Samsung TV driver for S5P platform (experimental)"
+	depends on PLAT_S5P
+	depends on EXPERIMENTAL
+	select MEDIA_EXYNOS
+	select VIDEO_EXYNOS_HDMI
+	select VIDEO_EXYNOS_MIXER
+	default n
+	---help---
+	  Say Y here to enable selecting the TV output devices for
+	  Samsung S5P platform.
+
+if VIDEO_EXYNOS_TV
+
+config VIDEO_EXYNOS_HDMI
+	tristate "Samsung HDMI Driver"
+	depends on VIDEO_V4L2
+	depends on VIDEO_EXYNOS_TV
+	select VIDEO_EXYNOS_HDMIPHY
+	help
+	  Say Y here if you want support for the HDMI output
+	  interface in S5P Samsung SoC. The driver can be compiled
+	  as module. It is an auxiliary driver, that exposes a V4L2
+	  subdev for use by other drivers. This driver requires
+	  hdmiphy driver to work correctly.
+
+config VIDEO_EXYNOS_HDMI_AUDIO_I2S
+	bool "Enable HDMI audio using I2S path"
+	depends on VIDEO_EXYNOS_HDMI
+	depends on SND_SAMSUNG_I2S
+	default y
+	help
+	  Enables HDMI audio through I2S path.
+
+config VIDEO_EXYNOS_HDMI_AUDIO_SPDIF
+	bool "Enable HDMI audio using SPDIF path"
+	depends on VIDEO_EXYNOS_HDMI
+	depends on SND_SAMSUNG_SPDIF
+	default n
+	help
+	  Enables HDMI audio through SPDIF path.
+
+config VIDEO_EXYNOS_HDCP
+	bool "Enable HDCP"
+	depends on VIDEO_EXYNOS_HDMI
+	depends on I2C
+	default n
+	help
+	  Enables HDCP feature. However if you want to use HDCP,
+	  device private key must be e-fused in SoC.
+
+config VIDEO_EXYNOS_HDMI_DEBUG
+	bool "Enable debug for HDMI Driver"
+	depends on VIDEO_EXYNOS_HDMI
+	default n
+	help
+	  Enables debugging for HDMI driver.
+
+config VIDEO_EXYNOS_HDMIPHY
+	tristate "Samsung HDMIPHY Driver"
+	depends on VIDEO_DEV && VIDEO_V4L2 && I2C
+	depends on VIDEO_EXYNOS_TV
+	help
+	  Say Y here if you want support for the physical HDMI
+	  interface in S5P Samsung SoC. The driver can be compiled
+	  as module. It is an I2C driver, that exposes a V4L2
+	  subdev for use by other drivers.
+
+config VIDEO_EXYNOS_SDO
+	tristate "Samsung Analog TV Driver"
+	depends on VIDEO_DEV && VIDEO_V4L2
+	depends on VIDEO_EXYNOS_TV
+	depends on CPU_EXYNOS4210
+	help
+	  Say Y here if you want support for the analog TV output
+	  interface in S5P Samsung SoC. The driver can be compiled
+	  as module. It is an auxiliary driver, that exposes a V4L2
+	  subdev for use by other drivers. This driver requires
+	  hdmiphy driver to work correctly.
+
+config VIDEO_EXYNOS_MIXER
+	tristate "Samsung Mixer and Video Processor Driver"
+	depends on VIDEO_DEV && VIDEO_V4L2
+	depends on VIDEO_EXYNOS_TV
+	select VIDEOBUF2_DMA_CONTIG
+	help
+	  Say Y here if you want support for the Mixer in Samsung S5P SoCs.
+	  This device produce image data to one of output interfaces.
+
+config VIDEO_EXYNOS_HDMI_CEC
+	tristate "Samsung HDMI CEC Driver"
+	depends on VIDEO_DEV && VIDEO_V4L2 && I2C
+	depends on VIDEO_EXYNOS_TV
+	help
+	  Say Y here if you want support for the HDMI CEC
+	  interface in S5P Samsung SoC. The driver can be compiled
+	  as module.
+
+config VIDEO_SAMSUNG_MEMSIZE_TV
+	int "Memory size in kbytes for TV"
+	depends on VIDEO_EXYNOS_MIXER && VIDEOBUF2_CMA_PHYS
+	default "16200"
+
+config VIDEO_EXYNOS_MIXER_DEBUG
+	bool "Enable debug for Mixer Driver"
+	depends on VIDEO_EXYNOS_MIXER
+	default n
+	help
+	  Enables debugging for Mixer driver.
+
+endif # VIDEO_EXYNOS_TV
diff --git a/drivers/media/video/exynos/tv/Makefile b/drivers/media/video/exynos/tv/Makefile
new file mode 100644
index 0000000..29cef3f
--- /dev/null
+++ b/drivers/media/video/exynos/tv/Makefile
@@ -0,0 +1,31 @@
+# drivers/media/video/samsung/tvout/Makefile
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+# Tomasz Stanislawski <t.stanislaws@samsung.com>
+#
+# Licensed under GPL
+obj-$(CONFIG_VIDEO_EXYNOS_HDMIPHY) += s5p-hdmiphy.o
+s5p-hdmiphy-y += hdmiphy_drv.o
+obj-$(CONFIG_VIDEO_EXYNOS_HDMI) += s5p-hdmi.o
+s5p-hdmi-y += hdcp_drv.o hdmi_drv.o
+obj-$(CONFIG_VIDEO_EXYNOS_SDO) += s5p-sdo.o
+s5p-sdo-y += sdo_drv.o
+obj-$(CONFIG_VIDEO_EXYNOS_MIXER) += s5p-mixer.o
+s5p-mixer-y += mixer_vb2.o mixer_drv.o mixer_video.o mixer_reg.o mixer_grp_layer.o
+obj-$(CONFIG_VIDEO_EXYNOS_HDMI_CEC) += s5p-hdmi_cec.o
+s5p-hdmi_cec-y += hdmi_cec.o hdmi_cec_ctrl.o
+
+ifeq ($(CONFIG_ARCH_EXYNOS4), y)
+	s5p-mixer-y += mixer_vp_layer.o
+else
+	s5p-mixer-y += mixer_video_layer.o
+endif
+
+ifeq ($(CONFIG_VIDEO_EXYNOS_HDMI),y)
+	ifeq ($(CONFIG_CPU_EXYNOS4210), y)
+		s5p-hdmi-y += hdmi_reg_4210.o hdmiphy_conf_4210.o
+	else
+		s5p-hdmi-y += hdmi_reg_5250.o hdmiphy_conf_5250.o
+	endif
+endif
diff --git a/drivers/media/video/exynos/tv/cec.h b/drivers/media/video/exynos/tv/cec.h
new file mode 100644
index 0000000..f33a619
--- /dev/null
+++ b/drivers/media/video/exynos/tv/cec.h
@@ -0,0 +1,84 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/hw_if.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Header file for interface of Samsung TVOUT-related hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _SAMSUNG_TVOUT_CEC_H_
+#define _SAMSUNG_TVOUT_CEC_H_ __FILE__
+
+/*****************************************************************************
+ * This file includes declarations for external functions of
+ * Samsung TVOUT-related hardware. So only external functions
+ * to be used by higher layer must exist in this file.
+ *
+ * Higher layer must use only the declarations included in this file.
+ ****************************************************************************/
+
+#define to_tvout_plat(d) (to_platform_device(d)->dev.platform_data)
+
+#ifndef tvout_dbg
+#ifdef CONFIG_TV_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "[%s] %s(): " fmt,		\
+			DRV_NAME, __func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+#endif
+
+enum s5p_tvout_endian {
+	TVOUT_LITTLE_ENDIAN = 0,
+	TVOUT_BIG_ENDIAN = 1
+};
+
+enum cec_state {
+	STATE_RX,
+	STATE_TX,
+	STATE_DONE,
+	STATE_ERROR
+};
+
+struct cec_rx_struct {
+	spinlock_t lock;
+	wait_queue_head_t waitq;
+	atomic_t state;
+	u8 *buffer;
+	unsigned int size;
+};
+
+struct cec_tx_struct {
+	wait_queue_head_t waitq;
+	atomic_t state;
+};
+
+extern struct cec_rx_struct cec_rx_struct;
+extern struct cec_tx_struct cec_tx_struct;
+
+void s5p_cec_set_divider(void);
+void s5p_cec_enable_rx(void);
+void s5p_cec_mask_rx_interrupts(void);
+void s5p_cec_unmask_rx_interrupts(void);
+void s5p_cec_mask_tx_interrupts(void);
+void s5p_cec_unmask_tx_interrupts(void);
+void s5p_cec_reset(void);
+void s5p_cec_tx_reset(void);
+void s5p_cec_rx_reset(void);
+void s5p_cec_threshold(void);
+void s5p_cec_set_tx_state(enum cec_state state);
+void s5p_cec_set_rx_state(enum cec_state state);
+void s5p_cec_copy_packet(char *data, size_t count);
+void s5p_cec_set_addr(u32 addr);
+u32 s5p_cec_get_status(void);
+void s5p_clr_pending_tx(void);
+void s5p_clr_pending_rx(void);
+void s5p_cec_get_rx_buf(u32 size, u8 *buffer);
+int __init s5p_cec_mem_probe(struct platform_device *pdev);
+
+#endif /* _SAMSUNG_TVOUT_CEC_H_ */
diff --git a/drivers/media/video/exynos/tv/hdcp_drv.c b/drivers/media/video/exynos/tv/hdcp_drv.c
new file mode 100644
index 0000000..d223fdd
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdcp_drv.c
@@ -0,0 +1,987 @@
+/* linux/drivers/media/video/exynos/tv/hdcp_drv.c
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * HDCP function for Samsung TV driver
+ *
+ * This program is free software. you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/workqueue.h>
+
+#include "hdmi.h"
+#include "regs-hdmi-5250.h"
+
+#define AN_SIZE			8
+#define AKSV_SIZE		5
+#define BKSV_SIZE		5
+#define MAX_KEY_SIZE		16
+
+#define BKSV_RETRY_CNT		14
+#define BKSV_DELAY		100
+
+#define DDC_RETRY_CNT		400000
+#define DDC_DELAY		25
+
+#define KEY_LOAD_RETRY_CNT	1000
+#define ENCRYPT_CHECK_CNT	10
+
+#define KSV_FIFO_RETRY_CNT	50
+#define KSV_FIFO_CHK_DELAY	100 /* ms */
+#define KSV_LIST_RETRY_CNT	10000
+
+#define BCAPS_SIZE		1
+#define BSTATUS_SIZE		2
+#define SHA_1_HASH_SIZE		20
+#define HDCP_MAX_DEVS		128
+#define HDCP_KSV_SIZE		5
+
+/* offset of HDCP port */
+#define HDCP_BKSV		0x00
+#define HDCP_RI			0x08
+#define HDCP_AKSV		0x10
+#define HDCP_AN			0x18
+#define HDCP_SHA1		0x20
+#define HDCP_BCAPS		0x40
+#define HDCP_BSTATUS		0x41
+#define HDCP_KSVFIFO		0x43
+
+#define KSV_FIFO_READY			(0x1 << 5)
+
+#define MAX_CASCADE_EXCEEDED_ERROR	(-2)
+#define MAX_DEVS_EXCEEDED_ERROR		(-3)
+#define REPEATER_ILLEGAL_DEVICE_ERROR	(-4)
+#define REPEATER_TIMEOUT_ERROR		(-5)
+
+#define MAX_CASCADE_EXCEEDED		(0x1 << 3)
+#define MAX_DEVS_EXCEEDED		(0x1 << 7)
+
+struct i2c_client *hdcp_client;
+
+int hdcp_i2c_read(struct hdmi_device *hdev, u8 offset, int bytes, u8 *buf)
+{
+	struct device *dev = hdev->dev;
+	struct i2c_client *i2c = hdcp_client;
+	int ret, cnt = 0;
+
+	struct i2c_msg msg[] = {
+		[0] = {
+			.addr = i2c->addr,
+			.flags = 0,
+			.len = 1,
+			.buf = &offset
+		},
+		[1] = {
+			.addr = i2c->addr,
+			.flags = I2C_M_RD,
+			.len = bytes,
+			.buf = buf
+		}
+	};
+
+	do {
+		if (!is_hdmi_streaming(hdev))
+			goto ddc_read_err;
+
+		ret = i2c_transfer(i2c->adapter, msg, 2);
+
+		if (ret < 0 || ret != 2)
+			dev_dbg(dev, "%s: can't read data, retry %d\n",
+					__func__, cnt);
+		else
+			break;
+
+		if (hdev->hdcp_info.auth_status == FIRST_AUTHENTICATION_DONE
+			|| hdev->hdcp_info.auth_status == SECOND_AUTHENTICATION_DONE)
+			goto ddc_read_err;
+
+		msleep(DDC_DELAY);
+		cnt++;
+	} while (cnt < DDC_RETRY_CNT);
+
+	if (cnt == DDC_RETRY_CNT)
+		goto ddc_read_err;
+
+	dev_dbg(dev, "%s: read data ok\n", __func__);
+
+	return 0;
+
+ddc_read_err:
+	dev_err(dev, "%s: can't read data, timeout\n", __func__);
+	return -ETIME;
+}
+
+int hdcp_i2c_write(struct hdmi_device *hdev, u8 offset, int bytes, u8 *buf)
+{
+	struct device *dev = hdev->dev;
+	struct i2c_client *i2c = hdcp_client;
+	u8 msg[bytes + 1];
+	int ret, cnt = 0;
+
+	msg[0] = offset;
+	memcpy(&msg[1], buf, bytes);
+
+	do {
+		if (!is_hdmi_streaming(hdev))
+			goto ddc_write_err;
+
+		ret = i2c_master_send(i2c, msg, bytes + 1);
+
+		if (ret < 0 || ret < bytes + 1)
+			dev_dbg(dev, "%s: can't write data, retry %d\n",
+					__func__, cnt);
+		else
+			break;
+
+		msleep(DDC_DELAY);
+		cnt++;
+	} while (cnt < DDC_RETRY_CNT);
+
+	if (cnt == DDC_RETRY_CNT)
+		goto ddc_write_err;
+
+	dev_dbg(dev, "%s: write data ok\n", __func__);
+	return 0;
+
+ddc_write_err:
+	dev_err(dev, "%s: can't write data, timeout\n", __func__);
+	return -ETIME;
+}
+
+static int __devinit hdcp_probe(struct i2c_client *client,
+			const struct i2c_device_id *dev_id)
+{
+	int ret = 0;
+
+	hdcp_client = client;
+
+	dev_info(&client->adapter->dev, "attached exynos hdcp "
+		"into i2c adapter successfully\n");
+
+	return ret;
+}
+
+static int hdcp_remove(struct i2c_client *client)
+{
+	dev_info(&client->adapter->dev, "detached exynos hdcp "
+		"from i2c adapter successfully\n");
+
+	return 0;
+}
+
+static int hdcp_suspend(struct i2c_client *cl, pm_message_t mesg)
+{
+	return 0;
+};
+
+static int hdcp_resume(struct i2c_client *cl)
+{
+	return 0;
+};
+
+static struct i2c_device_id hdcp_idtable[] = {
+	{"exynos_hdcp", 0},
+};
+MODULE_DEVICE_TABLE(i2c, hdcp_idtable);
+
+static struct i2c_driver hdcp_driver = {
+	.driver = {
+		.name = "exynos_hdcp",
+		.owner = THIS_MODULE,
+	},
+	.id_table	= hdcp_idtable,
+	.probe		= hdcp_probe,
+	.remove		= __devexit_p(hdcp_remove),
+	.suspend	= hdcp_suspend,
+	.resume		= hdcp_resume,
+};
+
+static int __init hdcp_init(void)
+{
+	return i2c_add_driver(&hdcp_driver);
+}
+
+static void __exit hdcp_exit(void)
+{
+	i2c_del_driver(&hdcp_driver);
+}
+
+module_init(hdcp_init);
+module_exit(hdcp_exit);
+
+/* internal functions of HDCP */
+static void hdcp_encryption(struct hdmi_device *hdev, bool on)
+{
+	if (on)
+		hdmi_write_mask(hdev, HDMI_ENC_EN, ~0, HDMI_HDCP_ENC_ENABLE);
+	else
+		hdmi_write_mask(hdev, HDMI_ENC_EN, 0, HDMI_HDCP_ENC_ENABLE);
+
+	hdmi_reg_mute(hdev, !on);
+}
+
+static int hdcp_write_key(struct hdmi_device *hdev, int size, int reg, int offset)
+{
+	struct device *dev = hdev->dev;
+	u8 buf[MAX_KEY_SIZE];
+	int cnt, zero = 0;
+	int i;
+
+	memset(buf, 0, sizeof(buf));
+	hdmi_read_bytes(hdev, reg, buf, size);
+
+	for (cnt = 0; cnt < size; cnt++)
+		if (buf[cnt] == 0)
+			zero++;
+
+	if (zero == size) {
+		dev_dbg(dev, "%s: %s is null\n", __func__,
+				offset == HDCP_AN ? "An" : "Aksv");
+		goto write_key_err;
+	}
+
+	if (hdcp_i2c_write(hdev, offset, size, buf) < 0)
+		goto write_key_err;
+
+	for (i = 1; i < size + 1; i++)
+		dev_dbg(dev, "%s: %s[%d] : 0x%02x\n", __func__,
+				offset == HDCP_AN ? "An" : "Aksv", i, buf[i]);
+
+	return 0;
+
+write_key_err:
+	dev_dbg(dev, "%s: write %s is failed\n", __func__,
+			offset == HDCP_AN ? "An" : "Aksv");
+	return -1;
+}
+
+static int hdcp_read_bcaps(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 bcaps = 0;
+
+	if (hdcp_i2c_read(hdev, HDCP_BCAPS, BCAPS_SIZE, &bcaps) < 0)
+		goto bcaps_read_err;
+
+	if (!is_hdmi_streaming(hdev))
+		goto bcaps_read_err;
+
+	hdmi_writeb(hdev, HDMI_HDCP_BCAPS, bcaps);
+
+	if (bcaps & HDMI_HDCP_BCAPS_REPEATER)
+		hdev->hdcp_info.is_repeater = 1;
+	else
+		hdev->hdcp_info.is_repeater = 0;
+
+	dev_dbg(dev, "%s: device is %s\n", __func__,
+			hdev->hdcp_info.is_repeater ? "REPEAT" : "SINK");
+	dev_dbg(dev, "%s: [i2c] bcaps : 0x%02x\n", __func__, bcaps);
+
+	return 0;
+
+bcaps_read_err:
+	dev_err(dev, "can't read bcaps : timeout\n");
+	return -ETIME;
+}
+
+static int hdcp_read_bksv(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 bksv[BKSV_SIZE];
+	int i, j;
+	u32 one = 0, zero = 0, result = 0;
+	u32 cnt = 0;
+
+	memset(bksv, 0, sizeof(bksv));
+
+	do {
+		if (hdcp_i2c_read(hdev, HDCP_BKSV, BKSV_SIZE, bksv) < 0)
+			goto bksv_read_err;
+
+		for (i = 0; i < BKSV_SIZE; i++)
+			dev_dbg(dev, "%s: i2c read : bksv[%d]: 0x%x\n",
+					__func__, i, bksv[i]);
+
+		for (i = 0; i < BKSV_SIZE; i++) {
+
+			for (j = 0; j < 8; j++) {
+				result = bksv[i] & (0x1 << j);
+
+				if (result == 0)
+					zero++;
+				else
+					one++;
+			}
+
+		}
+
+		if (!is_hdmi_streaming(hdev))
+			goto bksv_read_err;
+
+		if ((zero == 20) && (one == 20)) {
+			hdmi_write_bytes(hdev, HDMI_HDCP_BKSV_(0), bksv, BKSV_SIZE);
+			break;
+		}
+		dev_dbg(dev, "%s: invalid bksv, retry : %d\n", __func__, cnt);
+
+		msleep(BKSV_DELAY);
+		cnt++;
+	} while (cnt < BKSV_RETRY_CNT);
+
+	if (cnt == BKSV_RETRY_CNT)
+		goto bksv_read_err;
+
+	dev_dbg(dev, "%s: bksv read OK, retry : %d\n", __func__, cnt);
+	return 0;
+
+bksv_read_err:
+	dev_err(dev, "%s: can't read bksv : timeout\n", __func__);
+	return -ETIME;
+}
+
+static int hdcp_read_ri(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 ri[2] = {0, 0};
+	u8 rj[2] = {0, 0};
+
+
+	ri[0] = hdmi_readb(hdev, HDMI_HDCP_RI_0);
+	ri[1] = hdmi_readb(hdev, HDMI_HDCP_RI_1);
+
+	if (hdcp_i2c_read(hdev, HDCP_RI, 2, rj) < 0)
+		goto compare_err;
+
+	dev_dbg(dev, "%s: Rx -> rj[0]: 0x%02x, rj[1]: 0x%02x\n", __func__,
+			rj[0], rj[1]);
+	dev_dbg(dev, "%s: Tx -> ri[0]: 0x%02x, ri[1]: 0x%02x\n", __func__,
+			ri[0], ri[1]);
+
+	if ((ri[0] == rj[0]) && (ri[1] == rj[1]) && (ri[0] | ri[1]))
+		hdmi_writeb(hdev, HDMI_HDCP_CHECK_RESULT,
+				HDMI_HDCP_RI_MATCH_RESULT_Y);
+	else {
+		hdmi_writeb(hdev, HDMI_HDCP_CHECK_RESULT,
+				HDMI_HDCP_RI_MATCH_RESULT_N);
+		goto compare_err;
+	}
+
+	memset(ri, 0, sizeof(ri));
+	memset(rj, 0, sizeof(rj));
+
+	dev_dbg(dev, "%s: ri and ri' are matched\n", __func__);
+
+	return 0;
+
+compare_err:
+	hdev->hdcp_info.event = HDCP_EVENT_STOP;
+	hdev->hdcp_info.auth_status = NOT_AUTHENTICATED;
+	dev_err(dev, "%s: ri and ri' are mismatched\n", __func__);
+	msleep(10);
+	return -1;
+}
+
+static void hdcp_sw_reset(struct hdmi_device *hdev)
+{
+	u8 val;
+
+	val = hdmi_get_int_mask(hdev);
+
+	hdmi_set_int_mask(hdev, HDMI_INTC_EN_HPD_PLUG, 0);
+	hdmi_set_int_mask(hdev, HDMI_INTC_EN_HPD_UNPLUG, 0);
+
+	hdmi_sw_hpd_enable(hdev, 1);
+	hdmi_sw_hpd_plug(hdev, 0);
+	hdmi_sw_hpd_plug(hdev, 1);
+	hdmi_sw_hpd_enable(hdev, 0);
+
+	if (val & HDMI_INTC_EN_HPD_PLUG)
+		hdmi_set_int_mask(hdev, HDMI_INTC_EN_HPD_PLUG, 1);
+	if (val & HDMI_INTC_EN_HPD_UNPLUG)
+		hdmi_set_int_mask(hdev, HDMI_INTC_EN_HPD_UNPLUG, 1);
+}
+
+static int hdcp_reset_auth(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 val;
+	unsigned long spin_flags;
+
+	if (!is_hdmi_streaming(hdev))
+		return -ENODEV;
+
+	spin_lock_irqsave(&hdev->hdcp_info.reset_lock, spin_flags);
+
+	hdev->hdcp_info.event		= HDCP_EVENT_STOP;
+	hdev->hdcp_info.auth_status	= NOT_AUTHENTICATED;
+
+	hdmi_write(hdev, HDMI_HDCP_CTRL1, 0x0);
+	hdmi_write(hdev, HDMI_HDCP_CTRL2, 0x0);
+	hdmi_reg_mute(hdev, 1);
+
+	hdcp_encryption(hdev, 0);
+
+	dev_dbg(dev, "%s: reset authentication\n", __func__);
+
+	val = HDMI_UPDATE_RI_INT_EN | HDMI_WRITE_INT_EN |
+		HDMI_WATCHDOG_INT_EN | HDMI_WTFORACTIVERX_INT_EN;
+	hdmi_write_mask(hdev, HDMI_STATUS_EN, 0, val);
+
+	hdmi_writeb(hdev, HDMI_HDCP_CHECK_RESULT, HDMI_HDCP_CLR_ALL_RESULTS);
+
+	/* need some delay (at least 1 frame) */
+	mdelay(16);
+
+	hdcp_sw_reset(hdev);
+
+	val = HDMI_UPDATE_RI_INT_EN | HDMI_WRITE_INT_EN |
+		HDMI_WATCHDOG_INT_EN | HDMI_WTFORACTIVERX_INT_EN;
+	hdmi_write_mask(hdev, HDMI_STATUS_EN, ~0, val);
+	hdmi_write_mask(hdev, HDMI_HDCP_CTRL1, ~0, HDMI_HDCP_CP_DESIRED_EN);
+	spin_unlock_irqrestore(&hdev->hdcp_info.reset_lock, spin_flags);
+
+	return 0;
+}
+
+static int hdcp_loadkey(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 val;
+	int cnt = 0;
+
+	hdmi_write_mask(hdev, HDMI_EFUSE_CTRL, ~0, HDMI_EFUSE_CTRL_HDCP_KEY_READ);
+
+	do {
+		val = hdmi_readb(hdev, HDMI_EFUSE_STATUS);
+		if (val & HDMI_EFUSE_ECC_DONE)
+			break;
+		cnt++;
+		mdelay(1);
+	} while (cnt < KEY_LOAD_RETRY_CNT);
+
+	if (cnt == KEY_LOAD_RETRY_CNT)
+		goto key_load_err;
+
+	val = hdmi_readb(hdev, HDMI_EFUSE_STATUS);
+
+	if (val & HDMI_EFUSE_ECC_FAIL)
+		goto key_load_err;
+
+	dev_dbg(dev, "%s: load key is ok\n", __func__);
+	return 0;
+
+key_load_err:
+	dev_err(dev, "%s: can't load key\n", __func__);
+	return -1;
+}
+
+static int hdmi_start_encryption(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 val;
+	u32 cnt = 0;
+
+	do {
+		val = hdmi_readb(hdev, HDMI_STATUS);
+
+		if (val & HDMI_AUTHEN_ACK_AUTH) {
+			hdcp_encryption(hdev, 1);
+			break;
+		}
+
+		mdelay(1);
+
+		cnt++;
+	} while (cnt < ENCRYPT_CHECK_CNT);
+
+	if (cnt == ENCRYPT_CHECK_CNT)
+		goto encrypt_err;
+
+
+	dev_dbg(dev, "%s: encryption is start\n", __func__);
+	return 0;
+
+encrypt_err:
+	hdcp_encryption(hdev, 0);
+	dev_err(dev, "%s: encryption is failed\n", __func__);
+	return -1;
+}
+
+static int hdmi_check_repeater(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	int val, i;
+	int cnt = 0, cnt2 = 0;
+
+	u8 bcaps = 0;
+	u8 status[BSTATUS_SIZE];
+	u8 rx_v[SHA_1_HASH_SIZE];
+	u8 ksv_list[HDCP_MAX_DEVS * HDCP_KSV_SIZE];
+
+	u32 dev_cnt;
+
+	memset(status, 0, sizeof(status));
+	memset(rx_v, 0, sizeof(rx_v));
+	memset(ksv_list, 0, sizeof(ksv_list));
+
+	do {
+		if (hdcp_read_bcaps(hdev) < 0)
+			goto check_repeater_err;
+
+		bcaps = hdmi_readb(hdev, HDMI_HDCP_BCAPS);
+
+		if (bcaps & KSV_FIFO_READY) {
+			dev_dbg(dev, "%s: repeater : ksv fifo not ready\n",
+					__func__);
+			dev_dbg(dev, "%s: retries = %d\n", __func__, cnt);
+			break;
+		}
+
+		msleep(KSV_FIFO_CHK_DELAY);
+
+		cnt++;
+	} while (cnt < KSV_FIFO_RETRY_CNT);
+
+	if (cnt == KSV_FIFO_RETRY_CNT)
+		return REPEATER_TIMEOUT_ERROR;
+
+	dev_dbg(dev, "%s: repeater : ksv fifo ready\n", __func__);
+
+	if (hdcp_i2c_read(hdev, HDCP_BSTATUS, BSTATUS_SIZE, status) < 0)
+		goto check_repeater_err;
+
+	if (status[1] & MAX_CASCADE_EXCEEDED)
+		return MAX_CASCADE_EXCEEDED_ERROR;
+	else if (status[0] & MAX_DEVS_EXCEEDED)
+		return MAX_DEVS_EXCEEDED_ERROR;
+
+	hdmi_writeb(hdev, HDMI_HDCP_BSTATUS_0, status[0]);
+	hdmi_writeb(hdev, HDMI_HDCP_BSTATUS_1, status[1]);
+
+	dev_dbg(dev, "%s: status[0] :0x%02x\n", __func__, status[0]);
+	dev_dbg(dev, "%s: status[1] :0x%02x\n", __func__, status[1]);
+
+	dev_cnt = status[0] & 0x7f;
+
+	dev_dbg(dev, "%s: repeater : dev cnt = %d\n", __func__, dev_cnt);
+
+	if (dev_cnt) {
+
+		if (hdcp_i2c_read(hdev, HDCP_KSVFIFO, dev_cnt * HDCP_KSV_SIZE,
+				ksv_list) < 0)
+			goto check_repeater_err;
+
+		cnt = 0;
+
+		do {
+			hdmi_write_bytes(hdev, HDMI_HDCP_KSV_LIST_(0),
+					&ksv_list[cnt * 5], HDCP_KSV_SIZE);
+
+			val = HDMI_HDCP_KSV_WRITE_DONE;
+
+			if (cnt == dev_cnt - 1)
+				val |= HDMI_HDCP_KSV_END;
+
+			hdmi_write(hdev, HDMI_HDCP_KSV_LIST_CON, val);
+
+			if (cnt < dev_cnt - 1) {
+				cnt2 = 0;
+				do {
+					val = hdmi_readb(hdev,
+						HDMI_HDCP_KSV_LIST_CON);
+					if (val & HDMI_HDCP_KSV_READ)
+						break;
+					cnt2++;
+				} while (cnt2 < KSV_LIST_RETRY_CNT);
+
+				if (cnt2 == KSV_LIST_RETRY_CNT)
+					dev_dbg(dev, "%s: ksv list not readed\n",
+							__func__);
+			}
+			cnt++;
+		} while (cnt < dev_cnt);
+	} else
+		hdmi_writeb(hdev, HDMI_HDCP_KSV_LIST_CON, HDMI_HDCP_KSV_LIST_EMPTY);
+
+	if (hdcp_i2c_read(hdev, HDCP_SHA1, SHA_1_HASH_SIZE, rx_v) < 0)
+		goto check_repeater_err;
+
+	for (i = 0; i < SHA_1_HASH_SIZE; i++)
+		dev_dbg(dev, "%s: [i2c] SHA-1 rx :: %02x\n", __func__, rx_v[i]);
+
+	hdmi_write_bytes(hdev, HDMI_HDCP_SHA1_(0), rx_v, SHA_1_HASH_SIZE);
+
+	val = hdmi_readb(hdev, HDMI_HDCP_SHA_RESULT);
+	if (val & HDMI_HDCP_SHA_VALID_RD) {
+		if (val & HDMI_HDCP_SHA_VALID) {
+			dev_dbg(dev, "%s: SHA-1 result is ok\n", __func__);
+			hdmi_writeb(hdev, HDMI_HDCP_SHA_RESULT, 0x0);
+		} else {
+			dev_dbg(dev, "%s: SHA-1 result is not vaild\n", __func__);
+			hdmi_writeb(hdev, HDMI_HDCP_SHA_RESULT, 0x0);
+			goto check_repeater_err;
+		}
+	} else {
+		dev_dbg(dev, "%s: SHA-1 result is not ready\n", __func__);
+		hdmi_writeb(hdev, HDMI_HDCP_SHA_RESULT, 0x0);
+		goto check_repeater_err;
+	}
+
+	dev_dbg(dev, "%s: check repeater is ok\n", __func__);
+	return 0;
+
+check_repeater_err:
+	dev_err(dev, "%s: check repeater is failed\n", __func__);
+	return -1;
+}
+
+static int hdcp_bksv(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	hdev->hdcp_info.auth_status = RECEIVER_READ_READY;
+
+	if (hdcp_read_bcaps(hdev) < 0)
+		goto bksv_start_err;
+
+	hdev->hdcp_info.auth_status = BCAPS_READ_DONE;
+
+	if (hdcp_read_bksv(hdev) < 0)
+		goto bksv_start_err;
+
+	hdev->hdcp_info.auth_status = BKSV_READ_DONE;
+
+	dev_dbg(dev, "%s: bksv start is ok\n", __func__);
+
+	return 0;
+
+bksv_start_err:
+	dev_err(dev, "%s: failed to start bksv\n", __func__);
+	msleep(100);
+	return -1;
+}
+
+static int hdcp_second_auth(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	int ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (!hdev->hdcp_info.hdcp_start)
+		goto second_auth_err;
+
+	if (!is_hdmi_streaming(hdev))
+		goto second_auth_err;
+
+	ret = hdmi_check_repeater(hdev);
+
+	if (!ret) {
+		hdev->hdcp_info.auth_status = SECOND_AUTHENTICATION_DONE;
+		hdmi_start_encryption(hdev);
+	} else {
+		switch (ret) {
+
+		case REPEATER_ILLEGAL_DEVICE_ERROR:
+			hdmi_writeb(hdev, HDMI_HDCP_CTRL2, 0x1);
+			mdelay(1);
+			hdmi_writeb(hdev, HDMI_HDCP_CTRL2, 0x0);
+
+			dev_dbg(dev, "%s: repeater : illegal device\n",
+					__func__);
+			break;
+		case REPEATER_TIMEOUT_ERROR:
+			hdmi_write_mask(hdev, HDMI_HDCP_CTRL1, ~0,
+					HDMI_HDCP_SET_REPEATER_TIMEOUT);
+			hdmi_write_mask(hdev, HDMI_HDCP_CTRL1, 0,
+					HDMI_HDCP_SET_REPEATER_TIMEOUT);
+
+			dev_dbg(dev, "%s: repeater : timeout\n", __func__);
+			break;
+		case MAX_CASCADE_EXCEEDED_ERROR:
+
+			dev_dbg(dev, "%s: repeater : exceeded MAX_CASCADE\n",
+					__func__);
+			break;
+		case MAX_DEVS_EXCEEDED_ERROR:
+
+			dev_dbg(dev, "%s: repeater : exceeded MAX_DEVS\n",
+					__func__);
+			break;
+		default:
+			break;
+		}
+
+		hdev->hdcp_info.auth_status = NOT_AUTHENTICATED;
+
+		goto second_auth_err;
+	}
+
+	dev_dbg(dev, "%s: second authentication is OK\n", __func__);
+	return 0;
+
+second_auth_err:
+	dev_dbg(dev, "%s: second authentication is failed\n", __func__);
+	return -1;
+}
+
+static int hdcp_write_aksv(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (hdev->hdcp_info.auth_status != BKSV_READ_DONE) {
+		dev_err(dev, "%s: bksv is not ready\n", __func__);
+		goto aksv_write_err;
+	}
+	if (!is_hdmi_streaming(hdev))
+		goto aksv_write_err;
+
+	if (hdcp_write_key(hdev, AN_SIZE, HDMI_HDCP_AN_(0), HDCP_AN) < 0)
+		goto aksv_write_err;
+
+	hdev->hdcp_info.auth_status = AN_WRITE_DONE;
+
+	dev_dbg(dev, "%s: write An is done\n", __func__);
+
+	if (hdcp_write_key(hdev, AKSV_SIZE, HDMI_HDCP_AKSV_(0), HDCP_AKSV) < 0)
+		goto aksv_write_err;
+
+	msleep(100);
+
+	hdev->hdcp_info.auth_status = AKSV_WRITE_DONE;
+
+	dev_dbg(dev, "%s: write aksv is done\n", __func__);
+	dev_dbg(dev, "%s: aksv start is OK\n", __func__);
+	return 0;
+
+aksv_write_err:
+	dev_err(dev, "%s: aksv start is failed\n", __func__);
+	return -1;
+}
+
+static int hdcp_check_ri(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (hdev->hdcp_info.auth_status < AKSV_WRITE_DONE) {
+		dev_dbg(dev, "%s: ri check is not ready\n", __func__);
+		goto check_ri_err;
+	}
+
+	if (!is_hdmi_streaming(hdev))
+		goto check_ri_err;
+
+	if (hdcp_read_ri(hdev) < 0)
+		goto check_ri_err;
+
+	if (hdev->hdcp_info.is_repeater)
+		hdev->hdcp_info.auth_status
+			= SECOND_AUTHENTICATION_RDY;
+	else {
+		hdev->hdcp_info.auth_status
+			= FIRST_AUTHENTICATION_DONE;
+		hdmi_start_encryption(hdev);
+	}
+
+	dev_dbg(dev, "%s: ri check is OK\n", __func__);
+	return 0;
+
+check_ri_err:
+	dev_err(dev, "%s: ri check is failed\n", __func__);
+	return -1;
+}
+
+static void hdcp_work(struct work_struct *work)
+{
+	struct hdmi_device *hdev = container_of(work, struct hdmi_device, work);
+
+	if (!hdev->hdcp_info.hdcp_start)
+		return;
+
+	if (!is_hdmi_streaming(hdev))
+		return;
+
+	if (hdev->hdcp_info.event & HDCP_EVENT_READ_BKSV_START) {
+		if (hdcp_bksv(hdev) < 0)
+			goto work_err;
+		else
+			hdev->hdcp_info.event &= ~HDCP_EVENT_READ_BKSV_START;
+	}
+
+	if (hdev->hdcp_info.event & HDCP_EVENT_SECOND_AUTH_START) {
+		if (hdcp_second_auth(hdev) < 0)
+			goto work_err;
+		else
+			hdev->hdcp_info.event &= ~HDCP_EVENT_SECOND_AUTH_START;
+	}
+
+	if (hdev->hdcp_info.event & HDCP_EVENT_WRITE_AKSV_START) {
+		if (hdcp_write_aksv(hdev) < 0)
+			goto work_err;
+		else
+			hdev->hdcp_info.event  &= ~HDCP_EVENT_WRITE_AKSV_START;
+	}
+
+	if (hdev->hdcp_info.event & HDCP_EVENT_CHECK_RI_START) {
+		if (hdcp_check_ri(hdev) < 0)
+			goto work_err;
+		else
+			hdev->hdcp_info.event &= ~HDCP_EVENT_CHECK_RI_START;
+	}
+	return;
+work_err:
+	if (!hdev->hdcp_info.hdcp_start)
+		return;
+	if (!is_hdmi_streaming(hdev))
+		return;
+
+	hdcp_reset_auth(hdev);
+}
+
+/* HDCP APIs for hdmi driver */
+irqreturn_t hdcp_irq_handler(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u32 event = 0;
+	u8 flag;
+	event = 0;
+
+	if (!hdev->streaming) {
+		hdev->hdcp_info.event		= HDCP_EVENT_STOP;
+		hdev->hdcp_info.auth_status	= NOT_AUTHENTICATED;
+		return IRQ_HANDLED;
+	}
+
+	flag = hdmi_readb(hdev, HDMI_STATUS);
+
+	if (flag & HDMI_WTFORACTIVERX_INT_OCC) {
+		event |= HDCP_EVENT_READ_BKSV_START;
+		hdmi_write_mask(hdev, HDMI_STATUS, ~0, HDMI_WTFORACTIVERX_INT_OCC);
+		hdmi_write(hdev, HDMI_HDCP_I2C_INT, 0x0);
+	}
+
+	if (flag & HDMI_WRITE_INT_OCC) {
+		event |= HDCP_EVENT_WRITE_AKSV_START;
+		hdmi_write_mask(hdev, HDMI_STATUS, ~0, HDMI_WRITE_INT_OCC);
+		hdmi_write(hdev, HDMI_HDCP_AN_INT, 0x0);
+	}
+
+	if (flag & HDMI_UPDATE_RI_INT_OCC) {
+		event |= HDCP_EVENT_CHECK_RI_START;
+		hdmi_write_mask(hdev, HDMI_STATUS, ~0, HDMI_UPDATE_RI_INT_OCC);
+		hdmi_write(hdev, HDMI_HDCP_RI_INT, 0x0);
+	}
+
+	if (flag & HDMI_WATCHDOG_INT_OCC) {
+		event |= HDCP_EVENT_SECOND_AUTH_START;
+		hdmi_write_mask(hdev, HDMI_STATUS, ~0, HDMI_WATCHDOG_INT_OCC);
+		hdmi_write(hdev, HDMI_HDCP_WDT_INT, 0x0);
+	}
+
+	if (!event) {
+		dev_dbg(dev, "%s: unknown irq\n", __func__);
+		return IRQ_HANDLED;
+	}
+
+	if (is_hdmi_streaming(hdev)) {
+		hdev->hdcp_info.event |= event;
+		queue_work(hdev->hdcp_wq, &hdev->work);
+	} else {
+		hdev->hdcp_info.event		= HDCP_EVENT_STOP;
+		hdev->hdcp_info.auth_status	= NOT_AUTHENTICATED;
+	}
+
+	return IRQ_HANDLED;
+}
+
+int hdcp_prepare(struct hdmi_device *hdev)
+{
+	hdev->hdcp_wq = create_workqueue("khdcpd");
+	if (hdev->hdcp_wq == NULL)
+		return -ENOMEM;
+
+	INIT_WORK(&hdev->work, hdcp_work);
+
+	spin_lock_init(&hdev->hdcp_info.reset_lock);
+
+#if defined(CONFIG_VIDEO_EXYNOS_HDCP)
+	hdev->hdcp_info.hdcp_enable = 1;
+#else
+	hdev->hdcp_info.hdcp_enable = 0;
+#endif
+	return 0;
+}
+
+int hdcp_start(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+
+	hdev->hdcp_info.event = HDCP_EVENT_STOP;
+	hdev->hdcp_info.auth_status = NOT_AUTHENTICATED;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	hdcp_sw_reset(hdev);
+
+	dev_dbg(dev, "%s: stop encryption\n", __func__);
+
+	hdcp_encryption(hdev, 0);
+
+	msleep(120);
+	if (hdcp_loadkey(hdev) < 0)
+		return -1;
+
+	hdmi_write(hdev, HDMI_GCP_CON, HDMI_GCP_CON_NO_TRAN);
+	hdmi_write(hdev, HDMI_STATUS_EN, HDMI_INT_EN_ALL);
+
+	hdmi_write(hdev, HDMI_HDCP_CTRL1, HDMI_HDCP_CP_DESIRED_EN);
+
+	hdmi_set_int_mask(hdev, HDMI_INTC_EN_HDCP, 1);
+
+	hdev->hdcp_info.hdcp_start = 1;
+
+	return 0;
+}
+
+int hdcp_stop(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	u8 val;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	hdmi_set_int_mask(hdev, HDMI_INTC_EN_HDCP, 0);
+
+	hdev->hdcp_info.event		= HDCP_EVENT_STOP;
+	hdev->hdcp_info.auth_status	= NOT_AUTHENTICATED;
+	hdev->hdcp_info.hdcp_start	= false;
+
+	hdmi_writeb(hdev, HDMI_HDCP_CTRL1, 0x0);
+
+	hdmi_sw_hpd_enable(hdev, 0);
+
+	val = HDMI_UPDATE_RI_INT_EN | HDMI_WRITE_INT_EN |
+		HDMI_WATCHDOG_INT_EN | HDMI_WTFORACTIVERX_INT_EN;
+	hdmi_write_mask(hdev, HDMI_STATUS_EN, 0, val);
+	hdmi_write_mask(hdev, HDMI_STATUS_EN, ~0, val);
+
+	hdmi_write_mask(hdev, HDMI_STATUS, ~0, HDMI_INT_EN_ALL);
+
+	dev_dbg(dev, "%s: stop encryption\n", __func__);
+	hdcp_encryption(hdev, 0);
+
+	hdmi_writeb(hdev, HDMI_HDCP_CHECK_RESULT, HDMI_HDCP_CLR_ALL_RESULTS);
+
+	return 0;
+}
diff --git a/drivers/media/video/exynos/tv/hdmi.h b/drivers/media/video/exynos/tv/hdmi.h
new file mode 100644
index 0000000..dbdebb6
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi.h
@@ -0,0 +1,407 @@
+/*
+ * Samsung HDMI interface driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Jiun Yu, <jiun.yu@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#ifndef SAMSUMG_HDMI_H
+#define SAMSUNG_HDMI_H
+
+#ifdef CONFIG_VIDEO_EXYNOS_HDMI_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/consumer.h>
+
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-device.h>
+
+#define INFOFRAME_CNT          2
+
+#define HDMI_VSI_VERSION       0x01;
+#define HDMI_AVI_VERSION       0x02;
+#define HDMI_VSI_LENGTH                0x05;
+#define HDMI_AVI_LENGTH                0x0d;
+
+/* HDMI audio configuration value */
+#define DEFAULT_SAMPLE_RATE	44100
+#define DEFAULT_BITS_PER_SAMPLE	16
+
+/* HDMI pad definitions */
+#define HDMI_PAD_SINK		0
+#define HDMI_PADS_NUM		1
+
+/* HPD state definitions */
+#define HPD_LOW		0
+#define HPD_HIGH	1
+
+enum HDMI_VIDEO_FORMAT {
+	HDMI_VIDEO_FORMAT_2D = 0x0,
+	/** refer to Table 8-12 HDMI_Video_Format in HDMI specification v1.4a */
+	HDMI_VIDEO_FORMAT_3D = 0x2
+};
+
+enum HDMI_3D_FORMAT {
+	/** refer to Table 8-13 3D_Structure in HDMI specification v1.4a */
+
+	/** Frame Packing */
+	HDMI_3D_FORMAT_FP = 0x0,
+	/** Top-and-Bottom */
+	HDMI_3D_FORMAT_TB = 0x6,
+	/** Side-by-Side Half */
+	HDMI_3D_FORMAT_SB_HALF = 0x8
+};
+
+enum HDMI_3D_EXT_DATA {
+	/* refer to Table H-3 3D_Ext_Data - Additional video format
+	 * information for Side-by-side(half) 3D structure */
+
+	/** Horizontal sub-sampleing */
+	HDMI_H_SUB_SAMPLE = 0x1
+};
+
+enum HDMI_OUTPUT_FMT {
+	HDMI_OUTPUT_RGB888 = 0x0,
+	HDMI_OUTPUT_YUV444 = 0x2
+};
+
+enum HDMI_PACKET_TYPE {
+	/** refer to Table 5-8 Packet Type in HDMI specification v1.4a */
+
+	/** InfoFrame packet type */
+	HDMI_PACKET_TYPE_INFOFRAME = 0X80,
+	/** Vendor-Specific InfoFrame */
+	HDMI_PACKET_TYPE_VSI = HDMI_PACKET_TYPE_INFOFRAME + 1,
+	/** Auxiliary Video information InfoFrame */
+	HDMI_PACKET_TYPE_AVI = HDMI_PACKET_TYPE_INFOFRAME + 2
+};
+
+enum HDMI_AUDIO_CODEC {
+	HDMI_AUDIO_PCM,
+	HDMI_AUDIO_AC3,
+	HDMI_AUDIO_MP3
+};
+
+enum HDCP_EVENT {
+	HDCP_EVENT_STOP			= 1 << 0,
+	HDCP_EVENT_START		= 1 << 1,
+	HDCP_EVENT_READ_BKSV_START	= 1 << 2,
+	HDCP_EVENT_WRITE_AKSV_START	= 1 << 4,
+	HDCP_EVENT_CHECK_RI_START	= 1 << 8,
+	HDCP_EVENT_SECOND_AUTH_START	= 1 << 16
+};
+
+enum HDCP_STATE {
+	NOT_AUTHENTICATED,
+	RECEIVER_READ_READY,
+	BCAPS_READ_DONE,
+	BKSV_READ_DONE,
+	AN_WRITE_DONE,
+	AKSV_WRITE_DONE,
+	FIRST_AUTHENTICATION_DONE,
+	SECOND_AUTHENTICATION_RDY,
+	SECOND_AUTHENTICATION_DONE,
+};
+
+#define DEFAULT_AUDIO_CODEC	HDMI_AUDIO_PCM
+
+struct hdmi_resources {
+	struct clk *hdmi;
+	struct clk *sclk_hdmi;
+	struct clk *sclk_pixel;
+	struct clk *sclk_hdmiphy;
+	struct clk *hdmiphy;
+	struct regulator_bulk_data *regul_bulk;
+	int regul_count;
+};
+
+struct hdmi_tg_regs {
+	u8 cmd;
+	u8 h_fsz_l;
+	u8 h_fsz_h;
+	u8 hact_st_l;
+	u8 hact_st_h;
+	u8 hact_sz_l;
+	u8 hact_sz_h;
+	u8 v_fsz_l;
+	u8 v_fsz_h;
+	u8 vsync_l;
+	u8 vsync_h;
+	u8 vsync2_l;
+	u8 vsync2_h;
+	u8 vact_st_l;
+	u8 vact_st_h;
+	u8 vact_sz_l;
+	u8 vact_sz_h;
+	u8 field_chg_l;
+	u8 field_chg_h;
+	u8 vact_st2_l;
+	u8 vact_st2_h;
+#ifndef CONFIG_CPU_EXYNOS4210
+	u8 vact_st3_l;
+	u8 vact_st3_h;
+	u8 vact_st4_l;
+	u8 vact_st4_h;
+#endif
+	u8 vsync_top_hdmi_l;
+	u8 vsync_top_hdmi_h;
+	u8 vsync_bot_hdmi_l;
+	u8 vsync_bot_hdmi_h;
+	u8 field_top_hdmi_l;
+	u8 field_top_hdmi_h;
+	u8 field_bot_hdmi_l;
+	u8 field_bot_hdmi_h;
+#ifndef CONFIG_CPU_EXYNOS4210
+	u8 tg_3d;
+#endif
+};
+
+struct hdmi_core_regs {
+#ifndef CONFIG_CPU_EXYNOS4210
+	u8 h_blank[2];
+	u8 v2_blank[2];
+	u8 v1_blank[2];
+	u8 v_line[2];
+	u8 h_line[2];
+	u8 hsync_pol[1];
+	u8 vsync_pol[1];
+	u8 int_pro_mode[1];
+	u8 v_blank_f0[2];
+	u8 v_blank_f1[2];
+	u8 h_sync_start[2];
+	u8 h_sync_end[2];
+	u8 v_sync_line_bef_2[2];
+	u8 v_sync_line_bef_1[2];
+	u8 v_sync_line_aft_2[2];
+	u8 v_sync_line_aft_1[2];
+	u8 v_sync_line_aft_pxl_2[2];
+	u8 v_sync_line_aft_pxl_1[2];
+	u8 v_blank_f2[2]; /* for 3D mode */
+	u8 v_blank_f3[2]; /* for 3D mode */
+	u8 v_blank_f4[2]; /* for 3D mode */
+	u8 v_blank_f5[2]; /* for 3D mode */
+	u8 v_sync_line_aft_3[2];
+	u8 v_sync_line_aft_4[2];
+	u8 v_sync_line_aft_5[2];
+	u8 v_sync_line_aft_6[2];
+	u8 v_sync_line_aft_pxl_3[2];
+	u8 v_sync_line_aft_pxl_4[2];
+	u8 v_sync_line_aft_pxl_5[2];
+	u8 v_sync_line_aft_pxl_6[2];
+	u8 vact_space_1[2];
+	u8 vact_space_2[2];
+	u8 vact_space_3[2];
+	u8 vact_space_4[2];
+	u8 vact_space_5[2];
+	u8 vact_space_6[2];
+#else
+	u8 h_blank[2];
+	u8 v_blank[3];
+	u8 h_v_line[3];
+	u8 vsync_pol[1];
+	u8 int_pro_mode[1];
+	u8 v_blank_f[3];
+	u8 h_sync_gen[3];
+	u8 v_sync_gen1[3];
+	u8 v_sync_gen2[3];
+	u8 v_sync_gen3[3];
+#endif
+};
+
+struct hdmi_3d_info {
+	enum HDMI_VIDEO_FORMAT is_3d;
+	enum HDMI_3D_FORMAT fmt_3d;
+};
+
+struct hdmi_preset_conf {
+	struct hdmi_core_regs core;
+	struct hdmi_tg_regs tg;
+	struct v4l2_mbus_framefmt mbus_fmt;
+};
+
+struct hdmi_driver_data {
+	int hdmiphy_bus;
+};
+
+struct hdmi_infoframe {
+	enum HDMI_PACKET_TYPE type;
+	u8 ver;
+	u8 len;
+};
+
+struct hdcp_info {
+	u8 is_repeater;
+	u32 hdcp_start;
+	int hdcp_enable;
+	spinlock_t reset_lock;
+
+	enum HDCP_EVENT	event;
+	enum HDCP_STATE	auth_status;
+};
+
+struct hdmi_device {
+	/** base address of HDMI registers */
+	void __iomem *regs;
+
+	/** HDMI interrupt */
+	unsigned int int_irq;
+	unsigned int ext_irq;
+	unsigned int curr_irq;
+
+	/** pointer to device parent */
+	struct device *dev;
+	/** subdev generated by HDMI device */
+	struct v4l2_subdev sd;
+	/** sink pad connected to mixer */
+	struct media_pad pad;
+	/** V4L2 device structure */
+	struct v4l2_device v4l2_dev;
+	/** subdev of HDMIPHY interface */
+	struct v4l2_subdev *phy_sd;
+	/** configuration of current graphic mode */
+	const struct hdmi_preset_conf *cur_conf;
+	/** current preset */
+	u32 cur_preset;
+	/** other resources */
+	struct hdmi_resources res;
+	/** HDMI is streaming or not */
+	int streaming;
+	/** supported HDMI InfoFrame */
+	struct hdmi_infoframe infoframe[INFOFRAME_CNT];
+	/** audio on/off control flag */
+	int audio_enable;
+	/** audio sample rate */
+	int sample_rate;
+	/** audio bits per sample */
+	int bits_per_sample;
+	/** current audio codec type */
+	enum HDMI_AUDIO_CODEC audio_codec;
+	/** HDMI output format */
+	enum HDMI_OUTPUT_FMT output_fmt;
+
+	/** HDCP information */
+	struct hdcp_info hdcp_info;
+	struct work_struct work;
+	struct work_struct hpd_work;
+	struct workqueue_struct	*hdcp_wq;
+	struct workqueue_struct *hpd_wq;
+
+	/* HPD releated */
+	bool hpd_user_checked;
+	atomic_t hpd_state;
+	spinlock_t hpd_lock;
+
+	/* choose DVI or HDMI mode */
+	int dvi_mode;
+};
+
+struct hdmi_conf {
+	u32 preset;
+	const struct hdmi_preset_conf *conf;
+	const struct hdmi_3d_info *info;
+};
+extern const struct hdmi_conf hdmi_conf[];
+
+struct hdmiphy_conf {
+	u32 preset;
+	const u8 *data;
+};
+extern const struct hdmiphy_conf hdmiphy_conf[];
+extern const int hdmi_pre_cnt;
+extern const int hdmiphy_conf_cnt;
+
+const struct hdmi_3d_info *hdmi_preset2info(u32 preset);
+
+irqreturn_t hdmi_irq_handler(int irq, void *dev_data);
+int hdmi_conf_apply(struct hdmi_device *hdmi_dev);
+int is_hdmiphy_ready(struct hdmi_device *hdev);
+void hdmi_enable(struct hdmi_device *hdev, int on);
+void hdmi_hpd_enable(struct hdmi_device *hdev, int on);
+void hdmi_tg_enable(struct hdmi_device *hdev, int on);
+void hdmi_reg_stop_vsi(struct hdmi_device *hdev);
+void hdmi_reg_infoframe(struct hdmi_device *hdev,
+		struct hdmi_infoframe *infoframe);
+void hdmi_reg_set_acr(struct hdmi_device *hdev);
+void hdmi_reg_spdif_audio_init(struct hdmi_device *hdev);
+void hdmi_reg_i2s_audio_init(struct hdmi_device *hdev);
+void hdmi_audio_enable(struct hdmi_device *hdev, int on);
+void hdmi_bluescreen_enable(struct hdmi_device *hdev, int on);
+void hdmi_reg_mute(struct hdmi_device *hdev, int on);
+int hdmi_hpd_status(struct hdmi_device *hdev);
+int is_hdmi_streaming(struct hdmi_device *hdev);
+u8 hdmi_get_int_mask(struct hdmi_device *hdev);
+void hdmi_set_int_mask(struct hdmi_device *hdev, u8 mask, int en);
+void hdmi_sw_hpd_enable(struct hdmi_device *hdev, int en);
+void hdmi_sw_hpd_plug(struct hdmi_device *hdev, int en);
+void hdmi_phy_sw_reset(struct hdmi_device *hdev);
+void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix);
+void hdmi_set_3d_info(struct hdmi_device *hdev);
+void hdmi_set_dvi_mode(struct hdmi_device *hdev);
+
+/** HDCP functions */
+irqreturn_t hdcp_irq_handler(struct hdmi_device *hdev);
+int hdcp_stop(struct hdmi_device *hdev);
+int hdcp_start(struct hdmi_device *hdev);
+int hdcp_prepare(struct hdmi_device *hdev);
+int hdcp_i2c_read(struct hdmi_device *hdev, u8 offset, int bytes, u8 *buf);
+int hdcp_i2c_write(struct hdmi_device *hdev, u8 offset, int bytes, u8 *buf);
+
+static inline
+void hdmi_write(struct hdmi_device *hdev, u32 reg_id, u32 value)
+{
+	writel(value, hdev->regs + reg_id);
+}
+
+static inline
+void hdmi_write_mask(struct hdmi_device *hdev, u32 reg_id, u32 value, u32 mask)
+{
+	u32 old = readl(hdev->regs + reg_id);
+	value = (value & mask) | (old & ~mask);
+	writel(value, hdev->regs + reg_id);
+}
+
+static inline
+void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value)
+{
+	writeb(value, hdev->regs + reg_id);
+}
+
+static inline void hdmi_write_bytes(struct hdmi_device *hdev, u32 reg_id,
+		u8 *buf, int bytes)
+{
+	int i;
+
+	for (i = 0; i < bytes; ++i)
+		writeb(buf[i], hdev->regs + reg_id + i * 4);
+}
+
+static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id)
+{
+	return readl(hdev->regs + reg_id);
+}
+
+static inline u8 hdmi_readb(struct hdmi_device *hdev, u32 reg_id)
+{
+	return readb(hdev->regs + reg_id);
+}
+
+static inline void hdmi_read_bytes(struct hdmi_device *hdev, u32 reg_id,
+		u8 *buf, int bytes)
+{
+	int i;
+
+	for (i = 0; i < bytes; ++i)
+		buf[i] = readb(hdev->regs + reg_id + i * 4);
+}
+
+#endif /* SAMSUNG_HDMI_H */
diff --git a/drivers/media/video/exynos/tv/hdmi_cec.c b/drivers/media/video/exynos/tv/hdmi_cec.c
new file mode 100644
index 0000000..3ae783b
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi_cec.c
@@ -0,0 +1,433 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_cec_ctrl.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * cec interface file for Samsung TVOut driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/poll.h>
+#include <linux/miscdevice.h>
+#include <linux/clk.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <plat/tvout.h>
+
+#include "cec.h"
+
+#define CEC_IOC_MAGIC        'c'
+#define CEC_IOC_SETLADDR     _IOW(CEC_IOC_MAGIC, 0, unsigned int)
+
+#define VERSION   "1.0" /* Driver version number */
+#define CEC_MINOR 243	/* Major 10, Minor 242, /dev/cec */
+
+
+#define CEC_STATUS_TX_RUNNING       (1<<0)
+#define CEC_STATUS_TX_TRANSFERRING  (1<<1)
+#define CEC_STATUS_TX_DONE          (1<<2)
+#define CEC_STATUS_TX_ERROR         (1<<3)
+#define CEC_STATUS_TX_BYTES         (0xFF<<8)
+#define CEC_STATUS_RX_RUNNING       (1<<16)
+#define CEC_STATUS_RX_RECEIVING     (1<<17)
+#define CEC_STATUS_RX_DONE          (1<<18)
+#define CEC_STATUS_RX_ERROR         (1<<19)
+#define CEC_STATUS_RX_BCAST         (1<<20)
+#define CEC_STATUS_RX_BYTES         (0xFF<<24)
+
+
+/* CEC Rx buffer size */
+#define CEC_RX_BUFF_SIZE            16
+/* CEC Tx buffer size */
+#define CEC_TX_BUFF_SIZE            16
+
+#define TV_CLK_GET_WITH_ERR_CHECK(clk, pdev, clk_name)			\
+		do {							\
+			clk = clk_get(&pdev->dev, clk_name);		\
+			if (IS_ERR(clk)) {				\
+				printk(KERN_ERR				\
+				"failed to find clock %s\n", clk_name);	\
+				return -ENOENT;				\
+			}						\
+		} while (0);
+
+static atomic_t hdmi_on = ATOMIC_INIT(0);
+static DEFINE_MUTEX(cec_lock);
+struct clk *hdmi_cec_clk;
+
+static int s5p_cec_open(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+
+	mutex_lock(&cec_lock);
+	clk_enable(hdmi_cec_clk);
+
+	if (atomic_read(&hdmi_on)) {
+		tvout_dbg("do not allow multiple open for tvout cec\n");
+		ret = -EBUSY;
+		goto err_multi_open;
+	} else
+		atomic_inc(&hdmi_on);
+
+	s5p_cec_reset();
+
+	s5p_cec_set_divider();
+
+	s5p_cec_threshold();
+
+	s5p_cec_unmask_tx_interrupts();
+
+	s5p_cec_set_rx_state(STATE_RX);
+	s5p_cec_unmask_rx_interrupts();
+	s5p_cec_enable_rx();
+
+err_multi_open:
+	mutex_unlock(&cec_lock);
+
+	return ret;
+}
+
+static int s5p_cec_release(struct inode *inode, struct file *file)
+{
+	atomic_dec(&hdmi_on);
+
+	s5p_cec_mask_tx_interrupts();
+	s5p_cec_mask_rx_interrupts();
+
+	clk_disable(hdmi_cec_clk);
+	clk_put(hdmi_cec_clk);
+
+	return 0;
+}
+
+static ssize_t s5p_cec_read(struct file *file, char __user *buffer,
+			size_t count, loff_t *ppos)
+{
+	ssize_t retval;
+	unsigned long spin_flags;
+
+	if (wait_event_interruptible(cec_rx_struct.waitq,
+			atomic_read(&cec_rx_struct.state) == STATE_DONE)) {
+		return -ERESTARTSYS;
+	}
+	spin_lock_irqsave(&cec_rx_struct.lock, spin_flags);
+
+	if (cec_rx_struct.size > count) {
+		spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+
+		return -1;
+	}
+
+	if (copy_to_user(buffer, cec_rx_struct.buffer, cec_rx_struct.size)) {
+		spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+		printk(KERN_ERR " copy_to_user() failed!\n");
+
+		return -EFAULT;
+	}
+
+	retval = cec_rx_struct.size;
+
+	s5p_cec_set_rx_state(STATE_RX);
+	spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+
+	return retval;
+}
+
+static ssize_t s5p_cec_write(struct file *file, const char __user *buffer,
+			size_t count, loff_t *ppos)
+{
+	char *data;
+
+	/* check data size */
+
+	if (count > CEC_TX_BUFF_SIZE || count == 0)
+		return -1;
+
+	data = kmalloc(count, GFP_KERNEL);
+
+	if (!data) {
+		printk(KERN_ERR " kmalloc() failed!\n");
+
+		return -1;
+	}
+
+	if (copy_from_user(data, buffer, count)) {
+		printk(KERN_ERR " copy_from_user() failed!\n");
+		kfree(data);
+
+		return -EFAULT;
+	}
+
+	s5p_cec_copy_packet(data, count);
+
+	kfree(data);
+
+	/* wait for interrupt */
+	if (wait_event_interruptible(cec_tx_struct.waitq,
+		atomic_read(&cec_tx_struct.state)
+		!= STATE_TX)) {
+
+		return -ERESTARTSYS;
+	}
+
+	if (atomic_read(&cec_tx_struct.state) == STATE_ERROR)
+		return -1;
+
+	return count;
+}
+
+#if 0
+static int s5p_cec_ioctl(struct inode *inode, struct file *file, u32 cmd,
+			unsigned long arg)
+#else
+static long s5p_cec_ioctl(struct file *file, unsigned int cmd,
+						unsigned long arg)
+#endif
+{
+	u32 laddr;
+
+	switch (cmd) {
+	case CEC_IOC_SETLADDR:
+		if (get_user(laddr, (u32 __user *) arg))
+			return -EFAULT;
+
+		tvout_dbg("logical address = 0x%02x\n", laddr);
+
+		s5p_cec_set_addr(laddr);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static u32 s5p_cec_poll(struct file *file, poll_table *wait)
+{
+	poll_wait(file, &cec_rx_struct.waitq, wait);
+
+	if (atomic_read(&cec_rx_struct.state) == STATE_DONE)
+		return POLLIN | POLLRDNORM;
+
+	return 0;
+}
+
+static const struct file_operations cec_fops = {
+	.owner   = THIS_MODULE,
+	.open    = s5p_cec_open,
+	.release = s5p_cec_release,
+	.read    = s5p_cec_read,
+	.write   = s5p_cec_write,
+#if 1
+	.unlocked_ioctl = s5p_cec_ioctl,
+#else
+	.ioctl   = s5p_cec_ioctl,
+#endif
+	.poll    = s5p_cec_poll,
+};
+
+static struct miscdevice cec_misc_device = {
+	.minor = CEC_MINOR,
+	.name  = "CEC",
+	.fops  = &cec_fops,
+};
+
+static irqreturn_t s5p_cec_irq_handler(int irq, void *dev_id)
+{
+
+	u32 status = 0;
+
+	status = s5p_cec_get_status();
+
+	if (status & CEC_STATUS_TX_DONE) {
+		if (status & CEC_STATUS_TX_ERROR) {
+			tvout_dbg(" CEC_STATUS_TX_ERROR!\n");
+			s5p_cec_set_tx_state(STATE_ERROR);
+		} else {
+			tvout_dbg(" CEC_STATUS_TX_DONE!\n");
+			s5p_cec_set_tx_state(STATE_DONE);
+		}
+
+		s5p_clr_pending_tx();
+
+		wake_up_interruptible(&cec_tx_struct.waitq);
+	}
+
+	if (status & CEC_STATUS_RX_DONE) {
+		if (status & CEC_STATUS_RX_ERROR) {
+			tvout_dbg(" CEC_STATUS_RX_ERROR!\n");
+			s5p_cec_rx_reset();
+
+		} else {
+			u32 size;
+
+			tvout_dbg(" CEC_STATUS_RX_DONE!\n");
+
+			/* copy data from internal buffer */
+			size = status >> 24;
+
+			spin_lock(&cec_rx_struct.lock);
+
+			s5p_cec_get_rx_buf(size, cec_rx_struct.buffer);
+
+			cec_rx_struct.size = size;
+
+			s5p_cec_set_rx_state(STATE_DONE);
+
+			spin_unlock(&cec_rx_struct.lock);
+
+			s5p_cec_enable_rx();
+		}
+
+		/* clear interrupt pending bit */
+		s5p_clr_pending_rx();
+
+		wake_up_interruptible(&cec_rx_struct.waitq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit s5p_cec_probe(struct platform_device *pdev)
+{
+	struct s5p_platform_cec *pdata;
+	u8 *buffer;
+	int ret;
+	struct resource *res;
+
+	pdata = to_tvout_plat(&pdev->dev);
+
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdev);
+
+
+	s5p_cec_mem_probe(pdev);
+
+	if (misc_register(&cec_misc_device)) {
+		printk(KERN_WARNING " Couldn't register device 10, %d.\n",
+			CEC_MINOR);
+
+		return -EBUSY;
+	}
+
+#if 0
+	irq_num = platform_get_irq(pdev, 0);
+
+	if (irq_num < 0) {
+		printk(KERN_ERR  "failed to get %s irq resource\n", "cec");
+		ret = -ENOENT;
+
+		return ret;
+	}
+#endif
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to get irq resource.\n");
+		ret = -ENOENT;
+		return ret;
+	}
+
+	ret = request_irq(res->start, s5p_cec_irq_handler, IRQF_DISABLED,
+		pdev->name, &pdev->id);
+
+	if (ret != 0) {
+		printk(KERN_ERR  "failed to install %s irq (%d)\n", "cec", ret);
+
+		return ret;
+	}
+
+	init_waitqueue_head(&cec_rx_struct.waitq);
+	spin_lock_init(&cec_rx_struct.lock);
+	init_waitqueue_head(&cec_tx_struct.waitq);
+
+	buffer = kmalloc(CEC_TX_BUFF_SIZE, GFP_KERNEL);
+
+	if (!buffer) {
+		printk(KERN_ERR " kmalloc() failed!\n");
+		misc_deregister(&cec_misc_device);
+
+		return -EIO;
+	}
+
+	cec_rx_struct.buffer = buffer;
+
+	cec_rx_struct.size   = 0;
+	TV_CLK_GET_WITH_ERR_CHECK(hdmi_cec_clk, pdev, "sclk_cec");
+
+	dev_info(&pdev->dev, "probe successful\n");
+
+	return 0;
+}
+
+static int __devexit s5p_cec_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_cec_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int s5p_cec_resume(struct platform_device *dev)
+{
+	return 0;
+}
+#else
+#define s5p_cec_suspend NULL
+#define s5p_cec_resume NULL
+#endif
+
+static struct platform_driver s5p_cec_driver = {
+	.probe		= s5p_cec_probe,
+	.remove		= __devexit_p(s5p_cec_remove),
+	.suspend	= s5p_cec_suspend,
+	.resume		= s5p_cec_resume,
+	.driver		= {
+		.name	= "s5p-tvout-cec",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static char banner[] __initdata =
+	"S5P CEC for Exynos4 Driver, (c) 2009 Samsung Electronics\n";
+
+static int __init s5p_cec_init(void)
+{
+	int ret;
+
+	printk(banner);
+
+	ret = platform_driver_register(&s5p_cec_driver);
+
+	if (ret) {
+		printk(KERN_ERR "Platform Device Register Failed %d\n", ret);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+static void __exit s5p_cec_exit(void)
+{
+	kfree(cec_rx_struct.buffer);
+
+	platform_driver_unregister(&s5p_cec_driver);
+}
+
+module_init(s5p_cec_init);
+module_exit(s5p_cec_exit);
+
+MODULE_AUTHOR("SangPil Moon");
+MODULE_DESCRIPTION("S5P CEC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/exynos/tv/hdmi_cec_ctrl.c b/drivers/media/video/exynos/tv/hdmi_cec_ctrl.c
new file mode 100644
index 0000000..ec34091
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi_cec_ctrl.c
@@ -0,0 +1,266 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/cec.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * cec ftn file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/irqreturn.h>
+#include <linux/stddef.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-cec.h>
+
+#include "cec.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_CEC_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "\t\t[CEC] %s(): " fmt,	\
+			__func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+#define S5P_HDMI_FIN			24000000
+#define CEC_DIV_RATIO			320000
+
+#define CEC_MESSAGE_BROADCAST_MASK	0x0F
+#define CEC_MESSAGE_BROADCAST		0x0F
+#define CEC_FILTER_THRESHOLD		0x15
+
+static struct resource	*cec_mem;
+void __iomem		*cec_base;
+
+struct cec_rx_struct cec_rx_struct;
+struct cec_tx_struct cec_tx_struct;
+
+void s5p_cec_set_divider(void)
+{
+	u32 div_ratio, reg, div_val;
+
+	div_ratio  = S5P_HDMI_FIN / CEC_DIV_RATIO - 1;
+
+	reg = readl(S5P_HDMI_PHY_CONTROL);
+	reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16);
+
+	writel(reg, S5P_HDMI_PHY_CONTROL);
+
+	div_val = CEC_DIV_RATIO * 0.00005 - 1;
+
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_3);
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_2);
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_1);
+	writeb(div_val, cec_base + S5P_CES_DIVISOR_0);
+}
+
+void s5p_cec_enable_rx(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_RX_CTRL);
+	reg |= S5P_CES_RX_CTRL_ENABLE;
+	writeb(reg, cec_base + S5P_CES_RX_CTRL);
+}
+
+void s5p_cec_mask_rx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg |= S5P_CES_IRQ_RX_DONE;
+	reg |= S5P_CES_IRQ_RX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_unmask_rx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg &= ~S5P_CES_IRQ_RX_DONE;
+	reg &= ~S5P_CES_IRQ_RX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_mask_tx_interrupts(void)
+{
+	u8 reg;
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg |= S5P_CES_IRQ_TX_DONE;
+	reg |= S5P_CES_IRQ_TX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+
+}
+
+void s5p_cec_unmask_tx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg &= ~S5P_CES_IRQ_TX_DONE;
+	reg &= ~S5P_CES_IRQ_TX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_reset(void)
+{
+	writeb(S5P_CES_RX_CTRL_RESET, cec_base + S5P_CES_RX_CTRL);
+	writeb(S5P_CES_TX_CTRL_RESET, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_tx_reset(void)
+{
+	writeb(S5P_CES_TX_CTRL_RESET, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_rx_reset(void)
+{
+	writeb(S5P_CES_RX_CTRL_RESET, cec_base + S5P_CES_RX_CTRL);
+}
+
+void s5p_cec_threshold(void)
+{
+	writeb(CEC_FILTER_THRESHOLD, cec_base + S5P_CES_RX_FILTER_TH);
+	writeb(0, cec_base + S5P_CES_RX_FILTER_CTRL);
+}
+
+void s5p_cec_set_tx_state(enum cec_state state)
+{
+	atomic_set(&cec_tx_struct.state, state);
+}
+
+void s5p_cec_set_rx_state(enum cec_state state)
+{
+	atomic_set(&cec_rx_struct.state, state);
+}
+
+void s5p_cec_copy_packet(char *data, size_t count)
+{
+	int i = 0;
+	u8 reg;
+
+	while (i < count) {
+		writeb(data[i], cec_base + (S5P_CES_TX_BUFF0 + (i * 4)));
+		i++;
+	}
+
+	writeb(count, cec_base + S5P_CES_TX_BYTES);
+	s5p_cec_set_tx_state(STATE_TX);
+	reg = readb(cec_base + S5P_CES_TX_CTRL);
+	reg |= S5P_CES_TX_CTRL_START;
+
+	if ((data[0] & CEC_MESSAGE_BROADCAST_MASK) == CEC_MESSAGE_BROADCAST)
+		reg |= S5P_CES_TX_CTRL_BCAST;
+	else
+		reg &= ~S5P_CES_TX_CTRL_BCAST;
+
+	reg |= 0x50;
+	writeb(reg, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_set_addr(u32 addr)
+{
+	writeb(addr & 0x0F, cec_base + S5P_CES_LOGIC_ADDR);
+}
+
+u32 s5p_cec_get_status(void)
+{
+	u32 status = 0;
+
+	status = readb(cec_base + S5P_CES_STATUS_0);
+	status |= readb(cec_base + S5P_CES_STATUS_1) << 8;
+	status |= readb(cec_base + S5P_CES_STATUS_2) << 16;
+	status |= readb(cec_base + S5P_CES_STATUS_3) << 24;
+
+	tvout_dbg("status = 0x%x!\n", status);
+
+	return status;
+}
+
+void s5p_clr_pending_tx(void)
+{
+	writeb(S5P_CES_IRQ_TX_DONE | S5P_CES_IRQ_TX_ERROR,
+					cec_base + S5P_CES_IRQ_CLEAR);
+}
+
+void s5p_clr_pending_rx(void)
+{
+	writeb(S5P_CES_IRQ_RX_DONE | S5P_CES_IRQ_RX_ERROR,
+					cec_base + S5P_CES_IRQ_CLEAR);
+}
+
+void s5p_cec_get_rx_buf(u32 size, u8 *buffer)
+{
+	u32 i = 0;
+
+	while (i < size) {
+		buffer[i] = readb(cec_base + S5P_CES_RX_BUFF0 + (i * 4));
+		i++;
+	}
+}
+
+int __init s5p_cec_mem_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	size_t	size;
+	int	ret;
+
+	dev_dbg(&pdev->dev, "%s\n", __func__);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (res == NULL) {
+		dev_err(&pdev->dev,
+			"failed to get memory region resource for cec\n");
+		return -ENOENT;
+	}
+
+	size = (res->end - res->start) + 1;
+	cec_mem = request_mem_region(res->start, size, pdev->name);
+
+	if (cec_mem == NULL) {
+		dev_err(&pdev->dev,
+			"failed to get memory region for cec\n");
+		return -ENOENT;
+	}
+
+	cec_base = ioremap(res->start, size);
+
+	if (cec_base == NULL) {
+		dev_err(&pdev->dev,
+			"failed to ioremap address region for cec\n");
+		return -ENOENT;
+	}
+
+	return ret;
+}
+
+int __init s5p_cec_mem_release(struct platform_device *pdev)
+{
+	iounmap(cec_base);
+
+	if (cec_mem != NULL) {
+		if (release_resource(cec_mem))
+			dev_err(&pdev->dev,
+				"Can't remove tvout drv !!\n");
+
+		kfree(cec_mem);
+
+		cec_mem = NULL;
+	}
+
+	return 0;
+}
diff --git a/drivers/media/video/exynos/tv/hdmi_drv.c b/drivers/media/video/exynos/tv/hdmi_drv.c
new file mode 100644
index 0000000..1c18a25
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi_drv.c
@@ -0,0 +1,916 @@
+/*
+ * Samsung HDMI interface driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+#include "hdmi.h"
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <media/v4l2-subdev.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/bug.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/sched.h>
+#include <plat/tvout.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-device.h>
+#include <media/exynos_mc.h>
+
+MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
+MODULE_DESCRIPTION("Samsung HDMI");
+MODULE_LICENSE("GPL");
+
+/* default preset configured on probe */
+#define HDMI_DEFAULT_PRESET V4L2_DV_1080P60
+
+/* I2C module and id for HDMIPHY */
+static struct i2c_board_info hdmiphy_info = {
+	I2C_BOARD_INFO("hdmiphy", 0x38),
+};
+
+static struct hdmi_driver_data hdmi_driver_data[] = {
+	{ .hdmiphy_bus = 3 },
+	{ .hdmiphy_bus = 8 },
+	{ .hdmiphy_bus = 8 },
+};
+
+static struct platform_device_id hdmi_driver_types[] = {
+	{
+		.name		= "s5pv210-hdmi",
+		.driver_data	= (unsigned long)&hdmi_driver_data[0],
+	}, {
+		.name		= "exynos4-hdmi",
+		.driver_data	= (unsigned long)&hdmi_driver_data[1],
+	}, {
+		.name		= "exynos5-hdmi",
+		.driver_data	= (unsigned long)&hdmi_driver_data[2],
+	}, {
+		/* end node */
+	}
+};
+
+static const struct v4l2_subdev_ops hdmi_sd_ops;
+
+static struct hdmi_device *sd_to_hdmi_dev(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct hdmi_device, sd);
+}
+
+static int set_external_hpd_int(struct hdmi_device *hdev)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdev->hpd_lock, flags);
+
+	s5p_v4l2_int_src_ext_hpd();
+	/* irq change by TV power status */
+	if (hdev->curr_irq != hdev->ext_irq) {
+		disable_irq(hdev->curr_irq);
+		free_irq(hdev->curr_irq, hdev);
+	} else {
+		spin_unlock_irqrestore(&hdev->hpd_lock, flags);
+		return ret;
+	}
+
+	hdev->curr_irq = hdev->ext_irq;
+	ret = request_irq(hdev->curr_irq, hdmi_irq_handler,
+			IRQ_TYPE_EDGE_BOTH, "hdmi", hdev);
+
+	if (ret)
+		dev_err(hdev->dev, "request change failed.\n");
+
+	dev_info(hdev->dev, "HDMI interrupt source is changed : external\n");
+
+	spin_unlock_irqrestore(&hdev->hpd_lock, flags);
+	return ret;
+}
+
+static int set_internal_hpd_int(struct hdmi_device *hdev)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdev->hpd_lock, flags);
+
+	s5p_v4l2_int_src_hdmi_hpd();
+	/* irq change by TV power status */
+	if (hdev->curr_irq != hdev->int_irq) {
+		disable_irq(hdev->curr_irq);
+		free_irq(hdev->curr_irq, hdev);
+	} else {
+		spin_unlock_irqrestore(&hdev->hpd_lock, flags);
+		return ret;
+	}
+
+	hdev->curr_irq = hdev->int_irq;
+	ret = request_irq(hdev->curr_irq, hdmi_irq_handler,
+			0, "hdmi", hdev);
+	if (ret)
+		dev_err(hdev->dev, "request change failed.\n");
+
+	dev_info(hdev->dev, "HDMI interrupt source is changed : internal\n");
+	spin_unlock_irqrestore(&hdev->hpd_lock, flags);
+
+	return ret;
+}
+
+static const struct hdmi_preset_conf *hdmi_preset2conf(u32 preset)
+{
+	int i;
+
+	for (i = 0; i < hdmi_pre_cnt; ++i)
+		if (hdmi_conf[i].preset == preset)
+			return  hdmi_conf[i].conf;
+	return NULL;
+}
+
+const struct hdmi_3d_info *hdmi_preset2info(u32 preset)
+{
+	int i;
+
+	for (i = 0; i < hdmi_pre_cnt; ++i)
+		if (hdmi_conf[i].preset == preset)
+			return  hdmi_conf[i].info;
+	return NULL;
+}
+
+static int hdmi_set_infoframe(struct hdmi_device *hdev)
+{
+	struct hdmi_infoframe infoframe;
+	const struct hdmi_3d_info *info;
+
+	info = hdmi_preset2info(hdev->cur_preset);
+
+	if (info->is_3d == HDMI_VIDEO_FORMAT_3D) {
+		infoframe.type = HDMI_PACKET_TYPE_VSI;
+		infoframe.ver = HDMI_VSI_VERSION;
+		infoframe.len = HDMI_VSI_LENGTH;
+		hdmi_reg_infoframe(hdev, &infoframe);
+	} else
+		hdmi_reg_stop_vsi(hdev);
+
+	infoframe.type = HDMI_PACKET_TYPE_AVI;
+	infoframe.ver = HDMI_AVI_VERSION;
+	infoframe.len = HDMI_AVI_LENGTH;
+	hdmi_reg_infoframe(hdev, &infoframe);
+
+	return 0;
+}
+
+static int hdmi_set_packets(struct hdmi_device *hdev)
+{
+	hdmi_reg_set_acr(hdev);
+	return 0;
+}
+
+static int hdmi_streamon(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	struct hdmi_resources *res = &hdev->res;
+	int ret, tries;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	hdev->streaming = 1;
+	ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1);
+	if (ret)
+		return ret;
+
+	/* waiting for HDMIPHY's PLL to get to steady state */
+	for (tries = 100; tries; --tries) {
+		if (is_hdmiphy_ready(hdev))
+			break;
+
+		mdelay(1);
+	}
+	/* steady state not achieved */
+	if (tries == 0) {
+		dev_err(dev, "hdmiphy's pll could not reach steady state.\n");
+		v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
+		hdmi_dumpregs(hdev, "s_stream");
+		return -EIO;
+	}
+
+	/* hdmiphy clock is used for HDMI in streaming mode */
+	clk_disable(res->sclk_hdmi);
+	clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy);
+	clk_enable(res->sclk_hdmi);
+
+	/* 3D test */
+	hdmi_set_infoframe(hdev);
+
+	/* set packets for audio */
+	hdmi_set_packets(hdev);
+
+	/* init audio */
+#if defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_I2S)
+	hdmi_reg_i2s_audio_init(hdev);
+#elif defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_SPDIF)
+	hdmi_reg_spdif_audio_init(hdev);
+#endif
+	/* enbale HDMI audio */
+	if (hdev->audio_enable)
+		hdmi_audio_enable(hdev, 1);
+
+	hdmi_set_dvi_mode(hdev);
+
+	/* enable HDMI and timing generator */
+	hdmi_enable(hdev, 1);
+	hdmi_tg_enable(hdev, 1);
+
+	/* start HDCP if enabled */
+	if (hdev->hdcp_info.hdcp_enable) {
+		ret = hdcp_start(hdev);
+		if (ret)
+			return ret;
+	}
+
+	hdmi_dumpregs(hdev, "streamon");
+	return 0;
+}
+
+static int hdmi_streamoff(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	struct hdmi_resources *res = &hdev->res;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (hdev->hdcp_info.hdcp_enable)
+		hdcp_stop(hdev);
+
+	hdmi_audio_enable(hdev, 0);
+	hdmi_enable(hdev, 0);
+	hdmi_tg_enable(hdev, 0);
+
+	/* pixel(vpll) clock is used for HDMI in config mode */
+	clk_disable(res->sclk_hdmi);
+	clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
+	clk_enable(res->sclk_hdmi);
+
+	v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
+
+	hdev->streaming = 0;
+	hdmi_dumpregs(hdev, "streamoff");
+	return 0;
+}
+
+static int hdmi_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+
+	dev_dbg(dev, "%s(%d)\n", __func__, enable);
+	if (enable)
+		return hdmi_streamon(hdev);
+	return hdmi_streamoff(hdev);
+}
+
+static void hdmi_resource_poweron(struct hdmi_resources *res)
+{
+	/* power-on hdmi physical interface */
+	clk_enable(res->hdmiphy);
+	/* use VPP as parent clock; HDMIPHY is not working yet */
+	clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
+	/* turn clocks on */
+	clk_enable(res->sclk_hdmi);
+}
+
+static int hdmi_runtime_resume(struct device *dev);
+static int hdmi_runtime_suspend(struct device *dev);
+
+static int hdmi_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+
+	/* If runtime PM is not implemented, hdmi_runtime_resume
+	 * and hdmi_runtime_suspend functions are directly called.
+	 */
+#ifdef CONFIG_PM_RUNTIME
+	int ret;
+
+	if (on) {
+		clk_enable(hdev->res.hdmi);
+		hdmi_hpd_enable(hdev, 1);
+		ret = pm_runtime_get_sync(hdev->dev);
+		set_internal_hpd_int(hdev);
+	} else {
+		hdmi_hpd_enable(hdev, 0);
+		set_external_hpd_int(hdev);
+		ret = pm_runtime_put_sync(hdev->dev);
+		clk_disable(hdev->res.hdmi);
+	}
+	/* only values < 0 indicate errors */
+	return IS_ERR_VALUE(ret) ? ret : 0;
+#else
+	if (on) {
+		clk_enable(hdev->res.hdmi);
+		hdmi_hpd_enable(hdev, 1);
+		set_internal_hpd_int(hdev);
+		hdmi_runtime_resume(hdev->dev);
+	} else {
+		hdmi_hpd_enable(hdev, 0);
+		set_external_hpd_int(hdev);
+		clk_disable(hdev->res.hdmi);
+		hdmi_runtime_suspend(hdev->dev);
+	}
+	return 0;
+#endif
+}
+
+int hdmi_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+	int ret = 0;
+
+	dev_dbg(dev, "%s start\n", __func__);
+
+	switch (ctrl->id) {
+	case V4L2_CID_TV_SET_DVI_MODE:
+		hdev->dvi_mode = ctrl->value;
+		break;
+	default:
+		dev_err(dev, "invalid control id\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+int hdmi_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdev->hpd_lock, flags);
+
+	if (!pm_runtime_suspended(hdev->dev) && !hdev->hpd_user_checked)
+		ctrl->value = hdmi_hpd_status(hdev);
+	else
+		ctrl->value = atomic_read(&hdev->hpd_state);
+
+	dev_dbg(dev, "HDMI cable is %s\n", ctrl->value ?
+			"connected" : "disconnected");
+
+	spin_unlock_irqrestore(&hdev->hpd_lock, flags);
+	return 0;
+}
+
+static int hdmi_s_dv_preset(struct v4l2_subdev *sd,
+	struct v4l2_dv_preset *preset)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+	const struct hdmi_preset_conf *conf;
+
+	conf = hdmi_preset2conf(preset->preset);
+	if (conf == NULL) {
+		dev_err(dev, "preset (%u) not supported\n", preset->preset);
+		return -EINVAL;
+	}
+	hdev->cur_conf = conf;
+	hdev->cur_preset = preset->preset;
+	return 0;
+}
+
+static int hdmi_g_dv_preset(struct v4l2_subdev *sd,
+	struct v4l2_dv_preset *preset)
+{
+	memset(preset, 0, sizeof(*preset));
+	preset->preset = sd_to_hdmi_dev(sd)->cur_preset;
+	return 0;
+}
+
+static int hdmi_g_mbus_fmt(struct v4l2_subdev *sd,
+	  struct v4l2_mbus_framefmt *fmt)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+
+	dev_dbg(dev, "%s\n", __func__);
+	if (!hdev->cur_conf)
+		return -EINVAL;
+	*fmt = hdev->cur_conf->mbus_fmt;
+	return 0;
+}
+
+static int hdmi_s_mbus_fmt(struct v4l2_subdev *sd,
+	  struct v4l2_mbus_framefmt *fmt)
+{
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct device *dev = hdev->dev;
+
+	dev_dbg(dev, "%s\n", __func__);
+	if (fmt->code == V4L2_MBUS_FMT_YUV8_1X24)
+		hdev->output_fmt = HDMI_OUTPUT_YUV444;
+	else
+		hdev->output_fmt = HDMI_OUTPUT_RGB888;
+
+	return 0;
+}
+
+static int hdmi_enum_dv_presets(struct v4l2_subdev *sd,
+	struct v4l2_dv_enum_preset *preset)
+{
+	if (preset->index >= hdmi_pre_cnt)
+		return -EINVAL;
+	return v4l_fill_dv_preset_info(hdmi_conf[preset->index].preset, preset);
+}
+
+static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = {
+	.s_power = hdmi_s_power,
+	.s_ctrl = hdmi_s_ctrl,
+	.g_ctrl = hdmi_g_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops hdmi_sd_video_ops = {
+	.s_dv_preset = hdmi_s_dv_preset,
+	.g_dv_preset = hdmi_g_dv_preset,
+	.enum_dv_presets = hdmi_enum_dv_presets,
+	.g_mbus_fmt = hdmi_g_mbus_fmt,
+	.s_mbus_fmt = hdmi_s_mbus_fmt,
+	.s_stream = hdmi_s_stream,
+};
+
+static const struct v4l2_subdev_ops hdmi_sd_ops = {
+	.core = &hdmi_sd_core_ops,
+	.video = &hdmi_sd_video_ops,
+};
+
+static int hdmi_runtime_suspend(struct device *dev)
+{
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct hdmi_resources *res = &hdev->res;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	/* HDMI PHY off sequence
+	 * LINK off -> PHY off -> HDMI_PHY_CONTROL disable */
+
+	/* turn clocks off */
+	clk_disable(res->sclk_hdmi);
+
+	v4l2_subdev_call(hdev->phy_sd, core, s_power, 0);
+
+	/* power-off hdmiphy */
+	clk_disable(res->hdmiphy);
+
+	return 0;
+}
+
+static int hdmi_runtime_resume(struct device *dev)
+{
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
+	struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
+	struct hdmi_resources *res = &hdev->res;
+	int ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	hdmi_resource_poweron(&hdev->res);
+
+	hdmi_phy_sw_reset(hdev);
+	ret = v4l2_subdev_call(hdev->phy_sd, core, s_power, 1);
+	if (ret) {
+		dev_err(dev, "failed to turn on hdmiphy\n");
+		goto fail;
+	}
+
+	ret = hdmi_conf_apply(hdev);
+	if (ret)
+		goto fail;
+
+	dev_dbg(dev, "poweron succeed\n");
+
+	return 0;
+
+fail:
+	clk_disable(res->sclk_hdmi);
+	v4l2_subdev_call(hdev->phy_sd, core, s_power, 0);
+	clk_disable(res->hdmiphy);
+	dev_err(dev, "poweron failed\n");
+
+	return ret;
+}
+
+static const struct dev_pm_ops hdmi_pm_ops = {
+	.runtime_suspend = hdmi_runtime_suspend,
+	.runtime_resume	 = hdmi_runtime_resume,
+};
+
+static void hdmi_resources_cleanup(struct hdmi_device *hdev)
+{
+	struct hdmi_resources *res = &hdev->res;
+
+	dev_dbg(hdev->dev, "HDMI resource cleanup\n");
+	/* put clocks */
+	if (!IS_ERR_OR_NULL(res->hdmiphy))
+		clk_put(res->hdmiphy);
+	if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
+		clk_put(res->sclk_hdmiphy);
+	if (!IS_ERR_OR_NULL(res->sclk_pixel))
+		clk_put(res->sclk_pixel);
+	if (!IS_ERR_OR_NULL(res->sclk_hdmi))
+		clk_put(res->sclk_hdmi);
+	if (!IS_ERR_OR_NULL(res->hdmi))
+		clk_put(res->hdmi);
+	memset(res, 0, sizeof *res);
+}
+
+static int hdmi_resources_init(struct hdmi_device *hdev)
+{
+	struct device *dev = hdev->dev;
+	struct hdmi_resources *res = &hdev->res;
+
+	dev_dbg(dev, "HDMI resource init\n");
+
+	memset(res, 0, sizeof *res);
+	/* get clocks, power */
+
+	res->hdmi = clk_get(dev, "hdmi");
+	if (IS_ERR_OR_NULL(res->hdmi)) {
+		dev_err(dev, "failed to get clock 'hdmi'\n");
+		goto fail;
+	}
+	res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
+	if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
+		dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
+		goto fail;
+	}
+	res->sclk_pixel = clk_get(dev, "sclk_pixel");
+	if (IS_ERR_OR_NULL(res->sclk_pixel)) {
+		dev_err(dev, "failed to get clock 'sclk_pixel'\n");
+		goto fail;
+	}
+	res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
+	if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
+		dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n");
+		goto fail;
+	}
+	res->hdmiphy = clk_get(dev, "hdmiphy");
+	if (IS_ERR_OR_NULL(res->hdmiphy)) {
+		dev_err(dev, "failed to get clock 'hdmiphy'\n");
+		goto fail;
+	}
+
+	return 0;
+fail:
+	dev_err(dev, "HDMI resource init - failed\n");
+	hdmi_resources_cleanup(hdev);
+	return -ENODEV;
+}
+
+static int hdmi_link_setup(struct media_entity *entity,
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
+{
+	return 0;
+}
+
+/* hdmi entity operations */
+static const struct media_entity_operations hdmi_entity_ops = {
+	.link_setup = hdmi_link_setup,
+};
+
+static int hdmi_register_entity(struct hdmi_device *hdev)
+{
+	struct v4l2_subdev *sd = &hdev->sd;
+	struct v4l2_device *v4l2_dev;
+	struct media_pad *pads = &hdev->pad;
+	struct media_entity *me = &sd->entity;
+	struct device *dev = hdev->dev;
+	struct exynos_md *md;
+	int ret;
+
+	dev_dbg(dev, "HDMI entity init\n");
+
+	/* init hdmi subdev */
+	v4l2_subdev_init(sd, &hdmi_sd_ops);
+	sd->owner = THIS_MODULE;
+	strlcpy(sd->name, "s5p-hdmi", sizeof(sd->name));
+
+	dev_set_drvdata(dev, sd);
+
+	/* init hdmi sub-device as entity */
+	pads[HDMI_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	me->ops = &hdmi_entity_ops;
+	ret = media_entity_init(me, HDMI_PADS_NUM, pads, 0);
+	if (ret) {
+		dev_err(dev, "failed to initialize media entity\n");
+		return ret;
+	}
+
+	/* get output media ptr for registering hdmi's sd */
+	md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
+	if (!md) {
+		dev_err(dev, "failed to get output media device\n");
+		return -ENODEV;
+	}
+
+	v4l2_dev = &md->v4l2_dev;
+
+	/* regiser HDMI subdev as entity to v4l2_dev pointer of
+	 * output media device
+	 */
+	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+	if (ret) {
+		dev_err(dev, "failed to register HDMI subdev\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void hdmi_entity_info_print(struct hdmi_device *hdev)
+{
+	struct v4l2_subdev *sd = &hdev->sd;
+	struct media_entity *me = &sd->entity;
+
+	dev_dbg(hdev->dev, "\n************* HDMI entity info **************\n");
+	dev_dbg(hdev->dev, "[SUB DEVICE INFO]\n");
+	entity_info_print(me, hdev->dev);
+	dev_dbg(hdev->dev, "*********************************************\n\n");
+}
+
+static void s5p_hpd_kobject_uevent(struct work_struct *work)
+{
+	struct hdmi_device *hdev = container_of(work, struct hdmi_device,
+						hpd_work);
+	char *disconnected[2] = { "HDMI_STATE=offline", NULL };
+	char *connected[2]    = { "HDMI_STATE=online", NULL };
+	char **envp = NULL;
+	int state = atomic_read(&hdev->hpd_state);
+
+	/* irq setting by TV power on/off status */
+	if (!pm_runtime_suspended(hdev->dev))
+		set_internal_hpd_int(hdev);
+	else
+		set_external_hpd_int(hdev);
+
+	if (state)
+		envp = connected;
+	else
+		envp = disconnected;
+
+	hdev->hpd_user_checked = true;
+
+	kobject_uevent_env(&hdev->dev->kobj, KOBJ_CHANGE, envp);
+	pr_info("%s: sent uevent %s\n", __func__, envp[0]);
+}
+
+static int __devinit hdmi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct i2c_adapter *phy_adapter;
+	struct hdmi_device *hdmi_dev = NULL;
+	struct hdmi_driver_data *drv_data;
+	int ret;
+	unsigned int irq_type;
+
+	dev_dbg(dev, "probe start\n");
+
+	hdmi_dev = kzalloc(sizeof(*hdmi_dev), GFP_KERNEL);
+	if (!hdmi_dev) {
+		dev_err(dev, "out of memory\n");
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	hdmi_dev->dev = dev;
+
+	ret = hdmi_resources_init(hdmi_dev);
+	if (ret)
+		goto fail_hdev;
+
+	/* mapping HDMI registers */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "get memory resource failed.\n");
+		ret = -ENXIO;
+		goto fail_init;
+	}
+
+	hdmi_dev->regs = ioremap(res->start, resource_size(res));
+	if (hdmi_dev->regs == NULL) {
+		dev_err(dev, "register mapping failed.\n");
+		ret = -ENXIO;
+		goto fail_hdev;
+	}
+
+	/* External hpd */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(dev, "get external interrupt resource failed.\n");
+		ret = -ENXIO;
+		goto fail_regs;
+	}
+	hdmi_dev->ext_irq = res->start;
+
+	/* Internal hpd */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (res == NULL) {
+		dev_err(dev, "get internal interrupt resource failed.\n");
+		ret = -ENXIO;
+		goto fail_regs;
+	}
+	hdmi_dev->int_irq = res->start;
+
+	/* workqueue for HPD */
+	hdmi_dev->hpd_wq = create_workqueue("hdmi-hpd");
+	if (hdmi_dev->hpd_wq == NULL)
+		ret = -ENXIO;
+	INIT_WORK(&hdmi_dev->hpd_work, s5p_hpd_kobject_uevent);
+
+	/* setting v4l2 name to prevent WARN_ON in v4l2_device_register */
+	strlcpy(hdmi_dev->v4l2_dev.name, dev_name(dev),
+		sizeof(hdmi_dev->v4l2_dev.name));
+	/* passing NULL owner prevents driver from erasing drvdata */
+	ret = v4l2_device_register(NULL, &hdmi_dev->v4l2_dev);
+	if (ret) {
+		dev_err(dev, "could not register v4l2 device.\n");
+		goto fail_regs;
+	}
+
+	drv_data = (struct hdmi_driver_data *)
+		platform_get_device_id(pdev)->driver_data;
+	dev_info(dev, "hdmiphy i2c bus number = %d\n", drv_data->hdmiphy_bus);
+
+	phy_adapter = i2c_get_adapter(drv_data->hdmiphy_bus);
+	if (phy_adapter == NULL) {
+		dev_err(dev, "adapter request failed\n");
+		ret = -ENXIO;
+		goto fail_vdev;
+	}
+
+	hdmi_dev->phy_sd = v4l2_i2c_new_subdev_board(&hdmi_dev->v4l2_dev,
+		phy_adapter, &hdmiphy_info, NULL);
+	/* on failure or not adapter is no longer useful */
+	i2c_put_adapter(phy_adapter);
+	if (hdmi_dev->phy_sd == NULL) {
+		dev_err(dev, "missing subdev for hdmiphy\n");
+		ret = -ENODEV;
+		goto fail_vdev;
+	}
+
+	/* HDMI PHY power off
+	 * HDMI PHY is on as default configuration
+	 * So, HDMI PHY must be turned off if it's not used */
+	clk_enable(hdmi_dev->res.hdmiphy);
+	v4l2_subdev_call(hdmi_dev->phy_sd, core, s_power, 0);
+	clk_disable(hdmi_dev->res.hdmiphy);
+
+	pm_runtime_enable(dev);
+
+	/* irq setting by TV power on/off status */
+	if (!pm_runtime_suspended(hdmi_dev->dev)) {
+		hdmi_dev->curr_irq = hdmi_dev->int_irq;
+		irq_type = 0;
+		s5p_v4l2_int_src_hdmi_hpd();
+	} else {
+		if (s5p_v4l2_hpd_read_gpio())
+			atomic_set(&hdmi_dev->hpd_state, HPD_HIGH);
+		else
+			atomic_set(&hdmi_dev->hpd_state, HPD_LOW);
+		hdmi_dev->curr_irq = hdmi_dev->ext_irq;
+		irq_type = IRQ_TYPE_EDGE_BOTH;
+		s5p_v4l2_int_src_ext_hpd();
+	}
+
+	hdmi_dev->hpd_user_checked = false;
+
+	ret = request_irq(hdmi_dev->curr_irq, hdmi_irq_handler,
+			irq_type, "hdmi", hdmi_dev);
+
+	if (ret) {
+		dev_err(dev, "request interrupt failed.\n");
+		goto fail_vdev;
+	}
+
+	hdmi_dev->cur_preset = HDMI_DEFAULT_PRESET;
+	/* FIXME: missing fail preset is not supported */
+	hdmi_dev->cur_conf = hdmi_preset2conf(hdmi_dev->cur_preset);
+
+	/* default audio configuration : enable audio */
+	hdmi_dev->audio_enable = 1;
+	hdmi_dev->sample_rate = DEFAULT_SAMPLE_RATE;
+	hdmi_dev->bits_per_sample = DEFAULT_BITS_PER_SAMPLE;
+	hdmi_dev->audio_codec = DEFAULT_AUDIO_CODEC;
+
+	/* register hdmi subdev as entity */
+	ret = hdmi_register_entity(hdmi_dev);
+	if (ret)
+		goto fail_irq;
+
+	hdmi_entity_info_print(hdmi_dev);
+
+	/* initialize hdcp resource */
+	ret = hdcp_prepare(hdmi_dev);
+	if (ret)
+		goto fail_irq;
+
+	dev_info(dev, "probe sucessful\n");
+
+	return 0;
+
+fail_vdev:
+	v4l2_device_unregister(&hdmi_dev->v4l2_dev);
+
+fail_irq:
+	free_irq(hdmi_dev->curr_irq, hdmi_dev);
+
+fail_regs:
+	iounmap(hdmi_dev->regs);
+
+fail_init:
+	hdmi_resources_cleanup(hdmi_dev);
+
+fail_hdev:
+	kfree(hdmi_dev);
+
+fail:
+	dev_err(dev, "probe failed\n");
+	return ret;
+}
+
+static int __devexit hdmi_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
+	struct hdmi_device *hdmi_dev = sd_to_hdmi_dev(sd);
+
+	pm_runtime_disable(dev);
+	clk_disable(hdmi_dev->res.hdmi);
+	v4l2_device_unregister(&hdmi_dev->v4l2_dev);
+	disable_irq(hdmi_dev->curr_irq);
+	free_irq(hdmi_dev->curr_irq, hdmi_dev);
+	iounmap(hdmi_dev->regs);
+	hdmi_resources_cleanup(hdmi_dev);
+	flush_workqueue(hdmi_dev->hdcp_wq);
+	destroy_workqueue(hdmi_dev->hdcp_wq);
+	kfree(hdmi_dev);
+	dev_info(dev, "remove sucessful\n");
+
+	return 0;
+}
+
+static struct platform_driver hdmi_driver __refdata = {
+	.probe = hdmi_probe,
+	.remove = __devexit_p(hdmi_remove),
+	.id_table = hdmi_driver_types,
+	.driver = {
+		.name = "s5p-hdmi",
+		.owner = THIS_MODULE,
+		.pm = &hdmi_pm_ops,
+	}
+};
+
+/* D R I V E R   I N I T I A L I Z A T I O N */
+
+static int __init hdmi_init(void)
+{
+	int ret;
+	static const char banner[] __initdata = KERN_INFO \
+		"Samsung HDMI output driver, "
+		"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
+	printk(banner);
+
+	ret = platform_driver_register(&hdmi_driver);
+	if (ret)
+		printk(KERN_ERR "HDMI platform driver register failed\n");
+
+	return ret;
+}
+module_init(hdmi_init);
+
+static void __exit hdmi_exit(void)
+{
+	platform_driver_unregister(&hdmi_driver);
+}
+module_exit(hdmi_exit);
+
+
diff --git a/drivers/media/video/exynos/tv/hdmi_reg_4210.c b/drivers/media/video/exynos/tv/hdmi_reg_4210.c
new file mode 100644
index 0000000..51a37c8
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi_reg_4210.c
@@ -0,0 +1,450 @@
+/*
+ * Samsung HDMI driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Jiun Yu <jiun.yu@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include <linux/delay.h>
+
+#include "hdmi.h"
+#include "regs-hdmi-4210.h"
+
+static const struct hdmi_preset_conf hdmi_conf_480p = {
+	.core = {
+		.h_blank = {0x8a, 0x00},
+		.v_blank = {0x0d, 0x6a, 0x01},
+		.h_v_line = {0x0d, 0xa2, 0x35},
+		.vsync_pol = {0x01},
+		.int_pro_mode = {0x00},
+		.v_blank_f = {0x00, 0x00, 0x00},
+		.h_sync_gen = {0x0e, 0x30, 0x11},
+		.v_sync_gen1 = {0x0f, 0x90, 0x00},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x5a, 0x03, /* h_fsz */
+		0x8a, 0x00, 0xd0, 0x02, /* hact */
+		0x0d, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0xe0, 0x01, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+	},
+	.mbus_fmt = {
+		.width = 720,
+		.height = 480,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p60 = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v_blank = {0xee, 0xf2, 0x00},
+		.h_v_line = {0xee, 0x22, 0x67},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
+		.h_sync_gen = {0x6c, 0x50, 0x02},
+		.v_sync_gen1 = {0x0a, 0x50, 0x00},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
+	.core = {
+		.h_blank = {0xd0, 0x02},
+		.v_blank = {0x65, 0x6c, 0x01},
+		.h_v_line = {0x65, 0x04, 0xa5},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
+		.h_sync_gen = {0x0e, 0xea, 0x08},
+		.v_sync_gen1 = {0x09, 0x40, 0x00},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v_blank = {0x65, 0x6c, 0x01},
+		.h_v_line = {0x65, 0x84, 0x89},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
+		.h_sync_gen = {0x56, 0x08, 0x02},
+		.v_sync_gen1 = {0x09, 0x40, 0x00},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v_blank = {0x32, 0xb2, 0x00},
+		.h_v_line = {0x65, 0x84, 0x89},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f = {0x49, 0x2a, 0x23},
+		.h_sync_gen = {0x56, 0x08, 0x02},
+		.v_sync_gen1 = {0x07, 0x20, 0x00},
+		.v_sync_gen2 = {0x39, 0x42, 0x23},
+		.v_sync_gen3 = {0xa4, 0x44, 0x4a},
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x17, 0x01, 0x81, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+const struct hdmi_conf hdmi_conf[] = {
+	{ V4L2_DV_480P59_94, &hdmi_conf_480p },
+	{ V4L2_DV_720P59_94, &hdmi_conf_720p60 },
+	{ V4L2_DV_1080P50, &hdmi_conf_1080p50 },
+	{ V4L2_DV_1080P30, &hdmi_conf_1080p60 },
+	{ V4L2_DV_1080P60, &hdmi_conf_1080p60 },
+	{ V4L2_DV_1080I60, &hdmi_conf_1080i60 },
+};
+
+const int hdmi_pre_cnt = ARRAY_SIZE(hdmi_conf);
+
+irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
+{
+	struct hdmi_device *hdev = dev_data;
+	u32 intc_flag;
+
+	(void)irq;
+	intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG);
+	/* clearing flags for HPD plug/unplug */
+	if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
+		printk(KERN_INFO "unplugged\n");
+		hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
+			HDMI_INTC_FLAG_HPD_UNPLUG);
+	}
+	if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
+		printk(KERN_INFO "plugged\n");
+		hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
+			HDMI_INTC_FLAG_HPD_PLUG);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void hdmi_reg_init(struct hdmi_device *hdev)
+{
+	/* enable HPD interrupts */
+	hdmi_write_mask(hdev, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
+		HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
+	/* choose HDMI mode */
+	hdmi_write_mask(hdev, HDMI_MODE_SEL,
+		HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
+	/* disable bluescreen */
+	hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
+	/* choose bluescreen (fecal) color */
+	hdmi_writeb(hdev, HDMI_BLUE_SCREEN_0, 0x12);
+	hdmi_writeb(hdev, HDMI_BLUE_SCREEN_1, 0x34);
+	hdmi_writeb(hdev, HDMI_BLUE_SCREEN_2, 0x56);
+	/* enable AVI packet every vsync, fixes purple line problem */
+	hdmi_writeb(hdev, HDMI_AVI_CON, 0x02);
+	/* force YUV444, look to CEA-861-D, table 7 for more detail */
+	hdmi_writeb(hdev, HDMI_AVI_BYTE(0), 2 << 5);
+	hdmi_write_mask(hdev, HDMI_CON_1, 2, 3 << 5);
+}
+
+static void hdmi_timing_apply(struct hdmi_device *hdev,
+	const struct hdmi_preset_conf *conf)
+{
+	const struct hdmi_core_regs *core = &conf->core;
+	const struct hdmi_tg_regs *tg = &conf->tg;
+
+	/* setting core registers */
+	hdmi_writeb(hdev, HDMI_H_BLANK_0, core->h_blank[0]);
+	hdmi_writeb(hdev, HDMI_H_BLANK_1, core->h_blank[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_0, core->v_blank[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_1, core->v_blank[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_2, core->v_blank[2]);
+	hdmi_writeb(hdev, HDMI_H_V_LINE_0, core->h_v_line[0]);
+	hdmi_writeb(hdev, HDMI_H_V_LINE_1, core->h_v_line[1]);
+	hdmi_writeb(hdev, HDMI_H_V_LINE_2, core->h_v_line[2]);
+	hdmi_writeb(hdev, HDMI_VSYNC_POL, core->vsync_pol[0]);
+	hdmi_writeb(hdev, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F_0, core->v_blank_f[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F_1, core->v_blank_f[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F_2, core->v_blank_f[2]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_GEN_0, core->h_sync_gen[0]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_GEN_1, core->h_sync_gen[1]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_GEN_2, core->h_sync_gen[2]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
+	/* Timing generator registers */
+	hdmi_writeb(hdev, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
+	hdmi_writeb(hdev, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
+	hdmi_writeb(hdev, HDMI_TG_HACT_ST_L, tg->hact_st_l);
+	hdmi_writeb(hdev, HDMI_TG_HACT_ST_H, tg->hact_st_h);
+	hdmi_writeb(hdev, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
+	hdmi_writeb(hdev, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
+	hdmi_writeb(hdev, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
+	hdmi_writeb(hdev, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_L, tg->vsync_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_H, tg->vsync_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC2_L, tg->vsync2_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC2_H, tg->vsync2_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST_L, tg->vact_st_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST_H, tg->vact_st_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
+}
+
+int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
+{
+	struct device *dev = hdmi_dev->dev;
+	const struct hdmi_preset_conf *conf = hdmi_dev->cur_conf;
+	struct v4l2_dv_preset preset;
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	/* reset hdmiphy */
+	hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
+	mdelay(10);
+	hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT,  0, HDMI_PHY_SW_RSTOUT);
+	mdelay(10);
+
+	/* configure presets */
+	preset.preset = hdmi_dev->cur_preset;
+	ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
+	if (ret) {
+		dev_err(dev, "failed to set preset (%u)\n", preset.preset);
+		return ret;
+	}
+
+	/* resetting HDMI core */
+	hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT,  0, HDMI_CORE_SW_RSTOUT);
+	mdelay(10);
+	hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT);
+	mdelay(10);
+
+	hdmi_reg_init(hdmi_dev);
+
+	/* setting core registers */
+	hdmi_timing_apply(hdmi_dev, conf);
+
+	return 0;
+}
+
+int is_hdmiphy_ready(struct hdmi_device *hdev)
+{
+	u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
+	if (val & HDMI_PHY_STATUS_READY)
+		return 1;
+
+	return 0;
+}
+
+void hdmi_enable(struct hdmi_device *hdev, int on)
+{
+	if (on)
+		hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
+	else
+		hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
+}
+
+void hdmi_tg_enable(struct hdmi_device *hdev, int on)
+{
+	u32 mask;
+
+	mask = (hdev->cur_conf->mbus_fmt.field == V4L2_FIELD_INTERLACED) ?
+			HDMI_TG_EN | HDMI_FIELD_EN : HDMI_TG_EN;
+
+	if (on)
+		hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, mask);
+	else
+		hdmi_write_mask(hdev, HDMI_TG_CMD, 0, mask);
+}
+
+void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
+{
+#define DUMPREG(reg_id) \
+	dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
+		readl(hdev->regs + reg_id))
+
+	dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_INTC_FLAG);
+	DUMPREG(HDMI_INTC_CON);
+	DUMPREG(HDMI_HPD_STATUS);
+	DUMPREG(HDMI_PHY_RSTOUT);
+	DUMPREG(HDMI_PHY_VPLL);
+	DUMPREG(HDMI_PHY_CMU);
+	DUMPREG(HDMI_CORE_RSTOUT);
+
+	dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_CON_0);
+	DUMPREG(HDMI_CON_1);
+	DUMPREG(HDMI_CON_2);
+	DUMPREG(HDMI_SYS_STATUS);
+	DUMPREG(HDMI_PHY_STATUS);
+	DUMPREG(HDMI_STATUS_EN);
+	DUMPREG(HDMI_HPD);
+	DUMPREG(HDMI_MODE_SEL);
+	DUMPREG(HDMI_HPD_GEN);
+	DUMPREG(HDMI_DC_CONTROL);
+	DUMPREG(HDMI_VIDEO_PATTERN_GEN);
+
+	dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_H_BLANK_0);
+	DUMPREG(HDMI_H_BLANK_1);
+	DUMPREG(HDMI_V_BLANK_0);
+	DUMPREG(HDMI_V_BLANK_1);
+	DUMPREG(HDMI_V_BLANK_2);
+	DUMPREG(HDMI_H_V_LINE_0);
+	DUMPREG(HDMI_H_V_LINE_1);
+	DUMPREG(HDMI_H_V_LINE_2);
+	DUMPREG(HDMI_VSYNC_POL);
+	DUMPREG(HDMI_INT_PRO_MODE);
+	DUMPREG(HDMI_V_BLANK_F_0);
+	DUMPREG(HDMI_V_BLANK_F_1);
+	DUMPREG(HDMI_V_BLANK_F_2);
+	DUMPREG(HDMI_H_SYNC_GEN_0);
+	DUMPREG(HDMI_H_SYNC_GEN_1);
+	DUMPREG(HDMI_H_SYNC_GEN_2);
+	DUMPREG(HDMI_V_SYNC_GEN_1_0);
+	DUMPREG(HDMI_V_SYNC_GEN_1_1);
+	DUMPREG(HDMI_V_SYNC_GEN_1_2);
+	DUMPREG(HDMI_V_SYNC_GEN_2_0);
+	DUMPREG(HDMI_V_SYNC_GEN_2_1);
+	DUMPREG(HDMI_V_SYNC_GEN_2_2);
+	DUMPREG(HDMI_V_SYNC_GEN_3_0);
+	DUMPREG(HDMI_V_SYNC_GEN_3_1);
+	DUMPREG(HDMI_V_SYNC_GEN_3_2);
+
+	dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_TG_CMD);
+	DUMPREG(HDMI_TG_H_FSZ_L);
+	DUMPREG(HDMI_TG_H_FSZ_H);
+	DUMPREG(HDMI_TG_HACT_ST_L);
+	DUMPREG(HDMI_TG_HACT_ST_H);
+	DUMPREG(HDMI_TG_HACT_SZ_L);
+	DUMPREG(HDMI_TG_HACT_SZ_H);
+	DUMPREG(HDMI_TG_V_FSZ_L);
+	DUMPREG(HDMI_TG_V_FSZ_H);
+	DUMPREG(HDMI_TG_VSYNC_L);
+	DUMPREG(HDMI_TG_VSYNC_H);
+	DUMPREG(HDMI_TG_VSYNC2_L);
+	DUMPREG(HDMI_TG_VSYNC2_H);
+	DUMPREG(HDMI_TG_VACT_ST_L);
+	DUMPREG(HDMI_TG_VACT_ST_H);
+	DUMPREG(HDMI_TG_VACT_SZ_L);
+	DUMPREG(HDMI_TG_VACT_SZ_H);
+	DUMPREG(HDMI_TG_FIELD_CHG_L);
+	DUMPREG(HDMI_TG_FIELD_CHG_H);
+	DUMPREG(HDMI_TG_VACT_ST2_L);
+	DUMPREG(HDMI_TG_VACT_ST2_H);
+	DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
+	DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
+	DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
+	DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
+	DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
+	DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
+	DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
+	DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
+#undef DUMPREG
+}
diff --git a/drivers/media/video/exynos/tv/hdmi_reg_5250.c b/drivers/media/video/exynos/tv/hdmi_reg_5250.c
new file mode 100644
index 0000000..5d6475b
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmi_reg_5250.c
@@ -0,0 +1,2931 @@
+/*
+ * Samsung HDMI driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Jiun Yu <jiun.yu@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <plat/tvout.h>
+
+#include "hdmi.h"
+#include "regs-hdmi-5250.h"
+
+static const struct hdmi_preset_conf hdmi_conf_480p60 = {
+	.core = {
+		.h_blank = {0x8a, 0x00},
+		.v2_blank = {0x0d, 0x02},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x0d, 0x02},
+		.h_line = {0x5a, 0x03},
+		.hsync_pol = {0x01},
+		.vsync_pol = {0x01},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x0e, 0x00},
+		.h_sync_end = {0x4c, 0x00},
+		.v_sync_line_bef_2 = {0x0f, 0x00},
+		.v_sync_line_bef_1 = {0x09, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x5a, 0x03, /* h_fsz */
+		0x8a, 0x00, 0xd0, 0x02, /* hact */
+		0x0d, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0xe0, 0x01, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 720,
+		.height = 480,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p60 = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0xa4, 0x04},
+		.v_sync_line_aft_pxl_1 = {0xa4, 0x04},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_576p50 = {
+	.core = {
+		.h_blank = {0x90, 0x00},
+		.v2_blank = {0x71, 0x02},
+		.v1_blank = {0x31, 0x00},
+		.v_line = {0x71, 0x02},
+		.h_line = {0x60, 0x03},
+		.hsync_pol = {0x01},
+		.vsync_pol = {0x01},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x0a, 0x00},
+		.h_sync_end = {0x4a, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x60, 0x03, /* h_fsz */
+		0x90, 0x00, 0xd0, 0x02, /* hact */
+		0x71, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x31, 0x00, 0x40, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 720,
+		.height = 576,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p50 = {
+	.core = {
+		.h_blank = {0xbc, 0x02},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0xbc, 0x07},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0xb6, 0x01},
+		.h_sync_end = {0xde, 0x01},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbc, 0x07, /* h_fsz */
+		0xbc, 0x02, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i50 = {
+	.core = {
+		.h_blank = {0xd0, 0x02},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x50, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x0e, 0x02},
+		.h_sync_end = {0x3a, 0x02},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0x38, 0x07},
+		.v_sync_line_aft_pxl_1 = {0x38, 0x07},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x50, 0x0a, /* h_fsz */
+		0xd0, 0x02, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
+	.core = {
+		.h_blank = {0xd0, 0x02},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x50, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x0e, 0x02},
+		.h_sync_end = {0x3a, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x50, 0x0a, /* h_fsz */
+		0xd0, 0x02, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p30 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p24 = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p25 = {
+	.core = {
+		.h_blank = {0xd0, 0x02},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x50, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x0e, 0x02},
+		.h_sync_end = {0x3a, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x50, 0x0a, /* h_fsz */
+		0xd0, 0x02, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_480p59_94 = {
+	.core = {
+		.h_blank = {0x8a, 0x00},
+		.v2_blank = {0x0d, 0x02},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x0d, 0x02},
+		.h_line = {0x5a, 0x03},
+		.hsync_pol = {0x01},
+		.vsync_pol = {0x01},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x0e, 0x00},
+		.h_sync_end = {0x4c, 0x00},
+		.v_sync_line_bef_2 = {0x0f, 0x00},
+		.v_sync_line_bef_1 = {0x09, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x5a, 0x03, /* h_fsz */
+		0x8a, 0x00, 0xd0, 0x02, /* hact */
+		0x0d, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0xe0, 0x01, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 720,
+		.height = 480,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p59_94 = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i59_94 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0xa4, 0x04},
+		.v_sync_line_aft_pxl_1 = {0xa4, 0x04},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p59_94 = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p60_sb_half = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p60_tb = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p59_94_sb_half = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x00, 0x00, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p59_94_tb = {
+	.core = {
+		.h_blank = {0x72, 0x01},
+		.v2_blank = {0xee, 0x02},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xee, 0x02},
+		.h_line = {0x72, 0x06},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x6c, 0x00},
+		.h_sync_end = {0x94, 0x00},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x72, 0x06, /* h_fsz */
+		0x72, 0x01, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x00, 0x00, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p50_sb_half = {
+	.core = {
+		.h_blank = {0xbc, 0x02},
+		.v2_blank = {0xdc, 0x05},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xdc, 0x05},
+		.h_line = {0xbc, 0x07},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0xb6, 0x01},
+		.h_sync_end = {0xde, 0x01},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xee, 0x02},
+		.vact_space_2 = {0x0c, 0x03},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbc, 0x07, /* h_fsz */
+		0xbc, 0x02, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x00, 0x00, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_720p50_tb = {
+	.core = {
+		.h_blank = {0xbc, 0x02},
+		.v2_blank = {0xdc, 0x05},
+		.v1_blank = {0x1e, 0x00},
+		.v_line = {0xdc, 0x05},
+		.h_line = {0xbc, 0x07},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0xb6, 0x01},
+		.h_sync_end = {0xde, 0x01},
+		.v_sync_line_bef_2 = {0x0a, 0x00},
+		.v_sync_line_bef_1 = {0x05, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xee, 0x02},
+		.vact_space_2 = {0x0c, 0x03},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbc, 0x07, /* h_fsz */
+		0xbc, 0x02, 0x00, 0x05, /* hact */
+		0xee, 0x02, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x1e, 0x00, 0xd0, 0x02, /* vact */
+		0x00, 0x00, /* field_chg */
+		0x0c, 0x03, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1280,
+		.height = 720,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p24_fp = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0xca, 0x08},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0xca, 0x08},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0x65, 0x04},
+		.vact_space_2 = {0x92, 0x04},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0xca, 0x08, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x92, 0x04, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x01, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p24_sb_half = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p24_tb = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p23_98_fp = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0xca, 0x08},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0xca, 0x08},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0x65, 0x04},
+		.vact_space_2 = {0x92, 0x04},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0xca, 0x08, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x92, 0x04, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x01, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p23_98_sb_half = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p23_98_tb = {
+	.core = {
+		.h_blank = {0x3e, 0x03},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0xbe, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x7c, 0x02},
+		.h_sync_end = {0xa8, 0x02},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0xbe, 0x0a, /* h_fsz */
+		0x3e, 0x03, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i60_sb_half = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0xa4, 0x04},
+		.v_sync_line_aft_pxl_1 = {0xa4, 0x04},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x64, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x65, 0x04, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x7b, 0x04, /* vact_st3 */
+		0xae, 0x06, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i59_94_sb_half = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0xa4, 0x04},
+		.v_sync_line_aft_pxl_1 = {0xa4, 0x04},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x64, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x65, 0x04, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x7b, 0x04, /* vact_st3 */
+		0xae, 0x06, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080i50_sb_half = {
+	.core = {
+		.h_blank = {0xd0, 0x02},
+		.v2_blank = {0x32, 0x02},
+		.v1_blank = {0x16, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x50, 0x0a},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x01},
+		.v_blank_f0 = {0x49, 0x02},
+		.v_blank_f1 = {0x65, 0x04},
+		.h_sync_start = {0x0e, 0x02},
+		.h_sync_end = {0x3a, 0x02},
+		.v_sync_line_bef_2 = {0x07, 0x00},
+		.v_sync_line_bef_1 = {0x02, 0x00},
+		.v_sync_line_aft_2 = {0x39, 0x02},
+		.v_sync_line_aft_1 = {0x34, 0x02},
+		.v_sync_line_aft_pxl_2 = {0x38, 0x07},
+		.v_sync_line_aft_pxl_1 = {0x38, 0x07},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x50, 0x0a, /* h_fsz */
+		0xd0, 0x02, 0x80, 0x07, /* hact */
+		0x64, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x16, 0x00, 0x1c, 0x02, /* vact */
+		0x65, 0x04, /* field_chg */
+		0x49, 0x02, /* vact_st2 */
+		0x7b, 0x04, /* vact_st3 */
+		0xae, 0x06, /* vact_st4 */
+		0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_INTERLACED,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p60_sb_half = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p60_tb = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p30_sb_half = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_preset_conf hdmi_conf_1080p30_tb = {
+	.core = {
+		.h_blank = {0x18, 0x01},
+		.v2_blank = {0x65, 0x04},
+		.v1_blank = {0x2d, 0x00},
+		.v_line = {0x65, 0x04},
+		.h_line = {0x98, 0x08},
+		.hsync_pol = {0x00},
+		.vsync_pol = {0x00},
+		.int_pro_mode = {0x00},
+		.v_blank_f0 = {0xff, 0xff},
+		.v_blank_f1 = {0xff, 0xff},
+		.h_sync_start = {0x56, 0x00},
+		.h_sync_end = {0x82, 0x00},
+		.v_sync_line_bef_2 = {0x09, 0x00},
+		.v_sync_line_bef_1 = {0x04, 0x00},
+		.v_sync_line_aft_2 = {0xff, 0xff},
+		.v_sync_line_aft_1 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_2 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_1 = {0xff, 0xff},
+		.v_blank_f2 = {0xff, 0xff},
+		.v_blank_f3 = {0xff, 0xff},
+		.v_blank_f4 = {0xff, 0xff},
+		.v_blank_f5 = {0xff, 0xff},
+		.v_sync_line_aft_3 = {0xff, 0xff},
+		.v_sync_line_aft_4 = {0xff, 0xff},
+		.v_sync_line_aft_5 = {0xff, 0xff},
+		.v_sync_line_aft_6 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_3 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_4 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_5 = {0xff, 0xff},
+		.v_sync_line_aft_pxl_6 = {0xff, 0xff},
+		.vact_space_1 = {0xff, 0xff},
+		.vact_space_2 = {0xff, 0xff},
+		.vact_space_3 = {0xff, 0xff},
+		.vact_space_4 = {0xff, 0xff},
+		.vact_space_5 = {0xff, 0xff},
+		.vact_space_6 = {0xff, 0xff},
+		/* other don't care */
+	},
+	.tg = {
+		0x00, /* cmd */
+		0x98, 0x08, /* h_fsz */
+		0x18, 0x01, 0x80, 0x07, /* hact */
+		0x65, 0x04, /* v_fsz */
+		0x01, 0x00, 0x33, 0x02, /* vsync */
+		0x2d, 0x00, 0x38, 0x04, /* vact */
+		0x33, 0x02, /* field_chg */
+		0x48, 0x02, /* vact_st2 */
+		0x00, 0x00, /* vact_st3 */
+		0x00, 0x00, /* vact_st4 */
+		0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
+		0x01, 0x00, 0x33, 0x02, /* field top/bot */
+		0x00, /* 3d FP */
+	},
+	.mbus_fmt = {
+		.width = 1920,
+		.height = 1080,
+		.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
+		.field = V4L2_FIELD_NONE,
+	},
+};
+
+static const struct hdmi_3d_info info_2d = {
+	.is_3d = HDMI_VIDEO_FORMAT_2D,
+};
+
+static const struct hdmi_3d_info info_3d_sb_h = {
+	.is_3d = HDMI_VIDEO_FORMAT_3D,
+	.fmt_3d = HDMI_3D_FORMAT_SB_HALF,
+};
+
+static const struct hdmi_3d_info info_3d_tb = {
+	.is_3d = HDMI_VIDEO_FORMAT_3D,
+	.fmt_3d = HDMI_3D_FORMAT_TB,
+};
+
+static const struct hdmi_3d_info info_3d_fp = {
+	.is_3d = HDMI_VIDEO_FORMAT_3D,
+	.fmt_3d = HDMI_3D_FORMAT_FP,
+};
+
+const struct hdmi_conf hdmi_conf[] = {
+	{ V4L2_DV_480P59_94,	   &hdmi_conf_480p59_94,	&info_2d },
+	{ V4L2_DV_480P60,	   &hdmi_conf_480p60,		&info_2d },
+	{ V4L2_DV_576P50,	   &hdmi_conf_576p50,		&info_2d },
+	{ V4L2_DV_720P50,	   &hdmi_conf_720p50,		&info_2d },
+	{ V4L2_DV_720P59_94,	   &hdmi_conf_720p59_94,	&info_2d },
+	{ V4L2_DV_720P60,	   &hdmi_conf_720p60,		&info_2d },
+	{ V4L2_DV_1080I50,	   &hdmi_conf_1080i50,		&info_2d },
+	{ V4L2_DV_1080I59_94,	   &hdmi_conf_1080i59_94,	&info_2d },
+	{ V4L2_DV_1080I60,	   &hdmi_conf_1080i60,		&info_2d },
+	{ V4L2_DV_1080P24,	   &hdmi_conf_1080p24,		&info_2d },
+	{ V4L2_DV_1080P25,	   &hdmi_conf_1080p25,		&info_2d },
+	{ V4L2_DV_1080P30,	   &hdmi_conf_1080p30,		&info_2d },
+	{ V4L2_DV_1080P50,	   &hdmi_conf_1080p50,		&info_2d },
+	{ V4L2_DV_1080P59_94,	   &hdmi_conf_1080p59_94,	&info_2d },
+	{ V4L2_DV_1080P60,	   &hdmi_conf_1080p60,		&info_2d },
+	{ V4L2_DV_720P60_SB_HALF,  &hdmi_conf_720p60_sb_half,	&info_3d_sb_h },
+	{ V4L2_DV_720P60_TB,	   &hdmi_conf_720p60_tb,	&info_3d_tb },
+	{ V4L2_DV_720P59_94_SB_HALF, &hdmi_conf_720p59_94_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_720P59_94_TB,	   &hdmi_conf_720p59_94_tb,	&info_3d_tb },
+	{ V4L2_DV_720P50_SB_HALF,  &hdmi_conf_720p50_sb_half,	&info_3d_sb_h },
+	{ V4L2_DV_720P50_TB,	   &hdmi_conf_720p50_tb,	&info_3d_tb },
+	{ V4L2_DV_1080P24_FP,	   &hdmi_conf_1080p24_fp,	&info_3d_fp },
+	{ V4L2_DV_1080P24_SB_HALF, &hdmi_conf_1080p24_sb_half,	&info_3d_sb_h },
+	{ V4L2_DV_1080P24_TB,	   &hdmi_conf_1080p24_tb,	&info_3d_tb },
+	{ V4L2_DV_1080P23_98_FP,   &hdmi_conf_1080p23_98_fp,	&info_3d_fp },
+	{ V4L2_DV_1080P23_98_SB_HALF, &hdmi_conf_1080p23_98_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_1080P23_98_TB,   &hdmi_conf_1080p23_98_tb,	&info_3d_tb },
+	{ V4L2_DV_1080I60_SB_HALF, &hdmi_conf_1080i60_sb_half,	&info_3d_sb_h },
+	{ V4L2_DV_1080I59_94_SB_HALF, &hdmi_conf_1080i59_94_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_1080I50_SB_HALF, &hdmi_conf_1080i50_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_1080P60_SB_HALF, &hdmi_conf_1080p60_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_1080P60_TB, &hdmi_conf_1080p60_tb, &info_3d_tb },
+	{ V4L2_DV_1080P30_SB_HALF, &hdmi_conf_1080p30_sb_half, &info_3d_sb_h },
+	{ V4L2_DV_1080P30_TB, &hdmi_conf_1080p30_tb, &info_3d_tb },
+};
+
+const int hdmi_pre_cnt = ARRAY_SIZE(hdmi_conf);
+
+irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
+{
+	struct hdmi_device *hdev = dev_data;
+	u32 intc_flag;
+
+	if (!pm_runtime_suspended(hdev->dev)) {
+		intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG_0);
+		/* clearing flags for HPD plug/unplug */
+		if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
+			printk(KERN_INFO "unplugged\n");
+			if (hdev->hdcp_info.hdcp_enable)
+				hdcp_stop(hdev);
+			hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
+					HDMI_INTC_FLAG_HPD_UNPLUG);
+			atomic_set(&hdev->hpd_state, HPD_LOW);
+		}
+		if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
+			printk(KERN_INFO "plugged\n");
+			hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
+					HDMI_INTC_FLAG_HPD_PLUG);
+			atomic_set(&hdev->hpd_state, HPD_HIGH);
+		}
+		if (intc_flag & HDMI_INTC_FLAG_HDCP) {
+			printk(KERN_INFO "hdcp interrupt occur\n");
+			hdcp_irq_handler(hdev);
+			hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
+					HDMI_INTC_FLAG_HDCP);
+		}
+	} else{
+		if (s5p_v4l2_hpd_read_gpio())
+			atomic_set(&hdev->hpd_state, HPD_HIGH);
+		else
+			atomic_set(&hdev->hpd_state, HPD_LOW);
+	}
+
+	queue_work(hdev->hpd_wq, &hdev->hpd_work);
+
+	return IRQ_HANDLED;
+}
+
+void hdmi_reg_init(struct hdmi_device *hdev)
+{
+	/* enable HPD interrupts */
+	hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, HDMI_INTC_EN_GLOBAL |
+		HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
+	/* choose HDMI mode */
+	hdmi_write_mask(hdev, HDMI_MODE_SEL,
+		HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
+	/* disable bluescreen */
+	hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
+	/* enable AVI packet every vsync, fixes purple line problem */
+	hdmi_writeb(hdev, HDMI_AVI_CON, 0x02);
+	/* RGB888 is default output format of HDMI,
+	 * look to CEA-861-D, table 7 for more detail */
+	hdmi_writeb(hdev, HDMI_AVI_BYTE(1), 0 << 5);
+	hdmi_write_mask(hdev, HDMI_CON_1, 2, 3 << 5);
+
+}
+
+void hdmi_set_dvi_mode(struct hdmi_device *hdev)
+{
+	u32 val;
+
+	hdmi_write_mask(hdev, HDMI_MODE_SEL, hdev->dvi_mode ? HDMI_MODE_DVI_EN :
+		HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
+
+	if (hdev->dvi_mode)
+		val = HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS;
+	else
+		val = HDMI_VID_PREAMBLE_EN | HDMI_GUARD_BAND_EN;
+	hdmi_write(hdev, HDMI_CON_2, val);
+}
+
+void hdmi_timing_apply(struct hdmi_device *hdev,
+	const struct hdmi_preset_conf *conf)
+{
+	const struct hdmi_core_regs *core = &conf->core;
+	const struct hdmi_tg_regs *tg = &conf->tg;
+
+	/* setting core registers */
+	hdmi_writeb(hdev, HDMI_H_BLANK_0, core->h_blank[0]);
+	hdmi_writeb(hdev, HDMI_H_BLANK_1, core->h_blank[1]);
+	hdmi_writeb(hdev, HDMI_V2_BLANK_0, core->v2_blank[0]);
+	hdmi_writeb(hdev, HDMI_V2_BLANK_1, core->v2_blank[1]);
+	hdmi_writeb(hdev, HDMI_V1_BLANK_0, core->v1_blank[0]);
+	hdmi_writeb(hdev, HDMI_V1_BLANK_1, core->v1_blank[1]);
+	hdmi_writeb(hdev, HDMI_V_LINE_0, core->v_line[0]);
+	hdmi_writeb(hdev, HDMI_V_LINE_1, core->v_line[1]);
+	hdmi_writeb(hdev, HDMI_H_LINE_0, core->h_line[0]);
+	hdmi_writeb(hdev, HDMI_H_LINE_1, core->h_line[1]);
+	hdmi_writeb(hdev, HDMI_HSYNC_POL, core->hsync_pol[0]);
+	hdmi_writeb(hdev, HDMI_VSYNC_POL, core->vsync_pol[0]);
+	hdmi_writeb(hdev, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
+	hdmi_writeb(hdev, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_2_0, core->v_sync_line_bef_2[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_2_1, core->v_sync_line_bef_2[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_1_0, core->v_sync_line_bef_1[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_1_1, core->v_sync_line_bef_1[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_2_0, core->v_sync_line_aft_2[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_2_1, core->v_sync_line_aft_2[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_1_0, core->v_sync_line_aft_1[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_1_1, core->v_sync_line_aft_1[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_2_0, core->v_sync_line_aft_pxl_2[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_2_1, core->v_sync_line_aft_pxl_2[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_1_0, core->v_sync_line_aft_pxl_1[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_1_1, core->v_sync_line_aft_pxl_1[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
+	hdmi_writeb(hdev, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_3_0, core->v_sync_line_aft_3[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_3_1, core->v_sync_line_aft_3[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_4_0, core->v_sync_line_aft_4[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_4_1, core->v_sync_line_aft_4[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_5_0, core->v_sync_line_aft_5[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_5_1, core->v_sync_line_aft_5[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_6_0, core->v_sync_line_aft_6[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_6_1, core->v_sync_line_aft_6[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_3_0, core->v_sync_line_aft_pxl_3[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_3_1, core->v_sync_line_aft_pxl_3[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_4_0, core->v_sync_line_aft_pxl_4[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_4_1, core->v_sync_line_aft_pxl_4[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_5_0, core->v_sync_line_aft_pxl_5[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_5_1, core->v_sync_line_aft_pxl_5[1]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_6_0, core->v_sync_line_aft_pxl_6[0]);
+	hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_6_1, core->v_sync_line_aft_pxl_6[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
+	hdmi_writeb(hdev, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
+
+	/* Timing generator registers */
+	hdmi_writeb(hdev, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
+	hdmi_writeb(hdev, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
+	hdmi_writeb(hdev, HDMI_TG_HACT_ST_L, tg->hact_st_l);
+	hdmi_writeb(hdev, HDMI_TG_HACT_ST_H, tg->hact_st_h);
+	hdmi_writeb(hdev, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
+	hdmi_writeb(hdev, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
+	hdmi_writeb(hdev, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
+	hdmi_writeb(hdev, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_L, tg->vsync_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_H, tg->vsync_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC2_L, tg->vsync2_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC2_H, tg->vsync2_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST_L, tg->vact_st_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST_H, tg->vact_st_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST3_L, tg->vact_st3_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST3_H, tg->vact_st3_h);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST4_L, tg->vact_st4_l);
+	hdmi_writeb(hdev, HDMI_TG_VACT_ST4_H, tg->vact_st4_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
+	hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
+	hdmi_writeb(hdev, HDMI_TG_3D, tg->tg_3d);
+}
+
+int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
+{
+	struct device *dev = hdmi_dev->dev;
+	const struct hdmi_preset_conf *conf = hdmi_dev->cur_conf;
+	struct v4l2_dv_preset preset;
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	/* configure presets */
+	preset.preset = hdmi_dev->cur_preset;
+	ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
+	if (ret) {
+		dev_err(dev, "failed to set preset (%u)\n", preset.preset);
+		return ret;
+	}
+
+	hdmi_reg_init(hdmi_dev);
+
+	/* setting core registers */
+	hdmi_timing_apply(hdmi_dev, conf);
+
+	return 0;
+}
+
+int is_hdmiphy_ready(struct hdmi_device *hdev)
+{
+	u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
+	if (val & HDMI_PHY_STATUS_READY)
+		return 1;
+
+	return 0;
+}
+
+void hdmi_enable(struct hdmi_device *hdev, int on)
+{
+	if (on)
+		hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
+	else
+		hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
+}
+
+void hdmi_hpd_enable(struct hdmi_device *hdev, int on)
+{
+	/* enable HPD interrupts */
+	hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, HDMI_INTC_EN_GLOBAL |
+			HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
+}
+
+void hdmi_tg_enable(struct hdmi_device *hdev, int on)
+{
+	u32 mask;
+
+	mask = (hdev->cur_conf->mbus_fmt.field == V4L2_FIELD_INTERLACED) ?
+			HDMI_TG_EN | HDMI_FIELD_EN : HDMI_TG_EN;
+
+	if (on)
+		hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, mask);
+	else
+		hdmi_write_mask(hdev, HDMI_TG_CMD, 0, mask);
+}
+
+static u8 hdmi_chksum(struct hdmi_device *hdev, u32 start, u8 len, u32 hdr_sum)
+{
+	int i;
+
+	/* hdr_sum : header0 + header1 + header2
+	 * start : start address of packet byte1
+	 * len : packet bytes - 1 */
+	for (i = 0; i < len; ++i)
+		hdr_sum += hdmi_read(hdev, start + i * 4);
+
+	return (u8)(0x100 - (hdr_sum & 0xff));
+}
+
+void hdmi_reg_stop_vsi(struct hdmi_device *hdev)
+{
+	hdmi_writeb(hdev, HDMI_VSI_CON, HDMI_VSI_CON_DO_NOT_TRANSMIT);
+}
+
+void hdmi_reg_infoframe(struct hdmi_device *hdev,
+		struct hdmi_infoframe *infoframe)
+{
+	struct device *dev = hdev->dev;
+	const struct hdmi_3d_info *info = hdmi_preset2info(hdev->cur_preset);
+	u32 hdr_sum;
+	u8 chksum;
+	dev_dbg(dev, "%s: InfoFrame type = 0x%x\n", __func__, infoframe->type);
+
+	switch (infoframe->type) {
+	case HDMI_PACKET_TYPE_VSI:
+		hdmi_writeb(hdev, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
+		hdmi_writeb(hdev, HDMI_VSI_HEADER0, infoframe->type);
+		hdmi_writeb(hdev, HDMI_VSI_HEADER1, infoframe->ver);
+		/* 0x000C03 : 24-bit IEEE Registration Identifier */
+		hdmi_writeb(hdev, HDMI_VSI_DATA(1), 0x03);
+		hdmi_writeb(hdev, HDMI_VSI_DATA(2), 0x0c);
+		hdmi_writeb(hdev, HDMI_VSI_DATA(3), 0x00);
+		hdmi_writeb(hdev, HDMI_VSI_DATA(4),
+			HDMI_VSI_DATA04_VIDEO_FORMAT(info->is_3d));
+		hdmi_writeb(hdev, HDMI_VSI_DATA(5),
+			HDMI_VSI_DATA05_3D_STRUCTURE(info->fmt_3d));
+		if (info->fmt_3d == HDMI_3D_FORMAT_SB_HALF) {
+			infoframe->len += 1;
+			hdmi_writeb(hdev, HDMI_VSI_DATA(6),
+			(u8)HDMI_VSI_DATA06_3D_EXT_DATA(HDMI_H_SUB_SAMPLE));
+		}
+		hdmi_writeb(hdev, HDMI_VSI_HEADER2, infoframe->len);
+		hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
+		chksum = hdmi_chksum(hdev, HDMI_VSI_DATA(1), infoframe->len, hdr_sum);
+		dev_dbg(dev, "VSI checksum = 0x%x\n", chksum);
+		hdmi_writeb(hdev, HDMI_VSI_DATA(0), chksum);
+		break;
+	case HDMI_PACKET_TYPE_AVI:
+		hdmi_writeb(hdev, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
+		hdmi_writeb(hdev, HDMI_AVI_HEADER0, infoframe->type);
+		hdmi_writeb(hdev, HDMI_AVI_HEADER1, infoframe->ver);
+		hdmi_writeb(hdev, HDMI_AVI_HEADER2, infoframe->len);
+		hdmi_writeb(hdev, HDMI_AVI_BYTE(1), hdev->output_fmt << 5);
+		hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
+		chksum = hdmi_chksum(hdev, HDMI_AVI_BYTE(1), infoframe->len, hdr_sum);
+		dev_dbg(dev, "AVI checksum = 0x%x\n", chksum);
+		hdmi_writeb(hdev, HDMI_AVI_CHECK_SUM, chksum);
+		break;
+	default:
+		break;
+	}
+}
+
+void hdmi_reg_set_acr(struct hdmi_device *hdev)
+{
+	u32 n, cts;
+	int sample_rate = hdev->sample_rate;
+
+	if (sample_rate == 32000) {
+		n = 4096;
+		cts = 27000;
+	} else if (sample_rate == 44100) {
+		n = 6272;
+		cts = 30000;
+	} else if (sample_rate == 48000) {
+		n = 6144;
+		cts = 27000;
+	} else if (sample_rate == 88200) {
+		n = 12544;
+		cts = 30000;
+	} else if (sample_rate == 96000) {
+		n = 12288;
+		cts = 27000;
+	} else if (sample_rate == 176400) {
+		n = 25088;
+		cts = 30000;
+	} else if (sample_rate == 192000) {
+		n = 24576;
+		cts = 27000;
+	} else {
+		n = 0;
+		cts = 0;
+	}
+
+	hdmi_write(hdev, HDMI_ACR_N0, HDMI_ACR_N0_VAL(n));
+	hdmi_write(hdev, HDMI_ACR_N1, HDMI_ACR_N1_VAL(n));
+	hdmi_write(hdev, HDMI_ACR_N2, HDMI_ACR_N2_VAL(n));
+
+	/* transfer ACR packet */
+	hdmi_write(hdev, HDMI_ACR_CON, HDMI_ACR_CON_TX_MODE_MESURED_CTS);
+}
+
+void hdmi_reg_spdif_audio_init(struct hdmi_device *hdev)
+{
+	u32 val;
+	int bps, rep_time;
+
+	hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_ENABLE);
+
+	val = HDMI_SPDIFIN_CFG_NOISE_FILTER_2_SAMPLE |
+		HDMI_SPDIFIN_CFG_PCPD_MANUAL |
+		HDMI_SPDIFIN_CFG_WORD_LENGTH_MANUAL |
+		HDMI_SPDIFIN_CFG_UVCP_REPORT |
+		HDMI_SPDIFIN_CFG_HDMI_2_BURST |
+		HDMI_SPDIFIN_CFG_DATA_ALIGN_32;
+	hdmi_write(hdev, HDMI_SPDIFIN_CONFIG_1, val);
+	hdmi_write(hdev, HDMI_SPDIFIN_CONFIG_2, 0);
+
+	bps = hdev->audio_codec == HDMI_AUDIO_PCM ? hdev->bits_per_sample : 16;
+	rep_time = hdev->audio_codec == HDMI_AUDIO_AC3 ? 1536 * 2 - 1 : 0;
+	val = HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_LOW(rep_time) |
+		HDMI_SPDIFIN_USER_VAL_WORD_LENGTH_24;
+	hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_1, val);
+	val = HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_HIGH(rep_time);
+	hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_2, val);
+	hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_3, 0);
+	hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_4, 0);
+
+	val = HDMI_I2S_IN_ENABLE | HDMI_I2S_AUD_SPDIF | HDMI_I2S_MUX_ENABLE;
+	hdmi_write(hdev, HDMI_I2S_IN_MUX_CON, val);
+
+	hdmi_write(hdev, HDMI_I2S_MUX_CH, HDMI_I2S_CH_ALL_EN);
+	hdmi_write(hdev, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
+
+	hdmi_write_mask(hdev, HDMI_SPDIFIN_CLK_CTRL, 0, HDMI_SPDIFIN_CLK_ON);
+	hdmi_write_mask(hdev, HDMI_SPDIFIN_CLK_CTRL, ~0, HDMI_SPDIFIN_CLK_ON);
+
+	hdmi_write(hdev, HDMI_SPDIFIN_OP_CTRL, HDMI_SPDIFIN_STATUS_CHECK_MODE);
+	hdmi_write(hdev, HDMI_SPDIFIN_OP_CTRL,
+			HDMI_SPDIFIN_STATUS_CHECK_MODE_HDMI);
+}
+
+void hdmi_reg_i2s_audio_init(struct hdmi_device *hdev)
+{
+	u32 data_num, bit_ch, sample_frq, val;
+	int sample_rate = hdev->sample_rate;
+	int bits_per_sample = hdev->bits_per_sample;
+
+	if (bits_per_sample == 16) {
+		data_num = 1;
+		bit_ch = 0;
+	} else if (bits_per_sample == 20) {
+		data_num = 2;
+		bit_ch  = 1;
+	} else if (bits_per_sample == 24) {
+		data_num = 3;
+		bit_ch  = 1;
+	} else if (bits_per_sample == 32) {
+		data_num = 1;
+		bit_ch  = 2;
+	} else {
+		data_num = 1;
+		bit_ch = 0;
+	}
+
+	/* reset I2S */
+	hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DISABLE);
+	hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_ENABLE);
+
+	hdmi_write_mask(hdev, HDMI_I2S_DSD_CON, 0, HDMI_I2S_DSD_ENABLE);
+
+	/* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
+	val = HDMI_I2S_SEL_SCLK(5) | HDMI_I2S_SEL_LRCK(6);
+	hdmi_write(hdev, HDMI_I2S_PIN_SEL_0, val);
+	val = HDMI_I2S_SEL_SDATA1(3) | HDMI_I2S_SEL_SDATA0(4);
+	hdmi_write(hdev, HDMI_I2S_PIN_SEL_1, val);
+	val = HDMI_I2S_SEL_SDATA3(1) | HDMI_I2S_SEL_SDATA2(2);
+	hdmi_write(hdev, HDMI_I2S_PIN_SEL_2, val);
+	hdmi_write(hdev, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
+
+	/* I2S_CON_1 & 2 */
+	val = HDMI_I2S_SCLK_FALLING_EDGE | HDMI_I2S_L_CH_LOW_POL;
+	hdmi_write(hdev, HDMI_I2S_CON_1, val);
+	val = HDMI_I2S_MSB_FIRST_MODE | HDMI_I2S_SET_BIT_CH(bit_ch) |
+		HDMI_I2S_SET_SDATA_BIT(data_num) | HDMI_I2S_BASIC_FORMAT;
+	hdmi_write(hdev, HDMI_I2S_CON_2, val);
+
+	if (sample_rate == 32000)
+		sample_frq = 0x3;
+	else if (sample_rate == 44100)
+		sample_frq = 0x0;
+	else if (sample_rate == 48000)
+		sample_frq = 0x2;
+	else if (sample_rate == 96000)
+		sample_frq = 0xa;
+	else
+		sample_frq = 0;
+
+	/* Configure register related to CUV information */
+	val = HDMI_I2S_CH_STATUS_MODE_0 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH |
+		HDMI_I2S_COPYRIGHT | HDMI_I2S_LINEAR_PCM |
+		HDMI_I2S_CONSUMER_FORMAT;
+	hdmi_write(hdev, HDMI_I2S_CH_ST_0, val);
+	hdmi_write(hdev, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
+	hdmi_write(hdev, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
+	val = HDMI_I2S_CLK_ACCUR_LEVEL_1 |
+		HDMI_I2S_SET_SAMPLING_FREQ(sample_frq);
+	hdmi_write(hdev, HDMI_I2S_CH_ST_3, val);
+	val = HDMI_I2S_ORG_SAMPLING_FREQ_44_1 |
+		HDMI_I2S_WORD_LENGTH_MAX24_20BITS |
+		HDMI_I2S_WORD_LENGTH_MAX_20BITS;
+	hdmi_write(hdev, HDMI_I2S_CH_ST_4, val);
+
+	hdmi_write(hdev, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
+
+	val = HDMI_I2S_IN_ENABLE | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
+		| HDMI_I2S_MUX_ENABLE;
+	hdmi_write(hdev, HDMI_I2S_IN_MUX_CON, val);
+
+	val = HDMI_I2S_CH0_L_EN | HDMI_I2S_CH0_R_EN | HDMI_I2S_CH1_L_EN |
+		HDMI_I2S_CH1_R_EN | HDMI_I2S_CH2_L_EN | HDMI_I2S_CH2_R_EN |
+		HDMI_I2S_CH3_L_EN | HDMI_I2S_CH3_R_EN;
+	hdmi_write(hdev, HDMI_I2S_MUX_CH, val);
+
+	val = HDMI_I2S_CUV_L_EN | HDMI_I2S_CUV_R_EN;
+	hdmi_write(hdev, HDMI_I2S_MUX_CUV, val);
+}
+
+void hdmi_audio_enable(struct hdmi_device *hdev, int on)
+{
+	if (on) {
+		hdmi_write(hdev, HDMI_AUI_CON, HDMI_AUI_CON_TRANS_EVERY_VSYNC);
+		hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_ASP_ENABLE);
+	} else {
+		hdmi_write(hdev, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
+		hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_ASP_ENABLE);
+	}
+}
+
+void hdmi_bluescreen_enable(struct hdmi_device *hdev, int on)
+{
+	if (on)
+		hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
+	else
+		hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
+}
+
+void hdmi_reg_mute(struct hdmi_device *hdev, int on)
+{
+	hdmi_bluescreen_enable(hdev, on);
+	hdmi_audio_enable(hdev, !on);
+}
+
+int hdmi_hpd_status(struct hdmi_device *hdev)
+{
+	return hdmi_read(hdev, HDMI_HPD_STATUS);
+}
+
+int is_hdmi_streaming(struct hdmi_device *hdev)
+{
+	if (hdmi_hpd_status(hdev) && hdev->streaming)
+		return 1;
+	return 0;
+}
+
+u8 hdmi_get_int_mask(struct hdmi_device *hdev)
+{
+	return hdmi_readb(hdev, HDMI_INTC_CON_0);
+}
+
+void hdmi_set_int_mask(struct hdmi_device *hdev, u8 mask, int en)
+{
+	if (en) {
+		mask |= HDMI_INTC_EN_GLOBAL;
+		hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, mask);
+	} else
+		hdmi_write_mask(hdev, HDMI_INTC_CON_0, 0,
+				HDMI_INTC_EN_GLOBAL);
+}
+
+void hdmi_sw_hpd_enable(struct hdmi_device *hdev, int en)
+{
+	if (en)
+		hdmi_write_mask(hdev, HDMI_HPD, ~0, HDMI_HPD_SEL_I_HPD);
+	else
+		hdmi_write_mask(hdev, HDMI_HPD, 0, HDMI_HPD_SEL_I_HPD);
+}
+
+void hdmi_sw_hpd_plug(struct hdmi_device *hdev, int en)
+{
+	if (en)
+		hdmi_write_mask(hdev, HDMI_HPD, ~0, HDMI_SW_HPD_PLUGGED);
+	else
+		hdmi_write_mask(hdev, HDMI_HPD, 0, HDMI_SW_HPD_PLUGGED);
+}
+
+void hdmi_phy_sw_reset(struct hdmi_device *hdev)
+{
+	hdmi_write_mask(hdev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
+	mdelay(10);
+	hdmi_write_mask(hdev, HDMI_PHY_RSTOUT,  0, HDMI_PHY_SW_RSTOUT);
+}
+
+void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
+{
+#define DUMPREG(reg_id) \
+	dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
+		readl(hdev->regs + reg_id))
+
+	int i;
+
+	dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_INTC_CON_0);
+	DUMPREG(HDMI_INTC_FLAG_0);
+	DUMPREG(HDMI_HPD_STATUS);
+	DUMPREG(HDMI_INTC_CON_1);
+	DUMPREG(HDMI_INTC_FLAG_1);
+	DUMPREG(HDMI_PHY_STATUS_0);
+	DUMPREG(HDMI_PHY_STATUS_PLL);
+	DUMPREG(HDMI_PHY_CON_0);
+	DUMPREG(HDMI_PHY_RSTOUT);
+	DUMPREG(HDMI_PHY_VPLL);
+	DUMPREG(HDMI_PHY_CMU);
+	DUMPREG(HDMI_CORE_RSTOUT);
+
+	dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_CON_0);
+	DUMPREG(HDMI_CON_1);
+	DUMPREG(HDMI_CON_2);
+	DUMPREG(HDMI_STATUS);
+	DUMPREG(HDMI_PHY_STATUS);
+	DUMPREG(HDMI_STATUS_EN);
+	DUMPREG(HDMI_HPD);
+	DUMPREG(HDMI_MODE_SEL);
+	DUMPREG(HDMI_ENC_EN);
+	DUMPREG(HDMI_DC_CONTROL);
+	DUMPREG(HDMI_VIDEO_PATTERN_GEN);
+
+	dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_H_BLANK_0);
+	DUMPREG(HDMI_H_BLANK_1);
+	DUMPREG(HDMI_V2_BLANK_0);
+	DUMPREG(HDMI_V2_BLANK_1);
+	DUMPREG(HDMI_V1_BLANK_0);
+	DUMPREG(HDMI_V1_BLANK_1);
+	DUMPREG(HDMI_V_LINE_0);
+	DUMPREG(HDMI_V_LINE_1);
+	DUMPREG(HDMI_H_LINE_0);
+	DUMPREG(HDMI_H_LINE_1);
+	DUMPREG(HDMI_HSYNC_POL);
+
+	DUMPREG(HDMI_VSYNC_POL);
+	DUMPREG(HDMI_INT_PRO_MODE);
+	DUMPREG(HDMI_V_BLANK_F0_0);
+	DUMPREG(HDMI_V_BLANK_F0_1);
+	DUMPREG(HDMI_V_BLANK_F1_0);
+	DUMPREG(HDMI_V_BLANK_F1_1);
+
+	DUMPREG(HDMI_H_SYNC_START_0);
+	DUMPREG(HDMI_H_SYNC_START_1);
+	DUMPREG(HDMI_H_SYNC_END_0);
+	DUMPREG(HDMI_H_SYNC_END_1);
+
+	DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
+	DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
+	DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
+	DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
+
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
+
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
+
+	DUMPREG(HDMI_V_BLANK_F2_0);
+	DUMPREG(HDMI_V_BLANK_F2_1);
+	DUMPREG(HDMI_V_BLANK_F3_0);
+	DUMPREG(HDMI_V_BLANK_F3_1);
+	DUMPREG(HDMI_V_BLANK_F4_0);
+	DUMPREG(HDMI_V_BLANK_F4_1);
+	DUMPREG(HDMI_V_BLANK_F5_0);
+	DUMPREG(HDMI_V_BLANK_F5_1);
+
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
+
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
+	DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
+
+	DUMPREG(HDMI_VACT_SPACE_1_0);
+	DUMPREG(HDMI_VACT_SPACE_1_1);
+	DUMPREG(HDMI_VACT_SPACE_2_0);
+	DUMPREG(HDMI_VACT_SPACE_2_1);
+	DUMPREG(HDMI_VACT_SPACE_3_0);
+	DUMPREG(HDMI_VACT_SPACE_3_1);
+	DUMPREG(HDMI_VACT_SPACE_4_0);
+	DUMPREG(HDMI_VACT_SPACE_4_1);
+	DUMPREG(HDMI_VACT_SPACE_5_0);
+	DUMPREG(HDMI_VACT_SPACE_5_1);
+	DUMPREG(HDMI_VACT_SPACE_6_0);
+	DUMPREG(HDMI_VACT_SPACE_6_1);
+
+	dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_TG_CMD);
+	DUMPREG(HDMI_TG_H_FSZ_L);
+	DUMPREG(HDMI_TG_H_FSZ_H);
+	DUMPREG(HDMI_TG_HACT_ST_L);
+	DUMPREG(HDMI_TG_HACT_ST_H);
+	DUMPREG(HDMI_TG_HACT_SZ_L);
+	DUMPREG(HDMI_TG_HACT_SZ_H);
+	DUMPREG(HDMI_TG_V_FSZ_L);
+	DUMPREG(HDMI_TG_V_FSZ_H);
+	DUMPREG(HDMI_TG_VSYNC_L);
+	DUMPREG(HDMI_TG_VSYNC_H);
+	DUMPREG(HDMI_TG_VSYNC2_L);
+	DUMPREG(HDMI_TG_VSYNC2_H);
+	DUMPREG(HDMI_TG_VACT_ST_L);
+	DUMPREG(HDMI_TG_VACT_ST_H);
+	DUMPREG(HDMI_TG_VACT_SZ_L);
+	DUMPREG(HDMI_TG_VACT_SZ_H);
+	DUMPREG(HDMI_TG_FIELD_CHG_L);
+	DUMPREG(HDMI_TG_FIELD_CHG_H);
+	DUMPREG(HDMI_TG_VACT_ST2_L);
+	DUMPREG(HDMI_TG_VACT_ST2_H);
+	DUMPREG(HDMI_TG_VACT_ST3_L);
+	DUMPREG(HDMI_TG_VACT_ST3_H);
+	DUMPREG(HDMI_TG_VACT_ST4_L);
+	DUMPREG(HDMI_TG_VACT_ST4_H);
+	DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
+	DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
+	DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
+	DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
+	DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
+	DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
+	DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
+	DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
+	DUMPREG(HDMI_TG_3D);
+
+	dev_dbg(hdev->dev, "%s: ---- PACKET REGISTERS ----\n", prefix);
+	DUMPREG(HDMI_AVI_CON);
+	DUMPREG(HDMI_AVI_HEADER0);
+	DUMPREG(HDMI_AVI_HEADER1);
+	DUMPREG(HDMI_AVI_HEADER2);
+	DUMPREG(HDMI_AVI_CHECK_SUM);
+	DUMPREG(HDMI_AVI_BYTE(1));
+
+	DUMPREG(HDMI_VSI_CON);
+	DUMPREG(HDMI_VSI_HEADER0);
+	DUMPREG(HDMI_VSI_HEADER1);
+	DUMPREG(HDMI_VSI_HEADER2);
+	for (i = 0; i < 7; ++i)
+		DUMPREG(HDMI_VSI_DATA(i));
+
+#undef DUMPREG
+}
diff --git a/drivers/media/video/exynos/tv/hdmiphy_conf_4210.c b/drivers/media/video/exynos/tv/hdmiphy_conf_4210.c
new file mode 100644
index 0000000..67033c5
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmiphy_conf_4210.c
@@ -0,0 +1,53 @@
+/*
+ * Samsung HDMI Physical interface driver
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ * Author: Jiun Yu <jiun.yu@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include "hdmi.h"
+
+static const u8 hdmiphy_conf27[32] = {
+	0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+	0x6B, 0x10, 0x02, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+	0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+	0x22, 0x40, 0xe3, 0x26, 0x00, 0x00, 0x00, 0x80,
+};
+
+static const u8 hdmiphy_conf74_175[32] = {
+	0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
+	0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
+	0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+	0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
+};
+
+static const u8 hdmiphy_conf74_25[32] = {
+	0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
+	0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
+	0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
+	0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
+};
+
+static const u8 hdmiphy_conf148_5[32] = {
+	0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
+	0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
+	0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+	0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
+};
+
+const struct hdmiphy_conf hdmiphy_conf[] = {
+	{ V4L2_DV_480P59_94, hdmiphy_conf27 },
+	{ V4L2_DV_1080P30, hdmiphy_conf74_175 },
+	{ V4L2_DV_720P59_94, hdmiphy_conf74_175 },
+	{ V4L2_DV_720P60, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P50, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P60, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080I60, hdmiphy_conf74_25 },
+};
+
+const int hdmiphy_conf_cnt = ARRAY_SIZE(hdmiphy_conf);
diff --git a/drivers/media/video/exynos/tv/hdmiphy_conf_5250.c b/drivers/media/video/exynos/tv/hdmiphy_conf_5250.c
new file mode 100644
index 0000000..5cc0643
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmiphy_conf_5250.c
@@ -0,0 +1,94 @@
+/*
+ * Samsung HDMI Physical interface driver
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ * Author: Jiun Yu <jiun.yu@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include "hdmi.h"
+
+static const u8 hdmiphy_conf27[32] = {
+	0x01, 0x51, 0x2d, 0x75, 0x40, 0x01, 0x00, 0x08,
+	0x82, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+	0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+};
+
+static const u8 hdmiphy_conf27_027[32] = {
+	0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
+	0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+	0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+};
+
+static const u8 hdmiphy_conf74_175[32] = {
+	0x01, 0xd1, 0x1f, 0x10, 0x40, 0x5b, 0xef, 0x08,
+	0x81, 0xa0, 0xb9, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+	0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+};
+
+static const u8 hdmiphy_conf74_25[32] = {
+	0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
+	0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+	0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+};
+
+static const u8 hdmiphy_conf148_352[32] = {
+	0x01, 0xd2, 0x3e, 0x00, 0x40, 0x5b, 0xef, 0x08,
+	0x81, 0xa0, 0xb9, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+	0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+};
+
+static const u8 hdmiphy_conf148_5[32] = {
+	0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
+	0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+	0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+	0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+};
+
+const struct hdmiphy_conf hdmiphy_conf[] = {
+	{ V4L2_DV_480P59_94, hdmiphy_conf27 },
+	{ V4L2_DV_480P60, hdmiphy_conf27_027 },
+	{ V4L2_DV_576P50, hdmiphy_conf27 },
+	{ V4L2_DV_720P50, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P59_94, hdmiphy_conf74_175 },
+	{ V4L2_DV_720P60, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080I50, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080I59_94, hdmiphy_conf74_175 },
+	{ V4L2_DV_1080I60, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P24, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P25, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P30, hdmiphy_conf74_175 },
+	{ V4L2_DV_1080P50, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P59_94, hdmiphy_conf148_352 },
+	{ V4L2_DV_1080P60, hdmiphy_conf148_5 },
+	{ V4L2_DV_720P60_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P60_TB, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P59_94_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P59_94_TB, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P50_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_720P50_TB, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P24_FP, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P24_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P24_TB, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P23_98_FP, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P23_98_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P23_98_TB, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080I60_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080I59_94_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080I50_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P60_SB_HALF, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P60_TB, hdmiphy_conf148_5 },
+	{ V4L2_DV_1080P30_SB_HALF, hdmiphy_conf74_25 },
+	{ V4L2_DV_1080P30_TB, hdmiphy_conf74_25 },
+};
+
+const int hdmiphy_conf_cnt = ARRAY_SIZE(hdmiphy_conf);
diff --git a/drivers/media/video/exynos/tv/hdmiphy_drv.c b/drivers/media/video/exynos/tv/hdmiphy_drv.c
new file mode 100644
index 0000000..8cbb442
--- /dev/null
+++ b/drivers/media/video/exynos/tv/hdmiphy_drv.c
@@ -0,0 +1,260 @@
+/*
+ * Samsung HDMI Physical interface driver
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ * Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include "hdmi.h"
+
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+
+#include <media/v4l2-subdev.h>
+
+MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
+MODULE_DESCRIPTION("Samsung HDMI Physical interface driver");
+MODULE_LICENSE("GPL");
+
+#ifdef DEBUG
+static void hdmiphy_print_reg(u8 *recv_buffer)
+{
+	int i;
+
+	for (i = 1; i <= 32; i++) {
+		printk("[%2x]", recv_buffer[i - 1]);
+		if (!(i % 8) && i)
+			printk("\n");
+	}
+	printk("\n");
+}
+#endif
+
+const u8 *hdmiphy_preset2conf(u32 preset)
+{
+	int i;
+	for (i = 0; i < hdmiphy_conf_cnt; ++i)
+		if (hdmiphy_conf[i].preset == preset)
+			return hdmiphy_conf[i].data;
+	return NULL;
+}
+
+static int hdmiphy_ctrl(struct i2c_client *client, u8 reg, u8 bit,
+		u8 *recv_buffer, int en)
+{
+	int ret;
+	u8 buffer[2];
+	struct device *dev = &client->dev;
+
+	buffer[0] = reg;
+	buffer[1] = en ? (recv_buffer[reg] & (~(1 << bit))) :
+			(recv_buffer[reg] | (1 << bit));
+	recv_buffer[reg] = buffer[1];
+
+	ret = i2c_master_send(client, buffer, 2);
+	if (ret != 2) {
+		dev_err(dev, "failed to turn %s HDMIPHY via I2C\n",
+				en ? "on" : "off");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int hdmiphy_enable_oscpad(struct i2c_client *client, int on,
+		u8 *recv_buffer)
+{
+	int ret;
+	u8 buffer[2];
+	struct device *dev = &client->dev;
+
+	buffer[0] = 0x0b;
+	if (on)
+		buffer[1] = 0xd8;
+	else
+		buffer[1] = 0x18;
+	recv_buffer[0x0b] = buffer[1];
+
+	ret = i2c_master_send(client, buffer, 2);
+	if (ret != 2) {
+		dev_err(dev, "failed to %s osc pad\n",
+				on ? "enable" : "disable");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int hdmiphy_s_power(struct v4l2_subdev *sd, int on)
+{
+	u8 recv_buffer[32];
+	u8 buffer[2];
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *dev = &client->dev;
+
+	memset(recv_buffer, 0, sizeof(recv_buffer));
+
+	dev_dbg(dev, "%s: hdmiphy is %s\n", __func__, on ? "on" : "off");
+
+	buffer[0] = 0x1;
+	i2c_master_send(client, buffer, 1);
+	i2c_master_recv(client, recv_buffer, 32);
+
+#ifdef DEBUG
+	hdmiphy_print_reg(recv_buffer);
+#endif
+
+	if (!on)
+		hdmiphy_enable_oscpad(client, 0, recv_buffer);
+
+	hdmiphy_ctrl(client, 0x1d, 0x7, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x0, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x1, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x2, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x4, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x5, recv_buffer, on);
+	hdmiphy_ctrl(client, 0x1d, 0x6, recv_buffer, on);
+
+	if (!on)
+		hdmiphy_ctrl(client, 0x4, 0x3, recv_buffer, 0);
+
+#ifdef DEBUG
+	buffer[0] = 0x1;
+	i2c_master_send(client, buffer, 1);
+	i2c_master_recv(client, recv_buffer, 32);
+
+	hdmiphy_print_reg(recv_buffer);
+#endif
+	return 0;
+}
+
+static int hdmiphy_s_dv_preset(struct v4l2_subdev *sd,
+	struct v4l2_dv_preset *preset)
+{
+	const u8 *data;
+	u8 buffer[32];
+	u8 recv_buffer[32];
+	int ret;
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *dev = &client->dev;
+
+	dev_dbg(dev, "s_dv_preset(preset = %d)\n", preset->preset);
+	data = hdmiphy_preset2conf(preset->preset);
+	if (!data) {
+		dev_err(dev, "format not supported\n");
+		return -EINVAL;
+	}
+
+	memset(recv_buffer, 0, 32);
+
+#ifdef DEBUG
+	i2c_master_recv(client, recv_buffer, 32);
+	hdmiphy_print_reg(recv_buffer);
+#endif
+
+	/* storing configuration to the device */
+	memcpy(buffer, data, 32);
+	ret = i2c_master_send(client, buffer, 32);
+	if (ret != 32) {
+		dev_err(dev, "failed to configure HDMIPHY via I2C\n");
+		return -EIO;
+	}
+
+#ifdef DEBUG
+	i2c_master_recv(client, recv_buffer, 32);
+	hdmiphy_print_reg(recv_buffer);
+#endif
+
+	return 0;
+}
+
+static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *dev = &client->dev;
+	u8 buffer[2];
+	int ret;
+
+	dev_dbg(dev, "s_stream(%d)\n", enable);
+	/* going to/from configuration from/to operation mode */
+	buffer[0] = 0x1f;
+	buffer[1] = enable ? 0x80 : 0x00;
+
+	ret = i2c_master_send(client, buffer, 2);
+	if (ret != 2) {
+		dev_err(dev, "stream (%d) failed\n", enable);
+		return -EIO;
+	}
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops hdmiphy_core_ops = {
+	.s_power =  hdmiphy_s_power,
+};
+
+static const struct v4l2_subdev_video_ops hdmiphy_video_ops = {
+	.s_dv_preset = hdmiphy_s_dv_preset,
+	.s_stream =  hdmiphy_s_stream,
+};
+
+static const struct v4l2_subdev_ops hdmiphy_ops = {
+	.core = &hdmiphy_core_ops,
+	.video = &hdmiphy_video_ops,
+};
+
+static int __devinit hdmiphy_probe(struct i2c_client *client,
+	const struct i2c_device_id *id)
+{
+	static struct v4l2_subdev sd;
+
+	printk("hdmiphy_probe start\n");
+
+	v4l2_i2c_subdev_init(&sd, client, &hdmiphy_ops);
+	dev_info(&client->dev, "probe successful\n");
+	return 0;
+}
+
+static int __devexit hdmiphy_remove(struct i2c_client *client)
+{
+	dev_info(&client->dev, "remove successful\n");
+	return 0;
+}
+
+static const struct i2c_device_id hdmiphy_id[] = {
+	{ "hdmiphy", 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, hdmiphy_id);
+
+static struct i2c_driver hdmiphy_driver = {
+	.driver = {
+		.name	= "s5p-hdmiphy",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= hdmiphy_probe,
+	.remove		= __devexit_p(hdmiphy_remove),
+	.id_table = hdmiphy_id,
+};
+
+static int __init hdmiphy_init(void)
+{
+	printk("hdmiphy init start\n");
+	return i2c_add_driver(&hdmiphy_driver);
+}
+module_init(hdmiphy_init);
+
+static void __exit hdmiphy_exit(void)
+{
+	i2c_del_driver(&hdmiphy_driver);
+}
+module_exit(hdmiphy_exit);
diff --git a/drivers/media/video/exynos/tv/mixer.h b/drivers/media/video/exynos/tv/mixer.h
new file mode 100644
index 0000000..0a17942
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer.h
@@ -0,0 +1,544 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#ifndef SAMSUNG_MIXER_H
+#define SAMSUNG_MIXER_H
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIXER_DEBUG
+	#define DEBUG
+#endif
+
+#include <linux/fb.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <media/v4l2-device.h>
+#include <media/videobuf2-core.h>
+#include <media/exynos_mc.h>
+
+#include "regs-mixer.h"
+
+#define INT_LOCK_TV 267200
+
+/** maximum number of output interfaces */
+#define MXR_MAX_OUTPUTS 2
+
+/** There are 2 mixers after EXYNOS5250 */
+#define MXR_SUB_MIXER0		0
+#define MXR_SUB_MIXER1		1
+/** maximum number of sub-mixers */
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define MXR_MAX_SUB_MIXERS	1
+#else
+#define MXR_MAX_SUB_MIXERS	2
+#endif
+
+/** each sub-mixer supports 1 video layer and 2 graphic layers */
+#define MXR_LAYER_VIDEO		0
+#define MXR_LAYER_GRP0		1
+#define MXR_LAYER_GRP1		2
+
+/** maximum number of input interfaces (layers) */
+#define MXR_MAX_LAYERS 3
+#define MXR_DRIVER_NAME "s5p-mixer"
+/** maximal number of planes for every layer */
+#define MXR_MAX_PLANES	2
+
+#define MXR_ENABLE 1
+#define MXR_DISABLE 0
+
+/* mixer pad definitions */
+#define MXR_PAD_SINK_GSCALER	0
+#define MXR_PAD_SINK_GRP0	1
+#define MXR_PAD_SINK_GRP1	2
+#define MXR_PAD_SOURCE_GSCALER	3
+#define MXR_PAD_SOURCE_GRP0	4
+#define MXR_PAD_SOURCE_GRP1	5
+#define MXR_PADS_NUM		6
+/** description of a macroblock for packed formats */
+struct mxr_block {
+	/** vertical number of pixels in macroblock */
+	unsigned int width;
+	/** horizontal number of pixels in macroblock */
+	unsigned int height;
+	/** size of block in bytes */
+	unsigned int size;
+};
+
+/** description of supported format */
+struct mxr_format {
+	/** format name/mnemonic */
+	const char *name;
+	/** fourcc identifier */
+	u32 fourcc;
+	/** colorspace identifier */
+	enum v4l2_colorspace colorspace;
+	/** number of planes in image data */
+	int num_planes;
+	/** description of block for each plane */
+	struct mxr_block plane[MXR_MAX_PLANES];
+	/** number of subframes in image data */
+	int num_subframes;
+	/** specifies to which subframe belong given plane */
+	int plane2subframe[MXR_MAX_PLANES];
+	/** internal code, driver dependant */
+	unsigned long cookie;
+};
+
+/** description of crop configuration for image */
+struct mxr_crop {
+	/** width of layer in pixels */
+	unsigned int full_width;
+	/** height of layer in pixels */
+	unsigned int full_height;
+	/** horizontal offset of first pixel to be displayed */
+	unsigned int x_offset;
+	/** vertical offset of first pixel to be displayed */
+	unsigned int y_offset;
+	/** width of displayed data in pixels */
+	unsigned int width;
+	/** height of displayed data in pixels */
+	unsigned int height;
+	/** indicate which fields are present in buffer */
+	unsigned int field;
+};
+
+/** description of transformation from source to destination image */
+struct mxr_geometry {
+	/** cropping for source image */
+	struct mxr_crop src;
+	/** cropping for destination image */
+	struct mxr_crop dst;
+	/** layer-dependant description of horizontal scaling */
+	unsigned int x_ratio;
+	/** layer-dependant description of vertical scaling */
+	unsigned int y_ratio;
+};
+
+/** instance of a buffer */
+struct mxr_buffer {
+	/** common v4l buffer stuff -- must be first */
+	struct vb2_buffer	vb;
+	/** node for layer's lists */
+	struct list_head	list;
+};
+
+/** TV graphic layer pipeline state */
+enum mxr_pipeline_state {
+	/** graphic layer is not shown */
+	MXR_PIPELINE_IDLE = 0,
+	/** state between STREAMON and hardware start */
+	MXR_PIPELINE_STREAMING_START,
+	/** graphic layer is shown */
+	MXR_PIPELINE_STREAMING,
+	/** state before STREAMOFF is finished */
+	MXR_PIPELINE_STREAMING_FINISH,
+};
+
+/** TV graphic layer pipeline structure for streaming media data */
+struct mxr_pipeline {
+	struct media_pipeline pipe;
+	enum mxr_pipeline_state state;
+
+	/** starting point on pipeline */
+	struct mxr_layer *layer;
+};
+
+/** forward declarations */
+struct mxr_device;
+struct mxr_layer;
+
+/** callback for layers operation */
+struct mxr_layer_ops {
+	/* TODO: try to port it to subdev API */
+	/** handler for resource release function */
+	void (*release)(struct mxr_layer *);
+	/** setting buffer to HW */
+	void (*buffer_set)(struct mxr_layer *, struct mxr_buffer *);
+	/** setting format and geometry in HW */
+	void (*format_set)(struct mxr_layer *);
+	/** streaming stop/start */
+	void (*stream_set)(struct mxr_layer *, int);
+	/** adjusting geometry */
+	void (*fix_geometry)(struct mxr_layer *);
+};
+
+enum mxr_layer_type {
+	MXR_LAYER_TYPE_VIDEO = 0,
+	MXR_LAYER_TYPE_GRP = 1,
+};
+
+struct mxr_layer_en {
+	int graph0;
+	int graph1;
+	int graph2;
+	int graph3;
+};
+
+/** layer instance, a single window and content displayed on output */
+struct mxr_layer {
+	/** parent mixer device */
+	struct mxr_device *mdev;
+	/** layer index (unique identifier) */
+	int idx;
+	/** layer type */
+	enum mxr_layer_type type;
+	/** minor number of mixer layer as video device */
+	int minor;
+	/** callbacks for layer methods */
+	struct mxr_layer_ops ops;
+	/** format array */
+	const struct mxr_format **fmt_array;
+	/** size of format array */
+	unsigned long fmt_array_size;
+
+	/** lock for protection of list and state fields */
+	spinlock_t enq_slock;
+	/** list for enqueued buffers */
+	struct list_head enq_list;
+	/** buffer currently owned by hardware in temporary registers */
+	struct mxr_buffer *update_buf;
+	/** buffer currently owned by hardware in shadow registers */
+	struct mxr_buffer *shadow_buf;
+
+	/** mutex for protection of fields below */
+	struct mutex mutex;
+	/** handler for video node */
+	struct video_device vfd;
+	/** queue for output buffers */
+	struct vb2_queue vb_queue;
+	/** current image format */
+	const struct mxr_format *fmt;
+	/** current geometry of image */
+	struct mxr_geometry geo;
+
+	/** index of current mixer path : MXR_SUB_MIXERx*/
+	int cur_mxr;
+	/** source pad of mixer input */
+	struct media_pad pad;
+	/** pipeline structure for streaming TV graphic layer */
+	struct mxr_pipeline pipe;
+
+	/** enable per layer blending for each layer */
+	int layer_blend_en;
+	/** alpha value for per layer blending */
+	u32 layer_alpha;
+	/** enable per pixel blending */
+	int pixel_blend_en;
+	/** enable chromakey */
+	int chroma_en;
+	/** value for chromakey */
+	u32 chroma_val;
+	/** priority for each layer */
+	u8 prio;
+};
+
+/** description of mixers output interface */
+struct mxr_output {
+	/** name of output */
+	char name[32];
+	/** output subdev */
+	struct v4l2_subdev *sd;
+	/** cookie used for configuration of registers */
+	int cookie;
+};
+
+/** specify source of output subdevs */
+struct mxr_output_conf {
+	/** name of output (connector) */
+	char *output_name;
+	/** name of module that generates output subdev */
+	char *module_name;
+	/** cookie need for mixer HW */
+	int cookie;
+};
+
+struct clk;
+struct regulator;
+
+/** auxiliary resources used my mixer */
+struct mxr_resources {
+	/** interrupt index */
+	int irq;
+	/** pointer to Mixer registers */
+	void __iomem *mxr_regs;
+#if defined(CONFIG_ARCH_EXYNOS4)
+	/** pointer to Video Processor registers */
+	void __iomem *vp_regs;
+	/** other resources, should used under mxr_device.mutex */
+	struct clk *vp;
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+	struct clk *sclk_dac;
+#endif
+	struct clk *sclk_mixer;
+	struct clk *mixer;
+	struct clk *sclk_hdmi;
+};
+
+/* event flags used  */
+enum mxr_devide_flags {
+	MXR_EVENT_VSYNC = 0,
+};
+
+/** videobuf2 context of mixer */
+struct mxr_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct mxr_device *mdev);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+};
+
+/** sub-mixer 0,1 drivers instance */
+struct sub_mxr_device {
+	/** state of each layer */
+	struct mxr_layer *layer[MXR_MAX_LAYERS];
+
+	/** use of each sub mixer */
+	int use;
+	/** use of local path gscaler to mixer */
+	int local;
+	/** for mixer as sub-device */
+	struct v4l2_subdev sd;
+	/** mixer's pads : 3 sink pad, 3 source pad */
+	struct media_pad pads[MXR_PADS_NUM];
+	/** format info of mixer's pads */
+	struct v4l2_mbus_framefmt mbus_fmt[MXR_PADS_NUM];
+	/** crop info of mixer's pads */
+	struct v4l2_rect crop[MXR_PADS_NUM];
+};
+
+/** drivers instance */
+struct mxr_device {
+	/** master device */
+	struct device *dev;
+	struct device *bus_dev;
+	/** state of each output */
+	struct mxr_output *output[MXR_MAX_OUTPUTS];
+	/** number of registered outputs */
+	int output_cnt;
+
+	/* video resources */
+
+	/** videbuf2 context */
+	const struct mxr_vb2 *vb2;
+	/** context of allocator */
+	void *alloc_ctx;
+	/** event wait queue */
+	wait_queue_head_t event_queue;
+	/** state flags */
+	unsigned long event_flags;
+
+	/** spinlock for protection of registers */
+	spinlock_t reg_slock;
+
+	/** mutex for protection of fields below */
+	struct mutex mutex;
+	/** mutex for protection of streamer */
+	struct mutex s_mutex;
+
+	/** number of entities depndant on output configuration */
+	int n_output;
+	/** number of users that do streaming */
+	int n_streamer;
+	/** index of current output */
+	int current_output;
+	/** auxiliary resources used my mixer */
+	struct mxr_resources res;
+
+	/** number of G-Scaler linked to mixer0 */
+	int mxr0_gsc;
+	/** number of G-Scaler linked to mixer1 */
+	int mxr1_gsc;
+	/** media entity link setup flags */
+	unsigned long flags;
+
+	/** entity info which transfers media data to mixer subdev */
+	enum mxr_data_from mxr_data_from;
+
+	/** count of sub-mixers */
+	struct sub_mxr_device sub_mxr[MXR_MAX_SUB_MIXERS];
+
+	/** enabled layer number **/
+	struct mxr_layer_en layer_en;
+	/** frame packing flag **/
+	int frame_packing;
+};
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct mxr_vb2 mxr_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct mxr_vb2 mxr_vb2_ion;
+#endif
+
+/** transform device structure into mixer device */
+static inline struct mxr_device *to_mdev(struct device *dev)
+{
+	return dev_get_drvdata(dev);
+}
+
+/** transform subdev structure into mixer device */
+static inline struct mxr_device *sd_to_mdev(struct v4l2_subdev *sd)
+{
+	struct sub_mxr_device *sub_mxr =
+		container_of(sd, struct sub_mxr_device, sd);
+	return sub_mxr->layer[MXR_LAYER_GRP0]->mdev;
+}
+
+/** transform subdev structure into sub mixer device */
+static inline struct sub_mxr_device *sd_to_sub_mxr(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct sub_mxr_device, sd);
+}
+
+/** transform entity structure into sub mixer device */
+static inline struct sub_mxr_device *entity_to_sub_mxr(struct media_entity *me)
+{
+	struct v4l2_subdev *sd;
+
+	sd = container_of(me, struct v4l2_subdev, entity);
+	return container_of(sd, struct sub_mxr_device, sd);
+}
+
+/** transform entity structure into sub mixer device */
+static inline struct mxr_device *sub_mxr_to_mdev(struct sub_mxr_device *sub_mxr)
+{
+	int idx;
+
+	if (!strcmp(sub_mxr->sd.name, "s5p-mixer0"))
+		idx = MXR_SUB_MIXER0;
+	else
+		idx = MXR_SUB_MIXER1;
+
+	return container_of(sub_mxr, struct mxr_device, sub_mxr[idx]);
+}
+
+/** get current output data, should be called under mdev's mutex */
+static inline struct mxr_output *to_output(struct mxr_device *mdev)
+{
+	return mdev->output[mdev->current_output];
+}
+
+/** get current output subdev, should be called under mdev's mutex */
+static inline struct v4l2_subdev *to_outsd(struct mxr_device *mdev)
+{
+	struct mxr_output *out = to_output(mdev);
+	return out ? out->sd : NULL;
+}
+
+/** forward declaration for mixer platform data */
+struct mxr_platform_data;
+
+/** acquiring common video resources */
+int __devinit mxr_acquire_video(struct mxr_device *mdev,
+	struct mxr_output_conf *output_cont, int output_count);
+
+/** releasing common video resources */
+void __devexit mxr_release_video(struct mxr_device *mdev);
+
+struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int cur_mxr,
+	int idx, int nr);
+struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int cur_mxr,
+	int idx, int nr);
+struct mxr_layer *mxr_video_layer_create(struct mxr_device *mdev, int cur_mxr,
+	int idx);
+struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev,
+	int idx, char *name, struct mxr_layer_ops *ops);
+
+const struct mxr_format *find_format_by_fourcc(
+	struct mxr_layer *layer, unsigned long fourcc);
+
+void mxr_base_layer_release(struct mxr_layer *layer);
+void mxr_layer_release(struct mxr_layer *layer);
+void mxr_layer_geo_fix(struct mxr_layer *layer);
+void mxr_layer_default_geo(struct mxr_layer *layer);
+
+int mxr_base_layer_register(struct mxr_layer *layer);
+void mxr_base_layer_unregister(struct mxr_layer *layer);
+
+unsigned long mxr_get_plane_size(const struct mxr_block *blk,
+	unsigned int width, unsigned int height);
+
+/** adds new consumer for mixer's power */
+int __must_check mxr_power_get(struct mxr_device *mdev);
+/** removes consumer for mixer's power */
+void mxr_power_put(struct mxr_device *mdev);
+/** add new client for output configuration */
+void mxr_output_get(struct mxr_device *mdev);
+/** removes new client for output configuration */
+void mxr_output_put(struct mxr_device *mdev);
+/** returns format of data delivared to current output */
+void mxr_get_mbus_fmt(struct mxr_device *mdev,
+	struct v4l2_mbus_framefmt *mbus_fmt);
+
+/* Debug */
+
+#define mxr_err(mdev, fmt, ...)  dev_err(mdev->dev, fmt, ##__VA_ARGS__)
+#define mxr_warn(mdev, fmt, ...) dev_warn(mdev->dev, fmt, ##__VA_ARGS__)
+#define mxr_info(mdev, fmt, ...) dev_info(mdev->dev, fmt, ##__VA_ARGS__)
+
+#ifdef CONFIG_VIDEO_EXYNOS_MIXER_DEBUG
+	#define mxr_dbg(mdev, fmt, ...)  dev_dbg(mdev->dev, fmt, ##__VA_ARGS__)
+#else
+	#define mxr_dbg(mdev, fmt, ...)  do { (void) mdev; } while (0)
+#endif
+
+/* accessing Mixer's and Video Processor's registers */
+
+void mxr_layer_sync(struct mxr_device *mdev, int en);
+void mxr_vsync_set_update(struct mxr_device *mdev, int en);
+void mxr_reg_reset(struct mxr_device *mdev);
+void mxr_reg_set_layer_prio(struct mxr_device *mdev);
+void mxr_reg_set_layer_blend(struct mxr_device *mdev, int sub_mxr, int num,
+		int en);
+void mxr_reg_layer_alpha(struct mxr_device *mdev, int sub_mxr, int num, u32 a);
+void mxr_reg_set_pixel_blend(struct mxr_device *mdev, int sub_mxr, int num,
+		int en);
+void mxr_reg_set_colorkey(struct mxr_device *mdev, int sub_mxr, int num, int en);
+void mxr_reg_colorkey_val(struct mxr_device *mdev, int sub_mxr, int num, u32 v);
+irqreturn_t mxr_irq_handler(int irq, void *dev_data);
+void mxr_reg_s_output(struct mxr_device *mdev, int cookie);
+void mxr_reg_streamon(struct mxr_device *mdev);
+void mxr_reg_streamoff(struct mxr_device *mdev);
+int mxr_reg_wait4vsync(struct mxr_device *mdev);
+void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
+	struct v4l2_mbus_framefmt *fmt);
+void mxr_reg_local_path_clear(struct mxr_device *mdev);
+void mxr_reg_local_path_set(struct mxr_device *mdev, int mxr0_gsc, int mxr1_gsc,
+		u32 flags);
+void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en);
+void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr);
+void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
+	const struct mxr_format *fmt, const struct mxr_geometry *geo);
+
+void mxr_reg_video_layer_stream(struct mxr_device *mdev, int idx, int en);
+void mxr_reg_video_geo(struct mxr_device *mdev, int cur_mxr, int idx,
+		const struct mxr_geometry *geo);
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en);
+void mxr_reg_vp_buffer(struct mxr_device *mdev,
+	dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2]);
+void mxr_reg_vp_format(struct mxr_device *mdev,
+	const struct mxr_format *fmt, const struct mxr_geometry *geo);
+#endif
+void mxr_reg_dump(struct mxr_device *mdev);
+
+#endif /* SAMSUNG_MIXER_H */
diff --git a/drivers/media/video/exynos/tv/mixer_drv.c b/drivers/media/video/exynos/tv/mixer_drv.c
new file mode 100644
index 0000000..b7c11d1
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_drv.c
@@ -0,0 +1,1488 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+#include "mixer.h"
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/videodev2_exynos_media.h>
+#include <mach/dev.h>
+
+#include <mach/videonode-exynos5.h>
+#include <media/exynos_mc.h>
+
+MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
+MODULE_DESCRIPTION("Samsung MIXER");
+MODULE_LICENSE("GPL");
+
+/* --------- DRIVER PARAMETERS ---------- */
+
+static struct mxr_output_conf mxr_output_conf[] = {
+	{
+		.output_name = "S5P HDMI connector",
+		.module_name = "s5p-hdmi",
+		.cookie = 1,
+	},
+	{
+		.output_name = "S5P SDO connector",
+		.module_name = "s5p-sdo",
+		.cookie = 0,
+	},
+};
+
+void mxr_get_mbus_fmt(struct mxr_device *mdev,
+	struct v4l2_mbus_framefmt *mbus_fmt)
+{
+	struct v4l2_subdev *sd;
+	int ret;
+
+	mutex_lock(&mdev->mutex);
+	sd = to_outsd(mdev);
+	ret = v4l2_subdev_call(sd, video, g_mbus_fmt, mbus_fmt);
+	WARN(ret, "failed to get mbus_fmt for output %s\n", sd->name);
+	mutex_unlock(&mdev->mutex);
+}
+
+static void mxr_set_alpha_blend(struct mxr_device *mdev)
+{
+	int i, j;
+	int layer_en, pixel_en, chroma_en;
+	u32 a, v;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		for (j = 0; j < MXR_MAX_LAYERS; ++j) {
+			layer_en = mdev->sub_mxr[i].layer[j]->layer_blend_en;
+			a = mdev->sub_mxr[i].layer[j]->layer_alpha;
+			pixel_en = mdev->sub_mxr[i].layer[j]->pixel_blend_en;
+			chroma_en = mdev->sub_mxr[i].layer[j]->chroma_en;
+			v = mdev->sub_mxr[i].layer[j]->chroma_val;
+
+			mxr_dbg(mdev, "mixer%d: layer%d\n", i, j);
+			mxr_dbg(mdev, "layer blend is %s, alpha = %d\n",
+					layer_en ? "enabled" : "disabled", a);
+			mxr_dbg(mdev, "pixel blend is %s\n",
+					pixel_en ? "enabled" : "disabled");
+			mxr_dbg(mdev, "chromakey is %s, value = %d\n",
+					chroma_en ? "enabled" : "disabled", v);
+
+			mxr_reg_set_layer_blend(mdev, i, j, layer_en);
+			mxr_reg_layer_alpha(mdev, i, j, a);
+			mxr_reg_set_pixel_blend(mdev, i, j, pixel_en);
+			mxr_reg_set_colorkey(mdev, i, j, chroma_en);
+			mxr_reg_colorkey_val(mdev, i, j, v);
+		}
+	}
+}
+
+static int mxr_streamer_get(struct mxr_device *mdev, struct v4l2_subdev* sd)
+{
+	int i, ret;
+	int local = 1;
+	struct sub_mxr_device *sub_mxr;
+	struct mxr_layer *layer;
+	struct media_pad *pad;
+	struct v4l2_mbus_framefmt mbus_fmt;
+#if defined(CONFIG_CPU_EXYNOS4210)
+	struct mxr_resources *res = &mdev->res;
+#endif
+
+	mutex_lock(&mdev->s_mutex);
+	++mdev->n_streamer;
+	mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer);
+	/* If pipeline is started from Gscaler input video device,
+	 * TV basic configuration must be set before running mixer */
+
+#if defined(CONFIG_BUSFREQ_OPP)
+	/* add bus device ptr for using bus frequency with opp */
+	mdev->bus_dev = dev_get("exynos-busfreq");
+#endif
+
+	if (mdev->mxr_data_from == FROM_GSC_SD) {
+		mxr_dbg(mdev, "%s: from gscaler\n", __func__);
+		local = 0;
+		/* enable mixer clock */
+		ret = mxr_power_get(mdev);
+		if (ret) {
+			mxr_err(mdev, "power on failed\n");
+			return -ENODEV;
+		}
+		/* turn on connected output device through link
+		 * with mixer */
+		mxr_output_get(mdev);
+
+		for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+			sub_mxr = &mdev->sub_mxr[i];
+			if (sub_mxr->local) {
+				layer = sub_mxr->layer[MXR_LAYER_VIDEO];
+				layer->pipe.state = MXR_PIPELINE_STREAMING;
+				mxr_layer_geo_fix(layer);
+				layer->ops.format_set(layer);
+				layer->ops.stream_set(layer, 1);
+				local += sub_mxr->local;
+			}
+		}
+		if (local == 2)
+			mxr_layer_sync(mdev, MXR_ENABLE);
+
+		/* Set the TVOUT register about gsc-mixer local path */
+		mxr_reg_local_path_set(mdev, mdev->mxr0_gsc, mdev->mxr1_gsc, mdev->flags);
+	}
+
+	/* Alpha blending configuration always can be changed
+	 * whenever streaming */
+	mxr_set_alpha_blend(mdev);
+	mxr_reg_set_layer_prio(mdev);
+
+	if ((mdev->n_streamer == 1 && local == 1) ||
+	    (mdev->n_streamer == 2 && local == 2)) {
+		for (i = MXR_PAD_SOURCE_GSCALER; i < MXR_PADS_NUM; ++i) {
+			pad = &sd->entity.pads[i];
+
+			/* find sink pad of output via enabled link*/
+			pad = media_entity_remote_source(pad);
+			if (pad)
+				if (media_entity_type(pad->entity)
+						== MEDIA_ENT_T_V4L2_SUBDEV)
+					break;
+
+			if (i == MXR_PAD_SOURCE_GRP1)
+				return -ENODEV;
+		}
+
+		sd = media_entity_to_v4l2_subdev(pad->entity);
+
+		mxr_dbg(mdev, "cookie of current output = (%d)\n",
+			to_output(mdev)->cookie);
+
+#if defined(CONFIG_BUSFREQ_OPP)
+		/* Request min 200MHz */
+		dev_lock(mdev->bus_dev, mdev->dev, INT_LOCK_TV);
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210)
+		if (to_output(mdev)->cookie == 0)
+			clk_set_parent(res->sclk_mixer, res->sclk_dac);
+		else
+			clk_set_parent(res->sclk_mixer, res->sclk_hdmi);
+#endif
+		mxr_reg_s_output(mdev, to_output(mdev)->cookie);
+
+		ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mbus_fmt);
+		if (ret) {
+			mxr_err(mdev, "failed to get mbus_fmt for output %s\n",
+					sd->name);
+			return ret;
+		}
+
+		mxr_reg_set_mbus_fmt(mdev, &mbus_fmt);
+		ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mbus_fmt);
+		if (ret) {
+			mxr_err(mdev, "failed to set mbus_fmt for output %s\n",
+					sd->name);
+			return ret;
+		}
+		mxr_reg_streamon(mdev);
+
+		ret = v4l2_subdev_call(sd, video, s_stream, 1);
+		if (ret) {
+			mxr_err(mdev, "starting stream failed for output %s\n",
+					sd->name);
+			return ret;
+		}
+
+		ret = mxr_reg_wait4vsync(mdev);
+		if (ret) {
+			mxr_err(mdev, "failed to get vsync (%d) from output\n",
+					ret);
+			return ret;
+		}
+	}
+
+	mutex_unlock(&mdev->s_mutex);
+	mxr_reg_dump(mdev);
+
+	return 0;
+}
+
+static int mxr_streamer_put(struct mxr_device *mdev, struct v4l2_subdev *sd)
+{
+	int ret, i;
+	int local = 1;
+	struct media_pad *pad;
+	struct sub_mxr_device *sub_mxr;
+	struct mxr_layer *layer;
+	struct v4l2_subdev *hdmi_sd;
+	struct v4l2_subdev *gsc_sd;
+	struct exynos_entity_data *md_data;
+
+	mutex_lock(&mdev->s_mutex);
+	--mdev->n_streamer;
+	mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer);
+
+	/* distinction number of local path */
+	if (mdev->mxr_data_from == FROM_GSC_SD) {
+		local = 0;
+		for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+			sub_mxr = &mdev->sub_mxr[i];
+			if (sub_mxr->local) {
+				local += sub_mxr->local;
+			}
+		}
+		if (local == 2)
+			mxr_layer_sync(mdev, MXR_DISABLE);
+	}
+
+	if ((mdev->n_streamer == 0 && local == 1) ||
+	    (mdev->n_streamer == 1 && local == 2)) {
+		for (i = MXR_PAD_SOURCE_GSCALER; i < MXR_PADS_NUM; ++i) {
+			pad = &sd->entity.pads[i];
+
+			/* find sink pad of output via enabled link*/
+			pad = media_entity_remote_source(pad);
+			if (pad)
+				if (media_entity_type(pad->entity)
+						== MEDIA_ENT_T_V4L2_SUBDEV)
+					break;
+
+			if (i == MXR_PAD_SOURCE_GRP1)
+				return -ENODEV;
+		}
+
+		hdmi_sd = media_entity_to_v4l2_subdev(pad->entity);
+
+		mxr_reg_streamoff(mdev);
+#if defined(CONFIG_BUSFREQ_OPP)
+		dev_unlock(mdev->bus_dev, mdev->dev);
+#endif
+
+		/* vsync applies Mixer setup */
+		ret = mxr_reg_wait4vsync(mdev);
+		if (ret) {
+			mxr_err(mdev, "failed to get vsync (%d) from output\n",
+					ret);
+			return ret;
+		}
+	}
+	/* When using local path between gscaler and mixer, below stop sequence
+	 * must be processed */
+	if (mdev->mxr_data_from == FROM_GSC_SD) {
+		pad = &sd->entity.pads[MXR_PAD_SINK_GSCALER];
+		pad = media_entity_remote_source(pad);
+		if (pad) {
+			gsc_sd = media_entity_to_v4l2_subdev(
+					pad->entity);
+			mxr_dbg(mdev, "stop from %s\n", gsc_sd->name);
+			md_data = (struct exynos_entity_data *)
+				gsc_sd->dev_priv;
+			md_data->media_ops->power_off(gsc_sd);
+		}
+	}
+
+	if ((mdev->n_streamer == 0 && local == 1) ||
+	    (mdev->n_streamer == 1 && local == 2)) {
+		ret = v4l2_subdev_call(hdmi_sd, video, s_stream, 0);
+		if (ret) {
+			mxr_err(mdev, "stopping stream failed for output %s\n",
+					hdmi_sd->name);
+			return ret;
+		}
+	}
+	/* turn off connected output device through link
+	 * with mixer */
+	if (mdev->mxr_data_from == FROM_GSC_SD) {
+		for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+			sub_mxr = &mdev->sub_mxr[i];
+			if (sub_mxr->local) {
+				layer = sub_mxr->layer[MXR_LAYER_VIDEO];
+				layer->ops.stream_set(layer, 0);
+				layer->pipe.state = MXR_PIPELINE_IDLE;
+			}
+		}
+		mxr_reg_local_path_clear(mdev);
+		mxr_output_put(mdev);
+
+		/* disable mixer clock */
+		mxr_power_put(mdev);
+	}
+	WARN(mdev->n_streamer < 0, "negative number of streamers (%d)\n",
+		mdev->n_streamer);
+	mutex_unlock(&mdev->s_mutex);
+	mxr_reg_dump(mdev);
+
+	return 0;
+}
+
+void mxr_output_get(struct mxr_device *mdev)
+{
+	mutex_lock(&mdev->mutex);
+	++mdev->n_output;
+	mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output);
+	/* turn on auxiliary driver */
+	if (mdev->n_output == 1)
+		v4l2_subdev_call(to_outsd(mdev), core, s_power, 1);
+	mutex_unlock(&mdev->mutex);
+}
+
+void mxr_output_put(struct mxr_device *mdev)
+{
+	mutex_lock(&mdev->mutex);
+	--mdev->n_output;
+	mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output);
+	/* turn on auxiliary driver */
+	if (mdev->n_output == 0)
+		v4l2_subdev_call(to_outsd(mdev), core, s_power, 0);
+	WARN(mdev->n_output < 0, "negative number of output users (%d)\n",
+		mdev->n_output);
+	mutex_unlock(&mdev->mutex);
+}
+
+static int mxr_runtime_resume(struct device *dev);
+static int mxr_runtime_suspend(struct device *dev);
+
+int mxr_power_get(struct mxr_device *mdev)
+{
+	/* If runtime PM is not implemented, mxr_runtime_resume
+	 * function is directly called.
+	 */
+#ifdef CONFIG_PM_RUNTIME
+	int ret = pm_runtime_get_sync(mdev->dev);
+	/* returning 1 means that power is already enabled,
+	 * so zero success be returned */
+	if (IS_ERR_VALUE(ret))
+		return ret;
+	return 0;
+#else
+	mxr_runtime_resume(mdev->dev);
+	return 0;
+#endif
+}
+
+void mxr_power_put(struct mxr_device *mdev)
+{
+	/* If runtime PM is not implemented, mxr_runtime_suspend
+	 * function is directly called.
+	 */
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_put_sync(mdev->dev);
+#else
+	mxr_runtime_suspend(mdev->dev);
+#endif
+}
+
+/* --------- RESOURCE MANAGEMENT -------------*/
+
+static int __devinit mxr_acquire_plat_resources(struct mxr_device *mdev,
+	struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mxr");
+	if (res == NULL) {
+		mxr_err(mdev, "get memory resource failed.\n");
+		ret = -ENXIO;
+		goto fail;
+	}
+
+	mdev->res.mxr_regs = ioremap(res->start, resource_size(res));
+	if (mdev->res.mxr_regs == NULL) {
+		mxr_err(mdev, "register mapping failed.\n");
+		ret = -ENXIO;
+		goto fail;
+	}
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vp");
+	if (res == NULL) {
+		mxr_err(mdev, "get memory resource failed.\n");
+		ret = -ENXIO;
+		goto fail_mxr_regs;
+	}
+
+	mdev->res.vp_regs = ioremap(res->start, resource_size(res));
+	if (mdev->res.vp_regs == NULL) {
+		mxr_err(mdev, "register mapping failed.\n");
+		ret = -ENXIO;
+		goto fail_mxr_regs;
+	}
+#endif
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq");
+	if (res == NULL) {
+		mxr_err(mdev, "get interrupt resource failed.\n");
+		ret = -ENXIO;
+		goto fail_vp_regs;
+	}
+
+	ret = request_irq(res->start, mxr_irq_handler, 0, "s5p-mixer", mdev);
+	if (ret) {
+		mxr_err(mdev, "request interrupt failed.\n");
+		goto fail_vp_regs;
+	}
+	mdev->res.irq = res->start;
+
+	return 0;
+
+fail_vp_regs:
+#if defined(CONFIG_ARCH_EXYNOS4)
+	iounmap(mdev->res.vp_regs);
+
+fail_mxr_regs:
+#endif
+	iounmap(mdev->res.mxr_regs);
+
+fail:
+	return ret;
+}
+
+static void mxr_release_plat_resources(struct mxr_device *mdev)
+{
+	free_irq(mdev->res.irq, mdev);
+#if defined(CONFIG_ARCH_EXYNOS4)
+	iounmap(mdev->res.vp_regs);
+#endif
+	iounmap(mdev->res.mxr_regs);
+}
+
+static void mxr_release_clocks(struct mxr_device *mdev)
+{
+	struct mxr_resources *res = &mdev->res;
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	if (!IS_ERR_OR_NULL(res->vp))
+		clk_put(res->vp);
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+	if (!IS_ERR_OR_NULL(res->sclk_mixer))
+		clk_put(res->sclk_mixer);
+	if (!IS_ERR_OR_NULL(res->sclk_dac))
+		clk_put(res->sclk_dac);
+#endif
+	if (!IS_ERR_OR_NULL(res->mixer))
+		clk_put(res->mixer);
+	if (!IS_ERR_OR_NULL(res->sclk_hdmi))
+		clk_put(res->sclk_hdmi);
+}
+
+static int mxr_acquire_clocks(struct mxr_device *mdev)
+{
+	struct mxr_resources *res = &mdev->res;
+	struct device *dev = mdev->dev;
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	res->vp = clk_get(dev, "vp");
+	if (IS_ERR_OR_NULL(res->vp)) {
+		mxr_err(mdev, "failed to get clock 'vp'\n");
+		goto fail;
+	}
+	res->sclk_mixer = clk_get(dev, "sclk_mixer");
+	if (IS_ERR_OR_NULL(res->sclk_mixer)) {
+		mxr_err(mdev, "failed to get clock 'sclk_mixer'\n");
+		goto fail;
+	}
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+
+	res->sclk_dac = clk_get(dev, "sclk_dac");
+	if (IS_ERR_OR_NULL(res->sclk_dac)) {
+		mxr_err(mdev, "failed to get clock 'sclk_dac'\n");
+		goto fail;
+	}
+#endif
+	res->mixer = clk_get(dev, "mixer");
+	if (IS_ERR_OR_NULL(res->mixer)) {
+		mxr_err(mdev, "failed to get clock 'mixer'\n");
+		goto fail;
+	}
+	res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
+	if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
+		mxr_err(mdev, "failed to get clock 'sclk_hdmi'\n");
+		goto fail;
+	}
+
+	return 0;
+fail:
+	mxr_release_clocks(mdev);
+	return -ENODEV;
+}
+
+static int __devinit mxr_acquire_resources(struct mxr_device *mdev,
+	struct platform_device *pdev)
+{
+	int ret;
+	ret = mxr_acquire_plat_resources(mdev, pdev);
+
+	if (ret)
+		goto fail;
+
+	ret = mxr_acquire_clocks(mdev);
+	if (ret)
+		goto fail_plat;
+
+	mxr_info(mdev, "resources acquired\n");
+	return 0;
+
+fail_plat:
+	mxr_release_plat_resources(mdev);
+fail:
+	mxr_err(mdev, "resources acquire failed\n");
+	return ret;
+}
+
+static void mxr_release_resources(struct mxr_device *mdev)
+{
+	mxr_release_clocks(mdev);
+	mxr_release_plat_resources(mdev);
+	memset(&mdev->res, 0, sizeof mdev->res);
+}
+
+static void mxr_release_layers(struct mxr_device *mdev)
+{
+	int i, j;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		for (j = 0; j < MXR_MAX_LAYERS; ++j)
+			if (mdev->sub_mxr[i].layer[j])
+				mxr_layer_release(mdev->sub_mxr[i].layer[j]);
+	}
+}
+
+static int __devinit mxr_acquire_layers(struct mxr_device *mdev,
+	struct mxr_platform_data *pdata)
+{
+	struct sub_mxr_device *sub_mxr;
+
+	sub_mxr = &mdev->sub_mxr[MXR_SUB_MIXER0];
+#if defined(CONFIG_ARCH_EXYNOS4)
+	sub_mxr->layer[MXR_LAYER_VIDEO] = mxr_vp_layer_create(mdev,
+			MXR_SUB_MIXER0, 0, EXYNOS_VIDEONODE_MXR_VIDEO);
+#else
+	sub_mxr->layer[MXR_LAYER_VIDEO] =
+		mxr_video_layer_create(mdev, MXR_SUB_MIXER0, 0);
+#endif
+	sub_mxr->layer[MXR_LAYER_GRP0] = mxr_graph_layer_create(mdev,
+			MXR_SUB_MIXER0, 0, EXYNOS_VIDEONODE_MXR_GRP(0));
+	sub_mxr->layer[MXR_LAYER_GRP1] = mxr_graph_layer_create(mdev,
+			MXR_SUB_MIXER0, 1, EXYNOS_VIDEONODE_MXR_GRP(1));
+	if (!sub_mxr->layer[MXR_LAYER_VIDEO] || !sub_mxr->layer[MXR_LAYER_GRP0]
+			|| !sub_mxr->layer[MXR_LAYER_GRP1]) {
+		mxr_err(mdev, "failed to acquire layers\n");
+		goto fail;
+	}
+
+	/* Exynos5250 supports 2 sub-mixers */
+	if (MXR_MAX_SUB_MIXERS == 2) {
+		sub_mxr = &mdev->sub_mxr[MXR_SUB_MIXER1];
+		sub_mxr->layer[MXR_LAYER_VIDEO] =
+			mxr_video_layer_create(mdev, MXR_SUB_MIXER1, 1);
+		sub_mxr->layer[MXR_LAYER_GRP0] = mxr_graph_layer_create(mdev,
+				MXR_SUB_MIXER1, 2, EXYNOS_VIDEONODE_MXR_GRP(2));
+		sub_mxr->layer[MXR_LAYER_GRP1] = mxr_graph_layer_create(mdev,
+				MXR_SUB_MIXER1, 3, EXYNOS_VIDEONODE_MXR_GRP(3));
+		if (!sub_mxr->layer[MXR_LAYER_VIDEO] ||
+				!sub_mxr->layer[MXR_LAYER_GRP0] ||
+				!sub_mxr->layer[MXR_LAYER_GRP1]) {
+			mxr_err(mdev, "failed to acquire layers\n");
+			goto fail;
+		}
+	}
+
+	return 0;
+
+fail:
+	mxr_release_layers(mdev);
+	return -ENODEV;
+}
+
+/* ---------- POWER MANAGEMENT ----------- */
+
+static int mxr_runtime_resume(struct device *dev)
+{
+	struct mxr_device *mdev = to_mdev(dev);
+	struct mxr_resources *res = &mdev->res;
+
+	mxr_dbg(mdev, "resume - start\n");
+	mutex_lock(&mdev->mutex);
+	/* turn clocks on */
+	clk_enable(res->mixer);
+#if defined(CONFIG_ARCH_EXYNOS4)
+	clk_enable(res->vp);
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+	clk_enable(res->sclk_mixer);
+#endif
+	/* enable system mmu for tv. It must be enabled after enabling
+	 * mixer's clock. Because of system mmu limitation. */
+	mdev->vb2->resume(mdev->alloc_ctx);
+	/* apply default configuration */
+	mxr_reg_reset(mdev);
+	mxr_dbg(mdev, "resume - finished\n");
+
+	mutex_unlock(&mdev->mutex);
+	return 0;
+}
+
+static int mxr_runtime_suspend(struct device *dev)
+{
+	struct mxr_device *mdev = to_mdev(dev);
+	struct mxr_resources *res = &mdev->res;
+	mxr_dbg(mdev, "suspend - start\n");
+	mutex_lock(&mdev->mutex);
+	/* disable system mmu for tv. It must be disabled before disabling
+	 * mixer's clock. Because of system mmu limitation. */
+	mdev->vb2->suspend(mdev->alloc_ctx);
+	/* turn clocks off */
+#if defined(CONFIG_CPU_EXYNOS4210)
+	clk_disable(res->sclk_mixer);
+#endif
+#if defined(CONFIG_ARCH_EXYNOS4)
+	clk_disable(res->vp);
+#endif
+	clk_disable(res->mixer);
+	mutex_unlock(&mdev->mutex);
+	mxr_dbg(mdev, "suspend - finished\n");
+	return 0;
+}
+
+/* ---------- SUB-DEVICE CALLBACKS ----------- */
+
+static const struct dev_pm_ops mxr_pm_ops = {
+	.runtime_suspend = mxr_runtime_suspend,
+	.runtime_resume	 = mxr_runtime_resume,
+};
+
+static int mxr_s_power(struct v4l2_subdev *sd, int on)
+{
+	return 0;
+}
+
+/* When mixer is connected to gscaler through local path, only gscaler's
+ * video device can command alpha blending functionality for mixer */
+static int mxr_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct mxr_device *mdev = sd_to_mdev(sd);
+	struct mxr_layer *layer;
+	int v = ctrl->value;
+	int num = 0;
+
+	mxr_dbg(mdev, "%s start\n", __func__);
+	mxr_dbg(mdev, "id = %d, value = %d\n", ctrl->id, ctrl->value);
+
+	if (!strcmp(sd->name, "s5p-mixer0"))
+		num = MXR_SUB_MIXER0;
+	else if (!strcmp(sd->name, "s5p-mixer1"))
+		num = MXR_SUB_MIXER1;
+
+	layer = mdev->sub_mxr[num].layer[MXR_LAYER_VIDEO];
+	switch (ctrl->id) {
+	case V4L2_CID_TV_LAYER_BLEND_ENABLE:
+		layer->layer_blend_en = v;
+		break;
+	case V4L2_CID_TV_LAYER_BLEND_ALPHA:
+		layer->layer_alpha = (u32)v;
+		break;
+	case V4L2_CID_TV_PIXEL_BLEND_ENABLE:
+		layer->pixel_blend_en = v;
+		break;
+	case V4L2_CID_TV_CHROMA_ENABLE:
+		layer->chroma_en = v;
+		break;
+	case V4L2_CID_TV_CHROMA_VALUE:
+		layer->chroma_val = (u32)v;
+		break;
+	case V4L2_CID_TV_LAYER_PRIO:
+		layer->prio = (u8)v;
+		if (layer->pipe.state == MXR_PIPELINE_STREAMING)
+			mxr_reg_set_layer_prio(mdev);
+		break;
+	default:
+		mxr_err(mdev, "invalid control id\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mxr_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct mxr_device *mdev = sd_to_mdev(sd);
+	struct exynos_entity_data *md_data;
+	int ret;
+
+	/* It can be known which entity calls this function */
+	md_data = v4l2_get_subdevdata(sd);
+	mdev->mxr_data_from = md_data->mxr_data_from;
+
+	if (enable)
+		ret = mxr_streamer_get(mdev, sd);
+	else
+		ret = mxr_streamer_put(mdev, sd);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static struct v4l2_mbus_framefmt *
+__mxr_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		unsigned int pad, enum v4l2_subdev_format_whence which)
+{
+	struct sub_mxr_device *sub_mxr = sd_to_sub_mxr(sd);
+
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return v4l2_subdev_get_try_format(fh, pad);
+	else
+		return &sub_mxr->mbus_fmt[pad];
+}
+
+static struct v4l2_rect *
+__mxr_get_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		unsigned int pad, enum v4l2_subdev_format_whence which)
+{
+	struct sub_mxr_device *sub_mxr = sd_to_sub_mxr(sd);
+
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return v4l2_subdev_get_try_crop(fh, pad);
+	else
+		return &sub_mxr->crop[pad];
+}
+
+static unsigned int mxr_adjust_graph_format(unsigned int code)
+{
+	switch (code) {
+	case V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE:
+	case V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE:
+	case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
+	case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
+	case V4L2_MBUS_FMT_RGB565_2X8_BE:
+	case V4L2_MBUS_FMT_RGB565_2X8_LE:
+	case V4L2_MBUS_FMT_XRGB8888_4X8_LE:
+		return code;
+	default:
+		return V4L2_MBUS_FMT_XRGB8888_4X8_LE; /* default format */
+	}
+}
+
+/* This can be moved to graphic layer's callback function */
+static void mxr_set_layer_src_fmt(struct sub_mxr_device *sub_mxr, u32 pad)
+{
+	/* sink pad number and array index of layer are same */
+	struct mxr_layer *layer = sub_mxr->layer[pad];
+	struct v4l2_mbus_framefmt *fmt = &sub_mxr->mbus_fmt[pad];
+	u32 fourcc;
+
+	switch (fmt->code) {
+	case V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE:
+	case V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE:
+		fourcc = V4L2_PIX_FMT_RGB444;
+		break;
+	case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
+	case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
+		fourcc = V4L2_PIX_FMT_RGB555;
+		break;
+	case V4L2_MBUS_FMT_RGB565_2X8_BE:
+	case V4L2_MBUS_FMT_RGB565_2X8_LE:
+		fourcc = V4L2_PIX_FMT_RGB565;
+		break;
+	case V4L2_MBUS_FMT_XRGB8888_4X8_LE:
+		fourcc = V4L2_PIX_FMT_BGR32;
+		break;
+	}
+	/* This will be applied to hardware right after streamon */
+	layer->fmt = find_format_by_fourcc(layer, fourcc);
+}
+
+static int mxr_try_format(struct mxr_device *mdev,
+		struct v4l2_subdev_fh *fh, u32 pad,
+		struct v4l2_mbus_framefmt *fmt,
+		enum v4l2_subdev_format_whence which)
+{
+	struct v4l2_mbus_framefmt mbus_fmt;
+
+	fmt->width = clamp_val(fmt->width, 1, 32767);
+	fmt->height = clamp_val(fmt->height, 1, 2047);
+
+	switch (pad) {
+	case MXR_PAD_SINK_GSCALER:
+		fmt->code = V4L2_MBUS_FMT_YUV8_1X24;
+		break;
+	case MXR_PAD_SINK_GRP0:
+	case MXR_PAD_SINK_GRP1:
+		fmt->code = mxr_adjust_graph_format(fmt->code);
+		break;
+	case MXR_PAD_SOURCE_GSCALER:
+	case MXR_PAD_SOURCE_GRP0:
+	case MXR_PAD_SOURCE_GRP1:
+		mxr_get_mbus_fmt(mdev, &mbus_fmt);
+		fmt->code = (fmt->code == V4L2_MBUS_FMT_YUV8_1X24) ?
+			V4L2_MBUS_FMT_YUV8_1X24 : V4L2_MBUS_FMT_XRGB8888_4X8_LE;
+		fmt->width = mbus_fmt.width;
+		fmt->height = mbus_fmt.height;
+		break;
+	}
+
+	return 0;
+}
+
+static void mxr_apply_format(struct v4l2_subdev *sd,
+		struct v4l2_subdev_fh *fh, u32 pad,
+		struct v4l2_mbus_framefmt *fmt,
+		enum v4l2_subdev_format_whence which)
+{
+	struct sub_mxr_device *sub_mxr;
+	struct mxr_device *mdev;
+	int i, j;
+	sub_mxr = sd_to_sub_mxr(sd);
+	mdev = sd_to_mdev(sd);
+
+	if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		if (pad == MXR_PAD_SINK_GRP0 || pad == MXR_PAD_SINK_GRP1) {
+			struct mxr_layer *layer = sub_mxr->layer[pad];
+
+			mxr_set_layer_src_fmt(sub_mxr, pad);
+			layer->geo.src.full_width = fmt->width;
+			layer->geo.src.full_height = fmt->height;
+			layer->ops.fix_geometry(layer);
+		} else if (pad == MXR_PAD_SOURCE_GSCALER
+				|| pad == MXR_PAD_SOURCE_GRP0
+				|| pad == MXR_PAD_SOURCE_GRP1) {
+			for (i = 0; i < MXR_MAX_LAYERS; ++i) {
+				struct mxr_layer *layer = sub_mxr->layer[i];
+				layer->geo.dst.full_width = fmt->width;
+				layer->geo.dst.full_height = fmt->height;
+				layer->ops.fix_geometry(layer);
+			}
+			for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+				sub_mxr = &mdev->sub_mxr[i];
+				for (j = MXR_PAD_SOURCE_GSCALER;
+						j < MXR_PADS_NUM; ++j)
+					sub_mxr->mbus_fmt[j].code = fmt->code;
+			}
+		}
+	}
+}
+
+static int mxr_try_crop(struct v4l2_subdev *sd,
+		struct v4l2_subdev_fh *fh, unsigned int pad,
+		struct v4l2_rect *r, enum v4l2_subdev_format_whence which)
+{
+	struct v4l2_mbus_framefmt *fmt;
+
+	fmt = __mxr_get_fmt(sd, fh, pad, which);
+	if (fmt == NULL)
+		return -EINVAL;
+
+	r->left = clamp_val(r->left, 0, fmt->width);
+	r->top = clamp_val(r->top, 0, fmt->height);
+	r->width = clamp_val(r->width, 1, fmt->width - r->left);
+	r->height = clamp_val(r->height, 1, fmt->height - r->top);
+
+	/* need to align size with G-Scaler */
+	if (pad == MXR_PAD_SINK_GSCALER || pad == MXR_PAD_SOURCE_GSCALER)
+		if (r->width % 2)
+			r->width -= 1;
+
+	return 0;
+}
+
+static void mxr_apply_crop(struct v4l2_subdev *sd,
+		struct v4l2_subdev_fh *fh, unsigned int pad,
+		struct v4l2_rect *r, enum v4l2_subdev_format_whence which)
+{
+	struct sub_mxr_device *sub_mxr = sd_to_sub_mxr(sd);
+	struct mxr_layer *layer;
+
+	if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		if (pad == MXR_PAD_SINK_GRP0 || pad == MXR_PAD_SINK_GRP1) {
+			layer = sub_mxr->layer[pad];
+
+			layer->geo.src.width = r->width;
+			layer->geo.src.height = r->height;
+			layer->geo.src.x_offset = r->left;
+			layer->geo.src.y_offset = r->top;
+			layer->ops.fix_geometry(layer);
+		} else if (pad == MXR_PAD_SOURCE_GSCALER
+				|| pad == MXR_PAD_SOURCE_GRP0
+				|| pad == MXR_PAD_SOURCE_GRP1) {
+			layer = sub_mxr->layer[pad - (MXR_PADS_NUM >> 1)];
+
+			layer->geo.dst.width = r->width;
+			layer->geo.dst.height = r->height;
+			layer->geo.dst.x_offset = r->left;
+			layer->geo.dst.y_offset = r->top;
+			layer->ops.fix_geometry(layer);
+		}
+	}
+}
+
+static int mxr_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		       struct v4l2_subdev_format *format)
+{
+	struct v4l2_mbus_framefmt *fmt;
+
+	fmt = __mxr_get_fmt(sd, fh, format->pad, format->which);
+	if (fmt == NULL)
+		return -EINVAL;
+
+	format->format = *fmt;
+
+	return 0;
+}
+
+static int mxr_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		       struct v4l2_subdev_format *format)
+{
+	struct mxr_device *mdev = sd_to_mdev(sd);
+	struct v4l2_mbus_framefmt *fmt;
+	int ret;
+	u32 pad;
+
+	fmt = __mxr_get_fmt(sd, fh, format->pad, format->which);
+	if (fmt == NULL)
+		return -EINVAL;
+
+	ret = mxr_try_format(mdev, fh, format->pad, &format->format,
+			format->which);
+	if (ret)
+		return ret;
+
+	*fmt = format->format;
+
+	mxr_apply_format(sd, fh, format->pad, &format->format, format->which);
+
+	if (format->pad == MXR_PAD_SINK_GSCALER ||
+			format->pad == MXR_PAD_SINK_GRP0 ||
+			format->pad == MXR_PAD_SINK_GRP1) {
+		pad = format->pad + (MXR_PADS_NUM >> 1);
+		fmt = __mxr_get_fmt(sd, fh, pad, format->which);
+		if (fmt == NULL)
+			return -EINVAL;
+
+		*fmt = format->format;
+
+		ret = mxr_try_format(mdev, fh, pad, fmt, format->which);
+		if (ret)
+			return ret;
+
+		mxr_apply_format(sd, fh, pad, fmt, format->which);
+	}
+
+	return 0;
+}
+
+static int mxr_set_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		       struct v4l2_subdev_crop *crop)
+{
+	struct v4l2_rect *r;
+	int ret;
+	u32 pad;
+
+	r = __mxr_get_crop(sd, fh, crop->pad, crop->which);
+	if (r == NULL)
+		return -EINVAL;
+
+	ret = mxr_try_crop(sd, fh, crop->pad, &crop->rect, crop->which);
+	if (ret)
+		return ret;
+
+	/* transfer adjusted crop information to user space */
+	*r = crop->rect;
+
+	/* reserved[0] is used for sink pad number temporally */
+	mxr_apply_crop(sd, fh, crop->pad, r, crop->which);
+
+	/* In case of sink pad, crop info will be propagated to source pad */
+	if (crop->pad == MXR_PAD_SINK_GSCALER ||
+			crop->pad == MXR_PAD_SINK_GRP0 ||
+			crop->pad == MXR_PAD_SINK_GRP1) {
+		pad = crop->pad + (MXR_PADS_NUM >> 1);
+		r = __mxr_get_crop(sd, fh, pad, crop->which);
+		if (r == NULL)
+			return -EINVAL;
+		/* store propagated crop info to source pad */
+		*r = crop->rect;
+
+		ret = mxr_try_crop(sd, fh, pad, r, crop->which);
+		if (ret)
+			return ret;
+
+		mxr_apply_crop(sd, fh, pad, r, crop->which);
+	}
+
+	return 0;
+}
+
+static int mxr_get_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+		       struct v4l2_subdev_crop *crop)
+{
+	struct v4l2_rect *r;
+
+	r = __mxr_get_crop(sd, fh, crop->pad, crop->which);
+	if (r == NULL)
+		return -EINVAL;
+
+	crop->rect = *r;
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops mxr_sd_core_ops = {
+	.s_power = mxr_s_power,
+	.s_ctrl = mxr_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops mxr_sd_video_ops = {
+	.s_stream = mxr_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops	mxr_sd_pad_ops = {
+	.get_fmt = mxr_get_fmt,
+	.set_fmt = mxr_set_fmt,
+	.get_crop = mxr_get_crop,
+	.set_crop = mxr_set_crop
+};
+
+static const struct v4l2_subdev_ops mxr_sd_ops = {
+	.core = &mxr_sd_core_ops,
+	.video = &mxr_sd_video_ops,
+	.pad = &mxr_sd_pad_ops,
+};
+
+static int mxr_link_setup(struct media_entity *entity,
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
+{
+	struct media_pad *pad;
+	struct sub_mxr_device *sub_mxr = entity_to_sub_mxr(entity);
+	struct mxr_device *mdev = sub_mxr_to_mdev(sub_mxr);
+	int i;
+	int gsc_num = 0;
+
+	/* difficult to get dev ptr */
+	printk(KERN_DEBUG "%s %s\n", __func__, flags ? "start" : "stop");
+
+	if (flags & MEDIA_LNK_FL_ENABLED) {
+		sub_mxr->use = 1;
+		if (local->index == MXR_PAD_SINK_GSCALER)
+			sub_mxr->local = 1;
+		/* find a remote pad by interating over all links
+		 * until enabled link is found.
+		 * This will be remove. because Exynos5250 only supports
+		 * HDMI output */
+		pad = media_entity_remote_source((struct media_pad *)local);
+		if (pad) {
+			printk(KERN_ERR "%s is already connected to %s\n",
+					entity->name, pad->entity->name);
+			return -EBUSY;
+		}
+	} else {
+		if (local->index == MXR_PAD_SINK_GSCALER)
+			sub_mxr->local = 0;
+		sub_mxr->use = 0;
+		for (i = 0; i < entity->num_links; ++i)
+			if (entity->links[i].flags & MEDIA_LNK_FL_ENABLED)
+				sub_mxr->use = 1;
+	}
+
+	if (!strcmp(remote->entity->name, "exynos-gsc-sd.0"))
+		gsc_num = 0;
+	else if (!strcmp(remote->entity->name, "exynos-gsc-sd.1"))
+		gsc_num = 1;
+	else if (!strcmp(remote->entity->name, "exynos-gsc-sd.2"))
+		gsc_num = 2;
+	else if (!strcmp(remote->entity->name, "exynos-gsc-sd.3"))
+		gsc_num = 3;
+
+	if (!strcmp(local->entity->name, "s5p-mixer0"))
+		mdev->mxr0_gsc = gsc_num;
+	else if (!strcmp(local->entity->name, "s5p-mixer1"))
+		mdev->mxr1_gsc = gsc_num;
+
+	/* deliver those variables to mxr_streamer_get() */
+	mdev->flags = flags;
+	return 0;
+}
+
+/* mixer entity operations */
+static const struct media_entity_operations mxr_entity_ops = {
+	.link_setup = mxr_link_setup,
+};
+
+/* ---------- MEDIA CONTROLLER MANAGEMENT ----------- */
+
+static int mxr_register_entity(struct mxr_device *mdev, int mxr_num)
+{
+	struct v4l2_subdev *sd = &mdev->sub_mxr[mxr_num].sd;
+	struct media_pad *pads = mdev->sub_mxr[mxr_num].pads;
+	struct media_entity *me = &sd->entity;
+	struct exynos_md *md;
+	int ret;
+
+	mxr_dbg(mdev, "mixer%d entity init\n", mxr_num);
+
+	/* init mixer sub-device */
+	v4l2_subdev_init(sd, &mxr_sd_ops);
+	sd->owner = THIS_MODULE;
+	sprintf(sd->name, "s5p-mixer%d", mxr_num);
+
+	/* mixer sub-device can be opened in user space */
+	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+	/* init mixer sub-device as entity */
+	pads[MXR_PAD_SINK_GSCALER].flags = MEDIA_PAD_FL_SINK;
+	pads[MXR_PAD_SINK_GRP0].flags = MEDIA_PAD_FL_SINK;
+	pads[MXR_PAD_SINK_GRP1].flags = MEDIA_PAD_FL_SINK;
+	pads[MXR_PAD_SOURCE_GSCALER].flags = MEDIA_PAD_FL_SOURCE;
+	pads[MXR_PAD_SOURCE_GRP0].flags = MEDIA_PAD_FL_SOURCE;
+	pads[MXR_PAD_SOURCE_GRP1].flags = MEDIA_PAD_FL_SOURCE;
+	me->ops = &mxr_entity_ops;
+	ret = media_entity_init(me, MXR_PADS_NUM, pads, 0);
+	if (ret) {
+		mxr_err(mdev, "failed to initialize media entity\n");
+		return ret;
+	}
+
+	md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
+	if (!md) {
+		mxr_err(mdev, "failed to get output media device\n");
+		return -ENODEV;
+	}
+
+	ret = v4l2_device_register_subdev(&md->v4l2_dev, sd);
+	if (ret) {
+		mxr_err(mdev, "failed to register mixer subdev\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mxr_register_entities(struct mxr_device *mdev)
+{
+	int ret, i;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		ret = mxr_register_entity(mdev, i);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void mxr_unregister_entity(struct mxr_device *mdev, int mxr_num)
+{
+	v4l2_device_unregister_subdev(&mdev->sub_mxr[mxr_num].sd);
+}
+
+static void mxr_unregister_entities(struct mxr_device *mdev)
+{
+	int i;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i)
+		mxr_unregister_entity(mdev, i);
+}
+
+static void mxr_entities_info_print(struct mxr_device *mdev)
+{
+	struct v4l2_subdev *sd;
+	struct media_entity *sd_me;
+	struct media_entity *vd_me;
+	int num_layers;
+	int i, j;
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	num_layers = 3;
+#else
+	num_layers = 2;
+#endif
+	mxr_dbg(mdev, "\n************ MIXER entities info ***********\n");
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		mxr_dbg(mdev, "[SUB DEVICE INFO]\n");
+		sd = &mdev->sub_mxr[i].sd;
+		sd_me = &sd->entity;
+		entity_info_print(sd_me, mdev->dev);
+
+		for (j = 0; j < num_layers; ++j) {
+			vd_me = &mdev->sub_mxr[i].layer[j]->vfd.entity;
+
+			mxr_dbg(mdev, "\n[VIDEO DEVICE %d INFO]\n", j);
+			entity_info_print(vd_me, mdev->dev);
+		}
+	}
+
+	mxr_dbg(mdev, "**************************************************\n\n");
+}
+
+static int mxr_create_links_sub_mxr(struct mxr_device *mdev, int mxr_num,
+		int flags)
+{
+	struct exynos_md *md;
+	struct mxr_layer *layer;
+	int ret;
+	int i, j;
+	char err[80];
+
+	mxr_info(mdev, "mixer%d create links\n", mxr_num);
+
+	memset(err, 0, sizeof(err));
+
+	/* link creation : gscaler0~3[1] -> mixer[0] */
+	md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
+	for (i = 0; i < MAX_GSC_SUBDEV; ++i) {
+		if (md->gsc_sd[i] != NULL) {
+			ret = media_entity_create_link(&md->gsc_sd[i]->entity,
+				GSC_OUT_PAD_SOURCE,
+				&mdev->sub_mxr[mxr_num].sd.entity,
+				MXR_PAD_SINK_GSCALER, 0);
+			if (ret) {
+				sprintf(err, "%s --> %s",
+					md->gsc_sd[i]->entity.name,
+					mdev->sub_mxr[mxr_num].sd.entity.name);
+				goto fail;
+			}
+		}
+	}
+
+	/* link creation : mixer input0[0] -> mixer[1] */
+	layer = mdev->sub_mxr[mxr_num].layer[MXR_LAYER_GRP0];
+	ret = media_entity_create_link(&layer->vfd.entity, 0,
+		&mdev->sub_mxr[mxr_num].sd.entity, MXR_PAD_SINK_GRP0, flags);
+	if (ret) {
+		sprintf(err, "%s --> %s", layer->vfd.entity.name,
+				mdev->sub_mxr[mxr_num].sd.entity.name);
+		goto fail;
+	}
+
+	/* link creation : mixer input1[0] -> mixer[2] */
+	layer = mdev->sub_mxr[mxr_num].layer[MXR_LAYER_GRP1];
+	ret = media_entity_create_link(&layer->vfd.entity, 0,
+		&mdev->sub_mxr[mxr_num].sd.entity, MXR_PAD_SINK_GRP1, flags);
+	if (ret) {
+		sprintf(err, "%s --> %s", layer->vfd.entity.name,
+				mdev->sub_mxr[mxr_num].sd.entity.name);
+		goto fail;
+	}
+
+	/* link creation : mixer[3,4,5] -> output device(hdmi or sdo)[0] */
+	mxr_dbg(mdev, "output device count = %d\n", mdev->output_cnt);
+	for (i = 0; i < mdev->output_cnt; ++i) { /* sink pad of hdmi/sdo is 0 */
+		flags = 0;
+		/* default output device link is HDMI */
+		if (!strcmp(mdev->output[i]->sd->name, "s5p-hdmi"))
+			flags = MEDIA_LNK_FL_ENABLED;
+
+		for (j = MXR_PAD_SOURCE_GSCALER; j < MXR_PADS_NUM; ++j) {
+			ret = media_entity_create_link(
+					&mdev->sub_mxr[mxr_num].sd.entity,
+					j, &mdev->output[i]->sd->entity,
+					0, flags);
+			if (ret) {
+				sprintf(err, "%s --> %s",
+					mdev->sub_mxr[mxr_num].sd.entity.name,
+					mdev->output[i]->sd->entity.name);
+				goto fail;
+			}
+		}
+	}
+
+	return 0;
+
+fail:
+	mxr_err(mdev, "failed to create link : %s\n", err);
+	return ret;
+}
+
+static int mxr_create_links(struct mxr_device *mdev)
+{
+	int ret, i;
+	int flags;
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	struct mxr_layer *layer;
+	struct media_entity *source, *sink;
+
+	layer = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_VIDEO];
+	source = &layer->vfd.entity;
+	sink = &mdev->sub_mxr[MXR_SUB_MIXER0].sd.entity;
+	ret = media_entity_create_link(source, 0, sink, MXR_PAD_SINK_GSCALER,
+			MEDIA_LNK_FL_ENABLED);
+#endif
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		if (mdev->sub_mxr[i].use)
+			flags = MEDIA_LNK_FL_ENABLED;
+		else
+			flags = 0;
+
+		ret = mxr_create_links_sub_mxr(mdev, i, flags);
+		if (ret)
+			return ret;
+	}
+
+	mxr_info(mdev, "mixer links are created successfully\n");
+
+	return 0;
+}
+
+/* --------- DRIVER INITIALIZATION ---------- */
+
+static int __devinit mxr_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mxr_platform_data *pdata = dev->platform_data;
+	struct mxr_device *mdev;
+	int ret;
+
+	/* mdev does not exist yet so no mxr_dbg is used */
+	dev_info(dev, "probe start\n");
+
+	mdev = kzalloc(sizeof *mdev, GFP_KERNEL);
+	if (!mdev) {
+		dev_err(dev, "not enough memory.\n");
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	/* setup pointer to master device */
+	mdev->dev = dev;
+
+	/* use only sub mixer0 as default */
+	mdev->sub_mxr[MXR_SUB_MIXER0].use = 1;
+	mdev->sub_mxr[MXR_SUB_MIXER1].use = 1;
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	mdev->vb2 = &mxr_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	mdev->vb2 = &mxr_vb2_ion;
+#endif
+
+	mutex_init(&mdev->mutex);
+	mutex_init(&mdev->s_mutex);
+	spin_lock_init(&mdev->reg_slock);
+	init_waitqueue_head(&mdev->event_queue);
+
+	/* acquire resources: regs, irqs, clocks, regulators */
+	ret = mxr_acquire_resources(mdev, pdev);
+	if (ret)
+		goto fail_mem;
+
+	/* configure resources for video output */
+	ret = mxr_acquire_video(mdev, mxr_output_conf,
+		ARRAY_SIZE(mxr_output_conf));
+	if (ret)
+		goto fail_resources;
+
+	/* register mixer subdev as entity */
+	ret = mxr_register_entities(mdev);
+	if (ret)
+		goto fail_video;
+
+	/* configure layers */
+	ret = mxr_acquire_layers(mdev, pdata);
+	if (ret)
+		goto fail_entity;
+
+	/* create links connected to gscaler, mixer inputs and hdmi */
+	ret = mxr_create_links(mdev);
+	if (ret)
+		goto fail_entity;
+
+	dev_set_drvdata(dev, mdev);
+
+	pm_runtime_enable(dev);
+
+	mxr_entities_info_print(mdev);
+
+	mxr_info(mdev, "probe successful\n");
+	return 0;
+
+fail_entity:
+	mxr_unregister_entities(mdev);
+
+fail_video:
+	mxr_release_video(mdev);
+
+fail_resources:
+	mxr_release_resources(mdev);
+
+fail_mem:
+	kfree(mdev);
+
+fail:
+	dev_info(dev, "probe failed\n");
+	return ret;
+}
+
+static int __devexit mxr_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mxr_device *mdev = to_mdev(dev);
+
+	pm_runtime_disable(dev);
+
+	mxr_release_layers(mdev);
+	mxr_release_video(mdev);
+	mxr_release_resources(mdev);
+
+	kfree(mdev);
+
+	dev_info(dev, "remove sucessful\n");
+	return 0;
+}
+
+static struct platform_driver mxr_driver __refdata = {
+	.probe = mxr_probe,
+	.remove = __devexit_p(mxr_remove),
+	.driver = {
+		.name = MXR_DRIVER_NAME,
+		.owner = THIS_MODULE,
+		.pm = &mxr_pm_ops,
+	}
+};
+
+static int __init mxr_init(void)
+{
+	int i, ret;
+	static const char banner[] __initdata = KERN_INFO
+		"Samsung TV Mixer driver, "
+		"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
+	printk(banner);
+
+	/* Loading auxiliary modules */
+	for (i = 0; i < ARRAY_SIZE(mxr_output_conf); ++i)
+		request_module(mxr_output_conf[i].module_name);
+
+	ret = platform_driver_register(&mxr_driver);
+	if (ret != 0) {
+		printk(KERN_ERR "registration of MIXER driver failed\n");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+module_init(mxr_init);
+
+static void __exit mxr_exit(void)
+{
+	platform_driver_unregister(&mxr_driver);
+}
+module_exit(mxr_exit);
diff --git a/drivers/media/video/exynos/tv/mixer_grp_layer.c b/drivers/media/video/exynos/tv/mixer_grp_layer.c
new file mode 100644
index 0000000..447e0e3
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_grp_layer.c
@@ -0,0 +1,186 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include "mixer.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+/* FORMAT DEFINITIONS */
+
+static const struct mxr_format mxr_fb_fmt_rgb565 = {
+	.name = "RGB565",
+	.fourcc = V4L2_PIX_FMT_RGB565,
+	.colorspace = V4L2_COLORSPACE_SRGB,
+	.num_planes = 1,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 2 },
+	},
+	.num_subframes = 1,
+	.cookie = 4,
+};
+
+static const struct mxr_format mxr_fb_fmt_argb1555 = {
+	.name = "ARGB1555",
+	.num_planes = 1,
+	.fourcc = V4L2_PIX_FMT_RGB555,
+	.colorspace = V4L2_COLORSPACE_SRGB,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 2 },
+	},
+	.num_subframes = 1,
+	.cookie = 5,
+};
+
+static const struct mxr_format mxr_fb_fmt_argb4444 = {
+	.name = "ARGB4444",
+	.num_planes = 1,
+	.fourcc = V4L2_PIX_FMT_RGB444,
+	.colorspace = V4L2_COLORSPACE_SRGB,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 2 },
+	},
+	.num_subframes = 1,
+	.cookie = 6,
+};
+
+static const struct mxr_format mxr_fb_fmt_argb8888 = {
+	.name = "ARGB8888",
+	.fourcc = V4L2_PIX_FMT_BGR32,
+	.colorspace = V4L2_COLORSPACE_SRGB,
+	.num_planes = 1,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 4 },
+	},
+	.num_subframes = 1,
+	.cookie = 7,
+};
+
+static const struct mxr_format *mxr_graph_format[] = {
+	&mxr_fb_fmt_rgb565,
+	&mxr_fb_fmt_argb1555,
+	&mxr_fb_fmt_argb4444,
+	&mxr_fb_fmt_argb8888,
+};
+
+/* AUXILIARY CALLBACKS */
+
+static void mxr_graph_layer_release(struct mxr_layer *layer)
+{
+	mxr_base_layer_unregister(layer);
+	mxr_base_layer_release(layer);
+}
+
+static void mxr_graph_buffer_set(struct mxr_layer *layer,
+	struct mxr_buffer *buf)
+{
+	struct mxr_device *mdev = layer->mdev;
+	dma_addr_t addr = 0;
+
+	if (buf)
+		addr = mdev->vb2->plane_addr(&buf->vb, 0);
+	mxr_reg_graph_buffer(layer->mdev, layer->idx, addr);
+}
+
+static void mxr_graph_stream_set(struct mxr_layer *layer, int en)
+{
+	mxr_reg_graph_layer_stream(layer->mdev, layer->idx, en);
+}
+
+static void mxr_graph_format_set(struct mxr_layer *layer)
+{
+	mxr_reg_graph_format(layer->mdev, layer->idx,
+			layer->fmt, &layer->geo);
+}
+
+static void mxr_graph_fix_geometry(struct mxr_layer *layer)
+{
+	struct mxr_geometry *geo = &layer->geo;
+
+	mxr_dbg(layer->mdev, "%s start\n", __func__);
+	/* limit to boundary size */
+	geo->src.full_width = clamp_val(geo->src.full_width, 1, 32767);
+	geo->src.full_height = clamp_val(geo->src.full_height, 1, 2047);
+
+	/* limit to coordinate of source x, y */
+	geo->src.x_offset = clamp_val(geo->src.x_offset, 0,
+			geo->src.full_width - 1);
+	geo->src.y_offset = clamp_val(geo->src.y_offset, 0,
+			geo->src.full_height - 1);
+
+	/* limit to boundary size of crop width, height */
+	geo->src.width = clamp_val(geo->src.width, 1,
+			geo->src.full_width - geo->src.x_offset);
+	geo->src.height = clamp_val(geo->src.height, 1,
+			geo->src.full_height - geo->src.y_offset);
+
+	/* dst full resolution and TV display size are same */
+
+	geo->dst.x_offset = clamp_val(geo->dst.x_offset, 0,
+			geo->dst.full_width - 1);
+	geo->dst.y_offset = clamp_val(geo->dst.y_offset, 0,
+			geo->dst.full_height - 1);
+
+	/* mixer scale-up is unuseful. so no use it */
+	geo->dst.width = clamp_val(geo->src.width, 1,
+			geo->dst.full_width - geo->dst.x_offset);
+	geo->dst.height = clamp_val(geo->src.height, 1,
+			geo->dst.full_height - geo->dst.y_offset);
+}
+
+/* PUBLIC API */
+
+struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int cur_mxr,
+		int idx, int nr)
+{
+	struct mxr_layer *layer;
+	int ret;
+	struct mxr_layer_ops ops = {
+		.release = mxr_graph_layer_release,
+		.buffer_set = mxr_graph_buffer_set,
+		.stream_set = mxr_graph_stream_set,
+		.format_set = mxr_graph_format_set,
+		.fix_geometry = mxr_graph_fix_geometry,
+	};
+	char name[32];
+
+	sprintf(name, "mxr%d_graph%d", cur_mxr, idx);
+
+	layer = mxr_base_layer_create(mdev, idx, name, &ops);
+	if (layer == NULL) {
+		mxr_err(mdev, "failed to initialize layer(%d) base\n", idx);
+		goto fail;
+	}
+
+	layer->fmt_array = mxr_graph_format;
+	layer->fmt_array_size = ARRAY_SIZE(mxr_graph_format);
+	layer->minor = nr;
+	layer->type = MXR_LAYER_TYPE_GRP;
+
+	ret = mxr_base_layer_register(layer);
+	if (ret)
+		goto fail_layer;
+
+	layer->cur_mxr = cur_mxr;
+	return layer;
+
+fail_layer:
+	mxr_base_layer_release(layer);
+
+fail:
+	return NULL;
+}
+
diff --git a/drivers/media/video/exynos/tv/mixer_reg.c b/drivers/media/video/exynos/tv/mixer_reg.c
new file mode 100644
index 0000000..6d9851a
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_reg.c
@@ -0,0 +1,960 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include "mixer.h"
+#include "regs-mixer.h"
+#include "regs-vp.h"
+
+#include <plat/cpu.h>
+#include <linux/delay.h>
+
+/* Register access subroutines */
+
+static inline u32 vp_read(struct mxr_device *mdev, u32 reg_id)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	return readl(mdev->res.vp_regs + reg_id);
+#else
+	return 0;
+#endif
+}
+
+static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	writel(val, mdev->res.vp_regs + reg_id);
+#endif
+}
+
+static inline void vp_write_mask(struct mxr_device *mdev, u32 reg_id,
+	u32 val, u32 mask)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	u32 old = vp_read(mdev, reg_id);
+
+	val = (val & mask) | (old & ~mask);
+	writel(val, mdev->res.vp_regs + reg_id);
+#endif
+}
+
+static inline u32 mxr_read(struct mxr_device *mdev, u32 reg_id)
+{
+	return readl(mdev->res.mxr_regs + reg_id);
+}
+
+static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val)
+{
+	writel(val, mdev->res.mxr_regs + reg_id);
+}
+
+static inline void mxr_write_mask(struct mxr_device *mdev, u32 reg_id,
+	u32 val, u32 mask)
+{
+	u32 old = mxr_read(mdev, reg_id);
+
+	val = (val & mask) | (old & ~mask);
+	writel(val, mdev->res.mxr_regs + reg_id);
+}
+
+void mxr_layer_sync(struct mxr_device *mdev, int en)
+{
+	mxr_write_mask(mdev, MXR_STATUS, en ? MXR_STATUS_LAYER_SYNC : 0,
+		MXR_STATUS_LAYER_SYNC);
+}
+
+void mxr_vsync_set_update(struct mxr_device *mdev, int en)
+{
+	/* block update on vsync */
+	mxr_write_mask(mdev, MXR_STATUS, en ? MXR_STATUS_SYNC_ENABLE : 0,
+		MXR_STATUS_SYNC_ENABLE);
+#if defined(CONFIG_ARCH_EXYNOS4)
+	vp_write(mdev, VP_SHADOW_UPDATE, en ? VP_SHADOW_UPDATE_ENABLE : 0);
+#endif
+}
+
+static void __mxr_reg_vp_reset(struct mxr_device *mdev)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	int tries = 100;
+
+	vp_write(mdev, VP_SRESET, VP_SRESET_PROCESSING);
+	for (tries = 100; tries; --tries) {
+		/* waiting until VP_SRESET_PROCESSING is 0 */
+		if (~vp_read(mdev, VP_SRESET) & VP_SRESET_PROCESSING)
+			break;
+		mdelay(10);
+	}
+	WARN(tries == 0, "failed to reset Video Processor\n");
+#endif
+}
+
+static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
+{
+	u32 val; /* value stored to register */
+
+	if (mxr_num == MXR_SUB_MIXER0) {
+		/* use dark gray background color */
+		mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
+		mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
+		mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
+
+		/* setting graphical layers */
+
+		val  = MXR_GRP_CFG_BLANK_KEY_OFF; /* no blank key */
+		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
+
+		/* the same configuration for both layers */
+		mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
+		mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
+	} else if (mxr_num == MXR_SUB_MIXER1) {
+		val  = MXR_LAYER_CFG_GRP1_VAL(3);
+		val |= MXR_LAYER_CFG_GRP0_VAL(2);
+		val |= MXR_LAYER_CFG_VP_VAL(1);
+		mxr_write(mdev, MXR1_LAYER_CFG, val);
+
+		/* use dark gray background color */
+		mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
+		mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
+		mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);
+
+		/* setting graphical layers */
+
+		val  = MXR_GRP_CFG_BLANK_KEY_OFF; /* no blank key */
+		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
+
+		/* the same configuration for both layers */
+		mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
+		mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
+	}
+}
+
+static void mxr_reg_vp_default_filter(struct mxr_device *mdev);
+
+void mxr_reg_reset(struct mxr_device *mdev)
+{
+	int i;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+
+	mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	/* set output in RGB888 mode */
+	mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
+
+	/* 16 beat burst in DMA */
+	mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
+		MXR_STATUS_BURST_MASK);
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i)
+		mxr_reg_sub_mxr_reset(mdev, i);
+
+	/* configuration of Video Processor Registers */
+	__mxr_reg_vp_reset(mdev);
+	mxr_reg_vp_default_filter(mdev);
+
+	/* enable all interrupts */
+	mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
+	const struct mxr_format *fmt, const struct mxr_geometry *geo)
+{
+	u32 wh, sxy, dxy;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	/* Mostly, src width, height and dst width, height are same.
+	 * However, in case of doing src and dst cropping, those are different.
+	 * So you have to write dst width and height to MXR_GRAPHIC_WH register.
+	 */
+	wh  = MXR_GRP_WH_WIDTH(geo->dst.width);
+	wh |= MXR_GRP_WH_HEIGHT(geo->dst.height);
+	wh |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
+	wh |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
+
+	/* setup offsets in source image */
+	sxy  = MXR_GRP_SXY_SX(geo->src.x_offset);
+	sxy |= MXR_GRP_SXY_SY(geo->src.y_offset);
+
+	/* setup offsets in display image */
+	dxy  = MXR_GRP_DXY_DX(geo->dst.x_offset);
+	dxy |= MXR_GRP_DXY_DY(geo->dst.y_offset);
+
+	if (idx == 0) {
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0),
+				MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
+				MXR_GRP_CFG_FORMAT_MASK);
+		mxr_write(mdev, MXR_GRAPHIC_SPAN(0), geo->src.full_width);
+		mxr_write(mdev, MXR_GRAPHIC_WH(0), wh);
+		mxr_write(mdev, MXR_GRAPHIC_SXY(0), sxy);
+		mxr_write(mdev, MXR_GRAPHIC_DXY(0), dxy);
+	} else if (idx == 1) {
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1),
+				MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
+				MXR_GRP_CFG_FORMAT_MASK);
+		mxr_write(mdev, MXR_GRAPHIC_SPAN(1), geo->src.full_width);
+		mxr_write(mdev, MXR_GRAPHIC_WH(1), wh);
+		mxr_write(mdev, MXR_GRAPHIC_SXY(1), sxy);
+		mxr_write(mdev, MXR_GRAPHIC_DXY(1), dxy);
+	} else if (idx == 2) {
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0),
+				MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
+				MXR_GRP_CFG_FORMAT_MASK);
+		mxr_write(mdev, MXR1_GRAPHIC_SPAN(0), geo->src.full_width);
+		mxr_write(mdev, MXR1_GRAPHIC_WH(0), wh);
+		mxr_write(mdev, MXR1_GRAPHIC_SXY(0), sxy);
+		mxr_write(mdev, MXR1_GRAPHIC_DXY(0), dxy);
+	} else if (idx == 3) {
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1),
+				MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
+				MXR_GRP_CFG_FORMAT_MASK);
+		mxr_write(mdev, MXR1_GRAPHIC_SPAN(1), geo->src.full_width);
+		mxr_write(mdev, MXR1_GRAPHIC_WH(1), wh);
+		mxr_write(mdev, MXR1_GRAPHIC_SXY(1), sxy);
+		mxr_write(mdev, MXR1_GRAPHIC_DXY(1), dxy);
+	}
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_video_geo(struct mxr_device *mdev, int cur_mxr, int idx,
+		const struct mxr_geometry *geo)
+{
+	u32 lt, rb;
+	unsigned long flags;
+
+	mxr_dbg(mdev, "%s\n", __func__);
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	lt  = MXR_VIDEO_LT_LEFT_VAL(geo->dst.x_offset);
+	lt |= MXR_VIDEO_LT_TOP_VAL(geo->dst.y_offset);
+	rb  = MXR_VIDEO_RB_RIGHT_VAL(geo->dst.x_offset + geo->dst.width - 1);
+	rb |= MXR_VIDEO_RB_BOTTOM_VAL(geo->dst.y_offset + geo->dst.height - 1);
+
+	if (cur_mxr == MXR_SUB_MIXER0) {
+		mxr_write(mdev, MXR_VIDEO_LT, lt);
+		mxr_write(mdev, MXR_VIDEO_RB, rb);
+	} else if (cur_mxr == MXR_SUB_MIXER1) {
+		mxr_write(mdev, MXR1_VIDEO_LT, lt);
+		mxr_write(mdev, MXR1_VIDEO_RB, rb);
+	}
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+
+	mxr_dbg(mdev, "destination x = %d, y = %d, width = %d, height = %d\n",
+			geo->dst.x_offset, geo->dst.y_offset,
+			geo->dst.width, geo->dst.height);
+}
+
+void mxr_reg_vp_format(struct mxr_device *mdev,
+	const struct mxr_format *fmt, const struct mxr_geometry *geo)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	vp_write_mask(mdev, VP_MODE, fmt->cookie, VP_MODE_FMT_MASK);
+
+	/* setting size of input image */
+	vp_write(mdev, VP_IMG_SIZE_Y, VP_IMG_HSIZE(geo->src.full_width) |
+		VP_IMG_VSIZE(geo->src.full_height));
+	/* chroma height has to reduced by 2 to avoid chroma distorions */
+	vp_write(mdev, VP_IMG_SIZE_C, VP_IMG_HSIZE(geo->src.full_width) |
+		VP_IMG_VSIZE(geo->src.full_height / 2));
+
+	vp_write(mdev, VP_SRC_WIDTH, geo->src.width);
+	vp_write(mdev, VP_SRC_HEIGHT, geo->src.height);
+	vp_write(mdev, VP_SRC_H_POSITION,
+		VP_SRC_H_POSITION_VAL(geo->src.x_offset));
+	vp_write(mdev, VP_SRC_V_POSITION, geo->src.y_offset);
+
+	vp_write(mdev, VP_DST_WIDTH, geo->dst.width);
+	vp_write(mdev, VP_DST_H_POSITION, geo->dst.x_offset);
+	if (geo->dst.field == V4L2_FIELD_INTERLACED) {
+		vp_write(mdev, VP_DST_HEIGHT, geo->dst.height / 2);
+		vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset / 2);
+	} else {
+		vp_write(mdev, VP_DST_HEIGHT, geo->dst.height);
+		vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset);
+	}
+
+	vp_write(mdev, VP_H_RATIO, geo->x_ratio);
+	vp_write(mdev, VP_V_RATIO, geo->y_ratio);
+
+	vp_write(mdev, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+#endif
+}
+
+void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr)
+{
+	u32 val = addr ? ~0 : 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (idx == 0) {
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
+		mxr_write(mdev, MXR_GRAPHIC_BASE(0), addr);
+	} else if (idx == 1) {
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
+		mxr_write(mdev, MXR_GRAPHIC_BASE(1), addr);
+	} else if (idx == 2) {
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP0_ENABLE);
+		mxr_write(mdev, MXR1_GRAPHIC_BASE(0), addr);
+	} else if (idx == 3) {
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP1_ENABLE);
+		mxr_write(mdev, MXR1_GRAPHIC_BASE(1), addr);
+	}
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_vp_buffer(struct mxr_device *mdev,
+	dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2])
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	u32 val = luma_addr[0] ? ~0 : 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VIDEO_ENABLE);
+	vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON);
+	/* TODO: fix tiled mode */
+	vp_write(mdev, VP_TOP_Y_PTR, luma_addr[0]);
+	vp_write(mdev, VP_TOP_C_PTR, chroma_addr[0]);
+	vp_write(mdev, VP_BOT_Y_PTR, luma_addr[1]);
+	vp_write(mdev, VP_BOT_C_PTR, chroma_addr[1]);
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+#endif
+}
+
+void mxr_reg_set_layer_prio(struct mxr_device *mdev)
+{
+	u8 p_g0, p_g1, p_v;
+	u32 val;
+
+	p_v = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_VIDEO]->prio;
+	p_g0 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP0]->prio;
+	p_g1 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP1]->prio;
+	mxr_dbg(mdev, "video layer priority = %d\n", p_v);
+	mxr_dbg(mdev, "graphic0 layer priority = %d\n", p_g0);
+	mxr_dbg(mdev, "graphic1 layer priority = %d\n", p_g1);
+
+	val  = MXR_LAYER_CFG_GRP1_VAL(p_g1);
+	val |= MXR_LAYER_CFG_GRP0_VAL(p_g0);
+	val |= MXR_LAYER_CFG_VP_VAL(p_v);
+	mxr_write(mdev, MXR_LAYER_CFG, val);
+}
+
+void mxr_reg_set_layer_blend(struct mxr_device *mdev, int sub_mxr, int num,
+		int en)
+{
+	u32 val = en ? ~0 : 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_VIDEO)
+		mxr_write_mask(mdev, MXR_VIDEO_CFG, val,
+				MXR_VIDEO_CFG_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_LAYER_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_LAYER_BLEND_EN);
+#if defined(CONFIG_ARCH_EXYNOS5)
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_VIDEO)
+		mxr_write_mask(mdev, MXR1_VIDEO_CFG, val,
+				MXR_VIDEO_CFG_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_LAYER_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_LAYER_BLEND_EN);
+#endif
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_layer_alpha(struct mxr_device *mdev, int sub_mxr, int num, u32 a)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_VIDEO)
+		mxr_write_mask(mdev, MXR_VIDEO_CFG, MXR_VIDEO_CFG_ALPHA(a),
+				0xff);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), MXR_GRP_CFG_ALPHA_VAL(a),
+				0xff);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), MXR_GRP_CFG_ALPHA_VAL(a),
+				0xff);
+#if defined(CONFIG_ARCH_EXYNOS5)
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_VIDEO)
+		mxr_write_mask(mdev, MXR1_VIDEO_CFG, MXR_VIDEO_CFG_ALPHA(a),
+				0xff);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), MXR_GRP_CFG_ALPHA_VAL(a),
+				0xff);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), MXR_GRP_CFG_ALPHA_VAL(a),
+				0xff);
+#endif
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_set_pixel_blend(struct mxr_device *mdev, int sub_mxr, int num,
+		int en)
+{
+	u32 val = en ? ~0 : 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_PIXEL_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_PIXEL_BLEND_EN);
+#if defined(CONFIG_ARCH_EXYNOS5)
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_PIXEL_BLEND_EN);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_PIXEL_BLEND_EN);
+#endif
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_set_colorkey(struct mxr_device *mdev, int sub_mxr, int num, int en)
+{
+	u32 val = en ? ~0 : 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_BLANK_KEY_OFF);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_BLANK_KEY_OFF);
+#if defined(CONFIG_ARCH_EXYNOS5)
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), val,
+				MXR_GRP_CFG_BLANK_KEY_OFF);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
+		mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), val,
+				MXR_GRP_CFG_BLANK_KEY_OFF);
+#endif
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_colorkey_val(struct mxr_device *mdev, int sub_mxr, int num, u32 v)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
+		mxr_write(mdev, MXR_GRAPHIC_BLANK(0), v);
+	else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
+		mxr_write(mdev, MXR_GRAPHIC_BLANK(1), v);
+#if defined(CONFIG_ARCH_EXYNOS5)
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
+		mxr_write(mdev, MXR1_GRAPHIC_BLANK(0), v);
+	else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
+		mxr_write(mdev, MXR1_GRAPHIC_BLANK(1), v);
+#endif
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+static void mxr_irq_layer_handle(struct mxr_layer *layer)
+{
+	struct list_head *head = &layer->enq_list;
+	struct mxr_pipeline *pipe = &layer->pipe;
+	struct mxr_buffer *done;
+
+	/* skip non-existing layer */
+	if (layer == NULL)
+		return;
+
+	spin_lock(&layer->enq_slock);
+	if (pipe->state == MXR_PIPELINE_IDLE)
+		goto done;
+
+	done = layer->shadow_buf;
+	layer->shadow_buf = layer->update_buf;
+
+	if (list_empty(head)) {
+		if (pipe->state != MXR_PIPELINE_STREAMING)
+			layer->update_buf = NULL;
+	} else {
+		struct mxr_buffer *next;
+		next = list_first_entry(head, struct mxr_buffer, list);
+		list_del(&next->list);
+		layer->update_buf = next;
+	}
+
+	layer->ops.buffer_set(layer, layer->update_buf);
+
+	if (done && done != layer->shadow_buf)
+		vb2_buffer_done(&done->vb, VB2_BUF_STATE_DONE);
+
+done:
+	spin_unlock(&layer->enq_slock);
+}
+
+u32 mxr_irq_underrun_handle(struct mxr_device *mdev, u32 val)
+{
+	if (val & MXR_INT_STATUS_MX0_VIDEO) {
+		mxr_dbg(mdev, "mixer0 video layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX0_VIDEO;
+	} else if (val & MXR_INT_STATUS_MX0_GRP0) {
+		mxr_dbg(mdev, "mixer0 graphic0 layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX0_GRP0;
+	} else if (val & MXR_INT_STATUS_MX0_GRP1) {
+		mxr_dbg(mdev, "mixer0 graphic1 layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX0_GRP1;
+	} else if (val & MXR_INT_STATUS_MX1_VIDEO) {
+		mxr_dbg(mdev, "mixer1 video layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX1_VIDEO;
+	} else if (val & MXR_INT_STATUS_MX1_GRP0) {
+		mxr_dbg(mdev, "mixer1 graphic0 layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX1_GRP0;
+	} else if (val & MXR_INT_STATUS_MX1_GRP1) {
+		mxr_dbg(mdev, "mixer1 graphic1 layer underrun occur\n");
+		val |= MXR_INT_STATUS_MX1_GRP1;
+	}
+
+	return val;
+}
+
+irqreturn_t mxr_irq_handler(int irq, void *dev_data)
+{
+	struct mxr_device *mdev = dev_data;
+	u32 i, val;
+
+	spin_lock(&mdev->reg_slock);
+	val = mxr_read(mdev, MXR_INT_STATUS);
+
+	/* wake up process waiting for VSYNC */
+	if (val & MXR_INT_STATUS_VSYNC) {
+		set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
+		wake_up(&mdev->event_queue);
+	}
+
+	/* clear interrupts.
+	   vsync is updated after write MXR_CFG_LAYER_UPDATE bit */
+	if (val & MXR_INT_CLEAR_VSYNC)
+		mxr_write_mask(mdev, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
+
+	val = mxr_irq_underrun_handle(mdev, val);
+	mxr_write(mdev, MXR_INT_STATUS, val);
+
+	spin_unlock(&mdev->reg_slock);
+	/* leave on non-vsync event */
+	if (~val & MXR_INT_CLEAR_VSYNC)
+		return IRQ_HANDLED;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+#if defined(CONFIG_ARCH_EXYNOS4)
+		mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_VIDEO]);
+#endif
+		mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_GRP0]);
+		mxr_irq_layer_handle(mdev->sub_mxr[i].layer[MXR_LAYER_GRP1]);
+	}
+
+	if (test_bit(MXR_EVENT_VSYNC, &mdev->event_flags)) {
+		spin_lock(&mdev->reg_slock);
+		mxr_write_mask(mdev, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
+		spin_unlock(&mdev->reg_slock);
+	}
+
+	return IRQ_HANDLED;
+}
+
+void mxr_reg_s_output(struct mxr_device *mdev, int cookie)
+{
+	u32 val;
+
+	val = cookie == 0 ? MXR_CFG_DST_SDO : MXR_CFG_DST_HDMI;
+	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK);
+}
+
+void mxr_reg_streamon(struct mxr_device *mdev)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	/* single write -> no need to block vsync update */
+
+	/* start MIXER */
+	mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
+
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_streamoff(struct mxr_device *mdev)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	/* single write -> no need to block vsync update */
+
+	/* stop MIXER */
+	mxr_write_mask(mdev, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
+
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+int mxr_reg_wait4vsync(struct mxr_device *mdev)
+{
+	int ret;
+
+	clear_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
+	/* TODO: consider adding interruptible */
+	ret = wait_event_timeout(mdev->event_queue,
+		test_bit(MXR_EVENT_VSYNC, &mdev->event_flags),
+		msecs_to_jiffies(1000));
+	if (ret > 0)
+		return 0;
+	if (ret < 0)
+		return ret;
+	mxr_warn(mdev, "no vsync detected - timeout\n");
+	return -ETIME;
+}
+
+void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
+	struct v4l2_mbus_framefmt *fmt)
+{
+	u32 val = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	/* choosing between YUV444 and RGB888 as mixer output type */
+	if (mdev->sub_mxr[MXR_SUB_MIXER0].mbus_fmt[MXR_PAD_SOURCE_GRP0].code ==
+		V4L2_MBUS_FMT_YUV8_1X24) {
+		val = MXR_CFG_OUT_YUV444;
+		fmt->code = V4L2_MBUS_FMT_YUV8_1X24;
+	} else {
+		val = MXR_CFG_OUT_RGB888;
+		fmt->code = V4L2_MBUS_FMT_XRGB8888_4X8_LE;
+	}
+
+	/* choosing between interlace and progressive mode */
+	if (fmt->field == V4L2_FIELD_INTERLACED)
+		val |= MXR_CFG_SCAN_INTERLACE;
+	else
+		val |= MXR_CFG_SCAN_PROGRASSIVE;
+
+	/* choosing between porper HD and SD mode */
+	if (fmt->height == 480)
+		val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
+	else if (fmt->height == 576)
+		val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
+	else if (fmt->height == 720)
+		val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
+	else if (fmt->height == 1080)
+		val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
+	else
+		WARN(1, "unrecognized mbus height %u!\n", fmt->height);
+
+	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
+			MXR_CFG_OUT_MASK);
+
+	val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
+	vp_write_mask(mdev, VP_MODE, val,
+		VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING);
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_local_path_clear(struct mxr_device *mdev)
+{
+	u32 val;
+
+	val = readl(SYSREG_DISP1BLK_CFG);
+	val &= ~(DISP1BLK_CFG_MIXER0_VALID | DISP1BLK_CFG_MIXER1_VALID);
+	writel(val, SYSREG_DISP1BLK_CFG);
+	mxr_dbg(mdev, "SYSREG_DISP1BLK_CFG = 0x%x\n", readl(SYSREG_DISP1BLK_CFG));
+}
+
+void mxr_reg_local_path_set(struct mxr_device *mdev, int mxr0_gsc, int mxr1_gsc,
+		u32 flags)
+{
+	u32 val = 0;
+	int mxr0_local = mdev->sub_mxr[MXR_SUB_MIXER0].local;
+	int mxr1_local = mdev->sub_mxr[MXR_SUB_MIXER1].local;
+
+	if (mxr0_local && !mxr1_local) { /* 1-path : sub-mixer0 */
+		val  = MXR_TVOUT_CFG_ONE_PATH;
+		val |= MXR_TVOUT_CFG_PATH_MIXER0;
+	} else if (!mxr0_local && mxr1_local) { /* 1-path : sub-mixer1 */
+		val  = MXR_TVOUT_CFG_ONE_PATH;
+		val |= MXR_TVOUT_CFG_PATH_MIXER1;
+	} else if (mxr0_local && mxr1_local) { /* 2-path */
+		val  = MXR_TVOUT_CFG_TWO_PATH;
+		val |= MXR_TVOUT_CFG_STEREO_SCOPIC;
+	}
+
+	mxr_write(mdev, MXR_TVOUT_CFG, val);
+
+	/* set local path gscaler to mixer */
+	val = readl(SYSREG_DISP1BLK_CFG);
+	val |= DISP1BLK_CFG_FIFORST_DISP1;
+	val &= ~DISP1BLK_CFG_MIXER_MASK;
+	if (flags & MEDIA_LNK_FL_ENABLED) {
+		if (mxr0_local) {
+			val |= DISP1BLK_CFG_MIXER0_VALID;
+			val |= DISP1BLK_CFG_MIXER0_SRC_GSC(mxr0_gsc);
+		}
+		if (mxr1_local) {
+			val |= DISP1BLK_CFG_MIXER1_VALID;
+			val |= DISP1BLK_CFG_MIXER1_SRC_GSC(mxr1_gsc);
+		}
+	}
+	mxr_dbg(mdev, "%s: SYSREG value = 0x%x\n", __func__, val);
+	writel(val, SYSREG_DISP1BLK_CFG);
+}
+
+void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en)
+{
+	u32 val = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&mdev->reg_slock, flags);
+	mxr_vsync_set_update(mdev, MXR_DISABLE);
+
+	if (mdev->frame_packing) {
+		val  = MXR_TVOUT_CFG_TWO_PATH;
+		val |= MXR_TVOUT_CFG_STEREO_SCOPIC;
+	} else {
+		val  = MXR_TVOUT_CFG_ONE_PATH;
+		val |= MXR_TVOUT_CFG_PATH_MIXER0;
+	}
+
+	mxr_write(mdev, MXR_TVOUT_CFG, val);
+
+	mxr_vsync_set_update(mdev, MXR_ENABLE);
+	spin_unlock_irqrestore(&mdev->reg_slock, flags);
+}
+
+void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en)
+{
+	/* no extra actions need to be done */
+}
+
+void mxr_reg_video_layer_stream(struct mxr_device *mdev, int idx, int en)
+{
+	u32 val = en ? ~0 : 0;
+
+	if (idx == 0)
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VIDEO_ENABLE);
+	else if (idx == 1)
+		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_VIDEO_ENABLE);
+}
+
+static const u8 filter_y_horiz_tap8[] = {
+	0,	-1,	-1,	-1,	-1,	-1,	-1,	-1,
+	-1,	-1,	-1,	-1,	-1,	0,	0,	0,
+	0,	2,	4,	5,	6,	6,	6,	6,
+	6,	5,	5,	4,	3,	2,	1,	1,
+	0,	-6,	-12,	-16,	-18,	-20,	-21,	-20,
+	-20,	-18,	-16,	-13,	-10,	-8,	-5,	-2,
+	127,	126,	125,	121,	114,	107,	99,	89,
+	79,	68,	57,	46,	35,	25,	16,	8,
+};
+
+static const u8 filter_y_vert_tap4[] = {
+	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
+	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
+	127,	126,	124,	118,	111,	102,	92,	81,
+	70,	59,	48,	37,	27,	19,	11,	5,
+	0,	5,	11,	19,	27,	37,	48,	59,
+	70,	81,	92,	102,	111,	118,	124,	126,
+	0,	0,	-1,	-1,	-2,	-3,	-4,	-5,
+	-6,	-7,	-8,	-8,	-8,	-8,	-6,	-3,
+};
+
+static const u8 filter_cr_horiz_tap4[] = {
+	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
+	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
+	127,	126,	124,	118,	111,	102,	92,	81,
+	70,	59,	48,	37,	27,	19,	11,	5,
+};
+
+static inline void mxr_reg_vp_filter_set(struct mxr_device *mdev,
+	int reg_id, const u8 *data, unsigned int size)
+{
+	/* assure 4-byte align */
+	BUG_ON(size & 3);
+	for (; size; size -= 4, reg_id += 4, data += 4) {
+		u32 val = (data[0] << 24) |  (data[1] << 16) |
+			(data[2] << 8) | data[3];
+		vp_write(mdev, reg_id, val);
+	}
+}
+
+static void mxr_reg_vp_default_filter(struct mxr_device *mdev)
+{
+#if defined(CONFIG_ARCH_EXYNOS4)
+	mxr_reg_vp_filter_set(mdev, VP_POLY8_Y0_LL,
+		filter_y_horiz_tap8, sizeof filter_y_horiz_tap8);
+	mxr_reg_vp_filter_set(mdev, VP_POLY4_Y0_LL,
+		filter_y_vert_tap4, sizeof filter_y_vert_tap4);
+	mxr_reg_vp_filter_set(mdev, VP_POLY4_C0_LL,
+		filter_cr_horiz_tap4, sizeof filter_cr_horiz_tap4);
+#endif
+}
+
+static void mxr_reg_mxr_dump(struct mxr_device *mdev)
+{
+#define DUMPREG(reg_id) \
+do { \
+	mxr_dbg(mdev, #reg_id " = %08x\n", \
+		(u32)readl(mdev->res.mxr_regs + reg_id)); \
+} while (0)
+
+	DUMPREG(MXR_STATUS);
+	DUMPREG(MXR_CFG);
+	DUMPREG(MXR_INT_EN);
+	DUMPREG(MXR_INT_STATUS);
+
+	DUMPREG(MXR_LAYER_CFG);
+	DUMPREG(MXR_VIDEO_CFG);
+
+	DUMPREG(MXR_GRAPHIC0_CFG);
+	DUMPREG(MXR_GRAPHIC0_BASE);
+	DUMPREG(MXR_GRAPHIC0_SPAN);
+	DUMPREG(MXR_GRAPHIC0_WH);
+	DUMPREG(MXR_GRAPHIC0_SXY);
+	DUMPREG(MXR_GRAPHIC0_DXY);
+
+	DUMPREG(MXR_GRAPHIC1_CFG);
+	DUMPREG(MXR_GRAPHIC1_BASE);
+	DUMPREG(MXR_GRAPHIC1_SPAN);
+	DUMPREG(MXR_GRAPHIC1_WH);
+	DUMPREG(MXR_GRAPHIC1_SXY);
+	DUMPREG(MXR_GRAPHIC1_DXY);
+
+	if (soc_is_exynos5250()) {
+		DUMPREG(MXR1_LAYER_CFG);
+		DUMPREG(MXR1_VIDEO_CFG);
+
+		DUMPREG(MXR1_GRAPHIC0_CFG);
+		DUMPREG(MXR1_GRAPHIC0_BASE);
+		DUMPREG(MXR1_GRAPHIC0_SPAN);
+		DUMPREG(MXR1_GRAPHIC0_WH);
+		DUMPREG(MXR1_GRAPHIC0_SXY);
+		DUMPREG(MXR1_GRAPHIC0_DXY);
+
+		DUMPREG(MXR1_GRAPHIC1_CFG);
+		DUMPREG(MXR1_GRAPHIC1_BASE);
+		DUMPREG(MXR1_GRAPHIC1_SPAN);
+		DUMPREG(MXR1_GRAPHIC1_WH);
+		DUMPREG(MXR1_GRAPHIC1_SXY);
+		DUMPREG(MXR1_GRAPHIC1_DXY);
+
+		DUMPREG(MXR_TVOUT_CFG);
+	}
+#undef DUMPREG
+}
+
+static void mxr_reg_vp_dump(struct mxr_device *mdev)
+{
+#define DUMPREG(reg_id) \
+do { \
+	mxr_dbg(mdev, #reg_id " = %08x\n", \
+		(u32) readl(mdev->res.vp_regs + reg_id)); \
+} while (0)
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+	DUMPREG(VP_ENABLE);
+	DUMPREG(VP_SRESET);
+	DUMPREG(VP_SHADOW_UPDATE);
+	DUMPREG(VP_FIELD_ID);
+	DUMPREG(VP_MODE);
+	DUMPREG(VP_IMG_SIZE_Y);
+	DUMPREG(VP_IMG_SIZE_C);
+	DUMPREG(VP_PER_RATE_CTRL);
+	DUMPREG(VP_TOP_Y_PTR);
+	DUMPREG(VP_BOT_Y_PTR);
+	DUMPREG(VP_TOP_C_PTR);
+	DUMPREG(VP_BOT_C_PTR);
+	DUMPREG(VP_ENDIAN_MODE);
+	DUMPREG(VP_SRC_H_POSITION);
+	DUMPREG(VP_SRC_V_POSITION);
+	DUMPREG(VP_SRC_WIDTH);
+	DUMPREG(VP_SRC_HEIGHT);
+	DUMPREG(VP_DST_H_POSITION);
+	DUMPREG(VP_DST_V_POSITION);
+	DUMPREG(VP_DST_WIDTH);
+	DUMPREG(VP_DST_HEIGHT);
+	DUMPREG(VP_H_RATIO);
+	DUMPREG(VP_V_RATIO);
+#endif
+
+#undef DUMPREG
+}
+
+void mxr_reg_dump(struct mxr_device *mdev)
+{
+	mxr_reg_mxr_dump(mdev);
+	mxr_reg_vp_dump(mdev);
+}
diff --git a/drivers/media/video/exynos/tv/mixer_vb2.c b/drivers/media/video/exynos/tv/mixer_vb2.c
new file mode 100644
index 0000000..c2d7ddf
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_vb2.c
@@ -0,0 +1,76 @@
+/* linux/drivers/media/video/exynos/tv/mixer_vb2.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Videobuf2 allocator operations file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/platform_device.h>
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+#include "mixer.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *mxr_cma_init(struct mxr_device *mdev)
+{
+	return vb2_cma_phys_init(mdev->dev, NULL, 0, false);
+}
+
+int mxr_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void mxr_cma_suspend(void *alloc_ctx){}
+void mxr_cma_set_cacheable(void *alloc_ctx, bool cacheable){}
+
+int mxr_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct mxr_vb2 mxr_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= mxr_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= mxr_cma_resume,
+	.suspend	= mxr_cma_suspend,
+	.cache_flush	= mxr_cma_cache_flush,
+	.set_cacheable	= mxr_cma_set_cacheable,
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *mxr_ion_init(struct mxr_device *mdev)
+{
+	return vb2_ion_create_context(mdev->dev, SZ_4K,
+		VB2ION_CTX_VMCONTIG | VB2ION_CTX_UNCACHED | VB2ION_CTX_IOMMU);
+}
+
+unsigned long mxr_ion_plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+
+const struct mxr_vb2 mxr_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= mxr_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= mxr_ion_plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+};
+#endif
diff --git a/drivers/media/video/exynos/tv/mixer_video.c b/drivers/media/video/exynos/tv/mixer_video.c
new file mode 100644
index 0000000..7b4c05e
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_video.c
@@ -0,0 +1,1216 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+#include "mixer.h"
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/mm.h>
+#include <linux/version.h>
+#include <linux/timer.h>
+
+#include <media/exynos_mc.h>
+#include <media/v4l2-ioctl.h>
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+int __devinit mxr_acquire_video(struct mxr_device *mdev,
+	struct mxr_output_conf *output_conf, int output_count)
+{
+	int i;
+	int ret = 0;
+	struct v4l2_subdev *sd;
+
+	mdev->alloc_ctx = mdev->vb2->init(mdev);
+	if (IS_ERR_OR_NULL(mdev->alloc_ctx)) {
+		mxr_err(mdev, "could not acquire vb2 allocator\n");
+		ret = PTR_ERR(mdev->alloc_ctx);
+		goto fail;
+	}
+
+	/* registering outputs */
+	mdev->output_cnt = 0;
+	for (i = 0; i < output_count; ++i) {
+		struct mxr_output_conf *conf = &output_conf[i];
+		struct mxr_output *out;
+
+		/* find subdev of output devices */
+		sd = (struct v4l2_subdev *)
+			module_name_to_driver_data(conf->module_name);
+		/* trying to register next output */
+		if (sd == NULL)
+			continue;
+		out = kzalloc(sizeof *out, GFP_KERNEL);
+		if (out == NULL) {
+			mxr_err(mdev, "no memory for '%s'\n",
+				conf->output_name);
+			ret = -ENOMEM;
+			/* registered subdevs are removed in fail_v4l2_dev */
+			goto fail_output;
+		}
+		strlcpy(out->name, conf->output_name, sizeof(out->name));
+		out->sd = sd;
+		out->cookie = conf->cookie;
+		mdev->output[mdev->output_cnt++] = out;
+		mxr_info(mdev, "added output '%s' from module '%s'\n",
+			conf->output_name, conf->module_name);
+		/* checking if maximal number of outputs is reached */
+		if (mdev->output_cnt >= MXR_MAX_OUTPUTS)
+			break;
+	}
+
+	if (mdev->output_cnt == 0) {
+		mxr_err(mdev, "failed to register any output\n");
+		ret = -ENODEV;
+		/* skipping fail_output because there is nothing to free */
+		goto fail_vb2_allocator;
+	}
+
+	return 0;
+
+fail_output:
+	/* kfree is NULL-safe */
+	for (i = 0; i < mdev->output_cnt; ++i)
+		kfree(mdev->output[i]);
+	memset(mdev->output, 0, sizeof mdev->output);
+
+fail_vb2_allocator:
+	/* freeing allocator context */
+	mdev->vb2->cleanup(mdev->alloc_ctx);
+
+fail:
+	return ret;
+}
+
+void __devexit mxr_release_video(struct mxr_device *mdev)
+{
+	int i;
+
+	/* kfree is NULL-safe */
+	for (i = 0; i < mdev->output_cnt; ++i)
+		kfree(mdev->output[i]);
+
+	mdev->vb2->cleanup(mdev->alloc_ctx);
+}
+
+static void tv_graph_pipeline_stream(struct mxr_pipeline *pipe, int on)
+{
+	struct mxr_device *mdev = pipe->layer->mdev;
+	struct media_entity *me = &pipe->layer->vfd.entity;
+	/* source pad of graphic layer entity */
+	struct media_pad *pad = &me->pads[0];
+	struct v4l2_subdev *sd;
+	struct exynos_entity_data md_data;
+
+	mxr_dbg(mdev, "%s TV graphic layer pipeline\n", on ? "start" : "stop");
+
+	/* find remote pad through enabled link */
+	pad = media_entity_remote_source(pad);
+	if (media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV
+			|| pad == NULL)
+		mxr_warn(mdev, "cannot find remote pad\n");
+
+	sd = media_entity_to_v4l2_subdev(pad->entity);
+	mxr_dbg(mdev, "s_stream of %s sub-device is called\n", sd->name);
+
+	md_data.mxr_data_from = FROM_MXR_VD;
+	v4l2_set_subdevdata(sd, &md_data);
+	v4l2_subdev_call(sd, video, s_stream, on);
+}
+
+static int mxr_querycap(struct file *file, void *priv,
+	struct v4l2_capability *cap)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+
+	strlcpy(cap->driver, MXR_DRIVER_NAME, sizeof cap->driver);
+	strlcpy(cap->card, layer->vfd.name, sizeof cap->card);
+	sprintf(cap->bus_info, "%d", layer->idx);
+	cap->version = KERNEL_VERSION(0, 1, 0);
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+
+	return 0;
+}
+
+/* Geometry handling */
+void mxr_layer_geo_fix(struct mxr_layer *layer)
+{
+	struct mxr_device *mdev = layer->mdev;
+	struct v4l2_mbus_framefmt mbus_fmt;
+
+	/* TODO: add some dirty flag to avoid unnecessary adjustments */
+	mxr_get_mbus_fmt(mdev, &mbus_fmt);
+	layer->geo.dst.full_width = mbus_fmt.width;
+	layer->geo.dst.full_height = mbus_fmt.height;
+	layer->geo.dst.field = mbus_fmt.field;
+	layer->ops.fix_geometry(layer);
+}
+
+void mxr_layer_default_geo(struct mxr_layer *layer)
+{
+	struct mxr_device *mdev = layer->mdev;
+	struct v4l2_mbus_framefmt mbus_fmt;
+
+	mxr_dbg(layer->mdev, "%s start\n", __func__);
+	memset(&layer->geo, 0, sizeof layer->geo);
+
+	mxr_get_mbus_fmt(mdev, &mbus_fmt);
+
+	layer->geo.dst.full_width = mbus_fmt.width;
+	layer->geo.dst.full_height = mbus_fmt.height;
+	layer->geo.dst.width = layer->geo.dst.full_width;
+	layer->geo.dst.height = layer->geo.dst.full_height;
+	layer->geo.dst.field = mbus_fmt.field;
+
+	layer->geo.src.full_width = mbus_fmt.width;
+	layer->geo.src.full_height = mbus_fmt.height;
+	layer->geo.src.width = layer->geo.src.full_width;
+	layer->geo.src.height = layer->geo.src.full_height;
+
+	layer->ops.fix_geometry(layer);
+}
+
+static void mxr_geometry_dump(struct mxr_device *mdev, struct mxr_geometry *geo)
+{
+	mxr_dbg(mdev, "src.full_size = (%u, %u)\n",
+		geo->src.full_width, geo->src.full_height);
+	mxr_dbg(mdev, "src.size = (%u, %u)\n",
+		geo->src.width, geo->src.height);
+	mxr_dbg(mdev, "src.offset = (%u, %u)\n",
+		geo->src.x_offset, geo->src.y_offset);
+	mxr_dbg(mdev, "dst.full_size = (%u, %u)\n",
+		geo->dst.full_width, geo->dst.full_height);
+	mxr_dbg(mdev, "dst.size = (%u, %u)\n",
+		geo->dst.width, geo->dst.height);
+	mxr_dbg(mdev, "dst.offset = (%u, %u)\n",
+		geo->dst.x_offset, geo->dst.y_offset);
+	mxr_dbg(mdev, "ratio = (%u, %u)\n",
+		geo->x_ratio, geo->y_ratio);
+}
+
+static const struct mxr_format *find_format_by_index(
+	struct mxr_layer *layer, unsigned long index);
+
+static int mxr_enum_fmt(struct file *file, void  *priv,
+	struct v4l2_fmtdesc *f)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	const struct mxr_format *fmt;
+
+	mxr_dbg(mdev, "%s\n", __func__);
+	fmt = find_format_by_index(layer, f->index);
+	if (fmt == NULL)
+		return -EINVAL;
+
+	strlcpy(f->description, fmt->name, sizeof(f->description));
+	f->pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+static int mxr_s_fmt(struct file *file, void *priv,
+	struct v4l2_format *f)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	const struct mxr_format *fmt;
+	struct v4l2_pix_format_mplane *pix;
+	struct mxr_device *mdev = layer->mdev;
+	struct mxr_geometry *geo = &layer->geo;
+
+	mxr_dbg(mdev, "%s:%d\n", __func__, __LINE__);
+
+	pix = &f->fmt.pix_mp;
+	fmt = find_format_by_fourcc(layer, pix->pixelformat);
+	if (fmt == NULL) {
+		mxr_warn(mdev, "not recognized fourcc: %08x\n",
+			pix->pixelformat);
+		return -EINVAL;
+	}
+	layer->fmt = fmt;
+	geo->src.full_width = pix->width;
+	geo->src.width = pix->width;
+	geo->src.full_height = pix->height;
+	geo->src.height = pix->height;
+	/* assure consistency of geometry */
+	mxr_layer_geo_fix(layer);
+	mxr_dbg(mdev, "width=%u height=%u span=%u\n",
+		geo->src.width, geo->src.height, geo->src.full_width);
+
+	return 0;
+}
+
+static unsigned int divup(unsigned int divident, unsigned int divisor)
+{
+	return (divident + divisor - 1) / divisor;
+}
+
+unsigned long mxr_get_plane_size(const struct mxr_block *blk,
+	unsigned int width, unsigned int height)
+{
+	unsigned int bl_width = divup(width, blk->width);
+	unsigned int bl_height = divup(height, blk->height);
+
+	return bl_width * bl_height * blk->size;
+}
+
+static void mxr_mplane_fill(struct v4l2_plane_pix_format *planes,
+	const struct mxr_format *fmt, u32 width, u32 height)
+{
+	int i;
+
+	memset(planes, 0, sizeof(*planes) * fmt->num_subframes);
+	for (i = 0; i < fmt->num_planes; ++i) {
+		struct v4l2_plane_pix_format *plane = planes
+			+ fmt->plane2subframe[i];
+		const struct mxr_block *blk = &fmt->plane[i];
+		u32 bl_width = divup(width, blk->width);
+		u32 bl_height = divup(height, blk->height);
+		u32 sizeimage = bl_width * bl_height * blk->size;
+		u16 bytesperline = bl_width * blk->size / blk->height;
+
+		plane->sizeimage += sizeimage;
+		plane->bytesperline = max(plane->bytesperline, bytesperline);
+	}
+}
+
+static int mxr_g_fmt(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+
+	pix->width = layer->geo.src.full_width;
+	pix->height = layer->geo.src.full_height;
+	pix->field = V4L2_FIELD_NONE;
+	pix->pixelformat = layer->fmt->fourcc;
+	pix->colorspace = layer->fmt->colorspace;
+	mxr_mplane_fill(pix->plane_fmt, layer->fmt, pix->width, pix->height);
+
+	return 0;
+}
+
+static inline struct mxr_crop *choose_crop_by_type(struct mxr_geometry *geo,
+	enum v4l2_buf_type type)
+{
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
+		return &geo->dst;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		return &geo->src;
+	default:
+		return NULL;
+	}
+}
+
+static int mxr_g_crop(struct file *file, void *fh, struct v4l2_crop *a)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_crop *crop;
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	crop = choose_crop_by_type(&layer->geo, a->type);
+	if (crop == NULL)
+		return -EINVAL;
+	mxr_layer_geo_fix(layer);
+	a->c.left = crop->x_offset;
+	a->c.top = crop->y_offset;
+	a->c.width = crop->width;
+	a->c.height = crop->height;
+	return 0;
+}
+
+static int mxr_s_crop(struct file *file, void *fh, struct v4l2_crop *a)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_crop *crop;
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	crop = choose_crop_by_type(&layer->geo, a->type);
+	if (crop == NULL)
+		return -EINVAL;
+	crop->x_offset = a->c.left;
+	crop->y_offset = a->c.top;
+	crop->width = a->c.width;
+	crop->height = a->c.height;
+	mxr_layer_geo_fix(layer);
+	return 0;
+}
+
+static int mxr_cropcap(struct file *file, void *fh, struct v4l2_cropcap *a)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_crop *crop;
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	crop = choose_crop_by_type(&layer->geo, a->type);
+	if (crop == NULL)
+		return -EINVAL;
+	mxr_layer_geo_fix(layer);
+	a->bounds.left = 0;
+	a->bounds.top = 0;
+	a->bounds.width = crop->full_width;
+	a->bounds.top = crop->full_height;
+	a->defrect = a->bounds;
+	/* setting pixel aspect to 1/1 */
+	a->pixelaspect.numerator = 1;
+	a->pixelaspect.denominator = 1;
+	return 0;
+}
+
+static int mxr_check_ctrl_val(struct v4l2_control *ctrl)
+{
+	int ret = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_TV_LAYER_BLEND_ALPHA:
+	case V4L2_CID_TV_CHROMA_VALUE:
+		if (ctrl->value < 0 || ctrl->value > 256)
+			ret = -ERANGE;
+		break;
+	}
+
+	return ret;
+}
+
+static int mxr_s_ctrl(struct file *file, void *fh, struct v4l2_control *ctrl)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int v = ctrl->value;
+	int ret;
+
+	mxr_dbg(mdev, "%s start\n", __func__);
+
+	ret = mxr_check_ctrl_val(ctrl);
+	if (ret) {
+		mxr_err(mdev, "alpha value is out of range\n");
+		return ret;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_TV_LAYER_BLEND_ENABLE:
+		layer->layer_blend_en = v;
+		break;
+	case V4L2_CID_TV_LAYER_BLEND_ALPHA:
+		layer->layer_alpha = (u32)v;
+		break;
+	case V4L2_CID_TV_PIXEL_BLEND_ENABLE:
+		layer->pixel_blend_en = v;
+		break;
+	case V4L2_CID_TV_CHROMA_ENABLE:
+		layer->chroma_en = v;
+		break;
+	case V4L2_CID_TV_CHROMA_VALUE:
+		layer->chroma_val = (u32)v;
+		break;
+	case V4L2_CID_TV_HPD_STATUS:
+		v4l2_subdev_call(to_outsd(mdev), core, s_ctrl, ctrl);
+		break;
+	case V4L2_CID_TV_LAYER_PRIO:
+		layer->prio = (u8)v;
+		/* This can be turned on/off each layer while streaming */
+		if (layer->pipe.state == MXR_PIPELINE_STREAMING)
+			mxr_reg_set_layer_prio(mdev);
+		break;
+	case V4L2_CID_TV_SET_DVI_MODE:
+		v4l2_subdev_call(to_outsd(mdev), core, s_ctrl, ctrl);
+		break;
+	default:
+		mxr_err(mdev, "invalid control id\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int mxr_g_ctrl(struct file *file, void *fh, struct v4l2_control *ctrl)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int num = 0;
+	int ret = 0;
+
+	mxr_dbg(mdev, "%s start\n", __func__);
+
+	if (layer->type == MXR_LAYER_TYPE_VIDEO)
+		num = 0;
+	else if (layer->type == MXR_LAYER_TYPE_GRP && layer->idx == 0)
+		num = 1;
+	else if (layer->type == MXR_LAYER_TYPE_GRP && layer->idx == 1)
+		num = 2;
+
+	ret = mxr_check_ctrl_val(ctrl);
+
+	switch (ctrl->id) {
+	case V4L2_CID_TV_HPD_STATUS:
+		v4l2_subdev_call(to_outsd(mdev), core, g_ctrl, ctrl);
+		break;
+	default:
+		mxr_err(mdev, "invalid control id\n");
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static int mxr_enum_dv_presets(struct file *file, void *fh,
+	struct v4l2_dv_enum_preset *preset)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret;
+
+	/* lock protects from changing sd_out */
+	mutex_lock(&mdev->mutex);
+	ret = v4l2_subdev_call(to_outsd(mdev), video, enum_dv_presets, preset);
+	mutex_unlock(&mdev->mutex);
+
+	return ret ? -EINVAL : 0;
+}
+
+static int mxr_s_dv_preset(struct file *file, void *fh,
+	struct v4l2_dv_preset *preset)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret;
+
+	/* lock protects from changing sd_out */
+	mutex_lock(&mdev->mutex);
+
+	/* preset change cannot be done while there is an entity
+	 * dependant on output configuration
+	 */
+	if (mdev->n_output > 0) {
+		mutex_unlock(&mdev->mutex);
+		return -EBUSY;
+	}
+
+	ret = v4l2_subdev_call(to_outsd(mdev), video, s_dv_preset, preset);
+
+	mutex_unlock(&mdev->mutex);
+
+	/* any failure should return EINVAL according to V4L2 doc */
+	return ret ? -EINVAL : 0;
+}
+
+static int mxr_g_dv_preset(struct file *file, void *fh,
+	struct v4l2_dv_preset *preset)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret;
+
+	/* lock protects from changing sd_out */
+	mutex_lock(&mdev->mutex);
+	ret = v4l2_subdev_call(to_outsd(mdev), video, g_dv_preset, preset);
+	mutex_unlock(&mdev->mutex);
+
+	return ret ? -EINVAL : 0;
+}
+
+static int mxr_s_std(struct file *file, void *fh, v4l2_std_id *norm)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret;
+
+	/* lock protects from changing sd_out */
+	mutex_lock(&mdev->mutex);
+
+	/* standard change cannot be done while there is an entity
+	 * dependant on output configuration
+	 */
+	if (mdev->n_output > 0) {
+		mutex_unlock(&mdev->mutex);
+		return -EBUSY;
+	}
+
+	ret = v4l2_subdev_call(to_outsd(mdev), video, s_std_output, *norm);
+
+	mutex_unlock(&mdev->mutex);
+
+	return ret ? -EINVAL : 0;
+}
+
+static int mxr_g_std(struct file *file, void *fh, v4l2_std_id *norm)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret;
+
+	/* lock protects from changing sd_out */
+	mutex_lock(&mdev->mutex);
+	ret = v4l2_subdev_call(to_outsd(mdev), video, g_std_output, norm);
+	mutex_unlock(&mdev->mutex);
+
+	return ret ? -EINVAL : 0;
+}
+
+static int mxr_enum_output(struct file *file, void *fh, struct v4l2_output *a)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	struct mxr_output *out;
+	struct v4l2_subdev *sd;
+
+	if (a->index >= mdev->output_cnt)
+		return -EINVAL;
+	out = mdev->output[a->index];
+	BUG_ON(out == NULL);
+	sd = out->sd;
+	strlcpy(a->name, out->name, sizeof(a->name));
+
+	/* try to obtain supported tv norms */
+	v4l2_subdev_call(sd, video, g_tvnorms_output, &a->std);
+	a->capabilities = 0;
+	if (sd->ops->video && sd->ops->video->s_dv_preset)
+		a->capabilities |= V4L2_OUT_CAP_PRESETS;
+	if (sd->ops->video && sd->ops->video->s_std_output)
+		a->capabilities |= V4L2_OUT_CAP_STD;
+	a->type = V4L2_OUTPUT_TYPE_ANALOG;
+
+	return 0;
+}
+
+static int mxr_s_output(struct file *file, void *fh, unsigned int i)
+{
+	struct video_device *vfd = video_devdata(file);
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret = 0;
+
+	if (i >= mdev->output_cnt || mdev->output[i] == NULL)
+		return -EINVAL;
+
+	mutex_lock(&mdev->mutex);
+	if (mdev->n_output > 0) {
+		ret = -EBUSY;
+		goto done;
+	}
+	mdev->current_output = i;
+	vfd->tvnorms = 0;
+	v4l2_subdev_call(to_outsd(mdev), video, g_tvnorms_output,
+		&vfd->tvnorms);
+	mxr_dbg(mdev, "tvnorms = %08llx\n", vfd->tvnorms);
+
+done:
+	mutex_unlock(&mdev->mutex);
+	return ret;
+}
+
+static int mxr_g_output(struct file *file, void *fh, unsigned int *p)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+
+	mutex_lock(&mdev->mutex);
+	*p = mdev->current_output;
+	mutex_unlock(&mdev->mutex);
+
+	return 0;
+}
+
+static int mxr_reqbufs(struct file *file, void *priv,
+			  struct v4l2_requestbuffers *p)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	return vb2_reqbufs(&layer->vb_queue, p);
+}
+
+static int mxr_querybuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	return vb2_querybuf(&layer->vb_queue, p);
+}
+
+static int mxr_qbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	return vb2_qbuf(&layer->vb_queue, p);
+}
+
+static int mxr_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	return vb2_dqbuf(&layer->vb_queue, p, file->f_flags & O_NONBLOCK);
+}
+
+static int mxr_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+
+	switch (layer->idx) {
+	case 0:
+		mdev->layer_en.graph0 = 1;
+		break;
+	case 1:
+		mdev->layer_en.graph1 = 1;
+		break;
+	case 2:
+		mdev->layer_en.graph2 = 1;
+		break;
+	case 3:
+		mdev->layer_en.graph3 = 1;
+		break;
+	default:
+		mxr_err(mdev, "invalid layer number\n");
+		return -EINVAL;
+	}
+
+	if ((mdev->layer_en.graph0 && mdev->layer_en.graph2) ||
+	    (mdev->layer_en.graph1 && mdev->layer_en.graph3)) {
+		mdev->frame_packing = 1;
+		mxr_dbg(mdev, "frame packing mode\n");
+	}
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+	return vb2_streamon(&layer->vb_queue, i);
+}
+
+static int mxr_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+
+	switch (layer->idx) {
+	case 0:
+		mdev->layer_en.graph0 = 0;
+		break;
+	case 1:
+		mdev->layer_en.graph1 = 0;
+		break;
+	case 2:
+		mdev->layer_en.graph2 = 0;
+		break;
+	case 3:
+		mdev->layer_en.graph3 = 0;
+		break;
+	default:
+		mxr_err(mdev, "invalid layer number\n");
+		return -EINVAL;
+	}
+
+	mdev->frame_packing = 0;
+	if ((mdev->layer_en.graph0 && mdev->layer_en.graph2) ||
+	    (mdev->layer_en.graph1 && mdev->layer_en.graph3)) {
+		mdev->frame_packing = 1;
+		mxr_dbg(mdev, "frame packing mode\n");
+	}
+
+	mxr_dbg(mdev, "%s:%d\n", __func__, __LINE__);
+	return vb2_streamoff(&layer->vb_queue, i);
+}
+
+static const struct v4l2_ioctl_ops mxr_ioctl_ops = {
+	.vidioc_querycap = mxr_querycap,
+	/* format handling */
+	.vidioc_enum_fmt_vid_out = mxr_enum_fmt,
+	.vidioc_s_fmt_vid_out_mplane = mxr_s_fmt,
+	.vidioc_g_fmt_vid_out_mplane = mxr_g_fmt,
+	/* buffer control */
+	.vidioc_reqbufs = mxr_reqbufs,
+	.vidioc_querybuf = mxr_querybuf,
+	.vidioc_qbuf = mxr_qbuf,
+	.vidioc_dqbuf = mxr_dqbuf,
+	/* Streaming control */
+	.vidioc_streamon = mxr_streamon,
+	.vidioc_streamoff = mxr_streamoff,
+	/* Preset functions */
+	.vidioc_enum_dv_presets = mxr_enum_dv_presets,
+	.vidioc_s_dv_preset = mxr_s_dv_preset,
+	.vidioc_g_dv_preset = mxr_g_dv_preset,
+	/* analog TV standard functions */
+	.vidioc_s_std = mxr_s_std,
+	.vidioc_g_std = mxr_g_std,
+	/* Output handling */
+	.vidioc_enum_output = mxr_enum_output,
+	.vidioc_s_output = mxr_s_output,
+	.vidioc_g_output = mxr_g_output,
+	/* Crop ioctls */
+	.vidioc_g_crop = mxr_g_crop,
+	.vidioc_s_crop = mxr_s_crop,
+	.vidioc_cropcap = mxr_cropcap,
+	/* Alpha blending functions */
+	.vidioc_s_ctrl = mxr_s_ctrl,
+	.vidioc_g_ctrl = mxr_g_ctrl,
+};
+
+static int mxr_video_open(struct file *file)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+	struct mxr_device *mdev = layer->mdev;
+	int ret = 0;
+
+	mxr_dbg(mdev, "%s:%d\n", __func__, __LINE__);
+	/* assure device probe is finished */
+	wait_for_device_probe();
+	/* creating context for file descriptor */
+	ret = v4l2_fh_open(file);
+	if (ret) {
+		mxr_err(mdev, "v4l2_fh_open failed\n");
+		return ret;
+	}
+
+	/* leaving if layer is already initialized */
+	if (!v4l2_fh_is_singular_file(file))
+		return 0;
+
+	ret = vb2_queue_init(&layer->vb_queue);
+	if (ret != 0) {
+		mxr_err(mdev, "failed to initialize vb2 queue\n");
+		goto fail_fh_open;
+	}
+	/* set default format, first on the list */
+	layer->fmt = layer->fmt_array[0];
+	/* setup default geometry */
+	mxr_layer_default_geo(layer);
+
+	return 0;
+
+fail_fh_open:
+	v4l2_fh_release(file);
+
+	return ret;
+}
+
+static unsigned int
+mxr_video_poll(struct file *file, struct poll_table_struct *wait)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+
+	return vb2_poll(&layer->vb_queue, file, wait);
+}
+
+static int mxr_video_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+
+	return vb2_mmap(&layer->vb_queue, vma);
+}
+
+static int mxr_video_release(struct file *file)
+{
+	struct mxr_layer *layer = video_drvdata(file);
+
+	mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__);
+
+	/* initialize alpha blending variables */
+	layer->layer_blend_en = 0;
+	layer->layer_alpha = 0;
+	layer->pixel_blend_en = 0;
+	layer->chroma_en = 0;
+	layer->chroma_val = 0;
+
+	if (v4l2_fh_is_singular_file(file))
+		vb2_queue_release(&layer->vb_queue);
+
+	v4l2_fh_release(file);
+	return 0;
+}
+
+static const struct v4l2_file_operations mxr_fops = {
+	.owner = THIS_MODULE,
+	.open = mxr_video_open,
+	.poll = mxr_video_poll,
+	.mmap = mxr_video_mmap,
+	.release = mxr_video_release,
+	.unlocked_ioctl = video_ioctl2,
+};
+
+static int queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
+	unsigned int *nplanes, unsigned long sizes[],
+	void *alloc_ctxs[])
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vq);
+	const struct mxr_format *fmt = layer->fmt;
+	int i;
+	struct mxr_device *mdev = layer->mdev;
+	struct v4l2_plane_pix_format planes[3];
+
+	mxr_dbg(mdev, "%s\n", __func__);
+	/* checking if format was configured */
+	if (fmt == NULL)
+		return -EINVAL;
+	mxr_dbg(mdev, "fmt = %s\n", fmt->name);
+	mxr_mplane_fill(planes, fmt, layer->geo.src.full_width,
+		layer->geo.src.full_height);
+
+	*nplanes = fmt->num_subframes;
+	for (i = 0; i < fmt->num_subframes; ++i) {
+		alloc_ctxs[i] = layer->mdev->alloc_ctx;
+		sizes[i] = PAGE_ALIGN(planes[i].sizeimage);
+		mxr_dbg(mdev, "size[%d] = %08lx\n", i, sizes[i]);
+	}
+
+	if (*nbuffers == 0)
+		*nbuffers = 1;
+
+	vb2_queue_init(vq);
+
+	return 0;
+}
+
+static void buf_queue(struct vb2_buffer *vb)
+{
+	struct mxr_buffer *buffer = container_of(vb, struct mxr_buffer, vb);
+	struct mxr_layer *layer = vb2_get_drv_priv(vb->vb2_queue);
+	struct mxr_pipeline *pipe = &layer->pipe;
+	unsigned long flags;
+	int must_start = 0;
+
+	spin_lock_irqsave(&layer->enq_slock, flags);
+	if (pipe->state == MXR_PIPELINE_STREAMING_START) {
+		pipe->state = MXR_PIPELINE_STREAMING;
+		must_start = 1;
+	}
+	list_add_tail(&buffer->list, &layer->enq_list);
+	spin_unlock_irqrestore(&layer->enq_slock, flags);
+	if (must_start) {
+		layer->ops.stream_set(layer, MXR_ENABLE);
+		/* store starting entity ptr on the tv graphic pipeline */
+		pipe->layer = layer;
+		/* start streaming all entities on the tv graphic pipeline */
+		tv_graph_pipeline_stream(pipe, 1);
+	}
+}
+
+static void wait_lock(struct vb2_queue *vq)
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vq);
+
+	mutex_lock(&layer->mutex);
+}
+
+static void wait_unlock(struct vb2_queue *vq)
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vq);
+
+	mutex_unlock(&layer->mutex);
+}
+
+static int buf_prepare(struct vb2_buffer *vb)
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vb->vb2_queue);
+	struct mxr_device *mdev = layer->mdev;
+	struct v4l2_subdev *sd;
+	struct media_pad *pad;
+	int i, j;
+	int enable = 0;
+
+	for (i = 0; i < MXR_MAX_SUB_MIXERS; ++i) {
+		sd = &mdev->sub_mxr[i].sd;
+
+		for (j = MXR_PAD_SOURCE_GSCALER; j < MXR_PADS_NUM; ++j) {
+			pad = &sd->entity.pads[j];
+
+			/* find sink pad of hdmi or sdo through enabled link*/
+			pad = media_entity_remote_source(pad);
+			if (media_entity_type(pad->entity)
+					== MEDIA_ENT_T_V4L2_SUBDEV) {
+				enable = 1;
+				break;
+			}
+		}
+		if (enable)
+			break;
+	}
+	if (!enable)
+		return -ENODEV;
+
+	sd = media_entity_to_v4l2_subdev(pad->entity);
+
+	/* current output device must be matched terminal entity
+	 * which represents HDMI or SDO sub-device
+	 */
+	if (strcmp(sd->name, to_output(mdev)->sd->name)) {
+		mxr_err(mdev, "subdev name : %s, output device name : %s\n",
+				sd->name, to_output(mdev)->sd->name);
+		mxr_err(mdev, "output device is not mached\n");
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+static int start_streaming(struct vb2_queue *vq)
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vq);
+	struct mxr_device *mdev = layer->mdev;
+	struct mxr_pipeline *pipe = &layer->pipe;
+	unsigned long flags;
+	int ret;
+
+	mxr_dbg(mdev, "%s\n", __func__);
+
+	/* enable mixer clock */
+	ret = mxr_power_get(mdev);
+	if (ret) {
+		mxr_err(mdev, "power on failed\n");
+		return -ENODEV;
+	}
+
+	/* block any changes in output configuration */
+	mxr_output_get(mdev);
+
+	/* update layers geometry */
+	mxr_layer_geo_fix(layer);
+	mxr_geometry_dump(mdev, &layer->geo);
+
+	layer->ops.format_set(layer);
+	/* enabling layer in hardware */
+	spin_lock_irqsave(&layer->enq_slock, flags);
+	pipe->state = MXR_PIPELINE_STREAMING_START;
+	spin_unlock_irqrestore(&layer->enq_slock, flags);
+
+	return 0;
+}
+
+static void mxr_watchdog(unsigned long arg)
+{
+	struct mxr_layer *layer = (struct mxr_layer *) arg;
+	struct mxr_device *mdev = layer->mdev;
+	unsigned long flags;
+
+	mxr_err(mdev, "watchdog fired for layer %s\n", layer->vfd.name);
+
+	spin_lock_irqsave(&layer->enq_slock, flags);
+
+	if (layer->update_buf == layer->shadow_buf)
+		layer->update_buf = NULL;
+	if (layer->update_buf) {
+		vb2_buffer_done(&layer->update_buf->vb, VB2_BUF_STATE_ERROR);
+		layer->update_buf = NULL;
+	}
+	if (layer->shadow_buf) {
+		vb2_buffer_done(&layer->shadow_buf->vb, VB2_BUF_STATE_ERROR);
+		layer->shadow_buf = NULL;
+	}
+	spin_unlock_irqrestore(&layer->enq_slock, flags);
+}
+
+static int stop_streaming(struct vb2_queue *vq)
+{
+	struct mxr_layer *layer = vb2_get_drv_priv(vq);
+	struct mxr_device *mdev = layer->mdev;
+	unsigned long flags;
+	struct timer_list watchdog;
+	struct mxr_buffer *buf, *buf_tmp;
+	struct mxr_pipeline *pipe = &layer->pipe;
+
+	mxr_dbg(mdev, "%s\n", __func__);
+
+	spin_lock_irqsave(&layer->enq_slock, flags);
+
+	/* reset list */
+	pipe->state = MXR_PIPELINE_STREAMING_FINISH;
+
+	/* set all buffer to be done */
+	list_for_each_entry_safe(buf, buf_tmp, &layer->enq_list, list) {
+		list_del(&buf->list);
+		vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+	}
+
+	spin_unlock_irqrestore(&layer->enq_slock, flags);
+
+	/* give 1 seconds to complete to complete last buffers */
+	setup_timer_on_stack(&watchdog, mxr_watchdog,
+		(unsigned long)layer);
+	mod_timer(&watchdog, jiffies + msecs_to_jiffies(1000));
+
+	/* wait until all buffers are goes to done state */
+	vb2_wait_for_all_buffers(vq);
+
+	/* stop timer if all synchronization is done */
+	del_timer_sync(&watchdog);
+	destroy_timer_on_stack(&watchdog);
+
+	/* stopping hardware */
+	spin_lock_irqsave(&layer->enq_slock, flags);
+
+	pipe->state = MXR_PIPELINE_IDLE;
+	spin_unlock_irqrestore(&layer->enq_slock, flags);
+
+	/* disabling layer in hardware */
+	layer->ops.stream_set(layer, MXR_DISABLE);
+
+	/* starting entity on the pipeline */
+	pipe->layer = layer;
+	/* stop streaming all entities on the pipeline */
+	tv_graph_pipeline_stream(pipe, 0);
+
+	/* allow changes in output configuration */
+	mxr_output_put(mdev);
+
+	/* disable mixer clock */
+	mxr_power_put(mdev);
+
+	return 0;
+}
+
+static struct vb2_ops mxr_video_qops = {
+	.queue_setup = queue_setup,
+	.buf_queue = buf_queue,
+	.wait_prepare = wait_unlock,
+	.wait_finish = wait_lock,
+	.buf_prepare = buf_prepare,
+	.start_streaming = start_streaming,
+	.stop_streaming = stop_streaming,
+};
+
+/* FIXME: try to put this functions to mxr_base_layer_create */
+int mxr_base_layer_register(struct mxr_layer *layer)
+{
+	struct mxr_device *mdev = layer->mdev;
+	struct exynos_md *md;
+	int ret;
+
+	md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
+	if (!md) {
+		mxr_err(mdev, "failed to get output media device\n");
+		return -ENODEV;
+	}
+
+	layer->vfd.v4l2_dev = &md->v4l2_dev;
+	ret = video_register_device(&layer->vfd, VFL_TYPE_GRABBER, layer->minor);
+	if (ret)
+		mxr_err(mdev, "failed to register video device\n");
+	else
+		mxr_info(mdev, "registered layer %s as /dev/video%d\n",
+			layer->vfd.name, layer->vfd.num);
+	return ret;
+}
+
+void mxr_base_layer_unregister(struct mxr_layer *layer)
+{
+	video_unregister_device(&layer->vfd);
+}
+
+void mxr_layer_release(struct mxr_layer *layer)
+{
+	if (layer->ops.release)
+		layer->ops.release(layer);
+}
+
+void mxr_base_layer_release(struct mxr_layer *layer)
+{
+	kfree(layer);
+}
+
+static void mxr_vfd_release(struct video_device *vdev)
+{
+	printk(KERN_INFO "video device release\n");
+}
+
+struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev,
+	int idx, char *name, struct mxr_layer_ops *ops)
+{
+	struct mxr_layer *layer;
+	int ret;
+
+	layer = kzalloc(sizeof *layer, GFP_KERNEL);
+	if (layer == NULL) {
+		mxr_err(mdev, "not enough memory for layer.\n");
+		goto fail;
+	}
+
+	layer->mdev = mdev;
+	layer->idx = idx;
+	layer->ops = *ops;
+	layer->prio = idx + 2;
+
+	spin_lock_init(&layer->enq_slock);
+	INIT_LIST_HEAD(&layer->enq_list);
+	mutex_init(&layer->mutex);
+
+	layer->vfd = (struct video_device) {
+		.minor = -1,
+		.release = mxr_vfd_release,
+		.fops = &mxr_fops,
+		.ioctl_ops = &mxr_ioctl_ops,
+	};
+
+	/* media_entity_init must be called after initializing layer->vfd
+	 * for preventing to overwrite
+	 */
+	ret = media_entity_init(&layer->vfd.entity, 1, &layer->pad, 0);
+	if (ret) {
+		mxr_err(mdev, "media entity init failed\n");
+		goto fail_alloc;
+	}
+
+	strlcpy(layer->vfd.name, name, sizeof(layer->vfd.name));
+	layer->vfd.entity.name = layer->vfd.name;
+	/* let framework control PRIORITY */
+	set_bit(V4L2_FL_USE_FH_PRIO, &layer->vfd.flags);
+
+	video_set_drvdata(&layer->vfd, layer);
+	layer->vfd.lock = &layer->mutex;
+
+	layer->vb_queue = (struct vb2_queue) {
+		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+		.io_modes = VB2_MMAP | VB2_USERPTR,
+		.drv_priv = layer,
+		.buf_struct_size = sizeof(struct mxr_buffer),
+		.ops = &mxr_video_qops,
+		.mem_ops = mdev->vb2->ops,
+	};
+
+	return layer;
+
+fail_alloc:
+	kfree(layer);
+
+fail:
+	return NULL;
+}
+
+const struct mxr_format *find_format_by_fourcc(
+	struct mxr_layer *layer, unsigned long fourcc)
+{
+	int i;
+
+	for (i = 0; i < layer->fmt_array_size; ++i)
+		if (layer->fmt_array[i]->fourcc == fourcc)
+			return layer->fmt_array[i];
+	return NULL;
+}
+
+static const struct mxr_format *find_format_by_index(
+	struct mxr_layer *layer, unsigned long index)
+{
+	if (index >= layer->fmt_array_size)
+		return NULL;
+	return layer->fmt_array[index];
+}
+
diff --git a/drivers/media/video/exynos/tv/mixer_video_layer.c b/drivers/media/video/exynos/tv/mixer_video_layer.c
new file mode 100644
index 0000000..252e445
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_video_layer.c
@@ -0,0 +1,88 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include "mixer.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+/* AUXILIARY CALLBACKS */
+
+static void mxr_video_layer_release(struct mxr_layer *layer)
+{
+	mxr_base_layer_release(layer);
+}
+
+static void mxr_video_stream_set(struct mxr_layer *layer, int en) {
+	mxr_reg_video_layer_stream(layer->mdev, layer->idx, en);
+}
+
+static void mxr_video_format_set(struct mxr_layer *layer)
+{
+	mxr_reg_video_geo(layer->mdev, layer->cur_mxr, layer->idx, &layer->geo);
+}
+
+static void mxr_video_fix_geometry(struct mxr_layer *layer)
+{
+	struct mxr_geometry *geo = &layer->geo;
+
+	mxr_dbg(layer->mdev, "%s start\n", __func__);
+	geo->dst.x_offset = clamp_val(geo->dst.x_offset, 0,
+			geo->dst.full_width - 1);
+	geo->dst.y_offset = clamp_val(geo->dst.y_offset, 0,
+			geo->dst.full_height - 1);
+
+	/* mixer scale-up is unuseful. so no use it */
+	geo->dst.width = clamp_val(geo->dst.width, 1,
+			geo->dst.full_width - geo->dst.x_offset);
+	geo->dst.height = clamp_val(geo->dst.height, 1,
+			geo->dst.full_height - geo->dst.y_offset);
+}
+
+/* PUBLIC API */
+
+struct mxr_layer *mxr_video_layer_create(struct mxr_device *mdev, int cur_mxr,
+		int idx)
+{
+	struct mxr_layer *layer;
+	struct mxr_layer_ops ops = {
+		.release = mxr_video_layer_release,
+		.stream_set = mxr_video_stream_set,
+		.format_set = mxr_video_format_set,
+		.fix_geometry = mxr_video_fix_geometry,
+	};
+
+	layer = kzalloc(sizeof *layer, GFP_KERNEL);
+	if (layer == NULL) {
+		mxr_err(mdev, "not enough memory for layer.\n");
+		goto fail;
+	}
+
+	layer->mdev = mdev;
+	layer->idx = idx;
+	layer->type = MXR_LAYER_TYPE_VIDEO;
+	layer->ops = ops;
+	layer->prio = 1;
+
+	layer->cur_mxr = cur_mxr;
+
+	mxr_layer_default_geo(layer);
+
+	return layer;
+
+fail:
+	return NULL;
+}
diff --git a/drivers/media/video/exynos/tv/mixer_vp_layer.c b/drivers/media/video/exynos/tv/mixer_vp_layer.c
new file mode 100644
index 0000000..65bdbbe
--- /dev/null
+++ b/drivers/media/video/exynos/tv/mixer_vp_layer.c
@@ -0,0 +1,221 @@
+/*
+ * Samsung TV Mixer driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include "mixer.h"
+
+#include "regs-vp.h"
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+/* FORMAT DEFINITIONS */
+static const struct mxr_format mxr_fmt_nv12 = {
+	.name = "NV12",
+	.fourcc = V4L2_PIX_FMT_NV12,
+	.colorspace = V4L2_COLORSPACE_JPEG,
+	.num_planes = 2,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 1 },
+		{ .width = 2, .height = 2, .size = 2 },
+	},
+	.num_subframes = 1,
+	.cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR,
+};
+
+static const struct mxr_format mxr_fmt_nv21 = {
+	.name = "NV21",
+	.fourcc = V4L2_PIX_FMT_NV21,
+	.colorspace = V4L2_COLORSPACE_JPEG,
+	.num_planes = 2,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 1 },
+		{ .width = 2, .height = 2, .size = 2 },
+	},
+	.num_subframes = 1,
+	.cookie = VP_MODE_NV21 | VP_MODE_MEM_LINEAR,
+};
+
+static const struct mxr_format mxr_fmt_nv12m = {
+	.name = "NV12 (mplane)",
+	.fourcc = V4L2_PIX_FMT_NV12M,
+	.colorspace = V4L2_COLORSPACE_JPEG,
+	.num_planes = 2,
+	.plane = {
+		{ .width = 1, .height = 1, .size = 1 },
+		{ .width = 2, .height = 2, .size = 2 },
+	},
+	.num_subframes = 2,
+	.plane2subframe = {0, 1},
+	.cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR,
+};
+
+static const struct mxr_format mxr_fmt_nv12mt = {
+	.name = "NV12 tiled (mplane)",
+	.fourcc = V4L2_PIX_FMT_NV12MT,
+	.colorspace = V4L2_COLORSPACE_JPEG,
+	.num_planes = 2,
+	.plane = {
+		{ .width = 128, .height = 32, .size = 4096 },
+		{ .width = 128, .height = 32, .size = 2048 },
+	},
+	.num_subframes = 2,
+	.plane2subframe = {0, 1},
+	.cookie = VP_MODE_NV12 | VP_MODE_MEM_TILED,
+};
+
+static const struct mxr_format *mxr_video_format[] = {
+	&mxr_fmt_nv12,
+	&mxr_fmt_nv21,
+	&mxr_fmt_nv12m,
+	&mxr_fmt_nv12mt,
+};
+
+/* AUXILIARY CALLBACKS */
+
+static void mxr_vp_layer_release(struct mxr_layer *layer)
+{
+	mxr_base_layer_unregister(layer);
+	mxr_base_layer_release(layer);
+}
+
+static void mxr_vp_buffer_set(struct mxr_layer *layer,
+	struct mxr_buffer *buf)
+{
+	struct mxr_device *mdev = layer->mdev;
+	dma_addr_t luma_addr[2] = {0, 0};
+	dma_addr_t chroma_addr[2] = {0, 0};
+
+	if (buf == NULL) {
+		mxr_reg_vp_buffer(mdev, luma_addr, chroma_addr);
+		return;
+	}
+
+	luma_addr[0] = mdev->vb2->plane_addr(&buf->vb, 0);
+	if (layer->fmt->num_subframes == 2) {
+		chroma_addr[0] = mdev->vb2->plane_addr(&buf->vb, 1);
+	} else {
+		/* FIXME: mxr_get_plane_size compute integer division,
+		 * which is slow and should not be performed in interrupt */
+		chroma_addr[0] = luma_addr[0] + mxr_get_plane_size(
+			&layer->fmt->plane[0], layer->geo.src.full_width,
+			layer->geo.src.full_height);
+	}
+	if (layer->fmt->cookie & VP_MODE_MEM_TILED) {
+		luma_addr[1] = luma_addr[0] + 0x40;
+		chroma_addr[1] = chroma_addr[0] + 0x40;
+	} else {
+		luma_addr[1] = luma_addr[0] + layer->geo.src.full_width;
+		chroma_addr[1] = chroma_addr[0];
+	}
+	mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);
+}
+
+static void mxr_vp_stream_set(struct mxr_layer *layer, int en)
+{
+	mxr_reg_vp_layer_stream(layer->mdev, en);
+}
+
+static void mxr_vp_format_set(struct mxr_layer *layer)
+{
+	mxr_reg_vp_format(layer->mdev, layer->fmt, &layer->geo);
+}
+
+static void mxr_vp_fix_geometry(struct mxr_layer *layer)
+{
+	struct mxr_geometry *geo = &layer->geo;
+
+	mxr_dbg(layer->mdev, "%s start\n", __func__);
+	/* align horizontal size to 8 pixels */
+	geo->src.full_width = ALIGN(geo->src.full_width, 8);
+	/* limit to boundary size */
+	geo->src.full_width = clamp_val(geo->src.full_width, 8, 8192);
+	geo->src.full_height = clamp_val(geo->src.full_height, 1, 8192);
+	geo->src.width = clamp_val(geo->src.width, 32, geo->src.full_width);
+	geo->src.width = min(geo->src.width, 2047U);
+	geo->src.height = clamp_val(geo->src.height, 4, geo->src.full_height);
+	geo->src.height = min(geo->src.height, 2047U);
+
+	/* setting size of output window */
+	geo->dst.width = clamp_val(geo->dst.width, 8, geo->dst.full_width);
+	geo->dst.height = clamp_val(geo->dst.height, 1, geo->dst.full_height);
+
+	/* ensure that scaling is in range 1/4x to 16x */
+	if (geo->src.width >= 4 * geo->dst.width)
+		geo->src.width = 4 * geo->dst.width;
+	if (geo->dst.width >= 16 * geo->src.width)
+		geo->dst.width = 16 * geo->src.width;
+	if (geo->src.height >= 4 * geo->dst.height)
+		geo->src.height = 4 * geo->dst.height;
+	if (geo->dst.height >= 16 * geo->src.height)
+		geo->dst.height = 16 * geo->src.height;
+
+	/* setting scaling ratio */
+	geo->x_ratio = (geo->src.width << 16) / geo->dst.width;
+	geo->y_ratio = (geo->src.height << 16) / geo->dst.height;
+
+	/* adjust offsets */
+	geo->src.x_offset = min(geo->src.x_offset,
+		geo->src.full_width - geo->src.width);
+	geo->src.y_offset = min(geo->src.y_offset,
+		geo->src.full_height - geo->src.height);
+	geo->dst.x_offset = min(geo->dst.x_offset,
+		geo->dst.full_width - geo->dst.width);
+	geo->dst.y_offset = min(geo->dst.y_offset,
+		geo->dst.full_height - geo->dst.height);
+}
+
+/* PUBLIC API */
+
+struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int cur_mxr,
+		int idx, int nr)
+{
+	struct mxr_layer *layer;
+	int ret;
+	struct mxr_layer_ops ops = {
+		.release = mxr_vp_layer_release,
+		.buffer_set = mxr_vp_buffer_set,
+		.stream_set = mxr_vp_stream_set,
+		.format_set = mxr_vp_format_set,
+		.fix_geometry = mxr_vp_fix_geometry,
+	};
+	char name[32];
+
+	sprintf(name, "mxr%d_video%d", cur_mxr, idx);
+
+	layer = mxr_base_layer_create(mdev, idx, name, &ops);
+	if (layer == NULL) {
+		mxr_err(mdev, "failed to initialize layer(%d) base\n", idx);
+		goto fail;
+	}
+
+	layer->fmt_array = mxr_video_format;
+	layer->fmt_array_size = ARRAY_SIZE(mxr_video_format);
+	layer->minor = nr;
+	layer->type = MXR_LAYER_TYPE_VIDEO;
+
+	ret = mxr_base_layer_register(layer);
+	if (ret)
+		goto fail_layer;
+
+	layer->cur_mxr = cur_mxr;
+	return layer;
+
+fail_layer:
+	mxr_base_layer_release(layer);
+
+fail:
+	return NULL;
+}
diff --git a/drivers/media/video/exynos/tv/regs-hdmi-4210.h b/drivers/media/video/exynos/tv/regs-hdmi-4210.h
new file mode 100644
index 0000000..74c36d7
--- /dev/null
+++ b/drivers/media/video/exynos/tv/regs-hdmi-4210.h
@@ -0,0 +1,142 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * HDMI register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef SAMSUNG_REGS_HDMI_H
+#define SAMSUNG_REGS_HDMI_H
+
+/*
+ * Register part
+*/
+
+#define HDMI_CTRL_BASE(x)		((x) + 0x00000000)
+#define HDMI_CORE_BASE(x)		((x) + 0x00010000)
+#define HDMI_TG_BASE(x)			((x) + 0x00050000)
+
+/* Control registers */
+#define HDMI_INTC_CON			HDMI_CTRL_BASE(0x0000)
+#define HDMI_INTC_FLAG			HDMI_CTRL_BASE(0x0004)
+#define HDMI_HPD_STATUS			HDMI_CTRL_BASE(0x000C)
+#define HDMI_PHY_RSTOUT			HDMI_CTRL_BASE(0x0014)
+#define HDMI_PHY_VPLL			HDMI_CTRL_BASE(0x0018)
+#define HDMI_PHY_CMU			HDMI_CTRL_BASE(0x001C)
+#define HDMI_CORE_RSTOUT		HDMI_CTRL_BASE(0x0020)
+
+/* Core registers */
+#define HDMI_CON_0			HDMI_CORE_BASE(0x0000)
+#define HDMI_CON_1			HDMI_CORE_BASE(0x0004)
+#define HDMI_CON_2			HDMI_CORE_BASE(0x0008)
+#define HDMI_SYS_STATUS			HDMI_CORE_BASE(0x0010)
+#define HDMI_PHY_STATUS			HDMI_CORE_BASE(0x0014)
+#define HDMI_STATUS_EN			HDMI_CORE_BASE(0x0020)
+#define HDMI_HPD			HDMI_CORE_BASE(0x0030)
+#define HDMI_MODE_SEL			HDMI_CORE_BASE(0x0040)
+#define HDMI_BLUE_SCREEN_0		HDMI_CORE_BASE(0x0050)
+#define HDMI_BLUE_SCREEN_1		HDMI_CORE_BASE(0x0054)
+#define HDMI_BLUE_SCREEN_2		HDMI_CORE_BASE(0x0058)
+#define HDMI_H_BLANK_0			HDMI_CORE_BASE(0x00A0)
+#define HDMI_H_BLANK_1			HDMI_CORE_BASE(0x00A4)
+#define HDMI_V_BLANK_0			HDMI_CORE_BASE(0x00B0)
+#define HDMI_V_BLANK_1			HDMI_CORE_BASE(0x00B4)
+#define HDMI_V_BLANK_2			HDMI_CORE_BASE(0x00B8)
+#define HDMI_H_V_LINE_0			HDMI_CORE_BASE(0x00C0)
+#define HDMI_H_V_LINE_1			HDMI_CORE_BASE(0x00C4)
+#define HDMI_H_V_LINE_2			HDMI_CORE_BASE(0x00C8)
+#define HDMI_VSYNC_POL			HDMI_CORE_BASE(0x00E4)
+#define HDMI_INT_PRO_MODE		HDMI_CORE_BASE(0x00E8)
+#define HDMI_V_BLANK_F_0		HDMI_CORE_BASE(0x0110)
+#define HDMI_V_BLANK_F_1		HDMI_CORE_BASE(0x0114)
+#define HDMI_V_BLANK_F_2		HDMI_CORE_BASE(0x0118)
+#define HDMI_H_SYNC_GEN_0		HDMI_CORE_BASE(0x0120)
+#define HDMI_H_SYNC_GEN_1		HDMI_CORE_BASE(0x0124)
+#define HDMI_H_SYNC_GEN_2		HDMI_CORE_BASE(0x0128)
+#define HDMI_V_SYNC_GEN_1_0		HDMI_CORE_BASE(0x0130)
+#define HDMI_V_SYNC_GEN_1_1		HDMI_CORE_BASE(0x0134)
+#define HDMI_V_SYNC_GEN_1_2		HDMI_CORE_BASE(0x0138)
+#define HDMI_V_SYNC_GEN_2_0		HDMI_CORE_BASE(0x0140)
+#define HDMI_V_SYNC_GEN_2_1		HDMI_CORE_BASE(0x0144)
+#define HDMI_V_SYNC_GEN_2_2		HDMI_CORE_BASE(0x0148)
+#define HDMI_V_SYNC_GEN_3_0		HDMI_CORE_BASE(0x0150)
+#define HDMI_V_SYNC_GEN_3_1		HDMI_CORE_BASE(0x0154)
+#define HDMI_V_SYNC_GEN_3_2		HDMI_CORE_BASE(0x0158)
+#define HDMI_AVI_CON			HDMI_CORE_BASE(0x0300)
+#define HDMI_AVI_BYTE(n)		HDMI_CORE_BASE(0x0320 + 4 * (n))
+#define	HDMI_DC_CONTROL			HDMI_CORE_BASE(0x05C0)
+#define HDMI_VIDEO_PATTERN_GEN		HDMI_CORE_BASE(0x05C4)
+#define HDMI_HPD_GEN			HDMI_CORE_BASE(0x05C8)
+
+/* Timing generator registers */
+#define HDMI_TG_CMD			HDMI_TG_BASE(0x0000)
+#define HDMI_TG_H_FSZ_L			HDMI_TG_BASE(0x0018)
+#define HDMI_TG_H_FSZ_H			HDMI_TG_BASE(0x001C)
+#define HDMI_TG_HACT_ST_L		HDMI_TG_BASE(0x0020)
+#define HDMI_TG_HACT_ST_H		HDMI_TG_BASE(0x0024)
+#define HDMI_TG_HACT_SZ_L		HDMI_TG_BASE(0x0028)
+#define HDMI_TG_HACT_SZ_H		HDMI_TG_BASE(0x002C)
+#define HDMI_TG_V_FSZ_L			HDMI_TG_BASE(0x0030)
+#define HDMI_TG_V_FSZ_H			HDMI_TG_BASE(0x0034)
+#define HDMI_TG_VSYNC_L			HDMI_TG_BASE(0x0038)
+#define HDMI_TG_VSYNC_H			HDMI_TG_BASE(0x003C)
+#define HDMI_TG_VSYNC2_L		HDMI_TG_BASE(0x0040)
+#define HDMI_TG_VSYNC2_H		HDMI_TG_BASE(0x0044)
+#define HDMI_TG_VACT_ST_L		HDMI_TG_BASE(0x0048)
+#define HDMI_TG_VACT_ST_H		HDMI_TG_BASE(0x004C)
+#define HDMI_TG_VACT_SZ_L		HDMI_TG_BASE(0x0050)
+#define HDMI_TG_VACT_SZ_H		HDMI_TG_BASE(0x0054)
+#define HDMI_TG_FIELD_CHG_L		HDMI_TG_BASE(0x0058)
+#define HDMI_TG_FIELD_CHG_H		HDMI_TG_BASE(0x005C)
+#define HDMI_TG_VACT_ST2_L		HDMI_TG_BASE(0x0060)
+#define HDMI_TG_VACT_ST2_H		HDMI_TG_BASE(0x0064)
+#define HDMI_TG_VSYNC_TOP_HDMI_L	HDMI_TG_BASE(0x0078)
+#define HDMI_TG_VSYNC_TOP_HDMI_H	HDMI_TG_BASE(0x007C)
+#define HDMI_TG_VSYNC_BOT_HDMI_L	HDMI_TG_BASE(0x0080)
+#define HDMI_TG_VSYNC_BOT_HDMI_H	HDMI_TG_BASE(0x0084)
+#define HDMI_TG_FIELD_TOP_HDMI_L	HDMI_TG_BASE(0x0088)
+#define HDMI_TG_FIELD_TOP_HDMI_H	HDMI_TG_BASE(0x008C)
+#define HDMI_TG_FIELD_BOT_HDMI_L	HDMI_TG_BASE(0x0090)
+#define HDMI_TG_FIELD_BOT_HDMI_H	HDMI_TG_BASE(0x0094)
+
+/*
+ * Bit definition part
+ */
+
+/* HDMI_INTC_CON */
+#define HDMI_INTC_EN_GLOBAL		(1 << 6)
+#define HDMI_INTC_EN_HPD_PLUG		(1 << 3)
+#define HDMI_INTC_EN_HPD_UNPLUG		(1 << 2)
+
+/* HDMI_INTC_FLAG */
+#define HDMI_INTC_FLAG_HPD_PLUG		(1 << 3)
+#define HDMI_INTC_FLAG_HPD_UNPLUG	(1 << 2)
+
+/* HDMI_PHY_RSTOUT */
+#define HDMI_PHY_SW_RSTOUT		(1 << 0)
+
+/* HDMI_CORE_RSTOUT */
+#define HDMI_CORE_SW_RSTOUT		(1 << 0)
+
+/* HDMI_CON_0 */
+#define HDMI_BLUE_SCR_EN		(1 << 5)
+#define HDMI_EN				(1 << 0)
+
+/* HDMI_PHY_STATUS */
+#define HDMI_PHY_STATUS_READY		(1 << 0)
+
+/* HDMI_MODE_SEL */
+#define HDMI_MODE_HDMI_EN		(1 << 1)
+#define HDMI_MODE_DVI_EN		(1 << 0)
+#define HDMI_MODE_MASK			(3 << 0)
+
+/* HDMI_TG_CMD */
+#define HDMI_FIELD_EN			(1 << 1)
+#define HDMI_TG_EN			(1 << 0)
+
+#endif /* SAMSUNG_REGS_HDMI_H */
diff --git a/drivers/media/video/exynos/tv/regs-hdmi-5250.h b/drivers/media/video/exynos/tv/regs-hdmi-5250.h
new file mode 100644
index 0000000..be9ac4f
--- /dev/null
+++ b/drivers/media/video/exynos/tv/regs-hdmi-5250.h
@@ -0,0 +1,1275 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi_14.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * HDMI register header file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ARCH_ARM_REGS_HDMI_H
+#define __ARCH_ARM_REGS_HDMI_H
+
+/*
+ * Register part
+*/
+
+#define S5P_HDMI_I2C_PHY_BASE(x)	(x)
+
+#define HDMI_I2C_CON			S5P_HDMI_I2C_PHY_BASE(0x0000)
+#define HDMI_I2C_STAT			S5P_HDMI_I2C_PHY_BASE(0x0004)
+#define HDMI_I2C_ADD			S5P_HDMI_I2C_PHY_BASE(0x0008)
+#define HDMI_I2C_DS			S5P_HDMI_I2C_PHY_BASE(0x000c)
+#define HDMI_I2C_LC			S5P_HDMI_I2C_PHY_BASE(0x0010)
+
+#define HDMI_CTRL_BASE(x)		((x) + 0x00000000)
+#define HDMI_CORE_BASE(x)		((x) + 0x00010000)
+#define HDMI_SPDIF_BASE(x)		((x) + 0x00030000)
+#define HDMI_I2S_BASE(x)		((x) + 0x00040000)
+#define HDMI_TG_BASE(x)			((x) + 0x00050000)
+#define HDMI_EFUSE_BASE(x)		((x) + 0x00060000)
+
+/* Control registers */
+#define HDMI_INTC_CON_0			HDMI_CTRL_BASE(0x0000)
+#define HDMI_INTC_FLAG_0		HDMI_CTRL_BASE(0x0004)
+#define HDMI_HDCP_KEY_LOAD		HDMI_CTRL_BASE(0x0008)
+#define HDMI_HPD_STATUS			HDMI_CTRL_BASE(0x000C)
+
+#define HDMI_INTC_CON_1			HDMI_CTRL_BASE(0x0010)
+#define HDMI_INTC_FLAG_1		HDMI_CTRL_BASE(0x0014)
+#define HDMI_PHY_STATUS_0		HDMI_CTRL_BASE(0x0020)
+#define HDMI_PHY_STATUS_PLL		HDMI_CTRL_BASE(0x0028)
+#define HDMI_PHY_CON_0			HDMI_CTRL_BASE(0x0030)
+
+#define HDMI_HPD_CTRL			HDMI_CTRL_BASE(0x0040)
+#define HDMI_HPD_TH_(n)			HDMI_CTRL_BASE(0x0050 + 4 * (n))
+
+#define HDMI_AUDIO_CLKSEL		HDMI_CTRL_BASE(0x0070)
+#define HDMI_PHY_RSTOUT			HDMI_CTRL_BASE(0x0074)
+#define HDMI_PHY_VPLL			HDMI_CTRL_BASE(0x0078)
+#define HDMI_PHY_CMU			HDMI_CTRL_BASE(0x007C)
+#define HDMI_CORE_RSTOUT		HDMI_CTRL_BASE(0x080)
+
+/* HDMI core registers */
+#define HDMI_CON_0			HDMI_CORE_BASE(0x000)
+#define HDMI_CON_1			HDMI_CORE_BASE(0x004)
+#define HDMI_CON_2			HDMI_CORE_BASE(0x008)
+#define HDMI_SIM_MODE			HDMI_CORE_BASE(0x00C)
+#define HDMI_STATUS			HDMI_CORE_BASE(0x010)
+#define HDMI_PHY_STATUS			HDMI_CORE_BASE(0x014)
+#define HDMI_STATUS_EN			HDMI_CORE_BASE(0x020)
+#define HDMI_HPD			HDMI_CORE_BASE(0x030)
+#define HDMI_MODE_SEL			HDMI_CORE_BASE(0x040)
+#define HDMI_ENC_EN			HDMI_CORE_BASE(0x044)
+
+/* Video related registers */
+#define HDMI_YMAX			HDMI_CORE_BASE(0x060)
+#define HDMI_YMIN			HDMI_CORE_BASE(0x064)
+#define HDMI_CMAX			HDMI_CORE_BASE(0x068)
+#define HDMI_CMIN			HDMI_CORE_BASE(0x06c)
+
+#define HDMI_DI_PREFIX			HDMI_CORE_BASE(0x078)
+#define HDMI_VBI_ST_MG			HDMI_CORE_BASE(0x080)
+#define HDMI_END_MG			HDMI_CORE_BASE(0x084)
+
+#define HDMI_AUTH_ST_MG0		HDMI_CORE_BASE(0x090)
+#define HDMI_AUTH_ST_MG1		HDMI_CORE_BASE(0x094)
+#define HDMI_AUTH_END_MG0		HDMI_CORE_BASE(0x098)
+#define HDMI_AUTH_END_MG1		HDMI_CORE_BASE(0x09C)
+
+#define HDMI_H_BLANK_0			HDMI_CORE_BASE(0x0a0)
+#define HDMI_H_BLANK_1			HDMI_CORE_BASE(0x0a4)
+
+#define HDMI_V2_BLANK_0			HDMI_CORE_BASE(0x0b0)
+#define HDMI_V2_BLANK_1			HDMI_CORE_BASE(0x0b4)
+#define HDMI_V1_BLANK_0			HDMI_CORE_BASE(0x0b8)
+#define HDMI_V1_BLANK_1			HDMI_CORE_BASE(0x0bC)
+
+#define HDMI_V_LINE_0			HDMI_CORE_BASE(0x0c0)
+#define HDMI_V_LINE_1			HDMI_CORE_BASE(0x0c4)
+#define HDMI_H_LINE_0			HDMI_CORE_BASE(0x0c8)
+#define HDMI_H_LINE_1			HDMI_CORE_BASE(0x0cC)
+#define HDMI_HSYNC_POL			HDMI_CORE_BASE(0x0E0)
+
+#define HDMI_VSYNC_POL			HDMI_CORE_BASE(0x0e4)
+#define HDMI_INT_PRO_MODE		HDMI_CORE_BASE(0x0e8)
+
+#define HDMI_V_BLANK_F0_0		HDMI_CORE_BASE(0x110)
+#define HDMI_V_BLANK_F0_1		HDMI_CORE_BASE(0x114)
+#define HDMI_V_BLANK_F1_0		HDMI_CORE_BASE(0x118)
+#define HDMI_V_BLANK_F1_1		HDMI_CORE_BASE(0x11C)
+
+#define HDMI_H_SYNC_START_0		HDMI_CORE_BASE(0x120)
+#define HDMI_H_SYNC_START_1		HDMI_CORE_BASE(0x124)
+#define HDMI_H_SYNC_END_0		HDMI_CORE_BASE(0x128)
+#define HDMI_H_SYNC_END_1		HDMI_CORE_BASE(0x12C)
+
+#define HDMI_V_SYNC_LINE_BEF_2_0	HDMI_CORE_BASE(0x130)
+#define HDMI_V_SYNC_LINE_BEF_2_1	HDMI_CORE_BASE(0x134)
+#define HDMI_V_SYNC_LINE_BEF_1_0	HDMI_CORE_BASE(0x138)
+#define HDMI_V_SYNC_LINE_BEF_1_1	HDMI_CORE_BASE(0x13C)
+
+#define HDMI_V_SYNC_LINE_AFT_2_0	HDMI_CORE_BASE(0x140)
+#define HDMI_V_SYNC_LINE_AFT_2_1	HDMI_CORE_BASE(0x144)
+#define HDMI_V_SYNC_LINE_AFT_1_0	HDMI_CORE_BASE(0x148)
+#define HDMI_V_SYNC_LINE_AFT_1_1	HDMI_CORE_BASE(0x14C)
+
+#define HDMI_V_SYNC_LINE_AFT_PXL_2_0	HDMI_CORE_BASE(0x150)
+#define HDMI_V_SYNC_LINE_AFT_PXL_2_1	HDMI_CORE_BASE(0x154)
+#define HDMI_V_SYNC_LINE_AFT_PXL_1_0	HDMI_CORE_BASE(0x158)
+#define HDMI_V_SYNC_LINE_AFT_PXL_1_1	HDMI_CORE_BASE(0x15C)
+
+#define HDMI_V_BLANK_F2_0		HDMI_CORE_BASE(0x160)
+#define HDMI_V_BLANK_F2_1		HDMI_CORE_BASE(0x164)
+#define HDMI_V_BLANK_F3_0		HDMI_CORE_BASE(0x168)
+#define HDMI_V_BLANK_F3_1		HDMI_CORE_BASE(0x16C)
+#define HDMI_V_BLANK_F4_0		HDMI_CORE_BASE(0x170)
+#define HDMI_V_BLANK_F4_1		HDMI_CORE_BASE(0x174)
+#define HDMI_V_BLANK_F5_0		HDMI_CORE_BASE(0x178)
+#define HDMI_V_BLANK_F5_1		HDMI_CORE_BASE(0x17C)
+
+#define HDMI_V_SYNC_LINE_AFT_3_0	HDMI_CORE_BASE(0x180)
+#define HDMI_V_SYNC_LINE_AFT_3_1	HDMI_CORE_BASE(0x184)
+#define HDMI_V_SYNC_LINE_AFT_4_0	HDMI_CORE_BASE(0x188)
+#define HDMI_V_SYNC_LINE_AFT_4_1	HDMI_CORE_BASE(0x18C)
+#define HDMI_V_SYNC_LINE_AFT_5_0	HDMI_CORE_BASE(0x190)
+#define HDMI_V_SYNC_LINE_AFT_5_1	HDMI_CORE_BASE(0x194)
+#define HDMI_V_SYNC_LINE_AFT_6_0	HDMI_CORE_BASE(0x198)
+#define HDMI_V_SYNC_LINE_AFT_6_1	HDMI_CORE_BASE(0x19C)
+
+#define HDMI_V_SYNC_LINE_AFT_PXL_3_0	HDMI_CORE_BASE(0x1A0)
+#define HDMI_V_SYNC_LINE_AFT_PXL_3_1	HDMI_CORE_BASE(0x1A4)
+#define HDMI_V_SYNC_LINE_AFT_PXL_4_0	HDMI_CORE_BASE(0x1A8)
+#define HDMI_V_SYNC_LINE_AFT_PXL_4_1	HDMI_CORE_BASE(0x1AC)
+#define HDMI_V_SYNC_LINE_AFT_PXL_5_0	HDMI_CORE_BASE(0x1B0)
+#define HDMI_V_SYNC_LINE_AFT_PXL_5_1	HDMI_CORE_BASE(0x1B4)
+#define HDMI_V_SYNC_LINE_AFT_PXL_6_0	HDMI_CORE_BASE(0x1B8)
+#define HDMI_V_SYNC_LINE_AFT_PXL_6_1	HDMI_CORE_BASE(0x1BC)
+
+#define HDMI_VACT_SPACE_1_0		HDMI_CORE_BASE(0x1C0)
+#define HDMI_VACT_SPACE_1_1		HDMI_CORE_BASE(0x1C4)
+#define HDMI_VACT_SPACE_2_0		HDMI_CORE_BASE(0x1C8)
+#define HDMI_VACT_SPACE_2_1		HDMI_CORE_BASE(0x1CC)
+#define HDMI_VACT_SPACE_3_0		HDMI_CORE_BASE(0x1D0)
+#define HDMI_VACT_SPACE_3_1		HDMI_CORE_BASE(0x1D4)
+#define HDMI_VACT_SPACE_4_0		HDMI_CORE_BASE(0x1D8)
+#define HDMI_VACT_SPACE_4_1		HDMI_CORE_BASE(0x1DC)
+#define HDMI_VACT_SPACE_5_0		HDMI_CORE_BASE(0x1E0)
+#define HDMI_VACT_SPACE_5_1		HDMI_CORE_BASE(0x1E4)
+#define HDMI_VACT_SPACE_6_0		HDMI_CORE_BASE(0x1E8)
+#define HDMI_VACT_SPACE_6_1		HDMI_CORE_BASE(0x1EC)
+#define HDMI_CSC_MUX			HDMI_CORE_BASE(0x1F0)
+#define HDMI_SYNC_GEN_MUX		HDMI_CORE_BASE(0x1F4)
+
+#define HDMI_GCP_CON			HDMI_CORE_BASE(0x200)
+#define HDMI_GCP_CON_EX			HDMI_CORE_BASE(0x204)
+#define HDMI_GCP_BYTE1			HDMI_CORE_BASE(0x210)
+#define HDMI_GCP_BYTE2			HDMI_CORE_BASE(0x214)
+#define HDMI_GCP_BYTE3			HDMI_CORE_BASE(0x218)
+
+/* Audio related registers */
+#define HDMI_ASP_CON			HDMI_CORE_BASE(0x300)
+#define HDMI_ASP_SP_FLAT		HDMI_CORE_BASE(0x304)
+#define HDMI_ASP_CHCFG0			HDMI_CORE_BASE(0x310)
+#define HDMI_ASP_CHCFG1			HDMI_CORE_BASE(0x314)
+#define HDMI_ASP_CHCFG2			HDMI_CORE_BASE(0x318)
+#define HDMI_ASP_CHCFG3			HDMI_CORE_BASE(0x31c)
+
+#define HDMI_ACR_CON			HDMI_CORE_BASE(0x400)
+#define HDMI_ACR_MCTS0			HDMI_CORE_BASE(0x410)
+#define HDMI_ACR_MCTS1			HDMI_CORE_BASE(0x414)
+#define HDMI_ACR_MCTS2			HDMI_CORE_BASE(0x418)
+#define HDMI_ACR_CTS0			HDMI_CORE_BASE(0x420)
+#define HDMI_ACR_CTS1			HDMI_CORE_BASE(0x424)
+#define HDMI_ACR_CTS2			HDMI_CORE_BASE(0x428)
+#define HDMI_ACR_N0			HDMI_CORE_BASE(0x430)
+#define HDMI_ACR_N1			HDMI_CORE_BASE(0x434)
+#define HDMI_ACR_N2			HDMI_CORE_BASE(0x438)
+#define HDMI_ACR_LSB2			HDMI_CORE_BASE(0x440)
+#define HDMI_ACR_TXCNT			HDMI_CORE_BASE(0x444)
+#define HDMI_ACR_TXINTERNAL		HDMI_CORE_BASE(0x448)
+#define HDMI_ACR_CTS_OFFSET		HDMI_CORE_BASE(0x44c)
+
+#define HDMI_ACP_CON			HDMI_CORE_BASE(0x500)
+#define HDMI_ACP_TYPE			HDMI_CORE_BASE(0x514)
+/* offset of HDMI_ACP_DATA00 ~ 16 : 0x0520 ~ 0x0560 */
+#define HDMI_ACP_DATA(n)		HDMI_CORE_BASE(0x520 + 4 * (n))
+
+#define HDMI_ISRC_CON			HDMI_CORE_BASE(0x600)
+#define HDMI_ISRC1_HEADER1		HDMI_CORE_BASE(0x614)
+/* offset of HDMI_ISRC1_DATA00 ~ 15 : 0x0620 ~ 0x065C */
+#define HDMI_ISRC1_DATA(n)		HDMI_CORE_BASE(0x620 + 4 * (n))
+/* offset of HDMI_ISRC2_DATA00 ~ 15 : 0x06A0 ~ 0x06DC */
+#define HDMI_ISRC2_DATA(n)		HDMI_CORE_BASE(0x6A0 + 4 * (n))
+
+#define HDMI_AVI_CON			HDMI_CORE_BASE(0x700)
+#define HDMI_AVI_HEADER0		HDMI_CORE_BASE(0x710)
+#define HDMI_AVI_HEADER1		HDMI_CORE_BASE(0x714)
+#define HDMI_AVI_HEADER2		HDMI_CORE_BASE(0x718)
+#define HDMI_AVI_CHECK_SUM		HDMI_CORE_BASE(0x71C)
+/* offset of HDMI_AVI_BYTE1 ~ 13 : 0x0720 ~ 0x0750 */
+#define HDMI_AVI_BYTE(n)		HDMI_CORE_BASE(0x720 + 4 * (n - 1))
+
+#define HDMI_AUI_CON			HDMI_CORE_BASE(0x800)
+#define HDMI_AUI_HEADER0		HDMI_CORE_BASE(0x810)
+#define HDMI_AUI_HEADER1		HDMI_CORE_BASE(0x814)
+#define HDMI_AUI_HEADER2		HDMI_CORE_BASE(0x818)
+#define HDMI_AUI_CHECK_SUM		HDMI_CORE_BASE(0x81C)
+/* offset of HDMI_AUI_BYTE1 ~ 12 : 0x0820 ~ 0x084C */
+#define HDMI_AUI_BYTE(n)		HDMI_CORE_BASE(0x820 + 4 * (n - 1))
+
+#define HDMI_MPG_CON			HDMI_CORE_BASE(0x900)
+#define HDMI_MPG_CHECK_SUM		HDMI_CORE_BASE(0x91C)
+/* offset of HDMI_MPG_BYTE1 ~ 6 : 0x0920 ~ 0x0934 */
+#define HDMI_MPG_BYTE(n)		HDMI_CORE_BASE(0x920 + 4 * (n - 1))
+
+#define HDMI_SPD_CON			HDMI_CORE_BASE(0xA00)
+#define HDMI_SPD_HEADER0		HDMI_CORE_BASE(0xA10)
+#define HDMI_SPD_HEADER1		HDMI_CORE_BASE(0xA14)
+#define HDMI_SPD_HEADER2		HDMI_CORE_BASE(0xA18)
+/* offset of HDMI_SPD_DATA00 ~ 27 : 0x0A20 ~ 0x0A8C */
+#define HDMI_SPD_DATA0(n)		HDMI_CORE_BASE(0xA20 + 4 * (n))
+
+#define HDMI_GAMUT_CON			HDMI_CORE_BASE(0xB00)
+#define HDMI_GAMUT_HEADER0		HDMI_CORE_BASE(0xB10)
+#define HDMI_GAMUT_HEADER1		HDMI_CORE_BASE(0xB14)
+#define HDMI_GAMUT_HEADER2		HDMI_CORE_BASE(0xB18)
+/* offset of HDMI_GAMUT_METADATA00 ~ 27 : 0x0B20 ~ 0x0B8C */
+#define HDMI_GAMUT_METADATA(n)		HDMI_CORE_BASE(0xB20 + 4 * (n))
+
+#define HDMI_VSI_CON			HDMI_CORE_BASE(0xC00)
+#define HDMI_VSI_HEADER0		HDMI_CORE_BASE(0xC10)
+#define HDMI_VSI_HEADER1		HDMI_CORE_BASE(0xC14)
+#define HDMI_VSI_HEADER2		HDMI_CORE_BASE(0xC18)
+/* offset of HDMI_VSI_DATA00 ~ 27 : 0x0C20 ~ 0x0C8C */
+#define HDMI_VSI_DATA(n)		HDMI_CORE_BASE(0xC20 + 4 * (n))
+
+#define HDMI_DC_CONTROL			HDMI_CORE_BASE(0xD00)
+#define HDMI_VIDEO_PATTERN_GEN		HDMI_CORE_BASE(0xD04)
+#define HDMI_HPD_GEN0			HDMI_CORE_BASE(0xD08)
+#define HDMI_HPD_GEN1			HDMI_CORE_BASE(0xD0C)
+#define HDMI_HPD_GEN2			HDMI_CORE_BASE(0xD10)
+#define HDMI_HPD_GEN3			HDMI_CORE_BASE(0xD14)
+
+#define HDMI_DIM_CON			HDMI_CORE_BASE(0xD30)
+
+/* HDCP related registers */
+/* offset of HDMI_HDCP_SHA1_00 ~ 19 : 0x7000 ~ 0x704C */
+#define HDMI_HDCP_SHA1_(n)		HDMI_CORE_BASE(0x7000 + 4 * (n))
+
+/* offset of HDMI_HDCP_KSV_LIST_0 ~ 4 : 0x7050 ~ 0x7060 */
+#define HDMI_HDCP_KSV_LIST_(n)		HDMI_CORE_BASE(0x7050 + 4 * (n))
+
+#define HDMI_HDCP_KSV_LIST_CON		HDMI_CORE_BASE(0x7064)
+#define HDMI_HDCP_SHA_RESULT		HDMI_CORE_BASE(0x7070)
+#define HDMI_HDCP_CTRL1			HDMI_CORE_BASE(0x7080)
+#define HDMI_HDCP_CTRL2			HDMI_CORE_BASE(0x7084)
+#define HDMI_HDCP_CHECK_RESULT		HDMI_CORE_BASE(0x7090)
+
+/* offset of HDMI_HDCP_BKSV_0 ~ 4 : 0x70A0 ~ 0x70B0 */
+#define HDMI_HDCP_BKSV_(n)		HDMI_CORE_BASE(0x70A0 + 4 * (n))
+/* offset of HDMI_HDCP_AKSV_0 ~ 4 : 0x70C0 ~ 0x70D0 */
+#define HDMI_HDCP_AKSV_(n)		HDMI_CORE_BASE(0x70C0 + 4 * (n))
+
+/* offset of HDMI_HDCP_AN_0 ~ 7 : 0x70E0 ~ 0x70FC */
+#define HDMI_HDCP_AN_(n)		HDMI_CORE_BASE(0x70E0 + 4 * (n))
+
+#define HDMI_HDCP_BCAPS			HDMI_CORE_BASE(0x7100)
+#define HDMI_HDCP_BSTATUS_0		HDMI_CORE_BASE(0x7110)
+#define HDMI_HDCP_BSTATUS_1		HDMI_CORE_BASE(0x7114)
+#define HDMI_HDCP_RI_0			HDMI_CORE_BASE(0x7140)
+#define HDMI_HDCP_RI_1			HDMI_CORE_BASE(0x7144)
+#define HDMI_HDCP_I2C_INT		HDMI_CORE_BASE(0x7180)
+#define HDMI_HDCP_AN_INT		HDMI_CORE_BASE(0x7190)
+#define HDMI_HDCP_WDT_INT		HDMI_CORE_BASE(0x71a0)
+#define HDMI_HDCP_RI_INT		HDMI_CORE_BASE(0x71b0)
+
+#define HDMI_HDCP_RI_COMPARE_0		HDMI_CORE_BASE(0x71d0)
+#define HDMI_HDCP_RI_COMPARE_1		HDMI_CORE_BASE(0x71d4)
+#define HDMI_HDCP_FRAME_COUNT		HDMI_CORE_BASE(0x71e0)
+
+#define HDMI_RGB_ROUND_EN		HDMI_CORE_BASE(0xD500)
+
+#define HDMI_VACT_SPACE_R_0		HDMI_CORE_BASE(0xD504)
+#define HDMI_VACT_SPACE_R_1		HDMI_CORE_BASE(0xD508)
+
+#define HDMI_VACT_SPACE_G_0		HDMI_CORE_BASE(0xD50C)
+#define HDMI_VACT_SPACE_G_1		HDMI_CORE_BASE(0xD510)
+
+#define HDMI_VACT_SPACE_B_0		HDMI_CORE_BASE(0xD514)
+#define HDMI_VACT_SPACE_B_1		HDMI_CORE_BASE(0xD518)
+
+#define HDMI_BLUE_SCREEN_B_0		HDMI_CORE_BASE(0xD520)
+#define HDMI_BLUE_SCREEN_B_1		HDMI_CORE_BASE(0xD524)
+#define HDMI_BLUE_SCREEN_G_0		HDMI_CORE_BASE(0xD528)
+#define HDMI_BLUE_SCREEN_G_1		HDMI_CORE_BASE(0xD52C)
+#define HDMI_BLUE_SCREEN_R_0		HDMI_CORE_BASE(0xD530)
+#define HDMI_BLUE_SCREEN_R_1		HDMI_CORE_BASE(0xD534)
+
+/* SPDIF registers */
+#define HDMI_SPDIFIN_CLK_CTRL		HDMI_SPDIF_BASE(0x000)
+#define HDMI_SPDIFIN_OP_CTRL		HDMI_SPDIF_BASE(0x004)
+#define HDMI_SPDIFIN_IRQ_MASK		HDMI_SPDIF_BASE(0x008)
+#define HDMI_SPDIFIN_IRQ_STATUS		HDMI_SPDIF_BASE(0x00c)
+#define HDMI_SPDIFIN_CONFIG_1		HDMI_SPDIF_BASE(0x010)
+#define HDMI_SPDIFIN_CONFIG_2		HDMI_SPDIF_BASE(0x014)
+#define HDMI_SPDIFIN_USER_VALUE_1	HDMI_SPDIF_BASE(0x020)
+#define HDMI_SPDIFIN_USER_VALUE_2	HDMI_SPDIF_BASE(0x024)
+#define HDMI_SPDIFIN_USER_VALUE_3	HDMI_SPDIF_BASE(0x028)
+#define HDMI_SPDIFIN_USER_VALUE_4	HDMI_SPDIF_BASE(0x02c)
+#define HDMI_SPDIFIN_CH_STATUS_0_1	HDMI_SPDIF_BASE(0x030)
+#define HDMI_SPDIFIN_CH_STATUS_0_2	HDMI_SPDIF_BASE(0x034)
+#define HDMI_SPDIFIN_CH_STATUS_0_3	HDMI_SPDIF_BASE(0x038)
+#define HDMI_SPDIFIN_CH_STATUS_0_4	HDMI_SPDIF_BASE(0x03c)
+#define HDMI_SPDIFIN_CH_STATUS_1	HDMI_SPDIF_BASE(0x040)
+#define HDMI_SPDIFIN_FRAME_PERIOD_1	HDMI_SPDIF_BASE(0x048)
+#define HDMI_SPDIFIN_FRAME_PERIOD_2	HDMI_SPDIF_BASE(0x04c)
+#define HDMI_SPDIFIN_PC_INFO_1		HDMI_SPDIF_BASE(0x050)
+#define HDMI_SPDIFIN_PC_INFO_2		HDMI_SPDIF_BASE(0x054)
+#define HDMI_SPDIFIN_PD_INFO_1		HDMI_SPDIF_BASE(0x058)
+#define HDMI_SPDIFIN_PD_INFO_2		HDMI_SPDIF_BASE(0x05c)
+#define HDMI_SPDIFIN_DATA_BUF_0_1	HDMI_SPDIF_BASE(0x060)
+#define HDMI_SPDIFIN_DATA_BUF_0_2	HDMI_SPDIF_BASE(0x064)
+#define HDMI_SPDIFIN_DATA_BUF_0_3	HDMI_SPDIF_BASE(0x068)
+#define HDMI_SPDIFIN_USER_BUF_0		HDMI_SPDIF_BASE(0x06c)
+#define HDMI_SPDIFIN_DATA_BUF_1_1	HDMI_SPDIF_BASE(0x070)
+#define HDMI_SPDIFIN_DATA_BUF_1_2	HDMI_SPDIF_BASE(0x074)
+#define HDMI_SPDIFIN_DATA_BUF_1_3	HDMI_SPDIF_BASE(0x078)
+#define HDMI_SPDIFIN_USER_BUF_1		HDMI_SPDIF_BASE(0x07c)
+
+/* I2S registers */
+#define HDMI_I2S_CLK_CON		HDMI_I2S_BASE(0x000)
+#define HDMI_I2S_CON_1			HDMI_I2S_BASE(0x004)
+#define HDMI_I2S_CON_2			HDMI_I2S_BASE(0x008)
+#define HDMI_I2S_PIN_SEL_0		HDMI_I2S_BASE(0x00c)
+#define HDMI_I2S_PIN_SEL_1		HDMI_I2S_BASE(0x010)
+#define HDMI_I2S_PIN_SEL_2		HDMI_I2S_BASE(0x014)
+#define HDMI_I2S_PIN_SEL_3		HDMI_I2S_BASE(0x018)
+#define HDMI_I2S_DSD_CON		HDMI_I2S_BASE(0x01c)
+#define HDMI_I2S_IN_MUX_CON		HDMI_I2S_BASE(0x020)
+#define HDMI_I2S_CH_ST_CON		HDMI_I2S_BASE(0x024)
+#define HDMI_I2S_CH_ST_0		HDMI_I2S_BASE(0x028)
+#define HDMI_I2S_CH_ST_1		HDMI_I2S_BASE(0x02c)
+#define HDMI_I2S_CH_ST_2		HDMI_I2S_BASE(0x030)
+#define HDMI_I2S_CH_ST_3		HDMI_I2S_BASE(0x034)
+#define HDMI_I2S_CH_ST_4		HDMI_I2S_BASE(0x038)
+#define HDMI_I2S_CH_ST_SH_0		HDMI_I2S_BASE(0x03c)
+#define HDMI_I2S_CH_ST_SH_1		HDMI_I2S_BASE(0x040)
+#define HDMI_I2S_CH_ST_SH_2		HDMI_I2S_BASE(0x044)
+#define HDMI_I2S_CH_ST_SH_3		HDMI_I2S_BASE(0x048)
+#define HDMI_I2S_CH_ST_SH_4		HDMI_I2S_BASE(0x04c)
+#define HDMI_I2S_VD_DATA		HDMI_I2S_BASE(0x050)
+#define HDMI_I2S_MUX_CH			HDMI_I2S_BASE(0x054)
+#define HDMI_I2S_MUX_CUV		HDMI_I2S_BASE(0x058)
+#define HDMI_I2S_IRQ_MASK		HDMI_I2S_BASE(0x05c)
+#define HDMI_I2S_IRQ_STATUS		HDMI_I2S_BASE(0x060)
+
+#define HDMI_I2S_CH0_L_0		HDMI_I2S_BASE(0x0064)
+#define HDMI_I2S_CH0_L_1		HDMI_I2S_BASE(0x0068)
+#define HDMI_I2S_CH0_L_2		HDMI_I2S_BASE(0x006C)
+#define HDMI_I2S_CH0_L_3		HDMI_I2S_BASE(0x0070)
+#define HDMI_I2S_CH0_R_0		HDMI_I2S_BASE(0x0074)
+#define HDMI_I2S_CH0_R_1		HDMI_I2S_BASE(0x0078)
+#define HDMI_I2S_CH0_R_2		HDMI_I2S_BASE(0x007C)
+#define HDMI_I2S_CH0_R_3		HDMI_I2S_BASE(0x0080)
+#define HDMI_I2S_CH1_L_0		HDMI_I2S_BASE(0x0084)
+#define HDMI_I2S_CH1_L_1		HDMI_I2S_BASE(0x0088)
+#define HDMI_I2S_CH1_L_2		HDMI_I2S_BASE(0x008C)
+#define HDMI_I2S_CH1_L_3		HDMI_I2S_BASE(0x0090)
+#define HDMI_I2S_CH1_R_0		HDMI_I2S_BASE(0x0094)
+#define HDMI_I2S_CH1_R_1		HDMI_I2S_BASE(0x0098)
+#define HDMI_I2S_CH1_R_2		HDMI_I2S_BASE(0x009C)
+#define HDMI_I2S_CH1_R_3		HDMI_I2S_BASE(0x00A0)
+#define HDMI_I2S_CH2_L_0		HDMI_I2S_BASE(0x00A4)
+#define HDMI_I2S_CH2_L_1		HDMI_I2S_BASE(0x00A8)
+#define HDMI_I2S_CH2_L_2		HDMI_I2S_BASE(0x00AC)
+#define HDMI_I2S_CH2_L_3		HDMI_I2S_BASE(0x00B0)
+#define HDMI_I2S_CH2_R_0		HDMI_I2S_BASE(0x00B4)
+#define HDMI_I2S_CH2_R_1		HDMI_I2S_BASE(0x00B8)
+#define HDMI_I2S_CH2_R_2		HDMI_I2S_BASE(0x00BC)
+#define HDMI_I2S_Ch2_R_3		HDMI_I2S_BASE(0x00C0)
+#define HDMI_I2S_CH3_L_0		HDMI_I2S_BASE(0x00C4)
+#define HDMI_I2S_CH3_L_1		HDMI_I2S_BASE(0x00C8)
+#define HDMI_I2S_CH3_L_2		HDMI_I2S_BASE(0x00CC)
+#define HDMI_I2S_CH3_R_0		HDMI_I2S_BASE(0x00D0)
+#define HDMI_I2S_CH3_R_1		HDMI_I2S_BASE(0x00D4)
+#define HDMI_I2S_CH3_R_2		HDMI_I2S_BASE(0x00D8)
+#define HDMI_I2S_CUV_L_R		HDMI_I2S_BASE(0x00DC)
+
+/* Timing Generator registers */
+#define HDMI_TG_CMD			HDMI_TG_BASE(0x000)
+#define HDMI_TG_CFG			HDMI_TG_BASE(0x004)
+#define HDMI_TG_CB_SZ			HDMI_TG_BASE(0x008)
+#define HDMI_TG_INDELAY_L		HDMI_TG_BASE(0x00c)
+#define HDMI_TG_INDELAY_H		HDMI_TG_BASE(0x010)
+#define HDMI_TG_POL_CTRL		HDMI_TG_BASE(0x014)
+#define HDMI_TG_H_FSZ_L			HDMI_TG_BASE(0x018)
+#define HDMI_TG_H_FSZ_H			HDMI_TG_BASE(0x01c)
+#define HDMI_TG_HACT_ST_L		HDMI_TG_BASE(0x020)
+#define HDMI_TG_HACT_ST_H		HDMI_TG_BASE(0x024)
+#define HDMI_TG_HACT_SZ_L		HDMI_TG_BASE(0x028)
+#define HDMI_TG_HACT_SZ_H		HDMI_TG_BASE(0x02c)
+#define HDMI_TG_V_FSZ_L			HDMI_TG_BASE(0x030)
+#define HDMI_TG_V_FSZ_H			HDMI_TG_BASE(0x034)
+#define HDMI_TG_VSYNC_L			HDMI_TG_BASE(0x038)
+#define HDMI_TG_VSYNC_H			HDMI_TG_BASE(0x03c)
+#define HDMI_TG_VSYNC2_L		HDMI_TG_BASE(0x040)
+#define HDMI_TG_VSYNC2_H		HDMI_TG_BASE(0x044)
+#define HDMI_TG_VACT_ST_L		HDMI_TG_BASE(0x048)
+#define HDMI_TG_VACT_ST_H		HDMI_TG_BASE(0x04c)
+#define HDMI_TG_VACT_SZ_L		HDMI_TG_BASE(0x050)
+#define HDMI_TG_VACT_SZ_H		HDMI_TG_BASE(0x054)
+#define HDMI_TG_FIELD_CHG_L		HDMI_TG_BASE(0x058)
+#define HDMI_TG_FIELD_CHG_H		HDMI_TG_BASE(0x05c)
+#define HDMI_TG_VACT_ST2_L		HDMI_TG_BASE(0x060)
+#define HDMI_TG_VACT_ST2_H		HDMI_TG_BASE(0x064)
+#define HDMI_TG_VACT_ST3_L		HDMI_TG_BASE(0x068)
+#define HDMI_TG_VACT_ST3_H		HDMI_TG_BASE(0x06c)
+#define HDMI_TG_VACT_ST4_L		HDMI_TG_BASE(0x070)
+#define HDMI_TG_VACT_ST4_H		HDMI_TG_BASE(0x074)
+
+#define HDMI_TG_VSYNC_TOP_HDMI_L	HDMI_TG_BASE(0x078)
+#define HDMI_TG_VSYNC_TOP_HDMI_H	HDMI_TG_BASE(0x07c)
+#define HDMI_TG_VSYNC_BOT_HDMI_L	HDMI_TG_BASE(0x080)
+#define HDMI_TG_VSYNC_BOT_HDMI_H	HDMI_TG_BASE(0x084)
+#define HDMI_TG_FIELD_TOP_HDMI_L	HDMI_TG_BASE(0x088)
+#define HDMI_TG_FIELD_TOP_HDMI_H	HDMI_TG_BASE(0x08c)
+#define HDMI_TG_FIELD_BOT_HDMI_L	HDMI_TG_BASE(0x090)
+#define HDMI_TG_FIELD_BOT_HDMI_H	HDMI_TG_BASE(0x094)
+
+#define HDMI_TG_3D			HDMI_TG_BASE(0x0F0)
+
+#define HDMI_MHL_HSYNC_WIDTH		HDMI_TG_BASE(0x17C)
+#define HDMI_MHL_VSYNC_WIDTH		HDMI_TG_BASE(0x180)
+#define HDMI_MHL_CLK_INV		HDMI_TG_BASE(0x184)
+
+/* HDMI eFUSE registers */
+#define HDMI_EFUSE_CTRL			HDMI_EFUSE_BASE(0x000)
+#define HDMI_EFUSE_STATUS		HDMI_EFUSE_BASE(0x004)
+#define HDMI_EFUSE_ADDR_WIDTH		HDMI_EFUSE_BASE(0x008)
+#define HDMI_EFUSE_SIGDEV_ASSERT	HDMI_EFUSE_BASE(0x00c)
+#define HDMI_EFUSE_SIGDEV_DE_ASSERT	HDMI_EFUSE_BASE(0x010)
+#define HDMI_EFUSE_PRCHG_ASSERT		HDMI_EFUSE_BASE(0x014)
+#define HDMI_EFUSE_PRCHG_DE_ASSERT	HDMI_EFUSE_BASE(0x018)
+#define HDMI_EFUSE_FSET_ASSERT		HDMI_EFUSE_BASE(0x01c)
+#define HDMI_EFUSE_FSET_DE_ASSERT	HDMI_EFUSE_BASE(0x020)
+#define HDMI_EFUSE_SENSING		HDMI_EFUSE_BASE(0x024)
+#define HDMI_EFUSE_SCK_ASSERT		HDMI_EFUSE_BASE(0x028)
+#define HDMI_EFUSE_SCK_DE_ASSERT	HDMI_EFUSE_BASE(0x02c)
+#define HDMI_EFUSE_SDOUT_OFFSET		HDMI_EFUSE_BASE(0x030)
+#define HDMI_EFUSE_READ_OFFSET		HDMI_EFUSE_BASE(0x034)
+
+/*
+ * Bit definition part
+ */
+
+/* Control Register */
+
+/* HDMI_INTC_CON_0 */
+#define HDMI_INTC_POL				(1 << 7)
+#define HDMI_INTC_EN_GLOBAL			(1 << 6)
+#define HDMI_INTC_EN_I2S			(1 << 5)
+#define HDMI_INTC_EN_CEC			(1 << 4)
+#define HDMI_INTC_EN_HPD_PLUG			(1 << 3)
+#define HDMI_INTC_EN_HPD_UNPLUG			(1 << 2)
+#define HDMI_INTC_EN_SPDIF			(1 << 1)
+#define HDMI_INTC_EN_HDCP			(1 << 0)
+
+/* HDMI_INTC_FLAG_0 */
+#define HDMI_INTC_FLAG_I2S			(1 << 5)
+#define HDMI_INTC_FLAG_CEC			(1 << 4)
+#define HDMI_INTC_FLAG_HPD_PLUG			(1 << 3)
+#define HDMI_INTC_FLAG_HPD_UNPLUG		(1 << 2)
+#define HDMI_INTC_FLAG_SPDIF			(1 << 1)
+#define HDMI_INTC_FLAG_HDCP			(1 << 0)
+
+/* HDMI_HDCP_KEY_LOAD */
+#define HDMI_HDCP_KEY_LOAD_DONE			(1 << 0)
+
+/* HDMI_HPD_STATUS */
+#define HDMI_HPD_VALUE				(1 << 0)
+
+/* AUDIO_CLKSEL */
+#define HDMI_AUDIO_SPDIF_CLK			(1 << 0)
+#define HDMI_AUDIO_PCLK				(0 << 0)
+
+/* HDMI_PHY_RSTOUT */
+#define HDMI_PHY_SW_RSTOUT			(1 << 0)
+
+/* HDMI_PHY_VPLL */
+#define HDMI_PHY_VPLL_LOCK			(1 << 7)
+#define HDMI_PHY_VPLL_CODE_MASK			(0x7 << 0)
+
+/* HDMI_PHY_CMU */
+#define HDMI_PHY_CMU_LOCK			(1 << 7)
+#define HDMI_PHY_CMU_CODE_MASK			(0x7 << 0)
+
+/* HDMI_CORE_RSTOUT */
+#define HDMI_CORE_SW_RSTOUT			(1 << 0)
+
+/* Core Register */
+
+/* HDMI_CON_0 */
+#define HDMI_BLUE_SCR_EN			(1 << 5)
+#define HDMI_BLUE_SCR_DIS			(0 << 5)
+#define HDMI_ENC_OPTION				(1 << 4)
+#define HDMI_ASP_ENABLE				(1 << 2)
+#define HDMI_ASP_DISABLE			(0 << 2)
+#define HDMI_PWDN_ENB_NORMAL			(1 << 1)
+#define HDMI_PWDN_ENB_PD			(0 << 1)
+#define HDMI_EN					(1 << 0)
+#define HDMI_DIS				(~(1 << 0))
+
+/* HDMI_CON_1 */
+#define HDMI_PX_LMT_CTRL_BYPASS			(0 << 5)
+#define HDMI_PX_LMT_CTRL_RGB			(1 << 5)
+#define HDMI_PX_LMT_CTRL_YPBPR			(2 << 5)
+#define HDMI_PX_LMT_CTRL_RESERVED		(3 << 5)
+#define HDMI_CON_PXL_REP_RATIO_MASK		(1 << 1 | 1 << 0)
+#define HDMI_DOUBLE_PIXEL_REPETITION		(0x01)
+
+/* HDMI_CON_2 */
+#define HDMI_VID_PREAMBLE_EN			(0 << 5)
+#define HDMI_VID_PREAMBLE_DIS			(1 << 5)
+#define HDMI_GUARD_BAND_EN			(0 << 1)
+#define HDMI_GUARD_BAND_DIS			(1 << 1)
+
+/* STATUS */
+#define HDMI_AUTHEN_ACK_AUTH			(1 << 7)
+#define HDMI_AUTHEN_ACK_NOT			(0 << 7)
+#define HDMI_AUD_FIFO_OVF_FULL			(1 << 6)
+#define HDMI_AUD_FIFO_OVF_NOT			(0 << 6)
+#define HDMI_UPDATE_RI_INT_OCC			(1 << 4)
+#define HDMI_UPDATE_RI_INT_NOT			(0 << 4)
+#define HDMI_UPDATE_RI_INT_CLEAR		(1 << 4)
+#define HDMI_UPDATE_PJ_INT_OCC			(1 << 3)
+#define HDMI_UPDATE_PJ_INT_NOT			(0 << 3)
+#define HDMI_UPDATE_PJ_INT_CLEAR		(1 << 3)
+#define HDMI_WRITE_INT_OCC			(1 << 2)
+#define HDMI_WRITE_INT_NOT			(0 << 2)
+#define HDMI_WRITE_INT_CLEAR			(1 << 2)
+#define HDMI_WATCHDOG_INT_OCC			(1 << 1)
+#define HDMI_WATCHDOG_INT_NOT			(0 << 1)
+#define HDMI_WATCHDOG_INT_CLEAR			(1 << 1)
+#define HDMI_WTFORACTIVERX_INT_OCC		(1)
+#define HDMI_WTFORACTIVERX_INT_NOT		(0)
+#define HDMI_WTFORACTIVERX_INT_CLEAR		(1)
+
+/* PHY_STATUS */
+#define HDMI_PHY_STATUS_READY			(1)
+
+/* HDMI_MODE_SEL */
+#define HDMI_MODE_HDMI_EN		(1 << 1)
+#define HDMI_MODE_DVI_EN		(1 << 0)
+#define HDMI_MODE_MASK			(3 << 0)
+
+/* STATUS_EN */
+#define HDMI_AUD_FIFO_OVF_EN			(1 << 6)
+#define HDMI_AUD_FIFO_OVF_DIS			(0 << 6)
+#define HDMI_UPDATE_RI_INT_EN			(1 << 4)
+#define HDMI_UPDATE_RI_INT_DIS			(0 << 4)
+#define HDMI_UPDATE_PJ_INT_EN			(1 << 3)
+#define HDMI_UPDATE_PJ_INT_DIS			(0 << 3)
+#define HDMI_WRITE_INT_EN			(1 << 2)
+#define HDMI_WRITE_INT_DIS			(0 << 2)
+#define HDMI_WATCHDOG_INT_EN			(1 << 1)
+#define HDMI_WATCHDOG_INT_DIS			(0 << 1)
+#define HDMI_WTFORACTIVERX_INT_EN		(1)
+#define HDMI_WTFORACTIVERX_INT_DIS		(0)
+#define HDMI_INT_EN_ALL				(HDMI_UPDATE_RI_INT_EN|\
+						HDMI_UPDATE_PJ_INT_DIS|\
+						HDMI_WRITE_INT_EN|\
+						HDMI_WATCHDOG_INT_EN|\
+						HDMI_WTFORACTIVERX_INT_EN)
+#define HDMI_INT_DIS_ALL			(~0x1F)
+
+/* HPD */
+#define HDMI_SW_HPD_PLUGGED			(1 << 1)
+#define HDMI_SW_HPD_UNPLUGGED			(0 << 1)
+#define HDMI_HPD_SEL_I_HPD			(1)
+#define HDMI_HPD_SEL_SW_HPD			(0)
+
+/* MODE_SEL */
+#define HDMI_MODE_EN				(1 << 1)
+#define HDMI_MODE_DIS				(0 << 1)
+#define HDMI_DVI_MODE_EN			(1)
+#define HDMI_DVI_MODE_DIS			(0)
+
+/* ENC_EN */
+#define HDMI_HDCP_ENC_ENABLE			(1)
+#define HDMI_HDCP_ENC_DISABLE			(0)
+
+/* Video Related Register */
+
+/* BLUESCREEN_0/1/2 */
+
+/* HDMI_YMAX/YMIN/CMAX/CMIN */
+
+/* H_BLANK_0/1 */
+
+/* V_BLANK_0/1/2 */
+
+/* H_V_LINE_0/1/2 */
+
+/* VSYNC_POL */
+#define HDMI_V_SYNC_POL_ACT_LOW			(1)
+#define HDMI_V_SYNC_POL_ACT_HIGH		(0)
+
+/* INT_PRO_MODE */
+#define HDMI_INTERLACE_MODE			(1)
+#define HDMI_PROGRESSIVE_MODE			(0)
+
+/* V_BLANK_F_0/1/2 */
+
+/* H_SYNC_GEN_0/1/2 */
+
+/* V_SYNC_GEN1_0/1/2 */
+
+/* V_SYNC_GEN2_0/1/2 */
+
+/* V_SYNC_GEN3_0/1/2 */
+
+/* Audio Related Packet Register */
+
+/* ASP_CON */
+#define HDMI_AUD_DST_DOUBLE			(1 << 7)
+#define HDMI_AUD_NO_DST_DOUBLE			(0 << 7)
+#define HDMI_AUD_TYPE_SAMPLE			(0 << 5)
+#define HDMI_AUD_TYPE_ONE_BIT			(1 << 5)
+#define HDMI_AUD_TYPE_HBR			(2 << 5)
+#define HDMI_AUD_TYPE_DST			(3 << 5)
+#define HDMI_AUD_MODE_TWO_CH			(0 << 4)
+#define HDMI_AUD_MODE_MULTI_CH			(1 << 4)
+#define HDMI_AUD_SP_AUD3_EN			(1 << 3)
+#define HDMI_AUD_SP_AUD2_EN			(1 << 2)
+#define HDMI_AUD_SP_AUD1_EN			(1 << 1)
+#define HDMI_AUD_SP_AUD0_EN			(1 << 0)
+#define HDMI_AUD_SP_ALL_DIS			(0 << 0)
+
+#define HDMI_AUD_SET_SP_PRE(x)			((x) & 0xF)
+
+/* ASP_SP_FLAT */
+#define HDMI_ASP_SP_FLAT_AUD_SAMPLE		(0)
+
+/* ASP_CHCFG0/1/2/3 */
+#define HDMI_SPK3R_SEL_I_PCM0L			(0 << 27)
+#define HDMI_SPK3R_SEL_I_PCM0R			(1 << 27)
+#define HDMI_SPK3R_SEL_I_PCM1L			(2 << 27)
+#define HDMI_SPK3R_SEL_I_PCM1R			(3 << 27)
+#define HDMI_SPK3R_SEL_I_PCM2L			(4 << 27)
+#define HDMI_SPK3R_SEL_I_PCM2R			(5 << 27)
+#define HDMI_SPK3R_SEL_I_PCM3L			(6 << 27)
+#define HDMI_SPK3R_SEL_I_PCM3R			(7 << 27)
+#define HDMI_SPK3L_SEL_I_PCM0L			(0 << 24)
+#define HDMI_SPK3L_SEL_I_PCM0R			(1 << 24)
+#define HDMI_SPK3L_SEL_I_PCM1L			(2 << 24)
+#define HDMI_SPK3L_SEL_I_PCM1R			(3 << 24)
+#define HDMI_SPK3L_SEL_I_PCM2L			(4 << 24)
+#define HDMI_SPK3L_SEL_I_PCM2R			(5 << 24)
+#define HDMI_SPK3L_SEL_I_PCM3L			(6 << 24)
+#define HDMI_SPK3L_SEL_I_PCM3R			(7 << 24)
+#define HDMI_SPK2R_SEL_I_PCM0L			(0 << 19)
+#define HDMI_SPK2R_SEL_I_PCM0R			(1 << 19)
+#define HDMI_SPK2R_SEL_I_PCM1L			(2 << 19)
+#define HDMI_SPK2R_SEL_I_PCM1R			(3 << 19)
+#define HDMI_SPK2R_SEL_I_PCM2L			(4 << 19)
+#define HDMI_SPK2R_SEL_I_PCM2R			(5 << 19)
+#define HDMI_SPK2R_SEL_I_PCM3L			(6 << 19)
+#define HDMI_SPK2R_SEL_I_PCM3R			(7 << 19)
+#define HDMI_SPK2L_SEL_I_PCM0L			(0 << 16)
+#define HDMI_SPK2L_SEL_I_PCM0R			(1 << 16)
+#define HDMI_SPK2L_SEL_I_PCM1L			(2 << 16)
+#define HDMI_SPK2L_SEL_I_PCM1R			(3 << 16)
+#define HDMI_SPK2L_SEL_I_PCM2L			(4 << 16)
+#define HDMI_SPK2L_SEL_I_PCM2R			(5 << 16)
+#define HDMI_SPK2L_SEL_I_PCM3L			(6 << 16)
+#define HDMI_SPK2L_SEL_I_PCM3R			(7 << 16)
+#define HDMI_SPK1R_SEL_I_PCM0L			(0 << 11)
+#define HDMI_SPK1R_SEL_I_PCM0R			(1 << 11)
+#define HDMI_SPK1R_SEL_I_PCM1L			(2 << 11)
+#define HDMI_SPK1R_SEL_I_PCM1R			(3 << 11)
+#define HDMI_SPK1R_SEL_I_PCM2L			(4 << 11)
+#define HDMI_SPK1R_SEL_I_PCM2R			(5 << 11)
+#define HDMI_SPK1R_SEL_I_PCM3L			(6 << 11)
+#define HDMI_SPK1R_SEL_I_PCM3R			(7 << 11)
+#define HDMI_SPK1L_SEL_I_PCM0L			(0 << 8)
+#define HDMI_SPK1L_SEL_I_PCM0R			(1 << 8)
+#define HDMI_SPK1L_SEL_I_PCM1L			(2 << 8)
+#define HDMI_SPK1L_SEL_I_PCM1R			(3 << 8)
+#define HDMI_SPK1L_SEL_I_PCM2L			(4 << 8)
+#define HDMI_SPK1L_SEL_I_PCM2R			(5 << 8)
+#define HDMI_SPK1L_SEL_I_PCM3L			(6 << 8)
+#define HDMI_SPK1L_SEL_I_PCM3R			(7 << 8)
+#define HDMI_SPK0R_SEL_I_PCM0L			(0 << 3)
+#define HDMI_SPK0R_SEL_I_PCM0R			(1 << 3)
+#define HDMI_SPK0R_SEL_I_PCM1L			(2 << 3)
+#define HDMI_SPK0R_SEL_I_PCM1R			(3 << 3)
+#define HDMI_SPK0R_SEL_I_PCM2L			(4 << 3)
+#define HDMI_SPK0R_SEL_I_PCM2R			(5 << 3)
+#define HDMI_SPK0R_SEL_I_PCM3L			(6 << 3)
+#define HDMI_SPK0R_SEL_I_PCM3R			(7 << 3)
+#define HDMI_SPK0L_SEL_I_PCM0L			(0)
+#define HDMI_SPK0L_SEL_I_PCM0R			(1)
+#define HDMI_SPK0L_SEL_I_PCM1L			(2)
+#define HDMI_SPK0L_SEL_I_PCM1R			(3)
+#define HDMI_SPK0L_SEL_I_PCM2L			(4)
+#define HDMI_SPK0L_SEL_I_PCM2R			(5)
+#define HDMI_SPK0L_SEL_I_PCM3L			(6)
+#define HDMI_SPK0L_SEL_I_PCM3R			(7)
+
+/* ACR_CON */
+#define HDMI_ACR_CON_TX_MODE_NO_TX		(0 << 0)
+#define HDMI_ACR_CON_TX_MODE_MESURED_CTS	(4 << 0)
+
+/* ACR_MCTS0/1/2 */
+
+/* ACR_CTS0/1/2 */
+
+/* ACR_N0/1/2 */
+#define HDMI_ACR_N0_VAL(x)			(x & 0xff)
+#define HDMI_ACR_N1_VAL(x)			((x >> 8) & 0xff)
+#define HDMI_ACR_N2_VAL(x)			((x >> 16) & 0xff)
+
+/* ACR_LSB2 */
+#define HDMI_ACR_LSB2_MASK			(0xFF)
+
+/* ACR_TXCNT */
+#define HDMI_ACR_TXCNT_MASK			(0x1F)
+
+/* ACR_TXINTERNAL */
+#define HDMI_ACR_TX_INTERNAL_MASK		(0xFF)
+
+/* ACR_CTS_OFFSET */
+#define HDMI_ACR_CTS_OFFSET_MASK		(0xFF)
+
+/* GCP_CON */
+#define HDMI_GCP_CON_EN_1ST_VSYNC		(1 << 3)
+#define HDMI_GCP_CON_EN_2ST_VSYNC		(1 << 2)
+#define HDMI_GCP_CON_TRANS_EVERY_VSYNC		(2)
+#define HDMI_GCP_CON_NO_TRAN			(0)
+#define HDMI_GCP_CON_TRANS_ONCE			(1)
+#define HDMI_GCP_CON_TRANS_EVERY_VSYNC		(2)
+
+/* GCP_BYTE1 */
+#define HDMI_GCP_BYTE1_MASK			(0xFF)
+
+/* GCP_BYTE2 */
+#define HDMI_GCP_BYTE2_PP_MASK			(0xF << 4)
+#define HDMI_GCP_24BPP				(1 << 2)
+#define HDMI_GCP_30BPP				(1 << 0 | 1 << 2)
+#define HDMI_GCP_36BPP				(1 << 1 | 1 << 2)
+#define HDMI_GCP_48BPP				(1 << 0 | 1 << 1 | 1 << 2)
+
+/* GCP_BYTE3 */
+#define HDMI_GCP_BYTE3_MASK			(0xFF)
+
+/* ACP Packet Register */
+
+/* ACP_CON */
+#define HDMI_ACP_FR_RATE_MASK			(0x1F << 3)
+#define HDMI_ACP_CON_NO_TRAN			(0)
+#define HDMI_ACP_CON_TRANS_ONCE			(1)
+#define HDMI_ACP_CON_TRANS_EVERY_VSYNC		(2)
+
+/* ACP_TYPE */
+#define HDMI_ACP_TYPE_MASK			(0xFF)
+
+/* ACP_DATA00~16 */
+#define HDMI_ACP_DATA_MASK			(0xFF)
+
+/* ISRC1/2 Packet Register */
+
+/* ISRC_CON */
+#define HDMI_ISRC_FR_RATE_MASK			(0x1F << 3)
+#define HDMI_ISRC_EN				(1 << 2)
+#define HDMI_ISRC_DIS				(0 << 2)
+
+/* ISRC1_HEADER1 */
+#define HDMI_ISRC1_HEADER_MASK			(0xFF)
+
+/* ISRC1_DATA 00~15 */
+#define HDMI_ISRC1_DATA_MASK			(0xFF)
+
+/* ISRC2_DATA 00~15 */
+#define HDMI_ISRC2_DATA_MASK			(0xFF)
+
+/* AVI InfoFrame Register */
+
+/* AVI_CON */
+#define HDMI_AVI_CON_EVERY_VSYNC               (1 << 1)
+
+/* AVI_CHECK_SUM */
+
+/* AVI_DATA01~13 */
+#define HDMI_AVI_PIXEL_REPETITION_DOUBLE	(1<<0)
+#define HDMI_AVI_PICTURE_ASPECT_4_3		(1<<4)
+#define HDMI_AVI_PICTURE_ASPECT_16_9		(1<<5)
+
+/* Audio InfoFrame Register */
+
+/* AUI_CON */
+#define HDMI_AUI_CON_NO_TRAN			(0 << 0)
+#define HDMI_AUI_CON_TRANS_ONCE			(1 << 0)
+#define HDMI_AUI_CON_TRANS_EVERY_VSYNC		(2 << 0)
+
+/* AUI_CHECK_SUM */
+
+/* AUI_DATA1~5 */
+
+/* MPEG Source InfoFrame registers */
+
+/* MPG_CON */
+
+/* HDMI_MPG_CHECK_SUM */
+
+/* MPG_DATA1~5 */
+
+/* Source Product Descriptor Infoframe registers */
+
+/* SPD_CON */
+
+/* SPD_HEADER0/1/2 */
+
+/* SPD_DATA0~27 */
+
+/* VSI_CON */
+#define HDMI_VSI_CON_DO_NOT_TRANSMIT		(0 << 0)
+#define HDMI_VSI_CON_EVERY_VSYNC		(1 << 1)
+
+/* VSI_DATA00 ~ 27 */
+#define HDMI_VSI_DATA04_VIDEO_FORMAT(x)		(x << 5)
+#define HDMI_VSI_DATA05_3D_STRUCTURE(x)		(x << 4)
+#define HDMI_VSI_DATA06_3D_EXT_DATA(x)		(x << 4)
+
+/* HDCP Register */
+
+/* HDCP_SHA1_00~19 */
+
+/* HDCP_KSV_LIST_0~4 */
+
+/* HDCP_KSV_LIST_CON */
+#define HDMI_HDCP_KSV_WRITE_DONE		(0x1 << 3)
+#define HDMI_HDCP_KSV_LIST_EMPTY		(0x1 << 2)
+#define HDMI_HDCP_KSV_END			(0x1 << 1)
+#define HDMI_HDCP_KSV_READ			(0x1 << 0)
+
+/* HDCP_CTRL1 */
+#define HDMI_HDCP_EN_PJ_EN			(1 << 4)
+#define HDMI_HDCP_EN_PJ_DIS			(~(1 << 4))
+#define HDMI_HDCP_SET_REPEATER_TIMEOUT		(1 << 2)
+#define HDMI_HDCP_CLEAR_REPEATER_TIMEOUT	(~(1 << 2))
+#define HDMI_HDCP_CP_DESIRED_EN			(1 << 1)
+#define HDMI_HDCP_CP_DESIRED_DIS		(~(1 << 1))
+#define HDMI_HDCP_ENABLE_1_1_FEATURE_EN		(1)
+#define HDMI_HDCP_ENABLE_1_1_FEATURE_DIS	(~(1))
+
+/* HDCP_CHECK_RESULT */
+#define HDMI_HDCP_PI_MATCH_RESULT_Y		((0x1 << 3) | (0x1 << 2))
+#define HDMI_HDCP_PI_MATCH_RESULT_N		((0x1 << 3) | (0x0 << 2))
+#define HDMI_HDCP_RI_MATCH_RESULT_Y		((0x1 << 1) | (0x1 << 0))
+#define HDMI_HDCP_RI_MATCH_RESULT_N		((0x1 << 1) | (0x0 << 0))
+#define HDMI_HDCP_CLR_ALL_RESULTS		(0)
+
+/* HDCP_BKSV0~4 */
+/* HDCP_AKSV0~4 */
+
+/* HDCP_BCAPS */
+#define HDMI_HDCP_BCAPS_REPEATER		(1 << 6)
+#define HDMI_HDCP_BCAPS_READY			(1 << 5)
+#define HDMI_HDCP_BCAPS_FAST			(1 << 4)
+#define HDMI_HDCP_BCAPS_1_1_FEATURES		(1 << 1)
+#define HDMI_HDCP_BCAPS_FAST_REAUTH		(1)
+
+/* HDCP_BSTATUS_0/1 */
+/* HDCP_Ri_0/1 */
+/* HDCP_I2C_INT */
+/* HDCP_AN_INT */
+/* HDCP_WATCHDOG_INT */
+/* HDCP_RI_INT/1 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_1 */
+/* HDCP_Frame_Count */
+
+/* Gamut Metadata Packet Register */
+
+/* GAMUT_CON */
+/* GAMUT_HEADER0 */
+/* GAMUT_HEADER1 */
+/* GAMUT_HEADER2 */
+/* GAMUT_METADATA0~27 */
+
+/* Video Mode Register */
+
+/* VIDEO_PATTERN_GEN */
+/* HPD_GEN */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+/* HDCP_Ri_Compare_0 */
+
+/* SPDIF Register */
+
+/* SPDIFIN_CLK_CTRL */
+#define HDMI_SPDIFIN_READY_CLK_DOWN		(1 << 1)
+#define HDMI_SPDIFIN_CLK_ON			(1 << 0)
+
+/* SPDIFIN_OP_CTRL */
+#define HDMI_SPDIFIN_SW_RESET			(0 << 0)
+#define HDMI_SPDIFIN_STATUS_CHECK_MODE		(1 << 0)
+#define HDMI_SPDIFIN_STATUS_CHECK_MODE_HDMI	(3 << 0)
+
+/* SPDIFIN_IRQ_MASK */
+
+/* SPDIFIN_IRQ_STATUS */
+#define HDMI_SPDIFIN_IRQ_OVERFLOW_EN				(1 << 7)
+#define HDMI_SPDIFIN_IRQ_ABNORMAL_PD_EN				(1 << 6)
+#define HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_RIGHTTIME_EN		(1 << 5)
+#define HDMI_SPDIFIN_IRQ_SH_DETECTED_EN				(1 << 4)
+#define HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_EN			(1 << 3)
+#define HDMI_SPDIFIN_IRQ_WRONG_PREAMBLE_EN			(1 << 2)
+#define HDMI_SPDIFIN_IRQ_CH_STATUS_RECOVERED_EN			(1 << 1)
+#define HDMI_SPDIFIN_IRQ_WRONG_SIG_EN				(1 << 0)
+
+/* SPDIFIN_CONFIG_1 */
+#define HDMI_SPDIFIN_CFG_NOISE_FILTER_2_SAMPLE			(1 << 6)
+#define HDMI_SPDIFIN_CFG_PCPD_MANUAL				(1 << 4)
+#define HDMI_SPDIFIN_CFG_WORD_LENGTH_MANUAL			(1 << 3)
+#define HDMI_SPDIFIN_CFG_UVCP_REPORT				(1 << 2)
+#define HDMI_SPDIFIN_CFG_HDMI_2_BURST				(1 << 1)
+#define HDMI_SPDIFIN_CFG_DATA_ALIGN_32				(1 << 0)
+
+/* SPDIFIN_CONFIG_2 */
+#define HDMI_SPDIFIN_CFG2_NO_CLK_DIV				(0)
+
+/* SPDIFIN_USER_VALUE_1 */
+#define HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_LOW(x)	((x & 0xf) << 4)
+#define HDMI_SPDIFIN_USER_VAL_WORD_LENGTH_24		(0xb << 0)
+#define HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_HIGH(x)	((x >> 4) & 0xff)
+/* SPDIFIN_USER_VALUE_2 */
+/* SPDIFIN_USER_VALUE_3 */
+/* SPDIFIN_USER_VALUE_4 */
+/* SPDIFIN_CH_STATUS_0_1 */
+/* SPDIFIN_CH_STATUS_0_2 */
+/* SPDIFIN_CH_STATUS_0_3 */
+/* SPDIFIN_CH_STATUS_0_4 */
+/* SPDIFIN_CH_STATUS_1 */
+/* SPDIFIN_FRAME_PERIOD_1 */
+/* SPDIFIN_FRAME_PERIOD_2 */
+/* SPDIFIN_PC_INFO_1 */
+/* SPDIFIN_PC_INFO_2 */
+/* SPDIFIN_PD_INFO_1 */
+/* SPDIFIN_PD_INFO_2 */
+/* SPDIFIN_DATA_BUF_0_1 */
+/* SPDIFIN_DATA_BUF_0_2 */
+/* SPDIFIN_DATA_BUF_0_3 */
+/* SPDIFIN_USER_BUF_0 */
+/* SPDIFIN_USER_BUF_1_1 */
+/* SPDIFIN_USER_BUF_1_2 */
+/* SPDIFIN_USER_BUF_1_3 */
+/* SPDIFIN_USER_BUF_1 */
+
+/* I2S Register */
+
+/* I2S_CLK_CON */
+#define HDMI_I2S_CLK_DISABLE			(0)
+#define HDMI_I2S_CLK_ENABLE			(1)
+
+/* I2S_CON_1 */
+#define HDMI_I2S_SCLK_FALLING_EDGE		(0 << 1)
+#define HDMI_I2S_SCLK_RISING_EDGE		(1 << 1)
+#define HDMI_I2S_L_CH_LOW_POL			(0)
+#define HDMI_I2S_L_CH_HIGH_POL			(1)
+
+/* I2S_CON_2 */
+#define HDMI_I2S_MSB_FIRST_MODE			(0 << 6)
+#define HDMI_I2S_LSB_FIRST_MODE			(1 << 6)
+#define HDMI_I2S_BIT_CH_32FS			(0 << 4)
+#define HDMI_I2S_BIT_CH_48FS			(1 << 4)
+#define HDMI_I2S_BIT_CH_RESERVED		(2 << 4)
+#define HDMI_I2S_SDATA_16BIT			(1 << 2)
+#define HDMI_I2S_SDATA_20BIT			(2 << 2)
+#define HDMI_I2S_SDATA_24BIT			(3 << 2)
+#define HDMI_I2S_BASIC_FORMAT			(0)
+#define HDMI_I2S_L_JUST_FORMAT			(2)
+#define HDMI_I2S_R_JUST_FORMAT			(3)
+#define HDMI_I2S_CON_2_CLR			(~(0xFF))
+#define HDMI_I2S_SET_BIT_CH(x)			(((x) & 0x7) << 4)
+#define HDMI_I2S_SET_SDATA_BIT(x)		(((x) & 0x7) << 2)
+
+/* I2S_PIN_SEL_0 */
+#define HDMI_I2S_SEL_SCLK(x)			(((x) & 0x7) << 4)
+#define HDMI_I2S_SEL_LRCK(x)			((x) & 0x7)
+
+/* I2S_PIN_SEL_1 */
+#define HDMI_I2S_SEL_SDATA1(x)			(((x) & 0x7) << 4)
+#define HDMI_I2S_SEL_SDATA0(x)			((x) & 0x7)
+
+/* I2S_PIN_SEL_2 */
+#define HDMI_I2S_SEL_SDATA3(x)			(((x) & 0x7) << 4)
+#define HDMI_I2S_SEL_SDATA2(x)			((x) & 0x7)
+
+/* I2S_PIN_SEL_3 */
+#define HDMI_I2S_SEL_DSD(x)			((x) & 0x7)
+
+/* I2S_DSD_CON */
+#define HDMI_I2S_DSD_CLK_RI_EDGE		(1 << 1)
+#define HDMI_I2S_DSD_CLK_FA_EDGE		(0 << 1)
+#define HDMI_I2S_DSD_ENABLE			(1 << 0)
+#define HDMI_I2S_DSD_DISABLE			(0 << 0)
+
+/* I2S_MUX_CON */
+#define HDMI_I2S_NOISE_FILTER_ZERO		(0 << 5)
+#define HDMI_I2S_NOISE_FILTER_2_STAGE		(1 << 5)
+#define HDMI_I2S_NOISE_FILTER_3_STAGE		(2 << 5)
+#define HDMI_I2S_NOISE_FILTER_4_STAGE		(3 << 5)
+#define HDMI_I2S_NOISE_FILTER_5_STAGE		(4 << 5)
+#define HDMI_I2S_IN_ENABLE			(1 << 4)
+#define HDMI_I2S_IN_DISABLE			(0 << 4)
+#define HDMI_I2S_AUD_SPDIF			(0 << 2)
+#define HDMI_I2S_AUD_I2S			(1 << 2)
+#define HDMI_I2S_AUD_DSD			(2 << 2)
+#define HDMI_I2S_CUV_SPDIF_ENABLE		(0 << 1)
+#define HDMI_I2S_CUV_I2S_ENABLE			(1 << 1)
+#define HDMI_I2S_MUX_DISABLE			(0 << 0)
+#define HDMI_I2S_MUX_ENABLE			(1 << 0)
+
+/* I2S_CH_ST_CON */
+#define HDMI_I2S_CH_STATUS_RELOAD		(1 << 0)
+#define HDMI_I2S_CH_ST_CON_CLR			(~(1))
+
+/* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
+#define HDMI_I2S_CH_STATUS_MODE_0		(0 << 6)
+#define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH	(0 << 3)
+#define HDMI_I2S_2AUD_CH_WITH_PREEMPH		(1 << 3)
+#define HDMI_I2S_DEFAULT_EMPHASIS		(0 << 3)
+#define HDMI_I2S_COPYRIGHT			(0 << 2)
+#define HDMI_I2S_NO_COPYRIGHT			(1 << 2)
+#define HDMI_I2S_LINEAR_PCM			(0 << 1)
+#define HDMI_I2S_NO_LINEAR_PCM			(1 << 1)
+#define HDMI_I2S_CONSUMER_FORMAT		(0)
+#define HDMI_I2S_PROF_FORMAT			(1)
+#define HDMI_I2S_CH_ST_0_CLR			(~(0xFF))
+
+/* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
+#define HDMI_I2S_CD_PLAYER			(0x00)
+#define HDMI_I2S_DAT_PLAYER			(0x03)
+#define HDMI_I2S_DCC_PLAYER			(0x43)
+#define HDMI_I2S_MINI_DISC_PLAYER		(0x49)
+
+/* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
+#define HDMI_I2S_CHANNEL_NUM_MASK		(0xF << 4)
+#define HDMI_I2S_SOURCE_NUM_MASK		(0xF)
+#define HDMI_I2S_SET_CHANNEL_NUM(x)		((x) & (0xF) << 4)
+#define HDMI_I2S_SET_SOURCE_NUM(x)		((x) & (0xF))
+
+/* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
+#define HDMI_I2S_CLK_ACCUR_LEVEL_1		(1 << 4)
+#define HDMI_I2S_CLK_ACCUR_LEVEL_2		(0 << 4)
+#define HDMI_I2S_CLK_ACCUR_LEVEL_3		(2 << 4)
+#define HDMI_I2S_SAMPLING_FREQ_44_1		(0x0)
+#define HDMI_I2S_SAMPLING_FREQ_48		(0x2)
+#define HDMI_I2S_SAMPLING_FREQ_32		(0x3)
+#define HDMI_I2S_SAMPLING_FREQ_96		(0xA)
+#define HDMI_I2S_SET_SAMPLING_FREQ(x)		((x) & (0xF))
+
+/* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
+#define HDMI_I2S_ORG_SAMPLING_FREQ_44_1		(0xF << 4)
+#define HDMI_I2S_ORG_SAMPLING_FREQ_88_2		(0x7 << 4)
+#define HDMI_I2S_ORG_SAMPLING_FREQ_22_05	(0xB << 4)
+#define HDMI_I2S_ORG_SAMPLING_FREQ_176_4	(0x3 << 4)
+#define HDMI_I2S_WORD_LENGTH_NOT_DEFINE		(0x0 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX24_20BITS	(0x1 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX24_22BITS	(0x2 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX24_23BITS	(0x4 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX24_24BITS	(0x5 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX24_21BITS	(0x6 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX20_16BITS	(0x1 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX20_18BITS	(0x2 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX20_19BITS	(0x4 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX20_20BITS	(0x5 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX20_17BITS	(0x6 << 1)
+#define HDMI_I2S_WORD_LENGTH_MAX_24BITS		(1)
+#define HDMI_I2S_WORD_LENGTH_MAX_20BITS		(0)
+
+/* I2S_VD_DATA */
+#define HDMI_I2S_VD_AUD_SAMPLE_RELIABLE		(0)
+#define HDMI_I2S_VD_AUD_SAMPLE_UNRELIABLE	(1)
+
+/* I2S_MUX_CH */
+#define HDMI_I2S_CH3_R_EN			(1 << 7)
+#define HDMI_I2S_CH3_L_EN			(1 << 6)
+#define HDMI_I2S_CH2_R_EN			(1 << 5)
+#define HDMI_I2S_CH2_L_EN			(1 << 4)
+#define HDMI_I2S_CH1_R_EN			(1 << 3)
+#define HDMI_I2S_CH1_L_EN			(1 << 2)
+#define HDMI_I2S_CH0_R_EN			(1 << 1)
+#define HDMI_I2S_CH0_L_EN			(1)
+#define HDMI_I2S_CH_ALL_EN			(0xFF)
+#define HDMI_I2S_MUX_CH_CLR			(~HDMI_I2S_CH_ALL_EN)
+
+/* I2S_MUX_CUV */
+#define HDMI_I2S_CUV_R_EN			(1 << 1)
+#define HDMI_I2S_CUV_L_EN			(1 << 0)
+#define HDMI_I2S_CUV_RL_EN			(0x03)
+
+/* I2S_IRQ_MASK */
+#define HDMI_I2S_INT2_DIS			(0 << 1)
+#define HDMI_I2S_INT2_EN			(1 << 1)
+
+/* I2S_IRQ_STATUS */
+#define HDMI_I2S_INT2_STATUS			(1 << 1)
+
+/* I2S_CH0_L_0 */
+/* I2S_CH0_L_1 */
+/* I2S_CH0_L_2 */
+/* I2S_CH0_L_3 */
+/* I2S_CH0_R_0 */
+/* I2S_CH0_R_1 */
+/* I2S_CH0_R_2 */
+/* I2S_CH0_R_3 */
+/* I2S_CH1_L_0 */
+/* I2S_CH1_L_1 */
+/* I2S_CH1_L_2 */
+/* I2S_CH1_L_3 */
+/* I2S_CH1_R_0 */
+/* I2S_CH1_R_1 */
+/* I2S_CH1_R_2 */
+/* I2S_CH1_R_3 */
+/* I2S_CH2_L_0 */
+/* I2S_CH2_L_1 */
+/* I2S_CH2_L_2 */
+/* I2S_CH2_L_3 */
+/* I2S_CH2_R_0 */
+/* I2S_CH2_R_1 */
+/* I2S_CH2_R_2 */
+/* I2S_Ch2_R_3 */
+/* I2S_CH3_L_0 */
+/* I2S_CH3_L_1 */
+/* I2S_CH3_L_2 */
+/* I2S_CH3_R_0 */
+/* I2S_CH3_R_1 */
+/* I2S_CH3_R_2 */
+
+/* I2S_CUV_L_R */
+#define HDMI_I2S_CUV_R_DATA_MASK		(0x7 << 4)
+#define HDMI_I2S_CUV_L_DATA_MASK		(0x7)
+
+/* Timing Generator Register */
+/* TG_CMD */
+#define HDMI_GETSYNC_TYPE			(1 << 4)
+#define HDMI_GETSYNC				(1 << 3)
+
+/* HDMI_TG_CMD */
+#define HDMI_FIELD_EN				(1 << 1)
+#define HDMI_TG_EN				(1 << 0)
+
+/* TG_CFG */
+/* TG_CB_SZ */
+/* TG_INDELAY_L */
+/* TG_INDELAY_H */
+/* TG_POL_CTRL */
+
+/* TG_H_FSZ_L */
+/* TG_H_FSZ_H */
+/* TG_HACT_ST_L */
+/* TG_HACT_ST_H */
+/* TG_HACT_SZ_L */
+/* TG_HACT_SZ_H */
+/* TG_V_FSZ_L */
+/* TG_V_FSZ_H */
+/* TG_VSYNC_L */
+/* TG_VSYNC_H */
+/* TG_VSYNC2_L */
+/* TG_VSYNC2_H */
+/* TG_VACT_ST_L */
+/* TG_VACT_ST_H */
+/* TG_VACT_SZ_L */
+/* TG_VACT_SZ_H */
+/* TG_FIELD_CHG_L */
+/* TG_FIELD_CHG_H */
+/* TG_VACT_ST2_L */
+/* TG_VACT_ST2_H */
+/* TG_VACT_SC_ST_L */
+/* TG_VACT_SC_ST_H */
+/* TG_VACT_SC_SZ_L */
+/* TG_VACT_SC_SZ_H */
+
+/* TG_VSYNC_TOP_HDMI_L */
+/* TG_VSYNC_TOP_HDMI_H */
+/* TG_VSYNC_BOT_HDMI_L */
+/* TG_VSYNC_BOT_HDMI_H */
+/* TG_FIELD_TOP_HDMI_L */
+/* TG_FIELD_TOP_HDMI_H */
+/* TG_FIELD_BOT_HDMI_L */
+/* TG_FIELD_BOT_HDMI_H */
+/* TG_HSYNC_HDOUT_ST_L */
+/* TG_HSYNC_HDOUT_ST_H */
+/* TG_HSYNC_HDOUT_END_L */
+/* TG_HSYNC_HDOUT_END_H */
+/* TG_VSYNC_HDOUT_ST_L */
+/* TG_VSYNC_HDOUT_ST_H */
+/* TG_VSYNC_HDOUT_END_L */
+/* TG_VSYNC_HDOUT_END_H */
+/* TG_VSYNC_HDOUT_DLY_L */
+/* TG_VSYNC_HDOUT_DLY_H */
+/* TG_BT_ERR_RANGE */
+/* TG_BT_ERR_RESULT */
+/* TG_COR_THR */
+/* TG_COR_NUM */
+/* TG_BT_CON */
+/* TG_BT_H_FSZ_L */
+/* TG_BT_H_FSZ_H */
+/* TG_BT_HSYNC_ST */
+/* TG_BT_HSYNC_SZ */
+/* TG_BT_FSZ_L */
+/* TG_BT_FSZ_H */
+/* TG_BT_VACT_T_ST_L */
+/* TG_BT_VACT_T_ST_H */
+/* TG_BT_VACT_B_ST_L */
+/* TG_BT_VACT_B_ST_H */
+/* TG_BT_VACT_SZ_L */
+/* TG_BT_VACT_SZ_H */
+/* TG_BT_VSYNC_SZ */
+
+/* HDCP E-FUSE Control Register */
+/* HDCP_E_FUSE_CTRL */
+#define HDMI_EFUSE_CTRL_HDCP_KEY_READ		(1 << 0)
+
+/* HDCP_E_FUSE_STATUS */
+#define HDMI_EFUSE_ECC_FAIL			(1 << 2)
+#define HDMI_EFUSE_ECC_BUSY			(1 << 1)
+#define HDMI_EFUSE_ECC_DONE			(1)
+
+/* EFUSE_ADDR_WIDTH */
+/* EFUSE_SIGDEV_ASSERT */
+/* EFUSE_SIGDEV_DE-ASSERT */
+/* EFUSE_PRCHG_ASSERT */
+/* EFUSE_PRCHG_DE-ASSERT */
+/* EFUSE_FSET_ASSERT */
+/* EFUSE_FSET_DE-ASSERT */
+/* EFUSE_SENSING */
+/* EFUSE_SCK_ASSERT */
+/* EFUSE_SCK_DEASSERT */
+/* EFUSE_SDOUT_OFFSET */
+/* EFUSE_READ_OFFSET */
+
+/* HDCP_SHA_RESULT */
+#define HDMI_HDCP_SHA_VALID_NO_RD		(0 << 1)
+#define HDMI_HDCP_SHA_VALID_RD			(1 << 1)
+#define HDMI_HDCP_SHA_VALID			(1)
+#define HDMI_HDCP_SHA_NO_VALID			(0)
+
+/* DC_CONTRAL */
+#define HDMI_DC_CTL_12				(1 << 1)
+#define HDMI_DC_CTL_8				(0)
+#define HDMI_DC_CTL_10				(1)
+#endif	/* __ARCH_ARM_REGS_HDMI_H */
diff --git a/drivers/media/video/exynos/tv/regs-mixer.h b/drivers/media/video/exynos/tv/regs-mixer.h
new file mode 100644
index 0000000..15ad119
--- /dev/null
+++ b/drivers/media/video/exynos/tv/regs-mixer.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Mixer register header file for Samsung Mixer driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef SAMSUNG_REGS_MIXER_H
+#define SAMSUNG_REGS_MIXER_H
+
+#include <plat/map-base.h>
+
+/* SYSREG for local path between Gscaler and Mixer */
+#define SYSREG_DISP1BLK_CFG		(S3C_VA_SYS + 0x0214)
+
+#define DISP1BLK_CFG_FIFORST_DISP1	(1 << 23)
+#define DISP1BLK_CFG_MIXER_MASK		(0x3F << 2)
+#define DISP1BLK_CFG_MIXER0_VALID	(1 << 7)
+#define DISP1BLK_CFG_MIXER0_SRC_GSC(x)	(x << 5)
+#define DISP1BLK_CFG_MIXER1_VALID	(1 << 4)
+#define DISP1BLK_CFG_MIXER1_SRC_GSC(x)	(x << 2)
+
+/*
+ * Register part
+ */
+#define MXR_STATUS			0x0000
+#define MXR_CFG				0x0004
+#define MXR_INT_EN			0x0008
+#define MXR_INT_STATUS			0x000C
+#define MXR_LAYER_CFG			0x0010
+#define MXR_VIDEO_CFG			0x0014
+#define MXR_GRAPHIC0_CFG		0x0020
+#define MXR_GRAPHIC0_BASE		0x0024
+#define MXR_GRAPHIC0_SPAN		0x0028
+#define MXR_GRAPHIC0_SXY		0x002C
+#define MXR_GRAPHIC0_WH			0x0030
+#define MXR_GRAPHIC0_DXY		0x0034
+#define MXR_GRAPHIC0_BLANK		0x0038
+#define MXR_GRAPHIC1_CFG		0x0040
+#define MXR_GRAPHIC1_BASE		0x0044
+#define MXR_GRAPHIC1_SPAN		0x0048
+#define MXR_GRAPHIC1_SXY		0x004C
+#define MXR_GRAPHIC1_WH			0x0050
+#define MXR_GRAPHIC1_DXY		0x0054
+#define MXR_GRAPHIC1_BLANK		0x0058
+#define MXR_BG_CFG			0x0060
+#define MXR_BG_COLOR0			0x0064
+#define MXR_BG_COLOR1			0x0068
+#define MXR_BG_COLOR2			0x006C
+#define MXR_CM_COEFF_Y			0x0080
+#define MXR_CM_COEFF_CB			0x0084
+#define MXR_CM_COEFF_CR			0x0088
+/* after EXYNOS5250 for video layer transfered from Gscaler */
+#define MXR_VIDEO_LT			0x0090
+#define MXR_VIDEO_RB			0x0094
+
+/* after EXYNOS4212 for setting 3D */
+#define MXR_TVOUT_CFG			0x0100
+#define MXR_3D_ACTIVE_VIDEO		0x0104
+#define MXR_3D_ACTIVE_SPACE		0x0108
+
+/* after EXYNOS5250, support 2 sub-mixers */
+#define MXR1_LAYER_CFG			0x0110
+#define MXR1_VIDEO_CFG			0x0114
+#define MXR1_GRAPHIC0_CFG		0x0120
+#define MXR1_GRAPHIC0_BASE		0x0124
+#define MXR1_GRAPHIC0_SPAN		0x0128
+#define MXR1_GRAPHIC0_SXY		0x012C
+#define MXR1_GRAPHIC0_WH		0x0130
+#define MXR1_GRAPHIC0_DXY		0x0134
+#define MXR1_GRAPHIC0_BLANK		0x0138
+#define MXR1_GRAPHIC1_CFG		0x0140
+#define MXR1_GRAPHIC1_BASE		0x0144
+#define MXR1_GRAPHIC1_SPAN		0x0148
+#define MXR1_GRAPHIC1_SXY		0x014C
+#define MXR1_GRAPHIC1_WH		0x0150
+#define MXR1_GRAPHIC1_DXY		0x0154
+#define MXR1_GRAPHIC1_BLANK		0x0158
+#define MXR1_BG_CFG			0x0160
+#define MXR1_BG_COLOR0			0x0164
+#define MXR1_BG_COLOR1			0x0168
+#define MXR1_BG_COLOR2			0x016C
+#define MXR1_CM_COEFF_Y			0x0180
+#define MXR1_CM_COEFF_CB		0x0184
+#define MXR1_CM_COEFF_CR		0x0188
+/* after EXYNOS5250 for video layer transfered from Gscaler */
+#define MXR1_VIDEO_LT			0x0190
+#define MXR1_VIDEO_RB			0x0194
+
+/* for parametrized access to layer registers */
+#define MXR_GRAPHIC_CFG(i)		(0x0020 + (i) * 0x20)
+#define MXR_GRAPHIC_BASE(i)		(0x0024 + (i) * 0x20)
+#define MXR_GRAPHIC_SPAN(i)		(0x0028 + (i) * 0x20)
+#define MXR_GRAPHIC_SXY(i)		(0x002C + (i) * 0x20)
+#define MXR_GRAPHIC_WH(i)		(0x0030 + (i) * 0x20)
+#define MXR_GRAPHIC_DXY(i)		(0x0034 + (i) * 0x20)
+#define MXR_GRAPHIC_BLANK(i)		(0x0038 + (i) * 0x20)
+
+/* after EXYNOS5250, support 2 sub-mixers */
+#define MXR1_GRAPHIC_CFG(i)		(0x0120 + (i) * 0x20)
+#define MXR1_GRAPHIC_BASE(i)		(0x0124 + (i) * 0x20)
+#define MXR1_GRAPHIC_SPAN(i)		(0x0128 + (i) * 0x20)
+#define MXR1_GRAPHIC_SXY(i)		(0x012C + (i) * 0x20)
+#define MXR1_GRAPHIC_WH(i)		(0x0130 + (i) * 0x20)
+#define MXR1_GRAPHIC_DXY(i)		(0x0134 + (i) * 0x20)
+#define MXR1_GRAPHIC_BLANK(i)		(0x0138 + (i) * 0x20)
+
+/*
+ * Bit definition part
+ */
+
+/* generates mask for range of bits */
+#define MXR_MASK(high_bit, low_bit) \
+	(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
+
+#define MXR_MASK_VAL(val, high_bit, low_bit) \
+	(((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
+
+/* bits for MXR_STATUS */
+#define MXR_STATUS_SOFT_RESET		(1 << 8)
+#define MXR_STATUS_16_BURST		(1 << 7)
+#define MXR_STATUS_BURST_MASK		(1 << 7)
+#define MXR_STATUS_LAYER_SYNC		(1 << 6)
+#define MXR_STATUS_SYNC_ENABLE		(1 << 2)
+#define MXR_STATUS_REG_RUN		(1 << 0)
+
+/* bits for MXR_CFG */
+#define MXR_CFG_LAYER_UPDATE            (1 << 31)
+#define MXR_CFG_LAYER_UPDATE_COUNTER    (3 << 29)
+#define MXR_CFG_MX1_GRP1_ENABLE		(1 << 15)
+#define MXR_CFG_MX1_GRP0_ENABLE		(1 << 14)
+#define MXR_CFG_MX1_VIDEO_ENABLE	(1 << 13)
+#define MXR_CFG_OUT_YUV444		(0 << 8)
+#define MXR_CFG_OUT_RGB888		(1 << 8)
+#define MXR_CFG_OUT_MASK		(1 << 8)
+#define MXR_CFG_DST_SDO			(0 << 7)
+#define MXR_CFG_DST_HDMI		(1 << 7)
+#define MXR_CFG_DST_MASK		(1 << 7)
+#define MXR_CFG_SCAN_HD_720		(0 << 6)
+#define MXR_CFG_SCAN_HD_1080		(1 << 6)
+#define MXR_CFG_GRP1_ENABLE		(1 << 5)
+#define MXR_CFG_GRP0_ENABLE		(1 << 4)
+#define MXR_CFG_VIDEO_ENABLE		(1 << 3)
+#define MXR_CFG_SCAN_INTERLACE		(0 << 2)
+#define MXR_CFG_SCAN_PROGRASSIVE	(1 << 2)
+#define MXR_CFG_SCAN_NTSC		(0 << 1)
+#define MXR_CFG_SCAN_PAL		(1 << 1)
+#define MXR_CFG_SCAN_SD			(0 << 0)
+#define MXR_CFG_SCAN_HD			(1 << 0)
+#define MXR_CFG_SCAN_MASK		0x47
+
+/* bits for MXR_GRAPHICn_CFG */
+#define MXR_GRP_CFG_BLANK_KEY_OFF	(1 << 21)
+#define MXR_GRP_CFG_LAYER_BLEND_EN	(1 << 17)
+#define MXR_GRP_CFG_PIXEL_BLEND_EN	(1 << 16)
+#define MXR_GRP_CFG_FORMAT_VAL(x)	MXR_MASK_VAL(x, 11, 8)
+#define MXR_GRP_CFG_FORMAT_MASK		MXR_GRP_CFG_FORMAT_VAL(~0)
+#define MXR_GRP_CFG_ALPHA_VAL(x)	MXR_MASK_VAL(x, 7, 0)
+
+/* bits for MXR_GRAPHICn_WH */
+#define MXR_GRP_WH_H_SCALE(x)		MXR_MASK_VAL(x, 28, 28)
+#define MXR_GRP_WH_V_SCALE(x)		MXR_MASK_VAL(x, 12, 12)
+#define MXR_GRP_WH_WIDTH(x)		MXR_MASK_VAL(x, 26, 16)
+#define MXR_GRP_WH_HEIGHT(x)		MXR_MASK_VAL(x, 10, 0)
+
+/* bits for MXR_GRAPHICn_SXY */
+#define MXR_GRP_SXY_SX(x)		MXR_MASK_VAL(x, 26, 16)
+#define MXR_GRP_SXY_SY(x)		MXR_MASK_VAL(x, 10, 0)
+
+/* bits for MXR_GRAPHICn_DXY */
+#define MXR_GRP_DXY_DX(x)		MXR_MASK_VAL(x, 26, 16)
+#define MXR_GRP_DXY_DY(x)		MXR_MASK_VAL(x, 10, 0)
+
+/* bits for MXR_INT_EN */
+#define MXR_INT_EN_VSYNC		(1 << 11)
+#define MXR_INT_EN_ALL			(0x38b80)
+
+/* bit for MXR_INT_STATUS */
+#define MXR_INT_STATUS_MX1_GRP1		(1 << 17)
+#define MXR_INT_STATUS_MX1_GRP0		(1 << 16)
+#define MXR_INT_STATUS_MX1_VIDEO	(1 << 15)
+#define MXR_INT_CLEAR_VSYNC		(1 << 11)
+#define MXR_INT_STATUS_MX0_GRP1		(1 << 9)
+#define MXR_INT_STATUS_MX0_GRP0		(1 << 8)
+#define MXR_INT_STATUS_MX0_VIDEO	(1 << 7)
+#define MXR_INT_STATUS_VSYNC		(1 << 0)
+
+/* bit for MXR_LAYER_CFG */
+#define MXR_LAYER_CFG_GRP1_VAL(x)	MXR_MASK_VAL(x, 11, 8)
+#define MXR_LAYER_CFG_GRP0_VAL(x)	MXR_MASK_VAL(x, 7, 4)
+#define MXR_LAYER_CFG_VP_VAL(x)		MXR_MASK_VAL(x, 3, 0)
+
+/* bit for MXR_VIDEO_CFG */
+#define MXR_VIDEO_CFG_BLEND_EN		(1 << 16)
+#define MXR_VIDEO_CFG_ALPHA(x)		MXR_MASK_VAL(x, 7, 0)
+
+/* bit for MXR_VIDEO_LT */
+#define MXR_VIDEO_LT_LEFT_VAL(x)	MXR_MASK_VAL(x, 31, 16)
+#define MXR_VIDEO_LT_TOP_VAL(x)		MXR_MASK_VAL(x, 15, 0)
+
+/* bit for MXR_VIDEO_RB */
+#define MXR_VIDEO_RB_RIGHT_VAL(x)	MXR_MASK_VAL(x, 31, 16)
+#define MXR_VIDEO_RB_BOTTOM_VAL(x)	MXR_MASK_VAL(x, 15, 0)
+
+/* bit for MXR_TVOUT_CFG */
+#define MXR_TVOUT_CFG_3D_FROMAT_VAL(x)	MXR_MASK_VAL(x, 5, 4)
+#define MXR_TVOUT_CFG_PATH_MIXER0	(0 << 3)
+#define MXR_TVOUT_CFG_PATH_MIXER1	(1 << 3)
+#define MXR_TVOUT_CFG_ONE_PATH		(1 << 2)
+#define MXR_TVOUT_CFG_TWO_PATH		(0 << 2)
+#define MXR_TVOUT_CFG_PATH_MASK		(3 << 2)
+#define MXR_TVOUT_CFG_STEREO_SCOPIC	(1 << 0)
+
+#endif /* SAMSUNG_REGS_MIXER_H */
diff --git a/drivers/media/video/exynos/tv/regs-sdo.h b/drivers/media/video/exynos/tv/regs-sdo.h
new file mode 100644
index 0000000..7f7c2b8
--- /dev/null
+++ b/drivers/media/video/exynos/tv/regs-sdo.h
@@ -0,0 +1,63 @@
+/* drivers/media/video/s5p-tv/regs-sdo.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * SDO register description file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef SAMSUNG_REGS_SDO_H
+#define SAMSUNG_REGS_SDO_H
+
+/*
+ * Register part
+ */
+
+#define SDO_CLKCON			0x0000
+#define SDO_CONFIG			0x0008
+#define SDO_VBI				0x0014
+#define SDO_DAC				0x003C
+#define SDO_CCCON			0x0180
+#define SDO_IRQ				0x0280
+#define SDO_IRQMASK			0x0284
+#define SDO_VERSION			0x03D8
+
+/*
+ * Bit definition part
+ */
+
+/* SDO Clock Control Register (SDO_CLKCON) */
+#define SDO_TVOUT_SW_RESET		(1 << 4)
+#define SDO_TVOUT_CLOCK_READY		(1 << 1)
+#define SDO_TVOUT_CLOCK_ON		(1 << 0)
+
+/* SDO Video Standard Configuration Register (SDO_CONFIG) */
+#define SDO_PROGRESSIVE			(1 << 4)
+#define SDO_NTSC_M			0
+#define SDO_PAL_M			1
+#define SDO_PAL_BGHID			2
+#define SDO_PAL_N			3
+#define SDO_PAL_NC			4
+#define SDO_NTSC_443			8
+#define SDO_PAL_60			9
+#define SDO_STANDARD_MASK		0xf
+
+/* SDO VBI Configuration Register (SDO_VBI) */
+#define SDO_CVBS_WSS_INS		(1 << 14)
+#define SDO_CVBS_CLOSED_CAPTION_MASK	(3 << 12)
+
+/* SDO DAC Configuration Register (SDO_DAC) */
+#define SDO_POWER_ON_DAC		(1 << 0)
+
+/* SDO Color Compensation On/Off Control (SDO_CCCON) */
+#define SDO_COMPENSATION_BHS_ADJ_OFF	(1 << 4)
+#define SDO_COMPENSATION_CVBS_COMP_OFF	(1 << 0)
+
+/* SDO Interrupt Request Register (SDO_IRQ) */
+#define SDO_VSYNC_IRQ_PEND		(1 << 0)
+
+#endif /* SAMSUNG_REGS_SDO_H */
diff --git a/drivers/media/video/exynos/tv/regs-vp.h b/drivers/media/video/exynos/tv/regs-vp.h
new file mode 100644
index 0000000..6c63984
--- /dev/null
+++ b/drivers/media/video/exynos/tv/regs-vp.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Video processor register header file for Samsung Mixer driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef SAMSUNG_REGS_VP_H
+#define SAMSUNG_REGS_VP_H
+
+/*
+ * Register part
+ */
+
+#define VP_ENABLE			0x0000
+#define VP_SRESET			0x0004
+#define VP_SHADOW_UPDATE		0x0008
+#define VP_FIELD_ID			0x000C
+#define VP_MODE				0x0010
+#define VP_IMG_SIZE_Y			0x0014
+#define VP_IMG_SIZE_C			0x0018
+#define VP_PER_RATE_CTRL		0x001C
+#define VP_TOP_Y_PTR			0x0028
+#define VP_BOT_Y_PTR			0x002C
+#define VP_TOP_C_PTR			0x0030
+#define VP_BOT_C_PTR			0x0034
+#define VP_ENDIAN_MODE			0x03CC
+#define VP_SRC_H_POSITION		0x0044
+#define VP_SRC_V_POSITION		0x0048
+#define VP_SRC_WIDTH			0x004C
+#define VP_SRC_HEIGHT			0x0050
+#define VP_DST_H_POSITION		0x0054
+#define VP_DST_V_POSITION		0x0058
+#define VP_DST_WIDTH			0x005C
+#define VP_DST_HEIGHT			0x0060
+#define VP_H_RATIO			0x0064
+#define VP_V_RATIO			0x0068
+#define VP_POLY8_Y0_LL			0x006C
+#define VP_POLY4_Y0_LL			0x00EC
+#define VP_POLY4_C0_LL			0x012C
+
+/*
+ * Bit definition part
+ */
+
+/* generates mask for range of bits */
+
+#define VP_MASK(high_bit, low_bit) \
+	(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
+
+#define VP_MASK_VAL(val, high_bit, low_bit) \
+	(((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
+
+ /* VP_ENABLE */
+#define VP_ENABLE_ON			(1 << 0)
+
+/* VP_SRESET */
+#define VP_SRESET_PROCESSING		(1 << 0)
+
+/* VP_SHADOW_UPDATE */
+#define VP_SHADOW_UPDATE_ENABLE		(1 << 0)
+
+/* VP_MODE */
+#define VP_MODE_NV12			(0 << 6)
+#define VP_MODE_NV21			(1 << 6)
+#define VP_MODE_LINE_SKIP		(1 << 5)
+#define VP_MODE_MEM_LINEAR		(0 << 4)
+#define VP_MODE_MEM_TILED		(1 << 4)
+#define VP_MODE_FMT_MASK		(5 << 4)
+#define VP_MODE_FIELD_ID_AUTO_TOGGLING	(1 << 2)
+#define VP_MODE_2D_IPC			(1 << 1)
+
+/* VP_IMG_SIZE_Y */
+/* VP_IMG_SIZE_C */
+#define VP_IMG_HSIZE(x)			VP_MASK_VAL(x, 29, 16)
+#define VP_IMG_VSIZE(x)			VP_MASK_VAL(x, 13, 0)
+
+/* VP_SRC_H_POSITION */
+#define VP_SRC_H_POSITION_VAL(x)	VP_MASK_VAL(x, 14, 4)
+
+/* VP_ENDIAN_MODE */
+#define VP_ENDIAN_MODE_LITTLE		(1 << 0)
+
+#endif /* SAMSUNG_REGS_VP_H */
diff --git a/drivers/media/video/exynos/tv/sdo_drv.c b/drivers/media/video/exynos/tv/sdo_drv.c
new file mode 100644
index 0000000..c2975db
--- /dev/null
+++ b/drivers/media/video/exynos/tv/sdo_drv.c
@@ -0,0 +1,540 @@
+/*
+ * Samsung Standard Definition Output (SDO) driver
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * Tomasz Stanislawski, <t.stanislaws@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#include <media/v4l2-subdev.h>
+#include <media/exynos_mc.h>
+
+#include "regs-sdo.h"
+
+MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
+MODULE_DESCRIPTION("Samsung Standard Definition Output (SDO)");
+MODULE_LICENSE("GPL");
+
+/* SDO pad definitions */
+#define SDO_PAD_SINK		0
+#define SDO_PADS_NUM		1
+
+#define SDO_DEFAULT_STD	V4L2_STD_PAL
+
+struct sdo_format {
+	v4l2_std_id id;
+	/* all modes are 720 pixels wide */
+	unsigned int height;
+	unsigned int cookie;
+};
+
+struct sdo_device {
+	/** pointer to device parent */
+	struct device *dev;
+	/** base address of SDO registers */
+	void __iomem *regs;
+	/** SDO interrupt */
+	unsigned int irq;
+	/** DAC source clock */
+	struct clk *sclk_dac;
+	/** DAC clock */
+	struct clk *dac;
+	/** DAC physical interface */
+	struct clk *dacphy;
+	/** clock for control of VPLL */
+	struct clk *fout_vpll;
+	/** regulator for SDO IP power */
+	struct regulator *vdac;
+	/** regulator for SDO plug detection */
+	struct regulator *vdet;
+	/** subdev used as device interface */
+	struct v4l2_subdev sd;
+	/** sink pad connected to mixer */
+	struct media_pad pad;
+	/** current format */
+	const struct sdo_format *fmt;
+};
+
+static inline struct sdo_device *sd_to_sdev(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct sdo_device, sd);
+}
+
+static inline
+void sdo_write_mask(struct sdo_device *sdev, u32 reg_id, u32 value, u32 mask)
+{
+	u32 old = readl(sdev->regs + reg_id);
+	value = (value & mask) | (old & ~mask);
+	writel(value, sdev->regs + reg_id);
+}
+
+static inline
+void sdo_write(struct sdo_device *sdev, u32 reg_id, u32 value)
+{
+	writel(value, sdev->regs + reg_id);
+}
+
+static inline
+u32 sdo_read(struct sdo_device *sdev, u32 reg_id)
+{
+	return readl(sdev->regs + reg_id);
+}
+
+static irqreturn_t sdo_irq_handler(int irq, void *dev_data)
+{
+	struct sdo_device *sdev = dev_data;
+
+	/* clear interrupt */
+	sdo_write_mask(sdev, SDO_IRQ, ~0, SDO_VSYNC_IRQ_PEND);
+	return IRQ_HANDLED;
+}
+
+static void sdo_reg_debug(struct sdo_device *sdev)
+{
+#define DBGREG(reg_id) \
+	dev_info(sdev->dev, #reg_id " = %08x\n", \
+		sdo_read(sdev, reg_id))
+
+	DBGREG(SDO_CLKCON);
+	DBGREG(SDO_CONFIG);
+	DBGREG(SDO_VBI);
+	DBGREG(SDO_DAC);
+	DBGREG(SDO_IRQ);
+	DBGREG(SDO_IRQMASK);
+	DBGREG(SDO_VERSION);
+}
+
+static const struct sdo_format sdo_format[] = {
+	{ V4L2_STD_PAL_N,	.height = 576, .cookie = SDO_PAL_N },
+	{ V4L2_STD_PAL_Nc,	.height = 576, .cookie = SDO_PAL_NC },
+	{ V4L2_STD_PAL_M,	.height = 480, .cookie = SDO_PAL_M },
+	{ V4L2_STD_PAL_60,	.height = 480, .cookie = SDO_PAL_60 },
+	{ V4L2_STD_NTSC_443,	.height = 480, .cookie = SDO_NTSC_443 },
+	{ V4L2_STD_PAL,		.height = 576, .cookie = SDO_PAL_BGHID },
+	{ V4L2_STD_NTSC_M,	.height = 480, .cookie = SDO_NTSC_M },
+};
+
+static const struct sdo_format *sdo_find_format(v4l2_std_id id)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(sdo_format); ++i)
+		if (sdo_format[i].id & id)
+			return &sdo_format[i];
+	return NULL;
+}
+
+static int sdo_g_tvnorms_output(struct v4l2_subdev *sd, v4l2_std_id *std)
+{
+	*std = V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL |
+		V4L2_STD_PAL_N | V4L2_STD_PAL_Nc |
+		V4L2_STD_NTSC_443 | V4L2_STD_PAL_60;
+	return 0;
+}
+
+static int sdo_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
+{
+	struct sdo_device *sdev = sd_to_sdev(sd);
+	const struct sdo_format *fmt;
+	fmt = sdo_find_format(std);
+	if (fmt == NULL)
+		return -EINVAL;
+	sdev->fmt = fmt;
+	return 0;
+}
+
+static int sdo_g_std_output(struct v4l2_subdev *sd, v4l2_std_id *std)
+{
+	*std = sd_to_sdev(sd)->fmt->id;
+	return 0;
+}
+
+static int sdo_g_mbus_fmt(struct v4l2_subdev *sd,
+	struct v4l2_mbus_framefmt *fmt)
+{
+	struct sdo_device *sdev = sd_to_sdev(sd);
+
+	if (!sdev->fmt)
+		return -ENXIO;
+	/* all modes are 720 pixels wide */
+	fmt->width = 720;
+	fmt->height = sdev->fmt->height;
+	fmt->code = V4L2_MBUS_FMT_FIXED;
+	fmt->field = V4L2_FIELD_INTERLACED;
+	return 0;
+}
+
+static int sdo_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct sdo_device *sdev = sd_to_sdev(sd);
+	struct device *dev = sdev->dev;
+	int ret;
+
+	dev_info(dev, "sdo_s_power(%d)\n", on);
+
+	if (on)
+		ret = pm_runtime_get_sync(dev);
+	else
+		ret = pm_runtime_put_sync(dev);
+
+	/* only values < 0 indicate errors */
+	return IS_ERR_VALUE(ret) ? ret : 0;
+}
+
+static int sdo_streamon(struct sdo_device *sdev)
+{
+	/* set proper clock for Timing Generator */
+	clk_set_rate(sdev->fout_vpll, 54000000);
+	dev_info(sdev->dev, "fout_vpll.rate = %lu\n",
+	clk_get_rate(sdev->fout_vpll));
+	/* enable clock in SDO */
+	sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_CLOCK_ON);
+	clk_enable(sdev->dacphy);
+	/* enable DAC */
+	sdo_write_mask(sdev, SDO_DAC, ~0, SDO_POWER_ON_DAC);
+	sdo_reg_debug(sdev);
+	return 0;
+}
+
+static int sdo_streamoff(struct sdo_device *sdev)
+{
+	int tries;
+
+	sdo_write_mask(sdev, SDO_DAC, 0, SDO_POWER_ON_DAC);
+	clk_disable(sdev->dacphy);
+	sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
+	for (tries = 100; tries; --tries) {
+		if (sdo_read(sdev, SDO_CLKCON) & SDO_TVOUT_CLOCK_READY)
+			break;
+		mdelay(1);
+	}
+	if (tries == 0)
+		dev_err(sdev->dev, "failed to stop streaming\n");
+	return tries ? 0 : -EIO;
+}
+
+static int sdo_s_stream(struct v4l2_subdev *sd, int on)
+{
+	struct sdo_device *sdev = sd_to_sdev(sd);
+	return on ? sdo_streamon(sdev) : sdo_streamoff(sdev);
+}
+
+static const struct v4l2_subdev_core_ops sdo_sd_core_ops = {
+	.s_power = sdo_s_power,
+};
+
+static const struct v4l2_subdev_video_ops sdo_sd_video_ops = {
+	.s_std_output = sdo_s_std_output,
+	.g_std_output = sdo_g_std_output,
+	.g_tvnorms_output = sdo_g_tvnorms_output,
+	.g_mbus_fmt = sdo_g_mbus_fmt,
+	.s_stream = sdo_s_stream,
+};
+
+static const struct v4l2_subdev_ops sdo_sd_ops = {
+	.core = &sdo_sd_core_ops,
+	.video = &sdo_sd_video_ops,
+};
+
+static int sdo_runtime_suspend(struct device *dev)
+{
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
+	struct sdo_device *sdev = sd_to_sdev(sd);
+
+	dev_info(dev, "suspend\n");
+	regulator_disable(sdev->vdet);
+	regulator_disable(sdev->vdac);
+	clk_disable(sdev->sclk_dac);
+	return 0;
+}
+
+static int sdo_runtime_resume(struct device *dev)
+{
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
+	struct sdo_device *sdev = sd_to_sdev(sd);
+
+	dev_info(dev, "resume\n");
+	clk_enable(sdev->sclk_dac);
+	regulator_enable(sdev->vdac);
+	regulator_enable(sdev->vdet);
+
+	/* software reset */
+	sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_SW_RESET);
+	mdelay(10);
+	sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_SW_RESET);
+
+	/* setting TV mode */
+	sdo_write_mask(sdev, SDO_CONFIG, sdev->fmt->cookie, SDO_STANDARD_MASK);
+	/* XXX: forcing interlaced mode using undocumented bit */
+	sdo_write_mask(sdev, SDO_CONFIG, 0, SDO_PROGRESSIVE);
+	/* turn all VBI off */
+	sdo_write_mask(sdev, SDO_VBI, 0, SDO_CVBS_WSS_INS |
+		SDO_CVBS_CLOSED_CAPTION_MASK);
+	/* turn all post processing off */
+	sdo_write_mask(sdev, SDO_CCCON, ~0, SDO_COMPENSATION_BHS_ADJ_OFF |
+		SDO_COMPENSATION_CVBS_COMP_OFF);
+	sdo_reg_debug(sdev);
+	return 0;
+}
+
+static const struct dev_pm_ops sdo_pm_ops = {
+	.runtime_suspend = sdo_runtime_suspend,
+	.runtime_resume	 = sdo_runtime_resume,
+};
+
+static int sdo_link_setup(struct media_entity *entity,
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
+{
+	return 0;
+}
+
+/* sdo entity operations */
+static const struct media_entity_operations sdo_entity_ops = {
+	.link_setup = sdo_link_setup,
+};
+
+static int sdo_register_entity(struct sdo_device *sdev)
+{
+	struct v4l2_subdev *sd = &sdev->sd;
+	struct v4l2_device *v4l2_dev;
+	struct media_pad *pads = &sdev->pad;
+	struct media_entity *me = &sd->entity;
+	struct device *dev = sdev->dev;
+	struct exynos_md *md;
+	int ret;
+
+	dev_dbg(dev, "SDO entity init\n");
+
+	/* init sdo subdev */
+	v4l2_subdev_init(sd, &sdo_sd_ops);
+	sd->owner = THIS_MODULE;
+	strlcpy(sd->name, "s5p-sdo", sizeof(sd->name));
+
+	dev_set_drvdata(dev, sd);
+
+	/* init sdo sub-device as entity */
+	pads[SDO_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	me->ops = &sdo_entity_ops;
+	ret = media_entity_init(me, SDO_PADS_NUM, pads, 0);
+	if (ret) {
+		dev_err(dev, "failed to initialize media entity\n");
+		return ret;
+	}
+
+	/* get output media ptr for registering sdo's sd */
+	md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
+	if (!md) {
+		dev_err(dev, "failed to get output media device\n");
+		return -ENODEV;
+	}
+
+	v4l2_dev = &md->v4l2_dev;
+
+	/* regiser SDO subdev as entity to v4l2_dev pointer of
+	 * output media device
+	 */
+	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+	if (ret) {
+		dev_err(dev, "failed to register SDO subdev\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sdo_entity_info_print(struct sdo_device *sdev)
+{
+	struct v4l2_subdev *sd = &sdev->sd;
+	struct media_entity *me = &sd->entity;
+
+	dev_dbg(sdev->dev, "\n************** SDO entity info **************\n");
+	dev_dbg(sdev->dev, "[SUB DEVICE INFO]\n");
+	entity_info_print(me, sdev->dev);
+	dev_dbg(sdev->dev, "*********************************************\n\n");
+}
+
+static int __devinit sdo_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct sdo_device *sdev;
+	struct resource *res;
+	int ret = 0;
+	struct clk *sclk_vpll;
+
+	dev_info(dev, "probe start\n");
+	sdev = kzalloc(sizeof *sdev, GFP_KERNEL);
+	if (!sdev) {
+		dev_err(dev, "not enough memory.\n");
+		ret = -ENOMEM;
+		goto fail;
+	}
+	sdev->dev = dev;
+
+	/* mapping registers */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "get memory resource failed.\n");
+		ret = -ENXIO;
+		goto fail_sdev;
+	}
+
+	sdev->regs = ioremap(res->start, resource_size(res));
+	if (sdev->regs == NULL) {
+		dev_err(dev, "register mapping failed.\n");
+		ret = -ENXIO;
+		goto fail_sdev;
+	}
+
+	/* acquiring interrupt */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(dev, "get interrupt resource failed.\n");
+		ret = -ENXIO;
+		goto fail_regs;
+	}
+	ret = request_irq(res->start, sdo_irq_handler, 0, "s5p-sdo", sdev);
+	if (ret) {
+		dev_err(dev, "request interrupt failed.\n");
+		goto fail_regs;
+	}
+	sdev->irq = res->start;
+
+	/* acquire clocks */
+	sdev->sclk_dac = clk_get(dev, "sclk_dac");
+	if (IS_ERR_OR_NULL(sdev->sclk_dac)) {
+		dev_err(dev, "failed to get clock 'sclk_dac'\n");
+		ret = -ENXIO;
+		goto fail_irq;
+	}
+	sdev->dac = clk_get(dev, "dac");
+	if (IS_ERR_OR_NULL(sdev->dac)) {
+		dev_err(dev, "failed to get clock 'dac'\n");
+		ret = -ENXIO;
+		goto fail_sclk_dac;
+	}
+	sdev->dacphy = clk_get(dev, "dacphy");
+	if (IS_ERR_OR_NULL(sdev->dacphy)) {
+		dev_err(dev, "failed to get clock 'dacphy'\n");
+		ret = -ENXIO;
+		goto fail_dac;
+	}
+	sclk_vpll = clk_get(dev, "sclk_vpll");
+	if (IS_ERR_OR_NULL(sclk_vpll)) {
+		dev_err(dev, "failed to get clock 'sclk_vpll'\n");
+		ret = -ENXIO;
+		goto fail_dacphy;
+	}
+	clk_set_parent(sdev->sclk_dac, sclk_vpll);
+	clk_put(sclk_vpll);
+	sdev->fout_vpll = clk_get(dev, "fout_vpll");
+	if (IS_ERR_OR_NULL(sdev->fout_vpll)) {
+		dev_err(dev, "failed to get clock 'fout_vpll'\n");
+		goto fail_dacphy;
+	}
+	dev_info(dev, "fout_vpll.rate = %lu\n", clk_get_rate(sclk_vpll));
+
+	/* enable gate for dac clock, because mixer uses it */
+	clk_enable(sdev->dac);
+
+	/* configure power management */
+	pm_runtime_enable(dev);
+
+	/* set default format */
+	sdev->fmt = sdo_find_format(SDO_DEFAULT_STD);
+	BUG_ON(sdev->fmt == NULL);
+
+	ret = sdo_register_entity(sdev);
+	if (ret)
+		goto fail_dacphy;
+
+	sdo_entity_info_print(sdev);
+
+	dev_info(dev, "probe succeeded\n");
+	return 0;
+
+fail_dacphy:
+	clk_put(sdev->dacphy);
+fail_dac:
+	clk_put(sdev->dac);
+fail_sclk_dac:
+	clk_put(sdev->sclk_dac);
+fail_irq:
+	free_irq(sdev->irq, sdev);
+fail_regs:
+	iounmap(sdev->regs);
+fail_sdev:
+	kfree(sdev);
+fail:
+	dev_info(dev, "probe failed\n");
+	return ret;
+}
+
+static int __devexit sdo_remove(struct platform_device *pdev)
+{
+	struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
+	struct sdo_device *sdev = sd_to_sdev(sd);
+
+	pm_runtime_disable(&pdev->dev);
+	clk_disable(sdev->dac);
+	regulator_put(sdev->vdet);
+	regulator_put(sdev->vdac);
+	clk_put(sdev->fout_vpll);
+	clk_put(sdev->dacphy);
+	clk_put(sdev->dac);
+	clk_put(sdev->sclk_dac);
+	free_irq(sdev->irq, sdev);
+	iounmap(sdev->regs);
+	kfree(sdev);
+
+	dev_info(&pdev->dev, "remove successful\n");
+	return 0;
+}
+
+static struct platform_driver sdo_driver __refdata = {
+	.probe = sdo_probe,
+	.remove = __devexit_p(sdo_remove),
+	.driver = {
+		.name = "s5p-sdo",
+		.owner = THIS_MODULE,
+		.pm = &sdo_pm_ops,
+	}
+};
+
+static int __init sdo_init(void)
+{
+	int ret;
+	static const char banner[] __initdata = KERN_INFO \
+		"Samsung Standard Definition Output (SDO) driver, "
+		"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
+	printk(banner);
+
+	ret = platform_driver_register(&sdo_driver);
+	if (ret)
+		printk(KERN_ERR "SDO platform driver register failed\n");
+
+	return ret;
+}
+module_init(sdo_init);
+
+static void __exit sdo_exit(void)
+{
+	platform_driver_unregister(&sdo_driver);
+}
+module_exit(sdo_exit);
diff --git a/drivers/media/video/isx012.c b/drivers/media/video/isx012.c
new file mode 100644
index 0000000..ff2cbb0
--- /dev/null
+++ b/drivers/media/video/isx012.c
@@ -0,0 +1,3720 @@
+/* drivers/media/video/isx012.c
+ *
+ * Copyright (c) 2010, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * - change date: 2012.04.25
+ */
+#include "isx012.h"
+#include <linux/gpio.h>
+
+#define isx012_readb(sd, addr, data) isx012_i2c_read(sd, addr, data, 1)
+#define isx012_readw(sd, addr, data) isx012_i2c_read(sd, addr, data, 2)
+#define isx012_readl(sd, addr, data) isx012_i2c_read(sd, addr, data, 4)
+#define isx012_writeb(sd, addr, data) isx012_i2c_write(sd, addr, data, 1)
+#define isx012_writew(sd, addr, data) isx012_i2c_write(sd, addr, data, 2)
+#define isx012_writel(sd, addr, data) isx012_i2c_write(sd, addr, data, 4)
+
+static const struct isx012_fps isx012_framerates[] = {
+	{ I_FPS_0,	FRAME_RATE_AUTO },
+	{ I_FPS_15,	FRAME_RATE_15 },
+	{ I_FPS_25,	FRAME_RATE_25 },
+	{ I_FPS_30,	FRAME_RATE_30 },
+};
+
+static const struct isx012_framesize isx012_preview_frmsizes[] = {
+	{ PREVIEW_SZ_QCIF,	176,  144 },
+	{ PREVIEW_SZ_320x240,	320,  240 },
+	{ PREVIEW_SZ_CIF,	352,  288 },
+	{ PREVIEW_SZ_528x432,	528,  432 },
+	{ PREVIEW_SZ_VGA,	640,  480 },
+	{ PREVIEW_SZ_D1,	720,  480 },
+	{ PREVIEW_SZ_880x720,	880,  720 },
+	/*{ PREVIEW_SZ_SVGA,	800,  600 },*/
+	{ PREVIEW_SZ_1024x576,	1024, 576 },
+	/*{ PREVIEW_SZ_1024x616,1024, 616 },*/
+	{ PREVIEW_SZ_XGA,	1024, 768 },
+	{ PREVIEW_SZ_PVGA,	1280, 720 },
+};
+
+static const struct isx012_framesize isx012_capture_frmsizes[] = {
+	{ CAPTURE_SZ_VGA,	640,  480 },
+	{ CAPTURE_SZ_W1MP,	1536, 864 },
+	{ CAPTURE_SZ_2MP,	1600, 1200 },
+	{ CAPTURE_SZ_W2MP,	2048, 1152 },
+	{ CAPTURE_SZ_3MP,	2048, 1536 },
+	{ CAPTURE_SZ_W4MP,	2560, 1440 },
+	{ CAPTURE_SZ_5MP,	2560, 1920 },
+};
+
+static struct isx012_control isx012_ctrls[] = {
+	ISX012_INIT_CONTROL(V4L2_CID_CAMERA_FLASH_MODE, \
+					FLASH_MODE_OFF),
+
+	ISX012_INIT_CONTROL(V4L2_CID_CAMERA_BRIGHTNESS, \
+					EV_DEFAULT),
+
+	ISX012_INIT_CONTROL(V4L2_CID_CAMERA_METERING, \
+					METERING_MATRIX),
+
+	ISX012_INIT_CONTROL(V4L2_CID_CAMERA_WHITE_BALANCE, \
+					WHITE_BALANCE_AUTO),
+
+	ISX012_INIT_CONTROL(V4L2_CID_CAMERA_EFFECT, \
+					IMAGE_EFFECT_NONE),
+};
+
+static const struct isx012_regs reg_datas = {
+	.ev = {
+		ISX012_REGSET(GET_EV_INDEX(EV_MINUS_4),
+					ISX012_ExpSetting_M4Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_MINUS_3),
+					ISX012_ExpSetting_M3Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_MINUS_2),
+					ISX012_ExpSetting_M2Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_MINUS_1),
+					ISX012_ExpSetting_M1Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_DEFAULT),
+					ISX012_ExpSetting_Default),
+		ISX012_REGSET(GET_EV_INDEX(EV_PLUS_1),
+					ISX012_ExpSetting_P1Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_PLUS_2),
+					ISX012_ExpSetting_P2Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_PLUS_3),
+					ISX012_ExpSetting_P3Step),
+		ISX012_REGSET(GET_EV_INDEX(EV_PLUS_4),
+					ISX012_ExpSetting_P4Step),
+	},
+	.metering = {
+		ISX012_REGSET(METERING_MATRIX, isx012_Metering_Matrix),
+		ISX012_REGSET(METERING_CENTER, isx012_Metering_Center),
+		ISX012_REGSET(METERING_SPOT, isx012_Metering_Spot),
+	},
+	.iso = {
+		ISX012_REGSET(ISO_AUTO, isx012_ISO_Auto),
+		ISX012_REGSET(ISO_50, isx012_ISO_50),
+		ISX012_REGSET(ISO_100, isx012_ISO_100),
+		ISX012_REGSET(ISO_200, isx012_ISO_200),
+		ISX012_REGSET(ISO_400, isx012_ISO_400),
+	},
+	.effect = {
+		ISX012_REGSET(IMAGE_EFFECT_NONE, isx012_Effect_Normal),
+		ISX012_REGSET(IMAGE_EFFECT_BNW, isx012_Effect_Black_White),
+		ISX012_REGSET(IMAGE_EFFECT_SEPIA, isx012_Effect_Sepia),
+		ISX012_REGSET(IMAGE_EFFECT_NEGATIVE,
+				ISX012_Effect_Negative),
+	},
+	.white_balance = {
+		ISX012_REGSET(WHITE_BALANCE_AUTO, isx012_WB_Auto),
+		ISX012_REGSET(WHITE_BALANCE_SUNNY, isx012_WB_Sunny),
+		ISX012_REGSET(WHITE_BALANCE_CLOUDY, isx012_WB_Cloudy),
+		ISX012_REGSET(WHITE_BALANCE_TUNGSTEN,
+				isx012_WB_Tungsten),
+		ISX012_REGSET(WHITE_BALANCE_FLUORESCENT,
+				isx012_WB_Fluorescent),
+	},
+	.scene_mode = {
+		ISX012_REGSET(SCENE_MODE_NONE, isx012_Scene_Default),
+		ISX012_REGSET(SCENE_MODE_PORTRAIT, isx012_Scene_Portrait),
+		ISX012_REGSET(SCENE_MODE_NIGHTSHOT, isx012_Scene_Nightshot),
+		ISX012_REGSET(SCENE_MODE_BACK_LIGHT, isx012_Scene_Backlight),
+		ISX012_REGSET(SCENE_MODE_LANDSCAPE, isx012_Scene_Landscape),
+		ISX012_REGSET(SCENE_MODE_SPORTS, isx012_Scene_Sports),
+		ISX012_REGSET(SCENE_MODE_PARTY_INDOOR,
+				isx012_Scene_Party_Indoor),
+		ISX012_REGSET(SCENE_MODE_BEACH_SNOW, isx012_Scene_Beach_Snow),
+		ISX012_REGSET(SCENE_MODE_SUNSET, isx012_Scene_Sunset),
+		ISX012_REGSET(SCENE_MODE_DUSK_DAWN, isx012_Scene_Duskdawn),
+		ISX012_REGSET(SCENE_MODE_FALL_COLOR, isx012_Scene_Fall_Color),
+		ISX012_REGSET(SCENE_MODE_FIREWORKS, isx012_Scene_Fireworks),
+		ISX012_REGSET(SCENE_MODE_TEXT, isx012_Scene_Text),
+		ISX012_REGSET(SCENE_MODE_CANDLE_LIGHT,
+				isx012_Scene_Candle_Light),
+	},
+	.saturation = {
+		ISX012_REGSET(SATURATION_MINUS_2, isx012_Saturation_Minus_2),
+		ISX012_REGSET(SATURATION_MINUS_1, isx012_Saturation_Minus_1),
+		ISX012_REGSET(SATURATION_DEFAULT, isx012_Saturation_Default),
+		ISX012_REGSET(SATURATION_PLUS_1, isx012_Saturation_Plus_1),
+		ISX012_REGSET(SATURATION_PLUS_2, isx012_Saturation_Plus_2),
+	},
+	.contrast = {
+		ISX012_REGSET(CONTRAST_MINUS_2, isx012_Contrast_Minus_2),
+		ISX012_REGSET(CONTRAST_MINUS_1, isx012_Contrast_Minus_1),
+		ISX012_REGSET(CONTRAST_DEFAULT, isx012_Contrast_Default),
+		ISX012_REGSET(CONTRAST_PLUS_1, isx012_Contrast_Plus_1),
+		ISX012_REGSET(CONTRAST_PLUS_2, isx012_Contrast_Plus_2),
+
+	},
+	.sharpness = {
+		ISX012_REGSET(SHARPNESS_MINUS_2, isx012_Sharpness_Minus_2),
+		ISX012_REGSET(SHARPNESS_MINUS_1, isx012_Sharpness_Minus_1),
+		ISX012_REGSET(SHARPNESS_DEFAULT, isx012_Sharpness_Default),
+		ISX012_REGSET(SHARPNESS_PLUS_1, isx012_Sharpness_Plus_1),
+		ISX012_REGSET(SHARPNESS_PLUS_2, isx012_Sharpness_Plus_2),
+	},
+
+	.fps = {
+		ISX012_REGSET(I_FPS_0, isx012_fps_auto),
+		ISX012_REGSET(I_FPS_15, isx012_fps_15fix),
+		ISX012_REGSET(I_FPS_25, isx012_fps_25fix),
+		ISX012_REGSET(I_FPS_30, isx012_fps_30fix),
+	},
+
+	.preview_size = {
+		ISX012_REGSET(PREVIEW_SZ_320x240, isx012_320_Preview),
+		ISX012_REGSET(PREVIEW_SZ_VGA, isx012_640_Preview),
+		ISX012_REGSET(PREVIEW_SZ_D1, isx012_720_Preview),
+		ISX012_REGSET(PREVIEW_SZ_XGA, isx012_1024_768_Preview),
+		ISX012_REGSET(PREVIEW_SZ_PVGA, isx012_1280_Preview_E),
+	},
+	.capture_size = {
+		ISX012_REGSET(CAPTURE_SZ_VGA, isx012_VGA_Capture),
+		ISX012_REGSET(CAPTURE_SZ_3MP, isx012_3M_Capture),
+		ISX012_REGSET(CAPTURE_SZ_5MP, isx012_5M_Capture),
+	},
+#if 0 /* DSLIM: Should be implemented */
+	.preview_return = ISX012_REGSET_TABLE(s5k5ccgx_preview_return),
+
+	.ae_lock_on =
+		ISX012_REGSET_TABLE(s5k5ccgx_ae_lock),
+	.ae_lock_off =
+		ISX012_REGSET_TABLE(s5k5ccgx_ae_unlock),
+	.awb_lock_on =
+		ISX012_REGSET_TABLE(s5k5ccgx_awb_lock),
+	.awb_lock_off =
+		ISX012_REGSET_TABLE(s5k5ccgx_awb_unlock),
+#endif
+
+	/* AF */
+	.af_window_reset = ISX012_REGSET_TABLE(ISX012_AF_Window_Reset),
+	.af_winddow_set = ISX012_REGSET_TABLE(ISX012_AF_Window_Set),
+	.af_restart = ISX012_REGSET_TABLE(ISX012_AF_ReStart),
+	.af_saf_off = ISX012_REGSET_TABLE(ISX012_AF_SAF_OFF),
+	.af_touch_saf_off = ISX012_REGSET_TABLE(ISX012_AF_TouchSAF_OFF),
+	.cancel_af_macro = ISX012_REGSET_TABLE(ISX012_AF_Cancel_Macro_ON),
+	.cancel_af_normal = ISX012_REGSET_TABLE(ISX012_AF_Cancel_Macro_OFF),
+	.af_macro_mode = ISX012_REGSET_TABLE(ISX012_AF_Macro_ON),
+	.af_normal_mode = ISX012_REGSET_TABLE(ISX012_AF_Macro_OFF),
+	.af_camcorder_start = ISX012_REGSET_TABLE(ISX012_Camcorder_SAF_Start),
+
+	/* Flash */
+	.flash_ae_line = ISX012_REGSET_TABLE(ISX012_Flash_AELINE),
+	.flash_on = ISX012_REGSET_TABLE(ISX012_Flash_ON),
+	.flash_off = ISX012_REGSET_TABLE(ISX012_Flash_OFF),
+
+	.init_reg = ISX012_REGSET_TABLE(ISX012_Init_Reg),
+#if 0 /* DSLIM: Should be implemented */
+	.get_esd_status = ISX012_REGSET_TABLE(s5k5ccgx_get_esd_reg),
+#endif
+	/* Camera mode */
+	.preview_mode = ISX012_REGSET_TABLE(ISX012_Preview_Mode),
+	.capture_mode = ISX012_REGSET_TABLE(ISX012_Capture_Mode),
+	.capture_mode_night =
+		ISX012_REGSET_TABLE(ISX012_Lowlux_Night_Capture_Mode),
+	.halfrelease_mode = ISX012_REGSET_TABLE(ISX012_Halfrelease_Mode),
+	.halfrelease_mode_night =
+		ISX012_REGSET_TABLE(ISX012_Lowlux_night_Halfrelease_Mode),
+	.camcorder_on = ISX012_REGSET_TABLE(ISX012_Camcorder_Mode_ON),
+	.camcorder_off = ISX012_REGSET_TABLE(ISX012_Camcorder_Mode_OFF),
+
+	.lowlux_night_reset = ISX012_REGSET_TABLE(ISX012_Lowlux_Night_Reset),
+
+	.set_pll_4 = ISX012_REGSET_TABLE(ISX012_Pll_Setting_4),
+	.softlanding = ISX012_REGSET_TABLE(ISX012_Sensor_Off_VCM),
+#if 0 /* def CONFIG_VIDEO_ISX012_P8*/
+	.antibanding = ISX012_REGSET_TABLE(ISX012_ANTIBANDING_REG),
+#endif
+};
+
+static const struct v4l2_mbus_framefmt capture_fmts[] = {
+	{
+		.code		= V4L2_MBUS_FMT_FIXED,
+		.colorspace	= V4L2_COLORSPACE_JPEG,
+	},
+};
+
+/**
+ * msleep_debug: wrapper function calling proper sleep()
+ * @msecs: time to be sleep (in milli-seconds unit)
+ * @dbg_on: whether enable log or not.
+ */
+static void msleep_debug(u32 msecs, bool dbg_on)
+{
+	u32 delta_halfrange; /* in us unit */
+
+	if (dbg_on)
+		cam_dbg("delay for %dms\n", msecs);
+
+	if (msecs <= 5)
+		delta_halfrange = 100;
+	else
+		delta_halfrange = 500;
+
+	if (msecs <= 20)
+		usleep_range((msecs * 1000 - delta_halfrange),
+			(msecs * 1000 + delta_halfrange));
+	else
+		msleep(msecs);
+}
+
+#ifdef CONFIG_LOAD_FILE
+#define TABLE_MAX_NUM 500
+static char *isx012_regs_table;
+static int isx012_regs_table_size;
+static int gtable_buf[TABLE_MAX_NUM];
+static int isx012_i2c_write(struct v4l2_subdev *sd,
+		u16 subaddr, u32 data, u32 len);
+
+int isx012_regs_table_init(void)
+{
+	struct file *filp;
+	char *dp;
+	long l;
+	loff_t pos;
+	int ret;
+	mm_segment_t fs = get_fs();
+
+	printk(KERN_DEBUG "%s %d\n", __func__, __LINE__);
+
+	set_fs(get_ds());
+
+	filp = filp_open("/mnt/sdcard/isx012_regs.h", O_RDONLY, 0);
+
+	if (IS_ERR_OR_NULL(filp)) {
+		printk(KERN_DEBUG "file open error\n");
+		return PTR_ERR(filp);
+	}
+
+	l = filp->f_path.dentry->d_inode->i_size;
+	printk(KERN_DEBUG "l = %ld\n", l);
+	//dp = kmalloc(l, GFP_KERNEL);
+	dp = vmalloc(l);
+	if (dp == NULL) {
+		printk(KERN_DEBUG "Out of Memory\n");
+		filp_close(filp, current->files);
+	}
+
+	pos = 0;
+	memset(dp, 0, l);
+	ret = vfs_read(filp, (char __user *)dp, l, &pos);
+
+	if (ret != l) {
+		printk(KERN_DEBUG "Failed to read file ret = %d\n", ret);
+		/*kfree(dp);*/
+		vfree(dp);
+		filp_close(filp, current->files);
+		return -EINVAL;
+	}
+
+	filp_close(filp, current->files);
+
+	set_fs(fs);
+
+	isx012_regs_table = dp;
+
+	isx012_regs_table_size = l;
+
+	*((isx012_regs_table + isx012_regs_table_size) - 1) = '\0';
+
+	printk("isx012_reg_table_init end\n");
+	return 0;
+}
+
+void isx012_regs_table_exit(void)
+{
+	printk(KERN_DEBUG "%s %d\n", __func__, __LINE__);
+
+	if (isx012_regs_table) {
+		vfree(isx012_regs_table);
+		isx012_regs_table = NULL;
+	}
+}
+
+static int isx012_define_table(void)
+{
+	char *start, *end, *reg;
+	char *start_token, *reg_token, *temp;
+	char reg_buf[61], temp2[61];
+	char token_buf[5];
+	int token_value = 0;
+	int index_1 = 0, index_2 = 0, total_index;
+	int len = 0, total_len = 0;
+
+	*(reg_buf + 60) = '\0';
+	*(temp2 + 60) = '\0';
+	*(token_buf + 4) = '\0';
+	memset(gtable_buf, 9999, TABLE_MAX_NUM);
+
+	printk(KERN_DEBUG "isx012_define_table start!\n");
+
+	start = strstr(isx012_regs_table, "aeoffset_table");
+	end = strstr(start, "};");
+
+	/* Find table */
+	index_2 = 0;
+	while (1) {
+		reg = strstr(start,"	");
+		if ((reg == NULL) || (reg > end)) {
+			printk(KERN_DEBUG "isx012_define_table read end!\n");
+			break;
+		}
+
+		/* length cal */
+		index_1 = 0;
+		total_len = 0;
+		temp = reg;
+		if (temp != NULL) {
+			memcpy(temp2, (temp + 1), 60);
+			//printk(KERN_DEBUG "temp2 : %s\n", temp2);
+		}
+		start_token = strstr(temp,",");
+		while (index_1 < 10) {
+			start_token = strstr(temp, ",");
+			len = strcspn(temp, ",");
+			//printk(KERN_DEBUG "len[%d]\n", len);	//Only debug
+			total_len = total_len + len;
+			temp = (temp + (len+2));
+			index_1 ++;
+		}
+		total_len = total_len + 19;
+		//printk(KERN_DEBUG "%d\n", total_len);	//Only debug
+
+		/* read table */
+		if (reg != NULL) {
+			memcpy(reg_buf, (reg + 1), total_len);
+			//printk(KERN_DEBUG "reg_buf : %s\n", reg_buf);	//Only debug
+			start = (reg + total_len+1);
+		}
+
+		reg_token = reg_buf;
+
+		index_1 = 0;
+		start_token=strstr(reg_token,",");
+		while (index_1 < 10) {
+			start_token = strstr(reg_token, ",");
+			len = strcspn(reg_token, ",");
+			//printk(KERN_DEBUG "len[%d]\n", len);	//Only debug
+			memcpy(token_buf, reg_token, len);
+			//printk(KERN_DEBUG "[%d]%s ", index_1, token_buf);	//Only debug
+			token_value = (unsigned short)simple_strtoul(token_buf, NULL, 10);
+			total_index = index_2 * 10 + index_1;
+			//printk(KERN_DEBUG "[%d]%d ", total_index, token_value);	//Only debug
+			gtable_buf[total_index] = token_value;
+			index_1 ++;
+			reg_token = (reg_token + (len + 2));
+		}
+		index_2 ++;
+	}
+
+#if 0	//Only debug
+	index_2 = 0;
+	while ( index_2 < TABLE_MAX_NUM) {
+		printk(KERN_DEBUG "[%d]%d ",index_2, gtable_buf[index_2]);
+		index_2++;
+	}
+#endif
+	printk(KERN_DEBUG "isx012_define_table end!\n");
+
+	return 0;
+}
+
+static int isx012_define_read(char *name, int len_size)
+{
+	char *start, *end, *reg;
+	char reg_7[7], reg_5[5];
+	int define_value = 0;
+
+	*(reg_7 + 6) = '\0';
+	*(reg_5 + 4) = '\0';
+
+	//printk(KERN_DEBUG "isx012_define_read start!\n");
+
+	start = strstr(isx012_regs_table, name);
+	end = strstr(start, "tuning");
+
+	reg = strstr(start," ");
+
+	if ((reg == NULL) || (reg > end)) {
+		printk(KERN_DEBUG "isx012_define_read error %s : ",name);
+		return -1;
+	}
+
+	/* Write Value to Address */
+	if (reg != NULL) {
+		if (len_size == 6) {
+			memcpy(reg_7, (reg + 1), len_size);
+			define_value = (unsigned short)simple_strtoul(reg_7, NULL, 16);
+		} else {
+			memcpy(reg_5, (reg + 1), len_size);
+			define_value = (unsigned short)simple_strtoul(reg_5, NULL, 10);
+		}
+	}
+	//printk(KERN_DEBUG "isx012_define_read end (0x%x)!\n", define_value);
+
+	return define_value;
+}
+
+static int isx012_write_regs_from_sd(struct v4l2_subdev *sd, const char *name)
+{
+	char *start, *end, *reg, *size;
+	unsigned short addr;
+	unsigned int len, value;
+	char reg_buf[7], data_buf1[5], data_buf2[7], len_buf[5];
+
+	*(reg_buf + 6) = '\0';
+	*(data_buf1 + 4) = '\0';
+	*(data_buf2 + 6) = '\0';
+	*(len_buf + 4) = '\0';
+
+	printk(KERN_DEBUG "isx012_regs_table_write start!\n");
+	printk(KERN_DEBUG "E string = %s\n", name);
+
+	start = strstr(isx012_regs_table, name);
+	if (!start) {
+		cam_err("%s: can not find %s", __func__, name);
+		return -ENOENT;
+	}
+	end = strstr(start, "};");
+
+	while (1) {
+		/* Find Address */
+		reg = strstr(start,"{0x");
+		if ((reg == NULL) || (reg > end))
+			break;
+
+		/* Write Value to Address */
+		if (reg != NULL) {
+			memcpy(reg_buf, (reg + 1), 6);
+			memcpy(data_buf2, (reg + 8), 6);
+			size = strstr(data_buf2,",");
+			if (size) { /* 1 byte write */
+				memcpy(data_buf1, (reg + 8), 4);
+				memcpy(len_buf, (reg + 13), 4);
+				addr = (unsigned short)simple_strtoul(reg_buf, NULL, 16);
+				value = (unsigned int)simple_strtoul(data_buf1, NULL, 16);
+				len = (unsigned int)simple_strtoul(len_buf, NULL, 16);
+				if (reg)
+					start = (reg + 20);  //{0x000b,0x04,0x01},
+			} else {/* 2 byte write */
+				memcpy(len_buf, (reg + 15), 4);
+				addr = (u16)simple_strtoul(reg_buf, NULL, 16);
+				value = (u32)simple_strtoul(data_buf2, NULL, 16);
+				len = (u32)simple_strtoul(len_buf, NULL, 16);
+				if (reg)
+					start = (reg + 22);  //{0x000b,0x0004,0x01},
+			}
+			size = NULL;
+
+			if (addr == 0xFFFF)
+				msleep_debug(value, true);
+			else
+				isx012_i2c_write(sd, addr, value, len);
+		}
+	}
+
+	printk(KERN_DEBUG "isx012_regs_table_write end!\n");
+
+	return 0;
+}
+#endif
+
+/**
+ * isx012_i2c_write_twobyte: Write (I2C) multiple bytes to the camera sensor
+ * @client: pointer to i2c_client
+ * @cmd: command register
+ * @w_data: data to be written
+ * @w_len: length of data to be written
+ *
+ * Returns 0 on success, <0 on error
+ */
+static int isx012_i2c_write_twobyte(struct i2c_client *client,
+					 u16 addr, u16 w_data)
+{
+	int retry_count = 5;
+	int ret = 0;
+	u8 buf[4] = {0,};
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.len	= 4,
+		.buf	= buf,
+	};
+
+	buf[0] = addr >> 8;
+	buf[1] = addr;
+	buf[2] = w_data >> 8;
+	buf[3] = w_data & 0xff;
+
+#if (0)
+	isx012_debug(ISX012_DEBUG_I2C, "%s : W(0x%02X%02X%02X%02X)\n",
+		__func__, buf[0], buf[1], buf[2], buf[3]);
+#else
+	/* cam_dbg("I2C writing: 0x%02X%02X%02X%02X\n",
+			buf[0], buf[1], buf[2], buf[3]); */
+#endif
+
+	do {
+		ret = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(ret == 1))
+			break;
+		msleep(POLL_TIME_MS);
+		cam_err("%s: error(%d), write (%04X, %04X), retry %d.\n",
+				__func__, ret, addr, w_data, retry_count);
+	} while (retry_count-- > 0);
+
+	CHECK_ERR_COND_MSG(ret != 1, -EIO, "I2C does not working.\n\n");
+
+	return 0;
+}
+
+#if 0
+static int isx012_i2c_write_block(struct v4l2_subdev *sd, u8 *buf, u32 size)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int retry_count = 5;
+	int ret = 0;
+	struct i2c_msg msg = {client->addr, 0, size, buf};
+
+#ifdef CONFIG_VIDEO_ISX012_DEBUG
+	if (isx012_debug_mask & ISX012_DEBUG_I2C_BURSTS) {
+		if ((buf[0] == 0x0F) && (buf[1] == 0x12))
+			pr_info("%s : data[0,1] = 0x%02X%02X,"
+				" total data size = %d\n",
+				__func__, buf[2], buf[3], size-2);
+		else
+			pr_info("%s : 0x%02X%02X%02X%02X\n",
+				__func__, buf[0], buf[1], buf[2], buf[3]);
+	}
+#endif
+
+	do {
+		ret = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(ret == 1))
+			break;
+		msleep(POLL_TIME_MS);
+	} while (retry_count-- > 0);
+	if (ret != 1) {
+		dev_err(&client->dev, "%s: I2C is not working.\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif
+
+#define BURST_MODE_BUFFER_MAX_SIZE 2700
+u8 isx012_burstmode_buf[BURST_MODE_BUFFER_MAX_SIZE];
+
+/* PX: */
+static int isx012_burst_write_regs(struct v4l2_subdev *sd,
+			const u32 list[], u32 size, char *name)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+	int i = 0, idx = 0;
+	u16 subaddr = 0, next_subaddr = 0, value = 0;
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.len	= 0,
+		.buf	= isx012_burstmode_buf,
+	};
+
+	cam_trace("E\n");
+
+	for (i = 0; i < size; i++) {
+		CHECK_ERR_COND_MSG((idx > (BURST_MODE_BUFFER_MAX_SIZE - 10)),
+			err, "BURST MOD buffer overflow!\n")
+
+		subaddr = (list[i] & 0xFFFF0000) >> 16;
+		if (subaddr == 0x0F12)
+			next_subaddr = (list[i+1] & 0xFFFF0000) >> 16;
+
+		value = list[i] & 0x0000FFFF;
+
+		switch (subaddr) {
+		case 0x0F12:
+			/* make and fill buffer for burst mode write. */
+			if (idx == 0) {
+				isx012_burstmode_buf[idx++] = 0x0F;
+				isx012_burstmode_buf[idx++] = 0x12;
+			}
+			isx012_burstmode_buf[idx++] = value >> 8;
+			isx012_burstmode_buf[idx++] = value & 0xFF;
+
+			/* write in burstmode*/
+			if (next_subaddr != 0x0F12) {
+				msg.len = idx;
+				err = i2c_transfer(client->adapter,
+					&msg, 1) == 1 ? 0 : -EIO;
+				CHECK_ERR_MSG(err, "i2c_transfer\n");
+				/* cam_dbg("isx012_sensor_burst_write,
+						idx = %d\n", idx); */
+				idx = 0;
+			}
+			break;
+
+		case 0xFFFF:
+			msleep_debug(value, true);
+			break;
+
+		default:
+			idx = 0;
+			err = isx012_i2c_write_twobyte(client,
+						subaddr, value);
+			CHECK_ERR_MSG(err, "i2c_write_twobytes\n");
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * isx012_read: read data from sensor with I2C
+ * Note the data-store way(Big or Little)
+ */
+static int isx012_i2c_read(struct v4l2_subdev *sd,
+			u16 subaddr, u32 *data, u32 len)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u8 buf[16] = {0,};
+	struct i2c_msg msg[2];
+	int err, retry = 3;
+
+
+	if (unlikely(!client->adapter)) {
+		cam_err("i2c read: adapter is null\n");
+		return -EINVAL;
+	}
+
+	if ((len != 0x01) && (len != 0x02) && (len != 0x04)) {
+		cam_err("%s: error, invalid len=%d\n", __func__, len);
+		return -EINVAL;
+	}
+
+	cpu_to_be16s(&subaddr);
+
+	msg[0].addr = client->addr;
+	msg[0].flags = 0;
+	msg[0].len = sizeof(subaddr);
+	msg[0].buf = (u8 *)&subaddr;
+
+	msg[1].addr = client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = len;
+	msg[1].buf = buf;
+
+	do {
+		err = i2c_transfer(client->adapter, msg, 2);
+		if (likely(err == 2))
+			break;
+		cam_err("i2c read: error, read register(0x%X), len=%d. cnt=%d\n",
+			subaddr, len, retry);
+		msleep_debug(POLL_TIME_MS, false);
+	} while (retry-- > 0);
+
+	CHECK_ERR_COND_MSG(err != 2, -EIO, "I2C does not working\n");
+
+#ifdef CONFIG_CAM_I2C_LITTLE_ENDIAN
+	if (len == 1)
+		*data = buf[0];
+	else if (len == 2) {
+		*data = *(u16 *)buf;
+		/* *data = le16_to_cpup((u16 *)buf); */
+	} else {
+		*data = *(u32 *)buf;
+		/* *data = le32_to_cpup((u32 *)buf); */
+	}
+#else /* I2C BIG-ENDIAN */
+	if (len == 1)
+		*data = buf[0];
+	else if (len == 2) {
+		*data = (buf[0] << 8) | buf[1];
+		/* *data = be16_to_cpup((u16 *)(buf)); */
+	} else {
+		*data = (buf[0] << 24) | (buf[1] << 16) |
+			(buf[2] << 8) | buf[3];
+		/* *data = be32_to_cpup((u32 *)(buf)); */
+	}
+#endif
+
+	return 0;
+}
+
+/**
+ * isx012_write: write data with I2C
+ * Note the data-store way(Big or Little)
+ */
+static int isx012_i2c_write(struct v4l2_subdev *sd,
+		u16 subaddr, u32 data, u32 len)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	u8 buf[len + 2];
+	int retry_count = 5;
+	int err;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("i2c write: adapter is null\n");
+		return -EINVAL;
+	}
+
+	if ((len != 0x01) && (len != 0x02) && (len != 0x04)) {
+		cam_err("%s: error, invalid len=%d\n", __func__, len);
+		return -EINVAL;
+	}
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(buf);
+	msg.buf = buf;
+
+	buf[0] = subaddr >> 8;
+	buf[1] = subaddr & 0xFF;
+
+#ifdef CONFIG_CAM_I2C_LITTLE_ENDIAN
+	if (len == 1)
+		buf[2] = data & 0xFF;
+	else if (len == 2) {
+		*(u16 *)(&buf[2]) = (u16)data;
+		/* *(u16 *)(&buf[2]) = cpu_to_le16p((u16 *)&data); */
+	} else {
+		*(u32 *)(&buf[2]) = data;
+		/* *(u32 *)(&buf[2]) = cpu_to_le32p((u32 *)&data); */
+	}
+#else /* I2C BIG-ENDIAN */
+	if (len == 1)
+		buf[2] = data & 0xFF;
+	else if (len == 2) {
+		buf[2] = (data >> 8) & 0xFF;
+		buf[3] = data & 0xFF;
+		/* *(u16 *)(&buf[2]) = cpu_to_be16p((u16 *)&data); */
+	} else {
+		buf[2] = (data >> 24) & 0xFF;
+		buf[3] = (data >> 16) & 0xFF;
+		buf[4] = (data >> 8) & 0xFF;
+		buf[5] = data & 0xFF;
+		/* *(u32 *)(&buf[2]) = cpu_to_be32p(&data);*/
+	}
+#endif
+
+	do {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(err == 1))
+			break;
+		cam_err("i2c write: error(%d), write(0x%04X, px%08X),"
+			" len=%d, retry %d\n", err, subaddr, data, len,
+			retry_count);
+		msleep_debug(POLL_TIME_MS, false);
+	} while (retry_count-- > 0);
+
+	CHECK_ERR_COND_MSG(err != 1, -EIO, "I2C does not working\n");
+	return 0;
+}
+
+#define SONY_ISX012_BURST_DATA_LENGTH	1200
+static unsigned char burst_buf[SONY_ISX012_BURST_DATA_LENGTH];
+static int isx012_i2c_burst_write_list(struct v4l2_subdev *sd,
+		const isx012_regset_t regs[], int size, const char *name)
+{
+	struct i2c_client *isx012_client = v4l2_get_subdevdata(sd);
+	int i = 0;
+	int iTxDataIndex = 0;
+	int retry_count = 5;
+	int err = 0;
+	u8 *buf = burst_buf;
+
+	struct i2c_msg msg = {isx012_client->addr, 0, 4, buf};
+
+	if (!isx012_client->adapter) {
+		printk(KERN_ERR "%s: %d can't search i2c client adapter\n", __func__, __LINE__);
+		return -EIO;
+	}
+
+	while ( i < size )//0<1
+	{
+		if ( 0 == iTxDataIndex )
+		{
+	        //printk("11111111111 delay 0x%04x, value 0x%04x\n", regs[i].subaddr, regs[i].value);
+			buf[iTxDataIndex++] = ( regs[i].subaddr & 0xFF00 ) >> 8;
+			buf[iTxDataIndex++] = ( regs[i].subaddr & 0xFF );
+		}
+
+		if ( ( i < size - 1 ) && ( ( iTxDataIndex + regs[i].len ) <= ( SONY_ISX012_BURST_DATA_LENGTH - regs[i+1].len ) ) && ( regs[i].subaddr + regs[i].len == regs[i+1].subaddr ) )
+		{
+			if ( 1 == regs[i].len )
+			{
+				//printk("2222222 delay 0x%04x, value 0x%04x\n", regs[i].subaddr, regs[i].value);
+				buf[iTxDataIndex++] = ( regs[i].value & 0xFF );
+			}
+			else
+			{
+				// Little Endian
+				buf[iTxDataIndex++] = ( regs[i].value & 0x00FF );
+				buf[iTxDataIndex++] = ( regs[i].value & 0xFF00 ) >> 8;
+				//printk("3333333 delay 0x%04x, value 0x%04x\n", regs[i].subaddr, regs[i].value);
+			}
+		}
+		else
+		{
+				if ( 1 == regs[i].len )
+				{
+					//printk("4444444 delay 0x%04x, value 0x%04x\n", regs[i].subaddr, regs[i].value);
+					buf[iTxDataIndex++] = ( regs[i].value & 0xFF );
+					//printk("burst_index:%d\n", iTxDataIndex);
+					msg.len = iTxDataIndex;
+
+				}
+				else
+				{
+					//printk("555555 delay 0x%04x, value 0x%04x\n", regs[i].subaddr, regs[i].value);
+					// Little Endian
+					buf[iTxDataIndex++] = (regs[i].value & 0x00FF );
+					buf[iTxDataIndex++] = (regs[i].value & 0xFF00 ) >> 8;
+					//printk("burst_index:%d\n", iTxDataIndex);
+					msg.len = iTxDataIndex;
+
+				}
+
+				while(retry_count--) {
+				err  = i2c_transfer(isx012_client->adapter, &msg, 1);
+					if (likely(err == 1))
+						break;
+
+			}
+			iTxDataIndex = 0;
+		}
+		i++;
+	}
+
+	return 0;
+}
+
+static inline int isx012_write_regs(struct v4l2_subdev *sd,
+			const isx012_regset_t regs[], int size)
+{
+	int err = 0, i;
+
+	for (i = 0; i < size; i++) {
+		if (unlikely(regs[i].subaddr == 0xFFFF))
+			msleep_debug(regs[i].value, true);
+		else {
+			err = isx012_i2c_write(sd, regs[i].subaddr,
+				regs[i].value, regs[i].len);
+			CHECK_ERR_MSG(err, "register set failed\n")
+                }
+	}
+
+	return 0;
+}
+
+/* PX: */
+static int isx012_set_from_table(struct v4l2_subdev *sd,
+				const char *setting_name,
+				const struct regset_table *table,
+				u32 table_size, s32 index)
+{
+	int err = 0;
+
+	/* cam_dbg("%s: set %s index %d\n",
+		__func__, setting_name, index); */
+	CHECK_ERR_COND_MSG(((index < 0) || (index >= table_size)),
+		-EINVAL, "index(%d) out of range[0:%d] for table for %s\n",
+		index, table_size, setting_name);
+
+	table += index;
+
+#ifdef CONFIG_LOAD_FILE
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__,
+			setting_name, table->name);
+	return isx012_write_regs_from_sd(sd, table->name);
+
+#else /* !CONFIG_LOAD_FILE */
+	CHECK_ERR_COND_MSG(!table->reg, -EFAULT, \
+		"table=%s, index=%d, reg = NULL\n", setting_name, index);
+# ifdef DEBUG_WRITE_REGS
+	cam_dbg("write_regtable: \"%s\", reg_name=%s\n", setting_name,
+		table->name);
+# endif /* DEBUG_WRITE_REGS */
+
+	err = isx012_write_regs(sd, table->reg, table->array_size);
+	CHECK_ERR_MSG(err, "write regs(%s), err=%d\n", setting_name, err);
+
+	return 0;
+#endif /* CONFIG_LOAD_FILE */
+}
+
+static inline int isx012_hw_stby_on(struct v4l2_subdev *sd, bool on)
+{
+	struct isx012_state *state = to_state(sd);
+
+	return state->pdata->stby_on(on);
+}
+
+static inline int isx012_sw_stby_on(struct v4l2_subdev *sd, bool on)
+{
+	cam_trace(" %d\n", on);
+	return isx012_writeb(sd, 0x0005, on ? 0x01 : 0x00);
+}
+
+static int isx012_is_om_changed(struct v4l2_subdev *sd)
+{
+	u32 status = 0x3, val = 0;
+	int err, cnt1, cnt2;
+
+	for (cnt1 = 0; cnt1 < ISX012_CNT_OM_CHECK; cnt1++) {
+		err = isx012_readb(sd, REG_INTSTS, &val);
+		if (unlikely(err))
+			cam_err("om changed: error, readb cnt=%d\n", cnt1);
+
+		if ((val & REG_INTBIT_OM) == REG_INTBIT_OM) {
+			status &= ~0x01;
+			break;
+		}
+		msleep_debug(5, false);
+	}
+
+	for (cnt2 = 0; cnt2 < ISX012_CNT_OM_CHECK; cnt2++) {
+		err = isx012_writeb(sd, REG_INTCLR, REG_INTBIT_OM);
+		err |= isx012_readb(sd, REG_INTSTS, &val);
+		if (unlikely(err))
+			cam_err("om changed: error, rw cnt=%d\n", cnt2);
+
+		if ((val & REG_INTBIT_OM) == 0) {
+			status &= ~0x02;
+			break;
+		}
+		msleep_debug(5, false);
+	}
+
+	cam_dbg("om changed: sucess. int cnt=%d, clr cnt=%d\n", cnt1, cnt2);
+
+	if (unlikely(status)) {
+		cam_err("om changed: error, fail 0x%X\n", status);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/**
+ * isx012_is_cm_changed:
+ *
+ * status: 0x01 = int check fail
+ *       0x02 = int clear fail
+ *       0x03 = int check, clear fail
+ */
+static int isx012_is_cm_changed(struct v4l2_subdev *sd)
+{
+	u32 status = 0x3, val = 0;
+	int err = 0, cnt1, cnt2;
+
+	for (cnt1 = 0; cnt1 < ISX012_CNT_CM_CHECK; cnt1++) {
+		err = isx012_readb(sd, REG_INTSTS, &val);
+		CHECK_ERR_MSG(err, "cm changed: error, readb\n")
+		if ((val & REG_INTBIT_CM) == REG_INTBIT_CM) {
+			status &= ~0x01;
+			break;
+		}
+		msleep_debug(5, false);
+	}
+
+	for (cnt2 = 0; cnt2 < ISX012_CNT_CM_CHECK; cnt2++) {
+		err = isx012_writeb(sd, REG_INTCLR, REG_INTBIT_CM);
+		CHECK_ERR_MSG(err, "cm changed: error, writeb\n");
+		isx012_readb(sd, REG_INTSTS, &val);
+		if ((val & REG_INTBIT_CM) == 0) {
+			status &= ~0x02;
+			break;
+		}
+
+		msleep_debug(5, false);
+	}
+
+	cam_dbg("cm changed: int cnt=%d, clr cnt=%d\n", cnt1, cnt2);
+
+	if (unlikely(status)) {
+		cam_err("cm changed: error, fail 0x%X\n", status);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+static inline int isx012_transit_preview_mode(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EIO;
+
+	err = isx012_set_from_table(sd, "preview_mode",
+		&state->regs->preview_mode, 1, 0);
+	return err;
+}
+
+/**
+ * isx012_transit_half_mode: go to a half-release mode
+ * Don't forget that half mode is not used in movie mode.
+ */
+static inline int isx012_transit_half_mode(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EIO;
+
+	/* We do not go to half release mode in movie mode */
+	if (state->sensor_mode == SENSOR_MOVIE)
+		return 0;
+
+	if (state->scene_mode == SCENE_MODE_NIGHTSHOT &&
+	    state->light_level >= LUX_LEVEL_LOW) {
+		cam_info("half_mode: night lowlux\n");
+		state->lowlux_night = 1;
+		err = isx012_set_from_table(sd, "night_halfrelease_mode",
+			&state->regs->halfrelease_mode_night, 1, 0);
+	} else {
+		state->lowlux_night = 0;
+		err = isx012_set_from_table(sd, "halfrelease",
+			&state->regs->halfrelease_mode, 1, 0);
+	}
+
+	msleep_debug(40, true);
+	return err;
+}
+
+static inline int isx012_transit_capture_mode(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EIO;
+
+	if (state->lowlux_night) {
+		cam_info("capture_mode: night lowlux\n");
+#if !defined(CONFIG_NEW_STREAM_DELAY)
+		state->lowlux_night = 0;
+#endif
+		err = isx012_set_from_table(sd, "capture_mode_night",
+			&state->regs->capture_mode_night, 1, 0);
+	} else
+		err = isx012_set_from_table(sd, "capture_mode",
+			&state->regs->capture_mode, 1, 0);
+
+	return err;
+}
+
+/**
+ * isx012_transit_movie_mode: switch camera mode if needed.
+ * Note that this fuction should be called from start_preview().
+ */
+static inline int isx012_transit_movie_mode(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	/* we'll go from the below modes to RUNNING or RECORDING */
+	switch (state->runmode) {
+	case RUNMODE_INIT:
+		/* case of entering camcorder firstly */
+	case RUNMODE_RUNNING_STOP:
+		/* case of switching from camera to camcorder */
+		if (state->sensor_mode == SENSOR_MOVIE) {
+			cam_dbg("switching to camcorder mode\n");
+			isx012_set_from_table(sd, "camcorder_on",
+				&state->regs->camcorder_on, 1, 0);
+		}
+		break;
+
+	case RUNMODE_RECORDING_STOP:
+		/* case of switching from camcorder to camera */
+		if (state->sensor_mode == SENSOR_CAMERA) {
+			cam_dbg("switching to camera mode\n");
+			isx012_set_from_table(sd, "camcorder_off",
+				&state->regs->camcorder_off, 1, 0);
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_NO_FRAME
+#if 0 /* new written codes */
+static void isx012_frame_checker(struct work_struct *work)
+{
+	struct isx012_state *state = container_of(work, \
+			struct isx012_state, frame_work);
+	struct v4l2_subdev *sd = &state->sd;
+	u32 val = 0, mask;
+	int err, cnt, int_cnt = 0;
+	u32 target_cnt = 2;
+
+	/* cam_dbg("========= frame checker =========\n");*/
+
+#ifdef CONFIG_DEBUG_CAPTURE_FRAME
+	if (state->format_mode == V4L2_PIX_FMT_MODE_CAPTURE) {
+		mask = REG_INTBIT_CAPNUM_END;
+		target_cnt = 1;
+	} else
+#endif
+	{
+		mask = REG_INTBIT_VINT;
+		target_cnt = 2;
+	}
+
+	for (cnt = 0; cnt < ISX012_CNT_CAPTURE_FRM; cnt++) {
+		err = isx012_readb(sd, REG_INTSTS, &val);
+		if (unlikely(err)) {
+			cam_err("frame_checker: error, readb\n");
+			return;
+		}
+
+		if (((u8)val & mask) == mask) {
+			cam_info("frame INT %d (target %d)\n",
+				int_cnt, target_cnt);
+			if (++int_cnt >= target_cnt) {
+				state->frame_check = false;
+				return;
+			}
+
+			isx012_writeb(sd, REG_INTCLR, mask);
+			isx012_readb(sd, REG_INTSTS, &val);
+			if (((u8)val & mask) != 0) {
+				cam_info("frame_checker: cannot clear int");
+				return;
+			}
+		}
+
+		if (!state->frame_check) {
+			cam_dbg("frame_checker aborted.\n");
+			return;
+		}
+
+		msleep_debug(10, false);
+	}
+
+	cam_err("frame INT Not occured!\n");
+}
+
+static int isx012_start_frame_checker(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int cnt, err = 0;
+	u32 val = 0;
+	u32 mask = REG_INTBIT_VINT | REG_INTBIT_CAPNUM_END;
+
+	/* cam_trace("EX\n"); */
+#ifdef CONFIG_DEBUG_CAPTURE_FRAME
+	if (state->format_mode == V4L2_PIX_FMT_MODE_CAPTURE)
+		isx012_writeb(sd, REG_CAPNUM, 1);
+#endif
+
+	for (cnt = 0; cnt < ISX012_CNT_CLEAR_VINT; cnt++) {
+		isx012_writeb(sd, REG_INTCLR, mask);
+		isx012_readb(sd, REG_INTSTS, &val);
+		if (((u8)val & mask) == 0)
+			break;
+
+		cam_info("frame_checker: clear int register\n");
+		msleep_debug(5, false);
+	}
+
+	if (unlikely(cnt >= ISX012_CNT_CLEAR_VINT)) {
+		cam_info("fail to clear vint. frame_detecter not started\n");
+		return -1;
+	}
+
+	state->frame_check = true;
+	err = queue_work(state->workqueue, &state->frame_work);
+	if (unlikely(!err))
+		cam_info("frame_detecter is already operating!\n");
+
+	return 0;
+}
+#else
+static void isx012_frame_checker(struct work_struct *work)
+{
+	struct isx012_state *state = container_of(work, \
+			struct isx012_state, frame_work);
+	struct v4l2_subdev *sd = &state->sd;
+	u32 val = 0;
+	int cnt, err, int_cnt = 0;
+
+	/* cam_dbg("========= frame checker =========\n");*/
+
+	for (cnt = 0; cnt < ISX012_CNT_CAPTURE_FRM; cnt++) {
+		err = isx012_readb(sd, REG_INTSTS, &val);
+		if (unlikely(err)) {
+			cam_err("frame_checker: error, readb\n");
+			return;
+		}
+
+		if (((u8)val & ISX012_INTSRC_VINT) == ISX012_INTSRC_VINT) {
+			++int_cnt;
+			cam_info("frame INT %d (cnt=%d)\n", int_cnt, cnt);
+			if (int_cnt >= 2) {
+				state->frame_check = false;
+				return;
+			}
+
+			isx012_writeb(sd, REG_INTCLR, ISX012_INTSRC_VINT);
+			isx012_readb(sd, REG_INTSTS, &val);
+			if (((u8)val & ISX012_INTSRC_VINT) != 0) {
+				cam_info("frame_checker: cannot clear int");
+				return;
+			}
+		}
+
+		if (!state->frame_check) {
+			cam_dbg("frame_checker aborted.\n");
+			return;
+		}
+
+		msleep_debug(10, false);
+	}
+
+	cam_err("frame INT Not occured!\n");
+}
+
+static int isx012_start_frame_checker(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int cnt, err = 0;
+	u32 val = 0;
+
+	/* cam_trace("EX\n"); */
+
+	for (cnt = 0; cnt < ISX012_CNT_CLEAR_VINT; cnt++) {
+		isx012_writeb(sd, REG_INTCLR, ISX012_INTSRC_VINT);
+		isx012_readb(sd, REG_INTSTS, &val);
+		if (((u8)val & ISX012_INTSRC_VINT) == 0)
+			break;
+
+		msleep_debug(5, false);
+	}
+
+	if (unlikely(cnt >= ISX012_CNT_CLEAR_VINT)) {
+		cam_info("fail to clear vint. frame_detecter not started\n");
+		return -1;
+	}
+
+	state->frame_check = true;
+	err = queue_work(state->workqueue, &state->frame_work);
+	if (unlikely(!err))
+		cam_info("frame_detecter is already operating!\n");
+
+	return 0;
+}
+#endif
+
+static void isx012_stop_frame_checker(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	/* cam_trace("EX\n"); */
+	state->frame_check = false;
+	if (flush_work(&state->frame_work))
+		cam_dbg("wait... frame_checker stopped\n");
+}
+#endif /* CONFIG_DEBUG_NO_FRAME */
+
+/**
+ * isx012_is_hwflash_on - check whether flash device is on
+ *
+ * Refer to state->flash_on to check whether flash is in use in driver.
+ */
+static inline int isx012_is_hwflash_on(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+#ifdef ISX012_SUPPORT_FLASH
+	return state->pdata->is_flash_on();
+#else
+	return 0;
+#endif
+}
+
+/**
+ * isx012_flash_en - contro Flash LED
+ * @mode: ISX012_FLASH_MODE_NORMAL or ISX012_FLASH_MODE_MOVIE
+ * @onoff: ISX012_FLASH_ON or ISX012_FLASH_OFF
+ */
+static int isx012_flash_en(struct v4l2_subdev *sd, s32 mode, s32 onoff)
+{
+	struct isx012_state *state = to_state(sd);
+
+	if (unlikely(state->ignore_flash)) {
+		cam_warn("WARNING, we ignore flash command.\n");
+		return 0;
+	}
+
+#ifdef ISX012_SUPPORT_FLASH
+	return state->pdata->flash_en(mode, onoff);
+#else
+	return 0;
+#endif
+}
+
+/**
+ * isx012_flash_torch - turn flash on/off as torch for preflash, recording
+ * @onoff: ISX012_FLASH_ON or ISX012_FLASH_OFF
+ *
+ * This func set state->flash_on properly.
+ */
+static inline int isx012_flash_torch(struct v4l2_subdev *sd, s32 onoff)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	err = isx012_flash_en(sd, ISX012_FLASH_MODE_MOVIE, onoff);
+	state->flash_on = (onoff == ISX012_FLASH_ON) ? 1 : 0;
+
+	return err;
+}
+
+/**
+ * isx012_flash_oneshot - turn main flash on for capture
+ * @onoff: ISX012_FLASH_ON or ISX012_FLASH_OFF
+ *
+ * Main flash is turn off automatically in some milliseconds.
+ */
+static inline int isx012_flash_oneshot(struct v4l2_subdev *sd, s32 onoff)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	err = isx012_flash_en(sd, ISX012_FLASH_MODE_NORMAL, onoff);
+
+	/* The flash_on here is only used for EXIF */
+	state->flash_on = (onoff == ISX012_FLASH_ON) ? 1 : 0;
+
+	return err;
+}
+
+static const struct isx012_framesize *isx012_get_framesize
+	(const struct isx012_framesize *frmsizes,
+	u32 frmsize_count, u32 index)
+{
+	int i = 0;
+
+	for (i = 0; i < frmsize_count; i++) {
+		if (frmsizes[i].index == index)
+			return &frmsizes[i];
+	}
+
+	return NULL;
+}
+
+/* This function is called from the g_ctrl api
+ *
+ * This function should be called only after the s_fmt call,
+ * which sets the required width/height value.
+ *
+ * It checks a list of available frame sizes and sets the
+ * most appropriate frame size.
+ *
+ * The list is stored in an increasing order (as far as possible).
+ * Hence the first entry (searching from the beginning) where both the
+ * width and height is more than the required value is returned.
+ * In case of no perfect match, we set the last entry (which is supposed
+ * to be the largest resolution supported.)
+ */
+static void isx012_set_framesize(struct v4l2_subdev *sd,
+				const struct isx012_framesize *frmsizes,
+				u32 num_frmsize, bool preview)
+{
+	struct isx012_state *state = to_state(sd);
+	const struct isx012_framesize **found_frmsize = NULL;
+	u32 width = state->req_fmt.width;
+	u32 height = state->req_fmt.height;
+	int i = 0;
+
+	cam_dbg("%s: Requested Res %dx%d\n", __func__,
+			width, height);
+
+	found_frmsize = (preview ? &state->preview : &state->capture);
+
+	for (i = 0; i < num_frmsize; i++) {
+		if ((frmsizes[i].width == width) &&
+			(frmsizes[i].height == height)) {
+			*found_frmsize = &frmsizes[i];
+			break;
+		}
+	}
+
+	if (*found_frmsize == NULL) {
+		cam_err("%s: error, invalid frame size %dx%d\n",
+			__func__, width, height);
+		*found_frmsize = preview ?
+			isx012_get_framesize(frmsizes, num_frmsize,
+					PREVIEW_SZ_XGA) :
+			isx012_get_framesize(frmsizes, num_frmsize,
+					CAPTURE_SZ_3MP);
+		BUG_ON(!(*found_frmsize));
+	}
+
+	if (preview)
+		cam_info("Preview Res Set: %dx%d, index %d\n",
+			(*found_frmsize)->width, (*found_frmsize)->height,
+			(*found_frmsize)->index);
+	else
+		cam_info("Capture Res Set: %dx%d, index %d\n",
+			(*found_frmsize)->width, (*found_frmsize)->height,
+			(*found_frmsize)->index);
+}
+
+/* PX: Set scene mode */
+static int isx012_set_scene_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_trace("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case SCENE_MODE_NONE:
+	case SCENE_MODE_PORTRAIT:
+	case SCENE_MODE_NIGHTSHOT:
+	case SCENE_MODE_BACK_LIGHT:
+	case SCENE_MODE_LANDSCAPE:
+	case SCENE_MODE_SPORTS:
+	case SCENE_MODE_PARTY_INDOOR:
+	case SCENE_MODE_BEACH_SNOW:
+	case SCENE_MODE_SUNSET:
+	case SCENE_MODE_DUSK_DAWN:
+	case SCENE_MODE_FALL_COLOR:
+	case SCENE_MODE_FIREWORKS:
+	case SCENE_MODE_TEXT:
+	case SCENE_MODE_CANDLE_LIGHT:
+		isx012_set_from_table(sd, "scene_mode",
+			state->regs->scene_mode,
+			ARRAY_SIZE(state->regs->scene_mode), val);
+		break;
+
+	default:
+		cam_err("set_scene: error, not supported (%d)\n", val);
+		val = SCENE_MODE_NONE;
+		goto retry;
+	}
+
+	state->scene_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Set brightness */
+static int isx012_set_exposure(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+	static const u8 gain_level[GET_EV_INDEX(EV_MAX_V4L2)] = {
+		0x14, 0x1C, 0x21, 0x26, 0x2B, 0x2F, 0x33, 0x37, 0x3B};
+	int err = 0;
+
+	if ((val < EV_MINUS_4) || (val > EV_PLUS_4)) {
+		cam_err("%s: error, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	state->lux_level_flash = gain_level[GET_EV_INDEX(val)];
+
+	isx012_set_from_table(sd, "brightness", state->regs->ev,
+		ARRAY_SIZE(state->regs->ev), GET_EV_INDEX(val));
+
+	state->exposure.val = val;
+
+	return err;
+}
+
+static inline u32 isx012_get_light_level(struct v4l2_subdev *sd,
+					u32 *light_level)
+{
+	isx012_readb(sd, REG_USER_GAINLEVEL_NOW, light_level);
+
+	cam_trace("X, light level = 0x%X", *light_level);
+
+	return 0;
+}
+
+/* PX(NEW) */
+static int isx012_set_capture_size(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	if (unlikely(!state->capture)) {
+		cam_warn("warning, capture resolution not set\n");
+		state->capture = isx012_get_framesize(isx012_capture_frmsizes,
+					ARRAY_SIZE(isx012_capture_frmsizes),
+					CAPTURE_SZ_3MP);
+	}
+
+	cam_dbg("set capture size(%dx%d)\n",
+		state->capture->width, state->capture->height);
+
+	isx012_writew(sd, REG_HSIZE_CAP, state->capture->width);
+	isx012_writew(sd, REG_VSIZE_CAP, state->capture->height);
+
+	return 0;
+}
+
+/* PX: Set sensor mode */
+static int isx012_set_sensor_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_trace("mode=%d\n", val); /*DSLIM*/
+
+	switch (val) {
+	case SENSOR_MOVIE:
+		/* We does not support movie mode when in VT. */
+		if (state->vt_mode) {
+			state->sensor_mode = SENSOR_CAMERA;
+			cam_err("%s: error, Not support movie\n", __func__);
+			break;
+		}
+		/* We do not break. */
+
+	case SENSOR_CAMERA:
+		state->sensor_mode = val;
+		break;
+
+	default:
+		cam_err("%s: error, Not support.(%d)\n", __func__, val);
+		state->sensor_mode = SENSOR_CAMERA;
+		WARN_ON(1);
+		break;
+	}
+
+	return 0;
+}
+
+/* PX: Set framerate */
+static int isx012_set_frame_rate(struct v4l2_subdev *sd, s32 fps)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EIO;
+	int i = 0, fps_index = -1;
+
+	if (!state->initialized || (state->req_fps < 0))
+		return 0;
+
+	cam_info("set frame rate %d\n", fps);
+
+	for (i = 0; i < ARRAY_SIZE(isx012_framerates); i++) {
+		if (fps == isx012_framerates[i].fps) {
+			fps_index = isx012_framerates[i].index;
+			state->fps = fps;
+			state->req_fps = -1;
+			break;
+		}
+	}
+
+	if (unlikely(fps_index < 0)) {
+		cam_err("set_fps: warning, not supported fps %d\n", fps);
+		return 0;
+	}
+
+	err = isx012_set_from_table(sd, "fps", state->regs->fps,
+			ARRAY_SIZE(state->regs->fps), fps_index);
+	CHECK_ERR_MSG(err, "fail to set framerate\n");
+
+	return 0;
+}
+
+static int isx012_set_ae_lock(struct v4l2_subdev *sd, s32 lock, bool force)
+{
+	struct isx012_state *state = to_state(sd);
+	u32 val = 0;
+
+	switch (lock) {
+	case AE_LOCK:
+		isx012_readb(sd, REG_CPUEXT, &val);
+		val |= REG_CPUEXT_AE_HOLD;
+		isx012_writeb(sd, REG_CPUEXT, val);
+		state->exposure.ae_lock = 1;
+		cam_info("AE lock by user\n");
+		break;
+
+	case AE_UNLOCK:
+		if (unlikely(!force && !state->exposure.ae_lock))
+			return 0;
+
+		isx012_readb(sd, REG_CPUEXT, &val);
+		val &= ~REG_CPUEXT_AE_HOLD;
+		isx012_writeb(sd, REG_CPUEXT, val);
+		state->exposure.ae_lock = 0;
+		cam_info("AE unlock by user\n");
+		break;
+
+	default:
+		cam_err("ae_lock: warning, invalid argument(%d)\n", val);
+	}
+
+	return 0;
+}
+
+static int isx012_set_awb_lock(struct v4l2_subdev *sd, s32 lock, bool force)
+{
+	struct isx012_state *state = to_state(sd);
+	u32 val = 0;
+
+	switch (lock) {
+	case AWB_LOCK:
+		if (state->wb.mode != WHITE_BALANCE_AUTO)
+			return 0;
+
+		isx012_readb(sd, REG_CPUEXT, &val);
+		val |= REG_CPUEXT_AWB_HOLD;
+		isx012_writeb(sd, REG_CPUEXT, val);
+		state->wb.awb_lock = 1;
+		cam_info("AWB lock by user\n");
+		break;
+
+	case AWB_UNLOCK:
+		if (unlikely(!force && !state->wb.awb_lock))
+			return 0;
+
+		isx012_readb(sd, REG_CPUEXT, &val);
+		val &= ~REG_CPUEXT_AWB_HOLD;
+		isx012_writeb(sd, REG_CPUEXT, val);
+		state->wb.awb_lock = 0;
+		cam_info("AWB unlock by user\n");
+		break;
+
+	default:
+		cam_err("%s: warning, invalid argument(%d)\n", __func__, val);
+	}
+
+	return 0;
+}
+
+/* PX: Set AE, AWB Lock */
+static int isx012_set_lock(struct v4l2_subdev *sd, s32 lock, bool force)
+{
+#if 0
+	int err = -EIO;
+
+	cam_trace("%s\n", lock ? "on" : "off");
+	if (unlikely((u32)lock >= AEAWB_LOCK_MAX)) {
+		cam_err("%s: error, invalid argument\n", __func__);
+		return -EINVAL;
+	}
+
+	err = isx012_set_ae_lock(sd, (lock == AEAWB_LOCK) ?
+				AE_LOCK : AE_UNLOCK, force);
+	if (unlikely(err))
+		goto out_err;
+
+	err = isx012_set_awb_lock(sd, (lock == AEAWB_LOCK) ?
+				AWB_LOCK : AWB_UNLOCK, force);
+	if (unlikely(err))
+		goto out_err;
+
+	cam_trace("X\n");
+	return 0;
+
+out_err:
+	cam_err("%s: error, failed to set lock\n", __func__);
+	return err;
+#else
+	return 0;
+#endif
+}
+
+static int isx012_set_af_softlanding(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	err = isx012_set_from_table(sd, "softlanding",
+			&state->regs->softlanding, 1, 0);
+	CHECK_ERR_MSG(err, "fail to set softlanding\n");
+
+	return 0;
+}
+
+/* PX: */
+static int isx012_return_focus(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("EX\n");
+
+	if (state->focus.mode == FOCUS_MODE_MACRO)
+		err = isx012_set_from_table(sd, "af_macro_mode",
+				&state->regs->af_macro_mode, 1, 0);
+	else
+		err = isx012_set_from_table(sd, "af_normal_mode",
+				&state->regs->af_normal_mode, 1, 0);
+
+	CHECK_ERR(err);
+	return 0;
+}
+
+static int isx012_pre_sensor_flash(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_trace("EX\n");
+
+	/* change flash AE line */
+	isx012_set_from_table(sd, "flash_ae_line",
+		&state->regs->flash_ae_line, 1, 0);
+
+	/* Wait 1V time(60ms) */
+	msleep_debug(60, true);
+
+	/* read preview AE scale */
+	isx012_readw(sd, REG_USER_AESCL_AUTO,
+		&state->exposure.ae_offset.ae_auto);
+	isx012_readw(sd, REG_ERRSCL_AUTO, &state->exposure.ae_offset.ersc_auto);
+
+	if (state->wb.mode == WHITE_BALANCE_AUTO)
+		isx012_writeb(sd, REG_AWB_SN1, 0x00);
+
+	/* write flash_on_set */
+	isx012_set_from_table(sd, "flash_on",
+		&state->regs->flash_on, 1, 0);
+
+	isx012_writeb(sd, REG_VPARA_TRG, 0x01);
+
+	/* Wait 1V time(40ms) */
+	msleep_debug(40, true);
+
+	return 0;
+}
+
+static int isx012_post_sensor_flash(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_trace("EX\n");
+
+	isx012_set_from_table(sd, "flash_off",
+		&state->regs->flash_off, 1, 0);
+
+	if (state->wb.mode == WHITE_BALANCE_AUTO)
+		isx012_writeb(sd, REG_AWB_SN1, 0x20);
+
+	isx012_writeb(sd, REG_VPARA_TRG, 0x01);
+
+	return 0;
+}
+
+static int isx012_set_ae_gainoffset(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	s16 ae_diff, ae_offset;
+	u16 ae_auto, ae_now;
+	s16 ersc_auto, ersc_now;
+
+	ae_auto = (u16)state->exposure.ae_offset.ae_auto;
+	ae_now = (u16)state->exposure.ae_offset.ae_now;
+	ersc_auto = (u16)state->exposure.ae_offset.ersc_auto;
+	ersc_now = (u16)state->exposure.ae_offset.ersc_now;
+
+	ae_diff = (ae_now + ersc_now) - (ae_auto + ersc_auto);
+	if (ae_diff < 0)
+		ae_diff = 0;
+
+	if (ersc_now < 0) {
+		if (ae_diff >= AE_MAXDIFF)
+			ae_offset = -AE_OFSETVAL - ersc_now;
+		else {
+#ifdef CONFIG_LOAD_FILE
+			ae_offset = -gtable_buf[ae_diff / 10] - ersc_now;
+#else
+			ae_offset = -aeoffset_table[ae_diff / 10] - ersc_now;
+#endif
+		}
+	} else {
+		if (ae_diff >= AE_MAXDIFF)
+			ae_offset = -AE_OFSETVAL;
+		else {
+#ifdef CONFIG_LOAD_FILE
+			ae_offset = -gtable_buf[ae_offset / 10];
+#else
+			ae_offset = -aeoffset_table[ae_offset / 10];
+#endif
+		}
+	}
+
+	isx012_writew(sd, REG_CAP_GAINOFFSET, ae_offset);
+	return 0;
+}
+
+static int isx012_cancel_af(struct v4l2_subdev *sd, bool flash)
+{
+	struct isx012_state *state = to_state(sd);
+
+	if (state->focus.mode == FOCUS_MODE_MACRO)
+		isx012_set_from_table(sd, "cancel_af_macro",
+			&state->regs->cancel_af_macro, 1, 0);
+	else
+		isx012_set_from_table(sd, "cancel_af_normal",
+			&state->regs->cancel_af_normal, 1, 0);
+
+	if (flash)
+		isx012_post_sensor_flash(sd);
+
+	isx012_return_focus(sd);
+
+	return 0;
+}
+
+/* PX: Prepare AF Flash */
+static int isx012_af_start_preflash(struct v4l2_subdev *sd, u32 touch)
+{
+	struct isx012_state *state = to_state(sd);
+	u32 val = 0;
+	int count;
+	bool flash = false;
+
+	cam_trace("E\n");
+
+	if (state->sensor_mode == SENSOR_MOVIE)
+		return 0;
+
+	cam_dbg("Start SINGLE AF, flash mode %d\n", state->flash_mode);
+
+	state->focus.preflash = PREFLASH_OFF;
+	state->light_level = LUX_LEVEL_MAX;
+
+	/* We unlock AE, AWB if not going to capture mode after AF
+	 * for market app. */
+	if (state->focus.lock) {
+		isx012_writeb(sd, REG_MODESEL, 0x0);
+		msleep_debug(200, true);
+		state->focus.lock = 0;
+	}
+
+	if (!touch)
+		isx012_set_from_table(sd, "af_window_reset",
+			&state->regs->af_window_reset, 1, 0);
+
+	isx012_get_light_level(sd, &state->light_level);
+
+	switch (state->flash_mode) {
+	case FLASH_MODE_AUTO:
+		if (state->light_level < state->lux_level_flash) {
+			/* flash not needed */
+			break;
+		}
+
+	case FLASH_MODE_ON:
+		flash = true;
+		state->focus.preflash = PREFLASH_ON;
+		isx012_pre_sensor_flash(sd);
+		isx012_flash_torch(sd, ISX012_FLASH_ON);
+		break;
+
+	case FLASH_MODE_OFF:
+		break;
+
+	default:
+		break;
+	}
+
+	/* Check AE-stable */
+	if (flash) {
+		for (count = 0; count < ISX012_CNT_AE_STABLE; count++) {
+			if (state->focus.start == AUTO_FOCUS_OFF) {
+				cam_info("af_start_preflash: "
+					"AF is cancelled!\n");
+				state->focus.status = AF_RESULT_CANCELLED;
+				goto cancel_out;
+			}
+
+			isx012_readb(sd, REG_MODESEL_FIX, &val);
+			if ((u8)val == 0x01)
+				break;
+
+			msleep_debug(10, false);
+		}
+		if (count >= ISX012_CNT_AE_STABLE)
+			cam_info("start preflash: fail to check modesel_fix\n\n\n");
+		else
+			cam_dbg("start preflash: 1st check count=%d\n", count);
+
+		for (count = 0; count < ISX012_CNT_AE_STABLE; count++) {
+			if (state->focus.start == AUTO_FOCUS_OFF) {
+				cam_info("af_start_preflash: "
+					"AF is cancelled!\n");
+				state->focus.status = AF_RESULT_CANCELLED;
+				goto cancel_out;
+			}
+
+			isx012_readb(sd, REG_HALF_MOVE_STS, &val);
+			if ((u8)val == 0x00)
+				break;
+
+			msleep_debug(10, false);
+		}
+		if (count >= ISX012_CNT_AE_STABLE)
+			cam_info("start preflash: fail to check half_move_sts\n\n\n");
+		else
+			cam_dbg("start preflash: 2nd check count=%d\n", count);
+	}
+
+cancel_out:
+	/* If AF cancel, finish pre-flash process. */
+	if (state->focus.status == AF_RESULT_CANCELLED) {
+		if (flash) {
+			isx012_flash_torch(sd, ISX012_FLASH_OFF);
+			state->focus.preflash = PREFLASH_NONE;
+		}
+
+		isx012_cancel_af(sd, flash);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int isx012_do_af(struct v4l2_subdev *sd, u32 touch)
+{
+	struct isx012_state *state = to_state(sd);
+	u32 read_value = 0, ae_scl = 0;
+	u32 count = 0;
+	bool flash = false;
+
+	cam_trace("E\n");
+
+	/* We do not go to half-release mode if setting FLASH_ON.
+	 * And note that flash variable should only be set to true
+	 * in camera mode. */
+	if (state->focus.preflash == PREFLASH_ON)
+		flash = true;
+
+	if (state->sensor_mode == SENSOR_MOVIE) {
+		isx012_set_from_table(sd, "af_camcorder_start",
+			&state->regs->af_camcorder_start, 1, 0);
+	} else
+		isx012_transit_half_mode(sd);
+
+	/* Check the result of AF */
+	for (count = 0; count < AF_SEARCH_COUNT; count++) {
+		if (state->focus.start == AUTO_FOCUS_OFF) {
+			cam_dbg("do_af: AF is cancelled while doing\n");
+			state->focus.status = AF_RESULT_CANCELLED;
+			goto cancel_out;
+		}
+
+		isx012_readb(sd, REG_AF_STATE, &read_value);
+		if ((u8)read_value == 8)
+			break;
+
+		af_dbg("AF state= %d(0x%X)\n", read_value, read_value);
+		msleep_debug(30, false);
+	}
+
+	if (unlikely(count >= AF_SEARCH_COUNT)) {
+		cam_warn("warning, AF check failed. val=0x%X\n\n", read_value);
+		isx012_writeb(sd, REG_INTCLR, 0x10);
+		state->focus.status = AF_RESULT_FAILED;
+		goto check_fail;
+	}
+
+	isx012_writeb(sd, REG_INTCLR, 0x10);
+	isx012_readb(sd, REG_AF_RESUNT, &read_value);
+	if ((u8)read_value == 0x01)
+		state->focus.status = AF_RESULT_SUCCESS;
+	else {
+		state->focus.status = AF_RESULT_FAILED;
+		af_dbg("AF Fail. AF_RESULT reg=0x%X\n", (u8)read_value);
+	}
+
+check_fail:
+	if (flash) {
+		isx012_readw(sd, REG_ERRSCL_NOW,
+			&state->exposure.ae_offset.ersc_now);
+		isx012_readw(sd, REG_USER_AESCL_NOW,
+			&state->exposure.ae_offset.ae_now);
+		isx012_readw(sd, REG_AESCL, &ae_scl);
+	}
+
+	if (touch)
+		isx012_set_from_table(sd, "af_touch_saf_off",
+			&state->regs->af_touch_saf_off, 1, 0);
+	else
+		isx012_set_from_table(sd, "af_saf_off",
+			&state->regs->af_saf_off, 1, 0);
+
+	msleep_debug(66, true); /* Wait 1V time(66ms) */
+	if (state->focus.start == AUTO_FOCUS_OFF) {
+		cam_dbg("do_af: AF is cancelled 02\n");
+		state->focus.status = AF_RESULT_CANCELLED;
+		goto cancel_out;
+	}
+
+	if (flash) {
+		isx012_writew(sd, REG_MANOUTGAIN,
+			(u16)ae_scl - AE_SCL_SUBRACT_VALUE);
+		isx012_set_ae_gainoffset(sd);
+		isx012_flash_torch(sd, ISX012_FLASH_OFF);
+		state->focus.ae_manual_mode = touch ? 1 : 0;
+	}
+
+cancel_out:
+	if (state->focus.status == AF_RESULT_CANCELLED) {
+		cam_dbg("Single AF cancelled.\n");
+		if (flash) {
+			isx012_flash_torch(sd, ISX012_FLASH_OFF);
+			state->focus.preflash = PREFLASH_NONE;
+		}
+
+		isx012_cancel_af(sd, flash);
+	} else {
+		if (state->sensor_mode == SENSOR_MOVIE)
+			isx012_return_focus(sd);
+
+		state->focus.start = AUTO_FOCUS_OFF;
+		cam_dbg("Single AF finished(0x%X)\n", state->focus.status);
+		if (!touch)
+			state->focus.lock = 1; /* fix me */
+	}
+
+	return 0;
+}
+
+/* PX: Set AF */
+static int isx012_set_af(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("%s: %s, focus mode %d\n", __func__,
+			val ? "start" : "stop", state->focus.mode);
+
+	if (unlikely((u32)val >= AUTO_FOCUS_MAX)) {
+		cam_err("%s: error, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	if (state->focus.start == val)
+		return 0;
+
+	state->focus.start = val;
+
+	if (val == AUTO_FOCUS_ON) {
+		err = queue_work(state->workqueue, &state->af_work);
+		if (likely(err))
+			state->focus.status = AF_RESULT_DOING;
+		else
+			cam_warn("warning, AF is still processing.\n");
+	} else {
+		/* Cancel AF */
+		cam_info("set_af: AF cancel requested!\n");
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Stop AF */
+static int isx012_stop_af(struct v4l2_subdev *sd, s32 touch)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	cam_trace("E\n");
+	/* mutex_lock(&state->af_lock); */
+
+	switch (state->focus.status) {
+	case AF_RESULT_FAILED:
+	case AF_RESULT_SUCCESS:
+		cam_dbg("Stop AF, focus mode %d, AF result %d\n",
+			state->focus.mode, state->focus.status);
+
+		if (state->focus.mode == FOCUS_MODE_MACRO)
+			isx012_set_from_table(sd, "cancel_af_macro",
+				&state->regs->cancel_af_macro, 1, 0);
+		else
+			isx012_set_from_table(sd, "cancel_af_normal",
+				&state->regs->cancel_af_normal, 1, 0);
+
+		state->focus.status = AF_RESULT_CANCELLED;
+		state->focus.preflash = PREFLASH_NONE;
+		break;
+
+	case AF_RESULT_CANCELLED:
+		break;
+
+	default:
+		cam_warn("%s: WARNING, unnecessary calling. AF status=%d\n",
+			__func__, state->focus.status);
+		/* Return 0. */
+		goto err_out;
+		break;
+	}
+
+#if 0
+	if (!touch) {
+		/* We move lens to default position if af is cancelled.*/
+		err = isx012_return_focus(sd);
+		if (unlikely(err)) {
+			cam_err("%s: error, fail to af_norma_mode (%d)\n",
+				__func__, err);
+			goto err_out;
+		}
+	}
+#endif
+	/* mutex_unlock(&state->af_lock); */
+	cam_trace("X\n");
+	return 0;
+
+err_out:
+	/* mutex_unlock(&state->af_lock); */
+	return err;
+}
+
+static void isx012_af_worker(struct work_struct *work)
+{
+	struct isx012_state *state = container_of(work, \
+			struct isx012_state, af_work);
+	struct v4l2_subdev *sd = &state->sd;
+	int err = -EINVAL;
+	u32 touch;
+
+	mutex_lock(&state->af_lock);
+	touch = state->focus.touch;
+
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		err = isx012_af_start_preflash(sd, touch);
+		if (unlikely(err))
+			goto out;
+
+		if (state->focus.status == AF_RESULT_CANCELLED)
+			goto out;
+	}
+
+	isx012_do_af(sd, touch);
+
+out:
+	state->focus.touch = 0;
+	mutex_unlock(&state->af_lock);
+	return;
+}
+
+/* PX: Set focus mode */
+static int isx012_set_focus_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+	u32 cancel = 0;
+	u8 focus_mode = (u8)val;
+
+	cam_dbg("%s val =%d(0x%X)\n", __func__, val, val);
+
+	if (state->focus.mode == val)
+		return 0;
+
+	cancel = (u32)val & FOCUS_MODE_DEFAULT;
+
+	mutex_lock(&state->af_lock);
+
+	if (cancel)
+		isx012_stop_af(sd, 0);
+
+	/* check focus mode of lower byte  */
+	switch (focus_mode) {
+	case FOCUS_MODE_MACRO:
+		isx012_set_from_table(sd, "af_macro_mode",
+			&state->regs->af_macro_mode, 1, 0);
+		if (!cancel)
+			isx012_set_from_table(sd, "af_restart",
+				&state->regs->af_restart, 1, 0);
+
+		state->focus.mode = focus_mode;
+		break;
+
+	case FOCUS_MODE_INFINITY:
+	case FOCUS_MODE_AUTO:
+	case FOCUS_MODE_FIXED:
+		isx012_set_from_table(sd, "af_normal_mode",
+			&state->regs->af_normal_mode, 1, 0);
+		if (!cancel)
+			isx012_set_from_table(sd, "af_restart",
+				&state->regs->af_restart, 1, 0);
+		state->focus.mode = focus_mode;
+		break;
+
+	case FOCUS_MODE_FACEDETECT:
+	case FOCUS_MODE_CONTINOUS:
+	case FOCUS_MODE_TOUCH:
+		break;
+
+	default:
+		cam_err("focus mode: error, invalid val(0x%X)\n:", val);
+		goto err_out;
+		break;
+	}
+
+	mutex_unlock(&state->af_lock);
+	return 0;
+
+err_out:
+	mutex_unlock(&state->af_lock);
+	return err;
+}
+
+/* PX: */
+static int isx012_set_af_window(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	const s32 mapped_x = state->focus.pos_x;
+	const s32 mapped_y = state->focus.pos_y;
+	const u32 preview_width = state->preview->width;
+	const u32 preview_height = state->preview->height;
+	const u32 preview_ratio = FRM_RATIO(state->preview);
+	u32 start_x, start_y;
+	u32 ratio_width, ratio_height;
+	struct isx012_rect window = {0, 0, 0, 0};
+
+	cam_trace("E\n");
+	mutex_lock(&state->af_lock);
+
+	start_x = mapped_x - DEFAULT_WINDOW_WIDTH / 2;
+	start_y = mapped_y - DEFAULT_WINDOW_HEIGHT / 2;
+	ratio_width = 2592 * AF_PRECISION / preview_width;
+	ratio_height = 1944 * AF_PRECISION / preview_height;
+
+	af_dbg("start_x=%d, start_y=%d, ratio=(%d, %d)\n",
+			start_x, start_y, ratio_width, ratio_height);
+
+	/* Calculate x, y, width, height of window */
+	window.x = start_x * ratio_width / AF_PRECISION;
+	if (preview_ratio == FRMRATIO_HD) {
+		/* use width ratio*/
+		window.y = (start_y + 60) * ratio_width / AF_PRECISION;
+	} else if (preview_ratio == FRMRATIO_VGA)
+		window.y = start_y * ratio_height / AF_PRECISION;
+	else {
+		cam_err("AF window: not supported preview ratio %d\n",
+			preview_ratio);
+		window.y = start_y * ratio_height / AF_PRECISION;
+	}
+
+	window.width = DEFAULT_WINDOW_WIDTH * ratio_width / AF_PRECISION;
+	window.height = DEFAULT_WINDOW_HEIGHT * ratio_height / AF_PRECISION;
+	af_dbg("window.x=%d, window.y=%d, " \
+		"window.width=%d, window.height=%d\n",
+		window.x, window.y, window.width, window.height);
+
+	/* Write x, y, width, height of window */
+	isx012_writew(sd, 0x6A50, window.x);
+	isx012_writew(sd, 0x6A52, window.y);
+	isx012_writew(sd, 0x6A54, window.width);
+	isx012_writew(sd, 0x6A56, window.height);
+	isx012_set_from_table(sd, "af_winddow_set",
+		&state->regs->af_winddow_set, 1, 0);
+	mutex_unlock(&state->af_lock);
+
+	cam_dbg("AF window position completed.\n");
+	cam_trace("X\n");
+
+	return 0;
+}
+
+static int isx012_set_touch_af(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EIO;
+
+	cam_trace("%s, x=%d y=%d\n", val ? "start" : "stop",
+			state->focus.pos_x, state->focus.pos_y);
+
+	state->focus.touch = val;
+
+	if (val) {
+		if (mutex_is_locked(&state->af_lock)) {
+			cam_warn("%s: WARNING, AF is busy\n", __func__);
+			return 0;
+		}
+
+		err = queue_work(state->workqueue, &state->af_win_work);
+		if (likely(!err))
+			cam_warn("WARNING, AF window is still processing\n");
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static void isx012_af_win_worker(struct work_struct *work)
+{
+	struct isx012_state *state = container_of(work, \
+				struct isx012_state, af_win_work);
+	struct v4l2_subdev *sd = &state->sd;
+
+	isx012_set_af_window(sd);
+}
+
+#if 0 /* DSLIM */
+static int isx012_init_param(struct v4l2_subdev *sd)
+{
+	struct v4l2_control ctrl;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(isx012_ctrls); i++) {
+		if (isx012_ctrls[i].value !=
+				isx012_ctrls[i].default_value) {
+			ctrl.id = isx012_ctrls[i].id;
+			ctrl.value = isx012_ctrls[i].value;
+			isx012_s_ctrl(sd, &ctrl);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#if 0 /* dslim */
+static int isx012_init_regs(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct isx012_state *state = to_state(sd);
+	u16 read_value = 0;
+	int err = -ENODEV;
+
+
+	/* we'd prefer to do this in probe, but the framework hasn't
+	 * turned on the camera yet so our i2c operations would fail
+	 * if we tried to do it in probe, so we have to do it here
+	 * and keep track if we succeeded or not.
+	 */
+
+	/* enter read mode */
+	err = isx012_i2c_write_twobyte(client, 0x002C, 0x7000);
+	if (unlikely(err < 0))
+		return -ENODEV;
+
+	isx012_i2c_write_twobyte(client, 0x002E, 0x0150);
+	isx012_i2c_read_twobyte(client, 0x0F12, &read_value);
+	if (likely(read_value == ISX012_CHIP_ID))
+		cam_info("Sensor ChipID: 0x%04X\n", ISX012_CHIP_ID);
+	else
+		cam_info("Sensor ChipID: 0x%04X, unknown ChipID\n", read_value);
+
+	isx012_i2c_write_twobyte(client, 0x002C, 0x7000);
+	isx012_i2c_write_twobyte(client, 0x002E, 0x0152);
+	isx012_i2c_read_twobyte(client, 0x0F12, &read_value);
+	if (likely(read_value == ISX012_CHIP_REV))
+		cam_info("Sensor revision: 0x%04X\n", ISX012_CHIP_REV);
+	else
+		cam_info("Sensor revision: 0x%04X, unknown revision\n",
+				read_value);
+
+	/* restore write mode */
+	err = isx012_i2c_write_twobyte(client, 0x0028, 0x7000);
+	CHECK_ERR_COND(err < 0, -ENODEV);
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+#endif
+
+static int isx012_wait_steamoff(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	struct isx012_stream_time *stream_time = &state->stream_time;
+	s32 elapsed_msec = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(!(state->pdata->is_mipi & state->need_wait_streamoff)))
+		return 0;
+
+	do_gettimeofday(&stream_time->curr_time);
+
+	elapsed_msec = GET_ELAPSED_TIME(stream_time->curr_time, \
+				stream_time->before_time) / 1000;
+
+	if (state->pdata->streamoff_delay > elapsed_msec) {
+		cam_info("stream-off: %dms + %dms\n", elapsed_msec,
+			state->pdata->streamoff_delay - elapsed_msec);
+		msleep_debug(state->pdata->streamoff_delay - elapsed_msec,
+			true);
+	} else
+		cam_info("stream-off: %dms\n", elapsed_msec);
+
+	state->need_wait_streamoff = 0;
+
+	return 0;
+}
+
+static int isx012_control_stream(struct v4l2_subdev *sd, u32 cmd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_info("STREAM %s\n", (cmd == STREAM_STOP) ? "STOP" : "START");
+
+	if (cmd == STREAM_STOP) {
+		isx012_writeb(sd, 0x00BF, 0x01);
+#ifdef CONFIG_DEBUG_NO_FRAME
+		isx012_stop_frame_checker(sd);
+#endif
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+		do_gettimeofday(&state->stream_time.before_time);
+		state->need_wait_streamoff = 1;
+#else
+		msleep_debug(150, true);
+#endif
+	} else {
+		isx012_writeb(sd, 0x00BF, 0x00);
+		return 0;
+	}
+
+	switch (state->runmode) {
+	case RUNMODE_CAPTURING:
+		cam_dbg("Capture Stop!\n");
+		state->runmode = RUNMODE_CAPTURING_STOP;
+
+#ifdef CONFIG_NEW_STREAM_DELAY
+		if (state->lowlux_night) {
+			state->pdata->streamoff_delay = 400;
+			state->lowlux_night = 0;
+		} else
+			state->pdata->streamoff_delay = 150;
+#endif
+		/* We turn flash off if one shot flash is still on. */
+		if (isx012_is_hwflash_on(sd))
+			isx012_flash_oneshot(sd, ISX012_FLASH_OFF);
+
+		if (state->focus.preflash == PREFLASH_ON)
+			isx012_post_sensor_flash(sd);
+		break;
+
+	case RUNMODE_RUNNING:
+		cam_dbg("Preview Stop!\n");
+		state->runmode = RUNMODE_RUNNING_STOP;
+#ifdef CONFIG_NEW_STREAM_DELAY
+		if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+			state->pdata->streamoff_delay = 150;
+		else
+			state->pdata->streamoff_delay = 66;
+#endif
+
+		break;
+
+	case RUNMODE_RECORDING:
+		state->runmode = RUNMODE_RECORDING_STOP;
+#ifdef CONFIG_NEW_STREAM_DELAY
+		state->pdata->streamoff_delay = 66;
+#endif
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+/* PX: Set flash mode */
+static int isx012_set_flash_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+
+	/* movie flash mode should be set when recording is started */
+/*	if (state->sensor_mode == SENSOR_MOVIE && !state->recording)
+		return 0;*/
+
+	if (state->flash_mode == val) {
+		cam_dbg("the same flash mode=%d\n", val);
+		return 0;
+	}
+
+	if (val == FLASH_MODE_TORCH)
+		isx012_flash_torch(sd, ISX012_FLASH_ON);
+
+	if ((state->flash_mode == FLASH_MODE_TORCH)
+	    && (val == FLASH_MODE_OFF))
+		isx012_flash_torch(sd, ISX012_FLASH_OFF);
+
+	state->flash_mode = val;
+	cam_dbg("Flash mode = %d\n", val);
+	return 0;
+}
+
+static int isx012_check_esd(struct v4l2_subdev *sd, s32 val)
+{
+	u32 data = 0, size_h = 0, size_v = 0;
+
+	isx012_readw(sd, REG_ESD, &data);
+	if (data != ESD_VALUE)
+		goto esd_out;
+
+	isx012_readw(sd, REG_HSIZE_MONI, &size_h);
+	isx012_readw(sd, REG_VSIZE_MONI, &size_v);
+	cam_info("preview size %dx%d\n", size_h, size_v);
+
+	isx012_readw(sd, REG_HSIZE_CAP, &size_h);
+	isx012_readw(sd, REG_VSIZE_CAP, &size_v);
+	cam_info("capture size %dx%d\n", size_h, size_v);
+
+	cam_info("Check ESD(%d): not detected\n\n", val);
+	return 0;
+
+esd_out:
+	cam_err("Check ESD(%d): ESD Shock detected! val=0x%X\n\n", data, val);
+	return -ERESTART;
+}
+
+/* returns the real iso currently used by sensor due to lighting
+ * conditions, not the requested iso we sent using s_ctrl.
+ */
+static inline int isx012_get_exif_iso(struct v4l2_subdev *sd, u16 *iso)
+{
+	static const u16 iso_table[] = { 0, 25, 32, 40, 50, 64, 80, 100,
+		125, 160, 200, 250, 320, 400, 500, 640, 800,
+		1000, 1250, 1600};
+	u32 val = 0;
+
+	isx012_readb(sd, REG_ISOSENS_OUT, &val);
+	if (unlikely(val < 1))
+		val = 1;
+	else if (unlikely(val > 19))
+		val = 19;
+
+	*iso = iso_table[val];
+
+	cam_dbg("reg=%d, ISO=%d\n", val, *iso);
+	return 0;
+}
+
+/* PX: Set ISO */
+static int __used isx012_set_iso(struct v4l2_subdev *sd, s32 val)
+{
+	struct isx012_state *state = to_state(sd);
+
+retry:
+	switch (val) {
+	case ISO_AUTO:
+	case ISO_50:
+	case ISO_100:
+	case ISO_200:
+	case ISO_400:
+		isx012_set_from_table(sd, "iso",
+			state->regs->iso, ARRAY_SIZE(state->regs->iso),
+			val);
+		break;
+
+	default:
+		cam_err("set_iso: error, not supported (%d)\n", val);
+		val = ISO_AUTO;
+		goto retry;
+		break;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Return exposure time (ms) */
+static inline int isx012_get_exif_exptime(struct v4l2_subdev *sd,
+						u32 *exp_time)
+{
+	u32 val_lsb = 0, val_msb = 0;
+
+	isx012_readw(sd, REG_SHT_TIME_OUT_L, &val_lsb);
+	isx012_readw(sd, REG_SHT_TIME_OUT_H, &val_msb);
+
+	*exp_time = (val_msb << 16) | (val_lsb & 0xFFFF);
+	cam_dbg("exposure time %dus\n", *exp_time);
+	return 0;
+}
+
+static inline void isx012_get_exif_flash(struct v4l2_subdev *sd,
+					u16 *flash)
+{
+	struct isx012_state *state = to_state(sd);
+
+	switch (state->flash_mode) {
+	case FLASH_MODE_OFF:
+		*flash |= EXIF_FLASH_MODE_SUPPRESSION;
+		break;
+
+	case FLASH_MODE_AUTO:
+		*flash |= EXIF_FLASH_MODE_AUTO;
+		break;
+
+	case FLASH_MODE_ON:
+	case FLASH_MODE_TORCH:
+		*flash |= EXIF_FLASH_MODE_FIRING;
+		break;
+
+	default:
+		break;
+	}
+
+	if (state->flash_on) {
+		*flash |= EXIF_FLASH_FIRED;
+		if (state->sensor_mode == SENSOR_CAMERA)
+			state->flash_on = 0;
+	}
+
+}
+
+/* PX: */
+static int isx012_get_exif(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	u32 exposure_time = 0;
+
+	/* exposure time */
+	state->exif.exp_time_den = 0;
+	isx012_get_exif_exptime(sd, &exposure_time);
+	/*WARN(!exposure_time, "WARNING: exposure time is 0\n");*/
+	if (exposure_time)
+		state->exif.exp_time_den = 1000 * 1000 / exposure_time;
+	else
+		state->exif.exp_time_den = 0;
+
+	/* iso */
+	state->exif.iso = 0;
+	isx012_get_exif_iso(sd, &state->exif.iso);
+
+	/* flash */
+	isx012_get_exif_flash(sd, &state->exif.flash);
+
+	cam_dbg("EXIF: ex_time_den=%d, iso=%d, flash=0x%02X\n",
+		state->exif.exp_time_den, state->exif.iso, state->exif.flash);
+
+	return 0;
+}
+
+static int isx012_set_preview_size(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	if (!state->update_frmsize)
+		return 0;
+
+	cam_dbg("set preview size(%dx%d)\n",
+		state->preview->width, state->preview->height);
+
+	isx012_writew(sd, REG_HSIZE_MONI, state->preview->width);
+	isx012_writew(sd, REG_VSIZE_MONI, state->preview->height);
+
+	state->update_frmsize = 0;
+
+	return 0;
+}
+
+static int isx012_start_preview(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("Camera Preview start, runmode = %d\n", state->runmode);
+
+	if ((state->runmode == RUNMODE_NOTREADY) ||
+	    (state->runmode == RUNMODE_CAPTURING)) {
+		cam_err("%s: error - Invalid runmode\n", __func__);
+		return -EPERM;
+	}
+
+	state->focus.status = AF_RESULT_NONE;
+	state->focus.preflash = PREFLASH_NONE;
+	state->focus.touch = 0;
+
+	/* Set movie mode if needed. */
+	isx012_transit_movie_mode(sd);
+
+	isx012_set_preview_size(sd);
+
+	if (state->runmode == RUNMODE_CAPTURING_STOP) {
+		if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+			isx012_set_from_table(sd, "night_reset",
+				&state->regs->lowlux_night_reset, 1, 0);
+	}
+
+	/* Transit preview mode */
+	err = isx012_transit_preview_mode(sd);
+	CHECK_ERR_MSG(err, "preview_mode(%d)\n", err);
+
+	err = isx012_is_cm_changed(sd);
+	CHECK_ERR(err);
+	isx012_control_stream(sd, STREAM_START);
+
+#ifdef CONFIG_DEBUG_NO_FRAME
+	isx012_start_frame_checker(sd);
+#endif
+
+	if (state->runmode == RUNMODE_CAPTURING_STOP) {
+		isx012_return_focus(sd);
+		state->focus.lock = 0;
+	}
+
+	state->runmode = (state->sensor_mode == SENSOR_CAMERA) ?
+			RUNMODE_RUNNING : RUNMODE_RECORDING;
+	return 0;
+}
+
+static int isx012_start_video_preview(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("Video Preview start, runmode = %d (Not Implemented)\n",
+		state->runmode);
+	return err;
+}
+
+static int isx012_start_capture(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -ENODEV, count;
+	u32 lux = 0, val = 0;
+
+	cam_trace("E\n");
+
+	/* Set capture size */
+	err = isx012_set_capture_size(sd);
+	CHECK_ERR_MSG(err, "fail to set capture size (%d)\n", err);
+
+	if (state->focus.ae_manual_mode) {
+		isx012_writeb(sd, REG_AE_SN1, 0x02);
+		isx012_writeb(sd, REG_AE_SN4, 0x02);
+		isx012_writeb(sd, REG_AE_SN7, 0x02);
+		isx012_writeb(sd, REG_AE_SN11, 0x02);
+
+		msleep_debug(66, true); /* Wait 1v time(66ms) */
+	}
+
+	/* Set flash */
+	switch (state->flash_mode) {
+	case FLASH_MODE_AUTO:
+		/* 3rd party App could do capturing without AF. So we check
+		 * whether AF is executed  before capture and  turn on flash
+		 * if needed. But we do not consider low-light capture of Market
+		 * App. */
+		if (state->focus.preflash == PREFLASH_NONE) {
+			isx012_get_light_level(sd, &lux);
+			if (lux < state->lux_level_flash)
+				break;
+		} else if (state->focus.preflash == PREFLASH_OFF)
+			break;
+		/* We do not break. */
+
+	case FLASH_MODE_ON:
+		isx012_flash_oneshot(sd, ISX012_FLASH_ON);
+		/* We here don't need to set state->flash_on to 1 */
+		break;
+
+	case FLASH_MODE_OFF:
+	default:
+		break;
+	}
+
+	/* Set here lowlux_night field for night shot of 3rd party App.
+	 * Refer to comments of above switch() statements */
+
+	/* Transit to capture mode */
+	err = isx012_transit_capture_mode(sd);
+	CHECK_ERR_MSG(err, "fail to capture_mode (%d)\n", err);
+
+	err = isx012_is_cm_changed(sd);
+	CHECK_ERR(err);
+
+	isx012_control_stream(sd, STREAM_START);
+
+#ifdef CONFIG_DEBUG_NO_FRAME
+	isx012_start_frame_checker(sd);
+#endif
+
+	if (state->focus.preflash == PREFLASH_ON) {
+		msleep_debug(210, true);
+		for (count = 0; count < ISX012_CNT_CAPTURE_AWB; count++) {
+			isx012_readb(sd, REG_AWBSTS, &val);
+			if ((val & 0x06) != 0) {
+				cam_trace("AWB stable. cnt=%d\n", count);
+				break;
+			}
+			msleep_debug(30, false);
+		}
+	}
+
+	state->runmode = RUNMODE_CAPTURING;
+
+	/* Get EXIF */
+	isx012_get_exif(sd);
+
+	return 0;
+}
+
+/* PX(NEW) */
+static int isx012_s_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+{
+	struct isx012_state *state = to_state(sd);
+	s32 previous_index = 0;
+
+	cam_dbg("%s: pixelformat = 0x%x, colorspace = 0x%x, width = %d, height = %d\n",
+		__func__, fmt->code, fmt->colorspace, fmt->width, fmt->height);
+
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	if (fmt->field < IS_MODE_CAPTURE_STILL)
+		state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	else
+		state->format_mode = V4L2_PIX_FMT_MODE_CAPTURE;
+
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		previous_index = state->preview ? state->preview->index : -1;
+		isx012_set_framesize(sd, isx012_preview_frmsizes,
+			ARRAY_SIZE(isx012_preview_frmsizes), true);
+
+		if (previous_index != state->preview->index)
+			state->update_frmsize = 1;
+	} else {
+		/*
+		 * In case of image capture mode,
+		 * if the given image resolution is not supported,
+		 * use the next higher image resolution. */
+		isx012_set_framesize(sd, isx012_capture_frmsizes,
+			ARRAY_SIZE(isx012_capture_frmsizes), false);
+
+		/* for maket app.
+		 * Samsung camera app does not use unmatched ratio.*/
+		if (unlikely(FRM_RATIO(state->preview)
+		    != FRM_RATIO(state->capture))) {
+			cam_warn("%s: warning, capture ratio " \
+				"is different with preview ratio\n",
+				__func__);
+		}
+	}
+
+	return 0;
+}
+
+static int isx012_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
+					enum v4l2_mbus_pixelcode *code)
+{
+	cam_dbg("%s: index = %d\n", __func__, index);
+
+	if (index >= ARRAY_SIZE(capture_fmts))
+		return -EINVAL;
+
+	*code = capture_fmts[index].code;
+
+	return 0;
+}
+
+static int isx012_try_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+{
+	int num_entries;
+	int i;
+
+	num_entries = ARRAY_SIZE(capture_fmts);
+
+	cam_dbg("%s: code = 0x%x , colorspace = 0x%x, num_entries = %d\n",
+		__func__, fmt->code, fmt->colorspace, num_entries);
+
+	for (i = 0; i < num_entries; i++) {
+		if (capture_fmts[i].code == fmt->code &&
+		    capture_fmts[i].colorspace == fmt->colorspace) {
+			cam_dbg("%s: match found, returning 0\n", __func__);
+			return 0;
+		}
+	}
+
+	cam_err("%s: no match found, returning -EINVAL\n", __func__);
+	return -EINVAL;
+}
+
+
+static int isx012_enum_framesizes(struct v4l2_subdev *sd,
+				  struct v4l2_frmsizeenum *fsize)
+{
+	struct isx012_state *state = to_state(sd);
+
+	/*
+	* The camera interface should read this value, this is the resolution
+	* at which the sensor would provide framedata to the camera i/f
+	* In case of image capture,
+	* this returns the default camera resolution (VGA)
+	*/
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		if (unlikely(state->preview == NULL)) {
+			cam_err("%s: error\n", __func__);
+			return -EFAULT;
+		}
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->preview->width;
+		fsize->discrete.height = state->preview->height;
+	} else {
+		if (unlikely(state->capture == NULL)) {
+			cam_err("%s: error\n", __func__);
+			return -EFAULT;
+		}
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->capture->width;
+		fsize->discrete.height = state->capture->height;
+	}
+
+	return 0;
+}
+
+static int isx012_g_parm(struct v4l2_subdev *sd,
+			struct v4l2_streamparm *param)
+{
+	return 0;
+}
+
+static int isx012_s_parm(struct v4l2_subdev *sd,
+			struct v4l2_streamparm *param)
+{
+	struct isx012_state *state = to_state(sd);
+
+	state->req_fps = param->parm.capture.timeperframe.denominator /
+			param->parm.capture.timeperframe.numerator;
+
+	cam_dbg("s_parm state->fps=%d, state->req_fps=%d\n",
+		state->fps, state->req_fps);
+
+	if ((state->req_fps < 0) || (state->req_fps > 30)) {
+		cam_err("%s: error, invalid frame rate %d. we'll set to 30\n",
+				__func__, state->req_fps);
+		state->req_fps = 0;
+	}
+
+	return isx012_set_frame_rate(sd, state->req_fps);
+}
+
+static int isx012_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	if (!state->initialized) {
+		cam_err("%s: WARNING, camera not initialized\n", __func__);
+		return 0;
+	}
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.exp_time_den;
+		else
+			ctrl->value = 24;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.iso;
+		else
+			ctrl->value = 100;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_FLASH:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.flash;
+		else
+			isx012_get_exif_flash(sd, (u16 *)ctrl->value);
+		break;
+
+#if !defined(CONFIG_CAM_YUV_CAPTURE)
+	case V4L2_CID_CAM_JPEG_MAIN_SIZE:
+		ctrl->value = state->jpeg.main_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_OFFSET:
+		ctrl->value = state->jpeg.main_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_SIZE:
+		ctrl->value = state->jpeg.thumb_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_OFFSET:
+		ctrl->value = state->jpeg.thumb_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_QUALITY:
+		ctrl->value = state->jpeg.quality;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MEMSIZE:
+		ctrl->value = SENSOR_JPEG_SNAPSHOT_MEMSIZE;
+		break;
+#endif
+
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		ctrl->value = state->focus.status;
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+	case V4L2_CID_CAMERA_EFFECT:
+	case V4L2_CID_CAMERA_CONTRAST:
+	case V4L2_CID_CAMERA_SATURATION:
+	case V4L2_CID_CAMERA_SHARPNESS:
+	case V4L2_CID_CAMERA_OBJ_TRACKING_STATUS:
+	case V4L2_CID_CAMERA_SMART_AUTO_STATUS:
+	default:
+		cam_err("%s: WARNING, unknown Ctrl-ID 0x%x\n",
+					__func__, ctrl->id);
+		err = 0; /* we return no error. */
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	return err;
+}
+
+static int isx012_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -ENOIOCTLCMD;
+
+	if (!state->initialized && ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE) {
+		cam_warn("%s: WARNING, camera not initialized. ID = %d(0x%X)\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE,
+			ctrl->id - V4L2_CID_PRIVATE_BASE);
+		return 0;
+	}
+
+	cam_dbg("%s: ID =%d, val = %d\n",
+		__func__, ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = isx012_set_sensor_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		state->focus.pos_x = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		state->focus.pos_y = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		err = isx012_set_touch_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		err = isx012_set_focus_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		err = isx012_set_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		err = isx012_set_flash_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = isx012_set_exposure(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		err = isx012_set_from_table(sd, "white balance",
+			state->regs->white_balance,
+			ARRAY_SIZE(state->regs->white_balance), ctrl->value);
+		state->wb.mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_EFFECT:
+		err = isx012_set_from_table(sd, "effects",
+			state->regs->effect,
+			ARRAY_SIZE(state->regs->effect), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_METERING:
+		err = isx012_set_from_table(sd, "metering",
+			state->regs->metering,
+			ARRAY_SIZE(state->regs->metering), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CONTRAST:
+		err = isx012_set_from_table(sd, "contrast",
+			state->regs->contrast,
+			ARRAY_SIZE(state->regs->contrast), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SATURATION:
+		err = isx012_set_from_table(sd, "saturation",
+			state->regs->saturation,
+			ARRAY_SIZE(state->regs->saturation), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SHARPNESS:
+		err = isx012_set_from_table(sd, "sharpness",
+			state->regs->sharpness,
+			ARRAY_SIZE(state->regs->sharpness), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = isx012_set_scene_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_AE_LOCK_UNLOCK:
+		err = isx012_set_ae_lock(sd, ctrl->value, false);
+		break;
+
+	case V4L2_CID_CAMERA_AWB_LOCK_UNLOCK:
+		err = isx012_set_awb_lock(sd, ctrl->value, false);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = isx012_check_esd(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ISO:
+		err = isx012_set_iso(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FRAME_RATE:
+	default:
+		cam_err("%s: WARNING, unknown Ctrl-ID 0x%x\n",
+			__func__, ctrl->id);
+		err = 0; /* we return no error. */
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+	CHECK_ERR_MSG(err, "s_ctrl failed %d\n", err)
+
+	return 0;
+}
+
+static int isx012_s_ext_ctrl(struct v4l2_subdev *sd,
+			      struct v4l2_ext_control *ctrl)
+{
+	return 0;
+}
+
+static int isx012_s_ext_ctrls(struct v4l2_subdev *sd,
+				struct v4l2_ext_controls *ctrls)
+{
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int ret;
+	int i;
+
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		ret = isx012_s_ext_ctrl(sd, ctrl);
+
+		if (ret) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int isx012_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("stream mode = %d\n", enable);
+
+	BUG_ON(!state->initialized);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->pdata->is_mipi)
+			err = isx012_control_stream(sd, STREAM_STOP);
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		switch (state->sensor_mode) {
+		case SENSOR_CAMERA:
+			if (state->format_mode == V4L2_PIX_FMT_MODE_CAPTURE)
+				err = isx012_start_capture(sd);
+			else
+				err = isx012_start_preview(sd);
+			break;
+
+		case SENSOR_MOVIE:
+			err = isx012_start_preview(sd);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_info("movie on");
+		state->recording = 1;
+		if (state->flash_mode != FLASH_MODE_OFF)
+			isx012_flash_torch(sd, ISX012_FLASH_ON);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_info("movie off");
+		state->recording = 0;
+		if (state->flash_on)
+			isx012_flash_torch(sd, ISX012_FLASH_OFF);
+		break;
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	case STREAM_MODE_WAIT_OFF:
+		isx012_wait_steamoff(sd);
+		break;
+#endif
+	default:
+		cam_err("%s: error - Invalid stream mode\n", __func__);
+		break;
+	}
+
+	CHECK_ERR_MSG(err, "failed\n");
+
+	return 0;
+}
+
+#if 0 /* DSLIM */
+static int isx012_reset(struct v4l2_subdev *sd, u32 val)
+{
+	struct isx012_state *state = to_state(sd);
+
+	cam_trace("EX\n");
+
+	isx012_return_focus(sd);
+	state->initialized = 0;
+
+	return 0;
+}
+#endif
+
+void isx012_Sensor_Calibration(struct v4l2_subdev *sd)
+{
+	int status = 0;
+	int temp = 0;
+
+	cam_trace("EX\n");
+
+	/* Read OTP1 */
+	isx012_readw(sd, 0x004F, &status);
+	boot_dbg("Cal: 0x004F read %x\n", status);
+
+	if ((status & 0x10) == 0x10) {
+		/* Read ShadingTable */
+		isx012_readw(sd, 0x005C, &status);
+		temp = (status&0x03C0)>>6;
+		boot_dbg("Cal: Read ShadingTable [0x%x]\n", temp);
+
+		/* Write Shading Table */
+		if (temp == 0x0)
+			ISX012_BURST_WRITE_LIST(ISX012_Shading_0);
+		else if (temp == 0x1)
+			ISX012_BURST_WRITE_LIST(ISX012_Shading_1);
+		else if (temp == 0x2)
+			ISX012_BURST_WRITE_LIST(ISX012_Shading_2);
+
+		/* Write NorR */
+		isx012_readw(sd, 0x0054, &status);
+		temp = status&0x3FFF;
+		boot_dbg("Cal: NorR read : %x\n", temp);
+		isx012_writew(sd, 0x6804, temp);
+
+		/* Write NorB */
+		isx012_readw(sd, 0x0056, &status);
+		temp = status&0x3FFF;
+		boot_dbg("Cal: NorB read : %x\n", temp);
+		isx012_writew(sd, 0x6806, temp);
+
+		/* Write PreR */
+		isx012_readw(sd, 0x005A, &status);
+		temp = (status&0x0FFC)>>2;
+		boot_dbg("Cal: PreR read : %x\n", temp);
+		isx012_writew(sd, 0x6808, temp);
+
+		/* Write PreB */
+		isx012_readw(sd, 0x005B, &status);
+		temp = (status&0x3FF0)>>4;
+		boot_dbg("Cal: PreB read : %x\n", temp);
+		isx012_writew(sd, 0x680A, temp);
+	} else {
+		/* Read OTP0 */
+		isx012_readw(sd, 0x0040, &status);
+		boot_dbg("Cal: 0x0040 read : %x\n", status);
+
+		if ((status & 0x10) == 0x10) {
+			/* Read ShadingTable */
+			isx012_readw(sd, 0x004D, &status);
+			temp = (status&0x03C0)>>6;
+			boot_dbg("Cal: Read ShadingTable [0x%x]\n", temp);
+
+			/* Write Shading Table */
+			if (temp == 0x0)
+				ISX012_BURST_WRITE_LIST(ISX012_Shading_0);
+			else if (temp == 0x1)
+				ISX012_BURST_WRITE_LIST(ISX012_Shading_1);
+			else if (temp == 0x2)
+				ISX012_BURST_WRITE_LIST(ISX012_Shading_2);
+
+			/* Write NorR */
+			isx012_readw(sd, 0x0045, &status);
+			temp = status&0x3FFF;
+			boot_dbg("Cal: NorR read : %x\n", temp);
+			isx012_writew(sd, 0x6804, temp);
+
+			/* Write NorB */
+			isx012_readw(sd, 0x0047, &status);
+			temp = status&0x3FFF;
+			boot_dbg("Cal: NorB read : %x\n", temp);
+			isx012_writew(sd, 0x6806, temp);
+
+			/* Write PreR */
+			isx012_readw(sd, 0x004B, &status);
+			temp = (status&0x0FFC)>>2;
+			boot_dbg("Cal: PreR read : %x\n", temp);
+			isx012_writew(sd, 0x6808, temp);
+
+			/* Write PreB */
+			isx012_readw(sd, 0x004C, &status);
+			temp = (status&0x3FF0)>>4;
+			boot_dbg("Cal: PreB read : %x\n", temp);
+			isx012_writew(sd, 0x680A, temp);
+		} else
+			ISX012_BURST_WRITE_LIST(ISX012_Shading_Nocal);
+	}
+}
+
+static inline int isx012_check_i2c(struct v4l2_subdev *sd, u16 data)
+{
+	int err;
+	u32 val;
+
+	err = isx012_readw(sd, 0x0000, &val);
+	if (unlikely(err))
+		return err;
+
+	cam_info("version: 0x%04X is 0x6017?\n", val);
+	return 0;
+}
+
+static int isx012_post_poweron(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+	int err;
+
+	/* It's assumed that Mclk is already enabled */
+	cam_trace("E\n");
+
+	err = isx012_check_i2c(sd, 0x1234);
+	if (err) {
+		cam_err("%s: error, I2C check fail\n", __func__);
+		return err;
+	}
+	cam_info("I2C check success!\n");
+
+	msleep_debug(10, false);
+	err = isx012_is_om_changed(sd);
+	CHECK_ERR(err);
+
+	/* Pre-Sleep */
+	cam_dbg("=== Bootup: pre-sleep mode ===\n");
+	isx012_set_from_table(sd, "set_pll_4",
+		&state->regs->set_pll_4, 1, 0);
+	msleep_debug(10, false);
+	err = isx012_is_om_changed(sd);
+	CHECK_ERR(err);
+
+	/* Sleep */
+	cam_dbg("=== Bootup: sleep mode ===\n");
+	isx012_writeb(sd, 0x00BF, 0x01);
+	/* Negate nSTBY pin */
+	isx012_hw_stby_on(sd, false);
+
+	msleep_debug(50, false);
+	err = isx012_is_om_changed(sd);
+	CHECK_ERR(err);
+
+	/* Active */
+	cam_dbg("=== Bootup: active mode ===\n");
+	err = isx012_is_cm_changed(sd);
+	CHECK_ERR(err);
+
+	isx012_writeb(sd, 0x5008, 0x00);
+	isx012_Sensor_Calibration(sd);
+	cam_dbg("calibration complete!\n");
+
+	cam_dbg("POWER ON END\n\n");
+	return 0;
+}
+
+static void isx012_init_parameter(struct v4l2_subdev *sd)
+{
+	struct isx012_state *state = to_state(sd);
+
+	state->runmode = RUNMODE_INIT;
+
+	/* Default state values */
+	state->scene_mode = SCENE_MODE_NONE;
+	state->wb.mode = WHITE_BALANCE_AUTO;
+	state->light_level = LUX_LEVEL_MAX;
+
+	/* Set update_frmsize to 1 for case of power reset */
+	state->update_frmsize = 1;
+
+	/* Initialize focus field for case of init after power reset. */
+	memset(&state->focus, 0, sizeof(state->focus));
+
+#ifdef CONFIG_DEBUG_NO_FRAME
+	state->frame_check = false;
+#endif
+	state->lux_level_flash = LUX_LEVEL_FLASH_ON;
+}
+
+static int isx012_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct isx012_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("%s: start\n", __func__);
+
+#ifdef CONFIG_LOAD_FILE
+	err = isx012_regs_table_init();
+#endif
+	err = isx012_post_poweron(sd);
+	CHECK_ERR_MSG(err, "power-on fail!\n");
+
+	err = isx012_set_from_table(sd, "init_reg",
+			       &state->regs->init_reg, 1, 0);
+	CHECK_ERR_MSG(err, "failed to initialize camera device\n");
+
+#ifdef CONFIG_VIDEO_ISX012_P8
+	isx012_set_from_table(sd, "antibanding",
+		&state->regs->antibanding, 1, 0);
+#endif
+
+	isx012_init_parameter(sd);
+	state->initialized = 1;
+
+	/* Call after setting state->initialized to 1 */
+	err = isx012_set_frame_rate(sd, state->req_fps);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int isx012_s_config(struct v4l2_subdev *sd,
+			int irq, void *platform_data)
+{
+	struct isx012_state *state = to_state(sd);
+	int i;
+#ifdef CONFIG_LOAD_FILE
+	int err = 0;
+#endif
+
+	if (!platform_data) {
+		cam_err("%s: error, no platform data\n", __func__);
+		return -ENODEV;
+	}
+	state->pdata = platform_data;
+	state->dbg_level = &state->pdata->dbg_level;
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	state->req_fmt.width = state->pdata->default_width;
+	state->req_fmt.height = state->pdata->default_height;
+
+	if (!state->pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_PIX_FMT;
+	else
+		state->req_fmt.pixelformat = state->pdata->pixelformat;
+
+	if (!state->pdata->freq)
+		state->freq = DEFAULT_MCLK;	/* 24MHz default */
+	else
+		state->freq = state->pdata->freq;
+
+	state->preview = state->capture = NULL;
+	state->sensor_mode = SENSOR_CAMERA;
+	state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	state->fps = 0;
+	state->req_fps = -1;
+
+	/* Initialize the independant HW module like flash here */
+	state->flash_mode = FLASH_MODE_OFF;
+	state->flash_on = 0;
+
+	for (i = 0; i < ARRAY_SIZE(isx012_ctrls); i++)
+		isx012_ctrls[i].value = isx012_ctrls[i].default_value;
+
+#ifdef ISX012_SUPPORT_FLASH
+	if (isx012_is_hwflash_on(sd))
+		state->ignore_flash = 1;
+#endif
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops isx012_core_ops = {
+	.init = isx012_init,	/* initializing API */
+	.g_ctrl = isx012_g_ctrl,
+	.s_ctrl = isx012_s_ctrl,
+	.s_ext_ctrls = isx012_s_ext_ctrls,
+	/*eset = isx012_reset, */
+};
+
+static const struct v4l2_subdev_video_ops isx012_video_ops = {
+	.s_mbus_fmt = isx012_s_mbus_fmt,
+	.enum_framesizes = isx012_enum_framesizes,
+	.enum_mbus_fmt = isx012_enum_mbus_fmt,
+	.try_mbus_fmt = isx012_try_mbus_fmt,
+	.g_parm = isx012_g_parm,
+	.s_parm = isx012_s_parm,
+	.s_stream = isx012_s_stream,
+};
+
+static const struct v4l2_subdev_ops isx012_ops = {
+	.core = &isx012_core_ops,
+	.video = &isx012_video_ops,
+};
+
+
+/*
+ * isx012_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int isx012_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct v4l2_subdev *sd;
+	struct isx012_state *state;
+	int err = -EINVAL;
+
+	state = kzalloc(sizeof(struct isx012_state), GFP_KERNEL);
+	if (unlikely(!state)) {
+		dev_err(&client->dev, "probe, fail to get memory\n");
+		return -ENOMEM;
+	}
+
+	mutex_init(&state->ctrl_lock);
+	mutex_init(&state->af_lock);
+
+	state->runmode = RUNMODE_NOTREADY;
+	sd = &state->sd;
+	strcpy(sd->name, ISX012_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &isx012_ops);
+
+	state->workqueue = create_workqueue("cam_workqueue");
+	if (unlikely(!state->workqueue)) {
+		dev_err(&client->dev, "probe, fail to create workqueue\n");
+		goto err_out;
+	}
+	INIT_WORK(&state->af_work, isx012_af_worker);
+	INIT_WORK(&state->af_win_work, isx012_af_win_worker);
+#ifdef CONFIG_DEBUG_NO_FRAME
+	INIT_WORK(&state->frame_work, isx012_frame_checker);
+#endif
+
+	err = isx012_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+	printk(KERN_DEBUG "%s %s: driver probed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+
+	return 0;
+
+err_out:
+	kfree(state);
+	return -ENOMEM;
+}
+
+static int isx012_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct isx012_state *state = to_state(sd);
+
+	destroy_workqueue(state->workqueue);
+
+	/* do softlanding */
+	if (state->initialized)
+		isx012_set_af_softlanding(sd);
+
+	/* Check whether flash is on when unlolading driver,
+	 * to preventing Market App from controlling improperly flash.
+	 * It isn't necessary in case that you power flash down
+	 * in power routine to turn camera off.*/
+	if (unlikely(state->flash_on && !state->ignore_flash))
+		isx012_flash_torch(sd, ISX012_FLASH_OFF);
+
+	v4l2_device_unregister_subdev(sd);
+	mutex_destroy(&state->ctrl_lock);
+	mutex_destroy(&state->af_lock);
+	kfree(state);
+
+	printk(KERN_DEBUG "%s %s: driver removed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static const struct i2c_device_id isx012_id[] = {
+	{ ISX012_DRIVER_NAME, 0 },
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, isx012_id);
+
+static struct i2c_driver v4l2_i2c_driver = {
+	.driver.name	= ISX012_DRIVER_NAME,
+	.probe		= isx012_probe,
+	.remove		= isx012_remove,
+	.id_table	= isx012_id,
+};
+
+static int __init v4l2_i2c_drv_init(void)
+{
+	pr_info("%s: %s called\n", __func__, ISX012_DRIVER_NAME); /* dslim*/
+	isx012_create_file(camera_class);
+	return i2c_add_driver(&v4l2_i2c_driver);
+}
+
+static void __exit v4l2_i2c_drv_cleanup(void)
+{
+	pr_info("%s: %s called\n", __func__, ISX012_DRIVER_NAME); /* dslim*/
+	i2c_del_driver(&v4l2_i2c_driver);
+}
+
+module_init(v4l2_i2c_drv_init);
+module_exit(v4l2_i2c_drv_cleanup);
+
+MODULE_DESCRIPTION("LSI ISX012 3MP SOC camera driver");
+MODULE_AUTHOR("Dong-Seong Lim <dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/isx012.h b/drivers/media/video/isx012.h
new file mode 100644
index 0000000..9e34992
--- /dev/null
+++ b/drivers/media/video/isx012.h
@@ -0,0 +1,701 @@
+/* drivers/media/video/isx012.h
+ *
+ * Driver for isx012 (3MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * - change date: 2012.04.17 12
+ */
+
+#ifndef __ISX012_H__
+#define __ISX012_H__
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/completion.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/isx012_platform.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/workqueue.h>
+
+#define ISX012_DRIVER_NAME	"ISX012"
+
+#define ISX012_DELAY		0xFFFF0000
+
+/************************************
+ * FEATURE DEFINITIONS
+ ************************************/
+#define CONFIG_CAM_YUV_CAPTURE
+#define CONFIG_CAM_I2C_LITTLE_ENDIAN
+/* #define CONFIG_LOAD_FILE */ /* for tuning */
+#define CONFIG_DEBUG_NO_FRAME
+#define CONFIG_NEW_STREAM_DELAY
+
+/** Debuging Feature **/
+#define CONFIG_CAM_DEBUG
+#define CONFIG_CAM_TRACE /* Enable it with CONFIG_CAM_DEBUG */
+/* #define CONFIG_CAM_AF_DEBUG *//* Enable it with CONFIG_CAM_DEBUG */
+/* #define DEBUG_WRITE_REGS */
+/***********************************/
+
+#ifdef CONFIG_VIDEO_ISX012_DEBUG
+enum {
+	ISX012_DEBUG_I2C		= 1U << 0,
+	ISX012_DEBUG_I2C_BURSTS	= 1U << 1,
+};
+static uint32_t isx012_debug_mask = ISX012_DEBUG_I2C_BURSTS;
+module_param_named(debug_mask, isx012_debug_mask, uint, S_IWUSR | S_IRUGO);
+
+#define isx012_debug(mask, x...) \
+	do { \
+		if (isx012_debug_mask & mask) \
+			pr_info(x);	\
+	} while (0)
+#else
+#define isx012_debug(mask, x...)
+#endif
+
+#define TAG_NAME	"["ISX012_DRIVER_NAME"]"" "
+#define cam_err(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_warn(fmt, ...)	\
+	printk(KERN_WARNING TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_info(fmt, ...)	\
+	printk(KERN_INFO TAG_NAME fmt, ##__VA_ARGS__)
+
+#if defined(CONFIG_CAM_DEBUG)
+#define cam_dbg(fmt, ...)	\
+	printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_DEBUG) \
+			printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_TRACE)
+#define cam_trace(fmt, ...)	cam_dbg("%s: " fmt, __func__, ##__VA_ARGS__);
+#else
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_TRACE) \
+			printk(KERN_DEBUG TAG_NAME "%s: " fmt, \
+				__func__, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_AF_DEBUG)
+#define af_dbg(fmt, ...)	cam_dbg(fmt, ##__VA_ARGS__);
+#else
+#define af_dbg(fmt, ...)
+#endif
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_BOOT_DEBUG)
+#define boot_dbg(fmt, ...)	cam_dbg(fmt, ##__VA_ARGS__);
+#else
+#define boot_dbg(fmt, ...)
+#endif
+
+#if 0
+#define cam_bug_on(arg...)	\
+	do { cam_err(arg); BUG_ON(1); } while (0)
+#else
+#define cam_bug_on(arg...)
+#endif
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return ret; } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+		if (unlikely(condition)) { \
+			cam_err("%s: error, " fmt, __func__, ##__VA_ARGS__); \
+			return ret; \
+		}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+
+#ifdef CONFIG_LOAD_FILE
+#define ISX012_BURST_WRITE_REGS(sd, A) ({ \
+	int ret; \
+		cam_info("BURST_WRITE_REGS: reg_name=%s from setfile\n", #A); \
+		ret = isx012_write_regs_from_sd(sd, #A); \
+		ret; \
+	})
+#else
+
+#define ISX012_BURST_WRITE_REGS(sd, A) \
+	isx012_burst_write_regs(sd, A, (sizeof(A) / sizeof(A[0])), #A)
+#endif
+
+#define ISX012_WRITE_LIST(A) \
+	isx012_i2c_write_list(A, (sizeof(A) / sizeof(A[0])), #A)
+#define ISX012_BURST_WRITE_LIST(A) \
+	isx012_i2c_burst_write_list(sd, A, (sizeof(A) / sizeof(A[0])), #A)
+
+/* result values returned to HAL */
+enum af_result_status {
+	AF_RESULT_NONE = 0x00,
+	AF_RESULT_FAILED = 0x01,
+	AF_RESULT_SUCCESS = 0x02,
+	AF_RESULT_CANCELLED = 0x04,
+	AF_RESULT_DOING = 0x08
+};
+
+enum af_operation_status {
+	AF_NONE = 0,
+	AF_START,
+	AF_CANCEL,
+};
+
+enum preflash_status {
+	PREFLASH_NONE = 0,
+	PREFLASH_OFF,
+	PREFLASH_ON,
+};
+
+enum isx012_oprmode {
+	ISX012_OPRMODE_VIDEO = 0,
+	ISX012_OPRMODE_IMAGE = 1,
+};
+
+enum stream_cmd {
+	STREAM_STOP,
+	STREAM_START,
+};
+
+enum wide_req_cmd {
+	WIDE_REQ_NONE,
+	WIDE_REQ_CHANGE,
+	WIDE_REQ_RESTORE,
+};
+
+/* Preview Size List: refer to the belows. */
+enum isx012_preview_frame_size {
+	PREVIEW_SZ_QCIF = 0,	/* 176x144 */
+	PREVIEW_SZ_320x240,	/* 320x240 */
+	PREVIEW_SZ_CIF,		/* 352x288 */
+	PREVIEW_SZ_528x432,	/* 528x432 */
+	PREVIEW_SZ_VGA,		/* 640x480 */
+	PREVIEW_SZ_D1,		/* 720x480 */
+	PREVIEW_SZ_880x720,	/* 880x720 */
+	PREVIEW_SZ_SVGA,	/* 800x600 */
+	PREVIEW_SZ_1024x576,	/* 1024x576, 16:9 */
+	PREVIEW_SZ_1024x616,	/* 1024x616, ? */
+	PREVIEW_SZ_XGA,		/* 1024x768 */
+	PREVIEW_SZ_PVGA,	/* 1280x720 */
+	PREVIEW_SZ_SXGA,	/* 1280x1024 */
+	PREVIEW_SZ_MAX,
+};
+
+/* Capture Size List: Capture size is defined as below.
+ *
+ *	CAPTURE_SZ_VGA:		640x480
+ *	CAPTURE_SZ_WVGA:	800x480
+ *	CAPTURE_SZ_SVGA:	800x600
+ *	CAPTURE_SZ_WSVGA:	1024x600
+ *	CAPTURE_SZ_1MP:		1280x960
+ *	CAPTURE_SZ_W1MP:	1600x960
+ *	CAPTURE_SZ_2MP:		UXGA - 1600x1200
+ *	CAPTURE_SZ_W2MP:	35mm Academy Offset Standard 1.66
+ *				2048x1232, 2.4MP
+ *	CAPTURE_SZ_3MP:		QXGA  - 2048x1536
+ *	CAPTURE_SZ_W4MP:	WQXGA - 2560x1536
+ *	CAPTURE_SZ_5MP:		2560x1920
+ */
+
+enum isx012_capture_frame_size {
+	CAPTURE_SZ_VGA = 0,	/* 640x480 */
+	CAPTURE_SZ_W1MP,	/* 1536x864. Samsung-defined */
+	CAPTURE_SZ_2MP,		/* UXGA - 1600x1200 */
+	CAPTURE_SZ_W2MP,	/* 2048x1152. Samsung-defined */
+	CAPTURE_SZ_3MP,		/* QXGA  - 2048x1536 */
+	CAPTURE_SZ_W4MP,	/* 2560x1440. Samsung-defined */
+	CAPTURE_SZ_5MP,		/* 2560x1920 */
+	CAPTURE_SZ_MAX,
+};
+
+#ifdef CONFIG_VIDEO_ISX012_P2
+#define PREVIEW_WIDE_SIZE	PREVIEW_SZ_1024x552
+#else
+#define PREVIEW_WIDE_SIZE	PREVIEW_SZ_1024x576
+#endif
+#define CAPTURE_WIDE_SIZE	CAPTURE_SZ_W2MP
+
+enum frame_ratio {
+	FRMRATIO_QCIF   = 12,   /* 11 : 9 */
+	FRMRATIO_VGA    = 13,   /* 4 : 3 */
+	FRMRATIO_D1     = 15,   /* 3 : 2 */
+	FRMRATIO_WVGA   = 16,   /* 5 : 3 */
+	FRMRATIO_HD     = 17,   /* 16 : 9 */
+};
+
+enum isx012_fps_index {
+	I_FPS_0,
+	I_FPS_7,
+	I_FPS_10,
+	I_FPS_12,
+	I_FPS_15,
+	I_FPS_25,
+	I_FPS_30,
+	I_FPS_MAX,
+};
+
+enum ae_awb_lock {
+	AEAWB_UNLOCK = 0,
+	AEAWB_LOCK,
+	AEAWB_LOCK_MAX,
+};
+
+enum runmode {
+	RUNMODE_NOTREADY,
+	RUNMODE_INIT,
+	/*RUNMODE_IDLE,*/
+	RUNMODE_RUNNING,	/* previewing */
+	RUNMODE_RUNNING_STOP,
+	RUNMODE_CAPTURING,
+	RUNMODE_CAPTURING_STOP,
+	RUNMODE_RECORDING,	/* camcorder mode */
+	RUNMODE_RECORDING_STOP,
+};
+
+enum isx012_stby_type {
+	ISX012_STBY_HW,
+	ISX012_STBY_SW,
+};
+
+struct isx012_control {
+	u32 id;
+	s32 value;
+	s32 default_value;
+};
+
+#define ISX012_INIT_CONTROL(ctrl_id, default_val) \
+	{					\
+		.id = ctrl_id,			\
+		.value = default_val,		\
+		.default_value = default_val,	\
+	}
+
+struct isx012_framesize {
+	s32 index;
+	u32 width;
+	u32 height;
+};
+
+#define FRM_RATIO(framesize) \
+	(((framesize)->width) * 10 / ((framesize)->height))
+
+struct isx012_fps {
+	u32 index;
+	u32 fps;
+};
+
+struct isx012_version {
+	u32 major;
+	u32 minor;
+};
+
+struct isx012_date_info {
+	u32 year;
+	u32 month;
+	u32 date;
+};
+
+struct isx012_firmware {
+	u32 addr;
+	u32 size;
+};
+
+struct isx012_jpeg_param {
+	u32 enable;
+	u32 quality;
+	u32 main_size;		/* Main JPEG file size */
+	u32 thumb_size;		/* Thumbnail file size */
+	u32 main_offset;
+	u32 thumb_offset;
+	/* u32 postview_offset; */
+};
+
+struct isx012_position {
+	s32 x;
+	s32 y;
+};
+
+struct isx012_rect {
+	s32 x;
+	s32 y;
+	u32 width;
+	u32 height;
+};
+
+struct gps_info_common {
+	u32 direction;
+	u32 dgree;
+	u32 minute;
+	u32 second;
+};
+
+struct isx012_gps_info {
+	u8 gps_buf[8];
+	u8 altitude_buf[4];
+	s32 gps_timeStamp;
+};
+
+struct isx012_focus {
+	enum v4l2_focusmode mode;
+	enum af_result_status status;
+	enum preflash_status preflash;
+
+	u32 pos_x;
+	u32 pos_y;
+
+	u32 start:1;	/* enum v4l2_auto_focus*/
+	u32 touch:1;
+	u32 lock:1;	/* fix me */
+	u32 ae_manual_mode:1;
+};
+
+/* struct for sensor specific data */
+struct isx012_ae_gain_offset {
+	u32	ae_auto;
+	u32	ae_now;
+	u32	ersc_auto;
+	u32	ersc_now;
+};
+
+/* Exposure */
+struct isx012_exposure {
+	struct isx012_ae_gain_offset ae_offset;
+	s32 val;
+	u32 ae_lock:1;
+};
+
+/* White Balance */
+struct isx012_whitebalance {
+	enum v4l2_wb_mode mode; /* wb mode */
+	u32 awb_lock:1;
+};
+
+struct isx012_exif {
+	u16 exp_time_den;
+	u16 iso;
+	u16 flash;
+
+	/*int bv;*/		/* brightness */
+	/*int ebv;*/		/* exposure bias */
+};
+
+/* EXIF - flash filed */
+#define EXIF_FLASH_FIRED		(0x01)
+#define EXIF_FLASH_MODE_FIRING		(0x01)
+#define EXIF_FLASH_MODE_SUPPRESSION	(0x01 << 1)
+#define EXIF_FLASH_MODE_AUTO		(0x03 << 3)
+
+struct isx012_stream_time {
+	struct timeval curr_time;
+	struct timeval before_time;
+};
+
+#define GET_ELAPSED_TIME(cur, before) \
+		(((cur).tv_sec - (before).tv_sec) * USEC_PER_SEC \
+		+ ((cur).tv_usec - (before).tv_usec))
+
+typedef struct isx012_regset {
+	u16 subaddr;
+	u32 value;
+	u32 len;
+} isx012_regset_t;
+
+#ifdef CONFIG_LOAD_FILE
+#define DEBUG_WRITE_REGS
+struct regset_table {
+	const char	*const name;
+};
+
+#define ISX012_REGSET(x, y)		\
+	[(x)] = {			\
+		.name		= #y,	\
+	}
+
+#define ISX012_REGSET_TABLE(y)	\
+	{				\
+		.name		= #y,	\
+	}
+
+#else /* !CONFIG_LOAD_FILE */
+
+struct regset_table {
+	const isx012_regset_t * const reg;
+	const u32	array_size;
+#ifdef DEBUG_WRITE_REGS
+	const char	* const name;
+#endif
+};
+
+#ifdef DEBUG_WRITE_REGS
+#define ISX012_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+	}
+#define ISX012_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+	}
+#else /* !DEBUG_WRITE_REGS */
+#define ISX012_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+	}
+#define ISX012_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+	}
+#endif /* DEBUG_WRITE_REGS */
+
+#endif /* CONFIG_LOAD_FILE */
+
+#define EV_MIN_VLAUE		EV_MINUS_4
+#define GET_EV_INDEX(EV)	((EV) - (EV_MIN_VLAUE))
+
+struct isx012_regs {
+	struct regset_table ev[GET_EV_INDEX(EV_MAX_V4L2)];
+	struct regset_table metering[METERING_MAX];
+	struct regset_table iso[ISO_MAX];
+	struct regset_table effect[IMAGE_EFFECT_MAX];
+	struct regset_table white_balance[WHITE_BALANCE_MAX];
+	struct regset_table preview_size[PREVIEW_SZ_MAX];
+	struct regset_table capture_size[CAPTURE_SZ_MAX];
+	struct regset_table scene_mode[SCENE_MODE_MAX];
+	struct regset_table saturation[SATURATION_MAX];
+	struct regset_table contrast[CONTRAST_MAX];
+	struct regset_table sharpness[SHARPNESS_MAX];
+	struct regset_table fps[I_FPS_MAX];
+	struct regset_table preview_return;
+	struct regset_table ae_lock_on;
+	struct regset_table ae_lock_off;
+	struct regset_table awb_lock_on;
+	struct regset_table awb_lock_off;
+#ifdef CONFIG_VIDEO_ISX012_P8
+	struct regset_table set_lowlight_cap;
+#endif
+	/* Flash */
+	struct regset_table flash_ae_line;
+	struct regset_table flash_on;
+	struct regset_table flash_off;
+
+	/* AF */
+	struct regset_table af_normal_mode;
+	struct regset_table af_macro_mode;
+	struct regset_table cancel_af_normal;
+	struct regset_table cancel_af_macro;
+	struct regset_table af_restart;
+	struct regset_table af_window_reset;
+	struct regset_table af_winddow_set;
+	struct regset_table af_saf_off;
+	struct regset_table af_touch_saf_off;
+	struct regset_table af_camcorder_start;
+	struct regset_table softlanding;
+
+	struct regset_table get_esd_status;
+
+	/* camera mode */
+	struct regset_table preview_mode;
+	struct regset_table capture_mode;
+	struct regset_table capture_mode_night;
+	struct regset_table halfrelease_mode;
+	struct regset_table halfrelease_mode_night;
+	struct regset_table camcorder_on;
+	struct regset_table camcorder_off;
+	struct regset_table lowlux_night_reset;
+
+	struct regset_table init_reg;
+	struct regset_table set_pll_4;
+#ifdef CONFIG_VIDEO_ISX012_P8
+	struct regset_table antibanding;
+#endif /* CONFIG_VIDEO_ISX012_P8 */
+};
+
+struct isx012_state {
+	struct isx012_platform_data *pdata;
+	struct v4l2_subdev sd;
+	struct v4l2_pix_format req_fmt;
+	const struct isx012_framesize *preview;
+	const struct isx012_framesize *capture;
+	struct isx012_focus focus;
+	struct isx012_exposure exposure;
+	struct isx012_whitebalance wb;
+	struct isx012_exif exif;
+#if !defined(CONFIG_CAM_YUV_CAPTURE)
+	struct isx012_jpeg_param jpeg;
+#endif
+	struct isx012_stream_time stream_time;
+	const struct isx012_regs *regs;
+	struct mutex ctrl_lock;
+	struct mutex af_lock;
+	struct workqueue_struct *workqueue;
+	struct work_struct af_work;
+	struct work_struct af_win_work;
+#ifdef CONFIG_DEBUG_NO_FRAME
+	struct work_struct frame_work;
+#endif
+	enum runmode runmode;
+	enum v4l2_sensor_mode sensor_mode;
+	enum v4l2_pix_format_mode format_mode;
+	enum v4l2_flash_mode flash_mode;
+	enum v4l2_scene_mode scene_mode;
+
+	s32 vt_mode;
+	s32 req_fps;
+	s32 fps;
+	s32 freq;		/* MCLK in Hz */
+	u32 one_frame_delay_ms;
+	u32 light_level;	/* light level */
+	u32 lux_level_flash;
+	u8 *dbg_level;
+#ifdef CONFIG_DEBUG_NO_FRAME
+	bool frame_check;
+#endif
+	u32 recording:1;
+	u32 hd_videomode:1;
+	u32 flash_on:1;
+	u32 ignore_flash:1;
+	u32 update_frmsize:1;
+	u32 need_wait_streamoff:1;
+	u32 initialized:1;
+	u32 lowlux_night:1;
+};
+
+static inline struct  isx012_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct isx012_state, sd);
+}
+
+extern struct class *camera_class;
+extern int isx012_create_file(struct class *cls);
+
+#if !defined(CONFIG_CAM_YUV_CAPTURE)
+/* JPEG MEMORY SIZE */
+#define SENSOR_JPEG_OUTPUT_MAXSIZE	0x29999A /*2726298bytes, 2.6M */
+#define EXTRA_MEMSIZE			(0 * SZ_1K)
+#define SENSOR_JPEG_SNAPSHOT_MEMSIZE \
+	(((SENSOR_JPEG_OUTPUT_MAXSIZE + EXTRA_MEMSIZE  + SZ_16K-1) / SZ_16K) * SZ_16K)
+#endif
+
+/*********** Sensor specific ************/
+#define ISX012_INTSRC_VINT		(0x01 << 5)
+
+#define POLL_TIME_MS		10
+#define CAPTURE_POLL_TIME_MS    1000
+
+/* maximum time for one frame in norma light */
+#define ONE_FRAME_DELAY_MS_NORMAL		66
+/* maximum time for one frame in low light: minimum 10fps. */
+#define ONE_FRAME_DELAY_MS_LOW			100
+/* maximum time for one frame in night mode: 6fps */
+#define ONE_FRAME_DELAY_MS_NIGHTMODE		166
+
+/* level at or below which we need to enable flash when in auto mode */
+#define LUX_LEVEL_MAX			0x00 /* the brightest */
+#define LUX_LEVEL_LOW			0x3D /* low light */
+#define LUX_LEVEL_FLASH_ON		0x2B
+
+/* Count for loop */
+#define ISX012_CNT_CAPTURE_FRM		100
+#define ISX012_CNT_CLEAR_VINT		20
+#define ISX012_CNT_AE_STABLE		100 /* for checking MODESEL_FIX */
+#define ISX012_CNT_CAPTURE_AWB		8
+#define ISX012_CNT_OM_CHECK		30
+#define ISX012_CNT_CM_CHECK		180 /* 160 -> 180 */
+
+#define AF_SEARCH_COUNT			80
+#define AE_STABLE_SEARCH_COUNT		7
+
+/* Sensor AF first,second window size.
+ * we use constant values intead of reading sensor register */
+#define DEFAULT_WINDOW_WIDTH		80
+#define DEFAULT_WINDOW_HEIGHT		80
+#define AF_PRECISION	100
+
+/*
+ * Register Address Definition
+ */
+#define REG_INTSTS			0x000E
+#define REG_INTCLR			0x0012
+#define REG_ESD				0x005E
+
+#define REG_MODESEL_FIX			0x0080
+#define REG_MODESEL			0x0081
+#define REG_HSIZE_MONI			0x0090
+#define REG_HSIZE_CAP			0x0092
+#define REG_VSIZE_MONI			0x0096
+#define REG_VSIZE_CAP			0x0098
+#define REG_CAPNUM			0x00B6
+
+#define REG_CAP_GAINOFFSET		0x0186
+#define REG_ISOSENS_OUT			0x019A
+#define REG_SHT_TIME_OUT_L		0x019C
+#define REG_SHT_TIME_OUT_H		0x019E
+
+#define REG_USER_GAINLEVEL_NOW		0x01A5
+#define REG_HALF_MOVE_STS		0x01B0
+#define REG_ERRSCL_AUTO			0x01CA
+#define REG_ERRSCL_NOW			0x01CC
+#define REG_USER_AESCL_AUTO		0x01CE
+#define REG_USER_AESCL_NOW		0x01D0
+
+#define REG_AWB_SN1			0x0282
+#define REG_AE_SN1			0x0294
+#define REG_AE_SN4			0x0297
+#define REG_AE_SN7			0x029A
+#define REG_AE_SN11			0x029E
+
+#define REG_CPUEXT			0x5000
+#define REG_MANOUTGAIN			0x5E02
+#define REG_VPARA_TRG			0x8800
+#define REG_AWBSTS			0x8A24
+#define REG_AF_STATE			0x8B8A
+#define REG_AF_RESUNT			0x8B8B
+#define REG_AESCL			0x8BC0
+
+/*
+ * Bit definition of register
+ */
+/* CPUEXT register */
+#define REG_CPUEXT_AE_HOLD		(0x01 << 1)
+#define REG_CPUEXT_AWB_HOLD		(0x01 << 2)
+
+/* interrupt register */
+#define REG_INTBIT_OM			(0x01 << 0)
+#define REG_INTBIT_CM			(0x01 << 1)
+#define REG_INTBIT_CAPNUM_END		(0x01 << 3)
+#define REG_INTBIT_VINT			(0x01 << 5)
+
+/* The Path of Setfile */
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#define TUNING_FILE_PATH "/mnt/sdcard/isx012_regs.h"
+#endif /* CONFIG_LOAD_FILE*/
+
+#include "isx012_regs.h"
+
+#endif /* __ISX012_H__ */
diff --git a/drivers/media/video/isx012_regs.h b/drivers/media/video/isx012_regs.h
new file mode 100644
index 0000000..4e05dbf
--- /dev/null
+++ b/drivers/media/video/isx012_regs.h
@@ -0,0 +1,11218 @@
+/* drivers/media/video/s5k5ccgx_regs-p4w.h
+ *
+ * Driver for s5k5ccgx (5MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Change Date: 2012.04.19
+ */
+
+#ifndef __ISX012_REGS_H__ 
+#define __ISX012_REGS_H__
+
+#define	AE_OFSETVAL 3450	//for tuning // max 5.1times
+#define	AE_MAXDIFF 5000	//for tuning // max =< 5000
+#define GLOWLIGHT_DEFAULT 0x002B	//for tuning
+#define GLOWLIGHT_ISO50 0xB52A	//for tuning
+#define GLOWLIGHT_ISO100 0x9DBA	//for tuning
+#define GLOWLIGHT_ISO200 0x864A	//for tuning
+#define GLOWLIGHT_ISO400 0x738A	//for tuning
+
+#define ESD_VALUE	0xA6A6
+
+/* change 4129 to 4802 */
+#define AE_SCL_SUBRACT_VALUE		4802
+
+const uint16_t aeoffset_table[] = { // normal 4.6times
+	0, 35, 70, 103, 136, 167, 198, 228, 257, 285,
+	313, 339, 366, 391, 416, 441, 465, 488, 511, 533,
+	555, 576, 597, 618, 638, 657, 677, 696, 714, 732,
+	750, 768, 785, 802, 818, 835, 851, 866, 882, 897,
+	912, 927, 941, 955, 969, 983, 997, 1010, 1023, 1036,
+	1049, 1061, 1074, 1086, 1098, 1109, 1121, 1133, 1144, 1155,
+	1166, 1177, 1187, 1198, 1208, 1219, 1229, 1239, 1248, 1258,
+	1268, 1277, 1286, 1296, 1305, 1314, 1322, 1331, 1340, 1348,
+	1357, 1365, 1373, 1381, 1389, 1397, 1405, 1413, 1420, 1428,
+	1435, 1443, 1450, 1457, 1464, 1471, 1478, 1485, 1492, 1499,
+	1505, 1512, 1518, 1525, 1531, 1538, 1544, 1550, 1556, 1562,
+	1568, 1574, 1580, 1585, 1591, 1597, 1602, 1608, 1613, 1619,
+	1624, 1629, 1635, 1640, 1645, 1650, 1655, 1660, 1665, 1670,
+	1675, 1679, 1684, 1689, 1693, 1698, 1703, 1707, 1712, 1716,
+	1720, 1725, 1729, 1733, 1737, 1742, 1746, 1750, 1754, 1758,
+	1762, 1766, 1770, 1774, 1777, 1781, 1785, 1789, 1792, 1796,
+	1800, 1803, 1807, 1810, 1814, 1817, 1821, 1824, 1828, 1831,
+	1834, 1837, 1841, 1844, 1847, 1850, 1853, 1856, 1860, 1863,
+	1866, 1869, 1872, 1875, 1877, 1880, 1883, 1886, 1889, 1892,
+	1894, 1897, 1900, 1903, 1905, 1908, 1911, 1913, 1916, 1918,
+	1921, 1923, 1926, 1928, 1931, 1933, 1936, 1938, 1941, 1943,
+	1945, 1948, 1950, 1952, 1954, 1957, 1959, 1961, 1963, 1965,
+	1968, 1970, 1972, 1974, 1976, 1978, 1980, 1982, 1984, 1986,
+	1988, 1990, 1992, 1994, 1996, 1998, 2000, 2002, 2003, 2005,
+	2007, 2009, 2011, 2013, 2014, 2016, 2018, 2020, 2021, 2023,
+	2025, 2026, 2028, 2030, 2031, 2033, 2034, 2036, 2038, 2039,
+	2041, 2042, 2044, 2045, 2047, 2048, 2050, 2051, 2053, 2054,
+	2056, 2057, 2059, 2060, 2061, 2063, 2064, 2066, 2067, 2068,
+	2070, 2071, 2072, 2074, 2075, 2076, 2077, 2079, 2080, 2081,
+	2082, 2084, 2085, 2086, 2087, 2089, 2090, 2091, 2092, 2093,
+	2094, 2096, 2097, 2098, 2099, 2100, 2101, 2102, 2103, 2104,
+	2105, 2106, 2107, 2109, 2110, 2111, 2112, 2113, 2114, 2115,
+	2116, 2117, 2118, 2119, 2120, 2120, 2121, 2122, 2123, 2124,
+	2125, 2126, 2127, 2128, 2129, 2130, 2130, 2131, 2132, 2133,
+	2134, 2135, 2136, 2136, 2137, 2138, 2139, 2140, 2141, 2141,
+	2142, 2143, 2144, 2144, 2145, 2146, 2147, 2148, 2148, 2149,
+	2150, 2150, 2151, 2152, 2153, 2153, 2154, 2155, 2155, 2156,
+	2157, 2158, 2158, 2159, 2160, 2160, 2161, 2162, 2162, 2163,
+	2163, 2164, 2165, 2165, 2166, 2167, 2167, 2168, 2168, 2169,
+	2170, 2170, 2171, 2171, 2172, 2172, 2173, 2174, 2174, 2175,
+	2175, 2176, 2176, 2177, 2177, 2178, 2179, 2179, 2180, 2180,
+	2181, 2181, 2182, 2182, 2183, 2183, 2184, 2184, 2185, 2185,
+	2186, 2186, 2186, 2187, 2187, 2188, 2188, 2189, 2189, 2190,
+	2190, 2191, 2191, 2191, 2192, 2192, 2193, 2193, 2194, 2194,
+	2194, 2195, 2195, 2196, 2196, 2196, 2197, 2197, 2198, 2198,
+	2198, 2199, 2199, 2200, 2200, 2200, 2201, 2201, 2201, 2202,
+	2202, 2203, 2203, 2203, 2204, 2204, 2204, 2205, 2205, 2205,
+	2206, 2206, 2206, 2207, 2207, 2207, 2208, 2208, 2208, 2209,
+	2209, 2209, 2210, 2210, 2210, 2210, 2211, 2211, 2211, 2212,
+	2212, 2212, 2213, 2213, 2213, 2213, 2214, 2214, 2214, 2214,
+};
+
+static const isx012_regset_t ISX012_Init_Reg[] =
+{
+//ISX012_Initial_Setting_sensor_111218_V3.08.ini//
+/////////////////////////////////////
+//AF driver setting//³»ºÎ AF driver//
+/////////////////////////////////////
+{0x66C2,0x0C,0x01},//AF_INTERNAL_LENSDRV_ADRS
+{0x66C3,0x02,0x01},//AF_INTERNAL_LENSDRV_SIZE
+{0x66C5,0x14,0x01},//AF_INTERNAL_LENSDRV_SHIFT
+{0x66C8,0x0000,0x02},//AF_INTERNAL_LENSDRV_FIXEDPTN
+{0x66CA,0x000F,0x02},
+{0x000B,0x01,0x01},//AF_EXT : AF driver start
+
+//////////////////////////////////////////
+//	ISX012_Initial_Setting.ini	//
+//////////////////////////////////////////
+// AE window add V02
+{0x6000,0x06,0x01},    // CENTER_FIXWEIGHT_00_TYPE1 :
+{0x6001,0x06,0x01},    // CENTER_FIXWEIGHT_01_TYPE1 :
+{0x6002,0x06,0x01},    // CENTER_FIXWEIGHT_02_TYPE1 :
+{0x6003,0x06,0x01},    // CENTER_FIXWEIGHT_03_TYPE1 :
+{0x6004,0x06,0x01},    // CENTER_FIXWEIGHT_04_TYPE1 :
+{0x6005,0x06,0x01},    // CENTER_FIXWEIGHT_05_TYPE1 :
+{0x6006,0x06,0x01},    // CENTER_FIXWEIGHT_06_TYPE1 :
+{0x6007,0x06,0x01},    // CENTER_FIXWEIGHT_07_TYPE1 :
+{0x6008,0x06,0x01},    // CENTER_FIXWEIGHT_08_TYPE1 :
+{0x6009,0x0C,0x01},    // CENTER_FIXWEIGHT_09_TYPE1 :
+{0x600A,0x0C,0x01},    // CENTER_FIXWEIGHT_10_TYPE1 :
+{0x600B,0x0C,0x01},    // CENTER_FIXWEIGHT_11_TYPE1 :
+{0x600C,0x10,0x01},    // CENTER_FIXWEIGHT_12_TYPE1 :
+{0x600D,0x10,0x01},    // CENTER_FIXWEIGHT_13_TYPE1 :
+{0x600E,0x10,0x01},    // CENTER_FIXWEIGHT_14_TYPE1 :
+{0x600F,0x0C,0x01},    // CENTER_FIXWEIGHT_15_TYPE1 :
+{0x6010,0x0C,0x01},    // CENTER_FIXWEIGHT_16_TYPE1 :
+{0x6011,0x0C,0x01},    // CENTER_FIXWEIGHT_17_TYPE1 :
+{0x6012,0x0C,0x01},    // CENTER_FIXWEIGHT_18_TYPE1 :
+{0x6013,0x0C,0x01},    // CENTER_FIXWEIGHT_19_TYPE1 :
+{0x6014,0x18,0x01},    // CENTER_FIXWEIGHT_20_TYPE1 :
+{0x6015,0x18,0x01},    // CENTER_FIXWEIGHT_21_TYPE1 :
+{0x6016,0x18,0x01},    // CENTER_FIXWEIGHT_22_TYPE1 :
+{0x6017,0x18,0x01},    // CENTER_FIXWEIGHT_23_TYPE1 :
+{0x6018,0x18,0x01},    // CENTER_FIXWEIGHT_24_TYPE1 :
+{0x6019,0x0C,0x01},    // CENTER_FIXWEIGHT_25_TYPE1 :
+{0x601A,0x0C,0x01},    // CENTER_FIXWEIGHT_26_TYPE1 :
+{0x601B,0x0C,0x01},    // CENTER_FIXWEIGHT_27_TYPE1 :
+{0x601C,0x18,0x01},    // CENTER_FIXWEIGHT_28_TYPE1 :
+{0x601D,0x18,0x01},    // CENTER_FIXWEIGHT_29_TYPE1 :
+{0x601E,0x1E,0x01},    // CENTER_FIXWEIGHT_30_TYPE1 :
+{0x601F,0x1E,0x01},    // CENTER_FIXWEIGHT_31_TYPE1 :
+{0x6020,0x1E,0x01},    // CENTER_FIXWEIGHT_32_TYPE1 :
+{0x6021,0x18,0x01},    // CENTER_FIXWEIGHT_33_TYPE1 :
+{0x6022,0x18,0x01},    // CENTER_FIXWEIGHT_34_TYPE1 :
+{0x6023,0x0C,0x01},    // CENTER_FIXWEIGHT_35_TYPE1 :
+{0x6024,0x0C,0x01},    // CENTER_FIXWEIGHT_36_TYPE1 :
+{0x6025,0x18,0x01},    // CENTER_FIXWEIGHT_37_TYPE1 :
+{0x6026,0x18,0x01},    // CENTER_FIXWEIGHT_38_TYPE1 :
+{0x6027,0x1E,0x01},    // CENTER_FIXWEIGHT_39_TYPE1 :
+{0x6028,0x1E,0x01},    // CENTER_FIXWEIGHT_40_TYPE1 :
+{0x6029,0x1E,0x01},    // CENTER_FIXWEIGHT_41_TYPE1 :
+{0x602A,0x18,0x01},    // CENTER_FIXWEIGHT_42_TYPE1 :
+{0x602B,0x18,0x01},    // CENTER_FIXWEIGHT_43_TYPE1 :
+{0x602C,0x0C,0x01},    // CENTER_FIXWEIGHT_44_TYPE1 :
+{0x602D,0x0C,0x01},    // CENTER_FIXWEIGHT_45_TYPE1 :
+{0x602E,0x0C,0x01},    // CENTER_FIXWEIGHT_46_TYPE1 :
+{0x602F,0x18,0x01},    // CENTER_FIXWEIGHT_47_TYPE1 :
+{0x6030,0x18,0x01},    // CENTER_FIXWEIGHT_48_TYPE1 :
+{0x6031,0x18,0x01},    // CENTER_FIXWEIGHT_49_TYPE1 :
+{0x6032,0x18,0x01},    // CENTER_FIXWEIGHT_50_TYPE1 :
+{0x6033,0x18,0x01},    // CENTER_FIXWEIGHT_51_TYPE1 :
+{0x6034,0x0C,0x01},    // CENTER_FIXWEIGHT_52_TYPE1 :
+{0x6035,0x0C,0x01},    // CENTER_FIXWEIGHT_53_TYPE1 :
+{0x6036,0x0C,0x01},    // CENTER_FIXWEIGHT_54_TYPE1 :
+{0x6037,0x0C,0x01},    // CENTER_FIXWEIGHT_55_TYPE1 :
+{0x6038,0x0C,0x01},    // CENTER_FIXWEIGHT_56_TYPE1 :
+{0x6039,0x0C,0x01},    // CENTER_FIXWEIGHT_57_TYPE1 :
+{0x603A,0x0C,0x01},    // CENTER_FIXWEIGHT_58_TYPE1 :
+{0x603B,0x0C,0x01},    // CENTER_FIXWEIGHT_59_TYPE1 :
+{0x603C,0x0C,0x01},    // CENTER_FIXWEIGHT_60_TYPE1 :
+{0x603D,0x0C,0x01},    // CENTER_FIXWEIGHT_61_TYPE1 :
+{0x603E,0x0C,0x01},    // CENTER_FIXWEIGHT_62_TYPE1 :
+
+
+//AF filter
+{0x6D14,0x0001,0x02},    // HPF_HBPF_CORSL_Y1 :
+{0x6D16,0x0001,0x02},    // HPF_HBPF_CORSL_Y2 :
+{0x6D18,0x0002,0x02},    // HPF_HBPF_CORSL_Y3 :
+{0x6D1A,0x0005,0x02},    // HPF_HBPF_CORSL_Y4 :
+
+{0x6D20,0x0004,0x02},    // HPF_HBPF_CORL_Y1 :
+{0x6D22,0x0004,0x02},    // HPF_HBPF_CORL_Y2 :
+{0x6D24,0x000F,0x02},    // HPF_HBPF_CORL_Y3 :
+{0x6D26,0x001E,0x02},    // HPF_HBPF_CORL_Y4 :
+
+{0x6D2C,0x000E,0x02},    // HPF_HBPF_CORH_Y1 :
+{0x6D2E,0x000F,0x02},    // HPF_HBPF_CORH_Y2 :
+{0x6D30,0x0022,0x02},    // HPF_HBPF_CORH_Y3 :
+{0x6D32,0x004D,0x02},    // HPF_HBPF_CORH_Y4 :
+
+{0x6D44,0x0001,0x02},    // HPF_LBPF_CORSL_Y1 :
+{0x6D46,0x0001,0x02},    // HPF_LBPF_CORSL_Y2 :
+{0x6D48,0x0002,0x02},    // HPF_LBPF_CORSL_Y3 :
+{0x6D4A,0x0004,0x02},    // HPF_LBPF_CORSL_Y4 :
+
+{0x6D50,0x03FF,0x02},    // HPF_LBPF_CORL_Y1 :
+{0x6D52,0x03FF,0x02},    // HPF_LBPF_CORL_Y2 :
+{0x6D54,0x03FF,0x02},    // HPF_LBPF_CORL_Y3 :
+{0x6D56,0x03FF,0x02},    // HPF_LBPF_CORL_Y4 :
+
+{0x6D5C,0x03FF,0x02},    // HPF_LBPF_CORH_Y1 :
+{0x6D5E,0x03FF,0x02},    // HPF_LBPF_CORH_Y2 :
+{0x6D60,0x03FF,0x02},    // HPF_LBPF_CORH_Y3 :
+{0x6D62,0x03FF,0x02},    // HPF_LBPF_CORH_Y4 :
+
+{0x6D74,0x0001,0x02},    // HPF_VHBPF_CORSL_Y1 :
+{0x6D76,0x0001,0x02},    // HPF_VHBPF_CORSL_Y2 :
+{0x6D78,0x0002,0x02},    // HPF_VHBPF_CORSL_Y3 :
+{0x6D7A,0x0005,0x02},    // HPF_VHBPF_CORSL_Y4 :
+
+{0x6D80,0x0004,0x02},    // HPF_VHBPF_CORL_Y1 :
+{0x6D82,0x0005,0x02},    // HPF_VHBPF_CORL_Y2 :
+{0x6D84,0x000C,0x02},    // HPF_VHBPF_CORL_Y3 :
+{0x6D86,0x001C,0x02},    // HPF_VHBPF_CORL_Y4 :
+
+{0x6D8C,0x000D,0x02},    // HPF_VHBPF_CORH_Y1 :
+{0x6D8E,0x0010,0x02},    // HPF_VHBPF_CORH_Y2 :
+{0x6D90,0x0026,0x02},    // HPF_VHBPF_CORH_Y3 :
+{0x6D92,0x004D,0x02},    // HPF_VHBPF_CORH_Y4 :
+
+// CAF Ãß°¡ºÎºÐ
+{0x6622,0x0004,0x02},    // AF_CAF_PARAM_WOBBLE_STEP :
+{0x6624,0x0008,0x02},    // AF_CAF_CLIMB_STEP :
+{0x6687,0x01,0x01},    // AF_CAF_CLIMB_PEAK_BACK_STEP_ENABLE :
+{0x6698,0x00,0x01},    // AF_CAF_WOBBLE_FILTER_ENABLE :
+{0x66A4,0x06,0x01},    // AF_CAF_OPD_FLAT_MOVE_ENABLE :
+{0x66B0,0x0002,0x02},    // AF_CAF_WAIT_FOR_AF_STABLE_TH :
+{0x5003,0x04,0x01},    // Z1_HOLD = 1
+//110819
+{0x6696,0x16,0x01},	//AF_CAF_WOBBLE_START_INTERVAL_COUNTER
+{0x6716,0x0000,0x02},    // CAF_LVD_WOB_HBPF_VAL1 :
+{0x6718,0x0000,0x02},    // CAF_LVD_WOB_HBPF_VAL2 :
+{0x671A,0x00C8,0x02},    // CAF_LVD_WOB_HBPF_RATE1 :
+{0x671C,0x00C8,0x02},    // CAF_LVD_WOB_HBPF_RATE2 :
+{0x671E,0x00,0x01},    // CAF_LVD_WOB_HBPF_SHIFT :
+{0x6720,0x0000,0x02},    // CAF_LVD_WOB_LBPF_VAL1 :
+{0x6722,0x0000,0x02},    // CAF_LVD_WOB_LBPF_VAL2 :
+{0x6724,0x0014,0x02},    // CAF_LVD_WOB_LBPF_RATE1 :
+{0x6726,0x0014,0x02},    // CAF_LVD_WOB_LBPF_RATE2 :
+{0x6728,0x00,0x01},    // CAF_LVD_WOB_LBPF_SHIFT :
+{0x672A,0x0000,0x02},    // CAF_LVD_CLMP_HBPF_VAL1 :
+{0x672C,0x0000,0x02},    // CAF_LVD_CLMP_HBPF_VAL2 :
+{0x672E,0x012C,0x02},    // CAF_LVD_CLMP_HBPF_RATE1 :
+{0x6730,0x012C,0x02},    // CAF_LVD_CLMP_HBPF_RATE2 :
+{0x6732,0x00,0x01},    // CAF_LVD_CLMP_HBPF_SHIFT :
+{0x6734,0x0000,0x02},    // CAF_LVD_CLMP_LBPF_VAL1 :
+{0x6736,0x0000,0x02},    // CAF_LVD_CLMP_LBPF_VAL2 :
+{0x6738,0x0046,0x02},    // CAF_LVD_CLMP_LBPF_RATE1 :
+{0x673A,0x0046,0x02},    // CAF_LVD_CLMP_LBPF_RATE2 :
+{0x673C,0x00,0x01},    // CAF_LVD_CLMP_LBPF_SHIFT :
+{0x661E,0x00C8,0x02},    //AF_CAF_FAR_POSITION
+{0x6620,0x02BC,0x02},    //AF_CAF_NEAR_POSITION
+
+//Ãß°¡¼ÂÆúκРSAFºÎºÐ
+{0x00B2,0x02,0x01},    // AFMODE_MONI : manual AF mode
+{0x028E,0x00,0x01},    // AF_SN1_2 :
+{0x028F,0x00,0x01},    // AF_SN3_4 :
+{0x0290,0x00,0x01},    // AF_SN5_6 :
+{0x0291,0x00,0x01},    // AF_SN7_8 :
+{0x0292,0x00,0x01},    // AF_SN9_10 :
+{0x0293,0x00,0x01},    // AF_SN11_12 :
+{0x6604,0x00,0x01},    // AF_SEARCH_DIR :
+{0x6616,0x01,0x01},    // AF_DIRECTBACK_F :On=1
+{0x661B,0x03,0x01},    // AF_OPDDATA_SAVE :
+{0x661C,0x00,0x01},    // AF_MONOTONY_POS :
+{0x663E,0x01,0x01},    // AF_SEARCH_SECOND_DIR :
+{0x663F,0x01,0x01},    // AF_DIRECTBACK_SECOND_F :
+{0x6674,0x00,0x01},    // AF_MONICHG_MOVE_F : AF off½Ã zero positionÀ¸·Î °¥Áö(01) ÇöÀ§Ä¡¿¡ ÀÖÀ»Áö(00) Á¤ÇÔ
+{0x6675,0x01,0x01},    // CAP_AF_CANCEL_F : 1·Î ¼³Á¤½Ã capture¸ðµå¿¡¼­ AFÀÚµ¿ ĵ½½
+{0x6676,0x02,0x01},    // AF_SAxF_MODE :
+{0x669E,0x02,0x01},    // AF_SECOND_WND_CHK :
+{0x6600,0x00C8,0x02},    // AF_SEARCH_AREA_LOW :
+{0x6602,0x02BC,0x02},    // AF_SEARCH_AREA_HIGH :
+{0x6640,0x02,0x01},    // AF_DROPN_ON_PEAK_DETECT_SECOND :
+{0x6641,0x02,0x01},    // AF_UPN_ON_PEAK_DETECT_SECOND :
+{0x6642,0x02,0x01},        //AF_DROPRATE_ON_DETECT_SECOND_HBPF
+{0x6643,0x02,0x01},        //AF_DROPRATE_ON_DETECT_SECOND_LBPF
+{0x6644,0x14,0x01},    // AF_UPRATE_ON_PEAK_DETECT_HBPF_SECOND :
+{0x6646,0x08,0x01},    // AF_OPD_WEIGHT_TH :
+{0x664A,0x04,0x01},    // AF_DROPN_ON_PEAK_DETECT :
+{0x664B,0x02,0x01},    // AF_UPN_ON_PEAK_DETECT :
+{0x664C,0xFF,0x01},    // AF_UPRATE_ON_PEAK_DETECT_HBPF :
+{0x665A,0x00C8,0x02},    // AF_LENSPOS_ON_AFNG :
+{0x665C,0x0018,0x02},    // AF_DRV_AMOUNT_TONEAR_F :
+{0x665E,0x0004,0x02},    // AF_DRV_AMOUNT_TONEAR_S :
+{0x6660,0x0018,0x02},    // AF_DRV_AMOUNT_TOFAR_F :
+{0x6662,0x0004,0x02},    // AF_DRV_AMOUNT_TOFAR_S :
+{0x6666,0x00C8,0x02},    // AF_AREA_LOW_TYPE1 :
+{0x6668,0x02BC,0x02},    // AF_AREA_HIGH_TYPE1 :
+{0x669A,0x01F4,0x02},    // AF_OPD_MONOTONYUP_HBPF_TH :
+{0x66E4,0x50,0x01},    // AF_TH_1STDEPEND_HBPF_RATE :
+{0x66EE,0x03E8,0x02},    // AF_LVD_HBPF_VAL1_1ST :
+{0x66F0,0x4E20,0x02},    // AF_LVD_HBPF_VAL2_1ST :
+{0x66F2,0x004C,0x02},    // AF_LVD_HBPF_RATE1_1ST :
+{0x66F4,0x0019,0x02},    // AF_LVD_HBPF_RATE2_1ST :
+{0x66F6,0x00,0x01},    // AF_LVD_HBPF_SHIFT_1ST :
+{0x6702,0x03E8,0x02},    // AF_LVD_HBPF_VAL1_2ND :
+{0x6704,0x4E20,0x02},    // AF_LVD_HBPF_VAL2_2ND :
+{0x6706,0x0003,0x02},    // AF_LVD_HBPF_RATE1_2ND :
+{0x6708,0x0003,0x02},    // AF_LVD_HBPF_RATE2_2ND :
+{0x670A,0x00,0x01},    // AF_LVD_HBPF_SHIFT_2ND :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+//chooys add
+{0x6677,0x00,0x01}, /* AF_SEND_PARTITION : Use=1 */
+{0x6678,0x20,0x01},    // AF_SENDNUM_ALL
+{0x6679,0x01,0x01},    // AF_SENDNUM_UP
+{0x667A,0x01,0x01},    // AF_SENDNUM_DOWN
+{0x667C,0x0002,0x02},    // AF_SENDAMOUNT_ADDLIMIT
+{0x667E,0x0020,0x02},     //AF_SENDLINE
+
+// AF opd_TH
+{0x660E,0x5A,0x01},    // AF_HBPF_PEAK_OPD_TH_MIN
+{0x6610,0x5A,0x01},    // AF_HBPF_PEAK_OPD_TH_MAX
+
+//AF opd window setting
+{0x6A30,0x044E,0x02},    // AF_OPD0_HDELAY :
+{0x6A32,0x02E5,0x02},    // AF_OPD0_VDELAY :
+{0x6A34,0x01D8,0x02},    // AF_OPD0_HVALID :
+{0x6A36,0x01D8,0x02},    // AF_OPD0_VVALID :
+{0x6A38,0x0412,0x02},    // AF_OPD1_HDELAY :
+{0x6A3A,0x02A9,0x02},    // AF_OPD1_VDELAY :
+{0x6A3C,0x0251,0x02},    // AF_OPD1_HVALID :
+{0x6A3E,0x0251,0x02},    // AF_OPD1_VVALID :
+{0x6A40,0x04B4,0x02},    // AF_OPD2_HDELAY :
+{0x6A42,0x0114,0x02},    // AF_OPD2_VDELAY :
+{0x6A44,0x0118,0x02},    // AF_OPD2_HVALID :
+{0x6A46,0x0118,0x02},    // AF_OPD2_VVALID :
+{0x6A48,0x0469,0x02},    // AF_OPD3_HDELAY :
+{0x6A4A,0x00C9,0x02},    // AF_OPD3_VDELAY :
+{0x6A4C,0x01AE,0x02},    // AF_OPD3_HVALID :
+{0x6A4E,0x01AE,0x02},    // AF_OPD3_VVALID :
+{0x6A50,0x048A,0x02},    // AF_OPD4_HDELAY :
+{0x6A52,0x0321,0x02},    // AF_OPD4_VDELAY :
+{0x6A54,0x015F,0x02},    // AF_OPD4_HVALID :
+{0x6A56,0x015F,0x02},    // AF_OPD4_VVALID :
+{0x6A58,0x04BA,0x02},    // AF_OPD5_HDELAY :
+{0x6A5A,0x02E4,0x02},    // AF_OPD5_VDELAY :
+{0x6A5C,0x00F0,0x02},    // AF_OPD5_HVALID :
+{0x6A5E,0x0276,0x02},    // AF_OPD5_VVALID :
+{0x6A60,0x04B4,0x02},    // AF_OPD6_HDELAY :
+{0x6A62,0x0579,0x02},    // AF_OPD6_VDELAY :
+{0x6A64,0x0118,0x02},    // AF_OPD6_HVALID :
+{0x6A66,0x0118,0x02},    // AF_OPD6_VVALID :
+{0x6A68,0x0469,0x02},    // AF_OPD7_HDELAY :
+{0x6A6A,0x052C,0x02},    // AF_OPD7_VDELAY :
+{0x6A6C,0x01AE,0x02},    // AF_OPD7_HVALID :
+{0x6A6E,0x01AE,0x02},    // AF_OPD7_VVALID :
+{0x6A70,0x04C6,0x02},    // AF_OPD8_HDELAY :
+{0x6A72,0x0493,0x02},    // AF_OPD8_VDELAY :
+{0x6A74,0x00E6,0x02},    // AF_OPD8_HVALID :
+{0x6A76,0x00E6,0x02},    // AF_OPD8_VVALID :
+{0x6A78,0x048A,0x02},    // AF_OPD9_HDELAY :
+{0x6A7A,0x0457,0x02},    // AF_OPD9_VDELAY :
+{0x6A7C,0x015F,0x02},    // AF_OPD9_HVALID :
+{0x6A7E,0x015F,0x02},    // AF_OPD9_VVALID :
+{0x6A80,0x05,0x01},    // AF_OPD1A_WEIGHT :
+{0x6A81,0x04,0x01},    // AF_OPD1B_WEIGHT :
+{0x6A82,0x03,0x01},    // AF_OPD2A_WEIGHT :
+{0x6A83,0x02,0x01},    // AF_OPD2B_WEIGHT :
+{0x6A84,0x08,0x01},    // AF_OPD3A_WEIGHT :
+{0x6A85,0x07,0x01},    // AF_OPD3B_WEIGHT :
+{0x6A86,0x03,0x01},    // AF_OPD4A_WEIGHT :
+{0x6A87,0x02,0x01},    // AF_OPD4B_WEIGHT :
+{0x6A88,0x00,0x01},    // AF_OPD5A_WEIGHT :
+{0x6A89,0x00,0x01},    // AF_OPD5B_WEIGHT :
+
+
+//lee haknoh add
+{0x661C,0x00,0x01},
+//S,66BE,0F,8,    //AF_JUDGE_CONF
+//S,669A,01F4,16,    //AF_OPD_MONOTONYUP_HBPF_TH
+//S,669C,03E8,16,    //AF_OPD_MONOTONYUP_LBPF_TH
+{0x673D,0x01,0x01},    //AF_MANUAL_MOVE_TYTPE : manual mode½Ã AF_MANUAL_POS·Î À̵¿ÇÒÁö ¼³Á¤
+{0x6648,0x00C8,0x02},    //AF_MANUAL_POS
+{0x66E0,0x00C8,0x02},    //AF_POS_INF_SET
+{0x66E2,0x02BC,0x02},    //AF_POS_MACRO_SET
+{0x00B2,0x02,0x01}, //AFMODE_MONI : Manual AF mode
+
+
+//Ãß°¡ ¼¼Æà ºÎºÐ
+{0x00F7,0x52,0x01},    // INIT_QLTY0 : Standard 82
+{0x00F8,0x59,0x01},    // INIT_QLTY1 : Fine 89
+{0x00F9,0x5F,0x01},    // INIT_QLTY2 : SuperFine 95
+
+//minimum shutter speed
+{0x6800,0x03,0x01},    //SHTMINLINE
+
+/////// Normal AE Line //////
+// normal capture AE line
+{0x0326,0x21,0x01},    // SHTCTRLTIME1_TYPE1 :
+{0x0327,0x19,0x01},    // AGCGAIN1_TYPE1 :
+{0x0328,0x52,0x01},    // SHTCTRLTIME2_TYPE1 :
+{0x0329,0x23,0x01},    // AGCGAIN2_TYPE1 :
+{0x032A,0x3E,0x01},    // SHTCTRLTIME3_TYPE1 :
+{0x032B,0x42,0x01},    // AGCGAIN3_TYPE1 :
+
+// normal preview AE line
+{0x032C,0x7C,0x01},    // SHTCTRLTIME1_TYPE2
+{0x032D,0x3D,0x01},    // AGCGAIN1_TYPE2
+{0x032E,0x7C,0x01},    // SHTCTRLTIME2_TYPE2
+{0x032F,0x3D,0x01},    // AGCGAIN2_TYPE2
+{0x0330,0x3E,0x01},    // SHTCTRLTIME3_TYPE2
+{0x0331,0x42,0x01},    // AGCGAIN3_TYPE2
+
+// flash ae line
+{0x0332,0x42,0x01},    // SHTCTRLTIME1_TYPE3 :
+{0x0333,0x3C,0x01},    // AGCGAIN1_TYPE3 :
+{0x0334,0x42,0x01},    // SHTCTRLTIME2_TYPE3 :
+{0x0335,0x3C,0x01},    // AGCGAIN2_TYPE3 :
+{0x0336,0x21,0x01},    // SHTCTRLTIME3_TYPE3 :
+{0x0337,0x3C,0x01},    // AGCGAIN3_TYPE3 :
+
+//sports ae line
+{0x0338,0x01,0x01},    // SHTCTRLTIME1_TYPE4
+{0x0339,0x14,0x01},    // AGCGAIN1_TYPE4
+{0x033A,0x21,0x01},    // SHTCTRLTIME2_TYPE4
+{0x033B,0x19,0x01},    // AGCGAIN2_TYPE4
+{0x033C,0x3E,0x01},    // SHTCTRLTIME3_TYPE4
+{0x033D,0x3D,0x01},    // AGCGAIN3_TYPE4
+
+//night mode AF ae line
+{0x033E,0xFF,0x01},    // SHTCTRLTIME1_TYPE5 :
+{0x033F,0x00,0x01},    // AGCGAIN1_TYPE5 :
+{0x0340,0xFF,0x01},    // SHTCTRLTIME2_TYPE5 :
+{0x0341,0x00,0x01},    // AGCGAIN2_TYPE5 :
+{0x0342,0xA6,0x01},    // SHTCTRLTIME3_TYPE5 :
+{0x0343,0x49,0x01},    // AGCGAIN3_TYPE5 :
+
+//night mode capture ae line
+{0x0344,0xFF,0x01},    // SHTCTRLTIME1_TYPE6 :
+{0x0345,0x00,0x01},    // AGCGAIN1_TYPE6 :
+{0x0346,0xFF,0x01},    // SHTCTRLTIME2_TYPE6 :
+{0x0347,0x00,0x01},    // AGCGAIN2_TYPE6 :
+{0x0348,0xFA,0x01},    // SHTCTRLTIME3_TYPE6 :
+{0x0349,0x3D,0x01},    // AGCGAIN3_TYPE6 :
+
+// fire mode line
+{0x0356,0x01,0x01},    // SHTCTRLTIME1_TYPE9 :
+{0x0357,0x04,0x01},    // AGCGAIN1_TYPE9 :
+{0x0358,0x01,0x01},    // SHTCTRLTIME2_TYPE9 :
+{0x0359,0x04,0x01},    // AGCGAIN2_TYPE9 :
+{0x035A,0xF8,0x01},    // SHTCTRLTIME3_TYPE9 :
+{0x035B,0x04,0x01},    // AGCGAIN3_TYPE9 :
+
+// fire mode AF line
+{0x035C,0x01,0x01},    // SHTCTRLTIME1_TYPE10 :
+{0x035D,0x04,0x01},    // AGCGAIN1_TYPE10 :
+{0x035E,0x01,0x01},    // SHTCTRLTIME2_TYPE10 :
+{0x035F,0x04,0x01},    // AGCGAIN2_TYPE10 :
+{0x0360,0x21,0x01},    // SHTCTRLTIME3_TYPE10 :
+{0x0361,0x3E,0x01},    // AGCGAIN3_TYPE10 :
+
+
+//AE ref tunning
+{0x5E8A,0x02,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x02,0x01},    // EVREF_GAIN_B :
+{0x5E8C,0xFD,0x01},    // EVREF_GAIN_C :
+{0x5E8D,0xFD,0x01},    // EVREF_GAIN_D :
+{0x5E8E,0xFD,0x01},    // EVREF_GAIN_E :
+{0x5E8F,0x90,0x01},    // EVREF_TH_A :
+{0x5E90,0x94,0x01},    // EVREF_TH_B :
+{0x5E91,0xA5,0x01},    // EVREF_TH_C :
+{0x5E92,0xC0,0x01},    // EVREF_TH_D :
+{0x5E93,0xD5,0x01},    // EVREF_TH_E :
+
+
+//gamma Ilumi
+{0x9211,0x58,0x01},    // GAIN_TH_A_TYPE3 :
+{0x9212,0x63,0x01},    // GAIN_TH_B_TYPE3 :
+{0x9213,0x9F,0x01},    // GAIN_TH_C_TYPE3 :
+
+{0x984E,0x0A,0x01},    // GAMMA0_0CLIP_A :
+{0x984F,0x0A,0x01},    // GAMMA0_0CLIP_B :
+{0x9850,0x05,0x01},    // GAMMA0_0CLIP_C :
+{0x9851,0x1E,0x01},    // GAMMA0_SLOPE_A :
+{0x9852,0x1E,0x01},    // GAMMA0_SLOPE_B :
+{0x9853,0x1E,0x01},    // GAMMA0_SLOPE_C :
+{0x9854,0x0A,0x01},    // GAMMA1_0CLIP_A :
+{0x9855,0x0F,0x01},    // GAMMA1_0CLIP_B :
+{0x9856,0x0F,0x01},    // GAMMA1_0CLIP_C :
+{0x9857,0x32,0x01},    // GAMMA1_SLOPE_A :
+{0x9858,0x1E,0x01},    // GAMMA1_SLOPE_B :
+{0x9859,0x1E,0x01},    // GAMMA1_SLOPE_C :
+
+
+//Gammma Table 0
+{0x7000,0x0000,0x02},    // G0_KNOT_G0 :
+{0x7002,0x0015,0x02},    // G0_KNOT_G1 :
+{0x7004,0x002C,0x02},    // G0_KNOT_G2 :
+{0x7006,0x0041,0x02},    // G0_KNOT_G3 :
+{0x7008,0x004D,0x02},    // G0_KNOT_G4 :
+{0x700A,0x005B,0x02},    // G0_KNOT_G5 :
+{0x700C,0x0060,0x02},    // G0_KNOT_G6 :
+{0x700E,0x0068,0x02},    // G0_KNOT_G7 :
+{0x7010,0x006F,0x02},    // G0_KNOT_G8 :
+{0x7012,0x0078,0x02},    // G0_KNOT_G9 :
+{0x7014,0x0057,0x02},    // G0_KNOT_G10 :
+{0x7016,0x0090,0x02},    // G0_KNOT_G11 :
+{0x7018,0x00BB,0x02},    // G0_KNOT_G12 :
+{0x701A,0x00D6,0x02},    // G0_KNOT_G13 :
+{0x701C,0x00E5,0x02},    // G0_KNOT_G14 :
+{0x701E,0x00F0,0x02},    // G0_KNOT_G15 :
+{0x7020,0x00F9,0x02},    // G0_KNOT_G16 :
+{0x7022,0x0103,0x02},    // G0_KNOT_G17 :
+{0x7024,0x010C,0x02},    // G0_KNOT_G18 :
+{0x7026,0x00,0x01},    // G0_KNOT_R0_OFFSET :
+{0x7027,0x00,0x01},    // G0_KNOT_R2_OFFSET :
+{0x7028,0x00,0x01},    // G0_KNOT_R4_OFFSET :
+{0x7029,0x00,0x01},    // G0_KNOT_R6_OFFSET :
+{0x702A,0x00,0x01},    // G0_KNOT_R8_OFFSET :
+{0x702B,0x00,0x01},    // G0_KNOT_R10_OFFSET :
+{0x702C,0x00,0x01},    // G0_KNOT_R12_OFFSET :
+{0x702D,0x00,0x01},    // G0_KNOT_R14_OFFSET :
+{0x702E,0x00,0x01},    // G0_KNOT_R16_OFFSET :
+{0x702F,0x00,0x01},    // G0_KNOT_R18_OFFSET :
+{0x7030,0x00,0x01},    // G0_KNOT_B0_OFFSET :
+{0x7031,0x00,0x01},    // G0_KNOT_B2_OFFSET :
+{0x7032,0x00,0x01},    // G0_KNOT_B4_OFFSET :
+{0x7033,0x00,0x01},    // G0_KNOT_B6_OFFSET :
+{0x7034,0x00,0x01},    // G0_KNOT_B8_OFFSET :
+{0x7035,0x00,0x01},    // G0_KNOT_B10_OFFSET :
+{0x7036,0x00,0x01},    // G0_KNOT_B12_OFFSET :
+{0x7037,0x00,0x01},    // G0_KNOT_B14_OFFSET :
+{0x7038,0x00,0x01},    // G0_KNOT_B16_OFFSET :
+{0x7039,0x00,0x01},    // G0_KNOT_B18_OFFSET :
+{0x703A,0x0611,0x02},    // G0_LOWGM_ON_R :
+{0x703C,0x1E0A,0x02},    // G0_0CLIP_R :
+{0x703E,0x0611,0x02},    // G0_LOWGM_ON_G :
+{0x7040,0x1E0A,0x02},    // G0_0CLIP_G :
+{0x7042,0x0611,0x02},    // G0_LOWGM_ON_B :
+{0x7044,0x1E0A,0x02},    // G0_0CLIP_B :
+{0x7046,0x9C,0x01},    // G0_KNOT_GAINCTRL_TH_L :
+{0x7047,0xA1,0x01},    // G0_KNOT_GAINCTRL_TH_H :
+{0x7048,0x0000,0x02},    // G0_KNOT_L_G0 :
+{0x704A,0x0007,0x02},    // G0_KNOT_L_G1 :
+{0x704C,0x0016,0x02},    // G0_KNOT_L_G2 :
+{0x704E,0x002A,0x02},    // G0_KNOT_L_G3 :
+{0x7050,0x0039,0x02},    // G0_KNOT_L_G4 :
+{0x7052,0x004A,0x02},    // G0_KNOT_L_G5 :
+{0x7054,0x0051,0x02},    // G0_KNOT_L_G6 :
+{0x7056,0x005D,0x02},    // G0_KNOT_L_G7 :
+{0x7058,0x0065,0x02},    // G0_KNOT_L_G8 :
+{0x705A,0x006C,0x02},    // G0_KNOT_L_G9 :
+{0x705C,0x004E,0x02},    // G0_KNOT_L_G10 :
+{0x705E,0x0083,0x02},    // G0_KNOT_L_G11 :
+{0x7060,0x00AA,0x02},    // G0_KNOT_L_G12 :
+{0x7062,0x00C8,0x02},    // G0_KNOT_L_G13 :
+{0x7064,0x00E1,0x02},    // G0_KNOT_L_G14 :
+{0x7066,0x00F5,0x02},    // G0_KNOT_L_G15 :
+{0x7068,0x0100,0x02},    // G0_KNOT_L_G16 :
+{0x706A,0x0106,0x02},    // G0_KNOT_L_G17 :
+{0x706C,0x010C,0x02},    // G0_KNOT_L_G18 :
+
+//Gammma Table 1
+{0x7200,0x0000,0x02},    // G1_KNOT_G0 :
+{0x7202,0x0008,0x02},    // G1_KNOT_G1 :
+{0x7204,0x0020,0x02},    // G1_KNOT_G2 :
+{0x7206,0x0037,0x02},    // G1_KNOT_G3 :
+{0x7208,0x004D,0x02},    // G1_KNOT_G4 :
+{0x720A,0x0064,0x02},    // G1_KNOT_G5 :
+{0x720C,0x006E,0x02},    // G1_KNOT_G6 :
+{0x720E,0x0072,0x02},    // G1_KNOT_G7 :
+{0x7210,0x007A,0x02},    // G1_KNOT_G8 :
+{0x7212,0x007E,0x02},    // G1_KNOT_G9 :
+{0x7214,0x0064,0x02},    // G1_KNOT_G10 :
+{0x7216,0x0093,0x02},    // G1_KNOT_G11 :
+{0x7218,0x00B7,0x02},    // G1_KNOT_G12 :
+{0x721A,0x00CD,0x02},    // G1_KNOT_G13 :
+{0x721C,0x00DD,0x02},    // G1_KNOT_G14 :
+{0x721E,0x00ED,0x02},    // G1_KNOT_G15 :
+{0x7220,0x00F9,0x02},    // G1_KNOT_G16 :
+{0x7222,0x0102,0x02},    // G1_KNOT_G17 :
+{0x7224,0x0101,0x02},    // G1_KNOT_G18 :
+{0x7226,0x00,0x01},    // G1_KNOT_R0_OFFSET :
+{0x7227,0x00,0x01},    // G1_KNOT_R2_OFFSET :
+{0x7228,0x00,0x01},    // G1_KNOT_R4_OFFSET :
+{0x7229,0x00,0x01},    // G1_KNOT_R6_OFFSET :
+{0x722A,0x00,0x01},    // G1_KNOT_R8_OFFSET :
+{0x722B,0x00,0x01},    // G1_KNOT_R10_OFFSET :
+{0x722C,0x00,0x01},    // G1_KNOT_R12_OFFSET :
+{0x722D,0x00,0x01},    // G1_KNOT_R14_OFFSET :
+{0x722E,0x00,0x01},    // G1_KNOT_R16_OFFSET :
+{0x722F,0x00,0x01},    // G1_KNOT_R18_OFFSET :
+{0x7230,0x00,0x01},    // G1_KNOT_B0_OFFSET :
+{0x7231,0x00,0x01},    // G1_KNOT_B2_OFFSET :
+{0x7232,0x00,0x01},    // G1_KNOT_B4_OFFSET :
+{0x7233,0x00,0x01},    // G1_KNOT_B6_OFFSET :
+{0x7234,0x00,0x01},    // G1_KNOT_B8_OFFSET :
+{0x7235,0x00,0x01},    // G1_KNOT_B10_OFFSET :
+{0x7236,0x00,0x01},    // G1_KNOT_B12_OFFSET :
+{0x7237,0x00,0x01},    // G1_KNOT_B14_OFFSET :
+{0x7238,0x00,0x01},    // G1_KNOT_B16_OFFSET :
+{0x7239,0x00,0x01},    // G1_KNOT_B18_OFFSET :
+{0x723A,0x0321,0x02},    // G1_LOWGM_ON_R :
+{0x723C,0x0C00,0x02},    // G1_0CLIP_R :
+{0x723E,0x0321,0x02},    // G1_LOWGM_ON_G :
+{0x7240,0x0C00,0x02},    // G1_0CLIP_G :
+{0x7242,0x0321,0x02},    // G1_LOWGM_ON_B :
+{0x7244,0x0C00,0x02},    // G1_0CLIP_B :
+
+
+//Gammma Table 2
+{0x7400,0x0000,0x02},    // G2_KNOT_G0 :
+{0x7402,0x000A,0x02},    // G2_KNOT_G1 :
+{0x7404,0x0023,0x02},    // G2_KNOT_G2 :
+{0x7406,0x0038,0x02},    // G2_KNOT_G3 :
+{0x7408,0x003F,0x02},    // G2_KNOT_G4 :
+{0x740A,0x0047,0x02},    // G2_KNOT_G5 :
+{0x740C,0x004F,0x02},    // G2_KNOT_G6 :
+{0x740E,0x0058,0x02},    // G2_KNOT_G7 :
+{0x7410,0x005F,0x02},    // G2_KNOT_G8 :
+{0x7412,0x0068,0x02},    // G2_KNOT_G9 :
+{0x7414,0x0044,0x02},    // G2_KNOT_G10 :
+{0x7416,0x0083,0x02},    // G2_KNOT_G11 :
+{0x7418,0x00B6,0x02},    // G2_KNOT_G12 :
+{0x741A,0x00D1,0x02},    // G2_KNOT_G13 :
+{0x741C,0x00E4,0x02},    // G2_KNOT_G14 :
+{0x741E,0x00F0,0x02},    // G2_KNOT_G15 :
+{0x7420,0x00F9,0x02},    // G2_KNOT_G16 :
+{0x7422,0x0103,0x02},    // G2_KNOT_G17 :
+{0x7424,0x010C,0x02},    // G2_KNOT_G18 :
+{0x7426,0x00,0x01},    // G2_KNOT_R0_OFFSET :
+{0x7427,0x00,0x01},    // G2_KNOT_R2_OFFSET :
+{0x7428,0x00,0x01},    // G2_KNOT_R4_OFFSET :
+{0x7429,0x00,0x01},    // G2_KNOT_R6_OFFSET :
+{0x742A,0x00,0x01},    // G2_KNOT_R8_OFFSET :
+{0x742B,0x00,0x01},    // G2_KNOT_R10_OFFSET :
+{0x742C,0x00,0x01},    // G2_KNOT_R12_OFFSET :
+{0x742D,0x00,0x01},    // G2_KNOT_R14_OFFSET :
+{0x742E,0x00,0x01},    // G2_KNOT_R16_OFFSET :
+{0x742F,0x00,0x01},    // G2_KNOT_R18_OFFSET :
+{0x7430,0x00,0x01},    // G2_KNOT_B0_OFFSET :
+{0x7431,0x00,0x01},    // G2_KNOT_B2_OFFSET :
+{0x7432,0x00,0x01},    // G2_KNOT_B4_OFFSET :
+{0x7433,0x00,0x01},    // G2_KNOT_B6_OFFSET :
+{0x7434,0x00,0x01},    // G2_KNOT_B8_OFFSET :
+{0x7435,0x00,0x01},    // G2_KNOT_B10_OFFSET :
+{0x7436,0x00,0x01},    // G2_KNOT_B12_OFFSET :
+{0x7437,0x00,0x01},    // G2_KNOT_B14_OFFSET :
+{0x7438,0x00,0x01},    // G2_KNOT_B16_OFFSET :
+{0x7439,0x00,0x01},    // G2_KNOT_B18_OFFSET :
+{0x743A,0x0611,0x02},    // G2_LOWGM_ON_R :
+{0x743C,0x1E0A,0x02},    // G2_0CLIP_R :
+{0x743E,0x0611,0x02},    // G2_LOWGM_ON_G :
+{0x7440,0x1E0A,0x02},    // G2_0CLIP_G :
+{0x7442,0x0611,0x02},    // G2_LOWGM_ON_B :
+{0x7444,0x1E0A,0x02},    // G2_0CLIP_B :
+
+
+//AWB tuning
+{0x64A4,0xFF,0x01},    // OUTFRM_LEFT00 :
+{0x64A5,0xFF,0x01},    // OUTFRM_LEFT01 :
+{0x64A6,0xFF,0x01},    // OUTFRM_LEFT02 :
+{0x64A7,0xFF,0x01},    // OUTFRM_LEFT03 :
+{0x64A8,0xFF,0x01},    // OUTFRM_LEFT04 :
+{0x64A9,0xFF,0x01},    // OUTFRM_LEFT05 :
+{0x64AA,0xFF,0x01},    // OUTFRM_LEFT06 :
+{0x64AB,0xFF,0x01},    // OUTFRM_LEFT07 :
+{0x64AC,0xFF,0x01},    // OUTFRM_LEFT08 :
+{0x64AD,0xFD,0x01},    // OUTFRM_LEFT09 :
+{0x64AE,0xCB,0x01},    // OUTFRM_LEFT10 :
+{0x64AF,0xA9,0x01},    // OUTFRM_LEFT11 :
+{0x64B0,0x90,0x01},    // OUTFRM_LEFT12 :
+{0x64B1,0x7D,0x01},    // OUTFRM_LEFT13 :
+{0x64B2,0x70,0x01},    // OUTFRM_LEFT14 :
+{0x64B3,0x65,0x01},    // OUTFRM_LEFT15 :
+{0x64B4,0x5C,0x01},    // OUTFRM_LEFT16 :
+{0x64B5,0x55,0x01},    // OUTFRM_LEFT17 :
+{0x64B6,0x4F,0x01},    // OUTFRM_LEFT18 :
+{0x64B7,0x32,0x01},    // OUTFRM_LEFT19 :
+{0x64B8,0x4D,0x01},    // OUTFRM_LEFT20 :
+{0x64B9,0x40,0x01},    // OUTFRM_LEFT21 :
+{0x64BA,0x2D,0x01},    // OUTFRM_LEFT22 :
+{0x64BB,0x2B,0x01},    // OUTFRM_LEFT23 :
+{0x64BC,0x29,0x01},    // OUTFRM_LEFT24 :
+{0x64BD,0x27,0x01},    // OUTFRM_LEFT25 :
+{0x64BE,0x25,0x01},    // OUTFRM_LEFT26 :
+{0x64BF,0x23,0x01},    // OUTFRM_LEFT27 :
+{0x64C0,0x21,0x01},    // OUTFRM_LEFT28 :
+{0x64C1,0x1F,0x01},    // OUTFRM_LEFT29 :
+{0x64C2,0x1D,0x01},    // OUTFRM_LEFT30 :
+{0x64C3,0x1B,0x01},    // OUTFRM_LEFT31 :
+{0x64C4,0x1A,0x01},    // OUTFRM_LEFT32 :
+{0x64C5,0x1A,0x01},    // OUTFRM_LEFT33 :
+{0x64C6,0x1A,0x01},    // OUTFRM_LEFT34 :
+{0x64C7,0x28,0x01},    // OUTFRM_LEFT35 :
+{0x64C8,0x27,0x01},    // OUTFRM_LEFT36 :
+{0x64C9,0x26,0x01},    // OUTFRM_LEFT37 :
+{0x64CA,0xFF,0x01},    // OUTFRM_RIGHT00 :
+{0x64CB,0xFF,0x01},    // OUTFRM_RIGHT01 :
+{0x64CC,0xFF,0x01},    // OUTFRM_RIGHT02 :
+{0x64CD,0xFF,0x01},    // OUTFRM_RIGHT03 :
+{0x64CE,0xFF,0x01},    // OUTFRM_RIGHT04 :
+{0x64CF,0xFF,0x01},    // OUTFRM_RIGHT05 :
+{0x64D0,0xFF,0x01},    // OUTFRM_RIGHT06 :
+{0x64D1,0xFF,0x01},    // OUTFRM_RIGHT07 :
+{0x64D2,0xFF,0x01},    // OUTFRM_RIGHT08 :
+{0x64D3,0xFF,0x01},    // OUTFRM_RIGHT09 :
+{0x64D4,0xD3,0x01},    // OUTFRM_RIGHT10 :
+{0x64D5,0xB1,0x01},    // OUTFRM_RIGHT11 :
+{0x64D6,0x98,0x01},    // OUTFRM_RIGHT12 :
+{0x64D7,0x85,0x01},    // OUTFRM_RIGHT13 :
+{0x64D8,0x78,0x01},    // OUTFRM_RIGHT14 :
+{0x64D9,0x6D,0x01},    // OUTFRM_RIGHT15 :
+{0x64DA,0x64,0x01},    // OUTFRM_RIGHT16 :
+{0x64DB,0x5D,0x01},    // OUTFRM_RIGHT17 :
+{0x64DC,0x57,0x01},    // OUTFRM_RIGHT18 :
+{0x64DD,0x63,0x01},    // OUTFRM_RIGHT19 :
+{0x64DE,0x5E,0x01},    // OUTFRM_RIGHT20 :
+{0x64DF,0x5A,0x01},    // OUTFRM_RIGHT21 :
+{0x64E0,0x56,0x01},    // OUTFRM_RIGHT22 :
+{0x64E1,0x52,0x01},    // OUTFRM_RIGHT23 :
+{0x64E2,0x50,0x01},    // OUTFRM_RIGHT24 :
+{0x64E3,0x4E,0x01},    // OUTFRM_RIGHT25 :
+{0x64E4,0x4C,0x01},    // OUTFRM_RIGHT26 :
+{0x64E5,0x4A,0x01},    // OUTFRM_RIGHT27 :
+{0x64E6,0x48,0x01},    // OUTFRM_RIGHT28 :
+{0x64E7,0x46,0x01},    // OUTFRM_RIGHT29 :
+{0x64E8,0x44,0x01},    // OUTFRM_RIGHT30 :
+{0x64E9,0x43,0x01},    // OUTFRM_RIGHT31 :
+{0x64EA,0x42,0x01},    // OUTFRM_RIGHT32 :
+{0x64EB,0x42,0x01},    // OUTFRM_RIGHT33 :
+{0x64EC,0x42,0x01},    // OUTFRM_RIGHT34 :
+{0x64ED,0x30,0x01},    // OUTFRM_RIGHT35 :
+{0x64EE,0x2F,0x01},    // OUTFRM_RIGHT36 :
+{0x64EF,0x2E,0x01},    // OUTFRM_RIGHT37 :
+{0x64F0,0x2163,0x02},    // OUTFRM_TOP :
+{0x64F2,0x1400,0x02},    // OUTFRM_BOTM :
+{0x64F4,0x19,0x01},    // OUTFRM_FLTOP :
+{0x64F5,0x14,0x01},    // OUTFRM_FLBOTM :
+{0x64F6,0xFF,0x01},    // OUTAIM_LEFT00 :
+{0x64F7,0xFF,0x01},    // OUTAIM_LEFT01 :
+{0x64F8,0xFF,0x01},    // OUTAIM_LEFT02 :
+{0x64F9,0xFF,0x01},    // OUTAIM_LEFT03 :
+{0x64FA,0xFF,0x01},    // OUTAIM_LEFT04 :
+{0x64FB,0xFF,0x01},    // OUTAIM_LEFT05 :
+{0x64FC,0xFF,0x01},    // OUTAIM_LEFT06 :
+{0x64FD,0xFF,0x01},    // OUTAIM_LEFT07 :
+{0x64FE,0xFF,0x01},    // OUTAIM_LEFT08 :
+{0x64FF,0xFF,0x01},    // OUTAIM_LEFT09 :
+{0x6500,0x91,0x01},    // OUTAIM_LEFT10 :
+{0x6501,0x91,0x01},    // OUTAIM_LEFT11 :
+{0x6502,0x91,0x01},    // OUTAIM_LEFT12 :
+{0x6503,0x66,0x01},    // OUTAIM_LEFT13 :
+{0x6504,0x5D,0x01},    // OUTAIM_LEFT14 :
+{0x6505,0x3C,0x01},    // OUTAIM_LEFT15 :
+{0x6506,0x3C,0x01},    // OUTAIM_LEFT16 :
+{0x6507,0x3C,0x01},    // OUTAIM_LEFT17 :
+{0x6508,0x3A,0x01},    // OUTAIM_LEFT18 :
+{0x6509,0x39,0x01},    // OUTAIM_LEFT19 :
+{0x650A,0x40,0x01},    // OUTAIM_LEFT20 :
+{0x650B,0x46,0x01},    // OUTAIM_LEFT21 :
+{0x650C,0x42,0x01},    // OUTAIM_LEFT22 :
+{0x650D,0x3D,0x01},    // OUTAIM_LEFT23 :
+{0x650E,0x3A,0x01},    // OUTAIM_LEFT24 :
+{0x650F,0x3E,0x01},    // OUTAIM_LEFT25 :
+{0x6510,0x38,0x01},    // OUTAIM_LEFT26 :
+{0x6511,0x36,0x01},    // OUTAIM_LEFT27 :
+{0x6512,0x34,0x01},    // OUTAIM_LEFT28 :
+{0x6513,0x32,0x01},    // OUTAIM_LEFT29 :
+{0x6514,0x30,0x01},    // OUTAIM_LEFT30 :
+{0x6515,0x2F,0x01},    // OUTAIM_LEFT31 :
+{0x6516,0x2D,0x01},    // OUTAIM_LEFT32 :
+{0x6517,0x2C,0x01},    // OUTAIM_LEFT33 :
+{0x6518,0x2B,0x01},    // OUTAIM_LEFT34 :
+{0x6519,0x2A,0x01},    // OUTAIM_LEFT35 :
+{0x651A,0x29,0x01},    // OUTAIM_LEFT36 :
+{0x651B,0x28,0x01},    // OUTAIM_LEFT37 :
+{0x651C,0xFF,0x01},    // OUTAIM_RIGHT00 :
+{0x651D,0xFF,0x01},    // OUTAIM_RIGHT01 :
+{0x651E,0xFF,0x01},    // OUTAIM_RIGHT02 :
+{0x651F,0xFF,0x01},    // OUTAIM_RIGHT03 :
+{0x6520,0xFF,0x01},    // OUTAIM_RIGHT04 :
+{0x6521,0xFF,0x01},    // OUTAIM_RIGHT05 :
+{0x6522,0xFF,0x01},    // OUTAIM_RIGHT06 :
+{0x6523,0xFF,0x01},    // OUTAIM_RIGHT07 :
+{0x6524,0xFF,0x01},    // OUTAIM_RIGHT08 :
+{0x6525,0xFF,0x01},    // OUTAIM_RIGHT09 :
+{0x6526,0xD9,0x01},    // OUTAIM_RIGHT10 :
+{0x6527,0xB7,0x01},    // OUTAIM_RIGHT11 :
+{0x6528,0x96,0x01},    // OUTAIM_RIGHT12 :
+{0x6529,0x6C,0x01},    // OUTAIM_RIGHT13 :
+{0x652A,0x64,0x01},    // OUTAIM_RIGHT14 :
+{0x652B,0x62,0x01},    // OUTAIM_RIGHT15 :
+{0x652C,0x62,0x01},    // OUTAIM_RIGHT16 :
+{0x652D,0x61,0x01},    // OUTAIM_RIGHT17 :
+{0x652E,0x60,0x01},    // OUTAIM_RIGHT18 :
+{0x652F,0x5E,0x01},    // OUTAIM_RIGHT19 :
+{0x6530,0x5B,0x01},    // OUTAIM_RIGHT20 :
+{0x6531,0x4F,0x01},    // OUTAIM_RIGHT21 :
+{0x6532,0x48,0x01},    // OUTAIM_RIGHT22 :
+{0x6533,0x43,0x01},    // OUTAIM_RIGHT23 :
+{0x6534,0x41,0x01},    // OUTAIM_RIGHT24 :
+{0x6535,0x40,0x01},    // OUTAIM_RIGHT25 :
+{0x6536,0x3D,0x01},    // OUTAIM_RIGHT26 :
+{0x6537,0x3B,0x01},    // OUTAIM_RIGHT27 :
+{0x6538,0x39,0x01},    // OUTAIM_RIGHT28 :
+{0x6539,0x37,0x01},    // OUTAIM_RIGHT29 :
+{0x653A,0x36,0x01},    // OUTAIM_RIGHT30 :
+{0x653B,0x35,0x01},    // OUTAIM_RIGHT31 :
+{0x653C,0x33,0x01},    // OUTAIM_RIGHT32 :
+{0x653D,0x32,0x01},    // OUTAIM_RIGHT33 :
+{0x653E,0x31,0x01},    // OUTAIM_RIGHT34 :
+{0x653F,0x30,0x01},    // OUTAIM_RIGHT35 :
+{0x6540,0x2F,0x01},    // OUTAIM_RIGHT36 :
+{0x6541,0x2E,0x01},    // OUTAIM_RIGHT37 :
+{0x6542,0x1F40,0x02},    // OUTAIM_TOP :
+{0x6544,0x1752,0x02},    // OUTAIM_BOTM :
+{0x6546,0x19,0x01},    // OUTAIM_FLTOP :
+{0x6547,0x17,0x01},    // OUTAIM_FLBOTM :
+
+{0x657A,0x82,0x01},    // IN_CTMP_FRM_BG0 :
+{0x657B,0x78,0x01},    // IN_CTMP_FRM_BG1 :
+{0x657C,0x65,0x01},    // IN_CTMP_FRM_BG2 :
+{0x657D,0x5B,0x01},    // IN_CTMP_FRM_BG3 :
+{0x657E,0x55,0x01},    // IN_CTMP_FRM_BG4 :
+{0x657F,0x4F,0x01},    // IN_CTMP_FRM_BG5 :
+{0x6580,0x49,0x01},    // IN_CTMP_FRM_BG6 :
+{0x6581,0x43,0x01},    // IN_CTMP_FRM_BG7 :
+{0x6582,0x3E,0x01},    // IN_CTMP_FRM_BG8 :
+{0x6583,0x35,0x01},    // IN_CTMP_FRM_BG9 :
+{0x6584,0x30,0x01},    // IN_CTMP_FRM_BG10 :
+{0x6585,0x23,0x01},    // IN_CTMP_FRM_RG0 :
+{0x6586,0x33,0x01},    // IN_CTMP_FRM_RG1 :
+{0x6587,0x3F,0x01},    // IN_CTMP_FRM_RG2 :
+{0x6588,0x53,0x01},    // IN_CTMP_FRM_RG3 :
+{0x6589,0x63,0x01},    // IN_CTMP_FRM_RG4 :
+{0x658A,0x76,0x01},    // IN_CTMP_FRM_RG5 :
+{0x658B,0x9A,0x01},    // IN_CTMP_FRM_RG6 :
+{0x658C,0x00,0x01},    // IN_CTMP_WEIGHT00_01 :
+{0x658D,0x00,0x01},    // IN_CTMP_WEIGHT02_03 :
+{0x658E,0x00,0x01},    // IN_CTMP_WEIGHT04_05 :
+{0x658F,0x00,0x01},    // IN_CTMP_WEIGHT06_07 :
+{0x6590,0x00,0x01},    // IN_CTMP_WEIGHT08_09 :
+{0x6591,0x00,0x01},    // IN_CTMP_WEIGHT10_11 :
+{0x6592,0x00,0x01},    // IN_CTMP_WEIGHT12_13 :
+{0x6593,0x00,0x01},    // IN_CTMP_WEIGHT14_15 :
+{0x6594,0x00,0x01},    // IN_CTMP_WEIGHT16_17 :
+{0x6595,0x00,0x01},    // IN_CTMP_WEIGHT18_19 :
+{0x6596,0x00,0x01},    // IN_CTMP_WEIGHT20_21 :
+{0x6597,0x00,0x01},    // IN_CTMP_WEIGHT22_23 :
+{0x6598,0x00,0x01},    // IN_CTMP_WEIGHT24_25 :
+{0x6599,0x00,0x01},    // IN_CTMP_WEIGHT26_27 :
+{0x659A,0x00,0x01},    // IN_CTMP_WEIGHT28_29 :
+{0x659B,0x00,0x01},    // IN_CTMP_WEIGHT30_31 :
+{0x659C,0x00,0x01},    // IN_CTMP_WEIGHT32_33 :
+{0x659D,0x00,0x01},    // IN_CTMP_WEIGHT34_35 :
+{0x659E,0x00,0x01},    // IN_CTMP_WEIGHT36_37 :
+{0x659F,0x00,0x01},    // IN_CTMP_WEIGHT38_39 :
+{0x65A0,0x00,0x01},    // IN_CTMP_WEIGHT40_41 :
+{0x65A1,0x00,0x01},    // IN_CTMP_WEIGHT42_43 :
+{0x65A2,0x00,0x01},    // IN_CTMP_WEIGHT44_45 :
+{0x65A3,0x00,0x01},    // IN_CTMP_WEIGHT46_47 :
+{0x65A4,0x00,0x01},    // IN_CTMP_WEIGHT48_49 :
+{0x65A5,0x00,0x01},    // IN_CTMP_WEIGHT50_51 :
+{0x65A6,0x00,0x01},    // IN_CTMP_WEIGHT52_53 :
+{0x65A7,0x00,0x01},    // IN_CTMP_WEIGHT54_55 :
+{0x65A8,0x00,0x01},    // IN_CTMP_WEIGHT56_57 :
+{0x65A9,0x10,0x01},    // IN_CTMP_WEIGHT58_59 :
+
+{0x65AA,0x78,0x01},    // OUT_CTMP_FRM_BG0 :
+{0x65AB,0x74,0x01},    // OUT_CTMP_FRM_BG1 :
+{0x65AC,0x70,0x01},    // OUT_CTMP_FRM_BG2 :
+{0x65AD,0x6D,0x01},    // OUT_CTMP_FRM_BG3 :
+{0x65AE,0x69,0x01},    // OUT_CTMP_FRM_BG4 :
+{0x65AF,0x66,0x01},    // OUT_CTMP_FRM_BG5 :
+{0x65B0,0x61,0x01},    // OUT_CTMP_FRM_BG6 :
+{0x65B1,0x5D,0x01},    // OUT_CTMP_FRM_BG7 :
+{0x65B2,0x52,0x01},    // OUT_CTMP_FRM_BG8 :
+{0x65B3,0x4B,0x01},    // OUT_CTMP_FRM_BG9 :
+{0x65B4,0x44,0x01},    // OUT_CTMP_FRM_BG10 :
+{0x65B5,0x19,0x01},    // OUT_CTMP_FRM_RG0 :
+{0x65B6,0x27,0x01},    // OUT_CTMP_FRM_RG1 :
+{0x65B7,0x32,0x01},    // OUT_CTMP_FRM_RG2 :
+{0x65B8,0x3A,0x01},    // OUT_CTMP_FRM_RG3 :
+{0x65B9,0x43,0x01},    // OUT_CTMP_FRM_RG4 :
+{0x65BA,0x4A,0x01},    // OUT_CTMP_FRM_RG5 :
+{0x65BB,0x5E,0x01},    // OUT_CTMP_FRM_RG6 :
+{0x65BC,0x00,0x01},    // OUT_CTMP_WEIGHT00_01 :
+{0x65BD,0x00,0x01},    // OUT_CTMP_WEIGHT02_03 :
+{0x65BE,0x00,0x01},    // OUT_CTMP_WEIGHT04_05 :
+{0x65BF,0x00,0x01},    // OUT_CTMP_WEIGHT06_07 :
+{0x65C0,0x33,0x01},    // OUT_CTMP_WEIGHT08_09 :
+{0x65C1,0x00,0x01},    // OUT_CTMP_WEIGHT10_11 :
+{0x65C2,0x30,0x01},    // OUT_CTMP_WEIGHT12_13 :
+{0x65C3,0x33,0x01},    // OUT_CTMP_WEIGHT14_15 :
+{0x65C4,0x00,0x01},    // OUT_CTMP_WEIGHT16_17 :
+{0x65C5,0x30,0x01},    // OUT_CTMP_WEIGHT18_19 :
+{0x65C6,0x33,0x01},    // OUT_CTMP_WEIGHT20_21 :
+{0x65C7,0x00,0x01},    // OUT_CTMP_WEIGHT22_23 :
+{0x65C8,0x30,0x01},    // OUT_CTMP_WEIGHT24_25 :
+{0x65C9,0x33,0x01},    // OUT_CTMP_WEIGHT26_27 :
+{0x65CA,0x00,0x01},    // OUT_CTMP_WEIGHT28_29 :
+{0x65CB,0x30,0x01},    // OUT_CTMP_WEIGHT30_31 :
+{0x65CC,0x44,0x01},    // OUT_CTMP_WEIGHT32_33 :
+{0x65CD,0x00,0x01},    // OUT_CTMP_WEIGHT34_35 :
+{0x65CE,0x40,0x01},    // OUT_CTMP_WEIGHT36_37 :
+{0x65CF,0x55,0x01},    // OUT_CTMP_WEIGHT38_39 :
+{0x65D0,0x05,0x01},    // OUT_CTMP_WEIGHT40_41 :
+{0x65D1,0x20,0x01},    // OUT_CTMP_WEIGHT42_43 :
+{0x65D2,0x72,0x01},    // OUT_CTMP_WEIGHT44_45 :
+{0x65D3,0x07,0x01},    // OUT_CTMP_WEIGHT46_47 :
+{0x65D4,0x00,0x01},    // OUT_CTMP_WEIGHT48_49 :
+{0x65D5,0x00,0x01},    // OUT_CTMP_WEIGHT50_51 :
+{0x65D6,0x00,0x01},    // OUT_CTMP_WEIGHT52_53 :
+{0x65D7,0x00,0x01},    // OUT_CTMP_WEIGHT54_55 :
+{0x65D8,0x00,0x01},    // OUT_CTMP_WEIGHT56_57 :
+{0x65D9,0x00,0x01},    // OUT_CTMP_WEIGHT58_59 :
+
+{0x6400,0xAA,0x01},    // INFRM_LEFT00 :
+{0x6401,0xAA,0x01},    // INFRM_LEFT01 :
+{0x6402,0xAA,0x01},    // INFRM_LEFT02 :
+{0x6403,0xAA,0x01},    // INFRM_LEFT03 :
+{0x6404,0xAA,0x01},    // INFRM_LEFT04 :
+{0x6405,0xAA,0x01},    // INFRM_LEFT05 :
+{0x6406,0xAA,0x01},    // INFRM_LEFT06 :
+{0x6407,0xAA,0x01},    // INFRM_LEFT07 :
+{0x6408,0xAA,0x01},    // INFRM_LEFT08 :
+{0x6409,0xAE,0x01},    // INFRM_LEFT09 :
+{0x640A,0xA0,0x01},    // INFRM_LEFT10 :
+{0x640B,0x8C,0x01},    // INFRM_LEFT11 :
+{0x640C,0x72,0x01},    // INFRM_LEFT12 :
+{0x640D,0x64,0x01},    // INFRM_LEFT13 :
+{0x640E,0x5A,0x01},    // INFRM_LEFT14 :
+{0x640F,0x52,0x01},    // INFRM_LEFT15 :
+{0x6410,0x48,0x01},    // INFRM_LEFT16 :
+{0x6411,0x43,0x01},    // INFRM_LEFT17 :
+{0x6412,0x3D,0x01},    // INFRM_LEFT18 :
+{0x6413,0x37,0x01},    // INFRM_LEFT19 :
+{0x6414,0x33,0x01},    // INFRM_LEFT20 :
+{0x6415,0x30,0x01},    // INFRM_LEFT21 :
+{0x6416,0x2E,0x01},    // INFRM_LEFT22 :
+{0x6417,0x2B,0x01},    // INFRM_LEFT23 :
+{0x6418,0x28,0x01},    // INFRM_LEFT24 :
+{0x6419,0x26,0x01},    // INFRM_LEFT25 :
+{0x641A,0x24,0x01},    // INFRM_LEFT26 :
+{0x641B,0x23,0x01},    // INFRM_LEFT27 :
+{0x641C,0x22,0x01},    // INFRM_LEFT28 :
+{0x641D,0x22,0x01},    // INFRM_LEFT29 :
+{0x641E,0x21,0x01},    // INFRM_LEFT30 :
+{0x641F,0x20,0x01},    // INFRM_LEFT31 :
+{0x6420,0x1D,0x01},    // INFRM_LEFT32 :
+{0x6421,0x1A,0x01},    // INFRM_LEFT33 :
+{0x6422,0x18,0x01},    // INFRM_LEFT34 :
+{0x6423,0x17,0x01},    // INFRM_LEFT35 :
+{0x6424,0x16,0x01},    // INFRM_LEFT36 :
+{0x6425,0x17,0x01},    // INFRM_LEFT37 :
+{0x6426,0xAF,0x01},    // INFRM_RIGHT00 :
+{0x6427,0xAF,0x01},    // INFRM_RIGHT01 :
+{0x6428,0xAF,0x01},    // INFRM_RIGHT02 :
+{0x6429,0xAF,0x01},    // INFRM_RIGHT03 :
+{0x642A,0xAF,0x01},    // INFRM_RIGHT04 :
+{0x642B,0xAF,0x01},    // INFRM_RIGHT05 :
+{0x642C,0xAF,0x01},    // INFRM_RIGHT06 :
+{0x642D,0xAF,0x01},    // INFRM_RIGHT07 :
+{0x642E,0xAF,0x01},    // INFRM_RIGHT08 :
+{0x642F,0xAA,0x01},    // INFRM_RIGHT09 :
+{0x6430,0xB2,0x01},    // INFRM_RIGHT10 :
+{0x6431,0xB4,0x01},    // INFRM_RIGHT11 :
+{0x6432,0xB6,0x01},    // INFRM_RIGHT12 :
+{0x6433,0xB4,0x01},    // INFRM_RIGHT13 :
+{0x6434,0x9B,0x01},    // INFRM_RIGHT14 :
+{0x6435,0x8E,0x01},    // INFRM_RIGHT15 :
+{0x6436,0x84,0x01},    // INFRM_RIGHT16 :
+{0x6437,0x7A,0x01},    // INFRM_RIGHT17 :
+{0x6438,0x72,0x01},    // INFRM_RIGHT18 :
+{0x6439,0x6A,0x01},    // INFRM_RIGHT19 :
+{0x643A,0x63,0x01},    // INFRM_RIGHT20 :
+{0x643B,0x5E,0x01},    // INFRM_RIGHT21 :
+{0x643C,0x58,0x01},    // INFRM_RIGHT22 :
+{0x643D,0x53,0x01},    // INFRM_RIGHT23 :
+{0x643E,0x4E,0x01},    // INFRM_RIGHT24 :
+{0x643F,0x4A,0x01},    // INFRM_RIGHT25 :
+{0x6440,0x46,0x01},    // INFRM_RIGHT26 :
+{0x6441,0x42,0x01},    // INFRM_RIGHT27 :
+{0x6442,0x3F,0x01},    // INFRM_RIGHT28 :
+{0x6443,0x3C,0x01},    // INFRM_RIGHT29 :
+{0x6444,0x3A,0x01},    // INFRM_RIGHT30 :
+{0x6445,0x38,0x01},    // INFRM_RIGHT31 :
+{0x6446,0x37,0x01},    // INFRM_RIGHT32 :
+{0x6447,0x35,0x01},    // INFRM_RIGHT33 :
+{0x6448,0x33,0x01},    // INFRM_RIGHT34 :
+{0x6449,0x32,0x01},    // INFRM_RIGHT35 :
+{0x644A,0x32,0x01},    // INFRM_RIGHT36 :
+{0x644B,0x32,0x01},    // INFRM_RIGHT37 :
+{0x644C,0x24FA,0x02},    // INFRM_TOP :
+{0x644E,0x0940,0x02},    // INFRM_BOTM :
+{0x6450,0x19,0x01},    // INFRM_FLTOP :
+{0x6451,0x10,0x01},    // INFRM_FLBOTM :
+{0x6452,0x91,0x01},    // INAIM_LEFT00 :
+{0x6453,0x91,0x01},    // INAIM_LEFT01 :
+{0x6454,0x91,0x01},    // INAIM_LEFT02 :
+{0x6455,0x91,0x01},    // INAIM_LEFT03 :
+{0x6456,0x91,0x01},    // INAIM_LEFT04 :
+{0x6457,0x91,0x01},    // INAIM_LEFT05 :
+{0x6458,0x91,0x01},    // INAIM_LEFT06 :
+{0x6459,0x91,0x01},    // INAIM_LEFT07 :
+{0x645A,0x91,0x01},    // INAIM_LEFT08 :
+{0x645B,0x91,0x01},    // INAIM_LEFT09 :
+{0x645C,0x91,0x01},    // INAIM_LEFT10 :
+{0x645D,0x91,0x01},    // INAIM_LEFT11 :
+{0x645E,0x91,0x01},    // INAIM_LEFT12 :
+{0x645F,0x66,0x01},    // INAIM_LEFT13 :
+{0x6460,0x71,0x01},    // INAIM_LEFT14 :
+{0x6461,0x5A,0x01},    // INAIM_LEFT15 :
+{0x6462,0x4E,0x01},    // INAIM_LEFT16 :
+{0x6463,0x47,0x01},    // INAIM_LEFT17 :
+{0x6464,0x42,0x01},    // INAIM_LEFT18 :
+{0x6465,0x3C,0x01},    // INAIM_LEFT19 :
+{0x6466,0x38,0x01},    // INAIM_LEFT20 :
+{0x6467,0x36,0x01},    // INAIM_LEFT21 :
+{0x6468,0x33,0x01},    // INAIM_LEFT22 :
+{0x6469,0x30,0x01},    // INAIM_LEFT23 :
+{0x646A,0x2F,0x01},    // INAIM_LEFT24 :
+{0x646B,0x2B,0x01},    // INAIM_LEFT25 :
+{0x646C,0x29,0x01},    // INAIM_LEFT26 :
+{0x646D,0x27,0x01},    // INAIM_LEFT27 :
+{0x646E,0x26,0x01},    // INAIM_LEFT28 :
+{0x646F,0x28,0x01},    // INAIM_LEFT29 :
+{0x6470,0x2A,0x01},    // INAIM_LEFT30 :
+{0x6471,0x28,0x01},    // INAIM_LEFT31 :
+{0x6472,0x26,0x01},    // INAIM_LEFT32 :
+{0x6473,0x24,0x01},    // INAIM_LEFT33 :
+{0x6474,0x29,0x01},    // INAIM_LEFT34 :
+{0x6475,0x28,0x01},    // INAIM_LEFT35 :
+{0x6476,0x29,0x01},    // INAIM_LEFT36 :
+{0x6477,0x26,0x01},    // INAIM_LEFT37 :
+{0x6478,0xFF,0x01},    // INAIM_RIGHT00 :
+{0x6479,0xFF,0x01},    // INAIM_RIGHT01 :
+{0x647A,0xFF,0x01},    // INAIM_RIGHT02 :
+{0x647B,0xFF,0x01},    // INAIM_RIGHT03 :
+{0x647C,0xFF,0x01},    // INAIM_RIGHT04 :
+{0x647D,0xFF,0x01},    // INAIM_RIGHT05 :
+{0x647E,0xFF,0x01},    // INAIM_RIGHT06 :
+{0x647F,0xFF,0x01},    // INAIM_RIGHT07 :
+{0x6480,0xFF,0x01},    // INAIM_RIGHT08 :
+{0x6481,0xFF,0x01},    // INAIM_RIGHT09 :
+{0x6482,0xD9,0x01},    // INAIM_RIGHT10 :
+{0x6483,0xB7,0x01},    // INAIM_RIGHT11 :
+{0x6484,0x96,0x01},    // INAIM_RIGHT12 :
+{0x6485,0x68,0x01},    // INAIM_RIGHT13 :
+{0x6486,0x72,0x01},    // INAIM_RIGHT14 :
+{0x6487,0x71,0x01},    // INAIM_RIGHT15 :
+{0x6488,0x6E,0x01},    // INAIM_RIGHT16 :
+{0x6489,0x6A,0x01},    // INAIM_RIGHT17 :
+{0x648A,0x65,0x01},    // INAIM_RIGHT18 :
+{0x648B,0x60,0x01},    // INAIM_RIGHT19 :
+{0x648C,0x5B,0x01},    // INAIM_RIGHT20 :
+{0x648D,0x56,0x01},    // INAIM_RIGHT21 :
+{0x648E,0x51,0x01},    // INAIM_RIGHT22 :
+{0x648F,0x4C,0x01},    // INAIM_RIGHT23 :
+{0x6490,0x47,0x01},    // INAIM_RIGHT24 :
+{0x6491,0x44,0x01},    // INAIM_RIGHT25 :
+{0x6492,0x41,0x01},    // INAIM_RIGHT26 :
+{0x6493,0x3E,0x01},    // INAIM_RIGHT27 :
+{0x6494,0x3B,0x01},    // INAIM_RIGHT28 :
+{0x6495,0x39,0x01},    // INAIM_RIGHT29 :
+{0x6496,0x37,0x01},    // INAIM_RIGHT30 :
+{0x6497,0x34,0x01},    // INAIM_RIGHT31 :
+{0x6498,0x33,0x01},    // INAIM_RIGHT32 :
+{0x6499,0x32,0x01},    // INAIM_RIGHT33 :
+{0x649A,0x31,0x01},    // INAIM_RIGHT34 :
+{0x649B,0x30,0x01},    // INAIM_RIGHT35 :
+{0x649C,0x2F,0x01},    // INAIM_RIGHT36 :
+{0x649D,0x2E,0x01},    // INAIM_RIGHT37 :
+{0x649E,0x1E00,0x02},    // INAIM_TOP :
+{0x64A0,0x0DFF,0x02},    // INAIM_BOTM :
+{0x64A2,0x18,0x01},    // INAIM_FLTOP :
+{0x64A3,0x09,0x01},    // INAIM_FLBOTM :
+
+//AWB setting
+{0x629A,0x13,0x01},    // CAT_AWB_2 : OPDG ±â´É off
+{0x629B,0x41,0x01},    // CAT_AWB_3 : outdoor_°¡ÁßÄ¡ on
+{0x625F,0x15,0x01},    // CAT_AWB_1 : MWB½Ã userÁÂÇ¥·Î ÁÂÇ¥ °íÁ¤(AWB½Ã¿¡´Â ¿µÇâ ¹«)
+{0x629C,0x80,0x01},    // FRMOUT_RATIO_BLEND1_OUT
+{0x6224,0x04,0x01},    // ATW_DELAY
+{0x6226,0x08,0x01},    // ATW_GAINS_IN_NR :
+{0x6227,0x04,0x01},    // ATW_GAINS_IN :
+{0x6228,0x08,0x01},    // ATW_GAINS_OUT_NR :
+{0x6229,0x04,0x01},    // ATW_GAINS_OUT :
+
+//Bluesky threshold º¯°æ
+{0x6548,0x18F7,0x02},    // OUTAIM_TOP_BLUESKY :
+
+//Hue, Gain setting
+{0x6E86,0x0000,0x02},    // IBYHUE1_POS1 :
+{0x6E88,0xFFF5,0x02},    // IRYHUE1_POS1 :
+{0x6E8A,0xFFF8,0x02},    // IBYHUE2_POS1 :
+{0x6E8C,0xFFF5,0x02},    // IRYHUE2_POS1 :
+{0x6E8E,0xFFF8,0x02},    // IBYHUE3_POS1 :
+{0x6E90,0xFFEE,0x02},    // IRYHUE3_POS1 :
+{0x6E92,0x0000,0x02},    // IBYHUE4_POS1 :
+{0x6E94,0xFFEC,0x02},    // IRYHUE4_POS1 :
+{0x6E96,0x0000,0x02},    // IBYHUE1_POS2 :
+{0x6E98,0xFFF8,0x02},    // IRYHUE1_POS2 :
+{0x6E9A,0xFFFD,0x02},    // IBYHUE2_POS2 :
+{0x6E9C,0xFFF8,0x02},    // IRYHUE2_POS2 :
+{0x6E9E,0xFFFD,0x02},    // IBYHUE3_POS2 :
+{0x6EA0,0xFFEE,0x02},    // IRYHUE3_POS2 :
+{0x6EA2,0x0000,0x02},    // IBYHUE4_POS2 :
+{0x6EA4,0xFFEC,0x02},    // IRYHUE4_POS2 :
+{0x6EA6,0x0000,0x02},    // IBYHUE1_POS3 :
+{0x6EA8,0xFFF5,0x02},    // IRYHUE1_POS3 :
+{0x6EAA,0xFFF8,0x02},    // IBYHUE2_POS3 :
+{0x6EAC,0xFFF5,0x02},    // IRYHUE2_POS3 :
+{0x6EAE,0xFFF8,0x02},    // IBYHUE3_POS3 :
+{0x6EB0,0xFFEE,0x02},    // IRYHUE3_POS3 :
+{0x6EB2,0x0000,0x02},    // IBYHUE4_POS3 :
+{0x6EB4,0xFFEC,0x02},    // IRYHUE4_POS3 :
+{0x6EB6,0x0000,0x02},    // IBYHUE1_POS4 :
+{0x6EB8,0xFFF5,0x02},    // IRYHUE1_POS4 :
+{0x6EBA,0xFFF8,0x02},    // IBYHUE2_POS4 :
+{0x6EBC,0xFFF5,0x02},    // IRYHUE2_POS4 :
+{0x6EBE,0xFFF8,0x02},    // IBYHUE3_POS4 :
+{0x6EC0,0xFFEE,0x02},    // IRYHUE3_POS4 :
+{0x6EC2,0x0000,0x02},    // IBYHUE4_POS4 :
+{0x6EC4,0xFFEC,0x02},    // IRYHUE4_POS4 :
+{0x6EC6,0x0000,0x02},    // IBYHUE1_POS5 :
+{0x6EC8,0xFFF5,0x02},    // IRYHUE1_POS5 :
+{0x6ECA,0xFFF8,0x02},    // IBYHUE2_POS5 :
+{0x6ECC,0xFFF5,0x02},    // IRYHUE2_POS5 :
+{0x6ECE,0xFFF8,0x02},    // IBYHUE3_POS5 :
+{0x6ED0,0xFFEE,0x02},    // IRYHUE3_POS5 :
+{0x6ED2,0x0000,0x02},    // IBYHUE4_POS5 :
+{0x6ED4,0xFFEC,0x02},    // IRYHUE4_POS5 :
+{0x6ED6,0x0000,0x02},    // IBYHUE1_POS6 :
+{0x6ED8,0xFFF5,0x02},    // IRYHUE1_POS6 :
+{0x6EDA,0xFFF8,0x02},    // IBYHUE2_POS6 :
+{0x6EDC,0xFFF5,0x02},    // IRYHUE2_POS6 :
+{0x6EDE,0xFFF8,0x02},    // IBYHUE3_POS6 :
+{0x6EE0,0xFFEE,0x02},    // IRYHUE3_POS6 :
+{0x6EE2,0x0000,0x02},    // IBYHUE4_POS6 :
+{0x6EE4,0xFFEC,0x02},    // IRYHUE4_POS6 :
+{0x6EE6,0x0000,0x02},    // IBYHUE1_POS7 :
+{0x6EE8,0xFFF5,0x02},    // IRYHUE1_POS7 :
+{0x6EEA,0xFFEA,0x02},    // IBYHUE2_POS7 :
+{0x6EEC,0xFFF5,0x02},    // IRYHUE2_POS7 :
+{0x6EEE,0xFFEA,0x02},    // IBYHUE3_POS7 :
+{0x6EF0,0xFFEE,0x02},    // IRYHUE3_POS7 :
+{0x6EF2,0x0000,0x02},    // IBYHUE4_POS7 :
+{0x6EF4,0xFFEC,0x02},    // IRYHUE4_POS7 :
+{0x6EF6,0xFFF2,0x02},    // IBYHUE1_OUT :
+{0x6EF8,0x0000,0x02},    // IRYHUE1_OUT :
+{0x6EFA,0xFFFA,0x02},    // IBYHUE2_OUT :
+{0x6EFC,0x0000,0x02},    // IRYHUE2_OUT :
+{0x6EFE,0xFFFA,0x02},    // IBYHUE3_OUT :
+{0x6F00,0xFFE7,0x02},    // IRYHUE3_OUT :
+{0x6F02,0xFFF2,0x02},    // IBYHUE4_OUT :
+{0x6F04,0xFFE7,0x02},    // IRYHUE4_OUT :
+{0x6F06,0x0000,0x02},    // IBYHUE1_R2_POS4 :
+{0x6F08,0xFFF5,0x02},    // IRYHUE1_R2_POS4 :
+{0x6F0A,0xFFF8,0x02},    // IBYHUE2_R2_POS4 :
+{0x6F0C,0xFFF5,0x02},    // IRYHUE2_R2_POS4 :
+{0x6F0E,0xFFF8,0x02},    // IBYHUE3_R2_POS4 :
+{0x6F10,0xFFEE,0x02},    // IRYHUE3_R2_POS4 :
+{0x6F12,0x0000,0x02},    // IBYHUE4_R2_POS4 :
+{0x6F14,0xFFEC,0x02},    // IRYHUE4_R2_POS4 :
+{0x6F16,0x0000,0x02},    // IBYHUE1_R2_POS5 :
+{0x6F18,0xFFF5,0x02},    // IRYHUE1_R2_POS5 :
+{0x6F1A,0xFFF8,0x02},    // IBYHUE2_R2_POS5 :
+{0x6F1C,0xFFF5,0x02},    // IRYHUE2_R2_POS5 :
+{0x6F1E,0xFFF8,0x02},    // IBYHUE3_R2_POS5 :
+{0x6F20,0xFFEE,0x02},    // IRYHUE3_R2_POS5 :
+{0x6F22,0x0000,0x02},    // IBYHUE4_R2_POS5 :
+{0x6F24,0xFFEC,0x02},    // IRYHUE4_R2_POS5 :
+{0x6F26,0x4B,0x01},    // IRYGAIN1_POS1 :
+{0x6F27,0x50,0x01},    // IBYGAIN1_POS1 :
+{0x6F28,0x4B,0x01},    // IRYGAIN2_POS1 :
+{0x6F29,0x57,0x01},    // IBYGAIN2_POS1 :
+{0x6F2A,0x56,0x01},    // IRYGAIN3_POS1 :
+{0x6F2B,0x57,0x01},    // IBYGAIN3_POS1 :
+{0x6F2C,0x56,0x01},    // IRYGAIN4_POS1 :
+{0x6F2D,0x50,0x01},    // IBYGAIN4_POS1 :
+{0x6F2E,0x4B,0x01},    // IRYGAIN1_POS2 :
+{0x6F2F,0x50,0x01},    // IBYGAIN1_POS2 :
+{0x6F30,0x4B,0x01},    // IRYGAIN2_POS2 :
+{0x6F31,0x57,0x01},    // IBYGAIN2_POS2 :
+{0x6F32,0x54,0x01},    // IRYGAIN3_POS2 :
+{0x6F33,0x57,0x01},    // IBYGAIN3_POS2 :
+{0x6F34,0x54,0x01},    // IRYGAIN4_POS2 :
+{0x6F35,0x50,0x01},    // IBYGAIN4_POS2 :
+{0x6F36,0x4B,0x01},    // IRYGAIN1_POS3 :
+{0x6F37,0x50,0x01},    // IBYGAIN1_POS3 :
+{0x6F38,0x4B,0x01},    // IRYGAIN2_POS3 :
+{0x6F39,0x57,0x01},    // IBYGAIN2_POS3 :
+{0x6F3A,0x50,0x01},    // IRYGAIN3_POS3 :
+{0x6F3B,0x57,0x01},    // IBYGAIN3_POS3 :
+{0x6F3C,0x50,0x01},    // IRYGAIN4_POS3 :
+{0x6F3D,0x50,0x01},    // IBYGAIN4_POS3 :
+{0x6F3E,0x4B,0x01},    // IRYGAIN1_POS4 :
+{0x6F3F,0x50,0x01},    // IBYGAIN1_POS4 :
+{0x6F40,0x4B,0x01},    // IRYGAIN2_POS4 :
+{0x6F41,0x57,0x01},    // IBYGAIN2_POS4 :
+{0x6F42,0x50,0x01},    // IRYGAIN3_POS4 :
+{0x6F43,0x57,0x01},    // IBYGAIN3_POS4 :
+{0x6F44,0x50,0x01},    // IRYGAIN4_POS4 :
+{0x6F45,0x50,0x01},    // IBYGAIN4_POS4 :
+{0x6F46,0x4B,0x01},    // IRYGAIN1_POS5 :
+{0x6F47,0x50,0x01},    // IBYGAIN1_POS5 :
+{0x6F48,0x4B,0x01},    // IRYGAIN2_POS5 :
+{0x6F49,0x57,0x01},    // IBYGAIN2_POS5 :
+{0x6F4A,0x50,0x01},    // IRYGAIN3_POS5 :
+{0x6F4B,0x57,0x01},    // IBYGAIN3_POS5 :
+{0x6F4C,0x50,0x01},    // IRYGAIN4_POS5 :
+{0x6F4D,0x50,0x01},    // IBYGAIN4_POS5 :
+{0x6F4E,0x4B,0x01},    // IRYGAIN1_POS6 :
+{0x6F4F,0x50,0x01},    // IBYGAIN1_POS6 :
+{0x6F50,0x4B,0x01},    // IRYGAIN2_POS6 :
+{0x6F51,0x57,0x01},    // IBYGAIN2_POS6 :
+{0x6F52,0x50,0x01},    // IRYGAIN3_POS6 :
+{0x6F53,0x57,0x01},    // IBYGAIN3_POS6 :
+{0x6F54,0x50,0x01},    // IRYGAIN4_POS6 :
+{0x6F55,0x50,0x01},    // IBYGAIN4_POS6 :
+{0x6F56,0x4B,0x01},    // IRYGAIN1_POS7 :
+{0x6F57,0x50,0x01},    // IBYGAIN1_POS7 :
+{0x6F58,0x4B,0x01},    // IRYGAIN2_POS7 :
+{0x6F59,0x57,0x01},    // IBYGAIN2_POS7 :
+{0x6F5A,0x50,0x01},    // IRYGAIN3_POS7 :
+{0x6F5B,0x57,0x01},    // IBYGAIN3_POS7 :
+{0x6F5C,0x50,0x01},    // IRYGAIN4_POS7 :
+{0x6F5D,0x50,0x01},    // IBYGAIN4_POS7 :
+{0x6F5E,0x50,0x01},    // IRYGAIN1_OUT :
+{0x6F5F,0x5A,0x01},    // IBYGAIN1_OUT :
+{0x6F60,0x50,0x01},    // IRYGAIN2_OUT :
+{0x6F61,0x51,0x01},    // IBYGAIN2_OUT :
+{0x6F62,0x64,0x01},    // IRYGAIN3_OUT :
+{0x6F63,0x51,0x01},    // IBYGAIN3_OUT :
+{0x6F64,0x64,0x01},    // IRYGAIN4_OUT :
+{0x6F65,0x5A,0x01},    // IBYGAIN4_OUT :
+{0x6F66,0x4B,0x01},    // IRYGAIN1_R2_POS4 :
+{0x6F67,0x50,0x01},    // IBYGAIN1_R2_POS4 :
+{0x6F68,0x4B,0x01},    // IRYGAIN2_R2_POS4 :
+{0x6F69,0x57,0x01},    // IBYGAIN2_R2_POS4 :
+{0x6F6A,0x50,0x01},    // IRYGAIN3_R2_POS4 :
+{0x6F6B,0x57,0x01},    // IBYGAIN3_R2_POS4 :
+{0x6F6C,0x50,0x01},    // IRYGAIN4_R2_POS4 :
+{0x6F6D,0x50,0x01},    // IBYGAIN4_R2_POS4 :
+{0x6F6E,0x4B,0x01},    // IRYGAIN1_R2_POS5 :
+{0x6F6F,0x50,0x01},    // IBYGAIN1_R2_POS5 :
+{0x6F70,0x4B,0x01},    // IRYGAIN2_R2_POS5 :
+{0x6F71,0x57,0x01},    // IBYGAIN2_R2_POS5 :
+{0x6F72,0x50,0x01},    // IRYGAIN3_R2_POS5 :
+{0x6F73,0x57,0x01},    // IBYGAIN3_R2_POS5 :
+{0x6F74,0x50,0x01},    // IRYGAIN4_R2_POS5 :
+{0x6F75,0x50,0x01},    // IBYGAIN4_R2_POS5 :
+
+
+//LMT outdoor setting
+{0x6E54,0xFFB1,0x02},    // LM_GRG_OUT :
+{0x6E56,0x0015,0x02},    // LM_GRB_OUT :
+{0x6E58,0xFFE5,0x02},    // LM_GGR_OUT :
+{0x6E5A,0xFFFA,0x02},    // LM_GGB_OUT :
+{0x6E5C,0xFFDA,0x02},    // LM_GBR_OUT :
+{0x6E5E,0xFFE9,0x02},    // LM_GBG_OUT :
+
+//MC3 ON&OFF
+{0x6C49,0xF5,0x01},    // MAIN_CONFIG4 :
+
+
+////////////////////////////////////////////////////////////////
+
+{0x941F,0x00,0x01},    // AP_N_GC_POS_CORE_A : <<N´ë¿ª Coring ¾ç¼öÃø Äھ ¹üÀ§ A¼³Á¤°ª
+{0x9420,0x00,0x01},    // AP_N_GC_POS_CORE_B :
+{0x9421,0x02,0x01},    // AP_N_GC_POS_CORE_C1 :
+{0x9422,0x01,0x01},    // AP_N_GC_POS_CORE_C2 :
+{0x9423,0x20,0x01},    // AP_N_GC_POS_SLOPE_A : <<N´ë¿ª Coring ¾ç¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x9424,0x0D,0x01},    // AP_N_GC_POS_SLOPE_B :
+{0x9425,0x0F,0x01},    // AP_N_GC_POS_SLOPE_C1 :
+{0x9426,0x08,0x01},    // AP_N_GC_POS_SLOPE_C2 :
+{0x9427,0x00,0x01},    // AP_N_GC_NEG_CORE_A : <<N´ë¿ª Coring À½¼öÃøÄھ¹üÀ§ A¼³Á¤°ª
+{0x9428,0x00,0x01},    // AP_N_GC_NEG_CORE_B :
+{0x9429,0x02,0x01},    // AP_N_GC_NEG_CORE_C1 :
+{0x942A,0x01,0x01},    // AP_N_GC_NEG_CORE_C2 :
+{0x942B,0x20,0x01},    // AP_N_GC_NEG_SLOPE_A : <<N´ë¿ª Coring À½¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x942C,0x13,0x01},    // AP_N_GC_NEG_SLOPE_B :
+{0x942D,0x10,0x01},    // AP_N_GC_NEG_SLOPE_C1 :
+{0x942E,0x08,0x01},    // AP_N_GC_NEG_SLOPE_C2 :
+{0x942F,0x20,0x01},    // AP_N_GAIN_POS_A : <<N´ë¿ª POST Gain ¾ç¼öÃø A¼³Á¤°ª
+{0x9430,0x3C,0x01},    // AP_N_GAIN_POS_B :
+{0x9431,0x33,0x01},    // AP_N_GAIN_POS_C1 :
+{0x9432,0x30,0x01},    // AP_N_GAIN_POS_C2 :
+{0x9433,0x20,0x01},    // AP_N_GAIN_NEG_A : <<N´ë¿ª POST Gain À½¼öÃø A¼³Á¤°ª
+{0x9434,0x48,0x01},    // AP_N_GAIN_NEG_B :
+{0x9435,0x37,0x01},    // AP_N_GAIN_NEG_C1 :
+{0x9436,0x38,0x01},    // AP_N_GAIN_NEG_C2 :
+////////////////////////////////////////////////////////////////
+
+{0x9437,0x01,0x01},    // AP_H_GC_POS_CORE_A : <<H´ë¿ª Coring ¾ç¼öÃøÄھ¹üÀ§ A¼³Á¤°ª
+{0x9438,0x01,0x01},    // AP_H_GC_POS_CORE_B :
+{0x9439,0x00,0x01},    // AP_H_GC_POS_CORE_C1 :
+{0x943A,0x00,0x01},    // AP_H_GC_POS_CORE_C2 :
+{0x943B,0x38,0x01},    // AP_H_GC_POS_SLOPE_A : <<H´ë¿ª Coring ¾ç¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x943C,0x3F,0x01},    // AP_H_GC_POS_SLOPE_B :
+{0x943D,0x30,0x01},    // AP_H_GC_POS_SLOPE_C1 :
+{0x943E,0x13,0x01},    // AP_H_GC_POS_SLOPE_C2 :
+{0x943F,0x00,0x01},    // AP_H_GC_NEG_CORE_A : <<H´ë¿ª Coring À½¼öÃøÄھ¹üÀ§ A¼³Á¤°ª
+{0x9440,0x01,0x01},    // AP_H_GC_NEG_CORE_B :
+{0x9441,0x00,0x01},    // AP_H_GC_NEG_CORE_C1 :
+{0x9442,0x00,0x01},    // AP_H_GC_NEG_CORE_C2 :
+{0x9443,0x38,0x01},    // AP_H_GC_NEG_SLOPE_A : <<H´ë¿ª Coring À½¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x9444,0x09,0x01},    // AP_H_GC_NEG_SLOPE_B :
+{0x9445,0x2D,0x01},    // AP_H_GC_NEG_SLOPE_C1 :
+{0x9446,0x0A,0x01},    // AP_H_GC_NEG_SLOPE_C2 :
+{0x9447,0x50,0x01},    // AP_H_GAIN_POS_A : <<H´ë¿ª POST Gain ¾ç¼öÃø A¼³Á¤°ª
+{0x9448,0x38,0x01},    // AP_H_GAIN_POS_B :
+{0x9449,0x72,0x01},    // AP_H_GAIN_POS_C1 :
+{0x944A,0x72,0x01},    // AP_H_GAIN_POS_C2 :
+{0x944B,0x50,0x01},    // AP_H_GAIN_NEG_A : <<H´ë¿ª POST Gain À½¼öÃø A¼³Á¤°ª
+{0x944C,0x40,0x01},    // AP_H_GAIN_NEG_B :
+{0x944D,0x66,0x01},    // AP_H_GAIN_NEG_C1 :
+{0x944E,0x96,0x01},    // AP_H_GAIN_NEG_C2 :
+{0x944F,0x01,0x01},    // AP_L_GC_POS_CORE_A : <<L´ë¿ª Coring ¾ç¼öÃøÄھ¹üÀ§ A¼³Á¤°ª
+{0x9450,0x00,0x01},    // AP_L_GC_POS_CORE_B :
+{0x9451,0x00,0x01},    // AP_L_GC_POS_CORE_C1 :
+{0x9452,0x04,0x01},    // AP_L_GC_POS_CORE_C2
+{0x9453,0x24,0x01},    // AP_L_GC_POS_SLOPE_A : <<L´ë¿ª Coring ¾ç¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x9454,0x20,0x01},    // AP_L_GC_POS_SLOPE_B :
+{0x9455,0x08,0x01},    // AP_L_GC_POS_SLOPE_C1 :
+{0x9456,0x08,0x01},    // AP_L_GC_POS_SLOPE_C2 :
+{0x9457,0x01,0x01},    // AP_L_GC_NEG_CORE_A : <L´ë¿ª Coring À½¼öÃøÄھ¹üÀ§ A¼³Á¤°ª
+{0x9458,0x00,0x01},    // AP_L_GC_NEG_CORE_B :
+{0x9459,0x00,0x01},    // AP_L_GC_NEG_CORE_C1
+{0x945A,0x04,0x01},    // AP_L_GC_NEG_CORE_C2
+{0x945B,0x24,0x01},    // AP_L_GC_NEG_SLOPE_A : <<L´ë¿ª Coring À½¼öÃø °íÁøÆøÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x945C,0x20,0x01},    // AP_L_GC_NEG_SLOPE_B :
+{0x945D,0x04,0x01},    // AP_L_GC_NEG_SLOPE_C1 :
+{0x945E,0x04,0x01},    // AP_L_GC_NEG_SLOPE_C2 :
+{0x945F,0x0A,0x01},    // AP_L_GAIN_POS_A : <<L´ë¿ª POST Gain ¾ç¼öÃø A¼³Á¤°ª
+{0x9460,0x11,0x01},    // AP_L_GAIN_POS_B :
+{0x9461,0x1C,0x01},    // AP_L_GAIN_POS_C1 :
+{0x9462,0x60,0x01},    // AP_L_GAIN_POS_C2 :
+{0x9463,0x08,0x01},    // AP_L_GAIN_NEG_A : <<L´ë¿ª POST Gain À½¼öÃø A¼³Á¤°ª
+{0x9464,0x0B,0x01},    // AP_L_GAIN_NEG_B :
+{0x9465,0x0A,0x01},    // AP_L_GAIN_NEG_C1 :
+{0x9466,0x20,0x01},    // AP_L_GAIN_NEG_C2 :
+////////////////////////////////////////////////////////////////
+{0x9468,0x0200,0x02},    // AP_N_GC_POS_TH_A : <<N´ë¿ª Coring ¾ç¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x946A,0x00C0,0x02},    // AP_N_GC_POS_TH_B :
+{0x946C,0x0168,0x02},    // AP_N_GC_POS_TH_C1 :
+{0x946E,0x0168,0x02},    // AP_N_GC_POS_TH_C2 :
+{0x9470,0x0200,0x02},    // AP_N_GC_NEG_TH_A : <<N´ë¿ª Coring À½¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x9472,0x00C0,0x02},    // AP_N_GC_NEG_TH_B :
+{0x9474,0x00B4,0x02},    // AP_N_GC_NEG_TH_C1 :
+{0x9476,0x00B4,0x02},    // AP_N_GC_NEG_TH_C2 :
+{0x9478,0x0000,0x02},    // AP_N_LD_DARK_TH_A : <<£Î´ë¿ª LevelDepend ÀúÈÖµµ ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x947A,0x0000,0x02},    // AP_N_LD_DARK_TH_B :
+{0x947C,0x0000,0x02},    // AP_N_LD_DARK_TH_C1 :
+{0x947E,0x0000,0x02},    // AP_N_LD_DARK_TH_C2 :
+{0x9480,0x0096,0x02},    // AP_N_LD_HIGH_TH0_X_A: <<£Î´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0 A¼³Á¤°ª
+{0x9482,0x0050,0x02},    // AP_N_LD_HIGH_TH0_X_B :
+{0x9484,0x0050,0x02},    // AP_N_LD_HIGH_TH0_X_C1 :
+{0x9486,0x0050,0x02},    // AP_N_LD_HIGH_TH0_X_C2 :
+{0x9488,0x0080,0x02},    // AP_N_LD_HIGH_TH0_Y_A : <<£Î´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0¿¡¼­ÀÇ Ãâ·Â Gain A¼³Á¤°ª
+{0x948A,0x0080,0x02},    // AP_N_LD_HIGH_TH0_Y_B :
+{0x948C,0x0080,0x02},    // AP_N_LD_HIGH_TH0_Y_C1 :
+{0x948E,0x0080,0x02},    // AP_N_LD_HIGH_TH0_Y_C2 :
+{0x9490,0x00C8,0x02},    // AP_N_LD_HIGH_TH1_X_A : <<N´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡1 A¼³Á¤°ª
+{0x9492,0x012C,0x02},    // AP_N_LD_HIGH_TH1_X_B :
+{0x9494,0x00C8,0x02},    // AP_N_LD_HIGH_TH1_X_C1 :
+{0x9496,0x00C8,0x02},    // AP_N_LD_HIGH_TH1_X_C2
+{0x9498,0x01F4,0x02},    // AP_N_LD_HIGH_TH2_X_A : <<N´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡2 A¼³Á¤°ª
+{0x949A,0x0200,0x02},    // AP_N_LD_HIGH_TH2_X_B :
+{0x949C,0x0200,0x02},    // AP_N_LD_HIGH_TH2_X_C1 :
+{0x949E,0x0200,0x02},    // AP_N_LD_HIGH_TH2_X_C2 :
+////////////////////////////////////////////////////////////////
+
+{0x94A0,0x0050,0x02},    // AP_H_GC_POS_TH_A : <<H´ë¿ª Coring ¾ç¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94A2,0x00A0,0x02},    // AP_H_GC_POS_TH_B :
+{0x94A4,0x0033,0x02},    // AP_H_GC_POS_TH_C1 :
+{0x94A6,0x0033,0x02},    // AP_H_GC_POS_TH_C2 :
+{0x94A8,0x0050,0x02},    // AP_H_GC_NEG_TH_A : <<H´ë¿ª Coring À½¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94AA,0x00A0,0x02},    // AP_H_GC_NEG_TH_B :
+{0x94AC,0x0033,0x02},    // AP_H_GC_NEG_TH_C1 :
+{0x94AE,0x0033,0x02},    // AP_H_GC_NEG_TH_C2 :
+{0x94B0,0x0021,0x02},    // AP_H_LD_DARK_TH_A : <<H´ë¿ª LevelDepend ÀúÈÖµµ ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94B2,0x0000,0x02},    // AP_H_LD_DARK_TH_B :
+{0x94B4,0x0000,0x02},    // AP_H_LD_DARK_TH_C1 :
+{0x94B6,0x0000,0x02},    // AP_H_LD_DARK_TH_C2
+{0x94B8,0x01F4,0x02},    // AP_H_LD_HIGH_TH0_X_A : <<H´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0 A¼³Á¤°ª
+{0x94BA,0x0083,0x02},    // AP_H_LD_HIGH_TH0_X_B :
+{0x94BC,0x0064,0x02},    // AP_H_LD_HIGH_TH0_X_C1 :
+{0x94BE,0x0064,0x02},    // AP_H_LD_HIGH_TH0_X_C2 :
+{0x94C0,0x0080,0x02},    // AP_H_LD_HIGH_TH0_Y_A : <<H´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0¿¡¼­ÀÇ Ãâ·Â Gain A¼³Á¤°ª
+{0x94C2,0x0080,0x02},    // AP_H_LD_HIGH_TH0_Y_B :
+{0x94C4,0x0080,0x02},    // AP_H_LD_HIGH_TH0_Y_C1 :
+{0x94C6,0x0080,0x02},    // AP_H_LD_HIGH_TH0_Y_C2 :
+{0x94C8,0x0244,0x02},    // AP_H_LD_HIGH_TH1_X_A : <<H´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡1 A¼³Á¤
+{0x94CA,0x01AA,0x02},    // AP_H_LD_HIGH_TH1_X_B :
+{0x94CC,0x00C8,0x02},    // AP_H_LD_HIGH_TH1_X_C1 :
+{0x94CE,0x00C8,0x02},    // AP_H_LD_HIGH_TH1_X_C2 :
+{0x94D0,0x02EC,0x02},    // AP_H_LD_HIGH_TH2_X_A : <<H´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡2 A¼³Á¤°ª
+{0x94D2,0x01EF,0x02},    // AP_H_LD_HIGH_TH2_X_B :
+{0x94D4,0x01E0,0x02},    // AP_H_LD_HIGH_TH2_X_C1 :
+{0x94D6,0x01E0,0x02},    // AP_H_LD_HIGH_TH2_X_C2 :
+{0x94D8,0x0001,0x02},    // AP_L_GC_POS_TH_A : <<L´ë¿ª Coring ¾ç¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94DA,0x0040,0x02},    // AP_L_GC_POS_TH_B :
+{0x94DC,0x0010,0x02},    // AP_L_GC_POS_TH_C1 :
+{0x94DE,0x0010,0x02},    // AP_L_GC_POS_TH_C2 :
+{0x94E0,0x0001,0x02},    // AP_L_GC_NEG_TH_A : <<L´ë¿ª Coring À½¼öÃø °íÁøÆø ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94E2,0x0030,0x02},    // AP_L_GC_NEG_TH_B :
+{0x94E4,0x0020,0x02},    // AP_L_GC_NEG_TH_C1 :
+{0x94E6,0x0020,0x02},    // AP_L_GC_NEG_TH_C2 :
+{0x94E8,0x0000,0x02},    // AP_L_LD_DARK_TH_A : <<L´ë¿ª LevelDepend ÀúÈÖµµ ÀÓ°èÄ¡ A¼³Á¤°ª
+{0x94EA,0x0000,0x02},    // AP_L_LD_DARK_TH_B :
+{0x94EC,0x0000,0x02},    // AP_L_LD_DARK_TH_C1 :
+{0x94EE,0x0000,0x02},    // AP_L_LD_DARK_TH_C2 :
+{0x94F0,0x015E,0x02},    // AP_L_LD_HIGH_TH0_X_A : <<L´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0 A¼³Á¤°ª
+{0x94F2,0x015E,0x02},    // AP_L_LD_HIGH_TH0_X_B :
+{0x94F4,0x0010,0x02},    // AP_L_LD_HIGH_TH0_X_C1 :
+{0x94F6,0x0010,0x02},    // AP_L_LD_HIGH_TH0_X_C2 :
+{0x94F8,0x0080,0x02},    // AP_L_LD_HIGH_TH0_Y_A : <<L´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡0¿¡¼­ÀÇ Ãâ·Â Gain A¼³Á¤°ª
+{0x94FA,0x0080,0x02},    // AP_L_LD_HIGH_TH0_Y_B :
+{0x94FC,0x0080,0x02},    // AP_L_LD_HIGH_TH0_Y_C1 :
+{0x94FE,0x0080,0x02},    // AP_L_LD_HIGH_TH0_Y_C2 :
+{0x9500,0x0226,0x02},    // AP_L_LD_HIGH_TH1_X_A : <<L´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡1 A¼³Á¤°ª
+{0x9502,0x0226,0x02},    // AP_L_LD_HIGH_TH1_X_B :
+{0x9504,0x0020,0x02},    // AP_L_LD_HIGH_TH1_X_C1 :
+{0x9506,0x0020,0x02},    // AP_L_LD_HIGH_TH1_X_C2 :
+{0x9508,0x02A2,0x02},    // AP_L_LD_HIGH_TH2_X_A : <<L´ë¿ª LevelDepend °íÈÖµµ ÀÓ°èÄ¡2 A¼³Á¤°ª
+{0x950A,0x028A,0x02},    // AP_L_LD_HIGH_TH2_X_B :
+{0x950C,0x0050,0x02},    // AP_L_LD_HIGH_TH2_X_C1 :
+{0x950E,0x0050,0x02},    // AP_L_LD_HIGH_TH2_X_C2 :
+
+//blendÈÄ ¸®¹ÌÆ® ¼³Á¤
+
+{0x9510,0x0020,0x02},    // AP_POST_LIM_POS_A : <<
+{0x9512,0x0060,0x02},    // AP_POST_LIM_POS_B :
+{0x9514,0x0060,0x02},    // AP_POST_LIM_POS_C1 :
+{0x9516,0x0060,0x02},    // AP_POST_LIM_POS_C2 :
+{0x9518,0x0030,0x02},    // AP_POST_LIM_NEG_A : <<
+{0x951A,0x0048,0x02},    // AP_POST_LIM_NEG_B :
+{0x951C,0x0048,0x02},    // AP_POST_LIM_NEG_C1 :
+{0x951E,0x0048,0x02},    // AP_POST_LIM_NEG_C2 :
+{0x9520,0x0000,0x02},    // AP_POST_CORE_POS_A : <<
+{0x9522,0x0000,0x02},    // AP_POST_CORE_POS_B :
+{0x9524,0x0001,0x02},    // AP_POST_CORE_POS_C1 :
+{0x9526,0x0001,0x02},    // AP_POST_CORE_POS_C2 :
+{0x9528,0x0002,0x02},    // AP_POST_CORE_NEG_A : <
+{0x952A,0x0000,0x02},    // AP_POST_CORE_NEG_B :
+{0x952C,0x0000,0x02},    // AP_POST_CORE_NEG_C1 :
+{0x952E,0x0000,0x02},    // AP_POST_CORE_NEG_C2 :
+
+//level defender ¼³Á¤
+
+{0x9530,0x0000,0x02},    // AP_N_LD_DARK_SLOPE_A : << N´ë¿ª LevelDepend ÀúÈÖµµÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x9532,0x0000,0x02},
+{0x9534,0x0000,0x02},    // AP_N_LD_DARK_SLOPE_B :
+{0x9536,0x0000,0x02},
+{0x9538,0x0000,0x02},    // AP_N_LD_DARK_SLOPE_C1 :
+{0x953A,0x0000,0x02},
+{0x953C,0x0000,0x02},    // AP_N_LD_DARK_SLOPE_C2 :
+{0x953E,0x0000,0x02},
+{0x9540,0x0061,0x02},    // AP_N_LD_HIGH_SLOPE0_A : << N´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡0¢¦ÀÓ°èÄ¡1¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x9542,0x0000,0x02},
+{0x9544,0x0031,0x02},    // AP_N_LD_HIGH_SLOPE0_B :
+{0x9546,0x0000,0x02},
+{0x9548,0x0000,0x02},    // AP_N_LD_HIGH_SLOPE0_C1 :
+{0x954A,0x0000,0x02},
+{0x954C,0x0000,0x02},    // AP_N_LD_HIGH_SLOPE0_C2 :
+{0x954E,0x0000,0x02},
+{0x9550,0x001C,0x02},    // AP_N_LD_HIGH_SLOPE1_A : <<N´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡1¢¦ÀÓ°èÄ¡2¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x9552,0x0000,0x02},
+{0x9554,0x000C,0x02},    // AP_N_LD_HIGH_SLOPE1_B :
+{0x9556,0x0000,0x02},
+{0x9558,0x001A,0x02},    // AP_N_LD_HIGH_SLOPE1_C1 :
+{0x955A,0x0000,0x02},
+{0x955C,0x001A,0x02},    // AP_N_LD_HIGH_SLOPE1_C2 :
+{0x955E,0x0000,0x02},
+{0x9560,0x0000,0x02},    // AP_N_LD_HIGH_SLOPE2_A : <<N´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡2ì¤Ë½ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x9562,0x0000,0x02},
+{0x9564,0x0005,0x02},    // AP_N_LD_HIGH_SLOPE2_B :
+{0x9566,0x0000,0x02},
+{0x9568,0x0014,0x02},    // AP_N_LD_HIGH_SLOPE2_C1 :
+{0x956A,0x0000,0x02},
+{0x956C,0x0014,0x02},    // AP_N_LD_HIGH_SLOPE2_C2 :
+{0x956E,0x0000,0x02},
+{0x9570,0x0000,0x02},    // AP_H_LD_DARK_SLOPE_A : <<H´ë¿ª LevelDepend ÀúÈÖµµÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x9572,0x0000,0x02},
+{0x9574,0x0000,0x02},    // AP_H_LD_DARK_SLOPE_B :
+{0x9576,0x0000,0x02},
+{0x9578,0x0000,0x02},    // AP_H_LD_DARK_SLOPE_C1 :
+{0x957A,0x0000,0x02},
+{0x957C,0x0000,0x02},    // AP_H_LD_DARK_SLOPE_C2 :
+{0x957E,0x0000,0x02},
+{0x9580,0x0025,0x02},    // AP_H_LD_HIGH_SLOPE0_A : <<H´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡0¢¦ÀÓ°èÄ¡1¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x9582,0x0000,0x02},
+{0x9584,0x0025,0x02},    // AP_H_LD_HIGH_SLOPE0_B :
+{0x9586,0x0000,0x02},
+{0x9588,0x0064,0x02},    // AP_H_LD_HIGH_SLOPE0_C1 :
+{0x958A,0x0000,0x02},
+{0x958C,0x004D,0x02},    // AP_H_LD_HIGH_SLOPE0_C2 :
+{0x958E,0x0000,0x02},
+{0x9590,0x0050,0x02},    // AP_H_LD_HIGH_SLOPE1_A : <<H´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡1¢¦ÀÓ°èÄ¡2¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x9592,0x0000,0x02},
+{0x9594,0x0050,0x02},    // AP_H_LD_HIGH_SLOPE1_B :
+{0x9596,0x0000,0x02},
+{0x9598,0x0004,0x02},    // AP_H_LD_HIGH_SLOPE1_C1 :
+{0x959A,0x0000,0x02},
+{0x959C,0x000C,0x02},    // AP_H_LD_HIGH_SLOPE1_C2 :
+{0x959E,0x0000,0x02},
+{0x95A0,0x0000,0x02},    // AP_H_LD_HIGH_SLOPE2_A : <<H´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡2ì¤Ë½ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x95A2,0x0000,0x02},
+{0x95A4,0x0000,0x02},    // AP_H_LD_HIGH_SLOPE2_B :
+{0x95A6,0x0000,0x02},
+{0x95A8,0x000D,0x02},    // AP_H_LD_HIGH_SLOPE2_C1 :
+{0x95AA,0x0000,0x02},
+{0x95AC,0x000D,0x02},    // AP_H_LD_HIGH_SLOPE2_C2 :
+{0x95AE,0x0000,0x02},
+{0x95B0,0x0000,0x02},    // AP_L_LD_DARK_SLOPE_A : <<L´ë¿ª LevelDepend ÀúÈÖµµÂÊ ±â¿ï±â A¼³Á¤°ª
+{0x95B2,0x0000,0x02},
+{0x95B4,0x0000,0x02},    // AP_L_LD_DARK_SLOPE_B :
+{0x95B6,0x0000,0x02},
+{0x95B8,0x0000,0x02},    // AP_L_LD_DARK_SLOPE_C1 :
+{0x95BA,0x0000,0x02},
+{0x95BC,0x0000,0x02},    // AP_L_LD_DARK_SLOPE_C2 :
+{0x95BE,0x0000,0x02},
+{0x95C0,0x0020,0x02},    // AP_L_LD_HIGH_SLOPE0_A : <<L´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡0¢¦ÀÓ°èÄ¡1¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤
+{0x95C2,0x0000,0x02},
+{0x95C4,0x0023,0x02},    // AP_L_LD_HIGH_SLOPE0_B :
+{0x95C6,0x0000,0x02},
+{0x95C8,0x012C,0x02},    // AP_L_LD_HIGH_SLOPE0_C1 :
+{0x95CA,0x0000,0x02},
+{0x95CC,0x012C,0x02},    // AP_L_LD_HIGH_SLOPE0_C2 :
+{0x95CE,0x0000,0x02},
+{0x95D0,0x0051,0x02},    // AP_L_LD_HIGH_SLOPE1_A : <<L´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡1¢¦ÀÓ°èÄ¡2¿¡¼­ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x95D2,0x0000,0x02},
+{0x95D4,0x0050,0x02},    // AP_L_LD_HIGH_SLOPE1_B :
+{0x95D6,0x0000,0x02},
+{0x95D8,0x0058,0x02},    // AP_L_LD_HIGH_SLOPE1_C1 :
+{0x95DA,0x0000,0x02},
+{0x95DC,0x0058,0x02},    // AP_L_LD_HIGH_SLOPE1_C2 :
+{0x95DE,0x0000,0x02},
+{0x95E0,0x0000,0x02},    // AP_L_LD_HIGH_SLOPE2_A : <<L´ë¿ª LevelDepend °íÈÖµµÂÊ ÀÓ°èÄ¡2ì¤Ë½ÀÇ ±â¿ï±â A¼³Á¤°ª
+{0x95E2,0x0000,0x02},
+{0x95E4,0x0050,0x02},    // AP_L_LD_HIGH_SLOPE2_B :
+{0x95E6,0x0000,0x02},
+{0x95E8,0x002A,0x02},    // AP_L_LD_HIGH_SLOPE2_C1 :
+{0x95EA,0x0000,0x02},
+{0x95EC,0x002A,0x02},    // AP_L_LD_HIGH_SLOPE2_C2 :
+{0x95EE,0x0000,0x02},
+
+//C-sup tuning
+{0x6C47,0x0F,0x01},    // MAIN_CONFIG2 :
+{0x6C48,0x03,0x01},    // MAIN_CONFIG3 :
+{0x9805,0x0A,0x01},    // CS_SLP_C_A :
+{0x9806,0x0A,0x01},    // CS_SLP_C_B :
+{0x9807,0x0A,0x01},    // CS_SLP_C_C :
+{0x9808,0x20,0x01},    // CS_SLP_YC_A :
+{0x9809,0x20,0x01},    // CS_SLP_YC_B :
+{0x980A,0x20,0x01},    // CS_SLP_YC_C :
+{0x980B,0x20,0x01},    // CS_SLP_Y_A :
+{0x980C,0x20,0x01},    // CS_SLP_Y_B :
+{0x980D,0x20,0x01},    // CS_SLP_Y_C :
+{0x980E,0x14,0x01},    // CS_CBHLEV_A :
+{0x980F,0x14,0x01},    // CS_CBHLEV_B :
+{0x9810,0x14,0x01},    // CS_CBHLEV_C :
+{0x9811,0x14,0x01},    // CS_CRHLEV_A :
+{0x9812,0x14,0x01},    // CS_CRHLEV_B :
+{0x9813,0x14,0x01},    // CS_CRHLEV_C :
+{0x9802,0x77,0x01},    // CS_YHCOEF_A :
+{0x9803,0x77,0x01},    // CS_YHCOEF_B :
+{0x9804,0x77,0x01},    // CS_YHCOEF_C :
+{0x9808,0x20,0x01},    // CS_SLP_YC_A :
+{0x9809,0x20,0x01},    // CS_SLP_YC_B :
+{0x980A,0x20,0x01},    // CS_SLP_YC_C :
+{0x980B,0x20,0x01},    // CS_SLP_Y_A :
+{0x980C,0x20,0x01},    // CS_SLP_Y_B :
+{0x980D,0x20,0x01},    // CS_SLP_Y_C :
+{0x9814,0x14,0x01},    // CS_CBHLEV_Y_A :
+{0x9815,0x14,0x01},    // CS_CBHLEV_Y_B :
+{0x9816,0x14,0x01},    // CS_CBHLEV_Y_C :
+{0x9817,0x00,0x01},    // CS_CRHLEV_Y_A :
+{0x9818,0x00,0x01},    // CS_CRHLEV_Y_B :
+{0x9819,0x00,0x01},    // CS_CRHLEV_Y_C :
+{0x9836,0x0000,0x02},    // CS_CBLLEV_Y_A :
+{0x9838,0x0000,0x02},    // CS_CBLLEV_Y_B :
+{0x983A,0x0000,0x02},    // CS_CBLLEV_Y_C :
+{0x983C,0xFFEC,0x02},    // CS_CRLLEV_Y_A :
+{0x983E,0xFFEC,0x02},    // CS_CRLLEV_Y_B :
+{0x9840,0xFFEC,0x02},    // CS_CRLLEV_Y_C :
+{0x981A,0x03,0x01},    // CS_SLP_YC_L_A :
+{0x981B,0x03,0x01},    // CS_SLP_YC_L_B :
+{0x981C,0x03,0x01},    // CS_SLP_YC_L_C :
+{0x981D,0x32,0x01},    // CS_SLP_Y_L_A :
+{0x981E,0x20,0x01},    // CS_SLP_Y_L_B :
+{0x981F,0x20,0x01},    // CS_SLP_Y_L_C :
+{0x9820,0x1E,0x01},    // CS_YLCOEF_A :
+{0x9821,0x1E,0x01},    // CS_YLCOEF_B :
+{0x9822,0x1E,0x01},    // CS_YLCOEF_C :
+{0x9823,0x32,0x01},    // CS_CBHLEV_Y_L_A :
+{0x9824,0x32,0x01},    // CS_CBHLEV_Y_L_B :
+{0x9825,0x32,0x01},    // CS_CBHLEV_Y_L_C :
+{0x9826,0x32,0x01},    // CS_CRHLEV_Y_L_A :
+{0x9827,0x32,0x01},    // CS_CRHLEV_Y_L_B :
+{0x9828,0x32,0x01},    // CS_CRHLEV_Y_L_C :
+{0x982A,0xFFEC,0x02},    // CS_CBLLEV_A :
+{0x982C,0xFFEC,0x02},    // CS_CBLLEV_B :
+{0x982E,0xFFEC,0x02},    // CS_CBLLEV_C :
+{0x9830,0xFFEC,0x02},    // CS_CRLLEV_A :
+{0x9832,0xFFEC,0x02},    // CS_CRLLEV_B :
+{0x9834,0xFFEC,0x02},    // CS_CRLLEV_C :
+{0x9836,0x0000,0x02},    // CS_CBLLEV_Y_A :
+{0x9838,0x0000,0x02},    // CS_CBLLEV_Y_B :
+{0x983A,0x0000,0x02},    // CS_CBLLEV_Y_C :
+{0x983C,0xFFEC,0x02},    // CS_CRLLEV_Y_A :
+{0x983E,0xFFEC,0x02},    // CS_CRLLEV_Y_B :
+{0x9840,0xFFEC,0x02},    // CS_CRLLEV_Y_C :
+{0x9842,0xFFCE,0x02},    // CS_CBLLEV_Y_L_A :
+{0x9844,0xFFCE,0x02},    // CS_CBLLEV_Y_L_B :
+{0x9846,0xFFCE,0x02},    // CS_CBLLEV_Y_L_C :
+{0x9848,0xFFCE,0x02},    // CS_CRLLEV_Y_L_A :
+{0x984A,0xFFCE,0x02},    // CS_CRLLEV_Y_L_B :
+{0x984C,0xFFCE,0x02},    // CS_CRLLEV_Y_L_C :
+
+//CNR°ü·Ã
+{0x6C4A,0x07,0x01},    // MAIN_CONFIG5 :
+{0x6C4C,0x190A,0x02},    // CNR_CTRL_TH_H :
+{0x6C4E,0x1000,0x02},    // CNR_CTRL_TH_L :
+{0x9866,0x40,0x01},    // CNR_PREHNR_GAIN_A :
+{0x9867,0x00,0x01},    // CNR_PREHNR_GAIN_B :
+{0x9868,0x00,0x01},    // CNR_PREHNR_GAIN_C :
+{0x9869,0x32,0x01},    // CNR_NLM_TH_CR_H_A :
+{0x986A,0x04,0x01},    // CNR_NLM_TH_CR_H_B :
+{0x986B,0x0E,0x01},    // CNR_NLM_TH_CR_H_C :
+{0x986C,0x32,0x01},    // CNR_NLM_TH_CR_L_A :
+{0x986D,0x04,0x01},    // CNR_NLM_TH_CR_L_B :
+{0x986E,0x0E,0x01},    // CNR_NLM_TH_CR_L_C :
+{0x986F,0x32,0x01},    // CNR_NLM_TH_CR_M_H_A :
+{0x9870,0x04,0x01},    // CNR_NLM_TH_CR_M_H_B :
+{0x9871,0x0E,0x01},    // CNR_NLM_TH_CR_M_H_C :
+{0x9872,0x32,0x01},    // CNR_NLM_TH_CR_M_L_A :
+{0x9873,0x04,0x01},    // CNR_NLM_TH_CR_M_L_B :
+{0x9874,0x0E,0x01},    // CNR_NLM_TH_CR_M_L_C :
+{0x9875,0x32,0x01},    // CNR_NLM_TH_CB_H_A :
+{0x9876,0x04,0x01},    // CNR_NLM_TH_CB_H_B :
+{0x9877,0x0E,0x01},    // CNR_NLM_TH_CB_H_C :
+{0x9878,0x32,0x01},    // CNR_NLM_TH_CB_L_A :
+{0x9879,0x04,0x01},    // CNR_NLM_TH_CB_L_B :
+{0x987A,0x0E,0x01},    // CNR_NLM_TH_CB_L_C :
+{0x987B,0x32,0x01},    // CNR_NLM_TH_CB_M_H_A :
+{0x987C,0x04,0x01},    // CNR_NLM_TH_CB_M_H_B :
+{0x987D,0x0E,0x01},    // CNR_NLM_TH_CB_M_H_C :
+{0x987E,0x32,0x01},    // CNR_NLM_TH_CB_M_L_A :
+{0x987F,0x04,0x01},    // CNR_NLM_TH_CB_M_L_B :
+{0x9880,0x0E,0x01},    // CNR_NLM_TH_CB_M_L_C :
+{0x9881,0x7F,0x01},    // CNR_VE_TH_CR_H_A :
+{0x9882,0x01,0x01},    // CNR_VE_TH_CR_H_B :
+{0x9883,0x04,0x01},    // CNR_VE_TH_CR_H_C :
+{0x9884,0x7F,0x01},    // CNR_VE_TH_CR_L_A :
+{0x9885,0x01,0x01},    // CNR_VE_TH_CR_L_B :
+{0x9886,0x04,0x01},    // CNR_VE_TH_CR_L_C :
+{0x9887,0x7F,0x01},    // CNR_VE_TH_CR_M_H_A :
+{0x9888,0x01,0x01},    // CNR_VE_TH_CR_M_H_B :
+{0x9889,0x04,0x01},    // CNR_VE_TH_CR_M_H_C :
+{0x988A,0x7F,0x01},    // CNR_VE_TH_CR_M_L_A :
+{0x988B,0x01,0x01},    // CNR_VE_TH_CR_M_L_B :
+{0x988C,0x04,0x01},    // CNR_VE_TH_CR_M_L_C :
+{0x988D,0x7F,0x01},    // CNR_VE_TH_CB_H_A :
+{0x988E,0x01,0x01},    // CNR_VE_TH_CB_H_B :
+{0x988F,0x04,0x01},    // CNR_VE_TH_CB_H_C :
+{0x9890,0x7F,0x01},    // CNR_VE_TH_CB_L_A :
+{0x9891,0x01,0x01},    // CNR_VE_TH_CB_L_B :
+{0x9892,0x04,0x01},    // CNR_VE_TH_CB_L_C :
+{0x9893,0x7F,0x01},    // CNR_VE_TH_CB_M_H_A :
+{0x9894,0x01,0x01},    // CNR_VE_TH_CB_M_H_B :
+{0x9895,0x04,0x01},    // CNR_VE_TH_CB_M_H_C :
+{0x9896,0x7F,0x01},    // CNR_VE_TH_CB_M_L_A :
+{0x9897,0x01,0x01},    // CNR_VE_TH_CB_M_L_B :
+{0x9898,0x04,0x01},    // CNR_VE_TH_CB_M_L_C :
+{0x9881,0x7F,0x01},    // CNR_VE_TH_CR_H_A :
+{0x9882,0x01,0x01},    // CNR_VE_TH_CR_H_B :
+{0x9883,0x04,0x01},    // CNR_VE_TH_CR_H_C :
+{0x9884,0x7F,0x01},    // CNR_VE_TH_CR_L_A :
+{0x9885,0x01,0x01},    // CNR_VE_TH_CR_L_B :
+{0x9886,0x04,0x01},    // CNR_VE_TH_CR_L_C :
+{0x9887,0x7F,0x01},    // CNR_VE_TH_CR_M_H_A :
+{0x9888,0x01,0x01},    // CNR_VE_TH_CR_M_H_B :
+{0x9889,0x04,0x01},    // CNR_VE_TH_CR_M_H_C :
+{0x988A,0x7F,0x01},    // CNR_VE_TH_CR_M_L_A :
+{0x988B,0x01,0x01},    // CNR_VE_TH_CR_M_L_B :
+{0x988C,0x04,0x01},    // CNR_VE_TH_CR_M_L_C :
+{0x988D,0x7F,0x01},    // CNR_VE_TH_CB_H_A :
+{0x988E,0x01,0x01},    // CNR_VE_TH_CB_H_B :
+{0x988F,0x04,0x01},    // CNR_VE_TH_CB_H_C :
+{0x9890,0x7F,0x01},    // CNR_VE_TH_CB_L_A :
+{0x9891,0x01,0x01},    // CNR_VE_TH_CB_L_B :
+{0x9892,0x04,0x01},    // CNR_VE_TH_CB_L_C :
+{0x9893,0x7F,0x01},    // CNR_VE_TH_CB_M_H_A :
+{0x9894,0x01,0x01},    // CNR_VE_TH_CB_M_H_B :
+{0x9895,0x04,0x01},    // CNR_VE_TH_CB_M_H_C :
+{0x9896,0x7F,0x01},    // CNR_VE_TH_CB_M_L_A :
+{0x9897,0x01,0x01},    // CNR_VE_TH_CB_M_L_B :
+{0x9898,0x04,0x01},    // CNR_VE_TH_CB_M_L_C :
+{0x989A,0x0066,0x02},    // CNR_COEF_CR_H_A :
+{0x989C,0x0100,0x02},    // CNR_COEF_CR_H_B :
+{0x989E,0x0100,0x02},    // CNR_COEF_CR_H_C :
+{0x98A0,0x0066,0x02},    // CNR_COEF_CR_L_A :
+{0x98A2,0x0100,0x02},    // CNR_COEF_CR_L_B :
+{0x98A4,0x0100,0x02},    // CNR_COEF_CR_L_C :
+{0x98A6,0x0066,0x02},    // CNR_COEF_CR_M_H_A :
+{0x98A8,0x0100,0x02},    // CNR_COEF_CR_M_H_B :
+{0x98AA,0x0100,0x02},    // CNR_COEF_CR_M_H_C :
+{0x98AC,0x0066,0x02},    // CNR_COEF_CR_M_L_A :
+{0x98AE,0x0100,0x02},    // CNR_COEF_CR_M_L_B :
+{0x98B0,0x0100,0x02},    // CNR_COEF_CR_M_L_C :
+{0x98B2,0x0066,0x02},    // CNR_COEF_CB_H_A :
+{0x98B4,0x0100,0x02},    // CNR_COEF_CB_H_B :
+{0x98B6,0x0100,0x02},    // CNR_COEF_CB_H_C :
+{0x98B8,0x0066,0x02},    // CNR_COEF_CB_L_A :
+{0x98BA,0x0100,0x02},    // CNR_COEF_CB_L_B :
+{0x98BC,0x0100,0x02},    // CNR_COEF_CB_L_C :
+{0x98BE,0x0066,0x02},    // CNR_COEF_CB_M_H_A :
+{0x98C0,0x0100,0x02},    // CNR_COEF_CB_M_H_B :
+{0x98C2,0x0100,0x02},    // CNR_COEF_CB_M_H_C :
+{0x98C4,0x0066,0x02},    // CNR_COEF_CB_M_L_A :
+{0x98C6,0x0100,0x02},    // CNR_COEF_CB_M_L_B :
+{0x98C8,0x0100,0x02},    // CNR_COEF_CB_M_L_C :
+{0x98CA,0x1770,0x02},    // CNR_EDGE_GAIN_CR_H_A :
+{0x98CC,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_H_B :
+{0x98CE,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_H_C :
+{0x98D0,0x1770,0x02},    // CNR_EDGE_GAIN_CR_L_A :
+{0x98D2,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_L_B :
+{0x98D4,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_L_C :
+{0x98D6,0x1770,0x02},    // CNR_EDGE_GAIN_CR_M_H_A :
+{0x98D8,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_M_H_B :
+{0x98DA,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_M_H_C :
+{0x98DC,0x1770,0x02},    // CNR_EDGE_GAIN_CR_M_L_A :
+{0x98DE,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_M_L_B :
+{0x98E0,0x07D0,0x02},    // CNR_EDGE_GAIN_CR_M_L_C :
+{0x98E2,0x1770,0x02},    // CNR_EDGE_GAIN_CB_H_A :
+{0x98E4,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_H_B :
+{0x98E6,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_H_C :
+{0x98E8,0x1770,0x02},    // CNR_EDGE_GAIN_CB_L_A :
+{0x98EA,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_L_B :
+{0x98EC,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_L_C :
+{0x98EE,0x1770,0x02},    // CNR_EDGE_GAIN_CB_M_H_A :
+{0x98F0,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_M_H_B :
+{0x98F2,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_M_H_C :
+{0x98F4,0x1770,0x02},    // CNR_EDGE_GAIN_CB_M_L_A :
+{0x98F6,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_M_L_B :
+{0x98F8,0x07D0,0x02},    // CNR_EDGE_GAIN_CB_M_L_C :
+{0x98FA,0x7530,0x02},    // CNR_EDGE_TH_CR_H_A :
+{0x98FC,0x0000,0x02},    // CNR_EDGE_TH_CR_H_B :
+{0x98FE,0x0000,0x02},    // CNR_EDGE_TH_CR_H_C :
+{0x9900,0x7530,0x02},    // CNR_EDGE_TH_CR_L_A :
+{0x9902,0x0000,0x02},    // CNR_EDGE_TH_CR_L_B :
+{0x9904,0x0000,0x02},    // CNR_EDGE_TH_CR_L_C :
+{0x9906,0x7530,0x02},    // CNR_EDGE_TH_CR_M_H_A :
+{0x9908,0x0000,0x02},    // CNR_EDGE_TH_CR_M_H_B :
+{0x990A,0x0000,0x02},    // CNR_EDGE_TH_CR_M_H_C :
+{0x990C,0x7530,0x02},    // CNR_EDGE_TH_CR_M_L_A :
+{0x990E,0x0000,0x02},    // CNR_EDGE_TH_CR_M_L_B :
+{0x9910,0x0000,0x02},    // CNR_EDGE_TH_CR_M_L_C :
+{0x9912,0x7530,0x02},    // CNR_EDGE_TH_CB_H_A :
+{0x9914,0x0000,0x02},    // CNR_EDGE_TH_CB_H_B :
+{0x9916,0x0000,0x02},    // CNR_EDGE_TH_CB_H_C :
+{0x9918,0x7530,0x02},    // CNR_EDGE_TH_CB_L_A :
+{0x991A,0x0000,0x02},    // CNR_EDGE_TH_CB_L_B :
+{0x991C,0x0000,0x02},    // CNR_EDGE_TH_CB_L_C :
+{0x991E,0x7530,0x02},    // CNR_EDGE_TH_CB_M_H_A :
+{0x9920,0x0000,0x02},    // CNR_EDGE_TH_CB_M_H_B :
+{0x9922,0x0000,0x02},    // CNR_EDGE_TH_CB_M_H_C :
+{0x9924,0x7530,0x02},    // CNR_EDGE_TH_CB_M_L_A :
+{0x9926,0x0000,0x02},    // CNR_EDGE_TH_CB_M_L_B :
+{0x9928,0x0000,0x02},    // CNR_EDGE_TH_CB_M_L_C :
+
+//ITP NR°ü·Ã
+{0x5005,0xBB,0x01},    // DM_SW1 :
+{0x5006,0x03,0x01},    // DM_SW2 :
+{0x9608,0x0000,0x02},    // DS_GRADCORE_A :
+{0x960A,0x0004,0x02},    // DS_GRADCORE_B :
+{0x960C,0x0000,0x02},    // DS_GRADCORE_C1 :
+{0x960E,0x0000,0x02},    // DS_GRADCORE_C2 :
+{0x9610,0x000A,0x02},    // DS_GRADLIM_A :
+{0x9612,0x0019,0x02},    // DS_GRADLIM_B :
+{0x9614,0x0020,0x02},    // DS_GRADLIM_C1 :
+{0x9616,0x0020,0x02},    // DS_GRADLIM_C2 :
+{0x9600,0x0080,0x02},    // DS_NOISELVL_A :
+{0x9602,0x0039,0x02},    // DS_NOISELVL_B :
+{0x9604,0x0030,0x02},    // DS_NOISELVL_C1 :
+{0x9606,0x0030,0x02},    // DS_NOISELVL_C2
+{0x9670,0x14,0x01},    // YN_SLOPELIMIT_A :
+{0x9671,0x20,0x01},    // YN_SLOPELIMIT_B :
+{0x9672,0x20,0x01},    // YN_SLOPELIMIT_C1 :
+{0x9673,0x20,0x01},    // YN_SLOPELIMIT_C2 :
+{0x9674,0x0032,0x02},    // YN_LNRTH_CORE_A :
+{0x9676,0x0006,0x02},    // YN_LNRTH_CORE_B :
+{0x9678,0x0003,0x02},    // YN_LNRTH_CORE_C1 :
+{0x967A,0x0003,0x02},    // YN_LNRTH_CORE_C2 :
+{0x967C,0x0032,0x02},    // YN_LNRTH_LIM_A :
+{0x967E,0x0058,0x02},    // YN_LNRTH_LIM_B :
+{0x9680,0x00A0,0x02},    // YN_LNRTH_LIM_C1 :
+{0x9682,0x00A0,0x02},    // YN_LNRTH_LIM_C2 :
+{0x9684,0x000F,0x02},    // LN_CNRTH_A :
+{0x9686,0x0014,0x02},    // LN_CNRTH_B :
+{0x9688,0x0014,0x02},    // LN_CNRTH_C1 :
+{0x968A,0x0014,0x02},    // LN_CNRTH_C2 :
+{0x968C,0x0100,0x02},    // CS_BLEND_LL_A :
+{0x968E,0x0000,0x02},    // CS_BLEND_LL_B :
+{0x9690,0x03FF,0x02},    // CS_BLEND_LL_C1 :
+{0x9692,0x03FF,0x02},    // CS_BLEND_LL_C2 :
+{0x9628,0x0008,0x02},    // DS_HLNLBLENDCORE_A :
+{0x962A,0x0003,0x02},    // DS_HLNLBLENDCORE_B :
+{0x962C,0x0000,0x02},    // DS_HLNLBLENDCORE_C1 :
+{0x962E,0x0000,0x02},    // DS_HLNLBLENDCORE_C2 :
+{0x9630,0x0018,0x02},    // DS_HLNLBLENDLIM_A :
+{0x9632,0x0024,0x02},    // DS_HLNLBLENDLIM_B :
+{0x9634,0x0028,0x02},    // DS_HLNLBLENDLIM_C1 :
+{0x9636,0x0028,0x02},    // DS_HLNLBLENDLIM_C2 :
+{0x9638,0x0000,0x02},    // DS_MNBLENDCORE_A :
+{0x963A,0x000C,0x02},    // DS_MNBLENDCORE_B :
+{0x963C,0x0000,0x02},    // DS_MNBLENDCORE_C1 :
+{0x963E,0x0000,0x02},    // DS_MNBLENDCORE_C2 :
+{0x9640,0x0020,0x02},    // DS_MNBLENDLIM_A :
+{0x9642,0x0030,0x02},    // DS_MNBLENDLIM_B :
+{0x9644,0x0080,0x02},    // DS_MNBLENDLIM_C1 :
+{0x9646,0x0080,0x02},    // DS_MNBLENDLIM_C2 :
+{0x9648,0x0008,0x02},    // DS_MHBLENDCORE_A :
+{0x964A,0x0005,0x02},    // DS_MHBLENDCORE_B :
+{0x964C,0x0001,0x02},    // DS_MHBLENDCORE_C1 :
+{0x964E,0x0001,0x02},    // DS_MHBLENDCORE_C2 :
+{0x9650,0x0018,0x02},    // DS_MHBLENDLIM_A :
+{0x9652,0x0041,0x02},    // DS_MHBLENDLIM_B :
+{0x9654,0x005A,0x02},    // DS_MHBLENDLIM_C1 :
+{0x9656,0x0050,0x02},    // DS_MHBLENDLIM_C2 :
+{0x9668,0x0008,0x02},    // DS_NAPMSKLIM_A :
+{0x966A,0x0010,0x02},    // DS_NAPMSKLIM_B :
+{0x966C,0x0018,0x02},    // DS_NAPMSKLIM_C1 :
+{0x966E,0x0018,0x02},    // DS_NAPMSKLIM_C2 :
+{0x9618,0x0018,0x02},    // DS_ZIPSUPCORE_A :
+{0x961A,0x0018,0x02},    // DS_ZIPSUPCORE_B :
+{0x961C,0x0004,0x02},    // DS_ZIPSUPCORE_C1 :
+{0x961E,0x0004,0x02},    // DS_ZIPSUPCORE_C2 :
+{0x9620,0x0010,0x02},    // DS_ZIPSUPLIM_A :
+{0x9622,0x0010,0x02},    // DS_ZIPSUPLIM_B :
+{0x9624,0x0010,0x02},    // DS_ZIPSUPLIM_C1 :
+{0x9626,0x0010,0x02},    // DS_ZIPSUPLIM_C2 :
+{0x9658,0x0020,0x02},    // DS_ICDCORE_A :
+{0x965A,0x0010,0x02},    // DS_ICDCORE_B :
+{0x965C,0x0000,0x02},    // DS_ICDCORE_C1 :
+{0x965E,0x0000,0x02},    // DS_ICDCORE_C2 :
+{0x9660,0x0020,0x02},    // DS_ICDLIM_A :
+{0x9662,0x0040,0x02},    // DS_ICDLIM_B :
+{0x9664,0x0040,0x02},    // DS_ICDLIM_C1 :
+{0x9666,0x0040,0x02},    // DS_ICDLIM_C2 :
+{0x9694,0x000C,0x02},    // CS_EDGE_CSUP_CORE_A :
+{0x9696,0x000C,0x02},    // CS_EDGE_CSUP_CORE_B :
+{0x9698,0x000C,0x02},    // CS_EDGE_CSUP_CORE_C1 :
+{0x969A,0x0006,0x02},    // CS_EDGE_CSUP_CORE_C2 :
+{0x969C,0x000C,0x02},    // CS_EDGE_CSUP_LIM_A :
+{0x969E,0x000C,0x02},    // CS_EDGE_CSUP_LIM_B :
+{0x96A0,0x0010,0x02},    // CS_EDGE_CSUP_LIM_C1 :
+{0x96A2,0x0008,0x02},    // CS_EDGE_CSUP_LIM_C2 :
+{0x96A4,0x0180,0x02},    // CS_SPOT_CSUP_CORE_A :
+{0x96A6,0x0180,0x02},    // CS_SPOT_CSUP_CORE_B :
+{0x96A8,0x0100,0x02},    // CS_SPOT_CSUP_CORE_C1 :
+{0x96AA,0x0100,0x02},    // CS_SPOT_CSUP_CORE_C2 :
+{0x96AC,0x000A,0x02},    // CS_SPOT_CSUP_LIM_A :
+{0x96AE,0x000A,0x02},    // CS_SPOT_CSUP_LIM_B :
+{0x96B0,0x0018,0x02},    // CS_SPOT_CSUP_LIM_C1 :
+{0x96B2,0x0018,0x02},    // CS_SPOT_CSUP_LIM_C2 :
+
+//LMT Á¶µµ¿¬µ¿ Blend °ü·Ã
+{0x9800,0x40,0x01},    //
+{0x9801,0x80,0x01},    //
+
+//°ÔÀוּ¿ Type ¼³Á¤ °ü·Ã
+{0x9217,0x3C,0x01},    // GAIN_TH_A_TYPE5 :
+{0x9218,0x28,0x01},    // GAIN_TH_B_TYPE5 :
+{0x9219,0x1E,0x01},    // GAIN_TH_C_TYPE5 :
+
+//CNR Á¶µµ¿¬µ¿ °ü·Ã
+{0x928F,0x05,0x01},    // CNR_PREHNR_GAIN_SEL :
+{0x9290,0x05,0x01},    // CNR_NLM_TH_CR_H_SEL :
+{0x9291,0x05,0x01},    // CNR_NLM_TH_CR_L_SEL :
+{0x9292,0x05,0x01},    // CNR_NLM_TH_CR_M_H_SEL :
+{0x9293,0x05,0x01},    // CNR_NLM_TH_CR_M_L_SEL :
+{0x9294,0x05,0x01},    // CNR_NLM_TH_CB_H_SEL :
+{0x9295,0x05,0x01},    // CNR_NLM_TH_CB_L_SEL :
+{0x9296,0x05,0x01},    // CNR_NLM_TH_CB_M_H_SEL :
+{0x9297,0x05,0x01},    // CNR_NLM_TH_CB_M_L_SEL :
+{0x9298,0x05,0x01},    // CNR_VE_TH_CR_H_SEL :
+{0x9299,0x05,0x01},    // CNR_VE_TH_CR_L_SEL :
+{0x929A,0x05,0x01},    // CNR_VE_TH_CR_M_H_SEL :
+{0x929B,0x05,0x01},    // CNR_VE_TH_CR_M_L_SEL :
+{0x929C,0x05,0x01},    // CNR_VE_TH_CB_H_SEL :
+{0x929D,0x05,0x01},    // CNR_VE_TH_CB_L_SEL :
+{0x929E,0x05,0x01},    // CNR_VE_TH_CB_M_H_SEL :
+{0x929F,0x05,0x01},    // CNR_VE_TH_CB_M_L_SEL :
+{0x92A0,0x05,0x01},    // CNR_COEF_CR_H_SEL :
+{0x92A1,0x05,0x01},    // CNR_COEF_CR_L_SEL :
+{0x92A2,0x05,0x01},    // CNR_COEF_CR_M_H_SEL :
+{0x92A3,0x05,0x01},    // CNR_COEF_CR_M_L_SEL :
+{0x92A4,0x05,0x01},    // CNR_COEF_CB_H_SEL :
+{0x92A5,0x05,0x01},    // CNR_COEF_CB_L_SEL :
+{0x92A6,0x05,0x01},    // CNR_COEF_CB_M_H_SEL :
+{0x92A7,0x05,0x01},    // CNR_COEF_CB_M_L_SEL :
+{0x92A8,0x05,0x01},    // CNR_EDGE_GAIN_CR_H_SEL :
+{0x92A9,0x05,0x01},    // CNR_EDGE_GAIN_CR_L_SEL :
+{0x92AA,0x05,0x01},    // CNR_EDGE_GAIN_CR_M_H_SEL :
+{0x92AB,0x05,0x01},    // CNR_EDGE_GAIN_CR_M_L_SEL :
+{0x92AC,0x05,0x01},    // CNR_EDGE_GAIN_CB_H_SEL :
+{0x92AD,0x05,0x01},    // CNR_EDGE_GAIN_CB_L_SEL :
+{0x92AE,0x05,0x01},    // CNR_EDGE_GAIN_CB_M_H_SEL :
+{0x92AF,0x05,0x01},    // CNR_EDGE_GAIN_CB_M_L_SEL :
+{0x92B0,0x05,0x01},    // CNR_EDGE_TH_CR_H_SEL :
+{0x92B1,0x05,0x01},    // CNR_EDGE_TH_CR_L_SEL :
+{0x92B2,0x05,0x01},    // CNR_EDGE_TH_CR_M_H_SEL :
+{0x92B3,0x05,0x01},    // CNR_EDGE_TH_CR_M_L_SEL :
+{0x92B4,0x05,0x01},    // CNR_EDGE_TH_CB_H_SEL :
+{0x92B5,0x05,0x01},    // CNR_EDGE_TH_CB_L_SEL :
+{0x92B6,0x05,0x01},    // CNR_EDGE_TH_CB_M_H_SEL :
+{0x92B7,0x05,0x01},    // CNR_EDGE_TH_CB_M_L_SEL :
+
+////////////////MWB & AWB Æ©´×////////////
+{0x6244,0x0B81,0x02},    // USER0R :
+{0x6246,0x1832,0x02},    // USER0B :
+{0x6248,0x09C8,0x02},    // USER1R : Daylight
+{0x624A,0x1A06,0x02},    // USER1B :
+{0x624C,0x09C8,0x02},    // USER2R : Cloudy
+{0x624E,0x1A06,0x02},    // USER2B :
+{0x6250,0x0D61,0x02},    // USER3R : Fluorescent
+{0x6252,0x1161,0x02},    // USER3B :
+{0x6254,0x130B,0x02},    // USER4R : A
+{0x6256,0x0E92,0x02},    // USER4B :
+
+{0x6270,0xFD92,0x02},    // USER2_CONT_SHIFT_R : Cloudy cont shift
+{0x6272,0x0388,0x02},    // USER2_CONT_SHIFT_B :
+{0x62C6,0x1096,0x02},    // A_LIGHT_R :
+{0x62C8,0x0F26,0x02},    // A_LIGHT_B :
+{0x62CA,0x00B0,0x02},    // A_LIGHT_AIM_SHIFT_R :
+{0x62CC,0x00C0,0x02},    // A_LIGHT_AIM_SHIFT_B :
+{0x62CE,0x04,0x01},    // A_LIGHT_SCOPE_S_UP :
+{0x62CF,0x04,0x01},    // A_LIGHT_SCOPE_S_DOWN :
+{0x62D0,0x04,0x01},    // A_LIGHT_SCOPE_S_RIGHT :
+{0x62D1,0x04,0x01},    // A_LIGHT_SCOPE_S_LEFT :
+{0x62D2,0x14,0x01},    // A_LIGHT_SCOPE_L_UP :
+{0x62D3,0x14,0x01},    // A_LIGHT_SCOPE_L_DOWN :
+{0x62D4,0x14,0x01},    // A_LIGHT_SCOPE_L_RIGHT :
+{0x62D5,0x14,0x01},    // A_LIGHT_SCOPE_L_LEFT :
+{0x62D6,0x1217,0x02},    // H_LIGHT_R :
+{0x62D8,0x0B95,0x02},    // H_LIGHT_B :
+{0x62DA,0xFF7E,0x02},    // H_LIGHT_AIM_SHIFT_R :
+{0x62DC,0xFF36,0x02},    // H_LIGHT_AIM_SHIFT_B :
+{0x62DE,0x04,0x01},    // H_LIGHT_SCOPE_S_UP :
+{0x62DF,0x04,0x01},    // H_LIGHT_SCOPE_S_DOWN :
+{0x62E0,0x04,0x01},    // H_LIGHT_SCOPE_S_RIGHT :
+{0x62E1,0x04,0x01},    // H_LIGHT_SCOPE_S_LEFT :
+{0x62E2,0x14,0x01},    // H_LIGHT_SCOPE_L_UP :
+{0x62E3,0x17,0x01},    // H_LIGHT_SCOPE_L_DOWN :
+{0x62E4,0x26,0x01},    // H_LIGHT_SCOPE_L_RIGHT :
+{0x62E5,0x19,0x01},    // H_LIGHT_SCOPE_L_LEFT :
+
+/////MC3 Setting/////
+{0x7600,0x07,0x01},    // MC3_PXDEF0_SEL :
+{0x7601,0x07,0x01},    // MC3_PYDEF0_SEL :
+{0x7602,0x07,0x01},    // MC3_PXDEF1_SEL :
+{0x7603,0x07,0x01},    // MC3_PYDEF1_SEL :
+{0x7604,0x07,0x01},    // MC3_PXDEF2_SEL :
+{0x7605,0x07,0x01},    // MC3_PYDEF2_SEL :
+{0x7606,0x07,0x01},    // MC3_PXDEF3_SEL :
+{0x7607,0x07,0x01},    // MC3_PYDEF3_SEL :
+{0x7608,0x40,0x01},    // MC3_PXDEF0_A :
+{0x7609,0x40,0x01},    // MC3_PXDEF0_B :
+{0x760A,0x40,0x01},    // MC3_PXDEF0_C :
+{0x760B,0x40,0x01},    // MC3_PYDEF0_A :
+{0x760C,0x40,0x01},    // MC3_PYDEF0_B :
+{0x760D,0x40,0x01},    // MC3_PYDEF0_C :
+{0x760E,0x40,0x01},    // MC3_PXDEF1_A :
+{0x760F,0x40,0x01},    // MC3_PXDEF1_B :
+{0x7610,0x40,0x01},    // MC3_PXDEF1_C :
+{0x7611,0x40,0x01},    // MC3_PYDEF1_A :
+{0x7612,0x40,0x01},    // MC3_PYDEF1_B :
+{0x7613,0x40,0x01},    // MC3_PYDEF1_C :
+{0x7614,0x40,0x01},    // MC3_PXDEF2_A :
+{0x7615,0x40,0x01},    // MC3_PXDEF2_B :
+{0x7616,0x40,0x01},    // MC3_PXDEF2_C :
+{0x7617,0x40,0x01},    // MC3_PYDEF2_A :
+{0x7618,0x40,0x01},    // MC3_PYDEF2_B :
+{0x7619,0x40,0x01},    // MC3_PYDEF2_C :
+{0x761A,0x40,0x01},    // MC3_PXDEF3_A :
+{0x761B,0x40,0x01},    // MC3_PXDEF3_B :
+{0x761C,0x40,0x01},    // MC3_PXDEF3_C :
+{0x761D,0x40,0x01},    // MC3_PYDEF3_A :
+{0x761E,0x40,0x01},    // MC3_PYDEF3_B :
+{0x761F,0x40,0x01},    // MC3_PYDEF3_C :
+{0x7620,0x00,0x01},    // MC3_LUMSL0_IN :
+{0x7621,0x06,0x01},    // MC3_LUMSL1_IN :
+{0x7622,0x03,0x01},    // MC3_LUMSL2_IN :
+{0x7623,0x06,0x01},    // MC3_LUMSL3_IN :
+{0x7624,0x00,0x01},    // MC3_LUMSL0_OUT :
+{0x7625,0x03,0x01},    // MC3_LUMSL1_OUT :
+{0x7626,0x00,0x01},    // MC3_LUMSL2_OUT :
+{0x7627,0x00,0x01},    // MC3_LUMSL3_OUT :
+{0x7628,0x0000,0x02},    // MC3_L0DEF0_IN :
+{0x762A,0x008C,0x02},    // MC3_L0DEF1_IN :
+{0x762C,0x0078,0x02},    // MC3_L0DEF2_IN :
+{0x762E,0x00E6,0x02},    // MC3_L0DEF3_IN :
+{0x7630,0x0000,0x02},    // MC3_L0DEF0_OUT :
+{0x7632,0x0082,0x02},    // MC3_L0DEF1_OUT :
+{0x7634,0x0000,0x02},    // MC3_L0DEF2_OUT :
+{0x7636,0x0000,0x02},    // MC3_L0DEF3_OUT :
+{0x7638,0x41,0x01},    // MC3_RDEF0_POS1 :
+{0x7639,0x10,0x01},    // MC3_RDEF1_POS1 :
+{0x763A,0x15,0x01},    // MC3_RDEF2_POS1 :
+{0x763B,0x71,0x01},    // MC3_RDEF3_POS1 :
+{0x763C,0x41,0x01},    // MC3_RDEF0_POS2 :
+{0x763D,0x10,0x01},    // MC3_RDEF1_POS2 :
+{0x763E,0x15,0x01},    // MC3_RDEF2_POS2 :
+{0x763F,0x71,0x01},    // MC3_RDEF3_POS2 :
+{0x7640,0x3C,0x01},    // MC3_RDEF0_POS3 :
+{0x7641,0x10,0x01},    // MC3_RDEF1_POS3 :
+{0x7642,0x15,0x01},    // MC3_RDEF2_POS3 :
+{0x7643,0x71,0x01},    // MC3_RDEF3_POS3 :
+{0x7644,0x46,0x01},    // MC3_RDEF0_POS4 :
+{0x7645,0x32,0x01},    // MC3_RDEF1_POS4 :
+{0x7646,0x15,0x01},    // MC3_RDEF2_POS4 :
+{0x7647,0x71,0x01},    // MC3_RDEF3_POS4 :
+{0x7648,0x46,0x01},    // MC3_RDEF0_POS5 :
+{0x7649,0x32,0x01},    // MC3_RDEF1_POS5 :
+{0x764A,0x15,0x01},    // MC3_RDEF2_POS5 :
+{0x764B,0x71,0x01},    // MC3_RDEF3_POS5 :
+{0x764C,0x46,0x01},    // MC3_RDEF0_POS6 :
+{0x764D,0x10,0x01},    // MC3_RDEF1_POS6 :
+{0x764E,0x15,0x01},    // MC3_RDEF2_POS6 :
+{0x764F,0x71,0x01},    // MC3_RDEF3_POS6 :
+{0x7650,0x46,0x01},    // MC3_RDEF0_POS7 :
+{0x7651,0x10,0x01},    // MC3_RDEF1_POS7 :
+{0x7652,0x15,0x01},    // MC3_RDEF2_POS7 :
+{0x7653,0x71,0x01},    // MC3_RDEF3_POS7 :
+{0x7654,0x2D,0x01},    // MC3_RDEF0_OUT :
+{0x7655,0x10,0x01},    // MC3_RDEF1_OUT :
+{0x7656,0x15,0x01},    // MC3_RDEF2_OUT :
+{0x7657,0x54,0x01},    // MC3_RDEF3_OUT :
+{0x7658,0x46,0x01},    // MC3_RDEF0_R2_POS4 :
+{0x7659,0x32,0x01},    // MC3_RDEF1_R2_POS4 :
+{0x765A,0x15,0x01},    // MC3_RDEF2_R2_POS4 :
+{0x765B,0x71,0x01},    // MC3_RDEF3_R2_POS4 :
+{0x765C,0x46,0x01},    // MC3_RDEF0_R2_POS5 :
+{0x765D,0x32,0x01},    // MC3_RDEF1_R2_POS5 :
+{0x765E,0x15,0x01},    // MC3_RDEF2_R2_POS5 :
+{0x765F,0x71,0x01},    // MC3_RDEF3_R2_POS5 :
+{0x7660,0xFFBA,0x02},    // MC3_X0DEF0_POS1 :
+{0x7662,0xFFBA,0x02},    // MC3_Y0DEF0_POS1 :
+{0x7664,0xFFFE,0x02},    // MC3_X0DEF1_POS1 :
+{0x7666,0x000D,0x02},    // MC3_Y0DEF1_POS1 :
+{0x7668,0x0002,0x02},    // MC3_X0DEF2_POS1 :
+{0x766A,0xFFF6,0x02},    // MC3_Y0DEF2_POS1 :
+{0x766C,0x003B,0x02},    // MC3_X0DEF3_POS1 :
+{0x766E,0xFFBB,0x02},    // MC3_Y0DEF3_POS1 :
+{0x7670,0xFFBA,0x02},    // MC3_X0DEF0_POS2 :
+{0x7672,0xFFBA,0x02},    // MC3_Y0DEF0_POS2 :
+{0x7674,0xFFFE,0x02},    // MC3_X0DEF1_POS2 :
+{0x7676,0x000D,0x02},    // MC3_Y0DEF1_POS2 :
+{0x7678,0x0002,0x02},    // MC3_X0DEF2_POS2 :
+{0x767A,0xFFF6,0x02},    // MC3_Y0DEF2_POS2 :
+{0x767C,0x003B,0x02},    // MC3_X0DEF3_POS2 :
+{0x767E,0xFFBB,0x02},    // MC3_Y0DEF3_POS2 :
+{0x7680,0xFFCE,0x02},    // MC3_X0DEF0_POS3 :
+{0x7682,0xFFBA,0x02},    // MC3_Y0DEF0_POS3 :
+{0x7684,0xFFFE,0x02},    // MC3_X0DEF1_POS3 :
+{0x7686,0x000D,0x02},    // MC3_Y0DEF1_POS3 :
+{0x7688,0x0002,0x02},    // MC3_X0DEF2_POS3 :
+{0x768A,0xFFF6,0x02},    // MC3_Y0DEF2_POS3 :
+{0x768C,0x003B,0x02},    // MC3_X0DEF3_POS3 :
+{0x768E,0xFFBB,0x02},    // MC3_Y0DEF3_POS3 :
+{0x7690,0xFFCE,0x02},    // MC3_X0DEF0_POS4 :
+{0x7692,0xFFC9,0x02},    // MC3_Y0DEF0_POS4 :
+{0x7694,0xFFD0,0x02},    // MC3_X0DEF1_POS4 :
+{0x7696,0x0037,0x02},    // MC3_Y0DEF1_POS4 :
+{0x7698,0x0002,0x02},    // MC3_X0DEF2_POS4 :
+{0x769A,0xFFF6,0x02},    // MC3_Y0DEF2_POS4 :
+{0x769C,0x003B,0x02},    // MC3_X0DEF3_POS4 :
+{0x769E,0xFFBB,0x02},    // MC3_Y0DEF3_POS4 :
+{0x76A0,0xFFCE,0x02},    // MC3_X0DEF0_POS5 :
+{0x76A2,0xFFC9,0x02},    // MC3_Y0DEF0_POS5 :
+{0x76A4,0xFFD0,0x02},    // MC3_X0DEF1_POS5 :
+{0x76A6,0x0037,0x02},    // MC3_Y0DEF1_POS5 :
+{0x76A8,0x0002,0x02},    // MC3_X0DEF2_POS5 :
+{0x76AA,0xFFF6,0x02},    // MC3_Y0DEF2_POS5 :
+{0x76AC,0x003B,0x02},    // MC3_X0DEF3_POS5 :
+{0x76AE,0xFFBB,0x02},    // MC3_Y0DEF3_POS5 :
+{0x76B0,0xFFCE,0x02},    // MC3_X0DEF0_POS6 :
+{0x76B2,0xFFC9,0x02},    // MC3_Y0DEF0_POS6 :
+{0x76B4,0xFFFE,0x02},    // MC3_X0DEF1_POS6 :
+{0x76B6,0x000D,0x02},    // MC3_Y0DEF1_POS6 :
+{0x76B8,0x0002,0x02},    // MC3_X0DEF2_POS6 :
+{0x76BA,0xFFF6,0x02},    // MC3_Y0DEF2_POS6 :
+{0x76BC,0x003B,0x02},    // MC3_X0DEF3_POS6 :
+{0x76BE,0xFFBB,0x02},    // MC3_Y0DEF3_POS6 :
+{0x76C0,0xFFCE,0x02},    // MC3_X0DEF0_POS7 :
+{0x76C2,0xFFC9,0x02},    // MC3_Y0DEF0_POS7 :
+{0x76C4,0xFFFE,0x02},    // MC3_X0DEF1_POS7 :
+{0x76C6,0x000D,0x02},    // MC3_Y0DEF1_POS7 :
+{0x76C8,0x0002,0x02},    // MC3_X0DEF2_POS7 :
+{0x76CA,0xFFF6,0x02},    // MC3_Y0DEF2_POS7 :
+{0x76CC,0x003B,0x02},    // MC3_X0DEF3_POS7 :
+{0x76CE,0xFFBB,0x02},    // MC3_Y0DEF3_POS7 :
+{0x76D0,0xFF7E,0x02},    // MC3_X0DEF0_OUT :
+{0x76D2,0xFFE2,0x02},    // MC3_Y0DEF0_OUT :
+{0x76D4,0xFFFE,0x02},    // MC3_X0DEF1_OUT :
+{0x76D6,0x000D,0x02},    // MC3_Y0DEF1_OUT :
+{0x76D8,0x0002,0x02},    // MC3_X0DEF2_OUT :
+{0x76DA,0xFFF6,0x02},    // MC3_Y0DEF2_OUT :
+{0x76DC,0xFFC4,0x02},    // MC3_X0DEF3_OUT :
+{0x76DE,0xFFEC,0x02},    // MC3_Y0DEF3_OUT :
+{0x76E0,0xFFCE,0x02},    // MC3_X0DEF0_R2_POS4 :
+{0x76E2,0xFFC9,0x02},    // MC3_Y0DEF0_R2_POS4 :
+{0x76E4,0xFFD0,0x02},    // MC3_X0DEF1_R2_POS4 :
+{0x76E6,0x0037,0x02},    // MC3_Y0DEF1_R2_POS4 :
+{0x76E8,0x0002,0x02},    // MC3_X0DEF2_R2_POS4 :
+{0x76EA,0xFFF6,0x02},    // MC3_Y0DEF2_R2_POS4 :
+{0x76EC,0x003B,0x02},    // MC3_X0DEF3_R2_POS4 :
+{0x76EE,0xFFBB,0x02},    // MC3_Y0DEF3_R2_POS4 :
+{0x76F0,0xFFCE,0x02},    // MC3_X0DEF0_R2_POS5 :
+{0x76F2,0xFFC9,0x02},    // MC3_Y0DEF0_R2_POS5 :
+{0x76F4,0xFFD0,0x02},    // MC3_X0DEF1_R2_POS5 :
+{0x76F6,0x0037,0x02},    // MC3_Y0DEF1_R2_POS5 :
+{0x76F8,0x0002,0x02},    // MC3_X0DEF2_R2_POS5 :
+{0x76FA,0xFFF6,0x02},    // MC3_Y0DEF2_R2_POS5 :
+{0x76FC,0x003B,0x02},    // MC3_X0DEF3_R2_POS5 :
+{0x76FE,0xFFBB,0x02},    // MC3_Y0DEF3_R2_POS5 :
+{0x7700,0x0019,0x02},    // MC3_PXDEF0_POS1 :
+{0x7702,0xFF66,0x02},    // MC3_PYDEF0_POS1 :
+{0x7704,0x0000,0x02},    // MC3_PXDEF1_POS1 :
+{0x7706,0x0000,0x02},    // MC3_PYDEF1_POS1 :
+{0x7708,0x0000,0x02},    // MC3_PXDEF2_POS1 :
+{0x770A,0x0000,0x02},    // MC3_PYDEF2_POS1 :
+{0x770C,0xFFD7,0x02},    // MC3_PXDEF3_POS1 :
+{0x770E,0x0068,0x02},    // MC3_PYDEF3_POS1 :
+{0x7710,0x0000,0x02},    // MC3_PXDEF0_POS2 :
+{0x7712,0xFF66,0x02},    // MC3_PYDEF0_POS2 :
+{0x7714,0x0033,0x02},    // MC3_PXDEF1_POS2 :
+{0x7716,0xFF4C,0x02},    // MC3_PYDEF1_POS2 :
+{0x7718,0x0000,0x02},    // MC3_PXDEF2_POS2 :
+{0x771A,0x00B3,0x02},    // MC3_PYDEF2_POS2 :
+{0x771C,0xFFD7,0x02},    // MC3_PXDEF3_POS2 :
+{0x771E,0x0068,0x02},    // MC3_PYDEF3_POS2 :
+{0x7720,0x0000,0x02},    // MC3_PXDEF0_POS3 :
+{0x7722,0xFF80,0x02},    // MC3_PYDEF0_POS3 :
+{0x7724,0x0000,0x02},    // MC3_PXDEF1_POS3 :
+{0x7726,0x0000,0x02},    // MC3_PYDEF1_POS3 :
+{0x7728,0x0000,0x02},    // MC3_PXDEF2_POS3 :
+{0x772A,0x0000,0x02},    // MC3_PYDEF2_POS3 :
+{0x772C,0xFFD7,0x02},    // MC3_PXDEF3_POS3 :
+{0x772E,0x0068,0x02},    // MC3_PYDEF3_POS3 :
+{0x7730,0x0000,0x02},    // MC3_PXDEF0_POS4 :
+{0x7732,0xFFCC,0x02},    // MC3_PYDEF0_POS4 :
+{0x7734,0x0000,0x02},    // MC3_PXDEF1_POS4 :
+{0x7736,0x0000,0x02},    // MC3_PYDEF1_POS4 :
+{0x7738,0x0000,0x02},    // MC3_PXDEF2_POS4 :
+{0x773A,0x0000,0x02},    // MC3_PYDEF2_POS4 :
+{0x773C,0xFFD7,0x02},    // MC3_PXDEF3_POS4 :
+{0x773E,0x0068,0x02},    // MC3_PYDEF3_POS4 :
+{0x7740,0x0000,0x02},    // MC3_PXDEF0_POS5 :
+{0x7742,0xFFCC,0x02},    // MC3_PYDEF0_POS5 :
+{0x7744,0x0000,0x02},    // MC3_PXDEF1_POS5 :
+{0x7746,0x0000,0x02},    // MC3_PYDEF1_POS5 :
+{0x7748,0x0000,0x02},    // MC3_PXDEF2_POS5 :
+{0x774A,0x0000,0x02},    // MC3_PYDEF2_POS5 :
+{0x774C,0xFFD7,0x02},    // MC3_PXDEF3_POS5 :
+{0x774E,0x0068,0x02},    // MC3_PYDEF3_POS5 :
+{0x7750,0xFFB3,0x02},    // MC3_PXDEF0_POS6 :
+{0x7752,0x0000,0x02},    // MC3_PYDEF0_POS6 :
+{0x7754,0x0033,0x02},    // MC3_PXDEF1_POS6 :
+{0x7756,0xFF4C,0x02},    // MC3_PYDEF1_POS6 :
+{0x7758,0x0000,0x02},    // MC3_PXDEF2_POS6 :
+{0x775A,0x00B3,0x02},    // MC3_PYDEF2_POS6 :
+{0x775C,0xFFD7,0x02},    // MC3_PXDEF3_POS6 :
+{0x775E,0x0068,0x02},    // MC3_PYDEF3_POS6 :
+{0x7760,0xFFB3,0x02},    // MC3_PXDEF0_POS7 :
+{0x7762,0x0000,0x02},    // MC3_PYDEF0_POS7 :
+{0x7764,0x0000,0x02},    // MC3_PXDEF1_POS7 :
+{0x7766,0x0000,0x02},    // MC3_PYDEF1_POS7 :
+{0x7768,0x0000,0x02},    // MC3_PXDEF2_POS7 :
+{0x776A,0x0000,0x02},    // MC3_PYDEF2_POS7 :
+{0x776C,0xFFD7,0x02},    // MC3_PXDEF3_POS7 :
+{0x776E,0x0068,0x02},    // MC3_PYDEF3_POS7 :
+{0x7770,0x0019,0x02},    // MC3_PXDEF0_OUT :
+{0x7772,0xFFE6,0x02},    // MC3_PYDEF0_OUT :
+{0x7774,0x0000,0x02},    // MC3_PXDEF1_OUT :
+{0x7776,0x0000,0x02},    // MC3_PYDEF1_OUT :
+{0x7778,0x0000,0x02},    // MC3_PXDEF2_OUT :
+{0x777A,0x0000,0x02},    // MC3_PYDEF2_OUT :
+{0x777C,0xFFE1,0x02},    // MC3_PXDEF3_OUT :
+{0x777E,0xFFEB,0x02},    // MC3_PYDEF3_OUT :
+{0x7780,0x0000,0x02},    // MC3_PXDEF0_R2_POS4 :
+{0x7782,0xFFCC,0x02},    // MC3_PYDEF0_R2_POS4 :
+{0x7784,0x0000,0x02},    // MC3_PXDEF1_R2_POS4 :
+{0x7786,0x0000,0x02},    // MC3_PYDEF1_R2_POS4 :
+{0x7788,0x0000,0x02},    // MC3_PXDEF2_R2_POS4 :
+{0x778A,0x0000,0x02},    // MC3_PYDEF2_R2_POS4 :
+{0x778C,0xFFD7,0x02},    // MC3_PXDEF3_R2_POS4 :
+{0x778E,0x0068,0x02},    // MC3_PYDEF3_R2_POS4 :
+{0x7790,0x0000,0x02},    // MC3_PXDEF0_R2_POS5 :
+{0x7792,0xFFCC,0x02},    // MC3_PYDEF0_R2_POS5 :
+{0x7794,0x0000,0x02},    // MC3_PXDEF1_R2_POS5 :
+{0x7796,0x0000,0x02},    // MC3_PYDEF1_R2_POS5 :
+{0x7798,0x0000,0x02},    // MC3_PXDEF2_R2_POS5 :
+{0x779A,0x0000,0x02},    // MC3_PYDEF2_R2_POS5 :
+{0x779C,0xFFD7,0x02},    // MC3_PXDEF3_R2_POS5 :
+{0x779E,0x0068,0x02},    // MC3_PYDEF3_R2_POS5 :
+
+
+{0x6C44,0x13,0x01},    // G_CTRL_SEL :
+{0x0363,0x95,0x01},    // PICT3_GAMMA_MONI1 :
+{0x0366,0x95,0x01},    // PICT3_GAMMA_CAP1 :
+
+
+///////Scene Mode Setting////////////
+{0x0282,0x20,0x01},    //AWB_SN1 :
+{0x0283,0x20,0x01},    //AWB_SN2 :
+{0x0284,0x20,0x01},    //AWB_SN3 :
+{0x0285,0x20,0x01},    //AWB_SN4 :
+{0x0286,0x20,0x01},    //AWB_SN5 :
+{0x0287,0x25,0x01},    //AWB_SN6 :
+{0x0288,0x20,0x01},    //AWB_SN7 :
+{0x0289,0x20,0x01},    //AWB_SN8 :
+{0x028A,0x20,0x01},    //AWB_SN9 :
+{0x028B,0x20,0x01},    //AWB_SN10 :
+{0x028C,0x20,0x01},    //AWB_SN11 :
+{0x028D,0x20,0x01},    //AWB_SN12 :
+{0x028E,0x00,0x01},    //AF_SN1_2 :
+{0x028F,0x00,0x01},    //AF_SN3_4 :
+{0x0290,0x00,0x01},    //AF_SN5_6 :
+{0x0291,0x00,0x01},    //AF_SN7_8 :
+{0x0292,0x00,0x01},    //AF_SN9_10 :
+{0x0293,0x00,0x01},    //AF_SN11_12 :
+{0x0294,0x00,0x01},    //AE_SN1 :
+{0x0295,0x00,0x01},    //AE_SN2 :
+{0x0296,0x00,0x01},    //AE_SN3 :
+{0x0297,0x40,0x01},    //AE_SN4 :
+{0x0298,0x20,0x01},    //AE_SN5 :
+{0x0299,0x00,0x01},    //AE_SN6 :
+{0x029A,0x00,0x01},    //AE_SN7 :
+{0x029B,0x00,0x01},    //AE_SN8 :
+{0x029C,0x60,0x01},    //AE_SN9 :
+{0x029D,0x00,0x01},    //AE_SN10 :
+{0x029E,0x00,0x01},    //AE_SN11 :
+{0x029F,0x00,0x01},    //AE_SN12 :
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : AUTO
+{0x02A9,0x04,0x01},    //ISO_TYPE2 : ISO50
+{0x02AA,0x0A,0x01},    //ISO_TYPE3 : ISO200
+{0x02AB,0x00,0x01},    //ISO_TYPE4 : AUTO
+{0x02AC,0x01,0x01},    //AE_SUB_SN1 :
+{0x02AD,0x03,0x01},    //AE_SUB_SN2 :
+{0x02AE,0x01,0x01},    //AE_SUB_SN3 :
+{0x02AF,0x01,0x01},    //AE_SUB_SN4 :
+{0x02B0,0x01,0x01},    //AE_SUB_SN5 :
+{0x02B1,0x01,0x01},    //AE_SUB_SN6 :
+{0x02B2,0x01,0x01},    //AE_SUB_SN7 :
+{0x02B3,0x01,0x01},    //AE_SUB_SN8 :
+{0x02B4,0x01,0x01},    //AE_SUB_SN9 :
+{0x02B5,0x01,0x01},    //AE_SUB_SN10 :
+{0x02B6,0x02,0x01},    //AE_SUB_SN11 :
+{0x02B7,0x01,0x01},    //AE_SUB_SN12 :
+{0x02EA,0x00,0x01},    //EVREF_MONI_SN1_2 :
+{0x02EB,0x00,0x01},    //EVREF_MONI_SN3_4 :
+{0x02EC,0x03,0x01},    //EVREF_MONI_SN5_6 :
+{0x02ED,0x00,0x01},    //EVREF_MONI_SN7_8 :
+{0x02EE,0x00,0x01},    //EVREF_MONI_SN9_10 :
+{0x02EF,0x00,0x01},    //EVREF_MONI_SN11_12 :
+{0x02F0,0x01,0x01},    //EVREF_CAP_SN1_2 :
+{0x02F1,0x00,0x01},    //EVREF_CAP_SN3_4 :
+{0x02F2,0x03,0x01},    //EVREF_CAP_SN5_6 :
+{0x02F3,0x00,0x01},    //EVREF_CAP_SN7_8 :
+{0x02F4,0x00,0x01},    //EVREF_CAP_SN9_10 :
+{0x02F5,0x00,0x01},    //EVREF_CAP_SN11_12 :
+{0x02F6,0x00,0x01},    //EVREF_MOVIE_SN1_2 :
+{0x02F7,0x00,0x01},    //EVREF_MOVIE_SN3_4 :
+{0x02F8,0x03,0x01},    //EVREF_MOVIE_SN5_6 :
+{0x02F9,0x00,0x01},    //EVREF_MOVIE_SN7_8 :
+{0x02FA,0x00,0x01},    //EVREF_MOVIE_SN9_10 :
+{0x02FB,0x00,0x01},    //EVREF_MOVIE_SN11_12 :
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x0390,0xA4,0x01},    //PICT1_SN2 :
+{0x0391,0x00,0x01},    //PICT1_SN3 :
+{0x0392,0x04,0x01},    //PICT1_SN4 :
+{0x0393,0x04,0x01},    //PICT1_SN5 :
+{0x0394,0x00,0x01},    //PICT1_SN6 :
+{0x0395,0x50,0x01},    //PICT1_SN7 :
+{0x0396,0x0A,0x01},    //PICT1_SN8 :
+{0x0397,0x00,0x01},    //PICT1_SN9 :
+{0x0398,0xA0,0x01},    //PICT1_SN10 :
+{0x0399,0x00,0x01},    //PICT1_SN11 :
+{0x039A,0x00,0x01},    //PICT1_SN12 :
+{0x039B,0x00,0x01},    //UIHUE_TYPE1 :
+{0x039C,0x00,0x01},    //UIHUE_TYPE2 :
+{0x039D,0x00,0x01},    //UIHUE_TYPE3 :
+{0x039E,0x80,0x01},    //UISATURATION_TYPE1 :
+{0x039F,0x9E,0x01},    //UISATURATION_TYPE2 :
+{0x03A0,0x80,0x01},    //UISATURATION_TYPE3 :
+{0x03A1,0x20,0x01},    //UISHARPNESS_POS_TYPE1 :
+{0x03A2,0x14,0x01},    //UISHARPNESS_POS_TYPE2 :
+{0x03A3,0x2C,0x01},    //UISHARPNESS_POS_TYPE3 :
+{0x03A4,0x20,0x01},    //UISHARPNESS_NEG_TYPE1 :
+{0x03A5,0x14,0x01},    //UISHARPNESS_NEG_TYPE2 :
+{0x03A6,0x2C,0x01},    //UISHARPNESS_NEG_TYPE3 :
+{0x0308,0x11,0x01},    //AELINE_MONI_SN1_2 :
+{0x0309,0x13,0x01},    //AELINE_MONI_SN3_4 :
+{0x030A,0x11,0x01},    //AELINE_MONI_SN5_6 :
+{0x030B,0x41,0x01},    //AELINE_MONI_SN7_8 :
+{0x030C,0x19,0x01},    //AELINE_MONI_SN9_10 :
+{0x030D,0x11,0x01},    //AELINE_MONI_SN11_12 :
+{0x030E,0x11,0x01},    //AELINE_HALF_SN1_2 :
+{0x030F,0x13,0x01},    //AELINE_HALF_SN3_4 :
+{0x0310,0x11,0x01},    //AELINE_HALF_SN5_6 :
+{0x0311,0x41,0x01},    //AELINE_HALF_SN7_8 :
+{0x0312,0x19,0x01},    //AELINE_HALF_SN9_10 :
+{0x0313,0x11,0x01},    //AELINE_HALF_SN11_12 :
+{0x0314,0x11,0x01},    //AELINE_HALF_AFEND_SN1_2 :
+{0x0315,0x13,0x01},    //AELINE_HALF_AFEND_SN3_4 :
+{0x0316,0x11,0x01},    //AELINE_HALF_AFEND_SN5_6 :
+{0x0317,0x41,0x01},    //AELINE_HALF_AFEND_SN7_8 :
+{0x0318,0x19,0x01},    //AELINE_HALF_AFEND_SN9_10 :
+{0x0319,0x11,0x01},    //AELINE_HALF_AFEND_SN11_12 :
+{0x031A,0x00,0x01},    //AELINE_CAP_SN1_2 :
+{0x031B,0x03,0x01},    //AELINE_CAP_SN3_4 :
+{0x031C,0x00,0x01},    //AELINE_CAP_SN5_6 :
+{0x031D,0x50,0x01},    //AELINE_CAP_SN7_8 :
+{0x031E,0x08,0x01},    //AELINE_CAP_SN9_10 :
+{0x031F,0x00,0x01},    //AELINE_CAP_SN11_12 :
+{0x0320,0x22,0x01},    //AELINE_MOVIE_SN1_2 :
+{0x0321,0x22,0x01},    //AELINE_MOVIE_SN3_4 :
+{0x0322,0x22,0x01},    //AELINE_MOVIE_SN5_6 :
+{0x0323,0x22,0x01},    //AELINE_MOVIE_SN7_8 :
+{0x0324,0x22,0x01},    //AELINE_MOVIE_SN9_10 :
+{0x0325,0x22,0x01},    //AELINE_MOVIE_SN11_12 :
+{0x02DB,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN1_2 :
+{0x02DC,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN3_4 :
+{0x02DD,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN5_6 :
+{0x02DE,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN7_8 :
+{0x02DF,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN9_10 :
+{0x02E0,0x33,0x01},    //VADD_SHTGAIN_CTRL_SN11_12 :
+{0x0383,0x80,0x01},    // MC3_MODE_SN_1 :
+{0x0384,0x80,0x01},    // MC3_MODE_SN_2 :
+{0x0385,0x80,0x01},    // MC3_MODE_SN_3 :
+{0x0386,0x80,0x01},    // MC3_MODE_SN_4 :
+{0x0387,0x80,0x01},    // MC3_MODE_SN_5 :
+{0x0388,0x80,0x01},    // MC3_MODE_SN_6 :
+{0x0389,0x80,0x01},    // MC3_MODE_SN_7 :
+{0x038A,0x80,0x01},    // MC3_MODE_SN_8 :
+{0x038B,0x80,0x01},    // MC3_MODE_SN_9 :
+{0x038C,0x80,0x01},    // MC3_MODE_SN_10 :
+{0x038D,0x80,0x01},    // MC3_MODE_SN_11 :
+{0x038E,0x80,0x01},    // MC3_MODE_SN_12 :
+
+///AWBÃʱâÁÂÇ¥
+{0x6238,0x0BE3,0x02},    // INIT_CONT_INR :
+{0x623A,0x1718,0x02},    // INIT_CONT_INB :
+{0x623C,0x0BBB,0x02},    // INIT_CONT_OUTR :
+{0x623E,0x18B7,0x02},    // INIT_CONT_OUTB :
+
+//bluesky brightness setting
+{0x6298,0xB0,0x01},    // SHADE_JUDGPOS :
+{0x6299,0xB5,0x01},    // BLUESKY_JUDGPOS :
+
+//EV SEL gain step
+{0x5E6B,0x04,0x01},    // EVSEL_GAIN_P1_3 :
+{0x5E6C,0x08,0x01},    // EVSEL_GAIN_P2_3 :
+{0x5E6D,0x0C,0x01},    // EVSEL_GAIN_P3_3 :
+{0x5E6E,0x10,0x01},    // EVSEL_GAIN_P4_3 :
+{0x5E6F,0x14,0x01},    // EVSEL_GAIN_P5_3 :
+{0x5E70,0x18,0x01},    // EVSEL_GAIN_P6_3 :
+{0x5E71,0x05,0x01},    // EVSEL_GAIN_M1_3 :
+{0x5E72,0x0A,0x01},    // EVSEL_GAIN_M2_3 :
+{0x5E73,0x0F,0x01},    // EVSEL_GAIN_M3_3 :
+{0x5E74,0x16,0x01},    // EVSEL_GAIN_M4_3 :
+{0x5E75,0x1B,0x01},    // EVSEL_GAIN_M5_3 :
+{0x5E76,0x20,0x01},    // EVSEL_GAIN_M6_3 :
+
+//In, Out judge
+{0x62A2,0x8C,0x01},    // INOUT_WEIGHT_AREA_ST : 140
+{0x6258,0xA0,0x01},    // IN_JUDGPOS : 160
+{0x6259,0xA1,0x01},    // OUT_JUDGPOS : 161
+{0x62A3,0xA4,0x01},    // INOUT_WEIGHT_AREA_ED : 164
+{0x62A4,0x92,0x01},    // IN_LUMST : 146
+{0x62A5,0x9C,0x01},    // OUT_LUMST : 156
+
+//SHD TH
+{0x6C32,0x1964,0x02},    // SHD_INP_TH_HB_H_R2
+{0x6C34,0x18CE,0x02},    // SHD_INP_TH_HB_L_R2
+{0x6C36,0x10CC,0x02},    // SHD_INP_TH_LB_H_R2
+{0x6C38,0x1004,0x02},    // SHD_INP_TH_LB_L_R2
+{0x6C3C,0x10CC,0x02},    // SHD_INP_TH_HB_H_RB
+{0x6C3E,0x1004,0x02},    // SHD_INP_TH_HB_L_RB
+{0x6C40,0x0000,0x02},    // SHD_INP_TH_LB_H_RB
+{0x6C42,0x0000,0x02},    // SHD_INP_TH_LB_L_RB
+
+//PreWB_offset (for SHD2)
+{0x6828,0x0013,0x02},    // SHD_PRER_OFFSET_R2 :
+//PreWB_offset (for SHD3)
+{0x682C,0x000C,0x02},    // SHD_PRER_OFFSET_RB :
+{0x6830,0xFFFF,0x02},    // SHD_PREB_OFFSET_RB :
+{0x005E,0xA6A6,0x02}, /* for ESD check */
+};
+
+// ISX012-0
+// MIPI 2LANE      648
+//        PLL   648MHz
+//        DCK       81
+// inifile
+// size address data
+//
+static const isx012_regset_t ISX012_Pll_Setting_2[] =
+{
+{0x0007,0x01,0x01},                   // PLL_CKSEL                 : PLL 648MHz
+{0x0008,0x03,0x01},                   // SRCCK_DIV                 : 1/8 frequency
+
+{0x0004,0x03,0x01},                  //I2C_ADR_SEL 2: 0x3C MIPI selected, 3: 0x3D MIPI selected
+{0x5008,0x00,0x01},                  //ENDIAN_SEL : 0:Little Endian
+{0x6DA8,0x01,0x01},                  //SHD_CoEF (OTP shading ON flag)
+{0x6DA9,0x09,0x01},                  // WHITE_CTRL
+{0x6DCB,0x22,0x01},    // YGAM_CONFIG2 :
+
+{0x00C4,0x11,0x01},                   // VIF_CLKCONFIG1            : VIFSEL and VIFDIV setting value with full frame pixel setting for other then JPG
+{0x00C5,0x11,0x01},                   // VIF_CLKCONFIG2            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other then JPG
+{0x00C6,0x11,0x01},                   // VIF_CLKCONFIG3            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for other then JPG
+{0x00C7,0x11,0x01},                   // VIF_CLKCONFIG4            : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for other then JPG
+{0x00C8,0x11,0x01},                   // VIF_CLKCONFIG5            : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG mode
+{0x00C9,0x11,0x01},                   // VIF_CLKCONFIG6            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG mode
+{0x00CA,0x11,0x01},                   // VIF_CLKCONFIG7            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for JPG mode
+{0x018C,0x0000,0x02},                // VADJ_SENS_1_1             : VMAX adjustment value for full frame pixel
+{0x018E,0x0000,0x02},                // VADJ_SENS_1_2             : VMAX adjustment value for 1/2 sub-sampling
+{0x0190,0x0000,0x02},                // VADJ_SENS_1_4             : VMAX adjustment value for 1/4 sub-sampling
+{0x0192,0x0000,0x02},                // VADJ_SENS_1_8             : VMAX adjustment value for 1/8 sub-sampling
+{0x0194,0x0000,0x02},                // VADJ_SENS_HD_1_1          : VMAX adjustment value for HD full frame pixel
+{0x0196,0x0000,0x02},                // VADJ_SENS_HD_1_2          : VMAX adjustment value for HD 1/2 sub-sampling
+{0x6A16,0x0400,0x02},                // FLC_OPD_HEIGHT_NORMAL_1_1 : Detection window vertical size with all 32 windows for FLC full frame pixel
+{0x6A18,0x03C0,0x02},                // FLC_OPD_HEIGHT_NORMAL_1_2 : Detection window vertical size with all 32 windows for FLC 1/2 sub-sampling
+{0x6A1A,0x01E0,0x02},                // FLC_OPD_HEIGHT_NORMAL_1_4 : Detection window vertical size with all 32 windows for FLC 1/4 sub-sampling
+{0x6A1C,0x00E0,0x02},                // FLC_OPD_HEIGHT_NORMAL_1_8 : Detection window vertical size with all 32 windows for FLC 1/8 sub-sampling
+{0x6A1E,0x0400,0x02},                // FLC_OPD_HEIGHT_HD_1_1     : Detection window vertical size with all 32 windows for FLC HD full frame pixel
+{0x6A20,0x02C0,0x02},                // FLC_OPD_HEIGHT_HD_1_2     : Detection window vertical size with all 32 windows for FLC HD 1/2 sub-sampling
+{0x0016,0x0010,0x02},                // GPIO_FUNCSEL              : GPIO setting
+{0x5C01,0x00,0x01},                   // RGLANESEL                 : Select 1Lane or 2Lane
+
+{0x5C04,0x06,0x01},                   // RGTLPX                    : //0x5C04   0x4  ->  0x6
+{0x5C05,0x05,0x01},                   // RGTCLKPREPARE             : //0x5C05   0x3  ->  0x5
+{0x5C06,0x14,0x01},                   // RGTCLKZERO                :
+{0x5C07,0x02,0x01},                   // RGTCLKPRE                 :
+{0x5C08,0x0D,0x01},                   // RGTCLKPOST                : //0x5C08   0x11 ->  0xD
+{0x5C09,0x07,0x01},                   // RGTCLKTRAIL               : //0x5C09   0x5  ->  0x7
+{0x5C0A,0x0A,0x01},                   // RGTHSEXIT                 : //0x5C0A   0x7  ->  0xA
+{0x5C0B,0x05,0x01},                   // RGTHSPREPARE              : //0x5C0B   0x3  ->  0x5
+{0x5C0C,0x08,0x01},                   // RGTHSZERO                 : //0x5C0C   0x7  ->  0x8
+{0x5C0D,0x07,0x01},                   // RGTHSTRAIL                : //0x5C0D   0x5  ->  0x7
+
+{0x0009,0x01,0x01},                 // EXT_PLL_CKSEL       : PLL 648MHz
+{0x00D0,0x11,0x01},                 // VIF_CLKCONFIG_EXT1  : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG and interleave mode
+{0x00D1,0x11,0x01},                 // VIF_CLKCONFIG_EXT2  : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG and interleave mode
+{0x00D4,0x11,0x01},                 // VIF_CLKCONFIG_EXT5  : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG mode
+{0x00D5,0x11,0x01},                 // VIF_CLKCONFIG_EXT6  : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG mode
+{0x00D8,0x11,0x01},                 // VIF_CLKCONFIG_EXT9  : VIFSEL and VIFDIV setting value with full frame pixel setting for other than JPG
+{0x00D9,0x11,0x01},                 // VIF_CLKCONFIG_EXT10 : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other than JPG
+
+//init Preview setting
+{0x0089,0x00,0x01},//OUTFMT_MONI
+{0x0090,0x0280,0x02},//HSIZE_MONI : 640
+{0x0096,0x01E0,0x02},//VSIZE_MONI : 480
+{0x0083,0x01,0x01},//SENSMODE_MONI
+{0x0086,0x02,0x01},//FPSTYPE_MONI
+{0x0081,0x00,0x01},//MODESEL
+{0x0082,0x01,0x01},//MONI_REFRESH
+
+//jpeg setting
+//Apex40 is not Jpeg Capture
+
+//Fast mode setting
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x500C,0x00FA,0x02},    // FAST_SHT_LIMIT_COUNT
+
+//Select sensor inversion link control
+{0x501A,0x00,0x01},    //SENS_REVERSE_CTRL
+
+//shading
+{0x6DBC,0x03,0x01},    // WHITE_EDGE_MAX :
+{0x6DF6,0xFF,0x01},    // WHITE_SHD_JUDGE_BODY_COLOR_RATIO :
+{0x6DF7,0xF0,0x01},    // WHITE_SHD_JUDGE_RED_RATIO :
+{0x6DAD,0x0C,0x01},    // WHITE_OFSET1_UP :
+{0x6DAE,0x0C,0x01},    // WHITE_OFSET1_DOWN :
+{0x6DAF,0x11,0x01},    // WHITE_OFSET1_RIGHT :
+{0x6DB0,0x1B,0x01},    // WHITE_OFSET1_LEFT :
+{0x6DB1,0x0D,0x01},    // WHITE_OFSET2_UP :
+{0x6DB2,0x13,0x01},    // WHITE_OFSET2_DOWN :
+{0x6DB3,0x11,0x01},    // WHITE_OFSET2_RIGHT :
+{0x6DB4,0x17,0x01},    // WHITE_OFSET2_LEFT :
+
+//addtional code
+{0xF200,0xB9B9,0x02},
+{0xF202,0x4E12,0x02},
+{0xF204,0x6055,0x02},
+{0xF206,0x008B,0x02},
+{0xF208,0xF177,0x02},
+{0xF20A,0xFA70,0x02},
+{0xF20C,0x0000,0x02},
+{0xF20E,0x0000,0x02},
+{0xF210,0x0000,0x02},
+{0xF212,0x0000,0x02},
+{0xF214,0x0000,0x02},
+{0xF216,0x0000,0x02},
+{0xF218,0x0000,0x02},
+{0xF21A,0x0000,0x02},
+{0xF21C,0x0000,0x02},
+{0xF21E,0x0000,0x02},
+{0xF220,0x0000,0x02},
+{0xF222,0x0000,0x02},
+{0xF224,0x0000,0x02},
+{0xF226,0x0000,0x02},
+{0xF228,0x0000,0x02},
+{0xF22A,0x0000,0x02},
+{0xF22C,0x0000,0x02},
+{0xF22E,0x0000,0x02},
+{0xF230,0x0000,0x02},
+{0xF232,0x0000,0x02},
+{0xF234,0x0000,0x02},
+{0xF236,0x0000,0x02},
+{0xF238,0x0000,0x02},
+{0xF23A,0x0000,0x02},
+{0xF23C,0x0000,0x02},
+{0xF23E,0x0000,0x02},
+{0xF240,0x0000,0x02},
+{0xF242,0x0000,0x02},
+{0xF244,0xB47E,0x02},
+{0xF246,0x4808,0x02},
+{0xF248,0x7800,0x02},
+{0xF24A,0x07C0,0x02},
+{0xF24C,0x0FC0,0x02},
+{0xF24E,0xF687,0x02},
+{0xF250,0xF8ED,0x02},
+{0xF252,0xF68E,0x02},
+{0xF254,0xFE2B,0x02},
+{0xF256,0xF688,0x02},
+{0xF258,0xFF6B,0x02},
+{0xF25A,0xF693,0x02},
+{0xF25C,0xFB6B,0x02},
+{0xF25E,0xF687,0x02},
+{0xF260,0xF947,0x02},
+{0xF262,0xBC7E,0x02},
+{0xF264,0xF688,0x02},
+{0xF266,0xFD8F,0x02},
+{0xF268,0x239C,0x02},
+{0xF26A,0x0018,0x02},
+
+
+{0x0006,0x16,0x01},                  //INCK_SET : 24MHz
+};
+
+// ISX012-0
+// MIPI 2LANE 432/LANE
+//        PLL   432MHz
+//        DCK       54
+// inifile
+// size address data
+//
+static const isx012_regset_t ISX012_Pll_Setting_3[] =
+{
+{0x0007,0x00,0x01},                  // PLL_CKSEL                 : PLL 432MHz
+{0x0008,0x00,0x01},                  // SRCCK_DIV                 : 1/5 frequency
+
+{0x0004,0x03,0x01},                  //I2C_ADR_SEL 2: 0x3C MIPI selected, 3: 0x3D MIPI selected
+{0x5008,0x00,0x01},                  //ENDIAN_SEL : 0:Little Endian
+{0x6DA8,0x01,0x01},                  //SHD_CoEF (OTP shading ON flag)
+{0x6DA9,0x09,0x01},                  // WHITE_CTRL
+{0x6DCB,0x22,0x01},    // YGAM_CONFIG2 :
+
+{0x00C4,0x11,0x01},                  // VIF_CLKCONFIG1            : VIFSEL and VIFDIV setting value with full frame pixel setting for other then JPG
+{0x00C5,0x11,0x01},                  // VIF_CLKCONFIG2            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other then JPG
+{0x00C6,0x11,0x01},                  // VIF_CLKCONFIG3            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for other then JPG
+{0x00C7,0x11,0x01},                  // VIF_CLKCONFIG4            : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for other then JPG
+{0x00C8,0x11,0x01},                  // VIF_CLKCONFIG5            : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG mode
+{0x00C9,0x11,0x01},                  // VIF_CLKCONFIG6            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG mode
+{0x00CA,0x11,0x01},                  // VIF_CLKCONFIG7            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for JPG mode
+{0x00CC,0x11,0x01},                  // VIF_CLKCONFIG9            : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG and interleave mode
+{0x00CD,0x11,0x01},                  // VIF_CLKCONFIG10           : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG and interleave mode
+{0x6A12,0x11,0x01},                  // VIF_CLKCONFIG13 for RAW8  : VIFSEL and VIFDIV setting value with full frame pixel setting for RAW mode
+{0x6A13,0x11,0x01},                  // VIF_CLKCONFIG14 for RAW8  : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for RAW mode
+{0x6A14,0x11,0x01},                  // VIF_CLKCONFIG15 for RAW8  : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for RAW mode
+{0x6A15,0x11,0x01},                  // VIF_CLKCONFIG16 for RAW8  : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for RAW mode
+{0x018C,0x0000,0x02},                // VADJ_SENS_1_1             : VMAX adjustment value for full frame pixel
+{0x018E,0x0012,0x02},                // VADJ_SENS_1_2             : VMAX adjustment value for 1/2 sub-sampling
+{0x0190,0x0000,0x02},               // VADJ_SENS_1_4             : VMAX adjustment value for 1/4 sub-sampling
+{0x0192,0x0000,0x02},               // VADJ_SENS_1_8             : VMAX adjustment value for 1/8 sub-sampling
+{0x0194,0x0027,0x02},               // VADJ_SENS_HD_1_1          : VMAX adjustment value for HD full frame pixel
+{0x0196,0x0015,0x02},               // VADJ_SENS_HD_1_2          : VMAX adjustment value for HD 1/2 sub-sampling
+{0x6A16,0x0440,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_1 : Detection window vertical size with all 32 windows for FLC full frame pixel
+{0x6A18,0x03C0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_2 : Detection window vertical size with all 32 windows for FLC 1/2 sub-sampling
+{0x6A1A,0x01E0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_4 : Detection window vertical size with all 32 windows for FLC 1/4 sub-sampling
+{0x6A1C,0x00E0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_8 : Detection window vertical size with all 32 windows for FLC 1/8 sub-sampling
+{0x6A1E,0x0420,0x02},               // FLC_OPD_HEIGHT_HD_1_1     : Detection window vertical size with all 32 windows for FLC HD full frame pixel
+{0x6A20,0x02C0,0x02},               // FLC_OPD_HEIGHT_HD_1_2     : Detection window vertical size with all 32 windows for FLC HD 1/2 sub-sampling
+{0x0016,0x0010,0x02},               // GPIO_FUNCSEL              : GPIO setting
+{0x5C01,0x00,0x01},                  // RGLANESEL                 :
+{0x5C04,0x04,0x01},                  // RGTLPX                    :
+{0x5C05,0x03,0x01},                  // RGTCLKPREPARE             :
+{0x5C06,0x0E,0x01},                  // RGTCLKZERO                :
+{0x5C07,0x02,0x01},                  // RGTCLKPRE                 :
+{0x5C08,0x0B,0x01},                  // RGTCLKPOST                :
+{0x5C09,0x05,0x01},                  // RGTCLKTRAIL               :
+{0x5C0A,0x07,0x01},                  // RGTHSEXIT                 :
+{0x5C0B,0x03,0x01},                  // RGTHSPREPARE              :
+{0x5C0C,0x07,0x01},                  // RGTHSZERO                 :
+{0x5C0D,0x05,0x01},                  // RGTHSTRAIL                :
+
+{0x0009,0x01,0x01},		//
+{0x000A,0x03,0x01},		// EXT_SRCCK_DIV	: 1/8 frequency
+{0x00D8,0x11,0x01},                 // VIF_CLKCONFIG_EXT9  : VIFSEL and VIFDIV setting value with full frame pixel setting for other than JPG
+{0x00D9,0x11,0x01},                 // VIF_CLKCONFIG_EXT10 : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other than JPG
+{0x00DA,0x11,0x01},                 // VIF_CLKCONFIG_EXT11 : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for other than JPG
+{0x00DB,0x11,0x01},                 // VIF_CLKCONFIG_EXT12 : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for other than JPG
+{0x00AC,0x02,0x01},                 //
+
+//init Preview setting
+{0x0089,0x00,0x01},//OUTFMT_MONI
+{0x0090,0x0280,0x02},//HSIZE_MONI : 640
+{0x0096,0x01E0,0x02},//VSIZE_MONI : 480
+{0x0083,0x01,0x01},//SENSMODE_MONI
+{0x0086,0x02,0x01},//FPSTYPE_MONI
+{0x0081,0x00,0x01},//MODESEL
+{0x0082,0x01,0x01},//MONI_REFRESH
+
+//jpeg setting
+//Apex40 is not Jpeg Capture
+
+//Fast mode setting
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x500C,0x00FA,0x02},    // FAST_SHT_LIMIT_COUNT
+
+//Select sensor inversion link control
+{0x501A,0x00,0x01},    //SENS_REVERSE_CTRL
+
+//shading
+{0x6DBC,0x03,0x01},    // WHITE_EDGE_MAX :
+{0x6DF6,0xFF,0x01},    // WHITE_SHD_JUDGE_BODY_COLOR_RATIO :
+{0x6DF7,0xF0,0x01},    // WHITE_SHD_JUDGE_RED_RATIO :
+{0x6DAD,0x0C,0x01},    // WHITE_OFSET1_UP :
+{0x6DAE,0x0C,0x01},    // WHITE_OFSET1_DOWN :
+{0x6DAF,0x11,0x01},    // WHITE_OFSET1_RIGHT :
+{0x6DB0,0x1B,0x01},    // WHITE_OFSET1_LEFT :
+{0x6DB1,0x0D,0x01},    // WHITE_OFSET2_UP :
+{0x6DB2,0x13,0x01},    // WHITE_OFSET2_DOWN :
+{0x6DB3,0x11,0x01},    // WHITE_OFSET2_RIGHT :
+{0x6DB4,0x17,0x01},    // WHITE_OFSET2_LEFT :
+
+//additional code
+{0xF200,0xB9B9,0x02},
+{0xF202,0x4E12,0x02},
+{0xF204,0x6055,0x02},
+{0xF206,0x008B,0x02},
+{0xF208,0xF177,0x02},
+{0xF20A,0xFA70,0x02},
+{0xF20C,0x0000,0x02},
+{0xF20E,0x0000,0x02},
+{0xF210,0x0000,0x02},
+{0xF212,0x0000,0x02},
+{0xF214,0x0000,0x02},
+{0xF216,0x0000,0x02},
+{0xF218,0x0000,0x02},
+{0xF21A,0x0000,0x02},
+{0xF21C,0x0000,0x02},
+{0xF21E,0x0000,0x02},
+{0xF220,0x0000,0x02},
+{0xF222,0x0000,0x02},
+{0xF224,0x0000,0x02},
+{0xF226,0x0000,0x02},
+{0xF228,0x0000,0x02},
+{0xF22A,0x0000,0x02},
+{0xF22C,0x0000,0x02},
+{0xF22E,0x0000,0x02},
+{0xF230,0x0000,0x02},
+{0xF232,0x0000,0x02},
+{0xF234,0x0000,0x02},
+{0xF236,0x0000,0x02},
+{0xF238,0x0000,0x02},
+{0xF23A,0x0000,0x02},
+{0xF23C,0x0000,0x02},
+{0xF23E,0x0000,0x02},
+{0xF240,0x0000,0x02},
+{0xF242,0x0000,0x02},
+{0xF244,0xB47E,0x02},
+{0xF246,0x4808,0x02},
+{0xF248,0x7800,0x02},
+{0xF24A,0x07C0,0x02},
+{0xF24C,0x0FC0,0x02},
+{0xF24E,0xF687,0x02},
+{0xF250,0xF8ED,0x02},
+{0xF252,0xF68E,0x02},
+{0xF254,0xFE2B,0x02},
+{0xF256,0xF688,0x02},
+{0xF258,0xFF6B,0x02},
+{0xF25A,0xF693,0x02},
+{0xF25C,0xFB6B,0x02},
+{0xF25E,0xF687,0x02},
+{0xF260,0xF947,0x02},
+{0xF262,0xBC7E,0x02},
+{0xF264,0xF688,0x02},
+{0xF266,0xFD8F,0x02},
+{0xF268,0x239C,0x02},
+{0xF26A,0x0018,0x02},
+
+{0x0006,0x16,0x01},                  //INCK_SET : 24MHz
+};
+
+// ISX012-0
+// MIPI 2LANE 432/LANE
+//        PLL   432MHz
+//        DCK       54
+// inifile
+// size address data
+//
+static const isx012_regset_t ISX012_Pll_Setting_4[] =
+{
+{0x0007,0x00,0x01},                  // PLL_CKSEL                 : PLL 432MHz
+{0x0008,0x00,0x01},                  // SRCCK_DIV                 : 1/5 frequency
+
+{0x0004,0x03,0x01},                  //I2C_ADR_SEL 2: 0x3C MIPI selected, 3: 0x3D MIPI selected
+{0x5008,0x00,0x01},                  //ENDIAN_SEL : 0:Little Endian
+{0x6DA8,0x01,0x01},                  //SHD_CoEF (OTP shading ON flag)
+{0x6DA9,0x09,0x01},                  // WHITE_CTRL
+{0x6DCB,0x22,0x01},    // YGAM_CONFIG2 :
+
+{0x00C4,0x11,0x01},                  // VIF_CLKCONFIG1            : VIFSEL and VIFDIV setting value with full frame pixel setting for other then JPG
+{0x00C5,0x11,0x01},                  // VIF_CLKCONFIG2            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other then JPG
+{0x00C6,0x11,0x01},                  // VIF_CLKCONFIG3            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for other then JPG
+{0x00C7,0x11,0x01},                  // VIF_CLKCONFIG4            : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for other then JPG
+{0x00C8,0x11,0x01},                  // VIF_CLKCONFIG5            : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG mode
+{0x00C9,0x11,0x01},                  // VIF_CLKCONFIG6            : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG mode
+{0x00CA,0x11,0x01},                  // VIF_CLKCONFIG7            : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for JPG mode
+{0x00CC,0x11,0x01},                  // VIF_CLKCONFIG9            : VIFSEL and VIFDIV setting value with full frame pixel setting for JPG and interleave mode
+{0x00CD,0x11,0x01},                  // VIF_CLKCONFIG10           : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for JPG and interleave mode
+{0x6A12,0x11,0x01},                  // VIF_CLKCONFIG13 for RAW8  : VIFSEL and VIFDIV setting value with full frame pixel setting for RAW mode
+{0x6A13,0x11,0x01},                  // VIF_CLKCONFIG14 for RAW8  : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for RAW mode
+{0x6A14,0x11,0x01},                  // VIF_CLKCONFIG15 for RAW8  : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for RAW mode
+{0x6A15,0x11,0x01},                  // VIF_CLKCONFIG16 for RAW8  : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for RAW mode
+{0x018C,0x0026,0x02},                // VADJ_SENS_1_1             : VMAX adjustment value for full frame pixel
+{0x018E,0x0012,0x02},                // VADJ_SENS_1_2             : VMAX adjustment value for 1/2 sub-sampling
+{0x0190,0x0000,0x02},               // VADJ_SENS_1_4             : VMAX adjustment value for 1/4 sub-sampling
+{0x0192,0x0000,0x02},               // VADJ_SENS_1_8             : VMAX adjustment value for 1/8 sub-sampling
+{0x0194,0x0027,0x02},               // VADJ_SENS_HD_1_1          : VMAX adjustment value for HD full frame pixel
+{0x0196,0x0015,0x02},               // VADJ_SENS_HD_1_2          : VMAX adjustment value for HD 1/2 sub-sampling
+{0x6A16,0x0440,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_1 : Detection window vertical size with all 32 windows for FLC full frame pixel
+{0x6A18,0x03C0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_2 : Detection window vertical size with all 32 windows for FLC 1/2 sub-sampling
+{0x6A1A,0x01E0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_4 : Detection window vertical size with all 32 windows for FLC 1/4 sub-sampling
+{0x6A1C,0x00E0,0x02},               // FLC_OPD_HEIGHT_NORMAL_1_8 : Detection window vertical size with all 32 windows for FLC 1/8 sub-sampling
+{0x6A1E,0x0420,0x02},               // FLC_OPD_HEIGHT_HD_1_1     : Detection window vertical size with all 32 windows for FLC HD full frame pixel
+{0x6A20,0x02C0,0x02},               // FLC_OPD_HEIGHT_HD_1_2     : Detection window vertical size with all 32 windows for FLC HD 1/2 sub-sampling
+{0x0016,0x0010,0x02},               // GPIO_FUNCSEL              : GPIO setting
+{0x5C01,0x00,0x01},                  // RGLANESEL                 :
+{0x5C04,0x04,0x01},                  // RGTLPX                    :
+{0x5C05,0x03,0x01},                  // RGTCLKPREPARE             :
+{0x5C06,0x0E,0x01},                  // RGTCLKZERO                :
+{0x5C07,0x02,0x01},                  // RGTCLKPRE                 :
+{0x5C08,0x0B,0x01},                  // RGTCLKPOST                :
+{0x5C09,0x05,0x01},                  // RGTCLKTRAIL               :
+{0x5C0A,0x07,0x01},                  // RGTHSEXIT                 :
+{0x5C0B,0x03,0x01},                  // RGTHSPREPARE              :
+{0x5C0C,0x07,0x01},                  // RGTHSZERO                 :
+{0x5C0D,0x05,0x01},                  // RGTHSTRAIL                :
+
+{0x6A9E,0x15C0,0x02},                //HMAX_1_1(0x6A9E)=0x15C0
+
+{0x0009,0x01,0x01},		//
+{0x000A,0x03,0x01},		// EXT_SRCCK_DIV	: 1/8 frequency
+{0x00D8,0x11,0x01},                 // VIF_CLKCONFIG_EXT9  : VIFSEL and VIFDIV setting value with full frame pixel setting for other than JPG
+{0x00D9,0x11,0x01},                 // VIF_CLKCONFIG_EXT10 : VIFSEL and VIFDIV setting value with 1/2 sub-sampling setting for other than JPG
+{0x00DA,0x11,0x01},                 // VIF_CLKCONFIG_EXT11 : VIFSEL and VIFDIV setting value with 1/4 sub-sampling setting for other than JPG
+{0x00DB,0x11,0x01},                 // VIF_CLKCONFIG_EXT12 : VIFSEL and VIFDIV setting value with 1/8 sub-sampling setting for other than JPG
+{0x00AC,0x00,0x01},                 //
+
+//init Preview setting
+{0x0089,0x00,0x01},//OUTFMT_MONI
+{0x0090,0x0280,0x02},//HSIZE_MONI : 640
+{0x0096,0x01E0,0x02},//VSIZE_MONI : 480
+{0x0083,0x01,0x01},//SENSMODE_MONI
+{0x0086,0x02,0x01},//FPSTYPE_MONI
+{0x0081,0x00,0x01},//MODESEL
+{0x0082,0x01,0x01},//MONI_REFRESH
+
+//jpeg setting
+//Apex40 is not Jpeg Capture
+
+//Fast mode setting
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x500C,0x00FA,0x02},    // FAST_SHT_LIMIT_COUNT
+
+//Select sensor inversion link control
+{0x501A,0x00,0x01},    //SENS_REVERSE_CTRL
+
+//shading
+{0x6DBC,0x03,0x01},    // WHITE_EDGE_MAX :
+{0x6DF6,0xFF,0x01},    // WHITE_SHD_JUDGE_BODY_COLOR_RATIO :
+{0x6DF7,0xF0,0x01},    // WHITE_SHD_JUDGE_RED_RATIO :
+{0x6DAD,0x0C,0x01},    // WHITE_OFSET1_UP :
+{0x6DAE,0x0C,0x01},    // WHITE_OFSET1_DOWN :
+{0x6DAF,0x11,0x01},    // WHITE_OFSET1_RIGHT :
+{0x6DB0,0x1B,0x01},    // WHITE_OFSET1_LEFT :
+{0x6DB1,0x0D,0x01},    // WHITE_OFSET2_UP :
+{0x6DB2,0x13,0x01},    // WHITE_OFSET2_DOWN :
+{0x6DB3,0x11,0x01},    // WHITE_OFSET2_RIGHT :
+{0x6DB4,0x17,0x01},    // WHITE_OFSET2_LEFT :
+
+//additional code
+{0xF200,0xB9B9,0x02},
+{0xF202,0x4E12,0x02},
+{0xF204,0x6055,0x02},
+{0xF206,0x008B,0x02},
+{0xF208,0xF177,0x02},
+{0xF20A,0xFA70,0x02},
+{0xF20C,0x0000,0x02},
+{0xF20E,0x0000,0x02},
+{0xF210,0x0000,0x02},
+{0xF212,0x0000,0x02},
+{0xF214,0x0000,0x02},
+{0xF216,0x0000,0x02},
+{0xF218,0x0000,0x02},
+{0xF21A,0x0000,0x02},
+{0xF21C,0x0000,0x02},
+{0xF21E,0x0000,0x02},
+{0xF220,0x0000,0x02},
+{0xF222,0x0000,0x02},
+{0xF224,0x0000,0x02},
+{0xF226,0x0000,0x02},
+{0xF228,0x0000,0x02},
+{0xF22A,0x0000,0x02},
+{0xF22C,0x0000,0x02},
+{0xF22E,0x0000,0x02},
+{0xF230,0x0000,0x02},
+{0xF232,0x0000,0x02},
+{0xF234,0x0000,0x02},
+{0xF236,0x0000,0x02},
+{0xF238,0x0000,0x02},
+{0xF23A,0x0000,0x02},
+{0xF23C,0x0000,0x02},
+{0xF23E,0x0000,0x02},
+{0xF240,0x0000,0x02},
+{0xF242,0x0000,0x02},
+{0xF244,0xB47E,0x02},
+{0xF246,0x4808,0x02},
+{0xF248,0x7800,0x02},
+{0xF24A,0x07C0,0x02},
+{0xF24C,0x0FC0,0x02},
+{0xF24E,0xF687,0x02},
+{0xF250,0xF8ED,0x02},
+{0xF252,0xF68E,0x02},
+{0xF254,0xFE2B,0x02},
+{0xF256,0xF688,0x02},
+{0xF258,0xFF6B,0x02},
+{0xF25A,0xF693,0x02},
+{0xF25C,0xFB6B,0x02},
+{0xF25E,0xF687,0x02},
+{0xF260,0xF947,0x02},
+{0xF262,0xBC7E,0x02},
+{0xF264,0xF688,0x02},
+{0xF266,0xFD8F,0x02},
+{0xF268,0x239C,0x02},
+{0xF26A,0x0018,0x02},
+
+{0x0006,0x16,0x01},                  //INCK_SET : 24MHz
+};
+
+static const isx012_regset_t ISX012_Preview_SizeSetting[] =
+{
+{0x0090,0x0280,0x02},    //HSIZE_MONI : 640
+{0x0096,0x01E0,0x02},    //VSIZE_MONI : 480
+};
+
+static const isx012_regset_t ISX012_Preview_Mode[] =
+{
+{0x0089,0x00,0x01},    //OUTFMT_MONI
+{0x0083,0x01,0x01},    //SENSMODE_MONI
+{0x0086,0x02,0x01},    //FPSTYPE_MONI
+{0x0012,0xFF,0x01},    //INTCLR0
+{0x00F7,0x52,0x01},    // INIT_QLTY0 : Standard 82
+{0x00F8,0x59,0x01},    // INIT_QLTY1 : Fine 89
+{0x00F9,0x5F,0x01},    // INIT_QLTY2 : SuperFine 95
+{0x0081,0x00,0x01},    //MODESEL
+{0x0082,0x01,0x01},    //MONI_REFRESH
+{0xFFFF,0x1E,0x01},    //$wait,30
+};
+
+static const isx012_regset_t ISX012_Camcorder_Mode_ON[] =
+{
+//SN setting
+{0x0308,0x02,0x01},    // AELINE_MONI_SN1_2 :
+{0x0320,0x02,0x01},    // AELINE_MONI_SN1_2 :
+{0x00B2,0x02,0x01},    /* AFMODE_MONI : manual mode */
+
+//BRIGHTNESS setting
+{0x01C6,0x10,0x01},    //UIBRIGHTNESS
+
+//AE speed
+{0x02AC,0x00,0x01},    // AE_SUB_SN1 :
+{0x5E2D,0x0C,0x01},    // AEMOVECNT :
+{0x5E2E,0x20,0x01},    // AEINDEADBAND :
+{0x5E2F,0x08,0x01},    // AEOUTDEADBAND :
+{0x5E30,0xA0,0x01},    // AESPEED :
+
+{0x5E31,0x0F,0x01},    // AESPEED_INIT :
+{0x5E32,0x0F,0x01},    // AESPEED_FAST :
+
+{0x621E,0x18,0x01},    // AIM_NR_TH_UP :
+{0x621F,0x18,0x01},    // AIM_NR_TH_DOWN :
+{0x6220,0x18,0x01},    // AIM_NR_TH_RIGHT :
+{0x6221,0x18,0x01},    // AIM_NR_TH_LEFT :
+
+//AWB speed
+{0x6222,0x00,0x01},    // INIT_AIMW :
+{0x6223,0x04,0x01},    // INIT_GAINS :
+{0x6224,0x10,0x01},    // ATW_DELAY :
+{0x6225,0x00,0x01},    // ATW_AIMW :
+
+{0x6226,0x20,0x01},    // ATW_GAINS_IN_NR :
+{0x6227,0x30,0x01},    // ATW_GAINS_IN :
+{0x6228,0x20,0x01},    // ATW_GAINS_OUT_NR :
+{0x6229,0x30,0x01},    // ATW_GAINS_OUT :
+{0x622A,0x0D,0x01},    // ALLWB_GAINS :
+
+//Gammma Table 0
+{0x7000,0x0000,0x02},    // G0_KNOT_G0 :
+{0x7002,0x0000,0x02},    // G0_KNOT_G1 :
+{0x7004,0x001E,0x02},    // G0_KNOT_G2 :
+{0x7006,0x0038,0x02},    // G0_KNOT_G3 :
+{0x7008,0x0046,0x02},    // G0_KNOT_G4 :
+{0x700A,0x0053,0x02},    // G0_KNOT_G5 :
+{0x700C,0x005A,0x02},    // G0_KNOT_G6 :
+{0x700E,0x0063,0x02},    // G0_KNOT_G7 :
+{0x7010,0x006D,0x02},    // G0_KNOT_G8 :
+{0x7012,0x0076,0x02},    // G0_KNOT_G9 :
+{0x7014,0x0055,0x02},    // G0_KNOT_G10 :
+{0x7016,0x008E,0x02},    // G0_KNOT_G11 :
+{0x7018,0x00B9,0x02},    // G0_KNOT_G12 :
+{0x701A,0x00D5,0x02},    // G0_KNOT_G13 :
+{0x701C,0x00E4,0x02},    // G0_KNOT_G14 :
+{0x701E,0x00F0,0x02},    // G0_KNOT_G15 :
+{0x7020,0x00F9,0x02},    // G0_KNOT_G16 :
+{0x7022,0x0103,0x02},    // G0_KNOT_G17 :
+{0x7024,0x010C,0x02},    // G0_KNOT_G18 :
+{0x7026,0x00,0x01},    // G0_KNOT_R0_OFFSET :
+{0x7027,0x00,0x01},    // G0_KNOT_R2_OFFSET :
+{0x7028,0x00,0x01},    // G0_KNOT_R4_OFFSET :
+{0x7029,0x00,0x01},    // G0_KNOT_R6_OFFSET :
+{0x702A,0x00,0x01},    // G0_KNOT_R8_OFFSET :
+{0x702B,0x00,0x01},    // G0_KNOT_R10_OFFSET :
+{0x702C,0x00,0x01},    // G0_KNOT_R12_OFFSET :
+{0x702D,0x00,0x01},    // G0_KNOT_R14_OFFSET :
+{0x702E,0x00,0x01},    // G0_KNOT_R16_OFFSET :
+{0x702F,0x00,0x01},    // G0_KNOT_R18_OFFSET :
+{0x7030,0x00,0x01},    // G0_KNOT_B0_OFFSET :
+{0x7031,0x00,0x01},    // G0_KNOT_B2_OFFSET :
+{0x7032,0x00,0x01},    // G0_KNOT_B4_OFFSET :
+{0x7033,0x00,0x01},    // G0_KNOT_B6_OFFSET :
+{0x7034,0x00,0x01},    // G0_KNOT_B8_OFFSET :
+{0x7035,0x00,0x01},    // G0_KNOT_B10_OFFSET :
+{0x7036,0x00,0x01},    // G0_KNOT_B12_OFFSET :
+{0x7037,0x00,0x01},    // G0_KNOT_B14_OFFSET :
+{0x7038,0x00,0x01},    // G0_KNOT_B16_OFFSET :
+{0x7039,0x00,0x01},    // G0_KNOT_B18_OFFSET :
+{0x703A,0x0611,0x02},    // G0_LOWGM_ON_R :
+{0x703C,0x1E0A,0x02},    // G0_0CLIP_R :
+{0x703E,0x0611,0x02},    // G0_LOWGM_ON_G :
+{0x7040,0x1E0A,0x02},    // G0_0CLIP_G :
+{0x7042,0x0611,0x02},    // G0_LOWGM_ON_B :
+{0x7044,0x1E0A,0x02},    // G0_0CLIP_B :
+{0x7046,0x91,0x01},    // G0_KNOT_GAINCTRL_TH_L :
+{0x7047,0x96,0x01},    // G0_KNOT_GAINCTRL_TH_H :
+{0x7048,0x0000,0x02},    // G0_KNOT_L_G0 :
+{0x704A,0x0000,0x02},    // G0_KNOT_L_G1 :
+{0x704C,0x000E,0x02},    // G0_KNOT_L_G2 :
+{0x704E,0x002F,0x02},    // G0_KNOT_L_G3 :
+{0x7050,0x003D,0x02},    // G0_KNOT_L_G4 :
+{0x7052,0x004A,0x02},    // G0_KNOT_L_G5 :
+{0x7054,0x0051,0x02},    // G0_KNOT_L_G6 :
+{0x7056,0x005A,0x02},    // G0_KNOT_L_G7 :
+{0x7058,0x0061,0x02},    // G0_KNOT_L_G8 :
+{0x705A,0x006A,0x02},    // G0_KNOT_L_G9 :
+{0x705C,0x0049,0x02},    // G0_KNOT_L_G10 :
+{0x705E,0x0082,0x02},    // G0_KNOT_L_G11 :
+{0x7060,0x00AD,0x02},    // G0_KNOT_L_G12 :
+{0x7062,0x00CC,0x02},    // G0_KNOT_L_G13 :
+{0x7064,0x00E1,0x02},    // G0_KNOT_L_G14 :
+{0x7066,0x00ED,0x02},    // G0_KNOT_L_G15 :
+{0x7068,0x00F6,0x02},    // G0_KNOT_L_G16 :
+{0x706A,0x0106,0x02},    // G0_KNOT_L_G17 :
+{0x706C,0x010C,0x02},    // G0_KNOT_L_G18 :
+
+
+{0x6400,0x00,0x01},    // INFRM_LEFT00 :
+{0x6401,0x00,0x01},    // INFRM_LEFT01 :
+{0x6402,0x00,0x01},    // INFRM_LEFT02 :
+{0x6403,0x00,0x01},    // INFRM_LEFT03 :
+{0x6404,0x00,0x01},    // INFRM_LEFT04 :
+{0x6405,0x00,0x01},    // INFRM_LEFT05 :
+{0x6406,0x00,0x01},    // INFRM_LEFT06 :
+{0x6407,0x00,0x01},    // INFRM_LEFT07 :
+{0x6408,0x00,0x01},    // INFRM_LEFT08 :
+{0x6409,0x00,0x01},    // INFRM_LEFT09 :
+{0x640A,0x00,0x01},    // INFRM_LEFT10 :
+{0x640B,0x00,0x01},    // INFRM_LEFT11 :
+{0x640C,0x00,0x01},    // INFRM_LEFT12 :
+{0x640D,0x00,0x01},    // INFRM_LEFT13 :
+{0x640E,0x00,0x01},    // INFRM_LEFT14 :
+{0x640F,0x00,0x01},    // INFRM_LEFT15 :
+{0x6410,0x00,0x01},    // INFRM_LEFT16 :
+{0x6411,0x00,0x01},    // INFRM_LEFT17 :
+{0x6412,0x00,0x01},    // INFRM_LEFT18 :
+{0x6413,0x00,0x01},    // INFRM_LEFT19 :
+{0x6414,0x00,0x01},    // INFRM_LEFT20 :
+{0x6415,0x00,0x01},    // INFRM_LEFT21 :
+{0x6416,0x00,0x01},    // INFRM_LEFT22 :
+{0x6417,0x00,0x01},    // INFRM_LEFT23 :
+{0x6418,0x00,0x01},    // INFRM_LEFT24 :
+{0x6419,0x00,0x01},    // INFRM_LEFT25 :
+{0x641A,0x00,0x01},    // INFRM_LEFT26 :
+{0x641B,0x00,0x01},    // INFRM_LEFT27 :
+{0x641C,0x00,0x01},    // INFRM_LEFT28 :
+{0x641D,0x00,0x01},    // INFRM_LEFT29 :
+{0x641E,0x00,0x01},    // INFRM_LEFT30 :
+{0x641F,0x00,0x01},    // INFRM_LEFT31 :
+{0x6420,0x00,0x01},    // INFRM_LEFT32 :
+{0x6421,0x00,0x01},    // INFRM_LEFT33 :
+{0x6422,0x00,0x01},    // INFRM_LEFT34 :
+{0x6423,0x00,0x01},    // INFRM_LEFT35 :
+{0x6424,0x00,0x01},    // INFRM_LEFT36 :
+{0x6425,0x00,0x01},    // INFRM_LEFT37 :
+{0x6426,0xFF,0x01},    // INFRM_RIGHT00 :
+{0x6427,0xFF,0x01},    // INFRM_RIGHT01 :
+{0x6428,0xFF,0x01},    // INFRM_RIGHT02 :
+{0x6429,0xFF,0x01},    // INFRM_RIGHT03 :
+{0x642A,0xFF,0x01},    // INFRM_RIGHT04 :
+{0x642B,0xFF,0x01},    // INFRM_RIGHT05 :
+{0x642C,0xFF,0x01},    // INFRM_RIGHT06 :
+{0x642D,0xFF,0x01},    // INFRM_RIGHT07 :
+{0x642E,0xFF,0x01},    // INFRM_RIGHT08 :
+{0x642F,0xFF,0x01},    // INFRM_RIGHT09 :
+{0x6430,0xFF,0x01},    // INFRM_RIGHT10 :
+{0x6431,0xFF,0x01},    // INFRM_RIGHT11 :
+{0x6432,0xFF,0x01},    // INFRM_RIGHT12 :
+{0x6433,0xFF,0x01},    // INFRM_RIGHT13 :
+{0x6434,0xFF,0x01},    // INFRM_RIGHT14 :
+{0x6435,0xFF,0x01},    // INFRM_RIGHT15 :
+{0x6436,0xFF,0x01},    // INFRM_RIGHT16 :
+{0x6437,0xFF,0x01},    // INFRM_RIGHT17 :
+{0x6438,0xFF,0x01},    // INFRM_RIGHT18 :
+{0x6439,0xFF,0x01},    // INFRM_RIGHT19 :
+{0x643A,0xFF,0x01},    // INFRM_RIGHT20 :
+{0x643B,0xFF,0x01},    // INFRM_RIGHT21 :
+{0x643C,0xFF,0x01},    // INFRM_RIGHT22 :
+{0x643D,0xFF,0x01},    // INFRM_RIGHT23 :
+{0x643E,0xFF,0x01},    // INFRM_RIGHT24 :
+{0x643F,0xFF,0x01},    // INFRM_RIGHT25 :
+{0x6440,0xFF,0x01},    // INFRM_RIGHT26 :
+{0x6441,0xFF,0x01},    // INFRM_RIGHT27 :
+{0x6442,0xFF,0x01},    // INFRM_RIGHT28 :
+{0x6443,0xFF,0x01},    // INFRM_RIGHT29 :
+{0x6444,0xFF,0x01},    // INFRM_RIGHT30 :
+{0x6445,0xFF,0x01},    // INFRM_RIGHT31 :
+{0x6446,0xFF,0x01},    // INFRM_RIGHT32 :
+{0x6447,0xFF,0x01},    // INFRM_RIGHT33 :
+{0x6448,0xFF,0x01},    // INFRM_RIGHT34 :
+{0x6449,0xFF,0x01},    // INFRM_RIGHT35 :
+{0x644A,0xFF,0x01},    // INFRM_RIGHT36 :
+{0x644B,0xFF,0x01},    // INFRM_RIGHT37 :
+{0x644C,0xFFFF,0x02},	 // INFRM_TOP :
+{0x644E,0x0000,0x02},	 // INFRM_BOTM :
+{0x6450,0x25,0x01},    // INFRM_FLTOP :
+{0x6451,0x00,0x01},    // INFRM_FLBOTM :
+{0x6452,0x91,0x01},    // INAIM_LEFT00 :
+{0x6453,0x91,0x01},    // INAIM_LEFT01 :
+{0x6454,0x91,0x01},    // INAIM_LEFT02 :
+{0x6455,0x91,0x01},    // INAIM_LEFT03 :
+{0x6456,0x91,0x01},    // INAIM_LEFT04 :
+{0x6457,0x91,0x01},    // INAIM_LEFT05 :
+{0x6458,0x91,0x01},    // INAIM_LEFT06 :
+{0x6459,0x91,0x01},    // INAIM_LEFT07 :
+{0x645A,0x91,0x01},    // INAIM_LEFT08 :
+{0x645B,0x91,0x01},    // INAIM_LEFT09 :
+{0x645C,0x91,0x01},    // INAIM_LEFT10 :
+{0x645D,0x91,0x01},    // INAIM_LEFT11 :
+{0x645E,0x91,0x01},    // INAIM_LEFT12 :
+{0x645F,0x66,0x01},    // INAIM_LEFT13 :
+{0x6460,0x5D,0x01},    // INAIM_LEFT14 :
+{0x6461,0x69,0x01},    // INAIM_LEFT15 :
+{0x6462,0x54,0x01},    // INAIM_LEFT16 :
+{0x6463,0x4B,0x01},    // INAIM_LEFT17 :
+{0x6464,0x42,0x01},    // INAIM_LEFT18 :
+{0x6465,0x3C,0x01},    // INAIM_LEFT19 :
+{0x6466,0x38,0x01},    // INAIM_LEFT20 :
+{0x6467,0x36,0x01},    // INAIM_LEFT21 :
+{0x6468,0x35,0x01},    // INAIM_LEFT22 :
+{0x6469,0x33,0x01},    // INAIM_LEFT23 :
+{0x646A,0x32,0x01},    // INAIM_LEFT24 :
+{0x646B,0x30,0x01},    // INAIM_LEFT25 :
+{0x646C,0x2F,0x01},    // INAIM_LEFT26 :
+{0x646D,0x2D,0x01},    // INAIM_LEFT27 :
+{0x646E,0x2C,0x01},    // INAIM_LEFT28 :
+{0x646F,0x2B,0x01},    // INAIM_LEFT29 :
+{0x6470,0x2A,0x01},    // INAIM_LEFT30 :
+{0x6471,0x28,0x01},    // INAIM_LEFT31 :
+{0x6472,0x26,0x01},    // INAIM_LEFT32 :
+{0x6473,0x24,0x01},    // INAIM_LEFT33 :
+{0x6474,0x29,0x01},    // INAIM_LEFT34 :
+{0x6475,0x28,0x01},    // INAIM_LEFT35 :
+{0x6476,0x29,0x01},    // INAIM_LEFT36 :
+{0x6477,0x26,0x01},    // INAIM_LEFT37 :
+{0x6478,0xFF,0x01},    // INAIM_RIGHT00 :
+{0x6479,0xFF,0x01},    // INAIM_RIGHT01 :
+{0x647A,0xFF,0x01},    // INAIM_RIGHT02 :
+{0x647B,0xFF,0x01},    // INAIM_RIGHT03 :
+{0x647C,0xFF,0x01},    // INAIM_RIGHT04 :
+{0x647D,0xFF,0x01},    // INAIM_RIGHT05 :
+{0x647E,0xFF,0x01},    // INAIM_RIGHT06 :
+{0x647F,0xFF,0x01},    // INAIM_RIGHT07 :
+{0x6480,0xFF,0x01},    // INAIM_RIGHT08 :
+{0x6481,0xFF,0x01},    // INAIM_RIGHT09 :
+{0x6482,0xD9,0x01},    // INAIM_RIGHT10 :
+{0x6483,0xB7,0x01},    // INAIM_RIGHT11 :
+{0x6484,0x96,0x01},    // INAIM_RIGHT12 :
+{0x6485,0x68,0x01},    // INAIM_RIGHT13 :
+{0x6486,0x70,0x01},    // INAIM_RIGHT14 :
+{0x6487,0x72,0x01},    // INAIM_RIGHT15 :
+{0x6488,0x71,0x01},    // INAIM_RIGHT16 :
+{0x6489,0x6B,0x01},    // INAIM_RIGHT17 :
+{0x648A,0x65,0x01},    // INAIM_RIGHT18 :
+{0x648B,0x60,0x01},    // INAIM_RIGHT19 :
+{0x648C,0x5B,0x01},    // INAIM_RIGHT20 :
+{0x648D,0x56,0x01},    // INAIM_RIGHT21 :
+{0x648E,0x51,0x01},    // INAIM_RIGHT22 :
+{0x648F,0x4C,0x01},    // INAIM_RIGHT23 :
+{0x6490,0x47,0x01},    // INAIM_RIGHT24 :
+{0x6491,0x44,0x01},    // INAIM_RIGHT25 :
+{0x6492,0x41,0x01},    // INAIM_RIGHT26 :
+{0x6493,0x3E,0x01},    // INAIM_RIGHT27 :
+{0x6494,0x3B,0x01},    // INAIM_RIGHT28 :
+{0x6495,0x39,0x01},    // INAIM_RIGHT29 :
+{0x6496,0x37,0x01},    // INAIM_RIGHT30 :
+{0x6497,0x34,0x01},    // INAIM_RIGHT31 :
+{0x6498,0x33,0x01},    // INAIM_RIGHT32 :
+{0x6499,0x32,0x01},    // INAIM_RIGHT33 :
+{0x649A,0x31,0x01},    // INAIM_RIGHT34 :
+{0x649B,0x30,0x01},    // INAIM_RIGHT35 :
+{0x649C,0x2F,0x01},    // INAIM_RIGHT36 :
+{0x649D,0x2E,0x01},    // INAIM_RIGHT37 :
+{0x649E,0x1E00,0x02},	 // INAIM_TOP :
+{0x64A0,0x0F48,0x02},	 // INAIM_BOTM :
+{0x64A2,0x18,0x01},    // INAIM_FLTOP :
+{0x64A3,0x11,0x01},    // INAIM_FLBOTM :
+{0x64A4,0x00,0x01},   // OUTFRM_LEFT00 :
+{0x64A5,0x00,0x01},   // OUTFRM_LEFT01 :
+{0x64A6,0x00,0x01},   // OUTFRM_LEFT02 :
+{0x64A7,0x00,0x01},   // OUTFRM_LEFT03 :
+{0x64A8,0x00,0x01},   // OUTFRM_LEFT04 :
+{0x64A9,0x00,0x01},   // OUTFRM_LEFT05 :
+{0x64AA,0x00,0x01},   // OUTFRM_LEFT06 :
+{0x64AB,0x00,0x01},   // OUTFRM_LEFT07 :
+{0x64AC,0x00,0x01},   // OUTFRM_LEFT08 :
+{0x64AD,0x00,0x01},   // OUTFRM_LEFT09 :
+{0x64AE,0x00,0x01},   // OUTFRM_LEFT10 :
+{0x64AF,0x00,0x01},   // OUTFRM_LEFT11 :
+{0x64B0,0x00,0x01},   // OUTFRM_LEFT12 :
+{0x64B1,0x00,0x01},   // OUTFRM_LEFT13 :
+{0x64B2,0x00,0x01},   // OUTFRM_LEFT14 :
+{0x64B3,0x00,0x01},   // OUTFRM_LEFT15 :
+{0x64B4,0x00,0x01},   // OUTFRM_LEFT16 :
+{0x64B5,0x00,0x01},   // OUTFRM_LEFT17 :
+{0x64B6,0x00,0x01},   // OUTFRM_LEFT18 :
+{0x64B7,0x00,0x01},   // OUTFRM_LEFT19 :
+{0x64B8,0x00,0x01},   // OUTFRM_LEFT20 :
+{0x64B9,0x00,0x01},   // OUTFRM_LEFT21 :
+{0x64BA,0x00,0x01},   // OUTFRM_LEFT22 :
+{0x64BB,0x00,0x01},   // OUTFRM_LEFT23 :
+{0x64BC,0x00,0x01},   // OUTFRM_LEFT24 :
+{0x64BD,0x00,0x01},   // OUTFRM_LEFT25 :
+{0x64BE,0x00,0x01},   // OUTFRM_LEFT26 :
+{0x64BF,0x00,0x01},   // OUTFRM_LEFT27 :
+{0x64C0,0x00,0x01},   // OUTFRM_LEFT28 :
+{0x64C1,0x00,0x01},   // OUTFRM_LEFT29 :
+{0x64C2,0x00,0x01},   // OUTFRM_LEFT30 :
+{0x64C3,0x00,0x01},   // OUTFRM_LEFT31 :
+{0x64C4,0x00,0x01},   // OUTFRM_LEFT32 :
+{0x64C5,0x00,0x01},   // OUTFRM_LEFT33 :
+{0x64C6,0x00,0x01},   // OUTFRM_LEFT34 :
+{0x64C7,0x00,0x01},   // OUTFRM_LEFT35 :
+{0x64C8,0x00,0x01},   // OUTFRM_LEFT36 :
+{0x64C9,0x00,0x01},   // OUTFRM_LEFT37 :
+{0x64CA,0xFF,0x01},   // OUTFRM_RIGHT00 :
+{0x64CB,0xFF,0x01},   // OUTFRM_RIGHT01 :
+{0x64CC,0xFF,0x01},   // OUTFRM_RIGHT02 :
+{0x64CD,0xFF,0x01},   // OUTFRM_RIGHT03 :
+{0x64CE,0xFF,0x01},   // OUTFRM_RIGHT04 :
+{0x64CF,0xFF,0x01},   // OUTFRM_RIGHT05 :
+{0x64D0,0xFF,0x01},   // OUTFRM_RIGHT06 :
+{0x64D1,0xFF,0x01},   // OUTFRM_RIGHT07 :
+{0x64D2,0xFF,0x01},   // OUTFRM_RIGHT08 :
+{0x64D3,0xFF,0x01},   // OUTFRM_RIGHT09 :
+{0x64D4,0xFF,0x01},   // OUTFRM_RIGHT10 :
+{0x64D5,0xFF,0x01},   // OUTFRM_RIGHT11 :
+{0x64D6,0xFF,0x01},   // OUTFRM_RIGHT12 :
+{0x64D7,0xFF,0x01},   // OUTFRM_RIGHT13 :
+{0x64D8,0xFF,0x01},   // OUTFRM_RIGHT14 :
+{0x64D9,0xFF,0x01},   // OUTFRM_RIGHT15 :
+{0x64DA,0xFF,0x01},   // OUTFRM_RIGHT16 :
+{0x64DB,0xFF,0x01},   // OUTFRM_RIGHT17 :
+{0x64DC,0xFF,0x01},   // OUTFRM_RIGHT18 :
+{0x64DD,0xFF,0x01},   // OUTFRM_RIGHT19 :
+{0x64DE,0xFF,0x01},   // OUTFRM_RIGHT20 :
+{0x64DF,0xFF,0x01},   // OUTFRM_RIGHT21 :
+{0x64E0,0xFF,0x01},   // OUTFRM_RIGHT22 :
+{0x64E1,0xFF,0x01},   // OUTFRM_RIGHT23 :
+{0x64E2,0xFF,0x01},   // OUTFRM_RIGHT24 :
+{0x64E3,0xFF,0x01},   // OUTFRM_RIGHT25 :
+{0x64E4,0xFF,0x01},   // OUTFRM_RIGHT26 :
+{0x64E5,0xFF,0x01},   // OUTFRM_RIGHT27 :
+{0x64E6,0xFF,0x01},   // OUTFRM_RIGHT28 :
+{0x64E7,0xFF,0x01},   // OUTFRM_RIGHT29 :
+{0x64E8,0xFF,0x01},   // OUTFRM_RIGHT30 :
+{0x64E9,0xFF,0x01},   // OUTFRM_RIGHT31 :
+{0x64EA,0xFF,0x01},   // OUTFRM_RIGHT32 :
+{0x64EB,0xFF,0x01},   // OUTFRM_RIGHT33 :
+{0x64EC,0xFF,0x01},   // OUTFRM_RIGHT34 :
+{0x64ED,0xFF,0x01},   // OUTFRM_RIGHT35 :
+{0x64EE,0xFF,0x01},   // OUTFRM_RIGHT36 :
+{0x64EF,0xFF,0x01},   // OUTFRM_RIGHT37 :
+{0x64F0,0x24F0,0x02},	// OUTFRM_TOP :
+{0x64F2,0x1400,0x02},	// OUTFRM_BOTM :
+{0x64F4,0x37,0x01},   // OUTFRM_FLTOP :
+{0x64F5,0x00,0x01},   // OUTFRM_FLBOTM :
+
+//AWB
+{0x6232,0x07,0x01},//ATW_SFTLMT_OUT_NR
+{0x6234,0x05,0x01},//ATW_SFTLMT_OUT
+
+/////MC3 Setting/////
+{0x7600,0x07,0x01},    // MC3_PXDEF0_SEL :
+{0x7601,0x07,0x01},    // MC3_PYDEF0_SEL :
+{0x7602,0x07,0x01},    // MC3_PXDEF1_SEL :
+{0x7603,0x07,0x01},    // MC3_PYDEF1_SEL :
+{0x7604,0x07,0x01},    // MC3_PXDEF2_SEL :
+{0x7605,0x07,0x01},    // MC3_PYDEF2_SEL :
+{0x7606,0x07,0x01},    // MC3_PXDEF3_SEL :
+{0x7607,0x07,0x01},    // MC3_PYDEF3_SEL :
+{0x7608,0x40,0x01},    // MC3_PXDEF0_A :
+{0x7609,0x40,0x01},    // MC3_PXDEF0_B :
+{0x760A,0x40,0x01},    // MC3_PXDEF0_C :
+{0x760B,0x40,0x01},    // MC3_PYDEF0_A :
+{0x760C,0x40,0x01},    // MC3_PYDEF0_B :
+{0x760D,0x40,0x01},    // MC3_PYDEF0_C :
+{0x760E,0x40,0x01},    // MC3_PXDEF1_A :
+{0x760F,0x40,0x01},    // MC3_PXDEF1_B :
+{0x7610,0x40,0x01},    // MC3_PXDEF1_C :
+{0x7611,0x40,0x01},    // MC3_PYDEF1_A :
+{0x7612,0x40,0x01},    // MC3_PYDEF1_B :
+{0x7613,0x40,0x01},    // MC3_PYDEF1_C :
+{0x7614,0x40,0x01},    // MC3_PXDEF2_A :
+{0x7615,0x40,0x01},    // MC3_PXDEF2_B :
+{0x7616,0x40,0x01},    // MC3_PXDEF2_C :
+{0x7617,0x40,0x01},    // MC3_PYDEF2_A :
+{0x7618,0x40,0x01},    // MC3_PYDEF2_B :
+{0x7619,0x40,0x01},    // MC3_PYDEF2_C :
+{0x761A,0x40,0x01},    // MC3_PXDEF3_A :
+{0x761B,0x40,0x01},    // MC3_PXDEF3_B :
+{0x761C,0x40,0x01},    // MC3_PXDEF3_C :
+{0x761D,0x40,0x01},    // MC3_PYDEF3_A :
+{0x761E,0x40,0x01},    // MC3_PYDEF3_B :
+{0x761F,0x40,0x01},    // MC3_PYDEF3_C :
+{0x7620,0x00,0x01},    // MC3_LUMSL0_IN :
+{0x7621,0x06,0x01},    // MC3_LUMSL1_IN :
+{0x7622,0x03,0x01},    // MC3_LUMSL2_IN :
+{0x7623,0x06,0x01},    // MC3_LUMSL3_IN :
+{0x7624,0x00,0x01},    // MC3_LUMSL0_OUT :
+{0x7625,0x03,0x01},    // MC3_LUMSL1_OUT :
+{0x7626,0x00,0x01},    // MC3_LUMSL2_OUT :
+{0x7627,0x00,0x01},    // MC3_LUMSL3_OUT :
+{0x7628,0x0000,0x02},    // MC3_L0DEF0_IN :
+{0x762A,0x008C,0x02},    // MC3_L0DEF1_IN :
+{0x762C,0x0078,0x02},    // MC3_L0DEF2_IN :
+{0x762E,0x00E6,0x02},    // MC3_L0DEF3_IN :
+{0x7630,0x0000,0x02},    // MC3_L0DEF0_OUT :
+{0x7632,0x0082,0x02},    // MC3_L0DEF1_OUT :
+{0x7634,0x0000,0x02},    // MC3_L0DEF2_OUT :
+{0x7636,0x0000,0x02},    // MC3_L0DEF3_OUT :
+{0x7638,0x41,0x01},    // MC3_RDEF0_POS1 :
+{0x7639,0x10,0x01},    // MC3_RDEF1_POS1 :
+{0x763A,0x15,0x01},    // MC3_RDEF2_POS1 :
+{0x763B,0x71,0x01},    // MC3_RDEF3_POS1 :
+{0x763C,0x41,0x01},    // MC3_RDEF0_POS2 :
+{0x763D,0x10,0x01},    // MC3_RDEF1_POS2 :
+{0x763E,0x15,0x01},    // MC3_RDEF2_POS2 :
+{0x763F,0x71,0x01},    // MC3_RDEF3_POS2 :
+{0x7640,0x3C,0x01},    // MC3_RDEF0_POS3 :
+{0x7641,0x10,0x01},    // MC3_RDEF1_POS3 :
+{0x7642,0x15,0x01},    // MC3_RDEF2_POS3 :
+{0x7643,0x71,0x01},    // MC3_RDEF3_POS3 :
+{0x7644,0x46,0x01},    // MC3_RDEF0_POS4 :
+{0x7645,0x32,0x01},    // MC3_RDEF1_POS4 :
+{0x7646,0x15,0x01},    // MC3_RDEF2_POS4 :
+{0x7647,0x71,0x01},    // MC3_RDEF3_POS4 :
+{0x7648,0x46,0x01},    // MC3_RDEF0_POS5 :
+{0x7649,0x32,0x01},    // MC3_RDEF1_POS5 :
+{0x764A,0x15,0x01},    // MC3_RDEF2_POS5 :
+{0x764B,0x71,0x01},    // MC3_RDEF3_POS5 :
+{0x764C,0x46,0x01},    // MC3_RDEF0_POS6 :
+{0x764D,0x10,0x01},    // MC3_RDEF1_POS6 :
+{0x764E,0x15,0x01},    // MC3_RDEF2_POS6 :
+{0x764F,0x71,0x01},    // MC3_RDEF3_POS6 :
+{0x7650,0x46,0x01},    // MC3_RDEF0_POS7 :
+{0x7651,0x10,0x01},    // MC3_RDEF1_POS7 :
+{0x7652,0x15,0x01},    // MC3_RDEF2_POS7 :
+{0x7653,0x71,0x01},    // MC3_RDEF3_POS7 :
+{0x7654,0x2D,0x01},    // MC3_RDEF0_OUT :
+{0x7655,0x10,0x01},    // MC3_RDEF1_OUT :
+{0x7656,0x15,0x01},    // MC3_RDEF2_OUT :
+{0x7657,0x54,0x01},    // MC3_RDEF3_OUT :
+{0x7658,0x46,0x01},    // MC3_RDEF0_R2_POS4 :
+{0x7659,0x32,0x01},    // MC3_RDEF1_R2_POS4 :
+{0x765A,0x15,0x01},    // MC3_RDEF2_R2_POS4 :
+{0x765B,0x71,0x01},    // MC3_RDEF3_R2_POS4 :
+{0x765C,0x46,0x01},    // MC3_RDEF0_R2_POS5 :
+{0x765D,0x32,0x01},    // MC3_RDEF1_R2_POS5 :
+{0x765E,0x15,0x01},    // MC3_RDEF2_R2_POS5 :
+{0x765F,0x71,0x01},    // MC3_RDEF3_R2_POS5 :
+{0x7660,0xFFBA,0x02},    // MC3_X0DEF0_POS1 :
+{0x7662,0xFFBA,0x02},    // MC3_Y0DEF0_POS1 :
+{0x7664,0xFFFE,0x02},    // MC3_X0DEF1_POS1 :
+{0x7666,0x000D,0x02},    // MC3_Y0DEF1_POS1 :
+{0x7668,0x0002,0x02},    // MC3_X0DEF2_POS1 :
+{0x766A,0xFFF6,0x02},    // MC3_Y0DEF2_POS1 :
+{0x766C,0x003B,0x02},    // MC3_X0DEF3_POS1 :
+{0x766E,0xFFBB,0x02},    // MC3_Y0DEF3_POS1 :
+{0x7670,0xFFBA,0x02},    // MC3_X0DEF0_POS2 :
+{0x7672,0xFFBA,0x02},    // MC3_Y0DEF0_POS2 :
+{0x7674,0xFFFE,0x02},    // MC3_X0DEF1_POS2 :
+{0x7676,0x000D,0x02},    // MC3_Y0DEF1_POS2 :
+{0x7678,0x0002,0x02},    // MC3_X0DEF2_POS2 :
+{0x767A,0xFFF6,0x02},    // MC3_Y0DEF2_POS2 :
+{0x767C,0x003B,0x02},    // MC3_X0DEF3_POS2 :
+{0x767E,0xFFBB,0x02},    // MC3_Y0DEF3_POS2 :
+{0x7680,0xFFCE,0x02},    // MC3_X0DEF0_POS3 :
+{0x7682,0xFFBA,0x02},    // MC3_Y0DEF0_POS3 :
+{0x7684,0xFFFE,0x02},    // MC3_X0DEF1_POS3 :
+{0x7686,0x000D,0x02},    // MC3_Y0DEF1_POS3 :
+{0x7688,0x0002,0x02},    // MC3_X0DEF2_POS3 :
+{0x768A,0xFFF6,0x02},    // MC3_Y0DEF2_POS3 :
+{0x768C,0x003B,0x02},    // MC3_X0DEF3_POS3 :
+{0x768E,0xFFBB,0x02},    // MC3_Y0DEF3_POS3 :
+{0x7690,0xFFCE,0x02},    // MC3_X0DEF0_POS4 :
+{0x7692,0xFFC9,0x02},    // MC3_Y0DEF0_POS4 :
+{0x7694,0xFFD0,0x02},    // MC3_X0DEF1_POS4 :
+{0x7696,0x0037,0x02},    // MC3_Y0DEF1_POS4 :
+{0x7698,0x0002,0x02},    // MC3_X0DEF2_POS4 :
+{0x769A,0xFFF6,0x02},    // MC3_Y0DEF2_POS4 :
+{0x769C,0x003B,0x02},    // MC3_X0DEF3_POS4 :
+{0x769E,0xFFBB,0x02},    // MC3_Y0DEF3_POS4 :
+{0x76A0,0xFFCE,0x02},    // MC3_X0DEF0_POS5 :
+{0x76A2,0xFFC9,0x02},    // MC3_Y0DEF0_POS5 :
+{0x76A4,0xFFD0,0x02},    // MC3_X0DEF1_POS5 :
+{0x76A6,0x0037,0x02},    // MC3_Y0DEF1_POS5 :
+{0x76A8,0x0002,0x02},    // MC3_X0DEF2_POS5 :
+{0x76AA,0xFFF6,0x02},    // MC3_Y0DEF2_POS5 :
+{0x76AC,0x003B,0x02},    // MC3_X0DEF3_POS5 :
+{0x76AE,0xFFBB,0x02},    // MC3_Y0DEF3_POS5 :
+{0x76B0,0xFFCE,0x02},    // MC3_X0DEF0_POS6 :
+{0x76B2,0xFFC9,0x02},    // MC3_Y0DEF0_POS6 :
+{0x76B4,0xFFFE,0x02},    // MC3_X0DEF1_POS6 :
+{0x76B6,0x000D,0x02},    // MC3_Y0DEF1_POS6 :
+{0x76B8,0x0002,0x02},    // MC3_X0DEF2_POS6 :
+{0x76BA,0xFFF6,0x02},    // MC3_Y0DEF2_POS6 :
+{0x76BC,0x003B,0x02},    // MC3_X0DEF3_POS6 :
+{0x76BE,0xFFBB,0x02},    // MC3_Y0DEF3_POS6 :
+{0x76C0,0xFFCE,0x02},    // MC3_X0DEF0_POS7 :
+{0x76C2,0xFFC9,0x02},    // MC3_Y0DEF0_POS7 :
+{0x76C4,0xFFFE,0x02},    // MC3_X0DEF1_POS7 :
+{0x76C6,0x000D,0x02},    // MC3_Y0DEF1_POS7 :
+{0x76C8,0x0002,0x02},    // MC3_X0DEF2_POS7 :
+{0x76CA,0xFFF6,0x02},    // MC3_Y0DEF2_POS7 :
+{0x76CC,0x003B,0x02},    // MC3_X0DEF3_POS7 :
+{0x76CE,0xFFBB,0x02},    // MC3_Y0DEF3_POS7 :
+{0x76D0,0xFF7E,0x02},    // MC3_X0DEF0_OUT :
+{0x76D2,0xFFE2,0x02},    // MC3_Y0DEF0_OUT :
+{0x76D4,0xFFFE,0x02},    // MC3_X0DEF1_OUT :
+{0x76D6,0x000D,0x02},    // MC3_Y0DEF1_OUT :
+{0x76D8,0x0002,0x02},    // MC3_X0DEF2_OUT :
+{0x76DA,0xFFF6,0x02},    // MC3_Y0DEF2_OUT :
+{0x76DC,0xFFC4,0x02},    // MC3_X0DEF3_OUT :
+{0x76DE,0xFFEC,0x02},    // MC3_Y0DEF3_OUT :
+{0x76E0,0xFFCE,0x02},    // MC3_X0DEF0_R2_POS4 :
+{0x76E2,0xFFC9,0x02},    // MC3_Y0DEF0_R2_POS4 :
+{0x76E4,0xFFD0,0x02},    // MC3_X0DEF1_R2_POS4 :
+{0x76E6,0x0037,0x02},    // MC3_Y0DEF1_R2_POS4 :
+{0x76E8,0x0002,0x02},    // MC3_X0DEF2_R2_POS4 :
+{0x76EA,0xFFF6,0x02},    // MC3_Y0DEF2_R2_POS4 :
+{0x76EC,0x003B,0x02},    // MC3_X0DEF3_R2_POS4 :
+{0x76EE,0xFFBB,0x02},    // MC3_Y0DEF3_R2_POS4 :
+{0x76F0,0xFFCE,0x02},    // MC3_X0DEF0_R2_POS5 :
+{0x76F2,0xFFC9,0x02},    // MC3_Y0DEF0_R2_POS5 :
+{0x76F4,0xFFD0,0x02},    // MC3_X0DEF1_R2_POS5 :
+{0x76F6,0x0037,0x02},    // MC3_Y0DEF1_R2_POS5 :
+{0x76F8,0x0002,0x02},    // MC3_X0DEF2_R2_POS5 :
+{0x76FA,0xFFF6,0x02},    // MC3_Y0DEF2_R2_POS5 :
+{0x76FC,0x003B,0x02},    // MC3_X0DEF3_R2_POS5 :
+{0x76FE,0xFFBB,0x02},    // MC3_Y0DEF3_R2_POS5 :
+{0x7700,0x0019,0x02},    // MC3_PXDEF0_POS1 :
+{0x7702,0xFF66,0x02},    // MC3_PYDEF0_POS1 :
+{0x7704,0x0000,0x02},    // MC3_PXDEF1_POS1 :
+{0x7706,0x0000,0x02},    // MC3_PYDEF1_POS1 :
+{0x7708,0x0000,0x02},    // MC3_PXDEF2_POS1 :
+{0x770A,0x0000,0x02},    // MC3_PYDEF2_POS1 :
+{0x770C,0xFFD7,0x02},    // MC3_PXDEF3_POS1 :
+{0x770E,0x0068,0x02},    // MC3_PYDEF3_POS1 :
+{0x7710,0x0000,0x02},    // MC3_PXDEF0_POS2 :
+{0x7712,0xFF66,0x02},    // MC3_PYDEF0_POS2 :
+{0x7714,0x0033,0x02},    // MC3_PXDEF1_POS2 :
+{0x7716,0xFF4C,0x02},    // MC3_PYDEF1_POS2 :
+{0x7718,0x0000,0x02},    // MC3_PXDEF2_POS2 :
+{0x771A,0x00B3,0x02},    // MC3_PYDEF2_POS2 :
+{0x771C,0xFFD7,0x02},    // MC3_PXDEF3_POS2 :
+{0x771E,0x0068,0x02},    // MC3_PYDEF3_POS2 :
+{0x7720,0x0000,0x02},    // MC3_PXDEF0_POS3 :
+{0x7722,0xFF80,0x02},    // MC3_PYDEF0_POS3 :
+{0x7724,0x0000,0x02},    // MC3_PXDEF1_POS3 :
+{0x7726,0x0000,0x02},    // MC3_PYDEF1_POS3 :
+{0x7728,0x0000,0x02},    // MC3_PXDEF2_POS3 :
+{0x772A,0x0000,0x02},    // MC3_PYDEF2_POS3 :
+{0x772C,0xFFD7,0x02},    // MC3_PXDEF3_POS3 :
+{0x772E,0x0068,0x02},    // MC3_PYDEF3_POS3 :
+{0x7730,0x0000,0x02},    // MC3_PXDEF0_POS4 :
+{0x7732,0xFFCC,0x02},    // MC3_PYDEF0_POS4 :
+{0x7734,0x0000,0x02},    // MC3_PXDEF1_POS4 :
+{0x7736,0x0000,0x02},    // MC3_PYDEF1_POS4 :
+{0x7738,0x0000,0x02},    // MC3_PXDEF2_POS4 :
+{0x773A,0x0000,0x02},    // MC3_PYDEF2_POS4 :
+{0x773C,0xFFD7,0x02},    // MC3_PXDEF3_POS4 :
+{0x773E,0x0068,0x02},    // MC3_PYDEF3_POS4 :
+{0x7740,0x0000,0x02},    // MC3_PXDEF0_POS5 :
+{0x7742,0xFFCC,0x02},    // MC3_PYDEF0_POS5 :
+{0x7744,0x0000,0x02},    // MC3_PXDEF1_POS5 :
+{0x7746,0x0000,0x02},    // MC3_PYDEF1_POS5 :
+{0x7748,0x0000,0x02},    // MC3_PXDEF2_POS5 :
+{0x774A,0x0000,0x02},    // MC3_PYDEF2_POS5 :
+{0x774C,0xFFD7,0x02},    // MC3_PXDEF3_POS5 :
+{0x774E,0x0068,0x02},    // MC3_PYDEF3_POS5 :
+{0x7750,0xFFB3,0x02},    // MC3_PXDEF0_POS6 :
+{0x7752,0x0000,0x02},    // MC3_PYDEF0_POS6 :
+{0x7754,0x0033,0x02},    // MC3_PXDEF1_POS6 :
+{0x7756,0xFF4C,0x02},    // MC3_PYDEF1_POS6 :
+{0x7758,0x0000,0x02},    // MC3_PXDEF2_POS6 :
+{0x775A,0x00B3,0x02},    // MC3_PYDEF2_POS6 :
+{0x775C,0xFFD7,0x02},    // MC3_PXDEF3_POS6 :
+{0x775E,0x0068,0x02},    // MC3_PYDEF3_POS6 :
+{0x7760,0xFFB3,0x02},    // MC3_PXDEF0_POS7 :
+{0x7762,0x0000,0x02},    // MC3_PYDEF0_POS7 :
+{0x7764,0x0000,0x02},    // MC3_PXDEF1_POS7 :
+{0x7766,0x0000,0x02},    // MC3_PYDEF1_POS7 :
+{0x7768,0x0000,0x02},    // MC3_PXDEF2_POS7 :
+{0x776A,0x0000,0x02},    // MC3_PYDEF2_POS7 :
+{0x776C,0xFFD7,0x02},    // MC3_PXDEF3_POS7 :
+{0x776E,0x0068,0x02},    // MC3_PYDEF3_POS7 :
+{0x7770,0x0019,0x02},    // MC3_PXDEF0_OUT :
+{0x7772,0xFFE6,0x02},    // MC3_PYDEF0_OUT :
+{0x7774,0x0000,0x02},    // MC3_PXDEF1_OUT :
+{0x7776,0x0000,0x02},    // MC3_PYDEF1_OUT :
+{0x7778,0x0000,0x02},    // MC3_PXDEF2_OUT :
+{0x777A,0x0000,0x02},    // MC3_PYDEF2_OUT :
+{0x777C,0xFFE1,0x02},    // MC3_PXDEF3_OUT :
+{0x777E,0xFFEB,0x02},    // MC3_PYDEF3_OUT :
+{0x7780,0x0000,0x02},    // MC3_PXDEF0_R2_POS4 :
+{0x7782,0xFFCC,0x02},    // MC3_PYDEF0_R2_POS4 :
+{0x7784,0x0000,0x02},    // MC3_PXDEF1_R2_POS4 :
+{0x7786,0x0000,0x02},    // MC3_PYDEF1_R2_POS4 :
+{0x7788,0x0000,0x02},    // MC3_PXDEF2_R2_POS4 :
+{0x778A,0x0000,0x02},    // MC3_PYDEF2_R2_POS4 :
+{0x778C,0xFFD7,0x02},    // MC3_PXDEF3_R2_POS4 :
+{0x778E,0x0068,0x02},    // MC3_PYDEF3_R2_POS4 :
+{0x7790,0x0000,0x02},    // MC3_PXDEF0_R2_POS5 :
+{0x7792,0xFFCC,0x02},    // MC3_PYDEF0_R2_POS5 :
+{0x7794,0x0000,0x02},    // MC3_PXDEF1_R2_POS5 :
+{0x7796,0x0000,0x02},    // MC3_PYDEF1_R2_POS5 :
+{0x7798,0x0000,0x02},    // MC3_PXDEF2_R2_POS5 :
+{0x779A,0x0000,0x02},    // MC3_PYDEF2_R2_POS5 :
+{0x779C,0xFFD7,0x02},    // MC3_PXDEF3_R2_POS5 :
+{0x779E,0x0068,0x02},    // MC3_PYDEF3_R2_POS5 :
+
+};
+
+static const isx012_regset_t ISX012_Camcorder_Mode_OFF[] = {
+//SN setting
+{0x0308,0x11,0x01},    // AELINE_MONI_SN1_2 :
+{0x0320,0x22,0x01},    // AELINE_MONI_SN1_2 :
+{0x00B2,0x02,0x01},    // AFMODE_MONI :
+//BRIGHTNESS setting
+{0x01C6,0x00,0x01},    // UIBRIGHTNESS
+//AE speed
+{0x02AC,0x01,0x01},    // AE_SUB_SN1 :
+{0x5E2D,0x08,0x01},    // AEMOVECNT :
+{0x5E2E,0x1A,0x01},    // AEINDEADBAND :
+{0x5E2F,0x04,0x01},    // AEOUTDEADBAND :
+{0x5E30,0x20,0x01},    // AESPEED :
+{0x5E31,0x0F,0x01},    // AESPEED_INIT :
+{0x5E32,0x0F,0x01},    // AESPEED_FAST :
+{0x621E,0x20,0x01},    // AIM_NR_TH_UP :
+{0x621F,0x20,0x01},    // AIM_NR_TH_DOWN :
+{0x6220,0x20,0x01},    // AIM_NR_TH_RIGHT :
+{0x6221,0x20,0x01},    // AIM_NR_TH_LEFT :
+//AWB speed
+{0x6222,0x00,0x01},    // INIT_AIMW :
+{0x6223,0x04,0x01},    // INIT_GAINS :
+{0x6224,0x04,0x01},    // ATW_DELAY :
+{0x6225,0x00,0x01},    // ATW_AIMW :
+{0x6226,0x08,0x01},    // ATW_GAINS_IN_NR :
+{0x6227,0x04,0x01},    // ATW_GAINS_IN :
+{0x6228,0x08,0x01},    // ATW_GAINS_OUT_NR :
+{0x6229,0x04,0x01},    // ATW_GAINS_OUT :
+{0x622A,0x02,0x01},    // ALLWB_GAINS :
+//Gammma Table 0
+{0x7000,0x0000,0x02},	 // G0_KNOT_G0 :
+{0x7002,0x0015,0x02},	 // G0_KNOT_G1 :
+{0x7004,0x002C,0x02},	 // G0_KNOT_G2 :
+{0x7006,0x0041,0x02},	 // G0_KNOT_G3 :
+{0x7008,0x004D,0x02},	 // G0_KNOT_G4 :
+{0x700A,0x005B,0x02},	 // G0_KNOT_G5 :
+{0x700C,0x0060,0x02},	 // G0_KNOT_G6 :
+{0x700E,0x0068,0x02},	 // G0_KNOT_G7 :
+{0x7010,0x006F,0x02},	 // G0_KNOT_G8 :
+{0x7012,0x0078,0x02},	 // G0_KNOT_G9 :
+{0x7014,0x0057,0x02},	 // G0_KNOT_G10 :
+{0x7016,0x0090,0x02},	 // G0_KNOT_G11 :
+{0x7018,0x00BB,0x02},	 // G0_KNOT_G12 :
+{0x701A,0x00D6,0x02},	 // G0_KNOT_G13 :
+{0x701C,0x00E5,0x02},	 // G0_KNOT_G14 :
+{0x701E,0x00F0,0x02},	 // G0_KNOT_G15 :
+{0x7020,0x00F9,0x02},	 // G0_KNOT_G16 :
+{0x7022,0x0103,0x02},	 // G0_KNOT_G17 :
+{0x7024,0x010C,0x02},	 // G0_KNOT_G18 :
+{0x7026,0x00,0x01},    // G0_KNOT_R0_OFFSET :
+{0x7027,0x00,0x01},    // G0_KNOT_R2_OFFSET :
+{0x7028,0x00,0x01},    // G0_KNOT_R4_OFFSET :
+{0x7029,0x00,0x01},    // G0_KNOT_R6_OFFSET :
+{0x702A,0x00,0x01},    // G0_KNOT_R8_OFFSET :
+{0x702B,0x00,0x01},    // G0_KNOT_R10_OFFSET :
+{0x702C,0x00,0x01},    // G0_KNOT_R12_OFFSET :
+{0x702D,0x00,0x01},    // G0_KNOT_R14_OFFSET :
+{0x702E,0x00,0x01},    // G0_KNOT_R16_OFFSET :
+{0x702F,0x00,0x01},    // G0_KNOT_R18_OFFSET :
+{0x7030,0x00,0x01},    // G0_KNOT_B0_OFFSET :
+{0x7031,0x00,0x01},    // G0_KNOT_B2_OFFSET :
+{0x7032,0x00,0x01},    // G0_KNOT_B4_OFFSET :
+{0x7033,0x00,0x01},    // G0_KNOT_B6_OFFSET :
+{0x7034,0x00,0x01},    // G0_KNOT_B8_OFFSET :
+{0x7035,0x00,0x01},    // G0_KNOT_B10_OFFSET :
+{0x7036,0x00,0x01},    // G0_KNOT_B12_OFFSET :
+{0x7037,0x00,0x01},    // G0_KNOT_B14_OFFSET :
+{0x7038,0x00,0x01},    // G0_KNOT_B16_OFFSET :
+{0x7039,0x00,0x01},    // G0_KNOT_B18_OFFSET :
+{0x703A,0x0611,0x02},	 // G0_LOWGM_ON_R :
+{0x703C,0x1E0A,0x02},	 // G0_0CLIP_R :
+{0x703E,0x0611,0x02},	 // G0_LOWGM_ON_G :
+{0x7040,0x1E0A,0x02},	 // G0_0CLIP_G :
+{0x7042,0x0611,0x02},	 // G0_LOWGM_ON_B :
+{0x7044,0x1E0A,0x02},	 // G0_0CLIP_B :
+{0x7046,0x9C,0x01},    // G0_KNOT_GAINCTRL_TH_L :
+{0x7047,0xA1,0x01},    // G0_KNOT_GAINCTRL_TH_H :
+{0x7048,0x0000,0x02},	 // G0_KNOT_L_G0 :
+{0x704A,0x0007,0x02},	 // G0_KNOT_L_G1 :
+{0x704C,0x0016,0x02},	 // G0_KNOT_L_G2 :
+{0x704E,0x002A,0x02},	 // G0_KNOT_L_G3 :
+{0x7050,0x0039,0x02},	 // G0_KNOT_L_G4 :
+{0x7052,0x004A,0x02},	 // G0_KNOT_L_G5 :
+{0x7054,0x0051,0x02},	 // G0_KNOT_L_G6 :
+{0x7056,0x005D,0x02},	 // G0_KNOT_L_G7 :
+{0x7058,0x0065,0x02},	 // G0_KNOT_L_G8 :
+{0x705A,0x006C,0x02},	 // G0_KNOT_L_G9 :
+{0x705C,0x004E,0x02},	 // G0_KNOT_L_G10 :
+{0x705E,0x0083,0x02},	 // G0_KNOT_L_G11 :
+{0x7060,0x00AA,0x02},	 // G0_KNOT_L_G12 :
+{0x7062,0x00C8,0x02},	 // G0_KNOT_L_G13 :
+{0x7064,0x00E1,0x02},	 // G0_KNOT_L_G14 :
+{0x7066,0x00F5,0x02},	 // G0_KNOT_L_G15 :
+{0x7068,0x0100,0x02},	 // G0_KNOT_L_G16 :
+{0x706A,0x0106,0x02},	 // G0_KNOT_L_G17 :
+{0x706C,0x010C,0x02},	 // G0_KNOT_L_G18 :
+{0x6400,0xAA,0x01},    // INFRM_LEFT00 :
+{0x6401,0xAA,0x01},    // INFRM_LEFT01 :
+{0x6402,0xAA,0x01},    // INFRM_LEFT02 :
+{0x6403,0xAA,0x01},    // INFRM_LEFT03 :
+{0x6404,0xAA,0x01},    // INFRM_LEFT04 :
+{0x6405,0xAA,0x01},    // INFRM_LEFT05 :
+{0x6406,0xAA,0x01},    // INFRM_LEFT06 :
+{0x6407,0xAA,0x01},    // INFRM_LEFT07 :
+{0x6408,0xAA,0x01},    // INFRM_LEFT08 :
+{0x6409,0xAE,0x01},    // INFRM_LEFT09 :
+{0x640A,0xA0,0x01},    // INFRM_LEFT10 :
+{0x640B,0x8C,0x01},    // INFRM_LEFT11 :
+{0x640C,0x72,0x01},    // INFRM_LEFT12 :
+{0x640D,0x64,0x01},    // INFRM_LEFT13 :
+{0x640E,0x5A,0x01},    // INFRM_LEFT14 :
+{0x640F,0x52,0x01},    // INFRM_LEFT15 :
+{0x6410,0x48,0x01},    // INFRM_LEFT16 :
+{0x6411,0x43,0x01},    // INFRM_LEFT17 :
+{0x6412,0x3D,0x01},    // INFRM_LEFT18 :
+{0x6413,0x37,0x01},    // INFRM_LEFT19 :
+{0x6414,0x33,0x01},    // INFRM_LEFT20 :
+{0x6415,0x30,0x01},    // INFRM_LEFT21 :
+{0x6416,0x2E,0x01},    // INFRM_LEFT22 :
+{0x6417,0x2B,0x01},    // INFRM_LEFT23 :
+{0x6418,0x28,0x01},    // INFRM_LEFT24 :
+{0x6419,0x26,0x01},    // INFRM_LEFT25 :
+{0x641A,0x24,0x01},    // INFRM_LEFT26 :
+{0x641B,0x23,0x01},    // INFRM_LEFT27 :
+{0x641C,0x22,0x01},    // INFRM_LEFT28 :
+{0x641D,0x22,0x01},    // INFRM_LEFT29 :
+{0x641E,0x21,0x01},    // INFRM_LEFT30 :
+{0x641F,0x20,0x01},    // INFRM_LEFT31 :
+{0x6420,0x1D,0x01},    // INFRM_LEFT32 :
+{0x6421,0x1A,0x01},    // INFRM_LEFT33 :
+{0x6422,0x18,0x01},    // INFRM_LEFT34 :
+{0x6423,0x17,0x01},    // INFRM_LEFT35 :
+{0x6424,0x16,0x01},    // INFRM_LEFT36 :
+{0x6425,0x17,0x01},    // INFRM_LEFT37 :
+{0x6426,0xAF,0x01},    // INFRM_RIGHT00 :
+{0x6427,0xAF,0x01},    // INFRM_RIGHT01 :
+{0x6428,0xAF,0x01},    // INFRM_RIGHT02 :
+{0x6429,0xAF,0x01},    // INFRM_RIGHT03 :
+{0x642A,0xAF,0x01},    // INFRM_RIGHT04 :
+{0x642B,0xAF,0x01},    // INFRM_RIGHT05 :
+{0x642C,0xAF,0x01},    // INFRM_RIGHT06 :
+{0x642D,0xAF,0x01},    // INFRM_RIGHT07 :
+{0x642E,0xAF,0x01},    // INFRM_RIGHT08 :
+{0x642F,0xAA,0x01},    // INFRM_RIGHT09 :
+{0x6430,0xB2,0x01},    // INFRM_RIGHT10 :
+{0x6431,0xB4,0x01},    // INFRM_RIGHT11 :
+{0x6432,0xB6,0x01},    // INFRM_RIGHT12 :
+{0x6433,0xB4,0x01},    // INFRM_RIGHT13 :
+{0x6434,0x9B,0x01},    // INFRM_RIGHT14 :
+{0x6435,0x8E,0x01},    // INFRM_RIGHT15 :
+{0x6436,0x84,0x01},    // INFRM_RIGHT16 :
+{0x6437,0x7A,0x01},    // INFRM_RIGHT17 :
+{0x6438,0x72,0x01},    // INFRM_RIGHT18 :
+{0x6439,0x6A,0x01},    // INFRM_RIGHT19 :
+{0x643A,0x63,0x01},    // INFRM_RIGHT20 :
+{0x643B,0x5E,0x01},    // INFRM_RIGHT21 :
+{0x643C,0x58,0x01},    // INFRM_RIGHT22 :
+{0x643D,0x53,0x01},    // INFRM_RIGHT23 :
+{0x643E,0x4E,0x01},    // INFRM_RIGHT24 :
+{0x643F,0x4A,0x01},    // INFRM_RIGHT25 :
+{0x6440,0x46,0x01},    // INFRM_RIGHT26 :
+{0x6441,0x42,0x01},    // INFRM_RIGHT27 :
+{0x6442,0x3F,0x01},    // INFRM_RIGHT28 :
+{0x6443,0x3C,0x01},    // INFRM_RIGHT29 :
+{0x6444,0x3A,0x01},    // INFRM_RIGHT30 :
+{0x6445,0x38,0x01},    // INFRM_RIGHT31 :
+{0x6446,0x37,0x01},    // INFRM_RIGHT32 :
+{0x6447,0x35,0x01},    // INFRM_RIGHT33 :
+{0x6448,0x33,0x01},    // INFRM_RIGHT34 :
+{0x6449,0x32,0x01},    // INFRM_RIGHT35 :
+{0x644A,0x32,0x01},    // INFRM_RIGHT36 :
+{0x644B,0x32,0x01},    // INFRM_RIGHT37 :
+{0x644C,0x24FA,0x02},	 // INFRM_TOP :
+{0x644E,0x0940,0x02},	 // INFRM_BOTM :
+{0x6450,0x19,0x01},    // INFRM_FLTOP :
+{0x6451,0x10,0x01},    // INFRM_FLBOTM :
+{0x6452,0x91,0x01},    // INAIM_LEFT00 :
+{0x6453,0x91,0x01},    // INAIM_LEFT01 :
+{0x6454,0x91,0x01},    // INAIM_LEFT02 :
+{0x6455,0x91,0x01},    // INAIM_LEFT03 :
+{0x6456,0x91,0x01},    // INAIM_LEFT04 :
+{0x6457,0x91,0x01},    // INAIM_LEFT05 :
+{0x6458,0x91,0x01},    // INAIM_LEFT06 :
+{0x6459,0x91,0x01},    // INAIM_LEFT07 :
+{0x645A,0x91,0x01},    // INAIM_LEFT08 :
+{0x645B,0x91,0x01},    // INAIM_LEFT09 :
+{0x645C,0x91,0x01},    // INAIM_LEFT10 :
+{0x645D,0x91,0x01},    // INAIM_LEFT11 :
+{0x645E,0x91,0x01},    // INAIM_LEFT12 :
+{0x645F,0x66,0x01},    // INAIM_LEFT13 :
+{0x6460,0x71,0x01},    // INAIM_LEFT14 :
+{0x6461,0x5A,0x01},    // INAIM_LEFT15 :
+{0x6462,0x4E,0x01},    // INAIM_LEFT16 :
+{0x6463,0x47,0x01},    // INAIM_LEFT17 :
+{0x6464,0x42,0x01},    // INAIM_LEFT18 :
+{0x6465,0x3C,0x01},    // INAIM_LEFT19 :
+{0x6466,0x38,0x01},    // INAIM_LEFT20 :
+{0x6467,0x36,0x01},    // INAIM_LEFT21 :
+{0x6468,0x33,0x01},    // INAIM_LEFT22 :
+{0x6469,0x30,0x01},    // INAIM_LEFT23 :
+{0x646A,0x2F,0x01},    // INAIM_LEFT24 :
+{0x646B,0x2B,0x01},    // INAIM_LEFT25 :
+{0x646C,0x29,0x01},    // INAIM_LEFT26 :
+{0x646D,0x27,0x01},    // INAIM_LEFT27 :
+{0x646E,0x26,0x01},    // INAIM_LEFT28 :
+{0x646F,0x28,0x01},    // INAIM_LEFT29 :
+{0x6470,0x2A,0x01},    // INAIM_LEFT30 :
+{0x6471,0x28,0x01},    // INAIM_LEFT31 :
+{0x6472,0x26,0x01},    // INAIM_LEFT32 :
+{0x6473,0x24,0x01},    // INAIM_LEFT33 :
+{0x6474,0x29,0x01},    // INAIM_LEFT34 :
+{0x6475,0x28,0x01},    // INAIM_LEFT35 :
+{0x6476,0x29,0x01},    // INAIM_LEFT36 :
+{0x6477,0x26,0x01},    // INAIM_LEFT37 :
+{0x6478,0xFF,0x01},    // INAIM_RIGHT00 :
+{0x6479,0xFF,0x01},    // INAIM_RIGHT01 :
+{0x647A,0xFF,0x01},    // INAIM_RIGHT02 :
+{0x647B,0xFF,0x01},    // INAIM_RIGHT03 :
+{0x647C,0xFF,0x01},    // INAIM_RIGHT04 :
+{0x647D,0xFF,0x01},    // INAIM_RIGHT05 :
+{0x647E,0xFF,0x01},    // INAIM_RIGHT06 :
+{0x647F,0xFF,0x01},    // INAIM_RIGHT07 :
+{0x6480,0xFF,0x01},    // INAIM_RIGHT08 :
+{0x6481,0xFF,0x01},    // INAIM_RIGHT09 :
+{0x6482,0xD9,0x01},    // INAIM_RIGHT10 :
+{0x6483,0xB7,0x01},    // INAIM_RIGHT11 :
+{0x6484,0x96,0x01},    // INAIM_RIGHT12 :
+{0x6485,0x68,0x01},    // INAIM_RIGHT13 :
+{0x6486,0x72,0x01},    // INAIM_RIGHT14 :
+{0x6487,0x71,0x01},    // INAIM_RIGHT15 :
+{0x6488,0x6E,0x01},    // INAIM_RIGHT16 :
+{0x6489,0x6A,0x01},    // INAIM_RIGHT17 :
+{0x648A,0x65,0x01},    // INAIM_RIGHT18 :
+{0x648B,0x60,0x01},    // INAIM_RIGHT19 :
+{0x648C,0x5B,0x01},    // INAIM_RIGHT20 :
+{0x648D,0x56,0x01},    // INAIM_RIGHT21 :
+{0x648E,0x51,0x01},    // INAIM_RIGHT22 :
+{0x648F,0x4C,0x01},    // INAIM_RIGHT23 :
+{0x6490,0x47,0x01},    // INAIM_RIGHT24 :
+{0x6491,0x44,0x01},    // INAIM_RIGHT25 :
+{0x6492,0x41,0x01},    // INAIM_RIGHT26 :
+{0x6493,0x3E,0x01},    // INAIM_RIGHT27 :
+{0x6494,0x3B,0x01},    // INAIM_RIGHT28 :
+{0x6495,0x39,0x01},    // INAIM_RIGHT29 :
+{0x6496,0x37,0x01},    // INAIM_RIGHT30 :
+{0x6497,0x34,0x01},    // INAIM_RIGHT31 :
+{0x6498,0x33,0x01},    // INAIM_RIGHT32 :
+{0x6499,0x32,0x01},    // INAIM_RIGHT33 :
+{0x649A,0x31,0x01},    // INAIM_RIGHT34 :
+{0x649B,0x30,0x01},    // INAIM_RIGHT35 :
+{0x649C,0x2F,0x01},    // INAIM_RIGHT36 :
+{0x649D,0x2E,0x01},    // INAIM_RIGHT37 :
+{0x649E,0x1E00,0x02},	 // INAIM_TOP :
+{0x64A0,0x0DFF,0x02},	 // INAIM_BOTM :
+{0x64A2,0x18,0x01},    // INAIM_FLTOP :
+{0x64A3,0x09,0x01},    // INAIM_FLBOTM :
+{0x64A4,0xFF,0x01},    // OUTFRM_LEFT00 :
+{0x64A5,0xFF,0x01},    // OUTFRM_LEFT01 :
+{0x64A6,0xFF,0x01},    // OUTFRM_LEFT02 :
+{0x64A7,0xFF,0x01},    // OUTFRM_LEFT03 :
+{0x64A8,0xFF,0x01},    // OUTFRM_LEFT04 :
+{0x64A9,0xFF,0x01},    // OUTFRM_LEFT05 :
+{0x64AA,0xFF,0x01},    // OUTFRM_LEFT06 :
+{0x64AB,0xFF,0x01},    // OUTFRM_LEFT07 :
+{0x64AC,0xFF,0x01},    // OUTFRM_LEFT08 :
+{0x64AD,0xFD,0x01},    // OUTFRM_LEFT09 :
+{0x64AE,0xCB,0x01},    // OUTFRM_LEFT10 :
+{0x64AF,0xA9,0x01},    // OUTFRM_LEFT11 :
+{0x64B0,0x90,0x01},    // OUTFRM_LEFT12 :
+{0x64B1,0x7D,0x01},    // OUTFRM_LEFT13 :
+{0x64B2,0x70,0x01},    // OUTFRM_LEFT14 :
+{0x64B3,0x65,0x01},    // OUTFRM_LEFT15 :
+{0x64B4,0x5C,0x01},    // OUTFRM_LEFT16 :
+{0x64B5,0x55,0x01},    // OUTFRM_LEFT17 :
+{0x64B6,0x4F,0x01},    // OUTFRM_LEFT18 :
+{0x64B7,0x32,0x01},    // OUTFRM_LEFT19 :
+{0x64B8,0x4D,0x01},    // OUTFRM_LEFT20 :
+{0x64B9,0x40,0x01},    // OUTFRM_LEFT21 :
+{0x64BA,0x2D,0x01},    // OUTFRM_LEFT22 :
+{0x64BB,0x2B,0x01},    // OUTFRM_LEFT23 :
+{0x64BC,0x29,0x01},    // OUTFRM_LEFT24 :
+{0x64BD,0x27,0x01},    // OUTFRM_LEFT25 :
+{0x64BE,0x25,0x01},    // OUTFRM_LEFT26 :
+{0x64BF,0x23,0x01},    // OUTFRM_LEFT27 :
+{0x64C0,0x21,0x01},    // OUTFRM_LEFT28 :
+{0x64C1,0x1F,0x01},    // OUTFRM_LEFT29 :
+{0x64C2,0x1D,0x01},    // OUTFRM_LEFT30 :
+{0x64C3,0x1B,0x01},    // OUTFRM_LEFT31 :
+{0x64C4,0x1A,0x01},    // OUTFRM_LEFT32 :
+{0x64C5,0x1A,0x01},    // OUTFRM_LEFT33 :
+{0x64C6,0x1A,0x01},    // OUTFRM_LEFT34 :
+{0x64C7,0x28,0x01},    // OUTFRM_LEFT35 :
+{0x64C8,0x27,0x01},    // OUTFRM_LEFT36 :
+{0x64C9,0x26,0x01},    // OUTFRM_LEFT37 :
+{0x64CA,0xFF,0x01},   // OUTFRM_RIGHT00 :
+{0x64CB,0xFF,0x01},   // OUTFRM_RIGHT01 :
+{0x64CC,0xFF,0x01},   // OUTFRM_RIGHT02 :
+{0x64CD,0xFF,0x01},   // OUTFRM_RIGHT03 :
+{0x64CE,0xFF,0x01},   // OUTFRM_RIGHT04 :
+{0x64CF,0xFF,0x01},   // OUTFRM_RIGHT05 :
+{0x64D0,0xFF,0x01},   // OUTFRM_RIGHT06 :
+{0x64D1,0xFF,0x01},   // OUTFRM_RIGHT07 :
+{0x64D2,0xFF,0x01},   // OUTFRM_RIGHT08 :
+{0x64D3,0xFF,0x01},   // OUTFRM_RIGHT09 :
+{0x64D4,0xD3,0x01},    // OUTFRM_RIGHT10 :
+{0x64D5,0xB1,0x01},    // OUTFRM_RIGHT11 :
+{0x64D6,0x98,0x01},    // OUTFRM_RIGHT12 :
+{0x64D7,0x85,0x01},    // OUTFRM_RIGHT13 :
+{0x64D8,0x78,0x01},    // OUTFRM_RIGHT14 :
+{0x64D9,0x6D,0x01},    // OUTFRM_RIGHT15 :
+{0x64DA,0x64,0x01},    // OUTFRM_RIGHT16 :
+{0x64DB,0x5D,0x01},    // OUTFRM_RIGHT17 :
+{0x64DC,0x57,0x01},    // OUTFRM_RIGHT18 :
+{0x64DD,0x63,0x01},    // OUTFRM_RIGHT19 :
+{0x64DE,0x5E,0x01},    // OUTFRM_RIGHT20 :
+{0x64DF,0x5A,0x01},    // OUTFRM_RIGHT21 :
+{0x64E0,0x56,0x01},    // OUTFRM_RIGHT22 :
+{0x64E1,0x52,0x01},    // OUTFRM_RIGHT23 :
+{0x64E2,0x50,0x01},    // OUTFRM_RIGHT24 :
+{0x64E3,0x4E,0x01},    // OUTFRM_RIGHT25 :
+{0x64E4,0x4C,0x01},    // OUTFRM_RIGHT26 :
+{0x64E5,0x4A,0x01},    // OUTFRM_RIGHT27 :
+{0x64E6,0x48,0x01},    // OUTFRM_RIGHT28 :
+{0x64E7,0x46,0x01},    // OUTFRM_RIGHT29 :
+{0x64E8,0x44,0x01},    // OUTFRM_RIGHT30 :
+{0x64E9,0x43,0x01},    // OUTFRM_RIGHT31 :
+{0x64EA,0x42,0x01},    // OUTFRM_RIGHT32 :
+{0x64EB,0x42,0x01},    // OUTFRM_RIGHT33 :
+{0x64EC,0x42,0x01},    // OUTFRM_RIGHT34 :
+{0x64ED,0x30,0x01},    // OUTFRM_RIGHT35 :
+{0x64EE,0x2F,0x01},    // OUTFRM_RIGHT36 :
+{0x64EF,0x2E,0x01},    // OUTFRM_RIGHT37 :
+{0x64F0,0x2163,0x02},    // OUTFRM_TOP :
+{0x64F2,0x1400,0x02},	// OUTFRM_BOTM :
+{0x64F4,0x19,0x01},    // OUTFRM_FLTOP :
+{0x64F5,0x14,0x01},    // OUTFRM_FLBOTM :
+//AWB
+{0x6232,0xFF,0x01},    // ATW_SFTLMT_OUT_NR
+{0x6234,0xFF,0x01},    // ATW_SFTLMT_OUT
+/////MC3 Setting/////
+{0x7600,0x07,0x01},    // MC3_PXDEF0_SEL :
+{0x7601,0x07,0x01},    // MC3_PYDEF0_SEL :
+{0x7602,0x07,0x01},    // MC3_PXDEF1_SEL :
+{0x7603,0x07,0x01},    // MC3_PYDEF1_SEL :
+{0x7604,0x07,0x01},    // MC3_PXDEF2_SEL :
+{0x7605,0x07,0x01},    // MC3_PYDEF2_SEL :
+{0x7606,0x07,0x01},    // MC3_PXDEF3_SEL :
+{0x7607,0x07,0x01},    // MC3_PYDEF3_SEL :
+{0x7608,0x40,0x01},    // MC3_PXDEF0_A :
+{0x7609,0x40,0x01},    // MC3_PXDEF0_B :
+{0x760A,0x40,0x01},    // MC3_PXDEF0_C :
+{0x760B,0x40,0x01},    // MC3_PYDEF0_A :
+{0x760C,0x40,0x01},    // MC3_PYDEF0_B :
+{0x760D,0x40,0x01},    // MC3_PYDEF0_C :
+{0x760E,0x40,0x01},    // MC3_PXDEF1_A :
+{0x760F,0x40,0x01},    // MC3_PXDEF1_B :
+{0x7610,0x40,0x01},    // MC3_PXDEF1_C :
+{0x7611,0x40,0x01},    // MC3_PYDEF1_A :
+{0x7612,0x40,0x01},    // MC3_PYDEF1_B :
+{0x7613,0x40,0x01},    // MC3_PYDEF1_C :
+{0x7614,0x40,0x01},    // MC3_PXDEF2_A :
+{0x7615,0x40,0x01},    // MC3_PXDEF2_B :
+{0x7616,0x40,0x01},    // MC3_PXDEF2_C :
+{0x7617,0x40,0x01},    // MC3_PYDEF2_A :
+{0x7618,0x40,0x01},    // MC3_PYDEF2_B :
+{0x7619,0x40,0x01},    // MC3_PYDEF2_C :
+{0x761A,0x40,0x01},    // MC3_PXDEF3_A :
+{0x761B,0x40,0x01},    // MC3_PXDEF3_B :
+{0x761C,0x40,0x01},    // MC3_PXDEF3_C :
+{0x761D,0x40,0x01},    // MC3_PYDEF3_A :
+{0x761E,0x40,0x01},    // MC3_PYDEF3_B :
+{0x761F,0x40,0x01},    // MC3_PYDEF3_C :
+{0x7620,0x00,0x01},    // MC3_LUMSL0_IN :
+{0x7621,0x06,0x01},    // MC3_LUMSL1_IN :
+{0x7622,0x03,0x01},    // MC3_LUMSL2_IN :
+{0x7623,0x06,0x01},    // MC3_LUMSL3_IN :
+{0x7624,0x00,0x01},    // MC3_LUMSL0_OUT :
+{0x7625,0x03,0x01},    // MC3_LUMSL1_OUT :
+{0x7626,0x00,0x01},    // MC3_LUMSL2_OUT :
+{0x7627,0x00,0x01},    // MC3_LUMSL3_OUT :
+{0x7628,0x0000,0x02},	 // MC3_L0DEF0_IN :
+{0x762A,0x008C,0x02},	 // MC3_L0DEF1_IN :
+{0x762C,0x0078,0x02},	 // MC3_L0DEF2_IN :
+{0x762E,0x00E6,0x02},	 // MC3_L0DEF3_IN :
+{0x7630,0x0000,0x02},	 // MC3_L0DEF0_OUT :
+{0x7632,0x0082,0x02},	 // MC3_L0DEF1_OUT :
+{0x7634,0x0000,0x02},	 // MC3_L0DEF2_OUT :
+{0x7636,0x0000,0x02},	 // MC3_L0DEF3_OUT :
+{0x7638,0x41,0x01},    // MC3_RDEF0_POS1 :
+{0x7639,0x10,0x01},    // MC3_RDEF1_POS1 :
+{0x763A,0x15,0x01},    // MC3_RDEF2_POS1 :
+{0x763B,0x71,0x01},    // MC3_RDEF3_POS1 :
+{0x763C,0x41,0x01},    // MC3_RDEF0_POS2 :
+{0x763D,0x10,0x01},    // MC3_RDEF1_POS2 :
+{0x763E,0x15,0x01},    // MC3_RDEF2_POS2 :
+{0x763F,0x71,0x01},    // MC3_RDEF3_POS2 :
+{0x7640,0x3C,0x01},    // MC3_RDEF0_POS3 :
+{0x7641,0x10,0x01},    // MC3_RDEF1_POS3 :
+{0x7642,0x15,0x01},    // MC3_RDEF2_POS3 :
+{0x7643,0x71,0x01},    // MC3_RDEF3_POS3 :
+{0x7644,0x46,0x01},    // MC3_RDEF0_POS4 :
+{0x7645,0x32,0x01},    // MC3_RDEF1_POS4 :
+{0x7646,0x15,0x01},    // MC3_RDEF2_POS4 :
+{0x7647,0x71,0x01},    // MC3_RDEF3_POS4 :
+{0x7648,0x46,0x01},    // MC3_RDEF0_POS5 :
+{0x7649,0x32,0x01},    // MC3_RDEF1_POS5 :
+{0x764A,0x15,0x01},    // MC3_RDEF2_POS5 :
+{0x764B,0x71,0x01},    // MC3_RDEF3_POS5 :
+{0x764C,0x46,0x01},    // MC3_RDEF0_POS6 :
+{0x764D,0x10,0x01},    // MC3_RDEF1_POS6 :
+{0x764E,0x15,0x01},    // MC3_RDEF2_POS6 :
+{0x764F,0x71,0x01},    // MC3_RDEF3_POS6 :
+{0x7650,0x46,0x01},    // MC3_RDEF0_POS7 :
+{0x7651,0x10,0x01},    // MC3_RDEF1_POS7 :
+{0x7652,0x15,0x01},    // MC3_RDEF2_POS7 :
+{0x7653,0x71,0x01},    // MC3_RDEF3_POS7 :
+{0x7654,0x2D,0x01},    // MC3_RDEF0_OUT :
+{0x7655,0x10,0x01},    // MC3_RDEF1_OUT :
+{0x7656,0x15,0x01},    // MC3_RDEF2_OUT :
+{0x7657,0x54,0x01},    // MC3_RDEF3_OUT :
+{0x7658,0x46,0x01},    // MC3_RDEF0_R2_POS4 :
+{0x7659,0x32,0x01},    // MC3_RDEF1_R2_POS4 :
+{0x765A,0x15,0x01},    // MC3_RDEF2_R2_POS4 :
+{0x765B,0x71,0x01},    // MC3_RDEF3_R2_POS4 :
+{0x765C,0x46,0x01},    // MC3_RDEF0_R2_POS5 :
+{0x765D,0x32,0x01},    // MC3_RDEF1_R2_POS5 :
+{0x765E,0x15,0x01},    // MC3_RDEF2_R2_POS5 :
+{0x765F,0x71,0x01},    // MC3_RDEF3_R2_POS5 :
+{0x7660,0xFFBA,0x02},	 // MC3_X0DEF0_POS1 :
+{0x7662,0xFFBA,0x02},	 // MC3_Y0DEF0_POS1 :
+{0x7664,0xFFFE,0x02},	 // MC3_X0DEF1_POS1 :
+{0x7666,0x000D,0x02},	 // MC3_Y0DEF1_POS1 :
+{0x7668,0x0002,0x02},	 // MC3_X0DEF2_POS1 :
+{0x766A,0xFFF6,0x02},	 // MC3_Y0DEF2_POS1 :
+{0x766C,0x003B,0x02},	 // MC3_X0DEF3_POS1 :
+{0x766E,0xFFBB,0x02},	 // MC3_Y0DEF3_POS1 :
+{0x7670,0xFFBA,0x02},	 // MC3_X0DEF0_POS2 :
+{0x7672,0xFFBA,0x02},	 // MC3_Y0DEF0_POS2 :
+{0x7674,0xFFFE,0x02},	 // MC3_X0DEF1_POS2 :
+{0x7676,0x000D,0x02},	 // MC3_Y0DEF1_POS2 :
+{0x7678,0x0002,0x02},	 // MC3_X0DEF2_POS2 :
+{0x767A,0xFFF6,0x02},	 // MC3_Y0DEF2_POS2 :
+{0x767C,0x003B,0x02},	 // MC3_X0DEF3_POS2 :
+{0x767E,0xFFBB,0x02},	 // MC3_Y0DEF3_POS2 :
+{0x7680,0xFFCE,0x02},	 // MC3_X0DEF0_POS3 :
+{0x7682,0xFFBA,0x02},	 // MC3_Y0DEF0_POS3 :
+{0x7684,0xFFFE,0x02},	 // MC3_X0DEF1_POS3 :
+{0x7686,0x000D,0x02},	 // MC3_Y0DEF1_POS3 :
+{0x7688,0x0002,0x02},	 // MC3_X0DEF2_POS3 :
+{0x768A,0xFFF6,0x02},	 // MC3_Y0DEF2_POS3 :
+{0x768C,0x003B,0x02},	 // MC3_X0DEF3_POS3 :
+{0x768E,0xFFBB,0x02},	 // MC3_Y0DEF3_POS3 :
+{0x7690,0xFFCE,0x02},	 // MC3_X0DEF0_POS4 :
+{0x7692,0xFFC9,0x02},	 // MC3_Y0DEF0_POS4 :
+{0x7694,0xFFD0,0x02},	 // MC3_X0DEF1_POS4 :
+{0x7696,0x0037,0x02},	 // MC3_Y0DEF1_POS4 :
+{0x7698,0x0002,0x02},	 // MC3_X0DEF2_POS4 :
+{0x769A,0xFFF6,0x02},	 // MC3_Y0DEF2_POS4 :
+{0x769C,0x003B,0x02},	 // MC3_X0DEF3_POS4 :
+{0x769E,0xFFBB,0x02},	 // MC3_Y0DEF3_POS4 :
+{0x76A0,0xFFCE,0x02},	 // MC3_X0DEF0_POS5 :
+{0x76A2,0xFFC9,0x02},	 // MC3_Y0DEF0_POS5 :
+{0x76A4,0xFFD0,0x02},	 // MC3_X0DEF1_POS5 :
+{0x76A6,0x0037,0x02},	 // MC3_Y0DEF1_POS5 :
+{0x76A8,0x0002,0x02},	 // MC3_X0DEF2_POS5 :
+{0x76AA,0xFFF6,0x02},	 // MC3_Y0DEF2_POS5 :
+{0x76AC,0x003B,0x02},	 // MC3_X0DEF3_POS5 :
+{0x76AE,0xFFBB,0x02},	 // MC3_Y0DEF3_POS5 :
+{0x76B0,0xFFCE,0x02},	 // MC3_X0DEF0_POS6 :
+{0x76B2,0xFFC9,0x02},	 // MC3_Y0DEF0_POS6 :
+{0x76B4,0xFFFE,0x02},	 // MC3_X0DEF1_POS6 :
+{0x76B6,0x000D,0x02},	 // MC3_Y0DEF1_POS6 :
+{0x76B8,0x0002,0x02},	 // MC3_X0DEF2_POS6 :
+{0x76BA,0xFFF6,0x02},	 // MC3_Y0DEF2_POS6 :
+{0x76BC,0x003B,0x02},	 // MC3_X0DEF3_POS6 :
+{0x76BE,0xFFBB,0x02},	 // MC3_Y0DEF3_POS6 :
+{0x76C0,0xFFCE,0x02},	 // MC3_X0DEF0_POS7 :
+{0x76C2,0xFFC9,0x02},	 // MC3_Y0DEF0_POS7 :
+{0x76C4,0xFFFE,0x02},	 // MC3_X0DEF1_POS7 :
+{0x76C6,0x000D,0x02},	 // MC3_Y0DEF1_POS7 :
+{0x76C8,0x0002,0x02},	 // MC3_X0DEF2_POS7 :
+{0x76CA,0xFFF6,0x02},	 // MC3_Y0DEF2_POS7 :
+{0x76CC,0x003B,0x02},	 // MC3_X0DEF3_POS7 :
+{0x76CE,0xFFBB,0x02},	 // MC3_Y0DEF3_POS7 :
+{0x76D0,0xFF7E,0x02},	 // MC3_X0DEF0_OUT :
+{0x76D2,0xFFE2,0x02},	 // MC3_Y0DEF0_OUT :
+{0x76D4,0xFFFE,0x02},	 // MC3_X0DEF1_OUT :
+{0x76D6,0x000D,0x02},	 // MC3_Y0DEF1_OUT :
+{0x76D8,0x0002,0x02},	 // MC3_X0DEF2_OUT :
+{0x76DA,0xFFF6,0x02},	 // MC3_Y0DEF2_OUT :
+{0x76DC,0xFFC4,0x02},	 // MC3_X0DEF3_OUT :
+{0x76DE,0xFFEC,0x02},	 // MC3_Y0DEF3_OUT :
+{0x76E0,0xFFCE,0x02},	 // MC3_X0DEF0_R2_POS4 :
+{0x76E2,0xFFC9,0x02},	 // MC3_Y0DEF0_R2_POS4 :
+{0x76E4,0xFFD0,0x02},	 // MC3_X0DEF1_R2_POS4 :
+{0x76E6,0x0037,0x02},	 // MC3_Y0DEF1_R2_POS4 :
+{0x76E8,0x0002,0x02},	 // MC3_X0DEF2_R2_POS4 :
+{0x76EA,0xFFF6,0x02},	 // MC3_Y0DEF2_R2_POS4 :
+{0x76EC,0x003B,0x02},	 // MC3_X0DEF3_R2_POS4 :
+{0x76EE,0xFFBB,0x02},	 // MC3_Y0DEF3_R2_POS4 :
+{0x76F0,0xFFCE,0x02},	 // MC3_X0DEF0_R2_POS5 :
+{0x76F2,0xFFC9,0x02},	 // MC3_Y0DEF0_R2_POS5 :
+{0x76F4,0xFFD0,0x02},	 // MC3_X0DEF1_R2_POS5 :
+{0x76F6,0x0037,0x02},	 // MC3_Y0DEF1_R2_POS5 :
+{0x76F8,0x0002,0x02},	 // MC3_X0DEF2_R2_POS5 :
+{0x76FA,0xFFF6,0x02},	 // MC3_Y0DEF2_R2_POS5 :
+{0x76FC,0x003B,0x02},	 // MC3_X0DEF3_R2_POS5 :
+{0x76FE,0xFFBB,0x02},	 // MC3_Y0DEF3_R2_POS5 :
+{0x7700,0x0019,0x02},	 // MC3_PXDEF0_POS1 :
+{0x7702,0xFF66,0x02},	 // MC3_PYDEF0_POS1 :
+{0x7704,0x0000,0x02},	 // MC3_PXDEF1_POS1 :
+{0x7706,0x0000,0x02},	 // MC3_PYDEF1_POS1 :
+{0x7708,0x0000,0x02},	 // MC3_PXDEF2_POS1 :
+{0x770A,0x0000,0x02},	 // MC3_PYDEF2_POS1 :
+{0x770C,0xFFD7,0x02},	 // MC3_PXDEF3_POS1 :
+{0x770E,0x0068,0x02},	 // MC3_PYDEF3_POS1 :
+{0x7710,0x0000,0x02},	 // MC3_PXDEF0_POS2 :
+{0x7712,0xFF66,0x02},	 // MC3_PYDEF0_POS2 :
+{0x7714,0x0033,0x02},	 // MC3_PXDEF1_POS2 :
+{0x7716,0xFF4C,0x02},	 // MC3_PYDEF1_POS2 :
+{0x7718,0x0000,0x02},	 // MC3_PXDEF2_POS2 :
+{0x771A,0x00B3,0x02},	 // MC3_PYDEF2_POS2 :
+{0x771C,0xFFD7,0x02},	 // MC3_PXDEF3_POS2 :
+{0x771E,0x0068,0x02},	 // MC3_PYDEF3_POS2 :
+{0x7720,0x0000,0x02},	 // MC3_PXDEF0_POS3 :
+{0x7722,0xFF80,0x02},	 // MC3_PYDEF0_POS3 :
+{0x7724,0x0000,0x02},	 // MC3_PXDEF1_POS3 :
+{0x7726,0x0000,0x02},	 // MC3_PYDEF1_POS3 :
+{0x7728,0x0000,0x02},	 // MC3_PXDEF2_POS3 :
+{0x772A,0x0000,0x02},	 // MC3_PYDEF2_POS3 :
+{0x772C,0xFFD7,0x02},	 // MC3_PXDEF3_POS3 :
+{0x772E,0x0068,0x02},	 // MC3_PYDEF3_POS3 :
+{0x7730,0x0000,0x02},	 // MC3_PXDEF0_POS4 :
+{0x7732,0xFFCC,0x02},	 // MC3_PYDEF0_POS4 :
+{0x7734,0x0000,0x02},	 // MC3_PXDEF1_POS4 :
+{0x7736,0x0000,0x02},	 // MC3_PYDEF1_POS4 :
+{0x7738,0x0000,0x02},	 // MC3_PXDEF2_POS4 :
+{0x773A,0x0000,0x02},	 // MC3_PYDEF2_POS4 :
+{0x773C,0xFFD7,0x02},	 // MC3_PXDEF3_POS4 :
+{0x773E,0x0068,0x02},	 // MC3_PYDEF3_POS4 :
+{0x7740,0x0000,0x02},	 // MC3_PXDEF0_POS5 :
+{0x7742,0xFFCC,0x02},	 // MC3_PYDEF0_POS5 :
+{0x7744,0x0000,0x02},	 // MC3_PXDEF1_POS5 :
+{0x7746,0x0000,0x02},	 // MC3_PYDEF1_POS5 :
+{0x7748,0x0000,0x02},	 // MC3_PXDEF2_POS5 :
+{0x774A,0x0000,0x02},	 // MC3_PYDEF2_POS5 :
+{0x774C,0xFFD7,0x02},	 // MC3_PXDEF3_POS5 :
+{0x774E,0x0068,0x02},	 // MC3_PYDEF3_POS5 :
+{0x7750,0xFFB3,0x02},	 // MC3_PXDEF0_POS6 :
+{0x7752,0x0000,0x02},	 // MC3_PYDEF0_POS6 :
+{0x7754,0x0033,0x02},	 // MC3_PXDEF1_POS6 :
+{0x7756,0xFF4C,0x02},	 // MC3_PYDEF1_POS6 :
+{0x7758,0x0000,0x02},	 // MC3_PXDEF2_POS6 :
+{0x775A,0x00B3,0x02},	 // MC3_PYDEF2_POS6 :
+{0x775C,0xFFD7,0x02},	 // MC3_PXDEF3_POS6 :
+{0x775E,0x0068,0x02},	 // MC3_PYDEF3_POS6 :
+{0x7760,0xFFB3,0x02},	 // MC3_PXDEF0_POS7 :
+{0x7762,0x0000,0x02},	 // MC3_PYDEF0_POS7 :
+{0x7764,0x0000,0x02},	 // MC3_PXDEF1_POS7 :
+{0x7766,0x0000,0x02},	 // MC3_PYDEF1_POS7 :
+{0x7768,0x0000,0x02},	 // MC3_PXDEF2_POS7 :
+{0x776A,0x0000,0x02},	 // MC3_PYDEF2_POS7 :
+{0x776C,0xFFD7,0x02},	 // MC3_PXDEF3_POS7 :
+{0x776E,0x0068,0x02},	 // MC3_PYDEF3_POS7 :
+{0x7770,0x0019,0x02},	 // MC3_PXDEF0_OUT :
+{0x7772,0xFFE6,0x02},	 // MC3_PYDEF0_OUT :
+{0x7774,0x0000,0x02},	 // MC3_PXDEF1_OUT :
+{0x7776,0x0000,0x02},	 // MC3_PYDEF1_OUT :
+{0x7778,0x0000,0x02},	 // MC3_PXDEF2_OUT :
+{0x777A,0x0000,0x02},	 // MC3_PYDEF2_OUT :
+{0x777C,0xFFE1,0x02},	 // MC3_PXDEF3_OUT :
+{0x777E,0xFFEB,0x02},	 // MC3_PYDEF3_OUT :
+{0x7780,0x0000,0x02},	 // MC3_PXDEF0_R2_POS4 :
+{0x7782,0xFFCC,0x02},	 // MC3_PYDEF0_R2_POS4 :
+{0x7784,0x0000,0x02},	 // MC3_PXDEF1_R2_POS4 :
+{0x7786,0x0000,0x02},	 // MC3_PYDEF1_R2_POS4 :
+{0x7788,0x0000,0x02},	 // MC3_PXDEF2_R2_POS4 :
+{0x778A,0x0000,0x02},	 // MC3_PYDEF2_R2_POS4 :
+{0x778C,0xFFD7,0x02},	 // MC3_PXDEF3_R2_POS4 :
+{0x778E,0x0068,0x02},	 // MC3_PYDEF3_R2_POS4 :
+{0x7790,0x0000,0x02},	 // MC3_PXDEF0_R2_POS5 :
+{0x7792,0xFFCC,0x02},	 // MC3_PYDEF0_R2_POS5 :
+{0x7794,0x0000,0x02},	 // MC3_PXDEF1_R2_POS5 :
+{0x7796,0x0000,0x02},	 // MC3_PYDEF1_R2_POS5 :
+{0x7798,0x0000,0x02},	 // MC3_PXDEF2_R2_POS5 :
+{0x779A,0x0000,0x02},	 // MC3_PYDEF2_R2_POS5 :
+{0x779C,0xFFD7,0x02},	 // MC3_PXDEF3_R2_POS5 :
+{0x779E,0x0068,0x02},	 // MC3_PYDEF3_R2_POS5 :
+};
+
+static const isx012_regset_t ISX012_Halfrelease_Mode[] =
+{
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+{0x00B3,0x00,0x01},    //AFMODE_HREL :
+{0xFFFF,0x21,0x01},//$wait, 33
+{0x0081,0x01,0x01},    //MODESEL
+};
+
+static const isx012_regset_t ISX012_Barcode_SAF[] =
+{
+{0x00B1,0x01,0x01},    //AF_RESTART_F :
+{0xFFFF,0x21,0x01},    //$wait, 33
+{0x00B2,0x00,0x01},    //AFMODE_MONI :
+};
+
+static const isx012_regset_t ISX012_Lowlux_night_Halfrelease_Mode[] =
+{
+/*++ Disable mipi high clock */
+#if 0
+/* {0x6A9E,0x0AE0,0x02},*/ /* HMAX_1_1*/
+/* {0x00AC,0x02,0x01},*/ /* */
+#endif
+/*-- Disable mipi high clock */
+{0x660E,0x09,0x01},    // AF_HBPF_PEAK_OPD_TH_MIN
+{0x6610,0x09,0x01},    // AF_HBPF_PEAK_OPD_TH_MAX
+{0x664A,0x01,0x01},    // AF_DROPN_ON_PEAK_DETECT :
+{0x6640,0x01,0x01},    // AF_DROPN_ON_PEAK_DETECT_SECOND :
+{0x0289,0x21,0x01},    //AWB_SN8
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+{0x00B3,0x00,0x01},    //AFMODE_HREL :
+{0xFFFF,0x42,0x01},//$wait, 66
+{0x0081,0x01,0x01},    //MODESEL
+};
+
+static const isx012_regset_t ISX012_AF_Cancel_Macro_ON[] =
+{
+{0x00B2,0x02,0x01},    //AFMODE_MONI : Manual AF mode
+{0x0081,0x00,0x01},    //MODESEL : Monitoring mode
+{0x6648,0x02BC,0x02},    //AF_MANUAL_POS : MANUA AF search start position
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+};
+
+static const isx012_regset_t ISX012_AF_Cancel_Macro_OFF[] =
+{
+{0x00B2,0x02,0x01},    //AFMODE_MONI : Manual AF mode
+{0x0081,0x00,0x01},    //MODESEL : Monitoring mode
+{0x6648,0x00C8,0x02},    //AF_MANUAL_POS : MANUA AF search start position
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+};
+
+static const isx012_regset_t ISX012_AF_ReStart[] =
+{
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+};
+
+static const isx012_regset_t ISX012_AF_Macro_OFF[] =
+{
+{0x0081,0x00,0x01},    //MODESEL : Monitoring mode
+{0x6648,0x00C8,0x02},    //AF_MANUAL_POS : MANUA AF search start position
+{0x66DC,0x02BC,0x02},    //AF_JUDGE_MONO_POS_S
+{0x665A,0x00C8,0x02},    // AF_LENSPOS_ON_AFNG :
+{0x028E,0x00,0x01},    //AF_SEARCH_DIR : NEAR->FAR
+{0x00B3,0x00,0x01},    //AFMODE_HREL : Manual AF mode
+{0x00B2,0x02,0x01},    //AFMODE_MONI : Manual AF mode
+{0xFFFF,0x21,0x01},//$wait, 33
+};
+
+static const isx012_regset_t ISX012_AF_Macro_ON[] =
+{
+{0x0081,0x00,0x01},    //MODESEL : Monitoring mode
+{0x6648,0x02BC,0x02},    //AF_MANUAL_POS : MANUA AF search start position
+{0x66DC,0x00C8,0x02},    //AF_JUDGE_MONO_POS_S
+{0x665A,0x02BC,0x02},    // AF_LENSPOS_ON_AFNG :
+{0x028E,0x01,0x01},    //AF_SEARCH_DIR : NEAR->FAR
+{0x00B3,0x00,0x01},    //AFMODE_HREL : Manual AF mode
+{0x00B2,0x02,0x01},    //AFMODE_MONI : Manual AF mode
+{0xFFFF,0x21,0x01},//$wait, 33
+};
+
+static const isx012_regset_t ISX012_AF_SAF[] =
+{
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+{0x00B3,0x00,0x01},    //AFMODE_HREL :
+{0xFFFF,0x21,0x01},//$wait, 33
+{0x0081,0x01,0x01},    //MODESEL
+};
+
+static const isx012_regset_t ISX012_AF_SAF_OFF[] =
+{
+{0x00B2,0x03,0x01},    //AFMODE_MONI : AF OFF
+{0x00B3,0x03,0x01},    //AFMODE_HREL : AF OFF
+{0xFFFF,0x21,0x01},    //$wait,33
+};
+
+static const isx012_regset_t ISX012_AF_TouchSAF_OFF[] =
+{
+{0x00B2,0x03,0x01},    //AFMODE_MONI : AF OFF
+{0x00B3,0x03,0x01},    //AFMODE_HREL : AF OFF
+{0xFFFF,0x21,0x01},    //$wait,33
+{0x0081,0x00,0x01},    //MODESEL
+};
+
+static const isx012_regset_t ISX012_Camcorder_SAF_Start[] =
+{
+{0x00B1,0x01,0x01}, /* AF_RESTART_F */
+{0xFFFF,0x21,0x01}, /* $wait, 33 */
+{0x00B2,0x00,0x01}, /* AFMODE_MONI */
+};
+
+static const isx012_regset_t ISX012_Camcorder_CAF_Start[] =
+{
+{0x00B2,0x01,0x01}, /* AFMODE_MONI */
+};
+
+static const isx012_regset_t ISX012_AF_Window_Reset[] =
+{
+//AF opd window setting
+{0x6A30,0x044E,0x02},    // AF_OPD0_HDELAY :
+{0x6A32,0x02E5,0x02},    // AF_OPD0_VDELAY :
+{0x6A34,0x01D8,0x02},    // AF_OPD0_HVALID :
+{0x6A36,0x01D8,0x02},    // AF_OPD0_VVALID :
+{0x6A38,0x0412,0x02},    // AF_OPD1_HDELAY :
+{0x6A3A,0x02A9,0x02},    // AF_OPD1_VDELAY :
+{0x6A3C,0x0251,0x02},    // AF_OPD1_HVALID :
+{0x6A3E,0x0251,0x02},    // AF_OPD1_VVALID :
+{0x6A40,0x04B4,0x02},    // AF_OPD2_HDELAY :
+{0x6A42,0x0114,0x02},    // AF_OPD2_VDELAY :
+{0x6A44,0x0118,0x02},    // AF_OPD2_HVALID :
+{0x6A46,0x0118,0x02},    // AF_OPD2_VVALID :
+{0x6A48,0x0469,0x02},    // AF_OPD3_HDELAY :
+{0x6A4A,0x00C9,0x02},    // AF_OPD3_VDELAY :
+{0x6A4C,0x01AE,0x02},    // AF_OPD3_HVALID :
+{0x6A4E,0x01AE,0x02},    // AF_OPD3_VVALID :
+{0x6A50,0x04C6,0x02},    // AF_OPD4_HDELAY :
+{0x6A52,0x035D,0x02},    // AF_OPD4_VDELAY :
+{0x6A54,0x00E6,0x02},    // AF_OPD4_HVALID :
+{0x6A56,0x00E6,0x02},    // AF_OPD4_VVALID :
+{0x6A58,0x048A,0x02},    // AF_OPD5_HDELAY :
+{0x6A5A,0x0321,0x02},    // AF_OPD5_VDELAY :
+{0x6A5C,0x015F,0x02},    // AF_OPD5_HVALID :
+{0x6A5E,0x015F,0x02},    // AF_OPD5_VVALID :
+{0x6A60,0x04B4,0x02},    // AF_OPD6_HDELAY :
+{0x6A62,0x0579,0x02},    // AF_OPD6_VDELAY :
+{0x6A64,0x0118,0x02},    // AF_OPD6_HVALID :
+{0x6A66,0x0118,0x02},    // AF_OPD6_VVALID :
+{0x6A68,0x0469,0x02},    // AF_OPD7_HDELAY :
+{0x6A6A,0x052C,0x02},    // AF_OPD7_VDELAY :
+{0x6A6C,0x01AE,0x02},    // AF_OPD7_HVALID :
+{0x6A6E,0x01AE,0x02},    // AF_OPD7_VVALID :
+{0x6A70,0x04C6,0x02},    // AF_OPD8_HDELAY :
+{0x6A72,0x0493,0x02},    // AF_OPD8_VDELAY :
+{0x6A74,0x00E6,0x02},    // AF_OPD8_HVALID :
+{0x6A76,0x00E6,0x02},    // AF_OPD8_VVALID :
+{0x6A78,0x048A,0x02},    // AF_OPD9_HDELAY :
+{0x6A7A,0x0457,0x02},    // AF_OPD9_VDELAY :
+{0x6A7C,0x015F,0x02},    // AF_OPD9_HVALID :
+{0x6A7E,0x015F,0x02},    // AF_OPD9_VVALID :
+{0x6A80,0x05,0x01},    // AF_OPD1A_WEIGHT :
+{0x6A81,0x04,0x01},    // AF_OPD1B_WEIGHT :
+{0x6A82,0x03,0x01},    // AF_OPD2A_WEIGHT :
+{0x6A83,0x02,0x01},    // AF_OPD2B_WEIGHT :
+{0x6A84,0x08,0x01},    // AF_OPD3A_WEIGHT :
+{0x6A85,0x07,0x01},    // AF_OPD3B_WEIGHT :
+{0x6A86,0x03,0x01},    // AF_OPD4A_WEIGHT :
+{0x6A87,0x02,0x01},    // AF_OPD4B_WEIGHT :
+{0x6A88,0x00,0x01},    // AF_OPD5A_WEIGHT :
+{0x6A89,0x00,0x01},    // AF_OPD5B_WEIGHT :
+{0x6646,0x08,0x01},    // AF_OPD_WEIGHT_TH :
+};
+
+/* Added by Samsung TN */
+static const isx012_regset_t ISX012_AF_Window_Set[] =
+{
+{0x6A80,0x00,0x01},
+{0x6A81,0x00,0x01},
+{0x6A82,0x00,0x01},
+{0x6A83,0x00,0x01},
+{0x6A84,0x08,0x01},
+{0x6A85,0x00,0x01},
+{0x6A86,0x00,0x01},
+{0x6A87,0x00,0x01},
+{0x6A88,0x00,0x01},
+{0x6A89,0x00,0x01},
+{0x6646,0x08,0x01},
+};
+
+static const isx012_regset_t isx012_Contrast_Minus_2[] =
+{
+{0x01C7,0x58,0x01},    //UICONTRAST
+};
+
+static const isx012_regset_t isx012_Contrast_Minus_1[] =
+{
+{0x01C7,0x6C,0x01},    //UICONTRAST
+};
+
+static const isx012_regset_t isx012_Contrast_Default[] =
+{
+{0x01C7,0x80,0x01},    //UICONTRAST
+};
+
+static const isx012_regset_t isx012_Contrast_Plus_1[] =
+{
+{0x01C7,0x94,0x01},    //UICONTRAST
+};
+
+static const isx012_regset_t isx012_Contrast_Plus_2[] =
+{
+{0x01C7,0xA8,0x01},    //UICONTRAST
+};
+
+static const isx012_regset_t isx012_Effect_Black_White[] =
+{
+{0x01C5,0x04,0x01},    //FMODE
+};
+
+static const isx012_regset_t ISX012_Effect_Negative[] =
+{
+{0x01C5,0x02,0x01},    //FMODE
+};
+
+static const isx012_regset_t isx012_Effect_Normal[] =
+{
+{0x01C5,0x00,0x01},    //FMODE
+};
+
+static const isx012_regset_t isx012_Effect_Sepia[] =
+{
+{0x01C5,0x03,0x01},    //FMODE
+};
+
+static const isx012_regset_t isx012_Metering_Center[] =
+{
+{0x02AC,0x01,0x01},    //AE_SUB_SN1
+{0x02B6,0x01,0x01},    //AE_SUB_SN11
+};
+
+static const isx012_regset_t isx012_Metering_Matrix[] =
+{
+{0x02AC,0x00,0x01},    //AE_SUB_SN1
+};
+
+static const isx012_regset_t isx012_Metering_Spot[] =
+{
+{0x02AC,0x02,0x01},    //AE_SUB_SN1
+{0x02B6,0x02,0x01},    //AE_SUB_SN11
+};
+
+static const isx012_regset_t ISX012_ExpSetting_Default[] =
+{
+{0x0180,0x00,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_M1Step[] =
+{
+{0x0180,0xFF,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_M2Step[] =
+{
+{0x0180,0xFE,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_M3Step[] =
+{
+{0x0180,0xFD,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_M4Step[] =
+{
+{0x0180,0xFC,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_P1Step[] =
+{
+{0x0180,0x01,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_P2Step[] =
+{
+{0x0180,0x02,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_P3Step[] =
+{
+{0x0180,0x03,0x01},    //EVSEL
+};
+
+static const isx012_regset_t ISX012_ExpSetting_P4Step[] =
+{
+{0x0180,0x04,0x01},    //EVSEL
+};
+
+static const isx012_regset_t isx012_ISO_50[] =
+{
+{0x02A8,0x04,0x01},    //ISO_TYPE1
+{0x5E8A,0x00,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x00,0x01},    // EVREF_GAIN_B :
+{0x0362,0x57,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x57,0x01},    // PICT3_GAMMA_CAP0 :
+};
+
+static const isx012_regset_t isx012_ISO_100[] =
+{
+{0x02A8,0x07,0x01},    //ISO_TYPE1
+{0x5E8A,0x00,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x00,0x01},    // EVREF_GAIN_B :
+{0x0362,0x57,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x57,0x01},    // PICT3_GAMMA_CAP0 :
+};
+
+static const isx012_regset_t isx012_ISO_200[] =
+{
+{0x02A8,0x0A,0x01},    //ISO_TYPE1
+{0x5E8A,0x00,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x00,0x01},    // EVREF_GAIN_B :
+{0x0362,0x57,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x57,0x01},    // PICT3_GAMMA_CAP0 :
+};
+
+static const isx012_regset_t isx012_ISO_400[] =
+{
+{0x02A8,0x0D,0x01},    //ISO_TYPE1
+{0x5E8A,0x00,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x00,0x01},    // EVREF_GAIN_B :
+{0x0362,0x57,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x57,0x01},    // PICT3_GAMMA_CAP0 :
+};
+
+#if 0
+static const isx012_regset_t ISX012_ISO_800[] =
+{
+{0x02A8,0x10,0x01},    //ISO_TYPE1
+{0x5E8A,0x00,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x00,0x01},    // EVREF_GAIN_B :
+{0x0362,0x57,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x57,0x01},    // PICT3_GAMMA_CAP0 :
+};
+#endif
+
+static const isx012_regset_t isx012_ISO_Auto[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1
+{0x5E8A,0x02,0x01},    // EVREF_GAIN_A :
+{0x5E8B,0x02,0x01},    // EVREF_GAIN_B :
+{0x0362,0x55,0x01},    // PICT3_GAMMA_MONI0 :
+{0x0365,0x55,0x01},    // PICT3_GAMMA_CAP0 :
+};
+
+static const isx012_regset_t ISX012_Capture_SizeSetting[] =
+{
+{0x0092,0x0A20,0x02},    //HSIZE_CAP : 2592
+{0x0098,0x0798,0x02},    //VSIZE_CAP : 1944
+};
+
+static const isx012_regset_t ISX012_Capture_Mode[] =
+{
+{0x008A,0x00,0x01},    //OUTFMT_CAP
+{0x0084,0x00,0x01},    //SENSMODE_CAP
+{0x0087,0x03,0x01},    //FPSTYPE_CAP
+{0x0012,0xFF,0x01},    //INTCLR0
+{0x0081,0x02,0x01},    //MODESEL
+{0x0082,0x01,0x01},    //MONI_REFRESH
+{0xFFFF,0x42,0x01},    //$wait,66
+};
+
+static const isx012_regset_t ISX012_Lowlux_Night_Capture_Mode[] =
+{
+{0x03A0,0xA0,0x01},    //UISATURATION_TYPE3 :
+{0x039D,0xF6,0x01},    //UIHUE_TYPE3 :
+{0x982A,0xFFD8,0x02},    // CS_CBLLEV_A :
+{0x9830,0xFFD8,0x02},    // CS_CRLLEV_A :
+{0x9805,0x08,0x01},    // CS_SLP_C_A :
+{0x008A,0x00,0x01},    //OUTFMT_CAP
+{0x0084,0x00,0x01},    //SENSMODE_CAP
+{0x0087,0x03,0x01},    //FPSTYPE_CAP
+{0x0012,0xFF,0x01},    //INTCLR0
+{0x0081,0x02,0x01},    //MODESEL
+{0x0082,0x01,0x01},    //MONI_REFRESH
+{0xFFFF,0x03E8,0x01},    //$wait,1s
+};
+
+static const isx012_regset_t isx012_Saturation_Default[] =
+{
+{0x039E,0x80,0x01},    //UISATURATION_TYPE1
+};
+
+static const isx012_regset_t isx012_Saturation_Minus_1[] =
+{
+{0x039E,0x62,0x01},    //UISATURATION_TYPE1
+};
+
+static const isx012_regset_t isx012_Saturation_Minus_2[] =
+{
+{0x039E,0x44,0x01},    //UISATURATION_TYPE1
+};
+
+static const isx012_regset_t isx012_Saturation_Plus_1[] =
+{
+{0x039E,0x9E,0x01},    //UISATURATION_TYPE1
+};
+
+static const isx012_regset_t isx012_Saturation_Plus_2[] =
+{
+{0x039E,0xBC,0x01},    //UISATURATION_TYPE1
+};
+
+static const isx012_regset_t isx012_Scene_Default[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x00,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Landscape[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x039F,0x9E,0x01},    //UISATURATION_TYPE2 :
+{0x03A3,0x2C,0x01},    //UISHARPNESS_POS_TYPE3 : +1
+{0x03A6,0x2C,0x01},    //UISHARPNESS_NEG_TYPE3 : +1
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x01,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Sports[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x02,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Party_Indoor[] =
+{
+{0x02A8,0x0A,0x01},    //ISO_TYPE1 : ISO200
+{0x039F,0x9E,0x01},    //UISATURATION_TYPE2 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x04,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x00,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Beach_Snow[] =
+{
+{0x02A8,0x04,0x01},    //ISO_TYPE1 : ISO50
+{0x039F,0x9E,0x01},    //UISATURATION_TYPE2 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x04,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Sunset[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x0287,0x25,0x01},    //AWB_SN6 : daylight
+{0x0394,0x00,0x01},    //PICT1_SN6 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x05,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Duskdawn[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x0287,0x27,0x01},    //AWB_SN6 : CWF
+{0x0394,0x00,0x01},    //PICT1_SN6 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x05,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Candle_Light[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x0287,0x25,0x01},    //AWB_SN6 : daylight
+{0x0394,0x00,0x01},    //PICT1_SN6 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x05,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Fall_Color[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x039F,0xBC,0x01},    //UISATURATION_TYPE2 :
+{0x0287,0x20,0x01},    //AWB_SN6 : AWB
+{0x0394,0x04,0x01},    //PICT1_SN6 :
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x05,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Portrait[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x50,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x00,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Nightshot[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x000C,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x000C,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x00,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x07,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Fireworks[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : AUTO
+{0x5E06,0x04,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x000C,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x000C,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x00,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x08,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Text[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x03A3,0x38,0x01},    //UISHARPNESS_POS_TYPE3 : +2
+{0x03A6,0x38,0x01},    //UISHARPNESS_NEG_TYPE3 : +2
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0xA0,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x00,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Scene_Backlight[] =
+{
+{0x02A8,0x00,0x01},    //ISO_TYPE1 : Auto
+{0x5E06,0x02,0x01},    //SHTCTRLMAG3
+{0x038F,0x00,0x01},    //PICT1_SN1 :
+{0x6742,0x0024,0x02},    // AF_SEARCH_OFFSET_FAR :
+{0x6744,0x0024,0x02},    // AF_SEARCH_OFFSET_NEAR :
+{0x500B,0x01,0x01},    // FAST_SHT_MODE_SEL
+{0x0280,0x00,0x01},    //SCENE_SELECT
+};
+
+static const isx012_regset_t isx012_Sharpness_Default[] =
+{
+{0x00A1,0x20,0x01},    //UISHARPNESS_POS_TYPE1
+{0x00A4,0x20,0x01},    //UISHARPNESS_NEG_TYPE1
+};
+
+static const isx012_regset_t isx012_Sharpness_Minus_1[] =
+{
+{0x00A1,0x14,0x01},    //UISHARPNESS_POS_TYPE1
+{0x00A4,0x14,0x01},    //UISHARPNESS_NEG_TYPE1
+};
+
+static const isx012_regset_t isx012_Sharpness_Minus_2[] =
+{
+{0x00A1,0x08,0x01},    //UISHARPNESS_POS_TYPE1
+{0x00A4,0x08,0x01},    //UISHARPNESS_NEG_TYPE1
+};
+
+static const isx012_regset_t isx012_Sharpness_Plus_1[] =
+{
+{0x00A1,0x2C,0x01},    //UISHARPNESS_POS_TYPE1
+{0x00A4,0x2C,0x01},    //UISHARPNESS_NEG_TYPE1
+};
+
+static const isx012_regset_t isx012_Sharpness_Plus_2[] =
+{
+{0x00A1,0x38,0x01},    //UISHARPNESS_POS_TYPE1
+{0x00A4,0x38,0x01},    //UISHARPNESS_NEG_TYPE1
+};
+
+static const isx012_regset_t isx012_WB_Auto[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_WB_Cloudy[] =
+{
+{0x0282,0x26,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_WB_Sunny[] =
+{
+{0x0282,0x25,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_WB_Fluorescent[] =
+{
+{0x0282,0x27,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_WB_Tungsten[] =
+{
+{0x0282,0x28,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t ISX012_Image_Quality_Standard[] =
+{
+{0x00F6,0x00,0x01},    //JPG_QLTY
+{0x0082,0x01,0x01},    //MONI_REFRESH
+};
+
+static const isx012_regset_t ISX012_Image_Quality_Fine[] =
+{
+{0x00F6,0x01,0x01},    //JPG_QLTY
+{0x0082,0x01,0x01},    //MONI_REFRESH
+};
+
+static const isx012_regset_t ISX012_Image_Quality_Super_Fine[] =
+{
+{0x00F6,0x02,0x01},    //JPG_QLTY
+{0x0082,0x01,0x01},    //MONI_REFRESH
+};
+
+static const isx012_regset_t ISX012_Image_Quality_Table[] =
+{
+{0x00F7,0x52,0x01},    // INIT_QLTY0 : Standard 82
+{0x00F8,0x59,0x01},    // INIT_QLTY1 : Fine 89
+{0x00F9,0x5F,0x01},    // INIT_QLTY2 : SuperFine 95
+};
+
+static const isx012_regset_t ISX012_Sensor_Off_VCM[] =
+{
+{0x00B2,0x02,0x01},    //AFMODE_MONI : Manual AF mode
+{0x0081,0x00,0x01},    //MODESEL : Monitoring mode
+{0x6600,0x0000,0x02},
+{0x6666,0x0000,0x02},
+{0x6648,0x0020,0x02}, /* AF_MANUAL_POS : MANUA AF search start position */
+{0xFFFF,0x01,0x01},    //$wait, 1
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+{0xFFFF,0x96,0x01},    //$wait, 150
+};
+
+static const isx012_regset_t isx012_1280_Preview_E[] =
+{
+{0x0090,0x0500,0x02},	 //HSIZE_MONI : 1280
+{0x0096,0x02D0,0x02},	 //VSIZE_MONI : 720
+};
+
+static const isx012_regset_t isx012_1024_768_Preview[] = {
+{0x0090,0x0400,0x02}, /* HSIZE_MONI : 1024 */
+{0x0096,0x0300,0x02}, /* VSIZE_MONI : 768 */
+};
+
+static const isx012_regset_t isx012_800_Preview[] =
+{
+{0x0090,0x0320,0x02},	 //HSIZE_MONI : 800
+{0x0096,0x01E0,0x02},	 //VSIZE_MONI : 480
+
+};
+
+static const isx012_regset_t isx012_720_Preview[] =
+{
+{0x0090,0x02D0,0x02},	 //HSIZE_MONI : 720
+{0x0096,0x01E0,0x02},	 //VSIZE_MONI : 480
+
+};
+
+static const isx012_regset_t isx012_640_Preview[] =
+{
+{0x0090,0x0280,0x02},	 //HSIZE_MONI : 640
+{0x0096,0x01E0,0x02},	 //VSIZE_MONI : 480
+};
+
+static const isx012_regset_t isx012_320_Preview[] =
+{
+{0x0090,0x0140,0x02},	 //HSIZE_MONI : 320
+{0x0096,0x00F0,0x02},	 //VSIZE_MONI :240
+
+};
+static const isx012_regset_t isx012_176_Preview[] =
+{
+{0x0090,0x00B0,0x02},	 //HSIZE_MONI : 176
+{0x0096,0x0090,0x02},	 //VSIZE_MONI : 144
+};
+
+
+static const isx012_regset_t isx012_5M_Capture[] = {
+{0x0092,0x0A00,0x02}, /* HSIZE_CAP: 2560 */
+{0x0098,0x0780,0x02}, /* VSIZE_CAP: 1920 */
+};
+
+static const isx012_regset_t isx012_4M_WIDE_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_3M_Capture[] = {
+{0x0092,0x0800,0x02}, /* HSIZE_CAP : 2048 */
+{0x0098,0x0600,0x02}, /* VSIZE_CAP : 1536 */
+};
+
+static const isx012_regset_t isx012_2_4M_WIDE_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_1_5M_WIDE_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_1M_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_4K_WIDE_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_VGA_Capture[] = {
+{0x0092,0x0280,0x02}, /* HSIZE_CAP : 640 */
+{0x0098,0x01E0,0x02}, /* VSIZE_CAP : 480 */
+};
+
+static const isx012_regset_t isx012_QVGA_Capture[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_DTP_init[] =
+{
+{0x01BC,0x50,0x01},//Shading Gain off
+{0x5E00,0x07,0x01},//Flicker off
+
+// Pre-WB
+{0x6804,0x1000,0x02}, // NORMR
+{0x6806,0x1000,0x02}, // NORMB
+{0x6808,0x0100,0x02}, // AWBPRER
+{0x680A,0x0100,0x02}, // AWBPREB
+{0x6818,0x00,0x01},    //REFERENCE SENSITIVITY RATIO OF SENSOR (R/G)
+{0x6819,0x00,0x01},    //REFERENCE SENSITIVITY RATIO OF SENSOR (B/G)
+
+{0x036B,0x11,0x01},
+{0x0377,0x11,0x01},
+{0x0383,0x11,0x01},
+
+//
+{0x6C44,0x00,0x01},    // G_CTRL_SEL :
+
+//CNR
+{0x6C4A,0x07,0x01},    // MAIN_CONFIG5 :
+
+//ITP NR
+{0x5005,0xBB,0x01},    // DM_SW1 :
+{0x5006,0x03,0x01},    // DM_SW2 :
+{0x0362,0x00,0x01},
+
+{0x6C0B,0x04,0x01},    // PICT_FLAG :
+{0x9800,0x80,0x01},    // LMT_WEIGHT_A :
+{0x9801,0x80,0x01},    // LMT_WEIGHT_B :
+
+{0x6C46,0x00,0x01},    // MAIN_CONFIG1 :
+{0x6C47,0x00,0x01},    // MAIN_CONFIG2 :
+{0x6C48,0x00,0x01},    // MAIN_CONFIG3 :
+{0x6C49,0x00,0x01},    // MAIN_CONFIG4 :
+{0x6C4A,0x00,0x01},    // MAIN_CONFIG5 :
+
+
+{0x5001,0x04,0x01},    // MUTECNT :
+{0x5002,0x00,0x01},    // WDT_EN :
+{0x5003,0x07,0x01},    // Z1_SEL1 :
+{0x5004,0x00,0x01},    // Z1_SEL2 :
+{0x5005,0x00,0x01},    // DM_SW1 :
+{0x5006,0x00,0x01},    // DM_SW2 :
+{0x5007,0x00,0x01},    // CLMP_CTRL :
+{0x5009,0x00,0x01},    // CPUSLEEP_EN :
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN :
+{0x500B,0x00,0x01},    // FAST_SHT_MODE_SEL :
+{0x500C,0x00FA,0x02},    // FAST_SHT_LIMIT_COUNT :
+{0x500E,0x06D0,0x02},    // SYSINT3_VDLY_1_1 :
+{0x5010,0x02F8,0x02},    // SYSINT3_VDLY_1_2 :
+{0x5012,0x0118,0x02},    // SYSINT3_VDLY_1_4 :
+{0x5014,0x0028,0x02},    // SYSINT3_VDLY_1_8 :
+{0x5016,0x0370,0x02},    // SYSINT3_VDLY_1_1_HD :
+{0x5018,0x0208,0x02},    // SYSINT3_VDLY_1_2_HD :
+{0x501A,0x00,0x01},    // SENS_REVERSE_CTRL :
+{0x501B,0x19,0x01},    // EEP_ADDRESS :
+{0x501C,0x5180,0x02},    // SRCCK :
+{0x501E,0x0001,0x02},
+
+{0x6E86,0x0000,0x02},    // IBYHUE1_POS1 :
+{0x6E88,0xFFF5,0x02},    // IRYHUE1_POS1 :
+{0x6E8A,0xFFF8,0x02},    // IBYHUE2_POS1 :
+{0x6E8C,0xFFF5,0x02},    // IRYHUE2_POS1 :
+{0x6E8E,0xFFF8,0x02},    // IBYHUE3_POS1 :
+{0x6E90,0xFFEE,0x02},    // IRYHUE3_POS1 :
+{0x6E92,0x0000,0x02},    // IBYHUE4_POS1 :
+{0x6E94,0xFFEC,0x02},    // IRYHUE4_POS1 :
+{0x6F26,0x4E,0x01},    // IRYGAIN1_POS1 :
+{0x6F27,0x50,0x01},    // IBYGAIN1_POS1 :
+{0x6F28,0x4E,0x01},    // IRYGAIN2_POS1 :
+{0x6F29,0x5A,0x01},    // IBYGAIN2_POS1 :
+{0x6F2A,0x50,0x01},    // IRYGAIN3_POS1 :
+{0x6F2B,0x5A,0x01},    // IBYGAIN3_POS1 :
+{0x6F2C,0x50,0x01},    // IRYGAIN4_POS1 :
+{0x6F2D,0x50,0x01},    // IBYGAIN4_POS1 :
+
+//ae
+{0x5E12,0x0000,0x02},
+{0x5E14,0x0000,0x02},
+{0x0294,0x03,0x01},
+
+//AWB
+{0x625F,0x35,0x01},//CAT_AWB_1
+{0x0282,0x05,0x01},//AWB_SN1
+//S, 5000, 3F, 8,    // CPUEXT :
+
+
+{0x5021,0x00,0x01},    // PG_GAIN_SEL :
+{0x5022,0x01,0x01},    // PG_WIDTH_SEL :
+{0x5023,0x04,0x01},    // PG_MODE_SEL :
+{0x5024,0x0000,0x02},    // PG_LEVEL_SEL :
+{0x5026,0x00,0x01},    // PG_DATEN_OFF_SEL :
+{0x5020,0x01,0x01},    // PGSEL :
+
+};
+
+static const isx012_regset_t isx012_DTP_stop[] =
+{
+{0x01BC,0x57,0x01},    // Shading Gain off
+{0x5E00,0x00,0x01},    // Flicker off
+{0x6804,0x11F0,0x02},    // NORMR
+{0x6806,0x106F,0x02},    // NORMB
+{0x6808,0x014C,0x02},    // AWBPRER
+{0x680A,0x021E,0x02},    // AWBPREB
+{0x6818,0x00,0x01},    // REFERENCE SENSITIVITY RATIO OF SENSOR (R/G)
+{0x6819,0x00,0x01},    // REFERENCE SENSITIVITY RATIO OF SENSOR (B/G)
+{0x036B,0x80,0x01},    //
+{0x0377,0x80,0x01},    //
+{0x0383,0x80,0x01},    //
+{0x6C44,0x13,0x01},    // G_CTRL_SEL :
+{0x6C4A,0x07,0x01},    // MAIN_CONFIG5 :
+{0x5005,0xBB,0x01},    // DM_SW1 :
+{0x5006,0x03,0x01},    // DM_SW2 :
+{0x0362,0x55,0x01},    //
+{0x6C0B,0x00,0x01},    // PICT_FLAG :
+{0x9800,0x40,0x01},    // LMT_WEIGHT_A :
+{0x9801,0x80,0x01},    // LMT_WEIGHT_B :
+{0x6C46,0x1C,0x01},    // MAIN_CONFIG1 :
+{0x6C47,0x0F,0x01},    // MAIN_CONFIG2 :
+{0x6C48,0x03,0x01},    // MAIN_CONFIG3 :
+{0x6C49,0xF5,0x01},    // MAIN_CONFIG4 :
+{0x6C4A,0x07,0x01},    // MAIN_CONFIG5 :
+{0x5001,0x04,0x01},    // MUTECNT :
+{0x5002,0x01,0x01},    // WDT_EN :
+{0x5003,0x04,0x01},    // Z1_SEL1 :
+{0x5004,0x00,0x01},    // Z1_SEL2 :
+{0x5005,0xBB,0x01},    // DM_SW1 :
+{0x5006,0x03,0x01},    // DM_SW2 :
+{0x5007,0x01,0x01},    // CLMP_CTRL :
+{0x5009,0x00,0x01},    // CPUSLEEP_EN :
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN :
+{0x500B,0x00,0x01},    // FAST_SHT_MODE_SEL :
+{0x500C,0x00FA,0x02},    // FAST_SHT_LIMIT_COUNT :
+{0x500E,0x06D0,0x02},    // SYSINT3_VDLY_1_1 :
+{0x5010,0x02F8,0x02},    // SYSINT3_VDLY_1_2 :
+{0x5012,0x0118,0x02},    // SYSINT3_VDLY_1_4 :
+{0x5014,0x0028,0x02},    // SYSINT3_VDLY_1_8 :
+{0x5016,0x0370,0x02},    // SYSINT3_VDLY_1_1_HD :
+{0x5018,0x0208,0x02},    // SYSINT3_VDLY_1_2_HD :
+{0x501A,0x00,0x01},    // SENS_REVERSE_CTRL :
+{0x501B,0x50,0x01},    // EEP_ADDRESS :
+{0x501C,0x5180,0x02},    // SRCCK :
+{0x501E,0x0001,0x02},
+{0x6E86,0x0000,0x02},    // IBYHUE1_POS1 :
+{0x6E88,0xFFF5,0x02},    // IRYHUE1_POS1 :
+{0x6E8A,0xFFF8,0x02},    // IBYHUE2_POS1 :
+{0x6E8C,0xFFF5,0x02},    // IRYHUE2_POS1 :
+{0x6E8E,0xFFF8,0x02},    // IBYHUE3_POS1 :
+{0x6E90,0xFFEE,0x02},    // IRYHUE3_POS1 :
+{0x6E92,0x0000,0x02},    // IBYHUE4_POS1 :
+{0x6E94,0xFFEC,0x02},    // IRYHUE4_POS1 :
+{0x6F26,0x4E,0x01},    // IRYGAIN1_POS1 :
+{0x6F27,0x50,0x01},    // IBYGAIN1_POS1 :
+{0x6F28,0x4E,0x01},    // IRYGAIN2_POS1 :
+{0x6F29,0x5A,0x01},    // IBYGAIN2_POS1 :
+{0x6F2A,0x50,0x01},    // IRYGAIN3_POS1 :
+{0x6F2B,0x5A,0x01},    // IBYGAIN3_POS1 :
+{0x6F2C,0x50,0x01},    // IRYGAIN4_POS1 :
+{0x6F2D,0x50,0x01},    // IBYGAIN4_POS1 :
+{0x5E12,0x014A,0x02},    //
+{0x5E14,0x000D,0x02},    //
+{0x0294,0x00,0x01},    //
+{0x625F,0x35,0x01},    // CAT_AWB_1
+{0x0282,0x20,0x01},    // AWB_SN1
+{0x5021,0x00,0x01},    // PG_GAIN_SEL :
+{0x5022,0x00,0x01},    // PG_WIDTH_SEL :
+{0x5023,0x00,0x01},    // PG_MODE_SEL :
+{0x5024,0x0000,0x02},    // PG_LEVEL_SEL :
+{0x5026,0x00,0x01},    // PG_DATEN_OFF_SEL :
+{0x5020,0x00,0x01},    // PGSEL :
+
+};
+
+static const isx012_regset_t isx012_Preview_Return[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+
+};
+
+static const isx012_regset_t isx012_Capture_Start[] =
+{
+	{0x008A,0x00,0x01},    //OUTFMT_CAP
+	{0x0084,0x00,0x01},	  //SENSMODE_CAP
+	{0x0087,0x03,0x01},    //FPSTYPE_CAP
+	{0x0012,0x06,0x01},    //INTCLR0
+	{0x0081,0x02,0x01},    //MODESEL
+	{0x0082,0x01,0x01},    //MONI_REFRESH
+};
+#if 0
+static const isx012_regset_t isx012_Preview_Return[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+#endif
+
+static const isx012_regset_t isx012_fps_auto[] =
+{
+{0x0308,0x11,0x01}, /* AELINE_MONI_SN1_2 */
+{0x018E,0x0012,0x02}, /* VADJ_SENS_1_2 */
+};
+
+static const isx012_regset_t isx012_fps_15fix[] =
+{
+{0x0308,0x02,0x01}, /* AELINE_MONI_SN1_2 */
+{0x018E,0x041C,0x02}, /* VADJ_SENS_1_2 */
+};
+
+static const isx012_regset_t isx012_fps_25fix[] =
+{
+{0x0308,0x02,0x01}, /* AELINE_MONI_SN1_2 */
+{0x018E,0x00E1,0x02}, /* VADJ_SENS_1_2 */
+};
+
+static const isx012_regset_t isx012_fps_30fix[] =
+{
+{0x0308,0x02,0x01}, /* AELINE_MONI_SN1_2 */
+{0x018E,0x0012,0x02}, /* VADJ_SENS_1_2 */
+};
+
+static const isx012_regset_t isx012_ae_lock[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_ae_unlock[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_awb_lock[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+static const isx012_regset_t isx012_awb_unlock[] =
+{
+{0x0282,0x20,0x01},    //AWB_SN1
+};
+
+
+static const isx012_regset_t ISX012_Shading_Nocal[] =
+{
+{0x01BC,0x50,0x01},    // CXC OFF SHD OFF
+{0xEB00,0x8282,0x02},	//valid_code
+{0xEB02,0xFE,0x01},
+{0xEB03,0x84,0x01},
+{0xEB04,0x3F,0x01},
+{0xEB05,0x01,0x01},
+{0xEB06,0x50,0x01},
+{0xEB07,0x08,0x01},
+{0xEB08,0x14,0x01},
+{0xEB09,0xFF,0x01},
+{0xEB0A,0x45,0x01},
+{0xEB0B,0x80,0x01},
+{0xEB0C,0x01,0x01},
+{0xEB0D,0x68,0x01},
+{0xEB0E,0x04,0x01},
+{0xEB0F,0x1A,0x01},
+{0xEB10,0x81,0x01},
+{0xEB11,0x86,0x01},
+{0xEB12,0x3F,0x01},
+{0xEB13,0xE1,0x01},
+{0xEB14,0x4F,0x01},
+{0xEB15,0x00,0x01},
+{0xEB16,0x14,0x01},
+{0xEB17,0x02,0x01},
+{0xEB18,0xC5,0x01},
+{0xEB19,0x7F,0x01},
+{0xEB1A,0x11,0x01},
+{0xEB1B,0x60,0x01},
+{0xEB1C,0x00,0x01},
+{0xEB1D,0x1A,0x01},
+{0xEB1E,0x81,0x01},
+{0xEB1F,0x46,0x01},
+{0xEB20,0xA0,0x01},
+{0xEB21,0x01,0x01},
+{0xEB22,0x48,0x01},
+{0xEB23,0x00,0x01},
+{0xEB24,0x12,0x01},
+{0xEB25,0x81,0x01},
+{0xEB26,0x05,0x01},
+{0xEB27,0x20,0x01},
+{0xEB28,0xF1,0x01},
+{0xEB29,0x4F,0x01},
+{0xEB2A,0x00,0x01},
+{0xEB2B,0x14,0x01},
+{0xEB2C,0x82,0x01},
+{0xEB2D,0x85,0x01},
+{0xEB2E,0x80,0x01},
+{0xEB2F,0x21,0x01},
+{0xEB30,0x60,0x01},
+{0xEB31,0x04,0x01},
+{0xEB32,0x12,0x01},
+{0xEB33,0x81,0x01},
+{0xEB34,0x84,0x01},
+{0xEB35,0xE0,0x01},
+{0xEB36,0x00,0x01},
+{0xEB37,0x28,0x01},
+{0xEB38,0x04,0x01},
+{0xEB39,0x0C,0x01},
+{0xEB3A,0x82,0x01},
+{0xEB3B,0x43,0x01},
+{0xEB3C,0x20,0x01},
+{0xEB3D,0x11,0x01},
+{0xEB3E,0x68,0x01},
+{0xEB3F,0x04,0x01},
+{0xEB40,0x1A,0x01},
+{0xEB41,0x82,0x01},
+{0xEB42,0x83,0x01},
+{0xEB43,0xE0,0x01},
+{0xEB44,0x00,0x01},
+{0xEB45,0x20,0x01},
+{0xEB46,0x00,0x01},
+{0xEB47,0x06,0x01},
+{0xEB48,0xFF,0x01},
+{0xEB49,0x41,0x01},
+{0xEB4A,0x80,0x01},
+{0xEB4B,0x10,0x01},
+{0xEB4C,0x30,0x01},
+{0xEB4D,0x08,0x01},
+{0xEB4E,0x14,0x01},
+{0xEB4F,0x02,0x01},
+{0xEB50,0x45,0x01},
+{0xEB51,0xC0,0x01},
+{0xEB52,0x10,0x01},
+{0xEB53,0x30,0x01},
+{0xEB54,0x04,0x01},
+{0xEB55,0x04,0x01},
+{0xEB56,0x01,0x01},
+{0xEB57,0xC0,0x01},
+{0xEB58,0x3F,0x01},
+{0xEB59,0x10,0x01},
+{0xEB5A,0x10,0x01},
+{0xEB5B,0x04,0x01},
+{0xEB5C,0x0A,0x01},
+{0xEB5D,0x80,0x01},
+{0xEB5E,0x03,0x01},
+{0xEB5F,0xE0,0x01},
+{0xEB60,0x10,0x01},
+{0xEB61,0x28,0x01},
+{0xEB62,0x04,0x01},
+{0xEB63,0x0A,0x01},
+{0xEB64,0x81,0x01},
+{0xEB65,0x01,0x01},
+{0xEB66,0x00,0x01},
+{0xEB67,0x10,0x01},
+{0xEB68,0x00,0x01},
+{0xEB69,0x04,0x01},
+{0xEB6A,0x04,0x01},
+{0xEB6B,0x01,0x01},
+{0xEB6C,0x42,0x01},
+{0xEB6D,0xE0,0x01},
+{0xEB6E,0x10,0x01},
+{0xEB6F,0x38,0x01},
+{0xEB70,0xFC,0x01},
+{0xEB71,0x0D,0x01},
+{0xEB72,0x7F,0x01},
+{0xEB73,0x43,0x01},
+{0xEB74,0x60,0x01},
+{0xEB75,0x00,0x01},
+{0xEB76,0x08,0x01},
+{0xEB77,0x08,0x01},
+{0xEB78,0x02,0x01},
+{0xEB79,0x81,0x01},
+{0xEB7A,0x41,0x01},
+{0xEB7B,0x80,0x01},
+{0xEB7C,0x10,0x01},
+{0xEB7D,0x30,0x01},
+{0xEB7E,0x04,0x01},
+{0xEB7F,0x0C,0x01},
+{0xEB80,0x01,0x01},
+{0xEB81,0x43,0x01},
+{0xEB82,0xC0,0x01},
+{0xEB83,0x20,0x01},
+{0xEB84,0x28,0x01},
+{0xEB85,0x08,0x01},
+{0xEB86,0x06,0x01},
+{0xEB87,0x02,0x01},
+{0xEB88,0xC2,0x01},
+{0xEB89,0xA0,0x01},
+{0xEB8A,0x30,0x01},
+{0xEB8B,0x30,0x01},
+{0xEB8C,0x0C,0x01},
+{0xEB8D,0x12,0x01},
+{0xEB8E,0x83,0x01},
+{0xEB8F,0x84,0x01},
+{0xEB90,0x00,0x01},
+{0xEB91,0x21,0x01},
+{0xEB92,0x40,0x01},
+{0xEB93,0x0C,0x01},
+{0xEB94,0x0C,0x01},
+{0xEB95,0x82,0x01},
+{0xEB96,0x03,0x01},
+{0xEB97,0xC1,0x01},
+{0xEB98,0x40,0x01},
+{0xEB99,0x40,0x01},
+{0xEB9A,0x08,0x01},
+{0xEB9B,0x10,0x01},
+{0xEB9C,0x03,0x01},
+{0xEB9D,0xC4,0x01},
+{0xEB9E,0x00,0x01},
+{0xEB9F,0x21,0x01},
+{0xEBA0,0x38,0x01},
+{0xEBA1,0x08,0x01},
+{0xEBA2,0x0E,0x01},
+{0xEBA3,0x82,0x01},
+{0xEBA4,0xC3,0x01},
+{0xEBA5,0x20,0x01},
+{0xEBA6,0x41,0x01},
+{0xEBA7,0x48,0x01},
+{0xEBA8,0x00,0x01},
+{0xEBA9,0x14,0x01},
+{0xEBAA,0x83,0x01},
+{0xEBAB,0x44,0x01},
+{0xEBAC,0x20,0x01},
+{0xEBAD,0x11,0x01},
+{0xEBAE,0x48,0x01},
+{0xEBAF,0x08,0x01},
+{0xEBB0,0x0E,0x01},
+{0xEBB1,0x82,0x01},
+{0xEBB2,0x83,0x01},
+{0xEBB3,0xE0,0x01},
+{0xEBB4,0x30,0x01},
+{0xEBB5,0x48,0x01},
+{0xEBB6,0x10,0x01},
+{0xEBB7,0x12,0x01},
+{0xEBB8,0x00,0x01},
+{0xEBB9,0xC5,0x01},
+{0xEBBA,0x20,0x01},
+{0xEBBB,0x11,0x01},
+{0xEBBC,0x48,0x01},
+{0xEBBD,0x04,0x01},
+{0xEBBE,0x12,0x01},
+{0xEBBF,0x04,0x01},
+{0xEBC0,0x3B,0x01},
+{0xEBC1,0xC1,0x01},
+{0xEBC2,0x1E,0x01},
+{0xEBC3,0xC8,0x01},
+{0xEBC4,0x0F,0x01},
+{0xEBC5,0xF8,0x01},
+{0xEBC6,0x02,0x01},
+{0xEBC7,0xBB,0x01},
+{0xEBC8,0x60,0x01},
+{0xEBC9,0x0F,0x01},
+{0xEBCA,0xB8,0x01},
+{0xEBCB,0x0F,0x01},
+{0xEBCC,0xEA,0x01},
+{0xEBCD,0x83,0x01},
+{0xEBCE,0x3A,0x01},
+{0xEBCF,0xC1,0x01},
+{0xEBD0,0x4E,0x01},
+{0xEBD1,0xB0,0x01},
+{0xEBD2,0x07,0x01},
+{0xEBD3,0xF2,0x01},
+{0xEBD4,0x03,0x01},
+{0xEBD5,0xBE,0x01},
+{0xEBD6,0xC0,0x01},
+{0xEBD7,0x2E,0x01},
+{0xEBD8,0xD8,0x01},
+{0xEBD9,0x03,0x01},
+{0xEBDA,0xEE,0x01},
+{0xEBDB,0x83,0x01},
+{0xEBDC,0xFA,0x01},
+{0xEBDD,0xA0,0x01},
+{0xEBDE,0x2E,0x01},
+{0xEBDF,0xB0,0x01},
+{0xEBE0,0x0B,0x01},
+{0xEBE1,0xEC,0x01},
+{0xEBE2,0x05,0x01},
+{0xEBE3,0xBD,0x01},
+{0xEBE4,0x60,0x01},
+{0xEBE5,0x2F,0x01},
+{0xEBE6,0xD0,0x01},
+{0xEBE7,0x07,0x01},
+{0xEBE8,0xEC,0x01},
+{0xEBE9,0x02,0x01},
+{0xEBEA,0xBC,0x01},
+{0xEBEB,0x40,0x01},
+{0xEBEC,0x2F,0x01},
+{0xEBED,0xD0,0x01},
+{0xEBEE,0x13,0x01},
+{0xEBEF,0xEE,0x01},
+{0xEBF0,0x84,0x01},
+{0xEBF1,0xBB,0x01},
+{0xEBF2,0x00,0x01},
+{0xEBF3,0x1F,0x01},
+{0xEBF4,0xC8,0x01},
+{0xEBF5,0xFF,0x01},
+{0xEBF6,0xEF,0x01},
+{0xEBF7,0x00,0x01},
+{0xEBF8,0x7D,0x01},
+{0xEBF9,0x60,0x01},
+{0xEBFA,0x2F,0x01},
+{0xEBFB,0xD0,0x01},
+{0xEBFC,0x0B,0x01},
+{0xEBFD,0xF4,0x01},
+{0xEBFE,0x85,0x01},
+{0xEBFF,0x7D,0x01},
+{0xEC00,0x61,0x01},
+{0xEC01,0x0F,0x01},
+{0xEC02,0xC0,0x01},
+{0xEC03,0xFF,0x01},
+{0xEC04,0xF7,0x01},
+{0xEC05,0x7F,0x01},
+{0xEC06,0x3D,0x01},
+{0xEC07,0x40,0x01},
+{0xEC08,0xFF,0x01},
+{0xEC09,0xDF,0x01},
+{0xEC0A,0x07,0x01},
+{0xEC0B,0xFA,0x01},
+{0xEC0C,0x81,0x01},
+{0xEC0D,0x3E,0x01},
+{0xEC0E,0x61,0x01},
+{0xEC0F,0x4F,0x01},
+{0xEC10,0xD8,0x01},
+{0xEC11,0x0B,0x01},
+{0xEC12,0xFC,0x01},
+{0xEC13,0xFE,0x01},
+{0xEC14,0x3D,0x01},
+{0xEC15,0xC0,0x01},
+{0xEC16,0xFF,0x01},
+{0xEC17,0xFF,0x01},
+{0xEC18,0x03,0x01},
+{0xEC19,0xFC,0x01},
+{0xEC1A,0x82,0x01},
+{0xEC1B,0xBE,0x01},
+{0xEC1C,0xA0,0x01},
+{0xEC1D,0x6F,0x01},
+{0xEC1E,0xF8,0x01},
+{0xEC1F,0x1B,0x01},
+{0xEC20,0xFE,0x01},
+{0xEC21,0x83,0x01},
+{0xEC22,0xBF,0x01},
+{0xEC23,0xE0,0x01},
+{0xEC24,0x0F,0x01},
+{0xEC25,0x10,0x01},
+{0xEC26,0x00,0x01},
+{0xEC27,0x00,0x01},
+{0xEC28,0x82,0x01},
+{0xEC29,0xC0,0x01},
+{0xEC2A,0x60,0x01},
+{0xEC2B,0x30,0x01},
+{0xEC2C,0x18,0x01},
+{0xEC2D,0x20,0x01},
+{0xEC2E,0x04,0x01},
+{0xEC2F,0x08,0x01},
+{0xEC30,0x81,0x01},
+{0xEC31,0x21,0x01},
+{0xEC32,0x30,0x01},
+{0xEC33,0x08,0x01},
+{0xEC34,0x08,0x01},
+{0xEC35,0x08,0x01},
+{0xEC36,0x82,0x01},
+{0xEC37,0x01,0x01},
+{0xEC38,0x81,0x01},
+{0xEC39,0x50,0x01},
+{0xEC3A,0x08,0x01},
+{0xEC3B,0x14,0x01},
+{0xEC3C,0x02,0x01},
+{0xEC3D,0x09,0x01},
+{0xEC3E,0x41,0x01},
+{0xEC3F,0x42,0x01},
+{0xEC40,0x70,0x01},
+{0xEC41,0x20,0x01},
+{0xEC42,0x0C,0x01},
+{0xEC43,0x06,0x01},
+{0xEC44,0x84,0x01},
+{0xEC45,0x42,0x01},
+{0xEC46,0xE1,0x01},
+{0xEC47,0x40,0x01},
+{0xEC48,0x38,0x01},
+{0xEC49,0x1C,0x01},
+{0xEC4A,0x0C,0x01},
+{0xEC4B,0x07,0x01},
+{0xEC4C,0x03,0x01},
+{0xEC4D,0xA2,0x01},
+{0xEC4E,0x80,0x01},
+{0xEC4F,0x28,0x01},
+{0xEC50,0x18,0x01},
+{0xEC51,0x10,0x01},
+{0xEC52,0x87,0x01},
+{0xEC53,0x43,0x01},
+{0xEC54,0x61,0x01},
+{0xEC55,0x41,0x01},
+{0xEC56,0x48,0x01},
+{0xEC57,0x14,0x01},
+{0xEC58,0x10,0x01},
+{0xEC59,0x07,0x01},
+{0xEC5A,0xC2,0x01},
+{0xEC5B,0x81,0x01},
+{0xEC5C,0x80,0x01},
+{0xEC5D,0x30,0x01},
+{0xEC5E,0x20,0x01},
+{0xEC5F,0x0C,0x01},
+{0xEC60,0x87,0x01},
+{0xEC61,0x83,0x01},
+{0xEC62,0xC1,0x01},
+{0xEC63,0x40,0x01},
+{0xEC64,0x38,0x01},
+{0xEC65,0x14,0x01},
+{0xEC66,0x0A,0x01},
+{0xEC67,0x07,0x01},
+{0xEC68,0xC3,0x01},
+{0xEC69,0xC1,0x01},
+{0xEC6A,0x70,0x01},
+{0xEC6B,0x30,0x01},
+{0xEC6C,0x20,0x01},
+{0xEC6D,0x0C,0x01},
+{0xEC6E,0x08,0x01},
+{0xEC6F,0xC3,0x01},
+{0xEC70,0xE1,0x01},
+{0xEC71,0x60,0x01},
+{0xEC72,0x30,0x01},
+{0xEC73,0x10,0x01},
+{0xEC74,0x0E,0x01},
+{0xEC75,0x85,0x01},
+{0xEC76,0xC2,0x01},
+{0xEC77,0xC1,0x01},
+{0xEC78,0x70,0x01},
+{0xEC79,0x30,0x01},
+{0xEC7A,0x1C,0x01},
+{0xEC7B,0x0C,0x01},
+
+//SHD1(from CO1)
+{0xED02,0xE6,0x01},
+{0xED03,0x61,0x01},
+{0xED04,0x92,0x01},
+{0xED05,0x7C,0x01},
+{0xED06,0xBE,0x01},
+{0xED07,0xB4,0x01},
+{0xED08,0x9E,0x01},
+{0xED09,0x2C,0x01},
+{0xED0A,0x75,0x01},
+{0xED0B,0x47,0x01},
+{0xED0C,0x49,0x01},
+{0xED0D,0xD7,0x01},
+{0xED0E,0x61,0x01},
+{0xED0F,0x12,0x01},
+{0xED10,0x76,0x01},
+{0xED11,0xA8,0x01},
+{0xED12,0x34,0x01},
+{0xED13,0x1E,0x01},
+{0xED14,0x31,0x01},
+{0xED15,0xA1,0x01},
+{0xED16,0xC7,0x01},
+{0xED17,0x4C,0x01},
+{0xED18,0xDE,0x01},
+{0xED19,0xC1,0x01},
+{0xED1A,0xD2,0x01},
+{0xED1B,0x77,0x01},
+{0xED1C,0x76,0x01},
+{0xED1D,0x94,0x01},
+{0xED1E,0x9C,0x01},
+{0xED1F,0x10,0x01},
+{0xED20,0xC9,0x01},
+{0xED21,0xC6,0x01},
+{0xED22,0x40,0x01},
+{0xED23,0xA2,0x01},
+{0xED24,0x99,0x01},
+{0xED25,0x8F,0x01},
+{0xED26,0x66,0x01},
+{0xED27,0xDC,0x01},
+{0xED28,0xF3,0x01},
+{0xED29,0x19,0x01},
+{0xED2A,0xFC,0x01},
+{0xED2B,0xB0,0x01},
+{0xED2C,0xA6,0x01},
+{0xED2D,0x41,0x01},
+{0xED2E,0xC1,0x01},
+{0xED2F,0x49,0x01},
+{0xED30,0x91,0x01},
+{0xED31,0x75,0x01},
+{0xED32,0x8C,0x01},
+{0xED33,0x74,0x01},
+{0xED34,0x1C,0x01},
+{0xED35,0x0B,0x01},
+{0xED36,0x91,0x01},
+{0xED37,0x86,0x01},
+{0xED38,0x3D,0x01},
+{0xED39,0x87,0x01},
+{0xED3A,0x39,0x01},
+{0xED3B,0x4E,0x01},
+{0xED3C,0x5C,0x01},
+{0xED3D,0x50,0x01},
+{0xED3E,0x83,0x01},
+{0xED3F,0x16,0x01},
+{0xED40,0xCF,0x01},
+{0xED41,0xBC,0x01},
+{0xED42,0x45,0x01},
+{0xED43,0x35,0x01},
+{0xED44,0x83,0x01},
+{0xED45,0x41,0x01},
+{0xED46,0xCE,0x01},
+{0xED47,0x67,0x01},
+{0xED48,0xE8,0x01},
+{0xED49,0x33,0x01},
+{0xED4A,0x1C,0x01},
+{0xED4B,0x16,0x01},
+{0xED4C,0xC1,0x01},
+{0xED4D,0x86,0x01},
+{0xED4E,0x3E,0x01},
+{0xED4F,0x83,0x01},
+{0xED50,0xC1,0x01},
+{0xED51,0x0D,0x01},
+{0xED52,0x57,0x01},
+{0xED53,0x02,0x01},
+{0xED54,0x23,0x01},
+{0xED55,0x14,0x01},
+{0xED56,0xAE,0x01},
+{0xED57,0xE4,0x01},
+{0xED58,0x44,0x01},
+{0xED59,0x2A,0x01},
+{0xED5A,0x43,0x01},
+{0xED5B,0xF9,0x01},
+{0xED5C,0xCA,0x01},
+{0xED5D,0x56,0x01},
+{0xED5E,0x0C,0x01},
+{0xED5F,0x03,0x01},
+{0xED60,0x98,0x01},
+{0xED61,0xE2,0x01},
+{0xED62,0xA8,0x01},
+{0xED63,0x26,0x01},
+{0xED64,0x41,0x01},
+{0xED65,0x9E,0x01},
+{0xED66,0xC1,0x01},
+{0xED67,0xCE,0x01},
+{0xED68,0x59,0x01},
+{0xED69,0x1C,0x01},
+{0xED6A,0xB3,0x01},
+{0xED6B,0x93,0x01},
+{0xED6C,0xA7,0x01},
+{0xED6D,0x74,0x01},
+{0xED6E,0x04,0x01},
+{0xED6F,0x25,0x01},
+{0xED70,0x13,0x01},
+{0xED71,0xD9,0x01},
+{0xED72,0xC8,0x01},
+{0xED73,0x47,0x01},
+{0xED74,0x54,0x01},
+{0xED75,0xD2,0x01},
+{0xED76,0x93,0x01},
+{0xED77,0xAA,0x01},
+{0xED78,0x98,0x01},
+{0xED79,0xE5,0x01},
+{0xED7A,0x32,0x01},
+{0xED7B,0x9A,0x01},
+{0xED7C,0x29,0x01},
+{0xED7D,0xCF,0x01},
+{0xED7E,0x64,0x01},
+{0xED7F,0x8E,0x01},
+{0xED80,0x73,0x01},
+{0xED81,0x95,0x01},
+{0xED82,0xBB,0x01},
+{0xED83,0xA4,0x01},
+{0xED84,0xA4,0x01},
+{0xED85,0x26,0x01},
+{0xED86,0x0A,0x01},
+{0xED87,0x59,0x01},
+{0xED88,0x08,0x01},
+{0xED89,0x40,0x01},
+{0xED8A,0x00,0x01},
+{0xED8B,0xC2,0x01},
+{0xED8C,0x10,0x01},
+{0xED8D,0x88,0x01},
+{0xED8E,0xB0,0x01},
+{0xED8F,0x84,0x01},
+{0xED90,0x27,0x01},
+{0xED91,0x59,0x01},
+{0xED92,0xF1,0x01},
+{0xED93,0x0B,0x01},
+{0xED94,0x64,0x01},
+{0xED95,0xA2,0x01},
+{0xED96,0x43,0x01},
+{0xED97,0x99,0x01},
+{0xED98,0xE4,0x01},
+{0xED99,0x68,0x01},
+{0xED9A,0x25,0x01},
+{0xED9B,0x2F,0x01},
+{0xED9C,0x2B,0x01},
+{0xED9D,0xB1,0x01},
+{0xED9E,0xC9,0x01},
+{0xED9F,0x42,0x01},
+{0xEDA0,0x18,0x01},
+{0xEDA1,0x32,0x01},
+{0xEDA2,0x90,0x01},
+{0xEDA3,0x80,0x01},
+{0xEDA4,0x3C,0x01},
+{0xEDA5,0x24,0x01},
+{0xEDA6,0x22,0x01},
+{0xEDA7,0x2F,0x01},
+{0xEDA8,0xF1,0x01},
+{0xEDA9,0x09,0x01},
+{0xEDAA,0x57,0x01},
+{0xEDAB,0x00,0x01},
+{0xEDAC,0x53,0x01},
+{0xEDAD,0x99,0x01},
+{0xEDAE,0xEA,0x01},
+{0xEDAF,0x90,0x01},
+{0xEDB0,0xC6,0x01},
+{0xEDB1,0x3B,0x01},
+{0xEDB2,0x6D,0x01},
+{0xEDB3,0x99,0x01},
+{0xEDB4,0x4C,0x01},
+{0xEDB5,0x50,0x01},
+{0xEDB6,0xA4,0x01},
+{0xEDB7,0x32,0x01},
+{0xEDB8,0x12,0x01},
+{0xEDB9,0x94,0x01},
+{0xEDBA,0x64,0x01},
+{0xEDBB,0xA4,0x01},
+{0xEDBC,0x23,0x01},
+{0xEDBD,0x25,0x01},
+{0xEDBE,0x71,0x01},
+{0xEDBF,0x49,0x01},
+{0xEDC0,0x51,0x01},
+{0xEDC1,0xB2,0x01},
+{0xEDC2,0x02,0x01},
+{0xEDC3,0x17,0x01},
+{0xEDC4,0xCD,0x01},
+{0xEDC5,0x98,0x01},
+{0xEDC6,0x86,0x01},
+{0xEDC7,0x3D,0x01},
+{0xEDC8,0xBC,0x01},
+{0xEDC9,0x01,0x01},
+{0xEDCA,0x50,0x01},
+{0xEDCB,0x63,0x01},
+{0xEDCC,0x80,0x01},
+{0xEDCD,0x63,0x01},
+{0xEDCE,0x16,0x01},
+{0xEDCF,0xC3,0x01},
+{0xEDD0,0x2C,0x01},
+{0xEDD1,0x25,0x01},
+{0xEDD2,0x2C,0x01},
+{0xEDD3,0x43,0x01},
+{0xEDD4,0xB1,0x01},
+{0xEDD5,0x4A,0x01},
+{0xEDD6,0x53,0x01},
+{0xEDD7,0xCC,0x01},
+{0xEDD8,0x82,0x01},
+{0xEDD9,0x96,0x01},
+{0xEDDA,0xC7,0x01},
+{0xEDDB,0x40,0x01},
+{0xEDDC,0xA6,0x01},
+{0xEDDD,0x39,0x01},
+{0xEDDE,0xBE,0x01},
+{0xEDDF,0x91,0x01},
+{0xEDE0,0xD0,0x01},
+{0xEDE1,0x75,0x01},
+{0xEDE2,0x54,0x01},
+{0xEDE3,0x34,0x01},
+{0xEDE4,0x1B,0x01},
+{0xEDE5,0xFC,0x01},
+{0xEDE6,0x4C,0x01},
+{0xEDE7,0x46,0x01},
+{0xEDE8,0x39,0x01},
+{0xEDE9,0x7D,0x01},
+{0xEDEA,0x71,0x01},
+{0xEDEB,0x8D,0x01},
+{0xEDEC,0x5D,0x01},
+{0xEDED,0x46,0x01},
+{0xEDEE,0xE3,0x01},
+{0xEDEF,0x17,0x01},
+{0xEDF0,0xD9,0x01},
+{0xEDF1,0x50,0x01},
+{0xEDF2,0x86,0x01},
+{0xEDF3,0x3A,0x01},
+{0xEDF4,0xB3,0x01},
+{0xEDF5,0x09,0x01},
+{0xEDF6,0x50,0x01},
+{0xEDF7,0x76,0x01},
+{0xEDF8,0x6A,0x01},
+{0xEDF9,0xF4,0x01},
+{0xEDFA,0x1E,0x01},
+{0xEDFB,0x25,0x01},
+{0xEDFC,0x61,0x01},
+{0xEDFD,0x67,0x01},
+{0xEDFE,0x45,0x01},
+{0xEDFF,0xC0,0x01},
+{0xEE00,0x69,0x01},
+{0xEE01,0xD0,0x01},
+{0xEE02,0x6B,0x01},
+{0xEE03,0xF6,0x01},
+{0xEE04,0x93,0x01},
+{0xEE05,0x9A,0x01},
+{0xEE06,0xFA,0x01},
+{0xEE07,0xB8,0x01},
+{0xEE08,0x26,0x01},
+{0xEE09,0x40,0x01},
+{0xEE0A,0xC0,0x01},
+{0xEE0B,0xB9,0x01},
+{0xEE0C,0xD0,0x01},
+{0xEE0D,0x75,0x01},
+{0xEE0E,0x6E,0x01},
+{0xEE0F,0xE4,0x01},
+{0xEE10,0x9E,0x01},
+{0xEE11,0x2D,0x01},
+{0xEE12,0xE1,0x01},
+{0xEE13,0xA7,0x01},
+{0xEE14,0x49,0x01},
+{0xEE15,0xFD,0x01},
+{0xEE16,0xB9,0x01},
+{0xEE17,0x52,0x01},
+{0xEE18,0x7C,0x01},
+{0xEE19,0x98,0x01},
+{0xEE1A,0x64,0x01},
+{0xEE1B,0x1E,0x01},
+{0xEE1C,0x22,0x01},
+{0xEE1D,0x89,0x01},
+{0xEE1E,0xA7,0x01},
+{0xEE1F,0x48,0x01},
+{0xEE20,0xE4,0x01},
+{0xEE21,0x49,0x01},
+{0xEE22,0x12,0x01},
+{0xEE23,0x7D,0x01},
+{0xEE24,0xB4,0x01},
+{0xEE25,0xB4,0x01},
+{0xEE26,0x1F,0x01},
+{0xEE27,0x31,0x01},
+{0xEE28,0xC5,0x01},
+{0xEE29,0x47,0x01},
+{0xEE2A,0x4B,0x01},
+{0xEE2B,0xC2,0x01},
+{0xEE2C,0x19,0x01},
+{0xEE2D,0x0F,0x01},
+{0xEE2E,0x73,0x01},
+{0xEE2F,0xE2,0x01},
+{0xEE30,0x13,0x01},
+{0xEE31,0x1C,0x01},
+{0xEE32,0xF5,0x01},
+{0xEE33,0xE0,0x01},
+{0xEE34,0xC6,0x01},
+{0xEE35,0x3B,0x01},
+{0xEE36,0xB6,0x01},
+{0xEE37,0xB1,0x01},
+{0xEE38,0xCE,0x01},
+{0xEE39,0x6D,0x01},
+{0xEE3A,0xB8,0x01},
+{0xEE3B,0xF3,0x01},
+{0xEE3C,0x9B,0x01},
+{0xEE3D,0xF2,0x01},
+{0xEE3E,0x18,0x01},
+{0xEE3F,0x27,0x01},
+{0xEE40,0x3D,0x01},
+{0xEE41,0xBF,0x01},
+{0xEE42,0xE9,0x01},
+{0xEE43,0xCE,0x01},
+{0xEE44,0x6E,0x01},
+{0xEE45,0xBA,0x01},
+{0xEE46,0x83,0x01},
+{0xEE47,0x9A,0x01},
+{0xEE48,0xE4,0x01},
+{0xEE49,0x50,0x01},
+{0xEE4A,0x66,0x01},
+{0xEE4B,0x36,0x01},
+{0xEE4C,0x8A,0x01},
+{0xEE4D,0x29,0x01},
+{0xEE4E,0x4D,0x01},
+{0xEE4F,0x61,0x01},
+{0xEE50,0x3A,0x01},
+{0xEE51,0xA3,0x01},
+{0xEE52,0x18,0x01},
+{0xEE53,0xD2,0x01},
+{0xEE54,0x50,0x01},
+{0xEE55,0x26,0x01},
+{0xEE56,0x36,0x01},
+{0xEE57,0xA8,0x01},
+{0xEE58,0x21,0x01},
+{0xEE59,0xCE,0x01},
+{0xEE5A,0x6E,0x01},
+{0xEE5B,0xB2,0x01},
+{0xEE5C,0x03,0x01},
+{0xEE5D,0x9A,0x01},
+{0xEE5E,0xE0,0x01},
+{0xEE5F,0x1C,0x01},
+{0xEE60,0x46,0x01},
+{0xEE61,0x34,0x01},
+{0xEE62,0x72,0x01},
+{0xEE63,0x41,0x01},
+{0xEE64,0x8C,0x01},
+{0xEE65,0x58,0x01},
+{0xEE66,0xE8,0x01},
+{0xEE67,0xC2,0x01},
+{0xEE68,0x95,0x01},
+{0xEE69,0xB5,0x01},
+{0xEE6A,0x88,0x01},
+{0xEE6B,0x65,0x01},
+{0xEE6C,0x2E,0x01},
+{0xEE6D,0x72,0x01},
+{0xEE6E,0x39,0x01},
+{0xEE6F,0x8C,0x01},
+{0xEE70,0x62,0x01},
+{0xEE71,0x48,0x01},
+{0xEE72,0x83,0x01},
+{0xEE73,0x1A,0x01},
+{0xEE74,0xE4,0x01},
+{0xEE75,0x28,0x01},
+{0xEE76,0x06,0x01},
+{0xEE77,0x35,0x01},
+{0xEE78,0x6A,0x01},
+{0xEE79,0xF9,0x01},
+{0xEE7A,0x4B,0x01},
+{0xEE7B,0x53,0x01},
+{0xEE7C,0xB8,0x01},
+{0xEE7D,0x92,0x01},
+{0xEE7E,0x13,0x01},
+{0xEE7F,0xA2,0x01},
+{0xEE80,0xCC,0x01},
+{0xEE81,0x64,0x01},
+{0xEE82,0x27,0x01},
+{0xEE83,0x3B,0x01},
+{0xEE84,0x29,0x01},
+{0xEE85,0x0A,0x01},
+{0xEE86,0x54,0x01},
+{0xEE87,0xBC,0x01},
+{0xEE88,0xF2,0x01},
+{0xEE89,0x96,0x01},
+{0xEE8A,0xC1,0x01},
+{0xEE8B,0x40,0x01},
+{0xEE8C,0xA6,0x01},
+{0xEE8D,0x35,0x01},
+{0xEE8E,0x7A,0x01},
+{0xEE8F,0xB1,0x01},
+{0xEE90,0x8C,0x01},
+{0xEE91,0x54,0x01},
+{0xEE92,0xC8,0x01},
+{0xEE93,0xF2,0x01},
+{0xEE94,0x92,0x01},
+{0xEE95,0x9D,0x01},
+{0xEE96,0x64,0x01},
+{0xEE97,0xE4,0x01},
+{0xEE98,0x23,0x01},
+{0xEE99,0x13,0x01},
+{0xEE9A,0xA9,0x01},
+{0xEE9B,0x48,0x01},
+{0xEE9C,0x47,0x01},
+{0xEE9D,0x40,0x01},
+{0xEE9E,0x42,0x01},
+{0xEE9F,0x13,0x01},
+{0xEEA0,0x9F,0x01},
+{0xEEA1,0x58,0x01},
+{0xEEA2,0xE5,0x01},
+{0xEEA3,0x2C,0x01},
+{0xEEA4,0x7F,0x01},
+{0xEEA5,0xD9,0x01},
+{0xEEA6,0x8C,0x01},
+{0xEEA7,0x5B,0x01},
+{0xEEA8,0x12,0x01},
+{0xEEA9,0x43,0x01},
+{0xEEAA,0x14,0x01},
+{0xEEAB,0xAA,0x01},
+{0xEEAC,0x80,0x01},
+{0xEEAD,0x04,0x01},
+{0xEEAE,0x25,0x01},
+{0xEEAF,0x06,0x01},
+{0xEEB0,0x51,0x01},
+{0xEEB1,0x08,0x01},
+{0xEEB2,0x40,0x01},
+{0xEEB3,0x00,0x01},
+{0xEEB4,0xB2,0x01},
+{0xEEB5,0x10,0x01},
+{0xEEB6,0x86,0x01},
+{0xEEB7,0x98,0x01},
+{0xEEB8,0x64,0x01},
+{0xEEB9,0x25,0x01},
+{0xEEBA,0x4A,0x01},
+{0xEEBB,0xB9,0x01},
+{0xEEBC,0x0A,0x01},
+{0xEEBD,0x5D,0x01},
+{0xEEBE,0x1C,0x01},
+{0xEEBF,0x13,0x01},
+{0xEEC0,0x97,0x01},
+{0xEEC1,0xC4,0x01},
+{0xEEC2,0x18,0x01},
+{0xEEC3,0x85,0x01},
+{0xEEC4,0x2A,0x01},
+{0xEEC5,0x21,0x01},
+{0xEEC6,0x41,0x01},
+{0xEEC7,0xC9,0x01},
+{0xEEC8,0x41,0x01},
+{0xEEC9,0x12,0x01},
+{0xEECA,0x02,0x01},
+{0xEECB,0x10,0x01},
+{0xEECC,0x80,0x01},
+{0xEECD,0x2C,0x01},
+{0xEECE,0x64,0x01},
+{0xEECF,0x21,0x01},
+{0xEED0,0x27,0x01},
+{0xEED1,0x61,0x01},
+{0xEED2,0xC9,0x01},
+{0xEED3,0x52,0x01},
+{0xEED4,0xB0,0x01},
+{0xEED5,0x42,0x01},
+{0xEED6,0x17,0x01},
+{0xEED7,0xC8,0x01},
+{0xEED8,0x04,0x01},
+{0xEED9,0xE6,0x01},
+{0xEEDA,0x32,0x01},
+{0xEEDB,0x58,0x01},
+{0xEEDC,0x29,0x01},
+{0xEEDD,0xCB,0x01},
+{0xEEDE,0x4C,0x01},
+{0xEEDF,0x74,0x01},
+{0xEEE0,0x92,0x01},
+{0xEEE1,0x91,0x01},
+{0xEEE2,0x8E,0x01},
+{0xEEE3,0x48,0x01},
+{0xEEE4,0x84,0x01},
+{0xEEE5,0x22,0x01},
+{0xEEE6,0x1D,0x01},
+{0xEEE7,0x01,0x01},
+{0xEEE8,0xC9,0x01},
+{0xEEE9,0x4D,0x01},
+{0xEEEA,0x7E,0x01},
+{0xEEEB,0x82,0x01},
+{0xEEEC,0x15,0x01},
+{0xEEED,0xB5,0x01},
+{0xEEEE,0x04,0x01},
+{0xEEEF,0xE6,0x01},
+{0xEEF0,0x33,0x01},
+{0xEEF1,0x99,0x01},
+{0xEEF2,0x69,0x01},
+{0xEEF3,0x0D,0x01},
+{0xEEF4,0x5D,0x01},
+{0xEEF5,0x06,0x01},
+{0xEEF6,0x33,0x01},
+{0xEEF7,0x15,0x01},
+{0xEEF8,0xAF,0x01},
+{0xEEF9,0xEC,0x01},
+{0xEEFA,0xA4,0x01},
+{0xEEFB,0x28,0x01},
+{0xEEFC,0x35,0x01},
+{0xEEFD,0xE9,0x01},
+{0xEEFE,0x09,0x01},
+{0xEEFF,0x4F,0x01},
+{0xEF00,0x8E,0x01},
+{0xEF01,0x02,0x01},
+{0xEF02,0x95,0x01},
+{0xEF03,0xB1,0x01},
+{0xEF04,0xC4,0x01},
+{0xEF05,0x25,0x01},
+{0xEF06,0x31,0x01},
+{0xEF07,0x94,0x01},
+{0xEF08,0xB1,0x01},
+{0xEF09,0x4D,0x01},
+{0xEF0A,0x6C,0x01},
+{0xEF0B,0x94,0x01},
+{0xEF0C,0x43,0x01},
+{0xEF0D,0x99,0x01},
+{0xEF0E,0xD4,0x01},
+{0xEF0F,0xEC,0x01},
+{0xEF10,0xC5,0x01},
+{0xEF11,0x31,0x01},
+{0xEF12,0x69,0x01},
+{0xEF13,0xC9,0x01},
+{0xEF14,0x0B,0x01},
+{0xEF15,0x58,0x01},
+{0xEF16,0xE6,0x01},
+{0xEF17,0x52,0x01},
+{0xEF18,0x16,0x01},
+{0xEF19,0xBE,0x01},
+{0xEF1A,0xD4,0x01},
+{0xEF1B,0x45,0x01},
+{0xEF1C,0x32,0x01},
+{0xEF1D,0x8E,0x01},
+{0xEF1E,0x79,0x01},
+{0xEF1F,0x4D,0x01},
+{0xEF20,0x6A,0x01},
+{0xEF21,0xA4,0x01},
+{0xEF22,0x83,0x01},
+{0xEF23,0x1C,0x01},
+{0xEF24,0xF2,0x01},
+{0xEF25,0xDC,0x01},
+{0xEF26,0x26,0x01},
+{0xEF27,0x3A,0x01},
+{0xEF28,0xA3,0x01},
+{0xEF29,0xE1,0x01},
+{0xEF2A,0x4D,0x01},
+{0xEF2B,0x65,0x01},
+{0xEF2C,0x5C,0x01},
+{0xEF2D,0xC3,0x01},
+{0xEF2E,0x98,0x01},
+{0xEF2F,0xD4,0x01},
+{0xEF30,0x3C,0x01},
+{0xEF31,0xE6,0x01},
+{0xEF32,0x35,0x01},
+{0xEF33,0x9D,0x01},
+{0xEF34,0x09,0x01},
+{0xEF35,0x8E,0x01},
+{0xEF36,0x6B,0x01},
+{0xEF37,0xAC,0x01},
+{0xEF38,0xE3,0x01},
+{0xEF39,0x9B,0x01},
+{0xEF3A,0xF4,0x01},
+{0xEF3B,0x34,0x01},
+{0xEF3C,0x07,0x01},
+{0xEF3D,0x3E,0x01},
+{0xEF3E,0xDA,0x01},
+{0xEF3F,0xC1,0x01},
+{0xEF40,0x8F,0x01},
+{0xEF41,0x74,0x01},
+{0xEF42,0xEA,0x01},
+{0xEF43,0x13,0x01},
+{0xEF44,0x9C,0x01},
+{0xEF45,0xF4,0x01},
+{0xEF46,0xF0,0x01},
+{0xEF47,0xA6,0x01},
+{0xEF48,0x3C,0x01},
+{0xEF49,0xC0,0x01},
+{0xEF4A,0x49,0x01},
+{0xEF4B,0x0F,0x01},
+{0xEF4C,0x72,0x01},
+{0xEF4D,0xEA,0x01},
+{0xEF4E,0xD3,0x01},
+{0xEF4F,0x9C,0x01},
+{0xEF50,0xFE,0x01},
+{0xEF51,0x04,0x01},
+{0xEF52,0xA7,0x01},
+{0xEF53,0x3D,0x01},
+
+//SHD2 CW+TL84 33:66
+
+{0xED00,0x9191,0x02},//
+{0xEF54,0x21,0x01},
+{0xEF55,0x92,0x01},
+{0xEF56,0xD1,0x01},
+{0xEF57,0x8A,0x01},
+{0xEF58,0x3E,0x01},
+{0xEF59,0xF4,0x01},
+{0xEF5A,0xA1,0x01},
+{0xEF5B,0x10,0x01},
+{0xEF5C,0xB9,0x01},
+{0xEF5D,0x48,0x01},
+{0xEF5E,0x46,0x01},
+{0xEF5F,0x1F,0x01},
+{0xEF60,0x82,0x01},
+{0xEF61,0x10,0x01},
+{0xEF62,0x7E,0x01},
+{0xEF63,0xBC,0x01},
+{0xEF64,0xC3,0x01},
+{0xEF65,0x1C,0x01},
+{0xEF66,0xE3,0x01},
+{0xEF67,0x38,0x01},
+{0xEF68,0xC7,0x01},
+{0xEF69,0x3B,0x01},
+{0xEF6A,0xF7,0x01},
+{0xEF6B,0x71,0x01},
+{0xEF6C,0x90,0x01},
+{0xEF6D,0x7B,0x01},
+{0xEF6E,0x8E,0x01},
+{0xEF6F,0x53,0x01},
+{0xEF70,0x1A,0x01},
+{0xEF71,0xC5,0x01},
+{0xEF72,0x04,0x01},
+{0xEF73,0x46,0x01},
+{0xEF74,0x31,0x01},
+{0xEF75,0xA2,0x01},
+{0xEF76,0x39,0x01},
+{0xEF77,0x0E,0x01},
+{0xEF78,0x7E,0x01},
+{0xEF79,0x9A,0x01},
+{0xEF7A,0xA3,0x01},
+{0xEF7B,0x99,0x01},
+{0xEF7C,0xB5,0x01},
+{0xEF7D,0x34,0x01},
+{0xEF7E,0x85,0x01},
+{0xEF7F,0x28,0x01},
+{0xEF80,0x4D,0x01},
+{0xEF81,0x61,0x01},
+{0xEF82,0x8B,0x01},
+{0xEF83,0x67,0x01},
+{0xEF84,0xB0,0x01},
+{0xEF85,0x53,0x01},
+{0xEF86,0x1B,0x01},
+{0xEF87,0xBB,0x01},
+{0xEF88,0x08,0x01},
+{0xEF89,0x45,0x01},
+{0xEF8A,0x24,0x01},
+{0xEF8B,0x17,0x01},
+{0xEF8C,0x11,0x01},
+{0xEF8D,0x09,0x01},
+{0xEF8E,0x51,0x01},
+{0xEF8F,0xF2,0x01},
+{0xEF90,0xA2,0x01},
+{0xEF91,0x9B,0x01},
+{0xEF92,0xD3,0x01},
+{0xEF93,0x90,0x01},
+{0xEF94,0xC5,0x01},
+{0xEF95,0x25,0x01},
+{0xEF96,0x0A,0x01},
+{0xEF97,0x01,0x01},
+{0xEF98,0x48,0x01},
+{0xEF99,0x43,0x01},
+{0xEF9A,0x62,0x01},
+{0xEF9B,0x52,0x01},
+{0xEF9C,0x16,0x01},
+{0xEF9D,0xD5,0x01},
+{0xEF9E,0x9C,0x01},
+{0xEF9F,0xC6,0x01},
+{0xEFA0,0x2C,0x01},
+{0xEFA1,0x2F,0x01},
+{0xEFA2,0x51,0x01},
+{0xEFA3,0x48,0x01},
+{0xEFA4,0x40,0x01},
+{0xEFA5,0x1C,0x01},
+{0xEFA6,0x22,0x01},
+{0xEFA7,0x93,0x01},
+{0xEFA8,0xB3,0x01},
+{0xEFA9,0xB8,0x01},
+{0xEFAA,0x46,0x01},
+{0xEFAB,0x37,0x01},
+{0xEFAC,0x7A,0x01},
+{0xEFAD,0x21,0x01},
+{0xEFAE,0x4A,0x01},
+{0xEFAF,0x48,0x01},
+{0xEFB0,0x30,0x01},
+{0xEFB1,0x52,0x01},
+{0xEFB2,0x12,0x01},
+{0xEFB3,0xA4,0x01},
+{0xEFB4,0xF0,0x01},
+{0xEFB5,0xE5,0x01},
+{0xEFB6,0x37,0x01},
+{0xEFB7,0xD6,0x01},
+{0xEFB8,0xF9,0x01},
+{0xEFB9,0x8C,0x01},
+{0xEFBA,0x5B,0x01},
+{0xEFBB,0x9E,0x01},
+{0xEFBC,0x62,0x01},
+{0xEFBD,0x14,0x01},
+{0xEFBE,0xA9,0x01},
+{0xEFBF,0xC8,0x01},
+{0xEFC0,0xA5,0x01},
+{0xEFC1,0x34,0x01},
+{0xEFC2,0xE0,0x01},
+{0xEFC3,0xD1,0x01},
+{0xEFC4,0x8F,0x01},
+{0xEFC5,0x73,0x01},
+{0xEFC6,0x4C,0x01},
+{0xEFC7,0xE3,0x01},
+{0xEFC8,0x18,0x01},
+{0xEFC9,0xC2,0x01},
+{0xEFCA,0x3C,0x01},
+{0xEFCB,0x46,0x01},
+{0xEFCC,0x35,0x01},
+{0xEFCD,0xD2,0x01},
+{0xEFCE,0x09,0x01},
+{0xEFCF,0x90,0x01},
+{0xEFD0,0x85,0x01},
+{0xEFD1,0xF6,0x01},
+{0xEFD2,0x03,0x01},
+{0xEFD3,0x1E,0x01},
+{0xEFD4,0xE7,0x01},
+{0xEFD5,0x20,0x01},
+{0xEFD6,0x27,0x01},
+{0xEFD7,0x3A,0x01},
+{0xEFD8,0xE4,0x01},
+{0xEFD9,0x01,0x01},
+{0xEFDA,0x90,0x01},
+{0xEFDB,0x87,0x01},
+{0xEFDC,0x30,0x01},
+{0xEFDD,0x04,0x01},
+{0xEFDE,0x22,0x01},
+{0xEFDF,0x0B,0x01},
+{0xEFE0,0x2D,0x01},
+{0xEFE1,0x28,0x01},
+{0xEFE2,0x41,0x01},
+{0xEFE3,0x10,0x01},
+{0xEFE4,0xDA,0x01},
+{0xEFE5,0x90,0x01},
+{0xEFE6,0x88,0x01},
+{0xEFE7,0x3C,0x01},
+{0xEFE8,0x04,0x01},
+{0xEFE9,0x00,0x01},
+{0xEFEA,0x00,0x01},
+{0xEFEB,0x00,0x01},
+{0xEFEC,0x00,0x01},
+{0xEFED,0x00,0x01},
+
+
+
+//SHD3 D65+TL84 C01//
+{0xED00,0x9191,0x02},//
+{0xEFEE,0x12,0x01},
+{0xEFEF,0x42,0x01},
+{0xEFF0,0x51,0x01},
+{0xEFF1,0x89,0x01},
+{0xEFF2,0x38,0x01},
+{0xEFF3,0xD4,0x01},
+{0xEFF4,0x21,0x01},
+{0xEFF5,0x10,0x01},
+{0xEFF6,0xAD,0x01},
+{0xEFF7,0xA8,0x01},
+{0xEFF8,0x45,0x01},
+{0xEFF9,0x18,0x01},
+{0xEFFA,0x4A,0x01},
+{0xEFFB,0x50,0x01},
+{0xEFFC,0x7D,0x01},
+{0xEFFD,0xBA,0x01},
+{0xEFFE,0xD3,0x01},
+{0xEFFF,0x1C,0x01},
+{0xF000,0xE4,0x01},
+{0xF001,0x40,0x01},
+{0xF002,0x27,0x01},
+{0xF003,0x3C,0x01},
+{0xF004,0xF8,0x01},
+{0xF005,0x69,0x01},
+{0xF006,0x10,0x01},
+{0xF007,0x7B,0x01},
+{0xF008,0x8E,0x01},
+{0xF009,0x63,0x01},
+{0xF00A,0x1A,0x01},
+{0xF00B,0xC6,0x01},
+{0xF00C,0x10,0x01},
+{0xF00D,0xA6,0x01},
+{0xF00E,0x31,0x01},
+{0xF00F,0xA6,0x01},
+{0xF010,0x59,0x01},
+{0xF011,0x8E,0x01},
+{0xF012,0x7E,0x01},
+{0xF013,0x9A,0x01},
+{0xF014,0xB3,0x01},
+{0xF015,0x19,0x01},
+{0xF016,0xB6,0x01},
+{0xF017,0x38,0x01},
+{0xF018,0xA5,0x01},
+{0xF019,0x28,0x01},
+{0xF01A,0x4F,0x01},
+{0xF01B,0x79,0x01},
+{0xF01C,0xCB,0x01},
+{0xF01D,0x68,0x01},
+{0xF01E,0xBA,0x01},
+{0xF01F,0x53,0x01},
+{0xF020,0x9B,0x01},
+{0xF021,0xBB,0x01},
+{0xF022,0x0C,0x01},
+{0xF023,0x65,0x01},
+{0xF024,0x24,0x01},
+{0xF025,0x17,0x01},
+{0xF026,0x21,0x01},
+{0xF027,0xC9,0x01},
+{0xF028,0x51,0x01},
+{0xF029,0xFC,0x01},
+{0xF02A,0xF2,0x01},
+{0xF02B,0x9B,0x01},
+{0xF02C,0xD3,0x01},
+{0xF02D,0x94,0x01},
+{0xF02E,0xC5,0x01},
+{0xF02F,0x25,0x01},
+{0xF030,0x0A,0x01},
+{0xF031,0x01,0x01},
+{0xF032,0x48,0x01},
+{0xF033,0x43,0x01},
+{0xF034,0x66,0x01},
+{0xF035,0x92,0x01},
+{0xF036,0x96,0x01},
+{0xF037,0xD7,0x01},
+{0xF038,0xA0,0x01},
+{0xF039,0xE6,0x01},
+{0xF03A,0x2C,0x01},
+{0xF03B,0x2F,0x01},
+{0xF03C,0x51,0x01},
+{0xF03D,0x48,0x01},
+{0xF03E,0x40,0x01},
+{0xF03F,0x1E,0x01},
+{0xF040,0x42,0x01},
+{0xF041,0x93,0x01},
+{0xF042,0xB5,0x01},
+{0xF043,0xCC,0x01},
+{0xF044,0x46,0x01},
+{0xF045,0x37,0x01},
+{0xF046,0x7C,0x01},
+{0xF047,0x29,0x01},
+{0xF048,0x8A,0x01},
+{0xF049,0x48,0x01},
+{0xF04A,0x32,0x01},
+{0xF04B,0x72,0x01},
+{0xF04C,0x12,0x01},
+{0xF04D,0xA5,0x01},
+{0xF04E,0x00,0x01},
+{0xF04F,0xA6,0x01},
+{0xF050,0x38,0x01},
+{0xF051,0xD7,0x01},
+{0xF052,0x01,0x01},
+{0xF053,0x0D,0x01},
+{0xF054,0x5C,0x01},
+{0xF055,0xA2,0x01},
+{0xF056,0x82,0x01},
+{0xF057,0x94,0x01},
+{0xF058,0xAA,0x01},
+{0xF059,0xD8,0x01},
+{0xF05A,0x45,0x01},
+{0xF05B,0x35,0x01},
+{0xF05C,0xE5,0x01},
+{0xF05D,0xC9,0x01},
+{0xF05E,0xCF,0x01},
+{0xF05F,0x73,0x01},
+{0xF060,0x50,0x01},
+{0xF061,0x03,0x01},
+{0xF062,0x99,0x01},
+{0xF063,0xC3,0x01},
+{0xF064,0x4C,0x01},
+{0xF065,0xE6,0x01},
+{0xF066,0x35,0x01},
+{0xF067,0xD7,0x01},
+{0xF068,0x21,0x01},
+{0xF069,0x10,0x01},
+{0xF06A,0x84,0x01},
+{0xF06B,0xF2,0x01},
+{0xF06C,0x03,0x01},
+{0xF06D,0x9E,0x01},
+{0xF06E,0xE8,0x01},
+{0xF06F,0x2C,0x01},
+{0xF070,0xA7,0x01},
+{0xF071,0x3A,0x01},
+{0xF072,0xE8,0x01},
+{0xF073,0x11,0x01},
+{0xF074,0x90,0x01},
+{0xF075,0x87,0x01},
+{0xF076,0x18,0x01},
+{0xF077,0x94,0x01},
+{0xF078,0x21,0x01},
+{0xF079,0x09,0x01},
+{0xF07A,0x2D,0x01},
+{0xF07B,0x68,0x01},
+{0xF07C,0x41,0x01},
+{0xF07D,0x11,0x01},
+{0xF07E,0xDA,0x01},
+{0xF07F,0x10,0x01},
+{0xF080,0x88,0x01},
+{0xF081,0x2A,0x01},
+{0xF082,0x04,0x01},
+{0xF083,0x00,0x01},
+{0xF084,0x00,0x01},
+{0xF085,0x00,0x01},
+{0xF086,0x00,0x01},
+{0xF087,0x00,0x01},
+{0xF088,0xBE,0x01},
+{0xF089,0x51,0x01},
+{0xF08A,0x4E,0x01},
+{0xF08B,0x6F,0x01},
+{0xF08C,0x6C,0x01},
+{0xF08D,0x43,0x01},
+{0xF08E,0x1B,0x01},
+{0xF08F,0xDA,0x01},
+{0xF090,0xEC,0x01},
+{0xF091,0x46,0x01},
+{0xF092,0x38,0x01},
+{0xF093,0xBB,0x01},
+{0xF094,0xC1,0x01},
+{0xF095,0xCD,0x01},
+{0xF096,0x69,0x01},
+{0xF097,0x26,0x01},
+{0xF098,0x93,0x01},
+{0xF099,0x98,0x01},
+{0xF09A,0xC1,0x01},
+{0xF09B,0x20,0x01},
+{0xF09C,0x26,0x01},
+{0xF09D,0x32,0x01},
+{0xF09E,0xA5,0x01},
+{0xF09F,0xB1,0x01},
+{0xF0A0,0x8D,0x01},
+{0xF0A1,0x67,0x01},
+{0xF0A2,0x0E,0x01},
+{0xF0A3,0x23,0x01},
+{0xF0A4,0x97,0x01},
+{0xF0A5,0xB0,0x01},
+{0xF0A6,0x6C,0x01},
+{0xF0A7,0x25,0x01},
+{0xF0A8,0x2C,0x01},
+{0xF0A9,0x71,0x01},
+{0xF0AA,0x41,0x01},
+{0xF0AB,0x0C,0x01},
+{0xF0AC,0x69,0x01},
+{0xF0AD,0x14,0x01},
+{0xF0AE,0xB3,0x01},
+{0xF0AF,0x96,0x01},
+{0xF0B0,0xA6,0x01},
+{0xF0B1,0xE8,0x01},
+{0xF0B2,0x64,0x01},
+{0xF0B3,0x26,0x01},
+{0xF0B4,0x3A,0x01},
+{0xF0B5,0x79,0x01},
+{0xF0B6,0x4A,0x01},
+{0xF0B7,0x5B,0x01},
+{0xF0B8,0x18,0x01},
+{0xF0B9,0xA3,0x01},
+{0xF0BA,0x97,0x01},
+{0xF0BB,0xA9,0x01},
+{0xF0BC,0xBC,0x01},
+{0xF0BD,0x24,0x01},
+{0xF0BE,0x23,0x01},
+{0xF0BF,0x13,0x01},
+{0xF0C0,0xE1,0x01},
+{0xF0C1,0xC8,0x01},
+{0xF0C2,0x4C,0x01},
+{0xF0C3,0xAA,0x01},
+{0xF0C4,0xA2,0x01},
+{0xF0C5,0x97,0x01},
+{0xF0C6,0xB6,0x01},
+{0xF0C7,0x14,0x01},
+{0xF0C8,0x05,0x01},
+{0xF0C9,0x24,0x01},
+{0xF0CA,0x06,0x01},
+{0xF0CB,0x09,0x01},
+{0xF0CC,0xC8,0x01},
+{0xF0CD,0x42,0x01},
+{0xF0CE,0x48,0x01},
+{0xF0CF,0x82,0x01},
+{0xF0D0,0x14,0x01},
+{0xF0D1,0xB8,0x01},
+{0xF0D2,0xC0,0x01},
+{0xF0D3,0xE5,0x01},
+{0xF0D4,0x28,0x01},
+{0xF0D5,0x21,0x01},
+{0xF0D6,0x39,0x01},
+{0xF0D7,0x08,0x01},
+{0xF0D8,0x40,0x01},
+{0xF0D9,0x14,0x01},
+{0xF0DA,0x62,0x01},
+{0xF0DB,0x92,0x01},
+{0xF0DC,0xA4,0x01},
+{0xF0DD,0xC4,0x01},
+{0xF0DE,0x05,0x01},
+{0xF0DF,0x30,0x01},
+{0xF0E0,0x58,0x01},
+{0xF0E1,0xA1,0x01},
+{0xF0E2,0x49,0x01},
+{0xF0E3,0x46,0x01},
+{0xF0E4,0x22,0x01},
+{0xF0E5,0xB2,0x01},
+{0xF0E6,0x91,0x01},
+{0xF0E7,0x9A,0x01},
+{0xF0E8,0x58,0x01},
+{0xF0E9,0xA5,0x01},
+{0xF0EA,0x2F,0x01},
+{0xF0EB,0x96,0x01},
+{0xF0EC,0x99,0x01},
+{0xF0ED,0x8B,0x01},
+{0xF0EE,0x54,0x01},
+{0xF0EF,0x74,0x01},
+{0xF0F0,0x32,0x01},
+{0xF0F1,0x13,0x01},
+{0xF0F2,0x9D,0x01},
+{0xF0F3,0x38,0x01},
+{0xF0F4,0xC5,0x01},
+{0xF0F5,0x2D,0x01},
+{0xF0F6,0x90,0x01},
+{0xF0F7,0x59,0x01},
+{0xF0F8,0x4D,0x01},
+{0xF0F9,0x64,0x01},
+{0xF0FA,0xEE,0x01},
+{0xF0FB,0x62,0x01},
+{0xF0FC,0x16,0x01},
+{0xF0FD,0xAE,0x01},
+{0xF0FE,0x84,0x01},
+{0xF0FF,0x25,0x01},
+{0xF100,0x2E,0x01},
+{0xF101,0x8B,0x01},
+{0xF102,0x31,0x01},
+{0xF103,0xCD,0x01},
+{0xF104,0x6F,0x01},
+{0xF105,0x60,0x01},
+{0xF106,0xC3,0x01},
+{0xF107,0x19,0x01},
+{0xF108,0xC7,0x01},
+{0xF109,0x14,0x01},
+{0xF10A,0x26,0x01},
+{0xF10B,0x31,0x01},
+{0xF10C,0x97,0x01},
+{0xF10D,0x41,0x01},
+{0xF10E,0x8D,0x01},
+{0xF10F,0x6D,0x01},
+{0xF110,0x86,0x01},
+{0xF111,0xE3,0x01},
+{0xF112,0x9C,0x01},
+{0xF113,0xE2,0x01},
+{0xF114,0xD8,0x01},
+{0xF115,0x06,0x01},
+{0xF116,0x36,0x01},
+{0xF117,0xB5,0x01},
+{0xF118,0xE9,0x01},
+{0xF119,0x4D,0x01},
+{0xF11A,0x70,0x01},
+{0xF11B,0x68,0x01},
+{0xF11C,0x03,0x01},
+{0xF11D,0x00,0x01},
+{0xF11E,0x00,0x01},
+{0xF11F,0x00,0x01},
+{0xF120,0x00,0x01},
+{0xF121,0x00,0x01},
+
+
+//SHD TH
+{0x6C32,0x1964,0x02},    // SHD_INP_TH_HB_H_R2
+{0x6C34,0x18CE,0x02},    // SHD_INP_TH_HB_L_R2
+{0x6C36,0x10CC,0x02},    // SHD_INP_TH_LB_H_R2
+{0x6C38,0x1004,0x02},    // SHD_INP_TH_LB_L_R2
+{0x6C3C,0x10CC,0x02},    // SHD_INP_TH_HB_H_RB
+{0x6C3E,0x1004,0x02},    // SHD_INP_TH_HB_L_RB
+{0x6C40,0x0000,0x02},    // SHD_INP_TH_LB_H_RB
+{0x6C42,0x0000,0x02},    // SHD_INP_TH_LB_L_RB
+
+//PreWB_offset (for SHD2)
+{0x6828,0x0013,0x02},    // SHD_PRER_OFFSET_R2 :
+//PreWB_offset (for SHD3)
+{0x682C,0x000C,0x02},    // SHD_PRER_OFFSET_RB :
+{0x6830,0xFFFF,0x02},    // SHD_PREB_OFFSET_RB :
+
+// CXC/SHD EN
+{0x01BC,0x57,0x01},    // CXC ON SHD ON INP ON GAIN OFF
+};
+
+static const isx012_regset_t ISX012_Shading_0[] =
+{
+{0x01BC,0x50,0x01},    // CXC OFF SHD OFF
+{0xEB00,0x8282,0x02},	//valid_code
+{0xEB02,0xFE,0x01},
+{0xEB03,0x84,0x01},
+{0xEB04,0x3F,0x01},
+{0xEB05,0x01,0x01},
+{0xEB06,0x50,0x01},
+{0xEB07,0x08,0x01},
+{0xEB08,0x14,0x01},
+{0xEB09,0xFF,0x01},
+{0xEB0A,0x45,0x01},
+{0xEB0B,0x80,0x01},
+{0xEB0C,0x01,0x01},
+{0xEB0D,0x68,0x01},
+{0xEB0E,0x04,0x01},
+{0xEB0F,0x1A,0x01},
+{0xEB10,0x81,0x01},
+{0xEB11,0x86,0x01},
+{0xEB12,0x3F,0x01},
+{0xEB13,0xE1,0x01},
+{0xEB14,0x4F,0x01},
+{0xEB15,0x00,0x01},
+{0xEB16,0x14,0x01},
+{0xEB17,0x02,0x01},
+{0xEB18,0xC5,0x01},
+{0xEB19,0x7F,0x01},
+{0xEB1A,0x11,0x01},
+{0xEB1B,0x60,0x01},
+{0xEB1C,0x00,0x01},
+{0xEB1D,0x1A,0x01},
+{0xEB1E,0x81,0x01},
+{0xEB1F,0x46,0x01},
+{0xEB20,0xA0,0x01},
+{0xEB21,0x01,0x01},
+{0xEB22,0x48,0x01},
+{0xEB23,0x00,0x01},
+{0xEB24,0x12,0x01},
+{0xEB25,0x81,0x01},
+{0xEB26,0x05,0x01},
+{0xEB27,0x20,0x01},
+{0xEB28,0xF1,0x01},
+{0xEB29,0x4F,0x01},
+{0xEB2A,0x00,0x01},
+{0xEB2B,0x14,0x01},
+{0xEB2C,0x82,0x01},
+{0xEB2D,0x85,0x01},
+{0xEB2E,0x80,0x01},
+{0xEB2F,0x21,0x01},
+{0xEB30,0x60,0x01},
+{0xEB31,0x04,0x01},
+{0xEB32,0x12,0x01},
+{0xEB33,0x81,0x01},
+{0xEB34,0x84,0x01},
+{0xEB35,0xE0,0x01},
+{0xEB36,0x00,0x01},
+{0xEB37,0x28,0x01},
+{0xEB38,0x04,0x01},
+{0xEB39,0x0C,0x01},
+{0xEB3A,0x82,0x01},
+{0xEB3B,0x43,0x01},
+{0xEB3C,0x20,0x01},
+{0xEB3D,0x11,0x01},
+{0xEB3E,0x68,0x01},
+{0xEB3F,0x04,0x01},
+{0xEB40,0x1A,0x01},
+{0xEB41,0x82,0x01},
+{0xEB42,0x83,0x01},
+{0xEB43,0xE0,0x01},
+{0xEB44,0x00,0x01},
+{0xEB45,0x20,0x01},
+{0xEB46,0x00,0x01},
+{0xEB47,0x06,0x01},
+{0xEB48,0xFF,0x01},
+{0xEB49,0x41,0x01},
+{0xEB4A,0x80,0x01},
+{0xEB4B,0x10,0x01},
+{0xEB4C,0x30,0x01},
+{0xEB4D,0x08,0x01},
+{0xEB4E,0x14,0x01},
+{0xEB4F,0x02,0x01},
+{0xEB50,0x45,0x01},
+{0xEB51,0xC0,0x01},
+{0xEB52,0x10,0x01},
+{0xEB53,0x30,0x01},
+{0xEB54,0x04,0x01},
+{0xEB55,0x04,0x01},
+{0xEB56,0x01,0x01},
+{0xEB57,0xC0,0x01},
+{0xEB58,0x3F,0x01},
+{0xEB59,0x10,0x01},
+{0xEB5A,0x10,0x01},
+{0xEB5B,0x04,0x01},
+{0xEB5C,0x0A,0x01},
+{0xEB5D,0x80,0x01},
+{0xEB5E,0x03,0x01},
+{0xEB5F,0xE0,0x01},
+{0xEB60,0x10,0x01},
+{0xEB61,0x28,0x01},
+{0xEB62,0x04,0x01},
+{0xEB63,0x0A,0x01},
+{0xEB64,0x81,0x01},
+{0xEB65,0x01,0x01},
+{0xEB66,0x00,0x01},
+{0xEB67,0x10,0x01},
+{0xEB68,0x00,0x01},
+{0xEB69,0x04,0x01},
+{0xEB6A,0x04,0x01},
+{0xEB6B,0x01,0x01},
+{0xEB6C,0x42,0x01},
+{0xEB6D,0xE0,0x01},
+{0xEB6E,0x10,0x01},
+{0xEB6F,0x38,0x01},
+{0xEB70,0xFC,0x01},
+{0xEB71,0x0D,0x01},
+{0xEB72,0x7F,0x01},
+{0xEB73,0x43,0x01},
+{0xEB74,0x60,0x01},
+{0xEB75,0x00,0x01},
+{0xEB76,0x08,0x01},
+{0xEB77,0x08,0x01},
+{0xEB78,0x02,0x01},
+{0xEB79,0x81,0x01},
+{0xEB7A,0x41,0x01},
+{0xEB7B,0x80,0x01},
+{0xEB7C,0x10,0x01},
+{0xEB7D,0x30,0x01},
+{0xEB7E,0x04,0x01},
+{0xEB7F,0x0C,0x01},
+{0xEB80,0x01,0x01},
+{0xEB81,0x43,0x01},
+{0xEB82,0xC0,0x01},
+{0xEB83,0x20,0x01},
+{0xEB84,0x28,0x01},
+{0xEB85,0x08,0x01},
+{0xEB86,0x06,0x01},
+{0xEB87,0x02,0x01},
+{0xEB88,0xC2,0x01},
+{0xEB89,0xA0,0x01},
+{0xEB8A,0x30,0x01},
+{0xEB8B,0x30,0x01},
+{0xEB8C,0x0C,0x01},
+{0xEB8D,0x12,0x01},
+{0xEB8E,0x83,0x01},
+{0xEB8F,0x84,0x01},
+{0xEB90,0x00,0x01},
+{0xEB91,0x21,0x01},
+{0xEB92,0x40,0x01},
+{0xEB93,0x0C,0x01},
+{0xEB94,0x0C,0x01},
+{0xEB95,0x82,0x01},
+{0xEB96,0x03,0x01},
+{0xEB97,0xC1,0x01},
+{0xEB98,0x40,0x01},
+{0xEB99,0x40,0x01},
+{0xEB9A,0x08,0x01},
+{0xEB9B,0x10,0x01},
+{0xEB9C,0x03,0x01},
+{0xEB9D,0xC4,0x01},
+{0xEB9E,0x00,0x01},
+{0xEB9F,0x21,0x01},
+{0xEBA0,0x38,0x01},
+{0xEBA1,0x08,0x01},
+{0xEBA2,0x0E,0x01},
+{0xEBA3,0x82,0x01},
+{0xEBA4,0xC3,0x01},
+{0xEBA5,0x20,0x01},
+{0xEBA6,0x41,0x01},
+{0xEBA7,0x48,0x01},
+{0xEBA8,0x00,0x01},
+{0xEBA9,0x14,0x01},
+{0xEBAA,0x83,0x01},
+{0xEBAB,0x44,0x01},
+{0xEBAC,0x20,0x01},
+{0xEBAD,0x11,0x01},
+{0xEBAE,0x48,0x01},
+{0xEBAF,0x08,0x01},
+{0xEBB0,0x0E,0x01},
+{0xEBB1,0x82,0x01},
+{0xEBB2,0x83,0x01},
+{0xEBB3,0xE0,0x01},
+{0xEBB4,0x30,0x01},
+{0xEBB5,0x48,0x01},
+{0xEBB6,0x10,0x01},
+{0xEBB7,0x12,0x01},
+{0xEBB8,0x00,0x01},
+{0xEBB9,0xC5,0x01},
+{0xEBBA,0x20,0x01},
+{0xEBBB,0x11,0x01},
+{0xEBBC,0x48,0x01},
+{0xEBBD,0x04,0x01},
+{0xEBBE,0x12,0x01},
+{0xEBBF,0x04,0x01},
+{0xEBC0,0x3B,0x01},
+{0xEBC1,0xC1,0x01},
+{0xEBC2,0x1E,0x01},
+{0xEBC3,0xC8,0x01},
+{0xEBC4,0x0F,0x01},
+{0xEBC5,0xF8,0x01},
+{0xEBC6,0x02,0x01},
+{0xEBC7,0xBB,0x01},
+{0xEBC8,0x60,0x01},
+{0xEBC9,0x0F,0x01},
+{0xEBCA,0xB8,0x01},
+{0xEBCB,0x0F,0x01},
+{0xEBCC,0xEA,0x01},
+{0xEBCD,0x83,0x01},
+{0xEBCE,0x3A,0x01},
+{0xEBCF,0xC1,0x01},
+{0xEBD0,0x4E,0x01},
+{0xEBD1,0xB0,0x01},
+{0xEBD2,0x07,0x01},
+{0xEBD3,0xF2,0x01},
+{0xEBD4,0x03,0x01},
+{0xEBD5,0xBE,0x01},
+{0xEBD6,0xC0,0x01},
+{0xEBD7,0x2E,0x01},
+{0xEBD8,0xD8,0x01},
+{0xEBD9,0x03,0x01},
+{0xEBDA,0xEE,0x01},
+{0xEBDB,0x83,0x01},
+{0xEBDC,0xFA,0x01},
+{0xEBDD,0xA0,0x01},
+{0xEBDE,0x2E,0x01},
+{0xEBDF,0xB0,0x01},
+{0xEBE0,0x0B,0x01},
+{0xEBE1,0xEC,0x01},
+{0xEBE2,0x05,0x01},
+{0xEBE3,0xBD,0x01},
+{0xEBE4,0x60,0x01},
+{0xEBE5,0x2F,0x01},
+{0xEBE6,0xD0,0x01},
+{0xEBE7,0x07,0x01},
+{0xEBE8,0xEC,0x01},
+{0xEBE9,0x02,0x01},
+{0xEBEA,0xBC,0x01},
+{0xEBEB,0x40,0x01},
+{0xEBEC,0x2F,0x01},
+{0xEBED,0xD0,0x01},
+{0xEBEE,0x13,0x01},
+{0xEBEF,0xEE,0x01},
+{0xEBF0,0x84,0x01},
+{0xEBF1,0xBB,0x01},
+{0xEBF2,0x00,0x01},
+{0xEBF3,0x1F,0x01},
+{0xEBF4,0xC8,0x01},
+{0xEBF5,0xFF,0x01},
+{0xEBF6,0xEF,0x01},
+{0xEBF7,0x00,0x01},
+{0xEBF8,0x7D,0x01},
+{0xEBF9,0x60,0x01},
+{0xEBFA,0x2F,0x01},
+{0xEBFB,0xD0,0x01},
+{0xEBFC,0x0B,0x01},
+{0xEBFD,0xF4,0x01},
+{0xEBFE,0x85,0x01},
+{0xEBFF,0x7D,0x01},
+{0xEC00,0x61,0x01},
+{0xEC01,0x0F,0x01},
+{0xEC02,0xC0,0x01},
+{0xEC03,0xFF,0x01},
+{0xEC04,0xF7,0x01},
+{0xEC05,0x7F,0x01},
+{0xEC06,0x3D,0x01},
+{0xEC07,0x40,0x01},
+{0xEC08,0xFF,0x01},
+{0xEC09,0xDF,0x01},
+{0xEC0A,0x07,0x01},
+{0xEC0B,0xFA,0x01},
+{0xEC0C,0x81,0x01},
+{0xEC0D,0x3E,0x01},
+{0xEC0E,0x61,0x01},
+{0xEC0F,0x4F,0x01},
+{0xEC10,0xD8,0x01},
+{0xEC11,0x0B,0x01},
+{0xEC12,0xFC,0x01},
+{0xEC13,0xFE,0x01},
+{0xEC14,0x3D,0x01},
+{0xEC15,0xC0,0x01},
+{0xEC16,0xFF,0x01},
+{0xEC17,0xFF,0x01},
+{0xEC18,0x03,0x01},
+{0xEC19,0xFC,0x01},
+{0xEC1A,0x82,0x01},
+{0xEC1B,0xBE,0x01},
+{0xEC1C,0xA0,0x01},
+{0xEC1D,0x6F,0x01},
+{0xEC1E,0xF8,0x01},
+{0xEC1F,0x1B,0x01},
+{0xEC20,0xFE,0x01},
+{0xEC21,0x83,0x01},
+{0xEC22,0xBF,0x01},
+{0xEC23,0xE0,0x01},
+{0xEC24,0x0F,0x01},
+{0xEC25,0x10,0x01},
+{0xEC26,0x00,0x01},
+{0xEC27,0x00,0x01},
+{0xEC28,0x82,0x01},
+{0xEC29,0xC0,0x01},
+{0xEC2A,0x60,0x01},
+{0xEC2B,0x30,0x01},
+{0xEC2C,0x18,0x01},
+{0xEC2D,0x20,0x01},
+{0xEC2E,0x04,0x01},
+{0xEC2F,0x08,0x01},
+{0xEC30,0x81,0x01},
+{0xEC31,0x21,0x01},
+{0xEC32,0x30,0x01},
+{0xEC33,0x08,0x01},
+{0xEC34,0x08,0x01},
+{0xEC35,0x08,0x01},
+{0xEC36,0x82,0x01},
+{0xEC37,0x01,0x01},
+{0xEC38,0x81,0x01},
+{0xEC39,0x50,0x01},
+{0xEC3A,0x08,0x01},
+{0xEC3B,0x14,0x01},
+{0xEC3C,0x02,0x01},
+{0xEC3D,0x09,0x01},
+{0xEC3E,0x41,0x01},
+{0xEC3F,0x42,0x01},
+{0xEC40,0x70,0x01},
+{0xEC41,0x20,0x01},
+{0xEC42,0x0C,0x01},
+{0xEC43,0x06,0x01},
+{0xEC44,0x84,0x01},
+{0xEC45,0x42,0x01},
+{0xEC46,0xE1,0x01},
+{0xEC47,0x40,0x01},
+{0xEC48,0x38,0x01},
+{0xEC49,0x1C,0x01},
+{0xEC4A,0x0C,0x01},
+{0xEC4B,0x07,0x01},
+{0xEC4C,0x03,0x01},
+{0xEC4D,0xA2,0x01},
+{0xEC4E,0x80,0x01},
+{0xEC4F,0x28,0x01},
+{0xEC50,0x18,0x01},
+{0xEC51,0x10,0x01},
+{0xEC52,0x87,0x01},
+{0xEC53,0x43,0x01},
+{0xEC54,0x61,0x01},
+{0xEC55,0x41,0x01},
+{0xEC56,0x48,0x01},
+{0xEC57,0x14,0x01},
+{0xEC58,0x10,0x01},
+{0xEC59,0x07,0x01},
+{0xEC5A,0xC2,0x01},
+{0xEC5B,0x81,0x01},
+{0xEC5C,0x80,0x01},
+{0xEC5D,0x30,0x01},
+{0xEC5E,0x20,0x01},
+{0xEC5F,0x0C,0x01},
+{0xEC60,0x87,0x01},
+{0xEC61,0x83,0x01},
+{0xEC62,0xC1,0x01},
+{0xEC63,0x40,0x01},
+{0xEC64,0x38,0x01},
+{0xEC65,0x14,0x01},
+{0xEC66,0x0A,0x01},
+{0xEC67,0x07,0x01},
+{0xEC68,0xC3,0x01},
+{0xEC69,0xC1,0x01},
+{0xEC6A,0x70,0x01},
+{0xEC6B,0x30,0x01},
+{0xEC6C,0x20,0x01},
+{0xEC6D,0x0C,0x01},
+{0xEC6E,0x08,0x01},
+{0xEC6F,0xC3,0x01},
+{0xEC70,0xE1,0x01},
+{0xEC71,0x60,0x01},
+{0xEC72,0x30,0x01},
+{0xEC73,0x10,0x01},
+{0xEC74,0x0E,0x01},
+{0xEC75,0x85,0x01},
+{0xEC76,0xC2,0x01},
+{0xEC77,0xC1,0x01},
+{0xEC78,0x70,0x01},
+{0xEC79,0x30,0x01},
+{0xEC7A,0x1C,0x01},
+{0xEC7B,0x0C,0x01},
+
+//SHD1(from CO1)
+{0xED02,0xE6,0x01},
+{0xED03,0x61,0x01},
+{0xED04,0x92,0x01},
+{0xED05,0x7C,0x01},
+{0xED06,0xBE,0x01},
+{0xED07,0xB4,0x01},
+{0xED08,0x9E,0x01},
+{0xED09,0x2C,0x01},
+{0xED0A,0x75,0x01},
+{0xED0B,0x47,0x01},
+{0xED0C,0x49,0x01},
+{0xED0D,0xD7,0x01},
+{0xED0E,0x61,0x01},
+{0xED0F,0x12,0x01},
+{0xED10,0x76,0x01},
+{0xED11,0xA8,0x01},
+{0xED12,0x34,0x01},
+{0xED13,0x1E,0x01},
+{0xED14,0x31,0x01},
+{0xED15,0xA1,0x01},
+{0xED16,0xC7,0x01},
+{0xED17,0x4C,0x01},
+{0xED18,0xDE,0x01},
+{0xED19,0xC1,0x01},
+{0xED1A,0xD2,0x01},
+{0xED1B,0x77,0x01},
+{0xED1C,0x76,0x01},
+{0xED1D,0x94,0x01},
+{0xED1E,0x9C,0x01},
+{0xED1F,0x10,0x01},
+{0xED20,0xC9,0x01},
+{0xED21,0xC6,0x01},
+{0xED22,0x40,0x01},
+{0xED23,0xA2,0x01},
+{0xED24,0x99,0x01},
+{0xED25,0x8F,0x01},
+{0xED26,0x66,0x01},
+{0xED27,0xDC,0x01},
+{0xED28,0xF3,0x01},
+{0xED29,0x19,0x01},
+{0xED2A,0xFC,0x01},
+{0xED2B,0xB0,0x01},
+{0xED2C,0xA6,0x01},
+{0xED2D,0x41,0x01},
+{0xED2E,0xC1,0x01},
+{0xED2F,0x49,0x01},
+{0xED30,0x91,0x01},
+{0xED31,0x75,0x01},
+{0xED32,0x8C,0x01},
+{0xED33,0x74,0x01},
+{0xED34,0x1C,0x01},
+{0xED35,0x0B,0x01},
+{0xED36,0x91,0x01},
+{0xED37,0x86,0x01},
+{0xED38,0x3D,0x01},
+{0xED39,0x87,0x01},
+{0xED3A,0x39,0x01},
+{0xED3B,0x4E,0x01},
+{0xED3C,0x5C,0x01},
+{0xED3D,0x50,0x01},
+{0xED3E,0x83,0x01},
+{0xED3F,0x16,0x01},
+{0xED40,0xCF,0x01},
+{0xED41,0xBC,0x01},
+{0xED42,0x45,0x01},
+{0xED43,0x35,0x01},
+{0xED44,0x83,0x01},
+{0xED45,0x41,0x01},
+{0xED46,0xCE,0x01},
+{0xED47,0x67,0x01},
+{0xED48,0xE8,0x01},
+{0xED49,0x33,0x01},
+{0xED4A,0x1C,0x01},
+{0xED4B,0x16,0x01},
+{0xED4C,0xC1,0x01},
+{0xED4D,0x86,0x01},
+{0xED4E,0x3E,0x01},
+{0xED4F,0x83,0x01},
+{0xED50,0xC1,0x01},
+{0xED51,0x0D,0x01},
+{0xED52,0x57,0x01},
+{0xED53,0x02,0x01},
+{0xED54,0x23,0x01},
+{0xED55,0x14,0x01},
+{0xED56,0xAE,0x01},
+{0xED57,0xE4,0x01},
+{0xED58,0x44,0x01},
+{0xED59,0x2A,0x01},
+{0xED5A,0x43,0x01},
+{0xED5B,0xF9,0x01},
+{0xED5C,0xCA,0x01},
+{0xED5D,0x56,0x01},
+{0xED5E,0x0C,0x01},
+{0xED5F,0x03,0x01},
+{0xED60,0x98,0x01},
+{0xED61,0xE2,0x01},
+{0xED62,0xA8,0x01},
+{0xED63,0x26,0x01},
+{0xED64,0x41,0x01},
+{0xED65,0x9E,0x01},
+{0xED66,0xC1,0x01},
+{0xED67,0xCE,0x01},
+{0xED68,0x59,0x01},
+{0xED69,0x1C,0x01},
+{0xED6A,0xB3,0x01},
+{0xED6B,0x93,0x01},
+{0xED6C,0xA7,0x01},
+{0xED6D,0x74,0x01},
+{0xED6E,0x04,0x01},
+{0xED6F,0x25,0x01},
+{0xED70,0x13,0x01},
+{0xED71,0xD9,0x01},
+{0xED72,0xC8,0x01},
+{0xED73,0x47,0x01},
+{0xED74,0x54,0x01},
+{0xED75,0xD2,0x01},
+{0xED76,0x93,0x01},
+{0xED77,0xAA,0x01},
+{0xED78,0x98,0x01},
+{0xED79,0xE5,0x01},
+{0xED7A,0x32,0x01},
+{0xED7B,0x9A,0x01},
+{0xED7C,0x29,0x01},
+{0xED7D,0xCF,0x01},
+{0xED7E,0x64,0x01},
+{0xED7F,0x8E,0x01},
+{0xED80,0x73,0x01},
+{0xED81,0x95,0x01},
+{0xED82,0xBB,0x01},
+{0xED83,0xA4,0x01},
+{0xED84,0xA4,0x01},
+{0xED85,0x26,0x01},
+{0xED86,0x0A,0x01},
+{0xED87,0x59,0x01},
+{0xED88,0x08,0x01},
+{0xED89,0x40,0x01},
+{0xED8A,0x00,0x01},
+{0xED8B,0xC2,0x01},
+{0xED8C,0x10,0x01},
+{0xED8D,0x88,0x01},
+{0xED8E,0xB0,0x01},
+{0xED8F,0x84,0x01},
+{0xED90,0x27,0x01},
+{0xED91,0x59,0x01},
+{0xED92,0xF1,0x01},
+{0xED93,0x0B,0x01},
+{0xED94,0x64,0x01},
+{0xED95,0xA2,0x01},
+{0xED96,0x43,0x01},
+{0xED97,0x99,0x01},
+{0xED98,0xE4,0x01},
+{0xED99,0x68,0x01},
+{0xED9A,0x25,0x01},
+{0xED9B,0x2F,0x01},
+{0xED9C,0x2B,0x01},
+{0xED9D,0xB1,0x01},
+{0xED9E,0xC9,0x01},
+{0xED9F,0x42,0x01},
+{0xEDA0,0x18,0x01},
+{0xEDA1,0x32,0x01},
+{0xEDA2,0x90,0x01},
+{0xEDA3,0x80,0x01},
+{0xEDA4,0x3C,0x01},
+{0xEDA5,0x24,0x01},
+{0xEDA6,0x22,0x01},
+{0xEDA7,0x2F,0x01},
+{0xEDA8,0xF1,0x01},
+{0xEDA9,0x09,0x01},
+{0xEDAA,0x57,0x01},
+{0xEDAB,0x00,0x01},
+{0xEDAC,0x53,0x01},
+{0xEDAD,0x99,0x01},
+{0xEDAE,0xEA,0x01},
+{0xEDAF,0x90,0x01},
+{0xEDB0,0xC6,0x01},
+{0xEDB1,0x3B,0x01},
+{0xEDB2,0x6D,0x01},
+{0xEDB3,0x99,0x01},
+{0xEDB4,0x4C,0x01},
+{0xEDB5,0x50,0x01},
+{0xEDB6,0xA4,0x01},
+{0xEDB7,0x32,0x01},
+{0xEDB8,0x12,0x01},
+{0xEDB9,0x94,0x01},
+{0xEDBA,0x64,0x01},
+{0xEDBB,0xA4,0x01},
+{0xEDBC,0x23,0x01},
+{0xEDBD,0x25,0x01},
+{0xEDBE,0x71,0x01},
+{0xEDBF,0x49,0x01},
+{0xEDC0,0x51,0x01},
+{0xEDC1,0xB2,0x01},
+{0xEDC2,0x02,0x01},
+{0xEDC3,0x17,0x01},
+{0xEDC4,0xCD,0x01},
+{0xEDC5,0x98,0x01},
+{0xEDC6,0x86,0x01},
+{0xEDC7,0x3D,0x01},
+{0xEDC8,0xBC,0x01},
+{0xEDC9,0x01,0x01},
+{0xEDCA,0x50,0x01},
+{0xEDCB,0x63,0x01},
+{0xEDCC,0x80,0x01},
+{0xEDCD,0x63,0x01},
+{0xEDCE,0x16,0x01},
+{0xEDCF,0xC3,0x01},
+{0xEDD0,0x2C,0x01},
+{0xEDD1,0x25,0x01},
+{0xEDD2,0x2C,0x01},
+{0xEDD3,0x43,0x01},
+{0xEDD4,0xB1,0x01},
+{0xEDD5,0x4A,0x01},
+{0xEDD6,0x53,0x01},
+{0xEDD7,0xCC,0x01},
+{0xEDD8,0x82,0x01},
+{0xEDD9,0x96,0x01},
+{0xEDDA,0xC7,0x01},
+{0xEDDB,0x40,0x01},
+{0xEDDC,0xA6,0x01},
+{0xEDDD,0x39,0x01},
+{0xEDDE,0xBE,0x01},
+{0xEDDF,0x91,0x01},
+{0xEDE0,0xD0,0x01},
+{0xEDE1,0x75,0x01},
+{0xEDE2,0x54,0x01},
+{0xEDE3,0x34,0x01},
+{0xEDE4,0x1B,0x01},
+{0xEDE5,0xFC,0x01},
+{0xEDE6,0x4C,0x01},
+{0xEDE7,0x46,0x01},
+{0xEDE8,0x39,0x01},
+{0xEDE9,0x7D,0x01},
+{0xEDEA,0x71,0x01},
+{0xEDEB,0x8D,0x01},
+{0xEDEC,0x5D,0x01},
+{0xEDED,0x46,0x01},
+{0xEDEE,0xE3,0x01},
+{0xEDEF,0x17,0x01},
+{0xEDF0,0xD9,0x01},
+{0xEDF1,0x50,0x01},
+{0xEDF2,0x86,0x01},
+{0xEDF3,0x3A,0x01},
+{0xEDF4,0xB3,0x01},
+{0xEDF5,0x09,0x01},
+{0xEDF6,0x50,0x01},
+{0xEDF7,0x76,0x01},
+{0xEDF8,0x6A,0x01},
+{0xEDF9,0xF4,0x01},
+{0xEDFA,0x1E,0x01},
+{0xEDFB,0x25,0x01},
+{0xEDFC,0x61,0x01},
+{0xEDFD,0x67,0x01},
+{0xEDFE,0x45,0x01},
+{0xEDFF,0xC0,0x01},
+{0xEE00,0x69,0x01},
+{0xEE01,0xD0,0x01},
+{0xEE02,0x6B,0x01},
+{0xEE03,0xF6,0x01},
+{0xEE04,0x93,0x01},
+{0xEE05,0x9A,0x01},
+{0xEE06,0xFA,0x01},
+{0xEE07,0xB8,0x01},
+{0xEE08,0x26,0x01},
+{0xEE09,0x40,0x01},
+{0xEE0A,0xC0,0x01},
+{0xEE0B,0xB9,0x01},
+{0xEE0C,0xD0,0x01},
+{0xEE0D,0x75,0x01},
+{0xEE0E,0x6E,0x01},
+{0xEE0F,0xE4,0x01},
+{0xEE10,0x9E,0x01},
+{0xEE11,0x2D,0x01},
+{0xEE12,0xE1,0x01},
+{0xEE13,0xA7,0x01},
+{0xEE14,0x49,0x01},
+{0xEE15,0xFD,0x01},
+{0xEE16,0xB9,0x01},
+{0xEE17,0x52,0x01},
+{0xEE18,0x7C,0x01},
+{0xEE19,0x98,0x01},
+{0xEE1A,0x64,0x01},
+{0xEE1B,0x1E,0x01},
+{0xEE1C,0x22,0x01},
+{0xEE1D,0x89,0x01},
+{0xEE1E,0xA7,0x01},
+{0xEE1F,0x48,0x01},
+{0xEE20,0xE4,0x01},
+{0xEE21,0x49,0x01},
+{0xEE22,0x12,0x01},
+{0xEE23,0x7D,0x01},
+{0xEE24,0xB4,0x01},
+{0xEE25,0xB4,0x01},
+{0xEE26,0x1F,0x01},
+{0xEE27,0x31,0x01},
+{0xEE28,0xC5,0x01},
+{0xEE29,0x47,0x01},
+{0xEE2A,0x4B,0x01},
+{0xEE2B,0xC2,0x01},
+{0xEE2C,0x19,0x01},
+{0xEE2D,0x0F,0x01},
+{0xEE2E,0x73,0x01},
+{0xEE2F,0xE2,0x01},
+{0xEE30,0x13,0x01},
+{0xEE31,0x1C,0x01},
+{0xEE32,0xF5,0x01},
+{0xEE33,0xE0,0x01},
+{0xEE34,0xC6,0x01},
+{0xEE35,0x3B,0x01},
+{0xEE36,0xB6,0x01},
+{0xEE37,0xB1,0x01},
+{0xEE38,0xCE,0x01},
+{0xEE39,0x6D,0x01},
+{0xEE3A,0xB8,0x01},
+{0xEE3B,0xF3,0x01},
+{0xEE3C,0x9B,0x01},
+{0xEE3D,0xF2,0x01},
+{0xEE3E,0x18,0x01},
+{0xEE3F,0x27,0x01},
+{0xEE40,0x3D,0x01},
+{0xEE41,0xBF,0x01},
+{0xEE42,0xE9,0x01},
+{0xEE43,0xCE,0x01},
+{0xEE44,0x6E,0x01},
+{0xEE45,0xBA,0x01},
+{0xEE46,0x83,0x01},
+{0xEE47,0x9A,0x01},
+{0xEE48,0xE4,0x01},
+{0xEE49,0x50,0x01},
+{0xEE4A,0x66,0x01},
+{0xEE4B,0x36,0x01},
+{0xEE4C,0x8A,0x01},
+{0xEE4D,0x29,0x01},
+{0xEE4E,0x4D,0x01},
+{0xEE4F,0x61,0x01},
+{0xEE50,0x3A,0x01},
+{0xEE51,0xA3,0x01},
+{0xEE52,0x18,0x01},
+{0xEE53,0xD2,0x01},
+{0xEE54,0x50,0x01},
+{0xEE55,0x26,0x01},
+{0xEE56,0x36,0x01},
+{0xEE57,0xA8,0x01},
+{0xEE58,0x21,0x01},
+{0xEE59,0xCE,0x01},
+{0xEE5A,0x6E,0x01},
+{0xEE5B,0xB2,0x01},
+{0xEE5C,0x03,0x01},
+{0xEE5D,0x9A,0x01},
+{0xEE5E,0xE0,0x01},
+{0xEE5F,0x1C,0x01},
+{0xEE60,0x46,0x01},
+{0xEE61,0x34,0x01},
+{0xEE62,0x72,0x01},
+{0xEE63,0x41,0x01},
+{0xEE64,0x8C,0x01},
+{0xEE65,0x58,0x01},
+{0xEE66,0xE8,0x01},
+{0xEE67,0xC2,0x01},
+{0xEE68,0x95,0x01},
+{0xEE69,0xB5,0x01},
+{0xEE6A,0x88,0x01},
+{0xEE6B,0x65,0x01},
+{0xEE6C,0x2E,0x01},
+{0xEE6D,0x72,0x01},
+{0xEE6E,0x39,0x01},
+{0xEE6F,0x8C,0x01},
+{0xEE70,0x62,0x01},
+{0xEE71,0x48,0x01},
+{0xEE72,0x83,0x01},
+{0xEE73,0x1A,0x01},
+{0xEE74,0xE4,0x01},
+{0xEE75,0x28,0x01},
+{0xEE76,0x06,0x01},
+{0xEE77,0x35,0x01},
+{0xEE78,0x6A,0x01},
+{0xEE79,0xF9,0x01},
+{0xEE7A,0x4B,0x01},
+{0xEE7B,0x53,0x01},
+{0xEE7C,0xB8,0x01},
+{0xEE7D,0x92,0x01},
+{0xEE7E,0x13,0x01},
+{0xEE7F,0xA2,0x01},
+{0xEE80,0xCC,0x01},
+{0xEE81,0x64,0x01},
+{0xEE82,0x27,0x01},
+{0xEE83,0x3B,0x01},
+{0xEE84,0x29,0x01},
+{0xEE85,0x0A,0x01},
+{0xEE86,0x54,0x01},
+{0xEE87,0xBC,0x01},
+{0xEE88,0xF2,0x01},
+{0xEE89,0x96,0x01},
+{0xEE8A,0xC1,0x01},
+{0xEE8B,0x40,0x01},
+{0xEE8C,0xA6,0x01},
+{0xEE8D,0x35,0x01},
+{0xEE8E,0x7A,0x01},
+{0xEE8F,0xB1,0x01},
+{0xEE90,0x8C,0x01},
+{0xEE91,0x54,0x01},
+{0xEE92,0xC8,0x01},
+{0xEE93,0xF2,0x01},
+{0xEE94,0x92,0x01},
+{0xEE95,0x9D,0x01},
+{0xEE96,0x64,0x01},
+{0xEE97,0xE4,0x01},
+{0xEE98,0x23,0x01},
+{0xEE99,0x13,0x01},
+{0xEE9A,0xA9,0x01},
+{0xEE9B,0x48,0x01},
+{0xEE9C,0x47,0x01},
+{0xEE9D,0x40,0x01},
+{0xEE9E,0x42,0x01},
+{0xEE9F,0x13,0x01},
+{0xEEA0,0x9F,0x01},
+{0xEEA1,0x58,0x01},
+{0xEEA2,0xE5,0x01},
+{0xEEA3,0x2C,0x01},
+{0xEEA4,0x7F,0x01},
+{0xEEA5,0xD9,0x01},
+{0xEEA6,0x8C,0x01},
+{0xEEA7,0x5B,0x01},
+{0xEEA8,0x12,0x01},
+{0xEEA9,0x43,0x01},
+{0xEEAA,0x14,0x01},
+{0xEEAB,0xAA,0x01},
+{0xEEAC,0x80,0x01},
+{0xEEAD,0x04,0x01},
+{0xEEAE,0x25,0x01},
+{0xEEAF,0x06,0x01},
+{0xEEB0,0x51,0x01},
+{0xEEB1,0x08,0x01},
+{0xEEB2,0x40,0x01},
+{0xEEB3,0x00,0x01},
+{0xEEB4,0xB2,0x01},
+{0xEEB5,0x10,0x01},
+{0xEEB6,0x86,0x01},
+{0xEEB7,0x98,0x01},
+{0xEEB8,0x64,0x01},
+{0xEEB9,0x25,0x01},
+{0xEEBA,0x4A,0x01},
+{0xEEBB,0xB9,0x01},
+{0xEEBC,0x0A,0x01},
+{0xEEBD,0x5D,0x01},
+{0xEEBE,0x1C,0x01},
+{0xEEBF,0x13,0x01},
+{0xEEC0,0x97,0x01},
+{0xEEC1,0xC4,0x01},
+{0xEEC2,0x18,0x01},
+{0xEEC3,0x85,0x01},
+{0xEEC4,0x2A,0x01},
+{0xEEC5,0x21,0x01},
+{0xEEC6,0x41,0x01},
+{0xEEC7,0xC9,0x01},
+{0xEEC8,0x41,0x01},
+{0xEEC9,0x12,0x01},
+{0xEECA,0x02,0x01},
+{0xEECB,0x10,0x01},
+{0xEECC,0x80,0x01},
+{0xEECD,0x2C,0x01},
+{0xEECE,0x64,0x01},
+{0xEECF,0x21,0x01},
+{0xEED0,0x27,0x01},
+{0xEED1,0x61,0x01},
+{0xEED2,0xC9,0x01},
+{0xEED3,0x52,0x01},
+{0xEED4,0xB0,0x01},
+{0xEED5,0x42,0x01},
+{0xEED6,0x17,0x01},
+{0xEED7,0xC8,0x01},
+{0xEED8,0x04,0x01},
+{0xEED9,0xE6,0x01},
+{0xEEDA,0x32,0x01},
+{0xEEDB,0x58,0x01},
+{0xEEDC,0x29,0x01},
+{0xEEDD,0xCB,0x01},
+{0xEEDE,0x4C,0x01},
+{0xEEDF,0x74,0x01},
+{0xEEE0,0x92,0x01},
+{0xEEE1,0x91,0x01},
+{0xEEE2,0x8E,0x01},
+{0xEEE3,0x48,0x01},
+{0xEEE4,0x84,0x01},
+{0xEEE5,0x22,0x01},
+{0xEEE6,0x1D,0x01},
+{0xEEE7,0x01,0x01},
+{0xEEE8,0xC9,0x01},
+{0xEEE9,0x4D,0x01},
+{0xEEEA,0x7E,0x01},
+{0xEEEB,0x82,0x01},
+{0xEEEC,0x15,0x01},
+{0xEEED,0xB5,0x01},
+{0xEEEE,0x04,0x01},
+{0xEEEF,0xE6,0x01},
+{0xEEF0,0x33,0x01},
+{0xEEF1,0x99,0x01},
+{0xEEF2,0x69,0x01},
+{0xEEF3,0x0D,0x01},
+{0xEEF4,0x5D,0x01},
+{0xEEF5,0x06,0x01},
+{0xEEF6,0x33,0x01},
+{0xEEF7,0x15,0x01},
+{0xEEF8,0xAF,0x01},
+{0xEEF9,0xEC,0x01},
+{0xEEFA,0xA4,0x01},
+{0xEEFB,0x28,0x01},
+{0xEEFC,0x35,0x01},
+{0xEEFD,0xE9,0x01},
+{0xEEFE,0x09,0x01},
+{0xEEFF,0x4F,0x01},
+{0xEF00,0x8E,0x01},
+{0xEF01,0x02,0x01},
+{0xEF02,0x95,0x01},
+{0xEF03,0xB1,0x01},
+{0xEF04,0xC4,0x01},
+{0xEF05,0x25,0x01},
+{0xEF06,0x31,0x01},
+{0xEF07,0x94,0x01},
+{0xEF08,0xB1,0x01},
+{0xEF09,0x4D,0x01},
+{0xEF0A,0x6C,0x01},
+{0xEF0B,0x94,0x01},
+{0xEF0C,0x43,0x01},
+{0xEF0D,0x99,0x01},
+{0xEF0E,0xD4,0x01},
+{0xEF0F,0xEC,0x01},
+{0xEF10,0xC5,0x01},
+{0xEF11,0x31,0x01},
+{0xEF12,0x69,0x01},
+{0xEF13,0xC9,0x01},
+{0xEF14,0x0B,0x01},
+{0xEF15,0x58,0x01},
+{0xEF16,0xE6,0x01},
+{0xEF17,0x52,0x01},
+{0xEF18,0x16,0x01},
+{0xEF19,0xBE,0x01},
+{0xEF1A,0xD4,0x01},
+{0xEF1B,0x45,0x01},
+{0xEF1C,0x32,0x01},
+{0xEF1D,0x8E,0x01},
+{0xEF1E,0x79,0x01},
+{0xEF1F,0x4D,0x01},
+{0xEF20,0x6A,0x01},
+{0xEF21,0xA4,0x01},
+{0xEF22,0x83,0x01},
+{0xEF23,0x1C,0x01},
+{0xEF24,0xF2,0x01},
+{0xEF25,0xDC,0x01},
+{0xEF26,0x26,0x01},
+{0xEF27,0x3A,0x01},
+{0xEF28,0xA3,0x01},
+{0xEF29,0xE1,0x01},
+{0xEF2A,0x4D,0x01},
+{0xEF2B,0x65,0x01},
+{0xEF2C,0x5C,0x01},
+{0xEF2D,0xC3,0x01},
+{0xEF2E,0x98,0x01},
+{0xEF2F,0xD4,0x01},
+{0xEF30,0x3C,0x01},
+{0xEF31,0xE6,0x01},
+{0xEF32,0x35,0x01},
+{0xEF33,0x9D,0x01},
+{0xEF34,0x09,0x01},
+{0xEF35,0x8E,0x01},
+{0xEF36,0x6B,0x01},
+{0xEF37,0xAC,0x01},
+{0xEF38,0xE3,0x01},
+{0xEF39,0x9B,0x01},
+{0xEF3A,0xF4,0x01},
+{0xEF3B,0x34,0x01},
+{0xEF3C,0x07,0x01},
+{0xEF3D,0x3E,0x01},
+{0xEF3E,0xDA,0x01},
+{0xEF3F,0xC1,0x01},
+{0xEF40,0x8F,0x01},
+{0xEF41,0x74,0x01},
+{0xEF42,0xEA,0x01},
+{0xEF43,0x13,0x01},
+{0xEF44,0x9C,0x01},
+{0xEF45,0xF4,0x01},
+{0xEF46,0xF0,0x01},
+{0xEF47,0xA6,0x01},
+{0xEF48,0x3C,0x01},
+{0xEF49,0xC0,0x01},
+{0xEF4A,0x49,0x01},
+{0xEF4B,0x0F,0x01},
+{0xEF4C,0x72,0x01},
+{0xEF4D,0xEA,0x01},
+{0xEF4E,0xD3,0x01},
+{0xEF4F,0x9C,0x01},
+{0xEF50,0xFE,0x01},
+{0xEF51,0x04,0x01},
+{0xEF52,0xA7,0x01},
+{0xEF53,0x3D,0x01},
+
+//SHD2 CW+TL84 33:66
+
+{0xED00,0x9191,0x02},//
+{0xEF54,0x21,0x01},
+{0xEF55,0x92,0x01},
+{0xEF56,0xD1,0x01},
+{0xEF57,0x8A,0x01},
+{0xEF58,0x3E,0x01},
+{0xEF59,0xF4,0x01},
+{0xEF5A,0xA1,0x01},
+{0xEF5B,0x10,0x01},
+{0xEF5C,0xB9,0x01},
+{0xEF5D,0x48,0x01},
+{0xEF5E,0x46,0x01},
+{0xEF5F,0x1F,0x01},
+{0xEF60,0x82,0x01},
+{0xEF61,0x10,0x01},
+{0xEF62,0x7E,0x01},
+{0xEF63,0xBC,0x01},
+{0xEF64,0xC3,0x01},
+{0xEF65,0x1C,0x01},
+{0xEF66,0xE3,0x01},
+{0xEF67,0x38,0x01},
+{0xEF68,0xC7,0x01},
+{0xEF69,0x3B,0x01},
+{0xEF6A,0xF7,0x01},
+{0xEF6B,0x71,0x01},
+{0xEF6C,0x90,0x01},
+{0xEF6D,0x7B,0x01},
+{0xEF6E,0x8E,0x01},
+{0xEF6F,0x53,0x01},
+{0xEF70,0x1A,0x01},
+{0xEF71,0xC5,0x01},
+{0xEF72,0x04,0x01},
+{0xEF73,0x46,0x01},
+{0xEF74,0x31,0x01},
+{0xEF75,0xA2,0x01},
+{0xEF76,0x39,0x01},
+{0xEF77,0x0E,0x01},
+{0xEF78,0x7E,0x01},
+{0xEF79,0x9A,0x01},
+{0xEF7A,0xA3,0x01},
+{0xEF7B,0x99,0x01},
+{0xEF7C,0xB5,0x01},
+{0xEF7D,0x34,0x01},
+{0xEF7E,0x85,0x01},
+{0xEF7F,0x28,0x01},
+{0xEF80,0x4D,0x01},
+{0xEF81,0x61,0x01},
+{0xEF82,0x8B,0x01},
+{0xEF83,0x67,0x01},
+{0xEF84,0xB0,0x01},
+{0xEF85,0x53,0x01},
+{0xEF86,0x1B,0x01},
+{0xEF87,0xBB,0x01},
+{0xEF88,0x08,0x01},
+{0xEF89,0x45,0x01},
+{0xEF8A,0x24,0x01},
+{0xEF8B,0x17,0x01},
+{0xEF8C,0x11,0x01},
+{0xEF8D,0x09,0x01},
+{0xEF8E,0x51,0x01},
+{0xEF8F,0xF2,0x01},
+{0xEF90,0xA2,0x01},
+{0xEF91,0x9B,0x01},
+{0xEF92,0xD3,0x01},
+{0xEF93,0x90,0x01},
+{0xEF94,0xC5,0x01},
+{0xEF95,0x25,0x01},
+{0xEF96,0x0A,0x01},
+{0xEF97,0x01,0x01},
+{0xEF98,0x48,0x01},
+{0xEF99,0x43,0x01},
+{0xEF9A,0x62,0x01},
+{0xEF9B,0x52,0x01},
+{0xEF9C,0x16,0x01},
+{0xEF9D,0xD5,0x01},
+{0xEF9E,0x9C,0x01},
+{0xEF9F,0xC6,0x01},
+{0xEFA0,0x2C,0x01},
+{0xEFA1,0x2F,0x01},
+{0xEFA2,0x51,0x01},
+{0xEFA3,0x48,0x01},
+{0xEFA4,0x40,0x01},
+{0xEFA5,0x1C,0x01},
+{0xEFA6,0x22,0x01},
+{0xEFA7,0x93,0x01},
+{0xEFA8,0xB3,0x01},
+{0xEFA9,0xB8,0x01},
+{0xEFAA,0x46,0x01},
+{0xEFAB,0x37,0x01},
+{0xEFAC,0x7A,0x01},
+{0xEFAD,0x21,0x01},
+{0xEFAE,0x4A,0x01},
+{0xEFAF,0x48,0x01},
+{0xEFB0,0x30,0x01},
+{0xEFB1,0x52,0x01},
+{0xEFB2,0x12,0x01},
+{0xEFB3,0xA4,0x01},
+{0xEFB4,0xF0,0x01},
+{0xEFB5,0xE5,0x01},
+{0xEFB6,0x37,0x01},
+{0xEFB7,0xD6,0x01},
+{0xEFB8,0xF9,0x01},
+{0xEFB9,0x8C,0x01},
+{0xEFBA,0x5B,0x01},
+{0xEFBB,0x9E,0x01},
+{0xEFBC,0x62,0x01},
+{0xEFBD,0x14,0x01},
+{0xEFBE,0xA9,0x01},
+{0xEFBF,0xC8,0x01},
+{0xEFC0,0xA5,0x01},
+{0xEFC1,0x34,0x01},
+{0xEFC2,0xE0,0x01},
+{0xEFC3,0xD1,0x01},
+{0xEFC4,0x8F,0x01},
+{0xEFC5,0x73,0x01},
+{0xEFC6,0x4C,0x01},
+{0xEFC7,0xE3,0x01},
+{0xEFC8,0x18,0x01},
+{0xEFC9,0xC2,0x01},
+{0xEFCA,0x3C,0x01},
+{0xEFCB,0x46,0x01},
+{0xEFCC,0x35,0x01},
+{0xEFCD,0xD2,0x01},
+{0xEFCE,0x09,0x01},
+{0xEFCF,0x90,0x01},
+{0xEFD0,0x85,0x01},
+{0xEFD1,0xF6,0x01},
+{0xEFD2,0x03,0x01},
+{0xEFD3,0x1E,0x01},
+{0xEFD4,0xE7,0x01},
+{0xEFD5,0x20,0x01},
+{0xEFD6,0x27,0x01},
+{0xEFD7,0x3A,0x01},
+{0xEFD8,0xE4,0x01},
+{0xEFD9,0x01,0x01},
+{0xEFDA,0x90,0x01},
+{0xEFDB,0x87,0x01},
+{0xEFDC,0x30,0x01},
+{0xEFDD,0x04,0x01},
+{0xEFDE,0x22,0x01},
+{0xEFDF,0x0B,0x01},
+{0xEFE0,0x2D,0x01},
+{0xEFE1,0x28,0x01},
+{0xEFE2,0x41,0x01},
+{0xEFE3,0x10,0x01},
+{0xEFE4,0xDA,0x01},
+{0xEFE5,0x90,0x01},
+{0xEFE6,0x88,0x01},
+{0xEFE7,0x3C,0x01},
+{0xEFE8,0x04,0x01},
+{0xEFE9,0x00,0x01},
+{0xEFEA,0x00,0x01},
+{0xEFEB,0x00,0x01},
+{0xEFEC,0x00,0x01},
+{0xEFED,0x00,0x01},
+
+
+
+//SHD3 D65+TL84 C01//
+{0xED00,0x9191,0x02},//
+{0xEFEE,0x12,0x01},
+{0xEFEF,0x42,0x01},
+{0xEFF0,0x51,0x01},
+{0xEFF1,0x89,0x01},
+{0xEFF2,0x38,0x01},
+{0xEFF3,0xD4,0x01},
+{0xEFF4,0x21,0x01},
+{0xEFF5,0x10,0x01},
+{0xEFF6,0xAD,0x01},
+{0xEFF7,0xA8,0x01},
+{0xEFF8,0x45,0x01},
+{0xEFF9,0x18,0x01},
+{0xEFFA,0x4A,0x01},
+{0xEFFB,0x50,0x01},
+{0xEFFC,0x7D,0x01},
+{0xEFFD,0xBA,0x01},
+{0xEFFE,0xD3,0x01},
+{0xEFFF,0x1C,0x01},
+{0xF000,0xE4,0x01},
+{0xF001,0x40,0x01},
+{0xF002,0x27,0x01},
+{0xF003,0x3C,0x01},
+{0xF004,0xF8,0x01},
+{0xF005,0x69,0x01},
+{0xF006,0x10,0x01},
+{0xF007,0x7B,0x01},
+{0xF008,0x8E,0x01},
+{0xF009,0x63,0x01},
+{0xF00A,0x1A,0x01},
+{0xF00B,0xC6,0x01},
+{0xF00C,0x10,0x01},
+{0xF00D,0xA6,0x01},
+{0xF00E,0x31,0x01},
+{0xF00F,0xA6,0x01},
+{0xF010,0x59,0x01},
+{0xF011,0x8E,0x01},
+{0xF012,0x7E,0x01},
+{0xF013,0x9A,0x01},
+{0xF014,0xB3,0x01},
+{0xF015,0x19,0x01},
+{0xF016,0xB6,0x01},
+{0xF017,0x38,0x01},
+{0xF018,0xA5,0x01},
+{0xF019,0x28,0x01},
+{0xF01A,0x4F,0x01},
+{0xF01B,0x79,0x01},
+{0xF01C,0xCB,0x01},
+{0xF01D,0x68,0x01},
+{0xF01E,0xBA,0x01},
+{0xF01F,0x53,0x01},
+{0xF020,0x9B,0x01},
+{0xF021,0xBB,0x01},
+{0xF022,0x0C,0x01},
+{0xF023,0x65,0x01},
+{0xF024,0x24,0x01},
+{0xF025,0x17,0x01},
+{0xF026,0x21,0x01},
+{0xF027,0xC9,0x01},
+{0xF028,0x51,0x01},
+{0xF029,0xFC,0x01},
+{0xF02A,0xF2,0x01},
+{0xF02B,0x9B,0x01},
+{0xF02C,0xD3,0x01},
+{0xF02D,0x94,0x01},
+{0xF02E,0xC5,0x01},
+{0xF02F,0x25,0x01},
+{0xF030,0x0A,0x01},
+{0xF031,0x01,0x01},
+{0xF032,0x48,0x01},
+{0xF033,0x43,0x01},
+{0xF034,0x66,0x01},
+{0xF035,0x92,0x01},
+{0xF036,0x96,0x01},
+{0xF037,0xD7,0x01},
+{0xF038,0xA0,0x01},
+{0xF039,0xE6,0x01},
+{0xF03A,0x2C,0x01},
+{0xF03B,0x2F,0x01},
+{0xF03C,0x51,0x01},
+{0xF03D,0x48,0x01},
+{0xF03E,0x40,0x01},
+{0xF03F,0x1E,0x01},
+{0xF040,0x42,0x01},
+{0xF041,0x93,0x01},
+{0xF042,0xB5,0x01},
+{0xF043,0xCC,0x01},
+{0xF044,0x46,0x01},
+{0xF045,0x37,0x01},
+{0xF046,0x7C,0x01},
+{0xF047,0x29,0x01},
+{0xF048,0x8A,0x01},
+{0xF049,0x48,0x01},
+{0xF04A,0x32,0x01},
+{0xF04B,0x72,0x01},
+{0xF04C,0x12,0x01},
+{0xF04D,0xA5,0x01},
+{0xF04E,0x00,0x01},
+{0xF04F,0xA6,0x01},
+{0xF050,0x38,0x01},
+{0xF051,0xD7,0x01},
+{0xF052,0x01,0x01},
+{0xF053,0x0D,0x01},
+{0xF054,0x5C,0x01},
+{0xF055,0xA2,0x01},
+{0xF056,0x82,0x01},
+{0xF057,0x94,0x01},
+{0xF058,0xAA,0x01},
+{0xF059,0xD8,0x01},
+{0xF05A,0x45,0x01},
+{0xF05B,0x35,0x01},
+{0xF05C,0xE5,0x01},
+{0xF05D,0xC9,0x01},
+{0xF05E,0xCF,0x01},
+{0xF05F,0x73,0x01},
+{0xF060,0x50,0x01},
+{0xF061,0x03,0x01},
+{0xF062,0x99,0x01},
+{0xF063,0xC3,0x01},
+{0xF064,0x4C,0x01},
+{0xF065,0xE6,0x01},
+{0xF066,0x35,0x01},
+{0xF067,0xD7,0x01},
+{0xF068,0x21,0x01},
+{0xF069,0x10,0x01},
+{0xF06A,0x84,0x01},
+{0xF06B,0xF2,0x01},
+{0xF06C,0x03,0x01},
+{0xF06D,0x9E,0x01},
+{0xF06E,0xE8,0x01},
+{0xF06F,0x2C,0x01},
+{0xF070,0xA7,0x01},
+{0xF071,0x3A,0x01},
+{0xF072,0xE8,0x01},
+{0xF073,0x11,0x01},
+{0xF074,0x90,0x01},
+{0xF075,0x87,0x01},
+{0xF076,0x18,0x01},
+{0xF077,0x94,0x01},
+{0xF078,0x21,0x01},
+{0xF079,0x09,0x01},
+{0xF07A,0x2D,0x01},
+{0xF07B,0x68,0x01},
+{0xF07C,0x41,0x01},
+{0xF07D,0x11,0x01},
+{0xF07E,0xDA,0x01},
+{0xF07F,0x10,0x01},
+{0xF080,0x88,0x01},
+{0xF081,0x2A,0x01},
+{0xF082,0x04,0x01},
+{0xF083,0x00,0x01},
+{0xF084,0x00,0x01},
+{0xF085,0x00,0x01},
+{0xF086,0x00,0x01},
+{0xF087,0x00,0x01},
+{0xF088,0xBE,0x01},
+{0xF089,0x51,0x01},
+{0xF08A,0x4E,0x01},
+{0xF08B,0x6F,0x01},
+{0xF08C,0x6C,0x01},
+{0xF08D,0x43,0x01},
+{0xF08E,0x1B,0x01},
+{0xF08F,0xDA,0x01},
+{0xF090,0xEC,0x01},
+{0xF091,0x46,0x01},
+{0xF092,0x38,0x01},
+{0xF093,0xBB,0x01},
+{0xF094,0xC1,0x01},
+{0xF095,0xCD,0x01},
+{0xF096,0x69,0x01},
+{0xF097,0x26,0x01},
+{0xF098,0x93,0x01},
+{0xF099,0x98,0x01},
+{0xF09A,0xC1,0x01},
+{0xF09B,0x20,0x01},
+{0xF09C,0x26,0x01},
+{0xF09D,0x32,0x01},
+{0xF09E,0xA5,0x01},
+{0xF09F,0xB1,0x01},
+{0xF0A0,0x8D,0x01},
+{0xF0A1,0x67,0x01},
+{0xF0A2,0x0E,0x01},
+{0xF0A3,0x23,0x01},
+{0xF0A4,0x97,0x01},
+{0xF0A5,0xB0,0x01},
+{0xF0A6,0x6C,0x01},
+{0xF0A7,0x25,0x01},
+{0xF0A8,0x2C,0x01},
+{0xF0A9,0x71,0x01},
+{0xF0AA,0x41,0x01},
+{0xF0AB,0x0C,0x01},
+{0xF0AC,0x69,0x01},
+{0xF0AD,0x14,0x01},
+{0xF0AE,0xB3,0x01},
+{0xF0AF,0x96,0x01},
+{0xF0B0,0xA6,0x01},
+{0xF0B1,0xE8,0x01},
+{0xF0B2,0x64,0x01},
+{0xF0B3,0x26,0x01},
+{0xF0B4,0x3A,0x01},
+{0xF0B5,0x79,0x01},
+{0xF0B6,0x4A,0x01},
+{0xF0B7,0x5B,0x01},
+{0xF0B8,0x18,0x01},
+{0xF0B9,0xA3,0x01},
+{0xF0BA,0x97,0x01},
+{0xF0BB,0xA9,0x01},
+{0xF0BC,0xBC,0x01},
+{0xF0BD,0x24,0x01},
+{0xF0BE,0x23,0x01},
+{0xF0BF,0x13,0x01},
+{0xF0C0,0xE1,0x01},
+{0xF0C1,0xC8,0x01},
+{0xF0C2,0x4C,0x01},
+{0xF0C3,0xAA,0x01},
+{0xF0C4,0xA2,0x01},
+{0xF0C5,0x97,0x01},
+{0xF0C6,0xB6,0x01},
+{0xF0C7,0x14,0x01},
+{0xF0C8,0x05,0x01},
+{0xF0C9,0x24,0x01},
+{0xF0CA,0x06,0x01},
+{0xF0CB,0x09,0x01},
+{0xF0CC,0xC8,0x01},
+{0xF0CD,0x42,0x01},
+{0xF0CE,0x48,0x01},
+{0xF0CF,0x82,0x01},
+{0xF0D0,0x14,0x01},
+{0xF0D1,0xB8,0x01},
+{0xF0D2,0xC0,0x01},
+{0xF0D3,0xE5,0x01},
+{0xF0D4,0x28,0x01},
+{0xF0D5,0x21,0x01},
+{0xF0D6,0x39,0x01},
+{0xF0D7,0x08,0x01},
+{0xF0D8,0x40,0x01},
+{0xF0D9,0x14,0x01},
+{0xF0DA,0x62,0x01},
+{0xF0DB,0x92,0x01},
+{0xF0DC,0xA4,0x01},
+{0xF0DD,0xC4,0x01},
+{0xF0DE,0x05,0x01},
+{0xF0DF,0x30,0x01},
+{0xF0E0,0x58,0x01},
+{0xF0E1,0xA1,0x01},
+{0xF0E2,0x49,0x01},
+{0xF0E3,0x46,0x01},
+{0xF0E4,0x22,0x01},
+{0xF0E5,0xB2,0x01},
+{0xF0E6,0x91,0x01},
+{0xF0E7,0x9A,0x01},
+{0xF0E8,0x58,0x01},
+{0xF0E9,0xA5,0x01},
+{0xF0EA,0x2F,0x01},
+{0xF0EB,0x96,0x01},
+{0xF0EC,0x99,0x01},
+{0xF0ED,0x8B,0x01},
+{0xF0EE,0x54,0x01},
+{0xF0EF,0x74,0x01},
+{0xF0F0,0x32,0x01},
+{0xF0F1,0x13,0x01},
+{0xF0F2,0x9D,0x01},
+{0xF0F3,0x38,0x01},
+{0xF0F4,0xC5,0x01},
+{0xF0F5,0x2D,0x01},
+{0xF0F6,0x90,0x01},
+{0xF0F7,0x59,0x01},
+{0xF0F8,0x4D,0x01},
+{0xF0F9,0x64,0x01},
+{0xF0FA,0xEE,0x01},
+{0xF0FB,0x62,0x01},
+{0xF0FC,0x16,0x01},
+{0xF0FD,0xAE,0x01},
+{0xF0FE,0x84,0x01},
+{0xF0FF,0x25,0x01},
+{0xF100,0x2E,0x01},
+{0xF101,0x8B,0x01},
+{0xF102,0x31,0x01},
+{0xF103,0xCD,0x01},
+{0xF104,0x6F,0x01},
+{0xF105,0x60,0x01},
+{0xF106,0xC3,0x01},
+{0xF107,0x19,0x01},
+{0xF108,0xC7,0x01},
+{0xF109,0x14,0x01},
+{0xF10A,0x26,0x01},
+{0xF10B,0x31,0x01},
+{0xF10C,0x97,0x01},
+{0xF10D,0x41,0x01},
+{0xF10E,0x8D,0x01},
+{0xF10F,0x6D,0x01},
+{0xF110,0x86,0x01},
+{0xF111,0xE3,0x01},
+{0xF112,0x9C,0x01},
+{0xF113,0xE2,0x01},
+{0xF114,0xD8,0x01},
+{0xF115,0x06,0x01},
+{0xF116,0x36,0x01},
+{0xF117,0xB5,0x01},
+{0xF118,0xE9,0x01},
+{0xF119,0x4D,0x01},
+{0xF11A,0x70,0x01},
+{0xF11B,0x68,0x01},
+{0xF11C,0x03,0x01},
+{0xF11D,0x00,0x01},
+{0xF11E,0x00,0x01},
+{0xF11F,0x00,0x01},
+{0xF120,0x00,0x01},
+{0xF121,0x00,0x01},
+
+
+//SHD TH
+{0x6C32,0x1964,0x02},    // SHD_INP_TH_HB_H_R2
+{0x6C34,0x18CE,0x02},    // SHD_INP_TH_HB_L_R2
+{0x6C36,0x10CC,0x02},    // SHD_INP_TH_LB_H_R2
+{0x6C38,0x1004,0x02},    // SHD_INP_TH_LB_L_R2
+{0x6C3C,0x10CC,0x02},    // SHD_INP_TH_HB_H_RB
+{0x6C3E,0x1004,0x02},    // SHD_INP_TH_HB_L_RB
+{0x6C40,0x0000,0x02},    // SHD_INP_TH_LB_H_RB
+{0x6C42,0x0000,0x02},    // SHD_INP_TH_LB_L_RB
+
+//PreWB_offset (for SHD2)
+{0x6828,0x0013,0x02},    // SHD_PRER_OFFSET_R2 :
+//PreWB_offset (for SHD3)
+{0x682C,0x000C,0x02},    // SHD_PRER_OFFSET_RB :
+{0x6830,0xFFFF,0x02},    // SHD_PREB_OFFSET_RB :
+
+// CXC/SHD EN
+{0x01BC,0x57,0x01},    // CXC ON SHD ON INP ON GAIN OFF
+};
+
+static const isx012_regset_t ISX012_Shading_1[] =
+{
+{0x01BC,0x50,0x01},    // CXC OFF SHD OFF
+{0xEB00,0x8282,0x02},	//valid_code
+{0xEB02,0xFE,0x01},
+{0xEB03,0x84,0x01},
+{0xEB04,0x3F,0x01},
+{0xEB05,0x01,0x01},
+{0xEB06,0x50,0x01},
+{0xEB07,0x08,0x01},
+{0xEB08,0x14,0x01},
+{0xEB09,0xFF,0x01},
+{0xEB0A,0x45,0x01},
+{0xEB0B,0x80,0x01},
+{0xEB0C,0x01,0x01},
+{0xEB0D,0x68,0x01},
+{0xEB0E,0x04,0x01},
+{0xEB0F,0x1A,0x01},
+{0xEB10,0x81,0x01},
+{0xEB11,0x86,0x01},
+{0xEB12,0x3F,0x01},
+{0xEB13,0xE1,0x01},
+{0xEB14,0x4F,0x01},
+{0xEB15,0x00,0x01},
+{0xEB16,0x14,0x01},
+{0xEB17,0x02,0x01},
+{0xEB18,0xC5,0x01},
+{0xEB19,0x7F,0x01},
+{0xEB1A,0x11,0x01},
+{0xEB1B,0x60,0x01},
+{0xEB1C,0x00,0x01},
+{0xEB1D,0x1A,0x01},
+{0xEB1E,0x81,0x01},
+{0xEB1F,0x46,0x01},
+{0xEB20,0xA0,0x01},
+{0xEB21,0x01,0x01},
+{0xEB22,0x48,0x01},
+{0xEB23,0x00,0x01},
+{0xEB24,0x12,0x01},
+{0xEB25,0x81,0x01},
+{0xEB26,0x05,0x01},
+{0xEB27,0x20,0x01},
+{0xEB28,0xF1,0x01},
+{0xEB29,0x4F,0x01},
+{0xEB2A,0x00,0x01},
+{0xEB2B,0x14,0x01},
+{0xEB2C,0x82,0x01},
+{0xEB2D,0x85,0x01},
+{0xEB2E,0x80,0x01},
+{0xEB2F,0x21,0x01},
+{0xEB30,0x60,0x01},
+{0xEB31,0x04,0x01},
+{0xEB32,0x12,0x01},
+{0xEB33,0x81,0x01},
+{0xEB34,0x84,0x01},
+{0xEB35,0xE0,0x01},
+{0xEB36,0x00,0x01},
+{0xEB37,0x28,0x01},
+{0xEB38,0x04,0x01},
+{0xEB39,0x0C,0x01},
+{0xEB3A,0x82,0x01},
+{0xEB3B,0x43,0x01},
+{0xEB3C,0x20,0x01},
+{0xEB3D,0x11,0x01},
+{0xEB3E,0x68,0x01},
+{0xEB3F,0x04,0x01},
+{0xEB40,0x1A,0x01},
+{0xEB41,0x82,0x01},
+{0xEB42,0x83,0x01},
+{0xEB43,0xE0,0x01},
+{0xEB44,0x00,0x01},
+{0xEB45,0x20,0x01},
+{0xEB46,0x00,0x01},
+{0xEB47,0x06,0x01},
+{0xEB48,0xFF,0x01},
+{0xEB49,0x41,0x01},
+{0xEB4A,0x80,0x01},
+{0xEB4B,0x10,0x01},
+{0xEB4C,0x30,0x01},
+{0xEB4D,0x08,0x01},
+{0xEB4E,0x14,0x01},
+{0xEB4F,0x02,0x01},
+{0xEB50,0x45,0x01},
+{0xEB51,0xC0,0x01},
+{0xEB52,0x10,0x01},
+{0xEB53,0x30,0x01},
+{0xEB54,0x04,0x01},
+{0xEB55,0x04,0x01},
+{0xEB56,0x01,0x01},
+{0xEB57,0xC0,0x01},
+{0xEB58,0x3F,0x01},
+{0xEB59,0x10,0x01},
+{0xEB5A,0x10,0x01},
+{0xEB5B,0x04,0x01},
+{0xEB5C,0x0A,0x01},
+{0xEB5D,0x80,0x01},
+{0xEB5E,0x03,0x01},
+{0xEB5F,0xE0,0x01},
+{0xEB60,0x10,0x01},
+{0xEB61,0x28,0x01},
+{0xEB62,0x04,0x01},
+{0xEB63,0x0A,0x01},
+{0xEB64,0x81,0x01},
+{0xEB65,0x01,0x01},
+{0xEB66,0x00,0x01},
+{0xEB67,0x10,0x01},
+{0xEB68,0x00,0x01},
+{0xEB69,0x04,0x01},
+{0xEB6A,0x04,0x01},
+{0xEB6B,0x01,0x01},
+{0xEB6C,0x42,0x01},
+{0xEB6D,0xE0,0x01},
+{0xEB6E,0x10,0x01},
+{0xEB6F,0x38,0x01},
+{0xEB70,0xFC,0x01},
+{0xEB71,0x0D,0x01},
+{0xEB72,0x7F,0x01},
+{0xEB73,0x43,0x01},
+{0xEB74,0x60,0x01},
+{0xEB75,0x00,0x01},
+{0xEB76,0x08,0x01},
+{0xEB77,0x08,0x01},
+{0xEB78,0x02,0x01},
+{0xEB79,0x81,0x01},
+{0xEB7A,0x41,0x01},
+{0xEB7B,0x80,0x01},
+{0xEB7C,0x10,0x01},
+{0xEB7D,0x30,0x01},
+{0xEB7E,0x04,0x01},
+{0xEB7F,0x0C,0x01},
+{0xEB80,0x01,0x01},
+{0xEB81,0x43,0x01},
+{0xEB82,0xC0,0x01},
+{0xEB83,0x20,0x01},
+{0xEB84,0x28,0x01},
+{0xEB85,0x08,0x01},
+{0xEB86,0x06,0x01},
+{0xEB87,0x02,0x01},
+{0xEB88,0xC2,0x01},
+{0xEB89,0xA0,0x01},
+{0xEB8A,0x30,0x01},
+{0xEB8B,0x30,0x01},
+{0xEB8C,0x0C,0x01},
+{0xEB8D,0x12,0x01},
+{0xEB8E,0x83,0x01},
+{0xEB8F,0x84,0x01},
+{0xEB90,0x00,0x01},
+{0xEB91,0x21,0x01},
+{0xEB92,0x40,0x01},
+{0xEB93,0x0C,0x01},
+{0xEB94,0x0C,0x01},
+{0xEB95,0x82,0x01},
+{0xEB96,0x03,0x01},
+{0xEB97,0xC1,0x01},
+{0xEB98,0x40,0x01},
+{0xEB99,0x40,0x01},
+{0xEB9A,0x08,0x01},
+{0xEB9B,0x10,0x01},
+{0xEB9C,0x03,0x01},
+{0xEB9D,0xC4,0x01},
+{0xEB9E,0x00,0x01},
+{0xEB9F,0x21,0x01},
+{0xEBA0,0x38,0x01},
+{0xEBA1,0x08,0x01},
+{0xEBA2,0x0E,0x01},
+{0xEBA3,0x82,0x01},
+{0xEBA4,0xC3,0x01},
+{0xEBA5,0x20,0x01},
+{0xEBA6,0x41,0x01},
+{0xEBA7,0x48,0x01},
+{0xEBA8,0x00,0x01},
+{0xEBA9,0x14,0x01},
+{0xEBAA,0x83,0x01},
+{0xEBAB,0x44,0x01},
+{0xEBAC,0x20,0x01},
+{0xEBAD,0x11,0x01},
+{0xEBAE,0x48,0x01},
+{0xEBAF,0x08,0x01},
+{0xEBB0,0x0E,0x01},
+{0xEBB1,0x82,0x01},
+{0xEBB2,0x83,0x01},
+{0xEBB3,0xE0,0x01},
+{0xEBB4,0x30,0x01},
+{0xEBB5,0x48,0x01},
+{0xEBB6,0x10,0x01},
+{0xEBB7,0x12,0x01},
+{0xEBB8,0x00,0x01},
+{0xEBB9,0xC5,0x01},
+{0xEBBA,0x20,0x01},
+{0xEBBB,0x11,0x01},
+{0xEBBC,0x48,0x01},
+{0xEBBD,0x04,0x01},
+{0xEBBE,0x12,0x01},
+{0xEBBF,0x04,0x01},
+{0xEBC0,0x3B,0x01},
+{0xEBC1,0xC1,0x01},
+{0xEBC2,0x1E,0x01},
+{0xEBC3,0xC8,0x01},
+{0xEBC4,0x0F,0x01},
+{0xEBC5,0xF8,0x01},
+{0xEBC6,0x02,0x01},
+{0xEBC7,0xBB,0x01},
+{0xEBC8,0x60,0x01},
+{0xEBC9,0x0F,0x01},
+{0xEBCA,0xB8,0x01},
+{0xEBCB,0x0F,0x01},
+{0xEBCC,0xEA,0x01},
+{0xEBCD,0x83,0x01},
+{0xEBCE,0x3A,0x01},
+{0xEBCF,0xC1,0x01},
+{0xEBD0,0x4E,0x01},
+{0xEBD1,0xB0,0x01},
+{0xEBD2,0x07,0x01},
+{0xEBD3,0xF2,0x01},
+{0xEBD4,0x03,0x01},
+{0xEBD5,0xBE,0x01},
+{0xEBD6,0xC0,0x01},
+{0xEBD7,0x2E,0x01},
+{0xEBD8,0xD8,0x01},
+{0xEBD9,0x03,0x01},
+{0xEBDA,0xEE,0x01},
+{0xEBDB,0x83,0x01},
+{0xEBDC,0xFA,0x01},
+{0xEBDD,0xA0,0x01},
+{0xEBDE,0x2E,0x01},
+{0xEBDF,0xB0,0x01},
+{0xEBE0,0x0B,0x01},
+{0xEBE1,0xEC,0x01},
+{0xEBE2,0x05,0x01},
+{0xEBE3,0xBD,0x01},
+{0xEBE4,0x60,0x01},
+{0xEBE5,0x2F,0x01},
+{0xEBE6,0xD0,0x01},
+{0xEBE7,0x07,0x01},
+{0xEBE8,0xEC,0x01},
+{0xEBE9,0x02,0x01},
+{0xEBEA,0xBC,0x01},
+{0xEBEB,0x40,0x01},
+{0xEBEC,0x2F,0x01},
+{0xEBED,0xD0,0x01},
+{0xEBEE,0x13,0x01},
+{0xEBEF,0xEE,0x01},
+{0xEBF0,0x84,0x01},
+{0xEBF1,0xBB,0x01},
+{0xEBF2,0x00,0x01},
+{0xEBF3,0x1F,0x01},
+{0xEBF4,0xC8,0x01},
+{0xEBF5,0xFF,0x01},
+{0xEBF6,0xEF,0x01},
+{0xEBF7,0x00,0x01},
+{0xEBF8,0x7D,0x01},
+{0xEBF9,0x60,0x01},
+{0xEBFA,0x2F,0x01},
+{0xEBFB,0xD0,0x01},
+{0xEBFC,0x0B,0x01},
+{0xEBFD,0xF4,0x01},
+{0xEBFE,0x85,0x01},
+{0xEBFF,0x7D,0x01},
+{0xEC00,0x61,0x01},
+{0xEC01,0x0F,0x01},
+{0xEC02,0xC0,0x01},
+{0xEC03,0xFF,0x01},
+{0xEC04,0xF7,0x01},
+{0xEC05,0x7F,0x01},
+{0xEC06,0x3D,0x01},
+{0xEC07,0x40,0x01},
+{0xEC08,0xFF,0x01},
+{0xEC09,0xDF,0x01},
+{0xEC0A,0x07,0x01},
+{0xEC0B,0xFA,0x01},
+{0xEC0C,0x81,0x01},
+{0xEC0D,0x3E,0x01},
+{0xEC0E,0x61,0x01},
+{0xEC0F,0x4F,0x01},
+{0xEC10,0xD8,0x01},
+{0xEC11,0x0B,0x01},
+{0xEC12,0xFC,0x01},
+{0xEC13,0xFE,0x01},
+{0xEC14,0x3D,0x01},
+{0xEC15,0xC0,0x01},
+{0xEC16,0xFF,0x01},
+{0xEC17,0xFF,0x01},
+{0xEC18,0x03,0x01},
+{0xEC19,0xFC,0x01},
+{0xEC1A,0x82,0x01},
+{0xEC1B,0xBE,0x01},
+{0xEC1C,0xA0,0x01},
+{0xEC1D,0x6F,0x01},
+{0xEC1E,0xF8,0x01},
+{0xEC1F,0x1B,0x01},
+{0xEC20,0xFE,0x01},
+{0xEC21,0x83,0x01},
+{0xEC22,0xBF,0x01},
+{0xEC23,0xE0,0x01},
+{0xEC24,0x0F,0x01},
+{0xEC25,0x10,0x01},
+{0xEC26,0x00,0x01},
+{0xEC27,0x00,0x01},
+{0xEC28,0x82,0x01},
+{0xEC29,0xC0,0x01},
+{0xEC2A,0x60,0x01},
+{0xEC2B,0x30,0x01},
+{0xEC2C,0x18,0x01},
+{0xEC2D,0x20,0x01},
+{0xEC2E,0x04,0x01},
+{0xEC2F,0x08,0x01},
+{0xEC30,0x81,0x01},
+{0xEC31,0x21,0x01},
+{0xEC32,0x30,0x01},
+{0xEC33,0x08,0x01},
+{0xEC34,0x08,0x01},
+{0xEC35,0x08,0x01},
+{0xEC36,0x82,0x01},
+{0xEC37,0x01,0x01},
+{0xEC38,0x81,0x01},
+{0xEC39,0x50,0x01},
+{0xEC3A,0x08,0x01},
+{0xEC3B,0x14,0x01},
+{0xEC3C,0x02,0x01},
+{0xEC3D,0x09,0x01},
+{0xEC3E,0x41,0x01},
+{0xEC3F,0x42,0x01},
+{0xEC40,0x70,0x01},
+{0xEC41,0x20,0x01},
+{0xEC42,0x0C,0x01},
+{0xEC43,0x06,0x01},
+{0xEC44,0x84,0x01},
+{0xEC45,0x42,0x01},
+{0xEC46,0xE1,0x01},
+{0xEC47,0x40,0x01},
+{0xEC48,0x38,0x01},
+{0xEC49,0x1C,0x01},
+{0xEC4A,0x0C,0x01},
+{0xEC4B,0x07,0x01},
+{0xEC4C,0x03,0x01},
+{0xEC4D,0xA2,0x01},
+{0xEC4E,0x80,0x01},
+{0xEC4F,0x28,0x01},
+{0xEC50,0x18,0x01},
+{0xEC51,0x10,0x01},
+{0xEC52,0x87,0x01},
+{0xEC53,0x43,0x01},
+{0xEC54,0x61,0x01},
+{0xEC55,0x41,0x01},
+{0xEC56,0x48,0x01},
+{0xEC57,0x14,0x01},
+{0xEC58,0x10,0x01},
+{0xEC59,0x07,0x01},
+{0xEC5A,0xC2,0x01},
+{0xEC5B,0x81,0x01},
+{0xEC5C,0x80,0x01},
+{0xEC5D,0x30,0x01},
+{0xEC5E,0x20,0x01},
+{0xEC5F,0x0C,0x01},
+{0xEC60,0x87,0x01},
+{0xEC61,0x83,0x01},
+{0xEC62,0xC1,0x01},
+{0xEC63,0x40,0x01},
+{0xEC64,0x38,0x01},
+{0xEC65,0x14,0x01},
+{0xEC66,0x0A,0x01},
+{0xEC67,0x07,0x01},
+{0xEC68,0xC3,0x01},
+{0xEC69,0xC1,0x01},
+{0xEC6A,0x70,0x01},
+{0xEC6B,0x30,0x01},
+{0xEC6C,0x20,0x01},
+{0xEC6D,0x0C,0x01},
+{0xEC6E,0x08,0x01},
+{0xEC6F,0xC3,0x01},
+{0xEC70,0xE1,0x01},
+{0xEC71,0x60,0x01},
+{0xEC72,0x30,0x01},
+{0xEC73,0x10,0x01},
+{0xEC74,0x0E,0x01},
+{0xEC75,0x85,0x01},
+{0xEC76,0xC2,0x01},
+{0xEC77,0xC1,0x01},
+{0xEC78,0x70,0x01},
+{0xEC79,0x30,0x01},
+{0xEC7A,0x1C,0x01},
+{0xEC7B,0x0C,0x01},
+
+//SHD1(from CO1)
+{0xED02,0xE6,0x01},
+{0xED03,0x61,0x01},
+{0xED04,0x92,0x01},
+{0xED05,0x7C,0x01},
+{0xED06,0xBE,0x01},
+{0xED07,0xB4,0x01},
+{0xED08,0x9E,0x01},
+{0xED09,0x2C,0x01},
+{0xED0A,0x75,0x01},
+{0xED0B,0x47,0x01},
+{0xED0C,0x49,0x01},
+{0xED0D,0xD7,0x01},
+{0xED0E,0x61,0x01},
+{0xED0F,0x12,0x01},
+{0xED10,0x76,0x01},
+{0xED11,0xA8,0x01},
+{0xED12,0x34,0x01},
+{0xED13,0x1E,0x01},
+{0xED14,0x31,0x01},
+{0xED15,0xA1,0x01},
+{0xED16,0xC7,0x01},
+{0xED17,0x4C,0x01},
+{0xED18,0xDE,0x01},
+{0xED19,0xC1,0x01},
+{0xED1A,0xD2,0x01},
+{0xED1B,0x77,0x01},
+{0xED1C,0x76,0x01},
+{0xED1D,0x94,0x01},
+{0xED1E,0x9C,0x01},
+{0xED1F,0x10,0x01},
+{0xED20,0xC9,0x01},
+{0xED21,0xC6,0x01},
+{0xED22,0x40,0x01},
+{0xED23,0xA2,0x01},
+{0xED24,0x99,0x01},
+{0xED25,0x8F,0x01},
+{0xED26,0x66,0x01},
+{0xED27,0xDC,0x01},
+{0xED28,0xF3,0x01},
+{0xED29,0x19,0x01},
+{0xED2A,0xFC,0x01},
+{0xED2B,0xB0,0x01},
+{0xED2C,0xA6,0x01},
+{0xED2D,0x41,0x01},
+{0xED2E,0xC1,0x01},
+{0xED2F,0x49,0x01},
+{0xED30,0x91,0x01},
+{0xED31,0x75,0x01},
+{0xED32,0x8C,0x01},
+{0xED33,0x74,0x01},
+{0xED34,0x1C,0x01},
+{0xED35,0x0B,0x01},
+{0xED36,0x91,0x01},
+{0xED37,0x86,0x01},
+{0xED38,0x3D,0x01},
+{0xED39,0x87,0x01},
+{0xED3A,0x39,0x01},
+{0xED3B,0x4E,0x01},
+{0xED3C,0x5C,0x01},
+{0xED3D,0x50,0x01},
+{0xED3E,0x83,0x01},
+{0xED3F,0x16,0x01},
+{0xED40,0xCF,0x01},
+{0xED41,0xBC,0x01},
+{0xED42,0x45,0x01},
+{0xED43,0x35,0x01},
+{0xED44,0x83,0x01},
+{0xED45,0x41,0x01},
+{0xED46,0xCE,0x01},
+{0xED47,0x67,0x01},
+{0xED48,0xE8,0x01},
+{0xED49,0x33,0x01},
+{0xED4A,0x1C,0x01},
+{0xED4B,0x16,0x01},
+{0xED4C,0xC1,0x01},
+{0xED4D,0x86,0x01},
+{0xED4E,0x3E,0x01},
+{0xED4F,0x83,0x01},
+{0xED50,0xC1,0x01},
+{0xED51,0x0D,0x01},
+{0xED52,0x57,0x01},
+{0xED53,0x02,0x01},
+{0xED54,0x23,0x01},
+{0xED55,0x14,0x01},
+{0xED56,0xAE,0x01},
+{0xED57,0xE4,0x01},
+{0xED58,0x44,0x01},
+{0xED59,0x2A,0x01},
+{0xED5A,0x43,0x01},
+{0xED5B,0xF9,0x01},
+{0xED5C,0xCA,0x01},
+{0xED5D,0x56,0x01},
+{0xED5E,0x0C,0x01},
+{0xED5F,0x03,0x01},
+{0xED60,0x98,0x01},
+{0xED61,0xE2,0x01},
+{0xED62,0xA8,0x01},
+{0xED63,0x26,0x01},
+{0xED64,0x41,0x01},
+{0xED65,0x9E,0x01},
+{0xED66,0xC1,0x01},
+{0xED67,0xCE,0x01},
+{0xED68,0x59,0x01},
+{0xED69,0x1C,0x01},
+{0xED6A,0xB3,0x01},
+{0xED6B,0x93,0x01},
+{0xED6C,0xA7,0x01},
+{0xED6D,0x74,0x01},
+{0xED6E,0x04,0x01},
+{0xED6F,0x25,0x01},
+{0xED70,0x13,0x01},
+{0xED71,0xD9,0x01},
+{0xED72,0xC8,0x01},
+{0xED73,0x47,0x01},
+{0xED74,0x54,0x01},
+{0xED75,0xD2,0x01},
+{0xED76,0x93,0x01},
+{0xED77,0xAA,0x01},
+{0xED78,0x98,0x01},
+{0xED79,0xE5,0x01},
+{0xED7A,0x32,0x01},
+{0xED7B,0x9A,0x01},
+{0xED7C,0x29,0x01},
+{0xED7D,0xCF,0x01},
+{0xED7E,0x64,0x01},
+{0xED7F,0x8E,0x01},
+{0xED80,0x73,0x01},
+{0xED81,0x95,0x01},
+{0xED82,0xBB,0x01},
+{0xED83,0xA4,0x01},
+{0xED84,0xA4,0x01},
+{0xED85,0x26,0x01},
+{0xED86,0x0A,0x01},
+{0xED87,0x59,0x01},
+{0xED88,0x08,0x01},
+{0xED89,0x40,0x01},
+{0xED8A,0x00,0x01},
+{0xED8B,0xC2,0x01},
+{0xED8C,0x10,0x01},
+{0xED8D,0x88,0x01},
+{0xED8E,0xB0,0x01},
+{0xED8F,0x84,0x01},
+{0xED90,0x27,0x01},
+{0xED91,0x59,0x01},
+{0xED92,0xF1,0x01},
+{0xED93,0x0B,0x01},
+{0xED94,0x64,0x01},
+{0xED95,0xA2,0x01},
+{0xED96,0x43,0x01},
+{0xED97,0x99,0x01},
+{0xED98,0xE4,0x01},
+{0xED99,0x68,0x01},
+{0xED9A,0x25,0x01},
+{0xED9B,0x2F,0x01},
+{0xED9C,0x2B,0x01},
+{0xED9D,0xB1,0x01},
+{0xED9E,0xC9,0x01},
+{0xED9F,0x42,0x01},
+{0xEDA0,0x18,0x01},
+{0xEDA1,0x32,0x01},
+{0xEDA2,0x90,0x01},
+{0xEDA3,0x80,0x01},
+{0xEDA4,0x3C,0x01},
+{0xEDA5,0x24,0x01},
+{0xEDA6,0x22,0x01},
+{0xEDA7,0x2F,0x01},
+{0xEDA8,0xF1,0x01},
+{0xEDA9,0x09,0x01},
+{0xEDAA,0x57,0x01},
+{0xEDAB,0x00,0x01},
+{0xEDAC,0x53,0x01},
+{0xEDAD,0x99,0x01},
+{0xEDAE,0xEA,0x01},
+{0xEDAF,0x90,0x01},
+{0xEDB0,0xC6,0x01},
+{0xEDB1,0x3B,0x01},
+{0xEDB2,0x6D,0x01},
+{0xEDB3,0x99,0x01},
+{0xEDB4,0x4C,0x01},
+{0xEDB5,0x50,0x01},
+{0xEDB6,0xA4,0x01},
+{0xEDB7,0x32,0x01},
+{0xEDB8,0x12,0x01},
+{0xEDB9,0x94,0x01},
+{0xEDBA,0x64,0x01},
+{0xEDBB,0xA4,0x01},
+{0xEDBC,0x23,0x01},
+{0xEDBD,0x25,0x01},
+{0xEDBE,0x71,0x01},
+{0xEDBF,0x49,0x01},
+{0xEDC0,0x51,0x01},
+{0xEDC1,0xB2,0x01},
+{0xEDC2,0x02,0x01},
+{0xEDC3,0x17,0x01},
+{0xEDC4,0xCD,0x01},
+{0xEDC5,0x98,0x01},
+{0xEDC6,0x86,0x01},
+{0xEDC7,0x3D,0x01},
+{0xEDC8,0xBC,0x01},
+{0xEDC9,0x01,0x01},
+{0xEDCA,0x50,0x01},
+{0xEDCB,0x63,0x01},
+{0xEDCC,0x80,0x01},
+{0xEDCD,0x63,0x01},
+{0xEDCE,0x16,0x01},
+{0xEDCF,0xC3,0x01},
+{0xEDD0,0x2C,0x01},
+{0xEDD1,0x25,0x01},
+{0xEDD2,0x2C,0x01},
+{0xEDD3,0x43,0x01},
+{0xEDD4,0xB1,0x01},
+{0xEDD5,0x4A,0x01},
+{0xEDD6,0x53,0x01},
+{0xEDD7,0xCC,0x01},
+{0xEDD8,0x82,0x01},
+{0xEDD9,0x96,0x01},
+{0xEDDA,0xC7,0x01},
+{0xEDDB,0x40,0x01},
+{0xEDDC,0xA6,0x01},
+{0xEDDD,0x39,0x01},
+{0xEDDE,0xBE,0x01},
+{0xEDDF,0x91,0x01},
+{0xEDE0,0xD0,0x01},
+{0xEDE1,0x75,0x01},
+{0xEDE2,0x54,0x01},
+{0xEDE3,0x34,0x01},
+{0xEDE4,0x1B,0x01},
+{0xEDE5,0xFC,0x01},
+{0xEDE6,0x4C,0x01},
+{0xEDE7,0x46,0x01},
+{0xEDE8,0x39,0x01},
+{0xEDE9,0x7D,0x01},
+{0xEDEA,0x71,0x01},
+{0xEDEB,0x8D,0x01},
+{0xEDEC,0x5D,0x01},
+{0xEDED,0x46,0x01},
+{0xEDEE,0xE3,0x01},
+{0xEDEF,0x17,0x01},
+{0xEDF0,0xD9,0x01},
+{0xEDF1,0x50,0x01},
+{0xEDF2,0x86,0x01},
+{0xEDF3,0x3A,0x01},
+{0xEDF4,0xB3,0x01},
+{0xEDF5,0x09,0x01},
+{0xEDF6,0x50,0x01},
+{0xEDF7,0x76,0x01},
+{0xEDF8,0x6A,0x01},
+{0xEDF9,0xF4,0x01},
+{0xEDFA,0x1E,0x01},
+{0xEDFB,0x25,0x01},
+{0xEDFC,0x61,0x01},
+{0xEDFD,0x67,0x01},
+{0xEDFE,0x45,0x01},
+{0xEDFF,0xC0,0x01},
+{0xEE00,0x69,0x01},
+{0xEE01,0xD0,0x01},
+{0xEE02,0x6B,0x01},
+{0xEE03,0xF6,0x01},
+{0xEE04,0x93,0x01},
+{0xEE05,0x9A,0x01},
+{0xEE06,0xFA,0x01},
+{0xEE07,0xB8,0x01},
+{0xEE08,0x26,0x01},
+{0xEE09,0x40,0x01},
+{0xEE0A,0xC0,0x01},
+{0xEE0B,0xB9,0x01},
+{0xEE0C,0xD0,0x01},
+{0xEE0D,0x75,0x01},
+{0xEE0E,0x6E,0x01},
+{0xEE0F,0xE4,0x01},
+{0xEE10,0x9E,0x01},
+{0xEE11,0x2D,0x01},
+{0xEE12,0xE1,0x01},
+{0xEE13,0xA7,0x01},
+{0xEE14,0x49,0x01},
+{0xEE15,0xFD,0x01},
+{0xEE16,0xB9,0x01},
+{0xEE17,0x52,0x01},
+{0xEE18,0x7C,0x01},
+{0xEE19,0x98,0x01},
+{0xEE1A,0x64,0x01},
+{0xEE1B,0x1E,0x01},
+{0xEE1C,0x22,0x01},
+{0xEE1D,0x89,0x01},
+{0xEE1E,0xA7,0x01},
+{0xEE1F,0x48,0x01},
+{0xEE20,0xE4,0x01},
+{0xEE21,0x49,0x01},
+{0xEE22,0x12,0x01},
+{0xEE23,0x7D,0x01},
+{0xEE24,0xB4,0x01},
+{0xEE25,0xB4,0x01},
+{0xEE26,0x1F,0x01},
+{0xEE27,0x31,0x01},
+{0xEE28,0xC5,0x01},
+{0xEE29,0x47,0x01},
+{0xEE2A,0x4B,0x01},
+{0xEE2B,0xC2,0x01},
+{0xEE2C,0x19,0x01},
+{0xEE2D,0x0F,0x01},
+{0xEE2E,0x73,0x01},
+{0xEE2F,0xE2,0x01},
+{0xEE30,0x13,0x01},
+{0xEE31,0x1C,0x01},
+{0xEE32,0xF5,0x01},
+{0xEE33,0xE0,0x01},
+{0xEE34,0xC6,0x01},
+{0xEE35,0x3B,0x01},
+{0xEE36,0xB6,0x01},
+{0xEE37,0xB1,0x01},
+{0xEE38,0xCE,0x01},
+{0xEE39,0x6D,0x01},
+{0xEE3A,0xB8,0x01},
+{0xEE3B,0xF3,0x01},
+{0xEE3C,0x9B,0x01},
+{0xEE3D,0xF2,0x01},
+{0xEE3E,0x18,0x01},
+{0xEE3F,0x27,0x01},
+{0xEE40,0x3D,0x01},
+{0xEE41,0xBF,0x01},
+{0xEE42,0xE9,0x01},
+{0xEE43,0xCE,0x01},
+{0xEE44,0x6E,0x01},
+{0xEE45,0xBA,0x01},
+{0xEE46,0x83,0x01},
+{0xEE47,0x9A,0x01},
+{0xEE48,0xE4,0x01},
+{0xEE49,0x50,0x01},
+{0xEE4A,0x66,0x01},
+{0xEE4B,0x36,0x01},
+{0xEE4C,0x8A,0x01},
+{0xEE4D,0x29,0x01},
+{0xEE4E,0x4D,0x01},
+{0xEE4F,0x61,0x01},
+{0xEE50,0x3A,0x01},
+{0xEE51,0xA3,0x01},
+{0xEE52,0x18,0x01},
+{0xEE53,0xD2,0x01},
+{0xEE54,0x50,0x01},
+{0xEE55,0x26,0x01},
+{0xEE56,0x36,0x01},
+{0xEE57,0xA8,0x01},
+{0xEE58,0x21,0x01},
+{0xEE59,0xCE,0x01},
+{0xEE5A,0x6E,0x01},
+{0xEE5B,0xB2,0x01},
+{0xEE5C,0x03,0x01},
+{0xEE5D,0x9A,0x01},
+{0xEE5E,0xE0,0x01},
+{0xEE5F,0x1C,0x01},
+{0xEE60,0x46,0x01},
+{0xEE61,0x34,0x01},
+{0xEE62,0x72,0x01},
+{0xEE63,0x41,0x01},
+{0xEE64,0x8C,0x01},
+{0xEE65,0x58,0x01},
+{0xEE66,0xE8,0x01},
+{0xEE67,0xC2,0x01},
+{0xEE68,0x95,0x01},
+{0xEE69,0xB5,0x01},
+{0xEE6A,0x88,0x01},
+{0xEE6B,0x65,0x01},
+{0xEE6C,0x2E,0x01},
+{0xEE6D,0x72,0x01},
+{0xEE6E,0x39,0x01},
+{0xEE6F,0x8C,0x01},
+{0xEE70,0x62,0x01},
+{0xEE71,0x48,0x01},
+{0xEE72,0x83,0x01},
+{0xEE73,0x1A,0x01},
+{0xEE74,0xE4,0x01},
+{0xEE75,0x28,0x01},
+{0xEE76,0x06,0x01},
+{0xEE77,0x35,0x01},
+{0xEE78,0x6A,0x01},
+{0xEE79,0xF9,0x01},
+{0xEE7A,0x4B,0x01},
+{0xEE7B,0x53,0x01},
+{0xEE7C,0xB8,0x01},
+{0xEE7D,0x92,0x01},
+{0xEE7E,0x13,0x01},
+{0xEE7F,0xA2,0x01},
+{0xEE80,0xCC,0x01},
+{0xEE81,0x64,0x01},
+{0xEE82,0x27,0x01},
+{0xEE83,0x3B,0x01},
+{0xEE84,0x29,0x01},
+{0xEE85,0x0A,0x01},
+{0xEE86,0x54,0x01},
+{0xEE87,0xBC,0x01},
+{0xEE88,0xF2,0x01},
+{0xEE89,0x96,0x01},
+{0xEE8A,0xC1,0x01},
+{0xEE8B,0x40,0x01},
+{0xEE8C,0xA6,0x01},
+{0xEE8D,0x35,0x01},
+{0xEE8E,0x7A,0x01},
+{0xEE8F,0xB1,0x01},
+{0xEE90,0x8C,0x01},
+{0xEE91,0x54,0x01},
+{0xEE92,0xC8,0x01},
+{0xEE93,0xF2,0x01},
+{0xEE94,0x92,0x01},
+{0xEE95,0x9D,0x01},
+{0xEE96,0x64,0x01},
+{0xEE97,0xE4,0x01},
+{0xEE98,0x23,0x01},
+{0xEE99,0x13,0x01},
+{0xEE9A,0xA9,0x01},
+{0xEE9B,0x48,0x01},
+{0xEE9C,0x47,0x01},
+{0xEE9D,0x40,0x01},
+{0xEE9E,0x42,0x01},
+{0xEE9F,0x13,0x01},
+{0xEEA0,0x9F,0x01},
+{0xEEA1,0x58,0x01},
+{0xEEA2,0xE5,0x01},
+{0xEEA3,0x2C,0x01},
+{0xEEA4,0x7F,0x01},
+{0xEEA5,0xD9,0x01},
+{0xEEA6,0x8C,0x01},
+{0xEEA7,0x5B,0x01},
+{0xEEA8,0x12,0x01},
+{0xEEA9,0x43,0x01},
+{0xEEAA,0x14,0x01},
+{0xEEAB,0xAA,0x01},
+{0xEEAC,0x80,0x01},
+{0xEEAD,0x04,0x01},
+{0xEEAE,0x25,0x01},
+{0xEEAF,0x06,0x01},
+{0xEEB0,0x51,0x01},
+{0xEEB1,0x08,0x01},
+{0xEEB2,0x40,0x01},
+{0xEEB3,0x00,0x01},
+{0xEEB4,0xB2,0x01},
+{0xEEB5,0x10,0x01},
+{0xEEB6,0x86,0x01},
+{0xEEB7,0x98,0x01},
+{0xEEB8,0x64,0x01},
+{0xEEB9,0x25,0x01},
+{0xEEBA,0x4A,0x01},
+{0xEEBB,0xB9,0x01},
+{0xEEBC,0x0A,0x01},
+{0xEEBD,0x5D,0x01},
+{0xEEBE,0x1C,0x01},
+{0xEEBF,0x13,0x01},
+{0xEEC0,0x97,0x01},
+{0xEEC1,0xC4,0x01},
+{0xEEC2,0x18,0x01},
+{0xEEC3,0x85,0x01},
+{0xEEC4,0x2A,0x01},
+{0xEEC5,0x21,0x01},
+{0xEEC6,0x41,0x01},
+{0xEEC7,0xC9,0x01},
+{0xEEC8,0x41,0x01},
+{0xEEC9,0x12,0x01},
+{0xEECA,0x02,0x01},
+{0xEECB,0x10,0x01},
+{0xEECC,0x80,0x01},
+{0xEECD,0x2C,0x01},
+{0xEECE,0x64,0x01},
+{0xEECF,0x21,0x01},
+{0xEED0,0x27,0x01},
+{0xEED1,0x61,0x01},
+{0xEED2,0xC9,0x01},
+{0xEED3,0x52,0x01},
+{0xEED4,0xB0,0x01},
+{0xEED5,0x42,0x01},
+{0xEED6,0x17,0x01},
+{0xEED7,0xC8,0x01},
+{0xEED8,0x04,0x01},
+{0xEED9,0xE6,0x01},
+{0xEEDA,0x32,0x01},
+{0xEEDB,0x58,0x01},
+{0xEEDC,0x29,0x01},
+{0xEEDD,0xCB,0x01},
+{0xEEDE,0x4C,0x01},
+{0xEEDF,0x74,0x01},
+{0xEEE0,0x92,0x01},
+{0xEEE1,0x91,0x01},
+{0xEEE2,0x8E,0x01},
+{0xEEE3,0x48,0x01},
+{0xEEE4,0x84,0x01},
+{0xEEE5,0x22,0x01},
+{0xEEE6,0x1D,0x01},
+{0xEEE7,0x01,0x01},
+{0xEEE8,0xC9,0x01},
+{0xEEE9,0x4D,0x01},
+{0xEEEA,0x7E,0x01},
+{0xEEEB,0x82,0x01},
+{0xEEEC,0x15,0x01},
+{0xEEED,0xB5,0x01},
+{0xEEEE,0x04,0x01},
+{0xEEEF,0xE6,0x01},
+{0xEEF0,0x33,0x01},
+{0xEEF1,0x99,0x01},
+{0xEEF2,0x69,0x01},
+{0xEEF3,0x0D,0x01},
+{0xEEF4,0x5D,0x01},
+{0xEEF5,0x06,0x01},
+{0xEEF6,0x33,0x01},
+{0xEEF7,0x15,0x01},
+{0xEEF8,0xAF,0x01},
+{0xEEF9,0xEC,0x01},
+{0xEEFA,0xA4,0x01},
+{0xEEFB,0x28,0x01},
+{0xEEFC,0x35,0x01},
+{0xEEFD,0xE9,0x01},
+{0xEEFE,0x09,0x01},
+{0xEEFF,0x4F,0x01},
+{0xEF00,0x8E,0x01},
+{0xEF01,0x02,0x01},
+{0xEF02,0x95,0x01},
+{0xEF03,0xB1,0x01},
+{0xEF04,0xC4,0x01},
+{0xEF05,0x25,0x01},
+{0xEF06,0x31,0x01},
+{0xEF07,0x94,0x01},
+{0xEF08,0xB1,0x01},
+{0xEF09,0x4D,0x01},
+{0xEF0A,0x6C,0x01},
+{0xEF0B,0x94,0x01},
+{0xEF0C,0x43,0x01},
+{0xEF0D,0x99,0x01},
+{0xEF0E,0xD4,0x01},
+{0xEF0F,0xEC,0x01},
+{0xEF10,0xC5,0x01},
+{0xEF11,0x31,0x01},
+{0xEF12,0x69,0x01},
+{0xEF13,0xC9,0x01},
+{0xEF14,0x0B,0x01},
+{0xEF15,0x58,0x01},
+{0xEF16,0xE6,0x01},
+{0xEF17,0x52,0x01},
+{0xEF18,0x16,0x01},
+{0xEF19,0xBE,0x01},
+{0xEF1A,0xD4,0x01},
+{0xEF1B,0x45,0x01},
+{0xEF1C,0x32,0x01},
+{0xEF1D,0x8E,0x01},
+{0xEF1E,0x79,0x01},
+{0xEF1F,0x4D,0x01},
+{0xEF20,0x6A,0x01},
+{0xEF21,0xA4,0x01},
+{0xEF22,0x83,0x01},
+{0xEF23,0x1C,0x01},
+{0xEF24,0xF2,0x01},
+{0xEF25,0xDC,0x01},
+{0xEF26,0x26,0x01},
+{0xEF27,0x3A,0x01},
+{0xEF28,0xA3,0x01},
+{0xEF29,0xE1,0x01},
+{0xEF2A,0x4D,0x01},
+{0xEF2B,0x65,0x01},
+{0xEF2C,0x5C,0x01},
+{0xEF2D,0xC3,0x01},
+{0xEF2E,0x98,0x01},
+{0xEF2F,0xD4,0x01},
+{0xEF30,0x3C,0x01},
+{0xEF31,0xE6,0x01},
+{0xEF32,0x35,0x01},
+{0xEF33,0x9D,0x01},
+{0xEF34,0x09,0x01},
+{0xEF35,0x8E,0x01},
+{0xEF36,0x6B,0x01},
+{0xEF37,0xAC,0x01},
+{0xEF38,0xE3,0x01},
+{0xEF39,0x9B,0x01},
+{0xEF3A,0xF4,0x01},
+{0xEF3B,0x34,0x01},
+{0xEF3C,0x07,0x01},
+{0xEF3D,0x3E,0x01},
+{0xEF3E,0xDA,0x01},
+{0xEF3F,0xC1,0x01},
+{0xEF40,0x8F,0x01},
+{0xEF41,0x74,0x01},
+{0xEF42,0xEA,0x01},
+{0xEF43,0x13,0x01},
+{0xEF44,0x9C,0x01},
+{0xEF45,0xF4,0x01},
+{0xEF46,0xF0,0x01},
+{0xEF47,0xA6,0x01},
+{0xEF48,0x3C,0x01},
+{0xEF49,0xC0,0x01},
+{0xEF4A,0x49,0x01},
+{0xEF4B,0x0F,0x01},
+{0xEF4C,0x72,0x01},
+{0xEF4D,0xEA,0x01},
+{0xEF4E,0xD3,0x01},
+{0xEF4F,0x9C,0x01},
+{0xEF50,0xFE,0x01},
+{0xEF51,0x04,0x01},
+{0xEF52,0xA7,0x01},
+{0xEF53,0x3D,0x01},
+
+//SHD2 CW+TL84 33:66
+
+{0xED00,0x9191,0x02},//
+{0xEF54,0x21,0x01},
+{0xEF55,0x92,0x01},
+{0xEF56,0xD1,0x01},
+{0xEF57,0x8A,0x01},
+{0xEF58,0x3E,0x01},
+{0xEF59,0xF4,0x01},
+{0xEF5A,0xA1,0x01},
+{0xEF5B,0x10,0x01},
+{0xEF5C,0xB9,0x01},
+{0xEF5D,0x48,0x01},
+{0xEF5E,0x46,0x01},
+{0xEF5F,0x1F,0x01},
+{0xEF60,0x82,0x01},
+{0xEF61,0x10,0x01},
+{0xEF62,0x7E,0x01},
+{0xEF63,0xBC,0x01},
+{0xEF64,0xC3,0x01},
+{0xEF65,0x1C,0x01},
+{0xEF66,0xE3,0x01},
+{0xEF67,0x38,0x01},
+{0xEF68,0xC7,0x01},
+{0xEF69,0x3B,0x01},
+{0xEF6A,0xF7,0x01},
+{0xEF6B,0x71,0x01},
+{0xEF6C,0x90,0x01},
+{0xEF6D,0x7B,0x01},
+{0xEF6E,0x8E,0x01},
+{0xEF6F,0x53,0x01},
+{0xEF70,0x1A,0x01},
+{0xEF71,0xC5,0x01},
+{0xEF72,0x04,0x01},
+{0xEF73,0x46,0x01},
+{0xEF74,0x31,0x01},
+{0xEF75,0xA2,0x01},
+{0xEF76,0x39,0x01},
+{0xEF77,0x0E,0x01},
+{0xEF78,0x7E,0x01},
+{0xEF79,0x9A,0x01},
+{0xEF7A,0xA3,0x01},
+{0xEF7B,0x99,0x01},
+{0xEF7C,0xB5,0x01},
+{0xEF7D,0x34,0x01},
+{0xEF7E,0x85,0x01},
+{0xEF7F,0x28,0x01},
+{0xEF80,0x4D,0x01},
+{0xEF81,0x61,0x01},
+{0xEF82,0x8B,0x01},
+{0xEF83,0x67,0x01},
+{0xEF84,0xB0,0x01},
+{0xEF85,0x53,0x01},
+{0xEF86,0x1B,0x01},
+{0xEF87,0xBB,0x01},
+{0xEF88,0x08,0x01},
+{0xEF89,0x45,0x01},
+{0xEF8A,0x24,0x01},
+{0xEF8B,0x17,0x01},
+{0xEF8C,0x11,0x01},
+{0xEF8D,0x09,0x01},
+{0xEF8E,0x51,0x01},
+{0xEF8F,0xF2,0x01},
+{0xEF90,0xA2,0x01},
+{0xEF91,0x9B,0x01},
+{0xEF92,0xD3,0x01},
+{0xEF93,0x90,0x01},
+{0xEF94,0xC5,0x01},
+{0xEF95,0x25,0x01},
+{0xEF96,0x0A,0x01},
+{0xEF97,0x01,0x01},
+{0xEF98,0x48,0x01},
+{0xEF99,0x43,0x01},
+{0xEF9A,0x62,0x01},
+{0xEF9B,0x52,0x01},
+{0xEF9C,0x16,0x01},
+{0xEF9D,0xD5,0x01},
+{0xEF9E,0x9C,0x01},
+{0xEF9F,0xC6,0x01},
+{0xEFA0,0x2C,0x01},
+{0xEFA1,0x2F,0x01},
+{0xEFA2,0x51,0x01},
+{0xEFA3,0x48,0x01},
+{0xEFA4,0x40,0x01},
+{0xEFA5,0x1C,0x01},
+{0xEFA6,0x22,0x01},
+{0xEFA7,0x93,0x01},
+{0xEFA8,0xB3,0x01},
+{0xEFA9,0xB8,0x01},
+{0xEFAA,0x46,0x01},
+{0xEFAB,0x37,0x01},
+{0xEFAC,0x7A,0x01},
+{0xEFAD,0x21,0x01},
+{0xEFAE,0x4A,0x01},
+{0xEFAF,0x48,0x01},
+{0xEFB0,0x30,0x01},
+{0xEFB1,0x52,0x01},
+{0xEFB2,0x12,0x01},
+{0xEFB3,0xA4,0x01},
+{0xEFB4,0xF0,0x01},
+{0xEFB5,0xE5,0x01},
+{0xEFB6,0x37,0x01},
+{0xEFB7,0xD6,0x01},
+{0xEFB8,0xF9,0x01},
+{0xEFB9,0x8C,0x01},
+{0xEFBA,0x5B,0x01},
+{0xEFBB,0x9E,0x01},
+{0xEFBC,0x62,0x01},
+{0xEFBD,0x14,0x01},
+{0xEFBE,0xA9,0x01},
+{0xEFBF,0xC8,0x01},
+{0xEFC0,0xA5,0x01},
+{0xEFC1,0x34,0x01},
+{0xEFC2,0xE0,0x01},
+{0xEFC3,0xD1,0x01},
+{0xEFC4,0x8F,0x01},
+{0xEFC5,0x73,0x01},
+{0xEFC6,0x4C,0x01},
+{0xEFC7,0xE3,0x01},
+{0xEFC8,0x18,0x01},
+{0xEFC9,0xC2,0x01},
+{0xEFCA,0x3C,0x01},
+{0xEFCB,0x46,0x01},
+{0xEFCC,0x35,0x01},
+{0xEFCD,0xD2,0x01},
+{0xEFCE,0x09,0x01},
+{0xEFCF,0x90,0x01},
+{0xEFD0,0x85,0x01},
+{0xEFD1,0xF6,0x01},
+{0xEFD2,0x03,0x01},
+{0xEFD3,0x1E,0x01},
+{0xEFD4,0xE7,0x01},
+{0xEFD5,0x20,0x01},
+{0xEFD6,0x27,0x01},
+{0xEFD7,0x3A,0x01},
+{0xEFD8,0xE4,0x01},
+{0xEFD9,0x01,0x01},
+{0xEFDA,0x90,0x01},
+{0xEFDB,0x87,0x01},
+{0xEFDC,0x30,0x01},
+{0xEFDD,0x04,0x01},
+{0xEFDE,0x22,0x01},
+{0xEFDF,0x0B,0x01},
+{0xEFE0,0x2D,0x01},
+{0xEFE1,0x28,0x01},
+{0xEFE2,0x41,0x01},
+{0xEFE3,0x10,0x01},
+{0xEFE4,0xDA,0x01},
+{0xEFE5,0x90,0x01},
+{0xEFE6,0x88,0x01},
+{0xEFE7,0x3C,0x01},
+{0xEFE8,0x04,0x01},
+{0xEFE9,0x00,0x01},
+{0xEFEA,0x00,0x01},
+{0xEFEB,0x00,0x01},
+{0xEFEC,0x00,0x01},
+{0xEFED,0x00,0x01},
+
+
+
+//SHD3 D65+TL84 C01//
+{0xED00,0x9191,0x02},//
+{0xEFEE,0x12,0x01},
+{0xEFEF,0x42,0x01},
+{0xEFF0,0x51,0x01},
+{0xEFF1,0x89,0x01},
+{0xEFF2,0x38,0x01},
+{0xEFF3,0xD4,0x01},
+{0xEFF4,0x21,0x01},
+{0xEFF5,0x10,0x01},
+{0xEFF6,0xAD,0x01},
+{0xEFF7,0xA8,0x01},
+{0xEFF8,0x45,0x01},
+{0xEFF9,0x18,0x01},
+{0xEFFA,0x4A,0x01},
+{0xEFFB,0x50,0x01},
+{0xEFFC,0x7D,0x01},
+{0xEFFD,0xBA,0x01},
+{0xEFFE,0xD3,0x01},
+{0xEFFF,0x1C,0x01},
+{0xF000,0xE4,0x01},
+{0xF001,0x40,0x01},
+{0xF002,0x27,0x01},
+{0xF003,0x3C,0x01},
+{0xF004,0xF8,0x01},
+{0xF005,0x69,0x01},
+{0xF006,0x10,0x01},
+{0xF007,0x7B,0x01},
+{0xF008,0x8E,0x01},
+{0xF009,0x63,0x01},
+{0xF00A,0x1A,0x01},
+{0xF00B,0xC6,0x01},
+{0xF00C,0x10,0x01},
+{0xF00D,0xA6,0x01},
+{0xF00E,0x31,0x01},
+{0xF00F,0xA6,0x01},
+{0xF010,0x59,0x01},
+{0xF011,0x8E,0x01},
+{0xF012,0x7E,0x01},
+{0xF013,0x9A,0x01},
+{0xF014,0xB3,0x01},
+{0xF015,0x19,0x01},
+{0xF016,0xB6,0x01},
+{0xF017,0x38,0x01},
+{0xF018,0xA5,0x01},
+{0xF019,0x28,0x01},
+{0xF01A,0x4F,0x01},
+{0xF01B,0x79,0x01},
+{0xF01C,0xCB,0x01},
+{0xF01D,0x68,0x01},
+{0xF01E,0xBA,0x01},
+{0xF01F,0x53,0x01},
+{0xF020,0x9B,0x01},
+{0xF021,0xBB,0x01},
+{0xF022,0x0C,0x01},
+{0xF023,0x65,0x01},
+{0xF024,0x24,0x01},
+{0xF025,0x17,0x01},
+{0xF026,0x21,0x01},
+{0xF027,0xC9,0x01},
+{0xF028,0x51,0x01},
+{0xF029,0xFC,0x01},
+{0xF02A,0xF2,0x01},
+{0xF02B,0x9B,0x01},
+{0xF02C,0xD3,0x01},
+{0xF02D,0x94,0x01},
+{0xF02E,0xC5,0x01},
+{0xF02F,0x25,0x01},
+{0xF030,0x0A,0x01},
+{0xF031,0x01,0x01},
+{0xF032,0x48,0x01},
+{0xF033,0x43,0x01},
+{0xF034,0x66,0x01},
+{0xF035,0x92,0x01},
+{0xF036,0x96,0x01},
+{0xF037,0xD7,0x01},
+{0xF038,0xA0,0x01},
+{0xF039,0xE6,0x01},
+{0xF03A,0x2C,0x01},
+{0xF03B,0x2F,0x01},
+{0xF03C,0x51,0x01},
+{0xF03D,0x48,0x01},
+{0xF03E,0x40,0x01},
+{0xF03F,0x1E,0x01},
+{0xF040,0x42,0x01},
+{0xF041,0x93,0x01},
+{0xF042,0xB5,0x01},
+{0xF043,0xCC,0x01},
+{0xF044,0x46,0x01},
+{0xF045,0x37,0x01},
+{0xF046,0x7C,0x01},
+{0xF047,0x29,0x01},
+{0xF048,0x8A,0x01},
+{0xF049,0x48,0x01},
+{0xF04A,0x32,0x01},
+{0xF04B,0x72,0x01},
+{0xF04C,0x12,0x01},
+{0xF04D,0xA5,0x01},
+{0xF04E,0x00,0x01},
+{0xF04F,0xA6,0x01},
+{0xF050,0x38,0x01},
+{0xF051,0xD7,0x01},
+{0xF052,0x01,0x01},
+{0xF053,0x0D,0x01},
+{0xF054,0x5C,0x01},
+{0xF055,0xA2,0x01},
+{0xF056,0x82,0x01},
+{0xF057,0x94,0x01},
+{0xF058,0xAA,0x01},
+{0xF059,0xD8,0x01},
+{0xF05A,0x45,0x01},
+{0xF05B,0x35,0x01},
+{0xF05C,0xE5,0x01},
+{0xF05D,0xC9,0x01},
+{0xF05E,0xCF,0x01},
+{0xF05F,0x73,0x01},
+{0xF060,0x50,0x01},
+{0xF061,0x03,0x01},
+{0xF062,0x99,0x01},
+{0xF063,0xC3,0x01},
+{0xF064,0x4C,0x01},
+{0xF065,0xE6,0x01},
+{0xF066,0x35,0x01},
+{0xF067,0xD7,0x01},
+{0xF068,0x21,0x01},
+{0xF069,0x10,0x01},
+{0xF06A,0x84,0x01},
+{0xF06B,0xF2,0x01},
+{0xF06C,0x03,0x01},
+{0xF06D,0x9E,0x01},
+{0xF06E,0xE8,0x01},
+{0xF06F,0x2C,0x01},
+{0xF070,0xA7,0x01},
+{0xF071,0x3A,0x01},
+{0xF072,0xE8,0x01},
+{0xF073,0x11,0x01},
+{0xF074,0x90,0x01},
+{0xF075,0x87,0x01},
+{0xF076,0x18,0x01},
+{0xF077,0x94,0x01},
+{0xF078,0x21,0x01},
+{0xF079,0x09,0x01},
+{0xF07A,0x2D,0x01},
+{0xF07B,0x68,0x01},
+{0xF07C,0x41,0x01},
+{0xF07D,0x11,0x01},
+{0xF07E,0xDA,0x01},
+{0xF07F,0x10,0x01},
+{0xF080,0x88,0x01},
+{0xF081,0x2A,0x01},
+{0xF082,0x04,0x01},
+{0xF083,0x00,0x01},
+{0xF084,0x00,0x01},
+{0xF085,0x00,0x01},
+{0xF086,0x00,0x01},
+{0xF087,0x00,0x01},
+{0xF088,0xBE,0x01},
+{0xF089,0x51,0x01},
+{0xF08A,0x4E,0x01},
+{0xF08B,0x6F,0x01},
+{0xF08C,0x6C,0x01},
+{0xF08D,0x43,0x01},
+{0xF08E,0x1B,0x01},
+{0xF08F,0xDA,0x01},
+{0xF090,0xEC,0x01},
+{0xF091,0x46,0x01},
+{0xF092,0x38,0x01},
+{0xF093,0xBB,0x01},
+{0xF094,0xC1,0x01},
+{0xF095,0xCD,0x01},
+{0xF096,0x69,0x01},
+{0xF097,0x26,0x01},
+{0xF098,0x93,0x01},
+{0xF099,0x98,0x01},
+{0xF09A,0xC1,0x01},
+{0xF09B,0x20,0x01},
+{0xF09C,0x26,0x01},
+{0xF09D,0x32,0x01},
+{0xF09E,0xA5,0x01},
+{0xF09F,0xB1,0x01},
+{0xF0A0,0x8D,0x01},
+{0xF0A1,0x67,0x01},
+{0xF0A2,0x0E,0x01},
+{0xF0A3,0x23,0x01},
+{0xF0A4,0x97,0x01},
+{0xF0A5,0xB0,0x01},
+{0xF0A6,0x6C,0x01},
+{0xF0A7,0x25,0x01},
+{0xF0A8,0x2C,0x01},
+{0xF0A9,0x71,0x01},
+{0xF0AA,0x41,0x01},
+{0xF0AB,0x0C,0x01},
+{0xF0AC,0x69,0x01},
+{0xF0AD,0x14,0x01},
+{0xF0AE,0xB3,0x01},
+{0xF0AF,0x96,0x01},
+{0xF0B0,0xA6,0x01},
+{0xF0B1,0xE8,0x01},
+{0xF0B2,0x64,0x01},
+{0xF0B3,0x26,0x01},
+{0xF0B4,0x3A,0x01},
+{0xF0B5,0x79,0x01},
+{0xF0B6,0x4A,0x01},
+{0xF0B7,0x5B,0x01},
+{0xF0B8,0x18,0x01},
+{0xF0B9,0xA3,0x01},
+{0xF0BA,0x97,0x01},
+{0xF0BB,0xA9,0x01},
+{0xF0BC,0xBC,0x01},
+{0xF0BD,0x24,0x01},
+{0xF0BE,0x23,0x01},
+{0xF0BF,0x13,0x01},
+{0xF0C0,0xE1,0x01},
+{0xF0C1,0xC8,0x01},
+{0xF0C2,0x4C,0x01},
+{0xF0C3,0xAA,0x01},
+{0xF0C4,0xA2,0x01},
+{0xF0C5,0x97,0x01},
+{0xF0C6,0xB6,0x01},
+{0xF0C7,0x14,0x01},
+{0xF0C8,0x05,0x01},
+{0xF0C9,0x24,0x01},
+{0xF0CA,0x06,0x01},
+{0xF0CB,0x09,0x01},
+{0xF0CC,0xC8,0x01},
+{0xF0CD,0x42,0x01},
+{0xF0CE,0x48,0x01},
+{0xF0CF,0x82,0x01},
+{0xF0D0,0x14,0x01},
+{0xF0D1,0xB8,0x01},
+{0xF0D2,0xC0,0x01},
+{0xF0D3,0xE5,0x01},
+{0xF0D4,0x28,0x01},
+{0xF0D5,0x21,0x01},
+{0xF0D6,0x39,0x01},
+{0xF0D7,0x08,0x01},
+{0xF0D8,0x40,0x01},
+{0xF0D9,0x14,0x01},
+{0xF0DA,0x62,0x01},
+{0xF0DB,0x92,0x01},
+{0xF0DC,0xA4,0x01},
+{0xF0DD,0xC4,0x01},
+{0xF0DE,0x05,0x01},
+{0xF0DF,0x30,0x01},
+{0xF0E0,0x58,0x01},
+{0xF0E1,0xA1,0x01},
+{0xF0E2,0x49,0x01},
+{0xF0E3,0x46,0x01},
+{0xF0E4,0x22,0x01},
+{0xF0E5,0xB2,0x01},
+{0xF0E6,0x91,0x01},
+{0xF0E7,0x9A,0x01},
+{0xF0E8,0x58,0x01},
+{0xF0E9,0xA5,0x01},
+{0xF0EA,0x2F,0x01},
+{0xF0EB,0x96,0x01},
+{0xF0EC,0x99,0x01},
+{0xF0ED,0x8B,0x01},
+{0xF0EE,0x54,0x01},
+{0xF0EF,0x74,0x01},
+{0xF0F0,0x32,0x01},
+{0xF0F1,0x13,0x01},
+{0xF0F2,0x9D,0x01},
+{0xF0F3,0x38,0x01},
+{0xF0F4,0xC5,0x01},
+{0xF0F5,0x2D,0x01},
+{0xF0F6,0x90,0x01},
+{0xF0F7,0x59,0x01},
+{0xF0F8,0x4D,0x01},
+{0xF0F9,0x64,0x01},
+{0xF0FA,0xEE,0x01},
+{0xF0FB,0x62,0x01},
+{0xF0FC,0x16,0x01},
+{0xF0FD,0xAE,0x01},
+{0xF0FE,0x84,0x01},
+{0xF0FF,0x25,0x01},
+{0xF100,0x2E,0x01},
+{0xF101,0x8B,0x01},
+{0xF102,0x31,0x01},
+{0xF103,0xCD,0x01},
+{0xF104,0x6F,0x01},
+{0xF105,0x60,0x01},
+{0xF106,0xC3,0x01},
+{0xF107,0x19,0x01},
+{0xF108,0xC7,0x01},
+{0xF109,0x14,0x01},
+{0xF10A,0x26,0x01},
+{0xF10B,0x31,0x01},
+{0xF10C,0x97,0x01},
+{0xF10D,0x41,0x01},
+{0xF10E,0x8D,0x01},
+{0xF10F,0x6D,0x01},
+{0xF110,0x86,0x01},
+{0xF111,0xE3,0x01},
+{0xF112,0x9C,0x01},
+{0xF113,0xE2,0x01},
+{0xF114,0xD8,0x01},
+{0xF115,0x06,0x01},
+{0xF116,0x36,0x01},
+{0xF117,0xB5,0x01},
+{0xF118,0xE9,0x01},
+{0xF119,0x4D,0x01},
+{0xF11A,0x70,0x01},
+{0xF11B,0x68,0x01},
+{0xF11C,0x03,0x01},
+{0xF11D,0x00,0x01},
+{0xF11E,0x00,0x01},
+{0xF11F,0x00,0x01},
+{0xF120,0x00,0x01},
+{0xF121,0x00,0x01},
+
+
+//SHD TH
+{0x6C32,0x1964,0x02},    // SHD_INP_TH_HB_H_R2
+{0x6C34,0x18CE,0x02},    // SHD_INP_TH_HB_L_R2
+{0x6C36,0x10CC,0x02},    // SHD_INP_TH_LB_H_R2
+{0x6C38,0x1004,0x02},    // SHD_INP_TH_LB_L_R2
+{0x6C3C,0x10CC,0x02},    // SHD_INP_TH_HB_H_RB
+{0x6C3E,0x1004,0x02},    // SHD_INP_TH_HB_L_RB
+{0x6C40,0x0000,0x02},    // SHD_INP_TH_LB_H_RB
+{0x6C42,0x0000,0x02},    // SHD_INP_TH_LB_L_RB
+
+//PreWB_offset (for SHD2)
+{0x6828,0x0013,0x02},    // SHD_PRER_OFFSET_R2 :
+//PreWB_offset (for SHD3)
+{0x682C,0x000C,0x02},    // SHD_PRER_OFFSET_RB :
+{0x6830,0xFFFF,0x02},    // SHD_PREB_OFFSET_RB :
+
+// CXC/SHD EN
+{0x01BC,0x57,0x01},    // CXC ON SHD ON INP ON GAIN OFF
+};
+
+static const isx012_regset_t ISX012_Shading_2[] =
+{
+{0x01BC,0x50,0x01},    // CXC OFF SHD OFF
+{0xEB00,0x8282,0x02},	//valid_code
+{0xEB02,0xFE,0x01},
+{0xEB03,0x84,0x01},
+{0xEB04,0x3F,0x01},
+{0xEB05,0x01,0x01},
+{0xEB06,0x50,0x01},
+{0xEB07,0x08,0x01},
+{0xEB08,0x14,0x01},
+{0xEB09,0xFF,0x01},
+{0xEB0A,0x45,0x01},
+{0xEB0B,0x80,0x01},
+{0xEB0C,0x01,0x01},
+{0xEB0D,0x68,0x01},
+{0xEB0E,0x04,0x01},
+{0xEB0F,0x1A,0x01},
+{0xEB10,0x81,0x01},
+{0xEB11,0x86,0x01},
+{0xEB12,0x3F,0x01},
+{0xEB13,0xE1,0x01},
+{0xEB14,0x4F,0x01},
+{0xEB15,0x00,0x01},
+{0xEB16,0x14,0x01},
+{0xEB17,0x02,0x01},
+{0xEB18,0xC5,0x01},
+{0xEB19,0x7F,0x01},
+{0xEB1A,0x11,0x01},
+{0xEB1B,0x60,0x01},
+{0xEB1C,0x00,0x01},
+{0xEB1D,0x1A,0x01},
+{0xEB1E,0x81,0x01},
+{0xEB1F,0x46,0x01},
+{0xEB20,0xA0,0x01},
+{0xEB21,0x01,0x01},
+{0xEB22,0x48,0x01},
+{0xEB23,0x00,0x01},
+{0xEB24,0x12,0x01},
+{0xEB25,0x81,0x01},
+{0xEB26,0x05,0x01},
+{0xEB27,0x20,0x01},
+{0xEB28,0xF1,0x01},
+{0xEB29,0x4F,0x01},
+{0xEB2A,0x00,0x01},
+{0xEB2B,0x14,0x01},
+{0xEB2C,0x82,0x01},
+{0xEB2D,0x85,0x01},
+{0xEB2E,0x80,0x01},
+{0xEB2F,0x21,0x01},
+{0xEB30,0x60,0x01},
+{0xEB31,0x04,0x01},
+{0xEB32,0x12,0x01},
+{0xEB33,0x81,0x01},
+{0xEB34,0x84,0x01},
+{0xEB35,0xE0,0x01},
+{0xEB36,0x00,0x01},
+{0xEB37,0x28,0x01},
+{0xEB38,0x04,0x01},
+{0xEB39,0x0C,0x01},
+{0xEB3A,0x82,0x01},
+{0xEB3B,0x43,0x01},
+{0xEB3C,0x20,0x01},
+{0xEB3D,0x11,0x01},
+{0xEB3E,0x68,0x01},
+{0xEB3F,0x04,0x01},
+{0xEB40,0x1A,0x01},
+{0xEB41,0x82,0x01},
+{0xEB42,0x83,0x01},
+{0xEB43,0xE0,0x01},
+{0xEB44,0x00,0x01},
+{0xEB45,0x20,0x01},
+{0xEB46,0x00,0x01},
+{0xEB47,0x06,0x01},
+{0xEB48,0xFF,0x01},
+{0xEB49,0x41,0x01},
+{0xEB4A,0x80,0x01},
+{0xEB4B,0x10,0x01},
+{0xEB4C,0x30,0x01},
+{0xEB4D,0x08,0x01},
+{0xEB4E,0x14,0x01},
+{0xEB4F,0x02,0x01},
+{0xEB50,0x45,0x01},
+{0xEB51,0xC0,0x01},
+{0xEB52,0x10,0x01},
+{0xEB53,0x30,0x01},
+{0xEB54,0x04,0x01},
+{0xEB55,0x04,0x01},
+{0xEB56,0x01,0x01},
+{0xEB57,0xC0,0x01},
+{0xEB58,0x3F,0x01},
+{0xEB59,0x10,0x01},
+{0xEB5A,0x10,0x01},
+{0xEB5B,0x04,0x01},
+{0xEB5C,0x0A,0x01},
+{0xEB5D,0x80,0x01},
+{0xEB5E,0x03,0x01},
+{0xEB5F,0xE0,0x01},
+{0xEB60,0x10,0x01},
+{0xEB61,0x28,0x01},
+{0xEB62,0x04,0x01},
+{0xEB63,0x0A,0x01},
+{0xEB64,0x81,0x01},
+{0xEB65,0x01,0x01},
+{0xEB66,0x00,0x01},
+{0xEB67,0x10,0x01},
+{0xEB68,0x00,0x01},
+{0xEB69,0x04,0x01},
+{0xEB6A,0x04,0x01},
+{0xEB6B,0x01,0x01},
+{0xEB6C,0x42,0x01},
+{0xEB6D,0xE0,0x01},
+{0xEB6E,0x10,0x01},
+{0xEB6F,0x38,0x01},
+{0xEB70,0xFC,0x01},
+{0xEB71,0x0D,0x01},
+{0xEB72,0x7F,0x01},
+{0xEB73,0x43,0x01},
+{0xEB74,0x60,0x01},
+{0xEB75,0x00,0x01},
+{0xEB76,0x08,0x01},
+{0xEB77,0x08,0x01},
+{0xEB78,0x02,0x01},
+{0xEB79,0x81,0x01},
+{0xEB7A,0x41,0x01},
+{0xEB7B,0x80,0x01},
+{0xEB7C,0x10,0x01},
+{0xEB7D,0x30,0x01},
+{0xEB7E,0x04,0x01},
+{0xEB7F,0x0C,0x01},
+{0xEB80,0x01,0x01},
+{0xEB81,0x43,0x01},
+{0xEB82,0xC0,0x01},
+{0xEB83,0x20,0x01},
+{0xEB84,0x28,0x01},
+{0xEB85,0x08,0x01},
+{0xEB86,0x06,0x01},
+{0xEB87,0x02,0x01},
+{0xEB88,0xC2,0x01},
+{0xEB89,0xA0,0x01},
+{0xEB8A,0x30,0x01},
+{0xEB8B,0x30,0x01},
+{0xEB8C,0x0C,0x01},
+{0xEB8D,0x12,0x01},
+{0xEB8E,0x83,0x01},
+{0xEB8F,0x84,0x01},
+{0xEB90,0x00,0x01},
+{0xEB91,0x21,0x01},
+{0xEB92,0x40,0x01},
+{0xEB93,0x0C,0x01},
+{0xEB94,0x0C,0x01},
+{0xEB95,0x82,0x01},
+{0xEB96,0x03,0x01},
+{0xEB97,0xC1,0x01},
+{0xEB98,0x40,0x01},
+{0xEB99,0x40,0x01},
+{0xEB9A,0x08,0x01},
+{0xEB9B,0x10,0x01},
+{0xEB9C,0x03,0x01},
+{0xEB9D,0xC4,0x01},
+{0xEB9E,0x00,0x01},
+{0xEB9F,0x21,0x01},
+{0xEBA0,0x38,0x01},
+{0xEBA1,0x08,0x01},
+{0xEBA2,0x0E,0x01},
+{0xEBA3,0x82,0x01},
+{0xEBA4,0xC3,0x01},
+{0xEBA5,0x20,0x01},
+{0xEBA6,0x41,0x01},
+{0xEBA7,0x48,0x01},
+{0xEBA8,0x00,0x01},
+{0xEBA9,0x14,0x01},
+{0xEBAA,0x83,0x01},
+{0xEBAB,0x44,0x01},
+{0xEBAC,0x20,0x01},
+{0xEBAD,0x11,0x01},
+{0xEBAE,0x48,0x01},
+{0xEBAF,0x08,0x01},
+{0xEBB0,0x0E,0x01},
+{0xEBB1,0x82,0x01},
+{0xEBB2,0x83,0x01},
+{0xEBB3,0xE0,0x01},
+{0xEBB4,0x30,0x01},
+{0xEBB5,0x48,0x01},
+{0xEBB6,0x10,0x01},
+{0xEBB7,0x12,0x01},
+{0xEBB8,0x00,0x01},
+{0xEBB9,0xC5,0x01},
+{0xEBBA,0x20,0x01},
+{0xEBBB,0x11,0x01},
+{0xEBBC,0x48,0x01},
+{0xEBBD,0x04,0x01},
+{0xEBBE,0x12,0x01},
+{0xEBBF,0x04,0x01},
+{0xEBC0,0x3B,0x01},
+{0xEBC1,0xC1,0x01},
+{0xEBC2,0x1E,0x01},
+{0xEBC3,0xC8,0x01},
+{0xEBC4,0x0F,0x01},
+{0xEBC5,0xF8,0x01},
+{0xEBC6,0x02,0x01},
+{0xEBC7,0xBB,0x01},
+{0xEBC8,0x60,0x01},
+{0xEBC9,0x0F,0x01},
+{0xEBCA,0xB8,0x01},
+{0xEBCB,0x0F,0x01},
+{0xEBCC,0xEA,0x01},
+{0xEBCD,0x83,0x01},
+{0xEBCE,0x3A,0x01},
+{0xEBCF,0xC1,0x01},
+{0xEBD0,0x4E,0x01},
+{0xEBD1,0xB0,0x01},
+{0xEBD2,0x07,0x01},
+{0xEBD3,0xF2,0x01},
+{0xEBD4,0x03,0x01},
+{0xEBD5,0xBE,0x01},
+{0xEBD6,0xC0,0x01},
+{0xEBD7,0x2E,0x01},
+{0xEBD8,0xD8,0x01},
+{0xEBD9,0x03,0x01},
+{0xEBDA,0xEE,0x01},
+{0xEBDB,0x83,0x01},
+{0xEBDC,0xFA,0x01},
+{0xEBDD,0xA0,0x01},
+{0xEBDE,0x2E,0x01},
+{0xEBDF,0xB0,0x01},
+{0xEBE0,0x0B,0x01},
+{0xEBE1,0xEC,0x01},
+{0xEBE2,0x05,0x01},
+{0xEBE3,0xBD,0x01},
+{0xEBE4,0x60,0x01},
+{0xEBE5,0x2F,0x01},
+{0xEBE6,0xD0,0x01},
+{0xEBE7,0x07,0x01},
+{0xEBE8,0xEC,0x01},
+{0xEBE9,0x02,0x01},
+{0xEBEA,0xBC,0x01},
+{0xEBEB,0x40,0x01},
+{0xEBEC,0x2F,0x01},
+{0xEBED,0xD0,0x01},
+{0xEBEE,0x13,0x01},
+{0xEBEF,0xEE,0x01},
+{0xEBF0,0x84,0x01},
+{0xEBF1,0xBB,0x01},
+{0xEBF2,0x00,0x01},
+{0xEBF3,0x1F,0x01},
+{0xEBF4,0xC8,0x01},
+{0xEBF5,0xFF,0x01},
+{0xEBF6,0xEF,0x01},
+{0xEBF7,0x00,0x01},
+{0xEBF8,0x7D,0x01},
+{0xEBF9,0x60,0x01},
+{0xEBFA,0x2F,0x01},
+{0xEBFB,0xD0,0x01},
+{0xEBFC,0x0B,0x01},
+{0xEBFD,0xF4,0x01},
+{0xEBFE,0x85,0x01},
+{0xEBFF,0x7D,0x01},
+{0xEC00,0x61,0x01},
+{0xEC01,0x0F,0x01},
+{0xEC02,0xC0,0x01},
+{0xEC03,0xFF,0x01},
+{0xEC04,0xF7,0x01},
+{0xEC05,0x7F,0x01},
+{0xEC06,0x3D,0x01},
+{0xEC07,0x40,0x01},
+{0xEC08,0xFF,0x01},
+{0xEC09,0xDF,0x01},
+{0xEC0A,0x07,0x01},
+{0xEC0B,0xFA,0x01},
+{0xEC0C,0x81,0x01},
+{0xEC0D,0x3E,0x01},
+{0xEC0E,0x61,0x01},
+{0xEC0F,0x4F,0x01},
+{0xEC10,0xD8,0x01},
+{0xEC11,0x0B,0x01},
+{0xEC12,0xFC,0x01},
+{0xEC13,0xFE,0x01},
+{0xEC14,0x3D,0x01},
+{0xEC15,0xC0,0x01},
+{0xEC16,0xFF,0x01},
+{0xEC17,0xFF,0x01},
+{0xEC18,0x03,0x01},
+{0xEC19,0xFC,0x01},
+{0xEC1A,0x82,0x01},
+{0xEC1B,0xBE,0x01},
+{0xEC1C,0xA0,0x01},
+{0xEC1D,0x6F,0x01},
+{0xEC1E,0xF8,0x01},
+{0xEC1F,0x1B,0x01},
+{0xEC20,0xFE,0x01},
+{0xEC21,0x83,0x01},
+{0xEC22,0xBF,0x01},
+{0xEC23,0xE0,0x01},
+{0xEC24,0x0F,0x01},
+{0xEC25,0x10,0x01},
+{0xEC26,0x00,0x01},
+{0xEC27,0x00,0x01},
+{0xEC28,0x82,0x01},
+{0xEC29,0xC0,0x01},
+{0xEC2A,0x60,0x01},
+{0xEC2B,0x30,0x01},
+{0xEC2C,0x18,0x01},
+{0xEC2D,0x20,0x01},
+{0xEC2E,0x04,0x01},
+{0xEC2F,0x08,0x01},
+{0xEC30,0x81,0x01},
+{0xEC31,0x21,0x01},
+{0xEC32,0x30,0x01},
+{0xEC33,0x08,0x01},
+{0xEC34,0x08,0x01},
+{0xEC35,0x08,0x01},
+{0xEC36,0x82,0x01},
+{0xEC37,0x01,0x01},
+{0xEC38,0x81,0x01},
+{0xEC39,0x50,0x01},
+{0xEC3A,0x08,0x01},
+{0xEC3B,0x14,0x01},
+{0xEC3C,0x02,0x01},
+{0xEC3D,0x09,0x01},
+{0xEC3E,0x41,0x01},
+{0xEC3F,0x42,0x01},
+{0xEC40,0x70,0x01},
+{0xEC41,0x20,0x01},
+{0xEC42,0x0C,0x01},
+{0xEC43,0x06,0x01},
+{0xEC44,0x84,0x01},
+{0xEC45,0x42,0x01},
+{0xEC46,0xE1,0x01},
+{0xEC47,0x40,0x01},
+{0xEC48,0x38,0x01},
+{0xEC49,0x1C,0x01},
+{0xEC4A,0x0C,0x01},
+{0xEC4B,0x07,0x01},
+{0xEC4C,0x03,0x01},
+{0xEC4D,0xA2,0x01},
+{0xEC4E,0x80,0x01},
+{0xEC4F,0x28,0x01},
+{0xEC50,0x18,0x01},
+{0xEC51,0x10,0x01},
+{0xEC52,0x87,0x01},
+{0xEC53,0x43,0x01},
+{0xEC54,0x61,0x01},
+{0xEC55,0x41,0x01},
+{0xEC56,0x48,0x01},
+{0xEC57,0x14,0x01},
+{0xEC58,0x10,0x01},
+{0xEC59,0x07,0x01},
+{0xEC5A,0xC2,0x01},
+{0xEC5B,0x81,0x01},
+{0xEC5C,0x80,0x01},
+{0xEC5D,0x30,0x01},
+{0xEC5E,0x20,0x01},
+{0xEC5F,0x0C,0x01},
+{0xEC60,0x87,0x01},
+{0xEC61,0x83,0x01},
+{0xEC62,0xC1,0x01},
+{0xEC63,0x40,0x01},
+{0xEC64,0x38,0x01},
+{0xEC65,0x14,0x01},
+{0xEC66,0x0A,0x01},
+{0xEC67,0x07,0x01},
+{0xEC68,0xC3,0x01},
+{0xEC69,0xC1,0x01},
+{0xEC6A,0x70,0x01},
+{0xEC6B,0x30,0x01},
+{0xEC6C,0x20,0x01},
+{0xEC6D,0x0C,0x01},
+{0xEC6E,0x08,0x01},
+{0xEC6F,0xC3,0x01},
+{0xEC70,0xE1,0x01},
+{0xEC71,0x60,0x01},
+{0xEC72,0x30,0x01},
+{0xEC73,0x10,0x01},
+{0xEC74,0x0E,0x01},
+{0xEC75,0x85,0x01},
+{0xEC76,0xC2,0x01},
+{0xEC77,0xC1,0x01},
+{0xEC78,0x70,0x01},
+{0xEC79,0x30,0x01},
+{0xEC7A,0x1C,0x01},
+{0xEC7B,0x0C,0x01},
+
+//SHD1(from CO1)
+{0xED02,0xE6,0x01},
+{0xED03,0x61,0x01},
+{0xED04,0x92,0x01},
+{0xED05,0x7C,0x01},
+{0xED06,0xBE,0x01},
+{0xED07,0xB4,0x01},
+{0xED08,0x9E,0x01},
+{0xED09,0x2C,0x01},
+{0xED0A,0x75,0x01},
+{0xED0B,0x47,0x01},
+{0xED0C,0x49,0x01},
+{0xED0D,0xD7,0x01},
+{0xED0E,0x61,0x01},
+{0xED0F,0x12,0x01},
+{0xED10,0x76,0x01},
+{0xED11,0xA8,0x01},
+{0xED12,0x34,0x01},
+{0xED13,0x1E,0x01},
+{0xED14,0x31,0x01},
+{0xED15,0xA1,0x01},
+{0xED16,0xC7,0x01},
+{0xED17,0x4C,0x01},
+{0xED18,0xDE,0x01},
+{0xED19,0xC1,0x01},
+{0xED1A,0xD2,0x01},
+{0xED1B,0x77,0x01},
+{0xED1C,0x76,0x01},
+{0xED1D,0x94,0x01},
+{0xED1E,0x9C,0x01},
+{0xED1F,0x10,0x01},
+{0xED20,0xC9,0x01},
+{0xED21,0xC6,0x01},
+{0xED22,0x40,0x01},
+{0xED23,0xA2,0x01},
+{0xED24,0x99,0x01},
+{0xED25,0x8F,0x01},
+{0xED26,0x66,0x01},
+{0xED27,0xDC,0x01},
+{0xED28,0xF3,0x01},
+{0xED29,0x19,0x01},
+{0xED2A,0xFC,0x01},
+{0xED2B,0xB0,0x01},
+{0xED2C,0xA6,0x01},
+{0xED2D,0x41,0x01},
+{0xED2E,0xC1,0x01},
+{0xED2F,0x49,0x01},
+{0xED30,0x91,0x01},
+{0xED31,0x75,0x01},
+{0xED32,0x8C,0x01},
+{0xED33,0x74,0x01},
+{0xED34,0x1C,0x01},
+{0xED35,0x0B,0x01},
+{0xED36,0x91,0x01},
+{0xED37,0x86,0x01},
+{0xED38,0x3D,0x01},
+{0xED39,0x87,0x01},
+{0xED3A,0x39,0x01},
+{0xED3B,0x4E,0x01},
+{0xED3C,0x5C,0x01},
+{0xED3D,0x50,0x01},
+{0xED3E,0x83,0x01},
+{0xED3F,0x16,0x01},
+{0xED40,0xCF,0x01},
+{0xED41,0xBC,0x01},
+{0xED42,0x45,0x01},
+{0xED43,0x35,0x01},
+{0xED44,0x83,0x01},
+{0xED45,0x41,0x01},
+{0xED46,0xCE,0x01},
+{0xED47,0x67,0x01},
+{0xED48,0xE8,0x01},
+{0xED49,0x33,0x01},
+{0xED4A,0x1C,0x01},
+{0xED4B,0x16,0x01},
+{0xED4C,0xC1,0x01},
+{0xED4D,0x86,0x01},
+{0xED4E,0x3E,0x01},
+{0xED4F,0x83,0x01},
+{0xED50,0xC1,0x01},
+{0xED51,0x0D,0x01},
+{0xED52,0x57,0x01},
+{0xED53,0x02,0x01},
+{0xED54,0x23,0x01},
+{0xED55,0x14,0x01},
+{0xED56,0xAE,0x01},
+{0xED57,0xE4,0x01},
+{0xED58,0x44,0x01},
+{0xED59,0x2A,0x01},
+{0xED5A,0x43,0x01},
+{0xED5B,0xF9,0x01},
+{0xED5C,0xCA,0x01},
+{0xED5D,0x56,0x01},
+{0xED5E,0x0C,0x01},
+{0xED5F,0x03,0x01},
+{0xED60,0x98,0x01},
+{0xED61,0xE2,0x01},
+{0xED62,0xA8,0x01},
+{0xED63,0x26,0x01},
+{0xED64,0x41,0x01},
+{0xED65,0x9E,0x01},
+{0xED66,0xC1,0x01},
+{0xED67,0xCE,0x01},
+{0xED68,0x59,0x01},
+{0xED69,0x1C,0x01},
+{0xED6A,0xB3,0x01},
+{0xED6B,0x93,0x01},
+{0xED6C,0xA7,0x01},
+{0xED6D,0x74,0x01},
+{0xED6E,0x04,0x01},
+{0xED6F,0x25,0x01},
+{0xED70,0x13,0x01},
+{0xED71,0xD9,0x01},
+{0xED72,0xC8,0x01},
+{0xED73,0x47,0x01},
+{0xED74,0x54,0x01},
+{0xED75,0xD2,0x01},
+{0xED76,0x93,0x01},
+{0xED77,0xAA,0x01},
+{0xED78,0x98,0x01},
+{0xED79,0xE5,0x01},
+{0xED7A,0x32,0x01},
+{0xED7B,0x9A,0x01},
+{0xED7C,0x29,0x01},
+{0xED7D,0xCF,0x01},
+{0xED7E,0x64,0x01},
+{0xED7F,0x8E,0x01},
+{0xED80,0x73,0x01},
+{0xED81,0x95,0x01},
+{0xED82,0xBB,0x01},
+{0xED83,0xA4,0x01},
+{0xED84,0xA4,0x01},
+{0xED85,0x26,0x01},
+{0xED86,0x0A,0x01},
+{0xED87,0x59,0x01},
+{0xED88,0x08,0x01},
+{0xED89,0x40,0x01},
+{0xED8A,0x00,0x01},
+{0xED8B,0xC2,0x01},
+{0xED8C,0x10,0x01},
+{0xED8D,0x88,0x01},
+{0xED8E,0xB0,0x01},
+{0xED8F,0x84,0x01},
+{0xED90,0x27,0x01},
+{0xED91,0x59,0x01},
+{0xED92,0xF1,0x01},
+{0xED93,0x0B,0x01},
+{0xED94,0x64,0x01},
+{0xED95,0xA2,0x01},
+{0xED96,0x43,0x01},
+{0xED97,0x99,0x01},
+{0xED98,0xE4,0x01},
+{0xED99,0x68,0x01},
+{0xED9A,0x25,0x01},
+{0xED9B,0x2F,0x01},
+{0xED9C,0x2B,0x01},
+{0xED9D,0xB1,0x01},
+{0xED9E,0xC9,0x01},
+{0xED9F,0x42,0x01},
+{0xEDA0,0x18,0x01},
+{0xEDA1,0x32,0x01},
+{0xEDA2,0x90,0x01},
+{0xEDA3,0x80,0x01},
+{0xEDA4,0x3C,0x01},
+{0xEDA5,0x24,0x01},
+{0xEDA6,0x22,0x01},
+{0xEDA7,0x2F,0x01},
+{0xEDA8,0xF1,0x01},
+{0xEDA9,0x09,0x01},
+{0xEDAA,0x57,0x01},
+{0xEDAB,0x00,0x01},
+{0xEDAC,0x53,0x01},
+{0xEDAD,0x99,0x01},
+{0xEDAE,0xEA,0x01},
+{0xEDAF,0x90,0x01},
+{0xEDB0,0xC6,0x01},
+{0xEDB1,0x3B,0x01},
+{0xEDB2,0x6D,0x01},
+{0xEDB3,0x99,0x01},
+{0xEDB4,0x4C,0x01},
+{0xEDB5,0x50,0x01},
+{0xEDB6,0xA4,0x01},
+{0xEDB7,0x32,0x01},
+{0xEDB8,0x12,0x01},
+{0xEDB9,0x94,0x01},
+{0xEDBA,0x64,0x01},
+{0xEDBB,0xA4,0x01},
+{0xEDBC,0x23,0x01},
+{0xEDBD,0x25,0x01},
+{0xEDBE,0x71,0x01},
+{0xEDBF,0x49,0x01},
+{0xEDC0,0x51,0x01},
+{0xEDC1,0xB2,0x01},
+{0xEDC2,0x02,0x01},
+{0xEDC3,0x17,0x01},
+{0xEDC4,0xCD,0x01},
+{0xEDC5,0x98,0x01},
+{0xEDC6,0x86,0x01},
+{0xEDC7,0x3D,0x01},
+{0xEDC8,0xBC,0x01},
+{0xEDC9,0x01,0x01},
+{0xEDCA,0x50,0x01},
+{0xEDCB,0x63,0x01},
+{0xEDCC,0x80,0x01},
+{0xEDCD,0x63,0x01},
+{0xEDCE,0x16,0x01},
+{0xEDCF,0xC3,0x01},
+{0xEDD0,0x2C,0x01},
+{0xEDD1,0x25,0x01},
+{0xEDD2,0x2C,0x01},
+{0xEDD3,0x43,0x01},
+{0xEDD4,0xB1,0x01},
+{0xEDD5,0x4A,0x01},
+{0xEDD6,0x53,0x01},
+{0xEDD7,0xCC,0x01},
+{0xEDD8,0x82,0x01},
+{0xEDD9,0x96,0x01},
+{0xEDDA,0xC7,0x01},
+{0xEDDB,0x40,0x01},
+{0xEDDC,0xA6,0x01},
+{0xEDDD,0x39,0x01},
+{0xEDDE,0xBE,0x01},
+{0xEDDF,0x91,0x01},
+{0xEDE0,0xD0,0x01},
+{0xEDE1,0x75,0x01},
+{0xEDE2,0x54,0x01},
+{0xEDE3,0x34,0x01},
+{0xEDE4,0x1B,0x01},
+{0xEDE5,0xFC,0x01},
+{0xEDE6,0x4C,0x01},
+{0xEDE7,0x46,0x01},
+{0xEDE8,0x39,0x01},
+{0xEDE9,0x7D,0x01},
+{0xEDEA,0x71,0x01},
+{0xEDEB,0x8D,0x01},
+{0xEDEC,0x5D,0x01},
+{0xEDED,0x46,0x01},
+{0xEDEE,0xE3,0x01},
+{0xEDEF,0x17,0x01},
+{0xEDF0,0xD9,0x01},
+{0xEDF1,0x50,0x01},
+{0xEDF2,0x86,0x01},
+{0xEDF3,0x3A,0x01},
+{0xEDF4,0xB3,0x01},
+{0xEDF5,0x09,0x01},
+{0xEDF6,0x50,0x01},
+{0xEDF7,0x76,0x01},
+{0xEDF8,0x6A,0x01},
+{0xEDF9,0xF4,0x01},
+{0xEDFA,0x1E,0x01},
+{0xEDFB,0x25,0x01},
+{0xEDFC,0x61,0x01},
+{0xEDFD,0x67,0x01},
+{0xEDFE,0x45,0x01},
+{0xEDFF,0xC0,0x01},
+{0xEE00,0x69,0x01},
+{0xEE01,0xD0,0x01},
+{0xEE02,0x6B,0x01},
+{0xEE03,0xF6,0x01},
+{0xEE04,0x93,0x01},
+{0xEE05,0x9A,0x01},
+{0xEE06,0xFA,0x01},
+{0xEE07,0xB8,0x01},
+{0xEE08,0x26,0x01},
+{0xEE09,0x40,0x01},
+{0xEE0A,0xC0,0x01},
+{0xEE0B,0xB9,0x01},
+{0xEE0C,0xD0,0x01},
+{0xEE0D,0x75,0x01},
+{0xEE0E,0x6E,0x01},
+{0xEE0F,0xE4,0x01},
+{0xEE10,0x9E,0x01},
+{0xEE11,0x2D,0x01},
+{0xEE12,0xE1,0x01},
+{0xEE13,0xA7,0x01},
+{0xEE14,0x49,0x01},
+{0xEE15,0xFD,0x01},
+{0xEE16,0xB9,0x01},
+{0xEE17,0x52,0x01},
+{0xEE18,0x7C,0x01},
+{0xEE19,0x98,0x01},
+{0xEE1A,0x64,0x01},
+{0xEE1B,0x1E,0x01},
+{0xEE1C,0x22,0x01},
+{0xEE1D,0x89,0x01},
+{0xEE1E,0xA7,0x01},
+{0xEE1F,0x48,0x01},
+{0xEE20,0xE4,0x01},
+{0xEE21,0x49,0x01},
+{0xEE22,0x12,0x01},
+{0xEE23,0x7D,0x01},
+{0xEE24,0xB4,0x01},
+{0xEE25,0xB4,0x01},
+{0xEE26,0x1F,0x01},
+{0xEE27,0x31,0x01},
+{0xEE28,0xC5,0x01},
+{0xEE29,0x47,0x01},
+{0xEE2A,0x4B,0x01},
+{0xEE2B,0xC2,0x01},
+{0xEE2C,0x19,0x01},
+{0xEE2D,0x0F,0x01},
+{0xEE2E,0x73,0x01},
+{0xEE2F,0xE2,0x01},
+{0xEE30,0x13,0x01},
+{0xEE31,0x1C,0x01},
+{0xEE32,0xF5,0x01},
+{0xEE33,0xE0,0x01},
+{0xEE34,0xC6,0x01},
+{0xEE35,0x3B,0x01},
+{0xEE36,0xB6,0x01},
+{0xEE37,0xB1,0x01},
+{0xEE38,0xCE,0x01},
+{0xEE39,0x6D,0x01},
+{0xEE3A,0xB8,0x01},
+{0xEE3B,0xF3,0x01},
+{0xEE3C,0x9B,0x01},
+{0xEE3D,0xF2,0x01},
+{0xEE3E,0x18,0x01},
+{0xEE3F,0x27,0x01},
+{0xEE40,0x3D,0x01},
+{0xEE41,0xBF,0x01},
+{0xEE42,0xE9,0x01},
+{0xEE43,0xCE,0x01},
+{0xEE44,0x6E,0x01},
+{0xEE45,0xBA,0x01},
+{0xEE46,0x83,0x01},
+{0xEE47,0x9A,0x01},
+{0xEE48,0xE4,0x01},
+{0xEE49,0x50,0x01},
+{0xEE4A,0x66,0x01},
+{0xEE4B,0x36,0x01},
+{0xEE4C,0x8A,0x01},
+{0xEE4D,0x29,0x01},
+{0xEE4E,0x4D,0x01},
+{0xEE4F,0x61,0x01},
+{0xEE50,0x3A,0x01},
+{0xEE51,0xA3,0x01},
+{0xEE52,0x18,0x01},
+{0xEE53,0xD2,0x01},
+{0xEE54,0x50,0x01},
+{0xEE55,0x26,0x01},
+{0xEE56,0x36,0x01},
+{0xEE57,0xA8,0x01},
+{0xEE58,0x21,0x01},
+{0xEE59,0xCE,0x01},
+{0xEE5A,0x6E,0x01},
+{0xEE5B,0xB2,0x01},
+{0xEE5C,0x03,0x01},
+{0xEE5D,0x9A,0x01},
+{0xEE5E,0xE0,0x01},
+{0xEE5F,0x1C,0x01},
+{0xEE60,0x46,0x01},
+{0xEE61,0x34,0x01},
+{0xEE62,0x72,0x01},
+{0xEE63,0x41,0x01},
+{0xEE64,0x8C,0x01},
+{0xEE65,0x58,0x01},
+{0xEE66,0xE8,0x01},
+{0xEE67,0xC2,0x01},
+{0xEE68,0x95,0x01},
+{0xEE69,0xB5,0x01},
+{0xEE6A,0x88,0x01},
+{0xEE6B,0x65,0x01},
+{0xEE6C,0x2E,0x01},
+{0xEE6D,0x72,0x01},
+{0xEE6E,0x39,0x01},
+{0xEE6F,0x8C,0x01},
+{0xEE70,0x62,0x01},
+{0xEE71,0x48,0x01},
+{0xEE72,0x83,0x01},
+{0xEE73,0x1A,0x01},
+{0xEE74,0xE4,0x01},
+{0xEE75,0x28,0x01},
+{0xEE76,0x06,0x01},
+{0xEE77,0x35,0x01},
+{0xEE78,0x6A,0x01},
+{0xEE79,0xF9,0x01},
+{0xEE7A,0x4B,0x01},
+{0xEE7B,0x53,0x01},
+{0xEE7C,0xB8,0x01},
+{0xEE7D,0x92,0x01},
+{0xEE7E,0x13,0x01},
+{0xEE7F,0xA2,0x01},
+{0xEE80,0xCC,0x01},
+{0xEE81,0x64,0x01},
+{0xEE82,0x27,0x01},
+{0xEE83,0x3B,0x01},
+{0xEE84,0x29,0x01},
+{0xEE85,0x0A,0x01},
+{0xEE86,0x54,0x01},
+{0xEE87,0xBC,0x01},
+{0xEE88,0xF2,0x01},
+{0xEE89,0x96,0x01},
+{0xEE8A,0xC1,0x01},
+{0xEE8B,0x40,0x01},
+{0xEE8C,0xA6,0x01},
+{0xEE8D,0x35,0x01},
+{0xEE8E,0x7A,0x01},
+{0xEE8F,0xB1,0x01},
+{0xEE90,0x8C,0x01},
+{0xEE91,0x54,0x01},
+{0xEE92,0xC8,0x01},
+{0xEE93,0xF2,0x01},
+{0xEE94,0x92,0x01},
+{0xEE95,0x9D,0x01},
+{0xEE96,0x64,0x01},
+{0xEE97,0xE4,0x01},
+{0xEE98,0x23,0x01},
+{0xEE99,0x13,0x01},
+{0xEE9A,0xA9,0x01},
+{0xEE9B,0x48,0x01},
+{0xEE9C,0x47,0x01},
+{0xEE9D,0x40,0x01},
+{0xEE9E,0x42,0x01},
+{0xEE9F,0x13,0x01},
+{0xEEA0,0x9F,0x01},
+{0xEEA1,0x58,0x01},
+{0xEEA2,0xE5,0x01},
+{0xEEA3,0x2C,0x01},
+{0xEEA4,0x7F,0x01},
+{0xEEA5,0xD9,0x01},
+{0xEEA6,0x8C,0x01},
+{0xEEA7,0x5B,0x01},
+{0xEEA8,0x12,0x01},
+{0xEEA9,0x43,0x01},
+{0xEEAA,0x14,0x01},
+{0xEEAB,0xAA,0x01},
+{0xEEAC,0x80,0x01},
+{0xEEAD,0x04,0x01},
+{0xEEAE,0x25,0x01},
+{0xEEAF,0x06,0x01},
+{0xEEB0,0x51,0x01},
+{0xEEB1,0x08,0x01},
+{0xEEB2,0x40,0x01},
+{0xEEB3,0x00,0x01},
+{0xEEB4,0xB2,0x01},
+{0xEEB5,0x10,0x01},
+{0xEEB6,0x86,0x01},
+{0xEEB7,0x98,0x01},
+{0xEEB8,0x64,0x01},
+{0xEEB9,0x25,0x01},
+{0xEEBA,0x4A,0x01},
+{0xEEBB,0xB9,0x01},
+{0xEEBC,0x0A,0x01},
+{0xEEBD,0x5D,0x01},
+{0xEEBE,0x1C,0x01},
+{0xEEBF,0x13,0x01},
+{0xEEC0,0x97,0x01},
+{0xEEC1,0xC4,0x01},
+{0xEEC2,0x18,0x01},
+{0xEEC3,0x85,0x01},
+{0xEEC4,0x2A,0x01},
+{0xEEC5,0x21,0x01},
+{0xEEC6,0x41,0x01},
+{0xEEC7,0xC9,0x01},
+{0xEEC8,0x41,0x01},
+{0xEEC9,0x12,0x01},
+{0xEECA,0x02,0x01},
+{0xEECB,0x10,0x01},
+{0xEECC,0x80,0x01},
+{0xEECD,0x2C,0x01},
+{0xEECE,0x64,0x01},
+{0xEECF,0x21,0x01},
+{0xEED0,0x27,0x01},
+{0xEED1,0x61,0x01},
+{0xEED2,0xC9,0x01},
+{0xEED3,0x52,0x01},
+{0xEED4,0xB0,0x01},
+{0xEED5,0x42,0x01},
+{0xEED6,0x17,0x01},
+{0xEED7,0xC8,0x01},
+{0xEED8,0x04,0x01},
+{0xEED9,0xE6,0x01},
+{0xEEDA,0x32,0x01},
+{0xEEDB,0x58,0x01},
+{0xEEDC,0x29,0x01},
+{0xEEDD,0xCB,0x01},
+{0xEEDE,0x4C,0x01},
+{0xEEDF,0x74,0x01},
+{0xEEE0,0x92,0x01},
+{0xEEE1,0x91,0x01},
+{0xEEE2,0x8E,0x01},
+{0xEEE3,0x48,0x01},
+{0xEEE4,0x84,0x01},
+{0xEEE5,0x22,0x01},
+{0xEEE6,0x1D,0x01},
+{0xEEE7,0x01,0x01},
+{0xEEE8,0xC9,0x01},
+{0xEEE9,0x4D,0x01},
+{0xEEEA,0x7E,0x01},
+{0xEEEB,0x82,0x01},
+{0xEEEC,0x15,0x01},
+{0xEEED,0xB5,0x01},
+{0xEEEE,0x04,0x01},
+{0xEEEF,0xE6,0x01},
+{0xEEF0,0x33,0x01},
+{0xEEF1,0x99,0x01},
+{0xEEF2,0x69,0x01},
+{0xEEF3,0x0D,0x01},
+{0xEEF4,0x5D,0x01},
+{0xEEF5,0x06,0x01},
+{0xEEF6,0x33,0x01},
+{0xEEF7,0x15,0x01},
+{0xEEF8,0xAF,0x01},
+{0xEEF9,0xEC,0x01},
+{0xEEFA,0xA4,0x01},
+{0xEEFB,0x28,0x01},
+{0xEEFC,0x35,0x01},
+{0xEEFD,0xE9,0x01},
+{0xEEFE,0x09,0x01},
+{0xEEFF,0x4F,0x01},
+{0xEF00,0x8E,0x01},
+{0xEF01,0x02,0x01},
+{0xEF02,0x95,0x01},
+{0xEF03,0xB1,0x01},
+{0xEF04,0xC4,0x01},
+{0xEF05,0x25,0x01},
+{0xEF06,0x31,0x01},
+{0xEF07,0x94,0x01},
+{0xEF08,0xB1,0x01},
+{0xEF09,0x4D,0x01},
+{0xEF0A,0x6C,0x01},
+{0xEF0B,0x94,0x01},
+{0xEF0C,0x43,0x01},
+{0xEF0D,0x99,0x01},
+{0xEF0E,0xD4,0x01},
+{0xEF0F,0xEC,0x01},
+{0xEF10,0xC5,0x01},
+{0xEF11,0x31,0x01},
+{0xEF12,0x69,0x01},
+{0xEF13,0xC9,0x01},
+{0xEF14,0x0B,0x01},
+{0xEF15,0x58,0x01},
+{0xEF16,0xE6,0x01},
+{0xEF17,0x52,0x01},
+{0xEF18,0x16,0x01},
+{0xEF19,0xBE,0x01},
+{0xEF1A,0xD4,0x01},
+{0xEF1B,0x45,0x01},
+{0xEF1C,0x32,0x01},
+{0xEF1D,0x8E,0x01},
+{0xEF1E,0x79,0x01},
+{0xEF1F,0x4D,0x01},
+{0xEF20,0x6A,0x01},
+{0xEF21,0xA4,0x01},
+{0xEF22,0x83,0x01},
+{0xEF23,0x1C,0x01},
+{0xEF24,0xF2,0x01},
+{0xEF25,0xDC,0x01},
+{0xEF26,0x26,0x01},
+{0xEF27,0x3A,0x01},
+{0xEF28,0xA3,0x01},
+{0xEF29,0xE1,0x01},
+{0xEF2A,0x4D,0x01},
+{0xEF2B,0x65,0x01},
+{0xEF2C,0x5C,0x01},
+{0xEF2D,0xC3,0x01},
+{0xEF2E,0x98,0x01},
+{0xEF2F,0xD4,0x01},
+{0xEF30,0x3C,0x01},
+{0xEF31,0xE6,0x01},
+{0xEF32,0x35,0x01},
+{0xEF33,0x9D,0x01},
+{0xEF34,0x09,0x01},
+{0xEF35,0x8E,0x01},
+{0xEF36,0x6B,0x01},
+{0xEF37,0xAC,0x01},
+{0xEF38,0xE3,0x01},
+{0xEF39,0x9B,0x01},
+{0xEF3A,0xF4,0x01},
+{0xEF3B,0x34,0x01},
+{0xEF3C,0x07,0x01},
+{0xEF3D,0x3E,0x01},
+{0xEF3E,0xDA,0x01},
+{0xEF3F,0xC1,0x01},
+{0xEF40,0x8F,0x01},
+{0xEF41,0x74,0x01},
+{0xEF42,0xEA,0x01},
+{0xEF43,0x13,0x01},
+{0xEF44,0x9C,0x01},
+{0xEF45,0xF4,0x01},
+{0xEF46,0xF0,0x01},
+{0xEF47,0xA6,0x01},
+{0xEF48,0x3C,0x01},
+{0xEF49,0xC0,0x01},
+{0xEF4A,0x49,0x01},
+{0xEF4B,0x0F,0x01},
+{0xEF4C,0x72,0x01},
+{0xEF4D,0xEA,0x01},
+{0xEF4E,0xD3,0x01},
+{0xEF4F,0x9C,0x01},
+{0xEF50,0xFE,0x01},
+{0xEF51,0x04,0x01},
+{0xEF52,0xA7,0x01},
+{0xEF53,0x3D,0x01},
+
+//SHD2 CW+TL84 33:66
+
+{0xED00,0x9191,0x02},//
+{0xEF54,0x21,0x01},
+{0xEF55,0x92,0x01},
+{0xEF56,0xD1,0x01},
+{0xEF57,0x8A,0x01},
+{0xEF58,0x3E,0x01},
+{0xEF59,0xF4,0x01},
+{0xEF5A,0xA1,0x01},
+{0xEF5B,0x10,0x01},
+{0xEF5C,0xB9,0x01},
+{0xEF5D,0x48,0x01},
+{0xEF5E,0x46,0x01},
+{0xEF5F,0x1F,0x01},
+{0xEF60,0x82,0x01},
+{0xEF61,0x10,0x01},
+{0xEF62,0x7E,0x01},
+{0xEF63,0xBC,0x01},
+{0xEF64,0xC3,0x01},
+{0xEF65,0x1C,0x01},
+{0xEF66,0xE3,0x01},
+{0xEF67,0x38,0x01},
+{0xEF68,0xC7,0x01},
+{0xEF69,0x3B,0x01},
+{0xEF6A,0xF7,0x01},
+{0xEF6B,0x71,0x01},
+{0xEF6C,0x90,0x01},
+{0xEF6D,0x7B,0x01},
+{0xEF6E,0x8E,0x01},
+{0xEF6F,0x53,0x01},
+{0xEF70,0x1A,0x01},
+{0xEF71,0xC5,0x01},
+{0xEF72,0x04,0x01},
+{0xEF73,0x46,0x01},
+{0xEF74,0x31,0x01},
+{0xEF75,0xA2,0x01},
+{0xEF76,0x39,0x01},
+{0xEF77,0x0E,0x01},
+{0xEF78,0x7E,0x01},
+{0xEF79,0x9A,0x01},
+{0xEF7A,0xA3,0x01},
+{0xEF7B,0x99,0x01},
+{0xEF7C,0xB5,0x01},
+{0xEF7D,0x34,0x01},
+{0xEF7E,0x85,0x01},
+{0xEF7F,0x28,0x01},
+{0xEF80,0x4D,0x01},
+{0xEF81,0x61,0x01},
+{0xEF82,0x8B,0x01},
+{0xEF83,0x67,0x01},
+{0xEF84,0xB0,0x01},
+{0xEF85,0x53,0x01},
+{0xEF86,0x1B,0x01},
+{0xEF87,0xBB,0x01},
+{0xEF88,0x08,0x01},
+{0xEF89,0x45,0x01},
+{0xEF8A,0x24,0x01},
+{0xEF8B,0x17,0x01},
+{0xEF8C,0x11,0x01},
+{0xEF8D,0x09,0x01},
+{0xEF8E,0x51,0x01},
+{0xEF8F,0xF2,0x01},
+{0xEF90,0xA2,0x01},
+{0xEF91,0x9B,0x01},
+{0xEF92,0xD3,0x01},
+{0xEF93,0x90,0x01},
+{0xEF94,0xC5,0x01},
+{0xEF95,0x25,0x01},
+{0xEF96,0x0A,0x01},
+{0xEF97,0x01,0x01},
+{0xEF98,0x48,0x01},
+{0xEF99,0x43,0x01},
+{0xEF9A,0x62,0x01},
+{0xEF9B,0x52,0x01},
+{0xEF9C,0x16,0x01},
+{0xEF9D,0xD5,0x01},
+{0xEF9E,0x9C,0x01},
+{0xEF9F,0xC6,0x01},
+{0xEFA0,0x2C,0x01},
+{0xEFA1,0x2F,0x01},
+{0xEFA2,0x51,0x01},
+{0xEFA3,0x48,0x01},
+{0xEFA4,0x40,0x01},
+{0xEFA5,0x1C,0x01},
+{0xEFA6,0x22,0x01},
+{0xEFA7,0x93,0x01},
+{0xEFA8,0xB3,0x01},
+{0xEFA9,0xB8,0x01},
+{0xEFAA,0x46,0x01},
+{0xEFAB,0x37,0x01},
+{0xEFAC,0x7A,0x01},
+{0xEFAD,0x21,0x01},
+{0xEFAE,0x4A,0x01},
+{0xEFAF,0x48,0x01},
+{0xEFB0,0x30,0x01},
+{0xEFB1,0x52,0x01},
+{0xEFB2,0x12,0x01},
+{0xEFB3,0xA4,0x01},
+{0xEFB4,0xF0,0x01},
+{0xEFB5,0xE5,0x01},
+{0xEFB6,0x37,0x01},
+{0xEFB7,0xD6,0x01},
+{0xEFB8,0xF9,0x01},
+{0xEFB9,0x8C,0x01},
+{0xEFBA,0x5B,0x01},
+{0xEFBB,0x9E,0x01},
+{0xEFBC,0x62,0x01},
+{0xEFBD,0x14,0x01},
+{0xEFBE,0xA9,0x01},
+{0xEFBF,0xC8,0x01},
+{0xEFC0,0xA5,0x01},
+{0xEFC1,0x34,0x01},
+{0xEFC2,0xE0,0x01},
+{0xEFC3,0xD1,0x01},
+{0xEFC4,0x8F,0x01},
+{0xEFC5,0x73,0x01},
+{0xEFC6,0x4C,0x01},
+{0xEFC7,0xE3,0x01},
+{0xEFC8,0x18,0x01},
+{0xEFC9,0xC2,0x01},
+{0xEFCA,0x3C,0x01},
+{0xEFCB,0x46,0x01},
+{0xEFCC,0x35,0x01},
+{0xEFCD,0xD2,0x01},
+{0xEFCE,0x09,0x01},
+{0xEFCF,0x90,0x01},
+{0xEFD0,0x85,0x01},
+{0xEFD1,0xF6,0x01},
+{0xEFD2,0x03,0x01},
+{0xEFD3,0x1E,0x01},
+{0xEFD4,0xE7,0x01},
+{0xEFD5,0x20,0x01},
+{0xEFD6,0x27,0x01},
+{0xEFD7,0x3A,0x01},
+{0xEFD8,0xE4,0x01},
+{0xEFD9,0x01,0x01},
+{0xEFDA,0x90,0x01},
+{0xEFDB,0x87,0x01},
+{0xEFDC,0x30,0x01},
+{0xEFDD,0x04,0x01},
+{0xEFDE,0x22,0x01},
+{0xEFDF,0x0B,0x01},
+{0xEFE0,0x2D,0x01},
+{0xEFE1,0x28,0x01},
+{0xEFE2,0x41,0x01},
+{0xEFE3,0x10,0x01},
+{0xEFE4,0xDA,0x01},
+{0xEFE5,0x90,0x01},
+{0xEFE6,0x88,0x01},
+{0xEFE7,0x3C,0x01},
+{0xEFE8,0x04,0x01},
+{0xEFE9,0x00,0x01},
+{0xEFEA,0x00,0x01},
+{0xEFEB,0x00,0x01},
+{0xEFEC,0x00,0x01},
+{0xEFED,0x00,0x01},
+
+
+
+//SHD3 D65+TL84 C01//
+{0xED00,0x9191,0x02},//
+{0xEFEE,0x12,0x01},
+{0xEFEF,0x42,0x01},
+{0xEFF0,0x51,0x01},
+{0xEFF1,0x89,0x01},
+{0xEFF2,0x38,0x01},
+{0xEFF3,0xD4,0x01},
+{0xEFF4,0x21,0x01},
+{0xEFF5,0x10,0x01},
+{0xEFF6,0xAD,0x01},
+{0xEFF7,0xA8,0x01},
+{0xEFF8,0x45,0x01},
+{0xEFF9,0x18,0x01},
+{0xEFFA,0x4A,0x01},
+{0xEFFB,0x50,0x01},
+{0xEFFC,0x7D,0x01},
+{0xEFFD,0xBA,0x01},
+{0xEFFE,0xD3,0x01},
+{0xEFFF,0x1C,0x01},
+{0xF000,0xE4,0x01},
+{0xF001,0x40,0x01},
+{0xF002,0x27,0x01},
+{0xF003,0x3C,0x01},
+{0xF004,0xF8,0x01},
+{0xF005,0x69,0x01},
+{0xF006,0x10,0x01},
+{0xF007,0x7B,0x01},
+{0xF008,0x8E,0x01},
+{0xF009,0x63,0x01},
+{0xF00A,0x1A,0x01},
+{0xF00B,0xC6,0x01},
+{0xF00C,0x10,0x01},
+{0xF00D,0xA6,0x01},
+{0xF00E,0x31,0x01},
+{0xF00F,0xA6,0x01},
+{0xF010,0x59,0x01},
+{0xF011,0x8E,0x01},
+{0xF012,0x7E,0x01},
+{0xF013,0x9A,0x01},
+{0xF014,0xB3,0x01},
+{0xF015,0x19,0x01},
+{0xF016,0xB6,0x01},
+{0xF017,0x38,0x01},
+{0xF018,0xA5,0x01},
+{0xF019,0x28,0x01},
+{0xF01A,0x4F,0x01},
+{0xF01B,0x79,0x01},
+{0xF01C,0xCB,0x01},
+{0xF01D,0x68,0x01},
+{0xF01E,0xBA,0x01},
+{0xF01F,0x53,0x01},
+{0xF020,0x9B,0x01},
+{0xF021,0xBB,0x01},
+{0xF022,0x0C,0x01},
+{0xF023,0x65,0x01},
+{0xF024,0x24,0x01},
+{0xF025,0x17,0x01},
+{0xF026,0x21,0x01},
+{0xF027,0xC9,0x01},
+{0xF028,0x51,0x01},
+{0xF029,0xFC,0x01},
+{0xF02A,0xF2,0x01},
+{0xF02B,0x9B,0x01},
+{0xF02C,0xD3,0x01},
+{0xF02D,0x94,0x01},
+{0xF02E,0xC5,0x01},
+{0xF02F,0x25,0x01},
+{0xF030,0x0A,0x01},
+{0xF031,0x01,0x01},
+{0xF032,0x48,0x01},
+{0xF033,0x43,0x01},
+{0xF034,0x66,0x01},
+{0xF035,0x92,0x01},
+{0xF036,0x96,0x01},
+{0xF037,0xD7,0x01},
+{0xF038,0xA0,0x01},
+{0xF039,0xE6,0x01},
+{0xF03A,0x2C,0x01},
+{0xF03B,0x2F,0x01},
+{0xF03C,0x51,0x01},
+{0xF03D,0x48,0x01},
+{0xF03E,0x40,0x01},
+{0xF03F,0x1E,0x01},
+{0xF040,0x42,0x01},
+{0xF041,0x93,0x01},
+{0xF042,0xB5,0x01},
+{0xF043,0xCC,0x01},
+{0xF044,0x46,0x01},
+{0xF045,0x37,0x01},
+{0xF046,0x7C,0x01},
+{0xF047,0x29,0x01},
+{0xF048,0x8A,0x01},
+{0xF049,0x48,0x01},
+{0xF04A,0x32,0x01},
+{0xF04B,0x72,0x01},
+{0xF04C,0x12,0x01},
+{0xF04D,0xA5,0x01},
+{0xF04E,0x00,0x01},
+{0xF04F,0xA6,0x01},
+{0xF050,0x38,0x01},
+{0xF051,0xD7,0x01},
+{0xF052,0x01,0x01},
+{0xF053,0x0D,0x01},
+{0xF054,0x5C,0x01},
+{0xF055,0xA2,0x01},
+{0xF056,0x82,0x01},
+{0xF057,0x94,0x01},
+{0xF058,0xAA,0x01},
+{0xF059,0xD8,0x01},
+{0xF05A,0x45,0x01},
+{0xF05B,0x35,0x01},
+{0xF05C,0xE5,0x01},
+{0xF05D,0xC9,0x01},
+{0xF05E,0xCF,0x01},
+{0xF05F,0x73,0x01},
+{0xF060,0x50,0x01},
+{0xF061,0x03,0x01},
+{0xF062,0x99,0x01},
+{0xF063,0xC3,0x01},
+{0xF064,0x4C,0x01},
+{0xF065,0xE6,0x01},
+{0xF066,0x35,0x01},
+{0xF067,0xD7,0x01},
+{0xF068,0x21,0x01},
+{0xF069,0x10,0x01},
+{0xF06A,0x84,0x01},
+{0xF06B,0xF2,0x01},
+{0xF06C,0x03,0x01},
+{0xF06D,0x9E,0x01},
+{0xF06E,0xE8,0x01},
+{0xF06F,0x2C,0x01},
+{0xF070,0xA7,0x01},
+{0xF071,0x3A,0x01},
+{0xF072,0xE8,0x01},
+{0xF073,0x11,0x01},
+{0xF074,0x90,0x01},
+{0xF075,0x87,0x01},
+{0xF076,0x18,0x01},
+{0xF077,0x94,0x01},
+{0xF078,0x21,0x01},
+{0xF079,0x09,0x01},
+{0xF07A,0x2D,0x01},
+{0xF07B,0x68,0x01},
+{0xF07C,0x41,0x01},
+{0xF07D,0x11,0x01},
+{0xF07E,0xDA,0x01},
+{0xF07F,0x10,0x01},
+{0xF080,0x88,0x01},
+{0xF081,0x2A,0x01},
+{0xF082,0x04,0x01},
+{0xF083,0x00,0x01},
+{0xF084,0x00,0x01},
+{0xF085,0x00,0x01},
+{0xF086,0x00,0x01},
+{0xF087,0x00,0x01},
+{0xF088,0xBE,0x01},
+{0xF089,0x51,0x01},
+{0xF08A,0x4E,0x01},
+{0xF08B,0x6F,0x01},
+{0xF08C,0x6C,0x01},
+{0xF08D,0x43,0x01},
+{0xF08E,0x1B,0x01},
+{0xF08F,0xDA,0x01},
+{0xF090,0xEC,0x01},
+{0xF091,0x46,0x01},
+{0xF092,0x38,0x01},
+{0xF093,0xBB,0x01},
+{0xF094,0xC1,0x01},
+{0xF095,0xCD,0x01},
+{0xF096,0x69,0x01},
+{0xF097,0x26,0x01},
+{0xF098,0x93,0x01},
+{0xF099,0x98,0x01},
+{0xF09A,0xC1,0x01},
+{0xF09B,0x20,0x01},
+{0xF09C,0x26,0x01},
+{0xF09D,0x32,0x01},
+{0xF09E,0xA5,0x01},
+{0xF09F,0xB1,0x01},
+{0xF0A0,0x8D,0x01},
+{0xF0A1,0x67,0x01},
+{0xF0A2,0x0E,0x01},
+{0xF0A3,0x23,0x01},
+{0xF0A4,0x97,0x01},
+{0xF0A5,0xB0,0x01},
+{0xF0A6,0x6C,0x01},
+{0xF0A7,0x25,0x01},
+{0xF0A8,0x2C,0x01},
+{0xF0A9,0x71,0x01},
+{0xF0AA,0x41,0x01},
+{0xF0AB,0x0C,0x01},
+{0xF0AC,0x69,0x01},
+{0xF0AD,0x14,0x01},
+{0xF0AE,0xB3,0x01},
+{0xF0AF,0x96,0x01},
+{0xF0B0,0xA6,0x01},
+{0xF0B1,0xE8,0x01},
+{0xF0B2,0x64,0x01},
+{0xF0B3,0x26,0x01},
+{0xF0B4,0x3A,0x01},
+{0xF0B5,0x79,0x01},
+{0xF0B6,0x4A,0x01},
+{0xF0B7,0x5B,0x01},
+{0xF0B8,0x18,0x01},
+{0xF0B9,0xA3,0x01},
+{0xF0BA,0x97,0x01},
+{0xF0BB,0xA9,0x01},
+{0xF0BC,0xBC,0x01},
+{0xF0BD,0x24,0x01},
+{0xF0BE,0x23,0x01},
+{0xF0BF,0x13,0x01},
+{0xF0C0,0xE1,0x01},
+{0xF0C1,0xC8,0x01},
+{0xF0C2,0x4C,0x01},
+{0xF0C3,0xAA,0x01},
+{0xF0C4,0xA2,0x01},
+{0xF0C5,0x97,0x01},
+{0xF0C6,0xB6,0x01},
+{0xF0C7,0x14,0x01},
+{0xF0C8,0x05,0x01},
+{0xF0C9,0x24,0x01},
+{0xF0CA,0x06,0x01},
+{0xF0CB,0x09,0x01},
+{0xF0CC,0xC8,0x01},
+{0xF0CD,0x42,0x01},
+{0xF0CE,0x48,0x01},
+{0xF0CF,0x82,0x01},
+{0xF0D0,0x14,0x01},
+{0xF0D1,0xB8,0x01},
+{0xF0D2,0xC0,0x01},
+{0xF0D3,0xE5,0x01},
+{0xF0D4,0x28,0x01},
+{0xF0D5,0x21,0x01},
+{0xF0D6,0x39,0x01},
+{0xF0D7,0x08,0x01},
+{0xF0D8,0x40,0x01},
+{0xF0D9,0x14,0x01},
+{0xF0DA,0x62,0x01},
+{0xF0DB,0x92,0x01},
+{0xF0DC,0xA4,0x01},
+{0xF0DD,0xC4,0x01},
+{0xF0DE,0x05,0x01},
+{0xF0DF,0x30,0x01},
+{0xF0E0,0x58,0x01},
+{0xF0E1,0xA1,0x01},
+{0xF0E2,0x49,0x01},
+{0xF0E3,0x46,0x01},
+{0xF0E4,0x22,0x01},
+{0xF0E5,0xB2,0x01},
+{0xF0E6,0x91,0x01},
+{0xF0E7,0x9A,0x01},
+{0xF0E8,0x58,0x01},
+{0xF0E9,0xA5,0x01},
+{0xF0EA,0x2F,0x01},
+{0xF0EB,0x96,0x01},
+{0xF0EC,0x99,0x01},
+{0xF0ED,0x8B,0x01},
+{0xF0EE,0x54,0x01},
+{0xF0EF,0x74,0x01},
+{0xF0F0,0x32,0x01},
+{0xF0F1,0x13,0x01},
+{0xF0F2,0x9D,0x01},
+{0xF0F3,0x38,0x01},
+{0xF0F4,0xC5,0x01},
+{0xF0F5,0x2D,0x01},
+{0xF0F6,0x90,0x01},
+{0xF0F7,0x59,0x01},
+{0xF0F8,0x4D,0x01},
+{0xF0F9,0x64,0x01},
+{0xF0FA,0xEE,0x01},
+{0xF0FB,0x62,0x01},
+{0xF0FC,0x16,0x01},
+{0xF0FD,0xAE,0x01},
+{0xF0FE,0x84,0x01},
+{0xF0FF,0x25,0x01},
+{0xF100,0x2E,0x01},
+{0xF101,0x8B,0x01},
+{0xF102,0x31,0x01},
+{0xF103,0xCD,0x01},
+{0xF104,0x6F,0x01},
+{0xF105,0x60,0x01},
+{0xF106,0xC3,0x01},
+{0xF107,0x19,0x01},
+{0xF108,0xC7,0x01},
+{0xF109,0x14,0x01},
+{0xF10A,0x26,0x01},
+{0xF10B,0x31,0x01},
+{0xF10C,0x97,0x01},
+{0xF10D,0x41,0x01},
+{0xF10E,0x8D,0x01},
+{0xF10F,0x6D,0x01},
+{0xF110,0x86,0x01},
+{0xF111,0xE3,0x01},
+{0xF112,0x9C,0x01},
+{0xF113,0xE2,0x01},
+{0xF114,0xD8,0x01},
+{0xF115,0x06,0x01},
+{0xF116,0x36,0x01},
+{0xF117,0xB5,0x01},
+{0xF118,0xE9,0x01},
+{0xF119,0x4D,0x01},
+{0xF11A,0x70,0x01},
+{0xF11B,0x68,0x01},
+{0xF11C,0x03,0x01},
+{0xF11D,0x00,0x01},
+{0xF11E,0x00,0x01},
+{0xF11F,0x00,0x01},
+{0xF120,0x00,0x01},
+{0xF121,0x00,0x01},
+
+
+//SHD TH
+{0x6C32,0x1964,0x02},    // SHD_INP_TH_HB_H_R2
+{0x6C34,0x18CE,0x02},    // SHD_INP_TH_HB_L_R2
+{0x6C36,0x10CC,0x02},    // SHD_INP_TH_LB_H_R2
+{0x6C38,0x1004,0x02},    // SHD_INP_TH_LB_L_R2
+{0x6C3C,0x10CC,0x02},    // SHD_INP_TH_HB_H_RB
+{0x6C3E,0x1004,0x02},    // SHD_INP_TH_HB_L_RB
+{0x6C40,0x0000,0x02},    // SHD_INP_TH_LB_H_RB
+{0x6C42,0x0000,0x02},    // SHD_INP_TH_LB_L_RB
+
+//PreWB_offset (for SHD2)
+{0x6828,0x0013,0x02},    // SHD_PRER_OFFSET_R2 :
+//PreWB_offset (for SHD3)
+{0x682C,0x000C,0x02},    // SHD_PRER_OFFSET_RB :
+{0x6830,0xFFFF,0x02},    // SHD_PREB_OFFSET_RB :
+
+// CXC/SHD EN
+{0x01BC,0x57,0x01},    // CXC ON SHD ON INP ON GAIN OFF
+};
+
+static const isx012_regset_t ISX012_Flash_ON[] =
+{
+//Flash_ON_SET
+{0x00B7,0x15,0x01},    // LED_ON
+{0x0016,0x10,0x01},    // GPIO_FUNCSEL
+{0x0181,0x05,0x01},    // CAP_HALF_AE_CTRL
+{0x01AE,0x01,0x01},    // HALF_AWB_CTRL
+{0x6223,0x01,0x01},    // INIT_GAINS
+{0x6226,0x01,0x01},    // ATW_GAINS_IN_NR
+{0x6227,0x01,0x01},    // ATW_GAINS_IN
+{0x6228,0x01,0x01},    // ATW_GAINS_OUT_NR
+{0x6229,0x01,0x01},    // ATW_GAINS_OUT
+{0x5E3D,0x0F,0x01},    // FASTMOVE_TIMEOUT
+{0x5E32,0x0F,0x01},    // AESPEED_FAST
+{0x5E2E,0x1A,0x01},    // AEIINDEADBAND
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN
+{0x01AF,0x01,0x01},    // CAP_AWB_CTRL
+{0x6224,0x01,0x01},    // ATW_DELAY
+//AWB boundary set
+{0x6400,0x00,0x01},    // INFRM_LEFT00 :
+{0x6401,0x00,0x01},    // INFRM_LEFT01 :
+{0x6402,0x00,0x01},    // INFRM_LEFT02 :
+{0x6403,0x00,0x01},    // INFRM_LEFT03 :
+{0x6404,0x00,0x01},    // INFRM_LEFT04 :
+{0x6405,0x00,0x01},    // INFRM_LEFT05 :
+{0x6406,0x00,0x01},    // INFRM_LEFT06 :
+{0x6407,0x00,0x01},    // INFRM_LEFT07 :
+{0x6408,0x00,0x01},    // INFRM_LEFT08 :
+{0x6409,0x00,0x01},    // INFRM_LEFT09 :
+{0x640A,0x00,0x01},    // INFRM_LEFT10 :
+{0x640B,0x00,0x01},    // INFRM_LEFT11 :
+{0x640C,0x00,0x01},    // INFRM_LEFT12 :
+{0x640D,0x00,0x01},    // INFRM_LEFT13 :
+{0x640E,0x00,0x01},    // INFRM_LEFT14 :
+{0x640F,0x00,0x01},    // INFRM_LEFT15 :
+{0x6410,0x00,0x01},    // INFRM_LEFT16 :
+{0x6411,0x00,0x01},    // INFRM_LEFT17 :
+{0x6412,0x00,0x01},    // INFRM_LEFT18 :
+{0x6413,0x00,0x01},    // INFRM_LEFT19 :
+{0x6414,0x00,0x01},    // INFRM_LEFT20 :
+{0x6415,0x00,0x01},    // INFRM_LEFT21 :
+{0x6416,0x00,0x01},    // INFRM_LEFT22 :
+{0x6417,0x00,0x01},    // INFRM_LEFT23 :
+{0x6418,0x00,0x01},    // INFRM_LEFT24 :
+{0x6419,0x00,0x01},    // INFRM_LEFT25 :
+{0x641A,0x00,0x01},    // INFRM_LEFT26 :
+{0x641B,0x00,0x01},    // INFRM_LEFT27 :
+{0x641C,0x00,0x01},    // INFRM_LEFT28 :
+{0x641D,0x00,0x01},    // INFRM_LEFT29 :
+{0x641E,0x00,0x01},    // INFRM_LEFT30 :
+{0x641F,0x00,0x01},    // INFRM_LEFT31 :
+{0x6420,0x00,0x01},    // INFRM_LEFT32 :
+{0x6421,0x00,0x01},    // INFRM_LEFT33 :
+{0x6422,0x00,0x01},    // INFRM_LEFT34 :
+{0x6423,0x00,0x01},    // INFRM_LEFT35 :
+{0x6424,0x00,0x01},    // INFRM_LEFT36 :
+{0x6425,0x00,0x01},    // INFRM_LEFT37 :
+{0x6426,0xFF,0x01},    // INFRM_RIGHT00 :
+{0x6427,0xFF,0x01},    // INFRM_RIGHT01 :
+{0x6428,0xFF,0x01},    // INFRM_RIGHT02 :
+{0x6429,0xFF,0x01},    // INFRM_RIGHT03 :
+{0x642A,0xFF,0x01},    // INFRM_RIGHT04 :
+{0x642B,0xFF,0x01},    // INFRM_RIGHT05 :
+{0x642C,0xFF,0x01},    // INFRM_RIGHT06 :
+{0x642D,0xFF,0x01},    // INFRM_RIGHT07 :
+{0x642E,0xFF,0x01},    // INFRM_RIGHT08 :
+{0x642F,0xFF,0x01},    // INFRM_RIGHT09 :
+{0x6430,0xFF,0x01},    // INFRM_RIGHT10 :
+{0x6431,0xFF,0x01},    // INFRM_RIGHT11 :
+{0x6432,0xFF,0x01},    // INFRM_RIGHT12 :
+{0x6433,0xFF,0x01},    // INFRM_RIGHT13 :
+{0x6434,0xFF,0x01},    // INFRM_RIGHT14 :
+{0x6435,0xFF,0x01},    // INFRM_RIGHT15 :
+{0x6436,0xFF,0x01},    // INFRM_RIGHT16 :
+{0x6437,0xFF,0x01},    // INFRM_RIGHT17 :
+{0x6438,0xFF,0x01},    // INFRM_RIGHT18 :
+{0x6439,0xFF,0x01},    // INFRM_RIGHT19 :
+{0x643A,0xFF,0x01},    // INFRM_RIGHT20 :
+{0x643B,0xFF,0x01},    // INFRM_RIGHT21 :
+{0x643C,0xFF,0x01},    // INFRM_RIGHT22 :
+{0x643D,0xFF,0x01},    // INFRM_RIGHT23 :
+{0x643E,0xFF,0x01},    // INFRM_RIGHT24 :
+{0x643F,0xFF,0x01},    // INFRM_RIGHT25 :
+{0x6440,0xFF,0x01},    // INFRM_RIGHT26 :
+{0x6441,0xFF,0x01},    // INFRM_RIGHT27 :
+{0x6442,0xFF,0x01},    // INFRM_RIGHT28 :
+{0x6443,0xFF,0x01},    // INFRM_RIGHT29 :
+{0x6444,0xFF,0x01},    // INFRM_RIGHT30 :
+{0x6445,0xFF,0x01},    // INFRM_RIGHT31 :
+{0x6446,0xFF,0x01},    // INFRM_RIGHT32 :
+{0x6447,0xFF,0x01},    // INFRM_RIGHT33 :
+{0x6448,0xFF,0x01},    // INFRM_RIGHT34 :
+{0x6449,0xFF,0x01},    // INFRM_RIGHT35 :
+{0x644A,0xFF,0x01},    // INFRM_RIGHT36 :
+{0x644B,0xFF,0x01},    // INFRM_RIGHT37 :
+{0x644C,0x25C2,0x02},    // INFRM_TOP :
+{0x644E,0x0348,0x02},    // INFRM_BOTM :
+{0x6450,0x1D,0x01},    // INFRM_FLTOP :
+{0x6451,0x00,0x01},    // INFRM_FLBOTM :
+//halfrelease_mode value
+{0x00B1,0x01,0x01},    //AF_RESTART_F
+{0x00B3,0x00,0x01},    //AFMODE_HREL :
+{0xFFFF,0x21,0x01},//$wait, 33
+{0x0081,0x01,0x01},    //MODESEL
+};
+
+static const isx012_regset_t ISX012_Flash_OFF[] =
+{
+//Flash_OFF_RESET
+{0x00B7,0x00,0x01},    // LED_ON
+{0x0016,0x10,0x01},    // GPIO_FUNCSEL
+{0x0181,0x00,0x01},    // CAP_HALF_AE_CTRL
+{0x01AE,0x00,0x01},    // HALF_AWB_CTRL
+{0x6223,0x04,0x01},    // INIT_GAINS
+{0x6226,0x08,0x01},    // ATW_GAINS_IN_NR
+{0x6227,0x04,0x01},    // ATW_GAINS_IN
+{0x6228,0x08,0x01},    // ATW_GAINS_OUT_NR
+{0x6229,0x04,0x01},    // ATW_GAINS_OUT
+{0x5E3D,0x0A,0x01},    // FASTMOVE_TIMEOUT
+{0x5E32,0x0F,0x01},    // AESPEED_FAST
+{0x5E2E,0x1A,0x01},    // AEIINDEADBAND
+{0x500A,0x00,0x01},    // FAST_MODECHG_EN
+{0x01AF,0x00,0x01},    // CAP_AWB_CTRL
+{0x6224,0x04,0x01},    // ATW_DELAY
+//AWB boundary reset
+{0x6400,0xAA,0x01},    // INFRM_LEFT00 :
+{0x6401,0xAA,0x01},    // INFRM_LEFT01 :
+{0x6402,0xAA,0x01},    // INFRM_LEFT02 :
+{0x6403,0xAA,0x01},    // INFRM_LEFT03 :
+{0x6404,0xAA,0x01},    // INFRM_LEFT04 :
+{0x6405,0xAA,0x01},    // INFRM_LEFT05 :
+{0x6406,0xAA,0x01},    // INFRM_LEFT06 :
+{0x6407,0xAA,0x01},    // INFRM_LEFT07 :
+{0x6408,0xAA,0x01},    // INFRM_LEFT08 :
+{0x6409,0xAE,0x01},    // INFRM_LEFT09 :
+{0x640A,0xA0,0x01},    // INFRM_LEFT10 :
+{0x640B,0x8C,0x01},    // INFRM_LEFT11 :
+{0x640C,0x72,0x01},    // INFRM_LEFT12 :
+{0x640D,0x64,0x01},    // INFRM_LEFT13 :
+{0x640E,0x5A,0x01},    // INFRM_LEFT14 :
+{0x640F,0x52,0x01},    // INFRM_LEFT15 :
+{0x6410,0x48,0x01},    // INFRM_LEFT16 :
+{0x6411,0x43,0x01},    // INFRM_LEFT17 :
+{0x6412,0x3D,0x01},    // INFRM_LEFT18 :
+{0x6413,0x37,0x01},    // INFRM_LEFT19 :
+{0x6414,0x33,0x01},    // INFRM_LEFT20 :
+{0x6415,0x30,0x01},    // INFRM_LEFT21 :
+{0x6416,0x2E,0x01},    // INFRM_LEFT22 :
+{0x6417,0x2B,0x01},    // INFRM_LEFT23 :
+{0x6418,0x28,0x01},    // INFRM_LEFT24 :
+{0x6419,0x26,0x01},    // INFRM_LEFT25 :
+{0x641A,0x24,0x01},    // INFRM_LEFT26 :
+{0x641B,0x23,0x01},    // INFRM_LEFT27 :
+{0x641C,0x22,0x01},    // INFRM_LEFT28 :
+{0x641D,0x22,0x01},    // INFRM_LEFT29 :
+{0x641E,0x21,0x01},    // INFRM_LEFT30 :
+{0x641F,0x20,0x01},    // INFRM_LEFT31 :
+{0x6420,0x1D,0x01},    // INFRM_LEFT32 :
+{0x6421,0x1A,0x01},    // INFRM_LEFT33 :
+{0x6422,0x18,0x01},    // INFRM_LEFT34 :
+{0x6423,0x17,0x01},    // INFRM_LEFT35 :
+{0x6424,0x16,0x01},    // INFRM_LEFT36 :
+{0x6425,0x17,0x01},    // INFRM_LEFT37 :
+{0x6426,0xAF,0x01},    // INFRM_RIGHT00 :
+{0x6427,0xAF,0x01},    // INFRM_RIGHT01 :
+{0x6428,0xAF,0x01},    // INFRM_RIGHT02 :
+{0x6429,0xAF,0x01},    // INFRM_RIGHT03 :
+{0x642A,0xAF,0x01},    // INFRM_RIGHT04 :
+{0x642B,0xAF,0x01},    // INFRM_RIGHT05 :
+{0x642C,0xAF,0x01},    // INFRM_RIGHT06 :
+{0x642D,0xAF,0x01},    // INFRM_RIGHT07 :
+{0x642E,0xAF,0x01},    // INFRM_RIGHT08 :
+{0x642F,0xAA,0x01},    // INFRM_RIGHT09 :
+{0x6430,0xB2,0x01},    // INFRM_RIGHT10 :
+{0x6431,0xB4,0x01},    // INFRM_RIGHT11 :
+{0x6432,0xB6,0x01},    // INFRM_RIGHT12 :
+{0x6433,0xB4,0x01},    // INFRM_RIGHT13 :
+{0x6434,0x9B,0x01},    // INFRM_RIGHT14 :
+{0x6435,0x8E,0x01},    // INFRM_RIGHT15 :
+{0x6436,0x84,0x01},    // INFRM_RIGHT16 :
+{0x6437,0x7A,0x01},    // INFRM_RIGHT17 :
+{0x6438,0x72,0x01},    // INFRM_RIGHT18 :
+{0x6439,0x6A,0x01},    // INFRM_RIGHT19 :
+{0x643A,0x63,0x01},    // INFRM_RIGHT20 :
+{0x643B,0x5E,0x01},    // INFRM_RIGHT21 :
+{0x643C,0x58,0x01},    // INFRM_RIGHT22 :
+{0x643D,0x53,0x01},    // INFRM_RIGHT23 :
+{0x643E,0x4E,0x01},    // INFRM_RIGHT24 :
+{0x643F,0x4A,0x01},    // INFRM_RIGHT25 :
+{0x6440,0x46,0x01},    // INFRM_RIGHT26 :
+{0x6441,0x42,0x01},    // INFRM_RIGHT27 :
+{0x6442,0x3F,0x01},    // INFRM_RIGHT28 :
+{0x6443,0x3C,0x01},    // INFRM_RIGHT29 :
+{0x6444,0x3A,0x01},    // INFRM_RIGHT30 :
+{0x6445,0x38,0x01},    // INFRM_RIGHT31 :
+{0x6446,0x37,0x01},    // INFRM_RIGHT32 :
+{0x6447,0x35,0x01},    // INFRM_RIGHT33 :
+{0x6448,0x33,0x01},    // INFRM_RIGHT34 :
+{0x6449,0x32,0x01},    // INFRM_RIGHT35 :
+{0x644A,0x32,0x01},    // INFRM_RIGHT36 :
+{0x644B,0x32,0x01},    // INFRM_RIGHT37 :
+{0x644C,0x24FA,0x02},    // INFRM_TOP :
+{0x644E,0x0940,0x02},    // INFRM_BOTM :
+{0x6450,0x19,0x01},    // INFRM_FLTOP :
+{0x6451,0x10,0x01},    // INFRM_FLBOTM :
+////Flash_ON_RESET
+{0x0308,0x11,0x01},    // AELINE_MONI_SN1_2 :
+{0x0309,0x13,0x01},    // AELINE_MONI_SN3_4 :
+{0x030B,0x41,0x01},    // AELINE_MONI_SN7_8 :
+{0x030D,0x11,0x01},    // AELINE_MONI_SN11_12 :
+{0x030E,0x11,0x01},    // AELINE_HALF_SN1_2 :
+{0x030F,0x13,0x01},    // AELINE_HALF_SN3_4 :
+{0x0311,0x41,0x01},    // AELINE_HALF_SN7_8 :
+{0x0313,0x11,0x01},    // AELINE_HALF_SN11_12 :
+{0x0314,0x11,0x01},    // AELINE_HALF_AFEND_SN1_2 :
+{0x0315,0x13,0x01},    // AELINE_HALF_AFEND_SN3_4 :
+{0x0317,0x41,0x01},    // AELINE_HALF_AFEND_SN7_8 :
+{0x0319,0x11,0x01},    // AELINE_HALF_AFEND_SN11_12 :
+{0x031A,0x00,0x01},    // AELINE_CAP_SN1_2 :
+{0x031B,0x03,0x01},    // AELINE_CAP_SN3_4 :
+{0x031D,0x50,0x01},    // AELINE_CAP_SN7_8 :
+{0x031F,0x00,0x01},    // AELINE_CAP_SN11_12 :
+{0x0294,0x00,0x01},    // AE_SN1
+{0x0297,0x00,0x01},    // AE_SN4
+{0x029A,0x00,0x01},    // AE_SN7
+{0x029E,0x00,0x01},    // AE_SN11
+};
+
+static const isx012_regset_t ISX012_Flash_AELINE[] =
+{
+//Flash_ON_SET
+{0x0308,0x12,0x01},    // AELINE_MONI_SN1_2 :
+{0x0309,0x23,0x01},    // AELINE_MONI_SN3_4 :
+{0x030B,0x42,0x01},    // AELINE_MONI_SN7_8 :
+{0x030D,0x12,0x01},    // AELINE_MONI_SN11_12 :
+{0x030E,0x12,0x01},    // AELINE_HALF_SN1_2 :
+{0x030F,0x23,0x01},    // AELINE_HALF_SN3_4 :
+{0x0311,0x42,0x01},    // AELINE_HALF_SN7_8 :
+{0x0313,0x12,0x01},    // AELINE_HALF_SN11_12 :
+{0x0314,0x12,0x01},    // AELINE_HALF_AFEND_SN1_2 :
+{0x0315,0x23,0x01},    // AELINE_HALF_AFEND_SN3_4 :
+{0x0317,0x42,0x01},    // AELINE_HALF_AFEND_SN7_8 :
+{0x0319,0x12,0x01},    // AELINE_HALF_AFEND_SN11_12 :
+{0x031A,0x02,0x01},    // AELINE_CAP_SN1_2 :
+{0x031B,0x23,0x01},    // AELINE_CAP_SN3_4 :
+{0x031D,0x52,0x01},    // AELINE_CAP_SN7_8 :
+{0x031F,0x02,0x01},    // AELINE_CAP_SN11_12 :
+};
+
+static const isx012_regset_t ISX012_Lowlux_Night_Reset[] =
+{
+{0x039D,0x00,0x01},    //UIHUE_TYPE3 :
+{0x03A0,0x80,0x01},    //UISATURATION_TYPE3 :
+{0x982A,0xFFEC,0x02},	 // CS_CBLLEV_A :
+{0x9830,0xFFEC,0x02},	 // CS_CRLLEV_A :
+{0x9805,0x0A,0x01},    // CS_SLP_C_A :
+{0x6A9E,0x15C0,0x02},	 //HMAX_1_1(0x6A9E)=0x15C0
+{0x00AC,0x00,0x01},    //
+{0x660E,0x5A,0x01},    // AF_HBPF_PEAK_OPD_TH_MIN
+{0x6610,0x5A,0x01},    // AF_HBPF_PEAK_OPD_TH_MAX
+{0x664A,0x04,0x01},    // AF_DROPN_ON_PEAK_DETECT :
+{0x6640,0x02,0x01},    // AF_DROPN_ON_PEAK_DETECT_SECOND :
+{0x0289,0x20,0x01},    //AWB_SN8
+};
+
+#endif /* __ISX012_REGS_H__ */
diff --git a/drivers/media/video/m5mo.c b/drivers/media/video/m5mo.c
new file mode 100644
index 0000000..0750ecb
--- /dev/null
+++ b/drivers/media/video/m5mo.c
@@ -0,0 +1,3068 @@
+/*
+ * driver for Fusitju M5MO LS 8MP camera
+ *
+ * Copyright (c) 2010, Samsung Electronics. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <media/v4l2-device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/vmalloc.h>
+#include <linux/firmware.h>
+#include <linux/videodev2.h>
+#include <linux/slab.h>
+#include <linux/videodev2_exynos_media.h>
+
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+
+#include <linux/regulator/machine.h>
+
+#include <media/m5mo_platform.h>
+#include "m5mo.h"
+
+#define M5MO_DRIVER_NAME	"M5MO"
+
+#ifdef CONFIG_MACH_S2PLUS
+extern struct class *camera_class;
+struct device *m5mo_dev;
+#endif
+
+#define M5MO_FW_PATH		"/sdcard/RS_M5LS.bin"
+#define M5MO_FW_DUMP_PATH	"/data/RS_M5LS_dump.bin"
+
+#define M5MOTB_FW_PATH "RS_M5LS_TB.bin" /* TECHWIN - SONY */
+/* #define M5MOON_FW_PATH "RS_M5LS_ON.bin" */ /* FIBEROPTICS - SONY */
+/* #define M5MOOM_FW_PATH "RS_M5LS_OM.bin" */ /* FIBEROPTICS - S.LSI */
+#if defined(CONFIG_MACH_U1_KOR_LGT) || defined(CONFIG_TARGET_LOCALE_NTT)
+#define M5MOSB_FW_PATH "RS_M5LS_SB.bin" /* ELECTRO-MECHANICS - SONY */
+#endif
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+#define M5MOSC_FW_PATH "RS_M5LS_SC.bin" /* ELECTRO-MECHANICS - S.LSI*/
+#endif
+/* #define M5MOCB_FW_PATH "RS_M5LS_CB.bin" */ /* CAMSYS - SONY */
+#if defined(CONFIG_TARGET_LOCALE_NA)
+/* #define M5MOOE_FW_PATH "RS_M5LS_OE.bin" */ /* FIBEROPTICS - SONY */
+#endif
+#if defined(CONFIG_MACH_Q1_BD)
+#define M5MOOO_FW_PATH "RS_M5LS_OO.bin" /* FIBEROPTICS - SONY */
+#endif
+
+#define M5MO_FW_VER_LEN		22
+#define M5MO_FW_VER_FILE_CUR	0x16FF00
+
+#define M5MO_FLASH_BASE_ADDR	0x10000000
+#define M5MO_INT_RAM_BASE_ADDR	0x68000000
+
+#define M5MO_I2C_RETRY		5
+#define M5MO_I2C_VERIFY		100
+#define M5MO_ISP_TIMEOUT	3000
+#define M5MO_ISP_AFB_TIMEOUT	15000 /* FIXME */
+#define M5MO_ISP_ESD_TIMEOUT	1000
+
+#define M5MO_JPEG_MAXSIZE	0x3A0000
+#define M5MO_THUMB_MAXSIZE	0xFC00
+#define M5MO_POST_MAXSIZE	0xBB800
+
+#define M5MO_DEF_APEX_DEN	100
+
+#define m5mo_readb(sd, g, b, v)		m5mo_read(sd, 1, g, b, v)
+#define m5mo_readw(sd, g, b, v)		m5mo_read(sd, 2, g, b, v)
+#define m5mo_readl(sd, g, b, v)		m5mo_read(sd, 4, g, b, v)
+
+#define m5mo_writeb(sd, g, b, v)	m5mo_write(sd, 1, g, b, v)
+#define m5mo_writew(sd, g, b, v)	m5mo_write(sd, 2, g, b, v)
+#define m5mo_writel(sd, g, b, v)	m5mo_write(sd, 4, g, b, v)
+
+#define CHECK_ERR(x)	if ((x) < 0) { \
+				cam_err("i2c failed, err %d\n", x); \
+				return x; \
+			}
+
+#define NELEMS(array) (sizeof(array) / sizeof(array[0]))
+
+static const struct m5mo_frmsizeenum preview_frmsizes[] = {
+	{ M5MO_PREVIEW_QCIF,	176,	144,	0x05 },	/* 176 x 144 */
+	{ M5MO_PREVIEW_QCIF2,	528,	432,	0x2C },	/* 176 x 144 */
+	{ M5MO_PREVIEW_QVGA,	320,	240,	0x09 },
+	{ M5MO_PREVIEW_VGA,	640,	480,	0x17 },
+	{ M5MO_PREVIEW_D1,	720,	480,	0x18 },
+	{ M5MO_PREVIEW_WVGA,	800,	480,	0x1A },
+	{ M5MO_PREVIEW_720P,	1280,	720,	0x21 },
+
+#if defined(CONFIG_MACH_Q1_BD)
+	{ M5MO_PREVIEW_880_720,  880,	720,	0x2E },
+	{ M5MO_PREVIEW_1200_800, 1200,	800,	0x2F },
+	{ M5MO_PREVIEW_1280_800, 1280,	800,	0x35 },
+	{ M5MO_PREVIEW_1280_768, 1280,	768,	0x22 },
+	{ M5MO_PREVIEW_1072_800, 1072,	800,	0x36 },
+	{ M5MO_PREVIEW_980_800,	 980,	800,	0x37 },
+#endif
+
+	{ M5MO_PREVIEW_1080P,	1920,	1080,	0x28 },
+	{ M5MO_PREVIEW_HDR,	3264,	2448,	0x27 },
+};
+
+static const struct m5mo_frmsizeenum capture_frmsizes[] = {
+	{ M5MO_CAPTURE_VGA,	640,	480,	0x09 },
+	{ M5MO_CAPTURE_WVGA,	800,	480,	0x0A },
+	{ M5MO_CAPTURE_W2MP,	2048,	1232,	0x2C },
+	{ M5MO_CAPTURE_3MP,	2048,	1536,	0x1B },
+	{ M5MO_CAPTURE_W7MP,	3264,	1968,	0x2D },
+	{ M5MO_CAPTURE_8MP,	3264,	2448,	0x25 },
+};
+
+static struct m5mo_control m5mo_ctrls[] = {
+	{
+		.id = V4L2_CID_CAMERA_ISO,
+		.minimum = ISO_AUTO,
+		.maximum = ISO_800,
+		.step = 1,
+		.value = ISO_AUTO,
+		.default_value = ISO_AUTO,
+	}, {
+		.id = V4L2_CID_CAMERA_BRIGHTNESS,
+		.minimum = EV_MINUS_4,
+		.maximum = EV_MAX - 1,
+		.step = 1,
+		.value = EV_DEFAULT,
+		.default_value = EV_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SATURATION,
+		.minimum = SATURATION_MINUS_2,
+		.maximum = SATURATION_MAX - 1,
+		.step = 1,
+		.value = SATURATION_DEFAULT,
+		.default_value = SATURATION_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SHARPNESS,
+		.minimum = SHARPNESS_MINUS_2,
+		.maximum = SHARPNESS_MAX - 1,
+		.step = 1,
+		.value = SHARPNESS_DEFAULT,
+		.default_value = SHARPNESS_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_ZOOM,
+		.minimum = ZOOM_LEVEL_0,
+		.maximum = ZOOM_LEVEL_MAX - 1,
+		.step = 1,
+		.value = ZOOM_LEVEL_0,
+		.default_value = ZOOM_LEVEL_0,
+	}, {
+		.id = V4L2_CID_CAM_JPEG_QUALITY,
+		.minimum = 1,
+		.maximum = 100,
+		.step = 1,
+		.value = 100,
+		.default_value = 100,
+	}, {
+		.id = V4L2_CID_CAMERA_ANTI_BANDING,
+		.minimum = ANTI_BANDING_AUTO,
+		.maximum = ANTI_BANDING_OFF,
+		.step = 1,
+		.value = ANTI_BANDING_50HZ,
+		.default_value = ANTI_BANDING_50HZ,
+	},
+};
+
+#ifndef CONFIG_MACH_S2PLUS
+struct class *camera_class;
+#endif
+
+static inline struct m5mo_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct m5mo_state, sd);
+}
+
+static int m5mo_read(struct v4l2_subdev *sd,
+	u8 len, u8 category, u8 byte, int *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[5];
+	unsigned char recv_data[len + 1];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len != 0x01 && len != 0x02 && len != 0x04)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = msg.len;
+	data[1] = 0x01;			/* Read category parameters */
+	data[2] = category;
+	data[3] = byte;
+	data[4] = len;
+
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("category %#x, byte %#x\n", category, byte);
+		return err;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = sizeof(recv_data);
+	msg.buf = recv_data;
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("category %#x, byte %#x\n", category, byte);
+		return err;
+	}
+
+	if (recv_data[0] != sizeof(recv_data))
+		cam_i2c_dbg("expected length %d, but return length %d\n",
+				 sizeof(recv_data), recv_data[0]);
+
+	if (len == 0x01)
+		*val = recv_data[1];
+	else if (len == 0x02)
+		*val = recv_data[1] << 8 | recv_data[2];
+	else
+		*val = recv_data[1] << 24 | recv_data[2] << 16 |
+				recv_data[3] << 8 | recv_data[4];
+
+	cam_i2c_dbg("category %#02x, byte %#x, value %#x\n", category, byte, *val);
+	return err;
+}
+
+static int m5mo_write(struct v4l2_subdev *sd,
+	u8 len, u8 category, u8 byte, int val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[len + 4];
+	int i, err;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len != 0x01 && len != 0x02 && len != 0x04)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	data[0] = msg.len;
+	data[1] = 0x02;			/* Write category parameters */
+	data[2] = category;
+	data[3] = byte;
+	if (len == 0x01) {
+		data[4] = val & 0xFF;
+	} else if (len == 0x02) {
+		data[4] = (val >> 8) & 0xFF;
+		data[5] = val & 0xFF;
+	} else {
+		data[4] = (val >> 24) & 0xFF;
+		data[5] = (val >> 16) & 0xFF;
+		data[6] = (val >> 8) & 0xFF;
+		data[7] = val & 0xFF;
+	}
+
+	cam_i2c_dbg("category %#x, byte %#x, value %#x\n", category, byte, val);
+
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	return err;
+}
+
+static int m5mo_mem_read(struct v4l2_subdev *sd, u16 len, u32 addr, u8 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[8];
+	unsigned char recv_data[len + 3];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len <= 0)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = 0x00;
+	data[1] = 0x03;
+	data[2] = (addr >> 24) & 0xFF;
+	data[3] = (addr >> 16) & 0xFF;
+	data[4] = (addr >> 8) & 0xFF;
+	data[5] = addr & 0xFF;
+	data[6] = (len >> 8) & 0xFF;
+	data[7] = len & 0xFF;
+
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	msg.flags = I2C_M_RD;
+	msg.len = sizeof(recv_data);
+	msg.buf = recv_data;
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	if (len != (recv_data[1] << 8 | recv_data[2]))
+		cam_i2c_dbg("expected length %d, but return length %d\n",
+			len, recv_data[1] << 8 | recv_data[2]);
+
+	memcpy(val, recv_data + 3, len);
+
+	cam_i2c_dbg("address %#x, length %d\n", addr, len);
+	return err;
+}
+
+static int m5mo_mem_write(struct v4l2_subdev *sd, u8 cmd, u16 len, u32 addr, u8 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[len + 8];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = 0x00;
+	data[1] = cmd;
+	data[2] = (addr >> 24) & 0xFF;
+	data[3] = (addr >> 16) & 0xFF;
+	data[4] = (addr >> 8) & 0xFF;
+	data[5] = addr & 0xFF;
+	data[6] = (len >> 8) & 0xFF;
+	data[7] = len & 0xFF;
+	memcpy(data + 2 + sizeof(addr) + sizeof(len), val, len);
+
+	cam_i2c_dbg("address %#x, length %d\n", addr, len);
+
+	for (i = M5MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	return err;
+}
+
+static irqreturn_t m5mo_isp_isr(int irq, void *dev_id)
+{
+	struct v4l2_subdev *sd = (struct v4l2_subdev *)dev_id;
+	struct m5mo_state *state = to_state(sd);
+
+	cam_dbg("**************** interrupt ****************\n");
+	state->isp.issued = 1;
+	wake_up_interruptible(&state->isp.wait);
+
+	return IRQ_HANDLED;
+}
+
+static u32 m5mo_wait_interrupt(struct v4l2_subdev *sd,
+	unsigned int timeout)
+{
+	struct m5mo_state *state = to_state(sd);
+	cam_trace("E\n");
+
+	if (wait_event_interruptible_timeout(state->isp.wait,
+		state->isp.issued == 1,
+		msecs_to_jiffies(timeout)) == 0) {
+		cam_err("timeout\n");
+		return 0;
+	}
+
+	state->isp.issued = 0;
+
+	m5mo_readb(sd, M5MO_CATEGORY_SYS,
+		M5MO_SYS_INT_FACTOR, &state->isp.int_factor);
+
+	cam_trace("X\n");
+	return state->isp.int_factor;
+}
+
+static int m5mo_set_mode(struct v4l2_subdev *sd, u32 mode)
+{
+	int i, err;
+	u32 old_mode, val;
+	cam_trace("E\n");
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_MODE, &old_mode);
+
+	if (err < 0)
+		return err;
+
+	if (old_mode == mode) {
+		cam_dbg("%#x -> %#x\n", old_mode, mode);
+		return old_mode;
+	}
+
+	cam_dbg("%#x -> %#x\n", old_mode, mode);
+
+	switch (old_mode) {
+	case M5MO_SYSINIT_MODE:
+		cam_warn("sensor is initializing\n");
+		err = -EBUSY;
+		break;
+
+	case M5MO_PARMSET_MODE:
+		if (mode == M5MO_STILLCAP_MODE) {
+			err = m5mo_writeb(sd, M5MO_CATEGORY_SYS,
+				M5MO_SYS_MODE, M5MO_MONITOR_MODE);
+			if (err < 0)
+				break;
+			for (i = M5MO_I2C_VERIFY; i; i--) {
+				err = m5mo_readb(sd, M5MO_CATEGORY_SYS,
+					M5MO_SYS_MODE, &val);
+				if (val == M5MO_MONITOR_MODE)
+					break;
+				msleep(10);
+			}
+		}
+	case M5MO_MONITOR_MODE:
+	case M5MO_STILLCAP_MODE:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_MODE, mode);
+		break;
+
+	default:
+		cam_warn("current mode is unknown, %d\n", old_mode);
+		err = -EINVAL;
+	}
+
+	if (err < 0)
+		return err;
+
+	for (i = M5MO_I2C_VERIFY; i; i--) {
+		err = m5mo_readb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_MODE, &val);
+		if (val == mode)
+			break;
+		msleep(10);
+	}
+
+	cam_trace("X\n");
+	return old_mode;
+}
+
+/*
+ * v4l2_subdev_core_ops
+ */
+static int m5mo_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(m5mo_ctrls); i++) {
+		if (qc->id == m5mo_ctrls[i].id) {
+			qc->maximum = m5mo_ctrls[i].maximum;
+			qc->minimum = m5mo_ctrls[i].minimum;
+			qc->step = m5mo_ctrls[i].step;
+			qc->default_value = m5mo_ctrls[i].default_value;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+static int m5mo_get_af_result(struct v4l2_subdev *sd,
+		struct v4l2_control *ctrl);
+
+static int m5mo_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		m5mo_get_af_result(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAM_JPEG_MEMSIZE:
+		ctrl->value = M5MO_JPEG_MAXSIZE +
+			M5MO_THUMB_MAXSIZE + M5MO_POST_MAXSIZE;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_SIZE:
+		ctrl->value = state->jpeg.main_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_OFFSET:
+		ctrl->value = state->jpeg.main_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_SIZE:
+		ctrl->value = state->jpeg.thumb_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_OFFSET:
+		ctrl->value = state->jpeg.thumb_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_POSTVIEW_OFFSET:
+		ctrl->value = state->jpeg.postview_offset;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_FLASH:
+		ctrl->value = state->exif.flash;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_TV:
+		ctrl->value = state->exif.tv;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_BV:
+		ctrl->value = state->exif.bv;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_EBV:
+		ctrl->value = state->exif.ebv;
+		break;
+
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/*err = -ENOIOCTLCMD*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	return err;
+}
+
+static int m5mo_set_antibanding(struct v4l2_subdev *sd,
+		struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	struct m5mo_state *state = to_state(sd);
+	int val = ctrl->value, err;
+	u32 antibanding[] = {0x00, 0x01, 0x02, 0x03};
+
+	if (state->anti_banding == val)
+		return 0;
+
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE,
+					M5MO_AE_FLICKER, antibanding[val]);
+	CHECK_ERR(err);
+
+	state->anti_banding = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_af_softlanding(struct v4l2_subdev *sd)
+{
+	struct m5mo_state *state = to_state(sd);
+	u32 status = 0;
+	int i, err = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	err = m5mo_set_mode(sd, M5MO_MONITOR_MODE);
+	if (err <= 0) {
+		cam_err("failed to set mode\n");
+		return err;
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_LENS, M5MO_LENS_AF_MODE, 0x07);
+	CHECK_ERR(err);
+
+	for (i = M5MO_I2C_VERIFY; i; i--) {
+		msleep(10);
+		err = m5mo_readb(sd, M5MO_CATEGORY_LENS,
+			M5MO_LENS_AF_STATUS, &status);
+		CHECK_ERR(err);
+
+		if ((status & 0x01) == 0x00)
+			break;
+	}
+
+	if ((status & 0x01) != 0x00) {
+		cam_err("failed\n");
+		return -ETIMEDOUT;
+	}
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int m5mo_dump_fw(struct v4l2_subdev *sd)
+{
+	struct file *fp;
+	mm_segment_t old_fs;
+	u8 *buf, val;
+	u32 addr, unit, count, intram_unit = 0x1000;
+	int i, j, err;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M5MO_FW_DUMP_PATH,
+		O_WRONLY|O_CREAT|O_TRUNC, S_IRUGO|S_IWUGO|S_IXUSR);
+	if (IS_ERR(fp)) {
+		cam_err("failed to open %s, err %ld\n",
+			M5MO_FW_DUMP_PATH, PTR_ERR(fp));
+		err = -ENOENT;
+		goto file_out;
+	}
+
+	buf = kmalloc(intram_unit, GFP_KERNEL);
+	if (!buf) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	cam_dbg("start, file path %s\n", M5MO_FW_DUMP_PATH);
+
+	/* set pin */
+	val = 0x7E;
+	err = m5mo_mem_write(sd, 0x04, sizeof(val), 0x50000308, &val);
+	if (err < 0) {
+		cam_err("failed to write memory\n");
+		goto out;
+	}
+
+	addr = M5MO_FLASH_BASE_ADDR;
+	unit = SZ_64K;
+	count = 31;
+	for (i = 0; i < count; i++) {
+		for (j = 0; j < unit; j += intram_unit) {
+			err = m5mo_mem_read(sd,
+				intram_unit, addr + (i * unit) + j, buf);
+			if (err < 0) {
+				cam_err("i2c falied, err %d\n", err);
+				goto out;
+			}
+			vfs_write(fp, buf, intram_unit, &fp->f_pos);
+		}
+	}
+
+	addr = M5MO_FLASH_BASE_ADDR + SZ_64K * count;
+	unit = SZ_8K;
+	count = 4;
+	for (i = 0; i < count; i++) {
+		for (j = 0; j < unit; j += intram_unit) {
+			err = m5mo_mem_read(sd,
+				intram_unit, addr + (i * unit) + j, buf);
+			if (err < 0) {
+				cam_err("i2c falied, err %d\n", err);
+				goto out;
+			}
+			vfs_write(fp, buf, intram_unit, &fp->f_pos);
+		}
+	}
+
+	cam_dbg("end\n");
+
+out:
+	kfree(buf);
+	if (!IS_ERR(fp))
+		filp_close(fp, current->files);
+file_out:
+	set_fs(old_fs);
+
+	return err;
+}
+
+static int m5mo_get_sensor_fw_version(struct v4l2_subdev *sd,
+	char *buf)
+{
+	u8 val;
+	int err;
+
+	/* set pin */
+	val = 0x7E;
+	err = m5mo_mem_write(sd, 0x04, sizeof(val), 0x50000308, &val);
+	CHECK_ERR(err);
+
+	err = m5mo_mem_read(sd, M5MO_FW_VER_LEN,
+		M5MO_FLASH_BASE_ADDR + M5MO_FW_VER_FILE_CUR, buf);
+
+	cam_dbg("%s\n", buf);
+	return 0;
+}
+
+static int m5mo_get_phone_fw_version(struct v4l2_subdev *sd, char *buf)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	u8 sensor_ver[M5MO_FW_VER_LEN] = {0, };
+	const struct firmware *fw;
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long nread;
+	int fw_requested = 1;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M5MO_FW_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n", M5MO_FW_PATH,
+			  PTR_ERR(fp));
+		goto request_fw;
+	}
+
+	fw_requested = 0;
+	err = vfs_llseek(fp, M5MO_FW_VER_FILE_CUR, SEEK_SET);
+	if (err < 0) {
+		cam_warn("failed to fseek, %d\n", err);
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf, M5MO_FW_VER_LEN, &fp->f_pos);
+	if (nread != M5MO_FW_VER_LEN) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+
+		m5mo_get_sensor_fw_version(sd, sensor_ver);
+
+		if (sensor_ver[0] == 'T' && sensor_ver[1] == 'B') {
+			err = request_firmware(&fw, M5MOTB_FW_PATH, dev);
+#if defined(CONFIG_MACH_Q1_BD)
+		} else if (sensor_ver[0] == 'O' && sensor_ver[1] == 'O') {
+			err = request_firmware(&fw, M5MOOO_FW_PATH, dev);
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT) || defined(CONFIG_TARGET_LOCALE_NTT)
+		} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'B') {
+			err = request_firmware(&fw, M5MOSB_FW_PATH, dev);
+#endif
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+		} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'C') {
+			err = request_firmware(&fw, M5MOSC_FW_PATH, dev);
+#endif
+		} else {
+			cam_warn("cannot find the matched F/W file\n");
+#if defined(CONFIG_MACH_Q1_BD)
+			err = request_firmware(&fw, M5MOOO_FW_PATH, dev);
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+			err = request_firmware(&fw, M5MOSB_FW_PATH, dev);
+#else
+			err = request_firmware(&fw, M5MOTB_FW_PATH, dev);
+#endif
+		}
+
+		if (err != 0) {
+			cam_err("request_firmware falied\n");
+			err = -EINVAL;
+			goto out;
+		}
+
+		memcpy(buf, (u8 *)&fw->data[M5MO_FW_VER_FILE_CUR],
+		       M5MO_FW_VER_LEN);
+	}
+
+out:
+	if (!fw_requested) {
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	cam_dbg("%s\n", buf);
+	return 0;
+}
+
+static int m5mo_check_fw(struct v4l2_subdev *sd)
+{
+	struct m5mo_state *state = to_state(sd);
+	u8 sensor_ver[M5MO_FW_VER_LEN] = "FAILED Fujitsu M5MOLS";
+	u8 phone_ver[M5MO_FW_VER_LEN] = "FAILED Fujitsu M5MOLS";
+	int af_cal_h = 0, af_cal_l = 0;
+	int rg_cal_h = 0, rg_cal_l = 0;
+	int bg_cal_h = 0, bg_cal_l = 0;
+	int update_count = 0;
+	u32 int_factor;
+	int err;
+
+	cam_trace("E\n");
+
+	/* F/W version */
+	m5mo_get_phone_fw_version(sd, phone_ver);
+
+	if (state->isp.bad_fw)
+		goto out;
+
+	m5mo_get_sensor_fw_version(sd, sensor_ver);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH, M5MO_FLASH_CAM_START, 0x01);
+	CHECK_ERR(err);
+
+	int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+	if (!(int_factor & M5MO_INT_MODE)) {
+		cam_err("firmware was erased?\n");
+		return -ETIMEDOUT;
+	}
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_LENS, M5MO_LENS_AF_CAL, &af_cal_l);
+	CHECK_ERR(err);
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_ADJST, M5MO_ADJST_AWB_RG_H, &rg_cal_h);
+	CHECK_ERR(err);
+	err = m5mo_readb(sd, M5MO_CATEGORY_ADJST, M5MO_ADJST_AWB_RG_L, &rg_cal_l);
+	CHECK_ERR(err);
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_ADJST, M5MO_ADJST_AWB_BG_H, &bg_cal_h);
+	CHECK_ERR(err);
+	err = m5mo_readb(sd, M5MO_CATEGORY_ADJST, M5MO_ADJST_AWB_BG_L, &bg_cal_l);
+	CHECK_ERR(err);
+
+out:
+	if (!state->fw_version) {
+		state->fw_version = kzalloc(50, GFP_KERNEL);
+		if (!state->fw_version) {
+			cam_err("no memory for F/W version\n");
+			return -ENOMEM;
+		}
+	}
+
+	sprintf(state->fw_version, "%s %s %d %x %x %x %x %x %x",
+		sensor_ver, phone_ver, update_count,
+		af_cal_h, af_cal_l, rg_cal_h, rg_cal_l, bg_cal_h, bg_cal_l);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_sensor_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	err = m5mo_set_mode(sd, M5MO_PARMSET_MODE);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_PARM,
+		M5MO_PARM_HDMOVIE, val == SENSOR_MOVIE ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	state->sensor_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_flash(struct v4l2_subdev *sd, int val, int force)
+{
+	struct m5mo_state *state = to_state(sd);
+	int light, flash;
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	if (!force)
+		state->flash_mode = val;
+
+	/* movie flash mode should be set when recording is started */
+	if (state->sensor_mode == SENSOR_MOVIE && !state->recording)
+		return 0;
+
+retry:
+	switch (val) {
+	case FLASH_MODE_OFF:
+		light = 0x00;
+		flash = (state->sensor_mode == SENSOR_CAMERA) ? 0x00 : -1;
+		break;
+
+	case FLASH_MODE_AUTO:
+		light = (state->sensor_mode == SENSOR_CAMERA) ? 0x02 : 0x04;
+		flash = (state->sensor_mode == SENSOR_CAMERA) ? 0x02 : -1;
+		break;
+
+	case FLASH_MODE_ON:
+		light = (state->sensor_mode == SENSOR_CAMERA) ? 0x01 : 0x03;
+		flash = (state->sensor_mode == SENSOR_CAMERA) ? 0x01 : -1;
+		break;
+
+	case FLASH_MODE_TORCH:
+		light = 0x03;
+		flash = -1;
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = FLASH_MODE_OFF;
+		goto retry;
+	}
+
+	if (light >= 0) {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+			M5MO_CAPPARM_LIGHT_CTRL, light);
+		CHECK_ERR(err);
+	}
+
+	if (flash >= 0) {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+			M5MO_CAPPARM_FLASH_CTRL, flash);
+		CHECK_ERR(err);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_iso(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 iso[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05};
+
+	if (state->scene_mode != SCENE_MODE_NONE) {
+		/* sensor will set internally */
+		return 0;
+	}
+
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_ISOSEL, iso[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_metering(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case METERING_CENTER:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_MODE, 0x03);
+		CHECK_ERR(err);
+		break;
+	case METERING_SPOT:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_MODE, 0x06);
+		CHECK_ERR(err);
+		break;
+	case METERING_MATRIX:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_MODE, 0x01);
+		CHECK_ERR(err);
+		break;
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = METERING_CENTER;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_exposure(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 exposure[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE,
+		M5MO_AE_INDEX, exposure[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_whitebalance(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case WHITE_BALANCE_AUTO:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MODE, 0x01);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MANUAL, 0x01);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_SUNNY:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MANUAL, 0x04);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_CLOUDY:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MANUAL, 0x05);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_TUNGSTEN:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MANUAL, 0x01);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_FLUORESCENT:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB,
+			M5MO_WB_AWB_MANUAL, 0x02);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = WHITE_BALANCE_AUTO;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_sharpness(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 sharpness[] = {0x03, 0x04, 0x05, 0x06, 0x07};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_MON,
+		M5MO_MON_EDGE_LVL, sharpness[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_saturation(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 saturation[] = {0x01, 0x02, 0x03, 0x04, 0x05};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_MON,
+		M5MO_MON_CHROMA_LVL, saturation[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_scene_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	struct v4l2_control ctrl;
+	int evp, sharpness, saturation;
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	sharpness = SHARPNESS_DEFAULT;
+	saturation = CONTRAST_DEFAULT;
+
+retry:
+	switch (val) {
+	case SCENE_MODE_NONE:
+		evp = 0x00;
+		break;
+
+	case SCENE_MODE_PORTRAIT:
+		evp = 0x01;
+		sharpness = SHARPNESS_MINUS_1;
+		break;
+
+	case SCENE_MODE_LANDSCAPE:
+		evp = 0x02;
+		sharpness = SHARPNESS_PLUS_1;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_SPORTS:
+		evp = 0x03;
+		break;
+
+	case SCENE_MODE_PARTY_INDOOR:
+		evp = 0x04;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_BEACH_SNOW:
+		evp = 0x05;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_SUNSET:
+		evp = 0x06;
+		break;
+
+	case SCENE_MODE_DUSK_DAWN:
+		evp = 0x07;
+		break;
+
+	case SCENE_MODE_FALL_COLOR:
+		evp = 0x08;
+		saturation = SATURATION_PLUS_2;
+		break;
+
+	case SCENE_MODE_NIGHTSHOT:
+		evp = 0x09;
+		break;
+
+	case SCENE_MODE_BACK_LIGHT:
+		evp = 0x0A;
+		break;
+
+	case SCENE_MODE_FIREWORKS:
+		evp = 0x0B;
+		break;
+
+	case SCENE_MODE_TEXT:
+		evp = 0x0C;
+		sharpness = SHARPNESS_PLUS_2;
+		break;
+
+	case SCENE_MODE_CANDLE_LIGHT:
+		evp = 0x0D;
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = SCENE_MODE_NONE;
+		goto retry;
+	}
+
+	/* EV-P */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_EP_MODE_MON, evp);
+	CHECK_ERR(err);
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_EP_MODE_CAP, evp);
+	CHECK_ERR(err);
+
+	/* Chroma Saturation */
+	ctrl.id = V4L2_CID_CAMERA_SATURATION;
+	ctrl.value = saturation;
+	m5mo_set_saturation(sd, &ctrl);
+
+	/* Sharpness */
+	ctrl.id = V4L2_CID_CAMERA_SHARPNESS;
+	ctrl.value = sharpness;
+	m5mo_set_sharpness(sd, &ctrl);
+
+	/* Emotional Color */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_MCC_MODE, val == SCENE_MODE_NONE ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	state->scene_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_effect_color(struct v4l2_subdev *sd, int val)
+{
+	u32 int_factor;
+	int on, old_mode, cb, cr;
+	int err;
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_PARM, M5MO_PARM_EFFECT, &on);
+	CHECK_ERR(err);
+	if (on)	{
+		old_mode = m5mo_set_mode(sd, M5MO_PARMSET_MODE);
+		CHECK_ERR(old_mode);
+
+		err = m5mo_writeb(sd, M5MO_CATEGORY_PARM, M5MO_PARM_EFFECT, 0);
+		CHECK_ERR(err);
+
+		if (old_mode == M5MO_MONITOR_MODE) {
+			err = m5mo_set_mode(sd, old_mode);
+			CHECK_ERR(err);
+
+			int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+			if (!(int_factor & M5MO_INT_MODE)) {
+				cam_err("M5MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+			CHECK_ERR(err);
+		}
+	}
+
+	switch (val) {
+	case IMAGE_EFFECT_NONE:
+		break;
+
+	case IMAGE_EFFECT_SEPIA:
+		cb = 0xD8;
+		cr = 0x18;
+		break;
+
+	case IMAGE_EFFECT_BNW:
+		cb = 0x00;
+		cr = 0x00;
+		break;
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_MON,
+		M5MO_MON_COLOR_EFFECT, val == IMAGE_EFFECT_NONE ? 0x00 : 0x01);
+		CHECK_ERR(err);
+
+	if (val != IMAGE_EFFECT_NONE) {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_MON, M5MO_MON_CFIXB, cb);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_MON, M5MO_MON_CFIXR, cr);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+static int m5mo_set_effect_gamma(struct v4l2_subdev *sd, s32 val)
+{
+	u32 int_factor;
+	int on, effect, old_mode;
+	int err;
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_MON, M5MO_MON_COLOR_EFFECT, &on);
+	CHECK_ERR(err);
+	if (on) {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_MON,
+			M5MO_MON_COLOR_EFFECT, 0);
+		CHECK_ERR(err);
+	}
+
+	switch (val) {
+	case IMAGE_EFFECT_NEGATIVE:
+		effect = 0x01;
+		break;
+
+	case IMAGE_EFFECT_AQUA:
+		effect = 0x08;
+		break;
+	}
+
+	old_mode = m5mo_set_mode(sd, M5MO_PARMSET_MODE);
+	CHECK_ERR(old_mode);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_PARM, M5MO_PARM_EFFECT, effect);
+	CHECK_ERR(err);
+
+	if (old_mode == M5MO_MONITOR_MODE) {
+		err = m5mo_set_mode(sd, old_mode);
+		CHECK_ERR(err);
+
+		int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+		if (!(int_factor & M5MO_INT_MODE)) {
+			cam_err("M5MO_INT_MODE isn't issued, %#x\n",
+				int_factor);
+			return -ETIMEDOUT;
+		}
+		CHECK_ERR(err);
+	}
+
+	return err;
+}
+
+static int m5mo_set_effect(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case IMAGE_EFFECT_NONE:
+	case IMAGE_EFFECT_BNW:
+	case IMAGE_EFFECT_SEPIA:
+		err = m5mo_set_effect_color(sd, val);
+		CHECK_ERR(err);
+		break;
+
+	case IMAGE_EFFECT_AQUA:
+	case IMAGE_EFFECT_NEGATIVE:
+		err = m5mo_set_effect_gamma(sd, val);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = IMAGE_EFFECT_NONE;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_wdr(struct v4l2_subdev *sd, int val)
+{
+	int contrast, wdr, err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	contrast = (val == 1 ? 0x09 : 0x05);
+	wdr = (val == 1 ? 0x01 : 0x00);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_MON,
+			M5MO_MON_TONE_CTRL, contrast);
+		CHECK_ERR(err);
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+			M5MO_CAPPARM_WDR_EN, wdr);
+		CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_antishake(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int ahs, err;
+
+	if (state->scene_mode != SCENE_MODE_NONE) {
+		cam_warn("Should not be set with scene mode");
+		return 0;
+	}
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	ahs = (val == 1 ? 0x0E : 0x00);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_EP_MODE_MON, ahs);
+		CHECK_ERR(err);
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_EP_MODE_CAP, ahs);
+		CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_face_beauty(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_AFB_CAP_EN, val ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	state->face_beauty = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_lock(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err;
+
+	cam_trace("%s\n", val ? "on" : "off");
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_LOCK, val);
+	CHECK_ERR(err);
+	err = m5mo_writeb(sd, M5MO_CATEGORY_WB, M5MO_AWB_LOCK, val);
+	CHECK_ERR(err);
+
+	state->focus.lock = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+static int m5mo_get_af_result(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	int status, err;
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_LENS,
+		M5MO_LENS_AF_STATUS, &status);
+
+	state->focus.status = status;
+	ctrl->value = status;
+	return ctrl->value;
+}
+static int m5mo_set_af(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int i, status, err;
+
+	cam_info("%s, mode %#x\n", val ? "start" : "stop", state->focus.mode);
+
+	state->focus.start = val;
+
+	if (state->focus.mode != FOCUS_MODE_CONTINOUS) {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_LENS,
+			M5MO_LENS_AF_START, val);
+		CHECK_ERR(err);
+
+		if (!(state->focus.touch &&
+			state->focus.mode == FOCUS_MODE_TOUCH)) {
+			if (val && state->focus.lock) {
+				m5mo_set_lock(sd, 0);
+				msleep(100);
+			}
+			m5mo_set_lock(sd, val);
+		}
+
+	} else {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_LENS,
+			M5MO_LENS_AF_START, val ? 0x02 : 0x00);
+		CHECK_ERR(err);
+
+		err = -EBUSY;
+		for (i = M5MO_I2C_VERIFY; i && err; i--) {
+			msleep(10);
+			err = m5mo_readb(sd, M5MO_CATEGORY_LENS,
+				M5MO_LENS_AF_STATUS, &status);
+			CHECK_ERR(err);
+
+			if ((val && status == 0x05) || (!val && status != 0x05))
+				err = 0;
+		}
+	}
+
+	cam_dbg("X\n");
+	return err;
+}
+
+static int m5mo_set_af_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+#ifndef CONFIG_MACH_S2PLUS
+	struct regulator *movie = regulator_get(NULL, "led_movie");
+#endif
+	u32 cancel, mode, status = 0;
+	int i, err;
+
+	cancel = val & FOCUS_MODE_DEFAULT;
+	val &= 0xFF;
+
+retry:
+	switch (val) {
+	case FOCUS_MODE_AUTO:
+		mode = 0x00;
+		break;
+
+	case FOCUS_MODE_MACRO:
+		mode = 0x01;
+		break;
+
+	case FOCUS_MODE_CONTINOUS:
+		mode = 0x02;
+		cancel = 0;
+		break;
+
+	case FOCUS_MODE_FACEDETECT:
+		mode = 0x03;
+		break;
+
+	case FOCUS_MODE_TOUCH:
+		mode = 0x04;
+		cancel = 0;
+		break;
+
+	case FOCUS_MODE_INFINITY:
+		mode = 0x06;
+		cancel = 0;
+		break;
+
+	default:
+		cam_warn("invalid value, %d", val);
+		val = FOCUS_MODE_AUTO;
+		goto retry;
+	}
+
+	if (cancel) {
+		m5mo_set_af(sd, 0);
+		m5mo_set_lock(sd, 0);
+	} else {
+		if (state->focus.mode == val)
+			return 0;
+	}
+
+	cam_dbg("E, value %d\n", val);
+
+	if (val == FOCUS_MODE_FACEDETECT) {
+		/* enable face detection */
+		err = m5mo_writeb(sd, M5MO_CATEGORY_FD, M5MO_FD_CTL, 0x11);
+		CHECK_ERR(err);
+		msleep(10);
+	} else if (state->focus.mode == FOCUS_MODE_FACEDETECT) {
+		/* disable face detection */
+		err = m5mo_writeb(sd, M5MO_CATEGORY_FD, M5MO_FD_CTL, 0x00);
+		CHECK_ERR(err);
+	}
+
+#ifndef CONFIG_MACH_S2PLUS
+	if (val == FOCUS_MODE_MACRO)
+		regulator_set_current_limit(movie, 15000, 17000);
+	else if (state->focus.mode == FOCUS_MODE_MACRO)
+		regulator_set_current_limit(movie, 90000, 110000);
+#endif
+
+	state->focus.mode = val;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_LENS, M5MO_LENS_AF_MODE, mode);
+	CHECK_ERR(err);
+
+	for (i = M5MO_I2C_VERIFY; i; i--) {
+		msleep(10);
+		err = m5mo_readb(sd, M5MO_CATEGORY_LENS,
+			M5MO_LENS_AF_STATUS, &status);
+		CHECK_ERR(err);
+
+		if (!(status & 0x01))
+			break;
+	}
+
+	if ((status & 0x01) != 0x00) {
+		cam_err("failed\n");
+		return -ETIMEDOUT;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_touch_auto_focus(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err = 0;
+	cam_info("%s\n", val ? "start" : "stop");
+
+	state->focus.touch = val;
+
+	if (val) {
+		err = m5mo_set_af_mode(sd, FOCUS_MODE_TOUCH);
+		if (err < 0) {
+			cam_err("m5mo_set_af_mode failed\n");
+			return err;
+		}
+		err = m5mo_writew(sd, M5MO_CATEGORY_LENS,
+				M5MO_LENS_AF_TOUCH_POSX, state->focus.pos_x);
+		CHECK_ERR(err);
+		err = m5mo_writew(sd, M5MO_CATEGORY_LENS,
+				M5MO_LENS_AF_TOUCH_POSY, state->focus.pos_y);
+		CHECK_ERR(err);
+	}
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int m5mo_set_zoom(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	int zoom[] = { 1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 17, 18, 19,
+		20, 21, 22, 24, 25, 26, 28, 29, 30, 31, 32, 34, 35, 36, 38, 39};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_MON, M5MO_MON_ZOOM, zoom[val]);
+	CHECK_ERR(err);
+
+	state->zoom = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_jpeg_quality(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, ratio, err;
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m5mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_JPEG_RATIO, 0x62);
+	CHECK_ERR(err);
+
+	if (val <= 65)		/* Normal */
+		ratio = 0x0A;
+	else if (val <= 75)	/* Fine */
+		ratio = 0x05;
+	else			/* Superfine */
+		ratio = 0x00;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_JPEG_RATIO_OFS, ratio);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_get_exif(struct v4l2_subdev *sd)
+{
+	struct m5mo_state *state = to_state(sd);
+	/* standard values */
+	u16 iso_std_values[] = { 10, 12, 16, 20, 25, 32, 40, 50, 64, 80,
+		100, 125, 160, 200, 250, 320, 400, 500, 640, 800,
+		1000, 1250, 1600, 2000, 2500, 3200, 4000, 5000, 6400, 8000};
+	/* quantization table */
+	u16 iso_qtable[] = { 11, 14, 17, 22, 28, 35, 44, 56, 71, 89,
+		112, 141, 178, 224, 282, 356, 449, 565, 712, 890,
+		1122, 1414, 1782, 2245, 2828, 3564, 4490, 5657, 7127, 8909};
+	int num, den, i, err;
+
+	/* exposure time */
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF,
+		M5MO_EXIF_EXPTIME_NUM, &num);
+	CHECK_ERR(err);
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF,
+		M5MO_EXIF_EXPTIME_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.exptime = (u32)num*1000/den;
+
+	/* flash */
+	err = m5mo_readw(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_FLASH, &num);
+	CHECK_ERR(err);
+	state->exif.flash = (u16)num;
+
+	/* iso */
+	err = m5mo_readw(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_ISO, &num);
+	CHECK_ERR(err);
+	for (i = 0; i < NELEMS(iso_qtable); i++) {
+		if (num <= iso_qtable[i]) {
+			state->exif.iso = iso_std_values[i];
+			break;
+		}
+	}
+
+	/* shutter speed */
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_TV_NUM, &num);
+	CHECK_ERR(err);
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_TV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.tv = num*M5MO_DEF_APEX_DEN/den;
+
+	/* brightness */
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_BV_NUM, &num);
+	CHECK_ERR(err);
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_BV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.bv = num*M5MO_DEF_APEX_DEN/den;
+
+	/* exposure */
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_EBV_NUM, &num);
+	CHECK_ERR(err);
+	err = m5mo_readl(sd, M5MO_CATEGORY_EXIF, M5MO_EXIF_EBV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.ebv = num*M5MO_DEF_APEX_DEN/den;
+
+	return err;
+}
+
+static int m5mo_start_capture(struct v4l2_subdev *sd, int val)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err, int_factor;
+	cam_trace("E\n");
+
+	if (!(state->isp.int_factor & M5MO_INT_CAPTURE)) {
+		int_factor = m5mo_wait_interrupt(sd,
+			state->face_beauty ? M5MO_ISP_AFB_TIMEOUT : M5MO_ISP_TIMEOUT);
+		if (!(int_factor & M5MO_INT_CAPTURE)) {
+			cam_warn("M5MO_INT_CAPTURE isn't issued, %#x\n", int_factor);
+			return -ETIMEDOUT;
+		}
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_FRM_SEL, 0x01);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL,
+		M5MO_CAPCTRL_TRANSFER, 0x01);
+	int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+	if (!(int_factor & M5MO_INT_CAPTURE)) {
+		cam_warn("M5MO_INT_CAPTURE isn't issued on transfer, %#x\n", int_factor);
+		return -ETIMEDOUT;
+	}
+
+	err = m5mo_readl(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_IMG_SIZE,
+				&state->jpeg.main_size);
+	CHECK_ERR(err);
+	err = m5mo_readl(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_THUMB_SIZE,
+				&state->jpeg.thumb_size);
+	CHECK_ERR(err);
+
+	state->jpeg.main_offset = 0;
+	state->jpeg.thumb_offset = M5MO_JPEG_MAXSIZE;
+	state->jpeg.postview_offset = M5MO_JPEG_MAXSIZE + M5MO_THUMB_MAXSIZE;
+
+	m5mo_get_exif(sd);
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int m5mo_set_hdr(struct v4l2_subdev *sd, int val)
+{
+	u32 int_factor;
+	int err;
+	cam_trace("E\n");
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_FRM_SEL, val + 1);
+		CHECK_ERR(err);
+
+		int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+	if (!(int_factor & M5MO_INT_CAPTURE)) {
+		cam_warn("M5MO_INT_CAPTURE isn't issued on transfer, %#x\n", int_factor);
+			return -ETIMEDOUT;
+	}
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_TRANSFER, 0x01);
+		int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+	if (!(int_factor & M5MO_INT_CAPTURE)) {
+		cam_warn("M5MO_INT_CAPTURE isn't issued on transfer, %#x\n", int_factor);
+		return -ETIMEDOUT;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_set_aeawblock(struct v4l2_subdev *sd, int val)
+{
+	int err;
+
+	cam_err("%d\n", val);
+	switch (val) {
+	case AE_UNLOCK_AWB_UNLOCK:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_LOCK, 0);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB, M5MO_AWB_LOCK, 0);
+		CHECK_ERR(err);
+		break;
+
+	case AE_LOCK_AWB_UNLOCK:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_LOCK, 1);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB, M5MO_AWB_LOCK, 0);
+		CHECK_ERR(err);
+		break;
+
+	case AE_UNLOCK_AWB_LOCK:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_LOCK, 0);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB, M5MO_AWB_LOCK, 1);
+		CHECK_ERR(err);
+		break;
+
+	case AE_LOCK_AWB_LOCK:
+		err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_LOCK, 1);
+		CHECK_ERR(err);
+		err = m5mo_writeb(sd, M5MO_CATEGORY_WB, M5MO_AWB_LOCK, 1);
+		CHECK_ERR(err);
+		break;
+	}
+	cam_err("X\n");
+	return 0;
+}
+
+static int m5mo_check_dataline(struct v4l2_subdev *sd, int val)
+{
+	int err = 0;
+
+	cam_dbg("E, value %d\n", val);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_TEST,
+		M5MO_TEST_OUTPUT_YCO_TEST_DATA, val ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_check_esd(struct v4l2_subdev *sd)
+{
+	s32 val = 0;
+	int err = 0;
+
+	/* check ISP */
+	err = m5mo_readb(sd, M5MO_CATEGORY_TEST, M5MO_TEST_ISP_PROCESS, &val);
+	CHECK_ERR(err);
+	cam_dbg("progress %#x\n", val);
+
+	if (val != 0x80) {
+		goto esd_occur;
+	} else {
+		m5mo_wait_interrupt(sd, M5MO_ISP_ESD_TIMEOUT);
+
+		err = m5mo_readb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_ESD_INT, &val);
+		CHECK_ERR(err);
+
+		if (val & M5MO_INT_ESD)
+			goto esd_occur;
+	}
+
+	cam_warn("ESD is not detected\n");
+	return 0;
+
+esd_occur:
+	cam_warn("ESD shock is detected\n");
+	return -EIO;
+}
+
+static int m5mo_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err = 0;
+
+	printk(KERN_INFO "id %d, value %d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if (unlikely(state->isp.bad_fw && ctrl->id != V4L2_CID_CAM_UPDATE_FW)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_UPDATE_FW:
+		if (ctrl->value == FW_MODE_DUMP)
+			err = m5mo_dump_fw(sd);
+		else
+			err = m5mo_check_fw(sd);
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = m5mo_set_sensor_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		err = m5mo_set_flash(sd, ctrl->value, 0);
+		break;
+
+	case V4L2_CID_CAMERA_ISO:
+		err = m5mo_set_iso(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_METERING:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			err = m5mo_set_metering(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = m5mo_set_exposure(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		err = m5mo_set_whitebalance(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = m5mo_set_scene_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_EFFECT:
+		err = m5mo_set_effect(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_WDR:
+		err = m5mo_set_wdr(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_SHAKE:
+		err = m5mo_set_antishake(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BEAUTY_SHOT:
+		err = m5mo_set_face_beauty(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		err = m5mo_set_af_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		err = m5mo_set_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		state->focus.pos_x = ctrl->value;
+		/* FIXME - It should be fixed on F/W (touch AF offset) */
+	      if (state->preview != NULL) {
+			if (state->exif.unique_id[0] == 'T') {
+				if (state->preview->index == M5MO_PREVIEW_VGA)
+					state->focus.pos_x -= 40;
+				else if (state->preview->index ==
+					 M5MO_PREVIEW_WVGA)
+					state->focus.pos_x -= 50;
+			}
+		}
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		state->focus.pos_y = ctrl->value;
+		/* FIXME - It should be fixed on F/W (touch AF offset) */
+		if (state->preview != NULL) {
+			if (state->preview->index == M5MO_PREVIEW_VGA) {
+				if (state->exif.unique_id[0] == 'T')
+					state->focus.pos_y -=  50;
+			} else if (state->preview->index == M5MO_PREVIEW_WVGA) {
+				if (state->exif.unique_id[0] == 'T')
+					state->focus.pos_y -= 2;
+				else
+					state->focus.pos_y += 60;
+			}
+		}
+		break;
+
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		err = m5mo_set_touch_auto_focus(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ZOOM:
+		err = m5mo_set_zoom(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAM_JPEG_QUALITY:
+		err = m5mo_set_jpeg_quality(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CAPTURE:
+		err = m5mo_start_capture(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_HDR:
+		err = m5mo_set_hdr(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		err = m5mo_set_antibanding(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = m5mo_check_esd(sd);
+		break;
+
+	case V4L2_CID_CAMERA_AEAWB_LOCK_UNLOCK:
+		err = m5mo_set_aeawblock(sd, ctrl->value);
+		break;
+
+	default:
+		cam_err("no such control id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+		/*err = -ENOIOCTLCMD;*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+	return err;
+}
+
+static int m5mo_g_ext_ctrl(struct v4l2_subdev *sd, struct v4l2_ext_control *ctrl)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_SENSOR_FW_VER:
+		strcpy(ctrl->string, state->exif.unique_id);
+		break;
+
+	default:
+		cam_err("no such control id %d\n", ctrl->id - V4L2_CID_CAMERA_CLASS_BASE);
+		/*err = -ENOIOCTLCMD*/
+		/*err = 0;*/
+		break;
+	}
+
+	/* FIXME
+	 * if (err < 0 && err != -ENOIOCTLCMD)
+	 *	cam_err("failed, id %d\n", ctrl->id - V4L2_CID_CAMERA_CLASS_BASE);
+	 */
+
+	return err;
+}
+
+static int m5mo_g_ext_ctrls(struct v4l2_subdev *sd, struct v4l2_ext_controls *ctrls)
+{
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int i, err = 0;
+
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		err = m5mo_g_ext_ctrl(sd, ctrl);
+		if (err) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+	return err;
+}
+
+static int m5mo_check_manufacturer_id(struct v4l2_subdev *sd)
+{
+	int i, err;
+	u8 id;
+	u32 addr[] = {0x1000AAAA, 0x10005554, 0x1000AAAA};
+	u8 val[3][2] = {
+		[0] = {0x00, 0xAA},
+		[1] = {0x00, 0x55},
+		[2] = {0x00, 0x90},
+	};
+	u8 reset[] = {0x00, 0xF0};
+
+	/* set manufacturer's ID read-mode */
+	for (i = 0; i < 3; i++) {
+		err = m5mo_mem_write(sd, 0x06, 2, addr[i], val[i]);
+		CHECK_ERR(err);
+	}
+
+	/* read manufacturer's ID */
+	err = m5mo_mem_read(sd, sizeof(id), 0x10000001, &id);
+	CHECK_ERR(err);
+
+	/* reset manufacturer's ID read-mode */
+	err = m5mo_mem_write(sd, 0x06, sizeof(reset), 0x10000000, reset);
+	CHECK_ERR(err);
+
+	cam_dbg("%#x\n", id);
+
+	return id;
+}
+
+static int m5mo_program_fw(struct v4l2_subdev *sd,
+	u8 *buf, u32 addr, u32 unit, u32 count, u8 id)
+{
+	u32 val;
+	u32 intram_unit = SZ_4K;
+	int i, j, retries, err = 0;
+	int erase = 0x01;
+	if (unit == SZ_64K && id != 0x01)
+		erase = 0x04;
+
+	for (i = 0; i < unit*count; i += unit) {
+		/* Set Flash ROM memory address */
+		err = m5mo_writel(sd, M5MO_CATEGORY_FLASH,
+			M5MO_FLASH_ADDR, addr + i);
+		CHECK_ERR(err);
+
+		/* Erase FLASH ROM entire memory */
+		err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH,
+			M5MO_FLASH_ERASE, erase);
+		CHECK_ERR(err);
+		/* Response while sector-erase is operating */
+		retries = 0;
+		do {
+			mdelay(50);
+			err = m5mo_readb(sd, M5MO_CATEGORY_FLASH,
+				M5MO_FLASH_ERASE, &val);
+			CHECK_ERR(err);
+		} while (val == erase && retries++ < M5MO_I2C_VERIFY);
+
+		if (val != 0) {
+			cam_err("failed to erase sector\n");
+			return -1;
+		}
+
+		/* Set FLASH ROM programming size */
+		err = m5mo_writew(sd, M5MO_CATEGORY_FLASH, M5MO_FLASH_BYTE,
+			unit == SZ_64K ? 0 : unit);
+		CHECK_ERR(err);
+
+		/* Clear M-5MoLS internal RAM */
+		err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH,
+			M5MO_FLASH_RAM_CLEAR, 0x01);
+		CHECK_ERR(err);
+
+		/* Set Flash ROM programming address */
+		err = m5mo_writel(sd, M5MO_CATEGORY_FLASH,
+			M5MO_FLASH_ADDR, addr + i);
+		CHECK_ERR(err);
+
+		/* Send programmed firmware */
+		for (j = 0; j < unit; j += intram_unit) {
+			err = m5mo_mem_write(sd, 0x04, intram_unit,
+				M5MO_INT_RAM_BASE_ADDR + j, buf + i + j);
+			CHECK_ERR(err);
+			mdelay(10);
+		}
+
+		/* Start Programming */
+		err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH, M5MO_FLASH_WR, 0x01);
+		CHECK_ERR(err);
+
+		/* Confirm programming has been completed */
+		retries = 0;
+		do {
+			mdelay(50);
+			err = m5mo_readb(sd, M5MO_CATEGORY_FLASH,
+				M5MO_FLASH_WR, &val);
+			CHECK_ERR(err);
+		} while (val && retries++ < M5MO_I2C_VERIFY);
+
+		if (val != 0) {
+			cam_err("failed to program\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static int m5mo_load_fw(struct v4l2_subdev *sd)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	const struct firmware *fw = NULL;
+	u8 sensor_ver[M5MO_FW_VER_LEN] = {0, };
+	u8 *buf = NULL, val, id;
+	int offset;
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M5MO_FW_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n",
+			M5MO_FW_PATH, PTR_ERR(fp));
+		goto request_fw;
+	}
+
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+
+	cam_dbg("start, file path %s, size %ld Bytes\n", M5MO_FW_PATH, fsize);
+
+	buf = vmalloc(fsize);
+	if (!buf) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+
+	m5mo_get_sensor_fw_version(sd, sensor_ver);
+
+	if (sensor_ver[0] == 'T' && sensor_ver[1] == 'B') {
+		err = request_firmware(&fw, M5MOTB_FW_PATH, dev);
+#if defined(CONFIG_MACH_Q1_BD)
+	} else if (sensor_ver[0] == 'O' && sensor_ver[1] == 'O') {
+		err = request_firmware(&fw, M5MOOO_FW_PATH, dev);
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT) || defined(CONFIG_TARGET_LOCALE_NTT)
+	} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'B') {
+		err = request_firmware(&fw, M5MOSB_FW_PATH, dev);
+#endif
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+	} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'C') {
+		err = request_firmware(&fw, M5MOSC_FW_PATH, dev);
+#endif
+	} else {
+		cam_err("cannot find the matched F/W file\n");
+		err = -EINVAL;
+	}
+
+	if (err != 0) {
+		cam_err("request_firmware falied\n");
+			err = -EINVAL;
+			goto out;
+	}
+		cam_dbg("start, size %d Bytes\n", fw->size);
+		buf = (u8 *)fw->data;
+	}
+
+	/* set pin */
+	val = 0x7E;
+	err = m5mo_mem_write(sd, 0x04, sizeof(val), 0x50000308, &val);
+	if (err < 0) {
+		cam_err("i2c falied, err %d\n", err);
+		goto out;
+	}
+
+	id = m5mo_check_manufacturer_id(sd);
+	/* No Effect - compare unsigned with 0 */
+	/* FIXME
+	 * if (id < 0) {
+	 *	cam_err("i2c falied, err %d\n", id);
+	 *	goto out;
+	 *}
+	 */
+
+	/* select flash memory */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH,
+		M5MO_FLASH_SEL, id == 0x01 ? 0x00 : 0x01);
+	if (err < 0) {
+		cam_err("i2c falied, err %d\n", err);
+		goto out;
+	}
+
+	/* program FLSH ROM */
+	err = m5mo_program_fw(sd, buf, M5MO_FLASH_BASE_ADDR, SZ_64K, 31, id);
+	if (err < 0)
+		goto out;
+
+	offset = SZ_64K * 31;
+	if (id == 0x01) {
+		err = m5mo_program_fw(sd,
+			buf + offset, M5MO_FLASH_BASE_ADDR + offset, SZ_8K, 4, id);
+	} else {
+		err = m5mo_program_fw(sd,
+			buf + offset, M5MO_FLASH_BASE_ADDR + offset, SZ_4K, 8, id);
+	}
+
+	cam_dbg("end\n");
+
+out:
+	if (!fw_requested) {
+		vfree(buf);
+
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	return err;
+}
+
+/*
+ * v4l2_subdev_video_ops
+ */
+static const struct m5mo_frmsizeenum *m5mo_get_frmsize
+	(const struct m5mo_frmsizeenum *frmsizes, int num_entries, int index)
+{
+	int i;
+
+	for (i = 0; i < num_entries; i++) {
+		if (frmsizes[i].index == index)
+			return &frmsizes[i];
+	}
+
+	return NULL;
+}
+
+static int m5mo_set_frmsize(struct v4l2_subdev *sd)
+{
+	struct m5mo_state *state = to_state(sd);
+	struct v4l2_control ctrl;
+	int err;
+	cam_trace("E\n");
+
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		err = m5mo_set_mode(sd, M5MO_PARMSET_MODE);
+		CHECK_ERR(err);
+
+		err = m5mo_writeb(sd, M5MO_CATEGORY_PARM,
+			M5MO_PARM_MON_SIZE, state->preview->reg_val);
+		CHECK_ERR(err);
+
+		if (state->zoom) {
+			/* Zoom position returns to 1 when the monitor size is changed. */
+			ctrl.id = V4L2_CID_CAMERA_ZOOM;
+			ctrl.value = state->zoom;
+			m5mo_set_zoom(sd, &ctrl);
+		}
+
+		cam_info("preview frame size %dx%d\n",
+			state->preview->width, state->preview->height);
+	} else {
+		err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+			M5MO_CAPPARM_MAIN_IMG_SIZE, state->capture->reg_val);
+		CHECK_ERR(err);
+		cam_info("capture frame size %dx%d\n",
+			state->capture->width, state->capture->height);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *ffmt)
+{
+	struct m5mo_state *state = to_state(sd);
+	const struct m5mo_frmsizeenum **frmsize;
+
+	u32 width = ffmt->width;
+	u32 height = ffmt->height;
+	u32 old_index;
+	int i, num_entries;
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	state->format_mode = ffmt->field;
+
+	frmsize = state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW ?
+		&state->preview : &state->capture;
+
+	old_index = *frmsize ? (*frmsize)->index : -1;
+	*frmsize = NULL;
+
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		num_entries = ARRAY_SIZE(preview_frmsizes);
+		for (i = 0; i < num_entries; i++) {
+			if (width == preview_frmsizes[i].width &&
+				height == preview_frmsizes[i].height) {
+				*frmsize = &preview_frmsizes[i];
+				break;
+			}
+		}
+	} else {
+		num_entries = ARRAY_SIZE(capture_frmsizes);
+		for (i = 0; i < num_entries; i++) {
+			if (width == capture_frmsizes[i].width &&
+				height == capture_frmsizes[i].height) {
+				*frmsize = &capture_frmsizes[i];
+				break;
+			}
+		}
+	}
+
+	if (*frmsize == NULL) {
+		cam_warn("invalid frame size %dx%d\n", width, height);
+		*frmsize = state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW ?
+			m5mo_get_frmsize(preview_frmsizes, num_entries,
+				M5MO_PREVIEW_VGA) :
+			m5mo_get_frmsize(capture_frmsizes, num_entries,
+				M5MO_CAPTURE_3MP);
+	}
+
+	cam_dbg("%dx%d\n", (*frmsize)->width, (*frmsize)->height);
+	m5mo_set_frmsize(sd);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct m5mo_state *state = to_state(sd);
+
+	a->parm.capture.timeperframe.numerator = 1;
+	a->parm.capture.timeperframe.denominator = state->fps;
+
+	return 0;
+}
+
+static int m5mo_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err;
+
+	u32 fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	if (fps != state->fps) {
+		if (fps <= 0 || fps > 30) {
+			cam_err("invalid frame rate %d\n", fps);
+			fps = 30;
+		}
+		state->fps = fps;
+	}
+
+	err = m5mo_set_mode(sd, M5MO_PARMSET_MODE);
+	CHECK_ERR(err);
+
+	cam_dbg("fixed fps %d\n", state->fps);
+	err = m5mo_writeb(sd, M5MO_CATEGORY_PARM,
+		M5MO_PARM_FLEX_FPS, state->fps != 30 ? state->fps : 0);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int m5mo_enum_framesizes(struct v4l2_subdev *sd,
+	struct v4l2_frmsizeenum *fsize)
+{
+	struct m5mo_state *state = to_state(sd);
+
+	/*
+	* The camera interface should read this value, this is the resolution
+	* at which the sensor would provide framedata to the camera i/f
+	* In case of image capture,
+	* this returns the default camera resolution (VGA)
+	*/
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		if (state->preview == NULL /* FIXME || state->preview->index < 0 */)
+			return -EINVAL;
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->preview->width;
+		fsize->discrete.height = state->preview->height;
+	} else {
+		if (state->capture == NULL /* FIXME || state->capture->index < 0 */)
+			return -EINVAL;
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->capture->width;
+		fsize->discrete.height = state->capture->height;
+	}
+
+	return 0;
+}
+
+static int m5mo_s_stream_preview(struct v4l2_subdev *sd, int enable)
+{
+	struct m5mo_state *state = to_state(sd);
+	u32 old_mode, int_factor;
+	int err;
+
+	if (enable) {
+		if (state->vt_mode) {
+			err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_EP_MODE_MON, 0x11);
+			CHECK_ERR(err);
+		}
+
+		old_mode = m5mo_set_mode(sd, M5MO_MONITOR_MODE);
+		if (old_mode <= 0) {
+			cam_err("failed to set mode\n");
+			return old_mode;
+		}
+
+		if (old_mode != M5MO_MONITOR_MODE) {
+			int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+			if (!(int_factor & M5MO_INT_MODE)) {
+				cam_err("M5MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+		}
+
+		m5mo_set_lock(sd, 0);
+
+		if (state->check_dataline) {
+			err = m5mo_check_dataline(sd, state->check_dataline);
+			CHECK_ERR(err);
+		}
+	} else {
+	}
+
+	return 0;
+}
+
+static int m5mo_s_stream_capture(struct v4l2_subdev *sd, int enable)
+{
+	u32 int_factor;
+	int err;
+
+	if (enable) {
+		err = m5mo_set_mode(sd, M5MO_STILLCAP_MODE);
+		if (err <= 0) {
+			cam_err("failed to set mode\n");
+			return err;
+		}
+
+		int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+		if (!(int_factor & M5MO_INT_SOUND)) {
+			cam_err("M5MO_INT_SOUND isn't issued, %#x\n",
+				int_factor);
+			return -ETIMEDOUT;
+		}
+	} else {
+	}
+	return 0;
+}
+
+static int m5mo_s_stream_hdr(struct v4l2_subdev *sd, int enable)
+{
+	struct m5mo_state *state = to_state(sd);
+	int int_en, int_factor, i, err;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL,
+		M5MO_CAPCTRL_CAP_MODE, enable ? 0x06 : 0x00);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_YUVOUT_MAIN, enable ? 0x00 : 0x21);
+		CHECK_ERR(err);
+
+	err = m5mo_readb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_INT_EN, &int_en);
+		CHECK_ERR(err);
+
+	if (enable)
+		int_en |= M5MO_INT_FRAME_SYNC;
+	else
+		int_en &= ~M5MO_INT_FRAME_SYNC;
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_INT_EN, int_en);
+		CHECK_ERR(err);
+
+	if (enable) {
+		err = m5mo_set_mode(sd, M5MO_STILLCAP_MODE);
+		if (err <= 0) {
+			cam_err("failed to set mode\n");
+			return err;
+		}
+
+		/* convert raw to jpeg by the image data processing and store memory on ISP
+		and receive preview jpeg image from ISP */
+		for (i = 0; i < 3; i++) {
+			int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+			if (!(int_factor & M5MO_INT_FRAME_SYNC)) {
+				cam_err("M5MO_INT_FRAME_SYNC isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+		}
+
+		/* stop ring-buffer */
+		if (!(state->isp.int_factor & M5MO_INT_CAPTURE)) {
+			/* FIXME - M5MO_INT_FRAME_SYNC interrupt should be issued just three times */
+			for (i = 0; i < 9; i++) {
+				int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+				if (int_factor & M5MO_INT_CAPTURE)
+					break;
+
+				cam_err("M5MO_INT_CAPTURE isn't issued, %#x\n", int_factor);
+			}
+		}
+	} else {
+	}
+	return 0;
+}
+
+static int m5mo_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct m5mo_state *state = to_state(sd);
+	int err;
+
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (enable) {
+	case STREAM_MODE_CAM_ON:
+	case STREAM_MODE_CAM_OFF:
+		switch (state->format_mode) {
+		case V4L2_PIX_FMT_MODE_CAPTURE:
+			cam_info("capture %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+			err = m5mo_s_stream_capture(sd, enable == STREAM_MODE_CAM_ON);
+			break;
+		case V4L2_PIX_FMT_MODE_HDR:
+			err = m5mo_s_stream_hdr(sd, enable == STREAM_MODE_CAM_ON);
+			break;
+		default:
+			cam_info("preview %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+			err = m5mo_s_stream_preview(sd, enable == STREAM_MODE_CAM_ON);
+			break;
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		state->recording = 1;
+		if (state->flash_mode != FLASH_MODE_OFF)
+			err = m5mo_set_flash(sd, state->flash_mode, 1);
+
+		if (state->preview->index == M5MO_PREVIEW_720P ||
+				state->preview->index == M5MO_PREVIEW_1080P)
+			err = m5mo_set_af(sd, 1);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		if (state->preview->index == M5MO_PREVIEW_720P ||
+				state->preview->index == M5MO_PREVIEW_1080P)
+			err = m5mo_set_af(sd, 0);
+
+		m5mo_set_flash(sd, FLASH_MODE_OFF, 1);
+
+		state->recording = 0;
+		break;
+
+	default:
+		cam_err("invalid stream option, %d\n", enable);
+		break;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_check_version(struct v4l2_subdev *sd)
+{
+	struct m5mo_state *state = to_state(sd);
+	int i, val;
+
+	for (i = 0; i < 6; i++) {
+		m5mo_readb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_USER_VER, &val);
+		state->exif.unique_id[i] = (char)val;
+	}
+	state->exif.unique_id[i] = '\0';
+
+	cam_info("*************************************\n");
+	cam_info("F/W Version: %s\n", state->exif.unique_id);
+	cam_dbg("Binary Released: %s %s\n", __DATE__, __TIME__);
+	cam_info("*************************************\n");
+
+	return 0;
+}
+
+static int m5mo_init_param(struct v4l2_subdev *sd)
+{
+	int err;
+	cam_trace("E\n");
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_SYS, M5MO_SYS_INT_EN,
+		M5MO_INT_MODE | M5MO_INT_CAPTURE | M5MO_INT_SOUND);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_PARM, M5MO_PARM_OUT_SEL, 0x02);
+	CHECK_ERR(err);
+
+	/* Capture */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPPARM, M5MO_CAPPARM_YUVOUT_MAIN, 0x21);
+	CHECK_ERR(err);
+
+	err = m5mo_writel(sd, M5MO_CATEGORY_CAPPARM,
+		M5MO_CAPPARM_THUMB_JPEG_MAX, M5MO_THUMB_MAXSIZE);
+	CHECK_ERR(err);
+
+	/* Face detect */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_FD, M5MO_FD_SIZE, 0x01);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_FD, M5MO_FD_MAX, 0x0B);
+	CHECK_ERR(err);
+
+	/* HDR */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_CAPCTRL, M5MO_CAPCTRL_CAP_FRM_COUNT, 0x03);
+	CHECK_ERR(err);
+
+	err = m5mo_writeb(sd, M5MO_CATEGORY_AE, M5MO_AE_AUTO_BRACKET_EV, 0x64);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m5mo_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct m5mo_state *state = to_state(sd);
+	u32 int_factor;
+	int err;
+
+	/* Default state values */
+	state->preview = NULL;
+	state->capture = NULL;
+
+	state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	state->sensor_mode = SENSOR_CAMERA;
+	state->flash_mode = FLASH_MODE_OFF;
+	state->scene_mode = SCENE_MODE_NONE;
+
+	state->face_beauty = 0;
+
+	state->fps = 0;			/* auto */
+
+	state->isp.bad_fw = 0;
+	state->isp.issued = 0;
+
+	memset(&state->focus, 0, sizeof(state->focus));
+
+	/* start camera program(parallel FLASH ROM) */
+	err = m5mo_writeb(sd, M5MO_CATEGORY_FLASH,
+		M5MO_FLASH_CAM_START, 0x01);
+	CHECK_ERR(err);
+
+	int_factor = m5mo_wait_interrupt(sd, M5MO_ISP_TIMEOUT);
+	if (!(int_factor & M5MO_INT_MODE)) {
+		cam_err("firmware was erased?\n");
+		state->isp.bad_fw = 1;
+		return -ENOSYS;
+	}
+
+	/* check up F/W version */
+	err = m5mo_check_version(sd);
+	CHECK_ERR(err);
+
+	m5mo_init_param(sd);
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops m5mo_core_ops = {
+	.init = m5mo_init,		/* initializing API */
+	.load_fw = m5mo_load_fw,
+	.queryctrl = m5mo_queryctrl,
+	.g_ctrl = m5mo_g_ctrl,
+	.s_ctrl = m5mo_s_ctrl,
+	.g_ext_ctrls = m5mo_g_ext_ctrls,
+};
+
+static const struct v4l2_subdev_video_ops m5mo_video_ops = {
+	.s_mbus_fmt = m5mo_s_fmt,
+	.g_parm = m5mo_g_parm,
+	.s_parm = m5mo_s_parm,
+	.enum_framesizes = m5mo_enum_framesizes,
+	.s_stream = m5mo_s_stream,
+};
+
+static const struct v4l2_subdev_ops m5mo_ops = {
+	.core = &m5mo_core_ops,
+	.video = &m5mo_video_ops,
+};
+
+static ssize_t m5mo_camera_type_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct m5mo_state *state = dev_get_drvdata(dev);
+	char type[25];
+
+	if (state->exif.unique_id[1] == 'B') {
+		strcpy(type, "SONY_IMX105PQ_M5MOLS");
+	} else if (state->exif.unique_id[1] == 'C') {
+		strcpy(type, "SLSI_S5K3H2YX_M5MOLS");
+	} else {
+		cam_warn("cannot find the matched camera type\n");
+		strcpy(type, "SONY_IMX105PQ_M5MOLS");
+	}
+
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t m5mo_camera_fw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct m5mo_state *state = dev_get_drvdata(dev);
+	return sprintf(buf, "%s\n", state->fw_version);
+}
+
+static DEVICE_ATTR(rear_camtype, S_IRUGO, m5mo_camera_type_show, NULL);
+static DEVICE_ATTR(rear_camfw, S_IRUGO, m5mo_camera_fw_show, NULL);
+
+/*
+ * m5mo_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int __devinit m5mo_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct m5mo_state *state;
+	struct v4l2_subdev *sd;
+
+	const struct m5mo_platform_data *pdata = client->dev.platform_data;
+	int err = 0;
+
+	state = kzalloc(sizeof(struct m5mo_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, M5MO_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &m5mo_ops);
+
+#ifdef CAM_DEBUG
+	state->dbg_level = CAM_DEBUG;
+#endif
+#ifndef CONFIG_MACH_S2PLUS
+	if (state->m5mo_dev == NULL) {
+		state->m5mo_dev =
+		    device_create(camera_class, NULL, 0, NULL, "rear");
+		if (IS_ERR(state->m5mo_dev)) {
+			cam_err("failed to create device m5mo_dev!\n");
+		} else {
+			dev_set_drvdata(state->m5mo_dev, state);
+			if (device_create_file
+			    (state->m5mo_dev, &dev_attr_rear_camtype) < 0) {
+				cam_err("failed to create device file, %s\n",
+				dev_attr_rear_camtype.attr.name);
+			}
+			if (device_create_file
+			    (state->m5mo_dev, &dev_attr_rear_camfw) < 0) {
+				cam_err("failed to create device file, %s\n",
+				dev_attr_rear_camfw.attr.name);
+			}
+		}
+	}
+#endif
+	/* wait queue initialize */
+	init_waitqueue_head(&state->isp.wait);
+
+	if (pdata->config_isp_irq)
+		pdata->config_isp_irq();
+
+	err = request_irq(pdata->irq,
+		m5mo_isp_isr, IRQF_TRIGGER_RISING, "m5mo isp", sd);
+	if (err) {
+		cam_err("failed to request irq\n");
+		return err;
+	}
+	state->isp.irq = pdata->irq;
+	state->isp.issued = 0;
+
+	printk("%s\n", __func__);
+
+	return 0;
+}
+
+static int __devexit m5mo_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct m5mo_state *state = to_state(sd);
+
+	if (m5mo_set_af_softlanding(sd) < 0)
+		cam_err("failed to set soft landing\n");
+
+	device_remove_file(state->m5mo_dev, &dev_attr_rear_camtype);
+	device_remove_file(state->m5mo_dev, &dev_attr_rear_camfw);
+	device_destroy(camera_class, 0);
+	state->m5mo_dev = NULL;
+
+	if (state->isp.irq > 0)
+		free_irq(state->isp.irq, sd);
+
+	v4l2_device_unregister_subdev(sd);
+
+	kfree(state->fw_version);
+	kfree(state);
+
+	return 0;
+}
+
+static const struct i2c_device_id m5mo_id[] = {
+	{ M5MO_DRIVER_NAME, 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, m5mo_id);
+
+static struct i2c_driver m5mo_i2c_driver = {
+	.driver = {
+		.name	= M5MO_DRIVER_NAME,
+	},
+	.probe		= m5mo_probe,
+	.remove		= __devexit_p(m5mo_remove),
+	.id_table	= m5mo_id,
+};
+
+static int __init m5mo_mod_init(void)
+{
+#ifdef CONFIG_MACH_S2PLUS
+	if (!m5mo_dev) {
+		m5mo_dev =
+		device_create(camera_class, NULL, 0, NULL, "rear");
+		if (IS_ERR(m5mo_dev)) {
+			cam_err("failed to create device m5mo_dev!\n");
+			return 0;
+		}
+		if (device_create_file
+		(m5mo_dev, &dev_attr_rear_camtype) < 0) {
+			cam_err("failed to create device file, %s\n",
+			dev_attr_rear_camtype.attr.name);
+		}
+		if (device_create_file
+		(m5mo_dev, &dev_attr_rear_camfw) < 0) {
+			cam_err("failed to create device file, %s\n",
+			dev_attr_rear_camfw.attr.name);
+		}
+	}
+#else
+	camera_class = class_create(THIS_MODULE, "camera");
+	if (IS_ERR(camera_class))
+		pr_err("Failed to create class(camera)!\n");
+#endif
+	return i2c_add_driver(&m5mo_i2c_driver);
+}
+
+static void __exit m5mo_mod_exit(void)
+{
+	i2c_del_driver(&m5mo_i2c_driver);
+	if (camera_class)
+		class_destroy(camera_class);
+}
+module_init(m5mo_mod_init);
+module_exit(m5mo_mod_exit);
+
+
+MODULE_AUTHOR("Goeun Lee <ge.lee@samsung.com>");
+MODULE_DESCRIPTION("driver for Fusitju M5MO LS 8MP camera");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/m5mo.h b/drivers/media/video/m5mo.h
new file mode 100644
index 0000000..8d41584
--- /dev/null
+++ b/drivers/media/video/m5mo.h
@@ -0,0 +1,345 @@
+/*
+ * Driver for M5MO (5MP Camera) from NEC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __M5MO_H
+#define __M5MO_H
+
+#include <linux/wakelock.h>
+
+#define CONFIG_CAM_DEBUG
+
+#define cam_warn(fmt, ...)	\
+	do { \
+		printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_err(fmt, ...)	\
+	do { \
+		printk(KERN_ERR "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_info(fmt, ...)	\
+	do { \
+		printk(KERN_INFO "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#ifdef CONFIG_CAM_DEBUG
+#define CAM_DEBUG   (1 << 0)
+#define CAM_TRACE   (1 << 1)
+#define CAM_I2C     (1 << 2)
+
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_DEBUG) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_TRACE) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_i2c_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_I2C) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+#else
+#define cam_dbg(fmt, ...)
+#define cam_trace(fmt, ...)
+#define cam_i2c_dbg(fmt, ...)
+#endif
+
+enum m5mo_prev_frmsize {
+	M5MO_PREVIEW_QCIF,
+	M5MO_PREVIEW_QCIF2,
+	M5MO_PREVIEW_QVGA,
+	M5MO_PREVIEW_VGA,
+	M5MO_PREVIEW_D1,
+	M5MO_PREVIEW_WVGA,
+	M5MO_PREVIEW_720P,
+#if defined(CONFIG_MACH_Q1_BD)
+	M5MO_PREVIEW_880_720,
+	M5MO_PREVIEW_1200_800,
+	M5MO_PREVIEW_1280_800,
+	M5MO_PREVIEW_1280_768,
+	M5MO_PREVIEW_1072_800,
+	M5MO_PREVIEW_980_800,
+#endif
+	M5MO_PREVIEW_1080P,
+	M5MO_PREVIEW_HDR,
+};
+
+enum m5mo_cap_frmsize {
+	M5MO_CAPTURE_VGA,	/* 640 x 480 */
+	M5MO_CAPTURE_WVGA,	/* 800 x 480 */
+	M5MO_CAPTURE_W1MP,	/* 1600 x 960 */
+	M5MO_CAPTURE_2MP,	/* UXGA - 1600 x 1200 */
+	M5MO_CAPTURE_W2MP,	/* 2048 x 1232 */
+	M5MO_CAPTURE_3MP,	/* QXGA - 2048 x 1536 */
+	M5MO_CAPTURE_W4MP,	/* WQXGA - 2560 x 1536 */
+	M5MO_CAPTURE_5MP,	/* 2560 x 1920 */
+	M5MO_CAPTURE_W6MP,	/* 3072 x 1856 */
+	M5MO_CAPTURE_7MP,	/* 3072 x 2304 */
+	M5MO_CAPTURE_W7MP,	/* WQXGA - 2560 x 1536 */
+	M5MO_CAPTURE_8MP,	/* 3264 x 2448 */
+};
+
+struct m5mo_control {
+	u32 id;
+	s32 value;
+	s32 minimum;		/* Note signedness */
+	s32 maximum;
+	s32 step;
+	s32 default_value;
+};
+
+struct m5mo_frmsizeenum {
+	unsigned int index;
+	unsigned int width;
+	unsigned int height;
+	u8 reg_val;		/* a value for category parameter */
+};
+
+struct m5mo_isp {
+	wait_queue_head_t wait;
+	unsigned int irq;	/* irq issued by ISP */
+	unsigned int issued;
+	unsigned int int_factor;
+	unsigned int bad_fw:1;
+};
+
+struct m5mo_jpeg {
+	int quality;
+	unsigned int main_size;	/* Main JPEG file size */
+	unsigned int thumb_size;	/* Thumbnail file size */
+	unsigned int main_offset;
+	unsigned int thumb_offset;
+	unsigned int postview_offset;
+};
+
+struct m5mo_focus {
+	unsigned int start:1;
+	unsigned int lock:1;
+	unsigned int touch:1;
+
+	unsigned int mode;
+#if defined(CONFIG_TARGET_LOCALE_NA)
+	unsigned int ui_mode;
+	unsigned int mode_select;
+#endif
+	unsigned int status;
+
+	unsigned int pos_x;
+	unsigned int pos_y;
+};
+
+struct m5mo_exif {
+	char unique_id[7];
+	u32 exptime;		/* us */
+	u16 flash;
+	u16 iso;
+	int tv;			/* shutter speed */
+	int bv;			/* brightness */
+	int ebv;		/* exposure bias */
+};
+
+struct m5mo_state {
+	struct m5mo_platform_data *pdata;
+	struct device *m5mo_dev;
+	struct v4l2_subdev sd;
+
+	struct wake_lock wake_lock;
+
+	struct m5mo_isp isp;
+
+	const struct m5mo_frmsizeenum *preview;
+	const struct m5mo_frmsizeenum *capture;
+
+	enum v4l2_pix_format_mode format_mode;
+	enum v4l2_sensor_mode sensor_mode;
+	enum v4l2_flash_mode flash_mode;
+	enum v4l2_scene_mode scene_mode;
+	int vt_mode;
+	int zoom;
+
+	unsigned int fps;
+	struct m5mo_focus focus;
+
+	struct m5mo_jpeg jpeg;
+	struct m5mo_exif exif;
+
+	char *fw_version;
+
+#ifdef CONFIG_CAM_DEBUG
+	u8 dbg_level;
+#endif
+
+	unsigned int face_beauty:1;
+	unsigned int recording:1;
+	unsigned int check_dataline:1;
+	int anti_banding;
+};
+
+/* Category */
+#define M5MO_CATEGORY_SYS	0x00
+#define M5MO_CATEGORY_PARM	0x01
+#define M5MO_CATEGORY_MON	0x02
+#define M5MO_CATEGORY_AE	0x03
+#define M5MO_CATEGORY_WB	0x06
+#define M5MO_CATEGORY_EXIF	0x07
+#define M5MO_CATEGORY_FD	0x09
+#define M5MO_CATEGORY_LENS	0x0A
+#define M5MO_CATEGORY_CAPPARM	0x0B
+#define M5MO_CATEGORY_CAPCTRL	0x0C
+#define M5MO_CATEGORY_TEST	0x0D
+#define M5MO_CATEGORY_ADJST	0x0E
+#define M5MO_CATEGORY_FLASH	0x0F    /* F/W update */
+
+/* M5MO_CATEGORY_SYS: 0x00 */
+#define M5MO_SYS_PJT_CODE	0x01
+#define M5MO_SYS_VER_FW		0x02
+#define M5MO_SYS_VER_HW		0x04
+#define M5MO_SYS_VER_PARAM	0x06
+#define M5MO_SYS_VER_AWB	0x08
+#define M5MO_SYS_USER_VER	0x0A
+#define M5MO_SYS_MODE		0x0B
+#define M5MO_SYS_ESD_INT	0x0E
+#define M5MO_SYS_INT_FACTOR	0x10
+#define M5MO_SYS_INT_EN		0x11
+
+/* M5MO_CATEGORY_PARAM: 0x01 */
+#define M5MO_PARM_OUT_SEL	0x00
+#define M5MO_PARM_MON_SIZE	0x01
+#define M5MO_PARM_EFFECT	0x0B
+#define M5MO_PARM_FLEX_FPS	0x31
+#define M5MO_PARM_HDMOVIE	0x32
+
+/* M5MO_CATEGORY_MON: 0x02 */
+#define M5MO_MON_ZOOM		0x01
+#define M5MO_MON_MON_REVERSE	0x05
+#define M5MO_MON_MON_MIRROR	0x06
+#define M5MO_MON_SHOT_REVERSE	0x07
+#define M5MO_MON_SHOT_MIRROR	0x08
+#define M5MO_MON_CFIXB		0x09
+#define M5MO_MON_CFIXR		0x0A
+#define M5MO_MON_COLOR_EFFECT	0x0B
+#define M5MO_MON_CHROMA_LVL	0x0F
+#define M5MO_MON_EDGE_LVL	0x11
+#define M5MO_MON_TONE_CTRL	0x25
+
+/* M5MO_CATEGORY_AE: 0x03 */
+#define M5MO_AE_LOCK		0x00
+#define M5MO_AE_MODE		0x01
+#define M5MO_AE_ISOSEL		0x05
+#define M5MO_AE_FLICKER		0x06
+#define M5MO_AE_EP_MODE_MON	0x0A
+#define M5MO_AE_EP_MODE_CAP	0x0B
+#define M5MO_AE_AUTO_BRACKET_EV	0x20
+#define M5MO_AE_ONESHOT_MAX_EXP	0x36
+#define M5MO_AE_INDEX		0x38
+
+/* M5MO_CATEGORY_WB: 0x06 */
+#define M5MO_AWB_LOCK		0x00
+#define M5MO_WB_AWB_MODE	0x02
+#define M5MO_WB_AWB_MANUAL	0x03
+
+/* M5MO_CATEGORY_EXIF: 0x07 */
+#define M5MO_EXIF_EXPTIME_NUM	0x00
+#define M5MO_EXIF_EXPTIME_DEN	0x04
+#define M5MO_EXIF_TV_NUM	0x08
+#define M5MO_EXIF_TV_DEN	0x0C
+#define M5MO_EXIF_BV_NUM	0x18
+#define M5MO_EXIF_BV_DEN	0x1C
+#define M5MO_EXIF_EBV_NUM	0x20
+#define M5MO_EXIF_EBV_DEN	0x24
+#define M5MO_EXIF_ISO		0x28
+#define M5MO_EXIF_FLASH		0x2A
+
+/* M5MO_CATEGORY_FD: 0x09 */
+#define M5MO_FD_CTL		0x00
+#define M5MO_FD_SIZE		0x01
+#define M5MO_FD_MAX		0x02
+
+/* M5MO_CATEGORY_LENS: 0x0A */
+#define M5MO_LENS_AF_MODE	0x01
+#define M5MO_LENS_AF_START	0x02
+#define M5MO_LENS_AF_STATUS	0x03
+#define M5MO_LENS_AF_MODE_SELECT	0x05
+#define M5MO_LENS_AF_UPBYTE_STEP	0x06
+#define M5MO_LENS_AF_LOWBYTE_STEP	0x07
+#define M5MO_LENS_AF_CAL	0x1D
+#define M5MO_LENS_AF_TOUCH_POSX	0x30
+#define M5MO_LENS_AF_TOUCH_POSY	0x32
+
+/* M5MO_CATEGORY_CAPPARM: 0x0B */
+#define M5MO_CAPPARM_YUVOUT_MAIN	0x00
+#define M5MO_CAPPARM_MAIN_IMG_SIZE	0x01
+#define M5MO_CAPPARM_YUVOUT_PREVIEW	0x05
+#define M5MO_CAPPARM_PREVIEW_IMG_SIZE	0x06
+#define M5MO_CAPPARM_YUVOUT_THUMB	0x0A
+#define M5MO_CAPPARM_THUMB_IMG_SIZE	0x0B
+#define M5MO_CAPPARM_JPEG_SIZE_MAX	0x0F
+#define M5MO_CAPPARM_JPEG_RATIO		0x17
+#define M5MO_CAPPARM_MCC_MODE		0x1D
+#define M5MO_CAPPARM_WDR_EN		0x2C
+#define M5MO_CAPPARM_LIGHT_CTRL		0x40
+#define M5MO_CAPPARM_FLASH_CTRL		0x41
+#define M5MO_CAPPARM_JPEG_RATIO_OFS	0x34
+#define M5MO_CAPPARM_THUMB_JPEG_MAX	0x3C
+#define M5MO_CAPPARM_AFB_CAP_EN		0x53
+
+/* M5MO_CATEGORY_CAPCTRL: 0x0C */
+#define M5MO_CAPCTRL_CAP_MODE	0x00
+#define M5MO_CAPCTRL_CAP_FRM_COUNT 0x02
+#define M5MO_CAPCTRL_FRM_SEL	0x06
+#define M5MO_CAPCTRL_TRANSFER	0x09
+#define M5MO_CAPCTRL_IMG_SIZE	0x0D
+#define M5MO_CAPCTRL_THUMB_SIZE	0x11
+
+/* M5MO_CATEGORY_ADJST: 0x0E */
+#define M5MO_ADJST_AWB_RG_H	0x3C
+#define M5MO_ADJST_AWB_RG_L	0x3D
+#define M5MO_ADJST_AWB_BG_H	0x3E
+#define M5MO_ADJST_AWB_BG_L	0x3F
+
+/* M5MO_CATEGORY_FLASH: 0x0F */
+#define M5MO_FLASH_ADDR		0x00
+#define M5MO_FLASH_BYTE		0x04
+#define M5MO_FLASH_ERASE	0x06
+#define M5MO_FLASH_WR		0x07
+#define M5MO_FLASH_RAM_CLEAR	0x08
+#define M5MO_FLASH_CAM_START	0x12
+#define M5MO_FLASH_SEL		0x13
+
+/* M5MO_CATEGORY_TEST:	0x0D */
+#define M5MO_TEST_OUTPUT_YCO_TEST_DATA	0x1B
+#define M5MO_TEST_ISP_PROCESS		0x59
+
+/* M5MO Sensor Mode */
+#define M5MO_SYSINIT_MODE	0x0
+#define M5MO_PARMSET_MODE	0x1
+#define M5MO_MONITOR_MODE	0x2
+#define M5MO_STILLCAP_MODE	0x3
+
+/* Interrupt Factor */
+#define M5MO_INT_SOUND		(1 << 7)
+#define M5MO_INT_LENS_INIT	(1 << 6)
+#define M5MO_INT_FD		(1 << 5)
+#define M5MO_INT_FRAME_SYNC	(1 << 4)
+#define M5MO_INT_CAPTURE	(1 << 3)
+#define M5MO_INT_ZOOM		(1 << 2)
+#define M5MO_INT_AF		(1 << 1)
+#define M5MO_INT_MODE		(1 << 0)
+
+/* ESD Interrupt */
+#define M5MO_INT_ESD		(1 << 0)
+
+#endif /* __M5MO_H */
diff --git a/drivers/media/video/m5mols/Kconfig b/drivers/media/video/m5mols/Kconfig
index 302dc3d..ddb3314 100644
--- a/drivers/media/video/m5mols/Kconfig
+++ b/drivers/media/video/m5mols/Kconfig
@@ -1,5 +1,6 @@
 config VIDEO_M5MOLS
 	tristate "Fujitsu M-5MOLS 8MP sensor support"
-	depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+	depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API &&\
+	(VIDEO_S5P_MIPI_CSIS || VIDEO_EXYNOS_MIPI_CSIS)
 	---help---
 	  This driver supports Fujitsu M-5MOLS camera sensor with ISP
diff --git a/drivers/media/video/m5mols/Makefile b/drivers/media/video/m5mols/Makefile
index 0a44e02..b5d19bf 100644
--- a/drivers/media/video/m5mols/Makefile
+++ b/drivers/media/video/m5mols/Makefile
@@ -1,3 +1,3 @@
-m5mols-objs	:= m5mols_core.o m5mols_controls.o m5mols_capture.o
+m5mols-objs	:= m5mols_core.o m5mols_controls.o
 
 obj-$(CONFIG_VIDEO_M5MOLS)		+= m5mols.o
diff --git a/drivers/media/video/m5mols/m5mols.h b/drivers/media/video/m5mols/m5mols.h
index 89d09a8..94022e2 100644
--- a/drivers/media/video/m5mols/m5mols.h
+++ b/drivers/media/video/m5mols/m5mols.h
@@ -1,5 +1,5 @@
 /*
- * Header for M-5MOLS 8M Pixel camera sensor with ISP
+ * Header for M5MOLS 8M Pixel camera sensor with ISP
  *
  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  * Author: HeungJun Kim <riverful.kim@samsung.com>
@@ -19,12 +19,24 @@
 #include <media/v4l2-subdev.h>
 #include "m5mols_reg.h"
 
-extern int m5mols_debug;
+#define M5MO_JPEG_MAXSIZE	0x3A0000
+#define M5MO_THUMB_MAXSIZE	0xFC00
+#define M5MO_POST_MAXSIZE	0xBB800
+#define M5MO_JPEG_MEMSIZE	M5MO_JPEG_MAXSIZE + M5MO_THUMB_MAXSIZE + M5MO_POST_MAXSIZE
 
-#define to_m5mols(__sd)	container_of(__sd, struct m5mols_info, sd)
+#define v4l2msg(fmt, arg...)	do {				\
+	v4l2_dbg(1, m5mols_debug, &info->sd, fmt, ## arg);	\
+} while (0)
 
-#define to_sd(__ctrl) \
-	(&container_of(__ctrl->handler, struct m5mols_info, handle)->sd)
+extern int m5mols_debug;
+
+enum m5mols_mode {
+	MODE_SYSINIT,
+	MODE_PARMSET,
+	MODE_MONITOR,
+	MODE_CAPTURE,
+	MODE_UNKNOWN,
+};
 
 enum m5mols_restype {
 	M5MOLS_RESTYPE_MONITOR,
@@ -32,266 +44,341 @@ enum m5mols_restype {
 	M5MOLS_RESTYPE_MAX,
 };
 
-/**
- * struct m5mols_resolution - structure for the resolution
- * @type: resolution type according to the pixel code
- * @width: width of the resolution
- * @height: height of the resolution
- * @reg: resolution preset register value
- */
+enum m5mols_status {
+	STATUS_SYSINIT,
+	STATUS_PARMSET,
+	STATUS_MONITOR,
+	STATUS_AUTO_FOCUS,
+	STATUS_FACE_DETECTION,
+	STATUS_DUAL_CAPTURE,
+	STATUS_SINGLE_CAPTURE,
+	STATUS_PREVIEW,
+	STATUS_UNKNOWN,
+};
+
+enum m5mols_intterrupt_bit {
+	INT_BIT_MODE,
+	INT_BIT_AF,
+	INT_BIT_ZOOM,
+	INT_BIT_CAPTURE,
+	INT_BIT_FRAME_SYNC,
+	INT_BIT_FD,
+	INT_BIT_LENS_INIT,
+	INT_BIT_SOUND,
+};
+
+enum m5mols_i2c_size {
+	I2C_8BIT	= 1,
+	I2C_16BIT	= 2,
+	I2C_32BIT	= 4,
+	I2C_MAX		= 4,
+};
+
+enum m5mols_fps {
+	M5MOLS_FPS_AUTO	= 0,
+	M5MOLS_FPS_10	= 10,
+	M5MOLS_FPS_12	= 12,
+	M5MOLS_FPS_15	= 15,
+	M5MOLS_FPS_20	= 20,
+	M5MOLS_FPS_21	= 21,
+	M5MOLS_FPS_22	= 22,
+	M5MOLS_FPS_23	= 23,
+	M5MOLS_FPS_24	= 24,
+	M5MOLS_FPS_30	= 30,
+	M5MOLS_FPS_MAX	= M5MOLS_FPS_30,
+};
+
+enum m5mols_res_type {
+	M5MOLS_RES_MON,
+	/* It's not supported below yet. */
+	M5MOLS_RES_CAPTURE,
+	M5MOLS_RES_MAX,
+};
+
 struct m5mols_resolution {
-	u8 reg;
-	enum m5mols_restype type;
-	u16 width;
-	u16 height;
+	u8			value;
+	enum m5mols_res_type	type;
+	u16			width;
+	u16			height;
 };
 
-/**
- * struct m5mols_exif - structure for the EXIF information of M-5MOLS
- * @exposure_time: exposure time register value
- * @shutter_speed: speed of the shutter register value
- * @aperture: aperture register value
- * @exposure_bias: it calls also EV bias
- * @iso_speed: ISO register value
- * @flash: status register value of the flash
- * @sdr: status register value of the Subject Distance Range
- * @qval: not written exact meaning in document
- */
-struct m5mols_exif {
-	u32 exposure_time;
-	u32 shutter_speed;
-	u32 aperture;
-	u32 brightness;
-	u32 exposure_bias;
-	u16 iso_speed;
-	u16 flash;
-	u16 sdr;
-	u16 qval;
+struct m5mols_format {
+	enum v4l2_mbus_pixelcode code;
+	enum v4l2_colorspace colorspace;
 };
 
-/**
- * struct m5mols_capture - Structure for the capture capability
- * @exif: EXIF information
- * @main: size in bytes of the main image
- * @thumb: size in bytes of the thumb image, if it was accompanied
- * @total: total size in bytes of the produced image
- */
-struct m5mols_capture {
-	struct m5mols_exif exif;
-	u32 main;
-	u32 thumb;
-	u32 total;
+struct m5mols_control {
+	u32	id;
+	s32	min;
+	s32	max;
+	u32	step;
+	s32	def;
 };
 
-/**
- * struct m5mols_scenemode - structure for the scenemode capability
- * @metering: metering light register value
- * @ev_bias: EV bias register value
- * @wb_mode: mode which means the WhiteBalance is Auto or Manual
- * @wb_preset: whitebalance preset register value in the Manual mode
- * @chroma_en: register value whether the Chroma capability is enabled or not
- * @chroma_lvl: chroma's level register value
- * @edge_en: register value Whether the Edge capability is enabled or not
- * @edge_lvl: edge's level register value
- * @af_range: Auto Focus's range
- * @fd_mode: Face Detection mode
- * @mcc: Multi-axis Color Conversion which means emotion color
- * @light: status of the Light
- * @flash: status of the Flash
- * @tone: Tone color which means Contrast
- * @iso: ISO register value
- * @capt_mode: Mode of the Image Stabilization while the camera capturing
- * @wdr: Wide Dynamic Range register value
- *
- * The each value according to each scenemode is recommended in the documents.
- */
-struct m5mols_scenemode {
-	u8 metering;
-	u8 ev_bias;
-	u8 wb_mode;
-	u8 wb_preset;
-	u8 chroma_en;
-	u8 chroma_lvl;
-	u8 edge_en;
-	u8 edge_lvl;
-	u8 af_range;
-	u8 fd_mode;
-	u8 mcc;
-	u8 light;
-	u8 flash;
-	u8 tone;
-	u8 iso;
-	u8 capt_mode;
-	u8 wdr;
+struct m5mols_exif {
+	u32	exposure_time;
+	u32	shutter_speed;
+	u32	aperture;
+	u32	brightness;
+	u32	exposure_bias;
+	u16	iso_speed;
+	u16	flash;
+	u16	sdr;		/* subject(object) distance range */
+	u16	qval;		/* This is not written precisely in datasheet. */
+};
+
+struct m5mols_capture {
+	struct m5mols_exif		exif;
+	u32				main;
+	u32				thumb;
+	u32				total;
 };
 
-/**
- * struct m5mols_version - firmware version information
- * @customer:	customer information
- * @project:	version of project information according to customer
- * @fw:		firmware revision
- * @hw:		hardware revision
- * @param:	version of the parameter
- * @awb:	Auto WhiteBalance algorithm version
- * @str:	information about manufacturer and packaging vendor
- * @af:		Auto Focus version
- *
- * The register offset starts the customer version at 0x0, and it ends
- * the awb version at 0x09. The customer, project information occupies 1 bytes
- * each. And also the fw, hw, param, awb each requires 2 bytes. The str is
- * unique string associated with firmware's version. It includes information
- * about manufacturer and the vendor of the sensor's packaging. The least
- * significant 2 bytes of the string indicate packaging manufacturer.
- */
-#define VERSION_STRING_SIZE	22
 struct m5mols_version {
-	u8	customer;
-	u8	project;
-	u16	fw;
-	u16	hw;
-	u16	param;
-	u16	awb;
-	u8	str[VERSION_STRING_SIZE];
-	u8	af;
+	u8	ctm_code;	/* customer code */
+	u8	pj_code;	/* project code */
+	u16	fw;		/* firmware version */
+	u16	hw;		/* hardware version */
+	u16	parm;		/* parameter version */
+	u16	awb;		/* AWB version */
 };
 
-/**
- * struct m5mols_info - M-5MOLS driver data structure
- * @pdata: platform data
- * @sd: v4l-subdev instance
- * @pad: media pad
- * @ffmt: current fmt according to resolution type
- * @res_type: current resolution type
- * @code: current code
- * @irq_waitq: waitqueue for the capture
- * @work_irq: workqueue for the IRQ
- * @flags: state variable for the interrupt handler
- * @handle: control handler
- * @autoexposure: Auto Exposure control
- * @exposure: Exposure control
- * @autowb: Auto White Balance control
- * @colorfx: Color effect control
- * @saturation:	Saturation control
- * @zoom: Zoom control
- * @ver: information of the version
- * @cap: the capture mode attributes
- * @power: current sensor's power status
- * @ctrl_sync: true means all controls of the sensor are initialized
- * @int_capture: true means the capture interrupt is issued once
- * @lock_ae: true means the Auto Exposure is locked
- * @lock_awb: true means the Aut WhiteBalance is locked
- * @resolution:	register value for current resolution
- * @interrupt: register value for current interrupt status
- * @mode: register value for current operation mode
- * @mode_save: register value for current operation mode for saving
- * @set_power: optional power callback to the board code
- */
 struct m5mols_info {
-	const struct m5mols_platform_data *pdata;
-	struct v4l2_subdev sd;
+	struct v4l2_subdev		sd;
 	struct media_pad pad;
-	struct v4l2_mbus_framefmt ffmt[M5MOLS_RESTYPE_MAX];
 	int res_type;
-	enum v4l2_mbus_pixelcode code;
-	wait_queue_head_t irq_waitq;
-	struct work_struct work_irq;
-	unsigned long flags;
+	u8 resolution;
+	struct v4l2_mbus_framefmt	fmt[M5MOLS_RES_MAX];
+	struct v4l2_fract		tpf;
 
-	struct v4l2_ctrl_handler handle;
-	/* Autoexposure/exposure control cluster */
+	struct v4l2_ctrl_handler	handle;
 	struct {
-		struct v4l2_ctrl *autoexposure;
-		struct v4l2_ctrl *exposure;
+		/* support only AE of the Monitor Mode in this version */
+		struct v4l2_ctrl	*autoexposure;
+		struct v4l2_ctrl	*exposure;
+		bool			is_ae_lock;
 	};
-	struct v4l2_ctrl *autowb;
-	struct v4l2_ctrl *colorfx;
-	struct v4l2_ctrl *saturation;
-	struct v4l2_ctrl *zoom;
-
-	struct m5mols_version ver;
-	struct m5mols_capture cap;
-	bool power;
-	bool ctrl_sync;
-	bool lock_ae;
-	bool lock_awb;
-	u8 resolution;
-	u8 interrupt;
-	u8 mode;
-	u8 mode_save;
+	struct v4l2_ctrl		*autofocus;
+	bool				is_focus;
+	struct v4l2_ctrl		*autowb;
+	bool				is_awb_lock;
+	struct v4l2_ctrl		*colorfx;
+	struct v4l2_ctrl		*saturation;
+	struct v4l2_ctrl		*zoom;
+	struct v4l2_ctrl		*jpeg_size;
+	struct v4l2_ctrl		*encoded_size;
+
+	enum m5mols_mode		mode;
+	enum m5mols_mode		mode_backup;
+	enum m5mols_status		status;
+	enum v4l2_mbus_pixelcode	code;
+
+	struct m5mols_capture		cap;
+	wait_queue_head_t		cap_wait;
+	bool				captured;
+
+	const struct m5mols_platform_data	*pdata;
+	struct m5mols_version		ver;
+	struct work_struct		work;
+	bool				power;
+
+	/* for additional power if needed. */
 	int (*set_power)(struct device *dev, int on);
 };
 
-#define ST_CAPT_IRQ 0
+/* control functions */
+int m5mols_set_ctrl(struct v4l2_ctrl *ctrl);
 
-#define is_powered(__info) (__info->power)
-#define is_ctrl_synced(__info) (__info->ctrl_sync)
-#define is_available_af(__info)	(__info->ver.af)
-#define is_code(__code, __type) (__code == m5mols_default_ffmt[__type].code)
-#define is_manufacturer(__info, __manufacturer)	\
-				(__info->ver.str[0] == __manufacturer[0] && \
-				 __info->ver.str[1] == __manufacturer[1])
-/*
- * I2C operation of the M-5MOLS
- *
- * The I2C read operation of the M-5MOLS requires 2 messages. The first
- * message sends the information about the command, command category, and total
- * message size. The second message is used to retrieve the data specifed in
- * the first message
- *
- *   1st message                                2nd message
- *   +-------+---+----------+-----+-------+     +------+------+------+------+
- *   | size1 | R | category | cmd | size2 |     | d[0] | d[1] | d[2] | d[3] |
- *   +-------+---+----------+-----+-------+     +------+------+------+------+
- *   - size1: message data size(5 in this case)
- *   - size2: desired buffer size of the 2nd message
- *   - d[0..3]: according to size2
- *
- * The I2C write operation needs just one message. The message includes
- * category, command, total size, and desired data.
- *
- *   1st message
- *   +-------+---+----------+-----+------+------+------+------+
- *   | size1 | W | category | cmd | d[0] | d[1] | d[2] | d[3] |
- *   +-------+---+----------+-----+------+------+------+------+
- *   - d[0..3]: according to size1
- */
-int m5mols_read_u8(struct v4l2_subdev *sd, u32 reg_comb, u8 *val);
-int m5mols_read_u16(struct v4l2_subdev *sd, u32 reg_comb, u16 *val);
-int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg_comb, u32 *val);
-int m5mols_write(struct v4l2_subdev *sd, u32 reg_comb, u32 val);
-int m5mols_busy(struct v4l2_subdev *sd, u8 category, u8 cmd, u8 value);
+/* I2C functions - referenced by below I2C helper functions */
+int m5mols_read_reg(struct v4l2_subdev *sd, enum m5mols_i2c_size size,
+		u8 category, u8 cmd, u32 *val);
+int m5mols_write_reg(struct v4l2_subdev *sd, enum m5mols_i2c_size size,
+		u8 category, u8 cmd, u32 val);
+int m5mols_check_busy(struct v4l2_subdev *sd,
+		u8 category, u8 cmd, u32 value);
+int m5mols_set_mode(struct v4l2_subdev *sd, enum m5mols_mode mode);
+enum m5mols_status m5mols_get_status(struct v4l2_subdev *sd);
 
 /*
- * Mode operation of the M-5MOLS
- *
- * Changing the mode of the M-5MOLS is needed right executing order.
- * There are three modes(PARAMETER, MONITOR, CAPTURE) which can be changed
- * by user. There are various categories associated with each mode.
- *
- * +============================================================+
- * | mode	| category					|
- * +============================================================+
- * | FLASH	| FLASH(only after Stand-by or Power-on)	|
- * | SYSTEM	| SYSTEM(only after sensor arm-booting)		|
- * | PARAMETER	| PARAMETER					|
- * | MONITOR	| MONITOR(preview), Auto Focus, Face Detection	|
- * | CAPTURE	| Single CAPTURE, Preview(recording)		|
- * +============================================================+
- *
- * The available executing order between each modes are as follows:
- *   PARAMETER <---> MONITOR <---> CAPTURE
+ * helper functions
  */
-int m5mols_mode(struct m5mols_info *info, u8 mode);
+static inline struct m5mols_info *to_m5mols(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct m5mols_info, sd);
+}
 
-int m5mols_enable_interrupt(struct v4l2_subdev *sd, u8 reg);
-int m5mols_sync_controls(struct m5mols_info *info);
-int m5mols_start_capture(struct m5mols_info *info);
-int m5mols_do_scenemode(struct m5mols_info *info, u8 mode);
-int m5mols_lock_3a(struct m5mols_info *info, bool lock);
-int m5mols_set_ctrl(struct v4l2_ctrl *ctrl);
+static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
+{
+	return &container_of(ctrl->handler, struct m5mols_info, handle)->sd;
+}
+
+static inline bool is_streaming(struct v4l2_subdev *sd)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	return (info->mode == MODE_MONITOR) || (info->mode == MODE_CAPTURE);
+}
+
+static inline bool is_stoped(struct v4l2_subdev *sd)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	return (info->mode != MODE_MONITOR) && (info->mode != MODE_CAPTURE);
+}
+
+static inline bool is_powerup(struct v4l2_subdev *sd)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	return info->power;
+}
+
+static inline int m5mols_set_mode_backup(struct v4l2_subdev *sd,
+		enum m5mols_mode mode)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+
+	info->mode_backup = info->mode;
+	return m5mols_set_mode(sd, mode);
+}
+
+static inline int m5mols_set_mode_restore(struct v4l2_subdev *sd)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	int ret;
+
+	ret = m5mols_set_mode(sd, info->mode_backup);
+	if (!ret)
+		info->mode = info->mode_backup;
+	return ret;
+}
+
+static inline int __must_check i2c_w8_system(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_SYSTEM, cmd, val);
+}
+
+static inline int __must_check i2c_w8_param(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_PARAM, cmd, val);
+}
+
+static inline int __must_check i2c_w8_mon(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_MON, cmd, val);
+}
+
+static inline int __must_check i2c_w8_ae(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_AE, cmd, val);
+}
+
+static inline int __must_check i2c_w16_ae(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_16BIT, CAT_AE, cmd, val);
+}
+
+static inline int __must_check i2c_w8_wb(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_WB, cmd, val);
+}
+
+static inline int __must_check i2c_w8_lens(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_LENS, cmd, val);
+}
+
+static inline int __must_check i2c_w8_capt_parm(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_CAPTURE_PARAMETER, cmd, val);
+}
+
+static inline int __must_check i2c_w8_capt_ctrl(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_CAPTURE_CONTROL, cmd, val);
+}
+
+static inline int __must_check i2c_w8_flash(struct v4l2_subdev *sd,
+		u8 cmd, u32 val)
+{
+	return m5mols_write_reg(sd, I2C_8BIT, CAT_FLASH, cmd, val);
+}
+
+static inline int __must_check i2c_r8_system(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_8BIT, CAT_SYSTEM, cmd, val);
+}
+
+static inline int __must_check i2c_r8_param(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_8BIT, CAT_PARAM, cmd, val);
+}
+
+static inline int __must_check i2c_r8_mon(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_8BIT, CAT_MON, cmd, val);
+}
+
+static inline int __must_check i2c_r8_ae(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_8BIT, CAT_AE, cmd, val);
+}
+
+static inline int __must_check i2c_r16_ae(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_16BIT, CAT_AE, cmd, val);
+}
+
+static inline int __must_check i2c_r8_lens(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_8BIT, CAT_LENS, cmd, val);
+}
+
+static inline int __must_check i2c_r32_capt_ctrl(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_32BIT, CAT_CAPTURE_CONTROL, cmd, val);
+}
+
+static inline int __must_check i2c_r16_exif(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_16BIT, CAT_EXIF, cmd, val);
+}
+
+static inline int __must_check i2c_r32_exif(struct v4l2_subdev *sd,
+		u8 cmd, u32 *val)
+{
+	return m5mols_read_reg(sd, I2C_32BIT, CAT_EXIF, cmd, val);
+}
+
+static int m5mols_set_ae_lock(struct m5mols_info *info, bool lock)
+{
+	struct v4l2_subdev *sd = &info->sd;
+
+	info->is_ae_lock = lock;
+
+	return i2c_w8_ae(sd, CAT3_AE_LOCK, !!lock);
+}
+
+static int m5mols_set_awb_lock(struct m5mols_info *info, bool lock)
+{
+	struct v4l2_subdev *sd = &info->sd;
 
-/* The firmware function */
-int m5mols_update_fw(struct v4l2_subdev *sd,
-		     int (*set_power)(struct m5mols_info *, bool));
+	info->is_awb_lock = lock;
 
+	return i2c_w8_wb(sd, CAT6_AWB_LOCK, !!lock);
+}
 #endif	/* M5MOLS_H */
diff --git a/drivers/media/video/m5mols/m5mols_controls.c b/drivers/media/video/m5mols/m5mols_controls.c
index d135d20..3e08018 100644
--- a/drivers/media/video/m5mols/m5mols_controls.c
+++ b/drivers/media/video/m5mols/m5mols_controls.c
@@ -1,5 +1,5 @@
 /*
- * Controls for M-5MOLS 8M Pixel camera sensor with ISP
+ * Controls for M5MOLS 8M Pixel camera sensor with ISP
  *
  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  * Author: HeungJun Kim <riverful.kim@samsung.com>
@@ -14,285 +14,186 @@
  */
 
 #include <linux/i2c.h>
-#include <linux/delay.h>
 #include <linux/videodev2.h>
 #include <media/v4l2-ctrls.h>
 
 #include "m5mols.h"
 #include "m5mols_reg.h"
 
-static struct m5mols_scenemode m5mols_default_scenemode[] = {
-	[REG_SCENE_NORMAL] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_NORMAL, REG_LIGHT_OFF, REG_FLASH_OFF,
-		5, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_PORTRAIT] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 4,
-		REG_AF_NORMAL, BIT_FD_EN | BIT_FD_DRAW_FACE_FRAME,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_LANDSCAPE] = {
-		REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 4, REG_EDGE_ON, 6,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_SPORTS] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_PARTY_INDOOR] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_200, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_BEACH_SNOW] = {
-		REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_SUNSET] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
-		REG_AWB_DAYLIGHT,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_DAWN_DUSK] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
-		REG_AWB_FLUORESCENT_1,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_FALL] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 5, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_NIGHT] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_AGAINST_LIGHT] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_FIRE] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
-	},
-	[REG_SCENE_TEXT] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 7,
-		REG_AF_MACRO, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_ANTI_SHAKE, REG_WDR_ON,
-	},
-	[REG_SCENE_CANDLE] = {
-		REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
-		REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
-		REG_AF_NORMAL, REG_FD_OFF,
-		REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
-		6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
-	},
-};
+static int m5mols_wb_mode(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
+{
+	struct v4l2_subdev *sd = &info->sd;
+	int ret;
 
-/**
- * m5mols_do_scenemode() - Change current scenemode
- * @mode:	Desired mode of the scenemode
- *
- * WARNING: The execution order is important. Do not change the order.
- */
-int m5mols_do_scenemode(struct m5mols_info *info, u8 mode)
+	if (info->is_awb_lock) {
+		ret = m5mols_set_awb_lock(info, false);
+		if (!ret)
+			return ret;
+	}
+
+	/* 0x01 : Auto Whitebalance, 0x02 : Manual Whitebalance. */
+	return i2c_w8_wb(sd, CAT6_AWB_MODE, (ctrl->val) ? 0x1 : 0x2);
+
+}
+
+static int m5mols_exposure_mode(struct m5mols_info *info,
+		struct v4l2_ctrl *ctrl)
 {
 	struct v4l2_subdev *sd = &info->sd;
-	struct m5mols_scenemode scenemode = m5mols_default_scenemode[mode];
 	int ret;
 
-	if (mode > REG_SCENE_CANDLE)
-		return -EINVAL;
+	if (info->is_ae_lock) {
+		ret = m5mols_set_ae_lock(info, false);
+		if (ret)
+			return ret;
+	}
 
-	ret = m5mols_lock_3a(info, false);
-	if (!ret)
-		ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, mode);
-	if (!ret)
-		ret = m5mols_write(sd, AE_EV_PRESET_CAPTURE, mode);
-	if (!ret)
-		ret = m5mols_write(sd, AE_MODE, scenemode.metering);
-	if (!ret)
-		ret = m5mols_write(sd, AE_INDEX, scenemode.ev_bias);
-	if (!ret)
-		ret = m5mols_write(sd, AWB_MODE, scenemode.wb_mode);
-	if (!ret)
-		ret = m5mols_write(sd, AWB_MANUAL, scenemode.wb_preset);
-	if (!ret)
-		ret = m5mols_write(sd, MON_CHROMA_EN, scenemode.chroma_en);
-	if (!ret)
-		ret = m5mols_write(sd, MON_CHROMA_LVL, scenemode.chroma_lvl);
-	if (!ret)
-		ret = m5mols_write(sd, MON_EDGE_EN, scenemode.edge_en);
-	if (!ret)
-		ret = m5mols_write(sd, MON_EDGE_LVL, scenemode.edge_lvl);
-	if (!ret && is_available_af(info))
-		ret = m5mols_write(sd, AF_MODE, scenemode.af_range);
-	if (!ret && is_available_af(info))
-		ret = m5mols_write(sd, FD_CTL, scenemode.fd_mode);
-	if (!ret)
-		ret = m5mols_write(sd, MON_TONE_CTL, scenemode.tone);
-	if (!ret)
-		ret = m5mols_write(sd, AE_ISO, scenemode.iso);
-	if (!ret)
-		ret = m5mols_mode(info, REG_CAPTURE);
-	if (!ret)
-		ret = m5mols_write(sd, CAPP_WDR_EN, scenemode.wdr);
-	if (!ret)
-		ret = m5mols_write(sd, CAPP_MCC_MODE, scenemode.mcc);
-	if (!ret)
-		ret = m5mols_write(sd, CAPP_LIGHT_CTRL, scenemode.light);
+	/* 0x01 : Auto Exposure, 0x0 : Manual Exposure. */
+	return i2c_w8_ae(sd, CAT3_AE_MODE,
+			(ctrl->val == V4L2_EXPOSURE_AUTO) ? 0x1 : 0x0);
+}
+
+static int m5mols_exposure(struct m5mols_info *info)
+{
+	struct v4l2_subdev *sd = &info->sd;
+
+	return i2c_w16_ae(sd, CAT3_MANUAL_GAIN_MON, info->exposure->val);
+}
+
+static int m5mols_zoom(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
+{
+	struct v4l2_subdev *sd = &info->sd;
+
+	return i2c_w8_mon(sd, CAT2_ZOOM, ctrl->val);
+}
+
+static int m5mols_focus_mode(struct m5mols_info *info,
+		struct v4l2_ctrl *ctrl)
+{
+	struct v4l2_subdev *sd = &info->sd;
+	u32 reg;
+	int ret;
+
+	ret = m5mols_set_mode(sd, MODE_MONITOR);
 	if (!ret)
-		ret = m5mols_write(sd, CAPP_FLASH_CTRL, scenemode.flash);
+		ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
 	if (!ret)
-		ret = m5mols_write(sd, CAPC_MODE, scenemode.capt_mode);
+		ret = i2c_w8_system(sd, CAT0_INT_ENABLE, (1 << INT_BIT_AF));
 	if (!ret)
-		ret = m5mols_mode(info, REG_MONITOR);
+		/* must be excuted in the monitor mode */
+		ret = i2c_w8_lens(sd, CATA_INIT_AF_FUNC, 0x1);
 
-	return ret;
+	/* 0x0 : Normal AF mode
+	 * 0x1 : Macro AF mode
+	 * 0x2 : Continuous AF mode (Not working) */
+	return i2c_w8_lens(sd, CATA_AF_MODE, 0x0);
 }
 
-static int m5mols_lock_ae(struct m5mols_info *info, bool lock)
+static int m5mols_focus(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
 {
-	int ret = 0;
-
-	if (info->lock_ae != lock)
-		ret = m5mols_write(&info->sd, AE_LOCK,
-				lock ? REG_AE_LOCK : REG_AE_UNLOCK);
-	if (!ret)
-		info->lock_ae = lock;
+	struct v4l2_subdev *sd = &info->sd;
 
-	return ret;
+	/* 0x0: Stop,
+	   0x1: Excute AF,
+	   0x02: Excutre MF rel(Not tested),
+	   0x03: Excute MF absol(Not tested) */
+	return i2c_w8_lens(sd, CATA_AF_EXCUTE, ctrl->val);
 }
 
-static int m5mols_lock_awb(struct m5mols_info *info, bool lock)
+static int m5mols_set_saturation(struct m5mols_info *info,
+		struct v4l2_ctrl *ctrl)
 {
-	int ret = 0;
+	struct v4l2_subdev *sd = &info->sd;
+	static u8 m5mols_chroma_lvl[] = {
+		0x1c, 0x3e, 0x5f, 0x80, 0xa1, 0xc2, 0xe4,
+	};
+	int ret;
 
-	if (info->lock_awb != lock)
-		ret = m5mols_write(&info->sd, AWB_LOCK,
-				lock ? REG_AWB_LOCK : REG_AWB_UNLOCK);
+	ret = i2c_w8_mon(sd, CAT2_CHROMA_LVL, m5mols_chroma_lvl[ctrl->val]);
 	if (!ret)
-		info->lock_awb = lock;
+		ret = i2c_w8_mon(sd, CAT2_CHROMA_EN, true);
 
 	return ret;
 }
 
-/* m5mols_lock_3a() - Lock 3A(Auto Exposure, Auto Whitebalance, Auto Focus) */
-int m5mols_lock_3a(struct m5mols_info *info, bool lock)
+static int m5mols_set_colorfx(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
 {
-	int ret;
-
-	ret = m5mols_lock_ae(info, lock);
-	if (!ret)
-		ret = m5mols_lock_awb(info, lock);
-	/* Don't need to handle unlocking AF */
-	if (!ret && is_available_af(info) && lock)
-		ret = m5mols_write(&info->sd, AF_EXECUTE, REG_AF_STOP);
+	struct v4l2_subdev *sd = &info->sd;
+	static u8 m5mols_effects_gamma[] = {	/* cat 1: Effects */
+		[V4L2_COLORFX_NEGATIVE]		= 0x01,
+		[V4L2_COLORFX_EMBOSS]		= 0x06,
+		[V4L2_COLORFX_SKETCH]		= 0x07,
+	};
+	static u8 m5mols_cfixb_chroma[] = {	/* cat 2: Cr for effect */
+		[V4L2_COLORFX_BW]		= 0x0,
+		[V4L2_COLORFX_SEPIA]		= 0xd8,
+		[V4L2_COLORFX_SKY_BLUE]		= 0x40,
+		[V4L2_COLORFX_GRASS_GREEN]	= 0xe0,
+	};
+	static u8 m5mols_cfixr_chroma[] = {	/* cat 2: Cb for effect */
+		[V4L2_COLORFX_BW]		= 0x0,
+		[V4L2_COLORFX_SEPIA]		= 0x18,
+		[V4L2_COLORFX_SKY_BLUE]		= 0x00,
+		[V4L2_COLORFX_GRASS_GREEN]	= 0xe0,
+	};
+	int ret = -EINVAL;
+
+	switch (ctrl->val) {
+	case V4L2_COLORFX_NONE:
+		return i2c_w8_mon(sd, CAT2_COLOR_EFFECT, false);
+	case V4L2_COLORFX_BW:		/* chroma: Gray */
+	case V4L2_COLORFX_SEPIA:	/* chroma: Sepia */
+	case V4L2_COLORFX_SKY_BLUE:	/* chroma: Blue */
+	case V4L2_COLORFX_GRASS_GREEN:	/* chroma: Green */
+		ret = i2c_w8_mon(sd, CAT2_CFIXB,
+				m5mols_cfixb_chroma[ctrl->val]);
+		if (!ret)
+			ret = i2c_w8_mon(sd, CAT2_CFIXR,
+					m5mols_cfixr_chroma[ctrl->val]);
+		if (!ret)
+			ret = i2c_w8_mon(sd, CAT2_COLOR_EFFECT, true);
+		return ret;
+	case V4L2_COLORFX_NEGATIVE:	/* gamma: Negative */
+	case V4L2_COLORFX_EMBOSS:	/* gamma: Emboss */
+	case V4L2_COLORFX_SKETCH:	/* gamma: Outline */
+		ret = i2c_w8_param(sd, CAT1_EFFECT,
+				m5mols_effects_gamma[ctrl->val]);
+		if (!ret)
+			ret = i2c_w8_mon(sd, CAT2_COLOR_EFFECT, true);
+		return ret;
+	}
 
 	return ret;
 }
 
-/* m5mols_set_ctrl() - The main s_ctrl function called by m5mols_set_ctrl() */
 int m5mols_set_ctrl(struct v4l2_ctrl *ctrl)
 {
 	struct v4l2_subdev *sd = to_sd(ctrl);
 	struct m5mols_info *info = to_m5mols(sd);
-	int ret;
+	int ret = 0;
 
 	switch (ctrl->id) {
 	case V4L2_CID_ZOOM_ABSOLUTE:
-		return m5mols_write(sd, MON_ZOOM, ctrl->val);
-
+		return m5mols_zoom(info, ctrl);
+	case V4L2_CID_FOCUS_AUTO:
+		if (ctrl->val != 0)
+			ret = m5mols_focus_mode(info, ctrl);
+		if (!ret)
+			ret = m5mols_focus(info, ctrl);
+		return ret;
 	case V4L2_CID_EXPOSURE_AUTO:
-		ret = m5mols_lock_ae(info,
-			ctrl->val == V4L2_EXPOSURE_AUTO ? false : true);
-		if (!ret && ctrl->val == V4L2_EXPOSURE_AUTO)
-			ret = m5mols_write(sd, AE_MODE, REG_AE_ALL);
-		if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) {
-			int val = info->exposure->val;
-			ret = m5mols_write(sd, AE_MODE, REG_AE_OFF);
-			if (!ret)
-				ret = m5mols_write(sd, AE_MAN_GAIN_MON, val);
-			if (!ret)
-				ret = m5mols_write(sd, AE_MAN_GAIN_CAP, val);
-		}
+		if (!ctrl->is_new)
+			ctrl->val = V4L2_EXPOSURE_MANUAL;
+		ret = m5mols_exposure_mode(info, ctrl);
+		if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
+			ret = m5mols_exposure(info);
 		return ret;
-
 	case V4L2_CID_AUTO_WHITE_BALANCE:
-		ret = m5mols_lock_awb(info, ctrl->val ? false : true);
-		if (!ret)
-			ret = m5mols_write(sd, AWB_MODE, ctrl->val ?
-				REG_AWB_AUTO : REG_AWB_PRESET);
-		return ret;
-
+		return m5mols_wb_mode(info, ctrl);
 	case V4L2_CID_SATURATION:
-		ret = m5mols_write(sd, MON_CHROMA_LVL, ctrl->val);
-		if (!ret)
-			ret = m5mols_write(sd, MON_CHROMA_EN, REG_CHROMA_ON);
-		return ret;
-
+		return m5mols_set_saturation(info, ctrl);
 	case V4L2_CID_COLORFX:
-		/*
-		 * This control uses two kinds of registers: normal & color.
-		 * The normal effect belongs to category 1, while the color
-		 * one belongs to category 2.
-		 *
-		 * The normal effect uses one register: CAT1_EFFECT.
-		 * The color effect uses three registers:
-		 * CAT2_COLOR_EFFECT, CAT2_CFIXR, CAT2_CFIXB.
-		 */
-		ret = m5mols_write(sd, PARM_EFFECT,
-			ctrl->val == V4L2_COLORFX_NEGATIVE ? REG_EFFECT_NEGA :
-			ctrl->val == V4L2_COLORFX_EMBOSS ? REG_EFFECT_EMBOSS :
-			REG_EFFECT_OFF);
-		if (!ret)
-			ret = m5mols_write(sd, MON_EFFECT,
-				ctrl->val == V4L2_COLORFX_SEPIA ?
-				REG_COLOR_EFFECT_ON : REG_COLOR_EFFECT_OFF);
-		if (!ret)
-			ret = m5mols_write(sd, MON_CFIXR,
-				ctrl->val == V4L2_COLORFX_SEPIA ?
-				REG_CFIXR_SEPIA : 0);
-		if (!ret)
-			ret = m5mols_write(sd, MON_CFIXB,
-				ctrl->val == V4L2_COLORFX_SEPIA ?
-				REG_CFIXB_SEPIA : 0);
-		return ret;
+		return m5mols_set_colorfx(info, ctrl);
 	}
 
 	return -EINVAL;
diff --git a/drivers/media/video/m5mols/m5mols_core.c b/drivers/media/video/m5mols/m5mols_core.c
index 43c68f5..cf4c8ba 100644
--- a/drivers/media/video/m5mols/m5mols_core.c
+++ b/drivers/media/video/m5mols/m5mols_core.c
@@ -1,5 +1,5 @@
 /*
- * Driver for M-5MOLS 8M Pixel camera sensor with ISP
+ * Driver for M5MOLS 8M Pixel camera sensor with ISP
  *
  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  * Author: HeungJun Kim <riverful.kim@samsung.com>
@@ -22,6 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
 #include <media/v4l2-ctrls.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-subdev.h>
@@ -33,35 +34,66 @@
 int m5mols_debug;
 module_param(m5mols_debug, int, 0644);
 
-#define MODULE_NAME		"M5MOLS"
-#define M5MOLS_I2C_CHECK_RETRY	500
+#define MOD_NAME		"M5MOLS"
+#define M5MOLS_I2C_CHECK_RETRY 50
+#define DEBUG
+#define DEFAULT_SENSOR_WIDTH	800
+#define DEFAULT_SENSOR_HEIGHT	480
+
+#define m5_err	\
+	do { printk("%s : %d : ret : %d\n", __func__, __LINE__, ret);\
+	} while(0)
+/* M5MOLS mode */
+static u8 m5mols_reg_mode[] = {
+	[MODE_SYSINIT]		= 0x00,
+	[MODE_PARMSET]		= 0x01,
+	[MODE_MONITOR]		= 0x02,
+	[MODE_CAPTURE]		= 0x03,
+	[MODE_UNKNOWN]		= 0xff,
+};
+
+/* M5MOLS status */
+static u8 m5mols_reg_status[] = {
+	[STATUS_SYSINIT]	= 0x00,
+	[STATUS_PARMSET]	= 0x01,
+	[STATUS_MONITOR]	= 0x02,
+	[STATUS_AUTO_FOCUS]	= 0x03,
+	[STATUS_FACE_DETECTION]	= 0x04,
+	[STATUS_DUAL_CAPTURE]	= 0x05,
+	[STATUS_SINGLE_CAPTURE]	= 0x06,
+	[STATUS_PREVIEW]	= 0x07,
+	[STATUS_UNKNOWN]	= 0xff,
+};
 
-/* The regulator consumer names for external voltage regulators */
+/* M5MOLS regulator consumer names */
+/* The DEFAULT names of power are referenced with M5MO datasheet. */
 static struct regulator_bulk_data supplies[] = {
 	{
-		.supply = "core",	/* ARM core power, 1.2V */
+		/* core power - 1.2v, generally at the M5MOLS */
+		.supply		= "core",
 	}, {
-		.supply	= "dig_18",	/* digital power 1, 1.8V */
+		.supply		= "dig_18",	/* digital power 1 - 1.8v */
 	}, {
-		.supply	= "d_sensor",	/* sensor power 1, 1.8V */
+		.supply		= "d_sensor",	/* sensor power 1 - 1.8v */
 	}, {
-		.supply	= "dig_28",	/* digital power 2, 2.8V */
+		.supply		= "dig_28",	/* digital power 2 - 2.8v */
 	}, {
-		.supply	= "a_sensor",	/* analog power */
+		.supply		= "a_sensor",	/* analog power */
 	}, {
-		.supply	= "dig_12",	/* digital power 3, 1.2V */
+		.supply		= "dig_12",	/* digital power 3 - 1.2v */
 	},
 };
 
-static struct v4l2_mbus_framefmt m5mols_default_ffmt[M5MOLS_RESTYPE_MAX] = {
-	[M5MOLS_RESTYPE_MONITOR] = {
-		.width		= 1920,
-		.height		= 1080,
-		.code		= V4L2_MBUS_FMT_VYUY8_2X8,
+/* M5MOLS default format (codes, sizes, preset values) */
+static struct v4l2_mbus_framefmt default_fmt[M5MOLS_RES_MAX] = {
+	[M5MOLS_RES_MON] = {
+		.width		= DEFAULT_SENSOR_WIDTH,
+		.height		= DEFAULT_SENSOR_HEIGHT,
+		.code		= V4L2_MBUS_FMT_YUYV8_2X8,
 		.field		= V4L2_FIELD_NONE,
 		.colorspace	= V4L2_COLORSPACE_JPEG,
 	},
-	[M5MOLS_RESTYPE_CAPTURE] = {
+	[M5MOLS_RES_CAPTURE] = {
 		.width		= 1920,
 		.height		= 1080,
 		.code		= V4L2_MBUS_FMT_JPEG_1X8,
@@ -69,189 +101,201 @@ static struct v4l2_mbus_framefmt m5mols_default_ffmt[M5MOLS_RESTYPE_MAX] = {
 		.colorspace	= V4L2_COLORSPACE_JPEG,
 	},
 };
-#define SIZE_DEFAULT_FFMT	ARRAY_SIZE(m5mols_default_ffmt)
-
-static const struct m5mols_resolution m5mols_reg_res[] = {
-	{ 0x01, M5MOLS_RESTYPE_MONITOR, 128, 96 },	/* SUB-QCIF */
-	{ 0x03, M5MOLS_RESTYPE_MONITOR, 160, 120 },	/* QQVGA */
-	{ 0x05, M5MOLS_RESTYPE_MONITOR, 176, 144 },	/* QCIF */
-	{ 0x06, M5MOLS_RESTYPE_MONITOR, 176, 176 },
-	{ 0x08, M5MOLS_RESTYPE_MONITOR, 240, 320 },	/* QVGA */
-	{ 0x09, M5MOLS_RESTYPE_MONITOR, 320, 240 },	/* QVGA */
-	{ 0x0c, M5MOLS_RESTYPE_MONITOR, 240, 400 },	/* WQVGA */
-	{ 0x0d, M5MOLS_RESTYPE_MONITOR, 400, 240 },	/* WQVGA */
-	{ 0x0e, M5MOLS_RESTYPE_MONITOR, 352, 288 },	/* CIF */
-	{ 0x13, M5MOLS_RESTYPE_MONITOR, 480, 360 },
-	{ 0x15, M5MOLS_RESTYPE_MONITOR, 640, 360 },	/* qHD */
-	{ 0x17, M5MOLS_RESTYPE_MONITOR, 640, 480 },	/* VGA */
-	{ 0x18, M5MOLS_RESTYPE_MONITOR, 720, 480 },
-	{ 0x1a, M5MOLS_RESTYPE_MONITOR, 800, 480 },	/* WVGA */
-	{ 0x1f, M5MOLS_RESTYPE_MONITOR, 800, 600 },	/* SVGA */
-	{ 0x21, M5MOLS_RESTYPE_MONITOR, 1280, 720 },	/* HD */
-	{ 0x25, M5MOLS_RESTYPE_MONITOR, 1920, 1080 },	/* 1080p */
-	{ 0x29, M5MOLS_RESTYPE_MONITOR, 3264, 2448 },	/* 2.63fps 8M */
-	{ 0x39, M5MOLS_RESTYPE_MONITOR, 800, 602 },	/* AHS_MON debug */
-
-	{ 0x02, M5MOLS_RESTYPE_CAPTURE, 320, 240 },	/* QVGA */
-	{ 0x04, M5MOLS_RESTYPE_CAPTURE, 400, 240 },	/* WQVGA */
-	{ 0x07, M5MOLS_RESTYPE_CAPTURE, 480, 360 },
-	{ 0x08, M5MOLS_RESTYPE_CAPTURE, 640, 360 },	/* qHD */
-	{ 0x09, M5MOLS_RESTYPE_CAPTURE, 640, 480 },	/* VGA */
-	{ 0x0a, M5MOLS_RESTYPE_CAPTURE, 800, 480 },	/* WVGA */
-	{ 0x10, M5MOLS_RESTYPE_CAPTURE, 1280, 720 },	/* HD */
-	{ 0x14, M5MOLS_RESTYPE_CAPTURE, 1280, 960 },	/* 1M */
-	{ 0x17, M5MOLS_RESTYPE_CAPTURE, 1600, 1200 },	/* 2M */
-	{ 0x19, M5MOLS_RESTYPE_CAPTURE, 1920, 1080 },	/* Full-HD */
-	{ 0x1a, M5MOLS_RESTYPE_CAPTURE, 2048, 1152 },	/* 3Mega */
-	{ 0x1b, M5MOLS_RESTYPE_CAPTURE, 2048, 1536 },
-	{ 0x1c, M5MOLS_RESTYPE_CAPTURE, 2560, 1440 },	/* 4Mega */
-	{ 0x1d, M5MOLS_RESTYPE_CAPTURE, 2560, 1536 },
-	{ 0x1f, M5MOLS_RESTYPE_CAPTURE, 2560, 1920 },	/* 5Mega */
-	{ 0x21, M5MOLS_RESTYPE_CAPTURE, 3264, 1836 },	/* 6Mega */
-	{ 0x22, M5MOLS_RESTYPE_CAPTURE, 3264, 1960 },
-	{ 0x25, M5MOLS_RESTYPE_CAPTURE, 3264, 2448 },	/* 8Mega */
+
+#define SIZE_DEFAULT_FFMT	ARRAY_SIZE(default_fmt)
+
+static const struct m5mols_format m5mols_formats[] = {
+	[M5MOLS_RES_MON] = {
+		.code		= V4L2_MBUS_FMT_YUYV8_2X8,
+		.colorspace	= V4L2_COLORSPACE_JPEG,
+	},
+	[M5MOLS_RES_CAPTURE] = {
+		.code		= V4L2_MBUS_FMT_JPEG_1X8,
+		.colorspace	= V4L2_COLORSPACE_JPEG,
+	},
+};
+
+static const struct m5mols_resolution m5mols_resolutions[] = {
+	/* monitor size */
+	{ 0x01, M5MOLS_RES_MON, 128, 96 },	/* SUB-QCIF */
+	{ 0x03, M5MOLS_RES_MON, 160, 120 },	/* QQVGA */
+	{ 0x05, M5MOLS_RES_MON, 176, 144 },	/* QCIF */
+	{ 0x06, M5MOLS_RES_MON, 176, 176 },	/* 176*176 */
+	{ 0x08, M5MOLS_RES_MON, 240, 320 },	/* 1 QVGA */
+	{ 0x09, M5MOLS_RES_MON, 320, 240 },	/* QVGA */
+	{ 0x0c, M5MOLS_RES_MON, 240, 400 },	/* l WQVGA */
+	{ 0x0d, M5MOLS_RES_MON, 400, 240 },	/* WQVGA */
+	{ 0x0e, M5MOLS_RES_MON, 352, 288 },	/* CIF */
+	{ 0x13, M5MOLS_RES_MON, 480, 360 },	/* 480*360 */
+	{ 0x15, M5MOLS_RES_MON, 640, 360 },	/* qHD */
+	{ 0x17, M5MOLS_RES_MON, 640, 480 },	/* VGA */
+	{ 0x18, M5MOLS_RES_MON, 720, 480 },	/* 720x480 */
+	{ 0x1a, M5MOLS_RES_MON, 800, 480 },	/* WVGA */
+	{ 0x1f, M5MOLS_RES_MON, 800, 600 },	/* SVGA */
+	{ 0x21, M5MOLS_RES_MON, 1280, 720 },	/* HD */
+	{ 0x25, M5MOLS_RES_MON, 1920, 1080 },	/* 1080p */
+	{ 0x29, M5MOLS_RES_MON, 3264, 2448 },	/* 8M (2.63fps@3264*2448) */
+	{ 0x30, M5MOLS_RES_MON, 320, 240 },	/* 60fps for slow motion */
+	{ 0x31, M5MOLS_RES_MON, 320, 240 },	/* 120fps for slow motion */
+	{ 0x39, M5MOLS_RES_MON, 800, 602 },	/* AHS_MON debug */
+
+	/* capture(JPEG or Bayer RAW or YUV Raw) size */
+	{ 0x02, M5MOLS_RES_CAPTURE, 320, 240 },		/* QVGA */
+	{ 0x04, M5MOLS_RES_CAPTURE, 400, 240 },		/* WQVGA */
+	{ 0x07, M5MOLS_RES_CAPTURE, 480, 360 },		/* 480 x 360 */
+	{ 0x08, M5MOLS_RES_CAPTURE, 640, 360 },		/* qHD */
+	{ 0x09, M5MOLS_RES_CAPTURE, 640, 480 },		/* VGA */
+	{ 0x0a, M5MOLS_RES_CAPTURE, 800, 480 },		/* WVGA */
+	{ 0x10, M5MOLS_RES_CAPTURE, 1280, 720 },	/* HD */
+	{ 0x14, M5MOLS_RES_CAPTURE, 1280,  960 },	/* 1M */
+	{ 0x17, M5MOLS_RES_CAPTURE, 1600, 1200 },	/* 2M */
+	{ 0x19, M5MOLS_RES_CAPTURE, 1920, 1080 },	/* Full-HD */
+	{ 0x1a, M5MOLS_RES_CAPTURE, 2048, 1152 },	/* 3M */
+	{ 0x1b, M5MOLS_RES_CAPTURE, 2048, 1536 },	/* 3M */
+	{ 0x1c, M5MOLS_RES_CAPTURE, 2560, 1440 },	/* 4M */
+	{ 0x1d, M5MOLS_RES_CAPTURE, 2560, 1536 },	/* 4M */
+	{ 0x1f, M5MOLS_RES_CAPTURE, 2560, 1920 },	/* 5M */
+	{ 0x21, M5MOLS_RES_CAPTURE, 3264, 1836 },	/* 6M */
+	{ 0x22, M5MOLS_RES_CAPTURE, 3264, 1960 },	/* 6M */
+	{ 0x25, M5MOLS_RES_CAPTURE, 3264, 2448 },	/* 8M */
+#ifdef M5MO_THUMB_SUPPORT
+	/* capture thumb(JPEG) size */
+	{ 0x00, M5MOLS_RES_THUMB, 160, 90 },	/* 160 x 90 */
+	{ 0x02, M5MOLS_RES_THUMB, 160, 120 },	/* QQVGA */
+	{ 0x04, M5MOLS_RES_THUMB, 320, 240 },	/* QVGA */
+	{ 0x06, M5MOLS_RES_THUMB, 400, 240 },	/* WQVGA */
+	{ 0x09, M5MOLS_RES_THUMB, 480, 360 },	/* 480 x 360 */
+	{ 0x0a, M5MOLS_RES_THUMB, 640, 360 },	/* qHD */
+	{ 0x0b, M5MOLS_RES_THUMB, 640, 480 },	/* VGA */
+	{ 0x0c, M5MOLS_RES_THUMB, 800, 480 },	/* WVGA */
+#endif
 };
 
-/**
- * m5mols_swap_byte - an byte array to integer conversion function
- * @size: size in bytes of I2C packet defined in the M-5MOLS datasheet
- *
- * Convert I2C data byte array with performing any required byte
- * reordering to assure proper values for each data type, regardless
- * of the architecture endianness.
- */
-static u32 m5mols_swap_byte(u8 *data, u8 length)
+/* M5MOLS default FPS */
+static const struct v4l2_fract default_fps = {
+	.numerator		= 1,
+	.denominator		= M5MOLS_FPS_AUTO,
+};
+
+static u8 m5mols_reg_fps[] = {
+	[M5MOLS_FPS_AUTO]	= 0x01,
+	[M5MOLS_FPS_10]		= 0x05,
+	[M5MOLS_FPS_12]		= 0x04,
+	[M5MOLS_FPS_15]		= 0x03,
+	[M5MOLS_FPS_20]		= 0x08,
+	[M5MOLS_FPS_21]		= 0x09,
+	[M5MOLS_FPS_22]		= 0x0a,
+	[M5MOLS_FPS_23]		= 0x0b,
+	[M5MOLS_FPS_24]		= 0x07,
+	[M5MOLS_FPS_30]		= 0x02,
+};
+
+static u32 m5mols_swap_byte(u8 *data, enum m5mols_i2c_size size)
 {
-	if (length == 1)
+	if (size == I2C_8BIT)
 		return *data;
-	else if (length == 2)
+	else if (size == I2C_16BIT)
 		return be16_to_cpu(*((u16 *)data));
 	else
 		return be32_to_cpu(*((u32 *)data));
 }
 
-/**
- * m5mols_read -  I2C read function
- * @reg: combination of size, category and command for the I2C packet
- * @size: desired size of I2C packet
- * @val: read value
+/*
+ * m5mols_read_reg/m5mols_write_reg - handle sensor's I2C communications.
+ *
+ * The I2C command packet of M5MOLS is made up 3 kinds of I2C bytes(category,
+ * command, bytes). Reference m5mols.h.
+ *
+ * The packet is needed 2, when M5MOLS is read through I2C.
+ * The packet is needed 1, when M5MOLS is written through I2C.
+ *
+ * I2C packet common order(including both reading/writing)
+ *   1st : size (data size + 4)
+ *   2nd : READ/WRITE (R - 0x01, W - 0x02)
+ *   3rd : Category
+ *   4th : Command
+ *
+ * I2C packet order for READING operation
+ *   5th : data real size for reading
+ *   And, read another I2C packet again, until data size.
+ *
+ * I2C packet order for WRITING operation
+ *   5th to 8th: an actual data to write
  */
-static int m5mols_read(struct v4l2_subdev *sd, u32 size, u32 reg, u32 *val)
+
+#define M5MOLS_BYTE_READ	0x01
+#define M5MOLS_BYTE_WRITE	0x02
+
+int m5mols_read_reg(struct v4l2_subdev *sd,
+		enum m5mols_i2c_size size,
+		u8 category, u8 cmd, u32 *val)
 {
 	struct i2c_client *client = v4l2_get_subdevdata(sd);
-	u8 rbuf[M5MOLS_I2C_MAX_SIZE + 1];
-	u8 category = I2C_CATEGORY(reg);
-	u8 cmd = I2C_COMMAND(reg);
 	struct i2c_msg msg[2];
-	u8 wbuf[5];
+	u8 wbuf[5], rbuf[I2C_MAX + 1];
 	int ret;
 
 	if (!client->adapter)
 		return -ENODEV;
 
+	if (size != I2C_8BIT && size != I2C_16BIT && size != I2C_32BIT)
+		return -EINVAL;
+
+	/* 1st I2C operation for writing category & command. */
 	msg[0].addr = client->addr;
 	msg[0].flags = 0;
-	msg[0].len = 5;
+	msg[0].len = 5;		/* 1(cmd size per bytes) + 4 */
 	msg[0].buf = wbuf;
-	wbuf[0] = 5;
+	wbuf[0] = 5;		/* same right above this */
 	wbuf[1] = M5MOLS_BYTE_READ;
 	wbuf[2] = category;
 	wbuf[3] = cmd;
 	wbuf[4] = size;
 
+	/* 2nd I2C operation for reading data. */
 	msg[1].addr = client->addr;
 	msg[1].flags = I2C_M_RD;
 	msg[1].len = size + 1;
 	msg[1].buf = rbuf;
 
-	/* minimum stabilization time */
-	usleep_range(200, 200);
-
 	ret = i2c_transfer(client->adapter, msg, 2);
 	if (ret < 0) {
-		v4l2_err(sd, "read failed: size:%d cat:%02x cmd:%02x. %d\n",
-			 size, category, cmd, ret);
+		m5_err;
+		dev_err(&client->dev, "failed READ[%d] at "
+				"cat[%02x] cmd[%02x]\n",
+				size, category, cmd);
 		return ret;
 	}
 
 	*val = m5mols_swap_byte(&rbuf[1], size);
 
-	return 0;
-}
-
-int m5mols_read_u8(struct v4l2_subdev *sd, u32 reg, u8 *val)
-{
-	u32 val_32;
-	int ret;
+	usleep_range(15000, 20000);	/* must be for stabilization */
 
-	if (I2C_SIZE(reg) != 1) {
-		v4l2_err(sd, "Wrong data size\n");
-		return -EINVAL;
-	}
-
-	ret = m5mols_read(sd, I2C_SIZE(reg), reg, &val_32);
-	if (ret)
-		return ret;
-
-	*val = (u8)val_32;
-	return ret;
-}
-
-int m5mols_read_u16(struct v4l2_subdev *sd, u32 reg, u16 *val)
-{
-	u32 val_32;
-	int ret;
-
-	if (I2C_SIZE(reg) != 2) {
-		v4l2_err(sd, "Wrong data size\n");
-		return -EINVAL;
-	}
-
-	ret = m5mols_read(sd, I2C_SIZE(reg), reg, &val_32);
-	if (ret)
-		return ret;
-
-	*val = (u16)val_32;
-	return ret;
-}
-
-int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg, u32 *val)
-{
-	if (I2C_SIZE(reg) != 4) {
-		v4l2_err(sd, "Wrong data size\n");
-		return -EINVAL;
-	}
-
-	return m5mols_read(sd, I2C_SIZE(reg), reg, val);
+	return 0;
 }
 
-/**
- * m5mols_write - I2C command write function
- * @reg: combination of size, category and command for the I2C packet
- * @val: value to write
- */
-int m5mols_write(struct v4l2_subdev *sd, u32 reg, u32 val)
+int m5mols_write_reg(struct v4l2_subdev *sd,
+		enum m5mols_i2c_size size,
+		u8 category, u8 cmd, u32 val)
 {
 	struct i2c_client *client = v4l2_get_subdevdata(sd);
-	u8 wbuf[M5MOLS_I2C_MAX_SIZE + 4];
-	u8 category = I2C_CATEGORY(reg);
-	u8 cmd = I2C_COMMAND(reg);
-	u8 size	= I2C_SIZE(reg);
-	u32 *buf = (u32 *)&wbuf[4];
+	struct device *cdev = &client->dev;
 	struct i2c_msg msg[1];
+	u8 wbuf[I2C_MAX + 4];
+	u32 *buf = (u32 *)&wbuf[4];
 	int ret;
 
 	if (!client->adapter)
 		return -ENODEV;
 
-	if (size != 1 && size != 2 && size != 4) {
-		v4l2_err(sd, "Wrong data size\n");
+	if (size != I2C_8BIT && size != I2C_16BIT && size != I2C_32BIT) {
+		dev_err(cdev, "Wrong data size\n");
 		return -EINVAL;
 	}
 
 	msg->addr = client->addr;
 	msg->flags = 0;
-	msg->len = (u16)size + 4;
+	msg->len = size + 4;
 	msg->buf = wbuf;
 	wbuf[0] = size + 4;
 	wbuf[1] = M5MOLS_BYTE_WRITE;
@@ -260,551 +304,925 @@ int m5mols_write(struct v4l2_subdev *sd, u32 reg, u32 val)
 
 	*buf = m5mols_swap_byte((u8 *)&val, size);
 
-	usleep_range(200, 200);
-
 	ret = i2c_transfer(client->adapter, msg, 1);
 	if (ret < 0) {
-		v4l2_err(sd, "write failed: size:%d cat:%02x cmd:%02x. %d\n",
-			size, category, cmd, ret);
+		m5_err;
+		dev_err(&client->dev, "failed WRITE[%d] at "
+				"cat[%02x] cmd[%02x], ret %d\n",
+				size, msg->buf[2], msg->buf[3], ret);
 		return ret;
 	}
 
+	usleep_range(15000, 20000);	/* must be for stabilization */
+
 	return 0;
 }
 
-int m5mols_busy(struct v4l2_subdev *sd, u8 category, u8 cmd, u8 mask)
+int m5mols_check_busy(struct v4l2_subdev *sd, u8 category, u8 cmd, u32 value)
 {
-	u8 busy;
-	int i;
+	u32 busy, i;
 	int ret;
 
 	for (i = 0; i < M5MOLS_I2C_CHECK_RETRY; i++) {
-		ret = m5mols_read_u8(sd, I2C_REG(category, cmd, 1), &busy);
+		ret = m5mols_read_reg(sd, I2C_8BIT, category, cmd, &busy);
 		if (ret < 0)
 			return ret;
-		if ((busy & mask) == mask)
+
+		if (busy == value)	/* bingo */
 			return 0;
+
+		/* must be for stabilization */
+		usleep_range(10000, 10000);
 	}
 	return -EBUSY;
 }
 
-/**
- * m5mols_enable_interrupt - Clear interrupt pending bits and unmask interrupts
+/*
+ * m5mols_set_mode - change and set mode of M5MOLS.
  *
- * Before writing desired interrupt value the INT_FACTOR register should
- * be read to clear pending interrupts.
+ * This driver supports now only 3 modes(System, Monitor, Parameter).
  */
-int m5mols_enable_interrupt(struct v4l2_subdev *sd, u8 reg)
+int m5mols_set_mode(struct v4l2_subdev *sd, enum m5mols_mode mode)
 {
 	struct m5mols_info *info = to_m5mols(sd);
-	u8 mask = is_available_af(info) ? REG_INT_AF : 0;
-	u8 dummy;
-	int ret;
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *cdev = &client->dev;
+	const char *m5mols_str_mode[] = {
+		"System initialization",
+		"Parameter setting",
+		"Monitor setting",
+		"Capture setting",
+		"Unknown",
+	};
+	int ret = 0;
+
+	if (mode < MODE_SYSINIT || mode > MODE_UNKNOWN)
+		return -EINVAL;
+
+	ret = i2c_w8_system(sd, CAT0_SYSMODE, m5mols_reg_mode[mode]);
+	if (!ret) {
+		/* bug detect, capture status is  not 0x3 but 0x6 */
+		if (mode == MODE_CAPTURE)
+			mode = STATUS_SINGLE_CAPTURE;
+		ret = m5mols_check_busy(sd, CAT_SYSTEM, CAT0_STATUS,
+				m5mols_reg_status[mode]);
+		if (ret)
+			m5_err;
+	}
+	if (ret < 0)
+		return ret;
+
+	info->mode = m5mols_reg_mode[mode];
+	dev_dbg(cdev, " mode: %s\n", m5mols_str_mode[mode]);
 
-	ret = m5mols_read_u8(sd, SYSTEM_INT_FACTOR, &dummy);
-	if (!ret)
-		ret = m5mols_write(sd, SYSTEM_INT_ENABLE, reg & ~mask);
 	return ret;
 }
 
-/**
- * m5mols_reg_mode - Write the mode and check busy status
- *
- * It always accompanies a little delay changing the M-5MOLS mode, so it is
- * needed checking current busy status to guarantee right mode.
+/*
+ * m5mols_get_status - get status of M5MOLS.
  */
-static int m5mols_reg_mode(struct v4l2_subdev *sd, u8 mode)
+enum m5mols_status m5mols_get_status(struct v4l2_subdev *sd)
 {
-	int ret = m5mols_write(sd, SYSTEM_SYSMODE, mode);
+	struct m5mols_info *info = to_m5mols(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *cdev = &client->dev;
+	const char *m5mols_str_status[] = {
+		"System initialization",
+		"Parameter setting",
+		"Monitor setting",
+		"Auto Focus",
+		"Face Detection",
+		"Multi/Dual Capture",
+		"Single Capture",
+		"Preview (Data transfer)", /* It means recording, not preview. */
+		"Unknown",
+	};
+	u32 reg;
+	int ret = 0;
+
+	ret = i2c_r8_system(sd, CAT0_STATUS, &reg);
+	if (ret)
+		return ret;
+
+	if (reg < STATUS_SYSINIT || reg >= STATUS_UNKNOWN)
+		return -EINVAL;
 
-	return ret ? ret : m5mols_busy(sd, CAT_SYSTEM, CAT0_SYSMODE, mode);
+	info->status = m5mols_reg_status[reg];
+	dev_dbg(cdev, " status: %s\n", m5mols_str_status[reg]);
+
+	return ret;
 }
 
-/**
- * m5mols_mode - manage the M-5MOLS's mode
- * @mode: the required operation mode
- *
- * The commands of M-5MOLS are grouped into specific modes. Each functionality
- * can be guaranteed only when the sensor is operating in mode which which
- * a command belongs to.
+/*
+ * get_version - get M5MOLS sensor versions.
  */
-int m5mols_mode(struct m5mols_info *info, u8 mode)
+static int get_version(struct v4l2_subdev *sd)
 {
-	struct v4l2_subdev *sd = &info->sd;
-	int ret = -EINVAL;
-	u8 reg;
+	struct m5mols_info *info = to_m5mols(sd);
+	union {
+		struct m5mols_version	ver;
+		u8			bytes[10];
+	} value;
+	int ret, i;
+
+	for (i = CAT0_CUSTOMER_CODE; i <= CAT0_VERSION_AWB_L; i++) {
+		ret = i2c_r8_system(sd, i, (u32 *)&value.bytes[i]);
+		if (ret)
+			return ret;
+	}
 
-	if (mode < REG_PARAMETER && mode > REG_CAPTURE)
-		return ret;
+	info->ver = value.ver;
 
-	ret = m5mols_read_u8(sd, SYSTEM_SYSMODE, &reg);
-	if ((!ret && reg == mode) || ret)
-		return ret;
+	info->ver.fw = be16_to_cpu(info->ver.fw);
+	info->ver.hw = be16_to_cpu(info->ver.hw);
+	info->ver.parm = be16_to_cpu(info->ver.parm);
+	info->ver.awb = be16_to_cpu(info->ver.awb);
 
-	switch (reg) {
-	case REG_PARAMETER:
-		ret = m5mols_reg_mode(sd, REG_MONITOR);
-		if (!ret && mode == REG_MONITOR)
-			break;
-		if (!ret)
-			ret = m5mols_reg_mode(sd, REG_CAPTURE);
-		break;
+	return ret;
+}
 
-	case REG_MONITOR:
-		if (mode == REG_PARAMETER) {
-			ret = m5mols_reg_mode(sd, REG_PARAMETER);
-			break;
-		}
+static void m5mols_show_version(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct device *dev = &client->dev;
+	struct m5mols_info *info = to_m5mols(sd);
 
-		ret = m5mols_reg_mode(sd, REG_CAPTURE);
-		break;
+	dev_info(dev, "customer code\t0x%02x\n", info->ver.ctm_code);
+	dev_info(dev, "project code\t0x%02x\n", info->ver.pj_code);
+	dev_info(dev, "firmware version\t0x%04x\n", info->ver.fw);
+	dev_info(dev, "hardware version\t0x%04x\n", info->ver.hw);
+	dev_info(dev, "parameter version\t0x%04x\n", info->ver.parm);
+	dev_info(dev, "AWB version\t0x%04x\n", info->ver.awb);
+}
 
-	case REG_CAPTURE:
-		ret = m5mols_reg_mode(sd, REG_MONITOR);
-		if (!ret && mode == REG_MONITOR)
-			break;
-		if (!ret)
-			ret = m5mols_reg_mode(sd, REG_PARAMETER);
-		break;
+/*
+ * get_res_preset - find out M5MOLS register value from requested resolution.
+ *
+ * @width: requested width
+ * @height: requested height
+ * @type: requested type of each modes. It supports only monitor mode now.
+ */
+static int get_res_preset(struct v4l2_subdev *sd, u16 width, u16 height,
+		enum m5mols_res_type type)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	int i;
 
-	default:
-		v4l2_warn(sd, "Wrong mode: %d\n", mode);
+	for (i = 0; i < ARRAY_SIZE(m5mols_resolutions); i++) {
+		if ((m5mols_resolutions[i].type == type) &&
+			(m5mols_resolutions[i].width == width) &&
+			(m5mols_resolutions[i].height == height))
+			break;
 	}
 
-	if (!ret)
-		info->mode = mode;
+	if (i >= ARRAY_SIZE(m5mols_resolutions)) {
+		v4l2msg("no matching resolution\n");
+		return -EINVAL;
+	}
 
-	return ret;
+	return m5mols_resolutions[i].value;
 }
 
-/**
- * m5mols_get_version - retrieve full revisions information of M-5MOLS
+/*
+ * get_fps - calc & check FPS from v4l2_captureparm, if FPS is adequate, set.
  *
- * The version information includes revisions of hardware and firmware,
- * AutoFocus alghorithm version and the version string.
+ * In M5MOLS case, the denominator means FPS. The each value of numerator and
+ * denominator should not be minus. If numerator is 0, it sets AUTO FPS. If
+ * numerator is not 1, it recalculates denominator. After it checks, the
+ * denominator is set to timeperframe.denominator, and used by FPS.
  */
-static int m5mols_get_version(struct v4l2_subdev *sd)
+static int get_fps(struct v4l2_subdev *sd,
+		struct v4l2_captureparm *parm)
 {
-	struct m5mols_info *info = to_m5mols(sd);
-	struct m5mols_version *ver = &info->ver;
-	u8 *str = ver->str;
-	int i;
-	int ret;
+	int numerator = parm->timeperframe.numerator;
+	int denominator = parm->timeperframe.denominator;
 
-	ret = m5mols_read_u8(sd, SYSTEM_VER_CUSTOMER, &ver->customer);
-	if (!ret)
-		ret = m5mols_read_u8(sd, SYSTEM_VER_PROJECT, &ver->project);
-	if (!ret)
-		ret = m5mols_read_u16(sd, SYSTEM_VER_FIRMWARE, &ver->fw);
-	if (!ret)
-		ret = m5mols_read_u16(sd, SYSTEM_VER_HARDWARE, &ver->hw);
-	if (!ret)
-		ret = m5mols_read_u16(sd, SYSTEM_VER_PARAMETER, &ver->param);
-	if (!ret)
-		ret = m5mols_read_u16(sd, SYSTEM_VER_AWB, &ver->awb);
-	if (!ret)
-		ret = m5mols_read_u8(sd, AF_VERSION, &ver->af);
-	if (ret)
-		return ret;
+	/* The denominator should be +, except 0. The numerator shoud be +. */
+	if (numerator < 0 || denominator <= 0)
+		return -EINVAL;
 
-	for (i = 0; i < VERSION_STRING_SIZE; i++) {
-		ret = m5mols_read_u8(sd, SYSTEM_VER_STRING, &str[i]);
-		if (ret)
-			return ret;
+	/* The numerator is 0, return auto fps. */
+	if (numerator == 0) {
+		parm->timeperframe.denominator = M5MOLS_FPS_AUTO;
+		return 0;
 	}
 
-	ver->fw = be16_to_cpu(ver->fw);
-	ver->hw = be16_to_cpu(ver->hw);
-	ver->param = be16_to_cpu(ver->param);
-	ver->awb = be16_to_cpu(ver->awb);
+	/* calc FPS(not time per frame) per 1 numerator */
+	denominator = denominator / numerator;
 
-	v4l2_info(sd, "Manufacturer\t[%s]\n",
-			is_manufacturer(info, REG_SAMSUNG_ELECTRO) ?
-			"Samsung Electro-Machanics" :
-			is_manufacturer(info, REG_SAMSUNG_OPTICS) ?
-			"Samsung Fiber-Optics" :
-			is_manufacturer(info, REG_SAMSUNG_TECHWIN) ?
-			"Samsung Techwin" : "None");
-	v4l2_info(sd, "Customer/Project\t[0x%02x/0x%02x]\n",
-			info->ver.customer, info->ver.project);
+	if (denominator < M5MOLS_FPS_AUTO || denominator > M5MOLS_FPS_MAX)
+		return -EINVAL;
 
-	if (!is_available_af(info))
-		v4l2_info(sd, "No support Auto Focus on this firmware\n");
+	if (!m5mols_reg_fps[denominator])
+		return -EINVAL;
 
-	return ret;
+	return 0;
 }
 
-/**
- * __find_restype - Lookup M-5MOLS resolution type according to pixel code
- * @code: pixel code
+/*
+ * to_code - return pixelcode of M5MOLS according to resolution type.
  */
-static enum m5mols_restype __find_restype(enum v4l2_mbus_pixelcode code)
+static enum v4l2_mbus_pixelcode to_code(enum m5mols_res_type res_type)
 {
-	enum m5mols_restype type = M5MOLS_RESTYPE_MONITOR;
+	return m5mols_formats[res_type].code;
+}
 
-	do {
-		if (code == m5mols_default_ffmt[type].code)
-			return type;
-	} while (type++ != SIZE_DEFAULT_FFMT);
+/*
+ * to_res_type - return resolution type of M5MOLS according to pixelcode.
+ */
+static enum m5mols_res_type to_res_type(struct v4l2_subdev *sd,
+		enum v4l2_mbus_pixelcode code)
+{
+	int i = ARRAY_SIZE(m5mols_formats);
 
-	return 0;
+	while (i--)
+		if (code == m5mols_formats[i].code)
+			break;
+	if (i < 0)
+		return M5MOLS_RES_MAX;
+
+	if (code == m5mols_formats[M5MOLS_RES_MON].code)
+		return M5MOLS_RES_MON;
+	else
+		return M5MOLS_RES_CAPTURE;
 }
 
-/**
- * __find_resolution - Lookup preset and type of M-5MOLS's resolution
- * @mf: pixel format to find/negotiate the resolution preset for
- * @type: M-5MOLS resolution type
- * @resolution:	M-5MOLS resolution preset register value
- *
- * Find nearest resolution matching resolution preset and adjust mf
- * to supported values.
- */
-static int __find_resolution(struct v4l2_subdev *sd,
-			     struct v4l2_mbus_framefmt *mf,
-			     enum m5mols_restype *type,
-			     u32 *resolution)
+static int m5mols_g_mbus_fmt(struct v4l2_subdev *sd,
+		struct v4l2_mbus_framefmt *ffmt)
 {
-	const struct m5mols_resolution *fsize = &m5mols_reg_res[0];
-	const struct m5mols_resolution *match = NULL;
-	enum m5mols_restype stype = __find_restype(mf->code);
-	int i = ARRAY_SIZE(m5mols_reg_res);
-	unsigned int min_err = ~0;
+	struct m5mols_info *info = to_m5mols(sd);
+	enum m5mols_res_type res_type;
 
-	while (i--) {
-		int err;
-		if (stype == fsize->type) {
-			err = abs(fsize->width - mf->width)
-				+ abs(fsize->height - mf->height);
+	res_type = to_res_type(sd, ffmt->code);
+	if (res_type == M5MOLS_RES_MAX)
+		return -EINVAL;
 
-			if (err < min_err) {
-				min_err = err;
-				match = fsize;
-			}
-		}
-		fsize++;
-	}
-	if (match) {
-		mf->width  = match->width;
-		mf->height = match->height;
-		*resolution = match->reg;
-		*type = stype;
-		return 0;
-	}
+	*ffmt = info->fmt[res_type];
+	info->code = ffmt->code;
 
-	return -EINVAL;
+	return 0;
 }
 
-static struct v4l2_mbus_framefmt *__find_format(struct m5mols_info *info,
-				struct v4l2_subdev_fh *fh,
-				enum v4l2_subdev_format_whence which,
-				enum m5mols_restype type)
+static int m5mols_into_monitor(struct v4l2_subdev *sd, int res_size)
 {
-	if (which == V4L2_SUBDEV_FORMAT_TRY)
-		return fh ? v4l2_subdev_get_try_format(fh, 0) : NULL;
+	int ret;
 
-	return &info->ffmt[type];
+	ret = m5mols_set_mode(sd, MODE_PARMSET);
+	if (!ret)
+		ret = i2c_w8_param(sd, CAT1_MONITOR_SIZE, (u8)res_size);
+	if (!ret)
+		ret = m5mols_set_mode(sd, MODE_PARMSET);
+
+	return ret;
 }
 
-static int m5mols_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
-			  struct v4l2_subdev_format *fmt)
+static int m5mols_into_capture(struct v4l2_subdev *sd, int res_size)
 {
 	struct m5mols_info *info = to_m5mols(sd);
-	struct v4l2_mbus_framefmt *format;
+	u32 reg;
+	int ret, timeout = 1;
+	u32 temp = 0;
 
-	if (fmt->pad != 0)
-		return -EINVAL;
+	info->captured = false;
 
-	format = __find_format(info, fh, fmt->which, info->res_type);
-	if (!format)
-		return -EINVAL;
+	/*
+	 * The sequence of preparing Capture mode.
+	 * 1. Clear Interrupt bit (for dummy)
+	 * 2. Enable Capture bit at Interrupt
+	 * 3. Lock AE/AWB
+	 * 4. Enter Still Capture mode
+	 */
 
-	fmt->format = *format;
-	return 0;
+	ret = m5mols_set_mode(sd, MODE_MONITOR);
+	if (!ret)
+		/* FIXME: setting capture exposure at the middle of a amount. */
+		ret = i2c_w16_ae(sd, CAT3_MANUAL_GAIN_CAP, 0x90);
+	if (!ret)
+		ret = m5mols_set_ae_lock(info, true);
+	if (!ret)
+		ret = m5mols_set_awb_lock(info, true);
+	if (!ret)
+		ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
+	if (!ret)
+		ret = i2c_w8_system(sd, CAT0_INT_ENABLE, 1 << INT_BIT_CAPTURE);
+	if (!ret)
+		ret = m5mols_set_mode(sd, MODE_CAPTURE);
+	if (!ret)
+		timeout = wait_event_interruptible_timeout(info->cap_wait,
+				info->captured, msecs_to_jiffies(2000));
+
+	/* disable all interrupt & clear interrupt */
+	ret = i2c_w8_system(sd, CAT0_INT_ENABLE, 0x0);
+	if (!ret)
+		ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
+	if (ret)
+		return -EPERM;
+
+	/* If all timeout exhausted, return error. */
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	ret = i2c_r32_capt_ctrl(sd, CATC_CAP_IMAGE_SIZE, &temp);
+	info->captured = false;
+	return ret;
 }
 
-static int m5mols_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
-			  struct v4l2_subdev_format *fmt)
+static int m5mols_s_mbus_fmt(struct v4l2_subdev *sd,
+		struct v4l2_mbus_framefmt *ffmt)
 {
 	struct m5mols_info *info = to_m5mols(sd);
-	struct v4l2_mbus_framefmt *format = &fmt->format;
-	struct v4l2_mbus_framefmt *sfmt;
-	enum m5mols_restype type;
-	u32 resolution = 0;
-	int ret;
+	enum m5mols_res_type res_type;
+	int size;
+	int ret = -EINVAL;
 
-	if (fmt->pad != 0)
+	res_type = to_res_type(sd, ffmt->code);
+	if (res_type == M5MOLS_RES_MAX)
 		return -EINVAL;
 
-	ret = __find_resolution(sd, format, &type, &resolution);
-	if (ret < 0)
-		return ret;
+	/* If user set portrait for preview, it is substitued width width height
+	 * unless get_res_preset will fail that M5MOLS did not support
+	 * reverse WVGA */
+	if (ffmt->width < ffmt->height) {
+		int temp;
+		temp  = ffmt->width;
+		ffmt->width = ffmt->height;
+		ffmt->height = temp;
+	}
+	size = get_res_preset(sd, ffmt->width, ffmt->height, res_type);
+	if (size < 0)
+		return -EINVAL;
 
-	sfmt = __find_format(info, fh, fmt->which, type);
-	if (!sfmt)
-		return 0;
+	if (ffmt->code == m5mols_formats[M5MOLS_RES_MON].code)
+		ret = m5mols_into_monitor(sd, size);
+	else
+		ret = m5mols_into_capture(sd, 0);
 
-	*sfmt		= m5mols_default_ffmt[type];
-	sfmt->width	= format->width;
-	sfmt->height	= format->height;
+	info->fmt[res_type]		= default_fmt[res_type];
+	info->fmt[res_type].width	= ffmt->width;
+	info->fmt[res_type].height	= ffmt->height;
 
-	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
-		info->resolution = resolution;
-		info->code = format->code;
-		info->res_type = type;
-	}
+	*ffmt = info->fmt[res_type];
+	info->code = ffmt->code;
 
-	return 0;
+	return ret;
 }
 
-static int m5mols_enum_mbus_code(struct v4l2_subdev *sd,
-				 struct v4l2_subdev_fh *fh,
-				 struct v4l2_subdev_mbus_code_enum *code)
+static int m5mols_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
+			      enum v4l2_mbus_pixelcode *code)
 {
-	if (!code || code->index >= SIZE_DEFAULT_FFMT)
+	if (!code || index >= ARRAY_SIZE(m5mols_formats))
 		return -EINVAL;
 
-	code->code = m5mols_default_ffmt[code->index].code;
+	*code = m5mols_formats[index].code;
 
 	return 0;
 }
 
-static struct v4l2_subdev_pad_ops m5mols_pad_ops = {
-	.enum_mbus_code	= m5mols_enum_mbus_code,
-	.get_fmt	= m5mols_get_fmt,
-	.set_fmt	= m5mols_set_fmt,
-};
+static int m5mols_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	struct v4l2_captureparm *cp = &parms->parm.capture;
 
-/**
- * m5mols_sync_controls - Apply default scene mode and the current controls
- *
- * This is used only streaming for syncing between v4l2_ctrl framework and
- * m5mols's controls. First, do the scenemode to the sensor, then call
- * v4l2_ctrl_handler_setup. It can be same between some commands and
- * the scenemode's in the default v4l2_ctrls. But, such commands of control
- * should be prior to the scenemode's one.
- */
-int m5mols_sync_controls(struct m5mols_info *info)
+	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+			parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	cp->capability = V4L2_CAP_TIMEPERFRAME;
+	cp->timeperframe = info->tpf;
+
+	return 0;
+}
+
+static int m5mols_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
 {
+	struct m5mols_info *info = to_m5mols(sd);
+	struct v4l2_captureparm *cp = &parms->parm.capture;
 	int ret = -EINVAL;
 
-	if (!is_ctrl_synced(info)) {
-		ret = m5mols_do_scenemode(info, REG_SCENE_NORMAL);
-		if (ret)
-			return ret;
+	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+			parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
 
-		v4l2_ctrl_handler_setup(&info->handle);
-		info->ctrl_sync = true;
+	ret = m5mols_set_mode_backup(sd, MODE_PARMSET);
+	if (!ret)
+		ret = get_fps(sd, cp);	/* set right FPS to denominator. */
+	if (!ret)
+		ret = i2c_w8_param(sd, CAT1_MONITOR_FPS,
+				m5mols_reg_fps[cp->timeperframe.denominator]);
+	if (!ret)
+		ret = m5mols_set_mode_restore(sd);
+	if (!ret) {
+		cp->capability = V4L2_CAP_TIMEPERFRAME;
+		info->tpf = cp->timeperframe;
 	}
 
+	v4l2msg("denominator: %d / numerator: %d.\n",
+		cp->timeperframe.denominator, cp->timeperframe.numerator);
+
 	return ret;
 }
 
-/**
- * m5mols_start_monitor - Start the monitor mode
- *
- * Before applying the controls setup the resolution and frame rate
- * in PARAMETER mode, and then switch over to MONITOR mode.
- */
-static int m5mols_start_monitor(struct m5mols_info *info)
+static int m5mols_get_info_capture(struct v4l2_subdev *sd)
 {
-	struct v4l2_subdev *sd = &info->sd;
-	int ret;
+	struct m5mols_info *info = to_m5mols(sd);
+	struct m5mols_exif *exif = &info->cap.exif;
+	int denominator, numerator;
+	int ret = 0;
+
+	ret = i2c_r32_exif(sd, CAT7_INFO_EXPTIME_NU, &numerator);
+	if (!ret)
+		ret = i2c_r32_exif(sd, CAT7_INFO_EXPTIME_DE, &denominator);
+	if (!ret)
+		exif->exposure_time = (u32)(numerator / denominator);
+	if (ret)
+		return ret;
+
+	ret = i2c_r32_exif(sd, CAT7_INFO_TV_NU, &numerator);
+	if (!ret)
+		ret = i2c_r32_exif(sd, CAT7_INFO_TV_DE, &denominator);
+	if (!ret)
+		exif->shutter_speed = (u32)(numerator / denominator);
+	if (ret)
+		return ret;
 
-	ret = m5mols_mode(info, REG_PARAMETER);
+	ret = i2c_r32_exif(sd, CAT7_INFO_AV_NU, &numerator);
 	if (!ret)
-		ret = m5mols_write(sd, PARM_MON_SIZE, info->resolution);
+		ret = i2c_r32_exif(sd, CAT7_INFO_AV_DE, &denominator);
 	if (!ret)
-		ret = m5mols_write(sd, PARM_MON_FPS, REG_FPS_30);
+		exif->aperture = (u32)(numerator / denominator);
+	if (ret)
+		return ret;
+
+	ret = i2c_r32_exif(sd, CAT7_INFO_BV_NU, &numerator);
+	if (!ret)
+		ret = i2c_r32_exif(sd, CAT7_INFO_BV_DE, &denominator);
+	if (!ret)
+		exif->brightness = (u32)(numerator / denominator);
+	if (ret)
+		return ret;
+
+	ret = i2c_r32_exif(sd, CAT7_INFO_EBV_NU, &numerator);
+	if (!ret)
+		ret = i2c_r32_exif(sd, CAT7_INFO_EBV_DE, &denominator);
+	if (!ret)
+		exif->exposure_bias = (u32)(numerator / denominator);
+	if (ret)
+		return ret;
+
+	ret = i2c_r16_exif(sd, CAT7_INFO_ISO, (u32 *)&exif->iso_speed);
+	if (!ret)
+		ret = i2c_r16_exif(sd, CAT7_INFO_FLASH, (u32 *)&exif->flash);
+	if (!ret)
+		ret = i2c_r16_exif(sd, CAT7_INFO_SDR, (u32 *)&exif->sdr);
+	if (!ret)
+		ret = i2c_r16_exif(sd, CAT7_INFO_QVAL, (u32 *)&exif->qval);
+	if (ret)
+		return ret;
 	if (!ret)
-		ret = m5mols_mode(info, REG_MONITOR);
+		ret = i2c_r32_capt_ctrl(sd, CATC_CAP_IMAGE_SIZE,
+				&info->cap.main);
 	if (!ret)
-		ret = m5mols_sync_controls(info);
+		ret = i2c_r32_capt_ctrl(sd, CATC_CAP_THUMB_SIZE,
+				&info->cap.thumb);
+
+	info->cap.total = info->cap.main + info->cap.thumb;
+
+	v4l2_info(sd, "%s: capture total size %d\n", __func__, info->cap.total);
+	v4l2_info(sd, "%s: capture main size %d\n", __func__, info->cap.main);
+	v4l2_info(sd, "%s: capture thumb size %d\n", __func__, info->cap.thumb);
+	v4l2_info(sd, "%s: exposure_time %d\n", __func__, exif->exposure_time);
+	v4l2_info(sd, "%s: shutter_speed %d\n", __func__, exif->shutter_speed);
+	v4l2_info(sd, "%s: aperture %d\n", __func__, exif->aperture);
+	v4l2_info(sd, "%s: brightness %d\n", __func__, exif->brightness);
+	v4l2_info(sd, "%s: exposure_bias %d\n", __func__, exif->exposure_bias);
+	v4l2_info(sd, "%s: iso_speed %d\n", __func__, exif->iso_speed);
+	v4l2_info(sd, "%s: flash %d\n", __func__, exif->flash);
+	v4l2_info(sd, "%s: sdr %d\n", __func__, exif->sdr);
+	v4l2_info(sd, "%s: qval %d\n", __func__, exif->qval);
 
 	return ret;
 }
 
-static int m5mols_s_stream(struct v4l2_subdev *sd, int enable)
+/* TODO: not verified. */
+static int m5mols_start_capture(struct v4l2_subdev *sd)
 {
 	struct m5mols_info *info = to_m5mols(sd);
+	u32 reg, size;
+	int ret, timeout;
+
+	u8 reg_capt_fmt[] = {
+		0x10,	/* JPEG with header + Thumbnail JPEG(YUV422@QVGA) */
+	}; /* YUV422, JPEG(422), JPEG(420) */
+	info->captured = false;
+
+	size = get_res_preset(sd,
+			info->fmt[M5MOLS_RES_CAPTURE].width,
+			info->fmt[M5MOLS_RES_CAPTURE].height,
+			M5MOLS_RES_CAPTURE);
+	if (size < 0)
+		return -EINVAL;
+	ret = 0;
+	/*
+	 * The sequence of Starting Capture mode.
+	 * 1. Select capture Single or Multi
+	 * 2. Select format (YUV422, JPEG(YUV420, YUV422))
+	 * 3. Set image size preset of Capture
+	 * 4. Read Interrupt bit (for dummy)
+	 * 5. Enable Capture bit at Interrupt
+	 * 6. Start Capture
+	 * 7. Check interrupt and register value
+	 * 8. Get Image & Thumb size
+	 */
+	ret = i2c_w8_capt_ctrl(sd, CATC_CAP_SEL_FRAME, true);	/* single capture */
+	if (!ret)
+		ret = i2c_w8_capt_parm(sd, CATB_YUVOUT_MAIN, reg_capt_fmt[0]);
+	if (!ret)
+		ret = i2c_w8_capt_parm(sd, CATB_MAIN_IMAGE_SIZE, size);
+	if (!ret)
+		ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
+	if (!ret)
+		ret = i2c_w8_system(sd, CAT0_INT_ENABLE, 1 << INT_BIT_CAPTURE);
+	if (!ret)
+		ret = i2c_w8_capt_ctrl(sd, CATC_CAP_START, true);
+	if (!ret) {
+		timeout = wait_event_interruptible_timeout(info->cap_wait,
+				info->captured, msecs_to_jiffies(2000));
 
-	if (enable) {
-		int ret = -EINVAL;
+		if (info->captured) {
+			ret = m5mols_get_info_capture(sd);
+
+			if (!ret)
+				v4l2_subdev_notify(sd, info->cap.total, NULL);
+			else
+				return ret;
+		}
+
+		/* disable all interrupt & clear interrupt */
+		ret = i2c_w8_system(sd, CAT0_INT_ENABLE, 0x0);
+		if (!ret)
+			ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
+		if (ret)
+			return -EPERM;
 
-		if (is_code(info->code, M5MOLS_RESTYPE_MONITOR))
-			ret = m5mols_start_monitor(info);
-		if (is_code(info->code, M5MOLS_RESTYPE_CAPTURE))
-			ret = m5mols_start_capture(info);
+		/* If all timeout exhausted, return error. */
+		if (!timeout)
+			return -ETIMEDOUT;
 
-		return ret;
+		info->captured = false;
+
+		ret = 0;
 	}
 
-	return m5mols_mode(info, REG_PARAMETER);
+	/* TODO: complete capture. */
+
+	return ret;
+}
+
+static int m5mols_start_monitor(struct v4l2_subdev *sd)
+{
+	return m5mols_set_mode(sd, MODE_MONITOR);
+}
+
+static int m5mols_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+
+	if (enable) {
+		if (info->code == to_code(M5MOLS_RES_MON)) {
+			v4l2_info(sd, "%s : monitor mode\n", __func__);
+			return m5mols_start_monitor(sd);
+		}
+		if (info->code == to_code(M5MOLS_RES_CAPTURE)) {
+			v4l2_info(sd, "%s : capture mode\n", __func__);
+			return  m5mols_start_capture(sd);
+		}
+		return -EINVAL;
+	} else {
+		if (is_streaming(sd))
+			return m5mols_set_mode(sd, MODE_PARMSET);
+		return -EINVAL;
+	}
 }
 
 static const struct v4l2_subdev_video_ops m5mols_video_ops = {
-	.s_stream	= m5mols_s_stream,
+	.g_mbus_fmt		= m5mols_g_mbus_fmt,
+	.s_mbus_fmt		= m5mols_s_mbus_fmt,
+	.enum_mbus_fmt		= m5mols_enum_mbus_fmt,
+	.g_parm			= m5mols_g_parm,
+	.s_parm			= m5mols_s_parm,
+	.s_stream		= m5mols_s_stream,
 };
 
 static int m5mols_s_ctrl(struct v4l2_ctrl *ctrl)
 {
 	struct v4l2_subdev *sd = to_sd(ctrl);
-	struct m5mols_info *info = to_m5mols(sd);
 	int ret;
 
-	info->mode_save = info->mode;
-
-	ret = m5mols_mode(info, REG_PARAMETER);
+	ret = m5mols_set_mode_backup(sd, MODE_PARMSET);
 	if (!ret)
 		ret = m5mols_set_ctrl(ctrl);
 	if (!ret)
-		ret = m5mols_mode(info, info->mode_save);
+		ret = m5mols_set_mode_restore(sd);
 
 	return ret;
 }
 
+static int m5mols_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct v4l2_subdev *sd = to_sd(ctrl);
+	struct m5mols_info *info = to_m5mols(sd);
+	int ret = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_JPEG_ENCODEDSIZE:
+		ctrl->cur.val = info->cap.total;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
 static const struct v4l2_ctrl_ops m5mols_ctrl_ops = {
-	.s_ctrl	= m5mols_s_ctrl,
+	.s_ctrl = m5mols_s_ctrl,
+	.g_volatile_ctrl = m5mols_g_volatile_ctrl,
 };
 
+static const struct v4l2_ctrl_config ctrl_private[] = {
+	{
+		.ops = &m5mols_ctrl_ops,
+		.id = V4L2_CID_CAM_JPEG_MEMSIZE,
+		.name = "Jpeg memory size",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = M5MO_JPEG_MEMSIZE,
+		.step = 1,
+		.min = 0,
+		.def = M5MO_JPEG_MEMSIZE,
+		.is_private = 1,
+	}, {
+		.ops = &m5mols_ctrl_ops,
+		.id = V4L2_CID_CAM_JPEG_ENCODEDSIZE,
+		.name = "Jpeg encoded size",
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.flags = V4L2_CTRL_FLAG_SLIDER,
+		.max = M5MO_JPEG_MEMSIZE,
+		.step = 1,
+		.min = 0,
+		.def = 0,
+		.is_private = 1,
+		.is_volatile = 1,
+	},
+};
+/*
+ * m5mols_sensor_power - handle sensor power up/down.
+ *
+ * @enable: If it is true, power up. If is not, power down.
+ */
 static int m5mols_sensor_power(struct m5mols_info *info, bool enable)
 {
 	struct v4l2_subdev *sd = &info->sd;
-	struct i2c_client *client = v4l2_get_subdevdata(sd);
-	const struct m5mols_platform_data *pdata = info->pdata;
+	struct i2c_client *c = v4l2_get_subdevdata(sd);
 	int ret;
 
 	if (enable) {
-		if (is_powered(info))
+		if (is_powerup(sd))
 			return 0;
 
+		/* power-on additional power */
 		if (info->set_power) {
-			ret = info->set_power(&client->dev, 1);
+			ret = info->set_power(&c->dev, 1);
 			if (ret)
 				return ret;
 		}
 
 		ret = regulator_bulk_enable(ARRAY_SIZE(supplies), supplies);
-		if (ret) {
-			info->set_power(&client->dev, 0);
+		if (ret)
 			return ret;
-		}
 
-		gpio_set_value(pdata->gpio_reset, !pdata->reset_polarity);
+		gpio_set_value(info->pdata->gpio_rst, info->pdata->enable_rst);
 		usleep_range(1000, 1000);
-		info->power = true;
 
-		return ret;
-	}
+		info->power = true;
+	} else {
+		if (!is_powerup(sd))
+			return 0;
 
-	if (!is_powered(info))
-		return 0;
+		ret = regulator_bulk_disable(ARRAY_SIZE(supplies), supplies);
+		if (ret)
+			return ret;
 
-	ret = regulator_bulk_disable(ARRAY_SIZE(supplies), supplies);
-	if (ret)
-		return ret;
+		/* power-off additional power */
+		if (info->set_power) {
+			ret = info->set_power(&c->dev, 0);
+			if (ret)
+				return ret;
+		}
 
-	if (info->set_power)
-		info->set_power(&client->dev, 0);
+		info->power = false;
 
-	gpio_set_value(pdata->gpio_reset, pdata->reset_polarity);
-	usleep_range(1000, 1000);
-	info->power = false;
+		gpio_set_value(info->pdata->gpio_rst, !info->pdata->enable_rst);
+		usleep_range(1000, 1000);
+	}
 
 	return ret;
 }
 
-/* m5mols_update_fw - optional firmware update routine */
-int __attribute__ ((weak)) m5mols_update_fw(struct v4l2_subdev *sd,
-		int (*set_power)(struct m5mols_info *, bool))
+static void m5mols_irq_work(struct work_struct *work)
 {
-	return 0;
+	struct m5mols_info *info = container_of(work, struct m5mols_info, work);
+	struct v4l2_subdev *sd = &info->sd;
+	u32 reg;
+	int ret;
+	if (is_powerup(sd)) {
+		ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);
+		if (!ret) {
+			switch (reg & 0x0f) {
+			case (1 << INT_BIT_AF):
+				/* Except returning zero at just that upper
+				 * statments, not entering in this parenthesis.
+				 * The return value is below:
+				 * 0x0 : AF Fail
+				 * 0x2 : AF Success
+				 * 0x4 : Idle Status
+				 * 0x5 : Busy Status */
+				ret = i2c_r8_lens(sd, CATA_AF_STATUS, &reg);
+				if (!ret && (reg == 0x02))
+					info->is_focus = true;
+				else
+					info->is_focus = false;
+				printk("%s = AF %02x, focus %d\n",
+						__func__, reg, info->is_focus);
+				break;
+			case (1 << INT_BIT_CAPTURE):
+				printk("%s = CAPTURE\n", __func__);
+				if (!info->captured) {
+					wake_up_interruptible(&info->cap_wait);
+					info->captured = true;
+				}
+				break;
+			case (1 << INT_BIT_ZOOM):
+			case (1 << INT_BIT_FRAME_SYNC):
+			case (1 << INT_BIT_FD):
+			case (1 << INT_BIT_LENS_INIT):
+			case (1 << INT_BIT_SOUND):
+				printk("%s = Nothing : 0x%08x\n", __func__, reg);
+				break;
+			case (1 << INT_BIT_MODE):
+			default:
+				break;
+			}
+		}
+	}
 }
 
-/**
- * m5mols_sensor_armboot - Booting M-5MOLS internal ARM core.
+static irqreturn_t m5mols_irq_handler(int irq, void *data)
+{
+	struct v4l2_subdev *sd = data;
+	struct m5mols_info *info = to_m5mols(sd);
+
+	v4l2_info(sd, "%s\n", __func__);
+
+	schedule_work(&info->work);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * m5mols_sensor_armboot - booting M5MOLS internal ARM core-controller.
  *
- * Booting internal ARM core makes the M-5MOLS is ready for getting commands
- * with I2C. It's the first thing to be done after it powered up. It must wait
- * at least 520ms recommended by M-5MOLS datasheet, after executing arm booting.
+ * It makes to ready M5MOLS for I2C & MIPI interface. After it's powered up,
+ * it activates if it gets armboot command for I2C interface. After getting
+ * cmd, it must wait about least 500ms referenced by M5MOLS datasheet.
  */
 static int m5mols_sensor_armboot(struct v4l2_subdev *sd)
 {
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct m5mols_info *info = to_m5mols(sd);
+	static u8 m5mols_mipi_value = 0x02;
+	u32 reg;
 	int ret;
 
-	ret = m5mols_write(sd, FLASH_CAM_START, REG_START_ARM_BOOT);
+	/* 1. ARM booting */
+	ret = i2c_w8_flash(sd, CATC_CAM_START, true);
 	if (ret < 0)
 		return ret;
 
-	msleep(520);
-
-	ret = m5mols_get_version(sd);
-	if (!ret)
-		ret = m5mols_update_fw(sd, m5mols_sensor_power);
-	if (ret)
-		return ret;
+	msleep(500);
+	dev_dbg(&client->dev, "Success ARM Booting\n");
 
-	v4l2_dbg(1, m5mols_debug, sd, "Success ARM Booting\n");
+	/* after ARM booting, the M5MOLS state changed Parameter mode. */
+	info->mode = MODE_PARMSET;
 
-	ret = m5mols_write(sd, PARM_INTERFACE, REG_INTERFACE_MIPI);
+	ret = i2c_r8_system(sd, CAT0_INT_FACTOR, &reg);		/* clear intterupt */
 	if (!ret)
-		ret = m5mols_enable_interrupt(sd, REG_INT_AF);
+		ret = i2c_w8_system(sd, CAT0_INT_ENABLE, 0x0);	/* all disable */
+	if (!ret)
+		ret = get_version(sd);
+	if (!ret)
+		ret = i2c_w8_param(sd, CAT1_DATA_INTERFACE, m5mols_mipi_value);
+
+	m5mols_show_version(sd);
 
 	return ret;
 }
 
+/*
+ * m5mols_init_controls - initialization using v4l2_ctrl.
+ */
 static int m5mols_init_controls(struct m5mols_info *info)
 {
 	struct v4l2_subdev *sd = &info->sd;
-	u16 max_exposure;
-	u16 step_zoom;
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 max_ex_mon;
 	int ret;
 
-	/* Determine value's range & step of controls for various FW version */
-	ret = m5mols_read_u16(sd, AE_MAX_GAIN_MON, &max_exposure);
-	if (!ret)
-		step_zoom = is_manufacturer(info, REG_SAMSUNG_OPTICS) ? 31 : 1;
+	/* check minimum & maximum of M5MOLS controls */
+	ret = i2c_r16_ae(sd, CAT3_MAX_GAIN_MON, (u32 *)&max_ex_mon);
 	if (ret)
 		return ret;
 
-	v4l2_ctrl_handler_init(&info->handle, 6);
+	/* set the controls using v4l2 control frameworks */
+	v4l2_ctrl_handler_init(&info->handle, 9);
+
+	info->colorfx = v4l2_ctrl_new_std_menu(&info->handle,
+			&m5mols_ctrl_ops, V4L2_CID_COLORFX,
+			9, 1, V4L2_COLORFX_NONE);
+	info->autoexposure = v4l2_ctrl_new_std_menu(&info->handle,
+			&m5mols_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
+			1, 0, V4L2_EXPOSURE_AUTO);
+	info->exposure = v4l2_ctrl_new_std(&info->handle,
+			&m5mols_ctrl_ops, V4L2_CID_EXPOSURE,
+			0, max_ex_mon, 1, (int)max_ex_mon/2);
+	info->autofocus = v4l2_ctrl_new_std(&info->handle,
+			&m5mols_ctrl_ops, V4L2_CID_FOCUS_AUTO,
+			0, 1, 1, 0);
 	info->autowb = v4l2_ctrl_new_std(&info->handle,
 			&m5mols_ctrl_ops, V4L2_CID_AUTO_WHITE_BALANCE,
-			0, 1, 1, 0);
+			0, 1, 1, 1);
 	info->saturation = v4l2_ctrl_new_std(&info->handle,
 			&m5mols_ctrl_ops, V4L2_CID_SATURATION,
-			1, 5, 1, 3);
+			0, 6, 1, 3);
 	info->zoom = v4l2_ctrl_new_std(&info->handle,
 			&m5mols_ctrl_ops, V4L2_CID_ZOOM_ABSOLUTE,
-			1, 70, step_zoom, 1);
-	info->exposure = v4l2_ctrl_new_std(&info->handle,
-			&m5mols_ctrl_ops, V4L2_CID_EXPOSURE,
-			0, max_exposure, 1, (int)max_exposure/2);
-	info->colorfx = v4l2_ctrl_new_std_menu(&info->handle,
-			&m5mols_ctrl_ops, V4L2_CID_COLORFX,
-			4, (1 << V4L2_COLORFX_BW), V4L2_COLORFX_NONE);
-	info->autoexposure = v4l2_ctrl_new_std_menu(&info->handle,
-			&m5mols_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
-			1, 0, V4L2_EXPOSURE_MANUAL);
+			0, 70, 1, 0);
+	info->jpeg_size = v4l2_ctrl_new_custom(&info->handle,
+			&ctrl_private[0],
+			NULL);
+	info->encoded_size = v4l2_ctrl_new_custom(&info->handle,
+			&ctrl_private[1],
+			NULL);
 
 	sd->ctrl_handler = &info->handle;
+
 	if (info->handle.error) {
-		v4l2_err(sd, "Failed to initialize controls: %d\n", ret);
+		dev_err(&client->dev, "Failed to init controls, %d\n", ret);
 		v4l2_ctrl_handler_free(&info->handle);
 		return info->handle.error;
 	}
 
 	v4l2_ctrl_cluster(2, &info->autoexposure);
+	/* If above ctrl value is not good image, so it is better that not set */
+	v4l2_ctrl_handler_setup(&info->handle);
 
 	return 0;
 }
 
-/**
- * m5mols_s_power - Main sensor power control function
- *
- * To prevent breaking the lens when the sensor is powered off the Soft-Landing
- * algorithm is called where available. The Soft-Landing algorithm availability
- * dependends on the firmware provider.
+/*
+ * m5mols_setup_default - set default size & fps in the monitor mode.
  */
+static int m5mols_setup_default(struct v4l2_subdev *sd)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	int value;
+	int ret = -EINVAL;
+
+	value = get_res_preset(sd,
+			default_fmt[M5MOLS_RES_MON].width,
+			default_fmt[M5MOLS_RES_MON].height,
+			M5MOLS_RES_MON);
+	if (value >= 0)
+		ret = i2c_w8_param(sd, CAT1_MONITOR_SIZE, (u8)value);
+	if (!ret)
+		ret = i2c_w8_param(sd, CAT1_MONITOR_FPS,
+			m5mols_reg_fps[default_fps.denominator]);
+	if (!ret)
+		ret = m5mols_init_controls(info);
+	if (!ret)
+		ret = m5mols_set_ae_lock(info, false);
+	if (!ret)
+		ret = m5mols_set_awb_lock(info, false);
+	if (!ret) {
+		info->fmt[M5MOLS_RES_MON] = default_fmt[M5MOLS_RES_MON];
+		info->tpf = default_fps;
+
+		ret = 0;
+	}
+
+	return ret;
+}
+
 static int m5mols_s_power(struct v4l2_subdev *sd, int on)
 {
 	struct m5mols_info *info = to_m5mols(sd);
@@ -815,34 +1233,9 @@ static int m5mols_s_power(struct v4l2_subdev *sd, int on)
 		if (!ret)
 			ret = m5mols_sensor_armboot(sd);
 		if (!ret)
-			ret = m5mols_init_controls(info);
-		if (ret)
-			return ret;
-
-		info->ffmt[M5MOLS_RESTYPE_MONITOR] =
-			m5mols_default_ffmt[M5MOLS_RESTYPE_MONITOR];
-		info->ffmt[M5MOLS_RESTYPE_CAPTURE] =
-			m5mols_default_ffmt[M5MOLS_RESTYPE_CAPTURE];
-		return ret;
-	}
-
-	if (is_manufacturer(info, REG_SAMSUNG_TECHWIN)) {
-		ret = m5mols_mode(info, REG_MONITOR);
-		if (!ret)
-			ret = m5mols_write(sd, AF_EXECUTE, REG_AF_STOP);
-		if (!ret)
-			ret = m5mols_write(sd, AF_MODE, REG_AF_POWEROFF);
-		if (!ret)
-			ret = m5mols_busy(sd, CAT_SYSTEM, CAT0_STATUS,
-					REG_AF_IDLE);
-		if (!ret)
-			v4l2_info(sd, "Success soft-landing lens\n");
-	}
-
-	ret = m5mols_sensor_power(info, false);
-	if (!ret) {
-		v4l2_ctrl_handler_free(&info->handle);
-		info->ctrl_sync = false;
+			ret = m5mols_setup_default(sd);
+	} else {
+		ret = m5mols_sensor_power(info, false);
 	}
 
 	return ret;
@@ -858,168 +1251,334 @@ static int m5mols_log_status(struct v4l2_subdev *sd)
 }
 
 static const struct v4l2_subdev_core_ops m5mols_core_ops = {
-	.s_power	= m5mols_s_power,
-	.g_ctrl		= v4l2_subdev_g_ctrl,
-	.s_ctrl		= v4l2_subdev_s_ctrl,
-	.queryctrl	= v4l2_subdev_queryctrl,
-	.querymenu	= v4l2_subdev_querymenu,
-	.g_ext_ctrls	= v4l2_subdev_g_ext_ctrls,
-	.try_ext_ctrls	= v4l2_subdev_try_ext_ctrls,
-	.s_ext_ctrls	= v4l2_subdev_s_ext_ctrls,
-	.log_status	= m5mols_log_status,
+	.s_power		= m5mols_s_power,
+	.g_ctrl			= v4l2_subdev_g_ctrl,
+	.s_ctrl			= v4l2_subdev_s_ctrl,
+	.queryctrl		= v4l2_subdev_queryctrl,
+	.querymenu		= v4l2_subdev_querymenu,
+	.g_ext_ctrls		= v4l2_subdev_g_ext_ctrls,
+	.try_ext_ctrls		= v4l2_subdev_try_ext_ctrls,
+	.s_ext_ctrls		= v4l2_subdev_s_ext_ctrls,
+	.log_status		= m5mols_log_status,
+};
+
+/**
+ * __find_restype - Lookup M-5MOLS resolution type according to pixel code
+ * @code: pixel code
+ */
+static enum m5mols_restype __find_restype(enum v4l2_mbus_pixelcode code)
+{
+	enum m5mols_restype type = M5MOLS_RESTYPE_MONITOR;
+
+	do {
+		if (code == default_fmt[type].code)
+			return type;
+	} while (type++ != SIZE_DEFAULT_FFMT);
+
+	return 0;
+}
+
+/**
+ * __find_resolution - Lookup preset and type of M-5MOLS's resolution
+ * @mf: pixel format to find/negotiate the resolution preset for
+ * @type: M-5MOLS resolution type
+ * @resolution:	M-5MOLS resolution preset register value
+ *
+ * Find nearest resolution matching resolution preset and adjust mf
+ * to supported values.
+ */
+static int __find_resolution(struct v4l2_subdev *sd,
+			     struct v4l2_mbus_framefmt *mf,
+			     enum m5mols_restype *type,
+			     u32 *resolution)
+{
+	const struct m5mols_resolution *fsize = &m5mols_resolutions[0];
+	const struct m5mols_resolution *match = NULL;
+	enum m5mols_restype stype = __find_restype(mf->code);
+	int i = ARRAY_SIZE(m5mols_resolutions);
+	unsigned int min_err = ~0;
+
+	while (i--) {
+		int err;
+		if (stype == fsize->type) {
+			err = abs(fsize->width - mf->width)
+				+ abs(fsize->height - mf->height);
+
+			if (err < min_err) {
+				min_err = err;
+				match = fsize;
+			}
+		}
+		fsize++;
+	}
+	if (match) {
+		mf->width  = match->width;
+		mf->height = match->height;
+		*resolution = match->value;
+		*type = stype;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static struct v4l2_mbus_framefmt *__find_format(struct m5mols_info *info,
+				struct v4l2_subdev_fh *fh,
+				enum v4l2_subdev_format_whence which,
+				enum m5mols_restype type)
+{
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return fh ? v4l2_subdev_get_try_format(fh, 0) : NULL;
+
+	return &info->fmt[type];
+}
+
+static int m5mols_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+			  struct v4l2_subdev_format *fmt)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	struct v4l2_mbus_framefmt *format;
+
+	if (fmt->pad != 0)
+		return -EINVAL;
+
+	format = __find_format(info, fh, fmt->which, info->res_type);
+	if (!format)
+		return -EINVAL;
+
+	fmt->format = *format;
+	return 0;
+}
+
+static int m5mols_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+			  struct v4l2_subdev_format *fmt)
+{
+	struct m5mols_info *info = to_m5mols(sd);
+	struct v4l2_mbus_framefmt *format = &fmt->format;
+	struct v4l2_mbus_framefmt *sfmt;
+	enum m5mols_restype type;
+	u32 resolution = 0;
+	int ret;
+
+	if (fmt->pad != 0)
+		return -EINVAL;
+
+	ret = __find_resolution(sd, format, &type, &resolution);
+	if (ret < 0)
+		return ret;
+
+	sfmt = __find_format(info, fh, fmt->which, type);
+	if (!sfmt)
+		return 0;
+
+	sfmt		= &default_fmt[type];
+	sfmt->width	= format->width;
+	sfmt->height	= format->height;
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		info->resolution = resolution;
+		info->code = format->code;
+		info->res_type = type;
+	}
+
+	return 0;
+}
+
+static int m5mols_enum_mbus_code(struct v4l2_subdev *sd,
+				 struct v4l2_subdev_fh *fh,
+				 struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (!code || code->index >= SIZE_DEFAULT_FFMT)
+		return -EINVAL;
+
+	code->code = default_fmt[code->index].code;
+
+	return 0;
+}
+
+static struct v4l2_subdev_pad_ops m5mols_pad_ops = {
+	.enum_mbus_code	= m5mols_enum_mbus_code,
+	.get_fmt	= m5mols_get_fmt,
+	.set_fmt	= m5mols_set_fmt,
 };
 
 static const struct v4l2_subdev_ops m5mols_ops = {
-	.core		= &m5mols_core_ops,
-	.pad		= &m5mols_pad_ops,
-	.video		= &m5mols_video_ops,
+	.core	= &m5mols_core_ops,
+	.pad	= &m5mols_pad_ops,
+	.video	= &m5mols_video_ops,
 };
 
-static void m5mols_irq_work(struct work_struct *work)
+static int m5mols_link_setup(struct media_entity *entity,
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
 {
-	struct m5mols_info *info =
-		container_of(work, struct m5mols_info, work_irq);
-	struct v4l2_subdev *sd = &info->sd;
-	u8 reg;
-	int ret;
+	printk("%s\n", __func__);
+	return 0;
+}
+static const struct media_entity_operations m5mols_media_ops = {
+	.link_setup = m5mols_link_setup,
+};
 
-	if (!is_powered(info) ||
-			m5mols_read_u8(sd, SYSTEM_INT_FACTOR, &info->interrupt))
-		return;
+static int m5mols_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+	struct v4l2_subdev_format format;
 
-	switch (info->interrupt & REG_INT_MASK) {
-	case REG_INT_AF:
-		if (!is_available_af(info))
-			break;
-		ret = m5mols_read_u8(sd, AF_STATUS, &reg);
-		v4l2_dbg(2, m5mols_debug, sd, "AF %s\n",
-			 reg == REG_AF_FAIL ? "Failed" :
-			 reg == REG_AF_SUCCESS ? "Success" :
-			 reg == REG_AF_IDLE ? "Idle" : "Busy");
-		break;
-	case REG_INT_CAPTURE:
-		if (!test_and_set_bit(ST_CAPT_IRQ, &info->flags))
-			wake_up_interruptible(&info->irq_waitq);
+	memset(&format, 0, sizeof(format));
+	format.pad = 0;
+	format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
+	format.format.code = m5mols_formats[M5MOLS_RES_MON].code;
+	format.format.width = DEFAULT_SENSOR_WIDTH;
+	format.format.height = DEFAULT_SENSOR_HEIGHT;
 
-		v4l2_dbg(2, m5mols_debug, sd, "CAPTURE\n");
-		break;
-	default:
-		v4l2_dbg(2, m5mols_debug, sd, "Undefined: %02x\n", reg);
-		break;
-	};
+	m5mols_set_fmt(sd, fh, &format);
+
+	return 0;
 }
 
-static irqreturn_t m5mols_irq_handler(int irq, void *data)
+static int m5mols_subdev_close(struct v4l2_subdev *sd,
+			      struct v4l2_subdev_fh *fh)
 {
-	struct v4l2_subdev *sd = data;
-	struct m5mols_info *info = to_m5mols(sd);
+	v4l2_dbg(1, m5mols_debug, sd, "%s", __func__);
+	return 0;
+}
 
-	schedule_work(&info->work_irq);
+static int m5mols_subdev_registered(struct v4l2_subdev *sd)
+{
+	v4l2_dbg(1, m5mols_debug, sd, "%s", __func__);
+	return 0;
+}
 
-	return IRQ_HANDLED;
+static void m5mols_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	v4l2_dbg(1, m5mols_debug, sd, "%s", __func__);
 }
 
-static int __devinit m5mols_probe(struct i2c_client *client,
-				  const struct i2c_device_id *id)
+static const struct v4l2_subdev_internal_ops m5mols_v4l2_internal_ops = {
+	.open = m5mols_init_formats,
+	.close = m5mols_subdev_close,
+	.registered = m5mols_subdev_registered,
+	.unregistered = m5mols_subdev_unregistered,
+};
+
+static int m5mols_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
 {
-	const struct m5mols_platform_data *pdata = client->dev.platform_data;
+	const struct m5mols_platform_data *pdata =
+		client->dev.platform_data;
 	struct m5mols_info *info;
 	struct v4l2_subdev *sd;
-	int ret;
+	int ret = 0;
 
 	if (pdata == NULL) {
 		dev_err(&client->dev, "No platform data\n");
 		return -EINVAL;
 	}
 
-	if (!gpio_is_valid(pdata->gpio_reset)) {
-		dev_err(&client->dev, "No valid RESET GPIO specified\n");
+	if (!gpio_is_valid(pdata->gpio_rst)) {
+		dev_err(&client->dev, "No valid nRST gpio pin.\n");
 		return -EINVAL;
 	}
 
 	if (!pdata->irq) {
-		dev_err(&client->dev, "Interrupt not assigned\n");
+		dev_err(&client->dev, "Interrupt not assigned.\n");
 		return -EINVAL;
 	}
 
 	info = kzalloc(sizeof(struct m5mols_info), GFP_KERNEL);
-	if (!info)
+	if (info == NULL) {
+		dev_err(&client->dev, "Failed to allocate info\n");
 		return -ENOMEM;
+	}
 
-	info->pdata = pdata;
-	info->set_power	= pdata->set_power;
+	info->pdata	= pdata;
+	if (info->pdata->set_power)	/* for additional power if needed. */
+		info->set_power = pdata->set_power;
+
+	if (info->pdata->irq) {
+		INIT_WORK(&info->work, m5mols_irq_work);
+		ret = request_irq(info->pdata->irq, m5mols_irq_handler,
+				  IRQF_TRIGGER_RISING, MOD_NAME, &info->sd);
+		if (ret) {
+			dev_err(&client->dev, "Failed to request irq: %d\n", ret);
+			return ret;
+		}
+	}
 
-	ret = gpio_request(pdata->gpio_reset, "M5MOLS_NRST");
+	ret = gpio_request(info->pdata->gpio_rst, "M5MOLS nRST");
 	if (ret) {
-		dev_err(&client->dev, "Failed to request gpio: %d\n", ret);
-		goto out_free;
+		dev_err(&client->dev, "Failed to set gpio, %d\n", ret);
+		goto out_gpio;
 	}
-	gpio_direction_output(pdata->gpio_reset, pdata->reset_polarity);
+
+	gpio_direction_output(info->pdata->gpio_rst, !info->pdata->enable_rst);
 
 	ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(supplies), supplies);
 	if (ret) {
-		dev_err(&client->dev, "Failed to get regulators: %d\n", ret);
-		goto out_gpio;
+		dev_err(&client->dev, "Failed to get regulators, %d\n", ret);
+		goto out_reg;
 	}
 
 	sd = &info->sd;
-	strlcpy(sd->name, MODULE_NAME, sizeof(sd->name));
-	v4l2_i2c_subdev_init(sd, client, &m5mols_ops);
+	strlcpy(sd->name, MOD_NAME, sizeof(sd->name));
+
+	init_waitqueue_head(&info->cap_wait);
 
+	v4l2_i2c_subdev_init(sd, client, &m5mols_ops);
 	info->pad.flags = MEDIA_PAD_FL_SOURCE;
 	ret = media_entity_init(&sd->entity, 1, &info->pad, 0);
 	if (ret < 0)
 		goto out_reg;
+
+	m5mols_init_formats(sd, NULL);
+
 	sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	sd->internal_ops = &m5mols_v4l2_internal_ops;
+	sd->entity.ops = &m5mols_media_ops;
 
-	init_waitqueue_head(&info->irq_waitq);
-	INIT_WORK(&info->work_irq, m5mols_irq_work);
-	ret = request_irq(pdata->irq, m5mols_irq_handler,
-			  IRQF_TRIGGER_RISING, MODULE_NAME, sd);
-	if (ret) {
-		dev_err(&client->dev, "Interrupt request failed: %d\n", ret);
-		goto out_me;
-	}
 	info->res_type = M5MOLS_RESTYPE_MONITOR;
+
+	v4l2_info(sd, "%s : m5mols driver probed success\n", __func__);
+
 	return 0;
-out_me:
-	media_entity_cleanup(&sd->entity);
+
 out_reg:
 	regulator_bulk_free(ARRAY_SIZE(supplies), supplies);
 out_gpio:
-	gpio_free(pdata->gpio_reset);
-out_free:
+	gpio_free(info->pdata->gpio_rst);
 	kfree(info);
+
 	return ret;
 }
 
-static int __devexit m5mols_remove(struct i2c_client *client)
+static int m5mols_remove(struct i2c_client *client)
 {
 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 	struct m5mols_info *info = to_m5mols(sd);
 
 	v4l2_device_unregister_subdev(sd);
+	v4l2_ctrl_handler_free(&info->handle);
 	free_irq(info->pdata->irq, sd);
-
 	regulator_bulk_free(ARRAY_SIZE(supplies), supplies);
-	gpio_free(info->pdata->gpio_reset);
+	gpio_free(info->pdata->gpio_rst);
 	media_entity_cleanup(&sd->entity);
 	kfree(info);
+
 	return 0;
 }
 
 static const struct i2c_device_id m5mols_id[] = {
-	{ MODULE_NAME, 0 },
+	{ MOD_NAME, 0 },
 	{ },
 };
 MODULE_DEVICE_TABLE(i2c, m5mols_id);
 
 static struct i2c_driver m5mols_i2c_driver = {
 	.driver = {
-		.name	= MODULE_NAME,
+		.name	= MOD_NAME,
 	},
 	.probe		= m5mols_probe,
-	.remove		= __devexit_p(m5mols_remove),
+	.remove		= m5mols_remove,
 	.id_table	= m5mols_id,
 };
 
@@ -1038,5 +1597,5 @@ module_exit(m5mols_mod_exit);
 
 MODULE_AUTHOR("HeungJun Kim <riverful.kim@samsung.com>");
 MODULE_AUTHOR("Dongsoo Kim <dongsoo45.kim@samsung.com>");
-MODULE_DESCRIPTION("Fujitsu M-5MOLS 8M Pixel camera driver");
+MODULE_DESCRIPTION("Fujitsu M5MOLS 8M Pixel camera sensor with ISP driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/m5mols/m5mols_reg.h b/drivers/media/video/m5mols/m5mols_reg.h
index c755bd6..da9cab5 100644
--- a/drivers/media/video/m5mols/m5mols_reg.h
+++ b/drivers/media/video/m5mols/m5mols_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register map for M-5MOLS 8M Pixel camera sensor with ISP
+ * Register map for M5MOLS 8M Pixel camera sensor with ISP
  *
  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  * Author: HeungJun Kim <riverful.kim@samsung.com>
@@ -16,258 +16,104 @@
 #ifndef M5MOLS_REG_H
 #define M5MOLS_REG_H
 
-#define M5MOLS_I2C_MAX_SIZE	4
-#define M5MOLS_BYTE_READ	0x01
-#define M5MOLS_BYTE_WRITE	0x02
-
-#define I2C_CATEGORY(__cat)		((__cat >> 16) & 0xff)
-#define I2C_COMMAND(__comm)		((__comm >> 8) & 0xff)
-#define I2C_SIZE(__reg_s)		((__reg_s) & 0xff)
-#define I2C_REG(__cat, __cmd, __reg_s)	((__cat << 16) | (__cmd << 8) | __reg_s)
-
 /*
  * Category section register
  *
- * The category means set including relevant command of M-5MOLS.
+ * The category means a kind of command set. Including category section,
+ * all defined categories in this version supports only, as you see below:
  */
 #define CAT_SYSTEM		0x00
 #define CAT_PARAM		0x01
-#define CAT_MONITOR		0x02
+#define CAT_MON			0x02
 #define CAT_AE			0x03
 #define CAT_WB			0x06
 #define CAT_EXIF		0x07
-#define CAT_FD			0x09
 #define CAT_LENS		0x0a
-#define CAT_CAPT_PARM		0x0b
-#define CAT_CAPT_CTRL		0x0c
-#define CAT_FLASH		0x0f	/* related to FW, revisions, booting */
+#define CAT_CAPTURE_PARAMETER	0x0b
+#define CAT_CAPTURE_CONTROL	0x0c
+#define CAT_FLASH		0x0f	/* related with FW, Verions, booting */
 
 /*
- * Category 0 - SYSTEM mode
- *
- * The SYSTEM mode in the M-5MOLS means area available to handle with the whole
- * & all-round system of sensor. It deals with version/interrupt/setting mode &
- * even sensor's status. Especially, the M-5MOLS sensor with ISP varies by
- * packaging & manufacturer, even the customer and project code. And the
- * function details may vary among them. The version information helps to
- * determine what methods shall be used in the driver.
+ * Category 0 - System
  *
- * There is many registers between customer version address and awb one. For
- * more specific contents, see definition if file m5mols.h.
+ * This category supports FW version, managing mode, even interrupt.
  */
-#define CAT0_VER_CUSTOMER	0x00	/* customer version */
-#define CAT0_VER_PROJECT	0x01	/* project version */
-#define CAT0_VER_FIRMWARE	0x02	/* Firmware version */
-#define CAT0_VER_HARDWARE	0x04	/* Hardware version */
-#define CAT0_VER_PARAMETER	0x06	/* Parameter version */
-#define CAT0_VER_AWB		0x08	/* Auto WB version */
-#define CAT0_VER_STRING		0x0a	/* string including M-5MOLS */
-#define CAT0_SYSMODE		0x0b	/* SYSTEM mode register */
-#define CAT0_STATUS		0x0c	/* SYSTEM mode status register */
-#define CAT0_INT_FACTOR		0x10	/* interrupt pending register */
-#define CAT0_INT_ENABLE		0x11	/* interrupt enable register */
-
-#define SYSTEM_VER_CUSTOMER	I2C_REG(CAT_SYSTEM, CAT0_VER_CUSTOMER, 1)
-#define SYSTEM_VER_PROJECT	I2C_REG(CAT_SYSTEM, CAT0_VER_PROJECT, 1)
-#define SYSTEM_VER_FIRMWARE	I2C_REG(CAT_SYSTEM, CAT0_VER_FIRMWARE, 2)
-#define SYSTEM_VER_HARDWARE	I2C_REG(CAT_SYSTEM, CAT0_VER_HARDWARE, 2)
-#define SYSTEM_VER_PARAMETER	I2C_REG(CAT_SYSTEM, CAT0_VER_PARAMETER, 2)
-#define SYSTEM_VER_AWB		I2C_REG(CAT_SYSTEM, CAT0_VER_AWB, 2)
-
-#define SYSTEM_SYSMODE		I2C_REG(CAT_SYSTEM, CAT0_SYSMODE, 1)
-#define REG_SYSINIT		0x00	/* SYSTEM mode */
-#define REG_PARAMETER		0x01	/* PARAMETER mode */
-#define REG_MONITOR		0x02	/* MONITOR mode */
-#define REG_CAPTURE		0x03	/* CAPTURE mode */
-
-#define SYSTEM_CMD(__cmd)	I2C_REG(CAT_SYSTEM, cmd, 1)
-#define SYSTEM_VER_STRING	I2C_REG(CAT_SYSTEM, CAT0_VER_STRING, 1)
-#define REG_SAMSUNG_ELECTRO	"SE"	/* Samsung Electro-Mechanics */
-#define REG_SAMSUNG_OPTICS	"OP"	/* Samsung Fiber-Optics */
-#define REG_SAMSUNG_TECHWIN	"TB"	/* Samsung Techwin */
-
-#define SYSTEM_INT_FACTOR	I2C_REG(CAT_SYSTEM, CAT0_INT_FACTOR, 1)
-#define SYSTEM_INT_ENABLE	I2C_REG(CAT_SYSTEM, CAT0_INT_ENABLE, 1)
-#define REG_INT_MODE		(1 << 0)
-#define REG_INT_AF		(1 << 1)
-#define REG_INT_ZOOM		(1 << 2)
-#define REG_INT_CAPTURE		(1 << 3)
-#define REG_INT_FRAMESYNC	(1 << 4)
-#define REG_INT_FD		(1 << 5)
-#define REG_INT_LENS_INIT	(1 << 6)
-#define REG_INT_SOUND		(1 << 7)
-#define REG_INT_MASK		0x0f
+#define CAT0_CUSTOMER_CODE	0x00
+#define CAT0_PJ_CODE		0x01
+#define CAT0_VERSION_FW_H	0x02
+#define CAT0_VERSION_FW_L	0x03
+#define CAT0_VERSION_HW_H	0x04
+#define CAT0_VERSION_HW_L	0x05
+#define CAT0_VERSION_PARM_H	0x06
+#define CAT0_VERSION_PARM_L	0x07
+#define CAT0_VERSION_AWB_H	0x08
+#define CAT0_VERSION_AWB_L	0x09
+#define CAT0_SYSMODE		0x0b
+#define CAT0_STATUS		0x0c
+#define CAT0_INT_QUEUE		0x0e
+#define CAT0_INT_FACTOR		0x10	/* ver 10bit: 0x10, other 0x1c */
+#define CAT0_INT_ENABLE		0x11	/* ver 10bit: 0x11, other 0x10  */
+#define CAT0_INT_ROOTEN		0x12
+#define CAT0_INT_INFO		0x18
 
 /*
- * category 1 - PARAMETER mode
+ * category 1 - Parameter mode
  *
- * This category supports function of camera features of M-5MOLS. It means we
- * can handle with preview(MONITOR) resolution size/frame per second/interface
- * between the sensor and the Application Processor/even the image effect.
+ * This category is dealing with almost camera vendor. In spite of that,
+ * It's a register to be able to detailed value for whole camera syste.
+ * The key parameter like a resolution, FPS, data interface connecting
+ * with Mobile AP, even effects.
  */
-#define CAT1_DATA_INTERFACE	0x00	/* interface between sensor and AP */
-#define CAT1_MONITOR_SIZE	0x01	/* resolution at the MONITOR mode */
-#define CAT1_MONITOR_FPS	0x02	/* frame per second at this mode */
-#define CAT1_EFFECT		0x0b	/* image effects */
-
-#define PARM_MON_SIZE		I2C_REG(CAT_PARAM, CAT1_MONITOR_SIZE, 1)
-
-#define PARM_MON_FPS		I2C_REG(CAT_PARAM, CAT1_MONITOR_FPS, 1)
-#define REG_FPS_30		0x02
-
-#define PARM_INTERFACE		I2C_REG(CAT_PARAM, CAT1_DATA_INTERFACE, 1)
-#define REG_INTERFACE_MIPI	0x02
-
-#define PARM_EFFECT		I2C_REG(CAT_PARAM, CAT1_EFFECT, 1)
-#define REG_EFFECT_OFF		0x00
-#define REG_EFFECT_NEGA		0x01
-#define REG_EFFECT_EMBOSS	0x06
-#define REG_EFFECT_OUTLINE	0x07
-#define REG_EFFECT_WATERCOLOR	0x08
+#define CAT1_DATA_INTERFACE	0x00
+#define CAT1_MONITOR_SIZE	0x01
+#define CAT1_MONITOR_FPS	0x02
+#define CAT1_EFFECT		0x0b
 
 /*
- * Category 2 - MONITOR mode
+ * Category 2 - Monitor mode
  *
- * The MONITOR mode is same as preview mode as we said. The M-5MOLS has another
- * mode named "Preview", but this preview mode is used at the case specific
- * vider-recording mode. This mmode supports only YUYV format. On the other
- * hand, the JPEG & RAW formats is supports by CAPTURE mode. And, there are
- * another options like zoom/color effect(different with effect in PARAMETER
- * mode)/anti hand shaking algorithm.
+ * This category supports only monitoring mode. The monitoring mode means,
+ * similar to preview. It supports like a YUYV format. At the capture mode,
+ * it is handled like a JPEG & RAW formats.
  */
-#define CAT2_ZOOM		0x01	/* set the zoom position & execute */
-#define CAT2_ZOOM_STEP		0x03	/* set the zoom step */
-#define CAT2_CFIXB		0x09	/* CB value for color effect */
-#define CAT2_CFIXR		0x0a	/* CR value for color effect */
-#define CAT2_COLOR_EFFECT	0x0b	/* set on/off of color effect */
-#define CAT2_CHROMA_LVL		0x0f	/* set chroma level */
-#define CAT2_CHROMA_EN		0x10	/* set on/off of choroma */
-#define CAT2_EDGE_LVL		0x11	/* set sharpness level */
-#define CAT2_EDGE_EN		0x12	/* set on/off sharpness */
-#define CAT2_TONE_CTL		0x25	/* set tone color(contrast) */
-
-#define MON_ZOOM		I2C_REG(CAT_MONITOR, CAT2_ZOOM, 1)
-
-#define MON_CFIXR		I2C_REG(CAT_MONITOR, CAT2_CFIXR, 1)
-#define MON_CFIXB		I2C_REG(CAT_MONITOR, CAT2_CFIXB, 1)
-#define REG_CFIXB_SEPIA		0xd8
-#define REG_CFIXR_SEPIA		0x18
-
-#define MON_EFFECT		I2C_REG(CAT_MONITOR, CAT2_COLOR_EFFECT, 1)
-#define REG_COLOR_EFFECT_OFF	0x00
-#define REG_COLOR_EFFECT_ON	0x01
-
-#define MON_CHROMA_EN		I2C_REG(CAT_MONITOR, CAT2_CHROMA_EN, 1)
-#define MON_CHROMA_LVL		I2C_REG(CAT_MONITOR, CAT2_CHROMA_LVL, 1)
-#define REG_CHROMA_OFF		0x00
-#define REG_CHROMA_ON		0x01
-
-#define MON_EDGE_EN		I2C_REG(CAT_MONITOR, CAT2_EDGE_EN, 1)
-#define MON_EDGE_LVL		I2C_REG(CAT_MONITOR, CAT2_EDGE_LVL, 1)
-#define REG_EDGE_OFF		0x00
-#define REG_EDGE_ON		0x01
-
-#define MON_TONE_CTL		I2C_REG(CAT_MONITOR, CAT2_TONE_CTL, 1)
+#define CAT2_ZOOM		0x01
+#define CAT2_ZOOM_POSITION	0x02
+#define CAT2_ZOOM_STEP		0x03
+#define CAT2_CFIXB		0x09
+#define CAT2_CFIXR		0x0a
+#define CAT2_COLOR_EFFECT	0x0b
+#define CAT2_CHROMA_LVL		0x0f
+#define CAT2_CHROMA_EN		0x10
 
 /*
  * Category 3 - Auto Exposure
  *
- * The M-5MOLS exposure capbility is detailed as which is similar to digital
- * camera. This category supports AE locking/various AE mode(range of exposure)
- * /ISO/flickering/EV bias/shutter/meteoring, and anything else. And the
- * maximum/minimum exposure gain value depending on M-5MOLS firmware, may be
- * different. So, this category also provide getting the max/min values. And,
- * each MONITOR and CAPTURE mode has each gain/shutter/max exposure values.
+ * Currently, it supports only gain value with monitor mode. This device
+ * is able to support Shutter, Gain(similar with Aperture), Flicker, at
+ * monitor mode & capture mode both.
  */
-#define CAT3_AE_LOCK		0x00	/* locking Auto exposure */
-#define CAT3_AE_MODE		0x01	/* set AE mode, mode means range */
-#define CAT3_ISO		0x05	/* set ISO */
-#define CAT3_EV_PRESET_MONITOR	0x0a	/* EV(scenemode) preset for MONITOR */
-#define CAT3_EV_PRESET_CAPTURE	0x0b	/* EV(scenemode) preset for CAPTURE */
-#define CAT3_MANUAL_GAIN_MON	0x12	/* meteoring value for the MONITOR */
-#define CAT3_MAX_GAIN_MON	0x1a	/* max gain value for the MONITOR */
-#define CAT3_MANUAL_GAIN_CAP	0x26	/* meteoring value for the CAPTURE */
-#define CAT3_AE_INDEX		0x38	/* AE index */
-
-#define AE_LOCK			I2C_REG(CAT_AE, CAT3_AE_LOCK, 1)
-#define REG_AE_UNLOCK		0x00
-#define REG_AE_LOCK		0x01
-
-#define AE_MODE			I2C_REG(CAT_AE, CAT3_AE_MODE, 1)
-#define REG_AE_OFF		0x00	/* AE off */
-#define REG_AE_ALL		0x01	/* calc AE in all block integral */
-#define REG_AE_CENTER		0x03	/* calc AE in center weighted */
-#define REG_AE_SPOT		0x06	/* calc AE in specific spot */
-
-#define AE_ISO			I2C_REG(CAT_AE, CAT3_ISO, 1)
-#define REG_ISO_AUTO		0x00
-#define REG_ISO_50		0x01
-#define REG_ISO_100		0x02
-#define REG_ISO_200		0x03
-#define REG_ISO_400		0x04
-#define REG_ISO_800		0x05
-
-#define AE_EV_PRESET_MONITOR	I2C_REG(CAT_AE, CAT3_EV_PRESET_MONITOR, 1)
-#define AE_EV_PRESET_CAPTURE	I2C_REG(CAT_AE, CAT3_EV_PRESET_CAPTURE, 1)
-#define REG_SCENE_NORMAL	0x00
-#define REG_SCENE_PORTRAIT	0x01
-#define REG_SCENE_LANDSCAPE	0x02
-#define REG_SCENE_SPORTS	0x03
-#define REG_SCENE_PARTY_INDOOR	0x04
-#define REG_SCENE_BEACH_SNOW	0x05
-#define REG_SCENE_SUNSET	0x06
-#define REG_SCENE_DAWN_DUSK	0x07
-#define REG_SCENE_FALL		0x08
-#define REG_SCENE_NIGHT		0x09
-#define REG_SCENE_AGAINST_LIGHT	0x0a
-#define REG_SCENE_FIRE		0x0b
-#define REG_SCENE_TEXT		0x0c
-#define REG_SCENE_CANDLE	0x0d
-
-#define AE_MAN_GAIN_MON		I2C_REG(CAT_AE, CAT3_MANUAL_GAIN_MON, 2)
-#define AE_MAX_GAIN_MON		I2C_REG(CAT_AE, CAT3_MAX_GAIN_MON, 2)
-#define AE_MAN_GAIN_CAP		I2C_REG(CAT_AE, CAT3_MANUAL_GAIN_CAP, 2)
-
-#define AE_INDEX		I2C_REG(CAT_AE, CAT3_AE_INDEX, 1)
-#define REG_AE_INDEX_20_NEG	0x00
-#define REG_AE_INDEX_15_NEG	0x01
-#define REG_AE_INDEX_10_NEG	0x02
-#define REG_AE_INDEX_05_NEG	0x03
-#define REG_AE_INDEX_00		0x04
-#define REG_AE_INDEX_05_POS	0x05
-#define REG_AE_INDEX_10_POS	0x06
-#define REG_AE_INDEX_15_POS	0x07
-#define REG_AE_INDEX_20_POS	0x08
+#define CAT3_AE_LOCK		0x00
+#define CAT3_AE_MODE		0x01
+#define CAT3_MANUAL_GAIN_MON	0x12	/* 2 bytes operations belows */
+#define CAT3_MANUAL_SHUT_MON	0x14
+#define CAT3_MAX_EXPOSURE_MON	0x16
+#define CAT3_MAX_EXPOSURE_CAP	0x18
+#define CAT3_MAX_GAIN_MON	0x1a
+#define CAT3_MAX_GAIN_CAP	0x1c
+#define CAT3_MANUAL_GAIN_CAP	0x26
+#define CAT3_MANUAL_SHUT_CAP	0x28
 
 /*
  * Category 6 - White Balance
  *
- * This category provide AWB locking/mode/preset/speed/gain bias, etc.
+ * Currently, it supports only auto white balance.
  */
-#define CAT6_AWB_LOCK		0x00	/* locking Auto Whitebalance */
-#define CAT6_AWB_MODE		0x02	/* set Auto or Manual */
-#define CAT6_AWB_MANUAL		0x03	/* set Manual(preset) value */
-
-#define AWB_LOCK		I2C_REG(CAT_WB, CAT6_AWB_LOCK, 1)
-#define REG_AWB_UNLOCK		0x00
-#define REG_AWB_LOCK		0x01
-
-#define AWB_MODE		I2C_REG(CAT_WB, CAT6_AWB_MODE, 1)
-#define REG_AWB_AUTO		0x01	/* AWB off */
-#define REG_AWB_PRESET		0x02	/* AWB preset */
-
-#define AWB_MANUAL		I2C_REG(CAT_WB, CAT6_AWB_MANUAL, 1)
-#define REG_AWB_INCANDESCENT	0x01
-#define REG_AWB_FLUORESCENT_1	0x02
-#define REG_AWB_FLUORESCENT_2	0x03
-#define REG_AWB_DAYLIGHT	0x04
-#define REG_AWB_CLOUDY		0x05
-#define REG_AWB_SHADE		0x06
-#define REG_AWB_HORIZON		0x07
-#define REG_AWB_LEDLIGHT	0x09
+#define CAT6_AWB_LOCK		0x00
+#define CAT6_AWB_MODE		0x02
+#define CAT6_AWB_MANUAL		0x03
 
 /*
- * Category 7 - EXIF information
+ * Category 7 - EXIF Information
  */
 #define CAT7_INFO_EXPTIME_NU	0x00
 #define CAT7_INFO_EXPTIME_DE	0x04
@@ -284,127 +130,35 @@
 #define CAT7_INFO_SDR		0x2c
 #define CAT7_INFO_QVAL		0x2e
 
-#define EXIF_INFO_EXPTIME_NU	I2C_REG(CAT_EXIF, CAT7_INFO_EXPTIME_NU, 4)
-#define EXIF_INFO_EXPTIME_DE	I2C_REG(CAT_EXIF, CAT7_INFO_EXPTIME_DE, 4)
-#define EXIF_INFO_TV_NU		I2C_REG(CAT_EXIF, CAT7_INFO_TV_NU, 4)
-#define EXIF_INFO_TV_DE		I2C_REG(CAT_EXIF, CAT7_INFO_TV_DE, 4)
-#define EXIF_INFO_AV_NU		I2C_REG(CAT_EXIF, CAT7_INFO_AV_NU, 4)
-#define EXIF_INFO_AV_DE		I2C_REG(CAT_EXIF, CAT7_INFO_AV_DE, 4)
-#define EXIF_INFO_BV_NU		I2C_REG(CAT_EXIF, CAT7_INFO_BV_NU, 4)
-#define EXIF_INFO_BV_DE		I2C_REG(CAT_EXIF, CAT7_INFO_BV_DE, 4)
-#define EXIF_INFO_EBV_NU	I2C_REG(CAT_EXIF, CAT7_INFO_EBV_NU, 4)
-#define EXIF_INFO_EBV_DE	I2C_REG(CAT_EXIF, CAT7_INFO_EBV_DE, 4)
-#define EXIF_INFO_ISO		I2C_REG(CAT_EXIF, CAT7_INFO_ISO, 2)
-#define EXIF_INFO_FLASH		I2C_REG(CAT_EXIF, CAT7_INFO_FLASH, 2)
-#define EXIF_INFO_SDR		I2C_REG(CAT_EXIF, CAT7_INFO_SDR, 2)
-#define EXIF_INFO_QVAL		I2C_REG(CAT_EXIF, CAT7_INFO_QVAL, 2)
-
-/*
- * Category 9 - Face Detection
- */
-#define CAT9_FD_CTL		0x00
-
-#define FD_CTL			I2C_REG(CAT_FD, CAT9_FD_CTL, 1)
-#define BIT_FD_EN		0
-#define BIT_FD_DRAW_FACE_FRAME	4
-#define BIT_FD_DRAW_SMILE_LVL	6
-#define REG_FD(shift)		(1 << shift)
-#define REG_FD_OFF		0x0
-
 /*
  * Category A - Lens Parameter
  */
+#define CATA_INIT_AF_FUNC	0x00
 #define CATA_AF_MODE		0x01
-#define CATA_AF_EXECUTE		0x02
+#define CATA_AF_EXCUTE		0x02
 #define CATA_AF_STATUS		0x03
 #define CATA_AF_VERSION		0x0a
 
-#define AF_MODE			I2C_REG(CAT_LENS, CATA_AF_MODE, 1)
-#define REG_AF_NORMAL		0x00	/* Normal AF, one time */
-#define REG_AF_MACRO		0x01	/* Macro AF, one time */
-#define REG_AF_POWEROFF		0x07
-
-#define AF_EXECUTE		I2C_REG(CAT_LENS, CATA_AF_EXECUTE, 1)
-#define REG_AF_STOP		0x00
-#define REG_AF_EXE_AUTO		0x01
-#define REG_AF_EXE_CAF		0x02
-
-#define AF_STATUS		I2C_REG(CAT_LENS, CATA_AF_STATUS, 1)
-#define REG_AF_FAIL		0x00
-#define REG_AF_SUCCESS		0x02
-#define REG_AF_IDLE		0x04
-#define REG_AF_BUSY		0x05
-
-#define AF_VERSION		I2C_REG(CAT_LENS, CATA_AF_VERSION, 1)
-
 /*
- * Category B - CAPTURE Parameter
+ * Category B - Capture Parameter
  */
 #define CATB_YUVOUT_MAIN	0x00
 #define CATB_MAIN_IMAGE_SIZE	0x01
-#define CATB_MCC_MODE		0x1d
-#define CATB_WDR_EN		0x2c
-#define CATB_LIGHT_CTRL		0x40
-#define CATB_FLASH_CTRL		0x41
-
-#define CAPP_YUVOUT_MAIN	I2C_REG(CAT_CAPT_PARM, CATB_YUVOUT_MAIN, 1)
-#define REG_YUV422		0x00
-#define REG_BAYER10		0x05
-#define REG_BAYER8		0x06
-#define REG_JPEG		0x10
-
-#define CAPP_MAIN_IMAGE_SIZE	I2C_REG(CAT_CAPT_PARM, CATB_MAIN_IMAGE_SIZE, 1)
-
-#define CAPP_MCC_MODE		I2C_REG(CAT_CAPT_PARM, CATB_MCC_MODE, 1)
-#define REG_MCC_OFF		0x00
-#define REG_MCC_NORMAL		0x01
-
-#define CAPP_WDR_EN		I2C_REG(CAT_CAPT_PARM, CATB_WDR_EN, 1)
-#define REG_WDR_OFF		0x00
-#define REG_WDR_ON		0x01
-#define REG_WDR_AUTO		0x02
-
-#define CAPP_LIGHT_CTRL		I2C_REG(CAT_CAPT_PARM, CATB_LIGHT_CTRL, 1)
-#define REG_LIGHT_OFF		0x00
-#define REG_LIGHT_ON		0x01
-#define REG_LIGHT_AUTO		0x02
-
-#define CAPP_FLASH_CTRL		I2C_REG(CAT_CAPT_PARM, CATB_FLASH_CTRL, 1)
-#define REG_FLASH_OFF		0x00
-#define REG_FLASH_ON		0x01
-#define REG_FLASH_AUTO		0x02
 
 /*
- * Category C - CAPTURE Control
+ * Category C - Capture Control
  */
-#define CATC_CAP_MODE		0x00
-#define CATC_CAP_SEL_FRAME	0x06	/* It determines Single or Multi */
+#define CATC_CAP_SEL_FRAME	0x06	/* It determines Single or Multi. */
 #define CATC_CAP_START		0x09
 #define CATC_CAP_IMAGE_SIZE	0x0d
 #define CATC_CAP_THUMB_SIZE	0x11
 
-#define CAPC_MODE		I2C_REG(CAT_CAPT_CTRL, CATC_CAP_MODE, 1)
-#define REG_CAP_NONE		0x00
-#define REG_CAP_ANTI_SHAKE	0x02
-
-#define CAPC_SEL_FRAME		I2C_REG(CAT_CAPT_CTRL, CATC_CAP_SEL_FRAME, 1)
-
-#define CAPC_START		I2C_REG(CAT_CAPT_CTRL, CATC_CAP_START, 1)
-#define REG_CAP_START_MAIN	0x01
-#define REG_CAP_START_THUMB	0x03
-
-#define CAPC_IMAGE_SIZE		I2C_REG(CAT_CAPT_CTRL, CATC_CAP_IMAGE_SIZE, 4)
-#define CAPC_THUMB_SIZE		I2C_REG(CAT_CAPT_CTRL, CATC_CAP_THUMB_SIZE, 4)
-
 /*
  * Category F - Flash
  *
- * This mode provides functions about internal flash stuff and system startup.
+ * This mode provides functions about internal Flash works and System startup.
  */
-#define CATF_CAM_START		0x12	/* It starts internal ARM core booting
+#define CATC_CAM_START		0x12	/* It start internal ARM core booting
 					 * after power-up */
 
-#define FLASH_CAM_START		I2C_REG(CAT_FLASH, CATF_CAM_START, 1)
-#define REG_START_ARM_BOOT	0x01
-
 #endif	/* M5MOLS_REG_H */
diff --git a/drivers/media/video/m9mo.c b/drivers/media/video/m9mo.c
new file mode 100644
index 0000000..8b67610
--- /dev/null
+++ b/drivers/media/video/m9mo.c
@@ -0,0 +1,4526 @@
+/*
+ * driver for Fusitju M9MO LS 8MP camera
+ *
+ * Copyright (c) 2010, Samsung Electronics. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <media/v4l2-device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/vmalloc.h>
+#include <linux/firmware.h>
+#include <linux/videodev2.h>
+
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/videodev2_exynos_media.h>
+#endif
+
+#include <linux/regulator/machine.h>
+
+#include <media/m9mo_platform.h>
+#include "m9mo.h"
+
+#define M9MO_DRIVER_NAME	"M9MO"
+
+extern struct class *camera_class;
+struct device *m9mo_dev;
+
+#if 0
+#define M9MO_FW_PATH		"/data/RS_M9MO.bin"
+#define FW_INFO_PATH		"/data/FW_INFO.bin"
+#endif
+
+#define M9MO_FW_PATH		"/sdcard/RS_M9MO.bin"
+#define M9MO_FW_REQ_PATH	"RS_M9MO.bin"
+#define FW_INFO_PATH		"/sdcard/FW_INFO.bin"
+
+
+#define M9MO_FW_DUMP_PATH	"/data/RS_M9LS_dump.bin"
+
+#define M9MOTB_FW_PATH "RS_M9LS_TB.bin" /* TECHWIN - SONY */
+/* #define M9MOON_FW_PATH "RS_M9LS_ON.bin" */ /* FIBEROPTICS - SONY */
+/* #define M9MOOM_FW_PATH "RS_M9LS_OM.bin" */ /* FIBEROPTICS - S.LSI */
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+#define M9MOSB_FW_PATH "RS_M9LS_SB.bin" /* ELECTRO-MECHANICS - SONY */
+#endif
+/* #define M9MOSC_FW_PATH "RS_M9LS_SC.bin" */ /* ELECTRO-MECHANICS - S.LSI */
+/* #define M9MOCB_FW_PATH "RS_M9LS_CB.bin" */ /* CAMSYS - SONY */
+#if defined(CONFIG_TARGET_LOCALE_NA)
+/* #define M9MOOE_FW_PATH "RS_M9LS_OE.bin" */ /* FIBEROPTICS - SONY */
+#endif
+#if defined(CONFIG_MACH_Q1_BD)
+#define M9MOOO_FW_PATH "RS_M9LS_OO.bin" /* FIBEROPTICS - SONY */
+#endif
+
+#if 0
+#define M9MO_FW_VER_LEN		22
+#define M9MO_FW_VER_FILE_CUR	0x16FF00
+#else
+#define M9MO_FW_VER_LEN		20
+#define M9MO_FW_VER_FILE_CUR	0x1FF080
+#endif
+
+#define M9MO_FLASH_BASE_ADDR	0x00000000
+
+#define M9MO_FLASH_READ_BASE_ADDR	0x000000
+
+#define M9MO_FLASH_BASE_ADDR_1	0x001FF000
+
+#define M9MO_INT_RAM_BASE_ADDR	0x01100000
+
+#define M9MO_I2C_RETRY		5
+#define M9MO_I2C_VERIFY		100
+#define M9MO_ISP_TIMEOUT	5000  /* timeout delay for m9mo 3000->5000 */
+#define M9MO_ISP_AFB_TIMEOUT	15000 /* FIXME */
+#define M9MO_ISP_ESD_TIMEOUT	1000
+
+#if 1
+#define M9MO_JPEG_MAXSIZE	0x3A0000
+#define M9MO_THUMB_MAXSIZE	0xFC00
+#define M9MO_POST_MAXSIZE	0xBB800
+#else
+#define M9MO_JPEG_MAXSIZE	0x43C600
+#define M9MO_THUMB_MAXSIZE	0x0
+#define M9MO_POST_MAXSIZE	0x0
+#endif
+
+#define M9MO_DEF_APEX_DEN	100
+
+#define m9mo_readb(sd, g, b, v)		m9mo_read(sd, 1, g, b, v)
+#define m9mo_readw(sd, g, b, v)		m9mo_read(sd, 2, g, b, v)
+#define m9mo_readl(sd, g, b, v)		m9mo_read(sd, 4, g, b, v)
+
+#define m9mo_writeb(sd, g, b, v)	m9mo_write(sd, 1, g, b, v)
+#define m9mo_writew(sd, g, b, v)	m9mo_write(sd, 2, g, b, v)
+#define m9mo_writel(sd, g, b, v)	m9mo_write(sd, 4, g, b, v)
+
+#define CHECK_ERR(x)	if ((x) < 0) { \
+				cam_err("i2c failed, err %d\n", x); \
+				return x; \
+			}
+
+#define NELEMS(array) (sizeof(array) / sizeof(array[0]))
+
+#if 0
+#define FAST_CAPTURE
+#endif
+
+static const struct m9mo_frmsizeenum preview_frmsizes[] = {
+	{ M9MO_PREVIEW_QCIF,	176,	144,	0x05 },	/* 176 x 144 */
+	{ M9MO_PREVIEW_QCIF2,	528,	432,	0x2C },	/* 176 x 144 */
+	{ M9MO_PREVIEW_QVGA,	320,	240,	0x09 },
+	{ M9MO_PREVIEW_VGA,	640,	480,	0x17 },
+	{ M9MO_PREVIEW_D1,	720,	480,	0x33 }, /* High speed */
+	{ M9MO_PREVIEW_WVGA,	800,	480,	0x1A },
+	{ M9MO_PREVIEW_720P,	1280,	720,	0x21 },
+
+#if defined(CONFIG_MACH_Q1_BD)
+	{ M9MO_PREVIEW_880_720,  880,	720,	0x2E },
+	{ M9MO_PREVIEW_1200_800, 1200,	800,	0x2F },
+	{ M9MO_PREVIEW_1280_800, 1280,	800,	0x35 },
+	{ M9MO_PREVIEW_1280_768, 1280,	768,	0x22 },
+	{ M9MO_PREVIEW_1072_800, 1072,	800,	0x36 },
+	{ M9MO_PREVIEW_980_800,	 980,	800,	0x37 },
+#endif
+
+	{ M9MO_PREVIEW_1080P,	1920,	1080,	0x28 },
+	{ M9MO_PREVIEW_HDR,	3264,	2448,	0x27 },
+	{ M9MO_PREVIEW_720P_60FPS,	1280, 720,	   0x25 },
+	{ M9MO_PREVIEW_VGA_60FPS,	640, 480,	   0x2F },
+
+};
+
+static const struct m9mo_frmsizeenum capture_frmsizes[] = {
+	{ M9MO_CAPTURE_1MP,	1024,	768,	0x0F },
+	{ M9MO_CAPTURE_2MPW,	1920,	1080,	0x19 },
+	{ M9MO_CAPTURE_3MP,	1984,	1488,	0x2F },
+	{ M9MO_CAPTURE_5MP,	2592,	1944,	0x20 },
+	{ M9MO_CAPTURE_8MP,	3264,	2448,	0x25 },
+	{ M9MO_CAPTURE_10MP,	3648,	2736,	0x30 },
+	{ M9MO_CAPTURE_12MPW,	4608,	2592,	0x31 },
+	{ M9MO_CAPTURE_14MP,	4608,	3072,	0x32 },
+	{ M9MO_CAPTURE_16MP,	4608,	3456,	0x33 },
+	/* for Postview size */
+	{ M9MO_CAPTURE_POSTWVGA,	800,	480,	0x09 },
+	{ M9MO_CAPTURE_POSTVGA,		640,	480,	0x08 },
+	{ M9MO_CAPTURE_POSTWHD,		1280,	720,	0x0F },
+	{ M9MO_CAPTURE_POSTHD,		960,	720,	0x13 },
+};
+
+static struct m9mo_control m9mo_ctrls[] = {
+	{
+		.id = V4L2_CID_CAMERA_ISO,
+		.minimum = ISO_AUTO,
+		.maximum = ISO_800,
+		.step = 1,
+		.value = ISO_AUTO,
+		.default_value = ISO_AUTO,
+	}, {
+		.id = V4L2_CID_CAMERA_BRIGHTNESS,
+		.minimum = EXPOSURE_MINUS_6,
+		.maximum = EXPOSURE_PLUS_6,
+		.step = 1,
+		.value = EXPOSURE_DEFAULT,
+		.default_value = EXPOSURE_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SATURATION,
+		.minimum = SATURATION_MINUS_2,
+		.maximum = SATURATION_MAX - 1,
+		.step = 1,
+		.value = SATURATION_DEFAULT,
+		.default_value = SATURATION_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SHARPNESS,
+		.minimum = SHARPNESS_MINUS_2,
+		.maximum = SHARPNESS_MAX - 1,
+		.step = 1,
+		.value = SHARPNESS_DEFAULT,
+		.default_value = SHARPNESS_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_ZOOM,
+		.minimum = ZOOM_LEVEL_0,
+		.maximum = ZOOM_LEVEL_MAX - 1,
+		.step = 1,
+		.value = ZOOM_LEVEL_0,
+		.default_value = ZOOM_LEVEL_0,
+	}, {
+		.id = V4L2_CID_CAM_JPEG_QUALITY,
+		.minimum = 1,
+		.maximum = 100,
+		.step = 1,
+		.value = 100,
+		.default_value = 100,
+	}, {
+		.id = V4L2_CID_CAMERA_ANTI_BANDING,
+		.minimum = ANTI_BANDING_AUTO,
+		.maximum = ANTI_BANDING_OFF,
+		.step = 1,
+		.value = ANTI_BANDING_50HZ,
+		.default_value = ANTI_BANDING_50HZ,
+	},
+};
+
+static inline struct m9mo_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct m9mo_state, sd);
+}
+
+static int m9mo_read(struct v4l2_subdev *sd,
+	u8 len, u8 category, u8 byte, int *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[5];
+	unsigned char recv_data[len + 1];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len != 0x01 && len != 0x02 && len != 0x04)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = msg.len;
+	data[1] = 0x01;			/* Read category parameters */
+	data[2] = category;
+	data[3] = byte;
+	data[4] = len;
+
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("category %#x, byte %#x\n", category, byte);
+		return err;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = sizeof(recv_data);
+	msg.buf = recv_data;
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("category %#x, byte %#x\n", category, byte);
+		return err;
+	}
+
+	if (recv_data[0] != sizeof(recv_data))
+		cam_i2c_dbg("expected length %d, but return length %d\n",
+				 sizeof(recv_data), recv_data[0]);
+
+	if (len == 0x01)
+		*val = recv_data[1];
+	else if (len == 0x02)
+		*val = recv_data[1] << 8 | recv_data[2];
+	else
+		*val = recv_data[1] << 24 | recv_data[2] << 16 |
+				recv_data[3] << 8 | recv_data[4];
+
+	cam_i2c_dbg("category %#02x, byte %#x, value %#x\n",
+			category, byte, *val);
+	return err;
+}
+
+static int m9mo_write(struct v4l2_subdev *sd,
+	u8 len, u8 category, u8 byte, int val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[len + 4];
+	int i, err;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len != 0x01 && len != 0x02 && len != 0x04)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	data[0] = msg.len;
+	data[1] = 0x02;			/* Write category parameters */
+	data[2] = category;
+	data[3] = byte;
+	if (len == 0x01) {
+		data[4] = val & 0xFF;
+	} else if (len == 0x02) {
+		data[4] = (val >> 8) & 0xFF;
+		data[5] = val & 0xFF;
+	} else {
+		data[4] = (val >> 24) & 0xFF;
+		data[5] = (val >> 16) & 0xFF;
+		data[6] = (val >> 8) & 0xFF;
+		data[7] = val & 0xFF;
+	}
+
+	cam_i2c_dbg("category %#x, byte %#x, value %#x\n", category, byte, val);
+
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	return err;
+}
+static int m9mo_mem_read_1(struct v4l2_subdev *sd, u16 len, u32 addr, u8 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[8];
+	unsigned char recv_data[len + 3];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len <= 0)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = 0x00;
+	data[1] = 0x03;
+	data[2] = 0x18;
+	data[3] = (addr >> 16) & 0xFF;
+	data[4] = (addr >> 8) & 0xFF;
+	data[5] = addr & 0xFF;
+	data[6] = (len >> 8) & 0xFF;
+	data[7] = len & 0xFF;
+
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	msg.flags = I2C_M_RD;
+	msg.len = sizeof(recv_data);
+	msg.buf = recv_data;
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	if (len != (recv_data[1] << 8 | recv_data[2]))
+		cam_i2c_dbg("expected length %d, but return length %d\n",
+			len, recv_data[1] << 8 | recv_data[2]);
+
+	memcpy(val, recv_data + 3, len);
+
+	cam_i2c_dbg("address %#x, length %d\n", addr, len);
+	return err;
+}
+static int m9mo_mem_read(struct v4l2_subdev *sd, u16 len, u32 addr, u8 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[8];
+	unsigned char recv_data[len + 3];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	if (len <= 0)
+		return -EINVAL;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = 0x00;
+	data[1] = 0x03;
+	data[2] = (addr >> 24) & 0xFF;
+	data[3] = (addr >> 16) & 0xFF;
+	data[4] = (addr >> 8) & 0xFF;
+	data[5] = addr & 0xFF;
+	data[6] = (len >> 8) & 0xFF;
+	data[7] = len & 0xFF;
+
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	msg.flags = I2C_M_RD;
+	msg.len = sizeof(recv_data);
+	msg.buf = recv_data;
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1)
+		return err;
+
+	if (len != (recv_data[1] << 8 | recv_data[2]))
+		cam_i2c_dbg("expected length %d, but return length %d\n",
+			len, recv_data[1] << 8 | recv_data[2]);
+
+	memcpy(val, recv_data + 3, len);
+
+	cam_i2c_dbg("address %#x, length %d\n", addr, len);
+	return err;
+}
+
+static int m9mo_mem_write(struct v4l2_subdev *sd, u8 cmd,
+		u16 len, u32 addr, u8 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char data[len + 8];
+	int i, err = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(data);
+	msg.buf = data;
+
+	/* high byte goes out first */
+	data[0] = 0x00;
+	data[1] = cmd;
+	data[2] = (addr >> 24) & 0xFF;
+	data[3] = (addr >> 16) & 0xFF;
+	data[4] = (addr >> 8) & 0xFF;
+	data[5] = addr & 0xFF;
+	data[6] = (len >> 8) & 0xFF;
+	data[7] = len & 0xFF;
+	memcpy(data + 2 + sizeof(addr) + sizeof(len), val, len);
+
+	cam_i2c_dbg("address %#x, length %d\n", addr, len);
+
+	for (i = M9MO_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	return err;
+}
+
+static irqreturn_t m9mo_isp_isr(int irq, void *dev_id)
+{
+	struct v4l2_subdev *sd = (struct v4l2_subdev *)dev_id;
+	struct m9mo_state *state = to_state(sd);
+
+	cam_dbg("**************** interrupt ****************\n");
+	state->isp.issued = 1;
+	wake_up_interruptible(&state->isp.wait);
+
+	return IRQ_HANDLED;
+}
+
+static u32 m9mo_wait_interrupt(struct v4l2_subdev *sd,
+	unsigned int timeout)
+{
+	struct m9mo_state *state = to_state(sd);
+	cam_trace("E\n");
+
+	if (wait_event_interruptible_timeout(state->isp.wait,
+		state->isp.issued == 1,
+		msecs_to_jiffies(timeout)) == 0) {
+		cam_err("timeout ~~~~~~~~~~~~~~~~~~~~~\n");
+		return 0;
+	}
+
+	state->isp.issued = 0;
+
+	m9mo_readw(sd, M9MO_CATEGORY_SYS,
+		M9MO_SYS_INT_FACTOR, &state->isp.int_factor);
+	cam_err("state->isp.int_factor = %x\n", state->isp.int_factor);
+	cam_trace("X\n");
+	return state->isp.int_factor;
+}
+
+static int m9mo_wait_framesync(struct v4l2_subdev *sd)
+{
+	int i, frame_sync_count = 0;
+	u32 int_factor;
+	s32 read_val = 0;
+	struct m9mo_state *state = to_state(sd);
+
+	 if (state->running_capture_mode == RUNNING_MODE_CONTINUOUS) {
+		cam_dbg("Start Continuous capture");
+		frame_sync_count = 9;
+	} else if (state->running_capture_mode == RUNNING_MODE_BRACKET
+	       || state->running_capture_mode == RUNNING_MODE_HDR) {
+		cam_dbg("Start AutoBracket(AEB) or HDR capture");
+		frame_sync_count = 3;
+	} else if (state->running_capture_mode == RUNNING_MODE_BLINK) {
+		cam_dbg("Start FaceDetect EyeBlink capture");
+		frame_sync_count = 3;
+	}
+
+	/* Clear Interrupt factor */
+	for (i = frame_sync_count; i; i--) {
+		int_factor = m9mo_wait_interrupt(sd,
+				M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_FRAME_SYNC)) {
+			cam_warn("M9MO_INT_FRAME_SYNC isn't issued, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+		m9mo_readb(sd,
+				M9MO_CATEGORY_SYS,
+				M9MO_SYS_FRAMESYNC_CNT,
+				&read_val);
+		cam_dbg("Frame interrupt M9MO_INT_FRAME_SYNC cnt[%d]\n",
+				read_val);
+	}
+
+	return 0;
+}
+
+static int m9mo_set_mode(struct v4l2_subdev *sd, u32 mode)
+{
+	int i, err;
+	u32 old_mode, val;
+	u32 int_factor;
+
+	cam_trace("E\n");
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_SYS, M9MO_SYS_MODE, &old_mode);
+
+	if (err < 0)
+		return err;
+
+	if (old_mode == mode) {
+		cam_dbg("%#x -> %#x\n", old_mode, mode);
+		return old_mode;
+	}
+
+	cam_dbg("%#x -> %#x\n", old_mode, mode);
+
+	switch (old_mode) {
+	case M9MO_SYSINIT_MODE:
+		cam_warn("sensor is initializing\n");
+		err = -EBUSY;
+		break;
+
+	case M9MO_PARMSET_MODE:
+		if (mode == M9MO_STILLCAP_MODE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_SYS,
+				M9MO_SYS_MODE, M9MO_MONITOR_MODE);
+			if (err < 0)
+				break;
+			for (i = M9MO_I2C_VERIFY; i; i--) {
+				err = m9mo_readb(sd, M9MO_CATEGORY_SYS,
+					M9MO_SYS_MODE, &val);
+				if (val == M9MO_MONITOR_MODE)
+					break;
+				msleep(20);
+			}
+		}
+	case M9MO_MONITOR_MODE:
+	case M9MO_STILLCAP_MODE:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_SYS, M9MO_SYS_MODE, mode);
+		break;
+
+	default:
+		cam_warn("current mode is unknown, %d\n", old_mode);
+		err = 0;/* -EINVAL; */
+	}
+
+	if (err < 0)
+		return err;
+
+	if (mode == M9MO_STILLCAP_MODE) {
+		m9mo_wait_framesync(sd);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	}
+
+	for (i = M9MO_I2C_VERIFY; i; i--) {
+		err = m9mo_readb(sd, M9MO_CATEGORY_SYS, M9MO_SYS_MODE, &val);
+		if (val == mode)
+			break;
+		msleep(20);
+	}
+
+	cam_trace("X\n");
+	return old_mode;
+}
+
+static int m9mo_set_capture_mode(struct v4l2_subdev *sd, int val)
+{
+	int err, capture_val, shutter_val;
+	struct m9mo_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	state->running_capture_mode = val;
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_ADJST,
+			M9MO_ADJST_SHUTTER_MODE, &shutter_val);
+	CHECK_ERR(err);
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_CAPCTRL,
+			M9MO_CAPCTRL_CAP_MODE, &capture_val);
+	CHECK_ERR(err);
+
+	switch (state->running_capture_mode) {
+	case RUNNING_MODE_CONTINUOUS:
+		if (shutter_val != 0x00) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_ADJST,
+					M9MO_ADJST_SHUTTER_MODE, 0x00);
+			CHECK_ERR(err);
+		}
+
+		if (capture_val != M9MO_CAP_MODE_MULTI_CAPTURE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_MODE,
+					M9MO_CAP_MODE_MULTI_CAPTURE);
+			CHECK_ERR(err);
+		}
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_CAP_FRM_COUNT, 0x09);
+		CHECK_ERR(err);
+
+#if 0
+		switch (state->) {
+		case _CONTI_3:
+			cam_trace("~~~~~~ Continuous 3 ~~~~~~\n");
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_FRM_INTERVAL, 0x03);
+			CHECK_ERR(err);
+			break;
+
+		case _CONTI_5:
+			cam_trace("~~~~~~ Continuous 5 ~~~~~~\n");
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_FRM_INTERVAL, 0x01);
+			CHECK_ERR(err);
+			break;
+
+		case _CONTI_10:
+			cam_trace("~~~~~~ Continuous 10 ~~~~~~\n");
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_FRM_INTERVAL, 0x00);
+			CHECK_ERR(err);
+			break;
+		}
+#endif
+		break;
+
+	case RUNNING_MODE_BRACKET:
+		cam_trace("~~~~~~ AutoBracket ~~~~~~\n");
+		if (shutter_val != 0x00) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_ADJST,
+					M9MO_ADJST_SHUTTER_MODE, 0x00);
+			CHECK_ERR(err);
+		}
+
+		if (capture_val != M9MO_CAP_MODE_BRACKET_CAPTURE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_MODE,
+					M9MO_CAP_MODE_BRACKET_CAPTURE);
+			CHECK_ERR(err);
+		}
+		break;
+
+	case RUNNING_MODE_HDR:
+		cam_trace("~~~~~~ HDRmode capture ~~~~~~\n");
+		if (shutter_val != 0x00) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_ADJST,
+					M9MO_ADJST_SHUTTER_MODE, 0x00);
+			CHECK_ERR(err);
+		}
+
+		if (capture_val != M9MO_CAP_MODE_BRACKET_CAPTURE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_MODE,
+					M9MO_CAP_MODE_BRACKET_CAPTURE);
+			CHECK_ERR(err);
+		}
+		break;
+
+	case RUNNING_MODE_BLINK:
+		cam_trace("~~~~~~ EyeBlink capture ~~~~~~\n");
+		if (shutter_val != 0x00) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_ADJST,
+					M9MO_ADJST_SHUTTER_MODE, 0x00);
+			CHECK_ERR(err);
+		}
+
+		if (capture_val != M9MO_CAP_MODE_BLINK_CAPTURE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_MODE,
+					M9MO_CAP_MODE_BLINK_CAPTURE);
+			CHECK_ERR(err);
+			/* Set frame rate (0x00, 12 fps) */
+			/* err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_FRM_INTERVAL, 0x00);
+			CHECK_ERR(err); */
+			/* Set frame count (0x03, 3 frames) */
+			/* err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_FRM_COUNT, 0x03);
+			CHECK_ERR(err); */
+		}
+		break;
+
+	case RUNNING_MODE_SINGLE:
+	default:
+		cam_trace("~~~~~~ Single capture ~~~~~~\n");
+		if (shutter_val != 0x01) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_ADJST,
+					M9MO_ADJST_SHUTTER_MODE, 0x01);
+			CHECK_ERR(err);
+		}
+
+		if (capture_val != M9MO_CAP_MODE_SINGLE_CAPTURE) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+					M9MO_CAPCTRL_CAP_MODE, 0x00);
+			CHECK_ERR(err);
+		}
+		break;
+	}
+
+	cam_trace("X\n");
+	return state->running_capture_mode;
+}
+
+
+/*
+ * v4l2_subdev_core_ops
+ */
+static int m9mo_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(m9mo_ctrls); i++) {
+		if (qc->id == m9mo_ctrls[i].id) {
+			qc->maximum = m9mo_ctrls[i].maximum;
+			qc->minimum = m9mo_ctrls[i].minimum;
+			qc->step = m9mo_ctrls[i].step;
+			qc->default_value = m9mo_ctrls[i].default_value;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+static int m9mo_get_af_result(struct v4l2_subdev *sd,
+		struct v4l2_control *ctrl);
+
+static int m9mo_get_scene_mode(struct v4l2_subdev *sd,
+		struct v4l2_control *ctrl)
+{
+	int err;
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_NEW,
+			M9MO_NEW_DETECT_SCENE, &ctrl->value);
+
+	return ctrl->value;
+}
+
+static int m9mo_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		m9mo_get_af_result(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAM_JPEG_MEMSIZE:
+		ctrl->value = M9MO_JPEG_MAXSIZE +
+			M9MO_THUMB_MAXSIZE + M9MO_POST_MAXSIZE;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_SIZE:
+		ctrl->value = state->jpeg.main_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_OFFSET:
+		ctrl->value = state->jpeg.main_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_SIZE:
+		ctrl->value = state->jpeg.thumb_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_OFFSET:
+		ctrl->value = state->jpeg.thumb_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_POSTVIEW_OFFSET:
+		ctrl->value = state->jpeg.postview_offset;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_FLASH:
+		ctrl->value = state->exif.flash;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_TV:
+		ctrl->value = state->exif.tv;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_BV:
+		ctrl->value = state->exif.bv;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_EBV:
+		ctrl->value = state->exif.ebv;
+		break;
+
+	case V4L2_CID_CAMERA_FD_EYE_BLINK_RESULT:
+		ctrl->value = state->fd_eyeblink_cap;
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = m9mo_get_scene_mode(sd, ctrl);
+		cam_info("Smart scene mode = %d\n", ctrl->value);
+		break;
+
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/*err = -ENOIOCTLCMD*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	return err;
+}
+
+static int m9mo_set_antibanding(struct v4l2_subdev *sd,
+		struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	struct m9mo_state *state = to_state(sd);
+	int val = ctrl->value, err;
+	u32 antibanding[] = {0x00, 0x01, 0x02, 0x03};
+
+	if (state->anti_banding == val)
+		return 0;
+
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_FLICKER, antibanding[val]);
+	CHECK_ERR(err);
+
+	state->anti_banding = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_af_softlanding(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	u32 status = 0;
+	int i, err = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	err = m9mo_set_mode(sd, M9MO_MONITOR_MODE);
+	if (err <= 0) {
+		cam_err("failed to set mode\n");
+		return err;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS, M9MO_LENS_AF_MODE, 0x07);
+	CHECK_ERR(err);
+
+	for (i = M9MO_I2C_VERIFY; i; i--) {
+		msleep(20);
+		err = m9mo_readb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_STATUS, &status);
+		CHECK_ERR(err);
+
+		if ((status & 0x01) == 0x00)
+			break;
+	}
+
+	if ((status & 0x01) != 0x00) {
+		cam_err("failed\n");
+		return -ETIMEDOUT;
+	}
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int m9mo_dump_fw(struct v4l2_subdev *sd)
+{
+	struct file *fp;
+	mm_segment_t old_fs;
+	u8 *buf/*, val*/;
+	u32 addr, unit, count, intram_unit = 0x1000;
+	int i, /*j,*/ err;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M9MO_FW_DUMP_PATH,
+		O_WRONLY|O_CREAT|O_TRUNC, S_IRUGO|S_IWUGO|S_IXUSR);
+	if (IS_ERR(fp)) {
+		cam_err("failed to open %s, err %ld\n",
+			M9MO_FW_DUMP_PATH, PTR_ERR(fp));
+		err = -ENOENT;
+		goto file_out;
+	}
+
+	buf = kmalloc(intram_unit, GFP_KERNEL);
+	if (!buf) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	cam_dbg("start, file path %s\n", M9MO_FW_DUMP_PATH);
+
+
+/*
+	val = 0x7E;
+	err = m9mo_mem_write(sd, 0x04, sizeof(val), 0x50000308, &val);
+	if (err < 0) {
+		cam_err("failed to write memory\n");
+		goto out;
+	}
+*/
+
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001200 , buf_port_seting0);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001000 , buf_port_seting1);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001100 , buf_port_seting2);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+				0x1C, 0x0247036D);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+				0x57, 01);
+
+	CHECK_ERR(err);
+
+
+	addr = M9MO_FLASH_READ_BASE_ADDR;
+	unit = SZ_4K;
+	count = 512;
+	for (i = 0; i < count; i++) {
+
+			err = m9mo_mem_read_1(sd,
+				unit, addr + (i * unit), buf);
+			cam_err("dump ~~ %d\n", i);
+			if (err < 0) {
+				cam_err("i2c falied, err %d\n", err);
+				goto out;
+			}
+			vfs_write(fp, buf, unit, &fp->f_pos);
+	}
+/*
+	addr = M9MO_FLASH_BASE_ADDR + SZ_64K * count;
+	unit = SZ_8K;
+	count = 4;
+	for (i = 0; i < count; i++) {
+		for (j = 0; j < unit; j += intram_unit) {
+			err = m9mo_mem_read(sd,
+				intram_unit, addr + (i * unit) + j, buf);
+			if (err < 0) {
+				cam_err("i2c falied, err %d\n", err);
+				goto out;
+			}
+			vfs_write(fp, buf, intram_unit, &fp->f_pos);
+		}
+	}
+*/
+	cam_dbg("end\n");
+
+out:
+	kfree(buf);
+	if (!IS_ERR(fp))
+		filp_close(fp, current->files);
+file_out:
+	set_fs(old_fs);
+
+	return err;
+}
+
+static int m9mo_get_sensor_fw_version(struct v4l2_subdev *sd,
+	char *buf)
+{
+#if 0
+	u8 val;
+	int err;
+#endif
+
+	cam_err("E\n");
+#if 0
+	buf = "SJEL01 Fujitsu M9MOLS";
+	return 0;
+#endif
+#if 0
+	/* set pin */
+	val = 0x7E;
+	err = m9mo_mem_write(sd, 0x04, sizeof(val), 0x50000308, &val);
+	CHECK_ERR(err);
+
+	err = m9mo_mem_read(sd, M9MO_FW_VER_LEN,
+		M9MO_FLASH_BASE_ADDR + M9MO_FW_VER_FILE_CUR, buf);
+#endif
+
+	cam_info("%s\n", buf);
+	return 0;
+}
+
+static int m9mo_get_phone_fw_version(struct v4l2_subdev *sd, char *buf)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	/*u8 sensor_ver[M9MO_FW_VER_LEN] = {0, };*/
+	const struct firmware *fw;
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long nread;
+	int fw_requested = 1;
+
+	cam_info("E\n");
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M9MO_FW_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n", M9MO_FW_PATH,
+			  PTR_ERR(fp));
+		goto request_fw;
+	} else {
+		cam_info("FW File(phone) opened.\n");
+	}
+
+	fw_requested = 0;
+
+	err = vfs_llseek(fp, M9MO_FW_VER_FILE_CUR, SEEK_SET);
+	if (err < 0) {
+		cam_warn("failed to fseek, %d\n", err);
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf, M9MO_FW_VER_LEN, &fp->f_pos);
+	if (nread != M9MO_FW_VER_LEN) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+
+#if 0
+		m9mo_get_sensor_fw_version(sd, sensor_ver);
+
+		if (sensor_ver[0] == 'T' && sensor_ver[1] == 'B') {
+			err = request_firmware(&fw, M9MOTB_FW_PATH, dev);
+#if defined(CONFIG_MACH_Q1_BD)
+		} else if (sensor_ver[0] == 'O' && sensor_ver[1] == 'O') {
+			err = request_firmware(&fw, M9MOOO_FW_PATH, dev);
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+		} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'B') {
+			err = request_firmware(&fw, M9MOSB_FW_PATH, dev);
+#endif
+		} else {
+			cam_warn("cannot find the matched F/W file\n");
+#if defined(CONFIG_MACH_Q1_BD)
+			err = request_firmware(&fw, M9MOOO_FW_PATH, dev);
+#elif defined(CONFIG_MACH_U1_KOR_LGT)
+			err = request_firmware(&fw, M9MOSB_FW_PATH, dev);
+#else
+			err = request_firmware(&fw, M9MOTB_FW_PATH, dev);
+#endif
+		}
+#else
+		cam_info("Firmware Path = %s\n", M9MO_FW_REQ_PATH);
+		err = request_firmware(&fw, M9MO_FW_REQ_PATH, dev);
+#endif
+
+		if (err != 0) {
+			cam_err("request_firmware falied\n");
+			err = -EINVAL;
+			goto out;
+		}
+
+		memcpy(buf, (u8 *)&fw->data[M9MO_FW_VER_FILE_CUR],
+		       M9MO_FW_VER_LEN);
+	}
+
+out:
+	if (!fw_requested) {
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	cam_dbg("%s\n", buf);
+	return 0;
+}
+
+static int m9mo_check_fw(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	u8 sensor_ver[M9MO_FW_VER_LEN] = "FAILED Fujitsu M9MO";
+	u8 phone_ver[M9MO_FW_VER_LEN] = "FAILED Fujitsu M9MO";
+	int af_cal_h = 0, af_cal_l = 0;
+	int rg_cal_h = 0, rg_cal_l = 0;
+	int bg_cal_h = 0, bg_cal_l = 0;
+	int update_count = 0;
+	u32 int_factor;
+	int err;
+
+	cam_trace("E\n");
+
+	/* F/W version */
+	m9mo_get_phone_fw_version(sd, phone_ver);
+
+#if 0
+	if (state->isp.bad_fw)
+		goto out;
+#endif
+
+	m9mo_get_sensor_fw_version(sd, sensor_ver);
+
+	goto out;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH, M9MO_FLASH_CAM_START, 0x01);
+	CHECK_ERR(err);
+
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_MODE)) {
+		cam_err("firmware was erased?\n");
+		return -ETIMEDOUT;
+	}
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_LENS, M9MO_LENS_AF_CAL, &af_cal_l);
+	CHECK_ERR(err);
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_ADJST,
+			M9MO_ADJST_AWB_RG_H, &rg_cal_h);
+	CHECK_ERR(err);
+	err = m9mo_readb(sd, M9MO_CATEGORY_ADJST,
+			M9MO_ADJST_AWB_RG_L, &rg_cal_l);
+	CHECK_ERR(err);
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_ADJST,
+			M9MO_ADJST_AWB_BG_H, &bg_cal_h);
+	CHECK_ERR(err);
+	err = m9mo_readb(sd, M9MO_CATEGORY_ADJST,
+			M9MO_ADJST_AWB_BG_L, &bg_cal_l);
+	CHECK_ERR(err);
+
+out:
+	if (!state->fw_version) {
+		state->fw_version = kzalloc(50, GFP_KERNEL);
+		if (!state->fw_version) {
+			cam_err("no memory for F/W version\n");
+			return -ENOMEM;
+		}
+	}
+
+	sprintf(state->fw_version, "%s %s %d %x %x %x %x %x %x",
+		sensor_ver, phone_ver, update_count,
+		af_cal_h, af_cal_l, rg_cal_h, rg_cal_l, bg_cal_h, bg_cal_l);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+#ifdef FAST_CAPTURE
+static int m9mo_set_fast_capture(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+	cam_info("E\n");
+
+	err = m9mo_set_mode(sd, M9MO_STILLCAP_MODE);
+	if (err < 0) {
+		cam_err("Mode change is failed to STILLCAP for fast capture\n");
+		return err;
+	} else {
+		cam_info("Fast capture is issued. mode change start.\n");
+	}
+	return 0;
+}
+#endif
+
+static int m9mo_set_sensor_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	err = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+	CHECK_ERR(err);
+
+	state->sensor_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_flash(struct v4l2_subdev *sd, int val, int force)
+{
+	struct m9mo_state *state = to_state(sd);
+	int strobe_en = 0;
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	if (!force)
+		state->flash_mode = val;
+
+	/* movie flash mode should be set when recording is started */
+	if (state->sensor_mode == SENSOR_MOVIE && !state->recording)
+		return 0;
+
+retry:
+	switch (val) {
+	case FLASH_MODE_OFF:
+		 strobe_en = 0;
+		break;
+
+	case FLASH_MODE_AUTO:
+		 strobe_en = 2;
+		break;
+
+	case FLASH_MODE_ON:
+		 strobe_en = 1;
+		break;
+
+	case FLASH_MODE_RED_EYE:
+		 strobe_en = 1;
+		break;
+
+	case FLASH_MODE_FILL_IN:
+		 strobe_en = 1;
+		break;
+
+	case FLASH_MODE_SLOW_SYNC:
+		 strobe_en = 1;
+		break;
+
+	case FLASH_MODE_RED_EYE_FIX:
+		strobe_en = 2;
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD,
+				M9MO_FD_RED_EYE, 0x01);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = FLASH_MODE_OFF;
+		goto retry;
+	}
+
+	if (val !=  FLASH_MODE_RED_EYE_FIX) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD,
+				M9MO_FD_RED_EYE, 0x00);
+		CHECK_ERR(err);
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_STROBE_EN, strobe_en);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_iso(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 iso[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07};
+
+	if (state->scene_mode != SCENE_MODE_NONE) {
+		/* sensor will set internally */
+		return 0;
+	}
+
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_ISOSEL, iso[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_metering(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case METERING_CENTER:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_MODE, 0x03);
+		CHECK_ERR(err);
+		break;
+	case METERING_SPOT:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_MODE, 0x05);
+		CHECK_ERR(err);
+		break;
+	case METERING_MATRIX:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_MODE, 0x01);
+		CHECK_ERR(err);
+		break;
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = METERING_CENTER;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_exposure(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	/*
+	   -6, -5, -4, +4, +5, +6 is not implemented in ISP
+	*/
+	u32 exposure[] = {0x00, 0x00, 0x00,
+		0x00, 0x0A, 0x14, 0x1E, 0x28,
+		0x32, 0x3C, 0x3C, 0x3C, 0x3C};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+		M9MO_AE_INDEX, exposure[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_whitebalance(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case WHITE_BALANCE_AUTO:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x01);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x01);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_SUNNY:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x04);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_CLOUDY:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x05);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_TUNGSTEN:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x01);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_FLUORESCENT:
+	case WHITE_BALANCE_FLUORESCENT_H:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x02);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_FLUORESCENT_L:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MODE, 0x02);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB,
+			M9MO_WB_AWB_MANUAL, 0x03);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = WHITE_BALANCE_AUTO;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_sharpness(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 sharpness[] = {0x03, 0x04, 0x05, 0x06, 0x07};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+		M9MO_MON_EDGE_LVL, sharpness[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_saturation(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err;
+	u32 saturation[] = {0x01, 0x02, 0x03, 0x04, 0x05};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	val -= qc.minimum;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+		M9MO_MON_CHROMA_LVL, saturation[val]);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_scene_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct v4l2_control ctrl;
+	int evp, sharpness, saturation;
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	sharpness = SHARPNESS_DEFAULT;
+	saturation = CONTRAST_DEFAULT;
+
+retry:
+	switch (val) {
+	case SCENE_MODE_NONE:
+		evp = 0x00;
+		break;
+
+	case SCENE_MODE_PORTRAIT:
+		evp = 0x01;
+		sharpness = SHARPNESS_MINUS_1;
+		break;
+
+	case SCENE_MODE_LANDSCAPE:
+		evp = 0x02;
+		sharpness = SHARPNESS_PLUS_1;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_SPORTS:
+		evp = 0x03;
+		break;
+
+	case SCENE_MODE_PARTY_INDOOR:
+		evp = 0x04;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_BEACH_SNOW:
+		evp = 0x05;
+		saturation = SATURATION_PLUS_1;
+		break;
+
+	case SCENE_MODE_SUNSET:
+		evp = 0x06;
+		break;
+
+	case SCENE_MODE_DUSK_DAWN:
+		evp = 0x07;
+		break;
+
+	case SCENE_MODE_FALL_COLOR:
+		evp = 0x08;
+		saturation = SATURATION_PLUS_2;
+		break;
+
+	case SCENE_MODE_NIGHTSHOT:
+		evp = 0x09;
+		break;
+
+	case SCENE_MODE_BACK_LIGHT:
+		evp = 0x0A;
+		break;
+
+	case SCENE_MODE_FIREWORKS:
+		evp = 0x0B;
+		break;
+
+	case SCENE_MODE_TEXT:
+		evp = 0x0C;
+		sharpness = SHARPNESS_PLUS_2;
+		break;
+
+	case SCENE_MODE_CANDLE_LIGHT:
+		evp = 0x0D;
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = SCENE_MODE_NONE;
+		goto retry;
+	}
+
+	/* EV-P */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_EP_MODE_MON, evp);
+	CHECK_ERR(err);
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_EP_MODE_CAP, evp);
+	CHECK_ERR(err);
+
+	/* Chroma Saturation */
+	ctrl.id = V4L2_CID_CAMERA_SATURATION;
+	ctrl.value = saturation;
+	m9mo_set_saturation(sd, &ctrl);
+
+	/* Sharpness */
+	ctrl.id = V4L2_CID_CAMERA_SHARPNESS;
+	ctrl.value = sharpness;
+	m9mo_set_sharpness(sd, &ctrl);
+
+	/* Emotional Color */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_MCC_MODE, val == SCENE_MODE_NONE ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	state->scene_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+
+static int m9mo_set_effect_color(struct v4l2_subdev *sd, int val)
+{
+	u32 int_factor;
+	int on, old_mode, cb, cr;
+	int err;
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_PARM, M9MO_PARM_EFFECT, &on);
+	CHECK_ERR(err);
+	if (on)	{
+		old_mode = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+		CHECK_ERR(old_mode);
+
+		err = m9mo_writeb(sd, M9MO_CATEGORY_PARM, M9MO_PARM_EFFECT, 0);
+		CHECK_ERR(err);
+
+		if (old_mode == M9MO_MONITOR_MODE) {
+			err = m9mo_set_mode(sd, old_mode);
+			CHECK_ERR(err);
+
+			int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+			if (!(int_factor & M9MO_INT_MODE)) {
+				cam_err("M9MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+			CHECK_ERR(err);
+		}
+	}
+
+	switch (val) {
+	case IMAGE_EFFECT_NONE:
+		break;
+
+	case IMAGE_EFFECT_SEPIA:
+		cb = 0xD8;
+		cr = 0x18;
+		break;
+
+	case IMAGE_EFFECT_BNW:
+		cb = 0x00;
+		cr = 0x00;
+		break;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+		M9MO_MON_COLOR_EFFECT, val == IMAGE_EFFECT_NONE ? 0x00 : 0x01);
+		CHECK_ERR(err);
+
+	if (val != IMAGE_EFFECT_NONE) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_MON, M9MO_MON_CFIXB, cb);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_MON, M9MO_MON_CFIXR, cr);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+static int m9mo_set_effect_gamma(struct v4l2_subdev *sd, s32 val)
+{
+	u32 int_factor;
+	int on, effect, old_mode;
+	int err;
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_MON, M9MO_MON_COLOR_EFFECT, &on);
+	CHECK_ERR(err);
+	if (on) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+			M9MO_MON_COLOR_EFFECT, 0);
+		CHECK_ERR(err);
+	}
+
+	switch (val) {
+	case IMAGE_EFFECT_NEGATIVE:
+		effect = 0x01;
+		break;
+
+	case IMAGE_EFFECT_AQUA:
+		effect = 0x08;
+		break;
+	}
+
+	old_mode = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+	CHECK_ERR(old_mode);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_PARM, M9MO_PARM_EFFECT, effect);
+	CHECK_ERR(err);
+
+	if (old_mode == M9MO_MONITOR_MODE) {
+		err = m9mo_set_mode(sd, old_mode);
+		CHECK_ERR(err);
+
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_MODE)) {
+			cam_err("M9MO_INT_MODE isn't issued, %#x\n",
+				int_factor);
+			return -ETIMEDOUT;
+		}
+		CHECK_ERR(err);
+	}
+
+	return err;
+}
+
+static int m9mo_set_effect(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case IMAGE_EFFECT_NONE:
+	case IMAGE_EFFECT_BNW:
+	case IMAGE_EFFECT_SEPIA:
+		err = m9mo_set_effect_color(sd, val);
+		CHECK_ERR(err);
+		break;
+
+	case IMAGE_EFFECT_AQUA:
+	case IMAGE_EFFECT_NEGATIVE:
+		err = m9mo_set_effect_gamma(sd, val);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = IMAGE_EFFECT_NONE;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_wdr(struct v4l2_subdev *sd, int val)
+{
+	int contrast, wdr, err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	contrast = (val == 1 ? 0x09 : 0x05);
+	wdr = (val == 1 ? 0x01 : 0x00);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+			M9MO_MON_TONE_CTRL, contrast);
+		CHECK_ERR(err);
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_WDR_EN, wdr);
+		CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_antishake(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int ahs, err;
+
+	if (state->scene_mode != SCENE_MODE_NONE) {
+		cam_warn("Should not be set with scene mode");
+		return 0;
+	}
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	ahs = (val == 1 ? 0x0E : 0x00);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_EP_MODE_MON, ahs);
+		CHECK_ERR(err);
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_EP_MODE_CAP, ahs);
+		CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_face_beauty(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_AFB_CAP_EN, val ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	state->face_beauty = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_lock(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+
+	cam_trace("%s\n", val ? "on" : "off");
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_LOCK, val);
+	CHECK_ERR(err);
+	err = m9mo_writeb(sd, M9MO_CATEGORY_WB, M9MO_AWB_LOCK, val);
+	CHECK_ERR(err);
+
+	state->focus.lock = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+static int m9mo_get_af_result(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	int status, err;
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_LENS,
+		M9MO_LENS_AF_STATUS, &status);
+
+	state->focus.status = status;
+	ctrl->value = status;
+	/*
+	   Get af result is not supported in ISP now. FIXME
+	 */
+	ctrl->value = 0x02;
+	return ctrl->value;
+}
+static int m9mo_set_af(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	/* int i, status; */
+	int err = 0;
+
+	cam_info("%s, mode %#x\n", val ? "start" : "stop", state->focus.mode);
+
+	state->focus.start = val;
+
+	/*
+	   Single AF is only supported in ISP now. FIXME
+	*/
+#if 0
+	if (state->focus.mode != FOCUS_MODE_CONTINOUS) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_START, val);
+		CHECK_ERR(err);
+
+		if (!(state->focus.touch &&
+			state->focus.mode == FOCUS_MODE_TOUCH)) {
+			if (val && state->focus.lock) {
+				m9mo_set_lock(sd, 0);
+				msleep(100);
+			}
+			m9mo_set_lock(sd, val);
+		}
+
+	} else {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_START, val ? 0x02 : 0x00);
+		CHECK_ERR(err);
+
+		err = -EBUSY;
+		for (i = M9MO_I2C_VERIFY; i && err; i--) {
+			msleep(20);
+			err = m9mo_readb(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_STATUS, &status);
+			CHECK_ERR(err);
+
+			if ((val && status == 0x05) || (!val && status != 0x05))
+				err = 0;
+		}
+	}
+#endif
+	if (state->focus.start == 1) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+				0x03, 0x00);
+		CHECK_ERR(err);
+		msleep(100);
+	}
+
+	cam_dbg("X\n");
+	return err;
+}
+
+static int m9mo_set_af_mode(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	u32 cancel, mode, status = 0;
+	int i, err;
+
+	cancel = val & FOCUS_MODE_DEFAULT;
+	val &= 0xFF;
+
+retry:
+	switch (val) {
+	case FOCUS_MODE_AUTO:
+		mode = 0x00;
+		break;
+
+	case FOCUS_MODE_MACRO:
+		mode = 0x01;
+		break;
+
+	case FOCUS_MODE_CONTINOUS:
+		mode = 0x02;
+		cancel = 0;
+		break;
+
+	case FOCUS_MODE_FACEDETECT:
+		mode = 0x03;
+		break;
+
+	case FOCUS_MODE_TOUCH:
+		mode = 0x04;
+		cancel = 0;
+		break;
+
+	case FOCUS_MODE_INFINITY:
+		mode = 0x06;
+		cancel = 0;
+		break;
+
+	default:
+		cam_warn("invalid value, %d", val);
+		val = FOCUS_MODE_AUTO;
+		goto retry;
+	}
+
+	if (cancel) {
+		m9mo_set_af(sd, 0);
+		m9mo_set_lock(sd, 0);
+	} else {
+		if (state->focus.mode == val)
+			return 0;
+	}
+
+	cam_dbg("E, value %d\n", val);
+
+	if (val == FOCUS_MODE_FACEDETECT) {
+		/* enable face detection */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_CTL, 0x11);
+		CHECK_ERR(err);
+		msleep(20);
+	} else if (state->focus.mode == FOCUS_MODE_FACEDETECT) {
+		/* disable face detection */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_CTL, 0x00);
+		CHECK_ERR(err);
+	}
+
+	state->focus.mode = val;
+
+	/* Lens barrel error is occured by this command now. FIXME */
+#if 0
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS, M9MO_LENS_AF_MODE, mode);
+	CHECK_ERR(err);
+#endif
+
+	for (i = M9MO_I2C_VERIFY; i; i--) {
+		msleep(20);
+		err = m9mo_readb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_STATUS, &status);
+		CHECK_ERR(err);
+
+		if (!(status & 0x01))
+			break;
+	}
+
+	if ((status & 0x01) != 0x00) {
+		cam_err("failed\n");
+		return -ETIMEDOUT;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_touch_auto_focus(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err = 0;
+	cam_info("%s\n", val ? "start" : "stop");
+
+	state->focus.touch = val;
+
+	if (val) {
+		err = m9mo_set_af_mode(sd, FOCUS_MODE_TOUCH);
+		if (err < 0) {
+			cam_err("m9mo_set_af_mode failed\n");
+			return err;
+		}
+		err = m9mo_writew(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_TOUCH_POSX, state->focus.pos_x);
+		CHECK_ERR(err);
+		err = m9mo_writew(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_TOUCH_POSY, state->focus.pos_y);
+		CHECK_ERR(err);
+	}
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int m9mo_set_zoom(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err, i;
+	int n_zoom[] = { 75, 150, 225, 300};
+	int zoom[] = { 4, 16, 28, 39};
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < (qc.minimum * 10) || val > (qc.maximum * 10)) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value * 10;
+	}
+
+	for (i = 0 ; i <= sizeof(n_zoom) ; i++) {
+		if (n_zoom[i] >= ctrl->value) {
+			val = i;
+			break;
+		}
+	}
+
+	if (val < 0 || val > 4) {
+		cam_warn("invalied value, %d\n", val);
+		val = 0;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_MON, M9MO_MON_ZOOM, zoom[val]);
+	CHECK_ERR(err);
+
+	state->zoom = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_optical_zoom_step(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, err, i;
+	int n_zoom[] = { 10, 12, 15, 18, 22, 28, 34, 40, 50, 61, 75,
+		94, 114, 139, 179, 210};
+
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < (qc.minimum * 10) || val > (qc.maximum * 10)) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value * 10;
+	}
+
+	for (i = 0 ; i <= sizeof(n_zoom) ; i++) {
+		if (n_zoom[i] >= ctrl->value) {
+			val = i;
+			break;
+		}
+	}
+
+	if (val < 0 || val > 0x0F) {
+		cam_warn("invalied value, %d\n", val);
+		val = 0;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_ZOOM_LEVEL, val);
+	CHECK_ERR(err);
+
+	state->optical_zoom = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_optical_zoom_ctrl(struct v4l2_subdev *sd, int val)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+	s32 zoom_step;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_ZOOM_CTRL, val);
+	CHECK_ERR(err);
+
+	err = m9mo_readb(sd, M9MO_CATEGORY_LENS,
+			M9MO_LENS_AF_ZOOM_LEVEL, &zoom_step);
+
+	state->optical_zoom = zoom_step;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_jpeg_quality(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl qc = {0,};
+	int val = ctrl->value, ratio, err;
+	cam_dbg("E, value %d\n", val);
+
+	qc.id = ctrl->id;
+	m9mo_queryctrl(sd, &qc);
+
+	if (val < qc.minimum || val > qc.maximum) {
+		cam_warn("invalied value, %d\n", val);
+		val = qc.default_value;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_JPEG_RATIO, 0x62);
+	CHECK_ERR(err);
+
+#if 0	/* m9mo */
+	if (val <= 65)		/* Normal */
+		ratio = 0x0A;
+	else if (val <= 75)	/* Fine */
+		ratio = 0x05;
+	else			/* Superfine */
+#endif
+		ratio = 0x00;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_JPEG_RATIO_OFS, ratio);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_get_exif(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	/* standard values */
+	u16 iso_std_values[] = { 10, 12, 16, 20, 25, 32, 40, 50, 64, 80,
+		100, 125, 160, 200, 250, 320, 400, 500, 640, 800,
+		1000, 1250, 1600, 2000, 2500, 3200, 4000, 5000, 6400, 8000};
+	/* quantization table */
+	u16 iso_qtable[] = { 11, 14, 17, 22, 28, 35, 44, 56, 71, 89,
+		112, 141, 178, 224, 282, 356, 449, 565, 712, 890,
+		1122, 1414, 1782, 2245, 2828, 3564, 4490, 5657, 7127, 8909};
+	int num, den, i, err;
+
+	/* exposure time */
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF,
+		M9MO_EXIF_EXPTIME_NUM, &num);
+	CHECK_ERR(err);
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF,
+		M9MO_EXIF_EXPTIME_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.exptime = (u32)num*1000/den;
+
+	/* flash */
+	err = m9mo_readw(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_FLASH, &num);
+	CHECK_ERR(err);
+	state->exif.flash = (u16)num;
+
+	/* iso */
+	err = m9mo_readw(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_ISO, &num);
+	CHECK_ERR(err);
+	for (i = 0; i < NELEMS(iso_qtable); i++) {
+		if (num <= iso_qtable[i]) {
+			state->exif.iso = iso_std_values[i];
+			break;
+		}
+	}
+
+	/* shutter speed */
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_TV_NUM, &num);
+	CHECK_ERR(err);
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_TV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.tv = num*M9MO_DEF_APEX_DEN/den;
+
+	/* brightness */
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_BV_NUM, &num);
+	CHECK_ERR(err);
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_BV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.bv = num*M9MO_DEF_APEX_DEN/den;
+
+	/* exposure */
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_EBV_NUM, &num);
+	CHECK_ERR(err);
+	err = m9mo_readl(sd, M9MO_CATEGORY_EXIF, M9MO_EXIF_EBV_DEN, &den);
+	CHECK_ERR(err);
+	state->exif.ebv = num*M9MO_DEF_APEX_DEN/den;
+
+	return err;
+}
+
+static int m9mo_get_fd_eye_blink_result(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+	s32 val_no = 1, val_level = 0;
+
+	/* EyeBlink error check FRAME No, Level */
+	err = m9mo_readb(sd, M9MO_CATEGORY_FD,
+			M9MO_FD_BLINK_FRAMENO, &val_no);
+	CHECK_ERR(err);
+	if (val_no < 1 || val_no > 3) {
+		val_no = 1;
+		cam_warn("Read Error FD_BLINK_FRAMENO [0x%x]\n", val_no);
+	}
+	err = m9mo_readb(sd, M9MO_CATEGORY_FD,
+			M9MO_FD_BLINK_LEVEL_1+val_no-1, &val_level);
+	CHECK_ERR(err);
+
+	if (val_level >= 0x05)
+		state->fd_eyeblink_cap = 1;
+	else
+		state->fd_eyeblink_cap = 0;
+	cam_dbg("blink no[%d] level[0x%x]\n", val_no, val_level);
+
+	return err;
+}
+
+static int m9mo_start_postview_capture(struct v4l2_subdev *sd, int frame_num)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err, int_factor;
+	cam_trace("E\n");
+
+	if (state->running_capture_mode == RUNNING_MODE_CONTINUOUS) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_PRV_SEL, frame_num);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	} else if (state->running_capture_mode == RUNNING_MODE_BRACKET) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_PRV_SEL, frame_num);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	} else if (state->running_capture_mode == RUNNING_MODE_HDR) {
+		cam_warn("HDR have no PostView\n");
+		return 0;
+	} else if (state->running_capture_mode == RUNNING_MODE_BLINK) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_PRV_SEL, 0xFF);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	} else {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_PRV_SEL, 0x01);
+	}
+	CHECK_ERR(err);
+
+	/* Set YUV out for Preview */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_YUVOUT_PREVIEW, 0x00);
+	CHECK_ERR(err);
+
+	/* Set Preview Image size */
+	if (FRM_RATIO(state->capture) == CAM_FRMRATIO_WVGA) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+				M9MO_CAPPARM_PREVIEW_IMG_SIZE, 0x0F);
+		CHECK_ERR(err);
+	} else if (FRM_RATIO(state->capture) == CAM_FRMRATIO_VGA) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+				M9MO_CAPPARM_PREVIEW_IMG_SIZE, 0x13);
+		CHECK_ERR(err);
+	}
+
+	/* Get Preview data */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+			M9MO_CAPCTRL_TRANSFER, 0x02);
+	CHECK_ERR(err);
+
+	/* Clear Interrupt factor */
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_CAPTURE)) {
+		cam_warn("M9MO_INT_CAPTURE isn't issued on transfer, %#x\n",
+				int_factor);
+		return -ETIMEDOUT;
+	}
+
+/*
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_IMG_SIZE,
+				&state->jpeg.main_size);
+	CHECK_ERR(err);
+
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_THUMB_SIZE,
+				&state->jpeg.thumb_size);
+	CHECK_ERR(err);
+
+	state->jpeg.main_offset = 0;
+	state->jpeg.thumb_offset = M9MO_JPEG_MAXSIZE;
+	state->jpeg.postview_offset = M9MO_JPEG_MAXSIZE + M9MO_THUMB_MAXSIZE;
+
+	m9mo_get_exif(sd);
+*/
+	cam_trace("X\n");
+	return err;
+}
+
+static int m9mo_start_YUV_capture(struct v4l2_subdev *sd, int frame_num)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err, int_factor;
+	cam_trace("E\n");
+
+	/* Select image number of frame */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+	M9MO_CAPCTRL_FRM_SEL, frame_num);
+	CHECK_ERR(err);
+
+	/* Clear Interrupt factor */
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_CAPTURE)) {
+		cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+				int_factor);
+		return -ETIMEDOUT;
+	}
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_YUVOUT_MAIN, 0x00);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_MAIN_IMG_SIZE, state->capture->reg_val);
+	CHECK_ERR(err);
+	cam_trace("Select image size [ width %d, height : %d ]\n",
+			state->capture->width, state->capture->height);
+
+	/* Get main YUV data */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+			M9MO_CAPCTRL_TRANSFER, 0x01);
+	CHECK_ERR(err);
+
+	/* Clear Interrupt factor */
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_CAPTURE)) {
+		cam_warn("M9MO_INT_CAPTURE isn't issued on transfer, %#x\n",
+				int_factor);
+		return -ETIMEDOUT;
+	}
+
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_IMG_SIZE,
+				&state->jpeg.main_size);
+	CHECK_ERR(err);
+/*
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_THUMB_SIZE,
+				&state->jpeg.thumb_size);
+	CHECK_ERR(err);
+
+	state->jpeg.main_offset = 0;
+	state->jpeg.thumb_offset = M9MO_JPEG_MAXSIZE;
+	state->jpeg.postview_offset = M9MO_JPEG_MAXSIZE + M9MO_THUMB_MAXSIZE;
+
+	m9mo_get_exif(sd);
+*/
+	cam_trace("X\n");
+	return err;
+}
+
+static int m9mo_start_capture(struct v4l2_subdev *sd, int frame_num)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err, int_factor;
+	cam_trace("E\n");
+
+	if (state->running_capture_mode == RUNNING_MODE_CONTINUOUS) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_SEL, frame_num);
+		CHECK_ERR(err);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	} else if (state->running_capture_mode == RUNNING_MODE_BRACKET) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_SEL, frame_num);
+		CHECK_ERR(err);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+	} else if (state->running_capture_mode == RUNNING_MODE_BLINK) {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_SEL, 0xFF);
+		CHECK_ERR(err);
+
+		/* Clear Interrupt factor */
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_CAPTURE)) {
+			cam_warn("M9MO_INT_CAPTURE isn't issued on frame select, %#x\n",
+					int_factor);
+			return -ETIMEDOUT;
+		}
+
+		err = m9mo_get_fd_eye_blink_result(sd);
+		CHECK_ERR(err);
+	} else {
+		/* Select image number of frame */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+				M9MO_CAPCTRL_FRM_SEL, 0x01);
+		CHECK_ERR(err);
+	}
+
+	/* Set main image JPEG fime max size */
+	err = m9mo_writel(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_JPEG_SIZE_MAX, 0x00500000);
+	CHECK_ERR(err);
+
+	/* Set main image JPEG fime min size */
+	err = m9mo_writel(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_JPEG_SIZE_MIN, 0x00100000);
+	CHECK_ERR(err);
+
+	/* Select main image format */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_YUVOUT_MAIN, 0x01);
+	CHECK_ERR(err);
+
+#if 0
+	/* Select main image size */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_MAIN_IMG_SIZE, 0x31);
+	CHECK_ERR(err);
+#endif
+
+	/* Get main JPEG data */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+			M9MO_CAPCTRL_TRANSFER, 0x01);
+
+	/* Clear Interrupt factor */
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_CAPTURE)) {
+		cam_warn("M9MO_INT_CAPTURE isn't issued on transfer, %#x\n",
+				int_factor);
+		return -ETIMEDOUT;
+	}
+
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_IMG_SIZE,
+				&state->jpeg.main_size);
+	CHECK_ERR(err);
+
+/*
+	err = m9mo_readl(sd, M9MO_CATEGORY_CAPCTRL, M9MO_CAPCTRL_THUMB_SIZE,
+				&state->jpeg.thumb_size);
+	CHECK_ERR(err);
+*/
+	state->jpeg.main_offset = 0;
+	state->jpeg.thumb_offset = M9MO_JPEG_MAXSIZE;
+	state->jpeg.postview_offset = M9MO_JPEG_MAXSIZE + M9MO_THUMB_MAXSIZE;
+
+	m9mo_get_exif(sd);
+
+	cam_trace("X\n");
+	return err;
+}
+
+/*static int m9mo_set_hdr(struct v4l2_subdev *sd, int val)
+{
+	cam_trace("E val : %d\n", val);
+	cam_trace("X\n");
+	return 0;
+}*/
+
+
+static int m9mo_set_facedetect(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	struct m9mo_state *state = to_state(sd);
+
+	cam_trace("E val : %d\n", val);
+
+	state->facedetect_mode = val;
+
+	switch (state->facedetect_mode) {
+	case FACE_DETECTION_NORMAL:
+		cam_dbg("~~~~~~ face detect on ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_SIZE, 0x04);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_MAX, 0x07);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_CTL, 0x11);
+		CHECK_ERR(err);
+
+#if 0	/* AF */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_SCAN_RANGE, 0x00);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_ADJ_TEMP_VALUE, 0x23);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_ALGORITHM, 0x00);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_SYS,
+				M9MO_SYS_INT_EN, M9MO_INT_AF);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+				M9MO_LENS_AF_START, 0x01);
+		CHECK_ERR(err);
+#endif
+		break;
+
+	case FACE_DETECTION_SMILE_SHOT:
+		cam_dbg("~~~~~~ fd smile shot ~~~~~~ val : %d\n", val);
+		break;
+
+	case FACE_DETECTION_BLINK:
+		cam_dbg("~~~~~~ fd eye blink ~~~~~~ val : %d\n", val);
+		break;
+
+	case FACE_DETECTION_OFF:
+	default:
+		cam_dbg("~~~~~~ face detect off ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_CTL, 0x00);
+		CHECK_ERR(err);
+		break;
+	}
+	cam_trace("X\n");
+	return 0;
+}
+
+
+static int m9mo_set_bracket(struct v4l2_subdev *sd, int val)
+{
+	cam_trace("E val : %d\n", val);
+
+	switch (val) {
+	case BRACKET_MODE_OFF:
+		cam_dbg("~~~~~~ bracket off ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_MODE_AEB:
+		cam_dbg("~~~~~~ bracket aeb on ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_MODE_WBB:
+		cam_dbg("~~~~~~ bracket wbb on ~~~~~~ val : %d\n", val);
+		break;
+
+	default:
+		cam_err("~~~~ TBD ~~~~ val : %d", val);
+		break;
+	}
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_bracket_aeb(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_trace("E val : %d\n", val);
+
+	switch (val) {
+	case BRACKET_AEB_VALUE1:
+		cam_trace("~~~~~~ AEB value1 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0x1E); /* EV 0.3 */
+		break;
+
+	case BRACKET_AEB_VALUE2:
+		cam_trace("~~~~~~ AEB value2 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0x3C); /* EV 0.6 */
+		break;
+
+	case BRACKET_AEB_VALUE3:
+		cam_trace("~~~~~~ AEB value3 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0x64); /* EV 1.0 */
+		break;
+
+	case BRACKET_AEB_VALUE4:
+		cam_trace("~~~~~~ AEB value4 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0x82); /* EV 1.3 */
+		break;
+
+	case BRACKET_AEB_VALUE5:
+		cam_trace("~~~~~~ AEB value5 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0xA0); /* EV 1.6 */
+		break;
+
+	case BRACKET_AEB_VALUE6:
+		cam_trace("~~~~~~ AEB value6 ~~~~~~ val : %d\n", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0xC8); /* EV 2.0 */
+		break;
+
+	default:
+		cam_err("~~~~ TBD ~~~~ val : %d", val);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+				M9MO_AE_AUTO_BRACKET_EV, 0x64); /* Ev 1.0 */
+		break;
+	}
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_bracket_wbb(struct v4l2_subdev *sd, int val)
+{
+	cam_trace("E val : %d\n", val);
+
+	switch (val) {
+	case BRACKET_WBB_VALUE1:
+		cam_trace("~~~~~~ WBB value1 ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_WBB_VALUE2:
+		cam_trace("~~~~~~ WBB value2 ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_WBB_VALUE3:
+		cam_trace("~~~~~~ WBB value3 ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_WBB_VALUE4:
+		cam_trace("~~~~~~ WBB value4 ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_WBB_VALUE5:
+		cam_trace("~~~~~~ WBB value5 ~~~~~~ val : %d\n", val);
+		break;
+
+	case BRACKET_WBB_VALUE6:
+		cam_trace("~~~~~~ WBB value6 ~~~~~~ val : %d\n", val);
+		break;
+
+	default:
+		cam_err("~~~~ TBD ~~~~ val : %d", val);
+		break;
+	}
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_fps(struct v4l2_subdev *sd, int val)
+{
+	int err, old_mode;
+	u32 int_factor;
+
+	struct m9mo_state *state = to_state(sd);
+	cam_trace("E val : %d\n", val);
+
+	if (state->preview == NULL) {
+		cam_trace("~~~~~~ return ~~~~~~\n");
+		return 0;
+	}
+
+	switch (val) {
+	case 30:
+		cam_trace("~~~~~~ 30 fps ~~~~~~\n");
+
+		old_mode = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+		CHECK_ERR(old_mode);
+
+		if (state->preview->height == 480) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+			M9MO_PARM_MON_SIZE, 0x17);
+			CHECK_ERR(err);
+		} else if (state->preview->height == 720) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+			M9MO_PARM_MON_SIZE, 0x21);
+			CHECK_ERR(err);
+		}
+
+		if (old_mode == M9MO_MONITOR_MODE) {
+			err = m9mo_set_mode(sd, old_mode);
+			CHECK_ERR(err);
+
+			int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+			if (!(int_factor & M9MO_INT_MODE)) {
+				cam_err("M9MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+			CHECK_ERR(err);
+		}
+		break;
+
+	case 60:
+		cam_trace("~~~~~~ 60 fps ~~~~~~\n");
+
+		old_mode = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+		CHECK_ERR(old_mode);
+
+		if (state->preview->height == 480) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+			M9MO_PARM_MON_SIZE, 0x2F);
+			CHECK_ERR(err);
+		} else if (state->preview->height == 720) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+			M9MO_PARM_MON_SIZE, 0x25);
+			CHECK_ERR(err);
+		}
+
+		if (old_mode == M9MO_MONITOR_MODE) {
+			err = m9mo_set_mode(sd, old_mode);
+			CHECK_ERR(err);
+
+			int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+			if (!(int_factor & M9MO_INT_MODE)) {
+				cam_err("M9MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+			CHECK_ERR(err);
+		}
+		break;
+
+	case 120:
+		cam_trace("~~~~~~ 120 fps ~~~~~~\n");
+		break;
+
+	default:
+		cam_err("~~~~ 30fps ~~~~\n");
+		break;
+	}
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_LDC(struct v4l2_subdev *sd, int val)
+{
+	int err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+	if (val == 1) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+				M9MO_MON_TONE_CTRL, 0x01);
+		CHECK_ERR(err);
+	} else {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+				M9MO_CAPPARM_WDR_EN, 0x00);
+		CHECK_ERR(err);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_LSC(struct v4l2_subdev *sd, int val)
+{
+	int err;
+
+	cam_dbg("%s\n", val ? "on" : "off");
+
+#if 0
+	if (val == 1) {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_MON,
+				M9MO_MON_TONE_CTRL, 0x01);
+		CHECK_ERR(err);
+	} else {
+		err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+				M9MO_CAPPARM_WDR_EN, 0x00);
+		CHECK_ERR(err);
+	}
+#endif
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_aperture(struct v4l2_subdev *sd, int val)
+{
+	int err;
+
+	cam_trace("E val : %d\n", val);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+			M9MO_AE_EP_MODE_MON, 0x0C);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_set_aeawblock(struct v4l2_subdev *sd, int val)
+{
+	int err;
+
+	cam_err("%d\n", val);
+	switch (val) {
+	case AE_UNLOCK_AWB_UNLOCK:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_LOCK, 0);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB, M9MO_AWB_LOCK, 0);
+		CHECK_ERR(err);
+		break;
+
+	case AE_LOCK_AWB_UNLOCK:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_LOCK, 1);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB, M9MO_AWB_LOCK, 0);
+		CHECK_ERR(err);
+		break;
+
+	case AE_UNLOCK_AWB_LOCK:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_LOCK, 0);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB, M9MO_AWB_LOCK, 1);
+		CHECK_ERR(err);
+		break;
+
+	case AE_LOCK_AWB_LOCK:
+		err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_LOCK, 1);
+		CHECK_ERR(err);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_WB, M9MO_AWB_LOCK, 1);
+		CHECK_ERR(err);
+		break;
+	}
+	cam_err("X\n");
+	return 0;
+}
+
+static int m9mo_check_dataline(struct v4l2_subdev *sd, int val)
+{
+	int err = 0;
+
+	cam_dbg("E, value %d\n", val);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_TEST,
+		M9MO_TEST_OUTPUT_YCO_TEST_DATA, val ? 0x01 : 0x00);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_check_esd(struct v4l2_subdev *sd)
+{
+	s32 val = 0;
+	int err = 0;
+
+	/* check ISP */
+	err = m9mo_readb(sd, M9MO_CATEGORY_TEST, M9MO_TEST_ISP_PROCESS, &val);
+	CHECK_ERR(err);
+	cam_dbg("progress %#x\n", val);
+
+	if (val != 0x80) {
+		goto esd_occur;
+	} else {
+		m9mo_wait_interrupt(sd, M9MO_ISP_ESD_TIMEOUT);
+
+		err = m9mo_readb(sd, M9MO_CATEGORY_SYS, M9MO_SYS_ESD_INT, &val);
+		CHECK_ERR(err);
+
+		if (val & M9MO_INT_ESD)
+			goto esd_occur;
+	}
+
+	cam_warn("ESD is not detected\n");
+	return 0;
+
+esd_occur:
+	cam_warn("ESD shock is detected\n");
+	return -EIO;
+}
+
+static int m9mo_g_ext_ctrl(struct v4l2_subdev *sd,
+		struct v4l2_ext_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_SENSOR_FW_VER:
+		strcpy(ctrl->string, state->exif.unique_id);
+		break;
+
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_CAMERA_CLASS_BASE);
+		/*err = -ENOIOCTLCMD*/
+		/*err = 0;*/
+		break;
+	}
+
+	/* FIXME
+	 * if (err < 0 && err != -ENOIOCTLCMD)
+	 *	cam_err("failed, id %d\n",
+		ctrl->id - V4L2_CID_CAMERA_CLASS_BASE);
+	 */
+
+	return err;
+}
+
+static int m9mo_g_ext_ctrls(struct v4l2_subdev *sd,
+		struct v4l2_ext_controls *ctrls)
+{
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int i, err = 0;
+
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		err = m9mo_g_ext_ctrl(sd, ctrl);
+		if (err) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+	return err;
+}
+
+static int m9mo_check_manufacturer_id(struct v4l2_subdev *sd)
+{
+	int i, err;
+	u8 id;
+	u32 addr[] = {0x1000AAAA, 0x10005554, 0x1000AAAA};
+	u8 val[3][2] = {
+		[0] = {0x00, 0xAA},
+		[1] = {0x00, 0x55},
+		[2] = {0x00, 0x90},
+	};
+	u8 reset[] = {0x00, 0xF0};
+
+	/* set manufacturer's ID read-mode */
+	for (i = 0; i < 3; i++) {
+		err = m9mo_mem_write(sd, 0x06, 2, addr[i], val[i]);
+		CHECK_ERR(err);
+	}
+
+	/* read manufacturer's ID */
+	err = m9mo_mem_read(sd, sizeof(id), 0x10000001, &id);
+	CHECK_ERR(err);
+
+	/* reset manufacturer's ID read-mode */
+	err = m9mo_mem_write(sd, 0x06, sizeof(reset), 0x10000000, reset);
+	CHECK_ERR(err);
+
+	cam_dbg("%#x\n", id);
+
+	return id;
+}
+
+static int m9mo_program_fw(struct v4l2_subdev *sd,
+	u8 *buf, u32 addr, u32 unit, u32 count)
+{
+	u32 val;
+	int i, err = 0;
+	int erase = 0x01;
+	int test_count = 0;
+	int retries = 0;
+
+	for (i = 0; i < unit*count; i += unit) {
+		/* Set Flash ROM memory address */
+		err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+			M9MO_FLASH_ADDR, addr + i);
+		CHECK_ERR(err);
+
+		/* Erase FLASH ROM entire memory */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+			M9MO_FLASH_ERASE, erase);
+		CHECK_ERR(err);
+		/* Response while sector-erase is operating */
+		retries = 0;
+		do {
+			mdelay(30);
+			err = m9mo_readb(sd, M9MO_CATEGORY_FLASH,
+				M9MO_FLASH_ERASE, &val);
+			CHECK_ERR(err);
+		} while (val == erase && retries++ < M9MO_I2C_VERIFY);
+
+		if (val != 0) {
+			cam_err("failed to erase sector\n");
+			return -1;
+		}
+
+		/* Set FLASH ROM programming size */
+		err = m9mo_writew(sd, M9MO_CATEGORY_FLASH,
+				M9MO_FLASH_BYTE, unit);
+		CHECK_ERR(err);
+
+		err = m9mo_mem_write(sd, 0x04, unit,
+				M9MO_INT_RAM_BASE_ADDR, buf + i);
+			CHECK_ERR(err);
+		cam_err("fw Send = %x count = %d\n", i, test_count++);
+
+	/* Start Programming */
+		err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH, M9MO_FLASH_WR, 0x01);
+		CHECK_ERR(err);
+
+		/* Confirm programming has been completed */
+		retries = 0;
+		do {
+			mdelay(30);
+			err = m9mo_readb(sd, M9MO_CATEGORY_FLASH,
+				M9MO_FLASH_WR, &val);
+			CHECK_ERR(err);
+		} while (val && retries++ < M9MO_I2C_VERIFY);
+
+		if (val != 0) {
+			cam_err("failed to program~~~~\n");
+			return -1;
+		}
+	}
+	cam_err("m9mo_program_fw out ~~~~~~~~~~~\n");
+	return 0;
+}
+
+static int m9mo_load_fw_main(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct device *dev = sd->v4l2_dev->dev;
+	const struct firmware *fw = NULL;
+	u8 *buf_m9mo = NULL;
+	/*int offset;*/
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M9MO_FW_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n",
+			M9MO_FW_PATH, PTR_ERR(fp));
+		goto request_fw;
+	}
+
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+
+	cam_err("start, file path %s, size %ld Bytes\n", M9MO_FW_PATH, fsize);
+
+	buf_m9mo = vmalloc(fsize);
+	if (!buf_m9mo) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf_m9mo, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+	filp_close(fp, current->files);
+
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+
+		cam_info("Firmware Path = %s\n", M9MO_FW_REQ_PATH);
+		err = request_firmware(&fw, M9MO_FW_REQ_PATH, dev);
+
+		if (err != 0) {
+			cam_err("request_firmware failed\n");
+			err = -EINVAL;
+			goto out;
+		}
+		cam_dbg("start, size %d Bytes\n", fw->size);
+		buf_m9mo = (u8 *)fw->data;
+	}
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+			0x90001200 , buf_port_seting0);
+	CHECK_ERR(err);
+	mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+			0x90001000 , buf_port_seting1);
+	CHECK_ERR(err);
+	mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+			0x90001100 , buf_port_seting2);
+	CHECK_ERR(err);
+	mdelay(10);
+
+	err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+			0x1C, 0x0247036D);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+			0x4A, 0x01);
+	CHECK_ERR(err);
+	mdelay(10);
+
+	/* program FLASH ROM */
+	err = m9mo_program_fw(sd, buf_m9mo, M9MO_FLASH_BASE_ADDR, SZ_4K, 512);
+	if (err < 0)
+		goto out;
+
+
+#if 0
+	offset = SZ_64K * 31;
+	if (id == 0x01) {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_8K, 4, id);
+	} else {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_4K, 8, id);
+	}
+#endif
+	cam_err("end\n");
+	state->isp.bad_fw = 0;
+
+out:
+	if (!fw_requested) {
+		vfree(buf_m9mo);
+
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	return err;
+}
+
+static int m9mo_load_fw_info(struct v4l2_subdev *sd)
+{
+	const struct firmware *fw = NULL;
+	u8 *buf_m9mo = NULL;
+	/*int offset;*/
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(FW_INFO_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n",
+			M9MO_FW_PATH, PTR_ERR(fp));
+	}
+	fsize = fp->f_path.dentry->d_inode->i_size;
+
+	cam_err("start, file path %s, size %ld Bytes\n", FW_INFO_PATH, fsize);
+
+	buf_m9mo = vmalloc(fsize);
+	if (!buf_m9mo) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf_m9mo, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001200 , buf_port_seting0);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001000 , buf_port_seting1);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001100 , buf_port_seting2);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+				0x1C, 0x0247036D);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+				0x4A, 0x01);
+	CHECK_ERR(err);
+			mdelay(10);
+
+	/* program FLSH ROM */
+	err = m9mo_program_fw(sd, buf_m9mo, M9MO_FLASH_BASE_ADDR_1, SZ_4K, 1);
+	if (err < 0)
+		goto out;
+
+
+#if 0
+	offset = SZ_64K * 31;
+	if (id == 0x01) {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_8K, 4, id);
+	} else {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_4K, 8, id);
+	}
+#endif
+	cam_err("end\n");
+
+out:
+	if (!fw_requested) {
+		vfree(buf_m9mo);
+
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	return err;
+}
+
+
+
+static int m9mo_load_fw(struct v4l2_subdev *sd)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	const struct firmware *fw = NULL;
+	u8 sensor_ver[M9MO_FW_VER_LEN] = {0, };
+	u8 *buf_m9mo = NULL, *buf_fw_info = NULL;
+	/*int offset;*/
+	int err = 0;
+
+	struct file *fp;
+	mm_segment_t old_fs;
+	long fsize, nread;
+	int fw_requested = 1;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(M9MO_FW_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("failed to open %s, err %ld\n",
+			M9MO_FW_PATH, PTR_ERR(fp));
+		goto request_fw;
+	}
+
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+
+	cam_err("start, file path %s, size %ld Bytes\n", M9MO_FW_PATH, fsize);
+
+	buf_m9mo = vmalloc(fsize);
+	if (!buf_m9mo) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf_m9mo, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+	filp_close(fp, current->files);
+
+	fp = filp_open(FW_INFO_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_trace("failed to open %s, err %ld\n",
+			FW_INFO_PATH, PTR_ERR(fp));
+		goto request_fw;
+	}
+
+	fw_requested = 0;
+	fsize = fp->f_path.dentry->d_inode->i_size;
+
+	cam_err("start, file path %s, size %ld Bytes\n", FW_INFO_PATH, fsize);
+
+	buf_fw_info = vmalloc(fsize);
+	if (!buf_fw_info) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf_fw_info, fsize, &fp->f_pos);
+	if (nread != fsize) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+
+
+request_fw:
+	if (fw_requested) {
+		set_fs(old_fs);
+
+	m9mo_get_sensor_fw_version(sd, sensor_ver);
+
+	if (sensor_ver[0] == 'T' && sensor_ver[1] == 'B') {
+		err = request_firmware(&fw, M9MOTB_FW_PATH, dev);
+#if defined(CONFIG_MACH_Q1_BD)
+	} else if (sensor_ver[0] == 'O' && sensor_ver[1] == 'O') {
+		err = request_firmware(&fw, M9MOOO_FW_PATH, dev);
+#endif
+#if defined(CONFIG_MACH_U1_KOR_LGT)
+	} else if (sensor_ver[0] == 'S' && sensor_ver[1] == 'B') {
+		err = request_firmware(&fw, M9MOSB_FW_PATH, dev);
+#endif
+	} else {
+		cam_err("cannot find the matched F/W file\n");
+		err = -EINVAL;
+	}
+
+	if (err != 0) {
+		cam_err("request_firmware falied\n");
+			err = -EINVAL;
+			goto out;
+	}
+		cam_dbg("start, size %d Bytes\n", fw->size);
+		buf_m9mo = (u8 *)fw->data;
+	}
+
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001200 , buf_port_seting0);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001000 , buf_port_seting1);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_mem_write(sd, 0x04, SZ_64,
+				0x90001100 , buf_port_seting2);
+			CHECK_ERR(err);
+			mdelay(10);
+
+	err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+				0x1C, 0x0247036D);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+				0x4A, 0x01);
+	CHECK_ERR(err);
+			mdelay(10);
+
+	/* program FLSH ROM */
+	err = m9mo_program_fw(sd, buf_m9mo, M9MO_FLASH_BASE_ADDR, SZ_4K, 504);
+	if (err < 0)
+		goto out;
+
+	err = m9mo_program_fw(sd, buf_fw_info,
+			M9MO_FLASH_BASE_ADDR_1, SZ_4K, 1);
+	if (err < 0)
+		goto out;
+
+#if 0
+	offset = SZ_64K * 31;
+	if (id == 0x01) {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_8K, 4, id);
+	} else {
+		err = m9mo_program_fw(sd, buf + offset,
+				M9MO_FLASH_BASE_ADDR + offset, SZ_4K, 8, id);
+	}
+#endif
+	cam_err("end\n");
+
+out:
+	if (!fw_requested) {
+		vfree(buf_m9mo);
+		vfree(buf_fw_info);
+
+		filp_close(fp, current->files);
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	return err;
+}
+
+
+static int m9mo_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err = 0;
+
+	cam_trace(" id %d, value %d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if (unlikely(state->isp.bad_fw && ctrl->id != V4L2_CID_CAM_UPDATE_FW)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_UPDATE_FW:
+		if (ctrl->value == FW_MODE_DUMP)
+			err = m9mo_dump_fw(sd);
+		else
+			err = m9mo_check_fw(sd);
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+#ifdef FAST_CAPTURE
+		err = m9mo_set_fast_capture(sd);
+#else
+		err = m9mo_set_sensor_mode(sd, ctrl->value);
+#endif
+		break;
+
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		err = m9mo_set_flash(sd, ctrl->value, 0);
+		break;
+
+	case V4L2_CID_CAMERA_ISO:
+		err = m9mo_set_iso(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_METERING:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			err = m9mo_set_metering(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = m9mo_set_exposure(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		err = m9mo_set_whitebalance(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = m9mo_set_scene_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_EFFECT:
+		err = m9mo_set_effect(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_WDR:
+		err = m9mo_set_wdr(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_SHAKE:
+		err = m9mo_set_antishake(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BEAUTY_SHOT:
+		err = m9mo_set_face_beauty(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		err = m9mo_set_af_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		err = m9mo_set_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		state->focus.pos_x = ctrl->value;
+		/* FIXME - It should be fixed on F/W (touch AF offset) */
+		if (state->preview != NULL) {
+			if (state->exif.unique_id[0] == 'T') {
+				if (state->preview->index == M9MO_PREVIEW_VGA)
+					state->focus.pos_x -= 40;
+				else if (state->preview->index ==
+						M9MO_PREVIEW_WVGA)
+					state->focus.pos_x -= 50;
+			}
+		}
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		state->focus.pos_y = ctrl->value;
+		/* FIXME - It should be fixed on F/W (touch AF offset) */
+		if (state->preview != NULL) {
+			if (state->preview->index == M9MO_PREVIEW_VGA) {
+				if (state->exif.unique_id[0] == 'T')
+					state->focus.pos_y -= 50;
+			} else if (state->preview->index == M9MO_PREVIEW_WVGA) {
+				if (state->exif.unique_id[0] == 'T')
+					state->focus.pos_y -= 2;
+				else
+					state->focus.pos_y += 60;
+			}
+		}
+		break;
+
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		err = m9mo_set_touch_auto_focus(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ZOOM:
+		err = m9mo_set_zoom(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_OPTICAL_ZOOM_STEP:
+		err = m9mo_set_optical_zoom_step(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_OPTICAL_ZOOM_CTRL:
+		err = m9mo_set_optical_zoom_ctrl(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_JPEG_QUALITY:
+		err = m9mo_set_jpeg_quality(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CAPTURE:
+		err = m9mo_start_capture(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_YUV_CAPTURE:
+		err = m9mo_start_YUV_capture(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_POSTVIEW_CAPTURE:
+		err = m9mo_start_postview_capture(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CAPTURE_MODE:
+		err = m9mo_set_capture_mode(sd, ctrl->value);
+		break;
+
+	/*case V4L2_CID_CAMERA_HDR:
+		err = m9mo_set_hdr(sd, ctrl->value);
+		break;*/
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		err = m9mo_set_antibanding(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = m9mo_check_esd(sd);
+		break;
+
+	case V4L2_CID_CAMERA_AEAWB_LOCK_UNLOCK:
+		err = m9mo_set_aeawblock(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FACE_DETECTION:
+		err = m9mo_set_facedetect(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRACKET:
+		err = m9mo_set_bracket(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRACKET_AEB:
+		err = m9mo_set_bracket_aeb(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRACKET_WBB:
+		err = m9mo_set_bracket_wbb(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FRAME_RATE:
+		err = m9mo_set_fps(sd, ctrl->value);
+		state->fps = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_LDC:
+		err = m9mo_set_LDC(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_LSC:
+		err = m9mo_set_LSC(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_APERTURE:
+		err = m9mo_set_aperture(sd, ctrl->value);
+		break;
+
+	default:
+		cam_err("no such control id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+		/*err = -ENOIOCTLCMD;*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+	return err;
+}
+
+
+/*
+ * v4l2_subdev_video_ops
+ */
+static const struct m9mo_frmsizeenum *m9mo_get_frmsize
+	(const struct m9mo_frmsizeenum *frmsizes, int num_entries, int index)
+{
+	int i;
+
+	for (i = 0; i < num_entries; i++) {
+		if (frmsizes[i].index == index)
+			return &frmsizes[i];
+	}
+
+	return NULL;
+}
+
+static int m9mo_set_frmsize(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	struct v4l2_control ctrl;
+	int err;
+	cam_trace("E\n");
+
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		err = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+		CHECK_ERR(err);
+
+		err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+			M9MO_PARM_MON_SIZE, state->preview->reg_val);
+		CHECK_ERR(err);
+
+		if (state->zoom) {
+			/* Zoom position returns to 1
+			   when the monitor size is changed. */
+			ctrl.id = V4L2_CID_CAMERA_ZOOM;
+			ctrl.value = state->zoom;
+			m9mo_set_zoom(sd, &ctrl);
+		}
+
+		cam_err("preview frame size %dx%d\n",
+			state->preview->width, state->preview->height);
+	} else {
+		if (state->pixelformat == V4L2_COLORSPACE_JPEG) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+					M9MO_CAPPARM_MAIN_IMG_SIZE,
+					state->capture->reg_val);
+			CHECK_ERR(err);
+			cam_info("capture frame size %dx%d\n",
+			state->capture->width, state->capture->height);
+		} else {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+					M9MO_CAPPARM_PREVIEW_IMG_SIZE,
+					state->capture->reg_val);
+			CHECK_ERR(err);
+			cam_info("capture frame size %dx%d\n",
+					state->capture->width,
+					state->capture->height);
+		}
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *ffmt)
+{
+	struct m9mo_state *state = to_state(sd);
+	const struct m9mo_frmsizeenum **frmsize;
+
+	u32 width = ffmt->width;
+	u32 height = ffmt->height;
+	u32 old_index;
+	int i, num_entries;
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	state->format_mode = ffmt->field;
+	state->pixelformat = ffmt->colorspace;
+
+	frmsize = state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW ?
+		&state->preview : &state->capture;
+
+	old_index = *frmsize ? (*frmsize)->index : -1;
+	*frmsize = NULL;
+
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		num_entries = ARRAY_SIZE(preview_frmsizes);
+		for (i = 0; i < num_entries; i++) {
+			if (width == preview_frmsizes[i].width &&
+				height == preview_frmsizes[i].height) {
+				*frmsize = &preview_frmsizes[i];
+				break;
+			}
+		}
+	} else {
+		num_entries = ARRAY_SIZE(capture_frmsizes);
+		for (i = 0; i < num_entries; i++) {
+			if (width == capture_frmsizes[i].width &&
+				height == capture_frmsizes[i].height) {
+				*frmsize = &capture_frmsizes[i];
+				break;
+			}
+		}
+	}
+
+	if (*frmsize == NULL) {
+		cam_warn("invalid frame size %dx%d\n", width, height);
+		*frmsize = state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW ?
+			m9mo_get_frmsize(preview_frmsizes, num_entries,
+				M9MO_PREVIEW_VGA) :
+
+			m9mo_get_frmsize(capture_frmsizes, num_entries,
+				M9MO_CAPTURE_3MP);
+	}
+
+	cam_err("%dx%d\n", (*frmsize)->width, (*frmsize)->height);
+	m9mo_set_frmsize(sd);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct m9mo_state *state = to_state(sd);
+
+	a->parm.capture.timeperframe.numerator = 1;
+	a->parm.capture.timeperframe.denominator = state->fps;
+
+	return 0;
+}
+
+static int m9mo_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct m9mo_state *state = to_state(sd);
+	/*int err;*/
+
+	u32 fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	if (fps != state->fps) {
+		if (fps <= 0 || fps > 30) {
+			cam_err("invalid frame rate %d\n", fps);
+			fps = 30;
+		}
+		state->fps = fps;
+	}
+
+#if 0
+	err = m9mo_set_mode(sd, M9MO_PARMSET_MODE);
+	CHECK_ERR(err);
+#endif
+
+	cam_dbg("fixed fps %d\n", state->fps);
+#if 0
+	err = m9mo_writeb(sd, M9MO_CATEGORY_PARM,
+		M9MO_PARM_FLEX_FPS, state->fps != 30 ? state->fps : 0);
+	CHECK_ERR(err);
+#endif
+
+	return 0;
+}
+
+static int m9mo_enum_framesizes(struct v4l2_subdev *sd,
+	struct v4l2_frmsizeenum *fsize)
+{
+	struct m9mo_state *state = to_state(sd);
+
+	/*
+	* The camera interface should read this value, this is the resolution
+	* at which the sensor would provide framedata to the camera i/f
+	* In case of image capture,
+	* this returns the default camera resolution (VGA)
+	*/
+	if (state->format_mode == V4L2_PIX_FMT_MODE_PREVIEW) {
+		if (state->preview == NULL
+				/* FIXME || state->preview->index < 0 */)
+			return -EINVAL;
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->preview->width;
+		fsize->discrete.height = state->preview->height;
+	} else {
+		if (state->capture == NULL
+				/* FIXME || state->capture->index < 0 */)
+			return -EINVAL;
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->capture->width;
+		fsize->discrete.height = state->capture->height;
+	}
+
+	return 0;
+}
+
+static int m9mo_s_stream_preview(struct v4l2_subdev *sd, int enable)
+{
+	struct m9mo_state *state = to_state(sd);
+	u32 old_mode, int_factor, value;
+	int err;
+
+	if (enable) {
+		if (state->vt_mode) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_EP_MODE_MON, 0x11);
+			CHECK_ERR(err);
+		}
+
+		if (state->preview->width == 720 &&
+				state->preview->height == 480) {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_EP_MODE_MON, 0x1C);
+			CHECK_ERR(err);
+			err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_EP_MODE_CAP, 0x1C);
+			CHECK_ERR(err);
+		} else {
+			err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_EP_MODE_MON, 0x00);
+			CHECK_ERR(err);
+			err = m9mo_writeb(sd, M9MO_CATEGORY_AE,
+					M9MO_AE_EP_MODE_CAP, 0x00);
+			CHECK_ERR(err);
+		}
+
+		old_mode = m9mo_set_mode(sd, M9MO_MONITOR_MODE);
+		if (old_mode <= 0) {
+			cam_err("failed to set mode\n");
+			return old_mode;
+		}
+
+		if (old_mode != M9MO_MONITOR_MODE) {
+			int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+			if (!(int_factor & M9MO_INT_MODE)) {
+				cam_err("M9MO_INT_MODE isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+		}
+		err = m9mo_writeb(sd, M9MO_CATEGORY_TEST,
+			0x34, 0x00);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_TEST,
+			0x35, 0x02);
+		err = m9mo_writeb(sd, M9MO_CATEGORY_TEST,
+			0x33, 0x01);
+		msleep(20);
+		err = m9mo_readb(sd, M9MO_CATEGORY_TEST,
+			0x36, &value);
+		cam_err("******** sensor version = %x *********\n", value);
+
+		m9mo_set_lock(sd, 0);
+
+#if 0
+		cam_err("******** LENS ON *********\n");
+		err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			0x04, 0x0a);
+#endif
+
+#if 0
+		if (state->check_dataline) {
+			err = m9mo_check_dataline(sd, state->check_dataline);
+			CHECK_ERR(err);
+		}
+#endif
+	} else {
+	}
+
+	return 0;
+}
+
+static int m9mo_s_stream_capture(struct v4l2_subdev *sd, int enable)
+{
+	/*u32 int_factor;*/
+	int err;
+
+#ifndef FAST_CAPTURE
+	if (enable) {
+		err = m9mo_set_mode(sd, M9MO_STILLCAP_MODE);
+		if (err <= 0) {
+			cam_err("failed to set mode\n");
+			return err;
+		}
+/*
+		int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+		if (!(int_factor & M9MO_INT_SOUND)) {
+			cam_err("M9MO_INT_SOUND isn't issued, %#x\n",
+				int_factor);
+			return -ETIMEDOUT;
+		}
+*/
+	}
+#endif
+	return 0;
+}
+
+static int m9mo_s_stream_hdr(struct v4l2_subdev *sd, int enable)
+{
+	struct m9mo_state *state = to_state(sd);
+	int int_en, int_factor, i, err;
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+		M9MO_CAPCTRL_CAP_MODE, enable ? 0x06 : 0x00);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_YUVOUT_MAIN, enable ? 0x00 : 0x21);
+		CHECK_ERR(err);
+
+	err = m9mo_readw(sd, M9MO_CATEGORY_SYS, M9MO_SYS_INT_EN, &int_en);
+		CHECK_ERR(err);
+
+	if (enable)
+		int_en |= M9MO_INT_FRAME_SYNC;
+	else
+		int_en &= ~M9MO_INT_FRAME_SYNC;
+
+	err = m9mo_writew(sd, M9MO_CATEGORY_SYS, M9MO_SYS_INT_EN, int_en);
+		CHECK_ERR(err);
+
+	if (enable) {
+		err = m9mo_set_mode(sd, M9MO_STILLCAP_MODE);
+		if (err <= 0) {
+			cam_err("failed to set mode\n");
+			return err;
+		}
+
+		/* convert raw to jpeg by the image data processing and
+		   store memory on ISP and
+		   receive preview jpeg image from ISP */
+		for (i = 0; i < 3; i++) {
+			int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+			if (!(int_factor & M9MO_INT_FRAME_SYNC)) {
+				cam_err("M9MO_INT_FRAME_SYNC isn't issued, %#x\n",
+					int_factor);
+				return -ETIMEDOUT;
+			}
+		}
+
+		/* stop ring-buffer */
+		if (!(state->isp.int_factor & M9MO_INT_CAPTURE)) {
+			/* FIXME - M9MO_INT_FRAME_SYNC interrupt
+			   should be issued just three times */
+			for (i = 0; i < 9; i++) {
+				int_factor = m9mo_wait_interrupt(sd,
+						M9MO_ISP_TIMEOUT);
+				if (int_factor & M9MO_INT_CAPTURE)
+					break;
+
+				cam_err("M9MO_INT_CAPTURE isn't issued, %#x\n",
+						int_factor);
+			}
+		}
+	} else {
+	}
+	return 0;
+}
+
+static int m9mo_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct m9mo_state *state = to_state(sd);
+	int err;
+
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (enable) {
+	case STREAM_MODE_CAM_ON:
+	case STREAM_MODE_CAM_OFF:
+		switch (state->format_mode) {
+		case V4L2_PIX_FMT_MODE_CAPTURE:
+			cam_info("capture %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+			err = m9mo_s_stream_capture(sd,
+					enable == STREAM_MODE_CAM_ON);
+			break;
+		case V4L2_PIX_FMT_MODE_HDR:
+			err = m9mo_s_stream_hdr(sd,
+					enable == STREAM_MODE_CAM_ON);
+			break;
+		default:
+			cam_err("preview %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+			err = m9mo_s_stream_preview(sd,
+					enable == STREAM_MODE_CAM_ON);
+			break;
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		state->recording = 1;
+		if (state->flash_mode != FLASH_MODE_OFF)
+			err = m9mo_set_flash(sd, state->flash_mode, 1);
+
+		if (state->preview->index == M9MO_PREVIEW_720P ||
+				state->preview->index == M9MO_PREVIEW_1080P)
+			err = m9mo_set_af(sd, 1);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		if (state->preview->index == M9MO_PREVIEW_720P ||
+				state->preview->index == M9MO_PREVIEW_1080P)
+			err = m9mo_set_af(sd, 0);
+
+		m9mo_set_flash(sd, FLASH_MODE_OFF, 1);
+
+		state->recording = 0;
+		break;
+
+	default:
+		cam_err("invalid stream option, %d\n", enable);
+		break;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_check_version(struct v4l2_subdev *sd)
+{
+	struct m9mo_state *state = to_state(sd);
+	int i, val;
+
+	for (i = 0; i < 6; i++) {
+		m9mo_readb(sd, M9MO_CATEGORY_SYS, M9MO_SYS_USER_VER, &val);
+		state->exif.unique_id[i] = (char)val;
+	}
+	state->exif.unique_id[i] = '\0';
+
+	cam_info("*************************************\n");
+	cam_info("F/W Version: %s\n", state->exif.unique_id);
+	cam_dbg("Binary Released: %s %s\n", __DATE__, __TIME__);
+	cam_info("*************************************\n");
+
+	return 0;
+}
+
+static int m9mo_init_param(struct v4l2_subdev *sd)
+{
+	int err;
+	cam_trace("E\n");
+
+	err = m9mo_writew(sd, M9MO_CATEGORY_SYS, M9MO_SYS_INT_EN,
+			M9MO_INT_MODE | M9MO_INT_CAPTURE | M9MO_INT_FRAME_SYNC
+			/* | M9MO_INT_SOUND*/);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_PARM, M9MO_PARM_OUT_SEL, 0x02);
+	CHECK_ERR(err);
+
+	/* Capture */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPPARM,
+			M9MO_CAPPARM_YUVOUT_MAIN, 0x01);
+	CHECK_ERR(err);
+
+#if 0
+	err = m9mo_writel(sd, M9MO_CATEGORY_CAPPARM,
+		M9MO_CAPPARM_THUMB_JPEG_MAX, M9MO_THUMB_MAXSIZE);
+	CHECK_ERR(err);
+
+	/* Face detect */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_SIZE, 0x01);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FD, M9MO_FD_MAX, 0x0B);
+	CHECK_ERR(err);
+
+	/* HDR */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_CAPCTRL,
+			M9MO_CAPCTRL_CAP_FRM_COUNT, 0x03);
+	CHECK_ERR(err);
+
+	err = m9mo_writeb(sd, M9MO_CATEGORY_AE, M9MO_AE_AUTO_BRACKET_EV, 0x64);
+	CHECK_ERR(err);
+#endif
+	cam_trace("X\n");
+	return 0;
+}
+
+static int m9mo_ois_init(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	const struct m9mo_platform_data *pdata = client->dev.platform_data;
+	struct m9mo_state *state = to_state(sd);
+	u32 int_factor, int_en, err, ois_result;
+
+	err = m9mo_readw(sd, M9MO_CATEGORY_SYS, M9MO_SYS_INT_EN, &int_en);
+	CHECK_ERR(err);
+
+	/* enable OIS_INIT interrupt */
+	int_en |= M9MO_INT_OIS_INIT;
+	/* enable LENS_INIT interrupt */
+	int_en |= M9MO_INT_LENS_INIT;
+
+	err = m9mo_writew(sd, M9MO_CATEGORY_SYS, M9MO_SYS_INT_EN, int_en);
+	CHECK_ERR(err);
+
+	/* SambaZ PLL enable */
+	pdata->config_sambaz(1);
+
+	/* OIS on set */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_NEW,
+			0x10, 0x01);
+	CHECK_ERR(err);
+
+	/* OIS F/W download, boot */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_NEW,
+			0x11, 0x00);
+
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_OIS_INIT)) {
+		cam_err("OIS interrupt not issued\n");
+		state->isp.bad_fw = 1;
+		return -ENOSYS;
+	}
+	cam_info("OIS init complete\n");
+
+	/* Read OIS result */
+	m9mo_readb(sd, M9MO_CATEGORY_NEW, 0x17, &ois_result);
+	cam_info("ois result = %d", ois_result);
+
+	/* Lens boot */
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+			0x00, 0x00);
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_LENS_INIT)) {
+		cam_err("M9MO_INT_LENS_INIT isn't issued, %#x\n",
+				int_factor);
+		return -ETIMEDOUT;
+	}
+
+	return err;
+}
+
+static int m9mo_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct m9mo_state *state = to_state(sd);
+	u32 int_factor;
+	/*u32 value;*/
+	int err;
+	int fw_ver;
+
+	/* Default state values */
+	state->preview = NULL;
+	state->capture = NULL;
+
+	state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	state->sensor_mode = SENSOR_CAMERA;
+	state->flash_mode = FLASH_MODE_OFF;
+	state->scene_mode = SCENE_MODE_NONE;
+
+	state->face_beauty = 0;
+
+	state->fps = 0;			/* auto */
+
+	state->isp.bad_fw = 0;
+	state->isp.issued = 0;
+
+	memset(&state->focus, 0, sizeof(state->focus));
+
+	/* Test force update FW */
+#if 0
+	err = m9mo_load_fw_main(sd);
+	msleep(1000);
+#endif
+	if (system_rev > 0) {
+		err = m9mo_writel(sd, M9MO_CATEGORY_FLASH,
+				0x0C, 0x27c00020);
+	}
+
+	/* start camera program(parallel FLASH ROM) */
+	cam_info("write 0x0f, 0x12~~~\n");
+	err = m9mo_writeb(sd, M9MO_CATEGORY_FLASH,
+			M9MO_FLASH_CAM_START, 0x01);
+	CHECK_ERR(err);
+
+	int_factor = m9mo_wait_interrupt(sd, M9MO_ISP_TIMEOUT);
+	if (!(int_factor & M9MO_INT_MODE)) {
+		cam_err("firmware was erased?\n");
+		state->isp.bad_fw = 1;
+		return -ENOSYS;
+	}
+	cam_info("ISP boot complete\n");
+
+#if 0
+	cam_err("read 0x00, 0x1c~~~\n");
+
+	m9mo_readb(sd, M9MO_CATEGORY_SYS,
+		M9MO_SYS_INT_FACTOR, &state->isp.int_factor);
+	cam_err("state->isp.int_factor = %x\n", state->isp.int_factor);
+
+	m9mo_readb(sd, 0x01,
+		0x01, &value);
+	cam_err("value = %x\n", value);
+#endif
+
+	/* check up F/W version */
+#if 0
+	err = m9mo_check_version(sd);
+	CHECK_ERR(err);
+#else
+	/* read F/W version */
+	m9mo_readw(sd, M9MO_CATEGORY_SYS,
+		M9MO_SYS_VER_FW, &fw_ver);
+	cam_info("f/w version = %x\n", fw_ver);
+#endif
+
+	m9mo_init_param(sd);
+	m9mo_ois_init(sd);
+
+	cam_info("Lens boot complete - M9MO init complete\n");
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops m9mo_core_ops = {
+	.init = m9mo_init,		/* initializing API */
+	.load_fw = m9mo_load_fw_main,
+	.queryctrl = m9mo_queryctrl,
+	.g_ctrl = m9mo_g_ctrl,
+	.s_ctrl = m9mo_s_ctrl,
+	.g_ext_ctrls = m9mo_g_ext_ctrls,
+};
+
+static const struct v4l2_subdev_video_ops m9mo_video_ops = {
+	.s_mbus_fmt = m9mo_s_fmt,
+	.g_parm = m9mo_g_parm,
+	.s_parm = m9mo_s_parm,
+	.enum_framesizes = m9mo_enum_framesizes,
+	.s_stream = m9mo_s_stream,
+};
+
+static const struct v4l2_subdev_ops m9mo_ops = {
+	.core = &m9mo_core_ops,
+	.video = &m9mo_video_ops,
+};
+
+static ssize_t m9mo_camera_type_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct m9mo_state *state = dev_get_drvdata(dev);
+	char type[25];
+
+	if (state->exif.unique_id[1] == 'B') {
+		strcpy(type, "SONY_IMX105PQ_M9MOLS");
+	} else if (state->exif.unique_id[1] == 'C') {
+		strcpy(type, "SLSI_S5K3H2YX_M9MOLS");
+	} else {
+		cam_warn("cannot find the matched camera type\n");
+		strcpy(type, "SONY_IMX105PQ_M9MOLS");
+	}
+
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t m9mo_camera_fw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct m9mo_state *state = dev_get_drvdata(dev);
+	return sprintf(buf, "%s\n", state->fw_version);
+}
+
+static DEVICE_ATTR(rear_camtype, S_IRUGO, m9mo_camera_type_show, NULL);
+static DEVICE_ATTR(rear_camfw, S_IRUGO, m9mo_camera_fw_show, NULL);
+
+/*
+ * m9mo_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int __devinit m9mo_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct m9mo_state *state;
+	struct v4l2_subdev *sd;
+
+	const struct m9mo_platform_data *pdata = client->dev.platform_data;
+	int err = 0;
+
+	state = kzalloc(sizeof(struct m9mo_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, M9MO_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &m9mo_ops);
+
+#ifdef CAM_DEBUG
+	state->dbg_level = CAM_TRACE | CAM_DEBUG;
+#endif
+
+	/* wait queue initialize */
+	init_waitqueue_head(&state->isp.wait);
+
+	if (pdata->config_isp_irq)
+		pdata->config_isp_irq();
+
+	err = request_irq(pdata->irq,
+		m9mo_isp_isr, IRQF_TRIGGER_RISING, "m9mo isp", sd);
+	if (err) {
+		cam_err("failed to request irq ~~~~~~~~~~~~~\n");
+		return err;
+	}
+	state->isp.irq = pdata->irq;
+	state->isp.issued = 0;
+
+	cam_dbg("%s\n", __func__);
+
+	return 0;
+}
+
+static int __devexit m9mo_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct m9mo_state *state = to_state(sd);
+	int err;
+
+	cam_err("******** LENS OFF *********\n");
+	err = m9mo_writeb(sd, M9MO_CATEGORY_LENS,
+		0x04, 0x0b);
+	CHECK_ERR(err);
+	msleep(1500);
+/*	if (m9mo_set_af_softlanding(sd) < 0)
+		cam_err("failed to set soft landing\n");*/
+
+	device_remove_file(state->m9mo_dev, &dev_attr_rear_camtype);
+	device_remove_file(state->m9mo_dev, &dev_attr_rear_camfw);
+	device_destroy(camera_class, 0);
+	state->m9mo_dev = NULL;
+
+	if (state->isp.irq > 0)
+		free_irq(state->isp.irq, sd);
+
+	v4l2_device_unregister_subdev(sd);
+
+	kfree(state->fw_version);
+	kfree(state);
+
+	return 0;
+}
+
+static const struct i2c_device_id m9mo_id[] = {
+	{ M9MO_DRIVER_NAME, 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, m9mo_id);
+
+static struct i2c_driver m9mo_i2c_driver = {
+	.driver = {
+		.name	= M9MO_DRIVER_NAME,
+	},
+	.probe		= m9mo_probe,
+	.remove		= __devexit_p(m9mo_remove),
+	.id_table	= m9mo_id,
+};
+
+static int __init m9mo_mod_init(void)
+{
+	if (!m9mo_dev) {
+		m9mo_dev =
+		device_create(camera_class, NULL, 0, NULL, "rear");
+		if (IS_ERR(m9mo_dev)) {
+			cam_err("failed to create device m9mo_dev!\n");
+			return 0;
+		}
+		if (device_create_file
+		(m9mo_dev, &dev_attr_rear_camtype) < 0) {
+			cam_err("failed to create device file, %s\n",
+			dev_attr_rear_camtype.attr.name);
+		}
+		if (device_create_file
+		(m9mo_dev, &dev_attr_rear_camfw) < 0) {
+			cam_err("failed to create device file, %s\n",
+			dev_attr_rear_camfw.attr.name);
+		}
+	}
+	return i2c_add_driver(&m9mo_i2c_driver);
+}
+
+static void __exit m9mo_mod_exit(void)
+{
+	i2c_del_driver(&m9mo_i2c_driver);
+	if (camera_class)
+		class_destroy(camera_class);
+}
+module_init(m9mo_mod_init);
+module_exit(m9mo_mod_exit);
+
+
+MODULE_AUTHOR("Goeun Lee <ge.lee@samsung.com>");
+MODULE_DESCRIPTION("driver for Fusitju M9MO LS 16MP camera");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/m9mo.h b/drivers/media/video/m9mo.h
new file mode 100644
index 0000000..0c3f24c
--- /dev/null
+++ b/drivers/media/video/m9mo.h
@@ -0,0 +1,437 @@
+/*
+ * Driver for M9MO (16MP Camera) from NEC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __M9MO_H
+#define __M9MO_H
+
+#include <linux/wakelock.h>
+
+#define CONFIG_CAM_DEBUG
+
+#define cam_warn(fmt, ...)	\
+	do { \
+		printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_err(fmt, ...)	\
+	do { \
+		printk(KERN_ERR "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_info(fmt, ...)	\
+	do { \
+		printk(KERN_INFO "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#ifdef CONFIG_CAM_DEBUG
+#define CAM_DEBUG   (1 << 0)
+#define CAM_TRACE   (1 << 1)
+#define CAM_I2C     (1 << 2)
+
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_DEBUG) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_TRACE) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_i2c_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_I2C) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+#else
+#define cam_dbg(fmt, ...)
+#define cam_trace(fmt, ...)
+#define cam_i2c_dbg(fmt, ...)
+#endif
+#define FRM_RATIO(x)    ((x)->width*10/(x)->height)
+
+u8 buf_port_seting0[] = {
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+		  0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF,
+		 };
+u8 buf_port_seting1[] = {
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+		  0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF,
+		 };
+u8 buf_port_seting2[] = {
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C,
+		  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x10,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		 };
+
+enum m9mo_prev_frmsize {
+	M9MO_PREVIEW_QCIF,
+	M9MO_PREVIEW_QCIF2,
+	M9MO_PREVIEW_QVGA,
+	M9MO_PREVIEW_VGA,
+	M9MO_PREVIEW_D1,
+	M9MO_PREVIEW_WVGA,
+	M9MO_PREVIEW_720P,
+#if defined(CONFIG_MACH_Q1_BD)
+	M9MO_PREVIEW_880_720,
+	M9MO_PREVIEW_1200_800,
+	M9MO_PREVIEW_1280_800,
+	M9MO_PREVIEW_1280_768,
+	M9MO_PREVIEW_1072_800,
+	M9MO_PREVIEW_980_800,
+#endif
+	M9MO_PREVIEW_1080P,
+	M9MO_PREVIEW_HDR,
+	M9MO_PREVIEW_720P_60FPS,
+	M9MO_PREVIEW_VGA_60FPS,
+};
+
+enum m9mo_cap_frmsize {
+	M9MO_CAPTURE_1MP,	/* 1024 x 768 */
+	M9MO_CAPTURE_2MPW,	/* 1920 x 1080 */
+	M9MO_CAPTURE_3MP,	/* 1984 x 1488 */
+	M9MO_CAPTURE_5MP,	/* 2592 x 1944 */
+	M9MO_CAPTURE_8MP,	/* 3264 x 2448 */
+	M9MO_CAPTURE_10MP,	/* 3648 x 2736 */
+	M9MO_CAPTURE_12MPW,	/* 4608 x 2768 */
+	M9MO_CAPTURE_14MP,	/* 4608 x 3072 */
+	M9MO_CAPTURE_16MP,	/* 4608 x 3456 */
+	M9MO_CAPTURE_POSTWVGA,	/* 800 x 480 */
+	M9MO_CAPTURE_POSTVGA,	/* 640 x 480 */
+	M9MO_CAPTURE_POSTWHD,	/* 1280 x 720 */
+	M9MO_CAPTURE_POSTHD,	/* 960 x 720 */
+};
+
+enum cam_frmratio {
+	CAM_FRMRATIO_QCIF   = 12,   /* 11 : 9 */
+	CAM_FRMRATIO_VGA    = 13,   /* 4 : 3 */
+	CAM_FRMRATIO_D1     = 15,   /* 3 : 2 */
+	CAM_FRMRATIO_WVGA   = 16,   /* 5 : 3 */
+	CAM_FRMRATIO_HD     = 17,   /* 16 : 9 */
+};
+
+struct m9mo_control {
+	u32 id;
+	s32 value;
+	s32 minimum;		/* Note signedness */
+	s32 maximum;
+	s32 step;
+	s32 default_value;
+};
+
+struct m9mo_frmsizeenum {
+	unsigned int index;
+	unsigned int width;
+	unsigned int height;
+	u8 reg_val;		/* a value for category parameter */
+};
+
+struct m9mo_isp {
+	wait_queue_head_t wait;
+	unsigned int irq;	/* irq issued by ISP */
+	unsigned int issued;
+	unsigned int int_factor;
+	unsigned int bad_fw:1;
+};
+
+struct m9mo_jpeg {
+	int quality;
+	unsigned int main_size;	/* Main JPEG file size */
+	unsigned int thumb_size;	/* Thumbnail file size */
+	unsigned int main_offset;
+	unsigned int thumb_offset;
+	unsigned int postview_offset;
+};
+
+struct m9mo_focus {
+	unsigned int start:1;
+	unsigned int lock:1;
+	unsigned int touch:1;
+
+	unsigned int mode;
+#if defined(CONFIG_TARGET_LOCALE_NA)
+	unsigned int ui_mode;
+	unsigned int mode_select;
+#endif
+	unsigned int status;
+
+	unsigned int pos_x;
+	unsigned int pos_y;
+};
+
+struct m9mo_exif {
+	char unique_id[7];
+	u32 exptime;		/* us */
+	u16 flash;
+	u16 iso;
+	int tv;			/* shutter speed */
+	int bv;			/* brightness */
+	int ebv;		/* exposure bias */
+};
+
+struct m9mo_state {
+	struct m9mo_platform_data *pdata;
+	struct device *m9mo_dev;
+	struct v4l2_subdev sd;
+
+	struct wake_lock wake_lock;
+
+	struct m9mo_isp isp;
+
+	const struct m9mo_frmsizeenum *preview;
+	const struct m9mo_frmsizeenum *capture;
+
+	enum v4l2_pix_format_mode format_mode;
+	enum v4l2_sensor_mode sensor_mode;
+	enum v4l2_flash_mode flash_mode;
+	enum v4l2_scene_mode scene_mode;
+	int vt_mode;
+	int zoom;
+	int optical_zoom;
+
+	int m9mo_fw_done;
+	int fw_info_done;
+
+	unsigned int fps;
+	struct m9mo_focus focus;
+
+	struct m9mo_jpeg jpeg;
+	struct m9mo_exif exif;
+
+	char *fw_version;
+
+#ifdef CONFIG_CAM_DEBUG
+	u8 dbg_level;
+#endif
+
+	int facedetect_mode;
+	int running_capture_mode;
+	int fd_eyeblink_cap;
+
+	unsigned int face_beauty:1;
+	unsigned int recording:1;
+	unsigned int check_dataline:1;
+	int anti_banding;
+	int pixelformat;
+};
+
+/* Category */
+#define M9MO_CATEGORY_SYS	0x00
+#define M9MO_CATEGORY_PARM	0x01
+#define M9MO_CATEGORY_MON	0x02
+#define M9MO_CATEGORY_AE	0x03
+#define M9MO_CATEGORY_NEW	0x04
+#define M9MO_CATEGORY_WB	0x06
+#define M9MO_CATEGORY_EXIF	0x07
+#define M9MO_CATEGORY_FD	0x09
+#define M9MO_CATEGORY_LENS	0x0A
+#define M9MO_CATEGORY_CAPPARM	0x0B
+#define M9MO_CATEGORY_CAPCTRL	0x0C
+#define M9MO_CATEGORY_TEST	0x0D
+#define M9MO_CATEGORY_ADJST	0x0E
+#define M9MO_CATEGORY_FLASH	0x0F    /* F/W update */
+
+/* M9MO_CATEGORY_SYS: 0x00 */
+#define M9MO_SYS_PJT_CODE	0x01
+#define M9MO_SYS_VER_FW		0x02
+#define M9MO_SYS_VER_HW		0x04
+#define M9MO_SYS_VER_PARAM	0x06
+#define M9MO_SYS_VER_AWB	0x08
+#define M9MO_SYS_USER_VER	0x0A
+#define M9MO_SYS_MODE		0x0B
+#define M9MO_SYS_ESD_INT	0x0E
+
+#define M9MO_SYS_INT_EN		0x10
+#define M9MO_SYS_INT_FACTOR	0x1C
+#define M9MO_SYS_FRAMESYNC_CNT	0x14
+
+
+/* M9MO_CATEGORY_PARAM: 0x01 */
+#define M9MO_PARM_OUT_SEL	0x00
+#define M9MO_PARM_MON_SIZE	0x01
+#define M9MO_PARM_EFFECT	0x0B
+#define M9MO_PARM_FLEX_FPS	0x67
+#define M9MO_PARM_HDMOVIE	0x32
+
+/* M9MO_CATEGORY_MON: 0x02 */
+#define M9MO_MON_ZOOM		0x01
+#define M9MO_MON_MON_REVERSE	0x05
+#define M9MO_MON_MON_MIRROR	0x06
+#define M9MO_MON_SHOT_REVERSE	0x07
+#define M9MO_MON_SHOT_MIRROR	0x08
+#define M9MO_MON_CFIXB		0x09
+#define M9MO_MON_CFIXR		0x0A
+#define M9MO_MON_COLOR_EFFECT	0x0B
+#define M9MO_MON_CHROMA_LVL	0x0F
+#define M9MO_MON_EDGE_LVL	0x11
+#define M9MO_MON_TONE_CTRL	0x25
+
+/* M9MO_CATEGORY_AE: 0x03 */
+#define M9MO_AE_LOCK		0x00
+#define M9MO_AE_MODE		0x01
+#define M9MO_AE_ISOSEL		0x05
+#define M9MO_AE_FLICKER		0x06
+#define M9MO_AE_INDEX		0x09
+#define M9MO_AE_EP_MODE_MON	0x0A
+#define M9MO_AE_EP_MODE_CAP	0x0B
+#define M9MO_AE_AUTO_BRACKET_EV	0x20
+#define M9MO_AE_ONESHOT_MAX_EXP	0x36
+
+/* M9MO_CATEGORY_NEW: 0x04 */
+#define M9MO_NEW_DETECT_SCENE	0x0B
+
+/* M9MO_CATEGORY_WB: 0x06 */
+#define M9MO_AWB_LOCK		0x00
+#define M9MO_WB_AWB_MODE	0x02
+#define M9MO_WB_AWB_MANUAL	0x03
+
+/* M9MO_CATEGORY_EXIF: 0x07 */
+#define M9MO_EXIF_EXPTIME_NUM	0x00
+#define M9MO_EXIF_EXPTIME_DEN	0x04
+#define M9MO_EXIF_TV_NUM	0x08
+#define M9MO_EXIF_TV_DEN	0x0C
+#define M9MO_EXIF_BV_NUM	0x18
+#define M9MO_EXIF_BV_DEN	0x1C
+#define M9MO_EXIF_EBV_NUM	0x20
+#define M9MO_EXIF_EBV_DEN	0x24
+#define M9MO_EXIF_ISO		0x28
+#define M9MO_EXIF_FLASH		0x2A
+
+/* M9MO_CATEGORY_FD: 0x09 */
+#define M9MO_FD_CTL					0x00
+#define M9MO_FD_SIZE				0x01
+#define M9MO_FD_MAX					0x02
+#define M9MO_FD_RED_EYE				0x55
+#define M9MO_FD_BLINK_FRAMENO		0x59
+#define M9MO_FD_BLINK_LEVEL_1		0x5A
+#define M9MO_FD_BLINK_LEVEL_2		0x5B
+#define M9MO_FD_BLINK_LEVEL_3		0x5C
+
+/* M9MO_CATEGORY_LENS: 0x0A */
+#define M9MO_LENS_AF_INITIAL		0x00
+#define M9MO_LENS_AF_MODE			0x01
+#define M9MO_LENS_AF_ZOOM_CTRL		0x02
+#define M9MO_LENS_AF_START_STOP		0x03
+#define M9MO_LENS_AF_STATUS			0x03
+#define M9MO_LENS_AF_IRIS_STEP		0x05
+#define M9MO_LENS_AF_ZOOM_LEVEL		0x06
+#define M9MO_LENS_AF_BACKLASH_ADJ	0x0A
+#define M9MO_LENS_AF_FOCUS_ADJ		0x0B
+#define M9MO_LENS_AF_TILT_ADJ		0x0C
+#define M9MO_LENS_AF_AF_ADJ			0x0D
+#define M9MO_LENS_AF_PUNT_ADJ		0x0E
+#define M9MO_LENS_AF_ZOOM_ADJ		0x0F
+#define M9MO_LENS_AF_ADJ_TEMP_VALUE	0x0C
+#define M9MO_LENS_AF_ALGORITHM		0x0D
+#define M9MO_LENS_AF_CAL			0x1D
+#define M9MO_LENS_AF_TOUCH_POSX		0x30
+#define M9MO_LENS_AF_TOUCH_POSY		0x32
+
+/* M9MO_CATEGORY_CAPPARM: 0x0B */
+#define M9MO_CAPPARM_YUVOUT_MAIN	0x00
+#define M9MO_CAPPARM_MAIN_IMG_SIZE	0x01
+#define M9MO_CAPPARM_YUVOUT_PREVIEW	0x05
+#define M9MO_CAPPARM_PREVIEW_IMG_SIZE	0x06
+#define M9MO_CAPPARM_YUVOUT_THUMB	0x0A
+#define M9MO_CAPPARM_THUMB_IMG_SIZE	0x0B
+#define M9MO_CAPPARM_JPEG_SIZE_MAX	0x0F
+#define M9MO_CAPPARM_JPEG_SIZE_MIN	0x13
+#define M9MO_CAPPARM_JPEG_RATIO		0x17
+#define M9MO_CAPPARM_MCC_MODE		0x1D
+#define M9MO_CAPPARM_STROBE_EN		0x22
+#define M9MO_CAPPARM_WDR_EN			0x2C
+#define M9MO_CAPPARM_JPEG_RATIO_OFS	0x34
+#define M9MO_CAPPARM_THUMB_JPEG_MAX	0x3C
+#define M9MO_CAPPARM_AFB_CAP_EN		0x53
+
+/* M9MO_CATEGORY_CAPCTRL: 0x0C */
+#define M9MO_CAPCTRL_CAP_MODE	0x00
+#define M9MO_CAPCTRL_CAP_FRM_INTERVAL 0x01
+#define M9MO_CAPCTRL_CAP_FRM_COUNT 0x02
+#define M9MO_CAPCTRL_START_DUALCAP 0x05
+#define M9MO_CAPCTRL_FRM_SEL	0x06
+#define M9MO_CAPCTRL_FRM_PRV_SEL	0x07
+#define M9MO_CAPCTRL_TRANSFER	0x09
+#define M9MO_CAPCTRL_IMG_SIZE	0x0D
+#define M9MO_CAPCTRL_THUMB_SIZE	0x11
+
+/* M9MO_CATEGORY_CAPCTRL: 0x0C  M9MO_CAPCTRL_CAP_MODE: 0x00 */
+#define M9MO_CAP_MODE_SINGLE_CAPTURE		(0x00)
+#define M9MO_CAP_MODE_MULTI_CAPTURE			(0x01)
+#define M9MO_CAP_MODE_DUAL_CAPTURE			(0x05)
+#define M9MO_CAP_MODE_BRACKET_CAPTURE		(0x06)
+#define M9MO_CAP_MODE_ADDPIXEL_CAPTURE		(0x08)
+#define M9MO_CAP_MODE_PANORAMA_CAPTURE		(0x0B)
+#define M9MO_CAP_MODE_BLINK_CAPTURE			(0x0C)
+
+/* M9MO_CATEGORY_ADJST: 0x0E */
+#define M9MO_ADJST_SHUTTER_MODE	0x33
+#define M9MO_ADJST_AWB_RG_H	0x3C
+#define M9MO_ADJST_AWB_RG_L	0x3D
+#define M9MO_ADJST_AWB_BG_H	0x3E
+#define M9MO_ADJST_AWB_BG_L	0x3F
+
+/* M9MO_CATEGORY_FLASH: 0x0F */
+#define M9MO_FLASH_ADDR		0x00
+#define M9MO_FLASH_BYTE		0x04
+#define M9MO_FLASH_ERASE	0x06
+#define M9MO_FLASH_WR		0x07
+#define M9MO_FLASH_RAM_CLEAR	0x08
+#define M9MO_FLASH_CAM_START	0x12
+#define M9MO_FLASH_SEL		0x13
+
+/* M9MO_CATEGORY_TEST:	0x0D */
+#define M9MO_TEST_OUTPUT_YCO_TEST_DATA	0x1B
+#define M9MO_TEST_ISP_PROCESS		0x59
+
+/* M9MO Sensor Mode */
+#define M9MO_SYSINIT_MODE	0x0
+#define M9MO_PARMSET_MODE	0x1
+#define M9MO_MONITOR_MODE	0x2
+#define M9MO_STILLCAP_MODE	0x3
+
+/* Interrupt Factor */
+#define M9MO_INT_SOUND		(1 << 15)
+#define M9MO_INT_LENS_INIT	(1 << 14)
+#define M9MO_INT_FD		(1 << 13)
+#define M9MO_INT_FRAME_SYNC	(1 << 12)
+#define M9MO_INT_CAPTURE	(1 << 11)
+#define M9MO_INT_ZOOM		(1 << 10)
+#define M9MO_INT_AF		(1 << 9)
+#define M9MO_INT_MODE		(1 << 8)
+#define M9MO_INT_ATSCENE	(1 << 7)
+#define M9MO_INT_ATSCENE_UPDATE	(1 << 6)
+#define M9MO_INT_OIS_INIT	(1 << 3)
+#define M9MO_INT_STNW_DETECT	(1 << 2)
+#define M9MO_INT_SCENARIO_FIN	(1 << 1)
+#define M9MO_INT_PRINT	(1 << 0)
+
+/* ESD Interrupt */
+#define M9MO_INT_ESD		(1 << 0)
+
+#endif /* __M9MO_H */
diff --git a/drivers/media/video/mhl/Kconfig b/drivers/media/video/mhl/Kconfig
new file mode 100644
index 0000000..f4ff2873
--- /dev/null
+++ b/drivers/media/video/mhl/Kconfig
@@ -0,0 +1,30 @@
+#
+# mhl drivers configuration
+#
+
+menu "Mhl(sii9244) device support"
+
+
+config SAMSUNG_MHL
+        bool "Enable Sii9244 MHL Chip Driver"
+        default n
+        ---help---
+          support Sii9244 MHL Chip Driver
+
+
+config SAMSUNG_USE_11PIN_CONNECTOR
+	bool "11pin micro-usb connector support"
+	default n
+	---help---
+	  use 11pin micro usb connector instead of 5pin
+
+config SAMSUNG_SMARTDOCK
+	bool "smartdock support"
+	default n
+
+config SAMSUNG_WORKAROUND_HPD_GLANCE
+	bool "To avoid some effect of MHL's HPD glitch"
+	depends on (SAMSUNG_MHL || MHL_SII9234) && (CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412)
+	default y
+
+endmenu
diff --git a/drivers/media/video/mhl/Makefile b/drivers/media/video/mhl/Makefile
new file mode 100644
index 0000000..5ae250d
--- /dev/null
+++ b/drivers/media/video/mhl/Makefile
@@ -0,0 +1,2 @@
+#mhl driver
+obj-y				+= sii9234.o
diff --git a/drivers/media/video/mhl/sii9234.c b/drivers/media/video/mhl/sii9234.c
new file mode 100644
index 0000000..c3fc95b
--- /dev/null
+++ b/drivers/media/video/mhl/sii9234.c
@@ -0,0 +1,4135 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Authors: Adam Hampson <ahampson@sta.samsung.com>
+ *          Erik Gilling <konkers@android.com>
+ *
+ * Additional contributions by : Shankar Bandal <shankar.b@samsung.com>
+ *                               Dharam Kumar <dharam.kr@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/sii9234.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/file.h>
+#include <linux/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/wakelock.h>
+#include <linux/earlysuspend.h>
+#ifdef CONFIG_EXTCON
+#include <linux/extcon.h>
+#endif
+
+/*////////////////////////////////////////////////////////////////////////////*/
+/*/////////////////////////	definition area		//////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+#define	__CONFIG_USE_TIMER__
+#define	__CONFIG_RSEN_LOST_PATCH__
+/* #define	__CONFIG_MHL_SWING_LEVEL__ */
+#define	__CONFIG_SS_FACTORY__
+#define	__CONFIG_MHL_DEBUG__
+/* #define	__SII9234_MUTEX_DEBUG__ */
+/*////////////////////////////////////////////////////////////////////////////*/
+/*//////////////////     dependence hader file area     //////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+#ifdef __CONFIG_MHL_SWING_LEVEL__
+#include <linux/ctype.h>
+#endif
+#include "sii9234_driver.h"
+
+/*////////////////////////////////////////////////////////////////////////////*/
+/*//////////////////////////     mecro area     //////////////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+#undef pr_debug
+#ifdef __CONFIG_MHL_DEBUG__
+int mhl_dbg_flag;
+#	define pr_debug(fmt, ...) \
+	do { \
+		if (unlikely(mhl_dbg_flag == 1)) { \
+			printk(KERN_INFO fmt, ##__VA_ARGS__); \
+		} \
+	} while (0)
+#else
+#	define pr_debug(fmt, ...)
+#endif
+
+#ifdef __SII9234_MUTEX_DEBUG__
+	int g_mutex_cnt;
+	int g_cbus_mutex_cnt;
+#	define	sii9234_mutex_lock(prm)	\
+	do { \
+		printk(KERN_INFO"%s(%d) mutex++:%d\n", __func__,\
+				__LINE__, ++g_mutex_cnt); \
+		mutex_lock(prm); \
+		printk(KERN_INFO"%s(%d) mutex--:%d\n", __func__,\
+				__LINE__, g_mutex_cnt); \
+	} while (0)
+#	define	sii9234_mutex_unlock(prm) \
+	do { \
+		printk(KERN_INFO"%s(%d) mutex_unlock:%d\n", __func__, \
+				__LINE__, --g_mutex_cnt); \
+		mutex_unlock(prm); \
+	} while (0)
+#	define	sii9234_cbus_mutex_lock(prm) \
+	do { \
+		printk(KERN_INFO"%s(%d) cbus mutex++:%d\n", __func__, \
+				__LINE__, ++g_cbus_mutex_cnt); \
+		mutex_lock(prm); \
+		printk(KERN_INFO"%s(%d) cbus mutex--:%d\n", __func__, \
+				__LINE__, g_cbus_mutex_cnt); \
+	} while (0)
+#	define	sii9234_cbus_mutex_unlock(prm)	\
+	do { \
+		printk(KERN_INFO"%s(%d) cbus mutex_unlock:%d\n", __func__, \
+				__LINE__, --g_cbus_mutex_cnt); \
+		mutex_unlock(prm); \
+	} while (0)
+#else
+#	define	sii9234_mutex_lock(prm)	mutex_lock(prm);
+#	define	sii9234_mutex_unlock(prm)	mutex_unlock(prm);
+#	define	sii9234_cbus_mutex_lock(prm)	mutex_lock(prm);
+#	define	sii9234_cbus_mutex_unlock(prm)	mutex_unlock(prm);
+#endif /*__SII9234_MUTEX_DEBUG__*/
+
+#define	__SII9234_IRQ_DEBUG__
+#ifdef __SII9234_IRQ_DEBUG__
+int en_irq;
+#	define sii9234_enable_irq() \
+	do { \
+		if (atomic_read(&sii9234->is_irq_enabled) == false) { \
+			atomic_set(&sii9234->is_irq_enabled, true); \
+			enable_irq(sii9234->pdata->mhl_tx_client->irq); \
+			printk(KERN_INFO"%s() : enable_irq(%d)\n", __func__, \
+					++en_irq); \
+		} else { \
+			printk(KERN_INFO"%s() : irq is already enabled(%d)\n" \
+					, __func__, en_irq); \
+		} \
+	} while (0)
+
+#	define sii9234_disable_irq() \
+	do { \
+		if (atomic_read(&sii9234->is_irq_enabled) == true) { \
+			atomic_set(&sii9234->is_irq_enabled, false); \
+			disable_irq_nosync(sii9234->pdata->mhl_tx_client->irq);\
+			printk(KERN_INFO"%s() : disable_irq(%d)\n", \
+					__func__, --en_irq); \
+		} else { \
+			printk(KERN_INFO"%s() : irq is already disabled(%d)\n"\
+					, __func__, en_irq); \
+		} \
+	} while (0)
+#else
+#	define sii9234_enable_irq() \
+	do { \
+		if (atomic_read(&sii9234->is_irq_enabled) == false) { \
+			atomic_set(&sii9234->is_irq_enabled, true); \
+			enable_irq(sii9234->pdata->mhl_tx_client->irq); \
+		} \
+	} while (0)
+
+#	define sii9234_disable_irq() \
+	do { \
+		if (atomic_read(&sii9234->is_irq_enabled) == true) { \
+			atomic_set(&sii9234->is_irq_enabled, false); \
+			disable_irq_nosync(sii9234->pdata->mhl_tx_client->irq);\
+		} \
+	} while (0)
+#endif /*__SII9234_IRQ_DEBUG__*/
+
+/*////////////////////////////////////////////////////////////////////////////*/
+/*////////////////////     global value area     /////////////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+LIST_HEAD(g_msc_packet_list);
+static int g_list_cnt;
+static struct workqueue_struct *sii9234_msc_wq;
+#endif
+
+static struct cbus_packet cbus_pkt_buf[CBUS_PKT_BUF_COUNT];
+#ifdef	__CONFIG_USE_TIMER__
+static int cbus_command_abort_state;
+#endif
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+static struct workqueue_struct *sii9234_tmds_offon_wq;
+#endif
+
+/*////////////////////////////////////////////////////////////////////////////*/
+/*/////////////////     function declaration  area     ///////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+static u8 sii9234_tmds_control(struct sii9234_data *sii9234, bool enable);
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+static u8 sii9234_tmds_control2(struct sii9234_data *sii9234, bool enable);
+#endif
+static bool cbus_command_request(struct sii9234_data *sii9234,
+				 enum cbus_command command, u8 offset, u8 data);
+static void cbus_command_response(struct sii9234_data *sii9234);
+static irqreturn_t sii9234_irq_thread(int irq, void *data);
+
+static void goto_d3(void);
+
+/*////////////////////////////////////////////////////////////////////////////*/
+/*////////////////     function description  area     ////////////////////////*/
+/*////////////////////////////////////////////////////////////////////////////*/
+
+#ifdef CONFIG_MACH_MIDAS
+void sii9234_wake_lock(void)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	wake_lock(&sii9234->mhl_wake_lock);
+	pr_debug("%s()\n", __func__);
+}
+EXPORT_SYMBOL(sii9234_wake_lock);
+
+void sii9234_wake_unlock(void)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	wake_unlock(&sii9234->mhl_wake_lock);
+	pr_debug("%s()\n", __func__);
+}
+EXPORT_SYMBOL(sii9234_wake_unlock);
+#endif
+
+#ifdef __CONFIG_MHL_SWING_LEVEL__
+static ssize_t sii9234_swing_test_show(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t size)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	return sprintf(buf, "mhl_show_value : 0x%x\n",
+		       sii9234->pdata->swing_level);
+
+}
+
+static ssize_t sii9234_swing_test_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+
+	char temp[4] = { 0, };
+	const char *p = buf;
+	int data, clk;
+	unsigned int value;
+
+	while (*p != '\0') {
+		if (!isspace(*p))
+			strncat(temp, p, 1);
+		p++;
+	}
+
+	if (strlen(temp) != 2)
+		return -EINVAL;
+
+	kstrtoul(temp, 10, &value);
+	data = value / 10;
+	clk = value % 10;
+	sii9234->pdata->swing_level = 0xc0;
+	sii9234->pdata->swing_level = sii9234->pdata->swing_level
+	    | (data << 3) | clk;
+	sprintf(buf, "mhl_store_value : 0x%x\n", sii9234->pdata->swing_level);
+	return size;
+}
+
+static CLASS_ATTR(swing, 0664,
+		  sii9234_swing_test_show, sii9234_swing_test_store);
+#endif
+
+#ifdef CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+#	if !defined(CONFIG_MACH_P4NOTE)
+static int is_mhl_cable_connected(void)
+{
+#	ifdef CONFIG_SAMSUNG_SMARTDOCK
+	if (max77693_muic_get_status1_adc_value() == ADC_SMARTDOCK)
+		return 1;
+	else
+#	endif
+		return max77693_muic_get_status1_adc1k_value();
+}
+#endif
+#endif
+
+u8 mhl_onoff_ex(bool onoff)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	int ret;
+
+	pr_info("sii9234: %s(%s)\n", __func__, onoff ? "on" : "off");
+
+	if (!sii9234 || !sii9234->pdata) {
+		pr_info("sii9234: mhl_onoff_ex: getting resource is failed\n");
+		return 2;
+	}
+
+	if (sii9234->pdata->power_state == onoff) {
+		pr_info("sii9234: mhl_onoff_ex: mhl already %s\n",
+			onoff ? "on" : "off");
+		return 2;
+	}
+
+	sii9234->pdata->power_state = onoff;	/*save power state */
+
+	if (sii9234->pdata->mhl_sel)
+		sii9234->pdata->mhl_sel(onoff);
+
+	if (onoff) {
+		if (sii9234->pdata->hw_onoff)
+			sii9234->pdata->hw_onoff(1);
+
+		if (sii9234->pdata->hw_reset)
+			sii9234->pdata->hw_reset();
+
+		goto_d3();
+		return 2;
+	} else {
+		sii9234_cancel_callback();
+
+		if (sii9234->pdata->hw_onoff)
+			sii9234->pdata->hw_onoff(0);
+
+#ifdef CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+		mhl_hpd_handler(false);
+#endif
+
+#ifdef CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+#if !defined(CONFIG_MACH_P4NOTE)
+		ret = is_mhl_cable_connected();
+#endif
+		if (ret == 1) {
+			pr_info("sii9234: %s() mhl still inserted, "
+				 "retry discovery\n", __func__);
+			schedule_work(&sii9234->mhl_restart_work);
+		} else if (ret == 0) {
+			pr_info("sii9234: %s() mhl cable is removed\n",
+				__func__);
+		} else {
+			pr_err
+			    ("[ERROR] %s() is_mhl_cable_connected error : %d\n",
+			     __func__, ret);
+		}
+#endif
+	}
+	return sii9234->rgnd;
+}
+EXPORT_SYMBOL(mhl_onoff_ex);
+
+static int mhl_tx_write_reg(struct sii9234_data *sii9234, unsigned int offset,
+			    u8 value)
+{
+	int ret;
+	ret = i2c_smbus_write_byte_data(sii9234->pdata->mhl_tx_client, offset,
+					value);
+	if (ret < 0)
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, value);
+	return ret;
+}
+
+static int mhl_tx_read_reg(struct sii9234_data *sii9234, unsigned int offset,
+			   u8 *value)
+{
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = i2c_smbus_write_byte(sii9234->pdata->mhl_tx_client, offset);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	ret = i2c_smbus_read_byte(sii9234->pdata->mhl_tx_client);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	*value = ret & 0x000000FF;
+
+	return 0;
+}
+
+static int mhl_tx_set_reg(struct sii9234_data *sii9234, unsigned int offset,
+			  u8 mask)
+{
+	int ret;
+	u8 value;
+
+	ret = mhl_tx_read_reg(sii9234, offset, &value);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, mask);
+		return ret;
+	}
+
+	value |= mask;
+
+	return mhl_tx_write_reg(sii9234, offset, value);
+}
+
+static int mhl_tx_clear_reg(struct sii9234_data *sii9234, unsigned int offset,
+			    u8 mask)
+{
+	int ret;
+	u8 value;
+
+	ret = mhl_tx_read_reg(sii9234, offset, &value);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, mask);
+		return ret;
+	}
+
+	value &= ~mask;
+
+	ret = mhl_tx_write_reg(sii9234, offset, value);
+	if (ret < 0)
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, mask);
+	return ret;
+}
+
+static int tpi_write_reg(struct sii9234_data *sii9234, unsigned int offset,
+			 u8 value)
+{
+	int ret = 0;
+	ret = i2c_smbus_write_byte_data(sii9234->pdata->tpi_client, offset,
+					value);
+	if (ret < 0)
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, value);
+	return ret;
+}
+
+static int tpi_read_reg(struct sii9234_data *sii9234, unsigned int offset,
+			u8 *value)
+{
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = i2c_smbus_write_byte(sii9234->pdata->tpi_client, offset);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	ret = i2c_smbus_read_byte(sii9234->pdata->tpi_client);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	*value = ret & 0x000000FF;
+
+	return 0;
+}
+
+static int hdmi_rx_read_reg(struct sii9234_data *sii9234, unsigned int offset,
+			    u8 *value)
+{
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = i2c_smbus_write_byte(sii9234->pdata->hdmi_rx_client, offset);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	ret = i2c_smbus_read_byte(sii9234->pdata->hdmi_rx_client);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	*value = ret & 0x000000FF;
+
+	return 0;
+}
+
+static int hdmi_rx_write_reg(struct sii9234_data *sii9234, unsigned int offset,
+			     u8 value)
+{
+	int ret;
+	ret = i2c_smbus_write_byte_data(sii9234->pdata->hdmi_rx_client, offset,
+					value);
+	if (ret < 0)
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, value);
+	return ret;
+}
+
+static int cbus_write_reg(struct sii9234_data *sii9234, unsigned int offset,
+			  u8 value)
+{
+	return i2c_smbus_write_byte_data(sii9234->pdata->cbus_client, offset,
+					 value);
+}
+
+static int cbus_read_reg(struct sii9234_data *sii9234, unsigned int offset,
+			 u8 *value)
+{
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = i2c_smbus_write_byte(sii9234->pdata->cbus_client, offset);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	ret = i2c_smbus_read_byte(sii9234->pdata->cbus_client);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x)\n", __func__, offset);
+		return ret;
+	}
+
+	*value = ret & 0x000000FF;
+
+	return 0;
+}
+
+static int cbus_set_reg(struct sii9234_data *sii9234, unsigned int offset,
+			u8 mask)
+{
+	int ret;
+	u8 value;
+
+	ret = cbus_read_reg(sii9234, offset, &value);
+	if (ret < 0) {
+		pr_err("[ERROR] sii9234 : %s(0x%02x, 0x%02x)\n", __func__,
+		       offset, mask);
+		return ret;
+	}
+
+	value |= mask;
+
+	return cbus_write_reg(sii9234, offset, value);
+}
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+void sii9234_tmds_offon_work(struct work_struct *work)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+
+	pr_debug("%s()\n", __func__);
+	sii9234_tmds_control2(sii9234, false);
+	sii9234_tmds_control2(sii9234, true);
+}
+#endif
+
+static int mhl_wake_toggle(struct sii9234_data *sii9234,
+			   unsigned long high_period, unsigned long low_period)
+{
+	int ret;
+
+	/* These bits are not documented. */
+	ret =
+	    mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL7_REG, (1 << 7) | (1 << 6));
+	if (ret < 0)
+		return ret;
+
+	usleep_range(high_period * USEC_PER_MSEC, high_period * USEC_PER_MSEC);
+
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL7_REG,
+			     (1 << 7) | (1 << 6));
+	if (ret < 0)
+		return ret;
+
+	usleep_range(low_period * USEC_PER_MSEC, low_period * USEC_PER_MSEC);
+
+	return 0;
+}
+
+static int mhl_send_wake_pulses(struct sii9234_data *sii9234)
+{
+	int ret;
+
+	ret = mhl_wake_toggle(sii9234, T_SRC_WAKE_PULSE_WIDTH_1,
+			      T_SRC_WAKE_PULSE_WIDTH_1);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_wake_toggle(sii9234, T_SRC_WAKE_PULSE_WIDTH_1,
+			      T_SRC_WAKE_PULSE_WIDTH_2);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_wake_toggle(sii9234, T_SRC_WAKE_PULSE_WIDTH_1,
+			      T_SRC_WAKE_PULSE_WIDTH_1);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_wake_toggle(sii9234, T_SRC_WAKE_PULSE_WIDTH_1,
+			      T_SRC_WAKE_TO_DISCOVER);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int sii9234_cbus_reset(struct sii9234_data *sii9234)
+{
+	int ret;
+	u8 idx;
+	/* Reset CBUS */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_SRST, (1 << 3));
+	if (ret < 0)
+		return ret;
+
+	msleep(T_SRC_CBUS_DEGLITCH);
+
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_SRST, (1 << 3));
+	if (ret < 0)
+		return ret;
+
+	for (idx = 0; idx < 4; idx++) {
+		/* Enable WRITE_STAT interrupt for writes to all
+		   4 MSC Status registers. */
+		ret = cbus_write_reg(sii9234, 0xE0 + idx, 0xF2);
+		if (ret < 0)
+			return ret;
+
+		/*Enable SET_INT interrupt for writes to all
+		   4 MSC Interrupt registers. */
+		ret = cbus_write_reg(sii9234, 0xF0 + idx, 0xF2);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+
+}
+
+/* require to chek mhl imformation of samsung in cbus_init_register*/
+static int sii9234_cbus_init(struct sii9234_data *sii9234)
+{
+	u8 value;
+	int ret;
+
+	ret = cbus_write_reg(sii9234, 0x07, 0xF2);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_write_reg(sii9234, 0x40, 0x03);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x42, 0x06);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x36, 0x0C);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x3D, 0xFD);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_write_reg(sii9234, 0x1C, 0x01);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x1D, 0x0F);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_write_reg(sii9234, 0x44, 0x02);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Setup our devcap */
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_DEV_STATE, 0x00);
+				/*To meet cts 6.3.10.1 spec */
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_MHL_VERSION, 0x11);
+				/*mhl version 1.1 */
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_DEV_CAT, 0x02);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_ADOPTER_ID_H, 0x01);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_ADOPTER_ID_L, 0x41);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_VID_LINK_MODE, 0x03);
+				/* YCbCr444, RGB444 */
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_AUD_LINK_MODE, 0x03);
+				/* 8ch, 2ch */
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_VIDEO_TYPE, 0);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_LOG_DEV_MAP, (1 << 7));
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_BANDWIDTH, 0x0F);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret =
+	    cbus_write_reg(sii9234, 0x80 + DEVCAP_DEV_FEATURE_FLAG,
+			   (1 << 0) | (1 << 1) | (1 << 2));
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_DEVICE_ID_H, 0x0);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_DEVICE_ID_L, 0x0);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_SCRATCHPAD_SIZE, 0x10);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_INT_STAT_SIZE, 0x33);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x80 + DEVCAP_RESERVED, 0);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_read_reg(sii9234, 0x31, &value);
+	if (ret < 0)
+		goto i2c_error_exit;
+	value |= 0x0C;
+	ret = cbus_write_reg(sii9234, 0x31, value);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, 0x30, 0x01);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_read_reg(sii9234, 0x3C, &value);
+	if (ret < 0)
+		goto i2c_error_exit;
+	value &= ~0x38;
+	value |= 0x30;
+	ret = cbus_write_reg(sii9234, 0x3C, value);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_read_reg(sii9234, 0x22, &value);
+	if (ret < 0)
+		goto i2c_error_exit;
+	value &= ~0x0F;
+	value |= 0x0D;
+	ret = cbus_write_reg(sii9234, 0x22, value);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_read_reg(sii9234, 0x2E, &value);
+	if (ret < 0)
+		goto i2c_error_exit;
+	value |= 0x15;
+	ret = cbus_write_reg(sii9234, 0x2E, value);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_write_reg(sii9234, CBUS_INTR1_ENABLE_REG, 0);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, CBUS_INTR2_ENABLE_REG, 0);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	return 0;
+ i2c_error_exit:
+	pr_err("[ERROR] %s()\n", __func__);
+	return ret;
+}
+
+static void cbus_req_abort_error(struct sii9234_data *sii9234)
+{
+	u8 abort_reason = 0;
+
+	pr_debug("sii9234: MSC Request Aborted:");
+
+	cbus_read_reg(sii9234, MSC_REQ_ABORT_REASON_REG, &abort_reason);
+
+	if (abort_reason) {
+		if (abort_reason & BIT_MSC_XFR_ABORT) {
+			cbus_read_reg(sii9234, MSC_REQ_ABORT_REASON_REG,
+				      &abort_reason);
+			pr_cont("ABORT_REASON_REG = %d\n", abort_reason);
+			cbus_write_reg(sii9234, MSC_REQ_ABORT_REASON_REG, 0xff);
+		}
+		if (abort_reason & BIT_MSC_ABORT) {
+			cbus_read_reg(sii9234, BIT_MSC_ABORT, &abort_reason);
+			pr_cont("BIT_MSC_ABORT = %d\n", abort_reason);
+			cbus_write_reg(sii9234, BIT_MSC_ABORT, 0xff);
+		}
+		if (abort_reason & ABORT_BY_PEER)
+			pr_cont(" Peer Sent an ABORT:");
+		if (abort_reason & UNDEF_CMD)
+			pr_cont(" Undefined Opcode:");
+		if (abort_reason & TIMEOUT)
+			pr_cont(" Requestor Translation layer Timeout:");
+		if (abort_reason & PROTO_ERROR)
+			pr_cont(" Protocol Error:");
+		if (abort_reason & MAX_FAIL) {
+			u8 msc_retry_thr_val = 0;
+			pr_cont(" Retry Threshold exceeded:");
+			cbus_read_reg(sii9234,
+				      MSC_RETRY_FAIL_LIM_REG,
+				      &msc_retry_thr_val);
+			pr_cont("Retry Threshold value is:%d",
+				msc_retry_thr_val);
+		}
+	}
+	pr_cont("\n");
+}
+
+static void cbus_resp_abort_error(struct sii9234_data *sii9234)
+{
+	u8 abort_reason = 0;
+
+	pr_debug("sii9234: MSC Response Aborted:");
+	cbus_read_reg(sii9234, MSC_RESP_ABORT_REASON_REG, &abort_reason);
+	cbus_write_reg(sii9234, MSC_RESP_ABORT_REASON_REG, 0xff);
+	if (abort_reason) {
+		if (abort_reason & ABORT_BY_PEER)
+			pr_cont(" Peer Sent an ABORT");
+		if (abort_reason & UNDEF_CMD)
+			pr_cont(" Undefined Opcode");
+		if (abort_reason & TIMEOUT)
+			pr_cont(" Requestor Translation layer Timeout");
+	}
+	pr_cont("\n");
+}
+
+static void force_usb_id_switch_open(struct sii9234_data *sii9234)
+{
+	/*Disable CBUS discovery */
+	mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL1_REG, (1 << 0));
+	/*Force USB ID switch to open */
+	mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+
+	mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL3_REG, 0x86);
+	/*Force upstream HPD to 0 when not in MHL mode. */
+	mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 4) | (1 << 5));
+}
+
+static void release_usb_id_switch_open(struct sii9234_data *sii9234)
+{
+	msleep(T_SRC_CBUS_FLOAT);
+	/* clear USB ID switch to open */
+	mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	/* Enable CBUS discovery */
+	mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL1_REG, (1 << 0));
+}
+
+static bool cbus_ddc_abort_error(struct sii9234_data *sii9234)
+{
+	u8 val1, val2;
+
+	/* clear the ddc abort counter */
+	cbus_write_reg(sii9234, 0x29, 0xFF);
+	cbus_read_reg(sii9234, 0x29, &val1);
+	usleep_range(3000, 4000);
+	cbus_read_reg(sii9234, 0x29, &val2);
+	if (val2 > (val1 + 50)) {
+		pr_debug("Applying DDC Abort Safety(SWA 18958)\n)");
+		mhl_tx_set_reg(sii9234, MHL_TX_SRST, (1 << 3));
+		mhl_tx_clear_reg(sii9234, MHL_TX_SRST, (1 << 3));
+		force_usb_id_switch_open(sii9234);
+		release_usb_id_switch_open(sii9234);
+		mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL1_REG, 0xD0);
+		sii9234_tmds_control(sii9234, false);
+		/* Disconnect and notify to OTG */
+		return true;
+	}
+	pr_debug("sii9234: DDC abort interrupt\n");
+
+	return false;
+}
+
+#ifdef CONFIG_SII9234_RCP
+static void rcp_uevent_report(struct sii9234_data *sii9234, u8 key)
+{
+	if (!sii9234->input_dev) {
+		pr_err("%s: sii9234->input_dev is NULL & "
+		       "skip rcp_report\n", __func__);
+		return;
+	}
+
+	pr_info("sii9234: rcp_uevent_report key: %d\n", key);
+	input_report_key(sii9234->input_dev, (unsigned int)key + 1, 1);
+	input_report_key(sii9234->input_dev, (unsigned int)key + 1, 0);
+	input_sync(sii9234->input_dev);
+}
+
+/*
+ * is_rcp_code_valid: Validdates the recevied RCP key,
+ * valid key is 1 to 1  map to fwk keylayer file sii9234_rcp.kl
+ * located at (/system/usr/keylayout/sii9234_rcp.kl).
+ *
+ * New key support needs to be update is_rcp_key_code_valid at
+ * driver side and /system/usr/keylayout/sii9234_rcp.kl at fwk side.
+ */
+
+static int is_rcp_key_code_valid(u8 key)
+{
+	switch (key + 1) {
+		/*should resemble /system/usr/keylayout/sii9234_rcp.kl */
+	case 1:		/* ENTER                WAKE_DROPPED */
+	case 2:		/* DPAD_UP              WAKE_DROPPED */
+	case 3:		/* DPAD_DOWN            WAKE_DROPPED */
+	case 4:		/* DPAD_LEFT            WAKE_DROPPED */
+	case 5:		/* DPAD_RIGHT           WAKE_DROPPED */
+	case 10:		/* MENU                 WAKE_DROPPED */
+	case 14:		/* BACK                 WAKE_DROPPED */
+	case 33:		/* 0    */
+	case 34:		/* 1    */
+	case 35:		/* 2    */
+	case 36:		/* 3    */
+	case 37:		/* 4    */
+	case 38:		/* 5    */
+	case 39:		/* 6    */
+	case 40:		/* 7    */
+	case 41:		/* 8    */
+	case 42:		/* 9    */
+	case 43:		/* ENTER */
+	case 45:		/* DEL  */
+	case 69:		/* MEDIA_PLAY_PAUSE         WAKE */
+	case 70:		/* MEDIA_STOP               WAKE */
+	case 71:		/* MEDIA_PAUSE              WAKE */
+	case 73:		/* MEDIA_REWIND             WAKE */
+	case 74:		/* MEDIA_FAST_FORWARD       WAKE */
+	case 76:		/* MEDIA_NEXT               WAKE */
+	case 77:		/* MEDIA_PREVIOUS           WAKE */
+		return 1;
+	default:
+		return 0;
+	}
+
+}
+
+static void cbus_process_rcp_key(struct sii9234_data *sii9234, u8 key)
+{
+
+	if (is_rcp_key_code_valid(key)) {
+		/* Report the key */
+		rcp_uevent_report(sii9234, key);
+		/* Send the RCP ack */
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_MSC_MSG, MSG_RCPK, key);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_MSC_MSG,
+					 MSG_RCPK, key, 0x0);
+#endif
+	} else {
+		sii9234->error_key = key;
+		/*
+		 * Send a RCPE(RCP Error Message) to Peer followed by
+		 * RCPK with old key-code so that initiator(TV) can
+		 * recognize failed key code.error code = 0x01 means
+		 * Ineffective key code was received.
+		 * See Table 21.(PRM)for details.
+		 */
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_MSC_MSG, MSG_RCPE, 0x01);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_MSC_MSG, MSG_RCPE, 0x01,
+					 0x0);
+#endif
+	}
+}
+#endif
+
+static void cbus_process_rap_key(struct sii9234_data *sii9234, u8 key)
+{
+	if (CBUS_MSC_RAP_CONTENT_ON == key)
+		sii9234_tmds_control(sii9234, true);
+	else if (CBUS_MSC_RAP_CONTENT_OFF == key)
+		sii9234_tmds_control(sii9234, false);
+
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+	cbus_command_request(sii9234, CBUS_MSC_MSG, MSG_RAPK, 0x00);
+#else
+	sii9234_enqueue_msc_work(sii9234, CBUS_MSC_MSG, MSG_RAPK, 0x00, 0x0);
+#endif
+}
+
+/*
+ * Incoming MSC_MSG : RCP/RAP/RCPK/RCPE/RAPK commands
+ *
+ * Process RCP key codes and the send supported keys to userspace.
+ * If a key is not supported then an error ack is sent to the peer.  Note
+ * that by default all key codes are supported.
+ *
+ * An alternate method might be to decide the validity of the key in the
+ * driver itself.  However, the driver does not have any criteria to which
+ * to make this decision.
+ */
+static void cbus_handle_msc_msg(struct sii9234_data *sii9234)
+{
+	u8 cmd_code, key;
+
+	sii9234_cbus_mutex_lock(&sii9234->cbus_lock);
+	if (sii9234->state != STATE_ESTABLISHED) {
+		pr_debug("sii9234: invalid MHL state\n");
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		return;
+	}
+
+	cbus_read_reg(sii9234, CBUS_MSC_MSG_CMD_IN_REG, &cmd_code);
+	cbus_read_reg(sii9234, CBUS_MSC_MSG_DATA_IN_REG, &key);
+
+	pr_info("sii9234: cmd_code:%d, key:%d\n", cmd_code, key);
+
+	switch (cmd_code) {
+	case MSG_RCP:
+		pr_debug("sii9234: RCP Arrived. KEY CODE:%d\n", key);
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		cbus_process_rcp_key(sii9234, key);
+		return;
+	case MSG_RAP:
+		pr_debug("sii9234: RAP Arrived\n");
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		cbus_process_rap_key(sii9234, key);
+		return;
+	case MSG_RCPK:
+		pr_debug("sii9234: RCPK Arrived\n");
+		break;
+	case MSG_RCPE:
+		pr_debug("sii9234: RCPE Arrived\n");
+		break;
+	case MSG_RAPK:
+		pr_debug("sii9234: RAPK Arrived\n");
+		break;
+	default:
+		pr_debug("sii9234: MAC error\n");
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_GET_MSC_ERR_CODE, 0, 0);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_GET_MSC_ERR_CODE, 0, 0,
+					 0x0);
+#endif
+		return;
+	}
+	sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+}
+
+void mhl_path_enable(struct sii9234_data *sii9234, bool path_en)
+{
+	pr_debug("sii9234: mhl_path_enable MHL_STATUS_PATH_ENABLED,"
+		 " path_en=%d !!!\n", path_en);
+
+	if (path_en)
+		sii9234->mhl_status_value.linkmode |= MHL_STATUS_PATH_ENABLED;
+	else
+		sii9234->mhl_status_value.linkmode &= ~MHL_STATUS_PATH_ENABLED;
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+	cbus_command_request(sii9234, CBUS_WRITE_STAT, CBUS_LINK_CONTROL_2_REG,
+			     sii9234->mhl_status_value.linkmode);
+#else
+	sii9234_enqueue_msc_work(sii9234, CBUS_WRITE_STAT,
+				 CBUS_LINK_CONTROL_2_REG,
+				 sii9234->mhl_status_value.linkmode, 0x0);
+#endif
+}
+
+static void cbus_handle_wrt_burst_recd(struct sii9234_data *sii9234)
+{
+	pr_debug("sii9234: CBUS WRT_BURST_RECD\n");
+}
+
+static void cbus_handle_wrt_stat_recd(struct sii9234_data *sii9234)
+{
+	u8 status_reg0, status_reg1, value;
+
+	pr_debug("sii9234: CBUS WRT_STAT_RECD\n");
+
+	/*
+	 * The two MHL status registers need to read to ensure that the MSC is
+	 * ready to receive the READ_DEVCAP command.
+	 * The READ_DEVCAP command is need to determine the dongle power state
+	 * and whether RCP, RCPE, RCPK, RAP, and RAPE are supported.
+	 *
+	 * Note that this is not documented properly in the PRM.
+	 */
+
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_0, &status_reg0);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_0, 0xFF);
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_1, &status_reg1);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_1, 0xFF);
+
+	pr_debug("sii9234: STATUS_REG0 : [%d];STATUS_REG1 : [%d]\n",
+		 status_reg0, status_reg1);
+
+	/* clear WRT_STAT_RECD intr */
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_0, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_0, value);
+
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_1, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_1, value);
+
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_2, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_2, value);
+
+	cbus_read_reg(sii9234, CBUS_MHL_STATUS_REG_3, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_STATUS_REG_3, value);
+
+	if (!(sii9234->mhl_status_value.linkmode & MHL_STATUS_PATH_ENABLED) &&
+	    (MHL_STATUS_PATH_ENABLED & status_reg1)) {
+		mhl_path_enable(sii9234, true);
+	} else if ((sii9234->mhl_status_value.linkmode
+		    & MHL_STATUS_PATH_ENABLED) &&
+		   !(MHL_STATUS_PATH_ENABLED & status_reg1)) {
+		mhl_path_enable(sii9234, false);
+	}
+
+	if (status_reg0 & MHL_STATUS_DCAP_READY) {
+		pr_debug("sii9234: DEV CAP READY\n");
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_READ_DEVCAP,
+				     DEVCAP_DEV_CAT, 0x00);
+		cbus_command_request(sii9234, CBUS_READ_DEVCAP,
+				     DEVCAP_DEV_FEATURE_FLAG, 0x00);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_READ_DEVCAP,
+					 DEVCAP_DEV_CAT, 0x00, 0x0);
+		sii9234_enqueue_msc_work(sii9234, CBUS_READ_DEVCAP,
+					 DEVCAP_DEV_FEATURE_FLAG, 0x00, 0x0);
+		sii9234_enqueue_msc_work(sii9234, CBUS_READ_DEVCAP,
+					 DEVCAP_DEVICE_ID_H, 0x0, 0x0);
+		sii9234_enqueue_msc_work(sii9234, CBUS_READ_DEVCAP,
+					 DEVCAP_DEVICE_ID_L, 0x0, 0x0);
+		sii9234_enqueue_msc_work(sii9234, CBUS_READ_DEVCAP,
+					 DEVCAP_RESERVED, 0x0, 0x0);
+#endif
+	}
+}
+
+static void cbus_handle_set_int_recd(struct sii9234_data *sii9234)
+{
+	u8 intr_reg0, intr_reg1, value;
+
+	/* read and clear interrupt */
+	cbus_read_reg(sii9234, CBUS_MHL_INTR_REG_0, &intr_reg0);
+	cbus_write_reg(sii9234, CBUS_MHL_INTR_REG_0, intr_reg0);
+
+	cbus_read_reg(sii9234, CBUS_MHL_INTR_REG_1, &intr_reg1);
+	cbus_write_reg(sii9234, CBUS_MHL_INTR_REG_1, intr_reg1);
+
+	pr_debug("sii9234: INTR_REG0 : [%d]; INTR_REG1 : [%d]\n",
+		 intr_reg0, intr_reg1);
+
+	if (intr_reg0 & MHL_INT_DCAP_CHG) {
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		pr_debug("sii9234: MHL_INT_DCAP_CHG\n");
+		cbus_command_request(sii9234, CBUS_READ_DEVCAP,
+				     DEVCAP_DEV_CAT, 0x00);
+		cbus_command_request(sii9234, CBUS_READ_DEVCAP,
+				     DEVCAP_DEV_FEATURE_FLAG, 0x00);
+#endif
+	}
+
+	if (intr_reg0 & MHL_INT_DSCR_CHG)
+		pr_debug("sii9234:  MHL_INT_DSCR_CHG\n");
+
+	if (intr_reg0 & MHL_INT_REQ_WRT) {
+		pr_debug("sii9234:  MHL_INT_REQ_WRT\n");
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_SET_INT,
+				     MHL_RCHANGE_INT, MHL_INT_GRT_WRT);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_SET_INT,
+					 MHL_RCHANGE_INT, MHL_INT_GRT_WRT, 0x0);
+#endif
+	}
+
+	if (intr_reg0 & MHL_INT_GRT_WRT)
+		pr_debug("sii9234:  MHL_INT_GRT_WRT\n");
+
+	if (intr_reg1 & MHL_INT_EDID_CHG) {
+		pr_debug("sii9234:  MHL_INT_EDID_CHG\n");
+		/* Enable Overriding HPD OUT */
+		mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 4));
+
+		/*
+		 * As per HDMI specification to indicate EDID change
+		 * in TV (or sink), we need to toggle HPD line.
+		 */
+
+		/* HPD OUT = Low */
+		mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 5));
+
+		/* A SET_HPD command shall not follow a CLR_HPD command
+		 * within less than THPD_WIDTH(50ms).
+		 */
+		msleep(T_HPD_WIDTH);
+
+		/* HPD OUT = High */
+		mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 5));
+
+		/* Disable Overriding of HPD OUT */
+		mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 4));
+	}
+
+	/* clear SET_INT_RECD interrupt */
+	cbus_read_reg(sii9234, CBUS_MHL_INTR_REG_2, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_INTR_REG_2, value);
+
+	cbus_read_reg(sii9234, CBUS_MHL_INTR_REG_3, &value);
+	cbus_write_reg(sii9234, CBUS_MHL_INTR_REG_3, value);
+}
+
+static int sii9234_power_init(struct sii9234_data *sii9234)
+{
+	int ret;
+
+	/* Force the SiI9234 into the D0 state. */
+	ret = tpi_write_reg(sii9234, TPI_DPD_REG, 0x3F);
+	if (ret < 0)
+		return ret;
+
+	/* Enable TxPLL Clock */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS_CLK_EN_REG, 0x01);
+	if (ret < 0)
+		return ret;
+
+	/* Enable Tx Clock Path & Equalizer */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS_CH_EN_REG, 0x15);
+	if (ret < 0)
+		return ret;
+
+	/* Power Up TMDS */
+	ret = mhl_tx_write_reg(sii9234, 0x08, 0x35);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int sii9234_hdmi_init(struct sii9234_data *sii9234)
+{
+	int ret = 0;
+	/* Analog PLL Control
+	 * bits 5:4 = 2b00 as per characterization team.
+	 */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* PLL Calrefsel */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_PLL_CALREFSEL_REG, 0x03);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* VCO Cal */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_PLL_VCOCAL_REG, 0x20);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Auto EQ */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_EQ_DATA0_REG, 0x8A);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Auto EQ */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_EQ_DATA1_REG, 0x6A);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Auto EQ */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_EQ_DATA2_REG, 0xAA);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Auto EQ */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_EQ_DATA3_REG, 0xCA);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Auto EQ */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_EQ_DATA4_REG, 0xEA);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Manual zone */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* PLL Mode Value */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_TMDS_CCTRL, 0x34);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = hdmi_rx_write_reg(sii9234, 0x45, 0x44);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Rx PLL BW ~ 4MHz */
+	ret = hdmi_rx_write_reg(sii9234, 0x31, 0x0A);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	/* Analog PLL Control
+	 * bits 5:4 = 2b00 as per characterization team.
+	 */
+	ret = hdmi_rx_write_reg(sii9234, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	return ret;
+
+ i2c_error_exit:
+	pr_err("[ERROR] %s()\n", __func__);
+	return ret;
+}
+
+static int sii9234_mhl_tx_ctl_int(struct sii9234_data *sii9234)
+{
+	int ret = 0;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL1_REG, 0xD0);
+	if (ret < 0)
+		goto i2c_error_exit;
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xC0);
+	if (ret < 0)
+		goto i2c_error_exit;
+#else
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xFC);
+	if (ret < 0)
+		goto i2c_error_exit;
+#endif
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL4_REG,
+			       sii9234->pdata->swing_level);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL7_REG, 0x0C);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	return ret;
+
+ i2c_error_exit:
+	pr_err("[ERROR] %s()\n", __func__);
+	return ret;
+}
+
+static void sii9234_power_down(struct sii9234_data *sii9234)
+{
+	sii9234_disable_irq();
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	if (sii9234->claimed) {
+		if (sii9234->pdata->vbus_present)
+			sii9234->pdata->vbus_present(false,
+						     sii9234->vbus_owner);
+	}
+#endif
+
+	sii9234->state = STATE_DISCONNECTED;
+	sii9234->claimed = false;
+
+	tpi_write_reg(sii9234, TPI_DPD_REG, 0);
+	/*turn on&off hpd festure for only QCT HDMI */
+}
+
+int rsen_state_timer_out(struct sii9234_data *sii9234)
+{
+	int ret = 0;
+	u8 value;
+
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_SYSSTAT_REG, &value);
+	if (ret < 0)
+		goto err_exit;
+	sii9234->rsen = value & RSEN_STATUS;
+
+	if (value & RSEN_STATUS) {
+		pr_info("sii9234: MHL cable connected.. RSEN High\n");
+	} else {
+		pr_info("sii9234: RSEN lost\n");
+		msleep(T_SRC_RXSENSE_DEGLITCH);
+		ret = mhl_tx_read_reg(sii9234, MHL_TX_SYSSTAT_REG, &value);
+		if (ret < 0)
+			goto err_exit;
+
+		pr_info("sii9234: sys_stat: %x ~\n", value);
+		if ((value & RSEN_STATUS) == 0) {
+			pr_info("sii9234: RSEN Really LOW ~\n");
+			/*To meet CTS 3.3.22.2 spec */
+			sii9234_tmds_control(sii9234, false);
+			force_usb_id_switch_open(sii9234);
+			release_usb_id_switch_open(sii9234);
+			ret = -1;
+			goto err_exit;
+		} else
+			pr_info("sii9234: RSEN recovery\n");
+
+	}
+	return ret;
+
+ err_exit:
+	/*turn off mhl and change usb_sel to usb */
+	pr_info("sii9234: %s() call mhl_onoff_ex(off)\n", __func__);
+	schedule_work(&sii9234->mhl_end_work);
+	return ret;
+}
+
+int sii9234_callback_sched;
+static void goto_d3(void)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	int ret;
+	u8 value;
+
+	pr_debug("sii9234: detection started d3\n");
+	sii9234_callback_sched = 0;
+
+	sii9234->mhl_status_value.linkmode = MHL_STATUS_CLK_MODE_NORMAL;
+	sii9234->rgnd = RGND_UNKNOWN;
+
+	sii9234->state = NO_MHL_STATUS;
+
+	sii9234->rsen = false;
+
+#if defined(CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE) &&\
+	 defined(CONFIG_HAS_EARLYSUSPEND)
+	if (!sii9234->suspend_state)
+		mhl_hpd_handler(false);
+#endif
+	memset(cbus_pkt_buf, 0x00, sizeof(cbus_pkt_buf));
+
+	ret = sii9234_power_init(sii9234);
+	if (ret < 0)
+		goto exit;
+	ret = sii9234_hdmi_init(sii9234);
+	if (ret < 0)
+		goto exit;
+	ret = sii9234_mhl_tx_ctl_int(sii9234);
+	if (ret < 0)
+		goto exit;
+
+	/* Enable HDCP Compliance safety */
+	ret = mhl_tx_write_reg(sii9234, 0x2B, 0x01);
+	if (ret < 0)
+		goto exit;
+
+	/* CBUS discovery cycle time for each drive and float = 150us */
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_DISC_CTRL1_REG, &value);
+	if (ret < 0)
+		goto exit;
+
+	value &= ~(1 << 3);
+	value |= (1 << 2);
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL1_REG, value);
+	if (ret < 0)
+		goto exit;
+
+	/* Clear bit 6 (reg_skip_rgnd) */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL2_REG,
+			(1 << 7) /* Reserved Bit */ |
+			2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS);
+	if (ret < 0)
+		goto exit;
+
+	/* Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel */
+	/* 1.8V CBUS VTH & GND threshold */
+	/*To meet CTS 3.3.7.2 spec */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL5_REG, 0x77);
+	if (ret < 0)
+		goto exit;
+
+	/* set bit 2 and 3, which is Initiator Timeout */
+	ret = cbus_read_reg(sii9234, CBUS_LINK_CONTROL_2_REG, &value);
+	if (ret < 0)
+		goto exit;
+
+	value |= 0x0C;
+
+	ret = cbus_write_reg(sii9234, CBUS_LINK_CONTROL_2_REG, value);
+	if (ret < 0)
+		goto exit;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL6_REG, 0xA0);
+	if (ret < 0)
+		goto exit;
+
+	/* RGND & single discovery attempt (RGND blocking) */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |
+			       DVRFLT_SEL | SINGLE_ATT);
+	if (ret < 0)
+		goto exit;
+
+	/* Use VBUS path of discovery state machine */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL8_REG, 0);
+	if (ret < 0)
+		goto exit;
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	if (ret < 0)
+		goto exit;
+
+	/* To allow RGND engine to operate correctly.
+	 * When moving the chip from D2 to D0 (power up, init regs)
+	 * the values should be
+	 * 94[1:0] = 01  reg_cbusmhl_pup_sel[1:0] should be set for 5k
+	 * 93[7:6] = 10  reg_cbusdisc_pup_sel[1:0] should be
+	 * set for 10k (default)
+	 * 93[5:4] = 00  reg_cbusidle_pup_sel[1:0] = open (default)
+	 */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL3_REG, 0x86);
+	if (ret < 0)
+		goto exit;
+	/* change from CC to 8C to match 5K */
+	/*To meet CTS 3.3.72 spec */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL4_REG, 0x8C);
+	if (ret < 0)
+		goto exit;
+
+	/* Configure the interrupt as active high */
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 2) | (1 << 1));
+	if (ret < 0)
+		goto exit;
+
+	msleep(25);
+
+	/* release usb_id switch */
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	if (ret < 0)
+		goto exit;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL1_REG, 0x27);
+	if (ret < 0)
+		goto exit;
+
+	ret = sii9234_cbus_reset(sii9234);
+	if (ret < 0)
+		goto exit;
+	ret = sii9234_cbus_init(sii9234);
+	if (ret < 0)
+		goto exit;
+
+	/* Enable Auto soft reset on SCDT = 0 */
+	ret = mhl_tx_write_reg(sii9234, 0x05, 0x04);
+	if (ret < 0)
+		goto exit;
+
+	/* HDMI Transcode mode enable */
+	ret = mhl_tx_write_reg(sii9234, 0x0D, 0x1C);
+	if (ret < 0)
+		goto exit;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR4_ENABLE_REG,
+			       RGND_READY_MASK | CBUS_LKOUT_MASK |
+			       MHL_DISC_FAIL_MASK | MHL_EST_MASK);
+	if (ret < 0)
+		goto exit;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR1_ENABLE_REG,
+			       (1 << 5) | (1 << 6));
+	if (ret < 0)
+		goto exit;
+
+	/* this point is very importand before megsure RGND impedance */
+	force_usb_id_switch_open(sii9234);
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL4_REG,
+			       (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4));
+	if (ret < 0)
+		goto exit;
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL5_REG,
+			     (1 << 1) | (1 << 0));
+	if (ret < 0)
+		goto exit;
+	release_usb_id_switch_open(sii9234);
+	/*end of this */
+	/* Force upstream HPD to 0 when not in MHL mode */
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 5));
+	if (ret < 0)
+		goto exit;
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 4));
+	if (ret < 0)
+		goto exit;
+
+	ret = hdmi_rx_write_reg(sii9234, 0x01, 0x03);
+	if (ret < 0)
+		goto exit;
+	ret = tpi_read_reg(sii9234, 0x3D, &value);
+	if (ret < 0)
+		goto exit;
+	value &= ~BIT0;
+	ret = tpi_write_reg(sii9234, 0x3D, value);
+	if (ret < 0)
+		goto exit;
+	pr_info("sii9234 : go_to d3 mode!!!\n");
+
+	sii9234_enable_irq();
+
+	return;
+ exit:
+	pr_err("[ERROR] %s() error terminated!\n", __func__);
+	return;
+}
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+void sii9234_process_msc_work(struct work_struct *work)
+{
+	u8 value;
+	int ret;
+	struct msc_packet *p_msc_pkt, *scratch;
+	struct sii9234_data *sii9234 = container_of(work,
+						    struct sii9234_data,
+						    msc_work);
+
+	sii9234_cbus_mutex_lock(&sii9234->cbus_lock);
+	sii9234_mutex_lock(&sii9234->lock);
+
+	pr_debug("%s() - start\n", __func__);
+
+	list_for_each_entry_safe(p_msc_pkt, scratch,
+				 &g_msc_packet_list, p_msc_packet_list) {
+
+		pr_debug("[MSC] %s() command(0x%x), offset(0x%x), "
+				"data_1(0x%x), data_2(0x%x)\n",
+				__func__, p_msc_pkt->command, p_msc_pkt->offset,
+				p_msc_pkt->data_1, p_msc_pkt->data_2);
+
+		/* msc request */
+		ret = sii9234_msc_req_locked(sii9234, p_msc_pkt);
+		if (ret < 0) {
+			pr_info("%s(): msc_req_locked error %d\n",
+				__func__, ret);
+			goto exit;
+		}
+
+		/* MSC_REQ_DONE received */
+		switch (p_msc_pkt->command) {
+		case CBUS_MSC_MSG:
+			if ((p_msc_pkt->offset == MSG_RCPE) &&
+			    (p_msc_pkt->data_2 == 0x01)) {
+				sii9234_enqueue_msc_work(sii9234, CBUS_MSC_MSG,
+							 MSG_RCPK, MSG_RCPK,
+							 0x0);
+			}
+			break;
+		case CBUS_WRITE_STAT:
+			break;
+		case CBUS_SET_INT:
+			break;
+		case CBUS_WRITE_BURST:
+			break;
+		case CBUS_READ_DEVCAP:
+			ret = cbus_read_reg(sii9234,
+					    CBUS_MSC_FIRST_DATA_IN_REG, &value);
+			if (ret < 0)
+				break;
+			switch (p_msc_pkt->offset) {
+			case DEVCAP_DEV_STATE:
+				pr_debug("sii9234: DEVCAP_DEV_STATE\n");
+				break;
+			case DEVCAP_MHL_VERSION:
+				sii9234->devcap.mhl_ver = value;
+				pr_debug("sii9234: MHL_VERSION: %X\n", value);
+				break;
+			case DEVCAP_DEV_CAT:
+				if (value & MHL_DEV_CATEGORY_POW_BIT)
+					pr_debug("sii9234: CAT=POWERED");
+				else
+					pr_debug("sii9234: CAT=UNPOWERED");
+				break;
+			case DEVCAP_ADOPTER_ID_H:
+				sii9234->devcap.adopter_id =
+				    (value & 0xFF) << 0x8;
+				pr_debug("sii9234: DEVCAP_ADOPTER_ID_H = %X\n",
+					 value);
+				break;
+			case DEVCAP_ADOPTER_ID_L:
+				sii9234->devcap.adopter_id |= value & 0xFF;
+				pr_debug("sii9234: DEVCAP_ADOPTER_ID_L = %X\n",
+					 value);
+				break;
+			case DEVCAP_VID_LINK_MODE:
+				sii9234->devcap.vid_link_mode = 0x3F & value;
+				pr_debug
+				    ("sii9234: MHL_CAP_VID_LINK_MODE = %d\n",
+				     sii9234->devcap.vid_link_mode);
+				break;
+			case DEVCAP_AUD_LINK_MODE:
+				sii9234->devcap.aud_link_mode = 0x03 & value;
+				pr_debug("sii9234: DEVCAP_AUD_LINK_MODE =%d\n",
+					 sii9234->devcap.aud_link_mode);
+				break;
+			case DEVCAP_VIDEO_TYPE:
+				sii9234->devcap.video_type = 0x8F & value;
+				pr_debug("sii9234: DEVCAP_VIDEO_TYPE =%d\n",
+					 sii9234->devcap.video_type);
+				break;
+			case DEVCAP_LOG_DEV_MAP:
+				sii9234->devcap.log_dev_map = value;
+				pr_debug("sii9234: DEVCAP_LOG_DEV_MAP =%d\n",
+					 sii9234->devcap.log_dev_map);
+				break;
+			case DEVCAP_BANDWIDTH:
+				sii9234->devcap.bandwidth = value;
+				pr_debug("sii9234: DEVCAP_BANDWIDTH =%d\n",
+					 sii9234->devcap.bandwidth);
+				break;
+			case DEVCAP_DEV_FEATURE_FLAG:
+				if ((value & MHL_FEATURE_RCP_SUPPORT) == 0)
+					pr_debug("sii9234: FEATURE_FLAG=RCP");
+
+				if ((value & MHL_FEATURE_RAP_SUPPORT) == 0)
+					pr_debug("sii9234: FEATURE_FLAG=RAP\n");
+
+				if ((value & MHL_FEATURE_SP_SUPPORT) == 0)
+					pr_debug("sii9234: FEATURE_FLAG=SP\n");
+				break;
+			case DEVCAP_DEVICE_ID_H:
+				sii9234->devcap.device_id =
+				    (value & 0xFF) << 0x8;
+				pr_info("sii9234: DEVICE_ID_H=0x%x\n", value);
+				break;
+			case DEVCAP_DEVICE_ID_L:
+				sii9234->devcap.device_id |= value & 0xFF;
+				pr_info("sii9234: DEVICE_ID_L=0x%x\n", value);
+				break;
+			case DEVCAP_SCRATCHPAD_SIZE:
+				sii9234->devcap.scratchpad_size = value;
+				pr_debug
+				    ("sii9234: DEVCAP_SCRATCHPAD_SIZE =%d\n",
+				     sii9234->devcap.scratchpad_size);
+				break;
+			case DEVCAP_INT_STAT_SIZE:
+				sii9234->devcap.int_stat_size = value;
+				pr_debug("sii9234: DEVCAP_INT_STAT_SIZE =%d\n",
+					 sii9234->devcap.int_stat_size);
+				break;
+			case DEVCAP_RESERVED:
+				sii9234->dcap_ready_status = 1;
+				sii9234->devcap.reserved_data = value;
+				pr_info("sii9234: DEVCAP_RESERVED : %d\n",
+					value);
+				wake_up(&sii9234->wq);
+				break;
+			default:
+				pr_debug("sii9234: DEVCAP DEFAULT\n");
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+
+		list_del(&p_msc_pkt->p_msc_packet_list);
+		pr_debug("[MSC] %s() free item , addr = 0x%x, cnt=%d\n",
+			 __func__, (unsigned int)p_msc_pkt, --g_list_cnt);
+		kfree(p_msc_pkt);
+	}
+ exit:
+	sii9234_mutex_unlock(&sii9234->lock);
+	sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+}
+
+static int sii9234_enqueue_msc_work(struct sii9234_data *sii9234, u8 command,
+				    u8 offset, u8 data_1, u8 data_2)
+{
+	struct msc_packet *packet_item;
+
+	packet_item = kmalloc(sizeof(struct msc_packet), GFP_KERNEL);
+	if (!packet_item) {
+		pr_err("[ERROR] %s() kmalloc error\n", __func__);
+		return -ENOMEM;
+	} else
+		pr_debug("[MSC] %s() add item, addr = 0x%x, cnt=%d\n",
+			 __func__, (unsigned int)packet_item, ++g_list_cnt);
+
+	packet_item->command = command;
+	packet_item->offset = offset;
+	packet_item->data_1 = data_1;
+	packet_item->data_2 = data_2;
+
+	pr_debug("[MSC] %s() command(0x%x), offset(0x%x), data_1(0x%x), "
+		"data_2(0x%x)\n", __func__, command, offset, data_1, data_2);
+	list_add_tail(&packet_item->p_msc_packet_list, &g_msc_packet_list);
+
+	pr_debug("[MSC] %s() msc work schedule\n", __func__);
+	queue_work(sii9234_msc_wq, &(sii9234->msc_work));
+
+	return 0;
+}
+
+/* Must call with sii9234->lock held */
+static int sii9234_msc_req_locked(struct sii9234_data *sii9234,
+				  struct msc_packet *msc_pkt)
+{
+	int ret;
+	u8 start_command;
+
+	if (sii9234->state != STATE_ESTABLISHED)
+		return -ENOENT;
+
+	init_completion(&sii9234->msc_complete);
+
+	cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG, msc_pkt->offset);
+	if (msc_pkt->command == CBUS_MSC_MSG)
+		msc_pkt->data_1 = msc_pkt->offset;
+	cbus_write_reg(sii9234, CBUS_MSC_FIRST_DATA_OUT_REG, msc_pkt->data_1);
+
+	switch (msc_pkt->command) {
+	case CBUS_SET_INT:
+	case CBUS_WRITE_STAT:
+		start_command = START_BIT_WRITE_STAT_INT;
+		break;
+	case CBUS_MSC_MSG:
+		cbus_write_reg(sii9234, CBUS_MSC_SECOND_DATA_OUT_REG,
+			       msc_pkt->data_2);
+		cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG, msc_pkt->command);
+
+		start_command = START_BIT_MSC_MSG;
+		break;
+	case CBUS_READ_DEVCAP:
+		start_command = START_BIT_READ_DEVCAP;
+		break;
+	case CBUS_WRITE_BURST:
+		start_command = START_BIT_WRITE_BURST;
+		break;
+	case CBUS_GET_STATE:
+	case CBUS_GET_VENDOR_ID:
+	case CBUS_SET_HPD:
+	case CBUS_CLR_HPD:
+	case CBUS_GET_MSC_ERR_CODE:
+	case CBUS_GET_SC3_ERR_CODE:
+	case CBUS_GET_SC1_ERR_CODE:
+	case CBUS_GET_DDC_ERR_CODE:
+		cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG, msc_pkt->command);
+		start_command = START_BIT_MSC_RESERVED;
+		break;
+	default:
+		pr_err("[ERROR] %s() invalid msc command(%d)\n",
+		       __func__, msc_pkt->command);
+		return -EINVAL;
+	}
+
+	cbus_write_reg(sii9234, CBUS_MSC_COMMAND_START_REG, start_command);
+
+	sii9234_mutex_unlock(&sii9234->lock);
+	ret = wait_for_completion_timeout(&sii9234->msc_complete,
+					  msecs_to_jiffies(300));
+	if (ret == 0)
+		printk(KERN_ERR "[ERROR] %s() MSC_REQ_DONE timeout\n",
+		       __func__);
+
+	sii9234_mutex_lock(&sii9234->lock);
+
+	return ret ? 0 : -EIO;
+}
+#endif				/* __MHL_NEW_CBUS_MSC_CMD__ end */
+
+static void sii9234_detection_callback_worker(struct work_struct *p)
+{
+	pr_debug("%s()\n", __func__);
+	sii9234_detection_callback();
+	return;
+}
+
+static void mhl_start_worker(struct work_struct *p)
+{
+	pr_debug("%s()\n", __func__);
+	mhl_onoff_ex(1);
+	return;
+}
+
+static void mhl_end_worker(struct work_struct *p)
+{
+	pr_debug("%s()\n", __func__);
+	mhl_onoff_ex(0);
+	return;
+}
+
+static void mhl_goto_d3_worker(struct work_struct *p)
+{
+	pr_debug("%s()\n", __func__);
+	goto_d3();
+	return;
+}
+
+static void mhl_cbus_write_stat_worker(struct work_struct *p)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+	cbus_command_request(sii9234, CBUS_WRITE_STAT, CBUS_LINK_CONTROL_2_REG,
+			     sii9234->mhl_status_value.linkmode);
+#else
+	sii9234_enqueue_msc_work(sii9234, CBUS_WRITE_STAT,
+				 CBUS_LINK_CONTROL_2_REG,
+				 sii9234->mhl_status_value.linkmode, 0x0);
+#endif
+	return;
+}
+
+static int sii9234_detection_callback(void)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	int ret;
+	u8 value;
+	int handled = 0;
+
+	pr_debug("%s() - start\n", __func__);
+	sii9234_callback_sched = 1;
+
+	sii9234_mutex_lock(&sii9234->lock);
+	sii9234->mhl_status_value.linkmode = MHL_STATUS_CLK_MODE_NORMAL;
+	sii9234->rgnd = RGND_UNKNOWN;
+	sii9234->state = STATE_DISCONNECTED;
+	sii9234->rsen = false;
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	sii9234->dcap_ready_status = 0;
+#endif
+	memset(cbus_pkt_buf, 0x00, sizeof(cbus_pkt_buf));
+	ret = sii9234_power_init(sii9234);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - sii9234_power_init\n", __func__);
+		goto unhandled;
+	}
+
+	ret = sii9234_cbus_reset(sii9234);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - sii9234_cbus_reset\n", __func__);
+		goto unhandled;
+	}
+
+	ret = sii9234_hdmi_init(sii9234);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - sii9234_hdmi_init\n", __func__);
+		goto unhandled;
+	}
+
+	ret = sii9234_mhl_tx_ctl_int(sii9234);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - sii9234_mhl_tx_ctl_int\n", __func__);
+		goto unhandled;
+	}
+
+	/* Enable HDCP Compliance safety */
+	ret = mhl_tx_write_reg(sii9234, 0x2B, 0x01);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - mhl_tx_write_reg 0x2B\n", __func__);
+		goto unhandled;
+	}
+
+	/* CBUS discovery cycle time for each drive and float = 150us */
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_DISC_CTRL1_REG, &value);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - MHL_TX_DISC_CTRL1_REG\n", __func__);
+		goto unhandled;
+	}
+
+	value &= ~(1 << 3);
+	value |= (1 << 2);
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL1_REG, value);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - MHL_TX_DISC_CTRL1_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* Clear bit 6 (reg_skip_rgnd) */
+	ret = mhl_tx_write_reg(sii9234,
+			MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved Bit */ |
+			2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - Clear bit 6\n", __func__);
+		goto unhandled;
+	}
+
+	/* Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel */
+	/* 1.8V CBUS VTH & GND threshold */
+	/*To meet CTS 3.3.7.2 spec */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL5_REG, 0x77);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - MHL_TX_DISC_CTRL5_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* set bit 2 and 3, which is Initiator Timeout */
+	ret = cbus_read_reg(sii9234, CBUS_LINK_CONTROL_2_REG, &value);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - read CBUS_LINK_CONTROL_2_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	value |= 0x0C;
+
+	ret = cbus_write_reg(sii9234, CBUS_LINK_CONTROL_2_REG, value);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - write CBUS_LINK_CONTROL_2_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL6_REG, 0xA0);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - write MHL_TX_MHLTX_CTL6_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	/* RGND & single discovery attempt (RGND blocking) */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |
+			       DVRFLT_SEL | SINGLE_ATT);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - write MHL_TX_DISC_CTRL6_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	/* Use VBUS path of discovery state machine */
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL8_REG, 0);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - write MHL_TX_DISC_CTRL8_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	/* 0x92[3] sets the CBUS / ID switch */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - set MHL_TX_DISC_CTRL6_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* To allow RGND engine to operate correctly.
+	 * When moving the chip from D2 to D0 (power up, init regs)
+	 * the values should be
+	 * 94[1:0] = 01  reg_cbusmhl_pup_sel[1:0] should be set for 5k
+	 * 93[7:6] = 10  reg_cbusdisc_pup_sel[1:0] should be
+	 * set for 10k (default)
+	 * 93[5:4] = 00  reg_cbusidle_pup_sel[1:0] = open (default)
+	 */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL3_REG, 0x86);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - set MHL_TX_DISC_CTRL3_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* change from CC to 8C to match 5K */
+	/*To meet CTS 3.3.72 spec */
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL4_REG, 0x8C);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - set MHL_TX_DISC_CTRL4_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* Force upstream HPD to 0 when not in MHL mode */
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 5));
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - clear MHL_TX_INT_CTRL_REG\n", __func__);
+		goto unhandled;
+	}
+	ret = mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 4));
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - set MHL_TX_INT_CTRL_REG\n", __func__);
+		goto unhandled;
+	}
+
+	/* Configure the interrupt as active high */
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 2) | (1 << 1));
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - clear MHL_TX_INT_CTRL_REG\n", __func__);
+		goto unhandled;
+	}
+
+	msleep(25);
+
+	/* release usb_id switch : HW decides the switch setting */
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	if (ret < 0) {
+		pr_err("[ERROR] %s() - clear MHL_TX_DISC_CTRL6_REG\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	ret = sii9234_cbus_init(sii9234);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL1_REG, 0x27);
+	if (ret < 0)
+		goto unhandled;
+
+	/* Enable Auto soft reset on SCDT = 0 */
+	ret = mhl_tx_write_reg(sii9234, 0x05, 0x04);
+	if (ret < 0)
+		goto unhandled;
+
+	/* HDMI Transcode mode enable */
+	ret = mhl_tx_write_reg(sii9234, 0x0D, 0x1C);
+	if (ret < 0)
+		goto unhandled;
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR4_ENABLE_REG,
+			       RGND_READY_MASK | CBUS_LKOUT_MASK |
+			       MHL_DISC_FAIL_MASK | MHL_EST_MASK | (1 << 0));
+#else
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR4_ENABLE_REG,
+			       RGND_READY_MASK | CBUS_LKOUT_MASK |
+			       MHL_DISC_FAIL_MASK | MHL_EST_MASK);
+#endif
+	if (ret < 0)
+		goto unhandled;
+
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR1_ENABLE_REG,
+			       (1 << 5) | (1 << 6));
+	if (ret < 0)
+		goto unhandled;
+
+/* this point is very importand before megsure RGND impedance*/
+	force_usb_id_switch_open(sii9234);
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL4_REG,
+			       (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4));
+	if (ret < 0)
+		goto unhandled;
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL5_REG,
+			     (1 << 1) | (1 << 0));
+	if (ret < 0)
+		goto unhandled;
+	release_usb_id_switch_open(sii9234);
+/*end of this*/
+	pr_debug("sii9234: waiting for RGND measurement\n");
+	sii9234_enable_irq();
+
+	/* SiI9244 Programmer's Reference Section 2.4.3
+	 * State : RGND Ready
+	 */
+	sii9234_mutex_unlock(&sii9234->lock);
+
+	pr_debug("sii9234: waiting for detection\n");
+	ret = wait_event_timeout(sii9234->wq,
+				 sii9234->state != STATE_DISCONNECTED,
+				 msecs_to_jiffies(T_WAIT_TIMEOUT_DISC_INT * 2));
+	sii9234_mutex_lock(&sii9234->lock);
+	if (ret == 0) {
+		pr_err("[ERROR] %s() - wait detection\n", __func__);
+		goto unhandled;
+	}
+
+	if (sii9234->state == STATE_DISCOVERY_FAILED) {
+		handled = -1;
+		pr_err("[ERROR] %s() - state == STATE_DISCOVERY_FAILED\n",
+		       __func__);
+		goto unhandled;
+	}
+
+	if (sii9234->state == NO_MHL_STATUS) {
+		handled = -1;
+		pr_err("[ERROR] %s() - state == NO_MHL_STATUS\n", __func__);
+		goto unhandled;
+	}
+
+	if (mhl_state_is_error(sii9234->state)) {
+		pr_err("[ERROR] %s() -mhl_state_is_error\n", __func__);
+		goto unhandled;
+	}
+
+	sii9234_mutex_unlock(&sii9234->lock);
+	pr_info("sii9234: Established & start to moniter RSEN\n");
+	/*CTS 3.3.14.3 Discovery;Sink Never Drives MHL+/- HIGH */
+	/*MHL SPEC 8.2.1.1.1;Transition SRC4-SRC7 */
+	if (rsen_state_timer_out(sii9234) < 0)
+		return handled;
+
+	sii9234->claimed = true;
+
+	ret = cbus_write_reg(sii9234,
+			     CBUS_INTR1_ENABLE_REG,
+			     MSC_RESP_ABORT_MASK |
+			     MSC_REQ_ABORT_MASK |
+			     MSC_REQ_DONE_MASK |
+			     MSC_MSG_RECD_MASK | CBUS_DDC_ABORT_MASK);
+	if (ret < 0)
+		goto unhandled_nolock;
+
+	ret = cbus_write_reg(sii9234,
+			     CBUS_INTR2_ENABLE_REG,
+			     WRT_STAT_RECD_MASK | SET_INT_RECD_MASK);
+	if (ret < 0)
+		goto unhandled_nolock;
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	ret = wait_event_timeout(sii9234->wq,
+				 sii9234->dcap_ready_status,
+				 msecs_to_jiffies(500));
+	if (ret == 0) {
+		sii9234->vbus_owner = 0; /*UNKNOWN*/
+		pr_debug("dcap_timeout err, dcap_staus:%d\n",
+			 sii9234->dcap_ready_status);
+	} else {
+		/*SAMSUNG DEVICE_ID 0x1134:dongle, 0x1234:dock */
+		if (sii9234->devcap.device_id == SS_MHL_DONGLE_DEV_ID ||
+		    sii9234->devcap.device_id == SS_MHL_DOCK_DEV_ID)
+			sii9234->vbus_owner = sii9234->devcap.reserved_data;
+		else
+			sii9234->vbus_owner = 0;
+	}
+	pr_debug("device_id:0x%4x, vbus_owner:%d\n",
+		 sii9234->devcap.device_id, sii9234->vbus_owner);
+	/*send some data for VBUS SRC such a TA or USB or UNKNOWN */
+	if (sii9234->pdata->vbus_present)
+		sii9234->pdata->vbus_present(true, sii9234->vbus_owner);
+#endif
+
+	return handled;
+
+ unhandled:
+	pr_info("sii9234: Detection failed");
+	if (sii9234->state == STATE_DISCONNECTED) {
+		pr_cont(" (timeout)");
+		sii9234->pdata->power_state = 0;
+	} else if (sii9234->state == STATE_DISCOVERY_FAILED)
+		pr_cont(" (discovery failed)");
+	else if (sii9234->state == NO_MHL_STATUS)
+		pr_cont(" (already went to D3)");
+	else if (sii9234->state == STATE_CBUS_LOCKOUT)
+		pr_cont(" (cbus_lockout)");
+	pr_cont("\n");
+
+	/*mhl spec: 8.3.3, if discovery failed, must retry discovering */
+	if ((sii9234->state == STATE_DISCOVERY_FAILED) &&
+	    (sii9234->rgnd == RGND_1K)) {
+		pr_cont("Discovery failed but RGND_1K impedence"
+			" restart detection_callback");
+
+		schedule_work(&sii9234->mhl_end_work);
+	}
+
+	sii9234_mutex_unlock(&sii9234->lock);
+
+	return handled;
+
+ unhandled_nolock:
+	pr_info("sii9234: Detection failed");
+	if (sii9234->state == STATE_DISCONNECTED) {
+		pr_cont(" (timeout)");
+		sii9234->pdata->power_state = 0;
+	} else if (sii9234->state == STATE_DISCOVERY_FAILED)
+		pr_cont(" (discovery failed)");
+	else if (sii9234->state == NO_MHL_STATUS)
+		pr_cont(" (already went to D3)");
+	else if (sii9234->state == STATE_CBUS_LOCKOUT)
+		pr_cont(" (cbus_lockout)");
+	pr_cont("\n");
+
+	/*mhl spec: 8.3.3, if discovery failed, must retry discovering */
+	if ((sii9234->state == STATE_DISCOVERY_FAILED) &&
+	    (sii9234->rgnd == RGND_1K)) {
+		pr_cont("Discovery failed but RGND_1K impedence"
+			" restart detection_callback");
+
+		schedule_work(&sii9234->mhl_end_work);
+	}
+
+	return handled;
+}
+
+static void sii9234_cancel_callback(void)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+
+	sii9234_mutex_lock(&sii9234->lock);
+	sii9234_power_down(sii9234);
+	sii9234_mutex_unlock(&sii9234->lock);
+}
+
+#ifdef CONFIG_SAMSUNG_MHL_9290
+static int sii9234_30pin_callback(struct notifier_block *this,
+				  unsigned long event, void *ptr)
+{
+	int ret = false;
+	struct sii9234_data *sii9234 = container_of(this, struct sii9234_data,
+						    acc_con_nb);
+
+	pr_debug("%s\n", __func__);
+	/* if connection event, start detection */
+	if (event) {
+		ret = sii9234_30pin_init_for_9290(sii9234);
+#ifdef	CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+		mhl_hpd_handler(true);
+#endif
+	} else {
+		pr_info("sii9234: power down for 9290\n");
+		sii9234->state = STATE_DISCONNECTED;
+		sii9234->pdata->hw_onoff(0);
+#ifdef	CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+		mhl_hpd_handler(false);
+#endif
+		ret = false;
+	}
+	return ret;
+}
+
+static int sii9234_cbus_init_for_9290(struct sii9234_data *sii9234)
+{
+	int ret = 0;
+
+	ret = cbus_write_reg(sii9234, 0x1F, 0x02);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x07, 0x30 | 0x06);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x40, 0x03);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x42, 0x06);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x36, 0x0C);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x3D, 0xFD);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x1C, 0x00);
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x44, 0x00);
+
+	return ret;
+}
+
+static int sii9234_30pin_reg_init_for_9290(struct sii9234_data *sii9234)
+{
+	int ret = 0;
+	u8 value;
+
+	ret = tpi_write_reg(sii9234, 0x3D, 0x3F);
+	if (ret < 0)
+		return ret;
+
+	ret = hdmi_rx_write_reg(sii9234, 0x11, 0x01);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x12, 0x15);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x08, 0x35);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x00, 0x00);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x13, 0x60);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x14, 0xF0);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x4B, 0x06);
+	if (ret < 0)
+		return ret;
+
+	/* Analog PLL Control */
+	ret = hdmi_rx_write_reg(sii9234, 0x17, 0x07);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x1A, 0x20);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x22, 0xE0);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x23, 0xC0);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x24, 0xA0);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x25, 0x80);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x26, 0x60);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x27, 0x40);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x28, 0x20);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x29, 0x00);
+	if (ret < 0)
+		return ret;
+
+	ret = hdmi_rx_write_reg(sii9234, 0x4D, 0x02);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x4C, 0xA0);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x80, 0x34);
+	if (ret < 0)
+		return ret;
+
+	ret = hdmi_rx_write_reg(sii9234, 0x31, 0x0B);
+	if (ret < 0)
+		return ret;
+	ret = hdmi_rx_write_reg(sii9234, 0x45, 0x06);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0xA0, 0xD0);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0xA1, 0xFC);
+	if (ret < 0)
+		return ret;
+#ifdef	CONFIG_MACH_P4NOTE
+	ret = mhl_tx_write_reg(sii9234, 0xA3, 0xC0);	/*output swing level*/
+	if (ret < 0)
+		return ret;
+#else
+	ret = mhl_tx_write_reg(sii9234, 0xA3, 0xEB);	/*output swing level */
+	if (ret < 0)
+		return ret;
+#endif
+	ret = mhl_tx_write_reg(sii9234, 0xA6, 0x00);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x2B, 0x01);
+	if (ret < 0)
+		return ret;
+
+	/* CBUS & Discovery */
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_DISC_CTRL1_REG, &value);
+	if (ret < 0)
+		return ret;
+	value &= ~(1 << 2);
+	value |= (1 << 3);
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL1_REG, value);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x91, 0xE5);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x94, 0x66);
+	if (ret < 0)
+		return ret;
+
+	ret = cbus_read_reg(sii9234, 0x31, &value);
+	if (ret < 0)
+		return ret;
+	value |= 0x0C;
+	if (ret < 0)
+		return ret;
+	ret = cbus_write_reg(sii9234, 0x31, value);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0xA5, 0x80);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x95, 0x31);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x96, 0x22);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_DISC_CTRL6_REG, &value);
+	if (ret < 0)
+		return ret;
+	value |= (1 << 6);
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_DISC_CTRL6_REG, value);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x92, 0x46);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x93, 0xDC);
+	if (ret < 0)
+		return ret;
+
+	ret =
+	    mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG, (1 << 2) | (1 << 1));
+	if (ret < 0)
+		return ret;
+
+	mdelay(25);
+
+	ret = mhl_tx_clear_reg(sii9234, MHL_TX_DISC_CTRL6_REG, USB_ID_OVR);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x90, 0x27);
+	if (ret < 0)
+		return ret;
+
+	ret = sii9234_cbus_init_for_9290(sii9234);
+	if (ret < 0)
+		return ret;
+
+	ret = mhl_tx_write_reg(sii9234, 0x05, 0x4);
+	if (ret < 0)
+		return ret;
+	ret = mhl_tx_write_reg(sii9234, 0x0D, 0x1C);
+
+	return ret;
+}
+
+static int sii9234_30pin_init_for_9290(struct sii9234_data *sii9234)
+{
+	u8 value;
+	int ret = 0;
+
+	sii9234_mutex_lock(&sii9234->lock);
+	sii9234->pdata->hw_onoff(1);
+	sii9234->pdata->hw_reset();
+
+	/*sii9234->state = STATE_9290_CONNECTED; */
+
+	/* init registers */
+	ret = sii9234_30pin_reg_init_for_9290(sii9234);
+	if (ret < 0)
+		goto unhandled;
+
+	/* start tpi */
+	ret = mhl_tx_write_reg(sii9234, 0xC7, 0x00);
+	if (ret < 0)
+		goto unhandled;
+
+	/* enable interrupts */
+	ret = mhl_tx_write_reg(sii9234, 0xBC, 0x01);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, 0xBD, 0x78);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, 0xBE, 0x01);
+	if (ret < 0)
+		goto unhandled;
+
+	/* mhd rx connected */
+	ret = mhl_tx_write_reg(sii9234, 0xBC, 0x01);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, 0xBD, 0xA0);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, 0xBE, 0x10);
+	if (ret < 0)
+		goto unhandled;
+	ret = cbus_write_reg(sii9234, 0x07, 0x30 | 0x0E);
+	if (ret < 0)
+		goto unhandled;
+	ret = cbus_write_reg(sii9234, 0x47, 0x03);
+	if (ret < 0)
+		goto unhandled;
+	ret = cbus_write_reg(sii9234, 0x21, 0x01);
+	if (ret < 0)
+		goto unhandled;
+
+	/* enable mhd tx */
+	ret = mhl_tx_clear_reg(sii9234, 0x1A, 1 << 4);
+	if (ret < 0)
+		goto unhandled;
+
+	/* set mhd power active mode */
+	ret = mhl_tx_clear_reg(sii9234, 0x1E, 1 << 1 | 1 << 0);
+	if (ret < 0)
+		goto unhandled;
+
+	ret = mhl_tx_write_reg(sii9234, 0xBC, 0x01);
+	if (ret < 0)
+		goto unhandled;
+	ret = mhl_tx_write_reg(sii9234, 0xBD, 0xA0);
+	if (ret < 0)
+		goto unhandled;
+
+	ret = mhl_tx_read_reg(sii9234, 0xBE, &value);
+	if (ret < 0)
+		goto unhandled;
+	if ((value & (1 << 7 | 1 << 6)) != 0x00) {
+		/* Assert Mobile HD FIFO Reset */
+		ret = mhl_tx_write_reg(sii9234, 0xBC, 0x01);
+		if (ret < 0)
+			goto unhandled;
+		ret = mhl_tx_write_reg(sii9234, 0xBD, 0x05);
+		if (ret < 0)
+			goto unhandled;
+		ret = mhl_tx_write_reg(sii9234, 0xBE, (1 << 4 | 0x04));
+		if (ret < 0)
+			goto unhandled;
+		mdelay(1);
+		/* Deassert Mobile HD FIFO Reset */
+		ret = mhl_tx_write_reg(sii9234, 0xBC, 0x01);
+		if (ret < 0)
+			goto unhandled;
+		ret = mhl_tx_write_reg(sii9234, 0xBD, 0x05);
+		if (ret < 0)
+			goto unhandled;
+		ret = mhl_tx_write_reg(sii9234, 0xBE, 0x04);
+		if (ret < 0)
+			goto unhandled;
+	}
+
+	sii9234_mutex_unlock(&sii9234->lock);
+	return true;
+
+ unhandled:
+	sii9234->pdata->hw_onoff(0);
+	sii9234->state = STATE_DISCONNECTED;
+	sii9234_mutex_unlock(&sii9234->lock);
+	return false;
+}
+#endif				/* CONFIG_SAMSUNG_MHL_9290 */
+
+static void save_cbus_pkt_to_buffer(struct sii9234_data *sii9234)
+{
+	int index;
+
+	for (index = 0; index < CBUS_PKT_BUF_COUNT; index++)
+		if (sii9234->cbus_pkt_buf[index].status == false)
+			break;
+
+	if (index == CBUS_PKT_BUF_COUNT) {
+		pr_debug("sii9234: Error save_cbus_pkt Buffer Full\n");
+		index -= 1;	/*adjust index */
+	}
+
+	pr_debug("sii9234: save_cbus_pkt_to_buffer index = %d\n", index);
+	memcpy(&sii9234->cbus_pkt_buf[index], &sii9234->cbus_pkt,
+	       sizeof(struct cbus_packet));
+	sii9234->cbus_pkt_buf[index].status = true;
+}
+
+static void cbus_command_response(struct sii9234_data *sii9234)
+{
+	u8 value, offset = 0;
+
+	sii9234_cbus_mutex_lock(&sii9234->cbus_lock);
+	pr_debug("sii9234: cbus_command_response\n");
+
+	switch (sii9234->cbus_pkt.command) {
+	case CBUS_MSC_MSG:
+		pr_debug("sii9234: cbus_command_response Received"
+			 " ACK for CBUS_MSC_MSG\n");
+#ifdef CONFIG_SII9234_RCP
+		if (sii9234->cbus_pkt.data[0] == MSG_RCPE &&
+		    sii9234->cbus_pkt.data[1] == 0x01) {
+			sii9234->cbus_pkt.command = CBUS_IDLE;
+			sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+			cbus_command_request(sii9234, CBUS_MSC_MSG, MSG_RCPK,
+					     sii9234->error_key);
+			return;
+		}
+#endif
+		break;
+	case CBUS_WRITE_STAT:
+		pr_debug("sii9234: cbus_command_response" "CBUS_WRITE_STAT\n");
+		cbus_read_reg(sii9234, CBUS_MSC_FIRST_DATA_IN_REG,
+			      &sii9234->cbus_pkt.data[0]);
+		break;
+	case CBUS_SET_INT:
+		pr_debug("sii9234: cbus_command_response CBUS_SET_INT\n");
+		if (sii9234->cbus_pkt.offset == MHL_RCHANGE_INT &&
+		    sii9234->cbus_pkt.data[0] == MHL_INT_DSCR_CHG) {
+			/*Write burst final step... Req->GRT->Write->DSCR */
+			pr_debug("sii9234: MHL_RCHANGE_INT &"
+				 "MHL_INT_DSCR_CHG\n");
+		} else if (sii9234->cbus_pkt.offset == MHL_RCHANGE_INT &&
+			   sii9234->cbus_pkt.data[0] == MHL_INT_DCAP_CHG) {
+			pr_debug("sii9234: MHL_RCHANGE_INT &"
+				 "MHL_INT_DCAP_CHG\n");
+			sii9234->cbus_pkt.command = CBUS_IDLE;
+			sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+			cbus_command_request(sii9234, CBUS_WRITE_STAT,
+					     MHL_STATUS_REG_CONNECTED_RDY,
+					     MHL_STATUS_DCAP_READY);
+			return;
+		}
+		break;
+	case CBUS_WRITE_BURST:
+		pr_debug("sii9234: cbus_command_response" "MHL_WRITE_BURST\n");
+		sii9234->cbus_pkt.command = CBUS_IDLE;
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		cbus_command_request(sii9234, CBUS_SET_INT,
+				     MHL_RCHANGE_INT, MHL_INT_DSCR_CHG);
+		return;
+	case CBUS_READ_DEVCAP:
+		pr_debug("sii9234: cbus_command_response"
+			 " CBUS_READ_DEVCAP\n");
+		cbus_read_reg(sii9234, CBUS_MSC_FIRST_DATA_IN_REG, &value);
+		switch (sii9234->cbus_pkt.offset) {
+		case DEVCAP_MHL_VERSION:
+			sii9234->devcap.mhl_ver = value;
+			pr_debug("sii9234: MHL_VERSION: %X\n", value);
+			break;
+		case DEVCAP_DEV_CAT:
+			if (value & MHL_DEV_CATEGORY_POW_BIT)
+				pr_debug("sii9234: CAT=POWERED");
+			else
+				pr_debug("sii9234: CAT=UNPOWERED");
+			break;
+		case DEVCAP_ADOPTER_ID_H:
+			sii9234->devcap.adopter_id = (value & 0xFF) << 0x8;
+			pr_debug("sii9234: DEVCAP_ADOPTER_ID_H = %X\n", value);
+			break;
+		case DEVCAP_ADOPTER_ID_L:
+			sii9234->devcap.adopter_id |= value & 0xFF;
+			pr_debug("sii9234: DEVCAP_ADOPTER_ID_L = %X\n", value);
+			break;
+		case DEVCAP_VID_LINK_MODE:
+			sii9234->devcap.vid_link_mode = 0x3F & value;
+			pr_debug("sii9234: MHL_CAP_VID_LINK_MODE = %d\n",
+				 sii9234->devcap.vid_link_mode);
+			break;
+		case DEVCAP_AUD_LINK_MODE:
+			sii9234->devcap.aud_link_mode = 0x03 & value;
+			pr_debug("sii9234: DEVCAP_AUD_LINK_MODE =%d\n",
+				 sii9234->devcap.aud_link_mode);
+			break;
+		case DEVCAP_VIDEO_TYPE:
+			sii9234->devcap.video_type = 0x8F & value;
+			pr_debug("sii9234: DEVCAP_VIDEO_TYPE =%d\n",
+				 sii9234->devcap.video_type);
+			break;
+		case DEVCAP_LOG_DEV_MAP:
+			sii9234->devcap.log_dev_map = value;
+			pr_debug("sii9234: DEVCAP_LOG_DEV_MAP =%d\n",
+				 sii9234->devcap.log_dev_map);
+			break;
+		case DEVCAP_BANDWIDTH:
+			sii9234->devcap.bandwidth = value;
+			pr_debug("sii9234: DEVCAP_BANDWIDTH =%d\n",
+				 sii9234->devcap.bandwidth);
+			break;
+		case DEVCAP_DEV_FEATURE_FLAG:
+			if ((value & MHL_FEATURE_RCP_SUPPORT) == 0)
+				pr_debug("sii9234: FEATURE_FLAG=RCP");
+
+			if ((value & MHL_FEATURE_RAP_SUPPORT) == 0)
+				pr_debug("sii9234: FEATURE_FLAG=RAP\n");
+
+			if ((value & MHL_FEATURE_SP_SUPPORT) == 0)
+				pr_debug("sii9234: FEATURE_FLAG=SP\n");
+			break;
+		case DEVCAP_DEVICE_ID_H:
+			sii9234->devcap.device_id = (value & 0xFF) << 0x8;
+			pr_info("sii9234: DEVICE_ID_H=0x%x\n", value);
+			offset = DEVCAP_DEVICE_ID_L;
+			break;
+		case DEVCAP_DEVICE_ID_L:
+			sii9234->devcap.device_id |= value & 0xFF;
+			pr_info("sii9234: DEVICE_ID_L=0x%x\n", value);
+			break;
+		case DEVCAP_SCRATCHPAD_SIZE:
+			sii9234->devcap.scratchpad_size = value;
+			pr_debug("sii9234: DEVCAP_SCRATCHPAD_SIZE =%d\n",
+				 sii9234->devcap.scratchpad_size);
+			break;
+		case DEVCAP_INT_STAT_SIZE:
+			sii9234->devcap.int_stat_size = value;
+			pr_debug("sii9234: DEVCAP_INT_STAT_SIZE =%d\n",
+				 sii9234->devcap.int_stat_size);
+			break;
+		case DEVCAP_RESERVED:
+			pr_info("sii9234: DEVCAP_RESERVED : %d\n", value);
+			break;
+		case DEVCAP_DEV_STATE:
+			pr_debug("sii9234: DEVCAP_DEV_STATE\n");
+			break;
+		default:
+			pr_debug("sii9234: DEVCAP DEFAULT\n");
+			break;
+		}
+
+		break;
+	default:
+		pr_debug("sii9234: error: cbus_command_response"
+			 "cannot handle...\n");
+	}
+
+	sii9234->cbus_pkt.command = CBUS_IDLE;
+	sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+
+	if (offset)
+		cbus_command_request(sii9234, CBUS_READ_DEVCAP, offset, 0x00);
+}
+
+#ifdef DEBUG_MHL
+static void cbus_command_response_dbg_msg(struct sii9234_data *sii9234,
+					  u8 index)
+{
+	/*Added to debugcbus_pkt_buf */
+	pr_info("sii9234: cbus_pkt_buf[index].command = %d,"
+		"sii9234->cbus_pkt.command = %d\n",
+		sii9234->cbus_pkt_buf[index].command,
+		sii9234->cbus_pkt.command);
+	pr_info("sii9234: cbus_pkt_buf[index].data[0] = %d,"
+		"sii9234->cbus_pkt.data[0] =  %d\n",
+		sii9234->cbus_pkt_buf[index].data[0],
+		sii9234->cbus_pkt.data[0]);
+
+	pr_info("sii9234: cbus_pkt_buf[index].data[1] = %d,"
+		"sii9234->cbus_pkt.data[1] = %d\n",
+		sii9234->cbus_pkt_buf[index].data[1],
+		sii9234->cbus_pkt.data[1]);
+	pr_info("sii9234: cbus_pkt_buf[index].offset = %d,"
+		"sii9234->cbus_pkt.offset = %d\n",
+		sii9234->cbus_pkt_buf[index].offset, sii9234->cbus_pkt.offset);
+}
+#endif
+
+static void cbus_command_response_all(struct sii9234_data *sii9234)
+{
+	u8 index;
+	struct cbus_packet cbus_pkt_process_buf[CBUS_PKT_BUF_COUNT];
+
+	/*take bkp of cbus_pkt_buf */
+	memcpy(cbus_pkt_process_buf, sii9234->cbus_pkt_buf,
+	       sizeof(cbus_pkt_process_buf));
+
+	/*clear cbus_pkt_buf  to hold next request */
+	memset(sii9234->cbus_pkt_buf, 0x00, sizeof(sii9234->cbus_pkt_buf));
+
+	/*process all previous requests */
+	for (index = 0; index < CBUS_PKT_BUF_COUNT; index++) {
+		if (cbus_pkt_process_buf[index].status == true) {
+			memcpy(&sii9234->cbus_pkt, &cbus_pkt_process_buf[index],
+			       sizeof(struct cbus_packet));
+			cbus_command_response(sii9234);
+#ifdef DEBUG_MHL
+			/*print cbus_cmd messg */
+			cbus_command_response_dbg_msg(sii9234, index);
+#endif
+		}
+	}
+}
+
+static bool cbus_command_request(struct sii9234_data *sii9234,
+				 enum cbus_command command, u8 offset, u8 data)
+{
+	u8 start_bit = 0;
+
+	sii9234_cbus_mutex_lock(&sii9234->cbus_lock);
+	if (sii9234->state != STATE_ESTABLISHED) {
+		pr_debug("sii9234: cbus_command_request without establish\n");
+		pr_debug("sii9234: ==> command:0x%X, offset:0x%X",
+			 command, offset);
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		return -EINVAL;
+	}
+
+	sii9234->cbus_pkt.command = command;
+	sii9234->cbus_pkt.offset = offset;
+
+	if (command == CBUS_MSC_MSG)
+		sii9234->cbus_pkt.data[0] = offset;
+	else
+		sii9234->cbus_pkt.data[0] = data;
+
+	pr_debug("sii9234: cbus_command_request Sending MSC_MSG SubCommand=%d"
+		 ",key-code=%d\n", sii9234->cbus_pkt.offset,
+		 sii9234->cbus_pkt.data[0]);
+
+	cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG, sii9234->cbus_pkt.offset);
+	cbus_write_reg(sii9234, CBUS_MSC_FIRST_DATA_OUT_REG,
+		       sii9234->cbus_pkt.data[0]);
+
+	switch (sii9234->cbus_pkt.command) {
+	case CBUS_SET_INT:
+		pr_debug("sii9234: cbus_command_request" "CBUS_SET_INT\n");
+		start_bit = START_BIT_WRITE_STAT_INT;
+		break;
+	case CBUS_WRITE_STAT:
+		pr_debug("sii9234: cbus_command_request" "CBUS_WRITE_STAT\n");
+		start_bit = START_BIT_WRITE_STAT_INT;
+		break;
+	case CBUS_MSC_MSG:
+		/*treat offset as data[0] in case of CBUS_MSC_MSG */
+		sii9234->cbus_pkt.data[0] = offset;
+		sii9234->cbus_pkt.data[1] = data;
+		pr_debug("sii9234: cbus_command_request CBUS_MSC_MSG"
+			 "SubCommand=%d,key-code=%d\n",
+			 sii9234->cbus_pkt.data[0], sii9234->cbus_pkt.data[1]);
+
+		cbus_write_reg(sii9234, CBUS_MSC_SECOND_DATA_OUT_REG,
+			       sii9234->cbus_pkt.data[1]);
+		cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG,
+			       sii9234->cbus_pkt.command);
+		start_bit = START_BIT_MSC_MSG;
+		break;
+	case CBUS_READ_DEVCAP:
+		pr_debug("sii9234: cbus_command_request CBUS_READ_DEVCAP\n");
+		start_bit = START_BIT_READ_DEVCAP;
+		break;
+	case CBUS_WRITE_BURST:
+		pr_debug("sii9234: cbus_command_request CBUS_WRITE_BURST\n");
+		start_bit = START_BIT_WRITE_BURST;
+		break;
+	case CBUS_GET_STATE:
+	case CBUS_GET_VENDOR_ID:
+	case CBUS_SET_HPD:
+	case CBUS_CLR_HPD:
+	case CBUS_GET_MSC_ERR_CODE:
+	case CBUS_GET_SC3_ERR_CODE:
+	case CBUS_GET_SC1_ERR_CODE:
+	case CBUS_GET_DDC_ERR_CODE:
+		cbus_write_reg(sii9234, CBUS_MSC_OFFSET_REG,
+			       sii9234->cbus_pkt.command);
+		start_bit = START_BIT_MSC_RESERVED;
+		break;
+	default:
+		pr_debug("sii9234: error send cbus command fail\n");
+		sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+		return false;
+	}
+
+	pr_debug("sii9234: startbit = %d\n", start_bit);
+	cbus_write_reg(sii9234, CBUS_MSC_COMMAND_START_REG, start_bit);
+	save_cbus_pkt_to_buffer(sii9234);
+	sii9234_cbus_mutex_unlock(&sii9234->cbus_lock);
+
+	return true;
+}
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+static u8 sii9234_tmds_control(struct sii9234_data *sii9234, bool enable)
+{
+	int ret;
+
+	if (sii9234->tmds_state == enable) {
+		if (enable) {
+			pr_debug("sii9234: MHL HPD High, already enabled TMDS\n");
+			ret = mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG,
+					(1 << 4) | (1 << 5));
+			if (ret < 0)
+				return ret;
+		} else {
+			pr_debug("sii9234 MHL HPD low, already disabled TMDS\n");
+			ret = mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG,
+					(1 << 4) | (1 << 5));
+			if (ret < 0)
+				return ret;
+		}
+		return ret;
+	} else {
+		sii9234->tmds_state = enable;
+	}
+
+	if (enable) {
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xFC);
+		if (ret < 0)
+			return ret;
+#endif
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234: MHL HPD High, enabled TMDS\n");
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG,
+				     (1 << 4) | (1 << 5));
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = mhl_tx_clear_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234 MHL HPD low, disabled TMDS\n");
+		ret = mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG,
+				       (1 << 4) | (1 << 5));
+		if (ret < 0)
+			return ret;
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xC0);
+		if (ret < 0)
+			return ret;
+#endif
+	}
+
+	return ret;
+}
+
+static u8 sii9234_tmds_control2(struct sii9234_data *sii9234, bool enable)
+{
+	int ret;
+
+	if (sii9234->tmds_state == enable) {
+		pr_debug("%s(): already %s TMDS!!\n", __func__,
+				enable ? "enabled" : "disabled");
+		return 0;
+	} else {
+		sii9234->tmds_state = enable;
+	}
+
+	if (enable) {
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xFC);
+		if (ret < 0)
+			return ret;
+#endif
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234: enabled TMDS\n");
+	} else {
+		ret = mhl_tx_clear_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234: disabled TMDS\n");
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xC0);
+		if (ret < 0)
+			return ret;
+#endif
+	}
+
+	return ret;
+}
+#else
+static u8 sii9234_tmds_control(struct sii9234_data *sii9234, bool enable)
+{
+	int ret;
+
+	if (enable) {
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xFC);
+		if (ret < 0)
+			return ret;
+#endif
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234: MHL HPD High, enabled TMDS\n");
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_INT_CTRL_REG,
+				     (1 << 4) | (1 << 5));
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = mhl_tx_clear_reg(sii9234, MHL_TX_TMDS_CCTRL, (1 << 4));
+		if (ret < 0)
+			return ret;
+		pr_debug("sii9234 MHL HPD low, disabled TMDS\n");
+		ret = mhl_tx_clear_reg(sii9234, MHL_TX_INT_CTRL_REG,
+				       (1 << 4) | (1 << 5));
+		if (ret < 0)
+			return ret;
+#ifdef	__CONFIG_RSEN_LOST_PATCH__
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL2_REG, 0xC0);
+		if (ret < 0)
+			return ret;
+#endif
+	}
+
+	return ret;
+}
+#endif
+
+static irqreturn_t sii9234_irq_thread(int irq, void *data)
+{
+	struct sii9234_data *sii9234 = data;
+	int ret;
+	u8 intr1, intr4, value;
+	u8 intr1_en, intr4_en;
+	u8 cbus_intr1, cbus_intr2;
+	u8 mhl_poweroff = 0;
+	void (*cbus_resp_callback) (struct sii9234_data *) = NULL;
+
+	if (!sii9234) {
+		pr_err("[ERROR] %s: sii9234 is NULL & skipp this rutine\n",
+		       __func__);
+		return IRQ_HANDLED;
+	}
+
+	msleep(30);
+
+	sii9234_mutex_lock(&sii9234->lock);
+
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_INTR1_REG, &intr1);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read MHL_TX_INTR1_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_INTR4_REG, &intr4);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read MHL_TX_INTR4_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_INTR1_ENABLE_REG, &intr1_en);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read MHL_TX_INTR1_ENABLE_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+	ret = mhl_tx_read_reg(sii9234, MHL_TX_INTR4_ENABLE_REG, &intr4_en);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read MHL_TX_INTR4_ENABLE_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+
+	ret = cbus_read_reg(sii9234, CBUS_INT_STATUS_1_REG, &cbus_intr1);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read CBUS_INT_STATUS_1_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+	ret = cbus_read_reg(sii9234, CBUS_INT_STATUS_2_REG, &cbus_intr2);
+	if (ret < 0) {
+		printk(KERN_ERR
+		       "[ERROR] %s():%d read CBUS_INT_STATUS_2_REG failed !\n",
+		       __func__, __LINE__);
+		goto i2c_error_exit;
+	}
+
+	pr_debug("sii9234: irq %02x/%02x %02x/%02x %02x/%02x\n",
+		 intr1, intr1_en, intr4, intr4_en, cbus_intr1, cbus_intr2);
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	if (intr4 & (1 << 0)) {
+		ret = mhl_tx_read_reg(sii9234, 0x81, &value);
+		if (ret < 0) {
+			pr_err("[ERROR] %s() read 0x81\n", __func__);
+			goto i2c_error_exit;
+		} else
+			pr_debug("%s() 0x81 = 0x%x\n", __func__, value);
+
+		queue_work(sii9234_tmds_offon_wq, &(sii9234->tmds_offon_work));
+	}
+#endif
+
+	if (intr4 & RGND_READY_INT) {
+		if (sii9234_callback_sched == 0) {
+			pr_debug("%s() RGND_READY_INT\n", __func__);
+
+			sii9234_disable_irq();
+
+			if (sii9234->pdata->hw_reset)
+				sii9234->pdata->hw_reset();
+
+			schedule_work(&sii9234->rgnd_work);
+			goto err_exit;
+		}
+		ret = mhl_tx_read_reg(sii9234, MHL_TX_STAT2_REG, &value);
+		if (ret < 0) {
+			dev_err(&sii9234->pdata->mhl_tx_client->dev,
+				"STAT2 reg, err %d\n", ret);
+			goto err_exit;
+		}
+
+		switch (value & RGND_INTP_MASK) {
+		case RGND_INTP_OPEN:
+			pr_debug("sii9234: RGND Open\n");
+			sii9234->rgnd = RGND_OPEN;
+			break;
+		case RGND_INTP_1K:
+			pr_debug("sii9234: RGND 1K!!\n");
+			/* After applying RGND patch, there is some issue
+			   about discovry failure
+			   This point is add to fix that problem */
+			ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL4_REG,
+					     0x8C);
+			if (ret < 0) {
+				printk(KERN_ERR "[ERROR] %s():%d write "
+					"MHL_TX_DISC_CTRL4_REG failed !\n",
+					__func__, __LINE__);
+				goto i2c_error_exit;
+			}
+			ret = mhl_tx_write_reg(sii9234,
+					       MHL_TX_DISC_CTRL5_REG, 0x77);
+			if (ret < 0) {
+				printk(KERN_ERR "[ERROR] %s():%d write"
+					" MHL_TX_DISC_CTRL5_REG failed !\n",
+					__func__, __LINE__);
+				goto i2c_error_exit;
+			}
+
+			ret = mhl_tx_set_reg(sii9234,
+					     MHL_TX_DISC_CTRL6_REG, 0x05);
+			if (ret < 0) {
+				printk(KERN_ERR "[ERROR] %s():%d write "
+					"MHL_TX_DISC_CTRL6_REG failed !\n",
+					__func__, __LINE__);
+				goto i2c_error_exit;
+			}
+			usleep_range(T_SRC_VBUS_CBUS_TO_STABLE * USEC_PER_MSEC,
+				     T_SRC_VBUS_CBUS_TO_STABLE * USEC_PER_MSEC);
+			/* end of this */
+			pr_debug("sii9234: %s() send wake up pulse\n",
+				 __func__);
+			ret = mhl_send_wake_pulses(sii9234);
+			if (ret < 0) {
+				pr_err("[ERROR] sii9234: "
+						"sending wake pulses error\n");
+				goto err_exit;
+			}
+			sii9234->rgnd = RGND_1K;
+			break;
+
+		case RGND_INTP_2K:
+			pr_debug("sii9234: RGND 2K\n");
+			sii9234->rgnd = RGND_2K;
+			break;
+		case RGND_INTP_SHORT:
+			pr_debug("sii9234: RGND Short\n");
+			sii9234->rgnd = RGND_SHORT;
+			break;
+		};
+
+		if (sii9234->rgnd != RGND_1K) {
+			mhl_poweroff = 1;	/*Power down mhl chip */
+			pr_debug("sii9234: RGND is not 1k\n");
+			sii9234->state = STATE_DISCOVERY_FAILED;
+			goto err_exit;
+		}
+	}
+
+	if (intr4 & CBUS_LKOUT_INT) {	/* 1<<4 */
+		pr_debug("%s(): CBUS Lockout Interrupt\n", __func__);
+		sii9234->state = STATE_CBUS_LOCKOUT;
+	}
+
+	if (intr4 & MHL_DISC_FAIL_INT) {	/* 1<<3 */
+		printk(KERN_ERR "[ERROR] %s(): MHL_DISC_FAIL_INT\n", __func__);
+		sii9234->state = STATE_DISCOVERY_FAILED;
+		goto err_exit;
+	}
+
+	if (intr4 & MHL_EST_INT) {	/* 1<<2 */
+		pr_debug("%s(): mhl est interrupt\n", __func__);
+
+		/* discovery override */
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_MHLTX_CTL1_REG, 0x10);
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "[ERROR] %s():%d write MHL_TX_MHLTX_CTRL1_REG failed !\n",
+			       __func__, __LINE__);
+			goto i2c_error_exit;
+		}
+
+		/* increase DDC translation layer timer (byte mode) */
+		ret = cbus_write_reg(sii9234, 0x07, 0x32);
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "[ERROR] %s():%d cbus_write_reg failed !\n",
+			       __func__, __LINE__);
+			goto i2c_error_exit;
+		}
+		ret = cbus_set_reg(sii9234, 0x44, 1 << 1);
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "[ERROR] %s():%d cbus_set_reg failed !\n",
+			       __func__, __LINE__);
+			goto i2c_error_exit;
+		}
+
+		/* Keep the discovery enabled. Need RGND interrupt */
+		ret = mhl_tx_set_reg(sii9234, MHL_TX_DISC_CTRL1_REG, (1 << 0));
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "[ERROR] %s():%d mhl_tx_set_reg failed !\n",
+			       __func__, __LINE__);
+			goto i2c_error_exit;
+		}
+
+		sii9234->state = STATE_ESTABLISHED;
+
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+		cbus_command_request(sii9234, CBUS_SET_INT,
+				     MHL_RCHANGE_INT, MHL_INT_DCAP_CHG);
+#else
+		sii9234_enqueue_msc_work(sii9234, CBUS_SET_INT,
+					 MHL_RCHANGE_INT, MHL_INT_DCAP_CHG,
+					 0x0);
+#endif
+
+		ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR1_ENABLE_REG,
+				       RSEN_CHANGE_INT_MASK |
+				       HPD_CHANGE_INT_MASK);
+	}
+
+	if (intr1 & HPD_CHANGE_INT) {	/* 1<<6 */
+		ret = cbus_read_reg(sii9234, MSC_REQ_ABORT_REASON_REG, &value);
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "[ERROR] %s():%d cbus_read_reg failed !\n",
+			       __func__, __LINE__);
+			goto i2c_error_exit;
+		}
+
+		if (value & SET_HPD_DOWNSTREAM) {
+			pr_info("%s() hpd high\n", __func__);
+			/* Downstream HPD High */
+
+			/* Do we need to send HPD upstream using
+			 * Register 0x79(page0)? Is HPD need to be overriden??
+			 *      TODO: See if we need code for overriding HPD OUT
+			 *      as per Page 0,0x79 Register
+			 */
+			sii9234->mhl_status_value.sink_hpd = true;
+#ifdef	__CONFIG_USE_TIMER__
+			if (cbus_command_abort_state == 1) {
+				pr_debug("cbus_command_mod_timer\n");
+				mod_timer(&sii9234->cbus_command_timer,
+					  jiffies + 2 * HZ);
+				cbus_command_abort_state = 0;
+			} else
+#endif
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+				cbus_command_request(sii9234, CBUS_WRITE_STAT,
+						CBUS_LINK_CONTROL_2_REG,
+						sii9234->mhl_status_value.
+						linkmode);
+#else
+				sii9234_enqueue_msc_work(sii9234,
+						CBUS_WRITE_STAT,
+						CBUS_LINK_CONTROL_2_REG,
+						sii9234->
+						mhl_status_value.
+						linkmode, 0x0);
+#endif
+			/* Enable TMDS */
+			sii9234_tmds_control(sii9234, true);
+			/*turn on&off hpd festure for only QCT HDMI */
+#ifdef CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+			mhl_hpd_handler(true);
+#endif
+
+		} else {
+			pr_info("sii9234: hpd low\n");
+			/*Downstream HPD Low */
+
+			/* Similar to above comments.
+			 * TODO:Do we need to override HPD OUT value
+			 * and do we need to disable TMDS here?
+			 */
+			sii9234->mhl_status_value.sink_hpd = false;
+			/* Disable TMDS */
+			sii9234_tmds_control(sii9234, false);
+		}
+	}
+
+	if (intr1 & RSEN_CHANGE_INT) {
+		/* work_around code to handle worng interrupt */
+		if (sii9234->rgnd != RGND_1K) {
+			pr_err("[ERROR] sii9234: Err RSEN_HIGH"
+			       " without RGND_1K rgnd=%d\n", sii9234->rgnd);
+			goto err_exit2;
+		}
+		ret = mhl_tx_read_reg(sii9234, MHL_TX_SYSSTAT_REG, &value);
+		if (ret < 0) {
+			pr_err("[ERROR] sii9234: "
+					"MHL_TX_SYSSTAT_REG read error\n");
+			goto err_exit2;
+		}
+		sii9234->rsen = value & RSEN_STATUS;
+
+		if (value & RSEN_STATUS) {
+			pr_info("%s(): MHL cable connected.. RSEN High\n",
+				__func__);
+		} else {
+			pr_info("%s(): RSEN lost -\n", __func__);
+			/* Once RSEN loss is confirmed,we need to check
+			 * based on cable status and chip power status,whether
+			 * it is SINK Loss(HDMI cable not connected, TV Off)
+			 * or MHL cable disconnection
+			 * TODO: Define the below mhl_disconnection()
+			 */
+#ifdef	__CONFIG_USE_TIMER__
+			del_timer(&sii9234->cbus_command_timer);
+#endif
+			msleep(T_SRC_RXSENSE_DEGLITCH);
+			ret = mhl_tx_read_reg(sii9234, MHL_TX_SYSSTAT_REG,
+					      &value);
+			if (ret < 0) {
+				printk(KERN_ERR
+				       "[ERROR] %s() read MHL_TX_SYSSTAT_REG\n",
+				       __func__);
+				goto i2c_error_exit;
+			}
+			pr_info("sii9234:  sys_stat: %x\n", value);
+
+			if ((value & RSEN_STATUS) == 0) {
+				printk(KERN_INFO
+				       "%s() RSEN Really LOW ~\n", __func__);
+				/*To meet CTS 3.3.22.2 spec */
+				sii9234_tmds_control(sii9234, false);
+				force_usb_id_switch_open(sii9234);
+				release_usb_id_switch_open(sii9234);
+				mhl_poweroff = 1;	/*Power down mhl chip */
+				goto err_exit;
+			} else
+				pr_info("sii9234: RSEN recovery ~\n");
+		}
+	}
+
+	/*
+	 * Process CBUS interrupts only when MHL connection has been
+	 * established
+	 */
+	if (sii9234->state == STATE_ESTABLISHED) {
+
+		if (cbus_intr1 & MSC_RESP_ABORT)
+			cbus_resp_abort_error(sii9234);
+
+		if (cbus_intr1 & MSC_REQ_ABORT) {
+#ifdef	__CONFIG_USE_TIMER__
+			cbus_write_reg(sii9234, CBUS_INTR1_ENABLE_REG, 0);
+			cbus_req_abort_error(sii9234);
+			cbus_write_reg(sii9234, CBUS_INTR1_ENABLE_REG, 0xFF);
+			cbus_command_abort_state = 1;
+#else
+			cbus_req_abort_error(sii9234);
+#endif
+		}
+		if ((cbus_intr1 & CBUS_DDC_ABORT) ||
+		    (cbus_intr1 & MSC_RESP_ABORT)) {
+			if (cbus_intr1 & CBUS_DDC_ABORT)
+				pr_debug("sii9234: CBUS DDC abort\n");
+			if (cbus_ddc_abort_error(sii9234))
+				schedule_work(&sii9234->mhl_end_work);
+		}
+
+		if (cbus_intr1 & MSC_REQ_DONE) {
+			pr_debug("sii9234: CBUS cmd ACK Received\n");
+#ifndef __MHL_NEW_CBUS_MSC_CMD__
+			cbus_resp_callback = cbus_command_response_all;
+#else
+			complete(&sii9234->msc_complete);
+#endif
+		}
+#ifdef CONFIG_SII9234_RCP
+		if (cbus_intr1 & MSC_MSG_RECD) {
+			pr_debug("sii9234: MSC MSG Received\n");
+			cbus_handle_msc_msg(sii9234);
+		}
+#endif
+
+		/* ignore WRT_STAT_RECD interrupt when we get HPD CHANGE */
+		if (cbus_intr2 & WRT_STAT_RECD && intr1 == 0)
+			cbus_handle_wrt_stat_recd(sii9234);
+
+		if (cbus_intr2 & SET_INT_RECD)
+			cbus_handle_set_int_recd(sii9234);
+	}
+
+ err_exit:
+	pr_debug("sii9234: wake_up\n");
+	wake_up(&sii9234->wq);
+ err_exit2:
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR1_REG, intr1);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = mhl_tx_write_reg(sii9234, MHL_TX_INTR4_REG, intr4);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	ret = cbus_write_reg(sii9234, CBUS_INT_STATUS_1_REG, cbus_intr1);
+	if (ret < 0)
+		goto i2c_error_exit;
+	ret = cbus_write_reg(sii9234, CBUS_INT_STATUS_2_REG, cbus_intr2);
+	if (ret < 0)
+		goto i2c_error_exit;
+
+	sii9234_mutex_unlock(&sii9234->lock);
+
+	if (cbus_resp_callback)
+		cbus_resp_callback(sii9234);
+
+	if (mhl_poweroff) {
+		if (sii9234_callback_sched != 0) {
+			sii9234_disable_irq();
+			schedule_work(&sii9234->mhl_d3_work);
+		}
+	}
+	return IRQ_HANDLED;
+
+ i2c_error_exit:
+	sii9234_mutex_unlock(&sii9234->lock);
+	pr_info("%s(): i2c error exit\n", __func__);
+	pr_debug("sii9234: wake_up\n");
+	wake_up(&sii9234->wq);
+	return IRQ_HANDLED;
+}
+
+static void mhl_cbus_command_timer(unsigned long data)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	schedule_work(&sii9234->mhl_cbus_write_stat_work);
+}
+
+#ifdef __CONFIG_SS_FACTORY__
+#define SII_ID 0x92
+static ssize_t sysfs_check_mhl_command(struct class *class,
+				       struct class_attribute *attr, char *buf)
+{
+	int size;
+	u8 sii_id = 0;
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+
+	if (sii9234->pdata->hw_onoff)
+		sii9234->pdata->hw_onoff(1);
+
+	if (sii9234->pdata->hw_reset)
+		sii9234->pdata->hw_reset();
+
+	mhl_tx_read_reg(sii9234, MHL_TX_IDH_REG, &sii_id);
+	pr_info("sii9234 : sel_show sii_id: %X\n", sii_id);
+
+	if (sii9234->pdata->hw_onoff)
+		sii9234->pdata->hw_onoff(0);
+
+	size = snprintf(buf, 10, "%d\n", sii_id == SII_ID ? 1 : 0);
+
+	return size;
+}
+
+static CLASS_ATTR(test_result, 0664, sysfs_check_mhl_command, NULL);
+#endif /*__CONFIG_SS_FACTORY__*/
+
+static ssize_t sysfs_mhl_read_reg_show(struct device *dev,
+				       struct device_attribute *attr, char *buf)
+{
+	pr_info("sii9234: %s()\n", __func__);
+	return sprintf(buf, "sysfs_mhl_read_reg_show\n");
+}
+
+static ssize_t sysfs_mhl_read_reg_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	struct sii9234_data *sii9234 = dev_get_drvdata(sii9244_mhldev);
+	enum page_num pn;
+	unsigned int offset;
+	int ret;
+	u8 value = 0;
+	char dest[10];
+	char *buffer = (char *)buf;
+	char *token;
+
+	if (size > 10) {
+		pr_info("sii9234: Error : Unsupported format\n");
+		return size;
+	}
+
+	if (strnicmp(buf, "mhl", 3) == 0) {
+		printk(KERN_INFO "sii9234: %s() - mhl start\n", __func__);
+		schedule_work(&sii9234->mhl_restart_work);
+	}
+
+	token = strsep(&buffer, ":");
+	if (token != NULL)
+		strcpy(dest, token);
+	else {
+		pr_info("sii9234: Error: command parsing error\n");
+		return size;
+	}
+
+	ret = kstrtouint(dest, 0, &offset);
+	if (ret != 0) {
+		pr_info("sii9234: Error : Page number\n");
+		return size;
+	}
+	pn = (enum page_num)offset;
+
+	strcpy(dest, buffer);
+	ret = kstrtouint(dest, 0, &offset);
+	if (ret || offset > 0xff) {
+		pr_info("sii9234: Error : Offset number\n");
+		return size;
+	}
+
+	switch (pn) {
+	case PAGE0:
+		mhl_tx_read_reg(sii9234, offset, &value);
+		break;
+	case PAGE1:
+		tpi_read_reg(sii9234, offset, &value);
+		break;
+	case PAGE2:
+		hdmi_rx_read_reg(sii9234, offset, &value);
+		break;
+	case PAGE3:
+		cbus_read_reg(sii9234, offset, &value);
+		break;
+	default:
+		pr_info("\nsii9234: Error : Out of the page number range\n");
+		return size;
+	}
+	pr_info("sii9234: MHL register Page%d:0x%02x = 0x%02x\n", pn, offset,
+		value);
+
+	return size;
+}
+
+static DEVICE_ATTR(mhl_read_reg, S_IRUGO | S_IWUSR,
+		   sysfs_mhl_read_reg_show, sysfs_mhl_read_reg_store);
+
+#ifdef __CONFIG_MHL_DEBUG__
+module_param_named(mhl_dbg_flag, mhl_dbg_flag, uint, 0644);
+#endif
+
+#ifdef CONFIG_SLP
+#ifdef CONFIG_PM_SLEEP
+static int sii9234_mhl_tx_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct sii9234_data *sii9234 = i2c_get_clientdata(client);
+
+	if (!sii9234 || !sii9234->pdata)
+		return -EFAULT;
+
+	sii9234_mutex_lock(&sii9234->lock);
+
+	if (!sii9234->pdata->power_state)
+		goto out;
+
+	sii9234->pdata->power_state = 0;
+
+	if (sii9234->pdata->mhl_sel)
+		sii9234->pdata->mhl_sel(0);
+
+	sii9234_power_down(sii9234);
+
+	if (sii9234->pdata->hw_onoff)
+		sii9234->pdata->hw_onoff(0);
+ out:
+	sii9234_mutex_unlock(&sii9234->lock);
+	return 0;
+}
+
+static int sii9234_mhl_tx_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct sii9234_data *sii9234 = i2c_get_clientdata(client);
+
+	if (!sii9234 || !sii9234->pdata)
+		return -EFAULT;
+
+	sii9234_mutex_lock(&sii9234->lock);
+
+#ifdef	CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+	if (!is_mhl_cable_connected()) {
+		sii9234_mutex_unlock(&sii9234->lock);
+		return 0;
+	}
+#endif
+
+	schedule_work(&sii9234->mhl_restart_work);
+	sii9234_mutex_unlock(&sii9234->lock);
+
+	return 0;
+}
+
+static const struct dev_pm_ops sii9234_pm_ops = {
+	.suspend = sii9234_mhl_tx_suspend,
+	.resume = sii9234_mhl_tx_resume,
+};
+#endif
+#endif
+
+#ifdef CONFIG_EXTCON
+static void sii9234_extcon_work(struct work_struct *work)
+{
+	struct sii9234_data *sii9234 =
+		container_of(work, struct sii9234_data, extcon_wq);
+
+	pr_info("%s: MHL is %s\n", __func__,
+		sii9234->extcon_attached ? "attached" : "detached");
+
+	if (sii9234->extcon_attached) {
+#ifdef CONFIG_SAMSUNG_MHL
+#ifdef CONFIG_MACH_MIDAS
+		sii9234_wake_lock();
+#endif
+		mhl_onoff_ex(1);
+#endif
+
+	} else {
+#ifdef CONFIG_SAMSUNG_MHL
+		mhl_onoff_ex(false);
+#ifdef CONFIG_MACH_MIDAS
+		sii9234_wake_unlock();
+#endif
+#endif
+	}
+}
+
+static int sii9234_extcon_notifier(struct notifier_block *self,
+			unsigned long event, void *ptr)
+{
+	struct sii9234_data *sii9234 =
+		container_of(self, struct sii9234_data, extcon_nb);
+
+	sii9234->extcon_attached = event;
+	schedule_work(&sii9234->extcon_wq);
+
+	return NOTIFY_DONE;
+}
+#endif
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void sii9234_early_suspend(struct early_suspend *early_sus)
+{
+	struct sii9234_data *sii9234 = container_of(early_sus,
+			struct sii9234_data, early_suspend);
+
+	pr_debug("%s()\n", __func__);
+	if (!sii9234 || !sii9234->pdata)
+		return;
+
+	sii9234_mutex_lock(&sii9234->lock);
+	sii9234->suspend_state = true;
+	sii9234_mutex_unlock(&sii9234->lock);
+}
+
+static void sii9234_late_resume(struct early_suspend *early_sus)
+{
+	struct sii9234_data *sii9234 = container_of(early_sus,
+			struct sii9234_data, early_suspend);
+
+	pr_debug("%s()\n", __func__);
+	if (!sii9234 || !sii9234->pdata)
+		return;
+
+	sii9234_mutex_lock(&sii9234->lock);
+	sii9234->suspend_state = false;
+	sii9234_mutex_unlock(&sii9234->lock);
+}
+#endif
+
+static int __devinit sii9234_mhl_tx_i2c_probe(struct i2c_client *client,
+					      const struct i2c_device_id *id)
+{
+	struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+	struct sii9234_data *sii9234;
+#ifdef CONFIG_SII9234_RCP
+	struct input_dev *input;
+#endif
+	int ret;
+#if defined(__CONFIG_SS_FACTORY__) || defined(__CONFIG_MHL_SWING_LEVEL__)
+	struct class *sec_mhl;
+#endif
+#ifdef __CONFIG_MHL_DEBUG__
+	mhl_dbg_flag = 1;
+#endif
+
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	sii9234 = kzalloc(sizeof(struct sii9234_data), GFP_KERNEL);
+	if (!sii9234) {
+		dev_err(&client->dev, "failed to allocate driver data\n");
+		return -ENOMEM;
+	}
+#ifdef CONFIG_SII9234_RCP
+	input = input_allocate_device();
+	if (!input) {
+		dev_err(&client->dev, "failed to allocate input device.\n");
+		ret = -ENOMEM;
+		goto err_exit0;
+	}
+#endif
+
+	sii9234->pdata = client->dev.platform_data;
+	if (!sii9234->pdata) {
+		ret = -EINVAL;
+		goto err_exit1;
+	}
+	sii9234->pdata->mhl_tx_client = client;
+
+	init_waitqueue_head(&sii9234->wq);
+	mutex_init(&sii9234->lock);
+	mutex_init(&sii9234->cbus_lock);
+
+#ifdef __SII9234_MUTEX_DEBUG__
+	g_mutex_cnt = 0;
+	g_cbus_mutex_cnt = 0;
+#endif
+	INIT_WORK(&sii9234->mhl_restart_work, mhl_start_worker);
+
+	INIT_WORK(&sii9234->mhl_end_work, mhl_end_worker);
+
+	INIT_WORK(&sii9234->rgnd_work, sii9234_detection_callback_worker);
+
+	INIT_WORK(&sii9234->mhl_d3_work, mhl_goto_d3_worker);
+
+	INIT_WORK(&sii9234->mhl_cbus_write_stat_work,
+		  mhl_cbus_write_stat_worker);
+
+	sii9234->pdata->init();
+
+	i2c_set_clientdata(client, sii9234);
+	client->irq = gpio_to_irq(GPIO_MHL_INT);
+	sii9244_mhldev = &client->dev;
+
+#ifdef CONFIG_MACH_MIDAS
+	wake_lock_init(&sii9234->mhl_wake_lock, WAKE_LOCK_SUSPEND,
+		       "mhl_wake_lock");
+	pr_debug("%s(): wake lock is initialized.\n", __func__);
+#endif
+
+	ret = request_threaded_irq(client->irq, NULL, sii9234_irq_thread,
+				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+				   "sii9234", sii9234);
+	if (ret < 0)
+		goto err_exit1;
+
+	atomic_set(&sii9234->is_irq_enabled, false);
+	disable_irq(client->irq);
+#ifdef __SII9234_IRQ_DEBUG__
+	en_irq = 0;
+#endif
+	if (sii9234->pdata->swing_level == 0)
+		sii9234->pdata->swing_level = 0xEB;
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	sii9234_msc_wq = create_singlethread_workqueue("sii9234_msc_wq");
+	if (!sii9234_msc_wq) {
+		printk(KERN_ERR
+		       "[ERROR] %s() workqueue create fail\n", __func__);
+		ret = -ENOMEM;
+	}
+	INIT_WORK(&sii9234->msc_work, sii9234_process_msc_work);
+#endif
+
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	sii9234_tmds_offon_wq =
+		create_singlethread_workqueue("sii9234_tmds_offon_wq");
+	if (!sii9234_tmds_offon_wq) {
+		printk(KERN_ERR	"[ERROR] %s() tmds_offon"
+				" workqueue create fail\n", __func__);
+		ret = -ENOMEM;
+	}
+	INIT_WORK(&sii9234->tmds_offon_work, sii9234_tmds_offon_work);
+#endif
+
+#if defined(__CONFIG_SS_FACTORY__) || defined(__CONFIG_MHL_SWING_LEVEL__)
+	pr_info("sii9234 : create mhl sysfile\n");
+
+	sec_mhl = class_create(THIS_MODULE, "mhl");
+	if (IS_ERR(sec_mhl)) {
+		pr_err("[ERROR] Failed to create class(sec_mhl)!\n");
+		goto err_exit1;
+	}
+#endif
+
+#ifdef __CONFIG_SS_FACTORY__
+	ret = class_create_file(sec_mhl, &class_attr_test_result);
+	if (ret) {
+		pr_err("[ERROR] Failed to create "
+				"device file in sysfs entries!\n");
+		goto err_exit2a;
+	}
+#endif
+
+#ifdef __CONFIG_MHL_SWING_LEVEL__
+	pr_info("sii9234 : create mhl sysfile\n");
+
+	ret = class_create_file(sec_mhl, &class_attr_swing);
+	if (ret) {
+		pr_err("[ERROR] failed to create swing sysfs file\n");
+		goto err_exit2b;
+	}
+#endif
+
+	sii9234->cbus_pkt.command = CBUS_IDLE;
+	sii9234->cbus_pkt.offset = DEVCAP_DEV_STATE;
+	init_timer(&sii9234->cbus_command_timer);
+	sii9234->cbus_command_timer.function = mhl_cbus_command_timer;
+	sii9234->cbus_command_timer.data = (unsigned int)NULL;
+
+	sii9234->cbus_command_timer.expires = 0xffffffffL;
+	add_timer(&sii9234->cbus_command_timer);
+#ifdef CONFIG_SII9234_RCP
+	/* indicate that we generate key events */
+	set_bit(EV_KEY, input->evbit);
+	bitmap_fill(input->keybit, KEY_MAX);
+
+	sii9234->input_dev = input;
+	input_set_drvdata(input, sii9234);
+	input->name = "sii9234_rcp";
+	input->id.bustype = BUS_I2C;
+
+	ret = input_register_device(input);
+	if (ret < 0) {
+		dev_err(&client->dev, "fail to register input device\n");
+		goto err_exit2c;
+	}
+#endif
+#ifdef CONFIG_SAMSUNG_MHL_9290
+	sii9234->acc_con_nb.notifier_call = sii9234_30pin_callback;
+	acc_register_notifier(&sii9234->acc_con_nb);
+#endif
+
+#ifdef CONFIG_EXTCON
+	/* Extcon */
+	INIT_WORK(&sii9234->extcon_wq, sii9234_extcon_work);
+	sii9234->extcon_nb.notifier_call = sii9234_extcon_notifier;
+	ret = extcon_register_interest(&sii9234->extcon_dev,
+					sii9234->pdata->extcon_name,
+					"MHL",
+					&sii9234->extcon_nb);
+	if (ret < 0) {
+		pr_info("Cannot register extcon_dev for %s(cable: MHL).\n",
+						sii9234->pdata->extcon_name);
+		ret = -EINVAL;
+		goto err_extcon;
+	}
+#endif
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	sii9234->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 5;
+	sii9234->early_suspend.suspend = sii9234_early_suspend;
+	sii9234->early_suspend.resume = sii9234_late_resume;
+	register_early_suspend(&sii9234->early_suspend);
+	sii9234->suspend_state = false;
+#endif
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	sii9234->tmds_state = 0;
+#endif
+	return 0;
+
+#ifdef CONFIG_EXTCON
+err_extcon:
+	extcon_unregister_interest(&sii9234->extcon_dev);
+#endif
+ err_exit2c:
+#ifdef __CONFIG_MHL_SWING_LEVEL__
+	class_remove_file(sec_mhl, &class_attr_swing);
+#endif
+ err_exit2b:
+#ifdef __CONFIG_SS_FACTORY__
+	class_remove_file(sec_mhl, &class_attr_test_result);
+#endif
+ err_exit2a:
+#if defined(__CONFIG_SS_FACTORY__) || defined(__CONFIG_MHL_SWING_LEVEL__)
+	class_destroy(sec_mhl);
+#endif
+ err_exit1:
+#ifdef CONFIG_SII9234_RCP
+	input_free_device(input);
+#endif
+ err_exit0:
+	kfree(sii9234);
+	return ret;
+}
+
+static int __devinit sii9234_tpi_i2c_probe(struct i2c_client *client,
+					   const struct i2c_device_id *id)
+{
+	struct sii9234_platform_data *pdata = client->dev.platform_data;
+	if (!pdata)
+		return -EINVAL;
+	pdata->tpi_client = client;
+	return 0;
+}
+
+static int __devinit sii9234_hdmi_rx_i2c_probe(struct i2c_client *client,
+					       const struct i2c_device_id *id)
+{
+	struct sii9234_platform_data *pdata = client->dev.platform_data;
+	if (!pdata)
+		return -EINVAL;
+
+	pdata->hdmi_rx_client = client;
+	return 0;
+}
+
+static int __devinit sii9234_cbus_i2c_probe(struct i2c_client *client,
+					    const struct i2c_device_id *id)
+{
+	struct sii9234_platform_data *pdata = client->dev.platform_data;
+	if (!pdata)
+		return -EINVAL;
+
+	pdata->cbus_client = client;
+	return 0;
+}
+
+static int __devexit sii9234_mhl_tx_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static int __devexit sii9234_tpi_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static int __devexit sii9234_hdmi_rx_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static int __devexit sii9234_cbus_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id sii9234_mhl_tx_id[] = {
+	{"sii9234_mhl_tx", 0},
+	{}
+};
+
+static const struct i2c_device_id sii9234_tpi_id[] = {
+	{"sii9234_tpi", 0},
+	{}
+};
+
+static const struct i2c_device_id sii9234_hdmi_rx_id[] = {
+	{"sii9234_hdmi_rx", 0},
+	{}
+};
+
+static const struct i2c_device_id sii9234_cbus_id[] = {
+	{"sii9234_cbus", 0},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, sii9234_mhl_tx_id);
+MODULE_DEVICE_TABLE(i2c, sii9234_tpi_id);
+MODULE_DEVICE_TABLE(i2c, sii9234_hdmi_rx_id);
+MODULE_DEVICE_TABLE(i2c, sii9234_cbus_id);
+
+static struct i2c_driver sii9234_mhl_tx_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "sii9234_mhl_tx",
+#ifdef CONFIG_SLP
+		   .pm = &sii9234_pm_ops,
+#endif
+		   },
+	.id_table = sii9234_mhl_tx_id,
+	.probe = sii9234_mhl_tx_i2c_probe,
+	.remove = __devexit_p(sii9234_mhl_tx_remove),
+	.command = NULL,
+};
+
+static struct i2c_driver sii9234_tpi_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "sii9234_tpi",
+		   },
+	.id_table = sii9234_tpi_id,
+	.probe = sii9234_tpi_i2c_probe,
+	.remove = __devexit_p(sii9234_tpi_remove),
+};
+
+static struct i2c_driver sii9234_hdmi_rx_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "sii9234_hdmi_rx",
+		   },
+	.id_table = sii9234_hdmi_rx_id,
+	.probe = sii9234_hdmi_rx_i2c_probe,
+	.remove = __devexit_p(sii9234_hdmi_rx_remove),
+};
+
+static struct i2c_driver sii9234_cbus_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "sii9234_cbus",
+		   },
+	.id_table = sii9234_cbus_id,
+	.probe = sii9234_cbus_i2c_probe,
+	.remove = __devexit_p(sii9234_cbus_remove),
+};
+
+static int __init sii9234_init(void)
+{
+	int ret;
+
+	ret = i2c_add_driver(&sii9234_mhl_tx_i2c_driver);
+	if (ret < 0)
+		return ret;
+
+	ret = i2c_add_driver(&sii9234_tpi_i2c_driver);
+	if (ret < 0)
+		goto err_exit1;
+
+	ret = i2c_add_driver(&sii9234_hdmi_rx_i2c_driver);
+	if (ret < 0)
+		goto err_exit2;
+
+	ret = i2c_add_driver(&sii9234_cbus_i2c_driver);
+	if (ret < 0)
+		goto err_exit3;
+
+	return 0;
+
+ err_exit3:
+	i2c_del_driver(&sii9234_hdmi_rx_i2c_driver);
+ err_exit2:
+	i2c_del_driver(&sii9234_tpi_i2c_driver);
+ err_exit1:
+	i2c_del_driver(&sii9234_mhl_tx_i2c_driver);
+	pr_err("[ERROR] i2c_add_driver fail\n");
+	return ret;
+}
+
+static void __exit sii9234_exit(void)
+{
+	i2c_del_driver(&sii9234_cbus_i2c_driver);
+	i2c_del_driver(&sii9234_hdmi_rx_i2c_driver);
+	i2c_del_driver(&sii9234_tpi_i2c_driver);
+	i2c_del_driver(&sii9234_mhl_tx_i2c_driver);
+}
+
+module_init(sii9234_init);
+module_exit(sii9234_exit);
diff --git a/drivers/media/video/mhl/sii9234_driver.h b/drivers/media/video/mhl/sii9234_driver.h
new file mode 100644
index 0000000..081e5f6
--- /dev/null
+++ b/drivers/media/video/mhl/sii9234_driver.h
@@ -0,0 +1,596 @@
+/*
+ * opyright (C) 2011 Samsung Electronics
+ *
+ * Authors: Adam Hampson <ahampson@sta.samsung.com>
+ *          Erik Gilling <konkers@android.com>
+ *
+ * Additional contributions by : Shankar Bandal <shankar.b@samsung.com>
+ *                               Dharam Kumar <dharam.kr@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#ifndef _SII9234_DRIVER_H_
+#define _SII9234_DRIVER_H_
+
+/*Flag for MHL Factory test*/
+#ifndef CONFIG_SS_FACTORY
+#define CONFIG_SS_FACTORY	1
+#endif
+
+#ifndef __CONFIG_TMDS_OFFON_WORKAROUND__
+#define __CONFIG_TMDS_OFFON_WORKAROUND__
+#endif
+
+#ifndef CONFIG_SII9234_RCP
+#define CONFIG_SII9234_RCP		1
+#include <linux/input.h>
+#endif
+#include <linux/wakelock.h>
+
+#ifdef CONFIG_SAMSUNG_MHL_9290
+#include <linux/30pin_con.h>
+#endif
+
+#ifdef CONFIG_SAMSUNG_SMARTDOCK
+#define ADC_SMARTDOCK   0x10 /* 40.2K ohm */
+#endif
+
+#define T_WAIT_TIMEOUT_RGND_INT		2000
+#define T_WAIT_TIMEOUT_DISC_INT		1000
+#define T_WAIT_TIMEOUT_RSEN_INT		200
+
+#define T_SRC_VBUS_CBUS_TO_STABLE	200
+#define T_SRC_WAKE_PULSE_WIDTH_1	19
+#define T_SRC_WAKE_PULSE_WIDTH_2	60
+#define T_SRC_WAKE_TO_DISCOVER		500
+#define T_SRC_VBUS_CBUS_T0_STABLE	500
+
+#define T_SRC_CBUS_FLOAT		100
+#define T_HPD_WIDTH			100
+#define T_SRC_RXSENSE_DEGLITCH		110
+#define T_SRC_CBUS_DEGLITCH		2
+
+/* MHL TX Addr 0x72 Registers */
+#define MHL_TX_IDL_REG                  0x02
+#define MHL_TX_IDH_REG                  0x03
+#define MHL_TX_REV_REG                  0x04
+#define MHL_TX_SRST                     0x05
+#define MHL_TX_INTR1_REG                0x71
+#define MHL_TX_INTR2_REG                0x72    /* Not Documented */
+#define MHL_TX_INTR3_REG                0x73    /* Not Documented */
+#define MHL_TX_INTR4_REG                0x74
+#define MHL_TX_INTR1_ENABLE_REG         0x75
+#define MHL_TX_INTR2_ENABLE_REG         0x76    /* Not Documented */
+#define MHL_TX_INTR3_ENABLE_REG         0x77    /* Not Documented */
+#define MHL_TX_INTR4_ENABLE_REG         0x78
+#define MHL_TX_INT_CTRL_REG             0x79
+#define MHL_TX_TMDS_CCTRL               0x80
+
+#define MHL_TX_DISC_CTRL1_REG           0x90
+#define MHL_TX_DISC_CTRL2_REG           0x91
+#define MHL_TX_DISC_CTRL3_REG           0x92
+#define MHL_TX_DISC_CTRL4_REG		0x93
+
+#define MHL_TX_DISC_CTRL5_REG           0x94
+#define MHL_TX_DISC_CTRL6_REG           0x95
+#define MHL_TX_DISC_CTRL7_REG           0x96
+#define MHL_TX_DISC_CTRL8_REG		0x97
+#define MHL_TX_STAT1_REG		0x98
+#define MHL_TX_STAT2_REG                0x99
+
+#define MHL_TX_MHLTX_CTL1_REG           0xA0
+#define MHL_TX_MHLTX_CTL2_REG           0xA1
+#define MHL_TX_MHLTX_CTL4_REG           0xA3
+#define MHL_TX_MHLTX_CTL6_REG           0xA5
+#define MHL_TX_MHLTX_CTL7_REG           0xA6
+
+/* MHL TX SYS STAT Registers */
+#define MHL_TX_SYSSTAT_REG              0x09
+
+/* MHL TX SYS STAT Register Bits */
+#define RSEN_STATUS                     (1<<2)
+
+/* MHL TX INTR4 Register Bits */
+#define RGND_READY_INT                  (1<<6)
+#define VBUS_LOW_INT                    (1<<5)
+#define CBUS_LKOUT_INT                  (1<<4)
+#define MHL_DISC_FAIL_INT               (1<<3)
+#define MHL_EST_INT                     (1<<2)
+
+/* MHL TX INTR4_ENABLE 0x78 Register Bits */
+#define RGND_READY_MASK                 (1<<6)
+#define CBUS_LKOUT_MASK                 (1<<4)
+#define MHL_DISC_FAIL_MASK              (1<<3)
+#define MHL_EST_MASK                    (1<<2)
+
+/* MHL TX INTR1 Register Bits*/
+#define HPD_CHANGE_INT                  (1<<6)
+#define RSEN_CHANGE_INT                 (1<<5)
+
+/* MHL TX INTR1_ENABLE 0x75 Register Bits*/
+#define HPD_CHANGE_INT_MASK             (1<<6)
+#define RSEN_CHANGE_INT_MASK            (1<<5)
+
+/* CBUS_INT_1_ENABLE: CBUS Transaction Interrupt #1 Mask */
+#define CBUS_INTR1_ENABLE_REG		0x09
+#define CBUS_INTR2_ENABLE_REG		0x1F
+
+/* CBUS Interrupt Status Registers*/
+#define CBUS_INT_STATUS_1_REG           0x08
+#define CBUS_INT_STATUS_2_REG           0x1E
+
+/* CBUS INTR1 STATUS Register bits */
+#define MSC_RESP_ABORT                  (1<<6)
+#define MSC_REQ_ABORT                   (1<<5)
+#define MSC_REQ_DONE                    (1<<4)
+#define MSC_MSG_RECD                    (1<<3)
+#define CBUS_DDC_ABORT                  (1<<2)
+
+/* CBUS INTR1 STATUS 0x09 Enable Mask*/
+#define MSC_RESP_ABORT_MASK             (1<<6)
+#define MSC_REQ_ABORT_MASK              (1<<5)
+#define MSC_REQ_DONE_MASK               (1<<4)
+#define MSC_MSG_RECD_MASK               (1<<3)
+#define CBUS_DDC_ABORT_MASK             (1<<2)
+
+/* CBUS INTR2 STATUS Register bits */
+#define WRT_STAT_RECD                   (1<<3)
+#define SET_INT_RECD                    (1<<2)
+#define WRT_BURST_RECD                  (1<<0)
+
+/* CBUS INTR2 STATUS 0x1F Enable Mask*/
+#define WRT_STAT_RECD_MASK              (1<<3)
+#define SET_INT_RECD_MASK               (1<<2)
+#define WRT_BURST_RECD_MASK             (1<<0)
+
+#define MHL_INT_EDID_CHG                (1<<1)
+
+#define MHL_RCHANGE_INT			0x20
+#define MHL_DCHANGE_INT			0x21
+#define MHL_INT_DCAP_CHG		(1<<0)
+#define MHL_INT_DSCR_CHG		(1<<1)
+#define MHL_INT_REQ_WRT			(1<<2)
+#define MHL_INT_GRT_WRT			(1<<3)
+
+/* CBUS Control Registers*/
+/* Retry count for all MSC commands*/
+#define MSC_RETRY_FAIL_LIM_REG          0x1D
+
+#define MSC_REQ_ABORT_REASON_REG        0x0D
+#define MSC_RESP_ABORT_REASON_REG       0x0E
+
+/* MSC Requestor/Responder Abort Reason Register bits*/
+#define ABORT_BY_PEER                   (1<<7)
+#define UNDEF_CMD                       (1<<3)
+#define TIMEOUT                         (1<<2)
+#define PROTO_ERROR                     (1<<1)
+#define MAX_FAIL                        (1<<0)
+
+#define REG_CBUS_INTR_STATUS		0x08
+/* Responder aborted DDC command at translation layer */
+#define BIT_DDC_ABORT			(1<<2)
+/* Responder sent a VS_MSG packet (response data or command.) */
+#define BIT_MSC_MSG_RCV			(1<<3)
+ /* Responder sent ACK packet (not VS_MSG) */
+#define BIT_MSC_XFR_DONE		(1<<4)
+ /* Command send aborted on TX side */
+#define BIT_MSC_XFR_ABORT		(1<<5)
+#define BIT_MSC_ABORT			(1<<6)
+
+/* Set HPD came from Downstream, */
+#define SET_HPD_DOWNSTREAM              (1<<6)
+
+/* MHL TX DISC1 Register Bits */
+#define DISC_EN                         (1<<0)
+
+/* MHL TX DISC2 Register Bits */
+#define SKIP_GND                        (1<<6)
+#define ATT_THRESH_SHIFT                0x04
+#define ATT_THRESH_MASK                 (0x03 << ATT_THRESH_SHIFT)
+#define USB_D_OEN                       (1<<3)
+#define DEGLITCH_TIME_MASK              0x07
+#define DEGLITCH_TIME_2MS               0
+#define DEGLITCH_TIME_4MS               1
+#define DEGLITCH_TIME_8MS               2
+#define DEGLITCH_TIME_16MS              3
+#define DEGLITCH_TIME_40MS              4
+#define DEGLITCH_TIME_50MS              5
+#define DEGLITCH_TIME_60MS              6
+#define DEGLITCH_TIME_128MS             7
+
+#define DISC_CTRL3_COMM_IMME            (1<<7)
+#define DISC_CTRL3_FORCE_MHL            (1<<6)
+#define DISC_CTRL3_FORCE_USB            (1<<4)
+#define DISC_CTRL3_USB_EN               (1<<3)
+
+/* MHL TX DISC4 0x93 Register Bits*/
+#define CBUS_DISC_PUP_SEL_SHIFT         6
+#define CBUS_DISC_PUP_SEL_MASK          (3<<CBUS_DISC_PUP_SEL_SHIFT)
+#define CBUS_DISC_PUP_SEL_10K           (2<<CBUS_DISC_PUP_SEL_SHIFT)
+#define CBUS_DISC_PUP_SEL_OPEN          (0<<CBUS_DISC_PUP_SEL_SHIFT)
+#define CBUS_IDLE_PUP_SEL_SHIFT         4
+#define CBUS_IDLE_PUP_SEL_MASK          (3<<CBUS_IDLE_PUP_SEL_SHIFT)
+#define CBUS_IDLE_PUP_SEL_OPEN          (0<<CBUS_IDLE_PUP_SEL_SHIFT)
+
+/* MHL TX DISC5 0x94 Register Bits */
+#define CBUS_MHL_PUP_SEL_MASK		0x03
+#define CBUS_MHL_PUP_SEL_5K		0x01
+#define CBUS_MHL_PUP_SEL_OPEN           0x00
+
+/* MHL Interrupt Registers */
+#define CBUS_MHL_INTR_REG_0		0xA0
+#define CBUS_MHL_INTR_REG_1		0xA1
+#define CBUS_MHL_INTR_REG_2		0xA2
+#define CBUS_MHL_INTR_REG_3		0xA3
+
+/* MHL Status Registers */
+#define CBUS_MHL_STATUS_REG_0           0xB0
+#define CBUS_MHL_STATUS_REG_1           0xB1
+#define CBUS_MHL_STATUS_REG_2           0xB2
+#define CBUS_MHL_STATUS_REG_3           0xB3
+
+/* MHL TX DISC6 0x95 Register Bits */
+#define USB_D_OVR                       (1<<7)
+#define USB_ID_OVR                      (1<<6)
+#define DVRFLT_SEL                      (1<<5)
+#define BLOCK_RGND_INT                  (1<<4)
+#define SKIP_DEG                        (1<<3)
+#define CI2CA_POL                       (1<<2)
+#define CI2CA_WKUP                      (1<<1)
+#define SINGLE_ATT                      (1<<0)
+
+/* MHL TX DISC7 0x96 Register Bits
+ *
+ * Bits 7 and 6 are labeled as reserved but seem to be related to toggling
+ * the CBUS signal when generating the wake pulse sequence.
+ */
+#define USB_D_ODN                       (1<<5)
+#define VBUS_CHECK                      (1<<2)
+#define RGND_INTP_MASK                  0x03
+#define RGND_INTP_OPEN                  0
+#define RGND_INTP_2K                    1
+#define RGND_INTP_1K                    2
+#define RGND_INTP_SHORT                 3
+
+/* TPI Addr 0x7A Registers */
+#define TPI_DPD_REG                     0x3D
+
+#define TPI_PD_TMDS                     (1<<5)
+#define TPI_PD_OSC_EN                   (1<<4)
+#define TPI_TCLK_PHASE                  (1<<3)
+#define TPI_PD_IDCK                     (1<<2)
+#define TPI_PD_OSC                      (1<<1)
+#define TPI_PD                          (1<<0)
+
+#define CBUS_CONFIG_REG                 0x07
+#define CBUS_LINK_CONTROL_2_REG         0x31
+
+/* HDMI RX Registers */
+#define HDMI_RX_TMDS0_CCTRL1_REG        0x10
+#define HDMI_RX_TMDS_CLK_EN_REG         0x11
+#define HDMI_RX_TMDS_CH_EN_REG          0x12
+#define HDMI_RX_PLL_CALREFSEL_REG       0x17
+#define HDMI_RX_PLL_VCOCAL_REG          0x1A
+#define HDMI_RX_EQ_DATA0_REG            0x22
+#define HDMI_RX_EQ_DATA1_REG            0x23
+#define HDMI_RX_EQ_DATA2_REG            0x24
+#define HDMI_RX_EQ_DATA3_REG            0x25
+#define HDMI_RX_EQ_DATA4_REG            0x26
+#define HDMI_RX_TMDS_ZONE_CTRL_REG      0x4C
+#define HDMI_RX_TMDS_MODE_CTRL_REG      0x4D
+
+/* MHL SideBand Channel(MSC) Registers */
+#define CBUS_MSC_COMMAND_START_REG      0x12
+#define CBUS_MSC_OFFSET_REG             0x13
+#define CBUS_MSC_FIRST_DATA_OUT_REG     0x14
+#define CBUS_MSC_SECOND_DATA_OUT_REG    0x15
+#define CBUS_MSC_FIRST_DATA_IN_REG      0x16
+#define CBUS_MSC_SECOND_DATA_IN_REG     0x17
+#define CBUS_MSC_MSG_CMD_IN_REG         0x18
+#define CBUS_MSC_MSG_DATA_IN_REG        0x19
+#define CBUS_MSC_WRITE_BURST_LEN        0x20
+#define	CBUS_MSC_RAP_CONTENT_ON		0x10
+#define	CBUS_MSC_RAP_CONTENT_OFF	0x11
+
+/* Register Bits for CBUS_MSC_COMMAND_START_REG */
+#define START_BIT_MSC_RESERVED		(1<<0)
+#define START_BIT_MSC_MSG		(1<<1)
+#define START_BIT_READ_DEVCAP		(1<<2)
+#define START_BIT_WRITE_STAT_INT	(1<<3)
+#define START_BIT_WRITE_BURST		(1<<4)
+
+/* MHL Device Capability Register offsets */
+#define DEVCAP_DEV_STATE		0x00
+#define DEVCAP_MHL_VERSION		0x01
+#define DEVCAP_DEV_CAT                  0x02
+#define DEVCAP_ADOPTER_ID_H		0x03
+#define DEVCAP_ADOPTER_ID_L		0x04
+#define DEVCAP_VID_LINK_MODE		0x05
+#define DEVCAP_AUD_LINK_MODE		0x06
+#define DEVCAP_VIDEO_TYPE		0x07
+#define DEVCAP_LOG_DEV_MAP		0x08
+#define DEVCAP_BANDWIDTH		0x09
+#define DEVCAP_DEV_FEATURE_FLAG         0x0A
+#define DEVCAP_DEVICE_ID_H              0x0B
+#define DEVCAP_DEVICE_ID_L              0x0C
+#define DEVCAP_SCRATCHPAD_SIZE		0x0D
+#define DEVCAP_INT_STAT_SIZE		0x0E
+#define DEVCAP_RESERVED			0x0F
+
+#define BIT0				0x01
+#define BIT1				0x02
+#define BIT2				0x04
+#define BIT3				0x08
+#define BIT4				0x10
+#define BIT5				0x20
+#define BIT6				0x40
+#define BIT7				0x80
+
+#define MHL_DEV_CATEGORY_POW_BIT        (1<<4)
+
+/* Device Capability Ready Bit */
+#define MHL_STATUS_DCAP_READY           (1<<0)
+
+#define MHL_FEATURE_RCP_SUPPORT         (1<<0)
+#define MHL_FEATURE_RAP_SUPPORT         (1<<1)
+#define MHL_FEATURE_SP_SUPPORT          (1<<2)
+
+#define MHL_STATUS_CLK_MODE_PACKED_PIXEL	0x02
+#define MHL_STATUS_CLK_MODE_NORMAL	0x03
+
+#define MHL_STATUS_PATH_ENABLED		0x08
+#define MHL_STATUS_PATH_DISABLED	0x00
+
+#define MHL_STATUS_REG_CONNECTED_RDY	0x30
+
+#define CBUS_PKT_BUF_COUNT		18
+
+#define VBUS_NONE			0
+#define VBUS_USB			1
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+#	define SS_MHL_DONGLE_DEV_ID		0x1134
+#	define SS_MHL_DOCK_DEV_ID		0x1234
+#endif
+
+/* wolverin*/
+#define	INTR_CBUS1_DESIRED_MASK		(BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
+#define	INTR_CBUS2_DESIRED_MASK		(BIT2 | BIT3) /* (BIT0| BIT2 | BIT3) */
+
+enum page_num {
+	PAGE0 = 0,
+	PAGE1,
+	PAGE2,
+	PAGE3
+};
+
+enum rgnd_state {
+	RGND_UNKNOWN = 0,
+	RGND_OPEN,
+	RGND_1K,
+	RGND_2K,
+	RGND_SHORT
+};
+
+enum mhl_state {
+	NO_MHL_STATUS = 0x00,
+	STATE_DISCONNECTED,
+	STATE_DISCOVERY_FAILED,
+	STATE_CBUS_LOCKOUT,
+	STATE_ESTABLISHED,
+	MHL_READY_RGND_DETECT,  /* after d3mode wait rgnd int */
+	MHL_RX_CONNECTED, /* after detection rgnd 1K */
+	MHL_USB_CONNECTED, /* mhl is not 1K */
+	MHL_DISCOVERY_ON,
+	MHL_DISCOVERY_SUCCESS, /* after detection RSEN */
+};
+
+enum msc_subcommand {
+	/* MSC_MSG Sub-Command codes */
+	MSG_RCP =       0x10,
+	MSG_RCPK =      0x11,
+	MSG_RCPE =      0x12,
+	MSG_RAP =       0x20,
+	MSG_RAPK =      0x21,
+};
+
+enum cbus_command {
+	CBUS_IDLE =     0x00,
+	CBUS_ACK =		0x33,
+	CBUS_NACK =		0x35,
+	CBUS_WRITE_STAT  =      0x60 | 0x80,
+	CBUS_SET_INT     =      0x60,
+	CBUS_READ_DEVCAP =      0x61,
+	CBUS_GET_STATE =	0x62,
+	CBUS_GET_VENDOR_ID =	0x63,
+	CBUS_SET_HPD =		0x64,
+	CBUS_CLR_HPD =		0x65,
+	CBUS_SET_CAP_ID =	0x66,
+	CBUS_GET_CAP_ID =	0x67,
+	CBUS_MSC_MSG =		0x68,
+	CBUS_GET_SC1_ERR_CODE =	0x69,
+	CBUS_GET_DDC_ERR_CODE =	0x6A,
+	CBUS_GET_MSC_ERR_CODE =	0x6B,
+	CBUS_WRITE_BURST =      0x6C,
+	CBUS_GET_SC3_ERR_CODE =	0x6D,
+};
+#if 0
+enum mhl_status_enum_type {
+	NO_MHL_STATUS = 0x00,
+	MHL_INIT_DONE,
+	MHL_WAITING_RGND_DETECT,
+	MHL_CABLE_CONNECT,
+	MHL_DISCOVERY_START,
+	MHL_DISCOVERY_END,
+	MHL_DISCOVERY_SUCCESS,
+	MHL_DISCOVERY_FAIL,
+	MHL_RSEN_GLITCH,
+	MHL_RSEN_LOW,
+};
+
+#endif
+struct mhl_tx_status_type {
+	u8 intr4_mask_value;
+	u8 intr1_mask_value;
+	u8 intr_cbus1_mask_value;
+	u8 intr_cbus2_mask_value;
+/*	enum mhl_status_enum_type mhl_status;*/
+	u8 linkmode;
+	u8 connected_ready;
+	bool cbus_connected;
+	bool sink_hpd;
+	bool rgnd_1k;
+	u8 rsen_check_available;
+};
+
+static inline bool mhl_state_is_error(enum mhl_state state)
+{
+	return state == STATE_DISCOVERY_FAILED ||
+		state == STATE_CBUS_LOCKOUT;
+}
+
+struct sii9234_data;
+#define CBUS_DATA_LENGTH 2
+/* Structure for holding MSC command data */
+struct cbus_packet {
+	enum cbus_command command;
+	u8 offset;
+	u8 data[CBUS_DATA_LENGTH];
+	u8 status;
+};
+
+struct device_cap {
+	u8 mhl_ver;
+	u8 dev_type;
+	u16 adopter_id;
+	u8 vid_link_mode;
+	u8 aud_link_mode;
+	u8 video_type;
+	u8 log_dev_map;
+	u8 bandwidth;
+	u16 device_id;
+	u8 scratchpad_size;
+	u8 int_stat_size;
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	u8 reserved_data; /*Only SAMSUNG use this offset
+			  as a method to distinguish TA and USB*/
+#endif
+
+	bool rcp_support;
+	bool rap_support;
+	bool sp_support;
+};
+
+struct sii9234_data {
+	struct sii9234_platform_data	*pdata;
+	wait_queue_head_t		wq;
+#ifdef CONFIG_SAMSUNG_MHL_9290
+	struct notifier_block           acc_con_nb;
+#endif
+	bool				claimed;
+	u8				cbus_connected; /* wolverin */
+	enum mhl_state			state;
+	enum rgnd_state			rgnd;
+	bool				rsen;
+	atomic_t			is_irq_enabled;
+
+	struct mutex			lock;
+	struct mutex			cbus_lock;
+	struct mutex			mhl_status_lock; /* wolverin */
+	struct cbus_packet		cbus_pkt;
+	struct cbus_packet		cbus_pkt_buf[CBUS_PKT_BUF_COUNT];
+	struct device_cap		devcap;
+	struct mhl_tx_status_type mhl_status_value;
+#ifdef CONFIG_SII9234_RCP
+	u8 error_key;
+	struct input_dev		*input_dev;
+#endif
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+	struct completion		msc_complete;
+	struct work_struct		msc_work;
+	int				vbus_owner;
+	int				dcap_ready_status;
+#endif
+
+	struct work_struct		mhl_restart_work;
+	struct work_struct		mhl_end_work;
+	struct work_struct		rgnd_work;
+	struct work_struct		mhl_cbus_write_stat_work;
+	struct work_struct		mhl_d3_work;
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	struct work_struct		tmds_offon_work;
+#endif
+	struct timer_list		cbus_command_timer;
+#ifdef CONFIG_MACH_MIDAS
+	struct wake_lock		mhl_wake_lock;
+#endif
+	struct work_struct mhl_tx_init_work; /* wolverin */
+	struct workqueue_struct *mhl_tx_init_wq;
+	struct work_struct mhl_400ms_rsen_work;
+	struct workqueue_struct *mhl_400ms_rsen_wq;
+
+#ifdef CONFIG_EXTCON
+	/* Extcon */
+	struct extcon_specific_cable_nb extcon_dev;
+	struct notifier_block extcon_nb;
+	struct work_struct extcon_wq;
+	bool extcon_attached;
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend early_suspend;
+	bool suspend_state;
+#endif
+#ifdef __CONFIG_TMDS_OFFON_WORKAROUND__
+	bool tmds_state;
+#endif
+};
+
+#ifdef __MHL_NEW_CBUS_MSC_CMD__
+struct msc_packet {
+	enum cbus_command	command;
+	u8	offset;
+	u8	data_1;
+	u8	data_2;
+	struct list_head p_msc_packet_list;
+};
+
+static int sii9234_msc_req_locked(struct sii9234_data *sii9234,
+					struct msc_packet *msc_pkt);
+static int sii9234_enqueue_msc_work(struct sii9234_data *sii9234, u8 command,
+		u8 offset, u8 data_1, u8 data_2);
+#endif
+static struct device *sii9244_mhldev;
+extern void mhl_hpd_handler(bool state);
+static int sii9234_detection_callback(void);
+static void sii9234_cancel_callback(void);
+static u8 sii9234_tmds_control(struct sii9234_data *sii9234, bool enable);
+static bool cbus_command_request(struct sii9234_data *sii9234,
+				 enum cbus_command command,
+				 u8 offset, u8 data);
+static void cbus_command_response(struct sii9234_data *sii9234);
+static irqreturn_t sii9234_irq_thread(int irq, void *data);
+
+#ifdef CONFIG_SAMSUNG_MHL_9290
+static int sii9234_30pin_init_for_9290(struct sii9234_data *sii9234);
+#endif
+
+#ifdef CONFIG_SAMSUNG_USE_11PIN_CONNECTOR
+#	if !defined(CONFIG_MACH_P4NOTE)
+extern int max77693_muic_get_status1_adc1k_value(void);
+#endif
+#endif
+
+#endif
diff --git a/drivers/media/video/s5c73m3.c b/drivers/media/video/s5c73m3.c
new file mode 100644
index 0000000..07fab10
--- /dev/null
+++ b/drivers/media/video/s5c73m3.c
@@ -0,0 +1,3413 @@
+/*
+ * driver for LSI S5C73M3 (ISP for 8MP Camera)
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <media/v4l2-device.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+#include <linux/firmware.h>
+#include <linux/videodev2.h>
+#include <linux/unistd.h>
+
+#include <plat/gpio-cfg.h>
+#include <linux/gpio.h>
+
+#define S5C73M3_BUSFREQ_OPP
+
+#ifdef S5C73M3_BUSFREQ_OPP
+#include <mach/dev.h>
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#endif
+
+#include <linux/regulator/machine.h>
+
+#include <media/s5c73m3_platform.h>
+#include "s5c73m3.h"
+
+#define S5C73M3_DRIVER_NAME	"S5C73M3"
+
+extern struct class *camera_class; /*sys/class/camera*/
+struct device *s5c73m3_dev; /*sys/class/camera/rear*/
+struct v4l2_subdev *sd_internal;
+
+#ifdef S5C73M3_BUSFREQ_OPP
+struct device *bus_dev;
+#endif
+
+/*#define S5C73M3_FROM_BOOTING*/
+#define S5C73M3_CORE_VDD	"/data/ISP_CV"
+#define S5C73M3_FW_PATH		"/sdcard/SlimISP.bin"
+#define S5C73M3_FW_VER_LEN		6
+#define S5C73M3_FW_VER_FILE_CUR	0x60
+
+#define S5C73M3_I2C_RETRY		5
+
+#define CHECK_ERR(x)	if ((x) < 0) { \
+				cam_err("i2c failed, err %d\n", x); \
+				return x; \
+			}
+struct s5c73m3_fw_version camfw_info[S5C73M3_PATH_MAX];
+
+static const struct s5c73m3_frmsizeenum preview_frmsizes[] = {
+	{ S5C73M3_PREVIEW_QVGA,	320,	240,	0x01 },
+	{ S5C73M3_PREVIEW_CIF,	352,	288,	0x0E },
+	{ S5C73M3_PREVIEW_VGA,	640,	480,	0x02 },
+	{ S5C73M3_PREVIEW_704X576,	704,	576,	0x09 },
+	{ S5C73M3_PREVIEW_880X720,	880,	720,	0x03 },
+	{ S5C73M3_PREVIEW_960X640,	960,	640,	0x0B },
+	{ S5C73M3_PREVIEW_960X720,	960,	720,	0x04 },
+	{ S5C73M3_PREVIEW_1008X672,	1008,	672,	0x0F },
+	{ S5C73M3_PREVIEW_1184X666,	1184,	666,	0x05 },
+	{ S5C73M3_PREVIEW_720P,	1280,	720,	0x06 },
+	{ S5C73M3_VDIS_720P,	1536,	864,	0x07 },
+	{ S5C73M3_PREVIEW_1080P,	1920,	1080,	0x0A},
+	{ S5C73M3_VDIS_1080P,	2304,	1296,	0x0C},
+};
+
+static const struct s5c73m3_frmsizeenum capture_frmsizes[] = {
+	{ S5C73M3_CAPTURE_VGA,	640,	480,	0x10 },
+	{ S5C73M3_CAPTURE_1024X768,	1024,	768,	0xD0 },
+	{ S5C73M3_CAPTURE_HD,	1280,	720,	0x40 },
+	{ S5C73M3_CAPTURE_2MP,	1600,	1200,	0x70 },
+	{ S5C73M3_CAPTURE_W2MP,	2048,	1152,	0x80 },
+	{ S5C73M3_CAPTURE_3MP,	2048,	1536,	0x90 },
+	{ S5C73M3_CAPTURE_5MP,	2560,	1920,	0xB0 },
+	{ S5C73M3_CAPTURE_W6MP,	3264,	1836,	0xE0 },
+	{ S5C73M3_CAPTURE_3264X2176,	3264,	2176,	0xC0 },
+	{ S5C73M3_CAPTURE_8MP,	3264,	2448,	0xF0 },
+};
+
+static const struct s5c73m3_effectenum s5c73m3_effects[] = {
+	{IMAGE_EFFECT_NONE, S5C73M3_IMAGE_EFFECT_NONE},
+	{IMAGE_EFFECT_NEGATIVE, S5C73M3_IMAGE_EFFECT_NEGATIVE},
+	{IMAGE_EFFECT_AQUA, S5C73M3_IMAGE_EFFECT_AQUA},
+	{IMAGE_EFFECT_SEPIA, S5C73M3_IMAGE_EFFECT_SEPIA},
+	{IMAGE_EFFECT_BNW, S5C73M3_IMAGE_EFFECT_MONO},
+	{IMAGE_EFFECT_SKETCH, S5C73M3_IMAGE_EFFECT_SKETCH},
+	{IMAGE_EFFECT_WASHED, S5C73M3_IMAGE_EFFECT_WASHED},
+	{IMAGE_EFFECT_VINTAGE_WARM, S5C73M3_IMAGE_EFFECT_VINTAGE_WARM},
+	{IMAGE_EFFECT_VINTAGE_COLD, S5C73M3_IMAGE_EFFECT_VINTAGE_COLD},
+	{IMAGE_EFFECT_SOLARIZE, S5C73M3_IMAGE_EFFECT_SOLARIZE},
+	{IMAGE_EFFECT_POSTERIZE, S5C73M3_IMAGE_EFFECT_POSTERIZE},
+	{IMAGE_EFFECT_POINT_BLUE, S5C73M3_IMAGE_EFFECT_POINT_BLUE},
+	{IMAGE_EFFECT_POINT_RED_YELLOW, S5C73M3_IMAGE_EFFECT_POINT_RED_YELLOW},
+	{IMAGE_EFFECT_POINT_COLOR_3, S5C73M3_IMAGE_EFFECT_POINT_COLOR_3},
+	{IMAGE_EFFECT_POINT_GREEN, S5C73M3_IMAGE_EFFECT_POINT_GREEN},
+};
+
+static struct s5c73m3_control s5c73m3_ctrls[] = {
+	{
+		.id = V4L2_CID_CAMERA_ISO,
+		.minimum = ISO_AUTO,
+		.maximum = ISO_800,
+		.step = 1,
+		.value = ISO_AUTO,
+		.default_value = ISO_AUTO,
+	}, {
+		.id = V4L2_CID_CAMERA_BRIGHTNESS,
+		.minimum = EV_MINUS_4,
+		.maximum = EV_MAX - 1,
+		.step = 1,
+		.value = EV_DEFAULT,
+		.default_value = EV_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SATURATION,
+		.minimum = SATURATION_MINUS_2,
+		.maximum = SATURATION_MAX - 1,
+		.step = 1,
+		.value = SATURATION_DEFAULT,
+		.default_value = SATURATION_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_SHARPNESS,
+		.minimum = SHARPNESS_MINUS_2,
+		.maximum = SHARPNESS_MAX - 1,
+		.step = 1,
+		.value = SHARPNESS_DEFAULT,
+		.default_value = SHARPNESS_DEFAULT,
+	}, {
+		.id = V4L2_CID_CAMERA_ZOOM,
+		.minimum = ZOOM_LEVEL_0,
+		.maximum = ZOOM_LEVEL_MAX - 1,
+		.step = 1,
+		.value = ZOOM_LEVEL_0,
+		.default_value = ZOOM_LEVEL_0,
+	}, {
+		.id = V4L2_CID_CAM_JPEG_QUALITY,
+		.minimum = 1,
+		.maximum = 100,
+		.step = 1,
+		.value = 100,
+		.default_value = 100,
+	},
+};
+
+static u8 sysfs_sensor_fw[10] = {0,};
+static u8 sysfs_phone_fw[10] = {0,};
+static u8 sysfs_sensor_type[15] = {0,};
+static u8 sysfs_isp_core[10] = {0,};
+static u8 data_memory[500000] = {0,};
+
+static u16 isp_chip_info1;
+static u16 isp_chip_info2;
+static u16 isp_chip_info3;
+
+static int s5c73m3_s_stream_sensor(struct v4l2_subdev *sd, int onoff);
+static int s5c73m3_set_touch_auto_focus(struct v4l2_subdev *sd);
+static int s5c73m3_SPI_booting(struct v4l2_subdev *sd);
+static int s5c73m3_get_af_cal_version(struct v4l2_subdev *sd);
+static int s5c73m3_set_timing_register_for_vdd(struct v4l2_subdev *sd);
+
+static inline struct s5c73m3_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5c73m3_state, sd);
+}
+
+static int s5c73m3_i2c_write(struct v4l2_subdev *sd,
+	unsigned short addr, unsigned short data)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char buf[4];
+	int i, err;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(buf);
+	msg.buf = buf;
+
+	buf[0] = addr >> 8;
+	buf[1] = addr & 0xff;
+	buf[2] = data >> 8;
+	buf[3] = data & 0xff;
+
+	cam_i2c_dbg("addr %#x, data %#x\n", addr, data);
+
+	for (i = S5C73M3_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	return err;
+}
+
+static int s5c73m3_i2c_write_block(struct v4l2_subdev *sd,
+	const u32 regs[], int size)
+{
+	int i, err = 0;
+
+	for (i = 0; i < size; i++) {
+		err = s5c73m3_i2c_write(sd, (regs[i]>>16), regs[i]);
+		CHECK_ERR(err);
+	}
+
+	return err;
+}
+
+static int s5c73m3_i2c_read(struct v4l2_subdev *sd,
+	unsigned short addr, unsigned short *data)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg;
+	unsigned char buf[2];
+	int i, err;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = sizeof(buf);
+	msg.buf = buf;
+
+	buf[0] = addr >> 8;
+	buf[1] = addr & 0xff;
+
+	for (i = S5C73M3_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("addr %#x\n", addr);
+		return err;
+	}
+
+	msg.flags = I2C_M_RD;
+
+	for (i = S5C73M3_I2C_RETRY; i; i--) {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			break;
+		msleep(20);
+	}
+
+	if (err != 1) {
+		cam_err("addr %#x\n", addr);
+		return err;
+	}
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return err;
+}
+
+static int s5c73m3_write(struct v4l2_subdev *sd,
+	unsigned short addr1, unsigned short addr2, unsigned short data)
+{
+	int err;
+
+	err = s5c73m3_i2c_write(sd, 0x0050, addr1);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, addr2);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, data);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_read(struct v4l2_subdev *sd,
+	unsigned short addr1, unsigned short addr2, unsigned short *data)
+{
+	int err;
+
+	err = s5c73m3_i2c_write(sd, 0xfcfc, 0x3310);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0058, addr1);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x005C, addr2);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_read(sd, 0x0F14, data);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_i2c_check_status(struct v4l2_subdev *sd)
+{
+	int err = 0;
+	int index = 0;
+	u16 status = 0;
+	u16 i2c_status = 0;
+	u16 i2c_seq_status = 0;
+
+	do {
+		err = s5c73m3_read(sd, 0x0009, S5C73M3_STATUS, &status);
+		if (status == 0xffff)
+			break;
+
+		index++;
+		udelay(500);
+	} while (index < 2000);	/* 1 sec */
+
+	if (index >= 2000) {
+		err = s5c73m3_read(sd, 0x0009,
+			S5C73M3_I2C_ERR_STATUS, &i2c_status);
+		err = s5c73m3_read(sd, 0x0009,
+			S5C73M3_I2C_SEQ_STATUS, &i2c_seq_status);
+		cam_dbg("TimeOut!! index:%d,status:%#x,i2c_stauts:%#x,i2c_seq_status:%#x\n",
+			index,
+			status,
+			i2c_status,
+			i2c_seq_status);
+
+		err = -1;
+	}
+
+	return err;
+}
+
+static int s5c73m3_writeb(struct v4l2_subdev *sd,
+	unsigned short addr, unsigned short data)
+{
+	int err;
+	err = s5c73m3_i2c_check_status(sd);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5000);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, addr);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, data);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5080);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, 0x0001);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_set_mode(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_trace("E\n");
+
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		if (state->hdr_mode) {
+			err = s5c73m3_writeb(sd, S5C73M3_IMG_OUTPUT,
+				S5C73M3_HDR_OUTPUT);
+			CHECK_ERR(err);
+			cam_dbg("hdr ouput mode\n");
+		} else {
+			err = s5c73m3_writeb(sd, S5C73M3_IMG_OUTPUT,
+				S5C73M3_YUV_OUTPUT);
+			CHECK_ERR(err);
+			cam_dbg("yuv ouput mode\n");
+		}
+	} else {
+		if (state->hybrid_mode) {
+			err = s5c73m3_writeb(sd, S5C73M3_IMG_OUTPUT,
+				S5C73M3_HYBRID_OUTPUT);
+			CHECK_ERR(err);
+			cam_dbg("hybrid ouput mode\n");
+		} else {
+			err = s5c73m3_writeb(sd, S5C73M3_IMG_OUTPUT,
+				S5C73M3_INTERLEAVED_OUTPUT);
+			CHECK_ERR(err);
+			cam_dbg("interleaved ouput mode\n");
+		}
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/*
+ * v4l2_subdev_core_ops
+ */
+static int s5c73m3_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5c73m3_ctrls); i++) {
+		if (qc->id == s5c73m3_ctrls[i].id) {
+			qc->maximum = s5c73m3_ctrls[i].maximum;
+			qc->minimum = s5c73m3_ctrls[i].minimum;
+			qc->step = s5c73m3_ctrls[i].step;
+			qc->default_value = s5c73m3_ctrls[i].default_value;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int s5c73m3_set_antibanding(struct v4l2_subdev *sd, int val)
+{
+	int err = 0;
+	int antibanding_mode = 0;
+
+	switch (val) {
+	case ANTI_BANDING_OFF:
+		antibanding_mode = S5C73M3_FLICKER_NONE;
+		break;
+	case ANTI_BANDING_50HZ:
+		antibanding_mode = S5C73M3_FLICKER_AUTO_50HZ;
+		break;
+	case ANTI_BANDING_60HZ:
+		antibanding_mode = S5C73M3_FLICKER_AUTO_60HZ;
+		break;
+	case ANTI_BANDING_AUTO:
+	default:
+		antibanding_mode = S5C73M3_FLICKER_AUTO;
+		break;
+
+	}
+
+	err = s5c73m3_writeb(sd, S5C73M3_FLICKER_MODE, antibanding_mode);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_set_af_softlanding(struct v4l2_subdev *sd)
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	err = s5c73m3_writeb(sd, S5C73M3_AF_SOFTLANDING,
+		S5C73M3_AF_SOFTLANDING_ON);
+	CHECK_ERR(err);
+	cam_trace("X\n");
+
+	return 0;
+}
+
+static int s5c73m3_dump_fw(struct v4l2_subdev *sd)
+{
+	return 0;
+}
+
+static int s5c73m3_get_sensor_fw_binary(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	u16 read_val;
+	int i, rxSize;
+	int err = 0;
+	struct file *fp = NULL;
+	mm_segment_t old_fs;
+	long ret = 0;
+	char fw_path[25] = {0,};
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	udelay(400);
+
+	/*Check boot done*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x0C)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x0C) {
+		cam_err("boot fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/* Change I/O Driver Current in order to read from F-ROM */
+	err = s5c73m3_write(sd, 0x3010, 0x0120, 0x0820);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0124, 0x0820);
+	CHECK_ERR(err);
+
+	/*P,M,S and Boot Mode*/
+	err = s5c73m3_write(sd, 0x3010, 0x0014, 0x2146);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0010, 0x230C);
+	CHECK_ERR(err);
+
+	udelay(200);
+
+	/*Check SPI ready*/
+	for (i = 0; i < 300; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x230E)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x230E) {
+		cam_err("SPI not ready, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/*ARM reset*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFD);
+	CHECK_ERR(err);
+
+	/*remap*/
+	err = s5c73m3_write(sd, 0x3010, 0x00A4, 0x0183);
+	CHECK_ERR(err);
+
+	/*ARM go again*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	mdelay(200);
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	if (state->sensor_fw[0] == 'O') {
+		sprintf(fw_path, "/data/cfw/SlimISP_G%c.bin",
+			state->sensor_fw[1]);
+	} else if (state->sensor_fw[0] == 'S') {
+		sprintf(fw_path, "/data/cfw/SlimISP_Z%c.bin",
+			state->sensor_fw[1]);
+	} else {
+	sprintf(fw_path, "/data/cfw/SlimISP_%c%c.bin",
+		state->sensor_fw[0],
+		state->sensor_fw[1]);
+	}
+
+	fp = filp_open(fw_path, O_WRONLY|O_CREAT, 0644);
+	if (IS_ERR(fp) || fp == NULL) {
+		cam_err("failed to open %s, err %ld\n",
+			fw_path, PTR_ERR(fp));
+		err = -EINVAL;
+		goto out;
+	}
+
+	/* SPI Copy mode ready I2C CMD */
+	err = s5c73m3_writeb(sd, 0x0924, 0x0000);
+	CHECK_ERR(err);
+
+	rxSize = 64*1024;
+	mdelay(10);
+	s5c73m3_i2c_check_status(sd);
+
+	err = s5c73m3_spi_read((char *)&data_memory,
+		state->sensor_size, rxSize);
+	CHECK_ERR(err);
+
+	ret = vfs_write(fp, (char __user *)data_memory,
+		state->sensor_size, &fp->f_pos);
+
+	if (fp != NULL)
+		filp_close(fp, current->files);
+
+out:
+	set_fs(old_fs);
+
+	return err;
+}
+
+
+static int s5c73m3_get_sensor_fw_version(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	u16 read_val;
+	u16 sensor_fw;
+	u16 sensor_type;
+	u16 temp_buf;
+	int i;
+	int err = 0;
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	udelay(400);
+
+	/*Check boot done*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x0C)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x0C) {
+		cam_err("boot fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/* Change I/O Driver Current in order to read from F-ROM */
+	err = s5c73m3_write(sd, 0x3010, 0x0120, 0x0820);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0124, 0x0820);
+	CHECK_ERR(err);
+
+	/* Offset Setting */
+	err = s5c73m3_write(sd, 0x0001, 0x0418, 0x0008);
+	CHECK_ERR(err);
+
+	/*P,M,S and Boot Mode*/
+	err = s5c73m3_write(sd, 0x3010, 0x0014, 0x2146);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0010, 0x230C);
+	CHECK_ERR(err);
+
+	udelay(200);
+
+	/*Check SPI ready*/
+	for (i = 0; i < 300; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x230E)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x230E) {
+		cam_err("SPI not ready, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/*ARM reset*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFD);
+	CHECK_ERR(err);
+
+	/*remap*/
+	err = s5c73m3_write(sd, 0x3010, 0x00A4, 0x0183);
+	CHECK_ERR(err);
+
+	for (i = 0; i < 6; i++) {
+		err = s5c73m3_read(sd, 0x0000, 0x06+i*2, &sensor_type);
+		CHECK_ERR(err);
+		state->sensor_type[i*2] = sensor_type&0x00ff;
+		state->sensor_type[i*2+1] = (sensor_type&0xff00)>>8;
+#ifdef FEATURE_DEBUG_DUMP
+		cam_err("0x%x\n", sensor_type);
+#endif
+	}
+	state->sensor_type[i*2+2] = ' ';
+
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x0000, i*2, &sensor_fw);
+		CHECK_ERR(err);
+		state->sensor_fw[i*2] = sensor_fw&0x00ff;
+		state->sensor_fw[i*2+1] = (sensor_fw&0xff00)>>8;
+#ifdef FEATURE_DEBUG_DUMP
+		cam_err("0x%x\n", sensor_fw);
+#endif
+	}
+	state->sensor_fw[i*2+2] = ' ';
+
+	state->sensor_size = 0;
+	for (i = 0; i < 2; i++) {
+		err = s5c73m3_read(sd, 0x0000, 0x0014+i*2, &temp_buf);
+		state->sensor_size += temp_buf<<(i*16);
+		CHECK_ERR(err);
+	}
+
+	memcpy(sysfs_sensor_fw, state->sensor_fw,
+		sizeof(state->sensor_fw));
+	memcpy(sysfs_sensor_type, state->sensor_type,
+		sizeof(state->sensor_type));
+
+	cam_dbg("Sensor_version = %s, Sensor_Type = %s\n",
+		state->sensor_fw, state->sensor_type);
+
+	if ((state->sensor_fw[0] < 'A') || state->sensor_fw[0] > 'Z') {
+		cam_dbg("Sensor Version is invalid data\n");
+#ifdef FEATURE_DEBUG_DUMP
+		cam_err("0000h : ");
+		for (i = 0; i < 0x20; i++) {
+			err = s5c73m3_read(sd, 0x0000, i*2, &sensor_fw);
+			cam_err("%x", sensor_fw);
+
+			if (i == 0x10)
+				cam_err("\n 0010h : ");
+		}
+		mdelay(50);
+		memcpy(state->sensor_type,
+			state->sensor_fw,
+			0x100000); /* for kernel panic */
+#endif
+		err = -1;
+	}
+
+	return err;
+}
+
+static int s5c73m3_open_firmware_file(struct v4l2_subdev *sd,
+	const char *filename, u8 *buf, u16 offset, u16 size) {
+	struct file *fp;
+	int err = 0;
+	mm_segment_t old_fs;
+	long nread;
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(filename, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		err = -ENOENT;
+		goto out;
+	} else {
+		cam_dbg("%s is opened\n", filename);
+	}
+
+	err = vfs_llseek(fp, offset, SEEK_SET);
+	if (err < 0) {
+		cam_warn("failed to fseek, %d\n", err);
+		goto out;
+	}
+
+	nread = vfs_read(fp, (char __user *)buf, size, &fp->f_pos);
+
+	if (nread != size) {
+		cam_err("failed to read firmware file, %ld Bytes\n", nread);
+		err = -EIO;
+		goto out;
+	}
+out:
+	if (!IS_ERR(fp))
+		filp_close(fp, current->files);
+
+	set_fs(old_fs);
+
+	return err;
+}
+
+static int s5c73m3_compare_date(struct v4l2_subdev *sd,
+	int index1, int index2)
+{
+	u8 date1[5] = {0,};
+	u8 date2[5] = {0,};
+
+	strncpy((char *)&date1, &camfw_info[index1].ver[2], 4);
+	strncpy((char *)&date2, &camfw_info[index2].ver[2], 4);
+	cam_dbg("date1 = %s, date2 = %s\n, compare result = %d",
+		date1,
+		date2,
+		strcmp((char *)&date1, (char *)&date2));
+
+	return strcmp((char *)&date1, (char *)&date2);
+}
+
+static int s5c73m3_get_phone_fw_version(struct v4l2_subdev *sd)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	struct s5c73m3_state *state = to_state(sd);
+	const struct firmware *fw = {0, };
+	char fw_path[20] = {0,};
+	char fw_path_in_data[25] = {0,};
+	u8 *buf = NULL;
+	int err = 0;
+	int retVal = 0;
+	int fw_requested = 1;
+
+	if (state->sensor_fw[0] == 'O') {
+		sprintf(fw_path, "SlimISP_G%c.bin",
+			state->sensor_fw[1]);
+	} else if (state->sensor_fw[0] == 'S') {
+		sprintf(fw_path, "SlimISP_Z%c.bin",
+			state->sensor_fw[1]);
+	} else {
+		sprintf(fw_path, "SlimISP_%c%c.bin",
+			state->sensor_fw[0],
+			state->sensor_fw[1]);
+	}
+	sprintf(fw_path_in_data, "/data/cfw/%s",
+		fw_path);
+
+	buf = vmalloc(S5C73M3_FW_VER_LEN+1);
+	if (!buf) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	retVal = s5c73m3_open_firmware_file(sd,
+		S5C73M3_FW_PATH,
+		buf,
+		S5C73M3_FW_VER_FILE_CUR,
+		S5C73M3_FW_VER_LEN);
+	if (retVal >= 0) {
+		camfw_info[S5C73M3_SD_CARD].opened = 1;
+		memcpy(camfw_info[S5C73M3_SD_CARD].ver,
+			buf,
+			S5C73M3_FW_VER_LEN);
+		camfw_info[S5C73M3_SD_CARD]
+			.ver[S5C73M3_FW_VER_LEN+1] = ' ';
+		state->fw_index = S5C73M3_SD_CARD;
+		fw_requested = 0;
+	}
+request_fw:
+	if (fw_requested) {
+		/* check fw in data folder */
+		retVal = s5c73m3_open_firmware_file(sd,
+			fw_path_in_data,
+			buf,
+			S5C73M3_FW_VER_FILE_CUR,
+			S5C73M3_FW_VER_LEN);
+		if (retVal >= 0) {
+			camfw_info[S5C73M3_IN_DATA].opened = 1;
+			memcpy(camfw_info[S5C73M3_IN_DATA].ver,
+				buf,
+				S5C73M3_FW_VER_LEN);
+			camfw_info[S5C73M3_IN_DATA]
+				.ver[S5C73M3_FW_VER_LEN+1] = ' ';
+		}
+
+		/* check fw in system folder */
+		retVal = request_firmware(&fw, fw_path, dev);
+		if (retVal == 0) {
+			camfw_info[S5C73M3_IN_SYSTEM].opened = 1;
+			memcpy(camfw_info[S5C73M3_IN_SYSTEM].ver,
+				(u8 *)&fw->data[S5C73M3_FW_VER_FILE_CUR],
+				S5C73M3_FW_VER_LEN);
+		}
+
+		/* compare */
+		if (camfw_info[S5C73M3_IN_DATA].opened == 0 &&
+			camfw_info[S5C73M3_IN_SYSTEM].opened == 1)  {
+			state->fw_index = S5C73M3_IN_SYSTEM;
+		} else if (camfw_info[S5C73M3_IN_DATA].opened == 1 &&
+			camfw_info[S5C73M3_IN_SYSTEM].opened == 0) {
+			state->fw_index = S5C73M3_IN_DATA;
+		} else if (camfw_info[S5C73M3_IN_DATA].opened == 1 &&
+			camfw_info[S5C73M3_IN_SYSTEM].opened == 1) {
+			retVal = s5c73m3_compare_date(sd,
+				S5C73M3_IN_DATA,
+				S5C73M3_IN_SYSTEM);
+			if (retVal <= 0) {
+				/*unlink(&fw_path_in_data);*/
+				state->fw_index = S5C73M3_IN_SYSTEM;
+			} else {
+				state->fw_index = S5C73M3_IN_DATA;
+			}
+		} else {
+			cam_dbg("get new fw to F-ROM : %s Version\n",
+				state->sensor_fw);
+			if (fw != NULL)
+				release_firmware(fw);
+
+			retVal = state->pdata->is_isp_reset();
+			CHECK_ERR(retVal);
+			retVal = s5c73m3_set_timing_register_for_vdd(sd);
+			CHECK_ERR(retVal);
+			retVal = s5c73m3_get_sensor_fw_binary(sd);
+			CHECK_ERR(retVal);
+			goto request_fw;
+		}
+
+		memcpy(state->phone_fw,
+			camfw_info[state->fw_index].ver,
+			S5C73M3_FW_VER_LEN);
+	}
+	memcpy(state->phone_fw,
+		camfw_info[state->fw_index].ver,
+		S5C73M3_FW_VER_LEN);
+	state->phone_fw[S5C73M3_FW_VER_LEN+1] = ' ';
+
+	memcpy(sysfs_phone_fw, state->phone_fw, sizeof(state->phone_fw));
+	cam_dbg("Phone_version = %s(index=%d)\n",
+		state->phone_fw, state->fw_index);
+
+out:
+	if (buf != NULL)
+		vfree(buf);
+
+	if (fw_requested)
+		release_firmware(fw);
+
+	return err;
+}
+
+static int s5c73m3_update_camerafw_to_FROM(struct v4l2_subdev *sd)
+{
+	int err;
+	int index = 0;
+	u16 status = 0;
+
+	do {
+		/* stauts 0 : not ready ISP */
+		if (status == 0) {
+			err = s5c73m3_writeb(sd, 0x0906, 0x0000);
+			CHECK_ERR(err);
+		}
+
+		err = s5c73m3_read(sd, 0x0009, 0x5906, &status);
+		/* Success : 0x05, Fail : 0x07 , Progressing : 0xFFFF*/
+		if (status == 0x0005 ||
+			status == 0x0007)
+			break;
+
+		index++;
+		msleep(20);
+	} while (index < 500);	/* 10 sec */
+
+
+	if (status == 0x0007)
+		return -1;
+	else
+		return 0;
+}
+
+static int s5c73m3_SPI_booting_by_ISP(struct v4l2_subdev *sd)
+{
+	u16 read_val;
+	int i;
+	int err = 0;
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	udelay(400);
+
+	/*Check boot done*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x0C)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x0C) {
+		cam_err("boot fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/* Change I/O Driver Current in order to read from F-ROM */
+	err = s5c73m3_write(sd, 0x3010, 0x0120, 0x0820);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0124, 0x0820);
+	CHECK_ERR(err);
+
+	/*P,M,S and Boot Mode*/
+	err = s5c73m3_write(sd, 0x3010, 0x0014, 0x2146);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0010, 0x230C);
+	CHECK_ERR(err);
+
+	udelay(200);
+
+	/*Check SPI ready*/
+	for (i = 0; i < 300; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x230E)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x230E) {
+		cam_err("SPI not ready, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/*ARM reset*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFD);
+	CHECK_ERR(err);
+
+	/*remap*/
+	err = s5c73m3_write(sd, 0x3010, 0x00A4, 0x0183);
+	CHECK_ERR(err);
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_check_fw_date(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	u8 sensor_date[5] = {0,};
+	u8 phone_date[5] = {0,};
+
+	strncpy((char *)&sensor_date, &state->sensor_fw[2], 4);
+	strncpy((char *)&phone_date, (const char *)&state->phone_fw[2], 4);
+	cam_dbg("Sensor_date = %s, Phone_date = %s\n, compare result = %d",
+		sensor_date,
+		phone_date,
+		strcmp((char *)&sensor_date, (char *)&phone_date));
+
+	return strcmp((char *)&sensor_date, (char *)&phone_date);
+}
+
+static int s5c73m3_check_fw(struct v4l2_subdev *sd, int download)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err, i;
+	int retVal;
+
+	if (!download) {
+		for (i = 0; i < S5C73M3_PATH_MAX; i++)
+			camfw_info[i].opened = 0;
+
+		err = s5c73m3_get_sensor_fw_version(sd);
+		CHECK_ERR(err);
+		s5c73m3_get_af_cal_version(sd);
+		err = s5c73m3_get_phone_fw_version(sd);
+		CHECK_ERR(err);
+	}
+
+	retVal = s5c73m3_check_fw_date(sd);
+	err = state->pdata->is_isp_reset();
+	CHECK_ERR(err);
+	err = s5c73m3_set_timing_register_for_vdd(sd);
+	CHECK_ERR(err);
+
+	/* retVal = 0 : Same Version
+	    retVal < 0 : Phone Version is latest Version than sensorFW.
+	    retVal > 0 : Sensor Version is latest version than phoenFW. */
+	if (retVal <= 0 || download) {
+		cam_dbg("Loading From PhoneFW......\n");
+		err = s5c73m3_SPI_booting(sd);
+		CHECK_ERR(err);
+
+		if (download) {
+			err = s5c73m3_update_camerafw_to_FROM(sd);
+			CHECK_ERR(err);
+		}
+	} else {
+		cam_dbg("Loading From SensorFW......\n");
+#if 0
+		err = s5c73m3_SPI_booting_by_ISP(sd);
+		CHECK_ERR(err);
+#else
+		err = s5c73m3_get_sensor_fw_binary(sd);
+		CHECK_ERR(err);
+#endif
+	}
+
+	return 0;
+}
+
+static int s5c73m3_set_sensor_mode(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case SENSOR_CAMERA:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_AUTO_MODE_AE_SET);
+		CHECK_ERR(err);
+		break;
+
+	case SENSOR_MOVIE:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_FIXED_30FPS);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = SENSOR_CAMERA;
+		goto retry;
+	}
+	state->sensor_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_flash(struct v4l2_subdev *sd, int val, int recording)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case FLASH_MODE_OFF:
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_MODE,
+			S5C73M3_FLASH_MODE_OFF);
+		CHECK_ERR(err);
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_OFF);
+		CHECK_ERR(err);
+		break;
+
+	case FLASH_MODE_AUTO:
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_OFF);
+		CHECK_ERR(err);
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_MODE,
+			S5C73M3_FLASH_MODE_AUTO);
+		CHECK_ERR(err);
+		break;
+
+	case FLASH_MODE_ON:
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_OFF);
+		CHECK_ERR(err);
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_MODE,
+			S5C73M3_FLASH_MODE_ON);
+		CHECK_ERR(err);
+		break;
+
+	case FLASH_MODE_TORCH:
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_MODE,
+			S5C73M3_FLASH_MODE_OFF);
+		CHECK_ERR(err);
+		err = s5c73m3_writeb(sd, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_ON);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = FLASH_MODE_OFF;
+		goto retry;
+	}
+	state->flash_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_iso(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	int err;
+	cam_dbg("E, value %d\n", ctrl->value);
+
+retry:
+	switch (ctrl->value) {
+	case ISO_AUTO:
+		err = s5c73m3_writeb(sd, S5C73M3_ISO,
+			S5C73M3_ISO_AUTO);
+		CHECK_ERR(err);
+		break;
+
+	case ISO_100:
+		err = s5c73m3_writeb(sd, S5C73M3_ISO,
+			S5C73M3_ISO_100);
+		CHECK_ERR(err);
+		break;
+
+	case ISO_200:
+		err = s5c73m3_writeb(sd, S5C73M3_ISO,
+			S5C73M3_ISO_200);
+		CHECK_ERR(err);
+		break;
+
+	case ISO_400:
+		err = s5c73m3_writeb(sd, S5C73M3_ISO,
+			S5C73M3_ISO_400);
+		CHECK_ERR(err);
+		break;
+
+	case ISO_800:
+		err = s5c73m3_writeb(sd, S5C73M3_ISO,
+			S5C73M3_ISO_800);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", ctrl->value);
+		ctrl->value = ISO_AUTO;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_metering(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case METERING_CENTER:
+		err = s5c73m3_writeb(sd, S5C73M3_METER,
+			S5C73M3_METER_CENTER);
+		CHECK_ERR(err);
+		break;
+
+	case METERING_SPOT:
+		err = s5c73m3_writeb(sd, S5C73M3_METER,
+			S5C73M3_METER_SPOT);
+		CHECK_ERR(err);
+		break;
+
+	case METERING_MATRIX:
+		err = s5c73m3_writeb(sd, S5C73M3_METER,
+			S5C73M3_METER_AVERAGE);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = METERING_CENTER;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_exposure(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	int err;
+	cam_dbg("E, value %d\n", ctrl->value);
+
+	if (ctrl->value < -4 || ctrl->value > 4) {
+		cam_warn("invalid value, %d\n", ctrl->value);
+		ctrl->value = 0;
+	}
+	err = s5c73m3_writeb(sd, S5C73M3_EV,
+		ctrl->value + 4);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_contrast(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	int err;
+	int contrast = 0;
+	int temp_contrast = 0;
+	cam_dbg("E, value %d\n", ctrl->value);
+
+	if (ctrl->value < 0 || ctrl->value > 4) {
+		cam_warn("invalid value, %d\n", ctrl->value);
+		ctrl->value = 2;
+	}
+	temp_contrast = ctrl->value - 2;
+	if (temp_contrast < 0)
+		contrast = (temp_contrast * (-1)) + 2;
+	else
+		contrast = temp_contrast;
+	err = s5c73m3_writeb(sd, S5C73M3_CONTRAST,
+		contrast);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_whitebalance(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case WHITE_BALANCE_AUTO:
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_MODE,
+			S5C73M3_AWB_MODE_AUTO);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_SUNNY:
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_MODE,
+			S5C73M3_AWB_MODE_DAYLIGHT);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_CLOUDY:
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_MODE,
+			S5C73M3_AWB_MODE_CLOUDY);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_TUNGSTEN:
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_MODE,
+			S5C73M3_AWB_MODE_INCANDESCENT);
+		CHECK_ERR(err);
+		break;
+
+	case WHITE_BALANCE_FLUORESCENT:
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_MODE,
+			S5C73M3_AWB_MODE_FLUORESCENT1);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = WHITE_BALANCE_AUTO;
+		goto retry;
+	}
+
+	state->wb_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_scene_mode(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case SCENE_MODE_NONE:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_NONE);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_PORTRAIT:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_PORTRAIT);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_LANDSCAPE:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_LANDSCAPE);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_SPORTS:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_SPORTS);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_PARTY_INDOOR:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_INDOOR);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_BEACH_SNOW:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_BEACH);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_SUNSET:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_SUNSET);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_DUSK_DAWN:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_DAWN);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_FALL_COLOR:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_FALL);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_NIGHTSHOT:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_NIGHT);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_BACK_LIGHT:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_AGAINSTLIGHT);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_FIREWORKS:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_FIRE);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_TEXT:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_TEXT);
+		CHECK_ERR(err);
+		break;
+
+	case SCENE_MODE_CANDLE_LIGHT:
+		err = s5c73m3_writeb(sd, S5C73M3_SCENE_MODE,
+			S5C73M3_SCENE_MODE_CANDLE);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = SCENE_MODE_NONE;
+		goto retry;
+	}
+
+	state->scene_mode = val;
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_capture_firework(struct v4l2_subdev *sd)
+{
+	int err = 0;
+
+	cam_dbg("E, capture_firework\n");
+
+	err = s5c73m3_writeb(sd, S5C73M3_FIREWORK_CAPTURE, 0x0001);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_capture_nightshot(struct v4l2_subdev *sd)
+{
+	int err = 0;
+
+	cam_dbg("E, capture_nightshot\n");
+
+	err = s5c73m3_writeb(sd, S5C73M3_NIGHTSHOT_CAPTURE, 0x0001);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_set_effect(struct v4l2_subdev *sd, int val)
+{
+	int err = 0;
+	int num_entries = 0;
+	int i = 0;
+	cam_dbg("E, value %d\n", val);
+
+	if (val < IMAGE_EFFECT_BASE || val > IMAGE_EFFECT_MAX)
+		val = IMAGE_EFFECT_NONE;
+
+	num_entries = ARRAY_SIZE(s5c73m3_effects);
+	for (i = 0; i < num_entries; i++) {
+		if (val == s5c73m3_effects[i].index) {
+			err = s5c73m3_writeb(sd, S5C73M3_IMAGE_EFFECT,
+				s5c73m3_effects[i].reg_val);
+			CHECK_ERR(err);
+			break;
+		}
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_wdr(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case WDR_OFF:
+		err = s5c73m3_writeb(sd, S5C73M3_WDR,
+			S5C73M3_WDR_OFF);
+		CHECK_ERR(err);
+		break;
+
+	case WDR_ON:
+		err = s5c73m3_writeb(sd, S5C73M3_WDR,
+			S5C73M3_WDR_ON);
+		CHECK_ERR(err);
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = WDR_OFF;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_antishake(struct v4l2_subdev *sd, int val)
+{
+	int err = 0;
+	cam_dbg("E, value %d\n", val);
+
+	if (val) {
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_ANTI_SHAKE);
+		CHECK_ERR(err);
+	} else {
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_AUTO_MODE_AE_SET);
+		CHECK_ERR(err);
+	}
+	return err;
+}
+
+static int s5c73m3_get_af_cal_version(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	u32 data = 0;
+	u16 status = 0;
+	int err = 0;
+
+	/* Calibration Device */
+	err = s5c73m3_read(sd, 0x0009, 0x300C, &status);
+	CHECK_ERR(err);
+	data = status;
+
+	status = 0;
+	err = s5c73m3_read(sd, 0x0009, 0x300E, &status);
+	CHECK_ERR(err);
+	data += status<<16;
+	state->cal_device = data;
+
+	/* Calibration DLL Version */
+	status = 0;
+	data = 0;
+	err = s5c73m3_read(sd, 0x0009, 0x4FF8, &status);
+	CHECK_ERR(err);
+	data = status;
+
+	status = 0;
+	err = s5c73m3_read(sd, 0x0009, 0x4FFA, &status);
+	CHECK_ERR(err);
+	data += status<<16;
+	state->cal_dll = data;
+
+	cam_dbg("Cal_Device = 0x%x, Cal_DLL = 0x%x\n",
+		state->cal_device, state->cal_dll);
+	return 0;
+}
+
+static int s5c73m3_stop_af_lens(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+	if (val == CAF_START) {
+		if (state->focus.mode == FOCUS_MODE_CONTINOUS_VIDEO) {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_MOVIE_CAF_START);
+
+		} else {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_PREVIEW_CAF_START);
+		}
+	} else {
+		err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+			S5C73M3_AF_CON_STOP);
+	}
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+
+	return err;
+}
+
+static int s5c73m3_set_af(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("%s, mode %#x\n", val ? "start" : "stop", state->focus.mode);
+
+	state->focus.status = 0;
+
+	if (val) {
+		state->isflash = S5C73M3_ISNEED_FLASH_ON;
+
+		if (state->focus.mode == FOCUS_MODE_TOUCH)
+			err = s5c73m3_set_touch_auto_focus(sd);
+		else
+			err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+				S5C73M3_AF_CON_START);
+	} else {
+		err = s5c73m3_writeb(sd, S5C73M3_STILL_MAIN_FLASH
+				, S5C73M3_STILL_MAIN_FLASH_CANCEL);
+		err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+			S5C73M3_AF_CON_STOP);
+		state->isflash = S5C73M3_ISNEED_FLASH_UNDEFINED;
+	}
+
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return err;
+}
+
+static int s5c73m3_get_pre_flash(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	int err = 0;
+	u16 pre_flash = false;
+
+	s5c73m3_read(sd, 0x0009, S5C73M3_STILL_PRE_FLASH | 0x5000, &pre_flash);
+	ctrl->value = pre_flash;
+	return err;
+}
+
+static int s5c73m3_get_af_result(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+	u16 af_status = S5C73M3_AF_STATUS_UNFOCUSED;
+	/*u16 temp_status = 0;*/
+
+	err = s5c73m3_read(sd, 0x0009, S5C73M3_AF_STATUS, &af_status);
+
+	/*err = s5c73m3_read(sd, 0x0009, 0x5840, &temp_status);*/
+
+	switch (af_status) {
+	case S5C73M3_AF_STATUS_FOCUSING:
+	case S5C73M3_CAF_STATUS_FOCUSING:
+	case S5C73M3_CAF_STATUS_FIND_SEARCHING_DIR:
+	case S5C73M3_AF_STATUS_INVALID:
+		ctrl->value = CAMERA_AF_STATUS_IN_PROGRESS;
+		break;
+
+	case S5C73M3_AF_STATUS_FOCUSED:
+	case S5C73M3_CAF_STATUS_FOCUSED:
+		ctrl->value = CAMERA_AF_STATUS_SUCCESS;
+		break;
+
+	case S5C73M3_CAF_STATUS_UNFOCUSED:
+	case S5C73M3_AF_STATUS_UNFOCUSED:
+	default:
+		ctrl->value = CAMERA_AF_STATUS_FAIL;
+		break;
+	}
+
+	state->focus.status = af_status;
+
+	/*cam_dbg("af_status = %d, frame_cnt = %d\n",
+		state->focus.status, temp_status);*/
+	return err;
+}
+
+static int s5c73m3_set_af_mode(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case FOCUS_MODE_AUTO:
+	case FOCUS_MODE_INFINITY:
+		if (state->focus.mode != FOCUS_MODE_CONTINOUS_PICTURE) {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_NORMAL);
+			CHECK_ERR(err);
+		} else {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+				S5C73M3_AF_CON_STOP);
+			CHECK_ERR(err);
+		}
+
+		state->focus.mode = val;
+		state->caf_mode = S5C73M3_AF_MODE_NORMAL;
+		break;
+
+	case FOCUS_MODE_MACRO:
+		if (state->focus.mode != FOCUS_MODE_CONTINOUS_PICTURE_MACRO) {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_MACRO);
+			CHECK_ERR(err);
+		} else {
+			err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+				S5C73M3_AF_CON_STOP);
+			CHECK_ERR(err);
+		}
+
+		state->focus.mode = val;
+		state->caf_mode = S5C73M3_AF_MODE_MACRO;
+		break;
+
+	case FOCUS_MODE_CONTINOUS_PICTURE:
+		state->isflash = S5C73M3_ISNEED_FLASH_UNDEFINED;
+
+		if (val != state->focus.mode &&
+			state->caf_mode != S5C73M3_AF_MODE_NORMAL) {
+			state->focus.mode = val;
+
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_NORMAL);
+			CHECK_ERR(err);
+			state->caf_mode = S5C73M3_AF_MODE_NORMAL;
+		}
+
+		err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+		S5C73M3_AF_MODE_PREVIEW_CAF_START);
+		CHECK_ERR(err);
+		break;
+
+	case FOCUS_MODE_CONTINOUS_PICTURE_MACRO:
+		state->isflash = S5C73M3_ISNEED_FLASH_UNDEFINED;
+		if (val != state->focus.mode &&
+			state->caf_mode != S5C73M3_AF_MODE_MACRO) {
+			state->focus.mode = val;
+
+			err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+				S5C73M3_AF_MODE_MACRO);
+			state->caf_mode = S5C73M3_AF_MODE_MACRO;
+			CHECK_ERR(err);
+		}
+
+		err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+		S5C73M3_AF_MODE_PREVIEW_CAF_START);
+		CHECK_ERR(err);
+		break;
+
+	case FOCUS_MODE_CONTINOUS_VIDEO:
+		state->focus.mode = val;
+
+		err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+			S5C73M3_AF_MODE_MOVIE_CAF_START);
+		CHECK_ERR(err);
+		break;
+
+	case FOCUS_MODE_FACEDETECT:
+		state->focus.mode = val;
+		break;
+
+	case FOCUS_MODE_TOUCH:
+		state->focus.mode = val;
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = FOCUS_MODE_AUTO;
+		goto retry;
+	}
+
+	state->focus.mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_touch_auto_focus(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+
+	err = s5c73m3_i2c_write(sd, 0xfcfc, 0x3310);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, S5C73M3_AF_TOUCH_POSITION);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->focus.pos_x);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->focus.pos_y);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->real_preview_width);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->real_preview_height);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5000);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, 0x0E0A);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, 0x0000);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5080);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, 0x0001);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int s5c73m3_set_zoom(struct v4l2_subdev *sd, int value)
+{
+	int err;
+	cam_dbg("E, value %d\n", value);
+
+retry:
+	if (value < 0 || value > 30) {
+		cam_warn("invalid value, %d\n", value);
+		value = 0;
+		goto retry;
+	}
+	err = s5c73m3_writeb(sd, S5C73M3_ZOOM_STEP, value);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_set_jpeg_quality(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	int val = ctrl->value, err;
+	cam_dbg("E, value %d\n", val);
+
+	if (val <= 65)		/* Normal */
+		err = s5c73m3_writeb(sd, S5C73M3_IMAGE_QUALITY,
+			S5C73M3_IMAGE_QUALITY_NORMAL);
+	else if (val <= 75)	/* Fine */
+		err = s5c73m3_writeb(sd, S5C73M3_IMAGE_QUALITY,
+			S5C73M3_IMAGE_QUALITY_FINE);
+	else			/* Superfine */
+		err = s5c73m3_writeb(sd, S5C73M3_IMAGE_QUALITY,
+			S5C73M3_IMAGE_QUALITY_SUPERFINE);
+
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_aeawb_lock_unlock(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+	int ae_lock = val & 0x1;
+	int awb_lock = (val & 0x2) >> 1;
+	int ae_lock_changed =
+		~(ae_lock & state->ae_lock) & (ae_lock | state->ae_lock);
+	int awb_lock_changed =
+		~(awb_lock & state->awb_lock) & (awb_lock | state->awb_lock);
+
+	if (ae_lock_changed) {
+		cam_dbg("ae lock - %s\n", ae_lock ? "true" : "false");
+		err = s5c73m3_writeb(sd, S5C73M3_AE_CON,
+				ae_lock ? S5C73M3_AE_STOP : S5C73M3_AE_START);
+		CHECK_ERR(err);
+		state->ae_lock = ae_lock;
+	}
+	if (awb_lock_changed &&
+		state->wb_mode == WHITE_BALANCE_AUTO) {
+		cam_dbg("awb lock - %s\n", awb_lock ? "true" : "false");
+		err = s5c73m3_writeb(sd, S5C73M3_AWB_CON,
+			awb_lock ? S5C73M3_AWB_STOP : S5C73M3_AWB_START);
+		CHECK_ERR(err);
+		state->awb_lock = awb_lock;
+	}
+
+	return 0;
+}
+
+static int s5c73m3_start_capture(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+	u16 isneed_flash = false;
+	u16 pre_flash = false;
+
+	s5c73m3_read(sd, 0x0009, S5C73M3_STILL_PRE_FLASH | 0x5000, &pre_flash);
+
+	if (state->flash_mode == FLASH_MODE_ON) {
+		if (!pre_flash) {
+			err = s5c73m3_writeb(sd, S5C73M3_STILL_PRE_FLASH
+					, S5C73M3_STILL_PRE_FLASH_FIRE);
+			msleep(100);
+		}
+		err = s5c73m3_writeb(sd, S5C73M3_STILL_MAIN_FLASH
+			, S5C73M3_STILL_MAIN_FLASH_FIRE);
+	} else if (state->flash_mode == FLASH_MODE_AUTO) {
+		if (pre_flash) {
+			err = s5c73m3_writeb(sd, S5C73M3_STILL_MAIN_FLASH
+					, S5C73M3_STILL_MAIN_FLASH_FIRE);
+		} else if (state->isflash != S5C73M3_ISNEED_FLASH_ON) {
+			err = s5c73m3_read(sd, 0x0009,
+				S5C73M3_AE_ISNEEDFLASH | 0x5000, &isneed_flash);
+			if (isneed_flash) {
+				err = s5c73m3_writeb(sd, S5C73M3_STILL_PRE_FLASH
+						, S5C73M3_STILL_PRE_FLASH_FIRE);
+				msleep(100);
+				err = s5c73m3_writeb(sd,
+						S5C73M3_STILL_MAIN_FLASH,
+						S5C73M3_STILL_MAIN_FLASH_FIRE);
+			}
+		}
+	}
+
+	state->isflash = S5C73M3_ISNEED_FLASH_UNDEFINED;
+
+	return 0;
+}
+
+static int s5c73m3_set_auto_bracket_mode(struct v4l2_subdev *sd)
+{
+	int err = 0;
+
+		err = s5c73m3_writeb(sd, S5C73M3_AE_AUTO_BRAKET,
+		S5C73M3_AE_AUTO_BRAKET_EV20);
+		CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_set_frame_rate(struct v4l2_subdev *sd, int fps)
+{
+	int err = 0;
+	struct s5c73m3_state *state = to_state(sd);
+
+	if (!state->stream_enable) {
+		state->fps = fps;
+		return 0;
+	}
+
+	switch (fps) {
+	case 30:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_FIXED_30FPS); /* 30fps */
+		break;
+	case 20:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_FIXED_20FPS); /* 20fps */
+		break;
+	case 15:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_FIXED_15FPS); /* 15fps */
+		break;
+	case 10:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_FIXED_10FPS); /* 10fps */
+		break;
+	default:
+		err = s5c73m3_writeb(sd, S5C73M3_AE_MODE,
+			S5C73M3_AUTO_MODE_AE_SET); /* auto */
+		break;
+	}
+	return err;
+}
+
+static int s5c73m3_set_face_zoom(struct v4l2_subdev *sd, int val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+
+	cam_dbg("s5c73m3_set_face_zoom\n");
+
+	err = s5c73m3_writeb(sd, S5C73M3_AF_CON,
+		S5C73M3_AF_CON_STOP);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0xfcfc, 0x3310);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, S5C73M3_AF_TOUCH_POSITION);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->focus.pos_x);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->focus.pos_y);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->preview->width);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, state->preview->height);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5000);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, S5C73M3_AF_FACE_ZOOM);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, val); /*0:reset, 1:Start*/
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0054, 0x5080);
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_write(sd, 0x0F14, 0x0001);
+	CHECK_ERR(err);
+
+	udelay(400);
+	err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+		S5C73M3_AF_MODE_PREVIEW_CAF_START);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+
+static int s5c73m3_set_face_detection(struct v4l2_subdev *sd, int val)
+{
+	int err;
+	cam_dbg("E, value %d\n", val);
+
+retry:
+	switch (val) {
+	case FACE_DETECTION_ON:
+		err = s5c73m3_writeb(sd, S5C73M3_FACE_DET,
+			S5C73M3_FACE_DET_ON);
+		CHECK_ERR(err);
+
+		err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+		S5C73M3_AF_MODE_PREVIEW_CAF_START);
+		CHECK_ERR(err);
+
+		break;
+
+	case FACE_DETECTION_OFF:
+		err = s5c73m3_writeb(sd, S5C73M3_FACE_DET,
+			S5C73M3_FACE_DET_OFF);
+		CHECK_ERR(err);
+
+		err = s5c73m3_writeb(sd, S5C73M3_AF_MODE,
+		S5C73M3_AF_MODE_PREVIEW_CAF_START);
+		CHECK_ERR(err);
+
+		break;
+
+	default:
+		cam_warn("invalid value, %d\n", val);
+		val = FACE_DETECTION_OFF;
+		goto retry;
+	}
+
+	cam_trace("X\n");
+	return 0;
+
+}
+
+static int s5c73m3_set_hybrid_capture(struct v4l2_subdev *sd)
+{
+	int err;
+	cam_trace("E\n");
+
+	err = s5c73m3_writeb(sd, S5C73M3_HYBRID_CAPTURE, 1);
+
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_get_lux(struct v4l2_subdev *sd,
+	struct v4l2_control *ctrl)
+{
+	int err = 0;
+	u16 lux_val = 0;
+
+	err = s5c73m3_read(sd, 0x0009, 0x5C88, &lux_val);
+	ctrl->value = lux_val;
+
+	return err;
+}
+
+static int s5c73m3_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+
+	printk(KERN_INFO "id %d, value %d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if (unlikely(state->isp.bad_fw && ctrl->id != V4L2_CID_CAM_UPDATE_FW)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_FRAME_RATE:
+		err = s5c73m3_set_frame_rate(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FACE_DETECTION:
+		err = s5c73m3_set_face_detection(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FACE_ZOOM:
+		err = s5c73m3_set_face_zoom(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_UPDATE_FW:
+		if (ctrl->value == FW_MODE_DUMP)
+			err = s5c73m3_dump_fw(sd);
+		else if (ctrl->value == FW_MODE_UPDATE)
+			err = s5c73m3_check_fw(sd, 1);
+		else
+			err = 0;
+
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = s5c73m3_set_sensor_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		err = s5c73m3_set_flash(sd, ctrl->value, 0);
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		err = s5c73m3_set_antibanding(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ISO:
+		err = s5c73m3_set_iso(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_METERING:
+		err = s5c73m3_set_metering(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = s5c73m3_set_exposure(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CONTRAST:
+		err = s5c73m3_set_contrast(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		err = s5c73m3_set_whitebalance(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = s5c73m3_set_scene_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_EFFECT:
+		err = s5c73m3_set_effect(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_WDR:
+		err = s5c73m3_set_wdr(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_SHAKE:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			err = s5c73m3_set_antishake(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_DEFAULT_FOCUS_POSITION:
+		/*err = s5c73m3_set_af_mode(sd, state->focus.mode);*/
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		/*state->focus.mode = ctrl->value;*/
+		err = s5c73m3_set_af_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		state->real_preview_width = ((u32)ctrl->value >> 20) & 0xFFF;
+		state->real_preview_height = ((u32)ctrl->value >> 8) & 0xFFF;
+
+		err = s5c73m3_set_af(sd, (u32)ctrl->value & 0x000F);
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		state->focus.pos_x = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		state->focus.pos_y = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_ZOOM:
+		err = s5c73m3_set_zoom(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_JPEG_QUALITY:
+		err = s5c73m3_set_jpeg_quality(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_CAPTURE:
+		err = s5c73m3_start_capture(sd, ctrl->value);
+
+		if (state->scene_mode == SCENE_MODE_FIREWORKS)
+			err = s5c73m3_capture_firework(sd);
+		else if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+			err = s5c73m3_capture_nightshot(sd);
+		break;
+
+	case V4L2_CID_CAMERA_HDR:
+		state->hdr_mode = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_HYBRID:
+		state->hybrid_mode = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_HYBRID_CAPTURE:
+		err = s5c73m3_set_hybrid_capture(sd);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_JPEG_RESOLUTION:
+		state->jpeg_width = (u32)ctrl->value >> 16;
+		state->jpeg_height = (u32)ctrl->value & 0x0FFFF;
+		break;
+
+	case V4L2_CID_CAMERA_AEAWB_LOCK_UNLOCK:
+		err = s5c73m3_aeawb_lock_unlock(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CAF_START_STOP:
+		err = s5c73m3_stop_af_lens(sd, ctrl->value);
+		break;
+
+	default:
+		cam_err("no such control id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+		/*err = -ENOIOCTLCMD;*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d, value %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+	return err;
+}
+
+static int s5c73m3_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_CAPTURE:
+		err = s5c73m3_get_pre_flash(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		err = s5c73m3_get_af_result(sd, ctrl);
+		break;
+
+	case V4L2_CID_CAM_JPEG_MEMSIZE:
+		ctrl->value = 0xA00000; /*interleaved data size*/
+		break;
+
+	case V4L2_CID_CAMERA_GET_LUX:
+		err = s5c73m3_get_lux(sd, ctrl);
+		break;
+
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/*err = -ENOIOCTLCMD*/
+		err = 0;
+		break;
+	}
+
+	if (err < 0 && err != -ENOIOCTLCMD)
+		cam_err("failed, id %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	return err;
+}
+
+
+static int s5c73m3_g_ext_ctrl(struct v4l2_subdev *sd,
+	struct v4l2_ext_control *ctrl)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_SENSOR_FW_VER:
+		strcpy(ctrl->string, state->phone_fw);
+		break;
+
+	default:
+		cam_err("no such control id %d\n",
+			ctrl->id - V4L2_CID_CAMERA_CLASS_BASE);
+		/*err = -ENOIOCTLCMD*/
+		break;
+	}
+
+	return err;
+}
+
+static int s5c73m3_g_ext_ctrls(struct v4l2_subdev *sd,
+	struct v4l2_ext_controls *ctrls)
+{
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int i, err = 0;
+
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		err = s5c73m3_g_ext_ctrl(sd, ctrl);
+		if (err) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+	return err;
+}
+
+#ifndef CONFIG_VIDEO_S5C73M3_SPI
+int s5c73m3_spi_write(const u8 *addr, const int len, const int txSize)
+{ return 0; }
+#endif
+
+static int s5c73m3_load_fw(struct v4l2_subdev *sd)
+{
+	struct device *dev = sd->v4l2_dev->dev;
+	struct s5c73m3_state *state = to_state(sd);
+	const struct firmware *fw;
+	char fw_path[20] = {0,};
+	char fw_path_in_data[25] = {0,};
+	u8 *buf = NULL;
+	int err = 0;
+	int txSize = 0;
+
+	struct file *fp = NULL;
+	mm_segment_t old_fs;
+	long fsize = 0, nread;
+
+	if (state->sensor_fw[0] == 'O') {
+		sprintf(fw_path, "SlimISP_G%c.bin",
+			state->sensor_fw[1]);
+	} else if (state->sensor_fw[0] == 'S') {
+		sprintf(fw_path, "SlimISP_Z%c.bin",
+			state->sensor_fw[1]);
+	} else {
+		sprintf(fw_path, "SlimISP_%c%c.bin",
+			state->sensor_fw[0],
+			state->sensor_fw[1]);
+	}
+	sprintf(fw_path_in_data, "/data/cfw/%s",
+		fw_path);
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	if (state->fw_index == S5C73M3_SD_CARD ||
+		state->fw_index == S5C73M3_IN_DATA) {
+
+		if (state->fw_index == S5C73M3_SD_CARD)
+			fp = filp_open(S5C73M3_FW_PATH, O_RDONLY, 0);
+		else
+			fp = filp_open(fw_path_in_data, O_RDONLY, 0);
+		if (IS_ERR(fp))
+			goto out;
+		else
+			cam_dbg("%s is opened\n",
+			state->fw_index == S5C73M3_SD_CARD ?
+			S5C73M3_FW_PATH : fw_path_in_data);
+
+		fsize = fp->f_path.dentry->d_inode->i_size;
+
+		nread = vfs_read(fp, (char __user *)data_memory,
+			fsize, &fp->f_pos);
+		if (nread != fsize) {
+			cam_err("failed to read firmware file_2\n");
+			err = -EIO;
+			goto out;
+		}
+		set_fs(old_fs);
+	} else {
+		set_fs(old_fs);
+		err = request_firmware(&fw, fw_path, dev);
+		if (err != 0) {
+			/*cam_err("request_firmware falied\n");*/
+			err = -EINVAL;
+			goto out;
+		}
+
+		/*cam_dbg("start, size %d Bytes\n", fw->size);*/
+		buf = (u8 *)fw->data;
+		fsize = fw->size;
+	}
+
+	txSize = 60*1024; /*60KB*/
+
+	if (state->fw_index != S5C73M3_IN_SYSTEM) {
+		err = s5c73m3_spi_write((char *)&data_memory,
+			fsize, txSize);
+		if (err < 0) {
+			cam_err("s5c73m3_spi_write falied\n");
+			goto out;
+		}
+	} else {
+		err = s5c73m3_spi_write((char *)buf, fsize, txSize);
+	}
+out:
+	if (state->fw_index == S5C73M3_SD_CARD ||
+		state->fw_index == S5C73M3_IN_DATA) {
+		if (!IS_ERR(fp) && fp != NULL)
+			filp_close(fp, current->files);
+
+		vfree(buf);
+
+		set_fs(old_fs);
+	} else {
+		release_firmware(fw);
+	}
+
+	return err;
+}
+
+/*
+ * v4l2_subdev_video_ops
+ */
+static const struct s5c73m3_frmsizeenum *s5c73m3_get_frmsize
+	(const struct s5c73m3_frmsizeenum *frmsizes, int num_entries, int index)
+{
+	int i;
+
+	for (i = 0; i < num_entries; i++) {
+		if (frmsizes[i].index == index)
+			return &frmsizes[i];
+	}
+
+	return NULL;
+}
+
+static int s5c73m3_set_frmsize(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err ;
+	cam_trace("E\n");
+
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		err = s5c73m3_writeb(sd, S5C73M3_CHG_MODE,
+			S5C73M3_YUV_MODE | state->preview->reg_val |
+			(state->sensor_mode<<8));
+		CHECK_ERR(err);
+	} else {
+		err = s5c73m3_writeb(sd, S5C73M3_CHG_MODE,
+			S5C73M3_INTERLEAVED_MODE
+			| state->capture->reg_val | state->preview->reg_val
+			|(state->sensor_mode<<8));
+		CHECK_ERR(err);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_s_fmt(struct v4l2_subdev *sd,
+	struct v4l2_mbus_framefmt *ffmt)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	const struct s5c73m3_frmsizeenum **frmsize;
+	const struct s5c73m3_frmsizeenum **capfrmsize;
+
+	u32 width = ffmt->width;
+	u32 height = ffmt->height;
+	u32 tmp_width;
+	u32 old_index, old_index_cap;
+	int i, num_entries;
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+	if (ffmt->width < ffmt->height) {
+		tmp_width = ffmt->height;
+		height = ffmt->width;
+		width = tmp_width;
+	}
+
+	if (ffmt->colorspace == V4L2_COLORSPACE_JPEG)
+		state->format_mode = V4L2_PIX_FMT_MODE_CAPTURE;
+	else
+		state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+
+	s5c73m3_set_mode(sd);
+
+	/*set frame size for preview(yuv)*/
+	frmsize = &state->preview;
+	old_index = *frmsize ? (*frmsize)->index : -1;
+	*frmsize = NULL;
+
+	num_entries = ARRAY_SIZE(preview_frmsizes);
+	for (i = 0; i < num_entries; i++) {
+		if (width == preview_frmsizes[i].width &&
+			height == preview_frmsizes[i].height) {
+			*frmsize = &preview_frmsizes[i];
+			break;
+		}
+	}
+
+	if (*frmsize == NULL) {
+		cam_warn("invalid yuv frame size %dx%d\n", width, height);
+		*frmsize = s5c73m3_get_frmsize(preview_frmsizes,
+				num_entries,
+				S5C73M3_PREVIEW_960X720);
+	}
+
+	/*set frame size for capture(jpeg)*/
+	/*it's meaningful for interleaved mode*/
+	capfrmsize = &state->capture;
+	old_index_cap = *capfrmsize ? (*capfrmsize)->index : -1;
+	*capfrmsize = NULL;
+
+	width = state->jpeg_width;
+	height = state->jpeg_height;
+
+	num_entries = ARRAY_SIZE(capture_frmsizes);
+	for (i = 0; i < num_entries; i++) {
+		if (width == capture_frmsizes[i].width &&
+			height == capture_frmsizes[i].height) {
+			*capfrmsize = &capture_frmsizes[i];
+			break;
+		}
+	}
+
+	if (*capfrmsize == NULL) {
+		cam_warn("invalid jpeg frame size %dx%d\n", width, height);
+		*capfrmsize = s5c73m3_get_frmsize(capture_frmsizes, num_entries,
+				S5C73M3_CAPTURE_VGA);
+	}
+
+	cam_dbg("yuv %dx%d\n", (*frmsize)->width, (*frmsize)->height);
+	cam_dbg("jpeg %dx%d\n", (*capfrmsize)->width, (*capfrmsize)->height);
+	if (state->stream_enable) {
+		if (ffmt->colorspace == V4L2_COLORSPACE_JPEG) {
+			if ((old_index != (*frmsize)->index)
+				|| (old_index_cap != (*capfrmsize)->index))
+				s5c73m3_set_frmsize(sd);
+		} else {
+			if (old_index != (*frmsize)->index)
+				s5c73m3_set_frmsize(sd);
+		}
+	} else
+		s5c73m3_set_frmsize(sd);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct s5c73m3_state *state = to_state(sd);
+
+	a->parm.capture.timeperframe.numerator = 1;
+	a->parm.capture.timeperframe.denominator = state->fps;
+
+	return 0;
+}
+
+static int s5c73m3_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+
+	u32 fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	if (fps != state->fps) {
+		if (fps <= 0 || fps > 30) {
+			cam_err("invalid frame rate %d\n", fps);
+			fps = 30;
+		}
+		state->fps = fps;
+	}
+	cam_err("Frame rate = %d(%d)\n", fps, state->fps);
+
+	err = s5c73m3_set_frame_rate(sd, state->fps);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int s5c73m3_enum_framesizes(struct v4l2_subdev *sd,
+	struct v4l2_frmsizeenum *fsize)
+{
+	struct s5c73m3_state *state = to_state(sd);
+
+	/*
+	* The camera interface should read this value, this is the resolution
+	* at which the sensor would provide framedata to the camera i/f
+	* In case of image capture,
+	* this returns the default camera resolution (VGA)
+	*/
+	if (state->preview == NULL)
+		return -EINVAL;
+
+	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+	if (state->hdr_mode) {
+		fsize->discrete.width = state->capture->width;
+		fsize->discrete.height = state->capture->height;
+	} else {
+		fsize->discrete.width = state->preview->width;
+		fsize->discrete.height = state->preview->height;
+	}
+	return 0;
+}
+
+static int s5c73m3_s_stream_sensor(struct v4l2_subdev *sd, int onoff)
+{
+	int err = 0;
+	int index = 0;
+	u16 status = 0;
+	u16 i2c_status = 0;
+	u16 i2c_seq_status = 0;
+
+	cam_info("onoff=%d\n", onoff);
+	err = s5c73m3_writeb(sd, S5C73M3_SENSOR_STREAMING,
+		onoff ? S5C73M3_SENSOR_STREAMING_ON :
+		S5C73M3_SENSOR_STREAMING_OFF);
+	CHECK_ERR(err);
+
+	do {
+		err = s5c73m3_read(sd, 0x0009, S5C73M3_STATUS, &status);
+		if (status == 0xffff)
+			break;
+
+		index++;
+		msleep(20);
+	} while (index < 30);
+
+	if (index >= 30) {
+		err = s5c73m3_read(sd, 0x0009,
+			S5C73M3_I2C_ERR_STATUS, &i2c_status);
+		err = s5c73m3_read(sd, 0x0009,
+			S5C73M3_I2C_SEQ_STATUS, &i2c_seq_status);
+		cam_dbg("TimeOut!! index:%d,status:%#x,i2c_stauts:%#x,i2c_seq_status:%#x\n",
+			index,
+			status,
+			i2c_status,
+			i2c_seq_status);
+
+		err = -1;
+	}
+
+	return err;
+}
+
+static int s5c73m3_s_stream_hdr(struct v4l2_subdev *sd, int enable)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+	cam_trace("E\n");
+
+	if (enable) {
+		err = s5c73m3_i2c_write(sd, 0x0050, 0x0009);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0054, 0x5000);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x0902);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x0008);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x091A);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x0002);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x0B10);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x8000 |
+				state->capture->reg_val |
+				state->preview->reg_val);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0054, 0x5080);
+		CHECK_ERR(err);
+
+		err = s5c73m3_i2c_write(sd, 0x0F14, 0x0003);
+		CHECK_ERR(err);
+
+		err = s5c73m3_s_stream_sensor(sd, enable);
+		err = s5c73m3_set_auto_bracket_mode(sd);
+	} else {
+		  err = s5c73m3_s_stream_sensor(sd, enable);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err;
+
+	cam_trace("E\n");
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("\"Unknown\" state, please update F/W");
+		return -ENOSYS;
+	}
+
+	switch (enable) {
+	case STREAM_MODE_CAM_ON:
+	case STREAM_MODE_CAM_OFF:
+		switch (state->format_mode) {
+		case V4L2_PIX_FMT_MODE_CAPTURE:
+			cam_info("capture %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+
+			s5c73m3_s_stream_sensor(sd, enable);
+			if (enable == STREAM_MODE_CAM_ON &&
+				(state->focus.mode >=
+					FOCUS_MODE_CONTINOUS &&
+				state->focus.mode <=
+					FOCUS_MODE_CONTINOUS_VIDEO)) {
+				s5c73m3_set_af_mode(sd,
+					state->focus.mode);
+			}
+			break;
+
+		default:
+			cam_info("preview %s",
+				enable == STREAM_MODE_CAM_ON ? "on" : "off");
+
+			if (state->hdr_mode) {
+				err = s5c73m3_set_flash(sd, FLASH_MODE_OFF, 0);
+				err = s5c73m3_s_stream_hdr(sd, enable);
+			} else {
+				err = s5c73m3_s_stream_sensor(sd, enable);
+				if (enable == STREAM_MODE_CAM_ON &&
+					(state->focus.mode >=
+						FOCUS_MODE_CONTINOUS &&
+					state->focus.mode <=
+						FOCUS_MODE_CONTINOUS_VIDEO)) {
+					s5c73m3_set_af_mode(sd,
+						state->focus.mode);
+				}
+			}
+			break;
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		if (state->flash_mode != FLASH_MODE_OFF)
+			err = s5c73m3_set_flash(sd, state->flash_mode, 1);
+
+		if (state->preview->index == S5C73M3_PREVIEW_720P ||
+				state->preview->index == S5C73M3_PREVIEW_1080P)
+			err = s5c73m3_set_af(sd, 1);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		if (state->preview->index == S5C73M3_PREVIEW_720P ||
+				state->preview->index == S5C73M3_PREVIEW_1080P)
+			err = s5c73m3_set_af(sd, 0);
+
+		s5c73m3_set_flash(sd, FLASH_MODE_OFF, 1);
+		break;
+
+	default:
+		cam_err("invalid stream option, %d\n", enable);
+		break;
+	}
+
+#if 0
+		err = s5c73m3_writeb(sd, S5C73M3_AF_CAL, 0);
+		CHECK_ERR(err);
+#endif
+	state->stream_enable = enable;
+	if (state->stream_enable && state->hdr_mode == 0) {
+		if (state->fps)
+			s5c73m3_set_frame_rate(sd, state->fps);
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5c73m3_init_param(struct v4l2_subdev *sd)
+{
+	s5c73m3_set_flash(sd, FLASH_MODE_OFF, 0);
+	return 0;
+}
+
+static int s5c73m3_FROM_booting(struct v4l2_subdev *sd)
+{
+	u16 read_val;
+	int i, err;
+
+	cam_trace("E\n");
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	udelay(400);
+
+	/*Check boot done*/
+	for (i = 0; i < 4; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x0C)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x0C) {
+		cam_err("boot fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+       /*P,M,S and Boot Mode*/
+	err = s5c73m3_write(sd, 0x3100, 0x010C, 0x0044);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3100, 0x0108, 0x000D);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3100, 0x0304, 0x0001);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x0001, 0x0000, 0x5800);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x0001, 0x0002, 0x0002);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3100, 0x0000, 0x0001);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0014, 0x1B85);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0010, 0x230C);
+	CHECK_ERR(err);
+
+	mdelay(300);
+
+	/*Check binary read done*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x230E)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x230E) {
+		cam_err("binary read fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/*ARM reset*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFD);
+	CHECK_ERR(err);
+
+	/*remap*/
+	err = s5c73m3_write(sd, 0x3010, 0x00A4, 0x0183);
+	CHECK_ERR(err);
+
+	/*ARM go again*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	cam_trace("X\n");
+
+	return 0;
+}
+
+static int s5c73m3_SPI_booting(struct v4l2_subdev *sd)
+{
+	u16 read_val;
+	int i, err;
+
+	/*ARM go*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	udelay(400);
+
+	/*Check boot done*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x0C)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x0C) {
+		cam_err("boot fail, read_val %#x\n", read_val);
+		return -1;
+	}
+
+       /*P,M,S and Boot Mode*/
+	err = s5c73m3_write(sd, 0x3010, 0x0014, 0x2146);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0010, 0x210C);
+	CHECK_ERR(err);
+
+	udelay(200);
+
+	/*Check SPI ready*/
+	for (i = 0; i < 3; i++) {
+		err = s5c73m3_read(sd, 0x3010, 0x0010, &read_val);
+		CHECK_ERR(err);
+
+		if (read_val == 0x210D)
+			break;
+
+		udelay(100);
+	}
+
+	if (read_val != 0x210D) {
+		cam_err("SPI not ready, read_val %#x\n", read_val);
+		return -1;
+	}
+
+	/*download fw by SPI*/
+	s5c73m3_load_fw(sd);
+
+	/*ARM reset*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFD);
+	CHECK_ERR(err);
+
+	/*remap*/
+	err = s5c73m3_write(sd, 0x3010, 0x00A4, 0x0183);
+	CHECK_ERR(err);
+
+	/*ARM go again*/
+	err = s5c73m3_write(sd, 0x3000, 0x0004, 0xFFFF);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int s5c73m3_read_vdd_core(struct v4l2_subdev *sd)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	u8 *buf = NULL;
+	u16 read_val;
+	u32 vdd_core_val = 0;
+	int err;
+	struct file *fp;
+	mm_segment_t old_fs;
+
+	cam_trace("E\n");
+
+	/*Initialize OTP Controller*/
+	err = s5c73m3_write(sd, 0x3800, 0xA004, 0x0000);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA000, 0x0004);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0D8, 0x0000);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0DC, 0x0004);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0C4, 0x4000);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0D4, 0x0015);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA000, 0x0001);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0B4, 0x9F90);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA09C, 0x9A95);
+	CHECK_ERR(err);
+
+	/*Page Select*/
+	err = s5c73m3_write(sd, 0x3800, 0xA0C4, 0x4800);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0C4, 0x4400);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA0C4, 0x4200);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA004, 0x00C0);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3800, 0xA000, 0x0001);
+	CHECK_ERR(err);
+
+#if 0 /*read_val should be 0x7383*/
+	err = s5c73m3_read(sd, 0x0000, 0x131C, &read_val);
+	CHECK_ERR(err);
+
+	cam_dbg("read_val %#x\n", read_val);
+#endif
+
+	/*Read Data*/
+	err = s5c73m3_read(sd, 0x3800, 0xA034, &read_val);
+	CHECK_ERR(err);
+
+	cam_dbg("read_val %#x\n", read_val);
+
+	err = s5c73m3_read(sd, 0x3800, 0xA040, &isp_chip_info1);
+	CHECK_ERR(err);
+	err = s5c73m3_read(sd, 0x3800, 0xA044, &isp_chip_info2);
+	CHECK_ERR(err);
+	err = s5c73m3_read(sd, 0x3800, 0xA048, &isp_chip_info3);
+	CHECK_ERR(err);
+
+	/*Read Data End*/
+	err = s5c73m3_write(sd, 0x3800, 0xA000, 0x0000);
+	CHECK_ERR(err);
+
+	if (read_val & 0x200) {
+		state->pdata->set_vdd_core(1150000);
+		strcpy(sysfs_isp_core, "1.15V");
+		vdd_core_val = 1150000;
+	} else if (read_val & 0x800) {
+		state->pdata->set_vdd_core(1100000);
+		strcpy(sysfs_isp_core, "1.10V");
+		vdd_core_val = 1100000;
+	} else if (read_val & 0x2000) {
+		state->pdata->set_vdd_core(1100000);
+		strcpy(sysfs_isp_core, "1.05V");
+		vdd_core_val = 1100000;
+	} else if (read_val & 0x8000) {
+		state->pdata->set_vdd_core(1000000);
+		strcpy(sysfs_isp_core, "1.00V");
+		vdd_core_val = 1000000;
+	} else {
+		state->pdata->set_vdd_core(1150000);
+		strcpy(sysfs_isp_core, "1.15V");
+		vdd_core_val = 1150000;
+	}
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fp = filp_open(S5C73M3_CORE_VDD,
+		O_WRONLY|O_CREAT, 0666);
+	if (IS_ERR(fp))
+		goto out;
+
+	buf = vmalloc(10);
+	if (!buf) {
+		cam_err("failed to allocate memory\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	sprintf(buf, "%d\n", vdd_core_val);
+
+	err = vfs_write(fp, (char __user *)buf, 10, &fp->f_pos);
+	/*cam_dbg("return value of vfs_write = %d\n", err);*/
+out:
+	if (buf != NULL)
+		vfree(buf);
+
+	if (fp !=  NULL)
+		filp_close(fp, current->files);
+
+	set_fs(old_fs);
+	cam_trace("X\n");
+
+	return 0;
+}
+
+static int s5c73m3_set_timing_register_for_vdd(struct v4l2_subdev *sd)
+{
+	int err = 0;
+
+	err = s5c73m3_write(sd, 0x3010, 0x0018, 0x0618);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x001C, 0x10C1);
+	CHECK_ERR(err);
+	err = s5c73m3_write(sd, 0x3010, 0x0020, 0x249E);
+	CHECK_ERR(err);
+
+	return err;
+}
+
+static int s5c73m3_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct s5c73m3_state *state = to_state(sd);
+	int err = 0;
+	int retVal = 0;
+	sd_internal = sd;
+
+	/* Default state values */
+	state->isp.bad_fw = 1;
+
+	state->preview = NULL;
+	state->capture = NULL;
+	state->fw_index = S5C73M3_PATH_MAX;
+
+	state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	state->sensor_mode = SENSOR_CAMERA;
+	state->flash_mode = FLASH_MODE_OFF;
+	state->wb_mode = WHITE_BALANCE_AUTO;
+	state->focus.mode = FOCUS_MODE_CONTINOUS_PICTURE;
+	state->focus.touch = 0;
+
+	state->fps = 0;			/* auto */
+
+	memset(&state->focus, 0, sizeof(state->focus));
+
+	if (!state->pdata->is_vdd_core_set())
+		s5c73m3_read_vdd_core(sd);
+
+	cam_dbg("vdd core value from OTP : %s", sysfs_isp_core);
+	cam_dbg("chip info from OTP : %#x, %#x, %#x\n",
+		isp_chip_info1, isp_chip_info2, isp_chip_info3);
+
+#ifdef S5C73M3_FROM_BOOTING
+	err = s5c73m3_FROM_booting(sd);
+#else
+	err = s5c73m3_set_timing_register_for_vdd(sd);
+	CHECK_ERR(err);
+
+	err = s5c73m3_check_fw(sd, 0);
+	if (err < 0) {
+		cam_dbg("isp.bad_fw is true\n");
+		state->isp.bad_fw = 1;
+	}
+#endif
+	CHECK_ERR(err);
+
+	err = s5c73m3_i2c_check_status(sd);
+	if (err < 0) {
+		cam_err("ISP is not ready. retry loading fw!!\n");
+		/* retry */
+		retVal = s5c73m3_check_fw_date(sd);
+
+		err = state->pdata->is_isp_reset();
+		CHECK_ERR(err);
+		err = s5c73m3_set_timing_register_for_vdd(sd);
+		CHECK_ERR(err);
+
+		/* retVal = 0 : Same Version
+		retVal < 0 : Phone Version is latest Version than sensorFW.
+		retVal > 0 : Sensor Version is latest version than phoenFW. */
+		if (retVal <= 0) {
+			cam_dbg("Loading From PhoneFW......\n");
+			err = s5c73m3_SPI_booting(sd);
+			CHECK_ERR(err);
+		} else {
+			cam_dbg("Loading From SensorFW......\n");
+			err = s5c73m3_get_sensor_fw_binary(sd);
+			CHECK_ERR(err);
+		}
+
+	}
+
+	state->isp.bad_fw = 0;
+
+	s5c73m3_init_param(sd);
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops s5c73m3_core_ops = {
+	.init = s5c73m3_init,		/* initializing API */
+	.load_fw = s5c73m3_load_fw,
+	.queryctrl = s5c73m3_queryctrl,
+	.g_ctrl = s5c73m3_g_ctrl,
+	.s_ctrl = s5c73m3_s_ctrl,
+	.g_ext_ctrls = s5c73m3_g_ext_ctrls,
+};
+
+static const struct v4l2_subdev_video_ops s5c73m3_video_ops = {
+	.s_mbus_fmt = s5c73m3_s_fmt,
+	.g_parm = s5c73m3_g_parm,
+	.s_parm = s5c73m3_s_parm,
+	.enum_framesizes = s5c73m3_enum_framesizes,
+	.s_stream = s5c73m3_s_stream,
+};
+
+static const struct v4l2_subdev_ops s5c73m3_ops = {
+	.core = &s5c73m3_core_ops,
+	.video = &s5c73m3_video_ops,
+};
+
+static ssize_t s5c73m3_camera_rear_camtype_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char type[25];
+
+	strcpy(type, sysfs_sensor_type);
+	return sprintf(buf, "%s\n", type);
+}
+
+static ssize_t s5c73m3_camera_rear_camfw_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%s %s\n", sysfs_sensor_fw, sysfs_phone_fw);
+}
+
+static ssize_t s5c73m3_camera_rear_flash(struct device *dev,
+	struct device_attribute *attr, const char *buf,
+	size_t count)
+{
+	int err;
+
+	if (buf[0] == '0')
+		err = s5c73m3_writeb(sd_internal, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_OFF);
+	else
+		err = s5c73m3_writeb(sd_internal, S5C73M3_FLASH_TORCH,
+			S5C73M3_FLASH_TORCH_ON);
+
+	CHECK_ERR(err);
+
+	return count;
+}
+
+static ssize_t s5c73m3_camera_isp_core_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	char core[10];
+
+	strcpy(core, sysfs_isp_core);
+	return sprintf(buf, "%s\n", core);
+}
+
+static DEVICE_ATTR(rear_camtype, S_IRUGO,
+		s5c73m3_camera_rear_camtype_show, NULL);
+static DEVICE_ATTR(rear_camfw, S_IRUGO, s5c73m3_camera_rear_camfw_show, NULL);
+static DEVICE_ATTR(rear_flash, S_IWUSR|S_IWGRP|S_IROTH,
+	NULL, s5c73m3_camera_rear_flash);
+static DEVICE_ATTR(isp_core, S_IRUGO, s5c73m3_camera_isp_core_show, NULL);
+
+/*
+ * s5c73m3_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int __devinit s5c73m3_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct s5c73m3_state *state;
+	struct v4l2_subdev *sd;
+
+	state = kzalloc(sizeof(struct s5c73m3_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5C73M3_DRIVER_NAME);
+
+	state->pdata = client->dev.platform_data;
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5c73m3_ops);
+
+#ifdef CAM_DEBUG
+	state->dbg_level = CAM_DEBUG;
+#endif
+
+#ifdef S5C73M3_BUSFREQ_OPP
+	/* lock bus frequency */
+	dev_lock(bus_dev, s5c73m3_dev, 400200);
+#endif
+
+	if (s5c73m3_dev)
+		dev_set_drvdata(s5c73m3_dev, state);
+
+	printk(KERN_DEBUG "%s\n", __func__);
+
+	return 0;
+}
+
+static int __devexit s5c73m3_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct s5c73m3_state *state = to_state(sd);
+
+	if (unlikely(state->isp.bad_fw)) {
+		cam_err("camera is not ready!!\n");
+	} else {
+		if (s5c73m3_set_af_softlanding(sd) < 0)
+			cam_err("failed to set soft landing\n");
+	}
+	v4l2_device_unregister_subdev(sd);
+
+#ifdef S5C73M3_BUSFREQ_OPP
+	/* Unlock bus frequency */
+	dev_unlock(bus_dev, s5c73m3_dev);
+#endif
+
+	kfree(state);
+
+	return 0;
+}
+
+static const struct i2c_device_id s5c73m3_id[] = {
+	{ S5C73M3_DRIVER_NAME, 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
+
+static struct i2c_driver s5c73m3_i2c_driver = {
+	.driver = {
+		.name	= S5C73M3_DRIVER_NAME,
+	},
+	.probe		= s5c73m3_probe,
+	.remove		= __devexit_p(s5c73m3_remove),
+	.id_table	= s5c73m3_id,
+};
+
+static int __init s5c73m3_mod_init(void)
+{
+#ifdef S5C73M3_BUSFREQ_OPP
+	/* To lock bus frequency in OPP mode */
+	bus_dev = dev_get("exynos-busfreq");
+#endif
+
+	if (!s5c73m3_dev) {
+		s5c73m3_dev = device_create(camera_class,
+				NULL, 0, NULL, "rear");
+		if (IS_ERR(s5c73m3_dev)) {
+			cam_warn("failed to create device!\n");
+			return 0;
+		}
+
+		if (device_create_file(s5c73m3_dev, &dev_attr_rear_camtype)
+				< 0) {
+			cam_warn("failed to create device file, %s\n",
+					dev_attr_rear_camtype.attr.name);
+		}
+
+		if (device_create_file(s5c73m3_dev, &dev_attr_rear_camfw) < 0) {
+			cam_warn("failed to create device file, %s\n",
+					dev_attr_rear_camfw.attr.name);
+		}
+
+		if (device_create_file(s5c73m3_dev, &dev_attr_rear_flash) < 0) {
+			cam_warn("failed to create device file, %s\n",
+					dev_attr_rear_flash.attr.name);
+		}
+
+		if (device_create_file(s5c73m3_dev, &dev_attr_isp_core) < 0) {
+			cam_warn("failed to create device file, %s\n",
+					dev_attr_isp_core.attr.name);
+		}
+	}
+
+	return i2c_add_driver(&s5c73m3_i2c_driver);
+}
+
+static void __exit s5c73m3_mod_exit(void)
+{
+	i2c_del_driver(&s5c73m3_i2c_driver);
+}
+module_init(s5c73m3_mod_init);
+module_exit(s5c73m3_mod_exit);
+
+
+MODULE_DESCRIPTION("driver for LSI S5C73M3");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5c73m3.h b/drivers/media/video/s5c73m3.h
new file mode 100644
index 0000000..97a697b
--- /dev/null
+++ b/drivers/media/video/s5c73m3.h
@@ -0,0 +1,463 @@
+/*
+ * Driver for LSI S5C73M3 (ISP for 8MP Camera)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5C73M3_H
+#define __S5C73M3_H
+
+#define CONFIG_CAM_DEBUG	1
+/*#define FEATURE_DEBUG_DUMP*/
+
+#define cam_warn(fmt, ...)	\
+	do { \
+		printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_err(fmt, ...)	\
+	do { \
+		printk(KERN_ERR "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_info(fmt, ...)	\
+	do { \
+		printk(KERN_INFO "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#ifdef CONFIG_CAM_DEBUG
+#define CAM_DEBUG	(1 << 0)
+#define CAM_TRACE	(1 << 1)
+#define CAM_I2C		(1 << 2)
+
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_DEBUG) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_TRACE) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_i2c_dbg(fmt, ...)	\
+	do { \
+		if (to_state(sd)->dbg_level & CAM_I2C) \
+			printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+#else
+#define cam_dbg(fmt, ...)
+#define cam_trace(fmt, ...)
+#define cam_i2c_dbg(fmt, ...)
+#endif
+
+enum s5c73m3_fw_path{
+	S5C73M3_SD_CARD,
+	S5C73M3_IN_DATA,
+	S5C73M3_IN_SYSTEM,
+	S5C73M3_PATH_MAX,
+};
+
+enum s5c73m3_prev_frmsize {
+	S5C73M3_PREVIEW_QCIF,
+	S5C73M3_PREVIEW_QCIF2,
+	S5C73M3_PREVIEW_QVGA,
+	S5C73M3_PREVIEW_CIF,
+	S5C73M3_PREVIEW_VGA,
+	S5C73M3_PREVIEW_D1,
+	S5C73M3_PREVIEW_WVGA,
+	S5C73M3_PREVIEW_704X576,
+	S5C73M3_PREVIEW_880X720,
+	S5C73M3_PREVIEW_960X640,
+	S5C73M3_PREVIEW_960X720,
+	S5C73M3_PREVIEW_1008X672,
+	S5C73M3_PREVIEW_1056X704,
+	S5C73M3_PREVIEW_1184X666,
+	S5C73M3_PREVIEW_720P,
+	S5C73M3_VDIS_720P,
+	S5C73M3_PREVIEW_1080P,
+	S5C73M3_VDIS_1080P,
+	S5C73M3_PREVIEW_HDR,
+};
+
+enum s5c73m3_cap_frmsize {
+	S5C73M3_CAPTURE_VGA,	/* 640 x 480 */
+	S5C73M3_CAPTURE_WVGA,	/* 800 x 480 */
+	S5C73M3_CAPTURE_1024X768,	/* 1024 x 768 */
+	S5C73M3_CAPTURE_HD,	/* 1280 x 720 */
+	S5C73M3_CAPTURE_W1MP,	/* 1600 x 960 */
+	S5C73M3_CAPTURE_2MP,	/* UXGA - 1600 x 1200 */
+	S5C73M3_CAPTURE_W2MP,	/* 2048 x 1232 */
+	S5C73M3_CAPTURE_3MP,	/* QXGA - 2048 x 1536 */
+	S5C73M3_CAPTURE_W4MP,	/* WQXGA - 2560 x 1536 */
+	S5C73M3_CAPTURE_5MP,	/* 2560 x 1920 */
+	S5C73M3_CAPTURE_W6MP,	/* 3072 x 1856 */
+	S5C73M3_CAPTURE_7MP,	/* 3072 x 2304 */
+	S5C73M3_CAPTURE_W7MP,	/* WQXGA - 2560 x 1536 */
+	S5C73M3_CAPTURE_3264X2176,	/* 3264 x 2176 */
+	S5C73M3_CAPTURE_8MP,	/* 3264 x 2448 */
+};
+
+enum s5c73m3_isneed_flash_tristate {
+	S5C73M3_ISNEED_FLASH_OFF = 0x00,
+	S5C73M3_ISNEED_FLASH_ON = 0x01,
+	S5C73M3_ISNEED_FLASH_UNDEFINED = 0x02,
+};
+
+struct s5c73m3_control {
+	u32 id;
+	s32 value;
+	s32 minimum;		/* Note signedness */
+	s32 maximum;
+	s32 step;
+	s32 default_value;
+};
+
+struct s5c73m3_frmsizeenum {
+	unsigned int index;
+	unsigned int width;
+	unsigned int height;
+	u8 reg_val;		/* a value for category parameter */
+};
+
+struct s5c73m3_effectenum {
+	unsigned int index;
+	unsigned int reg_val;
+};
+
+struct s5c73m3_isp {
+	unsigned int bad_fw:1;
+};
+
+struct s5c73m3_fw_version {
+	unsigned int index;
+	unsigned int opened;
+	char path[25];
+	char ver[10];
+};
+
+struct s5c73m3_focus {
+	unsigned int mode;
+	unsigned int lock;
+	unsigned int status;
+	unsigned int touch;
+	unsigned int pos_x;
+	unsigned int pos_y;
+};
+
+struct s5c73m3_state {
+	struct s5c73m3_platform_data *pdata;
+	struct v4l2_subdev sd;
+
+	struct s5c73m3_isp isp;
+
+	const struct s5c73m3_frmsizeenum *preview;
+	const struct s5c73m3_frmsizeenum *capture;
+
+	enum v4l2_pix_format_mode format_mode;
+	enum v4l2_sensor_mode sensor_mode;
+	enum v4l2_flash_mode flash_mode;
+	enum v4l2_wb_mode wb_mode;
+	enum v4l2_scene_mode scene_mode;
+	int vt_mode;
+	int hdr_mode;
+	int hybrid_mode;
+	int zoom;
+	int stream_enable;
+	int ae_lock;
+	int awb_lock;
+	int fw_index;
+	u32 cal_device;
+	u32 cal_dll;
+
+	unsigned int fps;
+	struct s5c73m3_focus focus;
+	int caf_mode;
+	char isflash;
+
+	u32 real_preview_width;
+	u32 real_preview_height;
+	u32 jpeg_width;
+	u32 jpeg_height;
+	u32 sensor_size;
+
+	u8 sensor_fw[10];
+	u8 phone_fw[10];
+
+	u8 sensor_type[15];
+
+#ifdef CONFIG_CAM_DEBUG
+	u8 dbg_level;
+#endif
+};
+
+#define S5C73M3_IMG_OUTPUT	0x0902
+#define S5C73M3_HDR_OUTPUT	0x0008
+#define S5C73M3_YUV_OUTPUT	0x0009
+#define S5C73M3_INTERLEAVED_OUTPUT	0x000D
+#define S5C73M3_HYBRID_OUTPUT	0x0016
+
+#define S5C73M3_STILL_PRE_FLASH			0x0A00
+#define S5C73M3_STILL_PRE_FLASH_FIRE		0x0000
+#define S5C73M3_STILL_PRE_FLASH_NON_FIRED	0x0000
+#define S5C73M3_STILL_PRE_FLASH_FIRED		0x0001
+
+#define S5C73M3_STILL_MAIN_FLASH		0x0A02
+#define S5C73M3_STILL_MAIN_FLASH_CANCEL		0x0001
+#define S5C73M3_STILL_MAIN_FLASH_FIRE		0x0002
+
+
+#define S5C73M3_ZOOM_STEP	0x0B00
+
+
+#define S5C73M3_IMAGE_EFFECT		0x0B0A
+#define S5C73M3_IMAGE_EFFECT_NONE	0x0001
+#define S5C73M3_IMAGE_EFFECT_NEGATIVE	0x0002
+#define S5C73M3_IMAGE_EFFECT_AQUA	0x0003
+#define S5C73M3_IMAGE_EFFECT_SEPIA	0x0004
+#define S5C73M3_IMAGE_EFFECT_MONO	0x0005
+#define S5C73M3_IMAGE_EFFECT_SKETCH	0x0006
+#define S5C73M3_IMAGE_EFFECT_WASHED	0x0007
+#define S5C73M3_IMAGE_EFFECT_VINTAGE_WARM	0x0008
+#define S5C73M3_IMAGE_EFFECT_VINTAGE_COLD	0x0009
+#define S5C73M3_IMAGE_EFFECT_SOLARIZE	0x000A
+#define S5C73M3_IMAGE_EFFECT_POSTERIZE	0x000B
+#define S5C73M3_IMAGE_EFFECT_POINT_BLUE	0x000C
+#define S5C73M3_IMAGE_EFFECT_POINT_RED_YELLOW	0x000D
+#define S5C73M3_IMAGE_EFFECT_POINT_COLOR_3	0x000E
+#define S5C73M3_IMAGE_EFFECT_POINT_GREEN	0x000F
+
+#define S5C73M3_IMAGE_QUALITY		0x0B0C
+#define S5C73M3_IMAGE_QUALITY_SUPERFINE	0x0000
+#define S5C73M3_IMAGE_QUALITY_FINE	0x0001
+#define S5C73M3_IMAGE_QUALITY_NORMAL	0x0002
+
+
+#define S5C73M3_FLASH_MODE		0x0B0E
+#define S5C73M3_FLASH_MODE_OFF		0x0000
+#define S5C73M3_FLASH_MODE_ON		0x0001
+#define S5C73M3_FLASH_MODE_AUTO		0x0002
+
+#define S5C73M3_FLASH_TORCH		0x0B12
+#define S5C73M3_FLASH_TORCH_OFF		0x0000
+#define S5C73M3_FLASH_TORCH_ON		0x0001
+
+#define S5C73M3_AE_ISNEEDFLASH		0x0CBA
+#define S5C73M3_AE_ISNEEDFLASH_OFF	0x0000
+#define S5C73M3_AE_ISNEEDFLASH_ON	0x0001
+
+
+#define S5C73M3_CHG_MODE		0x0B10
+#define S5C73M3_YUV_MODE		0x8000
+#define S5C73M3_INTERLEAVED_MODE	0x8000
+
+
+#define S5C73M3_AF_CON			0x0E00
+#define S5C73M3_AF_CON_STOP		0x0000
+#define S5C73M3_AF_CON_SCAN		0x0001/*AF_SCAN:Full Search*/
+#define S5C73M3_AF_CON_START	0x0002/*AF_START:Fast Search*/
+
+#define S5C73M3_AF_STATUS		0x5E80
+
+#define S5C73M3_AF_TOUCH_AF		0x0E0A
+
+#define S5C73M3_AF_CAL			0x0E06
+
+#define S5C73M3_CAF_STATUS_FIND_SEARCHING_DIR	0x0001
+#define S5C73M3_CAF_STATUS_FOCUSING	0x0002
+#define S5C73M3_CAF_STATUS_FOCUSED	0x0003
+#define S5C73M3_CAF_STATUS_UNFOCUSED	0x0004
+
+#define S5C73M3_AF_STATUS_INVALID	0x0010
+#define S5C73M3_AF_STATUS_FOCUSING	0x0020
+#define S5C73M3_AF_STATUS_FOCUSED	0x0030/*SUCCESS*/
+#define S5C73M3_AF_STATUS_UNFOCUSED	0x0040/*FAIL*/
+
+#define S5C73M3_AF_TOUCH_POSITION	0x5E8E
+
+#define S5C73M3_AF_FACE_ZOOM	0x0E10
+
+#define S5C73M3_AF_MODE			0x0E02
+#define S5C73M3_AF_MODE_NORMAL		0x0000
+#define S5C73M3_AF_MODE_MACRO		0x0001
+#define S5C73M3_AF_MODE_MOVIE_CAF_START	0x0002
+#define S5C73M3_AF_MODE_MOVIE_CAF_STOP		0x0003
+#define S5C73M3_AF_MODE_PREVIEW_CAF_START	0x0004
+#define S5C73M3_AF_MODE_PREVIEW_CAF_STOP	0x0005
+
+#define S5C73M3_AF_SOFTLANDING		0x0E16
+#define S5C73M3_AF_SOFTLANDING_ON	0x0000
+
+#define S5C73M3_FACE_DET		0x0E0C
+#define S5C73M3_FACE_DET_OFF		0x0000
+#define S5C73M3_FACE_DET_ON		0x0001
+
+#define S5C73M3_FACE_DET_OSD		0x0E0E
+#define S5C73M3_FACE_DET_OSD_OFF	0x0000
+#define S5C73M3_FACE_DET_OSD_ON		0x0001
+
+#define S5C73M3_AE_CON		0x0C00
+#define S5C73M3_AE_STOP		0x0000/*LOCK*/
+#define S5C73M3_AE_START	0x0001/*UNLOCK*/
+
+#define S5C73M3_ISO		0x0C02
+#define S5C73M3_ISO_AUTO	0x0000
+#define S5C73M3_ISO_100		0x0001
+#define S5C73M3_ISO_200		0x0002
+#define S5C73M3_ISO_400		0x0003
+#define S5C73M3_ISO_800		0x0004
+#define S5C73M3_ISO_SPORTS	0x0005
+#define S5C73M3_ISO_NIGHT	0x0006
+#define S5C73M3_ISO_INDOOR	0x0007
+
+#define S5C73M3_EV		0x0C04
+#define S5C73M3_EV_M20		0x0000
+#define S5C73M3_EV_M15		0x0001
+#define S5C73M3_EV_M10		0x0002
+#define S5C73M3_EV_M05		0x0003
+#define S5C73M3_EV_ZERO		0x0004
+#define S5C73M3_EV_P05		0x0005
+#define S5C73M3_EV_P10		0x0006
+#define S5C73M3_EV_P15		0x0007
+#define S5C73M3_EV_P20		0x0008
+
+#define S5C73M3_METER		0x0C06
+#define S5C73M3_METER_CENTER	0x0000
+#define S5C73M3_METER_SPOT	0x0001
+#define S5C73M3_METER_AVERAGE	0x0002
+#define S5C73M3_METER_SMART	0x0003
+
+#define S5C73M3_WDR		0x0C08
+#define S5C73M3_WDR_OFF		0x0000
+#define S5C73M3_WDR_ON		0x0001
+
+#define S5C73M3_FLICKER_MODE	0x0C12
+#define S5C73M3_FLICKER_NONE	0x0000
+#define S5C73M3_FLICKER_MANUAL_50HZ	0x0001
+#define S5C73M3_FLICKER_MANUAL_60HZ	0x0002
+#define S5C73M3_FLICKER_AUTO	0x0003
+#define S5C73M3_FLICKER_AUTO_50HZ	0x0004
+#define S5C73M3_FLICKER_AUTO_60HZ	0x0005
+
+#define S5C73M3_AE_MODE	0x0C1E
+#define S5C73M3_AUTO_MODE_AE_SET	0x0000
+#define S5C73M3_FIXED_30FPS	0x0002
+#define S5C73M3_FIXED_20FPS	0x0003
+#define S5C73M3_FIXED_15FPS	0x0004
+#define S5C73M3_FIXED_120FPS	0x0008
+#define S5C73M3_FIXED_7FPS	0x0009
+#define S5C73M3_FIXED_10FPS	0x000A
+#define S5C73M3_ANTI_SHAKE	0x0013
+
+#define S5C73M3_SHARPNESS	0x0C14
+#define S5C73M3_SHARPNESS_0	0x0000
+#define S5C73M3_SHARPNESS_1	0x0001
+#define S5C73M3_SHARPNESS_2	0x0002
+#define S5C73M3_SHARPNESS_M1	0x0003
+#define S5C73M3_SHARPNESS_M2	0x0004
+
+#define S5C73M3_SATURATION	0x0C16
+#define S5C73M3_SATURATION_0	0x0000
+#define S5C73M3_SATURATION_1	0x0001
+#define S5C73M3_SATURATION_2	0x0002
+#define S5C73M3_SATURATION_M1	0x0003
+#define S5C73M3_SATURATION_M2	0x0004
+
+#define S5C73M3_CONTRAST	0x0C18
+#define S5C73M3_CONTRAST_0	0x0000
+#define S5C73M3_CONTRAST_1	0x0001
+#define S5C73M3_CONTRAST_2	0x0002
+#define S5C73M3_CONTRAST_M1	0x0003
+#define S5C73M3_CONTRAST_M2	0x0004
+
+#define S5C73M3_SCENE_MODE		0x0C1A
+#define S5C73M3_SCENE_MODE_NONE		0x0000
+#define S5C73M3_SCENE_MODE_PORTRAIT	0x0001
+#define S5C73M3_SCENE_MODE_LANDSCAPE	0x0002
+#define S5C73M3_SCENE_MODE_SPORTS	0x0003
+#define S5C73M3_SCENE_MODE_INDOOR	0x0004
+#define S5C73M3_SCENE_MODE_BEACH	0x0005
+#define S5C73M3_SCENE_MODE_SUNSET	0x0006
+#define S5C73M3_SCENE_MODE_DAWN		0x0007
+#define S5C73M3_SCENE_MODE_FALL		0x0008
+#define S5C73M3_SCENE_MODE_NIGHT	0x0009
+#define S5C73M3_SCENE_MODE_AGAINSTLIGHT	0x000A
+#define S5C73M3_SCENE_MODE_FIRE		0x000B
+#define S5C73M3_SCENE_MODE_TEXT		0x000C
+#define S5C73M3_SCENE_MODE_CANDLE	0x000D
+
+#define S5C73M3_FIREWORK_CAPTURE 0x0C20
+#define S5C73M3_NIGHTSHOT_CAPTURE 0x0C22
+
+#define S5C73M3_AE_AUTO_BRAKET		0x0B14
+#define S5C73M3_AE_AUTO_BRAKET_EV05	0x0080
+#define S5C73M3_AE_AUTO_BRAKET_EV10	0x0100
+#define S5C73M3_AE_AUTO_BRAKET_EV15	0x0180
+#define S5C73M3_AE_AUTO_BRAKET_EV20	0x0200
+
+#define S5C73M3_SENSOR_STREAMING	0x090A
+#define S5C73M3_SENSOR_STREAMING_OFF	0x0000
+#define S5C73M3_SENSOR_STREAMING_ON	0x0001
+
+#define S5C73M3_AWB_MODE		0x0D02
+#define S5C73M3_AWB_MODE_INCANDESCENT	0x0000
+#define S5C73M3_AWB_MODE_FLUORESCENT1	0x0001
+#define S5C73M3_AWB_MODE_FLUORESCENT2	0x0002
+#define S5C73M3_AWB_MODE_DAYLIGHT	0x0003
+#define S5C73M3_AWB_MODE_CLOUDY		0x0004
+#define S5C73M3_AWB_MODE_AUTO		0x0005
+
+#define S5C73M3_AWB_CON			0x0D00
+#define S5C73M3_AWB_STOP		0x0000/*LOCK*/
+#define S5C73M3_AWB_START		0x0001/*UNLOCK*/
+
+#define S5C73M3_HYBRID_CAPTURE	0x0996
+
+#define S5C73M3_STATUS			0x5080
+#define BOOT_SUB_MAIN_ENTER		0xFF01
+#define BOOT_SRAM_TIMING_OK		0xFF02
+#define BOOT_INTERRUPTS_ENABLE		0xFF03
+#define BOOT_R_PLL_DONE			0xFF04
+#define BOOT_R_PLL_LOCKTIME_DONE	0xFF05
+#define BOOT_DELAY_COUNT_DONE		0xFF06
+#define BOOT_I_PLL_DONE			0xFF07
+#define BOOT_I_PLL_LOCKTIME_DONE	0xFF08
+#define BOOT_PLL_INIT_OK		0xFF09
+#define BOOT_SENSOR_INIT_OK		0xFF0A
+#define BOOT_GPIO_SETTING_OK		0xFF0B
+#define BOOT_READ_CAL_DATA_OK		0xFF0C
+#define BOOT_STABLE_AE_AWB_OK		0xFF0D
+#define EXCEPTION_OCCURED		0xDEAD
+
+#define S5C73M3_I2C_SEQ_STATUS	0x59A6
+#define SEQ_END_PLL		(1<<0x0)
+#define SEQ_END_SENSOR		(1<<0x1)
+#define SEQ_END_GPIO		(1<<0x2)
+#define SEQ_END_FROM		(1<<0x3)
+#define SEQ_END_STABLE_AE_AWB	(1<<0x4)
+#define SEQ_END_READY_I2C_CMD	(1<<0x5)
+
+#define S5C73M3_I2C_ERR_STATUS		0x599E
+#define ERR_STATUS_CIS_I2C		(1<<0x0)
+#define ERR_STATUS_AF_INIT		(1<<0x1)
+#define ERR_STATUS_CAL_DATA		(1<<0x2)
+#define ERR_STATUS_FRAME_COUNT		(1<<0x3)
+#define ERR_STATUS_FROM_INIT		(1<<0x4)
+#define ERR_STATUS_I2C_CIS_STREAM_OFF	(1<<0x5)
+#define ERR_STATUS_I2C_N_CMD_OVER	(1<<0x6)
+#define ERR_STATUS_I2C_N_CMD_MISMATCH0	(1<<0x7)
+#define ERR_STATUS_I2C_N_CMD_MISMATCH1	(1<<0x8)
+#define ERR_STATUS_EXCEPTION		(1<<0x9)
+
+
+#ifdef CONFIG_VIDEO_S5C73M3_SPI
+extern int s5c73m3_spi_write(const u8 *addr, const int len, const int txSize);
+extern int s5c73m3_spi_read(u8 *buf, size_t len, const int rxSize);
+#endif
+
+#endif /* __S5C73M3_H */
diff --git a/drivers/media/video/s5c73m3_spi.c b/drivers/media/video/s5c73m3_spi.c
new file mode 100755
index 0000000..0b537cb
--- /dev/null
+++ b/drivers/media/video/s5c73m3_spi.c
@@ -0,0 +1,192 @@
+/*
+ * driver for S5C73M3 SPI
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/spi/spi.h>
+
+static struct spi_device *g_spi;
+
+static inline
+int spi_xmit(const u8 *addr, const int len)
+{
+	int ret;
+
+	struct spi_message msg;
+
+	struct spi_transfer xfer = {
+		.len = len,
+		.tx_buf = addr,
+	};
+
+	spi_message_init(&msg);
+	spi_message_add_tail(&xfer, &msg);
+
+	ret = spi_sync(g_spi, &msg);
+
+	if (ret < 0)
+		dev_err(&g_spi->dev, "%s - error %d\n",
+				__func__, ret);
+
+	return ret;
+}
+
+static inline
+int spi_xmit_rx(u8 *in_buf, size_t len)
+{
+	int ret;
+	u8 read_out_buf[2];
+
+	struct spi_message msg;
+	struct spi_transfer xfer = {
+		.tx_buf = read_out_buf,
+		.rx_buf = in_buf,
+		.len	= len,
+		.cs_change = 0,
+	};
+
+	spi_message_init(&msg);
+
+	spi_message_add_tail(&xfer, &msg);
+
+	ret = spi_sync(g_spi, &msg);
+
+	if (ret < 0)
+		dev_err(&g_spi->dev, "%s - error %d\n",
+				__func__, ret);
+
+	return ret;
+}
+
+int s5c73m3_spi_read(u8 *buf, size_t len, const int rxSize)
+{
+	int k;
+	int ret = 0;
+	int z = 0;
+
+	u8 paddingData[32];
+	u32 count = len/rxSize;
+	u32 extra = len%rxSize;
+
+	for (k = 0; k < count; k++) {
+		ret = spi_xmit_rx(&buf[rxSize*k], rxSize);
+		if (ret < 0)
+			return -EINVAL;
+	}
+
+	if (extra != 0) {
+		ret = spi_xmit_rx(&buf[rxSize*k], extra);
+		if (ret < 0)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+int s5c73m3_spi_write(const u8 *addr, const int len, const int txSize)
+{
+	int i, j = 0;
+	int ret = 0;
+	u8 paddingData[32];
+	u32 count = len/txSize;
+	u32 extra = len%txSize;
+
+	memset(paddingData, 0, sizeof(paddingData));
+
+	for (i = 0 ; i < count ; i++) {
+		ret = spi_xmit(&addr[j], txSize);
+		j += txSize;
+		if (ret < 0)
+			goto exit_err;
+	}
+
+	if (extra) {
+		ret = spi_xmit(&addr[j], extra);
+		if (ret < 0)
+			goto exit_err;
+	}
+
+	ret = spi_xmit(paddingData, 32);
+	if (ret < 0)
+		goto exit_err;
+
+exit_err:
+	return ret;
+}
+
+static
+int __devinit s5c73m3_spi_probe(struct spi_device *spi)
+{
+	int ret;
+
+	spi->bits_per_word = 32;
+	if (spi_setup(spi)) {
+		pr_err("failed to setup spi for s5c73m3_spi\n");
+		ret = -EINVAL;
+		goto err_setup;
+	}
+
+	g_spi = spi;
+
+	pr_err("s5c73m3_spi successfully probed\n");
+
+	return 0;
+
+err_setup:
+	return ret;
+}
+
+static
+int __devexit s5c73m3_spi_remove(struct spi_device *spi)
+{
+	return 0;
+}
+
+static
+struct spi_driver s5c73m3_spi_driver = {
+	.driver = {
+		.name = "s5c73m3_spi",
+		.bus = &spi_bus_type,
+		.owner = THIS_MODULE,
+	},
+	.probe = s5c73m3_spi_probe,
+	.remove = __devexit_p(s5c73m3_spi_remove),
+};
+
+static
+int __init s5c73m3_spi_init(void)
+{
+	int ret;
+	pr_err("%s\n", __func__);
+
+	ret = spi_register_driver(&s5c73m3_spi_driver);
+
+	if (ret)
+		pr_err("failed to register s5c73mc fw - %x\n", ret);
+
+	return ret;
+}
+
+static
+void __exit s5c73m3_spi_exit(void)
+{
+	spi_unregister_driver(&s5c73m3_spi_driver);
+}
+
+module_init(s5c73m3_spi_init);
+module_exit(s5c73m3_spi_exit);
+
+MODULE_DESCRIPTION("S5C73M3 SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k4ba.c b/drivers/media/video/s5k4ba.c
new file mode 100644
index 0000000..6c2ccbb
--- /dev/null
+++ b/drivers/media/video/s5k4ba.c
@@ -0,0 +1,594 @@
+/* linux/drivers/media/video/s5k4ba.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver for S5K4BA (UXGA camera) from Samsung Electronics
+ * 1/4" 2.0Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/s5k4ba_platform.h>
+
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+
+#include "s5k4ba.h"
+
+#define S5K4BA_DRIVER_NAME	"S5K4BA"
+
+/* Default resolution & pixelformat. plz ref s5k4ba_platform.h */
+#define DEFAULT_RES		WVGA	/* Index of resoultion */
+#define DEFAUT_FPS_INDEX	S5K4BA_15FPS
+#define DEFAULT_FMT		V4L2_PIX_FMT_UYVY	/* YUV422 */
+
+/*
+ * Specification
+ * Parallel : ITU-R. 656/601 YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Serial : MIPI CSI2 (single lane) YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Resolution : 1280 (H) x 1024 (V)
+ * Image control : Brightness, Contrast, Saturation, Sharpness, Glamour
+ * Effect : Mono, Negative, Sepia, Aqua, Sketch
+ * FPS : 15fps @full resolution, 30fps @VGA, 24fps @720p
+ * Max. pixel clock frequency : 48MHz(upto)
+ * Internal PLL (6MHz to 27MHz input frequency)
+ */
+
+/* Camera functional setting values configured by user concept */
+struct s5k4ba_userset {
+	signed int exposure_bias;	/* V4L2_CID_EXPOSURE */
+	unsigned int ae_lock;
+	unsigned int awb_lock;
+	unsigned int auto_wb;	/* V4L2_CID_AUTO_WHITE_BALANCE */
+	unsigned int manual_wb;	/* V4L2_CID_WHITE_BALANCE_PRESET */
+	unsigned int wb_temp;	/* V4L2_CID_WHITE_BALANCE_TEMPERATURE */
+	unsigned int effect;	/* Color FX (AKA Color tone) */
+	unsigned int contrast;	/* V4L2_CID_CONTRAST */
+	unsigned int saturation;	/* V4L2_CID_SATURATION */
+	unsigned int sharpness;		/* V4L2_CID_SHARPNESS */
+	unsigned int glamour;
+};
+
+struct s5k4ba_state {
+	struct s5k4ba_platform_data *pdata;
+	struct v4l2_subdev sd;
+	struct v4l2_pix_format pix;
+	struct v4l2_fract timeperframe;
+	struct s5k4ba_userset userset;
+	int freq;	/* MCLK in KHz */
+	int is_mipi;
+	int isize;
+	int ver;
+	int fps;
+};
+
+static inline struct s5k4ba_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k4ba_state, sd);
+}
+
+/*
+ * S5K4BA register structure : 2bytes address, 2bytes value
+ * retry on write failure up-to 5 times
+ */
+static inline int s5k4ba_write(struct v4l2_subdev *sd, u8 addr, u8 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg[1];
+	unsigned char reg[2];
+	int err = 0;
+	int retry = 0;
+
+
+	if (!client->adapter)
+		return -ENODEV;
+
+again:
+	msg->addr = client->addr;
+	msg->flags = 0;
+	msg->len = 2;
+	msg->buf = reg;
+
+	reg[0] = addr & 0xff;
+	reg[1] = val & 0xff;
+
+	err = i2c_transfer(client->adapter, msg, 1);
+	if (err >= 0)
+		return err;	/* Returns here on success */
+
+	/* abnormal case: retry 5 times */
+	if (retry < 5) {
+		dev_err(&client->dev, "%s: address: 0x%02x%02x, " \
+			"value: 0x%02x%02x\n", __func__, \
+			reg[0], reg[1], reg[2], reg[3]);
+		retry++;
+		goto again;
+	}
+
+	return err;
+}
+
+static int s5k4ba_i2c_write(struct v4l2_subdev *sd, unsigned char i2c_data[],
+				unsigned char length)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned char buf[length], i;
+	struct i2c_msg msg = {client->addr, 0, length, buf};
+
+	for (i = 0; i < length; i++)
+		buf[i] = i2c_data[i];
+
+	return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+}
+
+static int s5k4ba_write_regs(struct v4l2_subdev *sd, unsigned char regs[],
+				int size)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int i, err;
+
+	for (i = 0; i < size; i++) {
+		err = s5k4ba_i2c_write(sd, &regs[i], sizeof(regs[i]));
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	return 0;	/* FIXME */
+}
+
+static const char *s5k4ba_querymenu_wb_preset[] = {
+	"WB Tungsten", "WB Fluorescent", "WB sunny", "WB cloudy", NULL
+};
+
+static const char *s5k4ba_querymenu_effect_mode[] = {
+	"Effect Sepia", "Effect Aqua", "Effect Monochrome",
+	"Effect Negative", "Effect Sketch", NULL
+};
+
+static const char *s5k4ba_querymenu_ev_bias_mode[] = {
+	"-3EV",	"-2,1/2EV", "-2EV", "-1,1/2EV",
+	"-1EV", "-1/2EV", "0", "1/2EV",
+	"1EV", "1,1/2EV", "2EV", "2,1/2EV",
+	"3EV", NULL
+};
+
+static struct v4l2_queryctrl s5k4ba_controls[] = {
+	{
+		/*
+		 * For now, we just support in preset type
+		 * to be close to generic WB system,
+		 * we define color temp range for each preset
+		 */
+		.id = V4L2_CID_WHITE_BALANCE_TEMPERATURE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "White balance in kelvin",
+		.minimum = 0,
+		.maximum = 10000,
+		.step = 1,
+		.default_value = 0,	/* FIXME */
+	},
+	{
+		.id = V4L2_CID_WHITE_BALANCE_PRESET,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "White balance preset",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_wb_preset) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_AUTO_WHITE_BALANCE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Auto white balance",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_EXPOSURE,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Exposure bias",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_ev_bias_mode) - 2,
+		.step = 1,
+		.default_value = \
+			(ARRAY_SIZE(s5k4ba_querymenu_ev_bias_mode) - 2) / 2,
+			/* 0 EV */
+	},
+	{
+		.id = V4L2_CID_COLORFX,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Image Effect",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_effect_mode) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_CONTRAST,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Contrast",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SATURATION,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Saturation",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SHARPNESS,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Sharpness",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+};
+
+const char * const *s5k4ba_ctrl_get_menu(u32 id)
+{
+	switch (id) {
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		return s5k4ba_querymenu_wb_preset;
+
+	case V4L2_CID_COLORFX:
+		return s5k4ba_querymenu_effect_mode;
+
+	case V4L2_CID_EXPOSURE:
+		return s5k4ba_querymenu_ev_bias_mode;
+
+	default:
+		return v4l2_ctrl_get_menu(id);
+	}
+}
+
+static inline struct v4l2_queryctrl const *s5k4ba_find_qctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ba_controls); i++)
+		if (s5k4ba_controls[i].id == id)
+			return &s5k4ba_controls[i];
+
+	return NULL;
+}
+
+static int s5k4ba_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ba_controls); i++) {
+		if (s5k4ba_controls[i].id == qc->id) {
+			memcpy(qc, &s5k4ba_controls[i], \
+				sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int s5k4ba_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	struct v4l2_queryctrl qctrl;
+
+	qctrl.id = qm->id;
+	s5k4ba_queryctrl(sd, &qctrl);
+
+	return v4l2_ctrl_query_menu(qm, &qctrl, s5k4ba_ctrl_get_menu(qm->id));
+}
+
+/*
+ * Clock configuration
+ * Configure expected MCLK from host and return EINVAL if not supported clock
+ * frequency is expected
+ *	freq : in Hz
+ *	flag : not supported for now
+ */
+static int s5k4ba_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
+{
+	int err = -EINVAL;
+
+	return err;
+}
+
+static int s5k4ba_enum_framesizes(struct v4l2_subdev *sd, \
+					struct v4l2_frmsizeenum *fsize)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ba_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ba_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = 0;
+
+	dev_dbg(&client->dev, "%s\n", __func__);
+
+	return err;
+}
+
+static int s5k4ba_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = 0;
+
+	dev_dbg(&client->dev, "%s: numerator %d, denominator: %d\n", \
+		__func__, param->parm.capture.timeperframe.numerator, \
+		param->parm.capture.timeperframe.denominator);
+
+	return err;
+}
+
+static int s5k4ba_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ba_state *state = to_state(sd);
+	struct s5k4ba_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		ctrl->value = userset.exposure_bias;
+		err = 0;
+		break;
+
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		ctrl->value = userset.auto_wb;
+		err = 0;
+		break;
+
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		ctrl->value = userset.manual_wb;
+		err = 0;
+		break;
+
+	case V4L2_CID_COLORFX:
+		ctrl->value = userset.effect;
+		err = 0;
+		break;
+
+	case V4L2_CID_CONTRAST:
+		ctrl->value = userset.contrast;
+		err = 0;
+		break;
+
+	case V4L2_CID_SATURATION:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+
+	case V4L2_CID_SHARPNESS:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+
+	default:
+		dev_err(&client->dev, "%s: no such ctrl\n", __func__);
+		break;
+	}
+
+	return err;
+}
+
+static int s5k4ba_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+#ifdef S5K4BA_COMPLETE
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_EXPOSURE\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_ev_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_ev_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_AUTO_WHITE_BALANCE\n", \
+			__func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_awb_enable[ctrl->value], \
+			sizeof(s5k4ba_regs_awb_enable[ctrl->value]));
+		break;
+
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		dev_dbg(&client->dev, "%s: V4L2_CID_WHITE_BALANCE_PRESET\n", \
+			__func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_wb_preset[ctrl->value], \
+			sizeof(s5k4ba_regs_wb_preset[ctrl->value]));
+		break;
+
+	case V4L2_CID_COLORFX:
+		dev_dbg(&client->dev, "%s: V4L2_CID_COLORFX\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_color_effect[ctrl->value], \
+			sizeof(s5k4ba_regs_color_effect[ctrl->value]));
+		break;
+
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&client->dev, "%s: V4L2_CID_CONTRAST\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_contrast_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_contrast_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_SATURATION:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SATURATION\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_saturation_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_saturation_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_SHARPNESS:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SHARPNESS\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_sharpness_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_sharpness_bias[ctrl->value]));
+		break;
+
+	default:
+		dev_err(&client->dev, "%s: no such control\n", __func__);
+		break;
+	}
+
+	if (err < 0)
+		goto out;
+	else
+		return 0;
+
+out:
+	dev_dbg(&client->dev, "%s: vidioc_s_ctrl failed\n", __func__);
+	return err;
+#else
+	return 0;
+#endif
+}
+
+static int s5k4ba_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: camera initialization start\n", __func__);
+
+	for (i = 0; i < S5K4BA_INIT_REGS; i++) {
+		err = s5k4ba_i2c_write(sd, s5k4ba_init_reg[i], \
+					sizeof(s5k4ba_init_reg[i]));
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+	if (err < 0) {
+		v4l_err(client, "%s: camera initialization failed\n", \
+			__func__);
+		return -EIO;	/* FIXME */
+	}
+
+	return 0;
+}
+
+static int s5k4ba_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *ffmt)
+{
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops s5k4ba_core_ops = {
+	.init = s5k4ba_init,	/* initializing API */
+	.queryctrl = s5k4ba_queryctrl,
+	.querymenu = s5k4ba_querymenu,
+	.g_ctrl = s5k4ba_g_ctrl,
+	.s_ctrl = s5k4ba_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k4ba_video_ops = {
+	.s_crystal_freq = s5k4ba_s_crystal_freq,
+	.enum_framesizes = s5k4ba_enum_framesizes,
+	.enum_frameintervals = s5k4ba_enum_frameintervals,
+	.s_mbus_fmt = s5k4ba_s_fmt,
+	.g_parm = s5k4ba_g_parm,
+	.s_parm = s5k4ba_s_parm,
+};
+
+static const struct v4l2_subdev_ops s5k4ba_ops = {
+	.core = &s5k4ba_core_ops,
+	.video = &s5k4ba_video_ops,
+};
+
+/*
+ * s5k4ba_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k4ba_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct s5k4ba_state *state;
+	struct v4l2_subdev *sd;
+
+	state = kzalloc(sizeof(struct s5k4ba_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K4BA_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k4ba_ops);
+	printk("%s\n", __func__);
+	dev_info(&client->dev, "s5k4ba has been probed\n");
+	return 0;
+}
+
+
+static int s5k4ba_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+	return 0;
+}
+
+static const struct i2c_device_id s5k4ba_id[] = {
+	{ S5K4BA_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k4ba_id);
+
+static struct i2c_driver s5k4ba_i2c_driver = {
+	.driver = {
+		.name	= S5K4BA_DRIVER_NAME,
+	},
+	.probe		= s5k4ba_probe,
+	.remove		= s5k4ba_remove,
+	.id_table	= s5k4ba_id,
+};
+
+static int __init s5k4ba_mod_init(void)
+{
+	return i2c_add_driver(&s5k4ba_i2c_driver);
+}
+
+static void __exit s5k4ba_mod_exit(void)
+{
+	i2c_del_driver(&s5k4ba_i2c_driver);
+}
+module_init(s5k4ba_mod_init);
+module_exit(s5k4ba_mod_exit);
+
+MODULE_DESCRIPTION("Samsung Electronics S5K4BA UXGA camera driver");
+MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k4ba.h b/drivers/media/video/s5k4ba.h
new file mode 100644
index 0000000..08de291
--- /dev/null
+++ b/drivers/media/video/s5k4ba.h
@@ -0,0 +1,1462 @@
+/* linux/drivers/media/video/s5k4ba.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver for S5K4BA (UXGA camera) from Samsung Electronics
+ * 1/4" 2.0Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define S5K4BA_COMPLETE
+#ifndef __S5K4BA_H__
+#define __S5K4BA_H__
+
+struct s5k4ba_reg {
+	unsigned char addr;
+	unsigned char val;
+};
+
+struct s5k4ba_regset_type {
+	unsigned char *regset;
+	int len;
+};
+
+/*
+ * Macro
+ */
+#define REGSET_LENGTH(x)	(sizeof(x)/sizeof(s5k4ba_reg))
+
+/*
+ * User defined commands
+ */
+/* S/W defined features for tune */
+#define REG_DELAY	0xFF00	/* in ms */
+#define REG_CMD		0xFFFF	/* Followed by command */
+
+/* Following order should not be changed */
+enum image_size_s5k4ba {
+	/* This SoC supports upto UXGA (1600*1200) */
+#if 0
+	QQVGA,	/* 160*120*/
+	QCIF,	/* 176*144 */
+	QVGA,	/* 320*240 */
+	CIF,	/* 352*288 */
+	VGA,	/* 640*480 */
+#endif
+	SVGA,	/* 800*600 */
+#if 0
+	HD720P,	/* 1280*720 */
+	SXGA,	/* 1280*1024 */
+	UXGA,	/* 1600*1200 */
+#endif
+};
+
+/*
+ * Following values describe controls of camera
+ * in user aspect and must be match with index of s5k4ba_regset[]
+ * These values indicates each controls and should be used
+ * to control each control
+ */
+enum s5k4ba_control {
+	S5K4BA_INIT,
+	S5K4BA_EV,
+	S5K4BA_AWB,
+	S5K4BA_MWB,
+	S5K4BA_EFFECT,
+	S5K4BA_CONTRAST,
+	S5K4BA_SATURATION,
+	S5K4BA_SHARPNESS,
+};
+
+#define S5K4BA_REGSET(x)	{	\
+	.regset = x,			\
+	.len = sizeof(x)/sizeof(s5k4ba_reg),}
+
+
+/*
+ * User tuned register setting values
+ */
+static unsigned char s5k4ba_init_reg[][2] = {
+	//{0xfc, 0x01},
+	//{0x03, 0x00},
+	//{0xfc, 0x01},
+	//{0x03, 0x01},	/* sw reset */
+
+	{0xfc, 0x07},
+	{0x66, 0x01},   /* Watch Dog Time On */
+	{0xfc, 0x00},
+	{0x00, 0xAA},	/* For EDS Check */
+	{0x21, 0x03},	/* peter0223 */
+	{0xfc, 0x01},
+	{0x04, 0x01},	/* ARM Clock Divider */
+
+	{0xfc, 0x02},
+	{0x30, 0x90},	/* Analog offset */
+	{0x37, 0x0d},	/* Global Gain */
+	{0x2d, 0x48},	/* Double Shutter */
+	{0x60, 0x00},	/* Blank_Adrs */
+
+	{0x45, 0x1e},	/*0e// CDS Timing for Average Sub_Sampling */
+	{0x47, 0x2f},
+	{0x02, 0x0e},	/* ADC Resolution */
+	//{0x02, 0x1d},	/* ADC Resolution */
+	{0x3d, 0x06},	/* Frame ADLC */
+	{0x4d, 0x08},	/* Doubler Volatage */
+	{0x54, 0x02},	/* Double Shutter */
+	{0x55, 0x1e},	/* Line ADLC */
+	{0x56, 0x30},	/* */
+	{0x59, 0x00},	/* LineADLC offset */
+	{0x5b, 0x08},	/* R_Ref_Ctrl */
+	{0x44, 0x63},	/* CLP_EN */
+	{0x4A, 0x10},	/* Clamp Control */
+	{0x42, 0x02},	/* */
+	{0x43, 0xef},	/* */
+
+	/*========================================================== */
+	/*	Table Set for Sub-Sampling */
+	/*========================================================== */
+	{0xfc, 0x03},
+	{0x2c, 0x00},	/* crcb_sel for Sub-Sampling Table */
+	{0x05, 0x46},	/* Output Image Size Set for Capture */
+	{0x07, 0xb6},
+	{0x0e, 0x04},
+	{0x12, 0x03},
+
+	{0xfc, 0x04},
+	{0x32, 0x04},
+	{0x33, 0xbc},
+
+	{0xfc, 0x04},
+	{0xc5, 0x26},	/* Output Image Size Set for Preview */
+	{0xc7, 0x5e},
+	{0xce, 0x04},
+	{0xd2, 0x04},
+
+	{0xec, 0x06},	/*CrCb sel = YCBYCR(0x06) by jsgood */
+	{0xc0, 0x06},
+	{0xc1, 0x70},
+	{0xc2, 0x02},
+	{0xc3, 0x87},
+
+	{0xfc, 0x07},
+	{0x05, 0x00},
+	{0x06, 0x00},
+	{0x07, 0x8b},
+	{0x08, 0xf5},
+	{0x09, 0x00},
+	{0x0a, 0xb4},
+	{0x0b, 0x00},
+	{0x0c, 0xea},
+	{0x0d, 0x00},
+	{0x0e, 0x40},
+
+	{0xfc, 0x00},
+	{0x70, 0x02},
+
+	/* Jeongyun added still shot cbcr_sel */
+	{0xfc, 0x03},
+	{0x2c, 0x00},
+	{0x5c, 0x00},
+	{0x8c, 0x00},
+	{0xbc, 0x00},
+	{0xfc, 0x04},
+	{0x5c, 0x00},
+
+
+	/*========================================================== */
+	/*	COMMAND SET */
+	/*========================================================== */
+	{0xfc, 0x00},
+	{0x73, 0x21},	/* Frmae AE Enable peter */
+	{0x20, 0x02},	/* Change AWB Mode */
+
+	{0xfc, 0x00},
+	{0x6c, 0xb0},	/* AE target */
+	{0x6d, 0x00},
+
+	{0xfc, 0x20},
+	{0x16, 0x5a},	/* for Prevating AE Hunting */
+
+	{0xfc, 0x00},
+	{0x78, 0x6a},	/* AGC Max */
+	{0xfc, 0x20},
+	{0x16, 0x60},	/* Frame AE Start */
+
+	{0xfc, 0x20},
+	{0x57, 0x18},	/* Stable_Frame_AE */
+	{0x2C, 0x30},	/* For Forbidden Area */
+	{0x2E, 0x00},	/* For Forbidden Area */
+	{0x14, 0x70},
+	{0x01, 0x00},	/* Stepless_Off */
+
+	{0xfc, 0x07},
+	{0x11, 0x02},	/* AWB G Gain offset */
+
+	{0xfc, 0x07},
+	{0x3e, 0x0a},	/* AWB Cut R max */
+
+	{0xfc, 0x01},
+	{0xc8, 0xd0},	/* AWB Y Max e0 */
+	{0xfc, 0x00},
+	{0x3e, 0x20},	/*30 AWB Y_min */
+	{0x3d, 0x10},	/* AWB Y_min Low */
+	{0xfc, 0x22},
+	{0x8c, 0x04},	/* AWB Min Y Weight */
+	{0x8d, 0x16},	/* AWB Max Y Weight */
+
+	{0xfc, 0x00},
+	{0x32, 0x04},	/* AWB moving average 8 frame */
+	{0x81, 0x10},	/* AWB G gain suppress Disable */
+	{0xbc, 0xf0},
+
+	{0x29, 0x04},	/* Y level H */
+	{0x2a, 0x00},	/* Y level L */
+	{0x2b, 0x03},	/* color level H */
+	{0x2c, 0xc8},	/* color level L */
+
+	{0xfc, 0x07},
+	{0x37, 0x00},	/* Flicker Add for 32Mhz */
+	{0xfc, 0x00},
+	/*{0x72, 0x01},	// Flicker for 13.5MHz */
+	{0x72, 0xa0},	/* Flicker for 32MHz */
+	{0x74, 0x08},	/* flicker 60Hz Fix */
+
+	{0xfc, 0x20},
+	{0x02, 0x02},	/* Flicker Dgain Mode */
+
+	{0xfc, 0x00},
+	/*{0x23, 0x40},  // Mirror Option */
+	{0x62, 0x0a},	/* Mirror Option */
+
+	{0xfc, 0x02},
+	{0x4e, 0x00},	/* IO current 8mA set */
+	{0x4e, 0x00},	/* IO current 8mA set */
+	{0x4e, 0x00},	/* IO current 8mA set */
+	{0x4e, 0x00},	/* IO current 8mA set */
+	{0x4f, 0x0a},	/* 2a IO current 48mA set */
+	{0x4f, 0x0a},	/* IO current 48mA set */
+	{0x4f, 0x0a},	/* IO current 48mA set */
+	{0x4f, 0x0a},	/* IO current 48mA set */
+
+	{0xfc, 0x01},
+	{0x0c, 0x03},	/* Full YC Enable */
+	/*{0x0c,03},	// Full YC Enable */
+	/*{0x02,02},	// crcb_sel */
+	/*{0x02,02},	// crcb_sel  peter0222 */
+	/*{0x01,01},	// pclk      peter0222 */
+	/*{0x01,01}, */
+
+	/*========================================================== */
+	/*	COLOR MATRIX */
+	/*========================================================== */
+	{0xfc, 0x01},	/* color matrix */
+	{0x51, 0x0A},
+	{0x52, 0x42},
+	{0x53, 0xF9},
+	{0x54, 0x80},
+	{0x55, 0x00},
+	{0x56, 0x3D},
+
+	{0x57, 0xFE},
+	{0x58, 0x0B},
+	{0x59, 0x06},
+	{0x5A, 0x9C},
+	{0x5B, 0xFF},
+	{0x5C, 0x59},
+
+	{0x5D, 0xFF},
+	{0x5E, 0xD8},
+	{0x5F, 0xFC},
+	{0x60, 0x2E},
+	{0x61, 0x07},
+	{0x62, 0xFA},
+
+	/*========================================================== */
+	/*	EDGE ENHANCEMENT */
+	/*========================================================== */
+	{0xfc, 0x00},
+	{0x89, 0x03},	/* Edge Suppress On */
+	{0xfc, 0x0b},
+	{0x42, 0x50},	/* Edge AGC MIN */
+	{0x43, 0x60},	/* Edge AGC MAX */
+	{0x45, 0x18},	/* positive gain AGC MIN */
+	{0x49, 0x0a},	/* positive gain AGC MAX */
+	{0x4d, 0x18},	/* negative gain AGC MIN */
+	{0x51, 0x0a},	/* negative gain AGC MAX */
+
+	{0xfc, 0x05},
+	{0x34, 0x20},	/* APTCLP */
+	{0x35, 0x09},	/* APTSC */
+	{0x36, 0x0b},	/* ENHANCE */
+	{0x3f, 0x00},	/* NON-LIN */
+	{0x42, 0x10},	/* EGFALL */
+	{0x43, 0x00},	/* HLFALL */
+	{0x45, 0xa0},	/* EGREF */
+	{0x46, 0x7a},	/* HLREF */
+	{0x47, 0x40},	/* LLREF */
+	{0x48, 0x0c},
+	{0x49, 0x31},	/* CSSEL  EGSEL  CS_DLY */
+
+	{0x40, 0x41},	/* Y delay */
+
+	/*========================================================== */
+	/*	GAMMA */
+	/*========================================================== */
+	{0xfc, 0x01},
+
+	{0x6F, 0x0A},	/* R */
+	{0x70, 0x1A},
+	{0x71, 0x7A},
+	{0x72, 0xF8},
+	{0x73, 0x00},
+
+	{0x74, 0xA0},
+	{0x75, 0x18},
+	{0x76, 0x65},
+	{0x77, 0xAD},
+	{0x78, 0x6A},
+
+	{0x79, 0xE2},
+	{0x7A, 0x12},
+	{0x7B, 0x3D},
+	{0x7C, 0x5A},
+	{0x7D, 0xBF},
+
+	{0x7E, 0x72},
+	{0x7F, 0x88},
+	{0x80, 0x9D},
+	{0x81, 0xB0},
+	{0x82, 0xFF},
+
+	{0x83, 0xC0},
+	{0x84, 0xCF},
+	{0x85, 0xDA},
+	{0x86, 0xFC},
+
+	{0x87, 0x08},	/*G */
+	{0x88, 0x12},
+	{0x89, 0x42},
+	{0x8A, 0xBA},
+	{0x8B, 0x00},
+
+	{0x8C, 0x75},
+	{0x8D, 0xED},
+	{0x8E, 0x42},
+	{0x8F, 0x80},
+	{0x90, 0x5A},
+
+	{0x91, 0xB5},
+	{0x92, 0xE5},
+	{0x93, 0x10},
+	{0x94, 0x35},
+	{0x95, 0xAF},
+
+	{0x96, 0x55},
+	{0x97, 0x70},
+	{0x98, 0x88},
+	{0x99, 0x9D},
+	{0x9A, 0xFF},
+
+	{0x9B, 0xB1},
+	{0x9C, 0xC4},
+	{0x9D, 0xD5},
+	{0x9E, 0xFC},
+
+	{0x9F, 0x05},	/*B */
+	{0xA0, 0x18},
+	{0xA1, 0x42},
+	{0xA2, 0xd7},
+	{0xA3, 0x00},
+
+	{0xA4, 0xB6},
+	{0xA5, 0x3b},
+	{0xA6, 0x88},
+	{0xA7, 0xC8},
+	{0xA8, 0x6A},
+
+	{0xA9, 0x00},
+	{0xAA, 0x30},
+	{0xAB, 0x58},
+	{0xAC, 0x78},
+	{0xAD, 0xFF},
+
+	{0xAE, 0x90},
+	{0xAF, 0xA5},
+	{0xB0, 0xB6},
+	{0xB1, 0xC5},
+	{0xB2, 0xFF},
+
+	{0xB3, 0xD0},
+	{0xB4, 0xD6},
+	{0xB5, 0xDA},
+	{0xB6, 0xFC},
+
+	/*========================================================== */
+	/*	HUE CONTROL */
+	/*========================================================== */
+	{0xfc, 0x00},
+	{0x48, 0x34},	/* 2000K */
+	{0x49, 0x34},
+	{0x4a, 0xf4},
+	{0x4b, 0x00},
+	{0x4c, 0x44},
+	{0x4d, 0x3c},
+	{0x4e, 0xf0},
+	{0x4f, 0x0c},
+
+	{0x50, 0x34},	/* 3000K */
+	{0x51, 0x34},
+	{0x52, 0xf4},
+	{0x53, 0x00},
+	{0x54, 0x44},
+	{0x55, 0x3c},
+	{0x56, 0xf0},
+	{0x57, 0x0c},
+
+	{0x58, 0x34},	/* 5100K */
+	{0x59, 0x30},
+	{0x5a, 0x00},
+	{0x5b, 0x04},
+	{0x5c, 0x40},
+	{0x5d, 0x2c},
+	{0x5e, 0xfc},
+	{0x5f, 0x04},
+	/*========================================================== */
+	/*	UPPRE0x0x FUNCTION */
+	/*========================================================== */
+	{0xfc, 0x00},
+	{0x7e, 0xf4},
+
+	/*========================================================== */
+	/*	BPR */
+	/*========================================================== */
+	{0xfc, 0x01},
+	{0x3d, 0x10},
+
+	{0xfc, 0x0b},
+	{0x0b, 0x00},	/* ISP BPR On start */
+	{0x0c, 0x20},	/* Th13 AGC Min */
+	{0x0d, 0x40},	/* Th13 AGC Max */
+	{0x0e, 0x00},	/* Th1 Max H for AGCMIN */
+	{0x0f, 0x20},	/* Th1 Max L for AGCMIN */
+	{0x10, 0x00},	/* Th1 Min H for AGCMAX */
+	{0x11, 0x10},	/* Th1 Min L for AGCMAX */
+	{0x12, 0x00},	/* Th3 Max H for AGCMIN */
+	{0x13, 0x00},	/* Th3 Max L for AGCMIN */
+	{0x14, 0xff},	/* Th3 Min H for AGCMAX */
+	{0x15, 0xff},	/* Th3 Min L for AGCMAX */
+	{0x16, 0x20},	/* Th57 AGC Min */
+	{0x17, 0x40},	/* Th57 AGC Max */
+	{0x18, 0x00},	/* Th5 Max H for AGCMIN */
+	{0x19, 0x00},	/* Th5 Max L for AGCMIN */
+	{0x1a, 0x00},	/* Th5 Min H for AGCMAX */
+	{0x1b, 0x20},	/* Th5 Min L for AGCMAX */
+	{0x1c, 0x00},	/* Th7 Max H for AGCMIN */
+	{0x1d, 0x00},	/* Th7 Max L for AGCMIN */
+	{0x1e, 0x00},	/* Th7 Min H for AGCMAX */
+	{0x1f, 0x20},	/* Th7 Min L for AGCMAX */
+
+	/*========================================================== */
+	/*	GR/GB CORRECTION */
+	/*========================================================== */
+	{0xfc, 0x01},
+	{0x45, 0x0c},
+
+	{0xfc, 0x0b},
+	{0x21, 0x00},	/* start AGC */
+	{0x22, 0x18},	/* AGCMIN */
+	{0x23, 0x58},	/* AGCMAX */
+	{0x24, 0x0d}, 	/* G Th AGCMIN */
+	{0x25, 0x30}, 	/* G Th AGCMAX */
+	{0x26, 0x0d}, 	/* RB Th AGCMIN */
+	{0x27, 0x30}, 	/* RB Th AGCMAX */
+
+	/*========================================================== */
+	/*	NR */
+	/*========================================================== */
+	{0xfc, 0x01},
+	{0x4C, 0x01},	/* NR Enable */
+	{0x49, 0x15},	/* Sig_Th Mult */
+	{0x4B, 0x0A},	/* Pre_Th Mult */
+
+	{0xfc, 0x0b},
+	{0x28, 0x00},	/* NR start AGC	 */
+	{0x29, 0x00},	/* SIG Th AGCMIN H */
+	{0x2a, 0x14},	/* SIG Th AGCMIN L */
+	{0x2b, 0x00},	/* SIG Th AGCMAX H */
+	{0x2c, 0x14},	/* SIG Th AGCMAX L */
+	{0x2d, 0x00},	/* PRE Th AGCMIN H */
+	{0x2e, 0x90},	/* PRE Th AGCMIN L */
+	{0x2f, 0x01},	/* PRE Th AGCMAX H */
+	{0x30, 0x00},	/* PRE Th AGCMAX L */
+	{0x31, 0x00},	/* POST Th AGCMIN H */
+	{0x32, 0xa0},	/* POST Th AGCMIN L */
+	{0x33, 0x01},	/* POST Th AGCMAX H */
+	{0x34, 0x10},	/* POST Th AGCMAX L */
+
+	/*========================================================== */
+	/*	1D-Y/C-SIGMA-LPF */
+	/*========================================================== */
+	{0xfc, 0x01},
+//	{0x05, 0xe0},
+	{0x05, 0xc0},
+
+	{0xfc, 0x0b},
+	{0x35, 0x00},	/* YLPF start AGC */
+	{0x36, 0x40},	/* YLPF01 AGCMIN */
+	{0x37, 0x60},	/* YLPF01 AGCMAX */
+	{0x38, 0x00},	/* YLPF SIG01 Th AGCMINH */
+	{0x39, 0x18},	/* YLPF SIG01 Th AGCMINL */
+	{0x3a, 0x00},	/* YLPF SIG01 Th AGCMAXH */
+	{0x3b, 0x40},	/* YLPF SIG01 Th AGCMAXH */
+	{0x3c, 0x50},	/* YLPF02 AGCMIN */
+	{0x3d, 0x60},	/* YLPF02 AGCMAX */
+	{0x3e, 0x00},	/* YLPF SIG02 Th AGCMINH */
+	{0x3f, 0x30},	/* YLPF SIG02 Th AGCMINL */
+	{0x40, 0x00},	/* YLPF SIG02 Th AGCMAXH */
+	{0x41, 0x40},	/* YLPF SIG02 Th AGCMAXH */
+	{0xd4, 0x40},	/* CLPF AGCMIN */
+	{0xd5, 0x60},	/* CLPF AGCMAX */
+	{0xd6, 0xb0},	/* CLPF SIG01 Th AGCMIN */
+	{0xd7, 0xf0},	/* CLPF SIG01 Th AGCMAX */
+	{0xd8, 0xb0},	/* CLPF SIG02 Th AGCMIN */
+	{0xd9, 0xf0},	/* CLPF SIG02 Th AGCMAX */
+
+	/*========================================================== */
+	/*	COLOR SUPPRESS */
+	/*========================================================== */
+	{0xfc, 0x0b},
+	{0x08, 0x58},	/* Color suppress AGC MIN */
+	{0x09, 0x03},	/* Color suppress MIN H */
+	{0x0a, 0x80},	/* Color suppress MIN L */
+
+	/*========================================================== */
+	/*	SHADING */
+	/*========================================================== */
+	{0xfc, 0x09},
+	 /*Shading file for 3BAFX */
+	/*s90000// shading off */
+	/* DSP9_SH_WIDTH_H */
+	{0x01, 0x06},
+	{0x02, 0x40},
+	/* DSP9_SH_HEIGHT_H */
+	{0x03, 0x04},
+	{0x04, 0xB0},
+	/* DSP9_SH_XCH_R */
+	{0x05, 0x03},
+	{0x06, 0x1A},
+	{0x07, 0x02},
+	{0x08, 0x4E},
+	/* DSP9_SH_XCH_G */
+	{0x09, 0x03},
+	{0x0A, 0x27},
+	{0x0B, 0x02},
+	{0x0C, 0x11},
+	/* DSP9_SH_XCH_B */
+	{0x0D, 0x03},
+	{0x0E, 0x15},
+	{0x0F, 0x01},
+	{0x10, 0xE3},
+	/* DSP9_SH_Del_eH_R */
+	{0x1D, 0x85},
+	{0x1E, 0x55},
+	{0x1F, 0x77},
+	{0x20, 0x9E},
+	{0x23, 0x7F},
+	{0x24, 0xE6},
+	{0x21, 0x7F},
+	{0x22, 0xE6},
+	/* DSP9_SH_Del_eH_G */
+	{0x25, 0x82},
+	{0x26, 0x9A},
+	{0x27, 0x78},
+	{0x28, 0xC0},
+	{0x2B, 0x76},
+	{0x2C, 0x07},
+	{0x29, 0x86},
+	{0x2A, 0x09},
+	/* DSP9_SH_Del_eH_B */
+	{0x2D, 0x85},
+	{0x2E, 0x55},
+	{0x2F, 0x75},
+	{0x30, 0x6D},
+	{0x33, 0x74},
+	{0x34, 0xA2},
+	{0x31, 0x84},
+	{0x32, 0xA2},
+	/* DSP9_SH_VAL_R0H */
+	{0x35, 0x01},
+	{0x36, 0x01},
+	{0x37, 0x01},
+	{0x38, 0x14},
+	{0x39, 0x01},
+	{0x3A, 0x45},
+	{0x3B, 0x01},
+	{0x3C, 0x8A},
+	{0x3D, 0x01},
+	{0x3E, 0xA3},
+	{0x3F, 0x01},
+	{0x40, 0xB9},
+	{0x41, 0x01},
+	{0x42, 0xD9},
+	{0x43, 0x01},
+	{0x44, 0xF6},
+	/* DSP9_SH_VAL_G0H */
+	{0x45, 0x01},
+	{0x46, 0x00},
+	{0x47, 0x01},
+	{0x48, 0x0E},
+	{0x49, 0x01},
+	{0x4A, 0x34},
+	{0x4B, 0x01},
+	{0x4C, 0x68},
+	{0x4D, 0x01},
+	{0x4E, 0x76},
+	{0x4F, 0x01},
+	{0x50, 0x94},
+	{0x51, 0x01},
+	{0x52, 0xAB},
+	{0x53, 0x01},
+	{0x54, 0xC3},
+	/* DSP9_SH_VAL_B0H */
+	{0x55, 0x01},
+	{0x56, 0x00},
+	{0x57, 0x01},
+	{0x58, 0x0C},
+	{0x59, 0x01},
+	{0x5A, 0x2B},
+	{0x5B, 0x01},
+	{0x5C, 0x5D},
+	{0x5D, 0x01},
+	{0x5E, 0x70},
+	{0x5F, 0x01},
+	{0x60, 0x8A},
+	{0x61, 0x01},
+	{0x62, 0xA1},
+	{0x63, 0x01},
+	{0x64, 0xB3},
+	/* DSP9_SH_M_R2_R1H */
+	{0x65, 0x00},
+	{0x66, 0x98},
+	{0x67, 0x2C},
+	{0x68, 0x02},
+	{0x69, 0x60},
+	{0x6A, 0xB0},
+	{0x6B, 0x05},
+	{0x6C, 0x59},
+	{0x6D, 0x8C},
+	{0x6E, 0x07},
+	{0x6F, 0x48},
+	{0x70, 0x1B},
+	{0x71, 0x09},
+	{0x72, 0x82},
+	{0x73, 0xC0},
+	{0x74, 0x0C},
+	{0x75, 0x09},
+	{0x76, 0x7B},
+	{0x77, 0x0E},
+	{0x78, 0xDC},
+	{0x79, 0x4D},
+	/* DSP9_SH_M_R2_G1H */
+	{0x7A, 0x00},
+	{0x7B, 0xAD},
+	{0x7C, 0x76},
+	{0x7D, 0x02},
+	{0x7E, 0xB5},
+	{0x7F, 0xD7},
+	{0x80, 0x06},
+	{0x81, 0x19},
+	{0x82, 0x23},
+	{0x83, 0x08},
+	{0x84, 0x4C},
+	{0x85, 0xE2},
+	{0x86, 0x0A},
+	{0x87, 0xD7},
+	{0x88, 0x5C},
+	{0x89, 0x0D},
+	{0x8A, 0xB8},
+	{0x8B, 0x90},
+	{0x8C, 0x10},
+	{0x8D, 0xF0},
+	{0x8E, 0x7F},
+	/* DSP9_SH_M_R2_B1H */
+	{0x8F, 0x00},
+	{0x90, 0xC1},
+	{0x91, 0xD0},
+	{0x92, 0x03},
+	{0x93, 0x07},
+	{0x94, 0x3F},
+	{0x95, 0x06},
+	{0x96, 0xD0},
+	{0x97, 0x4F},
+	{0x98, 0x09},
+	{0x99, 0x46},
+	{0x9A, 0x32},
+	{0x9B, 0x0C},
+	{0x9C, 0x1C},
+	{0x9D, 0xFE},
+	{0x9E, 0x0F},
+	{0x9F, 0x54},
+	{0xA0, 0xB1},
+	{0xA1, 0x12},
+	{0xA2, 0xED},
+	{0xA3, 0x4C},
+	/* DSP9_SH_SUB_RR0H */
+	{0xA4, 0x6B},
+	{0xA5, 0xAA},
+	{0xA6, 0x23},
+	{0xA7, 0xE3},
+	{0xA8, 0x15},
+	{0xA9, 0x88},
+	{0xAA, 0x21},
+	{0xAB, 0x20},
+	{0xAC, 0x1C},
+	{0xAD, 0xB6},
+	{0xAE, 0x19},
+	{0xAF, 0x55},
+	{0xB0, 0x16},
+	{0xB1, 0xAA},
+	/* DSP9_SH_SUB_RG0H */
+	{0xB2, 0x5E},
+	{0xB3, 0x74},
+	{0xB4, 0x1F},
+	{0xB5, 0x7C},
+	{0xB6, 0x12},
+	{0xB7, 0xE4},
+	{0xB8, 0x1D},
+	{0xB9, 0x10},
+	{0xBA, 0x19},
+	{0xBB, 0x30},
+	{0xBC, 0x16},
+	{0xBD, 0x39},
+	{0xBE, 0x13},
+	{0xBF, 0xE2},
+	/* DSP9_SH_SUB_RB0H */
+	{0xC0, 0x54},
+	{0xC1, 0x89},
+	{0xC2, 0x1C},
+	{0xC3, 0x2D},
+	{0xC4, 0x10},
+	{0xC5, 0xE8},
+	{0xC6, 0x1A},
+	{0xC7, 0x02},
+	{0xC8, 0x16},
+	{0xC9, 0x8A},
+	{0xCA, 0x13},
+	{0xCB, 0xE4},
+	{0xCC, 0x11},
+	{0xCD, 0xCC},
+
+	{0x00, 0x02},  /* {0xhading on */
+
+	/*========================================================== */
+	/*	X-SHADING */
+	/*========================================================== */
+	{0xfc, 0x1B},
+	{0x80, 0x01},
+	{0x81, 0x00},
+	{0x82, 0x4C},
+	{0x83, 0x00},
+	{0x84, 0x86},
+	{0x85, 0x03},
+	{0x86, 0x5E},
+	{0x87, 0x00},
+	{0x88, 0x07},
+	{0x89, 0xA4},
+	{0x90, 0x00},
+	{0x91, 0x12},
+	{0x92, 0x00},
+	{0x93, 0x12},
+	{0x94, 0x00},
+	{0x95, 0x12},
+	{0x96, 0x00},
+	{0x97, 0x12},
+	{0x98, 0x00},
+	{0x99, 0x12},
+	{0x9A, 0x00},
+	{0x9B, 0x12},
+	{0x9C, 0x00},
+	{0x9D, 0x12},
+	{0x9E, 0x00},
+	{0x9F, 0x12},
+	{0xA0, 0x00},
+	{0xA1, 0x12},
+	{0xA2, 0x00},
+	{0xA3, 0x12},
+	{0xA4, 0x00},
+	{0xA5, 0x12},
+	{0xA6, 0x00},
+	{0xA7, 0x12},
+	{0xA8, 0x00},
+	{0xA9, 0x12},
+	{0xAA, 0x00},
+	{0xAB, 0x12},
+	{0xAC, 0x00},
+	{0xAD, 0x12},
+	{0xAE, 0x00},
+	{0xAF, 0x12},
+	{0xB0, 0x00},
+	{0xB1, 0x12},
+	{0xB2, 0x00},
+	{0xB3, 0x12},
+	{0xB4, 0x00},
+	{0xB5, 0x12},
+	{0xB6, 0x00},
+	{0xB7, 0x15},
+	{0xB8, 0x00},
+	{0xB9, 0x12},
+	{0xBA, 0x00},
+	{0xBB, 0x12},
+	{0xBC, 0x00},
+	{0xBD, 0x12},
+	{0xBE, 0x00},
+	{0xBF, 0x12},
+	{0xC0, 0x00},
+	{0xC1, 0x12},
+	{0xC2, 0x00},
+	{0xC3, 0x12},
+	{0xC4, 0x00},
+	{0xC5, 0x12},
+	{0xC6, 0x00},
+	{0xC7, 0x12},
+	{0xC8, 0x00},
+	{0xC9, 0x12},
+	{0xCA, 0x00},
+	{0xCB, 0x12},
+	{0xCC, 0x00},
+	{0xCD, 0x12},
+	{0xCE, 0x00},
+	{0xCF, 0x12},
+	{0xD0, 0x00},
+	{0xD1, 0x12},
+	{0xD2, 0x00},
+	{0xD3, 0x12},
+	{0xD4, 0x00},
+	{0xD5, 0x12},
+		 /* x-shading temp. correlation factor */
+	{0xfc, 0x0b},
+	{0xda, 0x00},	/* t0(3100K) */
+	{0xdb, 0xac},
+	{0xdc, 0x01},	/* tc(5100K) */
+	{0xdd, 0x30},	/* default eeh */
+
+	{0xfc, 0x00},
+	{0x81, 0x10},	/* xshading tem */
+
+	{0xfc, 0x1b},
+	{0x80, 0x01},	/* X-Shading On */
+
+	/*========================================================== */
+	/*	AE WINDOW WEIGHT */
+	/*========================================================== */
+	{0xfc, 0x00},
+	{0x03, 0x4b},	/* AE Suppress On */
+
+	{0xfc, 0x06},
+	{0x01, 0x35},	/* UXGA AE Window */
+	{0x03, 0xc2},
+	{0x05, 0x48},
+	{0x07, 0xb8},
+	{0x31, 0x2a},	/* Subsampling AE Window */
+	{0x33, 0x61},
+	{0x35, 0x28},
+	{0x37, 0x5c},
+	{0x39, 0x28},
+	{0x3B, 0x5A},
+	{0x3D, 0x10},	/* 1c */
+	{0x3F, 0x44},
+
+	{0xfc, 0x20},
+	{0x60, 0x11},
+	{0x61, 0x11},
+	{0x62, 0x11},
+	{0x63, 0x11},
+	{0x64, 0x11},
+	{0x65, 0x22},
+	{0x66, 0x22},
+	{0x67, 0x11},
+	{0x68, 0x11},
+	{0x69, 0x33},
+	{0x6a, 0x33},
+	{0x6b, 0x11},
+	{0x6c, 0x12},
+	{0x6d, 0x55},
+	{0x6e, 0x55},
+	{0x6f, 0x21},
+	{0x70, 0x13},
+	{0x71, 0x55},
+	{0x72, 0x55},
+	{0x73, 0x31},
+	{0x74, 0x33},
+	{0x75, 0x33},
+	{0x76, 0x33},
+	{0x77, 0x33},
+
+	/*========================================================== */
+	/*	SAIT AWB */
+	/*========================================================== */
+	/*================================= */
+	/* White Point */
+	/*================================= */
+	{0xfc, 0x22},	/* White Point (For Hue Control & MWB) */
+	{0x01, 0xD0},	/* D65 */
+	{0x03, 0x9B},
+	{0x05, 0xC0},	/* 5000K */
+	{0x07, 0xB8},
+	{0x09, 0xA7},	/* CWF */
+	{0x0b, 0xDC},
+	{0x0d, 0x98},	/* 3000K */
+	{0x0f, 0xE0},
+	{0x11, 0x85},	/* A */
+	{0x12, 0x00},
+	{0x13, 0xF6},
+	{0x15, 0x80},	/* 2000K */
+	{0x16, 0x01},
+	{0x17, 0x00},
+
+	/*================================= */
+	/* Basic Setting */
+	/*================================= */
+	{0xfc, 0x22},
+	{0xA0, 0x01},
+	{0xA1, 0x3F},
+	{0xA2, 0x0E},
+	{0xA3, 0x65},
+	{0xA4, 0x07},
+	{0xA5, 0xF4},
+	{0xA6, 0x11},
+	{0xA7, 0xC8},
+	{0xA9, 0x02},
+	{0xAA, 0x43},
+	{0xAB, 0x26},
+	{0xAC, 0x1F},
+	{0xAD, 0x02},
+	{0xAE, 0x2C},
+	{0xAF, 0x19},
+	{0xB0, 0x0F},
+
+	{0x94, 0x3C},
+	{0x95, 0xCC},
+	{0x96, 0x5C},
+	{0x97, 0x4D},
+	{0xD0, 0xA8},
+	{0xD1, 0x29},
+	{0xD2, 0x39},
+	{0xD3, 0x22},
+	{0xD4, 0x30},
+	{0xDB, 0x29},
+	{0xDC, 0x7E},
+	{0xDD, 0x22},
+
+	{0xE7, 0x00},
+	{0xE8, 0xca},
+	{0xE9, 0x00},
+	{0xEA, 0x62},
+	{0xEB, 0x00},
+	{0xEC, 0x00},
+	{0xEE, 0x97},
+
+	/*================================= */
+	/* Pixel Filter Setting */
+	/*================================= */
+	{0xFC, 0x07},
+	{0x95, 0x8F},
+
+	{0xfc, 0x01},
+	{0xD3, 0x4B},
+	{0xD4, 0x00},
+	{0xD5, 0x38},
+	{0xD6, 0x00},
+	{0xD7, 0x60},
+	{0xD8, 0x00},
+	{0xD9, 0x4E},
+	{0xDA, 0x00},
+	{0xDB, 0x27},
+	{0xDC, 0x15},
+	{0xDD, 0x23},
+	{0xDE, 0xAD},
+	{0xDF, 0x24},
+	{0xE0, 0x01},
+	{0xE1, 0x17},
+	{0xE2, 0x4A},
+	{0xE3, 0x36},
+	{0xE4, 0x40},
+	{0xE5, 0x40},
+	{0xE6, 0x40},
+	{0xE7, 0x40},
+	{0xE8, 0x30},
+	{0xE9, 0x3D},
+	{0xEA, 0x17},
+	{0xEB, 0x01},
+
+	/*================================= */
+	/* Polygon AWB Region Tune */
+	/*================================= */
+	{0xfc, 0x22},
+	{0x18, 0x00},	/* 1 */
+	{0x19, 0x5a},
+	{0x1a, 0xf8},
+	{0x1b, 0x00},	/* 2 */
+	{0x1c, 0x59},
+	{0x1d, 0xCC},
+	{0x1e, 0x00},	/* 3 */
+	{0x1f, 0x74},
+	{0x20, 0xB3},
+	{0x21, 0x00},	/* 4 */
+	{0x22, 0x86},
+	{0x23, 0xA2},
+	{0x24, 0x00},	/* 5 */
+	{0x25, 0x94},
+	{0x26, 0x89},
+	{0x27, 0x00},	/* 6 */
+	{0x28, 0xA6},
+	{0x29, 0x76},
+	{0x2A, 0x00},	/* 7 */
+	{0x2B, 0xd0},
+	{0x2C, 0x5e},
+	{0x2D, 0x00},	/* 8 */
+	{0x2E, 0xfa},
+	{0x2F, 0x47},
+	{0x30, 0x00},	/* 9 */
+	{0x31, 0xfD},
+	{0x32, 0x5D},
+	{0x33, 0x00},	/* 10 */
+	{0x34, 0xBB},
+	{0x35, 0x7c},
+	{0x36, 0x00},	/* 11 */
+	{0x37, 0xAD},
+	{0x38, 0x88},
+	{0x39, 0x00},	/* 12 */
+	{0x3A, 0x9A},
+	{0x3B, 0xA3},
+	{0x3C, 0x00},	/* 13 */
+	{0x3D, 0x7C},
+	{0x3E, 0xDD},
+	{0x3F, 0x00},	/* 14 */
+	{0x40, 0x00},
+	{0x41, 0x00},
+
+	/*================================= */
+	/* Moving Equation Weight */
+	/*================================= */
+	{0xfc, 0x22},
+	{0x98, 0x07},
+
+	/*================================= */
+	/* EIT Threshold */
+	/*================================= */
+	{0xfc, 0x22},
+	{0xb1, 0x00},	/* {0xunny */
+	{0xb2, 0x03},
+	{0xb3, 0x00},
+	{0xb4, 0xc1},
+
+	{0xb5, 0x00},	/* Cloudy */
+	{0xb6, 0x05},
+	{0xb7, 0xc9},
+	{0xb9, 0x81},
+
+	{0xd7, 0x00},	/* Shade */
+	{0xd8, 0x35},
+	{0xd9, 0x20},
+	{0xda, 0x81},
+
+	/*================================= */
+	/* Gain Offset */
+	/*================================= */
+	{0xfc, 0x00},
+	{0x79, 0xF9},
+	{0x7A, 0x02},	/* Global AWB gain off{0xet */
+
+	{0xfc, 0x22},
+	{0x58, 0xf6},	/* D65 R Off{0xet */
+	{0x59, 0xff},	/* D65 B Off{0xet */
+	{0x5A, 0xfa},	/* 5000K R Off{0xet */
+	{0x5B, 0xFe},	/* 5000K B Off{0xet */
+	{0x5C, 0xfb},	/* CWF R Off{0xet */
+	{0x5D, 0xFe},	/* CWF B Off{0xet */
+	{0x5E, 0xfb},	/* 3000K R Off{0xet */
+	{0x5F, 0xFb},	/* 3000K B Off{0xet */
+	{0x60, 0xfb},	/* A R Off0xet */
+	{0x61, 0xfb},	/* A B Off0xet */
+	{0x62, 0xfb},	/* 2000K R Off0xet */
+	{0x63, 0xfb},	/* 2000K B Off0xet */
+
+	{0xde, 0x00},	/* LARGE OBJECT BUG FIX */
+	{0xf0, 0x6a},	/* RB Ratio */
+	/*================================= */
+	/* Green Stablity Enhance */
+	/*================================= */
+	{0xfc, 0x22},
+	{0xb9, 0x00},
+	{0xba, 0x00},
+	{0xbb, 0x00},
+	{0xbc, 0x00},
+	{0xe5, 0x01},
+	{0xe6, 0xff},
+
+	{0xbd, 0x90},
+
+	/*========================================================== */
+	/*	Special Effect */
+	/*========================================================== */
+	{0xfc, 0x07},	/* Special Effect */
+	{0x30, 0xc0},
+	{0x31, 0x20},
+	{0x32, 0x40},
+	{0x33, 0xc0},
+	{0x34, 0x00},
+	{0x35, 0xb0},
+
+	{0xfc, 0x00},
+	{0x73, 0x21},	/* Frame AE Enable */
+
+	{0xfc, 0x04},
+	{0xc0, 0x06},
+	{0xc1, 0x70},
+	{0xFF, 0xFF}	/* REGISTER END */
+};
+
+#ifdef USE_4BA_SVGA
+/* For SVGA ( 800 x 600) on 4BA module */
+static unsigned char s5k4ba_svga_reg[][2] = {
+	{0xfc, 0x02},
+	{0x2d, 0x48},
+	{0x44, 0x63},
+
+	{0xfc, 0x03},
+	{0x02, 0x04},
+	{0xfc, 0x20},
+	{0x14, 0x70},
+
+	{0xfc, 0x00},
+	{0x03, 0x4b},	/* AE/AWB On */
+	{0x7e, 0xf4},	/* Suppress On */
+	{0x89, 0x03},	/* Edge Suppress On */
+
+	{0xfc, 0x02},
+	{0x02, 0x0e},	/* sensor BPRoff */
+
+	{0xfc, 0x20},
+	{0x16, 0x60},	/* Frame AE Start */
+
+	{0xfc, 0x02},
+	{0x30, 0x90},	/* Analog offset */
+	{0x37, 0x0d},	/* Global Gain */
+	{0x60, 0x00},	/* Blank_Adrs */
+	{0x45, 0x0e},	/* CDS Timing for Average Sub_Sampling */
+	{0x47, 0x2f},
+
+	{0xfc, 0x01},
+	{0x9F, 0x05},	/* B */
+	{0xA0, 0x18},
+	{0xA1, 0x42},
+	{0xA2, 0xd7},
+	{0xA3, 0x00},
+
+	{0xA4, 0xB6},
+	{0xA5, 0x3b},
+	{0xA6, 0x88},
+	{0xA7, 0xC8},
+	{0xA8, 0x6A},
+
+	{0xfc, 0x05},
+	{0x34, 0x20},	/* APTCLP */
+	{0x35, 0x08},	/*9 //APTSC */
+
+	{0xfc, 0x00},	/* flash 0821 */
+	{0x32, 0x04},	/* AWB moving average 8 frame */
+
+	{0xfc, 0x01},
+	{0x01, 0x01},	/* Pclk inversion */
+
+	{0xfc, 0x00},
+	{0x02, 0x09},	/* 800 x 600 */
+
+	/*{0xfc, 0x01},
+	{0x02, 0x04},	// crcb_sel
+
+	{0xfc, 0x01},
+	{0x05, 0xe0},	// special eff con */
+
+	{0xFF, 0xFF} 	/* REGISTER END */
+};
+#endif
+#ifdef USE_4BA_UXGA
+/* For UXGA ( 1600 x 1200) on 4BA module */
+static unsigned char s5k4ba_uxga_reg[][2] = {
+	{0xfc, 0x02},
+	{0x2d, 0x48},
+	{0x44, 0x63},
+
+	{0xfc, 0x03},
+	{0x02, 0x04},
+	{0xfc, 0x20},
+	{0x14, 0x70},
+
+	{0xfc, 0x00},
+	{0x03, 0x4b},	/* AE/AWB On */
+	{0x7e, 0xf4},	/* Suppress On */
+	{0x89, 0x03},	/* Edge Suppress On */
+
+	{0xfc, 0x02},
+	{0x02, 0x0e},	/*sensor BPRoff */
+
+	{0xfc, 0x20},
+	{0x16, 0x60},	/* Frame AE Start */
+
+	{0xfc, 0x02},
+	{0x30, 0x90},	/* Analog offset */
+	{0x37, 0x0d},	/* Global Gain */
+	{0x60, 0x00},	/* Blank_Adrs */
+	{0x45, 0x0e},	/* CDS Timing for Average Sub_Sampling */
+	{0x47, 0x2f},
+
+	{0xfc, 0x01},
+	{0x9F, 0x05},
+	{0xA0, 0x18},
+	{0xA1, 0x42},
+	{0xA2, 0xd7},
+	{0xA3, 0x00},
+
+	{0xA4, 0xB6},
+	{0xA5, 0x3b},
+	{0xA6, 0x88},
+	{0xA7, 0xC8},
+	{0xA8, 0x6A},
+
+	{0xfc, 0x05},
+	{0x34, 0x20},	/* APTCLP */
+	{0x35, 0x08},	/* 9 //APTSC */
+
+	{0xfc, 0x00},	/* flash 0821 */
+	{0x32, 0x04},	/* AWB moving average 8 frame */
+
+	{0xfc, 0x01},
+	{0x01, 0x01},	/* Pclk inversion */
+
+	{0xfc, 0x00},
+	{0x02, 0x00},	/* 1600 x 1200 */
+
+	{0xfc, 0x01},
+	{0x02, 0x06},	// crcb_sel
+
+	{0xFF, 0xFF}	/* REGISTER END */
+};
+#endif
+#define S5K4BA_INIT_REGS	\
+	(sizeof(s5k4ba_init_reg) / sizeof(s5k4ba_init_reg[0]))
+
+#define S5K4BA_SVGA_REGS	\
+	(sizeof(s5k4ba_svga_reg) / sizeof(s5k4ba_svga_reg[0]))
+
+#define S5K4BA_UXGA_REGS	\
+	(sizeof(s5k4ba_uxga_reg) / sizeof(s5k4ba_uxga_reg[0]))
+
+/*
+ * EV bias
+ */
+
+static const struct s5k4ba_reg s5k4ba_ev_m6[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_m5[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_m4[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_m3[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_m2[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_m1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_default[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p2[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p3[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p4[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p5[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_ev_p6[] = {
+};
+
+#ifdef S5K4BA_COMPLETE
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ba_regs_ev_bias[] = {
+	(unsigned char *)s5k4ba_ev_m6, (unsigned char *)s5k4ba_ev_m5,
+	(unsigned char *)s5k4ba_ev_m4, (unsigned char *)s5k4ba_ev_m3,
+	(unsigned char *)s5k4ba_ev_m2, (unsigned char *)s5k4ba_ev_m1,
+	(unsigned char *)s5k4ba_ev_default, (unsigned char *)s5k4ba_ev_p1,
+	(unsigned char *)s5k4ba_ev_p2, (unsigned char *)s5k4ba_ev_p3,
+	(unsigned char *)s5k4ba_ev_p4, (unsigned char *)s5k4ba_ev_p5,
+	(unsigned char *)s5k4ba_ev_p6,
+};
+
+/*
+ * Auto White Balance configure
+ */
+static const struct s5k4ba_reg s5k4ba_awb_off[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_awb_on[] = {
+};
+
+static const unsigned char *s5k4ba_regs_awb_enable[] = {
+	(unsigned char *)s5k4ba_awb_off,
+	(unsigned char *)s5k4ba_awb_on,
+};
+
+/*
+ * Manual White Balance (presets)
+ */
+static const struct s5k4ba_reg s5k4ba_wb_tungsten[] = {
+
+};
+
+static const struct s5k4ba_reg s5k4ba_wb_fluorescent[] = {
+
+};
+
+static const struct s5k4ba_reg s5k4ba_wb_sunny[] = {
+
+};
+
+static const struct s5k4ba_reg s5k4ba_wb_cloudy[] = {
+
+};
+
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ba_regs_wb_preset[] = {
+	(unsigned char *)s5k4ba_wb_tungsten,
+	(unsigned char *)s5k4ba_wb_fluorescent,
+	(unsigned char *)s5k4ba_wb_sunny,
+	(unsigned char *)s5k4ba_wb_cloudy,
+};
+
+/*
+ * Color Effect (COLORFX)
+ */
+static const struct s5k4ba_reg s5k4ba_color_sepia[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_color_aqua[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_color_monochrome[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_color_negative[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_color_sketch[] = {
+};
+
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ba_regs_color_effect[] = {
+	(unsigned char *)s5k4ba_color_sepia,
+	(unsigned char *)s5k4ba_color_aqua,
+	(unsigned char *)s5k4ba_color_monochrome,
+	(unsigned char *)s5k4ba_color_negative,
+	(unsigned char *)s5k4ba_color_sketch,
+};
+
+/*
+ * Contrast bias
+ */
+static const struct s5k4ba_reg s5k4ba_contrast_m2[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_contrast_m1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_contrast_default[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_contrast_p1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_contrast_p2[] = {
+};
+
+static const unsigned char *s5k4ba_regs_contrast_bias[] = {
+	(unsigned char *)s5k4ba_contrast_m2,
+	(unsigned char *)s5k4ba_contrast_m1,
+	(unsigned char *)s5k4ba_contrast_default,
+	(unsigned char *)s5k4ba_contrast_p1,
+	(unsigned char *)s5k4ba_contrast_p2,
+};
+
+/*
+ * Saturation bias
+ */
+static const struct s5k4ba_reg s5k4ba_saturation_m2[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_saturation_m1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_saturation_default[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_saturation_p1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_saturation_p2[] = {
+};
+
+static const unsigned char *s5k4ba_regs_saturation_bias[] = {
+	(unsigned char *)s5k4ba_saturation_m2,
+	(unsigned char *)s5k4ba_saturation_m1,
+	(unsigned char *)s5k4ba_saturation_default,
+	(unsigned char *)s5k4ba_saturation_p1,
+	(unsigned char *)s5k4ba_saturation_p2,
+};
+
+/*
+ * Sharpness bias
+ */
+static const struct s5k4ba_reg s5k4ba_sharpness_m2[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_sharpness_m1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_sharpness_default[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_sharpness_p1[] = {
+};
+
+static const struct s5k4ba_reg s5k4ba_sharpness_p2[] = {
+};
+
+static const unsigned char *s5k4ba_regs_sharpness_bias[] = {
+	(unsigned char *)s5k4ba_sharpness_m2,
+	(unsigned char *)s5k4ba_sharpness_m1,
+	(unsigned char *)s5k4ba_sharpness_default,
+	(unsigned char *)s5k4ba_sharpness_p1,
+	(unsigned char *)s5k4ba_sharpness_p2,
+};
+#endif /* S5K4BA_COMPLETE */
+
+#endif
diff --git a/drivers/media/video/s5k4ba2.c b/drivers/media/video/s5k4ba2.c
new file mode 100644
index 0000000..c8a8b3d
--- /dev/null
+++ b/drivers/media/video/s5k4ba2.c
@@ -0,0 +1,660 @@
+/* linux/drivers/media/video/s5k4ba.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver for S5K4BA (UXGA camera) from Samsung Electronics
+ * 1/4" 2.0Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/s5k4ba_platform.h>
+
+#include <linux/videodev2_exynos_camera.h>
+
+#include "s5k4ba.h"
+
+#define S5K4BA_DRIVER_NAME	"S5K4BA"
+
+/* Default resolution & pixelformat. plz ref s5k4ba_platform.h */
+#define DEFAULT_RES		WVGA	/* Index of resoultion */
+#define DEFAUT_FPS_INDEX	S5K4BA_15FPS
+#define DEFAULT_FMT		V4L2_PIX_FMT_UYVY	/* YUV422 */
+
+/*
+ * Specification
+ * Parallel : ITU-R. 656/601 YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Serial : MIPI CSI2 (single lane) YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Resolution : 1280 (H) x 1024 (V)
+ * Image control : Brightness, Contrast, Saturation, Sharpness, Glamour
+ * Effect : Mono, Negative, Sepia, Aqua, Sketch
+ * FPS : 15fps @full resolution, 30fps @VGA, 24fps @720p
+ * Max. pixel clock frequency : 48MHz(upto)
+ * Internal PLL (6MHz to 27MHz input frequency)
+ */
+
+/* Camera functional setting values configured by user concept */
+struct s5k4ba_userset {
+	signed int exposure_bias;	/* V4L2_CID_EXPOSURE */
+	unsigned int ae_lock;
+	unsigned int awb_lock;
+	unsigned int auto_wb;	/* V4L2_CID_AUTO_WHITE_BALANCE */
+	unsigned int manual_wb;	/* V4L2_CID_WHITE_BALANCE_PRESET */
+	unsigned int wb_temp;	/* V4L2_CID_WHITE_BALANCE_TEMPERATURE */
+	unsigned int effect;	/* Color FX (AKA Color tone) */
+	unsigned int contrast;	/* V4L2_CID_CONTRAST */
+	unsigned int saturation;	/* V4L2_CID_SATURATION */
+	unsigned int sharpness;		/* V4L2_CID_SHARPNESS */
+	unsigned int glamour;
+};
+
+struct s5k4ba_state {
+	struct s5k4ba_mbus_platform_data *pdata;
+	struct v4l2_subdev 		sd;
+	struct v4l2_mbus_framefmt 	fmt;
+	struct v4l2_fract 		timeperframe;
+	struct s5k4ba_userset 		userset;
+	int 				freq;	/* MCLK in KHz */
+	int 				is_mipi;
+	int 				isize;
+	int 				ver;
+	int 				fps;
+	int 				fmt_index;
+	unsigned short 			devid_mask;
+};
+
+static inline struct s5k4ba_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k4ba_state, sd);
+}
+
+/*
+ * S5K4BA register structure : 2bytes address, 2bytes value
+ * retry on write failure up-to 5 times
+ */
+static inline int s5k4ba_write(struct v4l2_subdev *sd, u8 addr, u8 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg[1];
+	unsigned char reg[2];
+	int err = 0;
+	int retry = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+again:
+	msg->addr = client->addr;
+	msg->flags = 0;
+	msg->len = 2;
+	msg->buf = reg;
+
+	reg[0] = addr & 0xff;
+	reg[1] = val & 0xff;
+
+	err = i2c_transfer(client->adapter, msg, 1);
+	if (err >= 0)
+		return err;	/* Returns here on success */
+
+	/* abnormal case: retry 5 times */
+	if (retry < 5) {
+		dev_err(&client->dev, "%s: address: 0x%02x%02x, " \
+			"value: 0x%02x%02x\n", __func__, \
+			reg[0], reg[1], reg[2], reg[3]);
+		retry++;
+		goto again;
+	}
+
+	return err;
+}
+
+static int s5k4ba_i2c_write(struct v4l2_subdev *sd, unsigned char i2c_data[],
+				unsigned char length)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned char buf[length], i;
+	struct i2c_msg msg = {client->addr, 0, length, buf};
+
+	for (i = 0; i < length; i++)
+		buf[i] = i2c_data[i];
+
+	return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+}
+
+static int s5k4ba_write_regs(struct v4l2_subdev *sd, unsigned char regs[],
+				int size)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int i, err;
+
+	for (i = 0; i < size; i++) {
+		err = s5k4ba_i2c_write(sd, &regs[i], sizeof(regs[i]));
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+	return 0;	/* FIXME */
+}
+
+static const char *s5k4ba_querymenu_wb_preset[] = {
+	"WB Tungsten", "WB Fluorescent", "WB sunny", "WB cloudy", NULL
+};
+
+static const char *s5k4ba_querymenu_effect_mode[] = {
+	"Effect Sepia", "Effect Aqua", "Effect Monochrome",
+	"Effect Negative", "Effect Sketch", NULL
+};
+
+static const char *s5k4ba_querymenu_ev_bias_mode[] = {
+	"-3EV",	"-2,1/2EV", "-2EV", "-1,1/2EV",
+	"-1EV", "-1/2EV", "0", "1/2EV",
+	"1EV", "1,1/2EV", "2EV", "2,1/2EV",
+	"3EV", NULL
+};
+
+static struct v4l2_queryctrl s5k4ba_controls[] = {
+	{
+		/*
+		 * For now, we just support in preset type
+		 * to be close to generic WB system,
+		 * we define color temp range for each preset
+		 */
+		.id = V4L2_CID_WHITE_BALANCE_TEMPERATURE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "White balance in kelvin",
+		.minimum = 0,
+		.maximum = 10000,
+		.step = 1,
+		.default_value = 0,	/* FIXME */
+	},
+	{
+		.id = V4L2_CID_WHITE_BALANCE_PRESET,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "White balance preset",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_wb_preset) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_AUTO_WHITE_BALANCE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Auto white balance",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_EXPOSURE,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Exposure bias",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_ev_bias_mode) - 2,
+		.step = 1,
+		.default_value = \
+			(ARRAY_SIZE(s5k4ba_querymenu_ev_bias_mode) - 2) / 2,
+			/* 0 EV */
+	},
+	{
+		.id = V4L2_CID_COLORFX,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Image Effect",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ba_querymenu_effect_mode) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_CONTRAST,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Contrast",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SATURATION,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Saturation",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SHARPNESS,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Sharpness",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+};
+
+const char * const *s5k4ba_ctrl_get_menu(u32 id)
+{
+	switch (id) {
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		return s5k4ba_querymenu_wb_preset;
+
+	case V4L2_CID_COLORFX:
+		return s5k4ba_querymenu_effect_mode;
+
+	case V4L2_CID_EXPOSURE:
+		return s5k4ba_querymenu_ev_bias_mode;
+
+	default:
+		return v4l2_ctrl_get_menu(id);
+	}
+}
+
+static inline struct v4l2_queryctrl const *s5k4ba_find_qctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ba_controls); i++)
+		if (s5k4ba_controls[i].id == id)
+			return &s5k4ba_controls[i];
+
+	return NULL;
+}
+
+static int s5k4ba_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ba_controls); i++) {
+		if (s5k4ba_controls[i].id == qc->id) {
+			memcpy(qc, &s5k4ba_controls[i], \
+				sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int s5k4ba_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	struct v4l2_queryctrl qctrl;
+
+	qctrl.id = qm->id;
+	s5k4ba_queryctrl(sd, &qctrl);
+
+	return v4l2_ctrl_query_menu(qm, &qctrl, s5k4ba_ctrl_get_menu(qm->id));
+}
+
+/*
+ * Clock configuration
+ * Configure expected MCLK from host and return EINVAL if not supported clock
+ * frequency is expected
+ *	freq : in Hz
+ *	flag : not supported for now
+ */
+static int s5k4ba_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
+{
+	int err = -EINVAL;
+
+	return err;
+}
+
+static int s5k4ba_g_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	struct s5k4ba_state *state = to_state(sd);
+	struct s5k4ba_mbus_platform_data *pdata = state->pdata;
+	int err = 0;
+	*fmt = pdata->fmt;
+	return err;
+}
+
+static int s5k4ba_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ba_state *state = to_state(sd);
+	struct s5k4ba_mbus_platform_data *pdata = state->pdata;
+	int err = 0;
+
+	dev_dbg(&client->dev, "requested res(%d, %d)\n",
+		fmt->width, fmt->height);
+
+	*fmt = pdata->fmt;
+	printk("%s\n", __func__);
+	return err;
+}
+
+static int s5k4ba_enum_framesizes(struct v4l2_subdev *sd, struct v4l2_frmsizeenum *fsize)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ba_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ba_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = 0;
+
+	dev_dbg(&client->dev, "%s\n", __func__);
+
+	return err;
+}
+
+static int s5k4ba_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = 0;
+
+	dev_dbg(&client->dev, "%s: numerator %d, denominator: %d\n", \
+		__func__, param->parm.capture.timeperframe.numerator, \
+		param->parm.capture.timeperframe.denominator);
+
+	return err;
+}
+
+static int s5k4ba_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ba_state *state = to_state(sd);
+	struct s5k4ba_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		ctrl->value = userset.exposure_bias;
+		err = 0;
+		break;
+
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		ctrl->value = userset.auto_wb;
+		err = 0;
+		break;
+
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		ctrl->value = userset.manual_wb;
+		err = 0;
+		break;
+
+	case V4L2_CID_COLORFX:
+		ctrl->value = userset.effect;
+		err = 0;
+		break;
+
+	case V4L2_CID_CONTRAST:
+		ctrl->value = userset.contrast;
+		err = 0;
+		break;
+
+	case V4L2_CID_SATURATION:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+
+	case V4L2_CID_SHARPNESS:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+
+	default:
+		dev_err(&client->dev, "%s: no such ctrl\n", __func__);
+		break;
+	}
+
+	return err;
+}
+
+static int s5k4ba_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+#ifdef S5K4BA_COMPLETE
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_EXPOSURE\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_ev_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_ev_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_AUTO_WHITE_BALANCE\n", \
+			__func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_awb_enable[ctrl->value], \
+			sizeof(s5k4ba_regs_awb_enable[ctrl->value]));
+		break;
+
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		dev_dbg(&client->dev, "%s: V4L2_CID_WHITE_BALANCE_PRESET\n", \
+			__func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_wb_preset[ctrl->value], \
+			sizeof(s5k4ba_regs_wb_preset[ctrl->value]));
+		break;
+
+	case V4L2_CID_COLORFX:
+		dev_dbg(&client->dev, "%s: V4L2_CID_COLORFX\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_color_effect[ctrl->value], \
+			sizeof(s5k4ba_regs_color_effect[ctrl->value]));
+		break;
+
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&client->dev, "%s: V4L2_CID_CONTRAST\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_contrast_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_contrast_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_SATURATION:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SATURATION\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_saturation_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_saturation_bias[ctrl->value]));
+		break;
+
+	case V4L2_CID_SHARPNESS:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SHARPNESS\n", __func__);
+		err = s5k4ba_write_regs(sd, \
+		(unsigned char *) s5k4ba_regs_sharpness_bias[ctrl->value], \
+			sizeof(s5k4ba_regs_sharpness_bias[ctrl->value]));
+		break;
+
+	default:
+		dev_err(&client->dev, "%s: no such control\n", __func__);
+		goto out;
+	}
+
+	if (err < 0)
+		goto out;
+	else
+		return 0;
+
+out:
+	dev_dbg(&client->dev, "%s: vidioc_s_ctrl failed\n", __func__);
+	return err;
+#else
+	return 0;
+#endif
+}
+
+static int s5k4ba_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: camera initialization start\n", __func__);
+
+	for (i = 0; i < S5K4BA_INIT_REGS; i++) {
+		err = s5k4ba_i2c_write(sd, s5k4ba_init_reg[i], \
+					sizeof(s5k4ba_init_reg[i]));
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	if (err < 0) {
+		v4l_err(client, "%s: camera initialization failed\n", \
+			__func__);
+		return -EIO;	/* FIXME */
+	}
+
+	return 0;
+}
+
+static int s5k4ba_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	/* No need */
+	return 0;
+}
+
+static int s5k4ba_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ba_state *state = to_state(sd);
+	struct s5k4ba_mbus_platform_data *pdata = state->pdata;
+	int ret;
+
+	/* bug report */
+	BUG_ON(!pdata);
+
+	if(pdata->set_clock) {
+		ret = pdata->set_clock(&client->dev, on);
+		if(ret)
+			return -EIO;
+	}
+	/* setting power */
+	if(pdata->set_power) {
+		ret = pdata->set_power(on);
+		if(ret)
+			return -EIO;
+		if(on)
+			return s5k4ba_init(sd, 0);
+	}
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops s5k4ba_core_ops = {
+	.init = s5k4ba_init,	/* initializing API */
+	.s_power = s5k4ba_s_power,
+	.queryctrl = s5k4ba_queryctrl,
+	.querymenu = s5k4ba_querymenu,
+	.g_ctrl = s5k4ba_g_ctrl,
+	.s_ctrl = s5k4ba_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k4ba_video_ops = {
+	.s_crystal_freq = s5k4ba_s_crystal_freq,
+	.g_mbus_fmt = s5k4ba_g_fmt,
+	.s_mbus_fmt = s5k4ba_s_fmt,
+	.enum_framesizes = s5k4ba_enum_framesizes,
+	.enum_frameintervals = s5k4ba_enum_frameintervals,
+	.g_parm = s5k4ba_g_parm,
+	.s_parm = s5k4ba_s_parm,
+	.s_stream = s5k4ba_s_stream,
+};
+
+static const struct v4l2_subdev_ops s5k4ba_ops = {
+	.core = &s5k4ba_core_ops,
+	.video = &s5k4ba_video_ops,
+};
+
+/*
+ * s5k4ba_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k4ba_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct s5k4ba_state *state;
+	struct v4l2_subdev *sd;
+	struct s5k4ba_mbus_platform_data *pdata = client->dev.platform_data;
+
+	if (!pdata) {
+		dev_err( &client->dev, "null platform data");
+		return -EIO;
+	}
+
+	state = kzalloc(sizeof(struct s5k4ba_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K4BA_DRIVER_NAME);
+	state->pdata = client->dev.platform_data;
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k4ba_ops);
+	state->fmt_index = -1;
+
+	/* needed for acquiring subdevice by this module name */
+	snprintf(sd->name, sizeof(sd->name), S5K4BA_DRIVER_NAME);
+
+	dev_info(&client->dev, "id: %d, fmt.code: %d, res: res: %d x %d",
+	    pdata->id, pdata->fmt.code,
+	    pdata->fmt.width, pdata->fmt.height);
+	dev_info(&client->dev, "s5k4ba has been probed\n");
+	return 0;
+}
+
+static int s5k4ba_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+	return 0;
+}
+
+static const struct i2c_device_id s5k4ba_id[] = {
+	{ S5K4BA_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k4ba_id);
+
+static struct i2c_driver s5k4ba_i2c_driver = {
+	.driver = {
+		.name	= S5K4BA_DRIVER_NAME,
+	},
+	.probe		= s5k4ba_probe,
+	.remove		= s5k4ba_remove,
+	.id_table	= s5k4ba_id,
+};
+
+static int __init s5k4ba_mod_init(void)
+{
+	return i2c_add_driver(&s5k4ba_i2c_driver);
+}
+
+static void __exit s5k4ba_mod_exit(void)
+{
+	i2c_del_driver(&s5k4ba_i2c_driver);
+}
+module_init(s5k4ba_mod_init);
+module_exit(s5k4ba_mod_exit);
+
+MODULE_DESCRIPTION("Samsung Electronics S5K4BA UXGA camera driver");
+MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k4ea.c b/drivers/media/video/s5k4ea.c
new file mode 100644
index 0000000..024b069
--- /dev/null
+++ b/drivers/media/video/s5k4ea.c
@@ -0,0 +1,713 @@
+/* linux/drivers/media/video/s5k4ea.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver for S5K4EA (SXGA camera) from Samsung Electronics
+ * 1/6" 1.3Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ * supporting MIPI CSI-2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/s5k4ea_platform.h>
+
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+
+#include "s5k4ea.h"
+
+#define S5K4EA_DRIVER_NAME	"S5K4EA"
+
+/* Default resolution & pixelformat. plz ref s5k4ea_platform.h */
+#define DEFAULT_RES		WVGA	/* Index of resoultion */
+#define DEFAUT_FPS_INDEX	S5K4EA_15FPS
+#define DEFAULT_FMT		V4L2_PIX_FMT_UYVY	/* YUV422 */
+
+/*
+ * Specification
+ * Parallel : ITU-R. 656/601 YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Serial : MIPI CSI2 (single lane) YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Resolution : 1280 (H) x 1024 (V)
+ * Image control : Brightness, Contrast, Saturation, Sharpness, Glamour
+ * Effect : Mono, Negative, Sepia, Aqua, Sketch
+ * FPS : 15fps @full resolution, 30fps @VGA, 24fps @720p
+ * Max. pixel clock frequency : 48MHz(upto)
+ * Internal PLL (6MHz to 27MHz input frequency)
+ */
+
+/* Camera functional setting values configured by user concept */
+struct s5k4ea_userset {
+	signed int exposure_bias;	/* V4L2_CID_EXPOSURE */
+	unsigned int ae_lock;
+	unsigned int awb_lock;
+	unsigned int auto_wb;	/* V4L2_CID_AUTO_WHITE_BALANCE */
+	unsigned int manual_wb;	/* V4L2_CID_WHITE_BALANCE_PRESET */
+	unsigned int wb_temp;	/* V4L2_CID_WHITE_BALANCE_TEMPERATURE */
+	unsigned int effect;	/* Color FX (AKA Color tone) */
+	unsigned int contrast;	/* V4L2_CID_CONTRAST */
+	unsigned int saturation;	/* V4L2_CID_SATURATION */
+	unsigned int sharpness;		/* V4L2_CID_SHARPNESS */
+	unsigned int glamour;
+};
+
+struct s5k4ea_state {
+	struct s5k4ea_platform_data *pdata;
+	struct v4l2_subdev sd;
+	struct v4l2_pix_format pix;
+	struct v4l2_fract timeperframe;
+	struct s5k4ea_userset userset;
+	int freq;	/* MCLK in KHz */
+	int is_mipi;
+	int isize;
+	int ver;
+	int fps;
+};
+
+static inline struct s5k4ea_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k4ea_state, sd);
+}
+
+/*
+ * S5K4EA register structure : 2bytes address, 2bytes value
+ * retry on write failure up-to 5 times
+ */
+static inline int s5k4ea_write(struct v4l2_subdev *sd, u16 addr, u16 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg[1];
+	unsigned char reg[4];
+	int err = 0;
+	int retry = 0;
+
+
+	if (!client->adapter)
+		return -ENODEV;
+
+again:
+	msg->addr = client->addr;
+	msg->flags = 0;
+	msg->len = 4;
+	msg->buf = reg;
+
+	reg[0] = addr >> 8;
+	reg[1] = addr & 0xff;
+	reg[2] = val >> 8;
+	reg[3] = val & 0xff;
+
+	err = i2c_transfer(client->adapter, msg, 1);
+	if (err >= 0)
+		return err;	/* Returns here on success */
+
+	/* abnormal case: retry 5 times */
+	if (retry < 5) {
+		dev_err(&client->dev, "%s: address: 0x%02x%02x, " \
+			"value: 0x%02x%02x\n", __func__, \
+			reg[0], reg[1], reg[2], reg[3]);
+		retry++;
+		goto again;
+	}
+
+	return err;
+}
+
+static int s5k4ea_i2c_write(struct v4l2_subdev *sd, unsigned char i2c_data[],
+				unsigned char length)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned char buf[length], i;
+	struct i2c_msg msg = {client->addr, 0, length, buf};
+
+	for (i = 0; i < length; i++)
+		buf[i] = i2c_data[i];
+
+	return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+}
+
+static const char *s5k4ea_querymenu_wb_preset[] = {
+	"WB Tungsten", "WB Fluorescent", "WB sunny", "WB cloudy", NULL
+};
+
+static const char *s5k4ea_querymenu_effect_mode[] = {
+	"Effect Sepia", "Effect Aqua", "Effect Monochrome",
+	"Effect Negative", "Effect Sketch", NULL
+};
+
+static const char *s5k4ea_querymenu_ev_bias_mode[] = {
+	"-3EV",	"-2,1/2EV", "-2EV", "-1,1/2EV",
+	"-1EV", "-1/2EV", "0", "1/2EV",
+	"1EV", "1,1/2EV", "2EV", "2,1/2EV",
+	"3EV", NULL
+};
+
+static struct v4l2_queryctrl s5k4ea_controls[] = {
+	{
+		/*
+		 * For now, we just support in preset type
+		 * to be close to generic WB system,
+		 * we define color temp range for each preset
+		 */
+		.id = V4L2_CID_WHITE_BALANCE_TEMPERATURE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "White balance in kelvin",
+		.minimum = 0,
+		.maximum = 10000,
+		.step = 1,
+		.default_value = 0,	/* FIXME */
+	},
+	{
+		.id = V4L2_CID_WHITE_BALANCE_PRESET,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "White balance preset",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_wb_preset) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_AUTO_WHITE_BALANCE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Auto white balance",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_EXPOSURE,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Exposure bias",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_ev_bias_mode) - 2,
+		.step = 1,
+		.default_value = (ARRAY_SIZE(s5k4ea_querymenu_ev_bias_mode) \
+				- 2) / 2,	/* 0 EV */
+	},
+	{
+		.id = V4L2_CID_COLORFX,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Image Effect",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_effect_mode) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_CONTRAST,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Contrast",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SATURATION,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Saturation",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SHARPNESS,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Sharpness",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+};
+
+const char * const *s5k4ea_ctrl_get_menu(u32 id)
+{
+	switch (id) {
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		return s5k4ea_querymenu_wb_preset;
+
+	case V4L2_CID_COLORFX:
+		return s5k4ea_querymenu_effect_mode;
+
+	case V4L2_CID_EXPOSURE:
+		return s5k4ea_querymenu_ev_bias_mode;
+
+	default:
+		return v4l2_ctrl_get_menu(id);
+	}
+}
+
+static inline struct v4l2_queryctrl const *s5k4ea_find_qctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ea_controls); i++)
+		if (s5k4ea_controls[i].id == id)
+			return &s5k4ea_controls[i];
+
+	return NULL;
+}
+
+static int s5k4ea_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ea_controls); i++) {
+		if (s5k4ea_controls[i].id == qc->id) {
+			memcpy(qc, &s5k4ea_controls[i], \
+				sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int s5k4ea_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	struct v4l2_queryctrl qctrl;
+
+	qctrl.id = qm->id;
+	s5k4ea_queryctrl(sd, &qctrl);
+
+	return v4l2_ctrl_query_menu(qm, &qctrl, s5k4ea_ctrl_get_menu(qm->id));
+}
+
+/*
+ * Clock configuration
+ * Configure expected MCLK from host and return EINVAL if not supported clock
+ * frequency is expected
+ *	freq : in Hz
+ *	flag : not supported for now
+ */
+static int s5k4ea_s_crystal_freq(struct v4l2_subdev *sd, u32  freq, u32 flags)
+{
+	int err = -EINVAL;
+
+	return err;
+}
+
+static int s5k4ea_g_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	int err = 0;
+
+	return err;
+}
+static int s5k4ea_enum_framesizes(struct v4l2_subdev *sd,
+					struct v4l2_frmsizeenum *fsize)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	struct s5k4ea_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		ctrl->value = userset.exposure_bias;
+		err = 0;
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		ctrl->value = userset.auto_wb;
+		err = 0;
+		break;
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		ctrl->value = userset.manual_wb;
+		err = 0;
+		break;
+	case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
+		ctrl->value = userset.wb_temp;
+		err = 0;
+		break;
+	case V4L2_CID_COLORFX:
+		ctrl->value = userset.effect;
+		err = 0;
+		break;
+	case V4L2_CID_CONTRAST:
+		ctrl->value = userset.contrast;
+		err = 0;
+		break;
+	case V4L2_CID_SATURATION:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+	case V4L2_CID_SHARPNESS:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+	default:
+		dev_err(&client->dev, "%s: no such ctrl\n", __func__);
+		break;
+	}
+
+	return err;
+}
+
+static int s5k4ea_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+#ifdef S5K4EA_COMPLETE
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	struct s5k4ea_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_EXPOSURE\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, s5k4ea_regs_ev_bias[ctrl->value]);
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_AUTO_WHITE_BALANCE\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_awb_enable[ctrl->value]);
+		break;
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		dev_dbg(&client->dev, "%s: V4L2_CID_WHITE_BALANCE_PRESET\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_wb_preset[ctrl->value]);
+		break;
+	case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
+		dev_dbg(&client->dev, \
+			"%s: V4L2_CID_WHITE_BALANCE_TEMPERATURE\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_wb_temperature[ctrl->value]);
+		break;
+	case V4L2_CID_COLORFX:
+		dev_dbg(&client->dev, "%s: V4L2_CID_COLORFX\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_color_effect[ctrl->value]);
+		break;
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&client->dev, "%s: V4L2_CID_CONTRAST\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_contrast_bias[ctrl->value]);
+		break;
+	case V4L2_CID_SATURATION:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SATURATION\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_saturation_bias[ctrl->value]);
+		break;
+	case V4L2_CID_SHARPNESS:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SHARPNESS\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_sharpness_bias[ctrl->value]);
+		break;
+	default:
+		dev_err(&client->dev, "%s: no such control\n", __func__);
+		break;
+	}
+
+	if (err < 0)
+		goto out;
+	else
+		return 0;
+
+out:
+	dev_dbg(&client->dev, "%s: vidioc_s_ctrl failed\n", __func__);
+	return err;
+#else
+	return 0;
+#endif
+}
+
+int
+__s5k4ea_init_4bytes(struct v4l2_subdev *sd, unsigned char *reg[], int total)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+	unsigned char *item;
+
+	for (i = 0; i < total; i++) {
+		item = (unsigned char *) &reg[i];
+		if (item[0] == REG_DELAY) {
+			mdelay(item[1]);
+			err = 0;
+		} else {
+			err = s5k4ea_i2c_write(sd, item, 4);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	return err;
+}
+
+static int
+__s5k4ea_init_2bytes(struct v4l2_subdev *sd, unsigned short *reg[], int total)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+	unsigned short *item;
+
+	for (i = 0; i < total; i++) {
+		item = (unsigned short *) &reg[i];
+		if (item[0] == REG_DELAY) {
+			mdelay(item[1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, item[0], item[1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	return err;
+}
+
+static int s5k4ea_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+
+	v4l_info(client, "%s: camera initialization start\n", __func__);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg1, S5K4EA_INIT_REGS1);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg2, S5K4EA_INIT_REGS2);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg3, S5K4EA_INIT_REGS3);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg4, S5K4EA_INIT_REGS4);
+
+	if (val == 1)
+		err = __s5k4ea_init_4bytes(sd, \
+			(unsigned char **) s5k4ea_init_jpeg, S5K4EA_INIT_JPEG);
+	else
+		err = __s5k4ea_init_4bytes(sd, \
+			(unsigned char **) s5k4ea_init_reg5, S5K4EA_INIT_REGS5);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg6, S5K4EA_INIT_REGS6);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg7, S5K4EA_INIT_REGS7);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg8, S5K4EA_INIT_REGS8);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg9, S5K4EA_INIT_REGS9);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg10, S5K4EA_INIT_REGS10);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg11, S5K4EA_INIT_REGS11);
+
+	if (err < 0) {
+		v4l_err(client, "%s: camera initialization failed\n", \
+			__func__);
+		return -EIO;	/* FIXME */
+	}
+
+	return 0;
+}
+
+static int s5k4ea_sleep(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: sleep mode\n", __func__);
+
+	for (i = 0; i < S5K4EA_SLEEP_REGS; i++) {
+		if (s5k4ea_sleep_reg[i][0] == REG_DELAY) {
+			mdelay(s5k4ea_sleep_reg[i][1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, s5k4ea_sleep_reg[i][0], \
+				s5k4ea_sleep_reg[i][1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", __func__);
+	}
+
+	if (err < 0) {
+		v4l_err(client, "%s: sleep failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k4ea_wakeup(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: wakeup mode\n", __func__);
+
+	for (i = 0; i < S5K4EA_WAKEUP_REGS; i++) {
+		if (s5k4ea_wakeup_reg[i][0] == REG_DELAY) {
+			mdelay(s5k4ea_wakeup_reg[i][1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, s5k4ea_wakeup_reg[i][0], \
+				s5k4ea_wakeup_reg[i][1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", __func__);
+	}
+
+	if (err < 0) {
+		v4l_err(client, "%s: wake up failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k4ea_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	return enable ? s5k4ea_wakeup(sd) : s5k4ea_sleep(sd);
+}
+
+static const struct v4l2_subdev_core_ops s5k4ea_core_ops = {
+	.init = s5k4ea_init,	/* initializing API */
+	.queryctrl = s5k4ea_queryctrl,
+	.querymenu = s5k4ea_querymenu,
+	.g_ctrl = s5k4ea_g_ctrl,
+	.s_ctrl = s5k4ea_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k4ea_video_ops = {
+	.s_crystal_freq = s5k4ea_s_crystal_freq,
+	.g_mbus_fmt = s5k4ea_g_fmt,
+	.s_mbus_fmt = s5k4ea_s_fmt,
+	.enum_framesizes = s5k4ea_enum_framesizes,
+	.enum_frameintervals = s5k4ea_enum_frameintervals,
+	.g_parm = s5k4ea_g_parm,
+	.s_parm = s5k4ea_s_parm,
+	.s_stream = s5k4ea_s_stream,
+};
+
+static const struct v4l2_subdev_ops s5k4ea_ops = {
+	.core = &s5k4ea_core_ops,
+	.video = &s5k4ea_video_ops,
+};
+
+/*
+ * s5k4ea_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k4ea_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct s5k4ea_state *state;
+	struct v4l2_subdev *sd;
+
+	state = kzalloc(sizeof(struct s5k4ea_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K4EA_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k4ea_ops);
+
+	dev_info(&client->dev, "s5k4ea has been probed\n");
+	return 0;
+}
+
+
+static int s5k4ea_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+	return 0;
+}
+
+static const struct i2c_device_id s5k4ea_id[] = {
+	{ S5K4EA_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k4ea_id);
+
+static struct i2c_driver s5k4ea_i2c_driver = {
+	.driver = {
+		.name	= S5K4EA_DRIVER_NAME,
+	},
+	.probe		= s5k4ea_probe,
+	.remove		= s5k4ea_remove,
+	.id_table	= s5k4ea_id,
+};
+
+static int __init s5k4ea_mod_init(void)
+{
+	return i2c_add_driver(&s5k4ea_i2c_driver);
+}
+
+static void __exit s5k4ea_mod_exit(void)
+{
+	i2c_del_driver(&s5k4ea_i2c_driver);
+}
+module_init(s5k4ea_mod_init);
+module_exit(s5k4ea_mod_exit);
+
+MODULE_DESCRIPTION("Samsung Electronics S5K4EA SXGA camera driver");
+MODULE_AUTHOR("Dongsoo Nathaniel Kim<dongsoo45.kim@samsung.com>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/video/s5k4ea.h b/drivers/media/video/s5k4ea.h
new file mode 100644
index 0000000..616d4a0
--- /dev/null
+++ b/drivers/media/video/s5k4ea.h
@@ -0,0 +1,1108 @@
+/* linux/drivers/media/video/s5k4ea.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Driver for S5K4EA (SXGA camera) from Samsung Electronics
+ * 1/6" 1.3Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ * supporting MIPI CSI-2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define S5K4EA_COMPLETE
+#undef S5K4EA_COMPLETE
+#ifndef __S5K4EA_H__
+#define __S5K4EA_H__
+
+struct s5k4ea_reg {
+	unsigned short addr;
+	unsigned short val;
+};
+
+struct s5k4ea_regset_type {
+	unsigned char *regset;
+	int len;
+};
+
+/*
+ * Macro
+ */
+#define REGSET_LENGTH(x)	(sizeof(x)/sizeof(s5k4ea_reg))
+
+/*
+ * Host S/W Register interface (0x70000000-0x70002000)
+ */
+/* Initialization section */
+#define S5K4EA_Speed_368Mbps		0
+#define S5K4EA_Speed_464Mbps		1
+#define S5K4EA_Speed_552Mbps		2
+#define S5K4EA_Speed_648Mbps		3
+#define S5K4EA_Speed_736Mbps		4
+#define S5K4EA_Speed_832Mbps		5
+#define S5K4EA_Speed_920Mbps		6
+
+#define S5K4EA4Khz_0Mhz		0x0000
+#define S5K4EA4Khz_46Mhz		0x2CEC
+#define S5K4EA4Khz_58Mhz		0x38A4
+#define S5K4EA4Khz_69Mhz		0x4362
+#define S5K4EA4Khz_81Mhz		0x4F1A
+#define S5K4EA4Khz_91Mhz		0x58DE
+#define S5K4EA4Khz_92Mhz		0x59D8
+#define S5K4EA4Khz_93Mhz		0x5AD2
+#define S5K4EA4Khz_104Mhz		0x6590
+#define S5K4EA4Khz_115Mhz		0x704E
+
+#define S5K4EAFrTime_30fps		0x014D	/*  33.3ms -> 30 fps */
+#define S5K4EAFrTime_15fps		0x029A	/*  66.6ms -> 15 fps */
+#define S5K4EAFrTime_7P5fps		0x0535	/*  133.3ms -> 7.5 fps */
+#define S5K4EAFrTime_1P5fps		0x1964	/*  650.0ms -> 1.5 fps */
+/*=====================================*/
+/*========Register map for S5K4EA EVT1(Don't modify)===========*/
+#define S5K4EA_REG_TC_IPRM_InClockLSBs				0x0238
+#define S5K4EA_REG_TC_IPRM_InClockMSBs				0x023A
+#define S5K4EA_REG_TC_IPRM_UseNPviClocks			0x0252
+#define S5K4EA_REG_TC_IPRM_UseNMipiClocks			0x0254
+#define S5K4EA_REG_TC_IPRM_NumberOfMipiLanes			0x0256
+#define S5K4EA_REG_TC_IPRM_OpClk4KHz_0				0x025A
+#define S5K4EA_REG_TC_IPRM_MinOutRate4KHz_0			0x025C
+#define S5K4EA_REG_TC_IPRM_MaxOutRate4KHz_0			0x025E
+#define S5K4EA_REG_TC_IPRM_InitParamsUpdated			0x026E
+#define S5K4EA_REG_TC_GP_EnablePreview				0x0280
+#define S5K4EA_REG_TC_GP_EnablePreviewChanged			0x0282
+#define S5K4EA_REG_TC_GP_NewConfigSync				0x0290
+#define S5K4EA_REG_TC_GP_ActivePrevConfig			0x02A4
+#define S5K4EA_REG_TC_GP_PrevConfigChanged			0x02A6
+#define S5K4EA_REG_TC_GP_PrevOpenAfterChange			0x02A8
+#define S5K4EA_REG_0TC_PCFG_usWidth				0x02E2
+#define S5K4EA_REG_0TC_PCFG_usHeight				0x02E4
+#define S5K4EA_REG_0TC_PCFG_Format				0x02E6
+#define S5K4EA_REG_0TC_PCFG_usMaxOut4KHzRate			0x02E8
+#define S5K4EA_REG_0TC_PCFG_usMinOut4KHzRate			0x02EA
+#define S5K4EA_REG_0TC_PCFG_PVIMask				0x02F0
+#define S5K4EA_REG_0TC_PCFG_uClockInd				0x02F8
+#define S5K4EA_REG_0TC_PCFG_FrRateQualityType			0x02FC
+#define S5K4EA_REG_0TC_PCFG_usFrTimeType			0x02FA
+#define S5K4EA_REG_0TC_PCFG_usMaxFrTimeMsecMult10		0x02FE
+#define S5K4EA_REG_0TC_PCFG_usMinFrTimeMsecMult10		0x0300
+
+#define S5K4EA_PCLK_MIN	S5K4EA4Khz_115Mhz
+#define S5K4EA_PCLK_MAX	S5K4EA4Khz_115Mhz
+
+#define S5K4EA_FrTime_MAX	S5K4EAFrTime_30fps
+/*
+ * User defined commands
+ */
+/* S/W defined features for tune */
+#define REG_DELAY	0xFF	/* in ms */
+#define REG_CMD		0xFFFF	/* Followed by command */
+
+/* Following order should not be changed */
+enum image_size_s5k4ea {
+	/* This SoC supports upto SXGA (1280*1024) */
+#if 0
+	QQVGA, /* 160*120*/
+	QCIF, /* 176*144 */
+	QVGA, /* 320*240 */
+	CIF, /* 352*288 */
+#endif
+	VGA, /* 640*480 */
+#if 0
+	SVGA, /* 800*600 */
+	HD720P, /* 1280*720 */
+	SXGA, /* 1280*1024 */
+#endif
+};
+
+/*
+ * Following values describe controls of camera
+ * in user aspect and must be match with index of s5k4ea_regset[]
+ * These values indicates each controls and should be used
+ * to control each control
+ */
+enum s5k4ea_control {
+	S5K4EA_INIT,
+	S5K4EA_EV,
+	S5K4EA_AWB,
+	S5K4EA_MWB,
+	S5K4EA_EFFECT,
+	S5K4EA_CONTRAST,
+	S5K4EA_SATURATION,
+	S5K4EA_SHARPNESS,
+};
+
+#define S5K4EA_REGSET(x)	{	\
+	.regset = x,			\
+	.len = sizeof(x)/sizeof(s5k4ea_reg),}
+
+/*
+ * User tuned register setting values
+ */
+unsigned char s5k4ea_init_reg1[][4] = {
+	{0xFC, 0xFC, 0xD0, 0x00},
+
+	/* === Analog/APS setting === */
+	/* WRITE	D000F262	0000
+	 * tgr_auto_exp (shutter off=0b shutter on=1b) */
+	{0x00, 0x28, 0xD0, 0x00},
+
+	/* 002A	F468 */
+	/* 0F12	0006	 For avg mode */
+	{0x00, 0x2A, 0xF4, 0x04},
+	{0x0F, 0x12, 0x00, 0x2A},/* ADC SAT(450mV):  by Ana 090609 */
+	{0x00, 0x2A, 0xF4, 0x6E},
+	{0x0F, 0x12, 0x00, 0x02},/* CDS TEST [0]SR/SS EN: by Ana 090126 */
+	/*  [1]S1 H, [2]LDB H, [3]clp H */
+	/*  [4]S34 P X, [5]S24 N X */
+	{0x00, 0x2A, 0xF4, 0x5A},
+	{0x0F, 0x12, 0x00, 0x02},/*  LD LDB EN :  by Ana 090126 */
+	{0x00, 0x2A, 0xF4, 0x0E},
+	{0x0F, 0x12, 0x00, 0x04},/*  RMP REG 1.8V:  by Ana 090126 */
+	{0x00, 0x2A, 0xF4, 0x0C},
+	{0x0F, 0x12, 0x00, 0x20}, /*  rmp_option(RMP_INIT_DAC):
+					*  by Ana 090126 */
+	{0x00, 0x2A, 0xF4, 0x20},
+	{0x0F, 0x12, 0x00, 0x76}, /* For SHBN 76 0075
+		* COMP(CDS) bias [7:4] comp2, [3:0] comp1: by Ana 090126 */
+
+	{0x0F, 0x12, 0x00, 0x05}, /*  pix current bias */
+
+	{0x00, 0x2A, 0xF4, 0x26},
+	{0x0F, 0x12, 0x00, 0xD4}, /*  CLP level */
+	{0x00, 0x2A, 0xF4, 0x60},
+	{0x0F, 0x12, 0x00, 0x01}, /*  CLP on:  by Ana 090126 */
+
+	{0x00, 0x2A, 0xE3, 0x04},
+	{0x0F, 0x12, 0x00, 0x81}, /*  ADC OFFSET 128:  by Ana 090126 */
+	{0x00, 0x2A, 0xE3, 0x08},
+	{0x0F, 0x12, 0x00, 0x81}, /*  ADC DEFAULT 128:  by Ana 090209 */
+
+	/*  ADLC */
+	{0x00, 0x2A, 0xE5, 0x06},
+	{0x0F, 0x12, 0x00, 0x93}, /*  ADLC [7]FL,[6:5]FM,: by Ana 090126 */
+	/*  [4]F,[3:2]LM,[1]L,[0]CH */
+	{0x00, 0x2A, 0xE4, 0x02},
+	{0x0F, 0x12, 0x04, 0x0C}, /*  ADLC BPR EN[10], th 12: by Ana 090126 */
+	/* WRITE D000E510 3804  adlc_frame_filter_co_reg[B][A] */
+
+	{0x00, 0x2A, 0xF4, 0x2A},
+	{0x0F, 0x12, 0x00, 0x80}, /*  ALL TX mode enable(ref_option[7]):
+			*  by Ana 090130 */
+
+	{0x00, 0x2A, 0xF4, 0x08},
+	{0x0F, 0x12, 0x00, 0x0E}, /* aig_sig_mx:  by Ana 090209 */
+	{0x0F, 0x12, 0x00, 0x07}, /* aig_rst_mx:  by Ana 090209 */
+	{0x00, 0x2A, 0xF4, 0x00},
+	{0x0F, 0x12, 0x00, 0x07}, /* 0007 aig_off_rst1: for 92MHZ HS (full) */
+				/* 0006	aig_off_rst1:
+				 * for 92MHz LS(full & avg)/ 46MHz LS(full) */
+				/*  0005 aig_off_rst1: for 46MHz LS(avg) */
+				/*  0004 aig_off_rst1: for 46MHz HS (full) */
+
+	/*  Doubler	 */
+	{0x00, 0x2A, 0xF4, 0x3C},
+	{0x0F, 0x12, 0x00, 0x01}, /*  aig_pd_inrush_ctrl: by Ana 090126 */
+	{0x00, 0x2A, 0xF4, 0x40},
+	{0x0F, 0x12, 0x00, 0x44}, /* aig_rosc_tune_ncp[7:4],
+				* aig_rosc_tune_cp[3:0]: by Ana 090126 */
+	{0x00, 0x2A, 0xF4, 0x44},
+	{0x0F, 0x12, 0x00, 0x08}, /*  aig_reg_tune_pix */
+	{0x00, 0x2A, 0xF4, 0x48},
+	{0x0F, 0x12, 0x00, 0x08}, /*  aig_reg_tune_ntg */
+
+	{0x00, 0x2A, 0xF4, 0x5C},
+	{0x0F, 0x12, 0x00, 0x01}, /*  aig_dshut_en */
+
+	/* Multiple Sampling */
+	{0x00, 0x2A, 0xF4, 0x06},
+	{0x0F, 0x12, 0x00, 0x01}, /*  MS[2:0], No Multiple Sampling @92MHz,
+				* :  by Ana 090130 */
+	/*  1b' 2 times multiple sampling(0001h) for 46MHz or LS@92MHz */
+	{0x00, 0x2A, 0xF4, 0x10},
+	{0x0F, 0x12, 0x00, 0x00}, /*  MSOFF_EN=0 : no Multiple sampling
+				* if gain < 2 :  by Ana 090609 */
+	/* === APS Timing === */
+	{0x00, 0x28, 0xD0, 0x00},
+	{0x00, 0x2A, 0xF4, 0x72},
+	{0x0F, 0x12, 0x00, 0x5C}, /* For 92MHz LS & HS aig_dstx_width(1us@92MHz)
+				* :  by Ana 090216  */
+				/* 002E	aig_dstx_width(1us@46MHz)
+				 * :  by Ana 090216 */
+
+	/* For 46MHz 7.5fps */
+	/* 002A	F476 */
+	/* 0F12	0045	aig_stx_width(1.5us@46MHz):  by Ana 090216 */
+
+	{0x00, 0x28, 0xD0, 0x00},
+	{0x00, 0x2A, 0xF4, 0x70},
+	{0x0F, 0x12, 0x00, 0x04},
+
+	/* == CDS Timing == */
+	/*  Rom retreive address was changed from 0x70003880 to 0x7000 3C00. */
+	/* 2009.03.16 */
+
+	{0x00, 0x28, 0x70, 0x00},
+	/* value       register		decription.   */
+	/* 700017CC    senHal_ContPtrs_senModesDataArr[0]
+		* nomal speed, normal */
+
+	/* 700017D0    senHal_ContPtrs_senModesDataArr[1]
+		* nomal speed, avg mode */
+	/* 700017D4    senHal_ContPtrs_senModesDataArr[2]
+		* nomal speed, weighted mode */
+	/* 700017D8    senHal_ContPtrs_senHighSpeedModesDataArr[0]
+		* high speed, normal        */
+	/* 700017DC    senHal_ContPtrs_senHighSpeedModesDataArr[1]
+		 * high speed, avg mode    */
+	/* 700017E0    senHal_ContPtrs_senHighSpeedModesDataArr[2]
+		* high speed, weighted mode   */
+
+	/* HS_Normal         */
+	{0x00, 0x2A, 0x17, 0xD8}, /*  High speed Normal/Dig-subsampling */
+	{0x0F, 0x12, 0x3C, 0x00}, /*  senHal_ContPtrs_senModesDataArr */
+	{0x0F, 0x12, 0x70, 0x00}, /*  senHal_ContPtrs_senModesDataArr */
+
+	/* 1.15fps@92MHz,HS,Normal 2.15fps@92MHz,LS,Normal  */
+	/* 3.15fps@92MHz,HS,avg    4.15fps@92MHz,LS,avg    */
+
+	/* 1. */
+	{0x00, 0x2A, 0x3C, 0x00},	/* 1.    2.    3.    4.   */
+	{0x0F, 0x12, 0x00, 0x03},	/* 0003  0003  0003  0003 */
+	{0x0F, 0x12, 0x05, 0xBA},	/* 05BA  098A  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0x01},	/* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x05, 0xBC},	/* 05BC  098C  0414  05CE */
+	{0x0F, 0x12, 0x00, 0x01},	/* 0001  0001  040F  05C9 */
+	{0x0F, 0x12, 0x05, 0xBC},	/* 05BC  098C  0820  0B94 */
+	{0x0F, 0x12, 0x00, 0x14},	/* 0014  0014  0014  0014 */
+	{0x0F, 0x12, 0x05, 0xBC},	/* 05BC  098C  040F  05C9 */
+	{0x0F, 0x12, 0x00, 0x14},	/* 0014  0014  0422  05DC */
+	{0x0F, 0x12, 0x05, 0xBC},	/* 05BC  098C  0820  0B94 */
+	{0x0F, 0x12, 0x01, 0xAE},	/* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x02, 0x38},	/* 0238  0310  01D0  0240 */
+	{0x0F, 0x12, 0x01, 0xAE},	/* 01AE  0286  0554  077E */
+	{0x0F, 0x12, 0x02, 0x38},	/* 0238  0310  05DE  0808 */
+	{0x0F, 0x12, 0x02, 0x38},	  /* 0238  0310  01D0  0240 */
+	{0x0F, 0x12, 0x05, 0xBA},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  05DE  0808 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x01, 0xAC},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0414  05CE */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x01, 0xAC},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x02, 0x40},	  /* 0240  0318  01D8  0248 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  05E6  0810 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x8C},	  /* 008C  008C  008C  008C */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  049A  0654 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x9E},	  /* 009E  009E  009E  009E */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  04AC  0666 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x01, 0xAC},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x00, 0xA6},	  /* 00A6  00A6  00A6  00A6 */
+	{0x0F, 0x12, 0x05, 0xBA},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  04B4  066E */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x02, 0x92},	  /* 0292  036A  022A  029A */
+	{0x0F, 0x12, 0x05, 0xBA},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0638  0862 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0xD8},	  /* 00D8  00D8  00D8  00D8 */
+	{0x0F, 0x12, 0x01, 0xA8},	  /* 01A8  0278  0140  01A8 */
+	{0x0F, 0x12, 0x02, 0xC4},	  /* 02C4  039C  0292  02CC */
+	{0x0F, 0x12, 0x05, 0xB4},	  /* 05B4  097C  040A  05BC */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  04E6  06A0 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  054E  0770 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  06A0  0894 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0818  0B84 */
+	{0x0F, 0x12, 0x01, 0xAA},	  /* 01AA  0282  0142  01B2 */
+	{0x0F, 0x12, 0x01, 0xD6},	  /* 01D6  02AE  016E  01DE */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  040C  05C6 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0438  05F2 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0550  077A */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  057C  07A6 */
+	{0x0F, 0x12, 0x01, 0xBB},	  /* 01BB  0293  014D  01BD */
+	{0x0F, 0x12, 0x01, 0xEF},	  /* 01EF  02C7  0182  01F2 */
+	{0x0F, 0x12, 0x01, 0xF9},	  /* 01F9  02D1  018C  01FC */
+	{0x0F, 0x12, 0x02, 0x03},	  /* 0203  02DB  0196  0206 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0417  05D1 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  044C  0606 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0456  0610 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0460  061A */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  055B  0785 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0590  07BA */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  059A  07C4 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  05A4  07CE */
+	{0x0F, 0x12, 0x01, 0xCC},	  /* 01CC  02A4  0158  01C8 */
+	{0x0F, 0x12, 0x01, 0xEF},	  /* 01EF  02C7  0182  01F2 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0422  05DC */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  044C  0606 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0566  0790 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0590  07BA */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x0D},	  /* 000D  000D  000D  000D */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x0D},	  /* 000D  000D  000D  000D */
+	{0x0F, 0x12, 0x01, 0xAE},	  /* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x01, 0xB6},	  /* 01B6  028E  014E  01BE */
+	{0x0F, 0x12, 0x05, 0xBA},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x05, 0xC6},	  /* 05C6  0996  0418  05D2 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0554  077E */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  055C  0786 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  082A  0B9E */
+	{0x0F, 0x12, 0x00, 0xD4},	  /* 00D4  00D4  00D4  00D4 */
+	{0x0F, 0x12, 0x01, 0xAC},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x02, 0xC0},	  /* 02C0  0398  028E  02C8 */
+	{0x0F, 0x12, 0x05, 0xB8},	  /* 05B8  0988  040E  05C8 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  04E2  069C */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  069C  0890 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  081C  0B90 */
+	{0x0F, 0x12, 0x01, 0xAE},	  /* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x05, 0xC9},	  /* 05C9  0A7C  0410  05CA */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0554  077E */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0830  0BA4 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+
+	/* HS_avg */
+	{0x00, 0x2A, 0x17, 0xDC}, /*  High speed Normal/Dig-subsampling */
+	{0x0F, 0x12, 0x3C, 0xE0}, /*  senHal_ContPtrs_senModesDataArr */
+	{0x0F, 0x12, 0x70, 0x00}, /*  senHal_ContPtrs_senModesDataArr */
+
+	/* 1.15fps@92MHz,HS,Normal 2.15fps@92MHz,LS,Normal  */
+	/* 3.15fps@92MHz,HS,avg    4.15fps@92MHz,LS,avg    */
+
+	/* 1. */
+	{0x00, 0x2A, 0x3C, 0xE0}, /* 1.    2.    3.    4.   */
+	{0x0F, 0x12, 0x00, 0x03}, /* 0003  0003  0003  0003 */
+	{0x0F, 0x12, 0x08, 0x1E},	  /* 05BA  098A  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x04, 0x14},	  /* 05BC  098C  0414  05CE */
+	{0x0F, 0x12, 0x04, 0x0F},	  /* 0001  0001  040F  05C9 */
+	{0x0F, 0x12, 0x08, 0x20},	  /* 05BC  098C  0820  0B94 */
+	{0x0F, 0x12, 0x00, 0x14},	  /* 0014  0014  0014  0014 */
+	{0x0F, 0x12, 0x04, 0x0F},	  /* 05BC  098C  040F  05C9 */
+	{0x0F, 0x12, 0x04, 0x22},	  /* 0014  0014  0422  05DC */
+	{0x0F, 0x12, 0x08, 0x20},	  /* 05BC  098C  0820  0B94 */
+	{0x0F, 0x12, 0x01, 0x46},	  /* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x01, 0xD0},	  /* 0238  0310  01D0  0240 */
+	{0x0F, 0x12, 0x05, 0x54},	  /* 01AE  0286  0554  077E */
+	{0x0F, 0x12, 0x05, 0xDE},	  /* 0238  0310  05DE  0808 */
+	{0x0F, 0x12, 0x01, 0xD0},	  /* 0238  0310  01D0  0240 */
+	{0x0F, 0x12, 0x04, 0x10},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x05, 0xDE},	  /* 0000  0000  05DE  0808 */
+	{0x0F, 0x12, 0x08, 0x1E},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x01, 0x44},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x04, 0x14},	  /* 0000  0000  0414  05CE */
+	{0x0F, 0x12, 0x05, 0x52},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x01, 0x44},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x01, 0xD8},	  /* 0240  0318  01D8  0248 */
+	{0x0F, 0x12, 0x05, 0x52},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x05, 0xE6},	  /* 0000  0000  05E6  0810 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x8C},	  /* 008C  008C  008C  008C */
+	{0x0F, 0x12, 0x04, 0x0F},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x04, 0x9A},	  /* 0000  0000  049A  0654 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x9E},	  /* 009E  009E  009E  009E */
+	{0x0F, 0x12, 0x04, 0x0F},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x04, 0xAC},	  /* 0000  0000  04AC  0666 */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x01, 0x44},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x04, 0x0F},	  /* 0000  0000  040F  05C9 */
+	{0x0F, 0x12, 0x05, 0x52},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x00, 0xA6},	  /* 00A6  00A6  00A6  00A6 */
+	{0x0F, 0x12, 0x04, 0x10},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x04, 0xB4},	  /* 0000  0000  04B4  066E */
+	{0x0F, 0x12, 0x08, 0x1E},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x02, 0x2A},	  /* 0292  036A  022A  029A */
+	{0x0F, 0x12, 0x04, 0x10},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x06, 0x38},	  /* 0000  0000  0638  0862 */
+	{0x0F, 0x12, 0x08, 0x1E},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x00, 0xD8},	  /* 00D8  00D8  00D8  00D8 */
+	{0x0F, 0x12, 0x01, 0x40},	  /* 01A8  0278  0140  01A8 */
+	{0x0F, 0x12, 0x02, 0x92},	  /* 02C4  039C  0292  02CC */
+	{0x0F, 0x12, 0x04, 0x0A},	  /* 05B4  097C  040A  05BC */
+	{0x0F, 0x12, 0x04, 0xE6},	  /* 0000  0000  04E6  06A0 */
+	{0x0F, 0x12, 0x05, 0x4E},	  /* 0000  0000  054E  0770 */
+	{0x0F, 0x12, 0x06, 0xA0},	  /* 0000  0000  06A0  0894 */
+	{0x0F, 0x12, 0x08, 0x18},	  /* 0000  0000  0818  0B84 */
+	{0x0F, 0x12, 0x01, 0x42},	  /* 01AA  0282  0142  01B2 */
+	{0x0F, 0x12, 0x01, 0x6E},	  /* 01D6  02AE  016E  01DE */
+	{0x0F, 0x12, 0x04, 0x0C},	  /* 0000  0000  040C  05C6 */
+	{0x0F, 0x12, 0x04, 0x38},	  /* 0000  0000  0438  05F2 */
+	{0x0F, 0x12, 0x05, 0x50},	  /* 0000  0000  0550  077A */
+	{0x0F, 0x12, 0x05, 0x7C},	  /* 0000  0000  057C  07A6 */
+	{0x0F, 0x12, 0x01, 0x4D},	  /* 01BB  0293  014D  01BD */
+	{0x0F, 0x12, 0x01, 0x82},	  /* 01EF  02C7  0182  01F2 */
+	{0x0F, 0x12, 0x01, 0x8C},	  /* 01F9  02D1  018C  01FC */
+	{0x0F, 0x12, 0x01, 0x96},	  /* 0203  02DB  0196  0206 */
+	{0x0F, 0x12, 0x04, 0x17},	  /* 0000  0000  0417  05D1 */
+	{0x0F, 0x12, 0x04, 0x4C},	  /* 0000  0000  044C  0606 */
+	{0x0F, 0x12, 0x04, 0x56},	  /* 0000  0000  0456  0610 */
+	{0x0F, 0x12, 0x04, 0x60},	  /* 0000  0000  0460  061A */
+	{0x0F, 0x12, 0x05, 0x5B},	  /* 0000  0000  055B  0785 */
+	{0x0F, 0x12, 0x05, 0x90},	  /* 0000  0000  0590  07BA */
+	{0x0F, 0x12, 0x05, 0x9A},	  /* 0000  0000  059A  07C4 */
+	{0x0F, 0x12, 0x05, 0xA4},	  /* 0000  0000  05A4  07CE */
+	{0x0F, 0x12, 0x01, 0x58},	  /* 01CC  02A4  0158  01C8 */
+	{0x0F, 0x12, 0x01, 0x82},	  /* 01EF  02C7  0182  01F2 */
+	{0x0F, 0x12, 0x04, 0x22},	  /* 0000  0000  0422  05DC */
+	{0x0F, 0x12, 0x04, 0x4C},	  /* 0000  0000  044C  0606 */
+	{0x0F, 0x12, 0x05, 0x66},	  /* 0000  0000  0566  0790 */
+	{0x0F, 0x12, 0x05, 0x90},	  /* 0000  0000  0590  07BA */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x0D},	  /* 000D  000D  000D  000D */
+	{0x0F, 0x12, 0x00, 0x01},	  /* 0001  0001  0001  0001 */
+	{0x0F, 0x12, 0x00, 0x0D},	  /* 000D  000D  000D  000D */
+	{0x0F, 0x12, 0x01, 0x46},	  /* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x01, 0x4E},	  /* 01B6  028E  014E  01BE */
+	{0x0F, 0x12, 0x04, 0x10},	  /* 05BA  098A  0410  05CA */
+	{0x0F, 0x12, 0x04, 0x18},	  /* 05C6  0996  0418  05D2 */
+	{0x0F, 0x12, 0x05, 0x54},	  /* 0000  0000  0554  077E */
+	{0x0F, 0x12, 0x05, 0x5C},	  /* 0000  0000  055C  0786 */
+	{0x0F, 0x12, 0x08, 0x1E},	  /* 0000  0000  081E  0B92 */
+	{0x0F, 0x12, 0x08, 0x2A},	  /* 0000  0000  082A  0B9E */
+	{0x0F, 0x12, 0x00, 0xD4},	  /* 00D4  00D4  00D4  00D4 */
+	{0x0F, 0x12, 0x01, 0x44},	  /* 01AC  0284  0144  01B4 */
+	{0x0F, 0x12, 0x02, 0x8E},	  /* 02C0  0398  028E  02C8 */
+	{0x0F, 0x12, 0x04, 0x0E},	  /* 05B8  0988  040E  05C8 */
+	{0x0F, 0x12, 0x04, 0xE2},	  /* 0000  0000  04E2  069C */
+	{0x0F, 0x12, 0x05, 0x52},	  /* 0000  0000  0552  077C */
+	{0x0F, 0x12, 0x06, 0x9C},	  /* 0000  0000  069C  0890 */
+	{0x0F, 0x12, 0x08, 0x1C},	  /* 0000  0000  081C  0B90 */
+	{0x0F, 0x12, 0x01, 0x46},	  /* 01AE  0286  0146  01B6 */
+	{0x0F, 0x12, 0x04, 0x10},	  /* 05C9  0A7C  0410  05CA */
+	{0x0F, 0x12, 0x05, 0x54},	  /* 0000  0000  0554  077E */
+	{0x0F, 0x12, 0x08, 0x30},	  /* 0000  0000  0830  0BA4 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+	{0x0F, 0x12, 0x00, 0x00},	  /* 0000  0000  0000  0000 */
+
+	{REG_DELAY, 100, 0, 0}, /*  p100 */
+
+	/* Current(00:2mA,01:4mA,10:6mA,11:8mA) */
+	{0x00, 0x28, 0xD0, 0x00},
+	{0x00, 0x2A, 0x10, 0x82},
+	{0x0F, 0x12, 0x01, 0x55}, /* FFFF	D0_D4_cs12 [11:0] */
+	{0x0F, 0x12, 0x01, 0x55}, /* FFFF	D0_D4_cs12 [11:0] */
+	{0x00, 0x2A, 0x10, 0x88},
+	{0x0F, 0x12, 0x05, 0x55}, /* 05CF	0555 Sda_cd10	Scl_cd10
+		PCLK_cd10	Reserved	Vsync_cd10	Hsync_cd10 */
+
+	{REG_DELAY, 100, 0, 0}, /*  p100 */
+
+	/*  End Analog script */
+
+	/*  */
+	/*  Start Tuning param for EVT1 */
+	/*  */
+
+	/* / AF Setting Start */
+	/*  AF Interface Settings */
+	{0x00, 0x28, 0x70, 0x00},
+	{0x00, 0x2A, 0x02, 0x3E},
+	{0x0F, 0x12, 0x00, 0x03}, /*  AFModeType - 0:NONE, 2:VCM_PWM,
+				* 3:VCM_I2C */
+	{0x00, 0x2A, 0x02, 0x3C},
+	{0x0F, 0x12, 0x00, 0x00}, /*  No Led Gpio */
+	{0x00, 0x2A, 0x02, 0x40},
+	{0x0F, 0x12, 0x00, 0x00}, /*  No PWM */
+	{0x00, 0x2A, 0x02, 0x42},
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x02, 0x44},
+	{0x0F, 0x12, 0x00, 0x31}, /*  No GPIO Port,
+				31	 Use GPIO3 for Enable Port */
+	{0x00, 0x2A, 0x02, 0x46},
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x02, 0x4C},
+	{0x0F, 0x12, 0x20, 0x0C}, /*  Use GPIO1 for SCL, GPIO2 for SDA */
+	{0x00, 0x2A, 0x02, 0x4E},
+	{0x0F, 0x12, 0x03, 0x20}, /* 0C0 0190	0320	 MI2C Speed : 400KHz */
+
+	/*  AF Window Settings */
+	{0x00, 0x2A, 0x02, 0xC6},
+	{0x0F, 0x12, 0x01, 0x00},
+	{0x00, 0x2A, 0x02, 0xC8},
+	{0x0F, 0x12, 0x00, 0xE3},
+	{0x00, 0x2A, 0x02, 0xCA},
+	{0x0F, 0x12, 0x02, 0x00},
+	{0x00, 0x2A, 0x02, 0xCC},
+	{0x0F, 0x12, 0x02, 0x38},
+	{0x00, 0x2A, 0x02, 0xCE},
+	{0x0F, 0x12, 0x01, 0x8C},
+	{0x00, 0x2A, 0x02, 0xD0},
+	{0x0F, 0x12, 0x01, 0x66},
+	{0x00, 0x2A, 0x02, 0xD2},
+	{0x0F, 0x12, 0x00, 0xE6},
+	{0x00, 0x2A, 0x02, 0xD4},
+	{0x0F, 0x12, 0x01, 0x32},
+	{0x00, 0x2A, 0x02, 0xD6},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	/*  AF Setot Settings */
+	{0x00, 0x2A, 0x06, 0xBE},
+	{0x0F, 0x12, 0x00, 0xFF},
+
+	/*  AF Scene Settings */
+	{0x00, 0x2A, 0x15, 0xDA},
+	{0x0F, 0x12, 0x00, 0x03},
+
+	/*  AF Fine Search Settings */
+	{0x00, 0x2A, 0x15, 0x50},
+	{0x0F, 0x12, 0x10, 0x02},
+	{0x00, 0x2A, 0x15, 0x5A},
+	{0x0F, 0x12, 0x00, 0x04},
+	{0x00, 0x2A, 0x14, 0xE8},
+	{0x0F, 0x12, 0x03, 0x02},
+
+
+	/*  AF Lens Position Table Settings */
+	{0x00, 0x2A, 0x14, 0xF0},
+	{0x0F, 0x12, 0x00, 0x11}, /*  18 Steps	 */
+	{0x0f, 0x12, 0x00, 0x36}, /*  af_pos_usTable */
+	{0x0F, 0x12, 0x00, 0x3D},
+	{0x0F, 0x12, 0x00, 0x44},
+	{0x0F, 0x12, 0x00, 0x4B},
+	{0x0F, 0x12, 0x00, 0x52},
+	{0x0F, 0x12, 0x00, 0x59},
+	{0x0F, 0x12, 0x00, 0x60},
+	{0x0F, 0x12, 0x00, 0x67},
+	{0x0F, 0x12, 0x00, 0x6E},
+	{0x0F, 0x12, 0x00, 0x75},
+	{0x0F, 0x12, 0x00, 0x7C},
+	{0x0F, 0x12, 0x00, 0x83},
+	{0x0F, 0x12, 0x00, 0x8A},
+	{0x0F, 0x12, 0x00, 0x91},
+	{0x0F, 0x12, 0x00, 0x98},
+	{0x0F, 0x12, 0x00, 0x9F},
+	{0x0F, 0x12, 0x00, 0xA6},
+	{0x0F, 0x12, 0x00, 0xAD},
+
+	/*  AF Macro Position Setting */
+	{0x00, 0x2A, 0x14, 0xE2},
+	{0x0F, 0x12, 0x11, 0x04},
+
+	/* / AF Setting End */
+
+	/* /Jpeg/ */
+	{0x00, 0x2A, 0x16, 0x90},
+	{0x0F, 0x12, 0x01, 0x8E}, /* jpeg_BrcMaxQuality */
+	{0x00, 0x2A, 0x16, 0xD6},
+	{0x0F, 0x12, 0x00, 0x01}, /* jpeg_MinQtblValue */
+	{0x00, 0x2A, 0x04, 0xC0},
+	{0x0F, 0x12, 0x00, 0x5D}, /* 005F 005D
+				* 4EA_REG_TC_BRC_usCaptureQuality(4~99_dec) */
+
+};
+
+unsigned short s5k4ea_init_reg2[][2] = {
+	/* clk Settings */
+	{0x002A, S5K4EA_REG_TC_IPRM_InClockLSBs}, /* input=24MHz */
+	{0x0F12, 0xBB80}, /*  input=48MHz : source clk is mpll */
+	{0x002A, S5K4EA_REG_TC_IPRM_InClockMSBs},
+	{0x0F12, 0x0000},
+	{0x002A, S5K4EA_REG_TC_IPRM_UseNPviClocks}, /* 0 PVI configurations */
+	{0x0F12, 0x0000},
+	{0x002A, S5K4EA_REG_TC_IPRM_UseNMipiClocks}, /* 1 MIPI configurations */
+	{0x0F12, 0x0001},
+	{0x002A, S5K4EA_REG_TC_IPRM_NumberOfMipiLanes}, /*  Num of lane MIPI  */
+	{0x0F12, 2},
+	{0x002A, S5K4EA_REG_TC_IPRM_OpClk4KHz_0}, /*  1st system CLK 92MHz
+						* for parallel */
+	{0x0F12, S5K4EA4Khz_92Mhz}, /*  2CEC */
+	{0x002A, S5K4EA_REG_TC_IPRM_MinOutRate4KHz_0},	/* Pclk : 92Mhz */
+	{0x0F12, S5K4EA_PCLK_MIN},
+	{0x002A, S5K4EA_REG_TC_IPRM_MaxOutRate4KHz_0},
+	{0x0F12, S5K4EA_PCLK_MAX},
+	{0x002A, S5K4EA_REG_TC_IPRM_InitParamsUpdated},
+	{0x0F12, 0x0001},
+	{REG_DELAY, 100}, /*  p100 */
+};
+
+unsigned char s5k4ea_init_reg3[][4] = {
+	/* AE Setting */
+	{0x00, 0x2A, 0x13, 0xC8},
+	{0x0F, 0x12, 0x00, 0x30}, /* 3C	002D 003C 003A 0030 003A 0038 003C 0035
+				TVAR_ae_BrAve	  AE target	 */
+	{0x00, 0x2A, 0x13, 0xCE},
+	{0x0F, 0x12, 0x00, 0x0F}, /* 0011  ae_StatMode */
+	{0x00, 0x2A, 0x05, 0x90},
+	{0x0F, 0x12, 0x35, 0x20}, /* lt_uMaxExp1 (x4 8000/ 80ms) */
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x05, 0x94},
+	{0x0F, 0x12, 0xC3, 0x50},
+	{0x0F, 0x12, 0x00, 0x00}, /* lt_uMaxExp2 (x4 25000/ 250ms) */
+	{0x00, 0x2A, 0x05, 0x98},
+	{0x0F, 0x12, 0x35, 0x20},
+	{0x0F, 0x12, 0x00, 0x00}, /* lt_uCapMaxExp1 (x4 8000/ 80ms) */
+	{0x00, 0x2A, 0x05, 0x9C},
+	{0x0F, 0x12, 0xC3, 0x50}, /* C350	86A0	 */
+	{0x0F, 0x12, 0x00, 0x00}, /* lt_uCapMaxExp2 (x4 25000/ 250ms) */
+	{0x00, 0x2A, 0x05, 0xA0},
+	{0x0F, 0x12, 0x04, 0x70}, /* (1/12) 0350 (1/8) 0200 lt_uMaxAnGain1 */
+	{0x00, 0x2A, 0x05, 0xA2},
+	{0x0F, 0x12, 0x10, 0x00}, /* lt_uMaxAnGain2 */
+	{0x00, 0x2A, 0x05, 0xA4},
+	{0x0F, 0x12, 0x01, 0x00},
+	{0x00, 0x2A, 0x05, 0xA6},
+	{0x0F, 0x12, 0x10, 0x00}, /* lt_uMaxTotGain (Limit Gain) */
+
+	{0x00, 0x2A, 0x05, 0x74},
+	{0x0F, 0x12, 0x01, 0x11}, /* lt_uLimitHigh */
+	{0x00, 0x2A, 0x05, 0x76},
+	{0x0F, 0x12, 0x00, 0xEF}, /* lt_uLimitLow */
+};
+
+unsigned short s5k4ea_init_reg4[][2] = {
+	/* / */
+	/* PREVIEW CONFIGURATION 0 (FullHD, YUV, 20fps) */
+	{0x002A, S5K4EA_REG_0TC_PCFG_usWidth},
+	{0x0F12, 1920},	/* 1920 */
+	{0x0F12, 1080}, /* 1080 */
+	{0x002A, 0x02E6},
+};
+
+unsigned char s5k4ea_init_reg5[][4] = {
+	{0x0F, 0x12, 0x00, 0x05}, /* YUV */
+	{0x00, 0x2A, 0x02, 0xF8}, /* PLL config */
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x02, 0xE8}, /* PCLK max */
+};
+
+unsigned char s5k4ea_init_jpeg[][4] = {
+	{0x0F, 0x12, 0x00, 0x09},	/* YUV */
+	{0x00, 0x2A, 0x02, 0xF8},	/* PLL config */
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x02, 0xE8},	/* PCLK max */
+};
+
+unsigned short s5k4ea_init_reg6[][2] = {
+	{0x0F12, S5K4EA_PCLK_MAX},
+};
+
+unsigned char s5k4ea_init_reg7[][4] = {
+	{0x00, 0x2A, 0x02, 0xEA}, /* PCLK min */
+};
+
+unsigned short s5k4ea_init_reg8[][2] = {
+	{0x0F12, S5K4EA_PCLK_MIN},
+};
+
+unsigned char s5k4ea_init_reg9[][4] = {
+	{0x00, 0x2A, 0x02, 0xF0}, /*  KJ_090802 : Non-continuous clock */
+	{0x0F, 0x12, 0x00, 0x12}, /*  [4]UY0VY1	0002 */
+	{0x00, 0x2A, 0x02, 0xFC}, /*  1b: FR (bin) 2b: Quality (no-bin) */
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x02, 0xFA},
+	{0x0F, 0x12, 0x00, 0x02},
+	{0x00, 0x2A, 0x02, 0xFE}, /* max frame time  */
+	{0x0F, 0x12, 0x05, 0x35},/*  7.5fps */
+	{0x00, 0x2A, 0x03, 0x00},
+	{0x0F, 0x12, 0x00, 0x00},
+
+	{REG_DELAY, 100, 0, 0}, /*  p100 */
+
+	/* 002A	17A0 */
+	/* 0F12	0000 [0]:dig [1]:avg */
+	/* 002A	17A2 1/2 sub-sampling */
+	/* 0F12	0002 */
+	{0x00, 0x2A, 0x05, 0x40}, /*  use high speed analog */
+	{0x0F, 0x12, 0x00, 0x01},
+	{0x00, 0x2A, 0x05, 0x3A},
+	{0x0F, 0x12, 0x00, 0x01},
+	/* 002A	17B2 17B2 */
+	/* 0F12	0549 */
+	/* 002A	17B6 17B6 */
+	/* 0F12	0549 */
+	/* 002A	17BA 17BA */
+	/* 0F12	005B */
+
+	/* For C100 -  jpeg output data  type control
+	 * 0028	 D000 002A	B032  0F12	 002A */
+	/*  JPEG data type (RAW8 type) */
+
+	{0x00, 0x28, 0x70, 0x00},
+
+	/* Capture Configuratio 0 (2592x1944,  MJPEG, 15fps) */
+	{0x00, 0x2A, 0x03, 0xD6},
+	{0x0F, 0x12, 0x0A, 0x20}, /* 2592 */
+	{0x00, 0x2A, 0x03, 0xD8},
+	{0x0F, 0x12, 0x07, 0x98}, /* 1944 */
+	{0x00, 0x2A, 0x03, 0xDA},
+	{0x0F, 0x12, 0x00, 0x09}, /* YUV */
+	{0x00, 0x2A, 0x03, 0xEC}, /* PLL config */
+	{0x0F, 0x12, 0x00, 0x00},
+	{0x00, 0x2A, 0x03, 0xDC}, /* PCLK max */
+	{0x0F, 0x12, 0x5A, 0xD2},
+	{0x00, 0x2A, 0x03, 0xDE}, /* PCLK min */
+	{0x0F, 0x12, 0x58, 0xDE},
+	{0x00, 0x2A, 0x03, 0xE4},
+	{0x0F, 0x12, 0x00, 0x42},
+	{0x00, 0x2A, 0x03, 0xF0}, /*  1b: FR (bin) 2b: Quality (no-bin) */
+	{0x0F, 0x12, 0x00, 0x02},
+	{0x00, 0x2A, 0x03, 0xEE},
+	{0x0F, 0x12, 0x00, 0x02},
+	{0x00, 0x2A, 0x03, 0xF2}, /* max frame time : 15fps 029a */
+	{0x0F, 0x12, 0x05, 0x35}, /*  7.5 fps */
+	{0x00, 0x2A, 0x03, 0xF4},
+	{0x0F, 0x12, 0x00, 0x00},
+
+	/*  */
+	/* PREVIEW */
+	{0x00, 0x2A, 0x02, 0xA4},
+	{0x0F, 0x12, 0x00, 0x00},
+
+	{0x00, 0x2A, 0x02, 0xA8},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x90},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0xA6},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x80},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x82},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	/*  */
+
+	{0x00, 0x2A, 0x02, 0x92},
+	{0x0F, 0x12, 0x07, 0x80}, /* input width  */
+	{0x0F, 0x12, 0x04, 0x38}, /* input height */
+	{0x0F, 0x12, 0x01, 0x50}, /* input w-offset */
+	{0x0F, 0x12, 0x01, 0xB0}, /* input h-offset */
+
+	{0x00, 0x2A, 0x04, 0xDA},
+	{0x0F, 0x12, 0x07, 0x80}, /* crop width  */
+	{0x0F, 0x12, 0x04, 0x38}, /* crop height */
+	/* 0F12	0150	w-offset */
+	/* 0F12	01B0	h-offset */
+
+	{0x00, 0x2A, 0x02, 0xA2}, /* 4EA_REG_TC_GP_InputsChangeRequest */
+	{0x0F, 0x12, 0x00, 0x01},
+	{0x00, 0x2A, 0x02, 0x90}, /* 4EA_REG_TC_GP_NewConfigSync */
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{REG_DELAY, 200, 0, 0}, /*  p200 */
+};
+
+unsigned short s5k4ea_init_reg10[][2] = {
+	{0x002A, S5K4EA_REG_0TC_PCFG_usMaxFrTimeMsecMult10},/* max frame time */
+	{0x0F12, S5K4EA_FrTime_MAX}, /* 30fps */
+};
+
+unsigned char s5k4ea_init_reg11[][4] = {
+	/*  */
+	/* PREVIEW */
+	{0x00, 0x2A, 0x02, 0xA4},
+	{0x0F, 0x12, 0x00, 0x00},
+
+	{0x00, 0x2A, 0x02, 0xA8},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x90},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0xA6},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x80},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	{0x00, 0x2A, 0x02, 0x82},
+	{0x0F, 0x12, 0x00, 0x01},
+
+	/*  */
+
+	/*  AF CMD */
+	{0x00, 0x2A, 0x02, 0xBE}, /* #4EA_REG_TC_AF	 */
+	{0x0F, 0x12, 0x00, 0x03}, /* 4EA_REG_TC_AF_AfCmd */
+
+	{REG_DELAY, 200, 0, 0}, /*  p300 */
+
+	{0x00, 0x2A, 0x02, 0xBE}, /* #4EA_REG_TC_AF	 */
+	{0x0F, 0x12, 0x00, 0x05}, /* 5:single AF, 6:continus AF */
+};
+
+#define S5K4EA_INIT_REGS1	\
+	(sizeof(s5k4ea_init_reg1) / sizeof(s5k4ea_init_reg1[0]))
+#define S5K4EA_INIT_REGS2	\
+	(sizeof(s5k4ea_init_reg2) / sizeof(s5k4ea_init_reg2[0]))
+#define S5K4EA_INIT_REGS3	\
+	(sizeof(s5k4ea_init_reg3) / sizeof(s5k4ea_init_reg3[0]))
+#define S5K4EA_INIT_REGS4	\
+	(sizeof(s5k4ea_init_reg4) / sizeof(s5k4ea_init_reg4[0]))
+#define S5K4EA_INIT_JPEG	\
+	(sizeof(s5k4ea_init_jpeg) / sizeof(s5k4ea_init_jpeg[0]))
+#define S5K4EA_INIT_REGS5\
+	(sizeof(s5k4ea_init_reg5) / sizeof(s5k4ea_init_reg5[0]))
+#define S5K4EA_INIT_REGS6	\
+	(sizeof(s5k4ea_init_reg6) / sizeof(s5k4ea_init_reg6[0]))
+#define S5K4EA_INIT_REGS7	\
+	(sizeof(s5k4ea_init_reg7) / sizeof(s5k4ea_init_reg7[0]))
+#define S5K4EA_INIT_REGS8	\
+	(sizeof(s5k4ea_init_reg8) / sizeof(s5k4ea_init_reg8[0]))
+#define S5K4EA_INIT_REGS9	\
+	(sizeof(s5k4ea_init_reg9) / sizeof(s5k4ea_init_reg9[0]))
+#define S5K4EA_INIT_REGS10	\
+	(sizeof(s5k4ea_init_reg10) / sizeof(s5k4ea_init_reg10[0]))
+#define S5K4EA_INIT_REGS11	\
+	(sizeof(s5k4ea_init_reg11) / sizeof(s5k4ea_init_reg11[0]))
+
+unsigned short s5k4ea_sleep_reg[][2] = {
+	{0x002A, S5K4EA_REG_TC_GP_EnablePreview},
+	{0x0F12, 0x0000},
+	{0x002A, S5K4EA_REG_TC_GP_EnablePreviewChanged},
+	{0x0F12, 0x0001},
+	{REG_DELAY, 100},
+};
+
+#define S5K4EA_SLEEP_REGS	\
+	(sizeof(s5k4ea_sleep_reg) / sizeof(s5k4ea_sleep_reg[0]))
+
+unsigned short s5k4ea_wakeup_reg[][2] = {
+	{0x002A, 0x02F0},
+	{0x0F12, 0x0052},
+	{0x002A, S5K4EA_REG_TC_GP_PrevConfigChanged},
+	{0x0F12, 0x0001},
+};
+
+#define S5K4EA_WAKEUP_REGS	\
+	(sizeof(s5k4ea_wakeup_reg) / sizeof(s5k4ea_wakeup_reg[0]))
+
+/* Preview configuration preset #1 */
+/* Preview configuration preset #2 */
+/* Preview configuration preset #3 */
+/* Preview configuration preset #4 */
+
+/* Capture configuration preset #0 */
+/* Capture configuration preset #1 */
+/* Capture configuration preset #2 */
+/* Capture configuration preset #3 */
+/* Capture configuration preset #4 */
+
+/*
+ * EV bias
+ */
+
+static const struct s5k4ea_reg s5k4ea_ev_m6[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_m5[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_m4[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_m3[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_m2[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_m1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_default[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p2[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p3[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p4[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p5[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_ev_p6[] = {
+};
+
+#ifdef S5K4EA_COMPLETE
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ea_regs_ev_bias[] = {
+	(unsigned char *)s5k4ea_ev_m6, (unsigned char *)s5k4ea_ev_m5,
+	(unsigned char *)s5k4ea_ev_m4, (unsigned char *)s5k4ea_ev_m3,
+	(unsigned char *)s5k4ea_ev_m2, (unsigned char *)s5k4ea_ev_m1,
+	(unsigned char *)s5k4ea_ev_default, (unsigned char *)s5k4ea_ev_p1,
+	(unsigned char *)s5k4ea_ev_p2, (unsigned char *)s5k4ea_ev_p3,
+	(unsigned char *)s5k4ea_ev_p4, (unsigned char *)s5k4ea_ev_p5,
+	(unsigned char *)s5k4ea_ev_p6,
+};
+
+/*
+ * Auto White Balance configure
+ */
+static const struct s5k4ea_reg s5k4ea_awb_off[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_awb_on[] = {
+};
+
+static const unsigned char *s5k4ea_regs_awb_enable[] = {
+	(unsigned char *)s5k4ea_awb_off,
+	(unsigned char *)s5k4ea_awb_on,
+};
+
+/*
+ * Manual White Balance (presets)
+ */
+static const struct s5k4ea_reg s5k4ea_wb_tungsten[] = {
+
+};
+
+static const struct s5k4ea_reg s5k4ea_wb_fluorescent[] = {
+
+};
+
+static const struct s5k4ea_reg s5k4ea_wb_sunny[] = {
+
+};
+
+static const struct s5k4ea_reg s5k4ea_wb_cloudy[] = {
+
+};
+
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ea_regs_wb_preset[] = {
+	(unsigned char *)s5k4ea_wb_tungsten,
+	(unsigned char *)s5k4ea_wb_fluorescent,
+	(unsigned char *)s5k4ea_wb_sunny,
+	(unsigned char *)s5k4ea_wb_cloudy,
+};
+
+/*
+ * Color Effect (COLORFX)
+ */
+static const struct s5k4ea_reg s5k4ea_color_sepia[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_color_aqua[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_color_monochrome[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_color_negative[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_color_sketch[] = {
+};
+
+/* Order of this array should be following the querymenu data */
+static const unsigned char *s5k4ea_regs_color_effect[] = {
+	(unsigned char *)s5k4ea_color_sepia,
+	(unsigned char *)s5k4ea_color_aqua,
+	(unsigned char *)s5k4ea_color_monochrome,
+	(unsigned char *)s5k4ea_color_negative,
+	(unsigned char *)s5k4ea_color_sketch,
+};
+
+/*
+ * Contrast bias
+ */
+static const struct s5k4ea_reg s5k4ea_contrast_m2[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_contrast_m1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_contrast_default[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_contrast_p1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_contrast_p2[] = {
+};
+
+static const unsigned char *s5k4ea_regs_contrast_bias[] = {
+	(unsigned char *)s5k4ea_contrast_m2,
+	(unsigned char *)s5k4ea_contrast_m1,
+	(unsigned char *)s5k4ea_contrast_default,
+	(unsigned char *)s5k4ea_contrast_p1,
+	(unsigned char *)s5k4ea_contrast_p2,
+};
+
+/*
+ * Saturation bias
+ */
+static const struct s5k4ea_reg s5k4ea_saturation_m2[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_saturation_m1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_saturation_default[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_saturation_p1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_saturation_p2[] = {
+};
+
+static const unsigned char *s5k4ea_regs_saturation_bias[] = {
+	(unsigned char *)s5k4ea_saturation_m2,
+	(unsigned char *)s5k4ea_saturation_m1,
+	(unsigned char *)s5k4ea_saturation_default,
+	(unsigned char *)s5k4ea_saturation_p1,
+	(unsigned char *)s5k4ea_saturation_p2,
+};
+
+/*
+ * Sharpness bias
+ */
+static const struct s5k4ea_reg s5k4ea_sharpness_m2[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_sharpness_m1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_sharpness_default[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_sharpness_p1[] = {
+};
+
+static const struct s5k4ea_reg s5k4ea_sharpness_p2[] = {
+};
+
+static const unsigned char *s5k4ea_regs_sharpness_bias[] = {
+	(unsigned char *)s5k4ea_sharpness_m2,
+	(unsigned char *)s5k4ea_sharpness_m1,
+	(unsigned char *)s5k4ea_sharpness_default,
+	(unsigned char *)s5k4ea_sharpness_p1,
+	(unsigned char *)s5k4ea_sharpness_p2,
+};
+#endif /* S5K4EA_COMPLETE */
+
+#endif
diff --git a/drivers/media/video/s5k4ea2.c b/drivers/media/video/s5k4ea2.c
new file mode 100644
index 0000000..6ebf10b
--- /dev/null
+++ b/drivers/media/video/s5k4ea2.c
@@ -0,0 +1,773 @@
+/* linux/drivers/media/video/s5k4ea.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver for S5K4EA (SXGA camera) from Samsung Electronics
+ * 1/6" 1.3Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ * supporting MIPI CSI-2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/s5k4ea_platform.h>
+
+#include <linux/videodev2_exynos_camera.h>
+
+#include "s5k4ea.h"
+
+#define S5K4EA_DRIVER_NAME	"S5K4EA"
+
+/* Default resolution & pixelformat. plz ref s5k4ea_platform.h */
+#define DEFAULT_RES		WVGA	/* Index of resoultion */
+#define DEFAUT_FPS_INDEX	S5K4EA_15FPS
+#define DEFAULT_FMT		V4L2_PIX_FMT_UYVY	/* YUV422 */
+
+/*
+ * Specification
+ * Parallel : ITU-R. 656/601 YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Serial : MIPI CSI2 (single lane) YUV422, RGB565, RGB888 (Up to VGA), RAW10
+ * Resolution : 1280 (H) x 1024 (V)
+ * Image control : Brightness, Contrast, Saturation, Sharpness, Glamour
+ * Effect : Mono, Negative, Sepia, Aqua, Sketch
+ * FPS : 15fps @full resolution, 30fps @VGA, 24fps @720p
+ * Max. pixel clock frequency : 48MHz(upto)
+ * Internal PLL (6MHz to 27MHz input frequency)
+ */
+
+/* Camera functional setting values configured by user concept */
+struct s5k4ea_userset {
+	signed int exposure_bias;	/* V4L2_CID_EXPOSURE */
+	unsigned int ae_lock;
+	unsigned int awb_lock;
+	unsigned int auto_wb;	/* V4L2_CID_AUTO_WHITE_BALANCE */
+	unsigned int manual_wb;	/* V4L2_CID_WHITE_BALANCE_PRESET */
+	unsigned int wb_temp;	/* V4L2_CID_WHITE_BALANCE_TEMPERATURE */
+	unsigned int effect;	/* Color FX (AKA Color tone) */
+	unsigned int contrast;	/* V4L2_CID_CONTRAST */
+	unsigned int saturation;	/* V4L2_CID_SATURATION */
+	unsigned int sharpness;		/* V4L2_CID_SHARPNESS */
+	unsigned int glamour;
+};
+
+struct s5k4ea_state {
+	struct s5k4ea_mbus_platform_data *pdata;
+	struct v4l2_subdev sd;
+	struct v4l2_mbus_framefmt 	fmt;
+	struct v4l2_fract 		timeperframe;
+	struct s5k4ea_userset 		userset;
+	int 				freq;	/* MCLK in KHz */
+	int 				is_mipi;
+	int 				isize;
+	int 				ver;
+	int 				fps;
+	int 				fmt_index;
+	unsigned short 			devid_mask;
+};
+
+static inline struct s5k4ea_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k4ea_state, sd);
+}
+
+/*
+ * S5K4EA register structure : 2bytes address, 2bytes value
+ * retry on write failure up-to 5 times
+ */
+static inline int s5k4ea_write(struct v4l2_subdev *sd, u16 addr, u16 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_msg msg[1];
+	unsigned char reg[4];
+	int err = 0;
+	int retry = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+again:
+	msg->addr = client->addr;
+	msg->flags = 0;
+	msg->len = 4;
+	msg->buf = reg;
+
+	reg[0] = addr >> 8;
+	reg[1] = addr & 0xff;
+	reg[2] = val >> 8;
+	reg[3] = val & 0xff;
+
+	err = i2c_transfer(client->adapter, msg, 1);
+	if (err >= 0)
+		return err;	/* Returns here on success */
+
+	/* abnormal case: retry 5 times */
+	if (retry < 5) {
+		dev_err(&client->dev, "%s: address: 0x%02x%02x, " \
+			"value: 0x%02x%02x\n", __func__, \
+			reg[0], reg[1], reg[2], reg[3]);
+		retry++;
+		goto again;
+	}
+
+	return err;
+}
+
+static int s5k4ea_i2c_write(struct v4l2_subdev *sd, unsigned char i2c_data[],
+				unsigned char length)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned char buf[length], i;
+	struct i2c_msg msg = {client->addr, 0, length, buf};
+
+	for (i = 0; i < length; i++)
+		buf[i] = i2c_data[i];
+
+	return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+}
+
+static const char *s5k4ea_querymenu_wb_preset[] = {
+	"WB Tungsten", "WB Fluorescent", "WB sunny", "WB cloudy", NULL
+};
+
+static const char *s5k4ea_querymenu_effect_mode[] = {
+	"Effect Sepia", "Effect Aqua", "Effect Monochrome",
+	"Effect Negative", "Effect Sketch", NULL
+};
+
+static const char *s5k4ea_querymenu_ev_bias_mode[] = {
+	"-3EV",	"-2,1/2EV", "-2EV", "-1,1/2EV",
+	"-1EV", "-1/2EV", "0", "1/2EV",
+	"1EV", "1,1/2EV", "2EV", "2,1/2EV",
+	"3EV", NULL
+};
+
+static struct v4l2_queryctrl s5k4ea_controls[] = {
+	{
+		/*
+		 * For now, we just support in preset type
+		 * to be close to generic WB system,
+		 * we define color temp range for each preset
+		 */
+		.id = V4L2_CID_WHITE_BALANCE_TEMPERATURE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "White balance in kelvin",
+		.minimum = 0,
+		.maximum = 10000,
+		.step = 1,
+		.default_value = 0,	/* FIXME */
+	},
+	{
+		.id = V4L2_CID_WHITE_BALANCE_PRESET,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "White balance preset",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_wb_preset) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_AUTO_WHITE_BALANCE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Auto white balance",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_EXPOSURE,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Exposure bias",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_ev_bias_mode) - 2,
+		.step = 1,
+		.default_value = (ARRAY_SIZE(s5k4ea_querymenu_ev_bias_mode) \
+				- 2) / 2,	/* 0 EV */
+	},
+	{
+		.id = V4L2_CID_COLORFX,
+		.type = V4L2_CTRL_TYPE_MENU,
+		.name = "Image Effect",
+		.minimum = 0,
+		.maximum = ARRAY_SIZE(s5k4ea_querymenu_effect_mode) - 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_CONTRAST,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Contrast",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SATURATION,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Saturation",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+	{
+		.id = V4L2_CID_SHARPNESS,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Sharpness",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 2,
+	},
+};
+
+const char * const *s5k4ea_ctrl_get_menu(u32 id)
+{
+	switch (id) {
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		return s5k4ea_querymenu_wb_preset;
+
+	case V4L2_CID_COLORFX:
+		return s5k4ea_querymenu_effect_mode;
+
+	case V4L2_CID_EXPOSURE:
+		return s5k4ea_querymenu_ev_bias_mode;
+
+	default:
+		return v4l2_ctrl_get_menu(id);
+	}
+}
+
+static inline struct v4l2_queryctrl const *s5k4ea_find_qctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ea_controls); i++)
+		if (s5k4ea_controls[i].id == id)
+			return &s5k4ea_controls[i];
+
+	return NULL;
+}
+
+static int s5k4ea_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4ea_controls); i++) {
+		if (s5k4ea_controls[i].id == qc->id) {
+			memcpy(qc, &s5k4ea_controls[i], \
+				sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int s5k4ea_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	struct v4l2_queryctrl qctrl;
+
+	qctrl.id = qm->id;
+	s5k4ea_queryctrl(sd, &qctrl);
+
+	return v4l2_ctrl_query_menu(qm, &qctrl, s5k4ea_ctrl_get_menu(qm->id));
+}
+
+/*
+ * Clock configuration
+ * Configure expected MCLK from host and return EINVAL if not supported clock
+ * frequency is expected
+ *	freq : in Hz
+ *	flag : not supported for now
+ */
+static int s5k4ea_s_crystal_freq(struct v4l2_subdev *sd, u32  freq, u32 flags)
+{
+	int err = -EINVAL;
+
+	return err;
+}
+
+static int s5k4ea_g_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	struct s5k4ea_state *state = to_state(sd);
+	int err = 0;
+
+	*fmt = state->fmt;
+	return err;
+}
+
+static int s5k4ea_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	int err = 0;
+
+	dev_dbg(&client->dev, "requested res(%d, %d)\n",
+		fmt->width, fmt->height);
+
+	if (!state->fmt.width ||
+		!state->fmt.height ||
+		!state->fmt.code)
+		state->fmt = *fmt;
+	else
+		*fmt = state->fmt;
+
+	return err;
+}
+static int s5k4ea_enum_framesizes(struct v4l2_subdev *sd,
+					struct v4l2_frmsizeenum *fsize)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
+{
+	int err = 0;
+
+	return err;
+}
+
+static int s5k4ea_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	struct s5k4ea_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		ctrl->value = userset.exposure_bias;
+		err = 0;
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		ctrl->value = userset.auto_wb;
+		err = 0;
+		break;
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		ctrl->value = userset.manual_wb;
+		err = 0;
+		break;
+	case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
+		ctrl->value = userset.wb_temp;
+		err = 0;
+		break;
+	case V4L2_CID_COLORFX:
+		ctrl->value = userset.effect;
+		err = 0;
+		break;
+	case V4L2_CID_CONTRAST:
+		ctrl->value = userset.contrast;
+		err = 0;
+		break;
+	case V4L2_CID_SATURATION:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+	case V4L2_CID_SHARPNESS:
+		ctrl->value = userset.saturation;
+		err = 0;
+		break;
+	default:
+		dev_err(&client->dev, "%s: no such ctrl\n", __func__);
+		break;
+	}
+
+	return err;
+}
+
+static int s5k4ea_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+#ifdef S5K4EA_COMPLETE
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	struct s5k4ea_userset userset = state->userset;
+	int err = -EINVAL;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_EXPOSURE\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, s5k4ea_regs_ev_bias[ctrl->value]);
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&client->dev, "%s: V4L2_CID_AUTO_WHITE_BALANCE\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_awb_enable[ctrl->value]);
+		break;
+	case V4L2_CID_WHITE_BALANCE_PRESET:
+		dev_dbg(&client->dev, "%s: V4L2_CID_WHITE_BALANCE_PRESET\n", \
+			__func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_wb_preset[ctrl->value]);
+		break;
+	case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
+		dev_dbg(&client->dev, \
+			"%s: V4L2_CID_WHITE_BALANCE_TEMPERATURE\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_wb_temperature[ctrl->value]);
+		break;
+	case V4L2_CID_COLORFX:
+		dev_dbg(&client->dev, "%s: V4L2_CID_COLORFX\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_color_effect[ctrl->value]);
+		break;
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&client->dev, "%s: V4L2_CID_CONTRAST\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_contrast_bias[ctrl->value]);
+		break;
+	case V4L2_CID_SATURATION:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SATURATION\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_saturation_bias[ctrl->value]);
+		break;
+	case V4L2_CID_SHARPNESS:
+		dev_dbg(&client->dev, "%s: V4L2_CID_SHARPNESS\n", __func__);
+		err = s5k4ea_write_regs(sd, \
+			s5k4ea_regs_sharpness_bias[ctrl->value]);
+		break;
+	default:
+		dev_err(&client->dev, "%s: no such control\n", __func__);
+		break;
+	}
+
+	if (err < 0)
+		goto out;
+	else
+		return 0;
+
+out:
+	dev_dbg(&client->dev, "%s: vidioc_s_ctrl failed\n", __func__);
+	return err;
+#else
+	return 0;
+#endif
+}
+
+int
+__s5k4ea_init_4bytes(struct v4l2_subdev *sd, unsigned char *reg[], int total)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+	unsigned char *item;
+
+	for (i = 0; i < total; i++) {
+		item = (unsigned char *) &reg[i];
+		if (item[0] == REG_DELAY) {
+			mdelay(item[1]);
+			err = 0;
+		} else {
+			err = s5k4ea_i2c_write(sd, item, 4);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	return err;
+}
+
+static int
+__s5k4ea_init_2bytes(struct v4l2_subdev *sd, unsigned short *reg[], int total)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+	unsigned short *item;
+
+	for (i = 0; i < total; i++) {
+		item = (unsigned short *) &reg[i];
+		if (item[0] == REG_DELAY) {
+			mdelay(item[1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, item[0], item[1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", \
+			__func__);
+	}
+
+	return err;
+}
+
+static int s5k4ea_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+
+	v4l_info(client, "%s: camera initialization start\n", __func__);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg1, S5K4EA_INIT_REGS1);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg2, S5K4EA_INIT_REGS2);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg3, S5K4EA_INIT_REGS3);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg4, S5K4EA_INIT_REGS4);
+
+	if (val == 1)
+		err = __s5k4ea_init_4bytes(sd, \
+			(unsigned char **) s5k4ea_init_jpeg, S5K4EA_INIT_JPEG);
+	else
+		err = __s5k4ea_init_4bytes(sd, \
+			(unsigned char **) s5k4ea_init_reg5, S5K4EA_INIT_REGS5);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg6, S5K4EA_INIT_REGS6);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg7, S5K4EA_INIT_REGS7);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg8, S5K4EA_INIT_REGS8);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg9, S5K4EA_INIT_REGS9);
+
+	err = __s5k4ea_init_2bytes(sd, \
+		(unsigned short **) s5k4ea_init_reg10, S5K4EA_INIT_REGS10);
+
+	err = __s5k4ea_init_4bytes(sd, \
+		(unsigned char **) s5k4ea_init_reg11, S5K4EA_INIT_REGS11);
+
+	if (err < 0) {
+		v4l_err(client, "%s: camera initialization failed\n", \
+			__func__);
+		return -EIO;	/* FIXME */
+	}
+
+	return 0;
+}
+
+static int s5k4ea_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k4ea_state *state = to_state(sd);
+	struct s5k4ea_mbus_platform_data *pdata = state->pdata;
+	int ret;
+
+	/* bug report */
+	BUG_ON(!pdata);
+	if(pdata->set_clock) {
+		ret = pdata->set_clock(&client->dev, on);
+		if(ret)
+			return -EIO;
+	}
+
+	/* setting power */
+	if(pdata->set_power) {
+		ret = pdata->set_power(on);
+		if(ret)
+			return -EIO;
+		if(on)
+			return s5k4ea_init(sd, 0);
+	}
+
+	return 0;
+}
+
+static int s5k4ea_sleep(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: sleep mode\n", __func__);
+
+	for (i = 0; i < S5K4EA_SLEEP_REGS; i++) {
+		if (s5k4ea_sleep_reg[i][0] == REG_DELAY) {
+			mdelay(s5k4ea_sleep_reg[i][1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, s5k4ea_sleep_reg[i][0], \
+				s5k4ea_sleep_reg[i][1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", __func__);
+	}
+
+	if (err < 0) {
+		v4l_err(client, "%s: sleep failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k4ea_wakeup(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL, i;
+
+	v4l_info(client, "%s: wakeup mode\n", __func__);
+
+	for (i = 0; i < S5K4EA_WAKEUP_REGS; i++) {
+		if (s5k4ea_wakeup_reg[i][0] == REG_DELAY) {
+			mdelay(s5k4ea_wakeup_reg[i][1]);
+			err = 0;
+		} else {
+			err = s5k4ea_write(sd, s5k4ea_wakeup_reg[i][0], \
+				s5k4ea_wakeup_reg[i][1]);
+		}
+
+		if (err < 0)
+			v4l_info(client, "%s: register set failed\n", __func__);
+	}
+
+	if (err < 0) {
+		v4l_err(client, "%s: wake up failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k4ea_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	return enable ? s5k4ea_wakeup(sd) : s5k4ea_sleep(sd);
+}
+
+static const struct v4l2_subdev_core_ops s5k4ea_core_ops = {
+	.init = s5k4ea_init,	/* initializing API */
+	.s_power = s5k4ea_s_power,
+	.queryctrl = s5k4ea_queryctrl,
+	.querymenu = s5k4ea_querymenu,
+	.g_ctrl = s5k4ea_g_ctrl,
+	.s_ctrl = s5k4ea_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k4ea_video_ops = {
+	.s_crystal_freq = s5k4ea_s_crystal_freq,
+	.g_mbus_fmt = s5k4ea_g_fmt,
+	.s_mbus_fmt = s5k4ea_s_fmt,
+	.enum_framesizes = s5k4ea_enum_framesizes,
+	.enum_frameintervals = s5k4ea_enum_frameintervals,
+	.g_parm = s5k4ea_g_parm,
+	.s_parm = s5k4ea_s_parm,
+	.s_stream = s5k4ea_s_stream,
+};
+
+static const struct v4l2_subdev_ops s5k4ea_ops = {
+	.core = &s5k4ea_core_ops,
+	.video = &s5k4ea_video_ops,
+};
+
+/*
+ * s5k4ea_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k4ea_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct s5k4ea_state *state;
+	struct v4l2_subdev *sd;
+	struct s5k4ea_mbus_platform_data *pdata = client->dev.platform_data;
+
+	if (!pdata) {
+		dev_err( &client->dev, "null platform data");
+		return -EIO;
+	}
+
+	state = kzalloc(sizeof(struct s5k4ea_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K4EA_DRIVER_NAME);
+	state->pdata = client->dev.platform_data;
+
+	/* set default data from sensor specific value */
+	state->fmt.width = pdata->fmt.width;
+	state->fmt.height = pdata->fmt.height;
+	state->fmt.code = pdata->fmt.code;
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k4ea_ops);
+
+	/* needed for acquiring subdevice by this module name */
+	snprintf(sd->name, sizeof(sd->name), S5K4EA_DRIVER_NAME);
+
+	dev_info(&client->dev, "id: %d, fmt.code: %d, res: res: %d x %d",
+	    pdata->id, pdata->fmt.code,
+	    pdata->fmt.width, pdata->fmt.height);
+	dev_info(&client->dev, "s5k4ea has been probed\n");
+
+	return 0;
+}
+
+
+static int s5k4ea_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+	return 0;
+}
+
+static const struct i2c_device_id s5k4ea_id[] = {
+	{ S5K4EA_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k4ea_id);
+
+static struct i2c_driver s5k4ea_i2c_driver = {
+	.driver = {
+		.name	= S5K4EA_DRIVER_NAME,
+	},
+	.probe		= s5k4ea_probe,
+	.remove		= s5k4ea_remove,
+	.id_table	= s5k4ea_id,
+};
+
+static int __init s5k4ea_mod_init(void)
+{
+	return i2c_add_driver(&s5k4ea_i2c_driver);
+}
+
+static void __exit s5k4ea_mod_exit(void)
+{
+	i2c_del_driver(&s5k4ea_i2c_driver);
+}
+module_init(s5k4ea_mod_init);
+module_exit(s5k4ea_mod_exit);
+
+MODULE_DESCRIPTION("Samsung Electronics S5K4EA SXGA camera driver");
+MODULE_AUTHOR("Dongsoo Nathaniel Kim<dongsoo45.kim@samsung.com>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/video/s5k5bafx-v2.c b/drivers/media/video/s5k5bafx-v2.c
new file mode 100644
index 0000000..24b0ef1
--- /dev/null
+++ b/drivers/media/video/s5k5bafx-v2.c
@@ -0,0 +1,1598 @@
+/*
+ * Driver for S5K5BAFX from Samsung Electronics
+ *
+ * 1/6" 2Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+#include <media/s5k5bafx_platform.h>
+#include "s5k5bafx-v2.h"
+#ifdef CONFIG_CPU_FREQ
+#include <mach/cpufreq.h>
+#endif
+#ifdef S5K5BAFX_USLEEP
+#include <linux/hrtimer.h>
+#endif
+
+static const struct s5k5bafx_fps s5k5bafx_framerates[] = {
+	{ I_FPS_0,	FRAME_RATE_AUTO },
+	{ I_FPS_7,	FRAME_RATE_7 },
+	{ I_FPS_10,	10 },
+	{ I_FPS_12,	12 },
+	{ I_FPS_15,	FRAME_RATE_15 },
+	{ I_FPS_25,	FRAME_RATE_25 },
+};
+
+static const struct s5k5bafx_regs reg_datas = {
+	.ev = {
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_MINUS_4), s5k5bafx_bright_m4),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_MINUS_3), s5k5bafx_bright_m3),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_MINUS_2), s5k5bafx_bright_m2),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_MINUS_1), s5k5bafx_bright_m1),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_DEFAULT),
+						s5k5bafx_bright_default),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_PLUS_1), s5k5bafx_bright_p1),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_PLUS_2), s5k5bafx_bright_p2),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_PLUS_3), s5k5bafx_bright_p3),
+		S5K5BAFX_REGSET(GET_EV_INDEX(EV_PLUS_4), s5k5bafx_bright_p4),
+	},
+	.blur = {
+		S5K5BAFX_REGSET(BLUR_LEVEL_0, s5k5bafx_vt_pretty_default),
+		S5K5BAFX_REGSET(BLUR_LEVEL_1, s5k5bafx_vt_pretty_1),
+		S5K5BAFX_REGSET(BLUR_LEVEL_2, s5k5bafx_vt_pretty_2),
+		S5K5BAFX_REGSET(BLUR_LEVEL_3, s5k5bafx_vt_pretty_3),
+	},
+	.fps = {
+		S5K5BAFX_REGSET(I_FPS_0, s5k5bafx_fps_auto),
+		S5K5BAFX_REGSET(I_FPS_7, s5k5bafx_fps_7fix),
+		S5K5BAFX_REGSET(I_FPS_10, s5k5bafx_fps_10fix),
+		S5K5BAFX_REGSET(I_FPS_12, s5k5bafx_fps_12fix),
+		S5K5BAFX_REGSET(I_FPS_15, s5k5bafx_fps_15fix),
+		S5K5BAFX_REGSET(I_FPS_25, s5k5bafx_fps_25fix),
+	},
+	.preview_start = S5K5BAFX_REGSET_TABLE(s5k5bafx_preview),
+	.capture_start = S5K5BAFX_REGSET_TABLE(s5k5bafx_capture),
+	.init = S5K5BAFX_REGSET_TABLE(s5k5bafx_common),
+	.init_vt = S5K5BAFX_REGSET_TABLE(s5k5bafx_vt_common),
+	.init_vt_wifi = S5K5BAFX_REGSET_TABLE(s5k5bafx_vt_wifi_common),
+#if defined(CONFIG_TARGET_LOCALE_KOR) || \
+	defined(CONFIG_TARGET_LOCALE_NAATT) || \
+	defined(CONFIG_MACH_P8LTE)
+	.init_recording = S5K5BAFX_REGSET_TABLE(s5k5bafx_recording_60Hz_common),
+#else
+	.init_recording = S5K5BAFX_REGSET_TABLE(s5k5bafx_recording_50Hz_common),
+#endif
+	.stream_stop = S5K5BAFX_REGSET_TABLE(s5k5bafx_stream_stop),
+	.dtp_on = S5K5BAFX_REGSET_TABLE(s5k5bafx_pattern_on),
+	.dtp_off = S5K5BAFX_REGSET_TABLE(s5k5bafx_pattern_off),
+};
+
+/**
+ * Use msleep() if the sleep time is over 1000 us.
+ */
+static void __used s5k5bafx_usleep(u32 usecs)
+{
+	ktime_t expires;
+	u64 add_time = (u64)usecs * 1000;
+
+	if (unlikely(!usecs))
+		return;
+
+	expires = ktime_add_ns(ktime_get(), add_time);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_hrtimeout(&expires, HRTIMER_MODE_ABS);
+}
+
+static inline int s5k5bafx_read(struct i2c_client *client,
+	u16 subaddr, u16 *data)
+{
+	u8 buf[2] = {0,};
+	int err = -EIO;
+	struct i2c_msg msg = {
+		.addr = client->addr,
+		.flags = 0,
+		.len = 2,
+		.buf = buf,
+	};
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	*(u16 *)buf = cpu_to_be16(subaddr);
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	CHECK_ERR_MSG(err, "%d register wite fail\n", __LINE__);
+
+	msg.flags = I2C_M_RD;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	CHECK_ERR_MSG(err, "%d register read fail\n", __LINE__);
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return 0;
+}
+
+/*
+ * s5k6aafx sensor i2c write routine
+ * <start>--<Device address><2Byte Subaddr><2Byte Value>--<stop>
+ */
+#ifdef CONFIG_LOAD_FILE
+static int loadFile(void)
+{
+	struct file *fp = NULL;
+	struct test *nextBuf = NULL;
+
+	u8 *nBuf = NULL;
+	size_t file_size = 0, max_size = 0, testBuf_size = 0;
+	ssize_t nread = 0;
+	s32 check = 0, starCheck = 0;
+	s32 tmp_large_file = 0;
+	s32 i = 0;
+	int ret = 0;
+	loff_t pos;
+
+	mm_segment_t fs = get_fs();
+	set_fs(get_ds());
+
+	cam_info("%s: E\n", __func__);
+
+	BUG_ON(testBuf);
+
+	fp = filp_open(TUNING_FILE_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("%s: ERROR, file open error\n", __func__);
+		return PTR_ERR(fp);
+	}
+
+	file_size = (size_t) fp->f_path.dentry->d_inode->i_size;
+	max_size = file_size;
+
+	cam_dbg("file_size = %d\n", file_size);
+
+	nBuf = kmalloc(file_size, GFP_ATOMIC);
+	if (nBuf == NULL) {
+		cam_dbg("Fail to 1st get memory\n");
+		nBuf = vmalloc(file_size);
+		if (nBuf == NULL) {
+			cam_err("%s: ERROR, nBuf Out of Memory\n", __func__);
+			ret = -ENOMEM;
+			goto error_out;
+		}
+		tmp_large_file = 1;
+	}
+
+	testBuf_size = sizeof(struct test) * file_size;
+	if (tmp_large_file) {
+		testBuf = (struct test *)vmalloc(testBuf_size);
+		large_file = 1;
+	} else {
+		testBuf = kmalloc(testBuf_size, GFP_ATOMIC);
+		if (testBuf == NULL) {
+			cam_dbg("Fail to get mem(%d bytes)\n", testBuf_size);
+			testBuf = (struct test *)vmalloc(testBuf_size);
+			large_file = 1;
+		}
+	}
+	if (testBuf == NULL) {
+		cam_err("%s: ERROR, Out of Memory\n", __func__);
+		ret = -ENOMEM;
+		goto error_out;
+	}
+
+	pos = 0;
+	memset(nBuf, 0, file_size);
+	memset(testBuf, 0, file_size * sizeof(struct test));
+
+	nread = vfs_read(fp, (char __user *)nBuf, file_size, &pos);
+	if (nread != file_size) {
+		cam_err("%s: ERROR, failed to read file ret = %d\n",
+						__func__, nread);
+		ret = -1;
+		goto error_out;
+	}
+
+	set_fs(fs);
+
+	i = max_size;
+
+	printk("i = %d\n", i);
+
+	while (i) {
+		testBuf[max_size - i].data = *nBuf;
+		if (i != 1) {
+			testBuf[max_size - i].nextBuf = &testBuf[max_size - i + 1];
+		} else {
+			testBuf[max_size - i].nextBuf = NULL;
+			break;
+		}
+		i--;
+		nBuf++;
+	}
+
+	i = max_size;
+	nextBuf = &testBuf[0];
+
+#if 1
+	while (i - 1) {
+		if (!check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+								== '/') {
+						check = 1;/* when find '//' */
+						i--;
+					} else if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1;/* when find '/ *' */
+						i--;
+					}
+				} else
+					break;
+			}
+			if (!check && !starCheck) {
+				/* ignore '\t' */
+				if (testBuf[max_size - i].data != '\t') {
+					nextBuf->nextBuf = &testBuf[max_size-i];
+					nextBuf = &testBuf[max_size - i];
+				}
+			}
+		} else if (check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if(testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1; /* when find '/ *' */
+						check = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+
+			 /* when find '\n' */
+			if (testBuf[max_size - i].data == '\n' && check) {
+				check = 0;
+				nextBuf->nextBuf = &testBuf[max_size - i];
+				nextBuf = &testBuf[max_size - i];
+			}
+
+		} else if (!check && starCheck) {
+			if (testBuf[max_size - i].data == '*') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '/') {
+						starCheck = 0; /* when find '* /' */
+						i--;
+					}
+				} else
+					break;
+			}
+		}
+
+		i--;
+
+		if (i < 2) {
+			nextBuf = NULL;
+			break;
+		}
+
+		if (testBuf[max_size - i].nextBuf == NULL) {
+			nextBuf = NULL;
+			break;
+		}
+	}
+#endif
+
+#if 0 // for print
+	printk("i = %d\n", i);
+	nextBuf = &testBuf[0];
+	while (1) {
+		//printk("sdfdsf\n");
+		if (nextBuf->nextBuf == NULL)
+			break;
+		printk("%c", nextBuf->data);
+		nextBuf = nextBuf->nextBuf;
+	}
+#endif
+
+error_out:
+
+	if (nBuf)
+		tmp_large_file ? vfree(nBuf) : kfree(nBuf);
+	if (fp)
+		filp_close(fp, current->files);
+	return ret;
+}
+#endif
+
+static inline int s5k5bafx_write(struct i2c_client *client,
+		u32 packet)
+{
+	u8 buf[4];
+	int err = 0, retry_count = 5;
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.buf	= buf,
+		.len	= 4,
+	};
+
+	CHECK_ERR_COND_MSG(!client->adapter, -ENODEV,
+			"can't search i2c client adapter\n");
+
+	while (retry_count--) {
+		*(u32 *)buf = cpu_to_be32(packet);
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(err == 1))
+			break;
+		mdelay(10);
+	}
+	CHECK_ERR_MSG(err, "0x%08x write failed err=%d\n",
+					(u32)packet, err)
+	return 0;
+}
+
+#ifdef CONFIG_LOAD_FILE
+/* #define DEBUG_LOAD_FILE */
+static int s5k5bafx_write_regs_from_sd(struct v4l2_subdev *sd, u8 s_name[])
+{
+
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct test *tempData = NULL;
+
+	int ret = -EAGAIN;
+	u32 temp;
+	u32 delay = 0;
+	u8 data[11];
+	s32 searched = 0;
+	size_t size = strlen(s_name);
+	s32 i;
+#ifdef DEBUG_LOAD_FILE
+	u8 regs_name[128] = {0,};
+
+	BUG_ON(size > sizeof(regs_name));
+#endif
+
+	cam_dbg("E size = %d, string = %s\n", size, s_name);
+	tempData = &testBuf[0];
+	while (!searched) {
+		searched = 1;
+		for (i = 0; i < size; i++) {
+			if (tempData->data != s_name[i]) {
+				searched = 0;
+				break;
+			}
+#ifdef DEBUG_LOAD_FILE
+			regs_name[i] = tempData->data;
+#endif
+
+			tempData = tempData->nextBuf;
+		}
+#ifdef DEBUG_LOAD_FILE
+		if (i > 9) {
+			regs_name[i] = '\0';
+			cam_dbg("Searching: regs_name = %s\n", regs_name);
+		}
+#endif
+
+		tempData = tempData->nextBuf;
+	}
+	/* structure is get..*/
+#ifdef DEBUG_LOAD_FILE
+	regs_name[i] = '\0';
+	cam_dbg("Searched regs_name = %s\n\n", regs_name);
+#endif
+
+	while (1) {
+		if (tempData->data == '{')
+			break;
+		else
+			tempData = tempData->nextBuf;
+	}
+
+	while (1) {
+		searched = 0;
+		while (1) {
+			if (tempData->data == 'x') {
+				/* get 10 strings.*/
+				data[0] = '0';
+				for (i = 1; i < 11; i++) {
+					data[i] = tempData->data;
+					tempData = tempData->nextBuf;
+				}
+				/*cam_dbg("%s\n", data);*/
+				temp = simple_strtoul(data, NULL, 16);
+				break;
+			} else if (tempData->data == '}') {
+				searched = 1;
+				break;
+			} else
+				tempData = tempData->nextBuf;
+
+			if (tempData->nextBuf == NULL)
+				return -1;
+		}
+
+		if (searched)
+			break;
+
+		if ((temp & S5K5BAFX_DELAY) == S5K5BAFX_DELAY) {
+			delay = temp & 0xFFFF;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+		ret = s5k5bafx_write(client, temp);
+
+		/* In error circumstances */
+		/* Give second shot */
+		if (unlikely(ret)) {
+			dev_info(&client->dev,
+					"s5k5bafx i2c retry one more time\n");
+			ret = s5k5bafx_write(client, temp);
+
+			/* Give it one more shot */
+			if (unlikely(ret)) {
+				dev_info(&client->dev,
+						"s5k5bafx i2c retry twice\n");
+				ret = s5k5bafx_write(client, temp);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+/*
+* Read a register.
+*/
+static int s5k5bafx_read_reg(struct v4l2_subdev *sd,
+		u16 page, u16 addr, u16 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u32 page_cmd = (0x002C << 16) | page;
+	u32 addr_cmd = (0x002E << 16) | addr;
+	int err = -EIO;
+
+	/* cam_trace("page_cmd=0x%X, addr_cmd=0x%X\n", page_cmd, addr_cmd); */
+
+	err = s5k5bafx_write(client, page_cmd);
+	CHECK_ERR(err);
+	err = s5k5bafx_write(client, addr_cmd);
+	err = s5k5bafx_read(client, 0x0F12, val);
+
+	return 0;
+}
+
+/* program multiple registers */
+static int s5k5bafx_write_regs(struct v4l2_subdev *sd,
+		const u32 *packet, u32 num)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int ret = -EAGAIN,  retry_count = 5;
+	u32 temp = 0;
+	u16 delay = 0;
+#ifdef S5K5BAFX_BURST_MODE
+	u16 addr, value;
+	int len = 0;
+	u8 *buf = state->burst_buf;
+#else
+	u8 buf[4] = {0,};
+#endif
+	struct i2c_msg msg = {
+		msg.addr = client->addr,
+		msg.flags = 0,
+		msg.len = 4,
+		msg.buf = buf,
+	};
+
+	CHECK_ERR_COND_MSG(!client->adapter, -ENODEV,
+			"can't search i2c client adapter\n");
+
+	while (num--) {
+		temp = *packet++;
+
+		if ((temp & S5K5BAFX_DELAY) == S5K5BAFX_DELAY) {
+			delay = temp & 0xFFFF;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+#ifdef S5K5BAFX_BURST_MODE
+		addr = temp >> 16;
+		value = temp & 0xFFFF;
+
+		/* cam_dbg("I2C writes: 0x%04X, 0x%04X\n", addr, value); */
+
+		switch (addr) {
+		case 0x0F12:
+			if (len == 0) {
+				buf[len++] = addr >> 8;
+				buf[len++] = addr & 0xFF;
+			}
+			buf[len++] = value >> 8;
+			buf[len++] = value & 0xFF;
+
+			if ((*packet >> 16) != addr) {
+				msg.len = len;
+				goto s5k5bafx_burst_write;
+			}
+			break;
+
+		case 0xFFFF:
+			break;
+
+		default:
+			msg.len = 4;
+			*(u32 *)buf = cpu_to_be32(temp);
+			goto s5k5bafx_burst_write;
+		}
+
+		continue;
+#else
+		*(u32 *)buf = cpu_to_be32(temp);
+#endif
+
+#ifdef S5K5BAFX_BURST_MODE
+s5k5bafx_burst_write:
+		len = 0;
+#endif
+		retry_count = 5;
+
+		while (retry_count--) {
+			ret = i2c_transfer(client->adapter, &msg, 1);
+			if (likely(ret == 1))
+				break;
+			mdelay(10);
+		}
+
+		if (unlikely(ret < 0)) {
+			cam_err("%s: ERROR, 0x%08x write failed err=%d\n",
+						__func__, (u32)packet, ret);
+			break;
+		}
+
+#ifdef S5K5BAFX_USLEEP
+		if (unlikely(state->vt_mode))
+			if (!(num%200))
+				s5k5bafx_usleep(3);
+#endif		
+	}
+
+	CHECK_ERR_COND_MSG(ret < 0, -EIO,
+		"fail to write registers. err=%d!!\n", ret);
+
+	return 0;
+}
+
+static int s5k5bafx_set_from_table(struct v4l2_subdev *sd,
+				const char *setting_name,
+				const struct s5k5bafx_regset_table *table,
+				int table_size, int index)
+{
+	int err = 0;
+
+	cam_dbg("%s: set %s index %d\n",
+		__func__, setting_name, index);
+	CHECK_ERR_COND_MSG(((index < 0) || (index >= table_size)),
+		-EINVAL, "index(%d) out of range[0:%d] for table for %s\n",
+		index, table_size, setting_name);
+
+	table += index;
+	CHECK_ERR_COND_MSG(!table->reg, -EFAULT, "reg = NULL\n");
+
+#ifdef CONFIG_LOAD_FILE
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__, setting_name,
+						table->name);
+	return s5k5bafx_write_regs_from_sd(sd, table->name);
+#else
+	err = s5k5bafx_write_regs(sd, table->reg, table->array_size);
+	CHECK_ERR_COND_MSG(err < 0, -EIO, "fail to write regs(%s), err=%d\n",
+			setting_name, err);
+
+	return 0;
+#endif
+}
+
+static inline int s5k5bafx_get_iso(struct v4l2_subdev *sd, u16 *iso)
+{
+	u16 iso_gain_table[] = {10, 18, 23, 28};
+	u16 iso_table[] = {0, 50, 100, 200, 400};
+	u16 val = 0, gain = 0;
+	int i = 0;
+
+	s5k5bafx_read_reg(sd, REG_PAGE_ISO, REG_ADDR_ISO, &val);
+	cam_dbg("val = %d\n", val);
+	gain = val * 10 / 256;
+	for (i = 0; i < ARRAY_SIZE(iso_gain_table); i++) {
+		if (gain < iso_gain_table[i])
+			break;
+	}
+
+	*iso = iso_table[i];
+
+	cam_dbg("gain=%d, ISO=%d\n", gain, *iso);
+
+	return 0;
+}
+
+static inline int  s5k5bafx_get_expousretime(struct v4l2_subdev *sd,
+						u32 *exp_time)
+{
+	u16 val = 0;
+
+	s5k5bafx_read_reg(sd, REG_PAGE_SHUTTER, REG_ADDR_SHUTTER, &val);
+	*exp_time = val * 1000 / 500;
+
+	return 0;
+}
+
+static int s5k5bafx_get_exif(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	u32 exposure_time = 0;
+
+	state->exif.exp_time_den = 0;
+	state->exif.iso = 0;
+
+	/* Get exposure-time */
+	s5k5bafx_get_expousretime(sd, &exposure_time);
+	state->exif.exp_time_den = 1000 * 1000 / exposure_time;
+	cam_dbg("real exposure time=%dms\n", exposure_time / 1000);
+
+	/* Get ISO */
+	s5k5bafx_get_iso(sd, &state->exif.iso);
+
+	cam_dbg("%s: exp_time_den=%d, ISO=%d\n",
+		__func__, state->exif.exp_time_den, state->exif.iso);
+
+	return 0;
+}
+
+#ifdef SUPPORT_FACTORY_TEST
+static int s5k5bafx_check_dataline(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EIO;
+
+	cam_info("DTP %s\n", val ? "ON" : "OFF");
+
+	if (val)
+		err = s5k5bafx_set_from_table(sd, "dtp_on",
+				&state->regs->dtp_on, 1, 0);
+	else
+		err = s5k5bafx_set_from_table(sd, "dtp_off",
+				&state->regs->dtp_off, 1, 0);
+
+	CHECK_ERR_MSG(err, "fail to DTP setting\n");
+	return 0;
+}
+#endif
+
+static int s5k5bafx_debug_sensor_status(struct v4l2_subdev *sd)
+{
+	u16 val = 0;
+	int err = -EINVAL;
+
+	/* Read Mon_DBG_Counters_2 */
+	/*err = s5k5bafx_read_reg(sd, 0x7000, 0x0402, &val);
+	CHECK_ERR(err);
+	cam_info("counter = %d\n", val); */
+
+	/* Read REG_TC_GP_EnableCaptureChanged. */
+	err = s5k5bafx_read_reg(sd, 0x7000, 0x01F6, &val);
+	CHECK_ERR(err);
+	
+	switch(val) {
+	case 0:
+		cam_info("In normal mode(0)\n");
+		break;
+	case 1:
+		cam_info("In swiching to capture mode(1).....\n");
+		break;
+	default:
+		cam_err("%s: ERROR, In Unknown mode(?)\n", __func__);
+		break;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_check_sensor_status(struct v4l2_subdev *sd)
+{
+	/*struct i2c_client *client = v4l2_get_subdevdata(sd);*/
+	u16 val_1 = 0, val_2 = 0;
+	int err = -EINVAL;
+
+	err = s5k5bafx_read_reg(sd, 0x7000, 0x0132, &val_1);
+	CHECK_ERR(err);
+	err = s5k5bafx_read_reg(sd, 0xD000, 0x1002, &val_2);
+	CHECK_ERR(err);
+
+	cam_dbg("read val1=0x%x, val2=0x%x\n", val_1, val_2);
+
+	if ((val_1 != 0xAAAA) || (val_2 != 0))
+		goto error_occur;
+
+	cam_info("Check ESD: not detected\n\n");
+	return 0;
+
+error_occur:
+	cam_err("Check ESD: ERROR, ESD Shock detected!\n\n");
+	return -ERESTART;
+}
+
+static inline int s5k5bafx_check_esd(struct v4l2_subdev *sd)
+{
+	int err = -EINVAL;
+
+	err = s5k5bafx_check_sensor_status(sd);
+	CHECK_ERR(err);
+
+	return 0;	
+}
+
+static int s5k5bafx_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_preview_start\n");
+
+	err = s5k5bafx_set_from_table(sd, "preview_start",
+			&state->regs->preview_start, 1, 0);
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		err = s5k5bafx_check_dataline(sd, 1);
+#endif
+	CHECK_ERR_MSG(err, "fail to make preview\n")
+
+	return 0;
+}
+
+static int s5k5bafx_set_capture_start(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_capture_start\n");
+
+	err = s5k5bafx_set_from_table(sd, "capture_start",
+				&state->regs->capture_start, 1, 0);
+	CHECK_ERR_MSG(err, "failed to make capture\n");
+
+	s5k5bafx_get_exif(sd);
+
+	return err;
+}
+
+static int s5k5bafx_set_sensor_mode(struct v4l2_subdev *sd,
+					s32 val)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+
+	switch (val) {
+	case SENSOR_MOVIE:
+		if (state->vt_mode) {
+			state->sensor_mode = SENSOR_CAMERA;
+			cam_warn("%s: WARNING, Not support movie in vt mode\n",
+							__func__);
+			break;
+		}
+		/* We do not break. */
+	case SENSOR_CAMERA:
+		state->sensor_mode = val;
+		break;
+	default:
+		CHECK_ERR_COND_MSG(true, -EINVAL,
+			"Not support mode.(%d)\n", val);
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_init_regs(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	const u32 write_reg = 0x00287000;
+	u16 read_value = 0;
+	int err = -ENODEV;
+
+	/* enter read mode */
+	err = s5k5bafx_read_reg(sd, 0xD000, 0x1006, &read_value);
+	if (unlikely(err < 0))
+		return -ENODEV;
+
+	if (likely(read_value == S5K5BAFX_CHIP_ID))
+		cam_info("Sensor ChipID: 0x%04X\n", S5K5BAFX_CHIP_ID);
+	else
+		cam_info("Sensor ChipID: 0x%04X, unknown ChipID\n", read_value);
+
+	err = s5k5bafx_read_reg(sd, 0xD000, 0x1008, &read_value);
+	if (likely((u8)read_value == S5K5BAFX_CHIP_REV))
+		cam_info("Sensor revision: 0x%02X\n", S5K5BAFX_CHIP_REV);
+	else
+		cam_info("Sensor revision: 0x%02X, unknown revision\n",
+				(u8)read_value);
+
+	/* restore write mode */
+	err = s5k5bafx_write_regs(sd, &write_reg, 1);
+	CHECK_ERR_COND(err < 0, -ENODEV);
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+
+#ifdef NEW_CAM_DRV
+static int s5k5bafx_g_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int s5k5bafx_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	cam_trace("E\n");
+	return 0;
+}
+
+static int s5k5bafx_enum_framesizes(struct v4l2_subdev *sd, \
+					struct v4l2_frmsizeenum *fsize)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	/*
+	 * Return the actual output settings programmed to the camera
+	 */
+	if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		fsize->discrete.width = state->capture_frmsizes.width;
+		fsize->discrete.height = state->capture_frmsizes.height;
+	} else {
+		fsize->discrete.width = state->preview_frmsizes.width;
+		fsize->discrete.height = state->preview_frmsizes.height;
+	}
+
+	cam_info("enum_framesizes: width - %d , height - %d\n",
+		fsize->discrete.width, fsize->discrete.height);
+
+	return 0;
+}
+
+#if (0) /* not used */
+static int s5k5bafx_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmtdesc)
+{
+	int err = 0;
+
+	FUNC_ENTR();
+	return err;
+}
+
+static int s5k5bafx_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	FUNC_ENTR();
+	return err;
+}
+#endif
+
+#ifdef NEW_CAM_DRV
+static int s5k5bafx_try_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int s5k5bafx_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	return err;
+}
+
+#ifdef NEW_CAM_DRV
+static int s5k5bafx_s_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+#else
+static int s5k5bafx_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	u32 *width = NULL, *height = NULL;
+
+	cam_trace("E\n");
+	/*
+	 * Just copying the requested format as of now.
+	 * We need to check here what are the formats the camera support, and
+	 * set the most appropriate one according to the request from FIMC
+	 */
+#ifdef NEW_CAM_DRV
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	state->req_fmt.priv = fmt->field;
+#else
+	memcpy(&state->req_fmt, &fmt->fmt.pix, sizeof(fmt->fmt.pix));
+#endif
+
+	switch (state->req_fmt.priv) {
+	case V4L2_PIX_FMT_MODE_PREVIEW:
+		width = &state->preview_frmsizes.width;
+		height = &state->preview_frmsizes.height;
+		break;
+
+	case V4L2_PIX_FMT_MODE_CAPTURE:
+		width = &state->capture_frmsizes.width;
+		height = &state->capture_frmsizes.height;
+		break;
+
+	default:
+		cam_err("%s: ERROR, inavlid FMT Mode(%d)\n",
+						__func__, state->req_fmt.priv);
+		return -EINVAL;
+	}
+
+	if ((*width != state->req_fmt.width) ||
+		(*height != state->req_fmt.height)) {
+		cam_err("%s: ERROR, Invalid size. width= %d, height= %d\n",
+			__func__, state->req_fmt.width, state->req_fmt.height);
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_set_frame_rate(struct v4l2_subdev *sd, u32 fps)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EIO;
+	int i = 0, fps_index = -1;
+
+	cam_info("set frame rate %d\n", fps);
+
+	for (i = 0; i < ARRAY_SIZE(s5k5bafx_framerates); i++) {
+		if (fps == s5k5bafx_framerates[i].fps) {
+			fps_index = s5k5bafx_framerates[i].index;
+			state->fps = fps;
+			state->req_fps = -1;
+			break;
+		}
+	}
+
+	if (unlikely(fps_index < 0)) {
+		cam_err("%s: WARNING, Not supported FPS(%d)\n", __func__, fps);
+		return 0;
+	}
+
+	if (state->sensor_mode != SENSOR_MOVIE) {
+		err = s5k5bafx_set_from_table(sd, "fps", state->regs->fps,
+			ARRAY_SIZE(state->regs->fps), fps_index);
+		CHECK_ERR_MSG(err, "fail to set framerate\n")
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	return err;
+}
+
+static int s5k5bafx_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+	struct s5k5bafx_state *state = to_state(sd);
+
+	state->req_fps = parms->parm.capture.timeperframe.denominator /
+			parms->parm.capture.timeperframe.numerator;
+
+	cam_dbg("s_parm fps=%d, req_fps=%d\n", state->fps, state->req_fps);
+
+	if ((state->req_fps < 0) && (state->req_fps > 15)) {
+		cam_err("%s: ERROR, invalid frame rate %d. we'll set to %d\n",
+			__func__, state->req_fps, DEFAULT_FPS);
+		state->req_fps = DEFAULT_FPS;
+	}
+
+	if (state->initialized) {
+		err = s5k5bafx_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+#if (0) /* not used */
+static int s5k5bafx_set_60hz_antibanding(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	FUNC_ENTR();
+
+	u32 s5k5bafx_antibanding60hz[] = {
+	0xFCFCD000,
+	0x00287000,
+	// Anti-Flicker //
+	// End user init script
+	0x002A0400,
+	0x0F12005F,  //REG_TC_DBG_AutoAlgEnBits //Auto Anti-Flicker is enabled bit[5] = 1.
+	0x002A03DC,
+	0x0F120002,  //02 REG_SF_USER_FlickerQuant //Set flicker quantization(0: no AFC, 1: 50Hz, 2: 60 Hz)
+	0x0F120001,
+	};
+
+	err = s5k5bafx_write_regs(sd, s5k5bafx_antibanding60hz,
+				       	sizeof(s5k5bafx_antibanding60hz) / sizeof(s5k5bafx_antibanding60hz[0]));
+	printk("%s:  setting 60hz antibanding \n", __func__);
+	if (unlikely(err))
+	{
+		printk("%s: failed to set 60hz antibanding \n", __func__);
+		return err;
+	}
+
+	return 0;
+}
+#endif
+
+static int s5k5bafx_wait_steamoff(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	struct s5k5bafx_stream_time *stream_time = &state->stream_time;
+	s32 elapsed_msec = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(!(state->pdata->is_mipi & state->need_wait_streamoff)))
+		return 0;
+
+	do_gettimeofday(&stream_time->curr_time);
+
+	elapsed_msec = GET_ELAPSED_TIME(stream_time->curr_time, \
+				stream_time->before_time) / 1000;
+
+	if (state->pdata->streamoff_delay > elapsed_msec) {
+		cam_info("stream-off: %dms + %dms\n", elapsed_msec,
+			state->pdata->streamoff_delay - elapsed_msec);
+		debug_msleep(sd, state->pdata->streamoff_delay - elapsed_msec);
+	} else
+		cam_info("stream-off: %dms\n", elapsed_msec);
+
+	state->need_wait_streamoff = 0;
+
+	return 0;
+}
+
+static int s5k5bafx_control_stream(struct v4l2_subdev *sd, u32 cmd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (unlikely(cmd != STREAM_STOP))
+		return 0;
+
+	cam_info("STREAM STOP!!\n");
+	err = s5k5bafx_set_from_table(sd, "stream_stop",
+			&state->regs->stream_stop, 1, 0);
+	CHECK_ERR_MSG(err, "failed to stop stream\n");
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	do_gettimeofday(&state->stream_time.before_time);
+	state->need_wait_streamoff = 1;
+#else
+	debug_msleep(sd, state->pdata->streamoff_delay);
+#endif
+	return 0;
+}
+
+static int s5k5bafx_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	err = s5k5bafx_init_regs(sd);
+	CHECK_ERR_MSG(err, "failed to indentify sensor chip\n");
+
+#if defined(CONFIG_USE_SW_I2C) && defined(CONFIG_CPU_FREQ)
+	if (state->cpufreq_lock_level == CPUFREQ_ENTRY_INVALID) {
+		err = exynos_cpufreq_get_level(1400 * 1000,
+			&state->cpufreq_lock_level);
+		CHECK_ERR_MSG(err, "failed get DVFS level\n");
+	}
+	err = exynos_cpufreq_lock(DVFS_LOCK_ID_CAM, state->cpufreq_lock_level);
+	CHECK_ERR_MSG(err, "failed lock DVFS\n");
+#endif
+	/* set initial regster value */
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			cam_info("load camera common setting\n");
+			err = s5k5bafx_set_from_table(sd, "init",
+				&state->regs->init, 1, 0);
+		} else {
+			if (state->vt_mode == 1) {
+				cam_info("load camera VT call setting\n");
+				err = s5k5bafx_set_from_table(sd, "init_vt",
+					&state->regs->init_vt, 1, 0);
+			} else {
+				cam_info("load camera WIFI VT call setting\n");
+				err = s5k5bafx_set_from_table(sd,
+					"init_vt_wifi",
+					&state->regs->init_vt_wifi, 1, 0);
+			}
+		}
+	} else {
+		cam_info("load recording setting\n");
+		err = s5k5bafx_set_from_table(sd, "init_recording",
+					&state->regs->init_recording, 1, 0);
+	}
+#if defined(CONFIG_USE_SW_I2C) && defined(CONFIG_CPU_FREQ)
+	exynos_cpufreq_lock_free(DVFS_LOCK_ID_CAM);
+#endif
+	CHECK_ERR_MSG(err, "failed to initialize camera device\n");
+
+	state->initialized = 1;
+
+	if (state->req_fps >= 0) {
+		err = s5k5bafx_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int s5k5bafx_s_config(struct v4l2_subdev *sd,
+		int irq, void *platform_data)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+#ifdef CONFIG_LOAD_FILE
+	int err = 0;
+#endif
+
+	if (!platform_data) {
+		cam_err("%s: ERROR, no platform data\n", __func__);
+		return -ENODEV;
+	}
+	state->pdata = platform_data;
+	state->dbg_level = &state->pdata->dbg_level;
+
+	state->req_fps = -1;
+	state->sensor_mode = SENSOR_CAMERA;
+#ifdef CONFIG_USE_SW_I2C
+	state->cpufreq_lock_level = CPUFREQ_ENTRY_INVALID;
+#endif
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	if (!(state->pdata->default_width && state->pdata->default_height)) {
+		state->default_frmsizes.width = DEFAULT_PREVIEW_WIDTH;
+		state->default_frmsizes.height = DEFAULT_PREVIEW_HEIGHT;
+	} else {
+		state->default_frmsizes.width = state->pdata->default_width;
+		state->default_frmsizes.height = state->pdata->default_height;
+	}
+	
+	state->preview_frmsizes.width = state->default_frmsizes.width;
+	state->preview_frmsizes.height = state->default_frmsizes.height;
+	state->capture_frmsizes.width = DEFAULT_CAPTURE_WIDTH;
+	state->capture_frmsizes.height = DEFAULT_CAPTURE_HEIGHT;
+
+	cam_dbg("Default preview_width: %d , preview_height: %d, "
+		"capture_width: %d, capture_height: %d",
+		state->preview_frmsizes.width, state->preview_frmsizes.height,
+		state->capture_frmsizes.width, state->capture_frmsizes.height);
+
+	state->req_fmt.width = state->preview_frmsizes.width;
+	state->req_fmt.height = state->preview_frmsizes.height;
+	if (!state->pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_FMT;
+	else
+		state->req_fmt.pixelformat = state->pdata->pixelformat;
+
+#ifdef CONFIG_LOAD_FILE
+	err = loadFile();
+	CHECK_ERR_MSG(err, "failed to load file ERR=%d\n", err)
+#endif
+
+	return 0;
+}
+
+#if 0
+static int s5k5bafx_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	FUNC_ENTR();
+	return 0;
+}
+
+static int s5k5bafx_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	FUNC_ENTR();
+	return 0;
+}
+#endif
+
+static int s5k5bafx_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	int err = 0;
+
+	cam_info("s_stream: mode = %d\n", enable);
+
+	BUG_ON(!state->initialized);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->sensor_mode == SENSOR_CAMERA) {
+#ifdef SUPPORT_FACTORY_TEST
+			if (state->check_dataline)
+				err = s5k5bafx_check_dataline(sd, 0);
+			else
+#endif
+				if (state->pdata->is_mipi)
+					err = s5k5bafx_control_stream(sd,
+						STREAM_STOP);
+		}
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		if ((state->sensor_mode == SENSOR_CAMERA)
+		    && (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE))
+			err = s5k5bafx_set_capture_start(sd);
+		else
+			err = s5k5bafx_set_preview_start(sd);
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_dbg("%s: do nothing(movie on)!!\n", __func__);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_dbg("%s: do nothing(movie off)!!\n", __func__);
+		break;
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	case STREAM_MODE_WAIT_OFF:
+		err = s5k5bafx_wait_steamoff(sd);
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR, Invalid stream mode %d\n",
+						__func__, enable);
+		err = -EINVAL;
+		break;
+	}
+
+	CHECK_ERR_MSG(err, "stream on(off) fail")
+
+	return 0;
+}
+
+static int s5k5bafx_set_exposure(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_exposure: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if ((val < EV_MINUS_4) || (val >= EV_MAX_V4L2)) {
+		cam_err("%s: ERROR, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = s5k5bafx_set_from_table(sd, "ev", state->regs->ev,
+		ARRAY_SIZE(state->regs->ev), GET_EV_INDEX(val));
+	CHECK_ERR_MSG(err, "i2c_write for set brightness\n")
+
+	return 0;
+}
+
+static int s5k5bafx_set_blur(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_blur: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if (unlikely(val < BLUR_LEVEL_0 || val >= BLUR_LEVEL_MAX)) {
+		cam_err("%s: ERROR, Invalid blur(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = s5k5bafx_set_from_table(sd, "blur", state->regs->blur,
+		ARRAY_SIZE(state->regs->blur), val);
+	CHECK_ERR_MSG(err, "i2c_write for set blur\n")
+
+	return 0;
+}
+
+#if (0)
+static int s5k5bafx_check_dataline_stop(struct v4l2_subdev *sd)
+{
+	return 0;
+}
+#endif
+
+static int s5k5bafx_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("g_ctrl: id = %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		ctrl->value = state->exif.exp_time_den;
+		break;
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+	default:
+		cam_err("%s: ERROR, no such control id %d\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	return err;
+}
+
+static int s5k5bafx_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("s_ctrl: id = %d, value=%d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if ((ctrl->id != V4L2_CID_CAMERA_CHECK_DATALINE)
+	    && (ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE)
+	    && ((ctrl->id != V4L2_CID_CAMERA_VT_MODE))
+	    && (!state->initialized)) {
+		cam_warn("%s: WARNING, camera not initialized\n", __func__);
+		return 0;
+	}
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = s5k5bafx_set_exposure(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_BRIGHTNESS [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		err = s5k5bafx_set_blur(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_VGA_BLUR [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = s5k5bafx_set_sensor_mode(sd, ctrl->value);
+		cam_dbg("sensor_mode = %d\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = s5k5bafx_check_esd(sd);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_SENSOR_STATUS:
+		s5k5bafx_debug_sensor_status(sd);
+		err = s5k5bafx_check_sensor_status(sd);
+		break;
+
+#ifdef SUPPORT_FACTORY_TEST
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		cam_dbg("check_dataline = %d\n", state->check_dataline);
+		err = 0;
+		break;
+#endif
+
+	default:
+		cam_err("%s: ERROR, Not supported ctrl-ID(%d)\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/* no errors return.*/
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops s5k5bafx_core_ops = {
+	.init = s5k5bafx_init,		/* initializing API */
+#if 0
+	.queryctrl = s5k5bafx_queryctrl,
+	.querymenu = s5k5bafx_querymenu,
+#endif
+	.g_ctrl = s5k5bafx_g_ctrl,
+	.s_ctrl = s5k5bafx_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k5bafx_video_ops = {
+	/*.s_crystal_freq = s5k5bafx_s_crystal_freq,*/
+#ifdef NEW_CAM_DRV
+	.g_mbus_fmt = s5k5bafx_g_mbus_fmt,
+	.s_mbus_fmt = s5k5bafx_s_mbus_fmt,
+#else
+	.g_fmt	= s5k5bafx_g_fmt,
+	.s_fmt	= s5k5bafx_s_fmt,
+#endif
+	.s_stream = s5k5bafx_s_stream,
+	.enum_framesizes = s5k5bafx_enum_framesizes,
+	/*.enum_frameintervals = s5k5bafx_enum_frameintervals,*/
+#ifdef NEW_CAM_DRV
+	/* .enum_mbus_fmt = s5k5bafx_enum_mbus_fmt, */
+	.try_mbus_fmt = s5k5bafx_try_mbus_fmt,
+#else
+	/*.enum_fmt = s5k5bafx_enum_fmt,*/
+	.try_fmt = s5k5bafx_try_fmt,
+#endif
+	.g_parm	= s5k5bafx_g_parm,
+	.s_parm	= s5k5bafx_s_parm,
+};
+
+static const struct v4l2_subdev_ops s5k5bafx_ops = {
+	.core = &s5k5bafx_core_ops,
+	.video = &s5k5bafx_video_ops,
+};
+
+ssize_t s5k5bafx_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	char *cam_type = "SLSI_S5K5BAFX";
+	cam_info("%s\n", __func__);
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static DEVICE_ATTR(camera_type, S_IRUGO, s5k5bafx_camera_type_show, NULL);
+
+/*
+ * s5k5bafx_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k5bafx_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	struct s5k5bafx_state *state = NULL;
+	struct v4l2_subdev *sd = NULL;
+	int err = -EINVAL;
+
+	state = kzalloc(sizeof(struct s5k5bafx_state), GFP_KERNEL);
+	CHECK_ERR_COND_MSG(!state, -ENOMEM, "fail to get memory(state)\n");
+
+	mutex_init(&state->ctrl_lock);
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K5BAFX_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k5bafx_ops);
+
+	err = s5k5bafx_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+#ifdef S5K5BAFX_BURST_MODE
+	state->burst_buf = kmalloc(SZ_2K, GFP_KERNEL);
+	CHECK_ERR_COND_MSG(!state->burst_buf, -ENOMEM,
+			"fail to get memory(buf)\n");
+#endif
+
+	printk(KERN_DEBUG "%s %s: driver probed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static int s5k5bafx_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct s5k5bafx_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	state->initialized = 0;
+
+	device_remove_file(&client->dev, &dev_attr_camera_type);
+	v4l2_device_unregister_subdev(sd);
+#ifdef S5K5BAFX_BURST_MODE
+	kfree(state->burst_buf);
+#endif
+	kfree(state);
+
+#ifdef CONFIG_LOAD_FILE
+	if (testBuf) {
+		large_file ? vfree(testBuf) : kfree(testBuf);
+		large_file = 0;
+		testBuf = NULL;
+	}
+#endif
+	printk(KERN_DEBUG "%s %s: driver removed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static const struct i2c_device_id s5k5bafx_id[] = {
+	{ S5K5BAFX_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k5bafx_id);
+
+static struct i2c_driver v4l2_i2c_driver = {
+	.driver.name	= S5K5BAFX_DRIVER_NAME,
+	.probe		= s5k5bafx_probe,
+	.remove		= s5k5bafx_remove,
+	.id_table	= s5k5bafx_id,
+};
+
+static int __init v4l2_i2c_drv_init(void)
+{
+	pr_info("%s: %s called\n", __func__, S5K5BAFX_DRIVER_NAME); /* dslim*/
+	return i2c_add_driver(&v4l2_i2c_driver);
+}
+
+static void __exit v4l2_i2c_drv_cleanup(void)
+{
+	pr_info("%s: %s called\n", __func__, S5K5BAFX_DRIVER_NAME); /* dslim*/
+	i2c_del_driver(&v4l2_i2c_driver);
+}
+
+module_init(v4l2_i2c_drv_init);
+module_exit(v4l2_i2c_drv_cleanup);
+
+MODULE_DESCRIPTION("S5K5BAFX ISP driver");
+MODULE_AUTHOR("DongSeong Lim<dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k5bafx-v2.h b/drivers/media/video/s5k5bafx-v2.h
new file mode 100644
index 0000000..78a095b
--- /dev/null
+++ b/drivers/media/video/s5k5bafx-v2.h
@@ -0,0 +1,267 @@
+/*
+ * Driver for S5K5BAFX 2M ISP from Samsung
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5K5BAFX_H
+#define __S5K5BAFX_H
+
+#include <linux/types.h>
+
+#define S5K5BAFX_DRIVER_NAME	"S5K5BAFX"
+
+/************************************
+ * FEATURE DEFINITIONS
+ ************************************/
+/* #define S5K5BAFX_USLEEP */
+#define S5K5BAFX_BURST_MODE
+/* #define CONFIG_LOAD_FILE */
+/* #define SUPPORT_FACTORY_TEST */
+#define NEW_CAM_DRV
+
+/** Debuging Feature **/
+/* #define CONFIG_CAM_DEBUG */
+/* #define CONFIG_CAM_TRACE *//* Enable it with CONFIG_CAM_DEBUG */
+/***********************************/
+
+#define TAG_NAME	"["S5K5BAFX_DRIVER_NAME"]"" "
+#define cam_err(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_warn(fmt, ...)	\
+	printk(KERN_WARNING TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_info(fmt, ...)	\
+	printk(KERN_INFO TAG_NAME fmt, ##__VA_ARGS__)
+
+#if defined(CONFIG_CAM_DEBUG)
+#define cam_dbg(fmt, ...)	\
+	printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_DEBUG) \
+			printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__); \
+	} while (0)
+#endif /* CONFIG_CAM_DEBUG */
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_TRACE)
+#define cam_trace(fmt, ...)	cam_dbg("%s: " fmt, __func__, ##__VA_ARGS__);
+#else
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_TRACE) \
+			printk(KERN_DEBUG TAG_NAME "%s: " fmt, \
+				__func__, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return (ret); } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+	if (unlikely(condition)) { \
+		cam_err("%s: ERROR, " fmt, __func__, ##__VA_ARGS__); \
+		return ret; \
+	}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+enum stream_cmd {
+	STREAM_STOP,
+	STREAM_START,
+};
+
+enum s5k5bafx_fps_index {
+	I_FPS_0,
+	I_FPS_7,
+	I_FPS_10,
+	I_FPS_12,
+	I_FPS_15,
+	I_FPS_25,
+	I_FPS_30,
+	I_FPS_MAX,
+};
+#define DEFAULT_FPS	15
+	
+struct s5k5bafx_framesize {
+	u32 width;
+	u32 height;
+};
+
+struct s5k5bafx_fps {
+	u32 index;
+	u32 fps;
+};
+
+struct s5k5bafx_exif {
+	u32 exp_time_den;
+	u32 shutter_speed;
+	u16 iso;
+};
+
+struct s5k5bafx_stream_time {
+	struct timeval curr_time;
+	struct timeval before_time;
+};
+
+#define GET_ELAPSED_TIME(cur, before) \
+		(((cur).tv_sec - (before).tv_sec) * USEC_PER_SEC \
+		+ ((cur).tv_usec - (before).tv_usec))
+
+
+#ifdef CONFIG_LOAD_FILE
+struct s5k5bafx_regset_table {
+	const u32	*reg;
+	int		array_size;
+	char		*name;
+};
+
+#define S5K5BAFX_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+
+#define S5K5BAFX_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+#else
+struct s5k5bafx_regset_table {
+	const u32	*reg;
+	int		array_size;
+};
+
+#define S5K5BAFX_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+
+#define S5K5BAFX_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+#endif
+
+#define EV_MIN_VLAUE	EV_MINUS_4
+#define GET_EV_INDEX(EV)	((EV) - (EV_MIN_VLAUE))
+
+struct s5k5bafx_regs {
+	struct s5k5bafx_regset_table ev[GET_EV_INDEX(EV_MAX_V4L2)];
+	struct s5k5bafx_regset_table blur[BLUR_LEVEL_MAX];
+	/* struct s5k5bafx_regset_table capture_size[S5K5BAFX_CAPTURE_MAX];*/
+	struct s5k5bafx_regset_table preview_start;
+	struct s5k5bafx_regset_table capture_start;
+	struct s5k5bafx_regset_table fps[I_FPS_MAX];
+	struct s5k5bafx_regset_table init;	/* Used */
+	struct s5k5bafx_regset_table init_vt;	/* Used */
+	struct s5k5bafx_regset_table init_vt_wifi;	/* Used */
+	struct s5k5bafx_regset_table init_recording;	/* Used */
+	struct s5k5bafx_regset_table get_light_level;
+	struct s5k5bafx_regset_table get_iso;
+	struct s5k5bafx_regset_table get_shutterspeed;
+	struct s5k5bafx_regset_table stream_stop;	/* Used */
+	struct s5k5bafx_regset_table dtp_on;
+	struct s5k5bafx_regset_table dtp_off;
+};
+
+/*
+ * Driver information
+ */
+struct s5k5bafx_state {
+	struct v4l2_subdev sd;
+	struct s5k5bafx_platform_data *pdata;
+	/*
+	 * req_fmt is the requested format from the application.
+	 * set_fmt is the output format of the camera. Finally FIMC
+	 * converts the camera output(set_fmt) to the requested format
+	 * with hardware scaler.
+	 */
+	struct v4l2_pix_format req_fmt;
+	struct s5k5bafx_framesize default_frmsizes;
+	struct s5k5bafx_framesize preview_frmsizes;
+	struct s5k5bafx_framesize capture_frmsizes;
+	struct s5k5bafx_exif exif;
+	struct s5k5bafx_stream_time stream_time;
+	const struct s5k5bafx_regs *regs;
+	struct mutex ctrl_lock;
+
+	enum v4l2_sensor_mode sensor_mode;
+	s32 vt_mode;
+	s32 req_fps;
+	s32 fps;
+#ifdef CONFIG_USE_SW_I2C
+	u32 cpufreq_lock_level;
+#endif
+	u8 *dbg_level;
+#ifdef S5K5BAFX_BURST_MODE
+	u8 *burst_buf;
+#endif
+	u32 check_dataline:1;
+	u32 need_wait_streamoff:1;
+	u32 initialized:1;
+};
+
+static inline struct s5k5bafx_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k5bafx_state, sd);
+}
+
+static inline void debug_msleep(struct v4l2_subdev *sd, u32 msecs)
+{
+	cam_dbg("delay for %dms\n", msecs);
+	msleep(msecs);
+}
+
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+struct test {
+	u8 data;
+	struct test *nextBuf;
+};
+static struct test *testBuf;
+static s32 large_file;
+
+#define TEST_INIT	\
+{			\
+	.data = 0;	\
+	.nextBuf = NULL;	\
+}
+
+#define TUNING_FILE_PATH "/mnt/sdcard/s5k5bafx_regs.h"
+#endif
+
+/*********** Sensor specific ************/
+#define S5K5BAFX_CHIP_ID	0x05BA
+#define S5K5BAFX_CHIP_REV	0xA0
+/* #define S5K5BAFX_100MS_DELAY	0xAA55AA5F */
+/* #define S5K5BAFX_10MS_DELAY	0xAA55AA5E */
+#define S5K5BAFX_DELAY		0xFFFF0000
+#define S5K5BAFX_DEF_APEX_DEN	100
+	
+/* Register address */
+#define REG_PAGE_SHUTTER    0x7000
+#define REG_ADDR_SHUTTER    0x14D0
+#define REG_PAGE_ISO        0x7000
+#define REG_ADDR_ISO        0x14C8
+	
+#include  "s5k5bafx_regs-p8.h"
+
+#endif /* __S5K5BAFX_H */
diff --git a/drivers/media/video/s5k5bafx.c b/drivers/media/video/s5k5bafx.c
new file mode 100644
index 0000000..ba8600d
--- /dev/null
+++ b/drivers/media/video/s5k5bafx.c
@@ -0,0 +1,1673 @@
+/*
+ * Driver for S5K5BAFX from Samsung Electronics
+ *
+ * 1/6" 2Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * Copyright (C) 2010, DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <media/v4l2-device.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+#include <media/s5k5bafx_platform.h>
+
+#include "s5k5bafx.h"
+
+#ifdef S5K5BAFX_USLEEP
+#include <linux/hrtimer.h>
+#endif
+
+#define S5K5BAFX_BURST_MODE
+
+#include <linux/slab.h>
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <asm/uaccess.h>
+
+struct test {
+	u8 data;
+	struct test *nextBuf;
+};
+static struct test *testBuf;
+static s32 large_file;
+
+#define TEST_INIT	\
+{			\
+	.data = 0;	\
+	.nextBuf = NULL;	\
+}
+#endif
+
+#define CHECK_ERR(x)	if (unlikely((x) < 0)) { \
+				cam_err("i2c failed, err %d\n", x); \
+				return x; \
+			}
+
+#define NELEMS(array) (sizeof(array) / sizeof(array[0]))
+
+extern struct class *camera_class;
+
+#ifdef S5K5BAFX_USLEEP
+/*
+ * Use msleep() if the sleep time is over 1000 us.
+*/
+static void s5k5bafx_usleep(u32 usecs)
+{
+	ktime_t expires;
+	u64 add_time = (u64)usecs * 1000;
+
+	if (unlikely(!usecs))
+		return;
+
+	expires = ktime_add_ns(ktime_get(), add_time);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_hrtimeout(&expires, HRTIMER_MODE_ABS);
+}
+#endif
+
+static inline int s5k5bafx_read(struct i2c_client *client,
+	u16 subaddr, u16 *data)
+{
+	u8 buf[2];
+	int err = 0;
+	struct i2c_msg msg = {
+		.addr = client->addr,
+		.flags = 0,
+		.len = 2,
+		.buf = buf,
+	};
+
+	*(u16 *)buf = cpu_to_be16(subaddr);
+
+	/* printk("\n\n\n%X %X\n\n\n", buf[0], buf[1]);*/
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0))
+		cam_err("ERR: %d register read fail\n", __LINE__);
+
+	msg.flags = I2C_M_RD;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0))
+		cam_err("ERR: %d register read fail\n", __LINE__);
+
+	/*printk("\n\n\n%X %X\n\n\n", buf[0], buf[1]);*/
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return err;
+}
+
+/*
+ * s5k6aafx sensor i2c write routine
+ * <start>--<Device address><2Byte Subaddr><2Byte Value>--<stop>
+ */
+#ifdef CONFIG_LOAD_FILE
+static int loadFile(void)
+{
+	struct file *fp = NULL;
+	struct test *nextBuf = NULL;
+
+	u8 *nBuf = NULL;
+	size_t file_size = 0, max_size = 0, testBuf_size = 0;
+	ssize_t nread = 0;
+	s32 check = 0, starCheck = 0;
+	s32 tmp_large_file = 0;
+	s32 i = 0;
+	int ret = 0;
+	loff_t pos;
+
+	mm_segment_t fs = get_fs();
+	set_fs(get_ds());
+
+	BUG_ON(testBuf);
+
+	fp = filp_open("/mnt/sdcard/external_sd/s5k5bafx.h", O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("file open error\n");
+		return PTR_ERR(fp);
+	}
+
+	file_size = (size_t) fp->f_path.dentry->d_inode->i_size;
+	max_size = file_size;
+
+	cam_dbg("file_size = %d\n", file_size);
+
+	nBuf = kmalloc(file_size, GFP_ATOMIC);
+	if (nBuf == NULL) {
+		cam_dbg("Fail to 1st get memory\n");
+		nBuf = vmalloc(file_size);
+		if (nBuf == NULL) {
+			cam_err("ERR: nBuf Out of Memory\n");
+			ret = -ENOMEM;
+			goto error_out;
+		}
+		tmp_large_file = 1;
+	}
+
+	testBuf_size = sizeof(struct test) * file_size;
+	if (tmp_large_file) {
+		testBuf = (struct test *)vmalloc(testBuf_size);
+		large_file = 1;
+	} else {
+		testBuf = kmalloc(testBuf_size, GFP_ATOMIC);
+		if (testBuf == NULL) {
+			cam_dbg("Fail to get mem(%d bytes)\n", testBuf_size);
+			testBuf = (struct test *)vmalloc(testBuf_size);
+			large_file = 1;
+		}
+	}
+	if (testBuf == NULL) {
+		cam_err("ERR: Out of Memory\n");
+		ret = -ENOMEM;
+		goto error_out;
+	}
+
+	pos = 0;
+	memset(nBuf, 0, file_size);
+	memset(testBuf, 0, file_size * sizeof(struct test));
+
+	nread = vfs_read(fp, (char __user *)nBuf, file_size, &pos);
+	if (nread != file_size) {
+		cam_err("failed to read file ret = %d\n", nread);
+		ret = -1;
+		goto error_out;
+	}
+
+	set_fs(fs);
+
+	i = max_size;
+
+	printk("i = %d\n", i);
+
+	while (i) {
+		testBuf[max_size - i].data = *nBuf;
+		if (i != 1) {
+			testBuf[max_size - i].nextBuf = &testBuf[max_size - i + 1];
+		} else {
+			testBuf[max_size - i].nextBuf = NULL;
+			break;
+		}
+		i--;
+		nBuf++;
+	}
+
+	i = max_size;
+	nextBuf = &testBuf[0];
+
+#if 1
+	while (i - 1) {
+		if (!check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+								== '/') {
+						check = 1;/* when find '//' */
+						i--;
+					} else if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1;/* when find '/ *' */
+						i--;
+					}
+				} else
+					break;
+			}
+			if (!check && !starCheck) {
+				/* ignore '\t' */
+				if (testBuf[max_size - i].data != '\t') {
+					nextBuf->nextBuf = &testBuf[max_size-i];
+					nextBuf = &testBuf[max_size - i];
+				}
+			}
+		} else if (check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1; /* when find '/ *' */
+						check = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+
+			 /* when find '\n' */
+			if (testBuf[max_size - i].data == '\n' && check) {
+				check = 0;
+				nextBuf->nextBuf = &testBuf[max_size - i];
+				nextBuf = &testBuf[max_size - i];
+			}
+
+		} else if (!check && starCheck) {
+			if (testBuf[max_size - i].data == '*') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '/') {
+						starCheck = 0; /* when find '* /' */
+						i--;
+					}
+				} else
+					break;
+			}
+		}
+
+		i--;
+
+		if (i < 2) {
+			nextBuf = NULL;
+			break;
+		}
+
+		if (testBuf[max_size - i].nextBuf == NULL) {
+			nextBuf = NULL;
+			break;
+		}
+	}
+#endif
+
+#if 0 /* for print */
+	printk("i = %d\n", i);
+	nextBuf = &testBuf[0];
+	while (1) {
+		/* printk("sdfdsf\n"); */
+		if (nextBuf->nextBuf == NULL)
+			break;
+		printk("%c", nextBuf->data);
+		nextBuf = nextBuf->nextBuf;
+	}
+#endif
+
+error_out:
+
+	if (nBuf)
+		tmp_large_file ? vfree(nBuf) : kfree(nBuf);
+	if (fp)
+		filp_close(fp, current->files);
+	return ret;
+}
+#endif
+
+static inline int s5k5bafx_write(struct i2c_client *client,
+		u32 packet)
+{
+	u8 buf[4];
+	int err = 0, retry_count = 5;
+
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.buf	= buf,
+		.len	= 4,
+	};
+
+	if (!client->adapter) {
+		cam_err("ERR - can't search i2c client adapter\n");
+		return -EIO;
+	}
+
+	while (retry_count--) {
+		*(u32 *)buf = cpu_to_be32(packet);
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(err == 1))
+			break;
+		mdelay(10);
+	}
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR - 0x%08x write failed err=%d\n",
+				(u32)packet, err);
+		return err;
+	}
+
+	return (err != 1) ? -1 : 0;
+}
+
+#ifdef CONFIG_LOAD_FILE
+static int s5k5bafx_write_regs_from_sd(struct v4l2_subdev *sd, u8 s_name[])
+{
+
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct test *tempData = NULL;
+
+	int ret = -EAGAIN;
+	u32 temp;
+	u32 delay = 0;
+	u8 data[11];
+	s32 searched = 0;
+	size_t size = strlen(s_name);
+	s32 i;
+
+	cam_dbg("E size = %d, string = %s\n", size, s_name);
+	tempData = &testBuf[0];
+	while (!searched) {
+		searched = 1;
+		for (i = 0; i < size; i++) {
+			if (tempData->data != s_name[i]) {
+				searched = 0;
+				break;
+			}
+			tempData = tempData->nextBuf;
+		}
+		tempData = tempData->nextBuf;
+	}
+	/* structure is get..*/
+
+	while (1) {
+		if (tempData->data == '{')
+			break;
+		else
+			tempData = tempData->nextBuf;
+	}
+
+	while (1) {
+		searched = 0;
+		while (1) {
+			if (tempData->data == 'x') {
+				/* get 10 strings.*/
+				data[0] = '0';
+				for (i = 1; i < 11; i++) {
+					data[i] = tempData->data;
+					tempData = tempData->nextBuf;
+				}
+				/*cam_dbg("%s\n", data);*/
+				temp = simple_strtoul(data, NULL, 16);
+				break;
+			} else if (tempData->data == '}') {
+				searched = 1;
+				break;
+			} else
+				tempData = tempData->nextBuf;
+
+			if (tempData->nextBuf == NULL)
+				return -1;
+		}
+
+		if (searched)
+			break;
+
+		if ((temp & S5K5BAFX_DELAY) == S5K5BAFX_DELAY) {
+			delay = temp & 0xFFFF;
+			cam_info("line(%d):delay(0x%x, %d)\n", __LINE__,
+							delay, delay);
+			msleep(delay);
+			continue;
+		}
+
+		ret = s5k5bafx_write(client, temp);
+
+		/* In error circumstances */
+		/* Give second shot */
+		if (unlikely(ret)) {
+			dev_info(&client->dev,
+					"s5k5bafx i2c retry one more time\n");
+			ret = s5k5bafx_write(client, temp);
+
+			/* Give it one more shot */
+			if (unlikely(ret)) {
+				dev_info(&client->dev,
+						"s5k5bafx i2c retry twice\n");
+				ret = s5k5bafx_write(client, temp);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+/*
+* Read a register.
+*/
+static int s5k5bafx_read_reg(struct v4l2_subdev *sd,
+		u16 page, u16 addr, u16 *val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u32 page_cmd = (0x002C << 16) | page;
+	u32 addr_cmd = (0x002E << 16) | addr;
+	int err = 0;
+
+	cam_dbg("page_cmd=0x%X, addr_cmd=0x%X\n", page_cmd, addr_cmd);
+
+	err = s5k5bafx_write(client, page_cmd);
+	CHECK_ERR(err);
+	err = s5k5bafx_write(client, addr_cmd);
+	CHECK_ERR(err);
+	err = s5k5bafx_read(client, 0x0F12, val);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+#ifdef S5K5BAFX_BURST_MODE
+	static u16 addr, value;
+
+	static int len;
+	static u8 buf[SZ_2K] = {0,};
+#else
+	static u8 buf[4] = {0,};
+#endif
+
+/* program multiple registers */
+static int s5k5bafx_write_regs(struct v4l2_subdev *sd,
+		const u32 *packet, u32 num)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int ret = -EAGAIN;
+	u32 temp = 0;
+	u16 delay = 0;
+	int retry_count = 5;
+
+	struct i2c_msg msg = {
+		msg.addr = client->addr,
+		msg.flags = 0,
+		msg.len = 4,
+		msg.buf = buf,
+	};
+
+	while (num--) {
+		temp = *packet++;
+
+		if ((temp & S5K5BAFX_DELAY) == S5K5BAFX_DELAY) {
+			delay = temp & 0xFFFF;
+			cam_dbg("line(%d):delay(0x%x):delay(%d)\n",
+						__LINE__, delay, delay);
+			msleep(delay);
+			continue;
+		}
+
+#ifdef S5K5BAFX_BURST_MODE
+		addr = temp >> 16;
+		value = temp & 0xFFFF;
+
+		switch (addr) {
+		case 0x0F12:
+			if (len == 0) {
+				buf[len++] = addr >> 8;
+				buf[len++] = addr & 0xFF;
+			}
+			buf[len++] = value >> 8;
+			buf[len++] = value & 0xFF;
+
+			if ((*packet >> 16) != addr) {
+				msg.len = len;
+				goto s5k5bafx_burst_write;
+			}
+			break;
+
+		case 0xFFFF:
+			break;
+
+		default:
+			msg.len = 4;
+			*(u32 *)buf = cpu_to_be32(temp);
+			goto s5k5bafx_burst_write;
+		}
+
+		continue;
+#else
+		*(u32 *)buf = cpu_to_be32(temp);
+#endif
+
+#ifdef S5K5BAFX_BURST_MODE
+s5k5bafx_burst_write:
+		len = 0;
+#endif
+		retry_count = 5;
+
+		while (retry_count--) {
+			ret = i2c_transfer(client->adapter, &msg, 1);
+			if (likely(ret == 1))
+				break;
+			mdelay(10);
+		}
+
+		if (unlikely(ret < 0)) {
+			cam_err("ERR - 0x%08x write failed err=%d\n", (u32)packet, ret);
+			break;
+		}
+
+#ifdef S5K5BAFX_USLEEP
+		if (unlikely(state->vt_mode))
+			if (!(num%200))
+				s5k5bafx_usleep(3);
+#endif
+	}
+
+	if (unlikely(ret < 0)) {
+		cam_err("fail to write registers!!\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_get_exif(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	u16 iso_gain_table[] = {10, 18, 23, 28};
+	u16 iso_table[] = {0, 50, 100, 200, 400};
+	u16 gain = 0, val = 0;
+	s32 index = 0;
+
+	state->exif.shutter_speed = 0;
+	state->exif.iso = 0;
+
+	/* Get shutter speed */
+	s5k5bafx_read_reg(sd, REG_PAGE_SHUTTER, REG_ADDR_SHUTTER, &val);
+	state->exif.shutter_speed = 1000 / (val / 500);
+	cam_dbg("val = %d\n", val);
+
+	/* Get ISO */
+	val = 0;
+	s5k5bafx_read_reg(sd, REG_PAGE_ISO, REG_ADDR_ISO, &val);
+	cam_dbg("val = %d\n", val);
+	gain = val * 10 / 256;
+	for (index = 0; index < NELEMS(iso_gain_table); index++) {
+		if (gain < iso_gain_table[index])
+			break;
+	}
+	state->exif.iso = iso_table[index];
+
+	cam_dbg("gain=%d, Shutter speed=%d, ISO=%d\n",
+		gain, state->exif.shutter_speed, state->exif.iso);
+	return 0;
+}
+
+static int s5k5bafx_check_dataline(struct v4l2_subdev *sd, s32 val)
+{
+	int err = 0;
+
+	cam_info("DTP %s\n", val ? "ON" : "OFF");
+
+#ifdef CONFIG_LOAD_FILE
+	if (val)
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_pattern_on");
+	else
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_pattern_off");
+#else
+	if (val) {
+		err = s5k5bafx_write_regs(sd, s5k5bafx_pattern_on,
+			sizeof(s5k5bafx_pattern_on) / \
+			sizeof(s5k5bafx_pattern_on[0]));
+	} else {
+		err = s5k5bafx_write_regs(sd, s5k5bafx_pattern_off,
+			sizeof(s5k5bafx_pattern_off) / \
+			sizeof(s5k5bafx_pattern_off[0]));
+	}
+#endif
+	if (unlikely(err)) {
+		cam_err("fail to DTP setting\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_debug_sensor_status(struct v4l2_subdev *sd)
+{
+	u16 val = 0;
+	int err = -EINVAL;
+
+	/* Read Mon_DBG_Counters_2 */
+	/*err = s5k5bafx_read_reg(sd, 0x7000, 0x0402, &val);
+	CHECK_ERR(err);
+	cam_info("counter = %d\n", val); */
+
+	/* Read REG_TC_GP_EnableCaptureChanged. */
+	err = s5k5bafx_read_reg(sd, 0x7000, 0x01F6, &val);
+	CHECK_ERR(err);
+
+	switch (val) {
+	case 0:
+		cam_info("In normal mode(0)\n");
+		break;
+	case 1:
+		cam_info("In swiching to capture mode(1).....\n");
+		break;
+	default:
+		cam_err("In Unknown mode(?)\n");
+		break;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_check_sensor_status(struct v4l2_subdev *sd)
+{
+	/*struct i2c_client *client = v4l2_get_subdevdata(sd);*/
+	u16 val_1 = 0, val_2 = 0;
+	int err = -EINVAL;
+
+	err = s5k5bafx_read_reg(sd, 0x7000, 0x0132, &val_1);
+	CHECK_ERR(err);
+	err = s5k5bafx_read_reg(sd, 0xD000, 0x1002, &val_2);
+	CHECK_ERR(err);
+
+	cam_dbg("read val1=0x%x, val2=0x%x\n", val_1, val_2);
+
+	if ((val_1 != 0xAAAA) || (val_2 != 0))
+		goto error_occur;
+
+	cam_dbg("Sensor error is not detected\n");
+	return 0;
+
+error_occur:
+	cam_err("ERR: Sensor error occurs\n\n");
+	return -EIO;
+}
+
+static inline int s5k5bafx_check_esd(struct v4l2_subdev *sd)
+{
+	int err = -EINVAL;
+
+	err = s5k5bafx_check_sensor_status(sd);
+	if (err < 0) {
+		cam_err("ERR: ESD Shock detected!\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("reset preview\n");
+
+#ifdef CONFIG_LOAD_FILE
+	err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_preview");
+#else
+	err = s5k5bafx_write_regs(sd, s5k5bafx_preview,
+		sizeof(s5k5bafx_preview) / sizeof(s5k5bafx_preview[0]));
+#endif
+	if (state->check_dataline)
+		err = s5k5bafx_check_dataline(sd, 1);
+	if (unlikely(err)) {
+		cam_err("fail to make preview\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_set_preview_stop(struct v4l2_subdev *sd)
+{
+	int err = 0;
+	cam_info("do nothing.\n");
+
+	return err;
+}
+
+static int s5k5bafx_set_capture_start(struct v4l2_subdev *sd)
+{
+	int err = -EINVAL;
+
+	/* set initial regster value */
+#ifdef CONFIG_LOAD_FILE
+	err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_capture");
+#else
+	err = s5k5bafx_write_regs(sd, s5k5bafx_capture,
+		sizeof(s5k5bafx_capture) / sizeof(s5k5bafx_capture[0]));
+#endif
+	if (unlikely(err)) {
+		cam_err("failed to make capture\n");
+		return err;
+	}
+
+	s5k5bafx_get_exif(sd);
+
+	return err;
+}
+
+static int s5k5bafx_set_sensor_mode(struct v4l2_subdev *sd,
+					struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+
+	if ((ctrl->value != SENSOR_CAMERA) &&
+	(ctrl->value != SENSOR_MOVIE)) {
+		cam_err("ERR: Not support.(%d)\n", ctrl->value);
+		return -EINVAL;
+	}
+
+	/* We does not support movie mode when in VT. */
+	if ((ctrl->value == SENSOR_MOVIE) && state->vt_mode) {
+		state->sensor_mode = SENSOR_CAMERA;
+		cam_warn("ERR: Not support movie\n");
+	} else
+		state->sensor_mode = ctrl->value;
+
+	return 0;
+}
+
+static int s5k5bafx_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+{
+	cam_dbg("E\n");
+	return 0;
+}
+
+static int s5k5bafx_enum_framesizes(struct v4l2_subdev *sd, \
+					struct v4l2_frmsizeenum *fsize)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+
+	cam_dbg("E\n");
+
+	/*
+	 * Return the actual output settings programmed to the camera
+	 */
+	if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		fsize->discrete.width = state->capture_frmsizes.width;
+		fsize->discrete.height = state->capture_frmsizes.height;
+	} else {
+		fsize->discrete.width = state->preview_frmsizes.width;
+		fsize->discrete.height = state->preview_frmsizes.height;
+	}
+
+	cam_info("width - %d , height - %d\n",
+		fsize->discrete.width, fsize->discrete.height);
+
+	return 0;
+}
+
+#if (0) /* not used */
+static int s5k5bafx_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmtdesc)
+{
+	int err = 0;
+
+	FUNC_ENTR();
+	return err;
+}
+
+static int s5k5bafx_enum_frameintervals(struct v4l2_subdev *sd,
+					struct v4l2_frmivalenum *fival)
+{
+	int err = 0;
+
+	FUNC_ENTR();
+	return err;
+}
+#endif
+
+static int s5k5bafx_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+{
+	int err = 0;
+
+	cam_dbg("E\n");
+
+	return err;
+}
+
+static int s5k5bafx_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *ffmt)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	u32 *width = NULL, *height = NULL;
+
+	cam_dbg("E\n");
+	/*
+	 * Just copying the requested format as of now.
+	 * We need to check here what are the formats the camera support, and
+	 * set the most appropriate one according to the request from FIMC
+	 */
+
+#ifdef CONFIG_VIDEO_CONFERENCE_CALL
+	if (state->vt_mode == 3) {
+		state->req_fmt.width = fmt->fmt.pix.height;
+		state->req_fmt.height = fmt->fmt.pix.width;
+	}
+#endif
+
+	state->req_fmt.width = ffmt->width;
+	state->req_fmt.height = ffmt->height;
+	state->req_fmt.priv = ffmt->field;
+
+	switch (state->req_fmt.priv) {
+	case V4L2_PIX_FMT_MODE_PREVIEW:
+		cam_dbg("V4L2_PIX_FMT_MODE_PREVIEW\n");
+		width = &state->preview_frmsizes.width;
+		height = &state->preview_frmsizes.height;
+		break;
+
+	case V4L2_PIX_FMT_MODE_CAPTURE:
+		cam_dbg("V4L2_PIX_FMT_MODE_CAPTURE\n");
+		width = &state->capture_frmsizes.width;
+		height = &state->capture_frmsizes.height;
+		break;
+
+	default:
+		cam_err("ERR(EINVAL)\n");
+		return -EINVAL;
+	}
+
+	if ((*width != state->req_fmt.width) ||
+		(*height != state->req_fmt.height)) {
+		cam_err("ERR: Invalid size. width= %d, height= %d\n",
+			state->req_fmt.width, state->req_fmt.height);
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_set_frame_rate(struct v4l2_subdev *sd, u32 fps)
+{
+	int err = 0;
+
+	cam_info("frame rate %d\n\n", fps);
+
+#ifdef CONFIG_LOAD_FILE
+	switch (fps) {
+	case 7:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_7fps");
+		break;
+	case 10:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_10fps");
+
+		break;
+	case 12:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_12fps");
+
+		break;
+	case 15:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_15fps");
+		break;
+	case 30:
+		cam_err("frame rate is 30\n");
+		break;
+	default:
+		cam_err("ERR: Invalid framerate\n");
+		break;
+	}
+#else
+	switch (fps) {
+	case 7:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_7fps,
+				sizeof(s5k5bafx_vt_7fps) / \
+				sizeof(s5k5bafx_vt_7fps[0]));
+		break;
+	case 10:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_10fps,
+				sizeof(s5k5bafx_vt_10fps) / \
+				sizeof(s5k5bafx_vt_10fps[0]));
+
+		break;
+	case 12:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_12fps,
+				sizeof(s5k5bafx_vt_12fps) / \
+				sizeof(s5k5bafx_vt_12fps[0]));
+
+		break;
+	case 15:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_15fps,
+				sizeof(s5k5bafx_vt_15fps) / \
+				sizeof(s5k5bafx_vt_15fps[0]));
+		break;
+	case 30:
+		cam_warn("frame rate is 30\n");
+		break;
+	default:
+		cam_err("ERR: Invalid framerate\n");
+		break;
+	}
+#endif
+
+	if (unlikely(err < 0)) {
+		cam_err("i2c_write for set framerate\n");
+		return -EIO;
+	}
+
+	return err;
+}
+
+static int s5k5bafx_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+
+	cam_dbg("E\n");
+
+	return err;
+}
+
+static int s5k5bafx_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+	u32 fps = 0;
+	struct s5k5bafx_state *state = to_state(sd);
+
+	if (!state->vt_mode)
+		return 0;
+
+	cam_dbg("E\n");
+
+	fps = parms->parm.capture.timeperframe.denominator /
+			parms->parm.capture.timeperframe.numerator;
+
+	if (fps != state->set_fps) {
+		if (fps < 0 && fps > 15) {
+			cam_err("invalid frame rate %d\n", fps);
+			fps = 15;
+		}
+		state->req_fps = fps;
+
+		if (state->initialized) {
+			err = s5k5bafx_set_frame_rate(sd, state->req_fps);
+			if (err >= 0)
+				state->set_fps = state->req_fps;
+		}
+
+	}
+
+	return err;
+}
+
+#if (0) /* not used */
+static int s5k5bafx_set_60hz_antibanding(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	FUNC_ENTR();
+
+	u32 s5k5bafx_antibanding60hz[] = {
+		0xFCFCD000,
+		0x00287000,
+		/* Anti-Flicker //
+		// End user init script */
+		0x002A0400,
+		0x0F12005F,	/* REG_TC_DBG_AutoAlgEnBits //Auto Anti-Flicker is enabled bit[5] = 1. */
+		0x002A03DC,
+		0x0F120002,	/* 02 REG_SF_USER_FlickerQuant //Set flicker quantization(0: no AFC, 1: 50Hz, 2: 60 Hz) */
+		0x0F120001,
+	};
+
+	err = s5k5bafx_write_regs(sd, s5k5bafx_antibanding60hz,
+				  sizeof(s5k5bafx_antibanding60hz) /
+				  sizeof(s5k5bafx_antibanding60hz[0]));
+	pr_info("%s: setting 60hz antibanding\n", __func__);
+	if (unlikely(err)) {
+		pr_info("%s: failed to set 60hz antibanding\n", __func__);
+		return err;
+	}
+
+	return 0;
+}
+#endif
+
+static int s5k5bafx_control_stream(struct v4l2_subdev *sd, stream_cmd_t cmd)
+{
+	int err = 0;
+
+	switch (cmd) {
+	case STREAM_START:
+		cam_warn("WARN: do nothing\n");
+		break;
+
+	case STREAM_STOP:
+		cam_dbg("stream stop!!!\n");
+#ifdef CONFIG_LOAD_FILE
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_stream_stop");
+#else
+		err = s5k5bafx_write_regs(sd, s5k5bafx_stream_stop,
+			sizeof(s5k5bafx_stream_stop) / \
+			sizeof(s5k5bafx_stream_stop[0]));
+#endif
+		break;
+	default:
+		cam_err("ERR: Invalid cmd\n");
+		break;
+	}
+
+	if (unlikely(err))
+		cam_err("failed to stream start(stop)\n");
+
+	return err;
+}
+
+static int s5k5bafx_init(struct v4l2_subdev *sd, u32 val)
+{
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("E\n");
+
+	/* set initial regster value */
+#ifdef CONFIG_LOAD_FILE
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			cam_dbg("load camera common setting\n");
+			err = s5k5bafx_write_regs_from_sd(sd,
+					"s5k5bafx_common");
+		} else {
+			if (state->vt_mode == 1) {
+				cam_info("load camera VT call setting\n");
+				err = s5k5bafx_write_regs_from_sd(sd,
+						"s5k5bafx_vt_common");
+			} else {
+				cam_info("load camera WIFI VT call setting\n");
+				err = s5k5bafx_write_regs_from_sd(sd,
+						"s5k5bafx_vt_wifi_common");
+			}
+		}
+	} else {
+		cam_info("load recording setting\n");
+
+		if (ANTI_BANDING_50HZ == state->anti_banding) {
+			err = s5k5bafx_write_regs_from_sd(sd,
+				"s5k5bafx_recording_50Hz_common");
+		} else {
+			err = s5k5bafx_write_regs_from_sd(sd,
+				"s5k5bafx_recording_60Hz_common");
+		}
+	}
+#else
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			cam_info("load camera common setting\n");
+			err = s5k5bafx_write_regs(sd, s5k5bafx_common,
+				sizeof(s5k5bafx_common) / \
+				sizeof(s5k5bafx_common[0]));
+		} else {
+#ifdef CONFIG_VIDEO_CONFERENCE_CALL
+			if (state->vt_mode == 1 || state->vt_mode == 3) {
+#else
+			if (state->vt_mode == 1) {
+#endif
+				cam_info("load camera VT call setting\n");
+				err = s5k5bafx_write_regs(sd, s5k5bafx_vt_common,
+					sizeof(s5k5bafx_vt_common) / \
+					sizeof(s5k5bafx_vt_common[0]));
+			} else {
+				cam_info("load camera WIFI VT call setting\n");
+				err = s5k5bafx_write_regs(sd, s5k5bafx_vt_wifi_common,
+					sizeof(s5k5bafx_vt_wifi_common) / \
+					sizeof(s5k5bafx_vt_wifi_common[0]));
+			}
+		}
+	} else {
+		cam_info("load recording setting\n");
+		if (ANTI_BANDING_50HZ == state->anti_banding) {
+			err = s5k5bafx_write_regs(sd, s5k5bafx_recording_50Hz_common,
+				sizeof(s5k5bafx_recording_50Hz_common) / \
+				sizeof(s5k5bafx_recording_50Hz_common[0]));
+		} else {
+			err = s5k5bafx_write_regs(sd, s5k5bafx_recording_60Hz_common,
+				sizeof(s5k5bafx_recording_60Hz_common) / \
+				sizeof(s5k5bafx_recording_60Hz_common[0]));
+		}
+	}
+#endif
+	if (unlikely(err)) {
+		cam_err("failed to init\n");
+		return err;
+	}
+
+	/* We stop stream-output from sensor when starting camera. */
+	err = s5k5bafx_control_stream(sd, STREAM_STOP);
+	if (unlikely(err < 0))
+		return err;
+	msleep(150);
+
+	if (state->vt_mode && (state->req_fps != state->set_fps)) {
+		err = s5k5bafx_set_frame_rate(sd, state->req_fps);
+		if (unlikely(err < 0))
+			return err;
+		else
+			state->set_fps = state->req_fps;
+	}
+
+	state->initialized = 1;
+
+	return 0;
+}
+
+#if 0
+static int s5k5bafx_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+	FUNC_ENTR();
+	return 0;
+}
+
+static int s5k5bafx_querymenu(struct v4l2_subdev *sd, struct v4l2_querymenu *qm)
+{
+	FUNC_ENTR();
+	return 0;
+}
+#endif
+
+static int s5k5bafx_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	int err = 0;
+
+	cam_info("stream mode = %d\n", enable);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->sensor_mode == SENSOR_CAMERA) {
+			if (state->check_dataline)
+				err = s5k5bafx_check_dataline(sd, 0);
+			else
+				err = s5k5bafx_control_stream(sd, STREAM_STOP);
+		}
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		/* The position of this code need to be adjusted later */
+		if ((state->sensor_mode == SENSOR_CAMERA)
+		&& (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE))
+			err = s5k5bafx_set_capture_start(sd);
+		else
+			err = s5k5bafx_set_preview_start(sd);
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_dbg("do nothing(movie on)!!\n");
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_dbg("do nothing(movie off)!!\n");
+		break;
+
+	default:
+		cam_err("ERR: Invalid stream mode\n");
+		break;
+	}
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR: faild\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("ctrl->id : %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_TV:
+		ctrl->value = state->exif.shutter_speed;
+		break;
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE);
+		break;
+	}
+
+	return err;
+}
+
+static int s5k5bafx_set_brightness(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("E\n");
+
+	if (state->check_dataline)
+		return 0;
+
+#ifdef CONFIG_LOAD_FILE
+	switch (ctrl->value) {
+	case EV_MINUS_4:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_m4");
+		break;
+	case EV_MINUS_3:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_m3");
+		break;
+	case EV_MINUS_2:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_m2");
+		break;
+	case EV_MINUS_1:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_m1");
+		break;
+	case EV_DEFAULT:
+		err = s5k5bafx_write_regs_from_sd(sd,
+			"s5k5bafx_bright_default");
+		break;
+	case EV_PLUS_1:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_p1");
+		break;
+	case EV_PLUS_2:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_p2");
+		break;
+	case EV_PLUS_3:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_p3");
+		break;
+	case EV_PLUS_4:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_bright_p4");
+		break;
+	default:
+		cam_err("ERR: Invalid brightness(%d)\n", ctrl->value);
+		return err;
+		break;
+	}
+#else
+	switch (ctrl->value) {
+	case EV_MINUS_4:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_m4, \
+			sizeof(s5k5bafx_bright_m4) / \
+			sizeof(s5k5bafx_bright_m4[0]));
+		break;
+	case EV_MINUS_3:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_m3, \
+			sizeof(s5k5bafx_bright_m3) / \
+			sizeof(s5k5bafx_bright_m3[0]));
+
+		break;
+	case EV_MINUS_2:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_m2, \
+			sizeof(s5k5bafx_bright_m2) / \
+			sizeof(s5k5bafx_bright_m2[0]));
+		break;
+	case EV_MINUS_1:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_m1, \
+			sizeof(s5k5bafx_bright_m1) / \
+			sizeof(s5k5bafx_bright_m1[0]));
+		break;
+	case EV_DEFAULT:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_default, \
+			sizeof(s5k5bafx_bright_default) / \
+			sizeof(s5k5bafx_bright_default[0]));
+		break;
+	case EV_PLUS_1:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_p1, \
+			sizeof(s5k5bafx_bright_p1) / \
+			sizeof(s5k5bafx_bright_p1[0]));
+		break;
+	case EV_PLUS_2:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_p2, \
+			sizeof(s5k5bafx_bright_p2) / \
+			sizeof(s5k5bafx_bright_p2[0]));
+		break;
+	case EV_PLUS_3:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_p3, \
+			sizeof(s5k5bafx_bright_p3) / \
+			sizeof(s5k5bafx_bright_p3[0]));
+		break;
+	case EV_PLUS_4:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_bright_p4, \
+			sizeof(s5k5bafx_bright_p4) / \
+			sizeof(s5k5bafx_bright_p4[0]));
+		break;
+	default:
+		cam_err("ERR: invalid brightness(%d)\n", ctrl->value);
+		return err;
+		break;
+	}
+#endif
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR: i2c_write for set brightness\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_set_blur(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("E\n");
+
+	if (state->check_dataline)
+		return 0;
+
+#ifdef CONFIG_LOAD_FILE
+	switch (ctrl->value) {
+	case BLUR_LEVEL_0:
+		err = s5k5bafx_write_regs_from_sd(sd,
+				"s5k5bafx_vt_pretty_default");
+		break;
+	case BLUR_LEVEL_1:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_pretty_1");
+		break;
+	case BLUR_LEVEL_2:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_pretty_2");
+		break;
+	case BLUR_LEVEL_3:
+	case BLUR_LEVEL_MAX:
+		err = s5k5bafx_write_regs_from_sd(sd, "s5k5bafx_vt_pretty_3");
+		break;
+	default:
+		cam_err("ERR: Invalid blur(%d)\n", ctrl->value);
+		return err;
+		break;
+	}
+#else
+	switch (ctrl->value) {
+	case BLUR_LEVEL_0:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_pretty_default, \
+			sizeof(s5k5bafx_vt_pretty_default) / \
+			sizeof(s5k5bafx_vt_pretty_default[0]));
+		break;
+	case BLUR_LEVEL_1:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_pretty_1, \
+			sizeof(s5k5bafx_vt_pretty_1) / \
+			sizeof(s5k5bafx_vt_pretty_1[0]));
+		break;
+	case BLUR_LEVEL_2:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_pretty_2, \
+			sizeof(s5k5bafx_vt_pretty_2) / \
+			sizeof(s5k5bafx_vt_pretty_2[0]));
+		break;
+	case BLUR_LEVEL_3:
+	case BLUR_LEVEL_MAX:
+		err = s5k5bafx_write_regs(sd, s5k5bafx_vt_pretty_3, \
+			sizeof(s5k5bafx_vt_pretty_3) / \
+			sizeof(s5k5bafx_vt_pretty_3[0]));
+		break;
+	default:
+		cam_err("ERR: Invalid blur(%d)\n", ctrl->value);
+		return err;
+		break;
+	}
+#endif
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR: i2c_write for set blur\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s5k5bafx_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	struct s5k5bafx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("ctrl->id : %d, value=%d\n", ctrl->id - V4L2_CID_PRIVATE_BASE,
+	ctrl->value);
+
+	if ((ctrl->id != V4L2_CID_CAMERA_CHECK_DATALINE)
+	&& (ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE)
+	&& ((ctrl->id != V4L2_CID_CAMERA_VT_MODE))
+	&& (ctrl->id != V4L2_CID_CAMERA_ANTI_BANDING)
+	&& (!state->initialized)) {
+		cam_warn("camera isn't initialized\n");
+		return 0;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_PREVIEW_ONOFF:
+		if (ctrl->value)
+			err = s5k5bafx_set_preview_start(sd);
+		else
+			err = s5k5bafx_set_preview_stop(sd);
+		cam_dbg("V4L2_CID_CAM_PREVIEW_ONOFF [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_CAPTURE:
+		err = s5k5bafx_set_capture_start(sd);
+		cam_dbg("V4L2_CID_CAM_CAPTURE\n");
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = s5k5bafx_set_brightness(sd, ctrl);
+		cam_dbg("V4L2_CID_CAMERA_BRIGHTNESS [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		err = s5k5bafx_set_blur(sd, ctrl);
+		cam_dbg("V4L2_CID_CAMERA_VGA_BLUR [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		state->anti_banding = ctrl->value;
+		cam_dbg("V4L2_CID_CAMERA_ANTI_BANDING [%d],[%d]\n",
+				state->anti_banding, ctrl->value);
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		cam_dbg("check_dataline = %d\n", state->check_dataline);
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = s5k5bafx_set_sensor_mode(sd, ctrl);
+		cam_dbg("sensor_mode = %d\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE_STOP:
+		cam_dbg("do nothing\n");
+		/*err = s5k5bafx_check_dataline_stop(sd);*/
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = s5k5bafx_check_esd(sd);
+		break;
+
+	case V4L2_CID_CAMERA_FRAME_RATE:
+		cam_dbg("do nothing\n");
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_SENSOR_STATUS:
+		s5k5bafx_debug_sensor_status(sd);
+		err = s5k5bafx_check_sensor_status(sd);
+		break;
+
+	default:
+		cam_err("ERR(ENOIOCTLCMD)\n");
+		/* no errors return.*/
+		break;
+	}
+
+	cam_dbg("X\n");
+	return err;
+}
+
+static const struct v4l2_subdev_core_ops s5k5bafx_core_ops = {
+	.init = s5k5bafx_init,		/* initializing API */
+#if 0
+	.queryctrl = s5k5bafx_queryctrl,
+	.querymenu = s5k5bafx_querymenu,
+#endif
+	.g_ctrl = s5k5bafx_g_ctrl,
+	.s_ctrl = s5k5bafx_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops s5k5bafx_video_ops = {
+	/*.s_crystal_freq = s5k5bafx_s_crystal_freq,*/
+	.s_mbus_fmt	= s5k5bafx_s_fmt,
+	.s_stream = s5k5bafx_s_stream,
+	.enum_framesizes = s5k5bafx_enum_framesizes,
+	/*.enum_frameintervals = s5k5bafx_enum_frameintervals,*/
+	/*.enum_fmt = s5k5bafx_enum_fmt,*/
+	.g_parm	= s5k5bafx_g_parm,
+	.s_parm	= s5k5bafx_s_parm,
+};
+
+static const struct v4l2_subdev_ops s5k5bafx_ops = {
+	.core = &s5k5bafx_core_ops,
+	.video = &s5k5bafx_video_ops,
+};
+
+ssize_t s5k5bafx_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	char *cam_type;
+	cam_info("%s\n", __func__);
+
+	cam_type = "SLSI_S5K5BAFX";
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static DEVICE_ATTR(front_camtype, S_IRUGO, s5k5bafx_camera_type_show, NULL);
+
+/*
+ * s5k5bafx_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k5bafx_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	struct s5k5bafx_state *state = NULL;
+	struct v4l2_subdev *sd = NULL;
+	struct s5k5bafx_platform_data *pdata = NULL;
+	cam_dbg("E\n");
+
+	state = kzalloc(sizeof(struct s5k5bafx_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, S5K5BAFX_DRIVER_NAME);
+
+	state->initialized = 0;
+	state->req_fps = state->set_fps = 8;
+	state->sensor_mode = SENSOR_CAMERA;
+
+	pdata = client->dev.platform_data;
+
+	if (!pdata) {
+		cam_err("no platform data\n");
+		return -ENODEV;
+	}
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k5bafx_ops);
+
+	if (state->s5k5bafx_dev == NULL) {
+		state->s5k5bafx_dev =
+		    device_create(camera_class, NULL, 0, NULL,
+				  "front");
+		if (IS_ERR(state->s5k5bafx_dev)) {
+			cam_err("failed to create device s5k5bafx_dev!\n");
+		} else {
+			dev_set_drvdata(state->s5k5bafx_dev, state);
+			if (device_create_file
+			    (state->s5k5bafx_dev,
+			     &dev_attr_front_camtype) < 0) {
+				cam_err("failed to create device file, %s\n",
+				dev_attr_front_camtype.attr.name);
+			}
+		}
+	}
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	if (!(pdata->default_width && pdata->default_height)) {
+		state->preview_frmsizes.width = DEFAULT_PREVIEW_WIDTH;
+		state->preview_frmsizes.height = DEFAULT_PREVIEW_HEIGHT;
+	} else {
+		state->preview_frmsizes.width = pdata->default_width;
+		state->preview_frmsizes.height = pdata->default_height;
+	}
+	state->capture_frmsizes.width = DEFAULT_CAPTURE_WIDTH;
+	state->capture_frmsizes.height = DEFAULT_CAPTURE_HEIGHT;
+
+	cam_dbg("preview_width: %d , preview_height: %d, "
+	"capture_width: %d, capture_height: %d",
+	state->preview_frmsizes.width, state->preview_frmsizes.height,
+	state->capture_frmsizes.width, state->capture_frmsizes.height);
+
+	state->req_fmt.width = state->preview_frmsizes.width;
+	state->req_fmt.height = state->preview_frmsizes.height;
+
+	if (!pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_FMT;
+	else
+		state->req_fmt.pixelformat = pdata->pixelformat;
+
+	cam_dbg("probed!!\n");
+
+	return 0;
+}
+
+static int s5k5bafx_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct s5k5bafx_state *state = to_state(sd);
+
+	cam_dbg("E\n");
+
+	state->initialized = 0;
+
+	device_remove_file(state->s5k5bafx_dev, &dev_attr_front_camtype);
+	device_destroy(camera_class, 0);
+	state->s5k5bafx_dev = NULL;
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+
+#ifdef CONFIG_LOAD_FILE
+	if (testBuf) {
+		large_file ? vfree(testBuf) : kfree(testBuf);
+		large_file = 0;
+		testBuf = NULL;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct i2c_device_id s5k5bafx_id[] = {
+	{ S5K5BAFX_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, s5k5bafx_id);
+
+static struct i2c_driver s5k5bafx_i2c_driver = {
+	.driver = {
+		.name	= S5K5BAFX_DRIVER_NAME,
+	},
+	.probe		= s5k5bafx_probe,
+	.remove		= s5k5bafx_remove,
+	.id_table	= s5k5bafx_id,
+};
+
+static int __init s5k5bafx_mod_init(void)
+{
+	cam_dbg("E\n");
+	return i2c_add_driver(&s5k5bafx_i2c_driver);
+}
+
+static void __exit s5k5bafx_mod_exit(void)
+{
+	cam_dbg("E\n");
+	i2c_del_driver(&s5k5bafx_i2c_driver);
+}
+module_init(s5k5bafx_mod_init);
+module_exit(s5k5bafx_mod_exit);
+
+MODULE_DESCRIPTION("S5K5BAFX ISP driver");
+MODULE_AUTHOR("DongSeong Lim<dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k5bafx.h b/drivers/media/video/s5k5bafx.h
new file mode 100644
index 0000000..00f4c88
--- /dev/null
+++ b/drivers/media/video/s5k5bafx.h
@@ -0,0 +1,116 @@
+/*
+ * Driver for S5K5BAFX 2M ISP from Samsung
+ *
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5K5BAFX_H
+#define __S5K5BAFX_H
+
+#include <linux/types.h>
+
+#define S5K5BAFX_DRIVER_NAME	"S5K5BAFX"
+
+typedef enum {
+	STREAM_STOP,
+	STREAM_START,
+} stream_cmd_t;
+
+struct s5k5bafx_framesize {
+	u32 width;
+	u32 height;
+};
+
+struct s5k5bafx_exif {
+	u32 shutter_speed;
+	u16 iso;
+};
+
+
+/*
+ * Driver information
+ */
+struct s5k5bafx_state {
+	struct v4l2_subdev sd;
+	struct device *s5k5bafx_dev;
+	/*
+	 * req_fmt is the requested format from the application.
+	 * set_fmt is the output format of the camera. Finally FIMC
+	 * converts the camera output(set_fmt) to the requested format
+	 * with hardware scaler.
+	 */
+	struct v4l2_pix_format req_fmt;
+	struct s5k5bafx_framesize preview_frmsizes;
+	struct s5k5bafx_framesize capture_frmsizes;
+	struct s5k5bafx_exif exif;
+
+	enum v4l2_sensor_mode sensor_mode;
+	s32 vt_mode;
+	s32 check_dataline;
+	s32 anti_banding;
+	u32 req_fps;
+	u32 set_fps;
+	u32 initialized;
+};
+
+static inline struct s5k5bafx_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k5bafx_state, sd);
+}
+
+/*#define CONFIG_CAM_DEBUG */
+#define cam_warn(fmt, ...)	\
+	do { \
+		printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_err(fmt, ...)	\
+	do { \
+		printk(KERN_ERR "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_info(fmt, ...)	\
+	do { \
+		printk(KERN_INFO "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#ifdef CONFIG_CAM_DEBUG
+#define cam_dbg(fmt, ...)	\
+	do { \
+		printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+#else
+#define cam_dbg(fmt, ...)
+#endif /* CONFIG_CAM_DEBUG */
+
+
+/************ driver feature ************/
+#define S5K5BAFX_USLEEP
+/* #define CONFIG_LOAD_FILE */
+
+
+/*********** Sensor specific ************/
+/* #define S5K5BAFX_100MS_DELAY	0xAA55AA5F */
+/* #define S5K5BAFX_10MS_DELAY	0xAA55AA5E */
+#define S5K5BAFX_DELAY		0xFFFF0000
+#define S5K5BAFX_DEF_APEX_DEN	100
+
+/* Register address */
+#define REG_PAGE_SHUTTER    0x7000
+#define REG_ADDR_SHUTTER    0x14D0
+#define REG_PAGE_ISO        0x7000
+#define REG_ADDR_ISO        0x14C8
+
+#ifdef CONFIG_MACH_U1_KOR_LGT
+#include  "s5k5bafx_setfile_lgt.h"
+#else
+#include  "s5k5bafx_setfile.h"
+#endif
+
+#endif /* __S5K5BAFX_H */
diff --git a/drivers/media/video/s5k5bafx_regs-p8.h b/drivers/media/video/s5k5bafx_regs-p8.h
new file mode 100644
index 0000000..266598c
--- /dev/null
+++ b/drivers/media/video/s5k5bafx_regs-p8.h
@@ -0,0 +1,13232 @@
+/*
+ * Driver for S5K5BAFX 2M ISP from Samsung
+ * latest version: 11/09/26
+ * 
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __S5K5BAFX_REGS_H
+#define __S5K5BAFX_REGS_H
+
+#include <linux/types.h>
+
+/*
+ * s5k5bafx register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name		: S5K5BAFX Initial Setfile
+* PLL mode	: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS		: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by	: ZEROHOY
+* Date		: 2011.03.07
+* History	:
+*******************************************************/
+static const u32 s5k5bafx_common[] = {
+	/* Self-Cam */
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064,
+
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA,
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+                                                                       
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+
+	0x0F120015,
+
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+                                                                                                             
+	0x002AF900,
+	0x0F120067,
+                                                                                                             
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+                                                                                                             
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+                                                                                                             
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+                                                                                
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+                                                                                
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+                                                                                
+	0x002AF4D6,
+	0x0F120090,
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller*/
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+                                                                        
+	0x002A10EE,
+	0x0F120000,
+
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* 3c-- */
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200FB, /* 0EB */
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,
+	0x0F120000,
+	0x0F12A122,
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,
+	0x0F120000,
+	0x002A043A,
+	0x0F120200,
+	0x0F120200,
+	0x002A0494,
+	0x0F120340,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+
+	0x002A0E98,
+	0x0F1202A8,
+	0x002A0E9E,
+	0x0F120298,
+
+	/*1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12007F,
+
+	0xffff000a, /* Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz)*/
+	0x002A01D2,
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps)*/
+	0x002A0242,
+#if 0
+	/*++ 640x480 */
+	/* 0x0F120280, */ /* REG_0TC_PCFG_usWidth */
+	/* 0x0F1201E0, */ /* REG_0TC_PCFG_usHeight */
+	/*-- 640x480 */
+#else
+	/*++ 800x600 */
+	0x0F120320, /* REG_0TC_PCFG_usWidth */
+	0x0F120258, /* REG_0TC_PCFG_usHeight */
+	/*-- 800x600 */
+#endif
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F120535,
+	0x0F12029A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps)*/
+	0x002A0268,
+#if 0
+	/*++ 640x480 */
+	/* 0x0F120280, */ /* REG_1TC_PCFG_usWidth */
+	/* 0x0F1201E0, */ /* REG_1TC_PCFG_usHeight */
+	/*-- 640x480 */
+#else
+	/*++ 800x600 */
+	0x0F120320, /* REG_1TC_PCFG_usWidth */
+	0x0F120258, /* REG_1TC_PCFG_usHeight */
+	/*-- 800x600 */
+#endif
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+
+	/* Apply preview config */
+	/* 0x002A021C, */
+	/* 0x0F120000, */
+	/* 0x002A0220, */
+	/* 0x0F120001, */
+	/* 0x002A01F8, */
+	/* 0x0F120001, */
+	/* 0x002A021E, */
+	/* 0x0F120001, */
+	/* 0x002A01F0, */
+	/* 0x0F120001, */
+	/* 0x0F120001, */
+
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord*/
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+
+	/* param_start	wbt_AwbCcmCord*/
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /*00E0 TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[2]  */
+	0x0F1200F0, /*0100 TVAR_ash_GASAlpha[3]  */
+
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[6]  */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[7]  */
+
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[10] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[11] */
+
+	0x0F1200F8, /*00F8 TVAR_ash_GASAlpha[12] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[13] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[14] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[15] */
+
+	0x0F1200F8, /*00F8 TVAR_ash_GASAlpha[16] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[17] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[18] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[20] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[21] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[22] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[24] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[25] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[26] */
+	0x0F1200F0, /*00E8 TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F1200F8, /* TVAR_ash_GASOutdoorAlpha_3_ */
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120198,
+	0x0F120176,
+	0x0F120140,
+	0x0F12010B,
+	0x0F1200E7,
+	0x0F1200D0,
+	0x0F1200C6,
+	0x0F1200CE,
+	0x0F1200E4,
+	0x0F120109,
+	0x0F12013A,
+	0x0F12016D,
+	0x0F120199,
+	0x0F120175,
+	0x0F12013C,
+	0x0F120105,
+	0x0F1200D3,
+	0x0F1200AC,
+	0x0F120093,
+	0x0F12008A,
+	0x0F120091,
+	0x0F1200AA,
+	0x0F1200D0,
+	0x0F120102,
+	0x0F12013E,
+	0x0F120171,
+	0x0F12014F,
+	0x0F12010C,
+	0x0F1200CF,
+	0x0F12009A,
+	0x0F120070,
+	0x0F120055,
+	0x0F12004C,
+	0x0F120055,
+	0x0F12006F,
+	0x0F12009A,
+	0x0F1200CF,
+	0x0F12010E,
+	0x0F12014D,
+	0x0F120130,
+	0x0F1200E9,
+	0x0F1200A7,
+	0x0F120070,
+	0x0F120045,
+	0x0F12002A,
+	0x0F120020,
+	0x0F12002A,
+	0x0F120045,
+	0x0F120071,
+	0x0F1200AA,
+	0x0F1200E8,
+	0x0F12012E,
+	0x0F12011C,
+	0x0F1200D7,
+	0x0F120091,
+	0x0F120057,
+	0x0F12002D,
+	0x0F120012,
+	0x0F12000A,
+	0x0F120013,
+	0x0F12002F,
+	0x0F12005B,
+	0x0F120094,
+	0x0F1200D6,
+	0x0F120119,
+	0x0F120116,
+	0x0F1200D0,
+	0x0F12008C,
+	0x0F12004F,
+	0x0F120024,
+	0x0F12000A,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120027,
+	0x0F120054,
+	0x0F120090,
+	0x0F1200D1,
+	0x0F120113,
+	0x0F12011D,
+	0x0F1200D7,
+	0x0F120095,
+	0x0F120057,
+	0x0F12002B,
+	0x0F120011,
+	0x0F120008,
+	0x0F120012,
+	0x0F120030,
+	0x0F12005C,
+	0x0F120099,
+	0x0F1200DA,
+	0x0F12011D,
+	0x0F120133,
+	0x0F1200EF,
+	0x0F1200AC,
+	0x0F12006F,
+	0x0F120043,
+	0x0F120028,
+	0x0F12001F,
+	0x0F12002A,
+	0x0F120047,
+	0x0F120077,
+	0x0F1200B1,
+	0x0F1200F2,
+	0x0F120135,
+	0x0F120153,
+	0x0F120113,
+	0x0F1200D2,
+	0x0F120098,
+	0x0F12006A,
+	0x0F12004E,
+	0x0F120046,
+	0x0F120053,
+	0x0F120070,
+	0x0F12009E,
+	0x0F1200D7,
+	0x0F120117,
+	0x0F120155,
+	0x0F12017B,
+	0x0F120141,
+	0x0F120100,
+	0x0F1200C9,
+	0x0F1200A0,
+	0x0F120086,
+	0x0F120080,
+	0x0F12008A,
+	0x0F1200A5,
+	0x0F1200CF,
+	0x0F120108,
+	0x0F120144,
+	0x0F12017B,
+	0x0F12019F,
+	0x0F120171,
+	0x0F120133,
+	0x0F1200FC,
+	0x0F1200D5,
+	0x0F1200BC,
+	0x0F1200B5,
+	0x0F1200BF,
+	0x0F1200D8,
+	0x0F120105,
+	0x0F12013A,
+	0x0F12016F,
+	0x0F12019D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120100,
+	0x0F1200EC,
+	0x0F1200C4,
+	0x0F1200A2,
+	0x0F120089,
+	0x0F12007C,
+	0x0F12007A,
+	0x0F120082,
+	0x0F120094,
+	0x0F1200B0,
+	0x0F1200D5,
+	0x0F120102,
+	0x0F120124,
+	0x0F1200E9,
+	0x0F1200BF,
+	0x0F12009C,
+	0x0F12007F,
+	0x0F120068,
+	0x0F12005A,
+	0x0F120057,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008A,
+	0x0F1200AF,
+	0x0F1200DC,
+	0x0F120109,
+	0x0F1200D1,
+	0x0F12009E,
+	0x0F120077,
+	0x0F12005B,
+	0x0F120044,
+	0x0F120036,
+	0x0F120031,
+	0x0F12003A,
+	0x0F12004D,
+	0x0F120068,
+	0x0F12008B,
+	0x0F1200B6,
+	0x0F1200E7,
+	0x0F1200BC,
+	0x0F120088,
+	0x0F12005E,
+	0x0F12003F,
+	0x0F120029,
+	0x0F12001B,
+	0x0F120016,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004D,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200AF,
+	0x0F12007C,
+	0x0F120050,
+	0x0F120030,
+	0x0F12001B,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000E,
+	0x0F120021,
+	0x0F120039,
+	0x0F12005C,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200AA,
+	0x0F120079,
+	0x0F12004E,
+	0x0F12002C,
+	0x0F120014,
+	0x0F120005,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120031,
+	0x0F120053,
+	0x0F120079,
+	0x0F1200A9,
+	0x0F1200AD,
+	0x0F12007F,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001A,
+	0x0F12000A,
+	0x0F120004,
+	0x0F12000B,
+	0x0F12001B,
+	0x0F120031,
+	0x0F120052,
+	0x0F120078,
+	0x0F1200A6,
+	0x0F1200BB,
+	0x0F12008D,
+	0x0F120065,
+	0x0F120042,
+	0x0F120029,
+	0x0F12001A,
+	0x0F120015,
+	0x0F12001A,
+	0x0F120028,
+	0x0F120040,
+	0x0F12005D,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200D5,
+	0x0F1200A7,
+	0x0F12007E,
+	0x0F12005E,
+	0x0F120043,
+	0x0F120033,
+	0x0F12002E,
+	0x0F120033,
+	0x0F120040,
+	0x0F120056,
+	0x0F120073,
+	0x0F120099,
+	0x0F1200C8,
+	0x0F1200F5,
+	0x0F1200C8,
+	0x0F12009E,
+	0x0F12007F,
+	0x0F120067,
+	0x0F120058,
+	0x0F120056,
+	0x0F120058,
+	0x0F120062,
+	0x0F120074,
+	0x0F120092,
+	0x0F1200B9,
+	0x0F1200E4,
+	0x0F120113,
+	0x0F1200ED,
+	0x0F1200C3,
+	0x0F1200A1,
+	0x0F12008A,
+	0x0F12007A,
+	0x0F120074,
+	0x0F120077,
+	0x0F120081,
+	0x0F120097,
+	0x0F1200B6,
+	0x0F1200DA,
+	0x0F120102,
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200F2, /*0F2*/
+	0x0F120148, /*148*/
+	0x0F12018E, /*18A*/
+	0x0F1201F6,
+	0x0F12024A,
+	0x0F1202CC,
+	0x0F120338,
+	0x0F12038C,
+	0x0F1203C6,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200F2, /*0F2*/
+	0x0F120148, /*148*/
+	0x0F12018E, /*18A*/
+	0x0F1201F6,
+	0x0F12024A,
+	0x0F1202CC,
+	0x0F120338,
+	0x0F12038C,
+	0x0F1203C6,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200F2, /*0F2*/
+	0x0F120148, /*148*/
+	0x0F12018E, /*18A*/
+	0x0F1201F6,
+	0x0F12024A,
+	0x0F1202CC,
+	0x0F120338,
+	0x0F12038C,
+	0x0F1203C6,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F1203B4, /*03B4 038F awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F1203BE, /*03C0 039B awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F12039A, /*037C 0373 awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203C4, /*03C8 03B0 awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F12037C, /*035E 0352 awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203C8, /*03C8 03B7 awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F12035E, /*0340 0334 awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203C0, /*03C0 03B5 awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120344, /*0328 0318 awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203AC, /*03B0 03B0 awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F12032A, /*0310 02FF awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F120394, /*039E 038D awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F12030E, /*02FA 02E7 awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120378, /*0384 0372 awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202F6, /*02DC 02D0 awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035C, /*036C 035D awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202DC, /*02CA 02B5 awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120344, /*035A 0345 awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202C6, /*02B4 02A1 awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F12032A, /*0340 0331 awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F1202B0, /*029E 028B awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12030E, /*0324 031E awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120298, /*028C 0273 awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F1202F8, /*0306 0309 awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F120286, /*027A 025F awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202E2, /*02F6 02F5 awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120270, /*026A 0250 awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202D0, /*02E4 02DB awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F12025E, /*025A 0241 awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202BC, /*02DA 02C7 awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F12024A, /*024C 0233 awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202AC, /*02CE 02B9 awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120238, /*023A 0223 awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202A0, /*02C4 02AB awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120226, /*0230 0217 awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F12029A, /*02B8 02A2 awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120214, /*0220 0207 awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120296, /*02AC 0294 awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F120202, /*0212 01FA awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120294, /*02AA 0289 awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201F4, /*0204 01EA awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120290, /*02A6 0281 awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201E6, /*01FA 01DD awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12028A, /*02A0 027B awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D8, /*01EE 01D0 awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120288, /*029C 0273 awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201CA, /*01E0 01C3 awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12027E, /*0294 026A awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201C0, /*01D4 01B6 awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120274, /*028A 0265 awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201B2, /*01C8 01AB awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12026C, /*0282 025B awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201AA, /*01C0 01A1 awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120264, /*027A 0254 awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F1201A6, /*01BC 0198 awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12025C, /*0272 024B awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F1201A2, /*01B8 0192 awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F12024C, /*0262 0242 awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F1201A8, /*01BC 0191 awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F120238, /*024E 023A awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F1201D6, /*01EC 0192 awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F1201F0, /*0206 0222 awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /*0000 01C5 awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /*0000 01DF awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001F,
+	0x0F120000,
+	0x0F120108,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F12025E, /*025E*/
+	0x0F120282, /*0282*/
+	0x0F120246, /*0240*/
+	0x0F12029E, /*0298*/
+	0x0F120230, /*022A*/
+	0x0F1202A0, /*029A*/
+	0x0F120220, /*021A*/
+	0x0F1202A0, /*029A*/
+	0x0F12020E, /*0206*/
+	0x0F12029E, /*0298*/
+	0x0F120206, /*01FE*/
+	0x0F120292, /*028C*/
+	0x0F120200, /*01FA*/
+	0x0F12027E, /*0278*/
+	0x0F1201FE, /*01F8*/
+	0x0F12026A, /*0266*/
+	0x0F12021A, /*0214*/
+	0x0F12023E, /*0238*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* param_WRITE 70000CC6 */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120208,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end*/
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__2_       */
+	0x0F12001E, /*0014 awbb_GridCorr_R_0__3_       */
+	0x0F120000, /*0000 awbb_GridCorr_R_0__4_       */
+	0x0F120082, /*005A awbb_GridCorr_R_0__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__2_       */
+	0x0F12001E, /*0014 awbb_GridCorr_R_1__3_       */
+	0x0F120000, /*0000 awbb_GridCorr_R_1__4_       */
+	0x0F120082, /*005A awbb_GridCorr_R_1__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__2_       */
+	0x0F12001E, /*0014 awbb_GridCorr_R_2__3_       */
+	0x0F120000, /*0000 awbb_GridCorr_R_2__4_       */
+	0x0F120082, /*005A awbb_GridCorr_R_2__5_       */
+
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_0__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_0__1_     */
+	0x0F12001E, /*001E awbb_GridCorr_B_0__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__3_     */
+	0x0F12FF88, /*FF88 awbb_GridCorr_B_0__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_0__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_1__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_1__1_     */
+	0x0F12001E, /*001E awbb_GridCorr_B_1__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__3_     */
+	0x0F12FF88, /*FF88 awbb_GridCorr_B_1__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_1__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_2__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_2__1_     */
+	0x0F12001E, /*001E awbb_GridCorr_B_2__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__3_     */
+	0x0F12FF88, /*FF88 awbb_GridCorr_B_2__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_2__5_     */
+
+	0x0F1202EA, /*awbb_GridConst_1_0_    */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F120388, /*awbb_GridConst_1_2_    */
+	          
+	0x0F121032, /* 1032 awbb_GridConst_2_0    */
+	0x0F1210B2, /* 10B2 awbb_GridConst_2_1    */
+	0x0F121140, /* 1160 awbb_GridConst_2_2    */
+	0x0F121141, /* 1161 awbb_GridConst_2_3    */
+	0x0F1211BE, /* 11BE awbb_GridConst_2_4    */
+	0x0F12124C, /* 124C awbb_GridConst_2_5    */
+
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,  /*--- 52A awbb_MvEq_RBthresh */
+
+	/* Gamut Thresholds */
+	0x002A0DAA,
+	0x0F120664, /*--- 71A */
+	0x0F120355, /*--- 3A4 */
+	0x002A0DAE,
+	0x0F12002C, /*--- 36 */
+	0x0F120024, /*--- 1C */
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120E01,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120256, /*-- 256 */
+	0x0F120248, /*-- 248 */
+	0x002A0D96,
+	0x0F120E00,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+	/* awbb_ChromaClassifyEn, default : enable*/
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120258,
+	0x0F120003,
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/*  param_start */
+	0x002A2800,
+	0x0F12010D, /*-0136---*/  /* H */
+	0x0F12FFA7, /*-FF8B---*/
+	0x0F12FFF5, /*-FFE8---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+
+	0x0F12010D, /*-010D---*/  /* A */
+	0x0F12FFA7, /*-FFA7---*/
+	0x0F12FFF5, /*-FFF5---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+
+	0x0F1201EA, /*01E9*/  /* WW */
+	0x0F12FFB9, /*FFAE*/
+	0x0F12FFDB, /*FFE6*/
+	0x0F120127, /*0127*/
+	0x0F120109, /*0109*/
+	0x0F12FF3C, /*FF3C*/
+	0x0F12FF2B, /*FF2B*/
+	0x0F12021B, /*021B*/
+	0x0F12FF48, /*FF48*/
+	0x0F12FF03, /*FF03*/
+	0x0F120207, /*0207*/
+	0x0F120113, /*0113*/
+	0x0F12FFCA, /*FFCA*/
+	0x0F12FF93, /*FF93*/
+	0x0F12016F, /*016F*/
+	0x0F120164, /*0164*/
+	0x0F12FF55, /*FF55*/
+	0x0F120163, /*0163*/
+
+	0x0F1201EA, /*01E9*/  /* CW */
+	0x0F12FFB9, /*FFAE*/
+	0x0F12FFDB, /*FFE6*/
+	0x0F120127, /*0127*/
+	0x0F120109, /*0109*/
+	0x0F12FF3C, /*FF3C*/
+	0x0F12FF2B, /*FF2B*/
+	0x0F12021B, /*021B*/
+	0x0F12FF48, /*FF48*/
+	0x0F12FF03, /*FF03*/
+	0x0F120207, /*0207*/
+	0x0F120113, /*0113*/
+	0x0F12FFCA, /*FFCA*/
+	0x0F12FF93, /*FF93*/
+	0x0F12016F, /*016F*/
+	0x0F120164, /*0164*/
+	0x0F12FF55, /*FF55*/
+	0x0F120163, /*0163*/
+
+	0x0F120194, /*-r018A---*/  /* D50 */
+	0x0F12FFAD, /*-rFFA0---*/
+	0x0F12FFFE, /*-rFFE9---*/
+	0x0F1200C5, /*-y00C5---*/
+	0x0F120103, /*-y0103---*/
+	0x0F12FF5D, /*-yFF5D---*/
+	0x0F12FEE3, /*-gFEFE---*/
+	0x0F1201AE, /*-g021D---*/
+	0x0F12FF27, /*-gFF2C---*/
+	0x0F12FF18, /*- FF18---*/
+	0x0F12018F, /*- 018F---*/
+	0x0F1200C8, /*- 00C8---*/
+	0x0F12FFE8, /*- FFE1---*/
+	0x0F12FFAA, /*- FFA0---*/
+	0x0F1201C8, /*- 01D9---*/
+	0x0F120132, /*- 0132---*/
+	0x0F12FF3E, /*- FF3E---*/
+	0x0F120100, /*- 0100---*/
+
+	0x0F120194, /*-r018A---*/  /* D65 */
+	0x0F12FFAD, /*-rFFA0---*/
+	0x0F12FFFE, /*-rFFE9---*/
+	0x0F1200C5, /*-y00C5---*/
+	0x0F120103, /*-y0103---*/
+	0x0F12FF5D, /*-yFF5D---*/
+	0x0F12FEE3, /*-gFEFE---*/
+	0x0F1201AE, /*-g021D---*/
+	0x0F12FF27, /*-gFF2C---*/
+	0x0F12FF18, /*- FF18---*/
+	0x0F12018F, /*- 018F---*/
+	0x0F1200C8, /*- 00C8---*/
+	0x0F12FFE8, /*- FFE1---*/
+	0x0F12FFAA, /*- FFA0---*/
+	0x0F1201C8, /*- 01D9---*/
+	0x0F120132, /*- 0132---*/
+	0x0F12FF3E, /*- FF3E---*/
+	0x0F120100, /*- 0100---*/
+
+
+	0x0F1201CC, /*--01CC--*/ /* OUT */
+	0x0F12FFC3, /*--FFC3--*/
+	0x0F120009, /*--0009--*/
+	0x0F1200A2, /*--009D--*/
+	0x0F120106, /*--00FA--*/
+	0x0F12FF3F, /*--FF50--*/
+	0x0F12FED8, /*--FED8--*/
+	0x0F1201FE, /*--01FE--*/
+	0x0F12FF08, /*--FF08--*/
+	0x0F12FEC7, /*--FEC7--*/
+	0x0F1200F5, /*--00F5--*/
+	0x0F120119, /*--0119--*/
+	0x0F12FFDF, /*--FFDF--*/
+	0x0F120024, /*--0024--*/
+	0x0F1201A8, /*--01A8--*/
+	0x0F120170, /*--0170--*/
+	0x0F12FFAD, /*--FFAD--*/
+	0x0F12011B, /*--011B--*/
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+
+	/* param_start SARR_uNormBrInDoor*/
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+	/* param_start SARR_uNormBrOutDoor */
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120004, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120012, /*  RGB2YUV_iYOffset                                                  */
+
+	0x002A08AA, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120009, /*  RGB2YUV_iYOffset                                                  */
+
+	0x002A0928, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x002A09A6, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x002A0A24, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x002A0AA2, /* --                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001,
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+	/* END of Initial*/
+};
+
+/* Set-data based on SKT VT standard ,when using 3G network */
+/* 8fps */
+static const u32 s5k5bafx_vt_common[] =
+{
+	/* SKT-VT - continuous*/
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* Delay */
+	
+	
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1201F4, /*--*/ 
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	
+	0x0F120015,
+	
+	
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting   sunkyu start */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003c, /* --- */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200FB, /* 0EB */
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F124074,
+	0x0F120000,
+	0x002A048C,
+	0x0F1280E8,
+	0x0F120000,
+	0x0F12A604,
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,
+	0x0F120000,
+	0x002A043A,
+	0x0F120200, /* p-gain */
+	0x0F120200,
+	0x002A0494,
+	0x0F120300, /* c-gain */
+	0x0F120600, /* 600 */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+	
+	0x002A0E98,
+	0x0F1202B0,
+	0x002A0E9E,
+	0x0F120290,
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12007F,
+	
+	0xffff000a, /* Wait10mSec */
+	
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+	
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052, /*--*/
+	0x0F120001,
+	0x0F120000, /*-0-*/
+	0x0F120000, /*-0-*/
+	0x0F1204E2, /*-535-*/
+	0x0F1204E2, /*-29A-*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+	
+	/* Apply preview config */
+	/* 0x002A021C, */
+	/* 0x0F120000, */
+	/* 0x002A0220, */
+	/* 0x0F120001, */
+	/* 0x002A01F8, */
+	/* 0x0F120001, */
+	/* 0x002A021E, */
+	/* 0x0F120001, */
+	/* 0x002A01F0, */
+	/* 0x0F120001, */
+	/* 0x0F120001, */
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F1204E2,
+	0x0F1204E2,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200E0,
+	0x0F120110,
+	0x0F120128,
+	0x0F120140,
+	0x0F12015E,
+	0x0F120190,
+	0x0F1201B0,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200E0,
+	0x0F120110,
+	0x0F120128,
+	0x0F120140,
+	0x0F12015E,
+	0x0F120190,
+
+
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /*00E0 TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[2]  */
+	0x0F1200F0, /*0100 TVAR_ash_GASAlpha[3]  */
+	
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[6]  */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[7]  */
+	
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[10] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[11] */
+	
+	0x0F1200F8, /*00F8 TVAR_ash_GASAlpha[12] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[13] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[14] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /*00F8 TVAR_ash_GASAlpha[16] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[17] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[18] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[20] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[21] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[22] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[24] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[25] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[26] */
+	0x0F1200F0, /*00E8 TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120198,
+	0x0F120176,
+	0x0F120140,
+	0x0F12010B,
+	0x0F1200E7,
+	0x0F1200D0,
+	0x0F1200C6,
+	0x0F1200CE,
+	0x0F1200E4,
+	0x0F120109,
+	0x0F12013A,
+	0x0F12016D,
+	0x0F120199,
+	0x0F120175,
+	0x0F12013C,
+	0x0F120105,
+	0x0F1200D3,
+	0x0F1200AC,
+	0x0F120093,
+	0x0F12008A,
+	0x0F120091,
+	0x0F1200AA,
+	0x0F1200D0,
+	0x0F120102,
+	0x0F12013E,
+	0x0F120171,
+	0x0F12014F,
+	0x0F12010C,
+	0x0F1200CF,
+	0x0F12009A,
+	0x0F120070,
+	0x0F120055,
+	0x0F12004C,
+	0x0F120055,
+	0x0F12006F,
+	0x0F12009A,
+	0x0F1200CF,
+	0x0F12010E,
+	0x0F12014D,
+	0x0F120130,
+	0x0F1200E9,
+	0x0F1200A7,
+	0x0F120070,
+	0x0F120045,
+	0x0F12002A,
+	0x0F120020,
+	0x0F12002A,
+	0x0F120045,
+	0x0F120071,
+	0x0F1200AA,
+	0x0F1200E8,
+	0x0F12012E,
+	0x0F12011C,
+	0x0F1200D7,
+	0x0F120091,
+	0x0F120057,
+	0x0F12002D,
+	0x0F120012,
+	0x0F12000A,
+	0x0F120013,
+	0x0F12002F,
+	0x0F12005B,
+	0x0F120094,
+	0x0F1200D6,
+	0x0F120119,
+	0x0F120116,
+	0x0F1200D0,
+	0x0F12008C,
+	0x0F12004F,
+	0x0F120024,
+	0x0F12000A,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120027,
+	0x0F120054,
+	0x0F120090,
+	0x0F1200D1,
+	0x0F120113,
+	0x0F12011D,
+	0x0F1200D7,
+	0x0F120095,
+	0x0F120057,
+	0x0F12002B,
+	0x0F120011,
+	0x0F120008,
+	0x0F120012,
+	0x0F120030,
+	0x0F12005C,
+	0x0F120099,
+	0x0F1200DA,
+	0x0F12011D,
+	0x0F120133,
+	0x0F1200EF,
+	0x0F1200AC,
+	0x0F12006F,
+	0x0F120043,
+	0x0F120028,
+	0x0F12001F,
+	0x0F12002A,
+	0x0F120047,
+	0x0F120077,
+	0x0F1200B1,
+	0x0F1200F2,
+	0x0F120135,
+	0x0F120153,
+	0x0F120113,
+	0x0F1200D2,
+	0x0F120098,
+	0x0F12006A,
+	0x0F12004E,
+	0x0F120046,
+	0x0F120053,
+	0x0F120070,
+	0x0F12009E,
+	0x0F1200D7,
+	0x0F120117,
+	0x0F120155,
+	0x0F12017B,
+	0x0F120141,
+	0x0F120100,
+	0x0F1200C9,
+	0x0F1200A0,
+	0x0F120086,
+	0x0F120080,
+	0x0F12008A,
+	0x0F1200A5,
+	0x0F1200CF,
+	0x0F120108,
+	0x0F120144,
+	0x0F12017B,
+	0x0F12019F,
+	0x0F120171,
+	0x0F120133,
+	0x0F1200FC,
+	0x0F1200D5,
+	0x0F1200BC,
+	0x0F1200B5,
+	0x0F1200BF,
+	0x0F1200D8,
+	0x0F120105,
+	0x0F12013A,
+	0x0F12016F,
+	0x0F12019D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120100,
+	0x0F1200EC,
+	0x0F1200C4,
+	0x0F1200A2,
+	0x0F120089,
+	0x0F12007C,
+	0x0F12007A,
+	0x0F120082,
+	0x0F120094,
+	0x0F1200B0,
+	0x0F1200D5,
+	0x0F120102,
+	0x0F120124,
+	0x0F1200E9,
+	0x0F1200BF,
+	0x0F12009C,
+	0x0F12007F,
+	0x0F120068,
+	0x0F12005A,
+	0x0F120057,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008A,
+	0x0F1200AF,
+	0x0F1200DC,
+	0x0F120109,
+	0x0F1200D1,
+	0x0F12009E,
+	0x0F120077,
+	0x0F12005B,
+	0x0F120044,
+	0x0F120036,
+	0x0F120031,
+	0x0F12003A,
+	0x0F12004D,
+	0x0F120068,
+	0x0F12008B,
+	0x0F1200B6,
+	0x0F1200E7,
+	0x0F1200BC,
+	0x0F120088,
+	0x0F12005E,
+	0x0F12003F,
+	0x0F120029,
+	0x0F12001B,
+	0x0F120016,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004D,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200AF,
+	0x0F12007C,
+	0x0F120050,
+	0x0F120030,
+	0x0F12001B,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000E,
+	0x0F120021,
+	0x0F120039,
+	0x0F12005C,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200AA,
+	0x0F120079,
+	0x0F12004E,
+	0x0F12002C,
+	0x0F120014,
+	0x0F120005,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120031,
+	0x0F120053,
+	0x0F120079,
+	0x0F1200A9,
+	0x0F1200AD,
+	0x0F12007F,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001A,
+	0x0F12000A,
+	0x0F120004,
+	0x0F12000B,
+	0x0F12001B,
+	0x0F120031,
+	0x0F120052,
+	0x0F120078,
+	0x0F1200A6,
+	0x0F1200BB,
+	0x0F12008D,
+	0x0F120065,
+	0x0F120042,
+	0x0F120029,
+	0x0F12001A,
+	0x0F120015,
+	0x0F12001A,
+	0x0F120028,
+	0x0F120040,
+	0x0F12005D,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200D5,
+	0x0F1200A7,
+	0x0F12007E,
+	0x0F12005E,
+	0x0F120043,
+	0x0F120033,
+	0x0F12002E,
+	0x0F120033,
+	0x0F120040,
+	0x0F120056,
+	0x0F120073,
+	0x0F120099,
+	0x0F1200C8,
+	0x0F1200F5,
+	0x0F1200C8,
+	0x0F12009E,
+	0x0F12007F,
+	0x0F120067,
+	0x0F120058,
+	0x0F120056,
+	0x0F120058,
+	0x0F120062,
+	0x0F120074,
+	0x0F120092,
+	0x0F1200B9,
+	0x0F1200E4,
+	0x0F120113,
+	0x0F1200ED,
+	0x0F1200C3,
+	0x0F1200A1,
+	0x0F12008A,
+	0x0F12007A,
+	0x0F120074,
+	0x0F120077,
+	0x0F120081,
+	0x0F120097,
+	0x0F1200B6,
+	0x0F1200DA,
+	0x0F120102,
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F120324, /*0324  0324  awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F120330, /*0330  0330  awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F12030E, /*030E  030E  awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F120330, /*0330  0330  awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F1202EE, /*02EE  02EE  awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F120330, /*0330  0330  awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F1202D0, /*02D0  02D0  awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F120340, /*0340  0340  awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F1202B8, /*02B8  02B8  awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F120344, /*0344  0336  awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202A2, /*02A2  02A2  awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F120332, /*0328  031A  awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F12028A, /*028A  028A  awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120312, /*02FE  02F4  awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F120278, /*0278  0278  awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F1202F2, /*02D6  02D6  awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F120260, /*0260  0260  awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F1202CC, /*02C2  02C2  awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F120250, /*0250  0250  awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F1202AE, /*02AE  02AE  awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12023C, /*023C  023C  awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12029E, /*029E  029E  awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F12022A, /*022A  022A  awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120292, /*0292  0292  awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F120218, /*0218  0218  awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F120288, /*0288  0288  awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120206, /*0206  0206  awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F120282, /*0282  0282  awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F1201F4, /*01F4  01F4  awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F120280, /*0280  0280  awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F1201E6, /*01E6  01E6  awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F12027C, /*027C  027C  awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F1201D8, /*01D8  01D8  awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F12027A, /*027A  027A  awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F1201C8, /*01C8  01C8  awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F120274, /*0274  0274  awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F1201BC, /*01BC  01BC  awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120270, /*0270  0270  awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201B2, /*01B2  01B2  awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120266, /*0266  0266  awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201A4, /*01A4  01A4  awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F12025E, /*025E  025E  awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F12019C, /*019C  019C  awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F120256, /*0256  0256  awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F120198, /*0198  0198  awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F12024E, /*024E  024E  awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F120192, /*0192  0192  awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12023E, /*023E  023E  awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F120198, /*0198  0198  awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F12022A, /*022A  022A  awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201C6, /*01C6  01C6  awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F1201E0, /*01E0  01E0  awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /*0000  0000  awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /*0000  0000 awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /*0000  0000 awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /*0000  0000 awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /*0000  0000 awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001A, /*--1F--*/
+	0x0F120000,
+	0x0F120158, /*--108--*/
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /*025E*/
+	0x0F120282, /*0282*/
+	0x0F120246, /*0240*/
+	0x0F12029E, /*0298*/
+	0x0F120230, /*022A*/
+	0x0F1202A0, /*029A*/
+	0x0F120220, /*021A*/
+	0x0F1202A0, /*029A*/
+	0x0F12020E, /*0206*/
+	0x0F12029E, /*0298*/
+	0x0F120206, /*01FE*/
+	0x0F120292, /*028C*/
+	0x0F120200, /*01FA*/
+	0x0F12027E, /*0278*/
+	0x0F1201FE, /*01F8*/
+	0x0F12026A, /*0266*/
+	0x0F12021A, /*0214*/
+	0x0F12023E, /*0238*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120208,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F1202FC, /*031F awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120340, /*0495 awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202D8, /*02FC awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120344, /*0495 awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202B6, /*02D9 awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F12034A, /*0495 awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F120292, /*02B6 awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F12034E, /*0495 awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120270, /*0293 awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120354, /*0495 awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F12024E, /*0270 awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120358, /*0495 awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12022A, /*024E awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F12035E, /*0495 awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F120208, /*022B awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120364, /*0495 awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F1201E4, /*0208 awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F120368, /*048A awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201C2, /*01E5 awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F12036E, /*0455 awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F12019E, /*01C2 awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F120372, /*041F awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12017C, /*019F awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F120378, /*03EA awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12015A, /*017D awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F12037E, /*03B4 awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F120136, /*015A awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F120348, /*037F awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120130, /*0137 awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120314, /*0349 awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F12012E, /*0130 awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F1202DE, /*0314 awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012E, /*012F awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202B0, /*02DE awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012E, /*012F awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F12028A, /*02B1 awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012C, /*012E awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F120264, /*028B awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012C, /*012D awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F12023E, /*0265 awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /*012C awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F120218, /*023F awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012A, /*012C awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F1201F2, /*0219 awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012A, /*012B awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201CC, /*01F3 awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F120000, /*012A awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F120000, /*01CD awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /*0000 awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /*0000 awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120017, /*18 */
+	0x0F120000,
+	0x0F1200CE, /* AF */
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	/* Duks add*/
+	0x002A0D8C,
+	0x0F120065, /* awbb_GridEnable */
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__0_       */
+	0x0F12FFCE, /*FFCE awbb_GridCorr_R_0__1_       */
+	0x0F120078, /*00A0 awbb_GridCorr_R_0__2_       */
+	0x0F12FFEC, /*0014 awbb_GridCorr_R_0__3_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__4_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__0_       */
+	0x0F12FFCE, /*FFCE awbb_GridCorr_R_1__1_       */
+	0x0F120078, /*00A0 awbb_GridCorr_R_1__2_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__3_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__4_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__0_       */
+	0x0F12FFCE, /*FFCE awbb_GridCorr_R_2__1_       */
+	0x0F120078, /*00A0 awbb_GridCorr_R_2__2_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__3_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__4_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__5_       */
+	
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_0__0_     */
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_0__1_     */
+	0x0F12FF38, /*FF38 awbb_GridCorr_B_0__2_     */
+	0x0F12FFD8, /*0000 awbb_GridCorr_B_0__3_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_0__4_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_0__5_     */
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_1__0_     */
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_1__1_     */
+	0x0F12FF38, /*FF38 awbb_GridCorr_B_1__2_     */
+	0x0F12FFD8, /*0000 awbb_GridCorr_B_1__3_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_1__4_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_1__5_     */
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_2__0_     */
+	0x0F12FFF4, /*FFF4 awbb_GridCorr_B_2__1_     */
+	0x0F12FF38, /*FF38 awbb_GridCorr_B_2__2_     */
+	0x0F12FFD8, /*0000 awbb_GridCorr_B_2__3_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_2__4_     */
+	0x0F120000, /*0000 awbb_GridCorr_B_2__5_     */
+	
+	0x0F1202EA,  /*02EA awbb_GridConst_1_0_    */
+	0x0F120335,  /*0335 awbb_GridConst_1_1_    */
+	0x0F120388,  /*0388 awbb_GridConst_1_2_    */
+	
+	0x0F121009,  /*1009 1009 1009 awbb_GridConst_2_0    */
+	0x0F1210C8,  /*10C8 10C8 10B3 awbb_GridConst_2_1    */
+	0x0F121135,  /*1135 1117 10FF awbb_GridConst_2_2    */
+	0x0F121156,  /*1163 1141 1120 awbb_GridConst_2_3    */
+	0x0F12118C,  /*118C 115D 115D awbb_GridConst_2_4    */
+	0x0F1211BE,  /*11BE 11BE 11BE awbb_GridConst_2_5    */
+	
+	0x0F1200B3,  /*00B3 awbb_GridCoeff_R_1    */
+	0x0F1200B7,  /*00B7 awbb_GridCoeff_B_1    */
+	0x0F1200D3,  /*00D3 awbb_GridCoeff_R_2    */
+	0x0F120091,  /*0091 awbb_GridCoeff_B_2    */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133, /* 133        0131 */
+	0x0F12010F, /* 10F        0128 */
+	0x002A0D74,
+	0x0F12052A, /*F5A*/  /*--- 52A awbb_MvEq_RBthresh */
+	
+	/* Gamut Thresholds */
+	0x002A0DAA,
+	0x0F120664, /*--- 71A */
+	0x0F120355, /*--- 3A4 */
+	0x002A0DAE,
+	0x0F12002C, /*--- 36 */
+	0x0F120024, /*--- 1C */
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120E01,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120256, /*-- 256 */
+	0x0F120248, /*-- 248 */
+	0x002A0D96,
+	0x0F120E00,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120026, /*32 darkBr */
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120258, 
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F1201CD, /*-0149---*/  /* H */
+	0x0F12FF86, /*-FF79---*/
+	0x0F12FFEC, /*-FFE6---*/
+	0x0F1200F3, /*-006E---*/
+	0x0F1200E3, /*-00E5---*/
+	0x0F12FF31, /*-FF0F---*/
+	0x0F12FF5F, /*-FF21---*/
+	0x0F1201E9, /*-01E2---*/
+	0x0F12FF30, /*-FF20---*/
+	0x0F12FED6, /*-FEED---*/
+	0x0F1201D3, /*-0198---*/
+	0x0F1200F4, /*-0198---*/
+	0x0F12FFDC, /*-FF95---*/
+	0x0F12FFA9, /*-FFA3---*/
+	0x0F1201A6, /*-0260---*/
+	0x0F120139, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F120139, /*-00F4---*/
+	
+	0x0F1201CD, /*-0149---*/  /* A */
+	0x0F12FF86, /*-FF79---*/
+	0x0F12FFEC, /*-FFE6---*/
+	0x0F1200F3, /*-006E---*/
+	0x0F1200E3, /*-00E5---*/
+	0x0F12FF31, /*-FF0F---*/
+	0x0F12FF5F, /*-FF21---*/
+	0x0F1201E9, /*-01E2---*/
+	0x0F12FF30, /*-FF20---*/
+	0x0F12FED6, /*-FEED---*/
+	0x0F1201D3, /*-0198---*/
+	0x0F1200F4, /*-0198---*/
+	0x0F12FFDC, /*-FF95---*/
+	0x0F12FFA9, /*-FFA3---*/
+	0x0F1201A6, /*-0260---*/
+	0x0F120139, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F120139, /*-00F4---*/
+	
+	0x0F1201DB, /*-0205   01A5*/  /* WW */
+	0x0F12FF94, /*-FF92   FF9D*/
+	0x0F12FFFA, /*-FFE6   FFE1*/
+	0x0F1200F3, /*-00FE   00D9*/
+	0x0F1200E3, /*-00E2   0153*/
+	0x0F12FF31, /*-FF33   FF25*/
+	0x0F12FF43, /*-FF1E   FF25*/
+	0x0F1201E9, /*-0222   028C*/
+	0x0F12FF4B, /*-FF68   FF25*/
+	0x0F12FED6, /*-FF03   FEBF*/
+	0x0F1201D3, /*-0207   01B6*/
+	0x0F1200F4, /*-0113   00F7*/
+	0x0F12FFDC, /*-FFE3   FF81*/
+	0x0F12FFA9, /*-FFC0   FF8C*/
+	0x0F1201A6, /*-0181   01AE*/
+	0x0F120139, /*-0164   00FC*/
+	0x0F12FF33, /*-FF55   FF48*/
+	0x0F120139, /*-0163   010D*/
+	
+	0x0F1201DB, /*-0205  01BD*/  /* CW */
+	0x0F12FF94, /*-FF92  FF89*/
+	0x0F12FFFA, /*-FFE6  FFDE*/
+	0x0F1200F3, /*-00FE  0098*/
+	0x0F1200E3, /*-00E2  00B8*/
+	0x0F12FF31, /*-FF33  FF69*/
+	0x0F12FF43, /*-FF1E  FF15*/
+	0x0F1201E9, /*-0222  025A*/
+	0x0F12FF4B, /*-FF68  FF65*/
+	0x0F12FED6, /*-FF03  FF03*/
+	0x0F1201D3, /*-0207  0207*/
+	0x0F1200F4, /*-0113  0113*/
+	0x0F12FFDC, /*-FFE3  FFDA*/
+	0x0F12FFA9, /*-FFC0  FFB8*/
+	0x0F1201A6, /*-0181  0166*/
+	0x0F120139, /*-0164  0164*/
+	0x0F12FF33, /*-FF55  FF55*/
+	0x0F120139, /*-0163  0163*/
+	
+	0x0F1201CD, /*-014D---*/  /* D50 */
+	0x0F12FFAB, /*-FFAA---*/
+	0x0F12FFF3, /*-FFF0---*/
+	0x0F1200DC, /*-00C5---*/
+	0x0F12011F, /*-0103---*/
+	0x0F12FF57, /*-FF5D---*/
+	0x0F12FF3D, /*-FF3D---*/
+	0x0F1201F6, /*-01F6---*/
+	0x0F12FF58, /*-FF58---*/
+	0x0F12FF18, /*-FF18---*/
+	0x0F12018F, /*-018F---*/
+	0x0F1200C8, /*-00C8---*/
+	0x0F12FFEC, /*-FFEC---*/
+	0x0F12FFAB, /*-FFAB---*/
+	0x0F1201E4, /*-01E4---*/
+	0x0F120132, /*-0132---*/
+	0x0F12FF3E, /*-FF3E---*/
+	0x0F120100, /*-0100---*/
+	
+	0x0F1201CD, /*-014D 018A---*/  /* D65 */   
+	0x0F12FFAB, /*-FFAA FFC1---*/
+	0x0F12FFF3, /*-FFF0 FFF5---*/
+	0x0F1200DC, /*-00C5 0086---*/
+	0x0F12011F, /*-0103 00D2---*/
+	0x0F12FF57, /*-FF5D FF73---*/
+	0x0F12FF3D, /*-FF3D FF0B---*/
+	0x0F1201F6, /*-01F6 0232---*/
+	0x0F12FF58, /*-FF58 FF49---*/
+	0x0F12FF18, /*-FF18 FF43---*/
+	0x0F12018F, /*-018F 01BA---*/
+	0x0F1200C8, /*-00C8 00F3---*/
+	0x0F12FFEC, /*-FFEC FFE2---*/
+	0x0F12FFAB, /*-FFAB FFB6---*/
+	0x0F1201E4, /*-01E4 01E6---*/
+	0x0F120132, /*-0132 018F---*/
+	0x0F12FF3E, /*-FF3E FF8C---*/
+	0x0F120100, /*-0100 0137---*/
+	
+	0x0F1201CC, /*--01CC--*/ /* OUT */
+	0x0F12FFC3, /*--FFC3--*/
+	0x0F120009, /*--0009--*/
+	0x0F1200A2, /*--009D--*/
+	0x0F120106, /*--00FA--*/
+	0x0F12FF3F, /*--FF50--*/
+	0x0F12FED8, /*--FED8--*/
+	0x0F1201FE, /*--01FE--*/
+	0x0F12FF08, /*--FF08--*/
+	0x0F12FEC7, /*--FEC7--*/
+	0x0F1200F5, /*--00F5--*/
+	0x0F120119, /*--0119--*/
+	0x0F12FFDF, /*--FFDF--*/
+	0x0F120024, /*--0024--*/
+	0x0F1201A8, /*--01A8--*/
+	0x0F120170, /*--0170--*/
+	0x0F12FFAD, /*--FFAD--*/
+	0x0F12011B, /*--011B--*/
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F120010,
+	0x0F12001E,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F120010,
+	0x0F12001E,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+	
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+
+	
+	/* param_start	TVAR_afit_pBaseVals */
+	0x002A082C,
+	0x0F12000E, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803c, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120038, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A08AA, /* --                                                         */
+	0x0F120006, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120114, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F121014, /* -- "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F121014, /* -- "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /*--  RGB2YUV_iYOffset                                                  */
+	
+	0x002A0928, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12200F, /* -- "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12200F, /* -- "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x002A09A6, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F12000F, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F12000A, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F12080F, /* -- "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F120508, /* -- "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12200A, /* -- "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12200A, /* -- "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x002A0A24, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                    */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120002, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120002, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F12020F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F120502, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122005, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122005, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x002A0AA2, /* --                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001,
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+	/*SKT-VT END of Initial*/
+
+
+};
+
+
+/* Set-data based on Samsung Reliabilty Group standard */
+/* ,when using WIFI. 15fps*/
+static const u32 s5k5bafx_vt_wifi_common[] =
+{
+	/* wifi 15fps vt-call 110815 */
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064,
+	
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	
+	0x0F120015,
+	
+	
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000, /* senHal_bUseAnalogBinning */
+	0x0F120000, /* senHal_bUseAnalogVerAvg  */
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* -- */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200FB, /* 0EB */
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F122710,
+	0x0F120000,
+	0x002A048C,
+	0x0F124E20, /* 8214 */
+	0x0F120000,
+	0x0F1261A8, /* A122 */
+	0x0F120000,
+	0x002A0488,
+	0x0F128214, /* f424 */
+	0x0F120000,
+	0x002A043A,
+	0x0F120340,
+	0x0F120600,
+	0x002A0494,
+	0x0F120340,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+
+	0x002A0E98,
+	0x0F1202B0,
+	0x002A0E9E,
+	0x0F120290,
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12007F,
+	
+	0xffff000a, /* Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+	
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052, /*-*/
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A, /*-535-*/
+	0x0F12029A, /*-29A-*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+	
+	/* Apply preview config */
+	/* 0x002A021C, */
+	/* 0x0F120000, */
+	/* 0x002A0220, */
+	/* 0x0F120001, */
+	/* 0x002A01F8, */
+	/* 0x0F120001, */
+	/* 0x002A021E, */
+	/* 0x0F120001, */
+	/* 0x002A01F0, */
+	/* 0x0F120001, */
+	/* 0x0F120001, */
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 15fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000, /* msm_uOffsetNoBin[0][0] */
+	0x0F120000, /* msm_uOffsetNoBin[0][1] */
+	0x0F120000, /* msm_uOffsetNoBin[1][0] */
+	0x0F120000, /* msm_uOffsetNoBin[1][1] */
+	0x0F120000, /* msm_uOffsetNoBin[2][0] */
+	0x0F120000, /* msm_uOffsetNoBin[2][1] */
+	0x0F120000, /* msm_uOffsetNoBin[3][0] */
+	0x0F120000, /* msm_uOffsetNoBin[3][1] */
+	
+	0x002A0798,
+	0x0F120000, /* msm_uOffsetBin[0][0] */
+	0x0F120000, /* msm_uOffsetBin[0][1] */
+	0x0F120000, /* msm_uOffsetBin[1][0] */
+	0x0F120000, /* msm_uOffsetBin[1][1] */
+	
+	0x002A07C0,
+	0x0F120004, /* msm_NonLinearOfsOutput[2] */
+	0x0F120004, /* msm_NonLinearOfsOutput[3] */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R */
+	0x0F120400, /* awbb_GainsInit_1_:G */
+	0x0F1205F0, /* awbb_GainsInit_2_:B */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start */
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120302,   /*0403     0101*/
+	0x0F120203,   /*0304     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120201,   /*0302     0101*/
+	0x0F120102,   /*0203     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120101,   /*0101     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	0x0F120000,   /*0000     0101*/
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /*00E0 TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[2]  */
+	0x0F1200F0, /*0100 TVAR_ash_GASAlpha[3]  */
+	
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[6]  */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[7]  */
+	
+	0x0F1200F8, /*00F0 TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[10] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[11] */
+	
+	0x0F1200F8, /*00F8 TVAR_ash_GASAlpha[12] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[13] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[14] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[15] */
+	
+	0x0F1200F8, /*00F8 TVAR_ash_GASAlpha[16] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[17] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[18] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[20] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[21] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[22] */
+	0x0F1200F0, /*00F0 TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[24] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[25] */
+	0x0F120100, /*0100 TVAR_ash_GASAlpha[26] */
+	0x0F1200F0, /*00E8 TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F1200F0, /* TVAR_ash_GASOutdoorAlpha_3_ */
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120198,
+	0x0F120176,
+	0x0F120140,
+	0x0F12010B,
+	0x0F1200E7,
+	0x0F1200D0,
+	0x0F1200C6,
+	0x0F1200CE,
+	0x0F1200E4,
+	0x0F120109,
+	0x0F12013A,
+	0x0F12016D,
+	0x0F120199,
+	0x0F120175,
+	0x0F12013C,
+	0x0F120105,
+	0x0F1200D3,
+	0x0F1200AC,
+	0x0F120093,
+	0x0F12008A,
+	0x0F120091,
+	0x0F1200AA,
+	0x0F1200D0,
+	0x0F120102,
+	0x0F12013E,
+	0x0F120171,
+	0x0F12014F,
+	0x0F12010C,
+	0x0F1200CF,
+	0x0F12009A,
+	0x0F120070,
+	0x0F120055,
+	0x0F12004C,
+	0x0F120055,
+	0x0F12006F,
+	0x0F12009A,
+	0x0F1200CF,
+	0x0F12010E,
+	0x0F12014D,
+	0x0F120130,
+	0x0F1200E9,
+	0x0F1200A7,
+	0x0F120070,
+	0x0F120045,
+	0x0F12002A,
+	0x0F120020,
+	0x0F12002A,
+	0x0F120045,
+	0x0F120071,
+	0x0F1200AA,
+	0x0F1200E8,
+	0x0F12012E,
+	0x0F12011C,
+	0x0F1200D7,
+	0x0F120091,
+	0x0F120057,
+	0x0F12002D,
+	0x0F120012,
+	0x0F12000A,
+	0x0F120013,
+	0x0F12002F,
+	0x0F12005B,
+	0x0F120094,
+	0x0F1200D6,
+	0x0F120119,
+	0x0F120116,
+	0x0F1200D0,
+	0x0F12008C,
+	0x0F12004F,
+	0x0F120024,
+	0x0F12000A,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120027,
+	0x0F120054,
+	0x0F120090,
+	0x0F1200D1,
+	0x0F120113,
+	0x0F12011D,
+	0x0F1200D7,
+	0x0F120095,
+	0x0F120057,
+	0x0F12002B,
+	0x0F120011,
+	0x0F120008,
+	0x0F120012,
+	0x0F120030,
+	0x0F12005C,
+	0x0F120099,
+	0x0F1200DA,
+	0x0F12011D,
+	0x0F120133,
+	0x0F1200EF,
+	0x0F1200AC,
+	0x0F12006F,
+	0x0F120043,
+	0x0F120028,
+	0x0F12001F,
+	0x0F12002A,
+	0x0F120047,
+	0x0F120077,
+	0x0F1200B1,
+	0x0F1200F2,
+	0x0F120135,
+	0x0F120153,
+	0x0F120113,
+	0x0F1200D2,
+	0x0F120098,
+	0x0F12006A,
+	0x0F12004E,
+	0x0F120046,
+	0x0F120053,
+	0x0F120070,
+	0x0F12009E,
+	0x0F1200D7,
+	0x0F120117,
+	0x0F120155,
+	0x0F12017B,
+	0x0F120141,
+	0x0F120100,
+	0x0F1200C9,
+	0x0F1200A0,
+	0x0F120086,
+	0x0F120080,
+	0x0F12008A,
+	0x0F1200A5,
+	0x0F1200CF,
+	0x0F120108,
+	0x0F120144,
+	0x0F12017B,
+	0x0F12019F,
+	0x0F120171,
+	0x0F120133,
+	0x0F1200FC,
+	0x0F1200D5,
+	0x0F1200BC,
+	0x0F1200B5,
+	0x0F1200BF,
+	0x0F1200D8,
+	0x0F120105,
+	0x0F12013A,
+	0x0F12016F,
+	0x0F12019D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120149,
+	0x0F12012C,
+	0x0F1200FC,
+	0x0F1200CE,
+	0x0F1200AE,
+	0x0F12009A,
+	0x0F120092,
+	0x0F120096,
+	0x0F1200A6,
+	0x0F1200C3,
+	0x0F1200E9,
+	0x0F120116,
+	0x0F120135,
+	0x0F120131,
+	0x0F1200FE,
+	0x0F1200CE,
+	0x0F1200A3,
+	0x0F120082,
+	0x0F12006D,
+	0x0F120066,
+	0x0F12006B,
+	0x0F12007B,
+	0x0F120096,
+	0x0F1200BF,
+	0x0F1200EF,
+	0x0F12011A,
+	0x0F120117,
+	0x0F1200D8,
+	0x0F1200A2,
+	0x0F120077,
+	0x0F120058,
+	0x0F120043,
+	0x0F12003A,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200FC,
+	0x0F1200FF,
+	0x0F1200BC,
+	0x0F120084,
+	0x0F120058,
+	0x0F120038,
+	0x0F120023,
+	0x0F12001A,
+	0x0F120021,
+	0x0F120035,
+	0x0F120052,
+	0x0F12007A,
+	0x0F1200AB,
+	0x0F1200E2,
+	0x0F1200EF,
+	0x0F1200AE,
+	0x0F120072,
+	0x0F120046,
+	0x0F120025,
+	0x0F120010,
+	0x0F120009,
+	0x0F12000F,
+	0x0F120023,
+	0x0F120040,
+	0x0F12006A,
+	0x0F120099,
+	0x0F1200CF,
+	0x0F1200E7,
+	0x0F1200AA,
+	0x0F12006E,
+	0x0F12003F,
+	0x0F12001E,
+	0x0F120009,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001B,
+	0x0F12003A,
+	0x0F120064,
+	0x0F120093,
+	0x0F1200C9,
+	0x0F1200EC,
+	0x0F1200B0,
+	0x0F120075,
+	0x0F120045,
+	0x0F120023,
+	0x0F12000E,
+	0x0F120006,
+	0x0F12000D,
+	0x0F120021,
+	0x0F12003E,
+	0x0F120068,
+	0x0F120097,
+	0x0F1200CD,
+	0x0F1200FD,
+	0x0F1200C0,
+	0x0F120088,
+	0x0F120057,
+	0x0F120035,
+	0x0F120020,
+	0x0F120018,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004F,
+	0x0F120077,
+	0x0F1200A6,
+	0x0F1200DD,
+	0x0F120116,
+	0x0F1200DA,
+	0x0F1200A3,
+	0x0F120075,
+	0x0F120052,
+	0x0F12003C,
+	0x0F120034,
+	0x0F12003C,
+	0x0F12004E,
+	0x0F12006A,
+	0x0F120090,
+	0x0F1200C0,
+	0x0F1200F4,
+	0x0F120132,
+	0x0F1200FD,
+	0x0F1200C5,
+	0x0F12009A,
+	0x0F120078,
+	0x0F120065,
+	0x0F12005F,
+	0x0F120064,
+	0x0F120073,
+	0x0F12008C,
+	0x0F1200B3,
+	0x0F1200E1,
+	0x0F12010E,
+	0x0F120150,
+	0x0F120122,
+	0x0F1200ED,
+	0x0F1200C1,
+	0x0F1200A1,
+	0x0F12008B,
+	0x0F120082,
+	0x0F120087,
+	0x0F120096,
+	0x0F1200B3,
+	0x0F1200DB,
+	0x0F120102,
+	0x0F12012D,
+	0x0F120100,
+	0x0F1200EC,
+	0x0F1200C4,
+	0x0F1200A2,
+	0x0F120089,
+	0x0F12007C,
+	0x0F12007A,
+	0x0F120082,
+	0x0F120094,
+	0x0F1200B0,
+	0x0F1200D5,
+	0x0F120102,
+	0x0F120124,
+	0x0F1200E9,
+	0x0F1200BF,
+	0x0F12009C,
+	0x0F12007F,
+	0x0F120068,
+	0x0F12005A,
+	0x0F120057,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008A,
+	0x0F1200AF,
+	0x0F1200DC,
+	0x0F120109,
+	0x0F1200D1,
+	0x0F12009E,
+	0x0F120077,
+	0x0F12005B,
+	0x0F120044,
+	0x0F120036,
+	0x0F120031,
+	0x0F12003A,
+	0x0F12004D,
+	0x0F120068,
+	0x0F12008B,
+	0x0F1200B6,
+	0x0F1200E7,
+	0x0F1200BC,
+	0x0F120088,
+	0x0F12005E,
+	0x0F12003F,
+	0x0F120029,
+	0x0F12001B,
+	0x0F120016,
+	0x0F12001F,
+	0x0F120032,
+	0x0F12004D,
+	0x0F12006F,
+	0x0F120097,
+	0x0F1200C9,
+	0x0F1200AF,
+	0x0F12007C,
+	0x0F120050,
+	0x0F120030,
+	0x0F12001B,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000E,
+	0x0F120021,
+	0x0F120039,
+	0x0F12005C,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200AA,
+	0x0F120079,
+	0x0F12004E,
+	0x0F12002C,
+	0x0F120014,
+	0x0F120005,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120031,
+	0x0F120053,
+	0x0F120079,
+	0x0F1200A9,
+	0x0F1200AD,
+	0x0F12007F,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001A,
+	0x0F12000A,
+	0x0F120004,
+	0x0F12000B,
+	0x0F12001B,
+	0x0F120031,
+	0x0F120052,
+	0x0F120078,
+	0x0F1200A6,
+	0x0F1200BB,
+	0x0F12008D,
+	0x0F120065,
+	0x0F120042,
+	0x0F120029,
+	0x0F12001A,
+	0x0F120015,
+	0x0F12001A,
+	0x0F120028,
+	0x0F120040,
+	0x0F12005D,
+	0x0F120084,
+	0x0F1200B4,
+	0x0F1200D5,
+	0x0F1200A7,
+	0x0F12007E,
+	0x0F12005E,
+	0x0F120043,
+	0x0F120033,
+	0x0F12002E,
+	0x0F120033,
+	0x0F120040,
+	0x0F120056,
+	0x0F120073,
+	0x0F120099,
+	0x0F1200C8,
+	0x0F1200F5,
+	0x0F1200C8,
+	0x0F12009E,
+	0x0F12007F,
+	0x0F120067,
+	0x0F120058,
+	0x0F120056,
+	0x0F120058,
+	0x0F120062,
+	0x0F120074,
+	0x0F120092,
+	0x0F1200B9,
+	0x0F1200E4,
+	0x0F120113,
+	0x0F1200ED,
+	0x0F1200C3,
+	0x0F1200A1,
+	0x0F12008A,
+	0x0F12007A,
+	0x0F120074,
+	0x0F120077,
+	0x0F120081,
+	0x0F120097,
+	0x0F1200B6,
+	0x0F1200DA,
+	0x0F120102,
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone  */
+	0x0F120000, /* awbb_LowBr0_NBzone */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F1203B4, /*03B4 038F awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F1203BE, /*03C0 039B awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F12039A, /*037C 0373 awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203C4, /*03C8 03B0 awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F12037C, /*035E 0352 awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203C8, /*03C8 03B7 awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F12035E, /*0340 0334 awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203C0, /*03C0 03B5 awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120344, /*0328 0318 awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203AC, /*03B0 03B0 awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F12032A, /*0310 02FF awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F120394, /*039E 038D awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F12030E, /*02FA 02E7 awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120378, /*0384 0372 awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202F6, /*02DC 02D0 awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035C, /*036C 035D awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202DC, /*02CA 02B5 awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120344, /*035A 0345 awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202C6, /*02B4 02A1 awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F12032A, /*0340 0331 awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F1202B0, /*029E 028B awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12030E, /*0324 031E awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120298, /*028C 0273 awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F1202F8, /*0306 0309 awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F120286, /*027A 025F awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202E2, /*02F6 02F5 awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120270, /*026A 0250 awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202D0, /*02E4 02DB awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F12025E, /*025A 0241 awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202BC, /*02DA 02C7 awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F12024A, /*024C 0233 awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202AC, /*02CE 02B9 awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120238, /*023A 0223 awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202A0, /*02C4 02AB awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120226, /*0230 0217 awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F12029A, /*02B8 02A2 awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120214, /*0220 0207 awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120296, /*02AC 0294 awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F120202, /*0212 01FA awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120294, /*02AA 0289 awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201F4, /*0204 01EA awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120290, /*02A6 0281 awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201E6, /*01FA 01DD awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12028A, /*02A0 027B awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D8, /*01EE 01D0 awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120288, /*029C 0273 awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201CA, /*01E0 01C3 awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12027E, /*0294 026A awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201C0, /*01D4 01B6 awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120274, /*028A 0265 awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201B2, /*01C8 01AB awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12026C, /*0282 025B awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201AA, /*01C0 01A1 awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120264, /*027A 0254 awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F1201A6, /*01BC 0198 awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12025C, /*0272 024B awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F1201A2, /*01B8 0192 awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F12024C, /*0262 0242 awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F1201A8, /*01BC 0191 awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F120238, /*024E 023A awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F1201D6, /*01EC 0192 awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F1201F0, /*0206 0222 awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /*0000 01C5 awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /*0000 01DF awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001F,
+	0x0F120000,
+	0x0F120108,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /*025E*/
+	0x0F120282, /*0282*/
+	0x0F120246, /*0240*/
+	0x0F12029E, /*0298*/
+	0x0F120230, /*022A*/
+	0x0F1202A0, /*029A*/
+	0x0F120220, /*021A*/
+	0x0F1202A0, /*029A*/
+	0x0F12020E, /*0206*/
+	0x0F12029E, /*0298*/
+	0x0F120206, /*01FE*/
+	0x0F120292, /*028C*/
+	0x0F120200, /*01FA*/
+	0x0F12027E, /*0278*/
+	0x0F1201FE, /*01F8*/
+	0x0F12026A, /*0266*/
+	0x0F12021A, /*0214*/
+	0x0F12023E, /*0238*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120208,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__2_       */
+	0x0F120014, /*0050 awbb_GridCorr_R_0__3_       */
+	0x0F12FFF0, /*0000 awbb_GridCorr_R_0__4_       */
+	0x0F1200C0, /*005A awbb_GridCorr_R_0__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__2_       */
+	0x0F120014, /*0050 awbb_GridCorr_R_1__3_       */
+	0x0F12FFF0, /*0000 awbb_GridCorr_R_1__4_       */
+	0x0F1200C0, /*005A awbb_GridCorr_R_1__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__2_       */
+	0x0F120014, /*0050 awbb_GridCorr_R_2__3_       */
+	0x0F12FFF0, /*0000 awbb_GridCorr_R_2__4_       */
+	0x0F1200C0, /*005A awbb_GridCorr_R_2__5_       */
+	
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_0__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_0__1_     */
+	0x0F120028, /*FFD8 awbb_GridCorr_B_0__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__3_     */
+	0x0F12FFA8, /*FF88 awbb_GridCorr_B_0__4_     */
+	0x0F12FE50, /*FEA0 awbb_GridCorr_B_0__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_1__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_1__1_     */
+	0x0F120028, /*FFD8 awbb_GridCorr_B_1__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__3_     */
+	0x0F12FFA8, /*FF88 awbb_GridCorr_B_1__4_     */
+	0x0F12FE50, /*FEA0 awbb_GridCorr_B_1__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_2__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_2__1_     */
+	0x0F120028, /*FFD8 awbb_GridCorr_B_2__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__3_     */
+	0x0F12FFA8, /*FF88 awbb_GridCorr_B_2__4_     */
+	0x0F12FE50, /*FEA0 awbb_GridCorr_B_2__5_     */
+	
+	0x0F1202EA, /*awbb_GridConst_1_0_    */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F120388, /*awbb_GridConst_1_2_    */
+	          
+	0x0F121032, /* 1032 awbb_GridConst_2_0    */
+	0x0F1210B2, /* 10B2 awbb_GridConst_2_1    */
+	0x0F12115B, /* 1160 awbb_GridConst_2_2    */
+	0x0F12115C, /* 1161 awbb_GridConst_2_3    */
+	0x0F1211BE, /* 11BE awbb_GridConst_2_4    */
+	0x0F12124C, /* 124C awbb_GridConst_2_5    */
+	
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,  /*--- 52A awbb_MvEq_RBthresh */
+	
+	/* Gamut Thresholds */
+	0x002A0DAA,
+	0x0F120664, /*--- 71A */
+	0x0F120355, /*--- 3A4 */
+	0x002A0DAE,
+	0x0F12002C, /*--- 36 */
+	0x0F120024, /*--- 1C */
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120E01,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120256, /*-- 256 */
+	0x0F120248, /*-- 248 */
+	0x002A0D96,
+	0x0F120E00,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120258,
+	0x0F120003,
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F12010D, /*-0136---*/  /* H */
+	0x0F12FFA7, /*-FF8B---*/
+	0x0F12FFF5, /*-FFE8---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+
+	0x0F12010D, /*-010D---*/  /* A */
+	0x0F12FFA7, /*-FFA7---*/
+	0x0F12FFF5, /*-FFF5---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+	
+	0x0F1201EA, /*01E9*/  /* WW */
+	0x0F12FFB9, /*FFAE*/
+	0x0F12FFDB, /*FFE6*/
+	0x0F120127, /*0127*/
+	0x0F120109, /*0109*/
+	0x0F12FF3C, /*FF3C*/
+	0x0F12FF2B, /*FF2B*/
+	0x0F12021B, /*021B*/
+	0x0F12FF48, /*FF48*/
+	0x0F12FF03, /*FF03*/
+	0x0F120207, /*0207*/
+	0x0F120113, /*0113*/
+	0x0F12FFCA, /*FFCA*/
+	0x0F12FF93, /*FF93*/
+	0x0F12016F, /*016F*/
+	0x0F120164, /*0164*/
+	0x0F12FF55, /*FF55*/
+	0x0F120163, /*0163*/
+	
+	0x0F1201EA, /*01E9*/  /* CW */
+	0x0F12FFB9, /*FFAE*/
+	0x0F12FFDB, /*FFE6*/
+	0x0F120127, /*0127*/
+	0x0F120109, /*0109*/
+	0x0F12FF3C, /*FF3C*/
+	0x0F12FF2B, /*FF2B*/
+	0x0F12021B, /*021B*/
+	0x0F12FF48, /*FF48*/
+	0x0F12FF03, /*FF03*/
+	0x0F120207, /*0207*/
+	0x0F120113, /*0113*/
+	0x0F12FFCA, /*FFCA*/
+	0x0F12FF93, /*FF93*/
+	0x0F12016F, /*016F*/
+	0x0F120164, /*0164*/
+	0x0F12FF55, /*FF55*/
+	0x0F120163, /*0163*/
+	
+	0x0F12018A, /*-r014D---*/  /* D50 */
+	0x0F12FFA0, /*-rFFA7---*/
+	0x0F12FFE9, /*-rFFF4---*/
+	0x0F1200C5, /*-y00C5---*/
+	0x0F120103, /*-y0103---*/
+	0x0F12FF5D, /*-yFF5D---*/
+	0x0F12FEFE, /*-gFF16---*/
+	0x0F12021D, /*-g0209---*/
+	0x0F12FF2C, /*-gFF42---*/
+	0x0F12FF18, /*- FF18---*/
+	0x0F12018F, /*- 018F---*/
+	0x0F1200C8, /*- 00C8---*/
+	0x0F12FFE1, /*- FFE1---*/
+	0x0F12FFA0, /*- FFA0---*/
+	0x0F1201D9, /*- 01D9---*/
+	0x0F120132, /*- 0132---*/
+	0x0F12FF3E, /*- FF3E---*/
+	0x0F120100, /*- 0100---*/
+	
+	0x0F12018A, /*-r014D---*/  /* D65 */
+	0x0F12FFA0, /*-rFFA7---*/
+	0x0F12FFE9, /*-rFFF4---*/
+	0x0F1200C5, /*-y00C5---*/
+	0x0F120103, /*-y0103---*/
+	0x0F12FF5D, /*-yFF5D---*/
+	0x0F12FEFE, /*-gFF16---*/
+	0x0F12021D, /*-g0209---*/
+	0x0F12FF2C, /*-gFF42---*/
+	0x0F12FF18, /*- FF18---*/
+	0x0F12018F, /*- 018F---*/
+	0x0F1200C8, /*- 00C8---*/
+	0x0F12FFE1, /*- FFE1---*/
+	0x0F12FFA0, /*- FFA0---*/
+	0x0F1201D9, /*- 01D9---*/
+	0x0F120132, /*- 0132---*/
+	0x0F12FF3E, /*- FF3E---*/
+	0x0F120100, /*- 0100---*/
+	
+	
+	0x0F1201CC, /*--01CC--*/ /* OUT */
+	0x0F12FFC3, /*--FFC3--*/
+	0x0F120009, /*--0009--*/
+	0x0F1200A2, /*--009D--*/
+	0x0F120106, /*--00FA--*/
+	0x0F12FF3F, /*--FF50--*/
+	0x0F12FED8, /*--FED8--*/
+	0x0F1201FE, /*--01FE--*/
+	0x0F12FF08, /*--FF08--*/
+	0x0F12FEC7, /*--FEC7--*/
+	0x0F1200F5, /*--00F5--*/
+	0x0F120119, /*--0119--*/
+	0x0F12FFDF, /*--FFDF--*/
+	0x0F120024, /*--0024--*/
+	0x0F1201A8, /*--01A8--*/
+	0x0F120170, /*--0170--*/
+	0x0F12FFAD, /*--FFAD--*/
+	0x0F12011B, /*--011B--*/
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F120008,
+	0x0F120016,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F120008,
+	0x0F120016,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+	
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+
+	
+	0x002A082C,
+	0x0F120020, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120014, /* SATURATION                                                         */
+	0x0F12ffb0, /* SHARP_BLUR                                                         */
+	0x0F120008, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12803c, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120058, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A08AA, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120020, /* SATURATION                                                         */
+	0x0F12ffe0, /* SHARP_BLUR                                                         */
+	0x0F120004, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120114, /* UVDenoise_iYLowThresh*/
+	0x0F12020A, /* UVDenoise_iYHighThresh*/
+	0x0F1203FF, /* UVDenoise_iUVLowThresh*/
+	0x0F1203FF, /* UVDenoise_iUVHighThresh*/
+	0x0F120028, /* DSMix1_iLowLimit_Wide*/
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin*/
+	0x0F120014, /* DSMix1_iHighLimit_Wide*/
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin*/
+	0x0F120050, /* DSMix1_iLowLimit_Fine*/
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin*/
+	0x0F120046, /* DSMix1_iHighLimit_Fine*/
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin*/
+	0x0F120106, /* DSMix1_iRGBOffset*/
+	0x0F12006F, /* DSMix1_iDemClamp*/
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin" bin: desparity low */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F12003C, /*--  RGB2YUV_iYOffset                                                  */
+	         
+	0x002A0928, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x002A09A6, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x002A0A24, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                  */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x002A0AA2, /* --                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                         */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                        */
+	0x0F120800, /* Denoise1_sensor_width                            */
+	0x0F120600, /* Denoise1_sensor_height                           */
+	0x0F120000, /* Denoise1_start_x                                 */
+	0x0F120000, /* Denoise1_start_y                                 */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "         */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "       */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  " */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "          */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "        */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "     */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "    */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh"*/
+	0x0F120000, /*  Demosaic4_iBypassSelect                         */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+	/* Wifi VT-Call END 110815 */
+	
+
+
+	
+};
+
+/*===========================================
+* CAMERA_PREVIEW - ÃÔ¿µ ÈÄ ÇÁ¸®ºä º¹±Í½Ã ¼ÂÆà *
+============================================*/
+
+static const u32 s5k5bafx_preview[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+
+};
+
+/*===========================================
+*	CAMERA_SNAPSHOT  - ÃÔ¿µ 		  *
+============================================*/
+
+static const u32 s5k5bafx_capture[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0224,
+	0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A0226,
+	0x0F120001, /* REG_TC_GP_CapConfigChanged */
+	0x002A01F4,
+	0x0F120001, /* REG_TC_GP_EnableCapture */
+	0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+#if defined(CONFIG_TARGET_LOCALE_KOR) || \
+	defined(CONFIG_TARGET_LOCALE_NAATT) || \
+	defined(CONFIG_MACH_P8LTE)
+static const u32 s5k5bafx_recording_60Hz_common[] = {
+	
+	/* recording 25fps Anti-Flicker 60Hz*/
+	
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064,
+	
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* -- */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB,
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,
+	0x0F120000,
+	0x0F12A122,
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,
+	0x0F120000,
+	0x002A043A,
+	0x0F120200,
+	0x0F120200,
+	0x002A0494,
+	0x0F120300,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+	
+	0x002A0E98,
+	0x0F1202A8,
+	0x002A0E9E,
+	0x0F120298,
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12005F,
+	
+	0xffff000a, /* Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+	
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 25fps) */
+	0x002A0242,
+#if 0
+	/*++ 640x480 */
+	/* 0x0F120280, */ /* REG_0TC_PCFG_usWidth */
+	/* 0x0F1201E0, */ /* REG_0TC_PCFG_usHeight */
+	/*-- 640x480 */
+#else
+	/*++ 800x600 */
+	0x0F120320, /* REG_0TC_PCFG_usWidth */
+	0x0F120258, /* REG_0TC_PCFG_usHeight */
+	/*-- 800x600 */
+#endif
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052, /*-*/
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F1201A0, /*-535-*/
+	0x0F1201A0, /*-29A-*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+	
+	/* Apply preview config */
+	/* 0x002A021C, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActivePrevConfig */
+	/* 0x002A0220, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevOpenAfterChange */
+	/* 0x002A01F8, */
+	/* 0x0F120001, */ /* REG_TC_GP_NewConfigSync */
+	/* 0x002A021E, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevConfigChanged */
+	/* 0x002A01F0, */
+	/* 0x0F120001, */ /* REG_TC_GP_EnablePreview */
+	/* 0x0F120001, */ /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160,
+	0x0F120134,
+	0x0F1200FF,
+	0x0F1200D1,
+	0x0F1200B1,
+	0x0F12009D,
+	0x0F120096,
+	0x0F12009E,
+	0x0F1200B3,
+	0x0F1200D3,
+	0x0F1200FF,
+	0x0F120131,
+	0x0F120159,
+	0x0F12013C,
+	0x0F120107,
+	0x0F1200CD,
+	0x0F1200A1,
+	0x0F120080,
+	0x0F12006B,
+	0x0F120064,
+	0x0F12006C,
+	0x0F120080,
+	0x0F1200A1,
+	0x0F1200CD,
+	0x0F120106,
+	0x0F120139,
+	0x0F120116,
+	0x0F1200DC,
+	0x0F1200A2,
+	0x0F120073,
+	0x0F120051,
+	0x0F12003B,
+	0x0F120033,
+	0x0F12003B,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A2,
+	0x0F1200DD,
+	0x0F120115,
+	0x0F1200FA,
+	0x0F1200BF,
+	0x0F120085,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001B,
+	0x0F120014,
+	0x0F12001A,
+	0x0F120031,
+	0x0F120055,
+	0x0F120085,
+	0x0F1200C0,
+	0x0F1200FB,
+	0x0F1200EA,
+	0x0F1200AF,
+	0x0F120074,
+	0x0F120045,
+	0x0F120020,
+	0x0F12000B,
+	0x0F120003,
+	0x0F12000A,
+	0x0F120020,
+	0x0F120046,
+	0x0F120076,
+	0x0F1200B1,
+	0x0F1200ED,
+	0x0F1200E6,
+	0x0F1200AA,
+	0x0F120071,
+	0x0F120041,
+	0x0F12001D,
+	0x0F120008,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001E,
+	0x0F120044,
+	0x0F120074,
+	0x0F1200B0,
+	0x0F1200EC,
+	0x0F1200EF,
+	0x0F1200B3,
+	0x0F12007A,
+	0x0F12004A,
+	0x0F120026,
+	0x0F120011,
+	0x0F12000A,
+	0x0F120011,
+	0x0F120029,
+	0x0F12004F,
+	0x0F120080,
+	0x0F1200BC,
+	0x0F1200F8,
+	0x0F120105,
+	0x0F1200C9,
+	0x0F12008F,
+	0x0F120060,
+	0x0F12003C,
+	0x0F120026,
+	0x0F12001F,
+	0x0F120028,
+	0x0F120040,
+	0x0F120066,
+	0x0F120097,
+	0x0F1200D4,
+	0x0F120110,
+	0x0F120124,
+	0x0F1200EB,
+	0x0F1200B1,
+	0x0F120082,
+	0x0F12005F,
+	0x0F12004A,
+	0x0F120043,
+	0x0F12004C,
+	0x0F120064,
+	0x0F120089,
+	0x0F1200BA,
+	0x0F1200F8,
+	0x0F12012F,
+	0x0F120147,
+	0x0F120116,
+	0x0F1200DE,
+	0x0F1200AF,
+	0x0F12008E,
+	0x0F12007A,
+	0x0F120072,
+	0x0F12007A,
+	0x0F120091,
+	0x0F1200B6,
+	0x0F1200E8,
+	0x0F120121,
+	0x0F120150,
+	0x0F120170,
+	0x0F12013F,
+	0x0F120110,
+	0x0F1200E2,
+	0x0F1200C0,
+	0x0F1200AB,
+	0x0F1200A4,
+	0x0F1200AC,
+	0x0F1200C3,
+	0x0F1200E6,
+	0x0F120117,
+	0x0F120145,
+	0x0F120172,
+	0x0F120127,
+	0x0F120100,
+	0x0F1200CF,
+	0x0F1200A7,
+	0x0F12008D,
+	0x0F12007D,
+	0x0F120077,
+	0x0F12007A,
+	0x0F120087,
+	0x0F12009E,
+	0x0F1200C0,
+	0x0F1200EC,
+	0x0F12010F,
+	0x0F120108,
+	0x0F1200D8,
+	0x0F1200A5,
+	0x0F120080,
+	0x0F120066,
+	0x0F120056,
+	0x0F12004F,
+	0x0F120053,
+	0x0F120061,
+	0x0F120077,
+	0x0F120098,
+	0x0F1200C6,
+	0x0F1200F3,
+	0x0F1200E7,
+	0x0F1200B4,
+	0x0F120081,
+	0x0F12005C,
+	0x0F120041,
+	0x0F120030,
+	0x0F120029,
+	0x0F12002E,
+	0x0F12003D,
+	0x0F120055,
+	0x0F120076,
+	0x0F1200A5,
+	0x0F1200D4,
+	0x0F1200CF,
+	0x0F12009B,
+	0x0F12006A,
+	0x0F120043,
+	0x0F120027,
+	0x0F120016,
+	0x0F12000F,
+	0x0F120015,
+	0x0F120025,
+	0x0F12003E,
+	0x0F120061,
+	0x0F12008E,
+	0x0F1200BF,
+	0x0F1200C2,
+	0x0F12008E,
+	0x0F12005D,
+	0x0F120037,
+	0x0F12001A,
+	0x0F120009,
+	0x0F120002,
+	0x0F120007,
+	0x0F120018,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200BE,
+	0x0F12008A,
+	0x0F12005A,
+	0x0F120034,
+	0x0F120017,
+	0x0F120006,
+	0x0F120000,
+	0x0F120006,
+	0x0F120017,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200C5,
+	0x0F120091,
+	0x0F120061,
+	0x0F12003B,
+	0x0F120020,
+	0x0F12000F,
+	0x0F120009,
+	0x0F120010,
+	0x0F120021,
+	0x0F12003D,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BE,
+	0x0F1200D7,
+	0x0F1200A2,
+	0x0F120072,
+	0x0F12004D,
+	0x0F120032,
+	0x0F120022,
+	0x0F12001D,
+	0x0F120024,
+	0x0F120035,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A0,
+	0x0F1200D2,
+	0x0F1200F0,
+	0x0F1200BE,
+	0x0F12008C,
+	0x0F120068,
+	0x0F12004F,
+	0x0F120040,
+	0x0F12003B,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006C,
+	0x0F12008E,
+	0x0F1200BE,
+	0x0F1200ED,
+	0x0F12010C,
+	0x0F1200E1,
+	0x0F1200AF,
+	0x0F12008A,
+	0x0F120072,
+	0x0F120064,
+	0x0F12005F,
+	0x0F120065,
+	0x0F120074,
+	0x0F12008D,
+	0x0F1200B2,
+	0x0F1200E0,
+	0x0F12010A,
+	0x0F12012F,
+	0x0F120104,
+	0x0F1200D9,
+	0x0F1200B3,
+	0x0F120099,
+	0x0F12008B,
+	0x0F120086,
+	0x0F12008B,
+	0x0F12009B,
+	0x0F1200B5,
+	0x0F1200DA,
+	0x0F120101,
+	0x0F120128,
+	0x0F12012F,
+	0x0F120106,
+	0x0F1200D4,
+	0x0F1200AA,
+	0x0F12008E,
+	0x0F12007D,
+	0x0F120079,
+	0x0F120080,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200DC,
+	0x0F12010C,
+	0x0F120130,
+	0x0F120112,
+	0x0F1200E0,
+	0x0F1200AB,
+	0x0F120083,
+	0x0F120067,
+	0x0F120057,
+	0x0F120051,
+	0x0F120059,
+	0x0F12006B,
+	0x0F120089,
+	0x0F1200B2,
+	0x0F1200E5,
+	0x0F120114,
+	0x0F1200F2,
+	0x0F1200BD,
+	0x0F120088,
+	0x0F120061,
+	0x0F120044,
+	0x0F120031,
+	0x0F12002C,
+	0x0F120033,
+	0x0F120047,
+	0x0F120065,
+	0x0F12008C,
+	0x0F1200C0,
+	0x0F1200F3,
+	0x0F1200DB,
+	0x0F1200A5,
+	0x0F120071,
+	0x0F120049,
+	0x0F12002A,
+	0x0F120018,
+	0x0F120011,
+	0x0F120018,
+	0x0F12002C,
+	0x0F12004B,
+	0x0F120072,
+	0x0F1200A3,
+	0x0F1200D7,
+	0x0F1200CD,
+	0x0F120097,
+	0x0F120065,
+	0x0F12003C,
+	0x0F12001D,
+	0x0F12000A,
+	0x0F120003,
+	0x0F120009,
+	0x0F12001D,
+	0x0F12003B,
+	0x0F120063,
+	0x0F120092,
+	0x0F1200C4,
+	0x0F1200CA,
+	0x0F120094,
+	0x0F120062,
+	0x0F12003A,
+	0x0F12001A,
+	0x0F120007,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120036,
+	0x0F12005C,
+	0x0F12008A,
+	0x0F1200BC,
+	0x0F1200D1,
+	0x0F12009B,
+	0x0F120069,
+	0x0F120042,
+	0x0F120022,
+	0x0F12000F,
+	0x0F120008,
+	0x0F12000D,
+	0x0F12001F,
+	0x0F12003B,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BF,
+	0x0F1200E3,
+	0x0F1200AC,
+	0x0F12007A,
+	0x0F120053,
+	0x0F120035,
+	0x0F120022,
+	0x0F12001B,
+	0x0F12001F,
+	0x0F120030,
+	0x0F12004B,
+	0x0F12006D,
+	0x0F12009C,
+	0x0F1200CE,
+	0x0F1200FE,
+	0x0F1200C9,
+	0x0F120095,
+	0x0F12006F,
+	0x0F120052,
+	0x0F120040,
+	0x0F120039,
+	0x0F12003D,
+	0x0F12004B,
+	0x0F120063,
+	0x0F120086,
+	0x0F1200B5,
+	0x0F1200E6,
+	0x0F12011B,
+	0x0F1200ED,
+	0x0F1200BA,
+	0x0F120092,
+	0x0F120076,
+	0x0F120065,
+	0x0F12005D,
+	0x0F120060,
+	0x0F12006D,
+	0x0F120084,
+	0x0F1200A8,
+	0x0F1200D6,
+	0x0F120101,
+	0x0F120140,
+	0x0F120112,
+	0x0F1200E5,
+	0x0F1200BD,
+	0x0F12009E,
+	0x0F12008C,
+	0x0F120085,
+	0x0F120087,
+	0x0F120094,
+	0x0F1200AC,
+	0x0F1200D0,
+	0x0F1200F8,
+	0x0F120123,
+	0x0F1200F2,
+	0x0F1200D1,
+	0x0F1200A7,
+	0x0F120087,
+	0x0F120073,
+	0x0F120067,
+	0x0F120064,
+	0x0F12006B,
+	0x0F12007C,
+	0x0F120094,
+	0x0F1200B7,
+	0x0F1200E1,
+	0x0F1200FF,
+	0x0F1200D6,
+	0x0F1200AE,
+	0x0F120085,
+	0x0F120068,
+	0x0F120054,
+	0x0F120048,
+	0x0F120045,
+	0x0F12004B,
+	0x0F12005B,
+	0x0F120073,
+	0x0F120093,
+	0x0F1200BF,
+	0x0F1200E9,
+	0x0F1200B8,
+	0x0F12008E,
+	0x0F120066,
+	0x0F120049,
+	0x0F120035,
+	0x0F120028,
+	0x0F120025,
+	0x0F12002B,
+	0x0F12003B,
+	0x0F120053,
+	0x0F120072,
+	0x0F12009D,
+	0x0F1200C8,
+	0x0F1200A2,
+	0x0F120078,
+	0x0F120051,
+	0x0F120034,
+	0x0F12001F,
+	0x0F120012,
+	0x0F12000E,
+	0x0F120014,
+	0x0F120024,
+	0x0F12003B,
+	0x0F12005B,
+	0x0F120083,
+	0x0F1200AD,
+	0x0F120095,
+	0x0F12006C,
+	0x0F120046,
+	0x0F12002A,
+	0x0F120014,
+	0x0F120007,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F12002D,
+	0x0F12004C,
+	0x0F120072,
+	0x0F12009B,
+	0x0F120093,
+	0x0F12006A,
+	0x0F120045,
+	0x0F120028,
+	0x0F120013,
+	0x0F120005,
+	0x0F120000,
+	0x0F120004,
+	0x0F120012,
+	0x0F120028,
+	0x0F120045,
+	0x0F12006A,
+	0x0F120093,
+	0x0F12009B,
+	0x0F120071,
+	0x0F12004C,
+	0x0F120030,
+	0x0F12001A,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000B,
+	0x0F120018,
+	0x0F12002C,
+	0x0F120048,
+	0x0F12006D,
+	0x0F120097,
+	0x0F1200AE,
+	0x0F120083,
+	0x0F12005C,
+	0x0F120040,
+	0x0F12002B,
+	0x0F12001E,
+	0x0F120018,
+	0x0F12001C,
+	0x0F120027,
+	0x0F12003A,
+	0x0F120055,
+	0x0F12007B,
+	0x0F1200A6,
+	0x0F1200CA,
+	0x0F12009E,
+	0x0F120076,
+	0x0F120059,
+	0x0F120046,
+	0x0F120039,
+	0x0F120033,
+	0x0F120036,
+	0x0F120040,
+	0x0F120052,
+	0x0F12006C,
+	0x0F120094,
+	0x0F1200BF,
+	0x0F1200EB,
+	0x0F1200C3,
+	0x0F120099,
+	0x0F12007A,
+	0x0F120066,
+	0x0F12005A,
+	0x0F120054,
+	0x0F120056,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008D,
+	0x0F1200B6,
+	0x0F1200DE,
+	0x0F12010D,
+	0x0F1200E7,
+	0x0F1200C1,
+	0x0F1200A0,
+	0x0F12008A,
+	0x0F12007C,
+	0x0F120076,
+	0x0F120078,
+	0x0F120081,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200D5,
+	0x0F1200FD,
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F1203B4, /*038F awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F1203C0, /*039B awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F12037C, /*0373 awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203C8, /*03B0 awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F12035E, /*0352 awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203C8, /*03B7 awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120340, /*0334 awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203C0, /*03B5 awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120328, /*0318 awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /*03B0 awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F120310, /*02FF awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12039E, /*038D awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202FA, /*02E7 awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120384, /*0372 awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202DC, /*02D0 awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12036C, /*035D awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202CA, /*02B5 awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F12035A, /*0345 awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202B4, /*02A1 awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120340, /*0331 awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12029E, /*028B awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F120324, /*031E awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F12028C, /*0273 awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120306, /*0309 awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12027A, /*025F awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F6, /*02F5 awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F12026A, /*0250 awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202E4, /*02DB awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F12025A, /*0241 awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202DA, /*02C7 awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F12024C, /*0233 awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202CE, /*02B9 awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F12023A, /*0223 awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202C4, /*02AB awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120230, /*0217 awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202B8, /*02A2 awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120220, /*0207 awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F1202AC, /*0294 awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F120212, /*01FA awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F1202AA, /*0289 awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F120204, /*01EA awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F1202A6, /*0281 awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201FA, /*01DD awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F1202A0, /*027B awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201EE, /*01D0 awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F12029C, /*0273 awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201E0, /*01C3 awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F120294, /*026A awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201D4, /*01B6 awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F12028A, /*0265 awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201C8, /*01AB awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F120282, /*025B awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201C0, /*01A1 awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F12027A, /*0254 awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F1201BC, /*0198 awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F120272, /*024B awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F1201B8, /*0192 awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120262, /*0242 awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F1201BC, /*0191 awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12024E, /*023A awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F1201EC, /*0192 awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120206, /*0222 awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /*01C5 awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /*01DF awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001F,
+	0x0F120000,
+	0x0F12010E,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /*025E*/
+	0x0F120282, /*0282*/
+	0x0F120246, /*0240*/
+	0x0F12029E, /*0298*/
+	0x0F120230, /*022A*/
+	0x0F1202A0, /*029A*/
+	0x0F120220, /*021A*/
+	0x0F1202A0, /*029A*/
+	0x0F12020E, /*0206*/
+	0x0F12029E, /*0298*/
+	0x0F120206, /*01FE*/
+	0x0F120292, /*028C*/
+	0x0F120200, /*01FA*/
+	0x0F12027E, /*0278*/
+	0x0F1201FE, /*01F8*/
+	0x0F12026A, /*0266*/
+	0x0F12021A, /*0214*/
+	0x0F12023E, /*0238*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120208,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_0__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_0__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_0__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_1__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_1__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_1__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_2__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_2__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_2__5_       */
+	
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_0__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_0__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_0__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_0__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_1__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_1__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_1__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_1__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_2__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_2__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_2__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_2__5_     */
+	
+	0x0F1202EA, /*awbb_GridConst_1_0_    */
+	0x0F120335, /*awbb_GridConst_1_1_    */
+	0x0F120388, /*awbb_GridConst_1_2_    */
+	
+	0x0F121032, /*1032 awbb_GridConst_2_0    */
+	0x0F1210B2, /*10B2 awbb_GridConst_2_1    */
+	0x0F121140, /*1124 awbb_GridConst_2_2    */
+	0x0F121141, /*112A awbb_GridConst_2_3    */
+	0x0F1211BE, /*11A4 awbb_GridConst_2_4    */
+	0x0F12124C, /*1272 awbb_GridConst_2_5    */
+	
+	0x0F1200B3, /*awbb_GridCoeff_R_1    */
+	0x0F1200B7, /*awbb_GridCoeff_B_1    */
+	0x0F1200D3, /*awbb_GridCoeff_R_2    */
+	0x0F120091, /*awbb_GridCoeff_B_2    */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,  /*--- 52A awbb_MvEq_RBthresh */
+	
+	/* Gamut Thresholds */
+	0x002A0DAA,
+	0x0F120664, /*--- 71A */
+	0x0F120355, /*--- 3A4 */
+	0x002A0DAE,
+	0x0F12002C, /*--- 36 */
+	0x0F120024, /*--- 1C */
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120E01,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120256, /*-- 256 */
+	0x0F120248, /*-- 248 */
+	0x002A0D96,
+	0x0F120E00,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable*/
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120258,
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* CCM */
+	0x002A2800,
+	0x0F12010D, /*-0136---*/  /* H */
+	0x0F12FFA7, /*-FF8B---*/
+	0x0F12FFF5, /*-FFE8---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+	
+	0x0F12010D, /*-010D---*/  /* A */
+	0x0F12FFA7, /*-FFA7---*/
+	0x0F12FFF5, /*-FFF5---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+	
+	0x0F120205, /*01A5   01A5*/  /* WW */
+	0x0F12FF92, /*FF9D   FF9D*/
+	0x0F12FFE6, /*FFE1   FFE1*/
+	0x0F1200FE, /*00F2   00D9*/
+	0x0F1200E2, /*0116   0153*/
+	0x0F12FF33, /*FF48   FF25*/
+	0x0F12FF1E, /*FF3A   FF25*/
+	0x0F120222, /*0263   028C*/
+	0x0F12FF68, /*FF3A   FF25*/
+	0x0F12FF03, /*FEBF   FEBF*/
+	0x0F120207, /*01B6   01B6*/
+	0x0F120113, /*00F7   00F7*/
+	0x0F12FFE3, /*FF81   FF81*/
+	0x0F12FFC0, /*FF8C   FF8C*/
+	0x0F120181, /*01AE   01AE*/
+	0x0F120164, /*00FC   00FC*/
+	0x0F12FF55, /*FF48   FF48*/
+	0x0F120163, /*010D   010D*/
+	
+	0x0F120205, /*01BD  01BD*/  /* CW */
+	0x0F12FF92, /*FF89  FF89*/
+	0x0F12FFE6, /*FFDE  FFDE*/
+	0x0F1200FE, /*00C9  0098*/
+	0x0F1200E2, /*00B1  00B8*/
+	0x0F12FF33, /*FF3F  FF69*/
+	0x0F12FF1E, /*FF2D  FF15*/
+	0x0F120222, /*0230  025A*/
+	0x0F12FF68, /*FF77  FF65*/
+	0x0F12FF03, /*FF03  FF03*/
+	0x0F120207, /*0207  0207*/
+	0x0F120113, /*0113  0113*/
+	0x0F12FFE3, /*FFDA  FFDA*/
+	0x0F12FFC0, /*FFB8  FFB8*/
+	0x0F120181, /*0166  0166*/
+	0x0F120164, /*0164  0164*/
+	0x0F12FF55, /*FF55  FF55*/
+	0x0F120163, /*0163  0163*/
+	
+	0x0F12018A, /*-0171---*/  /* D50 */
+	0x0F12FFC1, /*-FFAF---*/
+	0x0F12FFF5, /*-FFF3---*/
+	0x0F120086, /*-0086---*/
+	0x0F1200D2, /*-00D2---*/
+	0x0F12FF73, /*-FF73---*/
+	0x0F12FF0B, /*-FF17---*/
+	0x0F120232, /*-022B---*/
+	0x0F12FF49, /*-FF54---*/
+	0x0F12FF43, /*-FF43---*/
+	0x0F1201BA, /*-01BA---*/
+	0x0F1200F3, /*-00F3---*/
+	0x0F12FFE2, /*-FFF6---*/
+	0x0F12FFB6, /*-FFD0---*/
+	0x0F1201E6, /*-01B8---*/
+	0x0F12018F, /*-018F---*/
+	0x0F12FF8C, /*-FF8C---*/
+	0x0F120137, /*-0137---*/
+	
+	0x0F12018A, /*-0180---*/  /* D65 */   
+	0x0F12FFC1, /*-FFC2---*/
+	0x0F12FFF5, /*-FFFD---*/
+	0x0F120086, /*-0086---*/
+	0x0F1200D2, /*-00D2---*/
+	0x0F12FF73, /*-FF73---*/
+	0x0F12FF0B, /*-FF25---*/
+	0x0F120232, /*-022B---*/
+	0x0F12FF49, /*-FF61---*/
+	0x0F12FF43, /*-FF43---*/
+	0x0F1201BA, /*-01BA---*/
+	0x0F1200F3, /*-00F3---*/
+	0x0F12FFE2, /*-FFED---*/
+	0x0F12FFB6, /*-FFC4---*/
+	0x0F1201E6, /*-01CD---*/
+	0x0F12018F, /*-018F---*/
+	0x0F12FF8C, /*-FF8C---*/
+	0x0F120137, /*-0137---*/
+	
+	0x0F1201CC, /*----*/ /* OUT */
+	0x0F12FFC3, /*----*/
+	0x0F120009, /*----*/
+	0x0F12009D, /*----*/
+	0x0F1200FA, /*----*/
+	0x0F12FF50, /*----*/
+	0x0F12FED8, /*----*/
+	0x0F1201FE, /*----*/
+	0x0F12FF08, /*----*/
+	0x0F12FEC7, /*----*/
+	0x0F1200F5, /*----*/
+	0x0F120119, /*----*/
+	0x0F12FFDF, /*----*/
+	0x0F120024, /*----*/
+	0x0F1201A8, /*----*/
+	0x0F120170, /*----*/
+	0x0F12FFAD, /*----*/
+	0x0F12011B, /*----*/
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+	
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120012, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A08AA, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120009, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A0928, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A09A6, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A0A24, /* --                                                         */
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x002A0AA2, /* --                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001,
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+
+	/* Recording 25fps Anti-Flicker 60Hz END of Initial */
+};
+#else
+/* Recording with 25fps */
+static const u32 s5k5bafx_recording_50Hz_common[] = {
+
+	/* recording 25fps Anti-Flicker 50Hz*/
+	
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* p100	Delay */
+	
+	
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* -- */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+	
+	
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /* uMaxExp1 */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /* uMaxExp2 */
+	0x0F120000,
+	0x0F12A122, /* uMaxExp3 */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /* uMaxExp4 */
+	0x0F120000,
+	0x002A043A,
+	0x0F120200,
+	0x0F120200,
+	0x002A0494,
+	0x0F120300,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /* ae_StatMode */
+	
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202A8,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120298,
+	
+	/* 1. Auto Flicker 50Hz Start */
+	0x002A0B2E,
+	0x0F120000, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12005F, /* REG_TC_DBG_AutoAlgEnBits   default : 007F */
+	
+	
+	0xffff000a, /* p10	Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+	
+	/* Parallel or MIPI Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+	
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+	
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 30fps) */
+	0x002A0242,
+#if 0
+	/*++ 640x480 */
+	/* 0x0F120280, */ /* REG_0TC_PCFG_usWidth */
+	/* 0x0F1201E0, */ /* REG_0TC_PCFG_usHeight */
+	/*-- 640x480 */
+#else
+	/*++ 800x600 */
+	0x0F120320, /* REG_0TC_PCFG_usWidth */
+	0x0F120258, /* REG_0TC_PCFG_usHeight */
+	/*-- 800x600 */
+#endif
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052, /*-*/
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F120190, /*-535-*/
+	0x0F120190, /*-29A-*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+	
+	/* Apply preview config */
+	/* 0x002A021C, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActivePrevConfig */
+	/* 0x002A0220, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevOpenAfterChange */
+	/* 0x002A01F8, */
+	/* 0x0F120001, */ /* REG_TC_GP_NewConfigSync */
+	/* 0x002A021E, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevConfigChanged */
+	/* 0x002A01F0, */
+	/* 0x0F120001, */ /* REG_TC_GP_EnablePreview */
+	/* 0x0F120001, */ /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160,
+	0x0F120134,
+	0x0F1200FF,
+	0x0F1200D1,
+	0x0F1200B1,
+	0x0F12009D,
+	0x0F120096,
+	0x0F12009E,
+	0x0F1200B3,
+	0x0F1200D3,
+	0x0F1200FF,
+	0x0F120131,
+	0x0F120159,
+	0x0F12013C,
+	0x0F120107,
+	0x0F1200CD,
+	0x0F1200A1,
+	0x0F120080,
+	0x0F12006B,
+	0x0F120064,
+	0x0F12006C,
+	0x0F120080,
+	0x0F1200A1,
+	0x0F1200CD,
+	0x0F120106,
+	0x0F120139,
+	0x0F120116,
+	0x0F1200DC,
+	0x0F1200A2,
+	0x0F120073,
+	0x0F120051,
+	0x0F12003B,
+	0x0F120033,
+	0x0F12003B,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A2,
+	0x0F1200DD,
+	0x0F120115,
+	0x0F1200FA,
+	0x0F1200BF,
+	0x0F120085,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001B,
+	0x0F120014,
+	0x0F12001A,
+	0x0F120031,
+	0x0F120055,
+	0x0F120085,
+	0x0F1200C0,
+	0x0F1200FB,
+	0x0F1200EA,
+	0x0F1200AF,
+	0x0F120074,
+	0x0F120045,
+	0x0F120020,
+	0x0F12000B,
+	0x0F120003,
+	0x0F12000A,
+	0x0F120020,
+	0x0F120046,
+	0x0F120076,
+	0x0F1200B1,
+	0x0F1200ED,
+	0x0F1200E6,
+	0x0F1200AA,
+	0x0F120071,
+	0x0F120041,
+	0x0F12001D,
+	0x0F120008,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001E,
+	0x0F120044,
+	0x0F120074,
+	0x0F1200B0,
+	0x0F1200EC,
+	0x0F1200EF,
+	0x0F1200B3,
+	0x0F12007A,
+	0x0F12004A,
+	0x0F120026,
+	0x0F120011,
+	0x0F12000A,
+	0x0F120011,
+	0x0F120029,
+	0x0F12004F,
+	0x0F120080,
+	0x0F1200BC,
+	0x0F1200F8,
+	0x0F120105,
+	0x0F1200C9,
+	0x0F12008F,
+	0x0F120060,
+	0x0F12003C,
+	0x0F120026,
+	0x0F12001F,
+	0x0F120028,
+	0x0F120040,
+	0x0F120066,
+	0x0F120097,
+	0x0F1200D4,
+	0x0F120110,
+	0x0F120124,
+	0x0F1200EB,
+	0x0F1200B1,
+	0x0F120082,
+	0x0F12005F,
+	0x0F12004A,
+	0x0F120043,
+	0x0F12004C,
+	0x0F120064,
+	0x0F120089,
+	0x0F1200BA,
+	0x0F1200F8,
+	0x0F12012F,
+	0x0F120147,
+	0x0F120116,
+	0x0F1200DE,
+	0x0F1200AF,
+	0x0F12008E,
+	0x0F12007A,
+	0x0F120072,
+	0x0F12007A,
+	0x0F120091,
+	0x0F1200B6,
+	0x0F1200E8,
+	0x0F120121,
+	0x0F120150,
+	0x0F120170,
+	0x0F12013F,
+	0x0F120110,
+	0x0F1200E2,
+	0x0F1200C0,
+	0x0F1200AB,
+	0x0F1200A4,
+	0x0F1200AC,
+	0x0F1200C3,
+	0x0F1200E6,
+	0x0F120117,
+	0x0F120145,
+	0x0F120172,
+	0x0F120127,
+	0x0F120100,
+	0x0F1200CF,
+	0x0F1200A7,
+	0x0F12008D,
+	0x0F12007D,
+	0x0F120077,
+	0x0F12007A,
+	0x0F120087,
+	0x0F12009E,
+	0x0F1200C0,
+	0x0F1200EC,
+	0x0F12010F,
+	0x0F120108,
+	0x0F1200D8,
+	0x0F1200A5,
+	0x0F120080,
+	0x0F120066,
+	0x0F120056,
+	0x0F12004F,
+	0x0F120053,
+	0x0F120061,
+	0x0F120077,
+	0x0F120098,
+	0x0F1200C6,
+	0x0F1200F3,
+	0x0F1200E7,
+	0x0F1200B4,
+	0x0F120081,
+	0x0F12005C,
+	0x0F120041,
+	0x0F120030,
+	0x0F120029,
+	0x0F12002E,
+	0x0F12003D,
+	0x0F120055,
+	0x0F120076,
+	0x0F1200A5,
+	0x0F1200D4,
+	0x0F1200CF,
+	0x0F12009B,
+	0x0F12006A,
+	0x0F120043,
+	0x0F120027,
+	0x0F120016,
+	0x0F12000F,
+	0x0F120015,
+	0x0F120025,
+	0x0F12003E,
+	0x0F120061,
+	0x0F12008E,
+	0x0F1200BF,
+	0x0F1200C2,
+	0x0F12008E,
+	0x0F12005D,
+	0x0F120037,
+	0x0F12001A,
+	0x0F120009,
+	0x0F120002,
+	0x0F120007,
+	0x0F120018,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200BE,
+	0x0F12008A,
+	0x0F12005A,
+	0x0F120034,
+	0x0F120017,
+	0x0F120006,
+	0x0F120000,
+	0x0F120006,
+	0x0F120017,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200C5,
+	0x0F120091,
+	0x0F120061,
+	0x0F12003B,
+	0x0F120020,
+	0x0F12000F,
+	0x0F120009,
+	0x0F120010,
+	0x0F120021,
+	0x0F12003D,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BE,
+	0x0F1200D7,
+	0x0F1200A2,
+	0x0F120072,
+	0x0F12004D,
+	0x0F120032,
+	0x0F120022,
+	0x0F12001D,
+	0x0F120024,
+	0x0F120035,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A0,
+	0x0F1200D2,
+	0x0F1200F0,
+	0x0F1200BE,
+	0x0F12008C,
+	0x0F120068,
+	0x0F12004F,
+	0x0F120040,
+	0x0F12003B,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006C,
+	0x0F12008E,
+	0x0F1200BE,
+	0x0F1200ED,
+	0x0F12010C,
+	0x0F1200E1,
+	0x0F1200AF,
+	0x0F12008A,
+	0x0F120072,
+	0x0F120064,
+	0x0F12005F,
+	0x0F120065,
+	0x0F120074,
+	0x0F12008D,
+	0x0F1200B2,
+	0x0F1200E0,
+	0x0F12010A,
+	0x0F12012F,
+	0x0F120104,
+	0x0F1200D9,
+	0x0F1200B3,
+	0x0F120099,
+	0x0F12008B,
+	0x0F120086,
+	0x0F12008B,
+	0x0F12009B,
+	0x0F1200B5,
+	0x0F1200DA,
+	0x0F120101,
+	0x0F120128,
+	0x0F12012F,
+	0x0F120106,
+	0x0F1200D4,
+	0x0F1200AA,
+	0x0F12008E,
+	0x0F12007D,
+	0x0F120079,
+	0x0F120080,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200DC,
+	0x0F12010C,
+	0x0F120130,
+	0x0F120112,
+	0x0F1200E0,
+	0x0F1200AB,
+	0x0F120083,
+	0x0F120067,
+	0x0F120057,
+	0x0F120051,
+	0x0F120059,
+	0x0F12006B,
+	0x0F120089,
+	0x0F1200B2,
+	0x0F1200E5,
+	0x0F120114,
+	0x0F1200F2,
+	0x0F1200BD,
+	0x0F120088,
+	0x0F120061,
+	0x0F120044,
+	0x0F120031,
+	0x0F12002C,
+	0x0F120033,
+	0x0F120047,
+	0x0F120065,
+	0x0F12008C,
+	0x0F1200C0,
+	0x0F1200F3,
+	0x0F1200DB,
+	0x0F1200A5,
+	0x0F120071,
+	0x0F120049,
+	0x0F12002A,
+	0x0F120018,
+	0x0F120011,
+	0x0F120018,
+	0x0F12002C,
+	0x0F12004B,
+	0x0F120072,
+	0x0F1200A3,
+	0x0F1200D7,
+	0x0F1200CD,
+	0x0F120097,
+	0x0F120065,
+	0x0F12003C,
+	0x0F12001D,
+	0x0F12000A,
+	0x0F120003,
+	0x0F120009,
+	0x0F12001D,
+	0x0F12003B,
+	0x0F120063,
+	0x0F120092,
+	0x0F1200C4,
+	0x0F1200CA,
+	0x0F120094,
+	0x0F120062,
+	0x0F12003A,
+	0x0F12001A,
+	0x0F120007,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120036,
+	0x0F12005C,
+	0x0F12008A,
+	0x0F1200BC,
+	0x0F1200D1,
+	0x0F12009B,
+	0x0F120069,
+	0x0F120042,
+	0x0F120022,
+	0x0F12000F,
+	0x0F120008,
+	0x0F12000D,
+	0x0F12001F,
+	0x0F12003B,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BF,
+	0x0F1200E3,
+	0x0F1200AC,
+	0x0F12007A,
+	0x0F120053,
+	0x0F120035,
+	0x0F120022,
+	0x0F12001B,
+	0x0F12001F,
+	0x0F120030,
+	0x0F12004B,
+	0x0F12006D,
+	0x0F12009C,
+	0x0F1200CE,
+	0x0F1200FE,
+	0x0F1200C9,
+	0x0F120095,
+	0x0F12006F,
+	0x0F120052,
+	0x0F120040,
+	0x0F120039,
+	0x0F12003D,
+	0x0F12004B,
+	0x0F120063,
+	0x0F120086,
+	0x0F1200B5,
+	0x0F1200E6,
+	0x0F12011B,
+	0x0F1200ED,
+	0x0F1200BA,
+	0x0F120092,
+	0x0F120076,
+	0x0F120065,
+	0x0F12005D,
+	0x0F120060,
+	0x0F12006D,
+	0x0F120084,
+	0x0F1200A8,
+	0x0F1200D6,
+	0x0F120101,
+	0x0F120140,
+	0x0F120112,
+	0x0F1200E5,
+	0x0F1200BD,
+	0x0F12009E,
+	0x0F12008C,
+	0x0F120085,
+	0x0F120087,
+	0x0F120094,
+	0x0F1200AC,
+	0x0F1200D0,
+	0x0F1200F8,
+	0x0F120123,
+	0x0F1200F2,
+	0x0F1200D1,
+	0x0F1200A7,
+	0x0F120087,
+	0x0F120073,
+	0x0F120067,
+	0x0F120064,
+	0x0F12006B,
+	0x0F12007C,
+	0x0F120094,
+	0x0F1200B7,
+	0x0F1200E1,
+	0x0F1200FF,
+	0x0F1200D6,
+	0x0F1200AE,
+	0x0F120085,
+	0x0F120068,
+	0x0F120054,
+	0x0F120048,
+	0x0F120045,
+	0x0F12004B,
+	0x0F12005B,
+	0x0F120073,
+	0x0F120093,
+	0x0F1200BF,
+	0x0F1200E9,
+	0x0F1200B8,
+	0x0F12008E,
+	0x0F120066,
+	0x0F120049,
+	0x0F120035,
+	0x0F120028,
+	0x0F120025,
+	0x0F12002B,
+	0x0F12003B,
+	0x0F120053,
+	0x0F120072,
+	0x0F12009D,
+	0x0F1200C8,
+	0x0F1200A2,
+	0x0F120078,
+	0x0F120051,
+	0x0F120034,
+	0x0F12001F,
+	0x0F120012,
+	0x0F12000E,
+	0x0F120014,
+	0x0F120024,
+	0x0F12003B,
+	0x0F12005B,
+	0x0F120083,
+	0x0F1200AD,
+	0x0F120095,
+	0x0F12006C,
+	0x0F120046,
+	0x0F12002A,
+	0x0F120014,
+	0x0F120007,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F12002D,
+	0x0F12004C,
+	0x0F120072,
+	0x0F12009B,
+	0x0F120093,
+	0x0F12006A,
+	0x0F120045,
+	0x0F120028,
+	0x0F120013,
+	0x0F120005,
+	0x0F120000,
+	0x0F120004,
+	0x0F120012,
+	0x0F120028,
+	0x0F120045,
+	0x0F12006A,
+	0x0F120093,
+	0x0F12009B,
+	0x0F120071,
+	0x0F12004C,
+	0x0F120030,
+	0x0F12001A,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000B,
+	0x0F120018,
+	0x0F12002C,
+	0x0F120048,
+	0x0F12006D,
+	0x0F120097,
+	0x0F1200AE,
+	0x0F120083,
+	0x0F12005C,
+	0x0F120040,
+	0x0F12002B,
+	0x0F12001E,
+	0x0F120018,
+	0x0F12001C,
+	0x0F120027,
+	0x0F12003A,
+	0x0F120055,
+	0x0F12007B,
+	0x0F1200A6,
+	0x0F1200CA,
+	0x0F12009E,
+	0x0F120076,
+	0x0F120059,
+	0x0F120046,
+	0x0F120039,
+	0x0F120033,
+	0x0F120036,
+	0x0F120040,
+	0x0F120052,
+	0x0F12006C,
+	0x0F120094,
+	0x0F1200BF,
+	0x0F1200EB,
+	0x0F1200C3,
+	0x0F120099,
+	0x0F12007A,
+	0x0F120066,
+	0x0F12005A,
+	0x0F120054,
+	0x0F120056,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008D,
+	0x0F1200B6,
+	0x0F1200DE,
+	0x0F12010D,
+	0x0F1200E7,
+	0x0F1200C1,
+	0x0F1200A0,
+	0x0F12008A,
+	0x0F12007C,
+	0x0F120076,
+	0x0F120078,
+	0x0F120081,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200D5,
+	0x0F1200FD,
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	0x0F120000, /*0000*/
+	0x0F120002, /*0002*/
+	0x0F120005, /*0008*/
+	0x0F12000A, /*001A*/
+	0x0F120072, /*0066*/
+	0x0F120106, /*00E6*/
+	0x0F120150, /*0141*/
+	0x0F12018E, /*0188*/
+	0x0F1201F4, /*01E6*/
+	0x0F120240, /*0236*/
+	0x0F1202C4, /*02BA*/
+	0x0F120332, /*032A*/
+	0x0F120385, /*0385*/
+	0x0F1203C2, /*03C2*/
+	0x0F1203EA, /*03EA*/
+	0x0F1203FF, /*03FF*/
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F1203B4, /*038F awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F1203C0, /*039B awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F12037C, /*0373 awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203C8, /*03B0 awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F12035E, /*0352 awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203C8, /*03B7 awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120340, /*0334 awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203C0, /*03B5 awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120328, /*0318 awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /*03B0 awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F120310, /*02FF awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12039E, /*038D awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202FA, /*02E7 awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120384, /*0372 awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202DC, /*02D0 awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12036C, /*035D awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202CA, /*02B5 awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F12035A, /*0345 awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202B4, /*02A1 awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120340, /*0331 awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12029E, /*028B awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F120324, /*031E awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F12028C, /*0273 awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120306, /*0309 awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12027A, /*025F awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F6, /*02F5 awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F12026A, /*0250 awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202E4, /*02DB awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F12025A, /*0241 awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202DA, /*02C7 awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F12024C, /*0233 awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202CE, /*02B9 awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F12023A, /*0223 awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202C4, /*02AB awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120230, /*0217 awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202B8, /*02A2 awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120220, /*0207 awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F1202AC, /*0294 awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F120212, /*01FA awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F1202AA, /*0289 awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F120204, /*01EA awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F1202A6, /*0281 awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201FA, /*01DD awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F1202A0, /*027B awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201EE, /*01D0 awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F12029C, /*0273 awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201E0, /*01C3 awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F120294, /*026A awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201D4, /*01B6 awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F12028A, /*0265 awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201C8, /*01AB awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F120282, /*025B awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201C0, /*01A1 awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F12027A, /*0254 awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F1201BC, /*0198 awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F120272, /*024B awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F1201B8, /*0192 awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120262, /*0242 awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F1201BC, /*0191 awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12024E, /*023A awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F1201EC, /*0192 awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120206, /*0222 awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /*01C5 awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /*01DF awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /*0000 awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001F,
+	0x0F120000,
+	0x0F12010E,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /*025E*/
+	0x0F120282, /*0282*/
+	0x0F120246, /*0240*/
+	0x0F12029E, /*0298*/
+	0x0F120230, /*022A*/
+	0x0F1202A0, /*029A*/
+	0x0F120220, /*021A*/
+	0x0F1202A0, /*029A*/
+	0x0F12020E, /*0206*/
+	0x0F12029E, /*0298*/
+	0x0F120206, /*01FE*/
+	0x0F120292, /*028C*/
+	0x0F120200, /*01FA*/
+	0x0F12027E, /*0278*/
+	0x0F1201FE, /*01F8*/
+	0x0F12026A, /*0266*/
+	0x0F12021A, /*0214*/
+	0x0F12023E, /*0238*/
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120208,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_0__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_0__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_0__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_0__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_0__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_1__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_1__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_1__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_1__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_1__5_       */
+	0x0F12FFEC, /*FFEC awbb_GridCorr_R_2__0_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__1_       */
+	0x0F12FFE2, /*FFE2 awbb_GridCorr_R_2__2_       */
+	0x0F120050, /*0050 awbb_GridCorr_R_2__3_       */
+	0x0F120000, /*FFF0 awbb_GridCorr_R_2__4_       */
+	0x0F12005A, /*005A awbb_GridCorr_R_2__5_       */
+	
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_0__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_0__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_0__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_0__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_0__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_1__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_1__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_1__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_1__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_1__5_     */
+	0x0F12FFB5, /*FFB5 awbb_GridCorr_B_2__0_     */
+	0x0F12FFC9, /*FFC9 awbb_GridCorr_B_2__1_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__2_     */
+	0x0F12FFD8, /*FFD8 awbb_GridCorr_B_2__3_     */
+	0x0F12FF88, /*FFAC awbb_GridCorr_B_2__4_     */
+	0x0F12FEA0, /*FEA0 awbb_GridCorr_B_2__5_     */
+	
+	0x0F1202EA, /*awbb_GridConst_1_0_    */
+	0x0F120335, /*awbb_GridConst_1_1_    */
+	0x0F120388, /*awbb_GridConst_1_2_    */
+	
+	0x0F121032, /*1032 awbb_GridConst_2_0    */
+	0x0F1210B2, /*10B2 awbb_GridConst_2_1    */
+	0x0F121140, /*1124 awbb_GridConst_2_2    */
+	0x0F121141, /*112A awbb_GridConst_2_3    */
+	0x0F1211BE, /*11A4 awbb_GridConst_2_4    */
+	0x0F12124C, /*1272 awbb_GridConst_2_5    */
+	
+	0x0F1200B3, /*awbb_GridCoeff_R_1    */
+	0x0F1200B7, /*awbb_GridCoeff_B_1    */
+	0x0F1200D3, /*awbb_GridCoeff_R_2    */
+	0x0F120091, /*awbb_GridCoeff_B_2    */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,  /*--- 52A awbb_MvEq_RBthresh */
+	
+	/* Gamut Thresholds */
+	0x002A0DAA,
+	0x0F120664, /*--- 71A */
+	0x0F120355, /*--- 3A4 */
+	0x002A0DAE,
+	0x0F12002C, /*--- 36 */
+	0x0F120024, /*--- 1C */
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120E01,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120256, /*-- 256 */
+	0x0F120248, /*-- 248 */
+	0x002A0D96,
+	0x0F120E00,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable*/
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120258,
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* CCM */
+	0x002A2800,
+	0x0F12010D, /*-0136---*/  /* H */
+	0x0F12FFA7, /*-FF8B---*/
+	0x0F12FFF5, /*-FFE8---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+	
+	0x0F12010D, /*-010D---*/  /* A */
+	0x0F12FFA7, /*-FFA7---*/
+	0x0F12FFF5, /*-FFF5---*/
+	0x0F12003B, /*-0037---*/
+	0x0F1200EF, /*-00CD---*/
+	0x0F12FF38, /*-FF5E---*/
+	0x0F12FE42, /*-FE42---*/
+	0x0F120270, /*-0270---*/
+	0x0F12FF71, /*-FF71---*/
+	0x0F12FEED, /*-FEED---*/
+	0x0F120198, /*-0198---*/
+	0x0F120198, /*-0198---*/
+	0x0F12FF95, /*-FF95---*/
+	0x0F12FFA3, /*-FFA3---*/
+	0x0F120260, /*-0260---*/
+	0x0F1200EC, /*-00EC---*/
+	0x0F12FF33, /*-FF33---*/
+	0x0F1200F4, /*-00F4---*/
+	
+	0x0F120205, /*01A5   01A5*/  /* WW */
+	0x0F12FF92, /*FF9D   FF9D*/
+	0x0F12FFE6, /*FFE1   FFE1*/
+	0x0F1200FE, /*00F2   00D9*/
+	0x0F1200E2, /*0116   0153*/
+	0x0F12FF33, /*FF48   FF25*/
+	0x0F12FF1E, /*FF3A   FF25*/
+	0x0F120222, /*0263   028C*/
+	0x0F12FF68, /*FF3A   FF25*/
+	0x0F12FF03, /*FEBF   FEBF*/
+	0x0F120207, /*01B6   01B6*/
+	0x0F120113, /*00F7   00F7*/
+	0x0F12FFE3, /*FF81   FF81*/
+	0x0F12FFC0, /*FF8C   FF8C*/
+	0x0F120181, /*01AE   01AE*/
+	0x0F120164, /*00FC   00FC*/
+	0x0F12FF55, /*FF48   FF48*/
+	0x0F120163, /*010D   010D*/
+	
+	0x0F120205, /*01BD  01BD*/  /* CW */
+	0x0F12FF92, /*FF89  FF89*/
+	0x0F12FFE6, /*FFDE  FFDE*/
+	0x0F1200FE, /*00C9  0098*/
+	0x0F1200E2, /*00B1  00B8*/
+	0x0F12FF33, /*FF3F  FF69*/
+	0x0F12FF1E, /*FF2D  FF15*/
+	0x0F120222, /*0230  025A*/
+	0x0F12FF68, /*FF77  FF65*/
+	0x0F12FF03, /*FF03  FF03*/
+	0x0F120207, /*0207  0207*/
+	0x0F120113, /*0113  0113*/
+	0x0F12FFE3, /*FFDA  FFDA*/
+	0x0F12FFC0, /*FFB8  FFB8*/
+	0x0F120181, /*0166  0166*/
+	0x0F120164, /*0164  0164*/
+	0x0F12FF55, /*FF55  FF55*/
+	0x0F120163, /*0163  0163*/
+	
+	0x0F12018A, /*-0171---*/  /* D50 */
+	0x0F12FFC1, /*-FFAF---*/
+	0x0F12FFF5, /*-FFF3---*/
+	0x0F120086, /*-0086---*/
+	0x0F1200D2, /*-00D2---*/
+	0x0F12FF73, /*-FF73---*/
+	0x0F12FF0B, /*-FF17---*/
+	0x0F120232, /*-022B---*/
+	0x0F12FF49, /*-FF54---*/
+	0x0F12FF43, /*-FF43---*/
+	0x0F1201BA, /*-01BA---*/
+	0x0F1200F3, /*-00F3---*/
+	0x0F12FFE2, /*-FFF6---*/
+	0x0F12FFB6, /*-FFD0---*/
+	0x0F1201E6, /*-01B8---*/
+	0x0F12018F, /*-018F---*/
+	0x0F12FF8C, /*-FF8C---*/
+	0x0F120137, /*-0137---*/
+	
+	0x0F12018A, /*-0180---*/  /* D65 */   
+	0x0F12FFC1, /*-FFC2---*/
+	0x0F12FFF5, /*-FFFD---*/
+	0x0F120086, /*-0086---*/
+	0x0F1200D2, /*-00D2---*/
+	0x0F12FF73, /*-FF73---*/
+	0x0F12FF0B, /*-FF25---*/
+	0x0F120232, /*-022B---*/
+	0x0F12FF49, /*-FF61---*/
+	0x0F12FF43, /*-FF43---*/
+	0x0F1201BA, /*-01BA---*/
+	0x0F1200F3, /*-00F3---*/
+	0x0F12FFE2, /*-FFED---*/
+	0x0F12FFB6, /*-FFC4---*/
+	0x0F1201E6, /*-01CD---*/
+	0x0F12018F, /*-018F---*/
+	0x0F12FF8C, /*-FF8C---*/
+	0x0F120137, /*-0137---*/
+	
+	0x0F1201CC, /*----*/ /* OUT */
+	0x0F12FFC3, /*----*/
+	0x0F120009, /*----*/
+	0x0F12009D, /*----*/
+	0x0F1200FA, /*----*/
+	0x0F12FF50, /*----*/
+	0x0F12FED8, /*----*/
+	0x0F1201FE, /*----*/
+	0x0F12FF08, /*----*/
+	0x0F12FEC7, /*----*/
+	0x0F1200F5, /*----*/
+	0x0F120119, /*----*/
+	0x0F12FFDF, /*----*/
+	0x0F120024, /*----*/
+	0x0F1201A8, /*----*/
+	0x0F120170, /*----*/
+	0x0F12FFAD, /*----*/
+	0x0F12011B, /*----*/
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /*afit_bUseNoiseInd 0 : NB 1: Noise Index */
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+	
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120012, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120009, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Recording 25fps Anti-Flicker 50Hz END of Initial */
+};
+#endif
+
+static const u32 s5k5bafx_stream_stop[] =
+{
+	0xFCFCD000,
+	0x00287000,
+ 	0x002A01F0,
+	0x0F120000, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged*/
+};
+
+#if (0)
+static const u32 s5k5bafx_stream_start[] =
+{
+	0xFCFCD000,
+	0x002AB00C,
+	0x0F120001,
+};
+#endif
+
+/*=================================
+*	CAMERA_BRIGHTNESS_1 (1/9) M4   *
+==================================*/
+static const u32 s5k5bafx_bright_m4[] =
+{
+	/* Brightness -4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FF88, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+*	CAMERA_BRIGHTNESS_2 (2/9) M3  *
+==================================*/
+
+static const u32 s5k5bafx_bright_m3[] =
+{
+	/* Brightness -3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFBC, /* REG_TC_UserBrightness*/
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_3 (3/9) M2
+==================================*/
+static const u32 s5k5bafx_bright_m2[] =
+{
+	/* Brightness -2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFDC, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_4 (4/9) M1
+==================================*/
+
+static const u32 s5k5bafx_bright_m1[] =
+{
+	/* Brightness -1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFF2, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_5 (5/9) Default
+==================================*/
+static const u32 s5k5bafx_bright_default[] =
+{
+	/* Brightness 0 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120000, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_6 (6/9) P1
+==================================*/
+static const u32 s5k5bafx_bright_p1[] =
+{
+	/* Brightness +1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120020, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_7 (7/9) P2
+==================================*/
+static const u32 s5k5bafx_bright_p2[] =
+{
+	/* Brightness +2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120040, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_8 (8/9) P3
+==================================*/
+static const u32 s5k5bafx_bright_p3[] =
+{
+	/* Brightness +3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120060, /* REG_TC_UserBrightness */
+
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_9 (9/9) P4
+==================================*/
+static const u32 s5k5bafx_bright_p4[] =
+{
+	/* Brightness +4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120080, /* REG_TC_UserBrightness */
+};
+
+/*******************************************************
+* CAMERA_VT_PRETTY_0 Default
+* 200s self cam pretty
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_default[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_1
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_1[] =
+{
+	/*0xffff000A,*/
+	0xFCFCD000,
+
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_2				*
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_2[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_3
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_3[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+
+};
+
+/* Don't delete it. */
+static const u32 s5k5bafx_fps_auto[] = {
+	0xFCFCD000,
+	0x00287000,
+};
+
+static const u32 s5k5bafx_fps_7fix[] =
+{
+	/* Fixed 7fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120535, /* 7fps */
+	0x0F120000,
+
+	/* 0x002A021C, */
+	/* 0x0F120000, *//* REG_TC_GP_ActivePrevConfig */
+	/* 0x002A0220, */
+	/* 0x0F120001, *//* REG_TC_GP_PrevOpenAfterChange */
+	/* 0x002A01F8, */
+	/* 0x0F120001, *//* REG_TC_GP_NewConfigSync */
+	/* 0x002A021E, */
+	/* 0x0F120001, *//* REG_TC_GP_PrevConfigChanged */
+	/* 0x002A01F0, */
+	/* 0x0F120001, *//* REG_TC_GP_EnablePreview */
+	/* 0x0F120001, *//* REG_TC_GP_EnablePreviewChanged */
+
+	/* 0xffff0096, *//* delay 150ms */
+
+	/* 0x0028D000, *//* mipi */
+	/* 0x002AB0CC, */
+	/* 0x0F12000B, */
+};
+
+static const u32 s5k5bafx_fps_10fix[] =
+{
+	/*  Fixed 10fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F1203E8, /* 10fps */
+	0x0F120000,
+};
+
+static const u32 s5k5bafx_fps_12fix[] =
+{
+	/*  Fixed 12fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120341, /* 12fps */
+	0x0F120000,
+};
+
+static const u32 s5k5bafx_fps_15fix[] =
+{
+	/* Fixed 15fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F12029A, /* 15fps*/
+	0x0F120000,
+};
+
+static const u32 s5k5bafx_fps_25fix[] =
+{
+	/* Fixed 25fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120190, /* 15fps*/
+	0x0F120000,
+};
+
+
+/*******************************************************
+*	CAMERA_DTP_ON
+*******************************************************/
+static const u32 s5k5bafx_pattern_on[] = {
+	0xffff01f4, /* Delay 500ms*/
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12FFF0, /* SARR_uNormBrInDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrInDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrInDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrInDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrInDoor[4] */
+	
+	0x002A07F6,
+	0x0F12FFF0, /* SARR_uNormBrOutDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrOutDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrOutDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrOutDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a3, /* gas bypass */
+	0x002a6600,
+	0x0f120001, /* ccm bypass */
+	0x002a6800,
+	0x0f120001, /* gamma bypass */
+	0x002a4400,
+	0x0f120001, /* awb bypass */
+
+	0x00287000,
+	0x002A03b6,
+	0x0F120001,
+	0x002A03ba,
+	0x0F120001, /* LEI control */
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120002, /* Colorbar pattern */
+	
+	0xffff0032, /* Delay 50msec */
+};
+
+/*******************************************************
+*	CAMERA_DTP_OFF
+*******************************************************/
+static const u32 s5k5bafx_pattern_off[] = {
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	0x002A07F6,
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a2, /* gas bypass */
+	0x002a6600,
+	0x0f120000, /* ccm bypass */
+	0x002a6800,
+	0x0f120000, /* gamma bypass */
+	0x002a4400,
+	0x0f120000, /* awb bypass */
+
+	0x00287000,
+	0x002A03F8,
+	0x0F120079,
+
+	0xffff012c, /* Delay 300ms */
+	0x002A03F8,
+	0x0F12007F,
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120000, /* Colorbar pattern */
+};
+
+#endif /* __S5K5BAFX_REGS_H */
diff --git a/drivers/media/video/s5k5bafx_setfile.h b/drivers/media/video/s5k5bafx_setfile.h
new file mode 100644
index 0000000..6e4f999
--- /dev/null
+++ b/drivers/media/video/s5k5bafx_setfile.h
@@ -0,0 +1,13473 @@
+/*
+ * Driver for S5K5BAFX 2M ISP from Samsung
+ *
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __S5K5BAFX_SETFILE_H
+#define __S5K5BAFX_SETFILE_H
+
+#include <linux/types.h>
+
+/*
+ * s5k5bafx register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name		: S5K5BAFX Initial Setfile
+* PLL mode	: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS		: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by	: ZEROHOY
+* Date		: 2011.03.07
+* History	:
+*******************************************************/
+static const u32 s5k5bafx_common[] = {
+	/* Self-Cam */
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064,
+
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA,
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+
+	0x0F120015,
+
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+
+	0x002AF900,
+	0x0F120067,
+
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+
+	0x002AF4D6,
+	0x0F120090,
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller*/
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+
+	0x002A10EE,
+	0x0F120000,
+
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A,
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB,
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,
+	0x0F120000,
+	0x0F12A122,
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0,
+	0x0F1201E0,
+	0x002A0494,
+	0x0F120300,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+
+	0x002A0E98,
+	0x0F1202A8,
+	0x002A0E9E,
+	0x0F120298,
+
+	/*1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12007F,
+
+	0xffff000a, /* Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz)*/
+	0x002A01D2,
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps)*/
+	0x002A0242,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F120535,
+	0x0F12029A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps)*/
+	0x002A0268,
+	0x0F120280,
+	0x0F1201E0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120000,
+	0x0F120000,
+	0x0F12029A,
+	0x0F12014D,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000,
+	0x002A0220,
+	0x0F120001,
+	0x002A01F8,
+	0x0F120001,
+	0x002A021E,
+	0x0F120001,
+	0x002A01F0,
+	0x0F120001,
+	0x0F120001,
+
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord*/
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+
+	/* param_start	wbt_AwbCcmCord*/
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120108, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160,
+	0x0F120134,
+	0x0F1200FF,
+	0x0F1200D1,
+	0x0F1200B1,
+	0x0F12009D,
+	0x0F120096,
+	0x0F12009E,
+	0x0F1200B3,
+	0x0F1200D3,
+	0x0F1200FF,
+	0x0F120131,
+	0x0F120159,
+	0x0F12013C,
+	0x0F120107,
+	0x0F1200CD,
+	0x0F1200A1,
+	0x0F120080,
+	0x0F12006B,
+	0x0F120064,
+	0x0F12006C,
+	0x0F120080,
+	0x0F1200A1,
+	0x0F1200CD,
+	0x0F120106,
+	0x0F120139,
+	0x0F120116,
+	0x0F1200DC,
+	0x0F1200A2,
+	0x0F120073,
+	0x0F120051,
+	0x0F12003B,
+	0x0F120033,
+	0x0F12003B,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A2,
+	0x0F1200DD,
+	0x0F120115,
+	0x0F1200FA,
+	0x0F1200BF,
+	0x0F120085,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001B,
+	0x0F120014,
+	0x0F12001A,
+	0x0F120031,
+	0x0F120055,
+	0x0F120085,
+	0x0F1200C0,
+	0x0F1200FB,
+	0x0F1200EA,
+	0x0F1200AF,
+	0x0F120074,
+	0x0F120045,
+	0x0F120020,
+	0x0F12000B,
+	0x0F120003,
+	0x0F12000A,
+	0x0F120020,
+	0x0F120046,
+	0x0F120076,
+	0x0F1200B1,
+	0x0F1200ED,
+	0x0F1200E6,
+	0x0F1200AA,
+	0x0F120071,
+	0x0F120041,
+	0x0F12001D,
+	0x0F120008,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001E,
+	0x0F120044,
+	0x0F120074,
+	0x0F1200B0,
+	0x0F1200EC,
+	0x0F1200EF,
+	0x0F1200B3,
+	0x0F12007A,
+	0x0F12004A,
+	0x0F120026,
+	0x0F120011,
+	0x0F12000A,
+	0x0F120011,
+	0x0F120029,
+	0x0F12004F,
+	0x0F120080,
+	0x0F1200BC,
+	0x0F1200F8,
+	0x0F120105,
+	0x0F1200C9,
+	0x0F12008F,
+	0x0F120060,
+	0x0F12003C,
+	0x0F120026,
+	0x0F12001F,
+	0x0F120028,
+	0x0F120040,
+	0x0F120066,
+	0x0F120097,
+	0x0F1200D4,
+	0x0F120110,
+	0x0F120124,
+	0x0F1200EB,
+	0x0F1200B1,
+	0x0F120082,
+	0x0F12005F,
+	0x0F12004A,
+	0x0F120043,
+	0x0F12004C,
+	0x0F120064,
+	0x0F120089,
+	0x0F1200BA,
+	0x0F1200F8,
+	0x0F12012F,
+	0x0F120147,
+	0x0F120116,
+	0x0F1200DE,
+	0x0F1200AF,
+	0x0F12008E,
+	0x0F12007A,
+	0x0F120072,
+	0x0F12007A,
+	0x0F120091,
+	0x0F1200B6,
+	0x0F1200E8,
+	0x0F120121,
+	0x0F120150,
+	0x0F120170,
+	0x0F12013F,
+	0x0F120110,
+	0x0F1200E2,
+	0x0F1200C0,
+	0x0F1200AB,
+	0x0F1200A4,
+	0x0F1200AC,
+	0x0F1200C3,
+	0x0F1200E6,
+	0x0F120117,
+	0x0F120145,
+	0x0F120172,
+	0x0F120127,
+	0x0F120100,
+	0x0F1200CF,
+	0x0F1200A7,
+	0x0F12008D,
+	0x0F12007D,
+	0x0F120077,
+	0x0F12007A,
+	0x0F120087,
+	0x0F12009E,
+	0x0F1200C0,
+	0x0F1200EC,
+	0x0F12010F,
+	0x0F120108,
+	0x0F1200D8,
+	0x0F1200A5,
+	0x0F120080,
+	0x0F120066,
+	0x0F120056,
+	0x0F12004F,
+	0x0F120053,
+	0x0F120061,
+	0x0F120077,
+	0x0F120098,
+	0x0F1200C6,
+	0x0F1200F3,
+	0x0F1200E7,
+	0x0F1200B4,
+	0x0F120081,
+	0x0F12005C,
+	0x0F120041,
+	0x0F120030,
+	0x0F120029,
+	0x0F12002E,
+	0x0F12003D,
+	0x0F120055,
+	0x0F120076,
+	0x0F1200A5,
+	0x0F1200D4,
+	0x0F1200CF,
+	0x0F12009B,
+	0x0F12006A,
+	0x0F120043,
+	0x0F120027,
+	0x0F120016,
+	0x0F12000F,
+	0x0F120015,
+	0x0F120025,
+	0x0F12003E,
+	0x0F120061,
+	0x0F12008E,
+	0x0F1200BF,
+	0x0F1200C2,
+	0x0F12008E,
+	0x0F12005D,
+	0x0F120037,
+	0x0F12001A,
+	0x0F120009,
+	0x0F120002,
+	0x0F120007,
+	0x0F120018,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200BE,
+	0x0F12008A,
+	0x0F12005A,
+	0x0F120034,
+	0x0F120017,
+	0x0F120006,
+	0x0F120000,
+	0x0F120006,
+	0x0F120017,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200C5,
+	0x0F120091,
+	0x0F120061,
+	0x0F12003B,
+	0x0F120020,
+	0x0F12000F,
+	0x0F120009,
+	0x0F120010,
+	0x0F120021,
+	0x0F12003D,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BE,
+	0x0F1200D7,
+	0x0F1200A2,
+	0x0F120072,
+	0x0F12004D,
+	0x0F120032,
+	0x0F120022,
+	0x0F12001D,
+	0x0F120024,
+	0x0F120035,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A0,
+	0x0F1200D2,
+	0x0F1200F0,
+	0x0F1200BE,
+	0x0F12008C,
+	0x0F120068,
+	0x0F12004F,
+	0x0F120040,
+	0x0F12003B,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006C,
+	0x0F12008E,
+	0x0F1200BE,
+	0x0F1200ED,
+	0x0F12010C,
+	0x0F1200E1,
+	0x0F1200AF,
+	0x0F12008A,
+	0x0F120072,
+	0x0F120064,
+	0x0F12005F,
+	0x0F120065,
+	0x0F120074,
+	0x0F12008D,
+	0x0F1200B2,
+	0x0F1200E0,
+	0x0F12010A,
+	0x0F12012F,
+	0x0F120104,
+	0x0F1200D9,
+	0x0F1200B3,
+	0x0F120099,
+	0x0F12008B,
+	0x0F120086,
+	0x0F12008B,
+	0x0F12009B,
+	0x0F1200B5,
+	0x0F1200DA,
+	0x0F120101,
+	0x0F120128,
+	0x0F12012F,
+	0x0F120106,
+	0x0F1200D4,
+	0x0F1200AA,
+	0x0F12008E,
+	0x0F12007D,
+	0x0F120079,
+	0x0F120080,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200DC,
+	0x0F12010C,
+	0x0F120130,
+	0x0F120112,
+	0x0F1200E0,
+	0x0F1200AB,
+	0x0F120083,
+	0x0F120067,
+	0x0F120057,
+	0x0F120051,
+	0x0F120059,
+	0x0F12006B,
+	0x0F120089,
+	0x0F1200B2,
+	0x0F1200E5,
+	0x0F120114,
+	0x0F1200F2,
+	0x0F1200BD,
+	0x0F120088,
+	0x0F120061,
+	0x0F120044,
+	0x0F120031,
+	0x0F12002C,
+	0x0F120033,
+	0x0F120047,
+	0x0F120065,
+	0x0F12008C,
+	0x0F1200C0,
+	0x0F1200F3,
+	0x0F1200DB,
+	0x0F1200A5,
+	0x0F120071,
+	0x0F120049,
+	0x0F12002A,
+	0x0F120018,
+	0x0F120011,
+	0x0F120018,
+	0x0F12002C,
+	0x0F12004B,
+	0x0F120072,
+	0x0F1200A3,
+	0x0F1200D7,
+	0x0F1200CD,
+	0x0F120097,
+	0x0F120065,
+	0x0F12003C,
+	0x0F12001D,
+	0x0F12000A,
+	0x0F120003,
+	0x0F120009,
+	0x0F12001D,
+	0x0F12003B,
+	0x0F120063,
+	0x0F120092,
+	0x0F1200C4,
+	0x0F1200CA,
+	0x0F120094,
+	0x0F120062,
+	0x0F12003A,
+	0x0F12001A,
+	0x0F120007,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120036,
+	0x0F12005C,
+	0x0F12008A,
+	0x0F1200BC,
+	0x0F1200D1,
+	0x0F12009B,
+	0x0F120069,
+	0x0F120042,
+	0x0F120022,
+	0x0F12000F,
+	0x0F120008,
+	0x0F12000D,
+	0x0F12001F,
+	0x0F12003B,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BF,
+	0x0F1200E3,
+	0x0F1200AC,
+	0x0F12007A,
+	0x0F120053,
+	0x0F120035,
+	0x0F120022,
+	0x0F12001B,
+	0x0F12001F,
+	0x0F120030,
+	0x0F12004B,
+	0x0F12006D,
+	0x0F12009C,
+	0x0F1200CE,
+	0x0F1200FE,
+	0x0F1200C9,
+	0x0F120095,
+	0x0F12006F,
+	0x0F120052,
+	0x0F120040,
+	0x0F120039,
+	0x0F12003D,
+	0x0F12004B,
+	0x0F120063,
+	0x0F120086,
+	0x0F1200B5,
+	0x0F1200E6,
+	0x0F12011B,
+	0x0F1200ED,
+	0x0F1200BA,
+	0x0F120092,
+	0x0F120076,
+	0x0F120065,
+	0x0F12005D,
+	0x0F120060,
+	0x0F12006D,
+	0x0F120084,
+	0x0F1200A8,
+	0x0F1200D6,
+	0x0F120101,
+	0x0F120140,
+	0x0F120112,
+	0x0F1200E5,
+	0x0F1200BD,
+	0x0F12009E,
+	0x0F12008C,
+	0x0F120085,
+	0x0F120087,
+	0x0F120094,
+	0x0F1200AC,
+	0x0F1200D0,
+	0x0F1200F8,
+	0x0F120123,
+	0x0F1200F2,
+	0x0F1200D1,
+	0x0F1200A7,
+	0x0F120087,
+	0x0F120073,
+	0x0F120067,
+	0x0F120064,
+	0x0F12006B,
+	0x0F12007C,
+	0x0F120094,
+	0x0F1200B7,
+	0x0F1200E1,
+	0x0F1200FF,
+	0x0F1200D6,
+	0x0F1200AE,
+	0x0F120085,
+	0x0F120068,
+	0x0F120054,
+	0x0F120048,
+	0x0F120045,
+	0x0F12004B,
+	0x0F12005B,
+	0x0F120073,
+	0x0F120093,
+	0x0F1200BF,
+	0x0F1200E9,
+	0x0F1200B8,
+	0x0F12008E,
+	0x0F120066,
+	0x0F120049,
+	0x0F120035,
+	0x0F120028,
+	0x0F120025,
+	0x0F12002B,
+	0x0F12003B,
+	0x0F120053,
+	0x0F120072,
+	0x0F12009D,
+	0x0F1200C8,
+	0x0F1200A2,
+	0x0F120078,
+	0x0F120051,
+	0x0F120034,
+	0x0F12001F,
+	0x0F120012,
+	0x0F12000E,
+	0x0F120014,
+	0x0F120024,
+	0x0F12003B,
+	0x0F12005B,
+	0x0F120083,
+	0x0F1200AD,
+	0x0F120095,
+	0x0F12006C,
+	0x0F120046,
+	0x0F12002A,
+	0x0F120014,
+	0x0F120007,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F12002D,
+	0x0F12004C,
+	0x0F120072,
+	0x0F12009B,
+	0x0F120093,
+	0x0F12006A,
+	0x0F120045,
+	0x0F120028,
+	0x0F120013,
+	0x0F120005,
+	0x0F120000,
+	0x0F120004,
+	0x0F120012,
+	0x0F120028,
+	0x0F120045,
+	0x0F12006A,
+	0x0F120093,
+	0x0F12009B,
+	0x0F120071,
+	0x0F12004C,
+	0x0F120030,
+	0x0F12001A,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000B,
+	0x0F120018,
+	0x0F12002C,
+	0x0F120048,
+	0x0F12006D,
+	0x0F120097,
+	0x0F1200AE,
+	0x0F120083,
+	0x0F12005C,
+	0x0F120040,
+	0x0F12002B,
+	0x0F12001E,
+	0x0F120018,
+	0x0F12001C,
+	0x0F120027,
+	0x0F12003A,
+	0x0F120055,
+	0x0F12007B,
+	0x0F1200A6,
+	0x0F1200CA,
+	0x0F12009E,
+	0x0F120076,
+	0x0F120059,
+	0x0F120046,
+	0x0F120039,
+	0x0F120033,
+	0x0F120036,
+	0x0F120040,
+	0x0F120052,
+	0x0F12006C,
+	0x0F120094,
+	0x0F1200BF,
+	0x0F1200EB,
+	0x0F1200C3,
+	0x0F120099,
+	0x0F12007A,
+	0x0F120066,
+	0x0F12005A,
+	0x0F120054,
+	0x0F120056,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008D,
+	0x0F1200B6,
+	0x0F1200DE,
+	0x0F12010D,
+	0x0F1200E7,
+	0x0F1200C1,
+	0x0F1200A0,
+	0x0F12008A,
+	0x0F12007C,
+	0x0F120076,
+	0x0F120078,
+	0x0F120081,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200D5,
+	0x0F1200FD,
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F12025E,
+	0x0F120282,
+	0x0F120240,
+	0x0F120298,
+	0x0F12022A,
+	0x0F12029A,
+	0x0F12021A,
+	0x0F12029A,
+	0x0F120206,
+	0x0F120298,
+	0x0F1201FE,
+	0x0F12028C,
+	0x0F1201FA,
+	0x0F120278,
+	0x0F1201F8,
+	0x0F120266,
+	0x0F120214,
+	0x0F120238,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* param_WRITE 70000CC6 */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end*/
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120030, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120030, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120030, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F121021, /* awbb_GridConst_2_0  */
+	0x0F12107E, /* awbb_GridConst_2_1  */
+	0x0F12113E, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+	/* awbb_ChromaClassifyEn, default : enable*/
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/*  param_start */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+
+	/* param_start SARR_uNormBrInDoor*/
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+	/* param_start SARR_uNormBrOutDoor */
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F12FFFE, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120018, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120009, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F12000E, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F12000E, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120014, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001,
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+	/* END of Initial*/
+};
+
+/* Set-data based on SKT VT standard ,when using 3G network
+* 8fps
+*/
+static const u32 s5k5bafx_vt_common[] =
+{
+	/* VT-Call */
+
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* Delay */
+
+
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,	/* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E,	/* setot_usSetRomWaitStateThreshold4KHz */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+
+	0x0F120015,
+
+
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+
+
+	0x002AF900,
+	0x0F120067,
+
+
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+
+	0x002AF4D6,
+	0x0F120090,
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+
+	/* sensor aig table setting   sunkyu start */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* 3A TVAR_ae_BrAve */
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /*uMaxExp1         */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /*uMaxExp2         */
+	0x0F120000,
+	0x0F12A122, /*uMaxExp3         */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /*uMaxExp4         */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0, /*lt_uMaxAnGain0   */
+	0x0F1201E0, /*lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300, /*lt_uMaxAnGain1   */
+	0x0F120C80, /* E00 lt_uMaxAnGain2   */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /*ae_StatMode      */
+
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202B0,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120290,
+
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12007F, /* REG_TC_DBG_AutoAlgEnBits             default : 007F */
+
+
+	0xffff000a, /* Wait10mSec */
+
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F121B58, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+
+
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* Delay 100ms                   */
+
+
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+
+
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight              */
+	0x0F120005, /* REG_0TC_PCFG_Format                */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_PCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex     */
+	0x0F120001, /* REG_0TC_PCFG_uPrevMirror           */
+	0x0F120001, /* REG_0TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_0TC_PCFG_uRotation             */
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight              */
+	0x0F120005, /* REG_1TC_PCFG_Format                */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd             */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType          */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex     */
+	0x0F120001, /* REG_1TC_PCFG_uPrevMirror           */
+	0x0F120001, /* REG_1TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_1TC_PCFG_uRotation             */
+
+
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig     */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange  */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync        */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged    */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview        */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+
+
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+
+
+
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000, /* msm_uOffsetNoBin[0][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[0][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[1][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[1][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[2][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[2][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[3][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[3][1]    */
+
+	0x002A0798,
+	0x0F120000, /* msm_uOffsetBin[0][0]      */
+	0x0F120000, /* msm_uOffsetBin[0][1]      */
+	0x0F120000, /* msm_uOffsetBin[1][0]      */
+	0x0F120000, /* msm_uOffsetBin[1][1]      */
+
+	0x002A07C0,
+	0x0F120004, /* msm_NonLinearOfsOutput[2] */
+	0x0F120004, /* msm_NonLinearOfsOutput[3] */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120100, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120001, /* ae_WeightTbl_16_7_ */
+	0x0F120100, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120001, /* ae_WeightTbl_16_11 */
+	0x0F120100, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120001, /* ae_WeightTbl_16_15 */
+	0x0F120100, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120001, /* ae_WeightTbl_16_19 */
+	0x0F120100, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120001, /* ae_WeightTbl_16_23 */
+	0x0F120100, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120001, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3, /* TVAR_ash_AwbAshCord_0_ */
+	0x0F1200E5, /* TVAR_ash_AwbAshCord_1_ */
+	0x0F120120, /* TVAR_ash_AwbAshCord_2_ */
+	0x0F120136, /* TVAR_ash_AwbAshCord_3_ */
+	0x0F120180, /* TVAR_ash_AwbAshCord_4_ */
+	0x0F1201B0, /* TVAR_ash_AwbAshCord_5_ */
+	0x0F120200, /* TVAR_ash_AwbAshCord_6_ */
+
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3, /* SARR_AwbCcmCord_0_	Hor   */
+	0x0F1200E5, /* SARR_AwbCcmCord_1_	IncaA */
+	0x0F120120, /* SARR_AwbCcmCord_2_	WW    */
+	0x0F120136, /* SARR_AwbCcmCord_3_	CW    */
+	0x0F120180, /* SARR_AwbCcmCord_4_	D50   */
+	0x0F120190, /* SARR_AwbCcmCord_5_	D65   */
+
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000, /* SARR_IllumType_0_      */
+	0x0F120009, /* SARR_IllumType_1_      */
+	0x0F120018, /* SARR_IllumType_2_      */
+	0x0F120032, /* SARR_IllumType_3_      */
+	0x0F12004A, /* SARR_IllumType_4_      */
+	0x0F120051, /* SARR_IllumType_5_      */
+	0x0F120056, /* SARR_IllumType_6_      */
+	0x0F12010C, /* SARe_2_R_IllumTypeF_0_ */
+	0x0F12010C, /* SARe_3_R_IllumTypeF_1_ */
+	0x0F120109, /* SARe_4_R_IllumTypeF_2_ */
+	0x0F120105, /* SARe_5_R_IllumTypeF_3_ */
+	0x0F120102, /* SARe_6_R_IllumTypeF_4_ */
+	0x0F1200FB, /* SARR_IllumTypeF_5_     */
+	0x0F1200F8, /* SARR_IllumTypeF_6_     */
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388, /* TVAR_ash_pGAS */
+	0x0F127000, /* TVAR_ash_pGAS */
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[0][15] */
+
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[1][15] */
+
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[2][15] */
+
+
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12035E, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12036A, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120348, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F120380, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F120384, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F12037E, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F1202FE, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F12037A, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202E6, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12036C, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F12035C, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202B4, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F120344, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202A0, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120330, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F12028A, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F120272, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F120308, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F12025E, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F1202F4, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202DA, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120240, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202C6, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120232, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202B8, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202AA, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120216, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120206, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120288, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120280, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201DC, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F12027A, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F120272, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201C2, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F120264, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201AA, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F12025A, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201A0, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F12024A, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120190, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F1201C4, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F1201DE, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F12001F,
+	0x0F120000,
+	0x0F12011E,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F120264,
+	0x0F120279,
+	0x0F120250,
+	0x0F120287,
+	0x0F120244,
+	0x0F120287,
+	0x0F120235,
+	0x0F120289,
+	0x0F120225,
+	0x0F120287,
+	0x0F120213,
+	0x0F120286,
+	0x0F120202,
+	0x0F12027A,
+	0x0F1201F3,
+	0x0F120272,
+	0x0F1201E9,
+	0x0F120269,
+	0x0F1201E2,
+	0x0F120263,
+	0x0F1201E0,
+	0x0F12025A,
+	0x0F1201E1,
+	0x0F120256,
+	0x0F1201EE,
+	0x0F120251,
+	0x0F1201F8,
+	0x0F12024A,
+	0x0F12020D,
+	0x0F120231,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120011,
+	0x0F120000,
+	0x0F1201FF,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F120000, /* awbb_GridCorr_R_0__0_ */
+	0x0F120000, /* awbb_GridCorr_R_0__1_ */
+	0x0F120040, /* awbb_GridCorr_R_0__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_0__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_0__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F120000, /* awbb_GridCorr_R_1__0_ */
+	0x0F120000, /* awbb_GridCorr_R_1__1_ */
+	0x0F120040, /* awbb_GridCorr_R_1__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_1__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_1__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F120000, /* awbb_GridCorr_R_2__0_ */
+	0x0F120000, /* awbb_GridCorr_R_2__1_ */
+	0x0F120040, /* awbb_GridCorr_R_2__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_2__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_2__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120030, /* awbb_GridCorr_B_0__2_ */
+	0x0F120000, /* awbb_GridCorr_B_0__3_ */
+	0x0F120018, /* awbb_GridCorr_B_0__4_ */
+	0x0F120040, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120030, /* awbb_GridCorr_B_1__2_ */
+	0x0F120000, /* awbb_GridCorr_B_1__3_ */
+	0x0F120018, /* awbb_GridCorr_B_1__4_ */
+	0x0F120040, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120030, /* awbb_GridCorr_B_2__2_ */
+	0x0F120000, /* awbb_GridCorr_B_2__3_ */
+	0x0F120018, /* awbb_GridCorr_B_2__4_ */
+	0x0F120040, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F120FD7, /* awbb_GridConst_2_0  */
+	0x0F1210C5, /* awbb_GridConst_2_1  */
+	0x0F12116A, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F120365, /* 52A awbb_MvEq_RBthresh */
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F12041B, /* 459 awbb_LowTempRB */
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F1201E5, /* 01D6 01E1 01FB */
+	0x0F12FFBF, /* FFC9 FFC4 FF9C */
+	0x0F12FFF4, /* FFFB FFF8 FFFF */
+	0x0F1200EE, /* 010A 0101 0137 */
+	0x0F12019B, /* 0177 014C 0113 */
+	0x0F12FF1E, /* FF24 FF55 FF6F */
+	0x0F12FF38, /* FF9C FF5B FF21 */
+	0x0F12026D, /* 0230 0205 0194 */
+	0x0F12FEDD, /* FEB1 FF17 FF69 */
+	0x0F12FF00, /* FEFF FEFE FF14 */
+	0x0F1201B8, /* 01B7 01B6 0158 */
+	0x0F120109, /* 0108 0107 015D */
+	0x0F12FFCC, /* FFEB FFDB FFF2 */
+	0x0F12FFA4, /* FFB5 FFDB FFF1 */
+	0x0F120212, /* 01E4 01D1 0179 */
+	0x0F120136, /* 011E 0163 017C */
+	0x0F12FFA5, /* FFAD FF9E FFC3 */
+	0x0F1201CF, /* 01E3 01B3 0197 */
+
+	0x0F1201E5, /* 01D6 01E1 01FB */
+	0x0F12FFBF, /* FFC9 FFC4 FF9C */
+	0x0F12FFF4, /* FFFB FFF8 FFFF */
+	0x0F1200EE, /* 010A 0101 0137 */
+	0x0F12019B, /* 0177 014C 0113 */
+	0x0F12FF1E, /* FF24 FF55 FF6F */
+	0x0F12FF38, /* FF9C FF5B FF21 */
+	0x0F12026D, /* 0230 0205 0194 */
+	0x0F12FEDD, /* FEB1 FF17 FF69 */
+	0x0F12FF00, /* FEFF FEFE FF14 */
+	0x0F1201B8, /* 01B7 01B6 0158 */
+	0x0F120109, /* 0108 0107 015D */
+	0x0F12FFCC, /* FFEB FFDB FFF2 */
+	0x0F12FFA4, /* FFB5 FFDB FFF1 */
+	0x0F120212, /* 01E4 01D1 0179 */
+	0x0F120136, /* 011E 0163 017C */
+	0x0F12FFA5, /* FFAD FF9E FFC3 */
+	0x0F1201CF, /* 01E3 01B3 0197 */
+
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+
+	0x0F1201FB, /* 01FB 01FB */
+	0x0F12FFA9, /* FFA9 FF9C */
+	0x0F12FFEA, /* FFEA FFFF */
+	0x0F12013C, /* 0134 0137 */
+	0x0F120140, /* 0133 0113 */
+	0x0F12FF53, /* FF5D FF6F */
+	0x0F12FE7A, /* FE7A FF21 */
+	0x0F12017D, /* 017D 0194 */
+	0x0F12FEED, /* FEED FF69 */
+	0x0F12FF39, /* FF39 FF14 */
+	0x0F1201D6, /* 01D6 0158 */
+	0x0F1200C4, /* 00C4 015D */
+	0x0F12FFC0, /* FFCE FFF2 */
+	0x0F12FFBF, /* FFCD FFF1 */
+	0x0F1201CD, /* 01B7 0179 */
+	0x0F120182, /* 0176 017C */
+	0x0F12FF91, /* FFBD FFC3 */
+	0x0F1201AA, /* 0191 0197 */
+
+	0x0F1201D2, /* 01C5 01F9 020A */
+	0x0F12FFC2, /* FF9F FFBC FFB2 */
+	0x0F12FFFC, /* FFE5 FFF2 FFEB */
+	0x0F1200E8, /* 00E2 00FA 0134 */
+	0x0F120126, /* 010E 0157 0133 */
+	0x0F12FF83, /* FF62 FF81 FF5D */
+	0x0F12FE7A, /* FF03 FE7A FEFD */
+	0x0F12017D, /* 01D0 017D 01BF */
+	0x0F12FEED, /* FF3E FEED FF2A */
+	0x0F12FF1C, /* FF00 FF8A FF39 */
+	0x0F120194, /* 01A6 01F9 01D6 */
+	0x0F12011F, /* 00BB 005B 00C4 */
+	0x0F12FFEA, /* FFBF FFCA FFCE */
+	0x0F12FFDE, /* FFDD FFA3 FFCD */
+	0x0F1201E9, /* 01F6 01DA 01B7 */
+	0x0F120178, /* 00CB 0108 0176 */
+	0x0F12FFBF, /* FF94 FFB3 FFBD */
+	0x0F120193, /* 019E 01DD 0191 */
+
+	0x0F1201D2, /* 01F9 020A 01D0   R */
+	0x0F12FFC2, /* FFBC FFB2 FFB4     */
+	0x0F12FFFC, /* FFF2 FFEB 000C     */
+	0x0F1200E8, /* 00FA 011E 0122   Y */
+	0x0F120126, /* 0157 011D 0103     */
+	0x0F12FF83, /* FF81 FF86 FF9B     */
+	0x0F12FE7A, /* FE7A FEFD FF33   G */
+	0x0F12017D, /* 017D 01BF 01C5     */
+	0x0F12FEED, /* FEED FF2A FF33     */
+	0x0F12FF1C, /* FF8A FF38 FF16   C */
+	0x0F120194, /* 01F9 01D5 015A     */
+	0x0F12011F, /* 005B 00C3 015F     */
+	0x0F12FFEA, /* FFCA FFCF FFE0   B */
+	0x0F12FFDE, /* FFA3 FFCE FFDF     */
+	0x0F1201E9, /* 01DA 01B8 0197     */
+	0x0F120178, /* 0108 0178 0178   M */
+	0x0F12FFBF, /* FFB3 FFBF FFBF     */
+	0x0F120193, /* 01DD 0193 0193     */
+
+	0x0F1201F1, /* outdoor CCM */
+	0x0F12FFB0,
+	0x0F12FFEF,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FF4E,
+	0x0F120164,
+	0x0F12011D,
+	0x0F12FFEA,
+	0x0F12FFDE,
+	0x0F1201E9,
+	0x0F120178,
+	0x0F12FFBF,
+	0x0F120193,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /* afit_bUseNoiseInd 0 : NB 1: Noise Index */
+
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+
+	/* Set AFIT */
+	/* AFIT Start Address */
+	0x002A0814,
+	0x0F12082C, /* TVAR_afit_pBaseVals */
+	0x0F127000, /* TVAR_afit_pBaseVals */
+
+	/* param_start	TVAR_afit_pBaseVals */
+	0x002A082C,
+	0x0F120003, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F12FFFE, /* SATURATION                                                               */
+	0x0F12FFE2, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120035, /* RGB2YUV_iYOffset                                                         */
+
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120114, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120008, /* RGB2YUV_iYOffset                                                         */
+
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F12000A, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                    */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* VT-Call END of Initial */
+};
+
+
+/* Set-data based on Samsung Reliabilty Group standard
+* ,when using WIFI. 15fps
+*/
+static const u32 s5k5bafx_vt_wifi_common[] =
+{
+	/* Wifi_VT */
+
+	0xFCFCD000,
+
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* Delay */
+
+
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+
+	0x0F120015,
+
+
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+
+
+	0x002AF900,
+	0x0F120067,
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+
+	0x002AF4D6,
+	0x0F120090,
+
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000, /* senHal_bUseAnalogBinning */
+	0x0F120000, /* senHal_bUseAnalogVerAvg  */
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F120038, /* 3A TVAR_ae_BrAve */
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+
+
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,/* uMaxExp1         */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,/* uMaxExp2         */
+	0x0F120000,
+	0x0F12A122,/* uMaxExp3         */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,/* uMaxExp4         */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201B0,/* lt_uMaxAnGain0   */
+	0x0F1201C0,/* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F1202B0,/* lt_uMaxAnGain1   */
+	0x0F120B00,/* lt_uMaxAnGain2   */
+	0x0f120100,/* lt_uMaxDigGain   */
+	0x002A0F52,
+	0x0F12000F,/* ae_StatMode */
+
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12007F, /* REG_TC_DBG_AutoAlgEnBits          default : 007F  */
+
+
+
+	0xffff000a, /* Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F121B58, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+
+
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* Delay 100msec                 */
+
+
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+
+
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight              */
+	0x0F120005, /* REG_0TC_PCFG_Format                */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType          */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12029A, /* REG_0TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex     */
+	0x0F120003, /* REG_0TC_PCFG_uPrevMirror           */
+	0x0F120003, /* REG_0TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_0TC_PCFG_uRotation             */
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight              */
+	0x0F120005, /* REG_1TC_PCFG_Format                */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd             */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType          */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex     */
+	0x0F120003, /* REG_1TC_PCFG_uPrevMirror           */
+	0x0F120003, /* REG_1TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_1TC_PCFG_uRotation             */
+
+
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig     */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange  */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync        */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged    */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview        */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+
+
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 15fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F12029A, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+
+
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000, /* msm_uOffsetNoBin[0][0] */
+	0x0F120000, /* msm_uOffsetNoBin[0][1] */
+	0x0F120000, /* msm_uOffsetNoBin[1][0] */
+	0x0F120000, /* msm_uOffsetNoBin[1][1] */
+	0x0F120000, /* msm_uOffsetNoBin[2][0] */
+	0x0F120000, /* msm_uOffsetNoBin[2][1] */
+	0x0F120000, /* msm_uOffsetNoBin[3][0] */
+	0x0F120000, /* msm_uOffsetNoBin[3][1] */
+
+	0x002A0798,
+	0x0F120000, /* msm_uOffsetBin[0][0] */
+	0x0F120000, /* msm_uOffsetBin[0][1] */
+	0x0F120000, /* msm_uOffsetBin[1][0] */
+	0x0F120000, /* msm_uOffsetBin[1][1] */
+
+	0x002A07C0,
+	0x0F120004, /* msm_NonLinearOfsOutput[2] */
+	0x0F120004, /* msm_NonLinearOfsOutput[3] */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R */
+	0x0F120400, /* awbb_GainsInit_1_:G */
+	0x0F1205F0, /* awbb_GainsInit_2_:B */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start */
+
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3, /* TVAR_ash_AwbAshCord_0_ */
+	0x0F1200E5, /* TVAR_ash_AwbAshCord_1_ */
+	0x0F120120, /* TVAR_ash_AwbAshCord_2_ */
+	0x0F120136, /* TVAR_ash_AwbAshCord_3_ */
+	0x0F120180, /* TVAR_ash_AwbAshCord_4_ */
+	0x0F1201B0, /* TVAR_ash_AwbAshCord_5_ */
+	0x0F120200, /* TVAR_ash_AwbAshCord_6_ */
+
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3, /* SARR_AwbCcmCord_0_	Hor   */
+	0x0F1200E5, /* SARR_AwbCcmCord_1_	IncaA */
+	0x0F120100, /* SARR_AwbCcmCord_2_	WW    */
+	0x0F120116, /* SARR_AwbCcmCord_3_	CW    */
+	0x0F120150, /* SARR_AwbCcmCord_4_	D50   */
+	0x0F120198, /* SARR_AwbCcmCord_5_	D65   */
+
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000, /* SARR_IllumType_0_      */
+	0x0F120009, /* SARR_IllumType_1_      */
+	0x0F120018, /* SARR_IllumType_2_      */
+	0x0F120032, /* SARR_IllumType_3_      */
+	0x0F12004A, /* SARR_IllumType_4_      */
+	0x0F120051, /* SARR_IllumType_5_      */
+	0x0F120056, /* SARR_IllumType_6_      */
+	0x0F12010C, /* SARe_2_R_IllumTypeF_0_ */
+	0x0F12010C, /* SARe_3_R_IllumTypeF_1_ */
+	0x0F120109, /* SARe_4_R_IllumTypeF_2_ */
+	0x0F120105, /* SARe_5_R_IllumTypeF_3_ */
+	0x0F120102, /* SARe_6_R_IllumTypeF_4_ */
+	0x0F1200FB, /* SARR_IllumTypeF_5_     */
+	0x0F1200F8, /* SARR_IllumTypeF_6_     */
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388, /* TVAR_ash_pGAS */
+	0x0F127000, /* TVAR_ash_pGAS */
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F1201CC, /* TVAR_ash_pGAS[0]   */
+	0x0F120178, /* TVAR_ash_pGAS[1]   */
+	0x0F12013B, /* TVAR_ash_pGAS[2]   */
+	0x0F120108, /* TVAR_ash_pGAS[3]   */
+	0x0F1200E4, /* TVAR_ash_pGAS[4]   */
+	0x0F1200CC, /* TVAR_ash_pGAS[5]   */
+	0x0F1200C5, /* TVAR_ash_pGAS[6]   */
+	0x0F1200CF, /* TVAR_ash_pGAS[7]   */
+	0x0F1200E8, /* TVAR_ash_pGAS[8]   */
+	0x0F120111, /* TVAR_ash_pGAS[9]   */
+	0x0F120142, /* TVAR_ash_pGAS[10]  */
+	0x0F120183, /* TVAR_ash_pGAS[11]  */
+	0x0F1201D9, /* TVAR_ash_pGAS[12]  */
+	0x0F120184, /* TVAR_ash_pGAS[13]  */
+	0x0F120142, /* TVAR_ash_pGAS[14]  */
+	0x0F120101, /* TVAR_ash_pGAS[15]  */
+	0x0F1200CF, /* TVAR_ash_pGAS[16]  */
+	0x0F1200A7, /* TVAR_ash_pGAS[17]  */
+	0x0F120090, /* TVAR_ash_pGAS[18]  */
+	0x0F120088, /* TVAR_ash_pGAS[19]  */
+	0x0F120092, /* TVAR_ash_pGAS[20]  */
+	0x0F1200AC, /* TVAR_ash_pGAS[21]  */
+	0x0F1200D5, /* TVAR_ash_pGAS[22]  */
+	0x0F12010D, /* TVAR_ash_pGAS[23]  */
+	0x0F12014E, /* TVAR_ash_pGAS[24]  */
+	0x0F120190, /* TVAR_ash_pGAS[25]  */
+	0x0F12014E, /* TVAR_ash_pGAS[26]  */
+	0x0F12010D, /* TVAR_ash_pGAS[27]  */
+	0x0F1200CA, /* TVAR_ash_pGAS[28]  */
+	0x0F120094, /* TVAR_ash_pGAS[29]  */
+	0x0F12006D, /* TVAR_ash_pGAS[30]  */
+	0x0F120054, /* TVAR_ash_pGAS[31]  */
+	0x0F12004E, /* TVAR_ash_pGAS[32]  */
+	0x0F120058, /* TVAR_ash_pGAS[33]  */
+	0x0F120073, /* TVAR_ash_pGAS[34]  */
+	0x0F12009D, /* TVAR_ash_pGAS[35]  */
+	0x0F1200D5, /* TVAR_ash_pGAS[36]  */
+	0x0F12011D, /* TVAR_ash_pGAS[37]  */
+	0x0F12015A, /* TVAR_ash_pGAS[38]  */
+	0x0F120129, /* TVAR_ash_pGAS[39]  */
+	0x0F1200E5, /* TVAR_ash_pGAS[40]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[41]  */
+	0x0F12006B, /* TVAR_ash_pGAS[42]  */
+	0x0F120042, /* TVAR_ash_pGAS[43]  */
+	0x0F12002A, /* TVAR_ash_pGAS[44]  */
+	0x0F120022, /* TVAR_ash_pGAS[45]  */
+	0x0F12002D, /* TVAR_ash_pGAS[46]  */
+	0x0F120049, /* TVAR_ash_pGAS[47]  */
+	0x0F120075, /* TVAR_ash_pGAS[48]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[49]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[50]  */
+	0x0F12013A, /* TVAR_ash_pGAS[51]  */
+	0x0F120113, /* TVAR_ash_pGAS[52]  */
+	0x0F1200CE, /* TVAR_ash_pGAS[53]  */
+	0x0F120088, /* TVAR_ash_pGAS[54]  */
+	0x0F120052, /* TVAR_ash_pGAS[55]  */
+	0x0F12002A, /* TVAR_ash_pGAS[56]  */
+	0x0F120010, /* TVAR_ash_pGAS[57]  */
+	0x0F120009, /* TVAR_ash_pGAS[58]  */
+	0x0F120015, /* TVAR_ash_pGAS[59]  */
+	0x0F120032, /* TVAR_ash_pGAS[60]  */
+	0x0F12005E, /* TVAR_ash_pGAS[61]  */
+	0x0F120098, /* TVAR_ash_pGAS[62]  */
+	0x0F1200E3, /* TVAR_ash_pGAS[63]  */
+	0x0F120128, /* TVAR_ash_pGAS[64]  */
+	0x0F12010A, /* TVAR_ash_pGAS[65]  */
+	0x0F1200C4, /* TVAR_ash_pGAS[66]  */
+	0x0F120080, /* TVAR_ash_pGAS[67]  */
+	0x0F120049, /* TVAR_ash_pGAS[68]  */
+	0x0F120020, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F12000D, /* TVAR_ash_pGAS[72]  */
+	0x0F12002A, /* TVAR_ash_pGAS[73]  */
+	0x0F120058, /* TVAR_ash_pGAS[74]  */
+	0x0F120093, /* TVAR_ash_pGAS[75]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[76]  */
+	0x0F120123, /* TVAR_ash_pGAS[77]  */
+	0x0F12010D, /* TVAR_ash_pGAS[78]  */
+	0x0F1200CA, /* TVAR_ash_pGAS[79]  */
+	0x0F120085, /* TVAR_ash_pGAS[80]  */
+	0x0F12004E, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F12000E, /* TVAR_ash_pGAS[83]  */
+	0x0F120007, /* TVAR_ash_pGAS[84]  */
+	0x0F120014, /* TVAR_ash_pGAS[85]  */
+	0x0F120032, /* TVAR_ash_pGAS[86]  */
+	0x0F120061, /* TVAR_ash_pGAS[87]  */
+	0x0F12009C, /* TVAR_ash_pGAS[88]  */
+	0x0F1200E8, /* TVAR_ash_pGAS[89]  */
+	0x0F12012F, /* TVAR_ash_pGAS[90]  */
+	0x0F120121, /* TVAR_ash_pGAS[91]  */
+	0x0F1200DE, /* TVAR_ash_pGAS[92]  */
+	0x0F12009A, /* TVAR_ash_pGAS[93]  */
+	0x0F120063, /* TVAR_ash_pGAS[94]  */
+	0x0F12003B, /* TVAR_ash_pGAS[95]  */
+	0x0F120024, /* TVAR_ash_pGAS[96]  */
+	0x0F12001D, /* TVAR_ash_pGAS[97]  */
+	0x0F12002B, /* TVAR_ash_pGAS[98]  */
+	0x0F120049, /* TVAR_ash_pGAS[99]  */
+	0x0F120079, /* TVAR_ash_pGAS[100] */
+	0x0F1200B5, /* TVAR_ash_pGAS[101] */
+	0x0F120100, /* TVAR_ash_pGAS[102] */
+	0x0F120145, /* TVAR_ash_pGAS[103] */
+	0x0F12013F, /* TVAR_ash_pGAS[104] */
+	0x0F120101, /* TVAR_ash_pGAS[105] */
+	0x0F1200BE, /* TVAR_ash_pGAS[106] */
+	0x0F120087, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F120048, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F120051, /* TVAR_ash_pGAS[111] */
+	0x0F120070, /* TVAR_ash_pGAS[112] */
+	0x0F1200A0, /* TVAR_ash_pGAS[113] */
+	0x0F1200DF, /* TVAR_ash_pGAS[114] */
+	0x0F120126, /* TVAR_ash_pGAS[115] */
+	0x0F120168, /* TVAR_ash_pGAS[116] */
+	0x0F12016D, /* TVAR_ash_pGAS[117] */
+	0x0F12012F, /* TVAR_ash_pGAS[118] */
+	0x0F1200EF, /* TVAR_ash_pGAS[119] */
+	0x0F1200BA, /* TVAR_ash_pGAS[120] */
+	0x0F120093, /* TVAR_ash_pGAS[121] */
+	0x0F12007E, /* TVAR_ash_pGAS[122] */
+	0x0F120079, /* TVAR_ash_pGAS[123] */
+	0x0F120087, /* TVAR_ash_pGAS[124] */
+	0x0F1200A6, /* TVAR_ash_pGAS[125] */
+	0x0F1200D7, /* TVAR_ash_pGAS[126] */
+	0x0F120114, /* TVAR_ash_pGAS[127] */
+	0x0F120158, /* TVAR_ash_pGAS[128] */
+	0x0F120199, /* TVAR_ash_pGAS[129] */
+	0x0F1201A6, /* TVAR_ash_pGAS[130] */
+	0x0F12015E, /* TVAR_ash_pGAS[131] */
+	0x0F120122, /* TVAR_ash_pGAS[132] */
+	0x0F1200F1, /* TVAR_ash_pGAS[133] */
+	0x0F1200CB, /* TVAR_ash_pGAS[134] */
+	0x0F1200B6, /* TVAR_ash_pGAS[135] */
+	0x0F1200B2, /* TVAR_ash_pGAS[136] */
+	0x0F1200C0, /* TVAR_ash_pGAS[137] */
+	0x0F1200DF, /* TVAR_ash_pGAS[138] */
+	0x0F12010D, /* TVAR_ash_pGAS[139] */
+	0x0F120145, /* TVAR_ash_pGAS[140] */
+	0x0F120188, /* TVAR_ash_pGAS[141] */
+	0x0F1201DF, /* TVAR_ash_pGAS[142] */
+	0x0F12016C, /* TVAR_ash_pGAS[143] */
+	0x0F120127, /* TVAR_ash_pGAS[144] */
+	0x0F1200F2, /* TVAR_ash_pGAS[145] */
+	0x0F1200CA, /* TVAR_ash_pGAS[146] */
+	0x0F1200AC, /* TVAR_ash_pGAS[147] */
+	0x0F12009B, /* TVAR_ash_pGAS[148] */
+	0x0F120096, /* TVAR_ash_pGAS[149] */
+	0x0F12009C, /* TVAR_ash_pGAS[150] */
+	0x0F1200AE, /* TVAR_ash_pGAS[151] */
+	0x0F1200CC, /* TVAR_ash_pGAS[152] */
+	0x0F1200F4, /* TVAR_ash_pGAS[153] */
+	0x0F12012D, /* TVAR_ash_pGAS[154] */
+	0x0F120179, /* TVAR_ash_pGAS[155] */
+	0x0F120130, /* TVAR_ash_pGAS[156] */
+	0x0F1200F6, /* TVAR_ash_pGAS[157] */
+	0x0F1200C4, /* TVAR_ash_pGAS[158] */
+	0x0F120099, /* TVAR_ash_pGAS[159] */
+	0x0F12007C, /* TVAR_ash_pGAS[160] */
+	0x0F12006C, /* TVAR_ash_pGAS[161] */
+	0x0F120067, /* TVAR_ash_pGAS[162] */
+	0x0F12006E, /* TVAR_ash_pGAS[163] */
+	0x0F12007F, /* TVAR_ash_pGAS[164] */
+	0x0F12009E, /* TVAR_ash_pGAS[165] */
+	0x0F1200C8, /* TVAR_ash_pGAS[166] */
+	0x0F120100, /* TVAR_ash_pGAS[167] */
+	0x0F120138, /* TVAR_ash_pGAS[168] */
+	0x0F120107, /* TVAR_ash_pGAS[169] */
+	0x0F1200CF, /* TVAR_ash_pGAS[170] */
+	0x0F120097, /* TVAR_ash_pGAS[171] */
+	0x0F12006D, /* TVAR_ash_pGAS[172] */
+	0x0F120050, /* TVAR_ash_pGAS[173] */
+	0x0F120040, /* TVAR_ash_pGAS[174] */
+	0x0F12003B, /* TVAR_ash_pGAS[175] */
+	0x0F120042, /* TVAR_ash_pGAS[176] */
+	0x0F120055, /* TVAR_ash_pGAS[177] */
+	0x0F120074, /* TVAR_ash_pGAS[178] */
+	0x0F12009F, /* TVAR_ash_pGAS[179] */
+	0x0F1200D9, /* TVAR_ash_pGAS[180] */
+	0x0F120110, /* TVAR_ash_pGAS[181] */
+	0x0F1200E9, /* TVAR_ash_pGAS[182] */
+	0x0F1200AE, /* TVAR_ash_pGAS[183] */
+	0x0F120077, /* TVAR_ash_pGAS[184] */
+	0x0F12004D, /* TVAR_ash_pGAS[185] */
+	0x0F12002F, /* TVAR_ash_pGAS[186] */
+	0x0F12001F, /* TVAR_ash_pGAS[187] */
+	0x0F12001A, /* TVAR_ash_pGAS[188] */
+	0x0F120022, /* TVAR_ash_pGAS[189] */
+	0x0F120036, /* TVAR_ash_pGAS[190] */
+	0x0F120055, /* TVAR_ash_pGAS[191] */
+	0x0F120081, /* TVAR_ash_pGAS[192] */
+	0x0F1200BC, /* TVAR_ash_pGAS[193] */
+	0x0F1200F5, /* TVAR_ash_pGAS[194] */
+	0x0F1200D8, /* TVAR_ash_pGAS[195] */
+	0x0F12009C, /* TVAR_ash_pGAS[196] */
+	0x0F120064, /* TVAR_ash_pGAS[197] */
+	0x0F12003A, /* TVAR_ash_pGAS[198] */
+	0x0F12001C, /* TVAR_ash_pGAS[199] */
+	0x0F12000B, /* TVAR_ash_pGAS[200] */
+	0x0F120006, /* TVAR_ash_pGAS[201] */
+	0x0F12000F, /* TVAR_ash_pGAS[202] */
+	0x0F120024, /* TVAR_ash_pGAS[203] */
+	0x0F120044, /* TVAR_ash_pGAS[204] */
+	0x0F120070, /* TVAR_ash_pGAS[205] */
+	0x0F1200AD, /* TVAR_ash_pGAS[206] */
+	0x0F1200E6, /* TVAR_ash_pGAS[207] */
+	0x0F1200D0, /* TVAR_ash_pGAS[208] */
+	0x0F120095, /* TVAR_ash_pGAS[209] */
+	0x0F12005D, /* TVAR_ash_pGAS[210] */
+	0x0F120033, /* TVAR_ash_pGAS[211] */
+	0x0F120015, /* TVAR_ash_pGAS[212] */
+	0x0F120005, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120009, /* TVAR_ash_pGAS[215] */
+	0x0F12001E, /* TVAR_ash_pGAS[216] */
+	0x0F120041, /* TVAR_ash_pGAS[217] */
+	0x0F12006D, /* TVAR_ash_pGAS[218] */
+	0x0F1200AA, /* TVAR_ash_pGAS[219] */
+	0x0F1200E4, /* TVAR_ash_pGAS[220] */
+	0x0F1200D6, /* TVAR_ash_pGAS[221] */
+	0x0F12009A, /* TVAR_ash_pGAS[222] */
+	0x0F120062, /* TVAR_ash_pGAS[223] */
+	0x0F120038, /* TVAR_ash_pGAS[224] */
+	0x0F12001B, /* TVAR_ash_pGAS[225] */
+	0x0F12000A, /* TVAR_ash_pGAS[226] */
+	0x0F120006, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120026, /* TVAR_ash_pGAS[229] */
+	0x0F120049, /* TVAR_ash_pGAS[230] */
+	0x0F120076, /* TVAR_ash_pGAS[231] */
+	0x0F1200B4, /* TVAR_ash_pGAS[232] */
+	0x0F1200ED, /* TVAR_ash_pGAS[233] */
+	0x0F1200E4, /* TVAR_ash_pGAS[234] */
+	0x0F1200AB, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F120049, /* TVAR_ash_pGAS[237] */
+	0x0F12002C, /* TVAR_ash_pGAS[238] */
+	0x0F12001C, /* TVAR_ash_pGAS[239] */
+	0x0F120019, /* TVAR_ash_pGAS[240] */
+	0x0F120023, /* TVAR_ash_pGAS[241] */
+	0x0F12003A, /* TVAR_ash_pGAS[242] */
+	0x0F12005D, /* TVAR_ash_pGAS[243] */
+	0x0F12008B, /* TVAR_ash_pGAS[244] */
+	0x0F1200C8, /* TVAR_ash_pGAS[245] */
+	0x0F1200FF, /* TVAR_ash_pGAS[246] */
+	0x0F1200FF, /* TVAR_ash_pGAS[247] */
+	0x0F1200C8, /* TVAR_ash_pGAS[248] */
+	0x0F120090, /* TVAR_ash_pGAS[249] */
+	0x0F120066, /* TVAR_ash_pGAS[250] */
+	0x0F12004A, /* TVAR_ash_pGAS[251] */
+	0x0F12003A, /* TVAR_ash_pGAS[252] */
+	0x0F120038, /* TVAR_ash_pGAS[253] */
+	0x0F120042, /* TVAR_ash_pGAS[254] */
+	0x0F120059, /* TVAR_ash_pGAS[255] */
+	0x0F12007C, /* TVAR_ash_pGAS[256] */
+	0x0F1200AB, /* TVAR_ash_pGAS[257] */
+	0x0F1200E7, /* TVAR_ash_pGAS[258] */
+	0x0F12011D, /* TVAR_ash_pGAS[259] */
+	0x0F120123, /* TVAR_ash_pGAS[260] */
+	0x0F1200EC, /* TVAR_ash_pGAS[261] */
+	0x0F1200B7, /* TVAR_ash_pGAS[262] */
+	0x0F12008E, /* TVAR_ash_pGAS[263] */
+	0x0F120073, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F120062, /* TVAR_ash_pGAS[266] */
+	0x0F12006D, /* TVAR_ash_pGAS[267] */
+	0x0F120083, /* TVAR_ash_pGAS[268] */
+	0x0F1200A7, /* TVAR_ash_pGAS[269] */
+	0x0F1200D4, /* TVAR_ash_pGAS[270] */
+	0x0F12010B, /* TVAR_ash_pGAS[271] */
+	0x0F120144, /* TVAR_ash_pGAS[272] */
+	0x0F120156, /* TVAR_ash_pGAS[273] */
+	0x0F120114, /* TVAR_ash_pGAS[274] */
+	0x0F1200E2, /* TVAR_ash_pGAS[275] */
+	0x0F1200BB, /* TVAR_ash_pGAS[276] */
+	0x0F12009F, /* TVAR_ash_pGAS[277] */
+	0x0F120090, /* TVAR_ash_pGAS[278] */
+	0x0F12008E, /* TVAR_ash_pGAS[279] */
+	0x0F120099, /* TVAR_ash_pGAS[280] */
+	0x0F1200B0, /* TVAR_ash_pGAS[281] */
+	0x0F1200D2, /* TVAR_ash_pGAS[282] */
+	0x0F1200FE, /* TVAR_ash_pGAS[283] */
+	0x0F120133, /* TVAR_ash_pGAS[284] */
+	0x0F12017D, /* TVAR_ash_pGAS[285] */
+	0x0F120174, /* TVAR_ash_pGAS[286] */
+	0x0F12012A, /* TVAR_ash_pGAS[287] */
+	0x0F1200F6, /* TVAR_ash_pGAS[288] */
+	0x0F1200CC, /* TVAR_ash_pGAS[289] */
+	0x0F1200AD, /* TVAR_ash_pGAS[290] */
+	0x0F12009C, /* TVAR_ash_pGAS[291] */
+	0x0F120099, /* TVAR_ash_pGAS[292] */
+	0x0F1200A4, /* TVAR_ash_pGAS[293] */
+	0x0F1200BC, /* TVAR_ash_pGAS[294] */
+	0x0F1200E0, /* TVAR_ash_pGAS[295] */
+	0x0F12010E, /* TVAR_ash_pGAS[296] */
+	0x0F120147, /* TVAR_ash_pGAS[297] */
+	0x0F120193, /* TVAR_ash_pGAS[298] */
+	0x0F12013A, /* TVAR_ash_pGAS[299] */
+	0x0F1200FE, /* TVAR_ash_pGAS[300] */
+	0x0F1200C9, /* TVAR_ash_pGAS[301] */
+	0x0F12009E, /* TVAR_ash_pGAS[302] */
+	0x0F12007E, /* TVAR_ash_pGAS[303] */
+	0x0F12006E, /* TVAR_ash_pGAS[304] */
+	0x0F12006B, /* TVAR_ash_pGAS[305] */
+	0x0F120075, /* TVAR_ash_pGAS[306] */
+	0x0F12008D, /* TVAR_ash_pGAS[307] */
+	0x0F1200B2, /* TVAR_ash_pGAS[308] */
+	0x0F1200E0, /* TVAR_ash_pGAS[309] */
+	0x0F12011B, /* TVAR_ash_pGAS[310] */
+	0x0F120152, /* TVAR_ash_pGAS[311] */
+	0x0F120112, /* TVAR_ash_pGAS[312] */
+	0x0F1200D8, /* TVAR_ash_pGAS[313] */
+	0x0F12009F, /* TVAR_ash_pGAS[314] */
+	0x0F120073, /* TVAR_ash_pGAS[315] */
+	0x0F120054, /* TVAR_ash_pGAS[316] */
+	0x0F120042, /* TVAR_ash_pGAS[317] */
+	0x0F12003F, /* TVAR_ash_pGAS[318] */
+	0x0F120049, /* TVAR_ash_pGAS[319] */
+	0x0F120061, /* TVAR_ash_pGAS[320] */
+	0x0F120085, /* TVAR_ash_pGAS[321] */
+	0x0F1200B5, /* TVAR_ash_pGAS[322] */
+	0x0F1200F2, /* TVAR_ash_pGAS[323] */
+	0x0F120128, /* TVAR_ash_pGAS[324] */
+	0x0F1200F5, /* TVAR_ash_pGAS[325] */
+	0x0F1200BA, /* TVAR_ash_pGAS[326] */
+	0x0F120080, /* TVAR_ash_pGAS[327] */
+	0x0F120054, /* TVAR_ash_pGAS[328] */
+	0x0F120034, /* TVAR_ash_pGAS[329] */
+	0x0F120022, /* TVAR_ash_pGAS[330] */
+	0x0F12001D, /* TVAR_ash_pGAS[331] */
+	0x0F120027, /* TVAR_ash_pGAS[332] */
+	0x0F12003F, /* TVAR_ash_pGAS[333] */
+	0x0F120064, /* TVAR_ash_pGAS[334] */
+	0x0F120092, /* TVAR_ash_pGAS[335] */
+	0x0F1200CF, /* TVAR_ash_pGAS[336] */
+	0x0F120109, /* TVAR_ash_pGAS[337] */
+	0x0F1200E4, /* TVAR_ash_pGAS[338] */
+	0x0F1200A8, /* TVAR_ash_pGAS[339] */
+	0x0F12006E, /* TVAR_ash_pGAS[340] */
+	0x0F120041, /* TVAR_ash_pGAS[341] */
+	0x0F120021, /* TVAR_ash_pGAS[342] */
+	0x0F12000E, /* TVAR_ash_pGAS[343] */
+	0x0F120008, /* TVAR_ash_pGAS[344] */
+	0x0F120012, /* TVAR_ash_pGAS[345] */
+	0x0F120029, /* TVAR_ash_pGAS[346] */
+	0x0F12004D, /* TVAR_ash_pGAS[347] */
+	0x0F12007C, /* TVAR_ash_pGAS[348] */
+	0x0F1200B8, /* TVAR_ash_pGAS[349] */
+	0x0F1200F3, /* TVAR_ash_pGAS[350] */
+	0x0F1200DF, /* TVAR_ash_pGAS[351] */
+	0x0F1200A2, /* TVAR_ash_pGAS[352] */
+	0x0F120068, /* TVAR_ash_pGAS[353] */
+	0x0F12003B, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120006, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120009, /* TVAR_ash_pGAS[358] */
+	0x0F12001F, /* TVAR_ash_pGAS[359] */
+	0x0F120042, /* TVAR_ash_pGAS[360] */
+	0x0F120071, /* TVAR_ash_pGAS[361] */
+	0x0F1200AE, /* TVAR_ash_pGAS[362] */
+	0x0F1200E9, /* TVAR_ash_pGAS[363] */
+	0x0F1200E4, /* TVAR_ash_pGAS[364] */
+	0x0F1200A7, /* TVAR_ash_pGAS[365] */
+	0x0F12006C, /* TVAR_ash_pGAS[366] */
+	0x0F12003F, /* TVAR_ash_pGAS[367] */
+	0x0F12001E, /* TVAR_ash_pGAS[368] */
+	0x0F12000B, /* TVAR_ash_pGAS[369] */
+	0x0F120004, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F120022, /* TVAR_ash_pGAS[372] */
+	0x0F120044, /* TVAR_ash_pGAS[373] */
+	0x0F120072, /* TVAR_ash_pGAS[374] */
+	0x0F1200AE, /* TVAR_ash_pGAS[375] */
+	0x0F1200EA, /* TVAR_ash_pGAS[376] */
+	0x0F1200F5, /* TVAR_ash_pGAS[377] */
+	0x0F1200B9, /* TVAR_ash_pGAS[378] */
+	0x0F12007D, /* TVAR_ash_pGAS[379] */
+	0x0F120051, /* TVAR_ash_pGAS[380] */
+	0x0F12002F, /* TVAR_ash_pGAS[381] */
+	0x0F12001C, /* TVAR_ash_pGAS[382] */
+	0x0F120015, /* TVAR_ash_pGAS[383] */
+	0x0F12001D, /* TVAR_ash_pGAS[384] */
+	0x0F120031, /* TVAR_ash_pGAS[385] */
+	0x0F120053, /* TVAR_ash_pGAS[386] */
+	0x0F120080, /* TVAR_ash_pGAS[387] */
+	0x0F1200BC, /* TVAR_ash_pGAS[388] */
+	0x0F1200F7, /* TVAR_ash_pGAS[389] */
+	0x0F120111, /* TVAR_ash_pGAS[390] */
+	0x0F1200D6, /* TVAR_ash_pGAS[391] */
+	0x0F12009C, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F12004E, /* TVAR_ash_pGAS[394] */
+	0x0F12003A, /* TVAR_ash_pGAS[395] */
+	0x0F120033, /* TVAR_ash_pGAS[396] */
+	0x0F12003A, /* TVAR_ash_pGAS[397] */
+	0x0F12004E, /* TVAR_ash_pGAS[398] */
+	0x0F12006E, /* TVAR_ash_pGAS[399] */
+	0x0F12009B, /* TVAR_ash_pGAS[400] */
+	0x0F1200D5, /* TVAR_ash_pGAS[401] */
+	0x0F12010F, /* TVAR_ash_pGAS[402] */
+	0x0F120139, /* TVAR_ash_pGAS[403] */
+	0x0F1200FD, /* TVAR_ash_pGAS[404] */
+	0x0F1200C6, /* TVAR_ash_pGAS[405] */
+	0x0F120098, /* TVAR_ash_pGAS[406] */
+	0x0F120077, /* TVAR_ash_pGAS[407] */
+	0x0F120064, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120064, /* TVAR_ash_pGAS[410] */
+	0x0F120076, /* TVAR_ash_pGAS[411] */
+	0x0F120095, /* TVAR_ash_pGAS[412] */
+	0x0F1200C2, /* TVAR_ash_pGAS[413] */
+	0x0F1200F8, /* TVAR_ash_pGAS[414] */
+	0x0F120135, /* TVAR_ash_pGAS[415] */
+	0x0F12016C, /* TVAR_ash_pGAS[416] */
+	0x0F120128, /* TVAR_ash_pGAS[417] */
+	0x0F1200F2, /* TVAR_ash_pGAS[418] */
+	0x0F1200C7, /* TVAR_ash_pGAS[419] */
+	0x0F1200A4, /* TVAR_ash_pGAS[420] */
+	0x0F120092, /* TVAR_ash_pGAS[421] */
+	0x0F12008A, /* TVAR_ash_pGAS[422] */
+	0x0F12008F, /* TVAR_ash_pGAS[423] */
+	0x0F1200A3, /* TVAR_ash_pGAS[424] */
+	0x0F1200C0, /* TVAR_ash_pGAS[425] */
+	0x0F1200EA, /* TVAR_ash_pGAS[426] */
+	0x0F120121, /* TVAR_ash_pGAS[427] */
+	0x0F12016F, /* TVAR_ash_pGAS[428] */
+	0x0F120123, /* TVAR_ash_pGAS[429] */
+	0x0F1200E7, /* TVAR_ash_pGAS[430] */
+	0x0F1200BD, /* TVAR_ash_pGAS[431] */
+	0x0F12009C, /* TVAR_ash_pGAS[432] */
+	0x0F120087, /* TVAR_ash_pGAS[433] */
+	0x0F12007C, /* TVAR_ash_pGAS[434] */
+	0x0F12007B, /* TVAR_ash_pGAS[435] */
+	0x0F120086, /* TVAR_ash_pGAS[436] */
+	0x0F120099, /* TVAR_ash_pGAS[437] */
+	0x0F1200B7, /* TVAR_ash_pGAS[438] */
+	0x0F1200DC, /* TVAR_ash_pGAS[439] */
+	0x0F12010E, /* TVAR_ash_pGAS[440] */
+	0x0F12014A, /* TVAR_ash_pGAS[441] */
+	0x0F1200F1, /* TVAR_ash_pGAS[442] */
+	0x0F1200C1, /* TVAR_ash_pGAS[443] */
+	0x0F120096, /* TVAR_ash_pGAS[444] */
+	0x0F120077, /* TVAR_ash_pGAS[445] */
+	0x0F120062, /* TVAR_ash_pGAS[446] */
+	0x0F120058, /* TVAR_ash_pGAS[447] */
+	0x0F120057, /* TVAR_ash_pGAS[448] */
+	0x0F120061, /* TVAR_ash_pGAS[449] */
+	0x0F120074, /* TVAR_ash_pGAS[450] */
+	0x0F120090, /* TVAR_ash_pGAS[451] */
+	0x0F1200B7, /* TVAR_ash_pGAS[452] */
+	0x0F1200E7, /* TVAR_ash_pGAS[453] */
+	0x0F120113, /* TVAR_ash_pGAS[454] */
+	0x0F1200CB, /* TVAR_ash_pGAS[455] */
+	0x0F12009D, /* TVAR_ash_pGAS[456] */
+	0x0F120071, /* TVAR_ash_pGAS[457] */
+	0x0F120052, /* TVAR_ash_pGAS[458] */
+	0x0F120040, /* TVAR_ash_pGAS[459] */
+	0x0F120035, /* TVAR_ash_pGAS[460] */
+	0x0F120034, /* TVAR_ash_pGAS[461] */
+	0x0F12003D, /* TVAR_ash_pGAS[462] */
+	0x0F12004F, /* TVAR_ash_pGAS[463] */
+	0x0F12006B, /* TVAR_ash_pGAS[464] */
+	0x0F120090, /* TVAR_ash_pGAS[465] */
+	0x0F1200C2, /* TVAR_ash_pGAS[466] */
+	0x0F1200EC, /* TVAR_ash_pGAS[467] */
+	0x0F1200B0, /* TVAR_ash_pGAS[468] */
+	0x0F120082, /* TVAR_ash_pGAS[469] */
+	0x0F120057, /* TVAR_ash_pGAS[470] */
+	0x0F12003A, /* TVAR_ash_pGAS[471] */
+	0x0F120026, /* TVAR_ash_pGAS[472] */
+	0x0F12001B, /* TVAR_ash_pGAS[473] */
+	0x0F120019, /* TVAR_ash_pGAS[474] */
+	0x0F120021, /* TVAR_ash_pGAS[475] */
+	0x0F120033, /* TVAR_ash_pGAS[476] */
+	0x0F12004F, /* TVAR_ash_pGAS[477] */
+	0x0F120072, /* TVAR_ash_pGAS[478] */
+	0x0F1200A2, /* TVAR_ash_pGAS[479] */
+	0x0F1200CF, /* TVAR_ash_pGAS[480] */
+	0x0F12009F, /* TVAR_ash_pGAS[481] */
+	0x0F120072, /* TVAR_ash_pGAS[482] */
+	0x0F120047, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120016, /* TVAR_ash_pGAS[485] */
+	0x0F12000A, /* TVAR_ash_pGAS[486] */
+	0x0F120008, /* TVAR_ash_pGAS[487] */
+	0x0F12000F, /* TVAR_ash_pGAS[488] */
+	0x0F120021, /* TVAR_ash_pGAS[489] */
+	0x0F12003A, /* TVAR_ash_pGAS[490] */
+	0x0F12005C, /* TVAR_ash_pGAS[491] */
+	0x0F12008C, /* TVAR_ash_pGAS[492] */
+	0x0F1200BB, /* TVAR_ash_pGAS[493] */
+	0x0F12009A, /* TVAR_ash_pGAS[494] */
+	0x0F12006C, /* TVAR_ash_pGAS[495] */
+	0x0F120042, /* TVAR_ash_pGAS[496] */
+	0x0F120024, /* TVAR_ash_pGAS[497] */
+	0x0F120010, /* TVAR_ash_pGAS[498] */
+	0x0F120004, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120007, /* TVAR_ash_pGAS[501] */
+	0x0F120018, /* TVAR_ash_pGAS[502] */
+	0x0F120030, /* TVAR_ash_pGAS[503] */
+	0x0F120050, /* TVAR_ash_pGAS[504] */
+	0x0F120080, /* TVAR_ash_pGAS[505] */
+	0x0F1200AF, /* TVAR_ash_pGAS[506] */
+	0x0F12009F, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F120046, /* TVAR_ash_pGAS[509] */
+	0x0F120028, /* TVAR_ash_pGAS[510] */
+	0x0F120014, /* TVAR_ash_pGAS[511] */
+	0x0F120006, /* TVAR_ash_pGAS[512] */
+	0x0F120003, /* TVAR_ash_pGAS[513] */
+	0x0F120009, /* TVAR_ash_pGAS[514] */
+	0x0F120019, /* TVAR_ash_pGAS[515] */
+	0x0F120030, /* TVAR_ash_pGAS[516] */
+	0x0F120051, /* TVAR_ash_pGAS[517] */
+	0x0F120080, /* TVAR_ash_pGAS[518] */
+	0x0F1200B0, /* TVAR_ash_pGAS[519] */
+	0x0F1200AD, /* TVAR_ash_pGAS[520] */
+	0x0F120080, /* TVAR_ash_pGAS[521] */
+	0x0F120055, /* TVAR_ash_pGAS[522] */
+	0x0F120036, /* TVAR_ash_pGAS[523] */
+	0x0F120021, /* TVAR_ash_pGAS[524] */
+	0x0F120015, /* TVAR_ash_pGAS[525] */
+	0x0F120010, /* TVAR_ash_pGAS[526] */
+	0x0F120016, /* TVAR_ash_pGAS[527] */
+	0x0F120024, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F12005B, /* TVAR_ash_pGAS[530] */
+	0x0F12008B, /* TVAR_ash_pGAS[531] */
+	0x0F1200BA, /* TVAR_ash_pGAS[532] */
+	0x0F1200C8, /* TVAR_ash_pGAS[533] */
+	0x0F120099, /* TVAR_ash_pGAS[534] */
+	0x0F12006E, /* TVAR_ash_pGAS[535] */
+	0x0F12004E, /* TVAR_ash_pGAS[536] */
+	0x0F12003A, /* TVAR_ash_pGAS[537] */
+	0x0F12002D, /* TVAR_ash_pGAS[538] */
+	0x0F12002A, /* TVAR_ash_pGAS[539] */
+	0x0F12002E, /* TVAR_ash_pGAS[540] */
+	0x0F12003B, /* TVAR_ash_pGAS[541] */
+	0x0F120051, /* TVAR_ash_pGAS[542] */
+	0x0F120072, /* TVAR_ash_pGAS[543] */
+	0x0F1200A1, /* TVAR_ash_pGAS[544] */
+	0x0F1200D2, /* TVAR_ash_pGAS[545] */
+	0x0F1200EC, /* TVAR_ash_pGAS[546] */
+	0x0F1200BE, /* TVAR_ash_pGAS[547] */
+	0x0F120092, /* TVAR_ash_pGAS[548] */
+	0x0F120072, /* TVAR_ash_pGAS[549] */
+	0x0F12005C, /* TVAR_ash_pGAS[550] */
+	0x0F120050, /* TVAR_ash_pGAS[551] */
+	0x0F12004D, /* TVAR_ash_pGAS[552] */
+	0x0F120050, /* TVAR_ash_pGAS[553] */
+	0x0F12005D, /* TVAR_ash_pGAS[554] */
+	0x0F120073, /* TVAR_ash_pGAS[555] */
+	0x0F120094, /* TVAR_ash_pGAS[556] */
+	0x0F1200C2, /* TVAR_ash_pGAS[557] */
+	0x0F1200F4, /* TVAR_ash_pGAS[558] */
+	0x0F12011A, /* TVAR_ash_pGAS[559] */
+	0x0F1200E3, /* TVAR_ash_pGAS[560] */
+	0x0F1200B7, /* TVAR_ash_pGAS[561] */
+	0x0F120097, /* TVAR_ash_pGAS[562] */
+	0x0F120081, /* TVAR_ash_pGAS[563] */
+	0x0F120075, /* TVAR_ash_pGAS[564] */
+	0x0F12006F, /* TVAR_ash_pGAS[565] */
+	0x0F120074, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120097, /* TVAR_ash_pGAS[568] */
+	0x0F1200B8, /* TVAR_ash_pGAS[569] */
+	0x0F1200E7, /* TVAR_ash_pGAS[570] */
+	0x0F120127, /* TVAR_ash_pGAS[571] */
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[0][15] */
+
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[1][15] */
+
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[2][15] */
+
+
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone  */
+	0x0F120000, /* awbb_LowBr0_NBzone */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv */
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F120264,
+	0x0F120279,
+	0x0F120250,
+	0x0F120287,
+	0x0F120244,
+	0x0F120287,
+	0x0F120235,
+	0x0F120289,
+	0x0F120225,
+	0x0F120287,
+	0x0F120213,
+	0x0F120286,
+	0x0F120202,
+	0x0F12027A,
+	0x0F1201F3,
+	0x0F120272,
+	0x0F1201E9,
+	0x0F120269,
+	0x0F1201E2,
+	0x0F120263,
+	0x0F1201E0,
+	0x0F12025A,
+	0x0F1201E1,
+	0x0F120256,
+	0x0F1201EE,
+	0x0F120251,
+	0x0F1201F8,
+	0x0F12024A,
+	0x0F12020D,
+	0x0F120231,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120011,
+	0x0F120000,
+	0x0F1201FF,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120058, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120058, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120058, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F120000, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F120000, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120000, /* awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F120000, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F120FD7, /* awbb_GridConst_2_0  */
+	0x0F1210C5, /* awbb_GridConst_2_1  */
+	0x0F12116A, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000, /* awbb_OutdoorFltrSz (outdoor WB moving average filtering) */
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+
+	0x0F1201FB, /* 01FB */
+	0x0F12FFA9, /* FF9C */
+	0x0F12FFEA, /* FFFF */
+	0x0F120134, /* 0137 */
+	0x0F120133, /* 0113 */
+	0x0F12FF5D, /* FF6F */
+	0x0F12FE7A, /* FF21 */
+	0x0F12017D, /* 0194 */
+	0x0F12FEED, /* FF69 */
+	0x0F12FF39, /* FF14 */
+	0x0F1201D6, /* 0158 */
+	0x0F1200C4, /* 015D */
+	0x0F12FFCE, /* FFF2 */
+	0x0F12FFCD, /* FFF1 */
+	0x0F1201B7, /* 0179 */
+	0x0F120176, /* 017C */
+	0x0F12FFBD, /* FFC3 */
+	0x0F120191, /* 0197 */
+
+	0x0F1201FB, /* 01FB */
+	0x0F12FFA9, /* FF9C */
+	0x0F12FFEA, /* FFFF */
+	0x0F120134, /* 0137 */
+	0x0F120133, /* 0113 */
+	0x0F12FF5D, /* FF6F */
+	0x0F12FE7A, /* FF21 */
+	0x0F12017D, /* 0194 */
+	0x0F12FEED, /* FF69 */
+	0x0F12FF39, /* FF14 */
+	0x0F1201D6, /* 0158 */
+	0x0F1200C4, /* 015D */
+	0x0F12FFCE, /* FFF2 */
+	0x0F12FFCD, /* FFF1 */
+	0x0F1201B7, /* 0179 */
+	0x0F120176, /* 017C */
+	0x0F12FFBD, /* FFC3 */
+	0x0F120191, /* 0197 */
+
+	0x0F1201D2, /* 01D0 */
+	0x0F12FFC2, /* FFB4 */
+	0x0F12FFFC, /* 000C */
+	0x0F12011E, /* 0122 */
+	0x0F12011D, /* 0103 */
+	0x0F12FF86, /* FF9B */
+	0x0F12FE78, /* FF33 */
+	0x0F12017B, /* 01C5 */
+	0x0F12FEEB, /* FF33 */
+	0x0F12FF38, /* FF16 */
+	0x0F1201D5, /* 015A */
+	0x0F1200C3, /* 015F */
+	0x0F12FFCF, /* FFE0 */
+	0x0F12FFCE, /* FFDF */
+	0x0F1201B8, /* 0197 */
+	0x0F120178, /* 0178 */
+	0x0F12FFBF, /* FFBF */
+	0x0F120193, /* 0193 */
+
+	0x0F1201E0, /* outdoor CCM */
+	0x0F12FFBF,
+	0x0F12FFFD,
+	0x0F1200F5,
+	0x0F120139,
+	0x0F12FF74,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /* afit_bUseNoiseInd 0 : NB 1: Noise Index */
+
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+
+	/* Set AFIT */
+	/* AFIT Start Address */
+	0x002A0814,
+	0x0F12082C, /* TVAR_afit_pBaseVals */
+	0x0F127000, /* TVAR_afit_pBaseVals */
+
+	/* param_start	TVAR_afit_pBaseVals */
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120030, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F1203ff, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F1203ff, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12090F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F120032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120412, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F12040C, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120005, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120805, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F1201AA, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120032, /*  RGB2YUV_iYOffset                                                      */
+
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120114, /* UVDenoise_iYLowThresh*/
+	0x0F12020A, /* UVDenoise_iYHighThresh*/
+	0x0F1203FF, /* UVDenoise_iUVLowThresh*/
+	0x0F1203FF, /* UVDenoise_iUVHighThresh*/
+	0x0F120028, /* DSMix1_iLowLimit_Wide*/
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin*/
+	0x0F120014, /* DSMix1_iHighLimit_Wide*/
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin*/
+	0x0F120050, /* DSMix1_iLowLimit_Fine*/
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin*/
+	0x0F120046, /* DSMix1_iHighLimit_Fine*/
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin*/
+	0x0F120106, /* DSMix1_iRGBOffset*/
+	0x0F12006F, /* DSMix1_iDemClamp*/
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin" bin: desparity low */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin" */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12090F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F120032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120412, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F12040C, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120005, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120805, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F1201A0, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120015, /*  RGB2YUV_iYOffset                                                      */
+
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120129, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12100F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F121032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F120002, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122019, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F122032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F12000A, /* SATURATION                                                             */
+	0x0F120008, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                  */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F121408, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F120F05, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120105, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122019, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F122032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12805A, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                         */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                        */
+	0x0F120800, /* Denoise1_sensor_width                            */
+	0x0F120600, /* Denoise1_sensor_height                           */
+	0x0F120000, /* Denoise1_start_x                                 */
+	0x0F120000, /* Denoise1_start_y                                 */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "         */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "       */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  " */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "          */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "        */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "     */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "    */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh"*/
+	0x0F120000, /*  Demosaic4_iBypassSelect                         */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Wifi VT-Call END of Initial */
+};
+
+/*===========================================
+* CAMERA_PREVIEW - ÃÔ¿µ ÈÄ ÇÁ¸®ºä º¹±Í½Ã ¼ÂÆà *
+============================================*/
+
+static const u32 s5k5bafx_preview[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+
+};
+
+/*===========================================
+*	CAMERA_SNAPSHOT  - ÃÔ¿µ 		  *
+============================================*/
+
+static const u32 s5k5bafx_capture[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0224,
+	0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A0226,
+	0x0F120001, /* REG_TC_GP_CapConfigChanged */
+	0x002A01F4,
+	0x0F120001, /* REG_TC_GP_EnableCapture */
+	0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_recording_60Hz_common[] = {
+
+	/* recording 25fps Anti-Flicker 60Hz*/
+
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* p100	Delay */
+
+
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+
+
+	0x002AF900,
+	0x0F120067,
+
+
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+
+	0x002AF4D6,
+	0x0F120090,
+
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A, /* TVAR_ae_BrAve */
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+
+
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /* uMaxExp1 */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /* uMaxExp2 */
+	0x0F120000,
+	0x0F12A122, /* uMaxExp3 */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /* uMaxExp4 */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0, /* lt_uMaxAnGain0   */
+	0x0F1201E0, /* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300, /* lt_uMaxAnGain1 */
+	0x0F120650, /* lt_uMaxAnGain2 */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /* ae_StatMode */
+
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202A8,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120298,
+
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12005F, /* REG_TC_DBG_AutoAlgEnBits   default : 007F */
+
+
+	0xffff000a, /* p10	Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+
+	/* Parallel or MIPI Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F122EE0, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+
+
+
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* p100                          */
+
+
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+
+
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 30fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight               */
+	0x0F120005, /* REG_0TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd              */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType           */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType      */
+	0x0F12018c, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12018c, /* REG_0TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_0TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_0TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_0TC_PCFG_uRotation              */
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight               */
+	0x0F120005, /* REG_1TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd              */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType           */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType      */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_1TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_1TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_1TC_PCFG_uRotation              */
+
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+
+
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+
+
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120108, /* 100 TVAR_ash_GASOutdoorAlpha_0_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[0][15] */
+
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[1][15] */
+
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[2][15] */
+
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000,
+	0x0F120000,
+	0x002A0E8C,
+	0x0F120000,
+	0x002A0D6C,
+	0x0F120040,
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F12025E, /* 0264 awbb_OutdoorGrZones_m_BGrid_0__m_left    */
+	0x0F120282, /* 0279 awbb_OutdoorGrZones_m_BGrid_0__m_right   */
+	0x0F120240, /* 0250 awbb_OutdoorGrZones_m_BGrid_1__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_1__m_right   */
+	0x0F12022A, /* 0244 awbb_OutdoorGrZones_m_BGrid_2__m_left    */
+	0x0F12029A, /* 0287 awbb_OutdoorGrZones_m_BGrid_2__m_right   */
+	0x0F12021A, /* 0235 awbb_OutdoorGrZones_m_BGrid_3__m_left    */
+	0x0F12029A, /* 0289 awbb_OutdoorGrZones_m_BGrid_3__m_right   */
+	0x0F120206, /* 0225 awbb_OutdoorGrZones_m_BGrid_4__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_4__m_right   */
+	0x0F1201FE, /* 0213 awbb_OutdoorGrZones_m_BGrid_5__m_left    */
+	0x0F12028C, /* 0286 awbb_OutdoorGrZones_m_BGrid_5__m_right   */
+	0x0F1201FA, /* 0202 awbb_OutdoorGrZones_m_BGrid_6__m_left    */
+	0x0F120278, /* 027A awbb_OutdoorGrZones_m_BGrid_6__m_right   */
+	0x0F1201F8, /* 01F3 awbb_OutdoorGrZones_m_BGrid_7__m_left    */
+	0x0F120266, /* 0272 awbb_OutdoorGrZones_m_BGrid_7__m_right   */
+	0x0F120214, /* 01E9 awbb_OutdoorGrZones_m_BGrid_8__m_left    */
+	0x0F120238, /* 0269 awbb_OutdoorGrZones_m_BGrid_8__m_right   */
+	0x0F120000, /* 01E2 awbb_OutdoorGrZones_m_BGrid_9__m_left    */
+	0x0F120000, /* 0263 awbb_OutdoorGrZones_m_BGrid_9__m_right   */
+	0x0F120000, /* 01E0 awbb_OutdoorGrZones_m_BGrid_10__m_left   */
+	0x0F120000, /* 025A awbb_OutdoorGrZones_m_BGrid_10__m_right  */
+	0x0F120000, /* 01E1 awbb_OutdoorGrZones_m_BGrid_11__m_left   */
+	0x0F120000, /* 0256 awbb_OutdoorGrZones_m_BGrid_11__m_right  */
+	0x0F120000, /* 01EE awbb_OutdoorGrZones_m_BGrid_12__m_left   */
+	0x0F120000, /* 0251 awbb_OutdoorGrZones_m_BGrid_12__m_right  */
+	0x0F120000, /* 01F8 awbb_OutdoorGrZones_m_BGrid(26)          */
+	0x0F120000, /* 024A awbb_OutdoorGrZones_m_BGrid(27)          */
+	0x0F120000, /* 020D awbb_OutdoorGrZones_m_BGrid(28)          */
+	0x0F120000, /* 0231 awbb_OutdoorGrZones_m_BGrid(29)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(30)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(31)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(32)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(33)          */
+
+
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/*  7-3. Low Br grey zone                     */
+	/* param_  C4start	awbb_LowBrGrZones_m_BGrid */
+
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120030, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120030, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120030, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6,
+	0x0F120335,
+	0x0F1203B3,
+	0x0F121021,
+	0x0F12107E,
+	0x0F12113E,
+	0x0F12117C,
+	0x0F1211C2,
+	0x0F12120B,
+
+	0x0F1200B3,
+	0x0F1200B7,
+	0x0F1200D3,
+	0x0F120091,
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/* CCM */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /*afit_bUseNoiseInd 0 : NB 1: Noise Index */
+
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120010, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120008, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F1200FF,
+	0x0F1200FF,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120300,
+	0x0F120002,
+	0x0F120400,
+	0x0F120106,
+	0x0F120005,
+	0x0F120000,
+	0x0F120703,
+	0x0F120000,
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Recording 25fps Anti-Flicker 60Hz END of Initial */
+};
+
+static const u32 s5k5bafx_recording_50Hz_common[] = {
+
+	/* recording 25fps Anti-Flicker 50Hz*/
+
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* p100	Delay */
+
+
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+
+
+	0x002AF900,
+	0x0F120067,
+
+
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+
+	0x002AF4D6,
+	0x0F120090,
+
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A, /* TVAR_ae_BrAve */
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+
+
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /* uMaxExp1 */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /* uMaxExp2 */
+	0x0F120000,
+	0x0F12A122, /* uMaxExp3 */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /* uMaxExp4 */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0, /* lt_uMaxAnGain0   */
+	0x0F1201E0, /* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300, /* lt_uMaxAnGain1 */
+	0x0F120650, /* lt_uMaxAnGain2 */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /* ae_StatMode */
+
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202A8,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120298,
+
+	/* 1. Auto Flicker 50Hz Start */
+	0x002A0B2E,
+	0x0F120000, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12005F, /* REG_TC_DBG_AutoAlgEnBits   default : 007F */
+
+
+	0xffff000a, /* p10	Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+
+	/* Parallel or MIPI Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F122EE0, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+
+
+
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* p100                          */
+
+
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+
+
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 30fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight               */
+	0x0F120005, /* REG_0TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd              */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType           */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType      */
+	0x0F12018c, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12018c, /* REG_0TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_0TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_0TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_0TC_PCFG_uRotation              */
+
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight               */
+	0x0F120005, /* REG_1TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd              */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType           */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType      */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_1TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_1TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_1TC_PCFG_uRotation              */
+
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+
+
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+
+
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120108, /* 100 TVAR_ash_GASOutdoorAlpha_0_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[0][15] */
+
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[1][15] */
+
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[2][15] */
+
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000,
+	0x0F120000,
+	0x002A0E8C,
+	0x0F120000,
+	0x002A0D6C,
+	0x0F120040,
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F12025E, /* 0264 awbb_OutdoorGrZones_m_BGrid_0__m_left    */
+	0x0F120282, /* 0279 awbb_OutdoorGrZones_m_BGrid_0__m_right   */
+	0x0F120240, /* 0250 awbb_OutdoorGrZones_m_BGrid_1__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_1__m_right   */
+	0x0F12022A, /* 0244 awbb_OutdoorGrZones_m_BGrid_2__m_left    */
+	0x0F12029A, /* 0287 awbb_OutdoorGrZones_m_BGrid_2__m_right   */
+	0x0F12021A, /* 0235 awbb_OutdoorGrZones_m_BGrid_3__m_left    */
+	0x0F12029A, /* 0289 awbb_OutdoorGrZones_m_BGrid_3__m_right   */
+	0x0F120206, /* 0225 awbb_OutdoorGrZones_m_BGrid_4__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_4__m_right   */
+	0x0F1201FE, /* 0213 awbb_OutdoorGrZones_m_BGrid_5__m_left    */
+	0x0F12028C, /* 0286 awbb_OutdoorGrZones_m_BGrid_5__m_right   */
+	0x0F1201FA, /* 0202 awbb_OutdoorGrZones_m_BGrid_6__m_left    */
+	0x0F120278, /* 027A awbb_OutdoorGrZones_m_BGrid_6__m_right   */
+	0x0F1201F8, /* 01F3 awbb_OutdoorGrZones_m_BGrid_7__m_left    */
+	0x0F120266, /* 0272 awbb_OutdoorGrZones_m_BGrid_7__m_right   */
+	0x0F120214, /* 01E9 awbb_OutdoorGrZones_m_BGrid_8__m_left    */
+	0x0F120238, /* 0269 awbb_OutdoorGrZones_m_BGrid_8__m_right   */
+	0x0F120000, /* 01E2 awbb_OutdoorGrZones_m_BGrid_9__m_left    */
+	0x0F120000, /* 0263 awbb_OutdoorGrZones_m_BGrid_9__m_right   */
+	0x0F120000, /* 01E0 awbb_OutdoorGrZones_m_BGrid_10__m_left   */
+	0x0F120000, /* 025A awbb_OutdoorGrZones_m_BGrid_10__m_right  */
+	0x0F120000, /* 01E1 awbb_OutdoorGrZones_m_BGrid_11__m_left   */
+	0x0F120000, /* 0256 awbb_OutdoorGrZones_m_BGrid_11__m_right  */
+	0x0F120000, /* 01EE awbb_OutdoorGrZones_m_BGrid_12__m_left   */
+	0x0F120000, /* 0251 awbb_OutdoorGrZones_m_BGrid_12__m_right  */
+	0x0F120000, /* 01F8 awbb_OutdoorGrZones_m_BGrid(26)          */
+	0x0F120000, /* 024A awbb_OutdoorGrZones_m_BGrid(27)          */
+	0x0F120000, /* 020D awbb_OutdoorGrZones_m_BGrid(28)          */
+	0x0F120000, /* 0231 awbb_OutdoorGrZones_m_BGrid(29)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(30)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(31)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(32)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(33)          */
+
+
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/*  7-3. Low Br grey zone                     */
+	/* param_  C4start	awbb_LowBrGrZones_m_BGrid */
+
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120030, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120030, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120030, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6,
+	0x0F120335,
+	0x0F1203B3,
+	0x0F121021,
+	0x0F12107E,
+	0x0F12113E,
+	0x0F12117C,
+	0x0F1211C2,
+	0x0F12120B,
+
+	0x0F1200B3,
+	0x0F1200B7,
+	0x0F1200D3,
+	0x0F120091,
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/* CCM */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /*afit_bUseNoiseInd 0 : NB 1: Noise Index */
+
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120010, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120008, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F1200FF,
+	0x0F1200FF,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120300,
+	0x0F120002,
+	0x0F120400,
+	0x0F120106,
+	0x0F120005,
+	0x0F120000,
+	0x0F120703,
+	0x0F120000,
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Recording 25fps Anti-Flicker 50Hz END of Initial */
+};
+
+static const u32 s5k5bafx_stream_stop[] =
+{
+	0xFCFCD000,
+	0x00287000,
+ 	0x002A01F0,
+	0x0F120000, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged*/
+	/*0xffff0096, 150ms*/
+};
+
+#if (0)
+static const u32 s5k5bafx_stream_start[] =
+{
+	0xFCFCD000,
+	0x002AB00C,
+	0x0F120001,
+};
+#endif
+
+/*=================================
+*	CAMERA_BRIGHTNESS_1 (1/9) M4   *
+==================================*/
+static const u32 s5k5bafx_bright_m4[] =
+{
+	/* Brightness -4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FF80, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+*	CAMERA_BRIGHTNESS_2 (2/9) M3  *
+==================================*/
+
+static const u32 s5k5bafx_bright_m3[] =
+{
+	/* Brightness -3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFBC, /* REG_TC_UserBrightness*/
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_3 (3/9) M2
+==================================*/
+static const u32 s5k5bafx_bright_m2[] =
+{
+	/* Brightness -2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFDC, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_4 (4/9) M1
+==================================*/
+
+static const u32 s5k5bafx_bright_m1[] =
+{
+	/* Brightness -1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFF2, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_5 (5/9) Default
+==================================*/
+static const u32 s5k5bafx_bright_default[] =
+{
+	/* Brightness 0 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120000, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_6 (6/9) P1
+==================================*/
+static const u32 s5k5bafx_bright_p1[] =
+{
+	/* Brightness +1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120020, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_7 (7/9) P2
+==================================*/
+static const u32 s5k5bafx_bright_p2[] =
+{
+	/* Brightness +2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120040, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_8 (8/9) P3
+==================================*/
+static const u32 s5k5bafx_bright_p3[] =
+{
+	/* Brightness +3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120060, /* REG_TC_UserBrightness */
+
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_9 (9/9) P4
+==================================*/
+static const u32 s5k5bafx_bright_p4[] =
+{
+	/* Brightness +4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120080, /* REG_TC_UserBrightness */
+};
+
+/*******************************************************
+* CAMERA_VT_PRETTY_0 Default
+* 200s self cam pretty
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_default[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_1
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_1[] =
+{
+	/*0xffff000A,*/
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_2				*
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_2[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_3
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_3[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000, /* 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B,  */
+	0x0F120064, /* 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00DC,  */
+	0x0F120190, /* 95, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01EA,  */
+	0x0F120260, /* 0265, 024E,  */
+	0x0F1202E5, /* 02F0, 02DA,  */
+	0x0F12032A, /* 30, 0335, 0320,  */
+	0x0F12038A, /* 90, 0395, 038E,  */
+	0x0F1203C5, /* CA, 03D0, 03CA, / */
+	0x0F1203E0, /* E5, 03E8, 03E8,  */
+	0x0F1203EC, /* F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400,  */
+
+	0x0F120000, /* 0000, 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B, 001B,  */
+	0x0F120064, /* 0064, 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00E5, 00DC,  */
+	0x0F120190, /* 0195, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01F5, 01EA,  */
+	0x0F120260, /* 0260, 0265, 024E,  */
+	0x0F1202E5, /* 02E5, 02F0, 02DA,  */
+	0x0F12032A, /* 0330, 0335, 0320,  */
+	0x0F12038A, /* 0390, 0395, 038E,  */
+	0x0F1203C5, /* 03CA, 03D0, 03CA,  */
+	0x0F1203E0, /* 03E5, 03E8, 03E8,  */
+	0x0F1203EC, /* 03F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400, 0400,  */
+
+	0x0F120000, /* 0000, 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B, 001B,  */
+	0x0F120064, /* 0064, 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00E5, 00DC,  */
+	0x0F120190, /* 0195, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01F5, 01EA,  */
+	0x0F120260, /* 0260, 0265, 024E,  */
+	0x0F1202E5, /* 02E5, 02F0, 02DA,  */
+	0x0F12032A, /* 0330, 0335, 0320,  */
+	0x0F12038A, /* 0390, 0395, 038E,  */
+	0x0F1203C5, /* 03CA, 03D0, 03CA,  */
+	0x0F1203E0, /* 03E5, 03E8, 03E8,  */
+	0x0F1203EC, /* 03F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400, 0400,  */
+};
+
+static const u32 s5k5bafx_vt_7fps[] =
+{
+	/* Fixed 7fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120535, /* 7fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_10fps[] =
+{
+	/*  Fixed 10fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F1203E8, /* 10fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync  */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged  */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_12fps[] =
+{
+	/*  Fixed 12fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120341, /* 12fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_15fps[] =
+{
+	/* Fixed 15fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F12029A, /* 15fps*/
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged  */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /*mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+/*******************************************************
+*	CAMERA_DTP_ON
+*******************************************************/
+static const u32 s5k5bafx_pattern_on[] = {
+	0xffff01f4, /* Delay 500ms*/
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12FFF0, /* SARR_uNormBrInDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrInDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrInDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrInDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrInDoor[4] */
+
+	0x002A07F6,
+	0x0F12FFF0, /* SARR_uNormBrOutDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrOutDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrOutDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrOutDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a3, /* gas bypass */
+	0x002a6600,
+	0x0f120001, /* ccm bypass */
+	0x002a6800,
+	0x0f120001, /* gamma bypass */
+	0x002a4400,
+	0x0f120001, /* awb bypass */
+
+	0x00287000,
+	0x002A03b6,
+	0x0F120001,
+	0x002A03ba,
+	0x0F120001, /* LEI control */
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120002, /* Colorbar pattern */
+
+	0xffff0032, /* Delay 50msec */
+};
+
+/*******************************************************
+*	CAMERA_DTP_OFF
+*******************************************************/
+static const u32 s5k5bafx_pattern_off[] = {
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	0x002A07F6,
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a2, /* gas bypass */
+	0x002a6600,
+	0x0f120000, /* ccm bypass */
+	0x002a6800,
+	0x0f120000, /* gamma bypass */
+	0x002a4400,
+	0x0f120000, /* awb bypass */
+
+	0x00287000,
+	0x002A03F8,
+	0x0F120079,
+
+	0xffff012c, /* Delay 300ms */
+	0x002A03F8,
+	0x0F12007F,
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120000, /* Colorbar pattern */
+};
+
+#endif /* __S5K5BAFX_SETFILE_H */
diff --git a/drivers/media/video/s5k5bafx_setfile_lgt.h b/drivers/media/video/s5k5bafx_setfile_lgt.h
new file mode 100755
index 0000000..3a9a7b3
--- /dev/null
+++ b/drivers/media/video/s5k5bafx_setfile_lgt.h
@@ -0,0 +1,13478 @@
+/*
+ * Driver for S5K5BAFX 2M ISP from Samsung
+ *
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __S5K5BAFX_SETFILE_H
+#define __S5K5BAFX_SETFILE_H
+
+#include <linux/types.h>
+
+/*
+ * s5k5bafx register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name		: S5K5BAFX Initial Setfile
+* PLL mode	: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS		: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by	: ZEROHOY
+* Date		: 2011.03.07
+* History	: Edge °ú´ÙÇ¥Çö °ü·Ã AFIT ¼öÁ¤(2011.03.07)
+*             µ¿¿µ»ó 25fps ¼ÂÆ𪠼öÁ¤(2011.03.07)
+*             Wifi VT-Call Edge Á¦°Å(2011.03.05)
+*******************************************************/
+static const u32 s5k5bafx_common[] = {
+	/* Self-Cam */
+	0xFCFCD000,
+
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064,
+
+	/* Trap and Patch */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE, /*70001668*/
+	0x0F120007, /*7000166A*/
+	0x0F12683C, /*7000166C*/
+	0x0F12687E, /*7000166E*/
+	0x0F121DA5, /*70001670*/
+	0x0F1288A0, /*70001672*/
+	0x0F122800, /*70001674*/
+	0x0F12D00B, /*70001676*/
+	0x0F1288A8, /*70001678*/
+	0x0F122800, /*7000167A*/
+	0x0F12D008, /*7000167C*/
+	0x0F128820, /*7000167E*/
+	0x0F128829, /*70001680*/
+	0x0F124288, /*70001682*/
+	0x0F12D301, /*70001684*/
+	0x0F121A40, /*70001686*/
+	0x0F12E000, /*70001688*/
+	0x0F121A08, /*7000168A*/
+	0x0F129001, /*7000168C*/
+	0x0F12E001, /*7000168E*/
+	0x0F122019, /*70001690*/
+	0x0F129001, /*70001692*/
+	0x0F124916, /*70001694*/
+	0x0F12466B, /*70001696*/
+	0x0F128A48, /*70001698*/
+	0x0F128118, /*7000169A*/
+	0x0F128A88, /*7000169C*/
+	0x0F128158, /*7000169E*/
+	0x0F124814, /*700016A0*/
+	0x0F128940, /*700016A2*/
+	0x0F120040, /*700016A4*/
+	0x0F122103, /*700016A6*/
+	0x0F12F000, /*700016A8*/
+	0x0F12F826, /*700016AA*/
+	0x0F1288A1, /*700016AC*/
+	0x0F124288, /*700016AE*/
+	0x0F12D908, /*700016B0*/
+	0x0F128828, /*700016B2*/
+	0x0F128030, /*700016B4*/
+	0x0F128868, /*700016B6*/
+	0x0F128070, /*700016B8*/
+	0x0F1288A8, /*700016BA*/
+	0x0F126038, /*700016BC*/
+	0x0F12BCFE, /*700016BE*/
+	0x0F12BC08, /*700016C0*/
+	0x0F124718, /*700016C2*/
+	0x0F1288A9, /*700016C4*/
+	0x0F124288, /*700016C6*/
+	0x0F12D906, /*700016C8*/
+	0x0F128820, /*700016CA*/
+	0x0F128030, /*700016CC*/
+	0x0F128860, /*700016CE*/
+	0x0F128070, /*700016D0*/
+	0x0F1288A0, /*700016D2*/
+	0x0F126038, /*700016D4*/
+	0x0F12E7F2, /*700016D6*/
+	0x0F129801, /*700016D8*/
+	0x0F12A902, /*700016DA*/
+	0x0F12F000, /*700016DC*/
+	0x0F12F812, /*700016DE*/
+	0x0F120033, /*700016E0*/
+	0x0F120029, /*700016E2*/
+	0x0F129A02, /*700016E4*/
+	0x0F120020, /*700016E6*/
+	0x0F12F000, /*700016E8*/
+	0x0F12F814, /*700016EA*/
+	0x0F126038, /*700016EC*/
+	0x0F12E7E6, /*700016EE*/
+	0x0F121A28, /*700016F0*/
+	0x0F127000, /*700016F2*/
+	0x0F120D64, /*700016F4*/
+	0x0F127000, /*700016F6*/
+	0x0F124778, /*700016F8*/
+	0x0F1246C0, /*700016FA*/
+	0x0F12F004, /*700016FC*/
+	0x0F12E51F, /*700016FE*/
+	0x0F12A464, /*70001700*/
+	0x0F120000, /*70001702*/
+	0x0F124778, /*70001704*/
+	0x0F1246C0, /*70001706*/
+	0x0F12C000, /*70001708*/
+	0x0F12E59F, /*7000170A*/
+	0x0F12FF1C, /*7000170C*/
+	0x0F12E12F, /*7000170E*/
+	0x0F126009, /*70001710*/
+	0x0F120000, /*70001712*/
+	0x0F124778, /*70001714*/
+	0x0F1246C0, /*70001716*/
+	0x0F12C000, /*70001718*/
+	0x0F12E59F, /*7000171A*/
+	0x0F12FF1C, /*7000171C*/
+	0x0F12E12F, /*7000171E*/
+	0x0F12622F, /*70001720*/
+	0x0F120000, /*70001722*/
+	0x002A2080,
+	0x0F12B510, /*70002080*/
+	0x0F12F000, /*70002082*/
+	0x0F12F8F4, /*70002084*/
+	0x0F12BC10, /*70002086*/
+	0x0F12BC08, /*70002088*/
+	0x0F124718, /*7000208A*/
+	0x0F12B5F0, /*7000208C*/
+	0x0F12B08B, /*7000208E*/
+	0x0F120006, /*70002090*/
+	0x0F122000, /*70002092*/
+	0x0F129004, /*70002094*/
+	0x0F126835, /*70002096*/
+	0x0F126874, /*70002098*/
+	0x0F1268B0, /*7000209A*/
+	0x0F12900A, /*7000209C*/
+	0x0F1268F0, /*7000209E*/
+	0x0F129009, /*700020A0*/
+	0x0F124F7D, /*700020A2*/
+	0x0F128979, /*700020A4*/
+	0x0F12084A, /*700020A6*/
+	0x0F1288A8, /*700020A8*/
+	0x0F1288A3, /*700020AA*/
+	0x0F124298, /*700020AC*/
+	0x0F12D300, /*700020AE*/
+	0x0F120018, /*700020B0*/
+	0x0F12F000, /*700020B2*/
+	0x0F12F907, /*700020B4*/
+	0x0F129007, /*700020B6*/
+	0x0F120021, /*700020B8*/
+	0x0F120028, /*700020BA*/
+	0x0F12AA04, /*700020BC*/
+	0x0F12F000, /*700020BE*/
+	0x0F12F909, /*700020C0*/
+	0x0F129006, /*700020C2*/
+	0x0F1288A8, /*700020C4*/
+	0x0F122800, /*700020C6*/
+	0x0F12D102, /*700020C8*/
+	0x0F1227FF, /*700020CA*/
+	0x0F121C7F, /*700020CC*/
+	0x0F12E047, /*700020CE*/
+	0x0F1288A0, /*700020D0*/
+	0x0F122800, /*700020D2*/
+	0x0F12D101, /*700020D4*/
+	0x0F122700, /*700020D6*/
+	0x0F12E042, /*700020D8*/
+	0x0F128820, /*700020DA*/
+	0x0F12466B, /*700020DC*/
+	0x0F128198, /*700020DE*/
+	0x0F128860, /*700020E0*/
+	0x0F1281D8, /*700020E2*/
+	0x0F128828, /*700020E4*/
+	0x0F128118, /*700020E6*/
+	0x0F128868, /*700020E8*/
+	0x0F128158, /*700020EA*/
+	0x0F12A802, /*700020EC*/
+	0x0F12C803, /*700020EE*/
+	0x0F12F000, /*700020F0*/
+	0x0F12F8F8, /*700020F2*/
+	0x0F129008, /*700020F4*/
+	0x0F128ABA, /*700020F6*/
+	0x0F129808, /*700020F8*/
+	0x0F12466B, /*700020FA*/
+	0x0F124342, /*700020FC*/
+	0x0F129202, /*700020FE*/
+	0x0F128820, /*70002100*/
+	0x0F128198, /*70002102*/
+	0x0F128860, /*70002104*/
+	0x0F1281D8, /*70002106*/
+	0x0F12980A, /*70002108*/
+	0x0F129903, /*7000210A*/
+	0x0F12F000, /*7000210C*/
+	0x0F12F8EA, /*7000210E*/
+	0x0F129A02, /*70002110*/
+	0x0F1217D1, /*70002112*/
+	0x0F120E09, /*70002114*/
+	0x0F121889, /*70002116*/
+	0x0F121209, /*70002118*/
+	0x0F124288, /*7000211A*/
+	0x0F12DD1F, /*7000211C*/
+	0x0F128820, /*7000211E*/
+	0x0F12466B, /*70002120*/
+	0x0F128198, /*70002122*/
+	0x0F128860, /*70002124*/
+	0x0F1281D8, /*70002126*/
+	0x0F12980A, /*70002128*/
+	0x0F129903, /*7000212A*/
+	0x0F12F000, /*7000212C*/
+	0x0F12F8DA, /*7000212E*/
+	0x0F129001, /*70002130*/
+	0x0F128828, /*70002132*/
+	0x0F12466B, /*70002134*/
+	0x0F128118, /*70002136*/
+	0x0F128868, /*70002138*/
+	0x0F128158, /*7000213A*/
+	0x0F12980A, /*7000213C*/
+	0x0F129902, /*7000213E*/
+	0x0F12F000, /*70002140*/
+	0x0F12F8D0, /*70002142*/
+	0x0F128AB9, /*70002144*/
+	0x0F129A08, /*70002146*/
+	0x0F124351, /*70002148*/
+	0x0F1217CA, /*7000214A*/
+	0x0F120E12, /*7000214C*/
+	0x0F121851, /*7000214E*/
+	0x0F12120A, /*70002150*/
+	0x0F129901, /*70002152*/
+	0x0F12F000, /*70002154*/
+	0x0F12F8B6, /*70002156*/
+	0x0F120407, /*70002158*/
+	0x0F120C3F, /*7000215A*/
+	0x0F12E000, /*7000215C*/
+	0x0F122700, /*7000215E*/
+	0x0F128820, /*70002160*/
+	0x0F12466B, /*70002162*/
+	0x0F12AA05, /*70002164*/
+	0x0F128198, /*70002166*/
+	0x0F128860, /*70002168*/
+	0x0F1281D8, /*7000216A*/
+	0x0F128828, /*7000216C*/
+	0x0F128118, /*7000216E*/
+	0x0F128868, /*70002170*/
+	0x0F128158, /*70002172*/
+	0x0F12A802, /*70002174*/
+	0x0F12C803, /*70002176*/
+	0x0F12003B, /*70002178*/
+	0x0F12F000, /*7000217A*/
+	0x0F12F8BB, /*7000217C*/
+	0x0F1288A1, /*7000217E*/
+	0x0F1288A8, /*70002180*/
+	0x0F12003A, /*70002182*/
+	0x0F12F000, /*70002184*/
+	0x0F12F8BE, /*70002186*/
+	0x0F120004, /*70002188*/
+	0x0F12A804, /*7000218A*/
+	0x0F12C803, /*7000218C*/
+	0x0F129A09, /*7000218E*/
+	0x0F129B07, /*70002190*/
+	0x0F12F000, /*70002192*/
+	0x0F12F8AF, /*70002194*/
+	0x0F12A806, /*70002196*/
+	0x0F12C805, /*70002198*/
+	0x0F120021, /*7000219A*/
+	0x0F12F000, /*7000219C*/
+	0x0F12F8B2, /*7000219E*/
+	0x0F126030, /*700021A0*/
+	0x0F12B00B, /*700021A2*/
+	0x0F12BCF0, /*700021A4*/
+	0x0F12BC08, /*700021A6*/
+	0x0F124718, /*700021A8*/
+	0x0F12B5F1, /*700021AA*/
+	0x0F129900, /*700021AC*/
+	0x0F12680C, /*700021AE*/
+	0x0F12493A, /*700021B0*/
+	0x0F12694B, /*700021B2*/
+	0x0F12698A, /*700021B4*/
+	0x0F124694, /*700021B6*/
+	0x0F1269CD, /*700021B8*/
+	0x0F126A0E, /*700021BA*/
+	0x0F124F38, /*700021BC*/
+	0x0F1242BC, /*700021BE*/
+	0x0F12D800, /*700021C0*/
+	0x0F120027, /*700021C2*/
+	0x0F124937, /*700021C4*/
+	0x0F126B89, /*700021C6*/
+	0x0F120409, /*700021C8*/
+	0x0F120C09, /*700021CA*/
+	0x0F124A35, /*700021CC*/
+	0x0F121E92, /*700021CE*/
+	0x0F126BD2, /*700021D0*/
+	0x0F120412, /*700021D2*/
+	0x0F120C12, /*700021D4*/
+	0x0F12429F, /*700021D6*/
+	0x0F12D801, /*700021D8*/
+	0x0F120020, /*700021DA*/
+	0x0F12E031, /*700021DC*/
+	0x0F12001F, /*700021DE*/
+	0x0F12434F, /*700021E0*/
+	0x0F120A3F, /*700021E2*/
+	0x0F1242A7, /*700021E4*/
+	0x0F12D301, /*700021E6*/
+	0x0F120018, /*700021E8*/
+	0x0F12E02A, /*700021EA*/
+	0x0F12002B, /*700021EC*/
+	0x0F12434B, /*700021EE*/
+	0x0F120A1B, /*700021F0*/
+	0x0F1242A3, /*700021F2*/
+	0x0F12D303, /*700021F4*/
+	0x0F120220, /*700021F6*/
+	0x0F12F000, /*700021F8*/
+	0x0F12F88C, /*700021FA*/
+	0x0F12E021, /*700021FC*/
+	0x0F120029, /*700021FE*/
+	0x0F124351, /*70002200*/
+	0x0F120A09, /*70002202*/
+	0x0F1242A1, /*70002204*/
+	0x0F12D301, /*70002206*/
+	0x0F120028, /*70002208*/
+	0x0F12E01A, /*7000220A*/
+	0x0F120031, /*7000220C*/
+	0x0F124351, /*7000220E*/
+	0x0F120A09, /*70002210*/
+	0x0F1242A1, /*70002212*/
+	0x0F12D304, /*70002214*/
+	0x0F120220, /*70002216*/
+	0x0F120011, /*70002218*/
+	0x0F12F000, /*7000221A*/
+	0x0F12F87B, /*7000221C*/
+	0x0F12E010, /*7000221E*/
+	0x0F12491E, /*70002220*/
+	0x0F128C89, /*70002222*/
+	0x0F12000A, /*70002224*/
+	0x0F124372, /*70002226*/
+	0x0F120A12, /*70002228*/
+	0x0F1242A2, /*7000222A*/
+	0x0F12D301, /*7000222C*/
+	0x0F120030, /*7000222E*/
+	0x0F12E007, /*70002230*/
+	0x0F124662, /*70002232*/
+	0x0F12434A, /*70002234*/
+	0x0F120A12, /*70002236*/
+	0x0F1242A2, /*70002238*/
+	0x0F12D302, /*7000223A*/
+	0x0F120220, /*7000223C*/
+	0x0F12F000, /*7000223E*/
+	0x0F12F869, /*70002240*/
+	0x0F124B16, /*70002242*/
+	0x0F124D18, /*70002244*/
+	0x0F128D99, /*70002246*/
+	0x0F121FCA, /*70002248*/
+	0x0F123AF9, /*7000224A*/
+	0x0F12D00A, /*7000224C*/
+	0x0F122001, /*7000224E*/
+	0x0F120240, /*70002250*/
+	0x0F128468, /*70002252*/
+	0x0F120220, /*70002254*/
+	0x0F12F000, /*70002256*/
+	0x0F12F85D, /*70002258*/
+	0x0F129900, /*7000225A*/
+	0x0F126008, /*7000225C*/
+	0x0F12BCF8, /*7000225E*/
+	0x0F12BC08, /*70002260*/
+	0x0F124718, /*70002262*/
+	0x0F128D19, /*70002264*/
+	0x0F128469, /*70002266*/
+	0x0F129900, /*70002268*/
+	0x0F126008, /*7000226A*/
+	0x0F12E7F7, /*7000226C*/
+	0x0F12B570, /*7000226E*/
+	0x0F122200, /*70002270*/
+	0x0F12490E, /*70002272*/
+	0x0F12480E, /*70002274*/
+	0x0F122401, /*70002276*/
+	0x0F12F000, /*70002278*/
+	0x0F12F852, /*7000227A*/
+	0x0F120022, /*7000227C*/
+	0x0F12490D, /*7000227E*/
+	0x0F12480D, /*70002280*/
+	0x0F122502, /*70002282*/
+	0x0F12F000, /*70002284*/
+	0x0F12F84C, /*70002286*/
+	0x0F12490C, /*70002288*/
+	0x0F12480D, /*7000228A*/
+	0x0F12002A, /*7000228C*/
+	0x0F12F000, /*7000228E*/
+	0x0F12F847, /*70002290*/
+	0x0F12BC70, /*70002292*/
+	0x0F12BC08, /*70002294*/
+	0x0F124718, /*70002296*/
+	0x0F120D64, /*70002298*/
+	0x0F127000, /*7000229A*/
+	0x0F120470, /*7000229C*/
+	0x0F127000, /*7000229E*/
+	0x0F12A120, /*700022A0*/
+	0x0F120007, /*700022A2*/
+	0x0F120402, /*700022A4*/
+	0x0F127000, /*700022A6*/
+	0x0F1214A0, /*700022A8*/
+	0x0F127000, /*700022AA*/
+	0x0F12208D, /*700022AC*/
+	0x0F127000, /*700022AE*/
+	0x0F12622F, /*700022B0*/
+	0x0F120000, /*700022B2*/
+	0x0F121669, /*700022B4*/
+	0x0F127000, /*700022B6*/
+	0x0F126445, /*700022B8*/
+	0x0F120000, /*700022BA*/
+	0x0F1221AB, /*700022BC*/
+	0x0F127000, /*700022BE*/
+	0x0F122AA9, /*700022C0*/
+	0x0F120000, /*700022C2*/
+	0x0F124778, /*700022C4*/
+	0x0F1246C0, /*700022C6*/
+	0x0F12C000, /*700022C8*/
+	0x0F12E59F, /*700022CA*/
+	0x0F12FF1C, /*700022CC*/
+	0x0F12E12F, /*700022CE*/
+	0x0F125F49, /*700022D0*/
+	0x0F120000, /*700022D2*/
+	0x0F124778, /*700022D4*/
+	0x0F1246C0, /*700022D6*/
+	0x0F12C000, /*700022D8*/
+	0x0F12E59F, /*700022DA*/
+	0x0F12FF1C, /*700022DC*/
+	0x0F12E12F, /*700022DE*/
+	0x0F125FC7, /*700022E0*/
+	0x0F120000, /*700022E2*/
+	0x0F124778, /*700022E4*/
+	0x0F1246C0, /*700022E6*/
+	0x0F12C000, /*700022E8*/
+	0x0F12E59F, /*700022EA*/
+	0x0F12FF1C, /*700022EC*/
+	0x0F12E12F, /*700022EE*/
+	0x0F125457, /*700022F0*/
+	0x0F120000, /*700022F2*/
+	0x0F124778, /*700022F4*/
+	0x0F1246C0, /*700022F6*/
+	0x0F12C000, /*700022F8*/
+	0x0F12E59F, /*700022FA*/
+	0x0F12FF1C, /*700022FC*/
+	0x0F12E12F, /*700022FE*/
+	0x0F125FA3, /*70002300*/
+	0x0F120000, /*70002302*/
+	0x0F124778, /*70002304*/
+	0x0F1246C0, /*70002306*/
+	0x0F12C000, /*70002308*/
+	0x0F12E59F, /*7000230A*/
+	0x0F12FF1C, /*7000230C*/
+	0x0F12E12F, /*7000230E*/
+	0x0F1251F9, /*70002310*/
+	0x0F120000, /*70002312*/
+	0x0F124778, /*70002314*/
+	0x0F1246C0, /*70002316*/
+	0x0F12F004, /*70002318*/
+	0x0F12E51F, /*7000231A*/
+	0x0F12A464, /*7000231C*/
+	0x0F120000, /*7000231E*/
+	0x0F124778, /*70002320*/
+	0x0F1246C0, /*70002322*/
+	0x0F12C000, /*70002324*/
+	0x0F12E59F, /*70002326*/
+	0x0F12FF1C, /*70002328*/
+	0x0F12E12F, /*7000232A*/
+	0x0F12A007, /*7000232C*/
+	0x0F120000, /*7000232E*/
+	0x0F126546, /*70002330*/
+	0x0F122062, /*70002332*/
+	0x0F123120, /*70002334*/
+	0x0F123220, /*70002336*/
+	0x0F123130, /*70002338*/
+	0x0F120030, /*7000233A*/
+	0x0F12E010, /*7000233C*/
+	0x0F120208, /*7000233E*/
+	0x0F120058, /*70002340*/
+	0x0F120000, /*70002342*/
+	/* End of Trap and Patch
+	Total Size 896 (0x0380)*/
+
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+
+
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+
+
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+
+
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,
+	0x002A0AE2,
+	0x0F12222E,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	0x002A049A,
+	0x0F1200FA,
+
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+
+	0x002AC202,
+	0x0F120700,
+
+	0x002AF260,
+	0x0F120001,
+
+	0x002AF414,
+	0x0F120030,
+                                                                       
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+
+	0x002AF700,
+	0x0F120040,
+
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+
+	0x0F120015,
+
+	0x0F120001,
+	0x0F120040,
+
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+                                                                                                             
+	0x002AF900,
+	0x0F120067,
+                                                                                                             
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+                                                                                                             
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+                                                                                                             
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+                                                                                
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+                                                                                
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+                                                                                
+	0x002AF4D6,
+	0x0F120090,
+
+	0x0F120000,
+
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+
+	0x002AF418,
+	0x0F120083,
+
+	0x002AF454,
+	0x0F120001,
+
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+
+	/* CFPN Canceller*/
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+                                                                        
+	0x002A10EE,
+	0x0F120000,
+
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+
+	0x002A1150,
+	0x0F1201F4,
+
+
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A,
+
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB,
+
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,
+	0x0F120000,
+	0x0F12A122,
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0,
+	0x0F1201E0,
+	0x002A0494,
+	0x0F120300,
+	0x0F120600,
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,
+
+	0x002A0E98,
+	0x0F1202A8,
+	0x002A0E9E,
+	0x0F120298,
+
+	/*1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001,
+	0x002A03F8,
+	0x0F12007F,
+
+	0xffff000a, /* Wait10mSec */
+
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0,
+	0x0F120000,
+
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001,
+	0x0F120001,
+	0x0F120000,
+
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz)*/
+	0x002A01D2,
+	0x0F121B58,
+	0x0F122EE0,
+	0x0F122EE0,
+
+	0x002A01DE,
+	0x0F120001,
+	0x0F120001,
+	0xffff0064, /* 100ms Delay */
+
+	/* Crop */
+	0x002A01FA,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120000,
+	0x0F120000,
+
+	/* Set Preview Config */
+	/* Preview Config 0 (640x480 VF 7.5~15fps)*/
+	0x002A0242,
+	0x0F120280,		/* REG_0TC_PCFG_usWidth               */
+	0x0F1201E0,		/* REG_0TC_PCFG_usHeight              */
+	0x0F120005,		/* REG_0TC_PCFG_Format                */
+	0x0F122EE0,		/* REG_0TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0,		/* REG_0TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052,		/* REG_0TC_PCFG_PVIMask               */
+	0x0F120001,		/* REG_0TC_PCFG_uClockInd             */
+	0x0F120000,		/* REG_0TC_PCFG_usFrTimeType          */
+	0x0F120000,		/* REG_0TC_PCFG_FrRateQualityType     */
+	0x0F120535,		/* REG_0TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12029A,		/* REG_0TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000,		/* REG_0TC_PCFG_sSaturation           */
+	0x0F120000,		/* REG_0TC_PCFG_sSharpBlur            */
+	0x0F120000,		/* REG_0TC_PCFG_sGlamour              */
+	0x0F120000,		/* REG_0TC_PCFG_sColorTemp            */
+	0x0F120000,		/* REG_0TC_PCFG_uDeviceGammaIndex     */
+	0x0F120000,		/* REG_0TC_PCFG_uPrevMirror           */
+	0x0F120000,		/* REG_0TC_PCFG_uCaptureMirror        */
+	0x0F120000,		/* REG_0TC_PCFG_uRotation             */
+
+	/* Preview Config 1 (640x480, VF 15 ~ 30fps)*/
+	0x002A0268,
+	0x0F120280,		/* REG_1TC_PCFG_usWidth               */
+	0x0F1201E0,		/* REG_1TC_PCFG_usHeight              */
+	0x0F120005,		/* REG_1TC_PCFG_Format                */
+	0x0F122EE0,		/* REG_1TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0,		/* REG_1TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052,		/* REG_1TC_PCFG_PVIMask               */
+	0x0F120001,		/* REG_1TC_PCFG_uClockInd             */
+	0x0F120000,		/* REG_1TC_PCFG_usFrTimeType          */
+	0x0F120000,		/* REG_1TC_PCFG_FrRateQualityType     */
+	0x0F12029A,		/* REG_1TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12014D,		/* REG_1TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000,		/* REG_1TC_PCFG_sSaturation           */
+	0x0F120000,		/* REG_1TC_PCFG_sSharpBlur            */
+	0x0F120000,		/* REG_1TC_PCFG_sGlamour              */
+	0x0F120000,		/* REG_1TC_PCFG_sColorTemp            */
+	0x0F120000,		/* REG_1TC_PCFG_uDeviceGammaIndex     */
+	0x0F120000,		/* REG_1TC_PCFG_uPrevMirror           */
+	0x0F120000,		/* REG_1TC_PCFG_uCaptureMirror        */
+	0x0F120000,		/* REG_1TC_PCFG_uRotation             */
+
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000,
+	0x002A03F2,
+	0x0F120001,
+	0x0F1200C3,
+	0x0F120001,
+
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000,
+	0x002A0220,
+	0x0F120001,
+	0x002A01F8,
+	0x0F120001,
+	0x002A021E,
+	0x0F120001,
+	0x002A01F0,
+	0x0F120001,
+	0x0F120001,
+
+	/* Capture Config 0 (1600x1200 FF 8fps) */
+	0x002A0302,
+	0x0F120000,
+	0x0F120640,
+	0x0F1204B0,
+	0x0F120005,
+	0x0F122EE0,
+	0x0F122EE0,
+	0x0F120052,
+	0x0F120001,
+	0x0F120002,
+	0x0F120002,
+	0x0F120535,
+	0x0F120535,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120403,
+	0x0F120304,
+	0x0F120101,
+	0x0F120101,
+	0x0F120302,
+	0x0F120203,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120101,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord*/
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+
+	/* param_start	wbt_AwbCcmCord*/
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+
+
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F12011a, /* 100 TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160,
+	0x0F120134,
+	0x0F1200FF,
+	0x0F1200D1,
+	0x0F1200B1,
+	0x0F12009D,
+	0x0F120096,
+	0x0F12009E,
+	0x0F1200B3,
+	0x0F1200D3,
+	0x0F1200FF,
+	0x0F120131,
+	0x0F120159,
+	0x0F12013C,
+	0x0F120107,
+	0x0F1200CD,
+	0x0F1200A1,
+	0x0F120080,
+	0x0F12006B,
+	0x0F120064,
+	0x0F12006C,
+	0x0F120080,
+	0x0F1200A1,
+	0x0F1200CD,
+	0x0F120106,
+	0x0F120139,
+	0x0F120116,
+	0x0F1200DC,
+	0x0F1200A2,
+	0x0F120073,
+	0x0F120051,
+	0x0F12003B,
+	0x0F120033,
+	0x0F12003B,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A2,
+	0x0F1200DD,
+	0x0F120115,
+	0x0F1200FA,
+	0x0F1200BF,
+	0x0F120085,
+	0x0F120055,
+	0x0F120031,
+	0x0F12001B,
+	0x0F120014,
+	0x0F12001A,
+	0x0F120031,
+	0x0F120055,
+	0x0F120085,
+	0x0F1200C0,
+	0x0F1200FB,
+	0x0F1200EA,
+	0x0F1200AF,
+	0x0F120074,
+	0x0F120045,
+	0x0F120020,
+	0x0F12000B,
+	0x0F120003,
+	0x0F12000A,
+	0x0F120020,
+	0x0F120046,
+	0x0F120076,
+	0x0F1200B1,
+	0x0F1200ED,
+	0x0F1200E6,
+	0x0F1200AA,
+	0x0F120071,
+	0x0F120041,
+	0x0F12001D,
+	0x0F120008,
+	0x0F120000,
+	0x0F120007,
+	0x0F12001E,
+	0x0F120044,
+	0x0F120074,
+	0x0F1200B0,
+	0x0F1200EC,
+	0x0F1200EF,
+	0x0F1200B3,
+	0x0F12007A,
+	0x0F12004A,
+	0x0F120026,
+	0x0F120011,
+	0x0F12000A,
+	0x0F120011,
+	0x0F120029,
+	0x0F12004F,
+	0x0F120080,
+	0x0F1200BC,
+	0x0F1200F8,
+	0x0F120105,
+	0x0F1200C9,
+	0x0F12008F,
+	0x0F120060,
+	0x0F12003C,
+	0x0F120026,
+	0x0F12001F,
+	0x0F120028,
+	0x0F120040,
+	0x0F120066,
+	0x0F120097,
+	0x0F1200D4,
+	0x0F120110,
+	0x0F120124,
+	0x0F1200EB,
+	0x0F1200B1,
+	0x0F120082,
+	0x0F12005F,
+	0x0F12004A,
+	0x0F120043,
+	0x0F12004C,
+	0x0F120064,
+	0x0F120089,
+	0x0F1200BA,
+	0x0F1200F8,
+	0x0F12012F,
+	0x0F120147,
+	0x0F120116,
+	0x0F1200DE,
+	0x0F1200AF,
+	0x0F12008E,
+	0x0F12007A,
+	0x0F120072,
+	0x0F12007A,
+	0x0F120091,
+	0x0F1200B6,
+	0x0F1200E8,
+	0x0F120121,
+	0x0F120150,
+	0x0F120170,
+	0x0F12013F,
+	0x0F120110,
+	0x0F1200E2,
+	0x0F1200C0,
+	0x0F1200AB,
+	0x0F1200A4,
+	0x0F1200AC,
+	0x0F1200C3,
+	0x0F1200E6,
+	0x0F120117,
+	0x0F120145,
+	0x0F120172,
+	0x0F120127,
+	0x0F120100,
+	0x0F1200CF,
+	0x0F1200A7,
+	0x0F12008D,
+	0x0F12007D,
+	0x0F120077,
+	0x0F12007A,
+	0x0F120087,
+	0x0F12009E,
+	0x0F1200C0,
+	0x0F1200EC,
+	0x0F12010F,
+	0x0F120108,
+	0x0F1200D8,
+	0x0F1200A5,
+	0x0F120080,
+	0x0F120066,
+	0x0F120056,
+	0x0F12004F,
+	0x0F120053,
+	0x0F120061,
+	0x0F120077,
+	0x0F120098,
+	0x0F1200C6,
+	0x0F1200F3,
+	0x0F1200E7,
+	0x0F1200B4,
+	0x0F120081,
+	0x0F12005C,
+	0x0F120041,
+	0x0F120030,
+	0x0F120029,
+	0x0F12002E,
+	0x0F12003D,
+	0x0F120055,
+	0x0F120076,
+	0x0F1200A5,
+	0x0F1200D4,
+	0x0F1200CF,
+	0x0F12009B,
+	0x0F12006A,
+	0x0F120043,
+	0x0F120027,
+	0x0F120016,
+	0x0F12000F,
+	0x0F120015,
+	0x0F120025,
+	0x0F12003E,
+	0x0F120061,
+	0x0F12008E,
+	0x0F1200BF,
+	0x0F1200C2,
+	0x0F12008E,
+	0x0F12005D,
+	0x0F120037,
+	0x0F12001A,
+	0x0F120009,
+	0x0F120002,
+	0x0F120007,
+	0x0F120018,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200BE,
+	0x0F12008A,
+	0x0F12005A,
+	0x0F120034,
+	0x0F120017,
+	0x0F120006,
+	0x0F120000,
+	0x0F120006,
+	0x0F120017,
+	0x0F120033,
+	0x0F120057,
+	0x0F120083,
+	0x0F1200B3,
+	0x0F1200C5,
+	0x0F120091,
+	0x0F120061,
+	0x0F12003B,
+	0x0F120020,
+	0x0F12000F,
+	0x0F120009,
+	0x0F120010,
+	0x0F120021,
+	0x0F12003D,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BE,
+	0x0F1200D7,
+	0x0F1200A2,
+	0x0F120072,
+	0x0F12004D,
+	0x0F120032,
+	0x0F120022,
+	0x0F12001D,
+	0x0F120024,
+	0x0F120035,
+	0x0F120050,
+	0x0F120073,
+	0x0F1200A0,
+	0x0F1200D2,
+	0x0F1200F0,
+	0x0F1200BE,
+	0x0F12008C,
+	0x0F120068,
+	0x0F12004F,
+	0x0F120040,
+	0x0F12003B,
+	0x0F120041,
+	0x0F120052,
+	0x0F12006C,
+	0x0F12008E,
+	0x0F1200BE,
+	0x0F1200ED,
+	0x0F12010C,
+	0x0F1200E1,
+	0x0F1200AF,
+	0x0F12008A,
+	0x0F120072,
+	0x0F120064,
+	0x0F12005F,
+	0x0F120065,
+	0x0F120074,
+	0x0F12008D,
+	0x0F1200B2,
+	0x0F1200E0,
+	0x0F12010A,
+	0x0F12012F,
+	0x0F120104,
+	0x0F1200D9,
+	0x0F1200B3,
+	0x0F120099,
+	0x0F12008B,
+	0x0F120086,
+	0x0F12008B,
+	0x0F12009B,
+	0x0F1200B5,
+	0x0F1200DA,
+	0x0F120101,
+	0x0F120128,
+	0x0F12012F,
+	0x0F120106,
+	0x0F1200D4,
+	0x0F1200AA,
+	0x0F12008E,
+	0x0F12007D,
+	0x0F120079,
+	0x0F120080,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200DC,
+	0x0F12010C,
+	0x0F120130,
+	0x0F120112,
+	0x0F1200E0,
+	0x0F1200AB,
+	0x0F120083,
+	0x0F120067,
+	0x0F120057,
+	0x0F120051,
+	0x0F120059,
+	0x0F12006B,
+	0x0F120089,
+	0x0F1200B2,
+	0x0F1200E5,
+	0x0F120114,
+	0x0F1200F2,
+	0x0F1200BD,
+	0x0F120088,
+	0x0F120061,
+	0x0F120044,
+	0x0F120031,
+	0x0F12002C,
+	0x0F120033,
+	0x0F120047,
+	0x0F120065,
+	0x0F12008C,
+	0x0F1200C0,
+	0x0F1200F3,
+	0x0F1200DB,
+	0x0F1200A5,
+	0x0F120071,
+	0x0F120049,
+	0x0F12002A,
+	0x0F120018,
+	0x0F120011,
+	0x0F120018,
+	0x0F12002C,
+	0x0F12004B,
+	0x0F120072,
+	0x0F1200A3,
+	0x0F1200D7,
+	0x0F1200CD,
+	0x0F120097,
+	0x0F120065,
+	0x0F12003C,
+	0x0F12001D,
+	0x0F12000A,
+	0x0F120003,
+	0x0F120009,
+	0x0F12001D,
+	0x0F12003B,
+	0x0F120063,
+	0x0F120092,
+	0x0F1200C4,
+	0x0F1200CA,
+	0x0F120094,
+	0x0F120062,
+	0x0F12003A,
+	0x0F12001A,
+	0x0F120007,
+	0x0F120000,
+	0x0F120006,
+	0x0F120018,
+	0x0F120036,
+	0x0F12005C,
+	0x0F12008A,
+	0x0F1200BC,
+	0x0F1200D1,
+	0x0F12009B,
+	0x0F120069,
+	0x0F120042,
+	0x0F120022,
+	0x0F12000F,
+	0x0F120008,
+	0x0F12000D,
+	0x0F12001F,
+	0x0F12003B,
+	0x0F120060,
+	0x0F12008D,
+	0x0F1200BF,
+	0x0F1200E3,
+	0x0F1200AC,
+	0x0F12007A,
+	0x0F120053,
+	0x0F120035,
+	0x0F120022,
+	0x0F12001B,
+	0x0F12001F,
+	0x0F120030,
+	0x0F12004B,
+	0x0F12006D,
+	0x0F12009C,
+	0x0F1200CE,
+	0x0F1200FE,
+	0x0F1200C9,
+	0x0F120095,
+	0x0F12006F,
+	0x0F120052,
+	0x0F120040,
+	0x0F120039,
+	0x0F12003D,
+	0x0F12004B,
+	0x0F120063,
+	0x0F120086,
+	0x0F1200B5,
+	0x0F1200E6,
+	0x0F12011B,
+	0x0F1200ED,
+	0x0F1200BA,
+	0x0F120092,
+	0x0F120076,
+	0x0F120065,
+	0x0F12005D,
+	0x0F120060,
+	0x0F12006D,
+	0x0F120084,
+	0x0F1200A8,
+	0x0F1200D6,
+	0x0F120101,
+	0x0F120140,
+	0x0F120112,
+	0x0F1200E5,
+	0x0F1200BD,
+	0x0F12009E,
+	0x0F12008C,
+	0x0F120085,
+	0x0F120087,
+	0x0F120094,
+	0x0F1200AC,
+	0x0F1200D0,
+	0x0F1200F8,
+	0x0F120123,
+	0x0F1200F2,
+	0x0F1200D1,
+	0x0F1200A7,
+	0x0F120087,
+	0x0F120073,
+	0x0F120067,
+	0x0F120064,
+	0x0F12006B,
+	0x0F12007C,
+	0x0F120094,
+	0x0F1200B7,
+	0x0F1200E1,
+	0x0F1200FF,
+	0x0F1200D6,
+	0x0F1200AE,
+	0x0F120085,
+	0x0F120068,
+	0x0F120054,
+	0x0F120048,
+	0x0F120045,
+	0x0F12004B,
+	0x0F12005B,
+	0x0F120073,
+	0x0F120093,
+	0x0F1200BF,
+	0x0F1200E9,
+	0x0F1200B8,
+	0x0F12008E,
+	0x0F120066,
+	0x0F120049,
+	0x0F120035,
+	0x0F120028,
+	0x0F120025,
+	0x0F12002B,
+	0x0F12003B,
+	0x0F120053,
+	0x0F120072,
+	0x0F12009D,
+	0x0F1200C8,
+	0x0F1200A2,
+	0x0F120078,
+	0x0F120051,
+	0x0F120034,
+	0x0F12001F,
+	0x0F120012,
+	0x0F12000E,
+	0x0F120014,
+	0x0F120024,
+	0x0F12003B,
+	0x0F12005B,
+	0x0F120083,
+	0x0F1200AD,
+	0x0F120095,
+	0x0F12006C,
+	0x0F120046,
+	0x0F12002A,
+	0x0F120014,
+	0x0F120007,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F12002D,
+	0x0F12004C,
+	0x0F120072,
+	0x0F12009B,
+	0x0F120093,
+	0x0F12006A,
+	0x0F120045,
+	0x0F120028,
+	0x0F120013,
+	0x0F120005,
+	0x0F120000,
+	0x0F120004,
+	0x0F120012,
+	0x0F120028,
+	0x0F120045,
+	0x0F12006A,
+	0x0F120093,
+	0x0F12009B,
+	0x0F120071,
+	0x0F12004C,
+	0x0F120030,
+	0x0F12001A,
+	0x0F12000C,
+	0x0F120007,
+	0x0F12000B,
+	0x0F120018,
+	0x0F12002C,
+	0x0F120048,
+	0x0F12006D,
+	0x0F120097,
+	0x0F1200AE,
+	0x0F120083,
+	0x0F12005C,
+	0x0F120040,
+	0x0F12002B,
+	0x0F12001E,
+	0x0F120018,
+	0x0F12001C,
+	0x0F120027,
+	0x0F12003A,
+	0x0F120055,
+	0x0F12007B,
+	0x0F1200A6,
+	0x0F1200CA,
+	0x0F12009E,
+	0x0F120076,
+	0x0F120059,
+	0x0F120046,
+	0x0F120039,
+	0x0F120033,
+	0x0F120036,
+	0x0F120040,
+	0x0F120052,
+	0x0F12006C,
+	0x0F120094,
+	0x0F1200BF,
+	0x0F1200EB,
+	0x0F1200C3,
+	0x0F120099,
+	0x0F12007A,
+	0x0F120066,
+	0x0F12005A,
+	0x0F120054,
+	0x0F120056,
+	0x0F12005F,
+	0x0F120071,
+	0x0F12008D,
+	0x0F1200B6,
+	0x0F1200DE,
+	0x0F12010D,
+	0x0F1200E7,
+	0x0F1200C1,
+	0x0F1200A0,
+	0x0F12008A,
+	0x0F12007C,
+	0x0F120076,
+	0x0F120078,
+	0x0F120081,
+	0x0F120093,
+	0x0F1200B1,
+	0x0F1200D5,
+	0x0F1200FD,
+
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120016,
+	0x0F120055,
+	0x0F1200E6,
+	0x0F120141,
+	0x0F120188,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Outdoor Gray Zone */
+	0x0F12025E,
+	0x0F120282,
+	0x0F120240,
+	0x0F120298,
+	0x0F12022A,
+	0x0F12029A,
+	0x0F12021A,
+	0x0F12029A,
+	0x0F120206,
+	0x0F120298,
+	0x0F1201FE,
+	0x0F12028C,
+	0x0F1201FA,
+	0x0F120278,
+	0x0F1201F8,
+	0x0F120266,
+	0x0F120214,
+	0x0F120238,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+
+
+	/* param_WRITE 70000CC6 */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+
+
+	/* 42param_end*/
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+
+
+	/* Duks add*/
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120020, /* awbb_GridCorr_R_0__4_ */
+	0x0F120060, /* awbb_GridCorr_R_0__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120020, /* awbb_GridCorr_R_1__4_ */
+	0x0F120060, /* awbb_GridCorr_R_1__5_ */
+
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120020, /* awbb_GridCorr_R_2__4_ */
+	0x0F120060, /* awbb_GridCorr_R_2__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F121021, /* awbb_GridConst_2_0  */
+	0x0F12107E, /* awbb_GridConst_2_1  */
+	0x0F12113E, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+
+	/* awbb_ChromaClassifyEn, default : enable*/
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+
+	/*  param_start */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000,
+
+	/* param_start SARR_uNormBrInDoor*/
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+	/* param_start SARR_uNormBrOutDoor */
+	0x0F12000A,
+	0x0F120019,
+	0x0F12007D,
+	0x0F1202BC,
+	0x0F1207D0,
+
+
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+
+
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F12FFFE, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120018, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120016, /* 14 Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120072, /* 64 Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12200A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120009, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F12000E, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120012, /* 0C Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006E, /* 60 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F12000E, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12006C, /* 5A Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122028, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122028, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F122000, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120014, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000F, /* 06 Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120068, /* 50 Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F126400, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001,
+
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+	/* END of Initial*/
+};
+
+/* Set-data based on SKT VT standard ,when using 3G network
+* 8fps
+*/
+static const u32 s5k5bafx_vt_common[] =
+{
+	/* VT-Call */
+	
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* Delay */
+	
+	
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0,	/* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E,	/* setot_usSetRomWaitStateThreshold4KHz */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	
+	0x0F120015,
+	
+	
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting   sunkyu start */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003C, /* 3A TVAR_ae_BrAve */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+	
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,/*uMaxExp1         */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,/*uMaxExp2         */
+	0x0F120000,
+	0x0F12A122,/*uMaxExp3         */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,/*uMaxExp4         */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0,/*lt_uMaxAnGain0   */
+	0x0F1201E0,/*lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300,/*lt_uMaxAnGain1   */
+	0x0F120E00,/*lt_uMaxAnGain2   */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F,/*ae_StatMode      */
+	
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202B0,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120290,
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12007F, /* REG_TC_DBG_AutoAlgEnBits             default : 007F */
+	
+	
+	0xffff000a, /* Wait10mSec */
+	
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+	
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+	
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,
+	0x0F121B58, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+	
+	
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* Delay 100ms                   */
+	
+	
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+	
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight              */
+	0x0F120005, /* REG_0TC_PCFG_Format                */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_PCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex     */
+	0x0F120001, /* REG_0TC_PCFG_uPrevMirror           */
+	0x0F120001, /* REG_0TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_0TC_PCFG_uRotation             */
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight              */
+	0x0F120005, /* REG_1TC_PCFG_Format                */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd             */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType          */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex     */
+	0x0F120001, /* REG_1TC_PCFG_uPrevMirror           */
+	0x0F120001, /* REG_1TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_1TC_PCFG_uRotation             */
+	
+	
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+	
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig     */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange  */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync        */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged    */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview        */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+	
+	
+	
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000, /* msm_uOffsetNoBin[0][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[0][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[1][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[1][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[2][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[2][1]    */
+	0x0F120000, /* msm_uOffsetNoBin[3][0]    */
+	0x0F120000, /* msm_uOffsetNoBin[3][1]    */
+	
+	0x002A0798,
+	0x0F120000, /* msm_uOffsetBin[0][0]      */
+	0x0F120000, /* msm_uOffsetBin[0][1]      */
+	0x0F120000, /* msm_uOffsetBin[1][0]      */
+	0x0F120000, /* msm_uOffsetBin[1][1]      */
+	
+	0x002A07C0,
+	0x0F120004, /* msm_NonLinearOfsOutput[2] */
+	0x0F120004, /* msm_NonLinearOfsOutput[3] */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120100, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120001, /* ae_WeightTbl_16_7_ */
+	0x0F120100, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120001, /* ae_WeightTbl_16_11 */
+	0x0F120100, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120001, /* ae_WeightTbl_16_15 */
+	0x0F120100, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120001, /* ae_WeightTbl_16_19 */
+	0x0F120100, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120001, /* ae_WeightTbl_16_23 */
+	0x0F120100, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120001, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3, /* TVAR_ash_AwbAshCord_0_ */
+	0x0F1200E5, /* TVAR_ash_AwbAshCord_1_ */
+	0x0F120120, /* TVAR_ash_AwbAshCord_2_ */
+	0x0F120136, /* TVAR_ash_AwbAshCord_3_ */
+	0x0F120180, /* TVAR_ash_AwbAshCord_4_ */
+	0x0F1201B0, /* TVAR_ash_AwbAshCord_5_ */
+	0x0F120200, /* TVAR_ash_AwbAshCord_6_ */
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3, /* SARR_AwbCcmCord_0_	Hor   */
+	0x0F1200E5, /* SARR_AwbCcmCord_1_	IncaA */
+	0x0F120120, /* SARR_AwbCcmCord_2_	WW    */
+	0x0F120136, /* SARR_AwbCcmCord_3_	CW    */
+	0x0F120180, /* SARR_AwbCcmCord_4_	D50   */
+	0x0F120190, /* SARR_AwbCcmCord_5_	D65   */
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000, /* SARR_IllumType_0_      */
+	0x0F120009, /* SARR_IllumType_1_      */
+	0x0F120018, /* SARR_IllumType_2_      */
+	0x0F120032, /* SARR_IllumType_3_      */
+	0x0F12004A, /* SARR_IllumType_4_      */
+	0x0F120051, /* SARR_IllumType_5_      */
+	0x0F120056, /* SARR_IllumType_6_      */
+	0x0F12010C, /* SARe_2_R_IllumTypeF_0_ */
+	0x0F12010C, /* SARe_3_R_IllumTypeF_1_ */
+	0x0F120109, /* SARe_4_R_IllumTypeF_2_ */
+	0x0F120105, /* SARe_5_R_IllumTypeF_3_ */
+	0x0F120102, /* SARe_6_R_IllumTypeF_4_ */
+	0x0F1200FB, /* SARR_IllumTypeF_5_     */
+	0x0F1200F8, /* SARR_IllumTypeF_6_     */
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388, /* TVAR_ash_pGAS */
+	0x0F127000, /* TVAR_ash_pGAS */
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[0][15] */
+	
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[1][15] */
+	
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* SARR_usGammaLutRGBIndoor[2][15] */
+	
+	
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone	       */
+	0x0F120000, /* awbb_LowBr0_NBzone       */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv       */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F120264,
+	0x0F120279,
+	0x0F120250,
+	0x0F120287,
+	0x0F120244,
+	0x0F120287,
+	0x0F120235,
+	0x0F120289,
+	0x0F120225,
+	0x0F120287,
+	0x0F120213,
+	0x0F120286,
+	0x0F120202,
+	0x0F12027A,
+	0x0F1201F3,
+	0x0F120272,
+	0x0F1201E9,
+	0x0F120269,
+	0x0F1201E2,
+	0x0F120263,
+	0x0F1201E0,
+	0x0F12025A,
+	0x0F1201E1,
+	0x0F120256,
+	0x0F1201EE,
+	0x0F120251,
+	0x0F1201F8,
+	0x0F12024A,
+	0x0F12020D,
+	0x0F120231,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120011,
+	0x0F120000,
+	0x0F1201FF,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F120000, /* awbb_GridCorr_R_0__0_ */
+	0x0F120000, /* awbb_GridCorr_R_0__1_ */
+	0x0F120040, /* awbb_GridCorr_R_0__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_0__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_0__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_0__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_R_1__0_ */
+	0x0F120000, /* awbb_GridCorr_R_1__1_ */
+	0x0F120040, /* awbb_GridCorr_R_1__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_1__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_1__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_1__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_R_2__0_ */
+	0x0F120000, /* awbb_GridCorr_R_2__1_ */
+	0x0F120040, /* awbb_GridCorr_R_2__2_ */
+	0x0F12FFF8, /* awbb_GridCorr_R_2__3_ */
+	0x0F12FFE0, /* awbb_GridCorr_R_2__4_ */
+	0x0F12FFD0, /* awbb_GridCorr_R_2__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120040, /* awbb_GridCorr_B_0__2_ */
+	0x0F120000, /* awbb_GridCorr_B_0__3_ */
+	0x0F120028, /* awbb_GridCorr_B_0__4_ */
+	0x0F120050, /* awbb_GridCorr_B_0__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120040, /* awbb_GridCorr_B_1__2_ */
+	0x0F120000, /* awbb_GridCorr_B_1__3_ */
+	0x0F120028, /* awbb_GridCorr_B_1__4_ */
+	0x0F120050, /* awbb_GridCorr_B_1__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120040, /* awbb_GridCorr_B_2__2_ */
+	0x0F120000, /* awbb_GridCorr_B_2__3_ */
+	0x0F120028, /* awbb_GridCorr_B_2__4_ */
+	0x0F120050, /* awbb_GridCorr_B_2__5_ */
+	
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F120FD7, /* awbb_GridConst_2_0  */
+	0x0F1210C5, /* awbb_GridConst_2_1  */
+	0x0F12116A, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+	
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+	
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F1201E5, /* 01D6 01E1 01FB */
+	0x0F12FFBF, /* FFC9 FFC4 FF9C */
+	0x0F12FFF4, /* FFFB FFF8 FFFF */
+	0x0F1200EE, /* 010A 0101 0137 */
+	0x0F12019B, /* 0177 014C 0113 */
+	0x0F12FF1E, /* FF24 FF55 FF6F */
+	0x0F12FF38, /* FF9C FF5B FF21 */
+	0x0F12026D, /* 0230 0205 0194 */
+	0x0F12FEDD, /* FEB1 FF17 FF69 */
+	0x0F12FF00, /* FEFF FEFE FF14 */
+	0x0F1201B8, /* 01B7 01B6 0158 */
+	0x0F120109, /* 0108 0107 015D */
+	0x0F12FFCC, /* FFEB FFDB FFF2 */
+	0x0F12FFA4, /* FFB5 FFDB FFF1 */
+	0x0F120212, /* 01E4 01D1 0179 */
+	0x0F120136, /* 011E 0163 017C */
+	0x0F12FFA5, /* FFAD FF9E FFC3 */
+	0x0F1201CF, /* 01E3 01B3 0197 */
+	
+	0x0F1201E5, /* 01D6 01E1 01FB */
+	0x0F12FFBF, /* FFC9 FFC4 FF9C */
+	0x0F12FFF4, /* FFFB FFF8 FFFF */
+	0x0F1200EE, /* 010A 0101 0137 */
+	0x0F12019B, /* 0177 014C 0113 */
+	0x0F12FF1E, /* FF24 FF55 FF6F */
+	0x0F12FF38, /* FF9C FF5B FF21 */
+	0x0F12026D, /* 0230 0205 0194 */
+	0x0F12FEDD, /* FEB1 FF17 FF69 */
+	0x0F12FF00, /* FEFF FEFE FF14 */
+	0x0F1201B8, /* 01B7 01B6 0158 */
+	0x0F120109, /* 0108 0107 015D */
+	0x0F12FFCC, /* FFEB FFDB FFF2 */
+	0x0F12FFA4, /* FFB5 FFDB FFF1 */
+	0x0F120212, /* 01E4 01D1 0179 */
+	0x0F120136, /* 011E 0163 017C */
+	0x0F12FFA5, /* FFAD FF9E FFC3 */
+	0x0F1201CF, /* 01E3 01B3 0197 */
+	
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+	
+	0x0F1201FB, /* 01FB 01FB */
+	0x0F12FFA9, /* FFA9 FF9C */
+	0x0F12FFEA, /* FFEA FFFF */
+	0x0F12013C, /* 0134 0137 */
+	0x0F120140, /* 0133 0113 */
+	0x0F12FF53, /* FF5D FF6F */
+	0x0F12FE7A, /* FE7A FF21 */
+	0x0F12017D, /* 017D 0194 */
+	0x0F12FEED, /* FEED FF69 */
+	0x0F12FF39, /* FF39 FF14 */
+	0x0F1201D6, /* 01D6 0158 */
+	0x0F1200C4, /* 00C4 015D */
+	0x0F12FFC0, /* FFCE FFF2 */
+	0x0F12FFBF, /* FFCD FFF1 */
+	0x0F1201CD, /* 01B7 0179 */
+	0x0F120182, /* 0176 017C */
+	0x0F12FF91, /* FFBD FFC3 */
+	0x0F1201AA, /* 0191 0197 */
+	
+	0x0F1201D2, /* 01C5 01F9 020A */
+	0x0F12FFC2, /* FF9F FFBC FFB2 */
+	0x0F12FFFC, /* FFE5 FFF2 FFEB */
+	0x0F1200E8, /* 00E2 00FA 0134 */
+	0x0F120126, /* 010E 0157 0133 */
+	0x0F12FF83, /* FF62 FF81 FF5D */
+	0x0F12FE7A, /* FF03 FE7A FEFD */
+	0x0F12017D, /* 01D0 017D 01BF */
+	0x0F12FEED, /* FF3E FEED FF2A */
+	0x0F12FF1C, /* FF00 FF8A FF39 */
+	0x0F120194, /* 01A6 01F9 01D6 */
+	0x0F12011F, /* 00BB 005B 00C4 */
+	0x0F12FFEA, /* FFBF FFCA FFCE */
+	0x0F12FFDE, /* FFDD FFA3 FFCD */
+	0x0F1201E9, /* 01F6 01DA 01B7 */
+	0x0F120178, /* 00CB 0108 0176 */
+	0x0F12FFBF, /* FF94 FFB3 FFBD */
+	0x0F120193, /* 019E 01DD 0191 */
+	
+	0x0F1201D2, /* 01F9 020A 01D0   R */
+	0x0F12FFC2, /* FFBC FFB2 FFB4     */
+	0x0F12FFFC, /* FFF2 FFEB 000C     */
+	0x0F1200E8, /* 00FA 011E 0122   Y */
+	0x0F120126, /* 0157 011D 0103     */
+	0x0F12FF83, /* FF81 FF86 FF9B     */
+	0x0F12FE7A, /* FE7A FEFD FF33   G */
+	0x0F12017D, /* 017D 01BF 01C5     */
+	0x0F12FEED, /* FEED FF2A FF33     */
+	0x0F12FF1C, /* FF8A FF38 FF16   C */
+	0x0F120194, /* 01F9 01D5 015A     */
+	0x0F12011F, /* 005B 00C3 015F     */
+	0x0F12FFEA, /* FFCA FFCF FFE0   B */
+	0x0F12FFDE, /* FFA3 FFCE FFDF     */
+	0x0F1201E9, /* 01DA 01B8 0197     */
+	0x0F120178, /* 0108 0178 0178   M */
+	0x0F12FFBF, /* FFB3 FFBF FFBF     */
+	0x0F120193, /* 01DD 0193 0193     */
+	
+	0x0F1201F1, /* outdoor CCM */
+	0x0F12FFB0,
+	0x0F12FFEF,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FF4E,
+	0x0F120164,
+	0x0F12011D,
+	0x0F12FFEA,
+	0x0F12FFDE,
+	0x0F1201E9,
+	0x0F120178,
+	0x0F12FFBF,
+	0x0F120193,
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /* afit_bUseNoiseInd 0 : NB 1: Noise Index */
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+	
+	
+	/* Set AFIT */
+	/* AFIT Start Address */
+	0x002A0814,
+	0x0F12082C, /* TVAR_afit_pBaseVals */
+	0x0F127000, /* TVAR_afit_pBaseVals */
+	
+	/* param_start	TVAR_afit_pBaseVals */
+	0x002A082C,
+	0x0F120003, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F12FFFE, /* SATURATION                                                               */
+	0x0F12FFE2, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120035, /* RGB2YUV_iYOffset                                                         */
+	
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120114, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120008, /* RGB2YUV_iYOffset                                                         */
+	
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F120000, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                    */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x0F120000, /* BRIGHTNESS                                                               */
+	0x0F12000A, /* CONTRAST                                                                 */
+	0x0F120000, /* SATURATION                                                               */
+	0x0F120000, /* SHARP_BLUR                                                               */
+	0x0F120000, /* GLAMOUR                                                                  */
+	0x0F1203FF, /* Disparity_iSatSat                                                        */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                              */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                                 */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                             */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                                 */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                                */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                  */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                                 */
+	0x0F1203FF, /* Denoise1_iSatSat                                                         */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                   */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                  */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                    */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                   */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                  */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                                */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                               */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                                    */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                                */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                                   */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                               */
+	0x0F120106, /* DSMix1_iRGBOffset                                                        */
+	0x0F12006F, /* DSMix1_iDemClamp                                                         */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"     bin: desparity low  */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"  bin: desparity high */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"       */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin           */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                      */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                        */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"              */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                      */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                       */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                                */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                       */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                            */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                              */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                        */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                       */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"  ]negati fine        */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"     ]low fine           */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"   ]high fine          */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"      ]high low thres     */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                        */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                       */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                     */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                       */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                       */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                       */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                             */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                               */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                             */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                                 */
+	0x0F120140, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                                 */
+	0x0F120000, /* RGB2YUV_iYOffset                                                         */
+	
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                          */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                         */
+	0x0F120800, /* Denoise1_sensor_width                             */
+	0x0F120600, /* Denoise1_sensor_height                            */
+	0x0F120000, /* Denoise1_start_x                                  */
+	0x0F120000, /* Denoise1_start_y                                  */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "          */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "        */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  "  */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "           */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "         */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "      */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "     */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh" */
+	0x0F120000, /*  Demosaic4_iBypassSelect                          */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* VT-Call END of Initial */
+};
+
+
+/* Set-data based on Samsung Reliabilty Group standard 
+* ,when using WIFI. 15fps
+*/
+static const u32 s5k5bafx_vt_wifi_common[] =
+{
+	/* Wifi_VT */
+	
+	0xFCFCD000,
+	
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* Delay */
+	
+	
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	
+	0x0F120015,
+	
+	
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000, /* senHal_bUseAnalogBinning */
+	0x0F120000, /* senHal_bUseAnalogVerAvg  */
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F120034, /* 3A TVAR_ae_BrAve */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+	
+	
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A,/* uMaxExp1         */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214,/* uMaxExp2         */
+	0x0F120000,
+	0x0F12A122,/* uMaxExp3         */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424,/* uMaxExp4         */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201B0,/* lt_uMaxAnGain0   */
+	0x0F1201C0,/* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F1202B0,/* lt_uMaxAnGain1   */
+	0x0F120B00,/* lt_uMaxAnGain2   */
+	0x0f120100,/* lt_uMaxDigGain   */
+	0x002A0F52,
+	0x0F12000F,/* ae_StatMode */
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12007F, /* REG_TC_DBG_AutoAlgEnBits          default : 007F  */
+	
+	
+	
+	0xffff000a, /* Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+	
+	/* Parallel or MIP Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+	
+	/* System Clock 1 (System : 28Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F121B58, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+	
+	
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* Delay 100msec                 */
+	
+	
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+	
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (1600x1200 fixed 15fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight              */
+	0x0F120005, /* REG_0TC_PCFG_Format                */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType          */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12029A, /* REG_0TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex     */
+	0x0F120000, /* REG_0TC_PCFG_uPrevMirror           */
+	0x0F120000, /* REG_0TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_0TC_PCFG_uRotation             */
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth               */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight              */
+	0x0F120005, /* REG_1TC_PCFG_Format                */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask               */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd             */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType          */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10 */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation           */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur            */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour              */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp            */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex     */
+	0x0F120000, /* REG_1TC_PCFG_uPrevMirror           */
+	0x0F120000, /* REG_1TC_PCFG_uCaptureMirror        */
+	0x0F120000, /* REG_1TC_PCFG_uRotation             */
+	
+	
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+	
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig     */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange  */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync        */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged    */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview        */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 15fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F12029A, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F12029A, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+	
+	
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000, /* msm_uOffsetNoBin[0][0] */
+	0x0F120000, /* msm_uOffsetNoBin[0][1] */
+	0x0F120000, /* msm_uOffsetNoBin[1][0] */
+	0x0F120000, /* msm_uOffsetNoBin[1][1] */
+	0x0F120000, /* msm_uOffsetNoBin[2][0] */
+	0x0F120000, /* msm_uOffsetNoBin[2][1] */
+	0x0F120000, /* msm_uOffsetNoBin[3][0] */
+	0x0F120000, /* msm_uOffsetNoBin[3][1] */
+	
+	0x002A0798,
+	0x0F120000, /* msm_uOffsetBin[0][0] */
+	0x0F120000, /* msm_uOffsetBin[0][1] */
+	0x0F120000, /* msm_uOffsetBin[1][0] */
+	0x0F120000, /* msm_uOffsetBin[1][1] */
+	
+	0x002A07C0,
+	0x0F120004, /* msm_NonLinearOfsOutput[2] */
+	0x0F120004, /* msm_NonLinearOfsOutput[3] */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R */
+	0x0F120400, /* awbb_GainsInit_1_:G */
+	0x0F1205F0, /* awbb_GainsInit_2_:B */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start */
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3, /* TVAR_ash_AwbAshCord_0_ */
+	0x0F1200E5, /* TVAR_ash_AwbAshCord_1_ */
+	0x0F120120, /* TVAR_ash_AwbAshCord_2_ */
+	0x0F120136, /* TVAR_ash_AwbAshCord_3_ */
+	0x0F120180, /* TVAR_ash_AwbAshCord_4_ */
+	0x0F1201B0, /* TVAR_ash_AwbAshCord_5_ */
+	0x0F120200, /* TVAR_ash_AwbAshCord_6_ */
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3, /* SARR_AwbCcmCord_0_	Hor   */
+	0x0F1200E5, /* SARR_AwbCcmCord_1_	IncaA */
+	0x0F120100, /* SARR_AwbCcmCord_2_	WW    */
+	0x0F120116, /* SARR_AwbCcmCord_3_	CW    */
+	0x0F120150, /* SARR_AwbCcmCord_4_	D50   */
+	0x0F120198, /* SARR_AwbCcmCord_5_	D65   */
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000, /* SARR_IllumType_0_      */
+	0x0F120009, /* SARR_IllumType_1_      */
+	0x0F120018, /* SARR_IllumType_2_      */
+	0x0F120032, /* SARR_IllumType_3_      */
+	0x0F12004A, /* SARR_IllumType_4_      */
+	0x0F120051, /* SARR_IllumType_5_      */
+	0x0F120056, /* SARR_IllumType_6_      */
+	0x0F12010C, /* SARe_2_R_IllumTypeF_0_ */
+	0x0F12010C, /* SARe_3_R_IllumTypeF_1_ */
+	0x0F120109, /* SARe_4_R_IllumTypeF_2_ */
+	0x0F120105, /* SARe_5_R_IllumTypeF_3_ */
+	0x0F120102, /* SARe_6_R_IllumTypeF_4_ */
+	0x0F1200FB, /* SARR_IllumTypeF_5_     */
+	0x0F1200F8, /* SARR_IllumTypeF_6_     */
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_0_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_ */
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_ */
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388, /* TVAR_ash_pGAS */
+	0x0F127000, /* TVAR_ash_pGAS */
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F1201CC, /* TVAR_ash_pGAS[0]   */
+	0x0F120178, /* TVAR_ash_pGAS[1]   */
+	0x0F12013B, /* TVAR_ash_pGAS[2]   */
+	0x0F120108, /* TVAR_ash_pGAS[3]   */
+	0x0F1200E4, /* TVAR_ash_pGAS[4]   */
+	0x0F1200CC, /* TVAR_ash_pGAS[5]   */
+	0x0F1200C5, /* TVAR_ash_pGAS[6]   */
+	0x0F1200CF, /* TVAR_ash_pGAS[7]   */
+	0x0F1200E8, /* TVAR_ash_pGAS[8]   */
+	0x0F120111, /* TVAR_ash_pGAS[9]   */
+	0x0F120142, /* TVAR_ash_pGAS[10]  */
+	0x0F120183, /* TVAR_ash_pGAS[11]  */
+	0x0F1201D9, /* TVAR_ash_pGAS[12]  */
+	0x0F120184, /* TVAR_ash_pGAS[13]  */
+	0x0F120142, /* TVAR_ash_pGAS[14]  */
+	0x0F120101, /* TVAR_ash_pGAS[15]  */
+	0x0F1200CF, /* TVAR_ash_pGAS[16]  */
+	0x0F1200A7, /* TVAR_ash_pGAS[17]  */
+	0x0F120090, /* TVAR_ash_pGAS[18]  */
+	0x0F120088, /* TVAR_ash_pGAS[19]  */
+	0x0F120092, /* TVAR_ash_pGAS[20]  */
+	0x0F1200AC, /* TVAR_ash_pGAS[21]  */
+	0x0F1200D5, /* TVAR_ash_pGAS[22]  */
+	0x0F12010D, /* TVAR_ash_pGAS[23]  */
+	0x0F12014E, /* TVAR_ash_pGAS[24]  */
+	0x0F120190, /* TVAR_ash_pGAS[25]  */
+	0x0F12014E, /* TVAR_ash_pGAS[26]  */
+	0x0F12010D, /* TVAR_ash_pGAS[27]  */
+	0x0F1200CA, /* TVAR_ash_pGAS[28]  */
+	0x0F120094, /* TVAR_ash_pGAS[29]  */
+	0x0F12006D, /* TVAR_ash_pGAS[30]  */
+	0x0F120054, /* TVAR_ash_pGAS[31]  */
+	0x0F12004E, /* TVAR_ash_pGAS[32]  */
+	0x0F120058, /* TVAR_ash_pGAS[33]  */
+	0x0F120073, /* TVAR_ash_pGAS[34]  */
+	0x0F12009D, /* TVAR_ash_pGAS[35]  */
+	0x0F1200D5, /* TVAR_ash_pGAS[36]  */
+	0x0F12011D, /* TVAR_ash_pGAS[37]  */
+	0x0F12015A, /* TVAR_ash_pGAS[38]  */
+	0x0F120129, /* TVAR_ash_pGAS[39]  */
+	0x0F1200E5, /* TVAR_ash_pGAS[40]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[41]  */
+	0x0F12006B, /* TVAR_ash_pGAS[42]  */
+	0x0F120042, /* TVAR_ash_pGAS[43]  */
+	0x0F12002A, /* TVAR_ash_pGAS[44]  */
+	0x0F120022, /* TVAR_ash_pGAS[45]  */
+	0x0F12002D, /* TVAR_ash_pGAS[46]  */
+	0x0F120049, /* TVAR_ash_pGAS[47]  */
+	0x0F120075, /* TVAR_ash_pGAS[48]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[49]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[50]  */
+	0x0F12013A, /* TVAR_ash_pGAS[51]  */
+	0x0F120113, /* TVAR_ash_pGAS[52]  */
+	0x0F1200CE, /* TVAR_ash_pGAS[53]  */
+	0x0F120088, /* TVAR_ash_pGAS[54]  */
+	0x0F120052, /* TVAR_ash_pGAS[55]  */
+	0x0F12002A, /* TVAR_ash_pGAS[56]  */
+	0x0F120010, /* TVAR_ash_pGAS[57]  */
+	0x0F120009, /* TVAR_ash_pGAS[58]  */
+	0x0F120015, /* TVAR_ash_pGAS[59]  */
+	0x0F120032, /* TVAR_ash_pGAS[60]  */
+	0x0F12005E, /* TVAR_ash_pGAS[61]  */
+	0x0F120098, /* TVAR_ash_pGAS[62]  */
+	0x0F1200E3, /* TVAR_ash_pGAS[63]  */
+	0x0F120128, /* TVAR_ash_pGAS[64]  */
+	0x0F12010A, /* TVAR_ash_pGAS[65]  */
+	0x0F1200C4, /* TVAR_ash_pGAS[66]  */
+	0x0F120080, /* TVAR_ash_pGAS[67]  */
+	0x0F120049, /* TVAR_ash_pGAS[68]  */
+	0x0F120020, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F12000D, /* TVAR_ash_pGAS[72]  */
+	0x0F12002A, /* TVAR_ash_pGAS[73]  */
+	0x0F120058, /* TVAR_ash_pGAS[74]  */
+	0x0F120093, /* TVAR_ash_pGAS[75]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[76]  */
+	0x0F120123, /* TVAR_ash_pGAS[77]  */
+	0x0F12010D, /* TVAR_ash_pGAS[78]  */
+	0x0F1200CA, /* TVAR_ash_pGAS[79]  */
+	0x0F120085, /* TVAR_ash_pGAS[80]  */
+	0x0F12004E, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F12000E, /* TVAR_ash_pGAS[83]  */
+	0x0F120007, /* TVAR_ash_pGAS[84]  */
+	0x0F120014, /* TVAR_ash_pGAS[85]  */
+	0x0F120032, /* TVAR_ash_pGAS[86]  */
+	0x0F120061, /* TVAR_ash_pGAS[87]  */
+	0x0F12009C, /* TVAR_ash_pGAS[88]  */
+	0x0F1200E8, /* TVAR_ash_pGAS[89]  */
+	0x0F12012F, /* TVAR_ash_pGAS[90]  */
+	0x0F120121, /* TVAR_ash_pGAS[91]  */
+	0x0F1200DE, /* TVAR_ash_pGAS[92]  */
+	0x0F12009A, /* TVAR_ash_pGAS[93]  */
+	0x0F120063, /* TVAR_ash_pGAS[94]  */
+	0x0F12003B, /* TVAR_ash_pGAS[95]  */
+	0x0F120024, /* TVAR_ash_pGAS[96]  */
+	0x0F12001D, /* TVAR_ash_pGAS[97]  */
+	0x0F12002B, /* TVAR_ash_pGAS[98]  */
+	0x0F120049, /* TVAR_ash_pGAS[99]  */
+	0x0F120079, /* TVAR_ash_pGAS[100] */
+	0x0F1200B5, /* TVAR_ash_pGAS[101] */
+	0x0F120100, /* TVAR_ash_pGAS[102] */
+	0x0F120145, /* TVAR_ash_pGAS[103] */
+	0x0F12013F, /* TVAR_ash_pGAS[104] */
+	0x0F120101, /* TVAR_ash_pGAS[105] */
+	0x0F1200BE, /* TVAR_ash_pGAS[106] */
+	0x0F120087, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F120048, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F120051, /* TVAR_ash_pGAS[111] */
+	0x0F120070, /* TVAR_ash_pGAS[112] */
+	0x0F1200A0, /* TVAR_ash_pGAS[113] */
+	0x0F1200DF, /* TVAR_ash_pGAS[114] */
+	0x0F120126, /* TVAR_ash_pGAS[115] */
+	0x0F120168, /* TVAR_ash_pGAS[116] */
+	0x0F12016D, /* TVAR_ash_pGAS[117] */
+	0x0F12012F, /* TVAR_ash_pGAS[118] */
+	0x0F1200EF, /* TVAR_ash_pGAS[119] */
+	0x0F1200BA, /* TVAR_ash_pGAS[120] */
+	0x0F120093, /* TVAR_ash_pGAS[121] */
+	0x0F12007E, /* TVAR_ash_pGAS[122] */
+	0x0F120079, /* TVAR_ash_pGAS[123] */
+	0x0F120087, /* TVAR_ash_pGAS[124] */
+	0x0F1200A6, /* TVAR_ash_pGAS[125] */
+	0x0F1200D7, /* TVAR_ash_pGAS[126] */
+	0x0F120114, /* TVAR_ash_pGAS[127] */
+	0x0F120158, /* TVAR_ash_pGAS[128] */
+	0x0F120199, /* TVAR_ash_pGAS[129] */
+	0x0F1201A6, /* TVAR_ash_pGAS[130] */
+	0x0F12015E, /* TVAR_ash_pGAS[131] */
+	0x0F120122, /* TVAR_ash_pGAS[132] */
+	0x0F1200F1, /* TVAR_ash_pGAS[133] */
+	0x0F1200CB, /* TVAR_ash_pGAS[134] */
+	0x0F1200B6, /* TVAR_ash_pGAS[135] */
+	0x0F1200B2, /* TVAR_ash_pGAS[136] */
+	0x0F1200C0, /* TVAR_ash_pGAS[137] */
+	0x0F1200DF, /* TVAR_ash_pGAS[138] */
+	0x0F12010D, /* TVAR_ash_pGAS[139] */
+	0x0F120145, /* TVAR_ash_pGAS[140] */
+	0x0F120188, /* TVAR_ash_pGAS[141] */
+	0x0F1201DF, /* TVAR_ash_pGAS[142] */
+	0x0F12016C, /* TVAR_ash_pGAS[143] */
+	0x0F120127, /* TVAR_ash_pGAS[144] */
+	0x0F1200F2, /* TVAR_ash_pGAS[145] */
+	0x0F1200CA, /* TVAR_ash_pGAS[146] */
+	0x0F1200AC, /* TVAR_ash_pGAS[147] */
+	0x0F12009B, /* TVAR_ash_pGAS[148] */
+	0x0F120096, /* TVAR_ash_pGAS[149] */
+	0x0F12009C, /* TVAR_ash_pGAS[150] */
+	0x0F1200AE, /* TVAR_ash_pGAS[151] */
+	0x0F1200CC, /* TVAR_ash_pGAS[152] */
+	0x0F1200F4, /* TVAR_ash_pGAS[153] */
+	0x0F12012D, /* TVAR_ash_pGAS[154] */
+	0x0F120179, /* TVAR_ash_pGAS[155] */
+	0x0F120130, /* TVAR_ash_pGAS[156] */
+	0x0F1200F6, /* TVAR_ash_pGAS[157] */
+	0x0F1200C4, /* TVAR_ash_pGAS[158] */
+	0x0F120099, /* TVAR_ash_pGAS[159] */
+	0x0F12007C, /* TVAR_ash_pGAS[160] */
+	0x0F12006C, /* TVAR_ash_pGAS[161] */
+	0x0F120067, /* TVAR_ash_pGAS[162] */
+	0x0F12006E, /* TVAR_ash_pGAS[163] */
+	0x0F12007F, /* TVAR_ash_pGAS[164] */
+	0x0F12009E, /* TVAR_ash_pGAS[165] */
+	0x0F1200C8, /* TVAR_ash_pGAS[166] */
+	0x0F120100, /* TVAR_ash_pGAS[167] */
+	0x0F120138, /* TVAR_ash_pGAS[168] */
+	0x0F120107, /* TVAR_ash_pGAS[169] */
+	0x0F1200CF, /* TVAR_ash_pGAS[170] */
+	0x0F120097, /* TVAR_ash_pGAS[171] */
+	0x0F12006D, /* TVAR_ash_pGAS[172] */
+	0x0F120050, /* TVAR_ash_pGAS[173] */
+	0x0F120040, /* TVAR_ash_pGAS[174] */
+	0x0F12003B, /* TVAR_ash_pGAS[175] */
+	0x0F120042, /* TVAR_ash_pGAS[176] */
+	0x0F120055, /* TVAR_ash_pGAS[177] */
+	0x0F120074, /* TVAR_ash_pGAS[178] */
+	0x0F12009F, /* TVAR_ash_pGAS[179] */
+	0x0F1200D9, /* TVAR_ash_pGAS[180] */
+	0x0F120110, /* TVAR_ash_pGAS[181] */
+	0x0F1200E9, /* TVAR_ash_pGAS[182] */
+	0x0F1200AE, /* TVAR_ash_pGAS[183] */
+	0x0F120077, /* TVAR_ash_pGAS[184] */
+	0x0F12004D, /* TVAR_ash_pGAS[185] */
+	0x0F12002F, /* TVAR_ash_pGAS[186] */
+	0x0F12001F, /* TVAR_ash_pGAS[187] */
+	0x0F12001A, /* TVAR_ash_pGAS[188] */
+	0x0F120022, /* TVAR_ash_pGAS[189] */
+	0x0F120036, /* TVAR_ash_pGAS[190] */
+	0x0F120055, /* TVAR_ash_pGAS[191] */
+	0x0F120081, /* TVAR_ash_pGAS[192] */
+	0x0F1200BC, /* TVAR_ash_pGAS[193] */
+	0x0F1200F5, /* TVAR_ash_pGAS[194] */
+	0x0F1200D8, /* TVAR_ash_pGAS[195] */
+	0x0F12009C, /* TVAR_ash_pGAS[196] */
+	0x0F120064, /* TVAR_ash_pGAS[197] */
+	0x0F12003A, /* TVAR_ash_pGAS[198] */
+	0x0F12001C, /* TVAR_ash_pGAS[199] */
+	0x0F12000B, /* TVAR_ash_pGAS[200] */
+	0x0F120006, /* TVAR_ash_pGAS[201] */
+	0x0F12000F, /* TVAR_ash_pGAS[202] */
+	0x0F120024, /* TVAR_ash_pGAS[203] */
+	0x0F120044, /* TVAR_ash_pGAS[204] */
+	0x0F120070, /* TVAR_ash_pGAS[205] */
+	0x0F1200AD, /* TVAR_ash_pGAS[206] */
+	0x0F1200E6, /* TVAR_ash_pGAS[207] */
+	0x0F1200D0, /* TVAR_ash_pGAS[208] */
+	0x0F120095, /* TVAR_ash_pGAS[209] */
+	0x0F12005D, /* TVAR_ash_pGAS[210] */
+	0x0F120033, /* TVAR_ash_pGAS[211] */
+	0x0F120015, /* TVAR_ash_pGAS[212] */
+	0x0F120005, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120009, /* TVAR_ash_pGAS[215] */
+	0x0F12001E, /* TVAR_ash_pGAS[216] */
+	0x0F120041, /* TVAR_ash_pGAS[217] */
+	0x0F12006D, /* TVAR_ash_pGAS[218] */
+	0x0F1200AA, /* TVAR_ash_pGAS[219] */
+	0x0F1200E4, /* TVAR_ash_pGAS[220] */
+	0x0F1200D6, /* TVAR_ash_pGAS[221] */
+	0x0F12009A, /* TVAR_ash_pGAS[222] */
+	0x0F120062, /* TVAR_ash_pGAS[223] */
+	0x0F120038, /* TVAR_ash_pGAS[224] */
+	0x0F12001B, /* TVAR_ash_pGAS[225] */
+	0x0F12000A, /* TVAR_ash_pGAS[226] */
+	0x0F120006, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120026, /* TVAR_ash_pGAS[229] */
+	0x0F120049, /* TVAR_ash_pGAS[230] */
+	0x0F120076, /* TVAR_ash_pGAS[231] */
+	0x0F1200B4, /* TVAR_ash_pGAS[232] */
+	0x0F1200ED, /* TVAR_ash_pGAS[233] */
+	0x0F1200E4, /* TVAR_ash_pGAS[234] */
+	0x0F1200AB, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F120049, /* TVAR_ash_pGAS[237] */
+	0x0F12002C, /* TVAR_ash_pGAS[238] */
+	0x0F12001C, /* TVAR_ash_pGAS[239] */
+	0x0F120019, /* TVAR_ash_pGAS[240] */
+	0x0F120023, /* TVAR_ash_pGAS[241] */
+	0x0F12003A, /* TVAR_ash_pGAS[242] */
+	0x0F12005D, /* TVAR_ash_pGAS[243] */
+	0x0F12008B, /* TVAR_ash_pGAS[244] */
+	0x0F1200C8, /* TVAR_ash_pGAS[245] */
+	0x0F1200FF, /* TVAR_ash_pGAS[246] */
+	0x0F1200FF, /* TVAR_ash_pGAS[247] */
+	0x0F1200C8, /* TVAR_ash_pGAS[248] */
+	0x0F120090, /* TVAR_ash_pGAS[249] */
+	0x0F120066, /* TVAR_ash_pGAS[250] */
+	0x0F12004A, /* TVAR_ash_pGAS[251] */
+	0x0F12003A, /* TVAR_ash_pGAS[252] */
+	0x0F120038, /* TVAR_ash_pGAS[253] */
+	0x0F120042, /* TVAR_ash_pGAS[254] */
+	0x0F120059, /* TVAR_ash_pGAS[255] */
+	0x0F12007C, /* TVAR_ash_pGAS[256] */
+	0x0F1200AB, /* TVAR_ash_pGAS[257] */
+	0x0F1200E7, /* TVAR_ash_pGAS[258] */
+	0x0F12011D, /* TVAR_ash_pGAS[259] */
+	0x0F120123, /* TVAR_ash_pGAS[260] */
+	0x0F1200EC, /* TVAR_ash_pGAS[261] */
+	0x0F1200B7, /* TVAR_ash_pGAS[262] */
+	0x0F12008E, /* TVAR_ash_pGAS[263] */
+	0x0F120073, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F120062, /* TVAR_ash_pGAS[266] */
+	0x0F12006D, /* TVAR_ash_pGAS[267] */
+	0x0F120083, /* TVAR_ash_pGAS[268] */
+	0x0F1200A7, /* TVAR_ash_pGAS[269] */
+	0x0F1200D4, /* TVAR_ash_pGAS[270] */
+	0x0F12010B, /* TVAR_ash_pGAS[271] */
+	0x0F120144, /* TVAR_ash_pGAS[272] */
+	0x0F120156, /* TVAR_ash_pGAS[273] */
+	0x0F120114, /* TVAR_ash_pGAS[274] */
+	0x0F1200E2, /* TVAR_ash_pGAS[275] */
+	0x0F1200BB, /* TVAR_ash_pGAS[276] */
+	0x0F12009F, /* TVAR_ash_pGAS[277] */
+	0x0F120090, /* TVAR_ash_pGAS[278] */
+	0x0F12008E, /* TVAR_ash_pGAS[279] */
+	0x0F120099, /* TVAR_ash_pGAS[280] */
+	0x0F1200B0, /* TVAR_ash_pGAS[281] */
+	0x0F1200D2, /* TVAR_ash_pGAS[282] */
+	0x0F1200FE, /* TVAR_ash_pGAS[283] */
+	0x0F120133, /* TVAR_ash_pGAS[284] */
+	0x0F12017D, /* TVAR_ash_pGAS[285] */
+	0x0F120174, /* TVAR_ash_pGAS[286] */
+	0x0F12012A, /* TVAR_ash_pGAS[287] */
+	0x0F1200F6, /* TVAR_ash_pGAS[288] */
+	0x0F1200CC, /* TVAR_ash_pGAS[289] */
+	0x0F1200AD, /* TVAR_ash_pGAS[290] */
+	0x0F12009C, /* TVAR_ash_pGAS[291] */
+	0x0F120099, /* TVAR_ash_pGAS[292] */
+	0x0F1200A4, /* TVAR_ash_pGAS[293] */
+	0x0F1200BC, /* TVAR_ash_pGAS[294] */
+	0x0F1200E0, /* TVAR_ash_pGAS[295] */
+	0x0F12010E, /* TVAR_ash_pGAS[296] */
+	0x0F120147, /* TVAR_ash_pGAS[297] */
+	0x0F120193, /* TVAR_ash_pGAS[298] */
+	0x0F12013A, /* TVAR_ash_pGAS[299] */
+	0x0F1200FE, /* TVAR_ash_pGAS[300] */
+	0x0F1200C9, /* TVAR_ash_pGAS[301] */
+	0x0F12009E, /* TVAR_ash_pGAS[302] */
+	0x0F12007E, /* TVAR_ash_pGAS[303] */
+	0x0F12006E, /* TVAR_ash_pGAS[304] */
+	0x0F12006B, /* TVAR_ash_pGAS[305] */
+	0x0F120075, /* TVAR_ash_pGAS[306] */
+	0x0F12008D, /* TVAR_ash_pGAS[307] */
+	0x0F1200B2, /* TVAR_ash_pGAS[308] */
+	0x0F1200E0, /* TVAR_ash_pGAS[309] */
+	0x0F12011B, /* TVAR_ash_pGAS[310] */
+	0x0F120152, /* TVAR_ash_pGAS[311] */
+	0x0F120112, /* TVAR_ash_pGAS[312] */
+	0x0F1200D8, /* TVAR_ash_pGAS[313] */
+	0x0F12009F, /* TVAR_ash_pGAS[314] */
+	0x0F120073, /* TVAR_ash_pGAS[315] */
+	0x0F120054, /* TVAR_ash_pGAS[316] */
+	0x0F120042, /* TVAR_ash_pGAS[317] */
+	0x0F12003F, /* TVAR_ash_pGAS[318] */
+	0x0F120049, /* TVAR_ash_pGAS[319] */
+	0x0F120061, /* TVAR_ash_pGAS[320] */
+	0x0F120085, /* TVAR_ash_pGAS[321] */
+	0x0F1200B5, /* TVAR_ash_pGAS[322] */
+	0x0F1200F2, /* TVAR_ash_pGAS[323] */
+	0x0F120128, /* TVAR_ash_pGAS[324] */
+	0x0F1200F5, /* TVAR_ash_pGAS[325] */
+	0x0F1200BA, /* TVAR_ash_pGAS[326] */
+	0x0F120080, /* TVAR_ash_pGAS[327] */
+	0x0F120054, /* TVAR_ash_pGAS[328] */
+	0x0F120034, /* TVAR_ash_pGAS[329] */
+	0x0F120022, /* TVAR_ash_pGAS[330] */
+	0x0F12001D, /* TVAR_ash_pGAS[331] */
+	0x0F120027, /* TVAR_ash_pGAS[332] */
+	0x0F12003F, /* TVAR_ash_pGAS[333] */
+	0x0F120064, /* TVAR_ash_pGAS[334] */
+	0x0F120092, /* TVAR_ash_pGAS[335] */
+	0x0F1200CF, /* TVAR_ash_pGAS[336] */
+	0x0F120109, /* TVAR_ash_pGAS[337] */
+	0x0F1200E4, /* TVAR_ash_pGAS[338] */
+	0x0F1200A8, /* TVAR_ash_pGAS[339] */
+	0x0F12006E, /* TVAR_ash_pGAS[340] */
+	0x0F120041, /* TVAR_ash_pGAS[341] */
+	0x0F120021, /* TVAR_ash_pGAS[342] */
+	0x0F12000E, /* TVAR_ash_pGAS[343] */
+	0x0F120008, /* TVAR_ash_pGAS[344] */
+	0x0F120012, /* TVAR_ash_pGAS[345] */
+	0x0F120029, /* TVAR_ash_pGAS[346] */
+	0x0F12004D, /* TVAR_ash_pGAS[347] */
+	0x0F12007C, /* TVAR_ash_pGAS[348] */
+	0x0F1200B8, /* TVAR_ash_pGAS[349] */
+	0x0F1200F3, /* TVAR_ash_pGAS[350] */
+	0x0F1200DF, /* TVAR_ash_pGAS[351] */
+	0x0F1200A2, /* TVAR_ash_pGAS[352] */
+	0x0F120068, /* TVAR_ash_pGAS[353] */
+	0x0F12003B, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120006, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120009, /* TVAR_ash_pGAS[358] */
+	0x0F12001F, /* TVAR_ash_pGAS[359] */
+	0x0F120042, /* TVAR_ash_pGAS[360] */
+	0x0F120071, /* TVAR_ash_pGAS[361] */
+	0x0F1200AE, /* TVAR_ash_pGAS[362] */
+	0x0F1200E9, /* TVAR_ash_pGAS[363] */
+	0x0F1200E4, /* TVAR_ash_pGAS[364] */
+	0x0F1200A7, /* TVAR_ash_pGAS[365] */
+	0x0F12006C, /* TVAR_ash_pGAS[366] */
+	0x0F12003F, /* TVAR_ash_pGAS[367] */
+	0x0F12001E, /* TVAR_ash_pGAS[368] */
+	0x0F12000B, /* TVAR_ash_pGAS[369] */
+	0x0F120004, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F120022, /* TVAR_ash_pGAS[372] */
+	0x0F120044, /* TVAR_ash_pGAS[373] */
+	0x0F120072, /* TVAR_ash_pGAS[374] */
+	0x0F1200AE, /* TVAR_ash_pGAS[375] */
+	0x0F1200EA, /* TVAR_ash_pGAS[376] */
+	0x0F1200F5, /* TVAR_ash_pGAS[377] */
+	0x0F1200B9, /* TVAR_ash_pGAS[378] */
+	0x0F12007D, /* TVAR_ash_pGAS[379] */
+	0x0F120051, /* TVAR_ash_pGAS[380] */
+	0x0F12002F, /* TVAR_ash_pGAS[381] */
+	0x0F12001C, /* TVAR_ash_pGAS[382] */
+	0x0F120015, /* TVAR_ash_pGAS[383] */
+	0x0F12001D, /* TVAR_ash_pGAS[384] */
+	0x0F120031, /* TVAR_ash_pGAS[385] */
+	0x0F120053, /* TVAR_ash_pGAS[386] */
+	0x0F120080, /* TVAR_ash_pGAS[387] */
+	0x0F1200BC, /* TVAR_ash_pGAS[388] */
+	0x0F1200F7, /* TVAR_ash_pGAS[389] */
+	0x0F120111, /* TVAR_ash_pGAS[390] */
+	0x0F1200D6, /* TVAR_ash_pGAS[391] */
+	0x0F12009C, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F12004E, /* TVAR_ash_pGAS[394] */
+	0x0F12003A, /* TVAR_ash_pGAS[395] */
+	0x0F120033, /* TVAR_ash_pGAS[396] */
+	0x0F12003A, /* TVAR_ash_pGAS[397] */
+	0x0F12004E, /* TVAR_ash_pGAS[398] */
+	0x0F12006E, /* TVAR_ash_pGAS[399] */
+	0x0F12009B, /* TVAR_ash_pGAS[400] */
+	0x0F1200D5, /* TVAR_ash_pGAS[401] */
+	0x0F12010F, /* TVAR_ash_pGAS[402] */
+	0x0F120139, /* TVAR_ash_pGAS[403] */
+	0x0F1200FD, /* TVAR_ash_pGAS[404] */
+	0x0F1200C6, /* TVAR_ash_pGAS[405] */
+	0x0F120098, /* TVAR_ash_pGAS[406] */
+	0x0F120077, /* TVAR_ash_pGAS[407] */
+	0x0F120064, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120064, /* TVAR_ash_pGAS[410] */
+	0x0F120076, /* TVAR_ash_pGAS[411] */
+	0x0F120095, /* TVAR_ash_pGAS[412] */
+	0x0F1200C2, /* TVAR_ash_pGAS[413] */
+	0x0F1200F8, /* TVAR_ash_pGAS[414] */
+	0x0F120135, /* TVAR_ash_pGAS[415] */
+	0x0F12016C, /* TVAR_ash_pGAS[416] */
+	0x0F120128, /* TVAR_ash_pGAS[417] */
+	0x0F1200F2, /* TVAR_ash_pGAS[418] */
+	0x0F1200C7, /* TVAR_ash_pGAS[419] */
+	0x0F1200A4, /* TVAR_ash_pGAS[420] */
+	0x0F120092, /* TVAR_ash_pGAS[421] */
+	0x0F12008A, /* TVAR_ash_pGAS[422] */
+	0x0F12008F, /* TVAR_ash_pGAS[423] */
+	0x0F1200A3, /* TVAR_ash_pGAS[424] */
+	0x0F1200C0, /* TVAR_ash_pGAS[425] */
+	0x0F1200EA, /* TVAR_ash_pGAS[426] */
+	0x0F120121, /* TVAR_ash_pGAS[427] */
+	0x0F12016F, /* TVAR_ash_pGAS[428] */
+	0x0F120123, /* TVAR_ash_pGAS[429] */
+	0x0F1200E7, /* TVAR_ash_pGAS[430] */
+	0x0F1200BD, /* TVAR_ash_pGAS[431] */
+	0x0F12009C, /* TVAR_ash_pGAS[432] */
+	0x0F120087, /* TVAR_ash_pGAS[433] */
+	0x0F12007C, /* TVAR_ash_pGAS[434] */
+	0x0F12007B, /* TVAR_ash_pGAS[435] */
+	0x0F120086, /* TVAR_ash_pGAS[436] */
+	0x0F120099, /* TVAR_ash_pGAS[437] */
+	0x0F1200B7, /* TVAR_ash_pGAS[438] */
+	0x0F1200DC, /* TVAR_ash_pGAS[439] */
+	0x0F12010E, /* TVAR_ash_pGAS[440] */
+	0x0F12014A, /* TVAR_ash_pGAS[441] */
+	0x0F1200F1, /* TVAR_ash_pGAS[442] */
+	0x0F1200C1, /* TVAR_ash_pGAS[443] */
+	0x0F120096, /* TVAR_ash_pGAS[444] */
+	0x0F120077, /* TVAR_ash_pGAS[445] */
+	0x0F120062, /* TVAR_ash_pGAS[446] */
+	0x0F120058, /* TVAR_ash_pGAS[447] */
+	0x0F120057, /* TVAR_ash_pGAS[448] */
+	0x0F120061, /* TVAR_ash_pGAS[449] */
+	0x0F120074, /* TVAR_ash_pGAS[450] */
+	0x0F120090, /* TVAR_ash_pGAS[451] */
+	0x0F1200B7, /* TVAR_ash_pGAS[452] */
+	0x0F1200E7, /* TVAR_ash_pGAS[453] */
+	0x0F120113, /* TVAR_ash_pGAS[454] */
+	0x0F1200CB, /* TVAR_ash_pGAS[455] */
+	0x0F12009D, /* TVAR_ash_pGAS[456] */
+	0x0F120071, /* TVAR_ash_pGAS[457] */
+	0x0F120052, /* TVAR_ash_pGAS[458] */
+	0x0F120040, /* TVAR_ash_pGAS[459] */
+	0x0F120035, /* TVAR_ash_pGAS[460] */
+	0x0F120034, /* TVAR_ash_pGAS[461] */
+	0x0F12003D, /* TVAR_ash_pGAS[462] */
+	0x0F12004F, /* TVAR_ash_pGAS[463] */
+	0x0F12006B, /* TVAR_ash_pGAS[464] */
+	0x0F120090, /* TVAR_ash_pGAS[465] */
+	0x0F1200C2, /* TVAR_ash_pGAS[466] */
+	0x0F1200EC, /* TVAR_ash_pGAS[467] */
+	0x0F1200B0, /* TVAR_ash_pGAS[468] */
+	0x0F120082, /* TVAR_ash_pGAS[469] */
+	0x0F120057, /* TVAR_ash_pGAS[470] */
+	0x0F12003A, /* TVAR_ash_pGAS[471] */
+	0x0F120026, /* TVAR_ash_pGAS[472] */
+	0x0F12001B, /* TVAR_ash_pGAS[473] */
+	0x0F120019, /* TVAR_ash_pGAS[474] */
+	0x0F120021, /* TVAR_ash_pGAS[475] */
+	0x0F120033, /* TVAR_ash_pGAS[476] */
+	0x0F12004F, /* TVAR_ash_pGAS[477] */
+	0x0F120072, /* TVAR_ash_pGAS[478] */
+	0x0F1200A2, /* TVAR_ash_pGAS[479] */
+	0x0F1200CF, /* TVAR_ash_pGAS[480] */
+	0x0F12009F, /* TVAR_ash_pGAS[481] */
+	0x0F120072, /* TVAR_ash_pGAS[482] */
+	0x0F120047, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120016, /* TVAR_ash_pGAS[485] */
+	0x0F12000A, /* TVAR_ash_pGAS[486] */
+	0x0F120008, /* TVAR_ash_pGAS[487] */
+	0x0F12000F, /* TVAR_ash_pGAS[488] */
+	0x0F120021, /* TVAR_ash_pGAS[489] */
+	0x0F12003A, /* TVAR_ash_pGAS[490] */
+	0x0F12005C, /* TVAR_ash_pGAS[491] */
+	0x0F12008C, /* TVAR_ash_pGAS[492] */
+	0x0F1200BB, /* TVAR_ash_pGAS[493] */
+	0x0F12009A, /* TVAR_ash_pGAS[494] */
+	0x0F12006C, /* TVAR_ash_pGAS[495] */
+	0x0F120042, /* TVAR_ash_pGAS[496] */
+	0x0F120024, /* TVAR_ash_pGAS[497] */
+	0x0F120010, /* TVAR_ash_pGAS[498] */
+	0x0F120004, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120007, /* TVAR_ash_pGAS[501] */
+	0x0F120018, /* TVAR_ash_pGAS[502] */
+	0x0F120030, /* TVAR_ash_pGAS[503] */
+	0x0F120050, /* TVAR_ash_pGAS[504] */
+	0x0F120080, /* TVAR_ash_pGAS[505] */
+	0x0F1200AF, /* TVAR_ash_pGAS[506] */
+	0x0F12009F, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F120046, /* TVAR_ash_pGAS[509] */
+	0x0F120028, /* TVAR_ash_pGAS[510] */
+	0x0F120014, /* TVAR_ash_pGAS[511] */
+	0x0F120006, /* TVAR_ash_pGAS[512] */
+	0x0F120003, /* TVAR_ash_pGAS[513] */
+	0x0F120009, /* TVAR_ash_pGAS[514] */
+	0x0F120019, /* TVAR_ash_pGAS[515] */
+	0x0F120030, /* TVAR_ash_pGAS[516] */
+	0x0F120051, /* TVAR_ash_pGAS[517] */
+	0x0F120080, /* TVAR_ash_pGAS[518] */
+	0x0F1200B0, /* TVAR_ash_pGAS[519] */
+	0x0F1200AD, /* TVAR_ash_pGAS[520] */
+	0x0F120080, /* TVAR_ash_pGAS[521] */
+	0x0F120055, /* TVAR_ash_pGAS[522] */
+	0x0F120036, /* TVAR_ash_pGAS[523] */
+	0x0F120021, /* TVAR_ash_pGAS[524] */
+	0x0F120015, /* TVAR_ash_pGAS[525] */
+	0x0F120010, /* TVAR_ash_pGAS[526] */
+	0x0F120016, /* TVAR_ash_pGAS[527] */
+	0x0F120024, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F12005B, /* TVAR_ash_pGAS[530] */
+	0x0F12008B, /* TVAR_ash_pGAS[531] */
+	0x0F1200BA, /* TVAR_ash_pGAS[532] */
+	0x0F1200C8, /* TVAR_ash_pGAS[533] */
+	0x0F120099, /* TVAR_ash_pGAS[534] */
+	0x0F12006E, /* TVAR_ash_pGAS[535] */
+	0x0F12004E, /* TVAR_ash_pGAS[536] */
+	0x0F12003A, /* TVAR_ash_pGAS[537] */
+	0x0F12002D, /* TVAR_ash_pGAS[538] */
+	0x0F12002A, /* TVAR_ash_pGAS[539] */
+	0x0F12002E, /* TVAR_ash_pGAS[540] */
+	0x0F12003B, /* TVAR_ash_pGAS[541] */
+	0x0F120051, /* TVAR_ash_pGAS[542] */
+	0x0F120072, /* TVAR_ash_pGAS[543] */
+	0x0F1200A1, /* TVAR_ash_pGAS[544] */
+	0x0F1200D2, /* TVAR_ash_pGAS[545] */
+	0x0F1200EC, /* TVAR_ash_pGAS[546] */
+	0x0F1200BE, /* TVAR_ash_pGAS[547] */
+	0x0F120092, /* TVAR_ash_pGAS[548] */
+	0x0F120072, /* TVAR_ash_pGAS[549] */
+	0x0F12005C, /* TVAR_ash_pGAS[550] */
+	0x0F120050, /* TVAR_ash_pGAS[551] */
+	0x0F12004D, /* TVAR_ash_pGAS[552] */
+	0x0F120050, /* TVAR_ash_pGAS[553] */
+	0x0F12005D, /* TVAR_ash_pGAS[554] */
+	0x0F120073, /* TVAR_ash_pGAS[555] */
+	0x0F120094, /* TVAR_ash_pGAS[556] */
+	0x0F1200C2, /* TVAR_ash_pGAS[557] */
+	0x0F1200F4, /* TVAR_ash_pGAS[558] */
+	0x0F12011A, /* TVAR_ash_pGAS[559] */
+	0x0F1200E3, /* TVAR_ash_pGAS[560] */
+	0x0F1200B7, /* TVAR_ash_pGAS[561] */
+	0x0F120097, /* TVAR_ash_pGAS[562] */
+	0x0F120081, /* TVAR_ash_pGAS[563] */
+	0x0F120075, /* TVAR_ash_pGAS[564] */
+	0x0F12006F, /* TVAR_ash_pGAS[565] */
+	0x0F120074, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120097, /* TVAR_ash_pGAS[568] */
+	0x0F1200B8, /* TVAR_ash_pGAS[569] */
+	0x0F1200E7, /* TVAR_ash_pGAS[570] */
+	0x0F120127, /* TVAR_ash_pGAS[571] */
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[0][15] */
+	
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[1][15] */
+	
+	0x0F120000, /* SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F12000D, /* SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F12001B, /* SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F12003C, /* SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120081, /* SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200FE, /* SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120159, /* SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F1201A1, /* SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F120210, /* SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120263, /* SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202D8, /* SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F120338, /* SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120384, /* SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203BA, /* SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203E8, /* SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F120400, /* SARR_usGammaLutRGBIndoor[2][15] */
+	
+	
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000, /* awbb_LowBr_NBzone  */
+	0x0F120000, /* awbb_LowBr0_NBzone */
+	0x002A0E8C,
+	0x0F120000, /* awbb_LowBr0_PatchNumZone */
+	0x002A0D6C,
+	0x0F120040, /* awbb_YMedMoveToYAv */
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F120264,
+	0x0F120279,
+	0x0F120250,
+	0x0F120287,
+	0x0F120244,
+	0x0F120287,
+	0x0F120235,
+	0x0F120289,
+	0x0F120225,
+	0x0F120287,
+	0x0F120213,
+	0x0F120286,
+	0x0F120202,
+	0x0F12027A,
+	0x0F1201F3,
+	0x0F120272,
+	0x0F1201E9,
+	0x0F120269,
+	0x0F1201E2,
+	0x0F120263,
+	0x0F1201E0,
+	0x0F12025A,
+	0x0F1201E1,
+	0x0F120256,
+	0x0F1201EE,
+	0x0F120251,
+	0x0F1201F8,
+	0x0F12024A,
+	0x0F12020D,
+	0x0F120231,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120011,
+	0x0F120000,
+	0x0F1201FF,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/* Low Brightness Gray Zone */
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end	awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F120000, /* awbb_GridCorr_R_0__0_ */
+	0x0F120000, /* awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120068, /* awbb_GridCorr_R_0__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_R_1__0_ */
+	0x0F120000, /* awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120068, /* awbb_GridCorr_R_1__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_R_2__0_ */
+	0x0F120000, /* awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120068, /* awbb_GridCorr_R_2__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F120000, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_0__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F120000, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_1__5_ */
+	
+	0x0F120000, /* awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F120000, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFF0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FED4, /* awbb_GridCorr_B_2__5_ */
+	
+	0x0F1202C6, /* awbb_GridConst_1_0_ */
+	0x0F120335, /* awbb_GridConst_1_1_ */
+	0x0F1203B3, /* awbb_GridConst_1_2_ */
+	0x0F120FD7, /* awbb_GridConst_2_0  */
+	0x0F1210C5, /* awbb_GridConst_2_1  */
+	0x0F12116A, /* awbb_GridConst_2_2  */
+	0x0F12117C, /* awbb_GridConst_2_3  */
+	0x0F1211C2, /* awbb_GridConst_2_4  */
+	0x0F12120B, /* awbb_GridConst_2_5  */
+	
+	0x0F1200B3, /* awbb_GridCoeff_R_1 */
+	0x0F1200B7, /* awbb_GridCoeff_B_1 */
+	0x0F1200D3, /* awbb_GridCoeff_R_2 */
+	0x0F120091, /* awbb_GridCoeff_B_2 */
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+	
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000, /* awbb_OutdoorFltrSz (outdoor WB moving average filtering) */
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	/* awbb_ChromaClassifyEn, default : enable */
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* param_start	TVAR_wbt_pBaseCcms */
+	0x002A2800,
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+	
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+	
+	0x0F1201E1, /* 01FB */
+	0x0F12FFC4, /* FF9C */
+	0x0F12FFF8, /* FFFF */
+	0x0F120101, /* 0137 */
+	0x0F12014C, /* 0113 */
+	0x0F12FF55, /* FF6F */
+	0x0F12FF5B, /* FF21 */
+	0x0F120205, /* 0194 */
+	0x0F12FF17, /* FF69 */
+	0x0F12FEFE, /* FF14 */
+	0x0F1201B6, /* 0158 */
+	0x0F120107, /* 015D */
+	0x0F12FFDB, /* FFF2 */
+	0x0F12FFDB, /* FFF1 */
+	0x0F1201D1, /* 0179 */
+	0x0F120163, /* 017C */
+	0x0F12FF9E, /* FFC3 */
+	0x0F1201B3, /* 0197 */
+	
+	0x0F1201FB, /* 01FB */
+	0x0F12FFA9, /* FF9C */
+	0x0F12FFEA, /* FFFF */
+	0x0F120134, /* 0137 */
+	0x0F120133, /* 0113 */
+	0x0F12FF5D, /* FF6F */
+	0x0F12FE7A, /* FF21 */
+	0x0F12017D, /* 0194 */
+	0x0F12FEED, /* FF69 */
+	0x0F12FF39, /* FF14 */
+	0x0F1201D6, /* 0158 */
+	0x0F1200C4, /* 015D */
+	0x0F12FFCE, /* FFF2 */
+	0x0F12FFCD, /* FFF1 */
+	0x0F1201B7, /* 0179 */
+	0x0F120176, /* 017C */
+	0x0F12FFBD, /* FFC3 */
+	0x0F120191, /* 0197 */
+	
+	0x0F1201FB, /* 01FB */
+	0x0F12FFA9, /* FF9C */
+	0x0F12FFEA, /* FFFF */
+	0x0F120134, /* 0137 */
+	0x0F120133, /* 0113 */
+	0x0F12FF5D, /* FF6F */
+	0x0F12FE7A, /* FF21 */
+	0x0F12017D, /* 0194 */
+	0x0F12FEED, /* FF69 */
+	0x0F12FF39, /* FF14 */
+	0x0F1201D6, /* 0158 */
+	0x0F1200C4, /* 015D */
+	0x0F12FFCE, /* FFF2 */
+	0x0F12FFCD, /* FFF1 */
+	0x0F1201B7, /* 0179 */
+	0x0F120176, /* 017C */
+	0x0F12FFBD, /* FFC3 */
+	0x0F120191, /* 0197 */
+	
+	0x0F1201D2, /* 01D0 */
+	0x0F12FFC2, /* FFB4 */
+	0x0F12FFFC, /* 000C */
+	0x0F12011E, /* 0122 */
+	0x0F12011D, /* 0103 */
+	0x0F12FF86, /* FF9B */
+	0x0F12FE78, /* FF33 */
+	0x0F12017B, /* 01C5 */
+	0x0F12FEEB, /* FF33 */
+	0x0F12FF38, /* FF16 */
+	0x0F1201D5, /* 015A */
+	0x0F1200C3, /* 015F */
+	0x0F12FFCF, /* FFE0 */
+	0x0F12FFCE, /* FFDF */
+	0x0F1201B8, /* 0197 */
+	0x0F120178, /* 0178 */
+	0x0F12FFBF, /* FFBF */
+	0x0F120193, /* 0193 */
+	
+	0x0F1201E0, /* outdoor CCM */
+	0x0F12FFBF,
+	0x0F12FFFD,
+	0x0F1200F5,
+	0x0F120139,
+	0x0F12FF74,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /* afit_bUseNoiseInd 0 : NB 1: Noise Index */
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+	
+	
+	/* Set AFIT */
+	/* AFIT Start Address */
+	0x002A0814,
+	0x0F12082C, /* TVAR_afit_pBaseVals */
+	0x0F127000, /* TVAR_afit_pBaseVals */
+	
+	/* param_start	TVAR_afit_pBaseVals */
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120030, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F1203ff, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F1203ff, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120344, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12090F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F120032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120412, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F12040C, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120005, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120805, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F1201AA, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120032, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120000, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120114, /* UVDenoise_iYLowThresh*/
+	0x0F12020A, /* UVDenoise_iYHighThresh*/
+	0x0F1203FF, /* UVDenoise_iUVLowThresh*/
+	0x0F1203FF, /* UVDenoise_iUVHighThresh*/
+	0x0F120028, /* DSMix1_iLowLimit_Wide*/
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin*/
+	0x0F120014, /* DSMix1_iHighLimit_Wide*/
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin*/
+	0x0F120050, /* DSMix1_iLowLimit_Fine*/
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin*/
+	0x0F120046, /* DSMix1_iHighLimit_Fine*/
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin*/
+	0x0F120106, /* DSMix1_iRGBOffset*/
+	0x0F12006F, /* DSMix1_iDemClamp*/
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin" bin: desparity low */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin" */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12090F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F120032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120412, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F12040C, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120005, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120805, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F1201A0, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120015, /*  RGB2YUV_iYOffset                                                      */
+	         
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F120000, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120129, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F12100F, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F121032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120500, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121008, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120164, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F128028, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F120002, /* SATURATION                                                             */
+	0x0F120000, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120014, /* UVDenoise_iYLowThresh                                                  */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122019, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F122032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x0F120000, /* BRIGHTNESS                                                             */
+	0x0F120014, /* CONTRAST                                                               */
+	0x0F12000A, /* SATURATION                                                             */
+	0x0F120008, /* SHARP_BLUR                                                             */
+	0x0F120000, /* GLAMOUR                                                                */
+	0x0F1203FF, /* Disparity_iSatSat                                                      */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                                */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                            */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                               */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                           */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                               */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                              */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                                */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                               */
+	0x0F1203FF, /* Denoise1_iSatSat                                                       */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                                 */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                                */
+	0x0F120000, /* UVDenoise_iYLowThresh                                                  */
+	0x0F120000, /* UVDenoise_iYHighThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                                 */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                                */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                              */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                             */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                                  */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                              */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                                 */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                             */
+	0x0F120106, /* DSMix1_iRGBOffset                                                      */
+	0x0F12006F, /* DSMix1_iDemClamp                                                       */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"    bin: desparity low */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                    */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin"     */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin         */
+	0x0F121408, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                    */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                      */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"            */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                    */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                     */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                              */
+	0x0F120F05, /* "Denoise1_iWideDenoise1_iWideWide"                                     */
+	0x0F120105, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                          */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                            */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                      */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                     */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                    */
+	0x0F122019, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                       */
+	0x0F122032, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                     */
+	0x0F120A0A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                        */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                      */
+	0x0F120405, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                     */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"             */
+	0x0F120003, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"                   */
+	0x0F120808, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                     */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                     */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                     */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                           */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                             */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                           */
+	0x0F12805A, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                               */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                               */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                      */
+	
+	0x0F1200FF, /* Denoise1_iUVDenThreshLow                         */
+	0x0F1200FF, /* Denoise1_iUVDenThreshHigh                        */
+	0x0F120800, /* Denoise1_sensor_width                            */
+	0x0F120600, /* Denoise1_sensor_height                           */
+	0x0F120000, /* Denoise1_start_x                                 */
+	0x0F120000, /* Denoise1_start_y                                 */
+	0x0F120000, /* "Denoise1_iYDenSmoothDenoise1_iWSharp  "         */
+	0x0F120300, /* "Denoise1_iWWSharp Denoise1_iRadialTune  "       */
+	0x0F120002, /* "Denoise1_iOutputBrightnessDenoise1_binning_x  " */
+	0x0F120400, /* "Denoise1_binning_yDemosaic4_iFDeriv  "          */
+	0x0F120106, /* "Demosaic4_iFDerivNeiDemosaic4_iSDeriv  "        */
+	0x0F120005, /* "Demosaic4_iSDerivNeiDemosaic4_iEnhancerG  "     */
+	0x0F120000, /* "Demosaic4_iEnhancerRBDemosaic4_iEnhancerV  "    */
+	0x0F120703, /* "Demosaic4_iDecisionThreshDemosaic4_iDesatThresh"*/
+	0x0F120000, /*  Demosaic4_iBypassSelect                         */
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Wifi VT-Call END of Initial */
+};
+
+/*===========================================
+* CAMERA_PREVIEW - ÃÔ¿µ ÈÄ ÇÁ¸®ºä º¹±Í½Ã ¼ÂÆà *
+============================================*/
+
+static const u32 s5k5bafx_preview[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+
+};
+
+/*===========================================
+*	CAMERA_SNAPSHOT  - ÃÔ¿µ 		  *
+============================================*/
+
+static const u32 s5k5bafx_capture[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0224,
+	0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A0226,
+	0x0F120001, /* REG_TC_GP_CapConfigChanged */
+	0x002A01F4,
+	0x0F120001, /* REG_TC_GP_EnableCapture */
+	0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+	0xffff0096, /* 150ms */
+
+	/*  MIPI */
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+/*===========================================
+*	CAMERA_RECORDING WITH 25fps  *
+============================================*/
+
+static const u32 s5k5bafx_recording_60Hz_common[] = {
+	
+	/* recording 25fps Anti-Flicker 60Hz*/
+	
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* p100	Delay */
+	
+	
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+	
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+
+
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A, /* TVAR_ae_BrAve */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+	
+	
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /* uMaxExp1 */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /* uMaxExp2 */
+	0x0F120000,
+	0x0F12A122, /* uMaxExp3 */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /* uMaxExp4 */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0, /* lt_uMaxAnGain0   */
+	0x0F1201E0, /* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300, /* lt_uMaxAnGain1 */
+	0x0F120650, /* lt_uMaxAnGain2 */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /* ae_StatMode */
+	
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202A8,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120298,
+	
+	/* 1. Auto Flicker 60Hz Start */
+	0x002A0B2E,
+	0x0F120001, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12005F, /* REG_TC_DBG_AutoAlgEnBits   default : 007F */
+	
+	
+	0xffff000a, /* p10	Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+	
+	/* Parallel or MIPI Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+	
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F122EE0, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+	
+	
+	
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* p100                          */
+	
+	
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+	
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 30fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight               */
+	0x0F120005, /* REG_0TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd              */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType           */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType      */
+	0x0F12018c, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12018c, /* REG_0TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_0TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_0TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_0TC_PCFG_uRotation              */
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight               */
+	0x0F120005, /* REG_1TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd              */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType           */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType      */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_1TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_1TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_1TC_PCFG_uRotation              */
+	
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+	
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+	
+	
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F12011a, /* 100 TVAR_ash_GASOutdoorAlpha_0_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[0][15] */
+	
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[1][15] */
+	
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[2][15] */
+	
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000,
+	0x0F120000,
+	0x002A0E8C,
+	0x0F120000,
+	0x002A0D6C,
+	0x0F120040,
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /* 0264 awbb_OutdoorGrZones_m_BGrid_0__m_left    */
+	0x0F120282, /* 0279 awbb_OutdoorGrZones_m_BGrid_0__m_right   */
+	0x0F120240, /* 0250 awbb_OutdoorGrZones_m_BGrid_1__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_1__m_right   */
+	0x0F12022A, /* 0244 awbb_OutdoorGrZones_m_BGrid_2__m_left    */
+	0x0F12029A, /* 0287 awbb_OutdoorGrZones_m_BGrid_2__m_right   */
+	0x0F12021A, /* 0235 awbb_OutdoorGrZones_m_BGrid_3__m_left    */
+	0x0F12029A, /* 0289 awbb_OutdoorGrZones_m_BGrid_3__m_right   */
+	0x0F120206, /* 0225 awbb_OutdoorGrZones_m_BGrid_4__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_4__m_right   */
+	0x0F1201FE, /* 0213 awbb_OutdoorGrZones_m_BGrid_5__m_left    */
+	0x0F12028C, /* 0286 awbb_OutdoorGrZones_m_BGrid_5__m_right   */
+	0x0F1201FA, /* 0202 awbb_OutdoorGrZones_m_BGrid_6__m_left    */
+	0x0F120278, /* 027A awbb_OutdoorGrZones_m_BGrid_6__m_right   */
+	0x0F1201F8, /* 01F3 awbb_OutdoorGrZones_m_BGrid_7__m_left    */
+	0x0F120266, /* 0272 awbb_OutdoorGrZones_m_BGrid_7__m_right   */
+	0x0F120214, /* 01E9 awbb_OutdoorGrZones_m_BGrid_8__m_left    */
+	0x0F120238, /* 0269 awbb_OutdoorGrZones_m_BGrid_8__m_right   */
+	0x0F120000, /* 01E2 awbb_OutdoorGrZones_m_BGrid_9__m_left    */
+	0x0F120000, /* 0263 awbb_OutdoorGrZones_m_BGrid_9__m_right   */
+	0x0F120000, /* 01E0 awbb_OutdoorGrZones_m_BGrid_10__m_left   */
+	0x0F120000, /* 025A awbb_OutdoorGrZones_m_BGrid_10__m_right  */
+	0x0F120000, /* 01E1 awbb_OutdoorGrZones_m_BGrid_11__m_left   */
+	0x0F120000, /* 0256 awbb_OutdoorGrZones_m_BGrid_11__m_right  */
+	0x0F120000, /* 01EE awbb_OutdoorGrZones_m_BGrid_12__m_left   */
+	0x0F120000, /* 0251 awbb_OutdoorGrZones_m_BGrid_12__m_right  */
+	0x0F120000, /* 01F8 awbb_OutdoorGrZones_m_BGrid(26)          */
+	0x0F120000, /* 024A awbb_OutdoorGrZones_m_BGrid(27)          */
+	0x0F120000, /* 020D awbb_OutdoorGrZones_m_BGrid(28)          */
+	0x0F120000, /* 0231 awbb_OutdoorGrZones_m_BGrid(29)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(30)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(31)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(32)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(33)          */
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/*  7-3. Low Br grey zone                     */
+	/* param_  C4start	awbb_LowBrGrZones_m_BGrid */
+	
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120020, /* awbb_GridCorr_R_0__4_ */
+	0x0F120060, /* awbb_GridCorr_R_0__5_ */
+	
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120020, /* awbb_GridCorr_R_1__4_ */
+	0x0F120060, /* awbb_GridCorr_R_1__5_ */
+	
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120020, /* awbb_GridCorr_R_2__4_ */
+	0x0F120060, /* awbb_GridCorr_R_2__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+	
+	0x0F1202C6,
+	0x0F120335,
+	0x0F1203B3,
+	0x0F121021,
+	0x0F12107E,
+	0x0F12113E,
+	0x0F12117C,
+	0x0F1211C2,
+	0x0F12120B,
+	
+	0x0F1200B3,
+	0x0F1200B7,
+	0x0F1200D3,
+	0x0F120091,
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+	
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* CCM */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+	
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+	
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+	
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /*afit_bUseNoiseInd 0 : NB 1: Noise Index */
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+	
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120010, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120008, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F1200FF,
+	0x0F1200FF,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120300,
+	0x0F120002,
+	0x0F120400,
+	0x0F120106,
+	0x0F120005,
+	0x0F120000,
+	0x0F120703,
+	0x0F120000,
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Recording 25fps Anti-Flicker 60Hz END of Initial */
+};
+
+/* Recording with 25fps */
+static const u32 s5k5bafx_recording_50Hz_common[] = {
+
+	/* recording 25fps Anti-Flicker 50Hz*/
+	
+	0xFCFCD000,
+	
+	/* ARM Go */
+	0x0028D000,
+	0x002A1030,
+	0x0F120000,
+	0x002A0014,
+	0x0F120001,
+	0xffff0064, /* p100	Delay */
+	
+	
+	/* Trap and Patch  2008-11-18 10:15:41 */
+	0x00287000,
+	0x002A1668,
+	0x0F12B5FE,
+	0x0F120007,
+	0x0F12683C,
+	0x0F12687E,
+	0x0F121DA5,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D00B,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D008,
+	0x0F128820,
+	0x0F128829,
+	0x0F124288,
+	0x0F12D301,
+	0x0F121A40,
+	0x0F12E000,
+	0x0F121A08,
+	0x0F129001,
+	0x0F12E001,
+	0x0F122019,
+	0x0F129001,
+	0x0F124916,
+	0x0F12466B,
+	0x0F128A48,
+	0x0F128118,
+	0x0F128A88,
+	0x0F128158,
+	0x0F124814,
+	0x0F128940,
+	0x0F120040,
+	0x0F122103,
+	0x0F12F000,
+	0x0F12F826,
+	0x0F1288A1,
+	0x0F124288,
+	0x0F12D908,
+	0x0F128828,
+	0x0F128030,
+	0x0F128868,
+	0x0F128070,
+	0x0F1288A8,
+	0x0F126038,
+	0x0F12BCFE,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F1288A9,
+	0x0F124288,
+	0x0F12D906,
+	0x0F128820,
+	0x0F128030,
+	0x0F128860,
+	0x0F128070,
+	0x0F1288A0,
+	0x0F126038,
+	0x0F12E7F2,
+	0x0F129801,
+	0x0F12A902,
+	0x0F12F000,
+	0x0F12F812,
+	0x0F120033,
+	0x0F120029,
+	0x0F129A02,
+	0x0F120020,
+	0x0F12F000,
+	0x0F12F814,
+	0x0F126038,
+	0x0F12E7E6,
+	0x0F121A28,
+	0x0F127000,
+	0x0F120D64,
+	0x0F127000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F126009,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12622F,
+	0x0F120000,
+	0x002A2080,
+	0x0F12B510,
+	0x0F12F000,
+	0x0F12F8F4,
+	0x0F12BC10,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F0,
+	0x0F12B08B,
+	0x0F120006,
+	0x0F122000,
+	0x0F129004,
+	0x0F126835,
+	0x0F126874,
+	0x0F1268B0,
+	0x0F12900A,
+	0x0F1268F0,
+	0x0F129009,
+	0x0F124F7D,
+	0x0F128979,
+	0x0F12084A,
+	0x0F1288A8,
+	0x0F1288A3,
+	0x0F124298,
+	0x0F12D300,
+	0x0F120018,
+	0x0F12F000,
+	0x0F12F907,
+	0x0F129007,
+	0x0F120021,
+	0x0F120028,
+	0x0F12AA04,
+	0x0F12F000,
+	0x0F12F909,
+	0x0F129006,
+	0x0F1288A8,
+	0x0F122800,
+	0x0F12D102,
+	0x0F1227FF,
+	0x0F121C7F,
+	0x0F12E047,
+	0x0F1288A0,
+	0x0F122800,
+	0x0F12D101,
+	0x0F122700,
+	0x0F12E042,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12F000,
+	0x0F12F8F8,
+	0x0F129008,
+	0x0F128ABA,
+	0x0F129808,
+	0x0F12466B,
+	0x0F124342,
+	0x0F129202,
+	0x0F128820,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8EA,
+	0x0F129A02,
+	0x0F1217D1,
+	0x0F120E09,
+	0x0F121889,
+	0x0F121209,
+	0x0F124288,
+	0x0F12DD1F,
+	0x0F128820,
+	0x0F12466B,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F12980A,
+	0x0F129903,
+	0x0F12F000,
+	0x0F12F8DA,
+	0x0F129001,
+	0x0F128828,
+	0x0F12466B,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12980A,
+	0x0F129902,
+	0x0F12F000,
+	0x0F12F8D0,
+	0x0F128AB9,
+	0x0F129A08,
+	0x0F124351,
+	0x0F1217CA,
+	0x0F120E12,
+	0x0F121851,
+	0x0F12120A,
+	0x0F129901,
+	0x0F12F000,
+	0x0F12F8B6,
+	0x0F120407,
+	0x0F120C3F,
+	0x0F12E000,
+	0x0F122700,
+	0x0F128820,
+	0x0F12466B,
+	0x0F12AA05,
+	0x0F128198,
+	0x0F128860,
+	0x0F1281D8,
+	0x0F128828,
+	0x0F128118,
+	0x0F128868,
+	0x0F128158,
+	0x0F12A802,
+	0x0F12C803,
+	0x0F12003B,
+	0x0F12F000,
+	0x0F12F8BB,
+	0x0F1288A1,
+	0x0F1288A8,
+	0x0F12003A,
+	0x0F12F000,
+	0x0F12F8BE,
+	0x0F120004,
+	0x0F12A804,
+	0x0F12C803,
+	0x0F129A09,
+	0x0F129B07,
+	0x0F12F000,
+	0x0F12F8AF,
+	0x0F12A806,
+	0x0F12C805,
+	0x0F120021,
+	0x0F12F000,
+	0x0F12F8B2,
+	0x0F126030,
+	0x0F12B00B,
+	0x0F12BCF0,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F12B5F1,
+	0x0F129900,
+	0x0F12680C,
+	0x0F12493A,
+	0x0F12694B,
+	0x0F12698A,
+	0x0F124694,
+	0x0F1269CD,
+	0x0F126A0E,
+	0x0F124F38,
+	0x0F1242BC,
+	0x0F12D800,
+	0x0F120027,
+	0x0F124937,
+	0x0F126B89,
+	0x0F120409,
+	0x0F120C09,
+	0x0F124A35,
+	0x0F121E92,
+	0x0F126BD2,
+	0x0F120412,
+	0x0F120C12,
+	0x0F12429F,
+	0x0F12D801,
+	0x0F120020,
+	0x0F12E031,
+	0x0F12001F,
+	0x0F12434F,
+	0x0F120A3F,
+	0x0F1242A7,
+	0x0F12D301,
+	0x0F120018,
+	0x0F12E02A,
+	0x0F12002B,
+	0x0F12434B,
+	0x0F120A1B,
+	0x0F1242A3,
+	0x0F12D303,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F88C,
+	0x0F12E021,
+	0x0F120029,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D301,
+	0x0F120028,
+	0x0F12E01A,
+	0x0F120031,
+	0x0F124351,
+	0x0F120A09,
+	0x0F1242A1,
+	0x0F12D304,
+	0x0F120220,
+	0x0F120011,
+	0x0F12F000,
+	0x0F12F87B,
+	0x0F12E010,
+	0x0F12491E,
+	0x0F128C89,
+	0x0F12000A,
+	0x0F124372,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D301,
+	0x0F120030,
+	0x0F12E007,
+	0x0F124662,
+	0x0F12434A,
+	0x0F120A12,
+	0x0F1242A2,
+	0x0F12D302,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F869,
+	0x0F124B16,
+	0x0F124D18,
+	0x0F128D99,
+	0x0F121FCA,
+	0x0F123AF9,
+	0x0F12D00A,
+	0x0F122001,
+	0x0F120240,
+	0x0F128468,
+	0x0F120220,
+	0x0F12F000,
+	0x0F12F85D,
+	0x0F129900,
+	0x0F126008,
+	0x0F12BCF8,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F128D19,
+	0x0F128469,
+	0x0F129900,
+	0x0F126008,
+	0x0F12E7F7,
+	0x0F12B570,
+	0x0F122200,
+	0x0F12490E,
+	0x0F12480E,
+	0x0F122401,
+	0x0F12F000,
+	0x0F12F852,
+	0x0F120022,
+	0x0F12490D,
+	0x0F12480D,
+	0x0F122502,
+	0x0F12F000,
+	0x0F12F84C,
+	0x0F12490C,
+	0x0F12480D,
+	0x0F12002A,
+	0x0F12F000,
+	0x0F12F847,
+	0x0F12BC70,
+	0x0F12BC08,
+	0x0F124718,
+	0x0F120D64,
+	0x0F127000,
+	0x0F120470,
+	0x0F127000,
+	0x0F12A120,
+	0x0F120007,
+	0x0F120402,
+	0x0F127000,
+	0x0F1214A0,
+	0x0F127000,
+	0x0F12208D,
+	0x0F127000,
+	0x0F12622F,
+	0x0F120000,
+	0x0F121669,
+	0x0F127000,
+	0x0F126445,
+	0x0F120000,
+	0x0F1221AB,
+	0x0F127000,
+	0x0F122AA9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125F49,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FC7,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125457,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F125FA3,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F1251F9,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12F004,
+	0x0F12E51F,
+	0x0F12A464,
+	0x0F120000,
+	0x0F124778,
+	0x0F1246C0,
+	0x0F12C000,
+	0x0F12E59F,
+	0x0F12FF1C,
+	0x0F12E12F,
+	0x0F12A007,
+	0x0F120000,
+	0x0F126546,
+	0x0F122062,
+	0x0F123120,
+	0x0F123220,
+	0x0F123130,
+	0x0F120030,
+	0x0F12E010,
+	0x0F120208,
+	0x0F120058,
+	0x0F120000,
+	/* End of Trap and Patch (Last : 70002342h) */
+	/* Total Size 896 (0x0380)                  */
+	
+	
+	0x0028D000,
+	0x002A1000,
+	0x0F120001,
+	
+	
+	0x00287000,
+	0x002A1662,
+	0x0F1203B0,
+	0x0F1203B0,
+	
+	
+	0x00287000,
+	0x002A1658,
+	0x0F129C40,
+	0x0F120000,
+	0x0F129C40,
+	0x0F120000,
+	
+	
+	0x00287000,
+	0x002A0ADC,
+	0x0F120AF0, /* setot_uOnlineClocksDiv40             */
+	0x002A0AE2,
+	0x0F12222E, /* setot_usSetRomWaitStateThreshold4KHz */
+	
+	0x002A0B94,
+	0x0F120580, /* awbb_GainsInit_0_:R       */
+	0x0F120400, /* awbb_GainsInit_1_:G       */
+	0x0F1205F0, /* awbb_GainsInit_2_:B       */
+	0x002A04A0,
+	0x0F128000, /* lt_uLeiInit:AE start      */
+	0x002A049A,
+	0x0F1200FA, /* lt_uMinExp   0.5ms·Î º¯°æ */
+	
+	
+	/* Set CIS/APS/Analog */
+	0x0028D000,
+	0x002AF106,
+	0x0F120001,
+	0x002AF206,
+	0x0F120001,
+	
+	
+	0x002AC202,
+	0x0F120700,
+	
+	0x002AF260,
+	0x0F120001,
+	
+	0x002AF414,
+	0x0F120030,
+	
+	0x002AC204,
+	0x0F120100,
+	0x002AF402,
+	0x0F120092,
+	0x0F12007F,
+	
+	0x002AF700,
+	0x0F120040,
+	0x002AF708,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120040,
+	0x0F120001,
+	0x0F120015,
+	0x0F120001,
+	0x0F120040,
+	
+	0x002AF48A,
+	0x0F120048,
+	0x002AF10A,
+	0x0F12008B,
+	
+	
+	0x002AF900,
+	0x0F120067,
+	
+	
+	0x002AF406,
+	0x0F120092,
+	0x0F12007F,
+	0x0F120003,
+	
+	0x0F120003,
+	0x0F120003,
+	0x002AF442,
+	0x0F120000,
+	0x0F120000,
+	0x002AF448,
+	0x0F120000,
+	0x002AF456,
+	0x0F120001,
+	0x0F120010,
+	0x0F120000,
+	
+	0x002AF41A,
+	0x0F1200FF,
+	0x0F120003,
+	
+	0x002AF420,
+	0x0F120030,
+	0x002AF410,
+	0x0F120001,
+	
+	0x0F120000,
+	0x002AF416,
+	0x0F120001,
+	0x002AF424,
+	0x0F120000,
+	0x002AF422,
+	0x0F120000,
+	
+	0x002AF41E,
+	0x0F120000,
+	0x002AF428,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x002AF430,
+	0x0F120000,
+	0x0F120000,
+	
+	0x0F120008,
+	0x0F120005,
+	0x0F12000F,
+	0x0F120001,
+	0x0F120040,
+	0x0F120040,
+	0x0F120010,
+	
+	0x002AF4D6,
+	0x0F120090,
+	
+	
+	0x0F120000,
+	
+	0x002AF47C,
+	0x0F12000C,
+	0x0F120000,
+	0x002AF49A,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4A2,
+	0x0F120008,
+	0x0F120000,
+	0x002AF4B2,
+	0x0F120013,
+	0x0F120000,
+	0x0F120013,
+	0x0F120000,
+	0x002AF4AA,
+	0x0F12009B,
+	0x0F1200FB,
+	0x0F12009B,
+	0x0F1200FB,
+	0x002AF474,
+	0x0F120017,
+	0x0F12005F,
+	0x0F120017,
+	0x0F12008F,
+	
+	0x002AF48C,
+	0x0F120017,
+	0x0F12009B,
+	0x002AF4C8,
+	0x0F120163,
+	0x0F120193,
+	0x002AF490,
+	0x0F120191,
+	
+	0x002AF418,
+	0x0F120083,
+	
+	0x002AF454,
+	0x0F120001,
+	
+	0x002AF702,
+	0x0F120081,
+	0x002AF4D2,
+	0x0F120000,
+	
+	/* For ESD Check */
+	0x00287000,
+	0x002A0132,
+	0x0F12AAAA,
+	
+	/* Set FPN Gain Input */
+	0x002A1176,
+	0x0F120020,
+	0x0F120040,
+	0x0F120080,
+	0x0F120100,
+	0x0F120014,
+	0x0F12000A,
+	0x0F120008,
+	0x0F120004,
+	
+	/* CFPN Canceller */
+	0x002A116C,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120002,
+	0x002A0AE8,
+	0x0F120000,
+	
+	/* sensor aig table setting */
+	0x002A10EE,
+	0x0F120000,
+	0x002A10F2,
+	0x0F120000,
+	0x002A1152,
+	0x0F120030,
+	0x0F120028,
+	0x0F120030,
+	0x002A1148,
+	0x0F1200FB,
+	0x002A1144,
+	0x0F1200FB,
+	0x002A1150,
+	0x0F1201F4,
+	
+	
+	0x002A1084,
+	0x0F120000,
+	0x0F120000,
+	
+	/* Set AE Target */
+	0x002A0F4C,
+	0x0F12003A, /* TVAR_ae_BrAve */
+	
+	0x002A0478,
+	0x0F120114,
+	0x0F1200EB, /* ae boundary */
+	
+	
+	
+	/* Set Frame Rate */
+	0x002A0484,
+	0x0F12410A, /* uMaxExp1 */
+	0x0F120000,
+	0x002A048C,
+	0x0F128214, /* uMaxExp2 */
+	0x0F120000,
+	0x0F12A122, /* uMaxExp3 */
+	0x0F120000,
+	0x002A0488,
+	0x0F12f424, /* uMaxExp4 */
+	0x0F120000,
+	0x002A043A,
+	0x0F1201D0, /* lt_uMaxAnGain0   */
+	0x0F1201E0, /* lt_uMaxAnGain0_1 */
+	0x002A0494,
+	0x0F120300, /* lt_uMaxAnGain1 */
+	0x0F120650, /* lt_uMaxAnGain2 */
+	0x0f120100,
+	0x002A0F52,
+	0x0F12000F, /* ae_StatMode */
+	
+	0x002A0E98, /* bp_uMaxBrightnessFactor */
+	0x0F1202A8,
+	0x002A0E9E, /* bp_uMinBrightnessFactor */
+	0x0F120298,
+	
+	/* 1. Auto Flicker 50Hz Start */
+	0x002A0B2E,
+	0x0F120000, /* AFC_Default60Hz	 Auto Flicker 60Hz start 0: Auto Flicker 50Hz start */
+	0x002A03F8,
+	0x0F12005F, /* REG_TC_DBG_AutoAlgEnBits   default : 007F */
+	
+	
+	0xffff000a, /* p10	Wait10mSec */
+	
+	/* Set PLL */
+	/* External CLOCK (MCLK) */
+	0x002A01B8,
+	0x0F125DC0, /* REG_TC_IPRM_InClockLSBs */
+	0x0F120000, /* REG_TC_IPRM_InClockMSBs */
+	
+	/* Parallel or MIPI Selection */
+	0x002A01C6,
+	0x0F120001, /* REG_TC_IPRM_UseNPviClocks         */
+	0x0F120001, /* REG_TC_IPRM_UseNMipiClocks        */
+	0x0F120000, /* REG_TC_IPRM_bBlockInternalPllCalc */
+	
+	/* System Clock 0 (System : 24Mhz, PCLK : 48Mhz) */
+	0x002A01CC,
+	0x0F121770, /* REG_TC_IPRM_OpClk4KHz_0      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_0 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_0 */
+	
+	/* System Clock 1 (System : 48Mhz, PCLK : 48Mhz) */
+	0x002A01D2,                
+	0x0F122EE0, /* REG_TC_IPRM_OpClk4KHz_1      */
+	0x0F122EE0, /* REG_TC_IPRM_MinOutRate4KHz_1 */
+	0x0F122EE0, /* REG_TC_IPRM_MaxOutRate4KHz_1 */
+	
+	
+	
+	0x002A01DE,
+	0x0F120001, /* REG_TC_IPRM_UseRegsAPI        */
+	0x0F120001, /* REG_TC_IPRM_InitParamsUpdated */
+	0xffff0064, /* p100                          */
+	
+	
+	
+	/* Crop */
+	0x002A01FA,
+	0x0F120640, /* REG_TC_GP_PrevReqInputWidth  */
+	0x0F1204B0, /* REG_TC_GP_PrevReqInputHeight */
+	0x0F120000, /* REG_TC_GP_PrevInputWidthOfs  */
+	0x0F120000, /* REG_TC_GP_PrevInputHeightOfs */
+	
+	
+	/* Set Preview Config */
+	/* Preview Config 0 (VGA fixed 30fps) */
+	0x002A0242,
+	0x0F120280, /* REG_0TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_0TC_PCFG_usHeight               */
+	0x0F120005, /* REG_0TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_0TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_0TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_0TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_0TC_PCFG_uClockInd              */
+	0x0F120002, /* REG_0TC_PCFG_usFrTimeType           */
+	0x0F120001, /* REG_0TC_PCFG_FrRateQualityType      */
+	0x0F12018c, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12018c, /* REG_0TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_0TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_0TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_0TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_0TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_0TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_0TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_0TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_0TC_PCFG_uRotation              */
+	
+	/* Preview Config 1 (640x480, Not Fixed 15 ~ 30fps) */
+	0x002A0268,
+	0x0F120280, /* REG_1TC_PCFG_usWidth                */
+	0x0F1201E0, /* REG_1TC_PCFG_usHeight               */
+	0x0F120005, /* REG_1TC_PCFG_Format                 */
+	0x0F122EE0, /* REG_1TC_PCFG_usMaxOut4KHzRate       */
+	0x0F122EE0, /* REG_1TC_PCFG_usMinOut4KHzRate       */
+	0x0F120052, /* REG_1TC_PCFG_PVIMask                */
+	0x0F120001, /* REG_1TC_PCFG_uClockInd              */
+	0x0F120000, /* REG_1TC_PCFG_usFrTimeType           */
+	0x0F120000, /* REG_1TC_PCFG_FrRateQualityType      */
+	0x0F12029A, /* REG_1TC_PCFG_usMaxFrTimeMsecMult10  */
+	0x0F12014D, /* REG_1TC_PCFG_usMinFrTimeMsecMult10  */
+	0x0F120000, /* REG_1TC_PCFG_sSaturation            */
+	0x0F120000, /* REG_1TC_PCFG_sSharpBlur             */
+	0x0F120000, /* REG_1TC_PCFG_sGlamour               */
+	0x0F120000, /* REG_1TC_PCFG_sColorTemp             */
+	0x0F120000, /* REG_1TC_PCFG_uDeviceGammaIndex      */
+	0x0F120000, /* REG_1TC_PCFG_uPrevMirror            */
+	0x0F120000, /* REG_1TC_PCFG_uCaptureMirror         */
+	0x0F120000, /* REG_1TC_PCFG_uRotation              */
+	
+	
+	/* Set MIPI */
+	0x002A03AC,
+	0x0F120000, /* REG_TC_FLS_Mode        */
+	0x002A03F2,
+	0x0F120001, /* REG_TC_OIF_EnMipiLanes */
+	0x0F1200C3, /* REG_TC_OIF_EnPackets   */
+	0x0F120001, /* REG_TC_OIF_CfgChanged  */
+	
+	/* Apply preview config */
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+	
+	
+	
+	/* Set Capture Config */
+	/* Capture Config 0 (1600x1200 fixed 8fps) */
+	0x002A0302,
+	0x0F120000, /* REG_0TC_CCFG_uCaptureMode          */
+	0x0F120640, /* REG_0TC_CCFG_usWidth               */
+	0x0F1204B0, /* REG_0TC_CCFG_usHeight              */
+	0x0F120005, /* REG_0TC_CCFG_Format                */
+	0x0F122EE0, /* REG_0TC_CCFG_usMaxOut4KHzRate      */
+	0x0F122EE0, /* REG_0TC_CCFG_usMinOut4KHzRate      */
+	0x0F120052, /* REG_0TC_CCFG_PVIMask               */
+	0x0F120001, /* REG_0TC_CCFG_uClockInd             */
+	0x0F120002, /* REG_0TC_CCFG_usFrTimeType          */
+	0x0F120002, /* REG_0TC_CCFG_FrRateQualityType     */
+	0x0F1204E2, /* REG_0TC_CCFG_usMaxFrTimeMsecMult10 */
+	0x0F1204E2, /* REG_0TC_CCFG_usMinFrTimeMsecMult10 */
+	0x0F120000, /* REG_0TC_CCFG_sSaturation           */
+	0x0F120000, /* REG_0TC_CCFG_sSharpBlur            */
+	0x0F120000, /* REG_0TC_CCFG_sGlamour              */
+	0x0F120000, /* REG_0TC_CCFG_sColorTemp            */
+	0x0F120000, /* REG_0TC_CCFG_uDeviceGammaIndex     */
+	
+	
+	
+	/* Periodic mismatch */
+	0x002A0780,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A0798,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	
+	0x002A07C0,
+	0x0F120004,
+	0x0F120004,
+	
+	0x002A0B94,
+	0x0F120580,
+	0x0F120400,
+	0x0F1205F0,
+	0x002A04A0,
+	0x0F128000,
+	
+	
+	/* Set AE Weights */
+	0x002A0F5A,
+	0x0F120000, /* ae_WeightTbl_16_0_ */
+	0x0F120000, /* ae_WeightTbl_16_1_ */
+	0x0F120000, /* ae_WeightTbl_16_2_ */
+	0x0F120000, /* ae_WeightTbl_16_3_ */
+	0x0F120101, /* ae_WeightTbl_16_4_ */
+	0x0F120101, /* ae_WeightTbl_16_5_ */
+	0x0F120101, /* ae_WeightTbl_16_6_ */
+	0x0F120101, /* ae_WeightTbl_16_7_ */
+	0x0F120101, /* ae_WeightTbl_16_8_ */
+	0x0F120302, /* ae_WeightTbl_16_9_ */
+	0x0F120203, /* ae_WeightTbl_16_10 */
+	0x0F120101, /* ae_WeightTbl_16_11 */
+	0x0F120101, /* ae_WeightTbl_16_12 */
+	0x0F120403, /* ae_WeightTbl_16_13 */
+	0x0F120304, /* ae_WeightTbl_16_14 */
+	0x0F120101, /* ae_WeightTbl_16_15 */
+	0x0F120101, /* ae_WeightTbl_16_16 */
+	0x0F120403, /* ae_WeightTbl_16_17 */
+	0x0F120304, /* ae_WeightTbl_16_18 */
+	0x0F120101, /* ae_WeightTbl_16_19 */
+	0x0F120101, /* ae_WeightTbl_16_20 */
+	0x0F120302, /* ae_WeightTbl_16_21 */
+	0x0F120203, /* ae_WeightTbl_16_22 */
+	0x0F120101, /* ae_WeightTbl_16_23 */
+	0x0F120101, /* ae_WeightTbl_16_24 */
+	0x0F120101, /* ae_WeightTbl_16_25 */
+	0x0F120101, /* ae_WeightTbl_16_26 */
+	0x0F120101, /* ae_WeightTbl_16_27 */
+	0x0F120000, /* ae_WeightTbl_16_28 */
+	0x0F120000, /* ae_WeightTbl_16_29 */
+	0x0F120000, /* ae_WeightTbl_16_30 */
+	0x0F120000, /* ae_WeightTbl_16_31 */
+	
+	
+	/* Set GAS & CCM White Point */
+	/* param_start	TVAR_ash_AwbAshCord */
+	0x002A0704,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F1201B0,
+	0x0F120200,
+	
+	/* param_start	wbt_AwbCcmCord */
+	0x002A06F2,
+	0x0F1200B3,
+	0x0F1200E5,
+	0x0F120120,
+	0x0F120136,
+	0x0F120180,
+	0x0F120190,
+	
+	/* Target Brightness Control */
+	0x002A103E,
+	0x0F120000,
+	0x0F120009,
+	0x0F120018,
+	0x0F120032,
+	0x0F12004A,
+	0x0F120051,
+	0x0F120056,
+	0x0F12010C,
+	0x0F12010C,
+	0x0F120109,
+	0x0F120105,
+	0x0F120102,
+	0x0F1200FB,
+	0x0F1200F8,
+	
+	/* TVAR_ash_GASAlpha(Indoor) */
+	0x002A0712,
+	0x0F120100, /* TVAR_ash_GASAlpha[0]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[1]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[2]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[3]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[4]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[5]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[6]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[7]  */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[8]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[9]  */
+	0x0F120100, /* TVAR_ash_GASAlpha[10] */
+	0x0F120100, /* TVAR_ash_GASAlpha[11] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[12] */
+	0x0F120100, /* TVAR_ash_GASAlpha[13] */
+	0x0F120100, /* TVAR_ash_GASAlpha[14] */
+	0x0F120100, /* TVAR_ash_GASAlpha[15] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[16] */
+	0x0F120100, /* TVAR_ash_GASAlpha[17] */
+	0x0F120100, /* TVAR_ash_GASAlpha[18] */
+	0x0F120100, /* TVAR_ash_GASAlpha[19] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[20] */
+	0x0F120100, /* TVAR_ash_GASAlpha[21] */
+	0x0F120100, /* TVAR_ash_GASAlpha[22] */
+	0x0F120100, /* TVAR_ash_GASAlpha[23] */
+	
+	0x0F120100, /* TVAR_ash_GASAlpha[24] */
+	0x0F120100, /* TVAR_ash_GASAlpha[25] */
+	0x0F120100, /* TVAR_ash_GASAlpha[26] */
+	0x0F120100, /* TVAR_ash_GASAlpha[27] */
+	
+	/* TVAR_ash_GASAlpha(Outdoor) */
+	0x0F120108, /* 100 TVAR_ash_GASOutdoorAlpha_0_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_1_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_2_*/
+	0x0F120100, /* TVAR_ash_GASOutdoorAlpha_3_*/
+	
+	/* GAS LUT Start Address */
+	0x002A0754,
+	0x0F122388,
+	0x0F127000,
+	
+	/* param_start	TVAR_ash_pGAS */
+	0x002A2388,
+	0x0F120160, /* TVAR_ash_pGAS[0]   */
+	0x0F120134, /* TVAR_ash_pGAS[1]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[2]   */
+	0x0F1200D1, /* TVAR_ash_pGAS[3]   */
+	0x0F1200B1, /* TVAR_ash_pGAS[4]   */
+	0x0F12009D, /* TVAR_ash_pGAS[5]   */
+	0x0F120096, /* TVAR_ash_pGAS[6]   */
+	0x0F12009E, /* TVAR_ash_pGAS[7]   */
+	0x0F1200B3, /* TVAR_ash_pGAS[8]   */
+	0x0F1200D3, /* TVAR_ash_pGAS[9]   */
+	0x0F1200FF, /* TVAR_ash_pGAS[10]  */
+	0x0F120131, /* TVAR_ash_pGAS[11]  */
+	0x0F120159, /* TVAR_ash_pGAS[12]  */
+	0x0F12013C, /* TVAR_ash_pGAS[13]  */
+	0x0F120107, /* TVAR_ash_pGAS[14]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[15]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[16]  */
+	0x0F120080, /* TVAR_ash_pGAS[17]  */
+	0x0F12006B, /* TVAR_ash_pGAS[18]  */
+	0x0F120064, /* TVAR_ash_pGAS[19]  */
+	0x0F12006C, /* TVAR_ash_pGAS[20]  */
+	0x0F120080, /* TVAR_ash_pGAS[21]  */
+	0x0F1200A1, /* TVAR_ash_pGAS[22]  */
+	0x0F1200CD, /* TVAR_ash_pGAS[23]  */
+	0x0F120106, /* TVAR_ash_pGAS[24]  */
+	0x0F120139, /* TVAR_ash_pGAS[25]  */
+	0x0F120116, /* TVAR_ash_pGAS[26]  */
+	0x0F1200DC, /* TVAR_ash_pGAS[27]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[28]  */
+	0x0F120073, /* TVAR_ash_pGAS[29]  */
+	0x0F120051, /* TVAR_ash_pGAS[30]  */
+	0x0F12003B, /* TVAR_ash_pGAS[31]  */
+	0x0F120033, /* TVAR_ash_pGAS[32]  */
+	0x0F12003B, /* TVAR_ash_pGAS[33]  */
+	0x0F120050, /* TVAR_ash_pGAS[34]  */
+	0x0F120073, /* TVAR_ash_pGAS[35]  */
+	0x0F1200A2, /* TVAR_ash_pGAS[36]  */
+	0x0F1200DD, /* TVAR_ash_pGAS[37]  */
+	0x0F120115, /* TVAR_ash_pGAS[38]  */
+	0x0F1200FA, /* TVAR_ash_pGAS[39]  */
+	0x0F1200BF, /* TVAR_ash_pGAS[40]  */
+	0x0F120085, /* TVAR_ash_pGAS[41]  */
+	0x0F120055, /* TVAR_ash_pGAS[42]  */
+	0x0F120031, /* TVAR_ash_pGAS[43]  */
+	0x0F12001B, /* TVAR_ash_pGAS[44]  */
+	0x0F120014, /* TVAR_ash_pGAS[45]  */
+	0x0F12001A, /* TVAR_ash_pGAS[46]  */
+	0x0F120031, /* TVAR_ash_pGAS[47]  */
+	0x0F120055, /* TVAR_ash_pGAS[48]  */
+	0x0F120085, /* TVAR_ash_pGAS[49]  */
+	0x0F1200C0, /* TVAR_ash_pGAS[50]  */
+	0x0F1200FB, /* TVAR_ash_pGAS[51]  */
+	0x0F1200EA, /* TVAR_ash_pGAS[52]  */
+	0x0F1200AF, /* TVAR_ash_pGAS[53]  */
+	0x0F120074, /* TVAR_ash_pGAS[54]  */
+	0x0F120045, /* TVAR_ash_pGAS[55]  */
+	0x0F120020, /* TVAR_ash_pGAS[56]  */
+	0x0F12000B, /* TVAR_ash_pGAS[57]  */
+	0x0F120003, /* TVAR_ash_pGAS[58]  */
+	0x0F12000A, /* TVAR_ash_pGAS[59]  */
+	0x0F120020, /* TVAR_ash_pGAS[60]  */
+	0x0F120046, /* TVAR_ash_pGAS[61]  */
+	0x0F120076, /* TVAR_ash_pGAS[62]  */
+	0x0F1200B1, /* TVAR_ash_pGAS[63]  */
+	0x0F1200ED, /* TVAR_ash_pGAS[64]  */
+	0x0F1200E6, /* TVAR_ash_pGAS[65]  */
+	0x0F1200AA, /* TVAR_ash_pGAS[66]  */
+	0x0F120071, /* TVAR_ash_pGAS[67]  */
+	0x0F120041, /* TVAR_ash_pGAS[68]  */
+	0x0F12001D, /* TVAR_ash_pGAS[69]  */
+	0x0F120008, /* TVAR_ash_pGAS[70]  */
+	0x0F120000, /* TVAR_ash_pGAS[71]  */
+	0x0F120007, /* TVAR_ash_pGAS[72]  */
+	0x0F12001E, /* TVAR_ash_pGAS[73]  */
+	0x0F120044, /* TVAR_ash_pGAS[74]  */
+	0x0F120074, /* TVAR_ash_pGAS[75]  */
+	0x0F1200B0, /* TVAR_ash_pGAS[76]  */
+	0x0F1200EC, /* TVAR_ash_pGAS[77]  */
+	0x0F1200EF, /* TVAR_ash_pGAS[78]  */
+	0x0F1200B3, /* TVAR_ash_pGAS[79]  */
+	0x0F12007A, /* TVAR_ash_pGAS[80]  */
+	0x0F12004A, /* TVAR_ash_pGAS[81]  */
+	0x0F120026, /* TVAR_ash_pGAS[82]  */
+	0x0F120011, /* TVAR_ash_pGAS[83]  */
+	0x0F12000A, /* TVAR_ash_pGAS[84]  */
+	0x0F120011, /* TVAR_ash_pGAS[85]  */
+	0x0F120029, /* TVAR_ash_pGAS[86]  */
+	0x0F12004F, /* TVAR_ash_pGAS[87]  */
+	0x0F120080, /* TVAR_ash_pGAS[88]  */
+	0x0F1200BC, /* TVAR_ash_pGAS[89]  */
+	0x0F1200F8, /* TVAR_ash_pGAS[90]  */
+	0x0F120105, /* TVAR_ash_pGAS[91]  */
+	0x0F1200C9, /* TVAR_ash_pGAS[92]  */
+	0x0F12008F, /* TVAR_ash_pGAS[93]  */
+	0x0F120060, /* TVAR_ash_pGAS[94]  */
+	0x0F12003C, /* TVAR_ash_pGAS[95]  */
+	0x0F120026, /* TVAR_ash_pGAS[96]  */
+	0x0F12001F, /* TVAR_ash_pGAS[97]  */
+	0x0F120028, /* TVAR_ash_pGAS[98]  */
+	0x0F120040, /* TVAR_ash_pGAS[99]  */
+	0x0F120066, /* TVAR_ash_pGAS[100] */
+	0x0F120097, /* TVAR_ash_pGAS[101] */
+	0x0F1200D4, /* TVAR_ash_pGAS[102] */
+	0x0F120110, /* TVAR_ash_pGAS[103] */
+	0x0F120124, /* TVAR_ash_pGAS[104] */
+	0x0F1200EB, /* TVAR_ash_pGAS[105] */
+	0x0F1200B1, /* TVAR_ash_pGAS[106] */
+	0x0F120082, /* TVAR_ash_pGAS[107] */
+	0x0F12005F, /* TVAR_ash_pGAS[108] */
+	0x0F12004A, /* TVAR_ash_pGAS[109] */
+	0x0F120043, /* TVAR_ash_pGAS[110] */
+	0x0F12004C, /* TVAR_ash_pGAS[111] */
+	0x0F120064, /* TVAR_ash_pGAS[112] */
+	0x0F120089, /* TVAR_ash_pGAS[113] */
+	0x0F1200BA, /* TVAR_ash_pGAS[114] */
+	0x0F1200F8, /* TVAR_ash_pGAS[115] */
+	0x0F12012F, /* TVAR_ash_pGAS[116] */
+	0x0F120147, /* TVAR_ash_pGAS[117] */
+	0x0F120116, /* TVAR_ash_pGAS[118] */
+	0x0F1200DE, /* TVAR_ash_pGAS[119] */
+	0x0F1200AF, /* TVAR_ash_pGAS[120] */
+	0x0F12008E, /* TVAR_ash_pGAS[121] */
+	0x0F12007A, /* TVAR_ash_pGAS[122] */
+	0x0F120072, /* TVAR_ash_pGAS[123] */
+	0x0F12007A, /* TVAR_ash_pGAS[124] */
+	0x0F120091, /* TVAR_ash_pGAS[125] */
+	0x0F1200B6, /* TVAR_ash_pGAS[126] */
+	0x0F1200E8, /* TVAR_ash_pGAS[127] */
+	0x0F120121, /* TVAR_ash_pGAS[128] */
+	0x0F120150, /* TVAR_ash_pGAS[129] */
+	0x0F120170, /* TVAR_ash_pGAS[130] */
+	0x0F12013F, /* TVAR_ash_pGAS[131] */
+	0x0F120110, /* TVAR_ash_pGAS[132] */
+	0x0F1200E2, /* TVAR_ash_pGAS[133] */
+	0x0F1200C0, /* TVAR_ash_pGAS[134] */
+	0x0F1200AB, /* TVAR_ash_pGAS[135] */
+	0x0F1200A4, /* TVAR_ash_pGAS[136] */
+	0x0F1200AC, /* TVAR_ash_pGAS[137] */
+	0x0F1200C3, /* TVAR_ash_pGAS[138] */
+	0x0F1200E6, /* TVAR_ash_pGAS[139] */
+	0x0F120117, /* TVAR_ash_pGAS[140] */
+	0x0F120145, /* TVAR_ash_pGAS[141] */
+	0x0F120172, /* TVAR_ash_pGAS[142] */
+	0x0F120127, /* TVAR_ash_pGAS[143] */
+	0x0F120100, /* TVAR_ash_pGAS[144] */
+	0x0F1200CF, /* TVAR_ash_pGAS[145] */
+	0x0F1200A7, /* TVAR_ash_pGAS[146] */
+	0x0F12008D, /* TVAR_ash_pGAS[147] */
+	0x0F12007D, /* TVAR_ash_pGAS[148] */
+	0x0F120077, /* TVAR_ash_pGAS[149] */
+	0x0F12007A, /* TVAR_ash_pGAS[150] */
+	0x0F120087, /* TVAR_ash_pGAS[151] */
+	0x0F12009E, /* TVAR_ash_pGAS[152] */
+	0x0F1200C0, /* TVAR_ash_pGAS[153] */
+	0x0F1200EC, /* TVAR_ash_pGAS[154] */
+	0x0F12010F, /* TVAR_ash_pGAS[155] */
+	0x0F120108, /* TVAR_ash_pGAS[156] */
+	0x0F1200D8, /* TVAR_ash_pGAS[157] */
+	0x0F1200A5, /* TVAR_ash_pGAS[158] */
+	0x0F120080, /* TVAR_ash_pGAS[159] */
+	0x0F120066, /* TVAR_ash_pGAS[160] */
+	0x0F120056, /* TVAR_ash_pGAS[161] */
+	0x0F12004F, /* TVAR_ash_pGAS[162] */
+	0x0F120053, /* TVAR_ash_pGAS[163] */
+	0x0F120061, /* TVAR_ash_pGAS[164] */
+	0x0F120077, /* TVAR_ash_pGAS[165] */
+	0x0F120098, /* TVAR_ash_pGAS[166] */
+	0x0F1200C6, /* TVAR_ash_pGAS[167] */
+	0x0F1200F3, /* TVAR_ash_pGAS[168] */
+	0x0F1200E7, /* TVAR_ash_pGAS[169] */
+	0x0F1200B4, /* TVAR_ash_pGAS[170] */
+	0x0F120081, /* TVAR_ash_pGAS[171] */
+	0x0F12005C, /* TVAR_ash_pGAS[172] */
+	0x0F120041, /* TVAR_ash_pGAS[173] */
+	0x0F120030, /* TVAR_ash_pGAS[174] */
+	0x0F120029, /* TVAR_ash_pGAS[175] */
+	0x0F12002E, /* TVAR_ash_pGAS[176] */
+	0x0F12003D, /* TVAR_ash_pGAS[177] */
+	0x0F120055, /* TVAR_ash_pGAS[178] */
+	0x0F120076, /* TVAR_ash_pGAS[179] */
+	0x0F1200A5, /* TVAR_ash_pGAS[180] */
+	0x0F1200D4, /* TVAR_ash_pGAS[181] */
+	0x0F1200CF, /* TVAR_ash_pGAS[182] */
+	0x0F12009B, /* TVAR_ash_pGAS[183] */
+	0x0F12006A, /* TVAR_ash_pGAS[184] */
+	0x0F120043, /* TVAR_ash_pGAS[185] */
+	0x0F120027, /* TVAR_ash_pGAS[186] */
+	0x0F120016, /* TVAR_ash_pGAS[187] */
+	0x0F12000F, /* TVAR_ash_pGAS[188] */
+	0x0F120015, /* TVAR_ash_pGAS[189] */
+	0x0F120025, /* TVAR_ash_pGAS[190] */
+	0x0F12003E, /* TVAR_ash_pGAS[191] */
+	0x0F120061, /* TVAR_ash_pGAS[192] */
+	0x0F12008E, /* TVAR_ash_pGAS[193] */
+	0x0F1200BF, /* TVAR_ash_pGAS[194] */
+	0x0F1200C2, /* TVAR_ash_pGAS[195] */
+	0x0F12008E, /* TVAR_ash_pGAS[196] */
+	0x0F12005D, /* TVAR_ash_pGAS[197] */
+	0x0F120037, /* TVAR_ash_pGAS[198] */
+	0x0F12001A, /* TVAR_ash_pGAS[199] */
+	0x0F120009, /* TVAR_ash_pGAS[200] */
+	0x0F120002, /* TVAR_ash_pGAS[201] */
+	0x0F120007, /* TVAR_ash_pGAS[202] */
+	0x0F120018, /* TVAR_ash_pGAS[203] */
+	0x0F120033, /* TVAR_ash_pGAS[204] */
+	0x0F120057, /* TVAR_ash_pGAS[205] */
+	0x0F120083, /* TVAR_ash_pGAS[206] */
+	0x0F1200B3, /* TVAR_ash_pGAS[207] */
+	0x0F1200BE, /* TVAR_ash_pGAS[208] */
+	0x0F12008A, /* TVAR_ash_pGAS[209] */
+	0x0F12005A, /* TVAR_ash_pGAS[210] */
+	0x0F120034, /* TVAR_ash_pGAS[211] */
+	0x0F120017, /* TVAR_ash_pGAS[212] */
+	0x0F120006, /* TVAR_ash_pGAS[213] */
+	0x0F120000, /* TVAR_ash_pGAS[214] */
+	0x0F120006, /* TVAR_ash_pGAS[215] */
+	0x0F120017, /* TVAR_ash_pGAS[216] */
+	0x0F120033, /* TVAR_ash_pGAS[217] */
+	0x0F120057, /* TVAR_ash_pGAS[218] */
+	0x0F120083, /* TVAR_ash_pGAS[219] */
+	0x0F1200B3, /* TVAR_ash_pGAS[220] */
+	0x0F1200C5, /* TVAR_ash_pGAS[221] */
+	0x0F120091, /* TVAR_ash_pGAS[222] */
+	0x0F120061, /* TVAR_ash_pGAS[223] */
+	0x0F12003B, /* TVAR_ash_pGAS[224] */
+	0x0F120020, /* TVAR_ash_pGAS[225] */
+	0x0F12000F, /* TVAR_ash_pGAS[226] */
+	0x0F120009, /* TVAR_ash_pGAS[227] */
+	0x0F120010, /* TVAR_ash_pGAS[228] */
+	0x0F120021, /* TVAR_ash_pGAS[229] */
+	0x0F12003D, /* TVAR_ash_pGAS[230] */
+	0x0F120060, /* TVAR_ash_pGAS[231] */
+	0x0F12008D, /* TVAR_ash_pGAS[232] */
+	0x0F1200BE, /* TVAR_ash_pGAS[233] */
+	0x0F1200D7, /* TVAR_ash_pGAS[234] */
+	0x0F1200A2, /* TVAR_ash_pGAS[235] */
+	0x0F120072, /* TVAR_ash_pGAS[236] */
+	0x0F12004D, /* TVAR_ash_pGAS[237] */
+	0x0F120032, /* TVAR_ash_pGAS[238] */
+	0x0F120022, /* TVAR_ash_pGAS[239] */
+	0x0F12001D, /* TVAR_ash_pGAS[240] */
+	0x0F120024, /* TVAR_ash_pGAS[241] */
+	0x0F120035, /* TVAR_ash_pGAS[242] */
+	0x0F120050, /* TVAR_ash_pGAS[243] */
+	0x0F120073, /* TVAR_ash_pGAS[244] */
+	0x0F1200A0, /* TVAR_ash_pGAS[245] */
+	0x0F1200D2, /* TVAR_ash_pGAS[246] */
+	0x0F1200F0, /* TVAR_ash_pGAS[247] */
+	0x0F1200BE, /* TVAR_ash_pGAS[248] */
+	0x0F12008C, /* TVAR_ash_pGAS[249] */
+	0x0F120068, /* TVAR_ash_pGAS[250] */
+	0x0F12004F, /* TVAR_ash_pGAS[251] */
+	0x0F120040, /* TVAR_ash_pGAS[252] */
+	0x0F12003B, /* TVAR_ash_pGAS[253] */
+	0x0F120041, /* TVAR_ash_pGAS[254] */
+	0x0F120052, /* TVAR_ash_pGAS[255] */
+	0x0F12006C, /* TVAR_ash_pGAS[256] */
+	0x0F12008E, /* TVAR_ash_pGAS[257] */
+	0x0F1200BE, /* TVAR_ash_pGAS[258] */
+	0x0F1200ED, /* TVAR_ash_pGAS[259] */
+	0x0F12010C, /* TVAR_ash_pGAS[260] */
+	0x0F1200E1, /* TVAR_ash_pGAS[261] */
+	0x0F1200AF, /* TVAR_ash_pGAS[262] */
+	0x0F12008A, /* TVAR_ash_pGAS[263] */
+	0x0F120072, /* TVAR_ash_pGAS[264] */
+	0x0F120064, /* TVAR_ash_pGAS[265] */
+	0x0F12005F, /* TVAR_ash_pGAS[266] */
+	0x0F120065, /* TVAR_ash_pGAS[267] */
+	0x0F120074, /* TVAR_ash_pGAS[268] */
+	0x0F12008D, /* TVAR_ash_pGAS[269] */
+	0x0F1200B2, /* TVAR_ash_pGAS[270] */
+	0x0F1200E0, /* TVAR_ash_pGAS[271] */
+	0x0F12010A, /* TVAR_ash_pGAS[272] */
+	0x0F12012F, /* TVAR_ash_pGAS[273] */
+	0x0F120104, /* TVAR_ash_pGAS[274] */
+	0x0F1200D9, /* TVAR_ash_pGAS[275] */
+	0x0F1200B3, /* TVAR_ash_pGAS[276] */
+	0x0F120099, /* TVAR_ash_pGAS[277] */
+	0x0F12008B, /* TVAR_ash_pGAS[278] */
+	0x0F120086, /* TVAR_ash_pGAS[279] */
+	0x0F12008B, /* TVAR_ash_pGAS[280] */
+	0x0F12009B, /* TVAR_ash_pGAS[281] */
+	0x0F1200B5, /* TVAR_ash_pGAS[282] */
+	0x0F1200DA, /* TVAR_ash_pGAS[283] */
+	0x0F120101, /* TVAR_ash_pGAS[284] */
+	0x0F120128, /* TVAR_ash_pGAS[285] */
+	0x0F12012F, /* TVAR_ash_pGAS[286] */
+	0x0F120106, /* TVAR_ash_pGAS[287] */
+	0x0F1200D4, /* TVAR_ash_pGAS[288] */
+	0x0F1200AA, /* TVAR_ash_pGAS[289] */
+	0x0F12008E, /* TVAR_ash_pGAS[290] */
+	0x0F12007D, /* TVAR_ash_pGAS[291] */
+	0x0F120079, /* TVAR_ash_pGAS[292] */
+	0x0F120080, /* TVAR_ash_pGAS[293] */
+	0x0F120093, /* TVAR_ash_pGAS[294] */
+	0x0F1200B1, /* TVAR_ash_pGAS[295] */
+	0x0F1200DC, /* TVAR_ash_pGAS[296] */
+	0x0F12010C, /* TVAR_ash_pGAS[297] */
+	0x0F120130, /* TVAR_ash_pGAS[298] */
+	0x0F120112, /* TVAR_ash_pGAS[299] */
+	0x0F1200E0, /* TVAR_ash_pGAS[300] */
+	0x0F1200AB, /* TVAR_ash_pGAS[301] */
+	0x0F120083, /* TVAR_ash_pGAS[302] */
+	0x0F120067, /* TVAR_ash_pGAS[303] */
+	0x0F120057, /* TVAR_ash_pGAS[304] */
+	0x0F120051, /* TVAR_ash_pGAS[305] */
+	0x0F120059, /* TVAR_ash_pGAS[306] */
+	0x0F12006B, /* TVAR_ash_pGAS[307] */
+	0x0F120089, /* TVAR_ash_pGAS[308] */
+	0x0F1200B2, /* TVAR_ash_pGAS[309] */
+	0x0F1200E5, /* TVAR_ash_pGAS[310] */
+	0x0F120114, /* TVAR_ash_pGAS[311] */
+	0x0F1200F2, /* TVAR_ash_pGAS[312] */
+	0x0F1200BD, /* TVAR_ash_pGAS[313] */
+	0x0F120088, /* TVAR_ash_pGAS[314] */
+	0x0F120061, /* TVAR_ash_pGAS[315] */
+	0x0F120044, /* TVAR_ash_pGAS[316] */
+	0x0F120031, /* TVAR_ash_pGAS[317] */
+	0x0F12002C, /* TVAR_ash_pGAS[318] */
+	0x0F120033, /* TVAR_ash_pGAS[319] */
+	0x0F120047, /* TVAR_ash_pGAS[320] */
+	0x0F120065, /* TVAR_ash_pGAS[321] */
+	0x0F12008C, /* TVAR_ash_pGAS[322] */
+	0x0F1200C0, /* TVAR_ash_pGAS[323] */
+	0x0F1200F3, /* TVAR_ash_pGAS[324] */
+	0x0F1200DB, /* TVAR_ash_pGAS[325] */
+	0x0F1200A5, /* TVAR_ash_pGAS[326] */
+	0x0F120071, /* TVAR_ash_pGAS[327] */
+	0x0F120049, /* TVAR_ash_pGAS[328] */
+	0x0F12002A, /* TVAR_ash_pGAS[329] */
+	0x0F120018, /* TVAR_ash_pGAS[330] */
+	0x0F120011, /* TVAR_ash_pGAS[331] */
+	0x0F120018, /* TVAR_ash_pGAS[332] */
+	0x0F12002C, /* TVAR_ash_pGAS[333] */
+	0x0F12004B, /* TVAR_ash_pGAS[334] */
+	0x0F120072, /* TVAR_ash_pGAS[335] */
+	0x0F1200A3, /* TVAR_ash_pGAS[336] */
+	0x0F1200D7, /* TVAR_ash_pGAS[337] */
+	0x0F1200CD, /* TVAR_ash_pGAS[338] */
+	0x0F120097, /* TVAR_ash_pGAS[339] */
+	0x0F120065, /* TVAR_ash_pGAS[340] */
+	0x0F12003C, /* TVAR_ash_pGAS[341] */
+	0x0F12001D, /* TVAR_ash_pGAS[342] */
+	0x0F12000A, /* TVAR_ash_pGAS[343] */
+	0x0F120003, /* TVAR_ash_pGAS[344] */
+	0x0F120009, /* TVAR_ash_pGAS[345] */
+	0x0F12001D, /* TVAR_ash_pGAS[346] */
+	0x0F12003B, /* TVAR_ash_pGAS[347] */
+	0x0F120063, /* TVAR_ash_pGAS[348] */
+	0x0F120092, /* TVAR_ash_pGAS[349] */
+	0x0F1200C4, /* TVAR_ash_pGAS[350] */
+	0x0F1200CA, /* TVAR_ash_pGAS[351] */
+	0x0F120094, /* TVAR_ash_pGAS[352] */
+	0x0F120062, /* TVAR_ash_pGAS[353] */
+	0x0F12003A, /* TVAR_ash_pGAS[354] */
+	0x0F12001A, /* TVAR_ash_pGAS[355] */
+	0x0F120007, /* TVAR_ash_pGAS[356] */
+	0x0F120000, /* TVAR_ash_pGAS[357] */
+	0x0F120006, /* TVAR_ash_pGAS[358] */
+	0x0F120018, /* TVAR_ash_pGAS[359] */
+	0x0F120036, /* TVAR_ash_pGAS[360] */
+	0x0F12005C, /* TVAR_ash_pGAS[361] */
+	0x0F12008A, /* TVAR_ash_pGAS[362] */
+	0x0F1200BC, /* TVAR_ash_pGAS[363] */
+	0x0F1200D1, /* TVAR_ash_pGAS[364] */
+	0x0F12009B, /* TVAR_ash_pGAS[365] */
+	0x0F120069, /* TVAR_ash_pGAS[366] */
+	0x0F120042, /* TVAR_ash_pGAS[367] */
+	0x0F120022, /* TVAR_ash_pGAS[368] */
+	0x0F12000F, /* TVAR_ash_pGAS[369] */
+	0x0F120008, /* TVAR_ash_pGAS[370] */
+	0x0F12000D, /* TVAR_ash_pGAS[371] */
+	0x0F12001F, /* TVAR_ash_pGAS[372] */
+	0x0F12003B, /* TVAR_ash_pGAS[373] */
+	0x0F120060, /* TVAR_ash_pGAS[374] */
+	0x0F12008D, /* TVAR_ash_pGAS[375] */
+	0x0F1200BF, /* TVAR_ash_pGAS[376] */
+	0x0F1200E3, /* TVAR_ash_pGAS[377] */
+	0x0F1200AC, /* TVAR_ash_pGAS[378] */
+	0x0F12007A, /* TVAR_ash_pGAS[379] */
+	0x0F120053, /* TVAR_ash_pGAS[380] */
+	0x0F120035, /* TVAR_ash_pGAS[381] */
+	0x0F120022, /* TVAR_ash_pGAS[382] */
+	0x0F12001B, /* TVAR_ash_pGAS[383] */
+	0x0F12001F, /* TVAR_ash_pGAS[384] */
+	0x0F120030, /* TVAR_ash_pGAS[385] */
+	0x0F12004B, /* TVAR_ash_pGAS[386] */
+	0x0F12006D, /* TVAR_ash_pGAS[387] */
+	0x0F12009C, /* TVAR_ash_pGAS[388] */
+	0x0F1200CE, /* TVAR_ash_pGAS[389] */
+	0x0F1200FE, /* TVAR_ash_pGAS[390] */
+	0x0F1200C9, /* TVAR_ash_pGAS[391] */
+	0x0F120095, /* TVAR_ash_pGAS[392] */
+	0x0F12006F, /* TVAR_ash_pGAS[393] */
+	0x0F120052, /* TVAR_ash_pGAS[394] */
+	0x0F120040, /* TVAR_ash_pGAS[395] */
+	0x0F120039, /* TVAR_ash_pGAS[396] */
+	0x0F12003D, /* TVAR_ash_pGAS[397] */
+	0x0F12004B, /* TVAR_ash_pGAS[398] */
+	0x0F120063, /* TVAR_ash_pGAS[399] */
+	0x0F120086, /* TVAR_ash_pGAS[400] */
+	0x0F1200B5, /* TVAR_ash_pGAS[401] */
+	0x0F1200E6, /* TVAR_ash_pGAS[402] */
+	0x0F12011B, /* TVAR_ash_pGAS[403] */
+	0x0F1200ED, /* TVAR_ash_pGAS[404] */
+	0x0F1200BA, /* TVAR_ash_pGAS[405] */
+	0x0F120092, /* TVAR_ash_pGAS[406] */
+	0x0F120076, /* TVAR_ash_pGAS[407] */
+	0x0F120065, /* TVAR_ash_pGAS[408] */
+	0x0F12005D, /* TVAR_ash_pGAS[409] */
+	0x0F120060, /* TVAR_ash_pGAS[410] */
+	0x0F12006D, /* TVAR_ash_pGAS[411] */
+	0x0F120084, /* TVAR_ash_pGAS[412] */
+	0x0F1200A8, /* TVAR_ash_pGAS[413] */
+	0x0F1200D6, /* TVAR_ash_pGAS[414] */
+	0x0F120101, /* TVAR_ash_pGAS[415] */
+	0x0F120140, /* TVAR_ash_pGAS[416] */
+	0x0F120112, /* TVAR_ash_pGAS[417] */
+	0x0F1200E5, /* TVAR_ash_pGAS[418] */
+	0x0F1200BD, /* TVAR_ash_pGAS[419] */
+	0x0F12009E, /* TVAR_ash_pGAS[420] */
+	0x0F12008C, /* TVAR_ash_pGAS[421] */
+	0x0F120085, /* TVAR_ash_pGAS[422] */
+	0x0F120087, /* TVAR_ash_pGAS[423] */
+	0x0F120094, /* TVAR_ash_pGAS[424] */
+	0x0F1200AC, /* TVAR_ash_pGAS[425] */
+	0x0F1200D0, /* TVAR_ash_pGAS[426] */
+	0x0F1200F8, /* TVAR_ash_pGAS[427] */
+	0x0F120123, /* TVAR_ash_pGAS[428] */
+	0x0F1200F2, /* TVAR_ash_pGAS[429] */
+	0x0F1200D1, /* TVAR_ash_pGAS[430] */
+	0x0F1200A7, /* TVAR_ash_pGAS[431] */
+	0x0F120087, /* TVAR_ash_pGAS[432] */
+	0x0F120073, /* TVAR_ash_pGAS[433] */
+	0x0F120067, /* TVAR_ash_pGAS[434] */
+	0x0F120064, /* TVAR_ash_pGAS[435] */
+	0x0F12006B, /* TVAR_ash_pGAS[436] */
+	0x0F12007C, /* TVAR_ash_pGAS[437] */
+	0x0F120094, /* TVAR_ash_pGAS[438] */
+	0x0F1200B7, /* TVAR_ash_pGAS[439] */
+	0x0F1200E1, /* TVAR_ash_pGAS[440] */
+	0x0F1200FF, /* TVAR_ash_pGAS[441] */
+	0x0F1200D6, /* TVAR_ash_pGAS[442] */
+	0x0F1200AE, /* TVAR_ash_pGAS[443] */
+	0x0F120085, /* TVAR_ash_pGAS[444] */
+	0x0F120068, /* TVAR_ash_pGAS[445] */
+	0x0F120054, /* TVAR_ash_pGAS[446] */
+	0x0F120048, /* TVAR_ash_pGAS[447] */
+	0x0F120045, /* TVAR_ash_pGAS[448] */
+	0x0F12004B, /* TVAR_ash_pGAS[449] */
+	0x0F12005B, /* TVAR_ash_pGAS[450] */
+	0x0F120073, /* TVAR_ash_pGAS[451] */
+	0x0F120093, /* TVAR_ash_pGAS[452] */
+	0x0F1200BF, /* TVAR_ash_pGAS[453] */
+	0x0F1200E9, /* TVAR_ash_pGAS[454] */
+	0x0F1200B8, /* TVAR_ash_pGAS[455] */
+	0x0F12008E, /* TVAR_ash_pGAS[456] */
+	0x0F120066, /* TVAR_ash_pGAS[457] */
+	0x0F120049, /* TVAR_ash_pGAS[458] */
+	0x0F120035, /* TVAR_ash_pGAS[459] */
+	0x0F120028, /* TVAR_ash_pGAS[460] */
+	0x0F120025, /* TVAR_ash_pGAS[461] */
+	0x0F12002B, /* TVAR_ash_pGAS[462] */
+	0x0F12003B, /* TVAR_ash_pGAS[463] */
+	0x0F120053, /* TVAR_ash_pGAS[464] */
+	0x0F120072, /* TVAR_ash_pGAS[465] */
+	0x0F12009D, /* TVAR_ash_pGAS[466] */
+	0x0F1200C8, /* TVAR_ash_pGAS[467] */
+	0x0F1200A2, /* TVAR_ash_pGAS[468] */
+	0x0F120078, /* TVAR_ash_pGAS[469] */
+	0x0F120051, /* TVAR_ash_pGAS[470] */
+	0x0F120034, /* TVAR_ash_pGAS[471] */
+	0x0F12001F, /* TVAR_ash_pGAS[472] */
+	0x0F120012, /* TVAR_ash_pGAS[473] */
+	0x0F12000E, /* TVAR_ash_pGAS[474] */
+	0x0F120014, /* TVAR_ash_pGAS[475] */
+	0x0F120024, /* TVAR_ash_pGAS[476] */
+	0x0F12003B, /* TVAR_ash_pGAS[477] */
+	0x0F12005B, /* TVAR_ash_pGAS[478] */
+	0x0F120083, /* TVAR_ash_pGAS[479] */
+	0x0F1200AD, /* TVAR_ash_pGAS[480] */
+	0x0F120095, /* TVAR_ash_pGAS[481] */
+	0x0F12006C, /* TVAR_ash_pGAS[482] */
+	0x0F120046, /* TVAR_ash_pGAS[483] */
+	0x0F12002A, /* TVAR_ash_pGAS[484] */
+	0x0F120014, /* TVAR_ash_pGAS[485] */
+	0x0F120007, /* TVAR_ash_pGAS[486] */
+	0x0F120002, /* TVAR_ash_pGAS[487] */
+	0x0F120008, /* TVAR_ash_pGAS[488] */
+	0x0F120016, /* TVAR_ash_pGAS[489] */
+	0x0F12002D, /* TVAR_ash_pGAS[490] */
+	0x0F12004C, /* TVAR_ash_pGAS[491] */
+	0x0F120072, /* TVAR_ash_pGAS[492] */
+	0x0F12009B, /* TVAR_ash_pGAS[493] */
+	0x0F120093, /* TVAR_ash_pGAS[494] */
+	0x0F12006A, /* TVAR_ash_pGAS[495] */
+	0x0F120045, /* TVAR_ash_pGAS[496] */
+	0x0F120028, /* TVAR_ash_pGAS[497] */
+	0x0F120013, /* TVAR_ash_pGAS[498] */
+	0x0F120005, /* TVAR_ash_pGAS[499] */
+	0x0F120000, /* TVAR_ash_pGAS[500] */
+	0x0F120004, /* TVAR_ash_pGAS[501] */
+	0x0F120012, /* TVAR_ash_pGAS[502] */
+	0x0F120028, /* TVAR_ash_pGAS[503] */
+	0x0F120045, /* TVAR_ash_pGAS[504] */
+	0x0F12006A, /* TVAR_ash_pGAS[505] */
+	0x0F120093, /* TVAR_ash_pGAS[506] */
+	0x0F12009B, /* TVAR_ash_pGAS[507] */
+	0x0F120071, /* TVAR_ash_pGAS[508] */
+	0x0F12004C, /* TVAR_ash_pGAS[509] */
+	0x0F120030, /* TVAR_ash_pGAS[510] */
+	0x0F12001A, /* TVAR_ash_pGAS[511] */
+	0x0F12000C, /* TVAR_ash_pGAS[512] */
+	0x0F120007, /* TVAR_ash_pGAS[513] */
+	0x0F12000B, /* TVAR_ash_pGAS[514] */
+	0x0F120018, /* TVAR_ash_pGAS[515] */
+	0x0F12002C, /* TVAR_ash_pGAS[516] */
+	0x0F120048, /* TVAR_ash_pGAS[517] */
+	0x0F12006D, /* TVAR_ash_pGAS[518] */
+	0x0F120097, /* TVAR_ash_pGAS[519] */
+	0x0F1200AE, /* TVAR_ash_pGAS[520] */
+	0x0F120083, /* TVAR_ash_pGAS[521] */
+	0x0F12005C, /* TVAR_ash_pGAS[522] */
+	0x0F120040, /* TVAR_ash_pGAS[523] */
+	0x0F12002B, /* TVAR_ash_pGAS[524] */
+	0x0F12001E, /* TVAR_ash_pGAS[525] */
+	0x0F120018, /* TVAR_ash_pGAS[526] */
+	0x0F12001C, /* TVAR_ash_pGAS[527] */
+	0x0F120027, /* TVAR_ash_pGAS[528] */
+	0x0F12003A, /* TVAR_ash_pGAS[529] */
+	0x0F120055, /* TVAR_ash_pGAS[530] */
+	0x0F12007B, /* TVAR_ash_pGAS[531] */
+	0x0F1200A6, /* TVAR_ash_pGAS[532] */
+	0x0F1200CA, /* TVAR_ash_pGAS[533] */
+	0x0F12009E, /* TVAR_ash_pGAS[534] */
+	0x0F120076, /* TVAR_ash_pGAS[535] */
+	0x0F120059, /* TVAR_ash_pGAS[536] */
+	0x0F120046, /* TVAR_ash_pGAS[537] */
+	0x0F120039, /* TVAR_ash_pGAS[538] */
+	0x0F120033, /* TVAR_ash_pGAS[539] */
+	0x0F120036, /* TVAR_ash_pGAS[540] */
+	0x0F120040, /* TVAR_ash_pGAS[541] */
+	0x0F120052, /* TVAR_ash_pGAS[542] */
+	0x0F12006C, /* TVAR_ash_pGAS[543] */
+	0x0F120094, /* TVAR_ash_pGAS[544] */
+	0x0F1200BF, /* TVAR_ash_pGAS[545] */
+	0x0F1200EB, /* TVAR_ash_pGAS[546] */
+	0x0F1200C3, /* TVAR_ash_pGAS[547] */
+	0x0F120099, /* TVAR_ash_pGAS[548] */
+	0x0F12007A, /* TVAR_ash_pGAS[549] */
+	0x0F120066, /* TVAR_ash_pGAS[550] */
+	0x0F12005A, /* TVAR_ash_pGAS[551] */
+	0x0F120054, /* TVAR_ash_pGAS[552] */
+	0x0F120056, /* TVAR_ash_pGAS[553] */
+	0x0F12005F, /* TVAR_ash_pGAS[554] */
+	0x0F120071, /* TVAR_ash_pGAS[555] */
+	0x0F12008D, /* TVAR_ash_pGAS[556] */
+	0x0F1200B6, /* TVAR_ash_pGAS[557] */
+	0x0F1200DE, /* TVAR_ash_pGAS[558] */
+	0x0F12010D, /* TVAR_ash_pGAS[559] */
+	0x0F1200E7, /* TVAR_ash_pGAS[560] */
+	0x0F1200C1, /* TVAR_ash_pGAS[561] */
+	0x0F1200A0, /* TVAR_ash_pGAS[562] */
+	0x0F12008A, /* TVAR_ash_pGAS[563] */
+	0x0F12007C, /* TVAR_ash_pGAS[564] */
+	0x0F120076, /* TVAR_ash_pGAS[565] */
+	0x0F120078, /* TVAR_ash_pGAS[566] */
+	0x0F120081, /* TVAR_ash_pGAS[567] */
+	0x0F120093, /* TVAR_ash_pGAS[568] */
+	0x0F1200B1, /* TVAR_ash_pGAS[569] */
+	0x0F1200D5, /* TVAR_ash_pGAS[570] */
+	0x0F1200FD, /* TVAR_ash_pGAS[571] */
+	
+	/* Gamma */
+	0x002A04CC,
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[0][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[0][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[0][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[0][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[0][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[0][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[0][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[0][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[0][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[0][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[0][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[0][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[0][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[0][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[0][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[0][15] */
+	
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[1][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[1][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[1][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[1][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[1][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[1][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[1][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[1][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[1][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[1][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[1][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[1][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[1][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[1][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[1][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[1][15] */
+	
+	0x0F120000, /* 0000 SARR_usGammaLutRGBIndoor[2][0]  */
+	0x0F120002, /* 0002 SARR_usGammaLutRGBIndoor[2][1]  */
+	0x0F120008, /* 0008 SARR_usGammaLutRGBIndoor[2][2]  */
+	0x0F120016, /* 0018 SARR_usGammaLutRGBIndoor[2][3]  */
+	0x0F120055, /* 005A SARR_usGammaLutRGBIndoor[2][4]  */
+	0x0F1200E6, /* 00DF SARR_usGammaLutRGBIndoor[2][5]  */
+	0x0F120141, /* 013F SARR_usGammaLutRGBIndoor[2][6]  */
+	0x0F120188, /* 0186 SARR_usGammaLutRGBIndoor[2][7]  */
+	0x0F1201E6, /* 01E6 SARR_usGammaLutRGBIndoor[2][8]  */
+	0x0F120236, /* 0236 SARR_usGammaLutRGBIndoor[2][9]  */
+	0x0F1202BA, /* 02BA SARR_usGammaLutRGBIndoor[2][10] */
+	0x0F12032A, /* 032A SARR_usGammaLutRGBIndoor[2][11] */
+	0x0F120385, /* 0385 SARR_usGammaLutRGBIndoor[2][12] */
+	0x0F1203C2, /* 03C2 SARR_usGammaLutRGBIndoor[2][13] */
+	0x0F1203EA, /* 03EA SARR_usGammaLutRGBIndoor[2][14] */
+	0x0F1203FF, /* 03FF SARR_usGammaLutRGBIndoor[2][15] */
+	
+	
+	/* Set AWB */
+	0x002A0DA6,
+	0x0F120000,
+	0x0F120000,
+	0x002A0E8C,
+	0x0F120000,
+	0x002A0D6C,
+	0x0F120040,
+	
+	/* Indoor Gray Zone */
+	0x002A0B9C,
+	0x0F12038F, /* awbb_IndoorGrZones_m_BGrid_0__m_left   */
+	0x0F12039B, /* awbb_IndoorGrZones_m_BGrid_0__m_right  */
+	0x0F120373, /* awbb_IndoorGrZones_m_BGrid_1__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_1__m_right  */
+	0x0F120352, /* awbb_IndoorGrZones_m_BGrid_2__m_left   */
+	0x0F1203B7, /* awbb_IndoorGrZones_m_BGrid_2__m_right  */
+	0x0F120334, /* awbb_IndoorGrZones_m_BGrid_3__m_left   */
+	0x0F1203B5, /* awbb_IndoorGrZones_m_BGrid_3__m_right  */
+	0x0F120318, /* awbb_IndoorGrZones_m_BGrid_4__m_left   */
+	0x0F1203B0, /* awbb_IndoorGrZones_m_BGrid_4__m_right  */
+	0x0F1202FF, /* awbb_IndoorGrZones_m_BGrid_5__m_left   */
+	0x0F12038D, /* awbb_IndoorGrZones_m_BGrid_5__m_right  */
+	0x0F1202E7, /* awbb_IndoorGrZones_m_BGrid_6__m_left   */
+	0x0F120372, /* awbb_IndoorGrZones_m_BGrid_6__m_right  */
+	0x0F1202D0, /* awbb_IndoorGrZones_m_BGrid_7__m_left   */
+	0x0F12035D, /* awbb_IndoorGrZones_m_BGrid_7__m_right  */
+	0x0F1202B5, /* awbb_IndoorGrZones_m_BGrid_8__m_left   */
+	0x0F120345, /* awbb_IndoorGrZones_m_BGrid_8__m_right  */
+	0x0F1202A1, /* awbb_IndoorGrZones_m_BGrid_9__m_left   */
+	0x0F120331, /* awbb_IndoorGrZones_m_BGrid_9__m_right  */
+	0x0F12028B, /* awbb_IndoorGrZones_m_BGrid_10__m_left  */
+	0x0F12031E, /* awbb_IndoorGrZones_m_BGrid_10__m_right */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_11__m_left  */
+	0x0F120309, /* awbb_IndoorGrZones_m_BGrid_11__m_right */
+	0x0F12025F, /* awbb_IndoorGrZones_m_BGrid_12__m_left  */
+	0x0F1202F5, /* awbb_IndoorGrZones_m_BGrid_12__m_right */
+	0x0F120250, /* awbb_IndoorGrZones_m_BGrid_13__m_left  */
+	0x0F1202DB, /* awbb_IndoorGrZones_m_BGrid_13__m_right */
+	0x0F120241, /* awbb_IndoorGrZones_m_BGrid_14__m_left  */
+	0x0F1202C7, /* awbb_IndoorGrZones_m_BGrid_14__m_right */
+	0x0F120233, /* awbb_IndoorGrZones_m_BGrid_15__m_left  */
+	0x0F1202B9, /* awbb_IndoorGrZones_m_BGrid_15__m_right */
+	0x0F120223, /* awbb_IndoorGrZones_m_BGrid_16__m_left  */
+	0x0F1202AB, /* awbb_IndoorGrZones_m_BGrid_16__m_right */
+	0x0F120217, /* awbb_IndoorGrZones_m_BGrid_17__m_left  */
+	0x0F1202A2, /* awbb_IndoorGrZones_m_BGrid_17__m_right */
+	0x0F120207, /* awbb_IndoorGrZones_m_BGrid_18__m_left  */
+	0x0F120294, /* awbb_IndoorGrZones_m_BGrid_18__m_right */
+	0x0F1201FA, /* awbb_IndoorGrZones_m_BGrid_19__m_left  */
+	0x0F120289, /* awbb_IndoorGrZones_m_BGrid_19__m_right */
+	0x0F1201EA, /* awbb_IndoorGrZones_m_BGrid_20__m_left  */
+	0x0F120281, /* awbb_IndoorGrZones_m_BGrid_20__m_right */
+	0x0F1201DD, /* awbb_IndoorGrZones_m_BGrid_21__m_left  */
+	0x0F12027B, /* awbb_IndoorGrZones_m_BGrid_21__m_right */
+	0x0F1201D0, /* awbb_IndoorGrZones_m_BGrid_22__m_left  */
+	0x0F120273, /* awbb_IndoorGrZones_m_BGrid_22__m_right */
+	0x0F1201C3, /* awbb_IndoorGrZones_m_BGrid_23__m_left  */
+	0x0F12026A, /* awbb_IndoorGrZones_m_BGrid_23__m_right */
+	0x0F1201B6, /* awbb_IndoorGrZones_m_BGrid_24__m_left  */
+	0x0F120265, /* awbb_IndoorGrZones_m_BGrid_24__m_right */
+	0x0F1201AB, /* awbb_IndoorGrZones_m_BGrid_25__m_left  */
+	0x0F12025B, /* awbb_IndoorGrZones_m_BGrid_25__m_right */
+	0x0F1201A1, /* awbb_IndoorGrZones_m_BGrid_26__m_left  */
+	0x0F120254, /* awbb_IndoorGrZones_m_BGrid_26__m_right */
+	0x0F120198, /* awbb_IndoorGrZones_m_BGrid_27__m_left  */
+	0x0F12024B, /* awbb_IndoorGrZones_m_BGrid_27__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_28__m_left  */
+	0x0F120242, /* awbb_IndoorGrZones_m_BGrid_28__m_right */
+	0x0F120191, /* awbb_IndoorGrZones_m_BGrid_29__m_left  */
+	0x0F12023A, /* awbb_IndoorGrZones_m_BGrid_29__m_right */
+	0x0F120192, /* awbb_IndoorGrZones_m_BGrid_30__m_left  */
+	0x0F120222, /* awbb_IndoorGrZones_m_BGrid_30__m_right */
+	0x0F1201C5, /* awbb_IndoorGrZones_m_BGrid_31__m_left  */
+	0x0F1201DF, /* awbb_IndoorGrZones_m_BGrid_31__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_32__m_right */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_left  */
+	0x0F120000, /* awbb_IndoorGrZones_m_BGrid_33__m_right */
+	
+	
+	/* param_end	awbb_IndoorGrZones_m_BGrid */
+	0x002A0C3C,
+	0x0F120004,
+	0x0F120000,
+	0x0F120022,
+	0x0F120000,
+	0x0F12010F,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0C50,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Outdoor Gray Zone */
+	0x0F12025E, /* 0264 awbb_OutdoorGrZones_m_BGrid_0__m_left    */
+	0x0F120282, /* 0279 awbb_OutdoorGrZones_m_BGrid_0__m_right   */
+	0x0F120240, /* 0250 awbb_OutdoorGrZones_m_BGrid_1__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_1__m_right   */
+	0x0F12022A, /* 0244 awbb_OutdoorGrZones_m_BGrid_2__m_left    */
+	0x0F12029A, /* 0287 awbb_OutdoorGrZones_m_BGrid_2__m_right   */
+	0x0F12021A, /* 0235 awbb_OutdoorGrZones_m_BGrid_3__m_left    */
+	0x0F12029A, /* 0289 awbb_OutdoorGrZones_m_BGrid_3__m_right   */
+	0x0F120206, /* 0225 awbb_OutdoorGrZones_m_BGrid_4__m_left    */
+	0x0F120298, /* 0287 awbb_OutdoorGrZones_m_BGrid_4__m_right   */
+	0x0F1201FE, /* 0213 awbb_OutdoorGrZones_m_BGrid_5__m_left    */
+	0x0F12028C, /* 0286 awbb_OutdoorGrZones_m_BGrid_5__m_right   */
+	0x0F1201FA, /* 0202 awbb_OutdoorGrZones_m_BGrid_6__m_left    */
+	0x0F120278, /* 027A awbb_OutdoorGrZones_m_BGrid_6__m_right   */
+	0x0F1201F8, /* 01F3 awbb_OutdoorGrZones_m_BGrid_7__m_left    */
+	0x0F120266, /* 0272 awbb_OutdoorGrZones_m_BGrid_7__m_right   */
+	0x0F120214, /* 01E9 awbb_OutdoorGrZones_m_BGrid_8__m_left    */
+	0x0F120238, /* 0269 awbb_OutdoorGrZones_m_BGrid_8__m_right   */
+	0x0F120000, /* 01E2 awbb_OutdoorGrZones_m_BGrid_9__m_left    */
+	0x0F120000, /* 0263 awbb_OutdoorGrZones_m_BGrid_9__m_right   */
+	0x0F120000, /* 01E0 awbb_OutdoorGrZones_m_BGrid_10__m_left   */
+	0x0F120000, /* 025A awbb_OutdoorGrZones_m_BGrid_10__m_right  */
+	0x0F120000, /* 01E1 awbb_OutdoorGrZones_m_BGrid_11__m_left   */
+	0x0F120000, /* 0256 awbb_OutdoorGrZones_m_BGrid_11__m_right  */
+	0x0F120000, /* 01EE awbb_OutdoorGrZones_m_BGrid_12__m_left   */
+	0x0F120000, /* 0251 awbb_OutdoorGrZones_m_BGrid_12__m_right  */
+	0x0F120000, /* 01F8 awbb_OutdoorGrZones_m_BGrid(26)          */
+	0x0F120000, /* 024A awbb_OutdoorGrZones_m_BGrid(27)          */
+	0x0F120000, /* 020D awbb_OutdoorGrZones_m_BGrid(28)          */
+	0x0F120000, /* 0231 awbb_OutdoorGrZones_m_BGrid(29)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(30)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(31)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(32)          */
+	0x0F120000, /* 0000 awbb_OutdoorGrZones_m_BGrid(33)          */
+	
+	
+	/* param_WRITE 70000CC6  B2end	awbb_OutdoorGrZones_m_BGrid */
+	0x002A0CB8,
+	0x0F120004,
+	0x0F120000,
+	0x0F120009,
+	0x0F120000,
+	0x0F120210,
+	0x0F120000,
+	0x0F120020,
+	0x0F120000,
+	0x002A0CCC,
+	0x0F1200C0,
+	0x0F120000,
+	
+	/*  7-3. Low Br grey zone                     */
+	/* param_  C4start	awbb_LowBrGrZones_m_BGrid */
+	
+	0x0F12031F, /* awbb_LowBrGrZones_m_BGrid_0__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_0__m_right  */
+	0x0F1202FC, /* awbb_LowBrGrZones_m_BGrid_1__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_1__m_right  */
+	0x0F1202D9, /* awbb_LowBrGrZones_m_BGrid_2__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_2__m_right  */
+	0x0F1202B6, /* awbb_LowBrGrZones_m_BGrid_3__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_3__m_right  */
+	0x0F120293, /* awbb_LowBrGrZones_m_BGrid_4__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_4__m_right  */
+	0x0F120270, /* awbb_LowBrGrZones_m_BGrid_5__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_5__m_right  */
+	0x0F12024E, /* awbb_LowBrGrZones_m_BGrid_6__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_6__m_right  */
+	0x0F12022B, /* awbb_LowBrGrZones_m_BGrid_7__m_left   */
+	0x0F120495, /* awbb_LowBrGrZones_m_BGrid_7__m_right  */
+	0x0F120208, /* awbb_LowBrGrZones_m_BGrid_8__m_left   */
+	0x0F12048A, /* awbb_LowBrGrZones_m_BGrid_8__m_right  */
+	0x0F1201E5, /* awbb_LowBrGrZones_m_BGrid_9__m_left   */
+	0x0F120455, /* awbb_LowBrGrZones_m_BGrid_9__m_right  */
+	0x0F1201C2, /* awbb_LowBrGrZones_m_BGrid_10__m_left  */
+	0x0F12041F, /* awbb_LowBrGrZones_m_BGrid_10__m_right */
+	0x0F12019F, /* awbb_LowBrGrZones_m_BGrid_11__m_left  */
+	0x0F1203EA, /* awbb_LowBrGrZones_m_BGrid_11__m_right */
+	0x0F12017D, /* awbb_LowBrGrZones_m_BGrid_12__m_left  */
+	0x0F1203B4, /* awbb_LowBrGrZones_m_BGrid_12__m_right */
+	0x0F12015A, /* awbb_LowBrGrZones_m_BGrid_13__m_left  */
+	0x0F12037F, /* awbb_LowBrGrZones_m_BGrid_13__m_right */
+	0x0F120137, /* awbb_LowBrGrZones_m_BGrid_14__m_left  */
+	0x0F120349, /* awbb_LowBrGrZones_m_BGrid_14__m_right */
+	0x0F120130, /* awbb_LowBrGrZones_m_BGrid_15__m_left  */
+	0x0F120314, /* awbb_LowBrGrZones_m_BGrid_15__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_16__m_left  */
+	0x0F1202DE, /* awbb_LowBrGrZones_m_BGrid_16__m_right */
+	0x0F12012F, /* awbb_LowBrGrZones_m_BGrid_17__m_left  */
+	0x0F1202B1, /* awbb_LowBrGrZones_m_BGrid_17__m_right */
+	0x0F12012E, /* awbb_LowBrGrZones_m_BGrid_18__m_left  */
+	0x0F12028B, /* awbb_LowBrGrZones_m_BGrid_18__m_right */
+	0x0F12012D, /* awbb_LowBrGrZones_m_BGrid_19__m_left  */
+	0x0F120265, /* awbb_LowBrGrZones_m_BGrid_19__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_20__m_left  */
+	0x0F12023F, /* awbb_LowBrGrZones_m_BGrid_20__m_right */
+	0x0F12012C, /* awbb_LowBrGrZones_m_BGrid_21__m_left  */
+	0x0F120219, /* awbb_LowBrGrZones_m_BGrid_21__m_right */
+	0x0F12012B, /* awbb_LowBrGrZones_m_BGrid_22__m_left  */
+	0x0F1201F3, /* awbb_LowBrGrZones_m_BGrid_22__m_right */
+	0x0F12012A, /* awbb_LowBrGrZones_m_BGrid_23__m_left  */
+	0x0F1201CD, /* awbb_LowBrGrZones_m_BGrid_23__m_right */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_left  */
+	0x0F120000, /* awbb_LowBrGrZones_m_BGrid_24__m_right */
+	
+	
+	/* 42param_end awbb_LowBrGrZones_m_BGrid */
+	0x0F120005,
+	0x0F120000,
+	0x0F120018,
+	0x0F120000,
+	0x0F1200AF,
+	0x0F120000,
+	0x0F120002,
+	0x0F120000,
+	0x002A0D48,
+	0x0F1200E0,
+	0x0F120000,
+	
+	/* Lowtemp circle */
+	0x0F12032F,
+	0x0F120000,
+	0x0F12017A,
+	0x0F120000,
+	0x0F127300,
+	0x0F120000,
+	0x0F12000A,
+	0x0F120000,
+	0x002A0D60,
+	0x0F1200E0,
+	0x0F120000,
+	0x002A0D82,
+	0x0F120001,
+	
+	
+	
+	0x002A0D8E,
+	0x0F120002, /* awbb_GridEnable */
+	
+	/* Grid coefficients and Contrants */
+	0x002A0DCE,
+	0x0F12FFE0, /* awbb_GridCorr_R_0__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_0__1_ */
+	0x0F120000, /* awbb_GridCorr_R_0__2_ */
+	0x0F120000, /* awbb_GridCorr_R_0__3_ */
+	0x0F120000, /* awbb_GridCorr_R_0__4_ */
+	0x0F120030, /* awbb_GridCorr_R_0__5_ */
+	
+	0x0F12FFE0, /* awbb_GridCorr_R_1__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_1__1_ */
+	0x0F120000, /* awbb_GridCorr_R_1__2_ */
+	0x0F120000, /* awbb_GridCorr_R_1__3_ */
+	0x0F120000, /* awbb_GridCorr_R_1__4_ */
+	0x0F120030, /* awbb_GridCorr_R_1__5_ */
+	
+	0x0F12FFE0, /* awbb_GridCorr_R_2__0_ */
+	0x0F12FFE0, /* D8 awbb_GridCorr_R_2__1_ */
+	0x0F120000, /* awbb_GridCorr_R_2__2_ */
+	0x0F120000, /* awbb_GridCorr_R_2__3_ */
+	0x0F120000, /* awbb_GridCorr_R_2__4_ */
+	0x0F120030, /* awbb_GridCorr_R_2__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_0__0_ */
+	0x0F120000, /* awbb_GridCorr_B_0__1_ */
+	0x0F120000, /* awbb_GridCorr_B_0__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_0__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_0__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_0__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_1__0_ */
+	0x0F120000, /* awbb_GridCorr_B_1__1_ */
+	0x0F120000, /* awbb_GridCorr_B_1__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_1__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_1__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_1__5_ */
+	
+	0x0F120004, /* 08 awbb_GridCorr_B_2__0_ */
+	0x0F120000, /* awbb_GridCorr_B_2__1_ */
+	0x0F120000, /* awbb_GridCorr_B_2__2_ */
+	0x0F12FFC0, /* awbb_GridCorr_B_2__3_ */
+	0x0F12FFB0, /* awbb_GridCorr_B_2__4_ */
+	0x0F12FF30, /* awbb_GridCorr_B_2__5_ */
+	
+	0x0F1202C6,
+	0x0F120335,
+	0x0F1203B3,
+	0x0F121021,
+	0x0F12107E,
+	0x0F12113E,
+	0x0F12117C,
+	0x0F1211C2,
+	0x0F12120B,
+	
+	0x0F1200B3,
+	0x0F1200B7,
+	0x0F1200D3,
+	0x0F120091,
+	
+	/* White Locus */
+	0x002A0D66,
+	0x0F120133,
+	0x0F12010F,
+	0x002A0D74,
+	0x0F12052A,
+	
+	/* Gamut Thresholds */
+	0x002A0DAE,
+	0x0F120036,
+	0x0F12001C,
+	0x002A0DAA,
+	0x0F12071A,
+	0x0F1203A4,
+	
+	/* SceneDetection Thresholds */
+	0x002A0D92,
+	0x0F120BB8,
+	0x0F120096,
+	0x002A0E86,
+	0x0F120216,
+	0x0F12029F,
+	0x002A0D96,
+	0x0F120BB7,
+	0x0F120096,
+	0x002A0DB2,
+	0x0F1200DA,
+	0x002A0D9A,
+	0x0F12000A,
+	0x002A0DB4,
+	0x0F120459,
+	0x002A0DA4,
+	0x0F12000E,
+	0x002A0D64,
+	0x0F120032,
+	0x002A0DA6,
+	0x0F12001E,
+	0x002A0D9C,
+	0x0F12001B,
+	0x0F12000E,
+	0x0F120008,
+	0x0F120004,
+	
+	/* AWB Debug.(Outdoor Pink) */
+	0x002A0E30,
+	0x0F120000,
+	0x002A0E84,
+	0x0F120000,
+	
+	/* UseInvalidOutdoor option */
+	0x002A0D88,
+	0x0F120001,
+	
+	/* AWB input Y-Filter setting */
+	0x002A0C48,
+	0x0F120020,
+	0x002A0C50,
+	0x0F1200E0,
+	0x002A0CC4,
+	0x0F120020,
+	0x002A0CCC,
+	0x0F1200C0,
+	
+	
+	0x002A0DC2,
+	0x0F120030,
+	0x0F1200C8,
+	0x0F12012C,
+	0x0F120210, /* 258 awbb_GainsMaxMove */
+	0x0F120003,
+	
+	
+	/* Set CCM */
+	/* CCM Start Address */
+	0x002A06D0,
+	0x0F122800,
+	0x0F127000,
+	0x0F122824,
+	0x0F127000,
+	0x0F122848,
+	0x0F127000,
+	0x0F12286C,
+	0x0F127000,
+	0x0F122890,
+	0x0F127000,
+	0x0F1228B4,
+	0x0F127000,
+	0x002A06EC,
+	0x0F1228D8,
+	0x0F127000,
+	
+	/* CCM */
+	0x002A2800,
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201E1,
+	0x0F12FFC4,
+	0x0F12FFF8,
+	0x0F120101,
+	0x0F12014C,
+	0x0F12FF55,
+	0x0F12FF5B,
+	0x0F120205,
+	0x0F12FF17,
+	0x0F12FEFE,
+	0x0F1201B6,
+	0x0F120107,
+	0x0F12FFDB,
+	0x0F12FFDB,
+	0x0F1201D1,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	0x0F1201FB,
+	0x0F12FFA9,
+	0x0F12FFEA,
+	0x0F12013C,
+	0x0F120140,
+	0x0F12FF53,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF39,
+	0x0F1201D6,
+	0x0F1200C4,
+	0x0F12FFC0,
+	0x0F12FFBF,
+	0x0F1201CD,
+	0x0F120182,
+	0x0F12FF91,
+	0x0F1201AA,
+	
+	0x0F1201C5,
+	0x0F12FF9F,
+	0x0F12FFE5,
+	0x0F1200E2,
+	0x0F12010E,
+	0x0F12FF62,
+	0x0F12FF03,
+	0x0F1201D0,
+	0x0F12FF3E,
+	0x0F12FF00,
+	0x0F1201A6,
+	0x0F1200BB,
+	0x0F12FFBF,
+	0x0F12FFDD,
+	0x0F1201F6,
+	0x0F1200CB,
+	0x0F12FF94,
+	0x0F12019E,
+	
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200E8,
+	0x0F120126,
+	0x0F12FF83,
+	0x0F12FE7A,
+	0x0F12017D,
+	0x0F12FEED,
+	0x0F12FF8A,
+	0x0F1201F9,
+	0x0F12005B,
+	0x0F12FFCA,
+	0x0F12FFA3,
+	0x0F1201DA,
+	0x0F120108,
+	0x0F12FFB3,
+	0x0F1201DD,
+	
+	0x0F1201D2,
+	0x0F12FFC2,
+	0x0F12FFFC,
+	0x0F1200F4,
+	0x0F120139,
+	0x0F12FF64,
+	0x0F12FEEC,
+	0x0F1201FD,
+	0x0F12FF8E,
+	0x0F12FEF4,
+	0x0F1201BD,
+	0x0F12010A,
+	0x0F12FFA2,
+	0x0F12FFDE,
+	0x0F120208,
+	0x0F120163,
+	0x0F12FF9E,
+	0x0F1201B3,
+	
+	/* Set NB */
+	0x002A07EA,
+	0x0F120000, /*afit_bUseNoiseInd 0 : NB 1: Noise Index */
+	
+	/* param_start	SARR_uNormBrInDoor */
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+	
+	/* param_start	SARR_uNormBrOutDoor */
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+	
+	/* Set AFIT */
+	0x002A0814,
+	0x0F12082C,
+	0x0F127000,
+	
+	0x002A082C,
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120010, /* SATURATION                                                         */
+	0x0F12FFE2, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F1203FF, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120028, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F1203FF, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120344, /* UVDenoise_iYLowThresh                                              */
+	0x0F12033A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120C0F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120C0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12023F, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F12030A, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F120003, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F120011, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F120900, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F120000, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120000, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120000, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12000A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F126E14, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120008, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120014, /* Denoise1_iYDenThreshLow                                            */
+	0x0F12000E, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120064, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F1200FF, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120114, /* UVDenoise_iYLowThresh                                              */
+	0x0F12020A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120000, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120046, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F12050F, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120A0F, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120303, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120303, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F12020A, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120305, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F12101E, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F12101E, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120005, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120400, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120400, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120000, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120A00, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F12100A, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128030, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F12000C, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120060, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F120000, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F12005A, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120014, /* UVDenoise_iYLowThresh                                              */
+	0x0F12000A, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120014, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120050, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120010, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120480, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120403, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120402, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120203, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F12803C, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F120000, /* BRIGHTNESS                                                         */
+	0x0F12000A, /* CONTRAST                                                           */
+	0x0F120000, /* SATURATION                                                         */
+	0x0F120000, /* SHARP_BLUR                                                         */
+	0x0F120000, /* GLAMOUR                                                            */
+	0x0F1203FF, /* Disparity_iSatSat                                                  */
+	0x0F120006, /* Denoise1_iYDenThreshLow                                            */
+	0x0F120006, /* Denoise1_iYDenThreshLow_Bin                                        */
+	0x0F120050, /* Denoise1_iYDenThreshHigh                                           */
+	0x0F120050, /* Denoise1_iYDenThreshHigh_Bin                                       */
+	0x0F120002, /* Denoise1_iLowWWideThresh                                           */
+	0x0F12000A, /* Denoise1_iHighWWideThresh                                          */
+	0x0F12000A, /* Denoise1_iLowWideThresh                                            */
+	0x0F12000A, /* Denoise1_iHighWideThresh                                           */
+	0x0F1203FF, /* Denoise1_iSatSat                                                   */
+	0x0F1203FF, /* Demosaic4_iHystGrayLow                                             */
+	0x0F120000, /* Demosaic4_iHystGrayHigh                                            */
+	0x0F120000, /* UVDenoise_iYLowThresh                                              */
+	0x0F120000, /* UVDenoise_iYHighThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVLowThresh                                             */
+	0x0F1203FF, /* UVDenoise_iUVHighThresh                                            */
+	0x0F120028, /* DSMix1_iLowLimit_Wide                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Wide_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Wide                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Wide_Bin                                         */
+	0x0F120030, /* DSMix1_iLowLimit_Fine                                              */
+	0x0F120032, /* DSMix1_iLowLimit_Fine_Bin                                          */
+	0x0F120000, /* DSMix1_iHighLimit_Fine                                             */
+	0x0F120032, /* DSMix1_iHighLimit_Fine_Bin                                         */
+	0x0F120106, /* DSMix1_iRGBOffset                                                  */
+	0x0F12006F, /* DSMix1_iDemClamp                                                   */
+	0x0F120202, /* "Disparity_iDispTH_LowDisparity_iDispTH_Low_Bin"                   */
+	0x0F120502, /* "Disparity_iDispTH_High Disparity_iDispTH_High_Bin"                */
+	0x0F120202, /* "Despeckle_iCorrectionLevelColdDespeckle_iCorrectionLevelCold_Bin" */
+	0x0F120202, /* Despeckle_iCorrectionLevelHotDespeckle_iCorrectionLevelHot_Bin     */
+	0x0F12140A, /* "Despeckle_iColdThreshLowDespeckle_iColdThreshHigh"                */
+	0x0F12140A, /* "Despeckle_iHotThreshLowDespeckle_iHotThreshHigh"                  */
+	0x0F122828, /* "Denoise1_iLowMaxSlopeAllowedDenoise1_iHighMaxSlopeAllowed"        */
+	0x0F120606, /* "Denoise1_iLowSlopeThreshDenoise1_iHighSlopeThresh"                */
+	0x0F120205, /* "Denoise1_iRadialPowerDenoise1_iRadialDivideShift"                 */
+	0x0F120880, /* "Denoise1_iRadialLimitDenoise1_iLWBNoise"                          */
+	0x0F12000F, /* "Denoise1_iWideDenoise1_iWideWide"                                 */
+	0x0F120005, /* "Demosaic4_iHystGrayRangeUVDenoise_iYSupport"                      */
+	0x0F122803, /* "UVDenoise_iUVSupportDSMix1_iLowPower_Wide"                        */
+	0x0F122811, /* "DSMix1_iLowPower_Wide_BinDSMix1_iHighPower_Wide"                  */
+	0x0F120A0F, /* "DSMix1_iHighPower_Wide_BinDSMix1_iLowThresh_Wide"                 */
+	0x0F12050A, /* "DSMix1_iHighThresh_WideDSMix1_iReduceNegativeWide"                */
+	0x0F122020, /* "DSMix1_iLowPower_FineDSMix1_iLowPower_Fine_Bin"                   */
+	0x0F122020, /* "DSMix1_iHighPower_FineDSMix1_iHighPower_Fine_Bin"                 */
+	0x0F12980A, /* "DSMix1_iLowThresh_FineDSMix1_iHighThresh_Fine"                    */
+	0x0F120007, /* "DSMix1_iReduceNegativeFineDSMix1_iRGBMultiplier"                  */
+	0x0F120408, /* "Mixer1_iNLowNoisePowerMixer1_iNLowNoisePower_Bin"                 */
+	0x0F120406, /* "Mixer1_iNVeryLowNoisePowerMixer1_iNVeryLowNoisePower_Bin"         */
+	0x0F120000, /* "Mixer1_iNHighNoisePowerMixer1_iNHighNoisePower_Bin"               */
+	0x0F120608, /* "Mixer1_iWLowNoisePowerMixer1_iWVeryLowNoisePower"                 */
+	0x0F120000, /* "Mixer1_iWHighNoisePowerMixer1_iWLowNoiseCeilGain"                 */
+	0x0F121006, /* "Mixer1_iWHighNoiseCeilGainMixer1_iWNoiseCeilGain"                 */
+	0x0F120180, /* "CCM_Oscar_iSaturationCCM_Oscar_bSaturation"                       */
+	0x0F120180, /* "RGBGamma2_iLinearityRGBGamma2_bLinearity"                         */
+	0x0F120100, /* "RGBGamma2_iDarkReduceRGBGamma2_bDarkReduce"                       */
+	0x0F128050, /* "byr_gas2_iShadingPowerRGB2YUV_iRGBGain"                           */
+	0x0F120180, /* "RGB2YUV_iSaturationRGB2YUV_bGainOffset"                           */
+	0x0F120000, /*  RGB2YUV_iYOffset                                                  */
+	
+	0x0F1200FF,
+	0x0F1200FF,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120000,
+	0x0F120300,
+	0x0F120002,
+	0x0F120400,
+	0x0F120106,
+	0x0F120005,
+	0x0F120000,
+	0x0F120703,
+	0x0F120000,
+	0x0F12FFD6,
+	0x0F1253C1,
+	0x0F12E1FE,
+	0x0F120001,
+	
+	/* Update Changed Registers */
+	0x002A03FC,
+	0x0F120001, /* REG_TC_DBG_ReInitCmd */
+	
+	0x0028D000,
+	0x002AB0CC,
+	0x0F12000B, /* Non contious mode */
+	/* Recording 25fps Anti-Flicker 50Hz END of Initial */
+};
+
+static const u32 s5k5bafx_stream_stop[] =
+{
+	0xFCFCD000,
+	0x00287000,
+ 	0x002A01F0,
+	0x0F120000, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged*/
+	/*0xffff0096, 150ms*/
+};
+
+#if (0)
+static const u32 s5k5bafx_stream_start[] =
+{
+	0xFCFCD000,
+	0x002AB00C,
+	0x0F120001,
+};
+#endif
+
+/*=================================
+*	CAMERA_BRIGHTNESS_1 (1/9) M4   *
+==================================*/
+static const u32 s5k5bafx_bright_m4[] =
+{
+	/* Brightness -4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FF80, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+*	CAMERA_BRIGHTNESS_2 (2/9) M3  *
+==================================*/
+
+static const u32 s5k5bafx_bright_m3[] =
+{
+	/* Brightness -3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFBC, /* REG_TC_UserBrightness*/
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_3 (3/9) M2
+==================================*/
+static const u32 s5k5bafx_bright_m2[] =
+{
+	/* Brightness -2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFDC, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_4 (4/9) M1
+==================================*/
+
+static const u32 s5k5bafx_bright_m1[] =
+{
+	/* Brightness -1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F12FFF2, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_5 (5/9) Default
+==================================*/
+static const u32 s5k5bafx_bright_default[] =
+{
+	/* Brightness 0 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120000, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_6 (6/9) P1
+==================================*/
+static const u32 s5k5bafx_bright_p1[] =
+{
+	/* Brightness +1 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120020, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_7 (7/9) P2
+==================================*/
+static const u32 s5k5bafx_bright_p2[] =
+{
+	/* Brightness +2 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120040, /* REG_TC_UserBrightness */
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_8 (8/9) P3
+==================================*/
+static const u32 s5k5bafx_bright_p3[] =
+{
+	/* Brightness +3 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120060, /* REG_TC_UserBrightness */
+
+};
+
+/*=================================
+	CAMERA_BRIGHTNESS_9 (9/9) P4
+==================================*/
+static const u32 s5k5bafx_bright_p4[] =
+{
+	/* Brightness +4 */
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120080, /* REG_TC_UserBrightness */
+};
+
+/*******************************************************
+* CAMERA_VT_PRETTY_0 Default
+* 200s self cam pretty
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_default[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+
+	0x0F120000,
+	0x0F120002,
+	0x0F120008,
+	0x0F120018,
+	0x0F12005A,
+	0x0F1200DF,
+	0x0F12013F,
+	0x0F120186,
+	0x0F1201E6,
+	0x0F120236,
+	0x0F1202BA,
+	0x0F12032A,
+	0x0F120385,
+	0x0F1203C2,
+	0x0F1203EA,
+	0x0F1203FF,
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_1
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_1[] =
+{
+	/*0xffff000A,*/
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+
+	0x0F120000,
+	0x0F12000D,
+	0x0F12001B,
+	0x0F120046,
+	0x0F1200AA,
+	0x0F120120,
+	0x0F120190,
+	0x0F1201E0,
+	0x0F120250,
+	0x0F1202A5,
+	0x0F120320,
+	0x0F120370,
+	0x0F1203B0,
+	0x0F1203D8,
+	0x0F1203F2,
+	0x0F120400,
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_2				*
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_2[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+
+	0x0F120000, /* 0000 */
+	0x0F12000D, /* 000D */
+	0x0F12001B, /* 001B */
+	0x0F120055, /* 0050 */
+	0x0F1200C0, /* 00B4 */
+	0x0F120164, /* 0154 */
+	0x0F1201C0, /* 01B8 */
+	0x0F120220, /* 0212 */
+	0x0F1202A0, /* 0294 */
+	0x0F1202F0, /* 02E4 */
+	0x0F120365, /* 0352 */
+	0x0F1203A0, /* 0398 */
+	0x0F1203D4, /* 03D4 */
+	0x0F1203E8, /* 03E8 */
+	0x0F1203F7, /* 03F7 */
+	0x0F120400, /* 0400 */
+};
+
+
+/*******************************************************
+*	CAMERA_VT_PRETTY_3
+*******************************************************/
+static const u32 s5k5bafx_vt_pretty_3[] =
+{
+	/* 0xffff000A, */
+	0xFCFCD000,
+	0x00287000,
+	0x002A04CC,
+
+	0x0F120000, /* 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B,  */
+	0x0F120064, /* 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00DC,  */
+	0x0F120190, /* 95, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01EA,  */
+	0x0F120260, /* 0265, 024E,  */
+	0x0F1202E5, /* 02F0, 02DA,  */
+	0x0F12032A, /* 30, 0335, 0320,  */
+	0x0F12038A, /* 90, 0395, 038E,  */
+	0x0F1203C5, /* CA, 03D0, 03CA, / */
+	0x0F1203E0, /* E5, 03E8, 03E8,  */
+	0x0F1203EC, /* F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400,  */
+
+	0x0F120000, /* 0000, 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B, 001B,  */
+	0x0F120064, /* 0064, 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00E5, 00DC,  */
+	0x0F120190, /* 0195, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01F5, 01EA,  */
+	0x0F120260, /* 0260, 0265, 024E,  */
+	0x0F1202E5, /* 02E5, 02F0, 02DA,  */
+	0x0F12032A, /* 0330, 0335, 0320,  */
+	0x0F12038A, /* 0390, 0395, 038E,  */
+	0x0F1203C5, /* 03CA, 03D0, 03CA,  */
+	0x0F1203E0, /* 03E5, 03E8, 03E8,  */
+	0x0F1203EC, /* 03F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400, 0400,  */
+
+	0x0F120000, /* 0000, 0000, 0000,  */
+	0x0F12000D, /* 000D, 000D, 000D,  */
+	0x0F12001B, /* 001B, 001B, 001B,  */
+	0x0F120064, /* 0064, 0064, 0064,  */
+	0x0F1200E5, /* 00E5, 00E5, 00DC,  */
+	0x0F120190, /* 0195, 0195, 0186,  */
+	0x0F1201F5, /* 01F5, 01F5, 01EA,  */
+	0x0F120260, /* 0260, 0265, 024E,  */
+	0x0F1202E5, /* 02E5, 02F0, 02DA,  */
+	0x0F12032A, /* 0330, 0335, 0320,  */
+	0x0F12038A, /* 0390, 0395, 038E,  */
+	0x0F1203C5, /* 03CA, 03D0, 03CA,  */
+	0x0F1203E0, /* 03E5, 03E8, 03E8,  */
+	0x0F1203EC, /* 03F0, 03F2, 03F2,  */
+	0x0F1203F7, /* 03F7, 03F7, 03F7,  */
+	0x0F120400, /* 0400, 0400, 0400,  */
+};
+
+static const u32 s5k5bafx_vt_7fps[] =
+{
+	/* Fixed 7fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120535, /* 7fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_10fps[] =
+{
+	/*  Fixed 10fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F1203E8, /* 10fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync  */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged  */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_12fps[] =
+{
+	/*  Fixed 12fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F120341, /* 12fps */
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /* mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+static const u32 s5k5bafx_vt_15fps[] =
+{
+	/* Fixed 15fps Mode */
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0252,
+	0x0F120000, /* FrRateQualityType */
+	0x002A0250,
+	0x0F120002, /* usFrTimeType */
+	0x002A0254,
+	0x0F12029A, /* 15fps*/
+	0x0F120000,
+
+	0x002A021C,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0220,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F8,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A021E,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A01F0,
+	0x0F120001, /* REG_TC_GP_EnablePreview */
+	0x0F120001, /* REG_TC_GP_EnablePreviewChanged  */
+
+	0xffff0096, /* delay 150ms */
+
+	0x0028D000, /*mipi */
+	0x002AB0CC,
+	0x0F12000B,
+};
+
+/*******************************************************
+*	CAMERA_DTP_ON
+*******************************************************/
+static const u32 s5k5bafx_pattern_on[] = {
+	0xffff01f4, /* Delay 500ms*/
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12FFF0, /* SARR_uNormBrInDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrInDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrInDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrInDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrInDoor[4] */
+	
+	0x002A07F6,
+	0x0F12FFF0, /* SARR_uNormBrOutDoor[0] */
+	0x0F12FFF1, /* SARR_uNormBrOutDoor[1] */
+	0x0F12FFF2, /* SARR_uNormBrOutDoor[2] */
+	0x0F12FFF3, /* SARR_uNormBrOutDoor[3] */
+	0x0F12FFF4, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a3, /* gas bypass */
+	0x002a6600,
+	0x0f120001, /* ccm bypass */
+	0x002a6800,
+	0x0f120001, /* gamma bypass */
+	0x002a4400,
+	0x0f120001, /* awb bypass */
+
+	0x00287000,
+	0x002A03b6,
+	0x0F120001,
+	0x002A03ba,
+	0x0F120001, /* LEI control */
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120002, /* Colorbar pattern */
+	
+	0xffff0032, /* Delay 50msec */
+};
+
+/*******************************************************
+*	CAMERA_DTP_OFF
+*******************************************************/
+static const u32 s5k5bafx_pattern_off[] = {
+
+	0xfcfcd000,
+	0x00287000,
+
+	0x002A07EC,
+	0x0F12000A, /* SARR_uNormBrInDoor[0] */
+	0x0F120019, /* SARR_uNormBrInDoor[1] */
+	0x0F12007D, /* SARR_uNormBrInDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrInDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrInDoor[4] */
+
+	0x002A07F6,
+	0x0F12000A, /* SARR_uNormBrOutDoor[0] */
+	0x0F120019, /* SARR_uNormBrOutDoor[1] */
+	0x0F12007D, /* SARR_uNormBrOutDoor[2] */
+	0x0F1202BC, /* SARR_uNormBrOutDoor[3] */
+	0x0F1207D0, /* SARR_uNormBrOutDoor[4] */
+
+	0xfcfcd000,
+	0x0028d000,
+	0x002a4100,
+	0x0f1208a2, /* gas bypass */
+	0x002a6600,
+	0x0f120000, /* ccm bypass */
+	0x002a6800,
+	0x0f120000, /* gamma bypass */
+	0x002a4400,
+	0x0f120000, /* awb bypass */
+
+	0x00287000,
+	0x002A03F8,
+	0x0F120079,
+
+	0xffff012c, /* Delay 300ms */
+	0x002A03F8,
+	0x0F12007F,
+
+	0x0028D000,
+	0x002A3118,
+	0x0F120320, /* Colorbar pattern x size */
+	0x0F120258, /* Colorbar pattern y size */
+	0x0F120000,
+	0x002A3100,
+	0x0F120000, /* Colorbar pattern */
+};
+
+#endif /* __S5K5BAFX_SETFILE_H */
diff --git a/drivers/media/video/s5k5ccgx.c b/drivers/media/video/s5k5ccgx.c
new file mode 100644
index 0000000..2123304
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx.c
@@ -0,0 +1,3199 @@
+/* drivers/media/video/s5k5ccgx.c
+ *
+ * Copyright (c) 2010, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include "s5k5ccgx.h"
+
+static int s5k5ccgx_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl);
+
+static const struct s5k5ccgx_fps s5k5ccgx_framerates[] = {
+	{ I_FPS_0,	FRAME_RATE_AUTO },
+	{ I_FPS_15,	FRAME_RATE_15 },
+	{ I_FPS_25,	FRAME_RATE_25 },
+	{ I_FPS_30,	FRAME_RATE_30 },
+};
+
+static const struct s5k5ccgx_framesize s5k5ccgx_preview_frmsizes[] = {
+	{ S5K5CCGX_PREVIEW_QCIF,	176,  144 },
+	{ S5K5CCGX_PREVIEW_320x240,	320,  240 },
+	{ S5K5CCGX_PREVIEW_CIF,		352,  288 },
+	{ S5K5CCGX_PREVIEW_528x432,	528,  432 },
+	{ S5K5CCGX_PREVIEW_VGA,		640,  480 },
+	{ S5K5CCGX_PREVIEW_D1,		720,  480 },
+	{ S5K5CCGX_PREVIEW_SVGA,	800,  600 },
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+	{ S5K5CCGX_PREVIEW_1024x552,	1024, 552 },
+#else
+	{ S5K5CCGX_PREVIEW_1024x576,	1024, 576 },
+#endif
+	/*{ S5K5CCGX_PREVIEW_1024x616,	1024, 616 },*/
+	{ S5K5CCGX_PREVIEW_XGA,		1024, 768 },
+	{ S5K5CCGX_PREVIEW_PVGA,	1280, 720 },
+};
+
+static const struct s5k5ccgx_framesize s5k5ccgx_capture_frmsizes[] = {
+	{ S5K5CCGX_CAPTURE_VGA,		640,  480 },
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+	{ S5K5CCGX_CAPTURE_W2MP,	2048, 1104 },
+#else
+	{ S5K5CCGX_CAPTURE_W2MP,	2048, 1152 },
+#endif
+	{ S5K5CCGX_CAPTURE_3MP,		2048, 1536 },
+};
+
+static struct s5k5ccgx_control s5k5ccgx_ctrls[] = {
+	S5K5CCGX_INIT_CONTROL(V4L2_CID_CAMERA_FLASH_MODE, \
+					FLASH_MODE_OFF),
+
+	S5K5CCGX_INIT_CONTROL(V4L2_CID_CAMERA_BRIGHTNESS, \
+					EV_DEFAULT),
+
+	S5K5CCGX_INIT_CONTROL(V4L2_CID_CAMERA_METERING, \
+					METERING_MATRIX),
+
+	S5K5CCGX_INIT_CONTROL(V4L2_CID_CAMERA_WHITE_BALANCE, \
+					WHITE_BALANCE_AUTO),
+
+	S5K5CCGX_INIT_CONTROL(V4L2_CID_CAMERA_EFFECT, \
+					IMAGE_EFFECT_NONE),
+};
+
+static const struct s5k5ccgx_regs reg_datas = {
+	.ev = {
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_MINUS_4),
+					s5k5ccgx_brightness_m_4),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_MINUS_3),
+					s5k5ccgx_brightness_m_3),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_MINUS_2),
+					s5k5ccgx_brightness_m_2),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_MINUS_1),
+					s5k5ccgx_brightness_m_1),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_DEFAULT),
+					s5k5ccgx_brightness_0),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_PLUS_1),
+					s5k5ccgx_brightness_p_1),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_PLUS_2),
+					s5k5ccgx_brightness_p_2),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_PLUS_3),
+					s5k5ccgx_brightness_p_3),
+		S5K5CCGX_REGSET(GET_EV_INDEX(EV_PLUS_4),
+					s5k5ccgx_brightness_p_4),
+	},
+	.metering = {
+		S5K5CCGX_REGSET(METERING_MATRIX, s5k5ccgx_metering_normal),
+		S5K5CCGX_REGSET(METERING_CENTER, s5k5ccgx_metering_center),
+		S5K5CCGX_REGSET(METERING_SPOT, s5k5ccgx_metering_spot),
+	},
+	.iso = {
+		S5K5CCGX_REGSET(ISO_AUTO, s5k5ccgx_iso_auto),
+		S5K5CCGX_REGSET(ISO_100, s5k5ccgx_iso_100),
+		S5K5CCGX_REGSET(ISO_200, s5k5ccgx_iso_200),
+		S5K5CCGX_REGSET(ISO_400, s5k5ccgx_iso_400),
+	},
+	.effect = {
+		S5K5CCGX_REGSET(IMAGE_EFFECT_NONE, s5k5ccgx_effect_off),
+		S5K5CCGX_REGSET(IMAGE_EFFECT_BNW, s5k5ccgx_effect_mono),
+		S5K5CCGX_REGSET(IMAGE_EFFECT_SEPIA, s5k5ccgx_effect_sepia),
+		S5K5CCGX_REGSET(IMAGE_EFFECT_NEGATIVE,
+				s5k5ccgx_effect_negative),
+	},
+	.white_balance = {
+		S5K5CCGX_REGSET(WHITE_BALANCE_AUTO, s5k5ccgx_wb_auto),
+		S5K5CCGX_REGSET(WHITE_BALANCE_SUNNY, s5k5ccgx_wb_daylight),
+		S5K5CCGX_REGSET(WHITE_BALANCE_CLOUDY, s5k5ccgx_wb_cloudy),
+		S5K5CCGX_REGSET(WHITE_BALANCE_TUNGSTEN,
+				s5k5ccgx_wb_incandescent),
+		S5K5CCGX_REGSET(WHITE_BALANCE_FLUORESCENT,
+				s5k5ccgx_wb_fluorescent),
+	},
+	.preview_size = {
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_QCIF,
+				s5k5ccgx_176_144_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_320x240,
+				s5k5ccgx_320_240_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_CIF, s5k5ccgx_352_288_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_528x432,
+				s5k5ccgx_528_432_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_VGA, s5k5ccgx_640_480_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_D1, s5k5ccgx_720_480_Preview),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_SVGA,
+				s5k5ccgx_800_600_Preview),
+		S5K5CCGX_REGSET(PREVIEW_WIDE_SIZE,
+				S5K5CCGX_WIDE_PREVIEW_REG),
+		S5K5CCGX_REGSET(S5K5CCGX_PREVIEW_XGA,
+				s5k5ccgx_1024_768_Preview),
+	},
+	.scene_mode = {
+		S5K5CCGX_REGSET(SCENE_MODE_NONE, s5k5ccgx_scene_off),
+		S5K5CCGX_REGSET(SCENE_MODE_PORTRAIT, s5k5ccgx_scene_portrait),
+		S5K5CCGX_REGSET(SCENE_MODE_NIGHTSHOT, s5k5ccgx_scene_nightshot),
+		S5K5CCGX_REGSET(SCENE_MODE_LANDSCAPE, s5k5ccgx_scene_landscape),
+		S5K5CCGX_REGSET(SCENE_MODE_SPORTS, s5k5ccgx_scene_sports),
+		S5K5CCGX_REGSET(SCENE_MODE_PARTY_INDOOR, s5k5ccgx_scene_party),
+		S5K5CCGX_REGSET(SCENE_MODE_BEACH_SNOW, s5k5ccgx_scene_beach),
+		S5K5CCGX_REGSET(SCENE_MODE_SUNSET, s5k5ccgx_scene_sunset),
+		S5K5CCGX_REGSET(SCENE_MODE_DUSK_DAWN, s5k5ccgx_scene_dawn),
+		S5K5CCGX_REGSET(SCENE_MODE_TEXT, s5k5ccgx_scene_text),
+		S5K5CCGX_REGSET(SCENE_MODE_CANDLE_LIGHT, s5k5ccgx_scene_candle),
+	},
+	.saturation = {
+		S5K5CCGX_REGSET(SATURATION_MINUS_2, s5k5ccgx_saturation_m_2),
+		S5K5CCGX_REGSET(SATURATION_MINUS_1, s5k5ccgx_saturation_m_1),
+		S5K5CCGX_REGSET(SATURATION_DEFAULT, s5k5ccgx_saturation_0),
+		S5K5CCGX_REGSET(SATURATION_PLUS_1, s5k5ccgx_saturation_p_1),
+		S5K5CCGX_REGSET(SATURATION_PLUS_2, s5k5ccgx_saturation_p_2),
+	},
+	.contrast = {
+		S5K5CCGX_REGSET(CONTRAST_MINUS_2, s5k5ccgx_contrast_m_2),
+		S5K5CCGX_REGSET(CONTRAST_MINUS_1, s5k5ccgx_contrast_m_1),
+		S5K5CCGX_REGSET(CONTRAST_DEFAULT, s5k5ccgx_contrast_0),
+		S5K5CCGX_REGSET(CONTRAST_PLUS_1, s5k5ccgx_contrast_p_1),
+		S5K5CCGX_REGSET(CONTRAST_PLUS_2, s5k5ccgx_contrast_p_2),
+
+	},
+	.sharpness = {
+		S5K5CCGX_REGSET(SHARPNESS_MINUS_2, s5k5ccgx_sharpness_m_2),
+		S5K5CCGX_REGSET(SHARPNESS_MINUS_1, s5k5ccgx_sharpness_m_1),
+		S5K5CCGX_REGSET(SHARPNESS_DEFAULT, s5k5ccgx_sharpness_0),
+		S5K5CCGX_REGSET(SHARPNESS_PLUS_1, s5k5ccgx_sharpness_p_1),
+		S5K5CCGX_REGSET(SHARPNESS_PLUS_2, s5k5ccgx_sharpness_p_2),
+	},
+	.fps = {
+		S5K5CCGX_REGSET(I_FPS_0, s5k5ccgx_fps_auto),
+		S5K5CCGX_REGSET(I_FPS_15, s5k5ccgx_fps_15fix),
+		S5K5CCGX_REGSET(I_FPS_25, s5k5ccgx_fps_25fix),
+		S5K5CCGX_REGSET(I_FPS_30, s5k5ccgx_fps_30fix),
+	},
+	.preview_return = S5K5CCGX_REGSET_TABLE(s5k5ccgx_preview_return),
+
+	.flash_start = S5K5CCGX_REGSET_TABLE(s5k5ccgx_mainflash_start),
+	.flash_end = S5K5CCGX_REGSET_TABLE(s5k5ccgx_mainflash_end),
+	.af_pre_flash_start =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_preflash_start),
+	.af_pre_flash_end =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_preflash_end),
+	.flash_ae_set =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_flash_ae_set),
+	.flash_ae_clear =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_flash_ae_clear),
+	.ae_lock_on =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_ae_lock),
+	.ae_lock_off =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_ae_unlock),
+	.awb_lock_on =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_awb_lock),
+	.awb_lock_off =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_awb_unlock),
+
+	.restore_cap = S5K5CCGX_REGSET_TABLE(s5k5ccgx_restore_capture_reg),
+	.change_wide_cap = S5K5CCGX_REGSET_TABLE(s5k5ccgx_change_wide_cap),
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+	.set_lowlight_cap = S5K5CCGX_REGSET_TABLE(s5k5ccgx_set_lowlight_reg),
+#endif
+
+	.af_macro_mode = S5K5CCGX_REGSET_TABLE(s5k5ccgx_af_macro_on),
+	.af_normal_mode = S5K5CCGX_REGSET_TABLE(s5k5ccgx_af_normal_on),
+#if !defined(CONFIG_VIDEO_S5K5CCGX_P2)
+	.af_night_normal_mode =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_af_night_normal_on),
+#endif
+#ifdef CONFIG_VIDEO_S5K5CCGX_P4W
+	.af_off = S5K5CCGX_REGSET_TABLE(s5k5ccgx_af_off_reg),
+#endif
+	.hd_af_start = S5K5CCGX_REGSET_TABLE(s5k5ccgx_720P_af_do),
+	.hd_first_af_start = S5K5CCGX_REGSET_TABLE(s5k5ccgx_1st_720P_af_do),
+	.single_af_start = S5K5CCGX_REGSET_TABLE(s5k5ccgx_af_do),
+	.capture_start = {
+		S5K5CCGX_REGSET(S5K5CCGX_CAPTURE_VGA, s5k5ccgx_snapshot_vga),
+		S5K5CCGX_REGSET(S5K5CCGX_CAPTURE_W2MP, s5k5ccgx_snapshot),
+		S5K5CCGX_REGSET(S5K5CCGX_CAPTURE_3MP, s5k5ccgx_snapshot),
+	},
+	.init_reg = S5K5CCGX_REGSET_TABLE(s5k5ccgx_init_reg),
+	.get_esd_status = S5K5CCGX_REGSET_TABLE(s5k5ccgx_get_esd_reg),
+	.stream_stop = S5K5CCGX_REGSET_TABLE(s5k5ccgx_stream_stop_reg),
+	.get_light_level = S5K5CCGX_REGSET_TABLE(s5k5ccgx_get_light_status),
+	.get_iso = S5K5CCGX_REGSET_TABLE(s5k5ccgx_get_iso_reg),
+	.get_ae_stable = S5K5CCGX_REGSET_TABLE(s5k5ccgx_get_ae_stable_reg),
+	.get_shutterspeed =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_get_shutterspeed_reg),
+	.update_preview = S5K5CCGX_REGSET_TABLE(s5k5ccgx_update_preview_reg),
+	.update_hd_preview =
+		S5K5CCGX_REGSET_TABLE(s5k5ccgx_update_hd_preview_reg),
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+	.antibanding = S5K5CCGX_REGSET_TABLE(S5K5CCGX_ANTIBANDING_REG),
+#endif
+};
+
+static const struct v4l2_mbus_framefmt capture_fmts[] = {
+	{
+		.code		= V4L2_MBUS_FMT_FIXED,
+		.colorspace	= V4L2_COLORSPACE_JPEG,
+	},
+};
+
+#ifdef CONFIG_LOAD_FILE
+static int loadFile(void)
+{
+	struct file *fp = NULL;
+	struct test *nextBuf = NULL;
+
+	u8 *nBuf = NULL;
+	size_t file_size = 0, max_size = 0, testBuf_size = 0;
+	ssize_t nread = 0;
+	s32 check = 0, starCheck = 0;
+	s32 tmp_large_file = 0;
+	s32 i = 0;
+	int ret = 0;
+	loff_t pos;
+
+	mm_segment_t fs = get_fs();
+	set_fs(get_ds());
+
+	cam_info("%s: E\n", __func__);
+
+	BUG_ON(testBuf);
+
+	fp = filp_open(TUNING_FILE_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("file open error\n");
+		return PTR_ERR(fp);
+	}
+
+	file_size = (size_t) fp->f_path.dentry->d_inode->i_size;
+	max_size = file_size;
+
+	cam_dbg("file_size = %d\n", file_size);
+
+	nBuf = kmalloc(file_size, GFP_ATOMIC);
+	if (nBuf == NULL) {
+		cam_dbg("Fail to 1st get memory\n");
+		nBuf = vmalloc(file_size);
+		if (nBuf == NULL) {
+			cam_err("ERR: nBuf Out of Memory\n");
+			ret = -ENOMEM;
+			goto error_out;
+		}
+		tmp_large_file = 1;
+	}
+
+	testBuf_size = sizeof(struct test) * file_size;
+	if (tmp_large_file) {
+		testBuf = (struct test *)vmalloc(testBuf_size);
+		large_file = 1;
+	} else {
+		testBuf = kmalloc(testBuf_size, GFP_ATOMIC);
+		if (testBuf == NULL) {
+			cam_dbg("Fail to get mem(%d bytes)\n", testBuf_size);
+			testBuf = (struct test *)vmalloc(testBuf_size);
+			large_file = 1;
+		}
+	}
+	if (testBuf == NULL) {
+		cam_err("ERR: Out of Memory\n");
+		ret = -ENOMEM;
+		goto error_out;
+	}
+
+	pos = 0;
+	memset(nBuf, 0, file_size);
+	memset(testBuf, 0, file_size * sizeof(struct test));
+
+	nread = vfs_read(fp, (char __user *)nBuf, file_size, &pos);
+	if (nread != file_size) {
+		cam_err("failed to read file ret = %d\n", nread);
+		ret = -1;
+		goto error_out;
+	}
+
+	set_fs(fs);
+
+	i = max_size;
+
+	printk(KERN_DEBUG "i = %d\n", i);
+
+	while (i) {
+		testBuf[max_size - i].data = *nBuf;
+		if (i != 1) {
+			testBuf[max_size - i].nextBuf =
+				&testBuf[max_size - i + 1];
+		} else {
+			testBuf[max_size - i].nextBuf = NULL;
+			break;
+		}
+		i--;
+		nBuf++;
+	}
+
+	i = max_size;
+	nextBuf = &testBuf[0];
+
+#if 1
+	while (i - 1) {
+		if (!check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+								== '/') {
+						check = 1;/* when find '//' */
+						i--;
+					} else if (
+					    testBuf[max_size-i].nextBuf->data
+					    == '*') {
+						/* when find '/ *' */
+						starCheck = 1;
+						i--;
+					}
+				} else
+					break;
+			}
+			if (!check && !starCheck) {
+				/* ignore '\t' */
+				if (testBuf[max_size - i].data != '\t') {
+					nextBuf->nextBuf = &testBuf[max_size-i];
+					nextBuf = &testBuf[max_size - i];
+				}
+			}
+		} else if (check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+					    == '*') {
+						/* when find '/ *' */
+						starCheck = 1;
+						check = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+
+			 /* when find '\n' */
+			if (testBuf[max_size - i].data == '\n' && check) {
+				check = 0;
+				nextBuf->nextBuf = &testBuf[max_size - i];
+				nextBuf = &testBuf[max_size - i];
+			}
+
+		} else if (!check && starCheck) {
+			if (testBuf[max_size - i].data == '*') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+					    == '/') {
+						/* when find '* /' */
+						starCheck = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+		}
+
+		i--;
+
+		if (i < 2) {
+			nextBuf = NULL;
+			break;
+		}
+
+		if (testBuf[max_size - i].nextBuf == NULL) {
+			nextBuf = NULL;
+			break;
+		}
+	}
+#endif
+
+#if 0 /* for print */
+	cam_dbg("i = %d\n", i);
+	nextBuf = &testBuf[0];
+	while (1) {
+		if (nextBuf->nextBuf == NULL)
+			break;
+		cam_dbg("%c", nextBuf->data);
+		nextBuf = nextBuf->nextBuf;
+	}
+#endif
+
+error_out:
+	tmp_large_file ? vfree(nBuf) : kfree(nBuf);
+
+	if (fp)
+		filp_close(fp, current->files);
+	return ret;
+}
+
+
+#endif
+
+/**
+ * s5k5ccgx_i2c_read_twobyte: Read 2 bytes from sensor
+ */
+static int s5k5ccgx_i2c_read_twobyte(struct i2c_client *client,
+				  u16 subaddr, u16 *data)
+{
+	int err;
+	u8 buf[2];
+	struct i2c_msg msg[2];
+
+	cpu_to_be16s(&subaddr);
+
+	msg[0].addr = client->addr;
+	msg[0].flags = 0;
+	msg[0].len = 2;
+	msg[0].buf = (u8 *)&subaddr;
+
+	msg[1].addr = client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = 2;
+	msg[1].buf = buf;
+
+	err = i2c_transfer(client->adapter, msg, 2);
+	CHECK_ERR_COND_MSG(err != 2, -EIO, "fail to read register\n");
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return 0;
+}
+
+/**
+ * s5k5ccgx_i2c_write_twobyte: Write (I2C) multiple bytes to the camera sensor
+ * @client: pointer to i2c_client
+ * @cmd: command register
+ * @w_data: data to be written
+ * @w_len: length of data to be written
+ *
+ * Returns 0 on success, <0 on error
+ */
+static int s5k5ccgx_i2c_write_twobyte(struct i2c_client *client,
+					 u16 addr, u16 w_data)
+{
+	int retry_count = 5;
+	int ret = 0;
+	u8 buf[4] = {0,};
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.len	= 4,
+		.buf	= buf,
+	};
+
+	buf[0] = addr >> 8;
+	buf[1] = addr;
+	buf[2] = w_data >> 8;
+	buf[3] = w_data & 0xff;
+
+#if (0)
+	s5k5ccgx_debug(S5K5CCGX_DEBUG_I2C, "%s : W(0x%02X%02X%02X%02X)\n",
+		__func__, buf[0], buf[1], buf[2], buf[3]);
+#else
+	/* cam_dbg("I2C writing: 0x%02X%02X%02X%02X\n",
+			buf[0], buf[1], buf[2], buf[3]); */
+#endif
+
+	do {
+		ret = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(ret == 1))
+			break;
+		msleep(POLL_TIME_MS);
+		cam_err("%s: ERROR(%d), write (%04X, %04X), retry %d.\n",
+				__func__, ret, addr, w_data, retry_count);
+	} while (retry_count-- > 0);
+
+	CHECK_ERR_COND_MSG(ret != 1, -EIO, "I2C does not working.\n\n");
+
+	return 0;
+}
+
+/* PX: */
+#ifdef CONFIG_LOAD_FILE
+static int s5k5ccgx_write_regs_from_sd(struct v4l2_subdev *sd,
+						const u8 s_name[])
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct test *tempData = NULL;
+
+	int ret = -EAGAIN;
+	u32 temp;
+	u32 delay = 0;
+	u8 data[11];
+	s32 searched = 0;
+	size_t size = strlen(s_name);
+	s32 i;
+#ifdef DEBUG_WRITE_REGS
+	u8 regs_name[128] = {0,};
+
+	BUG_ON(size > sizeof(regs_name));
+#endif
+
+	cam_dbg("%s: E size = %d, string = %s\n", __func__, size, s_name);
+	tempData = &testBuf[0];
+	while (!searched) {
+		searched = 1;
+		for (i = 0; i < size; i++) {
+			if (tempData->data != s_name[i]) {
+				searched = 0;
+				break;
+			}
+#ifdef DEBUG_WRITE_REGS
+			regs_name[i] = tempData->data;
+#endif
+			tempData = tempData->nextBuf;
+		}
+#ifdef DEBUG_WRITE_REGS
+		if (i > 9) {
+			regs_name[i] = '\0';
+			cam_dbg("Searching: regs_name = %s\n", regs_name);
+		}
+#endif
+		tempData = tempData->nextBuf;
+	}
+	/* structure is get..*/
+#ifdef DEBUG_WRITE_REGS
+	regs_name[i] = '\0';
+	cam_dbg("Searched regs_name = %s\n\n", regs_name);
+#endif
+
+	while (1) {
+		if (tempData->data == '{')
+			break;
+		else
+			tempData = tempData->nextBuf;
+	}
+
+	while (1) {
+		searched = 0;
+		while (1) {
+			if (tempData->data == 'x') {
+				/* get 10 strings.*/
+				data[0] = '0';
+				for (i = 1; i < 11; i++) {
+					data[i] = tempData->data;
+					tempData = tempData->nextBuf;
+				}
+				/*cam_dbg("%s\n", data);*/
+				temp = simple_strtoul(data, NULL, 16);
+				break;
+			} else if (tempData->data == '}') {
+				searched = 1;
+				break;
+			} else
+				tempData = tempData->nextBuf;
+
+			if (tempData->nextBuf == NULL)
+				return -1;
+		}
+
+		if (searched)
+			break;
+
+		if ((temp & S5K5CCGX_DELAY) == S5K5CCGX_DELAY) {
+			delay = temp & 0x0FFFF;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+		/* cam_dbg("I2C writing: 0x%08X,\n",temp);*/
+		ret = s5k5ccgx_i2c_write_twobyte(client,
+			(temp >> 16), (u16)temp);
+
+		/* In error circumstances */
+		/* Give second shot */
+		if (unlikely(ret)) {
+			dev_info(&client->dev,
+					"s5k5ccgx i2c retry one more time\n");
+			ret = s5k5ccgx_i2c_write_twobyte(client,
+				(temp >> 16), (u16)temp);
+
+			/* Give it one more shot */
+			if (unlikely(ret)) {
+				dev_info(&client->dev,
+						"s5k5ccgx i2c retry twice\n");
+				ret = s5k5ccgx_i2c_write_twobyte(client,
+					(temp >> 16), (u16)temp);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+/* Write register
+ * If success, return value: 0
+ * If fail, return value: -EIO
+ */
+static int s5k5ccgx_write_regs(struct v4l2_subdev *sd, const u32 regs[],
+			     int size)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 delay = 0;
+	int i, err = 0;
+
+	for (i = 0; i < size; i++) {
+		if ((regs[i] & S5K5CCGX_DELAY) == S5K5CCGX_DELAY) {
+			delay = regs[i] & 0xFFFF;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+		err = s5k5ccgx_i2c_write_twobyte(client,
+			(regs[i] >> 16), regs[i]);
+		CHECK_ERR_MSG(err, "write registers\n")
+	}
+
+	return 0;
+}
+
+#if 0
+static int s5k5ccgx_i2c_write_block(struct v4l2_subdev *sd, u8 *buf, u32 size)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int retry_count = 5;
+	int ret = 0;
+	struct i2c_msg msg = {client->addr, 0, size, buf};
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_DEBUG
+	if (s5k5ccgx_debug_mask & S5K5CCGX_DEBUG_I2C_BURSTS) {
+		if ((buf[0] == 0x0F) && (buf[1] == 0x12))
+			pr_info("%s : data[0,1] = 0x%02X%02X,"
+				" total data size = %d\n",
+				__func__, buf[2], buf[3], size-2);
+		else
+			pr_info("%s : 0x%02X%02X%02X%02X\n",
+				__func__, buf[0], buf[1], buf[2], buf[3]);
+	}
+#endif
+
+	do {
+		ret = i2c_transfer(client->adapter, &msg, 1);
+		if (likely(ret == 1))
+			break;
+		msleep(POLL_TIME_MS);
+	} while (retry_count-- > 0);
+	if (ret != 1) {
+		dev_err(&client->dev, "%s: I2C is not working.\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif
+
+#define BURST_MODE_BUFFER_MAX_SIZE 2700
+u8 s5k5ccgx_burstmode_buf[BURST_MODE_BUFFER_MAX_SIZE];
+
+/* PX: */
+static int s5k5ccgx_burst_write_regs(struct v4l2_subdev *sd,
+			const u32 list[], u32 size, char *name)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+	int i = 0, idx = 0;
+	u16 subaddr = 0, next_subaddr = 0, value = 0;
+	struct i2c_msg msg = {
+		.addr	= client->addr,
+		.flags	= 0,
+		.len	= 0,
+		.buf	= s5k5ccgx_burstmode_buf,
+	};
+
+	cam_trace("E\n");
+
+	for (i = 0; i < size; i++) {
+		CHECK_ERR_COND_MSG((idx > (BURST_MODE_BUFFER_MAX_SIZE - 10)),
+			err, "BURST MOD buffer overflow!\n")
+
+		subaddr = (list[i] & 0xFFFF0000) >> 16;
+		if (subaddr == 0x0F12)
+			next_subaddr = (list[i+1] & 0xFFFF0000) >> 16;
+
+		value = list[i] & 0x0000FFFF;
+
+		switch (subaddr) {
+		case 0x0F12:
+			/* make and fill buffer for burst mode write. */
+			if (idx == 0) {
+				s5k5ccgx_burstmode_buf[idx++] = 0x0F;
+				s5k5ccgx_burstmode_buf[idx++] = 0x12;
+			}
+			s5k5ccgx_burstmode_buf[idx++] = value >> 8;
+			s5k5ccgx_burstmode_buf[idx++] = value & 0xFF;
+
+			/* write in burstmode*/
+			if (next_subaddr != 0x0F12) {
+				msg.len = idx;
+				err = i2c_transfer(client->adapter,
+					&msg, 1) == 1 ? 0 : -EIO;
+				CHECK_ERR_MSG(err, "i2c_transfer\n");
+				/* cam_dbg("s5k5ccgx_sensor_burst_write,
+						idx = %d\n", idx); */
+				idx = 0;
+			}
+			break;
+
+		case 0xFFFF:
+			debug_msleep(sd, value);
+			break;
+
+		default:
+			idx = 0;
+			err = s5k5ccgx_i2c_write_twobyte(client,
+						subaddr, value);
+			CHECK_ERR_MSG(err, "i2c_write_twobytes\n");
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/* PX: */
+static int s5k5ccgx_set_from_table(struct v4l2_subdev *sd,
+				const char *setting_name,
+				const struct s5k5ccgx_regset_table *table,
+				u32 table_size, s32 index)
+{
+	int err = 0;
+
+	/* cam_dbg("%s: set %s index %d\n",
+		__func__, setting_name, index); */
+	CHECK_ERR_COND_MSG(((index < 0) || (index >= table_size)),
+		-EINVAL, "index(%d) out of range[0:%d] for table for %s\n",
+		index, table_size, setting_name);
+
+	table += index;
+	CHECK_ERR_COND_MSG(!table->reg, -EFAULT, \
+		"table=%s, index=%d, reg = NULL\n", setting_name, index);
+
+#ifdef CONFIG_LOAD_FILE
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__,
+			setting_name, table->name);
+	return s5k5ccgx_write_regs_from_sd(sd, table->name);
+
+#else /* CONFIG_LOAD_FILE */
+
+# ifdef DEBUG_WRITE_REGS
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__,
+			setting_name, table->name);
+# endif /* DEBUG_WRITE_REGS */
+
+	err = s5k5ccgx_write_regs(sd, table->reg, table->array_size);
+	CHECK_ERR_MSG(err, "write regs(%s), err=%d\n", setting_name, err);
+
+	return 0;
+#endif /* CONFIG_LOAD_FILE */
+}
+
+/* PX: */
+static inline int s5k5ccgx_save_ctrl(struct v4l2_subdev *sd,
+					struct v4l2_control *ctrl)
+{
+	int ctrl_cnt = ARRAY_SIZE(s5k5ccgx_ctrls);
+	int i;
+
+	/* cam_trace("E, Ctrl-ID = 0x%X", ctrl->id);*/
+
+	for (i = 0; i < ctrl_cnt; i++) {
+		if (ctrl->id == s5k5ccgx_ctrls[i].id) {
+			s5k5ccgx_ctrls[i].value = ctrl->value;
+			break;
+		}
+	}
+
+	if (unlikely(i >= ctrl_cnt))
+		cam_trace("WARNING, not saved ctrl-ID=0x%X\n", ctrl->id);
+
+	return 0;
+}
+
+/**
+ * s5k5ccgx_is_hwflash_on - check whether flash device is on
+ *
+ * Refer to state->flash_on to check whether flash is in use in driver.
+ */
+static inline int s5k5ccgx_is_hwflash_on(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+#ifdef S5K5CCGX_SUPPORT_FLASH
+	return state->pdata->is_flash_on();
+#else
+	return 0;
+#endif
+}
+
+/**
+ * s5k5ccgx_flash_en - contro Flash LED
+ * @mode: S5K5CCGX_FLASH_MODE_NORMAL or S5K5CCGX_FLASH_MODE_MOVIE
+ * @onoff: S5K5CCGX_FLASH_ON or S5K5CCGX_FLASH_OFF
+ */
+static int s5k5ccgx_flash_en(struct v4l2_subdev *sd, s32 mode, s32 onoff)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	if (unlikely(state->ignore_flash)) {
+		cam_warn("WARNING, we ignore flash command.\n");
+		return 0;
+	}
+
+#ifdef S5K5CCGX_SUPPORT_FLASH
+	return state->pdata->flash_en(mode, onoff);
+#endif
+	return 0;
+}
+
+/**
+ * s5k5ccgx_flash_torch - turn flash on/off as torch for preflash, recording
+ * @onoff: S5K5CCGX_FLASH_ON or S5K5CCGX_FLASH_OFF
+ *
+ * This func set state->flash_on properly.
+ */
+static inline int s5k5ccgx_flash_torch(struct v4l2_subdev *sd, s32 onoff)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	err = s5k5ccgx_flash_en(sd, S5K5CCGX_FLASH_MODE_MOVIE, onoff);
+	state->flash_on = (onoff == S5K5CCGX_FLASH_ON) ? 1 : 0;
+
+	return err;
+}
+
+/**
+ * s5k5ccgx_flash_oneshot - turn main flash on for capture
+ * @onoff: S5K5CCGX_FLASH_ON or S5K5CCGX_FLASH_OFF
+ *
+ * Main flash is turn off automatically in some milliseconds.
+ */
+static inline int s5k5ccgx_flash_oneshot(struct v4l2_subdev *sd, s32 onoff)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	err = s5k5ccgx_flash_en(sd, S5K5CCGX_FLASH_MODE_NORMAL, onoff);
+
+	/* The flash_on here is only used for EXIF */
+	state->flash_on = (onoff == S5K5CCGX_FLASH_ON) ? 1 : 0;
+
+	return err;
+}
+
+/* PX: Set scene mode */
+static int s5k5ccgx_set_scene_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -ENODEV;
+
+	cam_trace("E, value %d\n", val);
+
+	if (state->scene_mode == val)
+		return 0;
+
+	/* when scene mode is switched,
+	 * we frist have to write scene_off.
+	 */
+	if (state->scene_mode != SCENE_MODE_NONE)
+		err = s5k5ccgx_set_from_table(sd, "scene_mode",
+			state->regs->scene_mode,
+			ARRAY_SIZE(state->regs->scene_mode), SCENE_MODE_NONE);
+
+	if (val != SCENE_MODE_NONE)
+		err = s5k5ccgx_set_from_table(sd, "scene_mode",
+			state->regs->scene_mode,
+			ARRAY_SIZE(state->regs->scene_mode), val);
+
+	state->scene_mode = val;
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Set brightness */
+static int s5k5ccgx_set_exposure(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if ((val < EV_MINUS_4) || (val > EV_PLUS_4)) {
+		cam_err("%s: ERROR, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = s5k5ccgx_set_from_table(sd, "brightness", state->regs->ev,
+		ARRAY_SIZE(state->regs->ev), GET_EV_INDEX(val));
+
+	return err;
+}
+
+/* PX: Check light level */
+static u32 s5k5ccgx_get_light_level(struct v4l2_subdev *sd, u32 *light_level)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_state *state = to_state(sd);
+	u16 val_lsb = 0;
+	u16 val_msb = 0;
+	int err = -ENODEV;
+
+	err = s5k5ccgx_set_from_table(sd, "get_light_level",
+			&state->regs->get_light_level, 1, 0);
+	CHECK_ERR_MSG(err, "fail to get light level\n");
+
+	err = s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &val_lsb);
+	err = s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &val_msb);
+	CHECK_ERR_MSG(err, "fail to read light level\n");
+
+	*light_level = val_lsb | (val_msb<<16);
+
+	/* cam_trace("X, light level = 0x%X", *light_level); */
+
+	return 0;
+}
+
+static int s5k5ccgx_set_capture_size(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (likely(!state->wide_cmd))
+		return 0;
+
+	cam_err("%s: WARNING, reconfiguring sensor register.\n\n", __func__);
+
+	switch (state->wide_cmd) {
+	case WIDE_REQ_CHANGE:
+		cam_info("%s: Wide Capture setting\n", __func__);
+		err = s5k5ccgx_set_from_table(sd, "change_wide_cap",
+			&state->regs->change_wide_cap, 1, 0);
+		break;
+
+	case WIDE_REQ_RESTORE:
+		cam_info("%s: Restore capture setting\n", __func__);
+		err = s5k5ccgx_set_from_table(sd, "restore_capture",
+				&state->regs->restore_cap, 1, 0);
+		break;
+
+	default:
+		cam_err("%s: WARNING, invalid argument(%d)\n",
+				__func__, state->wide_cmd);
+		break;
+	}
+
+	/* Don't forget the below codes.
+	 * We set here state->preview to NULL after reconfiguring
+	 * capure config if capture ratio does't match with preview ratio.
+	 */
+	state->preview = NULL;
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+/* PX: Set sensor mode */
+static int s5k5ccgx_set_sensor_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	state->hd_videomode = 0;
+
+	switch (val) {
+	case SENSOR_MOVIE:
+		/* We does not support movie mode when in VT. */
+		if (state->vt_mode) {
+			state->sensor_mode = SENSOR_CAMERA;
+			cam_err("%s: ERROR, Not support movie\n", __func__);
+			break;
+		}
+		/* We do not break. */
+
+	case SENSOR_CAMERA:
+		state->sensor_mode = val;
+		break;
+
+	case 2:	/* 720p HD video mode */
+		state->sensor_mode = SENSOR_MOVIE;
+		state->hd_videomode = 1;
+		break;
+
+	default:
+		cam_err("%s: ERROR, Not support.(%d)\n", __func__, val);
+		state->sensor_mode = SENSOR_CAMERA;
+		WARN_ON(1);
+		break;
+	}
+
+	return 0;
+}
+
+/* PX: Set framerate */
+static int s5k5ccgx_set_frame_rate(struct v4l2_subdev *sd, s32 fps)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EIO;
+	int i = 0, fps_index = -1;
+
+	cam_info("set frame rate %d\n", fps);
+
+	for (i = 0; i < ARRAY_SIZE(s5k5ccgx_framerates); i++) {
+		if (fps == s5k5ccgx_framerates[i].fps) {
+			fps_index = s5k5ccgx_framerates[i].index;
+			state->fps = fps;
+			state->req_fps = -1;
+			break;
+		}
+	}
+
+	if (unlikely(fps_index < 0)) {
+		cam_err("%s: WARNING, Not supported FPS(%d)\n", __func__, fps);
+		return 0;
+	}
+
+	if (!state->hd_videomode) {
+		err = s5k5ccgx_set_from_table(sd, "fps", state->regs->fps,
+				ARRAY_SIZE(state->regs->fps), fps_index);
+		CHECK_ERR_MSG(err, "fail to set framerate\n")
+	}
+
+	return 0;
+}
+
+static int s5k5ccgx_set_ae_lock(struct v4l2_subdev *sd, s32 val, bool force)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	switch (val) {
+	case AE_LOCK:
+		if (state->focus.touch)
+			return 0;
+
+		err = s5k5ccgx_set_from_table(sd, "ae_lock_on",
+				&state->regs->ae_lock_on, 1, 0);
+		WARN_ON(state->focus.ae_lock);
+		state->focus.ae_lock = 1;
+		break;
+
+	case AE_UNLOCK:
+		if (unlikely(!force && !state->focus.ae_lock))
+			return 0;
+
+		err = s5k5ccgx_set_from_table(sd, "ae_lock_off",
+				&state->regs->ae_lock_off, 1, 0);
+		state->focus.ae_lock = 0;
+		break;
+
+	default:
+		cam_err("%s: WARNING, invalid argument(%d)\n", __func__, val);
+	}
+
+	CHECK_ERR_MSG(err, "fail to lock AE(%d), err=%d\n", val, err);
+
+	return 0;
+}
+
+static int s5k5ccgx_set_awb_lock(struct v4l2_subdev *sd, s32 val, bool force)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	switch (val) {
+	case AWB_LOCK:
+		if (state->flash_on ||
+		    (state->wb_mode != WHITE_BALANCE_AUTO))
+			return 0;
+
+		err = s5k5ccgx_set_from_table(sd, "awb_lock_on",
+				&state->regs->awb_lock_on, 1, 0);
+		WARN_ON(state->focus.awb_lock);
+		state->focus.awb_lock = 1;
+		break;
+
+	case AWB_UNLOCK:
+		if (unlikely(!force && !state->focus.awb_lock))
+			return 0;
+
+		err = s5k5ccgx_set_from_table(sd, "awb_lock_off",
+			&state->regs->awb_lock_off, 1, 0);
+		state->focus.awb_lock = 0;
+		break;
+
+	default:
+		cam_err("%s: WARNING, invalid argument(%d)\n", __func__, val);
+	}
+
+	CHECK_ERR_MSG(err, "fail to lock AWB(%d), err=%d\n", val, err);
+
+	return 0;
+}
+
+/* PX: Set AE, AWB Lock */
+static int s5k5ccgx_set_lock(struct v4l2_subdev *sd, s32 lock, bool force)
+{
+	int err = -EIO;
+
+	cam_trace("%s\n", lock ? "on" : "off");
+	if (unlikely((u32)lock >= AEAWB_LOCK_MAX)) {
+		cam_err("%s: ERROR, invalid argument\n", __func__);
+		return -EINVAL;
+	}
+
+	err = s5k5ccgx_set_ae_lock(sd, (lock == AEAWB_LOCK) ?
+				AE_LOCK : AE_UNLOCK, force);
+	if (unlikely(err))
+		goto out_err;
+
+	err = s5k5ccgx_set_awb_lock(sd, (lock == AEAWB_LOCK) ?
+				AWB_LOCK : AWB_UNLOCK, force);
+	if (unlikely(err))
+		goto out_err;
+
+	cam_trace("X\n");
+	return 0;
+
+out_err:
+	cam_err("%s: ERROR, failed to set lock\n", __func__);
+	return err;
+}
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_P4W
+static int s5k5ccgx_set_af_softlanding(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	err = s5k5ccgx_set_from_table(sd, "af_off",
+			&state->regs->af_off, 1, 0);
+	CHECK_ERR_MSG(err, "fail to set softlanding\n");
+
+	cam_trace("X\n");
+	return 0;
+}
+#endif
+
+/* PX: */
+static int s5k5ccgx_return_focus(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	switch (state->focus.mode) {
+	case FOCUS_MODE_MACRO:
+		err = s5k5ccgx_set_from_table(sd, "af_macro_mode",
+				&state->regs->af_macro_mode, 1, 0);
+		break;
+
+	default:
+#if !defined(CONFIG_VIDEO_S5K5CCGX_P2)
+		if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+			err = s5k5ccgx_set_from_table(sd,
+				"af_night_normal_mode",
+				&state->regs->af_night_normal_mode, 1, 0);
+		else
+#endif
+			err = s5k5ccgx_set_from_table(sd,
+				"af_norma_mode",
+				&state->regs->af_normal_mode, 1, 0);
+		break;
+	}
+
+	CHECK_ERR(err);
+	return 0;
+}
+
+#ifdef DEBUG_FILTER_DATA
+static void __used s5k5ccgx_display_AF_win_info(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_rect first_win = {0, 0, 0, 0};
+	struct s5k5ccgx_rect second_win = {0, 0, 0, 0};
+
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x022C);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&first_win.x);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x022E);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&first_win.y);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0230);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&first_win.width);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0232);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&first_win.height);
+
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0234);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&second_win.x);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0236);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&second_win.y);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0238);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&second_win.width);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x023A);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, (u16 *)&second_win.height);
+
+	cam_info("------- AF Window info -------\n");
+	cam_info("Firtst Window: (%4d %4d %4d %4d)\n",
+		first_win.x, first_win.y, first_win.width, first_win.height);
+	cam_info("Second Window: (%4d %4d %4d %4d)\n",
+		second_win.x, second_win.y,
+		second_win.width, second_win.height);
+	cam_info("------- AF Window info -------\n\n");
+}
+#endif
+
+/* PX: Prepare AF Flash */
+static int s5k5ccgx_af_start_preflash(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_state *state = to_state(sd);
+	u16 read_value = 0;
+	int count = 0;
+	int err = 0;
+
+	cam_trace("E\n");
+
+	if (state->sensor_mode == SENSOR_MOVIE)
+		return 0;
+
+	cam_dbg("Start SINGLE AF, flash mode %d\n", state->flash_mode);
+
+	/* in case user calls auto_focus repeatedly without a cancel
+	 * or a capture, we need to cancel here to allow ae_awb
+	 * to work again, or else we could be locked forever while
+	 * that app is running, which is not the expected behavior.
+	 */
+	err = s5k5ccgx_set_lock(sd, AEAWB_UNLOCK, true);
+	CHECK_ERR_MSG(err, "fail to set lock\n");
+
+	state->focus.preflash = PREFLASH_OFF;
+	state->light_level = 0xFFFFFFFF;
+
+	s5k5ccgx_get_light_level(sd, &state->light_level);
+
+	switch (state->flash_mode) {
+	case FLASH_MODE_AUTO:
+		if (state->light_level >= FLASH_LOW_LIGHT_LEVEL) {
+			/* flash not needed */
+			break;
+		}
+
+	case FLASH_MODE_ON:
+		s5k5ccgx_set_from_table(sd, "af_pre_flash_start",
+			&state->regs->af_pre_flash_start, 1, 0);
+		s5k5ccgx_set_from_table(sd, "flash_ae_set",
+			&state->regs->flash_ae_set, 1, 0);
+		s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_ON);
+		state->focus.preflash = PREFLASH_ON;
+		break;
+
+	case FLASH_MODE_OFF:
+		if (state->light_level < FLASH_LOW_LIGHT_LEVEL)
+			state->one_frame_delay_ms = ONE_FRAME_DELAY_MS_LOW;
+		break;
+
+	default:
+		break;
+	}
+
+	/* We wait for 200ms after pre flash on.
+	 * check whether AE is stable.*/
+	msleep(200);
+
+	/* Check AE-stable */
+	if (state->focus.preflash == PREFLASH_ON) {
+		/* Do checking AE-stable */
+		for (count = 0; count < AE_STABLE_SEARCH_COUNT; count++) {
+			if (state->focus.start == AUTO_FOCUS_OFF) {
+				cam_info("af_start_preflash: \
+					AF is cancelled!\n");
+				state->focus.status = AF_RESULT_CANCELLED;
+				break;
+			}
+
+			s5k5ccgx_set_from_table(sd, "get_ae_stable",
+					&state->regs->get_ae_stable, 1, 0);
+			s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+
+			/* af_dbg("Check AE-Stable: 0x%04X\n", read_value); */
+			if (read_value == 0x0001) {
+				af_dbg("AE-stable success,"
+					" count=%d, delay=%dms\n", count,
+					state->one_frame_delay_ms);
+				break;
+			}
+
+			msleep(state->one_frame_delay_ms);
+		}
+
+		/* restore write mode */
+		s5k5ccgx_i2c_write_twobyte(client, 0x0028, 0x7000);
+
+		if (unlikely(count >= AE_STABLE_SEARCH_COUNT)) {
+			cam_err("%s: ERROR, AE unstable."
+				" count=%d, delay=%dms\n",
+				__func__, count, state->one_frame_delay_ms);
+			/* return -ENODEV; */
+		}
+	} else if (state->focus.start == AUTO_FOCUS_OFF) {
+		cam_info("af_start_preflash: AF is cancelled!\n");
+		state->focus.status = AF_RESULT_CANCELLED;
+	}
+
+	/* If AF cancel, finish pre-flash process. */
+	if (state->focus.status == AF_RESULT_CANCELLED) {
+		if (state->focus.preflash == PREFLASH_ON) {
+			s5k5ccgx_set_from_table(sd, "af_pre_flash_end",
+				&state->regs->af_pre_flash_end, 1, 0);
+			s5k5ccgx_set_from_table(sd, "flash_ae_clear",
+				&state->regs->flash_ae_clear, 1, 0);
+			s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_OFF);
+			state->focus.preflash = PREFLASH_NONE;
+		}
+
+		if (state->focus.touch)
+			state->focus.touch = 0;
+	}
+
+	cam_trace("X\n");
+
+	return 0;
+}
+
+/* PX: Do AF */
+static int s5k5ccgx_do_af(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_state *state = to_state(sd);
+	u16 read_value = 0;
+	u32 count = 0;
+
+	cam_trace("E\n");
+
+	/* AE, AWB Lock */
+	s5k5ccgx_set_lock(sd, AEAWB_LOCK, false);
+
+	if (state->sensor_mode == SENSOR_MOVIE) {
+		s5k5ccgx_set_from_table(sd, "hd_af_start",
+			&state->regs->hd_af_start, 1, 0);
+
+		cam_info("%s : 720P Auto Focus Operation\n\n", __func__);
+	} else
+		s5k5ccgx_set_from_table(sd, "single_af_start",
+			&state->regs->single_af_start, 1, 0);
+
+	/* Sleep while 2frame */
+	if (state->hd_videomode)
+		msleep(100); /* 100ms */
+	else if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+		msleep(ONE_FRAME_DELAY_MS_NIGHTMODE * 2); /* 330ms */
+	else
+		msleep(ONE_FRAME_DELAY_MS_LOW * 2); /* 200ms */
+
+	/* AF Searching */
+	cam_dbg("AF 1st search\n");
+
+	/*1st search*/
+	for (count = 0; count < FIRST_AF_SEARCH_COUNT; count++) {
+		if (state->focus.start == AUTO_FOCUS_OFF) {
+			cam_dbg("do_af: AF is cancelled while doing(1st)\n");
+			state->focus.status = AF_RESULT_CANCELLED;
+			goto check_done;
+		}
+
+		read_value = 0x0;
+		s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+		s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x2D12);
+		s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+		af_dbg("1st AF status(%02d) = 0x%04X\n",
+					count, read_value);
+		if (read_value != 0x01)
+			break;
+
+		msleep(state->one_frame_delay_ms);
+	}
+
+	if (read_value != 0x02) {
+		cam_err("%s: ERROR, 1st AF failed. count=%d, read_val=0x%X\n\n",
+					__func__, count, read_value);
+		state->focus.status = AF_RESULT_FAILED;
+		goto check_done;
+	}
+
+	/*2nd search*/
+	cam_dbg("AF 2nd search\n");
+	for (count = 0; count < SECOND_AF_SEARCH_COUNT; count++) {
+		msleep(state->one_frame_delay_ms);
+
+		if (state->focus.start == AUTO_FOCUS_OFF) {
+			cam_dbg("do_af: AF is cancelled while doing(2nd)\n");
+			state->focus.status = AF_RESULT_CANCELLED;
+			goto check_done;
+		}
+
+		read_value = 0x0FFFF;
+		s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+		s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x1F2F);
+		s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+		af_dbg("2nd AF status(%02d) = 0x%04X\n",
+						count, read_value);
+		if ((read_value & 0x0ff00) == 0x0)
+			break;
+	}
+
+	if (count >= SECOND_AF_SEARCH_COUNT) {
+		/* 0x01XX means "Not Finish". */
+		cam_err("%s: ERROR, 2nd AF failed. read_val=0x%X\n\n",
+			__func__, read_value & 0x0ff00);
+		state->focus.status = AF_RESULT_FAILED;
+		goto check_done;
+	}
+
+	cam_info("AF Success!\n");
+	state->focus.status = AF_RESULT_SUCCESS;
+
+check_done:
+	/* restore write mode */
+
+	/* We only unlocked AE,AWB in case of being cancelled.
+	 * But we now unlock it unconditionally if AF is started,
+	 */
+	if (state->focus.status == AF_RESULT_CANCELLED) {
+		cam_dbg("%s: Single AF cancelled.\n", __func__);
+		s5k5ccgx_set_lock(sd, AEAWB_UNLOCK, false);
+	} else {
+		state->focus.start = AUTO_FOCUS_OFF;
+		cam_dbg("%s: Single AF finished\n", __func__);
+	}
+
+	if ((state->focus.preflash == PREFLASH_ON) &&
+	    (state->sensor_mode == SENSOR_CAMERA)) {
+		s5k5ccgx_set_from_table(sd, "af_pre_flash_end",
+				&state->regs->af_pre_flash_end, 1, 0);
+		s5k5ccgx_set_from_table(sd, "flash_ae_clear",
+			&state->regs->flash_ae_clear, 1, 0);
+		s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_OFF);
+		if (state->focus.status == AF_RESULT_CANCELLED) {
+			state->focus.preflash = PREFLASH_NONE;
+		}
+	}
+
+	/* Notice: we here turn touch flag off set previously
+	 * when doing Touch AF. */
+	if (state->focus.touch)
+		state->focus.touch = 0;
+
+	return 0;
+}
+
+/* PX: Set AF */
+static int s5k5ccgx_set_af(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("%s: %s, focus mode %d\n", __func__,
+			val ? "start" : "stop", state->focus.mode);
+
+	if (unlikely((u32)val >= AUTO_FOCUS_MAX)) {
+		cam_err("%s: ERROR, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	if (state->focus.start == val)
+		return 0;
+
+	state->focus.start = val;
+
+	if (val == AUTO_FOCUS_ON) {
+		err = queue_work(state->workqueue, &state->af_work);
+		if (likely(err))
+			state->focus.status = AF_RESULT_DOING;
+		else
+			cam_warn("WARNING, AF is still processing. So new AF cannot start\n");
+	} else {
+		/* Cancel AF */
+		cam_info("set_af: AF cancel requested!\n");
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Stop AF */
+static int s5k5ccgx_stop_af(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_trace("E\n");
+	mutex_lock(&state->af_lock);
+
+	switch (state->focus.status) {
+	case AF_RESULT_FAILED:
+	case AF_RESULT_SUCCESS:
+		cam_dbg("Stop AF, focus mode %d, AF result %d\n",
+			state->focus.mode, state->focus.status);
+
+		err = s5k5ccgx_set_lock(sd, AEAWB_UNLOCK, false);
+		if (unlikely(err)) {
+			cam_err("%s: ERROR, fail to set lock\n", __func__);
+			goto err_out;
+		}
+		state->focus.status = AF_RESULT_CANCELLED;
+		state->focus.preflash = PREFLASH_NONE;
+		break;
+
+	case AF_RESULT_CANCELLED:
+		break;
+
+	default:
+		cam_warn("%s: WARNING, unnecessary calling. AF status=%d\n",
+			__func__, state->focus.status);
+		/* Return 0. */
+		goto err_out;
+		break;
+	}
+
+	if (!state->focus.touch) {
+		/* We move lens to default position if af is cancelled.*/
+		err = s5k5ccgx_return_focus(sd);
+		if (unlikely(err)) {
+			cam_err("%s: ERROR, fail to af_norma_mode (%d)\n",
+				__func__, err);
+			goto err_out;
+		}
+	} else
+		state->focus.touch = 0;
+
+	mutex_unlock(&state->af_lock);
+	cam_trace("X\n");
+	return 0;
+
+err_out:
+	mutex_unlock(&state->af_lock);
+	return err;
+}
+
+static void s5k5ccgx_af_worker(struct work_struct *work)
+{
+	struct s5k5ccgx_state *state = container_of(work, \
+				struct s5k5ccgx_state, af_work);
+	struct v4l2_subdev *sd = &state->sd;
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	mutex_lock(&state->af_lock);
+
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		state->one_frame_delay_ms = ONE_FRAME_DELAY_MS_NORMAL;
+		err = s5k5ccgx_af_start_preflash(sd);
+		if (unlikely(err))
+			goto out;
+
+		if (state->focus.status == AF_RESULT_CANCELLED)
+			goto out;
+	} else {
+		state->one_frame_delay_ms = 50;
+	}
+
+	s5k5ccgx_do_af(sd);
+
+out:
+	mutex_unlock(&state->af_lock);
+	cam_trace("X\n");
+	return;
+}
+
+/* PX: Set focus mode */
+static int s5k5ccgx_set_focus_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	u32 af_cancel = 0;
+	int err = -EINVAL;
+
+	/* cam_trace("E\n");*/
+	cam_dbg("%s val =%d(0x%X)\n", __func__, val, val);
+
+	if (state->focus.mode == val)
+		return 0;
+
+	af_cancel = (u32)val & FOCUS_MODE_DEFAULT;
+	mutex_lock(&state->af_lock);
+
+	switch (val) {
+	case FOCUS_MODE_MACRO:
+		err = s5k5ccgx_set_from_table(sd, "af_macro_mode",
+				&state->regs->af_macro_mode, 1, 0);
+		if (unlikely(err)) {
+			cam_err("%s: ERROR, fail to af_macro_mode (%d)\n",
+							__func__, err);
+			goto err_out;
+		}
+
+		state->focus.mode = FOCUS_MODE_MACRO;
+		break;
+
+	case FOCUS_MODE_INFINITY:
+	case FOCUS_MODE_AUTO:
+	case FOCUS_MODE_FIXED:
+		err = s5k5ccgx_set_from_table(sd, "af_norma_mode",
+				&state->regs->af_normal_mode, 1, 0);
+		if (unlikely(err)) {
+			cam_err("%s: ERROR, fail to af_norma_mode (%d)\n",
+							__func__, err);
+			goto err_out;
+		}
+
+		state->focus.mode = val;
+		break;
+
+	case FOCUS_MODE_FACEDETECT:
+	case FOCUS_MODE_CONTINOUS:
+	case FOCUS_MODE_TOUCH:
+		break;
+
+	default:
+		if (!af_cancel) {
+			cam_err("%s: ERROR, invalid val(0x%X)\n:",
+						__func__, val);
+			goto err_out;
+		}
+		break;
+	}
+	mutex_unlock(&state->af_lock);
+
+	if (af_cancel)
+		s5k5ccgx_stop_af(sd);
+
+	return 0;
+
+err_out:
+	mutex_unlock(&state->af_lock);
+	return err;
+}
+
+/* PX: */
+static int s5k5ccgx_set_af_window(struct v4l2_subdev *sd)
+{
+	int err = -EIO;
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_state *state = to_state(sd);
+	struct s5k5ccgx_rect inner_window = {0, 0, 0, 0};
+	struct s5k5ccgx_rect outter_window = {0, 0, 0, 0};
+	struct s5k5ccgx_rect first_window = {0, 0, 0, 0};
+	struct s5k5ccgx_rect second_window = {0, 0, 0, 0};
+	const s32 mapped_x = state->focus.pos_x;
+	const s32 mapped_y = state->focus.pos_y;
+	const u32 preview_width = state->preview->width;
+	const u32 preview_height = state->preview->height;
+	u32 inner_half_width = 0, inner_half_height = 0;
+	u32 outter_half_width = 0, outter_half_height = 0;
+
+	cam_trace("E\n");
+
+	mutex_lock(&state->af_lock);
+
+	inner_window.width = SCND_WINSIZE_X * preview_width / 1024;
+	inner_window.height = SCND_WINSIZE_Y * preview_height / 1024;
+	outter_window.width = FIRST_WINSIZE_X * preview_width / 1024;
+	outter_window.height = FIRST_WINSIZE_Y * preview_height / 1024;
+
+	inner_half_width = inner_window.width / 2;
+	inner_half_height = inner_window.height / 2;
+	outter_half_width = outter_window.width / 2;
+	outter_half_height = outter_window.height / 2;
+
+	af_dbg("Preview width=%d, height=%d\n", preview_width, preview_height);
+	af_dbg("inner_window_width=%d, inner_window_height=%d, " \
+		"outter_window_width=%d, outter_window_height=%d\n ",
+		inner_window.width, inner_window.height,
+		outter_window.width, outter_window.height);
+
+	/* Get X */
+	if (mapped_x <= inner_half_width) {
+		inner_window.x = outter_window.x = 0;
+		af_dbg("inner & outter window over sensor left."
+			"in_x=%d, out_x=%d\n", inner_window.x, outter_window.x);
+	} else if (mapped_x <= outter_half_width) {
+		inner_window.x = mapped_x - inner_half_width;
+		outter_window.x = 0;
+		af_dbg("outter window over sensor left. in_x=%d, out_x=%d\n",
+					inner_window.x, outter_window.x);
+	} else if (mapped_x >= ((preview_width - 1) - inner_half_width)) {
+		inner_window.x = (preview_width - 1) - inner_window.width;
+		outter_window.x = (preview_width - 1) - outter_window.width;
+		af_dbg("inner & outter window over sensor right." \
+			"in_x=%d, out_x=%d\n", inner_window.x, outter_window.x);
+	} else if (mapped_x >= ((preview_width - 1) - outter_half_width)) {
+		inner_window.x = mapped_x - inner_half_width;
+		outter_window.x = (preview_width - 1) - outter_window.width;
+		af_dbg("outter window over sensor right. in_x=%d, out_x=%d\n",
+					inner_window.x, outter_window.x);
+	} else {
+		inner_window.x = mapped_x - inner_half_width;
+		outter_window.x = mapped_x - outter_half_width;
+		af_dbg("inner & outter window within sensor area." \
+			"in_x=%d, out_x=%d\n", inner_window.x, outter_window.x);
+	}
+
+	/* Get Y */
+	if (mapped_y <= inner_half_height) {
+		inner_window.y = outter_window.y = 0;
+		af_dbg("inner & outter window over sensor top." \
+			"in_y=%d, out_y=%d\n", inner_window.y, outter_window.y);
+	} else if (mapped_y <= outter_half_height) {
+		inner_window.y = mapped_y - inner_half_height;
+		outter_window.y = 0;
+		af_dbg("outter window over sensor top. in_y=%d, out_y=%d\n",
+					inner_window.y, outter_window.y);
+	} else if (mapped_y >= ((preview_height - 1) - inner_half_height)) {
+		inner_window.y = (preview_height - 1) - inner_window.height;
+		outter_window.y = (preview_height - 1) - outter_window.height;
+		af_dbg("inner & outter window over sensor bottom." \
+			"in_y=%d, out_y=%d\n", inner_window.y, outter_window.y);
+	} else if (mapped_y >= ((preview_height - 1) - outter_half_height)) {
+		inner_window.y = mapped_y - inner_half_height;
+		outter_window.y = (preview_height - 1) - outter_window.height;
+		af_dbg("outter window over sensor bottom. in_y=%d, out_y=%d\n",
+					inner_window.y, outter_window.y);
+	} else {
+		inner_window.y = mapped_y - inner_half_height;
+		outter_window.y = mapped_y - outter_half_height;
+		af_dbg("inner & outter window within sensor area." \
+			"in_y=%d, out_y=%d\n", inner_window.y, outter_window.y);
+	}
+
+	af_dbg("==> inner_window top=(%d,%d), bottom=(%d, %d)\n",
+		inner_window.x, inner_window.y,
+		inner_window.x + inner_window.width,
+		inner_window.y + inner_window.height);
+	af_dbg("==> outter_window top=(%d,%d), bottom=(%d, %d)\n",
+		outter_window.x, outter_window.y,
+		outter_window.x + outter_window.width ,
+		outter_window.y + outter_window.height);
+
+	second_window.x = inner_window.x * 1024 / preview_width;
+	second_window.y = inner_window.y * 1024 / preview_height;
+	first_window.x = outter_window.x * 1024 / preview_width;
+	first_window.y = outter_window.y * 1024 / preview_height;
+
+	af_dbg("=> second_window top=(%d, %d)\n",
+		second_window.x, second_window.y);
+	af_dbg("=> first_window top=(%d, %d)\n",
+		first_window.x, first_window.y);
+
+	/* restore write mode */
+	err = s5k5ccgx_i2c_write_twobyte(client, 0x0028, 0x7000);
+
+	/* Set first window x, y */
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x002A, 0x022C);
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x0F12,
+					(u16)(first_window.x));
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x002A, 0x022E);
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x0F12,
+					(u16)(first_window.y));
+
+	/* Set second widnow x, y */
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x002A, 0x0234);
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x0F12,
+					(u16)(second_window.x));
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x002A, 0x0236);
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x0F12,
+					(u16)(second_window.y));
+
+	/* Update AF window */
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x002A, 0x023C);
+	err |= s5k5ccgx_i2c_write_twobyte(client, 0x0F12, 0x0001);
+
+	debug_msleep(sd, 60);
+	mutex_unlock(&state->af_lock);
+
+	CHECK_ERR(err);
+	cam_dbg("%s: AF window position completed.\n", __func__);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static int s5k5ccgx_set_touch_af(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EIO;
+
+	cam_trace("%s, x=%d y=%d\n", val ? "start" : "stop",
+			state->focus.pos_x, state->focus.pos_y);
+
+	state->focus.touch = val;
+
+	if (val) {
+		if (mutex_is_locked(&state->af_lock)) {
+			cam_warn("%s: WARNING, AF is busy\n", __func__);
+			return 0;
+		}
+
+		err = queue_work(state->workqueue, &state->af_win_work);
+		if (likely(!err))
+			cam_warn("WARNING, AF window is still processing\n");
+	} else {
+		err = s5k5ccgx_stop_af(sd);
+		CHECK_ERR_MSG(err, "val=%d\n", 0)
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static void s5k5ccgx_af_win_worker(struct work_struct *work)
+{
+	struct s5k5ccgx_state *state = container_of(work, \
+				struct s5k5ccgx_state, af_win_work);
+	struct v4l2_subdev *sd = &state->sd;
+
+	cam_trace("E\n");
+	s5k5ccgx_set_af_window(sd);
+	cam_trace("X\n");
+}
+
+static int s5k5ccgx_init_param(struct v4l2_subdev *sd)
+{
+	struct v4l2_control ctrl;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k5ccgx_ctrls); i++) {
+		if (s5k5ccgx_ctrls[i].value !=
+				s5k5ccgx_ctrls[i].default_value) {
+			ctrl.id = s5k5ccgx_ctrls[i].id;
+			ctrl.value = s5k5ccgx_ctrls[i].value;
+			s5k5ccgx_s_ctrl(sd, &ctrl);
+		}
+	}
+
+	return 0;
+}
+
+static int s5k5ccgx_init_regs(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct s5k5ccgx_state *state = to_state(sd);
+	u16 read_value = 0;
+	int err = -ENODEV;
+
+	/* we'd prefer to do this in probe, but the framework hasn't
+	 * turned on the camera yet so our i2c operations would fail
+	 * if we tried to do it in probe, so we have to do it here
+	 * and keep track if we succeeded or not.
+	 */
+
+	/* enter read mode */
+	err = s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	if (unlikely(err < 0))
+		return -ENODEV;
+
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0150);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+	if (likely(read_value == S5K5CCGX_CHIP_ID))
+		cam_info("Sensor ChipID: 0x%04X\n", S5K5CCGX_CHIP_ID);
+	else
+		cam_info("Sensor ChipID: 0x%04X, unknown ChipID\n", read_value);
+
+	s5k5ccgx_i2c_write_twobyte(client, 0x002C, 0x7000);
+	s5k5ccgx_i2c_write_twobyte(client, 0x002E, 0x0152);
+	s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+	if (likely(read_value == S5K5CCGX_CHIP_REV))
+		cam_info("Sensor revision: 0x%04X\n", S5K5CCGX_CHIP_REV);
+	else
+		cam_info("Sensor revision: 0x%04X, unknown revision\n",
+				read_value);
+
+	/* restore write mode */
+	err = s5k5ccgx_i2c_write_twobyte(client, 0x0028, 0x7000);
+	CHECK_ERR_COND(err < 0, -ENODEV);
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+
+static const struct s5k5ccgx_framesize *s5k5ccgx_get_framesize
+	(const struct s5k5ccgx_framesize *frmsizes,
+	u32 frmsize_count, u32 index)
+{
+	int i = 0;
+
+	for (i = 0; i < frmsize_count; i++) {
+		if (frmsizes[i].index == index)
+			return &frmsizes[i];
+	}
+
+	return NULL;
+}
+
+/* This function is called from the g_ctrl api
+ *
+ * This function should be called only after the s_fmt call,
+ * which sets the required width/height value.
+ *
+ * It checks a list of available frame sizes and sets the
+ * most appropriate frame size.
+ *
+ * The list is stored in an increasing order (as far as possible).
+ * Hence the first entry (searching from the beginning) where both the
+ * width and height is more than the required value is returned.
+ * In case of no perfect match, we set the last entry (which is supposed
+ * to be the largest resolution supported.)
+ */
+static void s5k5ccgx_set_framesize(struct v4l2_subdev *sd,
+				const struct s5k5ccgx_framesize *frmsizes,
+				u32 num_frmsize, bool preview)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	const struct s5k5ccgx_framesize **found_frmsize = NULL;
+	u32 width = state->req_fmt.width;
+	u32 height = state->req_fmt.height;
+	int i = 0;
+
+	cam_dbg("%s: Requested Res %dx%d\n", __func__,
+			width, height);
+
+	found_frmsize = (const struct s5k5ccgx_framesize **)
+			(preview ? &state->preview : &state->capture);
+
+	for (i = 0; i < num_frmsize; i++) {
+		if ((frmsizes[i].width == width) &&
+			(frmsizes[i].height == height)) {
+			*found_frmsize = &frmsizes[i];
+			break;
+		}
+	}
+
+	if (*found_frmsize == NULL) {
+		cam_err("%s: ERROR, invalid frame size %dx%d\n", __func__,
+						width, height);
+		*found_frmsize = preview ?
+			s5k5ccgx_get_framesize(frmsizes, num_frmsize,
+					S5K5CCGX_PREVIEW_XGA) :
+			s5k5ccgx_get_framesize(frmsizes, num_frmsize,
+					S5K5CCGX_CAPTURE_3MP);
+		BUG_ON(!(*found_frmsize));
+	}
+
+	if (preview)
+		cam_info("Preview Res Set: %dx%d, index %d\n",
+			(*found_frmsize)->width, (*found_frmsize)->height,
+			(*found_frmsize)->index);
+	else
+		cam_info("Capture Res Set: %dx%d, index %d\n",
+			(*found_frmsize)->width, (*found_frmsize)->height,
+			(*found_frmsize)->index);
+}
+
+static int s5k5ccgx_wait_steamoff(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	struct s5k5ccgx_stream_time *stream_time = &state->stream_time;
+	s32 elapsed_msec = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(!(state->pdata->is_mipi & state->need_wait_streamoff)))
+		return 0;
+
+	do_gettimeofday(&stream_time->curr_time);
+
+	elapsed_msec = GET_ELAPSED_TIME(stream_time->curr_time, \
+				stream_time->before_time) / 1000;
+
+	if (state->pdata->streamoff_delay > elapsed_msec) {
+		cam_info("stream-off: %dms + %dms\n", elapsed_msec,
+			state->pdata->streamoff_delay - elapsed_msec);
+		debug_msleep(sd, state->pdata->streamoff_delay - elapsed_msec);
+	} else
+		cam_info("stream-off: %dms\n", elapsed_msec);
+
+	state->need_wait_streamoff = 0;
+
+	return 0;
+}
+
+static int s5k5ccgx_control_stream(struct v4l2_subdev *sd, u32 cmd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (unlikely(cmd != STREAM_STOP))
+		return 0;
+
+	cam_info("STREAM STOP!!\n");
+	err = s5k5ccgx_set_from_table(sd, "stream_stop",
+			&state->regs->stream_stop, 1, 0);
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	do_gettimeofday(&state->stream_time.before_time);
+	state->need_wait_streamoff = 1;
+#else
+	debug_msleep(sd, state->pdata->streamoff_delay);
+#endif
+
+	if (state->runmode == S5K5CCGX_RUNMODE_CAPTURING) {
+		state->runmode = S5K5CCGX_RUNMODE_CAPTURE_STOP;
+		cam_dbg("Capture Stop!\n");
+	}
+
+	CHECK_ERR_MSG(err, "failed to stop stream\n");
+	return 0;
+}
+
+/* PX: Set flash mode */
+static int s5k5ccgx_set_flash_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	/* movie flash mode should be set when recording is started */
+/*	if (state->sensor_mode == SENSOR_MOVIE && !state->recording)
+		return 0;*/
+
+	if (state->flash_mode == val) {
+		cam_dbg("the same flash mode=%d\n", val);
+		return 0;
+	}
+
+	if (val == FLASH_MODE_TORCH)
+		s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_ON);
+
+	if ((state->flash_mode == FLASH_MODE_TORCH)
+	    && (val == FLASH_MODE_OFF))
+		s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_OFF);
+
+	state->flash_mode = val;
+	cam_dbg("Flash mode = %d\n", val);
+	return 0;
+}
+
+static int s5k5ccgx_check_esd(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+	u16 read_value = 0;
+
+	err = s5k5ccgx_set_from_table(sd, "get_esd_status",
+		&state->regs->get_esd_status, 1, 0);
+	CHECK_ERR(err);
+	err = s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value);
+	CHECK_ERR(err);
+
+	if (read_value != 0xAAAA)
+		goto esd_out;
+
+	cam_info("Check ESD: not detected\n\n");
+	return 0;
+
+esd_out:
+	cam_err("Check ESD: ERROR, ESD Shock detected! (val=0x%X)\n\n",
+		read_value);
+	return -ERESTART;
+}
+
+/* returns the real iso currently used by sensor due to lighting
+ * conditions, not the requested iso we sent using s_ctrl.
+ */
+/* PX: */
+static inline int s5k5ccgx_get_exif_iso(struct v4l2_subdev *sd, u16 *iso)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 iso_gain_table[] = {10, 15, 25, 35};
+	u16 iso_table[] = {0, 50, 100, 200, 400};
+	int err = -EIO;
+	u16 val = 0, gain = 0;
+	int i = 0;
+
+	err = s5k5ccgx_set_from_table(sd, "get_iso",
+				&state->regs->get_iso, 1, 0);
+	err |= s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &val);
+	CHECK_ERR(err);
+
+	gain = val * 10 / 256;
+	for (i = 0; i < ARRAY_SIZE(iso_gain_table); i++) {
+		if (gain < iso_gain_table[i])
+			break;
+	}
+
+	*iso = iso_table[i];
+
+	cam_dbg("gain=%d, ISO=%d\n", gain, *iso);
+
+	/* We do not restore write mode */
+
+	return 0;
+}
+
+/* PX: Set ISO */
+static int __used s5k5ccgx_set_iso(struct v4l2_subdev *sd, s32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+retry:
+	switch (val) {
+	case ISO_AUTO:
+	case ISO_50:
+	case ISO_100:
+	case ISO_200:
+	case ISO_400:
+		err = s5k5ccgx_set_from_table(sd, "iso",
+			state->regs->iso, ARRAY_SIZE(state->regs->iso),
+			val);
+		break;
+
+	default:
+		cam_err("%s: ERROR, invalid arguement(%d)\n", __func__, val);
+		val = ISO_AUTO;
+		goto retry;
+		break;
+	}
+
+	cam_trace("X\n");
+	return 0;
+}
+
+/* PX: Return exposure time (ms) */
+static inline int s5k5ccgx_get_exif_exptime(struct v4l2_subdev *sd,
+						u32 *exp_time)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err;
+	u16 read_value_lsb = 0;
+	u16 read_value_msb = 0;
+
+	err = s5k5ccgx_set_from_table(sd, "get_shutterspeed",
+				&state->regs->get_shutterspeed, 1, 0);
+	CHECK_ERR(err);
+
+	err = s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value_lsb);
+	err |= s5k5ccgx_i2c_read_twobyte(client, 0x0F12, &read_value_msb);
+	CHECK_ERR(err);
+
+	*exp_time = (((read_value_msb << 16) | (read_value_lsb & 0xFFFF))
+			* 1000) / 400;
+
+	/* We do not restore write mode */
+
+	return 0;
+
+}
+
+static inline void s5k5ccgx_get_exif_flash(struct v4l2_subdev *sd,
+					u16 *flash)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	switch (state->flash_mode) {
+	case FLASH_MODE_OFF:
+		*flash |= EXIF_FLASH_MODE_SUPPRESSION;
+		break;
+
+	case FLASH_MODE_AUTO:
+		*flash |= EXIF_FLASH_MODE_AUTO;
+		break;
+
+	case FLASH_MODE_ON:
+	case FLASH_MODE_TORCH:
+		*flash |= EXIF_FLASH_MODE_FIRING;
+		break;
+
+	default:
+		break;
+	}
+
+	if (state->flash_on) {
+		*flash |= EXIF_FLASH_FIRED;
+		if (state->sensor_mode == SENSOR_CAMERA)
+			state->flash_on = 0;
+	}
+
+}
+
+/* PX: */
+static int s5k5ccgx_get_exif(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	u32 exposure_time = 0;
+
+	/* exposure time */
+	state->exif.exp_time_den = 0;
+	s5k5ccgx_get_exif_exptime(sd, &exposure_time);
+	/*WARN(!exposure_time, "WARNING: exposure time is 0\n");*/
+	state->exif.exp_time_den = 1000 * 1000 / exposure_time;
+
+	/* iso */
+	state->exif.iso = 0;
+	s5k5ccgx_get_exif_iso(sd, &state->exif.iso);
+
+	/* flash */
+	state->exif.flash = 0;
+	s5k5ccgx_get_exif_flash(sd, &state->exif.flash);
+
+	cam_dbg("EXIF: ex_time_den=%d, iso=%d, flash=0x%02X\n",
+		state->exif.exp_time_den, state->exif.iso, state->exif.flash);
+
+	return 0;
+}
+
+static int s5k5ccgx_set_preview_size(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E, wide_cmd=%d\n", state->wide_cmd);
+
+	switch (state->wide_cmd) {
+	case WIDE_REQ_CHANGE:
+		cam_info("%s: Wide Capture setting\n", __func__);
+		err = s5k5ccgx_set_from_table(sd, "change_wide_cap",
+			&state->regs->change_wide_cap, 1, 0);
+		break;
+
+	case WIDE_REQ_RESTORE:
+		cam_info("%s:Restore capture setting\n", __func__);
+		err = s5k5ccgx_set_from_table(sd, "restore_capture",
+				&state->regs->restore_cap, 1, 0);
+		/* We do not break */
+
+	default:
+		cam_dbg("set_preview_size\n");
+		err = s5k5ccgx_set_from_table(sd, "preview_size",
+				state->regs->preview_size,
+				ARRAY_SIZE(state->regs->preview_size),
+				state->preview->index);
+		BUG_ON(state->preview->index == S5K5CCGX_PREVIEW_PVGA);
+		break;
+	}
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int s5k5ccgx_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+	/* bool set_size = true; */
+
+	cam_dbg("Camera Preview start, runmode = %d\n", state->runmode);
+
+	if ((state->runmode == S5K5CCGX_RUNMODE_NOTREADY) ||
+	    (state->runmode == S5K5CCGX_RUNMODE_CAPTURING)) {
+		cam_err("%s: ERROR - Invalid runmode\n", __func__);
+		return -EPERM;
+	}
+
+	state->focus.status = AF_RESULT_NONE;
+
+	if (state->need_update_frmsize) {
+		err = s5k5ccgx_set_preview_size(sd);
+		state->need_update_frmsize = 0;
+		CHECK_ERR_MSG(err, "failed to set preview size(%d)\n", err);
+	}
+
+	if (state->runmode == S5K5CCGX_RUNMODE_CAPTURE_STOP) {
+		/* We turn flash off if one shot flash is still on. */
+		if (s5k5ccgx_is_hwflash_on(sd))
+			s5k5ccgx_flash_oneshot(sd, S5K5CCGX_FLASH_OFF);
+
+		err = s5k5ccgx_set_lock(sd, AEAWB_UNLOCK, true);
+		CHECK_ERR_MSG(err, "fail to set lock\n");
+
+		cam_info("Sending Preview_Return cmd\n");
+		err = s5k5ccgx_set_from_table(sd, "preview_return",
+					&state->regs->preview_return, 1, 0);
+		CHECK_ERR_MSG(err, "fail to set Preview_Return (%d)\n", err)
+	} else {
+		err = s5k5ccgx_set_from_table(sd, "update_preview",
+			&state->regs->update_preview, 1, 0);
+		CHECK_ERR_MSG(err, "failed to update preview(%d)\n", err);
+	}
+
+	state->runmode = S5K5CCGX_RUNMODE_RUNNING;
+
+	return 0;
+}
+
+static int s5k5ccgx_set_video_preview(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("Video Preview start, runmode = %d\n", state->runmode);
+
+	if ((state->runmode == S5K5CCGX_RUNMODE_NOTREADY) ||
+	    (state->runmode == S5K5CCGX_RUNMODE_CAPTURING)) {
+		cam_err("%s: ERROR - Invalid runmode\n", __func__);
+		return -EPERM;
+	}
+
+	state->focus.status = AF_RESULT_NONE;
+
+	if (state->hd_videomode) {
+		s5k5ccgx_init_param(sd);
+		err = s5k5ccgx_set_from_table(sd, "update_hd_preview",
+			&state->regs->update_hd_preview, 1, 0);
+		CHECK_ERR_MSG(err, "failed to update HD preview\n");
+
+		s5k5ccgx_set_from_table(sd, "hd_first_af_start",
+				&state->regs->hd_first_af_start, 1, 0);
+	} else {
+		err = s5k5ccgx_set_from_table(sd, "preview_size",
+				state->regs->preview_size,
+				ARRAY_SIZE(state->regs->preview_size),
+				state->preview->index);
+		CHECK_ERR_MSG(err, "failed to set preview size\n");
+
+		err = s5k5ccgx_set_from_table(sd, "update_preview",
+			&state->regs->update_preview, 1, 0);
+		CHECK_ERR_MSG(err, "failed to update preview\n");
+	}
+
+	cam_dbg("runmode now RUNNING\n");
+	state->runmode = S5K5CCGX_RUNMODE_RUNNING;
+
+	return 0;
+}
+
+/* PX: Start capture */
+static int s5k5ccgx_set_capture_start(struct v4l2_subdev *sd)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -ENODEV;
+	u32 light_level = 0xFFFFFFFF;
+
+	/* Set capture size */
+	err = s5k5ccgx_set_capture_size(sd);
+	CHECK_ERR_MSG(err, "fail to set capture size (%d)\n", err);
+
+	/* Set flash */
+	switch (state->flash_mode) {
+	case FLASH_MODE_AUTO:
+		/* 3rd party App may do capturing without AF. So we check
+		 * whether AF is executed  before capture and  turn on flash
+		 * if needed. But we do not consider low-light capture of Market
+		 * App. */
+		if (state->focus.preflash == PREFLASH_NONE) {
+			s5k5ccgx_get_light_level(sd, &state->light_level);
+			if (light_level >= FLASH_LOW_LIGHT_LEVEL)
+				break;
+		} else if (state->focus.preflash == PREFLASH_OFF)
+			break;
+		/* We do not break. */
+
+	case FLASH_MODE_ON:
+		s5k5ccgx_flash_oneshot(sd, S5K5CCGX_FLASH_ON);
+		/* We here don't need to set state->flash_on to 1 */
+
+		err = s5k5ccgx_set_lock(sd, AEAWB_UNLOCK, true);
+		CHECK_ERR_MSG(err, "fail to set lock\n");
+
+		/* Full flash start */
+		err = s5k5ccgx_set_from_table(sd, "flash_start",
+			&state->regs->flash_start, 1, 0);
+		break;
+
+	case FLASH_MODE_OFF:
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+		if (state->light_level < CAPTURE_LOW_LIGHT_LEVEL)
+			err = s5k5ccgx_set_from_table(sd, "set_lowlight_cap",
+				&state->regs->set_lowlight_cap, 1, 0);
+		break;
+#endif
+	default:
+		break;
+	}
+
+	/* Send capture start command. */
+	cam_dbg("Send Capture_Start cmd\n");
+	err = s5k5ccgx_set_from_table(sd, "capture_start",
+			state->regs->capture_start,
+			ARRAY_SIZE(state->regs->capture_start),
+			state->capture->index);
+	if (state->scene_mode == SCENE_MODE_NIGHTSHOT)
+		debug_msleep(sd, 140);
+
+	state->runmode = S5K5CCGX_RUNMODE_CAPTURING;
+	state->focus.preflash = PREFLASH_NONE;
+
+	CHECK_ERR_MSG(err, "fail to capture_start (%d)\n", err);
+
+	s5k5ccgx_get_exif(sd);
+
+	return 0;
+}
+
+static int s5k5ccgx_s_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	s32 previous_index = 0;
+
+	cam_dbg("%s: pixelformat = 0x%x, colorspace = 0x%x, width = %d, height = %d\n",
+		__func__, fmt->code, fmt->colorspace, fmt->width, fmt->height);
+
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	state->format_mode = fmt->field;
+	state->wide_cmd = WIDE_REQ_NONE;
+
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		previous_index = state->preview ? state->preview->index : -1;
+
+		s5k5ccgx_set_framesize(sd, s5k5ccgx_preview_frmsizes,
+				ARRAY_SIZE(s5k5ccgx_preview_frmsizes),
+				true);
+
+		if (unlikely((state->sensor_mode == SENSOR_CAMERA) &&
+		    (state->preview->index == S5K5CCGX_PREVIEW_PVGA))) {
+			cam_err("%s: ERROR, invalid preview size\n", __func__);
+			return -EINVAL;
+		}
+
+		if (previous_index != state->preview->index) {
+			if ((state->preview->index == PREVIEW_WIDE_SIZE)
+			    && (previous_index != PREVIEW_WIDE_SIZE)) {
+				cam_dbg("preview, need to change to WIDE\n");
+				state->wide_cmd = WIDE_REQ_CHANGE;
+			} else if ((state->preview->index != PREVIEW_WIDE_SIZE)
+			    && (previous_index == PREVIEW_WIDE_SIZE)) {
+				cam_dbg("preview, need to restore form WIDE\n");
+				state->wide_cmd = WIDE_REQ_RESTORE;
+			}
+
+			state->need_update_frmsize = 1;
+		}
+	} else {
+		/*
+		 * In case of image capture mode,
+		 * if the given image resolution is not supported,
+		 * use the next higher image resolution. */
+		s5k5ccgx_set_framesize(sd, s5k5ccgx_capture_frmsizes,
+				ARRAY_SIZE(s5k5ccgx_capture_frmsizes),
+				false);
+
+		/* for maket app.
+		 * Samsung camera app does not use unmatched ratio.*/
+		if (unlikely(FRM_RATIO(state->preview)
+		    != FRM_RATIO(state->capture))) {
+			cam_warn("%s: WARNING, capture ratio " \
+				"is different with preview ratio\n\n",
+				__func__);
+			if (state->capture->index == CAPTURE_WIDE_SIZE) {
+				cam_dbg("captre: need to change to WIDE\n");
+				state->wide_cmd = WIDE_REQ_CHANGE;
+			} else {
+				cam_dbg("capture, need to restore form WIDE\n");
+				state->wide_cmd = WIDE_REQ_RESTORE;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int s5k5ccgx_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
+					enum v4l2_mbus_pixelcode *code)
+{
+	cam_dbg("%s: index = %d\n", __func__, index);
+
+	if (index >= ARRAY_SIZE(capture_fmts))
+		return -EINVAL;
+
+	*code = capture_fmts[index].code;
+
+	return 0;
+}
+
+static int s5k5ccgx_try_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+{
+	int num_entries;
+	int i;
+
+	num_entries = ARRAY_SIZE(capture_fmts);
+
+	cam_dbg("%s: code = 0x%x , colorspace = 0x%x, num_entries = %d\n",
+		__func__, fmt->code, fmt->colorspace, num_entries);
+
+	for (i = 0; i < num_entries; i++) {
+		if (capture_fmts[i].code == fmt->code &&
+		    capture_fmts[i].colorspace == fmt->colorspace) {
+			cam_dbg("%s: match found, returning 0\n", __func__);
+			return 0;
+		}
+	}
+
+	cam_err("%s: no match found, returning -EINVAL\n", __func__);
+	return -EINVAL;
+}
+
+
+static int s5k5ccgx_enum_framesizes(struct v4l2_subdev *sd,
+				  struct v4l2_frmsizeenum *fsize)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	/*
+	* The camera interface should read this value, this is the resolution
+	* at which the sensor would provide framedata to the camera i/f
+	* In case of image capture,
+	* this returns the default camera resolution (VGA)
+	*/
+	if (state->format_mode != V4L2_PIX_FMT_MODE_CAPTURE) {
+		if (unlikely(state->preview == NULL)) {
+			cam_err("%s: ERROR\n", __func__);
+			return -EFAULT;
+		}
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->preview->width;
+		fsize->discrete.height = state->preview->height;
+	} else {
+		if (unlikely(state->capture == NULL)) {
+			cam_err("%s: ERROR\n", __func__);
+			return -EFAULT;
+		}
+
+		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+		fsize->discrete.width = state->capture->width;
+		fsize->discrete.height = state->capture->height;
+	}
+
+	return 0;
+}
+
+static int s5k5ccgx_g_parm(struct v4l2_subdev *sd,
+			struct v4l2_streamparm *param)
+{
+	return 0;
+}
+
+static int s5k5ccgx_s_parm(struct v4l2_subdev *sd,
+			struct v4l2_streamparm *param)
+{
+	int err = 0;
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	state->req_fps = param->parm.capture.timeperframe.denominator /
+			param->parm.capture.timeperframe.numerator;
+
+	cam_dbg("s_parm state->fps=%d, state->req_fps=%d\n",
+		state->fps, state->req_fps);
+
+	if ((state->req_fps < 0) || (state->req_fps > 30)) {
+		cam_err("%s: ERROR, invalid frame rate %d. we'll set to 30\n",
+				__func__, state->req_fps);
+		state->req_fps = 30;
+	}
+
+	if (state->initialized && (state->scene_mode == SCENE_MODE_NONE)) {
+		err = s5k5ccgx_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+static int s5k5ccgx_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	if (!state->initialized) {
+		cam_err("%s: WARNING, camera not initialized\n", __func__);
+		return 0;
+	}
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.exp_time_den;
+		else
+			ctrl->value = 24;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.iso;
+		else
+			ctrl->value = 100;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_FLASH:
+		if (state->sensor_mode == SENSOR_CAMERA)
+			ctrl->value = state->exif.flash;
+		else
+			s5k5ccgx_get_exif_flash(sd, (u16 *)ctrl->value);
+		break;
+
+#if !defined(FEATURE_YUV_CAPTURE)
+	case V4L2_CID_CAM_JPEG_MAIN_SIZE:
+		ctrl->value = state->jpeg.main_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MAIN_OFFSET:
+		ctrl->value = state->jpeg.main_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_SIZE:
+		ctrl->value = state->jpeg.thumb_size;
+		break;
+
+	case V4L2_CID_CAM_JPEG_THUMB_OFFSET:
+		ctrl->value = state->jpeg.thumb_offset;
+		break;
+
+	case V4L2_CID_CAM_JPEG_QUALITY:
+		ctrl->value = state->jpeg.quality;
+		break;
+
+	case V4L2_CID_CAM_JPEG_MEMSIZE:
+		ctrl->value = SENSOR_JPEG_SNAPSHOT_MEMSIZE;
+		break;
+#endif
+
+	case V4L2_CID_CAMERA_AUTO_FOCUS_RESULT:
+		ctrl->value = state->focus.status;
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+	case V4L2_CID_CAMERA_EFFECT:
+	case V4L2_CID_CAMERA_CONTRAST:
+	case V4L2_CID_CAMERA_SATURATION:
+	case V4L2_CID_CAMERA_SHARPNESS:
+	case V4L2_CID_CAMERA_OBJ_TRACKING_STATUS:
+	case V4L2_CID_CAMERA_SMART_AUTO_STATUS:
+	default:
+		cam_err("%s: WARNING, unknown Ctrl-ID 0x%x\n",
+					__func__, ctrl->id);
+		err = 0; /* we return no error. */
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	return err;
+}
+
+static int s5k5ccgx_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -ENOIOCTLCMD;
+
+	if (unlikely(state->sensor_mode == SENSOR_MOVIE))
+		s5k5ccgx_save_ctrl(sd, ctrl);
+
+	if (!state->initialized && ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE) {
+		if (state->sensor_mode == SENSOR_MOVIE)
+			return 0;
+
+		cam_warn("%s: WARNING, camera not initialized. ID = %d(0x%X)\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE,
+			ctrl->id - V4L2_CID_PRIVATE_BASE);
+		return 0;
+	}
+
+	cam_dbg("%s: ID =%d, val = %d\n",
+		__func__, ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if (ctrl->id != V4L2_CID_CAMERA_SET_AUTO_FOCUS)
+		mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = s5k5ccgx_set_sensor_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_X:
+		state->focus.pos_x = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_OBJECT_POSITION_Y:
+		state->focus.pos_y = ctrl->value;
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_TOUCH_AF_START_STOP:
+		err = s5k5ccgx_set_touch_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FOCUS_MODE:
+		err = s5k5ccgx_set_focus_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SET_AUTO_FOCUS:
+		err = s5k5ccgx_set_af(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_FLASH_MODE:
+		err = s5k5ccgx_set_flash_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = s5k5ccgx_set_exposure(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_WHITE_BALANCE:
+		err = s5k5ccgx_set_from_table(sd, "white balance",
+			state->regs->white_balance,
+			ARRAY_SIZE(state->regs->white_balance), ctrl->value);
+		state->wb_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_EFFECT:
+		err = s5k5ccgx_set_from_table(sd, "effects",
+			state->regs->effect,
+			ARRAY_SIZE(state->regs->effect), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_METERING:
+		err = s5k5ccgx_set_from_table(sd, "metering",
+			state->regs->metering,
+			ARRAY_SIZE(state->regs->metering), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CONTRAST:
+		err = s5k5ccgx_set_from_table(sd, "contrast",
+			state->regs->contrast,
+			ARRAY_SIZE(state->regs->contrast), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SATURATION:
+		err = s5k5ccgx_set_from_table(sd, "saturation",
+			state->regs->saturation,
+			ARRAY_SIZE(state->regs->saturation), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SHARPNESS:
+		err = s5k5ccgx_set_from_table(sd, "sharpness",
+			state->regs->sharpness,
+			ARRAY_SIZE(state->regs->sharpness), ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_SCENE_MODE:
+		err = s5k5ccgx_set_scene_mode(sd, ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_AE_LOCK_UNLOCK:
+		err = s5k5ccgx_set_ae_lock(sd, ctrl->value, false);
+		break;
+
+	case V4L2_CID_CAMERA_AWB_LOCK_UNLOCK:
+		err = s5k5ccgx_set_awb_lock(sd, ctrl->value, false);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = s5k5ccgx_check_esd(sd);
+		break;
+
+	case V4L2_CID_CAMERA_ISO:
+		/* we do not break. */
+	case V4L2_CID_CAMERA_FRAME_RATE:
+	default:
+		cam_err("%s: WARNING, unknown Ctrl-ID 0x%x\n",
+			__func__, ctrl->id);
+		err = 0; /* we return no error. */
+		break;
+	}
+
+	if (ctrl->id != V4L2_CID_CAMERA_SET_AUTO_FOCUS)
+		mutex_unlock(&state->ctrl_lock);
+
+	CHECK_ERR_MSG(err, "s_ctrl failed %d\n", err)
+
+	return 0;
+}
+
+static int s5k5ccgx_s_ext_ctrl(struct v4l2_subdev *sd,
+			      struct v4l2_ext_control *ctrl)
+{
+	return 0;
+}
+
+static int s5k5ccgx_s_ext_ctrls(struct v4l2_subdev *sd,
+				struct v4l2_ext_controls *ctrls)
+{
+	struct v4l2_ext_control *ctrl = ctrls->controls;
+	int ret;
+	int i;
+
+	for (i = 0; i < ctrls->count; i++, ctrl++) {
+		ret = s5k5ccgx_s_ext_ctrl(sd, ctrl);
+
+		if (ret) {
+			ctrls->error_idx = i;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int s5k5ccgx_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("stream mode = %d\n", enable);
+
+	BUG_ON(!state->initialized);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->pdata->is_mipi)
+			err = s5k5ccgx_control_stream(sd, STREAM_STOP);
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		switch (state->sensor_mode) {
+		case SENSOR_CAMERA:
+			if (state->format_mode == V4L2_PIX_FMT_MODE_CAPTURE)
+				err = s5k5ccgx_set_capture_start(sd);
+			else
+				err = s5k5ccgx_set_preview_start(sd);
+			break;
+
+		case SENSOR_MOVIE:
+			err = s5k5ccgx_set_video_preview(sd);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_info("movie on");
+		state->recording = 1;
+		if (state->flash_mode != FLASH_MODE_OFF)
+			s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_ON);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_info("movie off");
+		state->recording = 0;
+		if (state->flash_on)
+			s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_OFF);
+		break;
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	case STREAM_MODE_WAIT_OFF:
+		s5k5ccgx_wait_steamoff(sd);
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR - Invalid stream mode\n", __func__);
+		break;
+	}
+
+	CHECK_ERR_MSG(err, "failed\n");
+
+	return 0;
+}
+
+static int s5k5ccgx_reset(struct v4l2_subdev *sd, u32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	cam_trace("EX\n");
+
+	s5k5ccgx_return_focus(sd);
+	state->initialized = 0;
+
+	return 0;
+}
+
+static int s5k5ccgx_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("%s: start\n", __func__);
+
+	err = s5k5ccgx_init_regs(sd);
+	CHECK_ERR_MSG(err, "failed to indentify sensor chip\n");
+
+	if (state->hd_videomode) {
+		cam_info("init: HD mode\n");
+		err = S5K5CCGX_BURST_WRITE_REGS(sd, s5k5ccgx_hd_init_reg);
+	} else {
+		cam_info("init: Cam, Non-HD mode\n");
+		err = S5K5CCGX_BURST_WRITE_REGS(sd, s5k5ccgx_init_reg);
+	}
+	CHECK_ERR_MSG(err, "failed to initialize camera device\n");
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+	s5k5ccgx_set_from_table(sd, "antibanding",
+		&state->regs->antibanding, 1, 0);
+#endif
+
+	state->runmode = S5K5CCGX_RUNMODE_INIT;
+
+	/* Default state values */
+	state->flash_mode = FLASH_MODE_OFF;
+	state->scene_mode = SCENE_MODE_NONE;
+	state->flash_on = 0;
+	state->light_level = 0xFFFFFFFF;
+	memset(&state->focus, 0, sizeof(state->focus));
+
+	state->initialized = 1;
+
+	if (state->sensor_mode == SENSOR_MOVIE)
+		s5k5ccgx_init_param(sd);
+
+	if (state->req_fps >= 0) {
+		err = s5k5ccgx_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int s5k5ccgx_s_config(struct v4l2_subdev *sd,
+			int irq, void *platform_data)
+{
+	struct s5k5ccgx_state *state = to_state(sd);
+	int i;
+#ifdef CONFIG_LOAD_FILE
+	int err = 0;
+#endif
+
+	if (!platform_data) {
+		cam_err("%s: ERROR, no platform data\n", __func__);
+		return -ENODEV;
+	}
+	state->pdata = platform_data;
+	state->dbg_level = &state->pdata->dbg_level;
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	state->req_fmt.width = state->pdata->default_width;
+	state->req_fmt.height = state->pdata->default_height;
+
+	if (!state->pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_PIX_FMT;
+	else
+		state->req_fmt.pixelformat = state->pdata->pixelformat;
+
+	if (!state->pdata->freq)
+		state->freq = DEFAULT_MCLK;	/* 24MHz default */
+	else
+		state->freq = state->pdata->freq;
+
+	state->preview = state->capture = NULL;
+	state->sensor_mode = SENSOR_CAMERA;
+	state->hd_videomode = 0;
+	state->format_mode = V4L2_PIX_FMT_MODE_PREVIEW;
+	state->fps = 0;
+	state->req_fps = -1;
+
+	for (i = 0; i < ARRAY_SIZE(s5k5ccgx_ctrls); i++)
+		s5k5ccgx_ctrls[i].value = s5k5ccgx_ctrls[i].default_value;
+
+#ifdef S5K5CCGX_SUPPORT_FLASH
+	if (s5k5ccgx_is_hwflash_on(sd))
+		state->ignore_flash = 1;
+#endif
+
+#if !defined(FEATURE_YUV_CAPTURE)
+	state->jpeg.enable = 0;
+	state->jpeg.quality = 100;
+	state->jpeg.main_offset = 1280; /* 0x500 */
+
+	/* Maximum size 2048 * 1536 * 2 = 6291456 */
+	state->jpeg.main_size = SENSOR_JPEG_SNAPSHOT_MEMSIZE;
+
+	state->jpeg.thumb_offset = 636; /* 0x27C */
+	state->jpeg.thumb_size = 320 * 240 * 2; /* 320 * 240 * 2 = 153600 */
+#endif
+
+#ifdef CONFIG_LOAD_FILE
+	err = loadFile();
+	if (unlikely(err < 0)) {
+		cam_err("failed to load file ERR=%d\n", err);
+		return err;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops s5k5ccgx_core_ops = {
+	.init = s5k5ccgx_init,	/* initializing API */
+	.g_ctrl = s5k5ccgx_g_ctrl,
+	.s_ctrl = s5k5ccgx_s_ctrl,
+	.s_ext_ctrls = s5k5ccgx_s_ext_ctrls,
+	.reset = s5k5ccgx_reset,
+};
+
+static const struct v4l2_subdev_video_ops s5k5ccgx_video_ops = {
+	.s_mbus_fmt = s5k5ccgx_s_mbus_fmt,
+	.enum_framesizes = s5k5ccgx_enum_framesizes,
+	.enum_mbus_fmt = s5k5ccgx_enum_mbus_fmt,
+	.try_mbus_fmt = s5k5ccgx_try_mbus_fmt,
+	.g_parm = s5k5ccgx_g_parm,
+	.s_parm = s5k5ccgx_s_parm,
+	.s_stream = s5k5ccgx_s_stream,
+};
+
+static const struct v4l2_subdev_ops s5k5ccgx_ops = {
+	.core = &s5k5ccgx_core_ops,
+	.video = &s5k5ccgx_video_ops,
+};
+
+
+/*
+ * s5k5ccgx_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int s5k5ccgx_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct v4l2_subdev *sd;
+	struct s5k5ccgx_state *state;
+	int err = -EINVAL;
+
+	state = kzalloc(sizeof(struct s5k5ccgx_state), GFP_KERNEL);
+	if (unlikely(!state)) {
+		dev_err(&client->dev, "probe, fail to get memory\n");
+		return -ENOMEM;
+	}
+
+	mutex_init(&state->ctrl_lock);
+	mutex_init(&state->af_lock);
+
+	state->runmode = S5K5CCGX_RUNMODE_NOTREADY;
+	sd = &state->sd;
+	strcpy(sd->name, S5K5CCGX_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &s5k5ccgx_ops);
+
+	state->workqueue = create_workqueue("cam_workqueue");
+	if (unlikely(!state->workqueue)) {
+		dev_err(&client->dev, "probe, fail to create workqueue\n");
+		goto err_out;
+	}
+	INIT_WORK(&state->af_work, s5k5ccgx_af_worker);
+	INIT_WORK(&state->af_win_work, s5k5ccgx_af_win_worker);
+
+	err = s5k5ccgx_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+	printk(KERN_DEBUG "%s %s: driver probed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+
+	return 0;
+
+err_out:
+	kfree(state);
+	return -ENOMEM;
+}
+
+static int s5k5ccgx_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct s5k5ccgx_state *state = to_state(sd);
+
+	destroy_workqueue(state->workqueue);
+
+	/* for softlanding */
+	if (state->initialized) {
+#ifdef CONFIG_VIDEO_S5K5CCGX_P4W
+		s5k5ccgx_set_af_softlanding(sd);
+#else
+		s5k5ccgx_return_focus(sd);
+#endif
+	}
+
+	/* Check whether flash is on when unlolading driver,
+	 * to preventing Market App from controlling improperly flash.
+	 * It isn't necessary in case that you power flash down
+	 * in power routine to turn camera off.*/
+	if (unlikely(state->flash_on && !state->ignore_flash))
+		s5k5ccgx_flash_torch(sd, S5K5CCGX_FLASH_OFF);
+
+	v4l2_device_unregister_subdev(sd);
+	mutex_destroy(&state->ctrl_lock);
+	mutex_destroy(&state->af_lock);
+	kfree(state);
+
+#ifdef CONFIG_LOAD_FILE
+	large_file ? vfree(testBuf) : kfree(testBuf);
+	large_file = 0;
+	testBuf = NULL;
+#endif
+
+	printk(KERN_DEBUG "%s %s: driver removed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static const struct i2c_device_id s5k5ccgx_id[] = {
+	{ S5K5CCGX_DRIVER_NAME, 0 },
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, s5k5ccgx_id);
+
+static struct i2c_driver v4l2_i2c_driver = {
+	.driver.name	= S5K5CCGX_DRIVER_NAME,
+	.probe		= s5k5ccgx_probe,
+	.remove		= s5k5ccgx_remove,
+	.id_table	= s5k5ccgx_id,
+};
+
+static int __init v4l2_i2c_drv_init(void)
+{
+	pr_info("%s: %s called\n", __func__, S5K5CCGX_DRIVER_NAME); /* dslim*/
+	return i2c_add_driver(&v4l2_i2c_driver);
+}
+
+static void __exit v4l2_i2c_drv_cleanup(void)
+{
+	pr_info("%s: %s called\n", __func__, S5K5CCGX_DRIVER_NAME); /* dslim*/
+	i2c_del_driver(&v4l2_i2c_driver);
+}
+
+module_init(v4l2_i2c_drv_init);
+module_exit(v4l2_i2c_drv_cleanup);
+
+MODULE_DESCRIPTION("LSI S5K5CCGX 3MP SOC camera driver");
+MODULE_AUTHOR("Dong-Seong Lim <dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5k5ccgx.h b/drivers/media/video/s5k5ccgx.h
new file mode 100644
index 0000000..09657b7
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx.h
@@ -0,0 +1,611 @@
+/* drivers/media/video/s5k5ccgx.h
+ *
+ * Driver for s5k5ccgx (3MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5K5CCGX_H__
+#define __S5K5CCGX_H__
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/completion.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/s5k5ccgx_platform.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/workqueue.h>
+
+#define S5K5CCGX_DRIVER_NAME	"S5K5CCGX"
+
+#define S5K5CCGX_DELAY		0xFFFF0000
+
+/************************************
+ * FEATURE DEFINITIONS
+ ************************************/
+#define FEATURE_YUV_CAPTURE
+/* #define CONFIG_LOAD_FILE */ /* for tuning */
+
+/** Debuging Feature **/
+#define CONFIG_CAM_DEBUG
+/* #define CONFIG_CAM_TRACE*/ /* Enable it with CONFIG_CAM_DEBUG */
+/* #define CONFIG_CAM_AF_DEBUG *//* Enable it with CONFIG_CAM_DEBUG */
+/* #define DEBUG_WRITE_REGS */
+/***********************************/
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_DEBUG
+enum {
+	S5K5CCGX_DEBUG_I2C		= 1U << 0,
+	S5K5CCGX_DEBUG_I2C_BURSTS	= 1U << 1,
+};
+static uint32_t s5k5ccgx_debug_mask = S5K5CCGX_DEBUG_I2C_BURSTS;
+module_param_named(debug_mask, s5k5ccgx_debug_mask, uint, S_IWUSR | S_IRUGO);
+
+#define s5k5ccgx_debug(mask, x...) \
+	do { \
+		if (s5k5ccgx_debug_mask & mask) \
+			pr_info(x);	\
+	} while (0)
+#else
+#define s5k5ccgx_debug(mask, x...)
+#endif
+
+#define TAG_NAME	"["S5K5CCGX_DRIVER_NAME"]"" "
+#define cam_err(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_warn(fmt, ...)	\
+	printk(KERN_WARNING TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_info(fmt, ...)	\
+	printk(KERN_INFO TAG_NAME fmt, ##__VA_ARGS__)
+
+#if defined(CONFIG_CAM_DEBUG)
+#define cam_dbg(fmt, ...)	\
+	printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_DEBUG) \
+			printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_TRACE)
+#define cam_trace(fmt, ...)	cam_dbg("%s: " fmt, __func__, ##__VA_ARGS__);
+#else
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_TRACE) \
+			printk(KERN_DEBUG TAG_NAME "%s: " fmt, \
+				__func__, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_AF_DEBUG)
+#define af_dbg(fmt, ...)	cam_dbg(fmt, ##__VA_ARGS__);
+#else
+#define af_dbg(fmt, ...)
+#endif
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return ret; } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+		if (unlikely(condition)) { \
+			cam_err("%s: ERROR, " fmt, __func__, ##__VA_ARGS__); \
+			return ret; \
+		}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+
+#ifdef CONFIG_LOAD_FILE
+#define S5K5CCGX_BURST_WRITE_REGS(sd, A) ({ \
+	int ret; \
+		cam_info("BURST_WRITE_REGS: reg_name=%s from setfile\n", #A); \
+		ret = s5k5ccgx_write_regs_from_sd(sd, #A); \
+		ret; \
+	})
+#else
+#define S5K5CCGX_BURST_WRITE_REGS(sd, A) \
+	s5k5ccgx_burst_write_regs(sd, A, (sizeof(A) / sizeof(A[0])), #A)
+#endif
+
+/* result values returned to HAL */
+enum af_result_status {
+	AF_RESULT_NONE = 0x00,
+	AF_RESULT_FAILED = 0x01,
+	AF_RESULT_SUCCESS = 0x02,
+	AF_RESULT_CANCELLED = 0x04,
+	AF_RESULT_DOING = 0x08
+};
+
+enum af_operation_status {
+	AF_NONE = 0,
+	AF_START,
+	AF_CANCEL,
+};
+
+enum preflash_status {
+	PREFLASH_NONE = 0,
+	PREFLASH_OFF,
+	PREFLASH_ON,
+};
+
+enum s5k5ccgx_oprmode {
+	S5K5CCGX_OPRMODE_VIDEO = 0,
+	S5K5CCGX_OPRMODE_IMAGE = 1,
+};
+
+enum stream_cmd {
+	STREAM_STOP,
+	STREAM_START,
+};
+
+enum wide_req_cmd {
+	WIDE_REQ_NONE,
+	WIDE_REQ_CHANGE,
+	WIDE_REQ_RESTORE,
+};
+
+enum s5k5ccgx_preview_frame_size {
+	S5K5CCGX_PREVIEW_QCIF = 0,	/* 176x144 */
+	S5K5CCGX_PREVIEW_320x240,	/* 320x240 */
+	S5K5CCGX_PREVIEW_CIF,		/* 352x288 */
+	S5K5CCGX_PREVIEW_528x432,	/* 528x432 */
+	S5K5CCGX_PREVIEW_VGA,		/* 640x480 */
+	S5K5CCGX_PREVIEW_D1,		/* 720x480 */
+	S5K5CCGX_PREVIEW_SVGA,		/* 800x600 */
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+	S5K5CCGX_PREVIEW_1024x552,	/* 1024x552, ? */
+#else
+	S5K5CCGX_PREVIEW_1024x576,	/* 1024x576, 16:9 */
+#endif
+	S5K5CCGX_PREVIEW_1024x616,	/* 1024x616, ? */
+	S5K5CCGX_PREVIEW_XGA,		/* 1024x768*/
+	S5K5CCGX_PREVIEW_PVGA,		/* 1280*720*/
+	S5K5CCGX_PREVIEW_SXGA,		/* 1280x1024*/
+	S5K5CCGX_PREVIEW_MAX,
+};
+
+/* Capture Size List: Capture size is defined as below.
+ *
+ *	S5K5CCGX_CAPTURE_VGA:		640x480
+ *	S5K5CCGX_CAPTURE_WVGA:		800x480
+ *	S5K5CCGX_CAPTURE_SVGA:		800x600
+ *	S5K5CCGX_CAPTURE_WSVGA:		1024x600
+ *	S5K5CCGX_CAPTURE_1MP:		1280x960
+ *	S5K5CCGX_CAPTURE_W1MP:		1600x960
+ *	S5K5CCGX_CAPTURE_2MP:		UXGA - 1600x1200
+ *	S5K5CCGX_CAPTURE_W2MP:		35mm Academy Offset Standard 1.66
+ *					2048x1232, 2.4MP
+ *	S5K5CCGX_CAPTURE_3MP:		QXGA  - 2048x1536
+ *	S5K5CCGX_CAPTURE_W4MP:		WQXGA - 2560x1536
+ *	S5K5CCGX_CAPTURE_5MP:		2560x1920
+ */
+
+enum s5k5ccgx_capture_frame_size {
+	S5K5CCGX_CAPTURE_VGA = 0,	/* 640x480 */
+	S5K5CCGX_CAPTURE_W2MP,		/* 35mm Academy Offset Standard 1.66 */
+					/* 2048x1232, 2.4MP */
+	S5K5CCGX_CAPTURE_3MP,		/* QXGA  - 2048x1536 */
+	S5K5CCGX_CAPTURE_MAX,
+};
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+#define PREVIEW_WIDE_SIZE	S5K5CCGX_PREVIEW_1024x552
+#else
+#define PREVIEW_WIDE_SIZE	S5K5CCGX_PREVIEW_1024x576
+#endif
+#define CAPTURE_WIDE_SIZE	S5K5CCGX_CAPTURE_W2MP
+
+enum s5k5ccgx_fps_index {
+	I_FPS_0,
+	I_FPS_7,
+	I_FPS_10,
+	I_FPS_12,
+	I_FPS_15,
+	I_FPS_25,
+	I_FPS_30,
+	I_FPS_MAX,
+};
+
+enum ae_awb_lock {
+	AEAWB_UNLOCK = 0,
+	AEAWB_LOCK,
+	AEAWB_LOCK_MAX,
+};
+
+struct s5k5ccgx_control {
+	u32 id;
+	s32 value;
+	s32 default_value;
+};
+
+#define S5K5CCGX_INIT_CONTROL(ctrl_id, default_val) \
+	{					\
+		.id = ctrl_id,			\
+		.value = default_val,		\
+		.default_value = default_val,	\
+	}
+
+struct s5k5ccgx_framesize {
+	s32 index;
+	u32 width;
+	u32 height;
+};
+
+#define FRM_RATIO(framesize) \
+	(((framesize)->width) * 10 / ((framesize)->height))
+
+struct s5k5ccgx_fps {
+	u32 index;
+	u32 fps;
+};
+
+struct s5k5ccgx_version {
+	u32 major;
+	u32 minor;
+};
+
+struct s5k5ccgx_date_info {
+	u32 year;
+	u32 month;
+	u32 date;
+};
+
+enum s5k5ccgx_runmode {
+	S5K5CCGX_RUNMODE_NOTREADY,
+	S5K5CCGX_RUNMODE_INIT,
+	/*S5K5CCGX_RUNMODE_IDLE,*/
+	S5K5CCGX_RUNMODE_RUNNING, /* previewing */
+	S5K5CCGX_RUNMODE_RUNNING_STOP,
+	S5K5CCGX_RUNMODE_CAPTURING,
+	S5K5CCGX_RUNMODE_CAPTURE_STOP,
+};
+
+struct s5k5ccgx_firmware {
+	u32 addr;
+	u32 size;
+};
+
+struct s5k5ccgx_jpeg_param {
+	u32 enable;
+	u32 quality;
+	u32 main_size;		/* Main JPEG file size */
+	u32 thumb_size;		/* Thumbnail file size */
+	u32 main_offset;
+	u32 thumb_offset;
+	/* u32 postview_offset; */
+};
+
+struct s5k5ccgx_position {
+	s32 x;
+	s32 y;
+};
+
+struct s5k5ccgx_rect {
+	s32 x;
+	s32 y;
+	u32 width;
+	u32 height;
+};
+
+struct gps_info_common {
+	u32 direction;
+	u32 dgree;
+	u32 minute;
+	u32 second;
+};
+
+struct s5k5ccgx_gps_info {
+	u8 gps_buf[8];
+	u8 altitude_buf[4];
+	s32 gps_timeStamp;
+};
+
+struct s5k5ccgx_focus {
+	enum v4l2_focusmode mode;
+	enum af_result_status status;
+	enum preflash_status preflash;
+
+	u32 pos_x;
+	u32 pos_y;
+
+	u32 start:1;	/* enum v4l2_auto_focus*/
+	u32 ae_lock:1;
+	u32 awb_lock:1;
+	u32 touch:1;
+	u32 af_cancel:1;
+};
+
+struct s5k5ccgx_exif {
+	u16 exp_time_den;
+	u16 iso;
+	u16 flash;
+
+	/*int bv;*/		/* brightness */
+	/*int ebv;*/		/* exposure bias */
+};
+
+/* EXIF - flash filed */
+#define EXIF_FLASH_FIRED		(0x01)
+#define EXIF_FLASH_MODE_FIRING		(0x01)
+#define EXIF_FLASH_MODE_SUPPRESSION	(0x01 << 1)
+#define EXIF_FLASH_MODE_AUTO		(0x03 << 3)
+
+struct s5k5ccgx_regset {
+	u32 size;
+	u8 *data;
+};
+
+struct s5k5ccgx_stream_time {
+	struct timeval curr_time;
+	struct timeval before_time;
+};
+
+#define GET_ELAPSED_TIME(cur, before) \
+		(((cur).tv_sec - (before).tv_sec) * USEC_PER_SEC \
+		+ ((cur).tv_usec - (before).tv_usec))
+
+#ifdef CONFIG_LOAD_FILE
+#define DEBUG_WRITE_REGS
+struct s5k5ccgx_regset_table {
+	const char	*const name;
+};
+
+#define S5K5CCGX_REGSET(x, y)		\
+	[(x)] = {			\
+		.name		= #y,	\
+}
+
+#define S5K5CCGX_REGSET_TABLE(y)	\
+	{				\
+		.name		= #y,	\
+}
+#else
+struct s5k5ccgx_regset_table {
+	const u32	*const reg;
+	const u32	array_size;
+#ifdef DEBUG_WRITE_REGS
+	const char	*const name;
+#endif
+};
+
+#ifdef DEBUG_WRITE_REGS
+#define S5K5CCGX_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+
+#define S5K5CCGX_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+#else
+#define S5K5CCGX_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+
+#define S5K5CCGX_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+#endif /* DEBUG_WRITE_REGS */
+#endif /* CONFIG_LOAD_FILE */
+
+#define EV_MIN_VLAUE		EV_MINUS_4
+#define GET_EV_INDEX(EV)	((EV) - (EV_MIN_VLAUE))
+
+struct s5k5ccgx_regs {
+	struct s5k5ccgx_regset_table ev[GET_EV_INDEX(EV_MAX_V4L2)];
+	struct s5k5ccgx_regset_table metering[METERING_MAX];
+	struct s5k5ccgx_regset_table iso[ISO_MAX];
+	struct s5k5ccgx_regset_table effect[IMAGE_EFFECT_MAX];
+	struct s5k5ccgx_regset_table white_balance[WHITE_BALANCE_MAX];
+	struct s5k5ccgx_regset_table preview_size[S5K5CCGX_PREVIEW_MAX];
+	struct s5k5ccgx_regset_table capture_start[S5K5CCGX_CAPTURE_MAX];
+	struct s5k5ccgx_regset_table scene_mode[SCENE_MODE_MAX];
+	struct s5k5ccgx_regset_table saturation[SATURATION_MAX];
+	struct s5k5ccgx_regset_table contrast[CONTRAST_MAX];
+	struct s5k5ccgx_regset_table sharpness[SHARPNESS_MAX];
+	struct s5k5ccgx_regset_table fps[I_FPS_MAX];
+	struct s5k5ccgx_regset_table preview_return;
+	struct s5k5ccgx_regset_table flash_start;
+	struct s5k5ccgx_regset_table flash_end;
+	struct s5k5ccgx_regset_table af_pre_flash_start;
+	struct s5k5ccgx_regset_table af_pre_flash_end;
+	struct s5k5ccgx_regset_table flash_ae_set;
+	struct s5k5ccgx_regset_table flash_ae_clear;
+	struct s5k5ccgx_regset_table ae_lock_on;
+	struct s5k5ccgx_regset_table ae_lock_off;
+	struct s5k5ccgx_regset_table awb_lock_on;
+	struct s5k5ccgx_regset_table awb_lock_off;
+	struct s5k5ccgx_regset_table restore_cap;
+	struct s5k5ccgx_regset_table change_wide_cap;
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+	struct s5k5ccgx_regset_table set_lowlight_cap;
+#endif
+	struct s5k5ccgx_regset_table af_macro_mode;
+	struct s5k5ccgx_regset_table af_normal_mode;
+#if !defined(CONFIG_VIDEO_S5K5CCGX_P2)
+	struct s5k5ccgx_regset_table af_night_normal_mode;
+#endif
+#ifdef CONFIG_VIDEO_S5K5CCGX_P4W
+	struct s5k5ccgx_regset_table af_off;
+#endif
+	struct s5k5ccgx_regset_table hd_af_start;
+	struct s5k5ccgx_regset_table hd_first_af_start;
+	struct s5k5ccgx_regset_table single_af_start;
+	struct s5k5ccgx_regset_table init_reg;
+	struct s5k5ccgx_regset_table get_light_level;
+	struct s5k5ccgx_regset_table get_esd_status;
+	struct s5k5ccgx_regset_table get_iso;
+	struct s5k5ccgx_regset_table get_ae_stable;
+	struct s5k5ccgx_regset_table get_shutterspeed;
+	struct s5k5ccgx_regset_table update_preview;
+	struct s5k5ccgx_regset_table update_hd_preview;
+	struct s5k5ccgx_regset_table stream_stop;
+#ifdef CONFIG_VIDEO_S5K5CCGX_P8
+	struct s5k5ccgx_regset_table antibanding;
+#endif /* CONFIG_VIDEO_S5K5CCGX_P8 */
+};
+
+struct s5k5ccgx_state {
+	struct s5k5ccgx_platform_data *pdata;
+	struct v4l2_subdev sd;
+	struct v4l2_pix_format req_fmt;
+	struct s5k5ccgx_framesize *preview;
+	struct s5k5ccgx_framesize *capture;
+	struct s5k5ccgx_focus focus;
+	struct s5k5ccgx_exif exif;
+#if !defined(FEATURE_YUV_CAPTURE)
+	struct s5k5ccgx_jpeg_param jpeg;
+#endif
+	struct s5k5ccgx_stream_time stream_time;
+	const struct s5k5ccgx_regs *regs;
+	struct mutex ctrl_lock;
+	struct mutex af_lock;
+	struct work_struct af_work;
+	struct work_struct af_win_work;
+	struct workqueue_struct *workqueue;
+	enum s5k5ccgx_runmode runmode;
+	enum v4l2_sensor_mode sensor_mode;
+	enum v4l2_pix_format_mode format_mode;
+	enum v4l2_flash_mode flash_mode;
+	enum v4l2_scene_mode scene_mode;
+	enum v4l2_wb_mode wb_mode;
+
+	/* To switch from nornal ratio to wide ratio.*/
+	enum wide_req_cmd wide_cmd;
+
+	s32 vt_mode;
+	s32 req_fps;
+	s32 fps;
+	s32 freq;		/* MCLK in Hz */
+	u32 one_frame_delay_ms;
+	u32 light_level;	/* light level */
+	u8 *dbg_level;
+
+	u32 recording:1;
+	u32 hd_videomode:1;
+	u32 flash_on:1;
+	u32 ignore_flash:1;
+	u32 need_update_frmsize:1;
+	u32 need_wait_streamoff:1;
+	u32 initialized:1;
+};
+
+static inline struct  s5k5ccgx_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k5ccgx_state, sd);
+}
+
+static inline void debug_msleep(struct v4l2_subdev *sd, u32 msecs)
+{
+	cam_dbg("delay for %dms\n", msecs);
+	msleep(msecs);
+}
+
+#if !defined(FEATURE_YUV_CAPTURE)
+/* JPEG MEMORY SIZE */
+#define SENSOR_JPEG_OUTPUT_MAXSIZE	0x29999A /*2726298bytes, 2.6M */
+#define EXTRA_MEMSIZE			(0 * SZ_1K)
+#define SENSOR_JPEG_SNAPSHOT_MEMSIZE \
+	(((SENSOR_JPEG_OUTPUT_MAXSIZE + EXTRA_MEMSIZE  + SZ_16K-1) / SZ_16K) * SZ_16K)
+#endif
+
+/*********** Sensor specific ************/
+#define S5K5CCGX_CHIP_ID	0x05CC
+#define S5K5CCGX_CHIP_REV	0x0001
+
+#define FORMAT_FLAGS_COMPRESSED		0x3
+
+#define POLL_TIME_MS		10
+#define CAPTURE_POLL_TIME_MS    1000
+
+/* maximum time for one frame in norma light */
+#define ONE_FRAME_DELAY_MS_NORMAL		66
+/* maximum time for one frame in low light: minimum 10fps. */
+#define ONE_FRAME_DELAY_MS_LOW			100
+/* maximum time for one frame in night mode: 6fps */
+#define ONE_FRAME_DELAY_MS_NIGHTMODE		166
+
+/* level at or below which we need to enable flash when in auto mode */
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+#define FLASH_LOW_LIGHT_LEVEL		0x3A
+#elif defined(CONFIG_VIDEO_S5K5CCGX_P8)
+#define FLASH_LOW_LIGHT_LEVEL		0x46 /* 70 */
+#define CAPTURE_LOW_LIGHT_LEVEL		0x20
+#else
+#define FLASH_LOW_LIGHT_LEVEL		0x4A
+#endif /* CONFIG_VIDEO_S5K5CCGX_P2 */
+
+#define FIRST_AF_SEARCH_COUNT   80
+#define SECOND_AF_SEARCH_COUNT  80
+#define AE_STABLE_SEARCH_COUNT	7 /* 4->7. but ae-unstable still occurs. */
+
+/* Sensor AF first,second window size.
+ * we use constant values intead of reading sensor register */
+#define FIRST_WINSIZE_X			512
+#define FIRST_WINSIZE_Y			568
+#define SCND_WINSIZE_X			230
+#define SCND_WINSIZE_Y			306
+
+/* The Path of Setfile */
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+struct test {
+	u8 data;
+	struct test *nextBuf;
+};
+static struct test *testBuf;
+static s32 large_file;
+
+#define TEST_INIT	\
+{			\
+	.data = 0;	\
+	.nextBuf = NULL;	\
+}
+
+#if defined(CONFIG_VIDEO_S5K5CCGX_P4W)
+#define TUNING_FILE_PATH "/mnt/sdcard/s5k5ccgx_regs-p4w.h"
+#elif defined(CONFIG_VIDEO_S5K5CCGX_P8)
+#define TUNING_FILE_PATH "/mnt/sdcard/s5k5ccgx_regs-p8.h"
+#elif defined(CONFIG_VIDEO_S5K5CCGX_P2)
+#define TUNING_FILE_PATH "/mnt/sdcard/s5k5ccgx_regs-p2.h"
+#else
+#define TUNING_FILE_PATH NULL
+#endif
+#endif /* CONFIG_LOAD_FILE*/
+
+#if defined(CONFIG_VIDEO_S5K5CCGX_P4W)
+#include "s5k5ccgx_regs-p4w.h"
+#elif defined(CONFIG_VIDEO_S5K5CCGX_P8)
+#include "s5k5ccgx_regs-p8.h"
+#elif defined(CONFIG_VIDEO_S5K5CCGX_P2)
+#include "s5k5ccgx_regs-p2.h"
+#else
+#include "s5k5ccgx_regs-p4w.h"
+#endif /* CONFIG_VIDEO_S5K5CCGX_P4W*/
+
+#endif /* __S5K5CCGX_H__ */
diff --git a/drivers/media/video/s5k5ccgx_reg.h b/drivers/media/video/s5k5ccgx_reg.h
new file mode 100644
index 0000000..4ec30e1
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx_reg.h
@@ -0,0 +1,16118 @@
+/* drivers/media/video/s5k5ccgx_reg.h
+ * latest version: 11/09/27
+ * 
+ * Driver for s5k5ccgx (5MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+
+#ifndef __S5K5CCGX_REG_H__
+#define __S5K5CCGX_REG_H__
+
+/* Init regs for YUV capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+0xFCFCD000,	//Reset                                  //
+0x00140001, //Wait100mSec                            //
+0x10021101,  
+
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000          //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A,     //p10
+// Start of Patch data
+0x00287000,
+0x002A352C,
+0x0F12B570, // 7000352C 
+0x0F124A24, // 7000352E 
+0x0F124924, // 70003530 
+0x0F124825, // 70003532 
+0x0F124B25, // 70003534 
+0x0F122500, // 70003536 
+0x0F12801D, // 70003538 
+0x0F12C004, // 7000353A 
+0x0F126001, // 7000353C 
+0x0F124924, // 7000353E 
+0x0F124824, // 70003540 
+0x0F12F000, // 70003542 
+0x0F12FBBD, // 70003544 
+0x0F124924, // 70003546 
+0x0F124824, // 70003548 
+0x0F12F000, // 7000354A 
+0x0F12FBB9, // 7000354C 
+0x0F124824, // 7000354E 
+0x0F124E24, // 70003550 
+0x0F126430, // 70003552 
+0x0F124924, // 70003554 
+0x0F124825, // 70003556 
+0x0F12F000, // 70003558 
+0x0F12FBB2, // 7000355A 
+0x0F124924, // 7000355C 
+0x0F120030, // 7000355E 
+0x0F123080, // 70003560 
+0x0F126141, // 70003562 
+0x0F124C23, // 70003564 
+0x0F128365, // 70003566 
+0x0F124923, // 70003568 
+0x0F124824, // 7000356A 
+0x0F12F000, // 7000356C 
+0x0F12FBA8, // 7000356E 
+0x0F124923, // 70003570 
+0x0F124824, // 70003572 
+0x0F12F000, // 70003574 
+0x0F12FBA4, // 70003576 
+0x0F124923, // 70003578 
+0x0F124824, // 7000357A 
+0x0F12F000, // 7000357C 
+0x0F12FBA0, // 7000357E 
+0x0F124923, // 70003580 
+0x0F124824, // 70003582 
+0x0F12F000, // 70003584 
+0x0F12FB9C, // 70003586 
+0x0F128125, // 70003588 
+0x0F124923, // 7000358A 
+0x0F124823, // 7000358C 
+0x0F12F000, // 7000358E 
+0x0F12FB97, // 70003590 
+0x0F124923, // 70003592 
+0x0F124823, // 70003594 
+0x0F12F000, // 70003596 
+0x0F12FB93, // 70003598 
+0x0F1283A5, // 7000359A 
+0x0F124922, // 7000359C 
+0x0F124823, // 7000359E 
+0x0F12F000, // 700035A0 
+0x0F12FB8E, // 700035A2 
+0x0F122101, // 700035A4 
+0x0F120349, // 700035A6 
+0x0F120020, // 700035A8 
+0x0F123020, // 700035AA 
+0x0F128041, // 700035AC 
+0x0F122185, // 700035AE 
+0x0F128081, // 700035B0 
+0x0F12491F, // 700035B2 
+0x0F1280C1, // 700035B4 
+0x0F12481F, // 700035B6 
+0x0F126730, // 700035B8 
+0x0F12BC70, // 700035BA 
+0x0F12BC08, // 700035BC 
+0x0F124718, // 700035BE 
+0x0F1200CA, // 700035C0 
+0x0F125CC1, // 700035C2 
+0x0F1203BD, // 700035C4 
+0x0F120000, // 700035C6 
+0x0F121C08, // 700035C8 
+0x0F127000, // 700035CA 
+0x0F123290, // 700035CC 
+0x0F127000, // 700035CE 
+0x0F123657, // 700035D0 
+0x0F127000, // 700035D2 
+0x0F12D9E7, // 700035D4 
+0x0F120000, // 700035D6 
+0x0F12383F, // 700035D8 
+0x0F127000, // 700035DA 
+0x0F12395D, // 700035DC 
+0x0F120000, // 700035DE 
+0x0F1238D1, // 700035E0 
+0x0F127000, // 700035E2 
+0x0F120000, // 700035E4 
+0x0F127000, // 700035E6 
+0x0F12399D, // 700035E8 
+0x0F127000, // 700035EA 
+0x0F12F903, // 700035EC 
+0x0F120000, // 700035EE 
+0x0F123AC1, // 700035F0 
+0x0F127000, // 700035F2 
+0x0F123FC8, // 700035F4 
+0x0F127000, // 700035F6 
+0x0F12368F, // 700035F8 
+0x0F127000, // 700035FA 
+0x0F12495F, // 700035FC 
+0x0F120000, // 700035FE 
+0x0F1236ED, // 70003600 
+0x0F127000, // 70003602 
+0x0F12E421, // 70003604 
+0x0F120000, // 70003606 
+0x0F1237AB, // 70003608 
+0x0F127000, // 7000360A 
+0x0F12216D, // 7000360C 
+0x0F120000, // 7000360E 
+0x0F12381F, // 70003610 
+0x0F127000, // 70003612 
+0x0F120179, // 70003614 
+0x0F120001, // 70003616 
+0x0F123BD5, // 70003618 
+0x0F127000, // 7000361A 
+0x0F1204C9, // 7000361C 
+0x0F120000, // 7000361E 
+0x0F123B25, // 70003620 
+0x0F127000, // 70003622 
+0x0F125027, // 70003624 
+0x0F120000, // 70003626 
+0x0F123BE1, // 70003628 
+0x0F127000, // 7000362A 
+0x0F1242B7, // 7000362C 
+0x0F120000, // 7000362E 
+0x0F1207FF, // 70003630 
+0x0F120000, // 70003632 
+0x0F123C5F, // 70003634 
+0x0F127000, // 70003636 
+0x0F12B570, // 70003638 
+0x0F12000D, // 7000363A 
+0x0F124CFC, // 7000363C 
+0x0F128821, // 7000363E 
+0x0F12F000, // 70003640 
+0x0F12FB46, // 70003642 
+0x0F128820, // 70003644 
+0x0F124AFB, // 70003646 
+0x0F120081, // 70003648 
+0x0F125055, // 7000364A 
+0x0F121C40, // 7000364C 
+0x0F128020, // 7000364E 
+0x0F12BC70, // 70003650 
+0x0F12BC08, // 70003652 
+0x0F124718, // 70003654 
+0x0F126801, // 70003656 
+0x0F120409, // 70003658 
+0x0F120C09, // 7000365A 
+0x0F126840, // 7000365C 
+0x0F120400, // 7000365E 
+0x0F120C00, // 70003660 
+0x0F124AF5, // 70003662 
+0x0F128992, // 70003664 
+0x0F122A00, // 70003666 
+0x0F12D00D, // 70003668 
+0x0F122300, // 7000366A 
+0x0F121A80, // 7000366C 
+0x0F12D400, // 7000366E 
+0x0F120003, // 70003670 
+0x0F120418, // 70003672 
+0x0F120C00, // 70003674 
+0x0F124BF1, // 70003676 
+0x0F121851, // 70003678 
+0x0F12891B, // 7000367A 
+0x0F12428B, // 7000367C 
+0x0F12D300, // 7000367E 
+0x0F12000B, // 70003680 
+0x0F120419, // 70003682 
+0x0F120C09, // 70003684 
+0x0F124AEE, // 70003686 
+0x0F128151, // 70003688 
+0x0F128190, // 7000368A 
+0x0F124770, // 7000368C 
+0x0F12B510, // 7000368E 
+0x0F124CEC, // 70003690 
+0x0F1248ED, // 70003692 
+0x0F1278A1, // 70003694 
+0x0F122900, // 70003696 
+0x0F12D101, // 70003698 
+0x0F1287C1, // 7000369A 
+0x0F12E004, // 7000369C 
+0x0F127AE1, // 7000369E 
+0x0F122900, // 700036A0 
+0x0F12D001, // 700036A2 
+0x0F122101, // 700036A4 
+0x0F1287C1, // 700036A6 
+0x0F12F000, // 700036A8 
+0x0F12FB1A, // 700036AA 
+0x0F1249E7, // 700036AC 
+0x0F128B08, // 700036AE 
+0x0F1206C2, // 700036B0 
+0x0F12D50A, // 700036B2 
+0x0F127AA2, // 700036B4 
+0x0F120652, // 700036B6 
+0x0F12D507, // 700036B8 
+0x0F122210, // 700036BA 
+0x0F124390, // 700036BC 
+0x0F128308, // 700036BE 
+0x0F1248E3, // 700036C0 
+0x0F127AE1, // 700036C2 
+0x0F126B00, // 700036C4 
+0x0F12F000, // 700036C6 
+0x0F12FB13, // 700036C8 
+0x0F1248DB, // 700036CA 
+0x0F1289C0, // 700036CC 
+0x0F122801, // 700036CE 
+0x0F12D109, // 700036D0 
+0x0F1278A0, // 700036D2 
+0x0F122800, // 700036D4 
+0x0F12D006, // 700036D6 
+0x0F127AE0, // 700036D8 
+0x0F122800, // 700036DA 
+0x0F12D003, // 700036DC 
+0x0F127AA0, // 700036DE 
+0x0F122140, // 700036E0 
+0x0F124308, // 700036E2 
+0x0F1272A0, // 700036E4 
+0x0F12BC10, // 700036E6 
+0x0F12BC08, // 700036E8 
+0x0F124718, // 700036EA 
+0x0F12B570, // 700036EC 
+0x0F124DD7, // 700036EE 
+0x0F124CD7, // 700036F0 
+0x0F128B28, // 700036F2 
+0x0F120701, // 700036F4 
+0x0F12D507, // 700036F6 
+0x0F122108, // 700036F8 
+0x0F124388, // 700036FA 
+0x0F128328, // 700036FC 
+0x0F1249D5, // 700036FE 
+0x0F126B20, // 70003700 
+0x0F126B89, // 70003702 
+0x0F12F000, // 70003704 
+0x0F12FAFC, // 70003706 
+0x0F128B28, // 70003708 
+0x0F1206C1, // 7000370A 
+0x0F12D5A0, // 7000370C 
+0x0F1249CD, // 7000370E 
+0x0F127A8A, // 70003710 
+0x0F120652, // 70003712 
+0x0F12D49C, // 70003714 
+0x0F122210, // 70003716 
+0x0F124390, // 70003718 
+0x0F128328, // 7000371A 
+0x0F127AC9, // 7000371C 
+0x0F126B20, // 7000371E 
+0x0F12F000, // 70003720 
+0x0F12FAE6, // 70003722 
+0x0F12E794, // 70003724 
+0x0F12B5F8, // 70003726 
+0x0F1249CB, // 70003728 
+0x0F128F08, // 7000372A 
+0x0F12000C, // 7000372C 
+0x0F123480, // 7000372E 
+0x0F122800, // 70003730 
+0x0F12D000, // 70003732 
+0x0F128360, // 70003734 
+0x0F122000, // 70003736 
+0x0F128708, // 70003738 
+0x0F124DC8, // 7000373A 
+0x0F1226FF, // 7000373C 
+0x0F128828, // 7000373E 
+0x0F121C76, // 70003740 
+0x0F122702, // 70003742 
+0x0F122803, // 70003744 
+0x0F12D112, // 70003746 
+0x0F128868, // 70003748 
+0x0F122800, // 7000374A 
+0x0F12D10F, // 7000374C 
+0x0F1288E8, // 7000374E 
+0x0F122800, // 70003750 
+0x0F12D10C, // 70003752 
+0x0F12F000, // 70003754 
+0x0F12FADC, // 70003756 
+0x0F122800, // 70003758 
+0x0F12D008, // 7000375A 
+0x0F128B60, // 7000375C 
+0x0F122800, // 7000375E 
+0x0F12D001, // 70003760 
+0x0F1280EE, // 70003762 
+0x0F1280AF, // 70003764 
+0x0F122001, // 70003766 
+0x0F127268, // 70003768 
+0x0F12F000, // 7000376A 
+0x0F12FAD9, // 7000376C 
+0x0F128828, // 7000376E 
+0x0F122802, // 70003770 
+0x0F12D10E, // 70003772 
+0x0F128868, // 70003774 
+0x0F122800, // 70003776 
+0x0F12D10B, // 70003778 
+0x0F1288E8, // 7000377A 
+0x0F122800, // 7000377C 
+0x0F12D108, // 7000377E 
+0x0F128B60, // 70003780 
+0x0F122800, // 70003782 
+0x0F12D001, // 70003784 
+0x0F1280EE, // 70003786 
+0x0F1280AF, // 70003788 
+0x0F122001, // 7000378A 
+0x0F127268, // 7000378C 
+0x0F12F000, // 7000378E 
+0x0F12FAC7, // 70003790 
+0x0F1288E8, // 70003792 
+0x0F122800, // 70003794 
+0x0F12D006, // 70003796 
+0x0F121FC1, // 70003798 
+0x0F1239FD, // 7000379A 
+0x0F12D003, // 7000379C 
+0x0F122001, // 7000379E 
+0x0F12BCF8, // 700037A0 
+0x0F12BC08, // 700037A2 
+0x0F124718, // 700037A4 
+0x0F122000, // 700037A6 
+0x0F12E7FA, // 700037A8 
+0x0F12B570, // 700037AA 
+0x0F124CAC, // 700037AC 
+0x0F128860, // 700037AE 
+0x0F122800, // 700037B0 
+0x0F12D00C, // 700037B2 
+0x0F128820, // 700037B4 
+0x0F124DA3, // 700037B6 
+0x0F122800, // 700037B8 
+0x0F12D009, // 700037BA 
+0x0F120029, // 700037BC 
+0x0F1231A0, // 700037BE 
+0x0F127AC9, // 700037C0 
+0x0F122900, // 700037C2 
+0x0F12D004, // 700037C4 
+0x0F127AA8, // 700037C6 
+0x0F122180, // 700037C8 
+0x0F124308, // 700037CA 
+0x0F1272A8, // 700037CC 
+0x0F12E73F, // 700037CE 
+0x0F122800, // 700037D0 
+0x0F12D003, // 700037D2 
+0x0F12F7FF, // 700037D4 
+0x0F12FFA7, // 700037D6 
+0x0F122800, // 700037D8 
+0x0F12D1F8, // 700037DA 
+0x0F122000, // 700037DC 
+0x0F128060, // 700037DE 
+0x0F128820, // 700037E0 
+0x0F122800, // 700037E2 
+0x0F12D003, // 700037E4 
+0x0F122008, // 700037E6 
+0x0F12F000, // 700037E8 
+0x0F12FAA2, // 700037EA 
+0x0F12E00B, // 700037EC 
+0x0F12489C, // 700037EE 
+0x0F123020, // 700037F0 
+0x0F128880, // 700037F2 
+0x0F122800, // 700037F4 
+0x0F12D103, // 700037F6 
+0x0F127AA8, // 700037F8 
+0x0F122101, // 700037FA 
+0x0F124308, // 700037FC 
+0x0F1272A8, // 700037FE 
+0x0F122010, // 70003800 
+0x0F12F000, // 70003802 
+0x0F12FA95, // 70003804 
+0x0F128820, // 70003806 
+0x0F122800, // 70003808 
+0x0F12D1E0, // 7000380A 
+0x0F12488A, // 7000380C 
+0x0F1289C0, // 7000380E 
+0x0F122801, // 70003810 
+0x0F12D1DC, // 70003812 
+0x0F127AA8, // 70003814 
+0x0F1221BF, // 70003816 
+0x0F124008, // 70003818 
+0x0F1272A8, // 7000381A 
+0x0F12E718, // 7000381C 
+0x0F126800, // 7000381E 
+0x0F124990, // 70003820 
+0x0F128188, // 70003822 
+0x0F124890, // 70003824 
+0x0F122201, // 70003826 
+0x0F128981, // 70003828 
+0x0F124890, // 7000382A 
+0x0F120252, // 7000382C 
+0x0F124291, // 7000382E 
+0x0F12D902, // 70003830 
+0x0F122102, // 70003832 
+0x0F128181, // 70003834 
+0x0F124770, // 70003836 
+0x0F122101, // 70003838 
+0x0F128181, // 7000383A 
+0x0F124770, // 7000383C 
+0x0F12B5F1, // 7000383E 
+0x0F124E80, // 70003840 
+0x0F128834, // 70003842 
+0x0F122C00, // 70003844 
+0x0F12D03F, // 70003846 
+0x0F122001, // 70003848 
+0x0F122C08, // 7000384A 
+0x0F12D000, // 7000384C 
+0x0F122000, // 7000384E 
+0x0F1270B0, // 70003850 
+0x0F124D7F, // 70003852 
+0x0F122800, // 70003854 
+0x0F12D009, // 70003856 
+0x0F12F000, // 70003858 
+0x0F12FA72, // 7000385A 
+0x0F120028, // 7000385C 
+0x0F1238F0, // 7000385E 
+0x0F126328, // 70003860 
+0x0F127AB0, // 70003862 
+0x0F12217E, // 70003864 
+0x0F124008, // 70003866 
+0x0F1272B0, // 70003868 
+0x0F12E00F, // 7000386A 
+0x0F124F7A, // 7000386C 
+0x0F123780, // 7000386E 
+0x0F128B78, // 70003870 
+0x0F122800, // 70003872 
+0x0F12D005, // 70003874 
+0x0F12F000, // 70003876 
+0x0F12FA6B, // 70003878 
+0x0F122000, // 7000387A 
+0x0F128378, // 7000387C 
+0x0F124976, // 7000387E 
+0x0F128708, // 70003880 
+0x0F122000, // 70003882 
+0x0F12F000, // 70003884 
+0x0F12FA6C, // 70003886 
+0x0F124879, // 70003888 
+0x0F126328, // 7000388A 
+0x0F1278B1, // 7000388C 
+0x0F122700, // 7000388E 
+0x0F120038, // 70003890 
+0x0F122900, // 70003892 
+0x0F12D008, // 70003894 
+0x0F124972, // 70003896 
+0x0F123920, // 70003898 
+0x0F128ACA, // 7000389A 
+0x0F122A00, // 7000389C 
+0x0F12D003, // 7000389E 
+0x0F128B09, // 700038A0 
+0x0F122900, // 700038A2 
+0x0F12D000, // 700038A4 
+0x0F122001, // 700038A6 
+0x0F127170, // 700038A8 
+0x0F122C02, // 700038AA 
+0x0F12D102, // 700038AC 
+0x0F124868, // 700038AE 
+0x0F123860, // 700038B0 
+0x0F126328, // 700038B2 
+0x0F122201, // 700038B4 
+0x0F122C02, // 700038B6 
+0x0F12D000, // 700038B8 
+0x0F122200, // 700038BA 
+0x0F124861, // 700038BC 
+0x0F122110, // 700038BE 
+0x0F12300A, // 700038C0 
+0x0F12F000, // 700038C2 
+0x0F12FA55, // 700038C4 
+0x0F128037, // 700038C6 
+0x0F129900, // 700038C8 
+0x0F120020, // 700038CA 
+0x0F12600C, // 700038CC 
+0x0F12E767, // 700038CE 
+0x0F12B538, // 700038D0 
+0x0F124865, // 700038D2 
+0x0F124669, // 700038D4 
+0x0F123848, // 700038D6 
+0x0F12F000, // 700038D8 
+0x0F12FA52, // 700038DA 
+0x0F124A5E, // 700038DC 
+0x0F124862, // 700038DE 
+0x0F128F51, // 700038E0 
+0x0F122400, // 700038E2 
+0x0F123020, // 700038E4 
+0x0F122900, // 700038E6 
+0x0F12D00A, // 700038E8 
+0x0F128754, // 700038EA 
+0x0F126941, // 700038EC 
+0x0F126451, // 700038EE 
+0x0F126491, // 700038F0 
+0x0F12466B, // 700038F2 
+0x0F128819, // 700038F4 
+0x0F1287D1, // 700038F6 
+0x0F12885B, // 700038F8 
+0x0F120011, // 700038FA 
+0x0F123140, // 700038FC 
+0x0F12800B, // 700038FE 
+0x0F128F91, // 70003900 
+0x0F122900, // 70003902 
+0x0F12D002, // 70003904 
+0x0F128794, // 70003906 
+0x0F126940, // 70003908 
+0x0F126490, // 7000390A 
+0x0F12F000, // 7000390C 
+0x0F12FA40, // 7000390E 
+0x0F12BC38, // 70003910 
+0x0F12BC08, // 70003912 
+0x0F124718, // 70003914 
+0x0F12B5F8, // 70003916 
+0x0F124C56, // 70003918 
+0x0F1289E0, // 7000391A 
+0x0F12F000, // 7000391C 
+0x0F12FA40, // 7000391E 
+0x0F120006, // 70003920 
+0x0F128A20, // 70003922 
+0x0F12F000, // 70003924 
+0x0F12FA44, // 70003926 
+0x0F120007, // 70003928 
+0x0F12484F, // 7000392A 
+0x0F124D4A, // 7000392C 
+0x0F123020, // 7000392E 
+0x0F126CA9, // 70003930 
+0x0F126940, // 70003932 
+0x0F121809, // 70003934 
+0x0F120200, // 70003936 
+0x0F12F000, // 70003938 
+0x0F12FA42, // 7000393A 
+0x0F120400, // 7000393C 
+0x0F120C00, // 7000393E 
+0x0F12002A, // 70003940 
+0x0F12326E, // 70003942 
+0x0F120011, // 70003944 
+0x0F12390A, // 70003946 
+0x0F122305, // 70003948 
+0x0F12F000, // 7000394A 
+0x0F12FA3F, // 7000394C 
+0x0F124C43, // 7000394E 
+0x0F1261A0, // 70003950 
+0x0F128FEB, // 70003952 
+0x0F120002, // 70003954 
+0x0F120031, // 70003956 
+0x0F120018, // 70003958 
+0x0F12F000, // 7000395A 
+0x0F12FA3F, // 7000395C 
+0x0F12466B, // 7000395E 
+0x0F120005, // 70003960 
+0x0F128018, // 70003962 
+0x0F12483C, // 70003964 
+0x0F1269A2, // 70003966 
+0x0F123040, // 70003968 
+0x0F128800, // 7000396A 
+0x0F120039, // 7000396C 
+0x0F12F000, // 7000396E 
+0x0F12FA35, // 70003970 
+0x0F12466B, // 70003972 
+0x0F120006, // 70003974 
+0x0F128058, // 70003976 
+0x0F120021, // 70003978 
+0x0F129800, // 7000397A 
+0x0F12311C, // 7000397C 
+0x0F12F000, // 7000397E 
+0x0F12FA35, // 70003980 
+0x0F124935, // 70003982 
+0x0F123180, // 70003984 
+0x0F12808D, // 70003986 
+0x0F1280CE, // 70003988 
+0x0F128BA1, // 7000398A 
+0x0F124836, // 7000398C 
+0x0F123820, // 7000398E 
+0x0F128001, // 70003990 
+0x0F128BE1, // 70003992 
+0x0F128041, // 70003994 
+0x0F128C21, // 70003996 
+0x0F128081, // 70003998 
+0x0F12E701, // 7000399A 
+0x0F12B5F8, // 7000399C 
+0x0F124E2E, // 7000399E 
+0x0F126C70, // 700039A0 
+0x0F126CB1, // 700039A2 
+0x0F120200, // 700039A4 
+0x0F12F000, // 700039A6 
+0x0F12FA0B, // 700039A8 
+0x0F120400, // 700039AA 
+0x0F120C00, // 700039AC 
+0x0F122401, // 700039AE 
+0x0F120364, // 700039B0 
+0x0F1242A0, // 700039B2 
+0x0F12D200, // 700039B4 
+0x0F120004, // 700039B6 
+0x0F124A27, // 700039B8 
+0x0F120020, // 700039BA 
+0x0F12327E, // 700039BC 
+0x0F121F91, // 700039BE 
+0x0F122303, // 700039C0 
+0x0F12F000, // 700039C2 
+0x0F12FA03, // 700039C4 
+0x0F120405, // 700039C6 
+0x0F120C2D, // 700039C8 
+0x0F124A23, // 700039CA 
+0x0F120020, // 700039CC 
+0x0F12325A, // 700039CE 
+0x0F120011, // 700039D0 
+0x0F12390A, // 700039D2 
+0x0F122305, // 700039D4 
+0x0F12F000, // 700039D6 
+0x0F12F9F9, // 700039D8 
+0x0F12491F, // 700039DA 
+0x0F1264C8, // 700039DC 
+0x0F12491F, // 700039DE 
+0x0F124E21, // 700039E0 
+0x0F1288C8, // 700039E2 
+0x0F122701, // 700039E4 
+0x0F122800, // 700039E6 
+0x0F12D009, // 700039E8 
+0x0F124C23, // 700039EA 
+0x0F1238FF, // 700039EC 
+0x0F121E40, // 700039EE 
+0x0F12D00A, // 700039F0 
+0x0F122804, // 700039F2 
+0x0F12D042, // 700039F4 
+0x0F122806, // 700039F6 
+0x0F12D101, // 700039F8 
+0x0F122000, // 700039FA 
+0x0F1280C8, // 700039FC 
+0x0F1282B7, // 700039FE 
+0x0F122001, // 70003A00 
+0x0F12F000, // 70003A02 
+0x0F12F9FB, // 70003A04 
+0x0F12E6CB, // 70003A06 
+0x0F12000D, // 70003A08 
+0x0F12724F, // 70003A0A 
+0x0F122001, // 70003A0C 
+0x0F12F000, // 70003A0E 
+0x0F12F9FD, // 70003A10 
+0x0F12F000, // 70003A12 
+0x0F12FA03, // 70003A14 
+0x0F124910, // 70003A16 
+0x0F123148, // 70003A18 
+0x0F12C903, // 70003A1A 
+0x0F124348, // 70003A1C 
+0x0F120A00, // 70003A1E 
+0x0F126160, // 70003A20 
+0x0F1220FF, // 70003A22 
+0x0F121D40, // 70003A24 
+0x0F1280E8, // 70003A26 
+0x0F12480C, // 70003A28 
+0x0F123040, // 70003A2A 
+0x0F127707, // 70003A2C 
+0x0F12E7E6, // 70003A2E 
+0x0F123290, // 70003A30 
+0x0F127000, // 70003A32 
+0x0F123294, // 70003A34 
+0x0F127000, // 70003A36 
+0x0F1204A8, // 70003A38 
+0x0F127000, // 70003A3A 
+0x0F1215DC, // 70003A3C 
+0x0F127000, // 70003A3E 
+0x0F125000, // 70003A40 
+0x0F12D000, // 70003A42 
+0x0F121E84, // 70003A44 
+0x0F127000, // 70003A46 
+0x0F121BE4, // 70003A48 
+0x0F127000, // 70003A4A 
+0x0F122EA8, // 70003A4C 
+0x0F127000, // 70003A4E 
+0x0F1221A4, // 70003A50 
+0x0F127000, // 70003A52 
+0x0F120100, // 70003A54 
+0x0F127000, // 70003A56 
+0x0F123F48, // 70003A58 
+0x0F127000, // 70003A5A 
+0x0F1231A0, // 70003A5C 
+0x0F127000, // 70003A5E 
+0x0F1201E8, // 70003A60 
+0x0F127000, // 70003A62 
+0x0F12F2A0, // 70003A64 
+0x0F12D000, // 70003A66 
+0x0F122A44, // 70003A68 
+0x0F127000, // 70003A6A 
+0x0F12F400, // 70003A6C 
+0x0F12D000, // 70003A6E 
+0x0F122024, // 70003A70 
+0x0F127000, // 70003A72 
+0x0F121650, // 70003A74 
+0x0F127000, // 70003A76 
+0x0F122A64, // 70003A78 
+0x0F127000, // 70003A7A 
+0x0F124982, // 70003A7C 
+0x0F12724F, // 70003A7E 
+0x0F1220FF, // 70003A80 
+0x0F121DC0, // 70003A82 
+0x0F1280C8, // 70003A84 
+0x0F12F000, // 70003A86 
+0x0F12F9D1, // 70003A88 
+0x0F124980, // 70003A8A 
+0x0F126ACA, // 70003A8C 
+0x0F12604A, // 70003A8E 
+0x0F122800, // 70003A90 
+0x0F12D006, // 70003A92 
+0x0F12436A, // 70003A94 
+0x0F120001, // 70003A96 
+0x0F120010, // 70003A98 
+0x0F12F000, // 70003A9A 
+0x0F12F991, // 70003A9C 
+0x0F126160, // 70003A9E 
+0x0F12E001, // 70003AA0 
+0x0F12436A, // 70003AA2 
+0x0F126162, // 70003AA4 
+0x0F128BF0, // 70003AA6 
+0x0F122800, // 70003AA8 
+0x0F12D001, // 70003AAA 
+0x0F12F7FF, // 70003AAC 
+0x0F12FF33, // 70003AAE 
+0x0F122000, // 70003AB0 
+0x0F12F000, // 70003AB2 
+0x0F12F9AB, // 70003AB4 
+0x0F124974, // 70003AB6 
+0x0F1220FF, // 70003AB8 
+0x0F121DC0, // 70003ABA 
+0x0F1280C8, // 70003ABC 
+0x0F12E79E, // 70003ABE 
+0x0F12B510, // 70003AC0 
+0x0F12F000, // 70003AC2 
+0x0F12F9BB, // 70003AC4 
+0x0F124870, // 70003AC6 
+0x0F1288C0, // 70003AC8 
+0x0F121FC1, // 70003ACA 
+0x0F1239FD, // 70003ACC 
+0x0F12D103, // 70003ACE 
+0x0F12496F, // 70003AD0 
+0x0F1220FF, // 70003AD2 
+0x0F121C40, // 70003AD4 
+0x0F128048, // 70003AD6 
+0x0F12E605, // 70003AD8 
+0x0F12B5F8, // 70003ADA 
+0x0F122400, // 70003ADC 
+0x0F124D6D, // 70003ADE 
+0x0F12486D, // 70003AE0 
+0x0F12210E, // 70003AE2 
+0x0F128041, // 70003AE4 
+0x0F122101, // 70003AE6 
+0x0F128001, // 70003AE8 
+0x0F12F000, // 70003AEA 
+0x0F12F9AF, // 70003AEC 
+0x0F12486B, // 70003AEE 
+0x0F128840, // 70003AF0 
+0x0F12F000, // 70003AF2 
+0x0F12F9B3, // 70003AF4 
+0x0F124E6A, // 70003AF6 
+0x0F12270D, // 70003AF8 
+0x0F12073F, // 70003AFA 
+0x0F1219E8, // 70003AFC 
+0x0F128803, // 70003AFE 
+0x0F1200E2, // 70003B00 
+0x0F121991, // 70003B02 
+0x0F12804B, // 70003B04 
+0x0F128843, // 70003B06 
+0x0F1252B3, // 70003B08 
+0x0F128882, // 70003B0A 
+0x0F1280CA, // 70003B0C 
+0x0F1288C0, // 70003B0E 
+0x0F128088, // 70003B10 
+0x0F123508, // 70003B12 
+0x0F12042D, // 70003B14 
+0x0F120C2D, // 70003B16 
+0x0F121C64, // 70003B18 
+0x0F120424, // 70003B1A 
+0x0F120C24, // 70003B1C 
+0x0F122C07, // 70003B1E 
+0x0F12D3EC, // 70003B20 
+0x0F12E63D, // 70003B22 
+0x0F12B5F0, // 70003B24 
+0x0F12B085, // 70003B26 
+0x0F126801, // 70003B28 
+0x0F129103, // 70003B2A 
+0x0F126881, // 70003B2C 
+0x0F12040A, // 70003B2E 
+0x0F120C12, // 70003B30 
+0x0F12495C, // 70003B32 
+0x0F128B89, // 70003B34 
+0x0F122900, // 70003B36 
+0x0F12D001, // 70003B38 
+0x0F120011, // 70003B3A 
+0x0F12E000, // 70003B3C 
+0x0F122100, // 70003B3E 
+0x0F129102, // 70003B40 
+0x0F126840, // 70003B42 
+0x0F120401, // 70003B44 
+0x0F129803, // 70003B46 
+0x0F120C09, // 70003B48 
+0x0F12F000, // 70003B4A 
+0x0F12F98F, // 70003B4C 
+0x0F124854, // 70003B4E 
+0x0F123080, // 70003B50 
+0x0F128900, // 70003B52 
+0x0F122800, // 70003B54 
+0x0F12D039, // 70003B56 
+0x0F122100, // 70003B58 
+0x0F124854, // 70003B5A 
+0x0F124D52, // 70003B5C 
+0x0F124684, // 70003B5E 
+0x0F124B53, // 70003B60 
+0x0F124C4F, // 70003B62 
+0x0F1288DA, // 70003B64 
+0x0F120048, // 70003B66 
+0x0F1200D7, // 70003B68 
+0x0F12193E, // 70003B6A 
+0x0F12197F, // 70003B6C 
+0x0F12183F, // 70003B6E 
+0x0F125A36, // 70003B70 
+0x0F128AFF, // 70003B72 
+0x0F12437E, // 70003B74 
+0x0F1200B6, // 70003B76 
+0x0F120C37, // 70003B78 
+0x0F121906, // 70003B7A 
+0x0F123680, // 70003B7C 
+0x0F128177, // 70003B7E 
+0x0F121C52, // 70003B80 
+0x0F1200D2, // 70003B82 
+0x0F121914, // 70003B84 
+0x0F121952, // 70003B86 
+0x0F121812, // 70003B88 
+0x0F125A24, // 70003B8A 
+0x0F128AD2, // 70003B8C 
+0x0F124354, // 70003B8E 
+0x0F1200A2, // 70003B90 
+0x0F120C12, // 70003B92 
+0x0F128272, // 70003B94 
+0x0F12891C, // 70003B96 
+0x0F12895B, // 70003B98 
+0x0F124367, // 70003B9A 
+0x0F12435A, // 70003B9C 
+0x0F121943, // 70003B9E 
+0x0F123340, // 70003BA0 
+0x0F1289DB, // 70003BA2 
+0x0F129C02, // 70003BA4 
+0x0F1218BA, // 70003BA6 
+0x0F124363, // 70003BA8 
+0x0F1218D2, // 70003BAA 
+0x0F120212, // 70003BAC 
+0x0F120C12, // 70003BAE 
+0x0F12466B, // 70003BB0 
+0x0F12521A, // 70003BB2 
+0x0F124663, // 70003BB4 
+0x0F127DDB, // 70003BB6 
+0x0F12435A, // 70003BB8 
+0x0F129B03, // 70003BBA 
+0x0F120252, // 70003BBC 
+0x0F120C12, // 70003BBE 
+0x0F12521A, // 70003BC0 
+0x0F121C49, // 70003BC2 
+0x0F120409, // 70003BC4 
+0x0F120C09, // 70003BC6 
+0x0F122904, // 70003BC8 
+0x0F12D3C9, // 70003BCA 
+0x0F12B005, // 70003BCC 
+0x0F12BCF0, // 70003BCE 
+0x0F12BC08, // 70003BD0 
+0x0F124718, // 70003BD2 
+0x0F12B510, // 70003BD4 
+0x0F12F7FF, // 70003BD6 
+0x0F12FF80, // 70003BD8 
+0x0F12F000, // 70003BDA 
+0x0F12F94F, // 70003BDC 
+0x0F12E582, // 70003BDE 
+0x0F12B570, // 70003BE0 
+0x0F126804, // 70003BE2 
+0x0F12F000, // 70003BE4 
+0x0F12F952, // 70003BE6 
+0x0F124D32, // 70003BE8 
+0x0F128C29, // 70003BEA 
+0x0F121A40, // 70003BEC 
+0x0F1242A0, // 70003BEE 
+0x0F12D901, // 70003BF0 
+0x0F120020, // 70003BF2 
+0x0F12E003, // 70003BF4 
+0x0F12F000, // 70003BF6 
+0x0F12F949, // 70003BF8 
+0x0F128C29, // 70003BFA 
+0x0F121A40, // 70003BFC 
+0x0F126268, // 70003BFE 
+0x0F12F000, // 70003C00 
+0x0F12F94C, // 70003C02 
+0x0F1262A8, // 70003C04 
+0x0F12F000, // 70003C06 
+0x0F12F951, // 70003C08 
+0x0F126328, // 70003C0A 
+0x0F128869, // 70003C0C 
+0x0F122900, // 70003C0E 
+0x0F12D000, // 70003C10 
+0x0F1262A8, // 70003C12 
+0x0F124828, // 70003C14 
+0x0F126B00, // 70003C16 
+0x0F128C00, // 70003C18 
+0x0F122800, // 70003C1A 
+0x0F12D11B, // 70003C1C 
+0x0F126AA8, // 70003C1E 
+0x0F12F000, // 70003C20 
+0x0F12F94C, // 70003C22 
+0x0F1261E8, // 70003C24 
+0x0F124A1E, // 70003C26 
+0x0F123280, // 70003C28 
+0x0F128B91, // 70003C2A 
+0x0F122900, // 70003C2C 
+0x0F12D00B, // 70003C2E 
+0x0F120011, // 70003C30 
+0x0F123120, // 70003C32 
+0x0F128809, // 70003C34 
+0x0F124288, // 70003C36 
+0x0F12D907, // 70003C38 
+0x0F1261E9, // 70003C3A 
+0x0F128C28, // 70003C3C 
+0x0F121A08, // 70003C3E 
+0x0F1262A8, // 70003C40 
+0x0F12F000, // 70003C42 
+0x0F12F92B, // 70003C44 
+0x0F1262A8, // 70003C46 
+0x0F12E502, // 70003C48 
+0x0F128BD1, // 70003C4A 
+0x0F124288, // 70003C4C 
+0x0F12D800, // 70003C4E 
+0x0F120008, // 70003C50 
+0x0F1261E8, // 70003C52 
+0x0F12E4FC, // 70003C54 
+0x0F12F000, // 70003C56 
+0x0F12F919, // 70003C58 
+0x0F1261E8, // 70003C5A 
+0x0F12E4F8, // 70003C5C 
+0x0F12B510, // 70003C5E 
+0x0F12F000, // 70003C60 
+0x0F12F934, // 70003C62 
+0x0F12480E, // 70003C64 
+0x0F1230A0, // 70003C66 
+0x0F128841, // 70003C68 
+0x0F122900, // 70003C6A 
+0x0F12D007, // 70003C6C 
+0x0F124A07, // 70003C6E 
+0x0F123280, // 70003C70 
+0x0F126953, // 70003C72 
+0x0F124A11, // 70003C74 
+0x0F12428B, // 70003C76 
+0x0F12D202, // 70003C78 
+0x0F128880, // 70003C7A 
+0x0F1281D0, // 70003C7C 
+0x0F12E532, // 70003C7E 
+0x0F1288C0, // 70003C80 
+0x0F1281D0, // 70003C82 
+0x0F12E52F, // 70003C84 
+0x0F120000, // 70003C86 
+0x0F1231A0, // 70003C88 
+0x0F127000, // 70003C8A 
+0x0F1229E4, // 70003C8C 
+0x0F127000, // 70003C8E 
+0x0F12C100, // 70003C90 
+0x0F12D000, // 70003C92 
+0x0F12A006, // 70003C94 
+0x0F120000, // 70003C96 
+0x0F12A000, // 70003C98 
+0x0F12D000, // 70003C9A 
+0x0F12064C, // 70003C9C 
+0x0F127000, // 70003C9E 
+0x0F123F48, // 70003CA0 
+0x0F127000, // 70003CA2 
+0x0F1207C4, // 70003CA4 
+0x0F127000, // 70003CA6 
+0x0F1207E8, // 70003CA8 
+0x0F127000, // 70003CAA 
+0x0F122B24, // 70003CAC 
+0x0F127000, // 70003CAE 
+0x0F121FA0, // 70003CB0 
+0x0F127000, // 70003CB2 
+0x0F121E3C, // 70003CB4 
+0x0F127000, // 70003CB6 
+0x0F1221A4, // 70003CB8 
+0x0F127000, // 70003CBA 
+0x0F12E200, // 70003CBC 
+0x0F12D000, // 70003CBE 
+0x0F124778, // 70003CC0 
+0x0F1246C0, // 70003CC2 
+0x0F12C000, // 70003CC4 
+0x0F12E59F, // 70003CC6 
+0x0F12FF1C, // 70003CC8 
+0x0F12E12F, // 70003CCA 
+0x0F121F63, // 70003CCC 
+0x0F120001, // 70003CCE 
+0x0F124778, // 70003CD0 
+0x0F1246C0, // 70003CD2 
+0x0F12C000, // 70003CD4 
+0x0F12E59F, // 70003CD6 
+0x0F12FF1C, // 70003CD8 
+0x0F12E12F, // 70003CDA 
+0x0F121EDF, // 70003CDC 
+0x0F120001, // 70003CDE 
+0x0F124778, // 70003CE0 
+0x0F1246C0, // 70003CE2 
+0x0F12C000, // 70003CE4 
+0x0F12E59F, // 70003CE6 
+0x0F12FF1C, // 70003CE8 
+0x0F12E12F, // 70003CEA 
+0x0F12495F, // 70003CEC 
+0x0F120000, // 70003CEE 
+0x0F124778, // 70003CF0 
+0x0F1246C0, // 70003CF2 
+0x0F12C000, // 70003CF4 
+0x0F12E59F, // 70003CF6 
+0x0F12FF1C, // 70003CF8 
+0x0F12E12F, // 70003CFA 
+0x0F12E403, // 70003CFC 
+0x0F120000, // 70003CFE 
+0x0F124778, // 70003D00 
+0x0F1246C0, // 70003D02 
+0x0F12C000, // 70003D04 
+0x0F12E59F, // 70003D06 
+0x0F12FF1C, // 70003D08 
+0x0F12E12F, // 70003D0A 
+0x0F1224B3, // 70003D0C 
+0x0F120001, // 70003D0E 
+0x0F124778, // 70003D10 
+0x0F1246C0, // 70003D12 
+0x0F12C000, // 70003D14 
+0x0F12E59F, // 70003D16 
+0x0F12FF1C, // 70003D18 
+0x0F12E12F, // 70003D1A 
+0x0F12EECD, // 70003D1C 
+0x0F120000, // 70003D1E 
+0x0F124778, // 70003D20 
+0x0F1246C0, // 70003D22 
+0x0F12C000, // 70003D24 
+0x0F12E59F, // 70003D26 
+0x0F12FF1C, // 70003D28 
+0x0F12E12F, // 70003D2A 
+0x0F12F049, // 70003D2C 
+0x0F120000, // 70003D2E 
+0x0F124778, // 70003D30 
+0x0F1246C0, // 70003D32 
+0x0F12C000, // 70003D34 
+0x0F12E59F, // 70003D36 
+0x0F12FF1C, // 70003D38 
+0x0F12E12F, // 70003D3A 
+0x0F1212DF, // 70003D3C 
+0x0F120000, // 70003D3E 
+0x0F124778, // 70003D40 
+0x0F1246C0, // 70003D42 
+0x0F12C000, // 70003D44 
+0x0F12E59F, // 70003D46 
+0x0F12FF1C, // 70003D48 
+0x0F12E12F, // 70003D4A 
+0x0F12F05B, // 70003D4C 
+0x0F120000, // 70003D4E 
+0x0F124778, // 70003D50 
+0x0F1246C0, // 70003D52 
+0x0F12C000, // 70003D54 
+0x0F12E59F, // 70003D56 
+0x0F12FF1C, // 70003D58 
+0x0F12E12F, // 70003D5A 
+0x0F12F07B, // 70003D5C 
+0x0F120000, // 70003D5E 
+0x0F124778, // 70003D60 
+0x0F1246C0, // 70003D62 
+0x0F12C000, // 70003D64 
+0x0F12E59F, // 70003D66 
+0x0F12FF1C, // 70003D68 
+0x0F12E12F, // 70003D6A 
+0x0F12FE6D, // 70003D6C 
+0x0F120000, // 70003D6E 
+0x0F124778, // 70003D70 
+0x0F1246C0, // 70003D72 
+0x0F12C000, // 70003D74 
+0x0F12E59F, // 70003D76 
+0x0F12FF1C, // 70003D78 
+0x0F12E12F, // 70003D7A 
+0x0F123295, // 70003D7C 
+0x0F120000, // 70003D7E 
+0x0F124778, // 70003D80 
+0x0F1246C0, // 70003D82 
+0x0F12C000, // 70003D84 
+0x0F12E59F, // 70003D86 
+0x0F12FF1C, // 70003D88 
+0x0F12E12F, // 70003D8A 
+0x0F12234F, // 70003D8C 
+0x0F120000, // 70003D8E 
+0x0F124778, // 70003D90 
+0x0F1246C0, // 70003D92 
+0x0F12C000, // 70003D94 
+0x0F12E59F, // 70003D96 
+0x0F12FF1C, // 70003D98 
+0x0F12E12F, // 70003D9A 
+0x0F124521, // 70003D9C 
+0x0F120000, // 70003D9E 
+0x0F124778, // 70003DA0 
+0x0F1246C0, // 70003DA2 
+0x0F12C000, // 70003DA4 
+0x0F12E59F, // 70003DA6 
+0x0F12FF1C, // 70003DA8 
+0x0F12E12F, // 70003DAA 
+0x0F127C0D, // 70003DAC 
+0x0F120000, // 70003DAE 
+0x0F124778, // 70003DB0 
+0x0F1246C0, // 70003DB2 
+0x0F12C000, // 70003DB4 
+0x0F12E59F, // 70003DB6 
+0x0F12FF1C, // 70003DB8 
+0x0F12E12F, // 70003DBA 
+0x0F127C2B, // 70003DBC 
+0x0F120000, // 70003DBE 
+0x0F124778, // 70003DC0 
+0x0F1246C0, // 70003DC2 
+0x0F12F004, // 70003DC4 
+0x0F12E51F, // 70003DC6 
+0x0F1224C4, // 70003DC8 
+0x0F120001, // 70003DCA 
+0x0F124778, // 70003DCC 
+0x0F1246C0, // 70003DCE 
+0x0F12C000, // 70003DD0 
+0x0F12E59F, // 70003DD2 
+0x0F12FF1C, // 70003DD4 
+0x0F12E12F, // 70003DD6 
+0x0F123183, // 70003DD8 
+0x0F120000, // 70003DDA 
+0x0F124778, // 70003DDC 
+0x0F1246C0, // 70003DDE 
+0x0F12C000, // 70003DE0 
+0x0F12E59F, // 70003DE2 
+0x0F12FF1C, // 70003DE4 
+0x0F12E12F, // 70003DE6 
+0x0F12302F, // 70003DE8 
+0x0F120000, // 70003DEA 
+0x0F124778, // 70003DEC 
+0x0F1246C0, // 70003DEE 
+0x0F12C000, // 70003DF0 
+0x0F12E59F, // 70003DF2 
+0x0F12FF1C, // 70003DF4 
+0x0F12E12F, // 70003DF6 
+0x0F12EF07, // 70003DF8 
+0x0F120000, // 70003DFA 
+0x0F124778, // 70003DFC 
+0x0F1246C0, // 70003DFE 
+0x0F12C000, // 70003E00 
+0x0F12E59F, // 70003E02 
+0x0F12FF1C, // 70003E04 
+0x0F12E12F, // 70003E06 
+0x0F1248FB, // 70003E08 
+0x0F120000, // 70003E0A 
+0x0F124778, // 70003E0C 
+0x0F1246C0, // 70003E0E 
+0x0F12C000, // 70003E10 
+0x0F12E59F, // 70003E12 
+0x0F12FF1C, // 70003E14 
+0x0F12E12F, // 70003E16 
+0x0F12F0B1, // 70003E18 
+0x0F120000, // 70003E1A 
+0x0F124778, // 70003E1C 
+0x0F1246C0, // 70003E1E 
+0x0F12C000, // 70003E20 
+0x0F12E59F, // 70003E22 
+0x0F12FF1C, // 70003E24 
+0x0F12E12F, // 70003E26 
+0x0F12EEDF, // 70003E28 
+0x0F120000, // 70003E2A 
+0x0F124778, // 70003E2C 
+0x0F1246C0, // 70003E2E 
+0x0F12C000, // 70003E30 
+0x0F12E59F, // 70003E32 
+0x0F12FF1C, // 70003E34 
+0x0F12E12F, // 70003E36 
+0x0F12AEF1, // 70003E38 
+0x0F120000, // 70003E3A 
+0x0F124778, // 70003E3C 
+0x0F1246C0, // 70003E3E 
+0x0F12C000, // 70003E40 
+0x0F12E59F, // 70003E42 
+0x0F12FF1C, // 70003E44 
+0x0F12E12F, // 70003E46 
+0x0F1202EB, // 70003E48 
+0x0F120001, // 70003E4A 
+0x0F124778, // 70003E4C 
+0x0F1246C0, // 70003E4E 
+0x0F12C000, // 70003E50 
+0x0F12E59F, // 70003E52 
+0x0F12FF1C, // 70003E54 
+0x0F12E12F, // 70003E56 
+0x0F12FD21, // 70003E58 
+0x0F120000, // 70003E5A 
+0x0F124778, // 70003E5C 
+0x0F1246C0, // 70003E5E 
+0x0F12C000, // 70003E60 
+0x0F12E59F, // 70003E62 
+0x0F12FF1C, // 70003E64 
+0x0F12E12F, // 70003E66 
+0x0F12FDAF, // 70003E68 
+0x0F120000, // 70003E6A 
+0x0F124778, // 70003E6C 
+0x0F1246C0, // 70003E6E 
+0x0F12C000, // 70003E70 
+0x0F12E59F, // 70003E72 
+0x0F12FF1C, // 70003E74 
+0x0F12E12F, // 70003E76 
+0x0F125027, // 70003E78 
+0x0F120000, // 70003E7A 
+0x0F124778, // 70003E7C 
+0x0F1246C0, // 70003E7E 
+0x0F12C000, // 70003E80 
+0x0F12E59F, // 70003E82 
+0x0F12FF1C, // 70003E84 
+0x0F12E12F, // 70003E86 
+0x0F1204C9, // 70003E88 
+0x0F120000, // 70003E8A 
+0x0F124778, // 70003E8C 
+0x0F1246C0, // 70003E8E 
+0x0F12C000, // 70003E90 
+0x0F12E59F, // 70003E92 
+0x0F12FF1C, // 70003E94 
+0x0F12E12F, // 70003E96 
+0x0F1239DF, // 70003E98 
+0x0F120000, // 70003E9A 
+0x0F124778, // 70003E9C 
+0x0F1246C0, // 70003E9E 
+0x0F12C000, // 70003EA0 
+0x0F12E59F, // 70003EA2 
+0x0F12FF1C, // 70003EA4 
+0x0F12E12F, // 70003EA6 
+0x0F126177, // 70003EA8 
+0x0F120000, // 70003EAA 
+0x0F124778, // 70003EAC 
+0x0F1246C0, // 70003EAE 
+0x0F12C000, // 70003EB0 
+0x0F12E59F, // 70003EB2 
+0x0F12FF1C, // 70003EB4 
+0x0F12E12F, // 70003EB6 
+0x0F12424F, // 70003EB8 
+0x0F120000, // 70003EBA 
+0x0F124778, // 70003EBC 
+0x0F1246C0, // 70003EBE 
+0x0F12C000, // 70003EC0 
+0x0F12E59F, // 70003EC2 
+0x0F12FF1C, // 70003EC4 
+0x0F12E12F, // 70003EC6 
+0x0F123F0D, // 70003EC8 
+0x0F120000, // 70003ECA 
+0x0F124778, // 70003ECC 
+0x0F1246C0, // 70003ECE 
+0x0F12C000, // 70003ED0 
+0x0F12E59F, // 70003ED2 
+0x0F12FF1C, // 70003ED4 
+0x0F12E12F, // 70003ED6 
+0x0F1202B9, // 70003ED8 
+0x0F120001, // 70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007, // clks_src_gf_force_enable
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120000, // on/off AFIT by NB option
+
+0x0F120005, // NormBR[0]
+0x0F120019, // NormBR[1]
+0x0F120050, // NormBR[2]
+0x0F120300, // NormBR[3]
+0x0F120375, // NormBR[4]
+
+// Flash
+0x002A3F82,
+0x0F120000,	// TNP_Regs_PreflashStart
+0x0F120000,	// TNP_Regs_PreflashEnd
+0x0F120260,	// TNP_Regs_PreWP_r
+0x0F120240, // TNP_Regs_PreWP_b
+
+0x002A3F98,	// BR Tuning
+0x0F120100,	// TNP_Regs_BrRatioIn_0_
+0x0F120150,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120100,	// TNP_Regs_BrRatioOut_0_
+0x0F1200A0,
+0x0F120080,
+0x0F120040,
+0x0F120020,
+
+0x0F120030,	// WP Tuning
+0x0F120040,	// TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	// T_BR tune	
+0x0F120150,	// TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F120048, //3C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B, //3B,
+0x0F12002E, //2E,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,		
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120235, //0244 0258 AWB R point          //0258 0245 0258
+0x0F12024A, //024D 0220 AWB B point          //0220 0245 0245
+
+
+//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //         
+//         ///
+// Analog & APS settings         //         //         //         //         /  ///
+// This register is for FACTORY ONLY. If you change it without prior notificat
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future         
+//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //         
+//         ///
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, // adc_sat[7:0]=84d (500mV)
+0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, // rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, // pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, // clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+0x002AF42E,
+0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+0x002AF434,
+0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, // reg_tune_pix[7:0]
+0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, // reg_tune_rg[7:0] (2.83V)
+0x0F120004, // reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, // blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, // srx_en[0]
+
+0x002A0054,
+0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, // div_dbr[7:4]
+
+0x002AF132,
+0x0F120206, // tgr_frame_decription 4
+0x002AF152,
+0x0F120206, // tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, // tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, // tgr_frame_params_descriptor_6
+//===========================================================================================
+
+//============================= Line-ADLC Tuning ============================================
+0x002AE412,
+0x0F120008, // adlc_tune_offset_gr[7:0]
+0x0F120008, // adlc_tune_offset_r[7:0]
+0x0F120010, // adlc_tune_offset_b[7:0]
+0x0F120010, // adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, // adlc_qec[2:0]
+//===========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F120132, //0138//awbb_IntcR
+0x0F12010A, //011C//awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041, //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C, //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+0x0F120190, //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000 //#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120003, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120602, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120003, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200CC, //#af_search_usPeakThr  for 80%
+0x0F1200A0,          //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F12952F, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120010, //#af_pos_usTableLastInd 10h + 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120033, //#af_pos_usTable_1_  51   
+0x0F120036, //#af_pos_usTable_2_  54	
+0x0F120039, //#af_pos_usTable_3_  57	
+0x0F12003D, //#af_pos_usTable_4_  61   
+0x0F120041, //#af_pos_usTable_5_  65	
+0x0F120045, //#af_pos_usTable_6_  69	
+0x0F120049, //#af_pos_usTable_7_  73	
+0x0F12004E, //#af_pos_usTable_8_  78	
+0x0F120053, //#af_pos_usTable_9_  83	
+0x0F120059, //#af_pos_usTable_10_ 89	
+0x0F120060, //#af_pos_usTable_11_ 104	
+0x0F120068, //#af_pos_usTable_12_ 109	
+0x0F120072, //#af_pos_usTable_13_ 114	
+0x0F12007D, //#af_pos_usTable_14_ 125
+0x0F120089, //#af_pos_usTable_15_ 137	
+0x0F120096, //#af_pos_usTable_16_ 150
+
+//8. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120020, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120008, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120008, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12005C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000, //senHal_bSRX //SRX off
+
+0x002A1680,
+0x0F120002, //senHal_NExpLinesCheckFine//0004//extend Forbidden area line
+
+0x002A0ED2,
+0x0F120FA0,	//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK   
+0x002A0188,
+0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+//SCLK & PCLK                    // clock set 0
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+//SCLK & PCLK                    // clock set 1
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 2                               
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz          
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz  
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz  
+
+0x002A1B78,
+0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A,     //p10
+
+
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6,
+0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 640 480 system 52M PCLK 87M
+//===================================================================
+0x002A023E,
+0x0F120400, //REG_0TC_PCFG_usWidth
+0x0F120300, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+#if 1 /* fix 180 rotation to 0*/
+0x0F120000, //REG_0TC_PCFG_uPrevMirror
+0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 87M
+//===================================================================
+
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+            
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+0x0F1254F6, //REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6, //REG_0TC_CCFG_usMinOut4KHzRate
+            
+0x002A033E, 
+0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+            
+0x002A0346, 
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+            
+0x002A0426, 
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+            
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+//===================================================================
+// Capture 1 640x480 system 52M PCLK 87M
+//===================================================================
+0x002A035A,
+0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+0x0F120280,                   //REG_1TC_CCFG_usWidth
+0x0F1201E0,                   //REG_1TC_CCFG_usHeight
+0x0F120005,                   //REG_1TC_CCFG_Format                           
+0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+0x002A036A,
+0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29 
+0x0F120010,                   //REG_1TC_CCFG_OIFMask
+0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+0x002A0372,
+0x0F120001,                   //REG_1TC_CCFG_uClockInd
+0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+0x0F120000,                   //REG_1TC_CCFG_sSaturation
+0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,  //0D22
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120000,  //000F
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F0F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F00
+0x0F12000F,  //0000
+0x0F12000F,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F0F,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120000,  //0000
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F0F
+0x0F12000F,  //0F00
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0000
+0x0F120F0F,  //000F
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F12000F,  //0000
+0x0F120000,  //000F
+0x0F12000F,  //000F
+0x0F120F0F,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F12000F,  //0F0F
+0x0F120F00,  //0000
+0x0F120F0F,  //0F0F
+0x0F12000F,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F12000F,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F0F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //0000
+0x0F120F0F,  //0F0F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120000,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F0F
+
+// TVAR_ash_pGAS_low
+0x0F1273AF,  //6E49
+0x0F12FF14,  //FB98
+0x0F12F1C4,  //F348
+0x0F1213DB,  //1BD6
+0x0F12034D,  //EBEF
+0x0F12EBBF,  //03D3
+0x0F12EB8A,  //EC8D
+0x0F12E1CD,  //F239
+0x0F122A09,  //0E64
+0x0F12DC91,  //F7EA
+0x0F12003B,  //FD3B
+0x0F121D67,  //0A7C
+0x0F12FCC8,  //FC9C
+0x0F121F53,  //0BD3
+0x0F12D360,  //F2E5
+0x0F122866,  //0619
+0x0F120453,  //0772
+0x0F12D38A,  //F0B0
+0x0F121340,  //184E
+0x0F12ED61,  //F95F
+0x0F12155A,  //0B1A
+0x0F12ECED,  //FC45
+0x0F12F641,  //F716
+0x0F122915,  //0DCD
+0x0F12FCA8,  //EF24
+0x0F12FDD5,  //0221
+0x0F120ED6,  //F6BD
+0x0F12F760,  //04CB
+0x0F12F975,  //00B1
+0x0F12FF26,  //FEB0
+0x0F12F704,  //0268
+0x0F120CE5,  //02C7
+0x0F12E58E,  //010A
+0x0F120DE5,  //FF93
+0x0F12170C,  //036D
+0x0F12E129,  //F859
+0x0F1289CF,  //81D0
+0x0F12FE3A,  //FA32
+0x0F12EDFB,  //EFDB
+0x0F121B1D,  //234D
+0x0F12FECB,  //E799
+0x0F12EBC2,  //0337
+0x0F12EC58,  //EB05
+0x0F12D642,  //E8F9
+0x0F1231C1,  //152E
+0x0F12D679,  //F0D5
+0x0F120E40,  //0842
+0x0F1210E6,  //043A
+0x0F12EC1D,  //F461
+0x0F122340,  //0E58
+0x0F12D764,  //F658
+0x0F122280,  //075D
+0x0F12F8D3,  //F78D
+0x0F12E5E2,  //FDE9
+0x0F123192,  //277A
+0x0F12F07C,  //FFDE
+0x0F120ED8,  //FD3B
+0x0F12F24C,  //FE50
+0x0F12FF63,  //0AD1
+0x0F1219AD,  //FE2C
+0x0F12E53A,  //E90D
+0x0F12FB55,  //F7B0
+0x0F1207AB,  //05DB
+0x0F12FF19,  //02CD
+0x0F12FC9D,  //F4F1
+0x0F12F7D2,  //02A8
+0x0F12FD6A,  //FDDC
+0x0F120D9D,  //0B59
+0x0F12F1AD,  //F74E
+0x0F12053D,  //03D5
+0x0F120669,  //FF4F
+0x0F12F887,  //00F7
+0x0F126F7B,  //6A44
+0x0F12FD92,  //FAD6
+0x0F12F87B,  //F261
+0x0F12054F,  //1F28
+0x0F121596,  //E691
+0x0F12E0A2,  //07D2
+0x0F12E9FC,  //EE85
+0x0F12E400,  //F426
+0x0F12279D,  //0F26
+0x0F12DEB1,  //F34B
+0x0F12FF95,  //0036
+0x0F121B50,  //0C0F
+0x0F120845,  //FDA9
+0x0F121B29,  //09EA
+0x0F12D7C2,  //F27A
+0x0F12289C,  //0CD5
+0x0F12FC02,  //01E1
+0x0F12DD73,  //ED41
+0x0F12084B,  //1DB5
+0x0F12EF8B,  //FD26
+0x0F120D89,  //03F7
+0x0F12EDD3,  //F7BB
+0x0F12FE1A,  //FE81
+0x0F122286,  //12D3
+0x0F12FC16,  //E061
+0x0F1202C7,  //F81C
+0x0F120F6E,  //07B1
+0x0F12FB29,  //0408
+0x0F12FCA0,  //F860
+0x0F12F19E,  //FC9A
+0x0F12FD3E,  //0DDE
+0x0F1202EF,  //0C9C
+0x0F12F154,  //F2A4
+0x0F120033,  //02EB
+0x0F121408,  //099B
+0x0F12F445,  //F5A6
+0x0F1275D7,  //7243
+0x0F12FAC3,  //F74D
+0x0F12F7F5,  //F74B
+0x0F120C29,  //1800
+0x0F120AC4,  //EF22
+0x0F12E7C3,  //0263
+0x0F12EBE4,  //EBE7
+0x0F12E43C,  //F5A4
+0x0F12260D,  //09D3
+0x0F12E05B,  //FAB8
+0x0F12FE64,  //FDFF
+0x0F121DAD,  //086B
+0x0F12FFFD,  //0338
+0x0F121AE5,  //0514
+0x0F12D7B3,  //F840
+0x0F122652,  //0768
+0x0F1203DD,  //FE55
+0x0F12D39B,  //F884
+0x0F121769,  //1488
+0x0F12EFEF,  //FFCD
+0x0F120F31,  //035B
+0x0F12ED25,  //FA4E
+0x0F12F920,  //01DB
+0x0F122A81,  //06D6
+0x0F12EFF9,  //EE19
+0x0F12FE2A,  //FEA3
+0x0F121531,  //FE8C
+0x0F12F886,  //03A3
+0x0F12F846,  //FDDB
+0x0F12F794,  //FD9B
+0x0F12000B,  //035E
+0x0F120CA4,  //03F2
+0x0F12E144,  //FCBD
+0x0F120E4E,  //0300
+0x0F121379,  //FF2E
+0x0F12EBB5,  //FE03
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F124000,	//3F00//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[0][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[0][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[0][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[0][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[0][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[0][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[0][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[0][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[0][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[0][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[0][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[0][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[0][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[0][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[0][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[0][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[0][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[0][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[0][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[0][19]
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[1][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[1][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[1][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[1][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[1][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[1][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[1][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[1][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[1][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[1][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[1][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[1][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[1][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[1][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[1][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[1][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[1][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[1][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[1][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[1][19]
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[2][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[2][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[2][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[2][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[2][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[2][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[2][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[2][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[2][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[2][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[2][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[2][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[2][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[2][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[2][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[2][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[2][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[2][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[2][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[2][19]
+
+//s002A06D8
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR//MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+//AE_state
+0x002A04EE,
+0x0F12010E, //#lt_uLimitHigh
+0x0F1200F5, //#lt_uLimitLow
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //#lt_uMaxExp1
+0x002A0508,
+0x0F12681F, //#lt_uMaxExp2
+0x002A050C,
+0x0F128227, //#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F12681F, //#lt_uCapMaxExp2
+0x002A051C,
+0x0F128227, //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F120200, //1E0 //#lt_uMaxAnGain1
+0x0F120200, //1E0 //#lt_uMaxAnGain2
+0x0F120300, //#lt_uMaxAnGain3
+0x0F120840, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //1E0 #lt_uCapMaxAnGain1
+0x0F120200, //1E0 #lt_uCapMaxAnGain2
+0x0F120300, //#lt_uCapMaxAnGain3
+0x0F120710, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,
+0x0F120000, //ae_WeightTbl_16[0]
+0x0F120000, //ae_WeightTbl_16[1]
+0x0F120000, //ae_WeightTbl_16[2]
+0x0F120000, //ae_WeightTbl_16[3]
+0x0F120101, //ae_WeightTbl_16[4]
+0x0F120101, //ae_WeightTbl_16[5]
+0x0F120101, //ae_WeightTbl_16[6]
+0x0F120101, //ae_WeightTbl_16[7]
+0x0F120101, //ae_WeightTbl_16[8]
+0x0F120201, //ae_WeightTbl_16[9]
+0x0F120102, //ae_WeightTbl_16[10]
+0x0F120101, //ae_WeightTbl_16[11]
+0x0F120101, //ae_WeightTbl_16[12]
+0x0F120202, //ae_WeightTbl_16[13]
+0x0F120202, //ae_WeightTbl_16[14]
+0x0F120101, //ae_WeightTbl_16[15]
+0x0F120101, //ae_WeightTbl_16[16]
+0x0F120202, //ae_WeightTbl_16[17]
+0x0F120202, //ae_WeightTbl_16[18]
+0x0F120101, //ae_WeightTbl_16[19]
+0x0F120201, //ae_WeightTbl_16[20]
+0x0F120202, //ae_WeightTbl_16[21]
+0x0F120202, //ae_WeightTbl_16[22]
+0x0F120102, //ae_WeightTbl_16[23]
+0x0F120201, //ae_WeightTbl_16[24]
+0x0F120202, //ae_WeightTbl_16[25]
+0x0F120202, //ae_WeightTbl_16[26]
+0x0F120102, //ae_WeightTbl_16[27]
+0x0F120101, //ae_WeightTbl_16[28]
+0x0F120101, //ae_WeightTbl_16[29]
+0x0F120101, //ae_WeightTbl_16[30]
+0x0F120101, //ae_WeightTbl_16[31]
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F1205F0, //awbb_GamutWidthThr1
+0x0F1201F4, //awbb_GamutHeightThr1
+0x0F12006C, //awbb_GamutWidthThr2
+0x0F120038, //awbb_GamutHeightThr2
+0x002A1020,
+0x0F12000C, //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A291A,
+0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+0x0F120008,	//001E	//awbb_WpFilterMinThr
+0x0F120160,	//0190	//awbb_WpFilterMaxThr
+0x0F1200A0, //awbb_WpFilterCoef
+0x0F120004, //awbb_WpFilterSize
+0x0F120001, //awbb_otp_disable
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F1203B0,  //03C0 //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F1203D4,  //03E2 //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F12037C,  //0356 //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F1203FE,  //03FC //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F120352,  //031E //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1203FC,  //03FE //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F120314,  //02F0 //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F1203E8,  //03F0 //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F1202DE,  //02CA //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F1203AC,  //03CC //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202AE,  //02A8 //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F120368,  //037A //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F120284,  //0280 //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F12031C,  //033C //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F120258,  //0260 //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F1202E4,  //030A //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120234,  //0242 //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F1202B8,  //02DC //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F120212,  //0228 //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F12029C,  //02B2 //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F1201F6,  //020E //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120290,  //0290 //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F1201DC,  //01F8 //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120288,  //0276 //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201CA,  //01E8 //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F120278,  //0268 //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201CA,  //01DC //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F12026C,  //0256 //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201D4,  //01E0 //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F120258,  //0238 //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201F2,  //01EC //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F120228,  //020E //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //05//awbb_IndoorGrZones_m_Grid
+0x002A0F80, //80
+0x0F1200F4, //E6//awbb_IndoorGrZones_m_Boff
+0x002A0F7C, //7C
+0x0F120010, //10
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+
+0x002A11A8,
+0x0F1202C8, //02C8//awbb_GridConst_1[0]
+0x0F120325, //0325//awbb_GridConst_1[1]
+0x0F12038F, //038F//awbb_GridConst_1[2]
+
+0x0F120F8E, //0F8E//awbb_GridConst_2[0]
+0x0F1210B3, //10B3//awbb_GridConst_2[1]
+0x0F121136, //1136//awbb_GridConst_2[2]
+0x0F121138, //1138//awbb_GridConst_2[3]
+0x0F1211A1, //118E//awbb_GridConst_2[4]
+0x0F121213, //1213//awbb_GridConst_2[5]
+
+0x0F1200A7, //00A7//awbb_GridCoeff_R_1
+0x0F1200C2, //00C2//awbb_GridCoeff_B_1
+0x0F1200BD, //00BD//awbb_GridCoeff_R_2
+0x0F1200AC, //00AC//awbb_GridCoeff_B_2
+
+0x002A1118,
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[0][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[0][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[0][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[0][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[0][5]
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[1][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[1][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[1][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[1][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[1][5]
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[2][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[2][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[2][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[2][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[2][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[0][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[0][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[0][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[0][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[0][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[0][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[1][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[1][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[1][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[1][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[1][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[1][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[2][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[2][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[2][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[2][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[2][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[2][5]
+
+0x002A1160,
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[0][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[0][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][5]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[1][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[1][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][5]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[2][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[2][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[0][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[0][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[1][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[1][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[2][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[2][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][5]
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0] 
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1] 
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2] 
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3] 
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[4] 
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5] 
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6] 
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7] 
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[8] 
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[9] 
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+0x0F120222,  //01F8  //01EA //01E2//TVAR_wbt_pBaseCcms[36]
+0x0F12FF9E,  //FFB0  //FFAC //FF9A//TVAR_wbt_pBaseCcms[37]
+0x0F12FFD0,  //FFE8  //FFE3 //FFE8//TVAR_wbt_pBaseCcms[38]
+0x0F12FEFD,  //FF39  //FF45 //FF45//TVAR_wbt_pBaseCcms[39]
+0x0F1201B2,  //0144  //0140 //0140//TVAR_wbt_pBaseCcms[40]
+0x0F12FF25,  //FF57  //FF4F //FF4F//TVAR_wbt_pBaseCcms[41]
+0x0F12FFC0,  //FFBD  //FFC3 //FFC3//TVAR_wbt_pBaseCcms[42]
+0x0F12FFC1,  //FFD0  //FFD5 //FFD5//TVAR_wbt_pBaseCcms[43]
+0x0F120189,  //017D  //0173 //0173//TVAR_wbt_pBaseCcms[44]
+0x0F1200C4,  //0113  //0137 //0128//TVAR_wbt_pBaseCcms[45]
+0x0F1200C3,  //00BF  //00C2 //00EA//TVAR_wbt_pBaseCcms[46]
+0x0F12FF33,  //FEE8  //FEC1 //FEA8//TVAR_wbt_pBaseCcms[47]
+0x0F1200CF,  //00CB  //00C8 //00C8//TVAR_wbt_pBaseCcms[48]
+0x0F12FF31,  //FF3F  //FF49 //FF49//TVAR_wbt_pBaseCcms[49]
+0x0F12015C,  //0152  //014B //014B//TVAR_wbt_pBaseCcms[50]
+0x0F12FF49,  //FF5E  //FF68 //FF68//TVAR_wbt_pBaseCcms[51]
+0x0F12011A,  //010F  //0109 //0109//TVAR_wbt_pBaseCcms[52]
+0x0F120102,  //00F9  //00F4 //00F4//TVAR_wbt_pBaseCcms[53]
+
+0x0F120222,  //01F8  //01EA //01E2//TVAR_wbt_pBaseCcms[54]
+0x0F12FF9E,  //FFB0  //FFAC //FF9A//TVAR_wbt_pBaseCcms[55]
+0x0F12FFD0,  //FFE8  //FFE3 //FFE8//TVAR_wbt_pBaseCcms[56]
+0x0F12FEFD,  //FF39  //FF45 //FF45//TVAR_wbt_pBaseCcms[57]
+0x0F1201B2,  //0144  //0140 //0140//TVAR_wbt_pBaseCcms[58]
+0x0F12FF25,  //FF57  //FF4F //FF4F//TVAR_wbt_pBaseCcms[59]
+0x0F12FFC0,  //FFBD  //FFC3 //FFC3//TVAR_wbt_pBaseCcms[60]
+0x0F12FFC1,  //FFD0  //FFD5 //FFD5//TVAR_wbt_pBaseCcms[61]
+0x0F120189,  //017D  //0173 //0173//TVAR_wbt_pBaseCcms[62]
+0x0F1200C4,  //0113  //0137 //0128//TVAR_wbt_pBaseCcms[63]
+0x0F1200C3,  //00BF  //00C2 //00EA//TVAR_wbt_pBaseCcms[64]
+0x0F12FF33,  //FEE8  //FEC1 //FEA8//TVAR_wbt_pBaseCcms[65]
+0x0F1200CF,  //00CB  //00C8 //00C8//TVAR_wbt_pBaseCcms[66]
+0x0F12FF31,  //FF3F  //FF49 //FF49//TVAR_wbt_pBaseCcms[67]
+0x0F12015C,  //0152  //014B //014B//TVAR_wbt_pBaseCcms[68]
+0x0F12FF49,  //FF5E  //FF68 //FF68//TVAR_wbt_pBaseCcms[69]
+0x0F12011A,  //010F  //0109 //0109//TVAR_wbt_pBaseCcms[70]
+0x0F120102,  //00F9  //00F4 //00F4//TVAR_wbt_pBaseCcms[71]
+
+0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F120040, //40 //4A //0049//#afit_uNoiseIndInDoor_0_
+0x0F120048, //48 //4E //005F//#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+0x002A08C0,
+0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700008C2//AFIT16_CONTRAST
+0x0F120000, //0000//700008C4//AFIT16_SATURATION
+0x0F120002, //0000//700008C6//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700008C8//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700008CA//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700008CC
+0x0F1203FF, //03FF//700008CE//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700008D0//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700008D2//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700008D4//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700008D6//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700008D8//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700008DA//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700008DC//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700008DE//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700008E0//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700008E2//AFIT16_demsharpmix1_iTune
+0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C//700008EA //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008//700008EC //AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700008EE //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700008F0 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700008F2 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700008F4 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700008F6 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//700008F8 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//700008FA //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//700008FC //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//700008FE //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000900 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000902 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000904 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //09E8//70000906 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000908 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//7000090A //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//7000090C //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F124000, //4000//7000090E 
+0x0F127803, //7803//70000910 
+0x0F123C50, //3C50//70000912 
+0x0F12003C, //003C//70000914 
+0x0F121E80, //1E80//70000916 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000918 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A//7000091A //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000//7000091C //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12120A, //120A//7000091E //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F121400, //0F00//70000920 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000922 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000924 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000926 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000928 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//7000092A //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//7000092C //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//7000092E //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000930 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000932 
+0x0F120609, //0609//70000934 
+0x0F122C07, //2C07//70000936 
+0x0F12142C, //142C//70000938 
+0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120880, //0880//7000093E //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120B50, //0B50//70000940 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000942 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000944 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000946 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124601, //4601//70000948 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12A444, //C844//7000094A //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F1250A4, //50C8//7000094C //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//7000094E //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120303, //0003//70000950 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121001, //1C01//70000952 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120710, //0714//70000954 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121448, //1464//70000956 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A03, //5A04//70000958 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12281E, //3C1E//7000095A //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //400F//7000095C //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//7000095E //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F121403, //1403//70000960 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120114, //0114//70000962 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000964 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124446, //4446//70000966 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F12646E, //646E//70000968 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//7000096A //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//7000096C //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120000, //0000//7000096E //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000970 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000972 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000974 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F120000, //0000//70000976 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000978 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//7000097A //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//7000097C //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121414, //1414//7000097E //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000980 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124601, //4601//70000982 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F126E44, //6E44//70000984 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122864, //2864//70000986 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000988 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F120003, //0003//7000098A //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E00, //1E00//7000098C //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//7000098E //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000990 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F120004, //0004//70000992 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F00, //0F00//70000994 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000996 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000998 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//7000099A //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//7000099C 
+0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700009A0//AFIT16_CONTRAST
+0x0F120000, //0000//700009A2//AFIT16_SATURATION
+0x0F120002, //0000//700009A4//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700009A6//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700009A8//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700009AA
+0x0F1203FF, //03FF//700009AC//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700009AE//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700009B0//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700009B2//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700009B4//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700009B6//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700009B8//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700009BA//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700009BC//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700009BE//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700009C0//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E//700009C8//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//700009CA//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700009CC//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700009CE//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700009D0//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700009D2//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700009D4//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//700009D6//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//700009D8//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//700009DA//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//700009DC//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//700009DE//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//700009E0//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//700009E2//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //05E8//700009E4//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//700009E6//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//700009E8//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//700009EA//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000//700009EC
+0x0F125003, //5003//700009EE
+0x0F123228, //3228//700009F0
+0x0F120032, //0032//700009F2
+0x0F121E80, //1E80//700009F4//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//700009F6//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A//700009F8//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000//700009FA//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12120A, //120A//700009FC//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F121400, //1400//700009FE//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000A00//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000A02//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000A04//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000A06//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000A08//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000A0A//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000A0C//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000A0E//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000A10
+0x0F120609, //0609//70000A12
+0x0F122C07, //2C07//70000A14
+0x0F12142C, //142C//70000A16
+0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120580, //0580//70000A1C//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000A1E//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000A20//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000A22//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000A24//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000A26//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12494B, //444B 494B//70000A28//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125044, //503C 5044//70000A2A//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000A2C//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120603, //0503//70000A2E//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D03, //0D02//70000A30//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //071E//70000A32//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1432//70000A34//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A01, //5A01//70000A36//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12281E, //281E//70000A38//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //200F//70000A3A//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000A3C//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F121E03, //1E03//70000A3E//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F12011E, //011E//70000A40//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000A42//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F123A3C, //3A3C//70000A44//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F12585A, //585A//70000A46//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000A48//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000A4A//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120000, //0000//70000A4C//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000A4E//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000A50//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000A52//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F120000, //0000//70000A54//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000A56//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000A58//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000A5A//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1E1E//70000A5C//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000A5E//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F123C01, //3C01//70000A60//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F125A3A, //5A3A//70000A62//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122858, //2858//70000A64//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000A66//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F120003, //0003//70000A68//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E00, //1E00//70000A6A//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//70000A6C//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000A6E//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F120004, //0004//70000A70//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F00, //0F00//70000A72//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000A74//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000A76//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000A78//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000A7A
+0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000A7E//AFIT16_CONTRAST
+0x0F120000, //0000//70000A80//AFIT16_SATURATION
+0x0F120000, //0000//70000A82//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000A84//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000A86//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000A88
+0x0F1203FF, //03FF//70000A8A//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000A8C//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000A8E//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000A90//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000A92//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000A94//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//70000A96//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000A98//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000A9A//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//70000A9C//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000A9E//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000AA6//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000AA8//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//70000AAA//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//70000AAC//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//70000AAE//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//70000AB0//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000AB2//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//70000AB4//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//70000AB6//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//70000AB8//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//70000ABA//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000ABC//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000ABE//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000AC0//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE//70000AC2//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000AC4//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//70000AC6//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//70000AC8//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000ACA
+0x0F122803, //2803//70000ACC
+0x0F12261E, //261E//70000ACE
+0x0F120026, //0026//70000AD0
+0x0F121E80, //1E80//70000AD2//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000AD4//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A//70000AD6//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001//70000AD8//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F123C0A, //3C0A//70000ADA//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122300, //2300//70000ADC//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000ADE//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000AE0//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000AE2//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000AE4//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000AE6//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000AE8//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000AEA//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000AEC//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000AEE
+0x0F120609, //0609//70000AF0
+0x0F121C07, //1C07//70000AF2
+0x0F121014, //1014//70000AF4
+0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000AFA//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000AFC//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000AFE//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000B00//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000B02//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000B04//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F122A4B, //2A4B//70000B06//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125020, //5020//70000B08//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000B0A//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121C03, //1C03//70000B0C//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D0C, //0D0C//70000B0E//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823//70000B10//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428//70000B12//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F126401, //6401//70000B14//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12282D, //282D//70000B16//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012//70000B18//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000B1A//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F122803, //2803//70000B1C//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120128, //0128//70000B1E//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000B20//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F122224, //2224//70000B22//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F123236, //3236//70000B24//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000B26//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000B28//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120410, //0410//70000B2A//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000B2C//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000B2E//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000B30//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124050, //4050//70000B32//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000B34//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000B36//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000B38//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F122828, //2828//70000B3A//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000B3C//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F122401, //2401//70000B3E//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F123622, //3622//70000B40//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122832, //2832//70000B42//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000B44//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121003, //1003//70000B46//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E04, //1E04//70000B48//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//70000B4A//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000B4C//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125004, //5004//70000B4E//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F40, //0F40//70000B50//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000B52//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000B54//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000B56//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000B58
+0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000B5C//AFIT16_CONTRAST
+0x0F120000, //0000//70000B5E//AFIT16_SATURATION
+0x0F120000, //0000//70000B60//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000B62//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000B64//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000B66
+0x0F1203FF, //03FF//70000B68//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000B6A//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000B6C//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000B6E//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000B70//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000B72//AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8//70000B74//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000B76//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000B78//AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050//70000B7A//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000B7C//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000B84//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000B86//AFIT16_Sharpening_iHighSharpClamp
+0x0F12002D, //002D//70000B88//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//70000B8A//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12002D, //002D//70000B8C//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//70000B8E//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000B90//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//70000B92//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//70000B94//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//70000B96//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//70000B98//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000B9A//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000B9C//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000B9E//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE//70000BA0//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000BA2//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//70000BA4//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//70000BA6//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000BA8
+0x0F122303, //2303//70000BAA
+0x0F12231A, //231A//70000BAC
+0x0F120023, //0023//70000BAE
+0x0F121E80, //1E80//70000BB0//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000BB2//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A//70000BB4//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001//70000BB6//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F123C0A, //3C0A//70000BB8//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122300, //2300//70000BBA//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000BBC//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000BBE//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000BC0//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10//70000BC2//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000BC4//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000BC6//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000BC8//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705//70000BCA//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120306, //0306//70000BCC
+0x0F120509, //0509//70000BCE
+0x0F122806, //2806//70000BD0
+0x0F121428, //1428//70000BD2
+0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000BD8//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000BDA//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000BDC//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000BDE//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000BE0//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000BE2//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F122A4B, //2A4B//70000BE4//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125020, //5020//70000BE6//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000BE8//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121C03, //1C03//70000BEA//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D0C, //0D0C//70000BEC//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823//70000BEE//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428//70000BF0//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F126401, //6401//70000BF2//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12282D, //282D//70000BF4//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012//70000BF6//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000BF8//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F123C03, //3C03//70000BFA//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F12013C, //013C//70000BFC//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000BFE//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F121C1E, //1C1E//70000C00//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F121E22, //1E22//70000C02//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000C04//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000C06//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120214, //0214//70000C08//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120E14, //0E14//70000C0A//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF06, //FF06//70000C0C//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000C0E//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124052, //4052//70000C10//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F12150C, //150C//70000C12//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000C14//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000C16//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F123C3C, //3C3C//70000C18//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000C1A//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F121E01, //1E01//70000C1C//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12221C, //221C//70000C1E//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F12281E, //281E//70000C20//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000C22//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121403, //1403//70000C24//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121402, //1402//70000C26//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12060E, //060E//70000C28//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000C2A//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125204, //5204//70000C2C//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120C40, //0C40//70000C2E//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124015, //4015//70000C30//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000C32//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000C34//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000C36
+0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//0000//70000C44
+0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]       
+0x0F121000, //1000//1000//70000C86        
+0x0F122003, //2003//2003//70000C88        
+0x0F121020, //1020//1020//70000C8A        
+0x0F120010, //0010//0010//70000C8C        
+0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120305, //0305//0305//70000CAA        
+0x0F120609, //0609//0609//70000CAC        
+0x0F122C07, //2C07//2C07//70000CAE        
+0x0F12142C, //142C//142C//70000CB0        
+0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH     
+0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]        
+0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//0001//70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F122102, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+
+};
+
+static const u32 s5k5ccgx_camcorder_set[] =
+{
+0xFCFCD000,
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight	//Sensor Crop Height 1536
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs	//Sensor VOffset 0
+0x0F120800,	//REG_TC_GP_CapReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_CapReqInputHeight		//Sensor Crop Height 1368
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs		//Sensor VOffset 0
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+
+
+//Preview Size
+0x002A0400,
+0x0F120300,	//REG_0TC_PCFG_usWidth
+0x0F1201E0,	//REG_0TC_PCFG_usHeight
+
+0x002A029E,
+0x0F120400,	//REG_2TC_PCFG_usWidth
+0x0F120300, //REG_2TC_PCFG_usHeight
+
+//Capture Size
+0x002A0330,
+0x0F120800,	//REG_0TC_CCFG_usWidth
+0x0F120600,	//REG_0TC_CCFG_usHeight
+
+0x002A0388,
+0x0F120800, //REG_2TC_CCFG_usWidth
+0x0F120600, //REG_2TC_CCFG_usHeight
+
+};
+
+static const u32 s5k5ccgx_update_preview_setting[] = {
+//PREVIEW   
+0x002A0208, 
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210, 
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C, 
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4, 
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A, 
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212, 
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8, 
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+0xFFFF0064, //Delay 100ms
+};
+
+static const u32 s5k5ccgx_stream_stop_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E4,
+0x0F120000,
+0x0F120001,
+0xFFFF0078, //Delay 120ms
+};
+
+static const u32 s5k5ccgx_176_144_Preview[] = {
+0xFCFCD000, 
+0x00287000,
+
+0x002A023E, //Preview Size 
+0x0F1200B0, //REG_0TC_PCFG_usWidth  
+0x0F120090, //REG_0TC_PCFG_usHeight        
+    
+};
+
+static const u32 s5k5ccgx_320_240_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120140,	//REG_0TC_PCFG_usWidth 320
+0x0F1200F0,	//REG_0TC_PCFG_usHeight 240
+};
+
+
+
+static const u32 s5k5ccgx_352_288_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120160,	//REG_0TC_PCFG_usWidth 280
+0x0F120120,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+static const u32 s5k5ccgx_528_432_Preview[] = {
+0xFCFCD000, 
+0x00287000,
+
+0x002A023E, //Preview Size 
+0x0F120210, //REG_0TC_PCFG_usWidth  
+0x0F1201B0, //REG_0TC_PCFG_usHeight        
+
+};
+
+static const u32 s5k5ccgx_640_480_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120280,	//REG_0TC_PCFG_usWidth 280
+0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_720_480_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F1202D0,	//REG_0TC_PCFG_usWidth 280
+0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_800_600_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120320,	//REG_0TC_PCFG_usWidth 280
+0x0F120258,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+#define S5K5CCGX_WIDE_PREVIEW_REG s5k5ccgx_1024_576_Preview
+static const u32 s5k5ccgx_1024_576_Preview[] = {
+0xFCFCD000,
+0x00287000,
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth 400
+0x0F120240,	//REG_0TC_PCFG_usHeight 240
+0x0F120005,	//REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_768_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth 280
+0x0F120300,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_1280_1024_Preview[] = {
+
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000          //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A,     //p10
+// Start of Patch data
+0x00287000,
+0x002A352C,
+0x0F12B570, // 7000352C 
+0x0F124A24, // 7000352E 
+0x0F124924, // 70003530 
+0x0F124825, // 70003532 
+0x0F124B25, // 70003534 
+0x0F122500, // 70003536 
+0x0F12801D, // 70003538 
+0x0F12C004, // 7000353A 
+0x0F126001, // 7000353C 
+0x0F124924, // 7000353E 
+0x0F124824, // 70003540 
+0x0F12F000, // 70003542 
+0x0F12FBBD, // 70003544 
+0x0F124924, // 70003546 
+0x0F124824, // 70003548 
+0x0F12F000, // 7000354A 
+0x0F12FBB9, // 7000354C 
+0x0F124824, // 7000354E 
+0x0F124E24, // 70003550 
+0x0F126430, // 70003552 
+0x0F124924, // 70003554 
+0x0F124825, // 70003556 
+0x0F12F000, // 70003558 
+0x0F12FBB2, // 7000355A 
+0x0F124924, // 7000355C 
+0x0F120030, // 7000355E 
+0x0F123080, // 70003560 
+0x0F126141, // 70003562 
+0x0F124C23, // 70003564 
+0x0F128365, // 70003566 
+0x0F124923, // 70003568 
+0x0F124824, // 7000356A 
+0x0F12F000, // 7000356C 
+0x0F12FBA8, // 7000356E 
+0x0F124923, // 70003570 
+0x0F124824, // 70003572 
+0x0F12F000, // 70003574 
+0x0F12FBA4, // 70003576 
+0x0F124923, // 70003578 
+0x0F124824, // 7000357A 
+0x0F12F000, // 7000357C 
+0x0F12FBA0, // 7000357E 
+0x0F124923, // 70003580 
+0x0F124824, // 70003582 
+0x0F12F000, // 70003584 
+0x0F12FB9C, // 70003586 
+0x0F128125, // 70003588 
+0x0F124923, // 7000358A 
+0x0F124823, // 7000358C 
+0x0F12F000, // 7000358E 
+0x0F12FB97, // 70003590 
+0x0F124923, // 70003592 
+0x0F124823, // 70003594 
+0x0F12F000, // 70003596 
+0x0F12FB93, // 70003598 
+0x0F1283A5, // 7000359A 
+0x0F124922, // 7000359C 
+0x0F124823, // 7000359E 
+0x0F12F000, // 700035A0 
+0x0F12FB8E, // 700035A2 
+0x0F122101, // 700035A4 
+0x0F120349, // 700035A6 
+0x0F120020, // 700035A8 
+0x0F123020, // 700035AA 
+0x0F128041, // 700035AC 
+0x0F122185, // 700035AE 
+0x0F128081, // 700035B0 
+0x0F12491F, // 700035B2 
+0x0F1280C1, // 700035B4 
+0x0F12481F, // 700035B6 
+0x0F126730, // 700035B8 
+0x0F12BC70, // 700035BA 
+0x0F12BC08, // 700035BC 
+0x0F124718, // 700035BE 
+0x0F1200CA, // 700035C0 
+0x0F125CC1, // 700035C2 
+0x0F1203BD, // 700035C4 
+0x0F120000, // 700035C6 
+0x0F121C08, // 700035C8 
+0x0F127000, // 700035CA 
+0x0F123290, // 700035CC 
+0x0F127000, // 700035CE 
+0x0F123657, // 700035D0 
+0x0F127000, // 700035D2 
+0x0F12D9E7, // 700035D4 
+0x0F120000, // 700035D6 
+0x0F12383F, // 700035D8 
+0x0F127000, // 700035DA 
+0x0F12395D, // 700035DC 
+0x0F120000, // 700035DE 
+0x0F1238D1, // 700035E0 
+0x0F127000, // 700035E2 
+0x0F120000, // 700035E4 
+0x0F127000, // 700035E6 
+0x0F12399D, // 700035E8 
+0x0F127000, // 700035EA 
+0x0F12F903, // 700035EC 
+0x0F120000, // 700035EE 
+0x0F123AC1, // 700035F0 
+0x0F127000, // 700035F2 
+0x0F123FC8, // 700035F4 
+0x0F127000, // 700035F6 
+0x0F12368F, // 700035F8 
+0x0F127000, // 700035FA 
+0x0F12495F, // 700035FC 
+0x0F120000, // 700035FE 
+0x0F1236ED, // 70003600 
+0x0F127000, // 70003602 
+0x0F12E421, // 70003604 
+0x0F120000, // 70003606 
+0x0F1237AB, // 70003608 
+0x0F127000, // 7000360A 
+0x0F12216D, // 7000360C 
+0x0F120000, // 7000360E 
+0x0F12381F, // 70003610 
+0x0F127000, // 70003612 
+0x0F120179, // 70003614 
+0x0F120001, // 70003616 
+0x0F123BD5, // 70003618 
+0x0F127000, // 7000361A 
+0x0F1204C9, // 7000361C 
+0x0F120000, // 7000361E 
+0x0F123B25, // 70003620 
+0x0F127000, // 70003622 
+0x0F125027, // 70003624 
+0x0F120000, // 70003626 
+0x0F123BE1, // 70003628 
+0x0F127000, // 7000362A 
+0x0F1242B7, // 7000362C 
+0x0F120000, // 7000362E 
+0x0F1207FF, // 70003630 
+0x0F120000, // 70003632 
+0x0F123C5F, // 70003634 
+0x0F127000, // 70003636 
+0x0F12B570, // 70003638 
+0x0F12000D, // 7000363A 
+0x0F124CFC, // 7000363C 
+0x0F128821, // 7000363E 
+0x0F12F000, // 70003640 
+0x0F12FB46, // 70003642 
+0x0F128820, // 70003644 
+0x0F124AFB, // 70003646 
+0x0F120081, // 70003648 
+0x0F125055, // 7000364A 
+0x0F121C40, // 7000364C 
+0x0F128020, // 7000364E 
+0x0F12BC70, // 70003650 
+0x0F12BC08, // 70003652 
+0x0F124718, // 70003654 
+0x0F126801, // 70003656 
+0x0F120409, // 70003658 
+0x0F120C09, // 7000365A 
+0x0F126840, // 7000365C 
+0x0F120400, // 7000365E 
+0x0F120C00, // 70003660 
+0x0F124AF5, // 70003662 
+0x0F128992, // 70003664 
+0x0F122A00, // 70003666 
+0x0F12D00D, // 70003668 
+0x0F122300, // 7000366A 
+0x0F121A80, // 7000366C 
+0x0F12D400, // 7000366E 
+0x0F120003, // 70003670 
+0x0F120418, // 70003672 
+0x0F120C00, // 70003674 
+0x0F124BF1, // 70003676 
+0x0F121851, // 70003678 
+0x0F12891B, // 7000367A 
+0x0F12428B, // 7000367C 
+0x0F12D300, // 7000367E 
+0x0F12000B, // 70003680 
+0x0F120419, // 70003682 
+0x0F120C09, // 70003684 
+0x0F124AEE, // 70003686 
+0x0F128151, // 70003688 
+0x0F128190, // 7000368A 
+0x0F124770, // 7000368C 
+0x0F12B510, // 7000368E 
+0x0F124CEC, // 70003690 
+0x0F1248ED, // 70003692 
+0x0F1278A1, // 70003694 
+0x0F122900, // 70003696 
+0x0F12D101, // 70003698 
+0x0F1287C1, // 7000369A 
+0x0F12E004, // 7000369C 
+0x0F127AE1, // 7000369E 
+0x0F122900, // 700036A0 
+0x0F12D001, // 700036A2 
+0x0F122101, // 700036A4 
+0x0F1287C1, // 700036A6 
+0x0F12F000, // 700036A8 
+0x0F12FB1A, // 700036AA 
+0x0F1249E7, // 700036AC 
+0x0F128B08, // 700036AE 
+0x0F1206C2, // 700036B0 
+0x0F12D50A, // 700036B2 
+0x0F127AA2, // 700036B4 
+0x0F120652, // 700036B6 
+0x0F12D507, // 700036B8 
+0x0F122210, // 700036BA 
+0x0F124390, // 700036BC 
+0x0F128308, // 700036BE 
+0x0F1248E3, // 700036C0 
+0x0F127AE1, // 700036C2 
+0x0F126B00, // 700036C4 
+0x0F12F000, // 700036C6 
+0x0F12FB13, // 700036C8 
+0x0F1248DB, // 700036CA 
+0x0F1289C0, // 700036CC 
+0x0F122801, // 700036CE 
+0x0F12D109, // 700036D0 
+0x0F1278A0, // 700036D2 
+0x0F122800, // 700036D4 
+0x0F12D006, // 700036D6 
+0x0F127AE0, // 700036D8 
+0x0F122800, // 700036DA 
+0x0F12D003, // 700036DC 
+0x0F127AA0, // 700036DE 
+0x0F122140, // 700036E0 
+0x0F124308, // 700036E2 
+0x0F1272A0, // 700036E4 
+0x0F12BC10, // 700036E6 
+0x0F12BC08, // 700036E8 
+0x0F124718, // 700036EA 
+0x0F12B570, // 700036EC 
+0x0F124DD7, // 700036EE 
+0x0F124CD7, // 700036F0 
+0x0F128B28, // 700036F2 
+0x0F120701, // 700036F4 
+0x0F12D507, // 700036F6 
+0x0F122108, // 700036F8 
+0x0F124388, // 700036FA 
+0x0F128328, // 700036FC 
+0x0F1249D5, // 700036FE 
+0x0F126B20, // 70003700 
+0x0F126B89, // 70003702 
+0x0F12F000, // 70003704 
+0x0F12FAFC, // 70003706 
+0x0F128B28, // 70003708 
+0x0F1206C1, // 7000370A 
+0x0F12D5A0, // 7000370C 
+0x0F1249CD, // 7000370E 
+0x0F127A8A, // 70003710 
+0x0F120652, // 70003712 
+0x0F12D49C, // 70003714 
+0x0F122210, // 70003716 
+0x0F124390, // 70003718 
+0x0F128328, // 7000371A 
+0x0F127AC9, // 7000371C 
+0x0F126B20, // 7000371E 
+0x0F12F000, // 70003720 
+0x0F12FAE6, // 70003722 
+0x0F12E794, // 70003724 
+0x0F12B5F8, // 70003726 
+0x0F1249CB, // 70003728 
+0x0F128F08, // 7000372A 
+0x0F12000C, // 7000372C 
+0x0F123480, // 7000372E 
+0x0F122800, // 70003730 
+0x0F12D000, // 70003732 
+0x0F128360, // 70003734 
+0x0F122000, // 70003736 
+0x0F128708, // 70003738 
+0x0F124DC8, // 7000373A 
+0x0F1226FF, // 7000373C 
+0x0F128828, // 7000373E 
+0x0F121C76, // 70003740 
+0x0F122702, // 70003742 
+0x0F122803, // 70003744 
+0x0F12D112, // 70003746 
+0x0F128868, // 70003748 
+0x0F122800, // 7000374A 
+0x0F12D10F, // 7000374C 
+0x0F1288E8, // 7000374E 
+0x0F122800, // 70003750 
+0x0F12D10C, // 70003752 
+0x0F12F000, // 70003754 
+0x0F12FADC, // 70003756 
+0x0F122800, // 70003758 
+0x0F12D008, // 7000375A 
+0x0F128B60, // 7000375C 
+0x0F122800, // 7000375E 
+0x0F12D001, // 70003760 
+0x0F1280EE, // 70003762 
+0x0F1280AF, // 70003764 
+0x0F122001, // 70003766 
+0x0F127268, // 70003768 
+0x0F12F000, // 7000376A 
+0x0F12FAD9, // 7000376C 
+0x0F128828, // 7000376E 
+0x0F122802, // 70003770 
+0x0F12D10E, // 70003772 
+0x0F128868, // 70003774 
+0x0F122800, // 70003776 
+0x0F12D10B, // 70003778 
+0x0F1288E8, // 7000377A 
+0x0F122800, // 7000377C 
+0x0F12D108, // 7000377E 
+0x0F128B60, // 70003780 
+0x0F122800, // 70003782 
+0x0F12D001, // 70003784 
+0x0F1280EE, // 70003786 
+0x0F1280AF, // 70003788 
+0x0F122001, // 7000378A 
+0x0F127268, // 7000378C 
+0x0F12F000, // 7000378E 
+0x0F12FAC7, // 70003790 
+0x0F1288E8, // 70003792 
+0x0F122800, // 70003794 
+0x0F12D006, // 70003796 
+0x0F121FC1, // 70003798 
+0x0F1239FD, // 7000379A 
+0x0F12D003, // 7000379C 
+0x0F122001, // 7000379E 
+0x0F12BCF8, // 700037A0 
+0x0F12BC08, // 700037A2 
+0x0F124718, // 700037A4 
+0x0F122000, // 700037A6 
+0x0F12E7FA, // 700037A8 
+0x0F12B570, // 700037AA 
+0x0F124CAC, // 700037AC 
+0x0F128860, // 700037AE 
+0x0F122800, // 700037B0 
+0x0F12D00C, // 700037B2 
+0x0F128820, // 700037B4 
+0x0F124DA3, // 700037B6 
+0x0F122800, // 700037B8 
+0x0F12D009, // 700037BA 
+0x0F120029, // 700037BC 
+0x0F1231A0, // 700037BE 
+0x0F127AC9, // 700037C0 
+0x0F122900, // 700037C2 
+0x0F12D004, // 700037C4 
+0x0F127AA8, // 700037C6 
+0x0F122180, // 700037C8 
+0x0F124308, // 700037CA 
+0x0F1272A8, // 700037CC 
+0x0F12E73F, // 700037CE 
+0x0F122800, // 700037D0 
+0x0F12D003, // 700037D2 
+0x0F12F7FF, // 700037D4 
+0x0F12FFA7, // 700037D6 
+0x0F122800, // 700037D8 
+0x0F12D1F8, // 700037DA 
+0x0F122000, // 700037DC 
+0x0F128060, // 700037DE 
+0x0F128820, // 700037E0 
+0x0F122800, // 700037E2 
+0x0F12D003, // 700037E4 
+0x0F122008, // 700037E6 
+0x0F12F000, // 700037E8 
+0x0F12FAA2, // 700037EA 
+0x0F12E00B, // 700037EC 
+0x0F12489C, // 700037EE 
+0x0F123020, // 700037F0 
+0x0F128880, // 700037F2 
+0x0F122800, // 700037F4 
+0x0F12D103, // 700037F6 
+0x0F127AA8, // 700037F8 
+0x0F122101, // 700037FA 
+0x0F124308, // 700037FC 
+0x0F1272A8, // 700037FE 
+0x0F122010, // 70003800 
+0x0F12F000, // 70003802 
+0x0F12FA95, // 70003804 
+0x0F128820, // 70003806 
+0x0F122800, // 70003808 
+0x0F12D1E0, // 7000380A 
+0x0F12488A, // 7000380C 
+0x0F1289C0, // 7000380E 
+0x0F122801, // 70003810 
+0x0F12D1DC, // 70003812 
+0x0F127AA8, // 70003814 
+0x0F1221BF, // 70003816 
+0x0F124008, // 70003818 
+0x0F1272A8, // 7000381A 
+0x0F12E718, // 7000381C 
+0x0F126800, // 7000381E 
+0x0F124990, // 70003820 
+0x0F128188, // 70003822 
+0x0F124890, // 70003824 
+0x0F122201, // 70003826 
+0x0F128981, // 70003828 
+0x0F124890, // 7000382A 
+0x0F120252, // 7000382C 
+0x0F124291, // 7000382E 
+0x0F12D902, // 70003830 
+0x0F122102, // 70003832 
+0x0F128181, // 70003834 
+0x0F124770, // 70003836 
+0x0F122101, // 70003838 
+0x0F128181, // 7000383A 
+0x0F124770, // 7000383C 
+0x0F12B5F1, // 7000383E 
+0x0F124E80, // 70003840 
+0x0F128834, // 70003842 
+0x0F122C00, // 70003844 
+0x0F12D03F, // 70003846 
+0x0F122001, // 70003848 
+0x0F122C08, // 7000384A 
+0x0F12D000, // 7000384C 
+0x0F122000, // 7000384E 
+0x0F1270B0, // 70003850 
+0x0F124D7F, // 70003852 
+0x0F122800, // 70003854 
+0x0F12D009, // 70003856 
+0x0F12F000, // 70003858 
+0x0F12FA72, // 7000385A 
+0x0F120028, // 7000385C 
+0x0F1238F0, // 7000385E 
+0x0F126328, // 70003860 
+0x0F127AB0, // 70003862 
+0x0F12217E, // 70003864 
+0x0F124008, // 70003866 
+0x0F1272B0, // 70003868 
+0x0F12E00F, // 7000386A 
+0x0F124F7A, // 7000386C 
+0x0F123780, // 7000386E 
+0x0F128B78, // 70003870 
+0x0F122800, // 70003872 
+0x0F12D005, // 70003874 
+0x0F12F000, // 70003876 
+0x0F12FA6B, // 70003878 
+0x0F122000, // 7000387A 
+0x0F128378, // 7000387C 
+0x0F124976, // 7000387E 
+0x0F128708, // 70003880 
+0x0F122000, // 70003882 
+0x0F12F000, // 70003884 
+0x0F12FA6C, // 70003886 
+0x0F124879, // 70003888 
+0x0F126328, // 7000388A 
+0x0F1278B1, // 7000388C 
+0x0F122700, // 7000388E 
+0x0F120038, // 70003890 
+0x0F122900, // 70003892 
+0x0F12D008, // 70003894 
+0x0F124972, // 70003896 
+0x0F123920, // 70003898 
+0x0F128ACA, // 7000389A 
+0x0F122A00, // 7000389C 
+0x0F12D003, // 7000389E 
+0x0F128B09, // 700038A0 
+0x0F122900, // 700038A2 
+0x0F12D000, // 700038A4 
+0x0F122001, // 700038A6 
+0x0F127170, // 700038A8 
+0x0F122C02, // 700038AA 
+0x0F12D102, // 700038AC 
+0x0F124868, // 700038AE 
+0x0F123860, // 700038B0 
+0x0F126328, // 700038B2 
+0x0F122201, // 700038B4 
+0x0F122C02, // 700038B6 
+0x0F12D000, // 700038B8 
+0x0F122200, // 700038BA 
+0x0F124861, // 700038BC 
+0x0F122110, // 700038BE 
+0x0F12300A, // 700038C0 
+0x0F12F000, // 700038C2 
+0x0F12FA55, // 700038C4 
+0x0F128037, // 700038C6 
+0x0F129900, // 700038C8 
+0x0F120020, // 700038CA 
+0x0F12600C, // 700038CC 
+0x0F12E767, // 700038CE 
+0x0F12B538, // 700038D0 
+0x0F124865, // 700038D2 
+0x0F124669, // 700038D4 
+0x0F123848, // 700038D6 
+0x0F12F000, // 700038D8 
+0x0F12FA52, // 700038DA 
+0x0F124A5E, // 700038DC 
+0x0F124862, // 700038DE 
+0x0F128F51, // 700038E0 
+0x0F122400, // 700038E2 
+0x0F123020, // 700038E4 
+0x0F122900, // 700038E6 
+0x0F12D00A, // 700038E8 
+0x0F128754, // 700038EA 
+0x0F126941, // 700038EC 
+0x0F126451, // 700038EE 
+0x0F126491, // 700038F0 
+0x0F12466B, // 700038F2 
+0x0F128819, // 700038F4 
+0x0F1287D1, // 700038F6 
+0x0F12885B, // 700038F8 
+0x0F120011, // 700038FA 
+0x0F123140, // 700038FC 
+0x0F12800B, // 700038FE 
+0x0F128F91, // 70003900 
+0x0F122900, // 70003902 
+0x0F12D002, // 70003904 
+0x0F128794, // 70003906 
+0x0F126940, // 70003908 
+0x0F126490, // 7000390A 
+0x0F12F000, // 7000390C 
+0x0F12FA40, // 7000390E 
+0x0F12BC38, // 70003910 
+0x0F12BC08, // 70003912 
+0x0F124718, // 70003914 
+0x0F12B5F8, // 70003916 
+0x0F124C56, // 70003918 
+0x0F1289E0, // 7000391A 
+0x0F12F000, // 7000391C 
+0x0F12FA40, // 7000391E 
+0x0F120006, // 70003920 
+0x0F128A20, // 70003922 
+0x0F12F000, // 70003924 
+0x0F12FA44, // 70003926 
+0x0F120007, // 70003928 
+0x0F12484F, // 7000392A 
+0x0F124D4A, // 7000392C 
+0x0F123020, // 7000392E 
+0x0F126CA9, // 70003930 
+0x0F126940, // 70003932 
+0x0F121809, // 70003934 
+0x0F120200, // 70003936 
+0x0F12F000, // 70003938 
+0x0F12FA42, // 7000393A 
+0x0F120400, // 7000393C 
+0x0F120C00, // 7000393E 
+0x0F12002A, // 70003940 
+0x0F12326E, // 70003942 
+0x0F120011, // 70003944 
+0x0F12390A, // 70003946 
+0x0F122305, // 70003948 
+0x0F12F000, // 7000394A 
+0x0F12FA3F, // 7000394C 
+0x0F124C43, // 7000394E 
+0x0F1261A0, // 70003950 
+0x0F128FEB, // 70003952 
+0x0F120002, // 70003954 
+0x0F120031, // 70003956 
+0x0F120018, // 70003958 
+0x0F12F000, // 7000395A 
+0x0F12FA3F, // 7000395C 
+0x0F12466B, // 7000395E 
+0x0F120005, // 70003960 
+0x0F128018, // 70003962 
+0x0F12483C, // 70003964 
+0x0F1269A2, // 70003966 
+0x0F123040, // 70003968 
+0x0F128800, // 7000396A 
+0x0F120039, // 7000396C 
+0x0F12F000, // 7000396E 
+0x0F12FA35, // 70003970 
+0x0F12466B, // 70003972 
+0x0F120006, // 70003974 
+0x0F128058, // 70003976 
+0x0F120021, // 70003978 
+0x0F129800, // 7000397A 
+0x0F12311C, // 7000397C 
+0x0F12F000, // 7000397E 
+0x0F12FA35, // 70003980 
+0x0F124935, // 70003982 
+0x0F123180, // 70003984 
+0x0F12808D, // 70003986 
+0x0F1280CE, // 70003988 
+0x0F128BA1, // 7000398A 
+0x0F124836, // 7000398C 
+0x0F123820, // 7000398E 
+0x0F128001, // 70003990 
+0x0F128BE1, // 70003992 
+0x0F128041, // 70003994 
+0x0F128C21, // 70003996 
+0x0F128081, // 70003998 
+0x0F12E701, // 7000399A 
+0x0F12B5F8, // 7000399C 
+0x0F124E2E, // 7000399E 
+0x0F126C70, // 700039A0 
+0x0F126CB1, // 700039A2 
+0x0F120200, // 700039A4 
+0x0F12F000, // 700039A6 
+0x0F12FA0B, // 700039A8 
+0x0F120400, // 700039AA 
+0x0F120C00, // 700039AC 
+0x0F122401, // 700039AE 
+0x0F120364, // 700039B0 
+0x0F1242A0, // 700039B2 
+0x0F12D200, // 700039B4 
+0x0F120004, // 700039B6 
+0x0F124A27, // 700039B8 
+0x0F120020, // 700039BA 
+0x0F12327E, // 700039BC 
+0x0F121F91, // 700039BE 
+0x0F122303, // 700039C0 
+0x0F12F000, // 700039C2 
+0x0F12FA03, // 700039C4 
+0x0F120405, // 700039C6 
+0x0F120C2D, // 700039C8 
+0x0F124A23, // 700039CA 
+0x0F120020, // 700039CC 
+0x0F12325A, // 700039CE 
+0x0F120011, // 700039D0 
+0x0F12390A, // 700039D2 
+0x0F122305, // 700039D4 
+0x0F12F000, // 700039D6 
+0x0F12F9F9, // 700039D8 
+0x0F12491F, // 700039DA 
+0x0F1264C8, // 700039DC 
+0x0F12491F, // 700039DE 
+0x0F124E21, // 700039E0 
+0x0F1288C8, // 700039E2 
+0x0F122701, // 700039E4 
+0x0F122800, // 700039E6 
+0x0F12D009, // 700039E8 
+0x0F124C23, // 700039EA 
+0x0F1238FF, // 700039EC 
+0x0F121E40, // 700039EE 
+0x0F12D00A, // 700039F0 
+0x0F122804, // 700039F2 
+0x0F12D042, // 700039F4 
+0x0F122806, // 700039F6 
+0x0F12D101, // 700039F8 
+0x0F122000, // 700039FA 
+0x0F1280C8, // 700039FC 
+0x0F1282B7, // 700039FE 
+0x0F122001, // 70003A00 
+0x0F12F000, // 70003A02 
+0x0F12F9FB, // 70003A04 
+0x0F12E6CB, // 70003A06 
+0x0F12000D, // 70003A08 
+0x0F12724F, // 70003A0A 
+0x0F122001, // 70003A0C 
+0x0F12F000, // 70003A0E 
+0x0F12F9FD, // 70003A10 
+0x0F12F000, // 70003A12 
+0x0F12FA03, // 70003A14 
+0x0F124910, // 70003A16 
+0x0F123148, // 70003A18 
+0x0F12C903, // 70003A1A 
+0x0F124348, // 70003A1C 
+0x0F120A00, // 70003A1E 
+0x0F126160, // 70003A20 
+0x0F1220FF, // 70003A22 
+0x0F121D40, // 70003A24 
+0x0F1280E8, // 70003A26 
+0x0F12480C, // 70003A28 
+0x0F123040, // 70003A2A 
+0x0F127707, // 70003A2C 
+0x0F12E7E6, // 70003A2E 
+0x0F123290, // 70003A30 
+0x0F127000, // 70003A32 
+0x0F123294, // 70003A34 
+0x0F127000, // 70003A36 
+0x0F1204A8, // 70003A38 
+0x0F127000, // 70003A3A 
+0x0F1215DC, // 70003A3C 
+0x0F127000, // 70003A3E 
+0x0F125000, // 70003A40 
+0x0F12D000, // 70003A42 
+0x0F121E84, // 70003A44 
+0x0F127000, // 70003A46 
+0x0F121BE4, // 70003A48 
+0x0F127000, // 70003A4A 
+0x0F122EA8, // 70003A4C 
+0x0F127000, // 70003A4E 
+0x0F1221A4, // 70003A50 
+0x0F127000, // 70003A52 
+0x0F120100, // 70003A54 
+0x0F127000, // 70003A56 
+0x0F123F48, // 70003A58 
+0x0F127000, // 70003A5A 
+0x0F1231A0, // 70003A5C 
+0x0F127000, // 70003A5E 
+0x0F1201E8, // 70003A60 
+0x0F127000, // 70003A62 
+0x0F12F2A0, // 70003A64 
+0x0F12D000, // 70003A66 
+0x0F122A44, // 70003A68 
+0x0F127000, // 70003A6A 
+0x0F12F400, // 70003A6C 
+0x0F12D000, // 70003A6E 
+0x0F122024, // 70003A70 
+0x0F127000, // 70003A72 
+0x0F121650, // 70003A74 
+0x0F127000, // 70003A76 
+0x0F122A64, // 70003A78 
+0x0F127000, // 70003A7A 
+0x0F124982, // 70003A7C 
+0x0F12724F, // 70003A7E 
+0x0F1220FF, // 70003A80 
+0x0F121DC0, // 70003A82 
+0x0F1280C8, // 70003A84 
+0x0F12F000, // 70003A86 
+0x0F12F9D1, // 70003A88 
+0x0F124980, // 70003A8A 
+0x0F126ACA, // 70003A8C 
+0x0F12604A, // 70003A8E 
+0x0F122800, // 70003A90 
+0x0F12D006, // 70003A92 
+0x0F12436A, // 70003A94 
+0x0F120001, // 70003A96 
+0x0F120010, // 70003A98 
+0x0F12F000, // 70003A9A 
+0x0F12F991, // 70003A9C 
+0x0F126160, // 70003A9E 
+0x0F12E001, // 70003AA0 
+0x0F12436A, // 70003AA2 
+0x0F126162, // 70003AA4 
+0x0F128BF0, // 70003AA6 
+0x0F122800, // 70003AA8 
+0x0F12D001, // 70003AAA 
+0x0F12F7FF, // 70003AAC 
+0x0F12FF33, // 70003AAE 
+0x0F122000, // 70003AB0 
+0x0F12F000, // 70003AB2 
+0x0F12F9AB, // 70003AB4 
+0x0F124974, // 70003AB6 
+0x0F1220FF, // 70003AB8 
+0x0F121DC0, // 70003ABA 
+0x0F1280C8, // 70003ABC 
+0x0F12E79E, // 70003ABE 
+0x0F12B510, // 70003AC0 
+0x0F12F000, // 70003AC2 
+0x0F12F9BB, // 70003AC4 
+0x0F124870, // 70003AC6 
+0x0F1288C0, // 70003AC8 
+0x0F121FC1, // 70003ACA 
+0x0F1239FD, // 70003ACC 
+0x0F12D103, // 70003ACE 
+0x0F12496F, // 70003AD0 
+0x0F1220FF, // 70003AD2 
+0x0F121C40, // 70003AD4 
+0x0F128048, // 70003AD6 
+0x0F12E605, // 70003AD8 
+0x0F12B5F8, // 70003ADA 
+0x0F122400, // 70003ADC 
+0x0F124D6D, // 70003ADE 
+0x0F12486D, // 70003AE0 
+0x0F12210E, // 70003AE2 
+0x0F128041, // 70003AE4 
+0x0F122101, // 70003AE6 
+0x0F128001, // 70003AE8 
+0x0F12F000, // 70003AEA 
+0x0F12F9AF, // 70003AEC 
+0x0F12486B, // 70003AEE 
+0x0F128840, // 70003AF0 
+0x0F12F000, // 70003AF2 
+0x0F12F9B3, // 70003AF4 
+0x0F124E6A, // 70003AF6 
+0x0F12270D, // 70003AF8 
+0x0F12073F, // 70003AFA 
+0x0F1219E8, // 70003AFC 
+0x0F128803, // 70003AFE 
+0x0F1200E2, // 70003B00 
+0x0F121991, // 70003B02 
+0x0F12804B, // 70003B04 
+0x0F128843, // 70003B06 
+0x0F1252B3, // 70003B08 
+0x0F128882, // 70003B0A 
+0x0F1280CA, // 70003B0C 
+0x0F1288C0, // 70003B0E 
+0x0F128088, // 70003B10 
+0x0F123508, // 70003B12 
+0x0F12042D, // 70003B14 
+0x0F120C2D, // 70003B16 
+0x0F121C64, // 70003B18 
+0x0F120424, // 70003B1A 
+0x0F120C24, // 70003B1C 
+0x0F122C07, // 70003B1E 
+0x0F12D3EC, // 70003B20 
+0x0F12E63D, // 70003B22 
+0x0F12B5F0, // 70003B24 
+0x0F12B085, // 70003B26 
+0x0F126801, // 70003B28 
+0x0F129103, // 70003B2A 
+0x0F126881, // 70003B2C 
+0x0F12040A, // 70003B2E 
+0x0F120C12, // 70003B30 
+0x0F12495C, // 70003B32 
+0x0F128B89, // 70003B34 
+0x0F122900, // 70003B36 
+0x0F12D001, // 70003B38 
+0x0F120011, // 70003B3A 
+0x0F12E000, // 70003B3C 
+0x0F122100, // 70003B3E 
+0x0F129102, // 70003B40 
+0x0F126840, // 70003B42 
+0x0F120401, // 70003B44 
+0x0F129803, // 70003B46 
+0x0F120C09, // 70003B48 
+0x0F12F000, // 70003B4A 
+0x0F12F98F, // 70003B4C 
+0x0F124854, // 70003B4E 
+0x0F123080, // 70003B50 
+0x0F128900, // 70003B52 
+0x0F122800, // 70003B54 
+0x0F12D039, // 70003B56 
+0x0F122100, // 70003B58 
+0x0F124854, // 70003B5A 
+0x0F124D52, // 70003B5C 
+0x0F124684, // 70003B5E 
+0x0F124B53, // 70003B60 
+0x0F124C4F, // 70003B62 
+0x0F1288DA, // 70003B64 
+0x0F120048, // 70003B66 
+0x0F1200D7, // 70003B68 
+0x0F12193E, // 70003B6A 
+0x0F12197F, // 70003B6C 
+0x0F12183F, // 70003B6E 
+0x0F125A36, // 70003B70 
+0x0F128AFF, // 70003B72 
+0x0F12437E, // 70003B74 
+0x0F1200B6, // 70003B76 
+0x0F120C37, // 70003B78 
+0x0F121906, // 70003B7A 
+0x0F123680, // 70003B7C 
+0x0F128177, // 70003B7E 
+0x0F121C52, // 70003B80 
+0x0F1200D2, // 70003B82 
+0x0F121914, // 70003B84 
+0x0F121952, // 70003B86 
+0x0F121812, // 70003B88 
+0x0F125A24, // 70003B8A 
+0x0F128AD2, // 70003B8C 
+0x0F124354, // 70003B8E 
+0x0F1200A2, // 70003B90 
+0x0F120C12, // 70003B92 
+0x0F128272, // 70003B94 
+0x0F12891C, // 70003B96 
+0x0F12895B, // 70003B98 
+0x0F124367, // 70003B9A 
+0x0F12435A, // 70003B9C 
+0x0F121943, // 70003B9E 
+0x0F123340, // 70003BA0 
+0x0F1289DB, // 70003BA2 
+0x0F129C02, // 70003BA4 
+0x0F1218BA, // 70003BA6 
+0x0F124363, // 70003BA8 
+0x0F1218D2, // 70003BAA 
+0x0F120212, // 70003BAC 
+0x0F120C12, // 70003BAE 
+0x0F12466B, // 70003BB0 
+0x0F12521A, // 70003BB2 
+0x0F124663, // 70003BB4 
+0x0F127DDB, // 70003BB6 
+0x0F12435A, // 70003BB8 
+0x0F129B03, // 70003BBA 
+0x0F120252, // 70003BBC 
+0x0F120C12, // 70003BBE 
+0x0F12521A, // 70003BC0 
+0x0F121C49, // 70003BC2 
+0x0F120409, // 70003BC4 
+0x0F120C09, // 70003BC6 
+0x0F122904, // 70003BC8 
+0x0F12D3C9, // 70003BCA 
+0x0F12B005, // 70003BCC 
+0x0F12BCF0, // 70003BCE 
+0x0F12BC08, // 70003BD0 
+0x0F124718, // 70003BD2 
+0x0F12B510, // 70003BD4 
+0x0F12F7FF, // 70003BD6 
+0x0F12FF80, // 70003BD8 
+0x0F12F000, // 70003BDA 
+0x0F12F94F, // 70003BDC 
+0x0F12E582, // 70003BDE 
+0x0F12B570, // 70003BE0 
+0x0F126804, // 70003BE2 
+0x0F12F000, // 70003BE4 
+0x0F12F952, // 70003BE6 
+0x0F124D32, // 70003BE8 
+0x0F128C29, // 70003BEA 
+0x0F121A40, // 70003BEC 
+0x0F1242A0, // 70003BEE 
+0x0F12D901, // 70003BF0 
+0x0F120020, // 70003BF2 
+0x0F12E003, // 70003BF4 
+0x0F12F000, // 70003BF6 
+0x0F12F949, // 70003BF8 
+0x0F128C29, // 70003BFA 
+0x0F121A40, // 70003BFC 
+0x0F126268, // 70003BFE 
+0x0F12F000, // 70003C00 
+0x0F12F94C, // 70003C02 
+0x0F1262A8, // 70003C04 
+0x0F12F000, // 70003C06 
+0x0F12F951, // 70003C08 
+0x0F126328, // 70003C0A 
+0x0F128869, // 70003C0C 
+0x0F122900, // 70003C0E 
+0x0F12D000, // 70003C10 
+0x0F1262A8, // 70003C12 
+0x0F124828, // 70003C14 
+0x0F126B00, // 70003C16 
+0x0F128C00, // 70003C18 
+0x0F122800, // 70003C1A 
+0x0F12D11B, // 70003C1C 
+0x0F126AA8, // 70003C1E 
+0x0F12F000, // 70003C20 
+0x0F12F94C, // 70003C22 
+0x0F1261E8, // 70003C24 
+0x0F124A1E, // 70003C26 
+0x0F123280, // 70003C28 
+0x0F128B91, // 70003C2A 
+0x0F122900, // 70003C2C 
+0x0F12D00B, // 70003C2E 
+0x0F120011, // 70003C30 
+0x0F123120, // 70003C32 
+0x0F128809, // 70003C34 
+0x0F124288, // 70003C36 
+0x0F12D907, // 70003C38 
+0x0F1261E9, // 70003C3A 
+0x0F128C28, // 70003C3C 
+0x0F121A08, // 70003C3E 
+0x0F1262A8, // 70003C40 
+0x0F12F000, // 70003C42 
+0x0F12F92B, // 70003C44 
+0x0F1262A8, // 70003C46 
+0x0F12E502, // 70003C48 
+0x0F128BD1, // 70003C4A 
+0x0F124288, // 70003C4C 
+0x0F12D800, // 70003C4E 
+0x0F120008, // 70003C50 
+0x0F1261E8, // 70003C52 
+0x0F12E4FC, // 70003C54 
+0x0F12F000, // 70003C56 
+0x0F12F919, // 70003C58 
+0x0F1261E8, // 70003C5A 
+0x0F12E4F8, // 70003C5C 
+0x0F12B510, // 70003C5E 
+0x0F12F000, // 70003C60 
+0x0F12F934, // 70003C62 
+0x0F12480E, // 70003C64 
+0x0F1230A0, // 70003C66 
+0x0F128841, // 70003C68 
+0x0F122900, // 70003C6A 
+0x0F12D007, // 70003C6C 
+0x0F124A07, // 70003C6E 
+0x0F123280, // 70003C70 
+0x0F126953, // 70003C72 
+0x0F124A11, // 70003C74 
+0x0F12428B, // 70003C76 
+0x0F12D202, // 70003C78 
+0x0F128880, // 70003C7A 
+0x0F1281D0, // 70003C7C 
+0x0F12E532, // 70003C7E 
+0x0F1288C0, // 70003C80 
+0x0F1281D0, // 70003C82 
+0x0F12E52F, // 70003C84 
+0x0F120000, // 70003C86 
+0x0F1231A0, // 70003C88 
+0x0F127000, // 70003C8A 
+0x0F1229E4, // 70003C8C 
+0x0F127000, // 70003C8E 
+0x0F12C100, // 70003C90 
+0x0F12D000, // 70003C92 
+0x0F12A006, // 70003C94 
+0x0F120000, // 70003C96 
+0x0F12A000, // 70003C98 
+0x0F12D000, // 70003C9A 
+0x0F12064C, // 70003C9C 
+0x0F127000, // 70003C9E 
+0x0F123F48, // 70003CA0 
+0x0F127000, // 70003CA2 
+0x0F1207C4, // 70003CA4 
+0x0F127000, // 70003CA6 
+0x0F1207E8, // 70003CA8 
+0x0F127000, // 70003CAA 
+0x0F122B24, // 70003CAC 
+0x0F127000, // 70003CAE 
+0x0F121FA0, // 70003CB0 
+0x0F127000, // 70003CB2 
+0x0F121E3C, // 70003CB4 
+0x0F127000, // 70003CB6 
+0x0F1221A4, // 70003CB8 
+0x0F127000, // 70003CBA 
+0x0F12E200, // 70003CBC 
+0x0F12D000, // 70003CBE 
+0x0F124778, // 70003CC0 
+0x0F1246C0, // 70003CC2 
+0x0F12C000, // 70003CC4 
+0x0F12E59F, // 70003CC6 
+0x0F12FF1C, // 70003CC8 
+0x0F12E12F, // 70003CCA 
+0x0F121F63, // 70003CCC 
+0x0F120001, // 70003CCE 
+0x0F124778, // 70003CD0 
+0x0F1246C0, // 70003CD2 
+0x0F12C000, // 70003CD4 
+0x0F12E59F, // 70003CD6 
+0x0F12FF1C, // 70003CD8 
+0x0F12E12F, // 70003CDA 
+0x0F121EDF, // 70003CDC 
+0x0F120001, // 70003CDE 
+0x0F124778, // 70003CE0 
+0x0F1246C0, // 70003CE2 
+0x0F12C000, // 70003CE4 
+0x0F12E59F, // 70003CE6 
+0x0F12FF1C, // 70003CE8 
+0x0F12E12F, // 70003CEA 
+0x0F12495F, // 70003CEC 
+0x0F120000, // 70003CEE 
+0x0F124778, // 70003CF0 
+0x0F1246C0, // 70003CF2 
+0x0F12C000, // 70003CF4 
+0x0F12E59F, // 70003CF6 
+0x0F12FF1C, // 70003CF8 
+0x0F12E12F, // 70003CFA 
+0x0F12E403, // 70003CFC 
+0x0F120000, // 70003CFE 
+0x0F124778, // 70003D00 
+0x0F1246C0, // 70003D02 
+0x0F12C000, // 70003D04 
+0x0F12E59F, // 70003D06 
+0x0F12FF1C, // 70003D08 
+0x0F12E12F, // 70003D0A 
+0x0F1224B3, // 70003D0C 
+0x0F120001, // 70003D0E 
+0x0F124778, // 70003D10 
+0x0F1246C0, // 70003D12 
+0x0F12C000, // 70003D14 
+0x0F12E59F, // 70003D16 
+0x0F12FF1C, // 70003D18 
+0x0F12E12F, // 70003D1A 
+0x0F12EECD, // 70003D1C 
+0x0F120000, // 70003D1E 
+0x0F124778, // 70003D20 
+0x0F1246C0, // 70003D22 
+0x0F12C000, // 70003D24 
+0x0F12E59F, // 70003D26 
+0x0F12FF1C, // 70003D28 
+0x0F12E12F, // 70003D2A 
+0x0F12F049, // 70003D2C 
+0x0F120000, // 70003D2E 
+0x0F124778, // 70003D30 
+0x0F1246C0, // 70003D32 
+0x0F12C000, // 70003D34 
+0x0F12E59F, // 70003D36 
+0x0F12FF1C, // 70003D38 
+0x0F12E12F, // 70003D3A 
+0x0F1212DF, // 70003D3C 
+0x0F120000, // 70003D3E 
+0x0F124778, // 70003D40 
+0x0F1246C0, // 70003D42 
+0x0F12C000, // 70003D44 
+0x0F12E59F, // 70003D46 
+0x0F12FF1C, // 70003D48 
+0x0F12E12F, // 70003D4A 
+0x0F12F05B, // 70003D4C 
+0x0F120000, // 70003D4E 
+0x0F124778, // 70003D50 
+0x0F1246C0, // 70003D52 
+0x0F12C000, // 70003D54 
+0x0F12E59F, // 70003D56 
+0x0F12FF1C, // 70003D58 
+0x0F12E12F, // 70003D5A 
+0x0F12F07B, // 70003D5C 
+0x0F120000, // 70003D5E 
+0x0F124778, // 70003D60 
+0x0F1246C0, // 70003D62 
+0x0F12C000, // 70003D64 
+0x0F12E59F, // 70003D66 
+0x0F12FF1C, // 70003D68 
+0x0F12E12F, // 70003D6A 
+0x0F12FE6D, // 70003D6C 
+0x0F120000, // 70003D6E 
+0x0F124778, // 70003D70 
+0x0F1246C0, // 70003D72 
+0x0F12C000, // 70003D74 
+0x0F12E59F, // 70003D76 
+0x0F12FF1C, // 70003D78 
+0x0F12E12F, // 70003D7A 
+0x0F123295, // 70003D7C 
+0x0F120000, // 70003D7E 
+0x0F124778, // 70003D80 
+0x0F1246C0, // 70003D82 
+0x0F12C000, // 70003D84 
+0x0F12E59F, // 70003D86 
+0x0F12FF1C, // 70003D88 
+0x0F12E12F, // 70003D8A 
+0x0F12234F, // 70003D8C 
+0x0F120000, // 70003D8E 
+0x0F124778, // 70003D90 
+0x0F1246C0, // 70003D92 
+0x0F12C000, // 70003D94 
+0x0F12E59F, // 70003D96 
+0x0F12FF1C, // 70003D98 
+0x0F12E12F, // 70003D9A 
+0x0F124521, // 70003D9C 
+0x0F120000, // 70003D9E 
+0x0F124778, // 70003DA0 
+0x0F1246C0, // 70003DA2 
+0x0F12C000, // 70003DA4 
+0x0F12E59F, // 70003DA6 
+0x0F12FF1C, // 70003DA8 
+0x0F12E12F, // 70003DAA 
+0x0F127C0D, // 70003DAC 
+0x0F120000, // 70003DAE 
+0x0F124778, // 70003DB0 
+0x0F1246C0, // 70003DB2 
+0x0F12C000, // 70003DB4 
+0x0F12E59F, // 70003DB6 
+0x0F12FF1C, // 70003DB8 
+0x0F12E12F, // 70003DBA 
+0x0F127C2B, // 70003DBC 
+0x0F120000, // 70003DBE 
+0x0F124778, // 70003DC0 
+0x0F1246C0, // 70003DC2 
+0x0F12F004, // 70003DC4 
+0x0F12E51F, // 70003DC6 
+0x0F1224C4, // 70003DC8 
+0x0F120001, // 70003DCA 
+0x0F124778, // 70003DCC 
+0x0F1246C0, // 70003DCE 
+0x0F12C000, // 70003DD0 
+0x0F12E59F, // 70003DD2 
+0x0F12FF1C, // 70003DD4 
+0x0F12E12F, // 70003DD6 
+0x0F123183, // 70003DD8 
+0x0F120000, // 70003DDA 
+0x0F124778, // 70003DDC 
+0x0F1246C0, // 70003DDE 
+0x0F12C000, // 70003DE0 
+0x0F12E59F, // 70003DE2 
+0x0F12FF1C, // 70003DE4 
+0x0F12E12F, // 70003DE6 
+0x0F12302F, // 70003DE8 
+0x0F120000, // 70003DEA 
+0x0F124778, // 70003DEC 
+0x0F1246C0, // 70003DEE 
+0x0F12C000, // 70003DF0 
+0x0F12E59F, // 70003DF2 
+0x0F12FF1C, // 70003DF4 
+0x0F12E12F, // 70003DF6 
+0x0F12EF07, // 70003DF8 
+0x0F120000, // 70003DFA 
+0x0F124778, // 70003DFC 
+0x0F1246C0, // 70003DFE 
+0x0F12C000, // 70003E00 
+0x0F12E59F, // 70003E02 
+0x0F12FF1C, // 70003E04 
+0x0F12E12F, // 70003E06 
+0x0F1248FB, // 70003E08 
+0x0F120000, // 70003E0A 
+0x0F124778, // 70003E0C 
+0x0F1246C0, // 70003E0E 
+0x0F12C000, // 70003E10 
+0x0F12E59F, // 70003E12 
+0x0F12FF1C, // 70003E14 
+0x0F12E12F, // 70003E16 
+0x0F12F0B1, // 70003E18 
+0x0F120000, // 70003E1A 
+0x0F124778, // 70003E1C 
+0x0F1246C0, // 70003E1E 
+0x0F12C000, // 70003E20 
+0x0F12E59F, // 70003E22 
+0x0F12FF1C, // 70003E24 
+0x0F12E12F, // 70003E26 
+0x0F12EEDF, // 70003E28 
+0x0F120000, // 70003E2A 
+0x0F124778, // 70003E2C 
+0x0F1246C0, // 70003E2E 
+0x0F12C000, // 70003E30 
+0x0F12E59F, // 70003E32 
+0x0F12FF1C, // 70003E34 
+0x0F12E12F, // 70003E36 
+0x0F12AEF1, // 70003E38 
+0x0F120000, // 70003E3A 
+0x0F124778, // 70003E3C 
+0x0F1246C0, // 70003E3E 
+0x0F12C000, // 70003E40 
+0x0F12E59F, // 70003E42 
+0x0F12FF1C, // 70003E44 
+0x0F12E12F, // 70003E46 
+0x0F1202EB, // 70003E48 
+0x0F120001, // 70003E4A 
+0x0F124778, // 70003E4C 
+0x0F1246C0, // 70003E4E 
+0x0F12C000, // 70003E50 
+0x0F12E59F, // 70003E52 
+0x0F12FF1C, // 70003E54 
+0x0F12E12F, // 70003E56 
+0x0F12FD21, // 70003E58 
+0x0F120000, // 70003E5A 
+0x0F124778, // 70003E5C 
+0x0F1246C0, // 70003E5E 
+0x0F12C000, // 70003E60 
+0x0F12E59F, // 70003E62 
+0x0F12FF1C, // 70003E64 
+0x0F12E12F, // 70003E66 
+0x0F12FDAF, // 70003E68 
+0x0F120000, // 70003E6A 
+0x0F124778, // 70003E6C 
+0x0F1246C0, // 70003E6E 
+0x0F12C000, // 70003E70 
+0x0F12E59F, // 70003E72 
+0x0F12FF1C, // 70003E74 
+0x0F12E12F, // 70003E76 
+0x0F125027, // 70003E78 
+0x0F120000, // 70003E7A 
+0x0F124778, // 70003E7C 
+0x0F1246C0, // 70003E7E 
+0x0F12C000, // 70003E80 
+0x0F12E59F, // 70003E82 
+0x0F12FF1C, // 70003E84 
+0x0F12E12F, // 70003E86 
+0x0F1204C9, // 70003E88 
+0x0F120000, // 70003E8A 
+0x0F124778, // 70003E8C 
+0x0F1246C0, // 70003E8E 
+0x0F12C000, // 70003E90 
+0x0F12E59F, // 70003E92 
+0x0F12FF1C, // 70003E94 
+0x0F12E12F, // 70003E96 
+0x0F1239DF, // 70003E98 
+0x0F120000, // 70003E9A 
+0x0F124778, // 70003E9C 
+0x0F1246C0, // 70003E9E 
+0x0F12C000, // 70003EA0 
+0x0F12E59F, // 70003EA2 
+0x0F12FF1C, // 70003EA4 
+0x0F12E12F, // 70003EA6 
+0x0F126177, // 70003EA8 
+0x0F120000, // 70003EAA 
+0x0F124778, // 70003EAC 
+0x0F1246C0, // 70003EAE 
+0x0F12C000, // 70003EB0 
+0x0F12E59F, // 70003EB2 
+0x0F12FF1C, // 70003EB4 
+0x0F12E12F, // 70003EB6 
+0x0F12424F, // 70003EB8 
+0x0F120000, // 70003EBA 
+0x0F124778, // 70003EBC 
+0x0F1246C0, // 70003EBE 
+0x0F12C000, // 70003EC0 
+0x0F12E59F, // 70003EC2 
+0x0F12FF1C, // 70003EC4 
+0x0F12E12F, // 70003EC6 
+0x0F123F0D, // 70003EC8 
+0x0F120000, // 70003ECA 
+0x0F124778, // 70003ECC 
+0x0F1246C0, // 70003ECE 
+0x0F12C000, // 70003ED0 
+0x0F12E59F, // 70003ED2 
+0x0F12FF1C, // 70003ED4 
+0x0F12E12F, // 70003ED6 
+0x0F1202B9, // 70003ED8 
+0x0F120001, // 70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007,// clks_src_gf_force_enable
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120000, //on/off AFIT by NB option
+
+0x0F120005, //NormBR[0]
+0x0F120019, //NormBR[1]
+0x0F120050, //NormBR[2]
+0x0F120300, //NormBR[3]
+0x0F120375, //NormBR[4]
+
+// Flash
+0x002A3F82,
+0x0F120000,	//TNP_Regs_PreflashStart
+0x0F120000,	//TNP_Regs_PreflashEnd
+0x0F120260,	//TNP_Regs_PreWP_r
+0x0F120240, //TNP_Regs_PreWP_b
+
+0x002A3F98,	//BR Tuning
+0x0F120100,	//TNP_Regs_BrRatioIn_0_
+0x0F120150,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120100,	//TNP_Regs_BrRatioOut_0_
+0x0F1200A0,
+0x0F120080,
+0x0F120040,
+0x0F120020,
+
+0x0F120030,	//WP Tuning
+0x0F120040,	//TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	//TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	//T_BR tune	
+0x0F120150,	//TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B,
+0x0F12002E,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120235, //0244 0258 AWB R point          //0258 0245 0258
+0x0F12024A, //024D 0220 AWB B point          //0220 0245 0245
+
+
+//         //         //         //         //         //         //         //         //   
+// Analog & APS settings         //         //         //         //         //         //   
+// This register is for FACTORY ONLY. If you change it without prior notification         //
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //  
+//         //         //         //         //         //         //         //         //   
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshadi
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, //analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, //ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, //cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, //adc_sat[7:0]=84d (500mV)
+0x0F120002, //ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, //rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, //msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, //rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, //dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, //comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, //pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, //clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001, //ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp
+
+0x002AF42E,
+0x0F120406, //fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg
+
+0x002AF434,
+0x0F120003, //dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, //reg_tune_pix[7:0]
+0x0F120002, //reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, //reg_tune_rg[7:0] (2.83V)
+0x0F120004, //reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, //blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, //srx_en[0]
+
+0x002A0054,
+0x0F120028, //pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, //div_dbr[7:4]
+
+0x002AF132,
+0x0F120206, //tgr_frame_decription 4
+0x002AF152,
+0x0F120206, //tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, //tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, //tgr_frame_params_descriptor_6
+//===========================================================================================
+
+//============================= Line-ADLC Tuning ============================================
+0x002AE412,
+0x0F120008, //adlc_tune_offset_gr[7:0]
+0x0F120008, //adlc_tune_offset_r[7:0]
+0x0F120010, //adlc_tune_offset_b[7:0]
+0x0F120010, //adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, //adlc_qec[2:0]
+//===========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F120132, //0138//awbb_IntcR
+0x0F12010A, //011C//awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041, //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C, //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for S
+0x0F120190, //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000//#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120003, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120602, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120003, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200CC, //#af_search_usPeakThr  for 80%
+0x0F1200A0, //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F12952F, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120010, //#af_pos_usTableLastInd 10h + 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120033, //#af_pos_usTable_1_  51   
+0x0F120036, //#af_pos_usTable_2_  54	
+0x0F120039, //#af_pos_usTable_3_  57	
+0x0F12003D, //#af_pos_usTable_4_  61   
+0x0F120041, //#af_pos_usTable_5_  65	
+0x0F120045, //#af_pos_usTable_6_  69	
+0x0F120049, //#af_pos_usTable_7_  73	
+0x0F12004E, //#af_pos_usTable_8_  78	
+0x0F120053, //#af_pos_usTable_9_  83	
+0x0F120059, //#af_pos_usTable_10_ 89	
+0x0F120060, //#af_pos_usTable_11_ 104	
+0x0F120068, //#af_pos_usTable_12_ 109	
+0x0F120072, //#af_pos_usTable_13_ 114	
+0x0F12007D, //#af_pos_usTable_14_ 125
+0x0F120089, //#af_pos_usTable_15_ 137	
+0x0F120096, //#af_pos_usTable_16_ 150
+
+//8. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120020, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120008, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120008, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is
+0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : M
+0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with A
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12005C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000,//senHal_bSRX//SRX off
+
+0x002A1680,
+0x0F120002,//senHal_NExpLinesCheckFine//0004            
+
+0x002A0ED2,
+0x0F120FA0,//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PL
+0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK   
+0x002A0188,
+0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+0x0F120000, //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001, //REG_TC_IPRM_UseNPviClocks
+0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll by
+
+
+//SCLK & PCLK  // clock set 0
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+//SCLK & PCLK // clock set 1
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+//SCLK & PCLK // clock set 2                                              
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+0x002A1B78,
+0x0F1238A4, //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_0__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4, //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_1__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4, //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_2__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A, //p10
+
+
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6,
+0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 640 480 system 52M PCLK 87M
+//===================================================================
+0x002A023E,
+0x0F120500, //REG_0TC_PCFG_usWidth
+0x0F120400, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+          
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+          
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+0x0F120535, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a
+0x0F12029A, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+0x0F120003, //REG_0TC_PCFG_uPrevMirror
+0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 87M
+//===================================================================
+
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV
+0x0F1254F6,	//REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_CCFG_usMinOut4KHzRate
+
+0x002A033E,
+0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+0x002A0346,
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120000,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F00,
+0x0F120000,
+0x0F120F0F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+
+// TVAR_ash_pGAS_low
+0x0F126E49,
+0x0F12FB98,
+0x0F12F348,
+0x0F121BD6,
+0x0F12EBEF,
+0x0F1203D3,
+0x0F12EC8D,
+0x0F12F239,
+0x0F120E64,
+0x0F12F7EA,
+0x0F12FD3B,
+0x0F120A7C,
+0x0F12FC9C,
+0x0F120BD3,
+0x0F12F2E5,
+0x0F120619,
+0x0F120772,
+0x0F12F0B0,
+0x0F12184E,
+0x0F12F95F,
+0x0F120B1A,
+0x0F12FC45,
+0x0F12F716,
+0x0F120DCD,
+0x0F12EF24,
+0x0F120221,
+0x0F12F6BD,
+0x0F1204CB,
+0x0F1200B1,
+0x0F12FEB0,
+0x0F120268,
+0x0F1202C7,
+0x0F12010A,
+0x0F12FF93,
+0x0F12036D,
+0x0F12F859,
+0x0F1281D0,
+0x0F12FA32,
+0x0F12EFDB,
+0x0F12234D,
+0x0F12E799,
+0x0F120337,
+0x0F12EB05,
+0x0F12E8F9,
+0x0F12152E,
+0x0F12F0D5,
+0x0F120842,
+0x0F12043A,
+0x0F12F461,
+0x0F120E58,
+0x0F12F658,
+0x0F12075D,
+0x0F12F78D,
+0x0F12FDE9,
+0x0F12277A,
+0x0F12FFDE,
+0x0F12FD3B,
+0x0F12FE50,
+0x0F120AD1,
+0x0F12FE2C,
+0x0F12E90D,
+0x0F12F7B0,
+0x0F1205DB,
+0x0F1202CD,
+0x0F12F4F1,
+0x0F1202A8,
+0x0F12FDDC,
+0x0F120B59,
+0x0F12F74E,
+0x0F1203D5,
+0x0F12FF4F,
+0x0F1200F7,
+0x0F126A44,
+0x0F12FAD6,
+0x0F12F261,
+0x0F121F28,
+0x0F12E691,
+0x0F1207D2,
+0x0F12EE85,
+0x0F12F426,
+0x0F120F26,
+0x0F12F34B,
+0x0F120036,
+0x0F120C0F,
+0x0F12FDA9,
+0x0F1209EA,
+0x0F12F27A,
+0x0F120CD5,
+0x0F1201E1,
+0x0F12ED41,
+0x0F121DB5,
+0x0F12FD26,
+0x0F1203F7,
+0x0F12F7BB,
+0x0F12FE81,
+0x0F1212D3,
+0x0F12E061,
+0x0F12F81C,
+0x0F1207B1,
+0x0F120408,
+0x0F12F860,
+0x0F12FC9A,
+0x0F120DDE,
+0x0F120C9C,
+0x0F12F2A4,
+0x0F1202EB,
+0x0F12099B,
+0x0F12F5A6,
+0x0F127243,
+0x0F12F74D,
+0x0F12F74B,
+0x0F121800,
+0x0F12EF22,
+0x0F120263,
+0x0F12EBE7,
+0x0F12F5A4,
+0x0F1209D3,
+0x0F12FAB8,
+0x0F12FDFF,
+0x0F12086B,
+0x0F120338,
+0x0F120514,
+0x0F12F840,
+0x0F120768,
+0x0F12FE55,
+0x0F12F884,
+0x0F121488,
+0x0F12FFCD,
+0x0F12035B,
+0x0F12FA4E,
+0x0F1201DB,
+0x0F1206D6,
+0x0F12EE19,
+0x0F12FEA3,
+0x0F12FE8C,
+0x0F1203A3,
+0x0F12FDDB,
+0x0F12FD9B,
+0x0F12035E,
+0x0F1203F2,
+0x0F12FCBD,
+0x0F120300,
+0x0F12FF2E,
+0x0F12FE03,
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F123F00,	//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[0][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[0][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[0][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[0][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[0][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[0][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[0][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[0][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[0][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[0][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[0][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[0][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[0][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[0][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[0][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[0][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[0][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[0][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[1][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[1][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[1][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[1][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[1][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[1][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[1][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[1][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[1][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[1][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[1][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[1][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[1][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[1][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[1][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[1][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[1][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[1][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[2][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[2][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[2][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[2][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[2][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[2][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[2][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[2][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[2][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[2][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[2][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[2][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[2][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[2][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[2][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[2][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[2][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[2][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[2][19]
+
+//s002A06D8
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR//MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Nigh
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight 
+
+//AE_state
+0x002A04EE,
+0x0F12010E, //#lt_uLimitHigh
+0x0F1200F5, //#lt_uLimitLow
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //#lt_uMaxExp1
+0x002A0508,
+0x0F12681F, //#lt_uMaxExp2
+0x002A050C,
+0x0F128227, //#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F12681F, //#lt_uCapMaxExp2
+0x002A051C,
+0x0F128227, //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F1201E0, //#lt_uMaxAnGain1
+0x0F1201E0, //#lt_uMaxAnGain2
+0x0F120300, //#lt_uMaxAnGain3
+0x0F120710, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F1201E0, //#lt_uCapMaxAnGain1
+0x0F1201E0, //#lt_uCapMaxAnGain2
+0x0F120300, //#lt_uCapMaxAnGain3
+0x0F120710, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,
+0x0F120000, //ae_WeightTbl_16[0]
+0x0F120000, //ae_WeightTbl_16[1]
+0x0F120000, //ae_WeightTbl_16[2]
+0x0F120000, //ae_WeightTbl_16[3]
+0x0F120101, //ae_WeightTbl_16[4]
+0x0F120101, //ae_WeightTbl_16[5]
+0x0F120101, //ae_WeightTbl_16[6]
+0x0F120101, //ae_WeightTbl_16[7]
+0x0F120101, //ae_WeightTbl_16[8]
+0x0F120201, //ae_WeightTbl_16[9]
+0x0F120102, //ae_WeightTbl_16[10]
+0x0F120101, //ae_WeightTbl_16[11]
+0x0F120101, //ae_WeightTbl_16[12]
+0x0F120202, //ae_WeightTbl_16[13]
+0x0F120202, //ae_WeightTbl_16[14]
+0x0F120101, //ae_WeightTbl_16[15]
+0x0F120101, //ae_WeightTbl_16[16]
+0x0F120202, //ae_WeightTbl_16[17]
+0x0F120202, //ae_WeightTbl_16[18]
+0x0F120101, //ae_WeightTbl_16[19]
+0x0F120201, //ae_WeightTbl_16[20]
+0x0F120202, //ae_WeightTbl_16[21]
+0x0F120202, //ae_WeightTbl_16[22]
+0x0F120102, //ae_WeightTbl_16[23]
+0x0F120201, //ae_WeightTbl_16[24]
+0x0F120202, //ae_WeightTbl_16[25]
+0x0F120202, //ae_WeightTbl_16[26]
+0x0F120102, //ae_WeightTbl_16[27]
+0x0F120101, //ae_WeightTbl_16[28]
+0x0F120101, //ae_WeightTbl_16[29]
+0x0F120101, //ae_WeightTbl_16[30]
+0x0F120101, //ae_WeightTbl_16[31]
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F1205F0, //awbb_GamutWidthThr1
+0x0F1201F4, //awbb_GamutHeightThr1
+0x0F12006C, //awbb_GamutWidthThr2
+0x0F120038, //awbb_GamutHeightThr2
+0x002A1020,
+0x0F12000C, //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A291A,
+0x0F120006, // #Mon_AWB_ByPassMode// [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+0x0F120008,	//001E//awbb_WpFilterMinThr
+0x0F120160,	//0190//awbb_WpFilterMaxThr
+0x0F1200A0, //awbb_WpFilterCoef
+0x0F120004, //awbb_WpFilterSize
+0x0F120001, //awbb_otp_disable
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //awbb_IndoorGrZones_m_Grid
+0x002A0F80,
+0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+0x002A0F7C,
+0x0F120010,
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+
+0x002A11A8,
+0x0F1202C8, //awbb_GridConst_1[0]
+0x0F120325, //awbb_GridConst_1[1]
+0x0F12038F, //awbb_GridConst_1[2]
+
+0x0F120F8E, //awbb_GridConst_2[0]
+0x0F1210B3, //awbb_GridConst_2[1]
+0x0F121136, //awbb_GridConst_2[2]
+0x0F121138, //awbb_GridConst_2[3]
+0x0F12118E, //awbb_GridConst_2[4]
+0x0F121213, //awbb_GridConst_2[5]
+
+0x0F1200A7, //awbb_GridCoeff_R_1
+0x0F1200C2, //awbb_GridCoeff_B_1
+0x0F1200BD, //awbb_GridCoeff_R_2
+0x0F1200AC, //awbb_GridCoeff_B_2
+
+0x002A1118,
+0x0F120050, //0032//awbb_GridCorr_R[0][0]
+0x0F120032, //0012//awbb_GridCorr_R[0][1]
+0x0F120032, //0012//awbb_GridCorr_R[0][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060, //0050//awbb_GridCorr_R[0][5]
+0x0F120050, //0032//awbb_GridCorr_R[1][0]
+0x0F120032, //0012//awbb_GridCorr_R[1][1]
+0x0F120032, //0012//awbb_GridCorr_R[1][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060, //0050//awbb_GridCorr_R[1][5]
+0x0F120050, //0032//awbb_GridCorr_R[2][0]
+0x0F120032, //0012//awbb_GridCorr_R[2][1]
+0x0F120032, //0012//awbb_GridCorr_R[2][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060, //0050//awbb_GridCorr_R[2][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+0x002A1160,
+0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+0x0F120000, //awbb_GridCorr_R_Out[0][2]
+0x0F120000, //awbb_GridCorr_R_Out[0][3]
+0x0F120000, //awbb_GridCorr_R_Out[0][4]
+0x0F120000, //awbb_GridCorr_R_Out[0][5]
+0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+0x0F120000, //awbb_GridCorr_R_Out[1][2]
+0x0F120000, //awbb_GridCorr_R_Out[1][3]
+0x0F120000, //awbb_GridCorr_R_Out[1][4]
+0x0F120000, //awbb_GridCorr_R_Out[1][5]
+0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+0x0F120000, //awbb_GridCorr_R_Out[2][2]
+0x0F120000, //awbb_GridCorr_R_Out[2][3]
+0x0F120000, //awbb_GridCorr_R_Out[2][4]
+0x0F120000, //awbb_GridCorr_R_Out[2][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+0x0F120000, //awbb_GridCorr_B_Out[0][2]
+0x0F120000, //awbb_GridCorr_B_Out[0][3]
+0x0F120000, //awbb_GridCorr_B_Out[0][4]
+0x0F120000, //awbb_GridCorr_B_Out[0][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+0x0F120000, //awbb_GridCorr_B_Out[1][2]
+0x0F120000, //awbb_GridCorr_B_Out[1][3]
+0x0F120000, //awbb_GridCorr_B_Out[1][4]
+0x0F120000, //awbb_GridCorr_B_Out[1][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+0x0F120000, //awbb_GridCorr_B_Out[2][2]
+0x0F120000, //awbb_GridCorr_B_Out[2][3]
+0x0F120000, //awbb_GridCorr_B_Out[2][4]
+0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0] 
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1] 
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2] 
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3] 
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[4] 
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5] 
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6] 
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7] 
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[8] 
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[9] 
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+0x0F12011D, //00F4//TVAR_wbt_pBaseCcms[72]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+0x0F12011D, //00F4//TVAR_wbt_pBaseCcms[90]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F120040, //4A //40 //4A //0049//#afit_uNoiseIndInDoor_0_
+0x0F120048, //48 //4E //005F//#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+0x002A08C0,
+0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700008C2 //AFIT16_CONTRAST
+0x0F120000, //0000//700008C4 //AFIT16_SATURATION
+0x0F120002, //0000//700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //0000//700008C8 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700008CA //AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700008CC 
+0x0F1203FF, //03FF//700008CE //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700008D0 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700008D2 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700008D4 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700008D6 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700008D8 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700008DA //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700008DC //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700008DE //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700008E0 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700008E2 //AFIT16_demsharpmix1_iTune
+0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C//700008EA//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008//700008EC//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700008EE//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700008F0//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700008F2//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700008F4//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700008F6//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//700008F8//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//700008FA//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//700008FC//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//700008FE//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000900//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000902//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000904//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205E8, //09E8//70000906//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000908//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//7000090A//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//7000090C//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F124000, //4000//7000090E
+0x0F127803, //7803//70000910
+0x0F123C50, //3C50//70000912
+0x0F12003C, //003C//70000914
+0x0F121E80, //1E80//70000916//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000918//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12000A, //000A//7000091A//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120000, //0000//7000091C//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F12120A, //120A//7000091E//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F121400, //0F00//70000920//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000922//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000924//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000926//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000928//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//7000092A//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//7000092C//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//7000092E//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000930//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000932
+0x0F120609, //0609//70000934
+0x0F122C07, //2C07//70000936
+0x0F12142C, //142C//70000938
+0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120880, //0880//7000093E//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120B50, //0B50//70000940//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000942//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000944//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000946//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124601, //4601//70000948//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F12A444, //C844//7000094A//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F1250A4, //50C8//7000094C//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//7000094E//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F120303, //0003//70000950//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F121001, //1C01//70000952//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120710, //0714//70000954//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121448, //1464//70000956//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F125A03, //5A04//70000958//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12281E, //3C1E//7000095A//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F12200F, //400F//7000095C//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//7000095E//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F121403, //1403//70000960//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F120114, //0114//70000962//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000964//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F124446, //4446//70000966//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F12646E, //646E//70000968//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//7000096A//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//7000096C//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120000, //0000//7000096E//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000970//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000972//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000974//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F120000, //0000//70000976//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000978//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//7000097A//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//7000097C//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F121414, //1414//7000097E//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000980//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F124601, //4601//70000982//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F126E44, //6E44//70000984//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122864, //2864//70000986//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000988//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F120003, //0003//7000098A//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E00, //1E00//7000098C//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//7000098E//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000990//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F120004, //0004//70000992//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F00, //0F00//70000994//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000996//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000998//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//7000099A//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//7000099C
+0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700009A0//AFIT16_CONTRAST
+0x0F120000, //0000//700009A2//AFIT16_SATURATION
+0x0F120002, //0000//700009A4//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700009A6//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700009A8//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700009AA
+0x0F1203FF, //03FF//700009AC//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700009AE//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700009B0//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700009B2//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700009B4//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700009B6//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700009B8//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700009BA//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700009BC//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700009BE//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700009C0//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E//700009C8//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//700009CA//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700009CC//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700009CE//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700009D0//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700009D2//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700009D4//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//700009D6//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//700009D8//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//700009DA//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//700009DC//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//700009DE//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//700009E0//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//700009E2//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205E8, //05E8//700009E4//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//700009E6//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//700009E8//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//700009EA//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000//700009EC
+0x0F125003, //5003//700009EE
+0x0F123228, //3228//700009F0
+0x0F120032, //0032//700009F2
+0x0F121E80, //1E80//700009F4//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//700009F6//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12000A, //000A//700009F8//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120000, //0000//700009FA//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F12120A, //120A//700009FC//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F121400, //1400//700009FE//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000A00//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000A02//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000A04//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000A06//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000A08//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000A0A//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000A0C//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000A0E//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000A10
+0x0F120609, //0609//70000A12
+0x0F122C07, //2C07//70000A14
+0x0F12142C, //142C//70000A16
+0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120580, //0580//70000A1C//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000A1E//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000A20//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000A22//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000A24//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000A26//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F12494B, //444B 494B//70000A28//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_i
+0x0F125044, //503C 5044//70000A2A//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosa
+0x0F120500, //0500//70000A2C//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F120603, //0503//70000A2E//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D03, //0D02//70000A30//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F12071E, //071E//70000A32//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121432, //1432//70000A34//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F125A01, //5A01//70000A36//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12281E, //281E//70000A38//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F12200F, //200F//70000A3A//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000A3C//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F121E03, //1E03//70000A3E//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F12011E, //011E//70000A40//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000A42//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F123A3C, //3A3C//70000A44//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F12585A, //585A//70000A46//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000A48//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000A4A//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120000, //0000//70000A4C//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000A4E//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000A50//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000A52//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F120000, //0000//70000A54//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000A56//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000A58//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000A5A//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F121E1E, //1E1E//70000A5C//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000A5E//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F123C01, //3C01//70000A60//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F125A3A, //5A3A//70000A62//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122858, //2858//70000A64//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000A66//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F120003, //0003//70000A68//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E00, //1E00//70000A6A//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//70000A6C//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000A6E//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F120004, //0004//70000A70//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F00, //0F00//70000A72//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000A74//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000A76//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000A78//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000A7A
+0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000A7E//AFIT16_CONTRAST
+0x0F120000, //0000//70000A80//AFIT16_SATURATION
+0x0F120000, //0000//70000A82//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000A84//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000A86//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000A88
+0x0F1203FF, //03FF//70000A8A//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000A8C//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000A8E//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000A90//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000A92//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000A94//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//70000A96//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000A98//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000A9A//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//70000A9C//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000A9E//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000AA6//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000AA8//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//70000AAA//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//70000AAC//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//70000AAE//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//70000AB0//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000AB2//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//70000AB4//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//70000AB6//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//70000AB8//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//70000ABA//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000ABC//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000ABE//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000AC0//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205DE, //05DE//70000AC2//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000AC4//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//70000AC6//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//70000AC8//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000ACA
+0x0F122803, //2803//70000ACC
+0x0F12261E, //261E//70000ACE
+0x0F120026, //0026//70000AD0
+0x0F121E80, //1E80//70000AD2//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000AD4//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12010A, //010A//70000AD6//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120001, //0001//70000AD8//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F123C0A, //3C0A//70000ADA//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F122300, //2300//70000ADC//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000ADE//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000AE0//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000AE2//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000AE4//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000AE6//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000AE8//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000AEA//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000AEC//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000AEE
+0x0F120609, //0609//70000AF0
+0x0F121C07, //1C07//70000AF2
+0x0F121014, //1014//70000AF4
+0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000AFA//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000AFC//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000AFE//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000B00//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000B02//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000B04//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F122A4B, //2A4B//70000B06//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F125020, //5020//70000B08//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//70000B0A//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F121C03, //1C03//70000B0C//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D0C, //0D0C//70000B0E//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120823, //0823//70000B10//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121428, //1428//70000B12//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F126401, //6401//70000B14//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12282D, //282D//70000B16//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F122012, //2012//70000B18//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000B1A//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F122803, //2803//70000B1C//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F120128, //0128//70000B1E//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000B20//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F122224, //2224//70000B22//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F123236, //3236//70000B24//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000B26//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000B28//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120410, //0410//70000B2A//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000B2C//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000B2E//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000B30//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F124050, //4050//70000B32//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000B34//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000B36//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000B38//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F122828, //2828//70000B3A//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000B3C//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F122401, //2401//70000B3E//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F123622, //3622//70000B40//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122832, //2832//70000B42//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000B44//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F121003, //1003//70000B46//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E04, //1E04//70000B48//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//70000B4A//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000B4C//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F125004, //5004//70000B4E//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F40, //0F40//70000B50//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000B52//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000B54//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000B56//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000B58
+0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000B5C//AFIT16_CONTRAST
+0x0F120000, //0000//70000B5E//AFIT16_SATURATION
+0x0F120000, //0000//70000B60//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000B62//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000B64//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000B66
+0x0F1203FF, //03FF//70000B68//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000B6A//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000B6C//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000B6E//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000B70//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000B72//AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8//70000B74//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000B76//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000B78//AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050//70000B7A//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000B7C//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000B84//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000B86//AFIT16_Sharpening_iHighSharpClamp
+0x0F12002D, //002D//70000B88//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//70000B8A//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12002D, //002D//70000B8C//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//70000B8E//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000B90//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//70000B92//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//70000B94//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//70000B96//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//70000B98//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000B9A//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000B9C//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000B9E//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205DE, //05DE//70000BA0//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000BA2//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//70000BA4//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//70000BA6//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000BA8
+0x0F122303, //2303//70000BAA
+0x0F12231A, //231A//70000BAC
+0x0F120023, //0023//70000BAE
+0x0F121E80, //1E80//70000BB0//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000BB2//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12010A, //010A//70000BB4//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120001, //0001//70000BB6//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F123C0A, //3C0A//70000BB8//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F122300, //2300//70000BBA//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000BBC//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000BBE//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000BC0//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121E10, //1E10//70000BC2//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000BC4//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000BC6//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000BC8//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120705, //0705//70000BCA//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120306, //0306//70000BCC
+0x0F120509, //0509//70000BCE
+0x0F122806, //2806//70000BD0
+0x0F121428, //1428//70000BD2
+0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000BD8//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000BDA//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000BDC//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000BDE//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000BE0//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000BE2//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F122A4B, //2A4B//70000BE4//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F125020, //5020//70000BE6//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//70000BE8//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F121C03, //1C03//70000BEA//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D0C, //0D0C//70000BEC//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120823, //0823//70000BEE//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121428, //1428//70000BF0//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F126401, //6401//70000BF2//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12282D, //282D//70000BF4//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F122012, //2012//70000BF6//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000BF8//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F123C03, //3C03//70000BFA//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F12013C, //013C//70000BFC//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000BFE//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F121C1E, //1C1E//70000C00//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F121E22, //1E22//70000C02//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000C04//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000C06//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120214, //0214//70000C08//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F120E14, //0E14//70000C0A//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF06, //FF06//70000C0C//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000C0E//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F124052, //4052//70000C10//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F12150C, //150C//70000C12//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000C14//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000C16//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F123C3C, //3C3C//70000C18//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000C1A//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F121E01, //1E01//70000C1C//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F12221C, //221C//70000C1E//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F12281E, //281E//70000C20//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000C22//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F121403, //1403//70000C24//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121402, //1402//70000C26//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F12060E, //060E//70000C28//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000C2A//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F125204, //5204//70000C2C//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120C40, //0C40//70000C2E//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F124015, //4015//70000C30//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000C32//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000C34//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000C36
+0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//0000//70000C44
+0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:
+0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:
+0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed
+0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshL
+0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThres
+0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePow
+0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower
+0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHigh
+0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlope
+0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]                      
+0x0F121000, //1000//1000//70000C86        
+0x0F122003, //2003//2003//70000C88        
+0x0F121020, //1020//1020//70000C8A        
+0x0F120010, //0010//0010//70000C8C        
+0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonoc
+0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_
+0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDe
+0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iN
+0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_
+0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharp
+0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpW
+0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iS
+0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1
+0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoef
+0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNar
+0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_i
+0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHy
+0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_
+0x0F120305, //0305//0305//70000CAA        
+0x0F120609, //0609//0609//70000CAC        
+0x0F122C07, //2C07//2C07//70000CAE        
+0x0F12142C, //142C//142C//70000CB0        
+0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]  
+0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkRe
+0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset
+0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation 
+0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThr
+0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT
+0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Lo
+0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshL
+0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdg
+0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaic
+0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing
+0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicin
+0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicin
+0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iD
+0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_i
+0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_
+0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_
+0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmi
+0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iC
+0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClu
+0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClust
+0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_H
+0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenT
+0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing
+0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demo
+0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosai
+0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosa
+0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_
+0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaici
+0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpeni
+0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpenin
+0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Shar
+0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsh
+0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClu
+0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClus
+0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_Disp
+0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenTh
+0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing
+0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demo
+0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demos
+0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demos
+0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosa
+0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaici
+0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpen
+0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpe
+0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpen
+0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsh
+0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//0001//70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F122102, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+};
+
+#ifdef CONFIG_MACH_P8LTE
+#define S5K5CCGX_720P_INIT_REG s5k5ccgx_1280_720_Preview_60hz
+/* anti-flicker 60Hz for LTE */
+static const u32 s5k5ccgx_1280_720_Preview_60hz[] = {
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000                            //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A, //p10
+// Start of Patch data
+// Start of Patch data
+0x00287000,
+0x002A352C,
+0x0F12B570, //7000352C 
+0x0F124A24, //7000352E 
+0x0F124924, //70003530 
+0x0F124825, //70003532 
+0x0F124B25, //70003534 
+0x0F122500, //70003536 
+0x0F12801D, //70003538 
+0x0F12C004, //7000353A 
+0x0F126001, //7000353C 
+0x0F124924, //7000353E 
+0x0F124824, //70003540 
+0x0F12F000, //70003542 
+0x0F12FBBD, //70003544 
+0x0F124924, //70003546 
+0x0F124824, //70003548 
+0x0F12F000, //7000354A 
+0x0F12FBB9, //7000354C 
+0x0F124824, //7000354E 
+0x0F124E24, //70003550 
+0x0F126430, //70003552 
+0x0F124924, //70003554 
+0x0F124825, //70003556 
+0x0F12F000, //70003558 
+0x0F12FBB2, //7000355A 
+0x0F124924, //7000355C 
+0x0F120030, //7000355E 
+0x0F123080, //70003560 
+0x0F126141, //70003562 
+0x0F124C23, //70003564 
+0x0F128365, //70003566 
+0x0F124923, //70003568 
+0x0F124824, //7000356A 
+0x0F12F000, //7000356C 
+0x0F12FBA8, //7000356E 
+0x0F124923, //70003570 
+0x0F124824, //70003572 
+0x0F12F000, //70003574 
+0x0F12FBA4, //70003576 
+0x0F124923, //70003578 
+0x0F124824, //7000357A 
+0x0F12F000, //7000357C 
+0x0F12FBA0, //7000357E 
+0x0F124923, //70003580 
+0x0F124824, //70003582 
+0x0F12F000, //70003584 
+0x0F12FB9C, //70003586 
+0x0F128125, //70003588 
+0x0F124923, //7000358A 
+0x0F124823, //7000358C 
+0x0F12F000, //7000358E 
+0x0F12FB97, //70003590 
+0x0F124923, //70003592 
+0x0F124823, //70003594 
+0x0F12F000, //70003596 
+0x0F12FB93, //70003598 
+0x0F1283A5, //7000359A 
+0x0F124922, //7000359C 
+0x0F124823, //7000359E 
+0x0F12F000, //700035A0 
+0x0F12FB8E, //700035A2 
+0x0F122101, //700035A4 
+0x0F120349, //700035A6 
+0x0F120020, //700035A8 
+0x0F123020, //700035AA 
+0x0F128041, //700035AC 
+0x0F122185, //700035AE 
+0x0F128081, //700035B0 
+0x0F12491F, //700035B2 
+0x0F1280C1, //700035B4 
+0x0F12481F, //700035B6 
+0x0F126730, //700035B8 
+0x0F12BC70, //700035BA 
+0x0F12BC08, //700035BC 
+0x0F124718, //700035BE 
+0x0F1200CA, //700035C0 
+0x0F125CC1, //700035C2 
+0x0F1203BD, //700035C4 
+0x0F120000, //700035C6 
+0x0F121C08, //700035C8 
+0x0F127000, //700035CA 
+0x0F123290, //700035CC 
+0x0F127000, //700035CE 
+0x0F123657, //700035D0 
+0x0F127000, //700035D2 
+0x0F12D9E7, //700035D4 
+0x0F120000, //700035D6 
+0x0F12383F, //700035D8 
+0x0F127000, //700035DA 
+0x0F12395D, //700035DC 
+0x0F120000, //700035DE 
+0x0F1238D1, //700035E0 
+0x0F127000, //700035E2 
+0x0F120000, //700035E4 
+0x0F127000, //700035E6 
+0x0F12399D, //700035E8 
+0x0F127000, //700035EA 
+0x0F12F903, //700035EC 
+0x0F120000, //700035EE 
+0x0F123AC1, //700035F0 
+0x0F127000, //700035F2 
+0x0F123FC8, //700035F4 
+0x0F127000, //700035F6 
+0x0F12368F, //700035F8 
+0x0F127000, //700035FA 
+0x0F12495F, //700035FC 
+0x0F120000, //700035FE 
+0x0F1236ED, //70003600 
+0x0F127000, //70003602 
+0x0F12E421, //70003604 
+0x0F120000, //70003606 
+0x0F1237AB, //70003608 
+0x0F127000, //7000360A 
+0x0F12216D, //7000360C 
+0x0F120000, //7000360E 
+0x0F12381F, //70003610 
+0x0F127000, //70003612 
+0x0F120179, //70003614 
+0x0F120001, //70003616 
+0x0F123BD5, //70003618 
+0x0F127000, //7000361A 
+0x0F1204C9, //7000361C 
+0x0F120000, //7000361E 
+0x0F123B25, //70003620 
+0x0F127000, //70003622 
+0x0F125027, //70003624 
+0x0F120000, //70003626 
+0x0F123BE1, //70003628 
+0x0F127000, //7000362A 
+0x0F1242B7, //7000362C 
+0x0F120000, //7000362E 
+0x0F1207FF, //70003630 
+0x0F120000, //70003632 
+0x0F123C5F, //70003634 
+0x0F127000, //70003636 
+0x0F12B570, //70003638 
+0x0F12000D, //7000363A 
+0x0F124CFC, //7000363C 
+0x0F128821, //7000363E 
+0x0F12F000, //70003640 
+0x0F12FB46, //70003642 
+0x0F128820, //70003644 
+0x0F124AFB, //70003646 
+0x0F120081, //70003648 
+0x0F125055, //7000364A 
+0x0F121C40, //7000364C 
+0x0F128020, //7000364E 
+0x0F12BC70, //70003650 
+0x0F12BC08, //70003652 
+0x0F124718, //70003654 
+0x0F126801, //70003656 
+0x0F120409, //70003658 
+0x0F120C09, //7000365A 
+0x0F126840, //7000365C 
+0x0F120400, //7000365E 
+0x0F120C00, //70003660 
+0x0F124AF5, //70003662 
+0x0F128992, //70003664 
+0x0F122A00, //70003666 
+0x0F12D00D, //70003668 
+0x0F122300, //7000366A 
+0x0F121A80, //7000366C 
+0x0F12D400, //7000366E 
+0x0F120003, //70003670 
+0x0F120418, //70003672 
+0x0F120C00, //70003674 
+0x0F124BF1, //70003676 
+0x0F121851, //70003678 
+0x0F12891B, //7000367A 
+0x0F12428B, //7000367C 
+0x0F12D300, //7000367E 
+0x0F12000B, //70003680 
+0x0F120419, //70003682 
+0x0F120C09, //70003684 
+0x0F124AEE, //70003686 
+0x0F128151, //70003688 
+0x0F128190, //7000368A 
+0x0F124770, //7000368C 
+0x0F12B510, //7000368E 
+0x0F124CEC, //70003690 
+0x0F1248ED, //70003692 
+0x0F1278A1, //70003694 
+0x0F122900, //70003696 
+0x0F12D101, //70003698 
+0x0F1287C1, //7000369A 
+0x0F12E004, //7000369C 
+0x0F127AE1, //7000369E 
+0x0F122900, //700036A0 
+0x0F12D001, //700036A2 
+0x0F122101, //700036A4 
+0x0F1287C1, //700036A6 
+0x0F12F000, //700036A8 
+0x0F12FB1A, //700036AA 
+0x0F1249E7, //700036AC 
+0x0F128B08, //700036AE 
+0x0F1206C2, //700036B0 
+0x0F12D50A, //700036B2 
+0x0F127AA2, //700036B4 
+0x0F120652, //700036B6 
+0x0F12D507, //700036B8 
+0x0F122210, //700036BA 
+0x0F124390, //700036BC 
+0x0F128308, //700036BE 
+0x0F1248E3, //700036C0 
+0x0F127AE1, //700036C2 
+0x0F126B00, //700036C4 
+0x0F12F000, //700036C6 
+0x0F12FB13, //700036C8 
+0x0F1248DB, //700036CA 
+0x0F1289C0, //700036CC 
+0x0F122801, //700036CE 
+0x0F12D109, //700036D0 
+0x0F1278A0, //700036D2 
+0x0F122800, //700036D4 
+0x0F12D006, //700036D6 
+0x0F127AE0, //700036D8 
+0x0F122800, //700036DA 
+0x0F12D003, //700036DC 
+0x0F127AA0, //700036DE 
+0x0F122140, //700036E0 
+0x0F124308, //700036E2 
+0x0F1272A0, //700036E4 
+0x0F12BC10, //700036E6 
+0x0F12BC08, //700036E8 
+0x0F124718, //700036EA 
+0x0F12B570, //700036EC 
+0x0F124DD7, //700036EE 
+0x0F124CD7, //700036F0 
+0x0F128B28, //700036F2 
+0x0F120701, //700036F4 
+0x0F12D507, //700036F6 
+0x0F122108, //700036F8 
+0x0F124388, //700036FA 
+0x0F128328, //700036FC 
+0x0F1249D5, //700036FE 
+0x0F126B20, //70003700 
+0x0F126B89, //70003702 
+0x0F12F000, //70003704 
+0x0F12FAFC, //70003706 
+0x0F128B28, //70003708 
+0x0F1206C1, //7000370A 
+0x0F12D5A0, //7000370C 
+0x0F1249CD, //7000370E 
+0x0F127A8A, //70003710 
+0x0F120652, //70003712 
+0x0F12D49C, //70003714 
+0x0F122210, //70003716 
+0x0F124390, //70003718 
+0x0F128328, //7000371A 
+0x0F127AC9, //7000371C 
+0x0F126B20, //7000371E 
+0x0F12F000, //70003720 
+0x0F12FAE6, //70003722 
+0x0F12E794, //70003724 
+0x0F12B5F8, //70003726 
+0x0F1249CB, //70003728 
+0x0F128F08, //7000372A 
+0x0F12000C, //7000372C 
+0x0F123480, //7000372E 
+0x0F122800, //70003730 
+0x0F12D000, //70003732 
+0x0F128360, //70003734 
+0x0F122000, //70003736 
+0x0F128708, //70003738 
+0x0F124DC8, //7000373A 
+0x0F1226FF, //7000373C 
+0x0F128828, //7000373E 
+0x0F121C76, //70003740 
+0x0F122702, //70003742 
+0x0F122803, //70003744 
+0x0F12D112, //70003746 
+0x0F128868, //70003748 
+0x0F122800, //7000374A 
+0x0F12D10F, //7000374C 
+0x0F1288E8, //7000374E 
+0x0F122800, //70003750 
+0x0F12D10C, //70003752 
+0x0F12F000, //70003754 
+0x0F12FADC, //70003756 
+0x0F122800, //70003758 
+0x0F12D008, //7000375A 
+0x0F128B60, //7000375C 
+0x0F122800, //7000375E 
+0x0F12D001, //70003760 
+0x0F1280EE, //70003762 
+0x0F1280AF, //70003764 
+0x0F122001, //70003766 
+0x0F127268, //70003768 
+0x0F12F000, //7000376A 
+0x0F12FAD9, //7000376C 
+0x0F128828, //7000376E 
+0x0F122802, //70003770 
+0x0F12D10E, //70003772 
+0x0F128868, //70003774 
+0x0F122800, //70003776 
+0x0F12D10B, //70003778 
+0x0F1288E8, //7000377A 
+0x0F122800, //7000377C 
+0x0F12D108, //7000377E 
+0x0F128B60, //70003780 
+0x0F122800, //70003782 
+0x0F12D001, //70003784 
+0x0F1280EE, //70003786 
+0x0F1280AF, //70003788 
+0x0F122001, //7000378A 
+0x0F127268, //7000378C 
+0x0F12F000, //7000378E 
+0x0F12FAC7, //70003790 
+0x0F1288E8, //70003792 
+0x0F122800, //70003794 
+0x0F12D006, //70003796 
+0x0F121FC1, //70003798 
+0x0F1239FD, //7000379A 
+0x0F12D003, //7000379C 
+0x0F122001, //7000379E 
+0x0F12BCF8, //700037A0 
+0x0F12BC08, //700037A2 
+0x0F124718, //700037A4 
+0x0F122000, //700037A6 
+0x0F12E7FA, //700037A8 
+0x0F12B570, //700037AA 
+0x0F124CAC, //700037AC 
+0x0F128860, //700037AE 
+0x0F122800, //700037B0 
+0x0F12D00C, //700037B2 
+0x0F128820, //700037B4 
+0x0F124DA3, //700037B6 
+0x0F122800, //700037B8 
+0x0F12D009, //700037BA 
+0x0F120029, //700037BC 
+0x0F1231A0, //700037BE 
+0x0F127AC9, //700037C0 
+0x0F122900, //700037C2 
+0x0F12D004, //700037C4 
+0x0F127AA8, //700037C6 
+0x0F122180, //700037C8 
+0x0F124308, //700037CA 
+0x0F1272A8, //700037CC 
+0x0F12E73F, //700037CE 
+0x0F122800, //700037D0 
+0x0F12D003, //700037D2 
+0x0F12F7FF, //700037D4 
+0x0F12FFA7, //700037D6 
+0x0F122800, //700037D8 
+0x0F12D1F8, //700037DA 
+0x0F122000, //700037DC 
+0x0F128060, //700037DE 
+0x0F128820, //700037E0 
+0x0F122800, //700037E2 
+0x0F12D003, //700037E4 
+0x0F122008, //700037E6 
+0x0F12F000, //700037E8 
+0x0F12FAA2, //700037EA 
+0x0F12E00B, //700037EC 
+0x0F12489C, //700037EE 
+0x0F123020, //700037F0 
+0x0F128880, //700037F2 
+0x0F122800, //700037F4 
+0x0F12D103, //700037F6 
+0x0F127AA8, //700037F8 
+0x0F122101, //700037FA 
+0x0F124308, //700037FC 
+0x0F1272A8, //700037FE 
+0x0F122010, //70003800 
+0x0F12F000, //70003802 
+0x0F12FA95, //70003804 
+0x0F128820, //70003806 
+0x0F122800, //70003808 
+0x0F12D1E0, //7000380A 
+0x0F12488A, //7000380C 
+0x0F1289C0, //7000380E 
+0x0F122801, //70003810 
+0x0F12D1DC, //70003812 
+0x0F127AA8, //70003814 
+0x0F1221BF, //70003816 
+0x0F124008, //70003818 
+0x0F1272A8, //7000381A 
+0x0F12E718, //7000381C 
+0x0F126800, //7000381E 
+0x0F124990, //70003820 
+0x0F128188, //70003822 
+0x0F124890, //70003824 
+0x0F122201, //70003826 
+0x0F128981, //70003828 
+0x0F124890, //7000382A 
+0x0F120252, //7000382C 
+0x0F124291, //7000382E 
+0x0F12D902, //70003830 
+0x0F122102, //70003832 
+0x0F128181, //70003834 
+0x0F124770, //70003836 
+0x0F122101, //70003838 
+0x0F128181, //7000383A 
+0x0F124770, //7000383C 
+0x0F12B5F1, //7000383E 
+0x0F124E80, //70003840 
+0x0F128834, //70003842 
+0x0F122C00, //70003844 
+0x0F12D03F, //70003846 
+0x0F122001, //70003848 
+0x0F122C08, //7000384A 
+0x0F12D000, //7000384C 
+0x0F122000, //7000384E 
+0x0F1270B0, //70003850 
+0x0F124D7F, //70003852 
+0x0F122800, //70003854 
+0x0F12D009, //70003856 
+0x0F12F000, //70003858 
+0x0F12FA72, //7000385A 
+0x0F120028, //7000385C 
+0x0F1238F0, //7000385E 
+0x0F126328, //70003860 
+0x0F127AB0, //70003862 
+0x0F12217E, //70003864 
+0x0F124008, //70003866 
+0x0F1272B0, //70003868 
+0x0F12E00F, //7000386A 
+0x0F124F7A, //7000386C 
+0x0F123780, //7000386E 
+0x0F128B78, //70003870 
+0x0F122800, //70003872 
+0x0F12D005, //70003874 
+0x0F12F000, //70003876 
+0x0F12FA6B, //70003878 
+0x0F122000, //7000387A 
+0x0F128378, //7000387C 
+0x0F124976, //7000387E 
+0x0F128708, //70003880 
+0x0F122000, //70003882 
+0x0F12F000, //70003884 
+0x0F12FA6C, //70003886 
+0x0F124879, //70003888 
+0x0F126328, //7000388A 
+0x0F1278B1, //7000388C 
+0x0F122700, //7000388E 
+0x0F120038, //70003890 
+0x0F122900, //70003892 
+0x0F12D008, //70003894 
+0x0F124972, //70003896 
+0x0F123920, //70003898 
+0x0F128ACA, //7000389A 
+0x0F122A00, //7000389C 
+0x0F12D003, //7000389E 
+0x0F128B09, //700038A0 
+0x0F122900, //700038A2 
+0x0F12D000, //700038A4 
+0x0F122001, //700038A6 
+0x0F127170, //700038A8 
+0x0F122C02, //700038AA 
+0x0F12D102, //700038AC 
+0x0F124868, //700038AE 
+0x0F123860, //700038B0 
+0x0F126328, //700038B2 
+0x0F122201, //700038B4 
+0x0F122C02, //700038B6 
+0x0F12D000, //700038B8 
+0x0F122200, //700038BA 
+0x0F124861, //700038BC 
+0x0F122110, //700038BE 
+0x0F12300A, //700038C0 
+0x0F12F000, //700038C2 
+0x0F12FA55, //700038C4 
+0x0F128037, //700038C6 
+0x0F129900, //700038C8 
+0x0F120020, //700038CA 
+0x0F12600C, //700038CC 
+0x0F12E767, //700038CE 
+0x0F12B538, //700038D0 
+0x0F124865, //700038D2 
+0x0F124669, //700038D4 
+0x0F123848, //700038D6 
+0x0F12F000, //700038D8 
+0x0F12FA52, //700038DA 
+0x0F124A5E, //700038DC 
+0x0F124862, //700038DE 
+0x0F128F51, //700038E0 
+0x0F122400, //700038E2 
+0x0F123020, //700038E4 
+0x0F122900, //700038E6 
+0x0F12D00A, //700038E8 
+0x0F128754, //700038EA 
+0x0F126941, //700038EC 
+0x0F126451, //700038EE 
+0x0F126491, //700038F0 
+0x0F12466B, //700038F2 
+0x0F128819, //700038F4 
+0x0F1287D1, //700038F6 
+0x0F12885B, //700038F8 
+0x0F120011, //700038FA 
+0x0F123140, //700038FC 
+0x0F12800B, //700038FE 
+0x0F128F91, //70003900 
+0x0F122900, //70003902 
+0x0F12D002, //70003904 
+0x0F128794, //70003906 
+0x0F126940, //70003908 
+0x0F126490, //7000390A 
+0x0F12F000, //7000390C 
+0x0F12FA40, //7000390E 
+0x0F12BC38, //70003910 
+0x0F12BC08, //70003912 
+0x0F124718, //70003914 
+0x0F12B5F8, //70003916 
+0x0F124C56, //70003918 
+0x0F1289E0, //7000391A 
+0x0F12F000, //7000391C 
+0x0F12FA40, //7000391E 
+0x0F120006, //70003920 
+0x0F128A20, //70003922 
+0x0F12F000, //70003924 
+0x0F12FA44, //70003926 
+0x0F120007, //70003928 
+0x0F12484F, //7000392A 
+0x0F124D4A, //7000392C 
+0x0F123020, //7000392E 
+0x0F126CA9, //70003930 
+0x0F126940, //70003932 
+0x0F121809, //70003934 
+0x0F120200, //70003936 
+0x0F12F000, //70003938 
+0x0F12FA42, //7000393A 
+0x0F120400, //7000393C 
+0x0F120C00, //7000393E 
+0x0F12002A, //70003940 
+0x0F12326E, //70003942 
+0x0F120011, //70003944 
+0x0F12390A, //70003946 
+0x0F122305, //70003948 
+0x0F12F000, //7000394A 
+0x0F12FA3F, //7000394C 
+0x0F124C43, //7000394E 
+0x0F1261A0, //70003950 
+0x0F128FEB, //70003952 
+0x0F120002, //70003954 
+0x0F120031, //70003956 
+0x0F120018, //70003958 
+0x0F12F000, //7000395A 
+0x0F12FA3F, //7000395C 
+0x0F12466B, //7000395E 
+0x0F120005, //70003960 
+0x0F128018, //70003962 
+0x0F12483C, //70003964 
+0x0F1269A2, //70003966 
+0x0F123040, //70003968 
+0x0F128800, //7000396A 
+0x0F120039, //7000396C 
+0x0F12F000, //7000396E 
+0x0F12FA35, //70003970 
+0x0F12466B, //70003972 
+0x0F120006, //70003974 
+0x0F128058, //70003976 
+0x0F120021, //70003978 
+0x0F129800, //7000397A 
+0x0F12311C, //7000397C 
+0x0F12F000, //7000397E 
+0x0F12FA35, //70003980 
+0x0F124935, //70003982 
+0x0F123180, //70003984 
+0x0F12808D, //70003986 
+0x0F1280CE, //70003988 
+0x0F128BA1, //7000398A 
+0x0F124836, //7000398C 
+0x0F123820, //7000398E 
+0x0F128001, //70003990 
+0x0F128BE1, //70003992 
+0x0F128041, //70003994 
+0x0F128C21, //70003996 
+0x0F128081, //70003998 
+0x0F12E701, //7000399A 
+0x0F12B5F8, //7000399C 
+0x0F124E2E, //7000399E 
+0x0F126C70, //700039A0 
+0x0F126CB1, //700039A2 
+0x0F120200, //700039A4 
+0x0F12F000, //700039A6 
+0x0F12FA0B, //700039A8 
+0x0F120400, //700039AA 
+0x0F120C00, //700039AC 
+0x0F122401, //700039AE 
+0x0F120364, //700039B0 
+0x0F1242A0, //700039B2 
+0x0F12D200, //700039B4 
+0x0F120004, //700039B6 
+0x0F124A27, //700039B8 
+0x0F120020, //700039BA 
+0x0F12327E, //700039BC 
+0x0F121F91, //700039BE 
+0x0F122303, //700039C0 
+0x0F12F000, //700039C2 
+0x0F12FA03, //700039C4 
+0x0F120405, //700039C6 
+0x0F120C2D, //700039C8 
+0x0F124A23, //700039CA 
+0x0F120020, //700039CC 
+0x0F12325A, //700039CE 
+0x0F120011, //700039D0 
+0x0F12390A, //700039D2 
+0x0F122305, //700039D4 
+0x0F12F000, //700039D6 
+0x0F12F9F9, //700039D8 
+0x0F12491F, //700039DA 
+0x0F1264C8, //700039DC 
+0x0F12491F, //700039DE 
+0x0F124E21, //700039E0 
+0x0F1288C8, //700039E2 
+0x0F122701, //700039E4 
+0x0F122800, //700039E6 
+0x0F12D009, //700039E8 
+0x0F124C23, //700039EA 
+0x0F1238FF, //700039EC 
+0x0F121E40, //700039EE 
+0x0F12D00A, //700039F0 
+0x0F122804, //700039F2 
+0x0F12D042, //700039F4 
+0x0F122806, //700039F6 
+0x0F12D101, //700039F8 
+0x0F122000, //700039FA 
+0x0F1280C8, //700039FC 
+0x0F1282B7, //700039FE 
+0x0F122001, //70003A00 
+0x0F12F000, //70003A02 
+0x0F12F9FB, //70003A04 
+0x0F12E6CB, //70003A06 
+0x0F12000D, //70003A08 
+0x0F12724F, //70003A0A 
+0x0F122001, //70003A0C 
+0x0F12F000, //70003A0E 
+0x0F12F9FD, //70003A10 
+0x0F12F000, //70003A12 
+0x0F12FA03, //70003A14 
+0x0F124910, //70003A16 
+0x0F123148, //70003A18 
+0x0F12C903, //70003A1A 
+0x0F124348, //70003A1C 
+0x0F120A00, //70003A1E 
+0x0F126160, //70003A20 
+0x0F1220FF, //70003A22 
+0x0F121D40, //70003A24 
+0x0F1280E8, //70003A26 
+0x0F12480C, //70003A28 
+0x0F123040, //70003A2A 
+0x0F127707, //70003A2C 
+0x0F12E7E6, //70003A2E 
+0x0F123290, //70003A30 
+0x0F127000, //70003A32 
+0x0F123294, //70003A34 
+0x0F127000, //70003A36 
+0x0F1204A8, //70003A38 
+0x0F127000, //70003A3A 
+0x0F1215DC, //70003A3C 
+0x0F127000, //70003A3E 
+0x0F125000, //70003A40 
+0x0F12D000, //70003A42 
+0x0F121E84, //70003A44 
+0x0F127000, //70003A46 
+0x0F121BE4, //70003A48 
+0x0F127000, //70003A4A 
+0x0F122EA8, //70003A4C 
+0x0F127000, //70003A4E 
+0x0F1221A4, //70003A50 
+0x0F127000, //70003A52 
+0x0F120100, //70003A54 
+0x0F127000, //70003A56 
+0x0F123F48, //70003A58 
+0x0F127000, //70003A5A 
+0x0F1231A0, //70003A5C 
+0x0F127000, //70003A5E 
+0x0F1201E8, //70003A60 
+0x0F127000, //70003A62 
+0x0F12F2A0, //70003A64 
+0x0F12D000, //70003A66 
+0x0F122A44, //70003A68 
+0x0F127000, //70003A6A 
+0x0F12F400, //70003A6C 
+0x0F12D000, //70003A6E 
+0x0F122024, //70003A70 
+0x0F127000, //70003A72 
+0x0F121650, //70003A74 
+0x0F127000, //70003A76 
+0x0F122A64, //70003A78 
+0x0F127000, //70003A7A 
+0x0F124982, //70003A7C 
+0x0F12724F, //70003A7E 
+0x0F1220FF, //70003A80 
+0x0F121DC0, //70003A82 
+0x0F1280C8, //70003A84 
+0x0F12F000, //70003A86 
+0x0F12F9D1, //70003A88 
+0x0F124980, //70003A8A 
+0x0F126ACA, //70003A8C 
+0x0F12604A, //70003A8E 
+0x0F122800, //70003A90 
+0x0F12D006, //70003A92 
+0x0F12436A, //70003A94 
+0x0F120001, //70003A96 
+0x0F120010, //70003A98 
+0x0F12F000, //70003A9A 
+0x0F12F991, //70003A9C 
+0x0F126160, //70003A9E 
+0x0F12E001, //70003AA0 
+0x0F12436A, //70003AA2 
+0x0F126162, //70003AA4 
+0x0F128BF0, //70003AA6 
+0x0F122800, //70003AA8 
+0x0F12D001, //70003AAA 
+0x0F12F7FF, //70003AAC 
+0x0F12FF33, //70003AAE 
+0x0F122000, //70003AB0 
+0x0F12F000, //70003AB2 
+0x0F12F9AB, //70003AB4 
+0x0F124974, //70003AB6 
+0x0F1220FF, //70003AB8 
+0x0F121DC0, //70003ABA 
+0x0F1280C8, //70003ABC 
+0x0F12E79E, //70003ABE 
+0x0F12B510, //70003AC0 
+0x0F12F000, //70003AC2 
+0x0F12F9BB, //70003AC4 
+0x0F124870, //70003AC6 
+0x0F1288C0, //70003AC8 
+0x0F121FC1, //70003ACA 
+0x0F1239FD, //70003ACC 
+0x0F12D103, //70003ACE 
+0x0F12496F, //70003AD0 
+0x0F1220FF, //70003AD2 
+0x0F121C40, //70003AD4 
+0x0F128048, //70003AD6 
+0x0F12E605, //70003AD8 
+0x0F12B5F8, //70003ADA 
+0x0F122400, //70003ADC 
+0x0F124D6D, //70003ADE 
+0x0F12486D, //70003AE0 
+0x0F12210E, //70003AE2 
+0x0F128041, //70003AE4 
+0x0F122101, //70003AE6 
+0x0F128001, //70003AE8 
+0x0F12F000, //70003AEA 
+0x0F12F9AF, //70003AEC 
+0x0F12486B, //70003AEE 
+0x0F128840, //70003AF0 
+0x0F12F000, //70003AF2 
+0x0F12F9B3, //70003AF4 
+0x0F124E6A, //70003AF6 
+0x0F12270D, //70003AF8 
+0x0F12073F, //70003AFA 
+0x0F1219E8, //70003AFC 
+0x0F128803, //70003AFE 
+0x0F1200E2, //70003B00 
+0x0F121991, //70003B02 
+0x0F12804B, //70003B04 
+0x0F128843, //70003B06 
+0x0F1252B3, //70003B08 
+0x0F128882, //70003B0A 
+0x0F1280CA, //70003B0C 
+0x0F1288C0, //70003B0E 
+0x0F128088, //70003B10 
+0x0F123508, //70003B12 
+0x0F12042D, //70003B14 
+0x0F120C2D, //70003B16 
+0x0F121C64, //70003B18 
+0x0F120424, //70003B1A 
+0x0F120C24, //70003B1C 
+0x0F122C07, //70003B1E 
+0x0F12D3EC, //70003B20 
+0x0F12E63D, //70003B22 
+0x0F12B5F0, //70003B24 
+0x0F12B085, //70003B26 
+0x0F126801, //70003B28 
+0x0F129103, //70003B2A 
+0x0F126881, //70003B2C 
+0x0F12040A, //70003B2E 
+0x0F120C12, //70003B30 
+0x0F12495C, //70003B32 
+0x0F128B89, //70003B34 
+0x0F122900, //70003B36 
+0x0F12D001, //70003B38 
+0x0F120011, //70003B3A 
+0x0F12E000, //70003B3C 
+0x0F122100, //70003B3E 
+0x0F129102, //70003B40 
+0x0F126840, //70003B42 
+0x0F120401, //70003B44 
+0x0F129803, //70003B46 
+0x0F120C09, //70003B48 
+0x0F12F000, //70003B4A 
+0x0F12F98F, //70003B4C 
+0x0F124854, //70003B4E 
+0x0F123080, //70003B50 
+0x0F128900, //70003B52 
+0x0F122800, //70003B54 
+0x0F12D039, //70003B56 
+0x0F122100, //70003B58 
+0x0F124854, //70003B5A 
+0x0F124D52, //70003B5C 
+0x0F124684, //70003B5E 
+0x0F124B53, //70003B60 
+0x0F124C4F, //70003B62 
+0x0F1288DA, //70003B64 
+0x0F120048, //70003B66 
+0x0F1200D7, //70003B68 
+0x0F12193E, //70003B6A 
+0x0F12197F, //70003B6C 
+0x0F12183F, //70003B6E 
+0x0F125A36, //70003B70 
+0x0F128AFF, //70003B72 
+0x0F12437E, //70003B74 
+0x0F1200B6, //70003B76 
+0x0F120C37, //70003B78 
+0x0F121906, //70003B7A 
+0x0F123680, //70003B7C 
+0x0F128177, //70003B7E 
+0x0F121C52, //70003B80 
+0x0F1200D2, //70003B82 
+0x0F121914, //70003B84 
+0x0F121952, //70003B86 
+0x0F121812, //70003B88 
+0x0F125A24, //70003B8A 
+0x0F128AD2, //70003B8C 
+0x0F124354, //70003B8E 
+0x0F1200A2, //70003B90 
+0x0F120C12, //70003B92 
+0x0F128272, //70003B94 
+0x0F12891C, //70003B96 
+0x0F12895B, //70003B98 
+0x0F124367, //70003B9A 
+0x0F12435A, //70003B9C 
+0x0F121943, //70003B9E 
+0x0F123340, //70003BA0 
+0x0F1289DB, //70003BA2 
+0x0F129C02, //70003BA4 
+0x0F1218BA, //70003BA6 
+0x0F124363, //70003BA8 
+0x0F1218D2, //70003BAA 
+0x0F120212, //70003BAC 
+0x0F120C12, //70003BAE 
+0x0F12466B, //70003BB0 
+0x0F12521A, //70003BB2 
+0x0F124663, //70003BB4 
+0x0F127DDB, //70003BB6 
+0x0F12435A, //70003BB8 
+0x0F129B03, //70003BBA 
+0x0F120252, //70003BBC 
+0x0F120C12, //70003BBE 
+0x0F12521A, //70003BC0 
+0x0F121C49, //70003BC2 
+0x0F120409, //70003BC4 
+0x0F120C09, //70003BC6 
+0x0F122904, //70003BC8 
+0x0F12D3C9, //70003BCA 
+0x0F12B005, //70003BCC 
+0x0F12BCF0, //70003BCE 
+0x0F12BC08, //70003BD0 
+0x0F124718, //70003BD2 
+0x0F12B510, //70003BD4 
+0x0F12F7FF, //70003BD6 
+0x0F12FF80, //70003BD8 
+0x0F12F000, //70003BDA 
+0x0F12F94F, //70003BDC 
+0x0F12E582, //70003BDE 
+0x0F12B570, //70003BE0 
+0x0F126804, //70003BE2 
+0x0F12F000, //70003BE4 
+0x0F12F952, //70003BE6 
+0x0F124D32, //70003BE8 
+0x0F128C29, //70003BEA 
+0x0F121A40, //70003BEC 
+0x0F1242A0, //70003BEE 
+0x0F12D901, //70003BF0 
+0x0F120020, //70003BF2 
+0x0F12E003, //70003BF4 
+0x0F12F000, //70003BF6 
+0x0F12F949, //70003BF8 
+0x0F128C29, //70003BFA 
+0x0F121A40, //70003BFC 
+0x0F126268, //70003BFE 
+0x0F12F000, //70003C00 
+0x0F12F94C, //70003C02 
+0x0F1262A8, //70003C04 
+0x0F12F000, //70003C06 
+0x0F12F951, //70003C08 
+0x0F126328, //70003C0A 
+0x0F128869, //70003C0C 
+0x0F122900, //70003C0E 
+0x0F12D000, //70003C10 
+0x0F1262A8, //70003C12 
+0x0F124828, //70003C14 
+0x0F126B00, //70003C16 
+0x0F128C00, //70003C18 
+0x0F122800, //70003C1A 
+0x0F12D11B, //70003C1C 
+0x0F126AA8, //70003C1E 
+0x0F12F000, //70003C20 
+0x0F12F94C, //70003C22 
+0x0F1261E8, //70003C24 
+0x0F124A1E, //70003C26 
+0x0F123280, //70003C28 
+0x0F128B91, //70003C2A 
+0x0F122900, //70003C2C 
+0x0F12D00B, //70003C2E 
+0x0F120011, //70003C30 
+0x0F123120, //70003C32 
+0x0F128809, //70003C34 
+0x0F124288, //70003C36 
+0x0F12D907, //70003C38 
+0x0F1261E9, //70003C3A 
+0x0F128C28, //70003C3C 
+0x0F121A08, //70003C3E 
+0x0F1262A8, //70003C40 
+0x0F12F000, //70003C42 
+0x0F12F92B, //70003C44 
+0x0F1262A8, //70003C46 
+0x0F12E502, //70003C48 
+0x0F128BD1, //70003C4A 
+0x0F124288, //70003C4C 
+0x0F12D800, //70003C4E 
+0x0F120008, //70003C50 
+0x0F1261E8, //70003C52 
+0x0F12E4FC, //70003C54 
+0x0F12F000, //70003C56 
+0x0F12F919, //70003C58 
+0x0F1261E8, //70003C5A 
+0x0F12E4F8, //70003C5C 
+0x0F12B510, //70003C5E 
+0x0F12F000, //70003C60 
+0x0F12F934, //70003C62 
+0x0F12480E, //70003C64 
+0x0F1230A0, //70003C66 
+0x0F128841, //70003C68 
+0x0F122900, //70003C6A 
+0x0F12D007, //70003C6C 
+0x0F124A07, //70003C6E 
+0x0F123280, //70003C70 
+0x0F126953, //70003C72 
+0x0F124A11, //70003C74 
+0x0F12428B, //70003C76 
+0x0F12D202, //70003C78 
+0x0F128880, //70003C7A 
+0x0F1281D0, //70003C7C 
+0x0F12E532, //70003C7E 
+0x0F1288C0, //70003C80 
+0x0F1281D0, //70003C82 
+0x0F12E52F, //70003C84 
+0x0F120000, //70003C86 
+0x0F1231A0, //70003C88 
+0x0F127000, //70003C8A 
+0x0F1229E4, //70003C8C 
+0x0F127000, //70003C8E 
+0x0F12C100, //70003C90 
+0x0F12D000, //70003C92 
+0x0F12A006, //70003C94 
+0x0F120000, //70003C96 
+0x0F12A000, //70003C98 
+0x0F12D000, //70003C9A 
+0x0F12064C, //70003C9C 
+0x0F127000, //70003C9E 
+0x0F123F48, //70003CA0 
+0x0F127000, //70003CA2 
+0x0F1207C4, //70003CA4 
+0x0F127000, //70003CA6 
+0x0F1207E8, //70003CA8 
+0x0F127000, //70003CAA 
+0x0F122B24, //70003CAC 
+0x0F127000, //70003CAE 
+0x0F121FA0, //70003CB0 
+0x0F127000, //70003CB2 
+0x0F121E3C, //70003CB4 
+0x0F127000, //70003CB6 
+0x0F1221A4, //70003CB8 
+0x0F127000, //70003CBA 
+0x0F12E200, //70003CBC 
+0x0F12D000, //70003CBE 
+0x0F124778, //70003CC0 
+0x0F1246C0, //70003CC2 
+0x0F12C000, //70003CC4 
+0x0F12E59F, //70003CC6 
+0x0F12FF1C, //70003CC8 
+0x0F12E12F, //70003CCA 
+0x0F121F63, //70003CCC 
+0x0F120001, //70003CCE 
+0x0F124778, //70003CD0 
+0x0F1246C0, //70003CD2 
+0x0F12C000, //70003CD4 
+0x0F12E59F, //70003CD6 
+0x0F12FF1C, //70003CD8 
+0x0F12E12F, //70003CDA 
+0x0F121EDF, //70003CDC 
+0x0F120001, //70003CDE 
+0x0F124778, //70003CE0 
+0x0F1246C0, //70003CE2 
+0x0F12C000, //70003CE4 
+0x0F12E59F, //70003CE6 
+0x0F12FF1C, //70003CE8 
+0x0F12E12F, //70003CEA 
+0x0F12495F, //70003CEC 
+0x0F120000, //70003CEE 
+0x0F124778, //70003CF0 
+0x0F1246C0, //70003CF2 
+0x0F12C000, //70003CF4 
+0x0F12E59F, //70003CF6 
+0x0F12FF1C, //70003CF8 
+0x0F12E12F, //70003CFA 
+0x0F12E403, //70003CFC 
+0x0F120000, //70003CFE 
+0x0F124778, //70003D00 
+0x0F1246C0, //70003D02 
+0x0F12C000, //70003D04 
+0x0F12E59F, //70003D06 
+0x0F12FF1C, //70003D08 
+0x0F12E12F, //70003D0A 
+0x0F1224B3, //70003D0C 
+0x0F120001, //70003D0E 
+0x0F124778, //70003D10 
+0x0F1246C0, //70003D12 
+0x0F12C000, //70003D14 
+0x0F12E59F, //70003D16 
+0x0F12FF1C, //70003D18 
+0x0F12E12F, //70003D1A 
+0x0F12EECD, //70003D1C 
+0x0F120000, //70003D1E 
+0x0F124778, //70003D20 
+0x0F1246C0, //70003D22 
+0x0F12C000, //70003D24 
+0x0F12E59F, //70003D26 
+0x0F12FF1C, //70003D28 
+0x0F12E12F, //70003D2A 
+0x0F12F049, //70003D2C 
+0x0F120000, //70003D2E 
+0x0F124778, //70003D30 
+0x0F1246C0, //70003D32 
+0x0F12C000, //70003D34 
+0x0F12E59F, //70003D36 
+0x0F12FF1C, //70003D38 
+0x0F12E12F, //70003D3A 
+0x0F1212DF, //70003D3C 
+0x0F120000, //70003D3E 
+0x0F124778, //70003D40 
+0x0F1246C0, //70003D42 
+0x0F12C000, //70003D44 
+0x0F12E59F, //70003D46 
+0x0F12FF1C, //70003D48 
+0x0F12E12F, //70003D4A 
+0x0F12F05B, //70003D4C 
+0x0F120000, //70003D4E 
+0x0F124778, //70003D50 
+0x0F1246C0, //70003D52 
+0x0F12C000, //70003D54 
+0x0F12E59F, //70003D56 
+0x0F12FF1C, //70003D58 
+0x0F12E12F, //70003D5A 
+0x0F12F07B, //70003D5C 
+0x0F120000, //70003D5E 
+0x0F124778, //70003D60 
+0x0F1246C0, //70003D62 
+0x0F12C000, //70003D64 
+0x0F12E59F, //70003D66 
+0x0F12FF1C, //70003D68 
+0x0F12E12F, //70003D6A 
+0x0F12FE6D, //70003D6C 
+0x0F120000, //70003D6E 
+0x0F124778, //70003D70 
+0x0F1246C0, //70003D72 
+0x0F12C000, //70003D74 
+0x0F12E59F, //70003D76 
+0x0F12FF1C, //70003D78 
+0x0F12E12F, //70003D7A 
+0x0F123295, //70003D7C 
+0x0F120000, //70003D7E 
+0x0F124778, //70003D80 
+0x0F1246C0, //70003D82 
+0x0F12C000, //70003D84 
+0x0F12E59F, //70003D86 
+0x0F12FF1C, //70003D88 
+0x0F12E12F, //70003D8A 
+0x0F12234F, //70003D8C 
+0x0F120000, //70003D8E 
+0x0F124778, //70003D90 
+0x0F1246C0, //70003D92 
+0x0F12C000, //70003D94 
+0x0F12E59F, //70003D96 
+0x0F12FF1C, //70003D98 
+0x0F12E12F, //70003D9A 
+0x0F124521, //70003D9C 
+0x0F120000, //70003D9E 
+0x0F124778, //70003DA0 
+0x0F1246C0, //70003DA2 
+0x0F12C000, //70003DA4 
+0x0F12E59F, //70003DA6 
+0x0F12FF1C, //70003DA8 
+0x0F12E12F, //70003DAA 
+0x0F127C0D, //70003DAC 
+0x0F120000, //70003DAE 
+0x0F124778, //70003DB0 
+0x0F1246C0, //70003DB2 
+0x0F12C000, //70003DB4 
+0x0F12E59F, //70003DB6 
+0x0F12FF1C, //70003DB8 
+0x0F12E12F, //70003DBA 
+0x0F127C2B, //70003DBC 
+0x0F120000, //70003DBE 
+0x0F124778, //70003DC0 
+0x0F1246C0, //70003DC2 
+0x0F12F004, //70003DC4 
+0x0F12E51F, //70003DC6 
+0x0F1224C4, //70003DC8 
+0x0F120001, //70003DCA 
+0x0F124778, //70003DCC 
+0x0F1246C0, //70003DCE 
+0x0F12C000, //70003DD0 
+0x0F12E59F, //70003DD2 
+0x0F12FF1C, //70003DD4 
+0x0F12E12F, //70003DD6 
+0x0F123183, //70003DD8 
+0x0F120000, //70003DDA 
+0x0F124778, //70003DDC 
+0x0F1246C0, //70003DDE 
+0x0F12C000, //70003DE0 
+0x0F12E59F, //70003DE2 
+0x0F12FF1C, //70003DE4 
+0x0F12E12F, //70003DE6 
+0x0F12302F, //70003DE8 
+0x0F120000, //70003DEA 
+0x0F124778, //70003DEC 
+0x0F1246C0, //70003DEE 
+0x0F12C000, //70003DF0 
+0x0F12E59F, //70003DF2 
+0x0F12FF1C, //70003DF4 
+0x0F12E12F, //70003DF6 
+0x0F12EF07, //70003DF8 
+0x0F120000, //70003DFA 
+0x0F124778, //70003DFC 
+0x0F1246C0, //70003DFE 
+0x0F12C000, //70003E00 
+0x0F12E59F, //70003E02 
+0x0F12FF1C, //70003E04 
+0x0F12E12F, //70003E06 
+0x0F1248FB, //70003E08 
+0x0F120000, //70003E0A 
+0x0F124778, //70003E0C 
+0x0F1246C0, //70003E0E 
+0x0F12C000, //70003E10 
+0x0F12E59F, //70003E12 
+0x0F12FF1C, //70003E14 
+0x0F12E12F, //70003E16 
+0x0F12F0B1, //70003E18 
+0x0F120000, //70003E1A 
+0x0F124778, //70003E1C 
+0x0F1246C0, //70003E1E 
+0x0F12C000, //70003E20 
+0x0F12E59F, //70003E22 
+0x0F12FF1C, //70003E24 
+0x0F12E12F, //70003E26 
+0x0F12EEDF, //70003E28 
+0x0F120000, //70003E2A 
+0x0F124778, //70003E2C 
+0x0F1246C0, //70003E2E 
+0x0F12C000, //70003E30 
+0x0F12E59F, //70003E32 
+0x0F12FF1C, //70003E34 
+0x0F12E12F, //70003E36 
+0x0F12AEF1, //70003E38 
+0x0F120000, //70003E3A 
+0x0F124778, //70003E3C 
+0x0F1246C0, //70003E3E 
+0x0F12C000, //70003E40 
+0x0F12E59F, //70003E42 
+0x0F12FF1C, //70003E44 
+0x0F12E12F, //70003E46 
+0x0F1202EB, //70003E48 
+0x0F120001, //70003E4A 
+0x0F124778, //70003E4C 
+0x0F1246C0, //70003E4E 
+0x0F12C000, //70003E50 
+0x0F12E59F, //70003E52 
+0x0F12FF1C, //70003E54 
+0x0F12E12F, //70003E56 
+0x0F12FD21, //70003E58 
+0x0F120000, //70003E5A 
+0x0F124778, //70003E5C 
+0x0F1246C0, //70003E5E 
+0x0F12C000, //70003E60 
+0x0F12E59F, //70003E62 
+0x0F12FF1C, //70003E64 
+0x0F12E12F, //70003E66 
+0x0F12FDAF, //70003E68 
+0x0F120000, //70003E6A 
+0x0F124778, //70003E6C 
+0x0F1246C0, //70003E6E 
+0x0F12C000, //70003E70 
+0x0F12E59F, //70003E72 
+0x0F12FF1C, //70003E74 
+0x0F12E12F, //70003E76 
+0x0F125027, //70003E78 
+0x0F120000, //70003E7A 
+0x0F124778, //70003E7C 
+0x0F1246C0, //70003E7E 
+0x0F12C000, //70003E80 
+0x0F12E59F, //70003E82 
+0x0F12FF1C, //70003E84 
+0x0F12E12F, //70003E86 
+0x0F1204C9, //70003E88 
+0x0F120000, //70003E8A 
+0x0F124778, //70003E8C 
+0x0F1246C0, //70003E8E 
+0x0F12C000, //70003E90 
+0x0F12E59F, //70003E92 
+0x0F12FF1C, //70003E94 
+0x0F12E12F, //70003E96 
+0x0F1239DF, //70003E98 
+0x0F120000, //70003E9A 
+0x0F124778, //70003E9C 
+0x0F1246C0, //70003E9E 
+0x0F12C000, //70003EA0 
+0x0F12E59F, //70003EA2 
+0x0F12FF1C, //70003EA4 
+0x0F12E12F, //70003EA6 
+0x0F126177, //70003EA8 
+0x0F120000, //70003EAA 
+0x0F124778, //70003EAC 
+0x0F1246C0, //70003EAE 
+0x0F12C000, //70003EB0 
+0x0F12E59F, //70003EB2 
+0x0F12FF1C, //70003EB4 
+0x0F12E12F, //70003EB6 
+0x0F12424F, //70003EB8 
+0x0F120000, //70003EBA 
+0x0F124778, //70003EBC 
+0x0F1246C0, //70003EBE 
+0x0F12C000, //70003EC0 
+0x0F12E59F, //70003EC2 
+0x0F12FF1C, //70003EC4 
+0x0F12E12F, //70003EC6 
+0x0F123F0D, //70003EC8 
+0x0F120000, //70003ECA 
+0x0F124778, //70003ECC 
+0x0F1246C0, //70003ECE 
+0x0F12C000, //70003ED0 
+0x0F12E59F, //70003ED2 
+0x0F12FF1C, //70003ED4 
+0x0F12E12F, //70003ED6 
+0x0F1202B9, //70003ED8 
+0x0F120001, //70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007, // clks_src_gf_force_enable
+
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120001, // on/off AFIT by NB option
+
+0x0F120005, //0005// NormBR[0]
+0x0F120066, //00C8// NormBR[1]
+0x0F1200C8, //00F4// NormBR[2]
+0x0F120320, //0320// NormBR[3]
+0x0F120375, //0375// NormBR[4]
+
+
+
+// Flash
+0x002A3F82,
+0x0F120000,// TNP_Regs_PreflashStart
+0x0F120000,// TNP_Regs_PreflashEnd
+0x0F120260,// TNP_Regs_PreWP_r
+0x0F120240, // TNP_Regs_PreWP_b
+
+0x002A3F98,	// BR Tuning
+0x0F120100,	// TNP_Regs_BrRatioIn_0_
+0x0F120150,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120100,	// TNP_Regs_BrRatioOut_0_
+0x0F1200A0,
+0x0F120080,
+0x0F120040,
+0x0F120020,
+
+0x0F120030,	// WP Tuning
+0x0F120040,	// TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	// T_BR tune	
+0x0F120150,	// TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B,
+0x0F12002C,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,	
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120240, //0244 0258 AWB R point //0258 0245 0258
+0x0F120244, //024D 0220 AWB B point //0220 0245 0245
+
+
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// Analog & APS settings                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// This register is for FACTORY ONLY. If you change it without prior notification                           //
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future                           //                           //                           //                           //                           //                           //                           //
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, // adc_sat[7:0]=84d (500mV)
+0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, // rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, // pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, // clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001,// ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+0x002AF42E,
+0x0F120406,// fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+0x002AF434,
+0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, // reg_tune_pix[7:0]
+0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, // reg_tune_rg[7:0] (2.83V)
+0x0F120004, // reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, // blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, // srx_en[0]
+
+0x002A0054,
+0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, // div_dbr[7:4]
+0x002AF132,
+0x0F124006,	//ki 0413// tgr_frame_decription 4
+0x002AF142,
+0x0F120000,	//ki 0413// tgr_frame_decription 4
+
+0x002AF152,
+0x0F120206, // tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, // tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, // tgr_frame_params_descriptor_6
+//==========================================================================================
+
+//============================= Line-ADLC Tuning ===========================================
+0x002AE412,
+0x0F120008, // adlc_tune_offset_gr[7:0]
+0x0F120008, // adlc_tune_offset_r[7:0]
+0x0F120010, // adlc_tune_offset_b[7:0]
+0x0F120010, // adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, // adlc_qec[2:0]
+//==========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F12012C,	//0132 //0138 //awbb_IntcR
+0x0F12010B,	//010A //011C //awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1// No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041,                            //REG_TC_IPRM_CM_Init_GpioConfig1 // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C,                            //REG_TC_IPRM_CM_Init_Mi2cBits // Use GPIO_5 for SCL GPIO_6 for SDA
+0x0F120190,                            //REG_TC_IPRM_CM_Init_Mi2cRateKhz // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000 //#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121000, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120002, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120601, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120001, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200F0, //#af_search_usPeakThr  for
+0x0F120090, //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F124040, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+0x002A0648,  
+0x0F120000, //skl_af_bPregmOff gamma
+
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120011, //#af_pos_usTableLastInd 10h_ 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120034, //#af_pos_usTable_1_  51   
+0x0F120038, //#af_pos_usTable_2_  54	
+0x0F12003C, //#af_pos_usTable_3_  57	
+0x0F120030, //#af_pos_usTable_4_  61   
+0x0F120044, //#af_pos_usTable_5_  65	
+0x0F120048, //#af_pos_usTable_6_  69	
+0x0F12004C, //#af_pos_usTable_7_  73	
+0x0F120050, //#af_pos_usTable_8_  78	
+0x0F120054, //#af_pos_usTable_9_  83	
+0x0F120058, //#af_pos_usTable_10_ 89	
+0x0F12005C, //#af_pos_usTable_11_ 89	
+0x0F120060, //#af_pos_usTable_12_ 89	
+0x0F120064, //#af_pos_usTable_13_ 89	
+0x0F120068, //#af_pos_usTable_14_ 89	
+0x0F12006C, //#af_pos_usTable_15_ 89	
+0x0F120070, //#af_pos_usTable_16_ 89	
+0x0F120074, //#af_pos_usTable_17_ 89		
+
+
+//8. Continuous AF setting
+//8-1 Continuous AF timing
+0x002A152A,
+0x0F120040, //40//30//af_refocus_usFlFrames_ lens movement each 64frame 
+0x002A154A,
+0x0F120010, //18//0C//af_scene_usResetNWaitFr (4 frame) lens movement each 64frame 
+
+//8-2 Continuous AF sensitivity
+0x002A154C, //      
+0x0F120000, //0010   
+0x0F120000, //03FF  
+0x0F120000, //0000  
+           
+
+0x002A1526, //Continuous AF sensitivity tuning
+0x0F128080, //
+0x0F12A0A0, //
+
+
+//8-3 Continuos AF, lens movement
+0x002A1424,  
+0x0F126060,  // af_pos_usMiddlePos  MSB_macro LSB_ normal lens moving direction lens À̵¿¹æÇâ °áÁ¤ AF position table ÀÇ Á߽ɰªÀ» ÀÔ·Â
+0x002A148E, // usPeakFrontThr
+0x0F120002, 
+
+
+//9. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120200, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120004, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120100, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001,//REG_TC_IPRM_AuxConfig // bit[0] : Flash is in use bit[1] : Mechanical shutter is in use                            // 0 : do not use 1 : use
+0x0F120003,//REG_TC_IPRM_AuxPolarity // bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+0x0F120003,//REG_TC_IPRM_AuxGpios  //1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12085C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000, //senHal_bSRX //SRX off
+
+0x002A1680,
+0x0F120002, //senHal_NExpLinesCheckFine //0004 //extend Forbidden area line
+
+0x002A0ED2,
+0x0F120FA0,	//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType // 0:Full 1:digital 2:PLA 3:CA
+0x0F120000, //senHal_SamplingMode // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK
+0x002A0188,
+0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+0x0F120000, //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001, //REG_TC_IPRM_UseNPviClocks
+0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+//SCLK & PCLK // clock set 0
+0x0F1238A4,//38A4	//36B0//34BC //32C8//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+0x0F1254F0,//4E20	//3A98//7148 //4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0	//54Mhz
+0x0F1254F8,//57E4	//61A8//7148 //4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0	//54Mhz
+
+	//SCLK & PCLK     // clock set 1
+0x0F1238A4,//38A4//36B0//34BC	//32C8//REG_TC_IPRM_OpClk4KHz_0	//52Mhz
+0x0F1254F0,//4E20//3A98//7148	//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0//54Mhz
+0x0F1254F8,//57E4//61A8//7148	//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0//54Mhz
+
+	//SCLK & PCLK     // clock set 2                                             
+0x0F1238A4,//38A4//36B0 //34BC//32C8//REG_TC_IPRM_OpClk4KHz_0//52Mhz          
+0x0F1254F0,//4E20//3A98 //7148//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz  
+0x0F1254F8,//57E4//61A8 //7148//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz  
+
+0x002A1B78,
+0x0F1238A4, //REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_0__usSysDiv
+0x0F120001, //REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4, //REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_1__usSysDiv
+0x0F120001, //REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4, //REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_2__usSysDiv
+0x0F120001, //REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A,
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6, 
+0x0F120500, //5C0, //0800 //REG_TC_GP_PrevReqInputWidth	  //Sensor Crop Width	2048
+0x0F1202d0, //33C, //0600 //REG_TC_GP_PrevReqInputHeight  //Sensor Crop Height 1536
+0x0F120198, //180, //120, //0000 //REG_TC_GP_PrevInputWidthOfs	  //Sensor HOffset 0
+0x0F120162, //0000 //REG_TC_GP_PrevInputHeightOfs  //Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A1676,
+0x0F120002,// 0:Full 1:digital 2:PLA 3:CA
+
+0x002A0216,
+0x0F120001,//for input size change
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 1024x768 system 52M PCLK 54M
+//===================================================================
+0x002A023E,
+0x0F120500, //REG_0TC_PCFG_usWidth
+0x0F1202D0, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMinOut4KHzRate
+
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+0x0F1201B8, //1A0 //REG_0TC_PCFG_usMaxFrTimeMsecMult10  //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS 01a0-24fr
+0x0F12014D, //REG_0TC_PCFG_usMinFrTimeMsecMult10 //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+0x0F120000, //3, //REG_0TC_PCFG_uPrevMirror
+0x0F120000, //3, //REG_0TC_PCFG_uCaptureMirror
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 54M
+//===================================================================
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format//PCAM 5:YUV   9:JPEG
+0x0F1254F6,	//REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_CCFG_usMinOut4KHzRate
+
+0x002A033E,
+0x0F120010, //REG_0TC_CCFG_PVIMask  => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+0x002A0346,
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+
+
+
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+
+0xFFFF0064, //Delay 100ms
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120001, //1, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120000,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F00,
+0x0F120000,
+0x0F120F0F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+
+// TVAR_ash_pGAS_low
+0x0F126E49,
+0x0F12FB98,
+0x0F12F348,
+0x0F121BD6,
+0x0F12EBEF,
+0x0F1203D3,
+0x0F12EC8D,
+0x0F12F239,
+0x0F120E64,
+0x0F12F7EA,
+0x0F12FD3B,
+0x0F120A7C,
+0x0F12FC9C,
+0x0F120BD3,
+0x0F12F2E5,
+0x0F120619,
+0x0F120772,
+0x0F12F0B0,
+0x0F12184E,
+0x0F12F95F,
+0x0F120B1A,
+0x0F12FC45,
+0x0F12F716,
+0x0F120DCD,
+0x0F12EF24,
+0x0F120221,
+0x0F12F6BD,
+0x0F1204CB,
+0x0F1200B1,
+0x0F12FEB0,
+0x0F120268,
+0x0F1202C7,
+0x0F12010A,
+0x0F12FF93,
+0x0F12036D,
+0x0F12F859,
+0x0F1281D0,
+0x0F12FA32,
+0x0F12EFDB,
+0x0F12234D,
+0x0F12E799,
+0x0F120337,
+0x0F12EB05,
+0x0F12E8F9,
+0x0F12152E,
+0x0F12F0D5,
+0x0F120842,
+0x0F12043A,
+0x0F12F461,
+0x0F120E58,
+0x0F12F658,
+0x0F12075D,
+0x0F12F78D,
+0x0F12FDE9,
+0x0F12277A,
+0x0F12FFDE,
+0x0F12FD3B,
+0x0F12FE50,
+0x0F120AD1,
+0x0F12FE2C,
+0x0F12E90D,
+0x0F12F7B0,
+0x0F1205DB,
+0x0F1202CD,
+0x0F12F4F1,
+0x0F1202A8,
+0x0F12FDDC,
+0x0F120B59,
+0x0F12F74E,
+0x0F1203D5,
+0x0F12FF4F,
+0x0F1200F7,
+0x0F126A44,
+0x0F12FAD6,
+0x0F12F261,
+0x0F121F28,
+0x0F12E691,
+0x0F1207D2,
+0x0F12EE85,
+0x0F12F426,
+0x0F120F26,
+0x0F12F34B,
+0x0F120036,
+0x0F120C0F,
+0x0F12FDA9,
+0x0F1209EA,
+0x0F12F27A,
+0x0F120CD5,
+0x0F1201E1,
+0x0F12ED41,
+0x0F121DB5,
+0x0F12FD26,
+0x0F1203F7,
+0x0F12F7BB,
+0x0F12FE81,
+0x0F1212D3,
+0x0F12E061,
+0x0F12F81C,
+0x0F1207B1,
+0x0F120408,
+0x0F12F860,
+0x0F12FC9A,
+0x0F120DDE,
+0x0F120C9C,
+0x0F12F2A4,
+0x0F1202EB,
+0x0F12099B,
+0x0F12F5A6,
+0x0F127243,
+0x0F12F74D,
+0x0F12F74B,
+0x0F121800,
+0x0F12EF22,
+0x0F120263,
+0x0F12EBE7,
+0x0F12F5A4,
+0x0F1209D3,
+0x0F12FAB8,
+0x0F12FDFF,
+0x0F12086B,
+0x0F120338,
+0x0F120514,
+0x0F12F840,
+0x0F120768,
+0x0F12FE55,
+0x0F12F884,
+0x0F121488,
+0x0F12FFCD,
+0x0F12035B,
+0x0F12FA4E,
+0x0F1201DB,
+0x0F1206D6,
+0x0F12EE19,
+0x0F12FEA3,
+0x0F12FE8C,
+0x0F1203A3,
+0x0F12FDDB,
+0x0F12FD9B,
+0x0F12035E,
+0x0F1203F2,
+0x0F12FCBD,
+0x0F120300,
+0x0F12FF2E,
+0x0F12FE03,
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F124000, //TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F123C00, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+
+//s002A06D8
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+
+//add ki 11.02.18
+// SLOW AE
+// SLOW AE
+0x002A13F2,
+0x0F120014,// 0010 ae_GainIn_0_	//
+0x0F120032,// 0020	ae_GainIn_1_//					
+0x0F120078,// 0040	ae_GainIn_2_//					
+0x0F1200AA,// 0080	ae_GainIn_3_//					
+0x0F120100,// 0100	ae_GainIn_4_//					
+0x0F120140,// 0200	ae_GainIn_5_//					
+0x0F1201B8,// 0400	ae_GainIn_6_//					
+0x0F120400,// 0800	ae_GainIn_7_//					
+0x0F122000,// 2000	ae_GainIn_8_//	
+
+0x0F120046,//0050	// 0010	ae_GainOut_0_	p	 //						
+0x0F120078,//0070	// 0020	ae_GainOut_1_ p //						
+0x0F1200BE,//00A0	// 0040	ae_GainOut_2_	p	 //						
+0x0F1200DC,//00D0	// 0080	ae_GainOut_3_	p	 //						
+0x0F120100,// fix 0100	ae_GainOut_4_	//
+0x0F12010E,// 0200	ae_GainOut_5_	//
+0x0F120140,// 0400	ae_GainOut_6_	//
+0x0F1201F4,// 0800	ae_GainOut_7_	//
+0x0F120200,// 2000	ae_GainOut_8_	//
+
+
+0x002A13BC,
+0x0F120100,//0000ae_ContrastS_0_//
+0x0F120100,//000Cae_ContrastS_1_//
+0x0F120100,//001Cae_ContrastS_2_//
+0x0F120100,//0020ae_ContrastS_3_//
+0x0F120100,//0020ae_ContrastS_4_//
+0x0F120100,//0020ae_ContrastS_5_//
+0x0F120100,//0020ae_ContrastS_6_//
+0x0F120100,//0020ae_ContrastS_7_//
+
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+
+
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR  //MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+//AE_state
+0x002A04EE,
+0x0F120105, //010E //#lt_uLimitHigh
+0x0F1200FA, //00F5 //#lt_uLimitLow
+
+0x002A0500,                           
+0x0F120001,	 //lt_uInitPostToleranceCnt
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //3415//#lt_uMaxExp1
+0x002A0508,
+0x0F123415, //26e8//681F//#lt_uMaxExp2
+0x002A050C,
+0x0F123415, //26e8//8227//#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F123415, //681F //#lt_uCapMaxExp2
+0x002A051C,
+0x0F123415, //8227 //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F120200, //1E0 //#lt_uMaxAnGain1
+0x0F120240, //1E0 //#lt_uMaxAnGain2
+0x0F120340, //0300 //#lt_uMaxAnGain3
+0x0F120A00, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //#lt_uCapMaxAnGain1
+0x0F120240, //#lt_uCapMaxAnGain2
+0x0F120340, //300 //#lt_uCapMaxAnGain3
+0x0F120A00, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,                                                                        
+0x0F120101, //ae_WeightTbl_16[0]   0000
+0x0F120101, //ae_WeightTbl_16[1]   0000
+0x0F120101, //ae_WeightTbl_16[2]   0000
+0x0F120101, //ae_WeightTbl_16[3]   0000
+0x0F120101, //ae_WeightTbl_16[4]   0101
+0x0F120101, //ae_WeightTbl_16[5]   0101
+0x0F120101, //ae_WeightTbl_16[6]   0101
+0x0F120101, //ae_WeightTbl_16[7]   0101
+0x0F120101, //ae_WeightTbl_16[8]   0101
+0x0F120202, //ae_WeightTbl_16[9]   0201
+0x0F120202, //ae_WeightTbl_16[10]  0102
+0x0F120101, //ae_WeightTbl_16[11]  0101
+0x0F120101, //ae_WeightTbl_16[12]  0101
+0x0F120202, //ae_WeightTbl_16[13]  0202
+0x0F120202, //ae_WeightTbl_16[14]  0202
+0x0F120101, //ae_WeightTbl_16[15]  0101
+0x0F120101, //ae_WeightTbl_16[16]  0101
+0x0F120202, //ae_WeightTbl_16[17]  0202
+0x0F120202, //ae_WeightTbl_16[18]  0202
+0x0F120101, //ae_WeightTbl_16[19]  0101
+0x0F120101, //ae_WeightTbl_16[20]  0201
+0x0F120202, //ae_WeightTbl_16[21]  0202
+0x0F120202, //ae_WeightTbl_16[22]  0202
+0x0F120101, //ae_WeightTbl_16[23]  0102
+0x0F120101, //ae_WeightTbl_16[24]  0201
+0x0F120101, //ae_WeightTbl_16[25]  0202
+0x0F120101, //ae_WeightTbl_16[26]  0202
+0x0F120101, //ae_WeightTbl_16[27]  0102
+0x0F120101, //ae_WeightTbl_16[28]  0101
+0x0F120101, //ae_WeightTbl_16[29]  0101
+0x0F120101, //ae_WeightTbl_16[30]  0101
+0x0F120101, //ae_WeightTbl_16[31]  0101
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F12074D,//05F0 //awbb_GamutWidthThr1
+0x0F120433,//01F4 //awbb_GamutHeightThr1
+0x0F12002A,//006C //awbb_GamutWidthThr2
+0x0F12000C,//0038 //awbb_GamutHeightThr2
+0x002A1020,
+0x0F120020,	//000C //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A1028,
+0x0F120020,	//awbb_MinNumOfOutdoorPatches
+
+0x002A291A,
+0x0F120004, // #Mon_AWB_ByPassMode // [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A1048,
+0x0F1200C8,	//awbb_LowBr								
+0x0F12001E,	//awbb_LowBr_NBzone						
+
+0x002A1008,
+0x0F120020,	//awbb_NormalYThresh_y_low
+0x0F1200A0,	//awbb_NormalYThresh_y_high
+0x0F120002, //awbb_LowBrYThresh_y_low
+0x0F1200A0, //awbb_LowBrYThresh_y_high
+
+
+
+0x002A102E,
+0x0F12054D,	//awbb_MvEq_RBthresh
+
+0x002A1032,
+0x0F120000, //awbb_MovingScale10
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F120426,	//03C0//03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F12047E,	//03E2//03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F1203C6,	//0356//0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F120496,	//03FC//03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F120374,	//031E//031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1204A0,	//03FE//03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F12033A,	//02F0//02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F120498,	//03F0//03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F120312,	//02CA//02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F120478,	//03CC//03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202EA,	//02A8//02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F120440,	//037A//037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F1202C2,	//0280//0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F1203FA,	//033C//033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F12029A,	//0260//0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F1203BE,	//030A//030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120272,	//0242//0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F120398,	//02DC//02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F12024E,	//0228//0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F120372,	//02B2//02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F12022A,	//020E//020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120340,	//0290//02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F120206,	//01F8//01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120310,	//0276//0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201E2,	//01E8//01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F1202DE,	//0268//0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201C0,	//01DC//01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F1202AE,	//0256//0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201B4,	//01E0//01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F12027E,	//0238//0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201C0,	//01EC//01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F12024C,	//020E//020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F1201FA,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F12021C,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //awbb_IndoorGrZones_m_Grid
+0x002A0F80,
+0x0F1200A6, //awbb_IndoorGrZones_m_Boff
+0x002A0F7C,
+0x0F120011,
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12023E, //awbb_OutdoorGrZones_m_BGrid[0]
+0x0F120286, //awbb_OutdoorGrZones_m_BGrid[1]
+0x0F12022C, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202CC, //awbb_OutdoorGrZones_m_BGrid[3]
+0x0F12021A, //awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202F0, //awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120208, //awbb_OutdoorGrZones_m_BGrid[6]
+0x0F120316, //awbb_OutdoorGrZones_m_BGrid[7]
+0x0F1201F6, //awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202FE, //awbb_OutdoorGrZones_m_BGrid[9]
+0x0F1201E4, //awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202E8, //awbb_OutdoorGrZones_m_BGrid[11]
+0x0F1201D2, //awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202D2, //awbb_OutdoorGrZones_m_BGrid[13]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[14]
+0x0F1202BC, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[16]
+0x0F1202A6, //awbb_OutdoorGrZones_m_BGrid[17]
+0x0F1201D0, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F12028E, //awbb_OutdoorGrZones_m_BGrid[19]
+0x0F1201D6, //awbb_OutdoorGrZones_m_BGrid[20]
+0x0F120278, //awbb_OutdoorGrZones_m_BGrid[21]
+0x0F1201F8, //awbb_OutdoorGrZones_m_BGrid[22]
+0x0F120244, //awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C, //awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201D8, //awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F120400, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F120656, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F1205BE, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202E6, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120524, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F120290, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1204A0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120246, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F12041A, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201FE, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F1203AE, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201C0, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F120192, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F120306, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F120170, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F1202BA, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F12015C, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F12019C, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F12024E, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000B, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F120082, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+          
+0x002A11A8,
+0x0F12028E, //awbb_GridCon0xt_1[0]
+0x0F120306, //awbb_GridCon0xt_1[1]
+0x0F1203A6, //awbb_GridCon0xt_1[2]
+          
+0x0F120F86, //awbb_GridCon0xt_2[0]  0F86
+0x0F12105F, //awbb_GridCon0xt_2[1]  105F
+0x0F121160, //awbb_GridCon0xt_2[2]  11AA
+0x0F121161, //awbb_GridCon0xt_2[3]  1111
+0x0F1211F2, //awbb_GridCon0xt_2[4]  120C
+0x0F1212A1, //awbb_GridCon0xt_2[5]  126D
+          
+0x0F12008F, //awbb_GridCoeff_R_1
+0x0F1200D4, //awbb_GridCoeff_B_1
+0x0F1200C6, //awbb_GridCoeff_R_2
+0x0F1200A2, //awbb_GridCoeff_B_2
+          
+0x002A1118,
+0x0F120000, //0032//awbb_GridCorr_R[0][0]
+0x0F120000, //0012//awbb_GridCorr_R[0][1]
+0x0F120000, //0012//awbb_GridCorr_R[0][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060, //0050//awbb_GridCorr_R[0][5]
+0x0F120000, //0032//awbb_GridCorr_R[1][0]
+0x0F120000, //0012//awbb_GridCorr_R[1][1]
+0x0F120000, //0012//awbb_GridCorr_R[1][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060, //0050//awbb_GridCorr_R[1][5]
+0x0F120000, //0032//awbb_GridCorr_R[2][0]
+0x0F120000, //0012//awbb_GridCorr_R[2][1]
+0x0F120000, //0012//awbb_GridCorr_R[2][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060, //0050//awbb_GridCorr_R[2][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[0][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[1][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[2][5]
+          
+0x002A1160,
+0x0F120000, //awbb_GridCorr_R_Out[0][0]
+0x0F120000, //awbb_GridCorr_R_Out[0][1]
+0x0F120000, //awbb_GridCorr_R_Out[0][2]
+0x0F120000, //awbb_GridCorr_R_Out[0][3]
+0x0F120000, //awbb_GridCorr_R_Out[0][4]
+0x0F120000, //awbb_GridCorr_R_Out[0][5]
+0x0F120000, //awbb_GridCorr_R_Out[1][0]
+0x0F120000, //awbb_GridCorr_R_Out[1][1]
+0x0F120000, //awbb_GridCorr_R_Out[1][2]
+0x0F120000, //awbb_GridCorr_R_Out[1][3]
+0x0F120000, //awbb_GridCorr_R_Out[1][4]
+0x0F120000, //awbb_GridCorr_R_Out[1][5]
+0x0F120000, //awbb_GridCorr_R_Out[2][0]
+0x0F120000, //awbb_GridCorr_R_Out[2][1]
+0x0F120000, //awbb_GridCorr_R_Out[2][2]
+0x0F120000, //awbb_GridCorr_R_Out[2][3]
+0x0F120000, //awbb_GridCorr_R_Out[2][4]
+0x0F120000, //awbb_GridCorr_R_Out[2][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][5]
+
+   
+ // SLOW AWB
+0x002A110E, 	
+0x0F120258, //0258 awbb_GainsMaxMove //
+
+ //AWB Convergence Speed //
+0x002A11D6, 
+0x0F120008,
+0x0F12FFFF,//0190	awbb_WpFilterMaxThr//
+0x0F120010,//00A0	//awbb_WpFilterCoef p  //
+0x0F120020, //0004 awbb_WpFilterSize//
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201D4, //01DA 01CF 01CE 01C0 01D4 //TVAR_wbt_pBaseCcms[0] 
+0x0F12FFCD, //FFC4 FFC3 FFB9 FFCB FFB2 //TVAR_wbt_pBaseCcms[1] 
+0x0F12FFC4, //FFCD FFDD FFE8 FFE4 FFEE //TVAR_wbt_pBaseCcms[2] 
+0x0F12FF2A, //FF31 FF43 FF43 FF43 FF47 //TVAR_wbt_pBaseCcms[3] 
+0x0F120124, //012A 011D 011D 011D 012C //TVAR_wbt_pBaseCcms[4] 
+0x0F12FF73, //FF6B FF6B FF6B FF6B FF5C //TVAR_wbt_pBaseCcms[5] 
+0x0F12FFE1, //FFDA FFDA FFDA FFDA FFCE //TVAR_wbt_pBaseCcms[6] 
+0x0F12FFBD, //FFC3 FFD1 FFD1 FFD1 FFD6 //TVAR_wbt_pBaseCcms[7] 
+0x0F120159, //015F 0156 0156 0156 0162 //TVAR_wbt_pBaseCcms[8] 
+0x0F1200EF, //0100 00FF 00FC 00F7 011D //TVAR_wbt_pBaseCcms[9] 
+0x0F1200E0, //00DE 00CE 00CC 00D1 00C6 //TVAR_wbt_pBaseCcms[10]
+0x0F12FED9, //FECE FEE3 FEE9 FEE9 FED2 //TVAR_wbt_pBaseCcms[11]
+0x0F1200DA, //00D5 00CD 00CD 00CD 00C8 //TVAR_wbt_pBaseCcms[12]
+0x0F12FF57, //FF56 FF5E FF5E FF5E FF56 //TVAR_wbt_pBaseCcms[13]
+0x0F120119, //0123 0128 0128 0128 0139 //TVAR_wbt_pBaseCcms[14]
+0x0F12FF74, //FF73 FF7E FF7E FF7E FF75 //TVAR_wbt_pBaseCcms[15]
+0x0F1200DF, //00E9 00EC 00EC 00EC 00FB //TVAR_wbt_pBaseCcms[16]
+0x0F1200FF, //00FC 00F2 00F2 00F2 00F0 //TVAR_wbt_pBaseCcms[17]
+
+0x0F1201D4, //01D4 //TVAR_wbt_pBaseCcms[18]
+0x0F12FFCD, //FFB2 //TVAR_wbt_pBaseCcms[19]
+0x0F12FFC4, //FFEE //TVAR_wbt_pBaseCcms[20]
+0x0F12FF2A, //FF47 //TVAR_wbt_pBaseCcms[21]
+0x0F120124, //012C //TVAR_wbt_pBaseCcms[22]
+0x0F12FF73, //FF5C //TVAR_wbt_pBaseCcms[23]
+0x0F12FFE1, //FFCE //TVAR_wbt_pBaseCcms[24]
+0x0F12FFBD, //FFD6 //TVAR_wbt_pBaseCcms[25]
+0x0F120159, //0162 //TVAR_wbt_pBaseCcms[26]
+0x0F1200EF, //011D //TVAR_wbt_pBaseCcms[27]
+0x0F1200E0, //00C6 //TVAR_wbt_pBaseCcms[28]
+0x0F12FED9, //FED2 //TVAR_wbt_pBaseCcms[29]
+0x0F1200DA, //00C8 //TVAR_wbt_pBaseCcms[30]
+0x0F12FF57, //FF56 //TVAR_wbt_pBaseCcms[31]
+0x0F120119, //0139 //TVAR_wbt_pBaseCcms[32]
+0x0F12FF74, //FF75 //TVAR_wbt_pBaseCcms[33]
+0x0F1200DF, //00FB //TVAR_wbt_pBaseCcms[34]
+0x0F1200FF, //00F0 //TVAR_wbt_pBaseCcms[35]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[36]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[37]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[38]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[39]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[40]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[41]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[42]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[43]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[44]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[45]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[46]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[47]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[48]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[49]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[50]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[51]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[52]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[53]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[54]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[55]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[56]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[57]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[58]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[59]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[60]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[61]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[62]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[63]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[64]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[65]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[66]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[67]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[68]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[69]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[70]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[71]
+
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[72]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[73]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[74]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[75]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[76]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[77]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[78]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[79]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[80]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[81]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[82]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[83]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[84]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[85]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[86]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[87]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[88]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[89]
+          
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[90]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[91]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[92]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[93]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[94]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[95]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[96]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[97]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[98]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[99]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[100]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[101]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[102]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[103]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[104]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[105]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[106]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms 
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201BE, //0205 //01F8 //TVAR_wbt_pOutdoorCcm[0]
+0x0F12FFE4, //FF96 //FFAF //TVAR_wbt_pOutdoorCcm[1]
+0x0F120000, //FFDF //FFD3 //TVAR_wbt_pOutdoorCcm[2]
+0x0F12FEF9, //FEC8 //FEC4 //TVAR_wbt_pOutdoorCcm[3]
+0x0F120149, //01A4 //0191 //TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF70, //FF1C //FF33 //TVAR_wbt_pOutdoorCcm[5]
+0x0F12003C, //FFF7 //FFED //TVAR_wbt_pOutdoorCcm[6]
+0x0F120023, //000C //0017 //TVAR_wbt_pOutdoorCcm[7]
+0x0F1201DD, //0211 //0210 //TVAR_wbt_pOutdoorCcm[8]
+0x0F1200D4, //0107 //00E3 //TVAR_wbt_pOutdoorCcm[9]
+0x0F1200F8, //00F3 //0107 //TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF74, //FF1F //FF2F //TVAR_wbt_pOutdoorCcm[11]
+0x0F120212, //0220 //0220 //TVAR_wbt_pOutdoorCcm[12]
+0x0F120039, //FFE7 //FFE7 //TVAR_wbt_pOutdoorCcm[13]
+0x0F120184, //01A1 //01A1 //TVAR_wbt_pOutdoorCcm[14]
+0x0F12FF28, //FEC7 //FEC8 //TVAR_wbt_pOutdoorCcm[15]
+0x0F120133, //016D //017D //TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153 //0142 //TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F120040, //4A //40 //4A //0049 //#afit_uNoiseIndInDoor_0_
+0x0F120048, //48 //4E //005F //#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB //#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0 //#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220 //#afit_uNoiseIndInDoor_4_
+
+
+0x002A08C0,
+0x0F120030, //0007 //700008C0 //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //700008C2 //AFIT16_CONTRAST
+0x0F120010, //0000 //700008C4 //AFIT16_SATURATION
+0x0F120000, //0000 //700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //700008C8 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700008CA //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700008CC 
+0x0F1203FF, //03FF //700008CE //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700008D0 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700008D2 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700008D4 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700008D6 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700008D8 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700008DA //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700008DC //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700008DE //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700008E0 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700008E2 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0010 //700008E4 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0010 //700008E6 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //01F4 //700008E8 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C //700008EA //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008 //700008EC //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700008EE //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700008F0 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700008F2 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700008F4 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700008F6 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700008F8 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700008FA //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700008FC //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700008FE //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000900 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000902 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000904 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //09E8 //70000906 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000908 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //7000090A //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //7000090C //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //4000 //7000090E 
+0x0F125003, //7803 //70000910 
+0x0F123228, //3C50 //70000912 
+0x0F120032, //003C //70000914 
+0x0F121E80, //1E80 //70000916 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000918 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //7000091A //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //7000091C //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //7000091E //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //0F00 //70000920 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000922 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000924 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000926 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000928 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //7000092A //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //7000092C //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //7000092E //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000930 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000932 
+0x0F120609, //0609 //70000934 
+0x0F122C07, //2C07 //70000936 
+0x0F12142C, //142C //70000938 
+0x0F120518, //0718 //7000093A //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F128005, //8007 //7000093C //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594, //0880 //7000093E //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0B50 //70000940 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000942 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000944 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000946 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4601 //70000948 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B, //C844 //7000094A //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125038, //50C8 //7000094C //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //7000094E //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0003 //70000950 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //1C01 //70000952 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //0714 //70000954 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1464 //70000956 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125F01, //5A04 //70000958 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //3C1E //7000095A //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //400F //7000095C //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //7000095E //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1403 //70000960 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0114 //70000962 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000964 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //4446 //70000966 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //646E //70000968 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //7000096A //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //7000096C //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //7000096E //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000970 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000972 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000974 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000976 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000978 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //7000097A //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //7000097C //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1414 //7000097E //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000980 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //4601 //70000982 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //6E44 //70000984 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2864 //70000986 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000988 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //7000098A //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //7000098C //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //7000098E //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000990 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000992 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000994 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000996 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000998 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //7000099A //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //7000099C 
+0x0F120030, //0000 //7000099E //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //700009A0 //AFIT16_CONTRAST
+0x0F120010, //0000 //700009A2 //AFIT16_SATURATION
+0x0F120000, //0000 //700009A4 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //700009A6 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700009A8 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700009AA 
+0x0F1203FF, //03FF //700009AC //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700009AE //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700009B0 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700009B2 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700009B4 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700009B6 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700009B8 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700009BA //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700009BC //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700009BE //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700009C0 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //700009C2 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //700009C4 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //700009C6 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E //700009C8 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //700009CA //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700009CC //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700009CE //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700009D0 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700009D2 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700009D4 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700009D6 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700009D8 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700009DA //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700009DC //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //700009DE //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //700009E0 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //700009E2 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //05E8 //700009E4 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //700009E6 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //700009E8 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //700009EA //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000 //700009EC        
+0x0F125003, //5003 //700009EE        
+0x0F123228, //3228 //700009F0        
+0x0F120032, //0032 //700009F2        
+0x0F121E80, //1E80 //700009F4 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //700009F6 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //700009F8 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //700009FA //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //700009FC //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //1400 //700009FE //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000A00 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000A02 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000A04 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000A06 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000A08 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000A0A //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000A0C //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000A0E //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000A10        
+0x0F120609, //0609 //70000A12        
+0x0F122C07, //2C07 //70000A14        
+0x0F12142C, //142C //70000A16        
+0x0F120518, //0518 //70000A18 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000A1A //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594, //0580 //70000A1C //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000A1E //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000A20 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000A22 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000A24 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000A26 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B, //444B 494B //70000A28 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125038, //503C 5044 //70000A2A //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000A2C //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0503 //70000A2E //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //0D02 //70000A30 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //071E //70000A32 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1432 //70000A34 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125F01, //5A01 //70000A36 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //281E //70000A38 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //200F //70000A3A //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000A3C //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1E03 //70000A3E //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //011E //70000A40 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000A42 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //3A3C //70000A44 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //585A //70000A46 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000A48 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000A4A //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //70000A4C //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000A4E //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000A50 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000A52 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000A54 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000A56 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000A58 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000A5A //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1E1E //70000A5C //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000A5E //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //3C01 //70000A60 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //5A3A //70000A62 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2858 //70000A64 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000A66 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //70000A68 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //70000A6A //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //70000A6C //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000A6E //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000A70 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000A72 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000A74 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000A76 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000A78 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000A7A 
+0x0F120000, //0000 //70000A7C //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000A7E //AFIT16_CONTRAST
+0x0F120000, //0000 //70000A80 //AFIT16_SATURATION
+0x0F120000, //0000 //70000A82 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000A84 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000A86 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000A88        
+0x0F1203FF, //03FF //70000A8A //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000A8C //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000A8E //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000A90 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000A92 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000A94 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //70000A96 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000A98 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000A9A //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //70000A9C //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000A9E //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000AA0 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000AA2 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000AA4 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000AA6 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000AA8 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //003C //70000AAA //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //70000AAC //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //003C //70000AAE //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //70000AB0 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000AB2 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000AB4 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000AB6 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000AB8 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000ABA //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000ABC //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000ABE //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000AC0 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000AC2 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000AC4 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000AC6 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000AC8 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000ACA        
+0x0F122803, //2803 //70000ACC        
+0x0F12261E, //261E //70000ACE        
+0x0F120026, //0026 //70000AD0        
+0x0F121E80, //1E80 //70000AD2 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000AD4 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000AD6 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000AD8 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F124C0A, //3C0A //70000ADA //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122B12, //2300 //70000ADC //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000ADE //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000AE0 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000AE2 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000AE4 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000AE6 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000AE8 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000AEA //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000AEC //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000AEE        
+0x0F120609, //0609 //70000AF0        
+0x0F121C07, //1C07 //70000AF2        
+0x0F121014, //1014 //70000AF4        
+0x0F120510, //0510 //70000AF6 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000AF8 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000AFA //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000AFC //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000AFE //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000B00 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000B02 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000B04 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000B06 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000B08 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000B0A //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121B03, //1C03 //70000B0C //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F123003, //0D0C //70000B0E //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000B10 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000B12 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F128601, //6401 //70000B14 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12283E, //282D //70000B16 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000B18 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000B1A //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //2803 //70000B1C //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0128 //70000B1E //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000B20 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //2224 //70000B22 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //3236 //70000B24 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000B26 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000B28 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0410 //70000B2A //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //141E //70000B2C //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122807, //FF07 //70000B2E //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000B30 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4050 //70000B32 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //0F0F //70000B34 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000B36 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000B38 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F122828, //2828 //70000B3A //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000B3C //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //2401 //70000B3E //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //3622 //70000B40 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //2832 //70000B42 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000B44 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1003 //70000B46 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1E04 //70000B48 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //0714 //70000B4A //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000B4C //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5004 //70000B4E //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0F40 //70000B50 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //400F //70000B52 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000B54 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000B56 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000B58        
+0x0F120000, //0000 //70000B5A //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000B5C //AFIT16_CONTRAST
+0x0F120000, //0000 //70000B5E //AFIT16_SATURATION
+0x0F120000, //0000 //70000B60 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000B62 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000B64 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000B66 
+0x0F1203FF, //03FF //70000B68 //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000B6A //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000B6C //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000B6E //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000B70 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000B72 //AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8 //70000B74 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000B76 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000B78 //AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050 //70000B7A //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000B7C //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000B7E //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000B80 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000B82 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000B84 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000B86 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //002D //70000B88 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //70000B8A //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //002D //70000B8C //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //70000B8E //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000B90 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000B92 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000B94 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000B96 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000B98 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000B9A //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000B9C //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000B9E //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000BA0 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000BA2 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000BA4 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000BA6 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000BA8 
+0x0F122303, //2303 //70000BAA 
+0x0F12231A, //231A //70000BAC 
+0x0F120023, //0023 //70000BAE 
+0x0F121E80, //1E80 //70000BB0 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000BB2 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000BB4 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000BB6 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F127D0A, //3C0A //70000BB8 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122C24, //2300 //70000BBA //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000BBC //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000BBE //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000BC0 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //70000BC2 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000BC4 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000BC6 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000BC8 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //70000BCA //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120306, //0306 //70000BCC 
+0x0F120509, //0509 //70000BCE 
+0x0F122806, //2806 //70000BD0 
+0x0F121428, //1428 //70000BD2 
+0x0F120518, //0518 //70000BD4 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000BD6 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000BD8 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000BDA //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000BDC //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000BDE //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000BE0 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000BE2 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000BE4 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000BE6 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000BE8 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F122B03, //1C03 //70000BEA //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F126303, //0D0C //70000BEC //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000BEE //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000BF0 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12CC01, //6401 //70000BF2 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12283E, //282D //70000BF4 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000BF6 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000BF8 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //3C03 //70000BFA //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //013C //70000BFC //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000BFE //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //1C1E //70000C00 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1E22 //70000C02 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000C04 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000C06 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0214 //70000C08 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //0E14 //70000C0A //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122808, //FF06 //70000C0C //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000C0E //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4052 //70000C10 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //150C //70000C12 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000C14 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000C16 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F123C3C, //3C3C //70000C18 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000C1A //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //1E01 //70000C1C //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //221C //70000C1E //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //281E //70000C20 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000C22 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1403 //70000C24 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1402 //70000C26 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //060E //70000C28 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000C2A //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5204 //70000C2C //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0C40 //70000C2E //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //4015 //70000C30 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000C32 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000C34 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000C36 
+0x0F120000, //0000 //0000 //70000C38 //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //0000 //70000C3A //AFIT16_CONTRAST
+0x0F120000, //0000 //0000 //70000C3C //AFIT16_SATURATION
+0x0F120000, //0000 //0000 //70000C3E //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //0000 //70000C40 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //00C1 //70000C42 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //0000 //70000C44
+0x0F1203FF, //03FF //03FF //70000C46 //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //0008 //70000C48 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251 //017C //70000C4A //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //03FF //70000C4C //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //000C //70000C4E //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //0010 //70000C50 //AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032 //0032 //70000C52 //AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A //028A //70000C54 //AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032 //0032 //70000C56 //AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4 //01F4 //70000C58 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //0070 //70000C5A //AFIT16_demsharpmix1_iTune
+0x0F120002, //0002 //0002 //70000C5C //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //0000 //70000C5E //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //0320 //70000C60 //AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044 //0070 //70000C62 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //0014 //70000C64 //AFIT16_Sharpening_iHighSharpClamp
+0x0F120044, //0046 //0046 //70000C66 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //0019 //70000C68 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120044, //0046 //0046 //70000C6A //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //0019 //70000C6C //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //0A24 //70000C6E //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //1701 //70000C70 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //0229 //70000C72 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503 //0503 //70000C74 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F12080F, //080F //0101 //70000C76 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120808, //0808 //0101 //70000C78 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //0000 //70000C7A //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1200FF, //00FF //02FF //70000C7C //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D //0396 //70000C7E //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //1414 //70000C80 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //0301 //70000C82 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //0007 //70000C84 //AFIT8_sddd8a_iSquaresRounding [7:0]                        
+0x0F121000, //1000 //1000 //70000C86 
+0x0F122003, //2003 //2003 //70000C88 
+0x0F121020, //1020 //1020 //70000C8A 
+0x0F120010, //0010 //0010 //70000C8C 
+0x0F121EFF, //1EFF //1E80 //70000C8E //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E06, //1E06 //1E06 //70000C90 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12060A, //060A //030C //70000C92 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120306, //0306 //0103 //70000C94 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12810A, //8B0A //5A0A //70000C96 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F1215C4, //2837 //2D00 //70000C98 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120107, //0110 //0100 //70000C9A //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //FF00 //70000C9C //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //0200 //70000C9E //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //1E10 //70000CA0 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //0000 //70000CA2 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //0009 //70000CA4 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //0406 //70000CA6 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //0705 //70000CA8 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120305, //0305 //0305 //70000CAA 
+0x0F120609, //0609 //0609 //70000CAC 
+0x0F122C07, //2C07 //2C07 //70000CAE 
+0x0F12142C, //142C //142C //70000CB0 
+0x0F120B18, //0B18 //0B18 //70000CB2 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F12800B, //800B //800B //70000CB4 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]        
+0x0F120080, //0080 //0080 //70000CB6 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //0080 //70000CB8 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //0080 //70000CBA //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F125050, //5050 //0101 //70000CBC //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120101, //0101 //0A0A //70000CBE //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F123201, //3201 //3201 //70000CC0 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F120032, //1832 //1428 //70000CC2 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F122100, //210C //100C //70000CC4 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120A00, //0A00 //0500 //70000CC6 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F125004, //1E04 //1E02 //70000CC8 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F12A400, //0A08 //040C //70000CCA //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12070C, //070C //0828 //70000CCC //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F123264, //3264 //5064 //70000CCE //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12F802, //5A02 //4605 //70000CD0 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12103E, //1040 //1E68 //70000CD2 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F124012, //4012 //201E //70000CD4 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120604, //0604 //0604 //70000CD6 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F125006, //4606 //4606 //70000CD8 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120150, //0146 //0146 //70000CDA //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //0101 //70000CDC //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F123232, //1C18 //1C18 //70000CDE //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1819 //1819 //70000CE0 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120021, //0028 //0028 //70000CE2 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12040A, //030A //030A //70000CE4 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F12085E, //0514 //0514 //70000CE6 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120C0A, //0C14 //0C14 //70000CE8 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF05 //FF05 //70000CEA //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120119, //0432 //0432 //70000CEC //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F12406A, //4052 //4052 //70000CEE //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //1514 //1514 //70000CF0 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440 //0440 //70000CF2 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120606, //0302 //0302 //70000CF4 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F124646, //4646 //4646 //70000CF6 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //0101 //70000CF8 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F123201, //1801 //1801 //70000CFA //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F120032, //191C //191C //70000CFC //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122100, //2818 //2818 //70000CFE //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00 //0A00 //70000D00 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125E04, //1403 //1403 //70000D02 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120A08, //1405 //1405 //70000D04 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12070C, //050C //050C //70000D06 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121932, //32FF //32FF //70000D08 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //5204 //5204 //70000D0A //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120840, //1440 //1440 //70000D0C //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124009, //4015 //4015 //70000D0E //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120604, //0204 //0204 //70000D10 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120006, //0003 //0003 //70000D12 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //0001 //70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F12BF02, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+
+
+0x002a3fea,
+0x0f120800, //analog filter update Green
+
+
+// TNP_Regs_bUseAccurateFR
+0x00287000,
+0x002A3FE4,
+0x0F120001, // on/off TNP_Regs_bAccuDynamicFR
+0x0F1234A2, // on/off TNP_Regs_usMinAccuDynamicFrTme
+0x0F1240FD, // on/off TNP_Regs_usMaxAccuDynamicFrTme
+};
+#else
+#define S5K5CCGX_720P_INIT_REG s5k5ccgx_1280_720_Preview
+static const u32 s5k5ccgx_1280_720_Preview[] = {
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000                            //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A, //p10
+// Start of Patch data
+// Start of Patch data
+0x00287000,
+0x002A352C,
+0x0F12B570, //7000352C 
+0x0F124A24, //7000352E 
+0x0F124924, //70003530 
+0x0F124825, //70003532 
+0x0F124B25, //70003534 
+0x0F122500, //70003536 
+0x0F12801D, //70003538 
+0x0F12C004, //7000353A 
+0x0F126001, //7000353C 
+0x0F124924, //7000353E 
+0x0F124824, //70003540 
+0x0F12F000, //70003542 
+0x0F12FBBD, //70003544 
+0x0F124924, //70003546 
+0x0F124824, //70003548 
+0x0F12F000, //7000354A 
+0x0F12FBB9, //7000354C 
+0x0F124824, //7000354E 
+0x0F124E24, //70003550 
+0x0F126430, //70003552 
+0x0F124924, //70003554 
+0x0F124825, //70003556 
+0x0F12F000, //70003558 
+0x0F12FBB2, //7000355A 
+0x0F124924, //7000355C 
+0x0F120030, //7000355E 
+0x0F123080, //70003560 
+0x0F126141, //70003562 
+0x0F124C23, //70003564 
+0x0F128365, //70003566 
+0x0F124923, //70003568 
+0x0F124824, //7000356A 
+0x0F12F000, //7000356C 
+0x0F12FBA8, //7000356E 
+0x0F124923, //70003570 
+0x0F124824, //70003572 
+0x0F12F000, //70003574 
+0x0F12FBA4, //70003576 
+0x0F124923, //70003578 
+0x0F124824, //7000357A 
+0x0F12F000, //7000357C 
+0x0F12FBA0, //7000357E 
+0x0F124923, //70003580 
+0x0F124824, //70003582 
+0x0F12F000, //70003584 
+0x0F12FB9C, //70003586 
+0x0F128125, //70003588 
+0x0F124923, //7000358A 
+0x0F124823, //7000358C 
+0x0F12F000, //7000358E 
+0x0F12FB97, //70003590 
+0x0F124923, //70003592 
+0x0F124823, //70003594 
+0x0F12F000, //70003596 
+0x0F12FB93, //70003598 
+0x0F1283A5, //7000359A 
+0x0F124922, //7000359C 
+0x0F124823, //7000359E 
+0x0F12F000, //700035A0 
+0x0F12FB8E, //700035A2 
+0x0F122101, //700035A4 
+0x0F120349, //700035A6 
+0x0F120020, //700035A8 
+0x0F123020, //700035AA 
+0x0F128041, //700035AC 
+0x0F122185, //700035AE 
+0x0F128081, //700035B0 
+0x0F12491F, //700035B2 
+0x0F1280C1, //700035B4 
+0x0F12481F, //700035B6 
+0x0F126730, //700035B8 
+0x0F12BC70, //700035BA 
+0x0F12BC08, //700035BC 
+0x0F124718, //700035BE 
+0x0F1200CA, //700035C0 
+0x0F125CC1, //700035C2 
+0x0F1203BD, //700035C4 
+0x0F120000, //700035C6 
+0x0F121C08, //700035C8 
+0x0F127000, //700035CA 
+0x0F123290, //700035CC 
+0x0F127000, //700035CE 
+0x0F123657, //700035D0 
+0x0F127000, //700035D2 
+0x0F12D9E7, //700035D4 
+0x0F120000, //700035D6 
+0x0F12383F, //700035D8 
+0x0F127000, //700035DA 
+0x0F12395D, //700035DC 
+0x0F120000, //700035DE 
+0x0F1238D1, //700035E0 
+0x0F127000, //700035E2 
+0x0F120000, //700035E4 
+0x0F127000, //700035E6 
+0x0F12399D, //700035E8 
+0x0F127000, //700035EA 
+0x0F12F903, //700035EC 
+0x0F120000, //700035EE 
+0x0F123AC1, //700035F0 
+0x0F127000, //700035F2 
+0x0F123FC8, //700035F4 
+0x0F127000, //700035F6 
+0x0F12368F, //700035F8 
+0x0F127000, //700035FA 
+0x0F12495F, //700035FC 
+0x0F120000, //700035FE 
+0x0F1236ED, //70003600 
+0x0F127000, //70003602 
+0x0F12E421, //70003604 
+0x0F120000, //70003606 
+0x0F1237AB, //70003608 
+0x0F127000, //7000360A 
+0x0F12216D, //7000360C 
+0x0F120000, //7000360E 
+0x0F12381F, //70003610 
+0x0F127000, //70003612 
+0x0F120179, //70003614 
+0x0F120001, //70003616 
+0x0F123BD5, //70003618 
+0x0F127000, //7000361A 
+0x0F1204C9, //7000361C 
+0x0F120000, //7000361E 
+0x0F123B25, //70003620 
+0x0F127000, //70003622 
+0x0F125027, //70003624 
+0x0F120000, //70003626 
+0x0F123BE1, //70003628 
+0x0F127000, //7000362A 
+0x0F1242B7, //7000362C 
+0x0F120000, //7000362E 
+0x0F1207FF, //70003630 
+0x0F120000, //70003632 
+0x0F123C5F, //70003634 
+0x0F127000, //70003636 
+0x0F12B570, //70003638 
+0x0F12000D, //7000363A 
+0x0F124CFC, //7000363C 
+0x0F128821, //7000363E 
+0x0F12F000, //70003640 
+0x0F12FB46, //70003642 
+0x0F128820, //70003644 
+0x0F124AFB, //70003646 
+0x0F120081, //70003648 
+0x0F125055, //7000364A 
+0x0F121C40, //7000364C 
+0x0F128020, //7000364E 
+0x0F12BC70, //70003650 
+0x0F12BC08, //70003652 
+0x0F124718, //70003654 
+0x0F126801, //70003656 
+0x0F120409, //70003658 
+0x0F120C09, //7000365A 
+0x0F126840, //7000365C 
+0x0F120400, //7000365E 
+0x0F120C00, //70003660 
+0x0F124AF5, //70003662 
+0x0F128992, //70003664 
+0x0F122A00, //70003666 
+0x0F12D00D, //70003668 
+0x0F122300, //7000366A 
+0x0F121A80, //7000366C 
+0x0F12D400, //7000366E 
+0x0F120003, //70003670 
+0x0F120418, //70003672 
+0x0F120C00, //70003674 
+0x0F124BF1, //70003676 
+0x0F121851, //70003678 
+0x0F12891B, //7000367A 
+0x0F12428B, //7000367C 
+0x0F12D300, //7000367E 
+0x0F12000B, //70003680 
+0x0F120419, //70003682 
+0x0F120C09, //70003684 
+0x0F124AEE, //70003686 
+0x0F128151, //70003688 
+0x0F128190, //7000368A 
+0x0F124770, //7000368C 
+0x0F12B510, //7000368E 
+0x0F124CEC, //70003690 
+0x0F1248ED, //70003692 
+0x0F1278A1, //70003694 
+0x0F122900, //70003696 
+0x0F12D101, //70003698 
+0x0F1287C1, //7000369A 
+0x0F12E004, //7000369C 
+0x0F127AE1, //7000369E 
+0x0F122900, //700036A0 
+0x0F12D001, //700036A2 
+0x0F122101, //700036A4 
+0x0F1287C1, //700036A6 
+0x0F12F000, //700036A8 
+0x0F12FB1A, //700036AA 
+0x0F1249E7, //700036AC 
+0x0F128B08, //700036AE 
+0x0F1206C2, //700036B0 
+0x0F12D50A, //700036B2 
+0x0F127AA2, //700036B4 
+0x0F120652, //700036B6 
+0x0F12D507, //700036B8 
+0x0F122210, //700036BA 
+0x0F124390, //700036BC 
+0x0F128308, //700036BE 
+0x0F1248E3, //700036C0 
+0x0F127AE1, //700036C2 
+0x0F126B00, //700036C4 
+0x0F12F000, //700036C6 
+0x0F12FB13, //700036C8 
+0x0F1248DB, //700036CA 
+0x0F1289C0, //700036CC 
+0x0F122801, //700036CE 
+0x0F12D109, //700036D0 
+0x0F1278A0, //700036D2 
+0x0F122800, //700036D4 
+0x0F12D006, //700036D6 
+0x0F127AE0, //700036D8 
+0x0F122800, //700036DA 
+0x0F12D003, //700036DC 
+0x0F127AA0, //700036DE 
+0x0F122140, //700036E0 
+0x0F124308, //700036E2 
+0x0F1272A0, //700036E4 
+0x0F12BC10, //700036E6 
+0x0F12BC08, //700036E8 
+0x0F124718, //700036EA 
+0x0F12B570, //700036EC 
+0x0F124DD7, //700036EE 
+0x0F124CD7, //700036F0 
+0x0F128B28, //700036F2 
+0x0F120701, //700036F4 
+0x0F12D507, //700036F6 
+0x0F122108, //700036F8 
+0x0F124388, //700036FA 
+0x0F128328, //700036FC 
+0x0F1249D5, //700036FE 
+0x0F126B20, //70003700 
+0x0F126B89, //70003702 
+0x0F12F000, //70003704 
+0x0F12FAFC, //70003706 
+0x0F128B28, //70003708 
+0x0F1206C1, //7000370A 
+0x0F12D5A0, //7000370C 
+0x0F1249CD, //7000370E 
+0x0F127A8A, //70003710 
+0x0F120652, //70003712 
+0x0F12D49C, //70003714 
+0x0F122210, //70003716 
+0x0F124390, //70003718 
+0x0F128328, //7000371A 
+0x0F127AC9, //7000371C 
+0x0F126B20, //7000371E 
+0x0F12F000, //70003720 
+0x0F12FAE6, //70003722 
+0x0F12E794, //70003724 
+0x0F12B5F8, //70003726 
+0x0F1249CB, //70003728 
+0x0F128F08, //7000372A 
+0x0F12000C, //7000372C 
+0x0F123480, //7000372E 
+0x0F122800, //70003730 
+0x0F12D000, //70003732 
+0x0F128360, //70003734 
+0x0F122000, //70003736 
+0x0F128708, //70003738 
+0x0F124DC8, //7000373A 
+0x0F1226FF, //7000373C 
+0x0F128828, //7000373E 
+0x0F121C76, //70003740 
+0x0F122702, //70003742 
+0x0F122803, //70003744 
+0x0F12D112, //70003746 
+0x0F128868, //70003748 
+0x0F122800, //7000374A 
+0x0F12D10F, //7000374C 
+0x0F1288E8, //7000374E 
+0x0F122800, //70003750 
+0x0F12D10C, //70003752 
+0x0F12F000, //70003754 
+0x0F12FADC, //70003756 
+0x0F122800, //70003758 
+0x0F12D008, //7000375A 
+0x0F128B60, //7000375C 
+0x0F122800, //7000375E 
+0x0F12D001, //70003760 
+0x0F1280EE, //70003762 
+0x0F1280AF, //70003764 
+0x0F122001, //70003766 
+0x0F127268, //70003768 
+0x0F12F000, //7000376A 
+0x0F12FAD9, //7000376C 
+0x0F128828, //7000376E 
+0x0F122802, //70003770 
+0x0F12D10E, //70003772 
+0x0F128868, //70003774 
+0x0F122800, //70003776 
+0x0F12D10B, //70003778 
+0x0F1288E8, //7000377A 
+0x0F122800, //7000377C 
+0x0F12D108, //7000377E 
+0x0F128B60, //70003780 
+0x0F122800, //70003782 
+0x0F12D001, //70003784 
+0x0F1280EE, //70003786 
+0x0F1280AF, //70003788 
+0x0F122001, //7000378A 
+0x0F127268, //7000378C 
+0x0F12F000, //7000378E 
+0x0F12FAC7, //70003790 
+0x0F1288E8, //70003792 
+0x0F122800, //70003794 
+0x0F12D006, //70003796 
+0x0F121FC1, //70003798 
+0x0F1239FD, //7000379A 
+0x0F12D003, //7000379C 
+0x0F122001, //7000379E 
+0x0F12BCF8, //700037A0 
+0x0F12BC08, //700037A2 
+0x0F124718, //700037A4 
+0x0F122000, //700037A6 
+0x0F12E7FA, //700037A8 
+0x0F12B570, //700037AA 
+0x0F124CAC, //700037AC 
+0x0F128860, //700037AE 
+0x0F122800, //700037B0 
+0x0F12D00C, //700037B2 
+0x0F128820, //700037B4 
+0x0F124DA3, //700037B6 
+0x0F122800, //700037B8 
+0x0F12D009, //700037BA 
+0x0F120029, //700037BC 
+0x0F1231A0, //700037BE 
+0x0F127AC9, //700037C0 
+0x0F122900, //700037C2 
+0x0F12D004, //700037C4 
+0x0F127AA8, //700037C6 
+0x0F122180, //700037C8 
+0x0F124308, //700037CA 
+0x0F1272A8, //700037CC 
+0x0F12E73F, //700037CE 
+0x0F122800, //700037D0 
+0x0F12D003, //700037D2 
+0x0F12F7FF, //700037D4 
+0x0F12FFA7, //700037D6 
+0x0F122800, //700037D8 
+0x0F12D1F8, //700037DA 
+0x0F122000, //700037DC 
+0x0F128060, //700037DE 
+0x0F128820, //700037E0 
+0x0F122800, //700037E2 
+0x0F12D003, //700037E4 
+0x0F122008, //700037E6 
+0x0F12F000, //700037E8 
+0x0F12FAA2, //700037EA 
+0x0F12E00B, //700037EC 
+0x0F12489C, //700037EE 
+0x0F123020, //700037F0 
+0x0F128880, //700037F2 
+0x0F122800, //700037F4 
+0x0F12D103, //700037F6 
+0x0F127AA8, //700037F8 
+0x0F122101, //700037FA 
+0x0F124308, //700037FC 
+0x0F1272A8, //700037FE 
+0x0F122010, //70003800 
+0x0F12F000, //70003802 
+0x0F12FA95, //70003804 
+0x0F128820, //70003806 
+0x0F122800, //70003808 
+0x0F12D1E0, //7000380A 
+0x0F12488A, //7000380C 
+0x0F1289C0, //7000380E 
+0x0F122801, //70003810 
+0x0F12D1DC, //70003812 
+0x0F127AA8, //70003814 
+0x0F1221BF, //70003816 
+0x0F124008, //70003818 
+0x0F1272A8, //7000381A 
+0x0F12E718, //7000381C 
+0x0F126800, //7000381E 
+0x0F124990, //70003820 
+0x0F128188, //70003822 
+0x0F124890, //70003824 
+0x0F122201, //70003826 
+0x0F128981, //70003828 
+0x0F124890, //7000382A 
+0x0F120252, //7000382C 
+0x0F124291, //7000382E 
+0x0F12D902, //70003830 
+0x0F122102, //70003832 
+0x0F128181, //70003834 
+0x0F124770, //70003836 
+0x0F122101, //70003838 
+0x0F128181, //7000383A 
+0x0F124770, //7000383C 
+0x0F12B5F1, //7000383E 
+0x0F124E80, //70003840 
+0x0F128834, //70003842 
+0x0F122C00, //70003844 
+0x0F12D03F, //70003846 
+0x0F122001, //70003848 
+0x0F122C08, //7000384A 
+0x0F12D000, //7000384C 
+0x0F122000, //7000384E 
+0x0F1270B0, //70003850 
+0x0F124D7F, //70003852 
+0x0F122800, //70003854 
+0x0F12D009, //70003856 
+0x0F12F000, //70003858 
+0x0F12FA72, //7000385A 
+0x0F120028, //7000385C 
+0x0F1238F0, //7000385E 
+0x0F126328, //70003860 
+0x0F127AB0, //70003862 
+0x0F12217E, //70003864 
+0x0F124008, //70003866 
+0x0F1272B0, //70003868 
+0x0F12E00F, //7000386A 
+0x0F124F7A, //7000386C 
+0x0F123780, //7000386E 
+0x0F128B78, //70003870 
+0x0F122800, //70003872 
+0x0F12D005, //70003874 
+0x0F12F000, //70003876 
+0x0F12FA6B, //70003878 
+0x0F122000, //7000387A 
+0x0F128378, //7000387C 
+0x0F124976, //7000387E 
+0x0F128708, //70003880 
+0x0F122000, //70003882 
+0x0F12F000, //70003884 
+0x0F12FA6C, //70003886 
+0x0F124879, //70003888 
+0x0F126328, //7000388A 
+0x0F1278B1, //7000388C 
+0x0F122700, //7000388E 
+0x0F120038, //70003890 
+0x0F122900, //70003892 
+0x0F12D008, //70003894 
+0x0F124972, //70003896 
+0x0F123920, //70003898 
+0x0F128ACA, //7000389A 
+0x0F122A00, //7000389C 
+0x0F12D003, //7000389E 
+0x0F128B09, //700038A0 
+0x0F122900, //700038A2 
+0x0F12D000, //700038A4 
+0x0F122001, //700038A6 
+0x0F127170, //700038A8 
+0x0F122C02, //700038AA 
+0x0F12D102, //700038AC 
+0x0F124868, //700038AE 
+0x0F123860, //700038B0 
+0x0F126328, //700038B2 
+0x0F122201, //700038B4 
+0x0F122C02, //700038B6 
+0x0F12D000, //700038B8 
+0x0F122200, //700038BA 
+0x0F124861, //700038BC 
+0x0F122110, //700038BE 
+0x0F12300A, //700038C0 
+0x0F12F000, //700038C2 
+0x0F12FA55, //700038C4 
+0x0F128037, //700038C6 
+0x0F129900, //700038C8 
+0x0F120020, //700038CA 
+0x0F12600C, //700038CC 
+0x0F12E767, //700038CE 
+0x0F12B538, //700038D0 
+0x0F124865, //700038D2 
+0x0F124669, //700038D4 
+0x0F123848, //700038D6 
+0x0F12F000, //700038D8 
+0x0F12FA52, //700038DA 
+0x0F124A5E, //700038DC 
+0x0F124862, //700038DE 
+0x0F128F51, //700038E0 
+0x0F122400, //700038E2 
+0x0F123020, //700038E4 
+0x0F122900, //700038E6 
+0x0F12D00A, //700038E8 
+0x0F128754, //700038EA 
+0x0F126941, //700038EC 
+0x0F126451, //700038EE 
+0x0F126491, //700038F0 
+0x0F12466B, //700038F2 
+0x0F128819, //700038F4 
+0x0F1287D1, //700038F6 
+0x0F12885B, //700038F8 
+0x0F120011, //700038FA 
+0x0F123140, //700038FC 
+0x0F12800B, //700038FE 
+0x0F128F91, //70003900 
+0x0F122900, //70003902 
+0x0F12D002, //70003904 
+0x0F128794, //70003906 
+0x0F126940, //70003908 
+0x0F126490, //7000390A 
+0x0F12F000, //7000390C 
+0x0F12FA40, //7000390E 
+0x0F12BC38, //70003910 
+0x0F12BC08, //70003912 
+0x0F124718, //70003914 
+0x0F12B5F8, //70003916 
+0x0F124C56, //70003918 
+0x0F1289E0, //7000391A 
+0x0F12F000, //7000391C 
+0x0F12FA40, //7000391E 
+0x0F120006, //70003920 
+0x0F128A20, //70003922 
+0x0F12F000, //70003924 
+0x0F12FA44, //70003926 
+0x0F120007, //70003928 
+0x0F12484F, //7000392A 
+0x0F124D4A, //7000392C 
+0x0F123020, //7000392E 
+0x0F126CA9, //70003930 
+0x0F126940, //70003932 
+0x0F121809, //70003934 
+0x0F120200, //70003936 
+0x0F12F000, //70003938 
+0x0F12FA42, //7000393A 
+0x0F120400, //7000393C 
+0x0F120C00, //7000393E 
+0x0F12002A, //70003940 
+0x0F12326E, //70003942 
+0x0F120011, //70003944 
+0x0F12390A, //70003946 
+0x0F122305, //70003948 
+0x0F12F000, //7000394A 
+0x0F12FA3F, //7000394C 
+0x0F124C43, //7000394E 
+0x0F1261A0, //70003950 
+0x0F128FEB, //70003952 
+0x0F120002, //70003954 
+0x0F120031, //70003956 
+0x0F120018, //70003958 
+0x0F12F000, //7000395A 
+0x0F12FA3F, //7000395C 
+0x0F12466B, //7000395E 
+0x0F120005, //70003960 
+0x0F128018, //70003962 
+0x0F12483C, //70003964 
+0x0F1269A2, //70003966 
+0x0F123040, //70003968 
+0x0F128800, //7000396A 
+0x0F120039, //7000396C 
+0x0F12F000, //7000396E 
+0x0F12FA35, //70003970 
+0x0F12466B, //70003972 
+0x0F120006, //70003974 
+0x0F128058, //70003976 
+0x0F120021, //70003978 
+0x0F129800, //7000397A 
+0x0F12311C, //7000397C 
+0x0F12F000, //7000397E 
+0x0F12FA35, //70003980 
+0x0F124935, //70003982 
+0x0F123180, //70003984 
+0x0F12808D, //70003986 
+0x0F1280CE, //70003988 
+0x0F128BA1, //7000398A 
+0x0F124836, //7000398C 
+0x0F123820, //7000398E 
+0x0F128001, //70003990 
+0x0F128BE1, //70003992 
+0x0F128041, //70003994 
+0x0F128C21, //70003996 
+0x0F128081, //70003998 
+0x0F12E701, //7000399A 
+0x0F12B5F8, //7000399C 
+0x0F124E2E, //7000399E 
+0x0F126C70, //700039A0 
+0x0F126CB1, //700039A2 
+0x0F120200, //700039A4 
+0x0F12F000, //700039A6 
+0x0F12FA0B, //700039A8 
+0x0F120400, //700039AA 
+0x0F120C00, //700039AC 
+0x0F122401, //700039AE 
+0x0F120364, //700039B0 
+0x0F1242A0, //700039B2 
+0x0F12D200, //700039B4 
+0x0F120004, //700039B6 
+0x0F124A27, //700039B8 
+0x0F120020, //700039BA 
+0x0F12327E, //700039BC 
+0x0F121F91, //700039BE 
+0x0F122303, //700039C0 
+0x0F12F000, //700039C2 
+0x0F12FA03, //700039C4 
+0x0F120405, //700039C6 
+0x0F120C2D, //700039C8 
+0x0F124A23, //700039CA 
+0x0F120020, //700039CC 
+0x0F12325A, //700039CE 
+0x0F120011, //700039D0 
+0x0F12390A, //700039D2 
+0x0F122305, //700039D4 
+0x0F12F000, //700039D6 
+0x0F12F9F9, //700039D8 
+0x0F12491F, //700039DA 
+0x0F1264C8, //700039DC 
+0x0F12491F, //700039DE 
+0x0F124E21, //700039E0 
+0x0F1288C8, //700039E2 
+0x0F122701, //700039E4 
+0x0F122800, //700039E6 
+0x0F12D009, //700039E8 
+0x0F124C23, //700039EA 
+0x0F1238FF, //700039EC 
+0x0F121E40, //700039EE 
+0x0F12D00A, //700039F0 
+0x0F122804, //700039F2 
+0x0F12D042, //700039F4 
+0x0F122806, //700039F6 
+0x0F12D101, //700039F8 
+0x0F122000, //700039FA 
+0x0F1280C8, //700039FC 
+0x0F1282B7, //700039FE 
+0x0F122001, //70003A00 
+0x0F12F000, //70003A02 
+0x0F12F9FB, //70003A04 
+0x0F12E6CB, //70003A06 
+0x0F12000D, //70003A08 
+0x0F12724F, //70003A0A 
+0x0F122001, //70003A0C 
+0x0F12F000, //70003A0E 
+0x0F12F9FD, //70003A10 
+0x0F12F000, //70003A12 
+0x0F12FA03, //70003A14 
+0x0F124910, //70003A16 
+0x0F123148, //70003A18 
+0x0F12C903, //70003A1A 
+0x0F124348, //70003A1C 
+0x0F120A00, //70003A1E 
+0x0F126160, //70003A20 
+0x0F1220FF, //70003A22 
+0x0F121D40, //70003A24 
+0x0F1280E8, //70003A26 
+0x0F12480C, //70003A28 
+0x0F123040, //70003A2A 
+0x0F127707, //70003A2C 
+0x0F12E7E6, //70003A2E 
+0x0F123290, //70003A30 
+0x0F127000, //70003A32 
+0x0F123294, //70003A34 
+0x0F127000, //70003A36 
+0x0F1204A8, //70003A38 
+0x0F127000, //70003A3A 
+0x0F1215DC, //70003A3C 
+0x0F127000, //70003A3E 
+0x0F125000, //70003A40 
+0x0F12D000, //70003A42 
+0x0F121E84, //70003A44 
+0x0F127000, //70003A46 
+0x0F121BE4, //70003A48 
+0x0F127000, //70003A4A 
+0x0F122EA8, //70003A4C 
+0x0F127000, //70003A4E 
+0x0F1221A4, //70003A50 
+0x0F127000, //70003A52 
+0x0F120100, //70003A54 
+0x0F127000, //70003A56 
+0x0F123F48, //70003A58 
+0x0F127000, //70003A5A 
+0x0F1231A0, //70003A5C 
+0x0F127000, //70003A5E 
+0x0F1201E8, //70003A60 
+0x0F127000, //70003A62 
+0x0F12F2A0, //70003A64 
+0x0F12D000, //70003A66 
+0x0F122A44, //70003A68 
+0x0F127000, //70003A6A 
+0x0F12F400, //70003A6C 
+0x0F12D000, //70003A6E 
+0x0F122024, //70003A70 
+0x0F127000, //70003A72 
+0x0F121650, //70003A74 
+0x0F127000, //70003A76 
+0x0F122A64, //70003A78 
+0x0F127000, //70003A7A 
+0x0F124982, //70003A7C 
+0x0F12724F, //70003A7E 
+0x0F1220FF, //70003A80 
+0x0F121DC0, //70003A82 
+0x0F1280C8, //70003A84 
+0x0F12F000, //70003A86 
+0x0F12F9D1, //70003A88 
+0x0F124980, //70003A8A 
+0x0F126ACA, //70003A8C 
+0x0F12604A, //70003A8E 
+0x0F122800, //70003A90 
+0x0F12D006, //70003A92 
+0x0F12436A, //70003A94 
+0x0F120001, //70003A96 
+0x0F120010, //70003A98 
+0x0F12F000, //70003A9A 
+0x0F12F991, //70003A9C 
+0x0F126160, //70003A9E 
+0x0F12E001, //70003AA0 
+0x0F12436A, //70003AA2 
+0x0F126162, //70003AA4 
+0x0F128BF0, //70003AA6 
+0x0F122800, //70003AA8 
+0x0F12D001, //70003AAA 
+0x0F12F7FF, //70003AAC 
+0x0F12FF33, //70003AAE 
+0x0F122000, //70003AB0 
+0x0F12F000, //70003AB2 
+0x0F12F9AB, //70003AB4 
+0x0F124974, //70003AB6 
+0x0F1220FF, //70003AB8 
+0x0F121DC0, //70003ABA 
+0x0F1280C8, //70003ABC 
+0x0F12E79E, //70003ABE 
+0x0F12B510, //70003AC0 
+0x0F12F000, //70003AC2 
+0x0F12F9BB, //70003AC4 
+0x0F124870, //70003AC6 
+0x0F1288C0, //70003AC8 
+0x0F121FC1, //70003ACA 
+0x0F1239FD, //70003ACC 
+0x0F12D103, //70003ACE 
+0x0F12496F, //70003AD0 
+0x0F1220FF, //70003AD2 
+0x0F121C40, //70003AD4 
+0x0F128048, //70003AD6 
+0x0F12E605, //70003AD8 
+0x0F12B5F8, //70003ADA 
+0x0F122400, //70003ADC 
+0x0F124D6D, //70003ADE 
+0x0F12486D, //70003AE0 
+0x0F12210E, //70003AE2 
+0x0F128041, //70003AE4 
+0x0F122101, //70003AE6 
+0x0F128001, //70003AE8 
+0x0F12F000, //70003AEA 
+0x0F12F9AF, //70003AEC 
+0x0F12486B, //70003AEE 
+0x0F128840, //70003AF0 
+0x0F12F000, //70003AF2 
+0x0F12F9B3, //70003AF4 
+0x0F124E6A, //70003AF6 
+0x0F12270D, //70003AF8 
+0x0F12073F, //70003AFA 
+0x0F1219E8, //70003AFC 
+0x0F128803, //70003AFE 
+0x0F1200E2, //70003B00 
+0x0F121991, //70003B02 
+0x0F12804B, //70003B04 
+0x0F128843, //70003B06 
+0x0F1252B3, //70003B08 
+0x0F128882, //70003B0A 
+0x0F1280CA, //70003B0C 
+0x0F1288C0, //70003B0E 
+0x0F128088, //70003B10 
+0x0F123508, //70003B12 
+0x0F12042D, //70003B14 
+0x0F120C2D, //70003B16 
+0x0F121C64, //70003B18 
+0x0F120424, //70003B1A 
+0x0F120C24, //70003B1C 
+0x0F122C07, //70003B1E 
+0x0F12D3EC, //70003B20 
+0x0F12E63D, //70003B22 
+0x0F12B5F0, //70003B24 
+0x0F12B085, //70003B26 
+0x0F126801, //70003B28 
+0x0F129103, //70003B2A 
+0x0F126881, //70003B2C 
+0x0F12040A, //70003B2E 
+0x0F120C12, //70003B30 
+0x0F12495C, //70003B32 
+0x0F128B89, //70003B34 
+0x0F122900, //70003B36 
+0x0F12D001, //70003B38 
+0x0F120011, //70003B3A 
+0x0F12E000, //70003B3C 
+0x0F122100, //70003B3E 
+0x0F129102, //70003B40 
+0x0F126840, //70003B42 
+0x0F120401, //70003B44 
+0x0F129803, //70003B46 
+0x0F120C09, //70003B48 
+0x0F12F000, //70003B4A 
+0x0F12F98F, //70003B4C 
+0x0F124854, //70003B4E 
+0x0F123080, //70003B50 
+0x0F128900, //70003B52 
+0x0F122800, //70003B54 
+0x0F12D039, //70003B56 
+0x0F122100, //70003B58 
+0x0F124854, //70003B5A 
+0x0F124D52, //70003B5C 
+0x0F124684, //70003B5E 
+0x0F124B53, //70003B60 
+0x0F124C4F, //70003B62 
+0x0F1288DA, //70003B64 
+0x0F120048, //70003B66 
+0x0F1200D7, //70003B68 
+0x0F12193E, //70003B6A 
+0x0F12197F, //70003B6C 
+0x0F12183F, //70003B6E 
+0x0F125A36, //70003B70 
+0x0F128AFF, //70003B72 
+0x0F12437E, //70003B74 
+0x0F1200B6, //70003B76 
+0x0F120C37, //70003B78 
+0x0F121906, //70003B7A 
+0x0F123680, //70003B7C 
+0x0F128177, //70003B7E 
+0x0F121C52, //70003B80 
+0x0F1200D2, //70003B82 
+0x0F121914, //70003B84 
+0x0F121952, //70003B86 
+0x0F121812, //70003B88 
+0x0F125A24, //70003B8A 
+0x0F128AD2, //70003B8C 
+0x0F124354, //70003B8E 
+0x0F1200A2, //70003B90 
+0x0F120C12, //70003B92 
+0x0F128272, //70003B94 
+0x0F12891C, //70003B96 
+0x0F12895B, //70003B98 
+0x0F124367, //70003B9A 
+0x0F12435A, //70003B9C 
+0x0F121943, //70003B9E 
+0x0F123340, //70003BA0 
+0x0F1289DB, //70003BA2 
+0x0F129C02, //70003BA4 
+0x0F1218BA, //70003BA6 
+0x0F124363, //70003BA8 
+0x0F1218D2, //70003BAA 
+0x0F120212, //70003BAC 
+0x0F120C12, //70003BAE 
+0x0F12466B, //70003BB0 
+0x0F12521A, //70003BB2 
+0x0F124663, //70003BB4 
+0x0F127DDB, //70003BB6 
+0x0F12435A, //70003BB8 
+0x0F129B03, //70003BBA 
+0x0F120252, //70003BBC 
+0x0F120C12, //70003BBE 
+0x0F12521A, //70003BC0 
+0x0F121C49, //70003BC2 
+0x0F120409, //70003BC4 
+0x0F120C09, //70003BC6 
+0x0F122904, //70003BC8 
+0x0F12D3C9, //70003BCA 
+0x0F12B005, //70003BCC 
+0x0F12BCF0, //70003BCE 
+0x0F12BC08, //70003BD0 
+0x0F124718, //70003BD2 
+0x0F12B510, //70003BD4 
+0x0F12F7FF, //70003BD6 
+0x0F12FF80, //70003BD8 
+0x0F12F000, //70003BDA 
+0x0F12F94F, //70003BDC 
+0x0F12E582, //70003BDE 
+0x0F12B570, //70003BE0 
+0x0F126804, //70003BE2 
+0x0F12F000, //70003BE4 
+0x0F12F952, //70003BE6 
+0x0F124D32, //70003BE8 
+0x0F128C29, //70003BEA 
+0x0F121A40, //70003BEC 
+0x0F1242A0, //70003BEE 
+0x0F12D901, //70003BF0 
+0x0F120020, //70003BF2 
+0x0F12E003, //70003BF4 
+0x0F12F000, //70003BF6 
+0x0F12F949, //70003BF8 
+0x0F128C29, //70003BFA 
+0x0F121A40, //70003BFC 
+0x0F126268, //70003BFE 
+0x0F12F000, //70003C00 
+0x0F12F94C, //70003C02 
+0x0F1262A8, //70003C04 
+0x0F12F000, //70003C06 
+0x0F12F951, //70003C08 
+0x0F126328, //70003C0A 
+0x0F128869, //70003C0C 
+0x0F122900, //70003C0E 
+0x0F12D000, //70003C10 
+0x0F1262A8, //70003C12 
+0x0F124828, //70003C14 
+0x0F126B00, //70003C16 
+0x0F128C00, //70003C18 
+0x0F122800, //70003C1A 
+0x0F12D11B, //70003C1C 
+0x0F126AA8, //70003C1E 
+0x0F12F000, //70003C20 
+0x0F12F94C, //70003C22 
+0x0F1261E8, //70003C24 
+0x0F124A1E, //70003C26 
+0x0F123280, //70003C28 
+0x0F128B91, //70003C2A 
+0x0F122900, //70003C2C 
+0x0F12D00B, //70003C2E 
+0x0F120011, //70003C30 
+0x0F123120, //70003C32 
+0x0F128809, //70003C34 
+0x0F124288, //70003C36 
+0x0F12D907, //70003C38 
+0x0F1261E9, //70003C3A 
+0x0F128C28, //70003C3C 
+0x0F121A08, //70003C3E 
+0x0F1262A8, //70003C40 
+0x0F12F000, //70003C42 
+0x0F12F92B, //70003C44 
+0x0F1262A8, //70003C46 
+0x0F12E502, //70003C48 
+0x0F128BD1, //70003C4A 
+0x0F124288, //70003C4C 
+0x0F12D800, //70003C4E 
+0x0F120008, //70003C50 
+0x0F1261E8, //70003C52 
+0x0F12E4FC, //70003C54 
+0x0F12F000, //70003C56 
+0x0F12F919, //70003C58 
+0x0F1261E8, //70003C5A 
+0x0F12E4F8, //70003C5C 
+0x0F12B510, //70003C5E 
+0x0F12F000, //70003C60 
+0x0F12F934, //70003C62 
+0x0F12480E, //70003C64 
+0x0F1230A0, //70003C66 
+0x0F128841, //70003C68 
+0x0F122900, //70003C6A 
+0x0F12D007, //70003C6C 
+0x0F124A07, //70003C6E 
+0x0F123280, //70003C70 
+0x0F126953, //70003C72 
+0x0F124A11, //70003C74 
+0x0F12428B, //70003C76 
+0x0F12D202, //70003C78 
+0x0F128880, //70003C7A 
+0x0F1281D0, //70003C7C 
+0x0F12E532, //70003C7E 
+0x0F1288C0, //70003C80 
+0x0F1281D0, //70003C82 
+0x0F12E52F, //70003C84 
+0x0F120000, //70003C86 
+0x0F1231A0, //70003C88 
+0x0F127000, //70003C8A 
+0x0F1229E4, //70003C8C 
+0x0F127000, //70003C8E 
+0x0F12C100, //70003C90 
+0x0F12D000, //70003C92 
+0x0F12A006, //70003C94 
+0x0F120000, //70003C96 
+0x0F12A000, //70003C98 
+0x0F12D000, //70003C9A 
+0x0F12064C, //70003C9C 
+0x0F127000, //70003C9E 
+0x0F123F48, //70003CA0 
+0x0F127000, //70003CA2 
+0x0F1207C4, //70003CA4 
+0x0F127000, //70003CA6 
+0x0F1207E8, //70003CA8 
+0x0F127000, //70003CAA 
+0x0F122B24, //70003CAC 
+0x0F127000, //70003CAE 
+0x0F121FA0, //70003CB0 
+0x0F127000, //70003CB2 
+0x0F121E3C, //70003CB4 
+0x0F127000, //70003CB6 
+0x0F1221A4, //70003CB8 
+0x0F127000, //70003CBA 
+0x0F12E200, //70003CBC 
+0x0F12D000, //70003CBE 
+0x0F124778, //70003CC0 
+0x0F1246C0, //70003CC2 
+0x0F12C000, //70003CC4 
+0x0F12E59F, //70003CC6 
+0x0F12FF1C, //70003CC8 
+0x0F12E12F, //70003CCA 
+0x0F121F63, //70003CCC 
+0x0F120001, //70003CCE 
+0x0F124778, //70003CD0 
+0x0F1246C0, //70003CD2 
+0x0F12C000, //70003CD4 
+0x0F12E59F, //70003CD6 
+0x0F12FF1C, //70003CD8 
+0x0F12E12F, //70003CDA 
+0x0F121EDF, //70003CDC 
+0x0F120001, //70003CDE 
+0x0F124778, //70003CE0 
+0x0F1246C0, //70003CE2 
+0x0F12C000, //70003CE4 
+0x0F12E59F, //70003CE6 
+0x0F12FF1C, //70003CE8 
+0x0F12E12F, //70003CEA 
+0x0F12495F, //70003CEC 
+0x0F120000, //70003CEE 
+0x0F124778, //70003CF0 
+0x0F1246C0, //70003CF2 
+0x0F12C000, //70003CF4 
+0x0F12E59F, //70003CF6 
+0x0F12FF1C, //70003CF8 
+0x0F12E12F, //70003CFA 
+0x0F12E403, //70003CFC 
+0x0F120000, //70003CFE 
+0x0F124778, //70003D00 
+0x0F1246C0, //70003D02 
+0x0F12C000, //70003D04 
+0x0F12E59F, //70003D06 
+0x0F12FF1C, //70003D08 
+0x0F12E12F, //70003D0A 
+0x0F1224B3, //70003D0C 
+0x0F120001, //70003D0E 
+0x0F124778, //70003D10 
+0x0F1246C0, //70003D12 
+0x0F12C000, //70003D14 
+0x0F12E59F, //70003D16 
+0x0F12FF1C, //70003D18 
+0x0F12E12F, //70003D1A 
+0x0F12EECD, //70003D1C 
+0x0F120000, //70003D1E 
+0x0F124778, //70003D20 
+0x0F1246C0, //70003D22 
+0x0F12C000, //70003D24 
+0x0F12E59F, //70003D26 
+0x0F12FF1C, //70003D28 
+0x0F12E12F, //70003D2A 
+0x0F12F049, //70003D2C 
+0x0F120000, //70003D2E 
+0x0F124778, //70003D30 
+0x0F1246C0, //70003D32 
+0x0F12C000, //70003D34 
+0x0F12E59F, //70003D36 
+0x0F12FF1C, //70003D38 
+0x0F12E12F, //70003D3A 
+0x0F1212DF, //70003D3C 
+0x0F120000, //70003D3E 
+0x0F124778, //70003D40 
+0x0F1246C0, //70003D42 
+0x0F12C000, //70003D44 
+0x0F12E59F, //70003D46 
+0x0F12FF1C, //70003D48 
+0x0F12E12F, //70003D4A 
+0x0F12F05B, //70003D4C 
+0x0F120000, //70003D4E 
+0x0F124778, //70003D50 
+0x0F1246C0, //70003D52 
+0x0F12C000, //70003D54 
+0x0F12E59F, //70003D56 
+0x0F12FF1C, //70003D58 
+0x0F12E12F, //70003D5A 
+0x0F12F07B, //70003D5C 
+0x0F120000, //70003D5E 
+0x0F124778, //70003D60 
+0x0F1246C0, //70003D62 
+0x0F12C000, //70003D64 
+0x0F12E59F, //70003D66 
+0x0F12FF1C, //70003D68 
+0x0F12E12F, //70003D6A 
+0x0F12FE6D, //70003D6C 
+0x0F120000, //70003D6E 
+0x0F124778, //70003D70 
+0x0F1246C0, //70003D72 
+0x0F12C000, //70003D74 
+0x0F12E59F, //70003D76 
+0x0F12FF1C, //70003D78 
+0x0F12E12F, //70003D7A 
+0x0F123295, //70003D7C 
+0x0F120000, //70003D7E 
+0x0F124778, //70003D80 
+0x0F1246C0, //70003D82 
+0x0F12C000, //70003D84 
+0x0F12E59F, //70003D86 
+0x0F12FF1C, //70003D88 
+0x0F12E12F, //70003D8A 
+0x0F12234F, //70003D8C 
+0x0F120000, //70003D8E 
+0x0F124778, //70003D90 
+0x0F1246C0, //70003D92 
+0x0F12C000, //70003D94 
+0x0F12E59F, //70003D96 
+0x0F12FF1C, //70003D98 
+0x0F12E12F, //70003D9A 
+0x0F124521, //70003D9C 
+0x0F120000, //70003D9E 
+0x0F124778, //70003DA0 
+0x0F1246C0, //70003DA2 
+0x0F12C000, //70003DA4 
+0x0F12E59F, //70003DA6 
+0x0F12FF1C, //70003DA8 
+0x0F12E12F, //70003DAA 
+0x0F127C0D, //70003DAC 
+0x0F120000, //70003DAE 
+0x0F124778, //70003DB0 
+0x0F1246C0, //70003DB2 
+0x0F12C000, //70003DB4 
+0x0F12E59F, //70003DB6 
+0x0F12FF1C, //70003DB8 
+0x0F12E12F, //70003DBA 
+0x0F127C2B, //70003DBC 
+0x0F120000, //70003DBE 
+0x0F124778, //70003DC0 
+0x0F1246C0, //70003DC2 
+0x0F12F004, //70003DC4 
+0x0F12E51F, //70003DC6 
+0x0F1224C4, //70003DC8 
+0x0F120001, //70003DCA 
+0x0F124778, //70003DCC 
+0x0F1246C0, //70003DCE 
+0x0F12C000, //70003DD0 
+0x0F12E59F, //70003DD2 
+0x0F12FF1C, //70003DD4 
+0x0F12E12F, //70003DD6 
+0x0F123183, //70003DD8 
+0x0F120000, //70003DDA 
+0x0F124778, //70003DDC 
+0x0F1246C0, //70003DDE 
+0x0F12C000, //70003DE0 
+0x0F12E59F, //70003DE2 
+0x0F12FF1C, //70003DE4 
+0x0F12E12F, //70003DE6 
+0x0F12302F, //70003DE8 
+0x0F120000, //70003DEA 
+0x0F124778, //70003DEC 
+0x0F1246C0, //70003DEE 
+0x0F12C000, //70003DF0 
+0x0F12E59F, //70003DF2 
+0x0F12FF1C, //70003DF4 
+0x0F12E12F, //70003DF6 
+0x0F12EF07, //70003DF8 
+0x0F120000, //70003DFA 
+0x0F124778, //70003DFC 
+0x0F1246C0, //70003DFE 
+0x0F12C000, //70003E00 
+0x0F12E59F, //70003E02 
+0x0F12FF1C, //70003E04 
+0x0F12E12F, //70003E06 
+0x0F1248FB, //70003E08 
+0x0F120000, //70003E0A 
+0x0F124778, //70003E0C 
+0x0F1246C0, //70003E0E 
+0x0F12C000, //70003E10 
+0x0F12E59F, //70003E12 
+0x0F12FF1C, //70003E14 
+0x0F12E12F, //70003E16 
+0x0F12F0B1, //70003E18 
+0x0F120000, //70003E1A 
+0x0F124778, //70003E1C 
+0x0F1246C0, //70003E1E 
+0x0F12C000, //70003E20 
+0x0F12E59F, //70003E22 
+0x0F12FF1C, //70003E24 
+0x0F12E12F, //70003E26 
+0x0F12EEDF, //70003E28 
+0x0F120000, //70003E2A 
+0x0F124778, //70003E2C 
+0x0F1246C0, //70003E2E 
+0x0F12C000, //70003E30 
+0x0F12E59F, //70003E32 
+0x0F12FF1C, //70003E34 
+0x0F12E12F, //70003E36 
+0x0F12AEF1, //70003E38 
+0x0F120000, //70003E3A 
+0x0F124778, //70003E3C 
+0x0F1246C0, //70003E3E 
+0x0F12C000, //70003E40 
+0x0F12E59F, //70003E42 
+0x0F12FF1C, //70003E44 
+0x0F12E12F, //70003E46 
+0x0F1202EB, //70003E48 
+0x0F120001, //70003E4A 
+0x0F124778, //70003E4C 
+0x0F1246C0, //70003E4E 
+0x0F12C000, //70003E50 
+0x0F12E59F, //70003E52 
+0x0F12FF1C, //70003E54 
+0x0F12E12F, //70003E56 
+0x0F12FD21, //70003E58 
+0x0F120000, //70003E5A 
+0x0F124778, //70003E5C 
+0x0F1246C0, //70003E5E 
+0x0F12C000, //70003E60 
+0x0F12E59F, //70003E62 
+0x0F12FF1C, //70003E64 
+0x0F12E12F, //70003E66 
+0x0F12FDAF, //70003E68 
+0x0F120000, //70003E6A 
+0x0F124778, //70003E6C 
+0x0F1246C0, //70003E6E 
+0x0F12C000, //70003E70 
+0x0F12E59F, //70003E72 
+0x0F12FF1C, //70003E74 
+0x0F12E12F, //70003E76 
+0x0F125027, //70003E78 
+0x0F120000, //70003E7A 
+0x0F124778, //70003E7C 
+0x0F1246C0, //70003E7E 
+0x0F12C000, //70003E80 
+0x0F12E59F, //70003E82 
+0x0F12FF1C, //70003E84 
+0x0F12E12F, //70003E86 
+0x0F1204C9, //70003E88 
+0x0F120000, //70003E8A 
+0x0F124778, //70003E8C 
+0x0F1246C0, //70003E8E 
+0x0F12C000, //70003E90 
+0x0F12E59F, //70003E92 
+0x0F12FF1C, //70003E94 
+0x0F12E12F, //70003E96 
+0x0F1239DF, //70003E98 
+0x0F120000, //70003E9A 
+0x0F124778, //70003E9C 
+0x0F1246C0, //70003E9E 
+0x0F12C000, //70003EA0 
+0x0F12E59F, //70003EA2 
+0x0F12FF1C, //70003EA4 
+0x0F12E12F, //70003EA6 
+0x0F126177, //70003EA8 
+0x0F120000, //70003EAA 
+0x0F124778, //70003EAC 
+0x0F1246C0, //70003EAE 
+0x0F12C000, //70003EB0 
+0x0F12E59F, //70003EB2 
+0x0F12FF1C, //70003EB4 
+0x0F12E12F, //70003EB6 
+0x0F12424F, //70003EB8 
+0x0F120000, //70003EBA 
+0x0F124778, //70003EBC 
+0x0F1246C0, //70003EBE 
+0x0F12C000, //70003EC0 
+0x0F12E59F, //70003EC2 
+0x0F12FF1C, //70003EC4 
+0x0F12E12F, //70003EC6 
+0x0F123F0D, //70003EC8 
+0x0F120000, //70003ECA 
+0x0F124778, //70003ECC 
+0x0F1246C0, //70003ECE 
+0x0F12C000, //70003ED0 
+0x0F12E59F, //70003ED2 
+0x0F12FF1C, //70003ED4 
+0x0F12E12F, //70003ED6 
+0x0F1202B9, //70003ED8 
+0x0F120001, //70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007, // clks_src_gf_force_enable
+
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120001, // on/off AFIT by NB option
+
+0x0F120005, //0005// NormBR[0]
+0x0F120066, //00C8// NormBR[1]
+0x0F1200C8, //00F4// NormBR[2]
+0x0F120320, //0320// NormBR[3]
+0x0F120375, //0375// NormBR[4]
+
+
+
+// Flash
+0x002A3F82,
+0x0F120000,// TNP_Regs_PreflashStart
+0x0F120000,// TNP_Regs_PreflashEnd
+0x0F120260,// TNP_Regs_PreWP_r
+0x0F120240, // TNP_Regs_PreWP_b
+
+0x002A3F98,	// BR Tuning
+0x0F120100,	// TNP_Regs_BrRatioIn_0_
+0x0F120150,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120100,	// TNP_Regs_BrRatioOut_0_
+0x0F1200A0,
+0x0F120080,
+0x0F120040,
+0x0F120020,
+
+0x0F120030,	// WP Tuning
+0x0F120040,	// TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	// T_BR tune	
+0x0F120150,	// TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B,
+0x0F12002C,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,	
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120240, //0244 0258 AWB R point //0258 0245 0258
+0x0F120244, //024D 0220 AWB B point //0220 0245 0245
+
+
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// Analog & APS settings                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// This register is for FACTORY ONLY. If you change it without prior notification                           //
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future                           //                           //                           //                           //                           //                           //                           //
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, // adc_sat[7:0]=84d (500mV)
+0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, // rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, // pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, // clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001,// ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+0x002AF42E,
+0x0F120406,// fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+0x002AF434,
+0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, // reg_tune_pix[7:0]
+0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, // reg_tune_rg[7:0] (2.83V)
+0x0F120004, // reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, // blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, // srx_en[0]
+
+0x002A0054,
+0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, // div_dbr[7:4]
+0x002AF132,
+0x0F124006,	//ki 0413// tgr_frame_decription 4
+0x002AF142,
+0x0F120000,	//ki 0413// tgr_frame_decription 4
+
+0x002AF152,
+0x0F120206, // tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, // tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, // tgr_frame_params_descriptor_6
+//==========================================================================================
+
+//============================= Line-ADLC Tuning ===========================================
+0x002AE412,
+0x0F120008, // adlc_tune_offset_gr[7:0]
+0x0F120008, // adlc_tune_offset_r[7:0]
+0x0F120010, // adlc_tune_offset_b[7:0]
+0x0F120010, // adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, // adlc_qec[2:0]
+//==========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F12012C,	//0132 //0138 //awbb_IntcR
+0x0F12010B,	//010A //011C //awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1// No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041,                            //REG_TC_IPRM_CM_Init_GpioConfig1 // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C,                            //REG_TC_IPRM_CM_Init_Mi2cBits // Use GPIO_5 for SCL GPIO_6 for SDA
+0x0F120190,                            //REG_TC_IPRM_CM_Init_Mi2cRateKhz // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000 //#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121000, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120002, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120601, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120001, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200F0, //#af_search_usPeakThr  for
+0x0F120090, //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F124040, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+0x002A0648,  
+0x0F120000, //skl_af_bPregmOff gamma
+
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120011, //#af_pos_usTableLastInd 10h_ 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120034, //#af_pos_usTable_1_  51   
+0x0F120038, //#af_pos_usTable_2_  54	
+0x0F12003C, //#af_pos_usTable_3_  57	
+0x0F120030, //#af_pos_usTable_4_  61   
+0x0F120044, //#af_pos_usTable_5_  65	
+0x0F120048, //#af_pos_usTable_6_  69	
+0x0F12004C, //#af_pos_usTable_7_  73	
+0x0F120050, //#af_pos_usTable_8_  78	
+0x0F120054, //#af_pos_usTable_9_  83	
+0x0F120058, //#af_pos_usTable_10_ 89	
+0x0F12005C, //#af_pos_usTable_11_ 89	
+0x0F120060, //#af_pos_usTable_12_ 89	
+0x0F120064, //#af_pos_usTable_13_ 89	
+0x0F120068, //#af_pos_usTable_14_ 89	
+0x0F12006C, //#af_pos_usTable_15_ 89	
+0x0F120070, //#af_pos_usTable_16_ 89	
+0x0F120074, //#af_pos_usTable_17_ 89		
+
+
+//8. Continuous AF setting
+//8-1 Continuous AF timing
+0x002A152A,
+0x0F120040, //40//30//af_refocus_usFlFrames_ lens movement each 64frame 
+0x002A154A,
+0x0F120010, //18//0C//af_scene_usResetNWaitFr (4 frame) lens movement each 64frame 
+
+//8-2 Continuous AF sensitivity
+0x002A154C, //      
+0x0F120000, //0010   
+0x0F120000, //03FF  
+0x0F120000, //0000  
+           
+
+0x002A1526, //Continuous AF sensitivity tuning
+0x0F128080, //
+0x0F12A0A0, //
+
+
+//8-3 Continuos AF, lens movement
+0x002A1424,  
+0x0F126060,  // af_pos_usMiddlePos  MSB_macro LSB_ normal lens moving direction lens À̵¿¹æÇâ °áÁ¤ AF position table ÀÇ Á߽ɰªÀ» ÀÔ·Â
+0x002A148E, // usPeakFrontThr
+0x0F120002, 
+
+
+//9. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120200, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120004, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120100, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001,//REG_TC_IPRM_AuxConfig // bit[0] : Flash is in use bit[1] : Mechanical shutter is in use                            // 0 : do not use 1 : use
+0x0F120003,//REG_TC_IPRM_AuxPolarity // bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+0x0F120003,//REG_TC_IPRM_AuxGpios  //1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12085C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000, //senHal_bSRX //SRX off
+
+0x002A1680,
+0x0F120002, //senHal_NExpLinesCheckFine //0004 //extend Forbidden area line
+
+0x002A0ED2,
+0x0F120FA0,	//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType // 0:Full 1:digital 2:PLA 3:CA
+0x0F120000, //senHal_SamplingMode // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK
+0x002A0188,
+0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+0x0F120000, //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001, //REG_TC_IPRM_UseNPviClocks
+0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+//SCLK & PCLK // clock set 0
+0x0F1238A4,//38A4	//36B0//34BC //32C8//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+0x0F1254F0,//4E20	//3A98//7148 //4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0	//54Mhz
+0x0F1254F8,//57E4	//61A8//7148 //4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0	//54Mhz
+
+	//SCLK & PCLK     // clock set 1
+0x0F1238A4,//38A4//36B0//34BC	//32C8//REG_TC_IPRM_OpClk4KHz_0	//52Mhz
+0x0F1254F0,//4E20//3A98//7148	//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0//54Mhz
+0x0F1254F8,//57E4//61A8//7148	//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0//54Mhz
+
+	//SCLK & PCLK     // clock set 2                                             
+0x0F1238A4,//38A4//36B0 //34BC//32C8//REG_TC_IPRM_OpClk4KHz_0//52Mhz          
+0x0F1254F0,//4E20//3A98 //7148//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz  
+0x0F1254F8,//57E4//61A8 //7148//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz  
+
+0x002A1B78,
+0x0F1238A4, //REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_0__usSysDiv
+0x0F120001, //REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4, //REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_1__usSysDiv
+0x0F120001, //REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4, //REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_2__usSysDiv
+0x0F120001, //REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A,
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6, 
+0x0F120500, //5C0, //0800 //REG_TC_GP_PrevReqInputWidth	  //Sensor Crop Width	2048
+0x0F1202d0, //33C, //0600 //REG_TC_GP_PrevReqInputHeight  //Sensor Crop Height 1536
+0x0F120198, //180, //120, //0000 //REG_TC_GP_PrevInputWidthOfs	  //Sensor HOffset 0
+0x0F120162, //0000 //REG_TC_GP_PrevInputHeightOfs  //Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A1676,
+0x0F120002,// 0:Full 1:digital 2:PLA 3:CA
+
+0x002A0216,
+0x0F120001,//for input size change
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 1024x768 system 52M PCLK 54M
+//===================================================================
+0x002A023E,
+0x0F120500, //REG_0TC_PCFG_usWidth
+0x0F1202D0, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMinOut4KHzRate
+
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+0x0F1201B8, //1A0 //REG_0TC_PCFG_usMaxFrTimeMsecMult10  //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS 01a0-24fr
+0x0F12014D, //REG_0TC_PCFG_usMinFrTimeMsecMult10 //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+0x0F120000, //3, //REG_0TC_PCFG_uPrevMirror
+0x0F120000, //3, //REG_0TC_PCFG_uCaptureMirror
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 54M
+//===================================================================
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format//PCAM 5:YUV   9:JPEG
+0x0F1254F6,	//REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_CCFG_usMinOut4KHzRate
+
+0x002A033E,
+0x0F120010, //REG_0TC_CCFG_PVIMask  => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+0x002A0346,
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+
+
+
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+
+0xFFFF0064, //Delay 100ms
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //1, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120000,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F00,
+0x0F120000,
+0x0F120F0F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+
+// TVAR_ash_pGAS_low
+0x0F126E49,
+0x0F12FB98,
+0x0F12F348,
+0x0F121BD6,
+0x0F12EBEF,
+0x0F1203D3,
+0x0F12EC8D,
+0x0F12F239,
+0x0F120E64,
+0x0F12F7EA,
+0x0F12FD3B,
+0x0F120A7C,
+0x0F12FC9C,
+0x0F120BD3,
+0x0F12F2E5,
+0x0F120619,
+0x0F120772,
+0x0F12F0B0,
+0x0F12184E,
+0x0F12F95F,
+0x0F120B1A,
+0x0F12FC45,
+0x0F12F716,
+0x0F120DCD,
+0x0F12EF24,
+0x0F120221,
+0x0F12F6BD,
+0x0F1204CB,
+0x0F1200B1,
+0x0F12FEB0,
+0x0F120268,
+0x0F1202C7,
+0x0F12010A,
+0x0F12FF93,
+0x0F12036D,
+0x0F12F859,
+0x0F1281D0,
+0x0F12FA32,
+0x0F12EFDB,
+0x0F12234D,
+0x0F12E799,
+0x0F120337,
+0x0F12EB05,
+0x0F12E8F9,
+0x0F12152E,
+0x0F12F0D5,
+0x0F120842,
+0x0F12043A,
+0x0F12F461,
+0x0F120E58,
+0x0F12F658,
+0x0F12075D,
+0x0F12F78D,
+0x0F12FDE9,
+0x0F12277A,
+0x0F12FFDE,
+0x0F12FD3B,
+0x0F12FE50,
+0x0F120AD1,
+0x0F12FE2C,
+0x0F12E90D,
+0x0F12F7B0,
+0x0F1205DB,
+0x0F1202CD,
+0x0F12F4F1,
+0x0F1202A8,
+0x0F12FDDC,
+0x0F120B59,
+0x0F12F74E,
+0x0F1203D5,
+0x0F12FF4F,
+0x0F1200F7,
+0x0F126A44,
+0x0F12FAD6,
+0x0F12F261,
+0x0F121F28,
+0x0F12E691,
+0x0F1207D2,
+0x0F12EE85,
+0x0F12F426,
+0x0F120F26,
+0x0F12F34B,
+0x0F120036,
+0x0F120C0F,
+0x0F12FDA9,
+0x0F1209EA,
+0x0F12F27A,
+0x0F120CD5,
+0x0F1201E1,
+0x0F12ED41,
+0x0F121DB5,
+0x0F12FD26,
+0x0F1203F7,
+0x0F12F7BB,
+0x0F12FE81,
+0x0F1212D3,
+0x0F12E061,
+0x0F12F81C,
+0x0F1207B1,
+0x0F120408,
+0x0F12F860,
+0x0F12FC9A,
+0x0F120DDE,
+0x0F120C9C,
+0x0F12F2A4,
+0x0F1202EB,
+0x0F12099B,
+0x0F12F5A6,
+0x0F127243,
+0x0F12F74D,
+0x0F12F74B,
+0x0F121800,
+0x0F12EF22,
+0x0F120263,
+0x0F12EBE7,
+0x0F12F5A4,
+0x0F1209D3,
+0x0F12FAB8,
+0x0F12FDFF,
+0x0F12086B,
+0x0F120338,
+0x0F120514,
+0x0F12F840,
+0x0F120768,
+0x0F12FE55,
+0x0F12F884,
+0x0F121488,
+0x0F12FFCD,
+0x0F12035B,
+0x0F12FA4E,
+0x0F1201DB,
+0x0F1206D6,
+0x0F12EE19,
+0x0F12FEA3,
+0x0F12FE8C,
+0x0F1203A3,
+0x0F12FDDB,
+0x0F12FD9B,
+0x0F12035E,
+0x0F1203F2,
+0x0F12FCBD,
+0x0F120300,
+0x0F12FF2E,
+0x0F12FE03,
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F124000, //TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F123C00, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+
+//s002A06D8
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+
+//add ki 11.02.18
+// SLOW AE
+// SLOW AE
+0x002A13F2,
+0x0F120014,// 0010 ae_GainIn_0_	//
+0x0F120032,// 0020	ae_GainIn_1_//					
+0x0F120078,// 0040	ae_GainIn_2_//					
+0x0F1200AA,// 0080	ae_GainIn_3_//					
+0x0F120100,// 0100	ae_GainIn_4_//					
+0x0F120140,// 0200	ae_GainIn_5_//					
+0x0F1201B8,// 0400	ae_GainIn_6_//					
+0x0F120400,// 0800	ae_GainIn_7_//					
+0x0F122000,// 2000	ae_GainIn_8_//	
+
+0x0F120046,//0050	// 0010	ae_GainOut_0_	p	 //						
+0x0F120078,//0070	// 0020	ae_GainOut_1_ p //						
+0x0F1200BE,//00A0	// 0040	ae_GainOut_2_	p	 //						
+0x0F1200DC,//00D0	// 0080	ae_GainOut_3_	p	 //						
+0x0F120100,// fix 0100	ae_GainOut_4_	//
+0x0F12010E,// 0200	ae_GainOut_5_	//
+0x0F120140,// 0400	ae_GainOut_6_	//
+0x0F1201F4,// 0800	ae_GainOut_7_	//
+0x0F120200,// 2000	ae_GainOut_8_	//
+
+
+0x002A13BC,
+0x0F120100,//0000ae_ContrastS_0_//
+0x0F120100,//000Cae_ContrastS_1_//
+0x0F120100,//001Cae_ContrastS_2_//
+0x0F120100,//0020ae_ContrastS_3_//
+0x0F120100,//0020ae_ContrastS_4_//
+0x0F120100,//0020ae_ContrastS_5_//
+0x0F120100,//0020ae_ContrastS_6_//
+0x0F120100,//0020ae_ContrastS_7_//
+
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+
+
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR  //MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+//AE_state
+0x002A04EE,
+0x0F120105, //010E //#lt_uLimitHigh
+0x0F1200FA, //00F5 //#lt_uLimitLow
+
+0x002A0500,                           
+0x0F120001,	 //lt_uInitPostToleranceCnt
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //3415//#lt_uMaxExp1
+0x002A0508,
+0x0F123415, //26e8//681F//#lt_uMaxExp2
+0x002A050C,
+0x0F123415, //26e8//8227//#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F123415, //681F //#lt_uCapMaxExp2
+0x002A051C,
+0x0F123415, //8227 //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F120200, //1E0 //#lt_uMaxAnGain1
+0x0F120240, //1E0 //#lt_uMaxAnGain2
+0x0F120340, //0300 //#lt_uMaxAnGain3
+0x0F120A00, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //#lt_uCapMaxAnGain1
+0x0F120240, //#lt_uCapMaxAnGain2
+0x0F120340, //300 //#lt_uCapMaxAnGain3
+0x0F120A00, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,                                                                        
+0x0F120101, //ae_WeightTbl_16[0]   0000
+0x0F120101, //ae_WeightTbl_16[1]   0000
+0x0F120101, //ae_WeightTbl_16[2]   0000
+0x0F120101, //ae_WeightTbl_16[3]   0000
+0x0F120101, //ae_WeightTbl_16[4]   0101
+0x0F120101, //ae_WeightTbl_16[5]   0101
+0x0F120101, //ae_WeightTbl_16[6]   0101
+0x0F120101, //ae_WeightTbl_16[7]   0101
+0x0F120101, //ae_WeightTbl_16[8]   0101
+0x0F120202, //ae_WeightTbl_16[9]   0201
+0x0F120202, //ae_WeightTbl_16[10]  0102
+0x0F120101, //ae_WeightTbl_16[11]  0101
+0x0F120101, //ae_WeightTbl_16[12]  0101
+0x0F120202, //ae_WeightTbl_16[13]  0202
+0x0F120202, //ae_WeightTbl_16[14]  0202
+0x0F120101, //ae_WeightTbl_16[15]  0101
+0x0F120101, //ae_WeightTbl_16[16]  0101
+0x0F120202, //ae_WeightTbl_16[17]  0202
+0x0F120202, //ae_WeightTbl_16[18]  0202
+0x0F120101, //ae_WeightTbl_16[19]  0101
+0x0F120101, //ae_WeightTbl_16[20]  0201
+0x0F120202, //ae_WeightTbl_16[21]  0202
+0x0F120202, //ae_WeightTbl_16[22]  0202
+0x0F120101, //ae_WeightTbl_16[23]  0102
+0x0F120101, //ae_WeightTbl_16[24]  0201
+0x0F120101, //ae_WeightTbl_16[25]  0202
+0x0F120101, //ae_WeightTbl_16[26]  0202
+0x0F120101, //ae_WeightTbl_16[27]  0102
+0x0F120101, //ae_WeightTbl_16[28]  0101
+0x0F120101, //ae_WeightTbl_16[29]  0101
+0x0F120101, //ae_WeightTbl_16[30]  0101
+0x0F120101, //ae_WeightTbl_16[31]  0101
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F12074D,//05F0 //awbb_GamutWidthThr1
+0x0F120433,//01F4 //awbb_GamutHeightThr1
+0x0F12002A,//006C //awbb_GamutWidthThr2
+0x0F12000C,//0038 //awbb_GamutHeightThr2
+0x002A1020,
+0x0F120020,	//000C //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A1028,
+0x0F120020,	//awbb_MinNumOfOutdoorPatches
+
+0x002A291A,
+0x0F120004, // #Mon_AWB_ByPassMode // [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A1048,
+0x0F1200C8,	//awbb_LowBr								
+0x0F12001E,	//awbb_LowBr_NBzone						
+
+0x002A1008,
+0x0F120020,	//awbb_NormalYThresh_y_low
+0x0F1200A0,	//awbb_NormalYThresh_y_high
+0x0F120002, //awbb_LowBrYThresh_y_low
+0x0F1200A0, //awbb_LowBrYThresh_y_high
+
+
+
+0x002A102E,
+0x0F12054D,	//awbb_MvEq_RBthresh
+
+0x002A1032,
+0x0F120000, //awbb_MovingScale10
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F120426,	//03C0//03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F12047E,	//03E2//03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F1203C6,	//0356//0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F120496,	//03FC//03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F120374,	//031E//031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1204A0,	//03FE//03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F12033A,	//02F0//02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F120498,	//03F0//03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F120312,	//02CA//02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F120478,	//03CC//03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202EA,	//02A8//02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F120440,	//037A//037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F1202C2,	//0280//0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F1203FA,	//033C//033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F12029A,	//0260//0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F1203BE,	//030A//030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120272,	//0242//0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F120398,	//02DC//02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F12024E,	//0228//0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F120372,	//02B2//02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F12022A,	//020E//020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120340,	//0290//02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F120206,	//01F8//01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120310,	//0276//0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201E2,	//01E8//01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F1202DE,	//0268//0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201C0,	//01DC//01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F1202AE,	//0256//0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201B4,	//01E0//01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F12027E,	//0238//0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201C0,	//01EC//01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F12024C,	//020E//020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F1201FA,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F12021C,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //awbb_IndoorGrZones_m_Grid
+0x002A0F80,
+0x0F1200A6, //awbb_IndoorGrZones_m_Boff
+0x002A0F7C,
+0x0F120011,
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12023E, //awbb_OutdoorGrZones_m_BGrid[0]
+0x0F120286, //awbb_OutdoorGrZones_m_BGrid[1]
+0x0F12022C, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202CC, //awbb_OutdoorGrZones_m_BGrid[3]
+0x0F12021A, //awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202F0, //awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120208, //awbb_OutdoorGrZones_m_BGrid[6]
+0x0F120316, //awbb_OutdoorGrZones_m_BGrid[7]
+0x0F1201F6, //awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202FE, //awbb_OutdoorGrZones_m_BGrid[9]
+0x0F1201E4, //awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202E8, //awbb_OutdoorGrZones_m_BGrid[11]
+0x0F1201D2, //awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202D2, //awbb_OutdoorGrZones_m_BGrid[13]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[14]
+0x0F1202BC, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[16]
+0x0F1202A6, //awbb_OutdoorGrZones_m_BGrid[17]
+0x0F1201D0, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F12028E, //awbb_OutdoorGrZones_m_BGrid[19]
+0x0F1201D6, //awbb_OutdoorGrZones_m_BGrid[20]
+0x0F120278, //awbb_OutdoorGrZones_m_BGrid[21]
+0x0F1201F8, //awbb_OutdoorGrZones_m_BGrid[22]
+0x0F120244, //awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C, //awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201D8, //awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F120400, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F120656, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F1205BE, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202E6, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120524, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F120290, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1204A0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120246, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F12041A, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201FE, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F1203AE, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201C0, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F120192, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F120306, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F120170, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F1202BA, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F12015C, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F12019C, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F12024E, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000B, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F120082, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+          
+0x002A11A8,
+0x0F12028E, //awbb_GridCon0xt_1[0]
+0x0F120306, //awbb_GridCon0xt_1[1]
+0x0F1203A6, //awbb_GridCon0xt_1[2]
+          
+0x0F120F86, //awbb_GridCon0xt_2[0]  0F86
+0x0F12105F, //awbb_GridCon0xt_2[1]  105F
+0x0F121160, //awbb_GridCon0xt_2[2]  11AA
+0x0F121161, //awbb_GridCon0xt_2[3]  1111
+0x0F1211F2, //awbb_GridCon0xt_2[4]  120C
+0x0F1212A1, //awbb_GridCon0xt_2[5]  126D
+          
+0x0F12008F, //awbb_GridCoeff_R_1
+0x0F1200D4, //awbb_GridCoeff_B_1
+0x0F1200C6, //awbb_GridCoeff_R_2
+0x0F1200A2, //awbb_GridCoeff_B_2
+          
+0x002A1118,
+0x0F120000, //0032//awbb_GridCorr_R[0][0]
+0x0F120000, //0012//awbb_GridCorr_R[0][1]
+0x0F120000, //0012//awbb_GridCorr_R[0][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060, //0050//awbb_GridCorr_R[0][5]
+0x0F120000, //0032//awbb_GridCorr_R[1][0]
+0x0F120000, //0012//awbb_GridCorr_R[1][1]
+0x0F120000, //0012//awbb_GridCorr_R[1][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060, //0050//awbb_GridCorr_R[1][5]
+0x0F120000, //0032//awbb_GridCorr_R[2][0]
+0x0F120000, //0012//awbb_GridCorr_R[2][1]
+0x0F120000, //0012//awbb_GridCorr_R[2][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060, //0050//awbb_GridCorr_R[2][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[0][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[1][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[2][5]
+          
+0x002A1160,
+0x0F120000, //awbb_GridCorr_R_Out[0][0]
+0x0F120000, //awbb_GridCorr_R_Out[0][1]
+0x0F120000, //awbb_GridCorr_R_Out[0][2]
+0x0F120000, //awbb_GridCorr_R_Out[0][3]
+0x0F120000, //awbb_GridCorr_R_Out[0][4]
+0x0F120000, //awbb_GridCorr_R_Out[0][5]
+0x0F120000, //awbb_GridCorr_R_Out[1][0]
+0x0F120000, //awbb_GridCorr_R_Out[1][1]
+0x0F120000, //awbb_GridCorr_R_Out[1][2]
+0x0F120000, //awbb_GridCorr_R_Out[1][3]
+0x0F120000, //awbb_GridCorr_R_Out[1][4]
+0x0F120000, //awbb_GridCorr_R_Out[1][5]
+0x0F120000, //awbb_GridCorr_R_Out[2][0]
+0x0F120000, //awbb_GridCorr_R_Out[2][1]
+0x0F120000, //awbb_GridCorr_R_Out[2][2]
+0x0F120000, //awbb_GridCorr_R_Out[2][3]
+0x0F120000, //awbb_GridCorr_R_Out[2][4]
+0x0F120000, //awbb_GridCorr_R_Out[2][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][5]
+
+   
+ // SLOW AWB
+0x002A110E, 	
+0x0F120258, //0258 awbb_GainsMaxMove //
+
+ //AWB Convergence Speed //
+0x002A11D6, 
+0x0F120008,
+0x0F12FFFF,//0190	awbb_WpFilterMaxThr//
+0x0F120010,//00A0	//awbb_WpFilterCoef p  //
+0x0F120020, //0004 awbb_WpFilterSize//
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201D4, //01DA 01CF 01CE 01C0 01D4 //TVAR_wbt_pBaseCcms[0] 
+0x0F12FFCD, //FFC4 FFC3 FFB9 FFCB FFB2 //TVAR_wbt_pBaseCcms[1] 
+0x0F12FFC4, //FFCD FFDD FFE8 FFE4 FFEE //TVAR_wbt_pBaseCcms[2] 
+0x0F12FF2A, //FF31 FF43 FF43 FF43 FF47 //TVAR_wbt_pBaseCcms[3] 
+0x0F120124, //012A 011D 011D 011D 012C //TVAR_wbt_pBaseCcms[4] 
+0x0F12FF73, //FF6B FF6B FF6B FF6B FF5C //TVAR_wbt_pBaseCcms[5] 
+0x0F12FFE1, //FFDA FFDA FFDA FFDA FFCE //TVAR_wbt_pBaseCcms[6] 
+0x0F12FFBD, //FFC3 FFD1 FFD1 FFD1 FFD6 //TVAR_wbt_pBaseCcms[7] 
+0x0F120159, //015F 0156 0156 0156 0162 //TVAR_wbt_pBaseCcms[8] 
+0x0F1200EF, //0100 00FF 00FC 00F7 011D //TVAR_wbt_pBaseCcms[9] 
+0x0F1200E0, //00DE 00CE 00CC 00D1 00C6 //TVAR_wbt_pBaseCcms[10]
+0x0F12FED9, //FECE FEE3 FEE9 FEE9 FED2 //TVAR_wbt_pBaseCcms[11]
+0x0F1200DA, //00D5 00CD 00CD 00CD 00C8 //TVAR_wbt_pBaseCcms[12]
+0x0F12FF57, //FF56 FF5E FF5E FF5E FF56 //TVAR_wbt_pBaseCcms[13]
+0x0F120119, //0123 0128 0128 0128 0139 //TVAR_wbt_pBaseCcms[14]
+0x0F12FF74, //FF73 FF7E FF7E FF7E FF75 //TVAR_wbt_pBaseCcms[15]
+0x0F1200DF, //00E9 00EC 00EC 00EC 00FB //TVAR_wbt_pBaseCcms[16]
+0x0F1200FF, //00FC 00F2 00F2 00F2 00F0 //TVAR_wbt_pBaseCcms[17]
+
+0x0F1201D4, //01D4 //TVAR_wbt_pBaseCcms[18]
+0x0F12FFCD, //FFB2 //TVAR_wbt_pBaseCcms[19]
+0x0F12FFC4, //FFEE //TVAR_wbt_pBaseCcms[20]
+0x0F12FF2A, //FF47 //TVAR_wbt_pBaseCcms[21]
+0x0F120124, //012C //TVAR_wbt_pBaseCcms[22]
+0x0F12FF73, //FF5C //TVAR_wbt_pBaseCcms[23]
+0x0F12FFE1, //FFCE //TVAR_wbt_pBaseCcms[24]
+0x0F12FFBD, //FFD6 //TVAR_wbt_pBaseCcms[25]
+0x0F120159, //0162 //TVAR_wbt_pBaseCcms[26]
+0x0F1200EF, //011D //TVAR_wbt_pBaseCcms[27]
+0x0F1200E0, //00C6 //TVAR_wbt_pBaseCcms[28]
+0x0F12FED9, //FED2 //TVAR_wbt_pBaseCcms[29]
+0x0F1200DA, //00C8 //TVAR_wbt_pBaseCcms[30]
+0x0F12FF57, //FF56 //TVAR_wbt_pBaseCcms[31]
+0x0F120119, //0139 //TVAR_wbt_pBaseCcms[32]
+0x0F12FF74, //FF75 //TVAR_wbt_pBaseCcms[33]
+0x0F1200DF, //00FB //TVAR_wbt_pBaseCcms[34]
+0x0F1200FF, //00F0 //TVAR_wbt_pBaseCcms[35]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[36]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[37]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[38]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[39]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[40]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[41]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[42]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[43]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[44]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[45]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[46]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[47]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[48]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[49]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[50]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[51]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[52]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[53]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[54]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[55]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[56]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[57]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[58]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[59]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[60]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[61]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[62]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[63]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[64]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[65]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[66]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[67]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[68]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[69]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[70]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[71]
+
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[72]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[73]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[74]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[75]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[76]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[77]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[78]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[79]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[80]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[81]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[82]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[83]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[84]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[85]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[86]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[87]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[88]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[89]
+          
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[90]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[91]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[92]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[93]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[94]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[95]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[96]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[97]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[98]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[99]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[100]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[101]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[102]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[103]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[104]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[105]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[106]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms 
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201BE, //0205 //01F8 //TVAR_wbt_pOutdoorCcm[0]
+0x0F12FFE4, //FF96 //FFAF //TVAR_wbt_pOutdoorCcm[1]
+0x0F120000, //FFDF //FFD3 //TVAR_wbt_pOutdoorCcm[2]
+0x0F12FEF9, //FEC8 //FEC4 //TVAR_wbt_pOutdoorCcm[3]
+0x0F120149, //01A4 //0191 //TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF70, //FF1C //FF33 //TVAR_wbt_pOutdoorCcm[5]
+0x0F12003C, //FFF7 //FFED //TVAR_wbt_pOutdoorCcm[6]
+0x0F120023, //000C //0017 //TVAR_wbt_pOutdoorCcm[7]
+0x0F1201DD, //0211 //0210 //TVAR_wbt_pOutdoorCcm[8]
+0x0F1200D4, //0107 //00E3 //TVAR_wbt_pOutdoorCcm[9]
+0x0F1200F8, //00F3 //0107 //TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF74, //FF1F //FF2F //TVAR_wbt_pOutdoorCcm[11]
+0x0F120212, //0220 //0220 //TVAR_wbt_pOutdoorCcm[12]
+0x0F120039, //FFE7 //FFE7 //TVAR_wbt_pOutdoorCcm[13]
+0x0F120184, //01A1 //01A1 //TVAR_wbt_pOutdoorCcm[14]
+0x0F12FF28, //FEC7 //FEC8 //TVAR_wbt_pOutdoorCcm[15]
+0x0F120133, //016D //017D //TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153 //0142 //TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F120040, //4A //40 //4A //0049 //#afit_uNoiseIndInDoor_0_
+0x0F120048, //48 //4E //005F //#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB //#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0 //#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220 //#afit_uNoiseIndInDoor_4_
+
+
+0x002A08C0,
+0x0F120030, //0007 //700008C0 //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //700008C2 //AFIT16_CONTRAST
+0x0F120010, //0000 //700008C4 //AFIT16_SATURATION
+0x0F120000, //0000 //700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //700008C8 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700008CA //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700008CC 
+0x0F1203FF, //03FF //700008CE //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700008D0 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700008D2 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700008D4 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700008D6 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700008D8 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700008DA //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700008DC //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700008DE //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700008E0 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700008E2 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0010 //700008E4 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0010 //700008E6 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //01F4 //700008E8 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C //700008EA //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008 //700008EC //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700008EE //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700008F0 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700008F2 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700008F4 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700008F6 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700008F8 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700008FA //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700008FC //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700008FE //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000900 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000902 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000904 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //09E8 //70000906 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000908 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //7000090A //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //7000090C //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //4000 //7000090E 
+0x0F125003, //7803 //70000910 
+0x0F123228, //3C50 //70000912 
+0x0F120032, //003C //70000914 
+0x0F121E80, //1E80 //70000916 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000918 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //7000091A //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //7000091C //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //7000091E //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //0F00 //70000920 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000922 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000924 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000926 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000928 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //7000092A //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //7000092C //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //7000092E //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000930 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000932 
+0x0F120609, //0609 //70000934 
+0x0F122C07, //2C07 //70000936 
+0x0F12142C, //142C //70000938 
+0x0F120518, //0718 //7000093A //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F128005, //8007 //7000093C //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594, //0880 //7000093E //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0B50 //70000940 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000942 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000944 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000946 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4601 //70000948 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B, //C844 //7000094A //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125038, //50C8 //7000094C //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //7000094E //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0003 //70000950 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //1C01 //70000952 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //0714 //70000954 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1464 //70000956 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125F01, //5A04 //70000958 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //3C1E //7000095A //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //400F //7000095C //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //7000095E //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1403 //70000960 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0114 //70000962 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000964 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //4446 //70000966 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //646E //70000968 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //7000096A //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //7000096C //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //7000096E //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000970 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000972 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000974 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000976 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000978 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //7000097A //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //7000097C //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1414 //7000097E //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000980 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //4601 //70000982 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //6E44 //70000984 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2864 //70000986 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000988 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //7000098A //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //7000098C //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //7000098E //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000990 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000992 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000994 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000996 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000998 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //7000099A //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //7000099C 
+0x0F120030, //0000 //7000099E //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //700009A0 //AFIT16_CONTRAST
+0x0F120010, //0000 //700009A2 //AFIT16_SATURATION
+0x0F120000, //0000 //700009A4 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //700009A6 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700009A8 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700009AA 
+0x0F1203FF, //03FF //700009AC //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700009AE //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700009B0 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700009B2 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700009B4 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700009B6 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700009B8 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700009BA //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700009BC //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700009BE //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700009C0 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //700009C2 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //700009C4 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //700009C6 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E //700009C8 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //700009CA //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700009CC //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700009CE //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700009D0 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700009D2 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700009D4 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700009D6 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700009D8 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700009DA //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700009DC //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //700009DE //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //700009E0 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //700009E2 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //05E8 //700009E4 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //700009E6 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //700009E8 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //700009EA //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000 //700009EC        
+0x0F125003, //5003 //700009EE        
+0x0F123228, //3228 //700009F0        
+0x0F120032, //0032 //700009F2        
+0x0F121E80, //1E80 //700009F4 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //700009F6 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //700009F8 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //700009FA //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //700009FC //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //1400 //700009FE //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000A00 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000A02 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000A04 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000A06 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000A08 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000A0A //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000A0C //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000A0E //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000A10        
+0x0F120609, //0609 //70000A12        
+0x0F122C07, //2C07 //70000A14        
+0x0F12142C, //142C //70000A16        
+0x0F120518, //0518 //70000A18 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000A1A //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594, //0580 //70000A1C //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000A1E //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000A20 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000A22 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000A24 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000A26 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B, //444B 494B //70000A28 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125038, //503C 5044 //70000A2A //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000A2C //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0503 //70000A2E //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //0D02 //70000A30 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //071E //70000A32 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1432 //70000A34 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125F01, //5A01 //70000A36 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //281E //70000A38 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //200F //70000A3A //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000A3C //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1E03 //70000A3E //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //011E //70000A40 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000A42 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //3A3C //70000A44 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //585A //70000A46 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000A48 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000A4A //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //70000A4C //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000A4E //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000A50 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000A52 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000A54 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000A56 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000A58 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000A5A //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1E1E //70000A5C //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000A5E //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //3C01 //70000A60 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //5A3A //70000A62 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2858 //70000A64 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000A66 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //70000A68 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //70000A6A //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //70000A6C //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000A6E //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000A70 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000A72 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000A74 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000A76 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000A78 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000A7A 
+0x0F120000, //0000 //70000A7C //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000A7E //AFIT16_CONTRAST
+0x0F120000, //0000 //70000A80 //AFIT16_SATURATION
+0x0F120000, //0000 //70000A82 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000A84 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000A86 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000A88        
+0x0F1203FF, //03FF //70000A8A //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000A8C //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000A8E //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000A90 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000A92 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000A94 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //70000A96 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000A98 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000A9A //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //70000A9C //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000A9E //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000AA0 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000AA2 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000AA4 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000AA6 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000AA8 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //003C //70000AAA //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //70000AAC //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //003C //70000AAE //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //70000AB0 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000AB2 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000AB4 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000AB6 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000AB8 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000ABA //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000ABC //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000ABE //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000AC0 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000AC2 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000AC4 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000AC6 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000AC8 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000ACA        
+0x0F122803, //2803 //70000ACC        
+0x0F12261E, //261E //70000ACE        
+0x0F120026, //0026 //70000AD0        
+0x0F121E80, //1E80 //70000AD2 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000AD4 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000AD6 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000AD8 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F124C0A, //3C0A //70000ADA //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122B12, //2300 //70000ADC //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000ADE //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000AE0 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000AE2 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000AE4 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000AE6 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000AE8 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000AEA //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000AEC //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000AEE        
+0x0F120609, //0609 //70000AF0        
+0x0F121C07, //1C07 //70000AF2        
+0x0F121014, //1014 //70000AF4        
+0x0F120510, //0510 //70000AF6 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000AF8 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000AFA //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000AFC //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000AFE //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000B00 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000B02 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000B04 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000B06 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000B08 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000B0A //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121B03, //1C03 //70000B0C //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F123003, //0D0C //70000B0E //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000B10 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000B12 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F128601, //6401 //70000B14 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12283E, //282D //70000B16 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000B18 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000B1A //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //2803 //70000B1C //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0128 //70000B1E //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000B20 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //2224 //70000B22 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //3236 //70000B24 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000B26 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000B28 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0410 //70000B2A //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //141E //70000B2C //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122807, //FF07 //70000B2E //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000B30 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4050 //70000B32 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //0F0F //70000B34 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000B36 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000B38 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F122828, //2828 //70000B3A //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000B3C //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //2401 //70000B3E //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //3622 //70000B40 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //2832 //70000B42 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000B44 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1003 //70000B46 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1E04 //70000B48 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //0714 //70000B4A //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000B4C //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5004 //70000B4E //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0F40 //70000B50 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //400F //70000B52 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000B54 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000B56 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000B58        
+0x0F120000, //0000 //70000B5A //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000B5C //AFIT16_CONTRAST
+0x0F120000, //0000 //70000B5E //AFIT16_SATURATION
+0x0F120000, //0000 //70000B60 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000B62 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000B64 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000B66 
+0x0F1203FF, //03FF //70000B68 //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000B6A //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000B6C //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000B6E //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000B70 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000B72 //AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8 //70000B74 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000B76 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000B78 //AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050 //70000B7A //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000B7C //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000B7E //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000B80 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000B82 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000B84 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000B86 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //002D //70000B88 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //70000B8A //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //002D //70000B8C //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //70000B8E //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000B90 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000B92 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000B94 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000B96 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000B98 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000B9A //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000B9C //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000B9E //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000BA0 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000BA2 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000BA4 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000BA6 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000BA8 
+0x0F122303, //2303 //70000BAA 
+0x0F12231A, //231A //70000BAC 
+0x0F120023, //0023 //70000BAE 
+0x0F121E80, //1E80 //70000BB0 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000BB2 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000BB4 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000BB6 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F127D0A, //3C0A //70000BB8 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122C24, //2300 //70000BBA //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000BBC //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000BBE //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000BC0 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //70000BC2 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000BC4 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000BC6 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000BC8 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //70000BCA //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120306, //0306 //70000BCC 
+0x0F120509, //0509 //70000BCE 
+0x0F122806, //2806 //70000BD0 
+0x0F121428, //1428 //70000BD2 
+0x0F120518, //0518 //70000BD4 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000BD6 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000BD8 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //70000BDA //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //70000BDC //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000BDE //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000BE0 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000BE2 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000BE4 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000BE6 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000BE8 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F122B03, //1C03 //70000BEA //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F126303, //0D0C //70000BEC //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000BEE //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000BF0 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12CC01, //6401 //70000BF2 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12283E, //282D //70000BF4 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000BF6 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000BF8 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //3C03 //70000BFA //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //013C //70000BFC //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000BFE //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //1C1E //70000C00 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1E22 //70000C02 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000C04 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000C06 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0214 //70000C08 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //0E14 //70000C0A //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122808, //FF06 //70000C0C //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000C0E //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4052 //70000C10 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //150C //70000C12 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000C14 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000C16 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F123C3C, //3C3C //70000C18 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000C1A //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //1E01 //70000C1C //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //221C //70000C1E //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //281E //70000C20 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000C22 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1403 //70000C24 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1402 //70000C26 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //060E //70000C28 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000C2A //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5204 //70000C2C //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0C40 //70000C2E //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //4015 //70000C30 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000C32 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000C34 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000C36 
+0x0F120000, //0000 //0000 //70000C38 //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //0000 //70000C3A //AFIT16_CONTRAST
+0x0F120000, //0000 //0000 //70000C3C //AFIT16_SATURATION
+0x0F120000, //0000 //0000 //70000C3E //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //0000 //70000C40 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //00C1 //70000C42 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //0000 //70000C44
+0x0F1203FF, //03FF //03FF //70000C46 //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //0008 //70000C48 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251 //017C //70000C4A //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //03FF //70000C4C //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //000C //70000C4E //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //0010 //70000C50 //AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032 //0032 //70000C52 //AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A //028A //70000C54 //AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032 //0032 //70000C56 //AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4 //01F4 //70000C58 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //0070 //70000C5A //AFIT16_demsharpmix1_iTune
+0x0F120002, //0002 //0002 //70000C5C //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //0000 //70000C5E //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //0320 //70000C60 //AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044 //0070 //70000C62 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //0014 //70000C64 //AFIT16_Sharpening_iHighSharpClamp
+0x0F120044, //0046 //0046 //70000C66 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //0019 //70000C68 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120044, //0046 //0046 //70000C6A //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //0019 //70000C6C //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //0A24 //70000C6E //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //1701 //70000C70 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //0229 //70000C72 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503 //0503 //70000C74 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F12080F, //080F //0101 //70000C76 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120808, //0808 //0101 //70000C78 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //0000 //70000C7A //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1200FF, //00FF //02FF //70000C7C //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D //0396 //70000C7E //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //1414 //70000C80 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //0301 //70000C82 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //0007 //70000C84 //AFIT8_sddd8a_iSquaresRounding [7:0]                        
+0x0F121000, //1000 //1000 //70000C86 
+0x0F122003, //2003 //2003 //70000C88 
+0x0F121020, //1020 //1020 //70000C8A 
+0x0F120010, //0010 //0010 //70000C8C 
+0x0F121EFF, //1EFF //1E80 //70000C8E //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E06, //1E06 //1E06 //70000C90 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12060A, //060A //030C //70000C92 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120306, //0306 //0103 //70000C94 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12810A, //8B0A //5A0A //70000C96 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F1215C4, //2837 //2D00 //70000C98 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120107, //0110 //0100 //70000C9A //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //FF00 //70000C9C //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //0200 //70000C9E //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //1E10 //70000CA0 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //0000 //70000CA2 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //0009 //70000CA4 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //0406 //70000CA6 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //0705 //70000CA8 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120305, //0305 //0305 //70000CAA 
+0x0F120609, //0609 //0609 //70000CAC 
+0x0F122C07, //2C07 //2C07 //70000CAE 
+0x0F12142C, //142C //142C //70000CB0 
+0x0F120B18, //0B18 //0B18 //70000CB2 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F12800B, //800B //800B //70000CB4 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]        
+0x0F120080, //0080 //0080 //70000CB6 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080 //0080 //70000CB8 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080 //0080 //70000CBA //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F125050, //5050 //0101 //70000CBC //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120101, //0101 //0A0A //70000CBE //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F123201, //3201 //3201 //70000CC0 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F120032, //1832 //1428 //70000CC2 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F122100, //210C //100C //70000CC4 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120A00, //0A00 //0500 //70000CC6 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F125004, //1E04 //1E02 //70000CC8 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F12A400, //0A08 //040C //70000CCA //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12070C, //070C //0828 //70000CCC //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F123264, //3264 //5064 //70000CCE //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12F802, //5A02 //4605 //70000CD0 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12103E, //1040 //1E68 //70000CD2 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F124012, //4012 //201E //70000CD4 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120604, //0604 //0604 //70000CD6 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F125006, //4606 //4606 //70000CD8 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120150, //0146 //0146 //70000CDA //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //0101 //70000CDC //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F123232, //1C18 //1C18 //70000CDE //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1819 //1819 //70000CE0 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120021, //0028 //0028 //70000CE2 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12040A, //030A //030A //70000CE4 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F12085E, //0514 //0514 //70000CE6 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120C0A, //0C14 //0C14 //70000CE8 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF05 //FF05 //70000CEA //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120119, //0432 //0432 //70000CEC //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F12406A, //4052 //4052 //70000CEE //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //1514 //1514 //70000CF0 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440 //0440 //70000CF2 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120606, //0302 //0302 //70000CF4 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F124646, //4646 //4646 //70000CF6 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //0101 //70000CF8 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F123201, //1801 //1801 //70000CFA //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F120032, //191C //191C //70000CFC //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122100, //2818 //2818 //70000CFE //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00 //0A00 //70000D00 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125E04, //1403 //1403 //70000D02 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120A08, //1405 //1405 //70000D04 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12070C, //050C //050C //70000D06 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121932, //32FF //32FF //70000D08 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //5204 //5204 //70000D0A //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120840, //1440 //1440 //70000D0C //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124009, //4015 //4015 //70000D0E //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120604, //0204 //0204 //70000D10 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120006, //0003 //0003 //70000D12 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //0001 //70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F12BF02, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+
+
+0x002a3fea,
+0x0f120800, //analog filter update Green
+
+
+// TNP_Regs_bUseAccurateFR
+0x00287000,
+0x002A3FE4,
+0x0F120001, // on/off TNP_Regs_bAccuDynamicFR
+0x0F1234A2, // on/off TNP_Regs_usMinAccuDynamicFrTme
+0x0F1240FD, // on/off TNP_Regs_usMaxAccuDynamicFrTme
+};
+#endif
+
+/* Return preview mode */
+static const u32 s5k5ccgx_preview_return[] =  {
+0xFCFCD000,
+0x00287000,
+
+0x002A085C,
+0x0F120040, //4A//40//4A//0049//#afit_uNoiseIndInDoor_0_
+0x0F120048, //48//4E//#afit_uNoiseIndInDoor_1_
+
+
+0x002A08C6,
+0x0F120002, //700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //700008C8 //AFIT16_GLAMOUR
+0x002A09A4,            
+0x0F120002, //700009A4 //AFIT16_SHARP_BLUR   
+0x0F120000, //700009A6 //AFIT16_GLAMOUR 
+                       
+0x002A08E4,            
+0x0F120001,	//700008E4 //AFIT16_demsharpmix1_iHystThLow
+                  
+0x002A0C7E,
+0x0F120396, //70000C7E//AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+0x002A0CC4,
+0x0F12100C, //70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+0x002A0836,
+0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+0x002A0D1E,
+0x0F122102, //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+/* 2048x1536 capture (Capture config0) */
+static const u32 s5k5ccgx_snapshot[] =
+{
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+	0xFFFF00A0,   //160ms
+};
+
+/* 640x480 capture (Capture config1) */
+static const u32 s5k5ccgx_snapshot_vga[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120001,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Write lowlight-regs before writing snapshot-regs
+ * in case of lowlight capture. */
+static const u32 s5k5ccgx_set_lowlight_reg[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A085C,
+0x0F12004A, //0049 //#afit_uNoiseIndInDoor_0_
+0x0F12004E, //005F //#afit_uNoiseIndInDoor_1_
+
+0x002A08C6,
+0x0F120000, //700008C6//AFIT16_SHARP_BLUR
+0x0F120010, //700008C8//AFIT16_GLAMOUR
+0x002A09A4,   
+0x0F120000, //700009A4//AFIT16_SHARP_BLUR   
+0x0F120010, //700009A6//AFIT16_GLAMOUR
+
+0x002A08E4,
+0x0F120010,	//700008E4//AFIT16_demsharpmix1_iHystThLow
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF012C,   //300ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_normal_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* For 2048x1152 cap */
+static const u32 s5k5ccgx_change_wide_cap[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_PrevInputHeightOfs (600h-480h)/2
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120480,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F1200C0,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120240,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120480,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+/* To change Wide Capture to Normal Capture,
+ * We have to restore capture configuration before starting Normal Capture.
+ */
+static const u32 s5k5ccgx_restore_capture_reg[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120600,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120300,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120600,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+static const u32 s5k5ccgx_get_light_status[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A3C,
+};
+
+static const u32 s5k5ccgx_get_iso_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A18,
+};
+
+static const u32 s5k5ccgx_get_shutterspeed_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A14,
+};
+
+static const u32 s5k5ccgx_fps_auto[] = {
+0x00287000,
+0x002A025A,
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+/* DSLIM.
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnablePreview
+0x0F120001, //REG_TC_GP_EnablePreviewChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_15fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12029A,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12029A,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_25fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F120190, //14E,//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F120190, //14E,//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_30fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12014E, //REG_0TC_PCFG_usMaxFrTimeMsecMult10 //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10 //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+/* effect off = normal */
+static const u32 s5k5ccgx_effect_off[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0648,
+0x0F120001,	//skl_af_bPregmOff	Pre/Post Gamma Off (¿øº¹)
+
+0x002A01E2,
+0x0F120000,	//REG_TC_GP_SpecialEffects	00:Normal Mode
+};
+
+static const u32 s5k5ccgx_effect_mono[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120001,	//REG_TC_GP_SpecialEffects	01:Mono Mode
+};
+
+static const u32 s5k5ccgx_effect_sepia[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120004,	//REG_TC_GP_SpecialEffects	04:Sepia Mode
+};
+
+static const u32 s5k5ccgx_effect_negative[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120003, //REG_TC_GP_SpecialEffects	03:Negative Mode
+};
+
+static const u32 s5k5ccgx_wb_auto[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,	//Mon_AAIO_bAWB		AWB ON
+};
+
+static const u32 s5k5ccgx_wb_daylight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120620,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120540,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_cloudy[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F1207B0, //REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F12046A, //REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_fluorescent[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120560,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F1208A0,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_incandescent[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F1203C0,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120980,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_brightness_m_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120016, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120020, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12002A, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120034, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_0[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120056,//TVAR_ae_BrAves
+
+};
+
+static const u32 s5k5ccgx_brightness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12006E,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120086,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12009E,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_scene_off[] = {
+// ==========================================================
+//	CAMERA_SCENE_OFF
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,		//Mon_AAIO_bAWB		0: AWB OFF, 1: AWB ON
+
+// Center (Metering)
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+//	01. Portait / Landscape / Text / Fall Color Off
+
+0x00287000,
+0x002A1308,
+0x0F12003E,	//TVAR_ae_BrAve
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x0F120000,	//REG_TC_UserContrast
+0x002A01D4,
+0x0F120000,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//	02. Night / Firework Off
+0x00287000,
+0x002A025A,
+0x0F1203E8,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+0x002A034C,
+0x0F120535,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120010,	// 0010 ae_GainIn_0_	//
+0x0F120020,	// 0020	ae_GainIn_1_	//
+0x0F120040,	// 0040	ae_GainIn_2_	//
+0x0F120080,	// 0080	ae_GainIn_3_	//
+0x0F120100,	// fix 0100	ae_GainIn_4_	//
+0x0F120200,	// 0200	ae_GainIn_5_	//
+0x0F120400,	// 0400	ae_GainIn_6_	//
+0x0F120800,	// 0800	ae_GainIn_7_	//
+0x0F122000,	// 2000	ae_GainIn_8_	//
+
+0x0F120010,	//0050//0010	ae_GainOut_0_	p	//
+0x0F120020,	//0070//0020	ae_GainOut_1_ p//
+0x0F120040,	//00A0//0040	ae_GainOut_2_	p	//
+0x0F120080,	//00D0//0080	ae_GainOut_3_	p	//
+0x0F120100,	//fix 0100	ae_GainOut_4_		//
+0x0F120200,	//0200	ae_GainOut_5_	//
+0x0F120400,	//0400	ae_GainOut_6_	//
+0x0F120800,	//0800	ae_GainOut_7_	//
+0x0F122000,	//2000	ae_GainOut_8_	//
+
+
+0x00287000,
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1	3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2	681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3	8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4	C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1	3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2	681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3	8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4	C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0524,
+0x0F120200, //1E0 //lt_uMaxAnGain1
+0x0F120200, //1E0 //lt_uMaxAnGain2
+0x0F120300,	//lt_uMaxAnGain3
+0x0F120840,	//lt_uMaxAnGain4
+
+0x0F120100,	//lt_uMaxDigGain
+0x0F128000,	//lt_uMaxTotGain
+
+0x0F120200, //1E0 //lt_uCapMaxAnGain1
+0x0F120200, //1E0 //lt_uCapMaxAnGain2
+0x0F120300,	//lt_uCapMaxAnGain3
+0x0F120710,	//lt_uCapMaxAnGain4
+
+0x0F120100,	//lt_uCapMaxDigGain
+0x0F128000,	//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120010,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120010,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F120B50,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+
+//	03. ISO Auto
+
+0x002A04A4,
+0x0F12067F,	//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+#if 0 /* DSLIM */
+/* 0x002A048C,*/
+/* 0x0F120001,*/	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+/* 0x0F120001,*/	//REG_SF_USER_FlickerQuantChanged
+#endif
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+0x002A0486,
+0x0F120000,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_portrait[] = {
+// ==========================================================
+//	CAMERA_SCENE_PORTRAIT (Auto/Center/Br0/Auto/Sharp-1/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,	//REG_TC_UserSaturation
+0x0F12FFF6,	//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_landscape[] = {
+// ==========================================================
+//	CAMERA_SCENE_LANDSCAPE (Auto/Matrix/Br0/Auto/Sharp+1/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F12000A,	//REG_TC_UserSharpBlur
+
+0x002A1316,	//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_scene_sports[] = {
+// ==========================================================
+//  CAMERA_SCENE_SPORTS (Sport/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+
+0x002A0504,
+0x0F121A0A,	//3415//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+
+0x002A0508,
+0x0F121E20,	//3415//lt_uMaxExp2		3415h = 13333d =  33.3325ms
+
+0x002A050C,
+0x0F123415,	//lt_uMaxExp3		3415h = 13333d =  33.3325ms
+0x002A0510,
+0x0F123415,	//lt_uMaxExp4		3415h = 13333d =  33.3325ms
+0x0F120000,
+
+
+0x002A0514,
+0x0F121A0A,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F121E20,	//lt_uCapMaxExp2		3415h = 13333d =  33.3325ms
+0x002A051C,
+0x0F123415,	//lt_uCapMaxExp3		3415h = 13333d =  33.3325ms
+0x002A0520,
+0x0F123415,	//lt_uCapMaxExp4		3415h = 13333d =  33.3325ms
+0x0F120000,
+
+0x002A0524,
+0x0F120300,	//lt_uMaxAnGain1
+0x0F120380,	//lt_uMaxAnGain2
+0x0F120480,	//lt_uMaxAnGain3
+0x0F120880,	//lt_uMaxAnGain4
+
+
+0x0F120100,	//lt_uMaxDigGain
+0x0F128000,	//lt_uMaxTotGain
+
+0x0F120300,	//lt_uCapMaxAnGain1
+0x0F120380,	//lt_uCapMaxAnGain2
+
+0x0F120480,	//lt_uCapMaxAnGain3
+0x0F120710,	//lt_uCapMaxAnGain4
+
+0x0F120100,	//lt_uCapMaxDigGain
+0x0F128000,	//lt_uCapMaxTotGain
+
+// ISO Gain
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,
+
+//Preview
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_party[] = {
+// ==========================================================
+//	CAMERA_SCENE_PARTYINDOOR (ISO200/Center/Br0/Auto/Sharp0/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120030,	// 0010 ae_GainIn_0_//						
+0x0F120090,	// 0020	ae_GainIn_1_//					
+0x0F1200A8,	// 0040	ae_GainIn_2_//					
+0x0F1200C0,	// 0080	ae_GainIn_3_//					
+0x0F120100,	// fix 0100	ae_GainIn_4_//					
+0x0F120140,	// 0200	ae_GainIn_5_//					
+0x0F120180,	// 0400	ae_GainIn_6_//					
+0x0F120400,	// 0800	ae_GainIn_7_//					
+0x0F122000,	// 2000	ae_GainIn_8_//	
+
+0x0F120080,	//0050//0010	ae_GainOut_0_	p	//						
+0x0F1200D0,	//0070//0020	ae_GainOut_1_ p//						
+0x0F1200D8,	//00A0//0040	ae_GainOut_2_	p	//						
+0x0F1200f8,	//00D0//0080	ae_GainOut_3_	p	//						
+0x0F120100,	//fix 0100	ae_GainOut_4_		//						
+0x0F120103,	//0200	ae_GainOut_5_//						
+0x0F120110,	//0400	ae_GainOut_6_//						
+0x0F120150,	//0800	ae_GainOut_7_//						
+0x0F120400,	//2000	ae_GainOut_8_//		
+
+//ISO 200
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1	C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2	C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3	C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4	C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1 C350h = 50000d = 125.0000ms
+0x002A0518,                  
+0x0F12C350,	//lt_uCapMaxExp2 C350h = 50000d = 125.0000ms
+0x002A051C,                  
+0x0F12C350,	//lt_uCapMaxExp3 C350h = 50000d = 125.0000ms
+0x002A0520,                  
+0x0F12C350,	//lt_uCapMaxExp4 C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120180,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120300,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_beach[] = {
+// ==========================================================
+//	CAMERA_SCENE_BEACHSNOW (ISO50/Center/Br+1/Auto/Sharp0/Sat+1)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120020,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//ISO 50
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120150,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_sunset[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120526,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_dawn[] = {
+// Use MWB CWF
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120530,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F1207E6,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_fall[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120032,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+};
+
+static const u32 s5k5ccgx_scene_nightshot[] = {
+// ==========================================================
+//	CAMERA_SCENE_NIGHT (Night/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F1209C4,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F121388,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F121388,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,	//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,	//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0524,
+0x0F1201D0,	//lt_uMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,	//lt_uMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,	//lt_uMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,	//lt_uMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,	//lt_uMaxDigGain
+0x0F128000,	//lt_uMaxTotGain
+
+0x0F1201D0,	//lt_uCapMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,	//lt_uCapMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,	//lt_uCapMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,	//lt_uCapMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,	//lt_uCapMaxDigGain
+0x0F128000,	//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120000,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120000,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F121080,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_backlight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+/* Not Used */
+static const u32 s5k5ccgx_scene_firework[] = {
+// ==========================================================
+//	CAMERA_SCENE_FIREWORK (ISO50/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F1209C4,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F122710,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F122710,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,	//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,	//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+//ISO 50
+
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_text[] = {
+// ==========================================================
+//	CAMERA_SCENE_TEXT (Auto/Center/Br0/Auto/Sharp+2/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120014,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_candle[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120526,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_metering_normal[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_metering_spot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+
+static const u32 s5k5ccgx_metering_center[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_auto[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12067F,	//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0486,
+0x0F120000,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,	//AFIT by Normalized Brightness Tunning Parameter
+
+//Preview
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_50[] = {
+
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_100[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120200,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_200[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120400,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_400[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120800,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_ae_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120000, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12FFFF, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_ae_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120001, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12001E, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_af_abort[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120001, // REG_TC_AF_AfCmd = 1, Abort A
+};
+
+static const u32 s5k5ccgx_af_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004,
+0xFFFF0043, //67 ms delay,  Min 1 frame delay
+0x002A0226, // write [7000 0226, REG_TC_AF_AfCmdParam]
+0x0F120000, // write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.
+0xFFFF0096, // 150ms Delay
+};
+
+static const u32 s5k5ccgx_af_normal_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+0xFFFF0096, /* 150ms Delay */
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+0x002A1494,
+0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_night_normal_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+
+0xFFFF00FA, /* 150ms Delay*/
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+0x002A1494,
+0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_macro_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120095, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+0xFFFF0096, /* 150ms Delay */
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+
+0x002A1494,
+0x0F121042,
+
+/* when user use lens position 16(10h) -> lens position 0(00h)
+MSB 10 b means user uses #af_pos_usTable_16_ as start position.
+LSB 00 b means user uses #af_pos_usTable_0_ as end position
+refer to 5.3 macro mode setting.
+"#af_pos_usMacroStartEnd" is only used in macro AF condition.
+(normal AF doesn't use "#af_pos_usMacroStartEnd") */
+0x002A1426,
+0x0F121000, /* #af_pos_usMacroStartEn */
+};
+
+static const u32 s5k5ccgx_af_do[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120005,   // REG_TC_AF_AfCmd = 5, single A
+};
+
+static const u32 s5k5ccgx_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_1st_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+0xFFFF01F4, /* tuning point */
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+#ifdef CONFIG_MACH_P8LTE
+#define S5K5CCGX_ANTIBANDING_REG s5k5ccgx_antibanding_60hz_reg
+/* 60Hz anti-flicker for LTE */
+static const u32 s5k5ccgx_antibanding_60hz_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0F08,
+0x0F120001, //AFC_Default60Hz   01:60hz 00:50Hz	
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+#else
+#define S5K5CCGX_ANTIBANDING_REG s5k5ccgx_antibanding_50hz_reg
+/* 50Hz anti-flicker */
+static const u32 s5k5ccgx_antibanding_50hz_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz	
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+#endif /* #ifdef CONFIG_MACH_P8LTE */
+
+static const u32 s5k5ccgx_contrast_m_2[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_m_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_0[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D2,
+//0F120080,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_saturation_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12007E,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFE0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120005,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D6,
+0x0F120010,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_dtp_on[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_dtp_off[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_pll_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_pll_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_preflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F82,
+0x0F120001,		// TNP_Regs_PreflashStart
+};
+
+static const u32 s5k5ccgx_preflash_end[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F84,
+0x0F120001,		// TNP_Regs_PreflashEnd
+};
+
+static const u32 s5k5ccgx_mainflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F80,		//TNP_Regs_FastFlashAlg
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_mainflash_end[] = {
+};
+
+static const u32 s5k5ccgx_flash_ae_set[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_flash_ae_clear[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120002,
+};
+
+static const u32 s5k5ccgx_get_ae_stable_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E1E3C,
+};
+
+static const u32 s5k5ccgx_get_esd_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E0150,
+};
+
+#endif /* __S5K5CCGX_REG_H__ */
diff --git a/drivers/media/video/s5k5ccgx_regs-p2.h b/drivers/media/video/s5k5ccgx_regs-p2.h
new file mode 100644
index 0000000..b4fde3f
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx_regs-p2.h
@@ -0,0 +1,16321 @@
+/* drivers/media/video/s5k5ccgx_regs-p2.h
+ *
+ * Driver for s5k5ccgx (5MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+
+#ifndef __S5K5CCGX_REGS_P2_H__
+#define __S5K5CCGX_REGS_P2_H__
+
+#if defined(FEATURE_YUV_CAPTURE)
+/* Init regs for YUV capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+	0xFCFCD000,	//Reset                                  //
+	0x00140001,   //Wait100mSec                            //
+	0x10021101,
+
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	/*++ Add ESD */
+	0x002A0150,
+	0x0F12AAAA,
+	/*-- Add ESD */
+	0x002A352C,
+	0x0F12B5F8,    // 7000352C
+	0x0F124A28,    // 7000352E
+	0x0F124928,    // 70003530
+	0x0F124829,    // 70003532
+	0x0F124B29,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124928,    // 7000353E
+	0x0F124828,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FBB9,    // 70003544
+	0x0F124928,    // 70003546
+	0x0F124828,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FBB5,    // 7000354C
+	0x0F124828,    // 7000354E
+	0x0F124E28,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124928,    // 70003554
+	0x0F124829,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FBAE,    // 7000355A
+	0x0F124828,    // 7000355C
+	0x0F120037,    // 7000355E
+	0x0F123780,    // 70003560
+	0x0F126178,    // 70003562
+	0x0F124C27,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124927,    // 70003568
+	0x0F124828,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FBA4,    // 7000356E
+	0x0F124927,    // 70003570
+	0x0F124828,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FBA0,    // 70003576
+	0x0F124927,    // 70003578
+	0x0F124828,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FB9C,    // 7000357E
+	0x0F124927,    // 70003580
+	0x0F124828,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB98,    // 70003586
+	0x0F1283A5,    // 70003588
+	0x0F124827,    // 7000358A
+	0x0F126470,    // 7000358C
+	0x0F122001,    // 7000358E
+	0x0F120340,    // 70003590
+	0x0F123420,    // 70003592
+	0x0F128060,    // 70003594
+	0x0F122085,    // 70003596
+	0x0F1280A0,    // 70003598
+	0x0F124824,    // 7000359A
+	0x0F1280E0,    // 7000359C
+	0x0F124824,    // 7000359E
+	0x0F126730,    // 700035A0
+	0x0F124924,    // 700035A2
+	0x0F124824,    // 700035A4
+	0x0F12F000,    // 700035A6
+	0x0F12FB87,    // 700035A8
+	0x0F1281E5,    // 700035AA
+	0x0F128225,    // 700035AC
+	0x0F124823,    // 700035AE
+	0x0F1282A0,    // 700035B0
+	0x0F124813,    // 700035B2
+	0x0F126178,    // 700035B4
+	0x0F122001,    // 700035B6
+	0x0F128260,    // 700035B8
+	0x0F124921,    // 700035BA
+	0x0F124821,    // 700035BC
+	0x0F12F000,    // 700035BE
+	0x0F12FB7B,    // 700035C0
+	0x0F124921,    // 700035C2
+	0x0F124821,    // 700035C4
+	0x0F12F000,    // 700035C6
+	0x0F12FB77,    // 700035C8
+	0x0F12BCF8,    // 700035CA
+	0x0F12BC08,    // 700035CC
+	0x0F124718,    // 700035CE
+	0x0F1200D6,    // 700035D0
+	0x0F125CC1,    // 700035D2
+	0x0F12633D,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F121C08,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F123290,    // 700035DC
+	0x0F127000,    // 700035DE
+	0x0F12366F,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F12D9E7,    // 700035E4
+	0x0F120000,    // 700035E6
+	0x0F123857,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F12395D,    // 700035EC
+	0x0F120000,    // 700035EE
+	0x0F1238E9,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F120000,    // 700035F4
+	0x0F127000,    // 700035F6
+	0x0F1239B5,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12F903,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F123BAF,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F123FC8,    // 70003604
+	0x0F127000,    // 70003606
+	0x0F1236A7,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F12495F,    // 7000360C
+	0x0F120000,    // 7000360E
+	0x0F123705,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F12E421,    // 70003614
+	0x0F120000,    // 70003616
+	0x0F1237C3,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F12216D,    // 7000361C
+	0x0F120000,    // 7000361E
+	0x0F123837,    // 70003620
+	0x0F127000,    // 70003622
+	0x0F120179,    // 70003624
+	0x0F120001,    // 70003626
+	0x0F123AD9,    // 70003628
+	0x0F127000,    // 7000362A
+	0x0F1207FF,    // 7000362C
+	0x0F120000,    // 7000362E
+	0x0F123B4D,    // 70003630
+	0x0F127000,    // 70003632
+	0x0F123B75,    // 70003634
+	0x0F127000,    // 70003636
+	0x0F12E8AD,    // 70003638
+	0x0F120000,    // 7000363A
+	0x0F124E20,    // 7000363C
+	0x0F120000,    // 7000363E
+	0x0F123C29,    // 70003640
+	0x0F127000,    // 70003642
+	0x0F123C4D,    // 70003644
+	0x0F120000,    // 70003646
+	0x0F123C2B,    // 70003648
+	0x0F127000,    // 7000364A
+	0x0F123F0D,    // 7000364C
+	0x0F120000,    // 7000364E
+	0x0F12B570,    // 70003650
+	0x0F12000D,    // 70003652
+	0x0F124CFC,    // 70003654
+	0x0F128821,    // 70003656
+	0x0F12F000,    // 70003658
+	0x0F12FB36,    // 7000365A
+	0x0F128820,    // 7000365C
+	0x0F124AFB,    // 7000365E
+	0x0F120081,    // 70003660
+	0x0F125055,    // 70003662
+	0x0F121C40,    // 70003664
+	0x0F128020,    // 70003666
+	0x0F12BC70,    // 70003668
+	0x0F12BC08,    // 7000366A
+	0x0F124718,    // 7000366C
+	0x0F126801,    // 7000366E
+	0x0F120409,    // 70003670
+	0x0F120C09,    // 70003672
+	0x0F126840,    // 70003674
+	0x0F120400,    // 70003676
+	0x0F120C00,    // 70003678
+	0x0F124AF5,    // 7000367A
+	0x0F128992,    // 7000367C
+	0x0F122A00,    // 7000367E
+	0x0F12D00D,    // 70003680
+	0x0F122300,    // 70003682
+	0x0F121A80,    // 70003684
+	0x0F12D400,    // 70003686
+	0x0F120003,    // 70003688
+	0x0F120418,    // 7000368A
+	0x0F120C00,    // 7000368C
+	0x0F124BF1,    // 7000368E
+	0x0F121851,    // 70003690
+	0x0F12891B,    // 70003692
+	0x0F12428B,    // 70003694
+	0x0F12D300,    // 70003696
+	0x0F12000B,    // 70003698
+	0x0F120419,    // 7000369A
+	0x0F120C09,    // 7000369C
+	0x0F124AEE,    // 7000369E
+	0x0F128151,    // 700036A0
+	0x0F128190,    // 700036A2
+	0x0F124770,    // 700036A4
+	0x0F12B510,    // 700036A6
+	0x0F124CEC,    // 700036A8
+	0x0F1248ED,    // 700036AA
+	0x0F1278A1,    // 700036AC
+	0x0F122900,    // 700036AE
+	0x0F12D101,    // 700036B0
+	0x0F1287C1,    // 700036B2
+	0x0F12E004,    // 700036B4
+	0x0F127AE1,    // 700036B6
+	0x0F122900,    // 700036B8
+	0x0F12D001,    // 700036BA
+	0x0F122101,    // 700036BC
+	0x0F1287C1,    // 700036BE
+	0x0F12F000,    // 700036C0
+	0x0F12FB0A,    // 700036C2
+	0x0F1249E7,    // 700036C4
+	0x0F128B08,    // 700036C6
+	0x0F1206C2,    // 700036C8
+	0x0F12D50A,    // 700036CA
+	0x0F127AA2,    // 700036CC
+	0x0F120652,    // 700036CE
+	0x0F12D507,    // 700036D0
+	0x0F122210,    // 700036D2
+	0x0F124390,    // 700036D4
+	0x0F128308,    // 700036D6
+	0x0F1248E3,    // 700036D8
+	0x0F127AE1,    // 700036DA
+	0x0F126B00,    // 700036DC
+	0x0F12F000,    // 700036DE
+	0x0F12FB03,    // 700036E0
+	0x0F1248DB,    // 700036E2
+	0x0F1289C0,    // 700036E4
+	0x0F122801,    // 700036E6
+	0x0F12D109,    // 700036E8
+	0x0F1278A0,    // 700036EA
+	0x0F122800,    // 700036EC
+	0x0F12D006,    // 700036EE
+	0x0F127AE0,    // 700036F0
+	0x0F122800,    // 700036F2
+	0x0F12D003,    // 700036F4
+	0x0F127AA0,    // 700036F6
+	0x0F122140,    // 700036F8
+	0x0F124308,    // 700036FA
+	0x0F1272A0,    // 700036FC
+	0x0F12BC10,    // 700036FE
+	0x0F12BC08,    // 70003700
+	0x0F124718,    // 70003702
+	0x0F12B570,    // 70003704
+	0x0F124DD7,    // 70003706
+	0x0F124CD7,    // 70003708
+	0x0F128B28,    // 7000370A
+	0x0F120701,    // 7000370C
+	0x0F12D507,    // 7000370E
+	0x0F122108,    // 70003710
+	0x0F124388,    // 70003712
+	0x0F128328,    // 70003714
+	0x0F1249D5,    // 70003716
+	0x0F126B20,    // 70003718
+	0x0F126B89,    // 7000371A
+	0x0F12F000,    // 7000371C
+	0x0F12FAEC,    // 7000371E
+	0x0F128B28,    // 70003720
+	0x0F1206C1,    // 70003722
+	0x0F12D5A0,    // 70003724
+	0x0F1249CD,    // 70003726
+	0x0F127A8A,    // 70003728
+	0x0F120652,    // 7000372A
+	0x0F12D49C,    // 7000372C
+	0x0F122210,    // 7000372E
+	0x0F124390,    // 70003730
+	0x0F128328,    // 70003732
+	0x0F127AC9,    // 70003734
+	0x0F126B20,    // 70003736
+	0x0F12F000,    // 70003738
+	0x0F12FAD6,    // 7000373A
+	0x0F12E794,    // 7000373C
+	0x0F12B5F8,    // 7000373E
+	0x0F1249CB,    // 70003740
+	0x0F128F08,    // 70003742
+	0x0F12000C,    // 70003744
+	0x0F123480,    // 70003746
+	0x0F122800,    // 70003748
+	0x0F12D000,    // 7000374A
+	0x0F128360,    // 7000374C
+	0x0F122000,    // 7000374E
+	0x0F128708,    // 70003750
+	0x0F124DC8,    // 70003752
+	0x0F1226FF,    // 70003754
+	0x0F128828,    // 70003756
+	0x0F121C76,    // 70003758
+	0x0F122702,    // 7000375A
+	0x0F122803,    // 7000375C
+	0x0F12D112,    // 7000375E
+	0x0F128868,    // 70003760
+	0x0F122800,    // 70003762
+	0x0F12D10F,    // 70003764
+	0x0F1288E8,    // 70003766
+	0x0F122800,    // 70003768
+	0x0F12D10C,    // 7000376A
+	0x0F12F000,    // 7000376C
+	0x0F12FACC,    // 7000376E
+	0x0F122800,    // 70003770
+	0x0F12D008,    // 70003772
+	0x0F128B60,    // 70003774
+	0x0F122800,    // 70003776
+	0x0F12D001,    // 70003778
+	0x0F1280EE,    // 7000377A
+	0x0F1280AF,    // 7000377C
+	0x0F122001,    // 7000377E
+	0x0F127268,    // 70003780
+	0x0F12F000,    // 70003782
+	0x0F12FAC9,    // 70003784
+	0x0F128828,    // 70003786
+	0x0F122802,    // 70003788
+	0x0F12D10E,    // 7000378A
+	0x0F128868,    // 7000378C
+	0x0F122800,    // 7000378E
+	0x0F12D10B,    // 70003790
+	0x0F1288E8,    // 70003792
+	0x0F122800,    // 70003794
+	0x0F12D108,    // 70003796
+	0x0F128B60,    // 70003798
+	0x0F122800,    // 7000379A
+	0x0F12D001,    // 7000379C
+	0x0F1280EE,    // 7000379E
+	0x0F1280AF,    // 700037A0
+	0x0F122001,    // 700037A2
+	0x0F127268,    // 700037A4
+	0x0F12F000,    // 700037A6
+	0x0F12FAB7,    // 700037A8
+	0x0F1288E8,    // 700037AA
+	0x0F122800,    // 700037AC
+	0x0F12D006,    // 700037AE
+	0x0F121FC1,    // 700037B0
+	0x0F1239FD,    // 700037B2
+	0x0F12D003,    // 700037B4
+	0x0F122001,    // 700037B6
+	0x0F12BCF8,    // 700037B8
+	0x0F12BC08,    // 700037BA
+	0x0F124718,    // 700037BC
+	0x0F122000,    // 700037BE
+	0x0F12E7FA,    // 700037C0
+	0x0F12B570,    // 700037C2
+	0x0F124CAC,    // 700037C4
+	0x0F128860,    // 700037C6
+	0x0F122800,    // 700037C8
+	0x0F12D00C,    // 700037CA
+	0x0F128820,    // 700037CC
+	0x0F124DA3,    // 700037CE
+	0x0F122800,    // 700037D0
+	0x0F12D009,    // 700037D2
+	0x0F120029,    // 700037D4
+	0x0F1231A0,    // 700037D6
+	0x0F127AC9,    // 700037D8
+	0x0F122900,    // 700037DA
+	0x0F12D004,    // 700037DC
+	0x0F127AA8,    // 700037DE
+	0x0F122180,    // 700037E0
+	0x0F124308,    // 700037E2
+	0x0F1272A8,    // 700037E4
+	0x0F12E73F,    // 700037E6
+	0x0F122800,    // 700037E8
+	0x0F12D003,    // 700037EA
+	0x0F12F7FF,    // 700037EC
+	0x0F12FFA7,    // 700037EE
+	0x0F122800,    // 700037F0
+	0x0F12D1F8,    // 700037F2
+	0x0F122000,    // 700037F4
+	0x0F128060,    // 700037F6
+	0x0F128820,    // 700037F8
+	0x0F122800,    // 700037FA
+	0x0F12D003,    // 700037FC
+	0x0F122008,    // 700037FE
+	0x0F12F000,    // 70003800
+	0x0F12FA92,    // 70003802
+	0x0F12E00B,    // 70003804
+	0x0F12489C,    // 70003806
+	0x0F123020,    // 70003808
+	0x0F128880,    // 7000380A
+	0x0F122800,    // 7000380C
+	0x0F12D103,    // 7000380E
+	0x0F127AA8,    // 70003810
+	0x0F122101,    // 70003812
+	0x0F124308,    // 70003814
+	0x0F1272A8,    // 70003816
+	0x0F122010,    // 70003818
+	0x0F12F000,    // 7000381A
+	0x0F12FA85,    // 7000381C
+	0x0F128820,    // 7000381E
+	0x0F122800,    // 70003820
+	0x0F12D1E0,    // 70003822
+	0x0F12488A,    // 70003824
+	0x0F1289C0,    // 70003826
+	0x0F122801,    // 70003828
+	0x0F12D1DC,    // 7000382A
+	0x0F127AA8,    // 7000382C
+	0x0F1221BF,    // 7000382E
+	0x0F124008,    // 70003830
+	0x0F1272A8,    // 70003832
+	0x0F12E718,    // 70003834
+	0x0F126800,    // 70003836
+	0x0F124990,    // 70003838
+	0x0F128188,    // 7000383A
+	0x0F124890,    // 7000383C
+	0x0F122201,    // 7000383E
+	0x0F128981,    // 70003840
+	0x0F124890,    // 70003842
+	0x0F120252,    // 70003844
+	0x0F124291,    // 70003846
+	0x0F12D902,    // 70003848
+	0x0F122102,    // 7000384A
+	0x0F128181,    // 7000384C
+	0x0F124770,    // 7000384E
+	0x0F122101,    // 70003850
+	0x0F128181,    // 70003852
+	0x0F124770,    // 70003854
+	0x0F12B5F1,    // 70003856
+	0x0F124E80,    // 70003858
+	0x0F128834,    // 7000385A
+	0x0F122C00,    // 7000385C
+	0x0F12D03F,    // 7000385E
+	0x0F122001,    // 70003860
+	0x0F122C08,    // 70003862
+	0x0F12D000,    // 70003864
+	0x0F122000,    // 70003866
+	0x0F1270B0,    // 70003868
+	0x0F124D7F,    // 7000386A
+	0x0F122800,    // 7000386C
+	0x0F12D009,    // 7000386E
+	0x0F12F000,    // 70003870
+	0x0F12FA62,    // 70003872
+	0x0F120028,    // 70003874
+	0x0F1238F0,    // 70003876
+	0x0F126328,    // 70003878
+	0x0F127AB0,    // 7000387A
+	0x0F12217E,    // 7000387C
+	0x0F124008,    // 7000387E
+	0x0F1272B0,    // 70003880
+	0x0F12E00F,    // 70003882
+	0x0F124F7A,    // 70003884
+	0x0F123780,    // 70003886
+	0x0F128B78,    // 70003888
+	0x0F122800,    // 7000388A
+	0x0F12D005,    // 7000388C
+	0x0F12F000,    // 7000388E
+	0x0F12FA5B,    // 70003890
+	0x0F122000,    // 70003892
+	0x0F128378,    // 70003894
+	0x0F124976,    // 70003896
+	0x0F128708,    // 70003898
+	0x0F122000,    // 7000389A
+	0x0F12F000,    // 7000389C
+	0x0F12FA5C,    // 7000389E
+	0x0F124879,    // 700038A0
+	0x0F126328,    // 700038A2
+	0x0F1278B1,    // 700038A4
+	0x0F122700,    // 700038A6
+	0x0F120038,    // 700038A8
+	0x0F122900,    // 700038AA
+	0x0F12D008,    // 700038AC
+	0x0F124972,    // 700038AE
+	0x0F123920,    // 700038B0
+	0x0F128ACA,    // 700038B2
+	0x0F122A00,    // 700038B4
+	0x0F12D003,    // 700038B6
+	0x0F128B09,    // 700038B8
+	0x0F122900,    // 700038BA
+	0x0F12D000,    // 700038BC
+	0x0F122001,    // 700038BE
+	0x0F127170,    // 700038C0
+	0x0F122C02,    // 700038C2
+	0x0F12D102,    // 700038C4
+	0x0F124868,    // 700038C6
+	0x0F123860,    // 700038C8
+	0x0F126328,    // 700038CA
+	0x0F122201,    // 700038CC
+	0x0F122C02,    // 700038CE
+	0x0F12D000,    // 700038D0
+	0x0F122200,    // 700038D2
+	0x0F124861,    // 700038D4
+	0x0F122110,    // 700038D6
+	0x0F12300A,    // 700038D8
+	0x0F12F000,    // 700038DA
+	0x0F12FA45,    // 700038DC
+	0x0F128037,    // 700038DE
+	0x0F129900,    // 700038E0
+	0x0F120020,    // 700038E2
+	0x0F12600C,    // 700038E4
+	0x0F12E767,    // 700038E6
+	0x0F12B538,    // 700038E8
+	0x0F124865,    // 700038EA
+	0x0F124669,    // 700038EC
+	0x0F123848,    // 700038EE
+	0x0F12F000,    // 700038F0
+	0x0F12FA42,    // 700038F2
+	0x0F124A5E,    // 700038F4
+	0x0F124862,    // 700038F6
+	0x0F128F51,    // 700038F8
+	0x0F122400,    // 700038FA
+	0x0F123020,    // 700038FC
+	0x0F122900,    // 700038FE
+	0x0F12D00A,    // 70003900
+	0x0F128754,    // 70003902
+	0x0F126941,    // 70003904
+	0x0F126451,    // 70003906
+	0x0F126491,    // 70003908
+	0x0F12466B,    // 7000390A
+	0x0F128819,    // 7000390C
+	0x0F1287D1,    // 7000390E
+	0x0F12885B,    // 70003910
+	0x0F120011,    // 70003912
+	0x0F123140,    // 70003914
+	0x0F12800B,    // 70003916
+	0x0F128F91,    // 70003918
+	0x0F122900,    // 7000391A
+	0x0F12D002,    // 7000391C
+	0x0F128794,    // 7000391E
+	0x0F126940,    // 70003920
+	0x0F126490,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA30,    // 70003926
+	0x0F12BC38,    // 70003928
+	0x0F12BC08,    // 7000392A
+	0x0F124718,    // 7000392C
+	0x0F12B5F8,    // 7000392E
+	0x0F124C56,    // 70003930
+	0x0F1289E0,    // 70003932
+	0x0F12F000,    // 70003934
+	0x0F12FA30,    // 70003936
+	0x0F120006,    // 70003938
+	0x0F128A20,    // 7000393A
+	0x0F12F000,    // 7000393C
+	0x0F12FA34,    // 7000393E
+	0x0F120007,    // 70003940
+	0x0F12484F,    // 70003942
+	0x0F124D4A,    // 70003944
+	0x0F123020,    // 70003946
+	0x0F126CA9,    // 70003948
+	0x0F126940,    // 7000394A
+	0x0F121809,    // 7000394C
+	0x0F120200,    // 7000394E
+	0x0F12F000,    // 70003950
+	0x0F12FA32,    // 70003952
+	0x0F120400,    // 70003954
+	0x0F120C00,    // 70003956
+	0x0F12002A,    // 70003958
+	0x0F12326E,    // 7000395A
+	0x0F120011,    // 7000395C
+	0x0F12390A,    // 7000395E
+	0x0F122305,    // 70003960
+	0x0F12F000,    // 70003962
+	0x0F12FA2F,    // 70003964
+	0x0F124C43,    // 70003966
+	0x0F1261A0,    // 70003968
+	0x0F128FEB,    // 7000396A
+	0x0F120002,    // 7000396C
+	0x0F120031,    // 7000396E
+	0x0F120018,    // 70003970
+	0x0F12F000,    // 70003972
+	0x0F12FA2F,    // 70003974
+	0x0F12466B,    // 70003976
+	0x0F120005,    // 70003978
+	0x0F128018,    // 7000397A
+	0x0F12483C,    // 7000397C
+	0x0F1269A2,    // 7000397E
+	0x0F123040,    // 70003980
+	0x0F128800,    // 70003982
+	0x0F120039,    // 70003984
+	0x0F12F000,    // 70003986
+	0x0F12FA25,    // 70003988
+	0x0F12466B,    // 7000398A
+	0x0F120006,    // 7000398C
+	0x0F128058,    // 7000398E
+	0x0F120021,    // 70003990
+	0x0F129800,    // 70003992
+	0x0F12311C,    // 70003994
+	0x0F12F000,    // 70003996
+	0x0F12FA25,    // 70003998
+	0x0F124935,    // 7000399A
+	0x0F123180,    // 7000399C
+	0x0F12808D,    // 7000399E
+	0x0F1280CE,    // 700039A0
+	0x0F128BA1,    // 700039A2
+	0x0F124836,    // 700039A4
+	0x0F123820,    // 700039A6
+	0x0F128001,    // 700039A8
+	0x0F128BE1,    // 700039AA
+	0x0F128041,    // 700039AC
+	0x0F128C21,    // 700039AE
+	0x0F128081,    // 700039B0
+	0x0F12E701,    // 700039B2
+	0x0F12B5F8,    // 700039B4
+	0x0F124E2E,    // 700039B6
+	0x0F126C70,    // 700039B8
+	0x0F126CB1,    // 700039BA
+	0x0F120200,    // 700039BC
+	0x0F12F000,    // 700039BE
+	0x0F12F9FB,    // 700039C0
+	0x0F120400,    // 700039C2
+	0x0F120C00,    // 700039C4
+	0x0F122401,    // 700039C6
+	0x0F120364,    // 700039C8
+	0x0F1242A0,    // 700039CA
+	0x0F12D200,    // 700039CC
+	0x0F120004,    // 700039CE
+	0x0F124A27,    // 700039D0
+	0x0F120020,    // 700039D2
+	0x0F12327E,    // 700039D4
+	0x0F121F91,    // 700039D6
+	0x0F122303,    // 700039D8
+	0x0F12F000,    // 700039DA
+	0x0F12F9F3,    // 700039DC
+	0x0F120405,    // 700039DE
+	0x0F120C2D,    // 700039E0
+	0x0F124A23,    // 700039E2
+	0x0F120020,    // 700039E4
+	0x0F12325A,    // 700039E6
+	0x0F120011,    // 700039E8
+	0x0F12390A,    // 700039EA
+	0x0F122305,    // 700039EC
+	0x0F12F000,    // 700039EE
+	0x0F12F9E9,    // 700039F0
+	0x0F12491F,    // 700039F2
+	0x0F1264C8,    // 700039F4
+	0x0F12491F,    // 700039F6
+	0x0F124E21,    // 700039F8
+	0x0F1288C8,    // 700039FA
+	0x0F122701,    // 700039FC
+	0x0F122800,    // 700039FE
+	0x0F12D009,    // 70003A00
+	0x0F124C23,    // 70003A02
+	0x0F1238FF,    // 70003A04
+	0x0F121E40,    // 70003A06
+	0x0F12D00A,    // 70003A08
+	0x0F122804,    // 70003A0A
+	0x0F12D042,    // 70003A0C
+	0x0F122806,    // 70003A0E
+	0x0F12D101,    // 70003A10
+	0x0F122000,    // 70003A12
+	0x0F1280C8,    // 70003A14
+	0x0F1282B7,    // 70003A16
+	0x0F122001,    // 70003A18
+	0x0F12F000,    // 70003A1A
+	0x0F12F9EB,    // 70003A1C
+	0x0F12E6CB,    // 70003A1E
+	0x0F12000D,    // 70003A20
+	0x0F12724F,    // 70003A22
+	0x0F122001,    // 70003A24
+	0x0F12F000,    // 70003A26
+	0x0F12F9ED,    // 70003A28
+	0x0F12F000,    // 70003A2A
+	0x0F12F9F3,    // 70003A2C
+	0x0F124910,    // 70003A2E
+	0x0F123148,    // 70003A30
+	0x0F12C903,    // 70003A32
+	0x0F124348,    // 70003A34
+	0x0F120A00,    // 70003A36
+	0x0F126160,    // 70003A38
+	0x0F1220FF,    // 70003A3A
+	0x0F121D40,    // 70003A3C
+	0x0F1280E8,    // 70003A3E
+	0x0F12480C,    // 70003A40
+	0x0F123040,    // 70003A42
+	0x0F127707,    // 70003A44
+	0x0F12E7E6,    // 70003A46
+	0x0F123290,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F123294,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F1204A8,    // 70003A50
+	0x0F127000,    // 70003A52
+	0x0F1215DC,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F125000,    // 70003A58
+	0x0F12D000,    // 70003A5A
+	0x0F121E84,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F121BE4,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F122EA8,    // 70003A64
+	0x0F127000,    // 70003A66
+	0x0F1221A4,    // 70003A68
+	0x0F127000,    // 70003A6A
+	0x0F120100,    // 70003A6C
+	0x0F127000,    // 70003A6E
+	0x0F123F48,    // 70003A70
+	0x0F127000,    // 70003A72
+	0x0F1231A0,    // 70003A74
+	0x0F127000,    // 70003A76
+	0x0F1201E8,    // 70003A78
+	0x0F127000,    // 70003A7A
+	0x0F12F2A0,    // 70003A7C
+	0x0F12D000,    // 70003A7E
+	0x0F122A44,    // 70003A80
+	0x0F127000,    // 70003A82
+	0x0F12F400,    // 70003A84
+	0x0F12D000,    // 70003A86
+	0x0F122024,    // 70003A88
+	0x0F127000,    // 70003A8A
+	0x0F121650,    // 70003A8C
+	0x0F127000,    // 70003A8E
+	0x0F122A64,    // 70003A90
+	0x0F127000,    // 70003A92
+	0x0F12497B,    // 70003A94
+	0x0F12724F,    // 70003A96
+	0x0F1220FF,    // 70003A98
+	0x0F121DC0,    // 70003A9A
+	0x0F1280C8,    // 70003A9C
+	0x0F12F000,    // 70003A9E
+	0x0F12F9C1,    // 70003AA0
+	0x0F124979,    // 70003AA2
+	0x0F126ACA,    // 70003AA4
+	0x0F12604A,    // 70003AA6
+	0x0F122800,    // 70003AA8
+	0x0F12D006,    // 70003AAA
+	0x0F12436A,    // 70003AAC
+	0x0F120001,    // 70003AAE
+	0x0F120010,    // 70003AB0
+	0x0F12F000,    // 70003AB2
+	0x0F12F981,    // 70003AB4
+	0x0F126160,    // 70003AB6
+	0x0F12E001,    // 70003AB8
+	0x0F12436A,    // 70003ABA
+	0x0F126162,    // 70003ABC
+	0x0F128BF0,    // 70003ABE
+	0x0F122800,    // 70003AC0
+	0x0F12D001,    // 70003AC2
+	0x0F12F7FF,    // 70003AC4
+	0x0F12FF33,    // 70003AC6
+	0x0F122000,    // 70003AC8
+	0x0F12F000,    // 70003ACA
+	0x0F12F99B,    // 70003ACC
+	0x0F12496D,    // 70003ACE
+	0x0F1220FF,    // 70003AD0
+	0x0F121DC0,    // 70003AD2
+	0x0F1280C8,    // 70003AD4
+	0x0F12E79E,    // 70003AD6
+	0x0F12B570,    // 70003AD8
+	0x0F120004,    // 70003ADA
+	0x0F12F000,    // 70003ADC
+	0x0F12F9AA,    // 70003ADE
+	0x0F124D6A,    // 70003AE0
+	0x0F128C29,    // 70003AE2
+	0x0F121A40,    // 70003AE4
+	0x0F1242A0,    // 70003AE6
+	0x0F12D803,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F9A3,    // 70003AEC
+	0x0F128C29,    // 70003AEE
+	0x0F121A44,    // 70003AF0
+	0x0F120020,    // 70003AF2
+	0x0F12626C,    // 70003AF4
+	0x0F12F000,    // 70003AF6
+	0x0F12F9A5,    // 70003AF8
+	0x0F1262A8,    // 70003AFA
+	0x0F12F000,    // 70003AFC
+	0x0F12F9AA,    // 70003AFE
+	0x0F126328,    // 70003B00
+	0x0F128869,    // 70003B02
+	0x0F122900,    // 70003B04
+	0x0F12D000,    // 70003B06
+	0x0F1262A8,    // 70003B08
+	0x0F124861,    // 70003B0A
+	0x0F126B00,    // 70003B0C
+	0x0F128C00,    // 70003B0E
+	0x0F122800,    // 70003B10
+	0x0F12D117,    // 70003B12
+	0x0F126AA8,    // 70003B14
+	0x0F12F000,    // 70003B16
+	0x0F12F9A5,    // 70003B18
+	0x0F1261E8,    // 70003B1A
+	0x0F12495D,    // 70003B1C
+	0x0F128B8A,    // 70003B1E
+	0x0F122A00,    // 70003B20
+	0x0F12D00C,    // 70003B22
+	0x0F128BC9,    // 70003B24
+	0x0F124288,    // 70003B26
+	0x0F12D90A,    // 70003B28
+	0x0F12485A,    // 70003B2A
+	0x0F123020,    // 70003B2C
+	0x0F128800,    // 70003B2E
+	0x0F1261E8,    // 70003B30
+	0x0F128C29,    // 70003B32
+	0x0F121A40,    // 70003B34
+	0x0F1262A8,    // 70003B36
+	0x0F12F000,    // 70003B38
+	0x0F12F984,    // 70003B3A
+	0x0F1262A8,    // 70003B3C
+	0x0F12E593,    // 70003B3E
+	0x0F1261E9,    // 70003B40
+	0x0F12E591,    // 70003B42
+	0x0F12F000,    // 70003B44
+	0x0F12F976,    // 70003B46
+	0x0F1261E8,    // 70003B48
+	0x0F12E58D,    // 70003B4A
+	0x0F12B510,    // 70003B4C
+	0x0F12F000,    // 70003B4E
+	0x0F12F991,    // 70003B50
+	0x0F124850,    // 70003B52
+	0x0F123020,    // 70003B54
+	0x0F128841,    // 70003B56
+	0x0F122900,    // 70003B58
+	0x0F12D007,    // 70003B5A
+	0x0F124A4A,    // 70003B5C
+	0x0F123280,    // 70003B5E
+	0x0F126953,    // 70003B60
+	0x0F124A4D,    // 70003B62
+	0x0F12428B,    // 70003B64
+	0x0F12D202,    // 70003B66
+	0x0F128880,    // 70003B68
+	0x0F1281D0,    // 70003B6A
+	0x0F12E5C7,    // 70003B6C
+	0x0F1288C0,    // 70003B6E
+	0x0F1281D0,    // 70003B70
+	0x0F12E5C4,    // 70003B72
+	0x0F12B570,    // 70003B74
+	0x0F126800,    // 70003B76
+	0x0F120605,    // 70003B78
+	0x0F120E2D,    // 70003B7A
+	0x0F124C47,    // 70003B7C
+	0x0F128B60,    // 70003B7E
+	0x0F122800,    // 70003B80
+	0x0F12D010,    // 70003B82
+	0x0F124846,    // 70003B84
+	0x0F128A00,    // 70003B86
+	0x0F1206C0,    // 70003B88
+	0x0F12D50C,    // 70003B8A
+	0x0F124845,    // 70003B8C
+	0x0F127800,    // 70003B8E
+	0x0F122800,    // 70003B90
+	0x0F12D008,    // 70003B92
+	0x0F122000,    // 70003B94
+	0x0F12F000,    // 70003B96
+	0x0F12F975,    // 70003B98
+	0x0F128B20,    // 70003B9A
+	0x0F122201,    // 70003B9C
+	0x0F122180,    // 70003B9E
+	0x0F12F000,    // 70003BA0
+	0x0F12F978,    // 70003BA2
+	0x0F128320,    // 70003BA4
+	0x0F120028,    // 70003BA6
+	0x0F12F000,    // 70003BA8
+	0x0F12F97C,    // 70003BAA
+	0x0F12E55C,    // 70003BAC
+	0x0F12B570,    // 70003BAE
+	0x0F124A38,    // 70003BB0
+	0x0F124836,    // 70003BB2
+	0x0F123220,    // 70003BB4
+	0x0F128A91,    // 70003BB6
+	0x0F1269C0,    // 70003BB8
+	0x0F1226FF,    // 70003BBA
+	0x0F124D31,    // 70003BBC
+	0x0F121D76,    // 70003BBE
+	0x0F124288,    // 70003BC0
+	0x0F12D927,    // 70003BC2
+	0x0F1288E8,    // 70003BC4
+	0x0F1242B0,    // 70003BC6
+	0x0F12D024,    // 70003BC8
+	0x0F124837,    // 70003BCA
+	0x0F124937,    // 70003BCC
+	0x0F127883,    // 70003BCE
+	0x0F120008,    // 70003BD0
+	0x0F1230FF,    // 70003BD2
+	0x0F1231FF,    // 70003BD4
+	0x0F124C36,    // 70003BD6
+	0x0F1230E1,    // 70003BD8
+	0x0F1231C1,    // 70003BDA
+	0x0F128800,    // 70003BDC
+	0x0F128BC9,    // 70003BDE
+	0x0F1269A4,    // 70003BE0
+	0x0F122B00,    // 70003BE2
+	0x0F12D00B,    // 70003BE4
+	0x0F1289D2,    // 70003BE6
+	0x0F122A00,    // 70003BE8
+	0x0F12D013,    // 70003BEA
+	0x0F124350,    // 70003BEC
+	0x0F12F000,    // 70003BEE
+	0x0F12F8E3,    // 70003BF0
+	0x0F121C40,    // 70003BF2
+	0x0F120400,    // 70003BF4
+	0x0F120C00,    // 70003BF6
+	0x0F12F000,    // 70003BF8
+	0x0F12F95C,    // 70003BFA
+	0x0F12E00A,    // 70003BFC
+	0x0F128A12,    // 70003BFE
+	0x0F122A00,    // 70003C00
+	0x0F12D007,    // 70003C02
+	0x0F124350,    // 70003C04
+	0x0F12F000,    // 70003C06
+	0x0F12F8D7,    // 70003C08
+	0x0F121C40,    // 70003C0A
+	0x0F120400,    // 70003C0C
+	0x0F120C00,    // 70003C0E
+	0x0F12F000,    // 70003C10
+	0x0F12F950,    // 70003C12
+	0x0F12F000,    // 70003C14
+	0x0F12F956,    // 70003C16
+	0x0F1288E8,    // 70003C18
+	0x0F1242B0,    // 70003C1A
+	0x0F12D103,    // 70003C1C
+	0x0F124925,    // 70003C1E
+	0x0F1220FF,    // 70003C20
+	0x0F121C40,    // 70003C22
+	0x0F128048,    // 70003C24
+	0x0F12E51F,    // 70003C26
+	0x0F124770,    // 70003C28
+	0x0F12B570,    // 70003C2A
+	0x0F120005,    // 70003C2C
+	0x0F126828,    // 70003C2E
+	0x0F124E16,    // 70003C30
+	0x0F128C31,    // 70003C32
+	0x0F12180C,    // 70003C34
+	0x0F128871,    // 70003C36
+	0x0F122900,    // 70003C38
+	0x0F12D003,    // 70003C3A
+	0x0F120021,    // 70003C3C
+	0x0F12F000,    // 70003C3E
+	0x0F12F949,    // 70003C40
+	0x0F120004,    // 70003C42
+	0x0F124812,    // 70003C44
+	0x0F126976,    // 70003C46
+	0x0F126B00,    // 70003C48
+	0x0F126B40,    // 70003C4A
+	0x0F124286,    // 70003C4C
+	0x0F12D800,    // 70003C4E
+	0x0F120006,    // 70003C50
+	0x0F122101,    // 70003C52
+	0x0F120030,    // 70003C54
+	0x0F12F000,    // 70003C56
+	0x0F12F945,    // 70003C58
+	0x0F120001,    // 70003C5A
+	0x0F12480D,    // 70003C5C
+	0x0F123020,    // 70003C5E
+	0x0F128A40,    // 70003C60
+	0x0F122800,    // 70003C62
+	0x0F12D005,    // 70003C64
+	0x0F120020,    // 70003C66
+	0x0F12428C,    // 70003C68
+	0x0F12D800,    // 70003C6A
+	0x0F120008,    // 70003C6C
+	0x0F126028,    // 70003C6E
+	0x0F12E4FA,    // 70003C70
+	0x0F120020,    // 70003C72
+	0x0F1242B4,    // 70003C74
+	0x0F12D800,    // 70003C76
+	0x0F120030,    // 70003C78
+	0x0F122101,    // 70003C7A
+	0x0F12F000,    // 70003C7C
+	0x0F12F932,    // 70003C7E
+	0x0F126028,    // 70003C80
+	0x0F12E4F1,    // 70003C82
+	0x0F1231A0,    // 70003C84
+	0x0F127000,    // 70003C86
+	0x0F1229E4,    // 70003C88
+	0x0F127000,    // 70003C8A
+	0x0F121E3C,    // 70003C8C
+	0x0F127000,    // 70003C8E
+	0x0F1221A4,    // 70003C90
+	0x0F127000,    // 70003C92
+	0x0F123FC8,    // 70003C94
+	0x0F127000,    // 70003C96
+	0x0F12E200,    // 70003C98
+	0x0F12D000,    // 70003C9A
+	0x0F122EA8,    // 70003C9C
+	0x0F127000,    // 70003C9E
+	0x0F12B040,    // 70003CA0
+	0x0F12D000,    // 70003CA2
+	0x0F12323C,    // 70003CA4
+	0x0F127000,    // 70003CA6
+	0x0F121E84,    // 70003CA8
+	0x0F127000,    // 70003CAA
+	0x0F122024,    // 70003CAC
+	0x0F127000,    // 70003CAE
+	0x0F120080,    // 70003CB0
+	0x0F127000,    // 70003CB2
+	0x0F12C100,    // 70003CB4
+	0x0F12D000,    // 70003CB6
+	0x0F124778,    // 70003CB8
+	0x0F1246C0,    // 70003CBA
+	0x0F12C000,    // 70003CBC
+	0x0F12E59F,    // 70003CBE
+	0x0F12FF1C,    // 70003CC0
+	0x0F12E12F,    // 70003CC2
+	0x0F121F63,    // 70003CC4
+	0x0F120001,    // 70003CC6
+	0x0F124778,    // 70003CC8
+	0x0F1246C0,    // 70003CCA
+	0x0F12C000,    // 70003CCC
+	0x0F12E59F,    // 70003CCE
+	0x0F12FF1C,    // 70003CD0
+	0x0F12E12F,    // 70003CD2
+	0x0F121EDF,    // 70003CD4
+	0x0F120001,    // 70003CD6
+	0x0F124778,    // 70003CD8
+	0x0F1246C0,    // 70003CDA
+	0x0F12C000,    // 70003CDC
+	0x0F12E59F,    // 70003CDE
+	0x0F12FF1C,    // 70003CE0
+	0x0F12E12F,    // 70003CE2
+	0x0F12495F,    // 70003CE4
+	0x0F120000,    // 70003CE6
+	0x0F124778,    // 70003CE8
+	0x0F1246C0,    // 70003CEA
+	0x0F12C000,    // 70003CEC
+	0x0F12E59F,    // 70003CEE
+	0x0F12FF1C,    // 70003CF0
+	0x0F12E12F,    // 70003CF2
+	0x0F12E403,    // 70003CF4
+	0x0F120000,    // 70003CF6
+	0x0F124778,    // 70003CF8
+	0x0F1246C0,    // 70003CFA
+	0x0F12C000,    // 70003CFC
+	0x0F12E59F,    // 70003CFE
+	0x0F12FF1C,    // 70003D00
+	0x0F12E12F,    // 70003D02
+	0x0F1224B3,    // 70003D04
+	0x0F120001,    // 70003D06
+	0x0F124778,    // 70003D08
+	0x0F1246C0,    // 70003D0A
+	0x0F12C000,    // 70003D0C
+	0x0F12E59F,    // 70003D0E
+	0x0F12FF1C,    // 70003D10
+	0x0F12E12F,    // 70003D12
+	0x0F12EECD,    // 70003D14
+	0x0F120000,    // 70003D16
+	0x0F124778,    // 70003D18
+	0x0F1246C0,    // 70003D1A
+	0x0F12C000,    // 70003D1C
+	0x0F12E59F,    // 70003D1E
+	0x0F12FF1C,    // 70003D20
+	0x0F12E12F,    // 70003D22
+	0x0F12F049,    // 70003D24
+	0x0F120000,    // 70003D26
+	0x0F124778,    // 70003D28
+	0x0F1246C0,    // 70003D2A
+	0x0F12C000,    // 70003D2C
+	0x0F12E59F,    // 70003D2E
+	0x0F12FF1C,    // 70003D30
+	0x0F12E12F,    // 70003D32
+	0x0F1212DF,    // 70003D34
+	0x0F120000,    // 70003D36
+	0x0F124778,    // 70003D38
+	0x0F1246C0,    // 70003D3A
+	0x0F12C000,    // 70003D3C
+	0x0F12E59F,    // 70003D3E
+	0x0F12FF1C,    // 70003D40
+	0x0F12E12F,    // 70003D42
+	0x0F12F05B,    // 70003D44
+	0x0F120000,    // 70003D46
+	0x0F124778,    // 70003D48
+	0x0F1246C0,    // 70003D4A
+	0x0F12C000,    // 70003D4C
+	0x0F12E59F,    // 70003D4E
+	0x0F12FF1C,    // 70003D50
+	0x0F12E12F,    // 70003D52
+	0x0F12F07B,    // 70003D54
+	0x0F120000,    // 70003D56
+	0x0F124778,    // 70003D58
+	0x0F1246C0,    // 70003D5A
+	0x0F12C000,    // 70003D5C
+	0x0F12E59F,    // 70003D5E
+	0x0F12FF1C,    // 70003D60
+	0x0F12E12F,    // 70003D62
+	0x0F12FE6D,    // 70003D64
+	0x0F120000,    // 70003D66
+	0x0F124778,    // 70003D68
+	0x0F1246C0,    // 70003D6A
+	0x0F12C000,    // 70003D6C
+	0x0F12E59F,    // 70003D6E
+	0x0F12FF1C,    // 70003D70
+	0x0F12E12F,    // 70003D72
+	0x0F123295,    // 70003D74
+	0x0F120000,    // 70003D76
+	0x0F124778,    // 70003D78
+	0x0F1246C0,    // 70003D7A
+	0x0F12C000,    // 70003D7C
+	0x0F12E59F,    // 70003D7E
+	0x0F12FF1C,    // 70003D80
+	0x0F12E12F,    // 70003D82
+	0x0F12234F,    // 70003D84
+	0x0F120000,    // 70003D86
+	0x0F124778,    // 70003D88
+	0x0F1246C0,    // 70003D8A
+	0x0F12C000,    // 70003D8C
+	0x0F12E59F,    // 70003D8E
+	0x0F12FF1C,    // 70003D90
+	0x0F12E12F,    // 70003D92
+	0x0F124521,    // 70003D94
+	0x0F120000,    // 70003D96
+	0x0F124778,    // 70003D98
+	0x0F1246C0,    // 70003D9A
+	0x0F12C000,    // 70003D9C
+	0x0F12E59F,    // 70003D9E
+	0x0F12FF1C,    // 70003DA0
+	0x0F12E12F,    // 70003DA2
+	0x0F127C0D,    // 70003DA4
+	0x0F120000,    // 70003DA6
+	0x0F124778,    // 70003DA8
+	0x0F1246C0,    // 70003DAA
+	0x0F12C000,    // 70003DAC
+	0x0F12E59F,    // 70003DAE
+	0x0F12FF1C,    // 70003DB0
+	0x0F12E12F,    // 70003DB2
+	0x0F127C2B,    // 70003DB4
+	0x0F120000,    // 70003DB6
+	0x0F124778,    // 70003DB8
+	0x0F1246C0,    // 70003DBA
+	0x0F12F004,    // 70003DBC
+	0x0F12E51F,    // 70003DBE
+	0x0F1224C4,    // 70003DC0
+	0x0F120001,    // 70003DC2
+	0x0F124778,    // 70003DC4
+	0x0F1246C0,    // 70003DC6
+	0x0F12C000,    // 70003DC8
+	0x0F12E59F,    // 70003DCA
+	0x0F12FF1C,    // 70003DCC
+	0x0F12E12F,    // 70003DCE
+	0x0F123183,    // 70003DD0
+	0x0F120000,    // 70003DD2
+	0x0F124778,    // 70003DD4
+	0x0F1246C0,    // 70003DD6
+	0x0F12C000,    // 70003DD8
+	0x0F12E59F,    // 70003DDA
+	0x0F12FF1C,    // 70003DDC
+	0x0F12E12F,    // 70003DDE
+	0x0F12302F,    // 70003DE0
+	0x0F120000,    // 70003DE2
+	0x0F124778,    // 70003DE4
+	0x0F1246C0,    // 70003DE6
+	0x0F12C000,    // 70003DE8
+	0x0F12E59F,    // 70003DEA
+	0x0F12FF1C,    // 70003DEC
+	0x0F12E12F,    // 70003DEE
+	0x0F12EF07,    // 70003DF0
+	0x0F120000,    // 70003DF2
+	0x0F124778,    // 70003DF4
+	0x0F1246C0,    // 70003DF6
+	0x0F12C000,    // 70003DF8
+	0x0F12E59F,    // 70003DFA
+	0x0F12FF1C,    // 70003DFC
+	0x0F12E12F,    // 70003DFE
+	0x0F1248FB,    // 70003E00
+	0x0F120000,    // 70003E02
+	0x0F124778,    // 70003E04
+	0x0F1246C0,    // 70003E06
+	0x0F12C000,    // 70003E08
+	0x0F12E59F,    // 70003E0A
+	0x0F12FF1C,    // 70003E0C
+	0x0F12E12F,    // 70003E0E
+	0x0F12F0B1,    // 70003E10
+	0x0F120000,    // 70003E12
+	0x0F124778,    // 70003E14
+	0x0F1246C0,    // 70003E16
+	0x0F12C000,    // 70003E18
+	0x0F12E59F,    // 70003E1A
+	0x0F12FF1C,    // 70003E1C
+	0x0F12E12F,    // 70003E1E
+	0x0F12EEDF,    // 70003E20
+	0x0F120000,    // 70003E22
+	0x0F124778,    // 70003E24
+	0x0F1246C0,    // 70003E26
+	0x0F12C000,    // 70003E28
+	0x0F12E59F,    // 70003E2A
+	0x0F12FF1C,    // 70003E2C
+	0x0F12E12F,    // 70003E2E
+	0x0F12AEF1,    // 70003E30
+	0x0F120000,    // 70003E32
+	0x0F124778,    // 70003E34
+	0x0F1246C0,    // 70003E36
+	0x0F12C000,    // 70003E38
+	0x0F12E59F,    // 70003E3A
+	0x0F12FF1C,    // 70003E3C
+	0x0F12E12F,    // 70003E3E
+	0x0F1239DF,    // 70003E40
+	0x0F120000,    // 70003E42
+	0x0F124778,    // 70003E44
+	0x0F1246C0,    // 70003E46
+	0x0F12C000,    // 70003E48
+	0x0F12E59F,    // 70003E4A
+	0x0F12FF1C,    // 70003E4C
+	0x0F12E12F,    // 70003E4E
+	0x0F126177,    // 70003E50
+	0x0F120000,    // 70003E52
+	0x0F124778,    // 70003E54
+	0x0F1246C0,    // 70003E56
+	0x0F12C000,    // 70003E58
+	0x0F12E59F,    // 70003E5A
+	0x0F12FF1C,    // 70003E5C
+	0x0F12E12F,    // 70003E5E
+	0x0F12424F,    // 70003E60
+	0x0F120000,    // 70003E62
+	0x0F124778,    // 70003E64
+	0x0F1246C0,    // 70003E66
+	0x0F12C000,    // 70003E68
+	0x0F12E59F,    // 70003E6A
+	0x0F12FF1C,    // 70003E6C
+	0x0F12E12F,    // 70003E6E
+	0x0F123F0D,    // 70003E70
+	0x0F120000,    // 70003E72
+	0x0F124778,    // 70003E74
+	0x0F1246C0,    // 70003E76
+	0x0F12C000,    // 70003E78
+	0x0F12E59F,    // 70003E7A
+	0x0F12FF1C,    // 70003E7C
+	0x0F12E12F,    // 70003E7E
+	0x0F1202B9,    // 70003E80
+	0x0F120001,    // 70003E82
+	0x0F124778,    // 70003E84
+	0x0F1246C0,    // 70003E86
+	0x0F12C000,    // 70003E88
+	0x0F12E59F,    // 70003E8A
+	0x0F12FF1C,    // 70003E8C
+	0x0F12E12F,    // 70003E8E
+	0x0F12FE45,    // 70003E90
+	0x0F120000,    // 70003E92
+	0x0F124778,    // 70003E94
+	0x0F1246C0,    // 70003E96
+	0x0F12C000,    // 70003E98
+	0x0F12E59F,    // 70003E9A
+	0x0F12FF1C,    // 70003E9C
+	0x0F12E12F,    // 70003E9E
+	0x0F1232A7,    // 70003EA0
+	0x0F120000,    // 70003EA2
+	0x0F124778,    // 70003EA4
+	0x0F1246C0,    // 70003EA6
+	0x0F12C000,    // 70003EA8
+	0x0F12E59F,    // 70003EAA
+	0x0F12FF1C,    // 70003EAC
+	0x0F12E12F,    // 70003EAE
+	0x0F12E8AD,    // 70003EB0
+	0x0F120000,    // 70003EB2
+	0x0F124778,    // 70003EB4
+	0x0F1246C0,    // 70003EB6
+	0x0F12C000,    // 70003EB8
+	0x0F12E59F,    // 70003EBA
+	0x0F12FF1C,    // 70003EBC
+	0x0F12E12F,    // 70003EBE
+	0x0F1224B9,    // 70003EC0
+	0x0F120001,    // 70003EC2
+	0x0F124778,    // 70003EC4
+	0x0F1246C0,    // 70003EC6
+	0x0F12C000,    // 70003EC8
+	0x0F12E59F,    // 70003ECA
+	0x0F12FF1C,    // 70003ECC
+	0x0F12E12F,    // 70003ECE
+	0x0F1202EB,    // 70003ED0
+	0x0F120001,    // 70003ED2
+	0x0F124778,    // 70003ED4
+	0x0F1246C0,    // 70003ED6
+	0x0F12C000,    // 70003ED8
+	0x0F12E59F,    // 70003EDA
+	0x0F12FF1C,    // 70003EDC
+	0x0F12E12F,    // 70003EDE
+	0x0F123EC9,    // 70003EE0
+	0x0F120000,    // 70003EE2
+	0x0F124778,    // 70003EE4
+	0x0F1246C0,    // 70003EE6
+	0x0F12C000,    // 70003EE8
+	0x0F12E59F,    // 70003EEA
+	0x0F12FF1C,    // 70003EEC
+	0x0F12E12F,    // 70003EEE
+	0x0F126123,    // 70003EF0
+	0x0F120000,    // 70003EF2
+	// End of Patch Data(Last : 70003EF2h)
+	// Total Size 2504 (0x09C8)
+	// Addr : 352C , Size : 2502(9C6h)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	// 	TNP_GAS_ALPHA_OTP
+	// 	TNP_FR_ACCURATE_DYNAMIC
+	// 	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F120035,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F12024C,	//22//28//2D//30//35,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12021E,	//45//3C//37//33//AA, // 0517 test 027A, // 025A, // 0517 test 024A,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// Analog & APS settings         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// This register is for FACTORY ONLY. If you change it without prior notification         //
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //         //         //         //         //         //
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	// 0810 added - Start
+	0x002AF462,
+	0x0F120001, // atx_option add 0725
+
+	0x002AF2A5,
+	0x0F1201FF, // atx_width  add 0725
+	// 0810 added - End
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120050,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0004                  //extend Forbidden area line
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120400, //REG_0TC_PCFG_usWidth
+	0x0F120300, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+	0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#else
+	0x0F120000, //REG_0TC_PCFG_uPrevMirror
+	0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120005,                   //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// Capture 1 640x480 system 52M PCLK 87M
+	//===================================================================
+	0x002A035A,
+	0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+	0x0F120280,                   //REG_1TC_CCFG_usWidth
+	0x0F1201E0,                   //REG_1TC_CCFG_usHeight
+	0x0F120005,                   //REG_1TC_CCFG_Format
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+	0x002A036A,
+	0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29
+	0x0F120010,                   //REG_1TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+	0x002A0372,
+	0x0F120001,                   //REG_1TC_CCFG_uClockInd
+	0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+	0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_1TC_CCFG_sSaturation
+	0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+
+	// 0613
+	0x0F123400, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123400, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123400, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123400, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123400, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123400, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F124000,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F124000,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120840, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+
+	};
+#else
+/* Init regs for Jpeg capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	0x002A352C,
+	0x0F12B5F8,    // 7000352C
+	0x0F124A28,    // 7000352E
+	0x0F124928,    // 70003530
+	0x0F124829,    // 70003532
+	0x0F124B29,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124928,    // 7000353E
+	0x0F124828,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FBB9,    // 70003544
+	0x0F124928,    // 70003546
+	0x0F124828,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FBB5,    // 7000354C
+	0x0F124828,    // 7000354E
+	0x0F124E28,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124928,    // 70003554
+	0x0F124829,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FBAE,    // 7000355A
+	0x0F124828,    // 7000355C
+	0x0F120037,    // 7000355E
+	0x0F123780,    // 70003560
+	0x0F126178,    // 70003562
+	0x0F124C27,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124927,    // 70003568
+	0x0F124828,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FBA4,    // 7000356E
+	0x0F124927,    // 70003570
+	0x0F124828,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FBA0,    // 70003576
+	0x0F124927,    // 70003578
+	0x0F124828,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FB9C,    // 7000357E
+	0x0F124927,    // 70003580
+	0x0F124828,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB98,    // 70003586
+	0x0F1283A5,    // 70003588
+	0x0F124827,    // 7000358A
+	0x0F126470,    // 7000358C
+	0x0F122001,    // 7000358E
+	0x0F120340,    // 70003590
+	0x0F123420,    // 70003592
+	0x0F128060,    // 70003594
+	0x0F122085,    // 70003596
+	0x0F1280A0,    // 70003598
+	0x0F124824,    // 7000359A
+	0x0F1280E0,    // 7000359C
+	0x0F124824,    // 7000359E
+	0x0F126730,    // 700035A0
+	0x0F124924,    // 700035A2
+	0x0F124824,    // 700035A4
+	0x0F12F000,    // 700035A6
+	0x0F12FB87,    // 700035A8
+	0x0F1281E5,    // 700035AA
+	0x0F128225,    // 700035AC
+	0x0F124823,    // 700035AE
+	0x0F1282A0,    // 700035B0
+	0x0F124813,    // 700035B2
+	0x0F126178,    // 700035B4
+	0x0F122001,    // 700035B6
+	0x0F128260,    // 700035B8
+	0x0F124921,    // 700035BA
+	0x0F124821,    // 700035BC
+	0x0F12F000,    // 700035BE
+	0x0F12FB7B,    // 700035C0
+	0x0F124921,    // 700035C2
+	0x0F124821,    // 700035C4
+	0x0F12F000,    // 700035C6
+	0x0F12FB77,    // 700035C8
+	0x0F12BCF8,    // 700035CA
+	0x0F12BC08,    // 700035CC
+	0x0F124718,    // 700035CE
+	0x0F1200D6,    // 700035D0
+	0x0F125CC1,    // 700035D2
+	0x0F12633D,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F121C08,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F123290,    // 700035DC
+	0x0F127000,    // 700035DE
+	0x0F12366F,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F12D9E7,    // 700035E4
+	0x0F120000,    // 700035E6
+	0x0F123857,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F12395D,    // 700035EC
+	0x0F120000,    // 700035EE
+	0x0F1238E9,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F120000,    // 700035F4
+	0x0F127000,    // 700035F6
+	0x0F1239B5,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12F903,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F123BAF,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F123FC8,    // 70003604
+	0x0F127000,    // 70003606
+	0x0F1236A7,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F12495F,    // 7000360C
+	0x0F120000,    // 7000360E
+	0x0F123705,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F12E421,    // 70003614
+	0x0F120000,    // 70003616
+	0x0F1237C3,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F12216D,    // 7000361C
+	0x0F120000,    // 7000361E
+	0x0F123837,    // 70003620
+	0x0F127000,    // 70003622
+	0x0F120179,    // 70003624
+	0x0F120001,    // 70003626
+	0x0F123AD9,    // 70003628
+	0x0F127000,    // 7000362A
+	0x0F1207FF,    // 7000362C
+	0x0F120000,    // 7000362E
+	0x0F123B4D,    // 70003630
+	0x0F127000,    // 70003632
+	0x0F123B75,    // 70003634
+	0x0F127000,    // 70003636
+	0x0F12E8AD,    // 70003638
+	0x0F120000,    // 7000363A
+	0x0F124E20,    // 7000363C
+	0x0F120000,    // 7000363E
+	0x0F123C29,    // 70003640
+	0x0F127000,    // 70003642
+	0x0F123C4D,    // 70003644
+	0x0F120000,    // 70003646
+	0x0F123C2B,    // 70003648
+	0x0F127000,    // 7000364A
+	0x0F123F0D,    // 7000364C
+	0x0F120000,    // 7000364E
+	0x0F12B570,    // 70003650
+	0x0F12000D,    // 70003652
+	0x0F124CFC,    // 70003654
+	0x0F128821,    // 70003656
+	0x0F12F000,    // 70003658
+	0x0F12FB36,    // 7000365A
+	0x0F128820,    // 7000365C
+	0x0F124AFB,    // 7000365E
+	0x0F120081,    // 70003660
+	0x0F125055,    // 70003662
+	0x0F121C40,    // 70003664
+	0x0F128020,    // 70003666
+	0x0F12BC70,    // 70003668
+	0x0F12BC08,    // 7000366A
+	0x0F124718,    // 7000366C
+	0x0F126801,    // 7000366E
+	0x0F120409,    // 70003670
+	0x0F120C09,    // 70003672
+	0x0F126840,    // 70003674
+	0x0F120400,    // 70003676
+	0x0F120C00,    // 70003678
+	0x0F124AF5,    // 7000367A
+	0x0F128992,    // 7000367C
+	0x0F122A00,    // 7000367E
+	0x0F12D00D,    // 70003680
+	0x0F122300,    // 70003682
+	0x0F121A80,    // 70003684
+	0x0F12D400,    // 70003686
+	0x0F120003,    // 70003688
+	0x0F120418,    // 7000368A
+	0x0F120C00,    // 7000368C
+	0x0F124BF1,    // 7000368E
+	0x0F121851,    // 70003690
+	0x0F12891B,    // 70003692
+	0x0F12428B,    // 70003694
+	0x0F12D300,    // 70003696
+	0x0F12000B,    // 70003698
+	0x0F120419,    // 7000369A
+	0x0F120C09,    // 7000369C
+	0x0F124AEE,    // 7000369E
+	0x0F128151,    // 700036A0
+	0x0F128190,    // 700036A2
+	0x0F124770,    // 700036A4
+	0x0F12B510,    // 700036A6
+	0x0F124CEC,    // 700036A8
+	0x0F1248ED,    // 700036AA
+	0x0F1278A1,    // 700036AC
+	0x0F122900,    // 700036AE
+	0x0F12D101,    // 700036B0
+	0x0F1287C1,    // 700036B2
+	0x0F12E004,    // 700036B4
+	0x0F127AE1,    // 700036B6
+	0x0F122900,    // 700036B8
+	0x0F12D001,    // 700036BA
+	0x0F122101,    // 700036BC
+	0x0F1287C1,    // 700036BE
+	0x0F12F000,    // 700036C0
+	0x0F12FB0A,    // 700036C2
+	0x0F1249E7,    // 700036C4
+	0x0F128B08,    // 700036C6
+	0x0F1206C2,    // 700036C8
+	0x0F12D50A,    // 700036CA
+	0x0F127AA2,    // 700036CC
+	0x0F120652,    // 700036CE
+	0x0F12D507,    // 700036D0
+	0x0F122210,    // 700036D2
+	0x0F124390,    // 700036D4
+	0x0F128308,    // 700036D6
+	0x0F1248E3,    // 700036D8
+	0x0F127AE1,    // 700036DA
+	0x0F126B00,    // 700036DC
+	0x0F12F000,    // 700036DE
+	0x0F12FB03,    // 700036E0
+	0x0F1248DB,    // 700036E2
+	0x0F1289C0,    // 700036E4
+	0x0F122801,    // 700036E6
+	0x0F12D109,    // 700036E8
+	0x0F1278A0,    // 700036EA
+	0x0F122800,    // 700036EC
+	0x0F12D006,    // 700036EE
+	0x0F127AE0,    // 700036F0
+	0x0F122800,    // 700036F2
+	0x0F12D003,    // 700036F4
+	0x0F127AA0,    // 700036F6
+	0x0F122140,    // 700036F8
+	0x0F124308,    // 700036FA
+	0x0F1272A0,    // 700036FC
+	0x0F12BC10,    // 700036FE
+	0x0F12BC08,    // 70003700
+	0x0F124718,    // 70003702
+	0x0F12B570,    // 70003704
+	0x0F124DD7,    // 70003706
+	0x0F124CD7,    // 70003708
+	0x0F128B28,    // 7000370A
+	0x0F120701,    // 7000370C
+	0x0F12D507,    // 7000370E
+	0x0F122108,    // 70003710
+	0x0F124388,    // 70003712
+	0x0F128328,    // 70003714
+	0x0F1249D5,    // 70003716
+	0x0F126B20,    // 70003718
+	0x0F126B89,    // 7000371A
+	0x0F12F000,    // 7000371C
+	0x0F12FAEC,    // 7000371E
+	0x0F128B28,    // 70003720
+	0x0F1206C1,    // 70003722
+	0x0F12D5A0,    // 70003724
+	0x0F1249CD,    // 70003726
+	0x0F127A8A,    // 70003728
+	0x0F120652,    // 7000372A
+	0x0F12D49C,    // 7000372C
+	0x0F122210,    // 7000372E
+	0x0F124390,    // 70003730
+	0x0F128328,    // 70003732
+	0x0F127AC9,    // 70003734
+	0x0F126B20,    // 70003736
+	0x0F12F000,    // 70003738
+	0x0F12FAD6,    // 7000373A
+	0x0F12E794,    // 7000373C
+	0x0F12B5F8,    // 7000373E
+	0x0F1249CB,    // 70003740
+	0x0F128F08,    // 70003742
+	0x0F12000C,    // 70003744
+	0x0F123480,    // 70003746
+	0x0F122800,    // 70003748
+	0x0F12D000,    // 7000374A
+	0x0F128360,    // 7000374C
+	0x0F122000,    // 7000374E
+	0x0F128708,    // 70003750
+	0x0F124DC8,    // 70003752
+	0x0F1226FF,    // 70003754
+	0x0F128828,    // 70003756
+	0x0F121C76,    // 70003758
+	0x0F122702,    // 7000375A
+	0x0F122803,    // 7000375C
+	0x0F12D112,    // 7000375E
+	0x0F128868,    // 70003760
+	0x0F122800,    // 70003762
+	0x0F12D10F,    // 70003764
+	0x0F1288E8,    // 70003766
+	0x0F122800,    // 70003768
+	0x0F12D10C,    // 7000376A
+	0x0F12F000,    // 7000376C
+	0x0F12FACC,    // 7000376E
+	0x0F122800,    // 70003770
+	0x0F12D008,    // 70003772
+	0x0F128B60,    // 70003774
+	0x0F122800,    // 70003776
+	0x0F12D001,    // 70003778
+	0x0F1280EE,    // 7000377A
+	0x0F1280AF,    // 7000377C
+	0x0F122001,    // 7000377E
+	0x0F127268,    // 70003780
+	0x0F12F000,    // 70003782
+	0x0F12FAC9,    // 70003784
+	0x0F128828,    // 70003786
+	0x0F122802,    // 70003788
+	0x0F12D10E,    // 7000378A
+	0x0F128868,    // 7000378C
+	0x0F122800,    // 7000378E
+	0x0F12D10B,    // 70003790
+	0x0F1288E8,    // 70003792
+	0x0F122800,    // 70003794
+	0x0F12D108,    // 70003796
+	0x0F128B60,    // 70003798
+	0x0F122800,    // 7000379A
+	0x0F12D001,    // 7000379C
+	0x0F1280EE,    // 7000379E
+	0x0F1280AF,    // 700037A0
+	0x0F122001,    // 700037A2
+	0x0F127268,    // 700037A4
+	0x0F12F000,    // 700037A6
+	0x0F12FAB7,    // 700037A8
+	0x0F1288E8,    // 700037AA
+	0x0F122800,    // 700037AC
+	0x0F12D006,    // 700037AE
+	0x0F121FC1,    // 700037B0
+	0x0F1239FD,    // 700037B2
+	0x0F12D003,    // 700037B4
+	0x0F122001,    // 700037B6
+	0x0F12BCF8,    // 700037B8
+	0x0F12BC08,    // 700037BA
+	0x0F124718,    // 700037BC
+	0x0F122000,    // 700037BE
+	0x0F12E7FA,    // 700037C0
+	0x0F12B570,    // 700037C2
+	0x0F124CAC,    // 700037C4
+	0x0F128860,    // 700037C6
+	0x0F122800,    // 700037C8
+	0x0F12D00C,    // 700037CA
+	0x0F128820,    // 700037CC
+	0x0F124DA3,    // 700037CE
+	0x0F122800,    // 700037D0
+	0x0F12D009,    // 700037D2
+	0x0F120029,    // 700037D4
+	0x0F1231A0,    // 700037D6
+	0x0F127AC9,    // 700037D8
+	0x0F122900,    // 700037DA
+	0x0F12D004,    // 700037DC
+	0x0F127AA8,    // 700037DE
+	0x0F122180,    // 700037E0
+	0x0F124308,    // 700037E2
+	0x0F1272A8,    // 700037E4
+	0x0F12E73F,    // 700037E6
+	0x0F122800,    // 700037E8
+	0x0F12D003,    // 700037EA
+	0x0F12F7FF,    // 700037EC
+	0x0F12FFA7,    // 700037EE
+	0x0F122800,    // 700037F0
+	0x0F12D1F8,    // 700037F2
+	0x0F122000,    // 700037F4
+	0x0F128060,    // 700037F6
+	0x0F128820,    // 700037F8
+	0x0F122800,    // 700037FA
+	0x0F12D003,    // 700037FC
+	0x0F122008,    // 700037FE
+	0x0F12F000,    // 70003800
+	0x0F12FA92,    // 70003802
+	0x0F12E00B,    // 70003804
+	0x0F12489C,    // 70003806
+	0x0F123020,    // 70003808
+	0x0F128880,    // 7000380A
+	0x0F122800,    // 7000380C
+	0x0F12D103,    // 7000380E
+	0x0F127AA8,    // 70003810
+	0x0F122101,    // 70003812
+	0x0F124308,    // 70003814
+	0x0F1272A8,    // 70003816
+	0x0F122010,    // 70003818
+	0x0F12F000,    // 7000381A
+	0x0F12FA85,    // 7000381C
+	0x0F128820,    // 7000381E
+	0x0F122800,    // 70003820
+	0x0F12D1E0,    // 70003822
+	0x0F12488A,    // 70003824
+	0x0F1289C0,    // 70003826
+	0x0F122801,    // 70003828
+	0x0F12D1DC,    // 7000382A
+	0x0F127AA8,    // 7000382C
+	0x0F1221BF,    // 7000382E
+	0x0F124008,    // 70003830
+	0x0F1272A8,    // 70003832
+	0x0F12E718,    // 70003834
+	0x0F126800,    // 70003836
+	0x0F124990,    // 70003838
+	0x0F128188,    // 7000383A
+	0x0F124890,    // 7000383C
+	0x0F122201,    // 7000383E
+	0x0F128981,    // 70003840
+	0x0F124890,    // 70003842
+	0x0F120252,    // 70003844
+	0x0F124291,    // 70003846
+	0x0F12D902,    // 70003848
+	0x0F122102,    // 7000384A
+	0x0F128181,    // 7000384C
+	0x0F124770,    // 7000384E
+	0x0F122101,    // 70003850
+	0x0F128181,    // 70003852
+	0x0F124770,    // 70003854
+	0x0F12B5F1,    // 70003856
+	0x0F124E80,    // 70003858
+	0x0F128834,    // 7000385A
+	0x0F122C00,    // 7000385C
+	0x0F12D03F,    // 7000385E
+	0x0F122001,    // 70003860
+	0x0F122C08,    // 70003862
+	0x0F12D000,    // 70003864
+	0x0F122000,    // 70003866
+	0x0F1270B0,    // 70003868
+	0x0F124D7F,    // 7000386A
+	0x0F122800,    // 7000386C
+	0x0F12D009,    // 7000386E
+	0x0F12F000,    // 70003870
+	0x0F12FA62,    // 70003872
+	0x0F120028,    // 70003874
+	0x0F1238F0,    // 70003876
+	0x0F126328,    // 70003878
+	0x0F127AB0,    // 7000387A
+	0x0F12217E,    // 7000387C
+	0x0F124008,    // 7000387E
+	0x0F1272B0,    // 70003880
+	0x0F12E00F,    // 70003882
+	0x0F124F7A,    // 70003884
+	0x0F123780,    // 70003886
+	0x0F128B78,    // 70003888
+	0x0F122800,    // 7000388A
+	0x0F12D005,    // 7000388C
+	0x0F12F000,    // 7000388E
+	0x0F12FA5B,    // 70003890
+	0x0F122000,    // 70003892
+	0x0F128378,    // 70003894
+	0x0F124976,    // 70003896
+	0x0F128708,    // 70003898
+	0x0F122000,    // 7000389A
+	0x0F12F000,    // 7000389C
+	0x0F12FA5C,    // 7000389E
+	0x0F124879,    // 700038A0
+	0x0F126328,    // 700038A2
+	0x0F1278B1,    // 700038A4
+	0x0F122700,    // 700038A6
+	0x0F120038,    // 700038A8
+	0x0F122900,    // 700038AA
+	0x0F12D008,    // 700038AC
+	0x0F124972,    // 700038AE
+	0x0F123920,    // 700038B0
+	0x0F128ACA,    // 700038B2
+	0x0F122A00,    // 700038B4
+	0x0F12D003,    // 700038B6
+	0x0F128B09,    // 700038B8
+	0x0F122900,    // 700038BA
+	0x0F12D000,    // 700038BC
+	0x0F122001,    // 700038BE
+	0x0F127170,    // 700038C0
+	0x0F122C02,    // 700038C2
+	0x0F12D102,    // 700038C4
+	0x0F124868,    // 700038C6
+	0x0F123860,    // 700038C8
+	0x0F126328,    // 700038CA
+	0x0F122201,    // 700038CC
+	0x0F122C02,    // 700038CE
+	0x0F12D000,    // 700038D0
+	0x0F122200,    // 700038D2
+	0x0F124861,    // 700038D4
+	0x0F122110,    // 700038D6
+	0x0F12300A,    // 700038D8
+	0x0F12F000,    // 700038DA
+	0x0F12FA45,    // 700038DC
+	0x0F128037,    // 700038DE
+	0x0F129900,    // 700038E0
+	0x0F120020,    // 700038E2
+	0x0F12600C,    // 700038E4
+	0x0F12E767,    // 700038E6
+	0x0F12B538,    // 700038E8
+	0x0F124865,    // 700038EA
+	0x0F124669,    // 700038EC
+	0x0F123848,    // 700038EE
+	0x0F12F000,    // 700038F0
+	0x0F12FA42,    // 700038F2
+	0x0F124A5E,    // 700038F4
+	0x0F124862,    // 700038F6
+	0x0F128F51,    // 700038F8
+	0x0F122400,    // 700038FA
+	0x0F123020,    // 700038FC
+	0x0F122900,    // 700038FE
+	0x0F12D00A,    // 70003900
+	0x0F128754,    // 70003902
+	0x0F126941,    // 70003904
+	0x0F126451,    // 70003906
+	0x0F126491,    // 70003908
+	0x0F12466B,    // 7000390A
+	0x0F128819,    // 7000390C
+	0x0F1287D1,    // 7000390E
+	0x0F12885B,    // 70003910
+	0x0F120011,    // 70003912
+	0x0F123140,    // 70003914
+	0x0F12800B,    // 70003916
+	0x0F128F91,    // 70003918
+	0x0F122900,    // 7000391A
+	0x0F12D002,    // 7000391C
+	0x0F128794,    // 7000391E
+	0x0F126940,    // 70003920
+	0x0F126490,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA30,    // 70003926
+	0x0F12BC38,    // 70003928
+	0x0F12BC08,    // 7000392A
+	0x0F124718,    // 7000392C
+	0x0F12B5F8,    // 7000392E
+	0x0F124C56,    // 70003930
+	0x0F1289E0,    // 70003932
+	0x0F12F000,    // 70003934
+	0x0F12FA30,    // 70003936
+	0x0F120006,    // 70003938
+	0x0F128A20,    // 7000393A
+	0x0F12F000,    // 7000393C
+	0x0F12FA34,    // 7000393E
+	0x0F120007,    // 70003940
+	0x0F12484F,    // 70003942
+	0x0F124D4A,    // 70003944
+	0x0F123020,    // 70003946
+	0x0F126CA9,    // 70003948
+	0x0F126940,    // 7000394A
+	0x0F121809,    // 7000394C
+	0x0F120200,    // 7000394E
+	0x0F12F000,    // 70003950
+	0x0F12FA32,    // 70003952
+	0x0F120400,    // 70003954
+	0x0F120C00,    // 70003956
+	0x0F12002A,    // 70003958
+	0x0F12326E,    // 7000395A
+	0x0F120011,    // 7000395C
+	0x0F12390A,    // 7000395E
+	0x0F122305,    // 70003960
+	0x0F12F000,    // 70003962
+	0x0F12FA2F,    // 70003964
+	0x0F124C43,    // 70003966
+	0x0F1261A0,    // 70003968
+	0x0F128FEB,    // 7000396A
+	0x0F120002,    // 7000396C
+	0x0F120031,    // 7000396E
+	0x0F120018,    // 70003970
+	0x0F12F000,    // 70003972
+	0x0F12FA2F,    // 70003974
+	0x0F12466B,    // 70003976
+	0x0F120005,    // 70003978
+	0x0F128018,    // 7000397A
+	0x0F12483C,    // 7000397C
+	0x0F1269A2,    // 7000397E
+	0x0F123040,    // 70003980
+	0x0F128800,    // 70003982
+	0x0F120039,    // 70003984
+	0x0F12F000,    // 70003986
+	0x0F12FA25,    // 70003988
+	0x0F12466B,    // 7000398A
+	0x0F120006,    // 7000398C
+	0x0F128058,    // 7000398E
+	0x0F120021,    // 70003990
+	0x0F129800,    // 70003992
+	0x0F12311C,    // 70003994
+	0x0F12F000,    // 70003996
+	0x0F12FA25,    // 70003998
+	0x0F124935,    // 7000399A
+	0x0F123180,    // 7000399C
+	0x0F12808D,    // 7000399E
+	0x0F1280CE,    // 700039A0
+	0x0F128BA1,    // 700039A2
+	0x0F124836,    // 700039A4
+	0x0F123820,    // 700039A6
+	0x0F128001,    // 700039A8
+	0x0F128BE1,    // 700039AA
+	0x0F128041,    // 700039AC
+	0x0F128C21,    // 700039AE
+	0x0F128081,    // 700039B0
+	0x0F12E701,    // 700039B2
+	0x0F12B5F8,    // 700039B4
+	0x0F124E2E,    // 700039B6
+	0x0F126C70,    // 700039B8
+	0x0F126CB1,    // 700039BA
+	0x0F120200,    // 700039BC
+	0x0F12F000,    // 700039BE
+	0x0F12F9FB,    // 700039C0
+	0x0F120400,    // 700039C2
+	0x0F120C00,    // 700039C4
+	0x0F122401,    // 700039C6
+	0x0F120364,    // 700039C8
+	0x0F1242A0,    // 700039CA
+	0x0F12D200,    // 700039CC
+	0x0F120004,    // 700039CE
+	0x0F124A27,    // 700039D0
+	0x0F120020,    // 700039D2
+	0x0F12327E,    // 700039D4
+	0x0F121F91,    // 700039D6
+	0x0F122303,    // 700039D8
+	0x0F12F000,    // 700039DA
+	0x0F12F9F3,    // 700039DC
+	0x0F120405,    // 700039DE
+	0x0F120C2D,    // 700039E0
+	0x0F124A23,    // 700039E2
+	0x0F120020,    // 700039E4
+	0x0F12325A,    // 700039E6
+	0x0F120011,    // 700039E8
+	0x0F12390A,    // 700039EA
+	0x0F122305,    // 700039EC
+	0x0F12F000,    // 700039EE
+	0x0F12F9E9,    // 700039F0
+	0x0F12491F,    // 700039F2
+	0x0F1264C8,    // 700039F4
+	0x0F12491F,    // 700039F6
+	0x0F124E21,    // 700039F8
+	0x0F1288C8,    // 700039FA
+	0x0F122701,    // 700039FC
+	0x0F122800,    // 700039FE
+	0x0F12D009,    // 70003A00
+	0x0F124C23,    // 70003A02
+	0x0F1238FF,    // 70003A04
+	0x0F121E40,    // 70003A06
+	0x0F12D00A,    // 70003A08
+	0x0F122804,    // 70003A0A
+	0x0F12D042,    // 70003A0C
+	0x0F122806,    // 70003A0E
+	0x0F12D101,    // 70003A10
+	0x0F122000,    // 70003A12
+	0x0F1280C8,    // 70003A14
+	0x0F1282B7,    // 70003A16
+	0x0F122001,    // 70003A18
+	0x0F12F000,    // 70003A1A
+	0x0F12F9EB,    // 70003A1C
+	0x0F12E6CB,    // 70003A1E
+	0x0F12000D,    // 70003A20
+	0x0F12724F,    // 70003A22
+	0x0F122001,    // 70003A24
+	0x0F12F000,    // 70003A26
+	0x0F12F9ED,    // 70003A28
+	0x0F12F000,    // 70003A2A
+	0x0F12F9F3,    // 70003A2C
+	0x0F124910,    // 70003A2E
+	0x0F123148,    // 70003A30
+	0x0F12C903,    // 70003A32
+	0x0F124348,    // 70003A34
+	0x0F120A00,    // 70003A36
+	0x0F126160,    // 70003A38
+	0x0F1220FF,    // 70003A3A
+	0x0F121D40,    // 70003A3C
+	0x0F1280E8,    // 70003A3E
+	0x0F12480C,    // 70003A40
+	0x0F123040,    // 70003A42
+	0x0F127707,    // 70003A44
+	0x0F12E7E6,    // 70003A46
+	0x0F123290,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F123294,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F1204A8,    // 70003A50
+	0x0F127000,    // 70003A52
+	0x0F1215DC,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F125000,    // 70003A58
+	0x0F12D000,    // 70003A5A
+	0x0F121E84,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F121BE4,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F122EA8,    // 70003A64
+	0x0F127000,    // 70003A66
+	0x0F1221A4,    // 70003A68
+	0x0F127000,    // 70003A6A
+	0x0F120100,    // 70003A6C
+	0x0F127000,    // 70003A6E
+	0x0F123F48,    // 70003A70
+	0x0F127000,    // 70003A72
+	0x0F1231A0,    // 70003A74
+	0x0F127000,    // 70003A76
+	0x0F1201E8,    // 70003A78
+	0x0F127000,    // 70003A7A
+	0x0F12F2A0,    // 70003A7C
+	0x0F12D000,    // 70003A7E
+	0x0F122A44,    // 70003A80
+	0x0F127000,    // 70003A82
+	0x0F12F400,    // 70003A84
+	0x0F12D000,    // 70003A86
+	0x0F122024,    // 70003A88
+	0x0F127000,    // 70003A8A
+	0x0F121650,    // 70003A8C
+	0x0F127000,    // 70003A8E
+	0x0F122A64,    // 70003A90
+	0x0F127000,    // 70003A92
+	0x0F12497B,    // 70003A94
+	0x0F12724F,    // 70003A96
+	0x0F1220FF,    // 70003A98
+	0x0F121DC0,    // 70003A9A
+	0x0F1280C8,    // 70003A9C
+	0x0F12F000,    // 70003A9E
+	0x0F12F9C1,    // 70003AA0
+	0x0F124979,    // 70003AA2
+	0x0F126ACA,    // 70003AA4
+	0x0F12604A,    // 70003AA6
+	0x0F122800,    // 70003AA8
+	0x0F12D006,    // 70003AAA
+	0x0F12436A,    // 70003AAC
+	0x0F120001,    // 70003AAE
+	0x0F120010,    // 70003AB0
+	0x0F12F000,    // 70003AB2
+	0x0F12F981,    // 70003AB4
+	0x0F126160,    // 70003AB6
+	0x0F12E001,    // 70003AB8
+	0x0F12436A,    // 70003ABA
+	0x0F126162,    // 70003ABC
+	0x0F128BF0,    // 70003ABE
+	0x0F122800,    // 70003AC0
+	0x0F12D001,    // 70003AC2
+	0x0F12F7FF,    // 70003AC4
+	0x0F12FF33,    // 70003AC6
+	0x0F122000,    // 70003AC8
+	0x0F12F000,    // 70003ACA
+	0x0F12F99B,    // 70003ACC
+	0x0F12496D,    // 70003ACE
+	0x0F1220FF,    // 70003AD0
+	0x0F121DC0,    // 70003AD2
+	0x0F1280C8,    // 70003AD4
+	0x0F12E79E,    // 70003AD6
+	0x0F12B570,    // 70003AD8
+	0x0F120004,    // 70003ADA
+	0x0F12F000,    // 70003ADC
+	0x0F12F9AA,    // 70003ADE
+	0x0F124D6A,    // 70003AE0
+	0x0F128C29,    // 70003AE2
+	0x0F121A40,    // 70003AE4
+	0x0F1242A0,    // 70003AE6
+	0x0F12D803,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F9A3,    // 70003AEC
+	0x0F128C29,    // 70003AEE
+	0x0F121A44,    // 70003AF0
+	0x0F120020,    // 70003AF2
+	0x0F12626C,    // 70003AF4
+	0x0F12F000,    // 70003AF6
+	0x0F12F9A5,    // 70003AF8
+	0x0F1262A8,    // 70003AFA
+	0x0F12F000,    // 70003AFC
+	0x0F12F9AA,    // 70003AFE
+	0x0F126328,    // 70003B00
+	0x0F128869,    // 70003B02
+	0x0F122900,    // 70003B04
+	0x0F12D000,    // 70003B06
+	0x0F1262A8,    // 70003B08
+	0x0F124861,    // 70003B0A
+	0x0F126B00,    // 70003B0C
+	0x0F128C00,    // 70003B0E
+	0x0F122800,    // 70003B10
+	0x0F12D117,    // 70003B12
+	0x0F126AA8,    // 70003B14
+	0x0F12F000,    // 70003B16
+	0x0F12F9A5,    // 70003B18
+	0x0F1261E8,    // 70003B1A
+	0x0F12495D,    // 70003B1C
+	0x0F128B8A,    // 70003B1E
+	0x0F122A00,    // 70003B20
+	0x0F12D00C,    // 70003B22
+	0x0F128BC9,    // 70003B24
+	0x0F124288,    // 70003B26
+	0x0F12D90A,    // 70003B28
+	0x0F12485A,    // 70003B2A
+	0x0F123020,    // 70003B2C
+	0x0F128800,    // 70003B2E
+	0x0F1261E8,    // 70003B30
+	0x0F128C29,    // 70003B32
+	0x0F121A40,    // 70003B34
+	0x0F1262A8,    // 70003B36
+	0x0F12F000,    // 70003B38
+	0x0F12F984,    // 70003B3A
+	0x0F1262A8,    // 70003B3C
+	0x0F12E593,    // 70003B3E
+	0x0F1261E9,    // 70003B40
+	0x0F12E591,    // 70003B42
+	0x0F12F000,    // 70003B44
+	0x0F12F976,    // 70003B46
+	0x0F1261E8,    // 70003B48
+	0x0F12E58D,    // 70003B4A
+	0x0F12B510,    // 70003B4C
+	0x0F12F000,    // 70003B4E
+	0x0F12F991,    // 70003B50
+	0x0F124850,    // 70003B52
+	0x0F123020,    // 70003B54
+	0x0F128841,    // 70003B56
+	0x0F122900,    // 70003B58
+	0x0F12D007,    // 70003B5A
+	0x0F124A4A,    // 70003B5C
+	0x0F123280,    // 70003B5E
+	0x0F126953,    // 70003B60
+	0x0F124A4D,    // 70003B62
+	0x0F12428B,    // 70003B64
+	0x0F12D202,    // 70003B66
+	0x0F128880,    // 70003B68
+	0x0F1281D0,    // 70003B6A
+	0x0F12E5C7,    // 70003B6C
+	0x0F1288C0,    // 70003B6E
+	0x0F1281D0,    // 70003B70
+	0x0F12E5C4,    // 70003B72
+	0x0F12B570,    // 70003B74
+	0x0F126800,    // 70003B76
+	0x0F120605,    // 70003B78
+	0x0F120E2D,    // 70003B7A
+	0x0F124C47,    // 70003B7C
+	0x0F128B60,    // 70003B7E
+	0x0F122800,    // 70003B80
+	0x0F12D010,    // 70003B82
+	0x0F124846,    // 70003B84
+	0x0F128A00,    // 70003B86
+	0x0F1206C0,    // 70003B88
+	0x0F12D50C,    // 70003B8A
+	0x0F124845,    // 70003B8C
+	0x0F127800,    // 70003B8E
+	0x0F122800,    // 70003B90
+	0x0F12D008,    // 70003B92
+	0x0F122000,    // 70003B94
+	0x0F12F000,    // 70003B96
+	0x0F12F975,    // 70003B98
+	0x0F128B20,    // 70003B9A
+	0x0F122201,    // 70003B9C
+	0x0F122180,    // 70003B9E
+	0x0F12F000,    // 70003BA0
+	0x0F12F978,    // 70003BA2
+	0x0F128320,    // 70003BA4
+	0x0F120028,    // 70003BA6
+	0x0F12F000,    // 70003BA8
+	0x0F12F97C,    // 70003BAA
+	0x0F12E55C,    // 70003BAC
+	0x0F12B570,    // 70003BAE
+	0x0F124A38,    // 70003BB0
+	0x0F124836,    // 70003BB2
+	0x0F123220,    // 70003BB4
+	0x0F128A91,    // 70003BB6
+	0x0F1269C0,    // 70003BB8
+	0x0F1226FF,    // 70003BBA
+	0x0F124D31,    // 70003BBC
+	0x0F121D76,    // 70003BBE
+	0x0F124288,    // 70003BC0
+	0x0F12D927,    // 70003BC2
+	0x0F1288E8,    // 70003BC4
+	0x0F1242B0,    // 70003BC6
+	0x0F12D024,    // 70003BC8
+	0x0F124837,    // 70003BCA
+	0x0F124937,    // 70003BCC
+	0x0F127883,    // 70003BCE
+	0x0F120008,    // 70003BD0
+	0x0F1230FF,    // 70003BD2
+	0x0F1231FF,    // 70003BD4
+	0x0F124C36,    // 70003BD6
+	0x0F1230E1,    // 70003BD8
+	0x0F1231C1,    // 70003BDA
+	0x0F128800,    // 70003BDC
+	0x0F128BC9,    // 70003BDE
+	0x0F1269A4,    // 70003BE0
+	0x0F122B00,    // 70003BE2
+	0x0F12D00B,    // 70003BE4
+	0x0F1289D2,    // 70003BE6
+	0x0F122A00,    // 70003BE8
+	0x0F12D013,    // 70003BEA
+	0x0F124350,    // 70003BEC
+	0x0F12F000,    // 70003BEE
+	0x0F12F8E3,    // 70003BF0
+	0x0F121C40,    // 70003BF2
+	0x0F120400,    // 70003BF4
+	0x0F120C00,    // 70003BF6
+	0x0F12F000,    // 70003BF8
+	0x0F12F95C,    // 70003BFA
+	0x0F12E00A,    // 70003BFC
+	0x0F128A12,    // 70003BFE
+	0x0F122A00,    // 70003C00
+	0x0F12D007,    // 70003C02
+	0x0F124350,    // 70003C04
+	0x0F12F000,    // 70003C06
+	0x0F12F8D7,    // 70003C08
+	0x0F121C40,    // 70003C0A
+	0x0F120400,    // 70003C0C
+	0x0F120C00,    // 70003C0E
+	0x0F12F000,    // 70003C10
+	0x0F12F950,    // 70003C12
+	0x0F12F000,    // 70003C14
+	0x0F12F956,    // 70003C16
+	0x0F1288E8,    // 70003C18
+	0x0F1242B0,    // 70003C1A
+	0x0F12D103,    // 70003C1C
+	0x0F124925,    // 70003C1E
+	0x0F1220FF,    // 70003C20
+	0x0F121C40,    // 70003C22
+	0x0F128048,    // 70003C24
+	0x0F12E51F,    // 70003C26
+	0x0F124770,    // 70003C28
+	0x0F12B570,    // 70003C2A
+	0x0F120005,    // 70003C2C
+	0x0F126828,    // 70003C2E
+	0x0F124E16,    // 70003C30
+	0x0F128C31,    // 70003C32
+	0x0F12180C,    // 70003C34
+	0x0F128871,    // 70003C36
+	0x0F122900,    // 70003C38
+	0x0F12D003,    // 70003C3A
+	0x0F120021,    // 70003C3C
+	0x0F12F000,    // 70003C3E
+	0x0F12F949,    // 70003C40
+	0x0F120004,    // 70003C42
+	0x0F124812,    // 70003C44
+	0x0F126976,    // 70003C46
+	0x0F126B00,    // 70003C48
+	0x0F126B40,    // 70003C4A
+	0x0F124286,    // 70003C4C
+	0x0F12D800,    // 70003C4E
+	0x0F120006,    // 70003C50
+	0x0F122101,    // 70003C52
+	0x0F120030,    // 70003C54
+	0x0F12F000,    // 70003C56
+	0x0F12F945,    // 70003C58
+	0x0F120001,    // 70003C5A
+	0x0F12480D,    // 70003C5C
+	0x0F123020,    // 70003C5E
+	0x0F128A40,    // 70003C60
+	0x0F122800,    // 70003C62
+	0x0F12D005,    // 70003C64
+	0x0F120020,    // 70003C66
+	0x0F12428C,    // 70003C68
+	0x0F12D800,    // 70003C6A
+	0x0F120008,    // 70003C6C
+	0x0F126028,    // 70003C6E
+	0x0F12E4FA,    // 70003C70
+	0x0F120020,    // 70003C72
+	0x0F1242B4,    // 70003C74
+	0x0F12D800,    // 70003C76
+	0x0F120030,    // 70003C78
+	0x0F122101,    // 70003C7A
+	0x0F12F000,    // 70003C7C
+	0x0F12F932,    // 70003C7E
+	0x0F126028,    // 70003C80
+	0x0F12E4F1,    // 70003C82
+	0x0F1231A0,    // 70003C84
+	0x0F127000,    // 70003C86
+	0x0F1229E4,    // 70003C88
+	0x0F127000,    // 70003C8A
+	0x0F121E3C,    // 70003C8C
+	0x0F127000,    // 70003C8E
+	0x0F1221A4,    // 70003C90
+	0x0F127000,    // 70003C92
+	0x0F123FC8,    // 70003C94
+	0x0F127000,    // 70003C96
+	0x0F12E200,    // 70003C98
+	0x0F12D000,    // 70003C9A
+	0x0F122EA8,    // 70003C9C
+	0x0F127000,    // 70003C9E
+	0x0F12B040,    // 70003CA0
+	0x0F12D000,    // 70003CA2
+	0x0F12323C,    // 70003CA4
+	0x0F127000,    // 70003CA6
+	0x0F121E84,    // 70003CA8
+	0x0F127000,    // 70003CAA
+	0x0F122024,    // 70003CAC
+	0x0F127000,    // 70003CAE
+	0x0F120080,    // 70003CB0
+	0x0F127000,    // 70003CB2
+	0x0F12C100,    // 70003CB4
+	0x0F12D000,    // 70003CB6
+	0x0F124778,    // 70003CB8
+	0x0F1246C0,    // 70003CBA
+	0x0F12C000,    // 70003CBC
+	0x0F12E59F,    // 70003CBE
+	0x0F12FF1C,    // 70003CC0
+	0x0F12E12F,    // 70003CC2
+	0x0F121F63,    // 70003CC4
+	0x0F120001,    // 70003CC6
+	0x0F124778,    // 70003CC8
+	0x0F1246C0,    // 70003CCA
+	0x0F12C000,    // 70003CCC
+	0x0F12E59F,    // 70003CCE
+	0x0F12FF1C,    // 70003CD0
+	0x0F12E12F,    // 70003CD2
+	0x0F121EDF,    // 70003CD4
+	0x0F120001,    // 70003CD6
+	0x0F124778,    // 70003CD8
+	0x0F1246C0,    // 70003CDA
+	0x0F12C000,    // 70003CDC
+	0x0F12E59F,    // 70003CDE
+	0x0F12FF1C,    // 70003CE0
+	0x0F12E12F,    // 70003CE2
+	0x0F12495F,    // 70003CE4
+	0x0F120000,    // 70003CE6
+	0x0F124778,    // 70003CE8
+	0x0F1246C0,    // 70003CEA
+	0x0F12C000,    // 70003CEC
+	0x0F12E59F,    // 70003CEE
+	0x0F12FF1C,    // 70003CF0
+	0x0F12E12F,    // 70003CF2
+	0x0F12E403,    // 70003CF4
+	0x0F120000,    // 70003CF6
+	0x0F124778,    // 70003CF8
+	0x0F1246C0,    // 70003CFA
+	0x0F12C000,    // 70003CFC
+	0x0F12E59F,    // 70003CFE
+	0x0F12FF1C,    // 70003D00
+	0x0F12E12F,    // 70003D02
+	0x0F1224B3,    // 70003D04
+	0x0F120001,    // 70003D06
+	0x0F124778,    // 70003D08
+	0x0F1246C0,    // 70003D0A
+	0x0F12C000,    // 70003D0C
+	0x0F12E59F,    // 70003D0E
+	0x0F12FF1C,    // 70003D10
+	0x0F12E12F,    // 70003D12
+	0x0F12EECD,    // 70003D14
+	0x0F120000,    // 70003D16
+	0x0F124778,    // 70003D18
+	0x0F1246C0,    // 70003D1A
+	0x0F12C000,    // 70003D1C
+	0x0F12E59F,    // 70003D1E
+	0x0F12FF1C,    // 70003D20
+	0x0F12E12F,    // 70003D22
+	0x0F12F049,    // 70003D24
+	0x0F120000,    // 70003D26
+	0x0F124778,    // 70003D28
+	0x0F1246C0,    // 70003D2A
+	0x0F12C000,    // 70003D2C
+	0x0F12E59F,    // 70003D2E
+	0x0F12FF1C,    // 70003D30
+	0x0F12E12F,    // 70003D32
+	0x0F1212DF,    // 70003D34
+	0x0F120000,    // 70003D36
+	0x0F124778,    // 70003D38
+	0x0F1246C0,    // 70003D3A
+	0x0F12C000,    // 70003D3C
+	0x0F12E59F,    // 70003D3E
+	0x0F12FF1C,    // 70003D40
+	0x0F12E12F,    // 70003D42
+	0x0F12F05B,    // 70003D44
+	0x0F120000,    // 70003D46
+	0x0F124778,    // 70003D48
+	0x0F1246C0,    // 70003D4A
+	0x0F12C000,    // 70003D4C
+	0x0F12E59F,    // 70003D4E
+	0x0F12FF1C,    // 70003D50
+	0x0F12E12F,    // 70003D52
+	0x0F12F07B,    // 70003D54
+	0x0F120000,    // 70003D56
+	0x0F124778,    // 70003D58
+	0x0F1246C0,    // 70003D5A
+	0x0F12C000,    // 70003D5C
+	0x0F12E59F,    // 70003D5E
+	0x0F12FF1C,    // 70003D60
+	0x0F12E12F,    // 70003D62
+	0x0F12FE6D,    // 70003D64
+	0x0F120000,    // 70003D66
+	0x0F124778,    // 70003D68
+	0x0F1246C0,    // 70003D6A
+	0x0F12C000,    // 70003D6C
+	0x0F12E59F,    // 70003D6E
+	0x0F12FF1C,    // 70003D70
+	0x0F12E12F,    // 70003D72
+	0x0F123295,    // 70003D74
+	0x0F120000,    // 70003D76
+	0x0F124778,    // 70003D78
+	0x0F1246C0,    // 70003D7A
+	0x0F12C000,    // 70003D7C
+	0x0F12E59F,    // 70003D7E
+	0x0F12FF1C,    // 70003D80
+	0x0F12E12F,    // 70003D82
+	0x0F12234F,    // 70003D84
+	0x0F120000,    // 70003D86
+	0x0F124778,    // 70003D88
+	0x0F1246C0,    // 70003D8A
+	0x0F12C000,    // 70003D8C
+	0x0F12E59F,    // 70003D8E
+	0x0F12FF1C,    // 70003D90
+	0x0F12E12F,    // 70003D92
+	0x0F124521,    // 70003D94
+	0x0F120000,    // 70003D96
+	0x0F124778,    // 70003D98
+	0x0F1246C0,    // 70003D9A
+	0x0F12C000,    // 70003D9C
+	0x0F12E59F,    // 70003D9E
+	0x0F12FF1C,    // 70003DA0
+	0x0F12E12F,    // 70003DA2
+	0x0F127C0D,    // 70003DA4
+	0x0F120000,    // 70003DA6
+	0x0F124778,    // 70003DA8
+	0x0F1246C0,    // 70003DAA
+	0x0F12C000,    // 70003DAC
+	0x0F12E59F,    // 70003DAE
+	0x0F12FF1C,    // 70003DB0
+	0x0F12E12F,    // 70003DB2
+	0x0F127C2B,    // 70003DB4
+	0x0F120000,    // 70003DB6
+	0x0F124778,    // 70003DB8
+	0x0F1246C0,    // 70003DBA
+	0x0F12F004,    // 70003DBC
+	0x0F12E51F,    // 70003DBE
+	0x0F1224C4,    // 70003DC0
+	0x0F120001,    // 70003DC2
+	0x0F124778,    // 70003DC4
+	0x0F1246C0,    // 70003DC6
+	0x0F12C000,    // 70003DC8
+	0x0F12E59F,    // 70003DCA
+	0x0F12FF1C,    // 70003DCC
+	0x0F12E12F,    // 70003DCE
+	0x0F123183,    // 70003DD0
+	0x0F120000,    // 70003DD2
+	0x0F124778,    // 70003DD4
+	0x0F1246C0,    // 70003DD6
+	0x0F12C000,    // 70003DD8
+	0x0F12E59F,    // 70003DDA
+	0x0F12FF1C,    // 70003DDC
+	0x0F12E12F,    // 70003DDE
+	0x0F12302F,    // 70003DE0
+	0x0F120000,    // 70003DE2
+	0x0F124778,    // 70003DE4
+	0x0F1246C0,    // 70003DE6
+	0x0F12C000,    // 70003DE8
+	0x0F12E59F,    // 70003DEA
+	0x0F12FF1C,    // 70003DEC
+	0x0F12E12F,    // 70003DEE
+	0x0F12EF07,    // 70003DF0
+	0x0F120000,    // 70003DF2
+	0x0F124778,    // 70003DF4
+	0x0F1246C0,    // 70003DF6
+	0x0F12C000,    // 70003DF8
+	0x0F12E59F,    // 70003DFA
+	0x0F12FF1C,    // 70003DFC
+	0x0F12E12F,    // 70003DFE
+	0x0F1248FB,    // 70003E00
+	0x0F120000,    // 70003E02
+	0x0F124778,    // 70003E04
+	0x0F1246C0,    // 70003E06
+	0x0F12C000,    // 70003E08
+	0x0F12E59F,    // 70003E0A
+	0x0F12FF1C,    // 70003E0C
+	0x0F12E12F,    // 70003E0E
+	0x0F12F0B1,    // 70003E10
+	0x0F120000,    // 70003E12
+	0x0F124778,    // 70003E14
+	0x0F1246C0,    // 70003E16
+	0x0F12C000,    // 70003E18
+	0x0F12E59F,    // 70003E1A
+	0x0F12FF1C,    // 70003E1C
+	0x0F12E12F,    // 70003E1E
+	0x0F12EEDF,    // 70003E20
+	0x0F120000,    // 70003E22
+	0x0F124778,    // 70003E24
+	0x0F1246C0,    // 70003E26
+	0x0F12C000,    // 70003E28
+	0x0F12E59F,    // 70003E2A
+	0x0F12FF1C,    // 70003E2C
+	0x0F12E12F,    // 70003E2E
+	0x0F12AEF1,    // 70003E30
+	0x0F120000,    // 70003E32
+	0x0F124778,    // 70003E34
+	0x0F1246C0,    // 70003E36
+	0x0F12C000,    // 70003E38
+	0x0F12E59F,    // 70003E3A
+	0x0F12FF1C,    // 70003E3C
+	0x0F12E12F,    // 70003E3E
+	0x0F1239DF,    // 70003E40
+	0x0F120000,    // 70003E42
+	0x0F124778,    // 70003E44
+	0x0F1246C0,    // 70003E46
+	0x0F12C000,    // 70003E48
+	0x0F12E59F,    // 70003E4A
+	0x0F12FF1C,    // 70003E4C
+	0x0F12E12F,    // 70003E4E
+	0x0F126177,    // 70003E50
+	0x0F120000,    // 70003E52
+	0x0F124778,    // 70003E54
+	0x0F1246C0,    // 70003E56
+	0x0F12C000,    // 70003E58
+	0x0F12E59F,    // 70003E5A
+	0x0F12FF1C,    // 70003E5C
+	0x0F12E12F,    // 70003E5E
+	0x0F12424F,    // 70003E60
+	0x0F120000,    // 70003E62
+	0x0F124778,    // 70003E64
+	0x0F1246C0,    // 70003E66
+	0x0F12C000,    // 70003E68
+	0x0F12E59F,    // 70003E6A
+	0x0F12FF1C,    // 70003E6C
+	0x0F12E12F,    // 70003E6E
+	0x0F123F0D,    // 70003E70
+	0x0F120000,    // 70003E72
+	0x0F124778,    // 70003E74
+	0x0F1246C0,    // 70003E76
+	0x0F12C000,    // 70003E78
+	0x0F12E59F,    // 70003E7A
+	0x0F12FF1C,    // 70003E7C
+	0x0F12E12F,    // 70003E7E
+	0x0F1202B9,    // 70003E80
+	0x0F120001,    // 70003E82
+	0x0F124778,    // 70003E84
+	0x0F1246C0,    // 70003E86
+	0x0F12C000,    // 70003E88
+	0x0F12E59F,    // 70003E8A
+	0x0F12FF1C,    // 70003E8C
+	0x0F12E12F,    // 70003E8E
+	0x0F12FE45,    // 70003E90
+	0x0F120000,    // 70003E92
+	0x0F124778,    // 70003E94
+	0x0F1246C0,    // 70003E96
+	0x0F12C000,    // 70003E98
+	0x0F12E59F,    // 70003E9A
+	0x0F12FF1C,    // 70003E9C
+	0x0F12E12F,    // 70003E9E
+	0x0F1232A7,    // 70003EA0
+	0x0F120000,    // 70003EA2
+	0x0F124778,    // 70003EA4
+	0x0F1246C0,    // 70003EA6
+	0x0F12C000,    // 70003EA8
+	0x0F12E59F,    // 70003EAA
+	0x0F12FF1C,    // 70003EAC
+	0x0F12E12F,    // 70003EAE
+	0x0F12E8AD,    // 70003EB0
+	0x0F120000,    // 70003EB2
+	0x0F124778,    // 70003EB4
+	0x0F1246C0,    // 70003EB6
+	0x0F12C000,    // 70003EB8
+	0x0F12E59F,    // 70003EBA
+	0x0F12FF1C,    // 70003EBC
+	0x0F12E12F,    // 70003EBE
+	0x0F1224B9,    // 70003EC0
+	0x0F120001,    // 70003EC2
+	0x0F124778,    // 70003EC4
+	0x0F1246C0,    // 70003EC6
+	0x0F12C000,    // 70003EC8
+	0x0F12E59F,    // 70003ECA
+	0x0F12FF1C,    // 70003ECC
+	0x0F12E12F,    // 70003ECE
+	0x0F1202EB,    // 70003ED0
+	0x0F120001,    // 70003ED2
+	0x0F124778,    // 70003ED4
+	0x0F1246C0,    // 70003ED6
+	0x0F12C000,    // 70003ED8
+	0x0F12E59F,    // 70003EDA
+	0x0F12FF1C,    // 70003EDC
+	0x0F12E12F,    // 70003EDE
+	0x0F123EC9,    // 70003EE0
+	0x0F120000,    // 70003EE2
+	0x0F124778,    // 70003EE4
+	0x0F1246C0,    // 70003EE6
+	0x0F12C000,    // 70003EE8
+	0x0F12E59F,    // 70003EEA
+	0x0F12FF1C,    // 70003EEC
+	0x0F12E12F,    // 70003EEE
+	0x0F126123,    // 70003EF0
+	0x0F120000,    // 70003EF2
+	// End of Patch Data(Last : 70003EF2h)
+	// Total Size 2504 (0x09C8)
+	// Addr : 352C , Size : 2502(9C6h)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	// 	TNP_GAS_ALPHA_OTP
+	// 	TNP_FR_ACCURATE_DYNAMIC
+	// 	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F120035,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F12024C,	//35,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12021E,	//AA, // 0517 test 027A, // 025A, // 0517 test 024A,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// Analog & APS settings         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// This register is for FACTORY ONLY. If you change it without prior notification         //
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //         //         //         //         //         //
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	// 0725 added - Start
+	0x002AF462,
+	0x0F120001, // atx_option add 0725
+
+	0x002AF2A5,
+	0x0F1201FF, // atx_width  add 0725
+	// 0725 added - End
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120050,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0004                  //extend Forbidden area line
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8	//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32	//34BC //REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32	//34BC //REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8	//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32	//34BC //REG_TC_IPRM_MinOutRate4KHz_0//54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32	//34BC //REG_TC_IPRM_MaxOutRate4KHz_0//54Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8 //REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32 //34BC //REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32 //34BC //REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+	//thumbnail set
+	0x002A0428,
+	0x0F120001,	//REG_TC_THUMB_Thumb_bActive	//Thumbnail Enable
+	0x0F120140,	//REG_TC_THUMB_Thumb_uWidth		//Thumbnail Width 320
+	0x0F1200F0,	//REG_TC_THUMB_Thumb_uHeight	//Thumbnail Height 240
+	0x0F120005,	//REG_TC_THUMB_Thumb_Format		//Thumbnail Output Format 5:YUV
+
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120400, //REG_0TC_PCFG_usWidth
+	0x0F120300, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+	0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#else
+	0x0F120000, //REG_0TC_PCFG_uPrevMirror
+	0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120009,                   //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+#if 0 /* UYVY -> YUYV */
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+#else
+	0x0F120000,                   //REG_0TC_CCFG_PVIMask
+#endif
+	0x0F120050,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// Capture 1 640x480 system 52M PCLK 87M
+	//===================================================================
+	0x002A035A,
+	0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+	0x0F120400,                   //REG_1TC_CCFG_usWidth
+	0x0F120300,                   //REG_1TC_CCFG_usHeight
+	0x0F120009,                   //REG_1TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+	0x002A036A,
+#if 0 /* UYVY -> YUYV */
+	0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+#else
+	0x0F120000,                   //REG_1TC_CCFG_PVIMask
+#endif
+	0x0F120050,                   //REG_1TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+	0x002A0372,
+	0x0F120001,                   //REG_1TC_CCFG_uClockInd
+	0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+	0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_1TC_CCFG_sSaturation
+	0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+
+	// 0613
+	0x0F123400, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123400, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123400, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123400, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123400, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123400, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F124000,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F124000,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120840, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+
+};
+#endif
+
+static const u32 s5k5ccgx_camcorder_set[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,	//REG_TC_GP_PrevReqInputWidth		//Sensor Crop Width	2048
+	0x0F120600,	//REG_TC_GP_PrevReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000,	//REG_TC_GP_PrevInputWidthOfs		//Sensor HOffset 0
+	0x0F120000,	//REG_TC_GP_PrevInputHeightOfs	//Sensor VOffset 0
+	0x0F120800,	//REG_TC_GP_CapReqInputWidth		//Sensor Crop Width	2048
+	0x0F120600,	//REG_TC_GP_CapReqInputHeight		//Sensor Crop Height 1368
+	0x0F120000,	//REG_TC_GP_CapInputWidthOfs		//Sensor HOffset 0
+	0x0F120000,	//REG_TC_GP_CapInputHeightOfs		//Sensor VOffset 0
+	0x002A0216,
+	0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+	0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+
+
+	//Preview Size
+	0x002A0400,
+	0x0F120300,	//REG_0TC_PCFG_usWidth
+	0x0F1201E0,	//REG_0TC_PCFG_usHeight
+
+	0x002A029E,
+	0x0F120400,		//REG_2TC_PCFG_usWidth
+	0x0F120300,   //REG_2TC_PCFG_usHeight
+
+	//Capture Size
+	0x002A0330,
+	0x0F120800,	//REG_0TC_CCFG_usWidth
+	0x0F120600,	//REG_0TC_CCFG_usHeight
+
+	0x002A0388,
+	0x0F120800,   //REG_2TC_CCFG_usWidth
+	0x0F120600,   //REG_2TC_CCFG_usHeight
+
+};
+
+static const u32 s5k5ccgx_update_preview_reg[] = {
+	//PREVIEW
+	0xFCFCD000, // 0601
+	0x00287000, // 0601
+	0x002A0208,
+	0x0F120000, //REG_TC_GP_ActivePrevConfig
+	0x002A0210,
+	0x0F120000, //REG_TC_GP_ActiveCapConfig
+	0x002A020C,
+	0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+	0x002A01F4,
+	0x0F120001, //REG_TC_GP_NewConfigSync
+	0x002A020A,
+	0x0F120001, //REG_TC_GP_PrevConfigChanged
+	0x002A0212,
+	0x0F120001, //REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120000, //REG_TC_GP_EnableCapture
+	0x0F120001, //REG_TC_GP_EnableCaptureChanged
+	0xFFFF0064, //Delay 100ms
+};
+
+static const u32 s5k5ccgx_update_hd_preview_reg[] = {
+	/* PREVIEW */
+	0x002A0208,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0210,
+	0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+	0x002A020C,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F4,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A020A,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A0212,
+	0x0F120001, /* REG_TC_GP_CapConfigChanged */
+	0x002A01E8,
+	0x0F120000, /* REG_TC_GP_EnableCapture */
+	0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+
+	/* TNP_Regs_bUseAccurateFR */
+	0x00287000,
+	0x002A3FE4,
+	0x0F120001, /* on/off TNP_Regs_bAccuDynamicFR */
+	0x0F1234A2, /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+	0x0F1240FD, /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+
+	0xFFFF0064, /* Delay 100ms */
+};
+
+static const u32 s5k5ccgx_stream_stop_reg[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120000,
+	0x0F120001,
+};
+
+static const u32 s5k5ccgx_176_144_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F1200B0,
+	0x0F120090,
+	0x0F120005,
+	0x002A043C,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A023E, //Preview Size
+	0x0F1200B0, //REG_0TC_PCFG_usWidth
+	0x0F120090, //REG_0TC_PCFG_usHeight
+	0x002A0D1E,
+	0x0F122102,
+};
+static const u32 s5k5ccgx_320_240_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F120140,
+	0x0F1200F0,
+	0x0F120005,
+	0x002A043C,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A023E, //Preview Size
+	0x0F120140,	//REG_0TC_PCFG_usWidth 320
+	0x0F1200F0,	//REG_0TC_PCFG_usHeight 240
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_352_288_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F1200B0,
+	0x0F120090,
+	0x0F120005,
+	0x002A043C,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A023E,
+	0x0F120160,	//REG_0TC_PCFG_usWidth 280
+	0x0F120120,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+	0x002A0D1E,
+	0x0F122102,
+};
+static const u32 s5k5ccgx_528_432_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F1200B0,
+	0x0F120090,
+	0x0F120005,
+	0x002A043C,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A023E, //Preview Size
+	0x0F120210, //REG_0TC_PCFG_usWidth
+	0x0F1201B0, //REG_0TC_PCFG_usHeight
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_640_480_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F120140,
+	0x0F1200F0,
+	0x0F120005,
+	0x002A043C,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A023E,
+	0x0F120280,	//REG_0TC_PCFG_usWidth 280
+	0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+	0x002A0D1E,
+	0x0F122102,
+
+};
+
+static const u32 s5k5ccgx_720_480_Preview[] = {
+	0x002A023E,
+	0x0F1202D0,	//REG_0TC_PCFG_usWidth 280
+	0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_736_552_Preview[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x002A043C,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A023E,
+	0x0F1202E0,
+	0x0F120228,
+	0x002A0D1E,
+	0x0F122102,
+	0x002A0208,
+	0x0F120000,
+	0x002A020C,
+	0x0F120001,
+	0x002A020A,
+	0x0F120001,
+};
+
+static const u32 s5k5ccgx_800_600_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F120140,
+	0x0F1200F0,
+	0x0F120005,
+	0x002A043C,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A023E,
+	0x0F120320,	//REG_0TC_PCFG_usWidth 280
+	0x0F120258,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_1024_552_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120228,	//REG_0TC_PCFG_usHeight 228
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+#define S5K5CCGX_WIDE_PREVIEW_REG s5k5ccgx_1024_552_Preview
+
+static const u32 s5k5ccgx_1024_576_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120240,	//REG_0TC_PCFG_usHeight 240
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_616_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120268,	//REG_0TC_PCFG_usHeight 268
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+
+static const u32 s5k5ccgx_1024_768_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F120140,
+	0x0F1200F0,
+	0x0F120005,
+	0x002A043C,
+	0x0F120800,
+	0x0F120600,
+	0x0F120000,
+	0x0F120000,
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 280
+	0x0F120300,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_1280_1024_Preview[] = {
+
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	0x002A352C,
+	0x0F12B5F8,    // 7000352C
+	0x0F124A28,    // 7000352E
+	0x0F124928,    // 70003530
+	0x0F124829,    // 70003532
+	0x0F124B29,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124928,    // 7000353E
+	0x0F124828,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FBB9,    // 70003544
+	0x0F124928,    // 70003546
+	0x0F124828,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FBB5,    // 7000354C
+	0x0F124828,    // 7000354E
+	0x0F124E28,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124928,    // 70003554
+	0x0F124829,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FBAE,    // 7000355A
+	0x0F124828,    // 7000355C
+	0x0F120037,    // 7000355E
+	0x0F123780,    // 70003560
+	0x0F126178,    // 70003562
+	0x0F124C27,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124927,    // 70003568
+	0x0F124828,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FBA4,    // 7000356E
+	0x0F124927,    // 70003570
+	0x0F124828,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FBA0,    // 70003576
+	0x0F124927,    // 70003578
+	0x0F124828,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FB9C,    // 7000357E
+	0x0F124927,    // 70003580
+	0x0F124828,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB98,    // 70003586
+	0x0F1283A5,    // 70003588
+	0x0F124827,    // 7000358A
+	0x0F126470,    // 7000358C
+	0x0F122001,    // 7000358E
+	0x0F120340,    // 70003590
+	0x0F123420,    // 70003592
+	0x0F128060,    // 70003594
+	0x0F122085,    // 70003596
+	0x0F1280A0,    // 70003598
+	0x0F124824,    // 7000359A
+	0x0F1280E0,    // 7000359C
+	0x0F124824,    // 7000359E
+	0x0F126730,    // 700035A0
+	0x0F124924,    // 700035A2
+	0x0F124824,    // 700035A4
+	0x0F12F000,    // 700035A6
+	0x0F12FB87,    // 700035A8
+	0x0F1281E5,    // 700035AA
+	0x0F128225,    // 700035AC
+	0x0F124823,    // 700035AE
+	0x0F1282A0,    // 700035B0
+	0x0F124813,    // 700035B2
+	0x0F126178,    // 700035B4
+	0x0F122001,    // 700035B6
+	0x0F128260,    // 700035B8
+	0x0F124921,    // 700035BA
+	0x0F124821,    // 700035BC
+	0x0F12F000,    // 700035BE
+	0x0F12FB7B,    // 700035C0
+	0x0F124921,    // 700035C2
+	0x0F124821,    // 700035C4
+	0x0F12F000,    // 700035C6
+	0x0F12FB77,    // 700035C8
+	0x0F12BCF8,    // 700035CA
+	0x0F12BC08,    // 700035CC
+	0x0F124718,    // 700035CE
+	0x0F1200D6,    // 700035D0
+	0x0F125CC1,    // 700035D2
+	0x0F12633D,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F121C08,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F123290,    // 700035DC
+	0x0F127000,    // 700035DE
+	0x0F12366F,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F12D9E7,    // 700035E4
+	0x0F120000,    // 700035E6
+	0x0F123857,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F12395D,    // 700035EC
+	0x0F120000,    // 700035EE
+	0x0F1238E9,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F120000,    // 700035F4
+	0x0F127000,    // 700035F6
+	0x0F1239B5,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12F903,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F123BAF,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F123FC8,    // 70003604
+	0x0F127000,    // 70003606
+	0x0F1236A7,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F12495F,    // 7000360C
+	0x0F120000,    // 7000360E
+	0x0F123705,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F12E421,    // 70003614
+	0x0F120000,    // 70003616
+	0x0F1237C3,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F12216D,    // 7000361C
+	0x0F120000,    // 7000361E
+	0x0F123837,    // 70003620
+	0x0F127000,    // 70003622
+	0x0F120179,    // 70003624
+	0x0F120001,    // 70003626
+	0x0F123AD9,    // 70003628
+	0x0F127000,    // 7000362A
+	0x0F1207FF,    // 7000362C
+	0x0F120000,    // 7000362E
+	0x0F123B4D,    // 70003630
+	0x0F127000,    // 70003632
+	0x0F123B75,    // 70003634
+	0x0F127000,    // 70003636
+	0x0F12E8AD,    // 70003638
+	0x0F120000,    // 7000363A
+	0x0F124E20,    // 7000363C
+	0x0F120000,    // 7000363E
+	0x0F123C29,    // 70003640
+	0x0F127000,    // 70003642
+	0x0F123C4D,    // 70003644
+	0x0F120000,    // 70003646
+	0x0F123C2B,    // 70003648
+	0x0F127000,    // 7000364A
+	0x0F123F0D,    // 7000364C
+	0x0F120000,    // 7000364E
+	0x0F12B570,    // 70003650
+	0x0F12000D,    // 70003652
+	0x0F124CFC,    // 70003654
+	0x0F128821,    // 70003656
+	0x0F12F000,    // 70003658
+	0x0F12FB36,    // 7000365A
+	0x0F128820,    // 7000365C
+	0x0F124AFB,    // 7000365E
+	0x0F120081,    // 70003660
+	0x0F125055,    // 70003662
+	0x0F121C40,    // 70003664
+	0x0F128020,    // 70003666
+	0x0F12BC70,    // 70003668
+	0x0F12BC08,    // 7000366A
+	0x0F124718,    // 7000366C
+	0x0F126801,    // 7000366E
+	0x0F120409,    // 70003670
+	0x0F120C09,    // 70003672
+	0x0F126840,    // 70003674
+	0x0F120400,    // 70003676
+	0x0F120C00,    // 70003678
+	0x0F124AF5,    // 7000367A
+	0x0F128992,    // 7000367C
+	0x0F122A00,    // 7000367E
+	0x0F12D00D,    // 70003680
+	0x0F122300,    // 70003682
+	0x0F121A80,    // 70003684
+	0x0F12D400,    // 70003686
+	0x0F120003,    // 70003688
+	0x0F120418,    // 7000368A
+	0x0F120C00,    // 7000368C
+	0x0F124BF1,    // 7000368E
+	0x0F121851,    // 70003690
+	0x0F12891B,    // 70003692
+	0x0F12428B,    // 70003694
+	0x0F12D300,    // 70003696
+	0x0F12000B,    // 70003698
+	0x0F120419,    // 7000369A
+	0x0F120C09,    // 7000369C
+	0x0F124AEE,    // 7000369E
+	0x0F128151,    // 700036A0
+	0x0F128190,    // 700036A2
+	0x0F124770,    // 700036A4
+	0x0F12B510,    // 700036A6
+	0x0F124CEC,    // 700036A8
+	0x0F1248ED,    // 700036AA
+	0x0F1278A1,    // 700036AC
+	0x0F122900,    // 700036AE
+	0x0F12D101,    // 700036B0
+	0x0F1287C1,    // 700036B2
+	0x0F12E004,    // 700036B4
+	0x0F127AE1,    // 700036B6
+	0x0F122900,    // 700036B8
+	0x0F12D001,    // 700036BA
+	0x0F122101,    // 700036BC
+	0x0F1287C1,    // 700036BE
+	0x0F12F000,    // 700036C0
+	0x0F12FB0A,    // 700036C2
+	0x0F1249E7,    // 700036C4
+	0x0F128B08,    // 700036C6
+	0x0F1206C2,    // 700036C8
+	0x0F12D50A,    // 700036CA
+	0x0F127AA2,    // 700036CC
+	0x0F120652,    // 700036CE
+	0x0F12D507,    // 700036D0
+	0x0F122210,    // 700036D2
+	0x0F124390,    // 700036D4
+	0x0F128308,    // 700036D6
+	0x0F1248E3,    // 700036D8
+	0x0F127AE1,    // 700036DA
+	0x0F126B00,    // 700036DC
+	0x0F12F000,    // 700036DE
+	0x0F12FB03,    // 700036E0
+	0x0F1248DB,    // 700036E2
+	0x0F1289C0,    // 700036E4
+	0x0F122801,    // 700036E6
+	0x0F12D109,    // 700036E8
+	0x0F1278A0,    // 700036EA
+	0x0F122800,    // 700036EC
+	0x0F12D006,    // 700036EE
+	0x0F127AE0,    // 700036F0
+	0x0F122800,    // 700036F2
+	0x0F12D003,    // 700036F4
+	0x0F127AA0,    // 700036F6
+	0x0F122140,    // 700036F8
+	0x0F124308,    // 700036FA
+	0x0F1272A0,    // 700036FC
+	0x0F12BC10,    // 700036FE
+	0x0F12BC08,    // 70003700
+	0x0F124718,    // 70003702
+	0x0F12B570,    // 70003704
+	0x0F124DD7,    // 70003706
+	0x0F124CD7,    // 70003708
+	0x0F128B28,    // 7000370A
+	0x0F120701,    // 7000370C
+	0x0F12D507,    // 7000370E
+	0x0F122108,    // 70003710
+	0x0F124388,    // 70003712
+	0x0F128328,    // 70003714
+	0x0F1249D5,    // 70003716
+	0x0F126B20,    // 70003718
+	0x0F126B89,    // 7000371A
+	0x0F12F000,    // 7000371C
+	0x0F12FAEC,    // 7000371E
+	0x0F128B28,    // 70003720
+	0x0F1206C1,    // 70003722
+	0x0F12D5A0,    // 70003724
+	0x0F1249CD,    // 70003726
+	0x0F127A8A,    // 70003728
+	0x0F120652,    // 7000372A
+	0x0F12D49C,    // 7000372C
+	0x0F122210,    // 7000372E
+	0x0F124390,    // 70003730
+	0x0F128328,    // 70003732
+	0x0F127AC9,    // 70003734
+	0x0F126B20,    // 70003736
+	0x0F12F000,    // 70003738
+	0x0F12FAD6,    // 7000373A
+	0x0F12E794,    // 7000373C
+	0x0F12B5F8,    // 7000373E
+	0x0F1249CB,    // 70003740
+	0x0F128F08,    // 70003742
+	0x0F12000C,    // 70003744
+	0x0F123480,    // 70003746
+	0x0F122800,    // 70003748
+	0x0F12D000,    // 7000374A
+	0x0F128360,    // 7000374C
+	0x0F122000,    // 7000374E
+	0x0F128708,    // 70003750
+	0x0F124DC8,    // 70003752
+	0x0F1226FF,    // 70003754
+	0x0F128828,    // 70003756
+	0x0F121C76,    // 70003758
+	0x0F122702,    // 7000375A
+	0x0F122803,    // 7000375C
+	0x0F12D112,    // 7000375E
+	0x0F128868,    // 70003760
+	0x0F122800,    // 70003762
+	0x0F12D10F,    // 70003764
+	0x0F1288E8,    // 70003766
+	0x0F122800,    // 70003768
+	0x0F12D10C,    // 7000376A
+	0x0F12F000,    // 7000376C
+	0x0F12FACC,    // 7000376E
+	0x0F122800,    // 70003770
+	0x0F12D008,    // 70003772
+	0x0F128B60,    // 70003774
+	0x0F122800,    // 70003776
+	0x0F12D001,    // 70003778
+	0x0F1280EE,    // 7000377A
+	0x0F1280AF,    // 7000377C
+	0x0F122001,    // 7000377E
+	0x0F127268,    // 70003780
+	0x0F12F000,    // 70003782
+	0x0F12FAC9,    // 70003784
+	0x0F128828,    // 70003786
+	0x0F122802,    // 70003788
+	0x0F12D10E,    // 7000378A
+	0x0F128868,    // 7000378C
+	0x0F122800,    // 7000378E
+	0x0F12D10B,    // 70003790
+	0x0F1288E8,    // 70003792
+	0x0F122800,    // 70003794
+	0x0F12D108,    // 70003796
+	0x0F128B60,    // 70003798
+	0x0F122800,    // 7000379A
+	0x0F12D001,    // 7000379C
+	0x0F1280EE,    // 7000379E
+	0x0F1280AF,    // 700037A0
+	0x0F122001,    // 700037A2
+	0x0F127268,    // 700037A4
+	0x0F12F000,    // 700037A6
+	0x0F12FAB7,    // 700037A8
+	0x0F1288E8,    // 700037AA
+	0x0F122800,    // 700037AC
+	0x0F12D006,    // 700037AE
+	0x0F121FC1,    // 700037B0
+	0x0F1239FD,    // 700037B2
+	0x0F12D003,    // 700037B4
+	0x0F122001,    // 700037B6
+	0x0F12BCF8,    // 700037B8
+	0x0F12BC08,    // 700037BA
+	0x0F124718,    // 700037BC
+	0x0F122000,    // 700037BE
+	0x0F12E7FA,    // 700037C0
+	0x0F12B570,    // 700037C2
+	0x0F124CAC,    // 700037C4
+	0x0F128860,    // 700037C6
+	0x0F122800,    // 700037C8
+	0x0F12D00C,    // 700037CA
+	0x0F128820,    // 700037CC
+	0x0F124DA3,    // 700037CE
+	0x0F122800,    // 700037D0
+	0x0F12D009,    // 700037D2
+	0x0F120029,    // 700037D4
+	0x0F1231A0,    // 700037D6
+	0x0F127AC9,    // 700037D8
+	0x0F122900,    // 700037DA
+	0x0F12D004,    // 700037DC
+	0x0F127AA8,    // 700037DE
+	0x0F122180,    // 700037E0
+	0x0F124308,    // 700037E2
+	0x0F1272A8,    // 700037E4
+	0x0F12E73F,    // 700037E6
+	0x0F122800,    // 700037E8
+	0x0F12D003,    // 700037EA
+	0x0F12F7FF,    // 700037EC
+	0x0F12FFA7,    // 700037EE
+	0x0F122800,    // 700037F0
+	0x0F12D1F8,    // 700037F2
+	0x0F122000,    // 700037F4
+	0x0F128060,    // 700037F6
+	0x0F128820,    // 700037F8
+	0x0F122800,    // 700037FA
+	0x0F12D003,    // 700037FC
+	0x0F122008,    // 700037FE
+	0x0F12F000,    // 70003800
+	0x0F12FA92,    // 70003802
+	0x0F12E00B,    // 70003804
+	0x0F12489C,    // 70003806
+	0x0F123020,    // 70003808
+	0x0F128880,    // 7000380A
+	0x0F122800,    // 7000380C
+	0x0F12D103,    // 7000380E
+	0x0F127AA8,    // 70003810
+	0x0F122101,    // 70003812
+	0x0F124308,    // 70003814
+	0x0F1272A8,    // 70003816
+	0x0F122010,    // 70003818
+	0x0F12F000,    // 7000381A
+	0x0F12FA85,    // 7000381C
+	0x0F128820,    // 7000381E
+	0x0F122800,    // 70003820
+	0x0F12D1E0,    // 70003822
+	0x0F12488A,    // 70003824
+	0x0F1289C0,    // 70003826
+	0x0F122801,    // 70003828
+	0x0F12D1DC,    // 7000382A
+	0x0F127AA8,    // 7000382C
+	0x0F1221BF,    // 7000382E
+	0x0F124008,    // 70003830
+	0x0F1272A8,    // 70003832
+	0x0F12E718,    // 70003834
+	0x0F126800,    // 70003836
+	0x0F124990,    // 70003838
+	0x0F128188,    // 7000383A
+	0x0F124890,    // 7000383C
+	0x0F122201,    // 7000383E
+	0x0F128981,    // 70003840
+	0x0F124890,    // 70003842
+	0x0F120252,    // 70003844
+	0x0F124291,    // 70003846
+	0x0F12D902,    // 70003848
+	0x0F122102,    // 7000384A
+	0x0F128181,    // 7000384C
+	0x0F124770,    // 7000384E
+	0x0F122101,    // 70003850
+	0x0F128181,    // 70003852
+	0x0F124770,    // 70003854
+	0x0F12B5F1,    // 70003856
+	0x0F124E80,    // 70003858
+	0x0F128834,    // 7000385A
+	0x0F122C00,    // 7000385C
+	0x0F12D03F,    // 7000385E
+	0x0F122001,    // 70003860
+	0x0F122C08,    // 70003862
+	0x0F12D000,    // 70003864
+	0x0F122000,    // 70003866
+	0x0F1270B0,    // 70003868
+	0x0F124D7F,    // 7000386A
+	0x0F122800,    // 7000386C
+	0x0F12D009,    // 7000386E
+	0x0F12F000,    // 70003870
+	0x0F12FA62,    // 70003872
+	0x0F120028,    // 70003874
+	0x0F1238F0,    // 70003876
+	0x0F126328,    // 70003878
+	0x0F127AB0,    // 7000387A
+	0x0F12217E,    // 7000387C
+	0x0F124008,    // 7000387E
+	0x0F1272B0,    // 70003880
+	0x0F12E00F,    // 70003882
+	0x0F124F7A,    // 70003884
+	0x0F123780,    // 70003886
+	0x0F128B78,    // 70003888
+	0x0F122800,    // 7000388A
+	0x0F12D005,    // 7000388C
+	0x0F12F000,    // 7000388E
+	0x0F12FA5B,    // 70003890
+	0x0F122000,    // 70003892
+	0x0F128378,    // 70003894
+	0x0F124976,    // 70003896
+	0x0F128708,    // 70003898
+	0x0F122000,    // 7000389A
+	0x0F12F000,    // 7000389C
+	0x0F12FA5C,    // 7000389E
+	0x0F124879,    // 700038A0
+	0x0F126328,    // 700038A2
+	0x0F1278B1,    // 700038A4
+	0x0F122700,    // 700038A6
+	0x0F120038,    // 700038A8
+	0x0F122900,    // 700038AA
+	0x0F12D008,    // 700038AC
+	0x0F124972,    // 700038AE
+	0x0F123920,    // 700038B0
+	0x0F128ACA,    // 700038B2
+	0x0F122A00,    // 700038B4
+	0x0F12D003,    // 700038B6
+	0x0F128B09,    // 700038B8
+	0x0F122900,    // 700038BA
+	0x0F12D000,    // 700038BC
+	0x0F122001,    // 700038BE
+	0x0F127170,    // 700038C0
+	0x0F122C02,    // 700038C2
+	0x0F12D102,    // 700038C4
+	0x0F124868,    // 700038C6
+	0x0F123860,    // 700038C8
+	0x0F126328,    // 700038CA
+	0x0F122201,    // 700038CC
+	0x0F122C02,    // 700038CE
+	0x0F12D000,    // 700038D0
+	0x0F122200,    // 700038D2
+	0x0F124861,    // 700038D4
+	0x0F122110,    // 700038D6
+	0x0F12300A,    // 700038D8
+	0x0F12F000,    // 700038DA
+	0x0F12FA45,    // 700038DC
+	0x0F128037,    // 700038DE
+	0x0F129900,    // 700038E0
+	0x0F120020,    // 700038E2
+	0x0F12600C,    // 700038E4
+	0x0F12E767,    // 700038E6
+	0x0F12B538,    // 700038E8
+	0x0F124865,    // 700038EA
+	0x0F124669,    // 700038EC
+	0x0F123848,    // 700038EE
+	0x0F12F000,    // 700038F0
+	0x0F12FA42,    // 700038F2
+	0x0F124A5E,    // 700038F4
+	0x0F124862,    // 700038F6
+	0x0F128F51,    // 700038F8
+	0x0F122400,    // 700038FA
+	0x0F123020,    // 700038FC
+	0x0F122900,    // 700038FE
+	0x0F12D00A,    // 70003900
+	0x0F128754,    // 70003902
+	0x0F126941,    // 70003904
+	0x0F126451,    // 70003906
+	0x0F126491,    // 70003908
+	0x0F12466B,    // 7000390A
+	0x0F128819,    // 7000390C
+	0x0F1287D1,    // 7000390E
+	0x0F12885B,    // 70003910
+	0x0F120011,    // 70003912
+	0x0F123140,    // 70003914
+	0x0F12800B,    // 70003916
+	0x0F128F91,    // 70003918
+	0x0F122900,    // 7000391A
+	0x0F12D002,    // 7000391C
+	0x0F128794,    // 7000391E
+	0x0F126940,    // 70003920
+	0x0F126490,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA30,    // 70003926
+	0x0F12BC38,    // 70003928
+	0x0F12BC08,    // 7000392A
+	0x0F124718,    // 7000392C
+	0x0F12B5F8,    // 7000392E
+	0x0F124C56,    // 70003930
+	0x0F1289E0,    // 70003932
+	0x0F12F000,    // 70003934
+	0x0F12FA30,    // 70003936
+	0x0F120006,    // 70003938
+	0x0F128A20,    // 7000393A
+	0x0F12F000,    // 7000393C
+	0x0F12FA34,    // 7000393E
+	0x0F120007,    // 70003940
+	0x0F12484F,    // 70003942
+	0x0F124D4A,    // 70003944
+	0x0F123020,    // 70003946
+	0x0F126CA9,    // 70003948
+	0x0F126940,    // 7000394A
+	0x0F121809,    // 7000394C
+	0x0F120200,    // 7000394E
+	0x0F12F000,    // 70003950
+	0x0F12FA32,    // 70003952
+	0x0F120400,    // 70003954
+	0x0F120C00,    // 70003956
+	0x0F12002A,    // 70003958
+	0x0F12326E,    // 7000395A
+	0x0F120011,    // 7000395C
+	0x0F12390A,    // 7000395E
+	0x0F122305,    // 70003960
+	0x0F12F000,    // 70003962
+	0x0F12FA2F,    // 70003964
+	0x0F124C43,    // 70003966
+	0x0F1261A0,    // 70003968
+	0x0F128FEB,    // 7000396A
+	0x0F120002,    // 7000396C
+	0x0F120031,    // 7000396E
+	0x0F120018,    // 70003970
+	0x0F12F000,    // 70003972
+	0x0F12FA2F,    // 70003974
+	0x0F12466B,    // 70003976
+	0x0F120005,    // 70003978
+	0x0F128018,    // 7000397A
+	0x0F12483C,    // 7000397C
+	0x0F1269A2,    // 7000397E
+	0x0F123040,    // 70003980
+	0x0F128800,    // 70003982
+	0x0F120039,    // 70003984
+	0x0F12F000,    // 70003986
+	0x0F12FA25,    // 70003988
+	0x0F12466B,    // 7000398A
+	0x0F120006,    // 7000398C
+	0x0F128058,    // 7000398E
+	0x0F120021,    // 70003990
+	0x0F129800,    // 70003992
+	0x0F12311C,    // 70003994
+	0x0F12F000,    // 70003996
+	0x0F12FA25,    // 70003998
+	0x0F124935,    // 7000399A
+	0x0F123180,    // 7000399C
+	0x0F12808D,    // 7000399E
+	0x0F1280CE,    // 700039A0
+	0x0F128BA1,    // 700039A2
+	0x0F124836,    // 700039A4
+	0x0F123820,    // 700039A6
+	0x0F128001,    // 700039A8
+	0x0F128BE1,    // 700039AA
+	0x0F128041,    // 700039AC
+	0x0F128C21,    // 700039AE
+	0x0F128081,    // 700039B0
+	0x0F12E701,    // 700039B2
+	0x0F12B5F8,    // 700039B4
+	0x0F124E2E,    // 700039B6
+	0x0F126C70,    // 700039B8
+	0x0F126CB1,    // 700039BA
+	0x0F120200,    // 700039BC
+	0x0F12F000,    // 700039BE
+	0x0F12F9FB,    // 700039C0
+	0x0F120400,    // 700039C2
+	0x0F120C00,    // 700039C4
+	0x0F122401,    // 700039C6
+	0x0F120364,    // 700039C8
+	0x0F1242A0,    // 700039CA
+	0x0F12D200,    // 700039CC
+	0x0F120004,    // 700039CE
+	0x0F124A27,    // 700039D0
+	0x0F120020,    // 700039D2
+	0x0F12327E,    // 700039D4
+	0x0F121F91,    // 700039D6
+	0x0F122303,    // 700039D8
+	0x0F12F000,    // 700039DA
+	0x0F12F9F3,    // 700039DC
+	0x0F120405,    // 700039DE
+	0x0F120C2D,    // 700039E0
+	0x0F124A23,    // 700039E2
+	0x0F120020,    // 700039E4
+	0x0F12325A,    // 700039E6
+	0x0F120011,    // 700039E8
+	0x0F12390A,    // 700039EA
+	0x0F122305,    // 700039EC
+	0x0F12F000,    // 700039EE
+	0x0F12F9E9,    // 700039F0
+	0x0F12491F,    // 700039F2
+	0x0F1264C8,    // 700039F4
+	0x0F12491F,    // 700039F6
+	0x0F124E21,    // 700039F8
+	0x0F1288C8,    // 700039FA
+	0x0F122701,    // 700039FC
+	0x0F122800,    // 700039FE
+	0x0F12D009,    // 70003A00
+	0x0F124C23,    // 70003A02
+	0x0F1238FF,    // 70003A04
+	0x0F121E40,    // 70003A06
+	0x0F12D00A,    // 70003A08
+	0x0F122804,    // 70003A0A
+	0x0F12D042,    // 70003A0C
+	0x0F122806,    // 70003A0E
+	0x0F12D101,    // 70003A10
+	0x0F122000,    // 70003A12
+	0x0F1280C8,    // 70003A14
+	0x0F1282B7,    // 70003A16
+	0x0F122001,    // 70003A18
+	0x0F12F000,    // 70003A1A
+	0x0F12F9EB,    // 70003A1C
+	0x0F12E6CB,    // 70003A1E
+	0x0F12000D,    // 70003A20
+	0x0F12724F,    // 70003A22
+	0x0F122001,    // 70003A24
+	0x0F12F000,    // 70003A26
+	0x0F12F9ED,    // 70003A28
+	0x0F12F000,    // 70003A2A
+	0x0F12F9F3,    // 70003A2C
+	0x0F124910,    // 70003A2E
+	0x0F123148,    // 70003A30
+	0x0F12C903,    // 70003A32
+	0x0F124348,    // 70003A34
+	0x0F120A00,    // 70003A36
+	0x0F126160,    // 70003A38
+	0x0F1220FF,    // 70003A3A
+	0x0F121D40,    // 70003A3C
+	0x0F1280E8,    // 70003A3E
+	0x0F12480C,    // 70003A40
+	0x0F123040,    // 70003A42
+	0x0F127707,    // 70003A44
+	0x0F12E7E6,    // 70003A46
+	0x0F123290,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F123294,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F1204A8,    // 70003A50
+	0x0F127000,    // 70003A52
+	0x0F1215DC,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F125000,    // 70003A58
+	0x0F12D000,    // 70003A5A
+	0x0F121E84,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F121BE4,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F122EA8,    // 70003A64
+	0x0F127000,    // 70003A66
+	0x0F1221A4,    // 70003A68
+	0x0F127000,    // 70003A6A
+	0x0F120100,    // 70003A6C
+	0x0F127000,    // 70003A6E
+	0x0F123F48,    // 70003A70
+	0x0F127000,    // 70003A72
+	0x0F1231A0,    // 70003A74
+	0x0F127000,    // 70003A76
+	0x0F1201E8,    // 70003A78
+	0x0F127000,    // 70003A7A
+	0x0F12F2A0,    // 70003A7C
+	0x0F12D000,    // 70003A7E
+	0x0F122A44,    // 70003A80
+	0x0F127000,    // 70003A82
+	0x0F12F400,    // 70003A84
+	0x0F12D000,    // 70003A86
+	0x0F122024,    // 70003A88
+	0x0F127000,    // 70003A8A
+	0x0F121650,    // 70003A8C
+	0x0F127000,    // 70003A8E
+	0x0F122A64,    // 70003A90
+	0x0F127000,    // 70003A92
+	0x0F12497B,    // 70003A94
+	0x0F12724F,    // 70003A96
+	0x0F1220FF,    // 70003A98
+	0x0F121DC0,    // 70003A9A
+	0x0F1280C8,    // 70003A9C
+	0x0F12F000,    // 70003A9E
+	0x0F12F9C1,    // 70003AA0
+	0x0F124979,    // 70003AA2
+	0x0F126ACA,    // 70003AA4
+	0x0F12604A,    // 70003AA6
+	0x0F122800,    // 70003AA8
+	0x0F12D006,    // 70003AAA
+	0x0F12436A,    // 70003AAC
+	0x0F120001,    // 70003AAE
+	0x0F120010,    // 70003AB0
+	0x0F12F000,    // 70003AB2
+	0x0F12F981,    // 70003AB4
+	0x0F126160,    // 70003AB6
+	0x0F12E001,    // 70003AB8
+	0x0F12436A,    // 70003ABA
+	0x0F126162,    // 70003ABC
+	0x0F128BF0,    // 70003ABE
+	0x0F122800,    // 70003AC0
+	0x0F12D001,    // 70003AC2
+	0x0F12F7FF,    // 70003AC4
+	0x0F12FF33,    // 70003AC6
+	0x0F122000,    // 70003AC8
+	0x0F12F000,    // 70003ACA
+	0x0F12F99B,    // 70003ACC
+	0x0F12496D,    // 70003ACE
+	0x0F1220FF,    // 70003AD0
+	0x0F121DC0,    // 70003AD2
+	0x0F1280C8,    // 70003AD4
+	0x0F12E79E,    // 70003AD6
+	0x0F12B570,    // 70003AD8
+	0x0F120004,    // 70003ADA
+	0x0F12F000,    // 70003ADC
+	0x0F12F9AA,    // 70003ADE
+	0x0F124D6A,    // 70003AE0
+	0x0F128C29,    // 70003AE2
+	0x0F121A40,    // 70003AE4
+	0x0F1242A0,    // 70003AE6
+	0x0F12D803,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F9A3,    // 70003AEC
+	0x0F128C29,    // 70003AEE
+	0x0F121A44,    // 70003AF0
+	0x0F120020,    // 70003AF2
+	0x0F12626C,    // 70003AF4
+	0x0F12F000,    // 70003AF6
+	0x0F12F9A5,    // 70003AF8
+	0x0F1262A8,    // 70003AFA
+	0x0F12F000,    // 70003AFC
+	0x0F12F9AA,    // 70003AFE
+	0x0F126328,    // 70003B00
+	0x0F128869,    // 70003B02
+	0x0F122900,    // 70003B04
+	0x0F12D000,    // 70003B06
+	0x0F1262A8,    // 70003B08
+	0x0F124861,    // 70003B0A
+	0x0F126B00,    // 70003B0C
+	0x0F128C00,    // 70003B0E
+	0x0F122800,    // 70003B10
+	0x0F12D117,    // 70003B12
+	0x0F126AA8,    // 70003B14
+	0x0F12F000,    // 70003B16
+	0x0F12F9A5,    // 70003B18
+	0x0F1261E8,    // 70003B1A
+	0x0F12495D,    // 70003B1C
+	0x0F128B8A,    // 70003B1E
+	0x0F122A00,    // 70003B20
+	0x0F12D00C,    // 70003B22
+	0x0F128BC9,    // 70003B24
+	0x0F124288,    // 70003B26
+	0x0F12D90A,    // 70003B28
+	0x0F12485A,    // 70003B2A
+	0x0F123020,    // 70003B2C
+	0x0F128800,    // 70003B2E
+	0x0F1261E8,    // 70003B30
+	0x0F128C29,    // 70003B32
+	0x0F121A40,    // 70003B34
+	0x0F1262A8,    // 70003B36
+	0x0F12F000,    // 70003B38
+	0x0F12F984,    // 70003B3A
+	0x0F1262A8,    // 70003B3C
+	0x0F12E593,    // 70003B3E
+	0x0F1261E9,    // 70003B40
+	0x0F12E591,    // 70003B42
+	0x0F12F000,    // 70003B44
+	0x0F12F976,    // 70003B46
+	0x0F1261E8,    // 70003B48
+	0x0F12E58D,    // 70003B4A
+	0x0F12B510,    // 70003B4C
+	0x0F12F000,    // 70003B4E
+	0x0F12F991,    // 70003B50
+	0x0F124850,    // 70003B52
+	0x0F123020,    // 70003B54
+	0x0F128841,    // 70003B56
+	0x0F122900,    // 70003B58
+	0x0F12D007,    // 70003B5A
+	0x0F124A4A,    // 70003B5C
+	0x0F123280,    // 70003B5E
+	0x0F126953,    // 70003B60
+	0x0F124A4D,    // 70003B62
+	0x0F12428B,    // 70003B64
+	0x0F12D202,    // 70003B66
+	0x0F128880,    // 70003B68
+	0x0F1281D0,    // 70003B6A
+	0x0F12E5C7,    // 70003B6C
+	0x0F1288C0,    // 70003B6E
+	0x0F1281D0,    // 70003B70
+	0x0F12E5C4,    // 70003B72
+	0x0F12B570,    // 70003B74
+	0x0F126800,    // 70003B76
+	0x0F120605,    // 70003B78
+	0x0F120E2D,    // 70003B7A
+	0x0F124C47,    // 70003B7C
+	0x0F128B60,    // 70003B7E
+	0x0F122800,    // 70003B80
+	0x0F12D010,    // 70003B82
+	0x0F124846,    // 70003B84
+	0x0F128A00,    // 70003B86
+	0x0F1206C0,    // 70003B88
+	0x0F12D50C,    // 70003B8A
+	0x0F124845,    // 70003B8C
+	0x0F127800,    // 70003B8E
+	0x0F122800,    // 70003B90
+	0x0F12D008,    // 70003B92
+	0x0F122000,    // 70003B94
+	0x0F12F000,    // 70003B96
+	0x0F12F975,    // 70003B98
+	0x0F128B20,    // 70003B9A
+	0x0F122201,    // 70003B9C
+	0x0F122180,    // 70003B9E
+	0x0F12F000,    // 70003BA0
+	0x0F12F978,    // 70003BA2
+	0x0F128320,    // 70003BA4
+	0x0F120028,    // 70003BA6
+	0x0F12F000,    // 70003BA8
+	0x0F12F97C,    // 70003BAA
+	0x0F12E55C,    // 70003BAC
+	0x0F12B570,    // 70003BAE
+	0x0F124A38,    // 70003BB0
+	0x0F124836,    // 70003BB2
+	0x0F123220,    // 70003BB4
+	0x0F128A91,    // 70003BB6
+	0x0F1269C0,    // 70003BB8
+	0x0F1226FF,    // 70003BBA
+	0x0F124D31,    // 70003BBC
+	0x0F121D76,    // 70003BBE
+	0x0F124288,    // 70003BC0
+	0x0F12D927,    // 70003BC2
+	0x0F1288E8,    // 70003BC4
+	0x0F1242B0,    // 70003BC6
+	0x0F12D024,    // 70003BC8
+	0x0F124837,    // 70003BCA
+	0x0F124937,    // 70003BCC
+	0x0F127883,    // 70003BCE
+	0x0F120008,    // 70003BD0
+	0x0F1230FF,    // 70003BD2
+	0x0F1231FF,    // 70003BD4
+	0x0F124C36,    // 70003BD6
+	0x0F1230E1,    // 70003BD8
+	0x0F1231C1,    // 70003BDA
+	0x0F128800,    // 70003BDC
+	0x0F128BC9,    // 70003BDE
+	0x0F1269A4,    // 70003BE0
+	0x0F122B00,    // 70003BE2
+	0x0F12D00B,    // 70003BE4
+	0x0F1289D2,    // 70003BE6
+	0x0F122A00,    // 70003BE8
+	0x0F12D013,    // 70003BEA
+	0x0F124350,    // 70003BEC
+	0x0F12F000,    // 70003BEE
+	0x0F12F8E3,    // 70003BF0
+	0x0F121C40,    // 70003BF2
+	0x0F120400,    // 70003BF4
+	0x0F120C00,    // 70003BF6
+	0x0F12F000,    // 70003BF8
+	0x0F12F95C,    // 70003BFA
+	0x0F12E00A,    // 70003BFC
+	0x0F128A12,    // 70003BFE
+	0x0F122A00,    // 70003C00
+	0x0F12D007,    // 70003C02
+	0x0F124350,    // 70003C04
+	0x0F12F000,    // 70003C06
+	0x0F12F8D7,    // 70003C08
+	0x0F121C40,    // 70003C0A
+	0x0F120400,    // 70003C0C
+	0x0F120C00,    // 70003C0E
+	0x0F12F000,    // 70003C10
+	0x0F12F950,    // 70003C12
+	0x0F12F000,    // 70003C14
+	0x0F12F956,    // 70003C16
+	0x0F1288E8,    // 70003C18
+	0x0F1242B0,    // 70003C1A
+	0x0F12D103,    // 70003C1C
+	0x0F124925,    // 70003C1E
+	0x0F1220FF,    // 70003C20
+	0x0F121C40,    // 70003C22
+	0x0F128048,    // 70003C24
+	0x0F12E51F,    // 70003C26
+	0x0F124770,    // 70003C28
+	0x0F12B570,    // 70003C2A
+	0x0F120005,    // 70003C2C
+	0x0F126828,    // 70003C2E
+	0x0F124E16,    // 70003C30
+	0x0F128C31,    // 70003C32
+	0x0F12180C,    // 70003C34
+	0x0F128871,    // 70003C36
+	0x0F122900,    // 70003C38
+	0x0F12D003,    // 70003C3A
+	0x0F120021,    // 70003C3C
+	0x0F12F000,    // 70003C3E
+	0x0F12F949,    // 70003C40
+	0x0F120004,    // 70003C42
+	0x0F124812,    // 70003C44
+	0x0F126976,    // 70003C46
+	0x0F126B00,    // 70003C48
+	0x0F126B40,    // 70003C4A
+	0x0F124286,    // 70003C4C
+	0x0F12D800,    // 70003C4E
+	0x0F120006,    // 70003C50
+	0x0F122101,    // 70003C52
+	0x0F120030,    // 70003C54
+	0x0F12F000,    // 70003C56
+	0x0F12F945,    // 70003C58
+	0x0F120001,    // 70003C5A
+	0x0F12480D,    // 70003C5C
+	0x0F123020,    // 70003C5E
+	0x0F128A40,    // 70003C60
+	0x0F122800,    // 70003C62
+	0x0F12D005,    // 70003C64
+	0x0F120020,    // 70003C66
+	0x0F12428C,    // 70003C68
+	0x0F12D800,    // 70003C6A
+	0x0F120008,    // 70003C6C
+	0x0F126028,    // 70003C6E
+	0x0F12E4FA,    // 70003C70
+	0x0F120020,    // 70003C72
+	0x0F1242B4,    // 70003C74
+	0x0F12D800,    // 70003C76
+	0x0F120030,    // 70003C78
+	0x0F122101,    // 70003C7A
+	0x0F12F000,    // 70003C7C
+	0x0F12F932,    // 70003C7E
+	0x0F126028,    // 70003C80
+	0x0F12E4F1,    // 70003C82
+	0x0F1231A0,    // 70003C84
+	0x0F127000,    // 70003C86
+	0x0F1229E4,    // 70003C88
+	0x0F127000,    // 70003C8A
+	0x0F121E3C,    // 70003C8C
+	0x0F127000,    // 70003C8E
+	0x0F1221A4,    // 70003C90
+	0x0F127000,    // 70003C92
+	0x0F123FC8,    // 70003C94
+	0x0F127000,    // 70003C96
+	0x0F12E200,    // 70003C98
+	0x0F12D000,    // 70003C9A
+	0x0F122EA8,    // 70003C9C
+	0x0F127000,    // 70003C9E
+	0x0F12B040,    // 70003CA0
+	0x0F12D000,    // 70003CA2
+	0x0F12323C,    // 70003CA4
+	0x0F127000,    // 70003CA6
+	0x0F121E84,    // 70003CA8
+	0x0F127000,    // 70003CAA
+	0x0F122024,    // 70003CAC
+	0x0F127000,    // 70003CAE
+	0x0F120080,    // 70003CB0
+	0x0F127000,    // 70003CB2
+	0x0F12C100,    // 70003CB4
+	0x0F12D000,    // 70003CB6
+	0x0F124778,    // 70003CB8
+	0x0F1246C0,    // 70003CBA
+	0x0F12C000,    // 70003CBC
+	0x0F12E59F,    // 70003CBE
+	0x0F12FF1C,    // 70003CC0
+	0x0F12E12F,    // 70003CC2
+	0x0F121F63,    // 70003CC4
+	0x0F120001,    // 70003CC6
+	0x0F124778,    // 70003CC8
+	0x0F1246C0,    // 70003CCA
+	0x0F12C000,    // 70003CCC
+	0x0F12E59F,    // 70003CCE
+	0x0F12FF1C,    // 70003CD0
+	0x0F12E12F,    // 70003CD2
+	0x0F121EDF,    // 70003CD4
+	0x0F120001,    // 70003CD6
+	0x0F124778,    // 70003CD8
+	0x0F1246C0,    // 70003CDA
+	0x0F12C000,    // 70003CDC
+	0x0F12E59F,    // 70003CDE
+	0x0F12FF1C,    // 70003CE0
+	0x0F12E12F,    // 70003CE2
+	0x0F12495F,    // 70003CE4
+	0x0F120000,    // 70003CE6
+	0x0F124778,    // 70003CE8
+	0x0F1246C0,    // 70003CEA
+	0x0F12C000,    // 70003CEC
+	0x0F12E59F,    // 70003CEE
+	0x0F12FF1C,    // 70003CF0
+	0x0F12E12F,    // 70003CF2
+	0x0F12E403,    // 70003CF4
+	0x0F120000,    // 70003CF6
+	0x0F124778,    // 70003CF8
+	0x0F1246C0,    // 70003CFA
+	0x0F12C000,    // 70003CFC
+	0x0F12E59F,    // 70003CFE
+	0x0F12FF1C,    // 70003D00
+	0x0F12E12F,    // 70003D02
+	0x0F1224B3,    // 70003D04
+	0x0F120001,    // 70003D06
+	0x0F124778,    // 70003D08
+	0x0F1246C0,    // 70003D0A
+	0x0F12C000,    // 70003D0C
+	0x0F12E59F,    // 70003D0E
+	0x0F12FF1C,    // 70003D10
+	0x0F12E12F,    // 70003D12
+	0x0F12EECD,    // 70003D14
+	0x0F120000,    // 70003D16
+	0x0F124778,    // 70003D18
+	0x0F1246C0,    // 70003D1A
+	0x0F12C000,    // 70003D1C
+	0x0F12E59F,    // 70003D1E
+	0x0F12FF1C,    // 70003D20
+	0x0F12E12F,    // 70003D22
+	0x0F12F049,    // 70003D24
+	0x0F120000,    // 70003D26
+	0x0F124778,    // 70003D28
+	0x0F1246C0,    // 70003D2A
+	0x0F12C000,    // 70003D2C
+	0x0F12E59F,    // 70003D2E
+	0x0F12FF1C,    // 70003D30
+	0x0F12E12F,    // 70003D32
+	0x0F1212DF,    // 70003D34
+	0x0F120000,    // 70003D36
+	0x0F124778,    // 70003D38
+	0x0F1246C0,    // 70003D3A
+	0x0F12C000,    // 70003D3C
+	0x0F12E59F,    // 70003D3E
+	0x0F12FF1C,    // 70003D40
+	0x0F12E12F,    // 70003D42
+	0x0F12F05B,    // 70003D44
+	0x0F120000,    // 70003D46
+	0x0F124778,    // 70003D48
+	0x0F1246C0,    // 70003D4A
+	0x0F12C000,    // 70003D4C
+	0x0F12E59F,    // 70003D4E
+	0x0F12FF1C,    // 70003D50
+	0x0F12E12F,    // 70003D52
+	0x0F12F07B,    // 70003D54
+	0x0F120000,    // 70003D56
+	0x0F124778,    // 70003D58
+	0x0F1246C0,    // 70003D5A
+	0x0F12C000,    // 70003D5C
+	0x0F12E59F,    // 70003D5E
+	0x0F12FF1C,    // 70003D60
+	0x0F12E12F,    // 70003D62
+	0x0F12FE6D,    // 70003D64
+	0x0F120000,    // 70003D66
+	0x0F124778,    // 70003D68
+	0x0F1246C0,    // 70003D6A
+	0x0F12C000,    // 70003D6C
+	0x0F12E59F,    // 70003D6E
+	0x0F12FF1C,    // 70003D70
+	0x0F12E12F,    // 70003D72
+	0x0F123295,    // 70003D74
+	0x0F120000,    // 70003D76
+	0x0F124778,    // 70003D78
+	0x0F1246C0,    // 70003D7A
+	0x0F12C000,    // 70003D7C
+	0x0F12E59F,    // 70003D7E
+	0x0F12FF1C,    // 70003D80
+	0x0F12E12F,    // 70003D82
+	0x0F12234F,    // 70003D84
+	0x0F120000,    // 70003D86
+	0x0F124778,    // 70003D88
+	0x0F1246C0,    // 70003D8A
+	0x0F12C000,    // 70003D8C
+	0x0F12E59F,    // 70003D8E
+	0x0F12FF1C,    // 70003D90
+	0x0F12E12F,    // 70003D92
+	0x0F124521,    // 70003D94
+	0x0F120000,    // 70003D96
+	0x0F124778,    // 70003D98
+	0x0F1246C0,    // 70003D9A
+	0x0F12C000,    // 70003D9C
+	0x0F12E59F,    // 70003D9E
+	0x0F12FF1C,    // 70003DA0
+	0x0F12E12F,    // 70003DA2
+	0x0F127C0D,    // 70003DA4
+	0x0F120000,    // 70003DA6
+	0x0F124778,    // 70003DA8
+	0x0F1246C0,    // 70003DAA
+	0x0F12C000,    // 70003DAC
+	0x0F12E59F,    // 70003DAE
+	0x0F12FF1C,    // 70003DB0
+	0x0F12E12F,    // 70003DB2
+	0x0F127C2B,    // 70003DB4
+	0x0F120000,    // 70003DB6
+	0x0F124778,    // 70003DB8
+	0x0F1246C0,    // 70003DBA
+	0x0F12F004,    // 70003DBC
+	0x0F12E51F,    // 70003DBE
+	0x0F1224C4,    // 70003DC0
+	0x0F120001,    // 70003DC2
+	0x0F124778,    // 70003DC4
+	0x0F1246C0,    // 70003DC6
+	0x0F12C000,    // 70003DC8
+	0x0F12E59F,    // 70003DCA
+	0x0F12FF1C,    // 70003DCC
+	0x0F12E12F,    // 70003DCE
+	0x0F123183,    // 70003DD0
+	0x0F120000,    // 70003DD2
+	0x0F124778,    // 70003DD4
+	0x0F1246C0,    // 70003DD6
+	0x0F12C000,    // 70003DD8
+	0x0F12E59F,    // 70003DDA
+	0x0F12FF1C,    // 70003DDC
+	0x0F12E12F,    // 70003DDE
+	0x0F12302F,    // 70003DE0
+	0x0F120000,    // 70003DE2
+	0x0F124778,    // 70003DE4
+	0x0F1246C0,    // 70003DE6
+	0x0F12C000,    // 70003DE8
+	0x0F12E59F,    // 70003DEA
+	0x0F12FF1C,    // 70003DEC
+	0x0F12E12F,    // 70003DEE
+	0x0F12EF07,    // 70003DF0
+	0x0F120000,    // 70003DF2
+	0x0F124778,    // 70003DF4
+	0x0F1246C0,    // 70003DF6
+	0x0F12C000,    // 70003DF8
+	0x0F12E59F,    // 70003DFA
+	0x0F12FF1C,    // 70003DFC
+	0x0F12E12F,    // 70003DFE
+	0x0F1248FB,    // 70003E00
+	0x0F120000,    // 70003E02
+	0x0F124778,    // 70003E04
+	0x0F1246C0,    // 70003E06
+	0x0F12C000,    // 70003E08
+	0x0F12E59F,    // 70003E0A
+	0x0F12FF1C,    // 70003E0C
+	0x0F12E12F,    // 70003E0E
+	0x0F12F0B1,    // 70003E10
+	0x0F120000,    // 70003E12
+	0x0F124778,    // 70003E14
+	0x0F1246C0,    // 70003E16
+	0x0F12C000,    // 70003E18
+	0x0F12E59F,    // 70003E1A
+	0x0F12FF1C,    // 70003E1C
+	0x0F12E12F,    // 70003E1E
+	0x0F12EEDF,    // 70003E20
+	0x0F120000,    // 70003E22
+	0x0F124778,    // 70003E24
+	0x0F1246C0,    // 70003E26
+	0x0F12C000,    // 70003E28
+	0x0F12E59F,    // 70003E2A
+	0x0F12FF1C,    // 70003E2C
+	0x0F12E12F,    // 70003E2E
+	0x0F12AEF1,    // 70003E30
+	0x0F120000,    // 70003E32
+	0x0F124778,    // 70003E34
+	0x0F1246C0,    // 70003E36
+	0x0F12C000,    // 70003E38
+	0x0F12E59F,    // 70003E3A
+	0x0F12FF1C,    // 70003E3C
+	0x0F12E12F,    // 70003E3E
+	0x0F1239DF,    // 70003E40
+	0x0F120000,    // 70003E42
+	0x0F124778,    // 70003E44
+	0x0F1246C0,    // 70003E46
+	0x0F12C000,    // 70003E48
+	0x0F12E59F,    // 70003E4A
+	0x0F12FF1C,    // 70003E4C
+	0x0F12E12F,    // 70003E4E
+	0x0F126177,    // 70003E50
+	0x0F120000,    // 70003E52
+	0x0F124778,    // 70003E54
+	0x0F1246C0,    // 70003E56
+	0x0F12C000,    // 70003E58
+	0x0F12E59F,    // 70003E5A
+	0x0F12FF1C,    // 70003E5C
+	0x0F12E12F,    // 70003E5E
+	0x0F12424F,    // 70003E60
+	0x0F120000,    // 70003E62
+	0x0F124778,    // 70003E64
+	0x0F1246C0,    // 70003E66
+	0x0F12C000,    // 70003E68
+	0x0F12E59F,    // 70003E6A
+	0x0F12FF1C,    // 70003E6C
+	0x0F12E12F,    // 70003E6E
+	0x0F123F0D,    // 70003E70
+	0x0F120000,    // 70003E72
+	0x0F124778,    // 70003E74
+	0x0F1246C0,    // 70003E76
+	0x0F12C000,    // 70003E78
+	0x0F12E59F,    // 70003E7A
+	0x0F12FF1C,    // 70003E7C
+	0x0F12E12F,    // 70003E7E
+	0x0F1202B9,    // 70003E80
+	0x0F120001,    // 70003E82
+	0x0F124778,    // 70003E84
+	0x0F1246C0,    // 70003E86
+	0x0F12C000,    // 70003E88
+	0x0F12E59F,    // 70003E8A
+	0x0F12FF1C,    // 70003E8C
+	0x0F12E12F,    // 70003E8E
+	0x0F12FE45,    // 70003E90
+	0x0F120000,    // 70003E92
+	0x0F124778,    // 70003E94
+	0x0F1246C0,    // 70003E96
+	0x0F12C000,    // 70003E98
+	0x0F12E59F,    // 70003E9A
+	0x0F12FF1C,    // 70003E9C
+	0x0F12E12F,    // 70003E9E
+	0x0F1232A7,    // 70003EA0
+	0x0F120000,    // 70003EA2
+	0x0F124778,    // 70003EA4
+	0x0F1246C0,    // 70003EA6
+	0x0F12C000,    // 70003EA8
+	0x0F12E59F,    // 70003EAA
+	0x0F12FF1C,    // 70003EAC
+	0x0F12E12F,    // 70003EAE
+	0x0F12E8AD,    // 70003EB0
+	0x0F120000,    // 70003EB2
+	0x0F124778,    // 70003EB4
+	0x0F1246C0,    // 70003EB6
+	0x0F12C000,    // 70003EB8
+	0x0F12E59F,    // 70003EBA
+	0x0F12FF1C,    // 70003EBC
+	0x0F12E12F,    // 70003EBE
+	0x0F1224B9,    // 70003EC0
+	0x0F120001,    // 70003EC2
+	0x0F124778,    // 70003EC4
+	0x0F1246C0,    // 70003EC6
+	0x0F12C000,    // 70003EC8
+	0x0F12E59F,    // 70003ECA
+	0x0F12FF1C,    // 70003ECC
+	0x0F12E12F,    // 70003ECE
+	0x0F1202EB,    // 70003ED0
+	0x0F120001,    // 70003ED2
+	0x0F124778,    // 70003ED4
+	0x0F1246C0,    // 70003ED6
+	0x0F12C000,    // 70003ED8
+	0x0F12E59F,    // 70003EDA
+	0x0F12FF1C,    // 70003EDC
+	0x0F12E12F,    // 70003EDE
+	0x0F123EC9,    // 70003EE0
+	0x0F120000,    // 70003EE2
+	0x0F124778,    // 70003EE4
+	0x0F1246C0,    // 70003EE6
+	0x0F12C000,    // 70003EE8
+	0x0F12E59F,    // 70003EEA
+	0x0F12FF1C,    // 70003EEC
+	0x0F12E12F,    // 70003EEE
+	0x0F126123,    // 70003EF0
+	0x0F120000,    // 70003EF2
+	// End of Patch Data(Last : 70003EF2h)
+	// Total Size 2504 (0x09C8)
+	// Addr : 352C , Size : 2502(9C6h)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	// 	TNP_GAS_ALPHA_OTP
+	// 	TNP_FR_ACCURATE_DYNAMIC
+	// 	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F120035,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F12024C,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12021E,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// Analog & APS settings         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// This register is for FACTORY ONLY. If you change it without prior notification         //
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //         //         //         //         //         //
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120020,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0004                  //extend Forbidden area line
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+	0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120500, //REG_0TC_PCFG_usWidth
+	0x0F120400, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+	0x0F120535, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+	0x0F12029A, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#else
+	0x0F120000, //REG_0TC_PCFG_uPrevMirror
+	0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120005,                   //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+	0x0F123200, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123200, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123200, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123200, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123200, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123200, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F124000,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120710, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+	};
+
+
+static const u32 s5k5ccgx_hd_init_reg[] =
+{
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000                            //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A, //p10
+	// Start of Patch data
+	0x00287000,
+	/*++ Add ESD */
+	0x002A0150,
+	0x0F12AAAA,
+	/*-- Add ESD */
+	0x002A352C,
+0x0F12B5F8,    // 7000352C
+0x0F124A28,    // 7000352E
+0x0F124928,    // 70003530
+0x0F124829,    // 70003532
+0x0F124B29,    // 70003534
+	0x0F122500, // 70003536
+	0x0F12801D, // 70003538
+	0x0F12C004, // 7000353A
+	0x0F126001, // 7000353C
+0x0F124928,    // 7000353E
+0x0F124828,    // 70003540
+	0x0F12F000, // 70003542
+0x0F12FBB9,    // 70003544
+0x0F124928,    // 70003546
+0x0F124828,    // 70003548
+	0x0F12F000, // 7000354A
+0x0F12FBB5,    // 7000354C
+0x0F124828,    // 7000354E
+0x0F124E28,    // 70003550
+	0x0F126430, // 70003552
+0x0F124928,    // 70003554
+0x0F124829,    // 70003556
+	0x0F12F000, // 70003558
+0x0F12FBAE,    // 7000355A
+0x0F124828,    // 7000355C
+0x0F120037,    // 7000355E
+0x0F123780,    // 70003560
+0x0F126178,    // 70003562
+0x0F124C27,    // 70003564
+	0x0F128365, // 70003566
+0x0F124927,    // 70003568
+0x0F124828,    // 7000356A
+	0x0F12F000, // 7000356C
+0x0F12FBA4,    // 7000356E
+0x0F124927,    // 70003570
+0x0F124828,    // 70003572
+	0x0F12F000, // 70003574
+0x0F12FBA0,    // 70003576
+0x0F124927,    // 70003578
+0x0F124828,    // 7000357A
+	0x0F12F000, // 7000357C
+0x0F12FB9C,    // 7000357E
+0x0F124927,    // 70003580
+0x0F124828,    // 70003582
+	0x0F12F000, // 70003584
+0x0F12FB98,    // 70003586
+0x0F1283A5,    // 70003588
+0x0F124827,    // 7000358A
+0x0F126470,    // 7000358C
+0x0F122001,    // 7000358E
+0x0F120340,    // 70003590
+0x0F123420,    // 70003592
+0x0F128060,    // 70003594
+0x0F122085,    // 70003596
+0x0F1280A0,    // 70003598
+0x0F124824,    // 7000359A
+0x0F1280E0,    // 7000359C
+0x0F124824,    // 7000359E
+0x0F126730,    // 700035A0
+0x0F124924,    // 700035A2
+0x0F124824,    // 700035A4
+0x0F12F000,    // 700035A6
+0x0F12FB87,    // 700035A8
+0x0F1281E5,    // 700035AA
+0x0F128225,    // 700035AC
+0x0F124823,    // 700035AE
+0x0F1282A0,    // 700035B0
+0x0F124813,    // 700035B2
+0x0F126178,    // 700035B4
+0x0F122001,    // 700035B6
+0x0F128260,    // 700035B8
+0x0F124921,    // 700035BA
+0x0F124821,    // 700035BC
+0x0F12F000,    // 700035BE
+0x0F12FB7B,    // 700035C0
+0x0F124921,    // 700035C2
+0x0F124821,    // 700035C4
+0x0F12F000,    // 700035C6
+0x0F12FB77,    // 700035C8
+0x0F12BCF8,    // 700035CA
+0x0F12BC08,    // 700035CC
+0x0F124718,    // 700035CE
+0x0F1200D6,    // 700035D0
+0x0F125CC1,    // 700035D2
+0x0F12633D,    // 700035D4
+	0x0F120000, // 700035D6
+0x0F121C08,    // 700035D8
+	0x0F127000, // 700035DA
+0x0F123290,    // 700035DC
+0x0F127000,    // 700035DE
+0x0F12366F,    // 700035E0
+	0x0F127000, // 700035E2
+0x0F12D9E7,    // 700035E4
+0x0F120000,    // 700035E6
+0x0F123857,    // 700035E8
+	0x0F127000, // 700035EA
+0x0F12395D,    // 700035EC
+	0x0F120000, // 700035EE
+0x0F1238E9,    // 700035F0
+	0x0F127000, // 700035F2
+0x0F120000,    // 700035F4
+	0x0F127000, // 700035F6
+0x0F1239B5,    // 700035F8
+	0x0F127000, // 700035FA
+0x0F12F903,    // 700035FC
+	0x0F120000, // 700035FE
+0x0F123BAF,    // 70003600
+	0x0F127000, // 70003602
+0x0F123FC8,    // 70003604
+0x0F127000,    // 70003606
+0x0F1236A7,    // 70003608
+	0x0F127000, // 7000360A
+0x0F12495F,    // 7000360C
+	0x0F120000, // 7000360E
+0x0F123705,    // 70003610
+	0x0F127000, // 70003612
+0x0F12E421,    // 70003614
+0x0F120000,    // 70003616
+0x0F1237C3,    // 70003618
+	0x0F127000, // 7000361A
+0x0F12216D,    // 7000361C
+	0x0F120000, // 7000361E
+0x0F123837,    // 70003620
+	0x0F127000, // 70003622
+0x0F120179,    // 70003624
+0x0F120001,    // 70003626
+0x0F123AD9,    // 70003628
+	0x0F127000, // 7000362A
+0x0F1207FF,    // 7000362C
+	0x0F120000, // 7000362E
+0x0F123B4D,    // 70003630
+0x0F127000,    // 70003632
+0x0F123B75,    // 70003634
+	0x0F127000, // 70003636
+0x0F12E8AD,    // 70003638
+0x0F120000,    // 7000363A
+0x0F124E20,    // 7000363C
+0x0F120000,    // 7000363E
+0x0F123C29,    // 70003640
+0x0F127000,    // 70003642
+0x0F123C4D,    // 70003644
+0x0F120000,    // 70003646
+0x0F123C2B,    // 70003648
+0x0F127000,    // 7000364A
+0x0F123F0D,    // 7000364C
+0x0F120000,    // 7000364E
+0x0F12B570,    // 70003650
+0x0F12000D,    // 70003652
+0x0F124CFC,    // 70003654
+0x0F128821,    // 70003656
+0x0F12F000,    // 70003658
+0x0F12FB36,    // 7000365A
+0x0F128820,    // 7000365C
+0x0F124AFB,    // 7000365E
+0x0F120081,    // 70003660
+0x0F125055,    // 70003662
+0x0F121C40,    // 70003664
+0x0F128020,    // 70003666
+0x0F12BC70,    // 70003668
+0x0F12BC08,    // 7000366A
+0x0F124718,    // 7000366C
+0x0F126801,    // 7000366E
+0x0F120409,    // 70003670
+0x0F120C09,    // 70003672
+0x0F126840,    // 70003674
+0x0F120400,    // 70003676
+0x0F120C00,    // 70003678
+0x0F124AF5,    // 7000367A
+0x0F128992,    // 7000367C
+0x0F122A00,    // 7000367E
+0x0F12D00D,    // 70003680
+0x0F122300,    // 70003682
+0x0F121A80,    // 70003684
+0x0F12D400,    // 70003686
+0x0F120003,    // 70003688
+0x0F120418,    // 7000368A
+0x0F120C00,    // 7000368C
+0x0F124BF1,    // 7000368E
+0x0F121851,    // 70003690
+0x0F12891B,    // 70003692
+0x0F12428B,    // 70003694
+0x0F12D300,    // 70003696
+0x0F12000B,    // 70003698
+0x0F120419,    // 7000369A
+0x0F120C09,    // 7000369C
+0x0F124AEE,    // 7000369E
+0x0F128151,    // 700036A0
+0x0F128190,    // 700036A2
+0x0F124770,    // 700036A4
+0x0F12B510,    // 700036A6
+0x0F124CEC,    // 700036A8
+0x0F1248ED,    // 700036AA
+0x0F1278A1,    // 700036AC
+0x0F122900,    // 700036AE
+0x0F12D101,    // 700036B0
+0x0F1287C1,    // 700036B2
+0x0F12E004,    // 700036B4
+0x0F127AE1,    // 700036B6
+0x0F122900,    // 700036B8
+0x0F12D001,    // 700036BA
+0x0F122101,    // 700036BC
+0x0F1287C1,    // 700036BE
+0x0F12F000,    // 700036C0
+0x0F12FB0A,    // 700036C2
+0x0F1249E7,    // 700036C4
+0x0F128B08,    // 700036C6
+0x0F1206C2,    // 700036C8
+0x0F12D50A,    // 700036CA
+0x0F127AA2,    // 700036CC
+0x0F120652,    // 700036CE
+0x0F12D507,    // 700036D0
+0x0F122210,    // 700036D2
+0x0F124390,    // 700036D4
+0x0F128308,    // 700036D6
+0x0F1248E3,    // 700036D8
+0x0F127AE1,    // 700036DA
+0x0F126B00,    // 700036DC
+0x0F12F000,    // 700036DE
+0x0F12FB03,    // 700036E0
+0x0F1248DB,    // 700036E2
+0x0F1289C0,    // 700036E4
+0x0F122801,    // 700036E6
+0x0F12D109,    // 700036E8
+0x0F1278A0,    // 700036EA
+0x0F122800,    // 700036EC
+0x0F12D006,    // 700036EE
+0x0F127AE0,    // 700036F0
+0x0F122800,    // 700036F2
+0x0F12D003,    // 700036F4
+0x0F127AA0,    // 700036F6
+0x0F122140,    // 700036F8
+0x0F124308,    // 700036FA
+0x0F1272A0,    // 700036FC
+0x0F12BC10,    // 700036FE
+0x0F12BC08,    // 70003700
+0x0F124718,    // 70003702
+0x0F12B570,    // 70003704
+0x0F124DD7,    // 70003706
+0x0F124CD7,    // 70003708
+0x0F128B28,    // 7000370A
+0x0F120701,    // 7000370C
+0x0F12D507,    // 7000370E
+0x0F122108,    // 70003710
+0x0F124388,    // 70003712
+0x0F128328,    // 70003714
+0x0F1249D5,    // 70003716
+0x0F126B20,    // 70003718
+0x0F126B89,    // 7000371A
+0x0F12F000,    // 7000371C
+0x0F12FAEC,    // 7000371E
+0x0F128B28,    // 70003720
+0x0F1206C1,    // 70003722
+0x0F12D5A0,    // 70003724
+0x0F1249CD,    // 70003726
+0x0F127A8A,    // 70003728
+0x0F120652,    // 7000372A
+0x0F12D49C,    // 7000372C
+0x0F122210,    // 7000372E
+0x0F124390,    // 70003730
+0x0F128328,    // 70003732
+0x0F127AC9,    // 70003734
+0x0F126B20,    // 70003736
+0x0F12F000,    // 70003738
+0x0F12FAD6,    // 7000373A
+0x0F12E794,    // 7000373C
+0x0F12B5F8,    // 7000373E
+0x0F1249CB,    // 70003740
+0x0F128F08,    // 70003742
+0x0F12000C,    // 70003744
+0x0F123480,    // 70003746
+0x0F122800,    // 70003748
+0x0F12D000,    // 7000374A
+0x0F128360,    // 7000374C
+0x0F122000,    // 7000374E
+0x0F128708,    // 70003750
+0x0F124DC8,    // 70003752
+0x0F1226FF,    // 70003754
+0x0F128828,    // 70003756
+0x0F121C76,    // 70003758
+0x0F122702,    // 7000375A
+0x0F122803,    // 7000375C
+0x0F12D112,    // 7000375E
+0x0F128868,    // 70003760
+0x0F122800,    // 70003762
+0x0F12D10F,    // 70003764
+0x0F1288E8,    // 70003766
+0x0F122800,    // 70003768
+0x0F12D10C,    // 7000376A
+0x0F12F000,    // 7000376C
+0x0F12FACC,    // 7000376E
+0x0F122800,    // 70003770
+0x0F12D008,    // 70003772
+0x0F128B60,    // 70003774
+	0x0F122800, // 70003776
+0x0F12D001,    // 70003778
+0x0F1280EE,    // 7000377A
+0x0F1280AF,    // 7000377C
+0x0F122001,    // 7000377E
+0x0F127268,    // 70003780
+0x0F12F000,    // 70003782
+0x0F12FAC9,    // 70003784
+0x0F128828,    // 70003786
+0x0F122802,    // 70003788
+0x0F12D10E,    // 7000378A
+0x0F128868,    // 7000378C
+0x0F122800,    // 7000378E
+0x0F12D10B,    // 70003790
+	0x0F1288E8, // 70003792
+	0x0F122800, // 70003794
+0x0F12D108,    // 70003796
+0x0F128B60,    // 70003798
+0x0F122800,    // 7000379A
+0x0F12D001,    // 7000379C
+0x0F1280EE,    // 7000379E
+0x0F1280AF,    // 700037A0
+0x0F122001,    // 700037A2
+0x0F127268,    // 700037A4
+0x0F12F000,    // 700037A6
+0x0F12FAB7,    // 700037A8
+0x0F1288E8,    // 700037AA
+0x0F122800,    // 700037AC
+0x0F12D006,    // 700037AE
+0x0F121FC1,    // 700037B0
+0x0F1239FD,    // 700037B2
+0x0F12D003,    // 700037B4
+0x0F122001,    // 700037B6
+0x0F12BCF8,    // 700037B8
+0x0F12BC08,    // 700037BA
+0x0F124718,    // 700037BC
+0x0F122000,    // 700037BE
+0x0F12E7FA,    // 700037C0
+0x0F12B570,    // 700037C2
+0x0F124CAC,    // 700037C4
+0x0F128860,    // 700037C6
+0x0F122800,    // 700037C8
+0x0F12D00C,    // 700037CA
+0x0F128820,    // 700037CC
+0x0F124DA3,    // 700037CE
+	0x0F122800, // 700037D0
+0x0F12D009,    // 700037D2
+0x0F120029,    // 700037D4
+0x0F1231A0,    // 700037D6
+0x0F127AC9,    // 700037D8
+0x0F122900,    // 700037DA
+0x0F12D004,    // 700037DC
+0x0F127AA8,    // 700037DE
+0x0F122180,    // 700037E0
+0x0F124308,    // 700037E2
+0x0F1272A8,    // 700037E4
+0x0F12E73F,    // 700037E6
+0x0F122800,    // 700037E8
+0x0F12D003,    // 700037EA
+0x0F12F7FF,    // 700037EC
+0x0F12FFA7,    // 700037EE
+0x0F122800,    // 700037F0
+0x0F12D1F8,    // 700037F2
+0x0F122000,    // 700037F4
+0x0F128060,    // 700037F6
+0x0F128820,    // 700037F8
+0x0F122800,    // 700037FA
+0x0F12D003,    // 700037FC
+0x0F122008,    // 700037FE
+0x0F12F000,    // 70003800
+0x0F12FA92,    // 70003802
+0x0F12E00B,    // 70003804
+0x0F12489C,    // 70003806
+0x0F123020,    // 70003808
+0x0F128880,    // 7000380A
+0x0F122800,    // 7000380C
+0x0F12D103,    // 7000380E
+0x0F127AA8,    // 70003810
+0x0F122101,    // 70003812
+0x0F124308,    // 70003814
+0x0F1272A8,    // 70003816
+0x0F122010,    // 70003818
+0x0F12F000,    // 7000381A
+0x0F12FA85,    // 7000381C
+0x0F128820,    // 7000381E
+0x0F122800,    // 70003820
+0x0F12D1E0,    // 70003822
+0x0F12488A,    // 70003824
+0x0F1289C0,    // 70003826
+0x0F122801,    // 70003828
+0x0F12D1DC,    // 7000382A
+0x0F127AA8,    // 7000382C
+0x0F1221BF,    // 7000382E
+0x0F124008,    // 70003830
+0x0F1272A8,    // 70003832
+0x0F12E718,    // 70003834
+0x0F126800,    // 70003836
+0x0F124990,    // 70003838
+0x0F128188,    // 7000383A
+0x0F124890,    // 7000383C
+0x0F122201,    // 7000383E
+0x0F128981,    // 70003840
+0x0F124890,    // 70003842
+0x0F120252,    // 70003844
+0x0F124291,    // 70003846
+0x0F12D902,    // 70003848
+0x0F122102,    // 7000384A
+0x0F128181,    // 7000384C
+0x0F124770,    // 7000384E
+0x0F122101,    // 70003850
+0x0F128181,    // 70003852
+0x0F124770,    // 70003854
+0x0F12B5F1,    // 70003856
+0x0F124E80,    // 70003858
+0x0F128834,    // 7000385A
+0x0F122C00,    // 7000385C
+0x0F12D03F,    // 7000385E
+0x0F122001,    // 70003860
+0x0F122C08,    // 70003862
+0x0F12D000,    // 70003864
+0x0F122000,    // 70003866
+0x0F1270B0,    // 70003868
+0x0F124D7F,    // 7000386A
+0x0F122800,    // 7000386C
+0x0F12D009,    // 7000386E
+0x0F12F000,    // 70003870
+0x0F12FA62,    // 70003872
+0x0F120028,    // 70003874
+0x0F1238F0,    // 70003876
+0x0F126328,    // 70003878
+0x0F127AB0,    // 7000387A
+0x0F12217E,    // 7000387C
+0x0F124008,    // 7000387E
+0x0F1272B0,    // 70003880
+0x0F12E00F,    // 70003882
+0x0F124F7A,    // 70003884
+0x0F123780,    // 70003886
+0x0F128B78,    // 70003888
+0x0F122800,    // 7000388A
+0x0F12D005,    // 7000388C
+0x0F12F000,    // 7000388E
+0x0F12FA5B,    // 70003890
+0x0F122000,    // 70003892
+0x0F128378,    // 70003894
+0x0F124976,    // 70003896
+0x0F128708,    // 70003898
+0x0F122000,    // 7000389A
+0x0F12F000,    // 7000389C
+0x0F12FA5C,    // 7000389E
+0x0F124879,    // 700038A0
+0x0F126328,    // 700038A2
+0x0F1278B1,    // 700038A4
+0x0F122700,    // 700038A6
+0x0F120038,    // 700038A8
+0x0F122900,    // 700038AA
+0x0F12D008,    // 700038AC
+0x0F124972,    // 700038AE
+0x0F123920,    // 700038B0
+0x0F128ACA,    // 700038B2
+0x0F122A00,    // 700038B4
+0x0F12D003,    // 700038B6
+0x0F128B09,    // 700038B8
+0x0F122900,    // 700038BA
+0x0F12D000,    // 700038BC
+0x0F122001,    // 700038BE
+0x0F127170,    // 700038C0
+0x0F122C02,    // 700038C2
+0x0F12D102,    // 700038C4
+0x0F124868,    // 700038C6
+0x0F123860,    // 700038C8
+0x0F126328,    // 700038CA
+0x0F122201,    // 700038CC
+0x0F122C02,    // 700038CE
+0x0F12D000,    // 700038D0
+0x0F122200,    // 700038D2
+0x0F124861,    // 700038D4
+0x0F122110,    // 700038D6
+0x0F12300A,    // 700038D8
+0x0F12F000,    // 700038DA
+0x0F12FA45,    // 700038DC
+0x0F128037,    // 700038DE
+0x0F129900,    // 700038E0
+0x0F120020,    // 700038E2
+0x0F12600C,    // 700038E4
+0x0F12E767,    // 700038E6
+0x0F12B538,    // 700038E8
+0x0F124865,    // 700038EA
+0x0F124669,    // 700038EC
+0x0F123848,    // 700038EE
+0x0F12F000,    // 700038F0
+0x0F12FA42,    // 700038F2
+0x0F124A5E,    // 700038F4
+0x0F124862,    // 700038F6
+0x0F128F51,    // 700038F8
+0x0F122400,    // 700038FA
+0x0F123020,    // 700038FC
+0x0F122900,    // 700038FE
+0x0F12D00A,    // 70003900
+0x0F128754,    // 70003902
+0x0F126941,    // 70003904
+0x0F126451,    // 70003906
+0x0F126491,    // 70003908
+0x0F12466B,    // 7000390A
+0x0F128819,    // 7000390C
+0x0F1287D1,    // 7000390E
+0x0F12885B,    // 70003910
+0x0F120011,    // 70003912
+0x0F123140,    // 70003914
+0x0F12800B,    // 70003916
+0x0F128F91,    // 70003918
+0x0F122900,    // 7000391A
+0x0F12D002,    // 7000391C
+0x0F128794,    // 7000391E
+0x0F126940,    // 70003920
+0x0F126490,    // 70003922
+	0x0F12F000, // 70003924
+0x0F12FA30,    // 70003926
+0x0F12BC38,    // 70003928
+0x0F12BC08,    // 7000392A
+0x0F124718,    // 7000392C
+0x0F12B5F8,    // 7000392E
+0x0F124C56,    // 70003930
+0x0F1289E0,    // 70003932
+0x0F12F000,    // 70003934
+0x0F12FA30,    // 70003936
+0x0F120006,    // 70003938
+0x0F128A20,    // 7000393A
+0x0F12F000,    // 7000393C
+0x0F12FA34,    // 7000393E
+0x0F120007,    // 70003940
+0x0F12484F,    // 70003942
+0x0F124D4A,    // 70003944
+0x0F123020,    // 70003946
+0x0F126CA9,    // 70003948
+0x0F126940,    // 7000394A
+0x0F121809,    // 7000394C
+0x0F120200,    // 7000394E
+0x0F12F000,    // 70003950
+0x0F12FA32,    // 70003952
+0x0F120400,    // 70003954
+0x0F120C00,    // 70003956
+0x0F12002A,    // 70003958
+0x0F12326E,    // 7000395A
+0x0F120011,    // 7000395C
+0x0F12390A,    // 7000395E
+0x0F122305,    // 70003960
+0x0F12F000,    // 70003962
+0x0F12FA2F,    // 70003964
+0x0F124C43,    // 70003966
+0x0F1261A0,    // 70003968
+0x0F128FEB,    // 7000396A
+0x0F120002,    // 7000396C
+0x0F120031,    // 7000396E
+0x0F120018,    // 70003970
+0x0F12F000,    // 70003972
+0x0F12FA2F,    // 70003974
+0x0F12466B,    // 70003976
+0x0F120005,    // 70003978
+0x0F128018,    // 7000397A
+0x0F12483C,    // 7000397C
+0x0F1269A2,    // 7000397E
+0x0F123040,    // 70003980
+0x0F128800,    // 70003982
+0x0F120039,    // 70003984
+0x0F12F000,    // 70003986
+0x0F12FA25,    // 70003988
+0x0F12466B,    // 7000398A
+0x0F120006,    // 7000398C
+0x0F128058,    // 7000398E
+0x0F120021,    // 70003990
+0x0F129800,    // 70003992
+0x0F12311C,    // 70003994
+0x0F12F000,    // 70003996
+0x0F12FA25,    // 70003998
+0x0F124935,    // 7000399A
+0x0F123180,    // 7000399C
+0x0F12808D,    // 7000399E
+0x0F1280CE,    // 700039A0
+0x0F128BA1,    // 700039A2
+0x0F124836,    // 700039A4
+0x0F123820,    // 700039A6
+0x0F128001,    // 700039A8
+0x0F128BE1,    // 700039AA
+0x0F128041,    // 700039AC
+0x0F128C21,    // 700039AE
+0x0F128081,    // 700039B0
+0x0F12E701,    // 700039B2
+0x0F12B5F8,    // 700039B4
+0x0F124E2E,    // 700039B6
+0x0F126C70,    // 700039B8
+0x0F126CB1,    // 700039BA
+0x0F120200,    // 700039BC
+0x0F12F000,    // 700039BE
+0x0F12F9FB,    // 700039C0
+0x0F120400,    // 700039C2
+0x0F120C00,    // 700039C4
+0x0F122401,    // 700039C6
+0x0F120364,    // 700039C8
+0x0F1242A0,    // 700039CA
+0x0F12D200,    // 700039CC
+0x0F120004,    // 700039CE
+0x0F124A27,    // 700039D0
+0x0F120020,    // 700039D2
+0x0F12327E,    // 700039D4
+0x0F121F91,    // 700039D6
+0x0F122303,    // 700039D8
+0x0F12F000,    // 700039DA
+0x0F12F9F3,    // 700039DC
+0x0F120405,    // 700039DE
+0x0F120C2D,    // 700039E0
+0x0F124A23,    // 700039E2
+0x0F120020,    // 700039E4
+0x0F12325A,    // 700039E6
+0x0F120011,    // 700039E8
+0x0F12390A,    // 700039EA
+0x0F122305,    // 700039EC
+0x0F12F000,    // 700039EE
+0x0F12F9E9,    // 700039F0
+0x0F12491F,    // 700039F2
+0x0F1264C8,    // 700039F4
+0x0F12491F,    // 700039F6
+0x0F124E21,    // 700039F8
+0x0F1288C8,    // 700039FA
+0x0F122701,    // 700039FC
+0x0F122800,    // 700039FE
+0x0F12D009,    // 70003A00
+0x0F124C23,    // 70003A02
+0x0F1238FF,    // 70003A04
+0x0F121E40,    // 70003A06
+0x0F12D00A,    // 70003A08
+0x0F122804,    // 70003A0A
+0x0F12D042,    // 70003A0C
+0x0F122806,    // 70003A0E
+0x0F12D101,    // 70003A10
+0x0F122000,    // 70003A12
+0x0F1280C8,    // 70003A14
+0x0F1282B7,    // 70003A16
+0x0F122001,    // 70003A18
+0x0F12F000,    // 70003A1A
+0x0F12F9EB,    // 70003A1C
+0x0F12E6CB,    // 70003A1E
+0x0F12000D,    // 70003A20
+0x0F12724F,    // 70003A22
+0x0F122001,    // 70003A24
+0x0F12F000,    // 70003A26
+0x0F12F9ED,    // 70003A28
+0x0F12F000,    // 70003A2A
+0x0F12F9F3,    // 70003A2C
+0x0F124910,    // 70003A2E
+0x0F123148,    // 70003A30
+0x0F12C903,    // 70003A32
+0x0F124348,    // 70003A34
+0x0F120A00,    // 70003A36
+0x0F126160,    // 70003A38
+0x0F1220FF,    // 70003A3A
+0x0F121D40,    // 70003A3C
+0x0F1280E8,    // 70003A3E
+0x0F12480C,    // 70003A40
+0x0F123040,    // 70003A42
+0x0F127707,    // 70003A44
+0x0F12E7E6,    // 70003A46
+0x0F123290,    // 70003A48
+	0x0F127000, // 70003A4A
+0x0F123294,    // 70003A4C
+	0x0F127000, // 70003A4E
+0x0F1204A8,    // 70003A50
+	0x0F127000, // 70003A52
+0x0F1215DC,    // 70003A54
+	0x0F127000, // 70003A56
+0x0F125000,    // 70003A58
+0x0F12D000,    // 70003A5A
+0x0F121E84,    // 70003A5C
+	0x0F127000, // 70003A5E
+0x0F121BE4,    // 70003A60
+	0x0F127000, // 70003A62
+0x0F122EA8,    // 70003A64
+0x0F127000,    // 70003A66
+0x0F1221A4,    // 70003A68
+	0x0F127000, // 70003A6A
+0x0F120100,    // 70003A6C
+0x0F127000,    // 70003A6E
+0x0F123F48,    // 70003A70
+	0x0F127000, // 70003A72
+0x0F1231A0,    // 70003A74
+	0x0F127000, // 70003A76
+0x0F1201E8,    // 70003A78
+	0x0F127000, // 70003A7A
+0x0F12F2A0,    // 70003A7C
+0x0F12D000,    // 70003A7E
+0x0F122A44,    // 70003A80
+0x0F127000,    // 70003A82
+0x0F12F400,    // 70003A84
+0x0F12D000,    // 70003A86
+0x0F122024,    // 70003A88
+0x0F127000,    // 70003A8A
+0x0F121650,    // 70003A8C
+0x0F127000,    // 70003A8E
+0x0F122A64,    // 70003A90
+0x0F127000,    // 70003A92
+0x0F12497B,    // 70003A94
+0x0F12724F,    // 70003A96
+0x0F1220FF,    // 70003A98
+0x0F121DC0,    // 70003A9A
+0x0F1280C8,    // 70003A9C
+0x0F12F000,    // 70003A9E
+0x0F12F9C1,    // 70003AA0
+0x0F124979,    // 70003AA2
+0x0F126ACA,    // 70003AA4
+0x0F12604A,    // 70003AA6
+	0x0F122800, // 70003AA8
+0x0F12D006,    // 70003AAA
+0x0F12436A,    // 70003AAC
+0x0F120001,    // 70003AAE
+0x0F120010,    // 70003AB0
+	0x0F12F000, // 70003AB2
+0x0F12F981,    // 70003AB4
+0x0F126160,    // 70003AB6
+0x0F12E001,    // 70003AB8
+0x0F12436A,    // 70003ABA
+0x0F126162,    // 70003ABC
+0x0F128BF0,    // 70003ABE
+0x0F122800,    // 70003AC0
+0x0F12D001,    // 70003AC2
+0x0F12F7FF,    // 70003AC4
+0x0F12FF33,    // 70003AC6
+0x0F122000,    // 70003AC8
+0x0F12F000,    // 70003ACA
+0x0F12F99B,    // 70003ACC
+0x0F12496D,    // 70003ACE
+0x0F1220FF,    // 70003AD0
+0x0F121DC0,    // 70003AD2
+0x0F1280C8,    // 70003AD4
+0x0F12E79E,    // 70003AD6
+0x0F12B570,    // 70003AD8
+0x0F120004,    // 70003ADA
+0x0F12F000,    // 70003ADC
+0x0F12F9AA,    // 70003ADE
+0x0F124D6A,    // 70003AE0
+0x0F128C29,    // 70003AE2
+0x0F121A40,    // 70003AE4
+0x0F1242A0,    // 70003AE6
+0x0F12D803,    // 70003AE8
+	0x0F12F000, // 70003AEA
+0x0F12F9A3,    // 70003AEC
+0x0F128C29,    // 70003AEE
+0x0F121A44,    // 70003AF0
+0x0F120020,    // 70003AF2
+0x0F12626C,    // 70003AF4
+0x0F12F000,    // 70003AF6
+0x0F12F9A5,    // 70003AF8
+0x0F1262A8,    // 70003AFA
+0x0F12F000,    // 70003AFC
+0x0F12F9AA,    // 70003AFE
+0x0F126328,    // 70003B00
+0x0F128869,    // 70003B02
+0x0F122900,    // 70003B04
+0x0F12D000,    // 70003B06
+0x0F1262A8,    // 70003B08
+0x0F124861,    // 70003B0A
+0x0F126B00,    // 70003B0C
+0x0F128C00,    // 70003B0E
+0x0F122800,    // 70003B10
+0x0F12D117,    // 70003B12
+0x0F126AA8,    // 70003B14
+0x0F12F000,    // 70003B16
+0x0F12F9A5,    // 70003B18
+0x0F1261E8,    // 70003B1A
+0x0F12495D,    // 70003B1C
+0x0F128B8A,    // 70003B1E
+0x0F122A00,    // 70003B20
+0x0F12D00C,    // 70003B22
+0x0F128BC9,    // 70003B24
+0x0F124288,    // 70003B26
+0x0F12D90A,    // 70003B28
+0x0F12485A,    // 70003B2A
+0x0F123020,    // 70003B2C
+0x0F128800,    // 70003B2E
+0x0F1261E8,    // 70003B30
+0x0F128C29,    // 70003B32
+0x0F121A40,    // 70003B34
+0x0F1262A8,    // 70003B36
+0x0F12F000,    // 70003B38
+0x0F12F984,    // 70003B3A
+0x0F1262A8,    // 70003B3C
+0x0F12E593,    // 70003B3E
+0x0F1261E9,    // 70003B40
+0x0F12E591,    // 70003B42
+0x0F12F000,    // 70003B44
+0x0F12F976,    // 70003B46
+0x0F1261E8,    // 70003B48
+0x0F12E58D,    // 70003B4A
+0x0F12B510,    // 70003B4C
+0x0F12F000,    // 70003B4E
+0x0F12F991,    // 70003B50
+0x0F124850,    // 70003B52
+0x0F123020,    // 70003B54
+0x0F128841,    // 70003B56
+0x0F122900,    // 70003B58
+0x0F12D007,    // 70003B5A
+0x0F124A4A,    // 70003B5C
+0x0F123280,    // 70003B5E
+0x0F126953,    // 70003B60
+0x0F124A4D,    // 70003B62
+0x0F12428B,    // 70003B64
+0x0F12D202,    // 70003B66
+0x0F128880,    // 70003B68
+0x0F1281D0,    // 70003B6A
+0x0F12E5C7,    // 70003B6C
+0x0F1288C0,    // 70003B6E
+0x0F1281D0,    // 70003B70
+0x0F12E5C4,    // 70003B72
+0x0F12B570,    // 70003B74
+0x0F126800,    // 70003B76
+0x0F120605,    // 70003B78
+0x0F120E2D,    // 70003B7A
+0x0F124C47,    // 70003B7C
+0x0F128B60,    // 70003B7E
+0x0F122800,    // 70003B80
+0x0F12D010,    // 70003B82
+0x0F124846,    // 70003B84
+0x0F128A00,    // 70003B86
+0x0F1206C0,    // 70003B88
+0x0F12D50C,    // 70003B8A
+0x0F124845,    // 70003B8C
+0x0F127800,    // 70003B8E
+0x0F122800,    // 70003B90
+0x0F12D008,    // 70003B92
+0x0F122000,    // 70003B94
+0x0F12F000,    // 70003B96
+0x0F12F975,    // 70003B98
+0x0F128B20,    // 70003B9A
+0x0F122201,    // 70003B9C
+0x0F122180,    // 70003B9E
+0x0F12F000,    // 70003BA0
+0x0F12F978,    // 70003BA2
+0x0F128320,    // 70003BA4
+0x0F120028,    // 70003BA6
+0x0F12F000,    // 70003BA8
+0x0F12F97C,    // 70003BAA
+0x0F12E55C,    // 70003BAC
+0x0F12B570,    // 70003BAE
+0x0F124A38,    // 70003BB0
+0x0F124836,    // 70003BB2
+0x0F123220,    // 70003BB4
+0x0F128A91,    // 70003BB6
+0x0F1269C0,    // 70003BB8
+0x0F1226FF,    // 70003BBA
+0x0F124D31,    // 70003BBC
+0x0F121D76,    // 70003BBE
+0x0F124288,    // 70003BC0
+0x0F12D927,    // 70003BC2
+0x0F1288E8,    // 70003BC4
+0x0F1242B0,    // 70003BC6
+0x0F12D024,    // 70003BC8
+0x0F124837,    // 70003BCA
+0x0F124937,    // 70003BCC
+0x0F127883,    // 70003BCE
+0x0F120008,    // 70003BD0
+0x0F1230FF,    // 70003BD2
+0x0F1231FF,    // 70003BD4
+0x0F124C36,    // 70003BD6
+0x0F1230E1,    // 70003BD8
+0x0F1231C1,    // 70003BDA
+0x0F128800,    // 70003BDC
+0x0F128BC9,    // 70003BDE
+0x0F1269A4,    // 70003BE0
+0x0F122B00,    // 70003BE2
+0x0F12D00B,    // 70003BE4
+0x0F1289D2,    // 70003BE6
+0x0F122A00,    // 70003BE8
+0x0F12D013,    // 70003BEA
+0x0F124350,    // 70003BEC
+0x0F12F000,    // 70003BEE
+0x0F12F8E3,    // 70003BF0
+0x0F121C40,    // 70003BF2
+0x0F120400,    // 70003BF4
+0x0F120C00,    // 70003BF6
+0x0F12F000,    // 70003BF8
+0x0F12F95C,    // 70003BFA
+0x0F12E00A,    // 70003BFC
+0x0F128A12,    // 70003BFE
+0x0F122A00,    // 70003C00
+0x0F12D007,    // 70003C02
+0x0F124350,    // 70003C04
+	0x0F12F000, // 70003C06
+0x0F12F8D7,    // 70003C08
+0x0F121C40,    // 70003C0A
+0x0F120400,    // 70003C0C
+0x0F120C00,    // 70003C0E
+0x0F12F000,    // 70003C10
+0x0F12F950,    // 70003C12
+0x0F12F000,    // 70003C14
+0x0F12F956,    // 70003C16
+0x0F1288E8,    // 70003C18
+0x0F1242B0,    // 70003C1A
+0x0F12D103,    // 70003C1C
+0x0F124925,    // 70003C1E
+0x0F1220FF,    // 70003C20
+0x0F121C40,    // 70003C22
+0x0F128048,    // 70003C24
+0x0F12E51F,    // 70003C26
+0x0F124770,    // 70003C28
+0x0F12B570,    // 70003C2A
+0x0F120005,    // 70003C2C
+0x0F126828,    // 70003C2E
+0x0F124E16,    // 70003C30
+0x0F128C31,    // 70003C32
+0x0F12180C,    // 70003C34
+0x0F128871,    // 70003C36
+0x0F122900,    // 70003C38
+0x0F12D003,    // 70003C3A
+0x0F120021,    // 70003C3C
+0x0F12F000,    // 70003C3E
+0x0F12F949,    // 70003C40
+0x0F120004,    // 70003C42
+0x0F124812,    // 70003C44
+0x0F126976,    // 70003C46
+0x0F126B00,    // 70003C48
+0x0F126B40,    // 70003C4A
+0x0F124286,    // 70003C4C
+	0x0F12D800, // 70003C4E
+0x0F120006,    // 70003C50
+0x0F122101,    // 70003C52
+0x0F120030,    // 70003C54
+	0x0F12F000, // 70003C56
+0x0F12F945,    // 70003C58
+0x0F120001,    // 70003C5A
+0x0F12480D,    // 70003C5C
+0x0F123020,    // 70003C5E
+0x0F128A40,    // 70003C60
+0x0F122800,    // 70003C62
+0x0F12D005,    // 70003C64
+0x0F120020,    // 70003C66
+0x0F12428C,    // 70003C68
+0x0F12D800,    // 70003C6A
+0x0F120008,    // 70003C6C
+0x0F126028,    // 70003C6E
+0x0F12E4FA,    // 70003C70
+0x0F120020,    // 70003C72
+0x0F1242B4,    // 70003C74
+0x0F12D800,    // 70003C76
+0x0F120030,    // 70003C78
+0x0F122101,    // 70003C7A
+0x0F12F000,    // 70003C7C
+0x0F12F932,    // 70003C7E
+0x0F126028,    // 70003C80
+0x0F12E4F1,    // 70003C82
+0x0F1231A0,    // 70003C84
+0x0F127000,    // 70003C86
+0x0F1229E4,    // 70003C88
+	0x0F127000, // 70003C8A
+0x0F121E3C,    // 70003C8C
+	0x0F127000, // 70003C8E
+0x0F1221A4,    // 70003C90
+0x0F127000,    // 70003C92
+0x0F123FC8,    // 70003C94
+0x0F127000,    // 70003C96
+0x0F12E200,    // 70003C98
+	0x0F12D000, // 70003C9A
+0x0F122EA8,    // 70003C9C
+	0x0F127000, // 70003C9E
+0x0F12B040,    // 70003CA0
+0x0F12D000,    // 70003CA2
+0x0F12323C,    // 70003CA4
+	0x0F127000, // 70003CA6
+0x0F121E84,    // 70003CA8
+	0x0F127000, // 70003CAA
+0x0F122024,    // 70003CAC
+	0x0F127000, // 70003CAE
+0x0F120080,    // 70003CB0
+	0x0F127000, // 70003CB2
+0x0F12C100,    // 70003CB4
+0x0F12D000,    // 70003CB6
+0x0F124778,    // 70003CB8
+0x0F1246C0,    // 70003CBA
+0x0F12C000,    // 70003CBC
+0x0F12E59F,    // 70003CBE
+0x0F12FF1C,    // 70003CC0
+0x0F12E12F,    // 70003CC2
+0x0F121F63,    // 70003CC4
+0x0F120001,    // 70003CC6
+0x0F124778,    // 70003CC8
+0x0F1246C0,    // 70003CCA
+0x0F12C000,    // 70003CCC
+0x0F12E59F,    // 70003CCE
+0x0F12FF1C,    // 70003CD0
+0x0F12E12F,    // 70003CD2
+0x0F121EDF,    // 70003CD4
+0x0F120001,    // 70003CD6
+0x0F124778,    // 70003CD8
+0x0F1246C0,    // 70003CDA
+0x0F12C000,    // 70003CDC
+0x0F12E59F,    // 70003CDE
+0x0F12FF1C,    // 70003CE0
+0x0F12E12F,    // 70003CE2
+0x0F12495F,    // 70003CE4
+0x0F120000,    // 70003CE6
+0x0F124778,    // 70003CE8
+0x0F1246C0,    // 70003CEA
+0x0F12C000,    // 70003CEC
+0x0F12E59F,    // 70003CEE
+0x0F12FF1C,    // 70003CF0
+0x0F12E12F,    // 70003CF2
+0x0F12E403,    // 70003CF4
+0x0F120000,    // 70003CF6
+0x0F124778,    // 70003CF8
+0x0F1246C0,    // 70003CFA
+0x0F12C000,    // 70003CFC
+0x0F12E59F,    // 70003CFE
+0x0F12FF1C,    // 70003D00
+0x0F12E12F,    // 70003D02
+0x0F1224B3,    // 70003D04
+0x0F120001,    // 70003D06
+0x0F124778,    // 70003D08
+0x0F1246C0,    // 70003D0A
+0x0F12C000,    // 70003D0C
+0x0F12E59F,    // 70003D0E
+0x0F12FF1C,    // 70003D10
+0x0F12E12F,    // 70003D12
+0x0F12EECD,    // 70003D14
+0x0F120000,    // 70003D16
+0x0F124778,    // 70003D18
+0x0F1246C0,    // 70003D1A
+0x0F12C000,    // 70003D1C
+0x0F12E59F,    // 70003D1E
+0x0F12FF1C,    // 70003D20
+0x0F12E12F,    // 70003D22
+0x0F12F049,    // 70003D24
+0x0F120000,    // 70003D26
+0x0F124778,    // 70003D28
+0x0F1246C0,    // 70003D2A
+0x0F12C000,    // 70003D2C
+0x0F12E59F,    // 70003D2E
+0x0F12FF1C,    // 70003D30
+0x0F12E12F,    // 70003D32
+0x0F1212DF,    // 70003D34
+0x0F120000,    // 70003D36
+0x0F124778,    // 70003D38
+0x0F1246C0,    // 70003D3A
+0x0F12C000,    // 70003D3C
+0x0F12E59F,    // 70003D3E
+0x0F12FF1C,    // 70003D40
+0x0F12E12F,    // 70003D42
+0x0F12F05B,    // 70003D44
+0x0F120000,    // 70003D46
+0x0F124778,    // 70003D48
+0x0F1246C0,    // 70003D4A
+0x0F12C000,    // 70003D4C
+0x0F12E59F,    // 70003D4E
+0x0F12FF1C,    // 70003D50
+0x0F12E12F,    // 70003D52
+0x0F12F07B,    // 70003D54
+0x0F120000,    // 70003D56
+0x0F124778,    // 70003D58
+0x0F1246C0,    // 70003D5A
+0x0F12C000,    // 70003D5C
+0x0F12E59F,    // 70003D5E
+0x0F12FF1C,    // 70003D60
+0x0F12E12F,    // 70003D62
+0x0F12FE6D,    // 70003D64
+0x0F120000,    // 70003D66
+0x0F124778,    // 70003D68
+0x0F1246C0,    // 70003D6A
+0x0F12C000,    // 70003D6C
+0x0F12E59F,    // 70003D6E
+0x0F12FF1C,    // 70003D70
+0x0F12E12F,    // 70003D72
+0x0F123295,    // 70003D74
+0x0F120000,    // 70003D76
+0x0F124778,    // 70003D78
+0x0F1246C0,    // 70003D7A
+0x0F12C000,    // 70003D7C
+0x0F12E59F,    // 70003D7E
+0x0F12FF1C,    // 70003D80
+0x0F12E12F,    // 70003D82
+0x0F12234F,    // 70003D84
+0x0F120000,    // 70003D86
+0x0F124778,    // 70003D88
+0x0F1246C0,    // 70003D8A
+0x0F12C000,    // 70003D8C
+0x0F12E59F,    // 70003D8E
+0x0F12FF1C,    // 70003D90
+0x0F12E12F,    // 70003D92
+0x0F124521,    // 70003D94
+0x0F120000,    // 70003D96
+0x0F124778,    // 70003D98
+0x0F1246C0,    // 70003D9A
+0x0F12C000,    // 70003D9C
+0x0F12E59F,    // 70003D9E
+0x0F12FF1C,    // 70003DA0
+0x0F12E12F,    // 70003DA2
+0x0F127C0D,    // 70003DA4
+0x0F120000,    // 70003DA6
+0x0F124778,    // 70003DA8
+0x0F1246C0,    // 70003DAA
+0x0F12C000,    // 70003DAC
+0x0F12E59F,    // 70003DAE
+0x0F12FF1C,    // 70003DB0
+0x0F12E12F,    // 70003DB2
+0x0F127C2B,    // 70003DB4
+0x0F120000,    // 70003DB6
+0x0F124778,    // 70003DB8
+0x0F1246C0,    // 70003DBA
+0x0F12F004,    // 70003DBC
+0x0F12E51F,    // 70003DBE
+0x0F1224C4,    // 70003DC0
+0x0F120001,    // 70003DC2
+0x0F124778,    // 70003DC4
+0x0F1246C0,    // 70003DC6
+0x0F12C000,    // 70003DC8
+0x0F12E59F,    // 70003DCA
+0x0F12FF1C,    // 70003DCC
+0x0F12E12F,    // 70003DCE
+0x0F123183,    // 70003DD0
+0x0F120000,    // 70003DD2
+0x0F124778,    // 70003DD4
+0x0F1246C0,    // 70003DD6
+0x0F12C000,    // 70003DD8
+0x0F12E59F,    // 70003DDA
+0x0F12FF1C,    // 70003DDC
+0x0F12E12F,    // 70003DDE
+0x0F12302F,    // 70003DE0
+0x0F120000,    // 70003DE2
+0x0F124778,    // 70003DE4
+0x0F1246C0,    // 70003DE6
+0x0F12C000,    // 70003DE8
+0x0F12E59F,    // 70003DEA
+0x0F12FF1C,    // 70003DEC
+0x0F12E12F,    // 70003DEE
+0x0F12EF07,    // 70003DF0
+0x0F120000,    // 70003DF2
+0x0F124778,    // 70003DF4
+0x0F1246C0,    // 70003DF6
+0x0F12C000,    // 70003DF8
+0x0F12E59F,    // 70003DFA
+0x0F12FF1C,    // 70003DFC
+0x0F12E12F,    // 70003DFE
+0x0F1248FB,    // 70003E00
+0x0F120000,    // 70003E02
+0x0F124778,    // 70003E04
+0x0F1246C0,    // 70003E06
+0x0F12C000,    // 70003E08
+0x0F12E59F,    // 70003E0A
+0x0F12FF1C,    // 70003E0C
+0x0F12E12F,    // 70003E0E
+0x0F12F0B1,    // 70003E10
+0x0F120000,    // 70003E12
+0x0F124778,    // 70003E14
+0x0F1246C0,    // 70003E16
+0x0F12C000,    // 70003E18
+0x0F12E59F,    // 70003E1A
+0x0F12FF1C,    // 70003E1C
+0x0F12E12F,    // 70003E1E
+0x0F12EEDF,    // 70003E20
+0x0F120000,    // 70003E22
+0x0F124778,    // 70003E24
+0x0F1246C0,    // 70003E26
+0x0F12C000,    // 70003E28
+0x0F12E59F,    // 70003E2A
+0x0F12FF1C,    // 70003E2C
+0x0F12E12F,    // 70003E2E
+0x0F12AEF1,    // 70003E30
+0x0F120000,    // 70003E32
+0x0F124778,    // 70003E34
+0x0F1246C0,    // 70003E36
+0x0F12C000,    // 70003E38
+0x0F12E59F,    // 70003E3A
+0x0F12FF1C,    // 70003E3C
+0x0F12E12F,    // 70003E3E
+0x0F1239DF,    // 70003E40
+0x0F120000,    // 70003E42
+0x0F124778,    // 70003E44
+0x0F1246C0,    // 70003E46
+0x0F12C000,    // 70003E48
+0x0F12E59F,    // 70003E4A
+0x0F12FF1C,    // 70003E4C
+0x0F12E12F,    // 70003E4E
+0x0F126177,    // 70003E50
+0x0F120000,    // 70003E52
+0x0F124778,    // 70003E54
+0x0F1246C0,    // 70003E56
+0x0F12C000,    // 70003E58
+0x0F12E59F,    // 70003E5A
+0x0F12FF1C,    // 70003E5C
+0x0F12E12F,    // 70003E5E
+0x0F12424F,    // 70003E60
+0x0F120000,    // 70003E62
+0x0F124778,    // 70003E64
+0x0F1246C0,    // 70003E66
+0x0F12C000,    // 70003E68
+0x0F12E59F,    // 70003E6A
+0x0F12FF1C,    // 70003E6C
+0x0F12E12F,    // 70003E6E
+0x0F123F0D,    // 70003E70
+0x0F120000,    // 70003E72
+0x0F124778,    // 70003E74
+0x0F1246C0,    // 70003E76
+0x0F12C000,    // 70003E78
+0x0F12E59F,    // 70003E7A
+0x0F12FF1C,    // 70003E7C
+0x0F12E12F,    // 70003E7E
+0x0F1202B9,    // 70003E80
+0x0F120001,    // 70003E82
+0x0F124778,    // 70003E84
+0x0F1246C0,    // 70003E86
+0x0F12C000,    // 70003E88
+0x0F12E59F,    // 70003E8A
+0x0F12FF1C,    // 70003E8C
+0x0F12E12F,    // 70003E8E
+0x0F12FE45,    // 70003E90
+0x0F120000,    // 70003E92
+0x0F124778,    // 70003E94
+0x0F1246C0,    // 70003E96
+0x0F12C000,    // 70003E98
+0x0F12E59F,    // 70003E9A
+0x0F12FF1C,    // 70003E9C
+0x0F12E12F,    // 70003E9E
+0x0F1232A7,    // 70003EA0
+0x0F120000,    // 70003EA2
+0x0F124778,    // 70003EA4
+0x0F1246C0,    // 70003EA6
+0x0F12C000,    // 70003EA8
+0x0F12E59F,    // 70003EAA
+0x0F12FF1C,    // 70003EAC
+0x0F12E12F,    // 70003EAE
+0x0F12E8AD,    // 70003EB0
+0x0F120000,    // 70003EB2
+0x0F124778,    // 70003EB4
+0x0F1246C0,    // 70003EB6
+0x0F12C000,    // 70003EB8
+0x0F12E59F,    // 70003EBA
+0x0F12FF1C,    // 70003EBC
+0x0F12E12F,    // 70003EBE
+0x0F1224B9,    // 70003EC0
+0x0F120001,    // 70003EC2
+0x0F124778,    // 70003EC4
+0x0F1246C0,    // 70003EC6
+0x0F12C000,    // 70003EC8
+0x0F12E59F,    // 70003ECA
+0x0F12FF1C,    // 70003ECC
+0x0F12E12F,    // 70003ECE
+0x0F1202EB,    // 70003ED0
+0x0F120001,    // 70003ED2
+0x0F124778,    // 70003ED4
+0x0F1246C0,    // 70003ED6
+0x0F12C000,    // 70003ED8
+0x0F12E59F,    // 70003EDA
+0x0F12FF1C,    // 70003EDC
+0x0F12E12F,    // 70003EDE
+0x0F123EC9,    // 70003EE0
+0x0F120000,    // 70003EE2
+0x0F124778,    // 70003EE4
+0x0F1246C0,    // 70003EE6
+0x0F12C000,    // 70003EE8
+0x0F12E59F,    // 70003EEA
+0x0F12FF1C,    // 70003EEC
+0x0F12E12F,    // 70003EEE
+0x0F126123,    // 70003EF0
+0x0F120000,    // 70003EF2
+// End of Patch Data(Last : 70003EF2h)
+// Total Size 2504 (0x09C8)
+// Addr : 352C , Size : 2502(9C6h)
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	// 	TNP_GAS_ALPHA_OTP
+	// 	TNP_FR_ACCURATE_DYNAMIC
+	// 	TNP_ADLC_TUNE
+
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007, // clks_src_gf_force_enable
+
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120001, // on/off AFIT by NB option
+
+	0x0F120005, //0005                 // NormBR[0]
+	0x0F120066, //00C8                 // NormBR[1]
+	0x0F1200C8, //00F4                 // NormBR[2]
+	0x0F120320, //0320                 // NormBR[3]
+	0x0F120375, //0375                 // NormBR[4]
+
+
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	                  // TNP_Regs_PreflashStart
+	0x0F120000,	                  // TNP_Regs_PreflashEnd
+	0x0F120260,	                  // TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	                  // BR Tuning
+	0x0F120100,	                  // TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	                  // TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	                  // WP Tuning
+	0x0F120040,	                  // TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	                  // TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	                  // T_BR tune
+	0x0F120150,	                  // TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	                  //TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F120035,
+
+	0x002A0430,	                  //REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	                  //TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F120240, //0244 0258 AWB R point                            //0258 0245 0258
+	0x0F120244, //024D 0220 AWB B point                            //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// Analog & APS settings         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+	// This register is for FACTORY ONLY. If you change it without prior notification         //
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //         //         //         //         //         //
+	//         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         //         ///
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001,          // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+	0x002AF42E,
+	0x0F120406,          // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+	0x002AF132,
+	0x0F124006,	         //ki 0413                   // tgr_frame_decription 4
+	0x002AF142,
+	0x0F120000,	         //ki 0413                   // tgr_frame_decription 4
+
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F12012C,	         //0132                   //0138                  //awbb_IntcR
+	0x0F12010B,	         //010A                   //011C                  //awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType                          // VCM_I2C actuator
+	0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1                         // No PWM
+	0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1                     // Use GPIO_4 for enable port
+	0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,                   //REG_TC_IPRM_CM_Init_Mi2cBits                 // Use GPIO_5 for SCL GPIO_6 for SDA
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz                     // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0, //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000                            //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000, //#af_search_usAeStable
+	0x002A1494,
+	0x0F121000, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120002, //#af_search_usFinePeakCount
+	0x0F120000, //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120601, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000, //#af_search_usCapturePolicy 0000 Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120001, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200F0, //#af_search_usPeakThr  for
+	0x0F120090, //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F124040, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320, //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030, //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060, //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003, //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120011, //#af_pos_usTableLastInd 10h_ 1h = 17 Steps
+
+	0x0F120030, //#af_pos_usTable_0_  48
+	0x0F120034, //#af_pos_usTable_1_  51
+	0x0F120038, //#af_pos_usTable_2_  54
+	0x0F12003C, //#af_pos_usTable_3_  57
+	0x0F120040, //#af_pos_usTable_4_  61
+	0x0F120044, //#af_pos_usTable_5_  65
+	0x0F120048, //#af_pos_usTable_6_  69
+	0x0F12004C, //#af_pos_usTable_7_  73
+	0x0F120050, //#af_pos_usTable_8_  78
+	0x0F120054, //#af_pos_usTable_9_  83
+	0x0F120058, //#af_pos_usTable_10_ 89
+	0x0F12005C, //#af_pos_usTable_11_ 89
+	0x0F120060, //#af_pos_usTable_12_ 89
+	0x0F120064, //#af_pos_usTable_13_ 89
+	0x0F120068, //#af_pos_usTable_14_ 89
+	0x0F12006C, //#af_pos_usTable_15_ 89
+	0x0F120070, //#af_pos_usTable_16_ 89
+	0x0F120074, //#af_pos_usTable_17_ 89
+
+
+	//9. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000, //#afd_usParam[0]  I2C power down command
+	0x0F120006, //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8, //#afd_usParam[3]  PWM Period
+	0x0F120000, //#afd_usParam[4]  PWM Divider
+	0x0F120200, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120004, //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120100, //#afd_usParam[7]  Signal Shaping
+	0x0F120040, //#afd_usParam[8]  Signal Shaping level
+	0x0F120080, //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003,          //REG_TC_AF_AfCmd         //Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001,          //REG_TC_IPRM_AuxConfig         // bit[0] : Flash is in use bit[1] : Mechanical shutter is in use                   // 0 : do not use 1 : use
+	0x0F120003,          //REG_TC_IPRM_AuxPolarity         // bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+	0x0F120003,          //REG_TC_IPRM_AuxGpios         //1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12085C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000, //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,	         //senHal_NExpLinesCheckFine	         //0004             //extend Forbidden area line
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001, //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001, //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001, //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001, //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60, //pll_uMaxSysFreqKhz
+	0x0F127530, //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530, //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+	0x0F120000, //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001, //REG_TC_IPRM_UseNPviClocks
+	0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	         //38A4	         //36B0	         //34BC	         //32C8	         //REG_TC_IPRM_OpClk4KHz_0	         //52Mhz
+	0x0F1254F0,	         //4E20	         //3A98	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MinOutRate4KHz_0	         //54Mhz
+	0x0F1254F8,	         //57E4	         //61A8	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MaxOutRate4KHz_0	         //54Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	         //38A4	         //36B0	         //34BC	         //32C8	         //REG_TC_IPRM_OpClk4KHz_0	         //52Mhz
+	0x0F1254F0,	         //4E20	         //3A98	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MinOutRate4KHz_0	         //54Mhz
+	0x0F1254F8,	         //57E4	         //61A8	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MaxOutRate4KHz_0	         //54Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	         //38A4	         //36B0	         //34BC	         //32C8	         //REG_TC_IPRM_OpClk4KHz_0	         //52Mhz
+	0x0F1254F0,	         //4E20	         //3A98	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MinOutRate4KHz_0	         //54Mhz
+	0x0F1254F8,	         //57E4	         //61A8	         //7148	         //4B32	         //34BC	         //REG_TC_IPRM_MaxOutRate4KHz_0	         //54Mhz
+
+	0x002A1B78,
+	0x0F1238A4, //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4, //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4, //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,//bestiq
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F1205C0,	         //0800	         //REG_TC_GP_PrevReqInputWidth		         //Sensor Crop Width	2048
+	0x0F12033C,	         //0600	         //REG_TC_GP_PrevReqInputHeight	         //Sensor Crop Height 1536
+	0x0F120120,	         //0000	         //REG_TC_GP_PrevInputWidthOfs		         //Sensor HOffset 0
+	0x0F120162,	         //0000	         //REG_TC_GP_PrevInputHeightOfs	         //Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	                  //Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	                  //Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	                  //Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	                  //Sensor VOffset 0
+
+	0x002A1676,
+	0x0F120002,	                           // 0:Full 1:digital 2:PLA 3:CA
+
+	0x002A0216,
+	0x0F120001,	                           //for input size change
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 1024x768 system 52M PCLK 54M
+	//===================================================================
+	0x002A023E,
+	0x0F120500, //REG_0TC_PCFG_usWidth
+	0x0F1202D0, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	         //7148	         //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	         //7148	         //REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1201B8, //1A0          //REG_0TC_PCFG_usMaxFrTimeMsecMult10         //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS 01a0-24fr
+	0x0F12014D,          //REG_0TC_PCFG_usMinFrTimeMsecMult10         //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#else
+	0x0F120000, //REG_0TC_PCFG_uPrevMirror
+	0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 54M
+	//===================================================================
+	0x002A032E,
+	0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800, //REG_0TC_CCFG_usWidth
+	0x0F120600, //REG_0TC_CCFG_usHeight
+	0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_CCFG_OIFMask
+	0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001, //REG_0TC_CCFG_uClockInd
+	0x0F120002, //REG_0TC_CCFG_usFrTimeType
+	0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000, //REG_0TC_CCFG_bSmearOutput
+	0x0F120000, //REG_0TC_CCFG_sSaturation
+	0x0F120000, //REG_0TC_CCFG_sSharpBlur
+	0x0F120000, //REG_0TC_CCFG_sColorTemp
+	0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+
+
+
+	/* PREVIEW */
+	/* 0x002A0208, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActivePrevConfig */
+	/* 0x002A0210, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActiveCapConfig */
+	/* 0x002A020C, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevOpenAfterChange */
+	/* 0x002A01F4, */
+	/* 0x0F120001, */ /* REG_TC_GP_NewConfigSync */
+	/* 0x002A020A, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevConfigChanged */
+	/* 0x002A0212 ,*/
+	/* 0x0F120001, */ /* REG_TC_GP_CapConfigChanged */
+	/* 0x002A01E8, */
+	/* 0x0F120000, */ /* REG_TC_GP_EnableCapture */
+	/* 0x0F120001, */ /* REG_TC_GP_EnableCaptureChanged */
+
+	/* 0xFFFF0064, */ /* Delay 100ms */
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_                  //HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_                  //INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_                  //WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_                  //CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_                  //D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_                  //D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_                  //D75
+	0x002A07FE,
+	// 0613
+	0x0F123400,                   //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123400,                   //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123400,                   //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123400,                   //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123400,                   //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123400,                   //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F124000, //TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000,                   //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F124000,                   //TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+
+	//s002A06D8
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+
+	//add ki 11.02.18
+	// SLOW AE
+	// SLOW AE
+	0x002A13F2,
+	0x0F120014,	                  // 0010 ae_GainIn_0_			                  //
+	0x0F120032,	         // 0020	ae_GainIn_1_			         //
+	0x0F120078,	         // 0040	ae_GainIn_2_			         //
+	0x0F1200AA,	         // 0080	ae_GainIn_3_			         //
+	0x0F120100,	         // fix 0100	ae_GainIn_4_			         //
+	0x0F120140,	         // 0200	ae_GainIn_5_			         //
+	0x0F1201B8,	         // 0400	ae_GainIn_6_			         //
+	0x0F120400,	         // 0800	ae_GainIn_7_			         //
+	0x0F122000,	         // 2000	ae_GainIn_8_			         //
+
+	0x0F120046,	         //0050	         // 0010	ae_GainOut_0_	p	         //
+	0x0F120078,	         //0070	         // 0020	ae_GainOut_1_ p         //
+	0x0F1200BE,	         //00A0	         // 0040	ae_GainOut_2_	p	         //
+	0x0F1200DC,	         //00D0	         // 0080	ae_GainOut_3_	p	         //
+	0x0F120100,	                  // fix 0100	ae_GainOut_4_		                  //
+	0x0F12010E,	                  // 0200	ae_GainOut_5_		                  //
+	0x0F120140,	                  // 0400	ae_GainOut_6_		                  //
+	0x0F1201F4,	                  // 0800	ae_GainOut_7_		                  //
+	0x0F120200,	                  // 2000	ae_GainOut_8_		                  //
+
+
+	0x002A13BC,
+	0x0F120100,										//0000    	ae_ContrastS_0_//
+	0x0F120100,                 	//000C    	ae_ContrastS_1_//
+	0x0F120100,                 	//001C    	ae_ContrastS_2_//
+	0x0F120100,                 	//0020    	ae_ContrastS_3_//
+	0x0F120100,                 	//0020    	ae_ContrastS_4_//
+	0x0F120100,                 	//0020    	ae_ContrastS_5_//
+	0x0F120100,                 	//0020    	ae_ContrastS_6_//
+	0x0F120100,                 	//0020    	ae_ContrastS_7_//
+
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+
+
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR                  //MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+	//AE_state
+	0x002A04EE,
+	0x0F120105, //010E                   //#lt_uLimitHigh
+	0x0F1200FA, //00F5                   //#lt_uLimitLow
+
+	0x002A0500,
+	0x0F120001,	         //lt_uInitPostToleranceCnt
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //3415                   //#lt_uMaxExp1
+	0x002A0508,
+	0x0F123415, //26e8          //681F                   //#lt_uMaxExp2
+	0x002A050C,
+	0x0F123415, //26e8          //8227                   //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F123415, //681F                   //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F123415, //8227                   //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F120200, //1E0                   //#lt_uMaxAnGain1
+	0x0F120240, //1E0                   //#lt_uMaxAnGain2
+	0x0F120340, //0300                   //#lt_uMaxAnGain3
+	0x0F120A00, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F120200, //#lt_uCapMaxAnGain1
+	0x0F120240, //#lt_uCapMaxAnGain2
+	0x0F120340, //300                   //#lt_uCapMaxAnGain3
+	0x0F120A00, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120101, //ae_WeightTbl_16[0]   0000
+	0x0F120101, //ae_WeightTbl_16[1]   0000
+	0x0F120101, //ae_WeightTbl_16[2]   0000
+	0x0F120101, //ae_WeightTbl_16[3]   0000
+	0x0F120101, //ae_WeightTbl_16[4]   0101
+	0x0F120101, //ae_WeightTbl_16[5]   0101
+	0x0F120101, //ae_WeightTbl_16[6]   0101
+	0x0F120101, //ae_WeightTbl_16[7]   0101
+	0x0F120101, //ae_WeightTbl_16[8]   0101
+	0x0F120202, //ae_WeightTbl_16[9]   0201
+	0x0F120202, //ae_WeightTbl_16[10]  0102
+	0x0F120101, //ae_WeightTbl_16[11]  0101
+	0x0F120101, //ae_WeightTbl_16[12]  0101
+	0x0F120202, //ae_WeightTbl_16[13]  0202
+	0x0F120202, //ae_WeightTbl_16[14]  0202
+	0x0F120101, //ae_WeightTbl_16[15]  0101
+	0x0F120101, //ae_WeightTbl_16[16]  0101
+	0x0F120202, //ae_WeightTbl_16[17]  0202
+	0x0F120202, //ae_WeightTbl_16[18]  0202
+	0x0F120101, //ae_WeightTbl_16[19]  0101
+	0x0F120101, //ae_WeightTbl_16[20]  0201
+	0x0F120202, //ae_WeightTbl_16[21]  0202
+	0x0F120202, //ae_WeightTbl_16[22]  0202
+	0x0F120101, //ae_WeightTbl_16[23]  0102
+	0x0F120101, //ae_WeightTbl_16[24]  0201
+	0x0F120101, //ae_WeightTbl_16[25]  0202
+	0x0F120101, //ae_WeightTbl_16[26]  0202
+	0x0F120101, //ae_WeightTbl_16[27]  0102
+	0x0F120101, //ae_WeightTbl_16[28]  0101
+	0x0F120101, //ae_WeightTbl_16[29]  0101
+	0x0F120101, //ae_WeightTbl_16[30]  0101
+	0x0F120101, //ae_WeightTbl_16[31]  0101
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F12074D,	         //05F0                   //awbb_GamutWidthThr1
+	0x0F120433,	         //01F4                   //awbb_GamutHeightThr1
+	0x0F12002A,	         //006C                   //awbb_GamutWidthThr2
+	0x0F12000C,	         //0038                   //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F120020,	         //000C                   //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A1028,
+	0x0F120020,	         //awbb_MinNumOfOutdoorPatches
+
+	0x002A291A,
+	0x0F120004,                   // #Mon_AWB_ByPassMode                            // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A1048,
+	0x0F1200C8,	         //awbb_LowBr
+	0x0F12001E,	         //awbb_LowBr_NBzone
+
+	0x002A1008,
+	0x0F120020,	         //awbb_NormalYThresh_y_low
+	0x0F1200A0,	         //awbb_NormalYThresh_y_high
+	0x0F120002, //awbb_LowBrYThresh_y_low
+	0x0F1200A0, //awbb_LowBrYThresh_y_high
+
+
+
+	0x002A102E,
+	0x0F12054D,					         //awbb_MvEq_RBthresh
+
+	0x002A1032,
+	0x0F120000, //awbb_MovingScale10
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F120426,	         //03C0                   //03C0                  //03C0                  //awbb_IndoorGrZones_m_BGrid[0]
+	0x0F12047E,	         //03E2                   //03E2                  //03E2                  //awbb_IndoorGrZones_m_BGrid[1]
+	0x0F1203C6,	//0356          //0356         //0356         //awbb_IndoorGrZones_m_BGrid[2]
+	0x0F120496,	         //03FC                   //03FC                  //03FC                  //awbb_IndoorGrZones_m_BGrid[3]
+	0x0F120374,	//031E          //031E         //031E         //awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1204A0,	         //03FE                   //03FE                  //03FE                  //awbb_IndoorGrZones_m_BGrid[5]
+	0x0F12033A,	//02F0          //02F0         //02F0         //awbb_IndoorGrZones_m_BGrid[6]
+	0x0F120498,	         //03F0                   //03F0                  //03F0                  //awbb_IndoorGrZones_m_BGrid[7]
+	0x0F120312,	//02CA          //02CA         //02CA         //awbb_IndoorGrZones_m_BGrid[8]
+	0x0F120478,	         //03CC                   //03CC                  //03CC                  //awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202EA,	//02A8          //02A8         //02A8         //awbb_IndoorGrZones_m_BGrid[10]
+	0x0F120440,	//037A          //037A         //037A         //awbb_IndoorGrZones_m_BGrid[11]
+	0x0F1202C2,	//0280          //0288         //0288         //awbb_IndoorGrZones_m_BGrid[12]
+	0x0F1203FA,	//033C          //033C         //033C         //awbb_IndoorGrZones_m_BGrid[13]
+	0x0F12029A,	//0260          //0266         //0266         //awbb_IndoorGrZones_m_BGrid[14]
+	0x0F1203BE,	//030A          //030A         //031E         //awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120272,	//0242          //0246         //0246         //awbb_IndoorGrZones_m_BGrid[16]
+	0x0F120398,	         //02DC                   //02EC                  //0300                  //awbb_IndoorGrZones_m_BGrid[17]
+	0x0F12024E,	//0228          //0228         //0228         //awbb_IndoorGrZones_m_BGrid[18]
+	0x0F120372,	//02B2          //02CE         //02E8         //awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12022A,	//020E          //020E         //020E         //awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120340,	         //0290                   //02B0                  //02CA                  //awbb_IndoorGrZones_m_BGrid[21]
+	0x0F120206,	         //01F8                   //01F8                  //01F8                  //awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120310,	         //0276                   //0292                  //02B0                  //awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E2,	         //01E8                   //01E8                  //01E8                  //awbb_IndoorGrZones_m_BGrid[24]
+	0x0F1202DE,	         //0268                   //0276                  //0296                  //awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201C0,	//01DC          //01DC         //01DC         //awbb_IndoorGrZones_m_BGrid[26]
+	0x0F1202AE,	         //0256                   //0256                  //027A                  //awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201B4,	         //01E0                   //01E0                  //01E0                  //awbb_IndoorGrZones_m_BGrid[28]
+	0x0F12027E,	         //0238                   //0238                  //0252                  //awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201C0,	         //01EC                   //01EC                  //01F2                  //awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12024C,	         //020E                   //020E                  //0226                  //awbb_IndoorGrZones_m_BGrid[31]
+	0x0F1201FA,	         //0000                   //0000                  //0000                  //awbb_IndoorGrZones_m_BGrid[32]
+	0x0F12021C,	         //0000                   //0000                  //0000                  //awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000,	         //0000                   //0000                  //0000                  //awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000,	         //0000                   //0000                  //0000                  //awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000,	//0000          //0000         //0000         //awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000,	//0000          //0000         //0000         //awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000,	//0000          //0000         //0000         //awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000,	//0000          //0000         //0000         //awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200A6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120011,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12023E, //awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F120286, //awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F12022C, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202CC, //awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F12021A, //awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202F0, //awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120208, //awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F120316, //awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F1201F6, //awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202FE, //awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F1201E4, //awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202E8, //awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F1201D2, //awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202D2, //awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F1202BC, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F1202A6, //awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F1201D0, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F12028E, //awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F1201D6, //awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F120278, //awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F1201F8, //awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F120244, //awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C, //awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201D8, //awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F120400, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F120656, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F12035A, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F1205BE, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202E6, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120524, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F120290, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1204A0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120246, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F12041A, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201FE, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F1203AE, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201C0, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F12035A, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F120192, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F120306, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F120170, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F1202BA, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F12015C, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F12019C, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F12024E, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000B, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F120082, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F12028E, //awbb_GridCon0xt_1[0]
+	0x0F120306, //awbb_GridCon0xt_1[1]
+	0x0F1203A6, //awbb_GridCon0xt_1[2]
+
+	0x0F120F86, //awbb_GridCon0xt_2[0]  0F86
+	0x0F12105F, //awbb_GridCon0xt_2[1]  105F
+	0x0F121160, //awbb_GridCon0xt_2[2]  11AA
+	0x0F121161, //awbb_GridCon0xt_2[3]  1111
+	0x0F1211F2, //awbb_GridCon0xt_2[4]  120C
+	0x0F1212A1, //awbb_GridCon0xt_2[5]  126D
+
+	0x0F12008F, //awbb_GridCoeff_R_1
+	0x0F1200D4, //awbb_GridCoeff_B_1
+	0x0F1200C6, //awbb_GridCoeff_R_2
+	0x0F1200A2, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120000, //0032         //awbb_GridCorr_R[0][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[0][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[0][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[0][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[0][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[0][5]
+	0x0F120000, //0032         //awbb_GridCorr_R[1][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[1][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[1][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[1][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[1][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[1][5]
+	0x0F120000, //0032         //awbb_GridCorr_R[2][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[2][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[2][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[2][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[2][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[2][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[0][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[0][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[0][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[1][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[1][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[1][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[2][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[2][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F120000, //awbb_GridCorr_R_Out[0][0]
+	0x0F120000, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F120000, //awbb_GridCorr_R_Out[1][0]
+	0x0F120000, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F120000, //awbb_GridCorr_R_Out[2][0]
+	0x0F120000, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][5]
+
+
+	// SLOW AWB
+	0x002A110E,
+	0x0F120258, //0258 awbb_GainsMaxMove         //
+
+	//AWB Convergence Speed          //
+	0x002A11D6,
+	0x0F120008,
+	0x0F12FFFF, 	         //0190	awbb_WpFilterMaxThr          //
+	0x0F120010, //00A0	         //awbb_WpFilterCoef p          //
+	0x0F120020, 	         //0004 awbb_WpFilterSize          //
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201D4, //01DA 01CF 01CE 01C0 01D4                  //TVAR_wbt_pBaseCcms[0]
+	0x0F12FFCD, //FFC4 FFC3 FFB9 FFCB FFB2                  //TVAR_wbt_pBaseCcms[1]
+	0x0F12FFC4, //FFCD FFDD FFE8 FFE4 FFEE                  //TVAR_wbt_pBaseCcms[2]
+	0x0F12FF2A, //FF31 FF43 FF43 FF43 FF47                  //TVAR_wbt_pBaseCcms[3]
+	0x0F120124, //012A 011D 011D 011D 012C                  //TVAR_wbt_pBaseCcms[4]
+	0x0F12FF73, //FF6B FF6B FF6B FF6B FF5C                  //TVAR_wbt_pBaseCcms[5]
+	0x0F12FFE1, //FFDA FFDA FFDA FFDA FFCE                  //TVAR_wbt_pBaseCcms[6]
+	0x0F12FFBD, //FFC3 FFD1 FFD1 FFD1 FFD6                  //TVAR_wbt_pBaseCcms[7]
+	0x0F120159, //015F 0156 0156 0156 0162                  //TVAR_wbt_pBaseCcms[8]
+	0x0F1200EF, //0100 00FF 00FC 00F7 011D                  //TVAR_wbt_pBaseCcms[9]
+	0x0F1200E0, //00DE 00CE 00CC 00D1 00C6                  //TVAR_wbt_pBaseCcms[10]
+	0x0F12FED9, //FECE FEE3 FEE9 FEE9 FED2                  //TVAR_wbt_pBaseCcms[11]
+	0x0F1200DA, //00D5 00CD 00CD 00CD 00C8                  //TVAR_wbt_pBaseCcms[12]
+	0x0F12FF57, //FF56 FF5E FF5E FF5E FF56                  //TVAR_wbt_pBaseCcms[13]
+	0x0F120119, //0123 0128 0128 0128 0139                  //TVAR_wbt_pBaseCcms[14]
+	0x0F12FF74, //FF73 FF7E FF7E FF7E FF75                  //TVAR_wbt_pBaseCcms[15]
+	0x0F1200DF, //00E9 00EC 00EC 00EC 00FB                  //TVAR_wbt_pBaseCcms[16]
+	0x0F1200FF, //00FC 00F2 00F2 00F2 00F0                  //TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201D4, //01D4                  //TVAR_wbt_pBaseCcms[18]
+	0x0F12FFCD, //FFB2                  //TVAR_wbt_pBaseCcms[19]
+	0x0F12FFC4, //FFEE                  //TVAR_wbt_pBaseCcms[20]
+	0x0F12FF2A, //FF47                  //TVAR_wbt_pBaseCcms[21]
+	0x0F120124, //012C                  //TVAR_wbt_pBaseCcms[22]
+	0x0F12FF73, //FF5C                  //TVAR_wbt_pBaseCcms[23]
+	0x0F12FFE1, //FFCE                  //TVAR_wbt_pBaseCcms[24]
+	0x0F12FFBD, //FFD6                  //TVAR_wbt_pBaseCcms[25]
+	0x0F120159, //0162                  //TVAR_wbt_pBaseCcms[26]
+	0x0F1200EF, //011D                  //TVAR_wbt_pBaseCcms[27]
+	0x0F1200E0, //00C6                  //TVAR_wbt_pBaseCcms[28]
+	0x0F12FED9, //FED2                  //TVAR_wbt_pBaseCcms[29]
+	0x0F1200DA, //00C8                  //TVAR_wbt_pBaseCcms[30]
+	0x0F12FF57, //FF56                  //TVAR_wbt_pBaseCcms[31]
+	0x0F120119, //0139                  //TVAR_wbt_pBaseCcms[32]
+	0x0F12FF74, //FF75                  //TVAR_wbt_pBaseCcms[33]
+	0x0F1200DF, //00FB                  //TVAR_wbt_pBaseCcms[34]
+	0x0F1200FF, //00F0                  //TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201C0, //01D4                  //TVAR_wbt_pBaseCcms[36]
+	0x0F12FFCB, //FFB2                  //TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE4, //FFEE                  //TVAR_wbt_pBaseCcms[38]
+	0x0F12FF43, //FF47                  //TVAR_wbt_pBaseCcms[39]
+	0x0F12011D, //012C                  //TVAR_wbt_pBaseCcms[40]
+	0x0F12FF6B, //FF5C                  //TVAR_wbt_pBaseCcms[41]
+	0x0F12FFDA, //FFCE                  //TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD1, //FFD6                  //TVAR_wbt_pBaseCcms[43]
+	0x0F120156, //0162                  //TVAR_wbt_pBaseCcms[44]
+	0x0F1200F7, //011D                  //TVAR_wbt_pBaseCcms[45]
+	0x0F1200D1, //00C6                  //TVAR_wbt_pBaseCcms[46]
+	0x0F12FEE9, //FED2                  //TVAR_wbt_pBaseCcms[47]
+	0x0F1200CD, //00C8                  //TVAR_wbt_pBaseCcms[48]
+	0x0F12FF5E, //FF56                  //TVAR_wbt_pBaseCcms[49]
+	0x0F120128, //0139                  //TVAR_wbt_pBaseCcms[50]
+	0x0F12FF7E, //FF75                  //TVAR_wbt_pBaseCcms[51]
+	0x0F1200EC, //00FB                  //TVAR_wbt_pBaseCcms[52]
+	0x0F1200F2, //00F0                  //TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201C0, //01D4                  //TVAR_wbt_pBaseCcms[54]
+	0x0F12FFCB, //FFB2                  //TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE4, //FFEE                  //TVAR_wbt_pBaseCcms[56]
+	0x0F12FF43, //FF47                  //TVAR_wbt_pBaseCcms[57]
+	0x0F12011D, //012C                  //TVAR_wbt_pBaseCcms[58]
+	0x0F12FF6B, //FF5C                  //TVAR_wbt_pBaseCcms[59]
+	0x0F12FFDA, //FFCE                  //TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD1, //FFD6                  //TVAR_wbt_pBaseCcms[61]
+	0x0F120156, //0162                  //TVAR_wbt_pBaseCcms[62]
+	0x0F1200F7, //011D                  //TVAR_wbt_pBaseCcms[63]
+	0x0F1200D1, //00C6                  //TVAR_wbt_pBaseCcms[64]
+	0x0F12FEE9, //FED2                  //TVAR_wbt_pBaseCcms[65]
+	0x0F1200CD, //00C8                  //TVAR_wbt_pBaseCcms[66]
+	0x0F12FF5E, //FF56                  //TVAR_wbt_pBaseCcms[67]
+	0x0F120128, //0139                  //TVAR_wbt_pBaseCcms[68]
+	0x0F12FF7E, //FF75                  //TVAR_wbt_pBaseCcms[69]
+	0x0F1200EC, //00FB                  //TVAR_wbt_pBaseCcms[70]
+	0x0F1200F2, //00F0                  //TVAR_wbt_pBaseCcms[71]
+
+	0x0F120111, //0114                            //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFB5, //FFAC                  //TVAR_wbt_pBaseCcms[73]
+	0x0F120000, //FFFB                  //TVAR_wbt_pBaseCcms[74]
+	0x0F12FF26, //FF1D                  //TVAR_wbt_pBaseCcms[75]
+	0x0F120179, //0182                  //TVAR_wbt_pBaseCcms[76]
+	0x0F12FF4B, //FF40                  //TVAR_wbt_pBaseCcms[77]
+	0x0F12FFE1, //FFD8                  //TVAR_wbt_pBaseCcms[78]
+	0x0F12FFF0, //FFE9                  //TVAR_wbt_pBaseCcms[79]
+	0x0F120151, //0155                  //TVAR_wbt_pBaseCcms[80]
+	0x0F120099, //009A                  //TVAR_wbt_pBaseCcms[81]
+	0x0F12008C, //008B                  //TVAR_wbt_pBaseCcms[82]
+	0x0F12FF28, //FF1C                  //TVAR_wbt_pBaseCcms[83]
+	0x0F1200C4, //00C2                  //TVAR_wbt_pBaseCcms[84]
+	0x0F12FF7A, //FF6E                  //TVAR_wbt_pBaseCcms[85]
+	0x0F120134, //0137                  //TVAR_wbt_pBaseCcms[86]
+	0x0F12FF85, //FF79                  //TVAR_wbt_pBaseCcms[87]
+	0x0F120105, //0106                  //TVAR_wbt_pBaseCcms[88]
+	0x0F1200F2, //00F1                  //TVAR_wbt_pBaseCcms[89]
+
+	0x0F120111, //0114                            //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFB5, //FFAC                  //TVAR_wbt_pBaseCcms[91]
+	0x0F120000, //FFFB                  //TVAR_wbt_pBaseCcms[92]
+	0x0F12FF26, //FF1D                  //TVAR_wbt_pBaseCcms[93]
+	0x0F120179, //0182                  //TVAR_wbt_pBaseCcms[94]
+	0x0F12FF4B, //FF40                  //TVAR_wbt_pBaseCcms[95]
+	0x0F12FFE1, //FFD8                  //TVAR_wbt_pBaseCcms[96]
+	0x0F12FFF0, //FFE9                  //TVAR_wbt_pBaseCcms[97]
+	0x0F120151, //0155                  //TVAR_wbt_pBaseCcms[98]
+	0x0F120099, //009A                  //TVAR_wbt_pBaseCcms[99]
+	0x0F12008C, //008B                  //TVAR_wbt_pBaseCcms[100]
+	0x0F12FF28, //FF1C                  //TVAR_wbt_pBaseCcms[101]
+	0x0F1200C4, //00C2                  //TVAR_wbt_pBaseCcms[102]
+	0x0F12FF7A, //FF6E                  //TVAR_wbt_pBaseCcms[103]
+	0x0F120134, //0137                  //TVAR_wbt_pBaseCcms[104]
+	0x0F12FF85, //FF79                  //TVAR_wbt_pBaseCcms[105]
+	0x0F120105, //0106                  //TVAR_wbt_pBaseCcms[106]
+	0x0F1200F2, //00F1                  //TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201BE, //0205                  //01F8                  //TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FFE4, //FF96                  //FFAF                  //TVAR_wbt_pOutdoorCcm[1]
+	0x0F120000, //FFDF                  //FFD3                  //TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FEF9, //FEC8                  //FEC4                  //TVAR_wbt_pOutdoorCcm[3]
+	0x0F120149, //01A4                  //0191                  //TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF70, //FF1C                  //FF33                  //TVAR_wbt_pOutdoorCcm[5]
+	0x0F12003C, //FFF7                  //FFED                  //TVAR_wbt_pOutdoorCcm[6]
+	0x0F120023, //000C                  //0017                  //TVAR_wbt_pOutdoorCcm[7]
+	0x0F1201DD, //0211                  //0210                  //TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200D4, //0107                  //00E3                  //TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200F8, //00F3                  //0107                  //TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF74, //FF1F                  //FF2F                  //TVAR_wbt_pOutdoorCcm[11]
+	0x0F120212, //0220                  //0220                  //TVAR_wbt_pOutdoorCcm[12]
+	0x0F120039, //FFE7                  //FFE7                  //TVAR_wbt_pOutdoorCcm[13]
+	0x0F120184, //01A1                  //01A1                  //TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FF28, //FEC7                  //FEC8                  //TVAR_wbt_pOutdoorCcm[15]
+	0x0F120133, //016D                  //017D                  //TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153                  //0142                  //TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049                  //#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F                  //#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB                  //#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0                  //#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220                  //#afit_uNoiseIndInDoor_4_
+
+	// 0810 HD gamma 0~255->16~255
+	0x002A08C0,
+	0x0F120030,
+	0x0F120000, //0000         //700008C2           //AFIT16_CONTRAST
+	0x0F120010, //0000         //700008C4           //AFIT16_SATURATION
+	0x0F12FFE2, //0000         //700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000         //700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1         //700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000         //700008CC
+	0x0F1203FF, //03FF         //700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C	   //700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C         //700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF         //700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C         //700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010	   //700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C         //700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8         //700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046         //700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A         //700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070         //700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0010         //700008E4           //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0010         //700008E6           //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //01F4         //700008E8           //AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C         //700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008         //700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12006E, //003C	   //700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120014, //001E	   //700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12006E, //003C	   //700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120014, //001E	   //700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24         //700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701         //700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229         //700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403         //700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004         //700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300         //70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000         //70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF         //70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //09E8         //70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414         //70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301         //7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007	   //7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //4000         //7000090E
+	0x0F125003, //7803         //70000910
+	0x0F123228, //3C50         //70000912
+	0x0F120032, //003C         //70000914
+	0x0F121E80, //1E80         //70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08         //70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A         //7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000         //7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12270A, //120A         //7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F120010, //0F00         //70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200         //70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00         //70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200         //70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11         //70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000         //7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009         //7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406         //7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605         //70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307         //70000932
+	0x0F120609, //0609         //70000934
+	0x0F122C07, //2C07         //70000936
+	0x0F12142C, //142C         //70000938
+	0x0F120518, //0718         //7000093A         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8007         //7000093C         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120594, //0880         //7000093E                    //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F121080, // 0810 0080->1080          //0B50         //70000940                    //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080,          //0080         //70000942                    //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101,          //0101         //70000944                    //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707,          //0707         //70000946                    //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01,          //4601         //70000948                    //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12314B,          //C844         //7000094A                    //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125038,          //50C8         //7000094C                    //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500,          //0500         //7000094E                    //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120903,          //0003         //70000950                    //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121003,          //1C01         //70000952                    //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E,          //0714         //70000954                    //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432,          //1464         //70000956                    //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125F01,          //5A04         //70000958                    //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F122829,          //3C1E         //7000095A                    //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F,          //400F         //7000095C                    //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204,          //0204         //7000095E                    //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F120103,          //1403         //70000960                    //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120701,          //0114         //70000962                    //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101,          //0101         //70000964                    //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124B4B,          //4446         //70000966                    //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F124449,          //646E         //70000968                    //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120050,          //0028         //7000096A                    //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F120305,          //030A         //7000096C                    //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120346,          //0000         //7000096E                    //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F121E0D,          //141E         //70000970                    //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F123207,          //FF07         //70000972                    //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120114,          //0432         //70000974                    //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F121E6A,          //0000         //70000976                    //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F28,          //0F0F         //70000978                    //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120420,          //0440         //7000097A                    //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302,          //0302         //7000097C                    //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E,          //1414         //7000097E                    //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101,          //0101         //70000980                    //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124B01,          //4601         //70000982                    //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12494B,          //6E44         //70000984                    //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F125044,          //2864         //70000986                    //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120500,          //0A00         //70000988                    //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F124603,          //0003         //7000098A                    //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F120D03,          //1E00         //7000098C                    //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12071E,          //0714         //7000098E                    //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F121432,          //32FF         //70000990                    //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F126A01,          //0004         //70000992                    //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F12281E,          //0F00         //70000994                    //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12200F,          //400F         //70000996                    //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204,          //0204         //70000998                    //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003,	         //0003	         //7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, 		//0001         //7000099C
+	0x0F120030,
+	0x0F120000, 		//0000                  //700009A0                             //AFIT16_CONTRAST
+	0x0F120010,                   //0000                  //700009A2                             //AFIT16_SATURATION
+	0x0F120000,                   //0000                  //700009A4                             //AFIT16_SHARP_BLUR
+	0x0F120000, 		//0000                  //700009A6                             //AFIT16_GLAMOUR
+	0x0F1200C1,	         //00C1	         //700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, 		//0000                  //700009AA
+	0x0F1203FF,	         //03FF	         //700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C,	         //009C	         //700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C,	         //017C	         //700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF,	         //03FF	         //700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C,	         //000C	         //700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010,	         //0010	         //700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C,	         //012C	         //700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8,	         //03E8	         //700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046,	         //0046	         //700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A,	         //005A	         //700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070,	         //0070	         //700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001,	         //0001	         //700009C2	         //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000,	         //0000	         //700009C4	         //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320,	         //0320	         //700009C6	         //AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E,	         //006E	         //700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014,	         //0014	         //700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12006E,	         //003C	         //700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120014,	         //001E	         //700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12006E,	         //003C	         //700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120014,	         //001E	         //700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24,          //0A24         //700009D4                    //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701,          //1701         //700009D6                    //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229,          //0229         //700009D8                    //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403,          //1403         //700009DA                    //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004,          //0004         //700009DC                    //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300,          //0300         //700009DE                    //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000,          //0000         //700009E0                    //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF,          //02FF         //700009E2                    //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8,          //05E8         //700009E4                    //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414,          //1414         //700009E6                    //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301,          //0301         //700009E8                    //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007,	         //0007	         //700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000,		 //2000                  //700009EC
+	0x0F125003,		 //5003                  //700009EE
+	0x0F123228,		 //3228                  //700009F0
+	0x0F120032,		 //0032                  //700009F2
+	0x0F121E80,          //1E80         //700009F4                    //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08,          //1E08         //700009F6                    //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A,          //000A         //700009F8                    //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000,          //0000         //700009FA                    //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12270A,          //120A         //700009FC                    //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F120010,          //1400         //700009FE                    //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200,          //0200         //70000A00                    //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00,          //FF00         //70000A02                    //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200,          //0200         //70000A04                    //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11,          //1B11         //70000A06                    //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000,          //0000         //70000A08                    //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009,          //0009         //70000A0A                    //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406,          //0406         //70000A0C                    //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605,          //0605         //70000A0E                    //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, 		//0307                  //70000A10
+	0x0F120609, 		//0609                  //70000A12
+	0x0F122C07, 		//2C07                  //70000A14
+	0x0F12142C, 		//142C                  //70000A16
+	0x0F120518,          //0518         //70000A18         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005,          //8005         //70000A1A         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120594,                   //0580                  //70000A1C                             //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F121080, // 0810 0080->1080           //0080         //70000A1E                    //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080,          //0080         //70000A20                    //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101,          //0101         //70000A22                    //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707,          //0707         //70000A24                    //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01,          //4B01         //70000A26                    //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12314B,          //444B 494B         //70000A28                    //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125038,          //503C 5044         //70000A2A                    //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500,          //0500         //70000A2C                    //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120903,          //0503         //70000A2E                    //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121003,          //0D02         //70000A30                    //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E,          //071E         //70000A32                    //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432,          //1432         //70000A34                    //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125F01,          //5A01         //70000A36                    //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F122829,          //281E         //70000A38                    //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F,          //200F         //70000A3A                    //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204,          //0204         //70000A3C                    //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F120103,          //1E03         //70000A3E                    //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120701,          //011E         //70000A40                    //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101,          //0101         //70000A42                    //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124B4B,          //3A3C         //70000A44                    //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F124449,          //585A         //70000A46                    //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120050,          //0028         //70000A48                    //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F120305,          //030A         //70000A4A                    //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120346,          //0000         //70000A4C                    //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F121E0D,          //141E         //70000A4E                    //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F123207,          //FF07         //70000A50                    //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120114,          //0432         //70000A52                    //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F121E6A,          //0000         //70000A54                    //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F28,          //0F0F         //70000A56                    //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120420,          //0440         //70000A58                    //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302,          //0302         //70000A5A                    //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E,          //1E1E         //70000A5C                    //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101,          //0101         //70000A5E                    //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124B01,          //3C01         //70000A60                    //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12494B,          //5A3A         //70000A62                    //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F125044,          //2858         //70000A64                    //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120500,          //0A00         //70000A66                    //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F124603,          //0003         //70000A68                    //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F120D03,          //1E00         //70000A6A                    //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12071E,          //0714         //70000A6C                    //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F121432,          //32FF         //70000A6E                    //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F126A01,          //0004         //70000A70                    //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F12281E,          //0F00         //70000A72                    //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12200F,          //400F         //70000A74                    //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204,          //0204         //70000A76                    //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003,	         //0003	         //70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, 		//0001                  //70000A7A
+	0x0F120000, 		//0000                  //70000A7C                  //AFIT16_BRIGHTNESS
+	0x0F120000, 		//0000                  //70000A7E                             //AFIT16_CONTRAST
+	0x0F120000,	         //0000	         //70000A80           //AFIT16_SATURATION
+	0x0F120000,	         //0000	         //70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, 		//0000                  //70000A84                             //AFIT16_GLAMOUR
+	0x0F1200C1,	         //00C1	         //70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, 		//0000                  //70000A88
+	0x0F1203FF,	         //03FF	         //70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E,	         //009E	         //70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C,	         //017C	         //70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF,	         //03FF	         //70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C,	         //000C	         //70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010,	         //0010	         //70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C,	         //012C	         //70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8,	         //03E8	         //70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046,	         //0046	         //70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A,	         //005A	         //70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070,	         //0070	         //70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001,	         //0001	         //70000AA0	         //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000,	         //0000	         //70000AA2	         //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320,	         //0320	         //70000AA4	         //AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C,	         //008C	         //70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014,	         //0014	         //70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12008C,	         //003C	         //70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120014,	         //001E	         //70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12008C,	         //003C	         //70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120014,	         //001E	         //70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24,          //0A24         //70000AB2                    //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701,          //1701         //70000AB4                    //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229,          //0229         //70000AB6                    //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403,          //1403         //70000AB8                    //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004,          //0004         //70000ABA                    //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300,          //0300         //70000ABC                    //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000,          //0000         //70000ABE                    //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF,          //02FF         //70000AC0                    //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE,          //05DE         //70000AC2                    //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414,          //1414         //70000AC4                    //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301,          //0301         //70000AC6                    //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007,	         //0007	         //70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, 		//1000                  //70000ACA
+	0x0F122803, 		//2803                  //70000ACC
+	0x0F12261E, 		//261E                  //70000ACE
+	0x0F120026, 		//0026                  //70000AD0
+	0x0F121E80,          //1E80         //70000AD2                    //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08,          //1E08         //70000AD4                    //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A,          //010A         //70000AD6                    //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001,          //0001         //70000AD8                    //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F124C0A,                   //3C0A                  //70000ADA                             //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122B12,          //2300         //70000ADC                    //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120207,          //0200         //70000ADE                    //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00,          //FF00         //70000AE0                    //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200,          //0200         //70000AE2                    //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11,          //1B11         //70000AE4                    //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000,          //0000         //70000AE6                    //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009,          //0009         //70000AE8                    //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406,          //0406         //70000AEA                    //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605,          //0605         //70000AEC                    //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, 		//0307                  //70000AEE
+	0x0F120609, 		//0609                  //70000AF0
+	0x0F121C07, 		//1C07                  //70000AF2
+	0x0F121014, 		//1014                  //70000AF4
+	0x0F120510,          //0510         //70000AF6         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005,          //8005         //70000AF8         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080,          //0080         //70000AFA                    //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F121080, // 0810 0080->1080          //0080         //70000AFC                    //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080,          //0080         //70000AFE                    //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101,          //0101         //70000B00                    //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707,          //0707         //70000B02                    //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01,          //4B01         //70000B04                    //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12144B,          //2A4B         //70000B06                    //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125014,          //5020         //70000B08                    //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500,          //0500         //70000B0A                    //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121B03,          //1C03         //70000B0C                    //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F123003,          //0D0C         //70000B0E                    //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823,          //0823         //70000B10                    //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428,          //1428         //70000B12                    //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F128601,          //6401         //70000B14                    //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12283E,          //282D         //70000B16                    //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012,          //2012         //70000B18                    //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204,          //0204         //70000B1A                    //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F120103,          //2803         //70000B1C                    //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120701,          //0128         //70000B1E                    //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101,          //0101         //70000B20                    //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124B4B,          //2224         //70000B22                    //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F120606,          //3236         //70000B24                    //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120050,          //0028         //70000B26                    //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F120305,          //030A         //70000B28                    //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120C5C,          //0410         //70000B2A                    //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12230D,          //141E         //70000B2C                    //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F122807,          //FF07         //70000B2E                    //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120114,          //0432         //70000B30                    //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F122D74,          //4050         //70000B32                    //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120908,          //0F0F         //70000B34                    //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120420,          //0440         //70000B36                    //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302,          //0302         //70000B38                    //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F122828,          //2828         //70000B3A                    //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101,          //0101         //70000B3C                    //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124B01,          //2401         //70000B3E                    //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12004B,          //3622         //70000B40                    //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F125000,          //2832         //70000B42                    //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120500,          //0A00         //70000B44                    //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F125C03,          //1003         //70000B46                    //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F120D0C,          //1E04         //70000B48                    //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120823,          //0714         //70000B4A                    //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F121428,          //32FF         //70000B4C                    //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F127401,          //5004         //70000B4E                    //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F12082D,          //0F40         //70000B50                    //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F122009,          //400F         //70000B52                    //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204,          //0204         //70000B54                    //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003,	     //0003	    //70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, 	     //0001         //70000B58
+	0x0F120000, 	     //0000         //70000B5A           //AFIT16_BRIGHTNESS
+	0x0F120000, 	     //0000         //70000B5C           //AFIT16_CONTRAST
+	0x0F120000,	     //0000	    //70000B5E           //AFIT16_SATURATION
+	0x0F120000,	     //0000	    //70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, 	     //0000         //70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1,	     //00C1	    //70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, 	     //0000         //70000B66
+	0x0F1203FF,	     //03FF	    //70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E,	     //009E	    //70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C,	     //017C	    //70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF,	     //03FF	    //70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C,	     //000C	    //70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010,	     //0010	    //70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8,	     //00C8	    //70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8,	     //03E8	    //70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046,	     //0046	    //70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050,	     //0050	    //70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070,	     //0070	    //70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001,	     //0001	    //70000B7E	         //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000,	     //0000	    //70000B80	         //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320,	     //0320	    //70000B82	         //AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C,	     //008C	    //70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014,	     //0014	    //70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12008C,	     //002D	    //70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120014,	     //0019	    //70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12008C,	     //002D	    //70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120014,	     //0019	    //70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24,          //0A24         //70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701,          //1701         //70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229,          //0229         //70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403,          //1403         //70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004,          //0004         //70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300,          //0300         //70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000,          //0000         //70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF,          //02FF         //70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE,          //05DE         //70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414,          //1414         //70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301,          //0301         //70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007,	     //0007	    //70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, 	     //1000         //70000BA8
+	0x0F122303, 	     //2303         //70000BAA
+	0x0F12231A, 	     //231A         //70000BAC
+	0x0F120023, 	     //0023         //70000BAE
+	0x0F121E80,          //1E80         //70000BB0          //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08,          //1E08         //70000BB2          //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A,          //010A         //70000BB4          //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001,          //0001         //70000BB6          //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F127D0A,          //3C0A         //70000BB8          //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122C24,          //2300         //70000BBA          //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120207,          //0200         //70000BBC          //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00,          //FF00         //70000BBE          //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200,          //0200         //70000BC0          //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10,          //1E10         //70000BC2          //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000,          //0000         //70000BC4          //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009,          //0009         //70000BC6          //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406,          //0406         //70000BC8          //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705,          //0705         //70000BCA          //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120306, 	     //0306         //70000BCC
+	0x0F120509, 	     //0509         //70000BCE
+	0x0F122806, 	     //2806         //70000BD0
+	0x0F121428, 	     //1428         //70000BD2
+	0x0F120518,          //0518         //70000BD4         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005,          //8005         //70000BD6         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080,          //0080         //70000BD8                    //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F121080, 	     // 0810 0080->1080          //0080         //70000BDA                    //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080,          //0080         //70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101,          //0101         //70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707,          //0707         //70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01,          //4B01         //70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12144B,          //2A4B         //70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125014,          //5020         //70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500,          //0500         //70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F122B03,          //1C03         //70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F126303,          //0D0C         //70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823,          //0823         //70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428,          //1428         //70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F12CC01,          //6401         //70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12283E,                   //282D                  //70000BF4                             //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012,          //2012         //70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204,          //0204         //70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F120103,          //3C03         //70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120701,          //013C         //70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101,          //0101         //70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124B4B,          //1C1E         //70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F120606,          //1E22         //70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120050,          //0028         //70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F120305,          //030A         //70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120C5C,          //0214         //70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12230D,          //0E14         //70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F122808,          //FF06         //70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120114,          //0432         //70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F122D74,          //4052         //70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120908,          //150C         //70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120420,          //0440         //70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302,          //0302         //70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F123C3C,          //3C3C         //70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101,          //0101         //70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124B01,          //1E01         //70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12004B,          //221C         //70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F125000,          //281E         //70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120500,          //0A00         //70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F125C03,          //1403         //70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F120D0C,          //1402         //70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120823,          //060E         //70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F121428,          //32FF         //70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F127401,          //5204         //70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F12082D,          //0C40         //70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F122009,          //4015         //70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204,          //0204         //70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003,	     //0003	    //70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, 	     //0001         //70000C36
+	0x0F120000,	     //0000	    //70000C38	         //AFIT16_BRIGHTNESS
+	0x0F120000,          //0000         //70000C3A           //AFIT16_CONTRAST
+	0x0F120000,	     //0000	    //70000C3C	         //AFIT16_SATURATION
+	0x0F120000,	     //0000	    //70000C3E	         //AFIT16_SHARP_BLUR
+	0x0F120000,	     //0000	    //70000C40	         //AFIT16_GLAMOUR
+	0x0F1200C1,	     //00C1	    //70000C42	         //AFIT16_sddd8a_edge_high
+	0x0F120000, 	     //0000         //70000C44
+	0x0F1203FF,	     //03FF	    //70000C46	         //AFIT16_Demosaicing_iSatVal
+	0x0F12009C,	     //009C	    //0008	         //70000C48	         //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251,	     //0251	    //017C	         //70000C4A	         //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF,	     //03FF	    //03FF	         //70000C4C	         //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C,	     //000C	    //000C	         //70000C4E	         //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010,	     //0010	    //0010	         //70000C50	         //AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032,	     //0032	    //0032	         //70000C52	         //AFIT16_demsharpmix1_iLowBright
+	0x0F12028A,	     //028A	    //028A	         //70000C54	         //AFIT16_demsharpmix1_iHighBright
+	0x0F120032,	     //0032	    //0032	         //70000C56	         //AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4,	     //01F4	    //01F4	         //70000C58	         //AFIT16_demsharpmix1_iHighSat
+	0x0F120070,	     //0070	    //0070	         //70000C5A	         //AFIT16_demsharpmix1_iTune
+	0x0F120002,	     //0002	    //0002	         //70000C5C	         //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000,	     //0000	    //0000	         //70000C5E	         //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320,	     //0320	    //0320	         //70000C60	         //AFIT16_demsharpmix1_iHystCenter
+	0x0F120044,	     //0044	    //0070	         //70000C62	         //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014,	     //0014	    	         //70000C64	         //AFIT16_Sharpening_iHighSharpClamp
+	0x0F120044,	     //0046	    	         //70000C66	         //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120014,	     //0019	    	         //70000C68	         //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120044,	     //0046	    	         //70000C6A	         //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120014,	     //0019	    	         //70000C6C	         //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24,          //0A24         //0A24         //70000C6E         //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701,          //1701         //1701         //70000C70         //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229,          //0229         //0229         //70000C72         //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503,          //0503         //0503         //70000C74         //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F12080F,          //080F         //0101         //70000C76         //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120808,          //0808         //0101         //70000C78         //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000,          //0000         //0000         //70000C7A         //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1200FF,          //00FF         //02FF         //70000C7C         //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D,          //012D         //0396         //70000C7E         //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414,          //1414         //1414         //70000C80         //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301,          //0301         //0301         //70000C82         //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007,	         //0007	         //0007	         //70000C84	         //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, 		//1000                  //1000                  //70000C86
+	0x0F122003, 		//2003                  //2003                  //70000C88
+	0x0F121020, 		//1020                  //1020                  //70000C8A
+	0x0F120010, 		//0010                  //0010                  //70000C8C
+	0x0F121EFF,          //1EFF         //1E80         //70000C8E         //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E06,          //1E06         //1E06         //70000C90         //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12060A,          //060A         //030C         //70000C92         //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120306,          //0306         //0103         //70000C94         //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12810A,                   //8B0A                  //5A0A                  //70000C96                  //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F1215C4,          //2837         //2D00         //70000C98         //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120107,          //0110         //0100         //70000C9A         //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00,          //FF00         //FF00         //70000C9C         //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200,          //0200         //0200         //70000C9E         //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10,          //1E10         //1E10         //70000CA0         //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000,          //0000         //0000         //70000CA2         //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009,          //0009         //0009         //70000CA4         //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406,          //0406         //0406         //70000CA6         //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705,          //0705         //0705         //70000CA8         //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120305, 		//0305                  //0305                  //70000CAA
+	0x0F120609, 		//0609                  //0609                  //70000CAC
+	0x0F122C07, 		//2C07                  //2C07                  //70000CAE
+	0x0F12142C, 		//142C                  //142C                  //70000CB0
+	0x0F120B18,          //0B18         //0B18         //70000CB2         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B,          //800B         //800B         //70000CB4         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080,          //0080         //0080         //70000CB6         //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F121080, 		// 0810 0080->1080          //0080         //0080         //70000CB8         //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080,          //0080         //0080         //70000CBA         //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F125050,          //5050         //0101         //70000CBC         //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120101,          //0101         //0A0A         //70000CBE         //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F123201,          //3201         //3201         //70000CC0         //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F120032,          //1832         //1428         //70000CC2         //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F122100,          //210C         //100C         //70000CC4         //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120A00,          //0A00         //0500         //70000CC6         //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F125004,                   //1E04                  //1E02                  //70000CC8                  //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F12A400,          //0A08         //040C         //70000CCA         //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12070C,          //070C         //0828         //70000CCC         //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F123264,          //3264         //5064         //70000CCE         //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F12F802,          //5A02         //4605         //70000CD0         //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12103E,                   //1040                  //1E68                  //70000CD2                  //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F124012,          //4012         //201E         //70000CD4         //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120604,          //0604         //0604         //70000CD6         //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F125006,          //4606         //4606         //70000CD8         //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120150,          //0146         //0146         //70000CDA         //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101,          //0101         //0101         //70000CDC         //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F123232,          //1C18         //1C18         //70000CDE         //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F120000,          //1819         //1819         //70000CE0         //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120021,          //0028         //0028         //70000CE2         //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12040A,          //030A         //030A         //70000CE4         //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F12085E,          //0514         //0514         //70000CE6         //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120C0A,          //0C14         //0C14         //70000CE8         //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F123207,          //FF05         //FF05         //70000CEA         //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120119,          //0432         //0432         //70000CEC         //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F12406A,          //4052         //4052         //70000CEE         //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120908,          //1514         //1514         //70000CF0         //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440,          //0440         //0440         //70000CF2         //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120606,          //0302         //0302         //70000CF4         //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F124646,          //4646         //4646         //70000CF6         //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101,          //0101         //0101         //70000CF8         //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F123201,          //1801         //1801         //70000CFA         //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F120032,          //191C         //191C         //70000CFC         //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122100,          //2818         //2818         //70000CFE         //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00,          //0A00         //0A00         //70000D00         //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F125E04,          //1403         //1403         //70000D02         //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F120A08,          //1405         //1405         //70000D04         //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12070C,          //050C         //050C         //70000D06         //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F121932,          //32FF         //32FF         //70000D08         //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F126A01,          //5204         //5204         //70000D0A         //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120840,          //1440         //1440         //70000D0C         //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124009,          //4015         //4015         //70000D0E         //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120604,          //0204         //0204         //70000D10         //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120006,	         //0003	         //0003	         //70000D12	         //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, 		//0001                  //0001                  //70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F12BF02, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+
+
+	0x002a3fea,
+	0x0f120800, //analog filter update Green
+
+
+	/* TNP_Regs_bUseAccurateFR */
+	/* 0x00287000, */
+	/* 0x002A3FE4, */
+	/* 0x0F120001, */ /* on/off TNP_Regs_bAccuDynamicFR */
+	/* 0x0F1234A2, */ /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+	/* 0x0F1240FD, */ /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+};
+
+/* Return preview mode */
+static const u32 s5k5ccgx_preview_return[] =  {
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0C7E,
+	0x0F120396, //70000C7E //AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+	0x002A0CC4,
+	0x0F12100C, //70000CC4	//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+	0x002A0836,
+0x0F124000,     // 0613 3E00->4000	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	0x002A0D1E,
+	0x0F122102, //70000D1E
+
+	//PREVIEW
+	0x002A0208,
+	0x0F120000, //REG_TC_GP_ActivePrevConfig
+	0x002A0210,
+	0x0F120000, //REG_TC_GP_ActiveCapConfig
+	0x002A020C,
+	0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+	0x002A01F4,
+	0x0F120001, //REG_TC_GP_NewConfigSync
+	0x002A020A,
+	0x0F120001, //REG_TC_GP_PrevConfigChanged
+	0x002A0212,
+	0x0F120001, //REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120000, //REG_TC_GP_EnableCapture
+	0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_highlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0C7E,
+0x0F12032D,	//70000C7E	//AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+0x002A0CC4,
+0x0F12210E,	//70000CC4	//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+0x002A0836,
+0x0F123A00,	//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_3_
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* 2048x1536 capture (Capture config0) */
+static const u32 s5k5ccgx_snapshot[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0D1E,
+	0x0F12A102,	//70000D1E
+
+	0x002A0210,
+	0x0F120000,	//REG_TC_GP_ActiveCapConfig
+	0x002A01F4,
+	0x0F120001,	//REG_TC_GP_NewConfigSync
+	0x002A0212,
+	0x0F120001,	//REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120001,	//REG_TC_GP_EnableCapture
+	0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+	0xFFFF00A0,   //160ms
+};
+
+/* 640x480 capture (Capture config1) */
+static const u32 s5k5ccgx_snapshot_vga[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120001,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_lowlight_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF012C,   //300ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_normal_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Wide capture 2048x1104 for P2*/
+static const u32 s5k5ccgx_change_wide_cap[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120450,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F1200D8,	//REG_TC_GP_PrevInputHeightOfs (600h-480h)/2
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120450,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F1200D8,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120450,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F1200D8,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120228,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120450,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+/* To change Wide Capture to Normal Capture,
+* We have to restore capture configuration before starting Normal Capture.
+*/
+static const u32 s5k5ccgx_restore_capture_reg[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120600,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120300,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120600,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+static const u32 s5k5ccgx_get_light_status[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A3C,
+};
+
+static const u32 s5k5ccgx_get_iso_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A18,
+};
+
+static const u32 s5k5ccgx_get_shutterspeed_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A14,
+};
+
+static const u32 s5k5ccgx_fps_auto[] = {
+0xFCFCD000, // 0601
+0x00287000,
+0x002A025A,
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+/* DSLIM.
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnablePreview
+0x0F120001, //REG_TC_GP_EnablePreviewChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_15fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12029A,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12029A,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_25fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F120190, //14E,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F120190, //14E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_30fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12014E,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+
+
+/* effect off = normal */
+static const u32 s5k5ccgx_effect_off[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0648,
+0x0F120001,
+
+0x002A01E2,
+0x0F120000,		//REG_TC_GP_SpecialEffects	00:Normal Mode
+};
+
+static const u32 s5k5ccgx_effect_mono[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120001,		//REG_TC_GP_SpecialEffects	01:Mono Mode
+};
+
+static const u32 s5k5ccgx_effect_sepia[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120004,		//REG_TC_GP_SpecialEffects	04:Sepia Mode
+};
+
+static const u32 s5k5ccgx_effect_negative[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120003,		//REG_TC_GP_SpecialEffects	03:Negative Mode
+};
+
+static const u32 s5k5ccgx_wb_auto[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120001,	//Mon_AAIO_bAWB		AWB ON
+};
+
+static const u32 s5k5ccgx_wb_daylight[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F120620,	//REG_SF_USER_Rgain
+	0x0F120001,	//REG_SF_USER_RgainChanged
+	0x0F120400,	//REG_SF_USER_Ggain
+	0x0F120001,	//REG_SF_USER_GgainChanged
+	0x0F120540,	//REG_SF_USER_Bgain
+	0x0F120001,	//REG_SF_USER_BgainChaged
+	};
+
+static const u32 s5k5ccgx_wb_cloudy[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F1207B0,     //REG_SF_USER_Rgain
+	0x0F120001,	//REG_SF_USER_RgainChanged
+	0x0F120400,	//REG_SF_USER_Ggain
+	0x0F120001,	//REG_SF_USER_GgainChanged
+	0x0F120455,     //65//80//95//A8//REG_SF_USER_Bgain
+	0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_fluorescent[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F120560,		//REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F1208A0,		//REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_incandescent[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F1203C0,		//REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F120980,		//REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_brightness_m_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12001A, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12001F, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120028, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120032, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_0[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12004A,//TVAR_ae_BrAves
+
+};
+
+static const u32 s5k5ccgx_brightness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120065,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120075,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12008B,//TVAR_ae_BrAv
+
+};
+
+static const u32 s5k5ccgx_scene_off[] = {
+// ==========================================================
+// 	CAMERA_SCENE_OFF
+// ==========================================================
+/*
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,		//Mon_AAIO_bAWB		0: AWB OFF, 1: AWB ON
+*/
+
+// Center (Metering)
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+//	01. Portait / Landscape / Text / Fall Color Off
+
+0x00287000,
+0x002A1308,
+0x0F12003E,		//TVAR_ae_BrAve
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x0F120000,  		//REG_TC_UserContrast
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+//	02. Night / Firework Off
+0x00287000,
+0x002A025A,
+0x0F1203E8,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+0x002A034C,
+0x0F120535,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120010,	// 0010 ae_GainIn_0_			//
+0x0F120020,	// 0020	ae_GainIn_1_			//
+0x0F120040,	// 0040	ae_GainIn_2_			//
+0x0F120080,	// 0080	ae_GainIn_3_			//
+0x0F120100,	// fix 0100	ae_GainIn_4_			//
+0x0F120200,	// 0200	ae_GainIn_5_			//
+0x0F120400,	// 0400	ae_GainIn_6_			//
+0x0F120800,	// 0800	ae_GainIn_7_			//
+0x0F122000,	// 2000	ae_GainIn_8_			//
+
+0x0F120010,	//0050	// 0010	ae_GainOut_0_	p	//
+0x0F120020,	//0070	// 0020	ae_GainOut_1_ p//
+0x0F120040,	//00A0	// 0040	ae_GainOut_2_	p	//
+0x0F120080,	//00D0	// 0080	ae_GainOut_3_	p	//
+0x0F120100,	// fix 0100	ae_GainOut_4_		//
+0x0F120200,	// 0200	ae_GainOut_5_		//
+0x0F120400,	// 0400	ae_GainOut_6_		//
+0x0F120800,	// 0800	ae_GainOut_7_		//
+0x0F122000,	// 2000	ae_GainOut_8_		//
+
+//AE_state 0623 add 0725 misprinted
+0x002A04EE,
+0x0F12010E,      //#lt_uLimitHigh
+0x0F1200F5,      //#lt_uLimitLow
+//
+
+0x00287000,
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0524,
+0x0F1201E0,		//lt_uMaxAnGain1
+0x0F1201E0,		//lt_uMaxAnGain2
+0x0F120300,		//lt_uMaxAnGain3
+0x0F120840,		//lt_uMaxAnGain4
+
+0x0F120100,		//lt_uMaxDigGain
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F1201E0,		//lt_uCapMaxAnGain1
+0x0F1201E0,		//lt_uCapMaxAnGain2
+0x0F120300,		//lt_uCapMaxAnGain3
+0x0F120710,		//lt_uCapMaxAnGain4
+
+0x0F120100,		//lt_uCapMaxDigGain
+0x0F128000,		//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120010,		//AFIT16_demsharpmix1_iHystThLow
+0x0F120010,		//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F120B50,		//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+
+//	03. ISO Auto
+
+0x002A04A4,
+0x0F12067F,		//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+0x002A0486,
+0x0F120000,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_portrait[] = {
+// ==========================================================
+// 	CAMERA_SCENE_PORTRAIT (Auto/Center/Br0/Auto/Sharp-1/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F12FFF6,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_landscape[] = {
+// ==========================================================
+// 	CAMERA_SCENE_LANDSCAPE (Auto/Matrix/Br0/Auto/Sharp+1/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F12000A,		//REG_TC_UserSharpBlur
+
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+
+
+};
+
+static const u32 s5k5ccgx_scene_sports[] = {
+// ==========================================================
+// 	CAMERA_SCENE_SPORTS (Sport/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+
+// 0623 add
+0x002A04EE,
+0x0F120112,		//lt_uLimitHigh
+0x0F1200EE,		//lt_uLimitLow
+
+0x002A0504,
+0x0F120002, // 0623 1A0A->0002	//3415		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F120D05, // 0623 1E20->0D05	//3415		//lt_uMaxExp2		3415h = 13333d =  33.3325ms
+0x002A050C,
+0x0F121A0A, // 0623 3415->1A0A		//lt_uMaxExp3		3415h = 13333d =  33.3325ms
+0x002A0510,
+0x0F123415,		//lt_uMaxExp4		3415h = 13333d =  33.3325ms
+
+0x002A0514,
+0x0F120002, // 0623 1A0A->0002		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F120D05, // 0623 1E20->0D05		//lt_uCapMaxExp2		3415h = 13333d =  33.3325ms
+0x002A051C,
+0x0F121A0A, // 0623 3415->1A0A		//lt_uCapMaxExp3		3415h = 13333d =  33.3325ms
+0x002A0520,
+0x0F123415,		//lt_uCapMaxExp4		3415h = 13333d =  33.3325ms
+// 0623 deleted 0x0F120000,
+
+0x002A0524,
+0x0F120200,		//lt_uMaxAnGain1 0623 0300->0200
+0x0F120200,		//lt_uMaxAnGain2 0623 0380->0200
+0x0F120200,		//lt_uMaxAnGain3 0623 0480->0200
+0x0F120200,		//lt_uMaxAnGain4 0623 0880->0200
+
+0x0F120200,		//lt_uMaxDigGain 0623 0100->0200
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F120200,		//lt_uCapMaxAnGain1 0623 0300->0200
+0x0F120200,		//lt_uCapMaxAnGain2 0623 0380->0200
+0x0F120200,		//lt_uCapMaxAnGain3 0623 0480->0200
+0x0F120200,		//lt_uCapMaxAnGain4 0623 0710->0200
+
+0x0F120200,		//lt_uCapMaxDigGain 0623 0100->0200
+0x0F128000,		//lt_uCapMaxTotGain
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,
+
+//Preview
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_party[] = {
+// ==========================================================
+// 	CAMERA_SCENE_PARTYINDOOR (ISO200/Center/Br0/Auto/Sharp0/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+
+0x002A04EE,
+0x0F120112,		//lt_uLimitHigh
+0x0F1200EE,		//lt_uLimitLow
+
+0x002A05EA,
+0x0F120220,		//lt_bUseSecISODgain 0623 0100->0220
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120300,		//REG_SF_USER_IsoVal 0623 0320->0300
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_beach[] = {
+// ==========================================================
+// 	CAMERA_SCENE_BEACHSNOW (ISO50/Center/Br+1/Auto/Sharp0/Sat+1)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120020,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+//ISO 50
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_sunset[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F120526,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_dawn[] = {
+// Use MWB CWF
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120530,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F1207E6,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_fall[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120032,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+};
+
+static const u32 s5k5ccgx_scene_nightshot[] = {
+// ==========================================================
+// 	CAMERA_SCENE_NIGHT (Night/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F120682,	//9C4,4fps ->6fps //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F121388,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F121388,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,		//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,		//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0524,
+0x0F1201D0,		//lt_uMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120B00,
+
+0x0F120100,		//lt_uMaxDigGain
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F1201D0,		//lt_uCapMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uCapMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uCapMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,		//lt_uCapMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,		//lt_uCapMaxDigGain
+0x0F128000,		//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120000,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120000,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F121080,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_backlight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+/* Not Used */
+static const u32 s5k5ccgx_scene_firework[] = {
+// ==========================================================
+// 	CAMERA_SCENE_FIREWORK (ISO50/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F1209C4,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F122710,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F122710,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,		//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,		//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+//ISO 50
+
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_text[] = {
+// ==========================================================
+// 	CAMERA_SCENE_TEXT (Auto/Center/Br0/Auto/Sharp+2/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120014,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_candle[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F120526,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_metering_normal[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_metering_spot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+
+static const u32 s5k5ccgx_metering_center[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_auto[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12067F,		//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0486,
+0x0F120000,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,		//AFIT by Normalized Brightness Tunning Parameter
+
+//Preview
+0x002A0208,
+0x0F120000,		//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,		//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,		//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,		//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,		//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,		//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_50[] = {
+
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_100[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120200,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_200[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120400,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_400[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120800,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_ae_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120000, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12FFFF, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_ae_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120001, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12001E, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_af_abort[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120001,   // REG_TC_AF_AfCmd = 1, Abort A
+};
+
+static const u32 s5k5ccgx_af_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004,
+0xFFFF0043,   //67 ms delay,  Min 1 frame delay
+0x002A0226,   // write [7000 0226, REG_TC_AF_AfCmdParam]
+0x0F120000,   // write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.
+0xFFFF0096,   // 150ms Delay
+};
+
+static const u32 s5k5ccgx_af_normal_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+	0xFFFF0096, /* 150ms Delay */
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+	0x002A1494,
+	0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_night_normal_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+
+	0xFFFF00FA, /* 150ms Delay*/
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+	0x002A1494,
+	0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_macro_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120095, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+	0xFFFF0096, /* 150ms Delay */
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+
+	0x002A1494,
+	0x0F121042,
+
+	/* when user use lens position 16(10h) -> lens position 0(00h)
+	MSB 10 b means user uses #af_pos_usTable_16_ as start position.
+	LSB 00 b means user uses #af_pos_usTable_0_ as end position
+	refer to 5.3 macro mode setting.
+	"#af_pos_usMacroStartEnd" is only used in macro AF condition.
+	(normal AF doesn't use "#af_pos_usMacroStartEnd") */
+	0x002A1426,
+	0x0F121000, /* #af_pos_usMacroStartEn */
+};
+
+static const u32 s5k5ccgx_af_do[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120005,   // REG_TC_AF_AfCmd = 5, single A
+};
+
+static const u32 s5k5ccgx_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_1st_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+0xFFFF01F4, /* tuning point */
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_contrast_m_2[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_m_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_0[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D2,
+//0F120080,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_saturation_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12007E,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFE0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120005,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D6,
+0x0F120010,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_dtp_on[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_dtp_off[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_pll_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_pll_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_preflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F82,
+0x0F120001,		// TNP_Regs_PreflashStart
+};
+
+static const u32 s5k5ccgx_preflash_end[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F84,
+0x0F120001,		// TNP_Regs_PreflashEnd
+};
+
+static const u32 s5k5ccgx_mainflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F80,		//TNP_Regs_FastFlashAlg
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_mainflash_end[] = {
+};
+
+static const u32 s5k5ccgx_flash_ae_set[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_flash_ae_clear[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120002,
+};
+
+static const u32 s5k5ccgx_get_ae_stable_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E1E3C,
+};
+
+static const u32 s5k5ccgx_get_esd_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E0150,
+};
+
+static const u32 s5k5ccgx_antibanding_50hz_reg[] = {
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz	01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+
+static const u32 s5k5ccgx_antibanding_60hz_reg[] = {
+0x002A0F08,
+0x0F120001, //AFC_Default60Hz	01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+
+
+#endif /* __S5K5CCGX_REGS_P2_H__ */
+
diff --git a/drivers/media/video/s5k5ccgx_regs-p4w.h b/drivers/media/video/s5k5ccgx_regs-p4w.h
new file mode 100644
index 0000000..2d9e99f
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx_regs-p4w.h
@@ -0,0 +1,16080 @@
+/* drivers/media/video/s5k5ccgx_regs-p4w.h
+ *
+ * Driver for s5k5ccgx (5MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+
+#ifndef __S5K5CCGX_REG_P4W_H__
+#define __S5K5CCGX_REG_P4W_H__
+
+#if defined(FEATURE_YUV_CAPTURE)
+/* Init regs for YUV capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+	0xFCFCD000,	//Reset                                  //
+	0x00140001,   //Wait100mSec                            //
+	0x10021101,
+
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//============================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prio
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//============================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	/*++ Add ESD */
+	0x002A0150,
+	0x0F12AAAA,
+	/*-- Add ESD */
+	0x00287000,
+	0x002A352C,
+	0x0F12B5F8,    // 7000352C
+	0x0F124A22,    // 7000352E
+	0x0F124922,    // 70003530
+	0x0F124823,    // 70003532
+	0x0F124B23,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124922,    // 7000353E
+	0x0F124822,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FB71,    // 70003544
+	0x0F124922,    // 70003546
+	0x0F124822,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FB6D,    // 7000354C
+	0x0F124822,    // 7000354E
+	0x0F124E22,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124922,    // 70003554
+	0x0F124823,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FB66,    // 7000355A
+	0x0F124822,    // 7000355C
+	0x0F120037,    // 7000355E
+	0x0F123780,    // 70003560
+	0x0F126178,    // 70003562
+	0x0F124C21,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124921,    // 70003568
+	0x0F124822,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FB5C,    // 7000356E
+	0x0F124921,    // 70003570
+	0x0F124822,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FB58,    // 70003576
+	0x0F124921,    // 70003578
+	0x0F124822,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FB54,    // 7000357E
+	0x0F124921,    // 70003580
+	0x0F124822,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB50,    // 70003586
+	0x0F1283A5,    // 70003588
+	0x0F124821,    // 7000358A
+	0x0F126470,    // 7000358C
+	0x0F122001,    // 7000358E
+	0x0F120340,    // 70003590
+	0x0F123420,    // 70003592
+	0x0F128060,    // 70003594
+	0x0F122085,    // 70003596
+	0x0F1280A0,    // 70003598
+	0x0F12481E,    // 7000359A
+	0x0F1280E0,    // 7000359C
+	0x0F12481E,    // 7000359E
+	0x0F126730,    // 700035A0
+	0x0F12491E,    // 700035A2
+	0x0F12481E,    // 700035A4
+	0x0F12F000,    // 700035A6
+	0x0F12FB3F,    // 700035A8
+	0x0F12480F,    // 700035AA
+	0x0F126178,    // 700035AC
+	0x0F1281E5,    // 700035AE
+	0x0F128225,    // 700035B0
+	0x0F12BCF8,    // 700035B2
+	0x0F12BC08,    // 700035B4
+	0x0F124718,    // 700035B6
+	0x0F1200D4,    // 700035B8
+	0x0F125CC1,    // 700035BA
+	0x0F12633D,    // 700035BC
+	0x0F120000,    // 700035BE
+	0x0F121C08,    // 700035C0
+	0x0F127000,    // 700035C2
+	0x0F123290,    // 700035C4
+	0x0F127000,    // 700035C6
+	0x0F123643,    // 700035C8
+	0x0F127000,    // 700035CA
+	0x0F12D9E7,    // 700035CC
+	0x0F120000,    // 700035CE
+	0x0F12382B,    // 700035D0
+	0x0F127000,    // 700035D2
+	0x0F12395D,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F1238BD,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F120000,    // 700035DC
+	0x0F127000,    // 700035DE
+	0x0F123989,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F12F903,    // 700035E4
+	0x0F120000,    // 700035E6
+	0x0F123B83,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F123FC8,    // 700035EC
+	0x0F127000,    // 700035EE
+	0x0F12367B,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F12495F,    // 700035F4
+	0x0F120000,    // 700035F6
+	0x0F1236D9,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12E421,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F123797,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F12216D,    // 70003604
+	0x0F120000,    // 70003606
+	0x0F12380B,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F120179,    // 7000360C
+	0x0F120001,    // 7000360E
+	0x0F123AAD,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F1207FF,    // 70003614
+	0x0F120000,    // 70003616
+	0x0F123B21,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F123B49,    // 7000361C
+	0x0F127000,    // 7000361E
+	0x0F12E8AD,    // 70003620
+	0x0F120000,    // 70003622
+	0x0F12B570,    // 70003624
+	0x0F12000D,    // 70003626
+	0x0F124CFC,    // 70003628
+	0x0F128821,    // 7000362A
+	0x0F12F000,    // 7000362C
+	0x0F12FB04,    // 7000362E
+	0x0F128820,    // 70003630
+	0x0F124AFB,    // 70003632
+	0x0F120081,    // 70003634
+	0x0F125055,    // 70003636
+	0x0F121C40,    // 70003638
+	0x0F128020,    // 7000363A
+	0x0F12BC70,    // 7000363C
+	0x0F12BC08,    // 7000363E
+	0x0F124718,    // 70003640
+	0x0F126801,    // 70003642
+	0x0F120409,    // 70003644
+	0x0F120C09,    // 70003646
+	0x0F126840,    // 70003648
+	0x0F120400,    // 7000364A
+	0x0F120C00,    // 7000364C
+	0x0F124AF5,    // 7000364E
+	0x0F128992,    // 70003650
+	0x0F122A00,    // 70003652
+	0x0F12D00D,    // 70003654
+	0x0F122300,    // 70003656
+	0x0F121A80,    // 70003658
+	0x0F12D400,    // 7000365A
+	0x0F120003,    // 7000365C
+	0x0F120418,    // 7000365E
+	0x0F120C00,    // 70003660
+	0x0F124BF1,    // 70003662
+	0x0F121851,    // 70003664
+	0x0F12891B,    // 70003666
+	0x0F12428B,    // 70003668
+	0x0F12D300,    // 7000366A
+	0x0F12000B,    // 7000366C
+	0x0F120419,    // 7000366E
+	0x0F120C09,    // 70003670
+	0x0F124AEE,    // 70003672
+	0x0F128151,    // 70003674
+	0x0F128190,    // 70003676
+	0x0F124770,    // 70003678
+	0x0F12B510,    // 7000367A
+	0x0F124CEC,    // 7000367C
+	0x0F1248ED,    // 7000367E
+	0x0F1278A1,    // 70003680
+	0x0F122900,    // 70003682
+	0x0F12D101,    // 70003684
+	0x0F1287C1,    // 70003686
+	0x0F12E004,    // 70003688
+	0x0F127AE1,    // 7000368A
+	0x0F122900,    // 7000368C
+	0x0F12D001,    // 7000368E
+	0x0F122101,    // 70003690
+	0x0F1287C1,    // 70003692
+	0x0F12F000,    // 70003694
+	0x0F12FAD8,    // 70003696
+	0x0F1249E7,    // 70003698
+	0x0F128B08,    // 7000369A
+	0x0F1206C2,    // 7000369C
+	0x0F12D50A,    // 7000369E
+	0x0F127AA2,    // 700036A0
+	0x0F120652,    // 700036A2
+	0x0F12D507,    // 700036A4
+	0x0F122210,    // 700036A6
+	0x0F124390,    // 700036A8
+	0x0F128308,    // 700036AA
+	0x0F1248E3,    // 700036AC
+	0x0F127AE1,    // 700036AE
+	0x0F126B00,    // 700036B0
+	0x0F12F000,    // 700036B2
+	0x0F12FAD1,    // 700036B4
+	0x0F1248DB,    // 700036B6
+	0x0F1289C0,    // 700036B8
+	0x0F122801,    // 700036BA
+	0x0F12D109,    // 700036BC
+	0x0F1278A0,    // 700036BE
+	0x0F122800,    // 700036C0
+	0x0F12D006,    // 700036C2
+	0x0F127AE0,    // 700036C4
+	0x0F122800,    // 700036C6
+	0x0F12D003,    // 700036C8
+	0x0F127AA0,    // 700036CA
+	0x0F122140,    // 700036CC
+	0x0F124308,    // 700036CE
+	0x0F1272A0,    // 700036D0
+	0x0F12BC10,    // 700036D2
+	0x0F12BC08,    // 700036D4
+	0x0F124718,    // 700036D6
+	0x0F12B570,    // 700036D8
+	0x0F124DD7,    // 700036DA
+	0x0F124CD7,    // 700036DC
+	0x0F128B28,    // 700036DE
+	0x0F120701,    // 700036E0
+	0x0F12D507,    // 700036E2
+	0x0F122108,    // 700036E4
+	0x0F124388,    // 700036E6
+	0x0F128328,    // 700036E8
+	0x0F1249D5,    // 700036EA
+	0x0F126B20,    // 700036EC
+	0x0F126B89,    // 700036EE
+	0x0F12F000,    // 700036F0
+	0x0F12FABA,    // 700036F2
+	0x0F128B28,    // 700036F4
+	0x0F1206C1,    // 700036F6
+	0x0F12D5A0,    // 700036F8
+	0x0F1249CD,    // 700036FA
+	0x0F127A8A,    // 700036FC
+	0x0F120652,    // 700036FE
+	0x0F12D49C,    // 70003700
+	0x0F122210,    // 70003702
+	0x0F124390,    // 70003704
+	0x0F128328,    // 70003706
+	0x0F127AC9,    // 70003708
+	0x0F126B20,    // 7000370A
+	0x0F12F000,    // 7000370C
+	0x0F12FAA4,    // 7000370E
+	0x0F12E794,    // 70003710
+	0x0F12B5F8,    // 70003712
+	0x0F1249CB,    // 70003714
+	0x0F128F08,    // 70003716
+	0x0F12000C,    // 70003718
+	0x0F123480,    // 7000371A
+	0x0F122800,    // 7000371C
+	0x0F12D000,    // 7000371E
+	0x0F128360,    // 70003720
+	0x0F122000,    // 70003722
+	0x0F128708,    // 70003724
+	0x0F124DC8,    // 70003726
+	0x0F1226FF,    // 70003728
+	0x0F128828,    // 7000372A
+	0x0F121C76,    // 7000372C
+	0x0F122702,    // 7000372E
+	0x0F122803,    // 70003730
+	0x0F12D112,    // 70003732
+	0x0F128868,    // 70003734
+	0x0F122800,    // 70003736
+	0x0F12D10F,    // 70003738
+	0x0F1288E8,    // 7000373A
+	0x0F122800,    // 7000373C
+	0x0F12D10C,    // 7000373E
+	0x0F12F000,    // 70003740
+	0x0F12FA9A,    // 70003742
+	0x0F122800,    // 70003744
+	0x0F12D008,    // 70003746
+	0x0F128B60,    // 70003748
+	0x0F122800,    // 7000374A
+	0x0F12D001,    // 7000374C
+	0x0F1280EE,    // 7000374E
+	0x0F1280AF,    // 70003750
+	0x0F122001,    // 70003752
+	0x0F127268,    // 70003754
+	0x0F12F000,    // 70003756
+	0x0F12FA97,    // 70003758
+	0x0F128828,    // 7000375A
+	0x0F122802,    // 7000375C
+	0x0F12D10E,    // 7000375E
+	0x0F128868,    // 70003760
+	0x0F122800,    // 70003762
+	0x0F12D10B,    // 70003764
+	0x0F1288E8,    // 70003766
+	0x0F122800,    // 70003768
+	0x0F12D108,    // 7000376A
+	0x0F128B60,    // 7000376C
+	0x0F122800,    // 7000376E
+	0x0F12D001,    // 70003770
+	0x0F1280EE,    // 70003772
+	0x0F1280AF,    // 70003774
+	0x0F122001,    // 70003776
+	0x0F127268,    // 70003778
+	0x0F12F000,    // 7000377A
+	0x0F12FA85,    // 7000377C
+	0x0F1288E8,    // 7000377E
+	0x0F122800,    // 70003780
+	0x0F12D006,    // 70003782
+	0x0F121FC1,    // 70003784
+	0x0F1239FD,    // 70003786
+	0x0F12D003,    // 70003788
+	0x0F122001,    // 7000378A
+	0x0F12BCF8,    // 7000378C
+	0x0F12BC08,    // 7000378E
+	0x0F124718,    // 70003790
+	0x0F122000,    // 70003792
+	0x0F12E7FA,    // 70003794
+	0x0F12B570,    // 70003796
+	0x0F124CAC,    // 70003798
+	0x0F128860,    // 7000379A
+	0x0F122800,    // 7000379C
+	0x0F12D00C,    // 7000379E
+	0x0F128820,    // 700037A0
+	0x0F124DA3,    // 700037A2
+	0x0F122800,    // 700037A4
+	0x0F12D009,    // 700037A6
+	0x0F120029,    // 700037A8
+	0x0F1231A0,    // 700037AA
+	0x0F127AC9,    // 700037AC
+	0x0F122900,    // 700037AE
+	0x0F12D004,    // 700037B0
+	0x0F127AA8,    // 700037B2
+	0x0F122180,    // 700037B4
+	0x0F124308,    // 700037B6
+	0x0F1272A8,    // 700037B8
+	0x0F12E73F,    // 700037BA
+	0x0F122800,    // 700037BC
+	0x0F12D003,    // 700037BE
+	0x0F12F7FF,    // 700037C0
+	0x0F12FFA7,    // 700037C2
+	0x0F122800,    // 700037C4
+	0x0F12D1F8,    // 700037C6
+	0x0F122000,    // 700037C8
+	0x0F128060,    // 700037CA
+	0x0F128820,    // 700037CC
+	0x0F122800,    // 700037CE
+	0x0F12D003,    // 700037D0
+	0x0F122008,    // 700037D2
+	0x0F12F000,    // 700037D4
+	0x0F12FA60,    // 700037D6
+	0x0F12E00B,    // 700037D8
+	0x0F12489C,    // 700037DA
+	0x0F123020,    // 700037DC
+	0x0F128880,    // 700037DE
+	0x0F122800,    // 700037E0
+	0x0F12D103,    // 700037E2
+	0x0F127AA8,    // 700037E4
+	0x0F122101,    // 700037E6
+	0x0F124308,    // 700037E8
+	0x0F1272A8,    // 700037EA
+	0x0F122010,    // 700037EC
+	0x0F12F000,    // 700037EE
+	0x0F12FA53,    // 700037F0
+	0x0F128820,    // 700037F2
+	0x0F122800,    // 700037F4
+	0x0F12D1E0,    // 700037F6
+	0x0F12488A,    // 700037F8
+	0x0F1289C0,    // 700037FA
+	0x0F122801,    // 700037FC
+	0x0F12D1DC,    // 700037FE
+	0x0F127AA8,    // 70003800
+	0x0F1221BF,    // 70003802
+	0x0F124008,    // 70003804
+	0x0F1272A8,    // 70003806
+	0x0F12E718,    // 70003808
+	0x0F126800,    // 7000380A
+	0x0F124990,    // 7000380C
+	0x0F128188,    // 7000380E
+	0x0F124890,    // 70003810
+	0x0F122201,    // 70003812
+	0x0F128981,    // 70003814
+	0x0F124890,    // 70003816
+	0x0F120252,    // 70003818
+	0x0F124291,    // 7000381A
+	0x0F12D902,    // 7000381C
+	0x0F122102,    // 7000381E
+	0x0F128181,    // 70003820
+	0x0F124770,    // 70003822
+	0x0F122101,    // 70003824
+	0x0F128181,    // 70003826
+	0x0F124770,    // 70003828
+	0x0F12B5F1,    // 7000382A
+	0x0F124E80,    // 7000382C
+	0x0F128834,    // 7000382E
+	0x0F122C00,    // 70003830
+	0x0F12D03F,    // 70003832
+	0x0F122001,    // 70003834
+	0x0F122C08,    // 70003836
+	0x0F12D000,    // 70003838
+	0x0F122000,    // 7000383A
+	0x0F1270B0,    // 7000383C
+	0x0F124D7F,    // 7000383E
+	0x0F122800,    // 70003840
+	0x0F12D009,    // 70003842
+	0x0F12F000,    // 70003844
+	0x0F12FA30,    // 70003846
+	0x0F120028,    // 70003848
+	0x0F1238F0,    // 7000384A
+	0x0F126328,    // 7000384C
+	0x0F127AB0,    // 7000384E
+	0x0F12217E,    // 70003850
+	0x0F124008,    // 70003852
+	0x0F1272B0,    // 70003854
+	0x0F12E00F,    // 70003856
+	0x0F124F7A,    // 70003858
+	0x0F123780,    // 7000385A
+	0x0F128B78,    // 7000385C
+	0x0F122800,    // 7000385E
+	0x0F12D005,    // 70003860
+	0x0F12F000,    // 70003862
+	0x0F12FA29,    // 70003864
+	0x0F122000,    // 70003866
+	0x0F128378,    // 70003868
+	0x0F124976,    // 7000386A
+	0x0F128708,    // 7000386C
+	0x0F122000,    // 7000386E
+	0x0F12F000,    // 70003870
+	0x0F12FA2A,    // 70003872
+	0x0F124879,    // 70003874
+	0x0F126328,    // 70003876
+	0x0F1278B1,    // 70003878
+	0x0F122700,    // 7000387A
+	0x0F120038,    // 7000387C
+	0x0F122900,    // 7000387E
+	0x0F12D008,    // 70003880
+	0x0F124972,    // 70003882
+	0x0F123920,    // 70003884
+	0x0F128ACA,    // 70003886
+	0x0F122A00,    // 70003888
+	0x0F12D003,    // 7000388A
+	0x0F128B09,    // 7000388C
+	0x0F122900,    // 7000388E
+	0x0F12D000,    // 70003890
+	0x0F122001,    // 70003892
+	0x0F127170,    // 70003894
+	0x0F122C02,    // 70003896
+	0x0F12D102,    // 70003898
+	0x0F124868,    // 7000389A
+	0x0F123860,    // 7000389C
+	0x0F126328,    // 7000389E
+	0x0F122201,    // 700038A0
+	0x0F122C02,    // 700038A2
+	0x0F12D000,    // 700038A4
+	0x0F122200,    // 700038A6
+	0x0F124861,    // 700038A8
+	0x0F122110,    // 700038AA
+	0x0F12300A,    // 700038AC
+	0x0F12F000,    // 700038AE
+	0x0F12FA13,    // 700038B0
+	0x0F128037,    // 700038B2
+	0x0F129900,    // 700038B4
+	0x0F120020,    // 700038B6
+	0x0F12600C,    // 700038B8
+	0x0F12E767,    // 700038BA
+	0x0F12B538,    // 700038BC
+	0x0F124865,    // 700038BE
+	0x0F124669,    // 700038C0
+	0x0F123848,    // 700038C2
+	0x0F12F000,    // 700038C4
+	0x0F12FA10,    // 700038C6
+	0x0F124A5E,    // 700038C8
+	0x0F124862,    // 700038CA
+	0x0F128F51,    // 700038CC
+	0x0F122400,    // 700038CE
+	0x0F123020,    // 700038D0
+	0x0F122900,    // 700038D2
+	0x0F12D00A,    // 700038D4
+	0x0F128754,    // 700038D6
+	0x0F126941,    // 700038D8
+	0x0F126451,    // 700038DA
+	0x0F126491,    // 700038DC
+	0x0F12466B,    // 700038DE
+	0x0F128819,    // 700038E0
+	0x0F1287D1,    // 700038E2
+	0x0F12885B,    // 700038E4
+	0x0F120011,    // 700038E6
+	0x0F123140,    // 700038E8
+	0x0F12800B,    // 700038EA
+	0x0F128F91,    // 700038EC
+	0x0F122900,    // 700038EE
+	0x0F12D002,    // 700038F0
+	0x0F128794,    // 700038F2
+	0x0F126940,    // 700038F4
+	0x0F126490,    // 700038F6
+	0x0F12F000,    // 700038F8
+	0x0F12F9FE,    // 700038FA
+	0x0F12BC38,    // 700038FC
+	0x0F12BC08,    // 700038FE
+	0x0F124718,    // 70003900
+	0x0F12B5F8,    // 70003902
+	0x0F124C56,    // 70003904
+	0x0F1289E0,    // 70003906
+	0x0F12F000,    // 70003908
+	0x0F12F9FE,    // 7000390A
+	0x0F120006,    // 7000390C
+	0x0F128A20,    // 7000390E
+	0x0F12F000,    // 70003910
+	0x0F12FA02,    // 70003912
+	0x0F120007,    // 70003914
+	0x0F12484F,    // 70003916
+	0x0F124D4A,    // 70003918
+	0x0F123020,    // 7000391A
+	0x0F126CA9,    // 7000391C
+	0x0F126940,    // 7000391E
+	0x0F121809,    // 70003920
+	0x0F120200,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA00,    // 70003926
+	0x0F120400,    // 70003928
+	0x0F120C00,    // 7000392A
+	0x0F12002A,    // 7000392C
+	0x0F12326E,    // 7000392E
+	0x0F120011,    // 70003930
+	0x0F12390A,    // 70003932
+	0x0F122305,    // 70003934
+	0x0F12F000,    // 70003936
+	0x0F12F9FD,    // 70003938
+	0x0F124C43,    // 7000393A
+	0x0F1261A0,    // 7000393C
+	0x0F128FEB,    // 7000393E
+	0x0F120002,    // 70003940
+	0x0F120031,    // 70003942
+	0x0F120018,    // 70003944
+	0x0F12F000,    // 70003946
+	0x0F12F9FD,    // 70003948
+	0x0F12466B,    // 7000394A
+	0x0F120005,    // 7000394C
+	0x0F128018,    // 7000394E
+	0x0F12483C,    // 70003950
+	0x0F1269A2,    // 70003952
+	0x0F123040,    // 70003954
+	0x0F128800,    // 70003956
+	0x0F120039,    // 70003958
+	0x0F12F000,    // 7000395A
+	0x0F12F9F3,    // 7000395C
+	0x0F12466B,    // 7000395E
+	0x0F120006,    // 70003960
+	0x0F128058,    // 70003962
+	0x0F120021,    // 70003964
+	0x0F129800,    // 70003966
+	0x0F12311C,    // 70003968
+	0x0F12F000,    // 7000396A
+	0x0F12F9F3,    // 7000396C
+	0x0F124935,    // 7000396E
+	0x0F123180,    // 70003970
+	0x0F12808D,    // 70003972
+	0x0F1280CE,    // 70003974
+	0x0F128BA1,    // 70003976
+	0x0F124836,    // 70003978
+	0x0F123820,    // 7000397A
+	0x0F128001,    // 7000397C
+	0x0F128BE1,    // 7000397E
+	0x0F128041,    // 70003980
+	0x0F128C21,    // 70003982
+	0x0F128081,    // 70003984
+	0x0F12E701,    // 70003986
+	0x0F12B5F8,    // 70003988
+	0x0F124E2E,    // 7000398A
+	0x0F126C70,    // 7000398C
+	0x0F126CB1,    // 7000398E
+	0x0F120200,    // 70003990
+	0x0F12F000,    // 70003992
+	0x0F12F9C9,    // 70003994
+	0x0F120400,    // 70003996
+	0x0F120C00,    // 70003998
+	0x0F122401,    // 7000399A
+	0x0F120364,    // 7000399C
+	0x0F1242A0,    // 7000399E
+	0x0F12D200,    // 700039A0
+	0x0F120004,    // 700039A2
+	0x0F124A27,    // 700039A4
+	0x0F120020,    // 700039A6
+	0x0F12327E,    // 700039A8
+	0x0F121F91,    // 700039AA
+	0x0F122303,    // 700039AC
+	0x0F12F000,    // 700039AE
+	0x0F12F9C1,    // 700039B0
+	0x0F120405,    // 700039B2
+	0x0F120C2D,    // 700039B4
+	0x0F124A23,    // 700039B6
+	0x0F120020,    // 700039B8
+	0x0F12325A,    // 700039BA
+	0x0F120011,    // 700039BC
+	0x0F12390A,    // 700039BE
+	0x0F122305,    // 700039C0
+	0x0F12F000,    // 700039C2
+	0x0F12F9B7,    // 700039C4
+	0x0F12491F,    // 700039C6
+	0x0F1264C8,    // 700039C8
+	0x0F12491F,    // 700039CA
+	0x0F124E21,    // 700039CC
+	0x0F1288C8,    // 700039CE
+	0x0F122701,    // 700039D0
+	0x0F122800,    // 700039D2
+	0x0F12D009,    // 700039D4
+	0x0F124C23,    // 700039D6
+	0x0F1238FF,    // 700039D8
+	0x0F121E40,    // 700039DA
+	0x0F12D00A,    // 700039DC
+	0x0F122804,    // 700039DE
+	0x0F12D042,    // 700039E0
+	0x0F122806,    // 700039E2
+	0x0F12D101,    // 700039E4
+	0x0F122000,    // 700039E6
+	0x0F1280C8,    // 700039E8
+	0x0F1282B7,    // 700039EA
+	0x0F122001,    // 700039EC
+	0x0F12F000,    // 700039EE
+	0x0F12F9B9,    // 700039F0
+	0x0F12E6CB,    // 700039F2
+	0x0F12000D,    // 700039F4
+	0x0F12724F,    // 700039F6
+	0x0F122001,    // 700039F8
+	0x0F12F000,    // 700039FA
+	0x0F12F9BB,    // 700039FC
+	0x0F12F000,    // 700039FE
+	0x0F12F9C1,    // 70003A00
+	0x0F124910,    // 70003A02
+	0x0F123148,    // 70003A04
+	0x0F12C903,    // 70003A06
+	0x0F124348,    // 70003A08
+	0x0F120A00,    // 70003A0A
+	0x0F126160,    // 70003A0C
+	0x0F1220FF,    // 70003A0E
+	0x0F121D40,    // 70003A10
+	0x0F1280E8,    // 70003A12
+	0x0F12480C,    // 70003A14
+	0x0F123040,    // 70003A16
+	0x0F127707,    // 70003A18
+	0x0F12E7E6,    // 70003A1A
+	0x0F123290,    // 70003A1C
+	0x0F127000,    // 70003A1E
+	0x0F123294,    // 70003A20
+	0x0F127000,    // 70003A22
+	0x0F1204A8,    // 70003A24
+	0x0F127000,    // 70003A26
+	0x0F1215DC,    // 70003A28
+	0x0F127000,    // 70003A2A
+	0x0F125000,    // 70003A2C
+	0x0F12D000,    // 70003A2E
+	0x0F121E84,    // 70003A30
+	0x0F127000,    // 70003A32
+	0x0F121BE4,    // 70003A34
+	0x0F127000,    // 70003A36
+	0x0F122EA8,    // 70003A38
+	0x0F127000,    // 70003A3A
+	0x0F1221A4,    // 70003A3C
+	0x0F127000,    // 70003A3E
+	0x0F120100,    // 70003A40
+	0x0F127000,    // 70003A42
+	0x0F123F48,    // 70003A44
+	0x0F127000,    // 70003A46
+	0x0F1231A0,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F1201E8,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F12F2A0,    // 70003A50
+	0x0F12D000,    // 70003A52
+	0x0F122A44,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F12F400,    // 70003A58
+	0x0F12D000,    // 70003A5A
+	0x0F122024,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F121650,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F122A64,    // 70003A64
+	0x0F127000,    // 70003A66
+	0x0F124962,    // 70003A68
+	0x0F12724F,    // 70003A6A
+	0x0F1220FF,    // 70003A6C
+	0x0F121DC0,    // 70003A6E
+	0x0F1280C8,    // 70003A70
+	0x0F12F000,    // 70003A72
+	0x0F12F98F,    // 70003A74
+	0x0F124960,    // 70003A76
+	0x0F126ACA,    // 70003A78
+	0x0F12604A,    // 70003A7A
+	0x0F122800,    // 70003A7C
+	0x0F12D006,    // 70003A7E
+	0x0F12436A,    // 70003A80
+	0x0F120001,    // 70003A82
+	0x0F120010,    // 70003A84
+	0x0F12F000,    // 70003A86
+	0x0F12F94F,    // 70003A88
+	0x0F126160,    // 70003A8A
+	0x0F12E001,    // 70003A8C
+	0x0F12436A,    // 70003A8E
+	0x0F126162,    // 70003A90
+	0x0F128BF0,    // 70003A92
+	0x0F122800,    // 70003A94
+	0x0F12D001,    // 70003A96
+	0x0F12F7FF,    // 70003A98
+	0x0F12FF33,    // 70003A9A
+	0x0F122000,    // 70003A9C
+	0x0F12F000,    // 70003A9E
+	0x0F12F969,    // 70003AA0
+	0x0F124954,    // 70003AA2
+	0x0F1220FF,    // 70003AA4
+	0x0F121DC0,    // 70003AA6
+	0x0F1280C8,    // 70003AA8
+	0x0F12E79E,    // 70003AAA
+	0x0F12B570,    // 70003AAC
+	0x0F120004,    // 70003AAE
+	0x0F12F000,    // 70003AB0
+	0x0F12F978,    // 70003AB2
+	0x0F124D51,    // 70003AB4
+	0x0F128C29,    // 70003AB6
+	0x0F121A40,    // 70003AB8
+	0x0F1242A0,    // 70003ABA
+	0x0F12D803,    // 70003ABC
+	0x0F12F000,    // 70003ABE
+	0x0F12F971,    // 70003AC0
+	0x0F128C29,    // 70003AC2
+	0x0F121A44,    // 70003AC4
+	0x0F120020,    // 70003AC6
+	0x0F12626C,    // 70003AC8
+	0x0F12F000,    // 70003ACA
+	0x0F12F973,    // 70003ACC
+	0x0F1262A8,    // 70003ACE
+	0x0F12F000,    // 70003AD0
+	0x0F12F978,    // 70003AD2
+	0x0F126328,    // 70003AD4
+	0x0F128869,    // 70003AD6
+	0x0F122900,    // 70003AD8
+	0x0F12D000,    // 70003ADA
+	0x0F1262A8,    // 70003ADC
+	0x0F124848,    // 70003ADE
+	0x0F126B00,    // 70003AE0
+	0x0F128C00,    // 70003AE2
+	0x0F122800,    // 70003AE4
+	0x0F12D117,    // 70003AE6
+	0x0F126AA8,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F973,    // 70003AEC
+	0x0F1261E8,    // 70003AEE
+	0x0F124944,    // 70003AF0
+	0x0F128B8A,    // 70003AF2
+	0x0F122A00,    // 70003AF4
+	0x0F12D00C,    // 70003AF6
+	0x0F128BC9,    // 70003AF8
+	0x0F124288,    // 70003AFA
+	0x0F12D90A,    // 70003AFC
+	0x0F124841,    // 70003AFE
+	0x0F123020,    // 70003B00
+	0x0F128800,    // 70003B02
+	0x0F1261E8,    // 70003B04
+	0x0F128C29,    // 70003B06
+	0x0F121A40,    // 70003B08
+	0x0F1262A8,    // 70003B0A
+	0x0F12F000,    // 70003B0C
+	0x0F12F952,    // 70003B0E
+	0x0F1262A8,    // 70003B10
+	0x0F12E593,    // 70003B12
+	0x0F1261E9,    // 70003B14
+	0x0F12E591,    // 70003B16
+	0x0F12F000,    // 70003B18
+	0x0F12F944,    // 70003B1A
+	0x0F1261E8,    // 70003B1C
+	0x0F12E58D,    // 70003B1E
+	0x0F12B510,    // 70003B20
+	0x0F12F000,    // 70003B22
+	0x0F12F95F,    // 70003B24
+	0x0F124837,    // 70003B26
+	0x0F123020,    // 70003B28
+	0x0F128841,    // 70003B2A
+	0x0F122900,    // 70003B2C
+	0x0F12D007,    // 70003B2E
+	0x0F124A31,    // 70003B30
+	0x0F123280,    // 70003B32
+	0x0F126953,    // 70003B34
+	0x0F124A34,    // 70003B36
+	0x0F12428B,    // 70003B38
+	0x0F12D202,    // 70003B3A
+	0x0F128880,    // 70003B3C
+	0x0F1281D0,    // 70003B3E
+	0x0F12E5C7,    // 70003B40
+	0x0F1288C0,    // 70003B42
+	0x0F1281D0,    // 70003B44
+	0x0F12E5C4,    // 70003B46
+	0x0F12B570,    // 70003B48
+	0x0F126800,    // 70003B4A
+	0x0F120605,    // 70003B4C
+	0x0F120E2D,    // 70003B4E
+	0x0F124C2E,    // 70003B50
+	0x0F128B60,    // 70003B52
+	0x0F122800,    // 70003B54
+	0x0F12D010,    // 70003B56
+	0x0F12482D,    // 70003B58
+	0x0F128A00,    // 70003B5A
+	0x0F1206C0,    // 70003B5C
+	0x0F12D50C,    // 70003B5E
+	0x0F12482C,    // 70003B60
+	0x0F127800,    // 70003B62
+	0x0F122800,    // 70003B64
+	0x0F12D008,    // 70003B66
+	0x0F122000,    // 70003B68
+	0x0F12F000,    // 70003B6A
+	0x0F12F943,    // 70003B6C
+	0x0F128B20,    // 70003B6E
+	0x0F122201,    // 70003B70
+	0x0F122180,    // 70003B72
+	0x0F12F000,    // 70003B74
+	0x0F12F946,    // 70003B76
+	0x0F128320,    // 70003B78
+	0x0F120028,    // 70003B7A
+	0x0F12F000,    // 70003B7C
+	0x0F12F94A,    // 70003B7E
+	0x0F12E55C,    // 70003B80
+	0x0F12B5F8,    // 70003B82
+	0x0F124D1B,    // 70003B84
+	0x0F1226FF,    // 70003B86
+	0x0F1288E8,    // 70003B88
+	0x0F121D76,    // 70003B8A
+	0x0F1242B0,    // 70003B8C
+	0x0F12D026,    // 70003B8E
+	0x0F124821,    // 70003B90
+	0x0F124F22,    // 70003B92
+	0x0F127883,    // 70003B94
+	0x0F120038,    // 70003B96
+	0x0F124921,    // 70003B98
+	0x0F1230FF,    // 70003B9A
+	0x0F1237FF,    // 70003B9C
+	0x0F124A19,    // 70003B9E
+	0x0F12698C,    // 70003BA0
+	0x0F1230E1,    // 70003BA2
+	0x0F1237C1,    // 70003BA4
+	0x0F128800,    // 70003BA6
+	0x0F128BF9,    // 70003BA8
+	0x0F123220,    // 70003BAA
+	0x0F122B00,    // 70003BAC
+	0x0F12D00B,    // 70003BAE
+	0x0F1289D2,    // 70003BB0
+	0x0F122A00,    // 70003BB2
+	0x0F12D013,    // 70003BB4
+	0x0F124350,    // 70003BB6
+	0x0F12F000,    // 70003BB8
+	0x0F12F8B6,    // 70003BBA
+	0x0F121C40,    // 70003BBC
+	0x0F120400,    // 70003BBE
+	0x0F120C00,    // 70003BC0
+	0x0F12F000,    // 70003BC2
+	0x0F12F92F,    // 70003BC4
+	0x0F12E00A,    // 70003BC6
+	0x0F128A12,    // 70003BC8
+	0x0F122A00,    // 70003BCA
+	0x0F12D007,    // 70003BCC
+	0x0F124350,    // 70003BCE
+	0x0F12F000,    // 70003BD0
+	0x0F12F8AA,    // 70003BD2
+	0x0F121C40,    // 70003BD4
+	0x0F120400,    // 70003BD6
+	0x0F120C00,    // 70003BD8
+	0x0F12F000,    // 70003BDA
+	0x0F12F923,    // 70003BDC
+	0x0F12F000,    // 70003BDE
+	0x0F12F929,    // 70003BE0
+	0x0F1288E8,    // 70003BE2
+	0x0F1242B0,    // 70003BE4
+	0x0F12D103,    // 70003BE6
+	0x0F12490E,    // 70003BE8
+	0x0F1220FF,    // 70003BEA
+	0x0F121C40,    // 70003BEC
+	0x0F128048,    // 70003BEE
+	0x0F12E5CC,    // 70003BF0
+	0x0F120000,    // 70003BF2
+	0x0F1231A0,    // 70003BF4
+	0x0F127000,    // 70003BF6
+	0x0F1229E4,    // 70003BF8
+	0x0F127000,    // 70003BFA
+	0x0F121E3C,    // 70003BFC
+	0x0F127000,    // 70003BFE
+	0x0F1221A4,    // 70003C00
+	0x0F127000,    // 70003C02
+	0x0F123FC8,    // 70003C04
+	0x0F127000,    // 70003C06
+	0x0F12E200,    // 70003C08
+	0x0F12D000,    // 70003C0A
+	0x0F122EA8,    // 70003C0C
+	0x0F127000,    // 70003C0E
+	0x0F12B040,    // 70003C10
+	0x0F12D000,    // 70003C12
+	0x0F12323C,    // 70003C14
+	0x0F127000,    // 70003C16
+	0x0F121E84,    // 70003C18
+	0x0F127000,    // 70003C1A
+	0x0F122024,    // 70003C1C
+	0x0F127000,    // 70003C1E
+	0x0F120080,    // 70003C20
+	0x0F127000,    // 70003C22
+	0x0F12C100,    // 70003C24
+	0x0F12D000,    // 70003C26
+	0x0F124778,    // 70003C28
+	0x0F1246C0,    // 70003C2A
+	0x0F12C000,    // 70003C2C
+	0x0F12E59F,    // 70003C2E
+	0x0F12FF1C,    // 70003C30
+	0x0F12E12F,    // 70003C32
+	0x0F121F63,    // 70003C34
+	0x0F120001,    // 70003C36
+	0x0F124778,    // 70003C38
+	0x0F1246C0,    // 70003C3A
+	0x0F12C000,    // 70003C3C
+	0x0F12E59F,    // 70003C3E
+	0x0F12FF1C,    // 70003C40
+	0x0F12E12F,    // 70003C42
+	0x0F121EDF,    // 70003C44
+	0x0F120001,    // 70003C46
+	0x0F124778,    // 70003C48
+	0x0F1246C0,    // 70003C4A
+	0x0F12C000,    // 70003C4C
+	0x0F12E59F,    // 70003C4E
+	0x0F12FF1C,    // 70003C50
+	0x0F12E12F,    // 70003C52
+	0x0F12495F,    // 70003C54
+	0x0F120000,    // 70003C56
+	0x0F124778,    // 70003C58
+	0x0F1246C0,    // 70003C5A
+	0x0F12C000,    // 70003C5C
+	0x0F12E59F,    // 70003C5E
+	0x0F12FF1C,    // 70003C60
+	0x0F12E12F,    // 70003C62
+	0x0F12E403,    // 70003C64
+	0x0F120000,    // 70003C66
+	0x0F124778,    // 70003C68
+	0x0F1246C0,    // 70003C6A
+	0x0F12C000,    // 70003C6C
+	0x0F12E59F,    // 70003C6E
+	0x0F12FF1C,    // 70003C70
+	0x0F12E12F,    // 70003C72
+	0x0F1224B3,    // 70003C74
+	0x0F120001,    // 70003C76
+	0x0F124778,    // 70003C78
+	0x0F1246C0,    // 70003C7A
+	0x0F12C000,    // 70003C7C
+	0x0F12E59F,    // 70003C7E
+	0x0F12FF1C,    // 70003C80
+	0x0F12E12F,    // 70003C82
+	0x0F12EECD,    // 70003C84
+	0x0F120000,    // 70003C86
+	0x0F124778,    // 70003C88
+	0x0F1246C0,    // 70003C8A
+	0x0F12C000,    // 70003C8C
+	0x0F12E59F,    // 70003C8E
+	0x0F12FF1C,    // 70003C90
+	0x0F12E12F,    // 70003C92
+	0x0F12F049,    // 70003C94
+	0x0F120000,    // 70003C96
+	0x0F124778,    // 70003C98
+	0x0F1246C0,    // 70003C9A
+	0x0F12C000,    // 70003C9C
+	0x0F12E59F,    // 70003C9E
+	0x0F12FF1C,    // 70003CA0
+	0x0F12E12F,    // 70003CA2
+	0x0F1212DF,    // 70003CA4
+	0x0F120000,    // 70003CA6
+	0x0F124778,    // 70003CA8
+	0x0F1246C0,    // 70003CAA
+	0x0F12C000,    // 70003CAC
+	0x0F12E59F,    // 70003CAE
+	0x0F12FF1C,    // 70003CB0
+	0x0F12E12F,    // 70003CB2
+	0x0F12F05B,    // 70003CB4
+	0x0F120000,    // 70003CB6
+	0x0F124778,    // 70003CB8
+	0x0F1246C0,    // 70003CBA
+	0x0F12C000,    // 70003CBC
+	0x0F12E59F,    // 70003CBE
+	0x0F12FF1C,    // 70003CC0
+	0x0F12E12F,    // 70003CC2
+	0x0F12F07B,    // 70003CC4
+	0x0F120000,    // 70003CC6
+	0x0F124778,    // 70003CC8
+	0x0F1246C0,    // 70003CCA
+	0x0F12C000,    // 70003CCC
+	0x0F12E59F,    // 70003CCE
+	0x0F12FF1C,    // 70003CD0
+	0x0F12E12F,    // 70003CD2
+	0x0F12FE6D,    // 70003CD4
+	0x0F120000,    // 70003CD6
+	0x0F124778,    // 70003CD8
+	0x0F1246C0,    // 70003CDA
+	0x0F12C000,    // 70003CDC
+	0x0F12E59F,    // 70003CDE
+	0x0F12FF1C,    // 70003CE0
+	0x0F12E12F,    // 70003CE2
+	0x0F123295,    // 70003CE4
+	0x0F120000,    // 70003CE6
+	0x0F124778,    // 70003CE8
+	0x0F1246C0,    // 70003CEA
+	0x0F12C000,    // 70003CEC
+	0x0F12E59F,    // 70003CEE
+	0x0F12FF1C,    // 70003CF0
+	0x0F12E12F,    // 70003CF2
+	0x0F12234F,    // 70003CF4
+	0x0F120000,    // 70003CF6
+	0x0F124778,    // 70003CF8
+	0x0F1246C0,    // 70003CFA
+	0x0F12C000,    // 70003CFC
+	0x0F12E59F,    // 70003CFE
+	0x0F12FF1C,    // 70003D00
+	0x0F12E12F,    // 70003D02
+	0x0F124521,    // 70003D04
+	0x0F120000,    // 70003D06
+	0x0F124778,    // 70003D08
+	0x0F1246C0,    // 70003D0A
+	0x0F12C000,    // 70003D0C
+	0x0F12E59F,    // 70003D0E
+	0x0F12FF1C,    // 70003D10
+	0x0F12E12F,    // 70003D12
+	0x0F127C0D,    // 70003D14
+	0x0F120000,    // 70003D16
+	0x0F124778,    // 70003D18
+	0x0F1246C0,    // 70003D1A
+	0x0F12C000,    // 70003D1C
+	0x0F12E59F,    // 70003D1E
+	0x0F12FF1C,    // 70003D20
+	0x0F12E12F,    // 70003D22
+	0x0F127C2B,    // 70003D24
+	0x0F120000,    // 70003D26
+	0x0F124778,    // 70003D28
+	0x0F1246C0,    // 70003D2A
+	0x0F12F004,    // 70003D2C
+	0x0F12E51F,    // 70003D2E
+	0x0F1224C4,    // 70003D30
+	0x0F120001,    // 70003D32
+	0x0F124778,    // 70003D34
+	0x0F1246C0,    // 70003D36
+	0x0F12C000,    // 70003D38
+	0x0F12E59F,    // 70003D3A
+	0x0F12FF1C,    // 70003D3C
+	0x0F12E12F,    // 70003D3E
+	0x0F123183,    // 70003D40
+	0x0F120000,    // 70003D42
+	0x0F124778,    // 70003D44
+	0x0F1246C0,    // 70003D46
+	0x0F12C000,    // 70003D48
+	0x0F12E59F,    // 70003D4A
+	0x0F12FF1C,    // 70003D4C
+	0x0F12E12F,    // 70003D4E
+	0x0F12302F,    // 70003D50
+	0x0F120000,    // 70003D52
+	0x0F124778,    // 70003D54
+	0x0F1246C0,    // 70003D56
+	0x0F12C000,    // 70003D58
+	0x0F12E59F,    // 70003D5A
+	0x0F12FF1C,    // 70003D5C
+	0x0F12E12F,    // 70003D5E
+	0x0F12EF07,    // 70003D60
+	0x0F120000,    // 70003D62
+	0x0F124778,    // 70003D64
+	0x0F1246C0,    // 70003D66
+	0x0F12C000,    // 70003D68
+	0x0F12E59F,    // 70003D6A
+	0x0F12FF1C,    // 70003D6C
+	0x0F12E12F,    // 70003D6E
+	0x0F1248FB,    // 70003D70
+	0x0F120000,    // 70003D72
+	0x0F124778,    // 70003D74
+	0x0F1246C0,    // 70003D76
+	0x0F12C000,    // 70003D78
+	0x0F12E59F,    // 70003D7A
+	0x0F12FF1C,    // 70003D7C
+	0x0F12E12F,    // 70003D7E
+	0x0F12F0B1,    // 70003D80
+	0x0F120000,    // 70003D82
+	0x0F124778,    // 70003D84
+	0x0F1246C0,    // 70003D86
+	0x0F12C000,    // 70003D88
+	0x0F12E59F,    // 70003D8A
+	0x0F12FF1C,    // 70003D8C
+	0x0F12E12F,    // 70003D8E
+	0x0F12EEDF,    // 70003D90
+	0x0F120000,    // 70003D92
+	0x0F124778,    // 70003D94
+	0x0F1246C0,    // 70003D96
+	0x0F12C000,    // 70003D98
+	0x0F12E59F,    // 70003D9A
+	0x0F12FF1C,    // 70003D9C
+	0x0F12E12F,    // 70003D9E
+	0x0F12AEF1,    // 70003DA0
+	0x0F120000,    // 70003DA2
+	0x0F124778,    // 70003DA4
+	0x0F1246C0,    // 70003DA6
+	0x0F12C000,    // 70003DA8
+	0x0F12E59F,    // 70003DAA
+	0x0F12FF1C,    // 70003DAC
+	0x0F12E12F,    // 70003DAE
+	0x0F1239DF,    // 70003DB0
+	0x0F120000,    // 70003DB2
+	0x0F124778,    // 70003DB4
+	0x0F1246C0,    // 70003DB6
+	0x0F12C000,    // 70003DB8
+	0x0F12E59F,    // 70003DBA
+	0x0F12FF1C,    // 70003DBC
+	0x0F12E12F,    // 70003DBE
+	0x0F126177,    // 70003DC0
+	0x0F120000,    // 70003DC2
+	0x0F124778,    // 70003DC4
+	0x0F1246C0,    // 70003DC6
+	0x0F12C000,    // 70003DC8
+	0x0F12E59F,    // 70003DCA
+	0x0F12FF1C,    // 70003DCC
+	0x0F12E12F,    // 70003DCE
+	0x0F12424F,    // 70003DD0
+	0x0F120000,    // 70003DD2
+	0x0F124778,    // 70003DD4
+	0x0F1246C0,    // 70003DD6
+	0x0F12C000,    // 70003DD8
+	0x0F12E59F,    // 70003DDA
+	0x0F12FF1C,    // 70003DDC
+	0x0F12E12F,    // 70003DDE
+	0x0F123F0D,    // 70003DE0
+	0x0F120000,    // 70003DE2
+	0x0F124778,    // 70003DE4
+	0x0F1246C0,    // 70003DE6
+	0x0F12C000,    // 70003DE8
+	0x0F12E59F,    // 70003DEA
+	0x0F12FF1C,    // 70003DEC
+	0x0F12E12F,    // 70003DEE
+	0x0F1202B9,    // 70003DF0
+	0x0F120001,    // 70003DF2
+	0x0F124778,    // 70003DF4
+	0x0F1246C0,    // 70003DF6
+	0x0F12C000,    // 70003DF8
+	0x0F12E59F,    // 70003DFA
+	0x0F12FF1C,    // 70003DFC
+	0x0F12E12F,    // 70003DFE
+	0x0F12FE45,    // 70003E00
+	0x0F120000,    // 70003E02
+	0x0F124778,    // 70003E04
+	0x0F1246C0,    // 70003E06
+	0x0F12C000,    // 70003E08
+	0x0F12E59F,    // 70003E0A
+	0x0F12FF1C,    // 70003E0C
+	0x0F12E12F,    // 70003E0E
+	0x0F1232A7,    // 70003E10
+	0x0F120000,    // 70003E12
+	0x0F124778,    // 70003E14
+	0x0F1246C0,    // 70003E16
+	0x0F12C000,    // 70003E18
+	0x0F12E59F,    // 70003E1A
+	0x0F12FF1C,    // 70003E1C
+	0x0F12E12F,    // 70003E1E
+	0x0F12E8AD,    // 70003E20
+	0x0F120000,    // 70003E22
+	0x0F124778,    // 70003E24
+	0x0F1246C0,    // 70003E26
+	0x0F12C000,    // 70003E28
+	0x0F12E59F,    // 70003E2A
+	0x0F12FF1C,    // 70003E2C
+	0x0F12E12F,    // 70003E2E
+	0x0F1224B9,    // 70003E30
+	0x0F120001,    // 70003E32
+	0x0F124778,    // 70003E34
+	0x0F1246C0,    // 70003E36
+	0x0F12C000,    // 70003E38
+	0x0F12E59F,    // 70003E3A
+	0x0F12FF1C,    // 70003E3C
+	0x0F12E12F,    // 70003E3E
+	0x0F1202EB,    // 70003E40
+	0x0F120001,    // 70003E42
+	// End of Patch Data(Last : 70003EDAh)
+	// Total Size 2480 (09B0)
+	// Addr : 352C , Size : 2478(9AEh)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	//	TNP_GAS_ALPHA_OTP
+	//	TNP_FR_ACCURATE_DYNAMIC
+	//	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F12002E,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F120235,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12024A,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //
+	//         ///
+	// Analog & APS settings         //         //         //         //         /  ///
+	// This register is for FACTORY ONLY. If you change it without prior notificat
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future
+	//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //
+	//         ///
+
+	//============================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//============================================================================
+	//============================= Analog & APS Control =========================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_re
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF462,
+	0x0F120001, // atx_option add 0714
+
+	0x002AF2A5,
+	0x0F1201FF, // atx_width  add 0714
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//============================================================================
+
+	//============================= Line-ADLC Tuning =============================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//============================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuat
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 fo
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for S
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed :
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Curr
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120050,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechan
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active h
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqD
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysD
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviD
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblD
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqD
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysD
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviD
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblD
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqD
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysD
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviD
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblD
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120400, //REG_0TC_PCFG_usWidth
+	0x0F120300, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D
+	0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+#if 1 /* [P4W] fix rotation to 180*/
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#endif
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120005,                   //REG_0TC_CCFG_Format
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29
+	0x0F120010,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// Capture 1 640x480 system 52M PCLK 87M
+	//===================================================================
+	0x002A035A,
+	0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+	0x0F120280,                   //REG_1TC_CCFG_usWidth
+	0x0F1201E0,                   //REG_1TC_CCFG_usHeight
+	0x0F120005,                   //REG_1TC_CCFG_Format
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+	0x002A036A,
+	0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29
+	0x0F120010,                   //REG_1TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+	0x002A0372,
+	0x0F120001,                   //REG_1TC_CCFG_uClockInd
+	0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+	0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_1TC_CCFG_sSaturation
+	0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AF
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+	0x0F123200, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123200, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123200, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123200, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123200, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123200, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F123F00,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 034
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has b
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especi
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120840, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBi
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sdd
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_s
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sdd
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFI
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFI
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFI
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0]
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0]
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFI
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0]
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AF
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0]
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPowe
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFI
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AF
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AF
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFI
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AF
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AF
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   A
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_B
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsha
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_B
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bi
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sB
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBi
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBi
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBi
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sB
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBi
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sdd
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_s
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sdd
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFI
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFI
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFI
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0]
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0]
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFI
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0]
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AF
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0]
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPowe
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFI
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AF
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AF
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFI
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AF
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   A
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_B
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsha
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_B
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bi
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sB
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBi
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBi
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBi
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sB
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBi
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sdd
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_s
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sdd
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFI
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFI
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFI
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0]
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0]
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFI
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0]
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AF
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0]
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPowe
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFI
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AF
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AF
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFI
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AF
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AF
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   A
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_B
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsha
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_B
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bi
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sB
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBi
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBi
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBi
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sB
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBi
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sdd
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_s
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sdd
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFI
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFI
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFI
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0]
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0]
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFI
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0]
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AF
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0]
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPowe
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFI
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AF
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AF
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFI
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AF
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AF
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   A
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_B
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsha
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_B
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bi
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sB
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBi
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBi
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBi
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sB
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_r
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_i
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sdd
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sd
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sdd
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRa
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFI
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sd
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Dem
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFI
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_De
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AF
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sha
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sha
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFI
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_dems
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_de
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_d
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadi
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RG
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_R
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2Y
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_s
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sd
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_s
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sdd
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_D
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AF
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   A
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   A
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFI
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AF
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AF
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  A
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AF
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFI
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AF
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bi
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AF
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFI
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AF
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AF
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+};
+#else
+/* Init regs for Jpeg capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	/*++ Add ESD */
+	0x002A0150,
+	0x0F12AAAA,
+	/*-- Add ESD */
+	0x002A352C,
+	0x0F12B570,    // 7000352C
+	0x0F124A24,    // 7000352E
+	0x0F124924,    // 70003530
+	0x0F124825,    // 70003532
+	0x0F124B25,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124924,    // 7000353E
+	0x0F124824,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FBBD,    // 70003544
+	0x0F124924,    // 70003546
+	0x0F124824,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FBB9,    // 7000354C
+	0x0F124824,    // 7000354E
+	0x0F124E24,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124924,    // 70003554
+	0x0F124825,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FBB2,    // 7000355A
+	0x0F124924,    // 7000355C
+	0x0F120030,    // 7000355E
+	0x0F123080,    // 70003560
+	0x0F126141,    // 70003562
+	0x0F124C23,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124923,    // 70003568
+	0x0F124824,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FBA8,    // 7000356E
+	0x0F124923,    // 70003570
+	0x0F124824,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FBA4,    // 70003576
+	0x0F124923,    // 70003578
+	0x0F124824,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FBA0,    // 7000357E
+	0x0F124923,    // 70003580
+	0x0F124824,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB9C,    // 70003586
+	0x0F128125,    // 70003588
+	0x0F124923,    // 7000358A
+	0x0F124823,    // 7000358C
+	0x0F12F000,    // 7000358E
+	0x0F12FB97,    // 70003590
+	0x0F124923,    // 70003592
+	0x0F124823,    // 70003594
+	0x0F12F000,    // 70003596
+	0x0F12FB93,    // 70003598
+	0x0F1283A5,    // 7000359A
+	0x0F124922,    // 7000359C
+	0x0F124823,    // 7000359E
+	0x0F12F000,    // 700035A0
+	0x0F12FB8E,    // 700035A2
+	0x0F122101,    // 700035A4
+	0x0F120349,    // 700035A6
+	0x0F120020,    // 700035A8
+	0x0F123020,    // 700035AA
+	0x0F128041,    // 700035AC
+	0x0F122185,    // 700035AE
+	0x0F128081,    // 700035B0
+	0x0F12491F,    // 700035B2
+	0x0F1280C1,    // 700035B4
+	0x0F12481F,    // 700035B6
+	0x0F126730,    // 700035B8
+	0x0F12BC70,    // 700035BA
+	0x0F12BC08,    // 700035BC
+	0x0F124718,    // 700035BE
+	0x0F1200CA,    // 700035C0
+	0x0F125CC1,    // 700035C2
+	0x0F1203BD,    // 700035C4
+	0x0F120000,    // 700035C6
+	0x0F121C08,    // 700035C8
+	0x0F127000,    // 700035CA
+	0x0F123290,    // 700035CC
+	0x0F127000,    // 700035CE
+	0x0F123657,    // 700035D0
+	0x0F127000,    // 700035D2
+	0x0F12D9E7,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F12383F,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F12395D,    // 700035DC
+	0x0F120000,    // 700035DE
+	0x0F1238D1,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F120000,    // 700035E4
+	0x0F127000,    // 700035E6
+	0x0F12399D,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F12F903,    // 700035EC
+	0x0F120000,    // 700035EE
+	0x0F123AC1,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F123FC8,    // 700035F4
+	0x0F127000,    // 700035F6
+	0x0F12368F,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12495F,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F1236ED,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F12E421,    // 70003604
+	0x0F120000,    // 70003606
+	0x0F1237AB,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F12216D,    // 7000360C
+	0x0F120000,    // 7000360E
+	0x0F12381F,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F120179,    // 70003614
+	0x0F120001,    // 70003616
+	0x0F123BD5,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F1204C9,    // 7000361C
+	0x0F120000,    // 7000361E
+	0x0F123B25,    // 70003620
+	0x0F127000,    // 70003622
+	0x0F125027,    // 70003624
+	0x0F120000,    // 70003626
+	0x0F123BE1,    // 70003628
+	0x0F127000,    // 7000362A
+	0x0F1242B7,    // 7000362C
+	0x0F120000,    // 7000362E
+	0x0F1207FF,    // 70003630
+	0x0F120000,    // 70003632
+	0x0F123C5F,    // 70003634
+	0x0F127000,    // 70003636
+	0x0F12B570,    // 70003638
+	0x0F12000D,    // 7000363A
+	0x0F124CFC,    // 7000363C
+	0x0F128821,    // 7000363E
+	0x0F12F000,    // 70003640
+	0x0F12FB46,    // 70003642
+	0x0F128820,    // 70003644
+	0x0F124AFB,    // 70003646
+	0x0F120081,    // 70003648
+	0x0F125055,    // 7000364A
+	0x0F121C40,    // 7000364C
+	0x0F128020,    // 7000364E
+	0x0F12BC70,    // 70003650
+	0x0F12BC08,    // 70003652
+	0x0F124718,    // 70003654
+	0x0F126801,    // 70003656
+	0x0F120409,    // 70003658
+	0x0F120C09,    // 7000365A
+	0x0F126840,    // 7000365C
+	0x0F120400,    // 7000365E
+	0x0F120C00,    // 70003660
+	0x0F124AF5,    // 70003662
+	0x0F128992,    // 70003664
+	0x0F122A00,    // 70003666
+	0x0F12D00D,    // 70003668
+	0x0F122300,    // 7000366A
+	0x0F121A80,    // 7000366C
+	0x0F12D400,    // 7000366E
+	0x0F120003,    // 70003670
+	0x0F120418,    // 70003672
+	0x0F120C00,    // 70003674
+	0x0F124BF1,    // 70003676
+	0x0F121851,    // 70003678
+	0x0F12891B,    // 7000367A
+	0x0F12428B,    // 7000367C
+	0x0F12D300,    // 7000367E
+	0x0F12000B,    // 70003680
+	0x0F120419,    // 70003682
+	0x0F120C09,    // 70003684
+	0x0F124AEE,    // 70003686
+	0x0F128151,    // 70003688
+	0x0F128190,    // 7000368A
+	0x0F124770,    // 7000368C
+	0x0F12B510,    // 7000368E
+	0x0F124CEC,    // 70003690
+	0x0F1248ED,    // 70003692
+	0x0F1278A1,    // 70003694
+	0x0F122900,    // 70003696
+	0x0F12D101,    // 70003698
+	0x0F1287C1,    // 7000369A
+	0x0F12E004,    // 7000369C
+	0x0F127AE1,    // 7000369E
+	0x0F122900,    // 700036A0
+	0x0F12D001,    // 700036A2
+	0x0F122101,    // 700036A4
+	0x0F1287C1,    // 700036A6
+	0x0F12F000,    // 700036A8
+	0x0F12FB1A,    // 700036AA
+	0x0F1249E7,    // 700036AC
+	0x0F128B08,    // 700036AE
+	0x0F1206C2,    // 700036B0
+	0x0F12D50A,    // 700036B2
+	0x0F127AA2,    // 700036B4
+	0x0F120652,    // 700036B6
+	0x0F12D507,    // 700036B8
+	0x0F122210,    // 700036BA
+	0x0F124390,    // 700036BC
+	0x0F128308,    // 700036BE
+	0x0F1248E3,    // 700036C0
+	0x0F127AE1,    // 700036C2
+	0x0F126B00,    // 700036C4
+	0x0F12F000,    // 700036C6
+	0x0F12FB13,    // 700036C8
+	0x0F1248DB,    // 700036CA
+	0x0F1289C0,    // 700036CC
+	0x0F122801,    // 700036CE
+	0x0F12D109,    // 700036D0
+	0x0F1278A0,    // 700036D2
+	0x0F122800,    // 700036D4
+	0x0F12D006,    // 700036D6
+	0x0F127AE0,    // 700036D8
+	0x0F122800,    // 700036DA
+	0x0F12D003,    // 700036DC
+	0x0F127AA0,    // 700036DE
+	0x0F122140,    // 700036E0
+	0x0F124308,    // 700036E2
+	0x0F1272A0,    // 700036E4
+	0x0F12BC10,    // 700036E6
+	0x0F12BC08,    // 700036E8
+	0x0F124718,    // 700036EA
+	0x0F12B570,    // 700036EC
+	0x0F124DD7,    // 700036EE
+	0x0F124CD7,    // 700036F0
+	0x0F128B28,    // 700036F2
+	0x0F120701,    // 700036F4
+	0x0F12D507,    // 700036F6
+	0x0F122108,    // 700036F8
+	0x0F124388,    // 700036FA
+	0x0F128328,    // 700036FC
+	0x0F1249D5,    // 700036FE
+	0x0F126B20,    // 70003700
+	0x0F126B89,    // 70003702
+	0x0F12F000,    // 70003704
+	0x0F12FAFC,    // 70003706
+	0x0F128B28,    // 70003708
+	0x0F1206C1,    // 7000370A
+	0x0F12D5A0,    // 7000370C
+	0x0F1249CD,    // 7000370E
+	0x0F127A8A,    // 70003710
+	0x0F120652,    // 70003712
+	0x0F12D49C,    // 70003714
+	0x0F122210,    // 70003716
+	0x0F124390,    // 70003718
+	0x0F128328,    // 7000371A
+	0x0F127AC9,    // 7000371C
+	0x0F126B20,    // 7000371E
+	0x0F12F000,    // 70003720
+	0x0F12FAE6,    // 70003722
+	0x0F12E794,    // 70003724
+	0x0F12B5F8,    // 70003726
+	0x0F1249CB,    // 70003728
+	0x0F128F08,    // 7000372A
+	0x0F12000C,    // 7000372C
+	0x0F123480,    // 7000372E
+	0x0F122800,    // 70003730
+	0x0F12D000,    // 70003732
+	0x0F128360,    // 70003734
+	0x0F122000,    // 70003736
+	0x0F128708,    // 70003738
+	0x0F124DC8,    // 7000373A
+	0x0F1226FF,    // 7000373C
+	0x0F128828,    // 7000373E
+	0x0F121C76,    // 70003740
+	0x0F122702,    // 70003742
+	0x0F122803,    // 70003744
+	0x0F12D112,    // 70003746
+	0x0F128868,    // 70003748
+	0x0F122800,    // 7000374A
+	0x0F12D10F,    // 7000374C
+	0x0F1288E8,    // 7000374E
+	0x0F122800,    // 70003750
+	0x0F12D10C,    // 70003752
+	0x0F12F000,    // 70003754
+	0x0F12FADC,    // 70003756
+	0x0F122800,    // 70003758
+	0x0F12D008,    // 7000375A
+	0x0F128B60,    // 7000375C
+	0x0F122800,    // 7000375E
+	0x0F12D001,    // 70003760
+	0x0F1280EE,    // 70003762
+	0x0F1280AF,    // 70003764
+	0x0F122001,    // 70003766
+	0x0F127268,    // 70003768
+	0x0F12F000,    // 7000376A
+	0x0F12FAD9,    // 7000376C
+	0x0F128828,    // 7000376E
+	0x0F122802,    // 70003770
+	0x0F12D10E,    // 70003772
+	0x0F128868,    // 70003774
+	0x0F122800,    // 70003776
+	0x0F12D10B,    // 70003778
+	0x0F1288E8,    // 7000377A
+	0x0F122800,    // 7000377C
+	0x0F12D108,    // 7000377E
+	0x0F128B60,    // 70003780
+	0x0F122800,    // 70003782
+	0x0F12D001,    // 70003784
+	0x0F1280EE,    // 70003786
+	0x0F1280AF,    // 70003788
+	0x0F122001,    // 7000378A
+	0x0F127268,    // 7000378C
+	0x0F12F000,    // 7000378E
+	0x0F12FAC7,    // 70003790
+	0x0F1288E8,    // 70003792
+	0x0F122800,    // 70003794
+	0x0F12D006,    // 70003796
+	0x0F121FC1,    // 70003798
+	0x0F1239FD,    // 7000379A
+	0x0F12D003,    // 7000379C
+	0x0F122001,    // 7000379E
+	0x0F12BCF8,    // 700037A0
+	0x0F12BC08,    // 700037A2
+	0x0F124718,    // 700037A4
+	0x0F122000,    // 700037A6
+	0x0F12E7FA,    // 700037A8
+	0x0F12B570,    // 700037AA
+	0x0F124CAC,    // 700037AC
+	0x0F128860,    // 700037AE
+	0x0F122800,    // 700037B0
+	0x0F12D00C,    // 700037B2
+	0x0F128820,    // 700037B4
+	0x0F124DA3,    // 700037B6
+	0x0F122800,    // 700037B8
+	0x0F12D009,    // 700037BA
+	0x0F120029,    // 700037BC
+	0x0F1231A0,    // 700037BE
+	0x0F127AC9,    // 700037C0
+	0x0F122900,    // 700037C2
+	0x0F12D004,    // 700037C4
+	0x0F127AA8,    // 700037C6
+	0x0F122180,    // 700037C8
+	0x0F124308,    // 700037CA
+	0x0F1272A8,    // 700037CC
+	0x0F12E73F,    // 700037CE
+	0x0F122800,    // 700037D0
+	0x0F12D003,    // 700037D2
+	0x0F12F7FF,    // 700037D4
+	0x0F12FFA7,    // 700037D6
+	0x0F122800,    // 700037D8
+	0x0F12D1F8,    // 700037DA
+	0x0F122000,    // 700037DC
+	0x0F128060,    // 700037DE
+	0x0F128820,    // 700037E0
+	0x0F122800,    // 700037E2
+	0x0F12D003,    // 700037E4
+	0x0F122008,    // 700037E6
+	0x0F12F000,    // 700037E8
+	0x0F12FAA2,    // 700037EA
+	0x0F12E00B,    // 700037EC
+	0x0F12489C,    // 700037EE
+	0x0F123020,    // 700037F0
+	0x0F128880,    // 700037F2
+	0x0F122800,    // 700037F4
+	0x0F12D103,    // 700037F6
+	0x0F127AA8,    // 700037F8
+	0x0F122101,    // 700037FA
+	0x0F124308,    // 700037FC
+	0x0F1272A8,    // 700037FE
+	0x0F122010,    // 70003800
+	0x0F12F000,    // 70003802
+	0x0F12FA95,    // 70003804
+	0x0F128820,    // 70003806
+	0x0F122800,    // 70003808
+	0x0F12D1E0,    // 7000380A
+	0x0F12488A,    // 7000380C
+	0x0F1289C0,    // 7000380E
+	0x0F122801,    // 70003810
+	0x0F12D1DC,    // 70003812
+	0x0F127AA8,    // 70003814
+	0x0F1221BF,    // 70003816
+	0x0F124008,    // 70003818
+	0x0F1272A8,    // 7000381A
+	0x0F12E718,    // 7000381C
+	0x0F126800,    // 7000381E
+	0x0F124990,    // 70003820
+	0x0F128188,    // 70003822
+	0x0F124890,    // 70003824
+	0x0F122201,    // 70003826
+	0x0F128981,    // 70003828
+	0x0F124890,    // 7000382A
+	0x0F120252,    // 7000382C
+	0x0F124291,    // 7000382E
+	0x0F12D902,    // 70003830
+	0x0F122102,    // 70003832
+	0x0F128181,    // 70003834
+	0x0F124770,    // 70003836
+	0x0F122101,    // 70003838
+	0x0F128181,    // 7000383A
+	0x0F124770,    // 7000383C
+	0x0F12B5F1,    // 7000383E
+	0x0F124E80,    // 70003840
+	0x0F128834,    // 70003842
+	0x0F122C00,    // 70003844
+	0x0F12D03F,    // 70003846
+	0x0F122001,    // 70003848
+	0x0F122C08,    // 7000384A
+	0x0F12D000,    // 7000384C
+	0x0F122000,    // 7000384E
+	0x0F1270B0,    // 70003850
+	0x0F124D7F,    // 70003852
+	0x0F122800,    // 70003854
+	0x0F12D009,    // 70003856
+	0x0F12F000,    // 70003858
+	0x0F12FA72,    // 7000385A
+	0x0F120028,    // 7000385C
+	0x0F1238F0,    // 7000385E
+	0x0F126328,    // 70003860
+	0x0F127AB0,    // 70003862
+	0x0F12217E,    // 70003864
+	0x0F124008,    // 70003866
+	0x0F1272B0,    // 70003868
+	0x0F12E00F,    // 7000386A
+	0x0F124F7A,    // 7000386C
+	0x0F123780,    // 7000386E
+	0x0F128B78,    // 70003870
+	0x0F122800,    // 70003872
+	0x0F12D005,    // 70003874
+	0x0F12F000,    // 70003876
+	0x0F12FA6B,    // 70003878
+	0x0F122000,    // 7000387A
+	0x0F128378,    // 7000387C
+	0x0F124976,    // 7000387E
+	0x0F128708,    // 70003880
+	0x0F122000,    // 70003882
+	0x0F12F000,    // 70003884
+	0x0F12FA6C,    // 70003886
+	0x0F124879,    // 70003888
+	0x0F126328,    // 7000388A
+	0x0F1278B1,    // 7000388C
+	0x0F122700,    // 7000388E
+	0x0F120038,    // 70003890
+	0x0F122900,    // 70003892
+	0x0F12D008,    // 70003894
+	0x0F124972,    // 70003896
+	0x0F123920,    // 70003898
+	0x0F128ACA,    // 7000389A
+	0x0F122A00,    // 7000389C
+	0x0F12D003,    // 7000389E
+	0x0F128B09,    // 700038A0
+	0x0F122900,    // 700038A2
+	0x0F12D000,    // 700038A4
+	0x0F122001,    // 700038A6
+	0x0F127170,    // 700038A8
+	0x0F122C02,    // 700038AA
+	0x0F12D102,    // 700038AC
+	0x0F124868,    // 700038AE
+	0x0F123860,    // 700038B0
+	0x0F126328,    // 700038B2
+	0x0F122201,    // 700038B4
+	0x0F122C02,    // 700038B6
+	0x0F12D000,    // 700038B8
+	0x0F122200,    // 700038BA
+	0x0F124861,    // 700038BC
+	0x0F122110,    // 700038BE
+	0x0F12300A,    // 700038C0
+	0x0F12F000,    // 700038C2
+	0x0F12FA55,    // 700038C4
+	0x0F128037,    // 700038C6
+	0x0F129900,    // 700038C8
+	0x0F120020,    // 700038CA
+	0x0F12600C,    // 700038CC
+	0x0F12E767,    // 700038CE
+	0x0F12B538,    // 700038D0
+	0x0F124865,    // 700038D2
+	0x0F124669,    // 700038D4
+	0x0F123848,    // 700038D6
+	0x0F12F000,    // 700038D8
+	0x0F12FA52,    // 700038DA
+	0x0F124A5E,    // 700038DC
+	0x0F124862,    // 700038DE
+	0x0F128F51,    // 700038E0
+	0x0F122400,    // 700038E2
+	0x0F123020,    // 700038E4
+	0x0F122900,    // 700038E6
+	0x0F12D00A,    // 700038E8
+	0x0F128754,    // 700038EA
+	0x0F126941,    // 700038EC
+	0x0F126451,    // 700038EE
+	0x0F126491,    // 700038F0
+	0x0F12466B,    // 700038F2
+	0x0F128819,    // 700038F4
+	0x0F1287D1,    // 700038F6
+	0x0F12885B,    // 700038F8
+	0x0F120011,    // 700038FA
+	0x0F123140,    // 700038FC
+	0x0F12800B,    // 700038FE
+	0x0F128F91,    // 70003900
+	0x0F122900,    // 70003902
+	0x0F12D002,    // 70003904
+	0x0F128794,    // 70003906
+	0x0F126940,    // 70003908
+	0x0F126490,    // 7000390A
+	0x0F12F000,    // 7000390C
+	0x0F12FA40,    // 7000390E
+	0x0F12BC38,    // 70003910
+	0x0F12BC08,    // 70003912
+	0x0F124718,    // 70003914
+	0x0F12B5F8,    // 70003916
+	0x0F124C56,    // 70003918
+	0x0F1289E0,    // 7000391A
+	0x0F12F000,    // 7000391C
+	0x0F12FA40,    // 7000391E
+	0x0F120006,    // 70003920
+	0x0F128A20,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA44,    // 70003926
+	0x0F120007,    // 70003928
+	0x0F12484F,    // 7000392A
+	0x0F124D4A,    // 7000392C
+	0x0F123020,    // 7000392E
+	0x0F126CA9,    // 70003930
+	0x0F126940,    // 70003932
+	0x0F121809,    // 70003934
+	0x0F120200,    // 70003936
+	0x0F12F000,    // 70003938
+	0x0F12FA42,    // 7000393A
+	0x0F120400,    // 7000393C
+	0x0F120C00,    // 7000393E
+	0x0F12002A,    // 70003940
+	0x0F12326E,    // 70003942
+	0x0F120011,    // 70003944
+	0x0F12390A,    // 70003946
+	0x0F122305,    // 70003948
+	0x0F12F000,    // 7000394A
+	0x0F12FA3F,    // 7000394C
+	0x0F124C43,    // 7000394E
+	0x0F1261A0,    // 70003950
+	0x0F128FEB,    // 70003952
+	0x0F120002,    // 70003954
+	0x0F120031,    // 70003956
+	0x0F120018,    // 70003958
+	0x0F12F000,    // 7000395A
+	0x0F12FA3F,    // 7000395C
+	0x0F12466B,    // 7000395E
+	0x0F120005,    // 70003960
+	0x0F128018,    // 70003962
+	0x0F12483C,    // 70003964
+	0x0F1269A2,    // 70003966
+	0x0F123040,    // 70003968
+	0x0F128800,    // 7000396A
+	0x0F120039,    // 7000396C
+	0x0F12F000,    // 7000396E
+	0x0F12FA35,    // 70003970
+	0x0F12466B,    // 70003972
+	0x0F120006,    // 70003974
+	0x0F128058,    // 70003976
+	0x0F120021,    // 70003978
+	0x0F129800,    // 7000397A
+	0x0F12311C,    // 7000397C
+	0x0F12F000,    // 7000397E
+	0x0F12FA35,    // 70003980
+	0x0F124935,    // 70003982
+	0x0F123180,    // 70003984
+	0x0F12808D,    // 70003986
+	0x0F1280CE,    // 70003988
+	0x0F128BA1,    // 7000398A
+	0x0F124836,    // 7000398C
+	0x0F123820,    // 7000398E
+	0x0F128001,    // 70003990
+	0x0F128BE1,    // 70003992
+	0x0F128041,    // 70003994
+	0x0F128C21,    // 70003996
+	0x0F128081,    // 70003998
+	0x0F12E701,    // 7000399A
+	0x0F12B5F8,    // 7000399C
+	0x0F124E2E,    // 7000399E
+	0x0F126C70,    // 700039A0
+	0x0F126CB1,    // 700039A2
+	0x0F120200,    // 700039A4
+	0x0F12F000,    // 700039A6
+	0x0F12FA0B,    // 700039A8
+	0x0F120400,    // 700039AA
+	0x0F120C00,    // 700039AC
+	0x0F122401,    // 700039AE
+	0x0F120364,    // 700039B0
+	0x0F1242A0,    // 700039B2
+	0x0F12D200,    // 700039B4
+	0x0F120004,    // 700039B6
+	0x0F124A27,    // 700039B8
+	0x0F120020,    // 700039BA
+	0x0F12327E,    // 700039BC
+	0x0F121F91,    // 700039BE
+	0x0F122303,    // 700039C0
+	0x0F12F000,    // 700039C2
+	0x0F12FA03,    // 700039C4
+	0x0F120405,    // 700039C6
+	0x0F120C2D,    // 700039C8
+	0x0F124A23,    // 700039CA
+	0x0F120020,    // 700039CC
+	0x0F12325A,    // 700039CE
+	0x0F120011,    // 700039D0
+	0x0F12390A,    // 700039D2
+	0x0F122305,    // 700039D4
+	0x0F12F000,    // 700039D6
+	0x0F12F9F9,    // 700039D8
+	0x0F12491F,    // 700039DA
+	0x0F1264C8,    // 700039DC
+	0x0F12491F,    // 700039DE
+	0x0F124E21,    // 700039E0
+	0x0F1288C8,    // 700039E2
+	0x0F122701,    // 700039E4
+	0x0F122800,    // 700039E6
+	0x0F12D009,    // 700039E8
+	0x0F124C23,    // 700039EA
+	0x0F1238FF,    // 700039EC
+	0x0F121E40,    // 700039EE
+	0x0F12D00A,    // 700039F0
+	0x0F122804,    // 700039F2
+	0x0F12D042,    // 700039F4
+	0x0F122806,    // 700039F6
+	0x0F12D101,    // 700039F8
+	0x0F122000,    // 700039FA
+	0x0F1280C8,    // 700039FC
+	0x0F1282B7,    // 700039FE
+	0x0F122001,    // 70003A00
+	0x0F12F000,    // 70003A02
+	0x0F12F9FB,    // 70003A04
+	0x0F12E6CB,    // 70003A06
+	0x0F12000D,    // 70003A08
+	0x0F12724F,    // 70003A0A
+	0x0F122001,    // 70003A0C
+	0x0F12F000,    // 70003A0E
+	0x0F12F9FD,    // 70003A10
+	0x0F12F000,    // 70003A12
+	0x0F12FA03,    // 70003A14
+	0x0F124910,    // 70003A16
+	0x0F123148,    // 70003A18
+	0x0F12C903,    // 70003A1A
+	0x0F124348,    // 70003A1C
+	0x0F120A00,    // 70003A1E
+	0x0F126160,    // 70003A20
+	0x0F1220FF,    // 70003A22
+	0x0F121D40,    // 70003A24
+	0x0F1280E8,    // 70003A26
+	0x0F12480C,    // 70003A28
+	0x0F123040,    // 70003A2A
+	0x0F127707,    // 70003A2C
+	0x0F12E7E6,    // 70003A2E
+	0x0F123290,    // 70003A30
+	0x0F127000,    // 70003A32
+	0x0F123294,    // 70003A34
+	0x0F127000,    // 70003A36
+	0x0F1204A8,    // 70003A38
+	0x0F127000,    // 70003A3A
+	0x0F1215DC,    // 70003A3C
+	0x0F127000,    // 70003A3E
+	0x0F125000,    // 70003A40
+	0x0F12D000,    // 70003A42
+	0x0F121E84,    // 70003A44
+	0x0F127000,    // 70003A46
+	0x0F121BE4,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F122EA8,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F1221A4,    // 70003A50
+	0x0F127000,    // 70003A52
+	0x0F120100,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F123F48,    // 70003A58
+	0x0F127000,    // 70003A5A
+	0x0F1231A0,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F1201E8,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F12F2A0,    // 70003A64
+	0x0F12D000,    // 70003A66
+	0x0F122A44,    // 70003A68
+	0x0F127000,    // 70003A6A
+	0x0F12F400,    // 70003A6C
+	0x0F12D000,    // 70003A6E
+	0x0F122024,    // 70003A70
+	0x0F127000,    // 70003A72
+	0x0F121650,    // 70003A74
+	0x0F127000,    // 70003A76
+	0x0F122A64,    // 70003A78
+	0x0F127000,    // 70003A7A
+	0x0F124982,    // 70003A7C
+	0x0F12724F,    // 70003A7E
+	0x0F1220FF,    // 70003A80
+	0x0F121DC0,    // 70003A82
+	0x0F1280C8,    // 70003A84
+	0x0F12F000,    // 70003A86
+	0x0F12F9D1,    // 70003A88
+	0x0F124980,    // 70003A8A
+	0x0F126ACA,    // 70003A8C
+	0x0F12604A,    // 70003A8E
+	0x0F122800,    // 70003A90
+	0x0F12D006,    // 70003A92
+	0x0F12436A,    // 70003A94
+	0x0F120001,    // 70003A96
+	0x0F120010,    // 70003A98
+	0x0F12F000,    // 70003A9A
+	0x0F12F991,    // 70003A9C
+	0x0F126160,    // 70003A9E
+	0x0F12E001,    // 70003AA0
+	0x0F12436A,    // 70003AA2
+	0x0F126162,    // 70003AA4
+	0x0F128BF0,    // 70003AA6
+	0x0F122800,    // 70003AA8
+	0x0F12D001,    // 70003AAA
+	0x0F12F7FF,    // 70003AAC
+	0x0F12FF33,    // 70003AAE
+	0x0F122000,    // 70003AB0
+	0x0F12F000,    // 70003AB2
+	0x0F12F9AB,    // 70003AB4
+	0x0F124974,    // 70003AB6
+	0x0F1220FF,    // 70003AB8
+	0x0F121DC0,    // 70003ABA
+	0x0F1280C8,    // 70003ABC
+	0x0F12E79E,    // 70003ABE
+	0x0F12B510,    // 70003AC0
+	0x0F12F000,    // 70003AC2
+	0x0F12F9BB,    // 70003AC4
+	0x0F124870,    // 70003AC6
+	0x0F1288C0,    // 70003AC8
+	0x0F121FC1,    // 70003ACA
+	0x0F1239FD,    // 70003ACC
+	0x0F12D103,    // 70003ACE
+	0x0F12496F,    // 70003AD0
+	0x0F1220FF,    // 70003AD2
+	0x0F121C40,    // 70003AD4
+	0x0F128048,    // 70003AD6
+	0x0F12E605,    // 70003AD8
+	0x0F12B5F8,    // 70003ADA
+	0x0F122400,    // 70003ADC
+	0x0F124D6D,    // 70003ADE
+	0x0F12486D,    // 70003AE0
+	0x0F12210E,    // 70003AE2
+	0x0F128041,    // 70003AE4
+	0x0F122101,    // 70003AE6
+	0x0F128001,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F9AF,    // 70003AEC
+	0x0F12486B,    // 70003AEE
+	0x0F128840,    // 70003AF0
+	0x0F12F000,    // 70003AF2
+	0x0F12F9B3,    // 70003AF4
+	0x0F124E6A,    // 70003AF6
+	0x0F12270D,    // 70003AF8
+	0x0F12073F,    // 70003AFA
+	0x0F1219E8,    // 70003AFC
+	0x0F128803,    // 70003AFE
+	0x0F1200E2,    // 70003B00
+	0x0F121991,    // 70003B02
+	0x0F12804B,    // 70003B04
+	0x0F128843,    // 70003B06
+	0x0F1252B3,    // 70003B08
+	0x0F128882,    // 70003B0A
+	0x0F1280CA,    // 70003B0C
+	0x0F1288C0,    // 70003B0E
+	0x0F128088,    // 70003B10
+	0x0F123508,    // 70003B12
+	0x0F12042D,    // 70003B14
+	0x0F120C2D,    // 70003B16
+	0x0F121C64,    // 70003B18
+	0x0F120424,    // 70003B1A
+	0x0F120C24,    // 70003B1C
+	0x0F122C07,    // 70003B1E
+	0x0F12D3EC,    // 70003B20
+	0x0F12E63D,    // 70003B22
+	0x0F12B5F0,    // 70003B24
+	0x0F12B085,    // 70003B26
+	0x0F126801,    // 70003B28
+	0x0F129103,    // 70003B2A
+	0x0F126881,    // 70003B2C
+	0x0F12040A,    // 70003B2E
+	0x0F120C12,    // 70003B30
+	0x0F12495C,    // 70003B32
+	0x0F128B89,    // 70003B34
+	0x0F122900,    // 70003B36
+	0x0F12D001,    // 70003B38
+	0x0F120011,    // 70003B3A
+	0x0F12E000,    // 70003B3C
+	0x0F122100,    // 70003B3E
+	0x0F129102,    // 70003B40
+	0x0F126840,    // 70003B42
+	0x0F120401,    // 70003B44
+	0x0F129803,    // 70003B46
+	0x0F120C09,    // 70003B48
+	0x0F12F000,    // 70003B4A
+	0x0F12F98F,    // 70003B4C
+	0x0F124854,    // 70003B4E
+	0x0F123080,    // 70003B50
+	0x0F128900,    // 70003B52
+	0x0F122800,    // 70003B54
+	0x0F12D039,    // 70003B56
+	0x0F122100,    // 70003B58
+	0x0F124854,    // 70003B5A
+	0x0F124D52,    // 70003B5C
+	0x0F124684,    // 70003B5E
+	0x0F124B53,    // 70003B60
+	0x0F124C4F,    // 70003B62
+	0x0F1288DA,    // 70003B64
+	0x0F120048,    // 70003B66
+	0x0F1200D7,    // 70003B68
+	0x0F12193E,    // 70003B6A
+	0x0F12197F,    // 70003B6C
+	0x0F12183F,    // 70003B6E
+	0x0F125A36,    // 70003B70
+	0x0F128AFF,    // 70003B72
+	0x0F12437E,    // 70003B74
+	0x0F1200B6,    // 70003B76
+	0x0F120C37,    // 70003B78
+	0x0F121906,    // 70003B7A
+	0x0F123680,    // 70003B7C
+	0x0F128177,    // 70003B7E
+	0x0F121C52,    // 70003B80
+	0x0F1200D2,    // 70003B82
+	0x0F121914,    // 70003B84
+	0x0F121952,    // 70003B86
+	0x0F121812,    // 70003B88
+	0x0F125A24,    // 70003B8A
+	0x0F128AD2,    // 70003B8C
+	0x0F124354,    // 70003B8E
+	0x0F1200A2,    // 70003B90
+	0x0F120C12,    // 70003B92
+	0x0F128272,    // 70003B94
+	0x0F12891C,    // 70003B96
+	0x0F12895B,    // 70003B98
+	0x0F124367,    // 70003B9A
+	0x0F12435A,    // 70003B9C
+	0x0F121943,    // 70003B9E
+	0x0F123340,    // 70003BA0
+	0x0F1289DB,    // 70003BA2
+	0x0F129C02,    // 70003BA4
+	0x0F1218BA,    // 70003BA6
+	0x0F124363,    // 70003BA8
+	0x0F1218D2,    // 70003BAA
+	0x0F120212,    // 70003BAC
+	0x0F120C12,    // 70003BAE
+	0x0F12466B,    // 70003BB0
+	0x0F12521A,    // 70003BB2
+	0x0F124663,    // 70003BB4
+	0x0F127DDB,    // 70003BB6
+	0x0F12435A,    // 70003BB8
+	0x0F129B03,    // 70003BBA
+	0x0F120252,    // 70003BBC
+	0x0F120C12,    // 70003BBE
+	0x0F12521A,    // 70003BC0
+	0x0F121C49,    // 70003BC2
+	0x0F120409,    // 70003BC4
+	0x0F120C09,    // 70003BC6
+	0x0F122904,    // 70003BC8
+	0x0F12D3C9,    // 70003BCA
+	0x0F12B005,    // 70003BCC
+	0x0F12BCF0,    // 70003BCE
+	0x0F12BC08,    // 70003BD0
+	0x0F124718,    // 70003BD2
+	0x0F12B510,    // 70003BD4
+	0x0F12F7FF,    // 70003BD6
+	0x0F12FF80,    // 70003BD8
+	0x0F12F000,    // 70003BDA
+	0x0F12F94F,    // 70003BDC
+	0x0F12E582,    // 70003BDE
+	0x0F12B570,    // 70003BE0
+	0x0F126804,    // 70003BE2
+	0x0F12F000,    // 70003BE4
+	0x0F12F952,    // 70003BE6
+	0x0F124D32,    // 70003BE8
+	0x0F128C29,    // 70003BEA
+	0x0F121A40,    // 70003BEC
+	0x0F1242A0,    // 70003BEE
+	0x0F12D901,    // 70003BF0
+	0x0F120020,    // 70003BF2
+	0x0F12E003,    // 70003BF4
+	0x0F12F000,    // 70003BF6
+	0x0F12F949,    // 70003BF8
+	0x0F128C29,    // 70003BFA
+	0x0F121A40,    // 70003BFC
+	0x0F126268,    // 70003BFE
+	0x0F12F000,    // 70003C00
+	0x0F12F94C,    // 70003C02
+	0x0F1262A8,    // 70003C04
+	0x0F12F000,    // 70003C06
+	0x0F12F951,    // 70003C08
+	0x0F126328,    // 70003C0A
+	0x0F128869,    // 70003C0C
+	0x0F122900,    // 70003C0E
+	0x0F12D000,    // 70003C10
+	0x0F1262A8,    // 70003C12
+	0x0F124828,    // 70003C14
+	0x0F126B00,    // 70003C16
+	0x0F128C00,    // 70003C18
+	0x0F122800,    // 70003C1A
+	0x0F12D11B,    // 70003C1C
+	0x0F126AA8,    // 70003C1E
+	0x0F12F000,    // 70003C20
+	0x0F12F94C,    // 70003C22
+	0x0F1261E8,    // 70003C24
+	0x0F124A1E,    // 70003C26
+	0x0F123280,    // 70003C28
+	0x0F128B91,    // 70003C2A
+	0x0F122900,    // 70003C2C
+	0x0F12D00B,    // 70003C2E
+	0x0F120011,    // 70003C30
+	0x0F123120,    // 70003C32
+	0x0F128809,    // 70003C34
+	0x0F124288,    // 70003C36
+	0x0F12D907,    // 70003C38
+	0x0F1261E9,    // 70003C3A
+	0x0F128C28,    // 70003C3C
+	0x0F121A08,    // 70003C3E
+	0x0F1262A8,    // 70003C40
+	0x0F12F000,    // 70003C42
+	0x0F12F92B,    // 70003C44
+	0x0F1262A8,    // 70003C46
+	0x0F12E502,    // 70003C48
+	0x0F128BD1,    // 70003C4A
+	0x0F124288,    // 70003C4C
+	0x0F12D800,    // 70003C4E
+	0x0F120008,    // 70003C50
+	0x0F1261E8,    // 70003C52
+	0x0F12E4FC,    // 70003C54
+	0x0F12F000,    // 70003C56
+	0x0F12F919,    // 70003C58
+	0x0F1261E8,    // 70003C5A
+	0x0F12E4F8,    // 70003C5C
+	0x0F12B510,    // 70003C5E
+	0x0F12F000,    // 70003C60
+	0x0F12F934,    // 70003C62
+	0x0F12480E,    // 70003C64
+	0x0F1230A0,    // 70003C66
+	0x0F128841,    // 70003C68
+	0x0F122900,    // 70003C6A
+	0x0F12D007,    // 70003C6C
+	0x0F124A07,    // 70003C6E
+	0x0F123280,    // 70003C70
+	0x0F126953,    // 70003C72
+	0x0F124A11,    // 70003C74
+	0x0F12428B,    // 70003C76
+	0x0F12D202,    // 70003C78
+	0x0F128880,    // 70003C7A
+	0x0F1281D0,    // 70003C7C
+	0x0F12E532,    // 70003C7E
+	0x0F1288C0,    // 70003C80
+	0x0F1281D0,    // 70003C82
+	0x0F12E52F,    // 70003C84
+	0x0F120000,    // 70003C86
+	0x0F1231A0,    // 70003C88
+	0x0F127000,    // 70003C8A
+	0x0F1229E4,    // 70003C8C
+	0x0F127000,    // 70003C8E
+	0x0F12C100,    // 70003C90
+	0x0F12D000,    // 70003C92
+	0x0F12A006,    // 70003C94
+	0x0F120000,    // 70003C96
+	0x0F12A000,    // 70003C98
+	0x0F12D000,    // 70003C9A
+	0x0F12064C,    // 70003C9C
+	0x0F127000,    // 70003C9E
+	0x0F123F48,    // 70003CA0
+	0x0F127000,    // 70003CA2
+	0x0F1207C4,    // 70003CA4
+	0x0F127000,    // 70003CA6
+	0x0F1207E8,    // 70003CA8
+	0x0F127000,    // 70003CAA
+	0x0F122B24,    // 70003CAC
+	0x0F127000,    // 70003CAE
+	0x0F121FA0,    // 70003CB0
+	0x0F127000,    // 70003CB2
+	0x0F121E3C,    // 70003CB4
+	0x0F127000,    // 70003CB6
+	0x0F1221A4,    // 70003CB8
+	0x0F127000,    // 70003CBA
+	0x0F12E200,    // 70003CBC
+	0x0F12D000,    // 70003CBE
+	0x0F124778,    // 70003CC0
+	0x0F1246C0,    // 70003CC2
+	0x0F12C000,    // 70003CC4
+	0x0F12E59F,    // 70003CC6
+	0x0F12FF1C,    // 70003CC8
+	0x0F12E12F,    // 70003CCA
+	0x0F121F63,    // 70003CCC
+	0x0F120001,    // 70003CCE
+	0x0F124778,    // 70003CD0
+	0x0F1246C0,    // 70003CD2
+	0x0F12C000,    // 70003CD4
+	0x0F12E59F,    // 70003CD6
+	0x0F12FF1C,    // 70003CD8
+	0x0F12E12F,    // 70003CDA
+	0x0F121EDF,    // 70003CDC
+	0x0F120001,    // 70003CDE
+	0x0F124778,    // 70003CE0
+	0x0F1246C0,    // 70003CE2
+	0x0F12C000,    // 70003CE4
+	0x0F12E59F,    // 70003CE6
+	0x0F12FF1C,    // 70003CE8
+	0x0F12E12F,    // 70003CEA
+	0x0F12495F,    // 70003CEC
+	0x0F120000,    // 70003CEE
+	0x0F124778,    // 70003CF0
+	0x0F1246C0,    // 70003CF2
+	0x0F12C000,    // 70003CF4
+	0x0F12E59F,    // 70003CF6
+	0x0F12FF1C,    // 70003CF8
+	0x0F12E12F,    // 70003CFA
+	0x0F12E403,    // 70003CFC
+	0x0F120000,    // 70003CFE
+	0x0F124778,    // 70003D00
+	0x0F1246C0,    // 70003D02
+	0x0F12C000,    // 70003D04
+	0x0F12E59F,    // 70003D06
+	0x0F12FF1C,    // 70003D08
+	0x0F12E12F,    // 70003D0A
+	0x0F1224B3,    // 70003D0C
+	0x0F120001,    // 70003D0E
+	0x0F124778,    // 70003D10
+	0x0F1246C0,    // 70003D12
+	0x0F12C000,    // 70003D14
+	0x0F12E59F,    // 70003D16
+	0x0F12FF1C,    // 70003D18
+	0x0F12E12F,    // 70003D1A
+	0x0F12EECD,    // 70003D1C
+	0x0F120000,    // 70003D1E
+	0x0F124778,    // 70003D20
+	0x0F1246C0,    // 70003D22
+	0x0F12C000,    // 70003D24
+	0x0F12E59F,    // 70003D26
+	0x0F12FF1C,    // 70003D28
+	0x0F12E12F,    // 70003D2A
+	0x0F12F049,    // 70003D2C
+	0x0F120000,    // 70003D2E
+	0x0F124778,    // 70003D30
+	0x0F1246C0,    // 70003D32
+	0x0F12C000,    // 70003D34
+	0x0F12E59F,    // 70003D36
+	0x0F12FF1C,    // 70003D38
+	0x0F12E12F,    // 70003D3A
+	0x0F1212DF,    // 70003D3C
+	0x0F120000,    // 70003D3E
+	0x0F124778,    // 70003D40
+	0x0F1246C0,    // 70003D42
+	0x0F12C000,    // 70003D44
+	0x0F12E59F,    // 70003D46
+	0x0F12FF1C,    // 70003D48
+	0x0F12E12F,    // 70003D4A
+	0x0F12F05B,    // 70003D4C
+	0x0F120000,    // 70003D4E
+	0x0F124778,    // 70003D50
+	0x0F1246C0,    // 70003D52
+	0x0F12C000,    // 70003D54
+	0x0F12E59F,    // 70003D56
+	0x0F12FF1C,    // 70003D58
+	0x0F12E12F,    // 70003D5A
+	0x0F12F07B,    // 70003D5C
+	0x0F120000,    // 70003D5E
+	0x0F124778,    // 70003D60
+	0x0F1246C0,    // 70003D62
+	0x0F12C000,    // 70003D64
+	0x0F12E59F,    // 70003D66
+	0x0F12FF1C,    // 70003D68
+	0x0F12E12F,    // 70003D6A
+	0x0F12FE6D,    // 70003D6C
+	0x0F120000,    // 70003D6E
+	0x0F124778,    // 70003D70
+	0x0F1246C0,    // 70003D72
+	0x0F12C000,    // 70003D74
+	0x0F12E59F,    // 70003D76
+	0x0F12FF1C,    // 70003D78
+	0x0F12E12F,    // 70003D7A
+	0x0F123295,    // 70003D7C
+	0x0F120000,    // 70003D7E
+	0x0F124778,    // 70003D80
+	0x0F1246C0,    // 70003D82
+	0x0F12C000,    // 70003D84
+	0x0F12E59F,    // 70003D86
+	0x0F12FF1C,    // 70003D88
+	0x0F12E12F,    // 70003D8A
+	0x0F12234F,    // 70003D8C
+	0x0F120000,    // 70003D8E
+	0x0F124778,    // 70003D90
+	0x0F1246C0,    // 70003D92
+	0x0F12C000,    // 70003D94
+	0x0F12E59F,    // 70003D96
+	0x0F12FF1C,    // 70003D98
+	0x0F12E12F,    // 70003D9A
+	0x0F124521,    // 70003D9C
+	0x0F120000,    // 70003D9E
+	0x0F124778,    // 70003DA0
+	0x0F1246C0,    // 70003DA2
+	0x0F12C000,    // 70003DA4
+	0x0F12E59F,    // 70003DA6
+	0x0F12FF1C,    // 70003DA8
+	0x0F12E12F,    // 70003DAA
+	0x0F127C0D,    // 70003DAC
+	0x0F120000,    // 70003DAE
+	0x0F124778,    // 70003DB0
+	0x0F1246C0,    // 70003DB2
+	0x0F12C000,    // 70003DB4
+	0x0F12E59F,    // 70003DB6
+	0x0F12FF1C,    // 70003DB8
+	0x0F12E12F,    // 70003DBA
+	0x0F127C2B,    // 70003DBC
+	0x0F120000,    // 70003DBE
+	0x0F124778,    // 70003DC0
+	0x0F1246C0,    // 70003DC2
+	0x0F12F004,    // 70003DC4
+	0x0F12E51F,    // 70003DC6
+	0x0F1224C4,    // 70003DC8
+	0x0F120001,    // 70003DCA
+	0x0F124778,    // 70003DCC
+	0x0F1246C0,    // 70003DCE
+	0x0F12C000,    // 70003DD0
+	0x0F12E59F,    // 70003DD2
+	0x0F12FF1C,    // 70003DD4
+	0x0F12E12F,    // 70003DD6
+	0x0F123183,    // 70003DD8
+	0x0F120000,    // 70003DDA
+	0x0F124778,    // 70003DDC
+	0x0F1246C0,    // 70003DDE
+	0x0F12C000,    // 70003DE0
+	0x0F12E59F,    // 70003DE2
+	0x0F12FF1C,    // 70003DE4
+	0x0F12E12F,    // 70003DE6
+	0x0F12302F,    // 70003DE8
+	0x0F120000,    // 70003DEA
+	0x0F124778,    // 70003DEC
+	0x0F1246C0,    // 70003DEE
+	0x0F12C000,    // 70003DF0
+	0x0F12E59F,    // 70003DF2
+	0x0F12FF1C,    // 70003DF4
+	0x0F12E12F,    // 70003DF6
+	0x0F12EF07,    // 70003DF8
+	0x0F120000,    // 70003DFA
+	0x0F124778,    // 70003DFC
+	0x0F1246C0,    // 70003DFE
+	0x0F12C000,    // 70003E00
+	0x0F12E59F,    // 70003E02
+	0x0F12FF1C,    // 70003E04
+	0x0F12E12F,    // 70003E06
+	0x0F1248FB,    // 70003E08
+	0x0F120000,    // 70003E0A
+	0x0F124778,    // 70003E0C
+	0x0F1246C0,    // 70003E0E
+	0x0F12C000,    // 70003E10
+	0x0F12E59F,    // 70003E12
+	0x0F12FF1C,    // 70003E14
+	0x0F12E12F,    // 70003E16
+	0x0F12F0B1,    // 70003E18
+	0x0F120000,    // 70003E1A
+	0x0F124778,    // 70003E1C
+	0x0F1246C0,    // 70003E1E
+	0x0F12C000,    // 70003E20
+	0x0F12E59F,    // 70003E22
+	0x0F12FF1C,    // 70003E24
+	0x0F12E12F,    // 70003E26
+	0x0F12EEDF,    // 70003E28
+	0x0F120000,    // 70003E2A
+	0x0F124778,    // 70003E2C
+	0x0F1246C0,    // 70003E2E
+	0x0F12C000,    // 70003E30
+	0x0F12E59F,    // 70003E32
+	0x0F12FF1C,    // 70003E34
+	0x0F12E12F,    // 70003E36
+	0x0F12AEF1,    // 70003E38
+	0x0F120000,    // 70003E3A
+	0x0F124778,    // 70003E3C
+	0x0F1246C0,    // 70003E3E
+	0x0F12C000,    // 70003E40
+	0x0F12E59F,    // 70003E42
+	0x0F12FF1C,    // 70003E44
+	0x0F12E12F,    // 70003E46
+	0x0F1202EB,    // 70003E48
+	0x0F120001,    // 70003E4A
+	0x0F124778,    // 70003E4C
+	0x0F1246C0,    // 70003E4E
+	0x0F12C000,    // 70003E50
+	0x0F12E59F,    // 70003E52
+	0x0F12FF1C,    // 70003E54
+	0x0F12E12F,    // 70003E56
+	0x0F12FD21,    // 70003E58
+	0x0F120000,    // 70003E5A
+	0x0F124778,    // 70003E5C
+	0x0F1246C0,    // 70003E5E
+	0x0F12C000,    // 70003E60
+	0x0F12E59F,    // 70003E62
+	0x0F12FF1C,    // 70003E64
+	0x0F12E12F,    // 70003E66
+	0x0F12FDAF,    // 70003E68
+	0x0F120000,    // 70003E6A
+	0x0F124778,    // 70003E6C
+	0x0F1246C0,    // 70003E6E
+	0x0F12C000,    // 70003E70
+	0x0F12E59F,    // 70003E72
+	0x0F12FF1C,    // 70003E74
+	0x0F12E12F,    // 70003E76
+	0x0F125027,    // 70003E78
+	0x0F120000,    // 70003E7A
+	0x0F124778,    // 70003E7C
+	0x0F1246C0,    // 70003E7E
+	0x0F12C000,    // 70003E80
+	0x0F12E59F,    // 70003E82
+	0x0F12FF1C,    // 70003E84
+	0x0F12E12F,    // 70003E86
+	0x0F1204C9,    // 70003E88
+	0x0F120000,    // 70003E8A
+	0x0F124778,    // 70003E8C
+	0x0F1246C0,    // 70003E8E
+	0x0F12C000,    // 70003E90
+	0x0F12E59F,    // 70003E92
+	0x0F12FF1C,    // 70003E94
+	0x0F12E12F,    // 70003E96
+	0x0F1239DF,    // 70003E98
+	0x0F120000,    // 70003E9A
+	0x0F124778,    // 70003E9C
+	0x0F1246C0,    // 70003E9E
+	0x0F12C000,    // 70003EA0
+	0x0F12E59F,    // 70003EA2
+	0x0F12FF1C,    // 70003EA4
+	0x0F12E12F,    // 70003EA6
+	0x0F126177,    // 70003EA8
+	0x0F120000,    // 70003EAA
+	0x0F124778,    // 70003EAC
+	0x0F1246C0,    // 70003EAE
+	0x0F12C000,    // 70003EB0
+	0x0F12E59F,    // 70003EB2
+	0x0F12FF1C,    // 70003EB4
+	0x0F12E12F,    // 70003EB6
+	0x0F12424F,    // 70003EB8
+	0x0F120000,    // 70003EBA
+	0x0F124778,    // 70003EBC
+	0x0F1246C0,    // 70003EBE
+	0x0F12C000,    // 70003EC0
+	0x0F12E59F,    // 70003EC2
+	0x0F12FF1C,    // 70003EC4
+	0x0F12E12F,    // 70003EC6
+	0x0F123F0D,    // 70003EC8
+	0x0F120000,    // 70003ECA
+	0x0F124778,    // 70003ECC
+	0x0F1246C0,    // 70003ECE
+	0x0F12C000,    // 70003ED0
+	0x0F12E59F,    // 70003ED2
+	0x0F12FF1C,    // 70003ED4
+	0x0F12E12F,    // 70003ED6
+	0x0F1202B9,    // 70003ED8
+	0x0F120001,    // 70003EDA
+	// End of Patch Data(Last : 70003EDAh)
+	// Total Size 2480 (09B0)
+	// Addr : 352C , Size : 2478(9AEh)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	//	TNP_GAS_ALPHA_OTP
+	//	TNP_FR_ACCURATE_DYNAMIC
+	//	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F12002E,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F120235,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12024A,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	/* Analog & APS settings
+
+
+	This register is for FACTORY ONLY. If you change it without prior notification.
+	YOU are RESPONSIBLE for the FAILURE that will happen in the future.*/
+
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120050,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0004                  //extend Forbidden area line
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8	//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32	//34BC //REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32	//34BC //REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8	//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32	//34BC //REG_TC_IPRM_MinOutRate4KHz_0//54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32	//34BC //REG_TC_IPRM_MaxOutRate4KHz_0//54Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4, //38A4 //36B0 //34BC //32C8 //REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+	0x0F1254F0, //4E20 //3A98 //7148 //4B32 //34BC //REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz
+	0x0F1254F8, //57E4 //61A8 //7148 //4B32 //34BC //REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+	//thumbnail set
+	0x002A0428,
+	0x0F120001,	//REG_TC_THUMB_Thumb_bActive	//Thumbnail Enable
+	0x0F120140,	//REG_TC_THUMB_Thumb_uWidth		//Thumbnail Width 320
+	0x0F1200F0,	//REG_TC_THUMB_Thumb_uHeight	//Thumbnail Height 240
+	0x0F120005,	//REG_TC_THUMB_Thumb_Format		//Thumbnail Output Format 5:YUV
+
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120400, //REG_0TC_PCFG_usWidth
+	0x0F120300, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+	0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+#if 1 /* [P4W] fix rotation to 180 */
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#endif
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120009,                   //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+#if 0 /* UYVY -> YUYV */
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+#else
+	0x0F120000,                   //REG_0TC_CCFG_PVIMask
+#endif
+	0x0F120050,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// Capture 1 640x480 system 52M PCLK 87M
+	//===================================================================
+	0x002A035A,
+	0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+	0x0F120400,                   //REG_1TC_CCFG_usWidth
+	0x0F120300,                   //REG_1TC_CCFG_usHeight
+	0x0F120009,                   //REG_1TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+	0x002A036A,
+#if 0 /* UYVY -> YUYV */
+	0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+#else
+	0x0F120000,                   //REG_1TC_CCFG_PVIMask
+#endif
+	0x0F120050,                   //REG_1TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+	0x002A0372,
+	0x0F120001,                   //REG_1TC_CCFG_uClockInd
+	0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+	0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_1TC_CCFG_sSaturation
+	0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+	0x0F123200, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123200, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123200, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123200, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123200, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123200, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F123F00,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120840, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+
+};
+#endif
+
+static const u32 s5k5ccgx_camcorder_set[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight	//Sensor Crop Height 1536
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs	//Sensor VOffset 0
+0x0F120800,	//REG_TC_GP_CapReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_CapReqInputHeight		//Sensor Crop Height 1368
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs		//Sensor VOffset 0
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+
+
+//Preview Size
+0x002A0400,
+0x0F120300,	//REG_0TC_PCFG_usWidth
+0x0F1201E0,	//REG_0TC_PCFG_usHeight
+
+0x002A029E,
+0x0F120400,		//REG_2TC_PCFG_usWidth
+0x0F120300,   //REG_2TC_PCFG_usHeight
+
+//Capture Size
+0x002A0330,
+0x0F120800,	//REG_0TC_CCFG_usWidth
+0x0F120600,	//REG_0TC_CCFG_usHeight
+
+0x002A0388,
+0x0F120800,   //REG_2TC_CCFG_usWidth
+0x0F120600,   //REG_2TC_CCFG_usHeight
+
+};
+
+static const u32 s5k5ccgx_update_preview_reg[] = {
+	//PREVIEW
+	0x002A0208,
+	0x0F120000, //REG_TC_GP_ActivePrevConfig
+	0x002A0210,
+	0x0F120000, //REG_TC_GP_ActiveCapConfig
+	0x002A020C,
+	0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+	0x002A01F4,
+	0x0F120001, //REG_TC_GP_NewConfigSync
+	0x002A020A,
+	0x0F120001, //REG_TC_GP_PrevConfigChanged
+	0x002A0212,
+	0x0F120001, //REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120000, //REG_TC_GP_EnableCapture
+	0x0F120001, //REG_TC_GP_EnableCaptureChanged
+	0xFFFF0064, //Delay 100ms
+};
+
+static const u32 s5k5ccgx_update_hd_preview_reg[] = {
+	/* PREVIEW */
+	0x002A0208,
+	0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+	0x002A0210,
+	0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+	0x002A020C,
+	0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+	0x002A01F4,
+	0x0F120001, /* REG_TC_GP_NewConfigSync */
+	0x002A020A,
+	0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+	0x002A0212,
+	0x0F120001, /* REG_TC_GP_CapConfigChanged */
+	0x002A01E8,
+	0x0F120000, /* REG_TC_GP_EnableCapture */
+	0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+
+	/* TNP_Regs_bUseAccurateFR */
+	0x00287000,
+	0x002A3FE4,
+	0x0F120001, /* on/off TNP_Regs_bAccuDynamicFR */
+	0x0F1234A2, /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+	0x0F1240FD, /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+
+	0xFFFF0064, /* Delay 100ms */
+};
+
+
+static const u32 s5k5ccgx_stream_stop_reg[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A01E4,
+	0x0F120000,
+	0x0F120001,
+};
+
+static const u32 s5k5ccgx_176_144_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F1200B0,
+	0x0F120090,
+	0x0F120005,
+	0x002A043C,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A023E, //Preview Size
+	0x0F1200B0, //REG_0TC_PCFG_usWidth
+	0x0F120090, //REG_0TC_PCFG_usHeight
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_320_240_Preview[] = {
+	0x002A023E,
+	0x0F120140,	//REG_0TC_PCFG_usWidth 320
+	0x0F1200F0,	//REG_0TC_PCFG_usHeight 240
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_352_288_Preview[] = {
+	0x002A023E,
+	0x0F120160,	//REG_0TC_PCFG_usWidth 280
+	0x0F120120,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_528_432_Preview[] = {
+	0xFCFCD000, // 0601 update preview setting
+	0x00287000,
+	0x002A01F6,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A0216,
+	0x0F120001,
+	0x0F120001,
+	0x002A0428,
+	0x0F120001,
+	0x0F1200B0,
+	0x0F120090,
+	0x0F120005,
+	0x002A043C,
+	0x0F120738,
+	0x0F120600,
+	0x0F120064,
+	0x0F120000,
+	0x002A023E, //Preview Size
+	0x0F120210, //REG_0TC_PCFG_usWidth
+	0x0F1201B0, //REG_0TC_PCFG_usHeight
+	0x002A0D1E,
+	0x0F122102,
+};
+
+static const u32 s5k5ccgx_640_480_Preview[] = {
+	0x002A023E,
+	0x0F120280,	//REG_0TC_PCFG_usWidth 280
+	0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_720_480_Preview[] = {
+	0x002A023E,
+	0x0F1202D0,	//REG_0TC_PCFG_usWidth 280
+	0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_800_600_Preview[] = {
+	0x002A023E,
+	0x0F120320,	//REG_0TC_PCFG_usWidth 280
+	0x0F120258,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_550_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120226,	//REG_0TC_PCFG_usHeight 226
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+#define S5K5CCGX_WIDE_PREVIEW_REG s5k5ccgx_1024_576_Preview
+static const u32 s5k5ccgx_1024_576_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120240,	//REG_0TC_PCFG_usHeight 240
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_616_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 400
+	0x0F120268,	//REG_0TC_PCFG_usHeight 268
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_768_Preview[] = {
+	0x002A023E,
+	0x0F120400,	//REG_0TC_PCFG_usWidth 280
+	0x0F120300,	//REG_0TC_PCFG_usHeight 1E0
+	0x0F120005,	//REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1280_1024_Preview[] = {
+
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000          //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A,     //p10
+	// Start of Patch data
+	0x00287000,
+	0x002A352C,
+	0x0F12B570,    // 7000352C
+	0x0F124A24,    // 7000352E
+	0x0F124924,    // 70003530
+	0x0F124825,    // 70003532
+	0x0F124B25,    // 70003534
+	0x0F122500,    // 70003536
+	0x0F12801D,    // 70003538
+	0x0F12C004,    // 7000353A
+	0x0F126001,    // 7000353C
+	0x0F124924,    // 7000353E
+	0x0F124824,    // 70003540
+	0x0F12F000,    // 70003542
+	0x0F12FBBD,    // 70003544
+	0x0F124924,    // 70003546
+	0x0F124824,    // 70003548
+	0x0F12F000,    // 7000354A
+	0x0F12FBB9,    // 7000354C
+	0x0F124824,    // 7000354E
+	0x0F124E24,    // 70003550
+	0x0F126430,    // 70003552
+	0x0F124924,    // 70003554
+	0x0F124825,    // 70003556
+	0x0F12F000,    // 70003558
+	0x0F12FBB2,    // 7000355A
+	0x0F124924,    // 7000355C
+	0x0F120030,    // 7000355E
+	0x0F123080,    // 70003560
+	0x0F126141,    // 70003562
+	0x0F124C23,    // 70003564
+	0x0F128365,    // 70003566
+	0x0F124923,    // 70003568
+	0x0F124824,    // 7000356A
+	0x0F12F000,    // 7000356C
+	0x0F12FBA8,    // 7000356E
+	0x0F124923,    // 70003570
+	0x0F124824,    // 70003572
+	0x0F12F000,    // 70003574
+	0x0F12FBA4,    // 70003576
+	0x0F124923,    // 70003578
+	0x0F124824,    // 7000357A
+	0x0F12F000,    // 7000357C
+	0x0F12FBA0,    // 7000357E
+	0x0F124923,    // 70003580
+	0x0F124824,    // 70003582
+	0x0F12F000,    // 70003584
+	0x0F12FB9C,    // 70003586
+	0x0F128125,    // 70003588
+	0x0F124923,    // 7000358A
+	0x0F124823,    // 7000358C
+	0x0F12F000,    // 7000358E
+	0x0F12FB97,    // 70003590
+	0x0F124923,    // 70003592
+	0x0F124823,    // 70003594
+	0x0F12F000,    // 70003596
+	0x0F12FB93,    // 70003598
+	0x0F1283A5,    // 7000359A
+	0x0F124922,    // 7000359C
+	0x0F124823,    // 7000359E
+	0x0F12F000,    // 700035A0
+	0x0F12FB8E,    // 700035A2
+	0x0F122101,    // 700035A4
+	0x0F120349,    // 700035A6
+	0x0F120020,    // 700035A8
+	0x0F123020,    // 700035AA
+	0x0F128041,    // 700035AC
+	0x0F122185,    // 700035AE
+	0x0F128081,    // 700035B0
+	0x0F12491F,    // 700035B2
+	0x0F1280C1,    // 700035B4
+	0x0F12481F,    // 700035B6
+	0x0F126730,    // 700035B8
+	0x0F12BC70,    // 700035BA
+	0x0F12BC08,    // 700035BC
+	0x0F124718,    // 700035BE
+	0x0F1200CA,    // 700035C0
+	0x0F125CC1,    // 700035C2
+	0x0F1203BD,    // 700035C4
+	0x0F120000,    // 700035C6
+	0x0F121C08,    // 700035C8
+	0x0F127000,    // 700035CA
+	0x0F123290,    // 700035CC
+	0x0F127000,    // 700035CE
+	0x0F123657,    // 700035D0
+	0x0F127000,    // 700035D2
+	0x0F12D9E7,    // 700035D4
+	0x0F120000,    // 700035D6
+	0x0F12383F,    // 700035D8
+	0x0F127000,    // 700035DA
+	0x0F12395D,    // 700035DC
+	0x0F120000,    // 700035DE
+	0x0F1238D1,    // 700035E0
+	0x0F127000,    // 700035E2
+	0x0F120000,    // 700035E4
+	0x0F127000,    // 700035E6
+	0x0F12399D,    // 700035E8
+	0x0F127000,    // 700035EA
+	0x0F12F903,    // 700035EC
+	0x0F120000,    // 700035EE
+	0x0F123AC1,    // 700035F0
+	0x0F127000,    // 700035F2
+	0x0F123FC8,    // 700035F4
+	0x0F127000,    // 700035F6
+	0x0F12368F,    // 700035F8
+	0x0F127000,    // 700035FA
+	0x0F12495F,    // 700035FC
+	0x0F120000,    // 700035FE
+	0x0F1236ED,    // 70003600
+	0x0F127000,    // 70003602
+	0x0F12E421,    // 70003604
+	0x0F120000,    // 70003606
+	0x0F1237AB,    // 70003608
+	0x0F127000,    // 7000360A
+	0x0F12216D,    // 7000360C
+	0x0F120000,    // 7000360E
+	0x0F12381F,    // 70003610
+	0x0F127000,    // 70003612
+	0x0F120179,    // 70003614
+	0x0F120001,    // 70003616
+	0x0F123BD5,    // 70003618
+	0x0F127000,    // 7000361A
+	0x0F1204C9,    // 7000361C
+	0x0F120000,    // 7000361E
+	0x0F123B25,    // 70003620
+	0x0F127000,    // 70003622
+	0x0F125027,    // 70003624
+	0x0F120000,    // 70003626
+	0x0F123BE1,    // 70003628
+	0x0F127000,    // 7000362A
+	0x0F1242B7,    // 7000362C
+	0x0F120000,    // 7000362E
+	0x0F1207FF,    // 70003630
+	0x0F120000,    // 70003632
+	0x0F123C5F,    // 70003634
+	0x0F127000,    // 70003636
+	0x0F12B570,    // 70003638
+	0x0F12000D,    // 7000363A
+	0x0F124CFC,    // 7000363C
+	0x0F128821,    // 7000363E
+	0x0F12F000,    // 70003640
+	0x0F12FB46,    // 70003642
+	0x0F128820,    // 70003644
+	0x0F124AFB,    // 70003646
+	0x0F120081,    // 70003648
+	0x0F125055,    // 7000364A
+	0x0F121C40,    // 7000364C
+	0x0F128020,    // 7000364E
+	0x0F12BC70,    // 70003650
+	0x0F12BC08,    // 70003652
+	0x0F124718,    // 70003654
+	0x0F126801,    // 70003656
+	0x0F120409,    // 70003658
+	0x0F120C09,    // 7000365A
+	0x0F126840,    // 7000365C
+	0x0F120400,    // 7000365E
+	0x0F120C00,    // 70003660
+	0x0F124AF5,    // 70003662
+	0x0F128992,    // 70003664
+	0x0F122A00,    // 70003666
+	0x0F12D00D,    // 70003668
+	0x0F122300,    // 7000366A
+	0x0F121A80,    // 7000366C
+	0x0F12D400,    // 7000366E
+	0x0F120003,    // 70003670
+	0x0F120418,    // 70003672
+	0x0F120C00,    // 70003674
+	0x0F124BF1,    // 70003676
+	0x0F121851,    // 70003678
+	0x0F12891B,    // 7000367A
+	0x0F12428B,    // 7000367C
+	0x0F12D300,    // 7000367E
+	0x0F12000B,    // 70003680
+	0x0F120419,    // 70003682
+	0x0F120C09,    // 70003684
+	0x0F124AEE,    // 70003686
+	0x0F128151,    // 70003688
+	0x0F128190,    // 7000368A
+	0x0F124770,    // 7000368C
+	0x0F12B510,    // 7000368E
+	0x0F124CEC,    // 70003690
+	0x0F1248ED,    // 70003692
+	0x0F1278A1,    // 70003694
+	0x0F122900,    // 70003696
+	0x0F12D101,    // 70003698
+	0x0F1287C1,    // 7000369A
+	0x0F12E004,    // 7000369C
+	0x0F127AE1,    // 7000369E
+	0x0F122900,    // 700036A0
+	0x0F12D001,    // 700036A2
+	0x0F122101,    // 700036A4
+	0x0F1287C1,    // 700036A6
+	0x0F12F000,    // 700036A8
+	0x0F12FB1A,    // 700036AA
+	0x0F1249E7,    // 700036AC
+	0x0F128B08,    // 700036AE
+	0x0F1206C2,    // 700036B0
+	0x0F12D50A,    // 700036B2
+	0x0F127AA2,    // 700036B4
+	0x0F120652,    // 700036B6
+	0x0F12D507,    // 700036B8
+	0x0F122210,    // 700036BA
+	0x0F124390,    // 700036BC
+	0x0F128308,    // 700036BE
+	0x0F1248E3,    // 700036C0
+	0x0F127AE1,    // 700036C2
+	0x0F126B00,    // 700036C4
+	0x0F12F000,    // 700036C6
+	0x0F12FB13,    // 700036C8
+	0x0F1248DB,    // 700036CA
+	0x0F1289C0,    // 700036CC
+	0x0F122801,    // 700036CE
+	0x0F12D109,    // 700036D0
+	0x0F1278A0,    // 700036D2
+	0x0F122800,    // 700036D4
+	0x0F12D006,    // 700036D6
+	0x0F127AE0,    // 700036D8
+	0x0F122800,    // 700036DA
+	0x0F12D003,    // 700036DC
+	0x0F127AA0,    // 700036DE
+	0x0F122140,    // 700036E0
+	0x0F124308,    // 700036E2
+	0x0F1272A0,    // 700036E4
+	0x0F12BC10,    // 700036E6
+	0x0F12BC08,    // 700036E8
+	0x0F124718,    // 700036EA
+	0x0F12B570,    // 700036EC
+	0x0F124DD7,    // 700036EE
+	0x0F124CD7,    // 700036F0
+	0x0F128B28,    // 700036F2
+	0x0F120701,    // 700036F4
+	0x0F12D507,    // 700036F6
+	0x0F122108,    // 700036F8
+	0x0F124388,    // 700036FA
+	0x0F128328,    // 700036FC
+	0x0F1249D5,    // 700036FE
+	0x0F126B20,    // 70003700
+	0x0F126B89,    // 70003702
+	0x0F12F000,    // 70003704
+	0x0F12FAFC,    // 70003706
+	0x0F128B28,    // 70003708
+	0x0F1206C1,    // 7000370A
+	0x0F12D5A0,    // 7000370C
+	0x0F1249CD,    // 7000370E
+	0x0F127A8A,    // 70003710
+	0x0F120652,    // 70003712
+	0x0F12D49C,    // 70003714
+	0x0F122210,    // 70003716
+	0x0F124390,    // 70003718
+	0x0F128328,    // 7000371A
+	0x0F127AC9,    // 7000371C
+	0x0F126B20,    // 7000371E
+	0x0F12F000,    // 70003720
+	0x0F12FAE6,    // 70003722
+	0x0F12E794,    // 70003724
+	0x0F12B5F8,    // 70003726
+	0x0F1249CB,    // 70003728
+	0x0F128F08,    // 7000372A
+	0x0F12000C,    // 7000372C
+	0x0F123480,    // 7000372E
+	0x0F122800,    // 70003730
+	0x0F12D000,    // 70003732
+	0x0F128360,    // 70003734
+	0x0F122000,    // 70003736
+	0x0F128708,    // 70003738
+	0x0F124DC8,    // 7000373A
+	0x0F1226FF,    // 7000373C
+	0x0F128828,    // 7000373E
+	0x0F121C76,    // 70003740
+	0x0F122702,    // 70003742
+	0x0F122803,    // 70003744
+	0x0F12D112,    // 70003746
+	0x0F128868,    // 70003748
+	0x0F122800,    // 7000374A
+	0x0F12D10F,    // 7000374C
+	0x0F1288E8,    // 7000374E
+	0x0F122800,    // 70003750
+	0x0F12D10C,    // 70003752
+	0x0F12F000,    // 70003754
+	0x0F12FADC,    // 70003756
+	0x0F122800,    // 70003758
+	0x0F12D008,    // 7000375A
+	0x0F128B60,    // 7000375C
+	0x0F122800,    // 7000375E
+	0x0F12D001,    // 70003760
+	0x0F1280EE,    // 70003762
+	0x0F1280AF,    // 70003764
+	0x0F122001,    // 70003766
+	0x0F127268,    // 70003768
+	0x0F12F000,    // 7000376A
+	0x0F12FAD9,    // 7000376C
+	0x0F128828,    // 7000376E
+	0x0F122802,    // 70003770
+	0x0F12D10E,    // 70003772
+	0x0F128868,    // 70003774
+	0x0F122800,    // 70003776
+	0x0F12D10B,    // 70003778
+	0x0F1288E8,    // 7000377A
+	0x0F122800,    // 7000377C
+	0x0F12D108,    // 7000377E
+	0x0F128B60,    // 70003780
+	0x0F122800,    // 70003782
+	0x0F12D001,    // 70003784
+	0x0F1280EE,    // 70003786
+	0x0F1280AF,    // 70003788
+	0x0F122001,    // 7000378A
+	0x0F127268,    // 7000378C
+	0x0F12F000,    // 7000378E
+	0x0F12FAC7,    // 70003790
+	0x0F1288E8,    // 70003792
+	0x0F122800,    // 70003794
+	0x0F12D006,    // 70003796
+	0x0F121FC1,    // 70003798
+	0x0F1239FD,    // 7000379A
+	0x0F12D003,    // 7000379C
+	0x0F122001,    // 7000379E
+	0x0F12BCF8,    // 700037A0
+	0x0F12BC08,    // 700037A2
+	0x0F124718,    // 700037A4
+	0x0F122000,    // 700037A6
+	0x0F12E7FA,    // 700037A8
+	0x0F12B570,    // 700037AA
+	0x0F124CAC,    // 700037AC
+	0x0F128860,    // 700037AE
+	0x0F122800,    // 700037B0
+	0x0F12D00C,    // 700037B2
+	0x0F128820,    // 700037B4
+	0x0F124DA3,    // 700037B6
+	0x0F122800,    // 700037B8
+	0x0F12D009,    // 700037BA
+	0x0F120029,    // 700037BC
+	0x0F1231A0,    // 700037BE
+	0x0F127AC9,    // 700037C0
+	0x0F122900,    // 700037C2
+	0x0F12D004,    // 700037C4
+	0x0F127AA8,    // 700037C6
+	0x0F122180,    // 700037C8
+	0x0F124308,    // 700037CA
+	0x0F1272A8,    // 700037CC
+	0x0F12E73F,    // 700037CE
+	0x0F122800,    // 700037D0
+	0x0F12D003,    // 700037D2
+	0x0F12F7FF,    // 700037D4
+	0x0F12FFA7,    // 700037D6
+	0x0F122800,    // 700037D8
+	0x0F12D1F8,    // 700037DA
+	0x0F122000,    // 700037DC
+	0x0F128060,    // 700037DE
+	0x0F128820,    // 700037E0
+	0x0F122800,    // 700037E2
+	0x0F12D003,    // 700037E4
+	0x0F122008,    // 700037E6
+	0x0F12F000,    // 700037E8
+	0x0F12FAA2,    // 700037EA
+	0x0F12E00B,    // 700037EC
+	0x0F12489C,    // 700037EE
+	0x0F123020,    // 700037F0
+	0x0F128880,    // 700037F2
+	0x0F122800,    // 700037F4
+	0x0F12D103,    // 700037F6
+	0x0F127AA8,    // 700037F8
+	0x0F122101,    // 700037FA
+	0x0F124308,    // 700037FC
+	0x0F1272A8,    // 700037FE
+	0x0F122010,    // 70003800
+	0x0F12F000,    // 70003802
+	0x0F12FA95,    // 70003804
+	0x0F128820,    // 70003806
+	0x0F122800,    // 70003808
+	0x0F12D1E0,    // 7000380A
+	0x0F12488A,    // 7000380C
+	0x0F1289C0,    // 7000380E
+	0x0F122801,    // 70003810
+	0x0F12D1DC,    // 70003812
+	0x0F127AA8,    // 70003814
+	0x0F1221BF,    // 70003816
+	0x0F124008,    // 70003818
+	0x0F1272A8,    // 7000381A
+	0x0F12E718,    // 7000381C
+	0x0F126800,    // 7000381E
+	0x0F124990,    // 70003820
+	0x0F128188,    // 70003822
+	0x0F124890,    // 70003824
+	0x0F122201,    // 70003826
+	0x0F128981,    // 70003828
+	0x0F124890,    // 7000382A
+	0x0F120252,    // 7000382C
+	0x0F124291,    // 7000382E
+	0x0F12D902,    // 70003830
+	0x0F122102,    // 70003832
+	0x0F128181,    // 70003834
+	0x0F124770,    // 70003836
+	0x0F122101,    // 70003838
+	0x0F128181,    // 7000383A
+	0x0F124770,    // 7000383C
+	0x0F12B5F1,    // 7000383E
+	0x0F124E80,    // 70003840
+	0x0F128834,    // 70003842
+	0x0F122C00,    // 70003844
+	0x0F12D03F,    // 70003846
+	0x0F122001,    // 70003848
+	0x0F122C08,    // 7000384A
+	0x0F12D000,    // 7000384C
+	0x0F122000,    // 7000384E
+	0x0F1270B0,    // 70003850
+	0x0F124D7F,    // 70003852
+	0x0F122800,    // 70003854
+	0x0F12D009,    // 70003856
+	0x0F12F000,    // 70003858
+	0x0F12FA72,    // 7000385A
+	0x0F120028,    // 7000385C
+	0x0F1238F0,    // 7000385E
+	0x0F126328,    // 70003860
+	0x0F127AB0,    // 70003862
+	0x0F12217E,    // 70003864
+	0x0F124008,    // 70003866
+	0x0F1272B0,    // 70003868
+	0x0F12E00F,    // 7000386A
+	0x0F124F7A,    // 7000386C
+	0x0F123780,    // 7000386E
+	0x0F128B78,    // 70003870
+	0x0F122800,    // 70003872
+	0x0F12D005,    // 70003874
+	0x0F12F000,    // 70003876
+	0x0F12FA6B,    // 70003878
+	0x0F122000,    // 7000387A
+	0x0F128378,    // 7000387C
+	0x0F124976,    // 7000387E
+	0x0F128708,    // 70003880
+	0x0F122000,    // 70003882
+	0x0F12F000,    // 70003884
+	0x0F12FA6C,    // 70003886
+	0x0F124879,    // 70003888
+	0x0F126328,    // 7000388A
+	0x0F1278B1,    // 7000388C
+	0x0F122700,    // 7000388E
+	0x0F120038,    // 70003890
+	0x0F122900,    // 70003892
+	0x0F12D008,    // 70003894
+	0x0F124972,    // 70003896
+	0x0F123920,    // 70003898
+	0x0F128ACA,    // 7000389A
+	0x0F122A00,    // 7000389C
+	0x0F12D003,    // 7000389E
+	0x0F128B09,    // 700038A0
+	0x0F122900,    // 700038A2
+	0x0F12D000,    // 700038A4
+	0x0F122001,    // 700038A6
+	0x0F127170,    // 700038A8
+	0x0F122C02,    // 700038AA
+	0x0F12D102,    // 700038AC
+	0x0F124868,    // 700038AE
+	0x0F123860,    // 700038B0
+	0x0F126328,    // 700038B2
+	0x0F122201,    // 700038B4
+	0x0F122C02,    // 700038B6
+	0x0F12D000,    // 700038B8
+	0x0F122200,    // 700038BA
+	0x0F124861,    // 700038BC
+	0x0F122110,    // 700038BE
+	0x0F12300A,    // 700038C0
+	0x0F12F000,    // 700038C2
+	0x0F12FA55,    // 700038C4
+	0x0F128037,    // 700038C6
+	0x0F129900,    // 700038C8
+	0x0F120020,    // 700038CA
+	0x0F12600C,    // 700038CC
+	0x0F12E767,    // 700038CE
+	0x0F12B538,    // 700038D0
+	0x0F124865,    // 700038D2
+	0x0F124669,    // 700038D4
+	0x0F123848,    // 700038D6
+	0x0F12F000,    // 700038D8
+	0x0F12FA52,    // 700038DA
+	0x0F124A5E,    // 700038DC
+	0x0F124862,    // 700038DE
+	0x0F128F51,    // 700038E0
+	0x0F122400,    // 700038E2
+	0x0F123020,    // 700038E4
+	0x0F122900,    // 700038E6
+	0x0F12D00A,    // 700038E8
+	0x0F128754,    // 700038EA
+	0x0F126941,    // 700038EC
+	0x0F126451,    // 700038EE
+	0x0F126491,    // 700038F0
+	0x0F12466B,    // 700038F2
+	0x0F128819,    // 700038F4
+	0x0F1287D1,    // 700038F6
+	0x0F12885B,    // 700038F8
+	0x0F120011,    // 700038FA
+	0x0F123140,    // 700038FC
+	0x0F12800B,    // 700038FE
+	0x0F128F91,    // 70003900
+	0x0F122900,    // 70003902
+	0x0F12D002,    // 70003904
+	0x0F128794,    // 70003906
+	0x0F126940,    // 70003908
+	0x0F126490,    // 7000390A
+	0x0F12F000,    // 7000390C
+	0x0F12FA40,    // 7000390E
+	0x0F12BC38,    // 70003910
+	0x0F12BC08,    // 70003912
+	0x0F124718,    // 70003914
+	0x0F12B5F8,    // 70003916
+	0x0F124C56,    // 70003918
+	0x0F1289E0,    // 7000391A
+	0x0F12F000,    // 7000391C
+	0x0F12FA40,    // 7000391E
+	0x0F120006,    // 70003920
+	0x0F128A20,    // 70003922
+	0x0F12F000,    // 70003924
+	0x0F12FA44,    // 70003926
+	0x0F120007,    // 70003928
+	0x0F12484F,    // 7000392A
+	0x0F124D4A,    // 7000392C
+	0x0F123020,    // 7000392E
+	0x0F126CA9,    // 70003930
+	0x0F126940,    // 70003932
+	0x0F121809,    // 70003934
+	0x0F120200,    // 70003936
+	0x0F12F000,    // 70003938
+	0x0F12FA42,    // 7000393A
+	0x0F120400,    // 7000393C
+	0x0F120C00,    // 7000393E
+	0x0F12002A,    // 70003940
+	0x0F12326E,    // 70003942
+	0x0F120011,    // 70003944
+	0x0F12390A,    // 70003946
+	0x0F122305,    // 70003948
+	0x0F12F000,    // 7000394A
+	0x0F12FA3F,    // 7000394C
+	0x0F124C43,    // 7000394E
+	0x0F1261A0,    // 70003950
+	0x0F128FEB,    // 70003952
+	0x0F120002,    // 70003954
+	0x0F120031,    // 70003956
+	0x0F120018,    // 70003958
+	0x0F12F000,    // 7000395A
+	0x0F12FA3F,    // 7000395C
+	0x0F12466B,    // 7000395E
+	0x0F120005,    // 70003960
+	0x0F128018,    // 70003962
+	0x0F12483C,    // 70003964
+	0x0F1269A2,    // 70003966
+	0x0F123040,    // 70003968
+	0x0F128800,    // 7000396A
+	0x0F120039,    // 7000396C
+	0x0F12F000,    // 7000396E
+	0x0F12FA35,    // 70003970
+	0x0F12466B,    // 70003972
+	0x0F120006,    // 70003974
+	0x0F128058,    // 70003976
+	0x0F120021,    // 70003978
+	0x0F129800,    // 7000397A
+	0x0F12311C,    // 7000397C
+	0x0F12F000,    // 7000397E
+	0x0F12FA35,    // 70003980
+	0x0F124935,    // 70003982
+	0x0F123180,    // 70003984
+	0x0F12808D,    // 70003986
+	0x0F1280CE,    // 70003988
+	0x0F128BA1,    // 7000398A
+	0x0F124836,    // 7000398C
+	0x0F123820,    // 7000398E
+	0x0F128001,    // 70003990
+	0x0F128BE1,    // 70003992
+	0x0F128041,    // 70003994
+	0x0F128C21,    // 70003996
+	0x0F128081,    // 70003998
+	0x0F12E701,    // 7000399A
+	0x0F12B5F8,    // 7000399C
+	0x0F124E2E,    // 7000399E
+	0x0F126C70,    // 700039A0
+	0x0F126CB1,    // 700039A2
+	0x0F120200,    // 700039A4
+	0x0F12F000,    // 700039A6
+	0x0F12FA0B,    // 700039A8
+	0x0F120400,    // 700039AA
+	0x0F120C00,    // 700039AC
+	0x0F122401,    // 700039AE
+	0x0F120364,    // 700039B0
+	0x0F1242A0,    // 700039B2
+	0x0F12D200,    // 700039B4
+	0x0F120004,    // 700039B6
+	0x0F124A27,    // 700039B8
+	0x0F120020,    // 700039BA
+	0x0F12327E,    // 700039BC
+	0x0F121F91,    // 700039BE
+	0x0F122303,    // 700039C0
+	0x0F12F000,    // 700039C2
+	0x0F12FA03,    // 700039C4
+	0x0F120405,    // 700039C6
+	0x0F120C2D,    // 700039C8
+	0x0F124A23,    // 700039CA
+	0x0F120020,    // 700039CC
+	0x0F12325A,    // 700039CE
+	0x0F120011,    // 700039D0
+	0x0F12390A,    // 700039D2
+	0x0F122305,    // 700039D4
+	0x0F12F000,    // 700039D6
+	0x0F12F9F9,    // 700039D8
+	0x0F12491F,    // 700039DA
+	0x0F1264C8,    // 700039DC
+	0x0F12491F,    // 700039DE
+	0x0F124E21,    // 700039E0
+	0x0F1288C8,    // 700039E2
+	0x0F122701,    // 700039E4
+	0x0F122800,    // 700039E6
+	0x0F12D009,    // 700039E8
+	0x0F124C23,    // 700039EA
+	0x0F1238FF,    // 700039EC
+	0x0F121E40,    // 700039EE
+	0x0F12D00A,    // 700039F0
+	0x0F122804,    // 700039F2
+	0x0F12D042,    // 700039F4
+	0x0F122806,    // 700039F6
+	0x0F12D101,    // 700039F8
+	0x0F122000,    // 700039FA
+	0x0F1280C8,    // 700039FC
+	0x0F1282B7,    // 700039FE
+	0x0F122001,    // 70003A00
+	0x0F12F000,    // 70003A02
+	0x0F12F9FB,    // 70003A04
+	0x0F12E6CB,    // 70003A06
+	0x0F12000D,    // 70003A08
+	0x0F12724F,    // 70003A0A
+	0x0F122001,    // 70003A0C
+	0x0F12F000,    // 70003A0E
+	0x0F12F9FD,    // 70003A10
+	0x0F12F000,    // 70003A12
+	0x0F12FA03,    // 70003A14
+	0x0F124910,    // 70003A16
+	0x0F123148,    // 70003A18
+	0x0F12C903,    // 70003A1A
+	0x0F124348,    // 70003A1C
+	0x0F120A00,    // 70003A1E
+	0x0F126160,    // 70003A20
+	0x0F1220FF,    // 70003A22
+	0x0F121D40,    // 70003A24
+	0x0F1280E8,    // 70003A26
+	0x0F12480C,    // 70003A28
+	0x0F123040,    // 70003A2A
+	0x0F127707,    // 70003A2C
+	0x0F12E7E6,    // 70003A2E
+	0x0F123290,    // 70003A30
+	0x0F127000,    // 70003A32
+	0x0F123294,    // 70003A34
+	0x0F127000,    // 70003A36
+	0x0F1204A8,    // 70003A38
+	0x0F127000,    // 70003A3A
+	0x0F1215DC,    // 70003A3C
+	0x0F127000,    // 70003A3E
+	0x0F125000,    // 70003A40
+	0x0F12D000,    // 70003A42
+	0x0F121E84,    // 70003A44
+	0x0F127000,    // 70003A46
+	0x0F121BE4,    // 70003A48
+	0x0F127000,    // 70003A4A
+	0x0F122EA8,    // 70003A4C
+	0x0F127000,    // 70003A4E
+	0x0F1221A4,    // 70003A50
+	0x0F127000,    // 70003A52
+	0x0F120100,    // 70003A54
+	0x0F127000,    // 70003A56
+	0x0F123F48,    // 70003A58
+	0x0F127000,    // 70003A5A
+	0x0F1231A0,    // 70003A5C
+	0x0F127000,    // 70003A5E
+	0x0F1201E8,    // 70003A60
+	0x0F127000,    // 70003A62
+	0x0F12F2A0,    // 70003A64
+	0x0F12D000,    // 70003A66
+	0x0F122A44,    // 70003A68
+	0x0F127000,    // 70003A6A
+	0x0F12F400,    // 70003A6C
+	0x0F12D000,    // 70003A6E
+	0x0F122024,    // 70003A70
+	0x0F127000,    // 70003A72
+	0x0F121650,    // 70003A74
+	0x0F127000,    // 70003A76
+	0x0F122A64,    // 70003A78
+	0x0F127000,    // 70003A7A
+	0x0F124982,    // 70003A7C
+	0x0F12724F,    // 70003A7E
+	0x0F1220FF,    // 70003A80
+	0x0F121DC0,    // 70003A82
+	0x0F1280C8,    // 70003A84
+	0x0F12F000,    // 70003A86
+	0x0F12F9D1,    // 70003A88
+	0x0F124980,    // 70003A8A
+	0x0F126ACA,    // 70003A8C
+	0x0F12604A,    // 70003A8E
+	0x0F122800,    // 70003A90
+	0x0F12D006,    // 70003A92
+	0x0F12436A,    // 70003A94
+	0x0F120001,    // 70003A96
+	0x0F120010,    // 70003A98
+	0x0F12F000,    // 70003A9A
+	0x0F12F991,    // 70003A9C
+	0x0F126160,    // 70003A9E
+	0x0F12E001,    // 70003AA0
+	0x0F12436A,    // 70003AA2
+	0x0F126162,    // 70003AA4
+	0x0F128BF0,    // 70003AA6
+	0x0F122800,    // 70003AA8
+	0x0F12D001,    // 70003AAA
+	0x0F12F7FF,    // 70003AAC
+	0x0F12FF33,    // 70003AAE
+	0x0F122000,    // 70003AB0
+	0x0F12F000,    // 70003AB2
+	0x0F12F9AB,    // 70003AB4
+	0x0F124974,    // 70003AB6
+	0x0F1220FF,    // 70003AB8
+	0x0F121DC0,    // 70003ABA
+	0x0F1280C8,    // 70003ABC
+	0x0F12E79E,    // 70003ABE
+	0x0F12B510,    // 70003AC0
+	0x0F12F000,    // 70003AC2
+	0x0F12F9BB,    // 70003AC4
+	0x0F124870,    // 70003AC6
+	0x0F1288C0,    // 70003AC8
+	0x0F121FC1,    // 70003ACA
+	0x0F1239FD,    // 70003ACC
+	0x0F12D103,    // 70003ACE
+	0x0F12496F,    // 70003AD0
+	0x0F1220FF,    // 70003AD2
+	0x0F121C40,    // 70003AD4
+	0x0F128048,    // 70003AD6
+	0x0F12E605,    // 70003AD8
+	0x0F12B5F8,    // 70003ADA
+	0x0F122400,    // 70003ADC
+	0x0F124D6D,    // 70003ADE
+	0x0F12486D,    // 70003AE0
+	0x0F12210E,    // 70003AE2
+	0x0F128041,    // 70003AE4
+	0x0F122101,    // 70003AE6
+	0x0F128001,    // 70003AE8
+	0x0F12F000,    // 70003AEA
+	0x0F12F9AF,    // 70003AEC
+	0x0F12486B,    // 70003AEE
+	0x0F128840,    // 70003AF0
+	0x0F12F000,    // 70003AF2
+	0x0F12F9B3,    // 70003AF4
+	0x0F124E6A,    // 70003AF6
+	0x0F12270D,    // 70003AF8
+	0x0F12073F,    // 70003AFA
+	0x0F1219E8,    // 70003AFC
+	0x0F128803,    // 70003AFE
+	0x0F1200E2,    // 70003B00
+	0x0F121991,    // 70003B02
+	0x0F12804B,    // 70003B04
+	0x0F128843,    // 70003B06
+	0x0F1252B3,    // 70003B08
+	0x0F128882,    // 70003B0A
+	0x0F1280CA,    // 70003B0C
+	0x0F1288C0,    // 70003B0E
+	0x0F128088,    // 70003B10
+	0x0F123508,    // 70003B12
+	0x0F12042D,    // 70003B14
+	0x0F120C2D,    // 70003B16
+	0x0F121C64,    // 70003B18
+	0x0F120424,    // 70003B1A
+	0x0F120C24,    // 70003B1C
+	0x0F122C07,    // 70003B1E
+	0x0F12D3EC,    // 70003B20
+	0x0F12E63D,    // 70003B22
+	0x0F12B5F0,    // 70003B24
+	0x0F12B085,    // 70003B26
+	0x0F126801,    // 70003B28
+	0x0F129103,    // 70003B2A
+	0x0F126881,    // 70003B2C
+	0x0F12040A,    // 70003B2E
+	0x0F120C12,    // 70003B30
+	0x0F12495C,    // 70003B32
+	0x0F128B89,    // 70003B34
+	0x0F122900,    // 70003B36
+	0x0F12D001,    // 70003B38
+	0x0F120011,    // 70003B3A
+	0x0F12E000,    // 70003B3C
+	0x0F122100,    // 70003B3E
+	0x0F129102,    // 70003B40
+	0x0F126840,    // 70003B42
+	0x0F120401,    // 70003B44
+	0x0F129803,    // 70003B46
+	0x0F120C09,    // 70003B48
+	0x0F12F000,    // 70003B4A
+	0x0F12F98F,    // 70003B4C
+	0x0F124854,    // 70003B4E
+	0x0F123080,    // 70003B50
+	0x0F128900,    // 70003B52
+	0x0F122800,    // 70003B54
+	0x0F12D039,    // 70003B56
+	0x0F122100,    // 70003B58
+	0x0F124854,    // 70003B5A
+	0x0F124D52,    // 70003B5C
+	0x0F124684,    // 70003B5E
+	0x0F124B53,    // 70003B60
+	0x0F124C4F,    // 70003B62
+	0x0F1288DA,    // 70003B64
+	0x0F120048,    // 70003B66
+	0x0F1200D7,    // 70003B68
+	0x0F12193E,    // 70003B6A
+	0x0F12197F,    // 70003B6C
+	0x0F12183F,    // 70003B6E
+	0x0F125A36,    // 70003B70
+	0x0F128AFF,    // 70003B72
+	0x0F12437E,    // 70003B74
+	0x0F1200B6,    // 70003B76
+	0x0F120C37,    // 70003B78
+	0x0F121906,    // 70003B7A
+	0x0F123680,    // 70003B7C
+	0x0F128177,    // 70003B7E
+	0x0F121C52,    // 70003B80
+	0x0F1200D2,    // 70003B82
+	0x0F121914,    // 70003B84
+	0x0F121952,    // 70003B86
+	0x0F121812,    // 70003B88
+	0x0F125A24,    // 70003B8A
+	0x0F128AD2,    // 70003B8C
+	0x0F124354,    // 70003B8E
+	0x0F1200A2,    // 70003B90
+	0x0F120C12,    // 70003B92
+	0x0F128272,    // 70003B94
+	0x0F12891C,    // 70003B96
+	0x0F12895B,    // 70003B98
+	0x0F124367,    // 70003B9A
+	0x0F12435A,    // 70003B9C
+	0x0F121943,    // 70003B9E
+	0x0F123340,    // 70003BA0
+	0x0F1289DB,    // 70003BA2
+	0x0F129C02,    // 70003BA4
+	0x0F1218BA,    // 70003BA6
+	0x0F124363,    // 70003BA8
+	0x0F1218D2,    // 70003BAA
+	0x0F120212,    // 70003BAC
+	0x0F120C12,    // 70003BAE
+	0x0F12466B,    // 70003BB0
+	0x0F12521A,    // 70003BB2
+	0x0F124663,    // 70003BB4
+	0x0F127DDB,    // 70003BB6
+	0x0F12435A,    // 70003BB8
+	0x0F129B03,    // 70003BBA
+	0x0F120252,    // 70003BBC
+	0x0F120C12,    // 70003BBE
+	0x0F12521A,    // 70003BC0
+	0x0F121C49,    // 70003BC2
+	0x0F120409,    // 70003BC4
+	0x0F120C09,    // 70003BC6
+	0x0F122904,    // 70003BC8
+	0x0F12D3C9,    // 70003BCA
+	0x0F12B005,    // 70003BCC
+	0x0F12BCF0,    // 70003BCE
+	0x0F12BC08,    // 70003BD0
+	0x0F124718,    // 70003BD2
+	0x0F12B510,    // 70003BD4
+	0x0F12F7FF,    // 70003BD6
+	0x0F12FF80,    // 70003BD8
+	0x0F12F000,    // 70003BDA
+	0x0F12F94F,    // 70003BDC
+	0x0F12E582,    // 70003BDE
+	0x0F12B570,    // 70003BE0
+	0x0F126804,    // 70003BE2
+	0x0F12F000,    // 70003BE4
+	0x0F12F952,    // 70003BE6
+	0x0F124D32,    // 70003BE8
+	0x0F128C29,    // 70003BEA
+	0x0F121A40,    // 70003BEC
+	0x0F1242A0,    // 70003BEE
+	0x0F12D901,    // 70003BF0
+	0x0F120020,    // 70003BF2
+	0x0F12E003,    // 70003BF4
+	0x0F12F000,    // 70003BF6
+	0x0F12F949,    // 70003BF8
+	0x0F128C29,    // 70003BFA
+	0x0F121A40,    // 70003BFC
+	0x0F126268,    // 70003BFE
+	0x0F12F000,    // 70003C00
+	0x0F12F94C,    // 70003C02
+	0x0F1262A8,    // 70003C04
+	0x0F12F000,    // 70003C06
+	0x0F12F951,    // 70003C08
+	0x0F126328,    // 70003C0A
+	0x0F128869,    // 70003C0C
+	0x0F122900,    // 70003C0E
+	0x0F12D000,    // 70003C10
+	0x0F1262A8,    // 70003C12
+	0x0F124828,    // 70003C14
+	0x0F126B00,    // 70003C16
+	0x0F128C00,    // 70003C18
+	0x0F122800,    // 70003C1A
+	0x0F12D11B,    // 70003C1C
+	0x0F126AA8,    // 70003C1E
+	0x0F12F000,    // 70003C20
+	0x0F12F94C,    // 70003C22
+	0x0F1261E8,    // 70003C24
+	0x0F124A1E,    // 70003C26
+	0x0F123280,    // 70003C28
+	0x0F128B91,    // 70003C2A
+	0x0F122900,    // 70003C2C
+	0x0F12D00B,    // 70003C2E
+	0x0F120011,    // 70003C30
+	0x0F123120,    // 70003C32
+	0x0F128809,    // 70003C34
+	0x0F124288,    // 70003C36
+	0x0F12D907,    // 70003C38
+	0x0F1261E9,    // 70003C3A
+	0x0F128C28,    // 70003C3C
+	0x0F121A08,    // 70003C3E
+	0x0F1262A8,    // 70003C40
+	0x0F12F000,    // 70003C42
+	0x0F12F92B,    // 70003C44
+	0x0F1262A8,    // 70003C46
+	0x0F12E502,    // 70003C48
+	0x0F128BD1,    // 70003C4A
+	0x0F124288,    // 70003C4C
+	0x0F12D800,    // 70003C4E
+	0x0F120008,    // 70003C50
+	0x0F1261E8,    // 70003C52
+	0x0F12E4FC,    // 70003C54
+	0x0F12F000,    // 70003C56
+	0x0F12F919,    // 70003C58
+	0x0F1261E8,    // 70003C5A
+	0x0F12E4F8,    // 70003C5C
+	0x0F12B510,    // 70003C5E
+	0x0F12F000,    // 70003C60
+	0x0F12F934,    // 70003C62
+	0x0F12480E,    // 70003C64
+	0x0F1230A0,    // 70003C66
+	0x0F128841,    // 70003C68
+	0x0F122900,    // 70003C6A
+	0x0F12D007,    // 70003C6C
+	0x0F124A07,    // 70003C6E
+	0x0F123280,    // 70003C70
+	0x0F126953,    // 70003C72
+	0x0F124A11,    // 70003C74
+	0x0F12428B,    // 70003C76
+	0x0F12D202,    // 70003C78
+	0x0F128880,    // 70003C7A
+	0x0F1281D0,    // 70003C7C
+	0x0F12E532,    // 70003C7E
+	0x0F1288C0,    // 70003C80
+	0x0F1281D0,    // 70003C82
+	0x0F12E52F,    // 70003C84
+	0x0F120000,    // 70003C86
+	0x0F1231A0,    // 70003C88
+	0x0F127000,    // 70003C8A
+	0x0F1229E4,    // 70003C8C
+	0x0F127000,    // 70003C8E
+	0x0F12C100,    // 70003C90
+	0x0F12D000,    // 70003C92
+	0x0F12A006,    // 70003C94
+	0x0F120000,    // 70003C96
+	0x0F12A000,    // 70003C98
+	0x0F12D000,    // 70003C9A
+	0x0F12064C,    // 70003C9C
+	0x0F127000,    // 70003C9E
+	0x0F123F48,    // 70003CA0
+	0x0F127000,    // 70003CA2
+	0x0F1207C4,    // 70003CA4
+	0x0F127000,    // 70003CA6
+	0x0F1207E8,    // 70003CA8
+	0x0F127000,    // 70003CAA
+	0x0F122B24,    // 70003CAC
+	0x0F127000,    // 70003CAE
+	0x0F121FA0,    // 70003CB0
+	0x0F127000,    // 70003CB2
+	0x0F121E3C,    // 70003CB4
+	0x0F127000,    // 70003CB6
+	0x0F1221A4,    // 70003CB8
+	0x0F127000,    // 70003CBA
+	0x0F12E200,    // 70003CBC
+	0x0F12D000,    // 70003CBE
+	0x0F124778,    // 70003CC0
+	0x0F1246C0,    // 70003CC2
+	0x0F12C000,    // 70003CC4
+	0x0F12E59F,    // 70003CC6
+	0x0F12FF1C,    // 70003CC8
+	0x0F12E12F,    // 70003CCA
+	0x0F121F63,    // 70003CCC
+	0x0F120001,    // 70003CCE
+	0x0F124778,    // 70003CD0
+	0x0F1246C0,    // 70003CD2
+	0x0F12C000,    // 70003CD4
+	0x0F12E59F,    // 70003CD6
+	0x0F12FF1C,    // 70003CD8
+	0x0F12E12F,    // 70003CDA
+	0x0F121EDF,    // 70003CDC
+	0x0F120001,    // 70003CDE
+	0x0F124778,    // 70003CE0
+	0x0F1246C0,    // 70003CE2
+	0x0F12C000,    // 70003CE4
+	0x0F12E59F,    // 70003CE6
+	0x0F12FF1C,    // 70003CE8
+	0x0F12E12F,    // 70003CEA
+	0x0F12495F,    // 70003CEC
+	0x0F120000,    // 70003CEE
+	0x0F124778,    // 70003CF0
+	0x0F1246C0,    // 70003CF2
+	0x0F12C000,    // 70003CF4
+	0x0F12E59F,    // 70003CF6
+	0x0F12FF1C,    // 70003CF8
+	0x0F12E12F,    // 70003CFA
+	0x0F12E403,    // 70003CFC
+	0x0F120000,    // 70003CFE
+	0x0F124778,    // 70003D00
+	0x0F1246C0,    // 70003D02
+	0x0F12C000,    // 70003D04
+	0x0F12E59F,    // 70003D06
+	0x0F12FF1C,    // 70003D08
+	0x0F12E12F,    // 70003D0A
+	0x0F1224B3,    // 70003D0C
+	0x0F120001,    // 70003D0E
+	0x0F124778,    // 70003D10
+	0x0F1246C0,    // 70003D12
+	0x0F12C000,    // 70003D14
+	0x0F12E59F,    // 70003D16
+	0x0F12FF1C,    // 70003D18
+	0x0F12E12F,    // 70003D1A
+	0x0F12EECD,    // 70003D1C
+	0x0F120000,    // 70003D1E
+	0x0F124778,    // 70003D20
+	0x0F1246C0,    // 70003D22
+	0x0F12C000,    // 70003D24
+	0x0F12E59F,    // 70003D26
+	0x0F12FF1C,    // 70003D28
+	0x0F12E12F,    // 70003D2A
+	0x0F12F049,    // 70003D2C
+	0x0F120000,    // 70003D2E
+	0x0F124778,    // 70003D30
+	0x0F1246C0,    // 70003D32
+	0x0F12C000,    // 70003D34
+	0x0F12E59F,    // 70003D36
+	0x0F12FF1C,    // 70003D38
+	0x0F12E12F,    // 70003D3A
+	0x0F1212DF,    // 70003D3C
+	0x0F120000,    // 70003D3E
+	0x0F124778,    // 70003D40
+	0x0F1246C0,    // 70003D42
+	0x0F12C000,    // 70003D44
+	0x0F12E59F,    // 70003D46
+	0x0F12FF1C,    // 70003D48
+	0x0F12E12F,    // 70003D4A
+	0x0F12F05B,    // 70003D4C
+	0x0F120000,    // 70003D4E
+	0x0F124778,    // 70003D50
+	0x0F1246C0,    // 70003D52
+	0x0F12C000,    // 70003D54
+	0x0F12E59F,    // 70003D56
+	0x0F12FF1C,    // 70003D58
+	0x0F12E12F,    // 70003D5A
+	0x0F12F07B,    // 70003D5C
+	0x0F120000,    // 70003D5E
+	0x0F124778,    // 70003D60
+	0x0F1246C0,    // 70003D62
+	0x0F12C000,    // 70003D64
+	0x0F12E59F,    // 70003D66
+	0x0F12FF1C,    // 70003D68
+	0x0F12E12F,    // 70003D6A
+	0x0F12FE6D,    // 70003D6C
+	0x0F120000,    // 70003D6E
+	0x0F124778,    // 70003D70
+	0x0F1246C0,    // 70003D72
+	0x0F12C000,    // 70003D74
+	0x0F12E59F,    // 70003D76
+	0x0F12FF1C,    // 70003D78
+	0x0F12E12F,    // 70003D7A
+	0x0F123295,    // 70003D7C
+	0x0F120000,    // 70003D7E
+	0x0F124778,    // 70003D80
+	0x0F1246C0,    // 70003D82
+	0x0F12C000,    // 70003D84
+	0x0F12E59F,    // 70003D86
+	0x0F12FF1C,    // 70003D88
+	0x0F12E12F,    // 70003D8A
+	0x0F12234F,    // 70003D8C
+	0x0F120000,    // 70003D8E
+	0x0F124778,    // 70003D90
+	0x0F1246C0,    // 70003D92
+	0x0F12C000,    // 70003D94
+	0x0F12E59F,    // 70003D96
+	0x0F12FF1C,    // 70003D98
+	0x0F12E12F,    // 70003D9A
+	0x0F124521,    // 70003D9C
+	0x0F120000,    // 70003D9E
+	0x0F124778,    // 70003DA0
+	0x0F1246C0,    // 70003DA2
+	0x0F12C000,    // 70003DA4
+	0x0F12E59F,    // 70003DA6
+	0x0F12FF1C,    // 70003DA8
+	0x0F12E12F,    // 70003DAA
+	0x0F127C0D,    // 70003DAC
+	0x0F120000,    // 70003DAE
+	0x0F124778,    // 70003DB0
+	0x0F1246C0,    // 70003DB2
+	0x0F12C000,    // 70003DB4
+	0x0F12E59F,    // 70003DB6
+	0x0F12FF1C,    // 70003DB8
+	0x0F12E12F,    // 70003DBA
+	0x0F127C2B,    // 70003DBC
+	0x0F120000,    // 70003DBE
+	0x0F124778,    // 70003DC0
+	0x0F1246C0,    // 70003DC2
+	0x0F12F004,    // 70003DC4
+	0x0F12E51F,    // 70003DC6
+	0x0F1224C4,    // 70003DC8
+	0x0F120001,    // 70003DCA
+	0x0F124778,    // 70003DCC
+	0x0F1246C0,    // 70003DCE
+	0x0F12C000,    // 70003DD0
+	0x0F12E59F,    // 70003DD2
+	0x0F12FF1C,    // 70003DD4
+	0x0F12E12F,    // 70003DD6
+	0x0F123183,    // 70003DD8
+	0x0F120000,    // 70003DDA
+	0x0F124778,    // 70003DDC
+	0x0F1246C0,    // 70003DDE
+	0x0F12C000,    // 70003DE0
+	0x0F12E59F,    // 70003DE2
+	0x0F12FF1C,    // 70003DE4
+	0x0F12E12F,    // 70003DE6
+	0x0F12302F,    // 70003DE8
+	0x0F120000,    // 70003DEA
+	0x0F124778,    // 70003DEC
+	0x0F1246C0,    // 70003DEE
+	0x0F12C000,    // 70003DF0
+	0x0F12E59F,    // 70003DF2
+	0x0F12FF1C,    // 70003DF4
+	0x0F12E12F,    // 70003DF6
+	0x0F12EF07,    // 70003DF8
+	0x0F120000,    // 70003DFA
+	0x0F124778,    // 70003DFC
+	0x0F1246C0,    // 70003DFE
+	0x0F12C000,    // 70003E00
+	0x0F12E59F,    // 70003E02
+	0x0F12FF1C,    // 70003E04
+	0x0F12E12F,    // 70003E06
+	0x0F1248FB,    // 70003E08
+	0x0F120000,    // 70003E0A
+	0x0F124778,    // 70003E0C
+	0x0F1246C0,    // 70003E0E
+	0x0F12C000,    // 70003E10
+	0x0F12E59F,    // 70003E12
+	0x0F12FF1C,    // 70003E14
+	0x0F12E12F,    // 70003E16
+	0x0F12F0B1,    // 70003E18
+	0x0F120000,    // 70003E1A
+	0x0F124778,    // 70003E1C
+	0x0F1246C0,    // 70003E1E
+	0x0F12C000,    // 70003E20
+	0x0F12E59F,    // 70003E22
+	0x0F12FF1C,    // 70003E24
+	0x0F12E12F,    // 70003E26
+	0x0F12EEDF,    // 70003E28
+	0x0F120000,    // 70003E2A
+	0x0F124778,    // 70003E2C
+	0x0F1246C0,    // 70003E2E
+	0x0F12C000,    // 70003E30
+	0x0F12E59F,    // 70003E32
+	0x0F12FF1C,    // 70003E34
+	0x0F12E12F,    // 70003E36
+	0x0F12AEF1,    // 70003E38
+	0x0F120000,    // 70003E3A
+	0x0F124778,    // 70003E3C
+	0x0F1246C0,    // 70003E3E
+	0x0F12C000,    // 70003E40
+	0x0F12E59F,    // 70003E42
+	0x0F12FF1C,    // 70003E44
+	0x0F12E12F,    // 70003E46
+	0x0F1202EB,    // 70003E48
+	0x0F120001,    // 70003E4A
+	0x0F124778,    // 70003E4C
+	0x0F1246C0,    // 70003E4E
+	0x0F12C000,    // 70003E50
+	0x0F12E59F,    // 70003E52
+	0x0F12FF1C,    // 70003E54
+	0x0F12E12F,    // 70003E56
+	0x0F12FD21,    // 70003E58
+	0x0F120000,    // 70003E5A
+	0x0F124778,    // 70003E5C
+	0x0F1246C0,    // 70003E5E
+	0x0F12C000,    // 70003E60
+	0x0F12E59F,    // 70003E62
+	0x0F12FF1C,    // 70003E64
+	0x0F12E12F,    // 70003E66
+	0x0F12FDAF,    // 70003E68
+	0x0F120000,    // 70003E6A
+	0x0F124778,    // 70003E6C
+	0x0F1246C0,    // 70003E6E
+	0x0F12C000,    // 70003E70
+	0x0F12E59F,    // 70003E72
+	0x0F12FF1C,    // 70003E74
+	0x0F12E12F,    // 70003E76
+	0x0F125027,    // 70003E78
+	0x0F120000,    // 70003E7A
+	0x0F124778,    // 70003E7C
+	0x0F1246C0,    // 70003E7E
+	0x0F12C000,    // 70003E80
+	0x0F12E59F,    // 70003E82
+	0x0F12FF1C,    // 70003E84
+	0x0F12E12F,    // 70003E86
+	0x0F1204C9,    // 70003E88
+	0x0F120000,    // 70003E8A
+	0x0F124778,    // 70003E8C
+	0x0F1246C0,    // 70003E8E
+	0x0F12C000,    // 70003E90
+	0x0F12E59F,    // 70003E92
+	0x0F12FF1C,    // 70003E94
+	0x0F12E12F,    // 70003E96
+	0x0F1239DF,    // 70003E98
+	0x0F120000,    // 70003E9A
+	0x0F124778,    // 70003E9C
+	0x0F1246C0,    // 70003E9E
+	0x0F12C000,    // 70003EA0
+	0x0F12E59F,    // 70003EA2
+	0x0F12FF1C,    // 70003EA4
+	0x0F12E12F,    // 70003EA6
+	0x0F126177,    // 70003EA8
+	0x0F120000,    // 70003EAA
+	0x0F124778,    // 70003EAC
+	0x0F1246C0,    // 70003EAE
+	0x0F12C000,    // 70003EB0
+	0x0F12E59F,    // 70003EB2
+	0x0F12FF1C,    // 70003EB4
+	0x0F12E12F,    // 70003EB6
+	0x0F12424F,    // 70003EB8
+	0x0F120000,    // 70003EBA
+	0x0F124778,    // 70003EBC
+	0x0F1246C0,    // 70003EBE
+	0x0F12C000,    // 70003EC0
+	0x0F12E59F,    // 70003EC2
+	0x0F12FF1C,    // 70003EC4
+	0x0F12E12F,    // 70003EC6
+	0x0F123F0D,    // 70003EC8
+	0x0F120000,    // 70003ECA
+	0x0F124778,    // 70003ECC
+	0x0F1246C0,    // 70003ECE
+	0x0F12C000,    // 70003ED0
+	0x0F12E59F,    // 70003ED2
+	0x0F12FF1C,    // 70003ED4
+	0x0F12E12F,    // 70003ED6
+	0x0F1202B9,    // 70003ED8
+	0x0F120001,    // 70003EDA
+	// End of Patch Data(Last : 70003EDAh)
+	// Total Size 2480 (09B0)
+	// Addr : 352C , Size : 2478(9AEh)
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007,         // clks_src_gf_force_enable
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	//	TNP_GAS_ALPHA_OTP
+	//	TNP_FR_ACCURATE_DYNAMIC
+	//	TNP_ADLC_TUNE
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120000, // on/off AFIT by NB option
+
+	0x0F120005, // NormBR[0]
+	0x0F120019, // NormBR[1]
+	0x0F120050, // NormBR[2]
+	0x0F120300, // NormBR[3]
+	0x0F120375, // NormBR[4]
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	// TNP_Regs_PreflashStart
+	0x0F120000,	// TNP_Regs_PreflashEnd
+	0x0F120260,	// TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	// BR Tuning
+	0x0F120100,	// TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	// TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	// WP Tuning
+	0x0F120040,	// TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	// T_BR tune
+	0x0F120150,	// TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F12002E,
+
+	0x002A0430,	//REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	//TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F120235,           //0244 0258 AWB R point          //0258 0245 0258
+	0x0F12024A,           //024D 0220 AWB B point          //0220 0245 0245
+
+
+	//         //         //         //         //         //         //         //         //
+	// Analog & APS settings         //         //         //         //         //         //
+	// This register is for FACTORY ONLY. If you change it without prior notification         //
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //
+	//         //         //         //         //         //         //         //         //
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshadi
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+
+	0x002AF132,
+	0x0F120206, // tgr_frame_decription 4
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//===========================================================================================
+
+	//============================= Line-ADLC Tuning ============================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//===========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F120132, //0138//awbb_IntcR
+	0x0F12010A, //011C//awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003,          //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+	0x0F120000,          //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041,          //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+	0x0F120000,          //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C,          //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for S
+	0x0F120190,          //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0,          //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000          //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000,          //#af_search_usAeStable
+	0x002A1494,
+	0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120003,          //#af_search_usFinePeakCount
+	0x0F120000,          //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120602, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000,          //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120003, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200CC, //#af_search_usPeakThr  for 80%
+	0x0F1200A0,          //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F12952F, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280,          //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0,          //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320,          //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030,          //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060,          //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003,          //#af_scene_usSaturatedScene
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120010,           //#af_pos_usTableLastInd 10h + 1h = 17 Steps
+
+	0x0F120030,           //#af_pos_usTable_0_  48
+	0x0F120033,           //#af_pos_usTable_1_  51
+	0x0F120036,           //#af_pos_usTable_2_  54
+	0x0F120039,           //#af_pos_usTable_3_  57
+	0x0F12003D,           //#af_pos_usTable_4_  61
+	0x0F120041,           //#af_pos_usTable_5_  65
+	0x0F120045,           //#af_pos_usTable_6_  69
+	0x0F120049,           //#af_pos_usTable_7_  73
+	0x0F12004E,           //#af_pos_usTable_8_  78
+	0x0F120053,           //#af_pos_usTable_9_  83
+	0x0F120059,           //#af_pos_usTable_10_ 89
+	0x0F120060,           //#af_pos_usTable_11_ 104
+	0x0F120068,           //#af_pos_usTable_12_ 109
+	0x0F120072,           //#af_pos_usTable_13_ 114
+	0x0F12007D,           //#af_pos_usTable_14_ 125
+	0x0F120089,           //#af_pos_usTable_15_ 137
+	0x0F120096,           //#af_pos_usTable_16_ 150
+
+	//8. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000,          //#afd_usParam[0]  I2C power down command
+	0x0F120006,          //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0,          //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8,          //#afd_usParam[3]  PWM Period
+	0x0F120000,          //#afd_usParam[4]  PWM Divider
+	0x0F120020,          //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120008,          //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120008,          //#afd_usParam[7]  Signal Shaping
+	0x0F120040,          //#afd_usParam[8]  Signal Shaping level
+	0x0F120080,          //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0,          //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0,          //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is
+	0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : M
+	0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with A
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12005C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000,                   //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002,                   //senHal_NExpLinesCheckFine                  //0004
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001,                   //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001,                   //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001,                   //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001,                   //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002,                   //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002,                   //senHal_SamplingType                  // 0:Full 1:digital 2:PL
+	0x0F120000,                   //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60,                   //pll_uMaxSysFreqKhz
+	0x0F127530,                   //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530,                   //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530,                   //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530,                   //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+	0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+	0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll by
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98
+	0x0F1254F8,	                  //57E4	                  //61A8
+
+	0x002A1B78,
+	0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,     //p10
+
+
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 640 480 system 52M PCLK 87M
+	//===================================================================
+	0x002A023E,
+	0x0F120500, //REG_0TC_PCFG_usWidth
+	0x0F120400, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+	0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+	0x0F120535, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a
+	0x0F12029A, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 87M
+	//===================================================================
+
+	0x002A032E,
+	0x0F120000,                   //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800,                   //REG_0TC_CCFG_usWidth
+	0x0F120600,                   //REG_0TC_CCFG_usHeight
+	0x0F120005,                   //REG_0TC_CCFG_Format                              //PCAM 5:YUV
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010,                   //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052
+	0x0F120010,                   //REG_0TC_CCFG_OIFMask
+	0x0F1203C0,                   //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001,                   //REG_0TC_CCFG_uClockInd
+	0x0F120002,                   //REG_0TC_CCFG_usFrTimeType
+	0x0F120002,                   //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535,                   //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A,                   //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000,                   //REG_0TC_CCFG_bSmearOutput
+	0x0F120000,                   //REG_0TC_CCFG_sSaturation
+	0x0F120000,                   //REG_0TC_CCFG_sSharpBlur
+	0x0F120000,                   //REG_0TC_CCFG_sColorTemp
+	0x0F120000,                   //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055,                   //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+	0x002A07FE,
+	0x0F123200, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123200, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123200, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123200, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123200, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123200, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F123F00,	//TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[0][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[0][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[0][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[0][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[0][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[0][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[0][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[0][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[0][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[0][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[0][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[0][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[0][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[0][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[0][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[0][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[0][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[0][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[0][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[0][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[1][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[1][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[1][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[1][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[1][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[1][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[1][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[1][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[1][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[1][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[1][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[1][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[1][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[1][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[1][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[1][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[1][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[1][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[1][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[1][19]
+	0x0F120000,          //saRR_usDualGammaLutRGBIndoor[2][0]
+	0x0F120008,          //saRR_usDualGammaLutRGBIndoor[2][1]
+	0x0F120015,          //saRR_usDualGammaLutRGBIndoor[2][2]
+	0x0F120032,          //saRR_usDualGammaLutRGBIndoor[2][3]
+	0x0F12006C,          //saRR_usDualGammaLutRGBIndoor[2][4]
+	0x0F1200D0,          //saRR_usDualGammaLutRGBIndoor[2][5]
+	0x0F120129,          //saRR_usDualGammaLutRGBIndoor[2][6]
+	0x0F120151,          //saRR_usDualGammaLutRGBIndoor[2][7]
+	0x0F120174,          //saRR_usDualGammaLutRGBIndoor[2][8]
+	0x0F1201AA,          //saRR_usDualGammaLutRGBIndoor[2][9]
+	0x0F1201D7,          //saRR_usDualGammaLutRGBIndoor[2][10]
+	0x0F1201FE,          //saRR_usDualGammaLutRGBIndoor[2][11]
+	0x0F120221,          //saRR_usDualGammaLutRGBIndoor[2][12]
+	0x0F120252,          //saRR_usDualGammaLutRGBIndoor[2][13]
+	0x0F120281,          //saRR_usDualGammaLutRGBIndoor[2][14]
+	0x0F1202E1,          //saRR_usDualGammaLutRGBIndoor[2][15]
+	0x0F120345,          //saRR_usDualGammaLutRGBIndoor[2][16]
+	0x0F12039C,          //saRR_usDualGammaLutRGBIndoor[2][17]
+	0x0F1203D9,          //saRR_usDualGammaLutRGBIndoor[2][18]
+	0x0F1203FF,          //saRR_usDualGammaLutRGBIndoor[2][19]
+
+	//s002A06D8
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR//MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Nigh
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight
+
+	//AE_state
+	0x002A04EE,
+	0x0F12010E, //#lt_uLimitHigh
+	0x0F1200F5, //#lt_uLimitLow
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //#lt_uMaxExp1
+	0x002A0508,
+	0x0F12681F, //#lt_uMaxExp2
+	0x002A050C,
+	0x0F128227, //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F12681F, //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F128227, //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F1201E0, //#lt_uMaxAnGain1
+	0x0F1201E0, //#lt_uMaxAnGain2
+	0x0F120300, //#lt_uMaxAnGain3
+	0x0F120710, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F1201E0, //#lt_uCapMaxAnGain1
+	0x0F1201E0, //#lt_uCapMaxAnGain2
+	0x0F120300, //#lt_uCapMaxAnGain3
+	0x0F120710, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120000, //ae_WeightTbl_16[0]
+	0x0F120000, //ae_WeightTbl_16[1]
+	0x0F120000, //ae_WeightTbl_16[2]
+	0x0F120000, //ae_WeightTbl_16[3]
+	0x0F120101, //ae_WeightTbl_16[4]
+	0x0F120101, //ae_WeightTbl_16[5]
+	0x0F120101, //ae_WeightTbl_16[6]
+	0x0F120101, //ae_WeightTbl_16[7]
+	0x0F120101, //ae_WeightTbl_16[8]
+	0x0F120201, //ae_WeightTbl_16[9]
+	0x0F120102, //ae_WeightTbl_16[10]
+	0x0F120101, //ae_WeightTbl_16[11]
+	0x0F120101, //ae_WeightTbl_16[12]
+	0x0F120202, //ae_WeightTbl_16[13]
+	0x0F120202, //ae_WeightTbl_16[14]
+	0x0F120101, //ae_WeightTbl_16[15]
+	0x0F120101, //ae_WeightTbl_16[16]
+	0x0F120202, //ae_WeightTbl_16[17]
+	0x0F120202, //ae_WeightTbl_16[18]
+	0x0F120101, //ae_WeightTbl_16[19]
+	0x0F120201, //ae_WeightTbl_16[20]
+	0x0F120202, //ae_WeightTbl_16[21]
+	0x0F120202, //ae_WeightTbl_16[22]
+	0x0F120102, //ae_WeightTbl_16[23]
+	0x0F120201, //ae_WeightTbl_16[24]
+	0x0F120202, //ae_WeightTbl_16[25]
+	0x0F120202, //ae_WeightTbl_16[26]
+	0x0F120102, //ae_WeightTbl_16[27]
+	0x0F120101, //ae_WeightTbl_16[28]
+	0x0F120101, //ae_WeightTbl_16[29]
+	0x0F120101, //ae_WeightTbl_16[30]
+	0x0F120101, //ae_WeightTbl_16[31]
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F1205F0, //awbb_GamutWidthThr1
+	0x0F1201F4, //awbb_GamutHeightThr1
+	0x0F12006C, //awbb_GamutWidthThr2
+	0x0F120038, //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F12000C, //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A291A,
+	0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+	0x0F120008,	//001E	//awbb_WpFilterMinThr
+	0x0F120160,	//0190	//awbb_WpFilterMaxThr
+	0x0F1200A0, //awbb_WpFilterCoef
+	0x0F120004, //awbb_WpFilterSize
+	0x0F120001, //awbb_otp_disable
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+	0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+	0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+	0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+	0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+	0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+	0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+	0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+	0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+	0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+	0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+	0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+	0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+	0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+	0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+	0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+	0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+	0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+	0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+	0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+	0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+	0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+	0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+	0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+	0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+	0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+	0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+	0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+	0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+	0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+	0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+	0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+	0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120010,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F1202C8, //awbb_GridConst_1[0]
+	0x0F120325, //awbb_GridConst_1[1]
+	0x0F12038F, //awbb_GridConst_1[2]
+
+	0x0F120F8E, //awbb_GridConst_2[0]
+	0x0F1210B3, //awbb_GridConst_2[1]
+	0x0F121136, //awbb_GridConst_2[2]
+	0x0F121138, //awbb_GridConst_2[3]
+	0x0F12118E, //awbb_GridConst_2[4]
+	0x0F121213, //awbb_GridConst_2[5]
+
+	0x0F1200A7, //awbb_GridCoeff_R_1
+	0x0F1200C2, //awbb_GridCoeff_B_1
+	0x0F1200BD, //awbb_GridCoeff_R_2
+	0x0F1200AC, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120050, //0032//awbb_GridCorr_R[0][0]
+	0x0F120032, //0012//awbb_GridCorr_R[0][1]
+	0x0F120032, //0012//awbb_GridCorr_R[0][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+	0x0F120060, //0050//awbb_GridCorr_R[0][5]
+	0x0F120050, //0032//awbb_GridCorr_R[1][0]
+	0x0F120032, //0012//awbb_GridCorr_R[1][1]
+	0x0F120032, //0012//awbb_GridCorr_R[1][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+	0x0F120060, //0050//awbb_GridCorr_R[1][5]
+	0x0F120050, //0032//awbb_GridCorr_R[2][0]
+	0x0F120032, //0012//awbb_GridCorr_R[2][1]
+	0x0F120032, //0012//awbb_GridCorr_R[2][2]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+	0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+	0x0F120060, //0050//awbb_GridCorr_R[2][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+	0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+	0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+	0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+	0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+	0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+	0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+	0x0F120000, //awbb_GridCorr_B_Out[0][2]
+	0x0F120000, //awbb_GridCorr_B_Out[0][3]
+	0x0F120000, //awbb_GridCorr_B_Out[0][4]
+	0x0F120000, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+	0x0F120000, //awbb_GridCorr_B_Out[1][2]
+	0x0F120000, //awbb_GridCorr_B_Out[1][3]
+	0x0F120000, //awbb_GridCorr_B_Out[1][4]
+	0x0F120000, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+	0x0F120000, //awbb_GridCorr_B_Out[2][2]
+	0x0F120000, //awbb_GridCorr_B_Out[2][3]
+	0x0F120000, //awbb_GridCorr_B_Out[2][4]
+	0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[4]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[8]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[9]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+	0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+	0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+	0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+	0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+	0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+	0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+	0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+	0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+	0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+	0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+	0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+	0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+	0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+	0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+	0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+	0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+	0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+	0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+	0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+	0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+	0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+	0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+	0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+	0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+	0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+	0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+	0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+	0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+	0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+	0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+	0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+	0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+	0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+	0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+	0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+	0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+	0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+	0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+	0x002A08C0,
+	0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700008C2           //AFIT16_CONTRAST
+	0x0F120000, //0000//700008C4           //AFIT16_SATURATION
+	0x0F120002, //0000//700008C6           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700008C8           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700008CA           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700008CC
+	0x0F1203FF, //03FF//700008CE           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700008D0           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700008D2           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700008D4           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700008D6           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700008D8           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700008DA           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700008DC           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700008DE           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700008E0           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700008E2           //AFIT16_demsharpmix1_iTune
+	0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+	0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+	0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C//700008EA           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008//700008EC           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700008EE           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700008F0           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700008F2           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700008F4           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700008F6           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+	0x0F121701, //1701//700008F8           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+	0x0F120229, //0229//700008FA           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+	0x0F121403, //1403//700008FC           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+	0x0F120004, //0004//700008FE           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+	0x0F120300, //0300//70000900           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+	0x0F120000, //0000//70000902           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+	0x0F1202FF, //02FF//70000904           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+	0x0F1205E8, //09E8//70000906           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+	0x0F121414, //1414//70000908           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+	0x0F120301, //0301//7000090A           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+	0x0F120007, //0007//7000090C           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F124000, //4000//7000090E
+	0x0F127803, //7803//70000910
+	0x0F123C50, //3C50//70000912
+	0x0F12003C, //003C//70000914
+	0x0F121E80, //1E80//70000916           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+	0x0F121E08, //1E08//70000918           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+	0x0F12000A, //000A//7000091A           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+	0x0F120000, //0000//7000091C           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+	0x0F12120A, //120A//7000091E           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+	0x0F121400, //0F00//70000920           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+	0x0F120200, //0200//70000922           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+	0x0F12FF00, //FF00//70000924           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+	0x0F120200, //0200//70000926           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+	0x0F121B11, //1B11//70000928           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+	0x0F120000, //0000//7000092A           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+	0x0F120009, //0009//7000092C           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+	0x0F120406, //0406//7000092E           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+	0x0F120605, //0605//70000930           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+	0x0F120307, //0307//70000932
+	0x0F120609, //0609//70000934
+	0x0F122C07, //2C07//70000936
+	0x0F12142C, //142C//70000938
+	0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120880, //0880//7000093E           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+	0x0F120B50, //0B50//70000940           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+	0x0F120080, //0080//70000942           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+	0x0F120101, //0101//70000944           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+	0x0F120707, //0707//70000946           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+	0x0F124601, //4601//70000948           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+	0x0F12A444, //C844//7000094A           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+	0x0F1250A4, //50C8//7000094C           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+	0x0F120500, //0500//7000094E           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+	0x0F120303, //0003//70000950           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+	0x0F121001, //1C01//70000952           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+	0x0F120710, //0714//70000954           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+	0x0F121448, //1464//70000956           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+	0x0F125A03, //5A04//70000958           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+	0x0F12281E, //3C1E//7000095A           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+	0x0F12200F, //400F//7000095C           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+	0x0F120204, //0204//7000095E           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+	0x0F121403, //1403//70000960           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+	0x0F120114, //0114//70000962           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000964           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+	0x0F124446, //4446//70000966           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+	0x0F12646E, //646E//70000968           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+	0x0F120028, //0028//7000096A           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+	0x0F12030A, //030A//7000096C           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+	0x0F120000, //0000//7000096E           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+	0x0F12141E, //141E//70000970           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+	0x0F12FF07, //FF07//70000972           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+	0x0F120432, //0432//70000974           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+	0x0F120000, //0000//70000976           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+	0x0F120F0F, //0F0F//70000978           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+	0x0F120440, //0440//7000097A           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+	0x0F120302, //0302//7000097C           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+	0x0F121414, //1414//7000097E           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000980           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+	0x0F124601, //4601//70000982           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+	0x0F126E44, //6E44//70000984           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+	0x0F122864, //2864//70000986           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+	0x0F120A00, //0A00//70000988           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+	0x0F120003, //0003//7000098A           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+	0x0F121E00, //1E00//7000098C           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+	0x0F120714, //0714//7000098E           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+	0x0F1232FF, //32FF//70000990           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+	0x0F120004, //0004//70000992           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+	0x0F120F00, //0F00//70000994           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+	0x0F12400F, //400F//70000996           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+	0x0F120204, //0204//70000998           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+	0x0F120003, //0003//7000099A           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//7000099C
+	0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//700009A0           //AFIT16_CONTRAST
+	0x0F120000, //0000//700009A2           //AFIT16_SATURATION
+	0x0F120002, //0000//700009A4           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//700009A6           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//700009A8           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//700009AA
+	0x0F1203FF, //03FF//700009AC           //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//700009AE           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//700009B0           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//700009B2           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//700009B4           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//700009B6           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//700009B8           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//700009BA           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//700009BC           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//700009BE           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//700009C0           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //006E//700009C8           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//700009CA           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//700009CC           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//700009CE           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//700009D0           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//700009D2           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//700009D4           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+	0x0F121701, //1701//700009D6           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+	0x0F120229, //0229//700009D8           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+	0x0F121403, //1403//700009DA           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+	0x0F120004, //0004//700009DC           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+	0x0F120300, //0300//700009DE           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+	0x0F120000, //0000//700009E0           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+	0x0F1202FF, //02FF//700009E2           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+	0x0F1205E8, //05E8//700009E4           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+	0x0F121414, //1414//700009E6           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+	0x0F120301, //0301//700009E8           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+	0x0F120007, //0007//700009EA           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F122000, //2000//700009EC
+	0x0F125003, //5003//700009EE
+	0x0F123228, //3228//700009F0
+	0x0F120032, //0032//700009F2
+	0x0F121E80, //1E80//700009F4           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+	0x0F121E08, //1E08//700009F6           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+	0x0F12000A, //000A//700009F8           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+	0x0F120000, //0000//700009FA           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+	0x0F12120A, //120A//700009FC           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+	0x0F121400, //1400//700009FE           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+	0x0F120200, //0200//70000A00           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+	0x0F12FF00, //FF00//70000A02           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+	0x0F120200, //0200//70000A04           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+	0x0F121B11, //1B11//70000A06           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+	0x0F120000, //0000//70000A08           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+	0x0F120009, //0009//70000A0A           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+	0x0F120406, //0406//70000A0C           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+	0x0F120605, //0605//70000A0E           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+	0x0F120307, //0307//70000A10
+	0x0F120609, //0609//70000A12
+	0x0F122C07, //2C07//70000A14
+	0x0F12142C, //142C//70000A16
+	0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120580, //0580//70000A1C           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+	0x0F120080, //0080//70000A1E           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+	0x0F120080, //0080//70000A20           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+	0x0F120101, //0101//70000A22           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+	0x0F120707, //0707//70000A24           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+	0x0F124B01, //4B01//70000A26           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+	0x0F12494B, //444B 494B//70000A28           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_i
+	0x0F125044, //503C 5044//70000A2A           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosa
+	0x0F120500, //0500//70000A2C           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+	0x0F120603, //0503//70000A2E           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+	0x0F120D03, //0D02//70000A30           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+	0x0F12071E, //071E//70000A32           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+	0x0F121432, //1432//70000A34           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+	0x0F125A01, //5A01//70000A36           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+	0x0F12281E, //281E//70000A38           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+	0x0F12200F, //200F//70000A3A           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+	0x0F120204, //0204//70000A3C           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+	0x0F121E03, //1E03//70000A3E           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+	0x0F12011E, //011E//70000A40           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000A42           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+	0x0F123A3C, //3A3C//70000A44           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+	0x0F12585A, //585A//70000A46           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+	0x0F120028, //0028//70000A48           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+	0x0F12030A, //030A//70000A4A           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+	0x0F120000, //0000//70000A4C           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+	0x0F12141E, //141E//70000A4E           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+	0x0F12FF07, //FF07//70000A50           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+	0x0F120432, //0432//70000A52           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+	0x0F120000, //0000//70000A54           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+	0x0F120F0F, //0F0F//70000A56           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+	0x0F120440, //0440//70000A58           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+	0x0F120302, //0302//70000A5A           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+	0x0F121E1E, //1E1E//70000A5C           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000A5E           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+	0x0F123C01, //3C01//70000A60           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+	0x0F125A3A, //5A3A//70000A62           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+	0x0F122858, //2858//70000A64           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+	0x0F120A00, //0A00//70000A66           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+	0x0F120003, //0003//70000A68           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+	0x0F121E00, //1E00//70000A6A           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+	0x0F120714, //0714//70000A6C           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+	0x0F1232FF, //32FF//70000A6E           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+	0x0F120004, //0004//70000A70           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+	0x0F120F00, //0F00//70000A72           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+	0x0F12400F, //400F//70000A74           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+	0x0F120204, //0204//70000A76           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+	0x0F120003, //0003//70000A78           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000A7A
+	0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000A7E           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000A80           //AFIT16_SATURATION
+	0x0F120000, //0000//70000A82           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000A84           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000A86           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000A88
+	0x0F1203FF, //03FF//70000A8A           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000A8C           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000A8E           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000A90           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000A92           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000A94           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F12012C, //012C//70000A96           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000A98           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000A9A           //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A//70000A9C           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000A9E           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000AA6           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000AA8           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12003C, //003C//70000AAA           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F12001E, //001E//70000AAC           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12003C, //003C//70000AAE           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F12001E, //001E//70000AB0           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000AB2           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+	0x0F121701, //1701//70000AB4           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+	0x0F120229, //0229//70000AB6           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+	0x0F121403, //1403//70000AB8           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+	0x0F120004, //0004//70000ABA           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+	0x0F120300, //0300//70000ABC           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+	0x0F120000, //0000//70000ABE           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+	0x0F1202FF, //02FF//70000AC0           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+	0x0F1205DE, //05DE//70000AC2           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+	0x0F121414, //1414//70000AC4           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+	0x0F120301, //0301//70000AC6           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+	0x0F120007, //0007//70000AC8           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000ACA
+	0x0F122803, //2803//70000ACC
+	0x0F12261E, //261E//70000ACE
+	0x0F120026, //0026//70000AD0
+	0x0F121E80, //1E80//70000AD2           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+	0x0F121E08, //1E08//70000AD4           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+	0x0F12010A, //010A//70000AD6           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+	0x0F120001, //0001//70000AD8           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+	0x0F123C0A, //3C0A//70000ADA           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+	0x0F122300, //2300//70000ADC           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+	0x0F120200, //0200//70000ADE           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+	0x0F12FF00, //FF00//70000AE0           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+	0x0F120200, //0200//70000AE2           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+	0x0F121B11, //1B11//70000AE4           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+	0x0F120000, //0000//70000AE6           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+	0x0F120009, //0009//70000AE8           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+	0x0F120406, //0406//70000AEA           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+	0x0F120605, //0605//70000AEC           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+	0x0F120307, //0307//70000AEE
+	0x0F120609, //0609//70000AF0
+	0x0F121C07, //1C07//70000AF2
+	0x0F121014, //1014//70000AF4
+	0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000AFA           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+	0x0F120080, //0080//70000AFC           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+	0x0F120080, //0080//70000AFE           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+	0x0F120101, //0101//70000B00           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+	0x0F120707, //0707//70000B02           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+	0x0F124B01, //4B01//70000B04           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+	0x0F122A4B, //2A4B//70000B06           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+	0x0F125020, //5020//70000B08           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+	0x0F120500, //0500//70000B0A           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+	0x0F121C03, //1C03//70000B0C           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+	0x0F120D0C, //0D0C//70000B0E           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+	0x0F120823, //0823//70000B10           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+	0x0F121428, //1428//70000B12           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+	0x0F126401, //6401//70000B14           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+	0x0F12282D, //282D//70000B16           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+	0x0F122012, //2012//70000B18           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+	0x0F120204, //0204//70000B1A           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+	0x0F122803, //2803//70000B1C           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+	0x0F120128, //0128//70000B1E           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000B20           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+	0x0F122224, //2224//70000B22           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+	0x0F123236, //3236//70000B24           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+	0x0F120028, //0028//70000B26           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+	0x0F12030A, //030A//70000B28           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+	0x0F120410, //0410//70000B2A           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+	0x0F12141E, //141E//70000B2C           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+	0x0F12FF07, //FF07//70000B2E           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+	0x0F120432, //0432//70000B30           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+	0x0F124050, //4050//70000B32           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+	0x0F120F0F, //0F0F//70000B34           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+	0x0F120440, //0440//70000B36           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+	0x0F120302, //0302//70000B38           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+	0x0F122828, //2828//70000B3A           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000B3C           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+	0x0F122401, //2401//70000B3E           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+	0x0F123622, //3622//70000B40           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+	0x0F122832, //2832//70000B42           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+	0x0F120A00, //0A00//70000B44           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+	0x0F121003, //1003//70000B46           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+	0x0F121E04, //1E04//70000B48           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+	0x0F120714, //0714//70000B4A           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+	0x0F1232FF, //32FF//70000B4C           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+	0x0F125004, //5004//70000B4E           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+	0x0F120F40, //0F40//70000B50           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+	0x0F12400F, //400F//70000B52           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+	0x0F120204, //0204//70000B54           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+	0x0F120003, //0003//70000B56           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000B58
+	0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//70000B5C           //AFIT16_CONTRAST
+	0x0F120000, //0000//70000B5E           //AFIT16_SATURATION
+	0x0F120000, //0000//70000B60           //AFIT16_SHARP_BLUR
+	0x0F120000, //0000//70000B62           //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//70000B64           //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//70000B66
+	0x0F1203FF, //03FF//70000B68           //AFIT16_Demosaicing_iSatVal
+	0x0F12009E, //009E//70000B6A           //AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F12017C, //017C//70000B6C           //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//70000B6E           //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//70000B70           //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//70000B72           //AFIT16_demsharpmix1_iHighThreshold
+	0x0F1200C8, //00C8//70000B74           //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8//70000B76           //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046//70000B78           //AFIT16_demsharpmix1_iLowSat
+	0x0F120050, //0050//70000B7A           //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//70000B7C           //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+	0x0F12008C, //008C//70000B84           //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//70000B86           //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12002D, //002D//70000B88           //AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//70000B8A           //AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F12002D, //002D//70000B8C           //AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//70000B8E           //AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//70000B90           //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+	0x0F121701, //1701//70000B92           //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+	0x0F120229, //0229//70000B94           //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+	0x0F121403, //1403//70000B96           //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+	0x0F120004, //0004//70000B98           //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+	0x0F120300, //0300//70000B9A           //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+	0x0F120000, //0000//70000B9C           //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+	0x0F1202FF, //02FF//70000B9E           //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+	0x0F1205DE, //05DE//70000BA0           //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+	0x0F121414, //1414//70000BA2           //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+	0x0F120301, //0301//70000BA4           //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+	0x0F120007, //0007//70000BA6           //AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//70000BA8
+	0x0F122303, //2303//70000BAA
+	0x0F12231A, //231A//70000BAC
+	0x0F120023, //0023//70000BAE
+	0x0F121E80, //1E80//70000BB0           //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+	0x0F121E08, //1E08//70000BB2           //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+	0x0F12010A, //010A//70000BB4           //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+	0x0F120001, //0001//70000BB6           //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+	0x0F123C0A, //3C0A//70000BB8           //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+	0x0F122300, //2300//70000BBA           //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+	0x0F120200, //0200//70000BBC           //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+	0x0F12FF00, //FF00//70000BBE           //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+	0x0F120200, //0200//70000BC0           //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+	0x0F121E10, //1E10//70000BC2           //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+	0x0F120000, //0000//70000BC4           //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+	0x0F120009, //0009//70000BC6           //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+	0x0F120406, //0406//70000BC8           //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+	0x0F120705, //0705//70000BCA           //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+	0x0F120306, //0306//70000BCC
+	0x0F120509, //0509//70000BCE
+	0x0F122806, //2806//70000BD0
+	0x0F121428, //1428//70000BD2
+	0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//70000BD8           //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+	0x0F120080, //0080//70000BDA           //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+	0x0F120080, //0080//70000BDC           //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+	0x0F120101, //0101//70000BDE           //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+	0x0F120707, //0707//70000BE0           //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+	0x0F124B01, //4B01//70000BE2           //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+	0x0F122A4B, //2A4B//70000BE4           //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+	0x0F125020, //5020//70000BE6           //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+	0x0F120500, //0500//70000BE8           //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+	0x0F121C03, //1C03//70000BEA           //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+	0x0F120D0C, //0D0C//70000BEC           //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+	0x0F120823, //0823//70000BEE           //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+	0x0F121428, //1428//70000BF0           //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+	0x0F126401, //6401//70000BF2           //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+	0x0F12282D, //282D//70000BF4           //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+	0x0F122012, //2012//70000BF6           //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+	0x0F120204, //0204//70000BF8           //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+	0x0F123C03, //3C03//70000BFA           //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+	0x0F12013C, //013C//70000BFC           //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000BFE           //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+	0x0F121C1E, //1C1E//70000C00           //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+	0x0F121E22, //1E22//70000C02           //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+	0x0F120028, //0028//70000C04           //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+	0x0F12030A, //030A//70000C06           //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+	0x0F120214, //0214//70000C08           //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+	0x0F120E14, //0E14//70000C0A           //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+	0x0F12FF06, //FF06//70000C0C           //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+	0x0F120432, //0432//70000C0E           //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+	0x0F124052, //4052//70000C10           //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+	0x0F12150C, //150C//70000C12           //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+	0x0F120440, //0440//70000C14           //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+	0x0F120302, //0302//70000C16           //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+	0x0F123C3C, //3C3C//70000C18           //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+	0x0F120101, //0101//70000C1A           //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+	0x0F121E01, //1E01//70000C1C           //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+	0x0F12221C, //221C//70000C1E           //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+	0x0F12281E, //281E//70000C20           //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+	0x0F120A00, //0A00//70000C22           //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+	0x0F121403, //1403//70000C24           //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+	0x0F121402, //1402//70000C26           //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+	0x0F12060E, //060E//70000C28           //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+	0x0F1232FF, //32FF//70000C2A           //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+	0x0F125204, //5204//70000C2C           //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+	0x0F120C40, //0C40//70000C2E           //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+	0x0F124015, //4015//70000C30           //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+	0x0F120204, //0204//70000C32           //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+	0x0F120003, //0003//70000C34           //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//70000C36
+	0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+	0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+	0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+	0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+	0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+	0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+	0x0F120000, //0000//0000//70000C44
+	0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+	0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+	0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+	0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+	0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+	0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+	0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+	0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+	0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+	0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+	0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+	0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+	0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:
+	0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:
+	0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+	0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed
+	0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshL
+	0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThres
+	0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePow
+	0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+	0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower
+	0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHigh
+	0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlope
+	0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]
+	0x0F121000, //1000//1000//70000C86
+	0x0F122003, //2003//2003//70000C88
+	0x0F121020, //1020//1020//70000C8A
+	0x0F120010, //0010//0010//70000C8C
+	0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonoc
+	0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_
+	0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDe
+	0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iN
+	0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_
+	0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharp
+	0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpW
+	0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iS
+	0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1
+	0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoef
+	0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNar
+	0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_i
+	0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHy
+	0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_
+	0x0F120305, //0305//0305//70000CAA
+	0x0F120609, //0609//0609//70000CAC
+	0x0F122C07, //2C07//2C07//70000CAE
+	0x0F12142C, //142C//142C//70000CB0
+	0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+	0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkRe
+	0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset
+	0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation
+	0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThr
+	0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT
+	0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Lo
+	0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshL
+	0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdg
+	0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaic
+	0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing
+	0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicin
+	0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicin
+	0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iD
+	0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_i
+	0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_
+	0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_
+	0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmi
+	0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iC
+	0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClu
+	0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClust
+	0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_H
+	0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenT
+	0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing
+	0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demo
+	0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosai
+	0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosa
+	0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_
+	0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaici
+	0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpeni
+	0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpenin
+	0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Shar
+	0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsh
+	0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClu
+	0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClus
+	0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_Disp
+	0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenTh
+	0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing
+	0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demo
+	0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demos
+	0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demos
+	0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosa
+	0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaici
+	0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpen
+	0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpe
+	0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpen
+	0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsh
+	0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+	0x0F120001, //0001//0001//70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F122102, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+};
+
+static const u32 s5k5ccgx_hd_init_reg[] = {
+	//****************************************/
+	0xFCFCD000,
+	//****************************************/
+	//===================================================================
+	// History
+	//===================================================================
+	//20100717 : 1st release
+	//20100806 : 2nd release for EVT0.1
+	//20101028 : 3rd release for EVT1
+	//WRITE #awbb_otp_disable  0000                            //awb otp use
+	//==========================================================================================
+	//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+	//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+	//==========================================================================================
+	//===================================================================
+	// Reset & Trap and Patch
+	//===================================================================
+
+	// Start of Trap and Patch
+	//  2010-08-11 13:53:35
+	0x00100001,
+	0x10300000,
+	0x00140001,
+
+	0xFFFF000A, //p10
+	// Start of Patch data
+	// Start of Patch data
+	0x00287000,
+	/*++ Add ESD */
+	0x002A0150,
+	0x0F12AAAA,
+	/*-- Add ESD */
+	0x002A352C,
+	0x0F12B570, // 7000352C
+	0x0F124A24, // 7000352E
+	0x0F124924, // 70003530
+	0x0F124825, // 70003532
+	0x0F124B25, // 70003534
+	0x0F122500, // 70003536
+	0x0F12801D, // 70003538
+	0x0F12C004, // 7000353A
+	0x0F126001, // 7000353C
+	0x0F124924, // 7000353E
+	0x0F124824, // 70003540
+	0x0F12F000, // 70003542
+	0x0F12FBBD, // 70003544
+	0x0F124924, // 70003546
+	0x0F124824, // 70003548
+	0x0F12F000, // 7000354A
+	0x0F12FBB9, // 7000354C
+	0x0F124824, // 7000354E
+	0x0F124E24, // 70003550
+	0x0F126430, // 70003552
+	0x0F124924, // 70003554
+	0x0F124825, // 70003556
+	0x0F12F000, // 70003558
+	0x0F12FBB2, // 7000355A
+	0x0F124924, // 7000355C
+	0x0F120030, // 7000355E
+	0x0F123080, // 70003560
+	0x0F126141, // 70003562
+	0x0F124C23, // 70003564
+	0x0F128365, // 70003566
+	0x0F124923, // 70003568
+	0x0F124824, // 7000356A
+	0x0F12F000, // 7000356C
+	0x0F12FBA8, // 7000356E
+	0x0F124923, // 70003570
+	0x0F124824, // 70003572
+	0x0F12F000, // 70003574
+	0x0F12FBA4, // 70003576
+	0x0F124923, // 70003578
+	0x0F124824, // 7000357A
+	0x0F12F000, // 7000357C
+	0x0F12FBA0, // 7000357E
+	0x0F124923, // 70003580
+	0x0F124824, // 70003582
+	0x0F12F000, // 70003584
+	0x0F12FB9C, // 70003586
+	0x0F128125, // 70003588
+	0x0F124923, // 7000358A
+	0x0F124823, // 7000358C
+	0x0F12F000, // 7000358E
+	0x0F12FB97, // 70003590
+	0x0F124923, // 70003592
+	0x0F124823, // 70003594
+	0x0F12F000, // 70003596
+	0x0F12FB93, // 70003598
+	0x0F1283A5, // 7000359A
+	0x0F124922, // 7000359C
+	0x0F124823, // 7000359E
+	0x0F12F000, // 700035A0
+	0x0F12FB8E, // 700035A2
+	0x0F122101, // 700035A4
+	0x0F120349, // 700035A6
+	0x0F120020, // 700035A8
+	0x0F123020, // 700035AA
+	0x0F128041, // 700035AC
+	0x0F122185, // 700035AE
+	0x0F128081, // 700035B0
+	0x0F12491F, // 700035B2
+	0x0F1280C1, // 700035B4
+	0x0F12481F, // 700035B6
+	0x0F126730, // 700035B8
+	0x0F12BC70, // 700035BA
+	0x0F12BC08, // 700035BC
+	0x0F124718, // 700035BE
+	0x0F1200CA, // 700035C0
+	0x0F125CC1, // 700035C2
+	0x0F1203BD, // 700035C4
+	0x0F120000, // 700035C6
+	0x0F121C08, // 700035C8
+	0x0F127000, // 700035CA
+	0x0F123290, // 700035CC
+	0x0F127000, // 700035CE
+	0x0F123657, // 700035D0
+	0x0F127000, // 700035D2
+	0x0F12D9E7, // 700035D4
+	0x0F120000, // 700035D6
+	0x0F12383F, // 700035D8
+	0x0F127000, // 700035DA
+	0x0F12395D, // 700035DC
+	0x0F120000, // 700035DE
+	0x0F1238D1, // 700035E0
+	0x0F127000, // 700035E2
+	0x0F120000, // 700035E4
+	0x0F127000, // 700035E6
+	0x0F12399D, // 700035E8
+	0x0F127000, // 700035EA
+	0x0F12F903, // 700035EC
+	0x0F120000, // 700035EE
+	0x0F123AC1, // 700035F0
+	0x0F127000, // 700035F2
+	0x0F123FC8, // 700035F4
+	0x0F127000, // 700035F6
+	0x0F12368F, // 700035F8
+	0x0F127000, // 700035FA
+	0x0F12495F, // 700035FC
+	0x0F120000, // 700035FE
+	0x0F1236ED, // 70003600
+	0x0F127000, // 70003602
+	0x0F12E421, // 70003604
+	0x0F120000, // 70003606
+	0x0F1237AB, // 70003608
+	0x0F127000, // 7000360A
+	0x0F12216D, // 7000360C
+	0x0F120000, // 7000360E
+	0x0F12381F, // 70003610
+	0x0F127000, // 70003612
+	0x0F120179, // 70003614
+	0x0F120001, // 70003616
+	0x0F123BD5, // 70003618
+	0x0F127000, // 7000361A
+	0x0F1204C9, // 7000361C
+	0x0F120000, // 7000361E
+	0x0F123B25, // 70003620
+	0x0F127000, // 70003622
+	0x0F125027, // 70003624
+	0x0F120000, // 70003626
+	0x0F123BE1, // 70003628
+	0x0F127000, // 7000362A
+	0x0F1242B7, // 7000362C
+	0x0F120000, // 7000362E
+	0x0F1207FF, // 70003630
+	0x0F120000, // 70003632
+	0x0F123C5F, // 70003634
+	0x0F127000, // 70003636
+	0x0F12B570, // 70003638
+	0x0F12000D, // 7000363A
+	0x0F124CFC, // 7000363C
+	0x0F128821, // 7000363E
+	0x0F12F000, // 70003640
+	0x0F12FB46, // 70003642
+	0x0F128820, // 70003644
+	0x0F124AFB, // 70003646
+	0x0F120081, // 70003648
+	0x0F125055, // 7000364A
+	0x0F121C40, // 7000364C
+	0x0F128020, // 7000364E
+	0x0F12BC70, // 70003650
+	0x0F12BC08, // 70003652
+	0x0F124718, // 70003654
+	0x0F126801, // 70003656
+	0x0F120409, // 70003658
+	0x0F120C09, // 7000365A
+	0x0F126840, // 7000365C
+	0x0F120400, // 7000365E
+	0x0F120C00, // 70003660
+	0x0F124AF5, // 70003662
+	0x0F128992, // 70003664
+	0x0F122A00, // 70003666
+	0x0F12D00D, // 70003668
+	0x0F122300, // 7000366A
+	0x0F121A80, // 7000366C
+	0x0F12D400, // 7000366E
+	0x0F120003, // 70003670
+	0x0F120418, // 70003672
+	0x0F120C00, // 70003674
+	0x0F124BF1, // 70003676
+	0x0F121851, // 70003678
+	0x0F12891B, // 7000367A
+	0x0F12428B, // 7000367C
+	0x0F12D300, // 7000367E
+	0x0F12000B, // 70003680
+	0x0F120419, // 70003682
+	0x0F120C09, // 70003684
+	0x0F124AEE, // 70003686
+	0x0F128151, // 70003688
+	0x0F128190, // 7000368A
+	0x0F124770, // 7000368C
+	0x0F12B510, // 7000368E
+	0x0F124CEC, // 70003690
+	0x0F1248ED, // 70003692
+	0x0F1278A1, // 70003694
+	0x0F122900, // 70003696
+	0x0F12D101, // 70003698
+	0x0F1287C1, // 7000369A
+	0x0F12E004, // 7000369C
+	0x0F127AE1, // 7000369E
+	0x0F122900, // 700036A0
+	0x0F12D001, // 700036A2
+	0x0F122101, // 700036A4
+	0x0F1287C1, // 700036A6
+	0x0F12F000, // 700036A8
+	0x0F12FB1A, // 700036AA
+	0x0F1249E7, // 700036AC
+	0x0F128B08, // 700036AE
+	0x0F1206C2, // 700036B0
+	0x0F12D50A, // 700036B2
+	0x0F127AA2, // 700036B4
+	0x0F120652, // 700036B6
+	0x0F12D507, // 700036B8
+	0x0F122210, // 700036BA
+	0x0F124390, // 700036BC
+	0x0F128308, // 700036BE
+	0x0F1248E3, // 700036C0
+	0x0F127AE1, // 700036C2
+	0x0F126B00, // 700036C4
+	0x0F12F000, // 700036C6
+	0x0F12FB13, // 700036C8
+	0x0F1248DB, // 700036CA
+	0x0F1289C0, // 700036CC
+	0x0F122801, // 700036CE
+	0x0F12D109, // 700036D0
+	0x0F1278A0, // 700036D2
+	0x0F122800, // 700036D4
+	0x0F12D006, // 700036D6
+	0x0F127AE0, // 700036D8
+	0x0F122800, // 700036DA
+	0x0F12D003, // 700036DC
+	0x0F127AA0, // 700036DE
+	0x0F122140, // 700036E0
+	0x0F124308, // 700036E2
+	0x0F1272A0, // 700036E4
+	0x0F12BC10, // 700036E6
+	0x0F12BC08, // 700036E8
+	0x0F124718, // 700036EA
+	0x0F12B570, // 700036EC
+	0x0F124DD7, // 700036EE
+	0x0F124CD7, // 700036F0
+	0x0F128B28, // 700036F2
+	0x0F120701, // 700036F4
+	0x0F12D507, // 700036F6
+	0x0F122108, // 700036F8
+	0x0F124388, // 700036FA
+	0x0F128328, // 700036FC
+	0x0F1249D5, // 700036FE
+	0x0F126B20, // 70003700
+	0x0F126B89, // 70003702
+	0x0F12F000, // 70003704
+	0x0F12FAFC, // 70003706
+	0x0F128B28, // 70003708
+	0x0F1206C1, // 7000370A
+	0x0F12D5A0, // 7000370C
+	0x0F1249CD, // 7000370E
+	0x0F127A8A, // 70003710
+	0x0F120652, // 70003712
+	0x0F12D49C, // 70003714
+	0x0F122210, // 70003716
+	0x0F124390, // 70003718
+	0x0F128328, // 7000371A
+	0x0F127AC9, // 7000371C
+	0x0F126B20, // 7000371E
+	0x0F12F000, // 70003720
+	0x0F12FAE6, // 70003722
+	0x0F12E794, // 70003724
+	0x0F12B5F8, // 70003726
+	0x0F1249CB, // 70003728
+	0x0F128F08, // 7000372A
+	0x0F12000C, // 7000372C
+	0x0F123480, // 7000372E
+	0x0F122800, // 70003730
+	0x0F12D000, // 70003732
+	0x0F128360, // 70003734
+	0x0F122000, // 70003736
+	0x0F128708, // 70003738
+	0x0F124DC8, // 7000373A
+	0x0F1226FF, // 7000373C
+	0x0F128828, // 7000373E
+	0x0F121C76, // 70003740
+	0x0F122702, // 70003742
+	0x0F122803, // 70003744
+	0x0F12D112, // 70003746
+	0x0F128868, // 70003748
+	0x0F122800, // 7000374A
+	0x0F12D10F, // 7000374C
+	0x0F1288E8, // 7000374E
+	0x0F122800, // 70003750
+	0x0F12D10C, // 70003752
+	0x0F12F000, // 70003754
+	0x0F12FADC, // 70003756
+	0x0F122800, // 70003758
+	0x0F12D008, // 7000375A
+	0x0F128B60, // 7000375C
+	0x0F122800, // 7000375E
+	0x0F12D001, // 70003760
+	0x0F1280EE, // 70003762
+	0x0F1280AF, // 70003764
+	0x0F122001, // 70003766
+	0x0F127268, // 70003768
+	0x0F12F000, // 7000376A
+	0x0F12FAD9, // 7000376C
+	0x0F128828, // 7000376E
+	0x0F122802, // 70003770
+	0x0F12D10E, // 70003772
+	0x0F128868, // 70003774
+	0x0F122800, // 70003776
+	0x0F12D10B, // 70003778
+	0x0F1288E8, // 7000377A
+	0x0F122800, // 7000377C
+	0x0F12D108, // 7000377E
+	0x0F128B60, // 70003780
+	0x0F122800, // 70003782
+	0x0F12D001, // 70003784
+	0x0F1280EE, // 70003786
+	0x0F1280AF, // 70003788
+	0x0F122001, // 7000378A
+	0x0F127268, // 7000378C
+	0x0F12F000, // 7000378E
+	0x0F12FAC7, // 70003790
+	0x0F1288E8, // 70003792
+	0x0F122800, // 70003794
+	0x0F12D006, // 70003796
+	0x0F121FC1, // 70003798
+	0x0F1239FD, // 7000379A
+	0x0F12D003, // 7000379C
+	0x0F122001, // 7000379E
+	0x0F12BCF8, // 700037A0
+	0x0F12BC08, // 700037A2
+	0x0F124718, // 700037A4
+	0x0F122000, // 700037A6
+	0x0F12E7FA, // 700037A8
+	0x0F12B570, // 700037AA
+	0x0F124CAC, // 700037AC
+	0x0F128860, // 700037AE
+	0x0F122800, // 700037B0
+	0x0F12D00C, // 700037B2
+	0x0F128820, // 700037B4
+	0x0F124DA3, // 700037B6
+	0x0F122800, // 700037B8
+	0x0F12D009, // 700037BA
+	0x0F120029, // 700037BC
+	0x0F1231A0, // 700037BE
+	0x0F127AC9, // 700037C0
+	0x0F122900, // 700037C2
+	0x0F12D004, // 700037C4
+	0x0F127AA8, // 700037C6
+	0x0F122180, // 700037C8
+	0x0F124308, // 700037CA
+	0x0F1272A8, // 700037CC
+	0x0F12E73F, // 700037CE
+	0x0F122800, // 700037D0
+	0x0F12D003, // 700037D2
+	0x0F12F7FF, // 700037D4
+	0x0F12FFA7, // 700037D6
+	0x0F122800, // 700037D8
+	0x0F12D1F8, // 700037DA
+	0x0F122000, // 700037DC
+	0x0F128060, // 700037DE
+	0x0F128820, // 700037E0
+	0x0F122800, // 700037E2
+	0x0F12D003, // 700037E4
+	0x0F122008, // 700037E6
+	0x0F12F000, // 700037E8
+	0x0F12FAA2, // 700037EA
+	0x0F12E00B, // 700037EC
+	0x0F12489C, // 700037EE
+	0x0F123020, // 700037F0
+	0x0F128880, // 700037F2
+	0x0F122800, // 700037F4
+	0x0F12D103, // 700037F6
+	0x0F127AA8, // 700037F8
+	0x0F122101, // 700037FA
+	0x0F124308, // 700037FC
+	0x0F1272A8, // 700037FE
+	0x0F122010, // 70003800
+	0x0F12F000, // 70003802
+	0x0F12FA95, // 70003804
+	0x0F128820, // 70003806
+	0x0F122800, // 70003808
+	0x0F12D1E0, // 7000380A
+	0x0F12488A, // 7000380C
+	0x0F1289C0, // 7000380E
+	0x0F122801, // 70003810
+	0x0F12D1DC, // 70003812
+	0x0F127AA8, // 70003814
+	0x0F1221BF, // 70003816
+	0x0F124008, // 70003818
+	0x0F1272A8, // 7000381A
+	0x0F12E718, // 7000381C
+	0x0F126800, // 7000381E
+	0x0F124990, // 70003820
+	0x0F128188, // 70003822
+	0x0F124890, // 70003824
+	0x0F122201, // 70003826
+	0x0F128981, // 70003828
+	0x0F124890, // 7000382A
+	0x0F120252, // 7000382C
+	0x0F124291, // 7000382E
+	0x0F12D902, // 70003830
+	0x0F122102, // 70003832
+	0x0F128181, // 70003834
+	0x0F124770, // 70003836
+	0x0F122101, // 70003838
+	0x0F128181, // 7000383A
+	0x0F124770, // 7000383C
+	0x0F12B5F1, // 7000383E
+	0x0F124E80, // 70003840
+	0x0F128834, // 70003842
+	0x0F122C00, // 70003844
+	0x0F12D03F, // 70003846
+	0x0F122001, // 70003848
+	0x0F122C08, // 7000384A
+	0x0F12D000, // 7000384C
+	0x0F122000, // 7000384E
+	0x0F1270B0, // 70003850
+	0x0F124D7F, // 70003852
+	0x0F122800, // 70003854
+	0x0F12D009, // 70003856
+	0x0F12F000, // 70003858
+	0x0F12FA72, // 7000385A
+	0x0F120028, // 7000385C
+	0x0F1238F0, // 7000385E
+	0x0F126328, // 70003860
+	0x0F127AB0, // 70003862
+	0x0F12217E, // 70003864
+	0x0F124008, // 70003866
+	0x0F1272B0, // 70003868
+	0x0F12E00F, // 7000386A
+	0x0F124F7A, // 7000386C
+	0x0F123780, // 7000386E
+	0x0F128B78, // 70003870
+	0x0F122800, // 70003872
+	0x0F12D005, // 70003874
+	0x0F12F000, // 70003876
+	0x0F12FA6B, // 70003878
+	0x0F122000, // 7000387A
+	0x0F128378, // 7000387C
+	0x0F124976, // 7000387E
+	0x0F128708, // 70003880
+	0x0F122000, // 70003882
+	0x0F12F000, // 70003884
+	0x0F12FA6C, // 70003886
+	0x0F124879, // 70003888
+	0x0F126328, // 7000388A
+	0x0F1278B1, // 7000388C
+	0x0F122700, // 7000388E
+	0x0F120038, // 70003890
+	0x0F122900, // 70003892
+	0x0F12D008, // 70003894
+	0x0F124972, // 70003896
+	0x0F123920, // 70003898
+	0x0F128ACA, // 7000389A
+	0x0F122A00, // 7000389C
+	0x0F12D003, // 7000389E
+	0x0F128B09, // 700038A0
+	0x0F122900, // 700038A2
+	0x0F12D000, // 700038A4
+	0x0F122001, // 700038A6
+	0x0F127170, // 700038A8
+	0x0F122C02, // 700038AA
+	0x0F12D102, // 700038AC
+	0x0F124868, // 700038AE
+	0x0F123860, // 700038B0
+	0x0F126328, // 700038B2
+	0x0F122201, // 700038B4
+	0x0F122C02, // 700038B6
+	0x0F12D000, // 700038B8
+	0x0F122200, // 700038BA
+	0x0F124861, // 700038BC
+	0x0F122110, // 700038BE
+	0x0F12300A, // 700038C0
+	0x0F12F000, // 700038C2
+	0x0F12FA55, // 700038C4
+	0x0F128037, // 700038C6
+	0x0F129900, // 700038C8
+	0x0F120020, // 700038CA
+	0x0F12600C, // 700038CC
+	0x0F12E767, // 700038CE
+	0x0F12B538, // 700038D0
+	0x0F124865, // 700038D2
+	0x0F124669, // 700038D4
+	0x0F123848, // 700038D6
+	0x0F12F000, // 700038D8
+	0x0F12FA52, // 700038DA
+	0x0F124A5E, // 700038DC
+	0x0F124862, // 700038DE
+	0x0F128F51, // 700038E0
+	0x0F122400, // 700038E2
+	0x0F123020, // 700038E4
+	0x0F122900, // 700038E6
+	0x0F12D00A, // 700038E8
+	0x0F128754, // 700038EA
+	0x0F126941, // 700038EC
+	0x0F126451, // 700038EE
+	0x0F126491, // 700038F0
+	0x0F12466B, // 700038F2
+	0x0F128819, // 700038F4
+	0x0F1287D1, // 700038F6
+	0x0F12885B, // 700038F8
+	0x0F120011, // 700038FA
+	0x0F123140, // 700038FC
+	0x0F12800B, // 700038FE
+	0x0F128F91, // 70003900
+	0x0F122900, // 70003902
+	0x0F12D002, // 70003904
+	0x0F128794, // 70003906
+	0x0F126940, // 70003908
+	0x0F126490, // 7000390A
+	0x0F12F000, // 7000390C
+	0x0F12FA40, // 7000390E
+	0x0F12BC38, // 70003910
+	0x0F12BC08, // 70003912
+	0x0F124718, // 70003914
+	0x0F12B5F8, // 70003916
+	0x0F124C56, // 70003918
+	0x0F1289E0, // 7000391A
+	0x0F12F000, // 7000391C
+	0x0F12FA40, // 7000391E
+	0x0F120006, // 70003920
+	0x0F128A20, // 70003922
+	0x0F12F000, // 70003924
+	0x0F12FA44, // 70003926
+	0x0F120007, // 70003928
+	0x0F12484F, // 7000392A
+	0x0F124D4A, // 7000392C
+	0x0F123020, // 7000392E
+	0x0F126CA9, // 70003930
+	0x0F126940, // 70003932
+	0x0F121809, // 70003934
+	0x0F120200, // 70003936
+	0x0F12F000, // 70003938
+	0x0F12FA42, // 7000393A
+	0x0F120400, // 7000393C
+	0x0F120C00, // 7000393E
+	0x0F12002A, // 70003940
+	0x0F12326E, // 70003942
+	0x0F120011, // 70003944
+	0x0F12390A, // 70003946
+	0x0F122305, // 70003948
+	0x0F12F000, // 7000394A
+	0x0F12FA3F, // 7000394C
+	0x0F124C43, // 7000394E
+	0x0F1261A0, // 70003950
+	0x0F128FEB, // 70003952
+	0x0F120002, // 70003954
+	0x0F120031, // 70003956
+	0x0F120018, // 70003958
+	0x0F12F000, // 7000395A
+	0x0F12FA3F, // 7000395C
+	0x0F12466B, // 7000395E
+	0x0F120005, // 70003960
+	0x0F128018, // 70003962
+	0x0F12483C, // 70003964
+	0x0F1269A2, // 70003966
+	0x0F123040, // 70003968
+	0x0F128800, // 7000396A
+	0x0F120039, // 7000396C
+	0x0F12F000, // 7000396E
+	0x0F12FA35, // 70003970
+	0x0F12466B, // 70003972
+	0x0F120006, // 70003974
+	0x0F128058, // 70003976
+	0x0F120021, // 70003978
+	0x0F129800, // 7000397A
+	0x0F12311C, // 7000397C
+	0x0F12F000, // 7000397E
+	0x0F12FA35, // 70003980
+	0x0F124935, // 70003982
+	0x0F123180, // 70003984
+	0x0F12808D, // 70003986
+	0x0F1280CE, // 70003988
+	0x0F128BA1, // 7000398A
+	0x0F124836, // 7000398C
+	0x0F123820, // 7000398E
+	0x0F128001, // 70003990
+	0x0F128BE1, // 70003992
+	0x0F128041, // 70003994
+	0x0F128C21, // 70003996
+	0x0F128081, // 70003998
+	0x0F12E701, // 7000399A
+	0x0F12B5F8, // 7000399C
+	0x0F124E2E, // 7000399E
+	0x0F126C70, // 700039A0
+	0x0F126CB1, // 700039A2
+	0x0F120200, // 700039A4
+	0x0F12F000, // 700039A6
+	0x0F12FA0B, // 700039A8
+	0x0F120400, // 700039AA
+	0x0F120C00, // 700039AC
+	0x0F122401, // 700039AE
+	0x0F120364, // 700039B0
+	0x0F1242A0, // 700039B2
+	0x0F12D200, // 700039B4
+	0x0F120004, // 700039B6
+	0x0F124A27, // 700039B8
+	0x0F120020, // 700039BA
+	0x0F12327E, // 700039BC
+	0x0F121F91, // 700039BE
+	0x0F122303, // 700039C0
+	0x0F12F000, // 700039C2
+	0x0F12FA03, // 700039C4
+	0x0F120405, // 700039C6
+	0x0F120C2D, // 700039C8
+	0x0F124A23, // 700039CA
+	0x0F120020, // 700039CC
+	0x0F12325A, // 700039CE
+	0x0F120011, // 700039D0
+	0x0F12390A, // 700039D2
+	0x0F122305, // 700039D4
+	0x0F12F000, // 700039D6
+	0x0F12F9F9, // 700039D8
+	0x0F12491F, // 700039DA
+	0x0F1264C8, // 700039DC
+	0x0F12491F, // 700039DE
+	0x0F124E21, // 700039E0
+	0x0F1288C8, // 700039E2
+	0x0F122701, // 700039E4
+	0x0F122800, // 700039E6
+	0x0F12D009, // 700039E8
+	0x0F124C23, // 700039EA
+	0x0F1238FF, // 700039EC
+	0x0F121E40, // 700039EE
+	0x0F12D00A, // 700039F0
+	0x0F122804, // 700039F2
+	0x0F12D042, // 700039F4
+	0x0F122806, // 700039F6
+	0x0F12D101, // 700039F8
+	0x0F122000, // 700039FA
+	0x0F1280C8, // 700039FC
+	0x0F1282B7, // 700039FE
+	0x0F122001, // 70003A00
+	0x0F12F000, // 70003A02
+	0x0F12F9FB, // 70003A04
+	0x0F12E6CB, // 70003A06
+	0x0F12000D, // 70003A08
+	0x0F12724F, // 70003A0A
+	0x0F122001, // 70003A0C
+	0x0F12F000, // 70003A0E
+	0x0F12F9FD, // 70003A10
+	0x0F12F000, // 70003A12
+	0x0F12FA03, // 70003A14
+	0x0F124910, // 70003A16
+	0x0F123148, // 70003A18
+	0x0F12C903, // 70003A1A
+	0x0F124348, // 70003A1C
+	0x0F120A00, // 70003A1E
+	0x0F126160, // 70003A20
+	0x0F1220FF, // 70003A22
+	0x0F121D40, // 70003A24
+	0x0F1280E8, // 70003A26
+	0x0F12480C, // 70003A28
+	0x0F123040, // 70003A2A
+	0x0F127707, // 70003A2C
+	0x0F12E7E6, // 70003A2E
+	0x0F123290, // 70003A30
+	0x0F127000, // 70003A32
+	0x0F123294, // 70003A34
+	0x0F127000, // 70003A36
+	0x0F1204A8, // 70003A38
+	0x0F127000, // 70003A3A
+	0x0F1215DC, // 70003A3C
+	0x0F127000, // 70003A3E
+	0x0F125000, // 70003A40
+	0x0F12D000, // 70003A42
+	0x0F121E84, // 70003A44
+	0x0F127000, // 70003A46
+	0x0F121BE4, // 70003A48
+	0x0F127000, // 70003A4A
+	0x0F122EA8, // 70003A4C
+	0x0F127000, // 70003A4E
+	0x0F1221A4, // 70003A50
+	0x0F127000, // 70003A52
+	0x0F120100, // 70003A54
+	0x0F127000, // 70003A56
+	0x0F123F48, // 70003A58
+	0x0F127000, // 70003A5A
+	0x0F1231A0, // 70003A5C
+	0x0F127000, // 70003A5E
+	0x0F1201E8, // 70003A60
+	0x0F127000, // 70003A62
+	0x0F12F2A0, // 70003A64
+	0x0F12D000, // 70003A66
+	0x0F122A44, // 70003A68
+	0x0F127000, // 70003A6A
+	0x0F12F400, // 70003A6C
+	0x0F12D000, // 70003A6E
+	0x0F122024, // 70003A70
+	0x0F127000, // 70003A72
+	0x0F121650, // 70003A74
+	0x0F127000, // 70003A76
+	0x0F122A64, // 70003A78
+	0x0F127000, // 70003A7A
+	0x0F124982, // 70003A7C
+	0x0F12724F, // 70003A7E
+	0x0F1220FF, // 70003A80
+	0x0F121DC0, // 70003A82
+	0x0F1280C8, // 70003A84
+	0x0F12F000, // 70003A86
+	0x0F12F9D1, // 70003A88
+	0x0F124980, // 70003A8A
+	0x0F126ACA, // 70003A8C
+	0x0F12604A, // 70003A8E
+	0x0F122800, // 70003A90
+	0x0F12D006, // 70003A92
+	0x0F12436A, // 70003A94
+	0x0F120001, // 70003A96
+	0x0F120010, // 70003A98
+	0x0F12F000, // 70003A9A
+	0x0F12F991, // 70003A9C
+	0x0F126160, // 70003A9E
+	0x0F12E001, // 70003AA0
+	0x0F12436A, // 70003AA2
+	0x0F126162, // 70003AA4
+	0x0F128BF0, // 70003AA6
+	0x0F122800, // 70003AA8
+	0x0F12D001, // 70003AAA
+	0x0F12F7FF, // 70003AAC
+	0x0F12FF33, // 70003AAE
+	0x0F122000, // 70003AB0
+	0x0F12F000, // 70003AB2
+	0x0F12F9AB, // 70003AB4
+	0x0F124974, // 70003AB6
+	0x0F1220FF, // 70003AB8
+	0x0F121DC0, // 70003ABA
+	0x0F1280C8, // 70003ABC
+	0x0F12E79E, // 70003ABE
+	0x0F12B510, // 70003AC0
+	0x0F12F000, // 70003AC2
+	0x0F12F9BB, // 70003AC4
+	0x0F124870, // 70003AC6
+	0x0F1288C0, // 70003AC8
+	0x0F121FC1, // 70003ACA
+	0x0F1239FD, // 70003ACC
+	0x0F12D103, // 70003ACE
+	0x0F12496F, // 70003AD0
+	0x0F1220FF, // 70003AD2
+	0x0F121C40, // 70003AD4
+	0x0F128048, // 70003AD6
+	0x0F12E605, // 70003AD8
+	0x0F12B5F8, // 70003ADA
+	0x0F122400, // 70003ADC
+	0x0F124D6D, // 70003ADE
+	0x0F12486D, // 70003AE0
+	0x0F12210E, // 70003AE2
+	0x0F128041, // 70003AE4
+	0x0F122101, // 70003AE6
+	0x0F128001, // 70003AE8
+	0x0F12F000, // 70003AEA
+	0x0F12F9AF, // 70003AEC
+	0x0F12486B, // 70003AEE
+	0x0F128840, // 70003AF0
+	0x0F12F000, // 70003AF2
+	0x0F12F9B3, // 70003AF4
+	0x0F124E6A, // 70003AF6
+	0x0F12270D, // 70003AF8
+	0x0F12073F, // 70003AFA
+	0x0F1219E8, // 70003AFC
+	0x0F128803, // 70003AFE
+	0x0F1200E2, // 70003B00
+	0x0F121991, // 70003B02
+	0x0F12804B, // 70003B04
+	0x0F128843, // 70003B06
+	0x0F1252B3, // 70003B08
+	0x0F128882, // 70003B0A
+	0x0F1280CA, // 70003B0C
+	0x0F1288C0, // 70003B0E
+	0x0F128088, // 70003B10
+	0x0F123508, // 70003B12
+	0x0F12042D, // 70003B14
+	0x0F120C2D, // 70003B16
+	0x0F121C64, // 70003B18
+	0x0F120424, // 70003B1A
+	0x0F120C24, // 70003B1C
+	0x0F122C07, // 70003B1E
+	0x0F12D3EC, // 70003B20
+	0x0F12E63D, // 70003B22
+	0x0F12B5F0, // 70003B24
+	0x0F12B085, // 70003B26
+	0x0F126801, // 70003B28
+	0x0F129103, // 70003B2A
+	0x0F126881, // 70003B2C
+	0x0F12040A, // 70003B2E
+	0x0F120C12, // 70003B30
+	0x0F12495C, // 70003B32
+	0x0F128B89, // 70003B34
+	0x0F122900, // 70003B36
+	0x0F12D001, // 70003B38
+	0x0F120011, // 70003B3A
+	0x0F12E000, // 70003B3C
+	0x0F122100, // 70003B3E
+	0x0F129102, // 70003B40
+	0x0F126840, // 70003B42
+	0x0F120401, // 70003B44
+	0x0F129803, // 70003B46
+	0x0F120C09, // 70003B48
+	0x0F12F000, // 70003B4A
+	0x0F12F98F, // 70003B4C
+	0x0F124854, // 70003B4E
+	0x0F123080, // 70003B50
+	0x0F128900, // 70003B52
+	0x0F122800, // 70003B54
+	0x0F12D039, // 70003B56
+	0x0F122100, // 70003B58
+	0x0F124854, // 70003B5A
+	0x0F124D52, // 70003B5C
+	0x0F124684, // 70003B5E
+	0x0F124B53, // 70003B60
+	0x0F124C4F, // 70003B62
+	0x0F1288DA, // 70003B64
+	0x0F120048, // 70003B66
+	0x0F1200D7, // 70003B68
+	0x0F12193E, // 70003B6A
+	0x0F12197F, // 70003B6C
+	0x0F12183F, // 70003B6E
+	0x0F125A36, // 70003B70
+	0x0F128AFF, // 70003B72
+	0x0F12437E, // 70003B74
+	0x0F1200B6, // 70003B76
+	0x0F120C37, // 70003B78
+	0x0F121906, // 70003B7A
+	0x0F123680, // 70003B7C
+	0x0F128177, // 70003B7E
+	0x0F121C52, // 70003B80
+	0x0F1200D2, // 70003B82
+	0x0F121914, // 70003B84
+	0x0F121952, // 70003B86
+	0x0F121812, // 70003B88
+	0x0F125A24, // 70003B8A
+	0x0F128AD2, // 70003B8C
+	0x0F124354, // 70003B8E
+	0x0F1200A2, // 70003B90
+	0x0F120C12, // 70003B92
+	0x0F128272, // 70003B94
+	0x0F12891C, // 70003B96
+	0x0F12895B, // 70003B98
+	0x0F124367, // 70003B9A
+	0x0F12435A, // 70003B9C
+	0x0F121943, // 70003B9E
+	0x0F123340, // 70003BA0
+	0x0F1289DB, // 70003BA2
+	0x0F129C02, // 70003BA4
+	0x0F1218BA, // 70003BA6
+	0x0F124363, // 70003BA8
+	0x0F1218D2, // 70003BAA
+	0x0F120212, // 70003BAC
+	0x0F120C12, // 70003BAE
+	0x0F12466B, // 70003BB0
+	0x0F12521A, // 70003BB2
+	0x0F124663, // 70003BB4
+	0x0F127DDB, // 70003BB6
+	0x0F12435A, // 70003BB8
+	0x0F129B03, // 70003BBA
+	0x0F120252, // 70003BBC
+	0x0F120C12, // 70003BBE
+	0x0F12521A, // 70003BC0
+	0x0F121C49, // 70003BC2
+	0x0F120409, // 70003BC4
+	0x0F120C09, // 70003BC6
+	0x0F122904, // 70003BC8
+	0x0F12D3C9, // 70003BCA
+	0x0F12B005, // 70003BCC
+	0x0F12BCF0, // 70003BCE
+	0x0F12BC08, // 70003BD0
+	0x0F124718, // 70003BD2
+	0x0F12B510, // 70003BD4
+	0x0F12F7FF, // 70003BD6
+	0x0F12FF80, // 70003BD8
+	0x0F12F000, // 70003BDA
+	0x0F12F94F, // 70003BDC
+	0x0F12E582, // 70003BDE
+	0x0F12B570, // 70003BE0
+	0x0F126804, // 70003BE2
+	0x0F12F000, // 70003BE4
+	0x0F12F952, // 70003BE6
+	0x0F124D32, // 70003BE8
+	0x0F128C29, // 70003BEA
+	0x0F121A40, // 70003BEC
+	0x0F1242A0, // 70003BEE
+	0x0F12D901, // 70003BF0
+	0x0F120020, // 70003BF2
+	0x0F12E003, // 70003BF4
+	0x0F12F000, // 70003BF6
+	0x0F12F949, // 70003BF8
+	0x0F128C29, // 70003BFA
+	0x0F121A40, // 70003BFC
+	0x0F126268, // 70003BFE
+	0x0F12F000, // 70003C00
+	0x0F12F94C, // 70003C02
+	0x0F1262A8, // 70003C04
+	0x0F12F000, // 70003C06
+	0x0F12F951, // 70003C08
+	0x0F126328, // 70003C0A
+	0x0F128869, // 70003C0C
+	0x0F122900, // 70003C0E
+	0x0F12D000, // 70003C10
+	0x0F1262A8, // 70003C12
+	0x0F124828, // 70003C14
+	0x0F126B00, // 70003C16
+	0x0F128C00, // 70003C18
+	0x0F122800, // 70003C1A
+	0x0F12D11B, // 70003C1C
+	0x0F126AA8, // 70003C1E
+	0x0F12F000, // 70003C20
+	0x0F12F94C, // 70003C22
+	0x0F1261E8, // 70003C24
+	0x0F124A1E, // 70003C26
+	0x0F123280, // 70003C28
+	0x0F128B91, // 70003C2A
+	0x0F122900, // 70003C2C
+	0x0F12D00B, // 70003C2E
+	0x0F120011, // 70003C30
+	0x0F123120, // 70003C32
+	0x0F128809, // 70003C34
+	0x0F124288, // 70003C36
+	0x0F12D907, // 70003C38
+	0x0F1261E9, // 70003C3A
+	0x0F128C28, // 70003C3C
+	0x0F121A08, // 70003C3E
+	0x0F1262A8, // 70003C40
+	0x0F12F000, // 70003C42
+	0x0F12F92B, // 70003C44
+	0x0F1262A8, // 70003C46
+	0x0F12E502, // 70003C48
+	0x0F128BD1, // 70003C4A
+	0x0F124288, // 70003C4C
+	0x0F12D800, // 70003C4E
+	0x0F120008, // 70003C50
+	0x0F1261E8, // 70003C52
+	0x0F12E4FC, // 70003C54
+	0x0F12F000, // 70003C56
+	0x0F12F919, // 70003C58
+	0x0F1261E8, // 70003C5A
+	0x0F12E4F8, // 70003C5C
+	0x0F12B510, // 70003C5E
+	0x0F12F000, // 70003C60
+	0x0F12F934, // 70003C62
+	0x0F12480E, // 70003C64
+	0x0F1230A0, // 70003C66
+	0x0F128841, // 70003C68
+	0x0F122900, // 70003C6A
+	0x0F12D007, // 70003C6C
+	0x0F124A07, // 70003C6E
+	0x0F123280, // 70003C70
+	0x0F126953, // 70003C72
+	0x0F124A11, // 70003C74
+	0x0F12428B, // 70003C76
+	0x0F12D202, // 70003C78
+	0x0F128880, // 70003C7A
+	0x0F1281D0, // 70003C7C
+	0x0F12E532, // 70003C7E
+	0x0F1288C0, // 70003C80
+	0x0F1281D0, // 70003C82
+	0x0F12E52F, // 70003C84
+	0x0F120000, // 70003C86
+	0x0F1231A0, // 70003C88
+	0x0F127000, // 70003C8A
+	0x0F1229E4, // 70003C8C
+	0x0F127000, // 70003C8E
+	0x0F12C100, // 70003C90
+	0x0F12D000, // 70003C92
+	0x0F12A006, // 70003C94
+	0x0F120000, // 70003C96
+	0x0F12A000, // 70003C98
+	0x0F12D000, // 70003C9A
+	0x0F12064C, // 70003C9C
+	0x0F127000, // 70003C9E
+	0x0F123F48, // 70003CA0
+	0x0F127000, // 70003CA2
+	0x0F1207C4, // 70003CA4
+	0x0F127000, // 70003CA6
+	0x0F1207E8, // 70003CA8
+	0x0F127000, // 70003CAA
+	0x0F122B24, // 70003CAC
+	0x0F127000, // 70003CAE
+	0x0F121FA0, // 70003CB0
+	0x0F127000, // 70003CB2
+	0x0F121E3C, // 70003CB4
+	0x0F127000, // 70003CB6
+	0x0F1221A4, // 70003CB8
+	0x0F127000, // 70003CBA
+	0x0F12E200, // 70003CBC
+	0x0F12D000, // 70003CBE
+	0x0F124778, // 70003CC0
+	0x0F1246C0, // 70003CC2
+	0x0F12C000, // 70003CC4
+	0x0F12E59F, // 70003CC6
+	0x0F12FF1C, // 70003CC8
+	0x0F12E12F, // 70003CCA
+	0x0F121F63, // 70003CCC
+	0x0F120001, // 70003CCE
+	0x0F124778, // 70003CD0
+	0x0F1246C0, // 70003CD2
+	0x0F12C000, // 70003CD4
+	0x0F12E59F, // 70003CD6
+	0x0F12FF1C, // 70003CD8
+	0x0F12E12F, // 70003CDA
+	0x0F121EDF, // 70003CDC
+	0x0F120001, // 70003CDE
+	0x0F124778, // 70003CE0
+	0x0F1246C0, // 70003CE2
+	0x0F12C000, // 70003CE4
+	0x0F12E59F, // 70003CE6
+	0x0F12FF1C, // 70003CE8
+	0x0F12E12F, // 70003CEA
+	0x0F12495F, // 70003CEC
+	0x0F120000, // 70003CEE
+	0x0F124778, // 70003CF0
+	0x0F1246C0, // 70003CF2
+	0x0F12C000, // 70003CF4
+	0x0F12E59F, // 70003CF6
+	0x0F12FF1C, // 70003CF8
+	0x0F12E12F, // 70003CFA
+	0x0F12E403, // 70003CFC
+	0x0F120000, // 70003CFE
+	0x0F124778, // 70003D00
+	0x0F1246C0, // 70003D02
+	0x0F12C000, // 70003D04
+	0x0F12E59F, // 70003D06
+	0x0F12FF1C, // 70003D08
+	0x0F12E12F, // 70003D0A
+	0x0F1224B3, // 70003D0C
+	0x0F120001, // 70003D0E
+	0x0F124778, // 70003D10
+	0x0F1246C0, // 70003D12
+	0x0F12C000, // 70003D14
+	0x0F12E59F, // 70003D16
+	0x0F12FF1C, // 70003D18
+	0x0F12E12F, // 70003D1A
+	0x0F12EECD, // 70003D1C
+	0x0F120000, // 70003D1E
+	0x0F124778, // 70003D20
+	0x0F1246C0, // 70003D22
+	0x0F12C000, // 70003D24
+	0x0F12E59F, // 70003D26
+	0x0F12FF1C, // 70003D28
+	0x0F12E12F, // 70003D2A
+	0x0F12F049, // 70003D2C
+	0x0F120000, // 70003D2E
+	0x0F124778, // 70003D30
+	0x0F1246C0, // 70003D32
+	0x0F12C000, // 70003D34
+	0x0F12E59F, // 70003D36
+	0x0F12FF1C, // 70003D38
+	0x0F12E12F, // 70003D3A
+	0x0F1212DF, // 70003D3C
+	0x0F120000, // 70003D3E
+	0x0F124778, // 70003D40
+	0x0F1246C0, // 70003D42
+	0x0F12C000, // 70003D44
+	0x0F12E59F, // 70003D46
+	0x0F12FF1C, // 70003D48
+	0x0F12E12F, // 70003D4A
+	0x0F12F05B, // 70003D4C
+	0x0F120000, // 70003D4E
+	0x0F124778, // 70003D50
+	0x0F1246C0, // 70003D52
+	0x0F12C000, // 70003D54
+	0x0F12E59F, // 70003D56
+	0x0F12FF1C, // 70003D58
+	0x0F12E12F, // 70003D5A
+	0x0F12F07B, // 70003D5C
+	0x0F120000, // 70003D5E
+	0x0F124778, // 70003D60
+	0x0F1246C0, // 70003D62
+	0x0F12C000, // 70003D64
+	0x0F12E59F, // 70003D66
+	0x0F12FF1C, // 70003D68
+	0x0F12E12F, // 70003D6A
+	0x0F12FE6D, // 70003D6C
+	0x0F120000, // 70003D6E
+	0x0F124778, // 70003D70
+	0x0F1246C0, // 70003D72
+	0x0F12C000, // 70003D74
+	0x0F12E59F, // 70003D76
+	0x0F12FF1C, // 70003D78
+	0x0F12E12F, // 70003D7A
+	0x0F123295, // 70003D7C
+	0x0F120000, // 70003D7E
+	0x0F124778, // 70003D80
+	0x0F1246C0, // 70003D82
+	0x0F12C000, // 70003D84
+	0x0F12E59F, // 70003D86
+	0x0F12FF1C, // 70003D88
+	0x0F12E12F, // 70003D8A
+	0x0F12234F, // 70003D8C
+	0x0F120000, // 70003D8E
+	0x0F124778, // 70003D90
+	0x0F1246C0, // 70003D92
+	0x0F12C000, // 70003D94
+	0x0F12E59F, // 70003D96
+	0x0F12FF1C, // 70003D98
+	0x0F12E12F, // 70003D9A
+	0x0F124521, // 70003D9C
+	0x0F120000, // 70003D9E
+	0x0F124778, // 70003DA0
+	0x0F1246C0, // 70003DA2
+	0x0F12C000, // 70003DA4
+	0x0F12E59F, // 70003DA6
+	0x0F12FF1C, // 70003DA8
+	0x0F12E12F, // 70003DAA
+	0x0F127C0D, // 70003DAC
+	0x0F120000, // 70003DAE
+	0x0F124778, // 70003DB0
+	0x0F1246C0, // 70003DB2
+	0x0F12C000, // 70003DB4
+	0x0F12E59F, // 70003DB6
+	0x0F12FF1C, // 70003DB8
+	0x0F12E12F, // 70003DBA
+	0x0F127C2B, // 70003DBC
+	0x0F120000, // 70003DBE
+	0x0F124778, // 70003DC0
+	0x0F1246C0, // 70003DC2
+	0x0F12F004, // 70003DC4
+	0x0F12E51F, // 70003DC6
+	0x0F1224C4, // 70003DC8
+	0x0F120001, // 70003DCA
+	0x0F124778, // 70003DCC
+	0x0F1246C0, // 70003DCE
+	0x0F12C000, // 70003DD0
+	0x0F12E59F, // 70003DD2
+	0x0F12FF1C, // 70003DD4
+	0x0F12E12F, // 70003DD6
+	0x0F123183, // 70003DD8
+	0x0F120000, // 70003DDA
+	0x0F124778, // 70003DDC
+	0x0F1246C0, // 70003DDE
+	0x0F12C000, // 70003DE0
+	0x0F12E59F, // 70003DE2
+	0x0F12FF1C, // 70003DE4
+	0x0F12E12F, // 70003DE6
+	0x0F12302F, // 70003DE8
+	0x0F120000, // 70003DEA
+	0x0F124778, // 70003DEC
+	0x0F1246C0, // 70003DEE
+	0x0F12C000, // 70003DF0
+	0x0F12E59F, // 70003DF2
+	0x0F12FF1C, // 70003DF4
+	0x0F12E12F, // 70003DF6
+	0x0F12EF07, // 70003DF8
+	0x0F120000, // 70003DFA
+	0x0F124778, // 70003DFC
+	0x0F1246C0, // 70003DFE
+	0x0F12C000, // 70003E00
+	0x0F12E59F, // 70003E02
+	0x0F12FF1C, // 70003E04
+	0x0F12E12F, // 70003E06
+	0x0F1248FB, // 70003E08
+	0x0F120000, // 70003E0A
+	0x0F124778, // 70003E0C
+	0x0F1246C0, // 70003E0E
+	0x0F12C000, // 70003E10
+	0x0F12E59F, // 70003E12
+	0x0F12FF1C, // 70003E14
+	0x0F12E12F, // 70003E16
+	0x0F12F0B1, // 70003E18
+	0x0F120000, // 70003E1A
+	0x0F124778, // 70003E1C
+	0x0F1246C0, // 70003E1E
+	0x0F12C000, // 70003E20
+	0x0F12E59F, // 70003E22
+	0x0F12FF1C, // 70003E24
+	0x0F12E12F, // 70003E26
+	0x0F12EEDF, // 70003E28
+	0x0F120000, // 70003E2A
+	0x0F124778, // 70003E2C
+	0x0F1246C0, // 70003E2E
+	0x0F12C000, // 70003E30
+	0x0F12E59F, // 70003E32
+	0x0F12FF1C, // 70003E34
+	0x0F12E12F, // 70003E36
+	0x0F12AEF1, // 70003E38
+	0x0F120000, // 70003E3A
+	0x0F124778, // 70003E3C
+	0x0F1246C0, // 70003E3E
+	0x0F12C000, // 70003E40
+	0x0F12E59F, // 70003E42
+	0x0F12FF1C, // 70003E44
+	0x0F12E12F, // 70003E46
+	0x0F1202EB, // 70003E48
+	0x0F120001, // 70003E4A
+	0x0F124778, // 70003E4C
+	0x0F1246C0, // 70003E4E
+	0x0F12C000, // 70003E50
+	0x0F12E59F, // 70003E52
+	0x0F12FF1C, // 70003E54
+	0x0F12E12F, // 70003E56
+	0x0F12FD21, // 70003E58
+	0x0F120000, // 70003E5A
+	0x0F124778, // 70003E5C
+	0x0F1246C0, // 70003E5E
+	0x0F12C000, // 70003E60
+	0x0F12E59F, // 70003E62
+	0x0F12FF1C, // 70003E64
+	0x0F12E12F, // 70003E66
+	0x0F12FDAF, // 70003E68
+	0x0F120000, // 70003E6A
+	0x0F124778, // 70003E6C
+	0x0F1246C0, // 70003E6E
+	0x0F12C000, // 70003E70
+	0x0F12E59F, // 70003E72
+	0x0F12FF1C, // 70003E74
+	0x0F12E12F, // 70003E76
+	0x0F125027, // 70003E78
+	0x0F120000, // 70003E7A
+	0x0F124778, // 70003E7C
+	0x0F1246C0, // 70003E7E
+	0x0F12C000, // 70003E80
+	0x0F12E59F, // 70003E82
+	0x0F12FF1C, // 70003E84
+	0x0F12E12F, // 70003E86
+	0x0F1204C9, // 70003E88
+	0x0F120000, // 70003E8A
+	0x0F124778, // 70003E8C
+	0x0F1246C0, // 70003E8E
+	0x0F12C000, // 70003E90
+	0x0F12E59F, // 70003E92
+	0x0F12FF1C, // 70003E94
+	0x0F12E12F, // 70003E96
+	0x0F1239DF, // 70003E98
+	0x0F120000, // 70003E9A
+	0x0F124778, // 70003E9C
+	0x0F1246C0, // 70003E9E
+	0x0F12C000, // 70003EA0
+	0x0F12E59F, // 70003EA2
+	0x0F12FF1C, // 70003EA4
+	0x0F12E12F, // 70003EA6
+	0x0F126177, // 70003EA8
+	0x0F120000, // 70003EAA
+	0x0F124778, // 70003EAC
+	0x0F1246C0, // 70003EAE
+	0x0F12C000, // 70003EB0
+	0x0F12E59F, // 70003EB2
+	0x0F12FF1C, // 70003EB4
+	0x0F12E12F, // 70003EB6
+	0x0F12424F, // 70003EB8
+	0x0F120000, // 70003EBA
+	0x0F124778, // 70003EBC
+	0x0F1246C0, // 70003EBE
+	0x0F12C000, // 70003EC0
+	0x0F12E59F, // 70003EC2
+	0x0F12FF1C, // 70003EC4
+	0x0F12E12F, // 70003EC6
+	0x0F123F0D, // 70003EC8
+	0x0F120000, // 70003ECA
+	0x0F124778, // 70003ECC
+	0x0F1246C0, // 70003ECE
+	0x0F12C000, // 70003ED0
+	0x0F12E59F, // 70003ED2
+	0x0F12FF1C, // 70003ED4
+	0x0F12E12F, // 70003ED6
+	0x0F1202B9, // 70003ED8
+	0x0F120001, // 70003EDA
+	// End of Patch Data(Last : 70003EDAh)
+	// Total Size 2480 (09B0)
+	// Addr : 352C , Size : 2478(9AEh)
+
+	//	TNP_USER_MBCV_CONTROL
+	//	TNP_FLS_SEC_CONFIG
+	//	TNP_SINGLE_FRAME_CAPTURE
+	//	TNP_CAPTURE_DONE_INFO
+	//	TNP_5CC_SENSOR_TUNE
+	//	TNP_GAS_ALPHA_OTP
+	//	TNP_FR_ACCURATE_DYNAMIC
+	//	TNP_ADLC_TUNE
+
+	0x10000001,
+
+	0x0028D000,
+	0x002A0070,
+	0x0F120007, // clks_src_gf_force_enable
+
+
+	//MBCV Control
+	0x00287000,
+	0x002A04B4,
+	0x0F120064,
+
+	// AFIT by Normalized Brightness Tuning parameter
+	0x00287000,
+	0x002A3302,
+	0x0F120001, // on/off AFIT by NB option
+
+	0x0F120005, //0005                 // NormBR[0]
+	0x0F120066, //00C8                 // NormBR[1]
+	0x0F1200C8, //00F4                 // NormBR[2]
+	0x0F120320, //0320                 // NormBR[3]
+	0x0F120375, //0375                 // NormBR[4]
+
+
+
+	// Flash
+	0x002A3F82,
+	0x0F120000,	                  // TNP_Regs_PreflashStart
+	0x0F120000,	                  // TNP_Regs_PreflashEnd
+	0x0F120260,	                  // TNP_Regs_PreWP_r
+	0x0F120240, // TNP_Regs_PreWP_b
+
+	0x002A3F98,	                  // BR Tuning
+	0x0F120100,	                  // TNP_Regs_BrRatioIn_0_
+	0x0F120150,
+	0x0F120200,
+	0x0F120300,
+	0x0F120400,
+
+	0x0F120100,	                  // TNP_Regs_BrRatioOut_0_
+	0x0F1200A0,
+	0x0F120080,
+	0x0F120040,
+	0x0F120020,
+
+	0x0F120030,	                  // WP Tuning
+	0x0F120040,	                  // TNP_Regs_WPThresTbl_0_
+	0x0F120048,
+	0x0F120050,
+	0x0F120060,
+
+	0x0F120100,	                  // TNP_Regs_WPWeightTbl_0_
+	0x0F1200C0,
+	0x0F120080,
+	0x0F12000A,
+	0x0F120000,
+
+	0x0F120120,	                  // T_BR tune
+	0x0F120150,	                  // TNP_Regs_FlBRIn_0_
+	0x0F120200,
+
+	0x0F12003C,	                  //TNP_Regs_FlBRInOut_0_
+	0x0F12003B,
+	0x0F12002C,
+
+	0x002A0430,	                  //REG_TC_FLS_Mode
+	0x0F120002,
+	0x002A3F80,	                  //TNP_Regs_FastFlashAlg
+	0x0F120000,
+
+	0x002A165E,
+	0x0F120240, //0244 0258 AWB R point                            //0258 0245 0258
+	0x0F120244, //024D 0220 AWB B point                            //0220 0245 0245
+
+
+	//                           //                           //                           //           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           ///
+	// Analog & APS settings                           //                           //           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           ///
+	// This register is for FACTORY ONLY. If you change it without prior notification
+	// YOU are RESPONSIBLE for the FAILURE that will happen in the future                                        //
+	//                           //                           //                           //           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           //
+	//                           //                           //                           //                           //                           ///
+
+	//========================================================================================
+	// 5CC EVT0 analog register setting
+	// '10.07.14. Initial Draft
+	// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+	// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+	// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+	//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+	// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshad
+	//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+	//========================================================================================
+	//============================= Analog & APS Control =====================================
+	0x0028D000,
+	0x002AF2AC,
+	0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+	0x002AF400,
+	0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+	0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+	0x002AF40A,
+	0x0F120054, // adc_sat[7:0]=84d (500mV)
+	0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+	0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+	0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+	0x0F1200A4, // rmp_init[7:0]
+
+	0x002AF416,
+	0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+	0x002AF41E,
+	0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+	0x002AF422,
+	0x0F120005, // pix_bias[3:0]
+
+	0x002AF426,
+	0x0F1200D4, // clp_lvl[7:0]
+
+	0x002AF42A,
+	0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clam
+
+	0x002AF42E,
+	0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_re
+
+	0x002AF434,
+	0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+	0x0F120004, // reg_tune_pix[7:0]
+	0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+	0x0F120001, // reg_tune_rg[7:0] (2.83V)
+	0x0F120004, // reg_tune_ntg[7:0]
+
+	0x002AF446,
+	0x0F120000, // blst_en_cintr[15:0]
+
+	0x002AF466,
+	0x0F120000, // srx_en[0]
+
+	0x002A0054,
+	0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+	0x0F128888, // div_dbr[7:4]
+	0x002AF132,
+	0x0F124006,	         //ki 0413                   // tgr_frame_decription 4
+	0x002AF142,
+	0x0F120000,	         //ki 0413                   // tgr_frame_decription 4
+
+	0x002AF152,
+	0x0F120206, // tgr_frame_decription 7
+	0x002AF1A2,
+	0x0F120200, // tgr_frame_params_descriptor_3
+	0x002AF1B2,
+	0x0F120202, // tgr_frame_params_descriptor_6
+	//==========================================================================================
+
+	//============================= Line-ADLC Tuning ===========================================
+	0x002AE412,
+	0x0F120008, // adlc_tune_offset_gr[7:0]
+	0x0F120008, // adlc_tune_offset_r[7:0]
+	0x0F120010, // adlc_tune_offset_b[7:0]
+	0x0F120010, // adlc_tune_offset_gb[7:0]
+	0x002AE42E,
+	0x0F120004, // adlc_qec[2:0]
+	//==========================================================================================
+
+	//===================================================================
+	// AWB white locus setting - Have to be written after TnP
+	//===================================================================
+	0x00287000,
+	0x002A1014,
+	0x0F12012C,	         //0132                   //0138                  //awbb_IntcR
+	0x0F12010B,	         //010A                   //011C                  //awbb_IntcB
+
+	//===================================================================
+	// AF
+	//===================================================================
+	//1. AF interface setting
+	0x002A01A2,
+	0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType                          // VCM_I2C actuator
+	0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1                         // No PWM
+	0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+	0x0F120041, //REG_TC_IPRM_CM_Init_GpioConfig1                          // Use GPIO_4 for ena
+	0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+	0x0F122A0C, //REG_TC_IPRM_CM_Init_Mi2cBits                          // Use GPIO_5 for SCL GP
+	0x0F120190, //REG_TC_IPRM_CM_Init_Mi2cRateKhz                          // MI2C Speed : 400KH
+
+	//2. AF window setting
+	0x002A022C,
+	0x0F120100, //REG_TC_AF_FstWinStartX
+	0x0F1200E3, //REG_TC_AF_FstWinStartY
+	0x0F120200, //REG_TC_AF_FstWinSizeX
+	0x0F120238, //REG_TC_AF_FstWinSizeY
+	0x0F12018C, //REG_TC_AF_ScndWinStartX
+	0x0F120166, //REG_TC_AF_ScndWinStartY
+	0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+	0x0F120132, //REG_TC_AF_ScndWinSizeY
+	0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+	//3. AF Fine Search Settings
+	0x002A063A,
+	0x0F1200C0, //#skl_af_StatOvlpExpFactor
+	0x002A064A,
+	0x0F120000, //0000                            //#skl_af_bAfStatOff
+	0x002A1488,
+	0x0F120000, //#af_search_usAeStable
+	0x002A1494,
+	0x0F121000, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+	0x002A149E,
+	0x0F120002, //#af_search_usFinePeakCount
+	0x0F120000, //#af_search_usFineMaxScale
+	0x002A142C,
+	0x0F120601, //#af_pos_usFineStepNumSize
+	0x002A14A2,
+	0x0F120000, //#af_search_usCapturePolicy 0000 Shutter_Priority_Current
+
+	//4.  AF Peak Threshold Setting
+	0x002A1498,
+	0x0F120001, //#af_search_usMinPeakSamples
+	0x002A148A,
+	0x0F1200F0, //#af_search_usPeakThr  for
+	0x0F120090, //#af_search_usPeakThrLow
+
+	//5.  AF Default Position
+	0x002A1420,
+	0x0F120000, //#af_pos_usHomePos
+	0x0F124040, //#af_pos_usLowConfPos
+
+	//6. AF statistics
+	0x002A14B4,
+	0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+	0x002A14C0,
+	0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+	0x0F120320, //#af_search_usConfThr_11_
+	0x002A14F4,
+	0x0F120030, //#af_stat_usMinStatVal
+	0x002A1514,
+	0x0F120060, //#af_scene_usSceneLowNormBrThr
+	// AF Scene Settings
+	0x002A151E,
+	0x0F120003, //#af_scene_usSaturatedScene
+
+
+
+	//7. AF Lens Position Table Settings
+	0x002A1434,
+	0x0F120011, //#af_pos_usTableLastInd 10h_ 1h = 17 Steps
+
+	0x0F120030, //#af_pos_usTable_0_  48
+	0x0F120034, //#af_pos_usTable_1_  51
+	0x0F120038, //#af_pos_usTable_2_  54
+	0x0F12003C, //#af_pos_usTable_3_  57
+	0x0F120040, /* #af_pos_usTable_4_ 61 */
+	0x0F120044, //#af_pos_usTable_5_  65
+	0x0F120048, //#af_pos_usTable_6_  69
+	0x0F12004C, //#af_pos_usTable_7_  73
+	0x0F120050, //#af_pos_usTable_8_  78
+	0x0F120054, //#af_pos_usTable_9_  83
+	0x0F120058, //#af_pos_usTable_10_ 89
+	0x0F12005C, //#af_pos_usTable_11_ 89
+	0x0F120060, //#af_pos_usTable_12_ 89
+	0x0F120064, //#af_pos_usTable_13_ 89
+	0x0F120068, //#af_pos_usTable_14_ 89
+	0x0F12006C, //#af_pos_usTable_15_ 89
+	0x0F120070, //#af_pos_usTable_16_ 89
+	0x0F120074, //#af_pos_usTable_17_ 89
+
+
+	//8. Continuous AF setting
+	//8-1 Continuous AF timing
+	0x002A152A,
+	0x0F120040, //40 //30  //af_refocus_usFlFrames_ lens movement each 64frame
+	0x002A154A,
+	0x0F120010, //18 //0C  //af_scene_usResetNWaitFr (4 frame) lens movement each 64frame
+
+	//8-2 Continuous AF sensitivity
+	0x002A154C, //
+	0x0F120000, //0010
+	0x0F120000, //03FF
+	0x0F120000, //0000
+
+
+	0x002A1526, //Continuous AF sensitivity tuning
+	0x0F128080, //
+	0x0F12A0A0, //
+
+
+	//8-3 Continuos AF, lens movement
+	0x002A1424,
+	0x0F126060, // af_pos_usMiddlePos  MSB_macro LSB_ normal lens moving direction lens À̵¿¹æÇâ
+	0x002A148E, // usPeakFrontThr
+	0x0F120002,
+
+
+	//9. VCM AF driver with PWM/I2C
+	0x002A1558,
+	0x0F128000, //#afd_usParam[0]  I2C power down command
+	0x0F120006, //#afd_usParam[1]  Position Right Shift
+	0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+	0x0F1203E8, //#afd_usParam[3]  PWM Period
+	0x0F120000, //#afd_usParam[4]  PWM Divider
+	0x0F120200, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+	0x0F120004, //#afd_usParam[6]  SlowMotion Threshold
+	0x0F120100, //#afd_usParam[7]  Signal Shaping
+	0x0F120040, //#afd_usParam[8]  Signal Shaping level
+	0x0F120080, //#afd_usParam[9]  Signal Shaping level
+	0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+	0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+	0x002A0224,
+	0x0F120003, //REG_TC_AF_AfCmd                  //Initialize AF subsystem (AF driver AF algor
+
+	//===================================================================
+	// Flash setting
+	//===================================================================
+	0x002A018C,
+	0x0F120001, //REG_TC_IPRM_AuxConfig                  // bit[0] : Flash is in use bit[1] : Me
+	0x0F120003, //REG_TC_IPRM_AuxPolarity                  // bit[0] : Flash polarity (1 is acti
+	0x0F120003, //REG_TC_IPRM_AuxGpios                  //1-4 : Flash GPIO number If GPIO number
+
+	//===================================================================
+	// 1-H timing setting
+	//===================================================================
+	0x002A1686,
+	0x0F12005C, //senHal_uAddColsBin
+	0x0F12005C, //senHal_uAddColsNoBin
+	0x0F12085C, //senHal_uMinColsHorBin
+	0x0F12085C, //senHal_uMinColsNoHorBin
+	0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+	//===================================================================
+	// Forbidden area setting
+	//===================================================================
+	0x002A1844,
+	0x0F120000, //senHal_bSRX                  //SRX off
+
+	0x002A1680,
+	0x0F120002, //senHal_NExpLinesCheckFine                  //0004                  //extend Fo
+
+	0x002A0ED2,
+	0x0F120FA0,	                  //setot_uOnlineClocksDiv40
+
+	//===================================================================
+	// Preview subsampling mode
+	//===================================================================
+	0x002A18F8,
+	0x0F120001, //senHal_bAACActiveWait2Start
+	0x002A18F6,
+	0x0F120001, //senHal_bAlwaysAAC
+	0x002A182C,
+	0x0F120001, //senHal_bSenAAC
+	0x002A0EE4,
+	0x0F120001, //setot_bUseDigitalHbin
+	0x002A1674,
+	0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+	0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+	0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+	//===================================================================
+	// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+	//===================================================================
+	0x002A19AE,
+	0x0F12EA60, //pll_uMaxSysFreqKhz
+	0x0F127530, //pll_uMaxPVIFreq4KH
+	0x002A19C2,
+	0x0F127530, //pll_uMaxMIPIFreq4KH
+	0x002A0244,
+	0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+	0x002A0336,
+	0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+	//===================================================================
+	// Init Parameters
+	//===================================================================
+	//MCLK
+	0x002A0188,
+	0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+	0x0F120000, //REG_TC_IPRM_InClockMSBs
+	0x002A01B2,
+	0x0F120001, //REG_TC_IPRM_UseNPviClocks
+	0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+	0x002A01B8,
+	0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+	//SCLK & PCLK                    // clock set 0
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98	            4Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	            4Mhz
+
+	//SCLK & PCLK                    // clock set 1
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98	            4Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	            4Mhz
+
+	//SCLK & PCLK                    // clock set 2
+	0x0F1238A4,	                  //38A4	                  //36B0
+	0x0F1254F0,	                  //4E20	                  //3A98	            4Mhz
+	0x0F1254F8,	                  //57E4	                  //61A8	            4Mhz
+
+	0x002A1B78,
+	0x0F1238A4, //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_0__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_0__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_0__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_0__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_0__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_0__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_0__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_0__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_0__usOIFDenum
+
+	0x002A1B9C,
+	0x0F1238A4, //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_1__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_1__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_1__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_1__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_1__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_1__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_1__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_1__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_1__usOIFDenum
+
+	0x002A1BC0,
+	0x0F1238A4, //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+	0x0F120074, //  REGM_gSensorClocks_2__PLL_PllHW_M
+	0x0F120004, //  REGM_gSensorClocks_2__PLL_PllHW_P
+	0x0F120000, //  REGM_gSensorClocks_2__PLL_PllHW_S
+	0x0F120002, //  REGM_gSensorClocks_2__PLL_PllHW_VS
+	0x0F120003, //  REGM_gSensorClocks_2__PLL_PllHW_VP
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OS
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OP
+	0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+	0x0F120006, //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+	0x0F12000C, //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+	0x0F125DC0, //  REGM_gSensorClocks_2__InputClk
+	0x0F120000,
+	0x0F1254F6, //  REGM_gSensorClocks_2__usPviFreqDiv4
+	0x0F12000C, //  REGM_gSensorClocks_2__usSysDiv
+	0x0F120001, //  REGM_gSensorClocks_2__usOIFDenum
+
+
+	0x002A01CC,
+	0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+	0xFFFF000A,
+	//===================================================================
+	// Input Width & Height
+	//===================================================================
+	0x002A01F6,
+	0x0F1205C0,	                  //0800                   //REG_TC_GP_PrevReqInputWidth
+	0x0F12033C,	                  //0600                   //REG_TC_GP_PrevReqInputHeight
+	0x0F120120,	                  //0000                   //REG_TC_GP_PrevInputWidthOfs
+	0x0F120162,	                  //0000                   //REG_TC_GP_PrevInputHeightOfs
+	0x0F120800, //REG_TC_GP_CapReqInputWidth	                  //Sensor Crop Width	2048
+	0x0F120600, //REG_TC_GP_CapReqInputHeight	                  //Sensor Crop Height 1536
+	0x0F120000, //REG_TC_GP_CapInputWidthOfs	                  //Sensor HOffset 0
+	0x0F120000, //REG_TC_GP_CapInputHeightOfs	                  //Sensor VOffset 0
+
+	0x002A1676,
+	0x0F120002,	                           // 0:Full 1:digital 2:PLA 3:CA
+
+	0x002A0216,
+	0x0F120001,	                           //for input size change
+
+	0x002A0216,
+	0x0F120001, //REG_TC_GP_bUseReqInputInPre
+	0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+	0x002A043C,
+	0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+	0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+	0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+	0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+	//===================================================================
+	// Preview 0 1024x768 system 52M PCLK 54M
+	//===================================================================
+	0x002A023E,
+	0x0F120500, //REG_0TC_PCFG_usWidth
+	0x0F1202D0, //REG_0TC_PCFG_usHeight
+	0x0F120005, //REG_0TC_PCFG_Format
+	0x0F1254F6,	                  //7148	                  //REG_0TC_PCFG_usMaxOut4KH
+	0x0F1254F6,	                  //7148	                  //REG_0TC_PCFG_usMinOut4KH
+
+	0x002A024C,
+	0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_PCFG_OIFMask
+
+	0x002A0254,
+	0x0F120001, //REG_0TC_PCFG_uClockInd
+	0x0F120000, //REG_0TC_PCFG_usFrTimeType
+	0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+	0x0F1201B8, //1A0                   //REG_0TC_PCFG_usMaxFrTimeMsecMult10                  //
+	0x0F12014D, //REG_0TC_PCFG_usMinFrTimeMsecMult10                  //min frame time : 30fps 0
+
+	0x0F120000, //REG_0TC_PCFG_bSmearOutput
+	0x0F120000, //REG_0TC_PCFG_sSaturation
+	0x0F120000, //REG_0TC_PCFG_sSharpBlur
+	0x0F120000, //REG_0TC_PCFG_sColorTemp
+	0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+#if 1 /* [P4W] fix rotation to 180*/
+	0x0F120003, //REG_0TC_PCFG_uPrevMirror
+	0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+#endif
+	0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+	//===================================================================
+	// Capture 0 2048x1536 system 52M PCLK 54M
+	//===================================================================
+	0x002A032E,
+	0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+	0x0F120800, //REG_0TC_CCFG_usWidth
+	0x0F120600, //REG_0TC_CCFG_usHeight
+	0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMaxOut4KHzRate
+	0x0F1254F6,	                  //REG_0TC_CCFG_usMinOut4KHzRate
+
+	0x002A033E,
+	0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+	0x0F120010, //REG_0TC_CCFG_OIFMask
+	0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+	0x002A0346,
+	0x0F120001, //REG_0TC_CCFG_uClockInd
+	0x0F120002, //REG_0TC_CCFG_usFrTimeType
+	0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+	0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+	0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+	0x0F120000, //REG_0TC_CCFG_bSmearOutput
+	0x0F120000, //REG_0TC_CCFG_sSaturation
+	0x0F120000, //REG_0TC_CCFG_sSharpBlur
+	0x0F120000, //REG_0TC_CCFG_sColorTemp
+	0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+	0x002A0426,
+	0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+	0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+	0x0F120000,
+
+
+
+
+	/* PREVIEW */
+	/* 0x002A0208, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActivePrevConfig */
+	/* 0x002A0210, */
+	/* 0x0F120000, */ /* REG_TC_GP_ActiveCapConfig */
+	/* 0x002A020C, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevOpenAfterChange */
+	/* 0x002A01F4, */
+	/* 0x0F120001, */ /* REG_TC_GP_NewConfigSync */
+	/* 0x002A020A, */
+	/* 0x0F120001, */ /* REG_TC_GP_PrevConfigChanged */
+	/* 0x002A0212 ,*/
+	/* 0x0F120001, */ /* REG_TC_GP_CapConfigChanged */
+	/* 0x002A01E8, */
+	/* 0x0F120000, */ /* REG_TC_GP_EnableCapture */
+	/* 0x0F120001, */ /* REG_TC_GP_EnableCaptureChanged */
+
+	/* 0xFFFF0064, */ /* Delay 100ms */
+
+	//===================================================================
+	// AFC
+	//===================================================================
+	//Auto
+	0x002A0F08,
+	0x0F120001, //AFC_Default60Hz   01:60hz 00:50Hz
+	0x002A04A4,
+	0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+
+	//===================================================================
+	// Shading (AF module)
+	//===================================================================
+	// TVAR_ash_pGAS_high
+	0x002A0D22,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120000,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F12000F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120F00,
+	0x0F120F00,
+	0x0F120000,
+	0x0F120F0F,
+	0x0F12000F,
+	0x0F120F0F,
+	0x0F120000,
+	0x0F12000F,
+	0x0F120F0F,
+
+	// TVAR_ash_pGAS_low
+	0x0F126E49,
+	0x0F12FB98,
+	0x0F12F348,
+	0x0F121BD6,
+	0x0F12EBEF,
+	0x0F1203D3,
+	0x0F12EC8D,
+	0x0F12F239,
+	0x0F120E64,
+	0x0F12F7EA,
+	0x0F12FD3B,
+	0x0F120A7C,
+	0x0F12FC9C,
+	0x0F120BD3,
+	0x0F12F2E5,
+	0x0F120619,
+	0x0F120772,
+	0x0F12F0B0,
+	0x0F12184E,
+	0x0F12F95F,
+	0x0F120B1A,
+	0x0F12FC45,
+	0x0F12F716,
+	0x0F120DCD,
+	0x0F12EF24,
+	0x0F120221,
+	0x0F12F6BD,
+	0x0F1204CB,
+	0x0F1200B1,
+	0x0F12FEB0,
+	0x0F120268,
+	0x0F1202C7,
+	0x0F12010A,
+	0x0F12FF93,
+	0x0F12036D,
+	0x0F12F859,
+	0x0F1281D0,
+	0x0F12FA32,
+	0x0F12EFDB,
+	0x0F12234D,
+	0x0F12E799,
+	0x0F120337,
+	0x0F12EB05,
+	0x0F12E8F9,
+	0x0F12152E,
+	0x0F12F0D5,
+	0x0F120842,
+	0x0F12043A,
+	0x0F12F461,
+	0x0F120E58,
+	0x0F12F658,
+	0x0F12075D,
+	0x0F12F78D,
+	0x0F12FDE9,
+	0x0F12277A,
+	0x0F12FFDE,
+	0x0F12FD3B,
+	0x0F12FE50,
+	0x0F120AD1,
+	0x0F12FE2C,
+	0x0F12E90D,
+	0x0F12F7B0,
+	0x0F1205DB,
+	0x0F1202CD,
+	0x0F12F4F1,
+	0x0F1202A8,
+	0x0F12FDDC,
+	0x0F120B59,
+	0x0F12F74E,
+	0x0F1203D5,
+	0x0F12FF4F,
+	0x0F1200F7,
+	0x0F126A44,
+	0x0F12FAD6,
+	0x0F12F261,
+	0x0F121F28,
+	0x0F12E691,
+	0x0F1207D2,
+	0x0F12EE85,
+	0x0F12F426,
+	0x0F120F26,
+	0x0F12F34B,
+	0x0F120036,
+	0x0F120C0F,
+	0x0F12FDA9,
+	0x0F1209EA,
+	0x0F12F27A,
+	0x0F120CD5,
+	0x0F1201E1,
+	0x0F12ED41,
+	0x0F121DB5,
+	0x0F12FD26,
+	0x0F1203F7,
+	0x0F12F7BB,
+	0x0F12FE81,
+	0x0F1212D3,
+	0x0F12E061,
+	0x0F12F81C,
+	0x0F1207B1,
+	0x0F120408,
+	0x0F12F860,
+	0x0F12FC9A,
+	0x0F120DDE,
+	0x0F120C9C,
+	0x0F12F2A4,
+	0x0F1202EB,
+	0x0F12099B,
+	0x0F12F5A6,
+	0x0F127243,
+	0x0F12F74D,
+	0x0F12F74B,
+	0x0F121800,
+	0x0F12EF22,
+	0x0F120263,
+	0x0F12EBE7,
+	0x0F12F5A4,
+	0x0F1209D3,
+	0x0F12FAB8,
+	0x0F12FDFF,
+	0x0F12086B,
+	0x0F120338,
+	0x0F120514,
+	0x0F12F840,
+	0x0F120768,
+	0x0F12FE55,
+	0x0F12F884,
+	0x0F121488,
+	0x0F12FFCD,
+	0x0F12035B,
+	0x0F12FA4E,
+	0x0F1201DB,
+	0x0F1206D6,
+	0x0F12EE19,
+	0x0F12FEA3,
+	0x0F12FE8C,
+	0x0F1203A3,
+	0x0F12FDDB,
+	0x0F12FD9B,
+	0x0F12035E,
+	0x0F1203F2,
+	0x0F12FCBD,
+	0x0F120300,
+	0x0F12FF2E,
+	0x0F12FE03,
+
+	0x002A04A8,
+	0x0F120001, //REG_TC_DBG_ReInitCmd
+
+	//===================================================================
+	// Shading - Alpha
+	//===================================================================
+	0x002A07E8,
+	0x0F1200BC, //TVAR_ash_AwbAshCord_0_                  //HOR
+	0x0F1200ED, //TVAR_ash_AwbAshCord_1_                  //INCA
+	0x0F120101, //TVAR_ash_AwbAshCord_2_                  //WW
+	0x0F12012D, //TVAR_ash_AwbAshCord_3_                  //CW
+	0x0F120166, //TVAR_ash_AwbAshCord_4_                  //D50
+	0x0F120184, //TVAR_ash_AwbAshCord_5_                  //D65
+	0x0F1201A0, //TVAR_ash_AwbAshCord_6_                  //D75
+	0x002A07FE,
+	0x0F123200, //TVAR_ash_GASAlpha_0__0_
+	0x0F124000, //TVAR_ash_GASAlpha_0__1_
+	0x0F124000, //TVAR_ash_GASAlpha_0__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+	0x0F123200, //TVAR_ash_GASAlpha_1__0_
+	0x0F124000, //TVAR_ash_GASAlpha_1__1_
+	0x0F124000, //TVAR_ash_GASAlpha_1__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+	0x0F123200, //TVAR_ash_GASAlpha_2__0_
+	0x0F124000, //TVAR_ash_GASAlpha_2__1_
+	0x0F124000, //TVAR_ash_GASAlpha_2__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+	0x0F123200, //TVAR_ash_GASAlpha_3__0_
+	0x0F124000, //TVAR_ash_GASAlpha_3__1_
+	0x0F124000, //TVAR_ash_GASAlpha_3__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+	0x0F123200, //TVAR_ash_GASAlpha_4__0_
+	0x0F124000, //TVAR_ash_GASAlpha_4__1_
+	0x0F124000, //TVAR_ash_GASAlpha_4__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+	0x0F123200, //TVAR_ash_GASAlpha_5__0_
+	0x0F124000, //TVAR_ash_GASAlpha_5__1_
+	0x0F124000, //TVAR_ash_GASAlpha_5__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+	0x0F124000, //TVAR_ash_GASAlpha_6__0_
+	0x0F124000, //TVAR_ash_GASAlpha_6__1_
+	0x0F124000, //TVAR_ash_GASAlpha_6__2_
+	0x0F123C00, //TVAR_ash_GASAlpha_6__3_
+
+	0x002A0836,
+	0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	//===================================================================
+	// Gamma
+	//===================================================================
+	//	param_start	SARR_usGammaLutRGBIndoor
+	0x002A0660,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+	0x0F120000,
+	0x0F120023,
+	0x0F120044,
+	0x0F12007B,
+	0x0F1200BB,
+	0x0F120102,
+	0x0F12012F,
+	0x0F120143,
+	0x0F120155,
+	0x0F120172,
+	0x0F12018C,
+	0x0F1201A4,
+	0x0F1201BC,
+	0x0F1201EC,
+	0x0F12021D,
+	0x0F12027E,
+	0x0F1202DF,
+	0x0F12033F,
+	0x0F12039F,
+	0x0F1203FF,
+
+	//s002A06D8
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[0][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[0][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[0][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[0][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[0][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[0][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[0][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[0][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[0][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[0][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[0][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[0][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[0][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[0][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[0][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[0][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[0][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[0][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[0][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[0][19]
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[1][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[1][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[1][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[1][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[1][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[1][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[1][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[1][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[1][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[1][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[1][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[1][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[1][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[1][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[1][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[1][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[1][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[1][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[1][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[1][19]
+	0x0F120001, //saRR_usDualGammaLutRGBOutdoor[2][0]
+	0x0F120011, //saRR_usDualGammaLutRGBOutdoor[2][1]
+	0x0F120028, //saRR_usDualGammaLutRGBOutdoor[2][2]
+	0x0F120059, //saRR_usDualGammaLutRGBOutdoor[2][3]
+	0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[2][4]
+	0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[2][5]
+	0x0F120128, //saRR_usDualGammaLutRGBOutdoor[2][6]
+	0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[2][7]
+	0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[2][8]
+	0x0F120168, //saRR_usDualGammaLutRGBOutdoor[2][9]
+	0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[2][10]
+	0x0F120190, //saRR_usDualGammaLutRGBOutdoor[2][11]
+	0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[2][12]
+	0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[2][13]
+	0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[2][14]
+	0x0F120243, //saRR_usDualGammaLutRGBOutdoor[2][15]
+	0x0F120293, //saRR_usDualGammaLutRGBOutdoor[2][16]
+	0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[2][17]
+	0x0F120338, //saRR_usDualGammaLutRGBOutdoor[2][18]
+	0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+	//===================================================================
+	// AE - shutter
+	//===================================================================
+	//****************************************/
+	// AE 2009 03 08 - based on TN
+	//****************************************/
+
+	//add ki 11.02.18
+	// SLOW AE
+	// SLOW AE
+	0x002A13F2,
+	0x0F120014,	                  // 0010 ae_GainIn_0_			                  //
+	0x0F120032,	                  // 0020	ae_GainIn_1_
+	0x0F120078,	                  // 0040	ae_GainIn_2_
+	0x0F1200AA,	                  // 0080	ae_GainIn_3_
+	0x0F120100,	                  // fix 0100	ae_GainIn_4_
+	0x0F120140,	                  // 0200	ae_GainIn_5_
+	0x0F1201B8,	                  // 0400	ae_GainIn_6_
+	0x0F120400,	                  // 0800	ae_GainIn_7_
+	0x0F122000,	                  // 2000	ae_GainIn_8_
+
+	0x0F120046,	                  //0050	                  // 0010	ae_GainOut_0
+	0x0F120078,	                  //0070	                  // 0020	ae_GainOut_1
+	0x0F1200BE,	                  //00A0	                  // 0040	ae_GainOut_2
+	0x0F1200DC,	                  //00D0	                  // 0080	ae_GainOut_3
+	0x0F120100,	                  // fix 0100	ae_GainOut_4_		                  //
+	0x0F12010E,	                  // 0200	ae_GainOut_5_		                  //
+	0x0F120140,	                  // 0400	ae_GainOut_6_		                  //
+	0x0F1201F4,	                  // 0800	ae_GainOut_7_		                  //
+	0x0F120200,	                  // 2000	ae_GainOut_8_		                  //
+
+
+	0x002A13BC,
+	0x0F120100,										//00
+	0x0F120100,			//000C		ae_ContrastS_1_//
+	0x0F120100,			//001C		ae_ContrastS_2_//
+	0x0F120100,			//0020		ae_ContrastS_3_//
+	0x0F120100,			//0020		ae_ContrastS_4_//
+	0x0F120100,			//0020		ae_ContrastS_5_//
+	0x0F120100,			//0020		ae_ContrastS_6_//
+	0x0F120100,			//0020		ae_ContrastS_7_//
+
+	//============================================================
+	// Frame rate setting
+	//============================================================
+	// How to set
+	// 1. Exposure value
+	// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+	//
+	//
+	// 2. Analog Digital gain
+	// dec2hex((Analog gain you want) * 256d)
+	//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+	//============================================================
+	//MBR
+
+
+	0x002A01DE,
+	0x0F120000, //REG_TC_bUseMBR                  //MBR off
+	//MBR off is needed to prevent a shorter integration time when the scene has blurring in Nig
+
+	//AE_Target
+	0x002A1308,
+	0x0F12003E, //TVAR_ae_BrAve
+	0x002A130E,
+	0x0F12000F, //ae_StatMode
+	//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight
+
+	//AE_state
+	0x002A04EE,
+	0x0F120105, //010E                   //#lt_uLimitHigh
+	0x0F1200FA, //00F5                   //#lt_uLimitLow
+
+	0x002A0500,
+	0x0F120001,	         //lt_uInitPostToleranceCnt
+
+	//For 60Hz
+	0x002A0504,
+	0x0F123415, //3415                   //#lt_uMaxExp1
+	0x002A0508,
+	0x0F123415, //26e8          //681F                   //#lt_uMaxExp2
+	0x002A050C,
+	0x0F123415, //26e8          //8227                   //#lt_uMaxExp3
+	0x002A0510,
+	0x0F12C350, //#lt_uMaxExp4
+
+	0x002A0514,
+	0x0F123415, //#lt_uCapMaxExp1
+	0x002A0518,
+	0x0F123415, //681F                   //#lt_uCapMaxExp2
+	0x002A051C,
+	0x0F123415, //8227                   //#lt_uCapMaxExp3
+	0x002A0520,
+	0x0F12C350, //#lt_uCapMaxExp4
+
+	0x002A0524,
+	0x0F120200, //1E0                   //#lt_uMaxAnGain1
+	0x0F120240, //1E0                   //#lt_uMaxAnGain2
+	0x0F120340, //0300                   //#lt_uMaxAnGain3
+	0x0F120A00, //#lt_uMaxAnGain4
+
+	0x0F120100, //#lt_uMaxDigGain
+	0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	0x0F120200, //#lt_uCapMaxAnGain1
+	0x0F120240, //#lt_uCapMaxAnGain2
+	0x0F120340, //300                   //#lt_uCapMaxAnGain3
+	0x0F120A00, //#lt_uCapMaxAnGain4
+
+	0x0F120100, //#lt_uCapMaxDigGain
+	0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+	//===================================================================
+	//AE - Weights
+	//===================================================================
+	0x002A1316,
+	0x0F120101, //ae_WeightTbl_16[0]   0000
+	0x0F120101, //ae_WeightTbl_16[1]   0000
+	0x0F120101, //ae_WeightTbl_16[2]   0000
+	0x0F120101, //ae_WeightTbl_16[3]   0000
+	0x0F120101, //ae_WeightTbl_16[4]   0101
+	0x0F120101, //ae_WeightTbl_16[5]   0101
+	0x0F120101, //ae_WeightTbl_16[6]   0101
+	0x0F120101, //ae_WeightTbl_16[7]   0101
+	0x0F120101, //ae_WeightTbl_16[8]   0101
+	0x0F120202, //ae_WeightTbl_16[9]   0201
+	0x0F120202, //ae_WeightTbl_16[10]  0102
+	0x0F120101, //ae_WeightTbl_16[11]  0101
+	0x0F120101, //ae_WeightTbl_16[12]  0101
+	0x0F120202, //ae_WeightTbl_16[13]  0202
+	0x0F120202, //ae_WeightTbl_16[14]  0202
+	0x0F120101, //ae_WeightTbl_16[15]  0101
+	0x0F120101, //ae_WeightTbl_16[16]  0101
+	0x0F120202, //ae_WeightTbl_16[17]  0202
+	0x0F120202, //ae_WeightTbl_16[18]  0202
+	0x0F120101, //ae_WeightTbl_16[19]  0101
+	0x0F120101, //ae_WeightTbl_16[20]  0201
+	0x0F120202, //ae_WeightTbl_16[21]  0202
+	0x0F120202, //ae_WeightTbl_16[22]  0202
+	0x0F120101, //ae_WeightTbl_16[23]  0102
+	0x0F120101, //ae_WeightTbl_16[24]  0201
+	0x0F120101, //ae_WeightTbl_16[25]  0202
+	0x0F120101, //ae_WeightTbl_16[26]  0202
+	0x0F120101, //ae_WeightTbl_16[27]  0102
+	0x0F120101, //ae_WeightTbl_16[28]  0101
+	0x0F120101, //ae_WeightTbl_16[29]  0101
+	0x0F120101, //ae_WeightTbl_16[30]  0101
+	0x0F120101, //ae_WeightTbl_16[31]  0101
+
+	//===================================================================
+	//AWB-BASIC setting
+	//===================================================================
+	0x002A1018,
+	0x0F1202A7, //awbb_GLocusR
+	0x0F120343, //awbb_GLocusB
+	0x002A0FFC,
+	0x0F12036C, //awbb_CrclLowT_R_c
+	0x002A1000,
+	0x0F12011D, //awbb_CrclLowT_B_c
+	0x002A1004,
+	0x0F1262C1, //awbb_CrclLowT_Rad_c
+	0x002A1034,
+	0x0F12074D,	         //05F0                   //awbb_GamutWidthThr1
+	0x0F120433,	         //01F4                   //awbb_GamutHeightThr1
+	0x0F12002A,	         //006C                   //awbb_GamutWidthThr2
+	0x0F12000C,	         //0038                   //awbb_GamutHeightThr2
+	0x002A1020,
+	0x0F120020,	         //000C                   //awbb_MinNumOfFinalPatches
+	0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+	0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+	0x002A1028,
+	0x0F120020,	         //awbb_MinNumOfOutdoorPatches
+
+	0x002A291A,
+	0x0F120004, // #Mon_AWB_ByPassMode                            // [0]Outdoor [1]LowBr [2]LowT
+
+	0x002A1048,
+	0x0F1200C8,	         //awbb_LowBr
+	0x0F12001E,	         //awbb_LowBr_NBzone
+
+	0x002A1008,
+	0x0F120020,	         //awbb_NormalYThresh_y_low
+	0x0F1200A0,	         //awbb_NormalYThresh_y_high
+	0x0F120002, //awbb_LowBrYThresh_y_low
+	0x0F1200A0, //awbb_LowBrYThresh_y_high
+
+
+
+	0x002A102E,
+	0x0F12054D,					         //awbb_MvEq_RBthresh
+
+	0x002A1032,
+	0x0F120000, //awbb_MovingScale10
+
+	0x002A11C2,
+	0x0F120000, //awbb_RGainOff
+	0x0F120000, //awbb_BGainOff
+	0x0F120000, //awbb_GGainOff
+	0x0F1200C2, //awbb_Alpha_Comp_Mode
+	0x0F120002, //awbb_Rpl_InvalidOutDoor
+	0x0F120001, //awbb_UseGrThrCorr
+	0x0F1200E4, //awbb_Use_Filters
+	0x0F12053C, //awbb_GainsInit[0]
+	0x0F120400, //awbb_GainsInit[1]
+	0x0F12055C, //awbb_GainsInit[2]
+
+	//===================================================================
+	//AWB-Zone
+	//===================================================================
+	//	param_start	awbb_IndoorGrZones_m_BGrid
+	0x002A0F28,
+	0x0F120426,	         //03C0                   //03C0                  //03C0
+	0x0F12047E,	         //03E2                   //03E2                  //03E2
+	0x0F1203C6,	         //0356                   //0356                  //0356
+	0x0F120496,	         //03FC                   //03FC                  //03FC
+	0x0F120374,	         //031E                   //031E                  //031E
+	0x0F1204A0,	         //03FE                   //03FE                  //03FE
+	0x0F12033A,	         //02F0                   //02F0                  //02F0
+	0x0F120498,	         //03F0                   //03F0                  //03F0
+	0x0F120312,	         //02CA                   //02CA                  //02CA
+	0x0F120478,	         //03CC                   //03CC                  //03CC
+	0x0F1202EA,	         //02A8                   //02A8                  //02A8
+	0x0F120440,	         //037A                   //037A                  //037A
+	0x0F1202C2,	         //0280                   //0288                  //0288
+	0x0F1203FA,	         //033C                   //033C                  //033C
+	0x0F12029A,	         //0260                   //0266                  //0266
+	0x0F1203BE,	         //030A                   //030A                  //031E
+	0x0F120272,	         //0242                   //0246                  //0246
+	0x0F120398,	         //02DC                   //02EC                  //0300
+	0x0F12024E,	         //0228                   //0228                  //0228
+	0x0F120372,	         //02B2                   //02CE                  //02E8
+	0x0F12022A,	         //020E                   //020E                  //020E
+	0x0F120340,	         //0290                   //02B0                  //02CA
+	0x0F120206,	         //01F8                   //01F8                  //01F8
+	0x0F120310,	         //0276                   //0292                  //02B0
+	0x0F1201E2,	         //01E8                   //01E8                  //01E8
+	0x0F1202DE,	         //0268                   //0276                  //0296
+	0x0F1201C0,	         //01DC                   //01DC                  //01DC
+	0x0F1202AE,	         //0256                   //0256                  //027A
+	0x0F1201B4,	         //01E0                   //01E0                  //01E0
+	0x0F12027E,	         //0238                   //0238                  //0252
+	0x0F1201C0,	         //01EC                   //01EC                  //01F2
+	0x0F12024C,	         //020E                   //020E                  //0226
+	0x0F1201FA,	         //0000                   //0000                  //0000
+	0x0F12021C,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	0x0F120000,	         //0000                   //0000                  //0000
+	//	param_end	awbb_IndoorGrZones_m_BGrid
+
+	0x0F120005, //awbb_IndoorGrZones_m_Grid
+	0x002A0F80,
+	0x0F1200A6, //awbb_IndoorGrZones_m_Boff
+	0x002A0F7C,
+	0x0F120011,
+
+	//	param_start	awbb_OutdoorGrZones_m_BGrid
+	0x002A0F84,
+	0x0F12023E, //awbb_OutdoorGrZones_m_BGrid[0]
+	0x0F120286, //awbb_OutdoorGrZones_m_BGrid[1]
+	0x0F12022C, //awbb_OutdoorGrZones_m_BGrid[2]
+	0x0F1202CC, //awbb_OutdoorGrZones_m_BGrid[3]
+	0x0F12021A, //awbb_OutdoorGrZones_m_BGrid[4]
+	0x0F1202F0, //awbb_OutdoorGrZones_m_BGrid[5]
+	0x0F120208, //awbb_OutdoorGrZones_m_BGrid[6]
+	0x0F120316, //awbb_OutdoorGrZones_m_BGrid[7]
+	0x0F1201F6, //awbb_OutdoorGrZones_m_BGrid[8]
+	0x0F1202FE, //awbb_OutdoorGrZones_m_BGrid[9]
+	0x0F1201E4, //awbb_OutdoorGrZones_m_BGrid[10]
+	0x0F1202E8, //awbb_OutdoorGrZones_m_BGrid[11]
+	0x0F1201D2, //awbb_OutdoorGrZones_m_BGrid[12]
+	0x0F1202D2, //awbb_OutdoorGrZones_m_BGrid[13]
+	0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[14]
+	0x0F1202BC, //awbb_OutdoorGrZones_m_BGrid[15]
+	0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[16]
+	0x0F1202A6, //awbb_OutdoorGrZones_m_BGrid[17]
+	0x0F1201D0, //awbb_OutdoorGrZones_m_BGrid[18]
+	0x0F12028E, //awbb_OutdoorGrZones_m_BGrid[19]
+	0x0F1201D6, //awbb_OutdoorGrZones_m_BGrid[20]
+	0x0F120278, //awbb_OutdoorGrZones_m_BGrid[21]
+	0x0F1201F8, //awbb_OutdoorGrZones_m_BGrid[22]
+	0x0F120244, //awbb_OutdoorGrZones_m_BGrid[23]
+	//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+	0x0F120004, //awbb_OutdoorGrZones_m_Gri
+	0x002A0FB8,
+	0x0F12000C, //awbb_OutdoorGrZones_ZInfo_m_GridSz
+	0x002A0FBC,
+	0x0F1201D8, //awbb_OutdoorGrZones_m_Bof
+
+	//	param_start	awbb_LowBrGrZones_m_BGrid
+	0x002A0FC0,
+	0x0F120400, //awbb_LowBrGrZones_m_BGrid[0]
+	0x0F120656, //awbb_LowBrGrZones_m_BGrid[1]
+	0x0F12035A, //awbb_LowBrGrZones_m_BGrid[2]
+	0x0F1205BE, //awbb_LowBrGrZones_m_BGrid[3]
+	0x0F1202E6, //awbb_LowBrGrZones_m_BGrid[4]
+	0x0F120524, //awbb_LowBrGrZones_m_BGrid[5]
+	0x0F120290, //awbb_LowBrGrZones_m_BGrid[6]
+	0x0F1204A0, //awbb_LowBrGrZones_m_BGrid[7]
+	0x0F120246, //awbb_LowBrGrZones_m_BGrid[8]
+	0x0F12041A, //awbb_LowBrGrZones_m_BGrid[9]
+	0x0F1201FE, //awbb_LowBrGrZones_m_BGrid[10]
+	0x0F1203AE, //awbb_LowBrGrZones_m_BGrid[11]
+	0x0F1201C0, //awbb_LowBrGrZones_m_BGrid[12]
+	0x0F12035A, //awbb_LowBrGrZones_m_BGrid[13]
+	0x0F120192, //awbb_LowBrGrZones_m_BGrid[14]
+	0x0F120306, //awbb_LowBrGrZones_m_BGrid[15]
+	0x0F120170, //awbb_LowBrGrZones_m_BGrid[16]
+	0x0F1202BA, //awbb_LowBrGrZones_m_BGrid[17]
+	0x0F12015C, //awbb_LowBrGrZones_m_BGrid[18]
+	0x0F120278, //awbb_LowBrGrZones_m_BGrid[19]
+	0x0F12019C, //awbb_LowBrGrZones_m_BGrid[20]
+	0x0F12024E, //awbb_LowBrGrZones_m_BGrid[21]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+	0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+	//	param_end	awbb_LowBrGrZones_m_BGrid
+	0x0F120006, //awbb_LowBrGrZones_m_GridStep
+	0x002A0FF4,
+	0x0F12000B, //awbb_LowBrGrZones_ZInfo_m_GridSz
+	0x002A0FF8,
+	0x0F120082, //awbb_LowBrGrZones_m_Boffs
+
+	//===================================================================
+	//AWB Scene Detection
+	//===================================================================
+	0x002A1098,
+	0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+	0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+	0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+	0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+	0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+	0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+	0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+	0x002A105C,
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+	0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+	0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+	0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+	0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+	0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+	0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+	0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+	0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+	0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+	0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+	0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+	0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+	0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+	0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+	0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+	0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+
+	//===================================================================
+	//AWB - GridCorrection
+	//===================================================================
+	0x002A11E0,
+	0x0F120002, //awbb_GridEnable
+
+	0x002A11A8,
+	0x0F12028E, //awbb_GridCon0xt_1[0]
+	0x0F120306, //awbb_GridCon0xt_1[1]
+	0x0F1203A6, //awbb_GridCon0xt_1[2]
+
+	0x0F120F86, //awbb_GridCon0xt_2[0]  0F86
+	0x0F12105F, //awbb_GridCon0xt_2[1]  105F
+	0x0F121160, //awbb_GridCon0xt_2[2]  11AA
+	0x0F121161, //awbb_GridCon0xt_2[3]  1111
+	0x0F1211F2, //awbb_GridCon0xt_2[4]  120C
+	0x0F1212A1, //awbb_GridCon0xt_2[5]  126D
+
+	0x0F12008F, //awbb_GridCoeff_R_1
+	0x0F1200D4, //awbb_GridCoeff_B_1
+	0x0F1200C6, //awbb_GridCoeff_R_2
+	0x0F1200A2, //awbb_GridCoeff_B_2
+
+	0x002A1118,
+	0x0F120000, //0032         //awbb_GridCorr_R[0][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[0][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[0][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[0][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[0][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[0][5]
+	0x0F120000, //0032         //awbb_GridCorr_R[1][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[1][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[1][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[1][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[1][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[1][5]
+	0x0F120000, //0032         //awbb_GridCorr_R[2][0]
+	0x0F120000, //0012         //awbb_GridCorr_R[2][1]
+	0x0F120000, //0012         //awbb_GridCorr_R[2][2]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[2][3]
+	0x0F120018, //FFEC         //awbb_GridCorr_R[2][4]
+	0x0F120060, //0050         //awbb_GridCorr_R[2][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[0][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[0][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[0][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[0][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[1][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[1][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[1][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[1][5]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][0]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][1]
+	0x0F12FFD0, //FFD0       //awbb_GridCorr_B[2][2]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[2][3]
+	0x0F12FF22, //FE40       //awbb_GridCorr_B[2][4]
+	0x0F12FE3E, //FCE0       //awbb_GridCorr_B[2][5]
+
+	0x002A1160,
+	0x0F120000, //awbb_GridCorr_R_Out[0][0]
+	0x0F120000, //awbb_GridCorr_R_Out[0][1]
+	0x0F120000, //awbb_GridCorr_R_Out[0][2]
+	0x0F120000, //awbb_GridCorr_R_Out[0][3]
+	0x0F120000, //awbb_GridCorr_R_Out[0][4]
+	0x0F120000, //awbb_GridCorr_R_Out[0][5]
+	0x0F120000, //awbb_GridCorr_R_Out[1][0]
+	0x0F120000, //awbb_GridCorr_R_Out[1][1]
+	0x0F120000, //awbb_GridCorr_R_Out[1][2]
+	0x0F120000, //awbb_GridCorr_R_Out[1][3]
+	0x0F120000, //awbb_GridCorr_R_Out[1][4]
+	0x0F120000, //awbb_GridCorr_R_Out[1][5]
+	0x0F120000, //awbb_GridCorr_R_Out[2][0]
+	0x0F120000, //awbb_GridCorr_R_Out[2][1]
+	0x0F120000, //awbb_GridCorr_R_Out[2][2]
+	0x0F120000, //awbb_GridCorr_R_Out[2][3]
+	0x0F120000, //awbb_GridCorr_R_Out[2][4]
+	0x0F120000, //awbb_GridCorr_R_Out[2][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[0][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[1][5]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][0]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][1]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][2]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][3]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][4]
+	0x0F12FFA0, //awbb_GridCorr_B_Out[2][5]
+
+
+	 // SLOW AWB
+	0x002A110E,
+	0x0F120258, //0258 awbb_GainsMaxMove         //
+
+	 //AWB Convergence Speed          //
+	0x002A11D6,
+	0x0F120008,
+	0x0F12FFFF,	         //0190	awbb_WpFilterMaxThr          //
+	0x0F120010, //00A0	         //awbb_WpFilterCoef p          //
+	0x0F120020,	         //0004 awbb_WpFilterSize          //
+
+	//===================================================================
+	// CCM
+	//===================================================================
+	0x002A07D2,
+	0x0F1200C0, //SARR_AwbCcmCord_0_
+	0x0F1200E0, //SARR_AwbCcmCord_1_
+	0x0F120110, //SARR_AwbCcmCord_2_
+	0x0F120139, //SARR_AwbCcmCord_3_
+	0x0F120166, //SARR_AwbCcmCord_4_
+	0x0F12019F, //SARR_AwbCcmCord_5_
+
+	//	param_start	TVAR_wbt_pBaseCcms
+	0x002A07C4,
+	0x0F124000, //TVAR_wbt_pBaseCcms
+	0x0F127000,
+
+	0x002A4000,
+	0x0F1201D4, //01DA 01CF 01CE 01C0 01D4                  //TVAR_wbt_pBaseCcms[0]
+	0x0F12FFCD, //FFC4 FFC3 FFB9 FFCB FFB2                  //TVAR_wbt_pBaseCcms[1]
+	0x0F12FFC4, //FFCD FFDD FFE8 FFE4 FFEE                  //TVAR_wbt_pBaseCcms[2]
+	0x0F12FF2A, //FF31 FF43 FF43 FF43 FF47                  //TVAR_wbt_pBaseCcms[3]
+	0x0F120124, //012A 011D 011D 011D 012C                  //TVAR_wbt_pBaseCcms[4]
+	0x0F12FF73, //FF6B FF6B FF6B FF6B FF5C                  //TVAR_wbt_pBaseCcms[5]
+	0x0F12FFE1, //FFDA FFDA FFDA FFDA FFCE                  //TVAR_wbt_pBaseCcms[6]
+	0x0F12FFBD, //FFC3 FFD1 FFD1 FFD1 FFD6                  //TVAR_wbt_pBaseCcms[7]
+	0x0F120159, //015F 0156 0156 0156 0162                  //TVAR_wbt_pBaseCcms[8]
+	0x0F1200EF, //0100 00FF 00FC 00F7 011D                  //TVAR_wbt_pBaseCcms[9]
+	0x0F1200E0, //00DE 00CE 00CC 00D1 00C6                  //TVAR_wbt_pBaseCcms[10]
+	0x0F12FED9, //FECE FEE3 FEE9 FEE9 FED2                  //TVAR_wbt_pBaseCcms[11]
+	0x0F1200DA, //00D5 00CD 00CD 00CD 00C8                  //TVAR_wbt_pBaseCcms[12]
+	0x0F12FF57, //FF56 FF5E FF5E FF5E FF56                  //TVAR_wbt_pBaseCcms[13]
+	0x0F120119, //0123 0128 0128 0128 0139                  //TVAR_wbt_pBaseCcms[14]
+	0x0F12FF74, //FF73 FF7E FF7E FF7E FF75                  //TVAR_wbt_pBaseCcms[15]
+	0x0F1200DF, //00E9 00EC 00EC 00EC 00FB                  //TVAR_wbt_pBaseCcms[16]
+	0x0F1200FF, //00FC 00F2 00F2 00F2 00F0                  //TVAR_wbt_pBaseCcms[17]
+
+	0x0F1201D4, //01D4                  //TVAR_wbt_pBaseCcms[18]
+	0x0F12FFCD, //FFB2                  //TVAR_wbt_pBaseCcms[19]
+	0x0F12FFC4, //FFEE                  //TVAR_wbt_pBaseCcms[20]
+	0x0F12FF2A, //FF47                  //TVAR_wbt_pBaseCcms[21]
+	0x0F120124, //012C                  //TVAR_wbt_pBaseCcms[22]
+	0x0F12FF73, //FF5C                  //TVAR_wbt_pBaseCcms[23]
+	0x0F12FFE1, //FFCE                  //TVAR_wbt_pBaseCcms[24]
+	0x0F12FFBD, //FFD6                  //TVAR_wbt_pBaseCcms[25]
+	0x0F120159, //0162                  //TVAR_wbt_pBaseCcms[26]
+	0x0F1200EF, //011D                  //TVAR_wbt_pBaseCcms[27]
+	0x0F1200E0, //00C6                  //TVAR_wbt_pBaseCcms[28]
+	0x0F12FED9, //FED2                  //TVAR_wbt_pBaseCcms[29]
+	0x0F1200DA, //00C8                  //TVAR_wbt_pBaseCcms[30]
+	0x0F12FF57, //FF56                  //TVAR_wbt_pBaseCcms[31]
+	0x0F120119, //0139                  //TVAR_wbt_pBaseCcms[32]
+	0x0F12FF74, //FF75                  //TVAR_wbt_pBaseCcms[33]
+	0x0F1200DF, //00FB                  //TVAR_wbt_pBaseCcms[34]
+	0x0F1200FF, //00F0                  //TVAR_wbt_pBaseCcms[35]
+
+	0x0F1201C0, //01D4                  //TVAR_wbt_pBaseCcms[36]
+	0x0F12FFCB, //FFB2                  //TVAR_wbt_pBaseCcms[37]
+	0x0F12FFE4, //FFEE                  //TVAR_wbt_pBaseCcms[38]
+	0x0F12FF43, //FF47                  //TVAR_wbt_pBaseCcms[39]
+	0x0F12011D, //012C                  //TVAR_wbt_pBaseCcms[40]
+	0x0F12FF6B, //FF5C                  //TVAR_wbt_pBaseCcms[41]
+	0x0F12FFDA, //FFCE                  //TVAR_wbt_pBaseCcms[42]
+	0x0F12FFD1, //FFD6                  //TVAR_wbt_pBaseCcms[43]
+	0x0F120156, //0162                  //TVAR_wbt_pBaseCcms[44]
+	0x0F1200F7, //011D                  //TVAR_wbt_pBaseCcms[45]
+	0x0F1200D1, //00C6                  //TVAR_wbt_pBaseCcms[46]
+	0x0F12FEE9, //FED2                  //TVAR_wbt_pBaseCcms[47]
+	0x0F1200CD, //00C8                  //TVAR_wbt_pBaseCcms[48]
+	0x0F12FF5E, //FF56                  //TVAR_wbt_pBaseCcms[49]
+	0x0F120128, //0139                  //TVAR_wbt_pBaseCcms[50]
+	0x0F12FF7E, //FF75                  //TVAR_wbt_pBaseCcms[51]
+	0x0F1200EC, //00FB                  //TVAR_wbt_pBaseCcms[52]
+	0x0F1200F2, //00F0                  //TVAR_wbt_pBaseCcms[53]
+
+	0x0F1201C0, //01D4                  //TVAR_wbt_pBaseCcms[54]
+	0x0F12FFCB, //FFB2                  //TVAR_wbt_pBaseCcms[55]
+	0x0F12FFE4, //FFEE                  //TVAR_wbt_pBaseCcms[56]
+	0x0F12FF43, //FF47                  //TVAR_wbt_pBaseCcms[57]
+	0x0F12011D, //012C                  //TVAR_wbt_pBaseCcms[58]
+	0x0F12FF6B, //FF5C                  //TVAR_wbt_pBaseCcms[59]
+	0x0F12FFDA, //FFCE                  //TVAR_wbt_pBaseCcms[60]
+	0x0F12FFD1, //FFD6                  //TVAR_wbt_pBaseCcms[61]
+	0x0F120156, //0162                  //TVAR_wbt_pBaseCcms[62]
+	0x0F1200F7, //011D                  //TVAR_wbt_pBaseCcms[63]
+	0x0F1200D1, //00C6                  //TVAR_wbt_pBaseCcms[64]
+	0x0F12FEE9, //FED2                  //TVAR_wbt_pBaseCcms[65]
+	0x0F1200CD, //00C8                  //TVAR_wbt_pBaseCcms[66]
+	0x0F12FF5E, //FF56                  //TVAR_wbt_pBaseCcms[67]
+	0x0F120128, //0139                  //TVAR_wbt_pBaseCcms[68]
+	0x0F12FF7E, //FF75                  //TVAR_wbt_pBaseCcms[69]
+	0x0F1200EC, //00FB                  //TVAR_wbt_pBaseCcms[70]
+	0x0F1200F2, //00F0                  //TVAR_wbt_pBaseCcms[71]
+
+	0x0F120111, //0114                            //TVAR_wbt_pBaseCcms[72]
+	0x0F12FFB5, //FFAC                  //TVAR_wbt_pBaseCcms[73]
+	0x0F120000, //FFFB                  //TVAR_wbt_pBaseCcms[74]
+	0x0F12FF26, //FF1D                  //TVAR_wbt_pBaseCcms[75]
+	0x0F120179, //0182                  //TVAR_wbt_pBaseCcms[76]
+	0x0F12FF4B, //FF40                  //TVAR_wbt_pBaseCcms[77]
+	0x0F12FFE1, //FFD8                  //TVAR_wbt_pBaseCcms[78]
+	0x0F12FFF0, //FFE9                  //TVAR_wbt_pBaseCcms[79]
+	0x0F120151, //0155                  //TVAR_wbt_pBaseCcms[80]
+	0x0F120099, //009A                  //TVAR_wbt_pBaseCcms[81]
+	0x0F12008C, //008B                  //TVAR_wbt_pBaseCcms[82]
+	0x0F12FF28, //FF1C                  //TVAR_wbt_pBaseCcms[83]
+	0x0F1200C4, //00C2                  //TVAR_wbt_pBaseCcms[84]
+	0x0F12FF7A, //FF6E                  //TVAR_wbt_pBaseCcms[85]
+	0x0F120134, //0137                  //TVAR_wbt_pBaseCcms[86]
+	0x0F12FF85, //FF79                  //TVAR_wbt_pBaseCcms[87]
+	0x0F120105, //0106                  //TVAR_wbt_pBaseCcms[88]
+	0x0F1200F2, //00F1                  //TVAR_wbt_pBaseCcms[89]
+
+	0x0F120111, //0114                            //TVAR_wbt_pBaseCcms[90]
+	0x0F12FFB5, //FFAC                  //TVAR_wbt_pBaseCcms[91]
+	0x0F120000, //FFFB                  //TVAR_wbt_pBaseCcms[92]
+	0x0F12FF26, //FF1D                  //TVAR_wbt_pBaseCcms[93]
+	0x0F120179, //0182                  //TVAR_wbt_pBaseCcms[94]
+	0x0F12FF4B, //FF40                  //TVAR_wbt_pBaseCcms[95]
+	0x0F12FFE1, //FFD8                  //TVAR_wbt_pBaseCcms[96]
+	0x0F12FFF0, //FFE9                  //TVAR_wbt_pBaseCcms[97]
+	0x0F120151, //0155                  //TVAR_wbt_pBaseCcms[98]
+	0x0F120099, //009A                  //TVAR_wbt_pBaseCcms[99]
+	0x0F12008C, //008B                  //TVAR_wbt_pBaseCcms[100]
+	0x0F12FF28, //FF1C                  //TVAR_wbt_pBaseCcms[101]
+	0x0F1200C4, //00C2                  //TVAR_wbt_pBaseCcms[102]
+	0x0F12FF7A, //FF6E                  //TVAR_wbt_pBaseCcms[103]
+	0x0F120134, //0137                  //TVAR_wbt_pBaseCcms[104]
+	0x0F12FF85, //FF79                  //TVAR_wbt_pBaseCcms[105]
+	0x0F120105, //0106                  //TVAR_wbt_pBaseCcms[106]
+	0x0F1200F2, //00F1                  //TVAR_wbt_pBaseCcms[107]
+	//	param_end	TVAR_wbt_pBasecms
+
+
+	0x002A07CC,
+	0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+	0x0F127000,
+
+	//	param_start	TVAR_wbt_pOutdoorCcm
+	0x002A40D8,
+	0x0F1201BE, //0205                  //01F8                  //TVAR_wbt_pOutdoorCcm[0]
+	0x0F12FFE4, //FF96                  //FFAF                  //TVAR_wbt_pOutdoorCcm[1]
+	0x0F120000, //FFDF                  //FFD3                  //TVAR_wbt_pOutdoorCcm[2]
+	0x0F12FEF9, //FEC8                  //FEC4                  //TVAR_wbt_pOutdoorCcm[3]
+	0x0F120149, //01A4                  //0191                  //TVAR_wbt_pOutdoorCcm[4]
+	0x0F12FF70, //FF1C                  //FF33                  //TVAR_wbt_pOutdoorCcm[5]
+	0x0F12003C, //FFF7                  //FFED                  //TVAR_wbt_pOutdoorCcm[6]
+	0x0F120023, //000C                  //0017                  //TVAR_wbt_pOutdoorCcm[7]
+	0x0F1201DD, //0211                  //0210                  //TVAR_wbt_pOutdoorCcm[8]
+	0x0F1200D4, //0107                  //00E3                  //TVAR_wbt_pOutdoorCcm[9]
+	0x0F1200F8, //00F3                  //0107                  //TVAR_wbt_pOutdoorCcm[10]
+	0x0F12FF74, //FF1F                  //FF2F                  //TVAR_wbt_pOutdoorCcm[11]
+	0x0F120212, //0220                  //0220                  //TVAR_wbt_pOutdoorCcm[12]
+	0x0F120039, //FFE7                  //FFE7                  //TVAR_wbt_pOutdoorCcm[13]
+	0x0F120184, //01A1                  //01A1                  //TVAR_wbt_pOutdoorCcm[14]
+	0x0F12FF28, //FEC7                  //FEC8                  //TVAR_wbt_pOutdoorCcm[15]
+	0x0F120133, //016D                  //017D                  //TVAR_wbt_pOutdoorCcm[16]
+	0x0F120153, //0153                  //0142                  //TVAR_wbt_pOutdoorCcm[17]
+	//	param_end	TVAR_wbt_pOutdoorCcm
+
+	0x002A2A64,
+	0x0F120001, //#MVAR_AAIO_bFIT
+	0x002A2A68,
+	0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+	0x002A2A3C,
+	0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+	//===================================================================
+	// AFIT
+	//===================================================================
+
+	//	param_start	afit_uNoiseIndInDoor
+	0x002A085C,
+	0x0F12004A, //0049                  //#afit_uNoiseIndInDoor_0_
+	0x0F12004E, //005F                  //#afit_uNoiseIndInDoor_1_
+	0x0F1200CB, //00CB                  //#afit_uNoiseIndInDoor_2_
+	0x0F1201C0, //01E0                  //#afit_uNoiseIndInDoor_3_
+	0x0F120200, //0220                  //#afit_uNoiseIndInDoor_4_
+
+
+	0x002A08C0,
+	0x0F120030, //0007         //700008C0         //AFIT16_BRIGHTNESS
+	0x0F120000, //0000         //700008C2                    //AFIT16_CONTRAST
+	0x0F120010, //0000         //700008C4                    //AFIT16_SATURATION
+	0x0F120000, //0000         //700008C6                    //AFIT16_SHARP_BLUR
+	0x0F120000, //0000         //700008C8                    //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1         //700008CA                    //AFIT16_sddd8a_edge_high
+	0x0F120000, //0000         //700008CC
+	0x0F1203FF, //03FF         //700008CE                    //AFIT16_Demosaicing_iSatVal
+	0x0F12009C, //009C         //700008D0                    //AFIT16_Sharpening_iReduceEdgeThre
+	0x0F12017C, //017C         //700008D2                    //AFIT16_demsharpmix1_iRGBOffset
+	0x0F1203FF, //03FF         //700008D4                    //AFIT16_demsharpmix1_iDemClamp
+	0x0F12000C, //000C         //700008D6                    //AFIT16_demsharpmix1_iLowThreshold
+	0x0F120010, //0010         //700008D8                    //AFIT16_demsharpmix1_iHighThreshol
+	0x0F12012C, //012C         //700008DA                    //AFIT16_demsharpmix1_iLowBright
+	0x0F1203E8, //03E8         //700008DC                    //AFIT16_demsharpmix1_iHighBright
+	0x0F120046, //0046         //700008DE                    //AFIT16_demsharpmix1_iLowSat
+	0x0F12005A, //005A         //700008E0                    //AFIT16_demsharpmix1_iHighSat
+	0x0F120070, //0070         //700008E2                    //AFIT16_demsharpmix1_iTune
+	0x0F120001, //0010         //700008E4         //AFIT16_demsharpmix1_iHystThLow
+	0x0F120000, //0010         //700008E6         //AFIT16_demsharpmix1_iHystThHigh
+	0x0F120320, //01F4         //700008E8         //AFIT16_demsharpmix1_iHystCenter
+	0x0F12006E, //003C         //700008EA                    //AFIT16_Sharpening_iLowSharpClamp
+	0x0F120014, //0008         //700008EC                    //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12006E, //003C         //700008EE                    //AFIT16_Sharpening_iLowSharpClamp_
+	0x0F120014, //001E         //700008F0                    //AFIT16_Sharpening_iHighSharpClamp
+	0x0F12006E, //003C         //700008F2                    //AFIT16_Sharpening_iLowSharpClamp_
+	0x0F120014, //001E         //700008F4                    //AFIT16_Sharpening_iHighSharpClamp
+	0x0F120A24, //0A24         //700008F6                    //AFIT8_sddd8a_edge_low [7:0] AFIT8
+	0x0F121701, //1701         //700008F8                    //AFIT8_sddd8a_repl_force [7:0] AFI
+	0x0F120229, //0229         //700008FA                    //AFIT8_sddd8a_sat_thr[7:0] AFIT8_s
+	0x0F121403, //1403         //700008FC                    //AFIT8_sddd8a_sat_noise[7:0] AFIT8
+	0x0F120004, //0004         //700008FE                    //AFIT8_sddd8a_iHotThreshHigh[7:0]
+	0x0F120300, //0300         //70000900                    //AFIT8_sddd8a_iColdThreshHigh[7:0]
+	0x0F120000, //0000         //70000902                    //AFIT8_sddd8a_AddNoisePower1[7:0]
+	0x0F1202FF, //02FF         //70000904                    //AFIT8_sddd8a_iSatSat[7:0] AFIT8_s
+	0x0F1205E8, //09E8         //70000906                    //AFIT8_sddd8a_iRadialLimit [7:0] A
+	0x0F121414, //1414         //70000908                    //AFIT8_sddd8a_iLowMaxSlopeAllowed
+	0x0F120301, //0301         //7000090A                    //AFIT8_sddd8a_iLowSlopeThresh[7:0]
+	0x0F120007, //0007         //7000090C                    //AFIT8_sddd8a_iSquaresRounding [7:
+	0x0F122000, //4000         //7000090E
+	0x0F125003, //7803         //70000910
+	0x0F123228, //3C50         //70000912
+	0x0F120032, //003C         //70000914
+	0x0F121E80, //1E80         //70000916                    //AFIT8_Demosaicing_iCentGrad[7:0]
+	0x0F121E08, //1E08         //70000918                    //AFIT8_Demosaicing_iDecisionThresh
+	0x0F12000A, //000A         //7000091A                    //AFIT8_Demosaicing_iEnhThresh[7:0]
+	0x0F120000, //0000         //7000091C                    //AFIT8_Demosaicing_iGBDenoiseVal[7
+	0x0F12270A, //120A         //7000091E                    //AFIT8_Demosaicing_iDFD_ReduceCoef
+	0x0F120010, //0F00         //70000920                    //AFIT8_Sharpening_iMShThresh[7:0]
+	0x0F120200, //0200         //70000922                    //AFIT8_Sharpening_iWShThresh[7:0]
+	0x0F12FF00, //FF00         //70000924                    //AFIT8_Sharpening_iReduceNegative[
+	0x0F120200, //0200         //70000926                    //AFIT8_demsharpmix1_iRGBMultiplier
+	0x0F121B11, //1B11         //70000928                    //AFIT8_demsharpmix1_iBCoeff[7:0] A
+	0x0F120000, //0000         //7000092A                    //AFIT8_demsharpmix1_iWideMult[7:0]
+	0x0F120009, //0009         //7000092C                    //AFIT8_demsharpmix1_iHystFalloff[7
+	0x0F120406, //0406         //7000092E                    //AFIT8_demsharpmix1_iHystWidth[7:0
+	0x0F120605, //0605         //70000930                    //AFIT8_demsharpmix1_iHystFallHigh[
+	0x0F120307, //0307         //70000932
+	0x0F120609, //0609         //70000934
+	0x0F122C07, //2C07         //70000936
+	0x0F12142C, //142C         //70000938
+	0x0F120518, //0718         //7000093A         //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+	0x0F128005, //8007         //7000093C         //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShading
+	0x0F120594, //0880         //7000093E                    //AFIT8_RGBGamma2_iLinearity [7:0]
+	0x0F120080, //0B50         //70000940                    //AFIT8_ccm_oscar_iSaturation[7:0]
+	0x0F120080, //0080         //70000942                    //AFIT8_RGB2YUV_iRGBGain [7:0]   AF
+	0x0F120101, //0101         //70000944                    //AFIT8_sddd8a_iClustThresh_H [7:0]
+	0x0F120707, //0707         //70000946                    //AFIT8_sddd8a_iClustMulT_H [7:0]
+	0x0F124B01, //4601         //70000948                    //AFIT8_sddd8a_nClustLevel_H [7:0]
+	0x0F12314B, //C844         //7000094A                    //AFIT8_sddd8a_DispTH_High [7:0]
+	0x0F125038, //50C8         //7000094C                    //AFIT8_sddd8a_iDenThreshHigh[7:0]
+	0x0F120500, //0500         //7000094E                    //AFIT8_Demosaicing_iEdgeDesatThrLo
+	0x0F120903, //0003         //70000950                    //AFIT8_Demosaicing_iEdgeDesatLimit
+	0x0F121003, //1C01         //70000952                    //AFIT8_Demosaicing_iDemSharpenHigh
+	0x0F12071E, //0714         //70000954                    //AFIT8_Demosaicing_iDemShLowLimit
+	0x0F121432, //1464         //70000956                    //AFIT8_Demosaicing_iDemBlurLow[7:0
+	0x0F125F01, //5A04         //70000958                    //AFIT8_Demosaicing_iDemBlurRange[7
+	0x0F122829, //3C1E         //7000095A                    //AFIT8_Sharpening_iHighSharpPower[
+	0x0F12200F, //400F         //7000095C                    //AFIT8_Sharpening_iHighShDenoise [
+	0x0F120204, //0204         //7000095E                    //AFIT8_Sharpening_iReduceEdgeSlope
+	0x0F120103, //1403         //70000960                    //AFIT8_demsharpmix1_iNarrFiltReduc
+	0x0F120701, //0114         //70000962                    //AFIT8_sddd8a_iClustThresh_C_Bin [
+	0x0F120101, //0101         //70000964                    //AFIT8_sddd8a_iClustMulT_C_Bin [7:
+	0x0F124B4B, //4446         //70000966                    //AFIT8_sddd8a_DispTH_Low_Bin [7:0]
+	0x0F124449, //646E         //70000968                    //AFIT8_sddd8a_iDenThreshLow_Bin [7
+	0x0F120050, //0028         //7000096A                    //AFIT8_Demosaicing_iEdgeDesat_Bin[
+	0x0F120305, //030A         //7000096C                    //AFIT8_Demosaicing_iEdgeDesatThrHi
+	0x0F120346, //0000         //7000096E                    //AFIT8_Demosaicing_iDemSharpenLow_
+	0x0F121E0D, //141E         //70000970                    //AFIT8_Demosaicing_iDemSharpThresh
+	0x0F123207, //FF07         //70000972                    //AFIT8_Demosaicing_iDespeckleForDe
+	0x0F120114, //0432         //70000974                    //AFIT8_Demosaicing_iDemBlurHigh_Bi
+	0x0F121E6A, //0000         //70000976                    //AFIT8_Sharpening_iLowSharpPower_B
+	0x0F120F28, //0F0F         //70000978                    //AFIT8_Sharpening_iLowShDenoise_Bi
+	0x0F120420, //0440         //7000097A                    //AFIT8_Sharpening_iReduceEdgeMinMu
+	0x0F120302, //0302         //7000097C                    //AFIT8_demsharpmix1_iWideFiltReduc
+	0x0F121E1E, //1414         //7000097E                    //AFIT8_sddd8a_iClustThresh_H_sBin[
+	0x0F120101, //0101         //70000980                    //AFIT8_sddd8a_iClustMulT_H_sBin [7
+	0x0F124B01, //4601         //70000982                    //AFIT8_sddd8a_nClustLevel_H_sBin [
+	0x0F12494B, //6E44         //70000984                    //AFIT8_sddd8a_DispTH_High_sBin [7:
+	0x0F125044, //2864         //70000986                    //AFIT8_sddd8a_iDenThreshHigh_sBin[
+	0x0F120500, //0A00         //70000988                    //AFIT8_Demosaicing_iEdgeDesatThrLo
+	0x0F124603, //0003         //7000098A                    //AFIT8_Demosaicing_iEdgeDesatLimit
+	0x0F120D03, //1E00         //7000098C                    //AFIT8_Demosaicing_iDemSharpenHigh
+	0x0F12071E, //0714         //7000098E                    //AFIT8_Demosaicing_iDemShLowLimit_
+	0x0F121432, //32FF         //70000990                    //AFIT8_Demosaicing_iDemBlurLow_sBi
+	0x0F126A01, //0004         //70000992                    //AFIT8_Demosaicing_iDemBlurRange_s
+	0x0F12281E, //0F00         //70000994                    //AFIT8_Sharpening_iHighSharpPower_
+	0x0F12200F, //400F         //70000996                    //AFIT8_Sharpening_iHighShDenoise_s
+	0x0F120204, //0204         //70000998                    //AFIT8_Sharpening_iReduceEdgeSlope
+	0x0F120003, //0003         //7000099A                    //AFIT8_demsharpmix1_iNarrFiltReduc
+	0x0F120001, //0001         //7000099C
+	0x0F120030, //0000                  //7000099E                  //AFIT16_BRIGHTNESS
+	0x0F120000, //0000                  //700009A0                             //AFIT16_CONTRAST
+	0x0F120010, //0000                  //700009A2                             //AFIT16_SATURATI
+	0x0F120000, //0000                  //700009A4                             //AFIT16_SHARP_BL
+	0x0F120000, //0000                  //700009A6                             //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1                  //700009A8                             //AFIT16_sddd8a_e
+	0x0F120000, //0000                  //700009AA
+	0x0F1203FF, //03FF                  //700009AC                             //AFIT16_Demosaic
+	0x0F12009C, //009C                  //700009AE                             //AFIT16_Sharpeni
+	0x0F12017C, //017C                  //700009B0                             //AFIT16_demsharp
+	0x0F1203FF, //03FF                  //700009B2                             //AFIT16_demsharp
+	0x0F12000C, //000C                  //700009B4                             //AFIT16_demsharp
+	0x0F120010, //0010                  //700009B6                             //AFIT16_demsharp
+	0x0F12012C, //012C                  //700009B8                             //AFIT16_demsharp
+	0x0F1203E8, //03E8                  //700009BA                             //AFIT16_demsharp
+	0x0F120046, //0046                  //700009BC                             //AFIT16_demsharp
+	0x0F12005A, //005A                  //700009BE                             //AFIT16_demsharp
+	0x0F120070, //0070                  //700009C0                             //AFIT16_demsharp
+	0x0F120001, //0001                  //700009C2                  //AFIT16_demsharpmix1_iHystT
+	0x0F120000, //0000                  //700009C4                  //AFIT16_demsharpmix1_iHystT
+	0x0F120320, //0320                  //700009C6                  //AFIT16_demsharpmix1_iHystC
+	0x0F12006E, //006E                  //700009C8                             //AFIT16_Sharpeni
+	0x0F120014, //0014                  //700009CA                             //AFIT16_Sharpeni
+	0x0F12006E, //003C                  //700009CC                             //AFIT16_Sharpeni
+	0x0F120014, //001E                  //700009CE                             //AFIT16_Sharpeni
+	0x0F12006E, //003C                  //700009D0                             //AFIT16_Sharpeni
+	0x0F120014, //001E                  //700009D2                             //AFIT16_Sharpeni
+	0x0F120A24, //0A24                  //700009D4                             //AFIT8_sddd8a_ed
+	0x0F121701, //1701                  //700009D6                             //AFIT8_sddd8a_re
+	0x0F120229, //0229                  //700009D8                             //AFIT8_sddd8a_sa
+	0x0F121403, //1403                  //700009DA                             //AFIT8_sddd8a_sa
+	0x0F120004, //0004                  //700009DC                             //AFIT8_sddd8a_iH
+	0x0F120300, //0300                  //700009DE                             //AFIT8_sddd8a_iC
+	0x0F120000, //0000                  //700009E0                             //AFIT8_sddd8a_Ad
+	0x0F1202FF, //02FF                  //700009E2                             //AFIT8_sddd8a_iS
+	0x0F1205E8, //05E8                  //700009E4                             //AFIT8_sddd8a_iR
+	0x0F121414, //1414                  //700009E6                             //AFIT8_sddd8a_iL
+	0x0F120301, //0301                  //700009E8                             //AFIT8_sddd8a_iL
+	0x0F120007, //0007                  //700009EA                             //AFIT8_sddd8a_iS
+	0x0F122000, //2000                  //700009EC
+	0x0F125003, //5003                  //700009EE
+	0x0F123228, //3228                  //700009F0
+	0x0F120032, //0032                  //700009F2
+	0x0F121E80, //1E80                  //700009F4                             //AFIT8_Demosaici
+	0x0F121E08, //1E08                  //700009F6                             //AFIT8_Demosaici
+	0x0F12000A, //000A                  //700009F8                             //AFIT8_Demosaici
+	0x0F120000, //0000                  //700009FA                             //AFIT8_Demosaici
+	0x0F12270A, //120A                  //700009FC                             //AFIT8_Demosaici
+	0x0F120010, //1400                  //700009FE                             //AFIT8_Sharpenin
+	0x0F120200, //0200                  //70000A00                             //AFIT8_Sharpenin
+	0x0F12FF00, //FF00                  //70000A02                             //AFIT8_Sharpenin
+	0x0F120200, //0200                  //70000A04                             //AFIT8_demsharpm
+	0x0F121B11, //1B11                  //70000A06                             //AFIT8_demsharpm
+	0x0F120000, //0000                  //70000A08                             //AFIT8_demsharpm
+	0x0F120009, //0009                  //70000A0A                             //AFIT8_demsharpm
+	0x0F120406, //0406                  //70000A0C                             //AFIT8_demsharpm
+	0x0F120605, //0605                  //70000A0E                             //AFIT8_demsharpm
+	0x0F120307, //0307                  //70000A10
+	0x0F120609, //0609                  //70000A12
+	0x0F122C07, //2C07                  //70000A14
+	0x0F12142C, //142C                  //70000A16
+	0x0F120518, //0518                  //70000A18                  //[15:8]iUVNRStrengthL [7:0]
+	0x0F128005, //8005                  //70000A1A                  //[7:0]iUVNRStrengthH AFIT8_
+	0x0F120594, //0580                  //70000A1C                             //AFIT8_RGBGamma2
+	0x0F120080, //0080                  //70000A1E                             //AFIT8_ccm_oscar
+	0x0F120080, //0080                  //70000A20                             //AFIT8_RGB2YUV_i
+	0x0F120101, //0101                  //70000A22                             //AFIT8_sddd8a_iC
+	0x0F120707, //0707                  //70000A24                             //AFIT8_sddd8a_iC
+	0x0F124B01, //4B01                  //70000A26                             //AFIT8_sddd8a_nC
+	0x0F12314B, //444B 494B                  //70000A28                             //AFIT8_sddd
+	0x0F125038, //503C 5044                  //70000A2A                             //AFIT8_sddd
+	0x0F120500, //0500                  //70000A2C                             //AFIT8_Demosaici
+	0x0F120903, //0503                  //70000A2E                             //AFIT8_Demosaici
+	0x0F121003, //0D02                  //70000A30                             //AFIT8_Demosaici
+	0x0F12071E, //071E                  //70000A32                             //AFIT8_Demosaici
+	0x0F121432, //1432                  //70000A34                             //AFIT8_Demosaici
+	0x0F125F01, //5A01                  //70000A36                             //AFIT8_Demosaici
+	0x0F122829, //281E                  //70000A38                             //AFIT8_Sharpenin
+	0x0F12200F, //200F                  //70000A3A                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000A3C                             //AFIT8_Sharpenin
+	0x0F120103, //1E03                  //70000A3E                             //AFIT8_demsharpm
+	0x0F120701, //011E                  //70000A40                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000A42                             //AFIT8_sddd8a_iC
+	0x0F124B4B, //3A3C                  //70000A44                             //AFIT8_sddd8a_Di
+	0x0F124449, //585A                  //70000A46                             //AFIT8_sddd8a_iD
+	0x0F120050, //0028                  //70000A48                             //AFIT8_Demosaici
+	0x0F120305, //030A                  //70000A4A                             //AFIT8_Demosaici
+	0x0F120346, //0000                  //70000A4C                             //AFIT8_Demosaici
+	0x0F121E0D, //141E                  //70000A4E                             //AFIT8_Demosaici
+	0x0F123207, //FF07                  //70000A50                             //AFIT8_Demosaici
+	0x0F120114, //0432                  //70000A52                             //AFIT8_Demosaici
+	0x0F121E6A, //0000                  //70000A54                             //AFIT8_Sharpenin
+	0x0F120F28, //0F0F                  //70000A56                             //AFIT8_Sharpenin
+	0x0F120420, //0440                  //70000A58                             //AFIT8_Sharpenin
+	0x0F120302, //0302                  //70000A5A                             //AFIT8_demsharpm
+	0x0F121E1E, //1E1E                  //70000A5C                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000A5E                             //AFIT8_sddd8a_iC
+	0x0F124B01, //3C01                  //70000A60                             //AFIT8_sddd8a_nC
+	0x0F12494B, //5A3A                  //70000A62                             //AFIT8_sddd8a_Di
+	0x0F125044, //2858                  //70000A64                             //AFIT8_sddd8a_iD
+	0x0F120500, //0A00                  //70000A66                             //AFIT8_Demosaici
+	0x0F124603, //0003                  //70000A68                             //AFIT8_Demosaici
+	0x0F120D03, //1E00                  //70000A6A                             //AFIT8_Demosaici
+	0x0F12071E, //0714                  //70000A6C                             //AFIT8_Demosaici
+	0x0F121432, //32FF                  //70000A6E                             //AFIT8_Demosaici
+	0x0F126A01, //0004                  //70000A70                             //AFIT8_Demosaici
+	0x0F12281E, //0F00                  //70000A72                             //AFIT8_Sharpenin
+	0x0F12200F, //400F                  //70000A74                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000A76                             //AFIT8_Sharpenin
+	0x0F120003, //0003                  //70000A78                             //AFIT8_demsharpm
+	0x0F120001, //0001                  //70000A7A
+	0x0F120000, //0000                  //70000A7C                  //AFIT16_BRIGHTNESS
+	0x0F120000, //0000                  //70000A7E                             //AFIT16_CONTRAST
+	0x0F120000, //0000                  //70000A80                             //AFIT16_SATURATI
+	0x0F120000, //0000                  //70000A82                             //AFIT16_SHARP_BL
+	0x0F120000, //0000                  //70000A84                             //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1                  //70000A86                             //AFIT16_sddd8a_e
+	0x0F120000, //0000                  //70000A88
+	0x0F1203FF, //03FF                  //70000A8A                             //AFIT16_Demosaic
+	0x0F12009E, //009E                  //70000A8C                             //AFIT16_Sharpeni
+	0x0F12017C, //017C                  //70000A8E                             //AFIT16_demsharp
+	0x0F1203FF, //03FF                  //70000A90                             //AFIT16_demsharp
+	0x0F12000C, //000C                  //70000A92                             //AFIT16_demsharp
+	0x0F120010, //0010                  //70000A94                             //AFIT16_demsharp
+	0x0F12012C, //012C                  //70000A96                             //AFIT16_demsharp
+	0x0F1203E8, //03E8                  //70000A98                             //AFIT16_demsharp
+	0x0F120046, //0046                  //70000A9A                             //AFIT16_demsharp
+	0x0F12005A, //005A                  //70000A9C                             //AFIT16_demsharp
+	0x0F120070, //0070                  //70000A9E                             //AFIT16_demsharp
+	0x0F120001, //0001                  //70000AA0                  //AFIT16_demsharpmix1_iHystT
+	0x0F120000, //0000                  //70000AA2                  //AFIT16_demsharpmix1_iHystT
+	0x0F120320, //0320                  //70000AA4                  //AFIT16_demsharpmix1_iHystC
+	0x0F12008C, //008C                  //70000AA6                             //AFIT16_Sharpeni
+	0x0F120014, //0014                  //70000AA8                             //AFIT16_Sharpeni
+	0x0F12008C, //003C                  //70000AAA                             //AFIT16_Sharpeni
+	0x0F120014, //001E                  //70000AAC                             //AFIT16_Sharpeni
+	0x0F12008C, //003C                  //70000AAE                             //AFIT16_Sharpeni
+	0x0F120014, //001E                  //70000AB0                             //AFIT16_Sharpeni
+	0x0F120A24, //0A24                  //70000AB2                             //AFIT8_sddd8a_ed
+	0x0F121701, //1701                  //70000AB4                             //AFIT8_sddd8a_re
+	0x0F120229, //0229                  //70000AB6                             //AFIT8_sddd8a_sa
+	0x0F121403, //1403                  //70000AB8                             //AFIT8_sddd8a_sa
+	0x0F120004, //0004                  //70000ABA                             //AFIT8_sddd8a_iH
+	0x0F120300, //0300                  //70000ABC                             //AFIT8_sddd8a_iC
+	0x0F120000, //0000                  //70000ABE                             //AFIT8_sddd8a_Ad
+	0x0F1202FF, //02FF                  //70000AC0                             //AFIT8_sddd8a_iS
+	0x0F1205DE, //05DE                  //70000AC2                             //AFIT8_sddd8a_iR
+	0x0F121414, //1414                  //70000AC4                             //AFIT8_sddd8a_iL
+	0x0F120301, //0301                  //70000AC6                             //AFIT8_sddd8a_iL
+	0x0F120007, //0007                  //70000AC8                             //AFIT8_sddd8a_iS
+	0x0F121000, //1000                  //70000ACA
+	0x0F122803, //2803                  //70000ACC
+	0x0F12261E, //261E                  //70000ACE
+	0x0F120026, //0026                  //70000AD0
+	0x0F121E80, //1E80                  //70000AD2                             //AFIT8_Demosaici
+	0x0F121E08, //1E08                  //70000AD4                             //AFIT8_Demosaici
+	0x0F12010A, //010A                  //70000AD6                             //AFIT8_Demosaici
+	0x0F120001, //0001                  //70000AD8                             //AFIT8_Demosaici
+	0x0F124C0A, //3C0A                  //70000ADA                             //AFIT8_Demosaici
+	0x0F122B12, //2300                  //70000ADC                             //AFIT8_Sharpenin
+	0x0F120207, //0200                  //70000ADE                             //AFIT8_Sharpenin
+	0x0F12FF00, //FF00                  //70000AE0                             //AFIT8_Sharpenin
+	0x0F120200, //0200                  //70000AE2                             //AFIT8_demsharpm
+	0x0F121B11, //1B11                  //70000AE4                             //AFIT8_demsharpm
+	0x0F120000, //0000                  //70000AE6                             //AFIT8_demsharpm
+	0x0F120009, //0009                  //70000AE8                             //AFIT8_demsharpm
+	0x0F120406, //0406                  //70000AEA                             //AFIT8_demsharpm
+	0x0F120605, //0605                  //70000AEC                             //AFIT8_demsharpm
+	0x0F120307, //0307                  //70000AEE
+	0x0F120609, //0609                  //70000AF0
+	0x0F121C07, //1C07                  //70000AF2
+	0x0F121014, //1014                  //70000AF4
+	0x0F120510, //0510                  //70000AF6                  //[15:8]iUVNRStrengthL [7:0]
+	0x0F128005, //8005                  //70000AF8                  //[7:0]iUVNRStrengthH AFIT8_
+	0x0F120080, //0080                  //70000AFA                             //AFIT8_RGBGamma2
+	0x0F120080, //0080                  //70000AFC                             //AFIT8_ccm_oscar
+	0x0F120080, //0080                  //70000AFE                             //AFIT8_RGB2YUV_i
+	0x0F120101, //0101                  //70000B00                             //AFIT8_sddd8a_iC
+	0x0F120707, //0707                  //70000B02                             //AFIT8_sddd8a_iC
+	0x0F124B01, //4B01                  //70000B04                             //AFIT8_sddd8a_nC
+	0x0F12144B, //2A4B                  //70000B06                             //AFIT8_sddd8a_Di
+	0x0F125014, //5020                  //70000B08                             //AFIT8_sddd8a_iD
+	0x0F120500, //0500                  //70000B0A                             //AFIT8_Demosaici
+	0x0F121B03, //1C03                  //70000B0C                             //AFIT8_Demosaici
+	0x0F123003, //0D0C                  //70000B0E                             //AFIT8_Demosaici
+	0x0F120823, //0823                  //70000B10                             //AFIT8_Demosaici
+	0x0F121428, //1428                  //70000B12                             //AFIT8_Demosaici
+	0x0F128601, //6401                  //70000B14                             //AFIT8_Demosaici
+	0x0F12283E, //282D                  //70000B16                             //AFIT8_Sharpenin
+	0x0F122012, //2012                  //70000B18                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000B1A                             //AFIT8_Sharpenin
+	0x0F120103, //2803                  //70000B1C                             //AFIT8_demsharpm
+	0x0F120701, //0128                  //70000B1E                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000B20                             //AFIT8_sddd8a_iC
+	0x0F124B4B, //2224                  //70000B22                             //AFIT8_sddd8a_Di
+	0x0F120000, //3236                  //70000B24                             //AFIT8_sddd8a_iD
+	0x0F120050, //0028                  //70000B26                             //AFIT8_Demosaici
+	0x0F120305, //030A                  //70000B28                             //AFIT8_Demosaici
+	0x0F120C5C, //0410                  //70000B2A                             //AFIT8_Demosaici
+	0x0F12230D, //141E                  //70000B2C                             //AFIT8_Demosaici
+	0x0F122807, //FF07                  //70000B2E                             //AFIT8_Demosaici
+	0x0F120114, //0432                  //70000B30                             //AFIT8_Demosaici
+	0x0F122D74, //4050                  //70000B32                             //AFIT8_Sharpenin
+	0x0F120908, //0F0F                  //70000B34                             //AFIT8_Sharpenin
+	0x0F120420, //0440                  //70000B36                             //AFIT8_Sharpenin
+	0x0F120302, //0302                  //70000B38                             //AFIT8_demsharpm
+	0x0F122828, //2828                  //70000B3A                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000B3C                             //AFIT8_sddd8a_iC
+	0x0F124B01, //2401                  //70000B3E                             //AFIT8_sddd8a_nC
+	0x0F12004B, //3622                  //70000B40                             //AFIT8_sddd8a_Di
+	0x0F125000, //2832                  //70000B42                             //AFIT8_sddd8a_iD
+	0x0F120500, //0A00                  //70000B44                             //AFIT8_Demosaici
+	0x0F125C03, //1003                  //70000B46                             //AFIT8_Demosaici
+	0x0F120D0C, //1E04                  //70000B48                             //AFIT8_Demosaici
+	0x0F120823, //0714                  //70000B4A                             //AFIT8_Demosaici
+	0x0F121428, //32FF                  //70000B4C                             //AFIT8_Demosaici
+	0x0F127401, //5004                  //70000B4E                             //AFIT8_Demosaici
+	0x0F12082D, //0F40                  //70000B50                             //AFIT8_Sharpenin
+	0x0F122009, //400F                  //70000B52                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000B54                             //AFIT8_Sharpenin
+	0x0F120003, //0003                  //70000B56                             //AFIT8_demsharpm
+	0x0F120001, //0001                  //70000B58
+	0x0F120000, //0000                  //70000B5A                  //AFIT16_BRIGHTNESS
+	0x0F120000, //0000                  //70000B5C                             //AFIT16_CONTRAST
+	0x0F120000, //0000                  //70000B5E                             //AFIT16_SATURATI
+	0x0F120000, //0000                  //70000B60                             //AFIT16_SHARP_BL
+	0x0F120000, //0000                  //70000B62                             //AFIT16_GLAMOUR
+	0x0F1200C1, //00C1                  //70000B64                             //AFIT16_sddd8a_e
+	0x0F120000, //0000                  //70000B66
+	0x0F1203FF, //03FF                  //70000B68                             //AFIT16_Demosaic
+	0x0F12009E, //009E                  //70000B6A                             //AFIT16_Sharpeni
+	0x0F12017C, //017C                  //70000B6C                             //AFIT16_demsharp
+	0x0F1203FF, //03FF                  //70000B6E                             //AFIT16_demsharp
+	0x0F12000C, //000C                  //70000B70                             //AFIT16_demsharp
+	0x0F120010, //0010                  //70000B72                             //AFIT16_demsharp
+	0x0F1200C8, //00C8                  //70000B74                             //AFIT16_demsharp
+	0x0F1203E8, //03E8                  //70000B76                             //AFIT16_demsharp
+	0x0F120046, //0046                  //70000B78                             //AFIT16_demsharp
+	0x0F120050, //0050                  //70000B7A                             //AFIT16_demsharp
+	0x0F120070, //0070                  //70000B7C                             //AFIT16_demsharp
+	0x0F120001, //0001                  //70000B7E                  //AFIT16_demsharpmix1_iHystT
+	0x0F120000, //0000                  //70000B80                  //AFIT16_demsharpmix1_iHystT
+	0x0F120320, //0320                  //70000B82                  //AFIT16_demsharpmix1_iHystC
+	0x0F12008C, //008C                  //70000B84                             //AFIT16_Sharpeni
+	0x0F120014, //0014                  //70000B86                             //AFIT16_Sharpeni
+	0x0F12008C, //002D                  //70000B88                             //AFIT16_Sharpeni
+	0x0F120014, //0019                  //70000B8A                             //AFIT16_Sharpeni
+	0x0F12008C, //002D                  //70000B8C                             //AFIT16_Sharpeni
+	0x0F120014, //0019                  //70000B8E                             //AFIT16_Sharpeni
+	0x0F120A24, //0A24                  //70000B90                             //AFIT8_sddd8a_ed
+	0x0F121701, //1701                  //70000B92                             //AFIT8_sddd8a_re
+	0x0F120229, //0229                  //70000B94                             //AFIT8_sddd8a_sa
+	0x0F121403, //1403                  //70000B96                             //AFIT8_sddd8a_sa
+	0x0F120004, //0004                  //70000B98                             //AFIT8_sddd8a_iH
+	0x0F120300, //0300                  //70000B9A                             //AFIT8_sddd8a_iC
+	0x0F120000, //0000                  //70000B9C                             //AFIT8_sddd8a_Ad
+	0x0F1202FF, //02FF                  //70000B9E                             //AFIT8_sddd8a_iS
+	0x0F1205DE, //05DE                  //70000BA0                             //AFIT8_sddd8a_iR
+	0x0F121414, //1414                  //70000BA2                             //AFIT8_sddd8a_iL
+	0x0F120301, //0301                  //70000BA4                             //AFIT8_sddd8a_iL
+	0x0F120007, //0007                  //70000BA6                             //AFIT8_sddd8a_iS
+	0x0F121000, //1000                  //70000BA8
+	0x0F122303, //2303                  //70000BAA
+	0x0F12231A, //231A                  //70000BAC
+	0x0F120023, //0023                  //70000BAE
+	0x0F121E80, //1E80                  //70000BB0                             //AFIT8_Demosaici
+	0x0F121E08, //1E08                  //70000BB2                             //AFIT8_Demosaici
+	0x0F12010A, //010A                  //70000BB4                             //AFIT8_Demosaici
+	0x0F120001, //0001                  //70000BB6                             //AFIT8_Demosaici
+	0x0F127D0A, //3C0A                  //70000BB8                             //AFIT8_Demosaici
+	0x0F122C24, //2300                  //70000BBA                             //AFIT8_Sharpenin
+	0x0F120207, //0200                  //70000BBC                             //AFIT8_Sharpenin
+	0x0F12FF00, //FF00                  //70000BBE                             //AFIT8_Sharpenin
+	0x0F120200, //0200                  //70000BC0                             //AFIT8_demsharpm
+	0x0F121E10, //1E10                  //70000BC2                             //AFIT8_demsharpm
+	0x0F120000, //0000                  //70000BC4                             //AFIT8_demsharpm
+	0x0F120009, //0009                  //70000BC6                             //AFIT8_demsharpm
+	0x0F120406, //0406                  //70000BC8                             //AFIT8_demsharpm
+	0x0F120705, //0705                  //70000BCA                             //AFIT8_demsharpm
+	0x0F120306, //0306                  //70000BCC
+	0x0F120509, //0509                  //70000BCE
+	0x0F122806, //2806                  //70000BD0
+	0x0F121428, //1428                  //70000BD2
+	0x0F120518, //0518                  //70000BD4                  //[15:8]iUVNRStrengthL [7:0]
+	0x0F128005, //8005                  //70000BD6                  //[7:0]iUVNRStrengthH AFIT8_
+	0x0F120080, //0080                  //70000BD8                             //AFIT8_RGBGamma2
+	0x0F120080, //0080                  //70000BDA                             //AFIT8_ccm_oscar
+	0x0F120080, //0080                  //70000BDC                             //AFIT8_RGB2YUV_i
+	0x0F120101, //0101                  //70000BDE                             //AFIT8_sddd8a_iC
+	0x0F120707, //0707                  //70000BE0                             //AFIT8_sddd8a_iC
+	0x0F124B01, //4B01                  //70000BE2                             //AFIT8_sddd8a_nC
+	0x0F12144B, //2A4B                  //70000BE4                             //AFIT8_sddd8a_Di
+	0x0F125014, //5020                  //70000BE6                             //AFIT8_sddd8a_iD
+	0x0F120500, //0500                  //70000BE8                             //AFIT8_Demosaici
+	0x0F122B03, //1C03                  //70000BEA                             //AFIT8_Demosaici
+	0x0F126303, //0D0C                  //70000BEC                             //AFIT8_Demosaici
+	0x0F120823, //0823                  //70000BEE                             //AFIT8_Demosaici
+	0x0F121428, //1428                  //70000BF0                             //AFIT8_Demosaici
+	0x0F12CC01, //6401                  //70000BF2                             //AFIT8_Demosaici
+	0x0F12283E, //282D                  //70000BF4                             //AFIT8_Sharpenin
+	0x0F122012, //2012                  //70000BF6                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000BF8                             //AFIT8_Sharpenin
+	0x0F120103, //3C03                  //70000BFA                             //AFIT8_demsharpm
+	0x0F120701, //013C                  //70000BFC                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000BFE                             //AFIT8_sddd8a_iC
+	0x0F124B4B, //1C1E                  //70000C00                             //AFIT8_sddd8a_Di
+	0x0F120000, //1E22                  //70000C02                             //AFIT8_sddd8a_iD
+	0x0F120050, //0028                  //70000C04                             //AFIT8_Demosaici
+	0x0F120305, //030A                  //70000C06                             //AFIT8_Demosaici
+	0x0F120C5C, //0214                  //70000C08                             //AFIT8_Demosaici
+	0x0F12230D, //0E14                  //70000C0A                             //AFIT8_Demosaici
+	0x0F122808, //FF06                  //70000C0C                             //AFIT8_Demosaici
+	0x0F120114, //0432                  //70000C0E                             //AFIT8_Demosaici
+	0x0F122D74, //4052                  //70000C10                             //AFIT8_Sharpenin
+	0x0F120908, //150C                  //70000C12                             //AFIT8_Sharpenin
+	0x0F120420, //0440                  //70000C14                             //AFIT8_Sharpenin
+	0x0F120302, //0302                  //70000C16                             //AFIT8_demsharpm
+	0x0F123C3C, //3C3C                  //70000C18                             //AFIT8_sddd8a_iC
+	0x0F120101, //0101                  //70000C1A                             //AFIT8_sddd8a_iC
+	0x0F124B01, //1E01                  //70000C1C                             //AFIT8_sddd8a_nC
+	0x0F12004B, //221C                  //70000C1E                             //AFIT8_sddd8a_Di
+	0x0F125000, //281E                  //70000C20                             //AFIT8_sddd8a_iD
+	0x0F120500, //0A00                  //70000C22                             //AFIT8_Demosaici
+	0x0F125C03, //1403                  //70000C24                             //AFIT8_Demosaici
+	0x0F120D0C, //1402                  //70000C26                             //AFIT8_Demosaici
+	0x0F120823, //060E                  //70000C28                             //AFIT8_Demosaici
+	0x0F121428, //32FF                  //70000C2A                             //AFIT8_Demosaici
+	0x0F127401, //5204                  //70000C2C                             //AFIT8_Demosaici
+	0x0F12082D, //0C40                  //70000C2E                             //AFIT8_Sharpenin
+	0x0F122009, //4015                  //70000C30                             //AFIT8_Sharpenin
+	0x0F120204, //0204                  //70000C32                             //AFIT8_Sharpenin
+	0x0F120003, //0003                  //70000C34                             //AFIT8_demsharpm
+	0x0F120001, //0001                  //70000C36
+	0x0F120000, //0000                  //0000                  //70000C38                  //AF
+	0x0F120000, //0000                  //0000                  //70000C3A                  //AF
+	0x0F120000, //0000                  //0000                  //70000C3C                  //AF
+	0x0F120000, //0000                  //0000                  //70000C3E                  //AF
+	0x0F120000, //0000                  //0000                  //70000C40                  //AF
+	0x0F1200C1, //00C1                  //00C1                  //70000C42                  //AF
+	0x0F120000, //0000                  //0000                  //70000C44
+	0x0F1203FF, //03FF                  //03FF                  //70000C46                  //AF
+	0x0F12009C, //009C                  //0008                  //70000C48                  //AF
+	0x0F120251, //0251                  //017C                  //70000C4A                  //AF
+	0x0F1203FF, //03FF                  //03FF                  //70000C4C                  //AF
+	0x0F12000C, //000C                  //000C                  //70000C4E                  //AF
+	0x0F120010, //0010                  //0010                  //70000C50                  //AF
+	0x0F120032, //0032                  //0032                  //70000C52                  //AF
+	0x0F12028A, //028A                  //028A                  //70000C54                  //AF
+	0x0F120032, //0032                  //0032                  //70000C56                  //AF
+	0x0F1201F4, //01F4                  //01F4                  //70000C58                  //AF
+	0x0F120070, //0070                  //0070                  //70000C5A                  //AF
+	0x0F120002, //0002                  //0002                  //70000C5C                  //AF
+	0x0F120000, //0000                  //0000                  //70000C5E                  //AF
+	0x0F120320, //0320                  //0320                  //70000C60                  //AF
+	0x0F120044, //0044                  //0070                  //70000C62                  //AF
+	0x0F120014, //0014                  //0014                  //70000C64                  //AF
+	0x0F120044, //0046                  //0046                  //70000C66                  //AF
+	0x0F120014, //0019                  //0019                  //70000C68                  //AF
+	0x0F120044, //0046                  //0046                  //70000C6A                  //AF
+	0x0F120014, //0019                  //0019                  //70000C6C                  //AF
+	0x0F120A24, //0A24                  //0A24                  //70000C6E                  //AF
+	0x0F121701, //1701                  //1701                  //70000C70                  //AF
+	0x0F120229, //0229                  //0229                  //70000C72                  //AF
+	0x0F120503, //0503                  //0503                  //70000C74                  //AF
+	0x0F12080F, //080F                  //0101                  //70000C76                  //AF
+	0x0F120808, //0808                  //0101                  //70000C78                  //AF
+	0x0F120000, //0000                  //0000                  //70000C7A                  //AF
+	0x0F1200FF, //00FF                  //02FF                  //70000C7C                  //AF
+	0x0F12012D, //012D                  //0396                  //70000C7E                  //AF
+	0x0F121414, //1414                  //1414                  //70000C80                  //AF
+	0x0F120301, //0301                  //0301                  //70000C82                  //AF
+	0x0F120007, //0007                  //0007                  //70000C84                  //AF
+	0x0F121000, //1000                  //1000                  //70000C86
+	0x0F122003, //2003                  //2003                  //70000C88
+	0x0F121020, //1020                  //1020                  //70000C8A
+	0x0F120010, //0010                  //0010                  //70000C8C
+	0x0F121EFF, //1EFF                  //1E80                  //70000C8E                  //AF
+	0x0F121E06, //1E06                  //1E06                  //70000C90                  //AF
+	0x0F12060A, //060A                  //030C                  //70000C92                  //AF
+	0x0F120306, //0306                  //0103                  //70000C94                  //AF
+	0x0F12810A, //8B0A                  //5A0A                  //70000C96                  //AF
+	0x0F1215C4, //2837                  //2D00                  //70000C98                  //AF
+	0x0F120107, //0110                  //0100                  //70000C9A                  //AF
+	0x0F12FF00, //FF00                  //FF00                  //70000C9C                  //AF
+	0x0F120200, //0200                  //0200                  //70000C9E                  //AF
+	0x0F121E10, //1E10                  //1E10                  //70000CA0                  //AF
+	0x0F120000, //0000                  //0000                  //70000CA2                  //AF
+	0x0F120009, //0009                  //0009                  //70000CA4                  //AF
+	0x0F120406, //0406                  //0406                  //70000CA6                  //AF
+	0x0F120705, //0705                  //0705                  //70000CA8                  //AF
+	0x0F120305, //0305                  //0305                  //70000CAA
+	0x0F120609, //0609                  //0609                  //70000CAC
+	0x0F122C07, //2C07                  //2C07                  //70000CAE
+	0x0F12142C, //142C                  //142C                  //70000CB0
+	0x0F120B18, //0B18                  //0B18                  //70000CB2                  //[1
+	0x0F12800B, //800B                  //800B                  //70000CB4                  //[7
+	0x0F120080, //0080                  //0080                  //70000CB6                  //AF
+	0x0F120080, //0080                  //0080                  //70000CB8                  //AF
+	0x0F120080, //0080                  //0080                  //70000CBA                  //AF
+	0x0F125050, //5050                  //0101                  //70000CBC                  //AF
+	0x0F120101, //0101                  //0A0A                  //70000CBE                  //AF
+	0x0F123201, //3201                  //3201                  //70000CC0                  //AF
+	0x0F120032, //1832                  //1428                  //70000CC2                  //AF
+	0x0F122100, //210C                  //100C                  //70000CC4                  //AF
+	0x0F120A00, //0A00                  //0500                  //70000CC6                  //AF
+	0x0F125004, //1E04                  //1E02                  //70000CC8                  //AF
+	0x0F12A400, //0A08                  //040C                  //70000CCA                  //AF
+	0x0F12070C, //070C                  //0828                  //70000CCC                  //AF
+	0x0F123264, //3264                  //5064                  //70000CCE                  //AF
+	0x0F12F802, //5A02                  //4605                  //70000CD0                  //AF
+	0x0F12103E, //1040                  //1E68                  //70000CD2                  //AF
+	0x0F124012, //4012                  //201E                  //70000CD4                  //AF
+	0x0F120604, //0604                  //0604                  //70000CD6                  //AF
+	0x0F125006, //4606                  //4606                  //70000CD8                  //AF
+	0x0F120150, //0146                  //0146                  //70000CDA                  //AF
+	0x0F120101, //0101                  //0101                  //70000CDC                  //AF
+	0x0F123232, //1C18                  //1C18                  //70000CDE                  //AF
+	0x0F120000, //1819                  //1819                  //70000CE0                  //AF
+	0x0F120021, //0028                  //0028                  //70000CE2                  //AF
+	0x0F12040A, //030A                  //030A                  //70000CE4                  //AF
+	0x0F12085E, //0514                  //0514                  //70000CE6                  //AF
+	0x0F120C0A, //0C14                  //0C14                  //70000CE8                  //AF
+	0x0F123207, //FF05                  //FF05                  //70000CEA                  //AF
+	0x0F120119, //0432                  //0432                  //70000CEC                  //AF
+	0x0F12406A, //4052                  //4052                  //70000CEE                  //AF
+	0x0F120908, //1514                  //1514                  //70000CF0                  //AF
+	0x0F120440, //0440                  //0440                  //70000CF2                  //AF
+	0x0F120606, //0302                  //0302                  //70000CF4                  //AF
+	0x0F124646, //4646                  //4646                  //70000CF6                  //AF
+	0x0F120101, //0101                  //0101                  //70000CF8                  //AF
+	0x0F123201, //1801                  //1801                  //70000CFA                  //AF
+	0x0F120032, //191C                  //191C                  //70000CFC                  //AF
+	0x0F122100, //2818                  //2818                  //70000CFE                  //AF
+	0x0F120A00, //0A00                  //0A00                  //70000D00                  //AF
+	0x0F125E04, //1403                  //1403                  //70000D02                  //AF
+	0x0F120A08, //1405                  //1405                  //70000D04                  //AF
+	0x0F12070C, //050C                  //050C                  //70000D06                  //AF
+	0x0F121932, //32FF                  //32FF                  //70000D08                  //AF
+	0x0F126A01, //5204                  //5204                  //70000D0A                  //AF
+	0x0F120840, //1440                  //1440                  //70000D0C                  //AF
+	0x0F124009, //4015                  //4015                  //70000D0E                  //AF
+	0x0F120604, //0204                  //0204                  //70000D10                  //AF
+	0x0F120006, //0003                  //0003                  //70000D12                  //AF
+	0x0F120001, //0001                  //0001                  //70000D14
+
+	0x0F12BA7A, //70000D16
+	0x0F124FDE, //70000D18
+	0x0F12137F, //70000D1A
+	0x0F123BDE, //70000D1C
+	0x0F12BF02, //70000D1E
+	0x0F1200B5, //70000D20
+
+	//===================================================================
+	// Brightness setting
+	//===================================================================
+	0x002A1300,
+	0x0F12019D,
+
+	0x002A1306,
+	0x0F120280,
+
+
+	0x002a3fea,
+	0x0f120800, //analog filter update Green
+
+
+	/* TNP_Regs_bUseAccurateFR */
+	/* 0x00287000, */
+	/* 0x002A3FE4, */
+	/* 0x0F120001, */ /* on/off TNP_Regs_bAccuDynamicFR */
+	/* 0x0F1234A2, */ /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+	/* 0x0F1240FD, */ /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+};
+
+/* Return preview mode */
+static const u32 s5k5ccgx_preview_return[] =  {
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0C7E,
+	0x0F120396, //70000C7E //AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+	0x002A0CC4,
+	0x0F12100C, //70000CC4	//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+	0x002A0836,
+	0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+	0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+	0x002A0D1E,
+	0x0F122102, //70000D1E
+
+	//PREVIEW
+	0x002A0208,
+	0x0F120000, //REG_TC_GP_ActivePrevConfig
+	0x002A0210,
+	0x0F120000, //REG_TC_GP_ActiveCapConfig
+	0x002A020C,
+	0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+	0x002A01F4,
+	0x0F120001, //REG_TC_GP_NewConfigSync
+	0x002A020A,
+	0x0F120001, //REG_TC_GP_PrevConfigChanged
+	0x002A0212,
+	0x0F120001, //REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120000, //REG_TC_GP_EnableCapture
+	0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_highlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0C7E,
+0x0F12032D,	//70000C7E	//AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+0x002A0CC4,
+0x0F12210E,	//70000CC4	//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+0x002A0836,
+0x0F123A00,	//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000,	//TVAR_ash_GASOutdoorAlpha_3_
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* 2048x1536 capture (Capture config0) */
+static const u32 s5k5ccgx_snapshot[] =
+{
+	0xFCFCD000,
+	0x00287000,
+
+	0x002A0D1E,
+	0x0F12A102,	//70000D1E
+
+	0x002A0210,
+	0x0F120000,	//REG_TC_GP_ActiveCapConfig
+	0x002A01F4,
+	0x0F120001,	//REG_TC_GP_NewConfigSync
+	0x002A0212,
+	0x0F120001,	//REG_TC_GP_CapConfigChanged
+	0x002A01E8,
+	0x0F120001,	//REG_TC_GP_EnableCapture
+	0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+	0xFFFF00A0,   //160ms
+};
+
+/* 640x480 capture (Capture config1) */
+static const u32 s5k5ccgx_snapshot_vga[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120001,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_lowlight_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF012C,   //300ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_normal_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* For 2048x1152 cap */
+static const u32 s5k5ccgx_change_wide_cap[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_PrevInputHeightOfs (600h-480h)/2
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120480,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F1200C0,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120240,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120480,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+#ifdef CONFIG_VIDEO_S5K5CCGX_P2
+/* Wide capture 2048x1100 */
+static const u32 s5k5ccgx_change_wide_cap_p2[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F12044C,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F1200DA,	//REG_TC_GP_PrevInputHeightOfs (600h-480h)/2
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F12044C,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F1200DA,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F12044C,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F1200DA,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120226,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F12044C,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+#endif
+
+/* To change Wide Capture to Normal Capture,
+ * We have to restore capture configuration before starting Normal Capture.
+ */
+static const u32 s5k5ccgx_restore_capture_reg[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120600,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120300,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120600,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+static const u32 s5k5ccgx_get_light_status[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A3C,
+};
+
+static const u32 s5k5ccgx_get_iso_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A18,
+};
+
+static const u32 s5k5ccgx_get_shutterspeed_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A14,
+};
+
+static const u32 s5k5ccgx_fps_auto[] = {
+0x00287000,
+0x002A025A,
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+/* DSLIM.
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnablePreview
+0x0F120001, //REG_TC_GP_EnablePreviewChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_15fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12029A,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12029A,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_25fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F120190, //14E,//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F120190, //14E,//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+
+static const u32 s5k5ccgx_fps_30fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12014E,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+
+
+/* effect off = normal */
+static const u32 s5k5ccgx_effect_off[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0648,
+0x0F120001,		//skl_af_bPregmOff	Pre/Post Gamma Off (¿øº¹)
+
+0x002A01E2,
+0x0F120000,		//REG_TC_GP_SpecialEffects	00:Normal Mode
+};
+
+static const u32 s5k5ccgx_effect_mono[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120001,		//REG_TC_GP_SpecialEffects	01:Mono Mode
+};
+
+static const u32 s5k5ccgx_effect_sepia[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120004,		//REG_TC_GP_SpecialEffects	04:Sepia Mode
+};
+
+static const u32 s5k5ccgx_effect_negative[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120003,		//REG_TC_GP_SpecialEffects	03:Negative Mode
+};
+
+static const u32 s5k5ccgx_wb_auto[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120001,		//Mon_AAIO_bAWB		AWB ON
+};
+
+static const u32 s5k5ccgx_wb_daylight[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F120620,		//REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F120540,		//REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_cloudy[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F1207B0,               //REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F1204A8,               //REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_fluorescent[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F120560,		//REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F1208A0,		//REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_incandescent[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A2A62,
+	0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+	0x002A0470,
+	0x0F1203C0,		//REG_SF_USER_Rgain
+	0x0F120001,		//REG_SF_USER_RgainChanged
+	0x0F120400,		//REG_SF_USER_Ggain
+	0x0F120001,		//REG_SF_USER_GgainChanged
+	0x0F120980,		//REG_SF_USER_Bgain
+	0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_brightness_m_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12001A, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12001F, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120028, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120032, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_0[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12004A,//TVAR_ae_BrAves
+
+};
+
+static const u32 s5k5ccgx_brightness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120065,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120075,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12008B,//TVAR_ae_BrAv
+
+};
+
+static const u32 s5k5ccgx_scene_off[] = {
+// ==========================================================
+//	CAMERA_SCENE_OFF
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,		//Mon_AAIO_bAWB		0: AWB OFF, 1: AWB ON
+
+// Center (Metering)
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+//	01. Portait / Landscape / Text / Fall Color Off
+
+0x00287000,
+0x002A1308,
+0x0F12003E,		//TVAR_ae_BrAve
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x0F120000,		//REG_TC_UserContrast
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+//	02. Night / Firework Off
+0x00287000,
+0x002A025A,
+0x0F1203E8,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+0x002A034C,
+0x0F120535,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120010,	// 0010 ae_GainIn_0_			//
+0x0F120020,	// 0020	ae_GainIn_1_			//
+0x0F120040,	// 0040	ae_GainIn_2_			//
+0x0F120080,	// 0080	ae_GainIn_3_			//
+0x0F120100,	// fix 0100	ae_GainIn_4_			//
+0x0F120200,	// 0200	ae_GainIn_5_			//
+0x0F120400,	// 0400	ae_GainIn_6_			//
+0x0F120800,	// 0800	ae_GainIn_7_			//
+0x0F122000,	// 2000	ae_GainIn_8_			//
+
+0x0F120010,	//0050	// 0010	ae_GainOut_0_	p	//
+0x0F120020,	//0070	// 0020	ae_GainOut_1_ p//
+0x0F120040,	//00A0	// 0040	ae_GainOut_2_	p	//
+0x0F120080,	//00D0	// 0080	ae_GainOut_3_	p	//
+0x0F120100,	// fix 0100	ae_GainOut_4_		//
+0x0F120200,	// 0200	ae_GainOut_5_		//
+0x0F120400,	// 0400	ae_GainOut_6_		//
+0x0F120800,	// 0800	ae_GainOut_7_		//
+0x0F122000,	// 2000	ae_GainOut_8_		//
+
+
+//AE_state
+0x002A04EE,
+0x0F12010E,      //#lt_uLimitHigh
+0x0F1200F5,      //#lt_uLimitLow
+
+0x00287000,
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0524,
+0x0F1201E0,		//lt_uMaxAnGain1
+0x0F1201E0,		//lt_uMaxAnGain2
+0x0F120300,		//lt_uMaxAnGain3
+0x0F120840,		//lt_uMaxAnGain4
+
+0x0F120100,		//lt_uMaxDigGain
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F1201E0,		//lt_uCapMaxAnGain1
+0x0F1201E0,		//lt_uCapMaxAnGain2
+0x0F120300,		//lt_uCapMaxAnGain3
+0x0F120710,		//lt_uCapMaxAnGain4
+
+0x0F120100,		//lt_uCapMaxDigGain
+0x0F128000,		//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120010,		//AFIT16_demsharpmix1_iHystThLow
+0x0F120010,		//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F120B50,		//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+
+//	03. ISO Auto
+
+0x002A04A4,
+0x0F12067F,		//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+0x002A0486,
+0x0F120000,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_portrait[] = {
+// ==========================================================
+//	CAMERA_SCENE_PORTRAIT (Auto/Center/Br0/Auto/Sharp-1/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F12FFF6,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_landscape[] = {
+// ==========================================================
+//	CAMERA_SCENE_LANDSCAPE (Auto/Matrix/Br0/Auto/Sharp+1/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F12000A,		//REG_TC_UserSharpBlur
+
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+
+
+};
+
+static const u32 s5k5ccgx_scene_sports[] = {
+// ==========================================================
+//  CAMERA_SCENE_SPORTS (Sport/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+
+0x002A04EE,
+0x0F120112,		//lt_uLimitHigh
+0x0F1200EE,		//lt_uLimitLow
+
+0x002A0504,
+0x0F120002, //3415  //lt_uMaxExp1  3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F120D05, //3415  //lt_uMaxExp2  3415h = 13333d =  33.3325ms
+0x002A050C,
+0x0F121A0A, //3415  //lt_uMaxExp3  3415h = 13333d =  33.3325ms
+0x002A0510,
+0x0F123415,  //lt_uMaxExp4  3415h = 13333d =  33.3325ms
+
+0x002A0514,
+0x0F120002, //3415  //lt_uCapMaxExp1  3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F120D05, //3415  //lt_uCapMaxExp2  3415h = 13333d =  33.3325ms
+0x002A051C,
+0x0F121A0A, //3415  //lt_uCapMaxExp3  3415h = 13333d =  33.3325ms
+0x002A0520,
+0x0F123415,  //lt_uCapMaxExp4  3415h = 13333d =  33.3325ms
+
+0x002A0524,
+0x0F120200, //lt_uMaxAnGain1
+0x0F120200, //lt_uMaxAnGain2
+0x0F120200, //lt_uMaxAnGain3
+0x0F120200, //lt_uMaxAnGain4
+
+0x0F120200, //lt_uMaxDigGain
+0x0F128000, //lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //lt_uCapMaxAnGain1
+0x0F120200, //lt_uCapMaxAnGain2
+0x0F120200, //lt_uCapMaxAnGain3
+0x0F120200, //lt_uCapMaxAnGain4
+
+0x0F120200, //lt_uCapMaxDigGain
+0x0F128000, //lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+
+
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,  //AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,
+
+//Preview
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_party[] = {
+// ==========================================================
+//	CAMERA_SCENE_PARTYINDOOR (ISO200/Center/Br0/Auto/Sharp0/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+
+0x002A04EE,
+0x0F120112,		//lt_uLimitHigh
+0x0F1200EE,		//lt_uLimitLow
+
+0x002A052C,
+0x0F120200,		//lt_Dgain
+
+0x002A05EA,
+0x0F120220,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120300,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_beach[] = {
+// ==========================================================
+//	CAMERA_SCENE_BEACHSNOW (ISO50/Center/Br+1/Auto/Sharp0/Sat+1)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120020,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+//ISO 50
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_sunset[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F120526,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_dawn[] = {
+// Use MWB CWF
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120530,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F1207E6,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_fall[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120032,		//REG_TC_UserSaturation
+0x0F120000,		//REG_TC_UserSharpBlur
+
+};
+
+static const u32 s5k5ccgx_scene_nightshot[] = {
+// ==========================================================
+//	CAMERA_SCENE_NIGHT (Night/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A, // 0602 09C4(4fps)->0682(6fps)
+0x0F120682,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F121388,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F121388,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,		//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,		//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0524,
+0x0F1201D0,		//lt_uMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120B00,		//lt_uMaxAnGain4 0602 0800->0B00 0710h	= 1808d	= x7.0625
+
+0x0F120100,		//lt_uMaxDigGain
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F1201D0,		//lt_uCapMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uCapMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uCapMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,		//lt_uCapMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,		//lt_uCapMaxDigGain
+0x0F128000,		//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120000,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120000,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F121080,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_backlight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+/* Not Used */
+static const u32 s5k5ccgx_scene_firework[] = {
+// ==========================================================
+//	CAMERA_SCENE_FIREWORK (ISO50/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F1209C4,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F122710,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F122710,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,		//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,		//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+//ISO 50
+
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_text[] = {
+// ==========================================================
+//	CAMERA_SCENE_TEXT (Auto/Center/Br0/Auto/Sharp+2/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120014,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_candle[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,		//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120600,		//REG_SF_USER_Rgain
+0x0F120001,		//REG_SF_USER_RgainChanged
+0x0F120400,		//REG_SF_USER_Ggain
+0x0F120001,		//REG_SF_USER_GgainChanged
+0x0F120526,		//REG_SF_USER_Bgain
+0x0F120001,		//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_metering_normal[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_metering_spot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+
+static const u32 s5k5ccgx_metering_center[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_auto[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12067F,		//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0486,
+0x0F120000,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,		//AFIT by Normalized Brightness Tunning Parameter
+
+//Preview
+0x002A0208,
+0x0F120000,		//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,		//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,		//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,		//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,		//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,		//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_50[] = {
+
+	0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_100[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120200,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_200[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120400,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_400[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,		//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,		//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,		//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,		//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,		//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,		//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,		//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,		//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,		//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,		//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,		//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,		//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120800,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_ae_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120000, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12FFFF, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_ae_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120001, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12001E, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_af_abort[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120001,   // REG_TC_AF_AfCmd = 1, Abort A
+};
+
+static const u32 s5k5ccgx_af_off_reg[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0226,
+	0x0F120000,
+	0xFFFF0049, /* 73 ms delay,  Min 1 frame delay */
+	0x002A0224, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120004, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+	0xFFFF0118, /* 280ms Delay */
+};
+
+static const u32 s5k5ccgx_af_normal_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+	0xFFFF0096, /* 150ms Delay */
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+	0x002A1494,
+	0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_night_normal_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+
+	0xFFFF00FA, /* 250ms Delay*/
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+	0x002A1494,
+	0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_macro_on[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0224,
+	0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+	0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120095, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+	0xFFFF0096, /* 150ms Delay */
+
+	/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+	1042 : macro mode on, 2nd search(fine search) on
+	1000 : macro mode off, 2nd search off,
+	1002 : macro mode off, 2nd search on */
+
+	0x002A1494,
+	0x0F121042,
+
+	/* when user use lens position 16(10h) -> lens position 0(00h)
+	MSB 10 b means user uses #af_pos_usTable_16_ as start position.
+	LSB 00 b means user uses #af_pos_usTable_0_ as end position
+	refer to 5.3 macro mode setting.
+	"#af_pos_usMacroStartEnd" is only used in macro AF condition.
+	(normal AF doesn't use "#af_pos_usMacroStartEnd") */
+	0x002A1426,
+	0x0F121000, /* #af_pos_usMacroStartEn */
+};
+
+static const u32 s5k5ccgx_af_do[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120005,   // REG_TC_AF_AfCmd = 5, single A
+};
+
+static const u32 s5k5ccgx_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_1st_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+0xFFFF01F4, /* tuning point */
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_contrast_m_2[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_m_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_0[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D2,
+//0F120080,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_saturation_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12007E,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFE0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120005,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D6,
+0x0F120010,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_dtp_on[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_dtp_off[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_pll_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_pll_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_preflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F82,
+0x0F120001,		// TNP_Regs_PreflashStart
+};
+
+static const u32 s5k5ccgx_preflash_end[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F84,
+0x0F120001,		// TNP_Regs_PreflashEnd
+};
+
+static const u32 s5k5ccgx_mainflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F80,		//TNP_Regs_FastFlashAlg
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_mainflash_end[] = {
+};
+
+static const u32 s5k5ccgx_flash_ae_set[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_flash_ae_clear[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120002,
+};
+
+static const u32 s5k5ccgx_get_ae_stable_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E1E3C,
+};
+
+static const u32 s5k5ccgx_get_esd_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E0150,
+};
+
+#endif /* __S5K5CCGX_REG_P4W_H__ */
diff --git a/drivers/media/video/s5k5ccgx_regs-p8.h b/drivers/media/video/s5k5ccgx_regs-p8.h
new file mode 100644
index 0000000..5df3cdb
--- /dev/null
+++ b/drivers/media/video/s5k5ccgx_regs-p8.h
@@ -0,0 +1,12701 @@
+/* drivers/media/video/s5k5ccgx_regs-p8.h
+ * latest version: 11/11/23
+ *
+ * Driver for s5k5ccgx (5MP Camera) from SEC(LSI), firmware EVT1.1
+ *
+ * Copyright (C) 2010, SAMSUNG ELECTRONICS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+
+#ifndef __S5K5CCGX_REG_P8_H__
+#define __S5K5CCGX_REG_P8_H__
+
+/* Init regs for YUV capture */
+static const u32 s5k5ccgx_init_reg[] =
+{
+0xFCFCD000,	//Reset                                  //
+0x00140001, //Wait100mSec                            //
+0x10021101,  
+
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000          //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A,     //p10
+// Start of Patch data
+/*++ Add ESD */
+0x00287000,
+0x002A0150,
+0x0F12AAAA,
+/*-- Add ESD */
+0x00287000,
+0x002A352C,
+0x0F12B570, // 7000352C 
+0x0F124A24, // 7000352E 
+0x0F124924, // 70003530 
+0x0F124825, // 70003532 
+0x0F124B25, // 70003534 
+0x0F122500, // 70003536 
+0x0F12801D, // 70003538 
+0x0F12C004, // 7000353A 
+0x0F126001, // 7000353C 
+0x0F124924, // 7000353E 
+0x0F124824, // 70003540 
+0x0F12F000, // 70003542 
+0x0F12FBBD, // 70003544 
+0x0F124924, // 70003546 
+0x0F124824, // 70003548 
+0x0F12F000, // 7000354A 
+0x0F12FBB9, // 7000354C 
+0x0F124824, // 7000354E 
+0x0F124E24, // 70003550 
+0x0F126430, // 70003552 
+0x0F124924, // 70003554 
+0x0F124825, // 70003556 
+0x0F12F000, // 70003558 
+0x0F12FBB2, // 7000355A 
+0x0F124924, // 7000355C 
+0x0F120030, // 7000355E 
+0x0F123080, // 70003560 
+0x0F126141, // 70003562 
+0x0F124C23, // 70003564 
+0x0F128365, // 70003566 
+0x0F124923, // 70003568 
+0x0F124824, // 7000356A 
+0x0F12F000, // 7000356C 
+0x0F12FBA8, // 7000356E 
+0x0F124923, // 70003570 
+0x0F124824, // 70003572 
+0x0F12F000, // 70003574 
+0x0F12FBA4, // 70003576 
+0x0F124923, // 70003578 
+0x0F124824, // 7000357A 
+0x0F12F000, // 7000357C 
+0x0F12FBA0, // 7000357E 
+0x0F124923, // 70003580 
+0x0F124824, // 70003582 
+0x0F12F000, // 70003584 
+0x0F12FB9C, // 70003586 
+0x0F128125, // 70003588 
+0x0F124923, // 7000358A 
+0x0F124823, // 7000358C 
+0x0F12F000, // 7000358E 
+0x0F12FB97, // 70003590 
+0x0F124923, // 70003592 
+0x0F124823, // 70003594 
+0x0F12F000, // 70003596 
+0x0F12FB93, // 70003598 
+0x0F1283A5, // 7000359A 
+0x0F124922, // 7000359C 
+0x0F124823, // 7000359E 
+0x0F12F000, // 700035A0 
+0x0F12FB8E, // 700035A2 
+0x0F122101, // 700035A4 
+0x0F120349, // 700035A6 
+0x0F120020, // 700035A8 
+0x0F123020, // 700035AA 
+0x0F128041, // 700035AC 
+0x0F122185, // 700035AE 
+0x0F128081, // 700035B0 
+0x0F12491F, // 700035B2 
+0x0F1280C1, // 700035B4 
+0x0F12481F, // 700035B6 
+0x0F126730, // 700035B8 
+0x0F12BC70, // 700035BA 
+0x0F12BC08, // 700035BC 
+0x0F124718, // 700035BE 
+0x0F1200CA, // 700035C0 
+0x0F125CC1, // 700035C2 
+0x0F1203BD, // 700035C4 
+0x0F120000, // 700035C6 
+0x0F121C08, // 700035C8 
+0x0F127000, // 700035CA 
+0x0F123290, // 700035CC 
+0x0F127000, // 700035CE 
+0x0F123657, // 700035D0 
+0x0F127000, // 700035D2 
+0x0F12D9E7, // 700035D4 
+0x0F120000, // 700035D6 
+0x0F12383F, // 700035D8 
+0x0F127000, // 700035DA 
+0x0F12395D, // 700035DC 
+0x0F120000, // 700035DE 
+0x0F1238D1, // 700035E0 
+0x0F127000, // 700035E2 
+0x0F120000, // 700035E4 
+0x0F127000, // 700035E6 
+0x0F12399D, // 700035E8 
+0x0F127000, // 700035EA 
+0x0F12F903, // 700035EC 
+0x0F120000, // 700035EE 
+0x0F123AC1, // 700035F0 
+0x0F127000, // 700035F2 
+0x0F123FC8, // 700035F4 
+0x0F127000, // 700035F6 
+0x0F12368F, // 700035F8 
+0x0F127000, // 700035FA 
+0x0F12495F, // 700035FC 
+0x0F120000, // 700035FE 
+0x0F1236ED, // 70003600 
+0x0F127000, // 70003602 
+0x0F12E421, // 70003604 
+0x0F120000, // 70003606 
+0x0F1237AB, // 70003608 
+0x0F127000, // 7000360A 
+0x0F12216D, // 7000360C 
+0x0F120000, // 7000360E 
+0x0F12381F, // 70003610 
+0x0F127000, // 70003612 
+0x0F120179, // 70003614 
+0x0F120001, // 70003616 
+0x0F123BD5, // 70003618 
+0x0F127000, // 7000361A 
+0x0F1204C9, // 7000361C 
+0x0F120000, // 7000361E 
+0x0F123B25, // 70003620 
+0x0F127000, // 70003622 
+0x0F125027, // 70003624 
+0x0F120000, // 70003626 
+0x0F123BE1, // 70003628 
+0x0F127000, // 7000362A 
+0x0F1242B7, // 7000362C 
+0x0F120000, // 7000362E 
+0x0F1207FF, // 70003630 
+0x0F120000, // 70003632 
+0x0F123C5F, // 70003634 
+0x0F127000, // 70003636 
+0x0F12B570, // 70003638 
+0x0F12000D, // 7000363A 
+0x0F124CFC, // 7000363C 
+0x0F128821, // 7000363E 
+0x0F12F000, // 70003640 
+0x0F12FB46, // 70003642 
+0x0F128820, // 70003644 
+0x0F124AFB, // 70003646 
+0x0F120081, // 70003648 
+0x0F125055, // 7000364A 
+0x0F121C40, // 7000364C 
+0x0F128020, // 7000364E 
+0x0F12BC70, // 70003650 
+0x0F12BC08, // 70003652 
+0x0F124718, // 70003654 
+0x0F126801, // 70003656 
+0x0F120409, // 70003658 
+0x0F120C09, // 7000365A 
+0x0F126840, // 7000365C 
+0x0F120400, // 7000365E 
+0x0F120C00, // 70003660 
+0x0F124AF5, // 70003662 
+0x0F128992, // 70003664 
+0x0F122A00, // 70003666 
+0x0F12D00D, // 70003668 
+0x0F122300, // 7000366A 
+0x0F121A80, // 7000366C 
+0x0F12D400, // 7000366E 
+0x0F120003, // 70003670 
+0x0F120418, // 70003672 
+0x0F120C00, // 70003674 
+0x0F124BF1, // 70003676 
+0x0F121851, // 70003678 
+0x0F12891B, // 7000367A 
+0x0F12428B, // 7000367C 
+0x0F12D300, // 7000367E 
+0x0F12000B, // 70003680 
+0x0F120419, // 70003682 
+0x0F120C09, // 70003684 
+0x0F124AEE, // 70003686 
+0x0F128151, // 70003688 
+0x0F128190, // 7000368A 
+0x0F124770, // 7000368C 
+0x0F12B510, // 7000368E 
+0x0F124CEC, // 70003690 
+0x0F1248ED, // 70003692 
+0x0F1278A1, // 70003694 
+0x0F122900, // 70003696 
+0x0F12D101, // 70003698 
+0x0F1287C1, // 7000369A 
+0x0F12E004, // 7000369C 
+0x0F127AE1, // 7000369E 
+0x0F122900, // 700036A0 
+0x0F12D001, // 700036A2 
+0x0F122101, // 700036A4 
+0x0F1287C1, // 700036A6 
+0x0F12F000, // 700036A8 
+0x0F12FB1A, // 700036AA 
+0x0F1249E7, // 700036AC 
+0x0F128B08, // 700036AE 
+0x0F1206C2, // 700036B0 
+0x0F12D50A, // 700036B2 
+0x0F127AA2, // 700036B4 
+0x0F120652, // 700036B6 
+0x0F12D507, // 700036B8 
+0x0F122210, // 700036BA 
+0x0F124390, // 700036BC 
+0x0F128308, // 700036BE 
+0x0F1248E3, // 700036C0 
+0x0F127AE1, // 700036C2 
+0x0F126B00, // 700036C4 
+0x0F12F000, // 700036C6 
+0x0F12FB13, // 700036C8 
+0x0F1248DB, // 700036CA 
+0x0F1289C0, // 700036CC 
+0x0F122801, // 700036CE 
+0x0F12D109, // 700036D0 
+0x0F1278A0, // 700036D2 
+0x0F122800, // 700036D4 
+0x0F12D006, // 700036D6 
+0x0F127AE0, // 700036D8 
+0x0F122800, // 700036DA 
+0x0F12D003, // 700036DC 
+0x0F127AA0, // 700036DE 
+0x0F122140, // 700036E0 
+0x0F124308, // 700036E2 
+0x0F1272A0, // 700036E4 
+0x0F12BC10, // 700036E6 
+0x0F12BC08, // 700036E8 
+0x0F124718, // 700036EA 
+0x0F12B570, // 700036EC 
+0x0F124DD7, // 700036EE 
+0x0F124CD7, // 700036F0 
+0x0F128B28, // 700036F2 
+0x0F120701, // 700036F4 
+0x0F12D507, // 700036F6 
+0x0F122108, // 700036F8 
+0x0F124388, // 700036FA 
+0x0F128328, // 700036FC 
+0x0F1249D5, // 700036FE 
+0x0F126B20, // 70003700 
+0x0F126B89, // 70003702 
+0x0F12F000, // 70003704 
+0x0F12FAFC, // 70003706 
+0x0F128B28, // 70003708 
+0x0F1206C1, // 7000370A 
+0x0F12D5A0, // 7000370C 
+0x0F1249CD, // 7000370E 
+0x0F127A8A, // 70003710 
+0x0F120652, // 70003712 
+0x0F12D49C, // 70003714 
+0x0F122210, // 70003716 
+0x0F124390, // 70003718 
+0x0F128328, // 7000371A 
+0x0F127AC9, // 7000371C 
+0x0F126B20, // 7000371E 
+0x0F12F000, // 70003720 
+0x0F12FAE6, // 70003722 
+0x0F12E794, // 70003724 
+0x0F12B5F8, // 70003726 
+0x0F1249CB, // 70003728 
+0x0F128F08, // 7000372A 
+0x0F12000C, // 7000372C 
+0x0F123480, // 7000372E 
+0x0F122800, // 70003730 
+0x0F12D000, // 70003732 
+0x0F128360, // 70003734 
+0x0F122000, // 70003736 
+0x0F128708, // 70003738 
+0x0F124DC8, // 7000373A 
+0x0F1226FF, // 7000373C 
+0x0F128828, // 7000373E 
+0x0F121C76, // 70003740 
+0x0F122702, // 70003742 
+0x0F122803, // 70003744 
+0x0F12D112, // 70003746 
+0x0F128868, // 70003748 
+0x0F122800, // 7000374A 
+0x0F12D10F, // 7000374C 
+0x0F1288E8, // 7000374E 
+0x0F122800, // 70003750 
+0x0F12D10C, // 70003752 
+0x0F12F000, // 70003754 
+0x0F12FADC, // 70003756 
+0x0F122800, // 70003758 
+0x0F12D008, // 7000375A 
+0x0F128B60, // 7000375C 
+0x0F122800, // 7000375E 
+0x0F12D001, // 70003760 
+0x0F1280EE, // 70003762 
+0x0F1280AF, // 70003764 
+0x0F122001, // 70003766 
+0x0F127268, // 70003768 
+0x0F12F000, // 7000376A 
+0x0F12FAD9, // 7000376C 
+0x0F128828, // 7000376E 
+0x0F122802, // 70003770 
+0x0F12D10E, // 70003772 
+0x0F128868, // 70003774 
+0x0F122800, // 70003776 
+0x0F12D10B, // 70003778 
+0x0F1288E8, // 7000377A 
+0x0F122800, // 7000377C 
+0x0F12D108, // 7000377E 
+0x0F128B60, // 70003780 
+0x0F122800, // 70003782 
+0x0F12D001, // 70003784 
+0x0F1280EE, // 70003786 
+0x0F1280AF, // 70003788 
+0x0F122001, // 7000378A 
+0x0F127268, // 7000378C 
+0x0F12F000, // 7000378E 
+0x0F12FAC7, // 70003790 
+0x0F1288E8, // 70003792 
+0x0F122800, // 70003794 
+0x0F12D006, // 70003796 
+0x0F121FC1, // 70003798 
+0x0F1239FD, // 7000379A 
+0x0F12D003, // 7000379C 
+0x0F122001, // 7000379E 
+0x0F12BCF8, // 700037A0 
+0x0F12BC08, // 700037A2 
+0x0F124718, // 700037A4 
+0x0F122000, // 700037A6 
+0x0F12E7FA, // 700037A8 
+0x0F12B570, // 700037AA 
+0x0F124CAC, // 700037AC 
+0x0F128860, // 700037AE 
+0x0F122800, // 700037B0 
+0x0F12D00C, // 700037B2 
+0x0F128820, // 700037B4 
+0x0F124DA3, // 700037B6 
+0x0F122800, // 700037B8 
+0x0F12D009, // 700037BA 
+0x0F120029, // 700037BC 
+0x0F1231A0, // 700037BE 
+0x0F127AC9, // 700037C0 
+0x0F122900, // 700037C2 
+0x0F12D004, // 700037C4 
+0x0F127AA8, // 700037C6 
+0x0F122180, // 700037C8 
+0x0F124308, // 700037CA 
+0x0F1272A8, // 700037CC 
+0x0F12E73F, // 700037CE 
+0x0F122800, // 700037D0 
+0x0F12D003, // 700037D2 
+0x0F12F7FF, // 700037D4 
+0x0F12FFA7, // 700037D6 
+0x0F122800, // 700037D8 
+0x0F12D1F8, // 700037DA 
+0x0F122000, // 700037DC 
+0x0F128060, // 700037DE 
+0x0F128820, // 700037E0 
+0x0F122800, // 700037E2 
+0x0F12D003, // 700037E4 
+0x0F122008, // 700037E6 
+0x0F12F000, // 700037E8 
+0x0F12FAA2, // 700037EA 
+0x0F12E00B, // 700037EC 
+0x0F12489C, // 700037EE 
+0x0F123020, // 700037F0 
+0x0F128880, // 700037F2 
+0x0F122800, // 700037F4 
+0x0F12D103, // 700037F6 
+0x0F127AA8, // 700037F8 
+0x0F122101, // 700037FA 
+0x0F124308, // 700037FC 
+0x0F1272A8, // 700037FE 
+0x0F122010, // 70003800 
+0x0F12F000, // 70003802 
+0x0F12FA95, // 70003804 
+0x0F128820, // 70003806 
+0x0F122800, // 70003808 
+0x0F12D1E0, // 7000380A 
+0x0F12488A, // 7000380C 
+0x0F1289C0, // 7000380E 
+0x0F122801, // 70003810 
+0x0F12D1DC, // 70003812 
+0x0F127AA8, // 70003814 
+0x0F1221BF, // 70003816 
+0x0F124008, // 70003818 
+0x0F1272A8, // 7000381A 
+0x0F12E718, // 7000381C 
+0x0F126800, // 7000381E 
+0x0F124990, // 70003820 
+0x0F128188, // 70003822 
+0x0F124890, // 70003824 
+0x0F122201, // 70003826 
+0x0F128981, // 70003828 
+0x0F124890, // 7000382A 
+0x0F120252, // 7000382C 
+0x0F124291, // 7000382E 
+0x0F12D902, // 70003830 
+0x0F122102, // 70003832 
+0x0F128181, // 70003834 
+0x0F124770, // 70003836 
+0x0F122101, // 70003838 
+0x0F128181, // 7000383A 
+0x0F124770, // 7000383C 
+0x0F12B5F1, // 7000383E 
+0x0F124E80, // 70003840 
+0x0F128834, // 70003842 
+0x0F122C00, // 70003844 
+0x0F12D03F, // 70003846 
+0x0F122001, // 70003848 
+0x0F122C08, // 7000384A 
+0x0F12D000, // 7000384C 
+0x0F122000, // 7000384E 
+0x0F1270B0, // 70003850 
+0x0F124D7F, // 70003852 
+0x0F122800, // 70003854 
+0x0F12D009, // 70003856 
+0x0F12F000, // 70003858 
+0x0F12FA72, // 7000385A 
+0x0F120028, // 7000385C 
+0x0F1238F0, // 7000385E 
+0x0F126328, // 70003860 
+0x0F127AB0, // 70003862 
+0x0F12217E, // 70003864 
+0x0F124008, // 70003866 
+0x0F1272B0, // 70003868 
+0x0F12E00F, // 7000386A 
+0x0F124F7A, // 7000386C 
+0x0F123780, // 7000386E 
+0x0F128B78, // 70003870 
+0x0F122800, // 70003872 
+0x0F12D005, // 70003874 
+0x0F12F000, // 70003876 
+0x0F12FA6B, // 70003878 
+0x0F122000, // 7000387A 
+0x0F128378, // 7000387C 
+0x0F124976, // 7000387E 
+0x0F128708, // 70003880 
+0x0F122000, // 70003882 
+0x0F12F000, // 70003884 
+0x0F12FA6C, // 70003886 
+0x0F124879, // 70003888 
+0x0F126328, // 7000388A 
+0x0F1278B1, // 7000388C 
+0x0F122700, // 7000388E 
+0x0F120038, // 70003890 
+0x0F122900, // 70003892 
+0x0F12D008, // 70003894 
+0x0F124972, // 70003896 
+0x0F123920, // 70003898 
+0x0F128ACA, // 7000389A 
+0x0F122A00, // 7000389C 
+0x0F12D003, // 7000389E 
+0x0F128B09, // 700038A0 
+0x0F122900, // 700038A2 
+0x0F12D000, // 700038A4 
+0x0F122001, // 700038A6 
+0x0F127170, // 700038A8 
+0x0F122C02, // 700038AA 
+0x0F12D102, // 700038AC 
+0x0F124868, // 700038AE 
+0x0F123860, // 700038B0 
+0x0F126328, // 700038B2 
+0x0F122201, // 700038B4 
+0x0F122C02, // 700038B6 
+0x0F12D000, // 700038B8 
+0x0F122200, // 700038BA 
+0x0F124861, // 700038BC 
+0x0F122110, // 700038BE 
+0x0F12300A, // 700038C0 
+0x0F12F000, // 700038C2 
+0x0F12FA55, // 700038C4 
+0x0F128037, // 700038C6 
+0x0F129900, // 700038C8 
+0x0F120020, // 700038CA 
+0x0F12600C, // 700038CC 
+0x0F12E767, // 700038CE 
+0x0F12B538, // 700038D0 
+0x0F124865, // 700038D2 
+0x0F124669, // 700038D4 
+0x0F123848, // 700038D6 
+0x0F12F000, // 700038D8 
+0x0F12FA52, // 700038DA 
+0x0F124A5E, // 700038DC 
+0x0F124862, // 700038DE 
+0x0F128F51, // 700038E0 
+0x0F122400, // 700038E2 
+0x0F123020, // 700038E4 
+0x0F122900, // 700038E6 
+0x0F12D00A, // 700038E8 
+0x0F128754, // 700038EA 
+0x0F126941, // 700038EC 
+0x0F126451, // 700038EE 
+0x0F126491, // 700038F0 
+0x0F12466B, // 700038F2 
+0x0F128819, // 700038F4 
+0x0F1287D1, // 700038F6 
+0x0F12885B, // 700038F8 
+0x0F120011, // 700038FA 
+0x0F123140, // 700038FC 
+0x0F12800B, // 700038FE 
+0x0F128F91, // 70003900 
+0x0F122900, // 70003902 
+0x0F12D002, // 70003904 
+0x0F128794, // 70003906 
+0x0F126940, // 70003908 
+0x0F126490, // 7000390A 
+0x0F12F000, // 7000390C 
+0x0F12FA40, // 7000390E 
+0x0F12BC38, // 70003910 
+0x0F12BC08, // 70003912 
+0x0F124718, // 70003914 
+0x0F12B5F8, // 70003916 
+0x0F124C56, // 70003918 
+0x0F1289E0, // 7000391A 
+0x0F12F000, // 7000391C 
+0x0F12FA40, // 7000391E 
+0x0F120006, // 70003920 
+0x0F128A20, // 70003922 
+0x0F12F000, // 70003924 
+0x0F12FA44, // 70003926 
+0x0F120007, // 70003928 
+0x0F12484F, // 7000392A 
+0x0F124D4A, // 7000392C 
+0x0F123020, // 7000392E 
+0x0F126CA9, // 70003930 
+0x0F126940, // 70003932 
+0x0F121809, // 70003934 
+0x0F120200, // 70003936 
+0x0F12F000, // 70003938 
+0x0F12FA42, // 7000393A 
+0x0F120400, // 7000393C 
+0x0F120C00, // 7000393E 
+0x0F12002A, // 70003940 
+0x0F12326E, // 70003942 
+0x0F120011, // 70003944 
+0x0F12390A, // 70003946 
+0x0F122305, // 70003948 
+0x0F12F000, // 7000394A 
+0x0F12FA3F, // 7000394C 
+0x0F124C43, // 7000394E 
+0x0F1261A0, // 70003950 
+0x0F128FEB, // 70003952 
+0x0F120002, // 70003954 
+0x0F120031, // 70003956 
+0x0F120018, // 70003958 
+0x0F12F000, // 7000395A 
+0x0F12FA3F, // 7000395C 
+0x0F12466B, // 7000395E 
+0x0F120005, // 70003960 
+0x0F128018, // 70003962 
+0x0F12483C, // 70003964 
+0x0F1269A2, // 70003966 
+0x0F123040, // 70003968 
+0x0F128800, // 7000396A 
+0x0F120039, // 7000396C 
+0x0F12F000, // 7000396E 
+0x0F12FA35, // 70003970 
+0x0F12466B, // 70003972 
+0x0F120006, // 70003974 
+0x0F128058, // 70003976 
+0x0F120021, // 70003978 
+0x0F129800, // 7000397A 
+0x0F12311C, // 7000397C 
+0x0F12F000, // 7000397E 
+0x0F12FA35, // 70003980 
+0x0F124935, // 70003982 
+0x0F123180, // 70003984 
+0x0F12808D, // 70003986 
+0x0F1280CE, // 70003988 
+0x0F128BA1, // 7000398A 
+0x0F124836, // 7000398C 
+0x0F123820, // 7000398E 
+0x0F128001, // 70003990 
+0x0F128BE1, // 70003992 
+0x0F128041, // 70003994 
+0x0F128C21, // 70003996 
+0x0F128081, // 70003998 
+0x0F12E701, // 7000399A 
+0x0F12B5F8, // 7000399C 
+0x0F124E2E, // 7000399E 
+0x0F126C70, // 700039A0 
+0x0F126CB1, // 700039A2 
+0x0F120200, // 700039A4 
+0x0F12F000, // 700039A6 
+0x0F12FA0B, // 700039A8 
+0x0F120400, // 700039AA 
+0x0F120C00, // 700039AC 
+0x0F122401, // 700039AE 
+0x0F120364, // 700039B0 
+0x0F1242A0, // 700039B2 
+0x0F12D200, // 700039B4 
+0x0F120004, // 700039B6 
+0x0F124A27, // 700039B8 
+0x0F120020, // 700039BA 
+0x0F12327E, // 700039BC 
+0x0F121F91, // 700039BE 
+0x0F122303, // 700039C0 
+0x0F12F000, // 700039C2 
+0x0F12FA03, // 700039C4 
+0x0F120405, // 700039C6 
+0x0F120C2D, // 700039C8 
+0x0F124A23, // 700039CA 
+0x0F120020, // 700039CC 
+0x0F12325A, // 700039CE 
+0x0F120011, // 700039D0 
+0x0F12390A, // 700039D2 
+0x0F122305, // 700039D4 
+0x0F12F000, // 700039D6 
+0x0F12F9F9, // 700039D8 
+0x0F12491F, // 700039DA 
+0x0F1264C8, // 700039DC 
+0x0F12491F, // 700039DE 
+0x0F124E21, // 700039E0 
+0x0F1288C8, // 700039E2 
+0x0F122701, // 700039E4 
+0x0F122800, // 700039E6 
+0x0F12D009, // 700039E8 
+0x0F124C23, // 700039EA 
+0x0F1238FF, // 700039EC 
+0x0F121E40, // 700039EE 
+0x0F12D00A, // 700039F0 
+0x0F122804, // 700039F2 
+0x0F12D042, // 700039F4 
+0x0F122806, // 700039F6 
+0x0F12D101, // 700039F8 
+0x0F122000, // 700039FA 
+0x0F1280C8, // 700039FC 
+0x0F1282B7, // 700039FE 
+0x0F122001, // 70003A00 
+0x0F12F000, // 70003A02 
+0x0F12F9FB, // 70003A04 
+0x0F12E6CB, // 70003A06 
+0x0F12000D, // 70003A08 
+0x0F12724F, // 70003A0A 
+0x0F122001, // 70003A0C 
+0x0F12F000, // 70003A0E 
+0x0F12F9FD, // 70003A10 
+0x0F12F000, // 70003A12 
+0x0F12FA03, // 70003A14 
+0x0F124910, // 70003A16 
+0x0F123148, // 70003A18 
+0x0F12C903, // 70003A1A 
+0x0F124348, // 70003A1C 
+0x0F120A00, // 70003A1E 
+0x0F126160, // 70003A20 
+0x0F1220FF, // 70003A22 
+0x0F121D40, // 70003A24 
+0x0F1280E8, // 70003A26 
+0x0F12480C, // 70003A28 
+0x0F123040, // 70003A2A 
+0x0F127707, // 70003A2C 
+0x0F12E7E6, // 70003A2E 
+0x0F123290, // 70003A30 
+0x0F127000, // 70003A32 
+0x0F123294, // 70003A34 
+0x0F127000, // 70003A36 
+0x0F1204A8, // 70003A38 
+0x0F127000, // 70003A3A 
+0x0F1215DC, // 70003A3C 
+0x0F127000, // 70003A3E 
+0x0F125000, // 70003A40 
+0x0F12D000, // 70003A42 
+0x0F121E84, // 70003A44 
+0x0F127000, // 70003A46 
+0x0F121BE4, // 70003A48 
+0x0F127000, // 70003A4A 
+0x0F122EA8, // 70003A4C 
+0x0F127000, // 70003A4E 
+0x0F1221A4, // 70003A50 
+0x0F127000, // 70003A52 
+0x0F120100, // 70003A54 
+0x0F127000, // 70003A56 
+0x0F123F48, // 70003A58 
+0x0F127000, // 70003A5A 
+0x0F1231A0, // 70003A5C 
+0x0F127000, // 70003A5E 
+0x0F1201E8, // 70003A60 
+0x0F127000, // 70003A62 
+0x0F12F2A0, // 70003A64 
+0x0F12D000, // 70003A66 
+0x0F122A44, // 70003A68 
+0x0F127000, // 70003A6A 
+0x0F12F400, // 70003A6C 
+0x0F12D000, // 70003A6E 
+0x0F122024, // 70003A70 
+0x0F127000, // 70003A72 
+0x0F121650, // 70003A74 
+0x0F127000, // 70003A76 
+0x0F122A64, // 70003A78 
+0x0F127000, // 70003A7A 
+0x0F124982, // 70003A7C 
+0x0F12724F, // 70003A7E 
+0x0F1220FF, // 70003A80 
+0x0F121DC0, // 70003A82 
+0x0F1280C8, // 70003A84 
+0x0F12F000, // 70003A86 
+0x0F12F9D1, // 70003A88 
+0x0F124980, // 70003A8A 
+0x0F126ACA, // 70003A8C 
+0x0F12604A, // 70003A8E 
+0x0F122800, // 70003A90 
+0x0F12D006, // 70003A92 
+0x0F12436A, // 70003A94 
+0x0F120001, // 70003A96 
+0x0F120010, // 70003A98 
+0x0F12F000, // 70003A9A 
+0x0F12F991, // 70003A9C 
+0x0F126160, // 70003A9E 
+0x0F12E001, // 70003AA0 
+0x0F12436A, // 70003AA2 
+0x0F126162, // 70003AA4 
+0x0F128BF0, // 70003AA6 
+0x0F122800, // 70003AA8 
+0x0F12D001, // 70003AAA 
+0x0F12F7FF, // 70003AAC 
+0x0F12FF33, // 70003AAE 
+0x0F122000, // 70003AB0 
+0x0F12F000, // 70003AB2 
+0x0F12F9AB, // 70003AB4 
+0x0F124974, // 70003AB6 
+0x0F1220FF, // 70003AB8 
+0x0F121DC0, // 70003ABA 
+0x0F1280C8, // 70003ABC 
+0x0F12E79E, // 70003ABE 
+0x0F12B510, // 70003AC0 
+0x0F12F000, // 70003AC2 
+0x0F12F9BB, // 70003AC4 
+0x0F124870, // 70003AC6 
+0x0F1288C0, // 70003AC8 
+0x0F121FC1, // 70003ACA 
+0x0F1239FD, // 70003ACC 
+0x0F12D103, // 70003ACE 
+0x0F12496F, // 70003AD0 
+0x0F1220FF, // 70003AD2 
+0x0F121C40, // 70003AD4 
+0x0F128048, // 70003AD6 
+0x0F12E605, // 70003AD8 
+0x0F12B5F8, // 70003ADA 
+0x0F122400, // 70003ADC 
+0x0F124D6D, // 70003ADE 
+0x0F12486D, // 70003AE0 
+0x0F12210E, // 70003AE2 
+0x0F128041, // 70003AE4 
+0x0F122101, // 70003AE6 
+0x0F128001, // 70003AE8 
+0x0F12F000, // 70003AEA 
+0x0F12F9AF, // 70003AEC 
+0x0F12486B, // 70003AEE 
+0x0F128840, // 70003AF0 
+0x0F12F000, // 70003AF2 
+0x0F12F9B3, // 70003AF4 
+0x0F124E6A, // 70003AF6 
+0x0F12270D, // 70003AF8 
+0x0F12073F, // 70003AFA 
+0x0F1219E8, // 70003AFC 
+0x0F128803, // 70003AFE 
+0x0F1200E2, // 70003B00 
+0x0F121991, // 70003B02 
+0x0F12804B, // 70003B04 
+0x0F128843, // 70003B06 
+0x0F1252B3, // 70003B08 
+0x0F128882, // 70003B0A 
+0x0F1280CA, // 70003B0C 
+0x0F1288C0, // 70003B0E 
+0x0F128088, // 70003B10 
+0x0F123508, // 70003B12 
+0x0F12042D, // 70003B14 
+0x0F120C2D, // 70003B16 
+0x0F121C64, // 70003B18 
+0x0F120424, // 70003B1A 
+0x0F120C24, // 70003B1C 
+0x0F122C07, // 70003B1E 
+0x0F12D3EC, // 70003B20 
+0x0F12E63D, // 70003B22 
+0x0F12B5F0, // 70003B24 
+0x0F12B085, // 70003B26 
+0x0F126801, // 70003B28 
+0x0F129103, // 70003B2A 
+0x0F126881, // 70003B2C 
+0x0F12040A, // 70003B2E 
+0x0F120C12, // 70003B30 
+0x0F12495C, // 70003B32 
+0x0F128B89, // 70003B34 
+0x0F122900, // 70003B36 
+0x0F12D001, // 70003B38 
+0x0F120011, // 70003B3A 
+0x0F12E000, // 70003B3C 
+0x0F122100, // 70003B3E 
+0x0F129102, // 70003B40 
+0x0F126840, // 70003B42 
+0x0F120401, // 70003B44 
+0x0F129803, // 70003B46 
+0x0F120C09, // 70003B48 
+0x0F12F000, // 70003B4A 
+0x0F12F98F, // 70003B4C 
+0x0F124854, // 70003B4E 
+0x0F123080, // 70003B50 
+0x0F128900, // 70003B52 
+0x0F122800, // 70003B54 
+0x0F12D039, // 70003B56 
+0x0F122100, // 70003B58 
+0x0F124854, // 70003B5A 
+0x0F124D52, // 70003B5C 
+0x0F124684, // 70003B5E 
+0x0F124B53, // 70003B60 
+0x0F124C4F, // 70003B62 
+0x0F1288DA, // 70003B64 
+0x0F120048, // 70003B66 
+0x0F1200D7, // 70003B68 
+0x0F12193E, // 70003B6A 
+0x0F12197F, // 70003B6C 
+0x0F12183F, // 70003B6E 
+0x0F125A36, // 70003B70 
+0x0F128AFF, // 70003B72 
+0x0F12437E, // 70003B74 
+0x0F1200B6, // 70003B76 
+0x0F120C37, // 70003B78 
+0x0F121906, // 70003B7A 
+0x0F123680, // 70003B7C 
+0x0F128177, // 70003B7E 
+0x0F121C52, // 70003B80 
+0x0F1200D2, // 70003B82 
+0x0F121914, // 70003B84 
+0x0F121952, // 70003B86 
+0x0F121812, // 70003B88 
+0x0F125A24, // 70003B8A 
+0x0F128AD2, // 70003B8C 
+0x0F124354, // 70003B8E 
+0x0F1200A2, // 70003B90 
+0x0F120C12, // 70003B92 
+0x0F128272, // 70003B94 
+0x0F12891C, // 70003B96 
+0x0F12895B, // 70003B98 
+0x0F124367, // 70003B9A 
+0x0F12435A, // 70003B9C 
+0x0F121943, // 70003B9E 
+0x0F123340, // 70003BA0 
+0x0F1289DB, // 70003BA2 
+0x0F129C02, // 70003BA4 
+0x0F1218BA, // 70003BA6 
+0x0F124363, // 70003BA8 
+0x0F1218D2, // 70003BAA 
+0x0F120212, // 70003BAC 
+0x0F120C12, // 70003BAE 
+0x0F12466B, // 70003BB0 
+0x0F12521A, // 70003BB2 
+0x0F124663, // 70003BB4 
+0x0F127DDB, // 70003BB6 
+0x0F12435A, // 70003BB8 
+0x0F129B03, // 70003BBA 
+0x0F120252, // 70003BBC 
+0x0F120C12, // 70003BBE 
+0x0F12521A, // 70003BC0 
+0x0F121C49, // 70003BC2 
+0x0F120409, // 70003BC4 
+0x0F120C09, // 70003BC6 
+0x0F122904, // 70003BC8 
+0x0F12D3C9, // 70003BCA 
+0x0F12B005, // 70003BCC 
+0x0F12BCF0, // 70003BCE 
+0x0F12BC08, // 70003BD0 
+0x0F124718, // 70003BD2 
+0x0F12B510, // 70003BD4 
+0x0F12F7FF, // 70003BD6 
+0x0F12FF80, // 70003BD8 
+0x0F12F000, // 70003BDA 
+0x0F12F94F, // 70003BDC 
+0x0F12E582, // 70003BDE 
+0x0F12B570, // 70003BE0 
+0x0F126804, // 70003BE2 
+0x0F12F000, // 70003BE4 
+0x0F12F952, // 70003BE6 
+0x0F124D32, // 70003BE8 
+0x0F128C29, // 70003BEA 
+0x0F121A40, // 70003BEC 
+0x0F1242A0, // 70003BEE 
+0x0F12D901, // 70003BF0 
+0x0F120020, // 70003BF2 
+0x0F12E003, // 70003BF4 
+0x0F12F000, // 70003BF6 
+0x0F12F949, // 70003BF8 
+0x0F128C29, // 70003BFA 
+0x0F121A40, // 70003BFC 
+0x0F126268, // 70003BFE 
+0x0F12F000, // 70003C00 
+0x0F12F94C, // 70003C02 
+0x0F1262A8, // 70003C04 
+0x0F12F000, // 70003C06 
+0x0F12F951, // 70003C08 
+0x0F126328, // 70003C0A 
+0x0F128869, // 70003C0C 
+0x0F122900, // 70003C0E 
+0x0F12D000, // 70003C10 
+0x0F1262A8, // 70003C12 
+0x0F124828, // 70003C14 
+0x0F126B00, // 70003C16 
+0x0F128C00, // 70003C18 
+0x0F122800, // 70003C1A 
+0x0F12D11B, // 70003C1C 
+0x0F126AA8, // 70003C1E 
+0x0F12F000, // 70003C20 
+0x0F12F94C, // 70003C22 
+0x0F1261E8, // 70003C24 
+0x0F124A1E, // 70003C26 
+0x0F123280, // 70003C28 
+0x0F128B91, // 70003C2A 
+0x0F122900, // 70003C2C 
+0x0F12D00B, // 70003C2E 
+0x0F120011, // 70003C30 
+0x0F123120, // 70003C32 
+0x0F128809, // 70003C34 
+0x0F124288, // 70003C36 
+0x0F12D907, // 70003C38 
+0x0F1261E9, // 70003C3A 
+0x0F128C28, // 70003C3C 
+0x0F121A08, // 70003C3E 
+0x0F1262A8, // 70003C40 
+0x0F12F000, // 70003C42 
+0x0F12F92B, // 70003C44 
+0x0F1262A8, // 70003C46 
+0x0F12E502, // 70003C48 
+0x0F128BD1, // 70003C4A 
+0x0F124288, // 70003C4C 
+0x0F12D800, // 70003C4E 
+0x0F120008, // 70003C50 
+0x0F1261E8, // 70003C52 
+0x0F12E4FC, // 70003C54 
+0x0F12F000, // 70003C56 
+0x0F12F919, // 70003C58 
+0x0F1261E8, // 70003C5A 
+0x0F12E4F8, // 70003C5C 
+0x0F12B510, // 70003C5E 
+0x0F12F000, // 70003C60 
+0x0F12F934, // 70003C62 
+0x0F12480E, // 70003C64 
+0x0F1230A0, // 70003C66 
+0x0F128841, // 70003C68 
+0x0F122900, // 70003C6A 
+0x0F12D007, // 70003C6C 
+0x0F124A07, // 70003C6E 
+0x0F123280, // 70003C70 
+0x0F126953, // 70003C72 
+0x0F124A11, // 70003C74 
+0x0F12428B, // 70003C76 
+0x0F12D202, // 70003C78 
+0x0F128880, // 70003C7A 
+0x0F1281D0, // 70003C7C 
+0x0F12E532, // 70003C7E 
+0x0F1288C0, // 70003C80 
+0x0F1281D0, // 70003C82 
+0x0F12E52F, // 70003C84 
+0x0F120000, // 70003C86 
+0x0F1231A0, // 70003C88 
+0x0F127000, // 70003C8A 
+0x0F1229E4, // 70003C8C 
+0x0F127000, // 70003C8E 
+0x0F12C100, // 70003C90 
+0x0F12D000, // 70003C92 
+0x0F12A006, // 70003C94 
+0x0F120000, // 70003C96 
+0x0F12A000, // 70003C98 
+0x0F12D000, // 70003C9A 
+0x0F12064C, // 70003C9C 
+0x0F127000, // 70003C9E 
+0x0F123F48, // 70003CA0 
+0x0F127000, // 70003CA2 
+0x0F1207C4, // 70003CA4 
+0x0F127000, // 70003CA6 
+0x0F1207E8, // 70003CA8 
+0x0F127000, // 70003CAA 
+0x0F122B24, // 70003CAC 
+0x0F127000, // 70003CAE 
+0x0F121FA0, // 70003CB0 
+0x0F127000, // 70003CB2 
+0x0F121E3C, // 70003CB4 
+0x0F127000, // 70003CB6 
+0x0F1221A4, // 70003CB8 
+0x0F127000, // 70003CBA 
+0x0F12E200, // 70003CBC 
+0x0F12D000, // 70003CBE 
+0x0F124778, // 70003CC0 
+0x0F1246C0, // 70003CC2 
+0x0F12C000, // 70003CC4 
+0x0F12E59F, // 70003CC6 
+0x0F12FF1C, // 70003CC8 
+0x0F12E12F, // 70003CCA 
+0x0F121F63, // 70003CCC 
+0x0F120001, // 70003CCE 
+0x0F124778, // 70003CD0 
+0x0F1246C0, // 70003CD2 
+0x0F12C000, // 70003CD4 
+0x0F12E59F, // 70003CD6 
+0x0F12FF1C, // 70003CD8 
+0x0F12E12F, // 70003CDA 
+0x0F121EDF, // 70003CDC 
+0x0F120001, // 70003CDE 
+0x0F124778, // 70003CE0 
+0x0F1246C0, // 70003CE2 
+0x0F12C000, // 70003CE4 
+0x0F12E59F, // 70003CE6 
+0x0F12FF1C, // 70003CE8 
+0x0F12E12F, // 70003CEA 
+0x0F12495F, // 70003CEC 
+0x0F120000, // 70003CEE 
+0x0F124778, // 70003CF0 
+0x0F1246C0, // 70003CF2 
+0x0F12C000, // 70003CF4 
+0x0F12E59F, // 70003CF6 
+0x0F12FF1C, // 70003CF8 
+0x0F12E12F, // 70003CFA 
+0x0F12E403, // 70003CFC 
+0x0F120000, // 70003CFE 
+0x0F124778, // 70003D00 
+0x0F1246C0, // 70003D02 
+0x0F12C000, // 70003D04 
+0x0F12E59F, // 70003D06 
+0x0F12FF1C, // 70003D08 
+0x0F12E12F, // 70003D0A 
+0x0F1224B3, // 70003D0C 
+0x0F120001, // 70003D0E 
+0x0F124778, // 70003D10 
+0x0F1246C0, // 70003D12 
+0x0F12C000, // 70003D14 
+0x0F12E59F, // 70003D16 
+0x0F12FF1C, // 70003D18 
+0x0F12E12F, // 70003D1A 
+0x0F12EECD, // 70003D1C 
+0x0F120000, // 70003D1E 
+0x0F124778, // 70003D20 
+0x0F1246C0, // 70003D22 
+0x0F12C000, // 70003D24 
+0x0F12E59F, // 70003D26 
+0x0F12FF1C, // 70003D28 
+0x0F12E12F, // 70003D2A 
+0x0F12F049, // 70003D2C 
+0x0F120000, // 70003D2E 
+0x0F124778, // 70003D30 
+0x0F1246C0, // 70003D32 
+0x0F12C000, // 70003D34 
+0x0F12E59F, // 70003D36 
+0x0F12FF1C, // 70003D38 
+0x0F12E12F, // 70003D3A 
+0x0F1212DF, // 70003D3C 
+0x0F120000, // 70003D3E 
+0x0F124778, // 70003D40 
+0x0F1246C0, // 70003D42 
+0x0F12C000, // 70003D44 
+0x0F12E59F, // 70003D46 
+0x0F12FF1C, // 70003D48 
+0x0F12E12F, // 70003D4A 
+0x0F12F05B, // 70003D4C 
+0x0F120000, // 70003D4E 
+0x0F124778, // 70003D50 
+0x0F1246C0, // 70003D52 
+0x0F12C000, // 70003D54 
+0x0F12E59F, // 70003D56 
+0x0F12FF1C, // 70003D58 
+0x0F12E12F, // 70003D5A 
+0x0F12F07B, // 70003D5C 
+0x0F120000, // 70003D5E 
+0x0F124778, // 70003D60 
+0x0F1246C0, // 70003D62 
+0x0F12C000, // 70003D64 
+0x0F12E59F, // 70003D66 
+0x0F12FF1C, // 70003D68 
+0x0F12E12F, // 70003D6A 
+0x0F12FE6D, // 70003D6C 
+0x0F120000, // 70003D6E 
+0x0F124778, // 70003D70 
+0x0F1246C0, // 70003D72 
+0x0F12C000, // 70003D74 
+0x0F12E59F, // 70003D76 
+0x0F12FF1C, // 70003D78 
+0x0F12E12F, // 70003D7A 
+0x0F123295, // 70003D7C 
+0x0F120000, // 70003D7E 
+0x0F124778, // 70003D80 
+0x0F1246C0, // 70003D82 
+0x0F12C000, // 70003D84 
+0x0F12E59F, // 70003D86 
+0x0F12FF1C, // 70003D88 
+0x0F12E12F, // 70003D8A 
+0x0F12234F, // 70003D8C 
+0x0F120000, // 70003D8E 
+0x0F124778, // 70003D90 
+0x0F1246C0, // 70003D92 
+0x0F12C000, // 70003D94 
+0x0F12E59F, // 70003D96 
+0x0F12FF1C, // 70003D98 
+0x0F12E12F, // 70003D9A 
+0x0F124521, // 70003D9C 
+0x0F120000, // 70003D9E 
+0x0F124778, // 70003DA0 
+0x0F1246C0, // 70003DA2 
+0x0F12C000, // 70003DA4 
+0x0F12E59F, // 70003DA6 
+0x0F12FF1C, // 70003DA8 
+0x0F12E12F, // 70003DAA 
+0x0F127C0D, // 70003DAC 
+0x0F120000, // 70003DAE 
+0x0F124778, // 70003DB0 
+0x0F1246C0, // 70003DB2 
+0x0F12C000, // 70003DB4 
+0x0F12E59F, // 70003DB6 
+0x0F12FF1C, // 70003DB8 
+0x0F12E12F, // 70003DBA 
+0x0F127C2B, // 70003DBC 
+0x0F120000, // 70003DBE 
+0x0F124778, // 70003DC0 
+0x0F1246C0, // 70003DC2 
+0x0F12F004, // 70003DC4 
+0x0F12E51F, // 70003DC6 
+0x0F1224C4, // 70003DC8 
+0x0F120001, // 70003DCA 
+0x0F124778, // 70003DCC 
+0x0F1246C0, // 70003DCE 
+0x0F12C000, // 70003DD0 
+0x0F12E59F, // 70003DD2 
+0x0F12FF1C, // 70003DD4 
+0x0F12E12F, // 70003DD6 
+0x0F123183, // 70003DD8 
+0x0F120000, // 70003DDA 
+0x0F124778, // 70003DDC 
+0x0F1246C0, // 70003DDE 
+0x0F12C000, // 70003DE0 
+0x0F12E59F, // 70003DE2 
+0x0F12FF1C, // 70003DE4 
+0x0F12E12F, // 70003DE6 
+0x0F12302F, // 70003DE8 
+0x0F120000, // 70003DEA 
+0x0F124778, // 70003DEC 
+0x0F1246C0, // 70003DEE 
+0x0F12C000, // 70003DF0 
+0x0F12E59F, // 70003DF2 
+0x0F12FF1C, // 70003DF4 
+0x0F12E12F, // 70003DF6 
+0x0F12EF07, // 70003DF8 
+0x0F120000, // 70003DFA 
+0x0F124778, // 70003DFC 
+0x0F1246C0, // 70003DFE 
+0x0F12C000, // 70003E00 
+0x0F12E59F, // 70003E02 
+0x0F12FF1C, // 70003E04 
+0x0F12E12F, // 70003E06 
+0x0F1248FB, // 70003E08 
+0x0F120000, // 70003E0A 
+0x0F124778, // 70003E0C 
+0x0F1246C0, // 70003E0E 
+0x0F12C000, // 70003E10 
+0x0F12E59F, // 70003E12 
+0x0F12FF1C, // 70003E14 
+0x0F12E12F, // 70003E16 
+0x0F12F0B1, // 70003E18 
+0x0F120000, // 70003E1A 
+0x0F124778, // 70003E1C 
+0x0F1246C0, // 70003E1E 
+0x0F12C000, // 70003E20 
+0x0F12E59F, // 70003E22 
+0x0F12FF1C, // 70003E24 
+0x0F12E12F, // 70003E26 
+0x0F12EEDF, // 70003E28 
+0x0F120000, // 70003E2A 
+0x0F124778, // 70003E2C 
+0x0F1246C0, // 70003E2E 
+0x0F12C000, // 70003E30 
+0x0F12E59F, // 70003E32 
+0x0F12FF1C, // 70003E34 
+0x0F12E12F, // 70003E36 
+0x0F12AEF1, // 70003E38 
+0x0F120000, // 70003E3A 
+0x0F124778, // 70003E3C 
+0x0F1246C0, // 70003E3E 
+0x0F12C000, // 70003E40 
+0x0F12E59F, // 70003E42 
+0x0F12FF1C, // 70003E44 
+0x0F12E12F, // 70003E46 
+0x0F1202EB, // 70003E48 
+0x0F120001, // 70003E4A 
+0x0F124778, // 70003E4C 
+0x0F1246C0, // 70003E4E 
+0x0F12C000, // 70003E50 
+0x0F12E59F, // 70003E52 
+0x0F12FF1C, // 70003E54 
+0x0F12E12F, // 70003E56 
+0x0F12FD21, // 70003E58 
+0x0F120000, // 70003E5A 
+0x0F124778, // 70003E5C 
+0x0F1246C0, // 70003E5E 
+0x0F12C000, // 70003E60 
+0x0F12E59F, // 70003E62 
+0x0F12FF1C, // 70003E64 
+0x0F12E12F, // 70003E66 
+0x0F12FDAF, // 70003E68 
+0x0F120000, // 70003E6A 
+0x0F124778, // 70003E6C 
+0x0F1246C0, // 70003E6E 
+0x0F12C000, // 70003E70 
+0x0F12E59F, // 70003E72 
+0x0F12FF1C, // 70003E74 
+0x0F12E12F, // 70003E76 
+0x0F125027, // 70003E78 
+0x0F120000, // 70003E7A 
+0x0F124778, // 70003E7C 
+0x0F1246C0, // 70003E7E 
+0x0F12C000, // 70003E80 
+0x0F12E59F, // 70003E82 
+0x0F12FF1C, // 70003E84 
+0x0F12E12F, // 70003E86 
+0x0F1204C9, // 70003E88 
+0x0F120000, // 70003E8A 
+0x0F124778, // 70003E8C 
+0x0F1246C0, // 70003E8E 
+0x0F12C000, // 70003E90 
+0x0F12E59F, // 70003E92 
+0x0F12FF1C, // 70003E94 
+0x0F12E12F, // 70003E96 
+0x0F1239DF, // 70003E98 
+0x0F120000, // 70003E9A 
+0x0F124778, // 70003E9C 
+0x0F1246C0, // 70003E9E 
+0x0F12C000, // 70003EA0 
+0x0F12E59F, // 70003EA2 
+0x0F12FF1C, // 70003EA4 
+0x0F12E12F, // 70003EA6 
+0x0F126177, // 70003EA8 
+0x0F120000, // 70003EAA 
+0x0F124778, // 70003EAC 
+0x0F1246C0, // 70003EAE 
+0x0F12C000, // 70003EB0 
+0x0F12E59F, // 70003EB2 
+0x0F12FF1C, // 70003EB4 
+0x0F12E12F, // 70003EB6 
+0x0F12424F, // 70003EB8 
+0x0F120000, // 70003EBA 
+0x0F124778, // 70003EBC 
+0x0F1246C0, // 70003EBE 
+0x0F12C000, // 70003EC0 
+0x0F12E59F, // 70003EC2 
+0x0F12FF1C, // 70003EC4 
+0x0F12E12F, // 70003EC6 
+0x0F123F0D, // 70003EC8 
+0x0F120000, // 70003ECA 
+0x0F124778, // 70003ECC 
+0x0F1246C0, // 70003ECE 
+0x0F12C000, // 70003ED0 
+0x0F12E59F, // 70003ED2 
+0x0F12FF1C, // 70003ED4 
+0x0F12E12F, // 70003ED6 
+0x0F1202B9, // 70003ED8 
+0x0F120001, // 70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007, // clks_src_gf_force_enable
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120000, // on/off AFIT by NB option
+
+0x0F120005, // NormBR[0]
+0x0F120019, // NormBR[1]
+0x0F120050, // NormBR[2]
+0x0F120300, // NormBR[3]
+0x0F120375, // NormBR[4]
+
+// Flash
+0x002A3F82,
+0x0F120000,	// TNP_Regs_PreflashStart
+0x0F120000,	// TNP_Regs_PreflashEnd
+0x0F120260,	// TNP_Regs_PreWP_r
+0x0F120240, // TNP_Regs_PreWP_b
+
+0x002A3F98,	// BR Tuning
+0x0F120100,	// TNP_Regs_BrRatioIn_0_
+0x0F120180,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120080, /* TNP_Regs_BrRatioOut_0_ */
+0x0F120050,
+0x0F120040,
+0x0F120030,
+0x0F120020,
+
+0x0F120030,	// WP Tuning
+0x0F120040,	// TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	// T_BR tune	
+0x0F120150,	// TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F120048, //3C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B, //3B,
+0x0F12002E, //2E,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,		
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120235, //0244 0258 AWB R point          //0258 0245 0258
+0x0F12024A, //024D 0220 AWB B point          //0220 0245 0245
+
+
+//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //         
+//         ///
+// Analog & APS settings         //         //         //         //         /  ///
+// This register is for FACTORY ONLY. If you change it without prior notificat
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future         
+//         //         //         //         //         //         //         /  //         //         //         //         //         //         //         //         
+//         ///
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, // adc_sat[7:0]=84d (500mV)
+0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, // rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, // pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, // clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001, // ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+0x002AF42E,
+0x0F120406, // fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+0x002AF434,
+0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, // reg_tune_pix[7:0]
+0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, // reg_tune_rg[7:0] (2.83V)
+0x0F120004, // reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, // blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, // srx_en[0]
+
+0x002A0054,
+0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, // div_dbr[7:4]
+
+0x002AF132,
+0x0F120206, // tgr_frame_decription 4
+0x002AF152,
+0x0F120206, // tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, // tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, // tgr_frame_params_descriptor_6
+//===========================================================================================
+
+//============================= Line-ADLC Tuning ============================================
+0x002AE412,
+0x0F120008, // adlc_tune_offset_gr[7:0]
+0x0F120008, // adlc_tune_offset_r[7:0]
+0x0F120010, // adlc_tune_offset_b[7:0]
+0x0F120010, // adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, // adlc_qec[2:0]
+//===========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F120132, //0138//awbb_IntcR
+0x0F12010A, //011C//awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041, //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C, //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for SDA
+0x0F120190, //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000 //#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120003, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120602, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120003, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200CC, //#af_search_usPeakThr  for 80%
+0x0F1200A0,          //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F12952F, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120010, //#af_pos_usTableLastInd 10h + 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120033, //#af_pos_usTable_1_  51   
+0x0F120036, //#af_pos_usTable_2_  54	
+0x0F120039, //#af_pos_usTable_3_  57	
+0x0F12003D, //#af_pos_usTable_4_  61   
+0x0F120041, //#af_pos_usTable_5_  65	
+0x0F120045, //#af_pos_usTable_6_  69	
+0x0F120049, //#af_pos_usTable_7_  73	
+0x0F12004E, //#af_pos_usTable_8_  78	
+0x0F120053, //#af_pos_usTable_9_  83	
+0x0F120059, //#af_pos_usTable_10_ 89	
+0x0F120060, //#af_pos_usTable_11_ 104	
+0x0F120068, //#af_pos_usTable_12_ 109	
+0x0F120072, //#af_pos_usTable_13_ 114	
+0x0F12007D, //#af_pos_usTable_14_ 125
+0x0F120089, //#af_pos_usTable_15_ 137	
+0x0F120096, //#af_pos_usTable_16_ 150
+
+//8. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120020, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120008, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120008, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is in use          // 0 : do not use 1 : use
+0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12005C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000, //senHal_bSRX //SRX off
+
+0x002A1680,
+0x0F120002, //senHal_NExpLinesCheckFine//0004//extend Forbidden area line
+
+0x002A0ED2,
+0x0F120FA0,	//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PLA 3:CA
+0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK   
+0x002A0188,
+0x0F125DC0,                   //REG_TC_IPRM_InClockLSBs
+0x0F120000,                   //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001,                   //REG_TC_IPRM_UseNPviClocks
+0x0F120002,                   //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001,                   //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+//SCLK & PCLK                    // clock set 0
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+//SCLK & PCLK                    // clock set 1
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz
+
+	//SCLK & PCLK                    // clock set 2                               
+0x0F1238A4,	                  //38A4	                  //36B0	                  //34BC	                  //32C8	                  //REG_TC_IPRM_OpClk4KHz_0	                  //52Mhz          
+0x0F1254F0,	                  //4E20	                  //3A98	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MinOutRate4KHz_0	                  //54Mhz  
+0x0F1254F8,	                  //57E4	                  //61A8	                  //7148	                  //4B32	                  //34BC	                  //REG_TC_IPRM_MaxOutRate4KHz_0	                  //54Mhz  
+
+0x002A1B78,
+0x0F1238A4,                           //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_0__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4,                           //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_1__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4,                           //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074,                           //  REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004,                           //  REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000,                           //  REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002,                           //  REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003,                           //  REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001,                           //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006,                           //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C,                           //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0,                           //  REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6,                           //  REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C,                           //  REGM_gSensorClocks_2__usSysDiv
+0x0F120001,                           //  REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001,                   //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A,     //p10
+
+
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6,
+0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 640 480 system 52M PCLK 87M
+//===================================================================
+0x002A023E,
+0x0F120400, //REG_0TC_PCFG_usWidth
+0x0F120300, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120001, //REG_0TC_PCFG_FrRateQualityType
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+#if 1 /* fix 180 rotation to 0*/
+0x0F120000, //REG_0TC_PCFG_uPrevMirror
+0x0F120000, //REG_0TC_PCFG_uCaptureMirror
+#endif
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 87M
+//===================================================================
+
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+            
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV   9:JPEG
+0x0F1254F6, //REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6, //REG_0TC_CCFG_usMinOut4KHzRate
+            
+0x002A033E, 
+0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+            
+0x002A0346, 
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+            
+0x002A0426, 
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+            
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+//===================================================================
+// Capture 1 640x480 system 52M PCLK 87M
+//===================================================================
+0x002A035A,
+0x0F120000,                   //REG_1TC_CCFG_uCaptureMode
+
+0x0F120280,                   //REG_1TC_CCFG_usWidth
+0x0F1201E0,                   //REG_1TC_CCFG_usHeight
+0x0F120005,                   //REG_1TC_CCFG_Format                           
+0x0F1254F6,	                  //REG_1TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	                  //REG_1TC_CCFG_usMinOut4KHzRate
+
+0x002A036A,
+0x0F120010,                   //REG_1TC_CCFG_PVIMask        => cmk 2010.10.29 
+0x0F120010,                   //REG_1TC_CCFG_OIFMask
+0x0F1203C0,                   //REG_1TC_CCFG_usJpegPacketSize
+
+0x002A0372,
+0x0F120001,                   //REG_1TC_CCFG_uClockInd
+0x0F120002,                   //REG_1TC_CCFG_usFrTimeType
+0x0F120002,                   //REG_1TC_CCFG_FrRateQualityType
+0x0F120535,                  //REG_1TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,                   //REG_1TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000,                   //REG_1TC_CCFG_bSmearOutput
+0x0F120000,                   //REG_1TC_CCFG_sSaturation
+0x0F120000,                   //REG_1TC_CCFG_sSharpBlur
+0x0F120000,                   //REG_1TC_CCFG_sColorTemp
+0x0F120000,                   //REG_1TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055,                   //REG_1TC_BRC_usCaptureQuality
+
+
+0x002A1E5C,            //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,  //0D22
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120000,  //000F
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F0F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F00
+0x0F12000F,  //0000
+0x0F12000F,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F0F,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120000,  //0000
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F0F
+0x0F12000F,  //0F00
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0000
+0x0F120F0F,  //000F
+0x0F12000F,  //000F
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F12000F,  //0000
+0x0F120000,  //000F
+0x0F12000F,  //000F
+0x0F120F0F,  //0F00
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F12000F,  //0F0F
+0x0F120F00,  //0000
+0x0F120F0F,  //0F0F
+0x0F12000F,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120F00,  //0F00
+0x0F12000F,  //000F
+0x0F12000F,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F0F
+0x0F120F00,  //0F00
+0x0F120F00,  //0F00
+0x0F12000F,  //0000
+0x0F120F0F,  //0F0F
+0x0F120F00,  //000F
+0x0F120F0F,  //0F0F
+0x0F120000,  //0000
+0x0F12000F,  //000F
+0x0F120F00,  //0F0F
+
+// TVAR_ash_pGAS_low
+0x0F1273AF,  //6E49
+0x0F12FF14,  //FB98
+0x0F12F1C4,  //F348
+0x0F1213DB,  //1BD6
+0x0F12034D,  //EBEF
+0x0F12EBBF,  //03D3
+0x0F12EB8A,  //EC8D
+0x0F12E1CD,  //F239
+0x0F122A09,  //0E64
+0x0F12DC91,  //F7EA
+0x0F12003B,  //FD3B
+0x0F121D67,  //0A7C
+0x0F12FCC8,  //FC9C
+0x0F121F53,  //0BD3
+0x0F12D360,  //F2E5
+0x0F122866,  //0619
+0x0F120453,  //0772
+0x0F12D38A,  //F0B0
+0x0F121340,  //184E
+0x0F12ED61,  //F95F
+0x0F12155A,  //0B1A
+0x0F12ECED,  //FC45
+0x0F12F641,  //F716
+0x0F122915,  //0DCD
+0x0F12FCA8,  //EF24
+0x0F12FDD5,  //0221
+0x0F120ED6,  //F6BD
+0x0F12F760,  //04CB
+0x0F12F975,  //00B1
+0x0F12FF26,  //FEB0
+0x0F12F704,  //0268
+0x0F120CE5,  //02C7
+0x0F12E58E,  //010A
+0x0F120DE5,  //FF93
+0x0F12170C,  //036D
+0x0F12E129,  //F859
+0x0F1289CF,  //81D0
+0x0F12FE3A,  //FA32
+0x0F12EDFB,  //EFDB
+0x0F121B1D,  //234D
+0x0F12FECB,  //E799
+0x0F12EBC2,  //0337
+0x0F12EC58,  //EB05
+0x0F12D642,  //E8F9
+0x0F1231C1,  //152E
+0x0F12D679,  //F0D5
+0x0F120E40,  //0842
+0x0F1210E6,  //043A
+0x0F12EC1D,  //F461
+0x0F122340,  //0E58
+0x0F12D764,  //F658
+0x0F122280,  //075D
+0x0F12F8D3,  //F78D
+0x0F12E5E2,  //FDE9
+0x0F123192,  //277A
+0x0F12F07C,  //FFDE
+0x0F120ED8,  //FD3B
+0x0F12F24C,  //FE50
+0x0F12FF63,  //0AD1
+0x0F1219AD,  //FE2C
+0x0F12E53A,  //E90D
+0x0F12FB55,  //F7B0
+0x0F1207AB,  //05DB
+0x0F12FF19,  //02CD
+0x0F12FC9D,  //F4F1
+0x0F12F7D2,  //02A8
+0x0F12FD6A,  //FDDC
+0x0F120D9D,  //0B59
+0x0F12F1AD,  //F74E
+0x0F12053D,  //03D5
+0x0F120669,  //FF4F
+0x0F12F887,  //00F7
+0x0F126F7B,  //6A44
+0x0F12FD92,  //FAD6
+0x0F12F87B,  //F261
+0x0F12054F,  //1F28
+0x0F121596,  //E691
+0x0F12E0A2,  //07D2
+0x0F12E9FC,  //EE85
+0x0F12E400,  //F426
+0x0F12279D,  //0F26
+0x0F12DEB1,  //F34B
+0x0F12FF95,  //0036
+0x0F121B50,  //0C0F
+0x0F120845,  //FDA9
+0x0F121B29,  //09EA
+0x0F12D7C2,  //F27A
+0x0F12289C,  //0CD5
+0x0F12FC02,  //01E1
+0x0F12DD73,  //ED41
+0x0F12084B,  //1DB5
+0x0F12EF8B,  //FD26
+0x0F120D89,  //03F7
+0x0F12EDD3,  //F7BB
+0x0F12FE1A,  //FE81
+0x0F122286,  //12D3
+0x0F12FC16,  //E061
+0x0F1202C7,  //F81C
+0x0F120F6E,  //07B1
+0x0F12FB29,  //0408
+0x0F12FCA0,  //F860
+0x0F12F19E,  //FC9A
+0x0F12FD3E,  //0DDE
+0x0F1202EF,  //0C9C
+0x0F12F154,  //F2A4
+0x0F120033,  //02EB
+0x0F121408,  //099B
+0x0F12F445,  //F5A6
+0x0F1275D7,  //7243
+0x0F12FAC3,  //F74D
+0x0F12F7F5,  //F74B
+0x0F120C29,  //1800
+0x0F120AC4,  //EF22
+0x0F12E7C3,  //0263
+0x0F12EBE4,  //EBE7
+0x0F12E43C,  //F5A4
+0x0F12260D,  //09D3
+0x0F12E05B,  //FAB8
+0x0F12FE64,  //FDFF
+0x0F121DAD,  //086B
+0x0F12FFFD,  //0338
+0x0F121AE5,  //0514
+0x0F12D7B3,  //F840
+0x0F122652,  //0768
+0x0F1203DD,  //FE55
+0x0F12D39B,  //F884
+0x0F121769,  //1488
+0x0F12EFEF,  //FFCD
+0x0F120F31,  //035B
+0x0F12ED25,  //FA4E
+0x0F12F920,  //01DB
+0x0F122A81,  //06D6
+0x0F12EFF9,  //EE19
+0x0F12FE2A,  //FEA3
+0x0F121531,  //FE8C
+0x0F12F886,  //03A3
+0x0F12F846,  //FDDB
+0x0F12F794,  //FD9B
+0x0F12000B,  //035E
+0x0F120CA4,  //03F2
+0x0F12E144,  //FCBD
+0x0F120E4E,  //0300
+0x0F121379,  //FF2E
+0x0F12EBB5,  //FE03
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F124000,	//3F00//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //4000//TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[0][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[0][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[0][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[0][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[0][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[0][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[0][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[0][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[0][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[0][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[0][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[0][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[0][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[0][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[0][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[0][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[0][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[0][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[0][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[0][19]
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[1][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[1][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[1][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[1][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[1][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[1][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[1][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[1][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[1][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[1][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[1][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[1][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[1][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[1][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[1][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[1][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[1][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[1][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[1][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[1][19]
+0x0F120000,  //0000  //0000 //saRR_usDualGammaLutRGBIndoor[2][0]
+0x0F120004,  //0003  //0008 //saRR_usDualGammaLutRGBIndoor[2][1]
+0x0F120009,  //000B  //0015 //saRR_usDualGammaLutRGBIndoor[2][2]
+0x0F12002B,  //002E  //0032 //saRR_usDualGammaLutRGBIndoor[2][3]
+0x0F12006D,  //0073  //006C //saRR_usDualGammaLutRGBIndoor[2][4]
+0x0F1200D5,  //00DA  //00D0 //saRR_usDualGammaLutRGBIndoor[2][5]
+0x0F120130,  //012E  //0129 //saRR_usDualGammaLutRGBIndoor[2][6]
+0x0F120159,  //0153  //0151 //saRR_usDualGammaLutRGBIndoor[2][7]
+0x0F12017D,  //0174  //0174 //saRR_usDualGammaLutRGBIndoor[2][8]
+0x0F1201B7,  //01AB  //01AA //saRR_usDualGammaLutRGBIndoor[2][9]
+0x0F1201E6,  //01DA  //01D7 //saRR_usDualGammaLutRGBIndoor[2][10]
+0x0F12020F,  //0202  //01FE //saRR_usDualGammaLutRGBIndoor[2][11]
+0x0F120231,  //0227  //0221 //saRR_usDualGammaLutRGBIndoor[2][12]
+0x0F12026B,  //0266  //0252 //saRR_usDualGammaLutRGBIndoor[2][13]
+0x0F12029C,  //02A2  //0281 //saRR_usDualGammaLutRGBIndoor[2][14]
+0x0F1202FB,  //0301  //02E1 //saRR_usDualGammaLutRGBIndoor[2][15]
+0x0F120349,  //0354  //0345 //saRR_usDualGammaLutRGBIndoor[2][16]
+0x0F120391,  //0399  //039C //saRR_usDualGammaLutRGBIndoor[2][17]
+0x0F1203D2,  //03D6  //03D9 //saRR_usDualGammaLutRGBIndoor[2][18]
+0x0F1203FF,  //03FF  //03FF //saRR_usDualGammaLutRGBIndoor[2][19]
+
+//s002A06D8
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR//MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+//AE_state
+0x002A04EE,
+0x0F12010E, //#lt_uLimitHigh
+0x0F1200F5, //#lt_uLimitLow
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //#lt_uMaxExp1
+0x002A0508,
+0x0F12681F, //#lt_uMaxExp2
+0x002A050C,
+0x0F128227, //#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F12681F, //#lt_uCapMaxExp2
+0x002A051C,
+0x0F128227, //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F120200, //1E0 //#lt_uMaxAnGain1
+0x0F120200, //1E0 //#lt_uMaxAnGain2
+0x0F120300, //#lt_uMaxAnGain3
+0x0F120840, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //1E0 #lt_uCapMaxAnGain1
+0x0F120200, //1E0 #lt_uCapMaxAnGain2
+0x0F120300, //#lt_uCapMaxAnGain3
+0x0F120710, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,
+0x0F120000, //ae_WeightTbl_16[0]
+0x0F120000, //ae_WeightTbl_16[1]
+0x0F120000, //ae_WeightTbl_16[2]
+0x0F120000, //ae_WeightTbl_16[3]
+0x0F120101, //ae_WeightTbl_16[4]
+0x0F120101, //ae_WeightTbl_16[5]
+0x0F120101, //ae_WeightTbl_16[6]
+0x0F120101, //ae_WeightTbl_16[7]
+0x0F120101, //ae_WeightTbl_16[8]
+0x0F120201, //ae_WeightTbl_16[9]
+0x0F120102, //ae_WeightTbl_16[10]
+0x0F120101, //ae_WeightTbl_16[11]
+0x0F120101, //ae_WeightTbl_16[12]
+0x0F120202, //ae_WeightTbl_16[13]
+0x0F120202, //ae_WeightTbl_16[14]
+0x0F120101, //ae_WeightTbl_16[15]
+0x0F120101, //ae_WeightTbl_16[16]
+0x0F120202, //ae_WeightTbl_16[17]
+0x0F120202, //ae_WeightTbl_16[18]
+0x0F120101, //ae_WeightTbl_16[19]
+0x0F120201, //ae_WeightTbl_16[20]
+0x0F120202, //ae_WeightTbl_16[21]
+0x0F120202, //ae_WeightTbl_16[22]
+0x0F120102, //ae_WeightTbl_16[23]
+0x0F120201, //ae_WeightTbl_16[24]
+0x0F120202, //ae_WeightTbl_16[25]
+0x0F120202, //ae_WeightTbl_16[26]
+0x0F120102, //ae_WeightTbl_16[27]
+0x0F120101, //ae_WeightTbl_16[28]
+0x0F120101, //ae_WeightTbl_16[29]
+0x0F120101, //ae_WeightTbl_16[30]
+0x0F120101, //ae_WeightTbl_16[31]
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F1205F0, //awbb_GamutWidthThr1
+0x0F1201F4, //awbb_GamutHeightThr1
+0x0F12006C, //awbb_GamutWidthThr2
+0x0F120038, //awbb_GamutHeightThr2
+0x002A1020,
+0x0F12000C, //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A291A,
+0x0F120006, // #Mon_AWB_ByPassMode          // [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+0x0F120008,	//001E	//awbb_WpFilterMinThr
+0x0F120160,	//0190	//awbb_WpFilterMaxThr
+0x0F1200A0, //awbb_WpFilterCoef
+0x0F120004, //awbb_WpFilterSize
+0x0F120001, //awbb_otp_disable
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F1203B0,  //03C0 //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F1203D4,  //03E2 //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F12037C,  //0356 //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F1203FE,  //03FC //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F120352,  //031E //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1203FC,  //03FE //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F120314,  //02F0 //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F1203E8,  //03F0 //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F1202DE,  //02CA //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F1203AC,  //03CC //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202AE,  //02A8 //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F120368,  //037A //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F120284,  //0280 //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F12031C,  //033C //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F120258,  //0260 //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F1202E4,  //030A //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120234,  //0242 //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F1202B8,  //02DC //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F120212,  //0228 //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F12029C,  //02B2 //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F1201F6,  //020E //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120290,  //0290 //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F1201DC,  //01F8 //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120288,  //0276 //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201CA,  //01E8 //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F120278,  //0268 //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201CA,  //01DC //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F12026C,  //0256 //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201D4,  //01E0 //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F120258,  //0238 //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201F2,  //01EC //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F120228,  //020E //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000,  //0000 //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //05//awbb_IndoorGrZones_m_Grid
+0x002A0F80, //80
+0x0F1200F4, //E6//awbb_IndoorGrZones_m_Boff
+0x002A0F7C, //7C
+0x0F120010, //10
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+
+0x002A11A8,
+0x0F1202C8, //awbb_GridConst_1[0]
+0x0F120325, //awbb_GridConst_1[1]
+0x0F12038F, //awbb_GridConst_1[2]
+
+0x0F120F8E, //awbb_GridConst_2[0]
+0x0F1210B3, //awbb_GridConst_2[1]
+0x0F121136, //awbb_GridConst_2[2]
+0x0F121138, //awbb_GridConst_2[3]
+0x0F12118E, //awbb_GridConst_2[4]
+0x0F121213, //awbb_GridConst_2[5]
+
+0x0F1200A7, //awbb_GridCoeff_R_1
+0x0F1200C2, //awbb_GridCoeff_B_1
+0x0F1200BD, //awbb_GridCoeff_R_2
+0x0F1200AC, //awbb_GridCoeff_B_2
+
+0x002A1118,
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[0][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[0][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[0][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[0][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[0][5]
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[1][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[1][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[1][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[1][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[1][5]
+0x0F12001E,  //0050 //0032//awbb_GridCorr_R[2][0]
+0x0F120032,  //0032 //0012//awbb_GridCorr_R[2][1]
+0x0F120050,  //0032 //0012//awbb_GridCorr_R[2][2]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[2][3]
+0x0F120000,  //0000 //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060,  //0060 //0050//awbb_GridCorr_R[2][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[0][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[0][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[0][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[0][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[0][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[0][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[1][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[1][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[1][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[1][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[1][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[1][5]
+0x0F12FFCE,  //FF9C //FF9C//awbb_GridCorr_B[2][0]
+0x0F120000,  //FFD8 //FFCE//awbb_GridCorr_B[2][1]
+0x0F120000,  //FFEC //FFCE//awbb_GridCorr_B[2][2]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[2][3]
+0x0F12FF97,  //FF97 //FF97//awbb_GridCorr_B[2][4]
+0x0F12FE30,  //FE30 //FDA8//awbb_GridCorr_B[2][5]
+
+0x002A1160,
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[0][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[0][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[0][5]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[1][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[1][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[1][5]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[2][0]
+0x0F12FFCE,   //FFCE//0000 //A //awbb_GridCorr_R_Out[2][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_R_Out[2][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[0][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[0][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[0][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[1][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[1][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[1][5]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[2][0]
+0x0F12FFE8,   //0000//FFD2 //awbb_GridCorr_B_Out[2][1]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][2]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][3]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][4]
+0x0F120000,   //0000//0000 //awbb_GridCorr_B_Out[2][5]
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0] 
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1] 
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2] 
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3] 
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[4] 
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5] 
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6] 
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7] 
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[8] 
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[9] 
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+0x0F120222,  //01F8  //01EA //01E2//TVAR_wbt_pBaseCcms[36]
+0x0F12FF9E,  //FFB0  //FFAC //FF9A//TVAR_wbt_pBaseCcms[37]
+0x0F12FFD0,  //FFE8  //FFE3 //FFE8//TVAR_wbt_pBaseCcms[38]
+0x0F12FEFD,  //FF39  //FF45 //FF45//TVAR_wbt_pBaseCcms[39]
+0x0F1201B2,  //0144  //0140 //0140//TVAR_wbt_pBaseCcms[40]
+0x0F12FF25,  //FF57  //FF4F //FF4F//TVAR_wbt_pBaseCcms[41]
+0x0F12FFC0,  //FFBD  //FFC3 //FFC3//TVAR_wbt_pBaseCcms[42]
+0x0F12FFC1,  //FFD0  //FFD5 //FFD5//TVAR_wbt_pBaseCcms[43]
+0x0F120189,  //017D  //0173 //0173//TVAR_wbt_pBaseCcms[44]
+0x0F1200C4,  //0113  //0137 //0128//TVAR_wbt_pBaseCcms[45]
+0x0F1200C3,  //00BF  //00C2 //00EA//TVAR_wbt_pBaseCcms[46]
+0x0F12FF33,  //FEE8  //FEC1 //FEA8//TVAR_wbt_pBaseCcms[47]
+0x0F1200CF,  //00CB  //00C8 //00C8//TVAR_wbt_pBaseCcms[48]
+0x0F12FF31,  //FF3F  //FF49 //FF49//TVAR_wbt_pBaseCcms[49]
+0x0F12015C,  //0152  //014B //014B//TVAR_wbt_pBaseCcms[50]
+0x0F12FF49,  //FF5E  //FF68 //FF68//TVAR_wbt_pBaseCcms[51]
+0x0F12011A,  //010F  //0109 //0109//TVAR_wbt_pBaseCcms[52]
+0x0F120102,  //00F9  //00F4 //00F4//TVAR_wbt_pBaseCcms[53]
+
+0x0F120222,  //01F8  //01EA //01E2//TVAR_wbt_pBaseCcms[54]
+0x0F12FF9E,  //FFB0  //FFAC //FF9A//TVAR_wbt_pBaseCcms[55]
+0x0F12FFD0,  //FFE8  //FFE3 //FFE8//TVAR_wbt_pBaseCcms[56]
+0x0F12FEFD,  //FF39  //FF45 //FF45//TVAR_wbt_pBaseCcms[57]
+0x0F1201B2,  //0144  //0140 //0140//TVAR_wbt_pBaseCcms[58]
+0x0F12FF25,  //FF57  //FF4F //FF4F//TVAR_wbt_pBaseCcms[59]
+0x0F12FFC0,  //FFBD  //FFC3 //FFC3//TVAR_wbt_pBaseCcms[60]
+0x0F12FFC1,  //FFD0  //FFD5 //FFD5//TVAR_wbt_pBaseCcms[61]
+0x0F120189,  //017D  //0173 //0173//TVAR_wbt_pBaseCcms[62]
+0x0F1200C4,  //0113  //0137 //0128//TVAR_wbt_pBaseCcms[63]
+0x0F1200C3,  //00BF  //00C2 //00EA//TVAR_wbt_pBaseCcms[64]
+0x0F12FF33,  //FEE8  //FEC1 //FEA8//TVAR_wbt_pBaseCcms[65]
+0x0F1200CF,  //00CB  //00C8 //00C8//TVAR_wbt_pBaseCcms[66]
+0x0F12FF31,  //FF3F  //FF49 //FF49//TVAR_wbt_pBaseCcms[67]
+0x0F12015C,  //0152  //014B //014B//TVAR_wbt_pBaseCcms[68]
+0x0F12FF49,  //FF5E  //FF68 //FF68//TVAR_wbt_pBaseCcms[69]
+0x0F12011A,  //010F  //0109 //0109//TVAR_wbt_pBaseCcms[70]
+0x0F120102,  //00F9  //00F4 //00F4//TVAR_wbt_pBaseCcms[71]
+
+0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[72]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+0x0F12011D, //00F4          //TVAR_wbt_pBaseCcms[90]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F120040, //40 //4A //0049//#afit_uNoiseIndInDoor_0_
+0x0F120048, //48 //4E //005F//#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+0x002A08C0,
+0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700008C2//AFIT16_CONTRAST
+0x0F120000, //0000//700008C4//AFIT16_SATURATION
+0x0F120002, //0000//700008C6//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700008C8//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700008CA//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700008CC
+0x0F1203FF, //03FF//700008CE//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700008D0//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700008D2//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700008D4//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700008D6//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700008D8//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700008DA//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700008DC//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700008DE//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700008E0//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700008E2//AFIT16_demsharpmix1_iTune
+0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C//700008EA //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008//700008EC //AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700008EE //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700008F0 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700008F2 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700008F4 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700008F6 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//700008F8 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//700008FA //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//700008FC //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//700008FE //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000900 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000902 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000904 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //09E8//70000906 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000908 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//7000090A //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//7000090C //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F124000, //4000//7000090E 
+0x0F127803, //7803//70000910 
+0x0F123C50, //3C50//70000912 
+0x0F12003C, //003C//70000914 
+0x0F121E80, //1E80//70000916 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000918 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A//7000091A //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000//7000091C //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12120A, //120A//7000091E //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F121400, //0F00//70000920 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000922 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000924 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000926 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000928 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//7000092A //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//7000092C //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//7000092E //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000930 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000932 
+0x0F120609, //0609//70000934 
+0x0F122C07, //2C07//70000936 
+0x0F12142C, //142C//70000938 
+0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120880, //0880//7000093E //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120B50, //0B50//70000940 //AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000942 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000944 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000946 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124601, //4601//70000948 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12A444, //C844//7000094A //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F1250A4, //50C8//7000094C //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//7000094E //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120303, //0003//70000950 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121001, //1C01//70000952 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120710, //0714//70000954 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121448, //1464//70000956 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A03, //5A04//70000958 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12281E, //3C1E//7000095A //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //400F//7000095C //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//7000095E //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F121403, //1403//70000960 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120114, //0114//70000962 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000964 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124446, //4446//70000966 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F12646E, //646E//70000968 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//7000096A //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//7000096C //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120000, //0000//7000096E //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000970 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000972 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000974 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F120000, //0000//70000976 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000978 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//7000097A //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//7000097C //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121414, //1414//7000097E //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000980 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124601, //4601//70000982 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F126E44, //6E44//70000984 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122864, //2864//70000986 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000988 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F120003, //0003//7000098A //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E00, //1E00//7000098C //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//7000098E //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000990 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F120004, //0004//70000992 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F00, //0F00//70000994 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000996 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000998 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//7000099A //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//7000099C 
+0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700009A0//AFIT16_CONTRAST
+0x0F120000, //0000//700009A2//AFIT16_SATURATION
+0x0F120002, //0000//700009A4//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700009A6//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700009A8//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700009AA
+0x0F1203FF, //03FF//700009AC//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700009AE//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700009B0//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700009B2//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700009B4//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700009B6//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700009B8//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700009BA//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700009BC//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700009BE//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700009C0//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E//700009C8//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//700009CA//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700009CC//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700009CE//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700009D0//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700009D2//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700009D4//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//700009D6//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//700009D8//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//700009DA//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//700009DC//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//700009DE//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//700009E0//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//700009E2//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //05E8//700009E4//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//700009E6//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//700009E8//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//700009EA//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000//700009EC
+0x0F125003, //5003//700009EE
+0x0F123228, //3228//700009F0
+0x0F120032, //0032//700009F2
+0x0F121E80, //1E80//700009F4//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//700009F6//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A//700009F8//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000//700009FA//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12120A, //120A//700009FC//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F121400, //1400//700009FE//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000A00//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000A02//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000A04//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000A06//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000A08//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000A0A//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000A0C//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000A0E//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000A10
+0x0F120609, //0609//70000A12
+0x0F122C07, //2C07//70000A14
+0x0F12142C, //142C//70000A16
+0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120580, //0580//70000A1C//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000A1E//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000A20//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000A22//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000A24//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000A26//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12494B, //444B 494B//70000A28//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125044, //503C 5044//70000A2A//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000A2C//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120603, //0503//70000A2E//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D03, //0D02//70000A30//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //071E//70000A32//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1432//70000A34//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A01, //5A01//70000A36//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12281E, //281E//70000A38//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //200F//70000A3A//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000A3C//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F121E03, //1E03//70000A3E//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F12011E, //011E//70000A40//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000A42//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F123A3C, //3A3C//70000A44//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F12585A, //585A//70000A46//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000A48//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000A4A//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120000, //0000//70000A4C//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000A4E//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000A50//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000A52//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F120000, //0000//70000A54//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000A56//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000A58//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000A5A//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1E1E//70000A5C//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000A5E//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F123C01, //3C01//70000A60//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F125A3A, //5A3A//70000A62//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122858, //2858//70000A64//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000A66//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F120003, //0003//70000A68//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E00, //1E00//70000A6A//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//70000A6C//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000A6E//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F120004, //0004//70000A70//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F00, //0F00//70000A72//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000A74//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000A76//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000A78//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000A7A
+0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000A7E//AFIT16_CONTRAST
+0x0F120000, //0000//70000A80//AFIT16_SATURATION
+0x0F120000, //0000//70000A82//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000A84//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000A86//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000A88
+0x0F1203FF, //03FF//70000A8A//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000A8C//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000A8E//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000A90//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000A92//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000A94//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//70000A96//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000A98//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000A9A//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//70000A9C//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000A9E//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000AA6//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000AA8//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//70000AAA//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//70000AAC//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//70000AAE//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//70000AB0//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000AB2//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//70000AB4//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//70000AB6//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//70000AB8//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//70000ABA//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000ABC//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000ABE//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000AC0//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE//70000AC2//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000AC4//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//70000AC6//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//70000AC8//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000ACA
+0x0F122803, //2803//70000ACC
+0x0F12261E, //261E//70000ACE
+0x0F120026, //0026//70000AD0
+0x0F121E80, //1E80//70000AD2//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000AD4//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A//70000AD6//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001//70000AD8//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F123C0A, //3C0A//70000ADA//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122300, //2300//70000ADC//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000ADE//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000AE0//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000AE2//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11//70000AE4//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000AE6//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000AE8//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000AEA//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605//70000AEC//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307//70000AEE
+0x0F120609, //0609//70000AF0
+0x0F121C07, //1C07//70000AF2
+0x0F121014, //1014//70000AF4
+0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000AFA//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000AFC//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000AFE//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000B00//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000B02//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000B04//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F122A4B, //2A4B//70000B06//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125020, //5020//70000B08//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000B0A//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121C03, //1C03//70000B0C//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D0C, //0D0C//70000B0E//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823//70000B10//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428//70000B12//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F126401, //6401//70000B14//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12282D, //282D//70000B16//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012//70000B18//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000B1A//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F122803, //2803//70000B1C//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120128, //0128//70000B1E//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000B20//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F122224, //2224//70000B22//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F123236, //3236//70000B24//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000B26//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000B28//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120410, //0410//70000B2A//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12141E, //141E//70000B2C//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF07, //FF07//70000B2E//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000B30//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124050, //4050//70000B32//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F0F, //0F0F//70000B34//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000B36//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000B38//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F122828, //2828//70000B3A//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000B3C//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F122401, //2401//70000B3E//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F123622, //3622//70000B40//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122832, //2832//70000B42//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000B44//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121003, //1003//70000B46//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121E04, //1E04//70000B48//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120714, //0714//70000B4A//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000B4C//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125004, //5004//70000B4E//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120F40, //0F40//70000B50//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12400F, //400F//70000B52//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000B54//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000B56//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000B58
+0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000B5C//AFIT16_CONTRAST
+0x0F120010, //00 //0000//70000B5E//AFIT16_SATURATION
+0x0F120000, //0000//70000B60//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000B62//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000B64//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000B66
+0x0F1203FF, //03FF//70000B68//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000B6A//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000B6C//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000B6E//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000B70//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000B72//AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8//70000B74//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000B76//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000B78//AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050//70000B7A//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000B7C//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000B84//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000B86//AFIT16_Sharpening_iHighSharpClamp
+0x0F12002D, //002D//70000B88//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//70000B8A//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12002D, //002D//70000B8C//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//70000B8E//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000B90//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//70000B92//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//70000B94//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403//70000B96//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004//70000B98//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300//70000B9A//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//70000B9C//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF//70000B9E//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE//70000BA0//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//70000BA2//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//70000BA4//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//70000BA6//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000BA8
+0x0F122303, //2303//70000BAA
+0x0F12231A, //231A//70000BAC
+0x0F120023, //0023//70000BAE
+0x0F121E80, //1E80//70000BB0//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08//70000BB2//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A//70000BB4//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001//70000BB6//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F123C0A, //3C0A//70000BB8//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122300, //2300//70000BBA//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200//70000BBC//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//70000BBE//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//70000BC0//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10//70000BC2//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//70000BC4//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//70000BC6//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//70000BC8//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705//70000BCA//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120306, //0306//70000BCC
+0x0F120509, //0509//70000BCE
+0x0F122806, //2806//70000BD0
+0x0F121428, //1428//70000BD2
+0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000BD8//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//70000BDA//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//70000BDC//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101//70000BDE//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707//70000BE0//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01//70000BE2//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F122A4B, //2A4B//70000BE4//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125020, //5020//70000BE6//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500//70000BE8//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121C03, //1C03//70000BEA//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120D0C, //0D0C//70000BEC//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823//70000BEE//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428//70000BF0//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F126401, //6401//70000BF2//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12282D, //282D//70000BF4//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012//70000BF6//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204//70000BF8//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F123C03, //3C03//70000BFA//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F12013C, //013C//70000BFC//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//70000BFE//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F121C1E, //1C1E//70000C00//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F121E22, //1E22//70000C02//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//70000C04//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//70000C06//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120214, //0214//70000C08//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120E14, //0E14//70000C0A//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF06, //FF06//70000C0C//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//70000C0E//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124052, //4052//70000C10//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F12150C, //150C//70000C12//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//70000C14//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//70000C16//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F123C3C, //3C3C//70000C18//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//70000C1A//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F121E01, //1E01//70000C1C//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12221C, //221C//70000C1E//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F12281E, //281E//70000C20//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//70000C22//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121403, //1403//70000C24//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121402, //1402//70000C26//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12060E, //060E//70000C28//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//70000C2A//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125204, //5204//70000C2C//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120C40, //0C40//70000C2E//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124015, //4015//70000C30//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//70000C32//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//70000C34//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000C36
+0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//0000//70000C44
+0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]       
+0x0F121000, //1000//1000//70000C86        
+0x0F122003, //2003//2003//70000C88        
+0x0F121020, //1020//1020//70000C8A        
+0x0F120010, //0010//0010//70000C8C        
+0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120305, //0305//0305//70000CAA        
+0x0F120609, //0609//0609//70000CAC        
+0x0F122C07, //2C07//2C07//70000CAE        
+0x0F12142C, //142C//142C//70000CB0        
+0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH     
+0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]        
+0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset [15:8]
+0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//0001//70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F122102, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+
+};
+
+static const u32 s5k5ccgx_camcorder_set[] =
+{
+0xFCFCD000,
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight	//Sensor Crop Height 1536
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs	//Sensor VOffset 0
+0x0F120800,	//REG_TC_GP_CapReqInputWidth		//Sensor Crop Width	2048
+0x0F120600,	//REG_TC_GP_CapReqInputHeight		//Sensor Crop Height 1368
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs		//Sensor HOffset 0
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs		//Sensor VOffset 0
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+
+
+//Preview Size
+0x002A0400,
+0x0F120300,	//REG_0TC_PCFG_usWidth
+0x0F1201E0,	//REG_0TC_PCFG_usHeight
+
+0x002A029E,
+0x0F120400,	//REG_2TC_PCFG_usWidth
+0x0F120300, //REG_2TC_PCFG_usHeight
+
+//Capture Size
+0x002A0330,
+0x0F120800,	//REG_0TC_CCFG_usWidth
+0x0F120600,	//REG_0TC_CCFG_usHeight
+
+0x002A0388,
+0x0F120800, //REG_2TC_CCFG_usWidth
+0x0F120600, //REG_2TC_CCFG_usHeight
+
+};
+
+static const u32 s5k5ccgx_update_preview_reg[] = {
+//PREVIEW   
+0x002A0208, 
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210, 
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C, 
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4, 
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A, 
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212, 
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8, 
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+0xFFFF0064, //Delay 100ms
+};
+
+static const u32 s5k5ccgx_update_hd_preview_reg[] = {
+/* PREVIEW */
+0x002A0208,
+0x0F120000, /* REG_TC_GP_ActivePrevConfig */
+0x002A0210,
+0x0F120000, /* REG_TC_GP_ActiveCapConfig */
+0x002A020C,
+0x0F120001, /* REG_TC_GP_PrevOpenAfterChange */
+0x002A01F4,
+0x0F120001, /* REG_TC_GP_NewConfigSync */
+0x002A020A,
+0x0F120001, /* REG_TC_GP_PrevConfigChanged */
+0x002A0212,
+0x0F120001, /* REG_TC_GP_CapConfigChanged */
+0x002A01E8,
+0x0F120000, /* REG_TC_GP_EnableCapture */
+0x0F120001, /* REG_TC_GP_EnableCaptureChanged */
+
+/* TNP_Regs_bUseAccurateFR */
+0x00287000,
+0x002A3FE4,
+0x0F120001, /* on/off TNP_Regs_bAccuDynamicFR */
+0x0F1234A2, /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+0x0F1240FD, /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+
+0xFFFF0064, /* Delay 100ms */
+};
+
+static const u32 s5k5ccgx_stream_stop_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E4,
+0x0F120000,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_176_144_Preview[] = {
+0xFCFCD000, 
+0x00287000,
+
+0x002A023E, //Preview Size 
+0x0F1200B0, //REG_0TC_PCFG_usWidth  
+0x0F120090, //REG_0TC_PCFG_usHeight        
+    
+};
+
+static const u32 s5k5ccgx_320_240_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120140,	//REG_0TC_PCFG_usWidth 320
+0x0F1200F0,	//REG_0TC_PCFG_usHeight 240
+};
+
+
+
+static const u32 s5k5ccgx_352_288_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120160,	//REG_0TC_PCFG_usWidth 280
+0x0F120120,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+static const u32 s5k5ccgx_528_432_Preview[] = {
+0xFCFCD000, 
+0x00287000,
+
+0x002A023E, //Preview Size 
+0x0F120210, //REG_0TC_PCFG_usWidth  
+0x0F1201B0, //REG_0TC_PCFG_usHeight        
+
+};
+
+static const u32 s5k5ccgx_640_480_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120280,	//REG_0TC_PCFG_usWidth 280
+0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_720_480_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F1202D0,	//REG_0TC_PCFG_usWidth 280
+0x0F1201E0,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_800_600_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120320,	//REG_0TC_PCFG_usWidth 280
+0x0F120258,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+#define S5K5CCGX_WIDE_PREVIEW_REG s5k5ccgx_1024_576_Preview
+static const u32 s5k5ccgx_1024_576_Preview[] = {
+0xFCFCD000,
+0x00287000,
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth 400
+0x0F120240,	//REG_0TC_PCFG_usHeight 240
+0x0F120005,	//REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+};
+
+static const u32 s5k5ccgx_1024_768_Preview[] = {
+0xFCFCD000, 
+0x00287000,	
+	
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth 280
+0x0F120300,	//REG_0TC_PCFG_usHeight 1E0
+
+};
+
+static const u32 s5k5ccgx_1280_1024_Preview[] = {
+
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000          //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A,     //p10
+// Start of Patch data
+0x00287000,
+0x002A352C,
+0x0F12B570, // 7000352C 
+0x0F124A24, // 7000352E 
+0x0F124924, // 70003530 
+0x0F124825, // 70003532 
+0x0F124B25, // 70003534 
+0x0F122500, // 70003536 
+0x0F12801D, // 70003538 
+0x0F12C004, // 7000353A 
+0x0F126001, // 7000353C 
+0x0F124924, // 7000353E 
+0x0F124824, // 70003540 
+0x0F12F000, // 70003542 
+0x0F12FBBD, // 70003544 
+0x0F124924, // 70003546 
+0x0F124824, // 70003548 
+0x0F12F000, // 7000354A 
+0x0F12FBB9, // 7000354C 
+0x0F124824, // 7000354E 
+0x0F124E24, // 70003550 
+0x0F126430, // 70003552 
+0x0F124924, // 70003554 
+0x0F124825, // 70003556 
+0x0F12F000, // 70003558 
+0x0F12FBB2, // 7000355A 
+0x0F124924, // 7000355C 
+0x0F120030, // 7000355E 
+0x0F123080, // 70003560 
+0x0F126141, // 70003562 
+0x0F124C23, // 70003564 
+0x0F128365, // 70003566 
+0x0F124923, // 70003568 
+0x0F124824, // 7000356A 
+0x0F12F000, // 7000356C 
+0x0F12FBA8, // 7000356E 
+0x0F124923, // 70003570 
+0x0F124824, // 70003572 
+0x0F12F000, // 70003574 
+0x0F12FBA4, // 70003576 
+0x0F124923, // 70003578 
+0x0F124824, // 7000357A 
+0x0F12F000, // 7000357C 
+0x0F12FBA0, // 7000357E 
+0x0F124923, // 70003580 
+0x0F124824, // 70003582 
+0x0F12F000, // 70003584 
+0x0F12FB9C, // 70003586 
+0x0F128125, // 70003588 
+0x0F124923, // 7000358A 
+0x0F124823, // 7000358C 
+0x0F12F000, // 7000358E 
+0x0F12FB97, // 70003590 
+0x0F124923, // 70003592 
+0x0F124823, // 70003594 
+0x0F12F000, // 70003596 
+0x0F12FB93, // 70003598 
+0x0F1283A5, // 7000359A 
+0x0F124922, // 7000359C 
+0x0F124823, // 7000359E 
+0x0F12F000, // 700035A0 
+0x0F12FB8E, // 700035A2 
+0x0F122101, // 700035A4 
+0x0F120349, // 700035A6 
+0x0F120020, // 700035A8 
+0x0F123020, // 700035AA 
+0x0F128041, // 700035AC 
+0x0F122185, // 700035AE 
+0x0F128081, // 700035B0 
+0x0F12491F, // 700035B2 
+0x0F1280C1, // 700035B4 
+0x0F12481F, // 700035B6 
+0x0F126730, // 700035B8 
+0x0F12BC70, // 700035BA 
+0x0F12BC08, // 700035BC 
+0x0F124718, // 700035BE 
+0x0F1200CA, // 700035C0 
+0x0F125CC1, // 700035C2 
+0x0F1203BD, // 700035C4 
+0x0F120000, // 700035C6 
+0x0F121C08, // 700035C8 
+0x0F127000, // 700035CA 
+0x0F123290, // 700035CC 
+0x0F127000, // 700035CE 
+0x0F123657, // 700035D0 
+0x0F127000, // 700035D2 
+0x0F12D9E7, // 700035D4 
+0x0F120000, // 700035D6 
+0x0F12383F, // 700035D8 
+0x0F127000, // 700035DA 
+0x0F12395D, // 700035DC 
+0x0F120000, // 700035DE 
+0x0F1238D1, // 700035E0 
+0x0F127000, // 700035E2 
+0x0F120000, // 700035E4 
+0x0F127000, // 700035E6 
+0x0F12399D, // 700035E8 
+0x0F127000, // 700035EA 
+0x0F12F903, // 700035EC 
+0x0F120000, // 700035EE 
+0x0F123AC1, // 700035F0 
+0x0F127000, // 700035F2 
+0x0F123FC8, // 700035F4 
+0x0F127000, // 700035F6 
+0x0F12368F, // 700035F8 
+0x0F127000, // 700035FA 
+0x0F12495F, // 700035FC 
+0x0F120000, // 700035FE 
+0x0F1236ED, // 70003600 
+0x0F127000, // 70003602 
+0x0F12E421, // 70003604 
+0x0F120000, // 70003606 
+0x0F1237AB, // 70003608 
+0x0F127000, // 7000360A 
+0x0F12216D, // 7000360C 
+0x0F120000, // 7000360E 
+0x0F12381F, // 70003610 
+0x0F127000, // 70003612 
+0x0F120179, // 70003614 
+0x0F120001, // 70003616 
+0x0F123BD5, // 70003618 
+0x0F127000, // 7000361A 
+0x0F1204C9, // 7000361C 
+0x0F120000, // 7000361E 
+0x0F123B25, // 70003620 
+0x0F127000, // 70003622 
+0x0F125027, // 70003624 
+0x0F120000, // 70003626 
+0x0F123BE1, // 70003628 
+0x0F127000, // 7000362A 
+0x0F1242B7, // 7000362C 
+0x0F120000, // 7000362E 
+0x0F1207FF, // 70003630 
+0x0F120000, // 70003632 
+0x0F123C5F, // 70003634 
+0x0F127000, // 70003636 
+0x0F12B570, // 70003638 
+0x0F12000D, // 7000363A 
+0x0F124CFC, // 7000363C 
+0x0F128821, // 7000363E 
+0x0F12F000, // 70003640 
+0x0F12FB46, // 70003642 
+0x0F128820, // 70003644 
+0x0F124AFB, // 70003646 
+0x0F120081, // 70003648 
+0x0F125055, // 7000364A 
+0x0F121C40, // 7000364C 
+0x0F128020, // 7000364E 
+0x0F12BC70, // 70003650 
+0x0F12BC08, // 70003652 
+0x0F124718, // 70003654 
+0x0F126801, // 70003656 
+0x0F120409, // 70003658 
+0x0F120C09, // 7000365A 
+0x0F126840, // 7000365C 
+0x0F120400, // 7000365E 
+0x0F120C00, // 70003660 
+0x0F124AF5, // 70003662 
+0x0F128992, // 70003664 
+0x0F122A00, // 70003666 
+0x0F12D00D, // 70003668 
+0x0F122300, // 7000366A 
+0x0F121A80, // 7000366C 
+0x0F12D400, // 7000366E 
+0x0F120003, // 70003670 
+0x0F120418, // 70003672 
+0x0F120C00, // 70003674 
+0x0F124BF1, // 70003676 
+0x0F121851, // 70003678 
+0x0F12891B, // 7000367A 
+0x0F12428B, // 7000367C 
+0x0F12D300, // 7000367E 
+0x0F12000B, // 70003680 
+0x0F120419, // 70003682 
+0x0F120C09, // 70003684 
+0x0F124AEE, // 70003686 
+0x0F128151, // 70003688 
+0x0F128190, // 7000368A 
+0x0F124770, // 7000368C 
+0x0F12B510, // 7000368E 
+0x0F124CEC, // 70003690 
+0x0F1248ED, // 70003692 
+0x0F1278A1, // 70003694 
+0x0F122900, // 70003696 
+0x0F12D101, // 70003698 
+0x0F1287C1, // 7000369A 
+0x0F12E004, // 7000369C 
+0x0F127AE1, // 7000369E 
+0x0F122900, // 700036A0 
+0x0F12D001, // 700036A2 
+0x0F122101, // 700036A4 
+0x0F1287C1, // 700036A6 
+0x0F12F000, // 700036A8 
+0x0F12FB1A, // 700036AA 
+0x0F1249E7, // 700036AC 
+0x0F128B08, // 700036AE 
+0x0F1206C2, // 700036B0 
+0x0F12D50A, // 700036B2 
+0x0F127AA2, // 700036B4 
+0x0F120652, // 700036B6 
+0x0F12D507, // 700036B8 
+0x0F122210, // 700036BA 
+0x0F124390, // 700036BC 
+0x0F128308, // 700036BE 
+0x0F1248E3, // 700036C0 
+0x0F127AE1, // 700036C2 
+0x0F126B00, // 700036C4 
+0x0F12F000, // 700036C6 
+0x0F12FB13, // 700036C8 
+0x0F1248DB, // 700036CA 
+0x0F1289C0, // 700036CC 
+0x0F122801, // 700036CE 
+0x0F12D109, // 700036D0 
+0x0F1278A0, // 700036D2 
+0x0F122800, // 700036D4 
+0x0F12D006, // 700036D6 
+0x0F127AE0, // 700036D8 
+0x0F122800, // 700036DA 
+0x0F12D003, // 700036DC 
+0x0F127AA0, // 700036DE 
+0x0F122140, // 700036E0 
+0x0F124308, // 700036E2 
+0x0F1272A0, // 700036E4 
+0x0F12BC10, // 700036E6 
+0x0F12BC08, // 700036E8 
+0x0F124718, // 700036EA 
+0x0F12B570, // 700036EC 
+0x0F124DD7, // 700036EE 
+0x0F124CD7, // 700036F0 
+0x0F128B28, // 700036F2 
+0x0F120701, // 700036F4 
+0x0F12D507, // 700036F6 
+0x0F122108, // 700036F8 
+0x0F124388, // 700036FA 
+0x0F128328, // 700036FC 
+0x0F1249D5, // 700036FE 
+0x0F126B20, // 70003700 
+0x0F126B89, // 70003702 
+0x0F12F000, // 70003704 
+0x0F12FAFC, // 70003706 
+0x0F128B28, // 70003708 
+0x0F1206C1, // 7000370A 
+0x0F12D5A0, // 7000370C 
+0x0F1249CD, // 7000370E 
+0x0F127A8A, // 70003710 
+0x0F120652, // 70003712 
+0x0F12D49C, // 70003714 
+0x0F122210, // 70003716 
+0x0F124390, // 70003718 
+0x0F128328, // 7000371A 
+0x0F127AC9, // 7000371C 
+0x0F126B20, // 7000371E 
+0x0F12F000, // 70003720 
+0x0F12FAE6, // 70003722 
+0x0F12E794, // 70003724 
+0x0F12B5F8, // 70003726 
+0x0F1249CB, // 70003728 
+0x0F128F08, // 7000372A 
+0x0F12000C, // 7000372C 
+0x0F123480, // 7000372E 
+0x0F122800, // 70003730 
+0x0F12D000, // 70003732 
+0x0F128360, // 70003734 
+0x0F122000, // 70003736 
+0x0F128708, // 70003738 
+0x0F124DC8, // 7000373A 
+0x0F1226FF, // 7000373C 
+0x0F128828, // 7000373E 
+0x0F121C76, // 70003740 
+0x0F122702, // 70003742 
+0x0F122803, // 70003744 
+0x0F12D112, // 70003746 
+0x0F128868, // 70003748 
+0x0F122800, // 7000374A 
+0x0F12D10F, // 7000374C 
+0x0F1288E8, // 7000374E 
+0x0F122800, // 70003750 
+0x0F12D10C, // 70003752 
+0x0F12F000, // 70003754 
+0x0F12FADC, // 70003756 
+0x0F122800, // 70003758 
+0x0F12D008, // 7000375A 
+0x0F128B60, // 7000375C 
+0x0F122800, // 7000375E 
+0x0F12D001, // 70003760 
+0x0F1280EE, // 70003762 
+0x0F1280AF, // 70003764 
+0x0F122001, // 70003766 
+0x0F127268, // 70003768 
+0x0F12F000, // 7000376A 
+0x0F12FAD9, // 7000376C 
+0x0F128828, // 7000376E 
+0x0F122802, // 70003770 
+0x0F12D10E, // 70003772 
+0x0F128868, // 70003774 
+0x0F122800, // 70003776 
+0x0F12D10B, // 70003778 
+0x0F1288E8, // 7000377A 
+0x0F122800, // 7000377C 
+0x0F12D108, // 7000377E 
+0x0F128B60, // 70003780 
+0x0F122800, // 70003782 
+0x0F12D001, // 70003784 
+0x0F1280EE, // 70003786 
+0x0F1280AF, // 70003788 
+0x0F122001, // 7000378A 
+0x0F127268, // 7000378C 
+0x0F12F000, // 7000378E 
+0x0F12FAC7, // 70003790 
+0x0F1288E8, // 70003792 
+0x0F122800, // 70003794 
+0x0F12D006, // 70003796 
+0x0F121FC1, // 70003798 
+0x0F1239FD, // 7000379A 
+0x0F12D003, // 7000379C 
+0x0F122001, // 7000379E 
+0x0F12BCF8, // 700037A0 
+0x0F12BC08, // 700037A2 
+0x0F124718, // 700037A4 
+0x0F122000, // 700037A6 
+0x0F12E7FA, // 700037A8 
+0x0F12B570, // 700037AA 
+0x0F124CAC, // 700037AC 
+0x0F128860, // 700037AE 
+0x0F122800, // 700037B0 
+0x0F12D00C, // 700037B2 
+0x0F128820, // 700037B4 
+0x0F124DA3, // 700037B6 
+0x0F122800, // 700037B8 
+0x0F12D009, // 700037BA 
+0x0F120029, // 700037BC 
+0x0F1231A0, // 700037BE 
+0x0F127AC9, // 700037C0 
+0x0F122900, // 700037C2 
+0x0F12D004, // 700037C4 
+0x0F127AA8, // 700037C6 
+0x0F122180, // 700037C8 
+0x0F124308, // 700037CA 
+0x0F1272A8, // 700037CC 
+0x0F12E73F, // 700037CE 
+0x0F122800, // 700037D0 
+0x0F12D003, // 700037D2 
+0x0F12F7FF, // 700037D4 
+0x0F12FFA7, // 700037D6 
+0x0F122800, // 700037D8 
+0x0F12D1F8, // 700037DA 
+0x0F122000, // 700037DC 
+0x0F128060, // 700037DE 
+0x0F128820, // 700037E0 
+0x0F122800, // 700037E2 
+0x0F12D003, // 700037E4 
+0x0F122008, // 700037E6 
+0x0F12F000, // 700037E8 
+0x0F12FAA2, // 700037EA 
+0x0F12E00B, // 700037EC 
+0x0F12489C, // 700037EE 
+0x0F123020, // 700037F0 
+0x0F128880, // 700037F2 
+0x0F122800, // 700037F4 
+0x0F12D103, // 700037F6 
+0x0F127AA8, // 700037F8 
+0x0F122101, // 700037FA 
+0x0F124308, // 700037FC 
+0x0F1272A8, // 700037FE 
+0x0F122010, // 70003800 
+0x0F12F000, // 70003802 
+0x0F12FA95, // 70003804 
+0x0F128820, // 70003806 
+0x0F122800, // 70003808 
+0x0F12D1E0, // 7000380A 
+0x0F12488A, // 7000380C 
+0x0F1289C0, // 7000380E 
+0x0F122801, // 70003810 
+0x0F12D1DC, // 70003812 
+0x0F127AA8, // 70003814 
+0x0F1221BF, // 70003816 
+0x0F124008, // 70003818 
+0x0F1272A8, // 7000381A 
+0x0F12E718, // 7000381C 
+0x0F126800, // 7000381E 
+0x0F124990, // 70003820 
+0x0F128188, // 70003822 
+0x0F124890, // 70003824 
+0x0F122201, // 70003826 
+0x0F128981, // 70003828 
+0x0F124890, // 7000382A 
+0x0F120252, // 7000382C 
+0x0F124291, // 7000382E 
+0x0F12D902, // 70003830 
+0x0F122102, // 70003832 
+0x0F128181, // 70003834 
+0x0F124770, // 70003836 
+0x0F122101, // 70003838 
+0x0F128181, // 7000383A 
+0x0F124770, // 7000383C 
+0x0F12B5F1, // 7000383E 
+0x0F124E80, // 70003840 
+0x0F128834, // 70003842 
+0x0F122C00, // 70003844 
+0x0F12D03F, // 70003846 
+0x0F122001, // 70003848 
+0x0F122C08, // 7000384A 
+0x0F12D000, // 7000384C 
+0x0F122000, // 7000384E 
+0x0F1270B0, // 70003850 
+0x0F124D7F, // 70003852 
+0x0F122800, // 70003854 
+0x0F12D009, // 70003856 
+0x0F12F000, // 70003858 
+0x0F12FA72, // 7000385A 
+0x0F120028, // 7000385C 
+0x0F1238F0, // 7000385E 
+0x0F126328, // 70003860 
+0x0F127AB0, // 70003862 
+0x0F12217E, // 70003864 
+0x0F124008, // 70003866 
+0x0F1272B0, // 70003868 
+0x0F12E00F, // 7000386A 
+0x0F124F7A, // 7000386C 
+0x0F123780, // 7000386E 
+0x0F128B78, // 70003870 
+0x0F122800, // 70003872 
+0x0F12D005, // 70003874 
+0x0F12F000, // 70003876 
+0x0F12FA6B, // 70003878 
+0x0F122000, // 7000387A 
+0x0F128378, // 7000387C 
+0x0F124976, // 7000387E 
+0x0F128708, // 70003880 
+0x0F122000, // 70003882 
+0x0F12F000, // 70003884 
+0x0F12FA6C, // 70003886 
+0x0F124879, // 70003888 
+0x0F126328, // 7000388A 
+0x0F1278B1, // 7000388C 
+0x0F122700, // 7000388E 
+0x0F120038, // 70003890 
+0x0F122900, // 70003892 
+0x0F12D008, // 70003894 
+0x0F124972, // 70003896 
+0x0F123920, // 70003898 
+0x0F128ACA, // 7000389A 
+0x0F122A00, // 7000389C 
+0x0F12D003, // 7000389E 
+0x0F128B09, // 700038A0 
+0x0F122900, // 700038A2 
+0x0F12D000, // 700038A4 
+0x0F122001, // 700038A6 
+0x0F127170, // 700038A8 
+0x0F122C02, // 700038AA 
+0x0F12D102, // 700038AC 
+0x0F124868, // 700038AE 
+0x0F123860, // 700038B0 
+0x0F126328, // 700038B2 
+0x0F122201, // 700038B4 
+0x0F122C02, // 700038B6 
+0x0F12D000, // 700038B8 
+0x0F122200, // 700038BA 
+0x0F124861, // 700038BC 
+0x0F122110, // 700038BE 
+0x0F12300A, // 700038C0 
+0x0F12F000, // 700038C2 
+0x0F12FA55, // 700038C4 
+0x0F128037, // 700038C6 
+0x0F129900, // 700038C8 
+0x0F120020, // 700038CA 
+0x0F12600C, // 700038CC 
+0x0F12E767, // 700038CE 
+0x0F12B538, // 700038D0 
+0x0F124865, // 700038D2 
+0x0F124669, // 700038D4 
+0x0F123848, // 700038D6 
+0x0F12F000, // 700038D8 
+0x0F12FA52, // 700038DA 
+0x0F124A5E, // 700038DC 
+0x0F124862, // 700038DE 
+0x0F128F51, // 700038E0 
+0x0F122400, // 700038E2 
+0x0F123020, // 700038E4 
+0x0F122900, // 700038E6 
+0x0F12D00A, // 700038E8 
+0x0F128754, // 700038EA 
+0x0F126941, // 700038EC 
+0x0F126451, // 700038EE 
+0x0F126491, // 700038F0 
+0x0F12466B, // 700038F2 
+0x0F128819, // 700038F4 
+0x0F1287D1, // 700038F6 
+0x0F12885B, // 700038F8 
+0x0F120011, // 700038FA 
+0x0F123140, // 700038FC 
+0x0F12800B, // 700038FE 
+0x0F128F91, // 70003900 
+0x0F122900, // 70003902 
+0x0F12D002, // 70003904 
+0x0F128794, // 70003906 
+0x0F126940, // 70003908 
+0x0F126490, // 7000390A 
+0x0F12F000, // 7000390C 
+0x0F12FA40, // 7000390E 
+0x0F12BC38, // 70003910 
+0x0F12BC08, // 70003912 
+0x0F124718, // 70003914 
+0x0F12B5F8, // 70003916 
+0x0F124C56, // 70003918 
+0x0F1289E0, // 7000391A 
+0x0F12F000, // 7000391C 
+0x0F12FA40, // 7000391E 
+0x0F120006, // 70003920 
+0x0F128A20, // 70003922 
+0x0F12F000, // 70003924 
+0x0F12FA44, // 70003926 
+0x0F120007, // 70003928 
+0x0F12484F, // 7000392A 
+0x0F124D4A, // 7000392C 
+0x0F123020, // 7000392E 
+0x0F126CA9, // 70003930 
+0x0F126940, // 70003932 
+0x0F121809, // 70003934 
+0x0F120200, // 70003936 
+0x0F12F000, // 70003938 
+0x0F12FA42, // 7000393A 
+0x0F120400, // 7000393C 
+0x0F120C00, // 7000393E 
+0x0F12002A, // 70003940 
+0x0F12326E, // 70003942 
+0x0F120011, // 70003944 
+0x0F12390A, // 70003946 
+0x0F122305, // 70003948 
+0x0F12F000, // 7000394A 
+0x0F12FA3F, // 7000394C 
+0x0F124C43, // 7000394E 
+0x0F1261A0, // 70003950 
+0x0F128FEB, // 70003952 
+0x0F120002, // 70003954 
+0x0F120031, // 70003956 
+0x0F120018, // 70003958 
+0x0F12F000, // 7000395A 
+0x0F12FA3F, // 7000395C 
+0x0F12466B, // 7000395E 
+0x0F120005, // 70003960 
+0x0F128018, // 70003962 
+0x0F12483C, // 70003964 
+0x0F1269A2, // 70003966 
+0x0F123040, // 70003968 
+0x0F128800, // 7000396A 
+0x0F120039, // 7000396C 
+0x0F12F000, // 7000396E 
+0x0F12FA35, // 70003970 
+0x0F12466B, // 70003972 
+0x0F120006, // 70003974 
+0x0F128058, // 70003976 
+0x0F120021, // 70003978 
+0x0F129800, // 7000397A 
+0x0F12311C, // 7000397C 
+0x0F12F000, // 7000397E 
+0x0F12FA35, // 70003980 
+0x0F124935, // 70003982 
+0x0F123180, // 70003984 
+0x0F12808D, // 70003986 
+0x0F1280CE, // 70003988 
+0x0F128BA1, // 7000398A 
+0x0F124836, // 7000398C 
+0x0F123820, // 7000398E 
+0x0F128001, // 70003990 
+0x0F128BE1, // 70003992 
+0x0F128041, // 70003994 
+0x0F128C21, // 70003996 
+0x0F128081, // 70003998 
+0x0F12E701, // 7000399A 
+0x0F12B5F8, // 7000399C 
+0x0F124E2E, // 7000399E 
+0x0F126C70, // 700039A0 
+0x0F126CB1, // 700039A2 
+0x0F120200, // 700039A4 
+0x0F12F000, // 700039A6 
+0x0F12FA0B, // 700039A8 
+0x0F120400, // 700039AA 
+0x0F120C00, // 700039AC 
+0x0F122401, // 700039AE 
+0x0F120364, // 700039B0 
+0x0F1242A0, // 700039B2 
+0x0F12D200, // 700039B4 
+0x0F120004, // 700039B6 
+0x0F124A27, // 700039B8 
+0x0F120020, // 700039BA 
+0x0F12327E, // 700039BC 
+0x0F121F91, // 700039BE 
+0x0F122303, // 700039C0 
+0x0F12F000, // 700039C2 
+0x0F12FA03, // 700039C4 
+0x0F120405, // 700039C6 
+0x0F120C2D, // 700039C8 
+0x0F124A23, // 700039CA 
+0x0F120020, // 700039CC 
+0x0F12325A, // 700039CE 
+0x0F120011, // 700039D0 
+0x0F12390A, // 700039D2 
+0x0F122305, // 700039D4 
+0x0F12F000, // 700039D6 
+0x0F12F9F9, // 700039D8 
+0x0F12491F, // 700039DA 
+0x0F1264C8, // 700039DC 
+0x0F12491F, // 700039DE 
+0x0F124E21, // 700039E0 
+0x0F1288C8, // 700039E2 
+0x0F122701, // 700039E4 
+0x0F122800, // 700039E6 
+0x0F12D009, // 700039E8 
+0x0F124C23, // 700039EA 
+0x0F1238FF, // 700039EC 
+0x0F121E40, // 700039EE 
+0x0F12D00A, // 700039F0 
+0x0F122804, // 700039F2 
+0x0F12D042, // 700039F4 
+0x0F122806, // 700039F6 
+0x0F12D101, // 700039F8 
+0x0F122000, // 700039FA 
+0x0F1280C8, // 700039FC 
+0x0F1282B7, // 700039FE 
+0x0F122001, // 70003A00 
+0x0F12F000, // 70003A02 
+0x0F12F9FB, // 70003A04 
+0x0F12E6CB, // 70003A06 
+0x0F12000D, // 70003A08 
+0x0F12724F, // 70003A0A 
+0x0F122001, // 70003A0C 
+0x0F12F000, // 70003A0E 
+0x0F12F9FD, // 70003A10 
+0x0F12F000, // 70003A12 
+0x0F12FA03, // 70003A14 
+0x0F124910, // 70003A16 
+0x0F123148, // 70003A18 
+0x0F12C903, // 70003A1A 
+0x0F124348, // 70003A1C 
+0x0F120A00, // 70003A1E 
+0x0F126160, // 70003A20 
+0x0F1220FF, // 70003A22 
+0x0F121D40, // 70003A24 
+0x0F1280E8, // 70003A26 
+0x0F12480C, // 70003A28 
+0x0F123040, // 70003A2A 
+0x0F127707, // 70003A2C 
+0x0F12E7E6, // 70003A2E 
+0x0F123290, // 70003A30 
+0x0F127000, // 70003A32 
+0x0F123294, // 70003A34 
+0x0F127000, // 70003A36 
+0x0F1204A8, // 70003A38 
+0x0F127000, // 70003A3A 
+0x0F1215DC, // 70003A3C 
+0x0F127000, // 70003A3E 
+0x0F125000, // 70003A40 
+0x0F12D000, // 70003A42 
+0x0F121E84, // 70003A44 
+0x0F127000, // 70003A46 
+0x0F121BE4, // 70003A48 
+0x0F127000, // 70003A4A 
+0x0F122EA8, // 70003A4C 
+0x0F127000, // 70003A4E 
+0x0F1221A4, // 70003A50 
+0x0F127000, // 70003A52 
+0x0F120100, // 70003A54 
+0x0F127000, // 70003A56 
+0x0F123F48, // 70003A58 
+0x0F127000, // 70003A5A 
+0x0F1231A0, // 70003A5C 
+0x0F127000, // 70003A5E 
+0x0F1201E8, // 70003A60 
+0x0F127000, // 70003A62 
+0x0F12F2A0, // 70003A64 
+0x0F12D000, // 70003A66 
+0x0F122A44, // 70003A68 
+0x0F127000, // 70003A6A 
+0x0F12F400, // 70003A6C 
+0x0F12D000, // 70003A6E 
+0x0F122024, // 70003A70 
+0x0F127000, // 70003A72 
+0x0F121650, // 70003A74 
+0x0F127000, // 70003A76 
+0x0F122A64, // 70003A78 
+0x0F127000, // 70003A7A 
+0x0F124982, // 70003A7C 
+0x0F12724F, // 70003A7E 
+0x0F1220FF, // 70003A80 
+0x0F121DC0, // 70003A82 
+0x0F1280C8, // 70003A84 
+0x0F12F000, // 70003A86 
+0x0F12F9D1, // 70003A88 
+0x0F124980, // 70003A8A 
+0x0F126ACA, // 70003A8C 
+0x0F12604A, // 70003A8E 
+0x0F122800, // 70003A90 
+0x0F12D006, // 70003A92 
+0x0F12436A, // 70003A94 
+0x0F120001, // 70003A96 
+0x0F120010, // 70003A98 
+0x0F12F000, // 70003A9A 
+0x0F12F991, // 70003A9C 
+0x0F126160, // 70003A9E 
+0x0F12E001, // 70003AA0 
+0x0F12436A, // 70003AA2 
+0x0F126162, // 70003AA4 
+0x0F128BF0, // 70003AA6 
+0x0F122800, // 70003AA8 
+0x0F12D001, // 70003AAA 
+0x0F12F7FF, // 70003AAC 
+0x0F12FF33, // 70003AAE 
+0x0F122000, // 70003AB0 
+0x0F12F000, // 70003AB2 
+0x0F12F9AB, // 70003AB4 
+0x0F124974, // 70003AB6 
+0x0F1220FF, // 70003AB8 
+0x0F121DC0, // 70003ABA 
+0x0F1280C8, // 70003ABC 
+0x0F12E79E, // 70003ABE 
+0x0F12B510, // 70003AC0 
+0x0F12F000, // 70003AC2 
+0x0F12F9BB, // 70003AC4 
+0x0F124870, // 70003AC6 
+0x0F1288C0, // 70003AC8 
+0x0F121FC1, // 70003ACA 
+0x0F1239FD, // 70003ACC 
+0x0F12D103, // 70003ACE 
+0x0F12496F, // 70003AD0 
+0x0F1220FF, // 70003AD2 
+0x0F121C40, // 70003AD4 
+0x0F128048, // 70003AD6 
+0x0F12E605, // 70003AD8 
+0x0F12B5F8, // 70003ADA 
+0x0F122400, // 70003ADC 
+0x0F124D6D, // 70003ADE 
+0x0F12486D, // 70003AE0 
+0x0F12210E, // 70003AE2 
+0x0F128041, // 70003AE4 
+0x0F122101, // 70003AE6 
+0x0F128001, // 70003AE8 
+0x0F12F000, // 70003AEA 
+0x0F12F9AF, // 70003AEC 
+0x0F12486B, // 70003AEE 
+0x0F128840, // 70003AF0 
+0x0F12F000, // 70003AF2 
+0x0F12F9B3, // 70003AF4 
+0x0F124E6A, // 70003AF6 
+0x0F12270D, // 70003AF8 
+0x0F12073F, // 70003AFA 
+0x0F1219E8, // 70003AFC 
+0x0F128803, // 70003AFE 
+0x0F1200E2, // 70003B00 
+0x0F121991, // 70003B02 
+0x0F12804B, // 70003B04 
+0x0F128843, // 70003B06 
+0x0F1252B3, // 70003B08 
+0x0F128882, // 70003B0A 
+0x0F1280CA, // 70003B0C 
+0x0F1288C0, // 70003B0E 
+0x0F128088, // 70003B10 
+0x0F123508, // 70003B12 
+0x0F12042D, // 70003B14 
+0x0F120C2D, // 70003B16 
+0x0F121C64, // 70003B18 
+0x0F120424, // 70003B1A 
+0x0F120C24, // 70003B1C 
+0x0F122C07, // 70003B1E 
+0x0F12D3EC, // 70003B20 
+0x0F12E63D, // 70003B22 
+0x0F12B5F0, // 70003B24 
+0x0F12B085, // 70003B26 
+0x0F126801, // 70003B28 
+0x0F129103, // 70003B2A 
+0x0F126881, // 70003B2C 
+0x0F12040A, // 70003B2E 
+0x0F120C12, // 70003B30 
+0x0F12495C, // 70003B32 
+0x0F128B89, // 70003B34 
+0x0F122900, // 70003B36 
+0x0F12D001, // 70003B38 
+0x0F120011, // 70003B3A 
+0x0F12E000, // 70003B3C 
+0x0F122100, // 70003B3E 
+0x0F129102, // 70003B40 
+0x0F126840, // 70003B42 
+0x0F120401, // 70003B44 
+0x0F129803, // 70003B46 
+0x0F120C09, // 70003B48 
+0x0F12F000, // 70003B4A 
+0x0F12F98F, // 70003B4C 
+0x0F124854, // 70003B4E 
+0x0F123080, // 70003B50 
+0x0F128900, // 70003B52 
+0x0F122800, // 70003B54 
+0x0F12D039, // 70003B56 
+0x0F122100, // 70003B58 
+0x0F124854, // 70003B5A 
+0x0F124D52, // 70003B5C 
+0x0F124684, // 70003B5E 
+0x0F124B53, // 70003B60 
+0x0F124C4F, // 70003B62 
+0x0F1288DA, // 70003B64 
+0x0F120048, // 70003B66 
+0x0F1200D7, // 70003B68 
+0x0F12193E, // 70003B6A 
+0x0F12197F, // 70003B6C 
+0x0F12183F, // 70003B6E 
+0x0F125A36, // 70003B70 
+0x0F128AFF, // 70003B72 
+0x0F12437E, // 70003B74 
+0x0F1200B6, // 70003B76 
+0x0F120C37, // 70003B78 
+0x0F121906, // 70003B7A 
+0x0F123680, // 70003B7C 
+0x0F128177, // 70003B7E 
+0x0F121C52, // 70003B80 
+0x0F1200D2, // 70003B82 
+0x0F121914, // 70003B84 
+0x0F121952, // 70003B86 
+0x0F121812, // 70003B88 
+0x0F125A24, // 70003B8A 
+0x0F128AD2, // 70003B8C 
+0x0F124354, // 70003B8E 
+0x0F1200A2, // 70003B90 
+0x0F120C12, // 70003B92 
+0x0F128272, // 70003B94 
+0x0F12891C, // 70003B96 
+0x0F12895B, // 70003B98 
+0x0F124367, // 70003B9A 
+0x0F12435A, // 70003B9C 
+0x0F121943, // 70003B9E 
+0x0F123340, // 70003BA0 
+0x0F1289DB, // 70003BA2 
+0x0F129C02, // 70003BA4 
+0x0F1218BA, // 70003BA6 
+0x0F124363, // 70003BA8 
+0x0F1218D2, // 70003BAA 
+0x0F120212, // 70003BAC 
+0x0F120C12, // 70003BAE 
+0x0F12466B, // 70003BB0 
+0x0F12521A, // 70003BB2 
+0x0F124663, // 70003BB4 
+0x0F127DDB, // 70003BB6 
+0x0F12435A, // 70003BB8 
+0x0F129B03, // 70003BBA 
+0x0F120252, // 70003BBC 
+0x0F120C12, // 70003BBE 
+0x0F12521A, // 70003BC0 
+0x0F121C49, // 70003BC2 
+0x0F120409, // 70003BC4 
+0x0F120C09, // 70003BC6 
+0x0F122904, // 70003BC8 
+0x0F12D3C9, // 70003BCA 
+0x0F12B005, // 70003BCC 
+0x0F12BCF0, // 70003BCE 
+0x0F12BC08, // 70003BD0 
+0x0F124718, // 70003BD2 
+0x0F12B510, // 70003BD4 
+0x0F12F7FF, // 70003BD6 
+0x0F12FF80, // 70003BD8 
+0x0F12F000, // 70003BDA 
+0x0F12F94F, // 70003BDC 
+0x0F12E582, // 70003BDE 
+0x0F12B570, // 70003BE0 
+0x0F126804, // 70003BE2 
+0x0F12F000, // 70003BE4 
+0x0F12F952, // 70003BE6 
+0x0F124D32, // 70003BE8 
+0x0F128C29, // 70003BEA 
+0x0F121A40, // 70003BEC 
+0x0F1242A0, // 70003BEE 
+0x0F12D901, // 70003BF0 
+0x0F120020, // 70003BF2 
+0x0F12E003, // 70003BF4 
+0x0F12F000, // 70003BF6 
+0x0F12F949, // 70003BF8 
+0x0F128C29, // 70003BFA 
+0x0F121A40, // 70003BFC 
+0x0F126268, // 70003BFE 
+0x0F12F000, // 70003C00 
+0x0F12F94C, // 70003C02 
+0x0F1262A8, // 70003C04 
+0x0F12F000, // 70003C06 
+0x0F12F951, // 70003C08 
+0x0F126328, // 70003C0A 
+0x0F128869, // 70003C0C 
+0x0F122900, // 70003C0E 
+0x0F12D000, // 70003C10 
+0x0F1262A8, // 70003C12 
+0x0F124828, // 70003C14 
+0x0F126B00, // 70003C16 
+0x0F128C00, // 70003C18 
+0x0F122800, // 70003C1A 
+0x0F12D11B, // 70003C1C 
+0x0F126AA8, // 70003C1E 
+0x0F12F000, // 70003C20 
+0x0F12F94C, // 70003C22 
+0x0F1261E8, // 70003C24 
+0x0F124A1E, // 70003C26 
+0x0F123280, // 70003C28 
+0x0F128B91, // 70003C2A 
+0x0F122900, // 70003C2C 
+0x0F12D00B, // 70003C2E 
+0x0F120011, // 70003C30 
+0x0F123120, // 70003C32 
+0x0F128809, // 70003C34 
+0x0F124288, // 70003C36 
+0x0F12D907, // 70003C38 
+0x0F1261E9, // 70003C3A 
+0x0F128C28, // 70003C3C 
+0x0F121A08, // 70003C3E 
+0x0F1262A8, // 70003C40 
+0x0F12F000, // 70003C42 
+0x0F12F92B, // 70003C44 
+0x0F1262A8, // 70003C46 
+0x0F12E502, // 70003C48 
+0x0F128BD1, // 70003C4A 
+0x0F124288, // 70003C4C 
+0x0F12D800, // 70003C4E 
+0x0F120008, // 70003C50 
+0x0F1261E8, // 70003C52 
+0x0F12E4FC, // 70003C54 
+0x0F12F000, // 70003C56 
+0x0F12F919, // 70003C58 
+0x0F1261E8, // 70003C5A 
+0x0F12E4F8, // 70003C5C 
+0x0F12B510, // 70003C5E 
+0x0F12F000, // 70003C60 
+0x0F12F934, // 70003C62 
+0x0F12480E, // 70003C64 
+0x0F1230A0, // 70003C66 
+0x0F128841, // 70003C68 
+0x0F122900, // 70003C6A 
+0x0F12D007, // 70003C6C 
+0x0F124A07, // 70003C6E 
+0x0F123280, // 70003C70 
+0x0F126953, // 70003C72 
+0x0F124A11, // 70003C74 
+0x0F12428B, // 70003C76 
+0x0F12D202, // 70003C78 
+0x0F128880, // 70003C7A 
+0x0F1281D0, // 70003C7C 
+0x0F12E532, // 70003C7E 
+0x0F1288C0, // 70003C80 
+0x0F1281D0, // 70003C82 
+0x0F12E52F, // 70003C84 
+0x0F120000, // 70003C86 
+0x0F1231A0, // 70003C88 
+0x0F127000, // 70003C8A 
+0x0F1229E4, // 70003C8C 
+0x0F127000, // 70003C8E 
+0x0F12C100, // 70003C90 
+0x0F12D000, // 70003C92 
+0x0F12A006, // 70003C94 
+0x0F120000, // 70003C96 
+0x0F12A000, // 70003C98 
+0x0F12D000, // 70003C9A 
+0x0F12064C, // 70003C9C 
+0x0F127000, // 70003C9E 
+0x0F123F48, // 70003CA0 
+0x0F127000, // 70003CA2 
+0x0F1207C4, // 70003CA4 
+0x0F127000, // 70003CA6 
+0x0F1207E8, // 70003CA8 
+0x0F127000, // 70003CAA 
+0x0F122B24, // 70003CAC 
+0x0F127000, // 70003CAE 
+0x0F121FA0, // 70003CB0 
+0x0F127000, // 70003CB2 
+0x0F121E3C, // 70003CB4 
+0x0F127000, // 70003CB6 
+0x0F1221A4, // 70003CB8 
+0x0F127000, // 70003CBA 
+0x0F12E200, // 70003CBC 
+0x0F12D000, // 70003CBE 
+0x0F124778, // 70003CC0 
+0x0F1246C0, // 70003CC2 
+0x0F12C000, // 70003CC4 
+0x0F12E59F, // 70003CC6 
+0x0F12FF1C, // 70003CC8 
+0x0F12E12F, // 70003CCA 
+0x0F121F63, // 70003CCC 
+0x0F120001, // 70003CCE 
+0x0F124778, // 70003CD0 
+0x0F1246C0, // 70003CD2 
+0x0F12C000, // 70003CD4 
+0x0F12E59F, // 70003CD6 
+0x0F12FF1C, // 70003CD8 
+0x0F12E12F, // 70003CDA 
+0x0F121EDF, // 70003CDC 
+0x0F120001, // 70003CDE 
+0x0F124778, // 70003CE0 
+0x0F1246C0, // 70003CE2 
+0x0F12C000, // 70003CE4 
+0x0F12E59F, // 70003CE6 
+0x0F12FF1C, // 70003CE8 
+0x0F12E12F, // 70003CEA 
+0x0F12495F, // 70003CEC 
+0x0F120000, // 70003CEE 
+0x0F124778, // 70003CF0 
+0x0F1246C0, // 70003CF2 
+0x0F12C000, // 70003CF4 
+0x0F12E59F, // 70003CF6 
+0x0F12FF1C, // 70003CF8 
+0x0F12E12F, // 70003CFA 
+0x0F12E403, // 70003CFC 
+0x0F120000, // 70003CFE 
+0x0F124778, // 70003D00 
+0x0F1246C0, // 70003D02 
+0x0F12C000, // 70003D04 
+0x0F12E59F, // 70003D06 
+0x0F12FF1C, // 70003D08 
+0x0F12E12F, // 70003D0A 
+0x0F1224B3, // 70003D0C 
+0x0F120001, // 70003D0E 
+0x0F124778, // 70003D10 
+0x0F1246C0, // 70003D12 
+0x0F12C000, // 70003D14 
+0x0F12E59F, // 70003D16 
+0x0F12FF1C, // 70003D18 
+0x0F12E12F, // 70003D1A 
+0x0F12EECD, // 70003D1C 
+0x0F120000, // 70003D1E 
+0x0F124778, // 70003D20 
+0x0F1246C0, // 70003D22 
+0x0F12C000, // 70003D24 
+0x0F12E59F, // 70003D26 
+0x0F12FF1C, // 70003D28 
+0x0F12E12F, // 70003D2A 
+0x0F12F049, // 70003D2C 
+0x0F120000, // 70003D2E 
+0x0F124778, // 70003D30 
+0x0F1246C0, // 70003D32 
+0x0F12C000, // 70003D34 
+0x0F12E59F, // 70003D36 
+0x0F12FF1C, // 70003D38 
+0x0F12E12F, // 70003D3A 
+0x0F1212DF, // 70003D3C 
+0x0F120000, // 70003D3E 
+0x0F124778, // 70003D40 
+0x0F1246C0, // 70003D42 
+0x0F12C000, // 70003D44 
+0x0F12E59F, // 70003D46 
+0x0F12FF1C, // 70003D48 
+0x0F12E12F, // 70003D4A 
+0x0F12F05B, // 70003D4C 
+0x0F120000, // 70003D4E 
+0x0F124778, // 70003D50 
+0x0F1246C0, // 70003D52 
+0x0F12C000, // 70003D54 
+0x0F12E59F, // 70003D56 
+0x0F12FF1C, // 70003D58 
+0x0F12E12F, // 70003D5A 
+0x0F12F07B, // 70003D5C 
+0x0F120000, // 70003D5E 
+0x0F124778, // 70003D60 
+0x0F1246C0, // 70003D62 
+0x0F12C000, // 70003D64 
+0x0F12E59F, // 70003D66 
+0x0F12FF1C, // 70003D68 
+0x0F12E12F, // 70003D6A 
+0x0F12FE6D, // 70003D6C 
+0x0F120000, // 70003D6E 
+0x0F124778, // 70003D70 
+0x0F1246C0, // 70003D72 
+0x0F12C000, // 70003D74 
+0x0F12E59F, // 70003D76 
+0x0F12FF1C, // 70003D78 
+0x0F12E12F, // 70003D7A 
+0x0F123295, // 70003D7C 
+0x0F120000, // 70003D7E 
+0x0F124778, // 70003D80 
+0x0F1246C0, // 70003D82 
+0x0F12C000, // 70003D84 
+0x0F12E59F, // 70003D86 
+0x0F12FF1C, // 70003D88 
+0x0F12E12F, // 70003D8A 
+0x0F12234F, // 70003D8C 
+0x0F120000, // 70003D8E 
+0x0F124778, // 70003D90 
+0x0F1246C0, // 70003D92 
+0x0F12C000, // 70003D94 
+0x0F12E59F, // 70003D96 
+0x0F12FF1C, // 70003D98 
+0x0F12E12F, // 70003D9A 
+0x0F124521, // 70003D9C 
+0x0F120000, // 70003D9E 
+0x0F124778, // 70003DA0 
+0x0F1246C0, // 70003DA2 
+0x0F12C000, // 70003DA4 
+0x0F12E59F, // 70003DA6 
+0x0F12FF1C, // 70003DA8 
+0x0F12E12F, // 70003DAA 
+0x0F127C0D, // 70003DAC 
+0x0F120000, // 70003DAE 
+0x0F124778, // 70003DB0 
+0x0F1246C0, // 70003DB2 
+0x0F12C000, // 70003DB4 
+0x0F12E59F, // 70003DB6 
+0x0F12FF1C, // 70003DB8 
+0x0F12E12F, // 70003DBA 
+0x0F127C2B, // 70003DBC 
+0x0F120000, // 70003DBE 
+0x0F124778, // 70003DC0 
+0x0F1246C0, // 70003DC2 
+0x0F12F004, // 70003DC4 
+0x0F12E51F, // 70003DC6 
+0x0F1224C4, // 70003DC8 
+0x0F120001, // 70003DCA 
+0x0F124778, // 70003DCC 
+0x0F1246C0, // 70003DCE 
+0x0F12C000, // 70003DD0 
+0x0F12E59F, // 70003DD2 
+0x0F12FF1C, // 70003DD4 
+0x0F12E12F, // 70003DD6 
+0x0F123183, // 70003DD8 
+0x0F120000, // 70003DDA 
+0x0F124778, // 70003DDC 
+0x0F1246C0, // 70003DDE 
+0x0F12C000, // 70003DE0 
+0x0F12E59F, // 70003DE2 
+0x0F12FF1C, // 70003DE4 
+0x0F12E12F, // 70003DE6 
+0x0F12302F, // 70003DE8 
+0x0F120000, // 70003DEA 
+0x0F124778, // 70003DEC 
+0x0F1246C0, // 70003DEE 
+0x0F12C000, // 70003DF0 
+0x0F12E59F, // 70003DF2 
+0x0F12FF1C, // 70003DF4 
+0x0F12E12F, // 70003DF6 
+0x0F12EF07, // 70003DF8 
+0x0F120000, // 70003DFA 
+0x0F124778, // 70003DFC 
+0x0F1246C0, // 70003DFE 
+0x0F12C000, // 70003E00 
+0x0F12E59F, // 70003E02 
+0x0F12FF1C, // 70003E04 
+0x0F12E12F, // 70003E06 
+0x0F1248FB, // 70003E08 
+0x0F120000, // 70003E0A 
+0x0F124778, // 70003E0C 
+0x0F1246C0, // 70003E0E 
+0x0F12C000, // 70003E10 
+0x0F12E59F, // 70003E12 
+0x0F12FF1C, // 70003E14 
+0x0F12E12F, // 70003E16 
+0x0F12F0B1, // 70003E18 
+0x0F120000, // 70003E1A 
+0x0F124778, // 70003E1C 
+0x0F1246C0, // 70003E1E 
+0x0F12C000, // 70003E20 
+0x0F12E59F, // 70003E22 
+0x0F12FF1C, // 70003E24 
+0x0F12E12F, // 70003E26 
+0x0F12EEDF, // 70003E28 
+0x0F120000, // 70003E2A 
+0x0F124778, // 70003E2C 
+0x0F1246C0, // 70003E2E 
+0x0F12C000, // 70003E30 
+0x0F12E59F, // 70003E32 
+0x0F12FF1C, // 70003E34 
+0x0F12E12F, // 70003E36 
+0x0F12AEF1, // 70003E38 
+0x0F120000, // 70003E3A 
+0x0F124778, // 70003E3C 
+0x0F1246C0, // 70003E3E 
+0x0F12C000, // 70003E40 
+0x0F12E59F, // 70003E42 
+0x0F12FF1C, // 70003E44 
+0x0F12E12F, // 70003E46 
+0x0F1202EB, // 70003E48 
+0x0F120001, // 70003E4A 
+0x0F124778, // 70003E4C 
+0x0F1246C0, // 70003E4E 
+0x0F12C000, // 70003E50 
+0x0F12E59F, // 70003E52 
+0x0F12FF1C, // 70003E54 
+0x0F12E12F, // 70003E56 
+0x0F12FD21, // 70003E58 
+0x0F120000, // 70003E5A 
+0x0F124778, // 70003E5C 
+0x0F1246C0, // 70003E5E 
+0x0F12C000, // 70003E60 
+0x0F12E59F, // 70003E62 
+0x0F12FF1C, // 70003E64 
+0x0F12E12F, // 70003E66 
+0x0F12FDAF, // 70003E68 
+0x0F120000, // 70003E6A 
+0x0F124778, // 70003E6C 
+0x0F1246C0, // 70003E6E 
+0x0F12C000, // 70003E70 
+0x0F12E59F, // 70003E72 
+0x0F12FF1C, // 70003E74 
+0x0F12E12F, // 70003E76 
+0x0F125027, // 70003E78 
+0x0F120000, // 70003E7A 
+0x0F124778, // 70003E7C 
+0x0F1246C0, // 70003E7E 
+0x0F12C000, // 70003E80 
+0x0F12E59F, // 70003E82 
+0x0F12FF1C, // 70003E84 
+0x0F12E12F, // 70003E86 
+0x0F1204C9, // 70003E88 
+0x0F120000, // 70003E8A 
+0x0F124778, // 70003E8C 
+0x0F1246C0, // 70003E8E 
+0x0F12C000, // 70003E90 
+0x0F12E59F, // 70003E92 
+0x0F12FF1C, // 70003E94 
+0x0F12E12F, // 70003E96 
+0x0F1239DF, // 70003E98 
+0x0F120000, // 70003E9A 
+0x0F124778, // 70003E9C 
+0x0F1246C0, // 70003E9E 
+0x0F12C000, // 70003EA0 
+0x0F12E59F, // 70003EA2 
+0x0F12FF1C, // 70003EA4 
+0x0F12E12F, // 70003EA6 
+0x0F126177, // 70003EA8 
+0x0F120000, // 70003EAA 
+0x0F124778, // 70003EAC 
+0x0F1246C0, // 70003EAE 
+0x0F12C000, // 70003EB0 
+0x0F12E59F, // 70003EB2 
+0x0F12FF1C, // 70003EB4 
+0x0F12E12F, // 70003EB6 
+0x0F12424F, // 70003EB8 
+0x0F120000, // 70003EBA 
+0x0F124778, // 70003EBC 
+0x0F1246C0, // 70003EBE 
+0x0F12C000, // 70003EC0 
+0x0F12E59F, // 70003EC2 
+0x0F12FF1C, // 70003EC4 
+0x0F12E12F, // 70003EC6 
+0x0F123F0D, // 70003EC8 
+0x0F120000, // 70003ECA 
+0x0F124778, // 70003ECC 
+0x0F1246C0, // 70003ECE 
+0x0F12C000, // 70003ED0 
+0x0F12E59F, // 70003ED2 
+0x0F12FF1C, // 70003ED4 
+0x0F12E12F, // 70003ED6 
+0x0F1202B9, // 70003ED8 
+0x0F120001, // 70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007,// clks_src_gf_force_enable
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120000, //on/off AFIT by NB option
+
+0x0F120005, //NormBR[0]
+0x0F120019, //NormBR[1]
+0x0F120050, //NormBR[2]
+0x0F120300, //NormBR[3]
+0x0F120375, //NormBR[4]
+
+// Flash
+0x002A3F82,
+0x0F120000,	//TNP_Regs_PreflashStart
+0x0F120000,	//TNP_Regs_PreflashEnd
+0x0F120260,	//TNP_Regs_PreWP_r
+0x0F120240, //TNP_Regs_PreWP_b
+
+0x002A3F98,	//BR Tuning
+0x0F120100, /* TNP_Regs_BrRatioIn_0_ */
+0x0F120180,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120080, /* TNP_Regs_BrRatioOut_0_ */
+0x0F120050,
+0x0F120040,
+0x0F120030,
+0x0F120020,
+
+0x0F120030,	//WP Tuning
+0x0F120040,	//TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	//TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	//T_BR tune	
+0x0F120150,	//TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B,
+0x0F12002E,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120235, //0244 0258 AWB R point          //0258 0245 0258
+0x0F12024A, //024D 0220 AWB B point          //0220 0245 0245
+
+
+//         //         //         //         //         //         //         //         //   
+// Analog & APS settings         //         //         //         //         //         //   
+// This register is for FACTORY ONLY. If you change it without prior notification         //
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future         //         //  
+//         //         //         //         //         //         //         //         //   
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshadi
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, //analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, //ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, //cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, //adc_sat[7:0]=84d (500mV)
+0x0F120002, //ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, //rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, //msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, //rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, //dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, //comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, //pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, //clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001, //ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp
+
+0x002AF42E,
+0x0F120406, //fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg
+
+0x002AF434,
+0x0F120003, //dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, //reg_tune_pix[7:0]
+0x0F120002, //reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, //reg_tune_rg[7:0] (2.83V)
+0x0F120004, //reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, //blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, //srx_en[0]
+
+0x002A0054,
+0x0F120028, //pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, //div_dbr[7:4]
+
+0x002AF132,
+0x0F120206, //tgr_frame_decription 4
+0x002AF152,
+0x0F120206, //tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, //tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, //tgr_frame_params_descriptor_6
+//===========================================================================================
+
+//============================= Line-ADLC Tuning ============================================
+0x002AE412,
+0x0F120008, //adlc_tune_offset_gr[7:0]
+0x0F120008, //adlc_tune_offset_r[7:0]
+0x0F120010, //adlc_tune_offset_b[7:0]
+0x0F120010, //adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, //adlc_qec[2:0]
+//===========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F120132, //0138//awbb_IntcR
+0x0F12010A, //011C//awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType        // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1       // No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041, //REG_TC_IPRM_CM_Init_GpioConfig1        // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C, //REG_TC_IPRM_CM_Init_Mi2cBits        // Use GPIO_5 for SCL GPIO_6 for S
+0x0F120190, //REG_TC_IPRM_CM_Init_Mi2cRateKhz        // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000//#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121002, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120003, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120602, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 : Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120003, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200CC, //#af_search_usPeakThr  for 80%
+0x0F1200A0, //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F12952F, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120010, //#af_pos_usTableLastInd 10h + 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120033, //#af_pos_usTable_1_  51   
+0x0F120036, //#af_pos_usTable_2_  54	
+0x0F120039, //#af_pos_usTable_3_  57	
+0x0F12003D, //#af_pos_usTable_4_  61   
+0x0F120041, //#af_pos_usTable_5_  65	
+0x0F120045, //#af_pos_usTable_6_  69	
+0x0F120049, //#af_pos_usTable_7_  73	
+0x0F12004E, //#af_pos_usTable_8_  78	
+0x0F120053, //#af_pos_usTable_9_  83	
+0x0F120059, //#af_pos_usTable_10_ 89	
+0x0F120060, //#af_pos_usTable_11_ 104	
+0x0F120068, //#af_pos_usTable_12_ 109	
+0x0F120072, //#af_pos_usTable_13_ 114	
+0x0F12007D, //#af_pos_usTable_14_ 125
+0x0F120089, //#af_pos_usTable_15_ 137	
+0x0F120096, //#af_pos_usTable_16_ 150
+
+//8. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120020, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120008, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120008, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001, //REG_TC_IPRM_AuxConfig// bit[0] : Flash is in use bit[1] : Mechanical shutter is
+0x0F120003, //REG_TC_IPRM_AuxPolarity// bit[0] : Flash polarity (1 is active high) bit[1] : M
+0x0F120003, //REG_TC_IPRM_AuxGpios//1-4 : Flash GPIO number If GPIO number is overaped with A
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12005C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000,//senHal_bSRX//SRX off
+
+0x002A1680,
+0x0F120002,//senHal_NExpLinesCheckFine//0004            
+
+0x002A0ED2,
+0x0F120FA0,//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor                  // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType                  // 0:Full 1:digital 2:PL
+0x0F120000, //senHal_SamplingMode                  // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK   
+0x002A0188,
+0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+0x0F120000, //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001, //REG_TC_IPRM_UseNPviClocks
+0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll by
+
+
+//SCLK & PCLK  // clock set 0
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+//SCLK & PCLK // clock set 1
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+//SCLK & PCLK // clock set 2                                              
+0x0F1238A4,	//38A4	                  //36B0	             
+0x0F1254F0,	//4E20	                  //3A98	             
+0x0F1254F8,	//57E4	                  //61A8	             
+
+0x002A1B78,
+0x0F1238A4, //  REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_0__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4, //  REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_1__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4, //  REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074, //  REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004, //  REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000, //  REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002, //  REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003, //  REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001, //  REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006, //  REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C, //  REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //  REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6, //  REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C, //  REGM_gSensorClocks_2__usSysDiv
+0x0F120001, //  REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A, //p10
+
+
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6,
+0x0F120800, //REG_TC_GP_PrevReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_PrevReqInputHeight//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_PrevInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_PrevInputHeightOfs//Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 640 480 system 52M PCLK 87M
+//===================================================================
+0x002A023E,
+0x0F120500, //REG_0TC_PCFG_usWidth
+0x0F120400, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_PCFG_usMinOut4KHzRate
+          
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+          
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+0x0F120535, //REG_0TC_PCFG_usMaxFrTimeMsecMult10//max frame time : 30fps 014D 15fps 029a; a6a
+0x0F12029A, //REG_0TC_PCFG_usMinFrTimeMsecMult10//min frame time : 30fps 014D 15fps 029a; a6a
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+0x0F120003, //REG_0TC_PCFG_uPrevMirror
+0x0F120003, //REG_0TC_PCFG_uCaptureMirror
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 87M
+//===================================================================
+
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format                              //PCAM 5:YUV
+0x0F1254F6,	//REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_CCFG_usMinOut4KHzRate
+
+0x002A033E,
+0x0F120010, //REG_0TC_CCFG_PVIMask        => cmk 2010.10.29 s0042 => s0052 
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+0x002A0346,
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120000,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F00,
+0x0F120000,
+0x0F120F0F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+
+// TVAR_ash_pGAS_low
+0x0F126E49,
+0x0F12FB98,
+0x0F12F348,
+0x0F121BD6,
+0x0F12EBEF,
+0x0F1203D3,
+0x0F12EC8D,
+0x0F12F239,
+0x0F120E64,
+0x0F12F7EA,
+0x0F12FD3B,
+0x0F120A7C,
+0x0F12FC9C,
+0x0F120BD3,
+0x0F12F2E5,
+0x0F120619,
+0x0F120772,
+0x0F12F0B0,
+0x0F12184E,
+0x0F12F95F,
+0x0F120B1A,
+0x0F12FC45,
+0x0F12F716,
+0x0F120DCD,
+0x0F12EF24,
+0x0F120221,
+0x0F12F6BD,
+0x0F1204CB,
+0x0F1200B1,
+0x0F12FEB0,
+0x0F120268,
+0x0F1202C7,
+0x0F12010A,
+0x0F12FF93,
+0x0F12036D,
+0x0F12F859,
+0x0F1281D0,
+0x0F12FA32,
+0x0F12EFDB,
+0x0F12234D,
+0x0F12E799,
+0x0F120337,
+0x0F12EB05,
+0x0F12E8F9,
+0x0F12152E,
+0x0F12F0D5,
+0x0F120842,
+0x0F12043A,
+0x0F12F461,
+0x0F120E58,
+0x0F12F658,
+0x0F12075D,
+0x0F12F78D,
+0x0F12FDE9,
+0x0F12277A,
+0x0F12FFDE,
+0x0F12FD3B,
+0x0F12FE50,
+0x0F120AD1,
+0x0F12FE2C,
+0x0F12E90D,
+0x0F12F7B0,
+0x0F1205DB,
+0x0F1202CD,
+0x0F12F4F1,
+0x0F1202A8,
+0x0F12FDDC,
+0x0F120B59,
+0x0F12F74E,
+0x0F1203D5,
+0x0F12FF4F,
+0x0F1200F7,
+0x0F126A44,
+0x0F12FAD6,
+0x0F12F261,
+0x0F121F28,
+0x0F12E691,
+0x0F1207D2,
+0x0F12EE85,
+0x0F12F426,
+0x0F120F26,
+0x0F12F34B,
+0x0F120036,
+0x0F120C0F,
+0x0F12FDA9,
+0x0F1209EA,
+0x0F12F27A,
+0x0F120CD5,
+0x0F1201E1,
+0x0F12ED41,
+0x0F121DB5,
+0x0F12FD26,
+0x0F1203F7,
+0x0F12F7BB,
+0x0F12FE81,
+0x0F1212D3,
+0x0F12E061,
+0x0F12F81C,
+0x0F1207B1,
+0x0F120408,
+0x0F12F860,
+0x0F12FC9A,
+0x0F120DDE,
+0x0F120C9C,
+0x0F12F2A4,
+0x0F1202EB,
+0x0F12099B,
+0x0F12F5A6,
+0x0F127243,
+0x0F12F74D,
+0x0F12F74B,
+0x0F121800,
+0x0F12EF22,
+0x0F120263,
+0x0F12EBE7,
+0x0F12F5A4,
+0x0F1209D3,
+0x0F12FAB8,
+0x0F12FDFF,
+0x0F12086B,
+0x0F120338,
+0x0F120514,
+0x0F12F840,
+0x0F120768,
+0x0F12FE55,
+0x0F12F884,
+0x0F121488,
+0x0F12FFCD,
+0x0F12035B,
+0x0F12FA4E,
+0x0F1201DB,
+0x0F1206D6,
+0x0F12EE19,
+0x0F12FEA3,
+0x0F12FE8C,
+0x0F1203A3,
+0x0F12FDDB,
+0x0F12FD9B,
+0x0F12035E,
+0x0F1203F2,
+0x0F12FCBD,
+0x0F120300,
+0x0F12FF2E,
+0x0F12FE03,
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F123F00,	//TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F124000, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F123F00,	//TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[0][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[0][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[0][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[0][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[0][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[0][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[0][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[0][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[0][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[0][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[0][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[0][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[0][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[0][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[0][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[0][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[0][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[0][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[1][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[1][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[1][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[1][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[1][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[1][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[1][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[1][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[1][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[1][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[1][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[1][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[1][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[1][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[1][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[1][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[1][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[1][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBIndoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBIndoor[2][1]
+0x0F120015, //saRR_usDualGammaLutRGBIndoor[2][2]
+0x0F120032, //saRR_usDualGammaLutRGBIndoor[2][3]
+0x0F12006C, //saRR_usDualGammaLutRGBIndoor[2][4]
+0x0F1200D0, //saRR_usDualGammaLutRGBIndoor[2][5]
+0x0F120129, //saRR_usDualGammaLutRGBIndoor[2][6]
+0x0F120151, //saRR_usDualGammaLutRGBIndoor[2][7]
+0x0F120174, //saRR_usDualGammaLutRGBIndoor[2][8]
+0x0F1201AA, //saRR_usDualGammaLutRGBIndoor[2][9]
+0x0F1201D7, //saRR_usDualGammaLutRGBIndoor[2][10]
+0x0F1201FE, //saRR_usDualGammaLutRGBIndoor[2][11]
+0x0F120221, //saRR_usDualGammaLutRGBIndoor[2][12]
+0x0F120252, //saRR_usDualGammaLutRGBIndoor[2][13]
+0x0F120281, //saRR_usDualGammaLutRGBIndoor[2][14]
+0x0F1202E1, //saRR_usDualGammaLutRGBIndoor[2][15]
+0x0F120345, //saRR_usDualGammaLutRGBIndoor[2][16]
+0x0F12039C, //saRR_usDualGammaLutRGBIndoor[2][17]
+0x0F1203D9, //saRR_usDualGammaLutRGBIndoor[2][18]
+0x0F1203FF, //saRR_usDualGammaLutRGBIndoor[2][19]
+
+//s002A06D8
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120000, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120008, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120013, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F12002C, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12005C, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200BB, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120109, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12012C, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014C, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120185, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F1201B9, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F1201E8, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F120210, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F12024C, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F120280, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F1202D4, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120324, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F12036C, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F1203AC, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F1203E6, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR//MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Nigh
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight 
+
+//AE_state
+0x002A04EE,
+0x0F12010E, //#lt_uLimitHigh
+0x0F1200F5, //#lt_uLimitLow
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //#lt_uMaxExp1
+0x002A0508,
+0x0F12681F, //#lt_uMaxExp2
+0x002A050C,
+0x0F128227, //#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F12681F, //#lt_uCapMaxExp2
+0x002A051C,
+0x0F128227, //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F1201E0, //#lt_uMaxAnGain1
+0x0F1201E0, //#lt_uMaxAnGain2
+0x0F120300, //#lt_uMaxAnGain3
+0x0F120710, //#lt_uMaxAnGain4
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F1201E0, //#lt_uCapMaxAnGain1
+0x0F1201E0, //#lt_uCapMaxAnGain2
+0x0F120300, //#lt_uCapMaxAnGain3
+0x0F120710, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,
+0x0F120000, //ae_WeightTbl_16[0]
+0x0F120000, //ae_WeightTbl_16[1]
+0x0F120000, //ae_WeightTbl_16[2]
+0x0F120000, //ae_WeightTbl_16[3]
+0x0F120101, //ae_WeightTbl_16[4]
+0x0F120101, //ae_WeightTbl_16[5]
+0x0F120101, //ae_WeightTbl_16[6]
+0x0F120101, //ae_WeightTbl_16[7]
+0x0F120101, //ae_WeightTbl_16[8]
+0x0F120201, //ae_WeightTbl_16[9]
+0x0F120102, //ae_WeightTbl_16[10]
+0x0F120101, //ae_WeightTbl_16[11]
+0x0F120101, //ae_WeightTbl_16[12]
+0x0F120202, //ae_WeightTbl_16[13]
+0x0F120202, //ae_WeightTbl_16[14]
+0x0F120101, //ae_WeightTbl_16[15]
+0x0F120101, //ae_WeightTbl_16[16]
+0x0F120202, //ae_WeightTbl_16[17]
+0x0F120202, //ae_WeightTbl_16[18]
+0x0F120101, //ae_WeightTbl_16[19]
+0x0F120201, //ae_WeightTbl_16[20]
+0x0F120202, //ae_WeightTbl_16[21]
+0x0F120202, //ae_WeightTbl_16[22]
+0x0F120102, //ae_WeightTbl_16[23]
+0x0F120201, //ae_WeightTbl_16[24]
+0x0F120202, //ae_WeightTbl_16[25]
+0x0F120202, //ae_WeightTbl_16[26]
+0x0F120102, //ae_WeightTbl_16[27]
+0x0F120101, //ae_WeightTbl_16[28]
+0x0F120101, //ae_WeightTbl_16[29]
+0x0F120101, //ae_WeightTbl_16[30]
+0x0F120101, //ae_WeightTbl_16[31]
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F1205F0, //awbb_GamutWidthThr1
+0x0F1201F4, //awbb_GamutHeightThr1
+0x0F12006C, //awbb_GamutWidthThr2
+0x0F120038, //awbb_GamutHeightThr2
+0x002A1020,
+0x0F12000C, //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A291A,
+0x0F120006, // #Mon_AWB_ByPassMode// [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+0x0F120008,	//001E//awbb_WpFilterMinThr
+0x0F120160,	//0190//awbb_WpFilterMaxThr
+0x0F1200A0, //awbb_WpFilterCoef
+0x0F120004, //awbb_WpFilterSize
+0x0F120001, //awbb_otp_disable
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F1203C0, //03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F1203E2, //03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F120356, //0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F1203FC, //03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F12031E, //031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1203FE, //03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F1202F0, //02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F1203F0, //03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F1202CA, //02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F1203CC, //03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202A8, //02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F12037A, //037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F120280, //0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F12033C, //033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F120260, //0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F12030A, //030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120242, //0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F1202DC, //02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F120228, //0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F1202B2, //02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F12020E, //020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120290, //02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F1201F8, //01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120276, //0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201E8, //01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F120268, //0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201DC, //01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F120256, //0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201E0, //01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F120238, //0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201EC, //01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F12020E, //020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000, //0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //awbb_IndoorGrZones_m_Grid
+0x002A0F80,
+0x0F1200E6, //awbb_IndoorGrZones_m_Boff
+0x002A0F7C,
+0x0F120010,
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12028E,	//awbb_OutdoorGrZones_m_BGrid[0]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[1]
+0x0F120276, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202B8,	//awbb_OutdoorGrZones_m_BGrid[3]
+0x0F120264,	//awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202BE,	//awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120252,	//awbb_OutdoorGrZones_m_BGrid[6]
+0x0F1202C0,	//awbb_OutdoorGrZones_m_BGrid[7]
+0x0F120244,	//awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202BC,	//awbb_OutdoorGrZones_m_BGrid[9]
+0x0F120234,	//awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202B2,	//awbb_OutdoorGrZones_m_BGrid[11]
+0x0F120228,	//awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202A6,	//awbb_OutdoorGrZones_m_BGrid[13]
+0x0F12021E,	//awbb_OutdoorGrZones_m_BGrid[14]
+0x0F12029C, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F120216,	//awbb_OutdoorGrZones_m_BGrid[16]
+0x0F12028A,	//awbb_OutdoorGrZones_m_BGrid[17]
+0x0F120216, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F120278,	//awbb_OutdoorGrZones_m_BGrid[19]
+0x0F120220,	//awbb_OutdoorGrZones_m_BGrid[20]
+0x0F12026A,	//awbb_OutdoorGrZones_m_BGrid[21]
+0x0F120232,	//awbb_OutdoorGrZones_m_BGrid[22]
+0x0F12024A,	//awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C,	//awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201E4,	//awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F1203B2, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F12044E, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F120330, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F120454, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120414, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F12026E, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1203D0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120226, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F120362, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201F0, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F120312, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201CE, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F1202CC, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F1201B2, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F12029E, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F1201AC, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F1201B6, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120248, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000A, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F1200C2, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+
+0x002A11A8,
+0x0F1202C8, //awbb_GridConst_1[0]
+0x0F120325, //awbb_GridConst_1[1]
+0x0F12038F, //awbb_GridConst_1[2]
+
+0x0F120F8E, //awbb_GridConst_2[0]
+0x0F1210B3, //awbb_GridConst_2[1]
+0x0F121136, //awbb_GridConst_2[2]
+0x0F121138, //awbb_GridConst_2[3]
+0x0F12118E, //awbb_GridConst_2[4]
+0x0F121213, //awbb_GridConst_2[5]
+
+0x0F1200A7, //awbb_GridCoeff_R_1
+0x0F1200C2, //awbb_GridCoeff_B_1
+0x0F1200BD, //awbb_GridCoeff_R_2
+0x0F1200AC, //awbb_GridCoeff_B_2
+
+0x002A1118,
+0x0F120050, //0032//awbb_GridCorr_R[0][0]
+0x0F120032, //0012//awbb_GridCorr_R[0][1]
+0x0F120032, //0012//awbb_GridCorr_R[0][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[0][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060, //0050//awbb_GridCorr_R[0][5]
+0x0F120050, //0032//awbb_GridCorr_R[1][0]
+0x0F120032, //0012//awbb_GridCorr_R[1][1]
+0x0F120032, //0012//awbb_GridCorr_R[1][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[1][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060, //0050//awbb_GridCorr_R[1][5]
+0x0F120050, //0032//awbb_GridCorr_R[2][0]
+0x0F120032, //0012//awbb_GridCorr_R[2][1]
+0x0F120032, //0012//awbb_GridCorr_R[2][2]
+0x0F120000, //FFEC//awbb_GridCorr_R[2][3]
+0x0F120000, //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060, //0050//awbb_GridCorr_R[2][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[0][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[0][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[0][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[0][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[0][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[0][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[1][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[1][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[1][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[1][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[1][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[1][5]
+0x0F12FF9C, //FF9C//awbb_GridCorr_B[2][0]
+0x0F12FFD8, //FFCE//awbb_GridCorr_B[2][1]
+0x0F12FFEC, //FFCE//awbb_GridCorr_B[2][2]
+0x0F12FF97, //FF97//awbb_GridCorr_B[2][3]
+0x0F12FF97, //FF97//awbb_GridCorr_B[2][4]
+0x0F12FE30, //FDA8//awbb_GridCorr_B[2][5]
+
+0x002A1160,
+0x0F12000A, //awbb_GridCorr_R_Out[0][0]
+0x0F12000A, //awbb_GridCorr_R_Out[0][1]
+0x0F120000, //awbb_GridCorr_R_Out[0][2]
+0x0F120000, //awbb_GridCorr_R_Out[0][3]
+0x0F120000, //awbb_GridCorr_R_Out[0][4]
+0x0F120000, //awbb_GridCorr_R_Out[0][5]
+0x0F12000A, //awbb_GridCorr_R_Out[1][0]
+0x0F12000A, //awbb_GridCorr_R_Out[1][1]
+0x0F120000, //awbb_GridCorr_R_Out[1][2]
+0x0F120000, //awbb_GridCorr_R_Out[1][3]
+0x0F120000, //awbb_GridCorr_R_Out[1][4]
+0x0F120000, //awbb_GridCorr_R_Out[1][5]
+0x0F12000A, //awbb_GridCorr_R_Out[2][0]
+0x0F12000A, //awbb_GridCorr_R_Out[2][1]
+0x0F120000, //awbb_GridCorr_R_Out[2][2]
+0x0F120000, //awbb_GridCorr_R_Out[2][3]
+0x0F120000, //awbb_GridCorr_R_Out[2][4]
+0x0F120000, //awbb_GridCorr_R_Out[2][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[0][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[0][1]
+0x0F120000, //awbb_GridCorr_B_Out[0][2]
+0x0F120000, //awbb_GridCorr_B_Out[0][3]
+0x0F120000, //awbb_GridCorr_B_Out[0][4]
+0x0F120000, //awbb_GridCorr_B_Out[0][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[1][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[1][1]
+0x0F120000, //awbb_GridCorr_B_Out[1][2]
+0x0F120000, //awbb_GridCorr_B_Out[1][3]
+0x0F120000, //awbb_GridCorr_B_Out[1][4]
+0x0F120000, //awbb_GridCorr_B_Out[1][5]
+0x0F12FFD2, //awbb_GridCorr_B_Out[2][0]
+0x0F12FFD2, //awbb_GridCorr_B_Out[2][1]
+0x0F120000, //awbb_GridCorr_B_Out[2][2]
+0x0F120000, //awbb_GridCorr_B_Out[2][3]
+0x0F120000, //awbb_GridCorr_B_Out[2][4]
+0x0F120000, //awbb_GridCorr_B_Out[2][5]
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[0] 
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[1] 
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[2] 
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[3] 
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[4] 
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[5] 
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[6] 
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[7] 
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[8] 
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[9] 
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[10]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[11]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[12]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[13]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[14]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[15]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[16]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[17]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[18]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[19]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[20]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[21]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[22]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[23]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[24]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[25]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[26]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[27]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[28]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[29]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[30]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[31]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[32]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[33]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[34]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[35]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[36]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[37]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[38]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[39]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[40]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[41]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[42]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[43]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[44]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[45]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[46]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[47]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[48]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[49]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[50]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[51]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[52]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[53]
+
+0x0F1201EA, //01E2//TVAR_wbt_pBaseCcms[54]
+0x0F12FFAC, //FF9A//TVAR_wbt_pBaseCcms[55]
+0x0F12FFE3, //FFE8//TVAR_wbt_pBaseCcms[56]
+0x0F12FF45, //FF45//TVAR_wbt_pBaseCcms[57]
+0x0F120140, //0140//TVAR_wbt_pBaseCcms[58]
+0x0F12FF4F, //FF4F//TVAR_wbt_pBaseCcms[59]
+0x0F12FFC3, //FFC3//TVAR_wbt_pBaseCcms[60]
+0x0F12FFD5, //FFD5//TVAR_wbt_pBaseCcms[61]
+0x0F120173, //0173//TVAR_wbt_pBaseCcms[62]
+0x0F120137, //0128//TVAR_wbt_pBaseCcms[63]
+0x0F1200C2, //00EA//TVAR_wbt_pBaseCcms[64]
+0x0F12FEC1, //FEA8//TVAR_wbt_pBaseCcms[65]
+0x0F1200C8, //00C8//TVAR_wbt_pBaseCcms[66]
+0x0F12FF49, //FF49//TVAR_wbt_pBaseCcms[67]
+0x0F12014B, //014B//TVAR_wbt_pBaseCcms[68]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[69]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[70]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[71]
+
+0x0F12011D, //00F4//TVAR_wbt_pBaseCcms[72]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[73]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[74]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[75]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[76]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[77]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[78]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[79]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[80]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[81]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[82]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[83]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[84]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[85]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[86]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[87]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[88]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[89]
+
+0x0F12011D, //00F4//TVAR_wbt_pBaseCcms[90]
+0x0F12FFA7, //FFC2//TVAR_wbt_pBaseCcms[91]
+0x0F12FFEC, //FFFA//TVAR_wbt_pBaseCcms[92]
+0x0F12FF0D, //FF3E//TVAR_wbt_pBaseCcms[93]
+0x0F120193, //0163//TVAR_wbt_pBaseCcms[94]
+0x0F12FF34, //FF5F//TVAR_wbt_pBaseCcms[95]
+0x0F12FFCE, //FFCE//TVAR_wbt_pBaseCcms[96]
+0x0F12FFDF, //FFDF//TVAR_wbt_pBaseCcms[97]
+0x0F12015E, //015E//TVAR_wbt_pBaseCcms[98]
+0x0F120095, //0095//TVAR_wbt_pBaseCcms[99]
+0x0F120096, //0096//TVAR_wbt_pBaseCcms[100]
+0x0F12FF0B, //FF0B//TVAR_wbt_pBaseCcms[101]
+0x0F1200C3, //00C3//TVAR_wbt_pBaseCcms[102]
+0x0F12FF5C, //FF5C//TVAR_wbt_pBaseCcms[103]
+0x0F12013D, //013D//TVAR_wbt_pBaseCcms[104]
+0x0F12FF68, //FF68//TVAR_wbt_pBaseCcms[105]
+0x0F120109, //0109//TVAR_wbt_pBaseCcms[106]
+0x0F1200F4, //00F4//TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201F6, //01F6//01F8//TVAR_wbt_pOutdoorCcm[0]
+0x0F12FF9F, //FF9F//FFAF//TVAR_wbt_pOutdoorCcm[1]
+0x0F12FFE5, //FFE5//FFD3//TVAR_wbt_pOutdoorCcm[2]
+0x0F12FED2, //FED2//FEC4//TVAR_wbt_pOutdoorCcm[3]
+0x0F120193, //0193//0191//TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF23, //FF23//FF33//TVAR_wbt_pOutdoorCcm[5]
+0x0F12FFF7, //FFF7//FFED//TVAR_wbt_pOutdoorCcm[6]
+0x0F12000C, //000C//0017//TVAR_wbt_pOutdoorCcm[7]
+0x0F120211, //0211//0210//TVAR_wbt_pOutdoorCcm[8]
+0x0F1200FF, //00F1//00E3//TVAR_wbt_pOutdoorCcm[9]
+0x0F1200EC, //00FA//0107//TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF2E, //FF2E//FF2F//TVAR_wbt_pOutdoorCcm[11]
+0x0F120220, //0220//0220//TVAR_wbt_pOutdoorCcm[12]
+0x0F12FFE7, //FFE7//FFE7//TVAR_wbt_pOutdoorCcm[13]
+0x0F1201A1, //01A1//01A1//TVAR_wbt_pOutdoorCcm[14]
+0x0F12FEC7, //FEC7//FEC8//TVAR_wbt_pOutdoorCcm[15]
+0x0F12016D, //016D//017D//TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153//0142//TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F12004A, //0049//#afit_uNoiseIndInDoor_0_
+0x0F12004E, //005F//#afit_uNoiseIndInDoor_1_
+0x0F1200CB, //00CB//#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0//#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220//#afit_uNoiseIndInDoor_4_
+
+0x002A08C0,
+0x0F120007, //0007//700008C0//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700008C2 //AFIT16_CONTRAST
+0x0F120000, //0000//700008C4 //AFIT16_SATURATION
+0x0F120002, //0000//700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //0000//700008C8 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700008CA //AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700008CC 
+0x0F1203FF, //03FF//700008CE //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700008D0 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700008D2 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700008D4 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700008D6 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700008D8 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700008DA //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700008DC //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700008DE //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700008E0 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700008E2 //AFIT16_demsharpmix1_iTune
+0x0F120010, //0010//700008E4//AFIT16_demsharpmix1_iHystThLow
+0x0F120010, //0010//700008E6//AFIT16_demsharpmix1_iHystThHigh
+0x0F1201F4, //01F4//700008E8//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C//700008EA//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008//700008EC//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700008EE//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700008F0//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700008F2//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700008F4//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700008F6//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//700008F8//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//700008FA//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//700008FC//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//700008FE//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000900//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000902//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000904//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205E8, //09E8//70000906//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000908//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//7000090A//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//7000090C//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F124000, //4000//7000090E
+0x0F127803, //7803//70000910
+0x0F123C50, //3C50//70000912
+0x0F12003C, //003C//70000914
+0x0F121E80, //1E80//70000916//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000918//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12000A, //000A//7000091A//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120000, //0000//7000091C//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F12120A, //120A//7000091E//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F121400, //0F00//70000920//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000922//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000924//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000926//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000928//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//7000092A//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//7000092C//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//7000092E//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000930//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000932
+0x0F120609, //0609//70000934
+0x0F122C07, //2C07//70000936
+0x0F12142C, //142C//70000938
+0x0F120B18, //0718//7000093A//[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F12800B, //8007//7000093C//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120880, //0880//7000093E//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120B50, //0B50//70000940//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000942//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000944//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000946//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124601, //4601//70000948//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F12A444, //C844//7000094A//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F1250A4, //50C8//7000094C//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//7000094E//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F120303, //0003//70000950//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F121001, //1C01//70000952//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120710, //0714//70000954//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121448, //1464//70000956//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F125A03, //5A04//70000958//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12281E, //3C1E//7000095A//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F12200F, //400F//7000095C//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//7000095E//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F121403, //1403//70000960//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F120114, //0114//70000962//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000964//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F124446, //4446//70000966//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F12646E, //646E//70000968//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//7000096A//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//7000096C//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120000, //0000//7000096E//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000970//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000972//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000974//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F120000, //0000//70000976//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000978//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//7000097A//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//7000097C//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F121414, //1414//7000097E//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000980//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F124601, //4601//70000982//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F126E44, //6E44//70000984//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122864, //2864//70000986//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000988//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F120003, //0003//7000098A//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E00, //1E00//7000098C//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//7000098E//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000990//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F120004, //0004//70000992//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F00, //0F00//70000994//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000996//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000998//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//7000099A//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//7000099C
+0x0F120000, //0000//7000099E//AFIT16_BRIGHTNESS
+0x0F120000, //0000//700009A0//AFIT16_CONTRAST
+0x0F120000, //0000//700009A2//AFIT16_SATURATION
+0x0F120002, //0000//700009A4//AFIT16_SHARP_BLUR
+0x0F120000, //0000//700009A6//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//700009A8//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//700009AA
+0x0F1203FF, //03FF//700009AC//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//700009AE//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//700009B0//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//700009B2//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//700009B4//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//700009B6//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//700009B8//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//700009BA//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//700009BC//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//700009BE//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//700009C0//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//700009C2//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//700009C4//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//700009C6//AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E//700009C8//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//700009CA//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//700009CC//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//700009CE//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//700009D0//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//700009D2//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//700009D4//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//700009D6//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//700009D8//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//700009DA//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//700009DC//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//700009DE//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//700009E0//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//700009E2//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205E8, //05E8//700009E4//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//700009E6//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//700009E8//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//700009EA//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000//700009EC
+0x0F125003, //5003//700009EE
+0x0F123228, //3228//700009F0
+0x0F120032, //0032//700009F2
+0x0F121E80, //1E80//700009F4//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//700009F6//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12000A, //000A//700009F8//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120000, //0000//700009FA//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F12120A, //120A//700009FC//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F121400, //1400//700009FE//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000A00//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000A02//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000A04//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000A06//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000A08//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000A0A//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000A0C//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000A0E//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000A10
+0x0F120609, //0609//70000A12
+0x0F122C07, //2C07//70000A14
+0x0F12142C, //142C//70000A16
+0x0F120518, //0518//70000A18//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000A1A//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120580, //0580//70000A1C//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000A1E//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000A20//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000A22//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000A24//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000A26//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F12494B, //444B 494B//70000A28//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_i
+0x0F125044, //503C 5044//70000A2A//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosa
+0x0F120500, //0500//70000A2C//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F120603, //0503//70000A2E//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D03, //0D02//70000A30//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F12071E, //071E//70000A32//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121432, //1432//70000A34//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F125A01, //5A01//70000A36//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12281E, //281E//70000A38//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F12200F, //200F//70000A3A//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000A3C//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F121E03, //1E03//70000A3E//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F12011E, //011E//70000A40//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000A42//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F123A3C, //3A3C//70000A44//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F12585A, //585A//70000A46//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000A48//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000A4A//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120000, //0000//70000A4C//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000A4E//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000A50//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000A52//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F120000, //0000//70000A54//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000A56//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000A58//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000A5A//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F121E1E, //1E1E//70000A5C//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000A5E//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F123C01, //3C01//70000A60//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F125A3A, //5A3A//70000A62//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122858, //2858//70000A64//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000A66//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F120003, //0003//70000A68//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E00, //1E00//70000A6A//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//70000A6C//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000A6E//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F120004, //0004//70000A70//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F00, //0F00//70000A72//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000A74//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000A76//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000A78//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000A7A
+0x0F120000, //0000//70000A7C//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000A7E//AFIT16_CONTRAST
+0x0F120000, //0000//70000A80//AFIT16_SATURATION
+0x0F120000, //0000//70000A82//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000A84//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000A86//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000A88
+0x0F1203FF, //03FF//70000A8A//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000A8C//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000A8E//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000A90//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000A92//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000A94//AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C//70000A96//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000A98//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000A9A//AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A//70000A9C//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000A9E//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000AA0//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000AA2//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000AA4//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000AA6//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000AA8//AFIT16_Sharpening_iHighSharpClamp
+0x0F12003C, //003C//70000AAA//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F12001E, //001E//70000AAC//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12003C, //003C//70000AAE//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F12001E, //001E//70000AB0//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000AB2//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//70000AB4//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//70000AB6//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//70000AB8//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//70000ABA//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000ABC//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000ABE//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000AC0//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205DE, //05DE//70000AC2//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000AC4//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//70000AC6//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//70000AC8//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000ACA
+0x0F122803, //2803//70000ACC
+0x0F12261E, //261E//70000ACE
+0x0F120026, //0026//70000AD0
+0x0F121E80, //1E80//70000AD2//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000AD4//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12010A, //010A//70000AD6//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120001, //0001//70000AD8//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F123C0A, //3C0A//70000ADA//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F122300, //2300//70000ADC//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000ADE//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000AE0//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000AE2//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121B11, //1B11//70000AE4//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000AE6//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000AE8//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000AEA//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120605, //0605//70000AEC//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120307, //0307//70000AEE
+0x0F120609, //0609//70000AF0
+0x0F121C07, //1C07//70000AF2
+0x0F121014, //1014//70000AF4
+0x0F120510, //0510//70000AF6//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000AF8//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000AFA//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000AFC//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000AFE//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000B00//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000B02//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000B04//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F122A4B, //2A4B//70000B06//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F125020, //5020//70000B08//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//70000B0A//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F121C03, //1C03//70000B0C//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D0C, //0D0C//70000B0E//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120823, //0823//70000B10//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121428, //1428//70000B12//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F126401, //6401//70000B14//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12282D, //282D//70000B16//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F122012, //2012//70000B18//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000B1A//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F122803, //2803//70000B1C//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F120128, //0128//70000B1E//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000B20//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F122224, //2224//70000B22//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F123236, //3236//70000B24//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000B26//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000B28//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120410, //0410//70000B2A//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F12141E, //141E//70000B2C//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF07, //FF07//70000B2E//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000B30//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F124050, //4050//70000B32//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F120F0F, //0F0F//70000B34//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000B36//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000B38//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F122828, //2828//70000B3A//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000B3C//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F122401, //2401//70000B3E//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F123622, //3622//70000B40//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F122832, //2832//70000B42//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000B44//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F121003, //1003//70000B46//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121E04, //1E04//70000B48//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F120714, //0714//70000B4A//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000B4C//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F125004, //5004//70000B4E//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120F40, //0F40//70000B50//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F12400F, //400F//70000B52//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000B54//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000B56//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000B58
+0x0F120000, //0000//70000B5A//AFIT16_BRIGHTNESS
+0x0F120000, //0000//70000B5C//AFIT16_CONTRAST
+0x0F120000, //0000//70000B5E//AFIT16_SATURATION
+0x0F120000, //0000//70000B60//AFIT16_SHARP_BLUR
+0x0F120000, //0000//70000B62//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//70000B64//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//70000B66
+0x0F1203FF, //03FF//70000B68//AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E//70000B6A//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C//70000B6C//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//70000B6E//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//70000B70//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//70000B72//AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8//70000B74//AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8//70000B76//AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046//70000B78//AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050//70000B7A//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//70000B7C//AFIT16_demsharpmix1_iTune
+0x0F120001, //0001//70000B7E//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//70000B80//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//70000B82//AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C//70000B84//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//70000B86//AFIT16_Sharpening_iHighSharpClamp
+0x0F12002D, //002D//70000B88//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//70000B8A//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12002D, //002D//70000B8C//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//70000B8E//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//70000B90//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh
+0x0F121701, //1701//70000B92//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level
+0x0F120229, //0229//70000B94//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8
+0x0F121403, //1403//70000B96//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAl
+0x0F120004, //0004//70000B98//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotTh
+0x0F120300, //0300//70000B9A//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iCold
+0x0F120000, //0000//70000B9C//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoi
+0x0F1202FF, //02FF//70000B9E//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [
+0x0F1205DE, //05DE//70000BA0//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadial
+0x0F121414, //1414//70000BA2//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_
+0x0F120301, //0301//70000BA4//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHigh
+0x0F120007, //0007//70000BA6//AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000//70000BA8
+0x0F122303, //2303//70000BAA
+0x0F12231A, //231A//70000BAC
+0x0F120023, //0023//70000BAE
+0x0F121E80, //1E80//70000BB0//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_i
+0x0F121E08, //1E08//70000BB2//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosai
+0x0F12010A, //010A//70000BB4//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_
+0x0F120001, //0001//70000BB6//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaici
+0x0F123C0A, //3C0A//70000BB8//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpe
+0x0F122300, //2300//70000BBA//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iW
+0x0F120200, //0200//70000BBC//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nS
+0x0F12FF00, //FF00//70000BBE//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpeni
+0x0F120200, //0200//70000BC0//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demshar
+0x0F121E10, //1E10//70000BC2//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_i
+0x0F120000, //0000//70000BC4//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1
+0x0F120009, //0009//70000BC6//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpm
+0x0F120406, //0406//70000BC8//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix
+0x0F120705, //0705//70000BCA//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharp
+0x0F120306, //0306//70000BCC
+0x0F120509, //0509//70000BCE
+0x0F122806, //2806//70000BD0
+0x0F121428, //1428//70000BD2
+0x0F120518, //0518//70000BD4//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005//70000BD6//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080//70000BD8//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iD
+0x0F120080, //0080//70000BDA//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYO
+0x0F120080, //0080//70000BDC//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSatura
+0x0F120101, //0101//70000BDE//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClu
+0x0F120707, //0707//70000BE0//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClus
+0x0F124B01, //4B01//70000BE2//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_Disp
+0x0F122A4B, //2A4B//70000BE4//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenTh
+0x0F125020, //5020//70000BE6//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing
+0x0F120500, //0500//70000BE8//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Dem
+0x0F121C03, //1C03//70000BEA//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosa
+0x0F120D0C, //0D0C//70000BEC//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demos
+0x0F120823, //0823//70000BEE//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demos
+0x0F121428, //1428//70000BF0//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaici
+0x0F126401, //6401//70000BF2//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpen
+0x0F12282D, //282D//70000BF4//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpe
+0x0F122012, //2012//70000BF6//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpe
+0x0F120204, //0204//70000BF8//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsh
+0x0F123C03, //3C03//70000BFA//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd
+0x0F12013C, //013C//70000BFC//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000BFE//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_n
+0x0F121C1E, //1C1E//70000C00//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_Dis
+0x0F121E22, //1E22//70000C02//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_
+0x0F120028, //0028//70000C04//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosa
+0x0F12030A, //030A//70000C06//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8
+0x0F120214, //0214//70000C08//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_De
+0x0F120E14, //0E14//70000C0A//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_D
+0x0F12FF06, //FF06//70000C0C//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  A
+0x0F120432, //0432//70000C0E//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demo
+0x0F124052, //4052//70000C10//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sha
+0x0F12150C, //150C//70000C12//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Shar
+0x0F120440, //0440//70000C14//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8
+0x0F120302, //0302//70000C16//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_
+0x0F123C3C, //3C3C//70000C18//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a
+0x0F120101, //0101//70000C1A//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_
+0x0F121E01, //1E01//70000C1C//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a
+0x0F12221C, //221C//70000C1E//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_i
+0x0F12281E, //281E//70000C20//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosa
+0x0F120A00, //0A00//70000C22//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8
+0x0F121403, //1403//70000C24//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_
+0x0F121402, //1402//70000C26//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_
+0x0F12060E, //060E//70000C28//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_D
+0x0F1232FF, //32FF//70000C2A//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demo
+0x0F125204, //5204//70000C2C//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sh
+0x0F120C40, //0C40//70000C2E//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_S
+0x0F124015, //4015//70000C30//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sh
+0x0F120204, //0204//70000C32//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_
+0x0F120003, //0003//70000C34//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//70000C36
+0x0F120003, //0000//0000//70000C38//AFIT16_BRIGHTNESS
+0x0F120000, //0000//0000//70000C3A//AFIT16_CONTRAST
+0x0F120000, //0000//0000//70000C3C//AFIT16_SATURATION
+0x0F120000, //0000//0000//70000C3E//AFIT16_SHARP_BLUR
+0x0F120000, //0000//0000//70000C40//AFIT16_GLAMOUR
+0x0F1200C1, //00C1//00C1//70000C42//AFIT16_sddd8a_edge_high
+0x0F120000, //0000//0000//70000C44
+0x0F1203FF, //03FF//03FF//70000C46//AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C//0008//70000C48//AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251//017C//70000C4A//AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF//03FF//70000C4C//AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C//000C//70000C4E//AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010//0010//70000C50//AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032//0032//70000C52//AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A//028A//70000C54//AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032//0032//70000C56//AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4//01F4//70000C58//AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070//0070//70000C5A//AFIT16_demsharpmix1_iTune
+0x0F120002, //0002//0002//70000C5C//AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000//0000//70000C5E//AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320//0320//70000C60//AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044//0070//70000C62//AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014//0014//70000C64//AFIT16_Sharpening_iHighSharpClamp
+0x0F120046, //0046//0046//70000C66//AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120019, //0019//0019//70000C68//AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120046, //0046//0046//70000C6A//AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120019, //0019//0019//70000C6C//AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24//0A24//70000C6E//AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:
+0x0F121701, //1701//1701//70000C70//AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:
+0x0F120229, //0229//0229//70000C72//AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503//0503//70000C74//AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed
+0x0F12080F, //080F//0101//70000C76//AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshL
+0x0F120808, //0808//0101//70000C78//AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThres
+0x0F120000, //0000//0000//70000C7A//AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePow
+0x0F1200FF, //00FF//02FF//70000C7C//AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D//0396//70000C7E//AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower
+0x0F121414, //1414//1414//70000C80//AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHigh
+0x0F120301, //0301//0301//70000C82//AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlope
+0x0F120007, //0007//0007//70000C84//AFIT8_sddd8a_iSquaresRounding [7:0]                      
+0x0F121000, //1000//1000//70000C86        
+0x0F122003, //2003//2003//70000C88        
+0x0F121020, //1020//1020//70000C8A        
+0x0F120010, //0010//0010//70000C8C        
+0x0F121EFF, //1EFF//1E80//70000C8E//AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonoc
+0x0F121E06, //1E06//1E06//70000C90//AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_
+0x0F12060A, //060A//030C//70000C92//AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDe
+0x0F120306, //0306//0103//70000C94//AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iN
+0x0F128B0A, //8B0A//5A0A//70000C96//AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_
+0x0F122837, //2837//2D00//70000C98//AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharp
+0x0F120110, //0110//0100//70000C9A//AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpW
+0x0F12FF00, //FF00//FF00//70000C9C//AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iS
+0x0F120200, //0200//0200//70000C9E//AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1
+0x0F121E10, //1E10//1E10//70000CA0//AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoef
+0x0F120000, //0000//0000//70000CA2//AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNar
+0x0F120009, //0009//0009//70000CA4//AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_i
+0x0F120406, //0406//0406//70000CA6//AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHy
+0x0F120705, //0705//0705//70000CA8//AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_
+0x0F120305, //0305//0305//70000CAA        
+0x0F120609, //0609//0609//70000CAC        
+0x0F122C07, //2C07//2C07//70000CAE        
+0x0F12142C, //142C//142C//70000CB0        
+0x0F120B18, //0B18//0B18//70000CB2//[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F12800B, //800B//800B//70000CB4//[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]  
+0x0F120080, //0080//0080//70000CB6//AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkRe
+0x0F120080, //0080//0080//70000CB8//AFIT8_ccm_oscar_iSaturation[7:0]   AFIT8_RGB2YUV_iYOffset
+0x0F120080, //0080//0080//70000CBA//AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation 
+0x0F125050, //5050//0101//70000CBC//AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThr
+0x0F120101, //0101//0A0A//70000CBE//AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT
+0x0F123201, //3201//3201//70000CC0//AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Lo
+0x0F121832, //1832//1428//70000CC2//AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshL
+0x0F12210C, //210C//100C//70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdg
+0x0F120A00, //0A00//0500//70000CC6//AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaic
+0x0F121E04, //1E04//1E02//70000CC8//AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing
+0x0F120A08, //0A08//040C//70000CCA//AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicin
+0x0F12070C, //070C//0828//70000CCC//AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicin
+0x0F123264, //3264//5064//70000CCE//AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iD
+0x0F125A02, //5A02//4605//70000CD0//AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_i
+0x0F121040, //1040//1E68//70000CD2//AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_
+0x0F124012, //4012//201E//70000CD4//AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_
+0x0F120604, //0604//0604//70000CD6//AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmi
+0x0F124606, //4606//4606//70000CD8//AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iC
+0x0F120146, //0146//0146//70000CDA//AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClu
+0x0F120101, //0101//0101//70000CDC//AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClust
+0x0F121C18, //1C18//1C18//70000CDE//AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_H
+0x0F121819, //1819//1819//70000CE0//AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenT
+0x0F120028, //0028//0028//70000CE2//AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing
+0x0F12030A, //030A//030A//70000CE4//AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demo
+0x0F120514, //0514//0514//70000CE6//AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosai
+0x0F120C14, //0C14//0C14//70000CE8//AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosa
+0x0F12FF05, //FF05//FF05//70000CEA//AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_
+0x0F120432, //0432//0432//70000CEC//AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaici
+0x0F124052, //4052//4052//70000CEE//AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpeni
+0x0F121514, //1514//1514//70000CF0//AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpenin
+0x0F120440, //0440//0440//70000CF2//AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Shar
+0x0F120302, //0302//0302//70000CF4//AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsh
+0x0F124646, //4646//4646//70000CF6//AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClu
+0x0F120101, //0101//0101//70000CF8//AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClus
+0x0F121801, //1801//1801//70000CFA//AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_Disp
+0x0F12191C, //191C//191C//70000CFC//AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenTh
+0x0F122818, //2818//2818//70000CFE//AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing
+0x0F120A00, //0A00//0A00//70000D00//AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demo
+0x0F121403, //1403//1403//70000D02//AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demos
+0x0F121405, //1405//1405//70000D04//AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demos
+0x0F12050C, //050C//050C//70000D06//AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosa
+0x0F1232FF, //32FF//32FF//70000D08//AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaici
+0x0F125204, //5204//5204//70000D0A//AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpen
+0x0F121440, //1440//1440//70000D0C//AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpe
+0x0F124015, //4015//4015//70000D0E//AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpen
+0x0F120204, //0204//0204//70000D10//AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsh
+0x0F120003, //0003//0003//70000D12//AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001//0001//70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F122102, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+};
+
+static const u32 s5k5ccgx_hd_init_reg[] = {
+//****************************************/
+0xFCFCD000,
+//****************************************/
+//===================================================================
+// History
+//===================================================================
+//20100717 : 1st release
+//20100806 : 2nd release for EVT0.1
+//20101028 : 3rd release for EVT1
+//WRITE #awbb_otp_disable  0000                            //awb otp use
+//==========================================================================================
+//-->The below registers are for FACTORY ONLY. if you change them without prior notification
+//   YOU are RESPONSIBLE for the FAILURE that will happen in the future.
+//==========================================================================================
+//===================================================================
+// Reset & Trap and Patch
+//===================================================================
+
+// Start of Trap and Patch
+//  2010-08-11 13:53:35
+0x00100001,
+0x10300000,
+0x00140001,
+
+0xFFFF000A, //p10
+// Start of Patch data
+/*++ Add ESD */
+0x00287000,
+0x002A0150,
+0x0F12AAAA,
+/*-- Add ESD */
+0x00287000,
+0x002A352C,
+0x0F12B570, //7000352C 
+0x0F124A24, //7000352E 
+0x0F124924, //70003530 
+0x0F124825, //70003532 
+0x0F124B25, //70003534 
+0x0F122500, //70003536 
+0x0F12801D, //70003538 
+0x0F12C004, //7000353A 
+0x0F126001, //7000353C 
+0x0F124924, //7000353E 
+0x0F124824, //70003540 
+0x0F12F000, //70003542 
+0x0F12FBBD, //70003544 
+0x0F124924, //70003546 
+0x0F124824, //70003548 
+0x0F12F000, //7000354A 
+0x0F12FBB9, //7000354C 
+0x0F124824, //7000354E 
+0x0F124E24, //70003550 
+0x0F126430, //70003552 
+0x0F124924, //70003554 
+0x0F124825, //70003556 
+0x0F12F000, //70003558 
+0x0F12FBB2, //7000355A 
+0x0F124924, //7000355C 
+0x0F120030, //7000355E 
+0x0F123080, //70003560 
+0x0F126141, //70003562 
+0x0F124C23, //70003564 
+0x0F128365, //70003566 
+0x0F124923, //70003568 
+0x0F124824, //7000356A 
+0x0F12F000, //7000356C 
+0x0F12FBA8, //7000356E 
+0x0F124923, //70003570 
+0x0F124824, //70003572 
+0x0F12F000, //70003574 
+0x0F12FBA4, //70003576 
+0x0F124923, //70003578 
+0x0F124824, //7000357A 
+0x0F12F000, //7000357C 
+0x0F12FBA0, //7000357E 
+0x0F124923, //70003580 
+0x0F124824, //70003582 
+0x0F12F000, //70003584 
+0x0F12FB9C, //70003586 
+0x0F128125, //70003588 
+0x0F124923, //7000358A 
+0x0F124823, //7000358C 
+0x0F12F000, //7000358E 
+0x0F12FB97, //70003590 
+0x0F124923, //70003592 
+0x0F124823, //70003594 
+0x0F12F000, //70003596 
+0x0F12FB93, //70003598 
+0x0F1283A5, //7000359A 
+0x0F124922, //7000359C 
+0x0F124823, //7000359E 
+0x0F12F000, //700035A0 
+0x0F12FB8E, //700035A2 
+0x0F122101, //700035A4 
+0x0F120349, //700035A6 
+0x0F120020, //700035A8 
+0x0F123020, //700035AA 
+0x0F128041, //700035AC 
+0x0F122185, //700035AE 
+0x0F128081, //700035B0 
+0x0F12491F, //700035B2 
+0x0F1280C1, //700035B4 
+0x0F12481F, //700035B6 
+0x0F126730, //700035B8 
+0x0F12BC70, //700035BA 
+0x0F12BC08, //700035BC 
+0x0F124718, //700035BE 
+0x0F1200CA, //700035C0 
+0x0F125CC1, //700035C2 
+0x0F1203BD, //700035C4 
+0x0F120000, //700035C6 
+0x0F121C08, //700035C8 
+0x0F127000, //700035CA 
+0x0F123290, //700035CC 
+0x0F127000, //700035CE 
+0x0F123657, //700035D0 
+0x0F127000, //700035D2 
+0x0F12D9E7, //700035D4 
+0x0F120000, //700035D6 
+0x0F12383F, //700035D8 
+0x0F127000, //700035DA 
+0x0F12395D, //700035DC 
+0x0F120000, //700035DE 
+0x0F1238D1, //700035E0 
+0x0F127000, //700035E2 
+0x0F120000, //700035E4 
+0x0F127000, //700035E6 
+0x0F12399D, //700035E8 
+0x0F127000, //700035EA 
+0x0F12F903, //700035EC 
+0x0F120000, //700035EE 
+0x0F123AC1, //700035F0 
+0x0F127000, //700035F2 
+0x0F123FC8, //700035F4 
+0x0F127000, //700035F6 
+0x0F12368F, //700035F8 
+0x0F127000, //700035FA 
+0x0F12495F, //700035FC 
+0x0F120000, //700035FE 
+0x0F1236ED, //70003600 
+0x0F127000, //70003602 
+0x0F12E421, //70003604 
+0x0F120000, //70003606 
+0x0F1237AB, //70003608 
+0x0F127000, //7000360A 
+0x0F12216D, //7000360C 
+0x0F120000, //7000360E 
+0x0F12381F, //70003610 
+0x0F127000, //70003612 
+0x0F120179, //70003614 
+0x0F120001, //70003616 
+0x0F123BD5, //70003618 
+0x0F127000, //7000361A 
+0x0F1204C9, //7000361C 
+0x0F120000, //7000361E 
+0x0F123B25, //70003620 
+0x0F127000, //70003622 
+0x0F125027, //70003624 
+0x0F120000, //70003626 
+0x0F123BE1, //70003628 
+0x0F127000, //7000362A 
+0x0F1242B7, //7000362C 
+0x0F120000, //7000362E 
+0x0F1207FF, //70003630 
+0x0F120000, //70003632 
+0x0F123C5F, //70003634 
+0x0F127000, //70003636 
+0x0F12B570, //70003638 
+0x0F12000D, //7000363A 
+0x0F124CFC, //7000363C 
+0x0F128821, //7000363E 
+0x0F12F000, //70003640 
+0x0F12FB46, //70003642 
+0x0F128820, //70003644 
+0x0F124AFB, //70003646 
+0x0F120081, //70003648 
+0x0F125055, //7000364A 
+0x0F121C40, //7000364C 
+0x0F128020, //7000364E 
+0x0F12BC70, //70003650 
+0x0F12BC08, //70003652 
+0x0F124718, //70003654 
+0x0F126801, //70003656 
+0x0F120409, //70003658 
+0x0F120C09, //7000365A 
+0x0F126840, //7000365C 
+0x0F120400, //7000365E 
+0x0F120C00, //70003660 
+0x0F124AF5, //70003662 
+0x0F128992, //70003664 
+0x0F122A00, //70003666 
+0x0F12D00D, //70003668 
+0x0F122300, //7000366A 
+0x0F121A80, //7000366C 
+0x0F12D400, //7000366E 
+0x0F120003, //70003670 
+0x0F120418, //70003672 
+0x0F120C00, //70003674 
+0x0F124BF1, //70003676 
+0x0F121851, //70003678 
+0x0F12891B, //7000367A 
+0x0F12428B, //7000367C 
+0x0F12D300, //7000367E 
+0x0F12000B, //70003680 
+0x0F120419, //70003682 
+0x0F120C09, //70003684 
+0x0F124AEE, //70003686 
+0x0F128151, //70003688 
+0x0F128190, //7000368A 
+0x0F124770, //7000368C 
+0x0F12B510, //7000368E 
+0x0F124CEC, //70003690 
+0x0F1248ED, //70003692 
+0x0F1278A1, //70003694 
+0x0F122900, //70003696 
+0x0F12D101, //70003698 
+0x0F1287C1, //7000369A 
+0x0F12E004, //7000369C 
+0x0F127AE1, //7000369E 
+0x0F122900, //700036A0 
+0x0F12D001, //700036A2 
+0x0F122101, //700036A4 
+0x0F1287C1, //700036A6 
+0x0F12F000, //700036A8 
+0x0F12FB1A, //700036AA 
+0x0F1249E7, //700036AC 
+0x0F128B08, //700036AE 
+0x0F1206C2, //700036B0 
+0x0F12D50A, //700036B2 
+0x0F127AA2, //700036B4 
+0x0F120652, //700036B6 
+0x0F12D507, //700036B8 
+0x0F122210, //700036BA 
+0x0F124390, //700036BC 
+0x0F128308, //700036BE 
+0x0F1248E3, //700036C0 
+0x0F127AE1, //700036C2 
+0x0F126B00, //700036C4 
+0x0F12F000, //700036C6 
+0x0F12FB13, //700036C8 
+0x0F1248DB, //700036CA 
+0x0F1289C0, //700036CC 
+0x0F122801, //700036CE 
+0x0F12D109, //700036D0 
+0x0F1278A0, //700036D2 
+0x0F122800, //700036D4 
+0x0F12D006, //700036D6 
+0x0F127AE0, //700036D8 
+0x0F122800, //700036DA 
+0x0F12D003, //700036DC 
+0x0F127AA0, //700036DE 
+0x0F122140, //700036E0 
+0x0F124308, //700036E2 
+0x0F1272A0, //700036E4 
+0x0F12BC10, //700036E6 
+0x0F12BC08, //700036E8 
+0x0F124718, //700036EA 
+0x0F12B570, //700036EC 
+0x0F124DD7, //700036EE 
+0x0F124CD7, //700036F0 
+0x0F128B28, //700036F2 
+0x0F120701, //700036F4 
+0x0F12D507, //700036F6 
+0x0F122108, //700036F8 
+0x0F124388, //700036FA 
+0x0F128328, //700036FC 
+0x0F1249D5, //700036FE 
+0x0F126B20, //70003700 
+0x0F126B89, //70003702 
+0x0F12F000, //70003704 
+0x0F12FAFC, //70003706 
+0x0F128B28, //70003708 
+0x0F1206C1, //7000370A 
+0x0F12D5A0, //7000370C 
+0x0F1249CD, //7000370E 
+0x0F127A8A, //70003710 
+0x0F120652, //70003712 
+0x0F12D49C, //70003714 
+0x0F122210, //70003716 
+0x0F124390, //70003718 
+0x0F128328, //7000371A 
+0x0F127AC9, //7000371C 
+0x0F126B20, //7000371E 
+0x0F12F000, //70003720 
+0x0F12FAE6, //70003722 
+0x0F12E794, //70003724 
+0x0F12B5F8, //70003726 
+0x0F1249CB, //70003728 
+0x0F128F08, //7000372A 
+0x0F12000C, //7000372C 
+0x0F123480, //7000372E 
+0x0F122800, //70003730 
+0x0F12D000, //70003732 
+0x0F128360, //70003734 
+0x0F122000, //70003736 
+0x0F128708, //70003738 
+0x0F124DC8, //7000373A 
+0x0F1226FF, //7000373C 
+0x0F128828, //7000373E 
+0x0F121C76, //70003740 
+0x0F122702, //70003742 
+0x0F122803, //70003744 
+0x0F12D112, //70003746 
+0x0F128868, //70003748 
+0x0F122800, //7000374A 
+0x0F12D10F, //7000374C 
+0x0F1288E8, //7000374E 
+0x0F122800, //70003750 
+0x0F12D10C, //70003752 
+0x0F12F000, //70003754 
+0x0F12FADC, //70003756 
+0x0F122800, //70003758 
+0x0F12D008, //7000375A 
+0x0F128B60, //7000375C 
+0x0F122800, //7000375E 
+0x0F12D001, //70003760 
+0x0F1280EE, //70003762 
+0x0F1280AF, //70003764 
+0x0F122001, //70003766 
+0x0F127268, //70003768 
+0x0F12F000, //7000376A 
+0x0F12FAD9, //7000376C 
+0x0F128828, //7000376E 
+0x0F122802, //70003770 
+0x0F12D10E, //70003772 
+0x0F128868, //70003774 
+0x0F122800, //70003776 
+0x0F12D10B, //70003778 
+0x0F1288E8, //7000377A 
+0x0F122800, //7000377C 
+0x0F12D108, //7000377E 
+0x0F128B60, //70003780 
+0x0F122800, //70003782 
+0x0F12D001, //70003784 
+0x0F1280EE, //70003786 
+0x0F1280AF, //70003788 
+0x0F122001, //7000378A 
+0x0F127268, //7000378C 
+0x0F12F000, //7000378E 
+0x0F12FAC7, //70003790 
+0x0F1288E8, //70003792 
+0x0F122800, //70003794 
+0x0F12D006, //70003796 
+0x0F121FC1, //70003798 
+0x0F1239FD, //7000379A 
+0x0F12D003, //7000379C 
+0x0F122001, //7000379E 
+0x0F12BCF8, //700037A0 
+0x0F12BC08, //700037A2 
+0x0F124718, //700037A4 
+0x0F122000, //700037A6 
+0x0F12E7FA, //700037A8 
+0x0F12B570, //700037AA 
+0x0F124CAC, //700037AC 
+0x0F128860, //700037AE 
+0x0F122800, //700037B0 
+0x0F12D00C, //700037B2 
+0x0F128820, //700037B4 
+0x0F124DA3, //700037B6 
+0x0F122800, //700037B8 
+0x0F12D009, //700037BA 
+0x0F120029, //700037BC 
+0x0F1231A0, //700037BE 
+0x0F127AC9, //700037C0 
+0x0F122900, //700037C2 
+0x0F12D004, //700037C4 
+0x0F127AA8, //700037C6 
+0x0F122180, //700037C8 
+0x0F124308, //700037CA 
+0x0F1272A8, //700037CC 
+0x0F12E73F, //700037CE 
+0x0F122800, //700037D0 
+0x0F12D003, //700037D2 
+0x0F12F7FF, //700037D4 
+0x0F12FFA7, //700037D6 
+0x0F122800, //700037D8 
+0x0F12D1F8, //700037DA 
+0x0F122000, //700037DC 
+0x0F128060, //700037DE 
+0x0F128820, //700037E0 
+0x0F122800, //700037E2 
+0x0F12D003, //700037E4 
+0x0F122008, //700037E6 
+0x0F12F000, //700037E8 
+0x0F12FAA2, //700037EA 
+0x0F12E00B, //700037EC 
+0x0F12489C, //700037EE 
+0x0F123020, //700037F0 
+0x0F128880, //700037F2 
+0x0F122800, //700037F4 
+0x0F12D103, //700037F6 
+0x0F127AA8, //700037F8 
+0x0F122101, //700037FA 
+0x0F124308, //700037FC 
+0x0F1272A8, //700037FE 
+0x0F122010, //70003800 
+0x0F12F000, //70003802 
+0x0F12FA95, //70003804 
+0x0F128820, //70003806 
+0x0F122800, //70003808 
+0x0F12D1E0, //7000380A 
+0x0F12488A, //7000380C 
+0x0F1289C0, //7000380E 
+0x0F122801, //70003810 
+0x0F12D1DC, //70003812 
+0x0F127AA8, //70003814 
+0x0F1221BF, //70003816 
+0x0F124008, //70003818 
+0x0F1272A8, //7000381A 
+0x0F12E718, //7000381C 
+0x0F126800, //7000381E 
+0x0F124990, //70003820 
+0x0F128188, //70003822 
+0x0F124890, //70003824 
+0x0F122201, //70003826 
+0x0F128981, //70003828 
+0x0F124890, //7000382A 
+0x0F120252, //7000382C 
+0x0F124291, //7000382E 
+0x0F12D902, //70003830 
+0x0F122102, //70003832 
+0x0F128181, //70003834 
+0x0F124770, //70003836 
+0x0F122101, //70003838 
+0x0F128181, //7000383A 
+0x0F124770, //7000383C 
+0x0F12B5F1, //7000383E 
+0x0F124E80, //70003840 
+0x0F128834, //70003842 
+0x0F122C00, //70003844 
+0x0F12D03F, //70003846 
+0x0F122001, //70003848 
+0x0F122C08, //7000384A 
+0x0F12D000, //7000384C 
+0x0F122000, //7000384E 
+0x0F1270B0, //70003850 
+0x0F124D7F, //70003852 
+0x0F122800, //70003854 
+0x0F12D009, //70003856 
+0x0F12F000, //70003858 
+0x0F12FA72, //7000385A 
+0x0F120028, //7000385C 
+0x0F1238F0, //7000385E 
+0x0F126328, //70003860 
+0x0F127AB0, //70003862 
+0x0F12217E, //70003864 
+0x0F124008, //70003866 
+0x0F1272B0, //70003868 
+0x0F12E00F, //7000386A 
+0x0F124F7A, //7000386C 
+0x0F123780, //7000386E 
+0x0F128B78, //70003870 
+0x0F122800, //70003872 
+0x0F12D005, //70003874 
+0x0F12F000, //70003876 
+0x0F12FA6B, //70003878 
+0x0F122000, //7000387A 
+0x0F128378, //7000387C 
+0x0F124976, //7000387E 
+0x0F128708, //70003880 
+0x0F122000, //70003882 
+0x0F12F000, //70003884 
+0x0F12FA6C, //70003886 
+0x0F124879, //70003888 
+0x0F126328, //7000388A 
+0x0F1278B1, //7000388C 
+0x0F122700, //7000388E 
+0x0F120038, //70003890 
+0x0F122900, //70003892 
+0x0F12D008, //70003894 
+0x0F124972, //70003896 
+0x0F123920, //70003898 
+0x0F128ACA, //7000389A 
+0x0F122A00, //7000389C 
+0x0F12D003, //7000389E 
+0x0F128B09, //700038A0 
+0x0F122900, //700038A2 
+0x0F12D000, //700038A4 
+0x0F122001, //700038A6 
+0x0F127170, //700038A8 
+0x0F122C02, //700038AA 
+0x0F12D102, //700038AC 
+0x0F124868, //700038AE 
+0x0F123860, //700038B0 
+0x0F126328, //700038B2 
+0x0F122201, //700038B4 
+0x0F122C02, //700038B6 
+0x0F12D000, //700038B8 
+0x0F122200, //700038BA 
+0x0F124861, //700038BC 
+0x0F122110, //700038BE 
+0x0F12300A, //700038C0 
+0x0F12F000, //700038C2 
+0x0F12FA55, //700038C4 
+0x0F128037, //700038C6 
+0x0F129900, //700038C8 
+0x0F120020, //700038CA 
+0x0F12600C, //700038CC 
+0x0F12E767, //700038CE 
+0x0F12B538, //700038D0 
+0x0F124865, //700038D2 
+0x0F124669, //700038D4 
+0x0F123848, //700038D6 
+0x0F12F000, //700038D8 
+0x0F12FA52, //700038DA 
+0x0F124A5E, //700038DC 
+0x0F124862, //700038DE 
+0x0F128F51, //700038E0 
+0x0F122400, //700038E2 
+0x0F123020, //700038E4 
+0x0F122900, //700038E6 
+0x0F12D00A, //700038E8 
+0x0F128754, //700038EA 
+0x0F126941, //700038EC 
+0x0F126451, //700038EE 
+0x0F126491, //700038F0 
+0x0F12466B, //700038F2 
+0x0F128819, //700038F4 
+0x0F1287D1, //700038F6 
+0x0F12885B, //700038F8 
+0x0F120011, //700038FA 
+0x0F123140, //700038FC 
+0x0F12800B, //700038FE 
+0x0F128F91, //70003900 
+0x0F122900, //70003902 
+0x0F12D002, //70003904 
+0x0F128794, //70003906 
+0x0F126940, //70003908 
+0x0F126490, //7000390A 
+0x0F12F000, //7000390C 
+0x0F12FA40, //7000390E 
+0x0F12BC38, //70003910 
+0x0F12BC08, //70003912 
+0x0F124718, //70003914 
+0x0F12B5F8, //70003916 
+0x0F124C56, //70003918 
+0x0F1289E0, //7000391A 
+0x0F12F000, //7000391C 
+0x0F12FA40, //7000391E 
+0x0F120006, //70003920 
+0x0F128A20, //70003922 
+0x0F12F000, //70003924 
+0x0F12FA44, //70003926 
+0x0F120007, //70003928 
+0x0F12484F, //7000392A 
+0x0F124D4A, //7000392C 
+0x0F123020, //7000392E 
+0x0F126CA9, //70003930 
+0x0F126940, //70003932 
+0x0F121809, //70003934 
+0x0F120200, //70003936 
+0x0F12F000, //70003938 
+0x0F12FA42, //7000393A 
+0x0F120400, //7000393C 
+0x0F120C00, //7000393E 
+0x0F12002A, //70003940 
+0x0F12326E, //70003942 
+0x0F120011, //70003944 
+0x0F12390A, //70003946 
+0x0F122305, //70003948 
+0x0F12F000, //7000394A 
+0x0F12FA3F, //7000394C 
+0x0F124C43, //7000394E 
+0x0F1261A0, //70003950 
+0x0F128FEB, //70003952 
+0x0F120002, //70003954 
+0x0F120031, //70003956 
+0x0F120018, //70003958 
+0x0F12F000, //7000395A 
+0x0F12FA3F, //7000395C 
+0x0F12466B, //7000395E 
+0x0F120005, //70003960 
+0x0F128018, //70003962 
+0x0F12483C, //70003964 
+0x0F1269A2, //70003966 
+0x0F123040, //70003968 
+0x0F128800, //7000396A 
+0x0F120039, //7000396C 
+0x0F12F000, //7000396E 
+0x0F12FA35, //70003970 
+0x0F12466B, //70003972 
+0x0F120006, //70003974 
+0x0F128058, //70003976 
+0x0F120021, //70003978 
+0x0F129800, //7000397A 
+0x0F12311C, //7000397C 
+0x0F12F000, //7000397E 
+0x0F12FA35, //70003980 
+0x0F124935, //70003982 
+0x0F123180, //70003984 
+0x0F12808D, //70003986 
+0x0F1280CE, //70003988 
+0x0F128BA1, //7000398A 
+0x0F124836, //7000398C 
+0x0F123820, //7000398E 
+0x0F128001, //70003990 
+0x0F128BE1, //70003992 
+0x0F128041, //70003994 
+0x0F128C21, //70003996 
+0x0F128081, //70003998 
+0x0F12E701, //7000399A 
+0x0F12B5F8, //7000399C 
+0x0F124E2E, //7000399E 
+0x0F126C70, //700039A0 
+0x0F126CB1, //700039A2 
+0x0F120200, //700039A4 
+0x0F12F000, //700039A6 
+0x0F12FA0B, //700039A8 
+0x0F120400, //700039AA 
+0x0F120C00, //700039AC 
+0x0F122401, //700039AE 
+0x0F120364, //700039B0 
+0x0F1242A0, //700039B2 
+0x0F12D200, //700039B4 
+0x0F120004, //700039B6 
+0x0F124A27, //700039B8 
+0x0F120020, //700039BA 
+0x0F12327E, //700039BC 
+0x0F121F91, //700039BE 
+0x0F122303, //700039C0 
+0x0F12F000, //700039C2 
+0x0F12FA03, //700039C4 
+0x0F120405, //700039C6 
+0x0F120C2D, //700039C8 
+0x0F124A23, //700039CA 
+0x0F120020, //700039CC 
+0x0F12325A, //700039CE 
+0x0F120011, //700039D0 
+0x0F12390A, //700039D2 
+0x0F122305, //700039D4 
+0x0F12F000, //700039D6 
+0x0F12F9F9, //700039D8 
+0x0F12491F, //700039DA 
+0x0F1264C8, //700039DC 
+0x0F12491F, //700039DE 
+0x0F124E21, //700039E0 
+0x0F1288C8, //700039E2 
+0x0F122701, //700039E4 
+0x0F122800, //700039E6 
+0x0F12D009, //700039E8 
+0x0F124C23, //700039EA 
+0x0F1238FF, //700039EC 
+0x0F121E40, //700039EE 
+0x0F12D00A, //700039F0 
+0x0F122804, //700039F2 
+0x0F12D042, //700039F4 
+0x0F122806, //700039F6 
+0x0F12D101, //700039F8 
+0x0F122000, //700039FA 
+0x0F1280C8, //700039FC 
+0x0F1282B7, //700039FE 
+0x0F122001, //70003A00 
+0x0F12F000, //70003A02 
+0x0F12F9FB, //70003A04 
+0x0F12E6CB, //70003A06 
+0x0F12000D, //70003A08 
+0x0F12724F, //70003A0A 
+0x0F122001, //70003A0C 
+0x0F12F000, //70003A0E 
+0x0F12F9FD, //70003A10 
+0x0F12F000, //70003A12 
+0x0F12FA03, //70003A14 
+0x0F124910, //70003A16 
+0x0F123148, //70003A18 
+0x0F12C903, //70003A1A 
+0x0F124348, //70003A1C 
+0x0F120A00, //70003A1E 
+0x0F126160, //70003A20 
+0x0F1220FF, //70003A22 
+0x0F121D40, //70003A24 
+0x0F1280E8, //70003A26 
+0x0F12480C, //70003A28 
+0x0F123040, //70003A2A 
+0x0F127707, //70003A2C 
+0x0F12E7E6, //70003A2E 
+0x0F123290, //70003A30 
+0x0F127000, //70003A32 
+0x0F123294, //70003A34 
+0x0F127000, //70003A36 
+0x0F1204A8, //70003A38 
+0x0F127000, //70003A3A 
+0x0F1215DC, //70003A3C 
+0x0F127000, //70003A3E 
+0x0F125000, //70003A40 
+0x0F12D000, //70003A42 
+0x0F121E84, //70003A44 
+0x0F127000, //70003A46 
+0x0F121BE4, //70003A48 
+0x0F127000, //70003A4A 
+0x0F122EA8, //70003A4C 
+0x0F127000, //70003A4E 
+0x0F1221A4, //70003A50 
+0x0F127000, //70003A52 
+0x0F120100, //70003A54 
+0x0F127000, //70003A56 
+0x0F123F48, //70003A58 
+0x0F127000, //70003A5A 
+0x0F1231A0, //70003A5C 
+0x0F127000, //70003A5E 
+0x0F1201E8, //70003A60 
+0x0F127000, //70003A62 
+0x0F12F2A0, //70003A64 
+0x0F12D000, //70003A66 
+0x0F122A44, //70003A68 
+0x0F127000, //70003A6A 
+0x0F12F400, //70003A6C 
+0x0F12D000, //70003A6E 
+0x0F122024, //70003A70 
+0x0F127000, //70003A72 
+0x0F121650, //70003A74 
+0x0F127000, //70003A76 
+0x0F122A64, //70003A78 
+0x0F127000, //70003A7A 
+0x0F124982, //70003A7C 
+0x0F12724F, //70003A7E 
+0x0F1220FF, //70003A80 
+0x0F121DC0, //70003A82 
+0x0F1280C8, //70003A84 
+0x0F12F000, //70003A86 
+0x0F12F9D1, //70003A88 
+0x0F124980, //70003A8A 
+0x0F126ACA, //70003A8C 
+0x0F12604A, //70003A8E 
+0x0F122800, //70003A90 
+0x0F12D006, //70003A92 
+0x0F12436A, //70003A94 
+0x0F120001, //70003A96 
+0x0F120010, //70003A98 
+0x0F12F000, //70003A9A 
+0x0F12F991, //70003A9C 
+0x0F126160, //70003A9E 
+0x0F12E001, //70003AA0 
+0x0F12436A, //70003AA2 
+0x0F126162, //70003AA4 
+0x0F128BF0, //70003AA6 
+0x0F122800, //70003AA8 
+0x0F12D001, //70003AAA 
+0x0F12F7FF, //70003AAC 
+0x0F12FF33, //70003AAE 
+0x0F122000, //70003AB0 
+0x0F12F000, //70003AB2 
+0x0F12F9AB, //70003AB4 
+0x0F124974, //70003AB6 
+0x0F1220FF, //70003AB8 
+0x0F121DC0, //70003ABA 
+0x0F1280C8, //70003ABC 
+0x0F12E79E, //70003ABE 
+0x0F12B510, //70003AC0 
+0x0F12F000, //70003AC2 
+0x0F12F9BB, //70003AC4 
+0x0F124870, //70003AC6 
+0x0F1288C0, //70003AC8 
+0x0F121FC1, //70003ACA 
+0x0F1239FD, //70003ACC 
+0x0F12D103, //70003ACE 
+0x0F12496F, //70003AD0 
+0x0F1220FF, //70003AD2 
+0x0F121C40, //70003AD4 
+0x0F128048, //70003AD6 
+0x0F12E605, //70003AD8 
+0x0F12B5F8, //70003ADA 
+0x0F122400, //70003ADC 
+0x0F124D6D, //70003ADE 
+0x0F12486D, //70003AE0 
+0x0F12210E, //70003AE2 
+0x0F128041, //70003AE4 
+0x0F122101, //70003AE6 
+0x0F128001, //70003AE8 
+0x0F12F000, //70003AEA 
+0x0F12F9AF, //70003AEC 
+0x0F12486B, //70003AEE 
+0x0F128840, //70003AF0 
+0x0F12F000, //70003AF2 
+0x0F12F9B3, //70003AF4 
+0x0F124E6A, //70003AF6 
+0x0F12270D, //70003AF8 
+0x0F12073F, //70003AFA 
+0x0F1219E8, //70003AFC 
+0x0F128803, //70003AFE 
+0x0F1200E2, //70003B00 
+0x0F121991, //70003B02 
+0x0F12804B, //70003B04 
+0x0F128843, //70003B06 
+0x0F1252B3, //70003B08 
+0x0F128882, //70003B0A 
+0x0F1280CA, //70003B0C 
+0x0F1288C0, //70003B0E 
+0x0F128088, //70003B10 
+0x0F123508, //70003B12 
+0x0F12042D, //70003B14 
+0x0F120C2D, //70003B16 
+0x0F121C64, //70003B18 
+0x0F120424, //70003B1A 
+0x0F120C24, //70003B1C 
+0x0F122C07, //70003B1E 
+0x0F12D3EC, //70003B20 
+0x0F12E63D, //70003B22 
+0x0F12B5F0, //70003B24 
+0x0F12B085, //70003B26 
+0x0F126801, //70003B28 
+0x0F129103, //70003B2A 
+0x0F126881, //70003B2C 
+0x0F12040A, //70003B2E 
+0x0F120C12, //70003B30 
+0x0F12495C, //70003B32 
+0x0F128B89, //70003B34 
+0x0F122900, //70003B36 
+0x0F12D001, //70003B38 
+0x0F120011, //70003B3A 
+0x0F12E000, //70003B3C 
+0x0F122100, //70003B3E 
+0x0F129102, //70003B40 
+0x0F126840, //70003B42 
+0x0F120401, //70003B44 
+0x0F129803, //70003B46 
+0x0F120C09, //70003B48 
+0x0F12F000, //70003B4A 
+0x0F12F98F, //70003B4C 
+0x0F124854, //70003B4E 
+0x0F123080, //70003B50 
+0x0F128900, //70003B52 
+0x0F122800, //70003B54 
+0x0F12D039, //70003B56 
+0x0F122100, //70003B58 
+0x0F124854, //70003B5A 
+0x0F124D52, //70003B5C 
+0x0F124684, //70003B5E 
+0x0F124B53, //70003B60 
+0x0F124C4F, //70003B62 
+0x0F1288DA, //70003B64 
+0x0F120048, //70003B66 
+0x0F1200D7, //70003B68 
+0x0F12193E, //70003B6A 
+0x0F12197F, //70003B6C 
+0x0F12183F, //70003B6E 
+0x0F125A36, //70003B70 
+0x0F128AFF, //70003B72 
+0x0F12437E, //70003B74 
+0x0F1200B6, //70003B76 
+0x0F120C37, //70003B78 
+0x0F121906, //70003B7A 
+0x0F123680, //70003B7C 
+0x0F128177, //70003B7E 
+0x0F121C52, //70003B80 
+0x0F1200D2, //70003B82 
+0x0F121914, //70003B84 
+0x0F121952, //70003B86 
+0x0F121812, //70003B88 
+0x0F125A24, //70003B8A 
+0x0F128AD2, //70003B8C 
+0x0F124354, //70003B8E 
+0x0F1200A2, //70003B90 
+0x0F120C12, //70003B92 
+0x0F128272, //70003B94 
+0x0F12891C, //70003B96 
+0x0F12895B, //70003B98 
+0x0F124367, //70003B9A 
+0x0F12435A, //70003B9C 
+0x0F121943, //70003B9E 
+0x0F123340, //70003BA0 
+0x0F1289DB, //70003BA2 
+0x0F129C02, //70003BA4 
+0x0F1218BA, //70003BA6 
+0x0F124363, //70003BA8 
+0x0F1218D2, //70003BAA 
+0x0F120212, //70003BAC 
+0x0F120C12, //70003BAE 
+0x0F12466B, //70003BB0 
+0x0F12521A, //70003BB2 
+0x0F124663, //70003BB4 
+0x0F127DDB, //70003BB6 
+0x0F12435A, //70003BB8 
+0x0F129B03, //70003BBA 
+0x0F120252, //70003BBC 
+0x0F120C12, //70003BBE 
+0x0F12521A, //70003BC0 
+0x0F121C49, //70003BC2 
+0x0F120409, //70003BC4 
+0x0F120C09, //70003BC6 
+0x0F122904, //70003BC8 
+0x0F12D3C9, //70003BCA 
+0x0F12B005, //70003BCC 
+0x0F12BCF0, //70003BCE 
+0x0F12BC08, //70003BD0 
+0x0F124718, //70003BD2 
+0x0F12B510, //70003BD4 
+0x0F12F7FF, //70003BD6 
+0x0F12FF80, //70003BD8 
+0x0F12F000, //70003BDA 
+0x0F12F94F, //70003BDC 
+0x0F12E582, //70003BDE 
+0x0F12B570, //70003BE0 
+0x0F126804, //70003BE2 
+0x0F12F000, //70003BE4 
+0x0F12F952, //70003BE6 
+0x0F124D32, //70003BE8 
+0x0F128C29, //70003BEA 
+0x0F121A40, //70003BEC 
+0x0F1242A0, //70003BEE 
+0x0F12D901, //70003BF0 
+0x0F120020, //70003BF2 
+0x0F12E003, //70003BF4 
+0x0F12F000, //70003BF6 
+0x0F12F949, //70003BF8 
+0x0F128C29, //70003BFA 
+0x0F121A40, //70003BFC 
+0x0F126268, //70003BFE 
+0x0F12F000, //70003C00 
+0x0F12F94C, //70003C02 
+0x0F1262A8, //70003C04 
+0x0F12F000, //70003C06 
+0x0F12F951, //70003C08 
+0x0F126328, //70003C0A 
+0x0F128869, //70003C0C 
+0x0F122900, //70003C0E 
+0x0F12D000, //70003C10 
+0x0F1262A8, //70003C12 
+0x0F124828, //70003C14 
+0x0F126B00, //70003C16 
+0x0F128C00, //70003C18 
+0x0F122800, //70003C1A 
+0x0F12D11B, //70003C1C 
+0x0F126AA8, //70003C1E 
+0x0F12F000, //70003C20 
+0x0F12F94C, //70003C22 
+0x0F1261E8, //70003C24 
+0x0F124A1E, //70003C26 
+0x0F123280, //70003C28 
+0x0F128B91, //70003C2A 
+0x0F122900, //70003C2C 
+0x0F12D00B, //70003C2E 
+0x0F120011, //70003C30 
+0x0F123120, //70003C32 
+0x0F128809, //70003C34 
+0x0F124288, //70003C36 
+0x0F12D907, //70003C38 
+0x0F1261E9, //70003C3A 
+0x0F128C28, //70003C3C 
+0x0F121A08, //70003C3E 
+0x0F1262A8, //70003C40 
+0x0F12F000, //70003C42 
+0x0F12F92B, //70003C44 
+0x0F1262A8, //70003C46 
+0x0F12E502, //70003C48 
+0x0F128BD1, //70003C4A 
+0x0F124288, //70003C4C 
+0x0F12D800, //70003C4E 
+0x0F120008, //70003C50 
+0x0F1261E8, //70003C52 
+0x0F12E4FC, //70003C54 
+0x0F12F000, //70003C56 
+0x0F12F919, //70003C58 
+0x0F1261E8, //70003C5A 
+0x0F12E4F8, //70003C5C 
+0x0F12B510, //70003C5E 
+0x0F12F000, //70003C60 
+0x0F12F934, //70003C62 
+0x0F12480E, //70003C64 
+0x0F1230A0, //70003C66 
+0x0F128841, //70003C68 
+0x0F122900, //70003C6A 
+0x0F12D007, //70003C6C 
+0x0F124A07, //70003C6E 
+0x0F123280, //70003C70 
+0x0F126953, //70003C72 
+0x0F124A11, //70003C74 
+0x0F12428B, //70003C76 
+0x0F12D202, //70003C78 
+0x0F128880, //70003C7A 
+0x0F1281D0, //70003C7C 
+0x0F12E532, //70003C7E 
+0x0F1288C0, //70003C80 
+0x0F1281D0, //70003C82 
+0x0F12E52F, //70003C84 
+0x0F120000, //70003C86 
+0x0F1231A0, //70003C88 
+0x0F127000, //70003C8A 
+0x0F1229E4, //70003C8C 
+0x0F127000, //70003C8E 
+0x0F12C100, //70003C90 
+0x0F12D000, //70003C92 
+0x0F12A006, //70003C94 
+0x0F120000, //70003C96 
+0x0F12A000, //70003C98 
+0x0F12D000, //70003C9A 
+0x0F12064C, //70003C9C 
+0x0F127000, //70003C9E 
+0x0F123F48, //70003CA0 
+0x0F127000, //70003CA2 
+0x0F1207C4, //70003CA4 
+0x0F127000, //70003CA6 
+0x0F1207E8, //70003CA8 
+0x0F127000, //70003CAA 
+0x0F122B24, //70003CAC 
+0x0F127000, //70003CAE 
+0x0F121FA0, //70003CB0 
+0x0F127000, //70003CB2 
+0x0F121E3C, //70003CB4 
+0x0F127000, //70003CB6 
+0x0F1221A4, //70003CB8 
+0x0F127000, //70003CBA 
+0x0F12E200, //70003CBC 
+0x0F12D000, //70003CBE 
+0x0F124778, //70003CC0 
+0x0F1246C0, //70003CC2 
+0x0F12C000, //70003CC4 
+0x0F12E59F, //70003CC6 
+0x0F12FF1C, //70003CC8 
+0x0F12E12F, //70003CCA 
+0x0F121F63, //70003CCC 
+0x0F120001, //70003CCE 
+0x0F124778, //70003CD0 
+0x0F1246C0, //70003CD2 
+0x0F12C000, //70003CD4 
+0x0F12E59F, //70003CD6 
+0x0F12FF1C, //70003CD8 
+0x0F12E12F, //70003CDA 
+0x0F121EDF, //70003CDC 
+0x0F120001, //70003CDE 
+0x0F124778, //70003CE0 
+0x0F1246C0, //70003CE2 
+0x0F12C000, //70003CE4 
+0x0F12E59F, //70003CE6 
+0x0F12FF1C, //70003CE8 
+0x0F12E12F, //70003CEA 
+0x0F12495F, //70003CEC 
+0x0F120000, //70003CEE 
+0x0F124778, //70003CF0 
+0x0F1246C0, //70003CF2 
+0x0F12C000, //70003CF4 
+0x0F12E59F, //70003CF6 
+0x0F12FF1C, //70003CF8 
+0x0F12E12F, //70003CFA 
+0x0F12E403, //70003CFC 
+0x0F120000, //70003CFE 
+0x0F124778, //70003D00 
+0x0F1246C0, //70003D02 
+0x0F12C000, //70003D04 
+0x0F12E59F, //70003D06 
+0x0F12FF1C, //70003D08 
+0x0F12E12F, //70003D0A 
+0x0F1224B3, //70003D0C 
+0x0F120001, //70003D0E 
+0x0F124778, //70003D10 
+0x0F1246C0, //70003D12 
+0x0F12C000, //70003D14 
+0x0F12E59F, //70003D16 
+0x0F12FF1C, //70003D18 
+0x0F12E12F, //70003D1A 
+0x0F12EECD, //70003D1C 
+0x0F120000, //70003D1E 
+0x0F124778, //70003D20 
+0x0F1246C0, //70003D22 
+0x0F12C000, //70003D24 
+0x0F12E59F, //70003D26 
+0x0F12FF1C, //70003D28 
+0x0F12E12F, //70003D2A 
+0x0F12F049, //70003D2C 
+0x0F120000, //70003D2E 
+0x0F124778, //70003D30 
+0x0F1246C0, //70003D32 
+0x0F12C000, //70003D34 
+0x0F12E59F, //70003D36 
+0x0F12FF1C, //70003D38 
+0x0F12E12F, //70003D3A 
+0x0F1212DF, //70003D3C 
+0x0F120000, //70003D3E 
+0x0F124778, //70003D40 
+0x0F1246C0, //70003D42 
+0x0F12C000, //70003D44 
+0x0F12E59F, //70003D46 
+0x0F12FF1C, //70003D48 
+0x0F12E12F, //70003D4A 
+0x0F12F05B, //70003D4C 
+0x0F120000, //70003D4E 
+0x0F124778, //70003D50 
+0x0F1246C0, //70003D52 
+0x0F12C000, //70003D54 
+0x0F12E59F, //70003D56 
+0x0F12FF1C, //70003D58 
+0x0F12E12F, //70003D5A 
+0x0F12F07B, //70003D5C 
+0x0F120000, //70003D5E 
+0x0F124778, //70003D60 
+0x0F1246C0, //70003D62 
+0x0F12C000, //70003D64 
+0x0F12E59F, //70003D66 
+0x0F12FF1C, //70003D68 
+0x0F12E12F, //70003D6A 
+0x0F12FE6D, //70003D6C 
+0x0F120000, //70003D6E 
+0x0F124778, //70003D70 
+0x0F1246C0, //70003D72 
+0x0F12C000, //70003D74 
+0x0F12E59F, //70003D76 
+0x0F12FF1C, //70003D78 
+0x0F12E12F, //70003D7A 
+0x0F123295, //70003D7C 
+0x0F120000, //70003D7E 
+0x0F124778, //70003D80 
+0x0F1246C0, //70003D82 
+0x0F12C000, //70003D84 
+0x0F12E59F, //70003D86 
+0x0F12FF1C, //70003D88 
+0x0F12E12F, //70003D8A 
+0x0F12234F, //70003D8C 
+0x0F120000, //70003D8E 
+0x0F124778, //70003D90 
+0x0F1246C0, //70003D92 
+0x0F12C000, //70003D94 
+0x0F12E59F, //70003D96 
+0x0F12FF1C, //70003D98 
+0x0F12E12F, //70003D9A 
+0x0F124521, //70003D9C 
+0x0F120000, //70003D9E 
+0x0F124778, //70003DA0 
+0x0F1246C0, //70003DA2 
+0x0F12C000, //70003DA4 
+0x0F12E59F, //70003DA6 
+0x0F12FF1C, //70003DA8 
+0x0F12E12F, //70003DAA 
+0x0F127C0D, //70003DAC 
+0x0F120000, //70003DAE 
+0x0F124778, //70003DB0 
+0x0F1246C0, //70003DB2 
+0x0F12C000, //70003DB4 
+0x0F12E59F, //70003DB6 
+0x0F12FF1C, //70003DB8 
+0x0F12E12F, //70003DBA 
+0x0F127C2B, //70003DBC 
+0x0F120000, //70003DBE 
+0x0F124778, //70003DC0 
+0x0F1246C0, //70003DC2 
+0x0F12F004, //70003DC4 
+0x0F12E51F, //70003DC6 
+0x0F1224C4, //70003DC8 
+0x0F120001, //70003DCA 
+0x0F124778, //70003DCC 
+0x0F1246C0, //70003DCE 
+0x0F12C000, //70003DD0 
+0x0F12E59F, //70003DD2 
+0x0F12FF1C, //70003DD4 
+0x0F12E12F, //70003DD6 
+0x0F123183, //70003DD8 
+0x0F120000, //70003DDA 
+0x0F124778, //70003DDC 
+0x0F1246C0, //70003DDE 
+0x0F12C000, //70003DE0 
+0x0F12E59F, //70003DE2 
+0x0F12FF1C, //70003DE4 
+0x0F12E12F, //70003DE6 
+0x0F12302F, //70003DE8 
+0x0F120000, //70003DEA 
+0x0F124778, //70003DEC 
+0x0F1246C0, //70003DEE 
+0x0F12C000, //70003DF0 
+0x0F12E59F, //70003DF2 
+0x0F12FF1C, //70003DF4 
+0x0F12E12F, //70003DF6 
+0x0F12EF07, //70003DF8 
+0x0F120000, //70003DFA 
+0x0F124778, //70003DFC 
+0x0F1246C0, //70003DFE 
+0x0F12C000, //70003E00 
+0x0F12E59F, //70003E02 
+0x0F12FF1C, //70003E04 
+0x0F12E12F, //70003E06 
+0x0F1248FB, //70003E08 
+0x0F120000, //70003E0A 
+0x0F124778, //70003E0C 
+0x0F1246C0, //70003E0E 
+0x0F12C000, //70003E10 
+0x0F12E59F, //70003E12 
+0x0F12FF1C, //70003E14 
+0x0F12E12F, //70003E16 
+0x0F12F0B1, //70003E18 
+0x0F120000, //70003E1A 
+0x0F124778, //70003E1C 
+0x0F1246C0, //70003E1E 
+0x0F12C000, //70003E20 
+0x0F12E59F, //70003E22 
+0x0F12FF1C, //70003E24 
+0x0F12E12F, //70003E26 
+0x0F12EEDF, //70003E28 
+0x0F120000, //70003E2A 
+0x0F124778, //70003E2C 
+0x0F1246C0, //70003E2E 
+0x0F12C000, //70003E30 
+0x0F12E59F, //70003E32 
+0x0F12FF1C, //70003E34 
+0x0F12E12F, //70003E36 
+0x0F12AEF1, //70003E38 
+0x0F120000, //70003E3A 
+0x0F124778, //70003E3C 
+0x0F1246C0, //70003E3E 
+0x0F12C000, //70003E40 
+0x0F12E59F, //70003E42 
+0x0F12FF1C, //70003E44 
+0x0F12E12F, //70003E46 
+0x0F1202EB, //70003E48 
+0x0F120001, //70003E4A 
+0x0F124778, //70003E4C 
+0x0F1246C0, //70003E4E 
+0x0F12C000, //70003E50 
+0x0F12E59F, //70003E52 
+0x0F12FF1C, //70003E54 
+0x0F12E12F, //70003E56 
+0x0F12FD21, //70003E58 
+0x0F120000, //70003E5A 
+0x0F124778, //70003E5C 
+0x0F1246C0, //70003E5E 
+0x0F12C000, //70003E60 
+0x0F12E59F, //70003E62 
+0x0F12FF1C, //70003E64 
+0x0F12E12F, //70003E66 
+0x0F12FDAF, //70003E68 
+0x0F120000, //70003E6A 
+0x0F124778, //70003E6C 
+0x0F1246C0, //70003E6E 
+0x0F12C000, //70003E70 
+0x0F12E59F, //70003E72 
+0x0F12FF1C, //70003E74 
+0x0F12E12F, //70003E76 
+0x0F125027, //70003E78 
+0x0F120000, //70003E7A 
+0x0F124778, //70003E7C 
+0x0F1246C0, //70003E7E 
+0x0F12C000, //70003E80 
+0x0F12E59F, //70003E82 
+0x0F12FF1C, //70003E84 
+0x0F12E12F, //70003E86 
+0x0F1204C9, //70003E88 
+0x0F120000, //70003E8A 
+0x0F124778, //70003E8C 
+0x0F1246C0, //70003E8E 
+0x0F12C000, //70003E90 
+0x0F12E59F, //70003E92 
+0x0F12FF1C, //70003E94 
+0x0F12E12F, //70003E96 
+0x0F1239DF, //70003E98 
+0x0F120000, //70003E9A 
+0x0F124778, //70003E9C 
+0x0F1246C0, //70003E9E 
+0x0F12C000, //70003EA0 
+0x0F12E59F, //70003EA2 
+0x0F12FF1C, //70003EA4 
+0x0F12E12F, //70003EA6 
+0x0F126177, //70003EA8 
+0x0F120000, //70003EAA 
+0x0F124778, //70003EAC 
+0x0F1246C0, //70003EAE 
+0x0F12C000, //70003EB0 
+0x0F12E59F, //70003EB2 
+0x0F12FF1C, //70003EB4 
+0x0F12E12F, //70003EB6 
+0x0F12424F, //70003EB8 
+0x0F120000, //70003EBA 
+0x0F124778, //70003EBC 
+0x0F1246C0, //70003EBE 
+0x0F12C000, //70003EC0 
+0x0F12E59F, //70003EC2 
+0x0F12FF1C, //70003EC4 
+0x0F12E12F, //70003EC6 
+0x0F123F0D, //70003EC8 
+0x0F120000, //70003ECA 
+0x0F124778, //70003ECC 
+0x0F1246C0, //70003ECE 
+0x0F12C000, //70003ED0 
+0x0F12E59F, //70003ED2 
+0x0F12FF1C, //70003ED4 
+0x0F12E12F, //70003ED6 
+0x0F1202B9, //70003ED8 
+0x0F120001, //70003EDA 
+// End of Patch Data(Last : 70003EDAh)
+// Total Size 2480 (09B0)
+// Addr : 352C , Size : 2478(9AEh) 
+
+//	TNP_USER_MBCV_CONTROL	
+//	TNP_FLS_SEC_CONFIG
+//	TNP_SINGLE_FRAME_CAPTURE
+//	TNP_CAPTURE_DONE_INFO
+//	TNP_5CC_SENSOR_TUNE		
+// 	TNP_GAS_ALPHA_OTP		
+// 	TNP_FR_ACCURATE_DYNAMIC	
+// 	TNP_ADLC_TUNE			
+
+0x10000001,
+
+0x0028D000,
+0x002A0070,
+0x0F120007, // clks_src_gf_force_enable
+
+
+//MBCV Control
+0x00287000,
+0x002A04B4,
+0x0F120064,
+
+// AFIT by Normalized Brightness Tuning parameter
+0x00287000,
+0x002A3302,
+0x0F120001, // on/off AFIT by NB option
+
+0x0F120005, //0005// NormBR[0]
+0x0F120066, //00C8// NormBR[1]
+0x0F1200C8, //00F4// NormBR[2]
+0x0F120320, //0320// NormBR[3]
+0x0F120375, //0375// NormBR[4]
+
+
+
+// Flash
+0x002A3F82,
+0x0F120000,// TNP_Regs_PreflashStart
+0x0F120000,// TNP_Regs_PreflashEnd
+0x0F120260,// TNP_Regs_PreWP_r
+0x0F120240, // TNP_Regs_PreWP_b
+
+0x002A3F98,	// BR Tuning
+0x0F120100,	// TNP_Regs_BrRatioIn_0_
+0x0F120180,
+0x0F120200,
+0x0F120300,
+0x0F120400,
+
+0x0F120080, /* TNP_Regs_BrRatioOut_0_ */
+0x0F120050,
+0x0F120040,
+0x0F120030,
+0x0F120020,
+
+0x0F120030,	// WP Tuning
+0x0F120040,	// TNP_Regs_WPThresTbl_0_
+0x0F120048,
+0x0F120050,
+0x0F120060,
+
+0x0F120100,	// TNP_Regs_WPWeightTbl_0_
+0x0F1200C0,
+0x0F120080,
+0x0F12000A,
+0x0F120000,
+
+0x0F120120,	// T_BR tune	
+0x0F120150,	// TNP_Regs_FlBRIn_0_
+0x0F120200,
+
+0x0F12003C,	//TNP_Regs_FlBRInOut_0_
+0x0F12003B,
+0x0F12002C,
+
+0x002A0430,	//REG_TC_FLS_Mode
+0x0F120002,	
+0x002A3F80,	//TNP_Regs_FastFlashAlg
+0x0F120000,
+
+0x002A165E,
+0x0F120240, //0244 0258 AWB R point //0258 0245 0258
+0x0F120244, //024D 0220 AWB B point //0220 0245 0245
+
+
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// Analog & APS settings                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+// This register is for FACTORY ONLY. If you change it without prior notification                           //
+// YOU are RESPONSIBLE for the FAILURE that will happen in the future                           //                           //                           //                           //                           //                           //                           //
+//                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           //                           ///
+
+//========================================================================================
+// 5CC EVT0 analog register setting
+// '10.07.14. Initial Draft
+// '10.07.24. sE404=0000 -> 1FC0 (Depedestal 0 -> -64d)
+// '10.08.16. sF410=0001 -> 0000 (for SHBN)
+// '10.08.25. sF438=0020 -> 0002 (VTGSL=2.96V) by APS
+//            sF43A=0020 -> 0001 (VRG=2.83V) by APS
+// '10.09.28. sF402=1F02 -> 3F02 ([13]: pixel bias powerdown according to HADR) for Darkshading
+//		    sF416=0000 -> 0001 (AAC_EN enable) for Darkshading
+//========================================================================================
+//============================= Analog & APS Control =====================================
+0x0028D000,
+0x002AF2AC,
+0x0F120100, // analog gain; 0200 x16 0100 x8 0080 x4 0040 x2 0020 x1
+0x002AF400,
+0x0F12001D, // ldb_en[4] ld_en[3] clp_en[2](N/A) smp_en[1] dshut_en[0]
+0x0F123F02, // cds_test[15:0]; refer to the ATOP_TEST_INFORMATION.
+
+0x002AF40A,
+0x0F120054, // adc_sat[7:0]=84d (500mV)
+0x0F120002, // ms[2:0]; 2h@Normal 2h@PLA 1h@CNT.AVG
+0x0F120008, // rmp_option[7:0]; [3]SL_Low_PWR_SAVE On
+0x0F120000, // msoff_en; No MS if gain gain is lower than x2
+0x0F1200A4, // rmp_init[7:0]
+
+0x002AF416,
+0x0F120001, // dbs_option[11:4] dbs_mode[3:2] dbs_bist_en[1] aac_en[0]
+
+0x002AF41E,
+0x0F120065, // comp2_bias[7:4] comp1_bias[3:0]
+
+0x002AF422,
+0x0F120005, // pix_bias[3:0]
+
+0x002AF426,
+0x0F1200D4, // clp_lvl[7:0]
+
+0x002AF42A,
+0x0F120001,// ref_option[7:0]; [4]OB_PIX monit en [3]Clamp monit en [2]Monit amp en [1]Clamp power-down [0]CDS power-down during SL=low
+
+0x002AF42E,
+0x0F120406,// fb_lv[11:10] pd_fblv[9] capa_ctrl_en[8] pd_inrush_ctrl[7] pd_reg_ntg[6] pd_reg_tgsl[5] pd_reg_rg[4] pd_reg_pix[3] pd_ncp_rosc[2] pd_cp_rosc[1] pd_cp[0]
+
+0x002AF434,
+0x0F120003, // dbr_clk_sel[1:0]; PLL_mode=3h ROSC_mode=0h
+0x0F120004, // reg_tune_pix[7:0]
+0x0F120002, // reg_tune_tgsl[7:0] (2.96V)
+0x0F120001, // reg_tune_rg[7:0] (2.83V)
+0x0F120004, // reg_tune_ntg[7:0]
+
+0x002AF446,
+0x0F120000, // blst_en_cintr[15:0]
+
+0x002AF466,
+0x0F120000, // srx_en[0]
+
+0x002A0054,
+0x0F120028, // pll_pd[10](0:enable 1:disable) div_clk_en[0](0:enable 1:disable)
+0x0F128888, // div_dbr[7:4]
+0x002AF132,
+0x0F124006,	//ki 0413// tgr_frame_decription 4
+0x002AF142,
+0x0F120000,	//ki 0413// tgr_frame_decription 4
+
+0x002AF152,
+0x0F120206, // tgr_frame_decription 7
+0x002AF1A2,
+0x0F120200, // tgr_frame_params_descriptor_3
+0x002AF1B2,
+0x0F120202, // tgr_frame_params_descriptor_6
+//==========================================================================================
+
+//============================= Line-ADLC Tuning ===========================================
+0x002AE412,
+0x0F120008, // adlc_tune_offset_gr[7:0]
+0x0F120008, // adlc_tune_offset_r[7:0]
+0x0F120010, // adlc_tune_offset_b[7:0]
+0x0F120010, // adlc_tune_offset_gb[7:0]
+0x002AE42E,
+0x0F120004, // adlc_qec[2:0]
+//==========================================================================================
+
+//===================================================================
+// AWB white locus setting - Have to be written after TnP
+//===================================================================
+0x00287000,
+0x002A1014,
+0x0F12012C,	//0132 //0138 //awbb_IntcR
+0x0F12010B,	//010A //011C //awbb_IntcB
+
+//===================================================================
+// AF
+//===================================================================
+//1. AF interface setting
+0x002A01A2,
+0x0F120003, //REG_TC_IPRM_CM_Init_AfModeType // VCM_I2C actuator
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig1// No PWM
+0x0F120000, //REG_TC_IPRM_CM_Init_PwmConfig2
+0x0F120041,                            //REG_TC_IPRM_CM_Init_GpioConfig1 // Use GPIO_4 for enable port
+0x0F120000, //REG_TC_IPRM_CM_Init_GpioConfig2
+0x0F122A0C,                            //REG_TC_IPRM_CM_Init_Mi2cBits // Use GPIO_5 for SCL GPIO_6 for SDA
+0x0F120190,                            //REG_TC_IPRM_CM_Init_Mi2cRateKhz // MI2C Speed : 400KHz
+
+//2. AF window setting
+0x002A022C,
+0x0F120100, //REG_TC_AF_FstWinStartX 
+0x0F1200E3, //REG_TC_AF_FstWinStartY
+0x0F120200, //REG_TC_AF_FstWinSizeX 
+0x0F120238, //REG_TC_AF_FstWinSizeY
+0x0F12018C, //REG_TC_AF_ScndWinStartX
+0x0F120166, //REG_TC_AF_ScndWinStartY
+0x0F1200E6, //REG_TC_AF_ScndWinSizeX
+0x0F120132, //REG_TC_AF_ScndWinSizeY
+0x0F120001, //REG_TC_AF_WinSizesUpdated
+
+//3. AF Fine Search Settings
+0x002A063A,
+0x0F1200C0, //#skl_af_StatOvlpExpFactor
+0x002A064A,
+0x0F120000, //0000 //#skl_af_bAfStatOff
+0x002A1488,
+0x0F120000, //#af_search_usAeStable
+0x002A1494,
+0x0F121000, //#af_search_usSingleAfFlags 1000- fine search disable 1002- fine search on
+0x002A149E,
+0x0F120002, //#af_search_usFinePeakCount
+0x0F120000, //#af_search_usFineMaxScale
+0x002A142C,
+0x0F120601, //#af_pos_usFineStepNumSize
+0x002A14A2,
+0x0F120000, //#af_search_usCapturePolicy 0000 Shutter_Priority_Current
+
+//4.  AF Peak Threshold Setting
+0x002A1498,
+0x0F120001, //#af_search_usMinPeakSamples
+0x002A148A,
+0x0F1200E6, /*#af_search_usPeakThr  for */
+0x0F120090, //#af_search_usPeakThrLow
+
+//5.  AF Default Position
+0x002A1420,
+0x0F120000, //#af_pos_usHomePos
+0x0F124040, //#af_pos_usLowConfPos
+
+//6. AF statistics
+0x002A14B4,
+0x0F120280, //#af_search_usConfThr_4_  LowEdgeBoth GRAD
+0x002A14C0,
+0x0F1203A0, //#af_search_usConfThr_10_ LowLight HPF
+0x0F120320, //#af_search_usConfThr_11_
+0x002A14F4,
+0x0F120030, //#af_stat_usMinStatVal
+0x002A1514,
+0x0F120060, //#af_scene_usSceneLowNormBrThr
+// AF Scene Settings
+0x002A151E,
+0x0F120003, //#af_scene_usSaturatedScene
+
+//7. AF Lens Position Table Settings
+0x002A1434,
+0x0F120011, //#af_pos_usTableLastInd 10h_ 1h = 17 Steps 
+
+0x0F120030, //#af_pos_usTable_0_  48  
+0x0F120034, //#af_pos_usTable_1_  51   
+0x0F120038, //#af_pos_usTable_2_  54	
+0x0F12003C, //#af_pos_usTable_3_  57	
+0x0F120040, //#af_pos_usTable_4_  61   
+0x0F120044, //#af_pos_usTable_5_  65	
+0x0F120048, //#af_pos_usTable_6_  69	
+0x0F12004C, //#af_pos_usTable_7_  73	
+0x0F120050, //#af_pos_usTable_8_  78	
+0x0F120054, //#af_pos_usTable_9_  83	
+0x0F120058, //#af_pos_usTable_10_ 89	
+0x0F12005C, //#af_pos_usTable_11_ 89	
+0x0F120060, //#af_pos_usTable_12_ 89	
+0x0F120064, //#af_pos_usTable_13_ 89	
+0x0F120068, //#af_pos_usTable_14_ 89	
+0x0F12006C, //#af_pos_usTable_15_ 89	
+0x0F120070, //#af_pos_usTable_16_ 89	
+0x0F120074, //#af_pos_usTable_17_ 89		
+
+/*
+//8. Continuous AF setting
+//8-1 Continuous AF timing
+*/
+
+//9. VCM AF driver with PWM/I2C 
+0x002A1558,
+0x0F128000, //#afd_usParam[0]  I2C power down command
+0x0F120006, //#afd_usParam[1]  Position Right Shift 
+0x0F123FF0, //#afd_usParam[2]  I2C Data Mask
+0x0F1203E8, //#afd_usParam[3]  PWM Period
+0x0F120000, //#afd_usParam[4]  PWM Divider
+0x0F120200, //#afd_usParam[5]  SlowMotion Delay    reduce lens collision noise.
+0x0F120004, //#afd_usParam[6]  SlowMotion Threshold
+0x0F120100, //#afd_usParam[7]  Signal Shaping
+0x0F120040, //#afd_usParam[8]  Signal Shaping level 
+0x0F120080, //#afd_usParam[9]  Signal Shaping level
+0x0F1200C0, //#afd_usParam[10] Signal Shaping level
+0x0F1200E0, //#afd_usParam[11] Signal Shaping level
+
+0x002A0224,
+0x0F120003, //REG_TC_AF_AfCmd//Initialize AF subsystem (AF driver AF algorithm)
+
+//===================================================================
+// Flash setting
+//===================================================================
+0x002A018C,
+0x0F120001,//REG_TC_IPRM_AuxConfig // bit[0] : Flash is in use bit[1] : Mechanical shutter is in use                            // 0 : do not use 1 : use
+0x0F120003,//REG_TC_IPRM_AuxPolarity // bit[0] : Flash polarity (1 is active high) bit[1] : Mechanical shutter polarity (1 is active high)
+0x0F120003,//REG_TC_IPRM_AuxGpios  //1-4 : Flash GPIO number If GPIO number is overaped with AF GPIO F/W could be stop.
+
+//===================================================================
+// 1-H timing setting
+//===================================================================
+0x002A1686,
+0x0F12005C, //senHal_uAddColsBin
+0x0F12005C, //senHal_uAddColsNoBin
+0x0F12085C, //senHal_uMinColsHorBin
+0x0F12085C, //senHal_uMinColsNoHorBin
+0x0F12025A, //senHal_uMinColsAddAnalogBin
+
+//===================================================================
+// Forbidden area setting
+//===================================================================
+0x002A1844,
+0x0F120000, //senHal_bSRX //SRX off
+
+0x002A1680,
+0x0F120002, //senHal_NExpLinesCheckFine //0004 //extend Forbidden area line
+
+0x002A0ED2,
+0x0F120FA0,	//setot_uOnlineClocksDiv40
+
+//===================================================================
+// Preview subsampling mode
+//===================================================================
+0x002A18F8,
+0x0F120001, //senHal_bAACActiveWait2Start
+0x002A18F6,
+0x0F120001, //senHal_bAlwaysAAC
+0x002A182C,
+0x0F120001, //senHal_bSenAAC
+0x002A0EE4,
+0x0F120001, //setot_bUseDigitalHbin
+0x002A1674,
+0x0F120002, //senHal_SenBinFactor // 2:2x2 4:4x4
+0x0F120002, //senHal_SamplingType // 0:Full 1:digital 2:PLA 3:CA
+0x0F120000, //senHal_SamplingMode // 0:2x2	1:4x4
+
+//===================================================================
+// PLL setting for Max frequency (EVT0.1) 2010.08.05 - Do not remove
+//===================================================================
+0x002A19AE,
+0x0F12EA60, //pll_uMaxSysFreqKhz
+0x0F127530, //pll_uMaxPVIFreq4KH
+0x002A19C2,
+0x0F127530, //pll_uMaxMIPIFreq4KH
+0x002A0244,
+0x0F127530, //REG_0TC_PCFG_usMaxOut4KHzRate
+0x002A0336,
+0x0F127530, //REG_0TC_CCFG_usMaxOut4KHzRate
+
+//===================================================================
+// Init Parameters
+//===================================================================
+//MCLK
+0x002A0188,
+0x0F125DC0, //REG_TC_IPRM_InClockLSBs
+0x0F120000, //REG_TC_IPRM_InClockMSBs
+0x002A01B2,
+0x0F120001, //REG_TC_IPRM_UseNPviClocks
+0x0F120002, //REG_TC_IPRM_UseNMipiClocks
+0x002A01B8,
+0x0F120001, //REG_TC_IPRM_bBlockInternalPllCalc                  //1:pll bypass
+
+
+//SCLK & PCLK // clock set 0
+0x0F1238A4,//38A4	//36B0//34BC //32C8//REG_TC_IPRM_OpClk4KHz_0 //52Mhz
+0x0F1254F0,//4E20	//3A98//7148 //4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0	//54Mhz
+0x0F1254F8,//57E4	//61A8//7148 //4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0	//54Mhz
+
+	//SCLK & PCLK     // clock set 1
+0x0F1238A4,//38A4//36B0//34BC	//32C8//REG_TC_IPRM_OpClk4KHz_0	//52Mhz
+0x0F1254F0,//4E20//3A98//7148	//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0//54Mhz
+0x0F1254F8,//57E4//61A8//7148	//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0//54Mhz
+
+	//SCLK & PCLK     // clock set 2                                             
+0x0F1238A4,//38A4//36B0 //34BC//32C8//REG_TC_IPRM_OpClk4KHz_0//52Mhz          
+0x0F1254F0,//4E20//3A98 //7148//4B32//34BC//REG_TC_IPRM_MinOutRate4KHz_0 //54Mhz  
+0x0F1254F8,//57E4//61A8 //7148//4B32//34BC//REG_TC_IPRM_MaxOutRate4KHz_0 //54Mhz  
+
+0x002A1B78,
+0x0F1238A4, //REGM_gSensorClocks_0__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_0__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_0__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_0__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_0__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_0__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_0__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_0__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_0__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_0__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_0__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_0__usSysDiv
+0x0F120001, //REGM_gSensorClocks_0__usOIFDenum
+
+0x002A1B9C,
+0x0F1238A4, //REGM_gSensorClocks_1__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_1__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_1__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_1__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_1__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_1__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_1__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_1__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_1__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_1__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_1__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_1__usSysDiv
+0x0F120001, //REGM_gSensorClocks_1__usOIFDenum
+
+0x002A1BC0,
+0x0F1238A4, //REGM_gSensorClocks_2__PLL_usClkFreqDiv4
+0x0F120074, //REGM_gSensorClocks_2__PLL_PllHW_M
+0x0F120004, //REGM_gSensorClocks_2__PLL_PllHW_P
+0x0F120000, //REGM_gSensorClocks_2__PLL_PllHW_S
+0x0F120002, //REGM_gSensorClocks_2__PLL_PllHW_VS
+0x0F120003, //REGM_gSensorClocks_2__PLL_PllHW_VP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_SysDiv
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OS
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_OP
+0x0F120001, //REGM_gSensorClocks_2__PLL_PllHW_PviDiv
+0x0F120006, //REGM_gSensorClocks_2__PLL_PllHW_DblDiv
+0x0F12000C, //REGM_gSensorClocks_2__PLL_PllHW_OIF_dphy_val
+0x0F125DC0, //REGM_gSensorClocks_2__InputClk
+0x0F120000,
+0x0F1254F6, //REGM_gSensorClocks_2__usPviFreqDiv4
+0x0F12000C, //REGM_gSensorClocks_2__usSysDiv
+0x0F120001, //REGM_gSensorClocks_2__usOIFDenum
+
+
+0x002A01CC,
+0x0F120001, //REG_TC_IPRM_InitParamsUpdated
+
+0xFFFF000A,
+//===================================================================
+// Input Width & Height
+//===================================================================
+0x002A01F6, 
+0x0F120500, //5C0, //0800 //REG_TC_GP_PrevReqInputWidth	  //Sensor Crop Width	2048
+0x0F1202d0, //33C, //0600 //REG_TC_GP_PrevReqInputHeight  //Sensor Crop Height 1536
+0x0F120198, //180, //120, //0000 //REG_TC_GP_PrevInputWidthOfs	  //Sensor HOffset 0
+0x0F120162, //0000 //REG_TC_GP_PrevInputHeightOfs  //Sensor VOffset 0
+0x0F120800, //REG_TC_GP_CapReqInputWidth	//Sensor Crop Width	2048
+0x0F120600, //REG_TC_GP_CapReqInputHeight	//Sensor Crop Height 1536
+0x0F120000, //REG_TC_GP_CapInputWidthOfs	//Sensor HOffset 0
+0x0F120000, //REG_TC_GP_CapInputHeightOfs	//Sensor VOffset 0
+
+0x002A1676,
+0x0F120002,// 0:Full 1:digital 2:PLA 3:CA
+
+0x002A0216,
+0x0F120001,//for input size change
+
+0x002A0216,
+0x0F120001, //REG_TC_GP_bUseReqInputInPre
+0x0F120001, //REG_TC_GP_bUseReqInputInCap
+
+0x002A043C,
+0x0F120800, //REG_TC_PZOOM_ZoomInputWidth
+0x0F120600, //REG_TC_PZOOM_ZoomInputHeight
+0x0F120000, //REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000, //REG_TC_PZOOM_ZoomInputHeightOfs
+
+//===================================================================
+// Preview 0 1024x768 system 52M PCLK 54M
+//===================================================================
+0x002A023E,
+0x0F120500, //REG_0TC_PCFG_usWidth
+0x0F1202D0, //REG_0TC_PCFG_usHeight
+0x0F120005, //REG_0TC_PCFG_Format
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMaxOut4KHzRate
+0x0F1254F6,	//7148 //REG_0TC_PCFG_usMinOut4KHzRate
+
+0x002A024C,
+0x0F120012, //REG_0TC_PCFG_PVIMask    => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_PCFG_OIFMask
+
+0x002A0254,
+0x0F120001, //REG_0TC_PCFG_uClockInd
+0x0F120000, //REG_0TC_PCFG_usFrTimeType
+0x0F120002, //REG_0TC_PCFG_FrRateQualityType
+0x0F1201B8, //1A0 //REG_0TC_PCFG_usMaxFrTimeMsecMult10  //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS 01a0-24fr
+0x0F12014D, //REG_0TC_PCFG_usMinFrTimeMsecMult10 //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+0x0F120000, //REG_0TC_PCFG_bSmearOutput
+0x0F120000, //REG_0TC_PCFG_sSaturation
+0x0F120000, //REG_0TC_PCFG_sSharpBlur
+0x0F120000, //REG_0TC_PCFG_sColorTemp
+0x0F120000, //REG_0TC_PCFG_uDeviceGammaIndex
+0x0F120000, //3, //REG_0TC_PCFG_uPrevMirror
+0x0F120000, //3, //REG_0TC_PCFG_uCaptureMirror
+0x0F120000, //REG_0TC_PCFG_uRotation
+
+
+//===================================================================
+// Capture 0 2048x1536 system 52M PCLK 54M
+//===================================================================
+0x002A032E,
+0x0F120000, //REG_0TC_CCFG_uCaptureMode
+
+0x0F120800, //REG_0TC_CCFG_usWidth
+0x0F120600, //REG_0TC_CCFG_usHeight
+0x0F120005, //REG_0TC_CCFG_Format//PCAM 5:YUV   9:JPEG
+0x0F1254F6,	//REG_0TC_CCFG_usMaxOut4KHzRate
+0x0F1254F6,	//REG_0TC_CCFG_usMinOut4KHzRate
+
+0x002A033E,
+0x0F120010, //REG_0TC_CCFG_PVIMask  => cmk 2010.10.29 s0042 => s0052 Invert Y C order
+0x0F120010, //REG_0TC_CCFG_OIFMask
+0x0F1203C0, //REG_0TC_CCFG_usJpegPacketSize
+
+0x002A0346,
+0x0F120001, //REG_0TC_CCFG_uClockInd
+0x0F120002, //REG_0TC_CCFG_usFrTimeType
+0x0F120002, //REG_0TC_CCFG_FrRateQualityType
+0x0F120535, //REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A, //REG_0TC_CCFG_usMinFrTimeMsecMult10
+0x0F120000, //REG_0TC_CCFG_bSmearOutput
+0x0F120000, //REG_0TC_CCFG_sSaturation
+0x0F120000, //REG_0TC_CCFG_sSharpBlur
+0x0F120000, //REG_0TC_CCFG_sColorTemp
+0x0F120000, //REG_0TC_CCFG_uDeviceGammaIndex
+
+0x002A0426,
+0x0F120055, //REG_TC_BRC_usCaptureQuality
+
+
+0x002A1E5C, //Mon_LT_uDefMinFrExpDelta
+0x0F120000,
+
+/* PREVIEW */
+/* 0x002A0208, */
+/* 0x0F120000, */ /* REG_TC_GP_ActivePrevConfig */
+/* 0x002A0210, */
+/* 0x0F120000, */ /* REG_TC_GP_ActiveCapConfig */
+/* 0x002A020C, */
+/* 0x0F120001, */ /* REG_TC_GP_PrevOpenAfterChange */
+/* 0x002A01F4, */
+/* 0x0F120001, */ /* REG_TC_GP_NewConfigSync */
+/* 0x002A020A, */
+/* 0x0F120001, */ /* REG_TC_GP_PrevConfigChanged */
+/* 0x002A0212 ,*/
+/* 0x0F120001, */ /* REG_TC_GP_CapConfigChanged */
+/* 0x002A01E8, */
+/* 0x0F120000, */ /* REG_TC_GP_EnableCapture */
+/* 0x0F120001, */ /* REG_TC_GP_EnableCaptureChanged */
+
+/* 0xFFFF0064, */ /* Delay 100ms */
+
+
+//===================================================================
+// AFC
+//===================================================================
+//Auto
+0x002A0F08,
+0x0F120000, //1, //AFC_Default60Hz   01:60hz 00:50Hz
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+
+
+//===================================================================
+// Shading (AF module)
+//===================================================================
+// TVAR_ash_pGAS_high
+0x002A0D22,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120000,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120000,
+0x0F12000F,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F00,
+0x0F120F00,
+0x0F12000F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F12000F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+0x0F120F00,
+0x0F120F00,
+0x0F120000,
+0x0F120F0F,
+0x0F12000F,
+0x0F120F0F,
+0x0F120000,
+0x0F12000F,
+0x0F120F0F,
+
+// TVAR_ash_pGAS_low
+0x0F126E49,
+0x0F12FB98,
+0x0F12F348,
+0x0F121BD6,
+0x0F12EBEF,
+0x0F1203D3,
+0x0F12EC8D,
+0x0F12F239,
+0x0F120E64,
+0x0F12F7EA,
+0x0F12FD3B,
+0x0F120A7C,
+0x0F12FC9C,
+0x0F120BD3,
+0x0F12F2E5,
+0x0F120619,
+0x0F120772,
+0x0F12F0B0,
+0x0F12184E,
+0x0F12F95F,
+0x0F120B1A,
+0x0F12FC45,
+0x0F12F716,
+0x0F120DCD,
+0x0F12EF24,
+0x0F120221,
+0x0F12F6BD,
+0x0F1204CB,
+0x0F1200B1,
+0x0F12FEB0,
+0x0F120268,
+0x0F1202C7,
+0x0F12010A,
+0x0F12FF93,
+0x0F12036D,
+0x0F12F859,
+0x0F1281D0,
+0x0F12FA32,
+0x0F12EFDB,
+0x0F12234D,
+0x0F12E799,
+0x0F120337,
+0x0F12EB05,
+0x0F12E8F9,
+0x0F12152E,
+0x0F12F0D5,
+0x0F120842,
+0x0F12043A,
+0x0F12F461,
+0x0F120E58,
+0x0F12F658,
+0x0F12075D,
+0x0F12F78D,
+0x0F12FDE9,
+0x0F12277A,
+0x0F12FFDE,
+0x0F12FD3B,
+0x0F12FE50,
+0x0F120AD1,
+0x0F12FE2C,
+0x0F12E90D,
+0x0F12F7B0,
+0x0F1205DB,
+0x0F1202CD,
+0x0F12F4F1,
+0x0F1202A8,
+0x0F12FDDC,
+0x0F120B59,
+0x0F12F74E,
+0x0F1203D5,
+0x0F12FF4F,
+0x0F1200F7,
+0x0F126A44,
+0x0F12FAD6,
+0x0F12F261,
+0x0F121F28,
+0x0F12E691,
+0x0F1207D2,
+0x0F12EE85,
+0x0F12F426,
+0x0F120F26,
+0x0F12F34B,
+0x0F120036,
+0x0F120C0F,
+0x0F12FDA9,
+0x0F1209EA,
+0x0F12F27A,
+0x0F120CD5,
+0x0F1201E1,
+0x0F12ED41,
+0x0F121DB5,
+0x0F12FD26,
+0x0F1203F7,
+0x0F12F7BB,
+0x0F12FE81,
+0x0F1212D3,
+0x0F12E061,
+0x0F12F81C,
+0x0F1207B1,
+0x0F120408,
+0x0F12F860,
+0x0F12FC9A,
+0x0F120DDE,
+0x0F120C9C,
+0x0F12F2A4,
+0x0F1202EB,
+0x0F12099B,
+0x0F12F5A6,
+0x0F127243,
+0x0F12F74D,
+0x0F12F74B,
+0x0F121800,
+0x0F12EF22,
+0x0F120263,
+0x0F12EBE7,
+0x0F12F5A4,
+0x0F1209D3,
+0x0F12FAB8,
+0x0F12FDFF,
+0x0F12086B,
+0x0F120338,
+0x0F120514,
+0x0F12F840,
+0x0F120768,
+0x0F12FE55,
+0x0F12F884,
+0x0F121488,
+0x0F12FFCD,
+0x0F12035B,
+0x0F12FA4E,
+0x0F1201DB,
+0x0F1206D6,
+0x0F12EE19,
+0x0F12FEA3,
+0x0F12FE8C,
+0x0F1203A3,
+0x0F12FDDB,
+0x0F12FD9B,
+0x0F12035E,
+0x0F1203F2,
+0x0F12FCBD,
+0x0F120300,
+0x0F12FF2E,
+0x0F12FE03,
+
+0x002A04A8,
+0x0F120001, //REG_TC_DBG_ReInitCmd
+
+//===================================================================
+// Shading - Alpha
+//===================================================================
+0x002A07E8,
+0x0F1200BC, //TVAR_ash_AwbAshCord_0_//HOR
+0x0F1200ED, //TVAR_ash_AwbAshCord_1_//INCA
+0x0F120101, //TVAR_ash_AwbAshCord_2_//WW
+0x0F12012D, //TVAR_ash_AwbAshCord_3_//CW
+0x0F120166, //TVAR_ash_AwbAshCord_4_//D50
+0x0F120184, //TVAR_ash_AwbAshCord_5_//D65
+0x0F1201A0, //TVAR_ash_AwbAshCord_6_//D75
+0x002A07FE,
+0x0F123200, //TVAR_ash_GASAlpha_0__0_
+0x0F124000, //TVAR_ash_GASAlpha_0__1_
+0x0F124000, //TVAR_ash_GASAlpha_0__2_
+0x0F123C00, //TVAR_ash_GASAlpha_0__3_
+0x0F123200, //TVAR_ash_GASAlpha_1__0_
+0x0F124000, //TVAR_ash_GASAlpha_1__1_
+0x0F124000, //TVAR_ash_GASAlpha_1__2_
+0x0F123C00, //TVAR_ash_GASAlpha_1__3_
+0x0F123200, //TVAR_ash_GASAlpha_2__0_
+0x0F124000, //TVAR_ash_GASAlpha_2__1_
+0x0F124000, //TVAR_ash_GASAlpha_2__2_
+0x0F123C00, //TVAR_ash_GASAlpha_2__3_
+0x0F123200, //TVAR_ash_GASAlpha_3__0_
+0x0F124000, //TVAR_ash_GASAlpha_3__1_
+0x0F124000, //TVAR_ash_GASAlpha_3__2_
+0x0F123C00, //TVAR_ash_GASAlpha_3__3_
+0x0F123200, //TVAR_ash_GASAlpha_4__0_
+0x0F124000, //TVAR_ash_GASAlpha_4__1_
+0x0F124000, //TVAR_ash_GASAlpha_4__2_
+0x0F123C00, //TVAR_ash_GASAlpha_4__3_
+0x0F123200, //TVAR_ash_GASAlpha_5__0_
+0x0F124000, //TVAR_ash_GASAlpha_5__1_
+0x0F124000, //TVAR_ash_GASAlpha_5__2_
+0x0F123C00, //TVAR_ash_GASAlpha_5__3_
+0x0F124000, //TVAR_ash_GASAlpha_6__0_
+0x0F124000, //TVAR_ash_GASAlpha_6__1_
+0x0F124000, //TVAR_ash_GASAlpha_6__2_
+0x0F123C00, //TVAR_ash_GASAlpha_6__3_
+
+0x002A0836,
+0x0F123E00, //TVAR_ash_GASOutdoorAlpha_0_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_1_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_2_
+0x0F124000, //TVAR_ash_GASOutdoorAlpha_3_
+
+//===================================================================
+// Gamma
+//===================================================================
+//	param_start	SARR_usGammaLutRGBIndoor
+0x002A0660,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+0x0F120000,
+0x0F120023,
+0x0F120044,
+0x0F12007B,
+0x0F1200BB,
+0x0F120102,
+0x0F12012F,
+0x0F120143,
+0x0F120155,
+0x0F120172,
+0x0F12018C,
+0x0F1201A4,
+0x0F1201BC,
+0x0F1201EC,
+0x0F12021D,
+0x0F12027E,
+0x0F1202DF,
+0x0F12033F,
+0x0F12039F,
+0x0F1203FF,
+
+//s002A06D8
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[0][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[0][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[0][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[0][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[0][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[0][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[0][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[0][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[0][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[0][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[0][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[0][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[0][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[0][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[0][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[0][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[0][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[0][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[0][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[0][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[1][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[1][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[1][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[1][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[1][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[1][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[1][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[1][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[1][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[1][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[1][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[1][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[1][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[1][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[1][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[1][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[1][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[1][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[1][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[1][19]
+0x0F120001, //saRR_usDualGammaLutRGBOutdoor[2][0]
+0x0F120011, //saRR_usDualGammaLutRGBOutdoor[2][1]
+0x0F120028, //saRR_usDualGammaLutRGBOutdoor[2][2]
+0x0F120059, //saRR_usDualGammaLutRGBOutdoor[2][3]
+0x0F12009D, //saRR_usDualGammaLutRGBOutdoor[2][4]
+0x0F1200F2, //saRR_usDualGammaLutRGBOutdoor[2][5]
+0x0F120128, //saRR_usDualGammaLutRGBOutdoor[2][6]
+0x0F12013D, //saRR_usDualGammaLutRGBOutdoor[2][7]
+0x0F12014E, //saRR_usDualGammaLutRGBOutdoor[2][8]
+0x0F120168, //saRR_usDualGammaLutRGBOutdoor[2][9]
+0x0F12017C, //saRR_usDualGammaLutRGBOutdoor[2][10]
+0x0F120190, //saRR_usDualGammaLutRGBOutdoor[2][11]
+0x0F1201A4, //saRR_usDualGammaLutRGBOutdoor[2][12]
+0x0F1201CC, //saRR_usDualGammaLutRGBOutdoor[2][13]
+0x0F1201F4, //saRR_usDualGammaLutRGBOutdoor[2][14]
+0x0F120243, //saRR_usDualGammaLutRGBOutdoor[2][15]
+0x0F120293, //saRR_usDualGammaLutRGBOutdoor[2][16]
+0x0F1202E9, //saRR_usDualGammaLutRGBOutdoor[2][17]
+0x0F120338, //saRR_usDualGammaLutRGBOutdoor[2][18]
+0x0F12038E, //saRR_usDualGammaLutRGBOutdoor[2][19]
+
+//===================================================================
+// AE - shutter
+//===================================================================
+//****************************************/
+// AE 2009 03 08 - based on TN
+//****************************************/
+
+//add ki 11.02.18
+// SLOW AE
+// SLOW AE
+0x002A13F2,
+0x0F120014,// 0010 ae_GainIn_0_	//
+0x0F120032,// 0020	ae_GainIn_1_//					
+0x0F120078,// 0040	ae_GainIn_2_//					
+0x0F1200AA,// 0080	ae_GainIn_3_//					
+0x0F120100,// 0100	ae_GainIn_4_//					
+0x0F120140,// 0200	ae_GainIn_5_//					
+0x0F1201B8,// 0400	ae_GainIn_6_//					
+0x0F120400,// 0800	ae_GainIn_7_//					
+0x0F122000,// 2000	ae_GainIn_8_//	
+
+0x0F120046,//0050	// 0010	ae_GainOut_0_	p	 //						
+0x0F120078,//0070	// 0020	ae_GainOut_1_ p //						
+0x0F1200BE,//00A0	// 0040	ae_GainOut_2_	p	 //						
+0x0F1200DC,//00D0	// 0080	ae_GainOut_3_	p	 //						
+0x0F120100,// fix 0100	ae_GainOut_4_	//
+0x0F12010E,// 0200	ae_GainOut_5_	//
+0x0F120140,// 0400	ae_GainOut_6_	//
+0x0F1201F4,// 0800	ae_GainOut_7_	//
+0x0F120200,// 2000	ae_GainOut_8_	//
+
+
+0x002A13BC,
+0x0F120100,//0000ae_ContrastS_0_//
+0x0F120100,//000Cae_ContrastS_1_//
+0x0F120100,//001Cae_ContrastS_2_//
+0x0F120100,//0020ae_ContrastS_3_//
+0x0F120100,//0020ae_ContrastS_4_//
+0x0F120100,//0020ae_ContrastS_5_//
+0x0F120100,//0020ae_ContrastS_6_//
+0x0F120100,//0020ae_ContrastS_7_//
+
+//============================================================
+// Frame rate setting
+//============================================================
+// How to set
+// 1. Exposure value
+// dec2hex((1 / (frame rate you want(ms))) * 100d * 5d)
+//
+//
+// 2. Analog Digital gain
+// dec2hex((Analog gain you want) * 256d)
+//              Ex1) Simple Caculation for x3.25?:   3.25x256 = 832[dec] = 0340[hex]
+//============================================================
+//MBR
+
+
+0x002A01DE,
+0x0F120000, //REG_TC_bUseMBR  //MBR off
+//MBR off is needed to prevent a shorter integration time when the scene has blurring in Night shot
+
+//AE_Target
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+0x002A130E,
+0x0F12000F, //ae_StatMode
+//ae_StatMode bit[3] BLC has to be bypassed to prevent AE weight change especially backlight scene
+
+//AE_state
+0x002A04EE,
+0x0F120105, //010E //#lt_uLimitHigh
+0x0F1200FA, //00F5 //#lt_uLimitLow
+
+0x002A0500,                           
+0x0F120001,	 //lt_uInitPostToleranceCnt
+
+//For 60Hz
+0x002A0504,
+0x0F123415, //3415//#lt_uMaxExp1
+0x002A0508,
+0x0F123415, //26e8//681F//#lt_uMaxExp2
+0x002A050C,
+0x0F123415, //26e8//8227//#lt_uMaxExp3
+0x002A0510,
+0x0F12C350, //#lt_uMaxExp4
+
+0x002A0514,
+0x0F123415, //#lt_uCapMaxExp1
+0x002A0518,
+0x0F123415, //681F //#lt_uCapMaxExp2
+0x002A051C,
+0x0F123415, //8227 //#lt_uCapMaxExp3
+0x002A0520,
+0x0F12C350, //#lt_uCapMaxExp4
+
+0x002A0524,
+0x0F120200, //1E0 //#lt_uMaxAnGain1
+0x0F120240, //1E0 //#lt_uMaxAnGain2
+0x0F120340, //0300 //#lt_uMaxAnGain3
+0x0F120A00, /*#lt_uMaxAnGain4*/
+
+0x0F120100, //#lt_uMaxDigGain
+0x0F128000, //#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+0x0F120200, //#lt_uCapMaxAnGain1
+0x0F120240, //#lt_uCapMaxAnGain2
+0x0F120340, //300 //#lt_uCapMaxAnGain3
+0x0F120A00, //#lt_uCapMaxAnGain4
+
+0x0F120100, //#lt_uCapMaxDigGain
+0x0F128000, //#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain
+
+//===================================================================
+//AE - Weights
+//===================================================================
+0x002A1316,                                                                        
+0x0F120101, //ae_WeightTbl_16[0]   0000
+0x0F120101, //ae_WeightTbl_16[1]   0000
+0x0F120101, //ae_WeightTbl_16[2]   0000
+0x0F120101, //ae_WeightTbl_16[3]   0000
+0x0F120101, //ae_WeightTbl_16[4]   0101
+0x0F120101, //ae_WeightTbl_16[5]   0101
+0x0F120101, //ae_WeightTbl_16[6]   0101
+0x0F120101, //ae_WeightTbl_16[7]   0101
+0x0F120101, //ae_WeightTbl_16[8]   0101
+0x0F120202, //ae_WeightTbl_16[9]   0201
+0x0F120202, //ae_WeightTbl_16[10]  0102
+0x0F120101, //ae_WeightTbl_16[11]  0101
+0x0F120101, //ae_WeightTbl_16[12]  0101
+0x0F120202, //ae_WeightTbl_16[13]  0202
+0x0F120202, //ae_WeightTbl_16[14]  0202
+0x0F120101, //ae_WeightTbl_16[15]  0101
+0x0F120101, //ae_WeightTbl_16[16]  0101
+0x0F120202, //ae_WeightTbl_16[17]  0202
+0x0F120202, //ae_WeightTbl_16[18]  0202
+0x0F120101, //ae_WeightTbl_16[19]  0101
+0x0F120101, //ae_WeightTbl_16[20]  0201
+0x0F120202, //ae_WeightTbl_16[21]  0202
+0x0F120202, //ae_WeightTbl_16[22]  0202
+0x0F120101, //ae_WeightTbl_16[23]  0102
+0x0F120101, //ae_WeightTbl_16[24]  0201
+0x0F120101, //ae_WeightTbl_16[25]  0202
+0x0F120101, //ae_WeightTbl_16[26]  0202
+0x0F120101, //ae_WeightTbl_16[27]  0102
+0x0F120101, //ae_WeightTbl_16[28]  0101
+0x0F120101, //ae_WeightTbl_16[29]  0101
+0x0F120101, //ae_WeightTbl_16[30]  0101
+0x0F120101, //ae_WeightTbl_16[31]  0101
+
+//===================================================================
+//AWB-BASIC setting
+//===================================================================
+0x002A1018,
+0x0F1202A7, //awbb_GLocusR
+0x0F120343, //awbb_GLocusB
+0x002A0FFC,
+0x0F12036C, //awbb_CrclLowT_R_c
+0x002A1000,
+0x0F12011D, //awbb_CrclLowT_B_c
+0x002A1004,
+0x0F1262C1, //awbb_CrclLowT_Rad_c
+0x002A1034,
+0x0F12074D,//05F0 //awbb_GamutWidthThr1
+0x0F120433,//01F4 //awbb_GamutHeightThr1
+0x0F12002A,//006C //awbb_GamutWidthThr2
+0x0F12000C,//0038 //awbb_GamutHeightThr2
+0x002A1020,
+0x0F120020,	//000C //awbb_MinNumOfFinalPatches
+0x0F12001E, //awbb_MinNumOfLowBrFinalPatches
+0x0F120046, //awbb_MinNumOfLowBr0_FinalPatches
+0x002A1028,
+0x0F120020,	//awbb_MinNumOfOutdoorPatches
+
+0x002A291A,
+0x0F120004, // #Mon_AWB_ByPassMode // [0]Outdoor [1]LowBr [2]LowTemp
+
+0x002A1048,
+0x0F1200C8,	//awbb_LowBr								
+0x0F12001E,	//awbb_LowBr_NBzone						
+
+0x002A1008,
+0x0F120020,	//awbb_NormalYThresh_y_low
+0x0F1200A0,	//awbb_NormalYThresh_y_high
+0x0F120002, //awbb_LowBrYThresh_y_low
+0x0F1200A0, //awbb_LowBrYThresh_y_high
+
+
+
+0x002A102E,
+0x0F12054D,	//awbb_MvEq_RBthresh
+
+0x002A1032,
+0x0F120000, //awbb_MovingScale10
+
+0x002A11C2,
+0x0F120000, //awbb_RGainOff
+0x0F120000, //awbb_BGainOff
+0x0F120000, //awbb_GGainOff
+0x0F1200C2, //awbb_Alpha_Comp_Mode
+0x0F120002, //awbb_Rpl_InvalidOutDoor
+0x0F120001, //awbb_UseGrThrCorr
+0x0F1200E4, //awbb_Use_Filters
+0x0F12053C, //awbb_GainsInit[0]
+0x0F120400, //awbb_GainsInit[1]
+0x0F12055C, //awbb_GainsInit[2]
+
+//===================================================================
+//AWB-Zone
+//===================================================================
+//	param_start	awbb_IndoorGrZones_m_BGrid
+0x002A0F28,
+0x0F120426,	//03C0//03C0//03C0//awbb_IndoorGrZones_m_BGrid[0]
+0x0F12047E,	//03E2//03E2//03E2//awbb_IndoorGrZones_m_BGrid[1]
+0x0F1203C6,	//0356//0356//0356//awbb_IndoorGrZones_m_BGrid[2]
+0x0F120496,	//03FC//03FC//03FC//awbb_IndoorGrZones_m_BGrid[3]
+0x0F120374,	//031E//031E//031E//awbb_IndoorGrZones_m_BGrid[4]
+0x0F1204A0,	//03FE//03FE//03FE//awbb_IndoorGrZones_m_BGrid[5]
+0x0F12033A,	//02F0//02F0//02F0//awbb_IndoorGrZones_m_BGrid[6]
+0x0F120498,	//03F0//03F0//03F0//awbb_IndoorGrZones_m_BGrid[7]
+0x0F120312,	//02CA//02CA//02CA//awbb_IndoorGrZones_m_BGrid[8]
+0x0F120478,	//03CC//03CC//03CC//awbb_IndoorGrZones_m_BGrid[9]
+0x0F1202EA,	//02A8//02A8//02A8//awbb_IndoorGrZones_m_BGrid[10]
+0x0F120440,	//037A//037A//037A//awbb_IndoorGrZones_m_BGrid[11]
+0x0F1202C2,	//0280//0288//0288//awbb_IndoorGrZones_m_BGrid[12]
+0x0F1203FA,	//033C//033C//033C//awbb_IndoorGrZones_m_BGrid[13]
+0x0F12029A,	//0260//0266//0266//awbb_IndoorGrZones_m_BGrid[14]
+0x0F1203BE,	//030A//030A//031E//awbb_IndoorGrZones_m_BGrid[15]
+0x0F120272,	//0242//0246//0246//awbb_IndoorGrZones_m_BGrid[16]
+0x0F120398,	//02DC//02EC//0300//awbb_IndoorGrZones_m_BGrid[17]
+0x0F12024E,	//0228//0228//0228//awbb_IndoorGrZones_m_BGrid[18]
+0x0F120372,	//02B2//02CE//02E8//awbb_IndoorGrZones_m_BGrid[19]
+0x0F12022A,	//020E//020E//020E//awbb_IndoorGrZones_m_BGrid[20]
+0x0F120340,	//0290//02B0//02CA//awbb_IndoorGrZones_m_BGrid[21]
+0x0F120206,	//01F8//01F8//01F8//awbb_IndoorGrZones_m_BGrid[22]
+0x0F120310,	//0276//0292//02B0//awbb_IndoorGrZones_m_BGrid[23]
+0x0F1201E2,	//01E8//01E8//01E8//awbb_IndoorGrZones_m_BGrid[24]
+0x0F1202DE,	//0268//0276//0296//awbb_IndoorGrZones_m_BGrid[25]
+0x0F1201C0,	//01DC//01DC//01DC//awbb_IndoorGrZones_m_BGrid[26]
+0x0F1202AE,	//0256//0256//027A//awbb_IndoorGrZones_m_BGrid[27]
+0x0F1201B4,	//01E0//01E0//01E0//awbb_IndoorGrZones_m_BGrid[28]
+0x0F12027E,	//0238//0238//0252//awbb_IndoorGrZones_m_BGrid[29]
+0x0F1201C0,	//01EC//01EC//01F2//awbb_IndoorGrZones_m_BGrid[30]
+0x0F12024C,	//020E//020E//0226//awbb_IndoorGrZones_m_BGrid[31]
+0x0F1201FA,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[32]
+0x0F12021C,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[33]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[34]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[35]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[36]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[37]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[38]
+0x0F120000,	//0000//0000//0000//awbb_IndoorGrZones_m_BGrid[39]
+//	param_end	awbb_IndoorGrZones_m_BGrid
+
+0x0F120005, //awbb_IndoorGrZones_m_Grid
+0x002A0F80,
+0x0F1200A6, //awbb_IndoorGrZones_m_Boff
+0x002A0F7C,
+0x0F120011,
+
+//	param_start	awbb_OutdoorGrZones_m_BGrid
+0x002A0F84,
+0x0F12023E, //awbb_OutdoorGrZones_m_BGrid[0]
+0x0F120286, //awbb_OutdoorGrZones_m_BGrid[1]
+0x0F12022C, //awbb_OutdoorGrZones_m_BGrid[2]
+0x0F1202CC, //awbb_OutdoorGrZones_m_BGrid[3]
+0x0F12021A, //awbb_OutdoorGrZones_m_BGrid[4]
+0x0F1202F0, //awbb_OutdoorGrZones_m_BGrid[5]
+0x0F120208, //awbb_OutdoorGrZones_m_BGrid[6]
+0x0F120316, //awbb_OutdoorGrZones_m_BGrid[7]
+0x0F1201F6, //awbb_OutdoorGrZones_m_BGrid[8]
+0x0F1202FE, //awbb_OutdoorGrZones_m_BGrid[9]
+0x0F1201E4, //awbb_OutdoorGrZones_m_BGrid[10]
+0x0F1202E8, //awbb_OutdoorGrZones_m_BGrid[11]
+0x0F1201D2, //awbb_OutdoorGrZones_m_BGrid[12]
+0x0F1202D2, //awbb_OutdoorGrZones_m_BGrid[13]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[14]
+0x0F1202BC, //awbb_OutdoorGrZones_m_BGrid[15]
+0x0F1201CA, //awbb_OutdoorGrZones_m_BGrid[16]
+0x0F1202A6, //awbb_OutdoorGrZones_m_BGrid[17]
+0x0F1201D0, //awbb_OutdoorGrZones_m_BGrid[18]
+0x0F12028E, //awbb_OutdoorGrZones_m_BGrid[19]
+0x0F1201D6, //awbb_OutdoorGrZones_m_BGrid[20]
+0x0F120278, //awbb_OutdoorGrZones_m_BGrid[21]
+0x0F1201F8, //awbb_OutdoorGrZones_m_BGrid[22]
+0x0F120244, //awbb_OutdoorGrZones_m_BGrid[23]
+//	param_end	awbb_OutdoorGrZones_m_BGrid
+
+0x0F120004, //awbb_OutdoorGrZones_m_Gri
+0x002A0FB8,
+0x0F12000C, //awbb_OutdoorGrZones_ZInfo_m_GridSz
+0x002A0FBC,
+0x0F1201D8, //awbb_OutdoorGrZones_m_Bof
+
+//	param_start	awbb_LowBrGrZones_m_BGrid
+0x002A0FC0,
+0x0F120400, //awbb_LowBrGrZones_m_BGrid[0]
+0x0F120656, //awbb_LowBrGrZones_m_BGrid[1]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[2]
+0x0F1205BE, //awbb_LowBrGrZones_m_BGrid[3]
+0x0F1202E6, //awbb_LowBrGrZones_m_BGrid[4]
+0x0F120524, //awbb_LowBrGrZones_m_BGrid[5]
+0x0F120290, //awbb_LowBrGrZones_m_BGrid[6]
+0x0F1204A0, //awbb_LowBrGrZones_m_BGrid[7]
+0x0F120246, //awbb_LowBrGrZones_m_BGrid[8]
+0x0F12041A, //awbb_LowBrGrZones_m_BGrid[9]
+0x0F1201FE, //awbb_LowBrGrZones_m_BGrid[10]
+0x0F1203AE, //awbb_LowBrGrZones_m_BGrid[11]
+0x0F1201C0, //awbb_LowBrGrZones_m_BGrid[12]
+0x0F12035A, //awbb_LowBrGrZones_m_BGrid[13]
+0x0F120192, //awbb_LowBrGrZones_m_BGrid[14]
+0x0F120306, //awbb_LowBrGrZones_m_BGrid[15]
+0x0F120170, //awbb_LowBrGrZones_m_BGrid[16]
+0x0F1202BA, //awbb_LowBrGrZones_m_BGrid[17]
+0x0F12015C, //awbb_LowBrGrZones_m_BGrid[18]
+0x0F120278, //awbb_LowBrGrZones_m_BGrid[19]
+0x0F12019C, //awbb_LowBrGrZones_m_BGrid[20]
+0x0F12024E, //awbb_LowBrGrZones_m_BGrid[21]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[22]
+0x0F120000, //awbb_LowBrGrZones_m_BGrid[23]
+
+//	param_end	awbb_LowBrGrZones_m_BGrid
+0x0F120006, //awbb_LowBrGrZones_m_GridStep
+0x002A0FF4,
+0x0F12000B, //awbb_LowBrGrZones_ZInfo_m_GridSz
+0x002A0FF8,
+0x0F120082, //awbb_LowBrGrZones_m_Boffs
+
+//===================================================================
+//AWB Scene Detection
+//===================================================================
+0x002A1098,
+0x0F12FE82, //awbb_SCDetectionMap_SEC_StartR_B
+0x0F12001E, //awbb_SCDetectionMap_SEC_StepR_B
+0x0F1209C4, //awbb_SCDetectionMap_SEC_SunnyNB
+0x0F120122, //awbb_SCDetectionMap_SEC_StepNB
+0x0F1200E4, //awbb_SCDetectionMap_SEC_LowTempR_B
+0x0F120096, //awbb_SCDetectionMap_SEC_SunnyNBZone
+0x0F12000E, //awbb_SCDetectionMap_SEC_LowTempR_BZone
+
+0x002A105C,
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_0__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_1__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__2_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_2__4_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__1_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_3__3_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__0_
+0x0F120000, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__2_
+0x0F120500, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_4__4_
+0x0F125555, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__1_
+0x0F125455, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_5__3_
+0x0F12AA55, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__0_
+0x0F12AAAA, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__2_
+0x0F12BF54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_6__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_7__3_
+0x0F12FF6F, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__2_
+0x0F121B54, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_8__4_
+0x0F12FFFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__1_
+0x0F1254FE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_9__3_
+0x0F12FF06, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__0_
+0x0F12FEFF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__2_
+0x0F120154, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_10__4_
+0x0F12BFBF, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__1_
+0x0F1254BE, //#awbb_SCDetectionMap_SEC_SceneDetectionMap_11__3_
+
+
+//===================================================================
+//AWB - GridCorrection
+//===================================================================
+0x002A11E0,
+0x0F120002, //awbb_GridEnable
+          
+0x002A11A8,
+0x0F12028E, //awbb_GridCon0xt_1[0]
+0x0F120306, //awbb_GridCon0xt_1[1]
+0x0F1203A6, //awbb_GridCon0xt_1[2]
+          
+0x0F120F86, //awbb_GridCon0xt_2[0]  0F86
+0x0F12105F, //awbb_GridCon0xt_2[1]  105F
+0x0F121160, //awbb_GridCon0xt_2[2]  11AA
+0x0F121161, //awbb_GridCon0xt_2[3]  1111
+0x0F1211F2, //awbb_GridCon0xt_2[4]  120C
+0x0F1212A1, //awbb_GridCon0xt_2[5]  126D
+          
+0x0F12008F, //awbb_GridCoeff_R_1
+0x0F1200D4, //awbb_GridCoeff_B_1
+0x0F1200C6, //awbb_GridCoeff_R_2
+0x0F1200A2, //awbb_GridCoeff_B_2
+          
+0x002A1118,
+0x0F120000, //0032//awbb_GridCorr_R[0][0]
+0x0F120000, //0012//awbb_GridCorr_R[0][1]
+0x0F120000, //0012//awbb_GridCorr_R[0][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[0][4]
+0x0F120060, //0050//awbb_GridCorr_R[0][5]
+0x0F120000, //0032//awbb_GridCorr_R[1][0]
+0x0F120000, //0012//awbb_GridCorr_R[1][1]
+0x0F120000, //0012//awbb_GridCorr_R[1][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[1][4]
+0x0F120060, //0050//awbb_GridCorr_R[1][5]
+0x0F120000, //0032//awbb_GridCorr_R[2][0]
+0x0F120000, //0012//awbb_GridCorr_R[2][1]
+0x0F120000, //0012//awbb_GridCorr_R[2][2]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][3]
+0x0F120018, //FFEC//awbb_GridCorr_R[2][4]
+0x0F120060, //0050//awbb_GridCorr_R[2][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[0][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[0][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[0][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[1][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[1][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[1][5]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][0]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][1]
+0x0F12FFD0, //FFD0//awbb_GridCorr_B[2][2]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][3]
+0x0F12FF22, //FE40//awbb_GridCorr_B[2][4]
+0x0F12FE3E, //FCE0//awbb_GridCorr_B[2][5]
+          
+0x002A1160,
+0x0F120000, //awbb_GridCorr_R_Out[0][0]
+0x0F120000, //awbb_GridCorr_R_Out[0][1]
+0x0F120000, //awbb_GridCorr_R_Out[0][2]
+0x0F120000, //awbb_GridCorr_R_Out[0][3]
+0x0F120000, //awbb_GridCorr_R_Out[0][4]
+0x0F120000, //awbb_GridCorr_R_Out[0][5]
+0x0F120000, //awbb_GridCorr_R_Out[1][0]
+0x0F120000, //awbb_GridCorr_R_Out[1][1]
+0x0F120000, //awbb_GridCorr_R_Out[1][2]
+0x0F120000, //awbb_GridCorr_R_Out[1][3]
+0x0F120000, //awbb_GridCorr_R_Out[1][4]
+0x0F120000, //awbb_GridCorr_R_Out[1][5]
+0x0F120000, //awbb_GridCorr_R_Out[2][0]
+0x0F120000, //awbb_GridCorr_R_Out[2][1]
+0x0F120000, //awbb_GridCorr_R_Out[2][2]
+0x0F120000, //awbb_GridCorr_R_Out[2][3]
+0x0F120000, //awbb_GridCorr_R_Out[2][4]
+0x0F120000, //awbb_GridCorr_R_Out[2][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[0][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[1][5]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][0]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][1]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][2]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][3]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][4]
+0x0F12FFA0, //awbb_GridCorr_B_Out[2][5]
+
+   
+ // SLOW AWB
+0x002A110E, 	
+0x0F120258, //0258 awbb_GainsMaxMove //
+
+ //AWB Convergence Speed //
+0x002A11D6, 
+0x0F120008,
+0x0F12FFFF,//0190	awbb_WpFilterMaxThr//
+0x0F120010,//00A0	//awbb_WpFilterCoef p  //
+0x0F120020, //0004 awbb_WpFilterSize//
+
+//===================================================================
+// CCM
+//===================================================================
+0x002A07D2,
+0x0F1200C0, //SARR_AwbCcmCord_0_
+0x0F1200E0, //SARR_AwbCcmCord_1_
+0x0F120110, //SARR_AwbCcmCord_2_
+0x0F120139, //SARR_AwbCcmCord_3_
+0x0F120166, //SARR_AwbCcmCord_4_
+0x0F12019F, //SARR_AwbCcmCord_5_
+
+//	param_start	TVAR_wbt_pBaseCcms
+0x002A07C4,
+0x0F124000, //TVAR_wbt_pBaseCcms
+0x0F127000,
+
+0x002A4000,
+0x0F1201D4, //01DA 01CF 01CE 01C0 01D4 //TVAR_wbt_pBaseCcms[0] 
+0x0F12FFCD, //FFC4 FFC3 FFB9 FFCB FFB2 //TVAR_wbt_pBaseCcms[1] 
+0x0F12FFC4, //FFCD FFDD FFE8 FFE4 FFEE //TVAR_wbt_pBaseCcms[2] 
+0x0F12FF2A, //FF31 FF43 FF43 FF43 FF47 //TVAR_wbt_pBaseCcms[3] 
+0x0F120124, //012A 011D 011D 011D 012C //TVAR_wbt_pBaseCcms[4] 
+0x0F12FF73, //FF6B FF6B FF6B FF6B FF5C //TVAR_wbt_pBaseCcms[5] 
+0x0F12FFE1, //FFDA FFDA FFDA FFDA FFCE //TVAR_wbt_pBaseCcms[6] 
+0x0F12FFBD, //FFC3 FFD1 FFD1 FFD1 FFD6 //TVAR_wbt_pBaseCcms[7] 
+0x0F120159, //015F 0156 0156 0156 0162 //TVAR_wbt_pBaseCcms[8] 
+0x0F1200EF, //0100 00FF 00FC 00F7 011D //TVAR_wbt_pBaseCcms[9] 
+0x0F1200E0, //00DE 00CE 00CC 00D1 00C6 //TVAR_wbt_pBaseCcms[10]
+0x0F12FED9, //FECE FEE3 FEE9 FEE9 FED2 //TVAR_wbt_pBaseCcms[11]
+0x0F1200DA, //00D5 00CD 00CD 00CD 00C8 //TVAR_wbt_pBaseCcms[12]
+0x0F12FF57, //FF56 FF5E FF5E FF5E FF56 //TVAR_wbt_pBaseCcms[13]
+0x0F120119, //0123 0128 0128 0128 0139 //TVAR_wbt_pBaseCcms[14]
+0x0F12FF74, //FF73 FF7E FF7E FF7E FF75 //TVAR_wbt_pBaseCcms[15]
+0x0F1200DF, //00E9 00EC 00EC 00EC 00FB //TVAR_wbt_pBaseCcms[16]
+0x0F1200FF, //00FC 00F2 00F2 00F2 00F0 //TVAR_wbt_pBaseCcms[17]
+
+0x0F1201D4, //01D4 //TVAR_wbt_pBaseCcms[18]
+0x0F12FFCD, //FFB2 //TVAR_wbt_pBaseCcms[19]
+0x0F12FFC4, //FFEE //TVAR_wbt_pBaseCcms[20]
+0x0F12FF2A, //FF47 //TVAR_wbt_pBaseCcms[21]
+0x0F120124, //012C //TVAR_wbt_pBaseCcms[22]
+0x0F12FF73, //FF5C //TVAR_wbt_pBaseCcms[23]
+0x0F12FFE1, //FFCE //TVAR_wbt_pBaseCcms[24]
+0x0F12FFBD, //FFD6 //TVAR_wbt_pBaseCcms[25]
+0x0F120159, //0162 //TVAR_wbt_pBaseCcms[26]
+0x0F1200EF, //011D //TVAR_wbt_pBaseCcms[27]
+0x0F1200E0, //00C6 //TVAR_wbt_pBaseCcms[28]
+0x0F12FED9, //FED2 //TVAR_wbt_pBaseCcms[29]
+0x0F1200DA, //00C8 //TVAR_wbt_pBaseCcms[30]
+0x0F12FF57, //FF56 //TVAR_wbt_pBaseCcms[31]
+0x0F120119, //0139 //TVAR_wbt_pBaseCcms[32]
+0x0F12FF74, //FF75 //TVAR_wbt_pBaseCcms[33]
+0x0F1200DF, //00FB //TVAR_wbt_pBaseCcms[34]
+0x0F1200FF, //00F0 //TVAR_wbt_pBaseCcms[35]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[36]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[37]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[38]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[39]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[40]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[41]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[42]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[43]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[44]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[45]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[46]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[47]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[48]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[49]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[50]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[51]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[52]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[53]
+
+0x0F1201C0, //01D4 //TVAR_wbt_pBaseCcms[54]
+0x0F12FFCB, //FFB2 //TVAR_wbt_pBaseCcms[55]
+0x0F12FFE4, //FFEE //TVAR_wbt_pBaseCcms[56]
+0x0F12FF43, //FF47 //TVAR_wbt_pBaseCcms[57]
+0x0F12011D, //012C //TVAR_wbt_pBaseCcms[58]
+0x0F12FF6B, //FF5C //TVAR_wbt_pBaseCcms[59]
+0x0F12FFDA, //FFCE //TVAR_wbt_pBaseCcms[60]
+0x0F12FFD1, //FFD6 //TVAR_wbt_pBaseCcms[61]
+0x0F120156, //0162 //TVAR_wbt_pBaseCcms[62]
+0x0F1200F7, //011D //TVAR_wbt_pBaseCcms[63]
+0x0F1200D1, //00C6 //TVAR_wbt_pBaseCcms[64]
+0x0F12FEE9, //FED2 //TVAR_wbt_pBaseCcms[65]
+0x0F1200CD, //00C8 //TVAR_wbt_pBaseCcms[66]
+0x0F12FF5E, //FF56 //TVAR_wbt_pBaseCcms[67]
+0x0F120128, //0139 //TVAR_wbt_pBaseCcms[68]
+0x0F12FF7E, //FF75 //TVAR_wbt_pBaseCcms[69]
+0x0F1200EC, //00FB //TVAR_wbt_pBaseCcms[70]
+0x0F1200F2, //00F0 //TVAR_wbt_pBaseCcms[71]
+
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[72]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[73]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[74]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[75]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[76]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[77]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[78]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[79]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[80]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[81]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[82]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[83]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[84]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[85]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[86]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[87]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[88]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[89]
+          
+0x0F120111, //0114 //TVAR_wbt_pBaseCcms[90]
+0x0F12FFB5, //FFAC //TVAR_wbt_pBaseCcms[91]
+0x0F120000, //FFFB //TVAR_wbt_pBaseCcms[92]
+0x0F12FF26, //FF1D //TVAR_wbt_pBaseCcms[93]
+0x0F120179, //0182 //TVAR_wbt_pBaseCcms[94]
+0x0F12FF4B, //FF40 //TVAR_wbt_pBaseCcms[95]
+0x0F12FFE1, //FFD8 //TVAR_wbt_pBaseCcms[96]
+0x0F12FFF0, //FFE9 //TVAR_wbt_pBaseCcms[97]
+0x0F120151, //0155 //TVAR_wbt_pBaseCcms[98]
+0x0F120099, //009A //TVAR_wbt_pBaseCcms[99]
+0x0F12008C, //008B //TVAR_wbt_pBaseCcms[100]
+0x0F12FF28, //FF1C //TVAR_wbt_pBaseCcms[101]
+0x0F1200C4, //00C2 //TVAR_wbt_pBaseCcms[102]
+0x0F12FF7A, //FF6E //TVAR_wbt_pBaseCcms[103]
+0x0F120134, //0137 //TVAR_wbt_pBaseCcms[104]
+0x0F12FF85, //FF79 //TVAR_wbt_pBaseCcms[105]
+0x0F120105, //0106 //TVAR_wbt_pBaseCcms[106]
+0x0F1200F2, //00F1 //TVAR_wbt_pBaseCcms[107]
+//	param_end	TVAR_wbt_pBasecms 
+
+
+0x002A07CC,
+0x0F1240D8, //#TVAR_wbt_pOutdoorCcm
+0x0F127000,
+
+//	param_start	TVAR_wbt_pOutdoorCcm
+0x002A40D8,
+0x0F1201BE, //0205 //01F8 //TVAR_wbt_pOutdoorCcm[0]
+0x0F12FFE4, //FF96 //FFAF //TVAR_wbt_pOutdoorCcm[1]
+0x0F120000, //FFDF //FFD3 //TVAR_wbt_pOutdoorCcm[2]
+0x0F12FEF9, //FEC8 //FEC4 //TVAR_wbt_pOutdoorCcm[3]
+0x0F120149, //01A4 //0191 //TVAR_wbt_pOutdoorCcm[4]
+0x0F12FF70, //FF1C //FF33 //TVAR_wbt_pOutdoorCcm[5]
+0x0F12003C, //FFF7 //FFED //TVAR_wbt_pOutdoorCcm[6]
+0x0F120023, //000C //0017 //TVAR_wbt_pOutdoorCcm[7]
+0x0F1201DD, //0211 //0210 //TVAR_wbt_pOutdoorCcm[8]
+0x0F1200D4, //0107 //00E3 //TVAR_wbt_pOutdoorCcm[9]
+0x0F1200F8, //00F3 //0107 //TVAR_wbt_pOutdoorCcm[10]
+0x0F12FF74, //FF1F //FF2F //TVAR_wbt_pOutdoorCcm[11]
+0x0F120212, //0220 //0220 //TVAR_wbt_pOutdoorCcm[12]
+0x0F120039, //FFE7 //FFE7 //TVAR_wbt_pOutdoorCcm[13]
+0x0F120184, //01A1 //01A1 //TVAR_wbt_pOutdoorCcm[14]
+0x0F12FF28, //FEC7 //FEC8 //TVAR_wbt_pOutdoorCcm[15]
+0x0F120133, //016D //017D //TVAR_wbt_pOutdoorCcm[16]
+0x0F120153, //0153 //0142 //TVAR_wbt_pOutdoorCcm[17]
+//	param_end	TVAR_wbt_pOutdoorCcm
+
+0x002A2A64,
+0x0F120001, //#MVAR_AAIO_bFIT
+0x002A2A68,
+0x0F120001, //#MVAR_AAIO_bAutoCCMandASH
+0x002A2A3C,
+0x0F1201DD, //#Mon_AAIO_PrevFrmData_NormBr
+
+//===================================================================
+// AFIT
+//===================================================================
+
+//	param_start	afit_uNoiseIndInDoor
+0x002A085C,
+0x0F12004A, /*0049 //#afit_uNoiseIndInDoor_0_*/
+0x0F12004E, /*/005F //#afit_uNoiseIndInDoor_1_*/
+0x0F1200CB, //00CB //#afit_uNoiseIndInDoor_2_
+0x0F1201C0, //01E0 //#afit_uNoiseIndInDoor_3_
+0x0F120200, //0220 //#afit_uNoiseIndInDoor_4_
+
+
+0x002A08C0,
+0x0F120030, /*0007 //700008C0 //AFIT16_BRIGHTNESS*/
+0x0F120000, //0000 //700008C2 //AFIT16_CONTRAST
+0x0F120010, /* 0000 //700008C4 //AFIT16_SATURATION*/
+0x0F12FFD8, /* 0000 //700008C6 //AFIT16_SHARP_BLUR */
+0x0F120000, //0000 //700008C8 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700008CA //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700008CC 
+0x0F1203FF, //03FF //700008CE //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700008D0 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700008D2 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700008D4 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700008D6 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700008D8 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700008DA //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700008DC //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700008DE //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700008E0 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700008E2 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0010 //700008E4 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0010 //700008E6 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //01F4 //700008E8 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //003C //700008EA //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0008 //700008EC //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700008EE //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700008F0 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700008F2 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700008F4 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700008F6 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700008F8 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700008FA //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700008FC //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700008FE //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000900 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000902 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000904 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //09E8 //70000906 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000908 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //7000090A //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //7000090C //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //4000 //7000090E 
+0x0F125003, //7803 //70000910 
+0x0F123228, //3C50 //70000912 
+0x0F120032, //003C //70000914 
+0x0F121E80, //1E80 //70000916 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000918 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //7000091A //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //7000091C //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //7000091E //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //0F00 //70000920 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000922 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000924 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000926 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000928 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //7000092A //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //7000092C //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //7000092E //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000930 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000932 
+0x0F120609, //0609 //70000934 
+0x0F122C07, //2C07 //70000936 
+0x0F12142C, //142C //70000938 
+0x0F120518, //0718 //7000093A //[15:8]iUVNRStrengthL [7:0]iMaxThreshH
+0x0F128005, //8007 //7000093C //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594,
+0x0F120080,
+0x0F120080,
+0x0F120101, //0101 //70000944 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000946 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4601 //70000948 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B,
+0x0F125038,
+0x0F120500, //0500 //7000094E //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0003 //70000950 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //1C01 //70000952 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //0714 //70000954 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432,
+0x0F125F01, //5A04 //70000958 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //3C1E //7000095A //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //400F //7000095C //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //7000095E //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1403 //70000960 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0114 //70000962 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000964 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //4446 //70000966 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //646E //70000968 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //7000096A //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //7000096C //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //7000096E //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000970 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000972 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000974 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000976 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000978 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //7000097A //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //7000097C //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1414 //7000097E //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000980 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //4601 //70000982 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //6E44 //70000984 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2864 //70000986 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000988 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //7000098A //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //7000098C //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //7000098E //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000990 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000992 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000994 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000996 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000998 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //7000099A //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //7000099C 
+0x0F120030, /*0000 //7000099E //AFIT16_BRIGHTNESS*/
+0x0F120000, //0000 //700009A0 //AFIT16_CONTRAST
+0x0F120010, /*0000 //700009A2 //AFIT16_SATURATION*/
+0x0F120000, //0000 //700009A4 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //700009A6 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //700009A8 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //700009AA 
+0x0F1203FF, //03FF //700009AC //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //700009AE //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //700009B0 //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //700009B2 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //700009B4 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //700009B6 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //700009B8 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //700009BA //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //700009BC //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //700009BE //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //700009C0 //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //700009C2 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //700009C4 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //700009C6 //AFIT16_demsharpmix1_iHystCenter
+0x0F12006E, //006E //700009C8 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //700009CA //AFIT16_Sharpening_iHighSharpClamp
+0x0F12006E, //003C //700009CC //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //700009CE //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12006E, //003C //700009D0 //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //700009D2 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //700009D4 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //700009D6 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //700009D8 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //700009DA //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //700009DC //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //700009DE //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //700009E0 //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //700009E2 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205E8, //05E8 //700009E4 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //700009E6 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //700009E8 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //700009EA //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F122000, //2000 //700009EC        
+0x0F125003, //5003 //700009EE        
+0x0F123228, //3228 //700009F0        
+0x0F120032, //0032 //700009F2        
+0x0F121E80, //1E80 //700009F4 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //700009F6 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12000A, //000A //700009F8 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120000, //0000 //700009FA //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12270A, //120A //700009FC //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F120010, //1400 //700009FE //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120200, //0200 //70000A00 //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000A02 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000A04 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000A06 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000A08 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000A0A //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000A0C //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000A0E //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000A10        
+0x0F120609, //0609 //70000A12        
+0x0F122C07, //2C07 //70000A14        
+0x0F12142C, //142C //70000A16        
+0x0F120518, //0518 //70000A18 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000A1A //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120594,
+0x0F120080,
+0x0F120080, //0080 //70000A20 //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000A22 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000A24 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000A26 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12314B, //444B 494B //70000A28 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125038, //503C 5044 //70000A2A //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000A2C //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F120903, //0503 //70000A2E //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F121003, //0D02 //70000A30 //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12071E, //071E //70000A32 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121432, //1432 //70000A34 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F125F01, //5A01 //70000A36 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F122829, //281E //70000A38 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F12200F, //200F //70000A3A //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000A3C //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //1E03 //70000A3E //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //011E //70000A40 //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000A42 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //3A3C //70000A44 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F124449, //585A //70000A46 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000A48 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000A4A //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120346, //0000 //70000A4C //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F121E0D, //141E //70000A4E //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF07 //70000A50 //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000A52 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F121E6A, //0000 //70000A54 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120F28, //0F0F //70000A56 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000A58 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000A5A //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F121E1E, //1E1E //70000A5C //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000A5E //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //3C01 //70000A60 //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12494B, //5A3A //70000A62 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125044, //2858 //70000A64 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000A66 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F124603, //0003 //70000A68 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D03, //1E00 //70000A6A //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12071E, //0714 //70000A6C //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121432, //32FF //70000A6E //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //0004 //70000A70 //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12281E, //0F00 //70000A72 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F12200F, //400F //70000A74 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000A76 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000A78 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000A7A 
+0x0F120000, //0000 //70000A7C //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000A7E //AFIT16_CONTRAST
+0x0F120000, //0000 //70000A80 //AFIT16_SATURATION
+0x0F120000, //0000 //70000A82 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000A84 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000A86 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000A88        
+0x0F1203FF, //03FF //70000A8A //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000A8C //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000A8E //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000A90 //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000A92 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000A94 //AFIT16_demsharpmix1_iHighThreshold
+0x0F12012C, //012C //70000A96 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000A98 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000A9A //AFIT16_demsharpmix1_iLowSat
+0x0F12005A, //005A //70000A9C //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000A9E //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000AA0 //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000AA2 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000AA4 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000AA6 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000AA8 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //003C //70000AAA //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //001E //70000AAC //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //003C //70000AAE //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //001E //70000AB0 //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000AB2 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000AB4 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000AB6 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000AB8 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000ABA //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000ABC //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000ABE //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000AC0 //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000AC2 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000AC4 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000AC6 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000AC8 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000ACA        
+0x0F122803, //2803 //70000ACC        
+0x0F12261E, //261E //70000ACE        
+0x0F120026, //0026 //70000AD0        
+0x0F121E80, //1E80 //70000AD2 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000AD4 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000AD6 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000AD8 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F124C0A, //3C0A //70000ADA //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122B12, //2300 //70000ADC //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000ADE //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000AE0 //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000AE2 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121B11, //1B11 //70000AE4 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000AE6 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000AE8 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000AEA //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120605, //0605 //70000AEC //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120307, //0307 //70000AEE        
+0x0F120609, //0609 //70000AF0        
+0x0F121C07, //1C07 //70000AF2        
+0x0F121014, //1014 //70000AF4        
+0x0F120510, //0510 //70000AF6 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000AF8 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000AFA //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080,
+0x0F120080, //0080 //70000AFE //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000B00 //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000B02 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000B04 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000B06 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000B08 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000B0A //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F121B03, //1C03 //70000B0C //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F123003, //0D0C //70000B0E //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000B10 //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000B12 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F128601, //6401 //70000B14 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12283E, //282D //70000B16 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000B18 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000B1A //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //2803 //70000B1C //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //0128 //70000B1E //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000B20 //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //2224 //70000B22 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //3236 //70000B24 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000B26 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000B28 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0410 //70000B2A //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //141E //70000B2C //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122807, //FF07 //70000B2E //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000B30 //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4050 //70000B32 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //0F0F //70000B34 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000B36 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000B38 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F122828, //2828 //70000B3A //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000B3C //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //2401 //70000B3E //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //3622 //70000B40 //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //2832 //70000B42 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000B44 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1003 //70000B46 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1E04 //70000B48 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //0714 //70000B4A //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000B4C //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5004 //70000B4E //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0F40 //70000B50 //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //400F //70000B52 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000B54 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000B56 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000B58        
+0x0F120000, //0000 //70000B5A //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //70000B5C //AFIT16_CONTRAST
+0x0F120000, //0000 //70000B5E //AFIT16_SATURATION
+0x0F120000, //0000 //70000B60 //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //70000B62 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //70000B64 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //70000B66 
+0x0F1203FF, //03FF //70000B68 //AFIT16_Demosaicing_iSatVal
+0x0F12009E, //009E //70000B6A //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F12017C, //017C //70000B6C //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //70000B6E //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //70000B70 //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //70000B72 //AFIT16_demsharpmix1_iHighThreshold
+0x0F1200C8, //00C8 //70000B74 //AFIT16_demsharpmix1_iLowBright
+0x0F1203E8, //03E8 //70000B76 //AFIT16_demsharpmix1_iHighBright
+0x0F120046, //0046 //70000B78 //AFIT16_demsharpmix1_iLowSat
+0x0F120050, //0050 //70000B7A //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //70000B7C //AFIT16_demsharpmix1_iTune
+0x0F120001, //0001 //70000B7E //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //70000B80 //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //70000B82 //AFIT16_demsharpmix1_iHystCenter
+0x0F12008C, //008C //70000B84 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //70000B86 //AFIT16_Sharpening_iHighSharpClamp
+0x0F12008C, //002D //70000B88 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //70000B8A //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F12008C, //002D //70000B8C //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //70000B8E //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //70000B90 //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //70000B92 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //70000B94 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F121403, //1403 //70000B96 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F120004, //0004 //70000B98 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120300, //0300 //70000B9A //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //70000B9C //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1202FF, //02FF //70000B9E //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F1205DE, //05DE //70000BA0 //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //70000BA2 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //70000BA4 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //70000BA6 //AFIT8_sddd8a_iSquaresRounding [7:0]
+0x0F121000, //1000 //70000BA8 
+0x0F122303, //2303 //70000BAA 
+0x0F12231A, //231A //70000BAC 
+0x0F120023, //0023 //70000BAE 
+0x0F121E80, //1E80 //70000BB0 //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E08, //1E08 //70000BB2 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12010A, //010A //70000BB4 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120001, //0001 //70000BB6 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F127D0A, //3C0A //70000BB8 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F122C24, //2300 //70000BBA //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120207, //0200 //70000BBC //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //70000BBE //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //70000BC0 //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //70000BC2 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //70000BC4 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //70000BC6 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //70000BC8 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //70000BCA //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120306, //0306 //70000BCC 
+0x0F120509, //0509 //70000BCE 
+0x0F122806, //2806 //70000BD0 
+0x0F121428, //1428 //70000BD2 
+0x0F120518, //0518 //70000BD4 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F128005, //8005 //70000BD6 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]
+0x0F120080, //0080 //70000BD8 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080,
+0x0F120080, //0080 //70000BDC //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F120101, //0101 //70000BDE //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120707, //0707 //70000BE0 //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F124B01, //4B01 //70000BE2 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F12144B, //2A4B //70000BE4 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F125014, //5020 //70000BE6 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120500, //0500 //70000BE8 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F122B03, //1C03 //70000BEA //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F126303, //0D0C //70000BEC //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F120823, //0823 //70000BEE //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F121428, //1428 //70000BF0 //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12CC01, //6401 //70000BF2 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]                         
+0x0F12283E, //282D //70000BF4 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F122012, //2012 //70000BF6 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120204, //0204 //70000BF8 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F120103, //3C03 //70000BFA //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120701, //013C //70000BFC //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //70000BFE //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F124B4B, //1C1E //70000C00 //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1E22 //70000C02 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120050, //0028 //70000C04 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F120305, //030A //70000C06 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F120C5C, //0214 //70000C08 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F12230D, //0E14 //70000C0A //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F122808, //FF06 //70000C0C //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120114, //0432 //70000C0E //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F122D74, //4052 //70000C10 //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //150C //70000C12 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120420, //0440 //70000C14 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120302, //0302 //70000C16 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F123C3C, //3C3C //70000C18 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //70000C1A //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F124B01, //1E01 //70000C1C //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F12004B, //221C //70000C1E //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F125000, //281E //70000C20 //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120500, //0A00 //70000C22 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125C03, //1403 //70000C24 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120D0C, //1402 //70000C26 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F120823, //060E //70000C28 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121428, //32FF //70000C2A //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F127401, //5204 //70000C2C //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F12082D, //0C40 //70000C2E //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F122009, //4015 //70000C30 //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120204, //0204 //70000C32 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120003, //0003 //70000C34 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //70000C36 
+0x0F120000, //0000 //0000 //70000C38 //AFIT16_BRIGHTNESS
+0x0F120000, //0000 //0000 //70000C3A //AFIT16_CONTRAST
+0x0F120000, //0000 //0000 //70000C3C //AFIT16_SATURATION
+0x0F120000, //0000 //0000 //70000C3E //AFIT16_SHARP_BLUR
+0x0F120000, //0000 //0000 //70000C40 //AFIT16_GLAMOUR
+0x0F1200C1, //00C1 //00C1 //70000C42 //AFIT16_sddd8a_edge_high
+0x0F120000, //0000 //0000 //70000C44
+0x0F1203FF, //03FF //03FF //70000C46 //AFIT16_Demosaicing_iSatVal
+0x0F12009C, //009C //0008 //70000C48 //AFIT16_Sharpening_iReduceEdgeThresh
+0x0F120251, //0251 //017C //70000C4A //AFIT16_demsharpmix1_iRGBOffset
+0x0F1203FF, //03FF //03FF //70000C4C //AFIT16_demsharpmix1_iDemClamp
+0x0F12000C, //000C //000C //70000C4E //AFIT16_demsharpmix1_iLowThreshold
+0x0F120010, //0010 //0010 //70000C50 //AFIT16_demsharpmix1_iHighThreshold
+0x0F120032, //0032 //0032 //70000C52 //AFIT16_demsharpmix1_iLowBright
+0x0F12028A, //028A //028A //70000C54 //AFIT16_demsharpmix1_iHighBright
+0x0F120032, //0032 //0032 //70000C56 //AFIT16_demsharpmix1_iLowSat
+0x0F1201F4, //01F4 //01F4 //70000C58 //AFIT16_demsharpmix1_iHighSat
+0x0F120070, //0070 //0070 //70000C5A //AFIT16_demsharpmix1_iTune
+0x0F120002, //0002 //0002 //70000C5C //AFIT16_demsharpmix1_iHystThLow
+0x0F120000, //0000 //0000 //70000C5E //AFIT16_demsharpmix1_iHystThHigh
+0x0F120320, //0320 //0320 //70000C60 //AFIT16_demsharpmix1_iHystCenter
+0x0F120044, //0044 //0070 //70000C62 //AFIT16_Sharpening_iLowSharpClamp
+0x0F120014, //0014 //0014 //70000C64 //AFIT16_Sharpening_iHighSharpClamp
+0x0F120044, //0046 //0046 //70000C66 //AFIT16_Sharpening_iLowSharpClamp_Bin
+0x0F120014, //0019 //0019 //70000C68 //AFIT16_Sharpening_iHighSharpClamp_Bin
+0x0F120044, //0046 //0046 //70000C6A //AFIT16_Sharpening_iLowSharpClamp_sBin
+0x0F120014, //0019 //0019 //70000C6C //AFIT16_Sharpening_iHighSharpClamp_sBin
+0x0F120A24, //0A24 //0A24 //70000C6E //AFIT8_sddd8a_edge_low [7:0] AFIT8_sddd8a_repl_thresh [15:8]
+0x0F121701, //1701 //1701 //70000C70 //AFIT8_sddd8a_repl_force [7:0] AFIT8_sddd8a_sat_level [15:8]
+0x0F120229, //0229 //0229 //70000C72 //AFIT8_sddd8a_sat_thr[7:0] AFIT8_sddd8a_sat_mpl [15:8]
+0x0F120503, //0503 //0503 //70000C74 //AFIT8_sddd8a_sat_noise[7:0] AFIT8_sddd8a_iMaxSlopeAllowed [15:8]
+0x0F12080F, //080F //0101 //70000C76 //AFIT8_sddd8a_iHotThreshHigh[7:0] AFIT8_sddd8a_iHotThreshLow [15:8]
+0x0F120808, //0808 //0101 //70000C78 //AFIT8_sddd8a_iColdThreshHigh[7:0] AFIT8_sddd8a_iColdThreshLow [15:8]
+0x0F120000, //0000 //0000 //70000C7A //AFIT8_sddd8a_AddNoisePower1[7:0] AFIT8_sddd8a_AddNoisePower2 [15:8]
+0x0F1200FF, //00FF //02FF //70000C7C //AFIT8_sddd8a_iSatSat[7:0] AFIT8_sddd8a_iRadialTune [15:8]
+0x0F12012D, //012D //0396 //70000C7E //AFIT8_sddd8a_iRadialLimit [7:0] AFIT8_sddd8a_iRadialPower [15:8]
+0x0F121414, //1414 //1414 //70000C80 //AFIT8_sddd8a_iLowMaxSlopeAllowed [7:0] AFIT8_sddd8a_iHighMaxSlopeAllowed [15:8]
+0x0F120301, //0301 //0301 //70000C82 //AFIT8_sddd8a_iLowSlopeThresh[7:0] AFIT8_sddd8a_iHighSlopeThresh [15:8]
+0x0F120007, //0007 //0007 //70000C84 //AFIT8_sddd8a_iSquaresRounding [7:0]                        
+0x0F121000, //1000 //1000 //70000C86 
+0x0F122003, //2003 //2003 //70000C88 
+0x0F121020, //1020 //1020 //70000C8A 
+0x0F120010, //0010 //0010 //70000C8C 
+0x0F121EFF, //1EFF //1E80 //70000C8E //AFIT8_Demosaicing_iCentGrad[7:0] AFIT8_Demosaicing_iMonochrom[15:8]
+0x0F121E06, //1E06 //1E06 //70000C90 //AFIT8_Demosaicing_iDecisionThresh[7:0] AFIT8_Demosaicing_iDesatThresh[15:8]
+0x0F12060A, //060A //030C //70000C92 //AFIT8_Demosaicing_iEnhThresh[7:0] AFIT8_Demosaicing_iGRDenoiseVal[15:8]
+0x0F120306, //0306 //0103 //70000C94 //AFIT8_Demosaicing_iGBDenoiseVal[7:0] AFIT8_Demosaicing_iNearGrayDesat[15:8]
+0x0F12810A, //8B0A //5A0A //70000C96 //AFIT8_Demosaicing_iDFD_ReduceCoeff[7:0] AFIT8_Sharpening_iMSharpen[15:8]
+0x0F1215C4, //2837 //2D00 //70000C98 //AFIT8_Sharpening_iMShThresh[7:0] AFIT8_Sharpening_iWSharpen[15:8]
+0x0F120107, //0110 //0100 //70000C9A //AFIT8_Sharpening_iWShThresh[7:0] AFIT8_Sharpening_nSharpWidth[15:8]
+0x0F12FF00, //FF00 //FF00 //70000C9C //AFIT8_Sharpening_iReduceNegative[7:0] AFIT8_Sharpening_iShDespeckle[15:8]
+0x0F120200, //0200 //0200 //70000C9E //AFIT8_demsharpmix1_iRGBMultiplier[7:0] AFIT8_demsharpmix1_iFilterPower[15:8]
+0x0F121E10, //1E10 //1E10 //70000CA0 //AFIT8_demsharpmix1_iBCoeff[7:0] AFIT8_demsharpmix1_iGCoeff[15:8]
+0x0F120000, //0000 //0000 //70000CA2 //AFIT8_demsharpmix1_iWideMult[7:0] AFIT8_demsharpmix1_iNarrMult[15:8]
+0x0F120009, //0009 //0009 //70000CA4 //AFIT8_demsharpmix1_iHystFalloff[7:0] AFIT8_demsharpmix1_iHystMinMult[15:8]
+0x0F120406, //0406 //0406 //70000CA6 //AFIT8_demsharpmix1_iHystWidth[7:0] AFIT8_demsharpmix1_iHystFallLow[15:8]
+0x0F120705, //0705 //0705 //70000CA8 //AFIT8_demsharpmix1_iHystFallHigh[7:0] AFIT8_demsharpmix1_iHystTune[15:8]
+0x0F120305, //0305 //0305 //70000CAA 
+0x0F120609, //0609 //0609 //70000CAC 
+0x0F122C07, //2C07 //2C07 //70000CAE 
+0x0F12142C, //142C //142C //70000CB0 
+0x0F120B18, //0B18 //0B18 //70000CB2 //[15:8]iUVNRStrengthL [7:0]iMaxThreshH        
+0x0F12800B, //800B //800B //70000CB4 //[7:0]iUVNRStrengthH AFIT8_byr_cgras_iShadingPower[15:8]        
+0x0F120080, //0080 //0080 //70000CB6 //AFIT8_RGBGamma2_iLinearity [7:0]  AFIT8_RGBGamma2_iDarkReduce [15:8]
+0x0F120080,
+0x0F120080, //0080 //0080 //70000CBA //AFIT8_RGB2YUV_iRGBGain [7:0]   AFIT8_RGB2YUV_iSaturation [15:8]
+0x0F125050, //5050 //0101 //70000CBC //AFIT8_sddd8a_iClustThresh_H [7:0]  AFIT8_sddd8a_iClustThresh_C [15:8]
+0x0F120101, //0101 //0A0A //70000CBE //AFIT8_sddd8a_iClustMulT_H [7:0]   AFIT8_sddd8a_iClustMulT_C [15:8]
+0x0F123201, //3201 //3201 //70000CC0 //AFIT8_sddd8a_nClustLevel_H [7:0]   AFIT8_sddd8a_DispTH_Low [15:8]
+0x0F120032, //1832 //1428 //70000CC2 //AFIT8_sddd8a_DispTH_High [7:0]   AFIT8_sddd8a_iDenThreshLow [15:8]
+0x0F122100, //210C //100C //70000CC4 //AFIT8_sddd8a_iDenThreshHigh[7:0]   AFIT8_Demosaicing_iEdgeDesat [15:8]
+0x0F120A00, //0A00 //0500 //70000CC6 //AFIT8_Demosaicing_iEdgeDesatThrLow [7:0]   AFIT8_Demosaicing_iEdgeDesatThrHigh [15:8]
+0x0F125004, //1E04 //1E02 //70000CC8 //AFIT8_Demosaicing_iEdgeDesatLimit[7:0]  AFIT8_Demosaicing_iDemSharpenLow [15:8]
+0x0F12A400, //0A08 //040C //70000CCA //AFIT8_Demosaicing_iDemSharpenHigh[7:0]   AFIT8_Demosaicing_iDemSharpThresh [15:8]
+0x0F12070C, //070C //0828 //70000CCC //AFIT8_Demosaicing_iDemShLowLimit [7:0]   AFIT8_Demosaicing_iDespeckleForDemsharp [15:8]
+0x0F123264, //3264 //5064 //70000CCE //AFIT8_Demosaicing_iDemBlurLow[7:0]   AFIT8_Demosaicing_iDemBlurHigh [15:8]
+0x0F12F802, //5A02 //4605 //70000CD0 //AFIT8_Demosaicing_iDemBlurRange[7:0]   AFIT8_Sharpening_iLowSharpPower [15:8]
+0x0F12103E, //1040 //1E68 //70000CD2 //AFIT8_Sharpening_iHighSharpPower[7:0]   AFIT8_Sharpening_iLowShDenoise [15:8]
+0x0F124012, //4012 //201E //70000CD4 //AFIT8_Sharpening_iHighShDenoise [7:0]   AFIT8_Sharpening_iReduceEdgeMinMult [15:8]
+0x0F120604, //0604 //0604 //70000CD6 //AFIT8_Sharpening_iReduceEdgeSlope [7:0]  AFIT8_demsharpmix1_iWideFiltReduce [15:8]
+0x0F125006, //4606 //4606 //70000CD8 //AFIT8_demsharpmix1_iNarrFiltReduce [7:0]  AFIT8_sddd8a_iClustThresh_H_Bin [15:8]
+0x0F120150, //0146 //0146 //70000CDA //AFIT8_sddd8a_iClustThresh_C_Bin [7:0]   AFIT8_sddd8a_iClustMulT_H_Bin [15:8]
+0x0F120101, //0101 //0101 //70000CDC //AFIT8_sddd8a_iClustMulT_C_Bin [7:0]   AFIT8_sddd8a_nClustLevel_H_Bin [15:8]
+0x0F123232, //1C18 //1C18 //70000CDE //AFIT8_sddd8a_DispTH_Low_Bin [7:0]   AFIT8_sddd8a_DispTH_High_Bin [15:8]
+0x0F120000, //1819 //1819 //70000CE0 //AFIT8_sddd8a_iDenThreshLow_Bin [7:0]   AFIT8_sddd8a_iDenThreshHigh_Bin [15:8]
+0x0F120021, //0028 //0028 //70000CE2 //AFIT8_Demosaicing_iEdgeDesat_Bin[7:0]   AFIT8_Demosaicing_iEdgeDesatThrLow_Bin [15:8]
+0x0F12040A, //030A //030A //70000CE4 //AFIT8_Demosaicing_iEdgeDesatThrHigh_Bin [7:0]  AFIT8_Demosaicing_iEdgeDesatLimit_Bin [15:8]
+0x0F12085E, //0514 //0514 //70000CE6 //AFIT8_Demosaicing_iDemSharpenLow_Bin [7:0]  AFIT8_Demosaicing_iDemSharpenHigh_Bin [15:8]
+0x0F120C0A, //0C14 //0C14 //70000CE8 //AFIT8_Demosaicing_iDemSharpThresh_Bin [7:0]  AFIT8_Demosaicing_iDemShLowLimit_Bin [15:8]
+0x0F123207, //FF05 //FF05 //70000CEA //AFIT8_Demosaicing_iDespeckleForDemsharp_Bin [7:0]  AFIT8_Demosaicing_iDemBlurLow_Bin [15:8]
+0x0F120119, //0432 //0432 //70000CEC //AFIT8_Demosaicing_iDemBlurHigh_Bin [7:0]  AFIT8_Demosaicing_iDemBlurRange_Bin [15:8]
+0x0F12406A, //4052 //4052 //70000CEE //AFIT8_Sharpening_iLowSharpPower_Bin [7:0]  AFIT8_Sharpening_iHighSharpPower_Bin [15:8]
+0x0F120908, //1514 //1514 //70000CF0 //AFIT8_Sharpening_iLowShDenoise_Bin [7:0]  AFIT8_Sharpening_iHighShDenoise_Bin [15:8]
+0x0F120440, //0440 //0440 //70000CF2 //AFIT8_Sharpening_iReduceEdgeMinMult_Bin [7:0]  AFIT8_Sharpening_iReduceEdgeSlope_Bin [15:8]
+0x0F120606, //0302 //0302 //70000CF4 //AFIT8_demsharpmix1_iWideFiltReduce_Bin [7:0]  AFIT8_demsharpmix1_iNarrFiltReduce_Bin [15:8]
+0x0F124646, //4646 //4646 //70000CF6 //AFIT8_sddd8a_iClustThresh_H_sBin[7:0]   AFIT8_sddd8a_iClustThresh_C_sBin [15:8]
+0x0F120101, //0101 //0101 //70000CF8 //AFIT8_sddd8a_iClustMulT_H_sBin [7:0]   AFIT8_sddd8a_iClustMulT_C_sBin [15:8]
+0x0F123201, //1801 //1801 //70000CFA //AFIT8_sddd8a_nClustLevel_H_sBin [7:0]   AFIT8_sddd8a_DispTH_Low_sBin [15:8]
+0x0F120032, //191C //191C //70000CFC //AFIT8_sddd8a_DispTH_High_sBin [7:0]   AFIT8_sddd8a_iDenThreshLow_sBin [15:8]
+0x0F122100, //2818 //2818 //70000CFE //AFIT8_sddd8a_iDenThreshHigh_sBin[7:0]   AFIT8_Demosaicing_iEdgeDesat_sBin [15:8]
+0x0F120A00, //0A00 //0A00 //70000D00 //AFIT8_Demosaicing_iEdgeDesatThrLow_sBin [7:0]  AFIT8_Demosaicing_iEdgeDesatThrHigh_sBin [15:8]
+0x0F125E04, //1403 //1403 //70000D02 //AFIT8_Demosaicing_iEdgeDesatLimit_sBin [7:0]  AFIT8_Demosaicing_iDemSharpenLow_sBin [15:8]
+0x0F120A08, //1405 //1405 //70000D04 //AFIT8_Demosaicing_iDemSharpenHigh_sBin [7:0]  AFIT8_Demosaicing_iDemSharpThresh_sBin [15:8]
+0x0F12070C, //050C //050C //70000D06 //AFIT8_Demosaicing_iDemShLowLimit_sBin [7:0]  AFIT8_Demosaicing_iDespeckleForDemsharp_sBin [15:8]
+0x0F121932, //32FF //32FF //70000D08 //AFIT8_Demosaicing_iDemBlurLow_sBin [7:0]  AFIT8_Demosaicing_iDemBlurHigh_sBin [15:8]
+0x0F126A01, //5204 //5204 //70000D0A //AFIT8_Demosaicing_iDemBlurRange_sBin [7:0]  AFIT8_Sharpening_iLowSharpPower_sBin [15:8]
+0x0F120840, //1440 //1440 //70000D0C //AFIT8_Sharpening_iHighSharpPower_sBin [7:0]  AFIT8_Sharpening_iLowShDenoise_sBin [15:8]
+0x0F124009, //4015 //4015 //70000D0E //AFIT8_Sharpening_iHighShDenoise_sBin [7:0]  AFIT8_Sharpening_iReduceEdgeMinMult_sBin [15:8]
+0x0F120604, //0204 //0204 //70000D10 //AFIT8_Sharpening_iReduceEdgeSlope_sBin [7:0]  AFIT8_demsharpmix1_iWideFiltReduce_sBin [15:8]
+0x0F120006, //0003 //0003 //70000D12 //AFIT8_demsharpmix1_iNarrFiltReduce_sBin [7:0]
+0x0F120001, //0001 //0001 //70000D14
+
+0x0F12BA7A, //70000D16
+0x0F124FDE, //70000D18
+0x0F12137F, //70000D1A
+0x0F123BDE, //70000D1C
+0x0F12BF02, //70000D1E
+0x0F1200B5, //70000D20
+
+//===================================================================
+// Brightness setting
+//===================================================================
+0x002A1300,
+0x0F12019D,
+
+0x002A1306,
+0x0F120280,
+
+
+0x002a3fea,
+0x0f120800, //analog filter update Green
+
+/* TNP_Regs_bUseAccurateFR */
+/* 0x00287000, */
+/* 0x002A3FE4, */
+/* 0x0F120001, */ /* on/off TNP_Regs_bAccuDynamicFR */
+/* 0x0F1234A2, */ /* on/off TNP_Regs_usMinAccuDynamicFrTme */
+/* 0x0F1240FD, */ /* on/off TNP_Regs_usMaxAccuDynamicFrTme */
+};
+
+/* Return preview mode */
+static const u32 s5k5ccgx_preview_return[] =  {
+0xFCFCD000,
+0x00287000,
+
+0x002A085C,
+0x0F120040, //#afit_uNoiseIndInDoor_0_
+0x0F120048, //#afit_uNoiseIndInDoor_1_
+
+
+0x002A08C6,
+0x0F120002, //700008C6 //AFIT16_SHARP_BLUR
+0x0F120000, //700008C8 //AFIT16_GLAMOUR
+0x002A09A4,            
+0x0F120002, //700009A4 //AFIT16_SHARP_BLUR   
+0x0F120000, //700009A6 //AFIT16_GLAMOUR 
+                       
+0x002A08E4,            
+0x0F120001,	//700008E4 //AFIT16_demsharpmix1_iHystThLow
+                  
+0x002A0C7E,
+0x0F120396, //70000C7E//AFIT8_sddd8a_iRadialLimit [7:0], AFIT8_sddd8a_iRadialPower [15:8]
+
+0x002A0CC4,
+0x0F12100C, //70000CC4//AFIT8_sddd8a_iDenThreshHigh[7:0],   AFIT8_Demosaicing_iEdgeDesat [15:8]
+
+0x002A0D1E,
+0x0F122102, //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+/* 2048x1536 capture (Capture config0) */
+static const u32 s5k5ccgx_snapshot[] =
+{
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+	0xFFFF00A0,   //160ms
+};
+
+/* 640x480 capture (Capture config1) */
+static const u32 s5k5ccgx_snapshot_vga[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120001,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF00A0,   //160ms
+};
+
+/* Write lowlight-regs before writing snapshot-regs
+ * in case of lowlight capture. */
+static const u32 s5k5ccgx_set_lowlight_reg[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A085C,
+0x0F12004A, //0049 //#afit_uNoiseIndInDoor_0_
+0x0F12004E, //005F //#afit_uNoiseIndInDoor_1_
+
+0x002A08C6,
+0x0F120000, //700008C6//AFIT16_SHARP_BLUR
+0x0F120010, //700008C8//AFIT16_GLAMOUR
+0x002A09A4,   
+0x0F120000, //700009A4//AFIT16_SHARP_BLUR   
+0x0F120010, //700009A6//AFIT16_GLAMOUR
+
+0x002A08E4,
+0x0F120010,	//700008E4//AFIT16_demsharpmix1_iHystThLow
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+
+0xFFFF012C,   //300ms
+};
+
+/* Not used */
+static const u32 s5k5ccgx_night_snapshot_off[] = {
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_normal_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_flash_lowlight_snapshot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0D1E,
+0x0F12A102,	//70000D1E
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120001,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* For 2048x1152 cap */
+static const u32 s5k5ccgx_change_wide_cap[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_PrevInputHeightOfs (600h-480h)/2
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120480,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F1200C0,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120480,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F1200C0,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120240,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120480,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+/* To change Wide Capture to Normal Capture,
+ * We have to restore capture configuration before starting Normal Capture.
+ */
+static const u32 s5k5ccgx_restore_capture_reg[] = {
+//================================
+// 17.Input Size Setting
+//================================
+
+0x00287000,
+0x002A01F6,
+0x0F120800,	//REG_TC_GP_PrevReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_PrevReqInputHeight //600h=1536d
+0x0F120000,	//REG_TC_GP_PrevInputWidthOfs
+0x0F120000,	//REG_TC_GP_PrevInputHeightOfs
+0x0F120800,	//REG_TC_GP_CapReqInputWidth //800h=2048d
+0x0F120600,	//REG_TC_GP_CapReqInputHeight //600h=1536
+0x0F120000,	//REG_TC_GP_CapInputWidthOfs
+0x0F120000,	//REG_TC_GP_CapInputHeightOfs
+0x002A0216,
+0x0F120001,	//REG_TC_GP_bUseReqInputInPre
+0x0F120001,	//REG_TC_GP_bUseReqInputInCap
+0x002A043C,
+0x0F120800,	//REG_TC_PZOOM_ZoomInputWidth //800h=2048d
+0x0F120600,	//REG_TC_PZOOM_ZoomInputHeight //600h=1536
+0x0F120000,	//REG_TC_PZOOM_ZoomInputWidthOfs
+0x0F120000,	//REG_TC_PZOOM_ZoomInputHeightOfs
+
+//================================
+// 18.Preview & Capture Configration Setting
+//================================
+
+//Preview Config  10fps~30fps
+0x002A023E,
+0x0F120400,	//REG_0TC_PCFG_usWidth //280h=640d
+0x0F120300,	//REG_0TC_PCFG_usHeight //1E0h=480d
+
+
+//Capture Config 0  2048x1536 7.5~15fps
+0x002A032E,
+0x0F120000,	//REG_0TC_CCFG_uCaptureMode
+0x0F120800,	//REG_0TC_CCFG_usWidth //800h=2048d
+0x0F120600,	//REG_0TC_CCFG_usHeight //600h=1536d
+};
+
+static const u32 s5k5ccgx_get_light_status[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A3C,
+};
+
+static const u32 s5k5ccgx_get_iso_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A18,
+};
+
+static const u32 s5k5ccgx_get_shutterspeed_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A14,
+};
+
+static const u32 s5k5ccgx_fps_auto[] = {
+0x00287000,
+0x002A025A,
+0x0F1203E8, //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+/* DSLIM.
+//PREVIEW
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnablePreview
+0x0F120001, //REG_TC_GP_EnablePreviewChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_15fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12029A,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12029A,	//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_25fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F120190, //14E,//REG_0TC_PCFG_usMaxFrTimeMsecMult10	//max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F120190, //14E,//REG_0TC_PCFG_usMinFrTimeMsecMult10	//min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+static const u32 s5k5ccgx_fps_30fix[] = {
+0xFCFCD000,
+0x00287000,
+0x002A025A,
+0x0F12014E, //REG_0TC_PCFG_usMaxFrTimeMsecMult10 //max frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+0x0F12014E, //REG_0TC_PCFG_usMinFrTimeMsecMult10 //min frame time : 30fps 014D 15fps 029a; a6a - 3.75 fps; 0535 - 7.5FPS
+
+/* DSLIM.
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+*/
+};
+
+/* effect off = normal */
+static const u32 s5k5ccgx_effect_off[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A0648,
+0x0F120001,	//skl_af_bPregmOff	Pre/Post Gamma Off (¿øº¹)
+
+0x002A01E2,
+0x0F120000,	//REG_TC_GP_SpecialEffects	00:Normal Mode
+};
+
+static const u32 s5k5ccgx_effect_mono[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120001, /* REG_TC_GP_SpecialEffects	01:Mono Mode */
+};
+
+static const u32 s5k5ccgx_effect_sepia[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120004, /* REG_TC_GP_SpecialEffects	04:Sepia Mode */
+};
+
+static const u32 s5k5ccgx_effect_negative[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01E2,
+0x0F120003,//REG_TC_GP_SpecialEffects	03:Negative Mode
+};
+
+static const u32 s5k5ccgx_wb_auto[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,	//Mon_AAIO_bAWB		AWB ON
+};
+
+static const u32 s5k5ccgx_wb_daylight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120620,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120540,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_cloudy[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F1207B0, //REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F12046A, //REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_fluorescent[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120560,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F1208A0,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_wb_incandescent[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F1203C0,	//REG_SF_USER_Rgain
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120980,	//REG_SF_USER_Bgain
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_brightness_m_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12001A, //16 //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120020, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12002A, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_m_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120034, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_0[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12003E, //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_1[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120054,//TVAR_ae_BrAves
+
+};
+
+static const u32 s5k5ccgx_brightness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F12006C,//6E //TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_3[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120080,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_brightness_p_4[] = {
+0xFCFCD000,
+0x00287000,
+
+0x002A1308,
+0x0F120090, //9B, //E,//TVAR_ae_BrAve
+
+};
+
+static const u32 s5k5ccgx_scene_off[] = {
+// ==========================================================
+//	CAMERA_SCENE_OFF
+// ==========================================================
+/*
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120001,		//Mon_AAIO_bAWB		0: AWB OFF, 1: AWB ON
+*/
+
+// Center (Metering)
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+
+//	01. Portait / Landscape / Text / Fall Color Off
+
+0x00287000,
+0x002A1308,
+0x0F12003E,	//TVAR_ae_BrAve
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x0F120000,	//REG_TC_UserContrast
+0x002A01D4,
+0x0F120000,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//	02. Night / Firework Off
+0x00287000,
+0x002A025A,
+0x0F1203E8,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+0x0F12014E,	//REG_0TC_PCFG_usMinFrTimeMsecMult10
+
+0x002A034C,
+0x0F120535,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F12029A,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120010,	// 0010 ae_GainIn_0_	//
+0x0F120020,	// 0020	ae_GainIn_1_	//
+0x0F120040,	// 0040	ae_GainIn_2_	//
+0x0F120080,	// 0080	ae_GainIn_3_	//
+0x0F120100,	// fix 0100	ae_GainIn_4_	//
+0x0F120200,	// 0200	ae_GainIn_5_	//
+0x0F120400,	// 0400	ae_GainIn_6_	//
+0x0F120800,	// 0800	ae_GainIn_7_	//
+0x0F122000,	// 2000	ae_GainIn_8_	//
+
+0x0F120010,	//0050//0010	ae_GainOut_0_	p	//
+0x0F120020,	//0070//0020	ae_GainOut_1_ p//
+0x0F120040,	//00A0//0040	ae_GainOut_2_	p	//
+0x0F120080,	//00D0//0080	ae_GainOut_3_	p	//
+0x0F120100,	//fix 0100	ae_GainOut_4_		//
+0x0F120200,	//0200	ae_GainOut_5_	//
+0x0F120400,	//0400	ae_GainOut_6_	//
+0x0F120800,	//0800	ae_GainOut_7_	//
+0x0F122000,	//2000	ae_GainOut_8_	//
+
+
+0x00287000,
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1	3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2	681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3	8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4	C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1	3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2	681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3	8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4	C350h = 50000d = 125.0000ms
+0x0F120000,
+
+0x002A0524,
+0x0F120200, //1E0 //lt_uMaxAnGain1
+0x0F120200, //1E0 //lt_uMaxAnGain2
+0x0F120300,	//lt_uMaxAnGain3
+0x0F120840,	//lt_uMaxAnGain4
+
+0x0F120100,	//lt_uMaxDigGain
+0x0F128000,	//lt_uMaxTotGain
+
+0x0F120200, //1E0 //lt_uCapMaxAnGain1
+0x0F120200, //1E0 //lt_uCapMaxAnGain2
+0x0F120300,	//lt_uCapMaxAnGain3
+0x0F120710,	//lt_uCapMaxAnGain4
+
+0x0F120100,	//lt_uCapMaxDigGain
+0x0F128000,	//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120010,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120010,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F120B50,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+
+//	03. ISO Auto
+
+0x002A04A4,
+0x0F12067F,	//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+#if 0 /* DSLIM */
+/* 0x002A048C,*/
+/* 0x0F120001,*/	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+/* 0x0F120001,*/	//REG_SF_USER_FlickerQuantChanged
+#endif
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+0x002A0486,
+0x0F120000,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_portrait[] = {
+// ==========================================================
+//	CAMERA_SCENE_PORTRAIT (Auto/Center/Br0/Auto/Sharp-1/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,	//REG_TC_UserSaturation
+0x0F12FFF6,	//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_landscape[] = {
+// ==========================================================
+//	CAMERA_SCENE_LANDSCAPE (Auto/Matrix/Br0/Auto/Sharp+1/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F12000A,	//REG_TC_UserSharpBlur
+
+0x002A1316,	//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_scene_sports[] = {
+// ==========================================================
+//  CAMERA_SCENE_SPORTS (Sport/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+
+0x002A04EE,
+0x0F120112, /*lt_uLimitHigh */
+0x0F1200EE, /*lt_uLimitLow */
+
+0x002A0504,
+0x0F120002, /*lt_uMaxExp1  3415h = 13333d =  33.3325ms */
+0x002A0508,
+0x0F120D05, /*lt_uMaxExp2  3415h = 13333d =  33.3325ms */
+0x002A050C,
+0x0F121A0A, /*lt_uMaxExp3  3415h = 13333d =  33.3325ms */
+0x002A0510,
+0x0F123415, /*lt_uMaxExp4  3415h = 13333d =  33.3325ms */
+
+0x002A0514,
+0x0F120002, /*lt_uCapMaxExp1  3415h = 13333d =  33.3325ms */
+0x002A0518,
+0x0F120D05, /*lt_uCapMaxExp2  3415h = 13333d =  33.3325ms */
+0x002A051C,
+0x0F121A0A, /*lt_uCapMaxExp3  3415h = 13333d =  33.3325ms */
+0x002A0520,
+0x0F123415, /*lt_uCapMaxExp4  3415h = 13333d =  33.3325ms */
+
+0x002A0524,
+0x0F120200, /*#lt_uMaxAnGain1 */
+0x0F120200, /*#lt_uMaxAnGain2 */
+0x0F120200, /*#lt_uMaxAnGain3 */
+0x0F120200, /*#lt_uMaxAnGain4 */
+
+0x0F120200, /*#lt_uMaxDigGain */
+0x0F128000, /*#lt_uMaxTotGain  Total-gain is limited by #lt_uMaxTotGain */
+
+0x0F120200, /*#lt_uCapMaxAnGain1 */
+0x0F120200, /*#lt_uCapMaxAnGain2 */
+0x0F120200, /*#lt_uCapMaxAnGain3 */
+0x0F120200, /*#lt_uCapMaxAnGain4 */
+
+0x0F120200, /*#lt_uCapMaxDigGain */
+0x0F128000, /*#lt_uCapMaxTotGain  Total-gain is limited by #lt_uMaxTotGain */
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,
+
+//Preview
+0x002A0208,
+0x0F120000, //REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000, //REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001, //REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001, //REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001, //REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001, //REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000, //REG_TC_GP_EnableCapture
+0x0F120001, //REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_party[] = {
+// ==========================================================
+//	CAMERA_SCENE_PARTYINDOOR (ISO200/Center/Br0/Auto/Sharp0/Sat+1)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//add ki 11.02.18
+// SLOW AE
+0x002A13F2,
+0x0F120030,	// 0010 ae_GainIn_0_//						
+0x0F120090,	// 0020	ae_GainIn_1_//					
+0x0F1200A8,	// 0040	ae_GainIn_2_//					
+0x0F1200C0,	// 0080	ae_GainIn_3_//					
+0x0F120100,	// fix 0100	ae_GainIn_4_//					
+0x0F120140,	// 0200	ae_GainIn_5_//					
+0x0F120180,	// 0400	ae_GainIn_6_//					
+0x0F120400,	// 0800	ae_GainIn_7_//					
+0x0F122000,	// 2000	ae_GainIn_8_//	
+
+0x0F120080,	//0050//0010	ae_GainOut_0_	p	//						
+0x0F1200D0,	//0070//0020	ae_GainOut_1_ p//						
+0x0F1200D8,	//00A0//0040	ae_GainOut_2_	p	//						
+0x0F1200f8,	//00D0//0080	ae_GainOut_3_	p	//						
+0x0F120100,	//fix 0100	ae_GainOut_4_		//						
+0x0F120103,	//0200	ae_GainOut_5_//						
+0x0F120110,	//0400	ae_GainOut_6_//						
+0x0F120150,	//0800	ae_GainOut_7_//						
+0x0F120400,	//2000	ae_GainOut_8_//		
+
+//ISO 200
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1	C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2	C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3	C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4	C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1 C350h = 50000d = 125.0000ms
+0x002A0518,                  
+0x0F12C350,	//lt_uCapMaxExp2 C350h = 50000d = 125.0000ms
+0x002A051C,                  
+0x0F12C350,	//lt_uCapMaxExp3 C350h = 50000d = 125.0000ms
+0x002A0520,                  
+0x0F12C350,	//lt_uCapMaxExp4 C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120180,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120300,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_beach[] = {
+// ==========================================================
+//	CAMERA_SCENE_BEACHSNOW (ISO50/Center/Br+1/Auto/Sharp0/Sat+1)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120020,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F12001E,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+//ISO 50
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120150,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_sunset[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120620, /* REG_SF_USER_Rgain */
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120540, /* REG_SF_USER_Bgain */
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_dawn[] = {
+// Use MWB CWF
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120560, /* REG_SF_USER_Rgain */
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F1208A0, /* REG_SF_USER_Bgain */
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+static const u32 s5k5ccgx_scene_fall[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,	//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120032,	//REG_TC_UserSaturation
+0x0F120000,	//REG_TC_UserSharpBlur
+
+};
+
+#if 0 /* P2 */
+static const u32 s5k5ccgx_scene_nightshot[] = {
+// ==========================================================
+// 	CAMERA_SCENE_NIGHT (Night/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F120682,	//9C4,4fps ->6fps //REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F121388,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F121388,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,		//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,		//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,		//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,		//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,		//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,		//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,		//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,		//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0524,
+0x0F1201D0,		//lt_uMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120B00,	//800  8¹è¿¡¼­ 11¹è·Î,		//lt_uMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,		//lt_uMaxDigGain
+0x0F128000,		//lt_uMaxTotGain
+
+0x0F1201D0,		//lt_uCapMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,		//lt_uCapMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,		//lt_uCapMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,		//lt_uCapMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,		//lt_uCapMaxDigGain
+0x0F128000,		//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120000,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120000,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F121080,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+#else
+
+static const u32 s5k5ccgx_scene_nightshot[] = {
+// ==========================================================
+//	CAMERA_SCENE_NIGHT (Night/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F120682, /* REG_0TC_PCFG_usMaxFrTimeMsecMult10*/
+
+0x002A034C,
+0x0F121388,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F121388,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,	//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,	//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0524,
+0x0F1201D0,	//lt_uMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,	//lt_uMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,	//lt_uMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,	//lt_uMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,	//lt_uMaxDigGain
+0x0F128000,	//lt_uMaxTotGain
+
+0x0F1201D0,	//lt_uCapMaxAnGain1		0180h	= 0384d	= x1.5000
+0x0F1201D0,	//lt_uCapMaxAnGain2		0180h	= 0384d	= x1.5000
+0x0F1202C0,	//lt_uCapMaxAnGain3		0250h	= 0592d	= x2.3125
+0x0F120800,	//lt_uCapMaxAnGain4		0710h	= 1808d	= x7.0625
+
+0x0F120100,	//lt_uCapMaxDigGain
+0x0F128000,	//lt_uCapMaxTotGain
+
+0x002A08E4,
+0x0F120000,	//AFIT16_demsharpmix1_iHystThLow
+0x0F120000,	//AFIT16_demsharpmix1_iHystThHigh
+0x002A0940,
+0x0F121080,	//[15:8] AFIT8_RGB2YUV_iYOffset, [7:0] AFIT8_ccm_oscar_iSaturation
+
+0x002A0D1E,
+0x0F122102,	//70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+#endif
+
+static const u32 s5k5ccgx_scene_backlight[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+/* Not Used */
+static const u32 s5k5ccgx_scene_firework[] = {
+// ==========================================================
+//	CAMERA_SCENE_FIREWORK (ISO50/Center/Br0/Auto/Sharp0/Sat0)
+// ==========================================================
+
+0xFCFCD000,
+0x00287000,
+
+0x002A025A,
+0x0F1209C4,	//REG_0TC_PCFG_usMaxFrTimeMsecMult10
+
+0x002A034C,
+0x0F122710,	//REG_0TC_CCFG_usMaxFrTimeMsecMult10
+0x0F122710,	//REG_0TC_CCFG_usMinFrTimeMsecMult10
+
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F121A80,	//lt_uMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F121A80,	//lt_uCapMaxExp4		00061A80h = 400000d =  1000ms
+0x0F120006,
+
+//ISO 50
+
+
+0x002A05EA,
+0x0F120150,		//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,		//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,		//REG_SF_USER_IsoVal
+0x0F120001,		//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,		//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0D1E,
+0x0F122102,	 //70000D1E
+
+//PREVIEW
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_scene_text[] = {
+// ==========================================================
+//	CAMERA_SCENE_TEXT (Auto/Center/Br0/Auto/Sharp+2/Sat0)
+// ==========================================================
+0xFCFCD000,
+0x00287000,
+0x002A01D0,
+0x0F120000,		//REG_TC_UserBrightness
+0x002A01D4,
+0x0F120000,		//REG_TC_UserSaturation
+0x0F120014,		//REG_TC_UserSharpBlur
+};
+
+static const u32 s5k5ccgx_scene_candle[] = {
+// Use MWB Daylight
+0xFCFCD000,
+0x00287000,
+0x002A2A62,
+0x0F120000,	//Mon_AAIO_bAWB		AWB OFF
+
+0x002A0470,
+0x0F120620, /* REG_SF_USER_Rgain */
+0x0F120001,	//REG_SF_USER_RgainChanged
+0x0F120400,	//REG_SF_USER_Ggain
+0x0F120001,	//REG_SF_USER_GgainChanged
+0x0F120540, /* REG_SF_USER_Bgain */
+0x0F120001,	//REG_SF_USER_BgainChaged
+};
+
+
+static const u32 s5k5ccgx_metering_normal[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+static const u32 s5k5ccgx_metering_spot[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120f01,
+0x0F12010f,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+};
+
+
+static const u32 s5k5ccgx_metering_center[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1316,		//ae_WeightTbl_16
+
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120000,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120201,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120101,
+0x0F120202,
+0x0F120202,
+0x0F120101,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120201,
+0x0F120202,
+0x0F120202,
+0x0F120102,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+0x0F120101,
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_auto[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12067F,	//REG_TC_DBG_AutoAlgEnBits		Auto Algorithm Enable
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F123415,	//lt_uMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0508,
+0x0F12681F,	//lt_uMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A050C,
+0x0F128227,	//lt_uMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F123415,	//lt_uCapMaxExp1		3415h = 13333d =  33.3325ms
+0x002A0518,
+0x0F12681F,	//lt_uCapMaxExp2		681Fh = 26655d =  66.6375ms
+0x002A051C,
+0x0F128227,	//lt_uCapMaxExp3		8227h = 33319d =  83.2975ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0486,
+0x0F120000,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x002A048A,
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+0x002A3302,
+0x0F120000,	//AFIT by Normalized Brightness Tunning Parameter
+
+//Preview
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_50[] = {
+
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120100,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_100[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120200,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_200[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120400,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+/* Not used */
+static const u32 s5k5ccgx_iso_400[] = {
+0xFCFCD000,
+0x00287000,
+
+//0002A167C,
+//00F120000,//senHal_ExpMinPixels
+
+0x002A04A4,
+0x0F12065F,	//REG_TC_DBG_AutoAlgEnBits		Auto Flicker Off
+0x002A048C,
+0x0F120001,	//REG_SF_USER_FlickerQuant		0:No AFC, 1:50Hz, 2:60Hz
+0x0F120001,	//REG_SF_USER_FlickerQuantChanged
+
+0x002A0504,
+0x0F12C350,	//lt_uMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0508,
+0x0F12C350,	//lt_uMaxExp2		C350h = 50000d = 125.0000ms
+0x002A050C,
+0x0F12C350,	//lt_uMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0510,
+0x0F12C350,	//lt_uMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A0514,
+0x0F12C350,	//lt_uCapMaxExp1		C350h = 50000d = 125.0000ms
+0x002A0518,
+0x0F12C350,	//lt_uCapMaxExp2		C350h = 50000d = 125.0000ms
+0x002A051C,
+0x0F12C350,	//lt_uCapMaxExp3		C350h = 50000d = 125.0000ms
+0x002A0520,
+0x0F12C350,	//lt_uCapMaxExp4		C350h = 50000d = 125.0000ms
+
+0x002A05EA,
+0x0F120100,	//lt_bUseSecISODgain
+
+// ISO Gain
+0x002A0486,
+0x0F120003,	//REG_SF_USER_IsoType		0:OFF 3:ISO
+0x0F120800,	//REG_SF_USER_IsoVal
+0x0F120001,	//REG_SF_USER_IsoChanged
+
+// AFIT by Normalized Brightness Tuning parameter
+0x002A3302,
+0x0F120001,	//AFIT by Normalized Brightness Tunning Parameter
+
+0x002A0208,
+0x0F120000,	//REG_TC_GP_ActivePrevConfig
+0x002A0210,
+0x0F120000,	//REG_TC_GP_ActiveCapConfig
+0x002A020C,
+0x0F120001,	//REG_TC_GP_PrevOpenAfterChange
+0x002A01F4,
+0x0F120001,	//REG_TC_GP_NewConfigSync
+0x002A020A,
+0x0F120001,	//REG_TC_GP_PrevConfigChanged
+0x002A0212,
+0x0F120001,	//REG_TC_GP_CapConfigChanged
+0x002A01E8,
+0x0F120000,	//REG_TC_GP_EnableCapture
+0x0F120001,	//REG_TC_GP_EnableCaptureChanged
+};
+
+static const u32 s5k5ccgx_ae_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120000, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_lock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12FFFF, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_ae_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A2A5A,
+0x0F120001, //Mon_AAIO_bAE
+};
+
+
+static const u32 s5k5ccgx_awb_unlock[] = {
+0xFCFCD000,
+0x00287000,
+0x002A11D6,
+0x0F12001E, //awbb_WpFilterMinThr
+};
+
+
+static const u32 s5k5ccgx_af_abort[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120001, // REG_TC_AF_AfCmd = 1, Abort A
+};
+
+static const u32 s5k5ccgx_af_off_reg[] = {
+	0xFCFCD000,
+	0x00287000,
+	0x002A0226,
+	0x0F120000,
+	0xFFFF0049, /* 73 ms delay,  Min 1 frame delay */
+	0x002A0224, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+	0x0F120004, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+	0xFFFF0118, /* 280ms Delay */
+};
+
+static const u32 s5k5ccgx_af_normal_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+0xFFFF0096, /* 150ms Delay */
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+0x002A1494,
+0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_night_normal_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120000, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro.*/
+
+0xFFFF00FA, /* 250ms Delay*/
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+0x002A1494,
+0x0F121002,
+};
+
+static const u32 s5k5ccgx_af_macro_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120004, /* write [7000 0224, REG_TC_AF_AfCmd] = 0004 , manual AF. */
+
+0x002A0226, /* write [7000 0226, REG_TC_AF_AfCmdParam] */
+0x0F120095, /* write lens position from 0000 to 00FF. 0000 means infinity and 00FF means macro. */
+
+0xFFFF0096, /* 150ms Delay */
+
+/* #af_search_usSingleAfFlags, 1040 : macro mode on,  2nd search off,
+1042 : macro mode on, 2nd search(fine search) on
+1000 : macro mode off, 2nd search off,
+1002 : macro mode off, 2nd search on */
+
+0x002A1494,
+0x0F121042,
+
+/* when user use lens position 16(10h) -> lens position 0(00h)
+MSB 10 b means user uses #af_pos_usTable_16_ as start position.
+LSB 00 b means user uses #af_pos_usTable_0_ as end position
+refer to 5.3 macro mode setting.
+"#af_pos_usMacroStartEnd" is only used in macro AF condition.
+(normal AF doesn't use "#af_pos_usMacroStartEnd") */
+0x002A1426,
+0x0F121000, /* #af_pos_usMacroStartEn */
+};
+
+static const u32 s5k5ccgx_af_do[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0224,
+0x0F120005,   // REG_TC_AF_AfCmd = 5, single A
+};
+
+static const u32 s5k5ccgx_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+static const u32 s5k5ccgx_1st_720P_af_do[] = {
+0xFCFCD000,
+0x00287000,
+
+0xFFFF01F4, /* tuning point */
+
+/* set AF operation value for 720P */
+0x002A0226,
+0x0F120010, /* REG_TC_AF_AfParam */
+
+/* 720P 1frame(50ms) delay  */
+0xFFFF0032, /* 50ms Delay */
+
+/* set AF start cmd value for 720P */
+0x002A0224,
+0x0F120006, /* REG_TC_AF_AfCmd = 5, single A */
+};
+
+#ifdef DEBUG_FILTER_DATA
+static const u32 s5k5ccgx_get_filter_data_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A1544,
+0x0F123000,
+0x0F127000,
+
+/* allocate memory */
+0x002A1540,
+0x0F120014,
+
+/* Select Focus value */
+0x002A1530,
+0x0F120000, /* 1530 addr */
+0x0F120000, /* 1532 addr */
+0x0F122010, /* 1534 addr */
+0x0F122020, /* 1536 addr */
+0x0F122012, /* 1538 addr */
+0x0F122022, /* 153A addr */
+0x0F122015, /* 153C addr */
+0x0F122025, /* 153E addr */
+};
+#endif /* DEBUG_FILTER_DATA */
+
+#ifdef CONFIG_MACH_P8LTE
+#define S5K5CCGX_ANTIBANDING_REG s5k5ccgx_antibanding_60hz_reg
+/* 60Hz anti-flicker for LTE */
+static const u32 s5k5ccgx_antibanding_60hz_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0F08,
+0x0F120001, //AFC_Default60Hz   01:60hz 00:50Hz	
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+#else
+#define S5K5CCGX_ANTIBANDING_REG s5k5ccgx_antibanding_50hz_reg
+/* 50Hz anti-flicker */
+static const u32 s5k5ccgx_antibanding_50hz_reg[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0F08,
+0x0F120000, //AFC_Default60Hz   01:60hz 00:50Hz	
+0x002A04A4,
+0x0F12067F, //REG_TC_DBG_AutoAlgEnBits 065f : Manual AFC on   067f : Manual AFC off
+};
+#endif /* #ifdef CONFIG_MACH_P8LTE */
+
+static const u32 s5k5ccgx_contrast_m_2[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_m_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_0[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_1[] = {
+//0FCFCD000,
+//000287000,
+//0002A01D2,
+//00F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_contrast_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D2,
+//0F120080,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_saturation_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FF80,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F120040,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_saturation_p_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D4,
+//0F12007E,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_2[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFC0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_m_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F12FFE0,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_0[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120000,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_1[] = {
+//FCFCD000,
+//00287000,
+//002A01D6,
+//0F120005,		//REG_TC_UserContrast
+};
+
+static const u32 s5k5ccgx_sharpness_p_2[] = {
+0xFCFCD000,
+0x00287000,
+0x002A01D6,
+0x0F120010,		//REG_TC_UserContrast
+};
+
+
+static const u32 s5k5ccgx_dtp_on[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_dtp_off[] = {
+0xFCFCD000,
+0x0028D000,
+0x002AB054,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_pll_on[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_pll_off[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0ED8,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_preflash_start[] = {
+0xFFFF012c, /* delay 300ms */
+
+0xFCFCD000,
+0x00287000,
+0x002A3F82,
+0x0F120001,		// TNP_Regs_PreflashStart
+};
+
+static const u32 s5k5ccgx_preflash_end[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F84,
+0x0F120001,		// TNP_Regs_PreflashEnd
+};
+
+static const u32 s5k5ccgx_mainflash_start[] = {
+0xFCFCD000,
+0x00287000,
+0x002A3F80,		//TNP_Regs_FastFlashAlg
+0x0F120001,
+};
+
+static const u32 s5k5ccgx_mainflash_end[] = {
+};
+
+static const u32 s5k5ccgx_flash_ae_set[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120000,
+};
+
+static const u32 s5k5ccgx_flash_ae_clear[] = {
+0xFCFCD000,
+0x00287000,
+0x002A0500,
+0x0F120002,
+};
+
+static const u32 s5k5ccgx_get_ae_stable_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E2A70,
+};
+
+static const u32 s5k5ccgx_get_esd_reg[] = {
+0xFCFCD000,
+0x002C7000,
+0x002E0150,
+};
+
+#endif /* __S5K5CCGX_REG_P8_H__ */
diff --git a/drivers/media/video/s5p-fimc/Makefile b/drivers/media/video/s5p-fimc/Makefile
index df6954a..6bca5f3 100644
--- a/drivers/media/video/s5p-fimc/Makefile
+++ b/drivers/media/video/s5p-fimc/Makefile
@@ -1,5 +1,6 @@
-s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-capture.o
-s5p-csis-objs := mipi-csis.o
+s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-capture.o fimc-vb2.o
+#s5p-csis-objs := mipi-csis.o /* w MC */
+s5p-csis-objs := s5p-mipi_csis.o
 
 obj-$(CONFIG_VIDEO_S5P_MIPI_CSIS)	+= s5p-csis.o
 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC)	+= s5p-fimc.o
diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c b/drivers/media/video/s5p-fimc/fimc-capture.c
index 81b4a82..93efab3 100644
--- a/drivers/media/video/s5p-fimc/fimc-capture.c
+++ b/drivers/media/video/s5p-fimc/fimc-capture.c
@@ -16,6 +16,7 @@
 #include <linux/errno.h>
 #include <linux/bug.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/list.h>
@@ -24,11 +25,12 @@
 #include <linux/i2c.h>
 
 #include <linux/videodev2.h>
+#include <linux/videodev2_exynos_camera.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-ioctl.h>
 #include <media/v4l2-mem2mem.h>
 #include <media/videobuf2-core.h>
-#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-cma-phys.h>
 
 #include "fimc-core.h"
 
@@ -44,7 +46,7 @@ static struct v4l2_subdev *fimc_subdev_register(struct fimc_dev *fimc,
 		return ERR_PTR(-ENOMEM);
 
 	sd = v4l2_i2c_new_subdev_board(&vid_cap->v4l2_dev, i2c_adap,
-				       isp_info->board_info, NULL);
+					isp_info->board_info, NULL);
 	if (!sd) {
 		v4l2_err(&vid_cap->v4l2_dev, "failed to acquire subdev\n");
 		return NULL;
@@ -71,10 +73,184 @@ static void fimc_subdev_unregister(struct fimc_dev *fimc)
 		i2c_put_adapter(client->adapter);
 		vid_cap->sd = NULL;
 	}
-
+	if (vid_cap->mipi_sd) {
+		v4l2_device_unregister_subdev(vid_cap->mipi_sd);
+		vid_cap->mipi_sd = NULL;
+	}
+	if (vid_cap->fb_sd) {
+		v4l2_device_unregister_subdev(vid_cap->fb_sd);
+		vid_cap->fb_sd = NULL;
+	}
+	if (vid_cap->is.sd) {
+		v4l2_device_unregister_subdev(vid_cap->is.sd);
+		vid_cap->is.sd = NULL;
+		vid_cap->is.frame_count = 0;
+		vid_cap->is.valid = 0;
+		vid_cap->is.bad_mark = 0;
+		vid_cap->is.offset_x = 0;
+		vid_cap->is.offset_y = 0;
+	}
+	if (vid_cap->flite_sd) {
+		v4l2_device_unregister_subdev(vid_cap->flite_sd);
+		vid_cap->flite_sd = NULL;
+	}
 	vid_cap->input_index = -1;
 }
 
+static int mipi_csi_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd_list = p;
+	struct v4l2_subdev *sd = NULL;
+
+	sd = dev_get_drvdata(dev);
+
+	if (sd) {
+		struct platform_device *pdev = v4l2_get_subdevdata(sd);
+		if (pdev)
+			dbg("pdev->id: %d", pdev->id);
+		*(sd_list + pdev->id) = sd;
+	}
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct v4l2_subdev *s5p_mipi_get_subdev(int id)
+{
+	const char *module_name = "s5p-mipi-csis";
+	struct device_driver *drv;
+	struct v4l2_subdev *sd[FIMC_MAX_CSIS_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv)  {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &sd[0],
+				     mipi_csi_register_callback);
+	put_driver(drv);
+
+	return ret ? NULL : sd[id];
+}
+
+static int s3cfb_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd = p;
+
+	/*
+	 * FIXME: detect platform device id and handle multiple
+	 * MIPI-CSI devices.
+	 */
+	*sd = dev_get_drvdata(dev);
+
+	if (*sd) {
+		struct platform_device *pdev = v4l2_get_subdevdata(*sd);
+		if (pdev)
+			dbg("pdev->id: %d", pdev->id);
+	}
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static int flite_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd_list = p;
+	struct v4l2_subdev *sd = NULL;
+
+	sd = dev_get_drvdata(dev);
+	if (sd) {
+		struct platform_device *pdev = v4l2_get_subdevdata(sd);
+		*(sd_list + pdev->id) = sd;
+	}
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct v4l2_subdev *exynos_flite_get_subdev(int id)
+{
+	const char *module_name = "exynos-fimc-lite";
+	struct device_driver *drv;
+	struct v4l2_subdev *sd[FLITE_MAX_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv)  {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &sd[0],
+				     flite_register_callback);
+	put_driver(drv);
+
+	return ret ? NULL : sd[id];
+}
+
+static int fimc_is_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd = p;
+	struct platform_device *pdev;
+
+	*sd = dev_get_drvdata(dev);
+
+	if (*sd)
+		pdev = v4l2_get_subdevdata(*sd);
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct v4l2_subdev *fimc_is_get_subdev(int id)
+{
+	const char *module_name = "exynos4-fimc-is";
+	struct device_driver *drv;
+	struct v4l2_subdev *sd = NULL;
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv)  {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &sd,
+				     fimc_is_register_callback);
+	put_driver(drv);
+	return ret ? NULL : sd;
+}
+
+static struct v4l2_subdev *s3c_fb_get_subdev(int id)
+{
+	const char *module_name = FIMD_MODULE_NAME;
+	struct device_driver *drv;
+	struct v4l2_subdev *sd = NULL;
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv) {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+	/*
+	 * FIXME: detect platform device id and handle multiple
+	 * MIPI-CSI devices. Now always a subdev from the last
+	 * found device is returned.
+	 */
+	ret = driver_for_each_device(drv, NULL, &sd,
+				     s3cfb_register_callback);
+	put_driver(drv);
+
+	return ret ? NULL : sd;
+}
+
 /**
  * fimc_subdev_attach - attach v4l2_subdev to camera host interface
  *
@@ -89,18 +265,62 @@ static int fimc_subdev_attach(struct fimc_dev *fimc, int index)
 	struct s5p_platform_fimc *pdata = fimc->pdata;
 	struct s5p_fimc_isp_info *isp_info;
 	struct v4l2_subdev *sd;
-	int i;
-
-	for (i = 0; i < pdata->num_clients; ++i) {
-		isp_info = &pdata->isp_info[i];
+	int i, ret;
 
-		if (index >= 0 && i != index)
+	for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i) {
+		isp_info = pdata->isp_info[i];
+		if (!isp_info || (index >= 0 && i != index))
 			continue;
+		if (isp_info->bus_type == FIMC_MIPI_CSI2) {
+			vid_cap->mipi_sd = s5p_mipi_get_subdev(isp_info->mux_id);
+			if (IS_ERR_OR_NULL(vid_cap->mipi_sd)) {
+				fimc->vid_cap.mipi_sd = NULL;
+				return PTR_ERR(vid_cap->mipi_sd);
+			}
+		} else if (isp_info->bus_type == FIMC_LCD_WB) {
+			vid_cap->fb_sd = s3c_fb_get_subdev(0);
+			if (IS_ERR_OR_NULL(vid_cap->fb_sd))
+				return PTR_ERR(vid_cap->fb_sd);
+			vid_cap->ctx->in_path = FIMC_LCD_WB;
+			vid_cap->input_index = i;
 
-		sd = fimc_subdev_register(fimc, isp_info);
-		if (!IS_ERR_OR_NULL(sd)) {
-			vid_cap->sd = sd;
+			return 0;
+		}
+
+		if (!isp_info->use_isp) {
+			sd = fimc_subdev_register(fimc, isp_info);
+			if (sd) {
+				vid_cap->sd = sd;
+				vid_cap->input_index = i;
+
+				return 0;
+			}
+		} else {
+			/* Register FIMC-Lite */
+			vid_cap->flite_sd = exynos_flite_get_subdev(isp_info->flite_id);
+			if (IS_ERR_OR_NULL(vid_cap->flite_sd)) {
+				vid_cap->flite_sd = NULL;
+				return PTR_ERR(vid_cap->flite_sd);
+			} else {
+				if (fimc_cam_use(index)) {
+					ret = v4l2_subdev_call(vid_cap->flite_sd, core, s_power, 1);
+					if (ret)
+						err("s_power failed: %d", ret);
+				}
+
+			}
+			dbg("FIMC%d Register FIMC-Lite subdev\n", fimc->id);
+			/* Register FIMC-IS*/
+			vid_cap->is.sd = fimc_is_get_subdev(index);
+			if (IS_ERR_OR_NULL(vid_cap->is.sd)) {
+				vid_cap->is.sd = NULL;
+				return PTR_ERR(vid_cap->is.sd);
+			}
 			vid_cap->input_index = i;
+			dbg("FIMC%d Register FIMC-IS subdev\n", fimc->id);
+			vid_cap->is.fmt.width = 0;
+			vid_cap->is.fmt.height = 0;
+			vid_cap->is.frame_count = 0;
 
 			return 0;
 		}
@@ -116,32 +336,165 @@ static int fimc_subdev_attach(struct fimc_dev *fimc, int index)
 static int fimc_isp_subdev_init(struct fimc_dev *fimc, unsigned int index)
 {
 	struct s5p_fimc_isp_info *isp_info;
-	struct s5p_platform_fimc *pdata = fimc->pdata;
 	int ret;
+	if (index >= FIMC_MAX_CAMIF_CLIENTS)
+		return -EINVAL;
 
-	if (index >= pdata->num_clients)
+	isp_info = fimc->pdata->isp_info[index];
+	if (!isp_info)
 		return -EINVAL;
 
-	isp_info = &pdata->isp_info[index];
+	if (isp_info->clk_frequency && isp_info->use_cam) {
+		if (isp_info->mux_id == 0) {
+			fimc->vid_cap.mux_id = 0;
+			fimc->clock[CLK_CAM0] =
+				clk_get(&fimc->pdev->dev, CLK_NAME_CAM0);
+			ret = fimc_clk_setrate(fimc, CLK_CAM0, isp_info);
+			if (!ret)
+				clk_enable(fimc->clock[CLK_CAM0]);
+		} else {
+			fimc->vid_cap.mux_id = 1;
+			fimc->clock[CLK_CAM1] =
+				clk_get(&fimc->pdev->dev, CLK_NAME_CAM1);
+			ret = fimc_clk_setrate(fimc, CLK_CAM1, isp_info);
+			if (!ret)
+				clk_enable(fimc->clock[CLK_CAM1]);
+		}
+		if (ret < 0)
+			return -EINVAL;
+	}
 
-	if (isp_info->clk_frequency)
-		clk_set_rate(fimc->clock[CLK_CAM], isp_info->clk_frequency);
+	if (isp_info->use_cam) {
+		dbg("FIMC%d try to attatch sensor\n", fimc->id);
+		ret = fimc_subdev_attach(fimc, index);
+		if (ret)
+			return ret;
+		fimc->vid_cap.is.camcording = 0;
+	} else {
+		dbg("FIMC%d didn't try to attatch sensor\n", fimc->id);
+		fimc->vid_cap.input_index = index;
+		fimc->vid_cap.mux_id = -1;
+		if (isp_info->use_isp)
+			fimc->vid_cap.is.camcording = 1;
+		else
+			fimc->vid_cap.is.camcording = 0;
+	}
 
-	ret = clk_enable(fimc->clock[CLK_CAM]);
+	ret = fimc_hw_set_camera_polarity(fimc, isp_info);
 	if (ret)
 		return ret;
 
-	ret = fimc_subdev_attach(fimc, index);
-	if (ret)
-		return ret;
+	if (fimc->vid_cap.mipi_sd)
+		ret = v4l2_subdev_call(fimc->vid_cap.mipi_sd, core, s_power, 1);
 
-	ret = fimc_hw_set_camera_polarity(fimc, isp_info);
-	if (ret)
-		return ret;
+	if (fimc->vid_cap.sd)
+		ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 1);
 
-	ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 1);
-	if (!ret)
+	if (fimc->vid_cap.fb_sd) {
+		unsigned int wb_on = 1;
+		dbg("write-back mode\n");
+		ret = v4l2_subdev_call(fimc->vid_cap.fb_sd, core, ioctl,
+					(unsigned int)NULL, &wb_on);
+	}
+
+	if (fimc->vid_cap.is.sd) {
+		dbg("FIMC-IS Init sequence\n");
+		ret = isp_info->cam_power(1);
+		if (unlikely(ret < 0))
+			err("Fail to power on\n");
+		ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, s_power, 1);
+		if (ret < 0) {
+			err("FIMC-IS init failed - power on");
+			return -ENODEV;
+		}
+		ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, load_fw);
+		if (ret < 0) {
+			err("FIMC-IS init failed - load fw");
+			return -ENODEV;
+		}
+
+		if (strcmp(&isp_info->board_info->type[0], "S5K3H2") == 0) {
+			switch (isp_info->mux_id) {
+			case 0:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 1);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			case 1:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 101);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			default:
+				break;
+			}
+		} else if (strcmp(&isp_info->board_info->type[0], "S5K4E5") == 0) {
+			switch (isp_info->mux_id) {
+			case 0:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 3);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			case 1:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 103);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			default:
+				break;
+			}
+		} else if (strcmp(&isp_info->board_info->type[0], "S5K3H7") == 0) {
+			switch (isp_info->mux_id) {
+			case 0:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 4);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			case 1:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 104);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			default:
+				break;
+			}
+		} else if (strcmp(&isp_info->board_info->type[0], "S5K6A3") == 0) {
+			switch (isp_info->mux_id) {
+			case 0:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 2);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			case 1:
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, init, 102);
+				if (ret < 0) {
+					err("FIMC-IS init failed - open sensor");
+					return -ENODEV;
+				}
+				break;
+			default:
+				break;
+			}
+		}
+	}
+
+	if (!ret) {
 		return ret;
+    }
 
 	/* enabling power failed so unregister subdev */
 	fimc_subdev_unregister(fimc);
@@ -157,7 +510,7 @@ static int fimc_stop_capture(struct fimc_dev *fimc)
 	unsigned long flags;
 	struct fimc_vid_cap *cap;
 	struct fimc_vid_buffer *buf;
-
+	int ret = 0;
 	cap = &fimc->vid_cap;
 
 	if (!fimc_capture_active(fimc))
@@ -168,15 +521,26 @@ static int fimc_stop_capture(struct fimc_dev *fimc)
 	fimc_deactivate_capture(fimc);
 	spin_unlock_irqrestore(&fimc->slock, flags);
 
-	wait_event_timeout(fimc->irq_queue,
-			   !test_bit(ST_CAPT_SHUT, &fimc->state),
-			   FIMC_SHUTDOWN_TIMEOUT);
+	ret = fimc_wait_disable_capture(fimc);
+	if (ret < 0)
+		err("wait stop seq fail");
+
+	if (cap->sd)
+		v4l2_subdev_call(cap->sd, video, s_stream, 0);
+
+	if (cap->is.sd)
+		v4l2_subdev_call(fimc->vid_cap.is.sd, video, s_stream, 0);
 
-	v4l2_subdev_call(cap->sd, video, s_stream, 0);
+	if (cap->flite_sd)
+		v4l2_subdev_call(fimc->vid_cap.flite_sd, video, s_stream, 0);
+
+	if (cap->mipi_sd)
+		v4l2_subdev_call(fimc->vid_cap.mipi_sd, video, s_stream, 0);
 
 	spin_lock_irqsave(&fimc->slock, flags);
 	fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_PEND |
-			 1 << ST_CAPT_SHUT | 1 << ST_CAPT_STREAM);
+			 1 << ST_CAPT_SHUT | 1 << ST_CAPT_STREAM |
+			 1 << ST_CAPT_SENS_STREAM);
 
 	fimc->vid_cap.active_buf_cnt = 0;
 
@@ -202,29 +566,61 @@ static int start_streaming(struct vb2_queue *q)
 	struct fimc_ctx *ctx = q->drv_priv;
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct s5p_fimc_isp_info *isp_info;
-	int ret;
+	int ret = 0;
 
-	fimc_hw_reset(fimc);
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
 
-	ret = v4l2_subdev_call(fimc->vid_cap.sd, video, s_stream, 1);
-	if (ret && ret != -ENOIOCTLCMD)
-		return ret;
+	if (fimc->vid_cap.mipi_sd) {
+		ret = v4l2_subdev_call(fimc->vid_cap.mipi_sd, video, s_stream, 1);
+		if (ret) {
+			err("mipi s_stream error");
+			return ret;
+		}
+	}
 
 	ret = fimc_prepare_config(ctx, ctx->state);
 	if (ret)
 		return ret;
 
-	isp_info = &fimc->pdata->isp_info[fimc->vid_cap.input_index];
+	isp_info = fimc->pdata->isp_info[fimc->vid_cap.input_index];
 	fimc_hw_set_camera_type(fimc, isp_info);
+
+	if (ctx->in_path == FIMC_LCD_WB) {
+		if (isp_info->mux_id == 0)
+			fimc_hwset_sysreg_camblk_fimd0_wb(fimc);
+		else
+			fimc_hwset_sysreg_camblk_fimd1_wb(fimc);
+	}
+
+	if (fimc->vid_cap.is.sd) {
+		struct platform_device *pdev = fimc->pdev;
+		struct clk *pxl_async = NULL;
+
+		dbg("FIMC-IS pixel async setting\n");
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+		    err("failed to get pxl_async\n");
+		    return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+		fimc_hwset_sysreg_camblk_isp_wb(fimc);
+	}
+
+	if (fimc->vid_cap.flite_sd) {
+		dbg("FIMC-Lite stream on..\n");
+		v4l2_subdev_call(fimc->vid_cap.flite_sd, video, s_stream, 1);
+	}
+
 	fimc_hw_set_camera_source(fimc, isp_info);
 	fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
 
 	if (ctx->state & FIMC_PARAMS) {
 		ret = fimc_set_scaler_info(ctx);
-		if (ret) {
+		if (ret)
 			err("Scaler setup error");
-			return ret;
-		}
 		fimc_hw_set_input_path(ctx);
 		fimc_hw_set_prescaler(ctx);
 		fimc_hw_set_mainscaler(ctx);
@@ -235,12 +631,14 @@ static int start_streaming(struct vb2_queue *q)
 
 	fimc_hw_set_output_path(ctx);
 	fimc_hw_set_out_dma(ctx);
+	/* for zero shuterlack at Exynos4210 EVT1 */
+	fimc_hwset_enable_lastend(fimc);
 
 	INIT_LIST_HEAD(&fimc->vid_cap.pending_buf_q);
 	INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
 	fimc->vid_cap.active_buf_cnt = 0;
 	fimc->vid_cap.frame_count = 0;
-	fimc->vid_cap.buf_index = 0;
+	fimc->vid_cap.buf_index = fimc_hw_get_frame_index(fimc);
 
 	set_bit(ST_CAPT_PEND, &fimc->state);
 
@@ -252,17 +650,28 @@ static int stop_streaming(struct vb2_queue *q)
 	struct fimc_ctx *ctx = q->drv_priv;
 	struct fimc_dev *fimc = ctx->fimc_dev;
 
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
 	if (!fimc_capture_active(fimc))
 		return -EINVAL;
 
-	return fimc_stop_capture(fimc);
+	fimc_stop_capture(fimc);
+	fimc_hw_reset(fimc);
+	fimc->vb2->suspend(fimc->alloc_ctx);
+
+	if (test_and_clear_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_put_sync(&fimc->pdev->dev);
+
+	return 0;
 }
 
 static unsigned int get_plane_size(struct fimc_frame *fr, unsigned int plane)
 {
 	if (!fr || plane >= fr->fmt->memplanes)
 		return 0;
-	return fr->f_width * fr->f_height * fr->fmt->depth[plane] / 8;
+
+	return fr->payload[plane];
 }
 
 static int queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
@@ -290,6 +699,8 @@ static int buffer_prepare(struct vb2_buffer *vb)
 {
 	struct vb2_queue *vq = vb->vb2_queue;
 	struct fimc_ctx *ctx = vq->drv_priv;
+	struct fimc_dev *fimc = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->d_frame;
 	struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
 	int i;
 
@@ -300,7 +711,7 @@ static int buffer_prepare(struct vb2_buffer *vb)
 		unsigned long size = get_plane_size(&ctx->d_frame, i);
 
 		if (vb2_plane_size(vb, i) < size) {
-			v4l2_err(v4l2_dev, "User buffer too small (%ld < %ld)\n",
+			v4l2_err(v4l2_dev, "User buffer too small(%ld < %ld)\n",
 				 vb2_plane_size(vb, i), size);
 			return -EINVAL;
 		}
@@ -308,28 +719,41 @@ static int buffer_prepare(struct vb2_buffer *vb)
 		vb2_set_plane_payload(vb, i, size);
 	}
 
+	if (ctx->d_frame.cacheable)
+		fimc->vb2->cache_flush(vb, frame->fmt->memplanes);
+
 	return 0;
 }
 
 static void buffer_queue(struct vb2_buffer *vb)
 {
-	struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
-	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_vid_buffer *buf
 		= container_of(vb, struct fimc_vid_buffer, vb);
+	struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
+	struct fimc_fmt *fmt = vid_cap->ctx->d_frame.fmt;
 	unsigned long flags;
 	int min_bufs;
 
 	spin_lock_irqsave(&fimc->slock, flags);
 	fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr);
 
+	if (fmt->fourcc == V4L2_PIX_FMT_YVU420 ||
+			fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+		u32 t_cb = buf->paddr.cb;
+		buf->paddr.cb = buf->paddr.cr;
+		buf->paddr.cr = t_cb;
+	}
+
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
 	if (!test_bit(ST_CAPT_STREAM, &fimc->state)
 	     && vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
 		/* Setup the buffer directly for processing. */
 		int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
 				vid_cap->buf_index;
-
 		fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
 		buf->index = vid_cap->buf_index;
 		active_queue_add(vid_cap, buf);
@@ -342,23 +766,46 @@ static void buffer_queue(struct vb2_buffer *vb)
 
 	min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
 
+	if (!test_bit(ST_CAPT_RUN, &fimc->state)) {
+		if (vid_cap->active_buf_cnt == 1)
+			fimc->vb2->resume(fimc->alloc_ctx);
+	}
 	if (vid_cap->active_buf_cnt >= min_bufs &&
-	    !test_and_set_bit(ST_CAPT_STREAM, &fimc->state))
+	    !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
+		int ret = 0;
 		fimc_activate_capture(ctx);
+		spin_unlock_irqrestore(&fimc->slock, flags);
+
+		if (!test_and_set_bit(ST_CAPT_SENS_STREAM, &fimc->state)) {
+			if (fimc->vid_cap.is.sd)
+				ret = v4l2_subdev_call(fimc->vid_cap.is.sd,
+					video, s_stream, 1);
+			else
+				ret = v4l2_subdev_call(fimc->vid_cap.sd, video,
+						s_stream, 1);
+		}
+		return;  /* ret = -ENOIOCTLCMD ? 0 : ret; */
+	}
 
 	spin_unlock_irqrestore(&fimc->slock, flags);
+
+	return;
 }
 
 static void fimc_lock(struct vb2_queue *vq)
 {
+#ifdef FOR_DIFF_VER
 	struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 	mutex_lock(&ctx->fimc_dev->lock);
+#endif
 }
 
 static void fimc_unlock(struct vb2_queue *vq)
 {
+#ifdef FOR_DIFF_VER
 	struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 	mutex_unlock(&ctx->fimc_dev->lock);
+#endif
 }
 
 static struct vb2_ops fimc_capture_qops = {
@@ -374,24 +821,26 @@ static struct vb2_ops fimc_capture_qops = {
 static int fimc_capture_open(struct file *file)
 {
 	struct fimc_dev *fimc = video_drvdata(file);
-	int ret = 0;
 
 	dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
+	fimc_hw_reset(fimc);
+	fimc_hw_set_irq_level(fimc);
+
+	if (fimc->variant->out_buf_count > 4)
+		fimc_hw_set_dma_seq(fimc, 0xF);
 
 	/* Return if the corresponding video mem2mem node is already opened. */
 	if (fimc_m2m_active(fimc))
 		return -EBUSY;
 
-	if (++fimc->vid_cap.refcnt == 1) {
-		ret = fimc_isp_subdev_init(fimc, 0);
-		if (ret) {
-			fimc->vid_cap.refcnt--;
-			return -EIO;
-		}
-	}
-
 	file->private_data = fimc->vid_cap.ctx;
 
+	if (test_and_clear_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_put_sync(&fimc->pdev->dev);
+
 	return 0;
 }
 
@@ -401,17 +850,40 @@ static int fimc_capture_close(struct file *file)
 
 	dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
 
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
 	if (--fimc->vid_cap.refcnt == 0) {
 		fimc_stop_capture(fimc);
 		vb2_queue_release(&fimc->vid_cap.vbq);
 
 		v4l2_err(&fimc->vid_cap.v4l2_dev, "releasing ISP\n");
 
-		v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
-		clk_disable(fimc->clock[CLK_CAM]);
+		if (fimc->vid_cap.sd)
+			v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
+
+		if (fimc->vid_cap.is.sd)
+			v4l2_subdev_call(fimc->vid_cap.is.sd, core, s_power, 0);
+
+		if (fimc->vid_cap.flite_sd)
+			v4l2_subdev_call(fimc->vid_cap.flite_sd, core, s_power, 0);
+
+		if (fimc->vid_cap.mipi_sd)
+			v4l2_subdev_call(fimc->vid_cap.mipi_sd, core, s_power, 0);
+
+		if (fimc->vid_cap.mux_id == 0) {
+			clk_put(fimc->clock[CLK_CAM0]);
+			clk_disable(fimc->clock[CLK_CAM0]);
+		} else if (fimc->vid_cap.mux_id == 1) {
+			clk_put(fimc->clock[CLK_CAM1]);
+			clk_disable(fimc->clock[CLK_CAM1]);
+		}
 		fimc_subdev_unregister(fimc);
 	}
 
+	if (test_and_clear_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_put_sync(&fimc->pdev->dev);
+
 	return 0;
 }
 
@@ -459,29 +931,88 @@ static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
 }
 
 /* Synchronize formats of the camera interface input and attached  sensor. */
-static int sync_capture_fmt(struct fimc_ctx *ctx)
+static int sync_capture_fmt(struct fimc_ctx *ctx, struct v4l2_rect *r)
 {
-	struct fimc_frame *frame = &ctx->s_frame;
+	struct fimc_frame *frame = &ctx->d_frame;
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct v4l2_mbus_framefmt *fmt = &fimc->vid_cap.fmt;
+	struct fimc_pix_limit *plim = fimc->variant->pix_limit;
 	int ret;
+	int max_w, max_h;
+
+	fmt->width  = r->width;
+	fmt->height = r->height;
+	max_w = ctx->scaler.enabled ? plim->scaler_en_w : plim->scaler_dis_w;
+	max_h = fimc_fmt_is_jpeg(frame->fmt->color) ? 0xFFFF : plim->in_rot_en_h;
+
+	v4l_bound_align_image(&fmt->width, 16, max_w, 4,
+			      &fmt->height, 2, max_h, 1, 0);
+
+	dbg("%dx%d", fmt->width, fmt->height);
+	/*
+	 *  Try to match image sensor pixel format to the color format
+	 *  of the capture image to avoid color conversion when possible.
+	 *  If fimc destination is jpeg, sensor should be jpeg mbus code,
+	 *  and others should be yuv type although fimc'output is rgb.
+	 */
+	if (frame->fmt->fourcc == V4L2_PIX_FMT_JPEG)
+		fmt->code = frame->fmt->mbus_code;
+	else
+		fmt->code = DEFAULT_ISP_PIXCODE;
+
+	dbg("frame->fmt->mbus_code : 0x%x", frame->fmt->mbus_code);
+	dbg("frame->fmt->name : %s", frame->fmt->name);
+	dbg("frame->fmt->fourcc : 0x%x", frame->fmt->fourcc);
+	dbg("frame->fmt->color : 0x%x", frame->fmt->color);
+	dbg("frame->fmt->memplanes : 0x%x", frame->fmt->memplanes);
+	dbg("frame->fmt->colplanes : 0x%x", frame->fmt->colplanes);
+
+	dbg("fmt->code : 0x%x", fmt->code);
+	dbg("fmt->colorspace : 0x%x", fmt->colorspace);
+
+	if (fimc->vid_cap.sd)
+		ret = v4l2_subdev_call(fimc->vid_cap.sd, video, s_mbus_fmt, fmt);
 
-	fmt->width  = ctx->d_frame.o_width;
-	fmt->height = ctx->d_frame.o_height;
+	if (ret) {
+		err("s_mbus_fmt failed");
+		return ret;
+	}
+
+	err("IS : w= %d, h= %d", fimc->vid_cap.is.mbus_fmt.width, fimc->vid_cap.is.mbus_fmt.height);
+	if (fimc->vid_cap.mipi_sd) {
+		if (fimc->vid_cap.is.sd)
+			ret = v4l2_subdev_call(fimc->vid_cap.mipi_sd, video, s_mbus_fmt, &fimc->vid_cap.is.mbus_fmt);
+		else
+			ret = v4l2_subdev_call(fimc->vid_cap.mipi_sd, video, s_mbus_fmt, fmt);
+		if (ret) {
+			err("s_mbus_fmt failed: %d", ret);
+			return ret;
+		}
+	}
 
-	ret = v4l2_subdev_call(fimc->vid_cap.sd, video, s_mbus_fmt, fmt);
-	if (ret == -ENOIOCTLCMD) {
+	if (fimc->vid_cap.flite_sd)
+		ret = v4l2_subdev_call(fimc->vid_cap.flite_sd, video, s_mbus_fmt, &fimc->vid_cap.is.mbus_fmt);
+
+	if (ret) {
 		err("s_mbus_fmt failed");
 		return ret;
 	}
-	dbg("w: %d, h: %d, code= %d", fmt->width, fmt->height, fmt->code);
+
+	dbg("w= %d, h= %d, code= %d", fmt->width, fmt->height, fmt->code);
+
+	frame = &ctx->s_frame;
 
 	frame->fmt = find_mbus_format(fmt, FMT_FLAGS_CAM);
 	if (!frame->fmt) {
-		err("fimc source format not found\n");
+		v4l2_err(&fimc->vid_cap.v4l2_dev,
+			 "fimc source format not found\n");
 		return -EINVAL;
 	}
 
+	/* Color conversion to JPEG is not supported */
+	if (ctx->d_frame.fmt->color == S5P_FIMC_JPEG &&
+	    fmt->code != V4L2_MBUS_FMT_JPEG_1X8)
+		return -EINVAL;
 	frame->f_width	= fmt->width;
 	frame->f_height = fmt->height;
 	frame->width	= fmt->width;
@@ -491,6 +1022,10 @@ static int sync_capture_fmt(struct fimc_ctx *ctx)
 	frame->offs_h	= 0;
 	frame->offs_v	= 0;
 
+	dbg("frame->width : %d, frame->f_height : %d, frame->width : %d,\
+		frame->height : %d, frame->o_width : %d, frame->o_height :\
+		%d\n", frame->width, frame->f_height, frame->width,\
+		frame->height, frame->o_width, frame->o_height);
 	return 0;
 }
 
@@ -501,17 +1036,22 @@ static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_frame *frame;
 	struct v4l2_pix_format_mplane *pix;
+	struct v4l2_rect r;
 	int ret;
 	int i;
+	struct v4l2_control is_ctrl;
 
 	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 		return -EINVAL;
 
+	r.width  = f->fmt.pix_mp.width;
+	r.height = f->fmt.pix_mp.height;
+
 	ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
 	if (ret)
 		return ret;
 
-	if (vb2_is_busy(&fimc->vid_cap.vbq) || fimc_capture_active(fimc))
+	if (vb2_is_streaming(&fimc->vid_cap.vbq) || fimc_capture_active(fimc))
 		return -EBUSY;
 
 	frame = &ctx->d_frame;
@@ -523,25 +1063,71 @@ static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
 		return -EINVAL;
 	}
 
-	for (i = 0; i < frame->fmt->colplanes; i++) {
-		frame->payload[i] =
-			(pix->width * pix->height * frame->fmt->depth[i]) >> 3;
-	}
+	for (i = 0; i < frame->fmt->colplanes; i++)
+		frame->payload[i] = pix->plane_fmt[i].sizeimage;
 
-	/* Output DMA frame pixel size and offsets. */
-	frame->f_width = pix->plane_fmt[0].bytesperline * 8
-			/ frame->fmt->depth[0];
-	frame->f_height = pix->height;
-	frame->width	= pix->width;
-	frame->height	= pix->height;
-	frame->o_width	= pix->width;
-	frame->o_height = pix->height;
-	frame->offs_h	= 0;
-	frame->offs_v	= 0;
+	fimc_set_frame_size_mp(frame, f);
 
 	ctx->state |= (FIMC_PARAMS | FIMC_DST_FMT);
 
-	ret = sync_capture_fmt(ctx);
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
+	/* for returning preview size for FIMC-Lite */
+	if (fimc->vid_cap.is.sd) {
+		fimc->vid_cap.is.mbus_fmt.code = V4L2_MBUS_FMT_SGRBG10_1X10;
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_WIDTH;
+		v4l2_subdev_call(fimc->vid_cap.is.sd, core, g_ctrl, &is_ctrl);
+		fimc->vid_cap.is.fmt.width = fimc->vid_cap.is.mbus_fmt.width = is_ctrl.value;
+
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_HEIGHT;
+		v4l2_subdev_call(fimc->vid_cap.is.sd, core, g_ctrl, &is_ctrl);
+		fimc->vid_cap.is.fmt.height = fimc->vid_cap.is.mbus_fmt.height = is_ctrl.value;
+		/* default offset values */
+		fimc->vid_cap.is.offset_x = 16;
+		fimc->vid_cap.is.offset_y = 12;
+		fimc->vid_cap.is.mbus_fmt.width += fimc->vid_cap.is.offset_x;
+		fimc->vid_cap.is.mbus_fmt.height += fimc->vid_cap.is.offset_y;
+	}
+	ret = sync_capture_fmt(ctx, &r);
+
+	/* Scaling is not supported with JPEG color format. */
+	ctx->scaler.enabled = !fimc_fmt_is_jpeg(ctx->d_frame.fmt->color);
+
+	return ret;
+}
+
+static int fimc_s_fmt_vid_private(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *fimc = ctx->fimc_dev;
+	struct v4l2_mbus_framefmt *mbus_fmt;
+	int ret = 0;
+
+	dbg("%s\n", __func__);
+	mbus_fmt = kzalloc(sizeof(*mbus_fmt), GFP_KERNEL);
+	if (!mbus_fmt) {
+		err("%s: no memory for "
+			"mbus_fmt\n", __func__);
+		return -ENOMEM;
+	}
+	fimc->vid_cap.is.fmt.width = f->fmt.pix.width;
+	fimc->vid_cap.is.fmt.height = f->fmt.pix.height;
+	fimc->vid_cap.is.fmt.pixelformat = f->fmt.pix.pixelformat;
+	fimc->vid_cap.is.mbus_fmt.width = f->fmt.pix.width + 16;
+	fimc->vid_cap.is.mbus_fmt.height = f->fmt.pix.height + 12;
+	fimc->vid_cap.is.mbus_fmt.code = V4L2_MBUS_FMT_SGRBG10_1X10;
+	fimc->vid_cap.is.mbus_fmt.colorspace = V4L2_COLORSPACE_SRGB;
+
+	mbus_fmt->width = f->fmt.pix.width;
+	mbus_fmt->height = f->fmt.pix.height;
+	mbus_fmt->code = V4L2_MBUS_FMT_YUYV8_2X8; /*dummy*/
+	mbus_fmt->field = f->fmt.pix.field;
+	mbus_fmt->colorspace = V4L2_COLORSPACE_SRGB;
+	if (fimc->vid_cap.is.sd)
+		ret = v4l2_subdev_call(fimc->vid_cap.is.sd, video,
+						s_mbus_fmt, mbus_fmt);
+	kfree(mbus_fmt);
 	return ret;
 }
 
@@ -552,10 +1138,12 @@ static int fimc_cap_enum_input(struct file *file, void *priv,
 	struct s5p_platform_fimc *pldata = ctx->fimc_dev->pdata;
 	struct s5p_fimc_isp_info *isp_info;
 
-	if (i->index >= pldata->num_clients)
+	if (i->index >= FIMC_MAX_CAMIF_CLIENTS)
 		return -EINVAL;
 
-	isp_info = &pldata->isp_info[i->index];
+	isp_info = pldata->isp_info[i->index];
+	if (isp_info == NULL)
+		return -EINVAL;
 
 	i->type = V4L2_INPUT_TYPE_CAMERA;
 	strncpy(i->name, isp_info->board_info->type, 32);
@@ -568,26 +1156,54 @@ static int fimc_cap_s_input(struct file *file, void *priv,
 	struct fimc_ctx *ctx = priv;
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct s5p_platform_fimc *pdata = fimc->pdata;
+	int ret;
 
 	if (fimc_capture_active(ctx->fimc_dev))
 		return -EBUSY;
 
-	if (i >= pdata->num_clients)
+	if (i >= FIMC_MAX_CAMIF_CLIENTS || !pdata->isp_info[i]) {
+		err("error max client or pdata");
 		return -EINVAL;
+	}
 
+	if (fimc->vid_cap.mipi_sd) {
+		ret = v4l2_subdev_call(fimc->vid_cap.mipi_sd, core, s_power, 0);
+		if (ret)
+			err("s_power failed: %d", ret);
+	}
 
 	if (fimc->vid_cap.sd) {
-		int ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
+		ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
 		if (ret)
 			err("s_power failed: %d", ret);
+	}
+	/* FIMC-IS power of */
+	if (fimc->vid_cap.is.sd) {
+		ret = v4l2_subdev_call(fimc->vid_cap.is.sd, core, s_power, 0);
+		if (ret)
+			err("s_power failed: %d", ret);
+	}
 
-		clk_disable(fimc->clock[CLK_CAM]);
+	if (fimc->vid_cap.flite_sd) {
+		ret = v4l2_subdev_call(fimc->vid_cap.flite_sd, core, s_power, 0);
+		if (ret)
+			err("s_power failed: %d", ret);
 	}
 
+	dbg("Release the attached sensor subdevice");
 	/* Release the attached sensor subdevice. */
 	fimc_subdev_unregister(fimc);
 
-	return fimc_isp_subdev_init(fimc, i);
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
+	ret = fimc_isp_subdev_init(fimc, i);
+	if (ret)
+		err("subdev init failed");
+
+	fimc->vid_cap.refcnt++;
+
+	return ret;
 }
 
 static int fimc_cap_g_input(struct file *file, void *priv,
@@ -606,9 +1222,6 @@ static int fimc_cap_streamon(struct file *file, void *priv,
 	struct fimc_ctx *ctx = priv;
 	struct fimc_dev *fimc = ctx->fimc_dev;
 
-	if (fimc_capture_active(fimc) || !fimc->vid_cap.sd)
-		return -EBUSY;
-
 	if (!(ctx->state & FIMC_DST_FMT)) {
 		v4l2_err(&fimc->vid_cap.v4l2_dev, "Format is not set\n");
 		return -EINVAL;
@@ -630,9 +1243,14 @@ static int fimc_cap_reqbufs(struct file *file, void *priv,
 			    struct v4l2_requestbuffers *reqbufs)
 {
 	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
+	struct fimc_frame *frame;
 	int ret;
 
+	frame = ctx_get_frame(ctx, reqbufs->type);
+	frame->cacheable = ctx->cacheable;
+	fimc->vb2->set_cacheable(fimc->alloc_ctx, frame->cacheable);
 
 	ret = vb2_reqbufs(&cap->vbq, reqbufs);
 	if (!ret)
@@ -655,6 +1273,7 @@ static int fimc_cap_qbuf(struct file *file, void *priv,
 {
 	struct fimc_ctx *ctx = priv;
 	struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
+
 	return vb2_qbuf(&cap->vbq, buf);
 }
 
@@ -683,9 +1302,12 @@ static int fimc_cap_s_ctrl(struct file *file, void *priv,
 				ctx->state |= FIMC_PARAMS;
 		}
 	}
-	if (ret == -EINVAL)
+	if (ret == -EINVAL && ctx->fimc_dev->vid_cap.sd)
 		ret = v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
 				       core, s_ctrl, ctrl);
+	if (ctx->fimc_dev->vid_cap.is.sd)
+		ret = v4l2_subdev_call(ctx->fimc_dev->vid_cap.is.sd,
+				       core, s_ctrl, ctrl);
 	return ret;
 }
 
@@ -747,11 +1369,11 @@ static int fimc_cap_s_crop(struct file *file, void *fh,
 
 	f = &ctx->s_frame;
 	/* Check for the pixel scaling ratio when cropping input image. */
-	ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
+	ret = fimc_check_scaler_ratio(ctx, cr->c.width, cr->c.height,
 				      ctx->d_frame.width, ctx->d_frame.height,
 				      ctx->rotation);
 	if (ret) {
-		v4l2_err(&fimc->vid_cap.v4l2_dev, "Out of the scaler range\n");
+		v4l2_err(&fimc->vid_cap.v4l2_dev, "Out of the scaler range");
 		return ret;
 	}
 
@@ -771,6 +1393,7 @@ static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
 	.vidioc_try_fmt_vid_cap_mplane	= fimc_vidioc_try_fmt_mplane,
 	.vidioc_s_fmt_vid_cap_mplane	= fimc_cap_s_fmt_mplane,
 	.vidioc_g_fmt_vid_cap_mplane	= fimc_vidioc_g_fmt_mplane,
+	.vidioc_s_fmt_type_private	= fimc_s_fmt_vid_private,
 
 	.vidioc_reqbufs			= fimc_cap_reqbufs,
 	.vidioc_querybuf		= fimc_cap_querybuf,
@@ -794,6 +1417,34 @@ static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
 	.vidioc_g_input			= fimc_cap_g_input,
 };
 
+/*
+ * The End Of Frame notification sent by sensor subdev in its still capture
+ * mode. If there is only a single VSYNC generated by the sensor, FIMC does
+ * not issue the LastIrq (end of frame) interrupt. And this notification
+ *  is used to complete a frame capture and passing it to userspace.
+ */
+void fimc_v4l2_dev_notify(struct v4l2_subdev *sd, unsigned int notification,
+			  void *arg)
+{
+	struct fimc_vid_cap *cap = container_of(sd->v4l2_dev,
+						struct fimc_vid_cap, v4l2_dev);
+	struct fimc_dev *fimc = container_of(cap, struct fimc_dev, vid_cap);
+	struct fimc_vid_buffer *buf;
+	unsigned long flags;
+
+	dbg("bytesused: %d", notification);
+
+	spin_lock_irqsave(&fimc->slock, flags);
+	buf = list_entry(cap->active_buf_q.next, struct fimc_vid_buffer, list);
+
+	vb2_set_plane_payload(&buf->vb, 0, notification);
+
+	fimc_capture_irq_handler(fimc);
+	fimc_deactivate_capture(fimc);
+
+	spin_unlock_irqrestore(&fimc->slock, flags);
+}
+
 /* fimc->lock must be already initialized */
 int fimc_register_capture_device(struct fimc_dev *fimc)
 {
@@ -826,6 +1477,8 @@ int fimc_register_capture_device(struct fimc_dev *fimc)
 		snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
 			 "%s.capture", dev_name(&fimc->pdev->dev));
 
+	v4l2_dev->notify = fimc_v4l2_dev_notify;
+
 	ret = v4l2_device_register(NULL, v4l2_dev);
 	if (ret)
 		goto err_info;
@@ -843,7 +1496,9 @@ int fimc_register_capture_device(struct fimc_dev *fimc)
 	vfd->ioctl_ops	= &fimc_capture_ioctl_ops;
 	vfd->minor	= -1;
 	vfd->release	= video_device_release;
+#ifdef FOR_DIFF_VER
 	vfd->lock	= &fimc->lock;
+#endif
 	video_set_drvdata(vfd, fimc);
 
 	vid_cap = &fimc->vid_cap;
@@ -851,8 +1506,18 @@ int fimc_register_capture_device(struct fimc_dev *fimc)
 	vid_cap->active_buf_cnt = 0;
 	vid_cap->reqbufs_count  = 0;
 	vid_cap->refcnt = 0;
-	/* Default color format for image sensor */
-	vid_cap->fmt.code = V4L2_MBUS_FMT_YUYV8_2X8;
+	vid_cap->sd = NULL;
+	vid_cap->fb_sd = NULL;
+	vid_cap->mipi_sd = NULL;
+	vid_cap->is.sd = NULL;
+	vid_cap->is.frame_count = 0;
+	vid_cap->is.valid = 0;
+	vid_cap->is.bad_mark = 0;
+	vid_cap->is.offset_x = 0;
+	vid_cap->is.offset_y = 0;
+
+	/* Default color format for 4EA image sensor */
+	vid_cap->fmt.code = V4L2_MBUS_FMT_VYUY8_2X8;
 
 	INIT_LIST_HEAD(&vid_cap->pending_buf_q);
 	INIT_LIST_HEAD(&vid_cap->active_buf_q);
@@ -865,7 +1530,7 @@ int fimc_register_capture_device(struct fimc_dev *fimc)
 	q->io_modes = VB2_MMAP | VB2_USERPTR;
 	q->drv_priv = fimc->vid_cap.ctx;
 	q->ops = &fimc_capture_qops;
-	q->mem_ops = &vb2_dma_contig_memops;
+	q->mem_ops = ctx->fimc_dev->vb2->ops;
 	q->buf_struct_size = sizeof(struct fimc_vid_buffer);
 
 	vb2_queue_init(q);
@@ -879,7 +1544,7 @@ int fimc_register_capture_device(struct fimc_dev *fimc)
 	v4l2_info(v4l2_dev,
 		  "FIMC capture driver registered as /dev/video%d\n",
 		  vfd->num);
-
+	dbg("%s : code : %d\n", __func__, fimc->vid_cap.fmt.code);
 	return 0;
 
 err_vd_reg:
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
index bdf19ad..4b892d2 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.c
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -17,6 +17,7 @@
 #include <linux/errno.h>
 #include <linux/bug.h>
 #include <linux/interrupt.h>
+#include <linux/workqueue.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/list.h>
@@ -24,13 +25,12 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <media/v4l2-ioctl.h>
-#include <media/videobuf2-core.h>
-#include <media/videobuf2-dma-contig.h>
+#include <plat/cpu.h>
 
 #include "fimc-core.h"
 
 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
-	"sclk_fimc", "fimc", "sclk_cam"
+	"sclk_fimc", "fimc"
 };
 
 static struct fimc_fmt fimc_formats[] = {
@@ -41,7 +41,7 @@ static struct fimc_fmt fimc_formats[] = {
 		.color		= S5P_FIMC_RGB565,
 		.memplanes	= 1,
 		.colplanes	= 1,
-		.flags		= FMT_FLAGS_M2M,
+		.flags		= FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 	}, {
 		.name		= "BGR666",
 		.fourcc		= V4L2_PIX_FMT_BGR666,
@@ -59,6 +59,23 @@ static struct fimc_fmt fimc_formats[] = {
 		.colplanes	= 1,
 		.flags		= FMT_FLAGS_M2M,
 	}, {
+		.name		= "RGB555",
+		.fourcc		= V4L2_PIX_FMT_RGB555,
+		.depth		= { 16 },
+		.color		= S5P_FIMC_RGB555,
+		.memplanes	= 1,
+		.colplanes	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
+		.flags		= FMT_FLAGS_M2M | FMT_FLAGS_CAM,
+	}, {
+		.name		= "RGB444",
+		.fourcc		= V4L2_PIX_FMT_RGB444,
+		.depth		= { 16 },
+		.color		= S5P_FIMC_RGB444,
+		.memplanes	= 1,
+		.colplanes	= 1,
+		.flags		= FMT_FLAGS_M2M | FMT_FLAGS_CAM,
+	}, {
 		.name		= "YUV 4:2:2 packed, YCbYCr",
 		.fourcc		= V4L2_PIX_FMT_YUYV,
 		.depth		= { 16 },
@@ -127,6 +144,14 @@ static struct fimc_fmt fimc_formats[] = {
 		.colplanes	= 3,
 		.flags		= FMT_FLAGS_M2M,
 	}, {
+		.name		= "YUV 4:2:0 planar, YCrCb",
+		.fourcc		= V4L2_PIX_FMT_YVU420,
+		.depth		= { 12 },
+		.color		= S5P_FIMC_YCBCR420,
+		.memplanes	= 1,
+		.colplanes	= 3,
+		.flags		= FMT_FLAGS_M2M,
+	}, {
 		.name		= "YUV 4:2:0 planar, Y/CbCr",
 		.fourcc		= V4L2_PIX_FMT_NV12,
 		.depth		= { 12 },
@@ -135,6 +160,14 @@ static struct fimc_fmt fimc_formats[] = {
 		.colplanes	= 2,
 		.flags		= FMT_FLAGS_M2M,
 	}, {
+		.name		= "YUV 4:2:0 planar, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_NV21,
+		.depth		= { 12 },
+		.color		= S5P_FIMC_YCRCB420,
+		.memplanes	= 1,
+		.colplanes	= 2,
+		.flags		= FMT_FLAGS_M2M,
+	}, {
 		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 		.fourcc		= V4L2_PIX_FMT_NV12M,
 		.color		= S5P_FIMC_YCBCR420,
@@ -151,6 +184,14 @@ static struct fimc_fmt fimc_formats[] = {
 		.colplanes	= 3,
 		.flags		= FMT_FLAGS_M2M,
 	}, {
+		.name		= "YUV 4:2:0 non-contiguous 3-planar, Y/Cr/Cb",
+		.fourcc		= V4L2_PIX_FMT_YVU420M,
+		.color		= S5P_FIMC_YCBCR420,
+		.depth		= { 8, 2, 2 },
+		.memplanes	= 3,
+		.colplanes	= 3,
+		.flags		= FMT_FLAGS_M2M,
+	}, {
 		.name		= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 		.fourcc		= V4L2_PIX_FMT_NV12MT,
 		.color		= S5P_FIMC_YCBCR420,
@@ -158,6 +199,15 @@ static struct fimc_fmt fimc_formats[] = {
 		.memplanes	= 2,
 		.colplanes	= 2,
 		.flags		= FMT_FLAGS_M2M,
+	}, {
+		.name		= "JPEG encoded data",
+		.fourcc		= V4L2_PIX_FMT_JPEG,
+		.color		= S5P_FIMC_JPEG,
+		.depth		= { 8 },
+		.memplanes	= 1,
+		.colplanes	= 1,
+		.mbus_code	= V4L2_MBUS_FMT_JPEG_1X8,
+		.flags		= FMT_FLAGS_CAM,
 	},
 };
 
@@ -184,6 +234,28 @@ static struct v4l2_queryctrl fimc_ctrls[] = {
 		.maximum	= 270,
 		.step		= 90,
 		.default_value	= 0,
+	}, {
+		.id		= V4L2_CID_GLOBAL_ALPHA,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Set RGB alpha",
+		.minimum	= 0,
+		.maximum	= 255,
+		.step		= 1,
+		.default_value	= 0,
+	}, {
+		.id		= V4L2_CID_CACHEABLE,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Enable cache configuration",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 0,
+	}, {
+		.id		= V4L2_CID_SET_SHAREABLE,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Enable cache configuration",
+		.minimum	= 3,
+		.maximum	= 256,
+		.default_value	= 0,
 	},
 };
 
@@ -198,7 +270,8 @@ static struct v4l2_queryctrl *get_ctrl(int id)
 	return NULL;
 }
 
-int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
+int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
+			    int dw, int dh, int rot)
 {
 	int tx, ty;
 
@@ -210,6 +283,9 @@ int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
 		ty = dh;
 	}
 
+	if (!ctx->scaler.enabled)
+		return (sw == tx && sh == ty) ? 0 : -EINVAL;
+
 	if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
 		return -EINVAL;
 
@@ -242,7 +318,10 @@ int fimc_set_scaler_info(struct fimc_ctx *ctx)
 	struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 	int tx, ty, sx, sy;
 	int ret;
-
+	dbg("%s : d_frame->width : %d, d_frame->height : %d\n", __func__,
+			d_frame->width, d_frame->height);
+	dbg("%s : s_frame->width : %d, s_frame->height : %d\n", __func__,
+			s_frame->width, s_frame->height);
 	if (ctx->rotation == 90 || ctx->rotation == 270) {
 		ty = d_frame->width;
 		tx = d_frame->height;
@@ -256,8 +335,13 @@ int fimc_set_scaler_info(struct fimc_ctx *ctx)
 		return -EINVAL;
 	}
 
-	sx = s_frame->width;
-	sy = s_frame->height;
+	if (ctx->fimc_dev->vid_cap.is.sd || ctx->fimc_dev->vid_cap.is.camcording) {
+		sx = ctx->fimc_dev->vid_cap.is.fmt.width;
+		sy = ctx->fimc_dev->vid_cap.is.fmt.height;
+	} else {
+		sx = s_frame->width;
+		sy = s_frame->height;
+	}
 	if (sx <= 0 || sy <= 0) {
 		err("invalid source size: %d x %d", sx, sy);
 		return -EINVAL;
@@ -265,6 +349,11 @@ int fimc_set_scaler_info(struct fimc_ctx *ctx)
 	sc->real_width = sx;
 	sc->real_height = sy;
 
+	dbg("%s : d_frame->width : %d, d_frame->height : %d\n", __func__,
+			tx, ty);
+	dbg("%s : s_frame->width : %d, s_frame->height : %d\n", __func__,
+			sx, sy);
+
 	ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 	if (ret)
 		return ret;
@@ -299,88 +388,126 @@ int fimc_set_scaler_info(struct fimc_ctx *ctx)
 	return 0;
 }
 
-static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
+static void fimc_runtime_get(struct fimc_dev *fimc)
 {
-	struct vb2_buffer *src_vb, *dst_vb;
-	struct fimc_dev *fimc = ctx->fimc_dev;
-
-	if (!ctx || !ctx->m2m_ctx)
-		return;
+	pm_runtime_get_sync(&fimc->pdev->dev);
+	fimc->vb2->resume(fimc->alloc_ctx);
+}
 
-	src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
-	dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+static void fimc_runtime_put(struct fimc_dev *fimc)
+{
+	fimc->vb2->suspend(fimc->alloc_ctx);
+	pm_runtime_put_sync(&fimc->pdev->dev);
+}
 
-	if (src_vb && dst_vb) {
-		v4l2_m2m_buf_done(src_vb, vb_state);
-		v4l2_m2m_buf_done(dst_vb, vb_state);
-		v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
+void fimc_wq_suspend(struct work_struct *work)
+{
+	struct fimc_dev *fimc = container_of(work, struct fimc_dev,
+					     work_struct);
+	if (!fimc_m2m_run(fimc)) {
+		clear_bit(ST_PWR_ON, &fimc->state);
+		fimc_runtime_put(fimc);
 	}
 }
 
-/* Complete the transaction which has been scheduled for execution. */
-static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
+static int fimc_ctx_stop_req(struct fimc_ctx *ctx)
 {
+	struct fimc_ctx *curr_ctx;
 	struct fimc_dev *fimc = ctx->fimc_dev;
-	int ret;
-
-	if (!fimc_m2m_pending(fimc))
-		return;
-
-	fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
+	int ret = 0;
 
+	curr_ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
+	if (!fimc_m2m_run(fimc) || (curr_ctx != ctx))
+		return 0;
+	ctx->state |= FIMC_CTX_STOP_REQ;
 	ret = wait_event_timeout(fimc->irq_queue,
-			   !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
-			   FIMC_SHUTDOWN_TIMEOUT);
-	/*
-	 * In case of a timeout the buffers are not released in the interrupt
-	 * handler so return them here with the error flag set, if there are
-	 * any on the queue.
-	 */
-	if (ret == 0)
-		fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
+			!fimc_ctx_state_is_set(FIMC_CTX_STOP_REQ, ctx),
+			FIMC_SHUTDOWN_TIMEOUT);
+	if (!ret)
+		ret = -EBUSY;
+
+	return ret;
 }
 
 static int stop_streaming(struct vb2_queue *q)
 {
 	struct fimc_ctx *ctx = q->drv_priv;
+	struct fimc_dev *fimc = ctx->fimc_dev;
+	int ret;
+
+	ret = fimc_ctx_stop_req(ctx);
+	/* FIXME: need to add v4l2_m2m_job_finish(fail) if ret is timeout */
+	if (ret < 0)
+		dev_err(&fimc->pdev->dev, "wait timeout : %s\n", __func__);
 
-	fimc_m2m_shutdown(ctx);
+	v4l2_m2m_get_next_job(fimc->m2m.m2m_dev, ctx->m2m_ctx);
 
 	return 0;
 }
 
-static void fimc_capture_irq_handler(struct fimc_dev *fimc)
+void fimc_capture_irq_handler(struct fimc_dev *fimc)
 {
 	struct fimc_vid_cap *cap = &fimc->vid_cap;
 	struct fimc_vid_buffer *v_buf;
-	struct timeval *tv;
-	struct timespec ts;
+	struct v4l2_control is_ctrl;
+	u32 is_fn;
 
 	if (!list_empty(&cap->active_buf_q) &&
 	    test_bit(ST_CAPT_RUN, &fimc->state)) {
-		ktime_get_real_ts(&ts);
-
 		v_buf = active_queue_pop(cap);
-
-		tv = &v_buf->vb.v4l2_buf.timestamp;
-		tv->tv_sec = ts.tv_sec;
-		tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
-		v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
-
 		vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 	}
 
-	if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
-		wake_up(&fimc->irq_queue);
-		return;
-	}
-
 	if (!list_empty(&cap->pending_buf_q)) {
 
 		v_buf = pending_queue_pop(cap);
 		fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 		v_buf->index = cap->buf_index;
 
+		dbg("hw ptr: %d, sw ptr: %d",
+		    fimc_hw_get_frame_index(fimc), cap->buf_index);
+
+		/* frame management for FIMC-IS */
+		if (fimc->vid_cap.is.sd) {
+			is_ctrl.id = V4L2_CID_IS_GET_FRAME_NUMBER;
+			v4l2_subdev_call(fimc->vid_cap.is.sd, core, g_ctrl, &is_ctrl);
+			is_fn = is_ctrl.value;
+			if (fimc->vid_cap.is.frame_count == is_fn) {
+				is_ctrl.id = V4L2_CID_IS_GET_FRAME_VALID;
+				v4l2_subdev_call(fimc->vid_cap.is.sd, core, g_ctrl,
+					&is_ctrl);
+				if (is_ctrl.value) {
+					is_ctrl.id =
+						V4L2_CID_IS_SET_FRAME_VALID;
+					is_ctrl.value = 0;
+					v4l2_subdev_call(fimc->vid_cap.is.sd,
+						core, s_ctrl, &is_ctrl);
+				} else {
+					dbg(
+					"Invalid frame - fn %d\n", is_fn);
+					is_ctrl.id =
+						V4L2_CID_IS_SET_FRAME_VALID;
+					is_ctrl.value = 0;
+					v4l2_subdev_call(fimc->vid_cap.is.sd,
+						core, s_ctrl, &is_ctrl);
+				}
+				fimc->vid_cap.is.frame_count++;
+			} else {
+			/* Frame lost case */
+				is_ctrl.id =
+					V4L2_CID_IS_GET_LOSTED_FRAME_NUMBER;
+				v4l2_subdev_call(fimc->vid_cap.is.sd,
+					core, g_ctrl, &is_ctrl);
+				dbg("%d Frame lost - %d,%d",
+					(is_ctrl.value-fimc->vid_cap.is.frame_count),
+					fimc->vid_cap.is.frame_count, is_ctrl.value);
+				fimc->vid_cap.is.frame_count = is_ctrl.value;
+				is_ctrl.id = V4L2_CID_IS_CLEAR_FRAME_NUMBER;
+				is_ctrl.value = fimc->vid_cap.is.frame_count;
+				v4l2_subdev_call(fimc->vid_cap.is.sd,
+					core, s_ctrl, &is_ctrl);
+			}
+		}
 		/* Move the buffer to the capture active queue */
 		active_queue_add(cap, v_buf);
 
@@ -396,6 +523,8 @@ static void fimc_capture_irq_handler(struct fimc_dev *fimc)
 
 		if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 			cap->buf_index = 0;
+		if (test_and_clear_bit(ST_PWR_ON, &fimc->state))
+			fimc_runtime_put(fimc);
 	} else {
 		set_bit(ST_CAPT_RUN, &fimc->state);
 	}
@@ -404,41 +533,62 @@ static void fimc_capture_irq_handler(struct fimc_dev *fimc)
 	    fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 }
 
-static irqreturn_t fimc_isr(int irq, void *priv)
+static irqreturn_t fimc_irq_handler(int irq, void *priv)
 {
 	struct fimc_dev *fimc = priv;
 	struct fimc_vid_cap *cap = &fimc->vid_cap;
-	struct fimc_ctx *ctx;
+	bool jpeg_capt = false;
+	bool is_set = false;
 
 	fimc_hw_clear_irq(fimc);
+	spin_lock(&fimc->slock);
 
-	if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
-		ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
-		if (ctx != NULL) {
-			fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
-
-			spin_lock(&ctx->slock);
-			if (ctx->state & FIMC_CTX_SHUT) {
-				ctx->state &= ~FIMC_CTX_SHUT;
+	if (test_and_clear_bit(ST_M2M_RUN, &fimc->state)) {
+		struct vb2_buffer *src_vb, *dst_vb;
+		struct fimc_ctx *ctx =
+			v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
+
+		if (!ctx || !ctx->m2m_ctx)
+			goto isr_unlock;
+
+		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+		if (src_vb && dst_vb) {
+			v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
+			v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
+
+			if (test_and_clear_bit(ST_M2M_STOP_REQ, &fimc->state))
+				wake_up(&fimc->irq_queue); /* wake_up APM suspend */
+			else
+				v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
+
+			is_set = fimc_ctx_state_is_set(FIMC_CTX_STOP_REQ, ctx);
+			ctx->state &= ~FIMC_CTX_STOP_REQ;
+			/* wake_up job_abort, stop_streaming */
+			if (is_set)
 				wake_up(&fimc->irq_queue);
-			}
-			spin_unlock(&ctx->slock);
-		}
 
-		return IRQ_HANDLED;
+			if (!fimc_m2m_run(fimc)) /* No job */
+				queue_work(fimc->irq_workqueue, &fimc->work_struct);
+
+			goto isr_unlock;
+		} else {
+			dev_err(&fimc->pdev->dev, "failed to get the buffer done\n");
+			goto isr_unlock;
+		}
 	}
 
-	spin_lock(&fimc->slock);
+	if (cap && cap->ctx && cap->ctx->d_frame.fmt)
+		jpeg_capt = fimc_fmt_is_jpeg(cap->ctx->d_frame.fmt->color);
 
-	if (test_bit(ST_CAPT_PEND, &fimc->state)) {
+	if (test_bit(ST_CAPT_PEND, &fimc->state))
 		fimc_capture_irq_handler(fimc);
 
-		if (cap->active_buf_cnt == 1) {
-			fimc_deactivate_capture(fimc);
-			clear_bit(ST_CAPT_STREAM, &fimc->state);
-		}
+	if (cap->active_buf_cnt == 1 && !jpeg_capt) {
+		fimc_deactivate_capture(fimc);
+		clear_bit(ST_CAPT_STREAM, &fimc->state);
 	}
-
+isr_unlock:
 	spin_unlock(&fimc->slock);
 	return IRQ_HANDLED;
 }
@@ -447,6 +597,7 @@ static irqreturn_t fimc_isr(int irq, void *priv)
 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 		      struct fimc_frame *frame, struct fimc_addr *paddr)
 {
+	struct fimc_dev *fimc = ctx->fimc_dev;
 	int ret = 0;
 	u32 pix_size;
 
@@ -458,7 +609,7 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 	dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 		frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 
-	paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
+	paddr->y = fimc->vb2->plane_addr(vb, 0);
 
 	if (frame->fmt->memplanes == 1) {
 		switch (frame->fmt->colplanes) {
@@ -486,10 +637,10 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 		}
 	} else {
 		if (frame->fmt->memplanes >= 2)
-			paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
+			paddr->cb = fimc->vb2->plane_addr(vb, 1);
 
 		if (frame->fmt->memplanes == 3)
-			paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
+			paddr->cr = fimc->vb2->plane_addr(vb, 2);
 	}
 
 	dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
@@ -607,9 +758,6 @@ int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 		fimc_set_yuv_order(ctx);
 	}
 
-	/* Input DMA mode is not allowed when the scaler is disabled. */
-	ctx->scaler.enabled = 1;
-
 	if (flags & FIMC_SRC_ADDR) {
 		vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 		ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
@@ -631,57 +779,66 @@ static void fimc_dma_run(void *priv)
 	struct fimc_dev *fimc;
 	unsigned long flags;
 	u32 ret;
+	bool is_set = false;
 
 	if (WARN(!ctx, "null hardware context\n"))
 		return;
 
 	fimc = ctx->fimc_dev;
 
-	spin_lock_irqsave(&ctx->slock, flags);
-	set_bit(ST_M2M_PEND, &fimc->state);
-
-	ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
-	ret = fimc_prepare_config(ctx, ctx->state);
-	if (ret)
-		goto dma_unlock;
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		fimc_runtime_get(fimc);
 
+	spin_lock_irqsave(&ctx->slock, flags);
 	/* Reconfigure hardware if the context has changed. */
 	if (fimc->m2m.ctx != ctx) {
 		ctx->state |= FIMC_PARAMS;
 		fimc->m2m.ctx = ctx;
 	}
 
-	spin_lock(&fimc->slock);
+	is_set = (ctx->state & FIMC_CTX_STOP_REQ) ? 1 : 0;
+	ctx->state &= ~FIMC_CTX_STOP_REQ;
+	if (is_set) {
+		wake_up(&fimc->irq_queue);
+		goto dma_unlock;
+	}
+
+	ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
+	ret = fimc_prepare_config(ctx, ctx->state);
+	if (ret) {
+		err("Wrong parameters");
+		goto dma_unlock;
+	}
+
+	set_bit(ST_M2M_RUN, &fimc->state);
+
 	fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
+	fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 
 	if (ctx->state & FIMC_PARAMS) {
 		fimc_hw_set_input_path(ctx);
 		fimc_hw_set_in_dma(ctx);
-		ret = fimc_set_scaler_info(ctx);
-		if (ret) {
-			spin_unlock(&fimc->slock);
+		if (fimc_set_scaler_info(ctx)) {
+			err("Scaler setup error");
 			goto dma_unlock;
 		}
+
 		fimc_hw_set_prescaler(ctx);
 		fimc_hw_set_mainscaler(ctx);
 		fimc_hw_set_target_format(ctx);
 		fimc_hw_set_rotation(ctx);
 		fimc_hw_set_effect(ctx);
-	}
-
-	fimc_hw_set_output_path(ctx);
-	if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
-		fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
-
-	if (ctx->state & FIMC_PARAMS)
 		fimc_hw_set_out_dma(ctx);
+		fimc_hw_set_rgb_alpha(ctx);
+	}
 
 	fimc_activate_capture(ctx);
 
-	ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
-		       FIMC_SRC_FMT | FIMC_DST_FMT);
+	ctx->state &= ~FIMC_PARAMS;
+	ctx->state &= ~FIMC_SRC_ADDR;
+	ctx->state &= ~FIMC_DST_ADDR;
+
 	fimc_hw_activate_input_dma(fimc, true);
-	spin_unlock(&fimc->slock);
 
 dma_unlock:
 	spin_unlock_irqrestore(&ctx->slock, flags);
@@ -689,7 +846,16 @@ dma_unlock:
 
 static void fimc_job_abort(void *priv)
 {
-	fimc_m2m_shutdown(priv);
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *fimc = ctx->fimc_dev;
+	int ret;
+
+	ret = fimc_ctx_stop_req(ctx);
+	/* FIXME: need to add v4l2_m2m_job_finish(fail) if ret is timeout */
+	if (ret < 0)
+		dev_err(&fimc->pdev->dev, "wait timeout : %s\n", __func__);
+
+	v4l2_m2m_get_next_job(fimc->m2m.m2m_dev, ctx->m2m_ctx);
 }
 
 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
@@ -721,6 +887,7 @@ static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
 static int fimc_buf_prepare(struct vb2_buffer *vb)
 {
 	struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_frame *frame;
 	int i;
 
@@ -731,6 +898,9 @@ static int fimc_buf_prepare(struct vb2_buffer *vb)
 	for (i = 0; i < frame->fmt->memplanes; i++)
 		vb2_set_plane_payload(vb, i, frame->payload[i]);
 
+	if (frame->cacheable)
+		fimc->vb2->cache_flush(vb, frame->fmt->memplanes);
+
 	return 0;
 }
 
@@ -746,17 +916,21 @@ static void fimc_buf_queue(struct vb2_buffer *vb)
 
 static void fimc_lock(struct vb2_queue *vq)
 {
+#ifdef FOR_DIFF_VER
 	struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 	mutex_lock(&ctx->fimc_dev->lock);
+#endif
 }
 
 static void fimc_unlock(struct vb2_queue *vq)
 {
+#ifdef FOR_DIFF_VER
 	struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 	mutex_unlock(&ctx->fimc_dev->lock);
+#endif
 }
 
-static struct vb2_ops fimc_qops = {
+struct vb2_ops fimc_qops = {
 	.queue_setup	 = fimc_queue_setup,
 	.buf_prepare	 = fimc_buf_prepare,
 	.buf_queue	 = fimc_buf_queue,
@@ -875,7 +1049,6 @@ int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
 	u32 max_width, mod_x, mod_y, mask;
 	int i, is_output = 0;
 
-
 	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 		if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
 			return -EINVAL;
@@ -902,21 +1075,34 @@ int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
 	if (is_output) {
 		max_width = variant->pix_limit->scaler_dis_w;
 		mod_x = ffs(variant->min_inp_pixsize) - 1;
+		mod_y = 0;
 	} else {
 		max_width = variant->pix_limit->out_rot_dis_w;
 		mod_x = ffs(variant->min_out_pixsize) - 1;
+		mod_y = (fmt->color == S5P_FIMC_YCBCR420) ? 1 : 0;
 	}
 
-	if (tiled_fmt(fmt)) {
-		mod_x = 6; /* 64 x 32 pixels tile */
+	switch (fmt->fourcc) {
+	case V4L2_PIX_FMT_NV12M:
+		mod_x = 4; /* 16 x 16 pixels align */
+		mod_y = 4;
+		break;
+	case V4L2_PIX_FMT_NV12MT:
+		mod_x = 7; /* 128 x 32 pixels tiled align */
 		mod_y = 5;
-	} else {
-		if (fimc->id == 1 && variant->pix_hoff)
-			mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
-		else
-			mod_y = mod_x;
+		break;
+	default:
+		/*
+		 * "Don't need to modify alignments
+		 */
+		break;
 	}
 
+	if (variant->pix_hoff)
+		mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
+	else
+		mod_y = mod_x;
+
 	dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
 
 	v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
@@ -925,28 +1111,62 @@ int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
 	pix->num_planes = fmt->memplanes;
 	pix->colorspace	= V4L2_COLORSPACE_JPEG;
 
-
 	for (i = 0; i < pix->num_planes; ++i) {
-		u32 bpl = pix->plane_fmt[i].bytesperline;
-		u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
+		int bpl = pix->plane_fmt[i].bytesperline;
+
+		dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
+		    i, bpl, fmt->depth[i], pix->width, pix->height);
 
-		if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
-			bpl = pix->width; /* Planar */
+		if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
+			bpl = (pix->width * fmt->depth[i]) >> 3;
 
-		if (fmt->colplanes == 1 && /* Packed */
-		    (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
-			bpl = (pix->width * fmt->depth[0]) / 8;
+		/* Support jpegbypass mode */
+		if (fmt->fourcc == V4L2_PIX_FMT_JPEG) {
+			struct v4l2_control ctrl;
+			ctrl.id = V4L2_CID_CAM_JPEG_MEMSIZE;
+			v4l2_subdev_call(fimc->vid_cap.sd, core, g_ctrl,
+					&ctrl);
+			pix->plane_fmt[i].sizeimage = ctrl.value;
+		}
+		if (!pix->plane_fmt[i].sizeimage)
+			pix->plane_fmt[i].sizeimage = pix->height * bpl;
+
+		/* Support to format NV12M & NV12TM for MFC */
+		if (fmt->fourcc == V4L2_PIX_FMT_NV12M ||
+		    fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
+			unsigned int alignment;
+			alignment =
+			(fmt->fourcc == V4L2_PIX_FMT_NV12M) ? SZ_2K : SZ_8K;
+			pix->plane_fmt[i].sizeimage =
+				ALIGN(pix->height * bpl, alignment);
+
+		}
 
-		if (i == 0) /* Same bytesperline for each plane. */
-			mod_x = bpl;
+		pix->plane_fmt[i].bytesperline = bpl;
 
-		pix->plane_fmt[i].bytesperline = mod_x;
-		*sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
+		dbg("[%d]: bpl: %d, sizeimage: %d",
+		    i, pix->plane_fmt[i].bytesperline,
+		    pix->plane_fmt[i].sizeimage);
 	}
 
 	return 0;
 }
 
+void fimc_set_frame_size_mp(struct fimc_frame *frame, struct v4l2_format *f)
+{
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+
+	frame->f_width	= pixm->plane_fmt[0].bytesperline * 8 /
+		frame->fmt->depth[0];
+	frame->f_height	= pixm->height;
+	frame->width	= pixm->width;
+	frame->height	= pixm->height;
+	frame->o_width	= pixm->width;
+	frame->o_height = pixm->height;
+	frame->offs_h	= 0;
+	frame->offs_v	= 0;
+}
+
 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
 				 struct v4l2_format *f)
 {
@@ -963,7 +1183,7 @@ static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
 
 	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
 
-	if (vb2_is_busy(vq)) {
+	if (vb2_is_streaming(vq)) {
 		v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
 		return -EBUSY;
 	}
@@ -983,20 +1203,13 @@ static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
 	if (!frame->fmt)
 		return -EINVAL;
 
-	for (i = 0; i < frame->fmt->colplanes; i++) {
+	for (i = 0; i < frame->fmt->colplanes; i++)
 		frame->payload[i] =
-			(pix->width * pix->height * frame->fmt->depth[i]) / 8;
-	}
+			pix->plane_fmt[i].bytesperline * pix->height;
 
-	frame->f_width	= pix->plane_fmt[0].bytesperline * 8 /
-		frame->fmt->depth[0];
-	frame->f_height	= pix->height;
-	frame->width	= pix->width;
-	frame->height	= pix->height;
-	frame->o_width	= pix->width;
-	frame->o_height = pix->height;
-	frame->offs_h	= 0;
-	frame->offs_v	= 0;
+	fimc_set_frame_size_mp(frame, f);
+
+	ctx->scaler.enabled = 1;
 
 	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 		fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
@@ -1012,6 +1225,13 @@ static int fimc_m2m_reqbufs(struct file *file, void *priv,
 			  struct v4l2_requestbuffers *reqbufs)
 {
 	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *fimc = ctx->fimc_dev;
+	struct fimc_frame *frame;
+
+	frame = ctx_get_frame(ctx, reqbufs->type);
+	frame->cacheable = ctx->cacheable;
+	fimc->vb2->set_cacheable(fimc->alloc_ctx, frame->cacheable);
+
 	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
 }
 
@@ -1026,7 +1246,6 @@ static int fimc_m2m_qbuf(struct file *file, void *priv,
 			  struct v4l2_buffer *buf)
 {
 	struct fimc_ctx *ctx = priv;
-
 	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
 }
 
@@ -1073,7 +1292,7 @@ int fimc_vidioc_queryctrl(struct file *file, void *priv,
 		return 0;
 	}
 
-	if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
+	if (ctx->state & FIMC_CTX_CAP) {
 		return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
 					core, queryctrl, qc);
 	}
@@ -1096,12 +1315,16 @@ int fimc_vidioc_g_ctrl(struct file *file, void *priv,
 	case V4L2_CID_ROTATE:
 		ctrl->value = ctx->rotation;
 		break;
+	case V4L2_CID_CACHEABLE:
+		ctrl->value = (int)ctx->cacheable;
+		break;
 	default:
-		if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
+		if (ctx->state & FIMC_CTX_CAP) {
 			return v4l2_subdev_call(fimc->vid_cap.sd, core,
 						g_ctrl, ctrl);
 		} else {
-			v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
+			v4l2_err(&fimc->m2m.v4l2_dev,
+				 "Invalid control\n");
 			return -EINVAL;
 		}
 	}
@@ -1133,6 +1356,12 @@ int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	int ret = 0;
 
+	if (fimc_fmt_is_jpeg(ctx->d_frame.fmt->color) &&
+	    (ctrl->id == V4L2_CID_HFLIP ||
+	     ctrl->id == V4L2_CID_VFLIP ||
+	     ctrl->id == V4L2_CID_ROTATE))
+		    return -EINVAL;
+
 	switch (ctrl->id) {
 	case V4L2_CID_HFLIP:
 		if (ctrl->value)
@@ -1150,21 +1379,33 @@ int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
 
 	case V4L2_CID_ROTATE:
 		if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
-			ret = fimc_check_scaler_ratio(ctx->s_frame.width,
+			ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 					ctx->s_frame.height, ctx->d_frame.width,
 					ctx->d_frame.height, ctrl->value);
 		}
 
-		if (ret) {
+			if (ret) {
 			v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
-			return -EINVAL;
-		}
+				return -EINVAL;
+			}
 
 		/* Check for the output rotator availability */
 		if ((ctrl->value == 90 || ctrl->value == 270) &&
 		    (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
 			return -EINVAL;
-		ctx->rotation = ctrl->value;
+			ctx->rotation = ctrl->value;
+		break;
+
+	case V4L2_CID_GLOBAL_ALPHA:
+		ctx->d_frame.alpha = ctrl->value;
+		break;
+
+	case V4L2_CID_CACHEABLE:
+		ctx->cacheable = (bool)ctrl->value;
+		break;
+
+	case V4L2_CID_SET_SHAREABLE:
+		fimc->vb2->set_sharable(fimc->alloc_ctx, ctrl->value);
 		break;
 
 	default:
@@ -1231,8 +1472,10 @@ int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
 {
 	struct fimc_dev *fimc = ctx->fimc_dev;
 	struct fimc_frame *f;
-	u32 min_size, halign, depth = 0;
+	u32 min_size, depth = 0;
 	bool is_capture_ctx;
+	u32 walign = 0;
+	u32 halign = 0;
 	int i;
 
 	if (cr->c.top < 0 || cr->c.left < 0) {
@@ -1254,24 +1497,28 @@ int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
 	min_size = (f == &ctx->s_frame) ?
 		fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
 
-	/* Get pixel alignment constraints. */
-	if (is_capture_ctx) {
+	if (!is_capture_ctx) {
+		if (fimc->variant->has_mainscaler_ext) {
+			if (V4L2_TYPE_IS_OUTPUT(cr->type))
+				walign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
+
+			if (f->fmt->color == S5P_FIMC_YCBCR420)
+				halign = 1;
+		} else {
+			walign = ffs(min_size) - 1;
+		}
+	/* there are more strict aligment requirements at camera interface */
+	} else {
 		min_size = 16;
 		halign = 4;
-	} else {
-		if (fimc->id == 1 && fimc->variant->pix_hoff)
-			halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
-		else
-			halign = ffs(min_size) - 1;
+		walign = 4;
 	}
 
 	for (i = 0; i < f->fmt->colplanes; i++)
 		depth += f->fmt->depth[i];
 
-	v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
-			      ffs(min_size) - 1,
-			      &cr->c.height, min_size, f->o_height,
-			      halign, 64/(ALIGN(depth, 8)));
+	v4l_bound_align_image(&cr->c.width, min_size, f->o_width, walign,
+			      &cr->c.height, min_size, f->o_height, halign, 0);
 
 	/* adjust left/top if cropping rectangle is out of bounds */
 	if (cr->c.left + cr->c.width > f->o_width)
@@ -1280,11 +1527,11 @@ int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
 		cr->c.top = f->o_height - cr->c.height;
 
 	cr->c.left = round_down(cr->c.left, min_size);
-	cr->c.top  = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
+	cr->c.top  = round_down(cr->c.top,
+				ctx->state & FIMC_CTX_M2M ? 8 : 16);
 
 	dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
-	    cr->c.left, cr->c.top, cr->c.width, cr->c.height,
-	    f->f_width, f->f_height);
+	    cr->c.left, cr->c.top, cr->c.width, cr->c.height, f->f_width, f->f_height);
 
 	return 0;
 }
@@ -1306,12 +1553,12 @@ static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
 	/* Check to see if scaling ratio is within supported range */
 	if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
 		if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
-			ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
+			ret = fimc_check_scaler_ratio(ctx, cr->c.width, cr->c.height,
 						      ctx->d_frame.width,
 						      ctx->d_frame.height,
 						      ctx->rotation);
 		} else {
-			ret = fimc_check_scaler_ratio(ctx->s_frame.width,
+			ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 						      ctx->s_frame.height,
 						      cr->c.width, cr->c.height,
 						      ctx->rotation);
@@ -1377,7 +1624,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq,
 	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
 	src_vq->drv_priv = ctx;
 	src_vq->ops = &fimc_qops;
-	src_vq->mem_ops = &vb2_dma_contig_memops;
+	src_vq->mem_ops = ctx->fimc_dev->vb2->ops;
 	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 
 	ret = vb2_queue_init(src_vq);
@@ -1389,7 +1636,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq,
 	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
 	dst_vq->drv_priv = ctx;
 	dst_vq->ops = &fimc_qops;
-	dst_vq->mem_ops = &vb2_dma_contig_memops;
+	dst_vq->mem_ops = ctx->fimc_dev->vb2->ops;
 	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 
 	return vb2_queue_init(dst_vq);
@@ -1407,11 +1654,11 @@ static int fimc_m2m_open(struct file *file)
 	 * Return if the corresponding video capture node
 	 * is already opened.
 	 */
-	if (fimc->vid_cap.refcnt > 0)
+	if (fimc_capture_opened(fimc))
 		return -EBUSY;
 
 	fimc->m2m.refcnt++;
-	set_bit(ST_OUTDMA_RUN, &fimc->state);
+	set_bit(ST_M2M_OPEN, &fimc->state);
 
 	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
 	if (!ctx)
@@ -1423,7 +1670,7 @@ static int fimc_m2m_open(struct file *file)
 	ctx->s_frame.fmt = &fimc_formats[0];
 	ctx->d_frame.fmt = &fimc_formats[0];
 	/* Setup the device context for mem2mem mode. */
-	ctx->state = FIMC_CTX_M2M;
+	ctx->state |= FIMC_CTX_M2M;
 	ctx->flags = 0;
 	ctx->in_path = FIMC_DMA;
 	ctx->out_path = FIMC_DMA;
@@ -1450,7 +1697,7 @@ static int fimc_m2m_release(struct file *file)
 	v4l2_m2m_ctx_release(ctx->m2m_ctx);
 	kfree(ctx);
 	if (--fimc->m2m.refcnt <= 0)
-		clear_bit(ST_OUTDMA_RUN, &fimc->state);
+		clear_bit(ST_M2M_OPEN, &fimc->state);
 
 	return 0;
 }
@@ -1503,7 +1750,7 @@ static int fimc_register_m2m_device(struct fimc_dev *fimc)
 		snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
 			 "%s.m2m", dev_name(&pdev->dev));
 
-	ret = v4l2_device_register(&pdev->dev, v4l2_dev);
+	ret = v4l2_device_register(NULL, v4l2_dev);
 	if (ret)
 		goto err_m2m_r1;
 
@@ -1517,8 +1764,9 @@ static int fimc_register_m2m_device(struct fimc_dev *fimc)
 	vfd->ioctl_ops	= &fimc_m2m_ioctl_ops;
 	vfd->minor	= -1;
 	vfd->release	= video_device_release;
-	vfd->lock	= &fimc->lock;
-
+#ifdef FOR_DIFF_VER
+	vfd->ulock	= &fimc->lock;
+#endif
 	snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
 
 	video_set_drvdata(vfd, fimc);
@@ -1563,14 +1811,29 @@ static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
 	}
 }
 
-static void fimc_clk_release(struct fimc_dev *fimc)
+static void fimc_clk_disable(struct fimc_dev *fimc)
 {
 	int i;
 	for (i = 0; i < fimc->num_clocks; i++) {
-		if (fimc->clock[i]) {
+		if (fimc->clock[i])
 			clk_disable(fimc->clock[i]);
+	}
+}
+
+static void fimc_clk_enable(struct fimc_dev *fimc)
+{
+	int i;
+
+	for (i = 0; i < fimc->num_clocks; i++)
+		clk_enable(fimc->clock[i]);
+}
+
+static void fimc_clk_release(struct fimc_dev *fimc)
+{
+	int i;
+	for (i = 0; i < fimc->num_clocks; i++) {
+		if (fimc->clock[i])
 			clk_put(fimc->clock[i]);
-		}
 	}
 }
 
@@ -1579,15 +1842,127 @@ static int fimc_clk_get(struct fimc_dev *fimc)
 	int i;
 	for (i = 0; i < fimc->num_clocks; i++) {
 		fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
+		if (IS_ERR_OR_NULL(fimc->clock[i])) {
+			dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
+				fimc_clocks[i]);
+			return -ENXIO;
+		}
+	}
+
+	return 0;
+}
+
+int fimc_clk_setrate(struct fimc_dev *fimc, int clk_num, void *pdata)
+{
+	struct clk *srclk;
+
+	if (clk_num == CLK_BUS) {
+		struct samsung_fimc_driverdata *drv_data =
+			(struct samsung_fimc_driverdata *)pdata;
+		if (soc_is_exynos4212() || soc_is_exynos4412())
+			srclk = clk_get(&fimc->pdev->dev, "mout_mpll_user");
+		else
+			srclk = clk_get(&fimc->pdev->dev, "mout_mpll");
+		if (IS_ERR_OR_NULL(srclk)) {
+			dev_err(&fimc->pdev->dev, "failed to get fimc source clock\n");
+			return -ENXIO;
+		}
+		clk_set_parent(fimc->clock[clk_num], srclk);
+		clk_put(srclk);
+		clk_set_rate(fimc->clock[clk_num], drv_data->lclk_frequency);
+	} else if ((clk_num == CLK_CAM0) || (clk_num == CLK_CAM1)) {
+		struct s5p_fimc_isp_info *isp_info =
+			(struct s5p_fimc_isp_info *)pdata;
+		srclk = clk_get(&fimc->pdev->dev, CAM_SRC_CLOCK);
+		if (IS_ERR_OR_NULL(srclk)) {
+			dev_err(&fimc->pdev->dev, "failed to get camera source clock\n");
+			return -ENXIO;
+		}
+		clk_set_parent(fimc->clock[clk_num], srclk);
+		clk_put(srclk);
+		clk_set_rate(fimc->clock[clk_num], isp_info->clk_frequency);
+	}
+
+	return 0;
+}
+
+static int fimc_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct fimc_dev *fimc = (struct fimc_dev *)platform_get_drvdata(pdev);
+
+	if (fimc_capture_camera(fimc)) {
+		dbg("camera mode, power block should not off\n");
+		pm_runtime_forbid(fimc->pdev->dev.parent);
+	} else if (fimc_capture_writeback(fimc)) {
+		dbg("writeback mode, it is possibility of power off\n");
+		fimc_hw_save_output_addr(fimc);
+	}
+
+	fimc->m2m.ctx = NULL;
+	fimc_clk_disable(fimc);
+
+	return 0;
+}
+
+static int fimc_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct fimc_dev *fimc = (struct fimc_dev *)platform_get_drvdata(pdev);
+	struct fimc_vid_cap *cap = &fimc->vid_cap;
+	struct fimc_ctx *ctx = cap->ctx;
+	struct samsung_fimc_driverdata *drv_data;
+	int ret;
+
+	fimc_clk_enable(fimc);
+
+	if (fimc_capture_camera(fimc)) {
+		dbg("camera mode, allowed lock of power block\n");
+		pm_runtime_allow(fimc->pdev->dev.parent);
+	} else {
+		drv_data = (struct samsung_fimc_driverdata *)
+			platform_get_device_id(pdev)->driver_data;
+
+		fimc_hw_set_irq_level(fimc);
+		if (fimc->variant->out_buf_count > 4)
+			fimc_hw_set_dma_seq(fimc, 0xF);
+
+		/* for write-back */
+		if (fimc_capture_writeback(fimc)) {
+			struct s5p_fimc_isp_info *isp_info;
+			int i;
+			isp_info = fimc->pdata->isp_info[fimc->vid_cap.input_index];
+			fimc_hw_set_camera_type(fimc, isp_info);
+
+			if (ctx->in_path == FIMC_LCD_WB) {
+				if (isp_info->mux_id == 0)
+					fimc_hwset_sysreg_camblk_fimd0_wb(fimc);
+				else
+					fimc_hwset_sysreg_camblk_fimd1_wb(fimc);
+			}
+			fimc_hw_set_camera_source(fimc, isp_info);
+			fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
+
+			if (ctx->state & FIMC_PARAMS) {
+				ret = fimc_set_scaler_info(ctx);
+				if (ret) {
+					err("Scaler setup error");
+					return ret;
+				}
+				fimc_hw_set_input_path(ctx);
+				fimc_hw_set_prescaler(ctx);
+				fimc_hw_set_mainscaler(ctx);
+				fimc_hw_set_target_format(ctx);
+				fimc_hw_set_rotation(ctx);
+				fimc_hw_set_effect(ctx);
+			}
 
-		if (!IS_ERR_OR_NULL(fimc->clock[i])) {
-			clk_enable(fimc->clock[i]);
-			continue;
+			fimc_hw_set_out_dma(ctx);
+			for (i = 0; i < FIMC_MAX_OUT_BUFS; i++)
+				fimc_hw_set_output_addr(fimc, &fimc->paddr[i], i);
 		}
-		dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
-			fimc_clocks[i]);
-		return -ENXIO;
 	}
+
 	return 0;
 }
 
@@ -1596,12 +1971,11 @@ static int fimc_probe(struct platform_device *pdev)
 	struct fimc_dev *fimc;
 	struct resource *res;
 	struct samsung_fimc_driverdata *drv_data;
-	struct s5p_platform_fimc *pdata;
 	int ret = 0;
 	int cap_input_index = -1;
+	char workqueue_name[WORKQUEUE_NAME_SIZE];
 
 	dev_dbg(&pdev->dev, "%s():\n", __func__);
-
 	drv_data = (struct samsung_fimc_driverdata *)
 		platform_get_device_id(pdev)->driver_data;
 
@@ -1618,15 +1992,14 @@ static int fimc_probe(struct platform_device *pdev)
 	fimc->id = pdev->id;
 	fimc->variant = drv_data->variant[fimc->id];
 	fimc->pdev = pdev;
-	pdata = pdev->dev.platform_data;
-	fimc->pdata = pdata;
+	fimc->pdata = pdev->dev.platform_data;
 	fimc->state = ST_IDLE;
 
 	init_waitqueue_head(&fimc->irq_queue);
 	spin_lock_init(&fimc->slock);
-
+#ifdef FOR_DIFF_VER
 	mutex_init(&fimc->lock);
-
+#endif
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "failed to find the registers\n");
@@ -1649,18 +2022,28 @@ static int fimc_probe(struct platform_device *pdev)
 		goto err_req_region;
 	}
 
-	fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
-
-	/* Check if a video capture node needs to be registered. */
-	if (pdata && pdata->num_clients > 0) {
-		cap_input_index = 0;
-		fimc->num_clocks++;
+	/*
+	 * Check if vide capture node needs to be registered for this device
+	 * instance.
+	 */
+	fimc->num_clocks = MAX_FIMC_CLOCKS - 2;
+
+	if (fimc->pdata) {
+		int i;
+		for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
+			if (fimc->pdata->isp_info[i])
+				break;
+		if (i < FIMC_MAX_CAMIF_CLIENTS)
+			cap_input_index = i;
 	}
 
 	ret = fimc_clk_get(fimc);
 	if (ret)
 		goto err_regs_unmap;
-	clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
+
+	ret = fimc_clk_setrate(fimc, CLK_BUS, drv_data);
+	if (ret)
+		goto err_regs_unmap;
 
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res) {
@@ -1670,20 +2053,19 @@ static int fimc_probe(struct platform_device *pdev)
 	}
 	fimc->irq = res->start;
 
-	fimc_hw_reset(fimc);
-
-	ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
+	ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
 		goto err_clk;
 	}
 
-	/* Initialize contiguous memory allocator */
-	fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
-	if (IS_ERR(fimc->alloc_ctx)) {
-		ret = PTR_ERR(fimc->alloc_ctx);
-		goto err_irq;
-	}
+#ifdef CONFIG_VIDEOBUF2_SDVMM
+	fimc->vb2 = &fimc_vb2_sdvmm;
+#elif defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+	fimc->vb2 = &fimc_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	fimc->vb2 = &fimc_vb2_ion;
+#endif
 
 	ret = fimc_register_m2m_device(fimc);
 	if (ret)
@@ -1694,15 +2076,35 @@ static int fimc_probe(struct platform_device *pdev)
 		ret = fimc_register_capture_device(fimc);
 		if (ret)
 			goto err_m2m;
-		clk_disable(fimc->clock[CLK_CAM]);
 	}
-	/*
-	 * Exclude the additional output DMA address registers by masking
-	 * them out on HW revisions that provide extended capabilites.
-	 */
+
+	pm_runtime_enable(&pdev->dev);
+	clear_bit(ST_PWR_ON, &fimc->state);
+
+	sprintf(workqueue_name, "fimc%d_irq_wq_name", fimc->id);
+	fimc->irq_workqueue = create_singlethread_workqueue(workqueue_name);
+	if (fimc->irq_workqueue == NULL) {
+		dev_err(&pdev->dev, "failed to create workqueue for fimc\n");
+		goto err_irq;
+	}
+	INIT_WORK(&fimc->work_struct, fimc_wq_suspend);
+
+	fimc->alloc_ctx = fimc->vb2->init(fimc);
+	if (IS_ERR(fimc->alloc_ctx)) {
+		ret = PTR_ERR(fimc->alloc_ctx);
+		goto err_wq;
+	}
+
+	set_bit(ST_PWR_ON, &fimc->state);
+	pm_runtime_get_sync(&fimc->pdev->dev);
+
+	fimc_hw_set_irq_level(fimc);
 	if (fimc->variant->out_buf_count > 4)
 		fimc_hw_set_dma_seq(fimc, 0xF);
 
+	clear_bit(ST_PWR_ON, &fimc->state);
+	fimc_runtime_put(fimc);
+
 	dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
 		__func__, fimc->id);
 
@@ -1710,6 +2112,8 @@ static int fimc_probe(struct platform_device *pdev)
 
 err_m2m:
 	fimc_unregister_m2m_device(fimc);
+err_wq:
+	destroy_workqueue(fimc->irq_workqueue);
 err_irq:
 	free_irq(fimc->irq, fimc);
 err_clk:
@@ -1731,24 +2135,201 @@ static int __devexit fimc_remove(struct platform_device *pdev)
 		(struct fimc_dev *)platform_get_drvdata(pdev);
 
 	free_irq(fimc->irq, fimc);
-	fimc_hw_reset(fimc);
 
 	fimc_unregister_m2m_device(fimc);
 	fimc_unregister_capture_device(fimc);
 
 	fimc_clk_release(fimc);
 
-	vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
+	fimc->vb2->cleanup(fimc->alloc_ctx);
 
 	iounmap(fimc->regs);
 	release_resource(fimc->regs_res);
 	kfree(fimc->regs_res);
 	kfree(fimc);
 
+	__pm_runtime_disable(&pdev->dev, false);
+
 	dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
 	return 0;
 }
 
+static int fimc_suspend_capture(struct fimc_dev *fimc)
+{
+	unsigned long flags;
+	struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
+	int ret = 0;
+
+	spin_lock_irqsave(&fimc->slock, flags);
+
+	/* when h/w did not working on */
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
+	set_bit(ST_CAPT_SHUT, &fimc->state);
+	fimc_deactivate_capture(fimc);
+
+	spin_unlock_irqrestore(&fimc->slock, flags);
+
+	ret = wait_event_timeout(fimc->irq_queue,
+			   !test_bit(ST_CAPT_SHUT, &fimc->state),
+			   FIMC_SHUTDOWN_TIMEOUT);
+	if (ret == 0)
+		dev_err(&fimc->pdev->dev, "wait timeout : %s\n", __func__);
+
+	if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state))
+		dbg("event timeout");
+
+	vid_cap->buf_index = 0;
+
+	fimc_hw_save_output_addr(fimc);
+
+	if (vid_cap->active_buf_cnt >= 1) {
+		int i;
+		unsigned int tmp_cnt = vid_cap->active_buf_cnt;
+		unsigned int cur_f_index = fimc_hw_get_frame_index(fimc);
+		for (i = 0; i < tmp_cnt; i++) {
+			fimc_hw_set_output_addr(fimc, &fimc->paddr[cur_f_index], i);
+			if (++cur_f_index >= FIMC_MAX_OUT_BUFS)
+				cur_f_index = 0;
+			if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
+				vid_cap->buf_index = 0;
+		}
+
+	}
+
+	fimc_hw_save_output_addr(fimc);
+
+	if (test_and_clear_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_put_sync(&fimc->pdev->dev);
+
+	return 0;
+}
+
+static int fimc_suspend(struct device *dev)
+{
+	struct platform_device *pdev;
+	struct fimc_dev *fimc;
+	int ret = 0;
+
+	pdev = to_platform_device(dev);
+	fimc = (struct fimc_dev *)platform_get_drvdata(pdev);
+
+	if (fimc_m2m_run(fimc)) {
+		set_bit(ST_M2M_STOP_REQ, &fimc->state);
+		ret = wait_event_timeout(fimc->irq_queue,
+				!test_bit(ST_M2M_STOP_REQ, &fimc->state),
+				FIMC_SHUTDOWN_TIMEOUT);
+		if (ret == 0)
+			dev_err(&fimc->pdev->dev, "wait timeout : %s\n",
+				__func__);
+	}
+
+	if (fimc_capture_writeback(fimc))
+		fimc_suspend_capture(fimc);
+
+	fimc_clk_disable(fimc);
+
+	return 0;
+}
+
+static int fimc_resume_capture(struct fimc_dev *fimc)
+{
+	struct s5p_fimc_isp_info *isp_info;
+	struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
+	struct fimc_ctx *ctx = vid_cap->ctx;
+	int ret, i;
+
+	isp_info = fimc->pdata->isp_info[fimc->vid_cap.input_index];
+
+	if (!test_and_set_bit(ST_PWR_ON, &fimc->state))
+		pm_runtime_get_sync(&fimc->pdev->dev);
+
+	fimc_hw_set_camera_type(fimc, isp_info);
+
+	if (ctx->in_path == FIMC_LCD_WB) {
+		if (isp_info->mux_id == 0)
+			fimc_hwset_sysreg_camblk_fimd0_wb(fimc);
+		else
+			fimc_hwset_sysreg_camblk_fimd1_wb(fimc);
+	}
+	fimc_hw_set_camera_source(fimc, isp_info);
+	fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
+
+	if (ctx->state & FIMC_PARAMS) {
+		ret = fimc_set_scaler_info(ctx);
+		if (ret) {
+			err("Scaler setup error");
+			return ret;
+		}
+		fimc_hw_set_input_path(ctx);
+		fimc_hw_set_prescaler(ctx);
+		fimc_hw_set_mainscaler(ctx);
+		fimc_hw_set_target_format(ctx);
+		fimc_hw_set_rotation(ctx);
+		fimc_hw_set_effect(ctx);
+	}
+
+	fimc_hw_set_out_dma(ctx);
+
+	for (i = 0; i < FIMC_MAX_OUT_BUFS; i++)
+		fimc_hw_set_output_addr(fimc, &fimc->paddr[i], i);
+
+	if (vid_cap->active_buf_cnt >= 1) {
+		fimc->vb2->resume(fimc->alloc_ctx);
+		fimc_activate_capture(ctx);
+	} else {
+		if (test_and_clear_bit(ST_PWR_ON, &fimc->state)) {
+			fimc->vb2->suspend(fimc->alloc_ctx);
+			pm_runtime_put_sync(&fimc->pdev->dev);
+		}
+	}
+
+	return 0;
+}
+
+static int fimc_resume(struct device *dev)
+{
+	struct platform_device *pdev;
+	struct samsung_fimc_driverdata *drv_data;
+	struct fimc_dev *fimc;
+	struct fimc_ctx *ctx;
+
+	pdev = to_platform_device(dev);
+	fimc = (struct fimc_dev *)platform_get_drvdata(pdev);
+	drv_data = (struct samsung_fimc_driverdata *)
+		platform_get_device_id(pdev)->driver_data;
+
+	set_bit(ST_PWR_ON, &fimc->state);
+	pm_runtime_get_sync(&fimc->pdev->dev);
+
+	fimc_hw_set_irq_level(fimc);
+	if (fimc->variant->out_buf_count > 4)
+		fimc_hw_set_dma_seq(fimc, 0xF);
+
+	clear_bit(ST_PWR_ON, &fimc->state);
+	pm_runtime_put_sync(&fimc->pdev->dev);
+
+	if (fimc_capture_opened(fimc)) {
+		if (fimc->vid_cap.fb_sd)
+			fimc_resume_capture(fimc);
+	} else {
+		ctx = fimc->m2m.ctx;
+		if (ctx == NULL)
+			return 0;
+		fimc->m2m.ctx = NULL;
+		v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops fimc_pm_ops = {
+	.suspend		= fimc_suspend,
+	.resume			= fimc_resume,
+	.runtime_suspend	= fimc_runtime_suspend,
+	.runtime_resume		= fimc_runtime_resume,
+};
+
 /* Image pixel limits, similar across several FIMC HW revisions. */
 static struct fimc_pix_limit s5p_pix_limit[4] = {
 	[0] = {
@@ -1835,7 +2416,7 @@ static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
 	.pix_limit	 = &s5p_pix_limit[2],
 };
 
-static struct samsung_fimc_variant fimc0_variant_exynos4 = {
+static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
 	.pix_hoff	 = 1,
 	.has_inp_rot	 = 1,
 	.has_out_rot	 = 1,
@@ -1848,7 +2429,7 @@ static struct samsung_fimc_variant fimc0_variant_exynos4 = {
 	.pix_limit	 = &s5p_pix_limit[1],
 };
 
-static struct samsung_fimc_variant fimc2_variant_exynos4 = {
+static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
 	.pix_hoff	 = 1,
 	.has_cistatus2	 = 1,
 	.has_mainscaler_ext = 1,
@@ -1882,12 +2463,12 @@ static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
 };
 
 /* S5PV310, S5PC210 */
-static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
+static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
 	.variant = {
-		[0] = &fimc0_variant_exynos4,
-		[1] = &fimc0_variant_exynos4,
-		[2] = &fimc0_variant_exynos4,
-		[3] = &fimc2_variant_exynos4,
+		[0] = &fimc0_variant_s5pv310,
+		[1] = &fimc0_variant_s5pv310,
+		[2] = &fimc0_variant_s5pv310,
+		[3] = &fimc2_variant_s5pv310,
 	},
 	.num_entities = 4,
 	.lclk_frequency = 166000000UL,
@@ -1901,8 +2482,8 @@ static struct platform_device_id fimc_driver_ids[] = {
 		.name		= "s5pv210-fimc",
 		.driver_data	= (unsigned long)&fimc_drvdata_s5pv210,
 	}, {
-		.name		= "exynos4-fimc",
-		.driver_data	= (unsigned long)&fimc_drvdata_exynos4,
+		.name		= "exynos4210-fimc",
+		.driver_data	= (unsigned long)&fimc_drvdata_s5pv310,
 	},
 	{},
 };
@@ -1915,6 +2496,7 @@ static struct platform_driver fimc_driver = {
 	.driver = {
 		.name	= MODULE_NAME,
 		.owner	= THIS_MODULE,
+		.pm	= &fimc_pm_ops,
 	}
 };
 
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
index 1f70772..4106248 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.h
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -10,60 +10,114 @@
 #define FIMC_CORE_H_
 
 /*#define DEBUG*/
-
+#include <linux/delay.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
 #include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
 #include <linux/io.h>
 #include <media/videobuf2-core.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-mem2mem.h>
 #include <media/v4l2-mediabus.h>
 #include <media/s5p_fimc.h>
-
 #include "regs-fimc.h"
 
+#if defined(CONFIG_VIDEOBUF2_SDVMM)
+#include <media/videobuf2-sdvmm.h>
+#include <plat/s5p-vcm.h>
+#elif defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#else
+#define pm_runtime_enable(x)		(void)NULL
+#define pm_runtime_get_sync(x)		(void)NULL
+#define pm_runtime_put_sync(x)		(void)NULL
+#define pm_runtime_forbid(x)		(void)NULL
+#define pm_runtime_allow(x)		(void)NULL
+#define __pm_runtime_disable(x, y)	(void)NULL
+#endif
+
+#define fimc_cam_use(x)		((pdata->isp_info[x]->use_cam) ? 1 : 0)
+
 #define err(fmt, args...) \
 	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
 
+#ifdef DEBUG
 #define dbg(fmt, args...) \
-	pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+	printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define dbg(fmt, args...)
+#endif
 
 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
 #define FIMC_SHUTDOWN_TIMEOUT	((100*HZ)/1000)
-#define MAX_FIMC_CLOCKS		3
+#define MAX_FIMC_CLOCKS		4
 #define MODULE_NAME		"s5p-fimc"
 #define FIMC_MAX_DEVS		4
 #define FIMC_MAX_OUT_BUFS	4
 #define SCALER_MAX_HRATIO	64
 #define SCALER_MAX_VRATIO	64
 #define DMA_MIN_SIZE		8
+#define DEFAULT_ISP_PIXCODE	V4L2_MBUS_FMT_YUYV8_2X8
+
+#define CAM_SRC_CLOCK		"xusbxti"
+#define CLK_NAME_CAM0		"sclk_cam0"
+#define CLK_NAME_CAM1		"sclk_cam1"
+#define FIMC_CMA_NAME		"fimc"
+#define FIMC_CMA_NAME_SIZE	6
+#define WORKQUEUE_NAME_SIZE	32
+
+#ifdef CONFIG_FB_S5P
+#define FIMD_MODULE_NAME	"s3cfb"
+#else
+#define FIMD_MODULE_NAME	"s3c-fb"
+#endif
 
 /* indices to the clocks array */
 enum {
 	CLK_BUS,
 	CLK_GATE,
-	CLK_CAM,
+	CLK_CAM0,
+	CLK_CAM1,
 };
 
 enum fimc_dev_flags {
-	/* for m2m node */
+	/* for global */
 	ST_IDLE,
-	ST_OUTDMA_RUN,
-	ST_M2M_PEND,
+	ST_PWR_ON,
+	/* for m2m node */
+	ST_M2M_OPEN,
+	ST_M2M_RUN,
+	ST_M2M_STOP_REQ,
 	/* for capture node */
 	ST_CAPT_PEND,
 	ST_CAPT_RUN,
+	ST_CAPT_SNAPSHOT,
 	ST_CAPT_STREAM,
+	ST_CAPT_SENS_STREAM,
 	ST_CAPT_SHUT,
 };
 
-#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
-#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
+#define fimc_m2m_active(dev) test_bit(ST_M2M_OPEN, &(dev)->state)
+#define fimc_m2m_run(dev) test_bit(ST_M2M_RUN, &(dev)->state)
 
 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
+#define fimc_capture_opened(dev) (dev->vid_cap.refcnt > 0) ? 1 : 0
+#define fimc_capture_camera(dev) (dev->vid_cap.sd == NULL) ? 0 : 1
+#define fimc_capture_writeback(dev) (dev->vid_cap.fb_sd != NULL &&\
+				test_bit(ST_CAPT_PEND, &(dev)->state)) ? 1 : 0
+
+#define fimc_capture_streaming(dev) \
+	test_bit(ST_CAPT_STREAM, &(dev)->state)
 
 enum fimc_datapath {
 	FIMC_CAMERA,
@@ -76,16 +130,22 @@ enum fimc_color_fmt {
 	S5P_FIMC_RGB565 = 0x10,
 	S5P_FIMC_RGB666,
 	S5P_FIMC_RGB888,
+	S5P_FIMC_RGB555,
+	S5P_FIMC_RGB444,
 	S5P_FIMC_RGB30_LOCAL,
 	S5P_FIMC_YCBCR420 = 0x20,
+	S5P_FIMC_YCRCB420,
+	S5P_FIMC_YCBCR422,
 	S5P_FIMC_YCBYCR422,
 	S5P_FIMC_YCRYCB422,
 	S5P_FIMC_CBYCRY422,
 	S5P_FIMC_CRYCBY422,
 	S5P_FIMC_YCBCR444_LOCAL,
+	S5P_FIMC_JPEG = 0x40,
 };
 
-#define fimc_fmt_is_rgb(x) ((x) & 0x10)
+#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
+#define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
 
 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
 #define	S5P_FIMC_LSB_CRCB	S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
@@ -106,7 +166,7 @@ enum fimc_color_fmt {
 #define	FIMC_DST_FMT		(1 << 4)
 #define	FIMC_CTX_M2M		(1 << 5)
 #define	FIMC_CTX_CAP		(1 << 6)
-#define	FIMC_CTX_SHUT		(1 << 7)
+#define	FIMC_CTX_STOP_REQ	(1 << 7)
 
 /* Image conversion flags */
 #define	FIMC_IN_DMA_ACCESS_TILED	(1 << 0)
@@ -266,10 +326,27 @@ struct fimc_frame {
 	u32	offs_v;
 	u32	width;
 	u32	height;
+	u8	alpha;
 	unsigned long		payload[VIDEO_MAX_PLANES];
 	struct fimc_addr	paddr;
 	struct fimc_dma_offset	dma_offset;
 	struct fimc_fmt		*fmt;
+	bool			cacheable;
+};
+
+/**
+ * struct fimc_is - fimc is subdevice information
+ */
+struct fimc_is {
+	struct v4l2_pix_format	fmt;
+	struct v4l2_mbus_framefmt mbus_fmt;
+	struct v4l2_subdev      *sd;
+	u32 frame_count;
+	u32 valid;
+	u32 bad_mark;
+	u32 offset_x;
+	u32 offset_y;
+	u16 camcording;
 };
 
 /**
@@ -310,17 +387,22 @@ struct fimc_vid_cap {
 	struct vb2_alloc_ctx		*alloc_ctx;
 	struct video_device		*vfd;
 	struct v4l2_device		v4l2_dev;
-	struct v4l2_subdev		*sd;;
+	struct v4l2_subdev		*sd;
+	struct v4l2_subdev		*fb_sd;
+	struct v4l2_subdev		*mipi_sd;
 	struct v4l2_mbus_framefmt	fmt;
 	struct list_head		pending_buf_q;
 	struct list_head		active_buf_q;
 	struct vb2_queue		vbq;
+	struct fimc_is			is;
+	struct v4l2_subdev		*flite_sd;
 	int				active_buf_cnt;
 	int				buf_index;
 	unsigned int			frame_count;
 	unsigned int			reqbufs_count;
 	int				input_index;
 	int				refcnt;
+	int				mux_id;
 };
 
 /**
@@ -383,6 +465,23 @@ struct samsung_fimc_driverdata {
 	int		num_entities;
 };
 
+struct fimc_dev;
+
+struct fimc_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct fimc_dev *fimc);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+	void (*set_sharable)(void *alloc_ctx, bool sharable);
+};
+
 struct fimc_ctx;
 
 /**
@@ -417,10 +516,17 @@ struct fimc_dev {
 	struct resource			*regs_res;
 	int				irq;
 	wait_queue_head_t		irq_queue;
+	struct work_struct		work_struct;
+	struct workqueue_struct		*irq_workqueue;
 	struct fimc_m2m_device		m2m;
 	struct fimc_vid_cap		vid_cap;
 	unsigned long			state;
 	struct vb2_alloc_ctx		*alloc_ctx;
+	struct fimc_addr		paddr[FIMC_MAX_OUT_BUFS];
+#ifdef CONFIG_VIDEOBUF2_SDVMM
+	enum vcm_dev_id			vcm_id;
+#endif
+	const struct fimc_vb2		*vb2;
 };
 
 /**
@@ -461,6 +567,7 @@ struct fimc_ctx {
 	u32			state;
 	struct fimc_dev		*fimc_dev;
 	struct v4l2_m2m_ctx	*m2m_ctx;
+	bool			cacheable;
 };
 
 static inline bool fimc_capture_active(struct fimc_dev *fimc)
@@ -534,6 +641,19 @@ static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 	writel(cfg, dev->regs + S5P_CIIMGCPT);
 }
 
+static inline void fimc_hw_enable_frame_end_irq(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg |= S5P_CIGCTRL_IRQ_END_DISABLE;
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+}
+
+static inline void fimc_hw_disable_frame_end_irq(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg &= ~S5P_CIGCTRL_IRQ_END_DISABLE;
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+}
 /**
  * fimc_hw_set_dma_seq - configure output DMA buffer sequence
  * @mask: each bit corresponds to one of 32 output buffer registers set
@@ -587,6 +707,7 @@ static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
 /* -----------------------------------------------------*/
 /* fimc-reg.c						*/
 void fimc_hw_reset(struct fimc_dev *fimc);
+void fimc_hw_set_irq_level(struct fimc_dev *dev);
 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
@@ -596,12 +717,14 @@ void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 void fimc_hw_set_effect(struct fimc_ctx *ctx);
+void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
 			     int index);
+int fimc_hw_save_output_addr(struct fimc_dev *fimc);
 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 			      struct s5p_fimc_isp_info *cam);
 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
@@ -609,9 +732,13 @@ int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 				struct s5p_fimc_isp_info *cam);
 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 			    struct s5p_fimc_isp_info *cam);
-
+int fimc_hwset_sysreg_camblk_fimd0_wb(struct fimc_dev *fimc);
+int fimc_hwset_sysreg_camblk_fimd1_wb(struct fimc_dev *fimc);
+int fimc_hwset_sysreg_camblk_isp_wb(struct fimc_dev *fimc);
+int fimc_wait_disable_capture(struct fimc_dev *fimc);
+int fimc_hwset_enable_lastend(struct fimc_dev *fimc);
 /* -----------------------------------------------------*/
-/* fimc-core.c */
+/* fimc-core.c						*/
 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
 				struct v4l2_fmtdesc *f);
 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
@@ -631,12 +758,15 @@ struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 				  unsigned int mask);
 
-int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
+int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
+			int dw, int dh, int rot);
 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 		      struct fimc_frame *frame, struct fimc_addr *paddr);
-
+void fimc_set_frame_size_mp(struct fimc_frame *frame, struct v4l2_format *f);
+int fimc_clk_setrate(struct fimc_dev *fimc, int clk_num, void *pdata);
+void fimc_capture_irq_handler(struct fimc_dev *fimc);
 /* -----------------------------------------------------*/
 /* fimc-capture.c					*/
 int fimc_register_capture_device(struct fimc_dev *fimc);
@@ -644,20 +774,29 @@ void fimc_unregister_capture_device(struct fimc_dev *fimc);
 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
 			     struct fimc_vid_buffer *fimc_vb);
+/* -----------------------------------------------------*/
+/* fimc-vb2.c						*/
+#if defined(CONFIG_VIDEOBUF2_SDVMM)
+extern const struct fimc_vb2 fimc_vb2_sdvmm;
+#elif defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct fimc_vb2 fimc_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct fimc_vb2 fimc_vb2_ion;
+#endif
 
 /* Locking: the caller holds fimc->slock */
 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
 {
 	fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
 	fimc_hw_en_capture(ctx);
+	fimc_hw_disable_frame_end_irq(ctx->fimc_dev);
 }
 
 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
 {
-	fimc_hw_en_lastirq(fimc, true);
 	fimc_hw_dis_capture(fimc);
 	fimc_hw_enable_scaler(fimc, false);
-	fimc_hw_en_lastirq(fimc, false);
+	fimc_hw_enable_frame_end_irq(fimc);
 }
 
 /*
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
index 4893b2d..5c8354d 100644
--- a/drivers/media/video/s5p-fimc/fimc-reg.c
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -14,10 +14,8 @@
 #include <linux/delay.h>
 #include <mach/map.h>
 #include <media/s5p_fimc.h>
-
 #include "fimc-core.h"
 
-
 void fimc_hw_reset(struct fimc_dev *dev)
 {
 	u32 cfg;
@@ -35,6 +33,19 @@ void fimc_hw_reset(struct fimc_dev *dev)
 	cfg = readl(dev->regs + S5P_CIGCTRL);
 	cfg &= ~S5P_CIGCTRL_SWRST;
 	writel(cfg, dev->regs + S5P_CIGCTRL);
+	/* Clear LASTCAPT_END bit : This is for Exynos4210 EVT1 */
+	cfg = readl(dev->regs + S5P_CISTATUS);
+	cfg &= ~S5P_CISTATUS_LASTCAPT_END;
+	writel(cfg, dev->regs + S5P_CISTATUS);
+}
+
+void fimc_hw_set_irq_level(struct fimc_dev *dev)
+{
+	u32 cfg;
+	cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg |= S5P_CIGCTRL_IRQ_LEVEL;
+
+	writel(cfg, dev->regs + S5P_CIGCTRL);
 }
 
 static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
@@ -118,22 +129,26 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
 
 void fimc_hw_set_target_format(struct fimc_ctx *ctx)
 {
-	u32 cfg;
+	u32 cfg, cfg_ext;
 	struct fimc_dev *dev = ctx->fimc_dev;
 	struct fimc_frame *frame = &ctx->d_frame;
 
 	dbg("w= %d, h= %d color: %d", frame->width,
 		frame->height, frame->fmt->color);
 
+	cfg_ext = readl(dev->regs + S5P_CIEXTEN);
+	cfg_ext &= ~(S5P_CIEXTEN_TRGHSIZE_EXT_MASK |
+		     S5P_CIEXTEN_TRGVSIZE_EXT_MASK);
 	cfg = readl(dev->regs + S5P_CITRGFMT);
 	cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
 		  S5P_CITRGFMT_VSIZE_MASK);
 
 	switch (frame->fmt->color) {
-	case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
+	case S5P_FIMC_RGB565...S5P_FIMC_RGB444:
 		cfg |= S5P_CITRGFMT_RGB;
 		break;
-	case S5P_FIMC_YCBCR420:
+	case S5P_FIMC_YCBCR420: /* fall through */
+	case S5P_FIMC_YCRCB420:
 		cfg |= S5P_CITRGFMT_YCBCR420;
 		break;
 	case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
@@ -149,16 +164,26 @@ void fimc_hw_set_target_format(struct fimc_ctx *ctx)
 	if (ctx->rotation == 90 || ctx->rotation == 270) {
 		cfg |= S5P_CITRGFMT_HSIZE(frame->height);
 		cfg |= S5P_CITRGFMT_VSIZE(frame->width);
+		cfg_ext |= S5P_CIEXTEN_TRGHSIZE_EXT(frame->height);
+		cfg_ext |= S5P_CIEXTEN_TRGVSIZE_EXT(frame->width);
 	} else {
 
 		cfg |= S5P_CITRGFMT_HSIZE(frame->width);
 		cfg |= S5P_CITRGFMT_VSIZE(frame->height);
+		cfg_ext |= S5P_CIEXTEN_TRGHSIZE_EXT(frame->width);
+		cfg_ext |= S5P_CIEXTEN_TRGVSIZE_EXT(frame->height);
 	}
 
 	writel(cfg, dev->regs + S5P_CITRGFMT);
+	writel(cfg_ext, dev->regs + S5P_CIEXTEN);
 
 	cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
+
+	if (frame->fmt->fourcc == V4L2_PIX_FMT_JPEG)
+		cfg |= frame->payload[0];
+	else
 	cfg |= (frame->width * frame->height);
+
 	writel(cfg, dev->regs + S5P_CITAREA);
 }
 
@@ -211,7 +236,7 @@ void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
 	cfg = readl(dev->regs + S5P_CIOCTRL);
 
 	cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
-		 S5P_CIOCTRL_YCBCR_PLANE_MASK);
+		 S5P_CIOCTRL_YCBCR_PLANE_MASK | S5P_CIOCTRL_RGB16FMT_MASK);
 
 	if (frame->fmt->colplanes == 1)
 		cfg |= ctx->out_order_1p;
@@ -220,6 +245,15 @@ void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
 	else if (frame->fmt->colplanes == 3)
 		cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
 
+	if (frame->fmt->color == S5P_FIMC_RGB565)
+		cfg |= S5P_CIOCTRL_RGB565;
+	else if (frame->fmt->color == S5P_FIMC_RGB555)
+		cfg |= S5P_CIOCTRL_ARGB1555;
+	else if (frame->fmt->color == S5P_FIMC_RGB444)
+		cfg |= S5P_CIOCTRL_ARGB4444;
+	else if (frame->fmt->color == S5P_FIMC_YCRCB420)
+		cfg |= S5P_CIOCTRL_ORDER422_2P_LSB_CBCR;
+
 	writel(cfg, dev->regs + S5P_CIOCTRL);
 }
 
@@ -295,14 +329,18 @@ static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
 	}
 
 	if (ctx->out_path == FIMC_DMA) {
-		if (dst_frame->fmt->color == S5P_FIMC_RGB565)
+		if ((dst_frame->fmt->color == S5P_FIMC_RGB565)
+		    | (dst_frame->fmt->color == S5P_FIMC_RGB555)
+		    | (dst_frame->fmt->color == S5P_FIMC_RGB444))
 			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
 		else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
 			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
 		else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
 			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
+		cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
 	} else {
-		cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
+		cfg |= (S5P_CISCCTRL_OUTRGB_FMT_RGB888
+			| S5P_CISCCTRL_LCDPATHEN_FIFO);
 
 		if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
 			cfg |= S5P_CISCCTRL_INTERLACE;
@@ -356,7 +394,7 @@ void fimc_hw_en_capture(struct fimc_ctx *ctx)
 		/* one shot mode */
 		cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN;
 	} else {
-		/* Continuous frame capture mode (freerun). */
+		/* Continous frame capture mode (freerun). */
 		cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
 			 S5P_CIIMGCPT_CPT_FRMOD_CNT);
 		cfg |= S5P_CIIMGCPT_IMGCPTEN;
@@ -372,7 +410,7 @@ void fimc_hw_set_effect(struct fimc_ctx *ctx)
 {
 	struct fimc_dev *dev = ctx->fimc_dev;
 	struct fimc_effect *effect = &ctx->effect;
-	u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
+	u32 cfg = S5P_CIIMGEFF_IE_SC_AFTER;
 
 	cfg |= effect->type;
 
@@ -384,6 +422,23 @@ void fimc_hw_set_effect(struct fimc_ctx *ctx)
 	writel(cfg, dev->regs + S5P_CIIMGEFF);
 }
 
+void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->d_frame;
+	u32 cfg;
+
+	if (!((frame->fmt->color == S5P_FIMC_RGB555)
+	    | (frame->fmt->color == S5P_FIMC_RGB444)
+	    | (frame->fmt->color == S5P_FIMC_RGB888)))
+		return;
+
+	cfg = readl(dev->regs + S5P_CIOCTRL);
+	cfg &= ~S5P_CIOCTRL_ALPHA_OUT_MASK;
+	cfg |= (frame->alpha << 4);
+	writel(cfg, dev->regs + S5P_CIOCTRL);
+}
+
 static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
 {
 	struct fimc_dev *dev = ctx->fimc_dev;
@@ -445,7 +500,8 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
 	case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
 		cfg |= S5P_MSCTRL_INFORMAT_RGB;
 		break;
-	case S5P_FIMC_YCBCR420:
+	case S5P_FIMC_YCBCR420: /* fall through */
+	case S5P_FIMC_YCRCB420:
 		cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
 
 		if (frame->fmt->colplanes == 2)
@@ -453,6 +509,8 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
 		else
 			cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
 
+		if (frame->fmt->color == S5P_FIMC_YCRCB420)
+			cfg |= S5P_MSCTRL_2P_IN_YCRCB;
 		break;
 	case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
 		if (frame->fmt->colplanes == 1) {
@@ -541,6 +599,18 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev,
 	} while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
 }
 
+int fimc_hw_save_output_addr(struct fimc_dev *fimc)
+{
+	int i;
+	for (i = 0; i < FIMC_MAX_OUT_BUFS; i++) {
+		fimc->paddr[i].y = readl(fimc->regs + S5P_CIOYSA(i));
+		fimc->paddr[i].cb = readl(fimc->regs + S5P_CIOCBSA(i));
+		fimc->paddr[i].cr = readl(fimc->regs + S5P_CIOCRSA(i));
+	}
+
+	return 0;
+}
+
 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 				struct s5p_fimc_isp_info *cam)
 {
@@ -573,7 +643,6 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 	u32 cfg = 0;
 	u32 bus_width;
 	int i;
-
 	static const struct {
 		u32 pixelcode;
 		u32 cisrcfmt;
@@ -585,6 +654,8 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 		{ V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
 		/* TODO: Add pixel codes for 16-bit bus width */
 	};
+	dbg("f->o_width : %d, f->o_height : %d\n", f->o_width, f->o_height);
+	dbg("code : %d\n", fimc->vid_cap.fmt.code);
 
 	if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
 		for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
@@ -608,9 +679,18 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 			else if (bus_width == 16)
 				cfg |= S5P_CISRCFMT_ITU601_16BIT;
 		} /* else defaults to ITU-R BT.656 8-bit */
+	} else if (cam->bus_type == FIMC_MIPI_CSI2) {
+		if (fimc_fmt_is_jpeg(f->fmt->color) || fimc->vid_cap.is.sd
+						|| fimc->vid_cap.is.camcording)
+			cfg |= S5P_CISRCFMT_ITU601_8BIT;
 	}
 
-	cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height);
+	if (fimc->vid_cap.is.sd || fimc->vid_cap.is.camcording)
+		cfg |= S5P_CISRCFMT_HSIZE(fimc->vid_cap.is.fmt.width) |
+			S5P_CISRCFMT_VSIZE(fimc->vid_cap.is.fmt.height);
+	else
+		cfg |= S5P_CISRCFMT_HSIZE(f->o_width) |
+			S5P_CISRCFMT_VSIZE(f->o_height);
 	writel(cfg, fimc->regs + S5P_CISRCFMT);
 	return 0;
 }
@@ -641,7 +721,8 @@ int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 			    struct s5p_fimc_isp_info *cam)
 {
-	u32 cfg, tmp;
+	u32 cfg = 0;
+	u32 tmp = 0;
 	struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
 
 	cfg = readl(fimc->regs + S5P_CIGCTRL);
@@ -649,32 +730,47 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 	/* Select ITU B interface, disable Writeback path and test pattern. */
 	cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A |
 		S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB |
-		S5P_CIGCTRL_SELCAM_MIPI_A);
+		S5P_CIGCTRL_SELCAM_MIPI_A | S5P_CIGCTRL_SELWRITEBACK_A |
+		S5P_CIGCTRL_CAM_JPEG);
 
 	if (cam->bus_type == FIMC_MIPI_CSI2) {
-		cfg |= S5P_CIGCTRL_SELCAM_MIPI;
-
-		if (cam->mux_id == 0)
-			cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
+		if (!vid_cap->is.sd && !vid_cap->is.camcording) {
+			cfg |= S5P_CIGCTRL_SELCAM_MIPI;
+
+			if (cam->mux_id == 0)
+				cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
+
+			/* TODO: add remaining supported formats. */
+			switch (vid_cap->fmt.code) {
+			case V4L2_MBUS_FMT_VYUY8_2X8:
+			case V4L2_MBUS_FMT_UYVY8_2X8:
+			case V4L2_MBUS_FMT_YUYV8_2X8:
+				tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
+				break;
+			case V4L2_MBUS_FMT_JPEG_1X8:
+				tmp = S5P_CSIIMGFMT_USER(1);
+				cfg |= S5P_CIGCTRL_CAM_JPEG;
+				break;
+			default:
+				v4l2_err(&fimc->vid_cap.v4l2_dev,
+				 "Not supported camera pixel format: %d",
+				 vid_cap->fmt.code);
+			}
+			tmp |= (cam->csi_data_align == 32) << 8;
 
-		/* TODO: add remaining supported formats. */
-		if (vid_cap->fmt.code == V4L2_MBUS_FMT_VYUY8_2X8) {
-			tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
+			writel(tmp, fimc->regs + S5P_CSIIMGFMT);
 		} else {
-			err("camera image format not supported: %d",
-			    vid_cap->fmt.code);
-			return -EINVAL;
+			cfg |= S5P_CIGCTRL_CAMIF_SELWB;
+			cfg |= S5P_CIGCTRL_SELWRITEBACK_B;
 		}
-		tmp |= (cam->csi_data_align == 32) << 8;
-
-		writel(tmp, fimc->regs + S5P_CSIIMGFMT);
-
 	} else if (cam->bus_type == FIMC_ITU_601 ||
-		   cam->bus_type == FIMC_ITU_656) {
+		  cam->bus_type == FIMC_ITU_656) {
 		if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
 			cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
 	} else if (cam->bus_type == FIMC_LCD_WB) {
 		cfg |= S5P_CIGCTRL_CAMIF_SELWB;
+		if (cam->mux_id == 0)
+			cfg |= S5P_CIGCTRL_SELWRITEBACK_A;
 	} else {
 		err("invalid camera bus type selected\n");
 		return -EINVAL;
@@ -683,3 +779,102 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 
 	return 0;
 }
+
+int fimc_hwset_sysreg_camblk_fimd0_wb(struct fimc_dev *fimc)
+{
+	u32 cfg = readl(SYSREG_CAMERA_BLK);
+	cfg = cfg & (~(0x3 << 14));
+	if (fimc->id == 0)
+		cfg = cfg | FIMD0_WB_DEST_FIMC0;
+	else if (fimc->id == 1)
+		cfg = cfg | FIMD0_WB_DEST_FIMC1;
+	else if (fimc->id == 2)
+		cfg = cfg | FIMD0_WB_DEST_FIMC2;
+	else if (fimc->id == 3)
+		cfg = cfg | FIMD0_WB_DEST_FIMC3;
+	else
+		err("%s: not supported id : %d\n", __func__, fimc->id);
+
+	writel(cfg, SYSREG_CAMERA_BLK);
+
+	return 0;
+}
+int fimc_hwset_sysreg_camblk_fimd1_wb(struct fimc_dev *fimc)
+{
+	u32 cfg = readl(SYSREG_CAMERA_BLK);
+	cfg = cfg & (~(0x3 << 10));
+	if (fimc->id == 0)
+		cfg = cfg | FIMD1_WB_DEST_FIMC0;
+	else if (fimc->id == 1)
+		cfg = cfg | FIMD1_WB_DEST_FIMC1;
+	else if (fimc->id == 2)
+		cfg = cfg | FIMD1_WB_DEST_FIMC2;
+	else if (fimc->id == 3)
+		cfg = cfg | FIMD1_WB_DEST_FIMC3;
+	else
+		err("%s: not supported id : %d\n", __func__, fimc->id);
+
+	writel(cfg, SYSREG_CAMERA_BLK);
+
+	return 0;
+}
+
+int fimc_hwset_sysreg_camblk_isp_wb(struct fimc_dev *fimc)
+{
+	u32 camblk_cfg = readl(SYSREG_CAMERA_BLK);
+	u32 ispblk_cfg = readl(SYSREG_ISP_BLK);
+	camblk_cfg = camblk_cfg & (~(0x7 << 20));
+	if (fimc->id == 0)
+		camblk_cfg = camblk_cfg | (0x1 << 20);
+	else if (fimc->id == 1)
+		camblk_cfg = camblk_cfg | (0x2 << 20);
+	else if (fimc->id == 2)
+		camblk_cfg = camblk_cfg | (0x4 << 20);
+	else if (fimc->id == 3)
+		camblk_cfg = camblk_cfg | (0x7 << 20); /* FIXME*/
+	else
+		err("%s: not supported id : %d\n", __func__, fimc->id);
+
+	camblk_cfg = camblk_cfg & (~(0x1 << 15));
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+	udelay(1000);
+	camblk_cfg = camblk_cfg | (0x1 << 15);
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+
+	ispblk_cfg = ispblk_cfg & (~(0x1 << 7));
+	writel(ispblk_cfg, SYSREG_ISP_BLK);
+	udelay(1000);
+	ispblk_cfg = ispblk_cfg | (0x1 << 7);
+	writel(ispblk_cfg, SYSREG_ISP_BLK);
+
+	return 0;
+}
+
+int fimc_wait_disable_capture(struct fimc_dev *fimc)
+{
+	unsigned long timeo = jiffies + 20; /* timeout of 100ms */
+	u32 cfg;
+
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(fimc->regs + S5P_CISTATUS);
+
+		if (!(cfg & S5P_CISTATUS_IMGCPT_EN) &&
+			!(cfg &	S5P_CISTATUS_IMGCPT_SCEN) &&
+			!(cfg & S5P_CISTATUS_SCALER_START))
+			return 0;
+		msleep(5);
+	}
+	dbg("wait time : %d ms\n", jiffies_to_msecs(jiffies - timeo + 20));
+
+	return -EBUSY;
+}
+
+int fimc_hwset_enable_lastend(struct fimc_dev *fimc)
+{
+	u32 cfg = readl(fimc->regs + S5P_CIOCTRL);
+
+	cfg |= S5P_CIOCTRL_LASTENDEN;
+	writel(cfg, fimc->regs + S5P_CIOCTRL);
+
+	return 0;
+}
diff --git a/drivers/media/video/s5p-fimc/fimc-vb2.c b/drivers/media/video/s5p-fimc/fimc-vb2.c
new file mode 100644
index 0000000..57bd428
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-vb2.c
@@ -0,0 +1,111 @@
+/* linux/drivers/media/video/s5p-fimc/fimc_vb2.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Core file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include "fimc-core.h"
+
+#if defined(CONFIG_VIDEOBUF2_SDVMM)
+void *fimc_sdvmm_init(struct fimc_dev *fimc)
+{
+	struct vb2_vcm vb2_vcm;
+	struct vb2_cma vb2_cma;
+	char cma_name[FIMC_CMA_NAME_SIZE] = {0,};
+	struct vb2_drv vb2_drv;
+
+	fimc->vcm_id = VCM_DEV_FIMC0 + fimc->id;
+
+	vb2_vcm.vcm_id = fimc->vcm_id;
+	vb2_vcm.size = SZ_64M;
+
+	vb2_cma.dev = &fimc->pdev->dev;
+	/* FIXME: need to set type value */
+	sprintf(cma_name, "%s%d", FIMC_CMA_NAME, fimc->id);
+	vb2_cma.type = cma_name;
+	vb2_cma.alignment = SZ_4K;
+
+	vb2_drv.cacheable = false;
+	vb2_drv.remap_dva = false;
+
+	return vb2_sdvmm_init(&vb2_vcm, &vb2_cma, &vb2_drv);
+}
+
+const struct fimc_vb2 fimc_vb2_sdvmm = {
+	.ops		= &vb2_sdvmm_memops,
+	.init		= fimc_sdvmm_init,
+	.cleanup	= vb2_sdvmm_cleanup,
+	.plane_addr	= vb2_sdvmm_plane_dvaddr,
+	.resume		= vb2_sdvmm_resume,
+	.suspend	= vb2_sdvmm_suspend,
+	.cache_flush	= vb2_sdvmm_cache_flush,
+	.set_cacheable	= vb2_sdvmm_set_cacheable,
+};
+
+#elif defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *fimc_cma_init(struct fimc_dev *fimc)
+{
+	return vb2_cma_phys_init(&fimc->pdev->dev, NULL, 0, false);
+}
+
+int fimc_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void fimc_cma_suspend(void *alloc_ctx){}
+void fimc_cma_set_cacheable(void *alloc_ctx, bool cacheable){}
+
+int fimc_cma_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return 0;
+}
+
+const struct fimc_vb2 fimc_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= fimc_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= fimc_cma_resume,
+	.suspend	= fimc_cma_suspend,
+	.cache_flush	= fimc_cma_cache_flush,
+	.set_cacheable	= fimc_cma_set_cacheable,
+};
+
+#elif defined(CONFIG_VIDEOBUF2_ION)
+void *fimc_ion_init(struct fimc_dev *fimc)
+{
+	struct vb2_ion vb2_ion;
+	struct vb2_drv vb2_drv = {0, };
+	char ion_name[16] = {0,};
+
+	vb2_ion.dev = &fimc->pdev->dev;
+	sprintf(ion_name, "fimc%d", fimc->id);
+	vb2_ion.name = ion_name;
+	vb2_ion.contig = false;
+	vb2_ion.cacheable = false;
+	vb2_ion.align = SZ_4K;
+
+	vb2_drv.use_mmu = true;
+
+	return vb2_ion_init(&vb2_ion, &vb2_drv);
+}
+
+const struct fimc_vb2 fimc_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= fimc_ion_init,
+	.cleanup	= vb2_ion_cleanup,
+	.plane_addr	= vb2_ion_plane_dvaddr,
+	.resume		= vb2_ion_resume,
+	.suspend	= vb2_ion_suspend,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cacheable,
+	.set_sharable	= vb2_ion_set_sharable,
+};
+#endif
diff --git a/drivers/media/video/s5p-fimc/regs-fimc.h b/drivers/media/video/s5p-fimc/regs-fimc.h
index 0fea3e6..e069a90 100644
--- a/drivers/media/video/s5p-fimc/regs-fimc.h
+++ b/drivers/media/video/s5p-fimc/regs-fimc.h
@@ -52,8 +52,13 @@
 #define S5P_CIGCTRL_HREF_MASK		(1 << 21)
 #define S5P_CIGCTRL_IRQ_LEVEL		(1 << 20)
 #define S5P_CIGCTRL_IRQ_CLR		(1 << 19)
+#define S5P_CIGCTRL_IRQ_END_DISABLE	(1 << 18)
+#define S5P_CIGCTRL_IRQ_START_ENABLE	(1 << 17)
 #define S5P_CIGCTRL_IRQ_ENABLE		(1 << 16)
 #define S5P_CIGCTRL_SHDW_DISABLE	(1 << 12)
+#define S5P_CIGCTRL_SELWRITEBACK_A	(1 << 10)
+#define S5P_CIGCTRL_SELWRITEBACK_B	(0 << 10)
+#define S5P_CIGCTRL_CAM_JPEG		(1 << 8)
 #define S5P_CIGCTRL_SELCAM_MIPI_A	(1 << 7)
 #define S5P_CIGCTRL_CAMIF_SELWB		(1 << 6)
 /* 0 - ITU601; 1 - ITU709 */
@@ -105,9 +110,16 @@
 #define S5P_CIOCTRL_YCBCR_3PLANE	(0 << 3)
 #define S5P_CIOCTRL_YCBCR_2PLANE	(1 << 3)
 #define S5P_CIOCTRL_YCBCR_PLANE_MASK	(1 << 3)
+#define S5P_CIOCTRL_ALPHA_OUT_MASK	(0xff << 4)
+#define S5P_CIOCTRL_RGB16FMT_MASK	(3 << 16)
+#define S5P_CIOCTRL_RGB565		(0 << 16)
+#define S5P_CIOCTRL_ARGB1555		(1 << 16)
+#define S5P_CIOCTRL_ARGB4444		(2 << 16)
 #define S5P_CIOCTRL_ORDER2P_SHIFT	(24)
 #define S5P_CIOCTRL_ORDER2P_MASK	(3 << 24)
 #define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
+#define S5P_CIOCTRL_ORDER422_2P_LSB_CBCR (1 << 24)
+#define S5P_CIOCTRL_LASTENDEN		(1 << 30)
 
 /* Pre-scaler control 1 */
 #define S5P_CISCPRERATIO		0x50
@@ -158,6 +170,7 @@
 #define S5P_CISTATUS_VSYNC		(1 << 28)
 #define S5P_CISTATUS_FRAMECNT_MASK	(3 << 26)
 #define S5P_CISTATUS_FRAMECNT_SHIFT	26
+#define S5P_CISTATUS_SCALER_START	(1 << 26)
 #define S5P_CISTATUS_WINOFF_EN		(1 << 25)
 #define S5P_CISTATUS_IMGCPT_EN		(1 << 22)
 #define S5P_CISTATUS_IMGCPT_SCEN	(1 << 21)
@@ -216,6 +229,7 @@
 #define S5P_MSCTRL			0xfc
 #define S5P_MSCTRL_IN_BURST_COUNT_MASK	(0xF << 24)
 #define S5P_MSCTRL_2P_IN_ORDER_MASK	(3 << 16)
+#define S5P_MSCTRL_2P_IN_YCRCB		(1 << 16)
 #define S5P_MSCTRL_2P_IN_ORDER_SHIFT	16
 #define S5P_MSCTRL_C_INT_IN_3PLANE	(0 << 15)
 #define S5P_MSCTRL_C_INT_IN_2PLANE	(1 << 15)
@@ -268,6 +282,10 @@
 
 /* Real output DMA image size (extension register) */
 #define S5P_CIEXTEN			0x188
+#define S5P_CIEXTEN_TRGHSIZE_EXT(x)	((((x) >> 13) & 0x1) << 26)
+#define S5P_CIEXTEN_TRGVSIZE_EXT(x)	((((x) >> 13) & 0x1) << 24)
+#define S5P_CIEXTEN_TRGHSIZE_EXT_MASK	(1 << 26)
+#define S5P_CIEXTEN_TRGVSIZE_EXT_MASK	(1 << 24)
 #define S5P_CIEXTEN_MHRATIO_EXT(x)	(((x) & 0x3f) << 10)
 #define S5P_CIEXTEN_MVRATIO_EXT(x)	((x) & 0x3f)
 #define S5P_CIEXTEN_MHRATIO_EXT_MASK	(0x3f << 10)
@@ -286,12 +304,22 @@
 #define S5P_CSIIMGFMT_RAW8		0x2a
 #define S5P_CSIIMGFMT_RAW10		0x2b
 #define S5P_CSIIMGFMT_RAW12		0x2c
-#define S5P_CSIIMGFMT_USER1		0x30
-#define S5P_CSIIMGFMT_USER2		0x31
-#define S5P_CSIIMGFMT_USER3		0x32
-#define S5P_CSIIMGFMT_USER4		0x33
+/* User defined formats. x = 0...16. */
+#define S5P_CSIIMGFMT_USER(x)		(0x30 + x - 1)
 
 /* Output frame buffer sequence mask */
 #define S5P_CIFCNTSEQ			0x1FC
 
+/* SYSREG for writeback */
+#define SYSREG_CAMERA_BLK			(S3C_VA_SYS + 0x0218)
+#define SYSREG_ISP_BLK				(S3C_VA_SYS + 0x020c)
+#define FIMD0_WB_DEST_FIMC0			(0x0 << 14)
+#define FIMD0_WB_DEST_FIMC1			(0x1 << 14)
+#define FIMD0_WB_DEST_FIMC2			(0x2 << 14)
+#define FIMD0_WB_DEST_FIMC3			(0x3 << 14)
+#define FIMD1_WB_DEST_FIMC0			(0x0 << 10)
+#define FIMD1_WB_DEST_FIMC1			(0x1 << 10)
+#define FIMD1_WB_DEST_FIMC2			(0x2 << 10)
+#define FIMD1_WB_DEST_FIMC3			(0x3 << 10)
+
 #endif /* REGS_FIMC_H_ */
diff --git a/drivers/media/video/s5p-fimc/s5p-mipi_csis.c b/drivers/media/video/s5p-fimc/s5p-mipi_csis.c
new file mode 100644
index 0000000..6cede76
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/s5p-mipi_csis.c
@@ -0,0 +1,710 @@
+/*
+ * Samsung S5P SoC series MIPI-CSI2 slave interface driver
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd
+ * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/memory.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <plat/mipi_csis.h>
+#include <plat/cpu.h>
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Enable module debug trace. Set to 1 to enable.");
+
+#define MODULE_NAME		"s5p-mipi-csis"
+
+/* Register map definition */
+
+/* CSI global control. */
+#define S5P_CSIS_CTRL			0x00
+#define S5P_CSIS_CTRL_DPDN_DEFAULT	(0 << 31)
+#define S5P_CSIS_CTRL_DPDN_SWAP		(1 << 31)
+#define S5P_CSIS_CTRL_ALIGN_32BIT	(1 << 20)
+#define S5P_CSIS_CTRL_UPDATE_SHADOW	(1 << 16)
+#define S5P_CSIS_CTRL_WCLK_EXTCLK	(1 << 8)
+#define S5P_CSIS_CTRL_RESET		(1 << 4)
+#define S5P_CSIS_CTRL_ENABLE		(1 << 0)
+
+/* D-PHY control. */
+#define S5P_CSIS_DPHYCTRL		0x04
+#define S5P_CSIS_DPHYCTRL_HSS_MASK	(0x1F << 27)
+/* 4-lanes #define S5P_CSIS_DPHYCTRL_ENABLE	(0x1F << 0) */
+#define S5P_CSIS_DPHYCTRL_ENABLE	(0x1F << 0)
+
+#define S5P_CSIS_CONFIG			0x08
+#define S5P_CSIS_CFG_FMT_YCBCR422_8BIT	(0x1E << 2)
+#define S5P_CSIS_CFG_FMT_RAW8		(0x2A << 2)
+#define S5P_CSIS_CFG_FMT_RAW10		(0x2B << 2)
+#define S5P_CSIS_CFG_FMT_RAW12		(0x2C << 2)
+/* User defined formats. x = 1...4. */
+#define S5P_CSIS_CFG_FMT_USER(x)	((0x30 + x - 1) << 2)
+#define S5P_CSIS_CFG_FMT_MASK		(0x3F << 2)
+#define S5P_CSIS_CFG_NR_LANE_MASK	3
+
+/* Interrupt mask. */
+#define S5P_CSIS_INTMSK			0x10
+#define S5P_CSIS_INTMSK_EN_ALL		0xF000103F
+#define S5P_CSIS_INTSRC			0x14
+
+/* Interrupt Source Register */
+#define S5P_CSIS_INTSRC_EVEN_BEFORE		(1 << 31)
+#define S5P_CSIS_INTSRC_EVEN_AFTER		(1 << 30)
+#define S5P_CSIS_INTSRC_ODD_BEFORE		(1 << 29)
+#define S5P_CSIS_INTSRC_ODD_AFTER		(1 << 28)
+
+#define S5P_CSIS_INTSRC_ERR_SOT_HS		(0xF << 12)
+#define S5P_CSIS_INTSRC_ERR_LOST_FS		(1 << 5)
+#define S5P_CSIS_INTSRC_ERR_LOST_FE		(1 << 4)
+#define S5P_CSIS_INTSRC_ERR_OVER		(1 << 3)
+#define S5P_CSIS_INTSRC_ERR_ECC			(1 << 2)
+#define S5P_CSIS_INTSRC_ERR_CRC			(1 << 1)
+#define S5P_CSIS_INTSRC_ERR_ID			(1 << 0)
+#define S5P_CSIS_INTSRC_ERR			(S5P_CSIS_INTSRC_ERR_SOT_HS | \
+						S5P_CSIS_INTSRC_ERR_LOST_FS | \
+						S5P_CSIS_INTSRC_ERR_LOST_FE | \
+						S5P_CSIS_INTSRC_ERR_OVER | \
+						S5P_CSIS_INTSRC_ERR_ECC | \
+						S5P_CSIS_INTSRC_ERR_CRC | \
+						S5P_CSIS_INTSRC_ERR_ID)
+
+/* Pixel resolution. */
+#define S5P_CSIS_RESOL			0x2C
+#define CSIS_MAX_PIX_WIDTH		0xFFFF
+#define CSIS_MAX_PIX_HEIGHT		0xFFFF
+
+enum {
+	CSIS_CLK_BUS,
+	CSIS_CLK_GATE,
+};
+
+static char *csi_clock_name[] = {
+	[CSIS_CLK_BUS]  = "sclk_csis",
+	[CSIS_CLK_GATE] = "csis",
+};
+
+#define NUM_CSIS_CLOCKS	ARRAY_SIZE(csi_clock_name)
+
+enum {
+	CSIS_PWR_ST_POWERED,
+	CSIS_PWR_ST_STREAMING,
+	CSIS_PWR_ST_SUSPENDED,
+};
+
+struct s5p_csis_state {
+	struct mutex lock;
+	struct v4l2_subdev sd;
+	struct v4l2_mbus_framefmt fmt;
+	struct platform_device *pdev;
+	struct resource *regs_res;
+	void __iomem *regs;
+	int irq;
+	struct clk *clock[NUM_CSIS_CLOCKS];
+	struct regulator *supply;
+	unsigned long power;
+};
+
+struct s5p_csis_color_format {
+	enum v4l2_mbus_pixelcode code;
+	u32 fmt_reg;
+	u16 pix_hor_align;
+};
+
+static s32 err_print_cnt;
+static const struct s5p_csis_color_format s5p_csis_formats[] = {
+	{
+		.code		= V4L2_MBUS_FMT_YUYV8_2X8,
+		.fmt_reg	= S5P_CSIS_CFG_FMT_YCBCR422_8BIT,
+		.pix_hor_align	= 1,
+	}, {
+		.code		= V4L2_MBUS_FMT_JPEG_1X8,
+		.fmt_reg	= S5P_CSIS_CFG_FMT_USER(1),
+		.pix_hor_align	= 1,
+	}, {
+		.code		= V4L2_MBUS_FMT_SGRBG10_1X10,
+		.fmt_reg	= S5P_CSIS_CFG_FMT_RAW10,
+		.pix_hor_align	= 1,
+	},
+};
+
+static struct s5p_csis_state *to_s5p_csis_state(struct v4l2_subdev *sdev)
+{
+	return container_of(sdev, struct s5p_csis_state, sd);
+}
+
+static void s5p_csis_enable_interrupts(struct s5p_csis_state *state, int on)
+{
+	u32 cfg = readl(state->regs + S5P_CSIS_CTRL);
+
+	if (on)
+		cfg |= S5P_CSIS_INTMSK_EN_ALL;
+	else
+		cfg &= ~S5P_CSIS_INTMSK_EN_ALL;
+	writel(cfg, state->regs + S5P_CSIS_INTMSK);
+}
+
+static void s5p_csis_reset(struct s5p_csis_state *state)
+{
+	u32 cfg = readl(state->regs + S5P_CSIS_CTRL);
+
+	writel(cfg | S5P_CSIS_CTRL_RESET, state->regs + S5P_CSIS_CTRL);
+	udelay(10);
+}
+
+static void s5p_csis_system_enable(struct s5p_csis_state *state, int on)
+{
+	u32 cfg;
+
+	cfg = readl(state->regs + S5P_CSIS_CTRL);
+	if (on)
+		cfg |= S5P_CSIS_CTRL_ENABLE;
+	else
+		cfg &= ~S5P_CSIS_CTRL_ENABLE;
+	writel(cfg, state->regs + S5P_CSIS_CTRL);
+
+	cfg = readl(state->regs + S5P_CSIS_DPHYCTRL);
+	if (on)
+		cfg |= S5P_CSIS_DPHYCTRL_ENABLE;
+	else
+		cfg &= ~S5P_CSIS_DPHYCTRL_ENABLE;
+	writel(cfg, state->regs + S5P_CSIS_DPHYCTRL);
+
+	s5p_csis_enable_interrupts(state, on);
+}
+
+static int s5p_csis_set_format(struct s5p_csis_state *state)
+{
+	u32 cfg;
+	int i = ARRAY_SIZE(s5p_csis_formats);
+
+	v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
+		 state->fmt.code, state->fmt.width, state->fmt.height);
+
+	/* Color format */
+	cfg = readl(state->regs + S5P_CSIS_CONFIG);
+	cfg &= ~S5P_CSIS_CFG_FMT_MASK;
+
+	while (i--)
+		if (state->fmt.code == s5p_csis_formats[i].code)
+			break;
+
+	if (i >= ARRAY_SIZE(s5p_csis_formats))
+		return -EINVAL;
+
+	writel(cfg | s5p_csis_formats[i].fmt_reg,
+	       state->regs + S5P_CSIS_CONFIG);
+
+	/* Pixel resolution */
+	cfg = (state->fmt.width << 16) | state->fmt.height;
+	writel(cfg, state->regs + S5P_CSIS_RESOL);
+
+	return 0;
+}
+
+static void s5p_csis_set_hsync_settle(struct s5p_csis_state *state, int settle)
+{
+	u32 cfg = readl(state->regs + S5P_CSIS_DPHYCTRL);
+
+	cfg &= ~S5P_CSIS_DPHYCTRL_HSS_MASK;
+	cfg |= (settle << 27);
+	writel(cfg, state->regs + S5P_CSIS_DPHYCTRL);
+}
+
+static void s5p_csis_set_params(struct s5p_csis_state *state)
+{
+	struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
+	u32 cfg, tmp;
+
+	/* Number of MIPI lanes used */
+	cfg = readl(state->regs + S5P_CSIS_CONFIG);
+	cfg &= ~S5P_CSIS_CFG_NR_LANE_MASK;
+	tmp = (pdata->lanes - 1) & 0x3;
+	writel(cfg | tmp, state->regs + S5P_CSIS_CONFIG);
+
+	s5p_csis_set_format(state);
+
+	s5p_csis_set_hsync_settle(state, pdata->hs_settle);
+
+	/* CSI bus data alignment. */
+	cfg = readl(state->regs + S5P_CSIS_CTRL);
+
+	if (pdata->alignment == 32)
+		cfg |= S5P_CSIS_CTRL_ALIGN_32BIT;
+	else /* 24-bits */
+		cfg &= ~S5P_CSIS_CTRL_ALIGN_32BIT;
+
+	/* Not using external clock. */
+	cfg |= S5P_CSIS_CTRL_WCLK_EXTCLK;
+
+	writel(cfg, state->regs + S5P_CSIS_CTRL);
+
+	/* Update the shadow register. */
+	cfg = readl(state->regs + S5P_CSIS_CTRL);
+	writel(cfg | S5P_CSIS_CTRL_UPDATE_SHADOW, state->regs + S5P_CSIS_CTRL);
+}
+
+static void s5p_csis_clk_enable(struct s5p_csis_state *state, bool on)
+{
+	int i;
+
+	for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
+		if (!state->clock[i])
+			continue;
+		if (on)
+			clk_enable(state->clock[i]);
+		else
+			clk_disable(state->clock[i]);
+	}
+
+	v4l2_dbg(1, debug, &state->sd, "%s: clocks %sabled\n",
+		 __func__, on ? "en" : "dis");
+}
+
+static void s5p_csis_clk_put(struct s5p_csis_state *state)
+{
+	int i = NUM_CSIS_CLOCKS;
+
+	while (--i >= 0) {
+		if (!state->clock[i])
+			continue;
+		clk_put(state->clock[i]);
+	}
+}
+
+static int s5p_csis_clk_get(struct s5p_csis_state *state)
+{
+	struct device *dev = &state->pdev->dev;
+	int i;
+
+	for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
+		state->clock[i] = clk_get(dev, csi_clock_name[i]);
+
+		if (IS_ERR(state->clock[i])) {
+			dev_err(dev, "failed to get clock: %s\n",
+				csi_clock_name[i]);
+			return -ENXIO;
+		}
+	}
+	return 0;
+}
+
+static int mipi_csis_power(struct v4l2_subdev *sd, int on)
+{
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+	struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
+	int ret;
+
+	if (on) {
+		ret = regulator_enable(state->supply);
+		if (!ret && pdata->phy_enable)
+			ret = pdata->phy_enable(state->pdev, true);
+		if (!ret)
+			set_bit(CSIS_PWR_ST_POWERED, &state->power);
+	} else {
+		if (pdata->phy_enable) {
+			ret = pdata->phy_enable(state->pdev, false);
+			if (ret)
+				return ret;
+		}
+		ret = regulator_disable(state->supply);
+		if (!ret)
+			clear_bit(CSIS_PWR_ST_POWERED, &state->power);
+	}
+
+	if (!ret)
+		v4l2_dbg(1, debug, sd, "%s: regulator is %s\n",
+			 __func__, on ? "on" : "off");
+	return ret;
+}
+
+static int s5p_csis_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+	struct device *dev = &state->pdev->dev;
+	int ret = 0;
+
+	v4l2_dbg(1, debug, sd, "%s: on: %d, state: 0x%lx\n",  __func__,
+		 on, state->power);
+
+	if (on) {
+		set_bit(CSIS_PWR_ST_POWERED, &state->power);
+		ret = pm_runtime_get_sync(dev);
+	} else
+		ret = pm_runtime_put_sync(dev);
+
+	if ((!ret && !on) || (ret && on))
+		clear_bit(CSIS_PWR_ST_POWERED, &state->power);
+
+	return ret;
+}
+
+static inline struct s5p_csis_color_format const *find_csis_format(
+	struct v4l2_mbus_framefmt *mf)
+{
+	int i = ARRAY_SIZE(s5p_csis_formats);
+
+	while (i--)
+		if (mf->code == s5p_csis_formats[i].code)
+			break;
+
+	if (i < 0)
+		return NULL;
+
+	return &s5p_csis_formats[i];
+}
+
+static int s5p_csis_try_fmt(struct v4l2_subdev *sd,
+			    struct v4l2_mbus_framefmt *mf)
+{
+	struct s5p_csis_color_format const *csis_fmt;
+
+	if (!sd || !mf)
+		return -EINVAL;
+
+	csis_fmt = find_csis_format(mf);
+
+	if (csis_fmt == NULL)
+		csis_fmt = &s5p_csis_formats[0];
+
+	mf->code = csis_fmt->code;
+
+	/* Adjust pixel size if required so it fits in the supported range
+	   and meets the aligment requirements. */
+	v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
+			      csis_fmt->pix_hor_align,
+			      &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
+			      0);
+	return 0;
+}
+
+static int s5p_csis_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
+{
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+	struct s5p_csis_color_format const *csis_fmt = find_csis_format(mf);
+
+	v4l2_dbg(1, debug, sd, "%s: w: %d, h: %d\n", __func__,
+		 mf->width, mf->height);
+
+	if (csis_fmt == NULL ||
+	   mf->width > CSIS_MAX_PIX_WIDTH  ||
+	   mf->height > CSIS_MAX_PIX_WIDTH ||
+	   mf->width & (u32)(csis_fmt->pix_hor_align - 1))
+		return -EINVAL;
+
+	printk(KERN_DEBUG "%s: w: %d, h: %d\n", __func__,
+					mf->width, mf->height);
+	state->fmt = *mf;
+
+	return 0;
+}
+
+static int s5p_csis_g_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
+{
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+
+	*mf = state->fmt;
+	return 0;
+}
+
+static void s5p_csis_start_stream(struct s5p_csis_state *state)
+{
+	s5p_csis_reset(state);
+	s5p_csis_set_params(state);
+	s5p_csis_system_enable(state, true);
+}
+
+static void s5p_csis_stop_stream(struct s5p_csis_state *state)
+{
+	s5p_csis_enable_interrupts(state, false);
+	s5p_csis_system_enable(state, false);
+}
+
+static int s5p_csis_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+
+	v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%lx\n", __func__,
+		 enable, state->power);
+
+	if (test_bit(CSIS_PWR_ST_SUSPENDED, &state->power))
+		return -EBUSY;
+
+	mutex_lock(&state->lock);
+	if (enable) {
+		s5p_csis_start_stream(state);
+		set_bit(CSIS_PWR_ST_STREAMING, &state->power);
+	} else {
+		s5p_csis_stop_stream(state);
+		clear_bit(CSIS_PWR_ST_STREAMING, &state->power);
+	}
+	mutex_unlock(&state->lock);
+
+	return 0;
+}
+
+static struct v4l2_subdev_core_ops s5p_csis_core_ops = {
+	.s_power = s5p_csis_s_power,
+};
+
+static struct v4l2_subdev_video_ops s5p_csis_video_ops = {
+	.try_mbus_fmt	= s5p_csis_try_fmt,
+	.g_mbus_fmt	= s5p_csis_g_fmt,
+	.s_mbus_fmt	= s5p_csis_s_fmt,
+	.s_stream	= s5p_csis_s_stream,
+};
+
+static struct v4l2_subdev_ops s5p_csis_subdev_ops = {
+	.core	= &s5p_csis_core_ops,
+	.video	= &s5p_csis_video_ops,
+};
+
+static irqreturn_t s5p_csis_isr(int irq, void *dev_id)
+{
+	struct s5p_csis_state *state = dev_id;
+	u32 cfg;
+
+	/* Just clear the interrupt pending bits. */
+	cfg = readl(state->regs + S5P_CSIS_INTSRC);
+	writel(cfg, state->regs + S5P_CSIS_INTSRC);
+
+	if (unlikely(cfg & S5P_CSIS_INTSRC_ERR)) {
+		if (err_print_cnt < 30) {
+			printk(KERN_ERR "csis error interrupt[%d]: %#x\n",
+							err_print_cnt, cfg);
+			err_print_cnt++;
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static int s5p_csis_probe(struct platform_device *pdev)
+{
+	struct s5p_platform_mipi_csis *pdata;
+	struct resource *mem_res;
+	struct resource *regs_res;
+	struct s5p_csis_state *state;
+	int ret = -ENODEV;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	mutex_init(&state->lock);
+	state->pdev = pdev;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "Platform data not set\n");
+		goto p_err1;
+	}
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "Failed to get io memory region\n");
+		goto p_err1;
+	}
+
+	regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
+				      pdev->name);
+	if (!regs_res) {
+		dev_err(&pdev->dev, "Failed to request io memory region\n");
+		goto p_err1;
+	}
+	state->regs_res = regs_res;
+
+	state->regs = ioremap(mem_res->start, resource_size(mem_res));
+	if (!state->regs) {
+		dev_err(&pdev->dev, "Failed to remap io region\n");
+		goto p_err2;
+	}
+
+	if (s5p_csis_clk_get(state))
+		goto p_err3;
+
+	if (pdata->clk_rate) {
+		struct clk *srclk;
+		if (soc_is_exynos4212() || soc_is_exynos4412())
+			srclk = clk_get(&state->pdev->dev, "mout_mpll_user");
+		else
+			srclk = clk_get(&state->pdev->dev, "mout_mpll");
+
+		if (IS_ERR_OR_NULL(srclk)) {
+			dev_err(&state->pdev->dev, "failed to get mipi-csis source clock\n");
+			return -ENXIO;
+		}
+		clk_set_parent(state->clock[CSIS_CLK_BUS], srclk);
+		clk_put(srclk);
+		clk_set_rate(state->clock[CSIS_CLK_BUS], pdata->clk_rate);
+	}
+
+	if (pdata->phy_enable)
+		pdata->phy_enable(state->pdev, false);
+
+	state->irq = platform_get_irq(pdev, 0);
+	if (state->irq < 0) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		goto p_err4;
+	}
+
+	ret = request_irq(state->irq, s5p_csis_isr, 0,
+				dev_name(&pdev->dev), state);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq failed\n");
+		goto p_err4;
+	}
+
+	state->supply = regulator_get(&pdev->dev, "mipi_csi");
+	if (IS_ERR(state->supply)) {
+		state->supply = NULL;
+		goto p_err5;
+	}
+
+	v4l2_subdev_init(&state->sd, &s5p_csis_subdev_ops);
+	state->sd.owner = THIS_MODULE;
+	strcpy(state->sd.name, MODULE_NAME);
+
+	/* This allows to retrieve the platform device id by the host driver */
+	v4l2_set_subdevdata(&state->sd, pdev);
+
+	/* .. and a pointer to the subdev. */
+	platform_set_drvdata(pdev, &state->sd);
+
+	pm_runtime_enable(&pdev->dev);
+
+	v4l2_info(&state->sd, "mipi-csis%d probed\n", pdev->id);
+
+	return 0;
+
+p_err5:
+	free_irq(state->irq, state);
+p_err4:
+	s5p_csis_clk_put(state);
+p_err3:
+	iounmap(state->regs);
+p_err2:
+	release_mem_region(regs_res->start, resource_size(regs_res));
+p_err1:
+	kfree(state);
+	return ret;
+}
+
+static int s5p_csis_remove(struct platform_device *pdev)
+{
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+	struct resource *res = state->regs_res;
+
+	s5p_csis_s_power(&state->sd, 0);
+	pm_runtime_disable(&pdev->dev);
+	s5p_csis_clk_put(state);
+
+	free_irq(state->irq, state);
+	iounmap(state->regs);
+	release_mem_region(res->start, resource_size(res));
+	kfree(state);
+	return 0;
+}
+
+static int s5p_csis_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+
+	mutex_lock(&state->lock);
+
+	v4l2_dbg(1, debug, sd, "%s: state: 0x%lx\n",
+		 __func__, state->power);
+
+	if (test_bit(CSIS_PWR_ST_POWERED, &state->power)) {
+		s5p_csis_stop_stream(state);
+		mipi_csis_power(sd, 0);
+
+		s5p_csis_clk_enable(to_s5p_csis_state(sd), false);
+	}
+
+	set_bit(CSIS_PWR_ST_SUSPENDED, &state->power);
+	mutex_unlock(&state->lock);
+
+	return 0;
+}
+
+static int s5p_csis_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+	struct s5p_csis_state *state = to_s5p_csis_state(sd);
+
+	mutex_lock(&state->lock);
+
+	v4l2_dbg(1, debug, sd, "%s: state: 0x%lx\n",
+		 __func__, state->power);
+
+	if (test_bit(CSIS_PWR_ST_POWERED, &state->power)) {
+		mipi_csis_power(sd, 1);
+
+		s5p_csis_clk_enable(to_s5p_csis_state(sd), true);
+	}
+
+	if (test_bit(CSIS_PWR_ST_STREAMING, &state->power))
+		s5p_csis_start_stream(state);
+
+	clear_bit(CSIS_PWR_ST_SUSPENDED, &state->power);
+	mutex_unlock(&state->lock);
+
+	return 0;
+}
+
+static const struct dev_pm_ops s5p_csis_pm_ops = {
+	.runtime_suspend = s5p_csis_suspend,
+	.runtime_resume	 = s5p_csis_resume,
+	.suspend	 = s5p_csis_suspend,
+	.resume		 = s5p_csis_resume,
+};
+
+static struct platform_driver s5p_csis_driver = {
+	.probe		= s5p_csis_probe,
+	.remove		= s5p_csis_remove,
+	.driver		= {
+		.name	= MODULE_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &s5p_csis_pm_ops,
+	},
+};
+
+static int __init s5p_csis_init(void)
+{
+	return platform_driver_probe(&s5p_csis_driver, s5p_csis_probe);
+}
+
+static void __exit s5p_csis_exit(void)
+{
+	platform_driver_unregister(&s5p_csis_driver);
+}
+
+module_init(s5p_csis_init);
+module_exit(s5p_csis_exit);
+
+MODULE_AUTHOR("Sylwester Nawrocki, <s.nawrocki@samsung.com>");
+MODULE_DESCRIPTION("S5P MIPI-CSI2 slave interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5p-mfc/Makefile b/drivers/media/video/s5p-mfc/Makefile
new file mode 100644
index 0000000..f595724
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) := s5p-mfc.o
+s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o
+s5p-mfc-y += s5p_mfc_dec.o s5p_mfc_enc.o
+s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_inst.o
+s5p-mfc-y += s5p_mfc_mem.o s5p_mfc_reg.o s5p_mfc_pm.o
+obj-$(CONFIG_S5P_MFC_V5) += s5p_mfc_opr_v5.o s5p_mfc_cmd_v5.o s5p_mfc_shm.o
+obj-$(CONFIG_S5P_MFC_V6) += s5p_mfc_opr_v6.o s5p_mfc_cmd_v6.o
diff --git a/drivers/media/video/s5p-mfc/regs-mfc-v5.h b/drivers/media/video/s5p-mfc/regs-mfc-v5.h
new file mode 100644
index 0000000..b98aa5d
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/regs-mfc-v5.h
@@ -0,0 +1,436 @@
+/*
+ * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _REGS_FIMV_V5_H
+#define _REGS_FIMV_V5_H
+
+#define S5P_FIMV_REG_SIZE	(S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
+#define S5P_FIMV_REG_COUNT	((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
+
+/* Number of bits that the buffer address should be shifted for particular
+ * MFC buffers.  */
+#define S5P_FIMV_MEM_OFFSET		11
+
+#define S5P_FIMV_START_ADDR		0x0000
+#define S5P_FIMV_END_ADDR		0xe008
+
+#define S5P_FIMV_SW_RESET		0x0000
+#define S5P_FIMV_RISC_HOST_INT		0x0008
+
+/* Command from HOST to RISC */
+#define S5P_FIMV_HOST2RISC_CMD		0x0030
+#define S5P_FIMV_HOST2RISC_ARG1		0x0034
+#define S5P_FIMV_HOST2RISC_ARG2		0x0038
+#define S5P_FIMV_HOST2RISC_ARG3		0x003c
+#define S5P_FIMV_HOST2RISC_ARG4		0x0040
+
+/* Command from RISC to HOST */
+#define S5P_FIMV_RISC2HOST_CMD		0x0044
+#define S5P_FIMV_RISC2HOST_CMD_MASK	0x1FFFF
+#define S5P_FIMV_RISC2HOST_ARG1		0x0048
+#define S5P_FIMV_RISC2HOST_ARG2		0x004c
+#define S5P_FIMV_RISC2HOST_ARG3		0x0050
+#define S5P_FIMV_RISC2HOST_ARG4		0x0054
+
+#define S5P_FIMV_FW_VERSION		0x0058
+#define S5P_FIMV_FW_Y_SHIFT		16
+#define S5P_FIMV_FW_M_SHIFT		8
+#define S5P_FIMV_FW_D_SHIFT		0
+#define S5P_FIMV_FW_MASK		0xff
+
+#define S5P_FIMV_SYS_MEM_SZ		0x005c
+#define S5P_FIMV_FW_STATUS		0x0080
+/* Memory controller register */
+#define S5P_FIMV_MC_DRAMBASE_ADR_A	0x0508
+#define S5P_FIMV_MC_DRAMBASE_ADR_B	0x050c
+#define S5P_FIMV_MC_STATUS		0x0510
+
+/* Common register */
+#define S5P_FIMV_COMMON_BASE_A		0x0600
+#define S5P_FIMV_COMMON_BASE_B		0x0700
+
+/* Decoder */
+#define S5P_FIMV_DEC_CHROMA_ADR		(S5P_FIMV_COMMON_BASE_A)
+#define S5P_FIMV_DEC_LUMA_ADR		(S5P_FIMV_COMMON_BASE_B)
+
+/* H.264 decoding */
+#define S5P_FIMV_H264_VERT_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)	/* vertical neighbor motion vector */
+#define S5P_FIMV_H264_NB_IP_ADR		(S5P_FIMV_COMMON_BASE_A + 0x90)	/* neighbor pixels for intra pred */
+#define S5P_FIMV_H264_MV_ADR		(S5P_FIMV_COMMON_BASE_B + 0x80)	/* H264 motion vector */
+
+/* MPEG4 decoding */
+#define S5P_FIMV_MPEG4_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)	/* neighbor AC/DC coeff. */
+#define S5P_FIMV_MPEG4_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)	/* upper neighbor motion vector */
+#define S5P_FIMV_MPEG4_SA_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x94)	/* subseq. anchor motion vector */
+#define S5P_FIMV_MPEG4_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)	/* overlap transform line */
+#define S5P_FIMV_MPEG4_SP_ADR		(S5P_FIMV_COMMON_BASE_A + 0xa8)	/* syntax parser */
+
+/* H.263 decoding */
+#define S5P_FIMV_H263_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)
+#define S5P_FIMV_H263_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)
+#define S5P_FIMV_H263_SA_MV_ADR		(S5P_FIMV_COMMON_BASE_A + 0x94)
+#define S5P_FIMV_H263_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)
+
+/* VC-1 decoding */
+#define S5P_FIMV_VC1_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)
+#define S5P_FIMV_VC1_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)
+#define S5P_FIMV_VC1_SA_MV_ADR		(S5P_FIMV_COMMON_BASE_A + 0x94)
+#define S5P_FIMV_VC1_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)
+#define S5P_FIMV_VC1_BITPLANE3_ADR	(S5P_FIMV_COMMON_BASE_A + 0x9c)	/* bitplane3 */
+#define S5P_FIMV_VC1_BITPLANE2_ADR	(S5P_FIMV_COMMON_BASE_A + 0xa0)	/* bitplane2 */
+#define S5P_FIMV_VC1_BITPLANE1_ADR	(S5P_FIMV_COMMON_BASE_A + 0xa4)	/* bitplane1 */
+
+/* Encoder */
+#define S5P_FIMV_ENC_REF0_LUMA_ADR	(S5P_FIMV_COMMON_BASE_A + 0x1c)	/* reconstructed luma */
+#define S5P_FIMV_ENC_REF1_LUMA_ADR	(S5P_FIMV_COMMON_BASE_A + 0x20)
+#define S5P_FIMV_ENC_REF0_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B)	/* reconstructed chroma */
+#define S5P_FIMV_ENC_REF1_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x04)
+#define S5P_FIMV_ENC_REF2_LUMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x10)
+#define S5P_FIMV_ENC_REF2_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x08)
+#define S5P_FIMV_ENC_REF3_LUMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x14)
+#define S5P_FIMV_ENC_REF3_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x0c)
+
+/* H.264 encoding */
+#define S5P_FIMV_H264_UP_MV_ADR		(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_H264_NBOR_INFO_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* entropy engine's neighbor info. */
+#define S5P_FIMV_H264_UP_INTRA_MD_ADR	(S5P_FIMV_COMMON_BASE_A + 0x08)	/* upper intra MD */
+#define S5P_FIMV_H264_COZERO_FLAG_ADR	(S5P_FIMV_COMMON_BASE_A + 0x10)	/* direct cozero flag */
+#define S5P_FIMV_H264_UP_INTRA_PRED_ADR	(S5P_FIMV_COMMON_BASE_B + 0x40)	/* upper intra PRED */
+
+/* H.263 encoding */
+#define S5P_FIMV_H263_UP_MV_ADR		(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_H263_ACDC_COEF_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* upper Q coeff. */
+
+/* MPEG4 encoding */
+#define S5P_FIMV_MPEG4_UP_MV_ADR	(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_MPEG4_ACDC_COEF_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* upper Q coeff. */
+#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR	(S5P_FIMV_COMMON_BASE_A + 0x10)	/* direct cozero flag */
+
+#define S5P_FIMV_ENC_REF_B_LUMA_ADR     0x062c /* ref B Luma addr */
+#define S5P_FIMV_ENC_REF_B_CHROMA_ADR   0x0630 /* ref B Chroma addr */
+
+#define S5P_FIMV_ENC_CUR_LUMA_ADR	0x0718 /* current Luma addr */
+#define S5P_FIMV_ENC_CUR_CHROMA_ADR	0x071C /* current Chroma addr */
+
+/* Codec common register */
+#define S5P_FIMV_ENC_HSIZE_PX		0x0818 /* frame width at encoder */
+#define S5P_FIMV_ENC_VSIZE_PX		0x081c /* frame height at encoder */
+#define S5P_FIMV_ENC_PROFILE		0x0830 /* profile register */
+#define S5P_FIMV_ENC_PROFILE_H264_MAIN			0
+#define S5P_FIMV_ENC_PROFILE_H264_HIGH			1
+#define S5P_FIMV_ENC_PROFILE_H264_BASELINE		2
+#define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE	3
+#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE		0
+#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE	1
+#define S5P_FIMV_ENC_PIC_STRUCT		0x083c /* picture field/frame flag */
+#define S5P_FIMV_ENC_LF_CTRL		0x0848 /* loop filter control */
+#define S5P_FIMV_ENC_ALPHA_OFF		0x084c /* loop filter alpha offset */
+#define S5P_FIMV_ENC_BETA_OFF		0x0850 /* loop filter beta offset */
+#define S5P_FIMV_MR_BUSIF_CTRL		0x0854 /* hidden, bus interface ctrl */
+#define S5P_FIMV_ENC_PXL_CACHE_CTRL	0x0a00 /* pixel cache control */
+
+/* Channel & stream interface register */
+#define S5P_FIMV_SI_RTN_CHID		0x2000 /* Return CH instance ID register */
+#define S5P_FIMV_SI_CH0_INST_ID		0x2040 /* codec instance ID */
+#define S5P_FIMV_SI_CH1_INST_ID		0x2080 /* codec instance ID */
+/* Decoder */
+#define S5P_FIMV_SI_VRESOL		0x2004 /* vertical resolution of decoder */
+#define S5P_FIMV_SI_HRESOL		0x2008 /* horizontal resolution of decoder */
+#define S5P_FIMV_SI_BUF_NUMBER		0x200c /* number of frames in the decoded pic */
+#define S5P_FIMV_SI_DISPLAY_Y_ADR	0x2010 /* luma address of displayed pic */
+#define S5P_FIMV_SI_DISPLAY_C_ADR	0x2014 /* chroma address of displayed pic */
+#define S5P_FIMV_SI_CONSUMED_BYTES	0x2018 /* Consumed number of bytes to decode
+								a frame */
+#define S5P_FIMV_SI_DISPLAY_STATUS	0x201c /* status of decoded picture */
+#define S5P_FIMV_SI_FRAME_TYPE		0x2020 /* frame type such as skip/I/P/B */
+#define S5P_FIMV_SI_DECODED_STATUS	0x202c /* status of decoded picture */
+#define S5P_FIMV_DEC_CRC_GEN_MASK	0x3
+#define S5P_FIMV_DEC_CRC_GEN_SHIFT	4
+
+#define S5P_FIMV_SI_CH0_SB_ST_ADR	0x2044 /* start addr of stream buf */
+#define S5P_FIMV_SI_CH0_SB_FRM_SIZE	0x2048 /* size of stream buf */
+#define S5P_FIMV_SI_CH0_DESC_ADR	0x204c /* addr of descriptor buf */
+#define S5P_FIMV_SI_CH0_CPB_SIZE	0x2058 /* max size of coded pic. buf */
+#define S5P_FIMV_SI_CH0_DESC_SIZE	0x205c /* max size of descriptor buf */
+
+#define S5P_FIMV_SI_CH1_SB_ST_ADR	0x2084 /* start addr of stream buf */
+#define S5P_FIMV_SI_CH1_SB_FRM_SIZE	0x2088 /* size of stream buf */
+#define S5P_FIMV_SI_CH1_DESC_ADR	0x208c /* addr of descriptor buf */
+#define S5P_FIMV_SI_CH1_CPB_SIZE	0x2098 /* max size of coded pic. buf */
+#define S5P_FIMV_SI_CH1_DESC_SIZE	0x209c /* max size of descriptor buf */
+
+#define S5P_FIMV_SI_FIMV1_HRESOL	0x2054 /* horizontal resolution */
+#define S5P_FIMV_SI_FIMV1_VRESOL	0x2050 /* vertical resolution */
+#define S5P_FIMV_CRC_LUMA0		0x2030 /* luma crc data per frame(top field)*/
+#define S5P_FIMV_CRC_CHROMA0		0x2034 /* chroma crc data per frame(top field)*/
+#define S5P_FIMV_CRC_LUMA1		0x2038 /* luma crc data per bottom field */
+#define S5P_FIMV_CRC_CHROMA1		0x203c /* chroma crc data per bottom field */
+
+/* Display status */
+#define S5P_FIMV_DEC_STATUS_DECODING_ONLY		0
+#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY		1
+#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY		2
+#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY		3
+#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK	7
+#define S5P_FIMV_DEC_STATUS_PROGRESSIVE			(0<<3)
+#define S5P_FIMV_DEC_STATUS_INTERLACE			(1<<3)
+#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK		(1<<3)
+#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO		(0<<4)
+#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR		(1<<4)
+#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK		(1<<4)
+#define S5P_FIMV_DEC_STATUS_CRC_GENERATED		(1<<5)
+#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED		(0<<5)
+#define S5P_FIMV_DEC_STATUS_CRC_MASK			(1<<5)
+
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK		(3<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC		(1<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC		(2<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT		4
+
+/* Decode frame address */
+#define S5P_FIMV_DECODE_Y_ADR			0x2024
+#define S5P_FIMV_DECODE_C_ADR			0x2028
+
+/* Decoded frame tpe */
+#define S5P_FIMV_DECODE_FRAME_TYPE		0x2020
+#define S5P_FIMV_DECODE_FRAME_MASK		7
+
+#define S5P_FIMV_DECODE_FRAME_SKIPPED		0
+#define S5P_FIMV_DECODE_FRAME_I_FRAME		1
+#define S5P_FIMV_DECODE_FRAME_P_FRAME		2
+#define S5P_FIMV_DECODE_FRAME_B_FRAME		3
+#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME	4
+
+/* Sizes of buffers required for decoding */
+#define S5P_FIMV_DEC_NB_IP_SIZE			(32 * 1024)
+#define S5P_FIMV_DEC_VERT_NB_MV_SIZE		(16 * 1024)
+#define S5P_FIMV_DEC_NB_DCAC_SIZE		(16 * 1024)
+#define S5P_FIMV_DEC_UPNB_MV_SIZE		(68 * 1024)
+#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE		(136 * 1024)
+#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE     (32 * 1024)
+#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE		(2 * 1024)
+#define S5P_FIMV_DEC_STX_PARSER_SIZE		(68 * 1024)
+
+#define S5P_FIMV_DEC_BUF_ALIGN			(8 * 1024)
+#define S5P_FIMV_ENC_BUF_ALIGN			(8 * 1024)
+#define S5P_FIMV_NV12M_HALIGN			16
+#define S5P_FIMV_NV12M_LVALIGN			16
+#define S5P_FIMV_NV12M_CVALIGN			8
+#define S5P_FIMV_NV12MT_HALIGN			128
+#define S5P_FIMV_NV12MT_VALIGN			32
+#define S5P_FIMV_NV12M_SALIGN			2048
+#define S5P_FIMV_NV12MT_SALIGN			8192
+
+/* Sizes of buffers required for encoding */
+#define S5P_FIMV_ENC_UPMV_SIZE			(0x10000)
+#define S5P_FIMV_ENC_COLFLG_SIZE		(0x10000)
+#define S5P_FIMV_ENC_INTRAMD_SIZE		(0x10000)
+#define S5P_FIMV_ENC_INTRAPRED_SIZE		(0x4000)
+#define S5P_FIMV_ENC_NBORINFO_SIZE		(0x10000)
+#define S5P_FIMV_ENC_ACDCCOEF_SIZE		(0x10000)
+
+/* Encoder */
+#define S5P_FIMV_ENC_SI_STRM_SIZE	0x2004 /* stream size */
+#define S5P_FIMV_ENC_SI_PIC_CNT		0x2008 /* picture count */
+#define S5P_FIMV_ENC_SI_WRITE_PTR	0x200c /* write pointer */
+#define S5P_FIMV_ENC_SI_SLICE_TYPE	0x2010 /* slice type(I/P/B/IDR) */
+#define S5P_FIMV_ENCODED_Y_ADDR         0x2014 /* the addr of the encoded luma pic */
+#define S5P_FIMV_ENCODED_C_ADDR         0x2018 /* the addr of the encoded chroma pic */
+
+#define S5P_FIMV_ENC_SI_CH0_SB_ADR	0x2044 /* addr of stream buf */
+#define S5P_FIMV_ENC_SI_CH0_SB_SIZE	0x204c /* size of stream buf */
+#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR	0x2050 /* current Luma addr */
+#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR	0x2054 /* current Chroma addr */
+#define S5P_FIMV_ENC_SI_CH0_FRAME_INS	0x2058 /* frame insertion */
+
+#define S5P_FIMV_ENC_SI_CH1_SB_ADR	0x2084 /* addr of stream buf */
+#define S5P_FIMV_ENC_SI_CH1_SB_SIZE	0x208c /* size of stream buf */
+#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR	0x2090 /* current Luma addr */
+#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR	0x2094 /* current Chroma addr */
+#define S5P_FIMV_ENC_SI_CH1_FRAME_INS	0x2098 /* frame insertion */
+
+#define S5P_FIMV_ENC_PIC_TYPE_CTRL	0xc504 /* pic type level control */
+#define S5P_FIMV_ENC_B_RECON_WRITE_ON	0xc508 /* B frame recon write ctrl */
+#define S5P_FIMV_ENC_MSLICE_CTRL	0xc50c /* multi slice control */
+#define S5P_FIMV_ENC_MSLICE_MB		0xc510 /* MB number in the one slice */
+#define S5P_FIMV_ENC_MSLICE_BIT		0xc514 /* bit count for one slice */
+#define S5P_FIMV_ENC_CIR_CTRL		0xc518 /* number of intra refresh MB */
+#define S5P_FIMV_ENC_MAP_FOR_CUR	0xc51c /* linear or 64x32 tiled mode */
+#define S5P_FIMV_ENC_PADDING_CTRL	0xc520 /* padding control */
+
+#define S5P_FIMV_ENC_RC_CONFIG		0xc5a0 /* RC config */
+#define S5P_FIMV_ENC_RC_BIT_RATE	0xc5a8 /* bit rate */
+#define S5P_FIMV_ENC_RC_QBOUND		0xc5ac /* max/min QP */
+#define S5P_FIMV_ENC_RC_RPARA		0xc5b0 /* rate control reaction coeff */
+#define S5P_FIMV_ENC_RC_MB_CTRL		0xc5b4 /* MB adaptive scaling */
+
+/* Encoder for H264 only */
+#define S5P_FIMV_ENC_H264_ENTRP_MODE	0xd004 /* CAVLC or CABAC */
+#define S5P_FIMV_ENC_H264_ALPHA_OFF	0xd008 /* loop filter alpha offset */
+#define S5P_FIMV_ENC_H264_BETA_OFF	0xd00c /* loop filter beta offset */
+#define S5P_FIMV_ENC_H264_NUM_OF_REF	0xd010 /* number of reference for P/B */
+#define S5P_FIMV_ENC_H264_TRANS_FLAG	0xd034 /* 8x8 transform flag in PPS & high profile */
+
+#define S5P_FIMV_ENC_RC_FRAME_RATE	0xd0d0 /* frame rate */
+
+/* Encoder for MPEG4 only */
+#define S5P_FIMV_ENC_MPEG4_QUART_PXL	0xe008 /* qpel interpolation ctrl */
+
+/* Additional */
+#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL   0x2068 /* DPB Config Control Register */
+#define S5P_FIMV_SLICE_INT_MASK		1
+#define S5P_FIMV_SLICE_INT_SHIFT	31
+#define S5P_FIMV_DDELAY_ENA_SHIFT	30
+#define S5P_FIMV_DDELAY_VAL_MASK	0xff
+#define S5P_FIMV_DDELAY_VAL_SHIFT	16
+#define S5P_FIMV_DPB_COUNT_MASK		0xffff
+
+#define S5P_FIMV_SI_CH0_RELEASE_BUF     0x2060 /* DPB release buffer register */
+#define S5P_FIMV_SI_CH0_HOST_WR_ADR	0x2064 /* address of shared memory */
+
+/* Codec numbers  */
+#define MFC_FORMATS_NO_CODEC		-1
+
+#define S5P_FIMV_CODEC_H264_DEC		0
+#define S5P_FIMV_CODEC_VC1_DEC		1
+#define S5P_FIMV_CODEC_MPEG4_DEC	2
+#define S5P_FIMV_CODEC_MPEG2_DEC	3
+#define S5P_FIMV_CODEC_H263_DEC		4
+#define S5P_FIMV_CODEC_VC1RCV_DEC	5
+#define S5P_FIMV_CODEC_FIMV1_DEC	6
+#define S5P_FIMV_CODEC_FIMV2_DEC	7
+#define S5P_FIMV_CODEC_FIMV3_DEC	8
+#define S5P_FIMV_CODEC_FIMV4_DEC	9
+
+#define S5P_FIMV_CODEC_H264_ENC		16
+#define S5P_FIMV_CODEC_MPEG4_ENC	17
+#define S5P_FIMV_CODEC_H263_ENC		18
+
+/* Channel Control Register */
+#define S5P_FIMV_CH_SEQ_HEADER		1
+#define S5P_FIMV_CH_FRAME_START		2
+#define S5P_FIMV_CH_LAST_FRAME		3
+#define S5P_FIMV_CH_INIT_BUFS		4
+#define S5P_FIMV_CH_FRAME_START_REALLOC	5
+
+#define S5P_FIMV_CH_MASK		7
+#define S5P_FIMV_CH_SHIFT		16
+
+/* Host to RISC command */
+#define S5P_FIMV_H2R_CMD_EMPTY		0
+#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE	1
+#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE	2
+#define S5P_FIMV_H2R_CMD_SYS_INIT	3
+#define S5P_FIMV_H2R_CMD_FLUSH		4
+#define S5P_FIMV_H2R_CMD_SLEEP		5
+#define S5P_FIMV_H2R_CMD_WAKEUP		6
+
+#define S5P_FIMV_R2H_CMD_EMPTY			0
+#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET	1
+#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET	2
+#define S5P_FIMV_R2H_CMD_RSV_RET		3
+#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET		4
+#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET		5
+#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET		6
+#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET	7
+#define S5P_FIMV_R2H_CMD_SYS_INIT_RET		8
+#define S5P_FIMV_R2H_CMD_FW_STATUS_RET		9
+#define S5P_FIMV_R2H_CMD_SLEEP_RET		10
+#define S5P_FIMV_R2H_CMD_WAKEUP_RET		11
+#define S5P_FIMV_R2H_CMD_FLUSH_RET		12
+#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET	15
+#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET		16
+#define S5P_FIMV_R2H_CMD_ERR_RET		32
+
+/* Dummy definition for MFCv6 compatibilty */
+#define S5P_FIMV_CODEC_H264_MVC_DEC		-1
+#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET		-1
+#define S5P_FIMV_MFC_RESET			-1
+#define S5P_FIMV_RISC_ON			-1
+#define S5P_FIMV_RISC_BASE_ADDRESS		-1
+#define S5P_FIMV_CODEC_VP8_DEC			-1
+#define S5P_FIMV_REG_CLEAR_BEGIN		0
+#define S5P_FIMV_REG_CLEAR_COUNT		0
+#define S5P_FIMV_CRC_DISP_LUMA0			S5P_FIMV_CRC_LUMA0
+#define S5P_FIMV_CRC_DISP_CHROMA0		S5P_FIMV_CRC_CHROMA0
+#define S5P_FIMV_CRC_DISP_STATUS		S5P_FIMV_SI_DECODED_STATUS
+#define S5P_FIMV_D_MVC_VIEW_ID			0
+#define S5P_FIMV_MFC_BUS_RESET_CTRL		-1
+#define S5P_FIMV_D_MIN_NUM_MV			-1
+#define S5P_FIMV_D_NUM_MV			-1
+#define S5P_FIMV_MFC_VERSION			0
+
+/* Error handling defines */
+#define S5P_FIMV_ERR_WARNINGS_START		145
+#define S5P_FIMV_ERR_DEC_MASK			0xFFFF
+#define S5P_FIMV_ERR_DEC_SHIFT			0
+#define S5P_FIMV_ERR_DSPL_MASK			0xFFFF0000
+#define S5P_FIMV_ERR_DSPL_SHIFT			16
+
+/* Shared memory registers' offsets */
+
+/* An offset of the start position in the stream when
+ * the start position is not aligned */
+#define S5P_FIMV_SHARED_CROP_INFO_H		0x0020
+#define S5P_FIMV_SHARED_CROP_LEFT_MASK		0xFFFF
+#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT		0
+#define S5P_FIMV_SHARED_CROP_RIGHT_MASK		0xFFFF0000
+#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT	16
+#define S5P_FIMV_SHARED_CROP_INFO_V		0x0024
+#define S5P_FIMV_SHARED_CROP_TOP_MASK		0xFFFF
+#define S5P_FIMV_SHARED_CROP_TOP_SHIFT		0
+#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK	0xFFFF0000
+#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT	16
+#define S5P_FIMV_SHARED_SET_FRAME_TAG		0x0004
+#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP	0x0008
+#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT	0x000C
+#define S5P_FIMV_SHARED_START_BYTE_NUM		0x0018
+#define S5P_FIMV_SHARED_PARAM_CHANGE		0x002c
+#define S5P_FIMV_SHARED_RC_VOP_TIMING		0x0030
+#define S5P_FIMV_SHARED_LUMA_DPB_SIZE		0x0064
+#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE		0x0068
+#define S5P_FIMV_SHARED_MV_SIZE			0x006C
+#define S5P_FIMV_SHARED_PIC_TIME_TOP		0x0010
+#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM		0x0014
+#define S5P_FIMV_SHARED_EXT_ENC_CONTROL		0x0028
+#define S5P_FIMV_SHARED_P_B_FRAME_QP		0x0070
+#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC	0x0074
+#define S5P_FIMV_SHARED_EXTENDED_SAR		0x0078
+#define S5P_FIMV_SHARED_NEW_RC_BIT_RATE		0x0090
+#define S5P_FIMV_SHARED_NEW_RC_FRAME_RATE	0x0094
+#define S5P_FIMV_SHARED_NEW_I_PERIOD		0x0098
+#define S5P_FIMV_SHARED_H264_I_PERIOD		0x009C
+#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG	0x00A0
+#define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT	2
+
+#define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL    0x16C
+#define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID  0x170
+#define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO     0x174
+#define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS     0x178
+
+/* SEI related information */
+#define S5P_FIMV_FRAME_PACK_SEI_AVAIL           S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL
+#define S5P_FIMV_FRAME_PACK_ARRGMENT_ID         S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID
+#define S5P_FIMV_FRAME_PACK_SEI_INFO            S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO
+#define S5P_FIMV_FRAME_PACK_GRID_POS            S5P_FIMV_SHARED_FRAME_PACK_GRID_POS
+
+#define S5P_FIMV_SHARED_SET_E_FRAME_TAG		S5P_FIMV_SHARED_SET_FRAME_TAG
+#define S5P_FIMV_SHARED_GET_E_FRAME_TAG		S5P_FIMV_SHARED_GET_FRAME_TAG_TOP
+#define S5P_FIMV_ENCODED_LUMA_ADDR		S5P_FIMV_ENCODED_Y_ADDR
+#define S5P_FIMV_ENCODED_CHROMA_ADDR		S5P_FIMV_ENCODED_C_ADDR
+#define	S5P_FIMV_FRAME_INSERTION		S5P_FIMV_ENC_SI_CH0_FRAME_INS
+
+#define S5P_FIMV_PARAM_CHANGE_FLAG		S5P_FIMV_SHARED_PARAM_CHANGE /* flag */
+#define S5P_FIMV_NEW_I_PERIOD			S5P_FIMV_SHARED_NEW_I_PERIOD
+#define S5P_FIMV_NEW_RC_FRAME_RATE		S5P_FIMV_SHARED_NEW_RC_FRAME_RATE
+#define S5P_FIMV_NEW_RC_BIT_RATE		S5P_FIMV_SHARED_NEW_RC_BIT_RATE
+
+#endif /* _REGS_FIMV_V5_H */
diff --git a/drivers/media/video/s5p-mfc/regs-mfc-v6.h b/drivers/media/video/s5p-mfc/regs-mfc-v6.h
new file mode 100644
index 0000000..8f09d6a
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/regs-mfc-v6.h
@@ -0,0 +1,682 @@
+/*
+ * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _REGS_FIMV_V6_H
+#define _REGS_FIMV_V6_H
+
+#define S5P_FIMV_REG_SIZE	(S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
+#define S5P_FIMV_REG_COUNT	((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
+
+/* Number of bits that the buffer address should be shifted for particular
+ * MFC buffers.  */
+#define S5P_FIMV_MEM_OFFSET		0
+
+#define S5P_FIMV_START_ADDR		0x0000
+#define S5P_FIMV_END_ADDR		0xfd80
+
+#define S5P_FIMV_REG_CLEAR_BEGIN	0xf000
+#define S5P_FIMV_REG_CLEAR_COUNT	1024
+
+/* Codec Common Registers */
+#define S5P_FIMV_RISC_ON			0x0000
+#define S5P_FIMV_RISC2HOST_INT			0x003C
+#define S5P_FIMV_HOST2RISC_INT			0x0044
+#define S5P_FIMV_RISC_BASE_ADDRESS		0x0054
+
+#define S5P_FIMV_MFC_RESET			0x1070
+
+/* FIXME: Need to unify H2R and CH */
+#define S5P_FIMV_HOST2RISC_CMD			0x1100
+#define S5P_FIMV_H2R_CMD_EMPTY			0
+#define S5P_FIMV_H2R_CMD_SYS_INIT		1
+#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE		2
+#define S5P_FIMV_CH_SEQ_HEADER			3
+#define S5P_FIMV_CH_INIT_BUFS			4
+#define S5P_FIMV_CH_FRAME_START			5
+#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE		6
+#define S5P_FIMV_H2R_CMD_SLEEP			7
+#define S5P_FIMV_H2R_CMD_WAKEUP			8
+#define S5P_FIMV_CH_LAST_FRAME			9
+#define S5P_FIMV_H2R_CMD_FLUSH			10
+/* RMVME: REALLOC used? */
+#define S5P_FIMV_CH_FRAME_START_REALLOC		5
+
+#define S5P_FIMV_RISC2HOST_CMD			0x1104
+#define S5P_FIMV_R2H_CMD_EMPTY			0
+#define S5P_FIMV_R2H_CMD_SYS_INIT_RET		1
+#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET	2
+#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET		3
+#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET	4
+
+#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET	6
+#define S5P_FIMV_R2H_CMD_SLEEP_RET		7
+#define S5P_FIMV_R2H_CMD_WAKEUP_RET		8
+#define S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET	9
+#define S5P_FIMV_R2H_CMD_DPB_FLUSH_RET		10
+#define S5P_FIMV_R2H_CMD_NAL_ABORT_RET		11
+#define S5P_FIMV_R2H_CMD_FW_STATUS_RET		12
+#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET		13
+#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET		14
+#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET		15
+#define S5P_FIMV_R2H_CMD_ENC_BUFFER_FUL_RET	16
+#define S5P_FIMV_R2H_CMD_ERR_RET		32
+
+#define S5P_FIMV_MFC_BUS_RESET_CTRL		0x7110
+#define S5P_FIMV_FW_VERSION			0xF000
+
+#define S5P_FIMV_INSTANCE_ID			0xF008
+#define S5P_FIMV_CODEC_TYPE			0xF00C
+#define S5P_FIMV_CONTEXT_MEM_ADDR		0xF014
+#define S5P_FIMV_CONTEXT_MEM_SIZE		0xF018
+#define S5P_FIMV_PIXEL_FORMAT			0xF020
+
+#define S5P_FIMV_METADATA_ENABLE		0xF024
+#define S5P_FIMV_MFC_VERSION			0xF028
+#define S5P_FIMV_DBG_BUFFER_ADDR		0xF030
+#define S5P_FIMV_DBG_BUFFER_SIZE		0xF034
+#define S5P_FIMV_RET_INSTANCE_ID		0xF070
+
+#define S5P_FIMV_ERROR_CODE			0xF074
+#define S5P_FIMV_ERR_WARNINGS_START		160
+#define S5P_FIMV_ERR_DEC_MASK			0xFFFF
+#define S5P_FIMV_ERR_DEC_SHIFT			0
+#define S5P_FIMV_ERR_DSPL_MASK			0xFFFF0000
+#define S5P_FIMV_ERR_DSPL_SHIFT			16
+
+#define S5P_FIMV_DBG_BUFFER_OUTPUT_SIZE		0xF078
+#define S5P_FIMV_METADATA_STATUS		0xF07C
+#define S5P_FIMV_METADATA_ADDR_MB_INFO		0xF080
+#define S5P_FIMV_METADATA_SIZE_MB_INFO		0xF084
+
+/* Decoder Registers */
+#define S5P_FIMV_D_CRC_CTRL			0xF0B0
+#define S5P_FIMV_D_DEC_OPTIONS			0xF0B4
+#define S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK	4
+#define S5P_FIMV_D_OPT_DDELAY_EN_SHIFT		3
+#define S5P_FIMV_D_OPT_LF_CTRL_SHIFT		1
+#define S5P_FIMV_D_OPT_LF_CTRL_MASK		0x3
+#define S5P_FIMV_D_OPT_TILE_MODE_SHIFT		0
+
+#define S5P_FIMV_D_DISPLAY_DELAY		0xF0B8
+
+#define S5P_FIMV_D_SET_FRAME_WIDTH		0xF0BC
+#define S5P_FIMV_D_SET_FRAME_HEIGHT		0xF0C0
+
+#define S5P_FIMV_D_SEI_ENABLE			0xF0C4
+
+/* Buffer setting registers */
+#define S5P_FIMV_D_MIN_NUM_DPB			0xF0F0
+#define S5P_FIMV_D_MIN_LUMA_DPB_SIZE		0xF0F4
+#define S5P_FIMV_D_MIN_CHROMA_DPB_SIZE		0xF0F8
+#define S5P_FIMV_D_MVC_NUM_VIEWS		0xF0FC
+#define S5P_FIMV_D_MIN_NUM_MV			0xF100
+#define S5P_FIMV_D_NUM_DPB			0xF130
+#define S5P_FIMV_D_LUMA_DPB_SIZE		0xF134
+#define S5P_FIMV_D_CHROMA_DPB_SIZE		0xF138
+#define S5P_FIMV_D_MV_BUFFER_SIZE		0xF13C
+
+#define S5P_FIMV_D_LUMA_DPB			0xF140
+#define S5P_FIMV_D_CHROMA_DPB			0xF240
+#define S5P_FIMV_D_MV_BUFFER			0xF340
+
+#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR		0xF440
+#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE		0xF444
+#define S5P_FIMV_D_METADATA_BUFFER_ADDR		0xF448
+#define S5P_FIMV_D_METADATA_BUFFER_SIZE		0xF44C
+#define S5P_FIMV_D_NUM_MV			0xF478
+#define S5P_FIMV_D_CPB_BUFFER_ADDR		0xF4B0
+#define S5P_FIMV_D_CPB_BUFFER_SIZE		0xF4B4
+
+#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER	0xF4B8
+#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER	0xF4BC
+#define S5P_FIMV_D_CPB_BUFFER_OFFSET		0xF4C0
+#define S5P_FIMV_D_SLICE_IF_ENABLE		0xF4C4
+#define S5P_FIMV_D_PICTURE_TAG			0xF4C8
+#define S5P_FIMV_D_STREAM_DATA_SIZE		0xF4D0
+
+/* Display information register */
+#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH		0xF500
+#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT		0xF504
+
+/* Display status */
+#define S5P_FIMV_D_DISPLAY_STATUS		0xF508
+#define S5P_FIMV_DEC_STATUS_DECODING_ONLY		0
+#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY		1
+#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY		2
+#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY		3
+#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK	7
+#define S5P_FIMV_DEC_STATUS_PROGRESSIVE			(0<<3)
+#define S5P_FIMV_DEC_STATUS_INTERLACE			(1<<3)
+#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK		(1<<3)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK		(3<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC		(1<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC		(2<<4)
+#define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT		4
+#define S5P_FIMV_DEC_STATUS_CRC_GENERATED		(1<<5)
+#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED		(0<<5)
+#define S5P_FIMV_DEC_STATUS_CRC_MASK			(1<<5)
+
+#define S5P_FIMV_D_DISPLAY_LUMA_ADDR		0xF50C
+#define S5P_FIMV_D_DISPLAY_CHROMA_ADDR		0xF510
+
+#define S5P_FIMV_D_DISPLAY_FRAME_TYPE		0xF514
+#define S5P_FIMV_DECODE_FRAME_SKIPPED		0
+#define S5P_FIMV_DECODE_FRAME_I_FRAME		1
+#define S5P_FIMV_DECODE_FRAME_P_FRAME		2
+#define S5P_FIMV_DECODE_FRAME_B_FRAME		3
+#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME	4
+#define S5P_FIMV_SHARED_CROP_INFO_H		0x0020
+#define S5P_FIMV_SHARED_CROP_LEFT_MASK		0xFFFF
+#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT		0
+#define S5P_FIMV_SHARED_CROP_RIGHT_MASK		0xFFFF0000
+#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT	16
+#define S5P_FIMV_SHARED_CROP_INFO_V		0x0024
+#define S5P_FIMV_SHARED_CROP_TOP_MASK		0xFFFF
+#define S5P_FIMV_SHARED_CROP_TOP_SHIFT		0
+#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK	0xFFFF0000
+#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT	16
+
+#define S5P_FIMV_D_DISPLAY_CROP_INFO1		0xF518
+#define S5P_FIMV_D_DISPLAY_CROP_INFO2		0xF51C
+#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE	0xF520
+#define S5P_FIMV_D_DISPLAY_LUMA_CRC_TOP		0xF524
+#define S5P_FIMV_D_DISPLAY_CHROMA_CRC_TOP	0xF528
+#define S5P_FIMV_D_DISPLAY_LUMA_CRC_BOT		0xF52C
+#define S5P_FIMV_D_DISPLAY_CHROMA_CRC_BOT	0xF530
+#define S5P_FIMV_D_DISPLAY_ASPECT_RATIO		0xF534
+#define S5P_FIMV_D_DISPLAY_EXTENDED_AR		0xF538
+
+/* Decoded picture information register */
+#define S5P_FIMV_D_DECODED_FRAME_WIDTH		0xF53C
+#define S5P_FIMV_D_DECODED_FRAME_HEIGHT		0xF540
+#define S5P_FIMV_D_DECODED_STATUS		0xF544
+#define S5P_FIMV_DEC_CRC_GEN_MASK		0x1
+#define S5P_FIMV_DEC_CRC_GEN_SHIFT		6
+
+#define S5P_FIMV_D_DECODED_LUMA_ADDR		0xF548
+#define S5P_FIMV_D_DECODED_CHROMA_ADDR		0xF54C
+
+#define S5P_FIMV_D_DECODED_FRAME_TYPE		0xF550
+#define S5P_FIMV_DECODE_FRAME_MASK		7
+
+#define S5P_FIMV_D_DECODED_CROP_INFO1		0xF554
+#define S5P_FIMV_D_DECODED_CROP_INFO2		0xF558
+#define S5P_FIMV_D_DECODED_PICTURE_PROFILE	0xF55C
+#define S5P_FIMV_D_DECODED_NAL_SIZE		0xF560
+#define S5P_FIMV_D_DECODED_LUMA_CRC_TOP		0xF564
+#define S5P_FIMV_D_DECODED_CHROMA_CRC_TOP	0xF568
+#define S5P_FIMV_D_DECODED_LUMA_CRC_BOT		0xF56C
+#define S5P_FIMV_D_DECODED_CHROMA_CRC_BOT	0xF570
+
+/* Returned value register for specific setting */
+#define S5P_FIMV_D_RET_PICTURE_TAG_TOP		0xF574
+#define S5P_FIMV_D_RET_PICTURE_TAG_BOT		0xF578
+#define S5P_FIMV_D_RET_PICTURE_TIME_TOP		0xF57C
+#define S5P_FIMV_D_RET_PICTURE_TIME_BOT		0xF580
+#define S5P_FIMV_D_CHROMA_FORMAT		0xF588
+#define S5P_FIMV_D_MPEG4_INFO			0xF58C
+#define S5P_FIMV_D_H264_INFO			0xF590
+
+#define S5P_FIMV_D_METADATA_ADDR_CONCEALED_MB	0xF594
+#define S5P_FIMV_D_METADATA_SIZE_CONCEALED_MB	0xF598
+#define S5P_FIMV_D_METADATA_ADDR_VC1_PARAM	0xF59C
+#define S5P_FIMV_D_METADATA_SIZE_VC1_PARAM	0xF5A0
+#define S5P_FIMV_D_METADATA_ADDR_SEI_NAL	0xF5A4
+#define S5P_FIMV_D_METADATA_SIZE_SEI_NAL	0xF5A8
+#define S5P_FIMV_D_METADATA_ADDR_VUI		0xF5AC
+#define S5P_FIMV_D_METADATA_SIZE_VUI		0xF5B0
+
+#define S5P_FIMV_D_MVC_VIEW_ID			0xF5B4
+#define S5P_FIMV_D_MVC_VIEW_ID_DISP_MASK	0xFFFF
+
+/* SEI related information */
+#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL		0xF5F0
+#define S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID	0xF5F4
+#define S5P_FIMV_D_FRAME_PACK_SEI_INFO		0xF5F8
+#define S5P_FIMV_D_FRAME_PACK_GRID_POS		0xF5FC
+
+/* Encoder Registers */
+#define S5P_FIMV_E_FRAME_WIDTH			0xF770
+#define S5P_FIMV_E_FRAME_HEIGHT			0xF774
+#define S5P_FIMV_E_CROPPED_FRAME_WIDTH		0xF778
+#define S5P_FIMV_E_CROPPED_FRAME_HEIGHT		0xF77C
+#define S5P_FIMV_E_FRAME_CROP_OFFSET		0xF780
+#define S5P_FIMV_E_ENC_OPTIONS			0xF784
+#define S5P_FIMV_E_PICTURE_PROFILE		0xF788
+#define S5P_FIMV_ENC_PROFILE_H264_BASELINE		0
+#define S5P_FIMV_ENC_PROFILE_H264_MAIN			1
+#define S5P_FIMV_ENC_PROFILE_H264_HIGH			2
+#define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE	3
+#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE		0
+#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE	1
+#define S5P_FIMV_E_FIXED_PICTURE_QP		0xF790
+
+#define S5P_FIMV_E_RC_CONFIG			0xF794
+#define S5P_FIMV_E_RC_QP_BOUND			0xF798
+#define S5P_FIMV_E_RC_RPARAM			0xF79C
+#define S5P_FIMV_E_MB_RC_CONFIG			0xF7A0
+#define S5P_FIMV_E_PADDING_CTRL			0xF7A4
+#define S5P_FIMV_E_MV_HOR_RANGE			0xF7AC
+#define S5P_FIMV_E_MV_VER_RANGE			0xF7B0
+
+#define S5P_FIMV_E_VBV_BUFFER_SIZE		0xF84C
+#define S5P_FIMV_E_VBV_INIT_DELAY		0xF850
+#define S5P_FIMV_E_NUM_DPB			0xF890
+#define S5P_FIMV_E_LUMA_DPB			0xF8C0
+#define S5P_FIMV_E_CHROMA_DPB			0xF904
+#define S5P_FIMV_E_ME_BUFFER			0xF948
+
+#define S5P_FIMV_E_SCRATCH_BUFFER_ADDR		0xF98C
+#define S5P_FIMV_E_SCRATCH_BUFFER_SIZE		0xF990
+#define S5P_FIMV_E_TMV_BUFFER0			0xF994
+#define S5P_FIMV_E_TMV_BUFFER1			0xF998
+#define S5P_FIMV_E_SOURCE_LUMA_ADDR		0xF9F0
+#define S5P_FIMV_E_SOURCE_CHROMA_ADDR		0xF9F4
+#define S5P_FIMV_E_STREAM_BUFFER_ADDR		0xF9F8
+#define S5P_FIMV_E_STREAM_BUFFER_SIZE		0xF9FC
+#define S5P_FIMV_E_ROI_BUFFER_ADDR		0xFA00
+
+#define S5P_FIMV_E_PARAM_CHANGE			0xFA04
+#define S5P_FIMV_E_IR_SIZE			0xFA08
+#define S5P_FIMV_E_GOP_CONFIG			0xFA0C
+#define S5P_FIMV_E_MSLICE_MODE			0xFA10
+#define S5P_FIMV_E_MSLICE_SIZE_MB		0xFA14
+#define S5P_FIMV_E_MSLICE_SIZE_BITS		0xFA18
+#define S5P_FIMV_E_FRAME_INSERTION		0xFA1C
+
+#define S5P_FIMV_E_RC_FRAME_RATE		0xFA20
+#define S5P_FIMV_E_RC_BIT_RATE			0xFA24
+#define S5P_FIMV_E_RC_QP_OFFSET			0xFA28
+#define S5P_FIMV_E_RC_ROI_CTRL			0xFA2C
+#define S5P_FIMV_E_PICTURE_TAG			0xFA30
+#define S5P_FIMV_E_BIT_COUNT_ENABLE		0xFA34
+#define S5P_FIMV_E_MAX_BIT_COUNT		0xFA38
+#define S5P_FIMV_E_MIN_BIT_COUNT		0xFA3C
+
+#define S5P_FIMV_E_METADATA_BUFFER_ADDR		0xFA40
+#define S5P_FIMV_E_METADATA_BUFFER_SIZE		0xFA44
+#define S5P_FIMV_E_STREAM_SIZE			0xFA80
+#define S5P_FIMV_E_SLICE_TYPE			0xFA84
+#define S5P_FIMV_E_PICTURE_COUNT		0xFA88
+#define S5P_FIMV_E_RET_PICTURE_TAG		0xFA8C
+#define S5P_FIMV_E_STREAM_BUFFER_WRITE_POINTER	0xFA90
+
+#define S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR	0xFA94
+#define S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR	0xFA98
+#define S5P_FIMV_E_RECON_LUMA_DPB_ADDR		0xFA9C
+#define S5P_FIMV_E_RECON_CHROMA_DPB_ADDR	0xFAA0
+#define S5P_FIMV_E_METADATA_ADDR_ENC_SLICE	0xFAA4
+#define S5P_FIMV_E_METADATA_SIZE_ENC_SLICE	0xFAA8
+
+#define S5P_FIMV_E_MPEG4_OPTIONS		0xFB10
+#define S5P_FIMV_E_MPEG4_HEC_PERIOD		0xFB14
+#define S5P_FIMV_E_ASPECT_RATIO			0xFB50
+#define S5P_FIMV_E_EXTENDED_SAR			0xFB54
+
+#define S5P_FIMV_E_H264_OPTIONS			0xFB58
+#define S5P_FIMV_E_H264_LF_ALPHA_OFFSET		0xFB5C
+#define S5P_FIMV_E_H264_LF_BETA_OFFSET		0xFB60
+#define S5P_FIMV_E_H264_I_PERIOD		0xFB64
+
+#define S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE			0xFB68
+#define S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1		0xFB6C
+#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR		0xFB70
+#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1	0xFB74
+#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0	0xFB78
+#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_1	0xFB7C
+#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_2	0xFB80
+#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_3	0xFB84
+
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_0	0xFB88
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_1	0xFB8C
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_2	0xFB90
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_3	0xFB94
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_4	0xFB98
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_5	0xFB9C
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_6	0xFBA0
+#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_7	0xFBA4
+
+#define S5P_FIMV_E_H264_CHROMA_QP_OFFSET	0xFBA8
+#define S5P_FIMV_E_H264_NUM_T_LAYER		0xFBAC
+
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0	0xFBB0
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER1	0xFBB4
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER2	0xFBB8
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER3	0xFBBC
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER4	0xFBC0
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER5	0xFBC4
+#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER6	0xFBC8
+
+#define S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO	0xFC4C
+
+#define S5P_FIMV_E_MVC_FRAME_QP_VIEW1		0xFD40
+#define S5P_FIMV_E_MVC_RC_FRAME_RATE_VIEW1	0xFD44
+#define S5P_FIMV_E_MVC_RC_BIT_RATE_VIEW1	0xFD48
+#define S5P_FIMV_E_MVC_RC_QBOUND_VIEW1		0xFD4C
+#define S5P_FIMV_E_MVC_RC_RPARA_VIEW1		0xFD50
+#define S5P_FIMV_E_MVC_INTER_VIEW_PREDICTION_ON	0xFD80
+
+/* Codec numbers  */
+#define MFC_FORMATS_NO_CODEC		-1
+
+#define S5P_FIMV_CODEC_H264_DEC		0
+#define S5P_FIMV_CODEC_H264_MVC_DEC	1
+
+#define S5P_FIMV_CODEC_MPEG4_DEC	3
+#define S5P_FIMV_CODEC_FIMV1_DEC	4
+#define S5P_FIMV_CODEC_FIMV2_DEC	5
+#define S5P_FIMV_CODEC_FIMV3_DEC	6
+#define S5P_FIMV_CODEC_FIMV4_DEC	7
+#define S5P_FIMV_CODEC_H263_DEC		8
+#define S5P_FIMV_CODEC_VC1RCV_DEC	9
+#define S5P_FIMV_CODEC_VC1_DEC		10
+/* FIXME: Add 11~12 */
+#define S5P_FIMV_CODEC_MPEG2_DEC	13
+#define S5P_FIMV_CODEC_VP8_DEC		14
+/* FIXME: Add 15~16 */
+#define S5P_FIMV_CODEC_H264_ENC		20
+#define S5P_FIMV_CODEC_H264_MVC_ENC	21
+
+#define S5P_FIMV_CODEC_MPEG4_ENC	23
+#define S5P_FIMV_CODEC_H263_ENC		24
+/* FIXME: Add 25 */
+
+/***	Definitions for MFCv5 compatibility ***/
+#define S5P_FIMV_SI_DISPLAY_Y_ADR		S5P_FIMV_D_DISPLAY_LUMA_ADDR
+#define S5P_FIMV_SI_DISPLAY_C_ADR		S5P_FIMV_D_DISPLAY_CHROMA_ADDR
+
+#define S5P_FIMV_CRC_LUMA0			S5P_FIMV_D_DECODED_LUMA_CRC_TOP
+#define S5P_FIMV_CRC_CHROMA0			S5P_FIMV_D_DECODED_CHROMA_CRC_TOP
+#define S5P_FIMV_CRC_LUMA1			S5P_FIMV_D_DECODED_LUMA_CRC_BOT
+#define S5P_FIMV_CRC_CHROMA1			S5P_FIMV_D_DECODED_CHROMA_CRC_BOT
+#define S5P_FIMV_CRC_DISP_LUMA0			S5P_FIMV_D_DISPLAY_LUMA_CRC_TOP
+#define S5P_FIMV_CRC_DISP_CHROMA0		S5P_FIMV_D_DISPLAY_CHROMA_CRC_TOP
+
+#define S5P_FIMV_SI_DECODED_STATUS		S5P_FIMV_D_DECODED_STATUS
+#define S5P_FIMV_SI_DISPLAY_STATUS		S5P_FIMV_D_DISPLAY_STATUS
+#define S5P_FIMV_SHARED_SET_FRAME_TAG		S5P_FIMV_D_PICTURE_TAG
+#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP	S5P_FIMV_D_RET_PICTURE_TAG_TOP
+#define S5P_FIMV_CRC_DISP_STATUS		S5P_FIMV_D_DISPLAY_STATUS
+
+/* SEI related information */
+#define S5P_FIMV_FRAME_PACK_SEI_AVAIL		S5P_FIMV_D_FRAME_PACK_SEI_AVAIL
+#define S5P_FIMV_FRAME_PACK_ARRGMENT_ID		S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID
+#define S5P_FIMV_FRAME_PACK_SEI_INFO		S5P_FIMV_D_FRAME_PACK_SEI_INFO
+#define S5P_FIMV_FRAME_PACK_GRID_POS		S5P_FIMV_D_FRAME_PACK_GRID_POS
+
+#define S5P_FIMV_SHARED_SET_E_FRAME_TAG		S5P_FIMV_E_PICTURE_TAG
+#define S5P_FIMV_SHARED_GET_E_FRAME_TAG		S5P_FIMV_E_RET_PICTURE_TAG
+#define S5P_FIMV_ENCODED_LUMA_ADDR		S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR
+#define S5P_FIMV_ENCODED_CHROMA_ADDR		S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR
+#define	S5P_FIMV_FRAME_INSERTION		S5P_FIMV_E_FRAME_INSERTION
+
+#define S5P_FIMV_PARAM_CHANGE_FLAG		S5P_FIMV_E_PARAM_CHANGE /* flag */
+#define S5P_FIMV_NEW_I_PERIOD			S5P_FIMV_E_GOP_CONFIG
+#define S5P_FIMV_NEW_RC_FRAME_RATE		S5P_FIMV_E_RC_FRAME_RATE
+#define S5P_FIMV_NEW_RC_BIT_RATE		S5P_FIMV_E_RC_BIT_RATE
+/*** End of MFCv5 compatibility definitions ***/
+
+/***      old definitions     ***/
+#if 1
+
+#define S5P_FIMV_SW_RESET		0x0000
+#define S5P_FIMV_RISC_HOST_INT		0x0008
+
+/* Command from HOST to RISC */
+#define S5P_FIMV_HOST2RISC_ARG1		0x0034
+#define S5P_FIMV_HOST2RISC_ARG2		0x0038
+#define S5P_FIMV_HOST2RISC_ARG3		0x003c
+#define S5P_FIMV_HOST2RISC_ARG4		0x0040
+
+/* Command from RISC to HOST */
+#define S5P_FIMV_RISC2HOST_CMD_MASK	0x1FFFF
+#define S5P_FIMV_RISC2HOST_ARG1		0x0048
+#define S5P_FIMV_RISC2HOST_ARG2		0x004c
+#define S5P_FIMV_RISC2HOST_ARG3		0x0050
+#define S5P_FIMV_RISC2HOST_ARG4		0x0054
+
+#define S5P_FIMV_SYS_MEM_SZ		0x005c
+#define S5P_FIMV_FW_STATUS		0x0080
+
+/* Memory controller register */
+#define S5P_FIMV_MC_DRAMBASE_ADR_A	0x0508
+#define S5P_FIMV_MC_DRAMBASE_ADR_B	0x050c
+#define S5P_FIMV_MC_STATUS		0x0510
+
+/* Common register */
+#define S5P_FIMV_COMMON_BASE_A		0x0600
+#define S5P_FIMV_COMMON_BASE_B		0x0700
+
+/* Decoder */
+#define S5P_FIMV_DEC_CHROMA_ADR		(S5P_FIMV_COMMON_BASE_A)
+#define S5P_FIMV_DEC_LUMA_ADR		(S5P_FIMV_COMMON_BASE_B)
+
+/* H.264 decoding */
+#define S5P_FIMV_H264_VERT_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)	/* vertical neighbor motion vector */
+#define S5P_FIMV_H264_NB_IP_ADR		(S5P_FIMV_COMMON_BASE_A + 0x90)	/* neighbor pixels for intra pred */
+#define S5P_FIMV_H264_MV_ADR		(S5P_FIMV_COMMON_BASE_B + 0x80)	/* H264 motion vector */
+
+/* MPEG4 decoding */
+#define S5P_FIMV_MPEG4_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)	/* neighbor AC/DC coeff. */
+#define S5P_FIMV_MPEG4_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)	/* upper neighbor motion vector */
+#define S5P_FIMV_MPEG4_SA_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x94)	/* subseq. anchor motion vector */
+#define S5P_FIMV_MPEG4_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)	/* overlap transform line */
+#define S5P_FIMV_MPEG4_SP_ADR		(S5P_FIMV_COMMON_BASE_A + 0xa8)	/* syntax parser */
+
+/* H.263 decoding */
+#define S5P_FIMV_H263_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)
+#define S5P_FIMV_H263_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)
+#define S5P_FIMV_H263_SA_MV_ADR		(S5P_FIMV_COMMON_BASE_A + 0x94)
+#define S5P_FIMV_H263_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)
+
+/* VC-1 decoding */
+#define S5P_FIMV_VC1_NB_DCAC_ADR	(S5P_FIMV_COMMON_BASE_A + 0x8c)
+#define S5P_FIMV_VC1_UP_NB_MV_ADR	(S5P_FIMV_COMMON_BASE_A + 0x90)
+#define S5P_FIMV_VC1_SA_MV_ADR		(S5P_FIMV_COMMON_BASE_A + 0x94)
+#define S5P_FIMV_VC1_OT_LINE_ADR	(S5P_FIMV_COMMON_BASE_A + 0x98)
+#define S5P_FIMV_VC1_BITPLANE3_ADR	(S5P_FIMV_COMMON_BASE_A + 0x9c)	/* bitplane3 */
+#define S5P_FIMV_VC1_BITPLANE2_ADR	(S5P_FIMV_COMMON_BASE_A + 0xa0)	/* bitplane2 */
+#define S5P_FIMV_VC1_BITPLANE1_ADR	(S5P_FIMV_COMMON_BASE_A + 0xa4)	/* bitplane1 */
+
+/* Encoder */
+#define S5P_FIMV_ENC_REF0_LUMA_ADR	(S5P_FIMV_COMMON_BASE_A + 0x1c)	/* reconstructed luma */
+#define S5P_FIMV_ENC_REF1_LUMA_ADR	(S5P_FIMV_COMMON_BASE_A + 0x20)
+#define S5P_FIMV_ENC_REF0_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B)	/* reconstructed chroma */
+#define S5P_FIMV_ENC_REF1_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x04)
+#define S5P_FIMV_ENC_REF2_LUMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x10)
+#define S5P_FIMV_ENC_REF2_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x08)
+#define S5P_FIMV_ENC_REF3_LUMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x14)
+#define S5P_FIMV_ENC_REF3_CHROMA_ADR	(S5P_FIMV_COMMON_BASE_B + 0x0c)
+
+/* H.264 encoding */
+#define S5P_FIMV_H264_UP_MV_ADR		(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_H264_NBOR_INFO_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* entropy engine's neighbor info. */
+#define S5P_FIMV_H264_UP_INTRA_MD_ADR	(S5P_FIMV_COMMON_BASE_A + 0x08)	/* upper intra MD */
+#define S5P_FIMV_H264_COZERO_FLAG_ADR	(S5P_FIMV_COMMON_BASE_A + 0x10)	/* direct cozero flag */
+#define S5P_FIMV_H264_UP_INTRA_PRED_ADR	(S5P_FIMV_COMMON_BASE_B + 0x40)	/* upper intra PRED */
+
+/* H.263 encoding */
+#define S5P_FIMV_H263_UP_MV_ADR		(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_H263_ACDC_COEF_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* upper Q coeff. */
+
+/* MPEG4 encoding */
+#define S5P_FIMV_MPEG4_UP_MV_ADR	(S5P_FIMV_COMMON_BASE_A)	/* upper motion vector */
+#define S5P_FIMV_MPEG4_ACDC_COEF_ADR	(S5P_FIMV_COMMON_BASE_A + 0x04)	/* upper Q coeff. */
+#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR	(S5P_FIMV_COMMON_BASE_A + 0x10)	/* direct cozero flag */
+
+#define S5P_FIMV_ENC_REF_B_LUMA_ADR     0x062c /* ref B Luma addr */
+#define S5P_FIMV_ENC_REF_B_CHROMA_ADR   0x0630 /* ref B Chroma addr */
+
+#define S5P_FIMV_ENC_CUR_LUMA_ADR	0x0718 /* current Luma addr */
+#define S5P_FIMV_ENC_CUR_CHROMA_ADR	0x071C /* current Chroma addr */
+
+/* Codec common register */
+#define S5P_FIMV_ENC_HSIZE_PX		0x0818 /* frame width at encoder */
+#define S5P_FIMV_ENC_VSIZE_PX		0x081c /* frame height at encoder */
+#define S5P_FIMV_ENC_PROFILE		0x0830 /* profile register */
+#define S5P_FIMV_ENC_PIC_STRUCT		0x083c /* picture field/frame flag */
+#define S5P_FIMV_ENC_LF_CTRL		0x0848 /* loop filter control */
+#define S5P_FIMV_ENC_ALPHA_OFF		0x084c /* loop filter alpha offset */
+#define S5P_FIMV_ENC_BETA_OFF		0x0850 /* loop filter beta offset */
+#define S5P_FIMV_MR_BUSIF_CTRL		0x0854 /* hidden, bus interface ctrl */
+#define S5P_FIMV_ENC_PXL_CACHE_CTRL	0x0a00 /* pixel cache control */
+
+/* Channel & stream interface register */
+#define S5P_FIMV_SI_RTN_CHID		0x2000 /* Return CH instance ID register */
+#define S5P_FIMV_SI_CH0_INST_ID		0x2040 /* codec instance ID */
+#define S5P_FIMV_SI_CH1_INST_ID		0x2080 /* codec instance ID */
+/* Decoder */
+#define S5P_FIMV_SI_VRESOL		0x2004 /* vertical resolution of decoder */
+#define S5P_FIMV_SI_HRESOL		0x2008 /* horizontal resolution of decoder */
+#define S5P_FIMV_SI_BUF_NUMBER		0x200c /* number of frames in the decoded pic */
+#define S5P_FIMV_SI_CONSUMED_BYTES	0x2018 /* Consumed number of bytes to decode
+								a frame */
+#define S5P_FIMV_SI_FRAME_TYPE		0x2020 /* frame type such as skip/I/P/B */
+
+#define S5P_FIMV_SI_CH0_SB_ST_ADR	0x2044 /* start addr of stream buf */
+#define S5P_FIMV_SI_CH0_SB_FRM_SIZE	0x2048 /* size of stream buf */
+#define S5P_FIMV_SI_CH0_DESC_ADR	0x204c /* addr of descriptor buf */
+#define S5P_FIMV_SI_CH0_CPB_SIZE	0x2058 /* max size of coded pic. buf */
+#define S5P_FIMV_SI_CH0_DESC_SIZE	0x205c /* max size of descriptor buf */
+
+#define S5P_FIMV_SI_CH1_SB_ST_ADR	0x2084 /* start addr of stream buf */
+#define S5P_FIMV_SI_CH1_SB_FRM_SIZE	0x2088 /* size of stream buf */
+#define S5P_FIMV_SI_CH1_DESC_ADR	0x208c /* addr of descriptor buf */
+#define S5P_FIMV_SI_CH1_CPB_SIZE	0x2098 /* max size of coded pic. buf */
+#define S5P_FIMV_SI_CH1_DESC_SIZE	0x209c /* max size of descriptor buf */
+
+#define S5P_FIMV_SI_FIMV1_HRESOL	0x2054 /* horizontal resolution */
+#define S5P_FIMV_SI_FIMV1_VRESOL	0x2050 /* vertical resolution */
+
+/* Decode frame address */
+#define S5P_FIMV_DECODE_Y_ADR			0x2024
+#define S5P_FIMV_DECODE_C_ADR			0x2028
+
+/* Decoded frame type */
+#define S5P_FIMV_DECODE_FRAME_TYPE		0x2020
+
+/* Sizes of buffers required for decoding */
+#define S5P_FIMV_DEC_NB_IP_SIZE			(32 * 1024)
+#define S5P_FIMV_DEC_VERT_NB_MV_SIZE		(16 * 1024)
+#define S5P_FIMV_DEC_NB_DCAC_SIZE		(16 * 1024)
+#define S5P_FIMV_DEC_UPNB_MV_SIZE		(68 * 1024)
+#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE		(136 * 1024)
+#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE     (32 * 1024)
+#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE		(2 * 1024)
+#define S5P_FIMV_DEC_STX_PARSER_SIZE		(68 * 1024)
+
+/* FIXME: Should be checked for alignment */
+#define S5P_FIMV_DEC_BUF_ALIGN			(8 * 1024)
+#define S5P_FIMV_ENC_BUF_ALIGN			(8 * 1024)
+#define S5P_FIMV_NV12M_HALIGN			16
+#define S5P_FIMV_NV12M_LVALIGN			16
+#define S5P_FIMV_NV12M_CVALIGN			8
+#define S5P_FIMV_NV12MT_HALIGN			16
+#define S5P_FIMV_NV12MT_VALIGN			16
+#define S5P_FIMV_NV12M_SALIGN			2048
+#define S5P_FIMV_NV12MT_SALIGN			8192
+
+/* Sizes of buffers required for encoding */
+#define S5P_FIMV_ENC_UPMV_SIZE			(0x10000)
+#define S5P_FIMV_ENC_COLFLG_SIZE		(0x10000)
+#define S5P_FIMV_ENC_INTRAMD_SIZE		(0x10000)
+#define S5P_FIMV_ENC_INTRAPRED_SIZE		(0x4000)
+#define S5P_FIMV_ENC_NBORINFO_SIZE		(0x10000)
+#define S5P_FIMV_ENC_ACDCCOEF_SIZE		(0x10000)
+
+/* Encoder */
+#define S5P_FIMV_ENC_SI_STRM_SIZE	0x2004 /* stream size */
+#define S5P_FIMV_ENC_SI_PIC_CNT		0x2008 /* picture count */
+#define S5P_FIMV_ENC_SI_WRITE_PTR	0x200c /* write pointer */
+#define S5P_FIMV_ENC_SI_SLICE_TYPE	0x2010 /* slice type(I/P/B/IDR) */
+#define S5P_FIMV_ENCODED_Y_ADDR         0x2014 /* the addr of the encoded luma pic */
+#define S5P_FIMV_ENCODED_C_ADDR         0x2018 /* the addr of the encoded chroma pic */
+
+#define S5P_FIMV_ENC_SI_CH0_SB_ADR	0x2044 /* addr of stream buf */
+#define S5P_FIMV_ENC_SI_CH0_SB_SIZE	0x204c /* size of stream buf */
+#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR	0x2050 /* current Luma addr */
+#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR	0x2054 /* current Chroma addr */
+#define S5P_FIMV_ENC_SI_CH0_FRAME_INS	0x2058 /* frame insertion */
+
+#define S5P_FIMV_ENC_SI_CH1_SB_ADR	0x2084 /* addr of stream buf */
+#define S5P_FIMV_ENC_SI_CH1_SB_SIZE	0x208c /* size of stream buf */
+#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR	0x2090 /* current Luma addr */
+#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR	0x2094 /* current Chroma addr */
+#define S5P_FIMV_ENC_SI_CH1_FRAME_INS	0x2098 /* frame insertion */
+
+#define S5P_FIMV_ENC_PIC_TYPE_CTRL	0xc504 /* pic type level control */
+#define S5P_FIMV_ENC_B_RECON_WRITE_ON	0xc508 /* B frame recon write ctrl */
+#define S5P_FIMV_ENC_MSLICE_CTRL	0xc50c /* multi slice control */
+#define S5P_FIMV_ENC_MSLICE_MB		0xc510 /* MB number in the one slice */
+#define S5P_FIMV_ENC_MSLICE_BIT		0xc514 /* bit count for one slice */
+#define S5P_FIMV_ENC_CIR_CTRL		0xc518 /* number of intra refresh MB */
+#define S5P_FIMV_ENC_MAP_FOR_CUR	0xc51c /* linear or 64x32 tiled mode */
+#define S5P_FIMV_ENC_PADDING_CTRL	0xc520 /* padding control */
+
+#define S5P_FIMV_ENC_RC_CONFIG		0xc5a0 /* RC config */
+#define S5P_FIMV_ENC_RC_BIT_RATE	0xc5a8 /* bit rate */
+#define S5P_FIMV_ENC_RC_QBOUND		0xc5ac /* max/min QP */
+#define S5P_FIMV_ENC_RC_RPARA		0xc5b0 /* rate control reaction coeff */
+#define S5P_FIMV_ENC_RC_MB_CTRL		0xc5b4 /* MB adaptive scaling */
+
+/* Encoder for H264 only */
+#define S5P_FIMV_ENC_H264_ENTRP_MODE	0xd004 /* CAVLC or CABAC */
+#define S5P_FIMV_ENC_H264_ALPHA_OFF	0xd008 /* loop filter alpha offset */
+#define S5P_FIMV_ENC_H264_BETA_OFF	0xd00c /* loop filter beta offset */
+#define S5P_FIMV_ENC_H264_NUM_OF_REF	0xd010 /* number of reference for P/B */
+#define S5P_FIMV_ENC_H264_TRANS_FLAG	0xd034 /* 8x8 transform flag in PPS & high profile */
+
+#define S5P_FIMV_ENC_RC_FRAME_RATE	0xd0d0 /* frame rate */
+
+/* Encoder for MPEG4 only */
+#define S5P_FIMV_ENC_MPEG4_QUART_PXL	0xe008 /* qpel interpolation ctrl */
+
+/* Additional */
+#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL   0x2068 /* DPB Config Control Register */
+#define S5P_FIMV_DPB_COUNT_MASK		0xffff
+
+#define S5P_FIMV_SI_CH0_RELEASE_BUF     0x2060 /* DPB release buffer register */
+#define S5P_FIMV_SI_CH0_HOST_WR_ADR	0x2064 /* address of shared memory */
+
+/* Channel Control Register */
+#define S5P_FIMV_CH_FRAME_START_REALLOC	5
+
+#define S5P_FIMV_CH_MASK		7
+#define S5P_FIMV_CH_SHIFT		16
+
+/* Host to RISC command */
+#define S5P_FIMV_R2H_CMD_RSV_RET		3
+#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET	7
+#define S5P_FIMV_R2H_CMD_FLUSH_RET		12
+#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET		16
+
+/* Shared memory registers' offsets */
+
+/* An offset of the start position in the stream when
+ * the start position is not aligned */
+#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT	0x000C
+#define S5P_FIMV_SHARED_START_BYTE_NUM		0x0018
+#define S5P_FIMV_SHARED_RC_VOP_TIMING		0x0030
+#define S5P_FIMV_SHARED_LUMA_DPB_SIZE		0x0064
+#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE		0x0068
+#define S5P_FIMV_SHARED_MV_SIZE			0x006C
+#define S5P_FIMV_SHARED_PIC_TIME_TOP		0x0010
+#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM		0x0014
+#define S5P_FIMV_SHARED_EXT_ENC_CONTROL		0x0028
+#define S5P_FIMV_SHARED_P_B_FRAME_QP		0x0070
+#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC	0x0074
+#define S5P_FIMV_SHARED_EXTENDED_SAR		0x0078
+#define S5P_FIMV_SHARED_H264_I_PERIOD		0x009C
+#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG	0x00A0
+
+#endif /* End of old definitions */
+
+#endif /* _REGS_FIMV_V6_H */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc.c b/drivers/media/video/s5p-mfc/s5p_mfc.c
new file mode 100644
index 0000000..3336491
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc.c
@@ -0,0 +1,1651 @@
+/*
+ * Samsung S5P Multi Format Codec v 5.1
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Kamil Debski, <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define DEBUG
+
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/proc_fs.h>
+#include <mach/videonode.h>
+#include <plat/cpu.h>
+#include <media/videobuf2-core.h>
+
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+#include <mach/dev.h>
+#endif
+#endif
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_ctrl.h"
+#include "s5p_mfc_dec.h"
+#include "s5p_mfc_enc.h"
+#include "s5p_mfc_pm.h"
+
+#define S5P_MFC_NAME		"s5p-mfc"
+#define S5P_MFC_DEC_NAME	"s5p-mfc-dec"
+#define S5P_MFC_ENC_NAME	"s5p-mfc-enc"
+
+int debug;
+module_param(debug, int, S_IRUGO | S_IWUSR);
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+static struct proc_dir_entry *mfc_proc_entry;
+
+#define MFC_PROC_ROOT			"mfc"
+#define MFC_PROC_INSTANCE_NUMBER	"instance_number"
+#define MFC_PROC_DRM_INSTANCE_NUMBER	"drm_instance_number"
+#define MFC_PROC_FW_STATUS		"fw_status"
+
+#define MFC_DRM_MAGIC_SIZE	0x10
+#define MFC_DRM_MAGIC_CHUNK0	0x13cdbf16
+#define MFC_DRM_MAGIC_CHUNK1	0x8b803342
+#define MFC_DRM_MAGIC_CHUNK2	0x5e87f4f5
+#define MFC_DRM_MAGIC_CHUNK3	0x3bd05317
+
+static bool check_magic(unsigned char *addr)
+{
+	if (((u32)*(u32 *)(addr      ) == MFC_DRM_MAGIC_CHUNK0) &&
+	    ((u32)*(u32 *)(addr + 0x4) == MFC_DRM_MAGIC_CHUNK1) &&
+	    ((u32)*(u32 *)(addr + 0x8) == MFC_DRM_MAGIC_CHUNK2) &&
+	    ((u32)*(u32 *)(addr + 0xC) == MFC_DRM_MAGIC_CHUNK3))
+		return true;
+	else
+		return false;
+}
+
+static inline void clear_magic(unsigned char *addr)
+{
+	memset((void *)addr, 0x00, MFC_DRM_MAGIC_SIZE);
+}
+#endif
+
+void mfc_workqueue_try_run(struct work_struct *work)
+{
+	struct s5p_mfc_dev *dev = container_of(work, struct s5p_mfc_dev,
+						work_struct);
+
+	s5p_mfc_try_run(dev);
+}
+
+/* Helper functions for interrupt processing */
+/* Remove from hw execution round robin */
+inline void clear_work_bit(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	spin_lock(&dev->condlock);
+	clear_bit(ctx->num, &dev->ctx_work_bits);
+	spin_unlock(&dev->condlock);
+}
+
+/* Wake up context wait_queue */
+static inline void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
+			       unsigned int err)
+{
+	ctx->int_cond = 1;
+	ctx->int_type = reason;
+	ctx->int_err = err;
+	if (ctx->state != MFCINST_ABORT)
+		wake_up_interruptible(&ctx->queue);
+	else
+		wake_up(&ctx->queue);
+}
+
+/* Wake up device wait_queue */
+static inline void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
+			       unsigned int err)
+{
+	dev->int_cond = 1;
+	dev->int_type = reason;
+	dev->int_err = err;
+	wake_up_interruptible(&dev->queue);
+}
+
+void s5p_mfc_watchdog(unsigned long arg)
+{
+	struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
+
+	if (test_bit(0, &dev->hw_lock))
+		atomic_inc(&dev->watchdog_cnt);
+	if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
+		/* This means that hw is busy and no interrupts were
+		 * generated by hw for the Nth time of running this
+		 * watchdog timer. This usually means a serious hw
+		 * error. Now it is time to kill all instances and
+		 * reset the MFC. */
+		mfc_err("Time out during waiting for HW.\n");
+		queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
+	}
+	dev->watchdog_timer.expires = jiffies +
+					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
+	add_timer(&dev->watchdog_timer);
+}
+
+static void s5p_mfc_watchdog_worker(struct work_struct *work)
+{
+	struct s5p_mfc_dev *dev;
+	struct s5p_mfc_ctx *ctx;
+	int i, ret;
+	int mutex_locked;
+	unsigned long flags;
+
+	dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
+
+	mfc_err("Driver timeout error handling.\n");
+	/* Lock the mutex that protects open and release.
+	 * This is necessary as they may load and unload firmware. */
+	mutex_locked = mutex_trylock(&dev->mfc_mutex);
+	if (!mutex_locked)
+		mfc_err("This is not good. Some instance may be "
+							"closing/opening.\n");
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	/* FIXME: */
+	s5p_mfc_clock_off();
+
+	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
+		ctx = dev->ctx[i];
+		if (ctx) {
+			ctx->state = MFCINST_ERROR;
+			s5p_mfc_cleanup_queue(&ctx->dst_queue,
+				&ctx->vq_dst);
+			s5p_mfc_cleanup_queue(&ctx->src_queue,
+				&ctx->vq_src);
+			clear_work_bit(ctx);
+			wake_up_ctx(ctx, S5P_FIMV_R2H_CMD_ERR_RET, 0);
+		}
+	}
+	clear_bit(0, &dev->hw_lock);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+	/* Double check if there is at least one instance running.
+	 * If no instance is in memory than no firmware should be present */
+	if (dev->num_inst > 0) {
+		ret = s5p_mfc_load_firmware(dev);
+		if (ret != 0) {
+			mfc_err("Failed to reload FW.\n");
+			if (mutex_locked)
+				mutex_unlock(&dev->mfc_mutex);
+			return;
+		}
+
+		ret = s5p_mfc_init_hw(dev);
+		if (ret != 0) {
+			mfc_err("Failed to reinit FW.\n");
+			if (mutex_locked)
+				mutex_unlock(&dev->mfc_mutex);
+			return;
+		}
+	}
+	if (mutex_locked)
+		mutex_unlock(&dev->mfc_mutex);
+}
+
+static inline enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
+{
+	struct video_device *vdev = video_devdata(file);
+
+	if (!vdev) {
+		mfc_err("failed to get video_device");
+		return MFCNODE_INVALID;
+	}
+
+	mfc_debug(2, "video_device index: %d\n", vdev->index);
+
+	if (vdev->index == 0)
+		return MFCNODE_DECODER;
+	else if (vdev->index == 1)
+		return MFCNODE_ENCODER;
+	else
+		return MFCNODE_INVALID;
+}
+
+static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_buf *dst_buf;
+	int index;
+
+	ctx->state = MFCINST_FINISHED;
+	mfc_debug(2, "Decided to finish\n");
+	ctx->sequence++;
+	while (!list_empty(&ctx->dst_queue)) {
+		dst_buf = list_entry(ctx->dst_queue.next,
+				     struct s5p_mfc_buf, list);
+		mfc_debug(2, "Cleaning up buffer: %d\n",
+					  dst_buf->vb.v4l2_buf.index);
+		vb2_set_plane_payload(&dst_buf->vb, 0, 0);
+		vb2_set_plane_payload(&dst_buf->vb, 1, 0);
+		list_del(&dst_buf->list);
+		ctx->dst_queue_cnt--;
+		dst_buf->vb.v4l2_buf.sequence = (ctx->sequence++);
+
+		if (s5p_mfc_read_info(ctx, PIC_TIME_TOP) ==
+			s5p_mfc_read_info(ctx, PIC_TIME_BOT))
+			dst_buf->vb.v4l2_buf.field = V4L2_FIELD_NONE;
+		else
+			dst_buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED;
+
+		clear_bit(dst_buf->vb.v4l2_buf.index, &dec->dpb_status);
+
+		vb2_buffer_done(&dst_buf->vb, VB2_BUF_STATE_DONE);
+		index = dst_buf->vb.v4l2_buf.index;
+		if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in get_buf_ctrls_val\n");
+
+		mfc_debug(2, "Cleaned up buffer: %d\n",
+			  dst_buf->vb.v4l2_buf.index);
+	}
+	ctx->state = MFCINST_RUNNING;
+	mfc_debug(2, "After cleanup\n");
+}
+
+static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
+{
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *dst_buf;
+	size_t dspl_y_addr = MFC_GET_ADR(DEC_DISPLAY_Y);
+	unsigned int index;
+	unsigned int frame_type = s5p_mfc_get_disp_frame_type();
+	unsigned int mvc_view_id = s5p_mfc_get_mvc_disp_view_id();
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) {
+		if (mvc_view_id == 0)
+			ctx->sequence++;
+	} else {
+		ctx->sequence++;
+	}
+	/* If frame is same as previous then skip and do not dequeue */
+	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
+		return;
+	/* The MFC returns address of the buffer, now we have to
+	 * check which videobuf does it correspond to */
+	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
+		mfc_debug(2, "Listing: %d\n", dst_buf->vb.v4l2_buf.index);
+		/* Check if this is the buffer we're looking for */
+		mfc_debug(2, "0x%08lx, 0x%08x", mfc_plane_cookie(&dst_buf->vb, 0),
+			dspl_y_addr);
+		if (mfc_plane_cookie(&dst_buf->vb, 0) == dspl_y_addr) {
+			list_del(&dst_buf->list);
+			ctx->dst_queue_cnt--;
+			dst_buf->vb.v4l2_buf.sequence = ctx->sequence;
+
+			if (s5p_mfc_read_info(ctx, PIC_TIME_TOP) ==
+				s5p_mfc_read_info(ctx, PIC_TIME_BOT))
+				dst_buf->vb.v4l2_buf.field = V4L2_FIELD_NONE;
+			else
+				dst_buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED;
+
+			vb2_set_plane_payload(&dst_buf->vb, 0, ctx->luma_size);
+			vb2_set_plane_payload(&dst_buf->vb, 1, ctx->chroma_size);
+			clear_bit(dst_buf->vb.v4l2_buf.index, &dec->dpb_status);
+
+			dst_buf->vb.v4l2_buf.flags &=
+					~(V4L2_BUF_FLAG_KEYFRAME |
+					V4L2_BUF_FLAG_PFRAME |
+					V4L2_BUF_FLAG_BFRAME);
+
+			switch (frame_type) {
+			case S5P_FIMV_DECODE_FRAME_I_FRAME:
+				dst_buf->vb.v4l2_buf.flags |=
+					V4L2_BUF_FLAG_KEYFRAME;
+				break;
+			case S5P_FIMV_DECODE_FRAME_P_FRAME:
+				dst_buf->vb.v4l2_buf.flags |=
+					V4L2_BUF_FLAG_PFRAME;
+				break;
+			case S5P_FIMV_DECODE_FRAME_B_FRAME:
+				dst_buf->vb.v4l2_buf.flags |=
+					V4L2_BUF_FLAG_BFRAME;
+				break;
+			default:
+				break;
+			}
+
+			vb2_buffer_done(&dst_buf->vb,
+				s5p_mfc_err_dspl(err) ?
+					VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
+
+			index = dst_buf->vb.v4l2_buf.index;
+			if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->dst_ctrls[index]) < 0)
+				mfc_err("failed in get_buf_ctrls_val\n");
+
+			break;
+		}
+	}
+}
+
+static int s5p_mfc_find_start_code(unsigned char *src_mem, unsigned int remainSize)
+{
+	unsigned int index = 0;
+
+	for (index = 0; index < remainSize - 3; index++) {
+		if ((src_mem[index] == 0x00) && (src_mem[index+1] == 0x00) &&
+				(src_mem[index+2] == 0x01))
+			return index;
+	}
+
+	return -1;
+}
+
+static void s5p_mfc_handle_frame_error(struct s5p_mfc_ctx *ctx,
+		unsigned int reason, unsigned int err)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_buf *src_buf;
+	unsigned long flags;
+	unsigned int index;
+
+	mfc_err("Interrupt Error: %d\n", err);
+
+	dec->dpb_flush = 0;
+	dec->remained = 0;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+	if (!list_empty(&ctx->src_queue)) {
+		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+		index = src_buf->vb.v4l2_buf.index;
+		if (call_cop(ctx, recover_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in recover_buf_ctrls_val\n");
+
+		mfc_debug(2, "MFC needs next buffer.\n");
+		dec->consumed = 0;
+		list_del(&src_buf->list);
+		ctx->src_queue_cnt--;
+
+		vb2_buffer_done(&src_buf->vb, VB2_BUF_STATE_ERROR);
+
+		if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in get_buf_ctrls_val\n");
+	}
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	mfc_debug(2, "Assesing whether this context should be run again.\n");
+	/* This context state is always RUNNING */
+	if (ctx->src_queue_cnt == 0 || ctx->dst_queue_cnt < ctx->dpb_count) {
+		mfc_err("No need to run again.\n");
+		clear_work_bit(ctx);
+	}
+	mfc_debug(2, "After assesing whether this context should be run again. %d\n", ctx->src_queue_cnt);
+
+	s5p_mfc_clear_int_flags();
+	wake_up_ctx(ctx, reason, err);
+	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+		BUG();
+
+	s5p_mfc_clock_off();
+
+	queue_work(dev->irq_workqueue, &dev->work_struct);
+}
+
+/* Handle frame decoding interrupt */
+static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
+					unsigned int reason, unsigned int err)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned int dst_frame_status;
+	struct s5p_mfc_buf *src_buf;
+	unsigned long flags;
+	unsigned int res_change;
+	unsigned int index, remained;
+
+	dst_frame_status = s5p_mfc_get_dspl_status()
+				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
+	res_change = (s5p_mfc_get_dspl_status()
+				& S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
+				>> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
+	mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
+	mfc_debug(2, "frame packing sei available status: %x\n", s5p_mfc_get_sei_avail_status());
+
+	if (ctx->state == MFCINST_RES_CHANGE_INIT)
+		ctx->state = MFCINST_RES_CHANGE_FLUSH;
+
+	if (res_change && res_change != 3) {
+		mfc_err("Resolution change set to %d\n", res_change);
+		ctx->state = MFCINST_RES_CHANGE_INIT;
+
+		s5p_mfc_clear_int_flags();
+		wake_up_ctx(ctx, reason, err);
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+			BUG();
+
+		s5p_mfc_clock_off();
+
+		queue_work(dev->irq_workqueue, &dev->work_struct);
+		return;
+	}
+	if (dec->dpb_flush)
+		dec->dpb_flush = 0;
+	if (dec->remained)
+		dec->remained = 0;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+	/* All frames remaining in the buffer have been extracted  */
+	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
+		if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
+			mfc_debug(2, "Last frame received after resolution change.\n");
+			s5p_mfc_handle_frame_all_extracted(ctx);
+			ctx->state = MFCINST_RES_CHANGE_END;
+			goto leave_handle_frame;
+		} else {
+			s5p_mfc_handle_frame_all_extracted(ctx);
+		}
+	}
+
+	/* A frame has been decoded and is in the buffer  */
+	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
+	    dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
+		s5p_mfc_handle_frame_new(ctx, err);
+	} else {
+		mfc_debug(2, "No frame decode.\n");
+	}
+	/* Mark source buffer as complete */
+	if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
+		&& !list_empty(&ctx->src_queue)) {
+		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
+								list);
+		mfc_debug(2, "Packed PB test. Size:%d, prev offset: %ld, this run:"
+			" %d\n", src_buf->vb.v4l2_planes[0].bytesused,
+			dec->consumed, s5p_mfc_get_consumed_stream());
+		dec->consumed += s5p_mfc_get_consumed_stream();
+		remained = src_buf->vb.v4l2_planes[0].bytesused - dec->consumed;
+
+		if (dec->is_packedpb && remained > STUFF_BYTE &&
+			s5p_mfc_get_dec_frame_type() == S5P_FIMV_DECODE_FRAME_P_FRAME) {
+			unsigned char *stream_vir;
+			int offset = 0;
+
+			/* Run MFC again on the same buffer */
+			mfc_debug(2, "Running again the same buffer.\n");
+
+			stream_vir = vb2_plane_vaddr(&src_buf->vb, 0);
+			s5p_mfc_cache_inv(&src_buf->vb, 0);
+
+			offset = s5p_mfc_find_start_code(
+					stream_vir + dec->consumed, remained);
+
+			if (offset > STUFF_BYTE)
+				dec->consumed += offset;
+
+			s5p_mfc_set_dec_stream_buffer(ctx,
+				src_buf->cookie.stream, dec->consumed,
+				src_buf->vb.v4l2_planes[0].bytesused -
+							dec->consumed);
+			dev->curr_ctx = ctx->num;
+			s5p_mfc_clean_ctx_int_flags(ctx);
+			spin_unlock_irqrestore(&dev->irqlock, flags);
+			s5p_mfc_clear_int_flags();
+			wake_up_ctx(ctx, reason, err);
+			s5p_mfc_decode_one_frame(ctx, 0);
+			return;
+		} else {
+			index = src_buf->vb.v4l2_buf.index;
+			if (call_cop(ctx, recover_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+				mfc_err("failed in recover_buf_ctrls_val\n");
+
+			mfc_debug(2, "MFC needs next buffer.\n");
+			dec->consumed = 0;
+			list_del(&src_buf->list);
+			ctx->src_queue_cnt--;
+
+			vb2_buffer_done(&src_buf->vb, VB2_BUF_STATE_DONE);
+
+			if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+				mfc_err("failed in get_buf_ctrls_val\n");
+		}
+	}
+leave_handle_frame:
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+	mfc_debug(2, "Assesing whether this context should be run again.\n");
+	/* if (!s5p_mfc_ctx_ready(ctx)) { */
+	if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
+				    || ctx->dst_queue_cnt < ctx->dpb_count) {
+		mfc_debug(2, "No need to run again.\n");
+		clear_work_bit(ctx);
+	}
+	mfc_debug(2, "After assesing whether this context should be run again.\n");
+	s5p_mfc_clear_int_flags();
+	wake_up_ctx(ctx, reason, err);
+	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+		BUG();
+
+	s5p_mfc_clock_off();
+
+	queue_work(dev->irq_workqueue, &dev->work_struct);
+}
+
+/* Error handling for interrupt */
+static inline void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
+	unsigned int reason, unsigned int err)
+{
+	/* FIXME: */
+	struct s5p_mfc_dev *dev;
+	unsigned long flags;
+
+	/* FIXME: */
+	/* If no context is available then all necessary
+	 * processing has been done. */
+	if (ctx == 0)
+		return;
+
+	dev = ctx->dev;
+	/* FIXME: */
+	mfc_err("Interrupt Error: %08x\n", err);
+	s5p_mfc_clear_int_flags();
+	wake_up_dev(dev, reason, err);
+
+	/* Error recovery is dependent on the state of context */
+	switch (ctx->state) {
+	case MFCINST_INIT:
+		/* This error had to happen while acquireing instance */
+	case MFCINST_GOT_INST:
+		/* This error had to happen while parsing the header */
+	case MFCINST_HEAD_PARSED:
+		/* This error had to happen while setting dst buffers */
+	case MFCINST_RETURN_INST:
+		/* This error had to happen while releasing instance */
+		clear_work_bit(ctx);
+		wake_up_ctx(ctx, reason, err);
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+			BUG();
+
+		s5p_mfc_clock_off();
+
+		break;
+	case MFCINST_FINISHING:
+	case MFCINST_FINISHED:
+		/* It is higly probable that an error occured
+		 * while decoding a frame */
+		clear_work_bit(ctx);
+		ctx->state = MFCINST_ERROR;
+		/* Mark all dst buffers as having an error */
+		spin_lock_irqsave(&dev->irqlock, flags);
+		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
+		/* Mark all src buffers as having an error */
+		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+			BUG();
+
+		s5p_mfc_clock_off();
+
+		break;
+	default:
+		mfc_err("Encountered an error interrupt which had not been handled.\n");
+		break;
+	}
+	return;
+}
+
+/* Interrupt processing */
+static irqreturn_t s5p_mfc_irq(int irq, void *priv)
+{
+	struct s5p_mfc_dev *dev = priv;
+	struct s5p_mfc_buf *src_buf;
+	struct s5p_mfc_ctx *ctx;
+	struct s5p_mfc_dec *dec = NULL;
+	unsigned int reason;
+	unsigned int err;
+	unsigned long flags;
+
+	mfc_debug_enter();
+	/* Reset the timeout watchdog */
+	atomic_set(&dev->watchdog_cnt, 0);
+	ctx = dev->ctx[dev->curr_ctx];
+	if (ctx->type == MFCINST_DECODER)
+		dec = ctx->dec_priv;
+
+	/* Get the reason of interrupt and the error code */
+	reason = s5p_mfc_get_int_reason();
+	err = s5p_mfc_get_int_err();
+	mfc_debug(2, "Int reason: %d (err: %d)\n", reason, err);
+	switch (reason) {
+	case S5P_FIMV_R2H_CMD_ERR_RET:
+		/* An error has occured */
+		if (ctx->state == MFCINST_RUNNING) {
+			if (s5p_mfc_err_dec(err) >= S5P_FIMV_ERR_WARNINGS_START)
+				s5p_mfc_handle_frame(ctx, reason, err);
+			else
+				s5p_mfc_handle_frame_error(ctx, reason, err);
+		} else {
+			s5p_mfc_handle_error(ctx, reason, err);
+		}
+		break;
+	case S5P_FIMV_R2H_CMD_SLICE_DONE_RET:
+	case S5P_FIMV_R2H_CMD_FIELD_DONE_RET:
+	case S5P_FIMV_R2H_CMD_FRAME_DONE_RET:
+		if (ctx->c_ops->post_frame_start) {
+			if (ctx->c_ops->post_frame_start(ctx))
+				mfc_err("post_frame_start() failed\n");
+
+			s5p_mfc_clear_int_flags();
+			wake_up_ctx(ctx, reason, err);
+			if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+				BUG();
+
+			s5p_mfc_clock_off();
+
+			queue_work(dev->irq_workqueue, &dev->work_struct);
+		} else {
+			s5p_mfc_handle_frame(ctx, reason, err);
+		}
+		break;
+	case S5P_FIMV_R2H_CMD_SEQ_DONE_RET:
+		if (ctx->type == MFCINST_ENCODER) {
+			if (ctx->c_ops->post_seq_start(ctx))
+				mfc_err("post_seq_start() failed\n");
+		} else if (ctx->type == MFCINST_DECODER) {
+			if (ctx->src_fmt->fourcc != V4L2_PIX_FMT_FIMV1) {
+				ctx->img_width = s5p_mfc_get_img_width();
+				ctx->img_height = s5p_mfc_get_img_height();
+			}
+
+			s5p_mfc_dec_calc_dpb_size(ctx);
+
+			ctx->dpb_count = s5p_mfc_get_dpb_count();
+			if (dev->fw.date >= 0x120206)
+				dec->mv_count = s5p_mfc_get_mv_count();
+			if (ctx->img_width == 0 || ctx->img_height == 0)
+				ctx->state = MFCINST_ERROR;
+			else
+				ctx->state = MFCINST_HEAD_PARSED;
+
+			if ((ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
+				ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) &&
+					!list_empty(&ctx->src_queue)) {
+				struct s5p_mfc_buf *src_buf;
+				src_buf = list_entry(ctx->src_queue.next,
+						struct s5p_mfc_buf, list);
+				mfc_debug(2, "Check consumed size of header. ");
+				mfc_debug(2, "source : %d, consumed : %d\n",
+						s5p_mfc_get_consumed_stream(),
+						src_buf->vb.v4l2_planes[0].bytesused);
+				if (s5p_mfc_get_consumed_stream() <
+						src_buf->vb.v4l2_planes[0].bytesused)
+					dec->remained = 1;
+			}
+		}
+
+		s5p_mfc_clear_int_flags();
+		clear_work_bit(ctx);
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+			BUG();
+
+		s5p_mfc_clock_off();
+
+		queue_work(dev->irq_workqueue, &dev->work_struct);
+		wake_up_ctx(ctx, reason, err);
+		break;
+	case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET:
+		ctx->inst_no = s5p_mfc_get_inst_no();
+		ctx->state = MFCINST_GOT_INST;
+		clear_work_bit(ctx);
+		wake_up_interruptible(&ctx->queue);
+		goto irq_cleanup_hw;
+		break;
+	case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET:
+		clear_work_bit(ctx);
+		ctx->state = MFCINST_FREE;
+		wake_up(&ctx->queue);
+		goto irq_cleanup_hw;
+		break;
+	case S5P_FIMV_R2H_CMD_SYS_INIT_RET:
+	case S5P_FIMV_R2H_CMD_FW_STATUS_RET:
+	case S5P_FIMV_R2H_CMD_SLEEP_RET:
+	case S5P_FIMV_R2H_CMD_WAKEUP_RET:
+		s5p_mfc_clear_int_flags();
+		wake_up_dev(dev, reason, err);
+		clear_bit(0, &dev->hw_lock);
+		break;
+	case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET:
+		/* FIXME: check encoder on MFC 6.x */
+		s5p_mfc_clear_int_flags();
+		ctx->int_type = reason;
+		ctx->int_err = err;
+		ctx->int_cond = 1;
+		spin_lock(&dev->condlock);
+		clear_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock(&dev->condlock);
+		if (err == 0) {
+			ctx->state = MFCINST_RUNNING;
+			if (ctx->type == MFCINST_DECODER &&
+				dec->dst_memtype == V4L2_MEMORY_MMAP) {
+				if (!dec->dpb_flush && !dec->remained) {
+					mfc_debug(2, "INIT_BUFFERS with dpb_flush - leaving image in src queue.\n");
+					spin_lock_irqsave(&dev->irqlock, flags);
+					if (!list_empty(&ctx->src_queue)) {
+						src_buf = list_entry(ctx->src_queue.next,
+								struct s5p_mfc_buf, list);
+						list_del(&src_buf->list);
+						ctx->src_queue_cnt--;
+						vb2_buffer_done(&src_buf->vb, VB2_BUF_STATE_DONE);
+					}
+					spin_unlock_irqrestore(&dev->irqlock, flags);
+				} else {
+					if (dec->dpb_flush)
+						dec->dpb_flush = 0;
+				}
+			} else if (ctx->type == MFCINST_ENCODER) {
+				spin_lock_irqsave(&dev->irqlock, flags);
+				if (!list_empty(&ctx->src_queue)) {
+					src_buf = list_entry(ctx->src_queue.next,
+							struct s5p_mfc_buf, list);
+					list_del(&src_buf->list);
+					ctx->src_queue_cnt--;
+					vb2_buffer_done(&src_buf->vb, VB2_BUF_STATE_DONE);
+				}
+				spin_unlock_irqrestore(&dev->irqlock, flags);
+			}
+
+			if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+				BUG();
+
+			s5p_mfc_clock_off();
+
+			wake_up_interruptible(&ctx->queue);
+			queue_work(dev->irq_workqueue, &dev->work_struct);
+		} else {
+			if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+				BUG();
+
+			s5p_mfc_clock_off();
+
+			wake_up_interruptible(&ctx->queue);
+		}
+		break;
+	default:
+		mfc_debug(2, "Unknown int reason.\n");
+		s5p_mfc_clear_int_flags();
+	}
+	mfc_debug_leave();
+	return IRQ_HANDLED;
+irq_cleanup_hw:
+	s5p_mfc_clear_int_flags();
+	ctx->int_type = reason;
+	ctx->int_err = err;
+	ctx->int_cond = 1;
+	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
+		mfc_err("Failed to unlock hw.\n");
+
+	s5p_mfc_clock_off();
+
+	queue_work(dev->irq_workqueue, &dev->work_struct);
+	mfc_debug(2, "%s-- (via irq_cleanup_hw)\n", __func__);
+	return IRQ_HANDLED;
+}
+
+/* Open an MFC node */
+static int s5p_mfc_open(struct file *file)
+{
+	struct s5p_mfc_ctx *ctx = NULL;
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	unsigned long flags;
+	int ret = 0;
+	enum s5p_mfc_node_type node;
+
+	mfc_debug_enter();
+
+	node = s5p_mfc_get_node_type(file);
+	if (node == MFCNODE_INVALID) {
+		mfc_err("cannot specify node type\n");
+		ret = -ENOENT;
+		goto err_node_type;
+	}
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (dev->num_drm_inst > 0) {
+		 mfc_err("DRM instance was activated, cannot open no more instance\n");
+		 ret = -EINVAL;
+		 goto err_drm_playback;
+	}
+#endif
+	dev->num_inst++;	/* It is guarded by mfc_mutex in vfd */
+
+	/* Allocate memory for context */
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx) {
+		mfc_err("Not enough memory.\n");
+		ret = -ENOMEM;
+		goto err_ctx_alloc;
+	}
+
+	ret = v4l2_fh_init(&ctx->fh, (node == MFCNODE_DECODER) ?
+			   dev->vfd_dec : dev->vfd_enc);
+	if (ret)
+		goto err_v4l2_fh;
+	file->private_data = &ctx->fh;
+	v4l2_fh_add(&ctx->fh);
+
+	ctx->dev = dev;
+
+	/* Get context number */
+	ctx->num = 0;
+	while (dev->ctx[ctx->num]) {
+		ctx->num++;
+		if (ctx->num >= MFC_NUM_CONTEXTS) {
+			mfc_err("Too many open contexts.\n");
+			ret = -EBUSY;
+			goto err_ctx_num;
+		}
+	}
+
+	/* Mark context as idle */
+	spin_lock_irqsave(&dev->condlock, flags);
+	clear_bit(ctx->num, &dev->ctx_work_bits);
+	spin_unlock_irqrestore(&dev->condlock, flags);
+	dev->ctx[ctx->num] = ctx;
+
+	init_waitqueue_head(&ctx->queue);
+
+	if (node == MFCNODE_DECODER)
+		ret = s5p_mfc_init_dec_ctx(ctx);
+	else
+		ret = s5p_mfc_init_enc_ctx(ctx);
+	if (ret)
+		goto err_ctx_init;
+
+	ret = call_cop(ctx, init_ctx_ctrls, ctx);
+	if (ret) {
+		mfc_err("failed int init_buf_ctrls\n");
+		goto err_ctx_ctrls;
+	}
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (check_magic(dev->drm_info.virt)) {
+		if (dev->num_inst == 1) {
+			mfc_debug(1, "DRM instance opened\n");
+
+			dev->num_drm_inst++;
+			ctx->is_drm = 1;
+
+			s5p_mfc_alloc_instance_buffer(ctx);
+		} else {
+			clear_magic(dev->drm_info.virt);
+			mfc_err("MFC instances are not cleared before DRM instance!\n");
+			ret = -EINVAL;
+			goto err_drm_start;
+		}
+	}
+#endif
+
+	/* Load firmware if this is the first instance */
+	if (dev->num_inst == 1) {
+		dev->watchdog_timer.expires = jiffies +
+					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
+		add_timer(&dev->watchdog_timer);
+
+		/* Load the FW */
+		ret = s5p_mfc_alloc_firmware(dev);
+		if (ret)
+			goto err_fw_alloc;
+
+		ret = s5p_mfc_load_firmware(dev);
+		if (ret)
+			goto err_fw_load;
+
+		mfc_debug(2, "power on\n");
+		ret = s5p_mfc_power_on();
+		if (ret < 0) {
+			mfc_err("power on failed\n");
+			goto err_pwr_enable;
+		}
+
+		dev->curr_ctx = ctx->num;
+
+		/* Init the FW */
+		ret = s5p_mfc_init_hw(dev);
+		if (ret)
+			goto err_hw_init;
+	}
+
+	return ret;
+
+	/* Deinit when failure occured */
+err_hw_init:
+	s5p_mfc_power_off();
+
+err_pwr_enable:
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	s5p_mfc_release_dev_context_buffer(dev);
+#endif
+err_fw_load:
+	s5p_mfc_release_firmware(dev);
+
+err_fw_alloc:
+	del_timer_sync(&dev->watchdog_timer);
+	if (ctx->is_drm) {
+		s5p_mfc_release_instance_buffer(ctx);
+		dev->num_drm_inst--;
+	}
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+err_drm_start:
+#endif
+	call_cop(ctx, cleanup_ctx_ctrls, ctx);
+
+err_ctx_ctrls:
+	if (node == MFCNODE_DECODER)
+		kfree(ctx->dec_priv);
+	else if (ctx->type == MFCINST_ENCODER)
+		kfree(ctx->enc_priv);
+
+err_ctx_init:
+	dev->ctx[ctx->num] = 0;
+
+err_ctx_num:
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+
+err_v4l2_fh:
+	kfree(ctx);
+
+err_ctx_alloc:
+	dev->num_inst--;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+err_drm_playback:
+#endif
+err_node_type:
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Release MFC context */
+static int s5p_mfc_release(struct file *file)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+
+	mfc_debug_enter();
+
+	if (call_cop(ctx, cleanup_ctx_ctrls, ctx) < 0)
+		mfc_err("failed in init_buf_ctrls\n");
+
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+
+	vb2_queue_release(&ctx->vq_src);
+	vb2_queue_release(&ctx->vq_dst);
+
+	/* Mark context as idle */
+	spin_lock_irqsave(&dev->condlock, flags);
+	clear_bit(ctx->num, &dev->ctx_work_bits);
+	spin_unlock_irqrestore(&dev->condlock, flags);
+	/* If instance was initialised then
+	 * return instance and free reosurces */
+	if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
+		ctx->state = MFCINST_RETURN_INST;
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+		s5p_mfc_clean_ctx_int_flags(ctx);
+		s5p_mfc_try_run(dev);
+		/* Wait until instance is returned or timeout occured */
+		if (s5p_mfc_wait_for_done_ctx
+		    (ctx, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
+			mfc_err("Err returning instance.\n");
+		}
+		/* Free resources */
+		s5p_mfc_release_codec_buffers(ctx);
+		s5p_mfc_release_instance_buffer(ctx);
+		if (ctx->type == MFCINST_DECODER)
+			s5p_mfc_release_dec_desc_buffer(ctx);
+
+		ctx->inst_no = -1;
+	}
+	/* hardware locking scheme */
+	if (dev->curr_ctx == ctx->num)
+		clear_bit(0, &dev->hw_lock);
+
+	dev->num_inst--;
+
+	if (dev->num_inst == 0) {
+		/* FIXME: is it need ? */
+		s5p_mfc_deinit_hw(dev);
+
+		/* reset <-> F/W release */
+		s5p_mfc_release_firmware(dev);
+		del_timer_sync(&dev->watchdog_timer);
+
+		mfc_debug(2, "power off\n");
+		s5p_mfc_power_off();
+	}
+
+	if (ctx->type == MFCINST_DECODER)
+		kfree(ctx->dec_priv);
+	else if (ctx->type == MFCINST_ENCODER)
+		kfree(ctx->enc_priv);
+	dev->ctx[ctx->num] = 0;
+	kfree(ctx);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Poll */
+static unsigned int s5p_mfc_poll(struct file *file,
+				 struct poll_table_struct *wait)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	unsigned int ret = 0;
+
+	if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER)
+		ret = vb2_poll(&ctx->vq_src, file, wait);
+	else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER)
+		ret = vb2_poll(&ctx->vq_dst, file, wait);
+
+	return ret;
+}
+
+/* Mmap */
+static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+	int ret;
+
+	mfc_debug_enter();
+	if (offset < DST_QUEUE_OFF_BASE) {
+		mfc_debug(2, "mmaping source.\n");
+		ret = vb2_mmap(&ctx->vq_src, vma);
+	} else {		/* capture */
+		mfc_debug(2, "mmaping destination.\n");
+		vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
+		ret = vb2_mmap(&ctx->vq_dst, vma);
+	}
+	mfc_debug_leave();
+	return ret;
+}
+
+/* v4l2 ops */
+static const struct v4l2_file_operations s5p_mfc_fops = {
+	.owner = THIS_MODULE,
+	.open = s5p_mfc_open,
+	.release = s5p_mfc_release,
+	.poll = s5p_mfc_poll,
+	.unlocked_ioctl = video_ioctl2,
+	.mmap = s5p_mfc_mmap,
+};
+
+/* videodec structure */
+static struct video_device s5p_mfc_dec_videodev = {
+	.name = S5P_MFC_DEC_NAME,
+	.fops = &s5p_mfc_fops,
+	/*
+	.ioctl_ops = &s5p_mfc_ioctl_ops,
+	*/
+	.minor = -1,
+	.release = video_device_release,
+};
+
+static struct video_device s5p_mfc_enc_videodev = {
+	.name = S5P_MFC_ENC_NAME,
+	.fops = &s5p_mfc_fops,
+	/*
+	.ioctl_ops = &s5p_mfc_enc_ioctl_ops,
+	*/
+	.minor = -1,
+	.release = video_device_release,
+};
+
+/* MFC probe function */
+static int __devinit s5p_mfc_probe(struct platform_device *pdev)
+{
+	struct s5p_mfc_dev *dev;
+	struct video_device *vfd;
+	struct resource *res;
+	int ret = -ENOENT;
+	unsigned int alloc_ctx_num;
+	size_t size;
+	char workqueue_name[MFC_WORKQUEUE_LEN];
+
+	pr_debug("%s++\n", __func__);
+	dev = kzalloc(sizeof *dev, GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "Not enough memory for MFC device.\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&dev->irqlock);
+	spin_lock_init(&dev->condlock);
+	dev_dbg(&pdev->dev, "Initialised spin lock\n");
+	dev->plat_dev = pdev;
+	if (!dev->plat_dev) {
+		dev_err(&pdev->dev, "No platform data specified\n");
+		ret = -ENODEV;
+		goto free_dev;
+	}
+
+	dev->platdata = (&pdev->dev)->platform_data;
+	dev_dbg(&pdev->dev, "Getting clocks\n");
+	ret = s5p_mfc_init_pm(dev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get mfc clock source\n");
+		goto free_clk;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to get memory region resource.\n");
+		ret = -ENOENT;
+		goto probe_out1;
+	}
+	size = (res->end - res->start) + 1;
+	dev->mfc_mem = request_mem_region(res->start, size, pdev->name);
+	if (dev->mfc_mem == NULL) {
+		dev_err(&pdev->dev, "failed to get memory region.\n");
+		ret = -ENOENT;
+		goto probe_out2;
+	}
+	dev->regs_base = ioremap(dev->mfc_mem->start,
+			      dev->mfc_mem->end - dev->mfc_mem->start + 1);
+	if (dev->regs_base == NULL) {
+		dev_err(&pdev->dev, "failed to ioremap address region.\n");
+		ret = -ENOENT;
+		goto probe_out3;
+	}
+
+	s5p_mfc_init_reg(dev->regs_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to get irq resource.\n");
+		ret = -ENOENT;
+		goto probe_out4;
+	}
+	dev->irq = res->start;
+	ret = request_irq(dev->irq, s5p_mfc_irq, IRQF_DISABLED, pdev->name,
+									dev);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
+		goto probe_out5;
+	}
+
+	mutex_init(&dev->mfc_mutex);
+
+	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+	if (ret)
+		goto probe_out6;
+	init_waitqueue_head(&dev->queue);
+
+	/* decoder */
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto unreg_dev;
+	}
+	*vfd = s5p_mfc_dec_videodev;
+
+	vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
+
+	vfd->lock = &dev->mfc_mutex;
+	vfd->v4l2_dev = &dev->v4l2_dev;
+	snprintf(vfd->name, sizeof(vfd->name), "%s", s5p_mfc_dec_videodev.name);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, S5P_VIDEONODE_MFC_DEC);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
+		video_device_release(vfd);
+		goto rel_vdev_dec;
+	}
+	v4l2_info(&dev->v4l2_dev, "decoder registered as /dev/video%d\n",
+								vfd->num);
+	dev->vfd_dec = vfd;
+
+	video_set_drvdata(vfd, dev);
+
+	/* encoder */
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto unreg_vdev_dec;
+	}
+	*vfd = s5p_mfc_enc_videodev;
+
+	vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
+
+	vfd->lock = &dev->mfc_mutex;
+	vfd->v4l2_dev = &dev->v4l2_dev;
+	snprintf(vfd->name, sizeof(vfd->name), "%s", s5p_mfc_enc_videodev.name);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, S5P_VIDEONODE_MFC_ENC);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
+		video_device_release(vfd);
+		goto rel_vdev_enc;
+	}
+	v4l2_info(&dev->v4l2_dev, "encoder registered as /dev/video%d\n",
+								vfd->num);
+	dev->vfd_enc = vfd;
+
+	video_set_drvdata(vfd, dev);
+
+	platform_set_drvdata(pdev, dev);
+
+	dev->hw_lock = 0;
+	dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
+	INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
+	atomic_set(&dev->watchdog_cnt, 0);
+	init_timer(&dev->watchdog_timer);
+	dev->watchdog_timer.data = (unsigned long)dev;
+	dev->watchdog_timer.function = s5p_mfc_watchdog;
+
+	dev->variant = (struct s5p_mfc_variant *)
+		platform_get_device_id(pdev)->driver_data;
+
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+	dev->bus_dev = dev_get("exynos-busfreq");
+	atomic_set(&dev->busfreq_lock, 0);
+#endif
+#endif
+	/* default FW alloc is added */
+	alloc_ctx_num = dev->variant->port_num + 1;
+	dev->alloc_ctx = (struct vb2_alloc_ctx **)
+			s5p_mfc_mem_init_multi(&pdev->dev, alloc_ctx_num);
+
+	if (IS_ERR(dev->alloc_ctx)) {
+		mfc_err("Couldn't prepare allocator ctx.\n");
+		ret = PTR_ERR(dev->alloc_ctx);
+		goto alloc_ctx_fail;
+	}
+
+	if (soc_is_exynos5250()) {
+		if (samsung_rev() >= EXYNOS5250_REV_1_0)
+			dev->fw.ver = 0x65;
+		else
+			dev->fw.ver = 0x61;
+	} else {
+		dev->fw.ver = 0x50;
+	}
+
+	sprintf(workqueue_name, "mfc_workqueue");
+	dev->irq_workqueue = create_workqueue(workqueue_name);
+	if (dev->irq_workqueue == NULL) {
+		dev_err(&pdev->dev, "failed to create workqueue for mfc\n");
+		goto workqueue_fail;
+	}
+	INIT_WORK(&dev->work_struct, mfc_workqueue_try_run);
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	dev->alloc_ctx_fw = (struct vb2_alloc_ctx *)
+		vb2_ion_create_context(&pdev->dev,
+			IS_MFCV6(dev) ? SZ_4K : SZ_128K,
+			VB2ION_CTX_DRM_MFCFW);
+	if (IS_ERR(dev->alloc_ctx_fw)) {
+		mfc_err("failed to prepare F/W allocation context\n");
+		ret = PTR_ERR(dev->alloc_ctx_fw);
+		goto alloc_ctx_fw_fail;
+	}
+
+	dev->alloc_ctx_sh = (struct vb2_alloc_ctx *)
+		vb2_ion_create_context(&pdev->dev,
+			SZ_4K,
+			VB2ION_CTX_DRM_MFCSH);
+	if (IS_ERR(dev->alloc_ctx_sh)) {
+		mfc_err("failed to prepare shared allocation context\n");
+		ret = PTR_ERR(dev->alloc_ctx_sh);
+		goto alloc_ctx_sh_fail;
+	}
+
+	dev->drm_info.alloc = s5p_mfc_mem_allocate(dev->alloc_ctx_sh, PAGE_SIZE);
+	if (IS_ERR(dev->drm_info.alloc)) {
+		mfc_err("failed to allocate shared region\n");
+		ret = PTR_ERR(dev->drm_info.alloc);
+		goto shared_alloc_fail;
+	}
+	dev->drm_info.virt = s5p_mfc_mem_vaddr(dev->drm_info.alloc);
+	if (!dev->drm_info.virt) {
+		mfc_err("failed to get vaddr for shared region\n");
+		ret = -ENOMEM;
+		goto shared_vaddr_fail;
+	}
+
+	dev->alloc_ctx_drm = (struct vb2_alloc_ctx *)
+		vb2_ion_create_context(&pdev->dev,
+			SZ_4K,
+			VB2ION_CTX_DRM_VIDEO);
+	if (IS_ERR(dev->alloc_ctx_drm)) {
+		mfc_err("failed to prepare DRM allocation context\n");
+		ret = PTR_ERR(dev->alloc_ctx_drm);
+		goto alloc_ctx_drm_fail;
+	}
+
+	mfc_proc_entry = proc_mkdir(MFC_PROC_ROOT, NULL);
+	if (!mfc_proc_entry) {
+		dev_err(&pdev->dev, "unable to create /proc/%s\n",
+				MFC_PROC_ROOT);
+		ret = -ENOMEM;
+		goto err_proc_entry;
+	}
+
+	if (!create_proc_read_entry(MFC_PROC_INSTANCE_NUMBER,
+				0,
+				mfc_proc_entry,
+				proc_read_inst_number,
+				dev)) {
+		dev_err(&pdev->dev, "unable to create /proc/%s/%s\n",
+				MFC_PROC_ROOT, MFC_PROC_INSTANCE_NUMBER);
+		ret = -ENOMEM;
+		goto err_proc_number;
+	}
+
+	if (!create_proc_read_entry(MFC_PROC_DRM_INSTANCE_NUMBER,
+				0,
+				mfc_proc_entry,
+				proc_read_drm_inst_number,
+				dev)) {
+		dev_err(&pdev->dev, "unable to create /proc/%s/%s\n",
+				MFC_PROC_ROOT, MFC_PROC_DRM_INSTANCE_NUMBER);
+		ret = -ENOMEM;
+		goto err_proc_drm;
+	}
+
+	if (!create_proc_read_entry(MFC_PROC_FW_STATUS,
+				0,
+				mfc_proc_entry,
+				proc_read_fw_status,
+				dev)) {
+		dev_err(&pdev->dev, "unable to create /proc/%s/%s\n",
+				MFC_PROC_ROOT, MFC_PROC_FW_STATUS);
+		ret = -ENOMEM;
+		goto err_proc_fw;
+	}
+#endif
+	pr_debug("%s--\n", __func__);
+	return 0;
+
+/* Deinit MFC if probe had failed */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+err_proc_fw:
+	remove_proc_entry(MFC_PROC_DRM_INSTANCE_NUMBER, mfc_proc_entry);
+err_proc_drm:
+	remove_proc_entry(MFC_PROC_INSTANCE_NUMBER, mfc_proc_entry);
+err_proc_number:
+	remove_proc_entry(MFC_PROC_ROOT, NULL);
+err_proc_entry:
+	vb2_ion_destroy_context(dev->alloc_ctx_drm);
+shared_vaddr_fail:
+	s5p_mfc_mem_free(dev->drm_info.alloc);
+shared_alloc_fail:
+alloc_ctx_drm_fail:
+	vb2_ion_destroy_context(dev->alloc_ctx_sh);
+alloc_ctx_sh_fail:
+	vb2_ion_destroy_context(dev->alloc_ctx_fw);
+alloc_ctx_fw_fail:
+	destroy_workqueue(dev->irq_workqueue);
+#endif
+workqueue_fail:
+	s5p_mfc_mem_cleanup_multi((void **)dev->alloc_ctx,
+			alloc_ctx_num);
+alloc_ctx_fail:
+	video_unregister_device(dev->vfd_enc);
+rel_vdev_enc:
+	video_device_release(dev->vfd_enc);
+unreg_vdev_dec:
+	video_unregister_device(dev->vfd_dec);
+rel_vdev_dec:
+	video_device_release(dev->vfd_dec);
+unreg_dev:
+	v4l2_device_unregister(&dev->v4l2_dev);
+probe_out6:
+	free_irq(dev->irq, dev);
+probe_out5:
+probe_out4:
+	iounmap(dev->regs_base);
+	dev->regs_base = NULL;
+probe_out3:
+	release_resource(dev->mfc_mem);
+	kfree(dev->mfc_mem);
+probe_out2:
+probe_out1:
+	s5p_mfc_final_pm(dev);
+free_clk:
+
+free_dev:
+	kfree(dev);
+	pr_debug("%s-- with error\n", __func__);
+	return ret;
+}
+
+/* Remove the driver */
+static int __devexit s5p_mfc_remove(struct platform_device *pdev)
+{
+	struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
+
+	dev_dbg(&pdev->dev, "%s++\n", __func__);
+	v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
+	del_timer_sync(&dev->watchdog_timer);
+	flush_workqueue(dev->watchdog_workqueue);
+	destroy_workqueue(dev->watchdog_workqueue);
+	video_unregister_device(dev->vfd_enc);
+	video_unregister_device(dev->vfd_dec);
+	v4l2_device_unregister(&dev->v4l2_dev);
+	s5p_mfc_mem_cleanup_multi((void **)dev->alloc_ctx,
+					dev->variant->port_num + 1);
+	mfc_debug(2, "Will now deinit HW\n");
+	s5p_mfc_deinit_hw(dev);
+	free_irq(dev->irq, dev);
+	iounmap(dev->regs_base);
+	if (dev->mfc_mem != NULL) {
+		release_resource(dev->mfc_mem);
+		kfree(dev->mfc_mem);
+		dev->mfc_mem = NULL;
+	}
+	s5p_mfc_final_pm(dev);
+	kfree(dev);
+	dev_dbg(&pdev->dev, "%s--\n", __func__);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_mfc_suspend(struct device *dev)
+{
+	struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int ret;
+
+	if (m_dev->num_inst == 0)
+		return 0;
+
+	/* FIXME: how about locking ? */
+	ret = s5p_mfc_sleep(m_dev);
+
+	return ret;
+}
+
+static int s5p_mfc_resume(struct device *dev)
+{
+	struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int ret;
+
+	if (m_dev->num_inst == 0)
+		return 0;
+
+	/* FIXME: how about locking ? */
+	ret = s5p_mfc_wakeup(m_dev);
+
+	return ret;
+}
+#ifdef CONFIG_PM_RUNTIME
+static int s5p_mfc_runtime_suspend(struct device *dev)
+{
+	struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int pre_power;
+
+	pre_power = atomic_read(&m_dev->pm.power);
+	atomic_set(&m_dev->pm.power, 0);
+
+	return 0;
+}
+
+static int s5p_mfc_runtime_idle(struct device *dev)
+{
+	return 0;
+}
+
+static int s5p_mfc_runtime_resume(struct device *dev)
+{
+	struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int pre_power;
+
+	/* FIXME: */
+	if (!m_dev->alloc_ctx)
+		return 0;
+
+	pre_power = atomic_read(&m_dev->pm.power);
+	atomic_set(&m_dev->pm.power, 1);
+
+	return 0;
+}
+#endif
+
+#else
+#define s5p_mfc_suspend		NULL
+#define s5p_mfc_resume		NULL
+#ifdef CONFIG_PM_RUNTIME
+#define mfc_runtime_idle 	NULL
+#define mfc_runtime_suspend 	NULL
+#define mfc_runtime_resume	NULL
+#endif
+#endif
+
+/* Power management */
+static const struct dev_pm_ops s5p_mfc_pm_ops = {
+	.suspend		= s5p_mfc_suspend,
+	.resume			= s5p_mfc_resume,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_idle		= s5p_mfc_runtime_idle,
+	.runtime_suspend	= s5p_mfc_runtime_suspend,
+	.runtime_resume		= s5p_mfc_runtime_resume,
+#endif
+};
+
+struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
+	.h264_ctx_buf = 0x96000,
+	.non_h264_ctx_buf = 0x2800,
+	.desc_buf = 0x20000,
+	.shared_buf = 0x1000,
+};
+
+struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
+	.dev_ctx = 0x6400,
+	.h264_dec_ctx = 0x200000,	/* FIXME: 1.6MB */
+	.other_dec_ctx = 0x5000,	/*  20KB */
+	.h264_enc_ctx = 0x19000,	/* 100KB */
+	.other_enc_ctx = 0x2800,	/*  10KB */
+};
+
+struct s5p_mfc_buf_size buf_size_v5 = {
+	.firmware_code = 0x60000,
+	.cpb_buf = 0x400000,		/*   4MB */
+	.buf = &mfc_buf_size_v5,
+};
+
+struct s5p_mfc_buf_size buf_size_v6 = {
+	.firmware_code = 0x100000,	/* 1MB */
+	.cpb_buf = 0x300000,		/* 3MB */
+	.buf = &mfc_buf_size_v6,
+};
+
+struct s5p_mfc_buf_align mfc_buf_align_v5 = {
+	.mfc_base_align = 17,
+};
+
+struct s5p_mfc_buf_align mfc_buf_align_v6 = {
+	.mfc_base_align = 0,
+};
+
+static struct s5p_mfc_variant mfc_drvdata_v5 = {
+	.version = 0x51,
+	.port_num = 2,
+	.buf_size = &buf_size_v5,
+	.buf_align = &mfc_buf_align_v5,
+};
+
+static struct s5p_mfc_variant mfc_drvdata_v6 = {
+	.version = 0x61,
+	.port_num = 1,
+	.buf_size = &buf_size_v6,
+	.buf_align = &mfc_buf_align_v6,
+};
+
+static struct platform_device_id mfc_driver_ids[] = {
+	{
+		.name = "s5p-mfc",
+		.driver_data = (unsigned long)&mfc_drvdata_v5,
+	}, {
+		.name = "s5p-mfc-v5",
+		.driver_data = (unsigned long)&mfc_drvdata_v5,
+	}, {
+		.name = "s5p-mfc-v6",
+		.driver_data = (unsigned long)&mfc_drvdata_v6,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
+
+static struct platform_driver s5p_mfc_driver = {
+	.probe	= s5p_mfc_probe,
+	.remove	= __devexit_p(s5p_mfc_remove),
+	.id_table = mfc_driver_ids,
+	.driver	= {
+		.name	= S5P_MFC_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &s5p_mfc_pm_ops
+	},
+};
+
+static char banner[] __initdata =
+			"S5P MFC V4L2 Driver, (c) 2010 Samsung Electronics\n";
+
+static int __init s5p_mfc_init(void)
+{
+	pr_info("%s", banner);
+	if (platform_driver_register(&s5p_mfc_driver) != 0) {
+		pr_err("Platform device registration failed..\n");
+		return -1;
+	}
+	return 0;
+}
+
+static void __devexit s5p_mfc_exit(void)
+{
+	platform_driver_unregister(&s5p_mfc_driver);
+}
+
+module_init(s5p_mfc_init);
+module_exit(s5p_mfc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
+
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_cmd.h b/drivers/media/video/s5p-mfc/s5p_mfc_cmd.h
new file mode 100644
index 0000000..a6a8e006
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_cmd.h
@@ -0,0 +1,29 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_cmd.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_CMD_H
+#define __S5P_MFC_CMD_H __FILE__
+
+#define MAX_H2R_ARG		4
+
+struct s5p_mfc_cmd_args {
+	unsigned int	arg[MAX_H2R_ARG];
+};
+
+int s5p_mfc_cmd_host2risc(int cmd, struct s5p_mfc_cmd_args *args);
+int s5p_mfc_sys_init_cmd(struct s5p_mfc_dev *dev);
+int s5p_mfc_sleep_cmd(struct s5p_mfc_dev *dev);
+int s5p_mfc_wakeup_cmd(struct s5p_mfc_dev *dev);
+int s5p_mfc_open_inst_cmd(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_close_inst_cmd(struct s5p_mfc_ctx *ctx);
+
+#endif /* __S5P_MFC_CMD_H */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v5.c b/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v5.c
new file mode 100644
index 0000000..2ae4b7a
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v5.c
@@ -0,0 +1,147 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v5.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_cmd.h"
+#include "s5p_mfc_mem.h"
+
+int s5p_mfc_cmd_host2risc(int cmd, struct s5p_mfc_cmd_args *args)
+{
+	int cur_cmd;
+	unsigned long timeout;
+
+	timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
+
+	/* wait until host to risc command register becomes 'H2R_CMD_EMPTY' */
+	do {
+		if (time_after(jiffies, timeout)) {
+			mfc_err("Timeout while waiting for hardware.\n");
+			return -EIO;
+		}
+
+		cur_cmd = s5p_mfc_read_reg(S5P_FIMV_HOST2RISC_CMD);
+	} while (cur_cmd != S5P_FIMV_H2R_CMD_EMPTY);
+
+	s5p_mfc_write_reg(args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
+	s5p_mfc_write_reg(args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
+	s5p_mfc_write_reg(args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
+	s5p_mfc_write_reg(args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
+
+	/* Issue the command */
+	s5p_mfc_write_reg(cmd, S5P_FIMV_HOST2RISC_CMD);
+
+	return 0;
+}
+
+int s5p_mfc_sys_init_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
+	int ret;
+
+	mfc_debug_enter();
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+	h2r_args.arg[0] = buf_size->firmware_code;
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_SYS_INIT, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+int s5p_mfc_sleep_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret;
+
+	mfc_debug_enter();
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_SLEEP, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+int s5p_mfc_wakeup_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret;
+
+	mfc_debug_enter();
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_WAKEUP, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Open a new instance and get its number */
+int s5p_mfc_open_inst_cmd(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	unsigned int crc = 0;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	int ret;
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
+
+	if (ctx->type == MFCINST_DECODER)
+		crc = dec->crc_enable;
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+	h2r_args.arg[0] = ctx->codec_mode;
+	h2r_args.arg[1] = crc << 31; /* no pixelcache */
+	h2r_args.arg[2] = ctx->ctx.ofs;
+	h2r_args.arg[3] = ctx->ctx_buf_size;
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_OPEN_INSTANCE, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Close instance */
+int s5p_mfc_close_inst_cmd(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	if (ctx->state != MFCINST_FREE) {
+		memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+		h2r_args.arg[0] = ctx->inst_no;
+
+		ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_CLOSE_INSTANCE,
+					    &h2r_args);
+	} else {
+		ret = -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return ret;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v6.c
new file mode 100644
index 0000000..677692d
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v6.c
@@ -0,0 +1,130 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_cmd_v6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_cmd.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_pm.h"
+
+int s5p_mfc_cmd_host2risc(int cmd, struct s5p_mfc_cmd_args *args)
+{
+	mfc_debug(2, "Issue the command: %d\n", cmd);
+
+	/* Reset RISC2HOST command */
+	s5p_mfc_write_reg(0x0, S5P_FIMV_RISC2HOST_CMD);
+
+	/* Issue the command */
+	s5p_mfc_write_reg(cmd, S5P_FIMV_HOST2RISC_CMD);
+	s5p_mfc_write_reg(0x1, S5P_FIMV_HOST2RISC_INT);
+
+	return 0;
+}
+
+int s5p_mfc_sys_init_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->buf;
+	int ret;
+
+	mfc_debug_enter();
+
+	s5p_mfc_alloc_dev_context_buffer(dev);
+
+	s5p_mfc_write_reg(dev->ctx_buf.ofs, S5P_FIMV_CONTEXT_MEM_ADDR);
+	s5p_mfc_write_reg(buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE);
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_SYS_INIT, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+int s5p_mfc_sleep_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret;
+
+	mfc_debug_enter();
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_SLEEP, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+int s5p_mfc_wakeup_cmd(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret;
+
+	mfc_debug_enter();
+
+	memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_WAKEUP, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Open a new instance and get its number */
+int s5p_mfc_open_inst_cmd(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	int ret;
+
+	mfc_debug_enter();
+	mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
+
+	s5p_mfc_write_reg(ctx->codec_mode, S5P_FIMV_CODEC_TYPE);
+	s5p_mfc_write_reg(ctx->ctx.ofs, S5P_FIMV_CONTEXT_MEM_ADDR);
+	s5p_mfc_write_reg(ctx->ctx_buf_size, S5P_FIMV_CONTEXT_MEM_SIZE);
+	if (ctx->type == MFCINST_DECODER)
+		s5p_mfc_write_reg(dec->crc_enable, S5P_FIMV_D_CRC_CTRL);
+
+	ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_OPEN_INSTANCE, &h2r_args);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Close instance */
+int s5p_mfc_close_inst_cmd(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_cmd_args h2r_args;
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	if (ctx->state != MFCINST_FREE) {
+		s5p_mfc_write_reg(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+		ret = s5p_mfc_cmd_host2risc(S5P_FIMV_H2R_CMD_CLOSE_INSTANCE,
+					    &h2r_args);
+	} else {
+		ret = -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return ret;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_common.h b/drivers/media/video/s5p-mfc/s5p_mfc_common.h
new file mode 100644
index 0000000..aacd00b
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_common.h
@@ -0,0 +1,657 @@
+/*
+ * Samsung S5P Multi Format Codec v 5.0
+ *
+ * This file contains definitions of enums and structs used by the codec
+ * driver.
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Kamil Debski, <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version
+ */
+
+#ifndef S5P_MFC_COMMON_H_
+#define S5P_MFC_COMMON_H_
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-fh.h>
+
+#include <media/videobuf2-core.h>
+
+#if defined(CONFIG_S5P_SYSTEM_MMU)
+#define SYSMMU_MFC_ON
+#endif
+
+#define MFC_MAX_EXTRA_DPB       5
+#define MFC_MAX_BUFFERS		32
+#define MFC_MAX_REF_BUFS	2
+#define MFC_FRAME_PLANES	2
+
+#define MFC_NUM_CONTEXTS	4
+/* Interrupt timeout */
+#define MFC_INT_TIMEOUT		2000
+/* Busy wait timeout */
+#define MFC_BW_TIMEOUT		500
+/* Watchdog interval */
+#define MFC_WATCHDOG_INTERVAL   1000
+/* After how many executions watchdog should assume lock up */
+#define MFC_WATCHDOG_CNT        10
+
+#define MFC_NO_INSTANCE_SET	-1
+
+#define MFC_ENC_CAP_PLANE_COUNT	1
+#define MFC_ENC_OUT_PLANE_COUNT	2
+
+#define MFC_NAME_LEN		16
+#define MFC_FW_NAME		"mfc_fw.bin"
+
+#define STUFF_BYTE		4
+#define MFC_WORKQUEUE_LEN	32
+
+#define MFC_BASE_MASK		((1 << 17) - 1)
+#define MFC_VER_MAJOR(ver)	((ver >> 4) & 0xF)
+#define MFC_VER_MINOR(ver)	(ver & 0xF)
+
+/**
+ * enum s5p_mfc_inst_type - The type of an MFC device node.
+ */
+enum s5p_mfc_node_type {
+	MFCNODE_INVALID = -1,
+	MFCNODE_DECODER = 0,
+	MFCNODE_ENCODER = 1,
+};
+
+/**
+ * enum s5p_mfc_inst_type - The type of an MFC instance.
+ */
+enum s5p_mfc_inst_type {
+	MFCINST_INVALID = 0,
+	MFCINST_DECODER = 1,
+	MFCINST_ENCODER = 2,
+};
+
+/**
+ * enum s5p_mfc_inst_state - The state of an MFC instance.
+ */
+enum s5p_mfc_inst_state {
+	MFCINST_FREE = 0,
+	MFCINST_INIT = 100,
+	MFCINST_GOT_INST,
+	MFCINST_HEAD_PARSED,
+	MFCINST_BUFS_SET,
+	MFCINST_RUNNING,
+	MFCINST_FINISHING,
+	MFCINST_FINISHED,
+	MFCINST_RETURN_INST,
+	MFCINST_ERROR,
+	MFCINST_ABORT,
+	MFCINST_RES_CHANGE_INIT,
+	MFCINST_RES_CHANGE_FLUSH,
+	MFCINST_RES_CHANGE_END,
+	MFCINST_RUNNING_NO_OUTPUT,
+};
+
+/**
+ * enum s5p_mfc_queue_state - The state of buffer queue.
+ */
+enum s5p_mfc_queue_state {
+	QUEUE_FREE = 0,
+	QUEUE_BUFS_REQUESTED,
+	QUEUE_BUFS_QUERIED,
+	QUEUE_BUFS_MMAPED,
+};
+
+/**
+ * enum s5p_mfc_check_state - The state for user notification
+ */
+enum s5p_mfc_check_state {
+	MFCSTATE_PROCESSING = 0,
+	MFCSTATE_DEC_RES_DETECT,
+	MFCSTATE_DEC_TERMINATING,
+	MFCSTATE_ENC_NO_OUTPUT,
+};
+
+/**
+ * enum s5p_mfc_buf_cacheable_mask - The mask for cacheble setting
+ */
+enum s5p_mfc_buf_cacheable_mask {
+	MFCMASK_DST_CACHE = (1 << 0),
+	MFCMASK_SRC_CACHE = (1 << 1),
+};
+
+struct s5p_mfc_ctx;
+struct s5p_mfc_extra_buf;
+
+/**
+ * struct s5p_mfc_buf - MFC buffer
+ *
+ */
+struct s5p_mfc_buf {
+	struct vb2_buffer vb;
+	struct list_head list;
+	union {
+		struct {
+			size_t luma;
+			size_t chroma;
+		} raw;
+		size_t stream;
+	} cookie;
+	int used;
+};
+
+#define vb_to_mfc_buf(x)	\
+	container_of(x, struct s5p_mfc_buf, vb)
+
+struct s5p_mfc_pm {
+	struct clk	*clock;
+	atomic_t	power;
+	struct device	*device;
+};
+
+struct s5p_mfc_fw {
+	const struct firmware	*info;
+	int			state;
+	int			ver;
+	int			date;
+};
+
+struct s5p_mfc_buf_align {
+	unsigned int mfc_base_align;
+};
+
+struct s5p_mfc_buf_size_v5 {
+	unsigned int h264_ctx_buf;
+	unsigned int non_h264_ctx_buf;
+	unsigned int desc_buf;
+	unsigned int shared_buf;
+};
+
+struct s5p_mfc_buf_size_v6 {
+	unsigned int dev_ctx;
+	unsigned int h264_dec_ctx;
+	unsigned int other_dec_ctx;
+	unsigned int h264_enc_ctx;
+	unsigned int other_enc_ctx;
+};
+
+struct s5p_mfc_buf_size {
+	unsigned int firmware_code;
+	unsigned int cpb_buf;
+	void *buf;
+};
+
+struct s5p_mfc_variant {
+	unsigned int version;
+	unsigned int port_num;
+	struct s5p_mfc_buf_size *buf_size;
+	struct s5p_mfc_buf_align *buf_align;
+};
+
+/**
+ * struct s5p_mfc_extra_buf - represents internal used buffer
+ * @alloc:		allocation-specific contexts for each buffer
+ *			(videobuf2 allocator)
+ * @ofs:		offset of each buffer, will be used for MFC
+ * @virt:		kernel virtual address, only valid when the
+ *			buffer accessed by driver
+ * @dma:		DMA address, only valid when kernel DMA API used
+ */
+struct s5p_mfc_extra_buf {
+	void		*alloc;
+	unsigned long	ofs;
+	void		*virt;
+	dma_addr_t	dma;
+};
+
+/**
+ * struct s5p_mfc_dev - The struct containing driver internal parameters.
+ */
+struct s5p_mfc_dev {
+	struct v4l2_device	v4l2_dev;
+	struct video_device	*vfd_dec;
+	struct video_device	*vfd_enc;
+	struct platform_device	*plat_dev;
+
+	void __iomem		*regs_base;
+	int			irq;
+	struct resource		*mfc_mem;
+
+	struct s5p_mfc_pm	pm;
+	struct s5p_mfc_fw	fw;
+	struct s5p_mfc_variant	*variant;
+	struct s5p_mfc_platdata	*platdata;
+
+	int num_inst;
+	spinlock_t irqlock;
+	spinlock_t condlock;
+
+	struct mutex mfc_mutex;
+
+	int int_cond;
+	int int_type;
+	unsigned int int_err;
+	wait_queue_head_t queue;
+
+	size_t port_a;
+	size_t port_b;
+
+	unsigned long hw_lock;
+
+	/*
+	struct clk *clock1;
+	struct clk *clock2;
+	*/
+
+	/* For 6.x, Added for SYS_INIT context buffer */
+	struct s5p_mfc_extra_buf ctx_buf;
+
+	struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
+	int curr_ctx;
+	unsigned long ctx_work_bits;
+
+	atomic_t watchdog_cnt;
+	struct timer_list watchdog_timer;
+	struct workqueue_struct *watchdog_workqueue;
+	struct work_struct watchdog_work;
+
+	struct vb2_alloc_ctx **alloc_ctx;
+
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+	struct device *bus_dev;
+	atomic_t busfreq_lock;
+#endif
+#endif
+
+    /* for DRM */
+	int curr_ctx_drm;
+	int fw_status;
+	int num_drm_inst;
+	struct s5p_mfc_extra_buf drm_info;
+	struct vb2_alloc_ctx *alloc_ctx_fw;
+	struct vb2_alloc_ctx *alloc_ctx_sh;
+	struct vb2_alloc_ctx *alloc_ctx_drm;
+
+	struct work_struct work_struct;
+	struct workqueue_struct *irq_workqueue;
+};
+
+/**
+ *
+ */
+struct s5p_mfc_h264_enc_params {
+	enum v4l2_mpeg_video_h264_profile profile;
+	u8 level;
+	u8 interlace;
+	enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
+	s8 loop_filter_alpha;
+	s8 loop_filter_beta;
+	enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
+	u8 num_ref_pic_4p;
+	u8 _8x8_transform;
+	u32 rc_framerate;
+	u8 rc_frame_qp;
+	u8 rc_min_qp;
+	u8 rc_max_qp;
+	u8 rc_mb_dark;
+	u8 rc_mb_smooth;
+	u8 rc_mb_static;
+	u8 rc_mb_activity;
+	u8 rc_p_frame_qp;
+	u8 rc_b_frame_qp;
+	u8 ar_vui;
+	enum v4l2_mpeg_video_h264_vui_sar_idc ar_vui_idc;
+	u16 ext_sar_width;
+	u16 ext_sar_height;
+	u8 open_gop;
+	u16 open_gop_size;
+	u8 hier_qp;
+	enum v4l2_mpeg_video_h264_hierarchical_coding_type hier_qp_type;
+	u8 hier_qp_layer;
+	u8 hier_qp_layer_qp[7];
+	u8 sei_gen_enable;
+	u8 sei_fp_curr_frame_0;
+	enum v4l2_mpeg_video_h264_sei_fp_arrangement_type \
+					sei_fp_arrangement_type;
+	u32 fmo_enable;
+	u32 fmo_slice_map_type;
+	u32 fmo_slice_num_grp;
+	u32 fmo_run_length[4];
+	u32 fmo_sg_dir;
+	u32 fmo_sg_rate;
+	u32 aso_enable;
+	u32 aso_slice_order[8];
+};
+
+/**
+ *
+ */
+struct s5p_mfc_mpeg4_enc_params {
+	/* MPEG4 Only */
+	enum v4l2_mpeg_video_mpeg4_profile profile;
+	u8 level;
+	u8 quarter_pixel; /* MFC5.x */
+	u16 vop_time_res;
+	u16 vop_frm_delta;
+	u8 rc_b_frame_qp;
+	/* Common for MPEG4, H263 */
+	u32 rc_framerate;
+	u8 rc_frame_qp;
+	u8 rc_min_qp;
+	u8 rc_max_qp;
+	u8 rc_p_frame_qp;
+};
+
+/**
+ *
+ */
+struct s5p_mfc_enc_params {
+	u16 width;
+	u16 height;
+
+	u16 gop_size;
+	enum v4l2_mpeg_video_multi_slice_mode slice_mode;
+	u16 slice_mb;
+	u32 slice_bit;
+	u16 intra_refresh_mb;
+	u8 pad;
+	u8 pad_luma;
+	u8 pad_cb;
+	u8 pad_cr;
+	u8 rc_frame;
+	u32 rc_bitrate;
+	u16 rc_reaction_coeff;
+	u8 frame_tag;
+
+	u8 num_b_frame;		/* H.264/MPEG4 */
+	u8 rc_mb;		/* H.264: MFCv5, MPEG4/H.263: MFCv6 */
+	u16 vbv_buf_size;
+	enum v4l2_mpeg_video_header_mode seq_hdr_mode;
+	enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
+	u8 fixed_target_bit;
+
+	u16 rc_frame_delta;   /* MFC6.1 Only */
+
+	union {
+		struct s5p_mfc_h264_enc_params h264;
+		struct s5p_mfc_mpeg4_enc_params mpeg4;
+	} codec;
+};
+
+enum s5p_mfc_ctrl_type {
+	MFC_CTRL_TYPE_GET_SRC	= 0x1,
+	MFC_CTRL_TYPE_GET_DST	= 0x2,
+	MFC_CTRL_TYPE_SET	= 0x4,
+};
+
+#define	MFC_CTRL_TYPE_GET	(MFC_CTRL_TYPE_GET_SRC | MFC_CTRL_TYPE_GET_DST)
+#define	MFC_CTRL_TYPE_SRC	(MFC_CTRL_TYPE_SET | MFC_CTRL_TYPE_GET_SRC)
+#define	MFC_CTRL_TYPE_DST	(MFC_CTRL_TYPE_GET_DST)
+
+enum s5p_mfc_ctrl_mode {
+	MFC_CTRL_MODE_NONE	= 0x0,
+	MFC_CTRL_MODE_SFR	= 0x1,
+	MFC_CTRL_MODE_SHM	= 0x2,
+	MFC_CTRL_MODE_CST	= 0x4,
+};
+
+struct s5p_mfc_ctrl_cfg {
+	enum s5p_mfc_ctrl_type type;
+	unsigned int id;
+	/*
+	unsigned int is_dynamic;
+	*/
+	unsigned int is_volatile;	/* only for MFC_CTRL_TYPE_SET */
+	unsigned int mode;
+	unsigned int addr;
+	unsigned int mask;
+	unsigned int shft;
+	unsigned int flag_mode;		/* only for MFC_CTRL_TYPE_SET */
+	unsigned int flag_addr;		/* only for MFC_CTRL_TYPE_SET */
+	unsigned int flag_shft;		/* only for MFC_CTRL_TYPE_SET */
+};
+
+struct s5p_mfc_ctx_ctrl {
+	struct list_head list;
+	enum s5p_mfc_ctrl_type type;
+	unsigned int id;
+	unsigned int addr;
+	/*
+	unsigned int is_dynamic;
+	*/
+	int has_new;
+	int val;
+};
+
+struct s5p_mfc_buf_ctrl {
+	struct list_head list;
+	unsigned int id;
+	enum s5p_mfc_ctrl_type type;
+	int has_new;
+	int val;
+	unsigned int old_val;		/* only for MFC_CTRL_TYPE_SET */
+	unsigned int is_volatile;	/* only for MFC_CTRL_TYPE_SET */
+	unsigned int updated;
+	unsigned int mode;
+	unsigned int addr;
+	unsigned int mask;
+	unsigned int shft;
+	unsigned int flag_mode;		/* only for MFC_CTRL_TYPE_SET */
+	unsigned int flag_addr;		/* only for MFC_CTRL_TYPE_SET */
+	unsigned int flag_shft;		/* only for MFC_CTRL_TYPE_SET */
+};
+
+struct s5p_mfc_codec_ops {
+	/* initialization routines */
+	int (*alloc_ctx_buf) (struct s5p_mfc_ctx *ctx);
+	int (*alloc_desc_buf) (struct s5p_mfc_ctx *ctx);
+	int (*get_init_arg) (struct s5p_mfc_ctx *ctx, void *arg);
+	int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
+	int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
+	int (*set_init_arg) (struct s5p_mfc_ctx *ctx, void *arg);
+	int (*set_codec_bufs) (struct s5p_mfc_ctx *ctx);
+	int (*set_dpbs) (struct s5p_mfc_ctx *ctx);		/* decoder */
+	/* execution routines */
+	int (*get_exe_arg) (struct s5p_mfc_ctx *ctx, void *arg);
+	int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
+	int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
+	int (*multi_data_frame) (struct s5p_mfc_ctx *ctx);
+	int (*set_exe_arg) (struct s5p_mfc_ctx *ctx, void *arg);
+	/* configuration routines */
+	int (*get_codec_cfg) (struct s5p_mfc_ctx *ctx, unsigned int type, int *value);
+	int (*set_codec_cfg) (struct s5p_mfc_ctx *ctx, unsigned int type, int *value);
+	/* controls per buffer */
+	int (*init_ctx_ctrls) (struct s5p_mfc_ctx *ctx);
+	int (*cleanup_ctx_ctrls) (struct s5p_mfc_ctx *ctx);
+	int (*init_buf_ctrls) (struct s5p_mfc_ctx *ctx, enum s5p_mfc_ctrl_type type, unsigned int index);
+	int (*cleanup_buf_ctrls) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+	int (*to_buf_ctrls) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+	int (*to_ctx_ctrls) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+	int (*set_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+	int (*get_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+	int (*recover_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, struct list_head *head);
+};
+
+#define call_cop(c, op, args...)				\
+	(((c)->c_ops->op) ?					\
+		((c)->c_ops->op(args)) : 0)
+
+struct s5p_mfc_dec {
+	int total_dpb_count;
+
+	struct list_head dpb_queue;
+	unsigned int dpb_queue_cnt;
+
+	size_t src_buf_size;
+
+	int loop_filter_mpeg4;
+	int display_delay;
+	int is_packedpb;
+	int slice_enable;
+	int mv_count;
+
+	int crc_enable;
+	int crc_luma0;
+	int crc_chroma0;
+	int crc_luma1;
+	int crc_chroma1;
+
+	struct s5p_mfc_extra_buf dsc;
+	unsigned long consumed;
+	unsigned long dpb_status;
+	unsigned int dpb_flush;
+
+	enum v4l2_memory dst_memtype;
+	int sei_parse;
+
+	/* For 6.x */
+	int remained;
+};
+
+struct s5p_mfc_enc {
+	struct s5p_mfc_enc_params params;
+
+	size_t dst_buf_size;
+
+	int frame_count;
+	enum v4l2_mpeg_mfc51_video_frame_type frame_type;
+	enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
+
+	struct list_head ref_queue;
+	unsigned int ref_queue_cnt;
+
+	/* For 6.x */
+	size_t luma_dpb_size;
+	size_t chroma_dpb_size;
+	size_t me_buffer_size;
+	size_t tmv_buffer_size;
+
+	unsigned int slice_mode;
+	union {
+		unsigned int mb;
+		unsigned int bits;
+	} slice_size;
+};
+
+/**
+ * struct s5p_mfc_ctx - This struct contains the instance context
+ */
+struct s5p_mfc_ctx {
+	struct s5p_mfc_dev *dev;
+	struct v4l2_fh fh;
+	int num;
+
+	int int_cond;
+	int int_type;
+	unsigned int int_err;
+	wait_queue_head_t queue;
+
+	struct s5p_mfc_fmt *src_fmt;
+	struct s5p_mfc_fmt *dst_fmt;
+
+	struct vb2_queue vq_src;
+	struct vb2_queue vq_dst;
+
+	struct list_head src_queue;
+	struct list_head dst_queue;
+
+	unsigned int src_queue_cnt;
+	unsigned int dst_queue_cnt;
+
+	enum s5p_mfc_inst_type type;
+	enum s5p_mfc_inst_state state;
+	int inst_no;
+
+	int img_width;
+	int img_height;
+	int buf_width;
+	int buf_height;
+	int dpb_count;
+
+	int luma_size;
+	int chroma_size;
+	int mv_size;
+
+	/* Buffers */
+	void *port_a_buf;
+	size_t port_a_phys;
+	size_t port_a_size;
+
+	void *port_b_buf;
+	size_t port_b_phys;
+	size_t port_b_size;
+
+	enum s5p_mfc_queue_state capture_state;
+	enum s5p_mfc_queue_state output_state;
+
+	struct list_head ctrls;
+
+	struct list_head src_ctrls[MFC_MAX_BUFFERS];
+	struct list_head dst_ctrls[MFC_MAX_BUFFERS];
+
+	int src_ctrls_flag[MFC_MAX_BUFFERS];
+	int dst_ctrls_flag[MFC_MAX_BUFFERS];
+
+	unsigned int sequence;
+
+	/* Control values */
+	int codec_mode;
+	__u32 pix_format;
+	int cacheable;
+
+	/* Extra Buffers */
+	unsigned int ctx_buf_size;
+	struct s5p_mfc_extra_buf ctx;
+	struct s5p_mfc_extra_buf shm;
+
+	struct s5p_mfc_dec *dec_priv;
+	struct s5p_mfc_enc *enc_priv;
+
+	struct s5p_mfc_codec_ops *c_ops;
+
+	/* For 6.x */
+	size_t scratch_buf_size;
+
+	/* for DRM */
+	int is_drm;
+};
+
+#define fh_to_mfc_ctx(x)	\
+	container_of(x, struct s5p_mfc_ctx, fh)
+
+#define MFC_FMT_DEC	0
+#define MFC_FMT_ENC	1
+#define MFC_FMT_RAW	2
+
+#define HAS_PORTNUM(dev)	(dev ? (dev->variant ? \
+				(dev->variant->port_num ? 1 : 0) : 0 ) : 0 )
+#define IS_TWOPORT(dev)		(dev->variant->port_num == 2 ? 1 : 0)
+#define IS_MFCV6(dev)		(dev->variant->version >= 0x60 ? 1 : 0)
+
+struct s5p_mfc_fmt {
+	char *name;
+	u32 fourcc;
+	u32 codec_mode;
+	u32 type;
+	u32 num_planes;
+};
+
+#if defined(CONFIG_S5P_MFC_V5)
+#include "regs-mfc-v5.h"
+#include "s5p_mfc_opr_v5.h"
+#include "s5p_mfc_shm.h"
+#elif defined(CONFIG_S5P_MFC_V6)
+#include "regs-mfc-v6.h"
+#include "s5p_mfc_opr_v6.h"
+#endif
+
+#endif /* S5P_MFC_COMMON_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
new file mode 100644
index 0000000..38ddc6a
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
@@ -0,0 +1,598 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+
+#include <linux/firmware.h>
+#include <linux/err.h>
+#include <linux/sched.h>
+#include <linux/cma.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_cmd.h"
+#include "s5p_mfc_pm.h"
+
+static void *s5p_mfc_bitproc_buf;
+static dma_addr_t s5p_mfc_bitproc_phys;
+static unsigned char *s5p_mfc_bitproc_virt;
+//static dma_addr_t s5p_mfc_bitproc_dma;
+
+/* Allocate firmware */
+int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
+{
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+	int err;
+	struct cma_info mem_info_f, mem_info_a, mem_info_b;
+#endif
+	unsigned int base_align = dev->variant->buf_align->mfc_base_align;
+	unsigned int firmware_size = dev->variant->buf_size->firmware_code;
+
+	mfc_debug_enter();
+
+#if !defined(CONFIG_S5P_MFC_VB2_ION)
+	if (s5p_mfc_bitproc_buf) {
+		mfc_err("Attempting to allocate firmware when it seems that it is already loaded.\n");
+		return -ENOMEM;
+	}
+#else
+	if (s5p_mfc_bitproc_buf)
+		return 0;
+#endif
+
+	/* Get memory region information and check if it is correct */
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+	err = cma_info(&mem_info_f, dev->v4l2_dev.dev, MFC_CMA_FW);
+	mfc_debug(3, "Area \"%s\" is from %08x to %08x and has size %08x", "f",
+				mem_info_f.lower_bound, mem_info_f.upper_bound,
+							mem_info_f.total_size);
+	if (err) {
+		mfc_err("Couldn't get memory information from CMA.\n");
+		return -EINVAL;
+	}
+	err = cma_info(&mem_info_a, dev->v4l2_dev.dev, MFC_CMA_BANK1);
+	mfc_debug(3, "Area \"%s\" is from %08x to %08x and has size %08x", "a",
+			mem_info_a.lower_bound, mem_info_a.upper_bound,
+						mem_info_a.total_size);
+	if (err) {
+		mfc_err("Couldn't get memory information from CMA.\n");
+		return -EINVAL;
+	}
+
+	if (mem_info_f.upper_bound > mem_info_a.lower_bound) {
+			mfc_err("Firmware has to be "
+			"allocated before  memory for buffers (bank A).\n");
+		return -EINVAL;
+	}
+	mfc_debug(2, "Allocating memory for firmware.\n");
+	s5p_mfc_bitproc_buf = s5p_mfc_mem_allocate(
+		dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX], firmware_size);
+	if (IS_ERR(s5p_mfc_bitproc_buf)) {
+		s5p_mfc_bitproc_buf = 0;
+		printk(KERN_ERR "Allocating bitprocessor buffer failed\n");
+		return -ENOMEM;
+	}
+	s5p_mfc_bitproc_phys = s5p_mfc_mem_dma_addr(s5p_mfc_bitproc_buf);
+
+	if (s5p_mfc_bitproc_phys & ((1 << base_align) - 1)) {
+		mfc_err("The base memory is not aligned to %dBytes.\n",
+				(1 << base_align));
+		s5p_mfc_mem_free(s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+	dev->port_a = s5p_mfc_bitproc_phys;
+
+	s5p_mfc_bitproc_virt = s5p_mfc_mem_vaddr(s5p_mfc_bitproc_buf);
+
+	mfc_debug(2, "Virtual address for FW: %08lx\n",
+				(long unsigned int)s5p_mfc_bitproc_virt);
+	if (!s5p_mfc_bitproc_virt) {
+		mfc_err("Bitprocessor memory remap failed\n");
+		s5p_mfc_mem_free(s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+
+	if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
+		err = cma_info(&mem_info_b, dev->v4l2_dev.dev, MFC_CMA_BANK2);
+		mfc_debug(3, "Area \"%s\" is from %08x to %08x and has size %08x", "b",
+				mem_info_b.lower_bound, mem_info_b.upper_bound,
+				mem_info_b.total_size);
+		if (err) {
+			mfc_err("Couldn't get memory information from CMA.\n");
+			return -EINVAL;
+		}
+		dev->port_b = mem_info_b.lower_bound;
+		mfc_debug(2, "Port A: %08x Port B: %08x (FW: %08x size: %08x)\n",
+				dev->port_a, dev->port_b, s5p_mfc_bitproc_phys,
+							firmware_size);
+	} else {
+		mfc_debug(2, "Port : %08x (FW: %08x size: %08x)\n",
+				dev->port_a, s5p_mfc_bitproc_phys,
+						firmware_size);
+	}
+#elif defined(CONFIG_S5P_MFC_VB2_SDVMM)
+	mfc_debug(2, "Allocating memory for firmware.\n");
+	s5p_mfc_bitproc_buf = s5p_mfc_mem_alloc(
+		dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX], firmware_size);
+	if (IS_ERR(s5p_mfc_bitproc_buf)) {
+		s5p_mfc_bitproc_buf = 0;
+		printk(KERN_ERR "Allocating bitprocessor buffer failed\n");
+		return -ENOMEM;
+	}
+
+	s5p_mfc_bitproc_phys = s5p_mfc_mem_cookie(
+		dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX], s5p_mfc_bitproc_buf);
+	if (s5p_mfc_bitproc_phys & ((1 << base_align) - 1)) {
+		mfc_err("The base memory is not aligned to %dBytes.\n",
+				(1 << base_align));
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX],
+							s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+
+	s5p_mfc_bitproc_virt = s5p_mfc_mem_vaddr(
+		dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX], s5p_mfc_bitproc_buf);
+	mfc_debug(2, "Virtual address for FW: %08lx\n",
+				(long unsigned int)s5p_mfc_bitproc_virt);
+	if (!s5p_mfc_bitproc_virt) {
+		mfc_err("Bitprocessor memory remap failed\n");
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX],
+							s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+
+	dev->port_a = s5p_mfc_bitproc_phys;
+	dev->port_b = s5p_mfc_bitproc_phys;
+
+	mfc_debug(2, "Port A: %08x Port B: %08x (FW: %08x size: %08x)\n",
+			dev->port_a, dev->port_b,
+			s5p_mfc_bitproc_phys,
+			firmware_size);
+#elif defined(CONFIG_S5P_MFC_VB2_ION)
+	mfc_debug(2, "Allocating memory for firmware.\n");
+	s5p_mfc_bitproc_buf = s5p_mfc_mem_allocate(
+		dev->alloc_ctx[MFC_CMA_FW_ALLOC_CTX], firmware_size);
+	if (IS_ERR(s5p_mfc_bitproc_buf)) {
+		s5p_mfc_bitproc_buf = 0;
+		printk(KERN_ERR "Allocating bitprocessor buffer failed\n");
+		return -ENOMEM;
+	}
+
+	s5p_mfc_bitproc_phys = s5p_mfc_mem_dma_addr(s5p_mfc_bitproc_buf);
+	if (s5p_mfc_bitproc_phys & ((1 << base_align) - 1)) {
+		mfc_err("The base memory is not aligned to %dBytes.\n",
+				(1 << base_align));
+		s5p_mfc_mem_free(s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+
+	s5p_mfc_bitproc_virt = s5p_mfc_mem_vaddr(s5p_mfc_bitproc_buf);
+	mfc_debug(2, "Virtual address for FW: %08lx\n",
+				(long unsigned int)s5p_mfc_bitproc_virt);
+	if (!s5p_mfc_bitproc_virt) {
+		mfc_err("Bitprocessor memory remap failed\n");
+		s5p_mfc_mem_free(s5p_mfc_bitproc_buf);
+		s5p_mfc_bitproc_phys = 0;
+		s5p_mfc_bitproc_buf = 0;
+		return -EIO;
+	}
+
+	dev->port_a = s5p_mfc_bitproc_phys;
+	dev->port_b = s5p_mfc_bitproc_phys;
+
+	mfc_debug(2, "Port A: %08x Port B: %08x (FW: %08x size: %08x)\n",
+			dev->port_a, dev->port_b,
+			s5p_mfc_bitproc_phys,
+			firmware_size);
+
+#endif
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Load firmware to MFC */
+int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
+{
+	struct firmware *fw_blob;
+	unsigned int firmware_size = dev->variant->buf_size->firmware_code;
+	int err;
+
+	/* Firmare has to be present as a separate file or compiled
+	 * into kernel. */
+	mfc_debug_enter();
+	mfc_debug(2, "Requesting fw\n");
+	err = request_firmware((const struct firmware **)&fw_blob,
+					MFC_FW_NAME, dev->v4l2_dev.dev);
+
+	if (err != 0) {
+		mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel.\n");
+		return -EINVAL;
+	}
+
+	mfc_debug(2, "Ret of request_firmware: %d Size: %d\n", err, fw_blob->size);
+
+	if (fw_blob->size > firmware_size) {
+		mfc_err("MFC firmware is too big to be loaded.\n");
+		release_firmware(fw_blob);
+		return -ENOMEM;
+	}
+	if (s5p_mfc_bitproc_buf == 0 || s5p_mfc_bitproc_phys == 0) {
+		mfc_err("MFC firmware is not allocated or was not mapped correctly.\n");
+		release_firmware(fw_blob);
+		return -EINVAL;
+	}
+	memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
+	/*
+	s5p_mfc_bitproc_dma = dma_map_single(dev->v4l2_dev.dev,
+					     s5p_mfc_bitproc_virt,
+					     FIRMWARE_CODE_SIZE,
+					     DMA_TO_DEVICE);
+	*/
+	s5p_mfc_cache_clean_fw(s5p_mfc_bitproc_buf);
+	release_firmware(fw_blob);
+	mfc_debug_leave();
+	return 0;
+}
+
+/* Release firmware memory */
+int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
+{
+	/* Before calling this function one has to make sure
+	 * that MFC is no longer processing */
+	if (!s5p_mfc_bitproc_buf)
+		return -EINVAL;
+	/*
+	if (s5p_mfc_bitproc_dma)
+		dma_unmap_single(dev->v4l2_dev.dev, s5p_mfc_bitproc_dma,
+				 FIRMWARE_CODE_SIZE, DMA_TO_DEVICE);
+	*/
+	s5p_mfc_mem_free(s5p_mfc_bitproc_buf);
+
+	s5p_mfc_bitproc_virt =  0;
+	s5p_mfc_bitproc_phys = 0;
+	s5p_mfc_bitproc_buf = 0;
+	/*
+	s5p_mfc_bitproc_dma = 0;
+	*/
+	return 0;
+}
+
+/* Reset the device */
+static int s5p_mfc_reset(struct s5p_mfc_dev *dev)
+{
+	int i;
+	unsigned int status;
+	unsigned long timeout;
+
+	mfc_debug_enter();
+
+	/* Stop procedure */
+	/* FIXME: F/W can be access invalid address */
+	/* Reset VI */
+	/*
+	s5p_mfc_write_reg(0x3f7, S5P_FIMV_SW_RESET);
+	*/
+
+	if (IS_MFCV6(dev)) {
+		/* Reset IP */
+		s5p_mfc_write_reg(0xFEE, S5P_FIMV_MFC_RESET);	/*  except RISC, reset */
+		s5p_mfc_write_reg(0x0, S5P_FIMV_MFC_RESET);	/*  reset release */
+
+		/* Zero Initialization of MFC registers */
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC2HOST_CMD);
+		s5p_mfc_write_reg(0, S5P_FIMV_HOST2RISC_CMD);
+		s5p_mfc_write_reg(0, S5P_FIMV_FW_VERSION);
+
+		for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT; i++)
+			s5p_mfc_write_reg(0, S5P_FIMV_REG_CLEAR_BEGIN + (i*4));
+
+		/* Reset */
+		s5p_mfc_write_reg(0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
+
+		timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
+		/* Check bus status */
+		do {
+			if (time_after(jiffies, timeout)) {
+				mfc_err("Timeout while resetting MFC.\n");
+				return -EIO;
+			}
+			status = s5p_mfc_read_reg(S5P_FIMV_MFC_BUS_RESET_CTRL);
+		} while ((status & 0x2) == 0);
+
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC_ON);
+		s5p_mfc_write_reg(0x1FFF, S5P_FIMV_MFC_RESET);
+		s5p_mfc_write_reg(0, S5P_FIMV_MFC_RESET);
+	} else {
+		s5p_mfc_write_reg(0x3f6, S5P_FIMV_SW_RESET);	/*  reset RISC */
+		s5p_mfc_write_reg(0x3e2, S5P_FIMV_SW_RESET);	/*  All reset except for MC */
+		mdelay(10);
+
+		timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
+
+		/* Check MC status */
+		do {
+			if (time_after(jiffies, timeout)) {
+				mfc_err("Timeout while resetting MFC.\n");
+				return -EIO;
+			}
+
+			status = s5p_mfc_read_reg(S5P_FIMV_MC_STATUS);
+
+		} while (status & 0x3);
+
+		s5p_mfc_write_reg(0x0, S5P_FIMV_SW_RESET);
+		s5p_mfc_write_reg(0x3fe, S5P_FIMV_SW_RESET);
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
+{
+	if (IS_MFCV6(dev)) {
+		s5p_mfc_write_reg(dev->port_a, S5P_FIMV_RISC_BASE_ADDRESS);
+		mfc_debug(2, "Base Address : %08x\n", dev->port_a);
+	} else {
+		/* channelA, port0 */
+		s5p_mfc_write_reg(dev->port_a, S5P_FIMV_MC_DRAMBASE_ADR_A);
+		/* channelB, port1 */
+		s5p_mfc_write_reg(dev->port_b, S5P_FIMV_MC_DRAMBASE_ADR_B);
+
+		mfc_debug(2, "Port A: %08x, Port B: %08x\n", dev->port_a, dev->port_b);
+	}
+}
+
+static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
+{
+	if (IS_MFCV6(dev)) {
+		/* Zero initialization should be done before RESET.
+		 * Nothing to do here. */
+	} else {
+		s5p_mfc_write_reg(0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
+		s5p_mfc_write_reg(0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
+
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC2HOST_CMD);
+		s5p_mfc_write_reg(0, S5P_FIMV_HOST2RISC_CMD);
+	}
+}
+
+/* Initialize hardware */
+int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
+{
+	char dvx_info;
+	int mfc_info;
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	/* RMVME: */
+	if (!s5p_mfc_bitproc_buf)
+		return -EINVAL;
+
+	/* 0. MFC reset */
+	mfc_debug(2, "MFC reset...\n");
+
+	s5p_mfc_clock_on();
+
+	ret = s5p_mfc_reset(dev);
+	if (ret) {
+		mfc_err("Failed to reset MFC - timeout.\n");
+		goto err_init_hw;
+	}
+	mfc_debug(2, "Done MFC reset...\n");
+
+	/* 1. Set DRAM base Addr */
+	s5p_mfc_init_memctrl(dev);
+
+	/* 2. Initialize registers of channel I/F */
+	s5p_mfc_clear_cmds(dev);
+
+	/* 3. Release reset signal to the RISC */
+	if (IS_MFCV6(dev))
+		s5p_mfc_write_reg(0x1, S5P_FIMV_RISC_ON);
+	else
+		s5p_mfc_write_reg(0x3ff, S5P_FIMV_SW_RESET);
+
+	mfc_debug(2, "Will now wait for completion of firmware transfer.\n");
+	if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) {
+		mfc_err("Failed to load firmware.\n");
+		s5p_mfc_clean_dev_int_flags(dev);
+		ret = -EIO;
+		goto err_init_hw;
+	}
+
+	s5p_mfc_clean_dev_int_flags(dev);
+	/* 4. Initialize firmware */
+	ret = s5p_mfc_sys_init_cmd(dev);
+	if (ret) {
+		mfc_err("Failed to send command to MFC - timeout.\n");
+		goto err_init_hw;
+	}
+	mfc_debug(2, "Ok, now will write a command to init the system\n");
+	if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SYS_INIT_RET)) {
+		mfc_err("Failed to load firmware\n");
+		ret = -EIO;
+		/* Disable the clock that enabled in s5p_mfc_sys_init_cmd() */
+		s5p_mfc_clock_off();
+		goto err_init_hw;
+	}
+
+	dev->int_cond = 0;
+	if (dev->int_err != 0 || dev->int_type !=
+						S5P_FIMV_R2H_CMD_SYS_INIT_RET) {
+		/* Failure. */
+		mfc_err("Failed to init firmware - error: %d"
+				" int: %d.\n",dev->int_err, dev->int_type);
+		ret = -EIO;
+		goto err_init_hw;
+	}
+
+	dvx_info = MFC_GET_REG(SYS_FW_DVX_INFO);
+	if (dvx_info != 'D' && dvx_info != 'E')
+		dvx_info = 'N';
+
+	mfc_info("MFC v%x.%x, F/W : (%c) %02xyy, %02xmm, %02xdd\n",
+		 MFC_VER_MAJOR(dev->fw.ver),
+		 MFC_VER_MINOR(dev->fw.ver),
+		 dvx_info,
+		 MFC_GET_REG(SYS_FW_VER_YEAR),
+		 MFC_GET_REG(SYS_FW_VER_MONTH),
+		 MFC_GET_REG(SYS_FW_VER_DATE));
+
+	dev->fw.date = MFC_GET_REG(SYS_FW_VER_ALL);
+	/* Check MFC version and F/W version */
+	if (dev->fw.date >= 0x120328) {
+		mfc_info = MFC_GET_REG(SYS_MFC_VER);
+		if (mfc_info != dev->fw.ver) {
+			mfc_err("Invalid F/W version(0x%x) for MFC H/W(0x%x)\n",
+					mfc_info, dev->fw.ver);
+			ret = -EIO;
+			goto err_init_hw;
+		}
+	}
+
+err_init_hw:
+	s5p_mfc_clock_off();
+	mfc_debug_leave();
+
+	return ret;
+}
+
+
+/* Deinitialize hardware */
+void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
+{
+	s5p_mfc_clock_on();
+
+	s5p_mfc_reset(dev);
+	if (IS_MFCV6(dev))
+		s5p_mfc_release_dev_context_buffer(dev);
+
+	s5p_mfc_clock_off();
+}
+
+int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
+{
+	int ret;
+
+	mfc_debug_enter();
+
+	s5p_mfc_clock_on();
+
+	s5p_mfc_clean_dev_int_flags(dev);
+	ret = s5p_mfc_sleep_cmd(dev);
+	if (ret) {
+		mfc_err("Failed to send command to MFC - timeout.\n");
+		goto err_mfc_sleep;
+	}
+	if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SLEEP_RET)) {
+		mfc_err("Failed to sleep\n");
+		ret = -EIO;
+		goto err_mfc_sleep;
+	}
+
+	dev->int_cond = 0;
+	if (dev->int_err != 0 || dev->int_type !=
+						S5P_FIMV_R2H_CMD_SLEEP_RET) {
+		/* Failure. */
+		mfc_err("Failed to sleep - error: %d"
+				" int: %d.\n",dev->int_err, dev->int_type);
+		ret = -EIO;
+		goto err_mfc_sleep;
+	}
+
+err_mfc_sleep:
+	s5p_mfc_clock_off();
+	mfc_debug_leave();
+
+	return ret;
+}
+
+int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
+{
+	int ret;
+
+	mfc_debug_enter();
+
+	/* 0. MFC reset */
+	mfc_debug(2, "MFC reset...\n");
+
+	s5p_mfc_clock_on();
+
+	ret = s5p_mfc_reset(dev);
+	if (ret) {
+		mfc_err("Failed to reset MFC - timeout.\n");
+		goto err_mfc_wakeup;
+	}
+	mfc_debug(2, "Done MFC reset...\n");
+
+	/* 1. Set DRAM base Addr */
+	s5p_mfc_init_memctrl(dev);
+
+	/* 2. Initialize registers of channel I/F */
+	s5p_mfc_clear_cmds(dev);
+
+	s5p_mfc_clean_dev_int_flags(dev);
+	/* 3. Initialize firmware */
+	ret = s5p_mfc_wakeup_cmd(dev);
+	if (ret) {
+		mfc_err("Failed to send command to MFC - timeout.\n");
+		goto err_mfc_wakeup;
+	}
+
+	/* 4. Release reset signal to the RISC */
+	if (IS_MFCV6(dev))
+		s5p_mfc_write_reg(0x1, S5P_FIMV_RISC_ON);
+	else
+		s5p_mfc_write_reg(0x3ff, S5P_FIMV_SW_RESET);
+
+	mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
+	if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) {
+		mfc_err("Failed to load firmware\n");
+		ret = -EIO;
+		goto err_mfc_wakeup;
+	}
+
+	dev->int_cond = 0;
+	if (dev->int_err != 0 || dev->int_type !=
+						S5P_FIMV_R2H_CMD_WAKEUP_RET) {
+		/* Failure. */
+		mfc_err("Failed to wakeup - error: %d"
+				" int: %d.\n",dev->int_err, dev->int_type);
+		ret = -EIO;
+		goto err_mfc_wakeup;
+	}
+
+err_mfc_wakeup:
+	s5p_mfc_clock_off();
+	mfc_debug_leave();
+
+	return 0;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.h b/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.h
new file mode 100644
index 0000000..fa7f5ef
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.h
@@ -0,0 +1,29 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_CTRL_H
+#define __S5P_MFC_CTRL_H __FILE__
+
+int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev);
+int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev);
+int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev);
+/*
+int mfc_load_firmware(const unsigned char *data, size_t size);
+*/
+
+int s5p_mfc_init_hw(struct s5p_mfc_dev *dev);
+void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev);
+
+int s5p_mfc_sleep(struct s5p_mfc_dev *dev);
+int s5p_mfc_wakeup(struct s5p_mfc_dev *dev);
+
+#endif /* __S5P_MFC_CTRL_H */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_debug.h b/drivers/media/video/s5p-mfc/s5p_mfc_debug.h
new file mode 100644
index 0000000..e099f9b
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_debug.h
@@ -0,0 +1,48 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_debug.h
+ *
+ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver
+ * This file contains debug macros
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef S5P_MFC_DEBUG_H_
+#define S5P_MFC_DEBUG_H_
+
+#define DEBUG
+
+#ifdef DEBUG
+extern int debug;
+
+#define mfc_debug(level, fmt, args...)				\
+	do {							\
+		if (debug >= level)				\
+			printk(KERN_DEBUG "%s:%d: " fmt,	\
+				__func__, __LINE__, ##args);	\
+	} while(0)
+#else
+#define mfc_debug(fmt, args...)
+#endif
+
+#define mfc_debug_enter() mfc_debug(5, "enter")
+#define mfc_debug_leave() mfc_debug(5, "leave")
+
+#define mfc_err(fmt, args...)				\
+	do {						\
+		printk(KERN_ERR "%s:%d: " fmt,		\
+		       __func__, __LINE__, ##args);	\
+	} while(0)
+
+#define mfc_info(fmt, args...)				\
+	do {						\
+		printk(KERN_INFO "%s:%d: " fmt,		\
+		       __func__, __LINE__, ##args);	\
+	} while(0)
+
+#endif /* S5P_MFC_DEBUG_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_dec.c b/drivers/media/video/s5p-mfc/s5p_mfc_dec.c
new file mode 100644
index 0000000..44282ff
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_dec.c
@@ -0,0 +1,2318 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_dec.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ * Kamil Debski, <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <media/videobuf2-core.h>
+
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+#include <mach/dev.h>
+#endif
+#endif
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_dec.h"
+#include "s5p_mfc_pm.h"
+
+#undef STREAM_SAVE
+
+#ifdef STREAM_SAVE
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+#include <linux/file.h>
+
+static void save_stream(unsigned long addr, unsigned int size)
+{
+	struct file *file;
+	loff_t pos = 0;
+	int fd;
+	mm_segment_t old_fs;
+	char filename[128];
+	char save_path[128] = "/data/app";
+
+	static int frame_count = 0;
+	char infobuf[128];
+	int infolen;
+	char infoname[128];
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	sprintf(filename, "%s/stream.dump", save_path);
+	fd = sys_open(filename, O_WRONLY | O_CREAT | O_APPEND, 0644);
+	if (fd >= 0) {
+		file = fget(fd);
+
+		if (file) {
+			vfs_write(file, (u8 *)addr, size, &pos);
+			fput(file);
+		}
+
+		sys_close(fd);
+	} else {
+		mfc_err("failed to open file to dump: %d\n", fd);
+	}
+
+	sprintf(infoname, "%s/stream.info", save_path);
+	infolen = sprintf(infobuf, "%d, %d\n", frame_count, size);
+
+	fd = sys_open(infoname, O_WRONLY | O_CREAT | O_APPEND, 0644);
+	if (fd >= 0) {
+		file = fget(fd);
+
+		if (file) {
+			vfs_write(file, (u8 *)infobuf, infolen, &pos);
+			fput(file);
+		}
+
+		sys_close(fd);
+	} else {
+		mfc_err("failed to open file to dump: %d\n", fd);
+	}
+
+	frame_count++;
+
+	set_fs(old_fs);
+}
+
+static void vb2_save_buf(struct vb2_buffer *vb, unsigned int plane_no)
+{
+	unsigned char *addr;
+
+	addr = (unsigned char *)vb2_plane_vaddr(vb, plane_no);
+	s5p_mfc_cache_inv(vb, plane_no);
+
+	save_stream((unsigned long)addr, vb->v4l2_planes[plane_no].bytesused);
+}
+#endif
+
+#define DEF_SRC_FMT	2
+#define DEF_DST_FMT	0
+
+static struct s5p_mfc_fmt formats[] = {
+	{
+		.name = "4:2:0 2 Planes 16x16 Tiles",
+		.fourcc = V4L2_PIX_FMT_NV12MT_16X16,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes 64x32 Tiles",
+		.fourcc = V4L2_PIX_FMT_NV12MT,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes Y/CbCr",
+		.fourcc = V4L2_PIX_FMT_NV12M,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes Y/CrCb",
+		.fourcc = V4L2_PIX_FMT_NV21M,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "H264 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H264,
+		.codec_mode = S5P_FIMV_CODEC_H264_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	/* MFC 6.x only */
+	{
+		.name = "H264/MVC Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H264_MVC,
+		.codec_mode = S5P_FIMV_CODEC_H264_MVC_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "H263 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H263,
+		.codec_mode = S5P_FIMV_CODEC_H263_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "MPEG1 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_MPEG1,
+		.codec_mode = S5P_FIMV_CODEC_MPEG2_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "MPEG2 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_MPEG2,
+		.codec_mode = S5P_FIMV_CODEC_MPEG2_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "MPEG4 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_MPEG4,
+		.codec_mode = S5P_FIMV_CODEC_MPEG4_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "FIMV Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_FIMV,
+		.codec_mode = S5P_FIMV_CODEC_MPEG4_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "FIMV1 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_FIMV1,
+		.codec_mode = S5P_FIMV_CODEC_FIMV1_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "FIMV2 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_FIMV2,
+		.codec_mode = S5P_FIMV_CODEC_FIMV2_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "FIMV3 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_FIMV3,
+		.codec_mode = S5P_FIMV_CODEC_FIMV3_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "FIMV4 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_FIMV4,
+		.codec_mode = S5P_FIMV_CODEC_FIMV4_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "XviD Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_XVID,
+		.codec_mode = S5P_FIMV_CODEC_MPEG4_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "VC1 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_G,
+		.codec_mode = S5P_FIMV_CODEC_VC1_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "VC1 RCV Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_L,
+		.codec_mode = S5P_FIMV_CODEC_VC1RCV_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+	{
+		.name = "VC8 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_VP8,
+		.codec_mode = S5P_FIMV_CODEC_VP8_DEC,
+		.type = MFC_FMT_DEC,
+		.num_planes = 1,
+	},
+};
+
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+/* Find selected format description */
+static struct s5p_mfc_fmt *find_format(struct v4l2_format *f, unsigned int t)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat &&
+		    formats[i].type == t)
+			return (struct s5p_mfc_fmt *)&formats[i];
+	}
+
+	return NULL;
+}
+
+static struct v4l2_queryctrl controls[] = {
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H.264 Display Delay",
+		.minimum = -1,
+		.maximum = 32,
+		.step = 1,
+		.default_value = -1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Mpeg4 Loop Filter Enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Slice Interface Enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Packed PB Enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Frame Tag",
+		.minimum = 0,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_CACHEABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Cacheable flag",
+		.minimum = 0,
+		.maximum = 3,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "CRC enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "CRC data",
+		.minimum = 0,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "CRC data",
+		.minimum = 0,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Display status",
+		.minimum = 0,
+		.maximum = 3,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Frame type",
+		.minimum = 0,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+#if defined(CONFIG_S5P_MFC_VB2_ION)
+	{
+		.id		= V4L2_CID_SET_SHAREABLE,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "File descriptor for ION",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 1,
+	},
+#endif
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Frame pack sei parse flag",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+};
+
+#define NUM_CTRLS ARRAY_SIZE(controls)
+
+static struct v4l2_queryctrl *get_ctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < NUM_CTRLS; ++i)
+		if (id == controls[i].id)
+			return &controls[i];
+	return NULL;
+}
+
+/* Check whether a ctrl value if correct */
+static int check_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct v4l2_queryctrl *c;
+
+	c = get_ctrl(ctrl->id);
+	if (!c)
+		return -EINVAL;
+
+	if (ctrl->value < c->minimum || ctrl->value > c->maximum
+		|| (c->step != 0 && ctrl->value % c->step != 0)) {
+		v4l2_err(&dev->v4l2_dev, "invalid control value\n");
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = {
+	{
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_SHARED_SET_FRAME_TAG,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_SHARED_GET_FRAME_TAG_TOP,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_SI_DISPLAY_STATUS,
+		.mask = 0x7,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	/* CRC related definitions are based on non-H.264 type */
+	{
+		.type = MFC_CTRL_TYPE_GET_SRC,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_CRC_LUMA0,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_SRC,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_CRC_CHROMA0,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_SRC,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA_BOT,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_CRC_LUMA1,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_SRC,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA_BOT,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_CRC_CHROMA1,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_SRC,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_GENERATED,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_SI_DECODED_STATUS,
+		.mask = S5P_FIMV_DEC_CRC_GEN_MASK,
+		.shft = S5P_FIMV_DEC_CRC_GEN_SHIFT,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_AVAIL,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_FRAME_PACK_SEI_AVAIL,
+		.mask = 0x1,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRGMENT_ID,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_FRAME_PACK_ARRGMENT_ID,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_INFO,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_FRAME_PACK_SEI_INFO,
+		.mask = 0x3FFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_GRID_POS,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_FRAME_PACK_GRID_POS,
+		.mask = 0xFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_VIDEO_H264_MVC_VIEW_ID,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_D_MVC_VIEW_ID,
+		.mask = 0xFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+};
+
+#define NUM_CTRL_CFGS ARRAY_SIZE(mfc_ctrl_list)
+
+/* Check whether a context should be run on hardware */
+static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
+{
+	mfc_debug(2, "src=%d, dst=%d, state=%d capstat=%d\n",
+		  ctx->src_queue_cnt, ctx->dst_queue_cnt,
+		  ctx->state, ctx->capture_state);
+
+	/* Context is to parse header */
+	if (ctx->src_queue_cnt >= 1 && ctx->state == MFCINST_GOT_INST)
+		return 1;
+	/* Context is to decode a frame */
+	if (ctx->src_queue_cnt >= 1 &&
+	    ctx->state == MFCINST_RUNNING &&
+	    ctx->dst_queue_cnt >= ctx->dpb_count)
+		return 1;
+	/* Context is to return last frame */
+	if (ctx->state == MFCINST_FINISHING &&
+	    ctx->dst_queue_cnt >= ctx->dpb_count)
+		return 1;
+	/* Context is to set buffers */
+	if (ctx->src_queue_cnt >= 1 &&
+	    ctx->state == MFCINST_HEAD_PARSED &&
+	    ctx->capture_state == QUEUE_BUFS_MMAPED)
+		return 1;
+	/* Resolution change */
+	if ((ctx->state == MFCINST_RES_CHANGE_INIT ||
+		ctx->state == MFCINST_RES_CHANGE_FLUSH) &&
+		ctx->dst_queue_cnt >= ctx->dpb_count)
+		return 1;
+	if (ctx->state == MFCINST_RES_CHANGE_END &&
+		ctx->src_queue_cnt >= 1)
+		return 1;
+
+	mfc_debug(2, "s5p_mfc_ctx_ready: ctx is not ready.\n");
+
+	return 0;
+}
+
+static int dec_init_ctx_ctrls(struct s5p_mfc_ctx *ctx)
+{
+	int i;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+
+	INIT_LIST_HEAD(&ctx->ctrls);
+
+	for (i = 0; i < NUM_CTRL_CFGS; i++) {
+		ctx_ctrl = kzalloc(sizeof(struct s5p_mfc_ctx_ctrl), GFP_KERNEL);
+		if (ctx_ctrl == NULL) {
+			mfc_err("failed to allocate ctx_ctrl type: %d, id: 0x%08x\n",
+				mfc_ctrl_list[i].type, mfc_ctrl_list[i].id);
+
+			return -ENOMEM;
+		}
+
+		ctx_ctrl->type = mfc_ctrl_list[i].type;
+		ctx_ctrl->id = mfc_ctrl_list[i].id;
+		ctx_ctrl->addr = mfc_ctrl_list[i].addr;
+		ctx_ctrl->has_new = 0;
+		ctx_ctrl->val = 0;
+
+		list_add_tail(&ctx_ctrl->list, &ctx->ctrls);
+
+		mfc_debug(5, "add ctx ctrl id: 0x%08x, type : %d\n",
+				ctx_ctrl->id, ctx_ctrl->type);
+	}
+
+	return 0;
+}
+
+static int dec_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+
+	while (!list_empty(&ctx->ctrls)) {
+		ctx_ctrl = list_entry((&ctx->ctrls)->next,
+				      struct s5p_mfc_ctx_ctrl, list);
+
+		mfc_debug(5, "del ctx ctrl id: 0x%08x\n", ctx_ctrl->id);
+
+		list_del(&ctx_ctrl->list);
+		kfree(ctx_ctrl);
+	}
+
+	INIT_LIST_HEAD(&ctx->ctrls);
+
+	return 0;
+}
+
+static int dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx,
+	enum s5p_mfc_ctrl_type type, unsigned int index)
+{
+	int i;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	struct list_head *head;
+
+	if (type & MFC_CTRL_TYPE_SRC) {
+		head = &ctx->src_ctrls[index];
+		ctx->src_ctrls_flag[index] = 1;
+	} else if (type & MFC_CTRL_TYPE_DST) {
+		head = &ctx->dst_ctrls[index];
+		ctx->dst_ctrls_flag[index] = 1;
+	} else {
+		mfc_err("Control type missmatch. type : %d\n", type);
+		return -EINVAL;
+	}
+
+	INIT_LIST_HEAD(head);
+
+	list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+		if (!(type & ctx_ctrl->type))
+			continue;
+
+		for (i = 0; i < NUM_CTRL_CFGS; i++)
+			if (ctx_ctrl->id == mfc_ctrl_list[i].id)
+				break;
+
+		if (i == NUM_CTRL_CFGS) {
+			mfc_err("Failed to get control. id : 0x%x\n", ctx_ctrl->id);
+			return -EINVAL;
+		}
+
+		buf_ctrl = kzalloc(sizeof(struct s5p_mfc_buf_ctrl), GFP_KERNEL);
+		if (buf_ctrl == NULL) {
+			mfc_err("failed to allocate buf_ctrl type: %d, id: 0x%08x\n",
+				mfc_ctrl_list[i].type, mfc_ctrl_list[i].id);
+
+			return -ENOMEM;
+		}
+
+		buf_ctrl->id = ctx_ctrl->id;
+		buf_ctrl->type = ctx_ctrl->type;
+		buf_ctrl->has_new = 0;
+		buf_ctrl->val = 0;
+		buf_ctrl->old_val = 0;
+		buf_ctrl->is_volatile = mfc_ctrl_list[i].is_volatile;
+		buf_ctrl->mode = mfc_ctrl_list[i].mode;
+		buf_ctrl->addr = ctx_ctrl->addr;
+		buf_ctrl->mask = mfc_ctrl_list[i].mask;
+		buf_ctrl->shft = mfc_ctrl_list[i].shft;
+		buf_ctrl->flag_mode = mfc_ctrl_list[i].flag_mode;
+		buf_ctrl->flag_addr = mfc_ctrl_list[i].flag_addr;
+		buf_ctrl->flag_shft = mfc_ctrl_list[i].flag_shft;
+
+		list_add_tail(&buf_ctrl->list, head);
+
+		mfc_debug(5, "add buf ctrl id: 0x%08x, type : %d\n",
+				buf_ctrl->id, buf_ctrl->type);
+	}
+
+	return 0;
+}
+
+static int dec_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	while (!list_empty(head)) {
+		buf_ctrl = list_entry(head->next,
+				      struct s5p_mfc_buf_ctrl, list);
+
+		mfc_debug(5, "del buf ctrl id: 0x%08x\n",  buf_ctrl->id);
+
+		list_del(&buf_ctrl->list);
+		kfree(buf_ctrl);
+	}
+
+	INIT_LIST_HEAD(head);
+
+	return 0;
+}
+
+static int dec_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+		if ((ctx_ctrl->type != MFC_CTRL_TYPE_SET) || (!ctx_ctrl->has_new))
+			continue;
+
+		list_for_each_entry(buf_ctrl, head, list) {
+			if (buf_ctrl->id == ctx_ctrl->id) {
+				buf_ctrl->has_new = 1;
+				buf_ctrl->val = ctx_ctrl->val;
+				if (buf_ctrl->is_volatile)
+					buf_ctrl->updated = 0;
+
+				ctx_ctrl->has_new = 0;
+				break;
+			}
+		}
+	}
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (buf_ctrl->has_new)
+			mfc_debug(5, "id: 0x%08x val: %d\n",
+				 buf_ctrl->id, buf_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int dec_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (!buf_ctrl->has_new)
+			continue;
+
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if ((ctx_ctrl->type & MFC_CTRL_TYPE_GET) == 0)
+				continue;
+
+			if (ctx_ctrl->id == buf_ctrl->id) {
+				mfc_debug(2, "overwrite ctx ctrl value\n");
+
+				ctx_ctrl->has_new = 1;
+				ctx_ctrl->val = buf_ctrl->val;
+
+				buf_ctrl->has_new = 0;
+			}
+		}
+	}
+
+	list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+		if (ctx_ctrl->has_new)
+			mfc_debug(5, "id: 0x%08x val: %d\n",
+				  ctx_ctrl->id, ctx_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int dec_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (!buf_ctrl->has_new)
+			continue;
+
+		/* read old vlaue */
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		/* save old vlaue for recovery */
+		if (buf_ctrl->is_volatile)
+			buf_ctrl->old_val = (value >> buf_ctrl->shft) & buf_ctrl->mask;
+
+		/* write new value */
+		value &= ~(buf_ctrl->mask << buf_ctrl->shft);
+		value |= ((buf_ctrl->val & buf_ctrl->mask) << buf_ctrl->shft);
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			s5p_mfc_write_reg(value, buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			s5p_mfc_write_info(ctx, value, buf_ctrl->addr);
+
+		/* set change flag bit */
+		if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) {
+			value = s5p_mfc_read_reg(buf_ctrl->flag_addr);
+			value |= (1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_reg(value, buf_ctrl->flag_addr);
+		} else if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SHM) {
+			value = s5p_mfc_read_info(ctx, buf_ctrl->flag_addr);
+			value |= (1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_info(ctx, value, buf_ctrl->flag_addr);
+		}
+
+		buf_ctrl->has_new = 0;
+		buf_ctrl->updated = 1;
+
+		mfc_debug(5, "id: 0x%08x val: %d\n", buf_ctrl->id,
+			  buf_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int dec_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if ((buf_ctrl->type & MFC_CTRL_TYPE_GET) == 0)
+			continue;
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		value = (value >> buf_ctrl->shft) & buf_ctrl->mask;
+
+		buf_ctrl->val = value;
+		buf_ctrl->has_new = 1;
+
+		mfc_debug(5, "id: 0x%08x val: %d\n", buf_ctrl->id,
+			  buf_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int dec_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if ((!buf_ctrl->is_volatile) || (!buf_ctrl->updated))
+			continue;
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		value &= ~(buf_ctrl->mask << buf_ctrl->shft);
+		value |= ((buf_ctrl->old_val & buf_ctrl->mask) << buf_ctrl->shft);
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			s5p_mfc_write_reg(value, buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			s5p_mfc_write_info(ctx, value, buf_ctrl->addr);
+
+		/* clear change flag bit */
+		if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) {
+			value = s5p_mfc_read_reg(buf_ctrl->flag_addr);
+			value &= ~(1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_reg(value, buf_ctrl->flag_addr);
+		} else if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SHM) {
+			value = s5p_mfc_read_info(ctx, buf_ctrl->flag_addr);
+			value &= ~(1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_info(ctx, value, buf_ctrl->flag_addr);
+		}
+
+		mfc_debug(5, "id: 0x%08x old_val: %d\n", buf_ctrl->id,
+			  buf_ctrl->old_val);
+	}
+
+	return 0;
+}
+
+static struct s5p_mfc_codec_ops decoder_codec_ops = {
+	.pre_seq_start		= NULL,
+	.post_seq_start		= NULL,
+	.pre_frame_start	= NULL,
+	.post_frame_start	= NULL,
+	.init_ctx_ctrls		= dec_init_ctx_ctrls,
+	.cleanup_ctx_ctrls	= dec_cleanup_ctx_ctrls,
+	.init_buf_ctrls		= dec_init_buf_ctrls,
+	.cleanup_buf_ctrls	= dec_cleanup_buf_ctrls,
+	.to_buf_ctrls		= dec_to_buf_ctrls,
+	.to_ctx_ctrls		= dec_to_ctx_ctrls,
+	.set_buf_ctrls_val	= dec_set_buf_ctrls_val,
+	.get_buf_ctrls_val	= dec_get_buf_ctrls_val,
+	.recover_buf_ctrls_val	= dec_recover_buf_ctrls_val,
+};
+
+/* Query capabilities of the device */
+static int vidioc_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+
+	strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT
+						    | V4L2_CAP_STREAMING;
+	return 0;
+}
+
+/* Enumerate format */
+static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool mplane, bool out)
+{
+	struct s5p_mfc_fmt *fmt;
+	int i, j = 0;
+
+	for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+		if (mplane && formats[i].num_planes == 1)
+			continue;
+		else if (!mplane && formats[i].num_planes > 1)
+			continue;
+		/* FIXME: to Kamil */
+		/*
+		if (out && formats[i].type != MFC_FMT_RAW)
+			continue;
+		else if (!out && formats[i].type != MFC_FMT_DEC)
+			continue;
+		*/
+		if (out && formats[i].type != MFC_FMT_DEC)
+			continue;
+		else if (!out && formats[i].type != MFC_FMT_RAW)
+			continue;
+
+		if (j == f->index)
+			break;
+		++j;
+	}
+	if (i == ARRAY_SIZE(formats))
+		return -EINVAL;
+	fmt = &formats[i];
+	strlcpy(f->description, fmt->name, sizeof(f->description));
+	f->pixelformat = fmt->fourcc;
+	return 0;
+}
+
+static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv,
+							struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, false, false);
+}
+
+static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
+							struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, true, false);
+}
+
+static int vidioc_enum_fmt_vid_out(struct file *file, void *prov,
+							struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, false, true);
+}
+
+static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov,
+							struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, true, true);
+}
+
+/* Get format */
+static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct v4l2_pix_format_mplane *pix_mp;
+
+	mfc_debug_enter();
+	pix_mp = &f->fmt.pix_mp;
+	mfc_debug(2, "f->type = %d ctx->state = %d\n", f->type, ctx->state);
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE &&
+	    (ctx->state == MFCINST_GOT_INST || ctx->state == MFCINST_RES_CHANGE_END)) {
+		/* If the MFC is parsing the header,
+		 * so wait until it is finished */
+		s5p_mfc_clean_ctx_int_flags(ctx);
+		s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_SEQ_DONE_RET,
+									1);
+	}
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE &&
+	    ctx->state >= MFCINST_HEAD_PARSED &&
+	    ctx->state < MFCINST_ABORT) {
+		/* This is run on CAPTURE (deocde output) */
+		/* Width and height are set to the dimensions
+		   of the movie, the buffer is bigger and
+		   further processing stages should crop to this
+		   rectangle. */
+		pix_mp->width = ctx->img_width;
+		pix_mp->height = ctx->img_height;
+		pix_mp->field = V4L2_FIELD_NONE;
+		pix_mp->num_planes = 2;
+		/* Set pixelformat to the format in which MFC
+		   outputs the decoded frame */
+		pix_mp->pixelformat = V4L2_PIX_FMT_NV12MT;
+		pix_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+		pix_mp->plane_fmt[0].sizeimage = ctx->buf_width * ctx->buf_height;
+		pix_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+		pix_mp->plane_fmt[1].sizeimage = ctx->buf_width * (ctx->buf_height >> 1);
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		/* This is run on OUTPUT
+		   The buffer contains compressed image
+		   so width and height have no meaning */
+		pix_mp->width = 0;
+		pix_mp->height = 0;
+		pix_mp->field = V4L2_FIELD_NONE;
+		pix_mp->plane_fmt[0].bytesperline = dec->src_buf_size;
+		pix_mp->plane_fmt[0].sizeimage = dec->src_buf_size;
+		pix_mp->pixelformat = ctx->src_fmt->fourcc;
+		pix_mp->num_planes = ctx->src_fmt->num_planes;
+	} else {
+		mfc_err("Format could not be read\n");
+		mfc_debug(2, "%s-- with error\n", __func__);
+		return -EINVAL;
+	}
+	mfc_debug_leave();
+	return 0;
+}
+
+/* Try format */
+static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_fmt *fmt;
+
+	mfc_debug(2, "Type is %d\n", f->type);
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		fmt = find_format(f, MFC_FMT_DEC);
+		if (!fmt) {
+			mfc_err("Unsupported format for source.\n");
+			return -EINVAL;
+		}
+		if (!IS_MFCV6(dev)) {
+			if (fmt->fourcc == V4L2_PIX_FMT_VP8) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		}
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		fmt = find_format(f, MFC_FMT_RAW);
+		if (!fmt) {
+			mfc_err("Unsupported format for destination.\n");
+			return -EINVAL;
+		}
+		if (IS_MFCV6(dev)) {
+			if (fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		} else {
+			if (fmt->fourcc != V4L2_PIX_FMT_NV12MT) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		}
+	}
+	/* Width and height are left intact as they may be relevant for
+	 * FIMV1 decoding. */
+
+	return 0;
+}
+
+/* Set format */
+static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned long flags;
+	int ret = 0;
+	struct s5p_mfc_fmt *fmt;
+	struct v4l2_pix_format_mplane *pix_mp;
+	int i;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+
+	mfc_debug_enter();
+	ret = vidioc_try_fmt(file, priv, f);
+	pix_mp = &f->fmt.pix_mp;
+	if (ret)
+		return ret;
+	if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
+		v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
+		ret = -EBUSY;
+		goto out;
+	}
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		fmt = find_format(f, MFC_FMT_RAW);
+		if (!fmt) {
+			mfc_err("Unsupported format for source.\n");
+			return -EINVAL;
+		}
+		if (!IS_MFCV6(dev)) {
+			if (fmt->fourcc != V4L2_PIX_FMT_NV12MT) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		} else if (IS_MFCV6(dev)) {
+			if (fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		}
+		ctx->dst_fmt = fmt;
+		mfc_debug_leave();
+		return ret;
+	} else if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		mfc_err("Wrong type error for S_FMT : %d", f->type);
+		return -EINVAL;
+	}
+
+	fmt = find_format(f, MFC_FMT_DEC);
+	if (!fmt || fmt->codec_mode == MFC_FORMATS_NO_CODEC) {
+		mfc_err("Unknown codec.\n");
+		ret = -EINVAL;
+		goto out;
+	}
+	if (!IS_MFCV6(dev)) {
+		if (fmt->fourcc == V4L2_PIX_FMT_VP8) {
+			mfc_err("Not supported format.\n");
+			return -EINVAL;
+		}
+	}
+	ctx->src_fmt = fmt;
+	ctx->codec_mode = fmt->codec_mode;
+	mfc_debug(2, "The codec number is: %d\n", ctx->codec_mode);
+	ctx->pix_format = pix_mp->pixelformat;
+	if ((pix_mp->width > 0) && (pix_mp->height > 0)) {
+		ctx->img_height = pix_mp->height;
+		ctx->img_width = pix_mp->width;
+	}
+	/* As this buffer will contain compressed data, the size is set
+	 * to the maximum size. */
+	if (pix_mp->plane_fmt[0].sizeimage)
+		dec->src_buf_size = pix_mp->plane_fmt[0].sizeimage;
+	else
+		dec->src_buf_size = MAX_FRAME_SIZE;
+	mfc_debug(2, "s_fmt w/h: %dx%d, ctx: %dx%d\n", pix_mp->width,
+		pix_mp->height, ctx->img_width, ctx->img_height);
+	mfc_debug(2, "sizeimage: %d\n", pix_mp->plane_fmt[0].sizeimage);
+	pix_mp->plane_fmt[0].bytesperline = 0;
+
+	/* In case of calling s_fmt twice or more */
+	if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
+		ctx->state = MFCINST_RETURN_INST;
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+		s5p_mfc_clean_ctx_int_flags(ctx);
+		s5p_mfc_try_run(dev);
+		/* Wait until instance is returned or timeout occured */
+		if (s5p_mfc_wait_for_done_ctx
+		    (ctx, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
+			mfc_err("Err returning instance.\n");
+		}
+		/* Free resources */
+		s5p_mfc_release_instance_buffer(ctx);
+		s5p_mfc_release_dec_desc_buffer(ctx);
+
+		ctx->state = MFCINST_INIT;
+	}
+
+	if (dec->crc_enable && (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
+				ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC)) {
+		/* CRC related control types should be changed by the codec mode. */
+		mfc_debug(5, "ctx_ctrl is changed for H.264\n");
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			switch (ctx_ctrl->id) {
+			case V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA:
+				ctx_ctrl->type = MFC_CTRL_TYPE_GET_DST;
+				ctx_ctrl->addr = S5P_FIMV_CRC_DISP_LUMA0;
+				break;
+			case V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA:
+				ctx_ctrl->type = MFC_CTRL_TYPE_GET_DST;
+				ctx_ctrl->addr = S5P_FIMV_CRC_DISP_CHROMA0;
+				break;
+			case V4L2_CID_MPEG_MFC51_VIDEO_CRC_GENERATED:
+				ctx_ctrl->type = MFC_CTRL_TYPE_GET_DST;
+				ctx_ctrl->addr = S5P_FIMV_CRC_DISP_STATUS;
+				break;
+			case V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA_BOT:
+			case V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA_BOT:
+				ctx_ctrl->type = MFC_CTRL_TYPE_GET_DST;
+				break;
+			default:
+				break;
+			}
+		}
+
+		/* Reinitialize controls for source buffers */
+		for (i = 0; i < MFC_MAX_BUFFERS; i++) {
+			if (ctx->src_ctrls_flag[i]) {
+				if (call_cop(ctx, cleanup_buf_ctrls, ctx, &ctx->src_ctrls[i]) < 0)
+					mfc_err("failed in cleanup_buf_ctrls\n");
+				ctx->src_ctrls_flag[i] = 0;
+				if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, i) < 0)
+					mfc_err("failed in init_buf_ctrls\n");
+			}
+		}
+	}
+
+	s5p_mfc_alloc_instance_buffer(ctx);
+	s5p_mfc_alloc_dec_temp_buffers(ctx);
+	spin_lock_irqsave(&dev->condlock, flags);
+	set_bit(ctx->num, &dev->ctx_work_bits);
+	spin_unlock_irqrestore(&dev->condlock, flags);
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_try_run(dev);
+	if (s5p_mfc_wait_for_done_ctx(ctx,
+				S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET, 1)) {
+		/* Error or timeout */
+		mfc_err("Error getting instance from hardware.\n");
+		s5p_mfc_release_instance_buffer(ctx);
+		s5p_mfc_release_dec_desc_buffer(ctx);
+		ret = -EIO;
+		goto out;
+	}
+	mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
+out:
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Reqeust buffers */
+static int vidioc_reqbufs(struct file *file, void *priv,
+		struct v4l2_requestbuffers *reqbufs)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	int ret = 0;
+	unsigned long flags;
+	int cacheable;
+
+	mfc_debug_enter();
+	mfc_debug(2, "Memory type: %d\n", reqbufs->memory);
+
+	if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		cacheable = (ctx->cacheable & MFCMASK_SRC_CACHE) ? 1 : 0;
+		s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], cacheable);
+		/* Can only request buffers after
+		   an instance has been opened.*/
+		if (ctx->state == MFCINST_GOT_INST) {
+			if (reqbufs->count == 0) {
+				mfc_debug(2, "Freeing buffers.\n");
+				ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
+				return ret;
+			}
+			/* Decoding */
+			if (ctx->output_state != QUEUE_FREE) {
+				mfc_err("Bufs have already been requested.\n");
+				return -EINVAL;
+			}
+			ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
+			if (ret) {
+				mfc_err("vb2_reqbufs on output failed.\n");
+				return ret;
+			}
+			mfc_debug(2, "vb2_reqbufs: %d\n", ret);
+			ctx->output_state = QUEUE_BUFS_REQUESTED;
+		}
+	} else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		dec->dst_memtype = reqbufs->memory;
+
+		/* cacheable setting */
+		cacheable = (ctx->cacheable & MFCMASK_DST_CACHE) ? 1 : 0;
+		if (ctx->is_drm) {
+			s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx_drm,
+				cacheable);
+		} else {
+			if (!IS_MFCV6(dev))
+				s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX],
+					cacheable);
+
+			s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+				cacheable);
+		}
+
+		if (reqbufs->count == 0) {
+			mfc_debug(2, "Freeing buffers.\n");
+			ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+			dec->dpb_queue_cnt = 0;
+			return ret;
+		}
+
+		if (ctx->capture_state != QUEUE_FREE) {
+			mfc_err("Bufs have already been requested.\n");
+			return -EINVAL;
+		}
+
+		ctx->capture_state = QUEUE_BUFS_REQUESTED;
+
+		ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+		if (ret) {
+			mfc_err("vb2_reqbufs on capture failed.\n");
+			return ret;
+		}
+
+		if (reqbufs->count < ctx->dpb_count) {
+			mfc_err("Not enough buffers allocated.\n");
+			reqbufs->count = 0;
+			ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+			return -ENOMEM;
+		}
+
+		dec->total_dpb_count = reqbufs->count;
+
+		ret = s5p_mfc_alloc_codec_buffers(ctx);
+		if (ret) {
+			mfc_err("Failed to allocate decoding buffers.\n");
+			reqbufs->count = 0;
+			ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+			return -ENOMEM;
+		}
+
+		if (dec->dst_memtype == V4L2_MEMORY_MMAP) {
+			if (dec->dpb_queue_cnt == dec->total_dpb_count) {
+				ctx->capture_state = QUEUE_BUFS_MMAPED;
+			} else {
+				mfc_err("Not all buffers passed to buf_init.\n");
+				reqbufs->count = 0;
+				ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+				s5p_mfc_release_codec_buffers(ctx);
+				return -ENOMEM;
+			}
+		}
+
+		if (s5p_mfc_ctx_ready(ctx)) {
+			spin_lock_irqsave(&dev->condlock, flags);
+			set_bit(ctx->num, &dev->ctx_work_bits);
+			spin_unlock_irqrestore(&dev->condlock, flags);
+		}
+
+		s5p_mfc_try_run(dev);
+
+		if (dec->dst_memtype == V4L2_MEMORY_MMAP) {
+			s5p_mfc_wait_for_done_ctx(ctx,
+					S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET, 1);
+		}
+	}
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Query buffer */
+static int vidioc_querybuf(struct file *file, void *priv,
+						   struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret;
+	int i;
+
+	mfc_debug_enter();
+
+	if (buf->memory != V4L2_MEMORY_MMAP) {
+		mfc_err("Only mmaped buffers can be used.\n");
+		return -EINVAL;
+	}
+
+	mfc_debug(2, "State: %d, buf->type: %d\n", ctx->state, buf->type);
+	if (ctx->state == MFCINST_GOT_INST &&
+			buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		ret = vb2_querybuf(&ctx->vq_src, buf);
+	} else if (ctx->state == MFCINST_RUNNING &&
+			buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		ret = vb2_querybuf(&ctx->vq_dst, buf);
+		for (i = 0; i < buf->length; i++)
+			buf->m.planes[i].m.mem_offset += DST_QUEUE_OFF_BASE;
+	} else {
+		mfc_err("vidioc_querybuf called in an inappropriate state.\n");
+		ret = -EINVAL;
+	}
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Queue a buffer */
+static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "Enqueued buf: %d, (type = %d)\n", buf->index, buf->type);
+	if (ctx->state == MFCINST_ERROR) {
+		mfc_err("Call on QBUF after unrecoverable error.\n");
+		return -EIO;
+	}
+
+	if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		return vb2_qbuf(&ctx->vq_src, buf);
+	else
+		return vb2_qbuf(&ctx->vq_dst, buf);
+
+	mfc_debug_leave();
+	return -EINVAL;
+}
+
+/* Dequeue a buffer */
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret;
+
+	mfc_debug_enter();
+	mfc_debug(2, "Addr: %p %p %p Type: %d\n", &ctx->vq_src, buf, buf->m.planes,
+								buf->type);
+	if (ctx->state == MFCINST_ERROR) {
+		mfc_err("Call on DQBUF after unrecoverable error.\n");
+		return -EIO;
+	}
+	if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
+	else
+		ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Stream on */
+static int vidioc_streamon(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int freq_mif = 400;
+	int freq_int = 200;
+	int lock_bw = 1280 * 720;
+#endif
+#endif
+	int ret = -EINVAL;
+
+	mfc_debug_enter();
+	if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		ret = vb2_streamon(&ctx->vq_src, type);
+	} else {
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+		if ((atomic_read(&dev->busfreq_lock) == 0) &&
+				(ctx->img_width * ctx->img_height > lock_bw)) {
+			dev_lock(dev->bus_dev, dev->v4l2_dev.dev, (freq_mif * 1000) + freq_int);
+			atomic_set(&dev->busfreq_lock, 1);
+			mfc_debug(1, "busfreq locked on <%d/%d>MHz\n", freq_mif, freq_int);
+		}
+#endif
+#endif
+		ret = vb2_streamon(&ctx->vq_dst, type);
+	}
+	mfc_debug(2, "ctx->src_queue_cnt = %d ctx->state = %d "
+		  "ctx->dst_queue_cnt = %d ctx->dpb_count = %d\n",
+		  ctx->src_queue_cnt, ctx->state, ctx->dst_queue_cnt,
+		  ctx->dpb_count);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Stream off, which equals to a pause */
+static int vidioc_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+	struct s5p_mfc_dev *dev = ctx->dev;
+#endif
+#endif
+	int ret;
+
+	mfc_debug_enter();
+	ret = -EINVAL;
+	if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		ret = vb2_streamoff(&ctx->vq_src, type);
+	} else {
+		ret = vb2_streamoff(&ctx->vq_dst, type);
+#ifdef CONFIG_BUSFREQ_OPP
+#ifdef CONFIG_CPU_EXYNOS5250
+		if (atomic_read(&dev->busfreq_lock) == 1) {
+			dev_unlock(dev->bus_dev, dev->v4l2_dev.dev);
+			atomic_set(&dev->busfreq_lock, 0);
+			mfc_debug(1, "busfreq locked off\n");
+		}
+#endif
+#endif
+	}
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Query a ctrl */
+static int vidioc_queryctrl(struct file *file, void *priv,
+			    struct v4l2_queryctrl *qc)
+{
+	struct v4l2_queryctrl *c;
+
+	c = get_ctrl(qc->id);
+	if (!c)
+		return -EINVAL;
+	*qc = *c;
+	return 0;
+}
+
+/* Get ctrl */
+static int get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	switch (ctrl->id) {
+	case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER:
+		ctrl->value = dec->loop_filter_mpeg4;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY:
+		ctrl->value = dec->display_delay;
+		break;
+	case V4L2_CID_CACHEABLE:
+		ctrl->value = ctx->cacheable;
+		break;
+	case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
+		if (ctx->state >= MFCINST_HEAD_PARSED &&
+		    ctx->state < MFCINST_ABORT) {
+			ctrl->value = ctx->dpb_count;
+			break;
+		} else if (ctx->state != MFCINST_INIT) {
+			v4l2_err(&dev->v4l2_dev, "Decoding not initialised.\n");
+			return -EINVAL;
+		}
+
+		/* Should wait for the header to be parsed */
+		s5p_mfc_clean_ctx_int_flags(ctx);
+		s5p_mfc_wait_for_done_ctx(ctx,
+				S5P_FIMV_R2H_CMD_SEQ_DONE_RET, 1);
+		if (ctx->state >= MFCINST_HEAD_PARSED &&
+		    ctx->state < MFCINST_ABORT) {
+			ctrl->value = ctx->dpb_count;
+		} else {
+			v4l2_err(&dev->v4l2_dev,
+					 "Decoding not initialised.\n");
+			return -EINVAL;
+		}
+		break;
+	case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE:
+		ctrl->value = dec->slice_enable;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB:
+		ctrl->value = dec->is_packedpb;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE:
+		ctrl->value = dec->crc_enable;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_CHECK_STATE:
+		if (ctx->state == MFCINST_RES_CHANGE_FLUSH
+				|| ctx->state == MFCINST_RES_CHANGE_END
+				|| ctx->state == MFCINST_HEAD_PARSED)
+			ctrl->value = MFCSTATE_DEC_RES_DETECT;
+		else if (ctx->state == MFCINST_FINISHING)
+			ctrl->value = MFCSTATE_DEC_TERMINATING;
+		else
+			ctrl->value = MFCSTATE_PROCESSING;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING:
+		ctrl->value = dec->sei_parse;
+		break;
+	default:
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if ((ctx_ctrl->type & MFC_CTRL_TYPE_GET) == 0)
+				continue;
+
+			if (ctx_ctrl->id == ctrl->id) {
+				if (ctx_ctrl->has_new) {
+					ctx_ctrl->has_new = 0;
+					ctrl->value = ctx_ctrl->val;
+				} else {
+					ctrl->value = 0;
+				}
+
+				ret = 1;
+				break;
+			}
+		}
+		if (!ret) {
+			v4l2_err(&dev->v4l2_dev, "invalid control 0x%08x\n", ctrl->id);
+			return -EINVAL;
+		}
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Get a ctrl */
+static int vidioc_g_ctrl(struct file *file, void *priv,
+			struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = 0;
+
+	mfc_debug_enter();
+	ret = get_ctrl_val(ctx, ctrl);
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Set a ctrl */
+static int vidioc_s_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	int ret = 0;
+	int stream_on;
+
+	mfc_debug_enter();
+
+	stream_on = ctx->vq_src.streaming || ctx->vq_dst.streaming;
+
+	ret = check_ctrl_val(ctx, ctrl);
+	if (ret != 0)
+		return ret;
+
+	switch (ctrl->id) {
+	case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER:
+		if (stream_on)
+			return -EBUSY;
+		dec->loop_filter_mpeg4 = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY:
+		if (stream_on)
+			return -EBUSY;
+		dec->display_delay = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE:
+		if (stream_on)
+			return -EBUSY;
+		dec->slice_enable = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB:
+		if (stream_on)
+			return -EBUSY;
+		if (ctx->codec_mode != S5P_FIMV_CODEC_MPEG4_DEC &&
+			ctx->codec_mode != S5P_FIMV_CODEC_FIMV1_DEC &&
+			ctx->codec_mode != S5P_FIMV_CODEC_FIMV2_DEC &&
+			ctx->codec_mode != S5P_FIMV_CODEC_FIMV3_DEC &&
+			ctx->codec_mode != S5P_FIMV_CODEC_FIMV4_DEC)
+			return -EINVAL;
+		dec->is_packedpb = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE:
+		if (ctrl->value == 1 || ctrl->value == 0)
+			dec->crc_enable = ctrl->value;
+		else
+			dec->crc_enable = 0;
+		break;
+	case V4L2_CID_CACHEABLE:
+		/*if (stream_on)
+			return -EBUSY; */
+		ctx->cacheable |= ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING:
+		/*if (stream_on)
+			return -EBUSY; */
+		if(ctrl->value == 0 || ctrl->value ==1)
+			dec->sei_parse = ctrl->value;
+		else
+			dec->sei_parse = 0;
+		break;
+	default:
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if (ctx_ctrl->type != MFC_CTRL_TYPE_SET)
+				continue;
+
+			if (ctx_ctrl->id == ctrl->id) {
+				ctx_ctrl->has_new = 1;
+				ctx_ctrl->val = ctrl->value;
+
+				ret = 1;
+				break;
+			}
+		}
+
+		if (!ret) {
+			v4l2_err(&dev->v4l2_dev, "invalid control 0x%08x\n", ctrl->id);
+			return -EINVAL;
+		}
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Get cropping information */
+static int vidioc_g_crop(struct file *file, void *priv,
+		struct v4l2_crop *cr)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	u32 left, right, top, bottom;
+
+	mfc_debug_enter();
+	if (ctx->state != MFCINST_HEAD_PARSED &&
+	ctx->state != MFCINST_RUNNING && ctx->state != MFCINST_FINISHING
+					&& ctx->state != MFCINST_FINISHED) {
+			mfc_debug(2, "%s-- with error\n", __func__);
+			return -EINVAL;
+		}
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264) {
+		s5p_mfc_clock_on();
+		left = s5p_mfc_read_info(ctx, CROP_INFO_H);
+		right = left >> S5P_FIMV_SHARED_CROP_RIGHT_SHIFT;
+		left = left & S5P_FIMV_SHARED_CROP_LEFT_MASK;
+		top = s5p_mfc_read_info(ctx, CROP_INFO_V);
+		s5p_mfc_clock_off();
+		bottom = top >> S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT;
+		top = top & S5P_FIMV_SHARED_CROP_TOP_MASK;
+		cr->c.left = left;
+		cr->c.top = top;
+		cr->c.width = ctx->img_width - left - right;
+		cr->c.height = ctx->img_height - top - bottom;
+		mfc_debug(2, "Cropping info [h264]: l=%d t=%d "
+			"w=%d h=%d (r=%d b=%d fw=%d fh=%d\n", left, top,
+			cr->c.width, cr->c.height, right, bottom,
+			ctx->buf_width, ctx->buf_height);
+	} else {
+		cr->c.left = 0;
+		cr->c.top = 0;
+		cr->c.width = ctx->img_width;
+		cr->c.height = ctx->img_height;
+		mfc_debug(2, "Cropping info: w=%d h=%d fw=%d "
+			"fh=%d\n", cr->c.width,	cr->c.height, ctx->buf_width,
+							ctx->buf_height);
+	}
+	mfc_debug_leave();
+	return 0;
+}
+
+static int vidioc_g_ext_ctrls(struct file *file, void *priv,
+			struct v4l2_ext_controls *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct v4l2_ext_control *ext_ctrl;
+	struct v4l2_control ctrl;
+	int i;
+	int ret = 0;
+
+	if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+		return -EINVAL;
+
+	for (i = 0; i < f->count; i++) {
+		ext_ctrl = (f->controls + i);
+
+		ctrl.id = ext_ctrl->id;
+
+		ret = get_ctrl_val(ctx, &ctrl);
+		if (ret == 0) {
+			ext_ctrl->value = ctrl.value;
+		} else {
+			f->error_idx = i;
+			break;
+		}
+
+		mfc_debug(2, "[%d] id: 0x%08x, value: %d", i, ext_ctrl->id, ext_ctrl->value);
+	}
+
+	return ret;
+}
+
+/* v4l2_ioctl_ops */
+static const struct v4l2_ioctl_ops s5p_mfc_dec_ioctl_ops = {
+	.vidioc_querycap = vidioc_querycap,
+	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
+	.vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
+	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
+	.vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane,
+	.vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
+	.vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
+	.vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
+	.vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
+	.vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
+	.vidioc_reqbufs = vidioc_reqbufs,
+	.vidioc_querybuf = vidioc_querybuf,
+	.vidioc_qbuf = vidioc_qbuf,
+	.vidioc_dqbuf = vidioc_dqbuf,
+	.vidioc_streamon = vidioc_streamon,
+	.vidioc_streamoff = vidioc_streamoff,
+	.vidioc_queryctrl = vidioc_queryctrl,
+	.vidioc_g_ctrl = vidioc_g_ctrl,
+	.vidioc_s_ctrl = vidioc_s_ctrl,
+	.vidioc_g_crop = vidioc_g_crop,
+	.vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
+};
+
+static int s5p_mfc_queue_setup(struct vb2_queue *vq, unsigned int *buf_count,
+			       unsigned int *plane_count, unsigned long psize[],
+			       void *allocators[])
+{
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+
+	mfc_debug_enter();
+
+	/* Video output for decoding (source)
+	 * this can be set after getting an instance */
+	if (ctx->state == MFCINST_GOT_INST &&
+	    vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		mfc_debug(2, "setting for VIDEO output\n");
+		/* A single plane is required for input */
+		*plane_count = 1;
+		if (*buf_count < 1)
+			*buf_count = 1;
+		if (*buf_count > MFC_MAX_BUFFERS)
+			*buf_count = MFC_MAX_BUFFERS;
+	/* Video capture for decoding (destination)
+	 * this can be set after the header was parsed */
+	} else if (ctx->state == MFCINST_HEAD_PARSED &&
+		   vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		mfc_debug(2, "setting for VIDEO capture\n");
+		/* Output plane count is 2 - one for Y and one for CbCr */
+		*plane_count = 2;
+		/* Setup buffer count */
+		if (*buf_count < ctx->dpb_count)
+			*buf_count = ctx->dpb_count;
+		if (*buf_count > ctx->dpb_count + MFC_MAX_EXTRA_DPB)
+			*buf_count = ctx->dpb_count + MFC_MAX_EXTRA_DPB;
+		if (*buf_count > MFC_MAX_BUFFERS)
+			*buf_count = MFC_MAX_BUFFERS;
+	} else {
+		mfc_err("State seems invalid. State = %d, vq->type = %d\n",
+							ctx->state, vq->type);
+		return -EINVAL;
+	}
+	mfc_debug(2, "%s, buffer count=%d, plane count=%d type=0x%x\n", __func__,
+					*buf_count, *plane_count, vq->type);
+
+	if (ctx->state == MFCINST_HEAD_PARSED &&
+	    vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		psize[0] = ctx->luma_size;
+		psize[1] = ctx->chroma_size;
+
+		if (IS_MFCV6(dev))
+			allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+		else
+			allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX];
+		allocators[1] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+		   ctx->state == MFCINST_GOT_INST) {
+		psize[0] = dec->src_buf_size;
+		allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+	} else {
+		mfc_err("Currently only decoding is supported. Decoding not initalised.\n");
+		return -EINVAL;
+	}
+
+	mfc_debug(2, "%s, plane=0, size=%lu\n", __func__, psize[0]);
+	mfc_debug(2, "%s, plane=1, size=%lu\n", __func__, psize[1]);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static void s5p_mfc_unlock(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mutex_unlock(&dev->mfc_mutex);
+}
+
+static void s5p_mfc_lock(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mutex_lock(&dev->mfc_mutex);
+}
+
+static int s5p_mfc_buf_init(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb);
+	int i;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (ctx->capture_state == QUEUE_BUFS_MMAPED) {
+			mfc_debug_leave();
+			return 0;
+		}
+		for (i = 0; i <= ctx->src_fmt->num_planes ; i++) {
+			if (mfc_plane_cookie(vb, i) == 0) {
+				mfc_err("Plane mem not allocated.\n");
+				return -EINVAL;
+			}
+		}
+
+		buf->cookie.raw.luma = mfc_plane_cookie(vb, 0);
+		buf->cookie.raw.chroma = mfc_plane_cookie(vb, 1);
+
+		list_add_tail(&buf->list, &dec->dpb_queue);
+		dec->dpb_queue_cnt++;
+
+		if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_DST, vb->v4l2_buf.index) < 0)
+			mfc_err("failed in init_buf_ctrls\n");
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (mfc_plane_cookie(vb, 0)  == 0) {
+			mfc_err("Plane memory not allocated.\n");
+			return -EINVAL;
+		}
+		buf->cookie.stream = mfc_plane_cookie(vb, 0);
+
+		if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, vb->v4l2_buf.index) < 0)
+			mfc_err("failed in init_buf_ctrls\n");
+	} else {
+		mfc_err("s5p_mfc_buf_init: unknown queue type.\n");
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned int index = vb->v4l2_buf.index;
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (vb2_plane_size(vb, 0) < ctx->luma_size ||
+			vb2_plane_size(vb, 1) < ctx->chroma_size) {
+			mfc_err("Plane buffer (CAPTURE) is too small.\n");
+			return -EINVAL;
+		}
+		mfc_debug(2, "Size: 0=%lu 2=%lu\n", vb2_plane_size(vb, 0),
+							vb2_plane_size(vb, 1));
+		if (ctx->cacheable & MFCMASK_DST_CACHE)
+			s5p_mfc_mem_cache_flush(vb, 2);
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (ctx->cacheable & MFCMASK_SRC_CACHE)
+			s5p_mfc_mem_cache_flush(vb, 1);
+		mfc_debug(2, "Plane size: %ld, ctx->dec_src_buf_size: %d\n",
+				vb2_plane_size(vb, 0), dec->src_buf_size);
+		if (vb2_plane_size(vb, 0) < dec->src_buf_size) {
+			mfc_err("Plane buffer (OUTPUT) is too small.\n");
+			return -EINVAL;
+		}
+		if (call_cop(ctx, to_buf_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in to_buf_ctrls\n");
+	}
+	return 0;
+}
+
+static int s5p_mfc_buf_finish(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	unsigned int index = vb->v4l2_buf.index;
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (ctx->cacheable & MFCMASK_DST_CACHE)
+			s5p_mfc_mem_cache_flush(vb, 2);
+		if (call_cop(ctx, to_ctx_ctrls, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in to_buf_ctrls\n");
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (call_cop(ctx, to_ctx_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in to_buf_ctrls\n");
+		#if 0
+		/* if there are not-handled mfc_ctrl, remove all */
+		while (!list_empty(&ctx->src_ctrls[index])) {
+			mfc_ctrl = list_entry((&ctx->src_ctrls[index])->next,
+					      struct s5p_mfc_ctrl, list);
+			mfc_debug(2, "not handled ctrl id: 0x%08x val: %d\n",
+				  mfc_ctrl->id, mfc_ctrl->val);
+			list_del(&mfc_ctrl->list);
+			kfree(mfc_ctrl);
+		}
+		#endif
+	}
+
+	return 0;
+}
+
+static void s5p_mfc_buf_cleanup(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	unsigned int index = vb->v4l2_buf.index;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (call_cop(ctx, cleanup_buf_ctrls, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in cleanup_buf_ctrls\n");
+		ctx->dst_ctrls_flag[index] = 0;
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (call_cop(ctx, cleanup_buf_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in cleanup_buf_ctrls\n");
+		ctx->src_ctrls_flag[index] = 0;
+	} else {
+		mfc_err("s5p_mfc_buf_cleanup: unknown queue type.\n");
+	}
+
+	mfc_debug_leave();
+}
+
+static int s5p_mfc_start_streaming(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+
+	if (ctx->state == MFCINST_FINISHING || ctx->state == MFCINST_FINISHED)
+		ctx->state = MFCINST_RUNNING;
+
+	/* If context is ready then dev = work->data;schedule it to run */
+	if (s5p_mfc_ctx_ready(ctx)) {
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+	}
+
+	s5p_mfc_try_run(dev);
+
+	return 0;
+}
+
+static int s5p_mfc_stop_streaming(struct vb2_queue *q)
+{
+	unsigned long flags;
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int aborted = 0;
+
+	if ((ctx->state == MFCINST_FINISHING ||
+		ctx->state ==  MFCINST_RUNNING) &&
+		(dev->curr_ctx == ctx->num) && test_bit(0, &dev->hw_lock)) {
+		ctx->state = MFCINST_ABORT;
+		s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_FRAME_DONE_RET,
+					  0);
+		aborted = 1;
+	}
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
+		INIT_LIST_HEAD(&ctx->dst_queue);
+		ctx->dst_queue_cnt = 0;
+		dec->dpb_flush = 1;
+		dec->dpb_status = 0;
+
+		INIT_LIST_HEAD(&dec->dpb_queue);
+		dec->dpb_queue_cnt = 0;
+	}
+
+	if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
+		INIT_LIST_HEAD(&ctx->src_queue);
+		ctx->src_queue_cnt = 0;
+	}
+
+	if (aborted)
+		ctx->state = MFCINST_RUNNING;
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	return 0;
+}
+
+
+static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned long flags;
+	struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb);
+	struct s5p_mfc_buf *dpb_buf, *tmp_buf;
+	int wait_flag = 0;
+	int remove_flag = 0;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		buf->used = 0;
+		mfc_debug(2, "Src queue: %p\n", &ctx->src_queue);
+		mfc_debug(2, "Adding to src: %p (%08lx, %08x)\n", vb,
+				mfc_plane_cookie(vb, 0),
+				buf->cookie.stream);
+		spin_lock_irqsave(&dev->irqlock, flags);
+		list_add_tail(&buf->list, &ctx->src_queue);
+		ctx->src_queue_cnt++;
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+
+#ifdef STREAM_SAVE
+		vb2_save_buf(vb, 0);
+#endif
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		buf->used = 0;
+		mfc_debug(2, "Dst queue: %p\n", &ctx->dst_queue);
+		mfc_debug(2, "Adding to dst: %p (%lx)\n", vb,
+						  mfc_plane_cookie(vb, 0));
+		mfc_debug(2, "ADDING Flag before: %lx (%d)\n",
+					dec->dpb_status, vb->v4l2_buf.index);
+		/* Mark destination as available for use by MFC */
+		spin_lock_irqsave(&dev->irqlock, flags);
+		if (!list_empty(&dec->dpb_queue)) {
+			remove_flag = 0;
+			list_for_each_entry_safe(dpb_buf, tmp_buf, &dec->dpb_queue, list) {
+				if (dpb_buf == buf) {
+					list_del(&dpb_buf->list);
+					remove_flag = 1;
+					break;
+				}
+			}
+			if (remove_flag == 0) {
+				mfc_err("Can't find buf(0x%x)\n", buf->cookie.raw.luma);
+				spin_unlock_irqrestore(&dev->irqlock, flags);
+				return;
+			}
+		}
+		set_bit(vb->v4l2_buf.index, &dec->dpb_status);
+		mfc_debug(2, "ADDING Flag after: %lx\n", dec->dpb_status);
+		list_add_tail(&buf->list, &ctx->dst_queue);
+		ctx->dst_queue_cnt++;
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		if (dec->dst_memtype == V4L2_MEMORY_USERPTR &&
+				ctx->dst_queue_cnt == dec->total_dpb_count)
+			ctx->capture_state = QUEUE_BUFS_MMAPED;
+	} else {
+		mfc_err("Unsupported buffer type (%d)\n", vq->type);
+	}
+
+	if (s5p_mfc_ctx_ready(ctx)) {
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+		if (ctx->state == MFCINST_HEAD_PARSED)
+			wait_flag = 1;
+	}
+	s5p_mfc_try_run(dev);
+	if (wait_flag) {
+		s5p_mfc_wait_for_done_ctx(ctx,
+				S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET, 1);
+	}
+
+	mfc_debug_leave();
+}
+
+static struct vb2_ops s5p_mfc_dec_qops = {
+	.queue_setup	= s5p_mfc_queue_setup,
+	.wait_prepare	= s5p_mfc_unlock,
+	.wait_finish	= s5p_mfc_lock,
+	.buf_init	= s5p_mfc_buf_init,
+	.buf_prepare	= s5p_mfc_buf_prepare,
+	.buf_finish	= s5p_mfc_buf_finish,
+	.buf_cleanup	= s5p_mfc_buf_cleanup,
+	.start_streaming= s5p_mfc_start_streaming,
+	.stop_streaming = s5p_mfc_stop_streaming,
+	.buf_queue	= s5p_mfc_buf_queue,
+};
+
+const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void)
+{
+	return &s5p_mfc_dec_ioctl_ops;
+}
+
+int s5p_mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dec *dec;
+	int i;
+	int ret = 0;
+
+	dec = kzalloc(sizeof(struct s5p_mfc_dec), GFP_KERNEL);
+	if (!dec) {
+		mfc_err("failed to allocate decoder private data\n");
+		return -ENOMEM;
+	}
+	ctx->dec_priv = dec;
+
+	ctx->inst_no = MFC_NO_INSTANCE_SET;
+
+	INIT_LIST_HEAD(&ctx->src_queue);
+	INIT_LIST_HEAD(&ctx->dst_queue);
+	ctx->src_queue_cnt = 0;
+	ctx->dst_queue_cnt = 0;
+
+	for (i = 0; i < MFC_MAX_BUFFERS; i++) {
+		ctx->src_ctrls_flag[i] = 0;
+		ctx->dst_ctrls_flag[i] = 0;
+	}
+
+	ctx->capture_state = QUEUE_FREE;
+	ctx->output_state = QUEUE_FREE;
+
+	ctx->state = MFCINST_INIT;
+	ctx->type = MFCINST_DECODER;
+	ctx->c_ops = &decoder_codec_ops;
+	ctx->src_fmt = &formats[DEF_SRC_FMT];
+	ctx->dst_fmt = &formats[DEF_DST_FMT];
+
+	INIT_LIST_HEAD(&dec->dpb_queue);
+	dec->dpb_queue_cnt = 0;
+
+	dec->display_delay = -1;
+	dec->is_packedpb = 0;
+
+	/* Init videobuf2 queue for OUTPUT */
+	ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	ctx->vq_src.drv_priv = ctx;
+	ctx->vq_src.buf_struct_size = sizeof(struct s5p_mfc_buf);
+	ctx->vq_src.io_modes = VB2_MMAP | VB2_USERPTR;
+	ctx->vq_src.ops = &s5p_mfc_dec_qops;
+	ctx->vq_src.mem_ops = s5p_mfc_mem_ops();
+	ret = vb2_queue_init(&ctx->vq_src);
+	if (ret) {
+		mfc_err("Failed to initialize videobuf2 queue(output)\n");
+		return ret;
+	}
+	/* Init videobuf2 queue for CAPTURE */
+	ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	ctx->vq_dst.drv_priv = ctx;
+	ctx->vq_dst.buf_struct_size = sizeof(struct s5p_mfc_buf);
+	ctx->vq_dst.io_modes = VB2_MMAP | VB2_USERPTR;
+	ctx->vq_dst.ops = &s5p_mfc_dec_qops;
+	ctx->vq_dst.mem_ops = s5p_mfc_mem_ops();
+	ret = vb2_queue_init(&ctx->vq_dst);
+	if (ret) {
+		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
+		return ret;
+	}
+
+	/* For MFC 6.x */
+	dec->remained = 0;
+
+	return ret;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_dec.h b/drivers/media/video/s5p-mfc/s5p_mfc_dec.h
new file mode 100644
index 0000000..f03346e
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_dec.h
@@ -0,0 +1,21 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_dec.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_DEC_H_
+#define __S5P_MFC_DEC_H_ __FILE__
+
+#define MAX_FRAME_SIZE		(2*1024*1024)
+
+const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void);
+int s5p_mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx);
+
+#endif /* __S5P_MFC_DEC_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_enc.c b/drivers/media/video/s5p-mfc/s5p_mfc_enc.c
new file mode 100644
index 0000000..c8292e5
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_enc.c
@@ -0,0 +1,3179 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_enc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <media/videobuf2-core.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_reg.h"
+#include "s5p_mfc_enc.h"
+#include "s5p_mfc_pm.h"
+
+#define DEF_SRC_FMT	1
+#define DEF_DST_FMT	2
+
+static struct s5p_mfc_fmt formats[] = {
+	{
+		.name = "4:2:0 2 Planes 16x16 Tiles",
+		.fourcc = V4L2_PIX_FMT_NV12MT_16X16,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes 64x32 Tiles",
+		.fourcc = V4L2_PIX_FMT_NV12MT,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes",
+		.fourcc = V4L2_PIX_FMT_NV12M,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "4:2:0 2 Planes Y/CrCb",
+		.fourcc = V4L2_PIX_FMT_NV21M,
+		.codec_mode = MFC_FORMATS_NO_CODEC,
+		.type = MFC_FMT_RAW,
+		.num_planes = 2,
+	},
+	{
+		.name = "H264 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H264,
+		.codec_mode = S5P_FIMV_CODEC_H264_ENC,
+		.type = MFC_FMT_ENC,
+		.num_planes = 1,
+	},
+	{
+		.name = "MPEG4 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_MPEG4,
+		.codec_mode = S5P_FIMV_CODEC_MPEG4_ENC,
+		.type = MFC_FMT_ENC,
+		.num_planes = 1,
+	},
+	{
+		.name = "H264 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H263,
+		.codec_mode = S5P_FIMV_CODEC_H263_ENC,
+		.type = MFC_FMT_ENC,
+		.num_planes = 1,
+	},
+};
+
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct s5p_mfc_fmt *find_format(struct v4l2_format *f, unsigned int t)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat &&
+		    formats[i].type == t)
+			return (struct s5p_mfc_fmt *)&formats[i];
+	}
+
+	return NULL;
+}
+
+static struct v4l2_queryctrl controls[] = {
+	{
+		.id = V4L2_CID_CACHEABLE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Cacheable flag",
+		.minimum = 0,
+		.maximum = 3,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The period of intra frame",
+		.minimum = 0,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The slice partitioning method",
+		.minimum = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
+		.maximum = V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The number of MB in a slice",
+		.minimum = 1,
+		.maximum = ENC_MULTI_SLICE_MB_MAX,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The maximum bits per slices",
+		.minimum = ENC_MULTI_SLICE_BYTE_MIN,
+		.maximum = (1 << 30) - 1,
+		.step = 1,
+		.default_value = ENC_MULTI_SLICE_BYTE_MIN,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The number of intra refresh MBs",
+		.minimum = 0,
+		.maximum = ENC_INTRA_REFRESH_MB_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Padding control enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Padding Color YUV Value",
+		.minimum = 0,
+		.maximum = (1 << 25) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Frame level rate control enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_BITRATE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Target bit rate rate-control",
+		.minimum = 1,
+		.maximum = (1 << 30) - 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Rate control reaction coeff.",
+		.minimum = 1,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_STREAM_SIZE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Encoded stream size",
+		.minimum = 0,
+		.maximum = (1 << 30) - 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_COUNT,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Encoded frame count",
+		.minimum = 0,
+		.maximum = (1 << 30) - 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Encoded frame type",
+		.minimum = 0,
+		.maximum = 5,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Force frame type",
+		.minimum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
+		.maximum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED,
+		.step = 1,
+		.default_value = \
+			V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_VBV_SIZE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "VBV buffer size (1Kbits)",
+		.minimum = 0,
+		.maximum = ENC_VBV_BUF_SIZE_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEADER_MODE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Sequence header mode",
+		.minimum = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
+		.maximum = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Frame skip enable",
+		.minimum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
+		.maximum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
+		.step = 1,
+		.default_value = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED,
+	},
+	{	/* MFC5.x Only */
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Fixed target bit enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{	/* MFC6.x Only for H.264 & H.263 */
+		.id = V4L2_CID_MPEG_MFC6X_VIDEO_FRAME_DELTA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 frame delta",
+		.minimum = 1,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The number of B frames",
+		.minimum = 0,
+		.maximum = 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 profile",
+		.minimum = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+		.maximum = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 level",
+		.minimum = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+		.maximum = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 interlace mode",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 loop filter mode",
+		.minimum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
+		.maximum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_S_B,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 loop filter alpha offset",
+		.minimum = ENC_H264_LOOP_FILTER_AB_MIN,
+		.maximum = ENC_H264_LOOP_FILTER_AB_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 loop filter beta offset",
+		.minimum = ENC_H264_LOOP_FILTER_AB_MIN,
+		.maximum = ENC_H264_LOOP_FILTER_AB_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 entorpy mode",
+		.minimum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+		.maximum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "The number of ref. picture of P",
+		.minimum = 1,
+		.maximum = 2,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 8x8 transform enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "MB level rate control",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 Frame rate",
+		.minimum = 1,
+		.maximum = ENC_H264_RC_FRAME_RATE_MAX,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 Frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 Minimum QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		/* MAX_QP must be greater than or equal to MIN_QP */
+		.id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 Maximum QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 dark region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 smooth region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 static region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "H264 MB activity adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 P frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 B frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Aspect ratio VUI enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "VUI aspect ratio IDC",
+		.minimum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED,
+		.maximum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Horizontal size of SAR",
+		.minimum = 0,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Vertical size of SAR",
+		.minimum = 0,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "GOP closure",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H264 I period",
+		.minimum = 0,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Hierarchical Coding",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Type",
+		.minimum = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B,
+		.maximum = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer",
+		.minimum = 0,
+		.maximum = 7,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer QP",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "frame pack sei generation flag",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Current frame is frame 0 flag",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Frame packing arrangement type",
+		.minimum = V4L2_MPEG_VIDEO_H264_SEI_FP_TYPE_SIDE_BY_SIDE,
+		.maximum = V4L2_MPEG_VIDEO_H264_SEI_FP_TYPE_TEMPORAL,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_SEI_FP_TYPE_SIDE_BY_SIDE,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Flexible Macroblock Order",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Map type for FMO",
+		.minimum = V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES,
+		.maximum = V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN,
+		.step = 1,
+		.default_value = \
+			V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Number of slice groups for FMO",
+		.minimum = 1,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "FMO Run Length",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Direction of the slice group",
+		.minimum = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT,
+		.maximum = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Size of the first slice group",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_ASO,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Arbitrary Slice Order",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "ASO Slice order",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 profile",
+		.minimum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
+		.maximum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 level",
+		.minimum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
+		.maximum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_5,
+		.step = 1,
+		.default_value = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 Frame QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 Minimum QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 Maximum QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{	/* MFC5.x Only */
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_QPEL,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Quarter pixel search enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 P frame QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 B frame QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_TIME_RES,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 vop time resolution",
+		.minimum = 0,
+		.maximum = ENC_MPEG4_VOP_TIME_RES_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_FRM_DELTA,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "MPEG4 frame delta",
+		.minimum = 1,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_H263_RC_FRAME_RATE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H263 Frame rate",
+		.minimum = 1,
+		.maximum = ENC_H263_RC_FRAME_RATE_MAX,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H263 Frame QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H263 Minimum QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H263 Maximum QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "H263 P frame QP value",
+		.minimum = 1,
+		.maximum = 31,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Frame Tag",
+		.minimum = 0,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+#if defined(CONFIG_S5P_MFC_VB2_ION)
+	{
+		.id		= V4L2_CID_SET_SHAREABLE,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "File descriptor for ION",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 1,
+	},
+#endif
+};
+
+#define NUM_CTRLS ARRAY_SIZE(controls)
+
+static struct v4l2_queryctrl *get_ctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < NUM_CTRLS; ++i)
+		if (id == controls[i].id)
+			return &controls[i];
+	return NULL;
+}
+
+static int check_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct v4l2_queryctrl *c;
+
+	c = get_ctrl(ctrl->id);
+	if (!c)
+		return -EINVAL;
+	if (ctrl->value < c->minimum || ctrl->value > c->maximum
+	    || (c->step != 0 && ctrl->value % c->step != 0)) {
+		v4l2_err(&dev->v4l2_dev, "Invalid control value\n");
+		return -ERANGE;
+	}
+	return 0;
+}
+
+static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = {
+	{	/* set frame tag */
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_SHARED_SET_E_FRAME_TAG,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{	/* get frame tag */
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_SHARED_GET_E_FRAME_TAG,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{	/* encoded y physical addr */
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_ENCODED_LUMA_ADDR,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{	/* encoded c physical addr */
+		.type = MFC_CTRL_TYPE_GET_DST,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR,
+		.is_volatile = 0,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_ENCODED_CHROMA_ADDR,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{	/* I, not coded frame insertion */
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_SFR,
+		.addr = S5P_FIMV_FRAME_INSERTION,
+		.mask = 0x3,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_NONE,
+		.flag_addr = 0,
+		.flag_shft = 0,
+	},
+	{	/* I period change */
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_NEW_I_PERIOD,
+		.mask = 0xFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_CUSTOM,
+		.flag_addr = S5P_FIMV_PARAM_CHANGE_FLAG,
+		.flag_shft = 0,
+	},
+	{	/* frame rate change */
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_NEW_RC_FRAME_RATE,
+		.mask = 0xFFFF,
+		.shft = 16,
+		.flag_mode = MFC_CTRL_MODE_CUSTOM,
+		.flag_addr = S5P_FIMV_PARAM_CHANGE_FLAG,
+		.flag_shft = 1,
+	},
+	{	/* bit rate change */
+		.type = MFC_CTRL_TYPE_SET,
+		.id = V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH,
+		.is_volatile = 1,
+		.mode = MFC_CTRL_MODE_CUSTOM,
+		.addr = S5P_FIMV_NEW_RC_BIT_RATE,
+		.mask = 0xFFFFFFFF,
+		.shft = 0,
+		.flag_mode = MFC_CTRL_MODE_CUSTOM,
+		.flag_addr = S5P_FIMV_PARAM_CHANGE_FLAG,
+		.flag_shft = 2,
+	},
+};
+
+#define NUM_CTRL_CFGS ARRAY_SIZE(mfc_ctrl_list)
+
+static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
+{
+	mfc_debug(2, "src=%d, dst=%d, state=%d\n",
+		  ctx->src_queue_cnt, ctx->dst_queue_cnt, ctx->state);
+
+	/* context is ready to make header */
+	if (ctx->state == MFCINST_GOT_INST && ctx->dst_queue_cnt >= 1)
+		return 1;
+	/* context is ready to allocate DPB */
+	if (ctx->dst_queue_cnt >= 1 && ctx->state == MFCINST_HEAD_PARSED)
+		return 1;
+	/* context is ready to encode a frame */
+	if (ctx->state == MFCINST_RUNNING &&
+		ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
+		return 1;
+	/* context is ready to encode a frame in case of B frame */
+	if (ctx->state == MFCINST_RUNNING_NO_OUTPUT &&
+		ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
+		return 1;
+	/* context is ready to encode remain frames */
+	if (ctx->state == MFCINST_FINISHING &&
+		ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
+		return 1;
+
+	mfc_debug(2, "ctx is not ready.\n");
+
+	return 0;
+}
+
+static int enc_init_ctx_ctrls(struct s5p_mfc_ctx *ctx)
+{
+	int i;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+
+	INIT_LIST_HEAD(&ctx->ctrls);
+
+	for (i = 0; i < NUM_CTRL_CFGS; i++) {
+		ctx_ctrl = kzalloc(sizeof(struct s5p_mfc_ctx_ctrl), GFP_KERNEL);
+		if (ctx_ctrl == NULL) {
+			mfc_err("failed to allocate ctx_ctrl type: %d, id: 0x%08x\n",
+				mfc_ctrl_list[i].type, mfc_ctrl_list[i].id);
+
+			return -ENOMEM;
+		}
+
+		ctx_ctrl->type = mfc_ctrl_list[i].type;
+		ctx_ctrl->id = mfc_ctrl_list[i].id;
+		ctx_ctrl->has_new = 0;
+		ctx_ctrl->val = 0;
+
+		list_add_tail(&ctx_ctrl->list, &ctx->ctrls);
+
+		mfc_debug(5, "add ctx ctrl id: 0x%08x\n", ctx_ctrl->id);
+	}
+
+	return 0;
+}
+
+static int enc_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+
+	while (!list_empty(&ctx->ctrls)) {
+		ctx_ctrl = list_entry((&ctx->ctrls)->next,
+				      struct s5p_mfc_ctx_ctrl, list);
+
+		mfc_debug(5, "del ctx ctrl id: 0x%08x\n", ctx_ctrl->id);
+
+		list_del(&ctx_ctrl->list);
+		kfree(ctx_ctrl);
+	}
+
+	INIT_LIST_HEAD(&ctx->ctrls);
+
+	return 0;
+}
+
+
+static int enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx,
+	enum s5p_mfc_ctrl_type type, unsigned int index)
+{
+	int i;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	struct list_head *head;
+
+	if ((type == MFC_CTRL_TYPE_SET) && (ctx->src_ctrls_flag[index])) {
+		mfc_debug(5, "ctx->src_ctrls[%d] is initialized\n", index);
+		return 0;
+	}
+	if ((type == MFC_CTRL_TYPE_GET_DST) && (ctx->dst_ctrls_flag[index])) {
+		mfc_debug(5, "ctx->dst_ctrls[%d] is initialized\n", index);
+		return 0;
+	}
+
+	if (type == MFC_CTRL_TYPE_SET) {
+		head = &ctx->src_ctrls[index];
+		ctx->src_ctrls_flag[index] = 1;
+	}
+	else if (type == MFC_CTRL_TYPE_GET_DST) {
+		head = &ctx->dst_ctrls[index];
+		ctx->dst_ctrls_flag[index] = 1;
+	}
+	else
+		return -EINVAL;
+
+	INIT_LIST_HEAD(head);
+
+	for (i = 0; i < NUM_CTRL_CFGS; i++) {
+		if (type != mfc_ctrl_list[i].type)
+			continue;
+
+		buf_ctrl = kzalloc(sizeof(struct s5p_mfc_buf_ctrl), GFP_KERNEL);
+		if (buf_ctrl == NULL) {
+			mfc_err("failed to allocate buf_ctrl type: %d, id: 0x%08x\n",
+				mfc_ctrl_list[i].type, mfc_ctrl_list[i].id);
+
+			return -ENOMEM;
+		}
+
+		buf_ctrl->id = mfc_ctrl_list[i].id;
+		buf_ctrl->has_new = 0;
+		buf_ctrl->val = 0;
+		buf_ctrl->old_val = 0;
+		buf_ctrl->is_volatile = mfc_ctrl_list[i].is_volatile;
+		buf_ctrl->mode = mfc_ctrl_list[i].mode;
+		buf_ctrl->addr = mfc_ctrl_list[i].addr;
+		buf_ctrl->mask = mfc_ctrl_list[i].mask;
+		buf_ctrl->shft = mfc_ctrl_list[i].shft;
+		buf_ctrl->flag_mode = mfc_ctrl_list[i].flag_mode;
+		buf_ctrl->flag_addr = mfc_ctrl_list[i].flag_addr;
+		buf_ctrl->flag_shft = mfc_ctrl_list[i].flag_shft;
+
+		list_add_tail(&buf_ctrl->list, head);
+
+		mfc_debug(5, "add buf ctrl id: 0x%08x\n", buf_ctrl->id);
+	}
+
+	return 0;
+}
+
+static int enc_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	while (!list_empty(head)) {
+		buf_ctrl = list_entry(head->next,
+				      struct s5p_mfc_buf_ctrl, list);
+
+		mfc_debug(5, "del buf ctrl id: 0x%08x\n",  buf_ctrl->id);
+
+		list_del(&buf_ctrl->list);
+		kfree(buf_ctrl);
+	}
+
+	INIT_LIST_HEAD(head);
+
+	return 0;
+}
+
+static int enc_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+		if ((ctx_ctrl->type != MFC_CTRL_TYPE_SET) || (!ctx_ctrl->has_new))
+			continue;
+
+		list_for_each_entry(buf_ctrl, head, list) {
+			if (buf_ctrl->id == ctx_ctrl->id) {
+				buf_ctrl->has_new = 1;
+				buf_ctrl->val = ctx_ctrl->val;
+				if (buf_ctrl->is_volatile)
+					buf_ctrl->updated = 0;
+
+				ctx_ctrl->has_new = 0;
+				break;
+			}
+		}
+	}
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (buf_ctrl->has_new)
+			mfc_debug(5, "id: 0x%08x val: %d\n",
+				 buf_ctrl->id, buf_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int enc_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (!buf_ctrl->has_new)
+			continue;
+
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if (ctx_ctrl->type != MFC_CTRL_TYPE_GET_DST)
+				continue;
+
+			if (ctx_ctrl->id == buf_ctrl->id) {
+				mfc_debug(!ctx_ctrl->has_new, "overwrite ctx ctrl value\n");
+
+				ctx_ctrl->has_new = 1;
+				ctx_ctrl->val = buf_ctrl->val;
+
+				buf_ctrl->has_new = 0;
+			}
+		}
+	}
+
+	list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+		if (ctx_ctrl->has_new)
+			mfc_debug(5, "id: 0x%08x val: %d\n",
+				  ctx_ctrl->id, ctx_ctrl->val);
+	}
+
+	return 0;
+}
+
+static int enc_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	mfc_debug_enter();
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (!buf_ctrl->has_new)
+			continue;
+
+		/* read old vlaue */
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		/* save old value for recovery */
+		if (buf_ctrl->is_volatile)
+			buf_ctrl->old_val = (value >> buf_ctrl->shft) & buf_ctrl->mask;
+
+		/* write new value */
+		value &= ~(buf_ctrl->mask << buf_ctrl->shft);
+		value |= ((buf_ctrl->val & buf_ctrl->mask) << buf_ctrl->shft);
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			s5p_mfc_write_reg(value, buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			s5p_mfc_write_info(ctx, value, buf_ctrl->addr);
+
+		/* set change flag bit */
+		if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) {
+			value = s5p_mfc_read_reg(buf_ctrl->flag_addr);
+			value |= (1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_reg(value, buf_ctrl->flag_addr);
+		} else if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SHM) {
+			value = s5p_mfc_read_info(ctx, buf_ctrl->flag_addr);
+			value |= (1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_info(ctx, value, buf_ctrl->flag_addr);
+		}
+
+		buf_ctrl->has_new = 0;
+		buf_ctrl->updated = 1;
+
+		mfc_debug(5, "id: 0x%08x val: %d\n", buf_ctrl->id,
+			  buf_ctrl->val);
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int enc_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		value = (value >> buf_ctrl->shft) & buf_ctrl->mask;
+
+		buf_ctrl->val = value;
+		buf_ctrl->has_new = 1;
+
+		mfc_debug(5, "id: 0x%08x val: %d\n", buf_ctrl->id,
+			  buf_ctrl->val);
+	}
+
+	return 0;
+}
+
+static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_buf *mb_entry;
+	unsigned long mb_y_addr, mb_c_addr;
+
+	/* move buffers in ref queue to src queue */
+	while (!list_empty(&enc->ref_queue)) {
+		mb_entry = list_entry((&enc->ref_queue)->next, struct s5p_mfc_buf, list);
+
+		mb_y_addr = mfc_plane_cookie(&mb_entry->vb, 0);
+		mb_c_addr = mfc_plane_cookie(&mb_entry->vb, 1);
+
+		mfc_debug(2, "enc ref y addr: 0x%08lx", mb_y_addr);
+		mfc_debug(2, "enc ref c addr: 0x%08lx", mb_c_addr);
+
+		list_del(&mb_entry->list);
+		enc->ref_queue_cnt--;
+
+		list_add_tail(&mb_entry->list, &ctx->src_queue);
+		ctx->src_queue_cnt++;
+	}
+
+	mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
+		  ctx->src_queue_cnt, enc->ref_queue_cnt);
+
+	INIT_LIST_HEAD(&enc->ref_queue);
+	enc->ref_queue_cnt = 0;
+}
+
+static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *dst_mb;
+	unsigned long dst_addr;
+	unsigned int dst_size;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	return 0;
+}
+
+static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_buf *dst_mb;
+	unsigned long flags;
+
+	mfc_debug(2, "seq header size: %d", s5p_mfc_get_enc_strm_size());
+
+	if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) {
+		spin_lock_irqsave(&dev->irqlock, flags);
+
+		dst_mb = list_entry(ctx->dst_queue.next,
+				struct s5p_mfc_buf, list);
+		list_del(&dst_mb->list);
+		ctx->dst_queue_cnt--;
+
+		vb2_set_plane_payload(&dst_mb->vb, 0, s5p_mfc_get_enc_strm_size());
+		vb2_buffer_done(&dst_mb->vb, VB2_BUF_STATE_DONE);
+
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+	}
+
+	if (IS_MFCV6(dev))
+		ctx->state = MFCINST_HEAD_PARSED; /* for INIT_BUFFER cmd */
+	else {
+		ctx->state = MFCINST_RUNNING;
+
+		if (s5p_mfc_ctx_ready(ctx)) {
+			spin_lock_irqsave(&dev->condlock, flags);
+			set_bit(ctx->num, &dev->ctx_work_bits);
+			spin_unlock_irqrestore(&dev->condlock, flags);
+		}
+		queue_work(dev->irq_workqueue, &dev->work_struct);
+	}
+	if (IS_MFCV6(dev))
+		ctx->dpb_count = s5p_mfc_get_enc_dpb_count();
+
+	return 0;
+}
+
+static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *dst_mb;
+	struct s5p_mfc_buf *src_mb;
+	unsigned long flags;
+	unsigned long src_y_addr, src_c_addr, dst_addr;
+	unsigned int dst_size;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	src_y_addr = mfc_plane_cookie(&src_mb->vb, 0);
+	src_c_addr = mfc_plane_cookie(&src_mb->vb, 1);
+	s5p_mfc_set_enc_frame_buffer(ctx, src_y_addr, src_c_addr);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	mfc_debug(2, "enc src y addr: 0x%08lx", src_y_addr);
+	mfc_debug(2, "enc src c addr: 0x%08lx", src_c_addr);
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	mfc_debug(2, "enc dst addr: 0x%08lx", dst_addr);
+
+	return 0;
+}
+
+static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_buf *mb_entry;
+	unsigned long enc_y_addr, enc_c_addr;
+	unsigned long mb_y_addr, mb_c_addr;
+	int slice_type;
+	unsigned int strm_size;
+	unsigned int pic_count;
+	unsigned long flags;
+	unsigned int index;
+
+	slice_type = s5p_mfc_get_enc_slice_type();
+	strm_size = s5p_mfc_get_enc_strm_size();
+	pic_count = s5p_mfc_get_enc_pic_count();
+
+	mfc_debug(2, "encoded slice type: %d", slice_type);
+	mfc_debug(2, "encoded stream size: %d", strm_size);
+	mfc_debug(2, "display order: %d", pic_count);
+
+	/* FIXME: set it to dest buffer not context */
+	/* set encoded frame type */
+	enc->frame_type = slice_type;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (slice_type >= 0) {
+		if (ctx->state == MFCINST_RUNNING_NO_OUTPUT)
+			ctx->state = MFCINST_RUNNING;
+
+		s5p_mfc_get_enc_frame_buffer(ctx, &enc_y_addr, &enc_c_addr);
+
+		mfc_debug(2, "encoded y addr: 0x%08lx", enc_y_addr);
+		mfc_debug(2, "encoded c addr: 0x%08lx", enc_c_addr);
+
+		list_for_each_entry(mb_entry, &ctx->src_queue, list) {
+			mb_y_addr = mfc_plane_cookie(&mb_entry->vb, 0);
+			mb_c_addr = mfc_plane_cookie(&mb_entry->vb, 1);
+
+			mfc_debug(2, "enc src y addr: 0x%08lx", mb_y_addr);
+			mfc_debug(2, "enc src c addr: 0x%08lx", mb_c_addr);
+
+			mb_entry = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+			index = mb_entry->vb.v4l2_buf.index;
+			if (call_cop(ctx, recover_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+				mfc_err("failed in recover_buf_ctrls_val\n");
+
+			if ((enc_y_addr == mb_y_addr) && (enc_c_addr == mb_c_addr)) {
+				list_del(&mb_entry->list);
+				ctx->src_queue_cnt--;
+
+				vb2_buffer_done(&mb_entry->vb, VB2_BUF_STATE_DONE);
+				break;
+			}
+		}
+
+		list_for_each_entry(mb_entry, &enc->ref_queue, list) {
+			mb_y_addr = mfc_plane_cookie(&mb_entry->vb, 0);
+			mb_c_addr = mfc_plane_cookie(&mb_entry->vb, 1);
+
+			mfc_debug(2, "enc ref y addr: 0x%08lx", mb_y_addr);
+			mfc_debug(2, "enc ref c addr: 0x%08lx", mb_c_addr);
+
+			if ((enc_y_addr == mb_y_addr) && (enc_c_addr == mb_c_addr)) {
+				list_del(&mb_entry->list);
+				enc->ref_queue_cnt--;
+
+				vb2_buffer_done(&mb_entry->vb, VB2_BUF_STATE_DONE);
+				break;
+			}
+		}
+	}
+
+	if ((ctx->src_queue_cnt > 0) &&
+		((ctx->state == MFCINST_RUNNING) ||
+		 (ctx->state == MFCINST_RUNNING_NO_OUTPUT))) {
+		mb_entry = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+
+		if (mb_entry->used) {
+			list_del(&mb_entry->list);
+			ctx->src_queue_cnt--;
+
+			list_add_tail(&mb_entry->list, &enc->ref_queue);
+			enc->ref_queue_cnt++;
+		}
+		/* FIXME: slice_type = 4 && strm_size = 0, skipped enable
+		   should be considered */
+		if ((slice_type == -1) && (strm_size == 0))
+			ctx->state = MFCINST_RUNNING_NO_OUTPUT;
+
+		mfc_debug(2, "slice_type: %d, ctx->state: %d \n", slice_type, ctx->state);
+		mfc_debug(2, "enc src count: %d, enc ref count: %d\n",
+			  ctx->src_queue_cnt, enc->ref_queue_cnt);
+	}
+
+	if (strm_size > 0) {
+		/* at least one more dest. buffers exist always  */
+		mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+
+		mb_entry->vb.v4l2_buf.flags &=
+			(V4L2_BUF_FLAG_KEYFRAME &
+			 V4L2_BUF_FLAG_PFRAME &
+			 V4L2_BUF_FLAG_BFRAME);
+
+		switch (slice_type) {
+		case S5P_FIMV_DECODE_FRAME_I_FRAME:
+			mb_entry->vb.v4l2_buf.flags |=
+				V4L2_BUF_FLAG_KEYFRAME;
+			break;
+		case S5P_FIMV_DECODE_FRAME_P_FRAME:
+			mb_entry->vb.v4l2_buf.flags |=
+				V4L2_BUF_FLAG_PFRAME;
+			break;
+		case S5P_FIMV_DECODE_FRAME_B_FRAME:
+			mb_entry->vb.v4l2_buf.flags |=
+				V4L2_BUF_FLAG_BFRAME;
+			break;
+		default:
+			mb_entry->vb.v4l2_buf.flags |=
+				V4L2_BUF_FLAG_KEYFRAME;
+			break;
+		}
+		mfc_debug(2, "Slice type : %d\n", mb_entry->vb.v4l2_buf.flags);
+
+		list_del(&mb_entry->list);
+		ctx->dst_queue_cnt--;
+		vb2_set_plane_payload(&mb_entry->vb, 0, strm_size);
+		vb2_buffer_done(&mb_entry->vb, VB2_BUF_STATE_DONE);
+
+		index = mb_entry->vb.v4l2_buf.index;
+		if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in get_buf_ctrls_val\n");
+	}
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	if ((ctx->src_queue_cnt == 0) || (ctx->dst_queue_cnt == 0))
+	/*
+		clear_work_bit(ctx);
+	*/
+	{
+		spin_lock(&dev->condlock);
+		clear_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock(&dev->condlock);
+	}
+
+	return 0;
+}
+
+static int enc_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head)
+{
+	struct s5p_mfc_buf_ctrl *buf_ctrl;
+	unsigned int value = 0;
+
+	list_for_each_entry(buf_ctrl, head, list) {
+		if ((!buf_ctrl->is_volatile) || (!buf_ctrl->updated))
+			continue;
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			value = s5p_mfc_read_reg(buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			value = s5p_mfc_read_info(ctx, buf_ctrl->addr);
+
+		value &= ~(buf_ctrl->mask << buf_ctrl->shft);
+		value |= ((buf_ctrl->old_val & buf_ctrl->mask) << buf_ctrl->shft);
+
+		if (buf_ctrl->mode == MFC_CTRL_MODE_SFR)
+			s5p_mfc_write_reg(value, buf_ctrl->addr);
+		else if (buf_ctrl->mode == MFC_CTRL_MODE_SHM)
+			s5p_mfc_write_info(ctx, value, buf_ctrl->addr);
+
+		/* clear change flag bit */
+		if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) {
+			value = s5p_mfc_read_reg(buf_ctrl->flag_addr);
+			value &= ~(1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_reg(value, buf_ctrl->flag_addr);
+		} else if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SHM) {
+			value = s5p_mfc_read_info(ctx, buf_ctrl->flag_addr);
+			value &= ~(1 << buf_ctrl->flag_shft);
+			s5p_mfc_write_info(ctx, value, buf_ctrl->flag_addr);
+		}
+
+		mfc_debug(5, "id: 0x%08x old_val: %d\n", buf_ctrl->id,
+			  buf_ctrl->old_val);
+	}
+
+	return 0;
+}
+
+static struct s5p_mfc_codec_ops encoder_codec_ops = {
+	.init_ctx_ctrls		= enc_init_ctx_ctrls,
+	.cleanup_ctx_ctrls	= enc_cleanup_ctx_ctrls,
+	.init_buf_ctrls		= enc_init_buf_ctrls,
+	.cleanup_buf_ctrls	= enc_cleanup_buf_ctrls,
+	.to_buf_ctrls		= enc_to_buf_ctrls,
+	.to_ctx_ctrls		= enc_to_ctx_ctrls,
+	.set_buf_ctrls_val	= enc_set_buf_ctrls_val,
+	.get_buf_ctrls_val	= enc_get_buf_ctrls_val,
+	.recover_buf_ctrls_val	= enc_recover_buf_ctrls_val,
+	.pre_seq_start		= enc_pre_seq_start,
+	.post_seq_start		= enc_post_seq_start,
+	.pre_frame_start	= enc_pre_frame_start,
+	.post_frame_start	= enc_post_frame_start,
+};
+
+/* Query capabilities of the device */
+static int vidioc_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+
+	strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE
+			  | V4L2_CAP_VIDEO_OUTPUT
+			  | V4L2_CAP_STREAMING;
+
+	return 0;
+}
+
+static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool mplane, bool out)
+{
+	struct s5p_mfc_fmt *fmt;
+	int i, j = 0;
+
+	for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+		if (mplane && formats[i].num_planes == 1)
+			continue;
+		else if (!mplane && formats[i].num_planes > 1)
+			continue;
+		if (out && formats[i].type != MFC_FMT_RAW)
+			continue;
+		else if (!out && formats[i].type != MFC_FMT_ENC)
+			continue;
+
+		if (j == f->index) {
+			fmt = &formats[i];
+			strlcpy(f->description, fmt->name,
+				sizeof(f->description));
+			f->pixelformat = fmt->fourcc;
+
+			return 0;
+		}
+
+		++j;
+	}
+
+	return -EINVAL;
+}
+
+static int vidioc_enum_fmt_vid_cap(struct file *file, void *pirv,
+				   struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, false, false);
+}
+
+static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv,
+					  struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, true, false);
+}
+
+static int vidioc_enum_fmt_vid_out(struct file *file, void *prov,
+				   struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, false, true);
+}
+
+static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov,
+					  struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt(f, true, true);
+}
+
+static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "f->type = %d ctx->state = %d\n", f->type, ctx->state);
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		/* This is run on output (encoder dest) */
+		pix_fmt_mp->width = 0;
+		pix_fmt_mp->height = 0;
+		pix_fmt_mp->field = V4L2_FIELD_NONE;
+		pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc;
+		pix_fmt_mp->num_planes = ctx->dst_fmt->num_planes;
+
+		pix_fmt_mp->plane_fmt[0].bytesperline = enc->dst_buf_size;
+		pix_fmt_mp->plane_fmt[0].sizeimage = enc->dst_buf_size;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		/* This is run on capture (encoder src) */
+		pix_fmt_mp->width = ctx->img_width;
+		pix_fmt_mp->height = ctx->img_height;
+		/* FIXME: interlace */
+		pix_fmt_mp->field = V4L2_FIELD_NONE;
+		pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc;
+		pix_fmt_mp->num_planes = ctx->src_fmt->num_planes;
+
+		pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+		pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
+		pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+		pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
+	} else {
+		mfc_err("invalid buf type\n");
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_fmt *fmt;
+	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		fmt = find_format(f, MFC_FMT_ENC);
+		if (!fmt) {
+			mfc_err("failed to try output format\n");
+			return -EINVAL;
+		}
+
+		if (pix_fmt_mp->plane_fmt[0].sizeimage == 0) {
+			mfc_err("must be set encoding output size\n");
+			return -EINVAL;
+		}
+
+		pix_fmt_mp->plane_fmt[0].bytesperline =
+			pix_fmt_mp->plane_fmt[0].sizeimage;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		fmt = find_format(f, MFC_FMT_RAW);
+		if (!fmt) {
+			mfc_err("failed to try output format\n");
+			return -EINVAL;
+		}
+
+		if (fmt->num_planes != pix_fmt_mp->num_planes) {
+			mfc_err("failed to try output format\n");
+			return -EINVAL;
+		}
+
+		/* FIXME: check below items */
+		/*
+		pix_fmt_mp->height;
+		pix_fmt_mp->width;
+
+		pix_fmt_mp->plane_fmt[0].bytesperline;  - buf_width
+		pix_fmt_mp->plane_fmt[0].sizeimage;	- luma
+		pix_fmt_mp->plane_fmt[1].bytesperline;  - buf_width
+		pix_fmt_mp->plane_fmt[1].sizeimage;	- chroma
+		*/
+	} else {
+		mfc_err("invalid buf type\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_fmt *fmt;
+	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
+	unsigned long flags;
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	ret = vidioc_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
+		v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
+		ret = -EBUSY;
+		goto out;
+	}
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		fmt = find_format(f, MFC_FMT_ENC);
+		if (!fmt) {
+			mfc_err("failed to set capture format\n");
+			return -EINVAL;
+		}
+		ctx->state = MFCINST_INIT;
+
+		ctx->dst_fmt = fmt;
+		ctx->codec_mode = ctx->dst_fmt->codec_mode;
+		mfc_debug(2, "codec number: %d\n", ctx->dst_fmt->codec_mode);
+
+		/* CHKME: 2KB aligned, multiple of 4KB - it may be ok with SDVMM */
+		enc->dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage;
+		pix_fmt_mp->plane_fmt[0].bytesperline = 0;
+
+		ctx->capture_state = QUEUE_FREE;
+
+		s5p_mfc_alloc_instance_buffer(ctx);
+
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+
+		s5p_mfc_clean_ctx_int_flags(ctx);
+		s5p_mfc_try_run(dev);
+		if (s5p_mfc_wait_for_done_ctx(ctx, \
+				S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET, 1)) {
+			/* Error or timeout */
+			mfc_err("Error getting instance from hardware.\n");
+			s5p_mfc_release_instance_buffer(ctx);
+			ret = -EIO;
+			goto out;
+		}
+		mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		fmt = find_format(f, MFC_FMT_RAW);
+		if (!fmt) {
+			mfc_err("failed to set output format\n");
+			return -EINVAL;
+		}
+		if (!IS_MFCV6(dev)) {
+			if (fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		} else if (IS_MFCV6(dev)) {
+			if (fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
+				mfc_err("Not supported format.\n");
+				return -EINVAL;
+			}
+		}
+
+		if (fmt->num_planes != pix_fmt_mp->num_planes) {
+			mfc_err("failed to set output format\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/* FIXME: Can be change source format in encoding? */
+		ctx->src_fmt = fmt;
+		ctx->img_width = pix_fmt_mp->width;
+		ctx->img_height = pix_fmt_mp->height;
+
+		mfc_debug(2, "codec number: %d\n", ctx->src_fmt->codec_mode);
+		mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n",
+			pix_fmt_mp->width, pix_fmt_mp->height,
+			ctx->img_width, ctx->img_height);
+
+		s5p_mfc_enc_calc_src_size(ctx);
+
+		ctx->output_state = QUEUE_FREE;
+
+		pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+		pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
+		pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+		pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
+	} else {
+		mfc_err("invalid buf type\n");
+		return -EINVAL;
+	}
+out:
+	mfc_debug_leave();
+	return ret;
+}
+
+static int vidioc_reqbufs(struct file *file, void *priv,
+					  struct v4l2_requestbuffers *reqbufs)
+{
+	struct s5p_mfc_dev *dev = video_drvdata(file);
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = 0;
+	int cacheable;
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "type: %d\n", reqbufs->memory);
+
+	/* if memory is not mmp or userptr return error */
+	if ((reqbufs->memory != V4L2_MEMORY_MMAP) &&
+		(reqbufs->memory != V4L2_MEMORY_USERPTR))
+		return -EINVAL;
+
+	if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		/* RMVME: s5p_mfc_buf_negotiate() ctx state checked */
+		/*
+		if (ctx->state != MFCINST_GOT_INST) {
+			mfc_err("invalid context state: %d\n", ctx->state);
+			return -EINVAL;
+		}
+		*/
+		/* FIXME: check it out in the MFC6.1 */
+		cacheable = (ctx->cacheable & MFCMASK_DST_CACHE) ? 1 : 0;
+		if (ctx->is_drm)
+			s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx_drm, cacheable);
+		else
+			s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+				cacheable);
+
+		if (ctx->capture_state != QUEUE_FREE) {
+			mfc_err("invalid capture state: %d\n", ctx->capture_state);
+			return -EINVAL;
+		}
+
+		ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+		if (ret != 0) {
+			mfc_err("error in vb2_reqbufs() for E(D)\n");
+			return ret;
+		}
+		ctx->capture_state = QUEUE_BUFS_REQUESTED;
+
+		if (!IS_MFCV6(dev)) {
+		ret = s5p_mfc_alloc_codec_buffers(ctx);
+			if (ret) {
+				mfc_err("Failed to allocate encoding buffers.\n");
+				reqbufs->count = 0;
+				ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
+				return -ENOMEM;
+			}
+		}
+	} else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		/* cacheable setting */
+		cacheable = (ctx->cacheable & MFCMASK_SRC_CACHE) ? 1 : 0;
+		if (ctx->is_drm) {
+			s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx_drm, cacheable);
+		} else {
+			if (!IS_MFCV6(dev))
+				s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX],
+					cacheable);
+			else
+				s5p_mfc_mem_set_cacheable(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+					cacheable);
+		}
+		if (ctx->output_state != QUEUE_FREE) {
+			mfc_err("invalid output state: %d\n", ctx->output_state);
+			return -EINVAL;
+		}
+
+		ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
+		if (ret != 0) {
+			mfc_err("error in vb2_reqbufs() for E(S)\n");
+			return ret;
+		}
+		ctx->output_state = QUEUE_BUFS_REQUESTED;
+	} else {
+		mfc_err("invalid buf type\n");
+		return -EINVAL;
+	}
+
+	mfc_debug(2, "--\n");
+
+	return ret;
+}
+
+static int vidioc_querybuf(struct file *file, void *priv,
+						   struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = 0;
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "type: %d\n", buf->memory);
+
+	/* if memory is not mmp or userptr return error */
+	if ((buf->memory != V4L2_MEMORY_MMAP) &&
+		(buf->memory != V4L2_MEMORY_USERPTR))
+		return -EINVAL;
+
+	mfc_debug(2, "state: %d, buf->type: %d\n", ctx->state, buf->type);
+
+	if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (ctx->state != MFCINST_GOT_INST) {
+			mfc_err("invalid context state: %d\n", ctx->state);
+			return -EINVAL;
+		}
+
+		/*
+		if (ctx->capture_state != QUEUE_BUFS_REQUESTED) {
+			mfc_err("invalid capture state: %d\n", ctx->capture_state);
+			return -EINVAL;
+		}
+		*/
+
+		ret = vb2_querybuf(&ctx->vq_dst, buf);
+		if (ret != 0) {
+			mfc_err("error in vb2_querybuf() for E(D)\n");
+			return ret;
+		}
+		buf->m.planes[0].m.mem_offset += DST_QUEUE_OFF_BASE;
+
+		/*
+		ctx->capture_state = QUEUE_BUFS_QUERIED;
+		*/
+	} else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		/* FIXME: check context state */
+		/*
+		if (ctx->output_state != QUEUE_BUFS_REQUESTED) {
+			mfc_err("invalid output state: %d\n", ctx->output_state);
+			return -EINVAL;
+		}
+		*/
+
+		ret = vb2_querybuf(&ctx->vq_src, buf);
+		if (ret != 0) {
+			mfc_err("error in vb2_querybuf() for E(S)\n");
+			return ret;
+		}
+
+		/*
+		ctx->output_state = QUEUE_BUFS_QUERIED;
+		*/
+	} else {
+		mfc_err("invalid buf type\n");
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+/* Queue a buffer */
+static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+
+	mfc_debug_enter();
+	mfc_debug(2, "Enqueued buf: %d (type = %d)\n", buf->index, buf->type);
+	if (ctx->state == MFCINST_ERROR) {
+		mfc_err("Call on QBUF after unrecoverable error.\n");
+		return -EIO;
+	}
+	if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		return vb2_qbuf(&ctx->vq_src, buf);
+	else
+		return vb2_qbuf(&ctx->vq_dst, buf);
+	mfc_debug_leave();
+	return -EINVAL;
+}
+
+/* Dequeue a buffer */
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret;
+
+	mfc_debug_enter();
+	mfc_debug(2, "Addr: %p %p %p Type: %d\n", &ctx->vq_src, buf, buf->m.planes,
+								buf->type);
+	if (ctx->state == MFCINST_ERROR) {
+		mfc_err("Call on DQBUF after unrecoverable error.\n");
+		return -EIO;
+	}
+	if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
+	else
+		ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Stream on */
+static int vidioc_streamon(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = -EINVAL;
+
+	mfc_debug_enter();
+	if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ret = vb2_streamon(&ctx->vq_src, type);
+	else
+		ret = vb2_streamon(&ctx->vq_dst, type);
+	mfc_debug(2, "ctx->src_queue_cnt = %d ctx->state = %d "
+		  "ctx->dst_queue_cnt = %d ctx->dpb_count = %d\n",
+		  ctx->src_queue_cnt, ctx->state, ctx->dst_queue_cnt,
+		  ctx->dpb_count);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Stream off, which equals to a pause */
+static int vidioc_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret;
+
+	mfc_debug_enter();
+	ret = -EINVAL;
+	if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ret = vb2_streamoff(&ctx->vq_src, type);
+	else
+		ret = vb2_streamoff(&ctx->vq_dst, type);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Query a ctrl */
+static int vidioc_queryctrl(struct file *file, void *priv,
+			    struct v4l2_queryctrl *qc)
+{
+	struct v4l2_queryctrl *c;
+
+	c = get_ctrl(qc->id);
+	if (!c)
+		return -EINVAL;
+	*qc = *c;
+	return 0;
+}
+
+static int get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	int ret = 0;
+	int check = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CACHEABLE:
+		ctrl->value = ctx->cacheable;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_STREAM_SIZE:
+		ctrl->value = enc->dst_buf_size;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_COUNT:
+		ctrl->value = enc->frame_count;
+		break;
+	/* FIXME: it doesn't need to return using GetConfig */
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE:
+		ctrl->value = enc->frame_type;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_CHECK_STATE:
+		if (ctx->state == MFCINST_RUNNING_NO_OUTPUT)
+			ctrl->value = MFCSTATE_ENC_NO_OUTPUT;
+		else
+			ctrl->value = MFCSTATE_PROCESSING;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG:
+	case V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR:
+	case V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR:
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if (ctx_ctrl->type != MFC_CTRL_TYPE_GET_DST)
+				continue;
+
+			if (ctx_ctrl->id == ctrl->id) {
+				if (ctx_ctrl->has_new) {
+					ctx_ctrl->has_new = 0;
+					ctrl->value = ctx_ctrl->val;
+				} else {
+					ctrl->value = 0;
+				}
+				check = 1;
+				break;
+			}
+		}
+		if (!check) {
+			v4l2_err(&dev->v4l2_dev, "invalid control 0x%08x\n", ctrl->id);
+			return -EINVAL;
+		}
+		break;
+	default:
+		v4l2_err(&dev->v4l2_dev, "Invalid control\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int vidioc_g_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = 0;
+
+	mfc_debug_enter();
+	ret = get_ctrl_val(ctx, ctrl);
+	mfc_debug_leave();
+
+	return ret;
+}
+
+static inline int h264_level(enum v4l2_mpeg_video_h264_level lvl)
+{
+	static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_4_2 + 1] = {
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_1_0   */ 10,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_1B    */ 9,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_1_1   */ 11,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_1_2   */ 12,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_1_3   */ 13,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_2_0   */ 20,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_2_1   */ 21,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_2_2   */ 22,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_3_0   */ 30,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_3_1   */ 31,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_3_2   */ 32,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_4_0   */ 40,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_4_1   */ 41,
+		/* V4L2_MPEG_VIDEO_H264_LEVEL_4_2   */ 42,
+	};
+	return t[lvl];
+}
+
+static inline int mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl)
+{
+	static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 + 1] = {
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0    */ 0,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B   */ 9,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_1    */ 1,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_2    */ 2,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3    */ 3,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B   */ 7,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_4    */ 4,
+		/* V4L2_MPEG_VIDEO_MPEG4_LEVEL_5    */ 5,
+	};
+	return t[lvl];
+}
+
+static inline int vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar)
+{
+	static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = {
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED     */ 0,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1             */ 1,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11           */ 2,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11           */ 3,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11           */ 4,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33           */ 5,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11           */ 6,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11           */ 7,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11           */ 8,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33           */ 9,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11           */ 10,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11           */ 11,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33           */ 12,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99          */ 13,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3             */ 14,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2             */ 15,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1             */ 16,
+		/* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED        */ 255,
+	};
+	return t[sar];
+}
+
+static int set_enc_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	int ret = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
+		p->gop_size = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
+		p->slice_mode = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
+		p->slice_mb = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
+		p->slice_bit = ctrl->value * 8;
+		break;
+	case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB:
+		p->intra_refresh_mb = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_PADDING:
+		p->pad = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV:
+		p->pad_luma = (ctrl->value >> 16) & 0xff;
+		p->pad_cb = (ctrl->value >> 8) & 0xff;
+		p->pad_cr = (ctrl->value >> 0) & 0xff;
+		break;
+	case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
+		p->rc_frame = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_BITRATE:
+		p->rc_bitrate = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF:
+		p->rc_reaction_coeff = ctrl->value;
+		break;
+	/* FIXME: why is it used ? */
+	case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
+		enc->force_frame_type = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_VBV_SIZE:
+		p->vbv_buf_size = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
+		p->seq_hdr_mode = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE:
+		p->frame_skip_mode = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT: /* MFC5.x Only */
+		p->fixed_target_bit = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_B_FRAMES:
+		p->num_b_frame = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
+		switch (ctrl->value) {
+		case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
+			p->codec.h264.profile =
+				S5P_FIMV_ENC_PROFILE_H264_MAIN;
+		break;
+		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
+			p->codec.h264.profile =
+				S5P_FIMV_ENC_PROFILE_H264_HIGH;
+			break;
+		case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
+			p->codec.h264.profile =
+				S5P_FIMV_ENC_PROFILE_H264_BASELINE;
+			break;
+		case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
+			if (IS_MFCV6(dev))
+				p->codec.h264.profile =
+				S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE;
+			else
+				ret = -EINVAL;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
+		p->codec.h264.level = h264_level(ctrl->value);
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE:
+		p->codec.h264.interlace = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
+		p->codec.h264.loop_filter_mode = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:
+		p->codec.h264.loop_filter_alpha = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:
+		p->codec.h264.loop_filter_beta = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
+		p->codec.h264.entropy_mode = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P:
+		p->codec.h264.num_ref_pic_4p = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM:
+		p->codec.h264._8x8_transform = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:
+		p->rc_mb = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE:
+		p->codec.h264.rc_framerate = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
+		p->codec.h264.rc_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
+		p->codec.h264.rc_min_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
+		p->codec.h264.rc_max_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK:
+		p->codec.h264.rc_mb_dark = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH:
+		p->codec.h264.rc_mb_smooth = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC:
+		p->codec.h264.rc_mb_static = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY:
+		p->codec.h264.rc_mb_activity = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
+		p->codec.h264.rc_p_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
+		p->codec.h264.rc_b_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE:
+		p->codec.h264.ar_vui = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC:
+		p->codec.h264.ar_vui_idc = vui_sar_idc(ctrl->value);
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH:
+		p->codec.h264.ext_sar_width = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT:
+		p->codec.h264.ext_sar_height = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE:
+		p->codec.h264.open_gop = ctrl->value ? 0 : 1;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
+		p->codec.h264.open_gop_size = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING:
+		p->codec.h264.hier_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE:
+		p->codec.h264.hier_qp_type = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER:
+		p->codec.h264.hier_qp_layer = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP:
+		p->codec.h264.hier_qp_layer_qp[(ctrl->value >> 16) & 0x7]
+			= ctrl->value & 0xFF;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING:
+		p->codec.h264.sei_gen_enable = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0:
+		p->codec.h264.sei_fp_curr_frame_0 = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE:
+		p->codec.h264.sei_fp_arrangement_type = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO:
+		p->codec.h264.fmo_enable = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE:
+		switch (ctrl->value) {
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
+			p->codec.h264.fmo_slice_map_type = ctrl->value;
+		break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP:
+		p->codec.h264.fmo_slice_num_grp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH:
+		p->codec.h264.fmo_run_length[ctrl->value >> 30]
+			= ctrl->value & 0x3FFFFFFF;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION:
+		p->codec.h264.fmo_sg_dir = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE:
+		p->codec.h264.fmo_sg_rate = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_ASO:
+		p->codec.h264.aso_enable = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER:
+		p->codec.h264.aso_slice_order[(ctrl->value >> 18) & 0x7]
+			&= ~(0xFF << (((ctrl->value >> 16) & 0x3) << 3));
+		p->codec.h264.aso_slice_order[(ctrl->value >> 18) & 0x7]
+			|= (ctrl->value & 0xFF) << \
+				(((ctrl->value >> 16) & 0x3) << 3);
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE:
+		switch (ctrl->value) {
+		case V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE:
+			p->codec.mpeg4.profile =
+				S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE;
+		break;
+		case V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE:
+			p->codec.mpeg4.profile =
+			S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE;
+		break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL:
+		p->codec.mpeg4.level = mpeg4_level(ctrl->value);
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
+		p->codec.mpeg4.rc_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP:
+		p->codec.mpeg4.rc_min_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP:
+		p->codec.mpeg4.rc_max_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_QPEL:
+		p->codec.mpeg4.quarter_pixel = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
+		p->codec.mpeg4.rc_p_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP:
+		p->codec.mpeg4.rc_b_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_TIME_RES:
+		p->codec.mpeg4.vop_time_res = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_FRM_DELTA:
+		p->codec.mpeg4.vop_frm_delta = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_H263_RC_FRAME_RATE:
+		p->codec.mpeg4.rc_framerate = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP:
+		p->codec.mpeg4.rc_frame_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H263_MIN_QP:
+		p->codec.mpeg4.rc_min_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H263_MAX_QP:
+		p->codec.mpeg4.rc_max_qp = ctrl->value;
+		break;
+	case V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP:
+		p->codec.mpeg4.rc_p_frame_qp = ctrl->value;
+		break;
+	default:
+		v4l2_err(&dev->v4l2_dev, "Invalid control\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl)
+{
+
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_ctx_ctrl *ctx_ctrl;
+	int ret = 0;
+	int check = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CACHEABLE:
+		ctx->cacheable |= ctrl->value;
+		break;
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG:
+	case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE:
+	case V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH:
+	case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH:
+	case V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH:
+		list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) {
+			if (ctx_ctrl->type != MFC_CTRL_TYPE_SET)
+				continue;
+			if (ctx_ctrl->id == ctrl->id) {
+				ctx_ctrl->has_new = 1;
+				ctx_ctrl->val = ctrl->value;
+				if (ctx_ctrl->id == \
+					V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH)
+					ctx_ctrl->val *= 1000;
+				check = 1;
+				break;
+			}
+		}
+		if (!check) {
+			v4l2_err(&dev->v4l2_dev,
+				"invalid control 0x%08x\n", ctrl->id);
+			return -EINVAL;
+		}
+		break;
+	default:
+		ret = set_enc_param(ctx, ctrl);
+		break;
+	}
+
+	return ret;
+}
+
+static int vidioc_s_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	int ret = 0;
+
+	mfc_debug_enter();
+	/*
+	int stream_on;
+	*/
+
+	/*
+	if (s5p_mfc_get_node_type(file) != MFCNODE_ENCODER)
+		return -EINVAL;
+	*/
+
+	/* FIXME:
+	stream_on = ctx->vq_src.streaming || ctx->vq_dst.streaming;
+	*/
+
+	ret = check_ctrl_val(ctx, ctrl);
+	if (ret != 0)
+		return ret;
+
+	ret = set_ctrl_val(ctx, ctrl);
+
+	mfc_debug_leave();
+
+	return ret;
+}
+
+static int vidioc_g_ext_ctrls(struct file *file, void *priv,
+			      struct v4l2_ext_controls *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct v4l2_ext_control *ext_ctrl;
+	struct v4l2_control ctrl;
+	int i;
+	int ret = 0;
+
+	/*
+	if (s5p_mfc_get_node_type(file) != MFCNODE_ENCODER)
+		return -EINVAL;
+	*/
+
+	if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+		return -EINVAL;
+
+	for (i = 0; i < f->count; i++) {
+		ext_ctrl = (f->controls + i);
+
+		ctrl.id = ext_ctrl->id;
+
+		ret = get_ctrl_val(ctx, &ctrl);
+		if (ret == 0) {
+			ext_ctrl->value = ctrl.value;
+		} else {
+			f->error_idx = i;
+			break;
+		}
+
+		mfc_debug(2, "[%d] id: 0x%08x, value: %d", i, ext_ctrl->id, ext_ctrl->value);
+	}
+
+	return ret;
+}
+
+static int vidioc_s_ext_ctrls(struct file *file, void *priv,
+				struct v4l2_ext_controls *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct v4l2_ext_control *ext_ctrl;
+	struct v4l2_control ctrl;
+	int i;
+	int ret = 0;
+
+	/*
+	if (s5p_mfc_get_node_type(file) != MFCNODE_ENCODER)
+		return -EINVAL;
+	*/
+
+	if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+		return -EINVAL;
+
+	for (i = 0; i < f->count; i++) {
+		ext_ctrl = (f->controls + i);
+
+		ctrl.id = ext_ctrl->id;
+		ctrl.value = ext_ctrl->value;
+
+		ret = check_ctrl_val(ctx, &ctrl);
+		if (ret != 0) {
+			f->error_idx = i;
+			break;
+		}
+
+		ret = set_enc_param(ctx, &ctrl);
+		if (ret != 0) {
+			f->error_idx = i;
+			break;
+		}
+
+		mfc_debug(2, "[%d] id: 0x%08x, value: %d", i, ext_ctrl->id, ext_ctrl->value);
+	}
+
+	return ret;
+}
+
+static int vidioc_try_ext_ctrls(struct file *file, void *priv,
+				struct v4l2_ext_controls *f)
+{
+	struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data);
+	struct v4l2_ext_control *ext_ctrl;
+	struct v4l2_control ctrl;
+	int i;
+	int ret = 0;
+
+	/*
+	if (s5p_mfc_get_node_type(file) != MFCNODE_ENCODER)
+		return -EINVAL;
+	*/
+
+	if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+		return -EINVAL;
+
+	for (i = 0; i < f->count; i++) {
+		ext_ctrl = (f->controls + i);
+
+		ctrl.id = ext_ctrl->id;
+		ctrl.value = ext_ctrl->value;
+
+		ret = check_ctrl_val(ctx, &ctrl);
+		if (ret != 0) {
+			f->error_idx = i;
+			break;
+		}
+
+		mfc_debug(2, "[%d] id: 0x%08x, value: %d", i, ext_ctrl->id, ext_ctrl->value);
+	}
+
+	return ret;
+}
+
+static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = {
+	.vidioc_querycap = vidioc_querycap,
+	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
+	.vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane,
+	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
+	.vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane,
+	.vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
+	.vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
+	.vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
+	.vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
+	.vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
+	.vidioc_reqbufs = vidioc_reqbufs,
+	.vidioc_querybuf = vidioc_querybuf,
+	.vidioc_qbuf = vidioc_qbuf,
+	.vidioc_dqbuf = vidioc_dqbuf,
+	.vidioc_streamon = vidioc_streamon,
+	.vidioc_streamoff = vidioc_streamoff,
+	.vidioc_queryctrl = vidioc_queryctrl,
+	.vidioc_g_ctrl = vidioc_g_ctrl,
+	.vidioc_s_ctrl = vidioc_s_ctrl,
+	.vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
+	.vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
+	.vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
+};
+
+static int check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb)
+{
+	int i;
+
+	if (!fmt)
+		return -EINVAL;
+
+	if (fmt->num_planes != vb->num_planes) {
+		mfc_err("invalid plane number for the format\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < fmt->num_planes; i++) {
+		if (!mfc_plane_cookie(vb, i)) {
+			mfc_err("failed to get plane cookie\n");
+			return -EINVAL;
+		}
+
+		mfc_debug(2, "index: %d, plane[%d] cookie: 0x%08lx",
+				vb->v4l2_buf.index, i,
+				mfc_plane_cookie(vb, i));
+	}
+
+	return 0;
+}
+
+static int s5p_mfc_queue_setup(struct vb2_queue *vq,
+			       unsigned int *buf_count, unsigned int *plane_count,
+			       unsigned long psize[], void *allocators[])
+{
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int i;
+
+	mfc_debug_enter();
+
+	if (ctx->state != MFCINST_GOT_INST &&
+	    vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		mfc_err("invalid state: %d\n", ctx->state);
+		return -EINVAL;
+	}
+	if (ctx->state >= MFCINST_FINISHING &&
+	    vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		mfc_err("invalid state: %d\n", ctx->state);
+		return -EINVAL;
+	}
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (ctx->dst_fmt)
+			*plane_count = ctx->dst_fmt->num_planes;
+		else
+			*plane_count = MFC_ENC_CAP_PLANE_COUNT;
+
+		if (*buf_count < 1)
+			*buf_count = 1;
+		if (*buf_count > MFC_MAX_BUFFERS)
+			*buf_count = MFC_MAX_BUFFERS;
+
+		psize[0] = enc->dst_buf_size;
+		allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (ctx->src_fmt)
+			*plane_count = ctx->src_fmt->num_planes;
+		else
+			*plane_count = MFC_ENC_OUT_PLANE_COUNT;
+
+		if (*buf_count < 1)
+			*buf_count = 1;
+		if (*buf_count > MFC_MAX_BUFFERS)
+			*buf_count = MFC_MAX_BUFFERS;
+
+		psize[0] = ctx->luma_size;
+		psize[1] = ctx->chroma_size;
+		if (IS_MFCV6(dev)) {
+			allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+			allocators[1] = ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+		}
+		else {
+			allocators[0] = ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX];
+			allocators[1] = ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX];
+		}
+
+	} else {
+		mfc_err("invalid queue type: %d\n", vq->type);
+		return -EINVAL;
+	}
+
+	mfc_debug(2, "buf_count: %d, plane_count: %d\n", *buf_count, *plane_count);
+	for (i = 0; i < *plane_count; i++)
+		mfc_debug(2, "plane[%d] size=%lu\n", i, psize[i]);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static void s5p_mfc_unlock(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mutex_unlock(&dev->mfc_mutex);
+}
+
+static void s5p_mfc_lock(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mutex_lock(&dev->mfc_mutex);
+}
+
+static int s5p_mfc_buf_init(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb);
+	int ret;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		ret = check_vb_with_fmt(ctx->dst_fmt, vb);
+		if (ret < 0)
+			return ret;
+
+		buf->cookie.stream = mfc_plane_cookie(vb, 0);
+
+		if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_GET_DST, vb->v4l2_buf.index) < 0)
+			mfc_err("failed in init_buf_ctrls\n");
+
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		ret = check_vb_with_fmt(ctx->src_fmt, vb);
+		if (ret < 0)
+			return ret;
+
+		buf->cookie.raw.luma = mfc_plane_cookie(vb, 0);
+		buf->cookie.raw.chroma = mfc_plane_cookie(vb, 1);
+
+		if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SET, vb->v4l2_buf.index) < 0)
+			mfc_err("failed in init_buf_ctrls\n");
+
+	} else {
+		mfc_err("inavlid queue type: %d\n", vq->type);
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	unsigned int index = vb->v4l2_buf.index;
+	int ret;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		ret = check_vb_with_fmt(ctx->dst_fmt, vb);
+		if (ret < 0)
+			return ret;
+
+		mfc_debug(2, "plane size: %ld, dst size: %d\n",
+			vb2_plane_size(vb, 0), enc->dst_buf_size);
+
+		if (vb2_plane_size(vb, 0) < enc->dst_buf_size) {
+			mfc_err("plane size is too small for capture\n");
+			return -EINVAL;
+		}
+		/* FIXME: 'cacheable' should be tested */
+		if (ctx->cacheable & MFCMASK_DST_CACHE)
+			s5p_mfc_mem_cache_flush(vb, 1);
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		ret = check_vb_with_fmt(ctx->src_fmt, vb);
+		if (ret < 0)
+			return ret;
+
+		mfc_debug(2, "plane size: %ld, luma size: %d\n",
+			vb2_plane_size(vb, 0), ctx->luma_size);
+		mfc_debug(2, "plane size: %ld, chroma size: %d\n",
+			vb2_plane_size(vb, 1), ctx->chroma_size);
+
+		if (vb2_plane_size(vb, 0) < ctx->luma_size ||
+		    vb2_plane_size(vb, 1) < ctx->chroma_size) {
+			mfc_err("plane size is too small for output\n");
+			return -EINVAL;
+		}
+
+		if (ctx->cacheable & MFCMASK_SRC_CACHE)
+			s5p_mfc_mem_cache_flush(vb, 2);
+		if (call_cop(ctx, to_buf_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in to_buf_ctrls\n");
+
+	} else {
+		mfc_err("inavlid queue type: %d\n", vq->type);
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_buf_finish(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	unsigned int index = vb->v4l2_buf.index;
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (call_cop(ctx, to_ctx_ctrls, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in to_ctx_ctrls\n");
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (call_cop(ctx, to_ctx_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+			mfc_err("failed in to_buf_ctrls\n");
+		#if 0
+		/* if there are not-handled mfc_ctrl, remove all */
+		while (!list_empty(&ctx->src_ctrls[index])) {
+			mfc_ctrl = list_entry((&ctx->src_ctrls[index])->next,
+					      struct s5p_mfc_ctrl, list);
+			mfc_debug(2, "not handled ctrl id: 0x%08x val: %d\n",
+				  mfc_ctrl->id, mfc_ctrl->val);
+			list_del(&mfc_ctrl->list);
+			kfree(mfc_ctrl);
+		}
+		#endif
+	}
+
+	return 0;
+}
+
+static void s5p_mfc_buf_cleanup(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	unsigned int index = vb->v4l2_buf.index;
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		if (call_cop(ctx, cleanup_buf_ctrls, ctx, &ctx->dst_ctrls[index]) < 0)
+			mfc_err("failed in cleanup_buf_ctrls\n");
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		if (ctx->src_ctrls_flag[index]) {
+			if (call_cop(ctx, cleanup_buf_ctrls, ctx, &ctx->src_ctrls[index]) < 0)
+				mfc_err("failed in cleanup_buf_ctrls\n");
+		}
+	} else {
+		mfc_err("s5p_mfc_buf_cleanup: unknown queue type.\n");
+	}
+
+	mfc_debug_leave();
+}
+
+static int s5p_mfc_start_streaming(struct vb2_queue *q)
+{
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+
+	/* If context is ready then dev = work->data;schedule it to run */
+	if (s5p_mfc_ctx_ready(ctx)) {
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+	}
+
+	s5p_mfc_try_run(dev);
+
+	return 0;
+}
+
+static int s5p_mfc_stop_streaming(struct vb2_queue *q)
+{
+	unsigned long flags;
+	struct s5p_mfc_ctx *ctx = q->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	if ((ctx->state == MFCINST_FINISHING ||
+		ctx->state ==  MFCINST_RUNNING) &&
+		(dev->curr_ctx == ctx->num) && test_bit(0, &dev->hw_lock)) {
+		ctx->state = MFCINST_ABORT;
+		s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_FRAME_DONE_RET,
+					  0);
+	}
+
+	ctx->state = MFCINST_FINISHED;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
+		INIT_LIST_HEAD(&ctx->dst_queue);
+		ctx->dst_queue_cnt = 0;
+	}
+
+	if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		cleanup_ref_queue(ctx);
+
+		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
+		INIT_LIST_HEAD(&ctx->src_queue);
+		ctx->src_queue_cnt = 0;
+	}
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	return 0;
+}
+
+static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct s5p_mfc_ctx *ctx = vq->drv_priv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb);
+
+	mfc_debug_enter();
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		buf->used = 0;
+		mfc_debug(2, "dst queue: %p\n", &ctx->dst_queue);
+		mfc_debug(2, "adding to dst: %p (%08lx, %08x)\n", vb,
+			mfc_plane_cookie(vb, 0),
+			buf->cookie.stream);
+
+		/* Mark destination as available for use by MFC */
+		spin_lock_irqsave(&dev->irqlock, flags);
+		list_add_tail(&buf->list, &ctx->dst_queue);
+		ctx->dst_queue_cnt++;
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		buf->used = 0;
+		mfc_debug(2, "src queue: %p\n", &ctx->src_queue);
+		mfc_debug(2, "adding to src: %p (%08lx, %08lx, %08x, %08x)\n", vb,
+			mfc_plane_cookie(vb, 0),
+			mfc_plane_cookie(vb, 1),
+			buf->cookie.raw.luma,
+			buf->cookie.raw.chroma);
+
+		spin_lock_irqsave(&dev->irqlock, flags);
+
+		if (vb->v4l2_planes[0].bytesused == 0) {
+			mfc_debug(1, "change state to FINISHING\n");
+			ctx->state = MFCINST_FINISHING;
+
+			vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+
+			cleanup_ref_queue(ctx);
+		} else {
+			list_add_tail(&buf->list, &ctx->src_queue);
+			ctx->src_queue_cnt++;
+		}
+
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+	} else {
+		mfc_err("unsupported buffer type (%d)\n", vq->type);
+	}
+
+	if (s5p_mfc_ctx_ready(ctx)) {
+		spin_lock_irqsave(&dev->condlock, flags);
+		set_bit(ctx->num, &dev->ctx_work_bits);
+		spin_unlock_irqrestore(&dev->condlock, flags);
+	}
+	s5p_mfc_try_run(dev);
+
+	mfc_debug_leave();
+}
+
+static struct vb2_ops s5p_mfc_enc_qops = {
+	.queue_setup	= s5p_mfc_queue_setup,
+	.wait_prepare	= s5p_mfc_unlock,
+	.wait_finish	= s5p_mfc_lock,
+	.buf_init	= s5p_mfc_buf_init,
+	.buf_prepare	= s5p_mfc_buf_prepare,
+	.buf_finish	= s5p_mfc_buf_finish,
+	.buf_cleanup	= s5p_mfc_buf_cleanup,
+	.start_streaming= s5p_mfc_start_streaming,
+	.stop_streaming = s5p_mfc_stop_streaming,
+	.buf_queue	= s5p_mfc_buf_queue,
+};
+
+const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void)
+{
+	return &s5p_mfc_enc_ioctl_ops;
+}
+
+int s5p_mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_enc *enc;
+	int ret = 0;
+
+	enc = kzalloc(sizeof(struct s5p_mfc_enc), GFP_KERNEL);
+	if (!enc) {
+		mfc_err("failed to allocate encoder private data\n");
+		return -ENOMEM;
+	}
+	ctx->enc_priv = enc;
+
+	ctx->inst_no = MFC_NO_INSTANCE_SET;
+
+	INIT_LIST_HEAD(&ctx->src_queue);
+	INIT_LIST_HEAD(&ctx->dst_queue);
+	ctx->src_queue_cnt = 0;
+	ctx->dst_queue_cnt = 0;
+
+	ctx->type = MFCINST_ENCODER;
+	ctx->c_ops = &encoder_codec_ops;
+	ctx->src_fmt = &formats[DEF_SRC_FMT];
+	ctx->dst_fmt = &formats[DEF_DST_FMT];
+
+	INIT_LIST_HEAD(&enc->ref_queue);
+	enc->ref_queue_cnt = 0;
+
+	/* Init videobuf2 queue for OUTPUT */
+	ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	ctx->vq_src.drv_priv = ctx;
+	ctx->vq_src.buf_struct_size = sizeof(struct s5p_mfc_buf);
+	ctx->vq_src.io_modes = VB2_MMAP | VB2_USERPTR;
+	ctx->vq_src.ops = &s5p_mfc_enc_qops;
+	ctx->vq_src.mem_ops = s5p_mfc_mem_ops();
+	ret = vb2_queue_init(&ctx->vq_src);
+	if (ret) {
+		mfc_err("Failed to initialize videobuf2 queue(output)\n");
+		return ret;
+	}
+
+	/* Init videobuf2 queue for CAPTURE */
+	ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	ctx->vq_dst.drv_priv = ctx;
+	ctx->vq_dst.buf_struct_size = sizeof(struct s5p_mfc_buf);
+	ctx->vq_dst.io_modes = VB2_MMAP | VB2_USERPTR;
+	ctx->vq_dst.ops = &s5p_mfc_enc_qops;
+	ctx->vq_dst.mem_ops = s5p_mfc_mem_ops();
+	ret = vb2_queue_init(&ctx->vq_dst);
+	if (ret) {
+		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_enc.h b/drivers/media/video/s5p-mfc/s5p_mfc_enc.h
new file mode 100644
index 0000000..c245b64
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_enc.h
@@ -0,0 +1,19 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_enc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_ENC_H_
+#define __S5P_MFC_ENC_H_ __FILE__
+
+const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void);
+int s5p_mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx);
+
+#endif /* __S5P_MFC_ENC_H_  */
\ No newline at end of file
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_inst.c b/drivers/media/video/s5p-mfc/s5p_mfc_inst.c
new file mode 100644
index 0000000..a34df74
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_inst.c
@@ -0,0 +1,52 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_inst.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "s5p_mfc_common.h"
+#include "s5p_mfc_cmd.h"
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_intr.h"
+
+int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int ret;
+
+	/* Preparing decoding - getting instance number */
+	mfc_debug(2, "Getting instance number\n");
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	ret = s5p_mfc_open_inst_cmd(ctx);
+	if (ret) {
+		mfc_err("Failed to create a new instance.\n");
+		ctx->state = MFCINST_ERROR;
+	}
+	return ret;
+}
+
+int s5p_mfc_close_inst(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int ret;
+
+	/* Closing decoding instance  */
+	mfc_debug(2, "Returning instance number\n");
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	ret = s5p_mfc_close_inst_cmd(ctx);
+	if (ret) {
+		mfc_err("Failed to return an instance.\n");
+		ctx->state = MFCINST_ERROR;
+		return ret;
+	}
+	return ret;
+}
+
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_inst.h b/drivers/media/video/s5p-mfc/s5p_mfc_inst.h
new file mode 100644
index 0000000..a547b31
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_inst.h
@@ -0,0 +1,19 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_inst.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_INST_H_
+#define __S5P_MFC_INST_H_ __FILE__
+
+int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_close_inst(struct s5p_mfc_ctx *ctx);
+
+#endif /* __S5P_MFC_INST_H_  */
\ No newline at end of file
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_intr.c b/drivers/media/video/s5p-mfc/s5p_mfc_intr.c
new file mode 100644
index 0000000..a74b580
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_intr.c
@@ -0,0 +1,95 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_intr.c
+ *
+ * C file for Samsung MFC (Multi Function Codec - FIMV) driver
+ * This file contains functions used to wait for command completion.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/io.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_debug.h"
+
+int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command)
+{
+	int ret;
+
+	ret = wait_event_interruptible_timeout(dev->queue,
+		(dev->int_cond && (dev->int_type == command
+		|| dev->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
+		msecs_to_jiffies(MFC_INT_TIMEOUT));
+	if (ret == 0) {
+		mfc_err("Interrupt (dev->int_type:%d, command:%d) timed out.\n",
+							dev->int_type, command);
+		return 1;
+	} else if (ret == -ERESTARTSYS) {
+		mfc_err("Interrupted by a signal.\n");
+		return 1;
+	}
+	mfc_debug(1, "Finished waiting (dev->int_type:%d, command: %d).\n",
+							dev->int_type, command);
+	/* RMVME: */
+	if (dev->int_type == S5P_FIMV_R2H_CMD_RSV_RET)
+		return 1;
+	return 0;
+}
+
+void s5p_mfc_clean_dev_int_flags(struct s5p_mfc_dev *dev)
+{
+	dev->int_cond = 0;
+	dev->int_type = 0;
+	dev->int_err = 0;
+}
+
+int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx,
+				    int command, int interrupt)
+{
+	int ret;
+
+	if (interrupt) {
+		ret = wait_event_interruptible_timeout(ctx->queue,
+				(ctx->int_cond && (ctx->int_type == command
+			|| ctx->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
+					msecs_to_jiffies(MFC_INT_TIMEOUT));
+	} else {
+		ret = wait_event_timeout(ctx->queue,
+				(ctx->int_cond && (ctx->int_type == command
+			|| ctx->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
+					msecs_to_jiffies(MFC_INT_TIMEOUT));
+	}
+	if (ret == 0) {
+		mfc_err("Interrupt (ctx->int_type:%d, command:%d) timed out.\n",
+							ctx->int_type, command);
+		return 1;
+	} else if (ret == -ERESTARTSYS) {
+		mfc_err("Interrupted by a signal.\n");
+		return 1;
+	}
+	mfc_debug(1, "Finished waiting (ctx->int_type:%d, command: %d).\n",
+							ctx->int_type, command);
+	/* RMVME: */
+	if (ctx->int_type == S5P_FIMV_R2H_CMD_RSV_RET)
+		return 1;
+	return 0;
+}
+
+void s5p_mfc_clean_ctx_int_flags(struct s5p_mfc_ctx *ctx)
+{
+	ctx->int_cond = 0;
+	ctx->int_type = 0;
+	ctx->int_err = 0;
+}
+
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_intr.h b/drivers/media/video/s5p-mfc/s5p_mfc_intr.h
new file mode 100644
index 0000000..8c531b6
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_intr.h
@@ -0,0 +1,26 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_intr.h
+ *
+ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver
+ * It contains waiting functions declarations.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _S5P_MFC_INTR_H_
+#define _S5P_MFC_INTR_H_
+
+#include "s5p_mfc_common.h"
+
+int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx,
+						int command, int interrupt);
+int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command);
+void s5p_mfc_clean_ctx_int_flags(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_clean_dev_int_flags(struct s5p_mfc_dev *dev);
+
+#endif /* _S5P_MFC_INTR_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_mem.c b/drivers/media/video/s5p-mfc/s5p_mfc_mem.c
new file mode 100644
index 0000000..71eda7a
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_mem.c
@@ -0,0 +1,398 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_mem.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/dma-mapping.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-memops.h>
+#include <asm/cacheflush.h>
+
+#include "s5p_mfc_common.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_pm.h"
+#include "s5p_mfc_debug.h"
+
+#define	MFC_ION_NAME	"s5p-mfc"
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+static const char *s5p_mem_types[] = {
+	MFC_CMA_FW,
+	MFC_CMA_BANK1,
+	MFC_CMA_BANK2,
+};
+
+static unsigned long s5p_mem_alignments[] = {
+	MFC_CMA_FW_ALIGN,
+	MFC_CMA_BANK1_ALIGN,
+	MFC_CMA_BANK2_ALIGN,
+};
+
+struct vb2_mem_ops *s5p_mfc_mem_ops(void)
+{
+	return (struct vb2_mem_ops *)&vb2_cma_phys_memops;
+}
+
+void **s5p_mfc_mem_init_multi(struct device *dev, unsigned int ctx_num)
+{
+/* TODO Cachable should be set */
+	return (void **)vb2_cma_phys_init_multi(dev, ctx_num,
+					   s5p_mem_types,
+					   s5p_mem_alignments,0);
+}
+
+void s5p_mfc_mem_cleanup_multi(void **alloc_ctxes, unsigned int ctx_num)
+{
+	vb2_cma_phys_cleanup_multi(alloc_ctxes);
+}
+#elif defined(CONFIG_S5P_MFC_VB2_SDVMM)
+struct vb2_mem_ops *s5p_mfc_mem_ops(void)
+{
+	return (struct vb2_mem_ops *)&vb2_sdvmm_memops;
+}
+
+void **s5p_mfc_mem_init_multi(struct device *dev, unsigned int ctx_num)
+{
+	struct vb2_vcm vcm;
+	void ** alloc_ctxes;
+	struct vb2_drv vb2_drv;
+
+	vcm.vcm_id = VCM_DEV_MFC;
+	/* FIXME: check port count */
+	vcm.size = SZ_256M;
+
+	vb2_drv.remap_dva = true;
+	vb2_drv.cacheable = false;
+
+	s5p_mfc_power_on();
+	alloc_ctxes = (void **)vb2_sdvmm_init_multi(ctx_num, &vcm,
+							NULL, &vb2_drv);
+	s5p_mfc_power_off();
+
+	return alloc_ctxes;
+}
+
+void s5p_mfc_mem_cleanup_multi(void **alloc_ctxes, unsigned int ctx_num)
+{
+	vb2_sdvmm_cleanup_multi(alloc_ctxes);
+}
+#elif defined(CONFIG_S5P_MFC_VB2_ION)
+struct vb2_mem_ops *s5p_mfc_mem_ops(void)
+{
+	return (struct vb2_mem_ops *)&vb2_ion_memops;
+}
+
+void **s5p_mfc_mem_init_multi(struct device *dev, unsigned int ctx_num)
+{
+	struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	void **alloc_ctxes;
+	unsigned int i;
+
+	alloc_ctxes = kmalloc(sizeof(*alloc_ctxes) * ctx_num, GFP_KERNEL);
+	if (!alloc_ctxes)
+		return NULL;
+
+	for (i = 0; i < ctx_num; i++) {
+		alloc_ctxes[i] = vb2_ion_create_context(dev,
+				IS_MFCV6(m_dev) ? SZ_4K : SZ_128K,
+				VB2ION_CTX_VMCONTIG | VB2ION_CTX_IOMMU);
+
+		if (IS_ERR(alloc_ctxes[i]))
+			break;
+	}
+
+	if (i < ctx_num) {
+		while (i-- > 0)
+			vb2_ion_destroy_context(alloc_ctxes[i]);
+
+		kfree(alloc_ctxes);
+		alloc_ctxes = NULL;
+	}
+
+	return alloc_ctxes;
+}
+
+void s5p_mfc_mem_cleanup_multi(void **alloc_ctxes, unsigned int ctx_num)
+{
+	while (ctx_num-- > 0)
+		vb2_ion_destroy_context(alloc_ctxes[ctx_num]);
+
+	kfree(alloc_ctxes);
+}
+#endif
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+struct vb2_cma_phys_conf {
+	struct device		*dev;
+	const char		*type;
+	unsigned long		alignment;
+	bool			cacheable;
+};
+
+struct vb2_cma_phys_buf {
+	struct vb2_cma_phys_conf		*conf;
+	dma_addr_t			paddr;
+	unsigned long			size;
+	struct vm_area_struct		*vma;
+	atomic_t			refcount;
+	struct vb2_vmarea_handler	handler;
+	bool				cacheable;
+};
+
+void s5p_mfc_cache_clean_fw(void *cookie)
+{
+	phys_addr_t phys = (phys_addr_t)cookie;
+	/* FIXME: cache maintenance operation */
+	dmac_map_area(phys_to_virt(phys), SZ_1M, DMA_TO_DEVICE);
+	outer_clean_range(phys, phys + SZ_1M);
+}
+
+void s5p_mfc_cache_clean(struct vb2_buffer *vb, int plane_no)
+{
+	struct vb2_cma_phys_buf *buf =
+		(struct vb2_cma_phys_buf *)vb->planes[plane_no].mem_priv;
+	void *start_addr;
+	unsigned long size;
+	unsigned long paddr = (dma_addr_t)buf->paddr;
+
+	start_addr = (dma_addr_t *)phys_to_virt(buf->paddr);
+	size = buf->size;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+	outer_clean_range(paddr, paddr + size);
+}
+
+void s5p_mfc_cache_inv(struct vb2_buffer *vb, int plane_no)
+{
+	struct vb2_cma_phys_buf *buf =
+		(struct vb2_cma_phys_buf *)vb->planes[plane_no].mem_priv;
+	void *start_addr;
+	unsigned long size;
+	unsigned long paddr = (dma_addr_t)buf->paddr;
+
+	start_addr = (dma_addr_t *)phys_to_virt(buf->paddr);
+	size = buf->size;
+
+	outer_inv_range(paddr, paddr + size);
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+}
+
+void s5p_mfc_mem_suspend(void *alloc_ctx)
+{
+	/* NOP */
+}
+
+int s5p_mfc_mem_resume(void *alloc_ctx)
+{
+	return 0;
+}
+
+void s5p_mfc_mem_set_cacheable(void *alloc_ctx, bool cacheable)
+{
+	vb2_cma_phys_set_cacheable(alloc_ctx, cacheable);
+}
+
+int s5p_mfc_mem_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	vb2_cma_phys_cache_flush(vb, plane_no);
+	return 0;
+}
+#elif defined(CONFIG_S5P_MFC_VB2_SDVMM)
+void s5p_mfc_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	end_addr = cur_addr + PAGE_ALIGN(size);
+
+	while (cur_addr < end_addr) {
+		paddr = page_to_pfn(vmalloc_to_page(cur_addr));
+		paddr <<= PAGE_SHIFT;
+		if (paddr)
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		cur_addr += PAGE_SIZE;
+	}
+
+	/* FIXME: L2 operation optimization */
+	/*
+	unsigned long start, end, unitsize;
+	unsigned long cur_addr, remain;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+
+	cur_addr = (unsigned long)start_addr;
+	remain = size;
+
+	start = page_to_pfn(vmalloc_to_page(cur_addr));
+	start <<= PAGE_SHIFT;
+	if (start & PAGE_MASK) {
+		unitsize = min((start | PAGE_MASK) - start + 1, remain);
+		end = start + unitsize;
+		outer_clean_range(start, end);
+		remain -= unitsize;
+		cur_addr += unitsize;
+	}
+
+	while (remain >= PAGE_SIZE) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + PAGE_SIZE;
+		outer_clean_range(start, end);
+		remain -= PAGE_SIZE;
+		cur_addr += PAGE_SIZE;
+	}
+
+	if (remain) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + remain;
+		outer_clean_range(start, end);
+	}
+	*/
+
+}
+
+void s5p_mfc_cache_inv(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	end_addr = cur_addr + PAGE_ALIGN(size);
+
+	while (cur_addr < end_addr) {
+		paddr = page_to_pfn(vmalloc_to_page(cur_addr));
+		paddr <<= PAGE_SHIFT;
+		if (paddr)
+			outer_inv_range(paddr, paddr + PAGE_SIZE);
+		cur_addr += PAGE_SIZE;
+	}
+
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+
+	/* FIXME: L2 operation optimization */
+	/*
+	unsigned long start, end, unitsize;
+	unsigned long cur_addr, remain;
+
+	cur_addr = (unsigned long)start_addr;
+	remain = size;
+
+	start = page_to_pfn(vmalloc_to_page(cur_addr));
+	start <<= PAGE_SHIFT;
+	if (start & PAGE_MASK) {
+		unitsize = min((start | PAGE_MASK) - start + 1, remain);
+		end = start + unitsize;
+		outer_inv_range(start, end);
+		remain -= unitsize;
+		cur_addr += unitsize;
+	}
+
+	while (remain >= PAGE_SIZE) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + PAGE_SIZE;
+		outer_inv_range(start, end);
+		remain -= PAGE_SIZE;
+		cur_addr += PAGE_SIZE;
+	}
+
+	if (remain) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + remain;
+		outer_inv_range(start, end);
+	}
+
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+	*/
+}
+
+void s5p_mfc_mem_suspend(void *alloc_ctx)
+{
+	s5p_mfc_clock_on();
+	vb2_sdvmm_suspend(alloc_ctx);
+	s5p_mfc_clock_off();
+}
+
+int s5p_mfc_mem_resume(void *alloc_ctx)
+{
+	s5p_mfc_clock_on();
+	vb2_sdvmm_resume(alloc_ctx);
+	s5p_mfc_clock_off();
+	return 0;
+}
+
+void s5p_mfc_mem_set_cacheable(void *alloc_ctx, bool cacheable)
+{
+	vb2_sdvmm_set_cacheable(alloc_ctx, cacheable);
+}
+
+int s5p_mfc_mem_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return vb2_sdvmm_cache_flush(vb, plane_no);
+}
+#elif defined(CONFIG_S5P_MFC_VB2_ION)
+
+void s5p_mfc_cache_clean_fw(void *cookie)
+{
+	int nents = 0;
+	struct scatterlist *sg;
+
+	sg = vb2_ion_get_sg(cookie, &nents);
+
+	dma_sync_sg_for_device(NULL, sg, nents, DMA_TO_DEVICE);
+}
+
+void s5p_mfc_cache_clean(struct vb2_buffer *vb, int plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	int nents = 0;
+	struct scatterlist *sg;
+
+	sg = vb2_ion_get_sg(cookie, &nents);
+
+	dma_sync_sg_for_device(NULL, sg, nents, DMA_TO_DEVICE);
+}
+
+void s5p_mfc_cache_inv(struct vb2_buffer *vb, int plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	int nents = 0;
+	struct scatterlist *sg;
+
+	sg = vb2_ion_get_sg(cookie, &nents);
+
+	dma_sync_sg_for_device(NULL, sg, nents, DMA_FROM_DEVICE);
+}
+
+void s5p_mfc_mem_suspend(void *alloc_ctx)
+{
+	vb2_ion_detach_iommu(alloc_ctx);
+}
+
+int s5p_mfc_mem_resume(void *alloc_ctx)
+{
+	return vb2_ion_attach_iommu(alloc_ctx);
+}
+
+void s5p_mfc_mem_set_cacheable(void *alloc_ctx, bool cacheable)
+{
+	vb2_ion_set_cached(alloc_ctx, cacheable);
+}
+
+int s5p_mfc_mem_cache_flush(struct vb2_buffer *vb, u32 plane_no)
+{
+	return vb2_ion_cache_flush(vb, plane_no);
+}
+#endif
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_mem.h b/drivers/media/video/s5p-mfc/s5p_mfc_mem.h
new file mode 100644
index 0000000..9efe766
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_mem.h
@@ -0,0 +1,166 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_mem.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_MEM_H_
+#define __S5P_MFC_MEM_H_ __FILE__
+
+#include <linux/platform_device.h>
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#define CONFIG_S5P_MFC_VB2_CMA	1
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#define CONFIG_S5P_MFC_VB2_ION	1
+#endif
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_S5P_MFC_VB2_SDVMM)
+#include <media/videobuf2-sdvmm.h>
+#elif defined(CONFIG_S5P_MFC_VB2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+
+/* Offset base used to differentiate between CAPTURE and OUTPUT
+*  while mmaping */
+#define DST_QUEUE_OFF_BASE      (TASK_SIZE / 2)
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+/* Define names for CMA memory kinds used by MFC */
+#define MFC_CMA_BANK1		"a"
+#define MFC_CMA_BANK2		"b"
+#define MFC_CMA_FW		"f"
+
+#define MFC_CMA_FW_ALLOC_CTX	0
+#define MFC_CMA_BANK1_ALLOC_CTX 1
+#define MFC_CMA_BANK2_ALLOC_CTX 2
+
+#define MFC_CMA_BANK1_ALIGN	0x2000	/* 8KB */
+#define MFC_CMA_BANK2_ALIGN	0x2000	/* 8KB */
+#define MFC_CMA_FW_ALIGN	0x20000	/* 128KB */
+
+#define mfc_plane_cookie(v, n)	vb2_cma_phys_plane_paddr(v, n)
+
+static inline void *s5p_mfc_mem_allocate(void *a, unsigned int s)
+{
+	return vb2_cma_phys_memops.alloc(a, s);
+}
+
+static inline size_t s5p_mfc_mem_dma_addr(void *b)
+{
+	return (size_t)vb2_cma_phys_memops.cookie(b);
+}
+
+static inline void s5p_mfc_mem_free(void *b)
+{
+	vb2_cma_phys_memops.put(b);
+}
+
+static inline void *s5p_mfc_mem_vaddr(void *b)
+{
+	return vb2_cma_phys_memops.vaddr(b);
+}
+#elif defined(CONFIG_S5P_MFC_VB2_SDVMM)
+#define MFC_ALLOC_CTX_NUM	2
+
+#define MFC_BANK_A_ALLOC_CTX	0
+#define MFC_BANK_B_ALLOC_CTX	1
+
+#define MFC_BANK_A_ALIGN_ORDER	11
+#define MFC_BANK_B_ALIGN_ORDER	11
+
+#define MFC_CMA_BANK1_ALLOC_CTX MFC_BANK_A_ALLOC_CTX
+#define MFC_CMA_BANK2_ALLOC_CTX MFC_BANK_B_ALLOC_CTX
+#define MFC_CMA_FW_ALLOC_CTX	MFC_BANK_A_ALLOC_CTX
+
+#define mfc_plane_cookie(v, n)	vb2_sdvmm_plane_dvaddr(v, n)
+
+static inline void *s5p_mfc_mem_alloc(void *a, unsigned int s)
+{
+	return vb2_sdvmm_memops.alloc(a, s);
+}
+
+static inline size_t s5p_mfc_mem_cookie(void *a, void *b)
+{
+	return (size_t)vb2_sdvmm_memops.cookie(b);
+}
+
+static inline void s5p_mfc_mem_put(void *a, void *b)
+{
+	vb2_sdvmm_memops.put(b);
+}
+
+static inline void *s5p_mfc_mem_vaddr(void *a, void *b)
+{
+	return vb2_sdvmm_memops.vaddr(b);
+}
+#elif defined(CONFIG_S5P_MFC_VB2_ION)
+#define MFC_ALLOC_CTX_NUM	2
+
+#define MFC_BANK_A_ALLOC_CTX	0
+#define MFC_BANK_B_ALLOC_CTX	1
+
+#define MFC_BANK_A_ALIGN_ORDER	11
+#define MFC_BANK_B_ALIGN_ORDER	11
+
+#define MFC_CMA_BANK1_ALLOC_CTX MFC_BANK_A_ALLOC_CTX
+#define MFC_CMA_BANK2_ALLOC_CTX MFC_BANK_B_ALLOC_CTX
+#define MFC_CMA_FW_ALLOC_CTX	MFC_BANK_A_ALLOC_CTX
+
+static inline unsigned long mfc_plane_cookie(
+					struct vb2_buffer *v, unsigned int n)
+{
+	void *cookie = vb2_plane_cookie(v, n);
+	dma_addr_t dva;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+	return (unsigned long)dva;
+}
+
+static inline void *s5p_mfc_mem_allocate(void *alloc_ctx, unsigned int size)
+{
+	return vb2_ion_private_alloc(alloc_ctx, size);
+}
+
+static inline dma_addr_t s5p_mfc_mem_dma_addr(void *cookie)
+{
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+
+static inline void s5p_mfc_mem_free(void *cookie)
+{
+	vb2_ion_private_free(cookie);
+}
+
+static inline void *s5p_mfc_mem_vaddr(void *cookie)
+{
+	return vb2_ion_private_vaddr(cookie);
+}
+#endif
+
+struct vb2_mem_ops *s5p_mfc_mem_ops(void);
+void **s5p_mfc_mem_init_multi(struct device *dev, unsigned int ctx_num);
+void s5p_mfc_mem_cleanup_multi(void **alloc_ctxes, unsigned int ctx_num);
+
+void s5p_mfc_cache_clean_fw(void *cookie);
+void s5p_mfc_cache_clean(struct vb2_buffer *vb, int plane_no);
+void s5p_mfc_cache_inv(struct vb2_buffer *vb, int plane_no);
+
+void s5p_mfc_mem_suspend(void *alloc_ctx);
+int s5p_mfc_mem_resume(void *alloc_ctx);
+
+void s5p_mfc_mem_set_cacheable(void *alloc_ctx, bool cacheable);
+int s5p_mfc_mem_cache_flush(struct vb2_buffer *vb, u32 plane_no);
+#endif /* __S5P_MFC_MEM_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.c
new file mode 100644
index 0000000..a716761
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.c
@@ -0,0 +1,1797 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_opr.c
+ *
+ * Samsung MFC (Multi Function Codec - FIMV) driver
+ * This file contains hw related functions.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG
+
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+
+#include <linux/firmware.h>
+#include <linux/err.h>
+#include <linux/sched.h>
+#include <linux/cma.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_inst.h"
+#include "s5p_mfc_pm.h"
+#include "s5p_mfc_debug.h"
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+#include <media/videobuf2-cma-phys.h>
+#endif
+
+/* #define S5P_MFC_DEBUG_REGWRITE  */
+#ifdef S5P_MFC_DEBUG_REGWRITE
+#undef writel
+#define writel(v, r) do { \
+	printk(KERN_ERR "MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
+	__raw_writel(v, r); } while (0)
+#endif /* S5P_MFC_DEBUG_REGWRITE */
+
+#define READL(offset)		readl(dev->regs_base + (offset))
+#define WRITEL(data, offset)	writel((data), dev->regs_base + (offset))
+#define OFFSETA(x)		(((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
+#define OFFSETB(x)		(((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
+
+/* Allocate temporary buffers for decoding */
+int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->buf;
+
+	mfc_debug_enter();
+
+	dec->dsc.alloc = s5p_mfc_mem_alloc(
+			dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], buf_size->desc_buf);
+	if (IS_ERR(dec->dsc.alloc)) {
+		mfc_err("Allocating DESC buffer failed.\n");
+		return PTR_ERR(dec->dsc.alloc);
+	}
+
+	dec->dsc.ofs = OFFSETA(s5p_mfc_mem_cookie(
+			dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], dec->dsc.alloc));
+
+	/* FIXME: need clean to zero */
+#if 0
+	dec->dsc.virt = s5p_mfc_mem_vaddr(
+			dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], dec->dsc.alloc);
+	if (!dec->dsc.virt) {
+		s5p_mfc_mem_put(
+			dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], dec->dsc.alloc);
+		dec->dsc.alloc = NULL;
+		dec->dsc.ofs = 0;
+
+		mfc_err("Remapping DESC buffer failed.\n");
+		return -ENOMEM;
+	}
+
+	memset(ctx->dec.virt, 0, DESC_BUF_SIZE);
+	s5p_mfc_cache_clean(ctx->dec.virt, DESC_BUF_SIZE);
+#endif
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release temproary buffers for decoding */
+void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+
+	if (dec->dsc.alloc) {
+		s5p_mfc_mem_put(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+								dec->dsc.alloc);
+		dec->dsc.alloc = NULL;
+		dec->dsc.ofs = 0;
+		dec->dsc.virt = NULL;
+	}
+}
+
+/* Allocate codec buffers */
+int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned int enc_ref_y_size = 0;
+	unsigned int enc_ref_c_size = 0;
+	unsigned int guard_width, guard_height;
+
+	mfc_debug_enter();
+
+	if (ctx->type == MFCINST_DECODER) {
+		mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
+			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
+		mfc_debug(2, "Totals bufs: %d\n", dec->total_dpb_count);
+	} else if (ctx->type == MFCINST_ENCODER) {
+		enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+			* ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
+		enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
+
+		if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) {
+			enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+				* ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
+			enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN);
+		} else {
+			guard_width = ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
+			guard_height = ALIGN((ctx->img_height >> 1) + 4, S5P_FIMV_NV12MT_VALIGN);
+			enc_ref_c_size = ALIGN(guard_width * guard_height,
+					       S5P_FIMV_NV12MT_SALIGN);
+		}
+
+		mfc_debug(2, "recon luma size: %d chroma size: %d\n",
+			  enc_ref_y_size, enc_ref_c_size);
+	} else {
+		return -EINVAL;
+	}
+
+	/* Codecs have different memory requirements */
+	switch (ctx->codec_mode) {
+	case S5P_FIMV_CODEC_H264_DEC:
+		ctx->port_a_size =
+		    ALIGN(S5P_FIMV_DEC_NB_IP_SIZE +
+					S5P_FIMV_DEC_VERT_NB_MV_SIZE,
+					S5P_FIMV_DEC_BUF_ALIGN);
+		/* TODO, when merged with FIMC then test will it work without
+		 * alignment to 8192. For all codecs. */
+		ctx->port_b_size = dec->total_dpb_count * ctx->mv_size;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_DEC:
+	case S5P_FIMV_CODEC_FIMV1_DEC:
+	case S5P_FIMV_CODEC_FIMV2_DEC:
+	case S5P_FIMV_CODEC_FIMV3_DEC:
+	case S5P_FIMV_CODEC_FIMV4_DEC:
+		ctx->port_a_size =
+		    ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE +
+				     S5P_FIMV_DEC_UPNB_MV_SIZE +
+				     S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
+				     S5P_FIMV_DEC_STX_PARSER_SIZE +
+				     S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE,
+				     S5P_FIMV_DEC_BUF_ALIGN);
+		ctx->port_b_size = 0;
+		break;
+
+	case S5P_FIMV_CODEC_VC1RCV_DEC:
+	case S5P_FIMV_CODEC_VC1_DEC:
+		ctx->port_a_size =
+		    ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
+			     S5P_FIMV_DEC_UPNB_MV_SIZE +
+			     S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
+			     S5P_FIMV_DEC_NB_DCAC_SIZE +
+			     3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE,
+			     S5P_FIMV_DEC_BUF_ALIGN);
+		ctx->port_b_size = 0;
+		break;
+
+	case S5P_FIMV_CODEC_MPEG2_DEC:
+		ctx->port_a_size = 0;
+		ctx->port_b_size = 0;
+		break;
+	case S5P_FIMV_CODEC_H263_DEC:
+		ctx->port_a_size =
+		    ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
+			     S5P_FIMV_DEC_UPNB_MV_SIZE +
+			     S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
+			     S5P_FIMV_DEC_NB_DCAC_SIZE,
+			     S5P_FIMV_DEC_BUF_ALIGN);
+		ctx->port_b_size = 0;
+		break;
+
+	case S5P_FIMV_CODEC_H264_ENC:
+		ctx->port_a_size = (enc_ref_y_size * 2) +
+				   S5P_FIMV_ENC_UPMV_SIZE +
+				   S5P_FIMV_ENC_COLFLG_SIZE +
+				   S5P_FIMV_ENC_INTRAMD_SIZE +
+				   S5P_FIMV_ENC_NBORINFO_SIZE;
+		ctx->port_b_size = (enc_ref_y_size * 2) +
+				   (enc_ref_c_size * 4) +
+				   S5P_FIMV_ENC_INTRAPRED_SIZE;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_ENC:
+		ctx->port_a_size = (enc_ref_y_size * 2) +
+				   S5P_FIMV_ENC_UPMV_SIZE +
+				   S5P_FIMV_ENC_COLFLG_SIZE +
+				   S5P_FIMV_ENC_ACDCCOEF_SIZE;
+		ctx->port_b_size = (enc_ref_y_size * 2) +
+				   (enc_ref_c_size * 4);
+		break;
+	case S5P_FIMV_CODEC_H263_ENC:
+		ctx->port_a_size = (enc_ref_y_size * 2) +
+				   S5P_FIMV_ENC_UPMV_SIZE +
+				   S5P_FIMV_ENC_ACDCCOEF_SIZE;
+		ctx->port_b_size = (enc_ref_y_size * 2) +
+				   (enc_ref_c_size * 4);
+		break;
+	default:
+		break;
+	}
+
+	/* Allocate only if memory from bank 1 is necessary */
+	if (ctx->port_a_size > 0) {
+		ctx->port_a_buf = s5p_mfc_mem_alloc(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->port_a_size);
+		if (IS_ERR(ctx->port_a_buf)) {
+			ctx->port_a_buf = 0;
+			printk(KERN_ERR
+			       "Buf alloc for decoding failed (port A).\n");
+			return -ENOMEM;
+		}
+		ctx->port_a_phys = s5p_mfc_mem_cookie(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->port_a_buf);
+	}
+
+	/* Allocate only if memory from bank 2 is necessary */
+	if (ctx->port_b_size > 0) {
+		ctx->port_b_buf = s5p_mfc_mem_alloc(
+		dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX], ctx->port_b_size);
+		if (IS_ERR(ctx->port_b_buf)) {
+			ctx->port_b_buf = 0;
+			mfc_err("Buf alloc for decoding failed (port B).\n");
+			return -ENOMEM;
+		}
+		ctx->port_b_phys = s5p_mfc_mem_cookie(
+		dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX], ctx->port_b_buf);
+	}
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release buffers allocated for codec */
+void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	if (ctx->port_a_buf) {
+		s5p_mfc_mem_put(ctx->dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+							ctx->port_a_buf);
+		ctx->port_a_buf = 0;
+		ctx->port_a_phys = 0;
+		ctx->port_a_size = 0;
+	}
+	if (ctx->port_b_buf) {
+		s5p_mfc_mem_put(ctx->dev->alloc_ctx[MFC_CMA_BANK2_ALLOC_CTX],
+							ctx->port_b_buf);
+		ctx->port_b_buf = 0;
+		ctx->port_b_phys = 0;
+		ctx->port_b_size = 0;
+	}
+}
+
+/* Allocate memory for instance data buffer */
+int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->buf;
+
+	mfc_debug_enter();
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC)
+		ctx->ctx_buf_size = buf_size->h264_ctx_buf;
+	else
+		ctx->ctx_buf_size = buf_size->non_h264_ctx_buf;
+
+	ctx->ctx.alloc = s5p_mfc_mem_alloc(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->ctx_buf_size);
+	if (IS_ERR(ctx->ctx.alloc)) {
+		mfc_err("Allocating context buffer failed.\n");
+		return PTR_ERR(ctx->ctx.alloc);
+	}
+
+	ctx->ctx.ofs = OFFSETA(s5p_mfc_mem_cookie(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->ctx.alloc));
+
+	ctx->ctx.virt = s5p_mfc_mem_vaddr(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->ctx.alloc);
+	if (!ctx->ctx.virt) {
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+							ctx->ctx.alloc);
+		ctx->ctx.alloc = NULL;
+		ctx->ctx.ofs = 0;
+		ctx->ctx.virt = NULL;
+
+		mfc_err("Remapping context buffer failed.\n");
+		return -ENOMEM;
+	}
+
+	memset(ctx->ctx.virt, 0, ctx->ctx_buf_size);
+	s5p_mfc_cache_clean(ctx->ctx.alloc);
+	/*
+	ctx->ctx.dma = dma_map_single(ctx->dev->v4l2_dev.dev,
+					  ctx->ctx.virt, ctx->ctx_buf_size,
+					  DMA_TO_DEVICE);
+	*/
+
+	if (s5p_mfc_init_shm(ctx) < 0) {
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+							ctx->ctx.alloc);
+		ctx->ctx.alloc = NULL;
+		ctx->ctx.ofs = 0;
+		ctx->ctx.virt = NULL;
+
+		mfc_err("Remapping shared mem buffer failed.\n");
+		return -ENOMEM;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release instance buffer */
+void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug_enter();
+
+	if (ctx->ctx.alloc) {
+		/*
+		dma_unmap_single(ctx->dev->v4l2_dev.dev,
+				ctx->ctx.dma, ctx->ctx_buf_size,
+				DMA_TO_DEVICE);
+		*/
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+							ctx->ctx.alloc);
+		ctx->ctx.alloc = NULL;
+		ctx->ctx.ofs = 0;
+		ctx->ctx.virt = NULL;
+	}
+	if (ctx->shm.alloc) {
+		s5p_mfc_mem_put(dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX],
+							ctx->shm.alloc);
+		ctx->shm.alloc = NULL;
+		ctx->shm.ofs = 0;
+		ctx->shm.virt = NULL;
+	}
+
+	mfc_debug_leave();
+}
+
+int s5p_mfc_alloc_dev_context_buffer(struct s5p_mfc_dev *dev)
+{
+	/* NOP */
+
+	return 0;
+}
+
+void s5p_mfc_release_dev_context_buffer(struct s5p_mfc_dev *dev)
+{
+	/* NOP */
+}
+
+void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx)
+{
+	unsigned int guard_width, guard_height;
+
+	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
+	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
+	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
+			"buffer dimensions: %dx%d\n", ctx->img_width,
+			ctx->img_height, ctx->buf_width, ctx->buf_height);
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) {
+		ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height,
+				S5P_FIMV_DEC_BUF_ALIGN);
+		ctx->chroma_size = ALIGN(ctx->buf_width *
+				ALIGN((ctx->img_height >> 1),
+					S5P_FIMV_NV12MT_VALIGN),
+				S5P_FIMV_DEC_BUF_ALIGN);
+		ctx->mv_size = ALIGN(ctx->buf_width *
+				ALIGN((ctx->buf_height >> 2),
+					S5P_FIMV_NV12MT_VALIGN),
+				S5P_FIMV_DEC_BUF_ALIGN);
+	} else {
+		guard_width = ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN);
+		guard_height = ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN);
+		ctx->luma_size = ALIGN(guard_width * guard_height,
+				S5P_FIMV_DEC_BUF_ALIGN);
+
+		guard_width = ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
+		guard_height = ALIGN((ctx->img_height >> 1) + 4, S5P_FIMV_NV12MT_VALIGN);
+		ctx->chroma_size = ALIGN(guard_width * guard_height,
+				S5P_FIMV_DEC_BUF_ALIGN);
+
+		ctx->mv_size = 0;
+	}
+}
+
+void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx)
+{
+	/* FIXME: Need to check the alignment value */
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
+		ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN);
+
+		ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
+			* ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN);
+		ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
+			* ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN);
+
+		ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN);
+		ctx->chroma_size = ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN);
+	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
+		ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
+
+		ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+			* ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
+		ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+			* ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
+
+		ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN);
+		ctx->chroma_size = ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN);
+	}
+}
+
+/* Set registers for decoding temporary buffers */
+void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->buf;
+
+	WRITEL(dec->dsc.ofs, S5P_FIMV_SI_CH0_DESC_ADR);
+	WRITEL(buf_size->desc_buf, S5P_FIMV_SI_CH0_DESC_SIZE);
+}
+
+/* Set registers for shared buffer */
+void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	WRITEL(ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
+}
+
+/* Set registers for decoding stream buffer */
+int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
+		  unsigned int start_num_byte, unsigned int buf_size)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf_size *variant_buf_size = dev->variant->buf_size;
+
+	mfc_debug_enter();
+	mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x, buf_size: 0x"
+		"%08x (%d)\n",  ctx->inst_no, buf_addr, buf_size, buf_size);
+	WRITEL(OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
+	WRITEL(variant_buf_size->cpb_buf, S5P_FIMV_SI_CH0_CPB_SIZE);
+	WRITEL(buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
+	mfc_debug(2, "Shared_virt: %p (start offset: %d)\n",
+					ctx->shm.virt, start_num_byte);
+	s5p_mfc_write_info(ctx, start_num_byte, START_BYTE_NUM);
+	mfc_debug_leave();
+	return 0;
+}
+
+/* Set decoding frame buffer */
+int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx)
+{
+	unsigned int frame_size, i;
+	unsigned int frame_size_ch, frame_size_mv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned int dpb;
+	size_t buf_addr1, buf_addr2;
+	int buf_size1, buf_size2;
+	struct s5p_mfc_buf *buf;
+	struct list_head *buf_queue;
+
+	buf_addr1 = ctx->port_a_phys;
+	buf_size1 = ctx->port_a_size;
+	buf_addr2 = ctx->port_b_phys;
+	buf_size2 = ctx->port_b_size;
+
+	mfc_debug(2, "Buf1: %p (%d) Buf2: %p (%d)\n",
+		  (void *)buf_addr1, buf_size1,
+		  (void *)buf_addr2, buf_size2);
+	mfc_debug(2, "Total DPB COUNT: %d\n", dec->total_dpb_count);
+	mfc_debug(2, "Setting display delay to %d\n", dec->display_delay);
+
+	dpb = READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & ~S5P_FIMV_DPB_COUNT_MASK;
+	WRITEL(dec->total_dpb_count | dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
+
+	s5p_mfc_set_shared_buffer(ctx);
+
+	switch (ctx->codec_mode) {
+	case S5P_FIMV_CODEC_H264_DEC:
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_VERT_NB_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR);
+		buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_DEC:
+	case S5P_FIMV_CODEC_FIMV1_DEC:
+	case S5P_FIMV_CODEC_FIMV2_DEC:
+	case S5P_FIMV_CODEC_FIMV3_DEC:
+	case S5P_FIMV_CODEC_FIMV4_DEC:
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR);
+		buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR);
+		buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR);
+		buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		break;
+	case S5P_FIMV_CODEC_H263_DEC:
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR);
+		buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR);
+		buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
+		break;
+	case S5P_FIMV_CODEC_VC1_DEC:
+	case S5P_FIMV_CODEC_VC1RCV_DEC:
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR);
+		buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR);
+		buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR);
+		buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR);
+		buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR);
+		buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR);
+		buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
+		break;
+	case S5P_FIMV_CODEC_MPEG2_DEC:
+		break;
+	default:
+		mfc_err("Unknown codec for decoding (%x).\n",
+			ctx->codec_mode);
+		return -EINVAL;
+		break;
+	}
+	frame_size = ctx->luma_size;
+	frame_size_ch = ctx->chroma_size;
+	frame_size_mv = ctx->mv_size;
+	mfc_debug(2, "Frame size: %d ch: %d mv: %d\n", frame_size, frame_size_ch,
+								frame_size_mv);
+
+	i = 0;
+	if (dec->dst_memtype == V4L2_MEMORY_USERPTR)
+		buf_queue = &ctx->dst_queue;
+	else
+		buf_queue = &dec->dpb_queue;
+	list_for_each_entry(buf, buf_queue, list) {
+		mfc_debug(2, "Luma %x\n", buf->cookie.raw.luma);
+		WRITEL(OFFSETB(buf->cookie.raw.luma), S5P_FIMV_DEC_LUMA_ADR + i * 4);
+		mfc_debug(2, "\tChroma %x\n", buf->cookie.raw.chroma);
+		WRITEL(OFFSETA(buf->cookie.raw.chroma), S5P_FIMV_DEC_CHROMA_ADR + i * 4);
+
+		if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) {
+			mfc_debug(2, "\tBuf2: %x, size: %d\n", buf_addr2, buf_size2);
+			WRITEL(OFFSETB(buf_addr2), S5P_FIMV_H264_MV_ADR + i * 4);
+			buf_addr2 += frame_size_mv;
+			buf_size2 -= frame_size_mv;
+		}
+
+		i++;
+	}
+
+	mfc_debug(2, "Buf1: %u, buf_size1: %d\n", buf_addr1, buf_size1);
+	mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n",
+			buf_size1,  buf_size2, dec->total_dpb_count);
+	if (buf_size1 < 0 || buf_size2 < 0) {
+		mfc_debug(2, "Not enough memory has been allocated.\n");
+		return -ENOMEM;
+	}
+
+	s5p_mfc_write_info(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
+	s5p_mfc_write_info(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC)
+		s5p_mfc_write_info(ctx, frame_size_mv, ALLOC_MV_SIZE);
+
+	WRITEL(((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
+				| (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
+
+	mfc_debug(2, "After setting buffers.\n");
+	return 0;
+}
+
+/* Set registers for encoding stream buffer */
+int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long addr, unsigned int size)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	WRITEL(OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR);
+	WRITEL(size, S5P_FIMV_ENC_SI_CH0_SB_SIZE);
+
+	return 0;
+}
+
+void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long y_addr, unsigned long c_addr)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	WRITEL(OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR);
+	WRITEL(OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR);
+}
+
+void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long *y_addr, unsigned long *c_addr)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	*y_addr = dev->port_b + (READL(S5P_FIMV_ENCODED_Y_ADDR) << 11);
+	*c_addr = dev->port_b + (READL(S5P_FIMV_ENCODED_C_ADDR) << 11);
+}
+
+/* Set encoding ref & codec buffer */
+int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	size_t buf_addr1, buf_addr2;
+	size_t buf_size1, buf_size2;
+	unsigned int enc_ref_y_size, enc_ref_c_size;
+	unsigned int guard_width, guard_height;
+	int i;
+
+	mfc_debug_enter();
+
+	buf_addr1 = ctx->port_a_phys;
+	buf_size1 = ctx->port_a_size;
+	buf_addr2 = ctx->port_b_phys;
+	buf_size2 = ctx->port_b_size;
+
+	enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+		* ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
+	enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) {
+		enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
+			* ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
+		enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN);
+	} else {
+		guard_width = ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
+		guard_height = ALIGN((ctx->img_height >> 1) + 4, S5P_FIMV_NV12MT_VALIGN);
+		enc_ref_c_size = ALIGN(guard_width * guard_height,
+				       S5P_FIMV_NV12MT_SALIGN);
+	}
+
+	mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", buf_size1, buf_size2);
+
+	switch (ctx->codec_mode) {
+	case S5P_FIMV_CODEC_H264_ENC:
+		for (i = 0; i < 2; i++) {
+			WRITEL(OFFSETA(buf_addr1),
+				S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
+			buf_addr1 += enc_ref_y_size;
+			buf_size1 -= enc_ref_y_size;
+
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_y_size;
+			buf_size2 -= enc_ref_y_size;
+		}
+
+		for (i = 0; i < 4; i++) {
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_c_size;
+			buf_size2 -= enc_ref_c_size;
+		}
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR);
+		buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_COZERO_FLAG_ADR);
+		buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_UP_INTRA_MD_ADR);
+		buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE;
+
+		WRITEL(OFFSETB(buf_addr2), S5P_FIMV_H264_UP_INTRA_PRED_ADR);
+		buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE;
+		buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H264_NBOR_INFO_ADR);
+		buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE;
+
+		mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
+			buf_size1, buf_size2);
+		break;
+
+	case S5P_FIMV_CODEC_MPEG4_ENC:
+		for (i = 0; i < 2; i++) {
+			WRITEL(OFFSETA(buf_addr1),
+				S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
+			buf_addr1 += enc_ref_y_size;
+			buf_size1 -= enc_ref_y_size;
+
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_y_size;
+			buf_size2 -= enc_ref_y_size;
+		}
+
+		for (i = 0; i < 4; i++) {
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_c_size;
+			buf_size2 -= enc_ref_c_size;
+		}
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR);
+		buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_COZERO_FLAG_ADR);
+		buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_MPEG4_ACDC_COEF_ADR);
+		buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
+
+		mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
+			buf_size1, buf_size2);
+		break;
+
+	case S5P_FIMV_CODEC_H263_ENC:
+		for (i = 0; i < 2; i++) {
+			WRITEL(OFFSETA(buf_addr1),
+				S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
+			buf_addr1 += enc_ref_y_size;
+			buf_size1 -= enc_ref_y_size;
+
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_y_size;
+			buf_size2 -= enc_ref_y_size;
+		}
+
+		for (i = 0; i < 4; i++) {
+			WRITEL(OFFSETB(buf_addr2),
+				S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
+			buf_addr2 += enc_ref_c_size;
+			buf_size2 -= enc_ref_c_size;
+		}
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR);
+		buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
+
+		WRITEL(OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR);
+		buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
+		buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
+
+		mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
+			buf_size1, buf_size2);
+		break;
+
+	default:
+		mfc_err("Unknown codec set for encoding: %d\n",
+			ctx->codec_mode);
+		return -EINVAL;
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	unsigned int reg;
+	unsigned int shm;
+
+	mfc_debug_enter();
+
+	/* width */
+	WRITEL(ctx->img_width, S5P_FIMV_ENC_HSIZE_PX);
+	/* height */
+	WRITEL(ctx->img_height, S5P_FIMV_ENC_VSIZE_PX);
+
+	/* pictype : enable, IDR period */
+	reg = READL(S5P_FIMV_ENC_PIC_TYPE_CTRL);
+	reg |= (1 << 18);
+	reg &= ~(0xFFFF);
+	reg |= p->gop_size;
+	WRITEL(reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
+
+	WRITEL(0, S5P_FIMV_ENC_B_RECON_WRITE_ON);
+
+	/* multi-slice control */
+	/* multi-slice MB number or bit size */
+	WRITEL(p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL);
+	if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
+		WRITEL(p->slice_mb, S5P_FIMV_ENC_MSLICE_MB);
+	} else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
+		WRITEL(p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT);
+	} else {
+		WRITEL(0, S5P_FIMV_ENC_MSLICE_MB);
+		WRITEL(0, S5P_FIMV_ENC_MSLICE_BIT);
+	}
+
+	/* cyclic intra refresh */
+	WRITEL(p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL);
+
+	/* memory structure cur. frame */
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
+		WRITEL(0, S5P_FIMV_ENC_MAP_FOR_CUR);
+	else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
+		WRITEL(3, S5P_FIMV_ENC_MAP_FOR_CUR);
+
+	/* padding control & value */
+	reg = READL(S5P_FIMV_ENC_PADDING_CTRL);
+	if (p->pad) {
+		/** enable */
+		reg |= (1 << 31);
+		/** cr value */
+		reg &= ~(0xFF << 16);
+		reg |= (p->pad_cr << 16);
+		/** cb value */
+		reg &= ~(0xFF << 8);
+		reg |= (p->pad_cb << 8);
+		/** y value */
+		reg &= ~(0xFF);
+		reg |= (p->pad_luma);
+	} else {
+		/** disable & all value clear */
+		reg = 0;
+	}
+	WRITEL(reg, S5P_FIMV_ENC_PADDING_CTRL);
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_ENC_RC_CONFIG);
+	/** frame-level rate control */
+	reg &= ~(0x1 << 9);
+	reg |= (p->rc_frame << 9);
+	WRITEL(reg, S5P_FIMV_ENC_RC_CONFIG);
+
+	/* bit rate */
+	if (p->rc_frame)
+		WRITEL(p->rc_bitrate,
+			S5P_FIMV_ENC_RC_BIT_RATE);
+	else
+		WRITEL(0, S5P_FIMV_ENC_RC_BIT_RATE);
+
+	/* reaction coefficient */
+	if (p->rc_frame)
+		WRITEL(p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA);
+
+	/* extended encoder ctrl */
+	shm = s5p_mfc_read_info(ctx, EXT_ENC_CONTROL);
+	/** vbv buffer size */
+	if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
+		shm &= ~(0xFFFF << 16);
+		shm |= (p->vbv_buf_size << 16);
+	}
+	/** seq header ctrl */
+	shm &= ~(0x1 << 3);
+	shm |= (p->seq_hdr_mode << 3);
+	/** frame skip mode */
+	shm &= ~(0x3 << 1);
+	shm |= (p->frame_skip_mode << 1);
+	s5p_mfc_write_info(ctx, shm, EXT_ENC_CONTROL);
+
+	/* fixed target bit */
+	s5p_mfc_write_info(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264;
+	unsigned int reg;
+	unsigned int shm;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* pictype : number of B */
+	reg = READL(S5P_FIMV_ENC_PIC_TYPE_CTRL);
+	/** num_b_frame - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= (p->num_b_frame << 16);
+	WRITEL(reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
+
+	/* profile & level */
+	reg = READL(S5P_FIMV_ENC_PROFILE);
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= (p_264->level << 8);
+	/** profile - 0 ~ 2 */
+	reg &= ~(0x3F);
+	reg |= p_264->profile;
+	WRITEL(reg, S5P_FIMV_ENC_PROFILE);
+
+	/* interlace  */
+	WRITEL(p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT);
+	/** height */
+	if (p_264->interlace)
+		WRITEL(ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
+
+	/* loopfilter ctrl */
+	WRITEL(p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL);
+
+	/* loopfilter alpha offset */
+	if (p_264->loop_filter_alpha < 0) {
+		reg = 0x10;
+		reg |= (0xFF - p_264->loop_filter_alpha) + 1;
+	} else {
+		reg = 0x00;
+		reg |= (p_264->loop_filter_alpha & 0xF);
+	}
+	WRITEL(reg, S5P_FIMV_ENC_ALPHA_OFF);
+
+	/* loopfilter beta offset */
+	if (p_264->loop_filter_beta < 0) {
+		reg = 0x10;
+		reg |= (0xFF - p_264->loop_filter_beta) + 1;
+	} else {
+		reg = 0x00;
+		reg |= (p_264->loop_filter_beta & 0xF);
+	}
+	WRITEL(reg, S5P_FIMV_ENC_BETA_OFF);
+
+	/* entropy coding mode */
+	WRITEL(p_264->entropy_mode, S5P_FIMV_ENC_H264_ENTRP_MODE);
+
+	/* number of ref. picture */
+	reg = READL(S5P_FIMV_ENC_H264_NUM_OF_REF);
+	/** num of ref. pictures of P */
+	reg &= ~(0x3 << 5);
+	reg |= (p_264->num_ref_pic_4p << 5);
+	WRITEL(reg, S5P_FIMV_ENC_H264_NUM_OF_REF);
+
+	/* 8x8 transform enable */
+	WRITEL(p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG);
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_ENC_RC_CONFIG);
+	/** macroblock level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= (p->rc_mb << 8);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_264->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_CONFIG);
+
+	/* frame rate */
+	if (p->rc_frame)
+		/* FIXME: user set 1000x scale value */
+		WRITEL(p_264->rc_framerate * 1000,
+			S5P_FIMV_ENC_RC_FRAME_RATE);
+	else
+		WRITEL(0, S5P_FIMV_ENC_RC_FRAME_RATE);
+
+	/* max & min value of QP */
+	reg = READL(S5P_FIMV_ENC_RC_QBOUND);
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_264->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_264->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_QBOUND);
+
+	/* macroblock adaptive scaling features */
+	if (p->rc_mb) {
+		reg = READL(S5P_FIMV_ENC_RC_MB_CTRL);
+		/** dark region */
+		reg &= ~(0x1 << 3);
+		reg |= (p_264->rc_mb_dark << 3);
+		/** smooth region */
+		reg &= ~(0x1 << 2);
+		reg |= (p_264->rc_mb_smooth << 2);
+		/** static region */
+		reg &= ~(0x1 << 1);
+		reg |= (p_264->rc_mb_static << 1);
+		/** high activity region */
+		reg &= ~(0x1);
+		reg |= p_264->rc_mb_activity;
+		WRITEL(reg, S5P_FIMV_ENC_RC_MB_CTRL);
+	}
+
+	if (!p->rc_frame && !p->rc_mb) {
+		shm = s5p_mfc_read_info(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF);
+		shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6);
+		shm |= (p_264->rc_p_frame_qp & 0x3F);
+		s5p_mfc_write_info(ctx, shm, P_B_FRAME_QP);
+	}
+
+	/* extended encoder ctrl */
+	shm = s5p_mfc_read_info(ctx, EXT_ENC_CONTROL);
+	/** AR VUI control */
+	shm &= ~(0x1 << 15);
+	shm |= (p_264->ar_vui << 1);
+	s5p_mfc_write_info(ctx, shm, EXT_ENC_CONTROL);
+
+	if (p_264->ar_vui) {
+		/* aspect ration IDC */
+		shm = s5p_mfc_read_info(ctx, ASPECT_RATIO_IDC);
+		shm &= ~(0xFF);
+		shm |= p_264->ar_vui_idc;
+		s5p_mfc_write_info(ctx, shm, ASPECT_RATIO_IDC);
+
+		if (p_264->ar_vui_idc == 0xFF) {
+			/* sample  AR info */
+			shm = s5p_mfc_read_info(ctx, EXTENDED_SAR);
+			shm &= ~(0xFFFFFFFF);
+			shm |= p_264->ext_sar_width << 16;
+			shm |= p_264->ext_sar_height;
+			s5p_mfc_write_info(ctx, shm, EXTENDED_SAR);
+		}
+	}
+
+	/* intra picture period for H.264 */
+	shm = s5p_mfc_read_info(ctx, H264_I_PERIOD);
+	/** control */
+	shm &= ~(0x1 << 16);
+	shm |= (p_264->open_gop << 16);
+	/** value */
+	if (p_264->open_gop) {
+		shm &= ~(0xFFFF);
+		shm |= p_264->open_gop_size;
+	}
+	s5p_mfc_write_info(ctx, shm, H264_I_PERIOD);
+
+	/* set frame pack sei generation */
+	if (p_264->sei_gen_enable) {
+		/* frame packing enable */
+		shm = s5p_mfc_read_info(ctx, FRAME_PACK_SEI_ENABLE);
+		shm |= (1 << 1);
+		s5p_mfc_write_info(ctx, shm, FRAME_PACK_SEI_ENABLE);
+
+		/* set current frame0 flag & arrangement type */
+		shm = 0;
+		/** current frame0 flag */
+		shm |= ((p_264->sei_fp_curr_frame_0 & 0x1) << 2);
+		/** arrangement type
+		  *(spec. Table D-8. Definition of frame_packing_arrangement_type)
+		  */
+		shm |= (p_264->sei_fp_arrangement_type - 3) & 0x3;
+		s5p_mfc_write_info(ctx, shm, FRAME_PACK_SEI_INFO);
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
+	unsigned int reg;
+	unsigned int shm;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* pictype : number of B */
+	reg = READL(S5P_FIMV_ENC_PIC_TYPE_CTRL);
+	/** num_b_frame - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= (p->num_b_frame << 16);
+	WRITEL(reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
+
+	/* profile & level */
+	reg = READL(S5P_FIMV_ENC_PROFILE);
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= (p_mpeg4->level << 8);
+	/** profile - 0 ~ 2 */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->profile;
+	WRITEL(reg, S5P_FIMV_ENC_PROFILE);
+
+	/* quarter_pixel */
+	WRITEL(p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL);
+
+	/* qp */
+	if (p->rc_frame) {
+		shm = s5p_mfc_read_info(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF);
+		shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6);
+		shm |= (p_mpeg4->rc_p_frame_qp & 0x3F);
+		s5p_mfc_write_info(ctx, shm, P_B_FRAME_QP);
+	}
+
+	/* frame rate */
+	if (p->rc_frame) {
+		if (p_mpeg4->vop_frm_delta > 0) {
+			p_mpeg4->rc_framerate = p_mpeg4->vop_time_res /
+						p_mpeg4->vop_frm_delta;
+			/* FIXME: user set 1000x scale value */
+			WRITEL(p_mpeg4->rc_framerate * 1000,
+				S5P_FIMV_ENC_RC_FRAME_RATE);
+			shm = s5p_mfc_read_info(ctx, RC_VOP_TIMING);
+			shm &= ~(0xFFFFFFFF);
+			shm |= (1 << 31);
+			shm |= ((p_mpeg4->vop_time_res & 0x7FFF) << 16);
+			shm |= (p_mpeg4->vop_frm_delta & 0xFFFF);
+			s5p_mfc_write_info(ctx, shm, RC_VOP_TIMING);
+		}
+	} else {
+		WRITEL(0, S5P_FIMV_ENC_RC_FRAME_RATE);
+	}
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_ENC_RC_CONFIG);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_CONFIG);
+
+	/* max & min value of QP */
+	reg = READL(S5P_FIMV_ENC_RC_QBOUND);
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_mpeg4->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_QBOUND);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
+	unsigned int reg;
+	unsigned int shm;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* qp */
+	if (!p->rc_frame) {
+		shm = s5p_mfc_read_info(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF);
+		shm |= (p_mpeg4->rc_p_frame_qp & 0x3F);
+		s5p_mfc_write_info(ctx, shm, P_B_FRAME_QP);
+	}
+
+	/* frame rate */
+	if (p->rc_frame)
+		WRITEL(p_mpeg4->rc_framerate * 1000,
+			S5P_FIMV_ENC_RC_FRAME_RATE);
+	else
+		WRITEL(0, S5P_FIMV_ENC_RC_FRAME_RATE);
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_ENC_RC_CONFIG);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_CONFIG);
+
+	/* max & min value of QP */
+	reg = READL(S5P_FIMV_ENC_RC_QBOUND);
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_mpeg4->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_ENC_RC_QBOUND);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+#if 0
+/* Open a new instance and get its number */
+int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx)
+{
+	int ret;
+
+	mfc_debug_enter();
+	mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
+	ret = s5p_mfc_cmd_host2risc(ctx->dev, ctx, \
+			S5P_FIMV_H2R_CMD_OPEN_INSTANCE, ctx->codec_mode);
+	mfc_debug_leave();
+	return ret;
+}
+
+/* Close instance */
+int s5p_mfc_close_inst(struct s5p_mfc_ctx *ctx)
+{
+	int ret = 0;
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug_enter();
+	if (ctx->state != MFCINST_FREE) {
+		ret = s5p_mfc_cmd_host2risc(dev, ctx,
+			S5P_FIMV_H2R_CMD_CLOSE_INSTANCE, ctx->inst_no);
+	} else {
+		ret = -EINVAL;
+	}
+	mfc_debug_leave();
+	return ret;
+}
+#endif
+
+/* Initialize decoding */
+int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+
+	mfc_debug_enter();
+	mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, S5P_FIMV_CH_SEQ_HEADER);
+	s5p_mfc_set_shared_buffer(ctx);
+	mfc_debug(2, "BUFs: %08x %08x %08x %08x %08x\n",
+		  READL(S5P_FIMV_SI_CH0_DESC_ADR),
+		  READL(S5P_FIMV_SI_CH0_CPB_SIZE),
+		  READL(S5P_FIMV_SI_CH0_DESC_SIZE),
+		  READL(S5P_FIMV_SI_CH0_SB_ST_ADR),
+		  READL(S5P_FIMV_SI_CH0_SB_FRM_SIZE));
+	/* Setup loop filter, for decoding this is only valid for MPEG4 */
+	if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_DEC) {
+		mfc_debug(2, "Set loop filter to: %d\n", dec->loop_filter_mpeg4);
+		WRITEL(dec->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL);
+	} else {
+		WRITEL(0, S5P_FIMV_ENC_LF_CTRL);
+	}
+	/* When user sets desplay_delay to 0,
+	 * It works as "display_delay enable" and delay set to 0.
+	 * If user wants display_delay disable, It should be
+	 * set to negative value. */
+	WRITEL(((dec->slice_enable & S5P_FIMV_SLICE_INT_MASK) <<
+				S5P_FIMV_SLICE_INT_SHIFT) |
+			((dec->display_delay < 0 ? 0 : 1) <<
+			S5P_FIMV_DDELAY_ENA_SHIFT) |
+			(((dec->display_delay >= 0 ? dec->display_delay : 0) &
+			S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT),
+			S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
+	if (ctx->codec_mode == S5P_FIMV_CODEC_FIMV1_DEC) {
+		mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n",
+					ctx->img_width, ctx->img_height);
+		WRITEL(ctx->img_width, S5P_FIMV_SI_FIMV1_HRESOL);
+		WRITEL(ctx->img_height, S5P_FIMV_SI_FIMV1_VRESOL);
+	}
+
+	/* sei parse */
+	s5p_mfc_write_info(ctx, dec->sei_parse, FRAME_PACK_SEI_ENABLE);
+
+	WRITEL(((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK)
+			<< S5P_FIMV_CH_SHIFT)
+			| (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
+
+	/* Enable CRC data */
+	WRITEL(dec->crc_enable << 31, S5P_FIMV_HOST2RISC_ARG2);
+
+	mfc_debug(2, "DELAY : %x\n", READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL));
+
+	mfc_debug_leave();
+	return 0;
+}
+
+static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned int dpb;
+	if (flush)
+		dpb = READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | (1 << 14);
+	else
+		dpb = READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & ~(1 << 14);
+	WRITEL(dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
+}
+
+/* Decode a single frame */
+int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+
+	mfc_debug(2, "Setting flags to %08lx (free:%d WTF:%d)\n",
+		dec->dpb_status, ctx->dst_queue_cnt, dec->dpb_queue_cnt);
+
+	WRITEL(dec->dpb_status, S5P_FIMV_SI_CH0_RELEASE_BUF);
+	s5p_mfc_set_shared_buffer(ctx);
+	s5p_mfc_set_flush(ctx, dec->dpb_flush);
+	/* Issue different commands to instance basing on whether it
+	 * is the last frame or not. */
+	switch(last_frame) {
+	case 0:
+		WRITEL(((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) <<
+		S5P_FIMV_CH_SHIFT ) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
+		break;
+	case 1:
+		WRITEL(((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) <<
+		S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
+		break;
+	case 2:
+		WRITEL(((S5P_FIMV_CH_FRAME_START_REALLOC & S5P_FIMV_CH_MASK) <<
+		S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
+		break;
+	}
+	mfc_debug(2, "Decoding a usual frame.\n");
+	return 0;
+}
+
+int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug(2, "++\n");
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC)
+		s5p_mfc_set_enc_params_h264(ctx);
+	else if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_ENC)
+		s5p_mfc_set_enc_params_mpeg4(ctx);
+	else if (ctx->codec_mode == S5P_FIMV_CODEC_H263_ENC)
+		s5p_mfc_set_enc_params_h263(ctx);
+	else {
+		mfc_err("Unknown codec for encoding (%x).\n",
+			ctx->codec_mode);
+		return -EINVAL;
+	}
+
+	s5p_mfc_set_shared_buffer(ctx);
+
+	WRITEL(((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | (ctx->inst_no),
+		S5P_FIMV_SI_CH0_INST_ID);
+
+	mfc_debug(2, "--\n");
+
+	return 0;
+}
+
+/* Encode a single frame */
+int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug(2, "++\n");
+
+	/* memory structure cur. frame */
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
+		WRITEL(0, S5P_FIMV_ENC_MAP_FOR_CUR);
+	else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
+		WRITEL(3, S5P_FIMV_ENC_MAP_FOR_CUR);
+
+	s5p_mfc_set_shared_buffer(ctx);
+
+	WRITEL((S5P_FIMV_CH_FRAME_START << 16 & 0x70000) | (ctx->inst_no),
+		S5P_FIMV_SI_CH0_INST_ID);
+
+	mfc_debug(2, "--\n");
+
+	return 0;
+}
+
+static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
+{
+	unsigned long flags;
+	int new_ctx;
+	int cnt;
+
+	spin_lock_irqsave(&dev->condlock, flags);
+	mfc_debug(2, "Previos context: %d (bits %08lx)\n", dev->curr_ctx,
+							dev->ctx_work_bits);
+	new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
+	cnt = 0;
+	while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
+		new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
+		cnt++;
+		if (cnt > MFC_NUM_CONTEXTS) {
+			/* No contexts to run */
+			spin_unlock_irqrestore(&dev->condlock, flags);
+			return -EAGAIN;
+		}
+	}
+	spin_unlock_irqrestore(&dev->condlock, flags);
+	return new_ctx;
+}
+
+static inline void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	s5p_mfc_set_dec_desc_buffer(ctx);
+	s5p_mfc_set_dec_stream_buffer(ctx, 0, 0, 0);
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_decode_one_frame(ctx, 2);
+}
+
+static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	s5p_mfc_set_dec_desc_buffer(ctx);
+	s5p_mfc_set_dec_stream_buffer(ctx, 0, 0, 0);
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_decode_one_frame(ctx, 1);
+}
+
+static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *temp_vb;
+	unsigned long flags;
+	int last_frame = 0;
+	unsigned int index;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	/* Frames are being decoded */
+	if (list_empty(&ctx->src_queue)) {
+		mfc_debug(2, "No src buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+	/* Get the next source buffer */
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	temp_vb->used = 1;
+	mfc_debug(2, "Temp vb: %p\n", temp_vb);
+	mfc_debug(2, "Src Addr: %08lx\n", mfc_plane_cookie(&temp_vb->vb, 0));
+	s5p_mfc_set_dec_desc_buffer(ctx);
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	index = temp_vb->vb.v4l2_buf.index;
+	if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+		mfc_err("failed in set_buf_ctrls_val\n");
+
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	if (temp_vb->vb.v4l2_planes[0].bytesused == 0) {
+		last_frame = 1;
+		mfc_debug(2, "Setting ctx->state to FINISHING\n");
+		ctx->state = MFCINST_FINISHING;
+	}
+	s5p_mfc_decode_one_frame(ctx, last_frame);
+
+	return 0;
+}
+
+static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *dst_mb;
+	struct s5p_mfc_buf *src_mb;
+	unsigned long src_y_addr, src_c_addr, dst_addr;
+	/*
+	unsigned int src_y_size, src_c_size;
+	*/
+	unsigned int dst_size;
+	unsigned int index;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (list_empty(&ctx->src_queue)) {
+		mfc_debug(2, "no src buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+
+	if (list_empty(&ctx->dst_queue)) {
+		mfc_debug(2, "no dst buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+
+	src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	src_mb->used = 1;
+	src_y_addr = mfc_plane_cookie(&src_mb->vb, 0);
+	src_c_addr = mfc_plane_cookie(&src_mb->vb, 1);
+
+	mfc_debug(2, "enc src y addr: 0x%08lx", src_y_addr);
+	mfc_debug(2, "enc src c addr: 0x%08lx", src_c_addr);
+
+	s5p_mfc_set_enc_frame_buffer(ctx, src_y_addr, src_c_addr);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_mb->used = 1;
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	index = src_mb->vb.v4l2_buf.index;
+	if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+		mfc_err("failed in set_buf_ctrls_val\n");
+
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_encode_one_frame(ctx);
+
+	return 0;
+}
+
+static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *temp_vb;
+
+	/* Initializing decoding - parsing header */
+	spin_lock_irqsave(&dev->irqlock, flags);
+	mfc_debug(2, "Preparing to init decoding.\n");
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	s5p_mfc_set_dec_desc_buffer(ctx);
+	mfc_debug(2, "Header size: %d\n", temp_vb->vb.v4l2_planes[0].bytesused);
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+	dev->curr_ctx = ctx->num;
+	mfc_debug(2, "paddr: %08x\n",
+			(int)phys_to_virt(mfc_plane_cookie(&temp_vb->vb, 0)));
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_init_decode(ctx);
+}
+
+static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *dst_mb;
+	unsigned long dst_addr;
+	unsigned int dst_size;
+
+	s5p_mfc_set_enc_ref_buffer(ctx);
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	dev->curr_ctx = ctx->num;
+	mfc_debug(2, "paddr: %08x\n",
+			(int)phys_to_virt(mfc_plane_cookie(&dst_mb->vb, 0)));
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_init_encode(ctx);
+}
+
+static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *temp_vb;
+	int ret;
+	/* Header was parsed now starting processing
+	 * First set the output frame buffers
+	 * s5p_mfc_alloc_dec_buffers(ctx); */
+
+	if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
+		mfc_err("It seems that not all destionation buffers were "
+			"mmaped.\nMFC requires that all destination are mmaped "
+			"before starting processing.\n");
+		return -EAGAIN;
+	}
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (list_empty(&ctx->src_queue)) {
+		mfc_err("Header has been deallocated in the middle of "
+							"initialization.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EIO;
+	}
+
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	s5p_mfc_set_dec_desc_buffer(ctx);
+	mfc_debug(2, "Header size: %d\n", temp_vb->vb.v4l2_planes[0].bytesused);
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	ret = s5p_mfc_set_dec_frame_buffer(ctx);
+	if (ret) {
+		mfc_err("Failed to alloc frame mem.\n");
+		ctx->state = MFCINST_ERROR;
+	}
+	return ret;
+}
+
+/* Try running an operation on hardware */
+void s5p_mfc_try_run(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_ctx *ctx;
+	int new_ctx;
+	unsigned int ret = 0;
+
+	mfc_debug(1, "Try run dev: %p\n", dev);
+
+	/* Check whether hardware is not running */
+	if (test_and_set_bit(0, &dev->hw_lock) != 0) {
+		/* This is perfectly ok, the scheduled ctx should wait */
+		mfc_debug(1, "Couldn't lock HW.\n");
+		return;
+	}
+
+	/* Choose the context to run */
+	new_ctx = s5p_mfc_get_new_ctx(dev);
+	if (new_ctx < 0) {
+		/* No contexts to run */
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
+			mfc_err("Failed to unlock hardware.\n");
+			return;
+		}
+
+		mfc_debug(1, "No ctx is scheduled to be run.\n");
+		return;
+	}
+
+	mfc_debug(1, "New context: %d\n", new_ctx);
+	ctx = dev->ctx[new_ctx];
+	mfc_debug(1, "Seting new context to %p\n", ctx);
+	/* Got context to run in ctx */
+	mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
+		ctx->dst_queue_cnt, ctx->dpb_count, ctx->src_queue_cnt);
+	mfc_debug(1, "ctx->state=%d\n", ctx->state);
+	/* Last frame has already been sent to MFC
+	 * Now obtaining frames from MFC buffer */
+
+	s5p_mfc_clock_on();
+
+	if (ctx->type == MFCINST_DECODER) {
+		switch (ctx->state) {
+		case MFCINST_FINISHING:
+			s5p_mfc_run_dec_last_frames(ctx);
+			break;
+		case MFCINST_RUNNING:
+			ret = s5p_mfc_run_dec_frame(ctx);
+			break;
+		case MFCINST_INIT:
+			ret = s5p_mfc_open_inst(ctx);
+			break;
+		case MFCINST_RETURN_INST:
+			ret = s5p_mfc_close_inst(ctx);
+			break;
+		case MFCINST_GOT_INST:
+			s5p_mfc_run_init_dec(ctx);
+			break;
+		case MFCINST_HEAD_PARSED:
+			ret = s5p_mfc_run_init_dec_buffers(ctx);
+			break;
+		case MFCINST_RES_CHANGE_INIT:
+			s5p_mfc_run_res_change(ctx);
+			break;
+		case MFCINST_RES_CHANGE_FLUSH:
+			s5p_mfc_run_dec_frame(ctx);
+			break;
+		case MFCINST_RES_CHANGE_END:
+			mfc_debug(2, "Finished remaining frames after resolution change.\n");
+			ctx->capture_state = QUEUE_FREE;
+			mfc_debug(2, "Will re-init the codec`.\n");
+			s5p_mfc_run_init_dec(ctx);
+			break;
+		default:
+			ret = -EAGAIN;
+		}
+	} else if (ctx->type == MFCINST_ENCODER) {
+		switch (ctx->state) {
+		case MFCINST_FINISHING:
+		case MFCINST_RUNNING:
+			ret = s5p_mfc_run_enc_frame(ctx);
+			break;
+		case MFCINST_INIT:
+			ret = s5p_mfc_open_inst(ctx);
+			break;
+		case MFCINST_RETURN_INST:
+			ret = s5p_mfc_close_inst(ctx);
+			break;
+		case MFCINST_GOT_INST:
+			s5p_mfc_run_init_enc(ctx);
+			break;
+		default:
+			ret = -EAGAIN;
+		}
+	} else {
+		mfc_err("invalid context type: %d\n", ctx->type);
+		ret = -EAGAIN;
+	}
+
+	if (ret) {
+		/* Free hardware lock */
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
+			mfc_err("Failed to unlock hardware.\n");
+		}
+		s5p_mfc_clock_off();
+	}
+}
+
+
+/* FIXME: where is my spot? */
+void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
+{
+	struct s5p_mfc_buf *b;
+	int i;
+
+	while (!list_empty(lh)) {
+		b = list_entry(lh->next, struct s5p_mfc_buf, list);
+		for (i = 0; i < b->vb.num_planes; i++)
+			vb2_set_plane_payload(&b->vb, i, 0);
+		vb2_buffer_done(&b->vb, VB2_BUF_STATE_ERROR);
+		list_del(&b->list);
+	}
+}
+
+void s5p_mfc_write_info(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs)
+{
+	/* MFC 5.x uses shared memory for information */
+	s5p_mfc_write_shm(ctx, data, ofs);
+}
+
+unsigned int s5p_mfc_read_info(struct s5p_mfc_ctx *ctx, unsigned int ofs)
+{
+	/* MFC 5.x uses shared memory for information */
+	return s5p_mfc_read_shm(ctx, ofs);
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.h b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.h
new file mode 100644
index 0000000..cb8aa7f
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v5.h
@@ -0,0 +1,145 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_opr.h
+ *
+ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver
+ * Contains declarations of hw related functions.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef S5P_MFC_OPR_V5_H_
+#define S5P_MFC_OPR_V5_H_
+
+#include "s5p_mfc_common.h"
+#include "s5p_mfc_mem.h"
+
+#define MFC_CTRL_MODE_CUSTOM	MFC_CTRL_MODE_SHM
+
+/*
+int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev);
+int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev);
+int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev);
+int s5p_mfc_init_hw(struct s5p_mfc_dev *dev);
+*/
+
+int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx);
+/*
+void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev);
+int s5p_mfc_set_sleep(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_set_wakeup(struct s5p_mfc_ctx *ctx);
+*/
+
+int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
+						  unsigned int start_num_byte,
+						  unsigned int buf_size);
+
+void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long y_addr, unsigned long c_addr);
+int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long addr, unsigned int size);
+void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long *y_addr, unsigned long *c_addr);
+int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *mfc_ctx);
+
+int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame);
+int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *mfc_ctx);
+
+/* Instance handling */
+/*
+int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_return_inst_no(struct s5p_mfc_ctx *ctx);
+*/
+
+/* Memory allocation */
+int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
+
+int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx);
+
+int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_alloc_dev_context_buffer(struct s5p_mfc_dev *dev);
+void s5p_mfc_release_dev_context_buffer(struct s5p_mfc_dev *dev);
+
+void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx);
+
+#define s5p_mfc_get_dspl_y_adr()	(readl(dev->regs_base + \
+					S5P_FIMV_SI_DISPLAY_Y_ADR) << 11)
+#define s5p_mfc_get_dspl_status()	readl(dev->regs_base + \
+						S5P_FIMV_SI_DISPLAY_STATUS)
+#define s5p_mfc_get_dec_frame_type()	(readl(dev->regs_base + \
+						S5P_FIMV_DECODE_FRAME_TYPE) \
+					& S5P_FIMV_DECODE_FRAME_MASK)
+#define s5p_mfc_get_disp_frame_type()	((s5p_mfc_read_shm(ctx, DISP_PIC_FRAME_TYPE) \
+						>> S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) \
+						& S5P_FIMV_DECODE_FRAME_MASK)
+#define s5p_mfc_get_consumed_stream()	readl(dev->regs_base + \
+						S5P_FIMV_SI_CONSUMED_BYTES)
+#define s5p_mfc_get_int_reason()	(readl(dev->regs_base + \
+					S5P_FIMV_RISC2HOST_CMD) & \
+					S5P_FIMV_RISC2HOST_CMD_MASK)
+#define s5p_mfc_get_int_err()		readl(dev->regs_base + \
+						S5P_FIMV_RISC2HOST_ARG2)
+#define s5p_mfc_err_dec(x)		(((x) & S5P_FIMV_ERR_DEC_MASK) >> \
+						S5P_FIMV_ERR_DEC_SHIFT)
+#define s5p_mfc_err_dspl(x)		(((x) & S5P_FIMV_ERR_DSPL_MASK) >> \
+						S5P_FIMV_ERR_DSPL_SHIFT)
+#define s5p_mfc_get_img_width()		readl(dev->regs_base + \
+						S5P_FIMV_SI_HRESOL)
+#define s5p_mfc_get_img_height()	readl(dev->regs_base + \
+						S5P_FIMV_SI_VRESOL)
+#define s5p_mfc_get_dpb_count()		readl(dev->regs_base + \
+						S5P_FIMV_SI_BUF_NUMBER)
+#define s5p_mfc_get_inst_no()		readl(dev->regs_base + \
+						S5P_FIMV_RISC2HOST_ARG1)
+#define s5p_mfc_get_mv_count()		0
+#define s5p_mfc_get_mvc_num_views()	-1
+#define s5p_mfc_get_mvc_disp_view_id()	-1
+#define s5p_mfc_get_enc_dpb_count()	-1
+#define s5p_mfc_get_enc_strm_size()	readl(dev->regs_base + \
+						S5P_FIMV_ENC_SI_STRM_SIZE)
+#define s5p_mfc_get_enc_slice_type()	readl(dev->regs_base + \
+						S5P_FIMV_ENC_SI_SLICE_TYPE)
+#define s5p_mfc_get_enc_pic_count()	readl(dev->regs_base + \
+						S5P_FIMV_ENC_SI_PIC_CNT)
+#define s5p_mfc_get_sei_avail_status()	s5p_mfc_read_shm(ctx, FRAME_PACK_SEI_AVAIL)
+
+#define s5p_mfc_clear_int_flags()				\
+	do {							\
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC_HOST_INT);	\
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC2HOST_CMD);	\
+		s5p_mfc_write_reg(0xffff, S5P_FIMV_SI_RTN_CHID);\
+	} while (0)
+
+/* Definition */
+#define ENC_MULTI_SLICE_MB_MAX		((1 << 16) - 1)
+#define ENC_MULTI_SLICE_BIT_MIN		1900
+#define ENC_MULTI_SLICE_BYTE_MIN	238
+#define ENC_INTRA_REFRESH_MB_MAX	((1 << 16) - 1)
+#define ENC_VBV_BUF_SIZE_MAX		((1 << 16) - 1)
+#define ENC_H264_LOOP_FILTER_AB_MIN	-6
+#define ENC_H264_LOOP_FILTER_AB_MAX	6
+#define ENC_H264_RC_FRAME_RATE_MAX	((1 << 30) - 1)
+#define ENC_H263_RC_FRAME_RATE_MAX	((1 << 30) - 1)
+#define ENC_H264_PROFILE_MAX		2
+#define ENC_H264_LEVEL_MAX		40
+#define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 15) - 1)
+
+void s5p_mfc_try_run(struct s5p_mfc_dev *dev);
+
+void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
+
+void s5p_mfc_write_info(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs);
+unsigned int s5p_mfc_read_info(struct s5p_mfc_ctx *ctx, unsigned int ofs);
+
+#endif /* S5P_MFC_OPR_V5_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.c
new file mode 100644
index 0000000..e6965da
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.c
@@ -0,0 +1,1907 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_opr.c
+ *
+ * Samsung MFC (Multi Function Codec - FIMV) driver
+ * This file contains hw related functions.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG
+
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+
+#include <linux/firmware.h>
+#include <linux/err.h>
+#include <linux/sched.h>
+#include <linux/cma.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_cmd.h"
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_intr.h"
+#include "s5p_mfc_inst.h"
+#include "s5p_mfc_pm.h"
+#include "s5p_mfc_debug.h"
+
+#if defined(CONFIG_S5P_MFC_VB2_CMA)
+#include <media/videobuf2-cma-phys.h>
+#endif
+
+/* #define S5P_MFC_DEBUG_REGWRITE  */
+#ifdef S5P_MFC_DEBUG_REGWRITE
+#undef writel
+#define writel(v, r) do { \
+	printk(KERN_ERR "MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
+	__raw_writel(v, r); } while (0)
+#endif /* S5P_MFC_DEBUG_REGWRITE */
+
+#define READL(offset)		readl(dev->regs_base + (offset))
+#define WRITEL(data, offset)	writel((data), dev->regs_base + (offset))
+#define OFFSETA(x)		(((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
+#define OFFSETB(x)		(((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
+
+/* Allocate temporary buffers for decoding */
+int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx)
+{
+	/* NOP */
+
+	return 0;
+}
+
+/* Release temproary buffers for decoding */
+void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
+{
+	/* NOP */
+}
+
+/* Allocate codec buffers */
+int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	unsigned int mb_width, mb_height;
+
+	mfc_debug_enter();
+
+	mb_width = mb_width(ctx->img_width);
+	mb_height = mb_height(ctx->img_height);
+
+	if (ctx->type == MFCINST_DECODER) {
+		mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
+			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
+		mfc_debug(2, "Totals bufs: %d\n", dec->total_dpb_count);
+	} else if (ctx->type == MFCINST_ENCODER) {
+		enc->tmv_buffer_size = ENC_TMV_SIZE(mb_width, mb_height);
+		enc->tmv_buffer_size = ALIGN(enc->tmv_buffer_size, 32) * 2;
+		enc->luma_dpb_size = ALIGN((mb_width * mb_height) * 256, 256);
+		enc->chroma_dpb_size = ALIGN((mb_width * mb_height) * 128, 256);
+		enc->me_buffer_size =
+			(ENC_ME_SIZE(ctx->img_width, ctx->img_height, mb_width, mb_height));
+		enc->me_buffer_size = ALIGN(enc->me_buffer_size, 256);
+
+		mfc_debug(2, "recon luma size: %d chroma size: %d\n",
+			  enc->luma_dpb_size, enc->chroma_dpb_size);
+	} else {
+		return -EINVAL;
+	}
+
+	/* Codecs have different memory requirements */
+	switch (ctx->codec_mode) {
+	case S5P_FIMV_CODEC_H264_DEC:
+	case S5P_FIMV_CODEC_H264_MVC_DEC:
+		if (dev->fw.date < 0x120206)
+			dec->mv_count = dec->total_dpb_count;
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_H264_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_H264_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size =
+			ctx->scratch_buf_size +
+			(dec->mv_count * ctx->mv_size);
+		break;
+	case S5P_FIMV_CODEC_MPEG4_DEC:
+	case S5P_FIMV_CODEC_FIMV1_DEC:
+	case S5P_FIMV_CODEC_FIMV2_DEC:
+	case S5P_FIMV_CODEC_FIMV3_DEC:
+	case S5P_FIMV_CODEC_FIMV4_DEC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size = ctx->scratch_buf_size;
+		break;
+	case S5P_FIMV_CODEC_VC1RCV_DEC:
+	case S5P_FIMV_CODEC_VC1_DEC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_VC1_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_VC1_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size = ctx->scratch_buf_size;
+		break;
+	case S5P_FIMV_CODEC_MPEG2_DEC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_MPEG2_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_MPEG2_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->port_a_size = 0;
+		ctx->port_b_size = 0;
+		break;
+	case S5P_FIMV_CODEC_H263_DEC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size = ctx->scratch_buf_size;
+		break;
+	case S5P_FIMV_CODEC_VP8_DEC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				DEC_V61_VP8_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				DEC_V65_VP8_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size = ctx->scratch_buf_size;
+		break;
+	case S5P_FIMV_CODEC_H264_ENC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				ENC_V61_H264_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				ENC_V65_H264_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size =
+			ctx->scratch_buf_size + enc->tmv_buffer_size +
+			(ctx->dpb_count * (enc->luma_dpb_size +
+			enc->chroma_dpb_size + enc->me_buffer_size));
+		ctx->port_b_size = 0;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_ENC:
+	case S5P_FIMV_CODEC_H263_ENC:
+		if (dev->fw.ver == 0x61)
+			ctx->scratch_buf_size =
+				ENC_V61_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		else
+			ctx->scratch_buf_size =
+				ENC_V65_MPEG4_SCRATCH_SIZE(mb_width, mb_height);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->port_a_size =
+			ctx->scratch_buf_size + enc->tmv_buffer_size +
+			(ctx->dpb_count * (enc->luma_dpb_size +
+			enc->chroma_dpb_size + enc->me_buffer_size));
+		ctx->port_b_size = 0;
+		break;
+	default:
+		break;
+	}
+
+	/* Allocate only if memory from bank 1 is necessary */
+	if (ctx->port_a_size > 0) {
+		ctx->port_a_buf = s5p_mfc_mem_allocate(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->port_a_size);
+		if (IS_ERR(ctx->port_a_buf)) {
+			ctx->port_a_buf = 0;
+			printk(KERN_ERR
+			       "Buf alloc for decoding failed (port A).\n");
+			return -ENOMEM;
+		}
+		ctx->port_a_phys = s5p_mfc_mem_dma_addr(ctx->port_a_buf);
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release buffers allocated for codec */
+void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	if (ctx->port_a_buf) {
+		s5p_mfc_mem_free(ctx->port_a_buf);
+		ctx->port_a_buf = 0;
+		ctx->port_a_phys = 0;
+		ctx->port_a_size = 0;
+	}
+}
+
+/* Allocate memory for instance data buffer */
+int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->buf;
+
+	mfc_debug_enter();
+
+	switch(ctx->codec_mode) {
+	case S5P_FIMV_CODEC_H264_DEC:
+	case S5P_FIMV_CODEC_H264_MVC_DEC:
+		ctx->ctx_buf_size = buf_size->h264_dec_ctx;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_DEC:
+	case S5P_FIMV_CODEC_H263_DEC:
+	case S5P_FIMV_CODEC_VC1RCV_DEC:
+	case S5P_FIMV_CODEC_VC1_DEC:
+	case S5P_FIMV_CODEC_MPEG2_DEC:
+	case S5P_FIMV_CODEC_VP8_DEC:
+	case S5P_FIMV_CODEC_FIMV1_DEC:
+	case S5P_FIMV_CODEC_FIMV2_DEC:
+	case S5P_FIMV_CODEC_FIMV3_DEC:
+	case S5P_FIMV_CODEC_FIMV4_DEC:
+		ctx->ctx_buf_size = buf_size->other_dec_ctx;
+		break;
+	case S5P_FIMV_CODEC_H264_ENC:
+		ctx->ctx_buf_size = buf_size->h264_enc_ctx;
+		break;
+	case S5P_FIMV_CODEC_MPEG4_ENC:
+	case S5P_FIMV_CODEC_H263_ENC:
+		ctx->ctx_buf_size = buf_size->other_enc_ctx;
+		break;
+	default:
+		ctx->ctx_buf_size = 0;
+		mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
+		break;
+	}
+
+	ctx->ctx.alloc = s5p_mfc_mem_allocate(
+		dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], ctx->ctx_buf_size);
+	if (IS_ERR(ctx->ctx.alloc)) {
+		mfc_err("Allocating context buffer failed.\n");
+		return PTR_ERR(ctx->ctx.alloc);
+	}
+
+	ctx->ctx.ofs = s5p_mfc_mem_dma_addr(ctx->ctx.alloc);
+
+	ctx->ctx.virt = s5p_mfc_mem_vaddr(ctx->ctx.alloc);
+	if (!ctx->ctx.virt) {
+		s5p_mfc_mem_free(ctx->ctx.alloc);
+		ctx->ctx.alloc = NULL;
+		ctx->ctx.ofs = 0;
+		ctx->ctx.virt = NULL;
+
+		mfc_err("Remapping context buffer failed.\n");
+		return -ENOMEM;
+	}
+
+	memset(ctx->ctx.virt, 0, ctx->ctx_buf_size);
+	s5p_mfc_cache_clean_fw(ctx->ctx.alloc);
+	/*
+	ctx->ctx.dma = dma_map_single(ctx->dev->v4l2_dev.dev,
+					  ctx->ctx.virt, ctx->ctx_buf_size,
+					  DMA_TO_DEVICE);
+	*/
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release instance buffer */
+void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx)
+{
+	mfc_debug_enter();
+
+	if (ctx->ctx.alloc) {
+		/*
+		dma_unmap_single(ctx->dev->v4l2_dev.dev,
+				ctx->ctx.dma, ctx->ctx_buf_size,
+				DMA_TO_DEVICE);
+		*/
+		s5p_mfc_mem_free(ctx->ctx.alloc);
+		ctx->ctx.alloc = NULL;
+		ctx->ctx.ofs = 0;
+		ctx->ctx.virt = NULL;
+	}
+
+	mfc_debug_leave();
+}
+
+/* Allocate context buffers for SYS_INIT */
+int s5p_mfc_alloc_dev_context_buffer(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->buf;
+
+	mfc_debug_enter();
+
+	dev->ctx_buf.alloc = s5p_mfc_mem_allocate(
+			dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX], buf_size->dev_ctx);
+	if (IS_ERR(dev->ctx_buf.alloc)) {
+		mfc_err("Allocating DESC buffer failed.\n");
+		return PTR_ERR(dev->ctx_buf.alloc);
+	}
+
+	dev->ctx_buf.ofs = s5p_mfc_mem_dma_addr(dev->ctx_buf.alloc);
+
+	dev->ctx_buf.virt = s5p_mfc_mem_vaddr(dev->ctx_buf.alloc);
+	if (!dev->ctx_buf.virt) {
+		s5p_mfc_mem_free(dev->ctx_buf.alloc);
+		dev->ctx_buf.alloc = NULL;
+		dev->ctx_buf.ofs = 0;
+
+		mfc_err("Remapping DESC buffer failed.\n");
+		return -ENOMEM;
+	}
+
+	memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
+	s5p_mfc_cache_clean_fw(dev->ctx_buf.alloc);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Release context buffers for SYS_INIT */
+void s5p_mfc_release_dev_context_buffer(struct s5p_mfc_dev *dev)
+{
+	if (dev->ctx_buf.alloc) {
+		s5p_mfc_mem_free(dev->ctx_buf.alloc);
+		dev->ctx_buf.alloc = NULL;
+		dev->ctx_buf.ofs = 0;
+		dev->ctx_buf.virt = NULL;
+	}
+}
+
+static int calc_plane(int width, int height)
+{
+	int mbX, mbY;
+
+	mbX = (width + 15)/16;
+	mbY = (height + 15)/16;
+
+	if (width * height < 2048 * 1024)
+		mbY = (mbY + 1) / 2 * 2;
+
+	return (mbX * 16) * (mbY * 16);
+}
+
+void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx)
+{
+	/* FIXME: Need to check the alignment value */
+	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
+	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
+	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
+			"buffer dimensions: %dx%d\n", ctx->img_width,
+			ctx->img_height, ctx->buf_width, ctx->buf_height);
+
+	ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
+	ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
+			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) {
+		ctx->mv_size = s5p_mfc_dec_mv_size(ctx->img_width,
+				ctx->img_height);
+		ctx->mv_size = ALIGN(ctx->mv_size, 16);
+	} else {
+		ctx->mv_size = 0;
+	}
+}
+
+void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx)
+{
+	unsigned int mb_width, mb_height;
+
+	mb_width = mb_width(ctx->img_width);
+	mb_height = mb_height(ctx->img_height);
+
+	/* FIXME: why buf_width is needed ? */
+	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN);
+	ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
+	ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
+}
+
+/* Set registers for decoding stream buffer */
+int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
+		  unsigned int start_num_byte, unsigned int strm_size)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
+
+	mfc_debug_enter();
+	mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x, buf_size: 0x"
+		"%08x (%d)\n",  ctx->inst_no, buf_addr, strm_size, strm_size);
+
+	WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE);
+	WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR);
+	WRITEL(buf_size->cpb_buf, S5P_FIMV_D_CPB_BUFFER_SIZE);
+	WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET);
+
+	mfc_debug_leave();
+	return 0;
+}
+
+/* Set decoding frame buffer */
+int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx)
+{
+	unsigned int frame_size, i;
+	unsigned int frame_size_ch, frame_size_mv;
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	size_t buf_addr1;
+	int buf_size1;
+	int align_gap;
+	struct s5p_mfc_buf *buf;
+	struct list_head *buf_queue;
+	unsigned char *dpb_vir;
+
+	buf_addr1 = ctx->port_a_phys;
+	buf_size1 = ctx->port_a_size;
+
+	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
+	mfc_debug(2, "Total DPB COUNT: %d\n", dec->total_dpb_count);
+	mfc_debug(2, "Setting display delay to %d\n", dec->display_delay);
+
+	WRITEL(dec->total_dpb_count, S5P_FIMV_D_NUM_DPB);
+	WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE);
+	WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE);
+
+	WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR);
+	WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE);
+	buf_addr1 += ctx->scratch_buf_size;
+	buf_size1 -= ctx->scratch_buf_size;
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
+			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC)
+		WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE);
+
+	frame_size = ctx->luma_size;
+	frame_size_ch = ctx->chroma_size;
+	frame_size_mv = ctx->mv_size;
+	mfc_debug(2, "Frame size: %d ch: %d mv: %d\n", frame_size, frame_size_ch,
+								frame_size_mv);
+
+	if (dec->dst_memtype == V4L2_MEMORY_USERPTR)
+		buf_queue = &ctx->dst_queue;
+	else
+		buf_queue = &dec->dpb_queue;
+
+	i = 0;
+	list_for_each_entry(buf, buf_queue, list) {
+		mfc_debug(2, "Luma %x\n", buf->cookie.raw.luma);
+		WRITEL(buf->cookie.raw.luma, S5P_FIMV_D_LUMA_DPB + i * 4);
+		mfc_debug(2, "\tChroma %x\n", buf->cookie.raw.chroma);
+		WRITEL(buf->cookie.raw.chroma, S5P_FIMV_D_CHROMA_DPB + i * 4);
+
+		if (i == 0) {
+			dpb_vir = vb2_plane_vaddr(&buf->vb, 0);
+			memset(dpb_vir, 0x0, ctx->luma_size);
+			s5p_mfc_cache_inv(&buf->vb, 0);
+
+			dpb_vir = vb2_plane_vaddr(&buf->vb, 1);
+			memset(dpb_vir, 0x80, ctx->chroma_size);
+			s5p_mfc_cache_inv(&buf->vb, 1);
+		}
+		i++;
+	}
+
+	WRITEL(dec->mv_count, S5P_FIMV_D_NUM_MV);
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
+			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) {
+		for (i = 0; i < dec->mv_count; i++) {
+			/* To test alignment */
+			align_gap = buf_addr1;
+			buf_addr1 = ALIGN(buf_addr1, 16);
+			align_gap = buf_addr1 - align_gap;
+			buf_size1 -= align_gap;
+
+			mfc_debug(2, "\tBuf1: %x, size: %d\n", buf_addr1, buf_size1);
+			WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER + i * 4);
+			buf_addr1 += frame_size_mv;
+			buf_size1 -= frame_size_mv;
+		}
+	}
+
+	mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
+			buf_addr1, buf_size1, dec->total_dpb_count);
+	if (buf_size1 < 0) {
+		mfc_debug(2, "Not enough memory has been allocated.\n");
+		return -ENOMEM;
+	}
+
+	/* FIXME: Is it needed? */
+#if 0
+	s5p_mfc_write_info(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
+	s5p_mfc_write_info(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC)
+		s5p_mfc_write_info(ctx, frame_size_mv, ALLOC_MV_SIZE);
+#endif
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	s5p_mfc_cmd_host2risc(S5P_FIMV_CH_INIT_BUFS, NULL);
+
+	mfc_debug(2, "After setting buffers.\n");
+	return 0;
+}
+
+/* Set registers for encoding stream buffer */
+int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long addr, unsigned int size)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR); /* 16B align */
+	WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE);
+
+	mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d",
+		addr, size);
+
+	return 0;
+}
+
+void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long y_addr, unsigned long c_addr)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR); /* 256B align */
+	WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR);
+
+	mfc_debug(2, "enc src y buf addr: 0x%08lx", y_addr);
+	mfc_debug(2, "enc src c buf addr: 0x%08lx", c_addr);
+}
+
+void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long *y_addr, unsigned long *c_addr)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long enc_recon_y_addr, enc_recon_c_addr;
+
+	*y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR);
+	*c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR);
+
+	enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR);
+	enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR);
+
+	mfc_debug(2, "recon y addr: 0x%08lx", enc_recon_y_addr);
+	mfc_debug(2, "recon c addr: 0x%08lx", enc_recon_c_addr);
+}
+
+/* Set encoding ref & codec buffer */
+int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	size_t buf_addr1;
+	int buf_size1;
+	int i;
+
+	mfc_debug_enter();
+
+	buf_addr1 = ctx->port_a_phys;
+	buf_size1 = ctx->port_a_size;
+
+	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
+
+	for (i = 0; i < ctx->dpb_count; i++) {
+		WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB + (4 * i));
+		buf_addr1 += enc->luma_dpb_size;
+		WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB + (4 * i));
+		buf_addr1 += enc->chroma_dpb_size;
+		WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER + (4 * i));
+		buf_addr1 += enc->me_buffer_size;
+		buf_size1 -= (enc->luma_dpb_size + enc->chroma_dpb_size +
+			enc->me_buffer_size);
+	}
+
+	WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR);
+	WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE);
+	buf_addr1 += ctx->scratch_buf_size;
+	buf_size1 -= ctx->scratch_buf_size;
+
+	WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0);
+	buf_addr1 += enc->tmv_buffer_size >> 1;
+	WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1);
+	buf_addr1 += enc->tmv_buffer_size >> 1;
+	buf_size1 -= enc->tmv_buffer_size;
+
+	mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
+			buf_addr1, buf_size1, ctx->dpb_count);
+	if (buf_size1 < 0) {
+		mfc_debug(2, "Not enough memory has been allocated.\n");
+		return -ENOMEM;
+	}
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	s5p_mfc_cmd_host2risc(S5P_FIMV_CH_INIT_BUFS, NULL);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+
+	/* multi-slice control */
+	WRITEL(enc->slice_mode, S5P_FIMV_E_MSLICE_MODE);
+	/* multi-slice MB number or bit size */
+	if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
+		WRITEL(enc->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB);
+	} else if (enc->slice_mode == \
+			V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
+		WRITEL(enc->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS);
+	} else {
+		WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB);
+		WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS);
+	}
+
+	return 0;
+
+}
+
+static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	unsigned int reg = 0;
+
+	mfc_debug_enter();
+	/* width */
+	WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH); /* 16 align */
+	/* height */
+	WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT); /* 16 align */
+
+	/* crop information FIXME: Is it really needed */
+	/** cropped width */
+	WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH);
+	/** cropped height */
+	WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT);
+	/** cropped offset */
+	WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET);
+
+	/* pictype : IDR period */
+	/* FIXME: it should be applied at NAL_start */
+	reg = 0;
+	reg &= ~(0xffff);
+	reg |= p->gop_size;
+	WRITEL(reg, S5P_FIMV_E_GOP_CONFIG);
+
+	/* multi-slice control */
+	/* multi-slice MB number or bit size */
+	reg = 0;
+	enc->slice_mode = p->slice_mode;
+
+	if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
+		/* reg |= (0x1 << 3); */
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+		enc->slice_size.mb = p->slice_mb;
+	} else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
+		/* reg |= (0x1 << 3); */
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+		enc->slice_size.bits = p->slice_bit;
+	} else {
+		reg &= ~(0x1 << 3);
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+	}
+
+	s5p_mfc_set_slice_mode(ctx);
+
+	/* cyclic intra refresh */
+	/* FIXME: it should be applied at NAL_start */
+	WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE);
+	reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+	if (p->intra_refresh_mb == 0)
+		reg &= ~(0x1 << 4);
+	else
+		reg |= (0x1 << 4);
+	WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+
+	/* 'NON_REFERENCE_STORE_ENABLE' for debugging */
+	reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+	reg &= ~(0x1 << 9);
+	WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+
+	/* memory structure cur. frame */
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
+		/* 0: Linear, 1: 2D tiled*/
+		reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+		reg &= ~(0x1 << 7);
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+		/* 0: NV12(CbCr), 1: NV21(CrCb) */
+		WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT);
+	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
+		/* 0: Linear, 1: 2D tiled*/
+		reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+		reg &= ~(0x1 << 7);
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+		/* 0: NV12(CbCr), 1: NV21(CrCb) */
+		WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT);
+	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
+		/* 0: Linear, 1: 2D tiled*/
+		reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+		reg |= (0x1 << 7);
+		WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+		/* 0: NV12(CbCr), 1: NV21(CrCb) */
+		WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT);
+	}
+
+	/* memory structure recon. frame */
+	/* 0: Linear, 1: 2D tiled */
+	reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+	reg |= (0x1 << 8);
+	WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+
+	/* padding control & value */
+	WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL);
+	if (p->pad) {
+		reg = 0;
+		/** enable */
+		reg |= (1 << 31);
+		/** cr value */
+		reg &= ~(0xFF << 16);
+		reg |= (p->pad_cr << 16);
+		/** cb value */
+		reg &= ~(0xFF << 8);
+		reg |= (p->pad_cb << 8);
+		/** y value */
+		reg &= ~(0xFF);
+		reg |= (p->pad_luma);
+		WRITEL(reg, S5P_FIMV_E_PADDING_CTRL);
+	}
+
+	/* rate control config. */
+	reg = 0;
+	/** frame-level rate control */
+	reg &= ~(0x1 << 9);
+	reg |= (p->rc_frame << 9);
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+
+	/* bit rate */
+	if (p->rc_frame)
+		WRITEL(p->rc_bitrate,
+			S5P_FIMV_E_RC_BIT_RATE);
+	else
+		WRITEL(1, S5P_FIMV_E_RC_BIT_RATE);
+
+	/* reaction coefficient, fixed value set from FW_111021*/
+	if (p->rc_frame) {
+		if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
+			WRITEL(1, S5P_FIMV_E_RC_RPARAM);
+		else				/* loose CBR */
+			WRITEL(2, S5P_FIMV_E_RC_RPARAM);
+	}
+
+	/* extended encoder ctrl */
+	/** vbv buffer size */
+	if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT)
+		WRITEL(p->vbv_buf_size, S5P_FIMV_E_VBV_BUFFER_SIZE);
+
+	/** seq header ctrl */
+	reg = READL(S5P_FIMV_E_ENC_OPTIONS);
+	reg &= ~(0x1 << 2);
+	reg |= (p->seq_hdr_mode << 2);
+	/** frame skip mode */
+	reg &= ~(0x3);
+	reg |= (p->frame_skip_mode);
+	WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS);
+
+	/* fixed target bit */
+	/* s5p_mfc_write_info(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); */
+
+	/* 'DROP_CONTROL_ENABLE', disable */
+	reg = READL(S5P_FIMV_E_RC_CONFIG);
+	reg &= ~(0x1 << 10);
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+
+	/* setting for MV range [16, 256] */
+	if (dev->fw.ver == 0x61)
+		reg = ENC_V61_MV_RANGE;
+	else
+		reg = ENC_V65_MV_RANGE;
+
+	WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE);
+	WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE);
+
+	WRITEL(0x0, S5P_FIMV_E_VBV_INIT_DELAY); /* SEQ_start Only */
+
+	/* initialize for '0' only setting */
+	WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG); /* NAL_start Only */
+
+	WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT); /* NAL_start Only */
+
+	WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR); /* NAL_start Only */
+	WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE); /* NAL_start Only */
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264;
+	unsigned int reg = 0;
+	int i;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* pictype : number of B */
+	reg = READL(S5P_FIMV_E_GOP_CONFIG);
+	/** num_b_frame - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= (p->num_b_frame << 16);
+	WRITEL(reg, S5P_FIMV_E_GOP_CONFIG);
+
+	/* profile & level */
+	reg = 0;
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= (p_264->level << 8);
+	/** profile - 0 ~ 3 */
+	reg &= ~(0x3F);
+	reg |= p_264->profile;
+	WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE);
+
+	/* interlace */
+	reg = 0;
+	reg &= ~(0x1 << 3);
+	reg |= (p_264->interlace << 3);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/** height */
+	if (p_264->interlace) {
+		WRITEL(ctx->img_height >> 1, S5P_FIMV_E_FRAME_HEIGHT); /* 32 align */
+		/** cropped height */
+		WRITEL(ctx->img_height >> 1, S5P_FIMV_E_CROPPED_FRAME_HEIGHT);
+	}
+
+	/* loop filter ctrl */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x3 << 1);
+	reg |= (p_264->loop_filter_mode << 1);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* loopfilter alpha offset */
+	if (p_264->loop_filter_alpha < 0) {
+		reg = 0x10;
+		reg |= (0xFF - p_264->loop_filter_alpha) + 1;
+	} else {
+		reg = 0x00;
+		reg |= (p_264->loop_filter_alpha & 0xF);
+	}
+	WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET);
+
+	/* loopfilter beta offset */
+	if (p_264->loop_filter_beta < 0) {
+		reg = 0x10;
+		reg |= (0xFF - p_264->loop_filter_beta) + 1;
+	} else {
+		reg = 0x00;
+		reg |= (p_264->loop_filter_beta & 0xF);
+	}
+	WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET);
+
+	/* entropy coding mode */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1);
+	reg |= (p_264->entropy_mode);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* number of ref. picture */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1 << 7);
+	reg |= ((p_264->num_ref_pic_4p-1) << 7);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* 8x8 transform enable */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x3 << 12);
+	reg |= (p_264->_8x8_transform << 12);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_E_RC_CONFIG);
+	/** macroblock level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= (p->rc_mb << 8);
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_264->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+
+	/* frame rate */
+	/* Fix value for H.264, H.263 in the driver */
+	/* FIXME: it should be applied at NAL_start */
+	p->rc_frame_delta = FRAME_DELTA_H264_H263;
+	if (p->rc_frame) {
+		/* FIXME: user set 1000x scale value */
+		reg = 0;
+		reg &= ~(0xffff << 16);
+		reg |= ((p_264->rc_framerate * p->rc_frame_delta) << 16);
+		reg &= ~(0xffff);
+		reg |= p->rc_frame_delta;
+		WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE);
+	}
+
+	/* max & min value of QP */
+	reg = 0;
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_264->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_264->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND);
+
+	/* macroblock adaptive scaling features */
+	WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG);
+	if (p->rc_mb) {
+		reg = 0;
+		/** dark region */
+		reg &= ~(0x1 << 3);
+		reg |= (p_264->rc_mb_dark << 3);
+		/** smooth region */
+		reg &= ~(0x1 << 2);
+		reg |= (p_264->rc_mb_smooth << 2);
+		/** static region */
+		reg &= ~(0x1 << 1);
+		reg |= (p_264->rc_mb_static << 1);
+		/** high activity region */
+		reg &= ~(0x1);
+		reg |= p_264->rc_mb_activity;
+		WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG);
+	}
+
+	WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP);
+	if (!p->rc_frame && !p->rc_mb) {
+		reg = 0;
+		reg &= ~(0x3f << 16);
+		reg |= (p_264->rc_b_frame_qp << 16);
+		reg &= ~(0x3f << 8);
+		reg |= (p_264->rc_p_frame_qp << 8);
+		reg &= ~(0x3f);
+		reg |= p_264->rc_frame_qp;
+		WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP);
+	}
+
+	/* extended encoder ctrl */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1 << 5);
+	reg |= (p_264->ar_vui << 5);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO);
+	WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR);
+	if (p_264->ar_vui) {
+		/* aspect ration IDC */
+		reg = 0;
+		reg &= ~(0xff);
+		reg |= p_264->ar_vui_idc;
+		WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO);
+		if (p_264->ar_vui_idc == 0xFF) {
+			/* sample  AR info. */
+			reg = 0;
+			reg &= ~(0xffffffff);
+			reg |= p_264->ext_sar_width << 16;
+			reg |= p_264->ext_sar_height;
+			WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR);
+		}
+	}
+
+	/* intra picture period for H.264 open GOP */
+	/** control */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1 << 4);
+	reg |= (p_264->open_gop << 4);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+	/** value */
+	WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD);
+	if (p_264->open_gop) {
+		reg = 0;
+		reg &= ~(0xffff);
+		reg |= p_264->open_gop_size;
+		WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD);
+	}
+
+	/* 'WEIGHTED_BI_PREDICTION' for B is disable */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x3 << 9);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1 << 14);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* ASO enable */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	if (p_264->aso_enable)
+		reg |= (0x1 << 6);
+	else
+		reg &= ~(0x1 << 6);
+	WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+	/* hier qp enable */
+	reg = READL(S5P_FIMV_E_H264_OPTIONS);
+	reg &= ~(0x1 << 8);
+	reg |= ((p_264->open_gop & 0x1) << 8);
+		WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+	reg = 0;
+	if (p_264->hier_qp && p_264->hier_qp_layer) {
+		reg |= (p_264->hier_qp_type & 0x1) << 0x3;
+		reg |= p_264->hier_qp_layer & 0x7;
+		WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER);
+		/* QP value for each layer */
+		for (i = 0; i < (p_264->hier_qp_layer & 0x7); i++)
+			WRITEL(p_264->hier_qp_layer_qp[i],
+				S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0 + i * 4);
+	}
+	/* number of coding layer should be zero when hierarchical is disable */
+	WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER);
+
+	/* set frame pack sei generation */
+	if (p_264->sei_gen_enable) {
+		/* frame packing enable */
+		reg = READL(S5P_FIMV_E_H264_OPTIONS);
+		reg |= (1 << 25);
+		WRITEL(reg, S5P_FIMV_E_H264_OPTIONS);
+
+		/* set current frame0 flag & arrangement type */
+		reg = 0;
+		/** current frame0 flag */
+		reg |= ((p_264->sei_fp_curr_frame_0 & 0x1) << 2);
+		/** arrangement type */
+		reg |= (p_264->sei_fp_arrangement_type - 3) & 0x3;
+		WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO);
+	}
+
+	if (p_264->fmo_enable) {
+		switch(p_264->fmo_slice_map_type) {
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
+			if (p_264->fmo_slice_num_grp > 4)
+				p_264->fmo_slice_num_grp = 4;
+			for (i = 0; i < (p_264->fmo_slice_num_grp & 0xF); i++)
+				WRITEL(p_264->fmo_run_length[i] - 1,
+				S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0 + i*4);
+			break;
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
+			if (p_264->fmo_slice_num_grp > 4)
+				p_264->fmo_slice_num_grp = 4;
+			break;
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
+		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
+			if (p_264->fmo_slice_num_grp > 2)
+				p_264->fmo_slice_num_grp = 2;
+			WRITEL(p_264->fmo_sg_dir & 0x1,
+				S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR);
+			/* the valid range is 0 ~ number of macroblocks -1 */
+			WRITEL(p_264->fmo_sg_rate, S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1);
+			break;
+		default:
+			mfc_err("Unsupported map type for FMO: %d\n",
+					p_264->fmo_slice_map_type);
+			p_264->fmo_slice_map_type = 0;
+			p_264->fmo_slice_num_grp = 1;
+			break;
+		}
+		WRITEL(p_264->fmo_slice_map_type, S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE);
+		WRITEL(p_264->fmo_slice_num_grp - 1, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1);
+	} else {
+		WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1);
+	}
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
+	unsigned int reg = 0;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* pictype : number of B */
+	reg = READL(S5P_FIMV_E_GOP_CONFIG);
+	/** num_b_frame - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= (p->num_b_frame << 16);
+	WRITEL(reg, S5P_FIMV_E_GOP_CONFIG);
+
+	/* profile & level */
+	reg = 0;
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= (p_mpeg4->level << 8);
+	/** profile - 0 ~ 1 */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->profile;
+	WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE);
+
+	/* quarter_pixel */
+	/* WRITEL(p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); */
+
+	/* qp */
+	WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP);
+	if (!p->rc_frame && !p->rc_mb) {
+		reg = 0;
+		reg &= ~(0x3f << 16);
+		reg |= (p_mpeg4->rc_b_frame_qp << 16);
+		reg &= ~(0x3f << 8);
+		reg |= (p_mpeg4->rc_p_frame_qp << 8);
+		reg &= ~(0x3f);
+		reg |= p_mpeg4->rc_frame_qp;
+		WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP);
+	}
+
+	/* frame rate */
+	/* FIXME: it should be applied at NAL_start */
+	if (p->rc_frame) {
+		/* FIXME: user set 1000x scale value */
+		reg = 0;
+		reg &= ~(0xffff << 16);
+		reg |= (p_mpeg4->vop_time_res << 16);
+		reg &= ~(0xffff);
+		reg |= p_mpeg4->vop_frm_delta;
+		WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE);
+	}
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_E_RC_CONFIG);
+	/** macroblock level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= (p->rc_mb << 8);
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+
+	/* max & min value of QP */
+	reg = 0;
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_mpeg4->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND);
+
+	/* initialize for '0' only setting*/
+	WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS); /* SEQ_start only */
+	WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD); /* SEQ_start only */
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
+	unsigned int reg = 0;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* profile & level */
+	reg = 0;
+	/** profile */
+	reg |= (0x1 << 4);
+	WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE);
+
+	/* qp */
+	WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP);
+	if (!p->rc_frame && !p->rc_mb) {
+		reg = 0;
+		reg &= ~(0x3f << 8);
+		reg |= (p_mpeg4->rc_p_frame_qp << 8);
+		reg &= ~(0x3f);
+		reg |= p_mpeg4->rc_frame_qp;
+		WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP);
+	}
+
+	/* frame rate */
+	/* Fix value for H.264, H.263 in the driver */
+	/* FIXME: it should be applied at NAL_start */
+	p->rc_frame_delta = FRAME_DELTA_H264_H263;
+	if (p->rc_frame) {
+		/* FIXME: user set 1000x scale value */
+		reg = 0;
+		reg &= ~(0xffff << 16);
+		reg |= ((p_mpeg4->rc_framerate * p->rc_frame_delta) << 16);
+		reg &= ~(0xffff);
+		reg |= p->rc_frame_delta;
+		WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE);
+	}
+
+	/* rate control config. */
+	reg = READL(S5P_FIMV_E_RC_CONFIG);
+	/** macroblock level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= (p->rc_mb << 8);
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+	/** frame QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_frame_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_CONFIG);
+
+	/* max & min value of QP */
+	reg = 0;
+	/** max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_mpeg4->rc_max_qp << 8);
+	/** min QP */
+	reg &= ~(0x3F);
+	reg |= p_mpeg4->rc_min_qp;
+	WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND);
+
+	mfc_debug_leave();
+
+	return 0;
+}
+
+/* Initialize decoding */
+int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+	unsigned int reg = 0;
+	int fmo_aso_ctrl = 0;
+
+	mfc_debug_enter();
+
+	mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, S5P_FIMV_CH_SEQ_HEADER);
+	mfc_debug(2, "BUFs: %08x %08x %08x\n",
+		  READL(S5P_FIMV_D_CPB_BUFFER_ADDR),
+		  READL(S5P_FIMV_D_CPB_BUFFER_ADDR),
+		  READL(S5P_FIMV_D_CPB_BUFFER_ADDR));
+
+	/* FIXME: Change fmo_aso_ctrl to be able to select */
+	/* FMO_ASO_CTRL - 0: Enable, 1: Disable */
+	reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK);
+
+	/* When user sets desplay_delay to 0,
+	 * It works as "display_delay enable" and delay set to 0.
+	 * If user wants display_delay disable, It should be
+	 * set to negative value. */
+	if (dec->display_delay >= 0) {
+		reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT);
+		WRITEL(dec->display_delay, S5P_FIMV_D_DISPLAY_DELAY);
+	}
+	/* Setup loop filter, for decoding this is only valid for MPEG4 */
+	if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_DEC) {
+		mfc_debug(2, "Set loop filter to: %d\n", dec->loop_filter_mpeg4);
+		reg |= (dec->loop_filter_mpeg4 << S5P_FIMV_D_OPT_LF_CTRL_SHIFT);
+	}
+	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
+		reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT);
+
+	WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS);
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_FIMV1_DEC) {
+		mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n",
+					ctx->img_width, ctx->img_height);
+		WRITEL(ctx->img_width, S5P_FIMV_D_SET_FRAME_WIDTH);
+		WRITEL(ctx->img_height, S5P_FIMV_D_SET_FRAME_HEIGHT);
+	}
+
+	/* 0: NV12(CbCr), 1: NV21(CrCb) */
+	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
+		WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT);
+	else
+		WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT);
+
+	/* sei parse */
+	WRITEL(dec->sei_parse, S5P_FIMV_D_SEI_ENABLE);
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	s5p_mfc_cmd_host2risc(S5P_FIMV_CH_SEQ_HEADER, NULL);
+
+	mfc_debug_leave();
+	return 0;
+}
+
+static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned int dpb;
+	if (flush)
+		dpb = READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | (1 << 14);
+	else
+		dpb = READL(S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & ~(1 << 14);
+	WRITEL(dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
+}
+
+/* Decode a single frame */
+int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_dec *dec = ctx->dec_priv;
+
+	mfc_debug(2, "Setting flags to %08lx (free:%d WTF:%d)\n",
+				dec->dpb_status, ctx->dst_queue_cnt,
+						dec->dpb_queue_cnt);
+	WRITEL(dec->dpb_status, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER);
+	WRITEL(0x0, S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER);
+	WRITEL(dec->slice_enable, S5P_FIMV_D_SLICE_IF_ENABLE);
+
+	/* FIXME: Is it needed for 6.x? */
+#if 0
+	s5p_mfc_set_flush(ctx, ctx->dpb_flush);
+#endif
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	/* Issue different commands to instance basing on whether it
+	 * is the last frame or not. */
+	switch(last_frame) {
+	case 0:
+		s5p_mfc_cmd_host2risc(S5P_FIMV_CH_FRAME_START, NULL);
+		break;
+	case 1:
+		s5p_mfc_cmd_host2risc(S5P_FIMV_CH_LAST_FRAME, NULL);
+		break;
+	}
+
+	mfc_debug(2, "Decoding a usual frame.\n");
+	return 0;
+}
+
+int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug(2, "++\n");
+
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC)
+		s5p_mfc_set_enc_params_h264(ctx);
+	else if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_ENC)
+		s5p_mfc_set_enc_params_mpeg4(ctx);
+	else if (ctx->codec_mode == S5P_FIMV_CODEC_H263_ENC)
+		s5p_mfc_set_enc_params_h263(ctx);
+	else {
+		mfc_err("Unknown codec for encoding (%x).\n",
+			ctx->codec_mode);
+		return -EINVAL;
+	}
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	s5p_mfc_cmd_host2risc(S5P_FIMV_CH_SEQ_HEADER, NULL);
+
+	mfc_debug(2, "--\n");
+
+	return 0;
+}
+
+int s5p_mfc_h264_set_aso_slice_order(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_enc *enc = ctx->enc_priv;
+	struct s5p_mfc_enc_params *p = &enc->params;
+	struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264;
+	int i;
+
+	if (p_264->aso_enable) {
+		for (i = 0; i < 8; i++)
+			WRITEL(p_264->aso_slice_order[i],
+				S5P_FIMV_E_H264_ASO_SLICE_ORDER_0 + i * 4);
+	}
+
+	return 0;
+}
+
+/* Encode a single frame */
+int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	mfc_debug(2, "++\n");
+
+	/* memory structure cur. frame */
+	/*
+	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
+		WRITEL(0, S5P_FIMV_ENC_MAP_FOR_CUR);
+	else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
+		WRITEL(3, S5P_FIMV_ENC_MAP_FOR_CUR);
+	*/
+	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC)
+		s5p_mfc_h264_set_aso_slice_order(ctx);
+
+	s5p_mfc_set_slice_mode(ctx);
+
+	WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+	s5p_mfc_cmd_host2risc(S5P_FIMV_CH_FRAME_START, NULL);
+
+	mfc_debug(2, "--\n");
+
+	return 0;
+}
+
+static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
+{
+	unsigned long flags;
+	int new_ctx;
+	int cnt;
+
+	spin_lock_irqsave(&dev->condlock, flags);
+	mfc_debug(2, "Previos context: %d (bits %08lx)\n", dev->curr_ctx,
+							dev->ctx_work_bits);
+	new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
+	cnt = 0;
+	while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
+		new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
+		cnt++;
+		if (cnt > MFC_NUM_CONTEXTS) {
+			/* No contexts to run */
+			spin_unlock_irqrestore(&dev->condlock, flags);
+			return -EAGAIN;
+		}
+	}
+	spin_unlock_irqrestore(&dev->condlock, flags);
+	return new_ctx;
+}
+
+static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *temp_vb;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	/* Frames are being decoded */
+	if (list_empty(&ctx->src_queue)) {
+		mfc_debug(2, "No src buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return;
+	}
+	/* Get the next source buffer */
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	temp_vb->used = 1;
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0), 0, 0);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_decode_one_frame(ctx, 1);
+}
+
+static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf *temp_vb;
+	unsigned long flags;
+	int last_frame = 0;
+	unsigned int index;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	/* Frames are being decoded */
+	if (list_empty(&ctx->src_queue)) {
+		mfc_debug(2, "No src buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+	if (ctx->dst_queue_cnt < ctx->dpb_count) {
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+	/* Get the next source buffer */
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	temp_vb->used = 1;
+	mfc_debug(2, "Temp vb: %p\n", temp_vb);
+	mfc_debug(2, "Src Addr: %08lx\n", mfc_plane_cookie(&temp_vb->vb, 0));
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	index = temp_vb->vb.v4l2_buf.index;
+	if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+		mfc_err("failed in set_buf_ctrls_val\n");
+
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	if (temp_vb->vb.v4l2_planes[0].bytesused == 0) {
+		last_frame = 1;
+		mfc_debug(2, "Setting ctx->state to FINISHING\n");
+		ctx->state = MFCINST_FINISHING;
+	}
+	s5p_mfc_decode_one_frame(ctx, last_frame);
+
+	return 0;
+}
+
+static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *dst_mb;
+	struct s5p_mfc_buf *src_mb;
+	unsigned long src_y_addr, src_c_addr, dst_addr;
+	/*
+	unsigned int src_y_size, src_c_size;
+	*/
+	unsigned int dst_size;
+	unsigned int index;
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (list_empty(&ctx->src_queue)) {
+		mfc_debug(2, "no src buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+
+	if (list_empty(&ctx->dst_queue)) {
+		mfc_debug(2, "no dst buffers.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EAGAIN;
+	}
+
+	src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	src_mb->used = 1;
+	src_y_addr = mfc_plane_cookie(&src_mb->vb, 0);
+	src_c_addr = mfc_plane_cookie(&src_mb->vb, 1);
+
+	mfc_debug(2, "enc src y addr: 0x%08lx", src_y_addr);
+	mfc_debug(2, "enc src c addr: 0x%08lx", src_c_addr);
+
+	s5p_mfc_set_enc_frame_buffer(ctx, src_y_addr, src_c_addr);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_mb->used = 1;
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	index = src_mb->vb.v4l2_buf.index;
+	if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0)
+		mfc_err("failed in set_buf_ctrls_val\n");
+
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_encode_one_frame(ctx);
+
+	return 0;
+}
+
+static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *temp_vb;
+
+	/* Initializing decoding - parsing header */
+	spin_lock_irqsave(&dev->irqlock, flags);
+	mfc_debug(2, "Preparing to init decoding.\n");
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	mfc_debug(2, "Header size: %d\n", temp_vb->vb.v4l2_planes[0].bytesused);
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+	dev->curr_ctx = ctx->num;
+	mfc_debug(2, "paddr: %08x\n",
+			(int)phys_to_virt(mfc_plane_cookie(&temp_vb->vb, 0)));
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_init_decode(ctx);
+}
+
+static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	unsigned long flags;
+	struct s5p_mfc_buf *dst_mb;
+	unsigned long dst_addr;
+	unsigned int dst_size;
+
+	//s5p_mfc_set_enc_ref_buffer(ctx);
+
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
+	dst_addr = mfc_plane_cookie(&dst_mb->vb, 0);
+	dst_size = vb2_plane_size(&dst_mb->vb, 0);
+	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
+
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+
+	dev->curr_ctx = ctx->num;
+	mfc_debug(2, "paddr: %08x\n",
+			(int)phys_to_virt(mfc_plane_cookie(&dst_mb->vb, 0)));
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	s5p_mfc_init_encode(ctx);
+}
+
+static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int ret;
+	/* FIXME: Is it needed? */
+#if 0
+	unsigned long flags;
+	struct s5p_mfc_buf *temp_vb;
+#endif
+	/* Header was parsed now starting processing
+	 * First set the output frame buffers
+	 * s5p_mfc_alloc_dec_buffers(ctx); */
+
+	if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
+		mfc_err("It seems that not all destionation buffers were "
+			"mmaped.\nMFC requires that all destination are mmaped "
+			"before starting processing.\n");
+		return -EAGAIN;
+	}
+
+	/* FIXME: Is it needed? */
+#if 0
+	spin_lock_irqsave(&dev->irqlock, flags);
+
+	if (list_empty(&ctx->src_queue)) {
+		mfc_err("Header has been deallocated in the middle of "
+							"initialization.\n");
+		spin_unlock_irqrestore(&dev->irqlock, flags);
+		return -EIO;
+	}
+
+	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
+	mfc_debug(2, "Header size: %d\n", temp_vb->vb.v4l2_planes[0].bytesused);
+	s5p_mfc_set_dec_stream_buffer(ctx, mfc_plane_cookie(&temp_vb->vb, 0),
+				0, temp_vb->vb.v4l2_planes[0].bytesused);
+	spin_unlock_irqrestore(&dev->irqlock, flags);
+#endif
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	ret = s5p_mfc_set_dec_frame_buffer(ctx);
+	if (ret) {
+		mfc_err("Failed to alloc frame mem.\n");
+		ctx->state = MFCINST_ERROR;
+	}
+	return ret;
+}
+
+static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int ret;
+
+	ret = s5p_mfc_alloc_codec_buffers(ctx);
+	if (ret) {
+		mfc_err("Failed to allocate encoding buffers.\n");
+		return -ENOMEM;
+	}
+
+	/* Header was generated now starting processing
+	 * First set the reference frame buffers
+	 */
+	if (ctx->capture_state != QUEUE_BUFS_REQUESTED) {
+		mfc_err("It seems that destionation buffers were not "
+			"requested.\nMFC requires that header should be generated "
+			"before allocating codec buffer.\n");
+		return -EAGAIN;
+	}
+
+	/* FIXME: Is it needed? */
+	dev->curr_ctx = ctx->num;
+	s5p_mfc_clean_ctx_int_flags(ctx);
+	ret = s5p_mfc_set_enc_ref_buffer(ctx);
+	if (ret) {
+		mfc_err("Failed to alloc frame mem.\n");
+		ctx->state = MFCINST_ERROR;
+	}
+	return ret;
+}
+
+/* Try running an operation on hardware */
+void s5p_mfc_try_run(struct s5p_mfc_dev *dev)
+{
+	struct s5p_mfc_ctx *ctx;
+	int new_ctx;
+	unsigned int ret = 0;
+
+	mfc_debug(1, "Try run dev: %p\n", dev);
+
+	/* Check whether hardware is not running */
+	if (test_and_set_bit(0, &dev->hw_lock) != 0) {
+		/* This is perfectly ok, the scheduled ctx should wait */
+		mfc_debug(1, "Couldn't lock HW.\n");
+		return;
+	}
+
+	/* Choose the context to run */
+	new_ctx = s5p_mfc_get_new_ctx(dev);
+	if (new_ctx < 0) {
+		/* No contexts to run */
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
+			mfc_err("Failed to unlock hardware.\n");
+			return;
+		}
+
+		mfc_debug(1, "No ctx is scheduled to be run.\n");
+		return;
+	}
+
+	mfc_debug(1, "New context: %d\n", new_ctx);
+	ctx = dev->ctx[new_ctx];
+	mfc_debug(1, "Seting new context to %p\n", ctx);
+	/* Got context to run in ctx */
+	mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
+		ctx->dst_queue_cnt, ctx->dpb_count, ctx->src_queue_cnt);
+	mfc_debug(1, "ctx->state=%d\n", ctx->state);
+	/* Last frame has already been sent to MFC
+	 * Now obtaining frames from MFC buffer */
+
+	s5p_mfc_clock_on();
+	if (ctx->type == MFCINST_DECODER) {
+		switch (ctx->state) {
+		case MFCINST_FINISHING:
+			s5p_mfc_run_dec_last_frames(ctx);
+			break;
+		case MFCINST_RUNNING:
+			ret = s5p_mfc_run_dec_frame(ctx);
+			break;
+		case MFCINST_INIT:
+			ret = s5p_mfc_open_inst(ctx);
+			break;
+		case MFCINST_RETURN_INST:
+			ret = s5p_mfc_close_inst(ctx);
+			break;
+		case MFCINST_GOT_INST:
+			s5p_mfc_run_init_dec(ctx);
+			break;
+		case MFCINST_HEAD_PARSED:
+			ret = s5p_mfc_run_init_dec_buffers(ctx);
+			break;
+		case MFCINST_RES_CHANGE_INIT:
+			s5p_mfc_run_dec_last_frames(ctx);
+			break;
+		case MFCINST_RES_CHANGE_FLUSH:
+			s5p_mfc_run_dec_last_frames(ctx);
+			break;
+		case MFCINST_RES_CHANGE_END:
+			mfc_debug(2, "Finished remaining frames after resolution change.\n");
+			ctx->capture_state = QUEUE_FREE;
+			mfc_debug(2, "Will re-init the codec`.\n");
+			s5p_mfc_run_init_dec(ctx);
+			break;
+		default:
+			ret = -EAGAIN;
+		}
+	} else if (ctx->type == MFCINST_ENCODER) {
+		switch (ctx->state) {
+		case MFCINST_FINISHING:
+		case MFCINST_RUNNING:
+		case MFCINST_RUNNING_NO_OUTPUT:
+			ret = s5p_mfc_run_enc_frame(ctx);
+			break;
+		case MFCINST_INIT:
+			ret = s5p_mfc_open_inst(ctx);
+			break;
+		case MFCINST_RETURN_INST:
+			ret = s5p_mfc_close_inst(ctx);
+			break;
+		case MFCINST_GOT_INST:
+			s5p_mfc_run_init_enc(ctx);
+			break;
+		case MFCINST_HEAD_PARSED: /* Only for MFC6.x */
+			ret = s5p_mfc_run_init_enc_buffers(ctx);
+			break;
+		default:
+			ret = -EAGAIN;
+		}
+	} else {
+		mfc_err("invalid context type: %d\n", ctx->type);
+		ret = -EAGAIN;
+	}
+
+	if (ret) {
+		/* Free hardware lock */
+		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
+			mfc_err("Failed to unlock hardware.\n");
+		}
+		s5p_mfc_clock_off();
+	}
+}
+
+
+/* FIXME: where is my spot? */
+void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
+{
+	struct s5p_mfc_buf *b;
+	int i;
+
+	while (!list_empty(lh)) {
+		b = list_entry(lh->next, struct s5p_mfc_buf, list);
+		for (i = 0; i < b->vb.num_planes; i++)
+			vb2_set_plane_payload(&b->vb, i, 0);
+		vb2_buffer_done(&b->vb, VB2_BUF_STATE_ERROR);
+		list_del(&b->list);
+	}
+}
+
+/*
+ * Clock on/off is not called if dev->hw_lock is not 0.
+ * dev->hw_lock is used as flag in read/write_info.
+ * [0] : 1 means it is in h/w processing.
+ * [1] : 1 means it is in spin_lock_irqsave.
+ */
+void s5p_mfc_write_info(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+
+	/* MFC 6.x uses SFR for information */
+	if (dev->hw_lock) {
+		WRITEL(data, ofs);
+	} else {
+		s5p_mfc_clock_on();
+		WRITEL(data, ofs);
+		s5p_mfc_clock_off();
+	}
+}
+
+unsigned int s5p_mfc_read_info(struct s5p_mfc_ctx *ctx, unsigned int ofs)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	int ret;
+
+	/* MFC 6.x uses SFR for information */
+	if (dev->hw_lock) {
+		ret = READL(ofs);
+	} else {
+		s5p_mfc_clock_on();
+		ret = READL(ofs);
+		s5p_mfc_clock_off();
+	}
+
+	return ret;
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.h
new file mode 100644
index 0000000..02a1b42
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_opr_v6.h
@@ -0,0 +1,210 @@
+/*
+ * drivers/media/video/samsung/mfc5/s5p_mfc_opr.h
+ *
+ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver
+ * Contains declarations of hw related functions.
+ *
+ * Kamil Debski, Copyright (c) 2010 Samsung Electronics
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef S5P_MFC_OPR_V6_H_
+#define S5P_MFC_OPR_V6_H_
+
+#include "s5p_mfc_common.h"
+#include "s5p_mfc_mem.h"
+
+#define MFC_CTRL_MODE_CUSTOM	MFC_CTRL_MODE_SFR
+
+int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx);
+
+int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
+						  unsigned int start_num_byte,
+						  unsigned int buf_size);
+
+void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long y_addr, unsigned long c_addr);
+int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long addr, unsigned int size);
+void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
+		unsigned long *y_addr, unsigned long *c_addr);
+int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *mfc_ctx);
+
+int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame);
+int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *mfc_ctx);
+
+/* Memory allocation */
+int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
+
+int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx);
+
+int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx);
+int s5p_mfc_alloc_dev_context_buffer(struct s5p_mfc_dev *dev);
+void s5p_mfc_release_dev_context_buffer(struct s5p_mfc_dev *dev);
+
+void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx);
+void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx);
+
+#define s5p_mfc_get_dspl_y_adr()	(readl(dev->regs_base + \
+					S5P_FIMV_SI_DISPLAY_Y_ADR) << 11)
+#define s5p_mfc_get_dspl_status()	readl(dev->regs_base + \
+						S5P_FIMV_D_DISPLAY_STATUS)
+#define s5p_mfc_get_decoded_status()	readl(dev->regs_base + \
+						S5P_FIMV_D_DECODED_STATUS)
+#define s5p_mfc_get_dec_frame_type()	(readl(dev->regs_base + \
+						S5P_FIMV_D_DECODED_FRAME_TYPE) \
+						& S5P_FIMV_DECODE_FRAME_MASK)
+#define s5p_mfc_get_disp_frame_type()	(readl(ctx->dev->regs_base + \
+						S5P_FIMV_D_DISPLAY_FRAME_TYPE) \
+						& S5P_FIMV_DECODE_FRAME_MASK)
+#define s5p_mfc_get_consumed_stream()	readl(dev->regs_base + \
+						S5P_FIMV_D_DECODED_NAL_SIZE)
+#define s5p_mfc_get_int_reason()	(readl(dev->regs_base + \
+					S5P_FIMV_RISC2HOST_CMD) & \
+					S5P_FIMV_RISC2HOST_CMD_MASK)
+#define s5p_mfc_get_int_err()		readl(dev->regs_base + \
+						S5P_FIMV_ERROR_CODE)
+#define s5p_mfc_err_dec(x)		(((x) & S5P_FIMV_ERR_DEC_MASK) >> \
+						S5P_FIMV_ERR_DEC_SHIFT)
+#define s5p_mfc_err_dspl(x)		(((x) & S5P_FIMV_ERR_DSPL_MASK) >> \
+						S5P_FIMV_ERR_DSPL_SHIFT)
+#define s5p_mfc_get_img_width()		readl(dev->regs_base + \
+						S5P_FIMV_D_DISPLAY_FRAME_WIDTH)
+#define s5p_mfc_get_img_height()	readl(dev->regs_base + \
+						S5P_FIMV_D_DISPLAY_FRAME_HEIGHT)
+#define s5p_mfc_get_dpb_count()		readl(dev->regs_base + \
+						S5P_FIMV_D_MIN_NUM_DPB)
+#define s5p_mfc_get_mv_count()		readl(dev->regs_base + \
+						S5P_FIMV_D_MIN_NUM_MV)
+#define s5p_mfc_get_inst_no()		readl(dev->regs_base + \
+						S5P_FIMV_RET_INSTANCE_ID)
+#define s5p_mfc_get_enc_dpb_count()	readl(dev->regs_base + \
+						S5P_FIMV_E_NUM_DPB)
+#define s5p_mfc_get_enc_strm_size()	readl(dev->regs_base + \
+						S5P_FIMV_E_STREAM_SIZE)
+#define s5p_mfc_get_enc_slice_type()	readl(dev->regs_base + \
+						S5P_FIMV_E_SLICE_TYPE)
+#define s5p_mfc_get_enc_pic_count()	readl(dev->regs_base + \
+						S5P_FIMV_E_PICTURE_COUNT)
+#define s5p_mfc_get_sei_avail_status()	readl(dev->regs_base + \
+						S5P_FIMV_D_FRAME_PACK_SEI_AVAIL)
+#define s5p_mfc_get_mvc_num_views()	readl(dev->regs_base + \
+						S5P_FIMV_D_MVC_NUM_VIEWS)
+#define s5p_mfc_get_mvc_disp_view_id()	(readl(dev->regs_base + \
+						S5P_FIMV_D_MVC_VIEW_ID) \
+						& S5P_FIMV_D_MVC_VIEW_ID_DISP_MASK)
+
+#define mb_width(x_size)		((x_size + 15) / 16)
+#define mb_height(y_size)		((y_size + 15) / 16)
+#define s5p_mfc_dec_mv_size(x, y)	(mb_width(x) * (((mb_height(y)+1)/2)*2) * 64 + 128)
+
+#define s5p_mfc_clear_int_flags()				\
+	do {							\
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC2HOST_CMD);	\
+		s5p_mfc_write_reg(0, S5P_FIMV_RISC2HOST_INT);	\
+	} while (0)
+
+/* Definition */
+#define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
+#define ENC_MULTI_SLICE_BIT_MIN		2800
+#define ENC_MULTI_SLICE_BYTE_MIN	350
+#define ENC_INTRA_REFRESH_MB_MAX	((1 << 18) - 1)
+#define ENC_VBV_BUF_SIZE_MAX		((1 << 30) - 1)
+#define ENC_H264_LOOP_FILTER_AB_MIN	-12
+#define ENC_H264_LOOP_FILTER_AB_MAX	12
+#define ENC_H264_RC_FRAME_RATE_MAX	((1 << 16) - 1)
+#define ENC_H263_RC_FRAME_RATE_MAX	((1 << 16) - 1)
+#define ENC_H264_PROFILE_MAX		3
+#define ENC_H264_LEVEL_MAX		42
+#define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
+#define FRAME_DELTA_H264_H263		1
+#define TIGHT_CBR_MAX			10
+
+/* Definitions for shared memory compatibility */
+#define PIC_TIME_TOP		S5P_FIMV_D_RET_PICTURE_TAG_TOP
+#define PIC_TIME_BOT		S5P_FIMV_D_RET_PICTURE_TAG_BOT
+#define CROP_INFO_H		S5P_FIMV_D_DISPLAY_CROP_INFO1
+#define CROP_INFO_V		S5P_FIMV_D_DISPLAY_CROP_INFO2
+
+/* Scratch buffer size for MFC v6.1 */
+#define DEC_V61_H264_SCRATCH_SIZE(x, y)				\
+		((x * 128) + 65536)
+#define DEC_V61_MPEG4_SCRATCH_SIZE(x, y)			\
+		((x) * ((y) * 64 + 144) +			\
+		 ((2048 + 15) / 16 * (y) * 64) +		\
+		 ((2048 + 15) / 16 * 256 + 8320))
+#define DEC_V61_VC1_SCRATCH_SIZE(x, y)				\
+		(2096 * ((x) + (y) + 1))
+#define DEC_V61_MPEG2_SCRATCH_SIZE(x, y)	0
+#define DEC_V61_H263_SCRATCH_SIZE(x, y)				\
+		((x) * 400)
+#define DEC_V61_VP8_SCRATCH_SIZE(x, y)				\
+		((x) * 32 + (y) * 128 + 34816)
+#define ENC_V61_H264_SCRATCH_SIZE(x, y)				\
+		(((x) * 64) + (((x) + 1) * 16) + (4096 * 16))
+#define ENC_V61_MPEG4_SCRATCH_SIZE(x, y)			\
+		(((x) * 16) + (((x) + 1) * 16))
+
+/* Scratch buffer size for MFC v6.5 */
+#define DEC_V65_H264_SCRATCH_SIZE(x, y)				\
+		((x * 192) + 64)
+#define DEC_V65_MPEG4_SCRATCH_SIZE(x, y)			\
+		((x) * ((y) * 64 + 144) + 			\
+		 ((2048 + 15) / 16 * (y) * 64) +		\
+		 ((2048 + 15) / 16 * 256 + 8320))
+#define DEC_V65_VC1_SCRATCH_SIZE(x, y)				\
+		(2096 * ((x) + (y) + 1))
+#define DEC_V65_MPEG2_SCRATCH_SIZE(x, y)	0
+#define DEC_V65_H263_SCRATCH_SIZE(x, y)				\
+		((x) * 400)
+#define DEC_V65_VP8_SCRATCH_SIZE(x, y)				\
+		((x) * 32 + (y) * 128 +				\
+		 (((x) + 1) / 2) * 64 + 2112)
+#define ENC_V65_H264_SCRATCH_SIZE(x, y)				\
+		(((x) * 48) + (((x) + 1) / 2 * 128) + 144)
+#define ENC_V65_MPEG4_SCRATCH_SIZE(x, y)			\
+		(((x) * 32) + 16)
+
+/* Encoder buffer size for common */
+#define ENC_TMV_SIZE(x,y)					\
+		(((x) + 1) * ((y) + 3) * 8)
+#define ENC_ME_SIZE(f_x,f_y,mb_x,mb_y)				\
+		((((((f_x) + 63) / 64) * 16) *			\
+		((((f_y) + 63) / 64) * 16)) +			\
+		((((mb_x) * (mb_y) + 31) / 32) * 16))
+
+/* MV range is [16,256] for v6.1, [16,128] for v6.5 */
+#define ENC_V61_MV_RANGE		256
+#define ENC_V65_MV_RANGE		128
+/* FIXME: temporal definition to avoid compile error */
+enum MFC_SHM_OFS
+{
+	EXT_ENC_CONTROL		= 0x28,	/* E */
+	RC_VOP_TIMING		= 0x30,	/* E, MPEG4 */
+
+	P_B_FRAME_QP		= 0x70,	/* E */
+	ASPECT_RATIO_IDC	= 0x74, /* E, H.264, depend on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+	EXTENDED_SAR		= 0x78, /* E, H.264, depned on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+
+	H264_I_PERIOD		= 0x9C, /* E, H.264, open GOP */
+	RC_CONTROL_CONFIG	= 0xA0, /* E */
+};
+
+void s5p_mfc_try_run(struct s5p_mfc_dev *dev);
+
+void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
+
+void s5p_mfc_write_info(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs);
+unsigned int s5p_mfc_read_info(struct s5p_mfc_ctx *ctx, unsigned int ofs);
+
+#endif /* S5P_MFC_OPR_V6_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_pm.c b/drivers/media/video/s5p-mfc/s5p_mfc_pm.c
new file mode 100644
index 0000000..ab6fb4b
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_pm.c
@@ -0,0 +1,325 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/jiffies.h>
+#include <plat/s5p-mfc.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_debug.h"
+#include "s5p_mfc_pm.h"
+#include "s5p_mfc_reg.h"
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#include <linux/platform_device.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+
+#define MFC_PARENT_CLK_NAME	"mout_mfc0"
+#define MFC_CLKNAME		"sclk_mfc"
+#define MFC_GATE_CLK_NAME	"mfc"
+
+#define CLK_DEBUG
+
+static struct s5p_mfc_pm *pm;
+
+atomic_t clk_ref;
+
+int s5p_mfc_init_pm(struct s5p_mfc_dev *dev)
+{
+	struct clk *parent, *sclk;
+	int ret = 0;
+
+	pm = &dev->pm;
+
+	/* FIXME : move to platform resource NAME */
+	parent = clk_get(&dev->plat_dev->dev, MFC_PARENT_CLK_NAME);
+	if (IS_ERR(parent)) {
+		printk(KERN_ERR "failed to get parent clock\n");
+		ret = -ENOENT;
+		goto err_p_clk;
+	}
+
+	/* FIXME : move to platform resource NAME */
+	sclk = clk_get(&dev->plat_dev->dev, MFC_CLKNAME);
+	if (IS_ERR(sclk)) {
+		printk(KERN_ERR "failed to get source clock\n");
+		ret = -ENOENT;
+		goto err_s_clk;
+	}
+
+	clk_set_parent(sclk, parent);
+	/* FIXME : move to platform resource RATE */
+	clk_set_rate(sclk, 200 * 1000000);
+
+	/* FIXME : move to platform resource NAME */
+	/* clock for gating */
+	pm->clock = clk_get(&dev->plat_dev->dev, MFC_GATE_CLK_NAME);
+	if (IS_ERR(pm->clock)) {
+		printk(KERN_ERR "failed to get clock-gating control\n");
+		ret = -ENOENT;
+		goto err_g_clk;
+	}
+
+	atomic_set(&pm->power, 0);
+	atomic_set(&clk_ref, 0);
+
+	pm->device = &dev->plat_dev->dev;
+
+	pm_runtime_enable(pm->device);
+
+	return 0;
+
+err_g_clk:
+	clk_put(sclk);
+err_s_clk:
+	clk_put(parent);
+err_p_clk:
+	return ret;
+}
+
+void s5p_mfc_final_pm(struct s5p_mfc_dev *dev)
+{
+	clk_put(pm->clock);
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(pm->device);
+#endif
+}
+
+int s5p_mfc_clock_on(void)
+{
+	int ret;
+	struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
+
+	atomic_inc(&clk_ref);
+
+#ifdef CLK_DEBUG
+	mfc_debug(3, "+ %d", atomic_read(&clk_ref));
+#endif
+
+	ret = clk_enable(pm->clock);
+	if (ret >= 0)
+		ret = s5p_mfc_mem_resume(dev->alloc_ctx[0]);
+
+	return ret;
+}
+
+void s5p_mfc_clock_off(void)
+{
+	struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
+
+	atomic_dec(&clk_ref);
+#ifdef CLK_DEBUG
+	mfc_debug(3, "- %d", atomic_read(&clk_ref));
+#endif
+
+	s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
+
+	clk_disable(pm->clock);
+}
+
+int s5p_mfc_power_on(void)
+{
+#ifdef CONFIG_PM_RUNTIME
+	return pm_runtime_get_sync(pm->device);
+#else
+	atomic_set(&pm->power, 1);
+
+	return 0;
+#endif
+}
+
+int s5p_mfc_power_off(void)
+{
+#ifdef CONFIG_PM_RUNTIME
+	return pm_runtime_put_sync(pm->device);
+#else
+	atomic_set(&pm->power, 0);
+
+	return 0;
+#endif
+}
+
+bool s5p_mfc_power_chk(void)
+{
+	mfc_debug(2, "%s", atomic_read(&pm->power) ? "on" : "off");
+
+	return atomic_read(&pm->power) ? true : false;
+}
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#define MFC_PARENT_CLK_NAME	"dout_aclk_333"
+#define MFC_CLKNAME		"sclk_mfc"
+#define MFC_GATE_CLK_NAME	"mfc"
+
+static struct s5p_mfc_pm *pm;
+
+atomic_t clk_ref;
+
+int s5p_mfc_init_pm(struct s5p_mfc_dev *dev)
+{
+	struct clk *parent_clk;
+	int ret = 0;
+	struct s5p_mfc_platdata *pdata;
+
+	pm = &dev->pm;
+
+	/* FIXME : move to platform resource NAME */
+	/* clock for gating */
+	pm->clock = clk_get(&dev->plat_dev->dev, MFC_GATE_CLK_NAME);
+	if (IS_ERR(pm->clock)) {
+		printk(KERN_ERR "failed to get clock-gating control\n");
+		ret = PTR_ERR(pm->clock);
+		goto err_g_clk;
+	}
+
+	parent_clk = clk_get(&dev->plat_dev->dev, MFC_PARENT_CLK_NAME);
+	if (IS_ERR(parent_clk)) {
+		printk(KERN_ERR "failed to get parent clock %s.\n", MFC_PARENT_CLK_NAME);
+		ret = PTR_ERR(parent_clk);
+		goto err_p_clk;
+	}
+
+	pdata = dev->platdata;
+	clk_set_rate(parent_clk, pdata->clock_rate);
+
+	atomic_set(&pm->power, 0);
+	atomic_set(&clk_ref, 0);
+
+	pm->device = &dev->plat_dev->dev;
+	pm_runtime_enable(pm->device);
+
+	clk_put(parent_clk);
+
+	return 0;
+
+err_p_clk:
+	clk_put(pm->clock);
+err_g_clk:
+	return ret;
+}
+
+void s5p_mfc_final_pm(struct s5p_mfc_dev *dev)
+{
+	clk_put(pm->clock);
+
+	pm_runtime_disable(pm->device);
+}
+
+int s5p_mfc_clock_on(void)
+{
+	int ret = 0;
+	int state, val;
+	struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
+
+	state = atomic_inc_return(&clk_ref);
+
+	mfc_debug(3, "+ %d", state);
+
+	ret = clk_enable(pm->clock);
+	if (ret < 0)
+		return ret;
+
+	ret = s5p_mfc_mem_resume(dev->alloc_ctx[0]);
+	if (ret < 0) {
+		clk_disable(pm->clock);
+		return ret;
+	}
+
+	if (dev->fw.date >= 0x120206) {
+		val = s5p_mfc_read_reg(S5P_FIMV_MFC_BUS_RESET_CTRL);
+		val &= ~(0x1);
+		s5p_mfc_write_reg(val, S5P_FIMV_MFC_BUS_RESET_CTRL);
+	}
+
+	return 0;
+}
+
+void s5p_mfc_clock_off(void)
+{
+	int state, val;
+	unsigned long timeout;
+	struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
+
+	state = atomic_dec_return(&clk_ref);
+
+	mfc_debug(3, "- %d", state);
+
+	if (dev->fw.date >= 0x120206) {
+		s5p_mfc_write_reg(0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
+
+		timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
+		/* Check bus status */
+		do {
+			if (time_after(jiffies, timeout)) {
+				mfc_err("Timeout while resetting MFC.\n");
+				break;
+			}
+			val = s5p_mfc_read_reg(S5P_FIMV_MFC_BUS_RESET_CTRL);
+		} while ((val & 0x2) == 0);
+	}
+
+	if (!dev->curr_ctx_drm)
+		s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
+	clk_disable(pm->clock);
+
+	if (state < 0) {
+		mfc_err("Clock state is wrong(%d)\n", state);
+	}
+}
+
+int s5p_mfc_power_on(void)
+{
+	return pm_runtime_get_sync(pm->device);
+}
+
+int s5p_mfc_power_off(void)
+{
+	return pm_runtime_put_sync(pm->device);
+}
+#else /* CONFIG_ARCH_NOT_SUPPORT */
+int s5p_mfc_init_pm(struct s5p_mfc_dev *mfcdev)
+{
+	return -1;
+}
+
+void s5p_mfc_final_pm(struct s5p_mfc_dev *mfcdev)
+{
+	/* NOP */
+}
+
+int s5p_mfc_clock_on(void)
+{
+	return -1;
+}
+
+void s5p_mfc_clock_off(void)
+{
+	/* NOP */
+}
+
+int s5p_mfc_power_on(void)
+{
+	return -1;
+}
+
+int s5p_mfc_power_off(void)
+{
+	return -1;
+}
+#endif
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_pm.h b/drivers/media/video/s5p-mfc/s5p_mfc_pm.h
new file mode 100644
index 0000000..81a2d93
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_pm.h
@@ -0,0 +1,27 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_pm.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_PM_H
+#define __S5P_MFC_PM_H __FILE__
+
+int s5p_mfc_init_pm(struct s5p_mfc_dev *dev);
+void s5p_mfc_final_pm(struct s5p_mfc_dev *dev);
+
+int s5p_mfc_clock_on(void);
+void s5p_mfc_clock_off(void);
+int s5p_mfc_power_on(void);
+int s5p_mfc_power_off(void);
+#ifdef CONFIG_ARCH_EXYNOS4
+bool s5p_mfc_power_chk(void);
+#endif
+
+#endif /* __S5P_MFC_PM_H */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_reg.c b/drivers/media/video/s5p-mfc/s5p_mfc_reg.c
new file mode 100644
index 0000000..31eca36
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_reg.c
@@ -0,0 +1,34 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_reg.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+ #include <linux/io.h>
+
+static void __iomem *regs;
+
+void s5p_mfc_init_reg(void __iomem *base)
+{
+	regs = base;
+}
+
+void s5p_mfc_write_reg(unsigned int data, unsigned int offset)
+{
+	writel(data, regs + offset);
+	/* FIXME: */
+	/* __raw_write() */
+}
+
+unsigned int s5p_mfc_read_reg(unsigned int offset)
+{
+	return readl(regs + offset);
+	/* FIXME: */
+	/* __raw_read() */
+}
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_reg.h b/drivers/media/video/s5p-mfc/s5p_mfc_reg.h
new file mode 100644
index 0000000..f61a7c4
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_reg.h
@@ -0,0 +1,122 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_reg.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_REG_H_
+#define __S5P_MFC_REG_H_ __FILE__
+
+#define MFC_SYS_SW_RESET_ADDR		S5P_FIMV_SW_RESET
+#define MFC_SYS_SW_RESET_MASK		0x3FF
+#define MFC_SYS_SW_RESET_SHFT		0x0
+#define MFC_SYS_R2H_INT_ADDR		S5P_FIMV_RISC_HOST_INT
+#define MFC_SYS_R2H_INT_MASK		0x1
+#define MFC_SYS_R2H_INT_SHFT		0x0
+#define MFC_SYS_H2R_CMD_ADDR		S5P_FIMV_HOST2RISC_CMD
+#define MFC_SYS_H2R_ARG1_ADDR		S5P_FIMV_HOST2RISC_ARG1
+#define MFC_SYS_CODEC_TYPE_ADDR		S5P_FIMV_HOST2RISC_ARG1
+#define MFC_SYS_INST_ID_ADDR		S5P_FIMV_HOST2RISC_ARG1
+#define MFC_SYS_FW_MEM_SIZE_ADDR	S5P_FIMV_HOST2RISC_ARG1
+#define MFC_SYS_H2R_ARG2_ADDR		S5P_FIMV_HOST2RISC_ARG2
+#define MFC_SYS_CRC_GEN_EN_ADDR		S5P_FIMV_HOST2RISC_ARG2
+#define MFC_SYS_CRC_GEN_EN_MASK		0x1
+#define MFC_SYS_CRC_GEN_EN_SHFT		0x1F
+#define MFC_SYS_ENC_PIXEL_CACHE_ADDR	S5P_FIMV_HOST2RISC_ARG2
+#define MFC_SYS_ENC_PIXEL_CACHE_MASK	0x2
+#define MFC_SYS_ENC_PIXEL_CACHE_SHFT	0x0
+#define MFC_SYS_DEC_PIXEL_CACHE_ADDR	S5P_FIMV_HOST2RISC_ARG2
+#define MFC_SYS_DEC_PIXEL_CACHE_MASK	0x2
+#define MFC_SYS_DEC_PIXEL_CACHE_SHFT	0x0
+#define MFC_SYS_H2R_ARG3_ADDR		S5P_FIMV_HOST2RISC_ARG3
+
+#define MFC_SYS_H2R_ARG4_ADDR		S5P_FIMV_HOST2RISC_ARG4
+
+#define MFC_SYS_FW_DVX_INFO_ADDR	S5P_FIMV_FW_VERSION
+#define MFC_SYS_FW_DVX_INFO_MASK	0xFF
+#define MFC_SYS_FW_DVX_INFO_SHFT	24
+#define MFC_SYS_FW_VER_YEAR_ADDR	S5P_FIMV_FW_VERSION
+#define MFC_SYS_FW_VER_YEAR_MASK	0xFF
+#define MFC_SYS_FW_VER_YEAR_SHFT	16
+#define MFC_SYS_FW_VER_MONTH_ADDR	S5P_FIMV_FW_VERSION
+#define MFC_SYS_FW_VER_MONTH_MASK	0xFF
+#define MFC_SYS_FW_VER_MONTH_SHFT	8
+#define MFC_SYS_FW_VER_DATE_ADDR	S5P_FIMV_FW_VERSION
+#define MFC_SYS_FW_VER_DATE_MASK	0xFF
+#define MFC_SYS_FW_VER_DATE_SHFT	0
+#define MFC_SYS_FW_VER_ALL_ADDR		S5P_FIMV_FW_VERSION
+#define MFC_SYS_FW_VER_ALL_MASK		0xFFFFFF
+#define MFC_SYS_FW_VER_ALL_SHFT	0
+
+#define MFC_DEC_DISPLAY_Y_ADR_ADDR	S5P_FIMV_SI_DISPLAY_Y_ADR
+#define MFC_DEC_DISPLAY_Y_ADR_MASK	0xFFFFFFFF
+#define MFC_DEC_DISPLAY_Y_ADR_SHFT	S5P_FIMV_MEM_OFFSET
+#define MFC_DEC_DISPLAY_C_ADR_ADDR	S5P_FIMV_SI_DISPLAY_C_ADR
+#define MFC_DEC_DISPLAY_C_ADR_MASK	0xFFFFFFFF
+#define MFC_DEC_DISPLAY_C_ADR_SHFT	S5P_FIMV_MEM_OFFSET
+
+#define MFC_DEC_DISPLAY_STATUS_ADDR	MFC_SI_DISPLAY_STATUS
+#define MFC_DEC_DISPLAY_STATUS_MASK	0x7
+#define MFC_DEC_DISPLAY_STATUS_SHFT	0x0
+#define MFC_DEC_DISPLAY_INTERACE_ADDR	MFC_SI_DISPLAY_STATUS
+#define MFC_DEC_DISPLAY_INTERACE_MASK	0x1
+#define MFC_DEC_DISPLAY_INTERACE_SHFT	0x3
+#define MFC_DEC_DISPLAY_RES_CHG_ADDR	MFC_SI_DISPLAY_STATUS
+#define MFC_DEC_DISPLAY_RES_CHG_MASK	0x3
+#define MFC_DEC_DISPLAY_RES_CHG_SHFT	0x4
+
+#define MFC_DEC_DECODE_FRAME_TYPE_ADDR	S5P_FIMV_DECODE_FRAME_TYPE
+#define MFC_DEC_DECODE_FRAME_TYPE_MASK	0x7
+#define MFC_DEC_DECODE_FRAME_TYPE_SHFT	0
+
+#define MFC_DEC_DECODE_STATUS_ADDR	MFC_SI_DECODE_STATUS
+#define MFC_DEC_DECODE_STATUS_MASK	0x7
+#define MFC_DEC_DECODE_STATUS_SHFT	0x0
+#define MFC_DEC_DECODE_INTERACE_ADDR	MFC_SI_DECODE_STATUS
+#define MFC_DEC_DECODE_INTERACE_MASK	0x1
+#define MFC_DEC_DECODE_INTERACE_SHFT	0x3
+#define MFC_DEC_DECODE_NUM_CRC_ADDR	MFC_SI_DECODE_STATUS
+#define MFC_DEC_DECODE_NUM_CRC_MASK	0x1
+#define MFC_DEC_DECODE_NUM_CRC_SHFT	0x4
+#define MFC_DEC_DECODE_GEN_CRC_ADDR	MFC_SI_DECODE_STATUS
+#define MFC_DEC_DECODE_GEN_CRC_MASK	0x1
+#define MFC_DEC_DECODE_GEN_CRC_SHFT	0x5
+
+#define MFC_SYS_MFC_VER_ADDR		S5P_FIMV_MFC_VERSION
+#define MFC_SYS_MFC_VER_MASK		0xFFFFFFFF
+#define MFC_SYS_MFC_VER_SHFT		0x0
+
+#define MFC_ENC_LEVEL_ADDR	MFC_ENC_PROFILE
+#define MFC_ENC_LEVEL_MASK	0xFF
+#define MFC_ENC_LEVEL_SHFT	0x8
+#define MFC_ENC_PROFILE_ADDR	MFC_ENC_PROFILE
+#define MFC_ENC_PROFILE_MASK	0x3
+#define MFC_ENC_PROFILE_SHFT	0x0
+
+#define _MFC_SET_REG(target, val)	s5p_mfc_write_reg(val, MFC_##target##_ADDR)
+#define MFC_SET_REG(target, val, shadow)					\
+	do {									\
+		shadow = s5p_mfc_read_reg(MFC_##target##_ADDR);			\
+		shadow &= ~(MFC_##target##_MASK << MFC_##target##_SHFT);	\
+		shadow |= ((val & MFC_##target##_MASK) << MFC_##target##_SHFT);	\
+		s5p_mfc_write_reg(shadow, MFC_##target##_ADDR);			\
+	} while (0)
+
+#define _MFC_GET_REG(target)	s5p_mfc_read_reg(MFC_##target##_ADDR)
+#define MFC_GET_REG(target)						\
+	((s5p_mfc_read_reg(MFC_##target##_ADDR) >> MFC_##target##_SHFT)	\
+	& MFC_##target##_MASK)
+
+#define MFC_GET_ADR(target)						\
+	(s5p_mfc_read_reg(MFC_##target##_ADR_ADDR) << MFC_##target##_ADR_SHFT)
+
+void s5p_mfc_init_reg(void __iomem *base);
+void s5p_mfc_write_reg(unsigned int data, unsigned int offset);
+unsigned int s5p_mfc_read_reg(unsigned int offset);
+#endif /* __S5P_MFC_REG_H_ */
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_shm.c b/drivers/media/video/s5p-mfc/s5p_mfc_shm.c
new file mode 100644
index 0000000..eac52d7
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_shm.c
@@ -0,0 +1,52 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+
+#include "s5p_mfc_common.h"
+
+#include "s5p_mfc_mem.h"
+#include "s5p_mfc_debug.h"
+
+int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->buf;
+	void *shm_alloc_ctx = dev->alloc_ctx[MFC_CMA_BANK1_ALLOC_CTX];
+
+	ctx->shm.alloc = s5p_mfc_mem_alloc(shm_alloc_ctx, buf_size->shared_buf);
+	if (IS_ERR(ctx->shm.alloc)) {
+		mfc_err("failed to allocate shared memory\n");
+		return PTR_ERR(ctx->shm.alloc);
+	}
+
+	/* shm_ofs only keeps the offset from base (port a) */
+	ctx->shm.ofs = s5p_mfc_mem_cookie(shm_alloc_ctx, ctx->shm.alloc) - dev->port_a;
+	ctx->shm.virt = s5p_mfc_mem_vaddr(shm_alloc_ctx, ctx->shm.alloc);
+	if (!ctx->shm.virt) {
+		s5p_mfc_mem_put(shm_alloc_ctx, ctx->shm.alloc);
+		ctx->shm.ofs = 0;
+		ctx->shm.alloc = NULL;
+
+		mfc_err("failed to virt addr of shared memory\n");
+		return -ENOMEM;
+	}
+
+	memset((void *)ctx->shm.virt, 0, buf_size->shared_buf);
+	s5p_mfc_cache_clean(ctx->shm.alloc);
+
+	mfc_debug(2, "shm info addr: 0x%08x, phys: 0x%08lx\n",
+		 (unsigned int)ctx->shm.virt, ctx->shm.ofs);
+
+	return 0;
+}
+
diff --git a/drivers/media/video/s5p-mfc/s5p_mfc_shm.h b/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
new file mode 100644
index 0000000..f5cfd37
--- /dev/null
+++ b/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
@@ -0,0 +1,91 @@
+/*
+ * linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S5P_MFC_SHM_H_
+#define __S5P_MFC_SHM_H_ __FILE__
+
+#include <linux/io.h>
+
+enum MFC_SHM_OFS
+{
+	EXTENEDED_DECODE_STATUS	= 0x00,	/* D */
+	SET_FRAME_TAG		= 0x04, /* D */
+	GET_FRAME_TAG_TOP	= 0x08, /* D */
+	GET_FRAME_TAG_BOT	= 0x0C, /* D */
+	PIC_TIME_TOP		= 0x10, /* D */
+	PIC_TIME_BOT		= 0x14, /* D */
+	START_BYTE_NUM		= 0x18, /* D */
+
+	CROP_INFO_H		= 0x20, /* D */
+	CROP_INFO_V		= 0x24, /* D */
+	EXT_ENC_CONTROL		= 0x28,	/* E */
+	ENC_PARAM_CHANGE	= 0x2C,	/* E */
+	RC_VOP_TIMING		= 0x30,	/* E, MPEG4 */
+	HEC_PERIOD		= 0x34,	/* E, MPEG4 */
+	METADATA_ENABLE		= 0x38, /* C */
+	METADATA_STATUS		= 0x3C, /* C */
+	METADATA_DISPLAY_INDEX	= 0x40,	/* C */
+	EXT_METADATA_START_ADDR	= 0x44, /* C */
+	PUT_EXTRADATA		= 0x48, /* C */
+	EXTRADATA_ADDR		= 0x4C, /* C */
+
+	ALLOC_LUMA_DPB_SIZE	= 0x64,	/* D */
+	ALLOC_CHROMA_DPB_SIZE	= 0x68,	/* D */
+	ALLOC_MV_SIZE		= 0x6C,	/* D */
+	P_B_FRAME_QP		= 0x70,	/* E */
+	ASPECT_RATIO_IDC	= 0x74, /* E, H.264, depend on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+	EXTENDED_SAR		= 0x78, /* E, H.264, depned on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+	DISP_PIC_PROFILE	= 0x7C, /* D */
+	FLUSH_CMD_TYPE		= 0x80, /* C */
+	FLUSH_CMD_INBUF1	= 0x84, /* C */
+	FLUSH_CMD_INBUF2	= 0x88, /* C */
+	FLUSH_CMD_OUTBUF	= 0x8C, /* E */
+	NEW_RC_BIT_RATE		= 0x90, /* E, format as RC_BIT_RATE(0xC5A8) depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
+	NEW_RC_FRAME_RATE	= 0x94, /* E, format as RC_FRAME_RATE(0xD0D0) depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
+	NEW_I_PERIOD		= 0x98, /* E, format as I_FRM_CTRL(0xC504) depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
+	H264_I_PERIOD		= 0x9C, /* E, H.264, open GOP */
+	RC_CONTROL_CONFIG	= 0xA0, /* E */
+	BATCH_INPUT_ADDR	= 0xA4, /* E */
+	BATCH_OUTPUT_ADDR	= 0xA8, /* E */
+	BATCH_OUTPUT_SIZE	= 0xAC, /* E */
+	MIN_LUMA_DPB_SIZE	= 0xB0, /* D */
+	DEVICE_FORMAT_ID	= 0xB4, /* C */
+	H264_POC_TYPE		= 0xB8, /* D */
+	MIN_CHROMA_DPB_SIZE	= 0xBC, /* D */
+	DISP_PIC_FRAME_TYPE	= 0xC0, /* D */
+	FREE_LUMA_DPB		= 0xC4, /* D, VC1 MPEG4 */
+	ASPECT_RATIO_INFO	= 0xC8, /* D, MPEG4 */
+	EXTENDED_PAR		= 0xCC, /* D, MPEG4 */
+	DBG_HISTORY_INPUT0	= 0xD0, /* C */
+	DBG_HISTORY_INPUT1	= 0xD4,	/* C */
+	DBG_HISTORY_OUTPUT	= 0xD8,	/* C */
+	HIERARCHICAL_P_QP	= 0xE0, /* E, H.264 */
+	FRAME_PACK_SEI_ENABLE	= 0x168, /* C */
+	FRAME_PACK_SEI_AVAIL	= 0x16c, /* D */
+	FRAME_PACK_SEI_INFO	= 0x17c, /* E */
+};
+
+int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
+
+static inline void s5p_mfc_write_shm(struct s5p_mfc_ctx *ctx, unsigned int data, unsigned int ofs)
+{
+	writel(data, (ctx->shm.virt + ofs));
+	s5p_mfc_cache_clean(ctx->shm.alloc);
+}
+
+static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
+{
+	s5p_mfc_cache_inv(ctx->shm.alloc);
+	return readl(ctx->shm.virt + ofs);
+}
+
+#endif /* __S5P_MFC_SHM_H_ */
diff --git a/drivers/media/video/samsung/Kconfig b/drivers/media/video/samsung/Kconfig
new file mode 100644
index 0000000..8421224
--- /dev/null
+++ b/drivers/media/video/samsung/Kconfig
@@ -0,0 +1,121 @@
+config VIDEO_SAMSUNG
+	bool "Samsung Multimedia Devices"
+	depends on VIDEO_CAPTURE_DRIVERS && VIDEO_V4L2
+	select VIDEO_FIXED_MINOR_RANGES
+	default n
+	help
+	  This is a representative video4linux configuration for Samsung multimedia devices.
+
+config VIDEO_SAMSUNG_V4L2
+	bool "V4L2 API for digital camera to be contributed by samsung"
+	depends on VIDEO_DEV && VIDEO_SAMSUNG
+	default n
+	help
+	  This feature is for new V4L2 APIs all about digital camera
+
+if CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
+	source "drivers/media/video/samsung/fimc/Kconfig"
+	source "drivers/media/video/samsung/tvout/Kconfig"
+	source "drivers/media/video/samsung/mfc5x/Kconfig"
+	source "drivers/media/video/samsung/ump/Kconfig"
+	source "drivers/media/video/samsung/tsi/Kconfig"
+endif
+if (CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412) && !SLP
+	source "drivers/media/video/samsung/mali/Kconfig"
+endif
+
+config VIDEO_FIMG2D
+	bool
+	depends on VIDEO_SAMSUNG
+	default n
+
+config VIDEO_FIMG2D_DEBUG
+	bool
+	depends on VIDEO_FIMG2D
+	default n
+
+if ARCH_EXYNOS5
+source "drivers/media/video/samsung/fimg2d3x/Kconfig"
+source "drivers/media/video/samsung/fimg2d4x/Kconfig"
+endif
+
+if ARCH_EXYNOS4
+source "drivers/media/video/samsung/fimg2d3x-exynos4/Kconfig"
+source "drivers/media/video/samsung/fimg2d4x-exynos4/Kconfig"
+endif
+
+
+if CPU_EXYNOS4210
+	source "drivers/media/video/samsung/jpeg/Kconfig"
+endif
+
+if CPU_EXYNOS4212 || CPU_EXYNOS4412 || CPU_EXYNOS5250
+	source "drivers/media/video/samsung/jpeg_v2x/Kconfig"
+endif
+
+if VIDEO_SAMSUNG
+comment "Reserved memory configurations"
+config VIDEO_SAMSUNG_USE_DMA_MEM
+	bool "Use common contigouse dma memory for Multimedia devices"
+	depends on SLP
+
+config VIDEO_SAMSUNG_MEMSIZE_DMA
+	int "Memory size in kbytes for DMA"
+	depends on VIDEO_SAMSUNG_USE_DMA_MEM
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_FIMC0
+	int "Memory size in kbytes for FIMC0"
+	depends on VIDEO_FIMC || VIDEO_SAMSUNG_S5P_FIMC
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_FIMC1
+	int "Memory size in kbytes for FIMC1"
+	depends on VIDEO_FIMC || VIDEO_SAMSUNG_S5P_FIMC
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_FIMC2
+	int "Memory size in kbytes for FIMC2"
+	depends on VIDEO_FIMC || VIDEO_SAMSUNG_S5P_FIMC
+	default "5120"
+
+config VIDEO_SAMSUNG_MEMSIZE_FIMC3
+	int "Memory size in kbytes for FIMC3"
+	depends on VIDEO_FIMC || VIDEO_SAMSUNG_S5P_FIMC
+	default "0"
+
+config VIDEO_SAMSUNG_MEMSIZE_MFC
+	int "Memory size in kbytes for MFC"
+	depends on VIDEO_MFC5X && (VIDEO_MFC_MEM_PORT_COUNT = 1) && (!EXYNOS_CONTENT_PATH_PROTECTION)
+	default "65536"
+
+config VIDEO_SAMSUNG_MEMSIZE_MFC0
+	int "Memory size in kbytes for MFC port0"
+	depends on VIDEO_MFC5X && (VIDEO_MFC_MEM_PORT_COUNT = 2) && (!EXYNOS_CONTENT_PATH_PROTECTION)
+	default "41984"
+
+config VIDEO_SAMSUNG_MEMSIZE_MFC1
+	int "Memory size in kbytes for MFC port1"
+	depends on VIDEO_MFC5X && (VIDEO_MFC_MEM_PORT_COUNT = 2) && (!EXYNOS_CONTENT_PATH_PROTECTION)
+	default "41984"
+
+config VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE
+	int "Memory size in kbytes for MFC Secure"
+	depends on VIDEO_MFC5X && EXYNOS_CONTENT_PATH_PROTECTION
+	default "41984"
+
+config VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL
+	int "Memory size in kbytes for MFC Normal"
+	depends on VIDEO_MFC5X && EXYNOS_CONTENT_PATH_PROTECTION
+	default "41984"
+
+config VIDEO_SAMSUNG_MEMSIZE_JPEG
+	int "Memory size in kbytes for JPEG"
+	depends on VIDEO_JPEG || (VIDEO_JPEG_V2X && (CPU_EXYNOS4212 || CPU_EXYNOS4412))
+	default "40960"
+
+config VIDEO_SAMSUNG_MEMSIZE_TVOUT
+	int "Memory size in kbytes for TVOUT"
+	depends on VIDEO_TVOUT
+	default "16384"
+endif
diff --git a/drivers/media/video/samsung/Makefile b/drivers/media/video/samsung/Makefile
new file mode 100644
index 0000000..301cd9a
--- /dev/null
+++ b/drivers/media/video/samsung/Makefile
@@ -0,0 +1,18 @@
+obj-$(CONFIG_VIDEO_FIMC)	+= fimc/
+obj-$(CONFIG_VIDEO_JPEG)	+= jpeg/
+obj-$(CONFIG_VIDEO_JPEG_V2X)	+= jpeg_v2x/
+obj-$(CONFIG_VIDEO_TVOUT)	+= tvout/
+obj-$(CONFIG_VIDEO_MFC5X)	+= mfc5x/
+
+ifeq ($(CONFIG_ARCH_EXYNOS4), y)
+obj-$(CONFIG_VIDEO_FIMG2D3X)	+= fimg2d3x-exynos4/
+obj-$(CONFIG_VIDEO_FIMG2D4X)	+= fimg2d4x-exynos4/
+else
+obj-$(CONFIG_VIDEO_FIMG2D3X)	+= fimg2d3x/
+obj-$(CONFIG_VIDEO_FIMG2D4X)	+= fimg2d4x/
+endif
+obj-$(CONFIG_VIDEO_UMP)		+= ump/
+obj-$(CONFIG_VIDEO_TSI)		+= tsi/
+obj-$(CONFIG_VIDEO_MALI400MP)	+= mali/
+
+EXTRA_CFLAGS += -Idrivers/media/video
diff --git a/drivers/media/video/samsung/fimc/Kconfig b/drivers/media/video/samsung/fimc/Kconfig
new file mode 100644
index 0000000..68f0b14
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/Kconfig
@@ -0,0 +1,59 @@
+config VIDEO_FIMC
+	bool "Samsung Camera Interface (FIMC) driver"
+	depends on VIDEO_SAMSUNG && ARCH_EXYNOS4
+	select VIDEO_IPC if ARCH_S5PV210
+	default n
+	help
+	  This is a video4linux driver for Samsung FIMC device.
+
+choice
+depends on VIDEO_FIMC
+prompt "Select CSC Range config"
+default VIDEO_FIMC_RANGE_NARROW
+config VIDEO_FIMC_RANGE_NARROW
+	bool "Narrow"
+	depends on VIDEO_FIMC && (ARCH_S5PV210 || ARCH_EXYNOS4)
+	---help---
+	  RGB <-> YUV Color Conversion Narrow Range Equation
+
+config VIDEO_FIMC_RANGE_WIDE
+	bool "Wide"
+	depends on VIDEO_FIMC && (ARCH_S5PV210 || ARCH_EXYNOS4)
+	---help---
+	  RGB <-> YUV Color Conversion Wide Range Equation
+endchoice
+
+config VIDEO_IPC
+	bool
+
+config VIDEO_FIMC_DEBUG
+	bool "FIMC driver debug messages"
+	depends on VIDEO_FIMC
+
+config VIDEO_FIMC_MIPI
+	bool "MIPI-CSI2 Slave Interface support"
+	depends on VIDEO_FIMC && (ARCH_S5PV210 || ARCH_EXYNOS4)
+	default y
+
+config VIDEO_FIMC_MIPI_IRQ_DEBUG
+	bool "FIMC MIPI Error interrupt message"
+	depends on VIDEO_FIMC_MIPI
+	default n
+
+choice
+depends on VIDEO_FIMC
+prompt "Select Output Mode"
+default VIDEO_FIMC_DMA_AUTO
+config VIDEO_FIMC_DMA_AUTO
+        bool "DMA AUTO MODE"
+        depends on VIDEO_FIMC
+        help
+          This enables support for FIMC1 DMA AUTO mode
+
+config VIDEO_FIMC_FIFO
+        bool "FIFO MODE"
+        depends on VIDEO_FIMC
+        help
+          This enables support for FIMC1 FIFO mode
+
+endchoice
diff --git a/drivers/media/video/samsung/fimc/Makefile b/drivers/media/video/samsung/fimc/Makefile
new file mode 100644
index 0000000..75d8750
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/Makefile
@@ -0,0 +1,22 @@
+obj-$(CONFIG_VIDEO_FIMC)	+= fimc_v4l2.o fimc_output.o fimc_overlay.o fimc_regs.o
+
+obj-$(CONFIG_CPU_EXYNOS4412)	+= fimc_capture.o fimc_dev.o
+obj-$(CONFIG_CPU_EXYNOS4212)	+= fimc_capture.o fimc_dev.o
+
+obj-$(CONFIG_CPU_EXYNOS4210)	+= fimc_capture_u1.o fimc_dev_u1.o
+obj-$(CONFIG_VIDEO_FIMC_MIPI)	+= csis.o
+obj-$(CONFIG_CPU_S5PV210)	+= ipc.o
+
+ifeq ($(CONFIG_CPU_S5PV210),y)
+EXTRA_CFLAGS += -DCONFIG_MIPI_CSI_ADV_FEATURE
+endif
+
+ifeq ($(CONFIG_ARCH_EXYNOS4),y)
+EXTRA_CFLAGS += -DCONFIG_MIPI_CSI_ADV_FEATURE
+endif
+
+EXTRA_CFLAGS += -Idrivers/media/video
+
+ifeq ($(CONFIG_VIDEO_FIMC_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/media/video/samsung/fimc/csis.c b/drivers/media/video/samsung/fimc/csis.c
new file mode 100644
index 0000000..1e27503
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/csis.c
@@ -0,0 +1,468 @@
+/* linux/drivers/media/video/samsung/csis.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co,. Ltd.
+ *	http://www.samsung.com/
+ *
+ * MIPI-CSI2 Support file for FIMC driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/slab.h>
+#include <plat/clock.h>
+#include <plat/regs-csis.h>
+#include <plat/csis.h>
+
+#include "csis.h"
+static s32 err_print_cnt;
+
+static struct s3c_csis_info *s3c_csis[S3C_CSIS_CH_NUM];
+
+static int s3c_csis_set_info(struct platform_device *pdev)
+{
+	s3c_csis[pdev->id] = (struct s3c_csis_info *)
+			kzalloc(sizeof(struct s3c_csis_info), GFP_KERNEL);
+	if (!s3c_csis[pdev->id]) {
+		err("no memory for configuration\n");
+		return -ENOMEM;
+	}
+
+	sprintf(s3c_csis[pdev->id]->name, "%s%d", S3C_CSIS_NAME, pdev->id);
+	s3c_csis[pdev->id]->nr_lanes = S3C_CSIS_NR_LANES;
+
+	return 0;
+}
+
+static void s3c_csis_reset(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg |= S3C_CSIS_CONTROL_RESET;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_set_nr_lanes(struct platform_device *pdev, int lanes)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONFIG);
+	cfg &= ~S3C_CSIS_CONFIG_NR_LANE_MASK;
+
+	if (lanes == 1)
+		cfg |= S3C_CSIS_CONFIG_NR_LANE_1;
+	else if (lanes == 2)
+		cfg |= S3C_CSIS_CONFIG_NR_LANE_2;
+	else if (lanes == 3)
+		cfg |= S3C_CSIS_CONFIG_NR_LANE_3;
+	else if (lanes == 4)
+		cfg |= S3C_CSIS_CONFIG_NR_LANE_4;
+	else
+		err("%d is not supported lane\n", lanes);
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONFIG);
+}
+
+static void s3c_csis_enable_interrupt(struct platform_device *pdev)
+{
+	u32 cfg = 0;
+
+	/* enable all interrupts */
+	cfg |= S3C_CSIS_INTMSK_EVEN_BEFORE_ENABLE | \
+		S3C_CSIS_INTMSK_EVEN_AFTER_ENABLE | \
+		S3C_CSIS_INTMSK_ODD_BEFORE_ENABLE | \
+		S3C_CSIS_INTMSK_ODD_AFTER_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_SOT_HS_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_LOST_FS_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_LOST_FE_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_OVER_ENABLE |\
+		S3C_CSIS_INTMSK_ERR_ECC_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_CRC_ENABLE | \
+		S3C_CSIS_INTMSK_ERR_ID_ENABLE;
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_INTMSK);
+}
+
+static void s3c_csis_disable_interrupt(struct platform_device *pdev)
+{
+	/* disable all interrupts */
+	writel(0, s3c_csis[pdev->id]->regs + S3C_CSIS_INTMSK);
+}
+
+static void s3c_csis_system_on(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg |= S3C_CSIS_CONTROL_ENABLE;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_system_off(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg &= ~S3C_CSIS_CONTROL_ENABLE;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_phy_on(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+	cfg |= S3C_CSIS_DPHYCTRL_ENABLE;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+}
+
+static void s3c_csis_phy_off(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+	cfg &= ~S3C_CSIS_DPHYCTRL_ENABLE;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+}
+
+#ifdef CONFIG_MIPI_CSI_ADV_FEATURE
+static void s3c_csis_update_shadow(struct platform_device *pdev)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg |= S3C_CSIS_CONTROL_UPDATE_SHADOW;
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_set_data_align(struct platform_device *pdev, int align)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg &= ~S3C_CSIS_CONTROL_ALIGN_MASK;
+
+	if (align == 24)
+		cfg |= S3C_CSIS_CONTROL_ALIGN_24BIT;
+	else
+		cfg |= S3C_CSIS_CONTROL_ALIGN_32BIT;
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_set_wclk(struct platform_device *pdev, int extclk)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+	cfg &= ~S3C_CSIS_CONTROL_WCLK_MASK;
+
+	if (extclk)
+		cfg |= S3C_CSIS_CONTROL_WCLK_EXTCLK;
+	else
+		cfg |= S3C_CSIS_CONTROL_WCLK_PCLK;
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONTROL);
+}
+
+static void s3c_csis_set_format(struct platform_device *pdev, enum mipi_format fmt)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_CONFIG);
+	cfg &= ~S3C_CSIS_CONFIG_FORMAT_MASK;
+	cfg |= (fmt << S3C_CSIS_CONFIG_FORMAT_SHIFT);
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_CONFIG);
+}
+
+static void s3c_csis_set_resol(struct platform_device *pdev, int width, int height)
+{
+	u32 cfg = 0;
+
+	cfg |= width << S3C_CSIS_RESOL_HOR_SHIFT;
+	cfg |= height << S3C_CSIS_RESOL_VER_SHIFT;
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_RESOL);
+}
+
+static void s3c_csis_set_hs_settle(struct platform_device *pdev, int settle)
+{
+	u32 cfg;
+
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+	cfg &= ~S3C_CSIS_DPHYCTRL_HS_SETTLE_MASK;
+	cfg |= (settle << S3C_CSIS_DPHYCTRL_HS_SETTLE_SHIFT);
+
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_DPHYCTRL);
+}
+#endif
+
+int s3c_csis_get_pkt(int csis_id, void *pktdata)
+{
+	memcpy(pktdata, s3c_csis[csis_id]->bufs.pktdata, CSIS_PKTSIZE);
+	return 0;
+}
+
+void s3c_csis_enable_pktdata(int csis_id, bool enable)
+{
+	s3c_csis[csis_id]->pktdata_enable = enable;
+}
+
+void s3c_csis_start(int csis_id, int lanes, int settle, int align, int width, \
+				int height, int pixel_format)
+{
+	struct platform_device *pdev = NULL;
+	struct s3c_platform_csis *pdata = NULL;
+	int i;
+
+	printk(KERN_INFO "csis width = %d, height = %d\n", width, height);
+
+	memset(&s3c_csis[csis_id]->bufs, 0, sizeof(s3c_csis[csis_id]->bufs));
+
+	/* clock & power on */
+	pdev = to_platform_device(s3c_csis[csis_id]->dev);
+	pdata = to_csis_plat(&pdev->dev);
+
+	if (pdata->clk_on)
+		pdata->clk_on(to_platform_device(s3c_csis[csis_id]->dev),
+			&s3c_csis[csis_id]->clock);
+	if (pdata->cfg_phy_global)
+		pdata->cfg_phy_global(1);
+
+	s3c_csis_reset(pdev);
+	s3c_csis_set_nr_lanes(pdev, lanes);
+
+#ifdef CONFIG_MIPI_CSI_ADV_FEATURE
+	/* FIXME: how configure the followings with FIMC dynamically? */
+	s3c_csis_set_hs_settle(pdev, settle);	/* s5k6aa */
+	s3c_csis_set_data_align(pdev, align);
+	s3c_csis_set_wclk(pdev, 1);
+	if (pixel_format == V4L2_PIX_FMT_JPEG ||
+		pixel_format == V4L2_PIX_FMT_INTERLEAVED) {
+			printk(KERN_INFO "%s V4L2_PIX_FMT_JPEG or INTERLEAVED\n", __func__);
+		s3c_csis_set_format(pdev, MIPI_USER_DEF_PACKET_1);
+	} else if (pixel_format == V4L2_PIX_FMT_SGRBG10)
+		s3c_csis_set_format(pdev, MIPI_CSI_RAW10);
+	else
+		s3c_csis_set_format(pdev, MIPI_CSI_YCBCR422_8BIT);
+	s3c_csis_set_resol(pdev, width, height);
+	s3c_csis_update_shadow(pdev);
+#endif
+
+	s3c_csis_enable_interrupt(pdev);
+	s3c_csis_system_on(pdev);
+	s3c_csis_phy_on(pdev);
+
+	err_print_cnt = 0;
+	info("Samsung MIPI-CSIS%d operation started\n", pdev->id);
+}
+
+void s3c_csis_stop(int csis_id)
+{
+	struct platform_device *pdev = NULL;
+	struct s3c_platform_csis *pdata = NULL;
+
+	pdev = to_platform_device(s3c_csis[csis_id]->dev);
+	pdata = to_csis_plat(&pdev->dev);
+
+	s3c_csis_disable_interrupt(pdev);
+	s3c_csis_system_off(pdev);
+	s3c_csis_phy_off(pdev);
+	s3c_csis[csis_id]->pktdata_enable = 0;
+
+	if (pdata->cfg_phy_global)
+		pdata->cfg_phy_global(0);
+
+	if (pdata->clk_off) {
+		if (s3c_csis[csis_id]->clock != NULL)
+			pdata->clk_off(pdev, &s3c_csis[csis_id]->clock);
+	}
+}
+
+static irqreturn_t s3c_csis_irq(int irq, void *dev_id)
+{
+	u32 cfg;
+
+	struct platform_device *pdev = (struct platform_device *) dev_id;
+	int bufnum = 0;
+	/* just clearing the pends */
+	cfg = readl(s3c_csis[pdev->id]->regs + S3C_CSIS_INTSRC);
+	writel(cfg, s3c_csis[pdev->id]->regs + S3C_CSIS_INTSRC);
+	/* receiving non-image data is not error */
+	cfg &= 0xFFFFFFFF;
+
+#ifdef CONFIG_VIDEO_FIMC_MIPI_IRQ_DEBUG
+	if (unlikely(cfg & S3C_CSIS_INTSRC_ERR)) {
+		if (err_print_cnt < 30) {
+			err("csis error interrupt[%d]: %#x\n", err_print_cnt, cfg);
+			err_print_cnt++;
+		}
+	}
+#endif
+	if(s3c_csis[pdev->id]->pktdata_enable) {
+		if (unlikely(cfg & S3C_CSIS_INTSRC_NON_IMAGE_DATA)) {
+			/* printk(KERN_INFO "%s NON Image Data bufnum = %d 0x%x\n", __func__, bufnum, cfg); */
+
+			if (cfg & S3C_CSIS_INTSRC_EVEN_BEFORE) {
+				/* printk(KERN_INFO "S3C_CSIS_INTSRC_EVEN_BEFORE\n"); */
+				memcpy_fromio(s3c_csis[pdev->id]->bufs.pktdata,
+					(s3c_csis[pdev->id]->regs + S3C_CSIS_PKTDATA_EVEN), CSIS_PKTSIZE);
+			} else if (cfg & S3C_CSIS_INTSRC_EVEN_AFTER) {
+				/* printk(KERN_INFO "S3C_CSIS_INTSRC_EVEN_AFTER\n"); */
+				memcpy_fromio(s3c_csis[pdev->id]->bufs.pktdata,
+					(s3c_csis[pdev->id]->regs + S3C_CSIS_PKTDATA_EVEN), CSIS_PKTSIZE);
+			} else if (cfg & S3C_CSIS_INTSRC_ODD_BEFORE) {
+				/* printk(KERN_INFO "S3C_CSIS_INTSRC_ODD_BEFORE\n"); */
+				memcpy_fromio(s3c_csis[pdev->id]->bufs.pktdata,
+					(s3c_csis[pdev->id]->regs + S3C_CSIS_PKTDATA_ODD), CSIS_PKTSIZE);
+			} else if (cfg & S3C_CSIS_INTSRC_ODD_AFTER) {
+				/* printk(KERN_INFO "S3C_CSIS_INTSRC_ODD_AFTER\n"); */
+				memcpy_fromio(s3c_csis[pdev->id]->bufs.pktdata,
+					(s3c_csis[pdev->id]->regs + S3C_CSIS_PKTDATA_ODD), CSIS_PKTSIZE);
+			}
+			/* printk(KERN_INFO "0x%x\n", s3c_csis[pdev->id]->bufs.pktdata[0x2c/4]); */
+			/* printk(KERN_INFO "0x%x\n", s3c_csis[pdev->id]->bufs.pktdata[0x30/4]); */
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int s3c_csis_probe(struct platform_device *pdev)
+{
+	struct s3c_platform_csis *pdata;
+	struct resource *res;
+	int ret = 0;
+
+	ret = s3c_csis_set_info(pdev);
+
+	s3c_csis[pdev->id]->dev = &pdev->dev;
+
+	pdata = to_csis_plat(&pdev->dev);
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio();
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		err("failed to get io memory region\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	s3c_csis[pdev->id]->regs_res = request_mem_region(res->start,
+				resource_size(res), pdev->name);
+	if (!s3c_csis[pdev->id]->regs_res) {
+		err("failed to request io memory region\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	/* ioremap for register block */
+	s3c_csis[pdev->id]->regs = ioremap(res->start, resource_size(res));
+	if (!s3c_csis[pdev->id]->regs) {
+		err("failed to remap io region\n");
+		ret = -ENXIO;
+		goto err_req_region;
+	}
+
+	/* irq */
+	s3c_csis[pdev->id]->irq = platform_get_irq(pdev, 0);
+	ret = request_irq(s3c_csis[pdev->id]->irq, s3c_csis_irq, IRQF_DISABLED,
+			s3c_csis[pdev->id]->name, pdev);
+	if (ret) {
+		err("request_irq failed\n");
+		goto err_regs_unmap;
+	}
+
+	info("Samsung MIPI-CSIS%d driver probed successfully\n", pdev->id);
+
+	return 0;
+
+err_regs_unmap:
+	iounmap(s3c_csis[pdev->id]->regs);
+err_req_region:
+	release_resource(s3c_csis[pdev->id]->regs_res);
+	kfree(s3c_csis[pdev->id]->regs_res);
+err_info:
+	kfree(s3c_csis[pdev->id]);
+
+	return ret;
+}
+
+static int s3c_csis_remove(struct platform_device *pdev)
+{
+	s3c_csis_stop(pdev->id);
+
+	free_irq(s3c_csis[pdev->id]->irq, s3c_csis[pdev->id]);
+	iounmap(s3c_csis[pdev->id]->regs);
+	release_resource(s3c_csis[pdev->id]->regs_res);
+
+	kfree(s3c_csis[pdev->id]);
+
+	return 0;
+}
+
+/* sleep */
+int s3c_csis_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct s3c_platform_csis *pdata = NULL;
+	pdata = to_csis_plat(&pdev->dev);
+
+	return 0;
+}
+
+/* wakeup */
+int s3c_csis_resume(struct platform_device *pdev)
+{
+	struct s3c_platform_csis *pdata = NULL;
+	pdata = to_csis_plat(&pdev->dev);
+
+	return 0;
+}
+
+static struct platform_driver s3c_csis_driver = {
+	.probe		= s3c_csis_probe,
+	.remove		= s3c_csis_remove,
+	.suspend	= s3c_csis_suspend,
+	.resume		= s3c_csis_resume,
+	.driver		= {
+		.name	= "s3c-csis",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int s3c_csis_register(void)
+{
+	return platform_driver_register(&s3c_csis_driver);
+}
+
+static void s3c_csis_unregister(void)
+{
+	platform_driver_unregister(&s3c_csis_driver);
+}
+
+module_init(s3c_csis_register);
+module_exit(s3c_csis_unregister);
+
+MODULE_AUTHOR("Jinsung, Yang <jsgood.yang@samsung.com>");
+MODULE_AUTHOR("Sewoon, Park <seuni.park@samsung.com>");
+MODULE_AUTHOR("Sungchun, Kang<sungchun.kang@samsung.com>");
+MODULE_DESCRIPTION("MIPI-CSI2 support for FIMC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimc/csis.h b/drivers/media/video/samsung/fimc/csis.h
new file mode 100644
index 0000000..fe0d689
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/csis.h
@@ -0,0 +1,60 @@
+/* linux/drivers/media/video/samsung/csis.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co,. Ltd.
+ *	http://www.samsung.com/
+ *
+ * Header file for Samsung MIPI-CSI2 driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __CSIS_H
+#define __CSIS_H __FILE__
+
+#define S3C_CSIS_NAME		"s3c-csis"
+#define S3C_CSIS_NR_LANES	1
+
+#define CSIS_PKTSIZE		0x1000
+
+#ifdef CONFIG_ARCH_EXYNOS4
+#define S3C_CSIS_CH_NUM		2
+#else
+#define S3C_CSIS_CH_NUM		1
+#endif
+
+#define info(args...)	\
+	do { printk(KERN_INFO S3C_CSIS_NAME ": " args); } while (0)
+#define err(args...)	\
+	do { printk(KERN_ERR  S3C_CSIS_NAME ": " args); } while (0)
+
+enum mipi_format {
+	MIPI_CSI_YCBCR422_8BIT	= 0x1e,
+	MIPI_CSI_RAW8		= 0x2a,
+	MIPI_CSI_RAW10		= 0x2b,
+	MIPI_CSI_RAW12		= 0x2c,
+	MIPI_USER_DEF_PACKET_1	= 0x30,	/* User defined Byte-based packet 1 */
+};
+
+struct csis_pkt_set {
+	int			id;
+	u32			pktdata[1024];
+	struct list_head	list;
+};
+
+struct s3c_csis_info {
+	char		name[16];
+	struct device	*dev;
+	struct clk	*clock;
+	void __iomem	*regs;
+	struct resource *regs_res;
+	int		irq;
+	int		nr_lanes;
+	bool		pktdata_enable;
+
+	struct csis_pkt_set	bufs;
+	spinlock_t		csis_spinlock;
+};
+
+#endif /* __CSIS_H */
diff --git a/drivers/media/video/samsung/fimc/fimc-ipc.h b/drivers/media/video/samsung/fimc/fimc-ipc.h
new file mode 100644
index 0000000..8e85d6e
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc-ipc.h
@@ -0,0 +1,146 @@
+/* linux/drivers/media/video/samsung/fimc/fimc-ipc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file for Samsung IPC driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMC_IPC_H
+#define __FIMC_IPC_H __FILE__
+
+#define IPC_NAME		"s3c-ipc"
+#define IPC_CLK_NAME		"ipc"
+
+#define OFF			0
+#define ON			1
+
+#define IN_SC_MAX_WIDTH		1024
+#define IN_SC_MAX_HEIGHT	768
+
+#define ipc_err(args...) do { printk(KERN_ERR  IPC_NAME ": " args); } while (0)
+
+enum ipc_enoff {
+	DISABLED,
+	ENABLED
+};
+
+enum ipc_field_id {
+	IPC_TOP_FIELD,
+	IPC_BOTTOM_FIELD
+};
+
+enum ipc_field_id_sel {
+	INTERNAL,
+	CAM_FIELD_SIG
+};
+
+enum ipc_field_id_togl {
+	BYUSER,
+	AUTO
+};
+
+enum ipc_2d {
+	IPC_HDS, /* Horizontal Double scaling */
+	IPC_2D	/* 2D IPC */
+};
+
+enum scan_mode {
+	PROGRESSIVE
+};
+
+enum ipc_sharpness {
+	NO_EFFECT,
+	MIN_EDGE,
+	MODERATE_EDGE,
+	MAX_EDGE
+};
+
+enum ipc_pp_lineeq_val {
+	IPC_PP_LINEEQ_0 = 0,
+	IPC_PP_LINEEQ_1,
+	IPC_PP_LINEEQ_2,
+	IPC_PP_LINEEQ_3,
+	IPC_PP_LINEEQ_4,
+	IPC_PP_LINEEQ_5,
+	IPC_PP_LINEEQ_6,
+	IPC_PP_LINEEQ_7,
+	IPC_PP_LINEEQ_ALL
+};
+
+enum ipc_filter_h_pp {
+	/* Don't change the order and the value */
+	IPC_PP_H_NORMAL = 0,
+	IPC_PP_H_8_9,		/* 720 to 640 */
+	IPC_PP_H_1_2,
+	IPC_PP_H_1_3,
+	IPC_PP_H_1_4
+};
+
+enum ipc_filter_v_pp{
+	/* Don't change the order and the value */
+	IPC_PP_V_NORMAL = 0,
+	IPC_PP_V_5_6,		/* PAL to NTSC */
+	IPC_PP_V_3_4,
+	IPC_PP_V_1_2,
+	IPC_PP_V_1_3,
+	IPC_PP_V_1_4
+};
+
+struct ipc_source{
+	u32 srcstaddr;
+	u32 imghsz;
+	u32 imgvsz;
+	u32 srcxpos;
+	u32 srcypos;
+	u32 srchsz;
+	u32 srcvsz;
+	u32 srcnumoffrm;
+	u32 lastfrmbufidx;
+};
+
+struct ipc_destination {
+	enum scan_mode scanmode;
+	u32 orgdsthsz;
+	u32 orgdstvsz;
+	u32 dstxpos;
+	u32 dstypos;
+	u32 dsthsz;
+	u32 dstvsz;
+};
+
+struct ipc_controlvariable {
+	u32 modeval;
+	u32 lineeqval;
+	u32 scanconversionidx;
+};
+
+struct ipc_enhancingvariable {
+	u32 contrast[8];
+	u32 brightness[8];
+	u32 saturation;
+	enum ipc_sharpness sharpness;
+	u32 thhnoise;
+	u32 brightoffset;
+};
+
+struct ipc_control {
+	char				name[16];
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct device			*dev;
+	struct ipc_source 		src;
+	struct ipc_destination 		dst;
+	struct ipc_controlvariable 	control_var;
+	struct ipc_enhancingvariable	enhance_var;
+};
+
+extern int ipc_init(u32 input_width, u32 input_height, enum ipc_2d ipc2d);
+extern void ipc_start(void);
+extern void ipc_stop(void);
+
+#endif /* __FIMC_IPC_H */
diff --git a/drivers/media/video/samsung/fimc/fimc.h b/drivers/media/video/samsung/fimc/fimc.h
new file mode 100644
index 0000000..9527f52
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc.h
@@ -0,0 +1,770 @@
+/* linux/drivers/media/video/samsung/fimc/fimc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef __FIMC_H
+#define __FIMC_H __FILE__
+
+#ifdef __KERNEL__
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf-core.h>
+#include <media/v4l2-mediabus.h>
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#include <mach/dev.h>
+#endif
+#include <plat/media.h>
+#include <plat/fimc.h>
+#include <plat/cpu.h>
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+
+#define FIMC_NAME		"s3c-fimc"
+#define FIMC_CMA_NAME		"fimc"
+
+#define FIMC_CORE_CLK		"sclk_fimc"
+#define FIMC_CLK_RATE		166750000
+#define EXYNOS_BUSFREQ_NAME	"exynos-busfreq"
+
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define FIMC_DEVICES		4
+#define FIMC_PHYBUFS		32
+#define FIMC_MAXCAMS		7
+#else
+#define FIMC_DEVICES		3
+#define FIMC_PHYBUFS		4
+#define FIMC_MAXCAMS		5
+#endif
+
+#define FIMC_SUBDEVS		3
+#define FIMC_OUTBUFS		3
+#define FIMC_INQUEUES		10
+#define FIMC_MAX_CTXS		4
+#define FIMC_TPID		3
+#define FIMC_CAPBUFS		32
+#define FIMC_ONESHOT_TIMEOUT	200
+#define FIMC_DQUEUE_TIMEOUT	1000
+
+#define FIMC_FIFOOFF_CNT	1000000 /* Sufficiently big value for stop */
+
+#define FORMAT_FLAGS_PACKED	0x1
+#define FORMAT_FLAGS_PLANAR	0x2
+
+#define FIMC_ADDR_Y		0
+#define FIMC_ADDR_CB		1
+#define FIMC_ADDR_CR		2
+
+#define FIMC_HD_WIDTH		1280
+#define FIMC_HD_HEIGHT		720
+
+#define FIMC_FHD_WIDTH		1920
+#define FIMC_FHD_HEIGHT		1080
+
+#define FIMC_MMAP_IDX		-1
+#define FIMC_USERPTR_IDX	-2
+
+#define FIMC_HCLK		0
+#define FIMC_SCLK		1
+#define CSI_CH_0		0
+#define CSI_CH_1		1
+#if defined(CONFIG_VIDEO_FIMC_FIFO)
+#define FIMC_OVLY_MODE FIMC_OVLY_FIFO
+#elif defined(CONFIG_VIDEO_FIMC_DMA_AUTO)
+#define FIMC_OVLY_MODE FIMC_OVLY_DMA_AUTO
+#endif
+
+#define PINGPONG_2ADDR_MODE
+#if defined(PINGPONG_2ADDR_MODE)
+#define FIMC_PINGPONG 2
+#endif
+
+#define check_bit(data, loc)	((data) & (0x1<<(loc)))
+#define FRAME_SEQ		0xf
+
+#define fimc_cam_use		((pdata->use_cam) ? 1 : 0)
+
+#define L2_FLUSH_ALL	SZ_1M
+#define L1_FLUSH_ALL	SZ_64K
+
+/*
+ * ENUMERATIONS
+*/
+enum fimc_status {
+	FIMC_READY_OFF		= 0x00,
+	FIMC_STREAMOFF		= 0x01,
+	FIMC_READY_ON		= 0x02,
+	FIMC_STREAMON		= 0x03,
+	FIMC_STREAMON_IDLE	= 0x04, /* oneshot mode */
+	FIMC_OFF_SLEEP		= 0x05,
+	FIMC_ON_SLEEP		= 0x06,
+	FIMC_ON_IDLE_SLEEP	= 0x07, /* oneshot mode */
+	FIMC_READY_RESUME	= 0x08,
+	FIMC_BUFFER_STOP	= 0x09,
+	FIMC_BUFFER_START	= 0x0A,
+};
+
+enum fimc_fifo_state {
+	FIFO_CLOSE,
+	FIFO_SLEEP,
+};
+
+enum fimc_fimd_state {
+	FIMD_OFF,
+	FIMD_ON,
+};
+
+enum fimc_rot_flip {
+	FIMC_XFLIP	= 0x01,
+	FIMC_YFLIP	= 0x02,
+	FIMC_ROT	= 0x10,
+};
+
+enum fimc_input {
+	FIMC_SRC_CAM,
+	FIMC_SRC_MSDMA,
+};
+
+enum fimc_overlay_mode {
+	FIMC_OVLY_NOT_FIXED		= 0x0,	/* Overlay mode isn't fixed. */
+	FIMC_OVLY_FIFO			= 0x1,	/* Non-destructive Overlay with FIFO */
+	FIMC_OVLY_DMA_AUTO		= 0x2,	/* Non-destructive Overlay with DMA */
+	FIMC_OVLY_DMA_MANUAL		= 0x3,	/* Non-destructive Overlay with DMA */
+	FIMC_OVLY_NONE_SINGLE_BUF	= 0x4,	/* Destructive Overlay with DMA single destination buffer */
+	FIMC_OVLY_NONE_MULTI_BUF	= 0x5,	/* Destructive Overlay with DMA multiple dstination buffer */
+};
+
+enum fimc_autoload {
+	FIMC_AUTO_LOAD,
+	FIMC_ONE_SHOT,
+};
+
+enum fimc_log {
+	FIMC_LOG_DEBUG		= 0x1000,
+	FIMC_LOG_INFO_L2	= 0x0200,
+	FIMC_LOG_INFO_L1	= 0x0100,
+	FIMC_LOG_WARN		= 0x0010,
+	FIMC_LOG_ERR		= 0x0001,
+};
+
+enum fimc_range {
+	FIMC_RANGE_NARROW	= 0x0,
+	FIMC_RANGE_WIDE		= 0x1,
+};
+
+enum fimc_pixel_format_type{
+	FIMC_RGB,
+	FIMC_YUV420,
+	FIMC_YUV422,
+	FIMC_YUV444,
+};
+
+enum fimc_framecnt_seq {
+	FIMC_FRAMECNT_SEQ_DISABLE,
+	FIMC_FRAMECNT_SEQ_ENABLE,
+};
+
+enum fimc_sysmmu_flag {
+	FIMC_SYSMMU_OFF,
+	FIMC_SYSMMU_ON,
+};
+
+enum fimc_id {
+	FIMC0 = 0x0,
+	FIMC1 = 0x1,
+	FIMC2 = 0x2,
+	FIMC3 = 0x3,
+};
+
+enum fimc_power_status {
+	FIMC_POWER_OFF,
+	FIMC_POWER_ON,
+	FIMC_POWER_SUSPEND,
+};
+
+enum cam_mclk_status {
+	CAM_MCLK_OFF,
+	CAM_MCLK_ON,
+};
+
+/*
+ * STRUCTURES
+*/
+
+/* for reserved memory */
+struct fimc_meminfo {
+	dma_addr_t	base;		/* buffer base */
+	size_t		size;		/* total length */
+	dma_addr_t	curr;		/* current addr */
+	dma_addr_t	vaddr_base;		/* buffer base */
+	dma_addr_t	vaddr_curr;		/* current addr */
+};
+
+struct fimc_buf {
+	dma_addr_t	base[3];
+	size_t		length[3];
+};
+
+struct fimc_overlay_buf {
+	u32 vir_addr[3];
+	size_t size[3];
+	u32 phy_addr[3];
+};
+
+struct fimc_overlay {
+	enum fimc_overlay_mode mode;
+	struct fimc_overlay_buf buf;
+	s32 req_idx;
+};
+
+/* general buffer */
+struct fimc_buf_set {
+	int			id;
+	dma_addr_t		base[4];
+	dma_addr_t		vaddr_base[4];
+	size_t			length[4];
+	size_t			garbage[4];
+	enum videobuf_state	state;
+	u32			flags;
+	atomic_t		mapped_cnt;
+	dma_addr_t		paddr_pktdata;
+	u32			*vaddr_pktdata;
+	struct list_head	list;
+};
+
+/* for capture device */
+struct fimc_capinfo {
+	struct v4l2_cropcap	cropcap;
+	struct v4l2_rect	crop;
+	struct v4l2_pix_format	fmt;
+	struct v4l2_mbus_framefmt mbus_fmt;
+	struct fimc_buf_set	bufs[FIMC_CAPBUFS];
+	/* using c110 */
+	struct list_head	inq;
+	int			outq[FIMC_PHYBUFS];
+	/* using c210 */
+	struct list_head	outgoing_q;
+	int			nr_bufs;
+	int			irq;
+	int			lastirq;
+
+	bool			cacheable;
+	bool			pktdata_enable;
+	u32			pktdata_size;
+	u32			pktdata_plane;
+
+	u32			cnt;
+	u32			poll_cnt;
+
+	/* flip: V4L2_CID_xFLIP, rotate: 90, 180, 270 */
+	u32			flip;
+	u32			rotate;
+	u32			dtp_mode;
+	u32			movie_mode;
+	u32			vt_mode;
+	u32			sensor_output_width;
+	u32			sensor_output_height;
+};
+
+/* for output overlay device */
+struct fimc_idx {
+	int ctx;
+	int idx;
+};
+
+struct fimc_ctx_idx {
+	struct fimc_idx prev;
+	struct fimc_idx active;
+	struct fimc_idx next;
+};
+
+/* scaler abstraction: local use recommended */
+struct fimc_scaler {
+	u32 bypass;
+	u32 hfactor;
+	u32 vfactor;
+	u32 pre_hratio;
+	u32 pre_vratio;
+	u32 pre_dst_width;
+	u32 pre_dst_height;
+	u32 scaleup_h;
+	u32 scaleup_v;
+	u32 main_hratio;
+	u32 main_vratio;
+	u32 real_width;
+	u32 real_height;
+	u32 shfactor;
+	u32 skipline;
+};
+
+struct fimc_ctx {
+	u32			ctx_num;
+	struct v4l2_cropcap	cropcap;
+	struct v4l2_rect 	crop;
+	struct v4l2_pix_format	pix;
+	struct v4l2_window	win;
+	struct v4l2_framebuffer	fbuf;
+	struct fimc_scaler	sc;
+	struct fimc_overlay	overlay;
+
+	u32			buf_num;
+	u32			is_requested;
+	struct fimc_buf_set	src[FIMC_OUTBUFS];
+	struct fimc_buf_set	dst[FIMC_OUTBUFS];
+	s32			inq[FIMC_OUTBUFS];
+	s32			outq[FIMC_OUTBUFS];
+
+	u32			flip;
+	u32			rotate;
+	enum fimc_status	status;
+};
+
+struct fimc_outinfo {
+	int			last_ctx;
+	spinlock_t		lock_in;
+	spinlock_t		lock_out;
+	spinlock_t		slock;
+	struct fimc_idx		inq[FIMC_INQUEUES];
+	struct fimc_ctx		ctx[FIMC_MAX_CTXS];
+	bool			ctx_used[FIMC_MAX_CTXS];
+	struct fimc_ctx_idx	idxs;
+};
+
+struct s3cfb_user_window {
+	int x;
+	int y;
+};
+
+enum s3cfb_data_path_t {
+	DATA_PATH_FIFO	= 0,
+	DATA_PATH_DMA	= 1,
+	DATA_PATH_IPC	= 2,
+};
+
+enum s3cfb_mem_owner_t {
+	DMA_MEM_NONE	= 0,
+	DMA_MEM_FIMD	= 1,
+	DMA_MEM_OTHER	= 2,
+};
+#define S3CFB_WIN_OFF_ALL	_IO('F', 202)
+#define S3CFB_WIN_POSITION	_IOW('F', 203, struct s3cfb_user_window)
+#define S3CFB_GET_LCD_WIDTH	_IOR('F', 302, int)
+#define S3CFB_GET_LCD_HEIGHT	_IOR('F', 303, int)
+#define S3CFB_SET_WRITEBACK	_IOW('F', 304, u32)
+#define S3CFB_SET_WIN_ON	_IOW('F', 305, u32)
+#define S3CFB_SET_WIN_OFF	_IOW('F', 306, u32)
+#define S3CFB_SET_WIN_PATH	_IOW('F', 307, enum s3cfb_data_path_t)
+#define S3CFB_SET_WIN_ADDR	_IOW('F', 308, unsigned long)
+#define S3CFB_SET_WIN_MEM	_IOW('F', 309, enum s3cfb_mem_owner_t)
+/* ------------------------------------------------------------------------ */
+
+struct fimc_fbinfo {
+	struct fb_fix_screeninfo	*fix;
+	struct fb_var_screeninfo	*var;
+	int				lcd_hres;
+	int				lcd_vres;
+	u32				is_enable;
+	/* lcd fifo control */
+
+	int (*open_fifo)(int id, int ch, int (*do_priv)(void *), void *param);
+	int (*close_fifo)(int id, int (*do_priv)(void *), void *param);
+};
+
+struct fimc_limit {
+	u32 pre_dst_w;
+	u32 bypass_w;
+	u32 trg_h_no_rot;
+	u32 trg_h_rot;
+	u32 real_w_no_rot;
+	u32 real_h_rot;
+};
+
+enum FIMC_EFFECT_FIN {
+	FIMC_EFFECT_FIN_BYPASS = 0,
+	FIMC_EFFECT_FIN_ARBITRARY_CBCR,
+	FIMC_EFFECT_FIN_NEGATIVE,
+	FIMC_EFFECT_FIN_ART_FREEZE,
+	FIMC_EFFECT_FIN_EMBOSSING,
+	FIMC_EFFECT_FIN_SILHOUETTE,
+};
+
+
+struct fimc_effect {
+	int ie_on;
+	int ie_after_sc;
+	enum FIMC_EFFECT_FIN fin;
+	int pat_cb;
+	int pat_cr;
+};
+
+struct fimc_is {
+	struct v4l2_pix_format	fmt;
+	struct v4l2_mbus_framefmt mbus_fmt;
+	struct v4l2_subdev      *sd;
+	u32 frame_count;
+	u32 valid;
+	u32 bad_mark;
+	u32 offset_x;
+	u32 offset_y;
+	u32 zoom_in_width;
+	u32 zoom_in_height;
+};
+
+/* fimc controller abstration */
+struct fimc_control {
+	int				id;		/* controller id */
+	char				name[16];
+	atomic_t			in_use;
+	void __iomem			*regs;		/* register i/o */
+	struct clk			*clk;		/* interface clock */
+	struct fimc_meminfo		mem;		/* for reserved mem */
+	atomic_t			irq_cnt;	/* for interrupt cnt */
+	struct work_struct		work_struct;	/* for work queue */
+	struct workqueue_struct		*fimc_irq_wq;	/* for work queue */
+
+	/* kernel helpers */
+	struct mutex			lock;		/* controller lock */
+	struct mutex			v4l2_lock;
+	spinlock_t			outq_lock;
+	wait_queue_head_t		wq;
+	struct device			*dev;
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	struct device			*bus_dev;
+#endif
+	int				irq;
+
+	/* v4l2 related */
+	struct video_device		*vd;
+	struct v4l2_device		v4l2_dev;
+	struct v4l2_subdev		*flite_sd;
+	struct fimc_is			is;
+	/* fimc specific */
+	struct fimc_limit		*limit;		/* H/W limitation */
+	struct s3c_platform_camera	*cam;		/* activated camera */
+	struct fimc_capinfo		*cap;		/* capture dev info */
+	struct fimc_outinfo		*out;		/* output dev info */
+	struct fimc_fbinfo		fb;		/* fimd info */
+	struct fimc_scaler		sc;		/* scaler info */
+	struct fimc_effect		fe;		/* fimc effect info */
+
+	enum fimc_status		status;
+	enum fimc_log			log;
+	enum fimc_range			range;
+	/* for suspend mode */
+	int 				suspend_flag;
+	int 				suspend_framecnt;
+	enum fimc_sysmmu_flag		sysmmu_flag;
+	enum fimc_power_status		power_status;
+	struct timeval			curr_time;
+	struct timeval			before_time;
+	char 				cma_name[16];
+	bool				restart;
+};
+
+/* global */
+struct fimc_global {
+	struct fimc_control 		ctrl[FIMC_DEVICES];
+	struct s3c_platform_camera	*camera[FIMC_MAXCAMS];
+	int				camera_isvalid[FIMC_MAXCAMS];
+	int 				active_camera;
+	int				initialized;
+	enum cam_mclk_status		mclk_status;
+	void __iomem				*backup_regs[4];
+};
+
+struct fimc_prv_data {
+	struct fimc_control *ctrl;
+	int ctx_id;
+};
+
+/* debug macro */
+#define FIMC_LOG_DEFAULT	(FIMC_LOG_WARN | FIMC_LOG_ERR)
+
+#define FIMC_DEBUG(fmt, ...)						\
+	do {								\
+		if (ctrl->log & FIMC_LOG_DEBUG)				\
+			printk(KERN_DEBUG FIMC_NAME "%d: "		\
+				fmt, ctrl->id, ##__VA_ARGS__);			\
+	} while (0)
+
+#define FIMC_INFO_L2(fmt, ...)						\
+	do {								\
+		if (ctrl->log & FIMC_LOG_INFO_L2)			\
+			printk(KERN_INFO FIMC_NAME "%d: "		\
+				fmt, ctrl->id, ##__VA_ARGS__);			\
+	} while (0)
+
+#define FIMC_INFO_L1(fmt, ...)						\
+	do {								\
+		if (ctrl->log & FIMC_LOG_INFO_L1)			\
+			printk(KERN_INFO FIMC_NAME "%d: "		\
+				fmt, ctrl->id, ##__VA_ARGS__);			\
+	} while (0)
+
+#define FIMC_WARN(fmt, ...)						\
+	do {								\
+		if (ctrl->log & FIMC_LOG_WARN)				\
+			printk(KERN_WARNING FIMC_NAME "%d: "		\
+				fmt, ctrl->id, ##__VA_ARGS__);			\
+	} while (0)
+
+
+#define FIMC_ERROR(fmt, ...)						\
+	do {								\
+		if (ctrl->log & FIMC_LOG_ERR)				\
+			printk(KERN_ERR FIMC_NAME "%d: "		\
+				fmt, ctrl->id, ##__VA_ARGS__);			\
+	} while (0)
+
+
+#define fimc_dbg(fmt, ...)		FIMC_DEBUG(fmt, ##__VA_ARGS__)
+#define fimc_info2(fmt, ...)		FIMC_INFO_L2(fmt, ##__VA_ARGS__)
+#define fimc_info1(fmt, ...)		FIMC_INFO_L1(fmt, ##__VA_ARGS__)
+#define fimc_warn(fmt, ...)		FIMC_WARN(fmt, ##__VA_ARGS__)
+#define fimc_err(fmt, ...)		FIMC_ERROR(fmt, ##__VA_ARGS__)
+
+/*
+ * EXTERNS
+*/
+extern struct fimc_global *fimc_dev;
+extern struct video_device fimc_video_device[FIMC_DEVICES];
+extern const struct v4l2_ioctl_ops fimc_v4l2_ops;
+extern struct fimc_limit fimc40_limits[FIMC_DEVICES];
+extern struct fimc_limit fimc43_limits[FIMC_DEVICES];
+extern struct fimc_limit fimc50_limits[FIMC_DEVICES];
+extern struct fimc_limit fimc51_limits[FIMC_DEVICES];
+
+/* FIMD */
+#ifdef CONFIG_FB_S5P /* Legacy FIMD */
+extern int s3cfb_direct_ioctl(int id, unsigned int cmd, unsigned long arg);
+extern int s3cfb_open_fifo(int id, int ch, int (*do_priv)(void *), void *param);
+extern int s3cfb_close_fifo(int id, int (*do_priv)(void *), void *param);
+#else /* Mainline FIMD */
+#ifdef CONFIG_DRM_EXYNOS_FIMD_WB
+extern int fimc_send_event(unsigned long val, void *v);
+static inline int s3cfb_direct_ioctl(int id, unsigned int cmd,
+unsigned long arg) { return fimc_send_event(cmd, (void *)arg); }
+#else
+static inline int s3cfb_direct_ioctl(int id, unsigned int cmd, unsigned long arg) { return 0; }
+#endif
+static inline int s3cfb_open_fifo(int id, int ch, int (*do_priv)(void *), void *param) { return 0; }
+static inline int s3cfb_close_fifo(int id, int (*do_priv)(void *), void *param) { return 0; }
+#endif
+
+/* general */
+extern void s3c_csis_start(int csis_id, int lanes, int settle, int align, int width, int height, int pixel_format);
+extern void s3c_csis_stop(int csis_id);
+extern int s3c_csis_get_pkt(int csis_id, void *pktdata);
+extern void s3c_csis_enable_pktdata(int csis_id, bool enable);
+extern int fimc_dma_alloc(struct fimc_control *ctrl, struct fimc_buf_set *bs, int i, int align);
+extern void fimc_dma_free(struct fimc_control *ctrl, struct fimc_buf_set *bs, int i);
+extern u32 fimc_mapping_rot_flip(u32 rot, u32 flip);
+extern int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift);
+extern void fimc_get_nv12t_size(int img_hres, int img_vres,
+					int *y_size, int *cb_size);
+extern int fimc_hwget_number_of_bits(u32 framecnt_seq);
+
+/* camera */
+extern int fimc_select_camera(struct fimc_control *ctrl);
+
+/* capture device */
+extern int fimc_enum_input(struct file *file, void *fh, struct v4l2_input *inp);
+extern int fimc_g_input(struct file *file, void *fh, unsigned int *i);
+extern int fimc_s_input(struct file *file, void *fh, unsigned int i);
+extern int fimc_enum_fmt_vid_capture(struct file *file, void *fh, struct v4l2_fmtdesc *f);
+extern int fimc_g_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f);
+extern int fimc_s_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f);
+extern int fimc_s_fmt_vid_private(struct file *file, void *fh, struct v4l2_format *f);
+extern int fimc_try_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f);
+extern int fimc_reqbufs_capture(void *fh, struct v4l2_requestbuffers *b);
+extern int fimc_querybuf_capture(void *fh, struct v4l2_buffer *b);
+extern int fimc_g_ctrl_capture(void *fh, struct v4l2_control *c);
+extern int fimc_g_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c);
+extern int fimc_s_ctrl_capture(void *fh, struct v4l2_control *c);
+extern int fimc_s_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c);
+#if defined(CONFIG_CPU_S5PV210)
+extern int fimc_change_clksrc(struct fimc_control *ctrl, int fimc_clk);
+#endif
+extern int fimc_cropcap_capture(void *fh, struct v4l2_cropcap *a);
+extern int fimc_g_crop_capture(void *fh, struct v4l2_crop *a);
+extern int fimc_s_crop_capture(void *fh, struct v4l2_crop *a);
+extern int fimc_streamon_capture(void *fh);
+extern int fimc_streamoff_capture(void *fh);
+extern int fimc_qbuf_capture(void *fh, struct v4l2_buffer *b);
+extern int fimc_dqbuf_capture(void *fh, struct v4l2_buffer *b);
+extern int fimc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a);
+extern int fimc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a);
+extern int fimc_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *qc);
+extern int fimc_querymenu(struct file *file, void *fh, struct v4l2_querymenu *qm);
+extern int fimc_stop_capture(struct fimc_control *ctrl);
+extern int fimc_enum_framesizes(struct file *filp, void *fh, struct v4l2_frmsizeenum *fsize);
+extern int fimc_enum_frameintervals(struct file *filp, void *fh, struct v4l2_frmivalenum *fival);
+extern int fimc_release_subdev(struct fimc_control *ctrl);
+extern int fimc_is_release_subdev(struct fimc_control *ctrl);
+extern int fimc_is_set_zoom(struct fimc_control *ctrl, struct v4l2_control *c);
+/* output device */
+extern void fimc_outdev_set_src_addr(struct fimc_control *ctrl, dma_addr_t *base);
+extern int fimc_output_set_dst_addr(struct fimc_control *ctrl, struct fimc_ctx *ctx, int idx);
+extern int fimc_outdev_set_ctx_param(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern int fimc_start_fifo(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern int fimc_fimd_rect(const struct fimc_control *ctrl, const struct fimc_ctx *ctx, struct v4l2_rect *fimd_rect);
+extern int fimc_outdev_stop_streaming(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern int fimc_outdev_resume_dma(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern int fimc_outdev_start_camif(void *param);
+extern int fimc_reqbufs_output(void *fh, struct v4l2_requestbuffers *b);
+extern int fimc_querybuf_output(void *fh, struct v4l2_buffer *b);
+extern int fimc_g_ctrl_output(void *fh, struct v4l2_control *c);
+extern int fimc_s_ctrl_output(struct file *filp, void *fh, struct v4l2_control *c);
+extern int fimc_cropcap_output(void *fh, struct v4l2_cropcap *a);
+extern int fimc_g_crop_output(void *fh, struct v4l2_crop *a);
+extern int fimc_s_crop_output(void *fh, struct v4l2_crop *a);
+extern int fimc_streamon_output(void *fh);
+extern int fimc_streamoff_output(void *fh);
+extern int fimc_qbuf_output(void *fh, struct v4l2_buffer *b);
+extern int fimc_dqbuf_output(void *fh, struct v4l2_buffer *b);
+extern int fimc_g_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f);
+extern int fimc_s_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f);
+extern int fimc_try_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f);
+
+extern int fimc_init_in_queue(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern int fimc_push_inq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int idx);
+extern int fimc_pop_inq(struct fimc_control *ctrl, int *ctx_num, int *idx);
+extern int fimc_push_outq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int idx);
+extern int fimc_pop_outq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int *idx);
+extern int fimc_init_out_queue(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern void fimc_outdev_init_idxs(struct fimc_control *ctrl);
+
+extern void fimc_dump_context(struct fimc_control *ctrl, struct fimc_ctx *ctx);
+extern void fimc_print_signal(struct fimc_control *ctrl);
+extern void fimc_sfr_dump(struct fimc_control *ctrl);
+
+/* overlay device */
+extern int fimc_try_fmt_overlay(struct file *filp, void *fh, struct v4l2_format *f);
+extern int fimc_g_fmt_vid_overlay(struct file *filp, void *fh, struct v4l2_format *f);
+extern int fimc_s_fmt_vid_overlay(struct file *filp, void *fh, struct v4l2_format *f);
+extern int fimc_g_fbuf(struct file *filp, void *fh, struct v4l2_framebuffer *fb);
+extern int fimc_s_fbuf(struct file *filp, void *fh, struct v4l2_framebuffer *fb);
+
+/* Register access file */
+extern int fimc_hwset_camera_source(struct fimc_control *ctrl);
+extern int fimc_hwset_camera_change_source(struct fimc_control *ctrl);
+extern int fimc_hwset_enable_irq(struct fimc_control *ctrl, int overflow, int level);
+extern int fimc_hwset_disable_irq(struct fimc_control *ctrl);
+extern int fimc_hwset_clear_irq(struct fimc_control *ctrl);
+extern int fimc_hwset_reset(struct fimc_control *ctrl);
+extern int fimc_hwset_sw_reset(struct fimc_control *ctrl);
+extern int fimc_hwget_frame_end(struct fimc_control *ctrl);
+extern int fimc_hwset_clksrc(struct fimc_control *ctrl, int src_clk);
+extern int fimc_hwget_overflow_state(struct fimc_control *ctrl);
+extern int fimc_hwset_camera_offset(struct fimc_control *ctrl);
+extern int fimc_hwset_camera_polarity(struct fimc_control *ctrl);
+extern int fimc_hwset_camera_type(struct fimc_control *ctrl);
+extern int fimc_hwset_output_size(struct fimc_control *ctrl, int width, int height);
+extern int fimc_hwset_output_colorspace(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_output_rot_flip(struct fimc_control *ctrl, u32 rot, u32 flip);
+extern int fimc_hwset_output_area(struct fimc_control *ctrl, u32 width, u32 height);
+extern int fimc_hwset_output_area_size(struct fimc_control *ctrl, u32 size);
+extern int fimc_hwset_output_scan(struct fimc_control *ctrl, struct v4l2_pix_format *fmt);
+extern int fimc_hwset_enable_lastirq(struct fimc_control *ctrl);
+extern int fimc_hwset_disable_lastirq(struct fimc_control *ctrl);
+extern int fimc_hwset_enable_lastend(struct fimc_control *ctrl);
+extern int fimc_hwset_disable_lastend(struct fimc_control *ctrl);
+extern int fimc_hwset_prescaler(struct fimc_control *ctrl, struct fimc_scaler *sc);
+extern int fimc_hwset_output_yuv(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_output_address(struct fimc_control *ctrl, struct fimc_buf_set *bs, int id);
+extern int fimc_hwset_input_rot(struct fimc_control *ctrl, u32 rot, u32 flip);
+extern int fimc_hwset_scaler(struct fimc_control *ctrl, struct fimc_scaler *sc);
+extern int fimc_hwset_scaler_bypass(struct fimc_control *ctrl);
+extern int fimc_hwset_enable_lcdfifo(struct fimc_control *ctrl);
+extern int fimc_hwset_disable_lcdfifo(struct fimc_control *ctrl);
+extern int fimc_hwset_start_scaler(struct fimc_control *ctrl);
+extern int fimc_hwset_stop_scaler(struct fimc_control *ctrl);
+extern int fimc_hwset_input_rgb(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_intput_field(struct fimc_control *ctrl, enum v4l2_field field);
+extern int fimc_hwset_output_rgb(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_ext_rgb(struct fimc_control *ctrl, int enable);
+extern int fimc_hwset_enable_capture(struct fimc_control *ctrl, u32 bypass);
+extern int fimc_hwset_disable_capture(struct fimc_control *ctrl);
+extern void fimc_wait_disable_capture(struct fimc_control *ctrl);
+extern int fimc_hwset_input_address(struct fimc_control *ctrl, dma_addr_t *base);
+extern int fimc_hwset_enable_autoload(struct fimc_control *ctrl);
+extern int fimc_hwset_disable_autoload(struct fimc_control *ctrl);
+extern int fimc_hwset_real_input_size(struct fimc_control *ctrl, u32 width, u32 height);
+extern int fimc_hwset_addr_change_enable(struct fimc_control *ctrl);
+extern int fimc_hwset_addr_change_disable(struct fimc_control *ctrl);
+extern int fimc_hwset_input_burst_cnt(struct fimc_control *ctrl, u32 cnt);
+extern int fimc_hwset_input_colorspace(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_input_yuv(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_input_flip(struct fimc_control *ctrl, u32 rot, u32 flip);
+extern int fimc_hwset_input_source(struct fimc_control *ctrl, enum fimc_input path);
+extern int fimc_hwset_start_input_dma(struct fimc_control *ctrl);
+extern int fimc_hwset_stop_input_dma(struct fimc_control *ctrl);
+extern int fimc_hwset_output_offset(struct fimc_control *ctrl, u32 pixelformat, struct v4l2_rect *bound, struct v4l2_rect *crop);
+extern int fimc_hwset_input_offset(struct fimc_control *ctrl, u32 pixelformat, struct v4l2_rect *bound, struct v4l2_rect *crop);
+extern int fimc_hwset_org_input_size(struct fimc_control *ctrl, u32 width, u32 height);
+extern int fimc_hwset_org_output_size(struct fimc_control *ctrl, u32 width, u32 height);
+extern int fimc_hwset_ext_output_size(struct fimc_control *ctrl, u32 width, u32 height);
+extern int fimc_hwset_input_addr_style(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_output_addr_style(struct fimc_control *ctrl, u32 pixelformat);
+extern int fimc_hwset_jpeg_mode(struct fimc_control *ctrl, bool enable);
+extern int fimc_hwget_frame_count(struct fimc_control *ctrl);
+extern int fimc_hw_wait_winoff(struct fimc_control *ctrl);
+extern int fimc_hw_wait_stop_input_dma(struct fimc_control *ctrl);
+extern int fimc_hwset_input_lineskip(struct fimc_control *ctrl);
+extern int fimc_hw_reset_camera(struct fimc_control *ctrl);
+extern void fimc_reset_status_reg(struct fimc_control *ctrl);
+void fimc_hwset_stop_processing(struct fimc_control *ctrl);
+extern int fimc_hw_reset_output_buf_sequence(struct fimc_control *ctrl);
+extern int fimc_hwset_output_buf_sequence(struct fimc_control *ctrl, u32 shift, u32 enable);
+extern void fimc_hwset_output_buf_sequence_all(struct fimc_control *ctrl, u32 framecnt_seq);
+extern int fimc_hwget_output_buf_sequence(struct fimc_control *ctrl);
+extern int fimc_hwget_before_frame_count(struct fimc_control *ctrl);
+extern int fimc_hwget_present_frame_count(struct fimc_control *ctrl);
+extern int fimc_hwget_output_buf_sequence(struct fimc_control *ctrl);
+extern int fimc_hwget_check_framecount_sequence(struct fimc_control *ctrl, u32 frame);
+extern int fimc_hwset_image_effect(struct fimc_control *ctrl);
+extern int fimc_hwset_sysreg_camblk_fimd0_wb(struct fimc_control *ctrl);
+extern int fimc_hwset_sysreg_camblk_fimd1_wb(struct fimc_control *ctrl);
+extern int fimc_hwset_sysreg_camblk_isp_wb(struct fimc_control *ctrl);
+extern int fimc_hwget_last_frame_end(struct fimc_control *ctrl);
+extern void fimc_hwset_enable_frame_end_irq(struct fimc_control *ctrl);
+extern void fimc_hwset_disable_frame_end_irq(struct fimc_control *ctrl);
+extern void fimc_reset_status_reg(struct fimc_control *ctrl);
+/* IPC related file */
+extern void ipc_start(void);
+
+/*
+ * DRIVER HELPERS
+ *
+*/
+#define to_fimc_plat(d)		(to_platform_device(d)->dev.platform_data)
+
+static inline struct fimc_global *get_fimc_dev(void)
+{
+	return fimc_dev;
+}
+
+static inline struct fimc_control *get_fimc_ctrl(int id)
+{
+	return &fimc_dev->ctrl[id];
+}
+
+#endif /* __FIMC_H */
diff --git a/drivers/media/video/samsung/fimc/fimc_capture.c b/drivers/media/video/samsung/fimc/fimc_capture.c
new file mode 100644
index 0000000..fe0878a
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_capture.c
@@ -0,0 +1,3171 @@
+/* linux/drivers/media/video/samsung/fimc_capture.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * V4L2 Capture device support file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/clk.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <plat/media.h>
+#include <plat/clock.h>
+#include <plat/fimc.h>
+#include <linux/delay.h>
+
+#include <asm/cacheflush.h>
+#include <linux/pm_qos_params.h>
+
+#include "fimc.h"
+
+static struct pm_qos_request_list bus_qos_pm_qos_req;
+
+static const struct v4l2_fmtdesc capture_fmts[] = {
+	{
+		.index		= 0,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "RGB-5-6-5",
+		.pixelformat	= V4L2_PIX_FMT_RGB565,
+	}, {
+		.index		= 1,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "RGB-8-8-8, unpacked 24 bpp",
+		.pixelformat	= V4L2_PIX_FMT_RGB32,
+	}, {
+		.index		= 2,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+	}, {
+		.index		= 3,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, CbYCrY",
+		.pixelformat	= V4L2_PIX_FMT_UYVY,
+	}, {
+		.index		= 4,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, CrYCbY",
+		.pixelformat	= V4L2_PIX_FMT_VYUY,
+	}, {
+		.index		= 5,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, YCrYCb",
+		.pixelformat	= V4L2_PIX_FMT_YVYU,
+	}, {
+		.index		= 6,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV422P,
+	}, {
+		.index		= 7,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12,
+	}, {
+		.index		= 8,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CbCr, Tiled",
+		.pixelformat	= V4L2_PIX_FMT_NV12T,
+	}, {
+		.index		= 9,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21,
+	}, {
+		.index		= 10,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV16,
+	}, {
+		.index		= 11,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV61,
+	}, {
+		.index		= 12,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420,
+	}, {
+		.index		= 13,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/Cr/Cb",
+		.pixelformat	= V4L2_PIX_FMT_YVU420,
+	}, {
+		.index		= 14,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.description	= "JPEG encoded data",
+		.pixelformat	= V4L2_PIX_FMT_JPEG,
+	}, {
+		.index		= 15,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.description	= "Interleaved data",
+		.pixelformat	= V4L2_PIX_FMT_INTERLEAVED,
+	},
+};
+
+static const struct v4l2_queryctrl fimc_controls[] = {
+	{
+		.id = V4L2_CID_ROTATION,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Roataion",
+		.minimum = 0,
+		.maximum = 270,
+		.step = 90,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_HFLIP,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Horizontal Flip",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_VFLIP,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Vertical Flip",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_PADDR_Y,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Y",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CB,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Cb",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CR,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Cr",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CBCR,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address CbCr",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_CACHEABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Cacheable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+};
+
+#ifndef CONFIG_VIDEO_FIMC_MIPI
+void s3c_csis_start(int csis_id, int lanes, int settle, \
+	int align, int width, int height, int pixel_format) {}
+void s3c_csis_stop(int csis_id) {}
+void s3c_csis_enable_pktdata(int csis_id, bool enable) {}
+#endif
+
+static int fimc_init_camera(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata;
+	struct s3c_platform_camera *cam;
+	int ret = 0, retry_cnt = 0;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+	pdata = to_fimc_plat(ctrl->dev);
+
+	cam = ctrl->cam;
+
+	/* do nothing if already initialized */
+	if (ctrl->cam->initialized)
+		return 0;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (ctrl->power_status == FIMC_POWER_OFF) {
+		pm_runtime_get_sync(&pdev->dev);
+	}
+#endif
+	/*
+	 * WriteBack mode doesn't need to set clock and power,
+	 * but it needs to set source width, height depend on LCD resolution.
+	*/
+	if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
+		ret = s3cfb_direct_ioctl(0, S3CFB_GET_LCD_WIDTH,
+					(unsigned long)&cam->width);
+		if (ret) {
+			fimc_err("fail to get LCD size\n");
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+			pm_runtime_put_sync(&pdev->dev);
+#endif
+			return ret;
+		}
+
+		ret = s3cfb_direct_ioctl(0, S3CFB_GET_LCD_HEIGHT,
+					(unsigned long)&cam->height);
+		if (ret) {
+			fimc_err("fail to get LCD size\n");
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+			pm_runtime_put_sync(&pdev->dev);
+#endif
+			return ret;
+		}
+
+		cam->window.width = cam->width;
+		cam->window.height = cam->height;
+		cam->initialized = 1;
+
+		return ret;
+	}
+
+retry:
+	/* set rate for mclk */
+	if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
+		clk_set_rate(cam->clk, cam->clk_rate);
+		clk_enable(cam->clk);
+		fimc->mclk_status = CAM_MCLK_ON;
+		fimc_info1("clock for camera: %d\n", cam->clk_rate);
+	}
+
+	/* enable camera power if needed */
+	if (cam->cam_power) {
+		ret = cam->cam_power(1);
+		if (unlikely(ret < 0)) {
+			fimc_err("\nfail to power on\n");
+			if (fimc->mclk_status == CAM_MCLK_ON) {
+				clk_disable(ctrl->cam->clk);
+				fimc->mclk_status = CAM_MCLK_OFF;
+			}
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+			pm_runtime_put_sync(&pdev->dev);
+#endif
+			return ret;
+		}
+	}
+
+	/* "0" argument means preview init for s5k4ea */
+	ret = v4l2_subdev_call(cam->sd, core, init, 0);
+
+	/* Retry camera power-up if first i2c fails. */
+	if (unlikely(ret < 0)) {
+		if (cam->cam_power)
+			cam->cam_power(0);
+
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+		if (retry_cnt++ < 3) {
+			msleep(100);
+			fimc_err("Retry power on(%d/3)\n\n", retry_cnt);
+			goto retry;
+		} else {
+			fimc_err("Camera power/init failed!!!!\n\n");
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+			if (ctrl->power_status == FIMC_POWER_ON) {
+				pm_runtime_put_sync(&pdev->dev);
+			}
+#endif
+		}
+	} else {
+		/* Apply things to interface register */
+		fimc_hwset_reset(ctrl);
+		cam->initialized = 1;
+	}
+
+	return ret;
+}
+
+static int fimc_camera_get_jpeg_memsize(struct fimc_control *ctrl)
+{
+	int ret = 0;
+	struct v4l2_control cam_ctrl;
+	cam_ctrl.id = V4L2_CID_CAM_JPEG_MEMSIZE;
+
+	ret = v4l2_subdev_call(ctrl->cam->sd, core, g_ctrl, &cam_ctrl);
+	if (ret < 0) {
+		fimc_err("%s: Subdev doesn't support JEPG encoding.\n", \
+				 __func__);
+		return 0;
+	}
+
+	return cam_ctrl.value;
+}
+
+
+static int fimc_capture_scaler_info(struct fimc_control *ctrl)
+{
+	struct fimc_scaler *sc = &ctrl->sc;
+	struct v4l2_rect *window = &ctrl->cam->window;
+	int tx, ty, sx, sy;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int rot = 0;
+
+	if (!ctrl->cam->use_isp) {
+		sx = window->width;
+		sy = window->height;
+	} else {
+		sx = ctrl->is.fmt.width;
+		sy = ctrl->is.fmt.height;
+	}
+
+	sc->real_width = sx;
+	sc->real_height = sy;
+
+	rot = fimc_mapping_rot_flip(ctrl->cap->rotate, ctrl->cap->flip);
+
+	if (rot & FIMC_ROT) {
+		tx = ctrl->cap->fmt.height;
+		ty = ctrl->cap->fmt.width;
+	} else {
+		tx = ctrl->cap->fmt.width;
+		ty = ctrl->cap->fmt.height;
+	}
+
+	fimc_dbg("%s: CamOut (%d, %d), TargetOut (%d, %d)\n",
+			__func__, sx, sy, tx, ty);
+
+	if (sx <= 0 || sy <= 0) {
+		fimc_err("%s: invalid source size\n", __func__);
+		return -EINVAL;
+	}
+
+	if (tx <= 0 || ty <= 0) {
+		fimc_err("%s: invalid target size\n", __func__);
+		return -EINVAL;
+	}
+
+	fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
+	fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
+
+	if (sx == sy) {
+		if (sx*10/tx >= 15 && sx*10/tx < 20) {
+			sc->pre_hratio = 2;
+			sc->hfactor = 1;
+		}
+		if (sy*10/ty >= 15 && sy*10/ty < 20) {
+			sc->pre_vratio = 2;
+			sc->vfactor = 1;
+		}
+	}
+
+
+	sc->pre_dst_width = sx / sc->pre_hratio;
+	sc->pre_dst_height = sy / sc->pre_vratio;
+
+	if (pdata->hw_ver >= 0x50) {
+		sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
+	} else {
+		sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
+	}
+
+	sc->scaleup_h = (tx >= sx) ? 1 : 0;
+	sc->scaleup_v = (ty >= sy) ? 1 : 0;
+
+	return 0;
+}
+
+static int fimc_capture_change_scaler_info(struct fimc_control *ctrl)
+{
+	struct fimc_scaler *sc = &ctrl->sc;
+	struct v4l2_rect *window = &ctrl->cam->window;
+	int tx, ty, sx, sy;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int rot = 0;
+
+	if (!ctrl->cam->use_isp) {
+		sx = window->width;
+		sy = window->height;
+	} else {
+		sx = ctrl->is.zoom_in_width;
+		sy = ctrl->is.zoom_in_height;
+	}
+
+	sc->real_width = sx;
+	sc->real_height = sy;
+
+	rot = fimc_mapping_rot_flip(ctrl->cap->rotate, ctrl->cap->flip);
+
+	if (rot & FIMC_ROT) {
+		tx = ctrl->cap->fmt.height;
+		ty = ctrl->cap->fmt.width;
+	} else {
+		tx = ctrl->cap->fmt.width;
+		ty = ctrl->cap->fmt.height;
+	}
+
+	fimc_dbg("%s: CamOut (%d, %d), TargetOut (%d, %d)\n",
+			__func__, sx, sy, tx, ty);
+
+	if (sx <= 0 || sy <= 0) {
+		fimc_err("%s: invalid source size\n", __func__);
+		return -EINVAL;
+	}
+
+	if (tx <= 0 || ty <= 0) {
+		fimc_err("%s: invalid target size\n", __func__);
+		return -EINVAL;
+	}
+
+	fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
+	fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
+
+	sc->pre_dst_width = sx / sc->pre_hratio;
+	sc->pre_dst_height = sy / sc->pre_vratio;
+
+	if (pdata->hw_ver >= 0x50) {
+		sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
+	} else {
+		sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
+	}
+
+	sc->scaleup_h = (tx >= sx) ? 1 : 0;
+	sc->scaleup_v = (ty >= sy) ? 1 : 0;
+
+	return 0;
+}
+
+int fimc_start_zoom_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+
+	fimc_hwset_start_scaler(ctrl);
+
+	fimc_hwset_enable_capture(ctrl, ctrl->sc.bypass);
+	fimc_hwset_disable_frame_end_irq(ctrl);
+
+	return 0;
+}
+
+int fimc_stop_zoom_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No cappure format.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cap->lastirq) {
+		fimc_hwset_enable_lastirq(ctrl);
+		fimc_hwset_disable_capture(ctrl);
+		fimc_hwset_disable_lastirq(ctrl);
+	} else {
+		fimc_hwset_disable_capture(ctrl);
+		fimc_hwset_enable_frame_end_irq(ctrl);
+	}
+
+	fimc_hwset_stop_scaler(ctrl);
+	return 0;
+}
+
+static int fimc_add_inqueue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *tmp_buf;
+	struct list_head *count;
+
+	/* PINGPONG_2ADDR_MODE Only */
+	list_for_each(count, &cap->inq) {
+		tmp_buf = list_entry(count, struct fimc_buf_set, list);
+		/* skip list_add_tail if already buffer is in cap->inq list*/
+		if (tmp_buf->id == i)
+			return 0;
+	}
+	list_add_tail(&cap->bufs[i].list, &cap->inq);
+
+	return 0;
+}
+
+static int fimc_add_outqueue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *buf;
+	unsigned int mask = 0x2;
+
+	/* PINGPONG_2ADDR_MODE Only */
+	/* pair_buf_index stands for pair index of i. (0<->2) (1<->3) */
+	int pair_buf_index = (i^mask);
+
+	/* FIMC have 4 h/w registers */
+	if (i < 0 || i >= FIMC_PHYBUFS) {
+		fimc_err("%s: invalid queue index : %d\n", __func__, i);
+		return -ENOENT;
+	}
+
+	if (list_empty(&cap->inq))
+		return -ENOENT;
+
+	buf = list_first_entry(&cap->inq, struct fimc_buf_set, list);
+
+	/* pair index buffer should be allocated first */
+	cap->outq[pair_buf_index] = buf->id;
+	fimc_hwset_output_address(ctrl, buf, pair_buf_index);
+
+	cap->outq[i] = buf->id;
+	fimc_hwset_output_address(ctrl, buf, i);
+
+	list_del(&buf->list);
+
+	return 0;
+}
+
+int fimc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	/* WriteBack doesn't have subdev_call */
+
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+		return 0;
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = v4l2_subdev_call(ctrl->cam->sd, video, g_parm, a);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret = 0;
+	int new_fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	fimc_info2("%s fimc%d, %d\n", __func__, ctrl->id, new_fps);
+
+	/* WriteBack doesn't have subdev_call */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+		return 0;
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	if (ctrl->cam->sd && fimc_cam_use)
+		ret = v4l2_subdev_call(ctrl->cam->sd, video, s_parm, a);
+	else if (ctrl->is.sd && fimc_cam_use)
+		ret = v4l2_subdev_call(ctrl->is.sd, video, s_parm, a);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+/* Enumerate controls */
+int fimc_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *qc)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i, ret;
+
+	fimc_dbg("%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(fimc_controls); i++) {
+		if (fimc_controls[i].id == qc->id) {
+			memcpy(qc, &fimc_controls[i], sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = v4l2_subdev_call(ctrl->cam->sd, core, queryctrl, qc);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+/* Menu control items */
+int fimc_querymenu(struct file *file, void *fh, struct v4l2_querymenu *qm)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = v4l2_subdev_call(ctrl->cam->sd, core, querymenu, qm);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_enum_input(struct file *file, void *fh, struct v4l2_input *inp)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+
+	fimc_dbg("%s: index %d\n", __func__, inp->index);
+
+	if (inp->index >= FIMC_MAXCAMS) {
+		fimc_err("%s: invalid input index, received = %d\n",
+				__func__, inp->index);
+		return -EINVAL;
+	}
+
+	if (!fimc->camera_isvalid[inp->index])
+		return -EINVAL;
+	mutex_lock(&ctrl->v4l2_lock);
+
+	if (fimc->camera[inp->index]->use_isp && !(fimc->camera[inp->index]->info))
+		strcpy(inp->name, "ISP Camera");
+	else
+		strcpy(inp->name, fimc->camera[inp->index]->info->type);
+
+	inp->type = V4L2_INPUT_TYPE_CAMERA;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_input(struct file *file, void *fh, unsigned int *i)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_global *fimc = get_fimc_dev();
+
+	/* In case of isueing g_input before s_input */
+	if (!ctrl->cam) {
+		fimc_err("no camera device selected yet. do VIDIOC_S_INPUT first\n");
+		return -ENODEV;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	*i = (unsigned int) fimc->active_camera;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	fimc_dbg("%s: index %d\n", __func__, *i);
+
+	return 0;
+}
+
+int fimc_release_subdev(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct i2c_client *client;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret;
+
+	if (ctrl->cam->sd && fimc_cam_use) {
+		fimc_dbg("%s called\n", __func__);
+
+		/* WriteBack doesn't need clock setting */
+		if ((ctrl->cam->id == CAMERA_WB) ||
+			(ctrl->cam->id == CAMERA_WB_B)) {
+			ctrl->cam->initialized = 0;
+			ctrl->cam = NULL;
+			fimc->active_camera = -1;
+			return 0;
+		}
+
+		client = v4l2_get_subdevdata(ctrl->cam->sd);
+		i2c_unregister_device(client);
+		ctrl->cam->sd = NULL;
+		if (ctrl->cam->cam_power)
+			ctrl->cam->cam_power(0);
+
+		/* shutdown the MCLK */
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+
+		ctrl->cam->initialized = 0;
+		ctrl->cam = NULL;
+		fimc->active_camera = -1;
+	} else if (ctrl->cam->sd) {
+		ctrl->cam->initialized = 0;
+		ctrl->cam = NULL;
+		fimc->active_camera = -1;
+	}
+
+	if (ctrl->flite_sd && fimc_cam_use) {
+		ret = v4l2_subdev_call(ctrl->flite_sd, core, s_power, 0);
+		if (ret)
+			fimc_err("s_power failed: %d", ret);
+
+		ctrl->flite_sd = NULL;
+	}
+
+	return 0;
+}
+
+static int fimc_configure_subdev(struct fimc_control *ctrl)
+{
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info *i2c_info;
+	struct i2c_client *client;
+	struct v4l2_subdev *sd;
+	unsigned short addr;
+	char *name;
+	int ret = 0;
+
+	i2c_adap = i2c_get_adapter(ctrl->cam->get_i2c_busnum());
+	if (!i2c_adap) {
+		fimc_err("subdev i2c_adapter missing-skip registration\n");
+		return -ENODEV;
+	}
+
+	i2c_info = ctrl->cam->info;
+	if (!i2c_info) {
+		fimc_err("%s: subdev i2c board info missing\n", __func__);
+		return -ENODEV;
+	}
+
+	name = i2c_info->type;
+	if (!name) {
+		fimc_err("subdev i2c driver name missing-skip registration\n");
+		return -ENODEV;
+	}
+
+	addr = i2c_info->addr;
+	if (!addr) {
+		fimc_err("subdev i2c address missing-skip registration\n");
+		return -ENODEV;
+	}
+	/*
+	 * NOTE: first time subdev being registered,
+	 * s_config is called and try to initialize subdev device
+	 * but in this point, we are not giving MCLK and power to subdev
+	 * so nothing happens but pass platform data through
+	 */
+	sd = v4l2_i2c_new_subdev_board(&ctrl->v4l2_dev, i2c_adap,
+			i2c_info, &addr);
+	if (!sd) {
+		fimc_err("%s: v4l2 subdev board registering failed\n",
+				__func__);
+	}
+	/* Assign subdev to proper camera device pointer */
+	ctrl->cam->sd = sd;
+
+	if (!ctrl->cam->initialized) {
+		ret = fimc_init_camera(ctrl);
+		if (ret < 0) {
+			fimc_err("%s: fail to initialize subdev\n", __func__);
+			client = v4l2_get_subdevdata(sd);
+			i2c_unregister_device(client);
+			ctrl->cam->sd = NULL;
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int flite_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd_list = p;
+	struct v4l2_subdev *sd = NULL;
+
+	sd = dev_get_drvdata(dev);
+	if (sd) {
+		struct platform_device *pdev = v4l2_get_subdev_hostdata(sd);
+		*(sd_list + pdev->id) = sd;
+	}
+
+	return 0; /* non-zero value stops iteration */
+}
+
+static struct v4l2_subdev *exynos_flite_get_subdev(int id)
+{
+	const char *module_name = "exynos-fimc-lite";
+	struct device_driver *drv;
+	struct v4l2_subdev *sd[FLITE_MAX_NUM] = {NULL,};
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv)  {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &sd[0],
+				     flite_register_callback);
+	put_driver(drv);
+
+	return ret ? NULL : sd[id];
+}
+
+int fimc_subdev_attatch(struct fimc_control *ctrl)
+{
+	int ret = 0;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	ctrl->flite_sd = exynos_flite_get_subdev(ctrl->cam->flite_id);
+	if (IS_ERR_OR_NULL(ctrl->flite_sd)) {
+			ctrl->flite_sd = NULL;
+			return PTR_ERR(ctrl->flite_sd);
+	} else {
+		if (fimc_cam_use) {
+			ret = v4l2_subdev_call(ctrl->flite_sd, core, s_power, 1);
+			if (ret)
+				fimc_err("s_power failed: %d", ret);
+		}
+
+	}
+
+	return 0;
+}
+
+static int fimc_is_register_callback(struct device *dev, void *p)
+{
+	struct v4l2_subdev **sd = p;
+
+	*sd = dev_get_drvdata(dev);
+
+	if (!*sd)
+		return -EINVAL;
+
+	return 0; /* non-zero value stops iteration */
+}
+
+int fimc_is_release_subdev(struct fimc_control *ctrl)
+{
+	int ret;
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	if (ctrl->is.sd && ctrl->cam && fimc_cam_use) {
+		if (ctrl->cam->cam_power)
+			ctrl->cam->cam_power(0);
+		/* shutdown the MCLK */
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+
+		ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 0);
+		if (ret < 0) {
+			fimc_dbg("FIMC-IS init failed");
+			return -ENODEV;
+		}
+
+		v4l2_device_unregister_subdev(ctrl->is.sd);
+		ctrl->is.sd = NULL;
+		ctrl->cam->initialized = 0;
+		ctrl->cam = NULL;
+		fimc->active_camera = -1;
+	} else if (ctrl->is.sd && ctrl->cam) {
+		ctrl->is.sd = NULL;
+		ctrl->cam->initialized = 0;
+		ctrl->cam = NULL;
+		fimc->active_camera = -1;
+	}
+
+	return 0;
+}
+
+static struct v4l2_subdev *fimc_is_get_subdev(int id)
+{
+	const char *module_name = "exynos4-fimc-is";
+	struct device_driver *drv;
+	struct v4l2_subdev *sd = NULL;
+	int ret;
+
+	drv = driver_find(module_name, &platform_bus_type);
+	if (!drv)  {
+		request_module(module_name);
+		drv = driver_find(module_name, &platform_bus_type);
+	}
+	if (!drv)
+		return ERR_PTR(-ENODEV);
+
+	ret = driver_for_each_device(drv, NULL, &sd,
+				     fimc_is_register_callback);
+	put_driver(drv);
+	return ret ? NULL : sd;
+}
+
+static int fimc_is_init_cam(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_camera *cam;
+	int ret = 0;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+
+	cam = ctrl->cam;
+	/* Do noting if already initialized */
+	if (ctrl->cam->initialized)
+		return 0;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (ctrl->power_status == FIMC_POWER_OFF)
+		pm_runtime_get_sync(&pdev->dev);
+#endif
+
+	/* set rate for mclk */
+	if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
+		clk_set_rate(cam->clk, cam->clk_rate);
+		clk_enable(cam->clk);
+		fimc->mclk_status = CAM_MCLK_ON;
+		fimc_info1("clock for camera (FIMC-IS): %d\n", cam->clk_rate);
+	}
+
+	/* enable camera power if needed */
+	if (cam->cam_power) {
+		ret = cam->cam_power(1);
+		if (unlikely(ret < 0))
+			fimc_err("\nfail to power on\n");
+	}
+
+
+	/* Retry camera power-up if first i2c fails. */
+	if (unlikely(ret < 0)) {
+		if (cam->cam_power)
+			cam->cam_power(0);
+
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+
+		fimc_err("Camera power/init failed!!!!\n\n");
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_ON)
+			pm_runtime_put_sync(&pdev->dev);
+#endif
+	} else {
+		/* Apply things to interface register */
+		fimc_hwset_reset(ctrl);
+		cam->initialized = 1;
+	}
+
+	return ret;
+}
+
+int fimc_s_input(struct file *file, void *fh, unsigned int i)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret = 0;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+
+	fimc_dbg("%s: index %d\n", __func__, i);
+
+	if (i >= FIMC_MAXCAMS) {
+		fimc_err("%s: invalid input index\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!fimc->camera_isvalid[i])
+		return -EINVAL;
+
+	if (fimc->camera[i]->sd && fimc_cam_use) {
+		fimc_err("%s: Camera already in use.\n", __func__);
+		return -EBUSY;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/* If ctrl->cam is not NULL, there is one subdev already registered.
+	 * We need to unregister that subdev first. */
+	if (i != fimc->active_camera) {
+		fimc_info1("\n\nfimc_s_input activating subdev\n");
+		if (ctrl->cam && (ctrl->cam->sd || ctrl->flite_sd))
+			fimc_release_subdev(ctrl);
+		else if (ctrl->is.sd)
+			fimc_is_release_subdev(ctrl);
+		ctrl->cam = fimc->camera[i];
+
+		if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id !=
+			CAMERA_WB_B) && (!ctrl->cam->use_isp) && fimc_cam_use) {
+			ret = fimc_configure_subdev(ctrl);
+			if (ret < 0) {
+#ifdef CONFIG_MACH_GC1
+				if (ret == -ENOSYS) {
+					/* return no error If firmware is bad.
+					Because F/W update app should access the sensor through HAL instance */
+					fimc_err("%s: please update the F/W\n", __func__);
+				} else {
+					ctrl->cam = NULL;
+					mutex_unlock(&ctrl->v4l2_lock);
+					fimc_err("%s: Could not register camera" \
+						" sensor with V4L2.\n", __func__);
+					return -ENODEV;
+				}
+#else
+				ctrl->cam = NULL;
+#ifdef CONFIG_MACH_P4NOTE
+				fimc_release_subdev(ctrl);
+#endif /* CONFIG_MACH_P4NOTE */
+				mutex_unlock(&ctrl->v4l2_lock);
+				fimc_err("%s: Could not register camera" \
+					" sensor with V4L2.\n", __func__);
+				return -ENODEV;
+#endif
+			}
+		}
+		fimc->active_camera = i;
+		fimc_info2("fimc_s_input activated subdev = %d\n", i);
+	}
+
+	if (!fimc_cam_use) {
+		if (i == fimc->active_camera) {
+			ctrl->cam = fimc->camera[i];
+			fimc_info2("fimc_s_input activating subdev FIMC%d\n",
+							ctrl->id);
+		} else {
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -EINVAL;
+		}
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+#ifdef CONFIG_DRM_EXYNOS_FIMD_WB
+		if ((ctrl->cam->id != CAMERA_WB) &&
+		(ctrl->cam->id !=	CAMERA_WB_B) &&
+		(ctrl->power_status == FIMC_POWER_OFF)) {
+#else
+		if (ctrl->power_status == FIMC_POWER_OFF) {
+#endif
+			pm_runtime_get_sync(&pdev->dev);
+		}
+		fimc_hwset_reset(ctrl);
+#endif
+	}
+
+	if (ctrl->cam->use_isp) {
+	    /* fimc-lite attatch */
+	    ret = fimc_subdev_attatch(ctrl);
+	    if (ret) {
+		    fimc_err("subdev_attatch failed\n");
+		    mutex_unlock(&ctrl->v4l2_lock);
+		    return -ENODEV;
+	    }
+	    /* fimc-is attatch */
+	    ctrl->is.sd = fimc_is_get_subdev(i);
+	    if (IS_ERR_OR_NULL(ctrl->is.sd)) {
+		fimc_err("fimc-is subdev_attatch failed\n");
+		mutex_unlock(&ctrl->v4l2_lock);
+		return -ENODEV;
+	    }
+
+	    ctrl->is.fmt.width = ctrl->cam->width;
+	    ctrl->is.fmt.height = ctrl->cam->height;
+	    ctrl->is.frame_count = 0;
+	    if (fimc_cam_use) {
+		ret = fimc_is_init_cam(ctrl);
+		if (ret < 0) {
+			fimc_dbg("FIMC-IS init clock failed");
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -ENODEV;
+		}
+		ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 1);
+		if (ret < 0) {
+			fimc_dbg("FIMC-IS init failed");
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -ENODEV;
+		}
+		ret = v4l2_subdev_call(ctrl->is.sd, core, load_fw);
+		if (ret < 0) {
+			fimc_dbg("FIMC-IS init failed");
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -ENODEV;
+		}
+		ret = v4l2_subdev_call(ctrl->is.sd, core, init, ctrl->cam->sensor_index);
+		if (ret < 0) {
+			fimc_dbg("FIMC-IS init failed");
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -ENODEV;
+		}
+	    }
+	}
+
+
+	/*
+	 * The first time alloc for struct cap_info, and will be
+	 * released at the file close.
+	 * Anyone has better idea to do this?
+	*/
+	if (!cap) {
+		cap = kzalloc(sizeof(*cap), GFP_KERNEL);
+		if (!cap) {
+			fimc_err("%s: no memory for "
+				"capture device info\n", __func__);
+			return -ENOMEM;
+		}
+
+		/* assign to ctrl */
+		ctrl->cap = cap;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_OFF)
+			pm_runtime_get_sync(&pdev->dev);
+#endif
+	} else {
+		memset(cap, 0, sizeof(*cap));
+	}
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_enum_fmt_vid_capture(struct file *file, void *fh,
+					struct v4l2_fmtdesc *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i = f->index;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (i >= ARRAY_SIZE(capture_fmts)) {
+		fimc_err("%s: There is no support format index %d\n", __func__, i);
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(f, 0, sizeof(*f));
+	memcpy(f, &capture_fmts[i], sizeof(*f));
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cap) {
+		fimc_err("%s: no capture device info\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(&f->fmt.pix, 0, sizeof(f->fmt.pix));
+	memcpy(&f->fmt.pix, &ctrl->cap->fmt, sizeof(f->fmt.pix));
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+/*
+ * Check for whether the requested format
+ * can be streamed out from FIMC
+ * depends on FIMC node
+ */
+static int fimc_fmt_avail(struct fimc_control *ctrl,
+		struct v4l2_pix_format *f)
+{
+	int i;
+
+	/*
+	 * TODO: check for which FIMC is used.
+	 * Available fmt should be varied for each FIMC
+	 */
+
+	for (i = 0; i < ARRAY_SIZE(capture_fmts); i++) {
+		if (capture_fmts[i].pixelformat == f->pixelformat)
+			return 0;
+	}
+
+	fimc_info1("Not supported pixelformat requested\n");
+
+	return -1;
+}
+
+/*
+ * figures out the depth of requested format
+ */
+static int fimc_fmt_depth(struct fimc_control *ctrl, struct v4l2_pix_format *f)
+{
+	int err, depth = 0;
+
+	/* First check for available format or not */
+	err = fimc_fmt_avail(ctrl, f);
+	if (err < 0)
+		return -1;
+
+	/* handles only supported pixelformats */
+	switch (f->pixelformat) {
+	case V4L2_PIX_FMT_RGB32:
+		depth = 32;
+		fimc_dbg("32bpp\n");
+		break;
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_YUYV:
+	case V4L2_PIX_FMT_UYVY:
+	case V4L2_PIX_FMT_VYUY:
+	case V4L2_PIX_FMT_YVYU:
+	case V4L2_PIX_FMT_YUV422P:
+	case V4L2_PIX_FMT_NV16:
+	case V4L2_PIX_FMT_NV61:
+		depth = 16;
+		fimc_dbg("16bpp\n");
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV12T:
+	case V4L2_PIX_FMT_NV21:
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		depth = 12;
+		fimc_dbg("12bpp\n");
+		break;
+	case V4L2_PIX_FMT_JPEG:
+	case V4L2_PIX_FMT_INTERLEAVED:
+		depth = -1;
+		fimc_dbg("Compressed format.\n");
+		break;
+	default:
+		fimc_dbg("why am I here?\n");
+		break;
+	}
+
+	return depth;
+}
+
+int fimc_s_fmt_vid_private(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	struct v4l2_mbus_framefmt *mbus_fmt;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+	if (ctrl->cam->sd) {
+		struct v4l2_pix_format *pix = &f->fmt.pix;
+		int depth;
+
+		fimc_info1("%s %d:\n", __func__, __LINE__);
+
+		mbus_fmt = &ctrl->cap->mbus_fmt;
+		mbus_fmt->width = pix->width;
+		mbus_fmt->height = pix->height;
+#ifdef CONFIG_MACH_P4NOTE
+/* Unfortuntely, we have to use pix->field (not pix->priv) since
+ * pix.field is already used in the below else condtion statement
+ * (in case that sub-devices are not registered)
+ */
+		mbus_fmt->field = pix->field;
+#endif
+#if (defined(CONFIG_MACH_S2PLUS) || defined(CONFIG_MACH_GC1))
+		mbus_fmt->field = pix->priv;
+#endif
+		printk(KERN_INFO "%s mbus_fmt->width = %d, height = %d,\n",
+			__func__,mbus_fmt->width ,mbus_fmt->height);
+
+		depth = fimc_fmt_depth(ctrl, pix);
+		if (depth == 0) {
+			fimc_err("%s: Invalid pixel format\n", __func__);
+			return -EINVAL;
+		} else if (depth < 0) {	/* JPEG  */
+			mbus_fmt->code = V4L2_MBUS_FMT_JPEG_1X8;
+			mbus_fmt->colorspace = V4L2_COLORSPACE_JPEG;
+		} else {
+			mbus_fmt->code = V4L2_MBUS_FMT_VYUY8_2X8;
+		}
+
+		if (fimc_cam_use) {
+			ret = v4l2_subdev_call(ctrl->cam->sd, video,
+					       s_mbus_fmt, mbus_fmt);
+			if (ret) {
+				fimc_err("%s: fail to s_mbus_fmt\n", __func__);
+				return ret;
+			}
+		}
+
+		return 0;
+	} else {
+		mbus_fmt = kzalloc(sizeof(*mbus_fmt), GFP_KERNEL);
+		if (!mbus_fmt) {
+			fimc_err("%s: no memory for "
+				"mbus_fmt\n", __func__);
+			return -ENOMEM;
+		}
+		ctrl->is.fmt.width = f->fmt.pix.width;
+		ctrl->is.fmt.height = f->fmt.pix.height;
+		ctrl->is.fmt.pixelformat = f->fmt.pix.pixelformat;
+
+		mbus_fmt->width = f->fmt.pix.width;
+		mbus_fmt->height = f->fmt.pix.height;
+		mbus_fmt->code = V4L2_MBUS_FMT_YUYV8_2X8; /*dummy*/
+		mbus_fmt->field = f->fmt.pix.field;
+		mbus_fmt->colorspace = V4L2_COLORSPACE_SRGB;
+
+		printk(KERN_INFO "%s mbus_fmt->width = %d, height = %d, \n",
+			__func__,mbus_fmt->width ,mbus_fmt->height);
+		if (fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->is.sd, video,
+					s_mbus_fmt, mbus_fmt);
+		kfree(mbus_fmt);
+		return ret;
+	}
+
+	return -EINVAL;
+}
+
+int fimc_s_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	int ret = 0;
+	int depth;
+	struct v4l2_control is_ctrl;
+
+	is_ctrl.id = 0;
+	is_ctrl.value = 0;
+
+	printk(KERN_INFO "%s\n", __func__);
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No capture structure."  \
+			"you have to call s_input first.\n", __func__);
+		return -ENODEV;
+	}
+
+	/* rotaton, flip, dtp_mode, movie_mode and vt_mode,
+	 * sensor_output_width,height should be maintained.(by TN) */
+	memset(cap, 0, sizeof(*cap) - sizeof(u32) * 7);
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(&cap->fmt, 0, sizeof(cap->fmt));
+	memcpy(&cap->fmt, &f->fmt.pix, sizeof(cap->fmt));
+
+	/*
+	 * Note that expecting format only can be with
+	 * available output format from FIMC
+	 * Following items should be handled in driver
+	 * bytesperline = width * depth / 8
+	 * sizeimage = bytesperline * height
+	 */
+	/* This function may return 0 or -1 in case of error,
+	 * hence need to check here.
+	 */
+
+	depth = fimc_fmt_depth(ctrl, &cap->fmt);
+	if (depth == 0) {
+		mutex_unlock(&ctrl->v4l2_lock);
+		fimc_err("%s: Invalid pixel format\n", __func__);
+		return -EINVAL;
+	} else if (depth < 0) {
+		/*
+		 * When the pixelformat is JPEG,
+		 * the application is requesting for data
+		 * in JPEG compressed format
+		*/
+		cap->fmt.colorspace = V4L2_COLORSPACE_JPEG;
+	} else {
+		cap->fmt.bytesperline = (cap->fmt.width * depth) >> 3;
+		cap->fmt.sizeimage = (cap->fmt.bytesperline * cap->fmt.height);
+	}
+
+
+	if (cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG ||
+		cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED) {
+		ctrl->sc.bypass = 1;
+		cap->lastirq = 0;
+		fimc_info1("fimc_s_fmt_vid_capture V4L2_COLORSPACE_JPEG or INTERLEAVED\n");
+	} else {
+#ifdef CONFIG_MACH_GC1
+	/*
+	 Fimc scaler input Hsize is restricted to 4224 pixels.
+	 So, GC1 has to bypass fimc scaler to use more than 12M YUV.
+	 */
+		ctrl->sc.bypass = 1;
+#else
+		ctrl->sc.bypass = 0;
+#endif
+		cap->lastirq = 0;
+	}
+
+	printk(KERN_INFO "fimc%d s_fmt width = %d, height = %d\n", ctrl->id, \
+				cap->fmt.width, cap->fmt.height);
+
+	/* WriteBack doesn't have subdev_call */
+	if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B) {
+		mutex_unlock(&ctrl->v4l2_lock);
+		return 0;
+	}
+
+	if (ctrl->is.sd && fimc_cam_use) {
+		ctrl->is.mbus_fmt.code = V4L2_MBUS_FMT_SGRBG10_1X10;
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_WIDTH;
+		is_ctrl.value = 0;
+		v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+		ctrl->is.fmt.width = ctrl->is.mbus_fmt.width = is_ctrl.value;
+
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_HEIGHT;
+		is_ctrl.value = 0;
+		v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+		ctrl->is.fmt.height = ctrl->is.mbus_fmt.height = is_ctrl.value;
+		/* default offset values */
+		ctrl->is.offset_x = 16;
+		ctrl->is.offset_y = 12;
+	}
+
+	fimc_hwset_reset(ctrl);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+	printk(KERN_INFO "%s -- FIMC%d\n", __func__, ctrl->id);
+
+	return ret;
+}
+
+int fimc_try_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	/* Not implement */
+	return -ENOTTY;
+}
+
+static int fimc_alloc_buffers(struct fimc_control *ctrl,
+			int plane, int size, int align, int bpp, int use_paddingbuf, int pad_size)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	int i, j;
+	int plane_length[4] = {0, };
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	int alloc_size, err;
+	struct cma_info mem_info;
+#endif
+
+	switch (plane) {
+	case 1:
+		if (align) {
+		plane_length[0] = PAGE_ALIGN((size*bpp) >> 3);
+		plane_length[1] = 0;
+		plane_length[2] = 0;
+		} else {
+			plane_length[0] = (size*bpp) >> 3;
+			plane_length[1] = 0;
+			plane_length[2] = 0;
+		}
+		break;
+		/* In case of 2, only NV12 and NV12T is supported. */
+	case 2:
+		if (align) {
+			plane_length[0] = PAGE_ALIGN((size*8) >> 3);
+			plane_length[1] = PAGE_ALIGN((size*(bpp-8)) >> 3);
+			plane_length[2] = 0;
+			fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
+					, plane_length[0], plane_length[1]);
+		} else {
+			plane_length[0] = ((size*8) >> 3);
+			plane_length[1] = ((size*(bpp-8)) >> 3);
+			plane_length[2] = 0;
+			fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
+					, plane_length[0], plane_length[1]);
+		}
+
+		break;
+		/* In case of 3
+		 * YUV422 : 8 / 4 / 4 (bits)
+		 * YUV420 : 8 / 2 / 2 (bits)
+	 * 3rd plane have to consider page align for mmap */
+	case 3:
+		if (align) {
+			plane_length[0] = (size*8) >> 3;
+			plane_length[1] = (size*((bpp-8)/2)) >> 3;
+			plane_length[2] = PAGE_ALIGN((size*bpp)>>3) - plane_length[0]
+				- plane_length[1];
+		} else {
+			plane_length[0] = (size*8) >> 3;
+			plane_length[1] = (size*((bpp-8)/2)) >> 3;
+			plane_length[2] = ((size*bpp)>>3) - plane_length[0]
+				- plane_length[1];
+		}
+		break;
+	default:
+		fimc_err("impossible!\n");
+		return -ENOMEM;
+	}
+
+	if (use_paddingbuf) {
+		plane_length[plane] = pad_size;
+		cap->pktdata_plane = plane;
+	} else
+		plane_length[plane] = 0;
+
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	if (align) {
+		alloc_size = (ALIGN(plane_length[0], align) +
+				ALIGN(plane_length[1], align)
+				+ ALIGN(plane_length[2], align))
+				* cap->nr_bufs;
+	} else {
+		alloc_size = (plane_length[0] + plane_length[1] +
+				plane_length[2]) * cap->nr_bufs;
+	}
+
+	err = cma_info(&mem_info, ctrl->dev, 0);
+	printk(KERN_DEBUG "%s : [cma_info] start_addr : 0x%x, end_addr	: 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x req_size : 0x%x\n",
+			__func__, mem_info.lower_bound,	mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size, alloc_size);
+
+	if (err || (mem_info.free_size < alloc_size)) {
+		fimc_err("%s: get cma info failed\n", __func__);
+		ctrl->mem.size = 0;
+		ctrl->mem.base = 0;
+		return -ENOMEM;
+	} else {
+		ctrl->mem.size = alloc_size;
+		ctrl->mem.base = (dma_addr_t)cma_alloc
+			(ctrl->dev, ctrl->cma_name, (size_t) alloc_size, align);
+	}
+
+	ctrl->mem.curr = ctrl->mem.base;
+#endif
+	for (i = 0; i < cap->nr_bufs; i++) {
+		for (j = 0; j < plane; j++) {
+			cap->bufs[i].length[j] = plane_length[j];
+			fimc_dma_alloc(ctrl, &cap->bufs[i], j, align);
+
+			if (!cap->bufs[i].base[j])
+				goto err_alloc;
+		}
+		if (use_paddingbuf) {
+			cap->bufs[i].length[plane] = plane_length[plane];
+			fimc_dma_alloc(ctrl, &cap->bufs[i], plane, align);
+
+			cap->bufs[i].vaddr_pktdata = phys_to_virt(cap->bufs[i].base[plane]);
+			/* printk(KERN_INFO "pktdata address = 0x%x, 0x%x\n"
+				,cap->bufs[i].base[1], cap->bufs[i].vaddr_pktdata ); */
+
+			if (!cap->bufs[i].base[plane])
+				goto err_alloc;
+		}
+		cap->bufs[i].state = VIDEOBUF_PREPARED;
+	}
+
+	return 0;
+
+err_alloc:
+	for (i = 0; i < cap->nr_bufs; i++) {
+		for (j = 0; j < plane; j++) {
+			if (cap->bufs[i].base[j])
+				fimc_dma_free(ctrl, &cap->bufs[i], j);
+		}
+		if (use_paddingbuf) {
+			if (cap->bufs[i].base[plane])
+				fimc_dma_free(ctrl, &cap->bufs[i], plane);
+		}
+		memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
+	}
+
+	return -ENOMEM;
+}
+
+static void fimc_free_buffers(struct fimc_control *ctrl)
+{
+	struct fimc_capinfo *cap;
+	int i;
+
+	if (ctrl && ctrl->cap)
+		cap = ctrl->cap;
+	else
+		return;
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
+		cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+	}
+
+	ctrl->mem.curr = ctrl->mem.base;
+}
+
+int fimc_reqbufs_capture_mmap(void *fh, struct v4l2_requestbuffers *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+	int ret = 0, i;
+	int bpp = 0;
+	int size = 0;
+
+	if (!cap) {
+		fimc_err("%s: no capture device info\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/*  A count value of zero frees all buffers */
+	if ((b->count == 0) || (b->count >= FIMC_CAPBUFS)) {
+		/* aborting or finishing any DMA in progress */
+		if (ctrl->status == FIMC_STREAMON)
+			fimc_streamoff_capture(fh);
+		for (i = 0; i < FIMC_CAPBUFS; i++) {
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 2);
+		}
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+		if (ctrl->mem.base) {
+			cma_free(ctrl->mem.base);
+			ctrl->mem.base = 0;
+			ctrl->mem.size = 0;
+		}
+#endif
+
+		mutex_unlock(&ctrl->v4l2_lock);
+		return 0;
+	}
+	/* free previous buffers */
+	if ((cap->nr_bufs >= 0) && (cap->nr_bufs < FIMC_CAPBUFS)) {
+		fimc_info1("%s : remained previous buffer count is %d\n", __func__,
+				cap->nr_bufs);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			fimc_dma_free(ctrl, &cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &cap->bufs[i], 2);
+			fimc_dma_free(ctrl, &cap->bufs[i], 3);
+		}
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+		if (ctrl->mem.base) {
+			cma_free(ctrl->mem.base);
+			ctrl->mem.base = 0;
+			ctrl->mem.size = 0;
+		}
+#endif
+	}
+	fimc_free_buffers(ctrl);
+
+	cap->nr_bufs = b->count;
+	if (pdata->hw_ver >= 0x51) {
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_OFF) {
+			pm_runtime_get_sync(&pdev->dev);
+		}
+#endif
+		fimc_hw_reset_output_buf_sequence(ctrl);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			fimc_hwset_output_buf_sequence(ctrl, i, 1);
+			cap->bufs[i].id = i;
+			cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+
+			/* initialize list */
+			INIT_LIST_HEAD(&cap->bufs[i].list);
+		}
+		fimc_info1("%s: requested %d buffers\n", __func__, b->count);
+		fimc_info1("%s: sequence[%d]\n", __func__,
+				fimc_hwget_output_buf_sequence(ctrl));
+		INIT_LIST_HEAD(&cap->outgoing_q);
+	}
+	if (pdata->hw_ver < 0x51) {
+		INIT_LIST_HEAD(&cap->inq);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			cap->bufs[i].id = i;
+			cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+
+			/* initialize list */
+			INIT_LIST_HEAD(&cap->bufs[i].list);
+		}
+	}
+
+	if (cap->pktdata_enable)
+		cap->pktdata_size = 0x1000;
+
+	bpp = fimc_fmt_depth(ctrl, &cap->fmt);
+
+	switch (cap->fmt.pixelformat) {
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:		/* fall through */
+	case V4L2_PIX_FMT_YVYU:		/* fall through */
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:		/* fall through */
+		fimc_info1("%s : 1plane\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 1,
+			cap->fmt.width * cap->fmt.height, SZ_4K, bpp, cap->pktdata_enable, cap->pktdata_size);
+		break;
+
+	case V4L2_PIX_FMT_NV21:
+		fimc_info1("%s : 2plane for NV21 w %d h %d\n", __func__,
+				cap->fmt.width, cap->fmt.height);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			cap->fmt.width * cap->fmt.height, 0, bpp, cap->pktdata_enable, cap->pktdata_size);
+		break;
+
+	case V4L2_PIX_FMT_NV12:
+		fimc_info1("%s : 2plane for NV12\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			cap->fmt.width * cap->fmt.height, SZ_64K, bpp, cap->pktdata_enable, cap->pktdata_size);
+		break;
+
+	case V4L2_PIX_FMT_NV12T:
+		fimc_info1("%s : 2plane for NV12T\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			ALIGN(cap->fmt.width, 128) * ALIGN(cap->fmt.height, 32),
+			SZ_64K, bpp, cap->pktdata_enable, cap->pktdata_size);
+		break;
+
+	case V4L2_PIX_FMT_YUV422P:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		fimc_info1("%s : 3plane\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 3,
+			cap->fmt.width * cap->fmt.height, 0, bpp, cap->pktdata_enable, cap->pktdata_size);
+		break;
+
+	case V4L2_PIX_FMT_JPEG:
+		fimc_info1("%s : JPEG 1plane\n", __func__);
+		size = fimc_camera_get_jpeg_memsize(ctrl);
+		fimc_info2("%s : JPEG 1plane size = %x\n", __func__, size);
+		ret = fimc_alloc_buffers(ctrl, 1, size, 0, 8, cap->pktdata_enable, cap->pktdata_size);
+		break;
+	case V4L2_PIX_FMT_INTERLEAVED:
+		fimc_info1("%s : Interleaved Format\n", __func__);
+		size = fimc_camera_get_jpeg_memsize(ctrl); /*0xA00000*/
+		fimc_info2("%s : Interleaved size = %x\n", __func__, size);
+		ret = fimc_alloc_buffers(ctrl, 1, size, 0, 8, cap->pktdata_enable, cap->pktdata_size);
+		break;
+	default:
+		break;
+	}
+
+	if (ret) {
+		fimc_err("%s: no memory for capture buffer\n", __func__);
+		mutex_unlock(&ctrl->v4l2_lock);
+		return -ENOMEM;
+	}
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_reqbufs_capture_userptr(void *fh, struct v4l2_requestbuffers *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+	int i;
+
+	if (!cap) {
+		fimc_err("%s: no capture device info\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/*  A count value of zero frees all buffers */
+	if ((b->count == 0) || (b->count >= FIMC_CAPBUFS)) {
+		/* aborting or finishing any DMA in progress */
+		if (ctrl->status == FIMC_STREAMON)
+			fimc_streamoff_capture(fh);
+
+		fimc_free_buffers(ctrl);
+
+		mutex_unlock(&ctrl->v4l2_lock);
+		return 0;
+	}
+
+	/* free previous buffers */
+	if ((cap->nr_bufs >= 0) && (cap->nr_bufs < FIMC_CAPBUFS)) {
+		fimc_info1("%s: prev buf cnt(%d)\n", __func__, cap->nr_bufs);
+		fimc_free_buffers(ctrl);
+	}
+
+	cap->nr_bufs = b->count;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (ctrl->power_status == FIMC_POWER_OFF) {
+		pm_runtime_get_sync(&pdev->dev);
+	}
+#endif
+	fimc_hw_reset_output_buf_sequence(ctrl);
+	for (i = 0; i < cap->nr_bufs; i++) {
+		fimc_hwset_output_buf_sequence(ctrl, i, 1);
+		cap->bufs[i].id = i;
+		cap->bufs[i].state = VIDEOBUF_IDLE;
+
+		/* initialize list */
+		INIT_LIST_HEAD(&cap->bufs[i].list);
+	}
+	fimc_info1("%s: requested %d buffers\n", __func__, b->count);
+	fimc_info1("%s: sequence[%d]\n", __func__,
+			fimc_hwget_output_buf_sequence(ctrl));
+	INIT_LIST_HEAD(&cap->outgoing_q);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_reqbufs_capture(void *fh, struct v4l2_requestbuffers *b)
+{
+	int ret = 0;
+
+	if (b->memory == V4L2_MEMORY_MMAP)
+		ret = fimc_reqbufs_capture_mmap(fh, b);
+	else
+		ret = fimc_reqbufs_capture_userptr(fh, b);
+
+	return ret;
+}
+
+int fimc_querybuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+
+	if (ctrl->status != FIMC_STREAMOFF) {
+		fimc_err("fimc is running\n");
+		return -EBUSY;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	switch (cap->fmt.pixelformat) {
+	case V4L2_PIX_FMT_JPEG:		/* fall through */
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:		/* fall through */
+	case V4L2_PIX_FMT_YVYU:		/* fall through */
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:
+	case V4L2_PIX_FMT_INTERLEAVED:
+		b->length = cap->bufs[b->index].length[0];
+		break;
+
+	case V4L2_PIX_FMT_NV21:
+		b->length = ctrl->cap->bufs[b->index].length[0]
+			+ ctrl->cap->bufs[b->index].length[1];
+		break;
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		b->length = ALIGN(ctrl->cap->bufs[b->index].length[0], SZ_64K)
+			+ ALIGN(ctrl->cap->bufs[b->index].length[1], SZ_64K);
+		break;
+	case V4L2_PIX_FMT_YUV422P:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:
+		b->length = ctrl->cap->bufs[b->index].length[0]
+			+ ctrl->cap->bufs[b->index].length[1]
+			+ ctrl->cap->bufs[b->index].length[2];
+		break;
+
+	default:
+		b->length = cap->bufs[b->index].length[0];
+		break;
+	}
+
+	if (cap->pktdata_enable)
+		b->length += ctrl->cap->bufs[b->index].length[cap->pktdata_plane];
+
+	b->m.offset = b->index * PAGE_SIZE;
+	/* memory field should filled V4L2_MEMORY_MMAP */
+	b->memory = V4L2_MEMORY_MMAP;
+
+	ctrl->cap->bufs[b->index].state = VIDEOBUF_IDLE;
+
+	fimc_dbg("%s: %d bytes with offset: %d\n",
+		__func__, b->length, b->m.offset);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_ctrl_capture(void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = fh;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	switch (c->id) {
+	case V4L2_CID_ROTATION:
+		c->value = ctrl->cap->rotate;
+		break;
+
+	case V4L2_CID_HFLIP:
+		c->value = (ctrl->cap->flip & FIMC_XFLIP) ? 1 : 0;
+		break;
+
+	case V4L2_CID_VFLIP:
+		c->value = (ctrl->cap->flip & FIMC_YFLIP) ? 1 : 0;
+		break;
+
+	case V4L2_CID_CACHEABLE:
+		c->value = ctrl->cap->cacheable;
+		break;
+
+	default:
+		/* get ctrl supported by subdev */
+		/* WriteBack doesn't have subdev_call */
+		if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+			break;
+		if (ctrl->cam->sd)
+			ret = v4l2_subdev_call(ctrl->cam->sd, core, g_ctrl, c);
+		if (ctrl->is.sd)
+			ret = v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, c);
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_s_ctrl_capture(void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam || !ctrl->cap ||
+		((ctrl->cam->id != CAMERA_WB && ctrl->cam->id != CAMERA_WB_B) &&
+		 (!ctrl->cam->sd) && (!ctrl->is.sd))) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	switch (c->id) {
+#ifdef CONFIG_MACH_GC1
+	case V4L2_CID_CAM_UPDATE_FW:
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+
+			mdelay(5);
+		}
+
+		if ((clk_get_rate(ctrl->cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
+			clk_set_rate(ctrl->cam->clk, ctrl->cam->clk_rate);
+			clk_enable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_ON;
+			fimc_info1("clock for camera: %d\n", ctrl->cam->clk_rate);
+
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(1);
+		}
+
+		if (c->value == FW_MODE_UPDATE)
+			ret = v4l2_subdev_call(ctrl->cam->sd, core, load_fw);
+
+		else
+			ret = v4l2_subdev_call(ctrl->cam->sd, core, s_ctrl, c);
+		break;
+#endif
+	case V4L2_CID_CAMERA_RESET:
+		fimc_warn("ESD: reset the camera sensor\n");
+		if (ctrl->cam->initialized) {
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+			ctrl->cam->initialized = 0;
+#ifdef CONFIG_MACH_P4NOTE
+	/* 100ms: increase delay.
+	 * There are cases that sensor doesn't get revived
+	 * inspite of doing power reset.*/
+			msleep(100);
+#else
+			msleep(5);
+#endif
+		}
+		if (ctrl->cam->sd) {
+			fimc_warn("ESD: init external sensor\n");
+			ret = fimc_init_camera(ctrl);
+		}
+		if (ctrl->is.sd && ctrl->cam->use_isp) {
+			fimc_warn("ESD: init FIMC-IS\n");
+			ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 0);
+			if (ret < 0) {
+				fimc_err("ESD : FIMC-IS power off failed");
+				return -EINVAL;
+			}
+			ret = fimc_is_init_cam(ctrl);
+			if (ret < 0) {
+				fimc_err("ESD : FIMC-IS init clock failed");
+				return -EINVAL;
+			}
+			ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 1);
+			if (ret < 0) {
+				fimc_err("ESD : FIMC-IS power on failed");
+				return -EINVAL;
+			}
+			ret = v4l2_subdev_call(ctrl->is.sd, core, load_fw);
+			if (ret < 0) {
+				fimc_dbg("ESD : FIMC-IS load FW failed");
+				return -EINVAL;
+			}
+			ret = v4l2_subdev_call(ctrl->is.sd, core,
+						init, ctrl->cam->sensor_index);
+			if (ret < 0) {
+				fimc_err("ESD : FIMC-IS init failed");
+				return -EINVAL;
+			}
+		}
+		break;
+	case V4L2_CID_ROTATION:
+		ctrl->cap->rotate = c->value;
+		break;
+
+	case V4L2_CID_HFLIP:
+		if (c->value)
+			ctrl->cap->flip |= FIMC_YFLIP;
+		else
+			ctrl->cap->flip &= ~FIMC_YFLIP;
+		break;
+
+	case V4L2_CID_VFLIP:
+		if (c->value)
+			ctrl->cap->flip |= FIMC_XFLIP;
+		else
+			ctrl->cap->flip &= ~FIMC_XFLIP;
+		break;
+
+	case V4L2_CID_PADDR_Y:
+		if (ctrl->cap->bufs[c->value].length[FIMC_ADDR_Y])
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_Y];
+		break;
+
+	case V4L2_CID_PADDR_CB:		/* fall through */
+	case V4L2_CID_PADDR_CBCR:
+		if (ctrl->cap->bufs[c->value].length[FIMC_ADDR_CB])
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_CB];
+		break;
+
+	case V4L2_CID_PADDR_CR:
+		if (ctrl->cap->bufs[c->value].length[FIMC_ADDR_CR])
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_CR];
+		break;
+	/* Implementation as per C100 FIMC driver */
+	case V4L2_CID_STREAM_PAUSE:
+		fimc_hwset_stop_processing(ctrl);
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_APPLY:
+		ctrl->fe.ie_on = c->value ? 1 : 0;
+		ctrl->fe.ie_after_sc = 0;
+		ret = fimc_hwset_image_effect(ctrl);
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_FN:
+		if (c->value < 0 || c->value > FIMC_EFFECT_FIN_SILHOUETTE)
+			return -EINVAL;
+		ctrl->fe.fin = c->value;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_CB:
+		ctrl->fe.pat_cb = c->value & 0xFF;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_CR:
+		ctrl->fe.pat_cr = c->value & 0xFF;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IS_LOAD_FW:
+		if (ctrl->is.sd && fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, c->value);
+		break;
+	case V4L2_CID_IS_RESET:
+		if (ctrl->is.sd && fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->is.sd, core, reset, c->value);
+		break;
+	case V4L2_CID_IS_S_POWER:
+		if (ctrl->is.sd && fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, c->value);
+		break;
+	case V4L2_CID_IS_S_STREAM:
+		if (ctrl->is.sd && fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->is.sd, video, s_stream, c->value);
+		break;
+	case V4L2_CID_CACHEABLE:
+		ctrl->cap->cacheable = c->value;
+		ret = 0;
+		break;
+
+	case V4L2_CID_EMBEDDEDDATA_ENABLE:
+		ctrl->cap->pktdata_enable = c->value;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IS_ZOOM:
+		fimc_is_set_zoom(ctrl, c);
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		ctrl->cap->movie_mode = c->value;
+		if (ctrl->cam->sd && fimc_cam_use)
+			ret = v4l2_subdev_call(ctrl->cam->sd, core, s_ctrl, c);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		ctrl->cap->vt_mode = c->value;
+		if (fimc_cam_use) {
+			if (ctrl->cam->sd)
+				ret = v4l2_subdev_call(ctrl->cam->sd,
+							core, s_ctrl, c);
+			if (ctrl->is.sd && ctrl->cam->use_isp)
+				ret = v4l2_subdev_call(ctrl->is.sd,
+							core, s_ctrl, c);
+		}
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_OUTPUT_SIZE:
+		ctrl->cap->sensor_output_width = (u32)c->value >> 16;
+		ctrl->cap->sensor_output_height = (u32)c->value & 0x0FFFF;
+		printk(KERN_DEBUG "sensor output size: %dx%d\n",
+			ctrl->cap->sensor_output_width,
+			ctrl->cap->sensor_output_height);
+		break;
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	case V4L2_CID_CAMERA_BUSFREQ_LOCK:
+		/* lock bus frequency */
+		dev_lock(ctrl->bus_dev, ctrl->dev, (unsigned long)c->value);
+		break;
+	case V4L2_CID_CAMERA_BUSFREQ_UNLOCK:
+		/* unlock bus frequency */
+		dev_unlock(ctrl->bus_dev, ctrl->dev);
+		break;
+#endif
+
+	case V4L2_CID_IS_CAMERA_FLASH_MODE:
+	case V4L2_CID_CAMERA_SCENE_MODE:
+	default:
+		/* try on subdev */
+		/* WriteBack doesn't have subdev_call */
+
+		if ((ctrl->cam->id == CAMERA_WB) || \
+			 (ctrl->cam->id == CAMERA_WB_B))
+			break;
+		if (fimc_cam_use) {
+			if (ctrl->cam->sd)
+				ret = v4l2_subdev_call(ctrl->cam->sd,
+							core, s_ctrl, c);
+			if (ctrl->is.sd && ctrl->cam->use_isp)
+				ret = v4l2_subdev_call(ctrl->is.sd,
+							core, s_ctrl, c);
+		} else
+			ret = 0;
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_g_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+	mutex_lock(&ctrl->v4l2_lock);
+
+	if (ctrl->cam->sd)
+		/* try on subdev */
+		ret = v4l2_subdev_call(ctrl->cam->sd, core, g_ext_ctrls, c);
+	if (ctrl->is.sd)
+		/* try on subdev */
+		ret = v4l2_subdev_call(ctrl->is.sd, core, g_ext_ctrls, c);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_s_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+	mutex_lock(&ctrl->v4l2_lock);
+
+	if (ctrl->cam->sd)
+		/* try on subdev */
+		ret = v4l2_subdev_call(ctrl->cam->sd, core, s_ext_ctrls, c);
+	else if (ctrl->is.sd)
+		ret = v4l2_subdev_call(ctrl->is.sd, core, s_ext_ctrls, c);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_cropcap_capture(void *fh, struct v4l2_cropcap *a)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam || !ctrl->cam->sd || !ctrl->cap) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	pdata = to_fimc_plat(ctrl->dev);
+	if (!ctrl->cam)
+		ctrl->cam = fimc->camera[pdata->default_cam];
+
+	if (!cap) {
+		cap = kzalloc(sizeof(*cap), GFP_KERNEL);
+		if (!cap) {
+			fimc_err("%s: no memory for "
+				"capture device info\n", __func__);
+			return -ENOMEM;
+		}
+
+		/* assign to ctrl */
+		ctrl->cap = cap;
+	}
+
+	/* crop limitations */
+	cap->cropcap.bounds.left = 0;
+	cap->cropcap.bounds.top = 0;
+	cap->cropcap.bounds.width = ctrl->cam->width;
+	cap->cropcap.bounds.height = ctrl->cam->height;
+
+	/* crop default values */
+	cap->cropcap.defrect.left = 0;
+	cap->cropcap.defrect.top = 0;
+	cap->cropcap.defrect.width = ctrl->cam->width;
+	cap->cropcap.defrect.height = ctrl->cam->height;
+
+	a->bounds = cap->cropcap.bounds;
+	a->defrect = cap->cropcap.defrect;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_crop_capture(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = fh;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	a->c = ctrl->cap->crop;
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_s_crop_capture(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = fh;
+
+	fimc_dbg("%s\n", __func__);
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ctrl->cap->crop = a->c;
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_start_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+
+	fimc_reset_status_reg(ctrl);
+
+	if (!ctrl->sc.bypass)
+		fimc_hwset_start_scaler(ctrl);
+
+	fimc_hwset_enable_capture(ctrl, ctrl->sc.bypass);
+	fimc_hwset_disable_frame_end_irq(ctrl);
+
+	return 0;
+}
+
+int fimc_stop_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No cappure format.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cap->lastirq) {
+		fimc_hwset_enable_lastirq(ctrl);
+		fimc_hwset_disable_capture(ctrl);
+		fimc_hwset_disable_lastirq(ctrl);
+	} else {
+		fimc_hwset_disable_capture(ctrl);
+		fimc_hwset_enable_frame_end_irq(ctrl);
+	}
+
+	fimc_hwset_stop_scaler(ctrl);
+
+	return 0;
+}
+
+static int fimc_check_capture_source(struct fimc_control *ctrl)
+{
+        if(!ctrl->cam)
+                return -ENODEV;
+
+        if (ctrl->cam->sd || ctrl->is.sd || !ctrl->flite_sd)
+                return 0;
+
+        if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B)
+                return 0;
+
+        return -ENODEV;
+}
+
+static int is_scale_up(struct fimc_control *ctrl)
+{
+	struct v4l2_mbus_framefmt *mbus_fmt = &ctrl->cap->mbus_fmt;
+	struct v4l2_pix_format *pix = &ctrl->cap->fmt;
+
+	if (!mbus_fmt->width) {
+		fimc_err("%s: sensor resolution isn't selected.\n", __func__);
+		return -EINVAL;
+	}
+
+	if (ctrl->cap->rotate == 90 || ctrl->cap->rotate == 270) {
+		if (pix->width > mbus_fmt->height ||
+			pix->height > mbus_fmt->width) {
+			fimc_err("%s: ScaleUp isn't supported.\n", __func__);
+			return -EINVAL;
+		}
+	} else {
+		if (pix->width > mbus_fmt->width ||
+			pix->height > mbus_fmt->height) {
+			fimc_err("%s: ScaleUp isn't supported.\n", __func__);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+int fimc_streamon_capture(void *fh)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct v4l2_frmsizeenum cam_frmsize;
+	struct v4l2_control is_ctrl;
+	void __iomem *qos_regs;
+
+	int rot = 0, i;
+	int ret = 0;
+	struct s3c_platform_camera *cam = NULL;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	printk(KERN_INFO "%s++ fimc%d\n", __func__, ctrl->id);
+	cam_frmsize.discrete.width = 0;
+	cam_frmsize.discrete.height = 0;
+	is_ctrl.id = 0;
+	is_ctrl.value = 0;
+
+	if (!ctrl->cam) {
+		fimc_err("%s: ctrl->cam is null\n", __func__);
+		return -EINVAL;
+	} else {
+		cam = ctrl->cam;
+	}
+
+        if (fimc_check_capture_source(ctrl)) {
+                fimc_err("%s: No capture device.\n", __func__);
+                return -ENODEV;
+        }
+
+	if (cam->sd) {
+		if (is_scale_up(ctrl))
+			return -EINVAL;
+	}
+
+	if (pdata->hw_ver < 0x51)
+		fimc_hw_reset_camera(ctrl);
+#if (!defined(CONFIG_EXYNOS_DEV_PD) && !defined(CONFIG_PM_RUNTIME))
+	ctrl->status = FIMC_READY_ON;
+#endif
+	cap->irq = 0;
+
+	fimc_hwset_enable_irq(ctrl, 0, 1);
+
+	if ((cam->id != CAMERA_WB) && (cam->id != CAMERA_WB_B)) {
+		if (fimc_cam_use && cam->sd) {
+			ret = v4l2_subdev_call(cam->sd, video, enum_framesizes,
+					&cam_frmsize);
+			if (ret < 0) {
+				dev_err(ctrl->dev, "%s: enum_framesizes failed\n",
+						__func__);
+				if (ret != -ENOIOCTLCMD)
+					return ret;
+			} else {
+				if (cam_frmsize.discrete.width > 0
+					&& cam_frmsize.discrete.height > 0) {
+					cam->window.left = 0;
+					cam->window.top = 0;
+					cam->width = cam->window.width
+						= cam_frmsize.discrete.width;
+					cam->height
+						= cam->window.height
+						= cam_frmsize.discrete.height;
+					printk(KERN_INFO "%s cam real size width = %d,"
+						"height = %d\n",__func__,  ctrl->cam->width,
+						ctrl->cam->height);
+				}
+			}
+
+#ifdef CONFIG_MACH_P4NOTE
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+			v4l2_subdev_call(cam->sd, video, s_stream,
+				STREAM_MODE_WAIT_OFF);
+#endif /* CONFIG_VIDEO_IMPROVE_STREAMOFF */
+#else /* !CONFIG_MACH_P4NOTE */
+			if (cap->fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+				ret = v4l2_subdev_call(cam->sd, video, s_stream, 1);
+				if (ret < 0) {
+					dev_err(ctrl->dev, "%s: s_stream failed\n",
+							__func__);
+					return ret;
+				}
+			}
+#endif
+			if (cam->type == CAM_TYPE_MIPI) {
+				if (cam->id == CAMERA_CSI_C) {
+					s3c_csis_enable_pktdata(CSI_CH_0, cap->pktdata_enable);
+					s3c_csis_start(CSI_CH_0, cam->mipi_lanes,
+					cam->mipi_settle, cam->mipi_align,
+					cam->width, cam->height,
+					cap->fmt.pixelformat);
+				} else {
+					s3c_csis_enable_pktdata(CSI_CH_1, cap->pktdata_enable);
+					s3c_csis_start(CSI_CH_1, cam->mipi_lanes,
+					cam->mipi_settle, cam->mipi_align,
+					cam->width, cam->height,
+					cap->fmt.pixelformat);
+				}
+			}
+#ifdef CONFIG_MACH_P4NOTE
+			if (1) {
+#else
+			if (cap->fmt.priv != V4L2_PIX_FMT_MODE_CAPTURE) {
+#endif
+				ret = v4l2_subdev_call(cam->sd, video, s_stream, 1);
+				if (ret < 0) {
+					dev_err(ctrl->dev, "%s: s_stream failed\n",
+							__func__);
+					if (cam->id == CAMERA_CSI_C)
+						s3c_csis_stop(CSI_CH_0);
+					else
+						s3c_csis_stop(CSI_CH_1);
+
+					return ret;
+				}
+			}
+		}
+	}
+	/* Set FIMD to write back */
+	if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
+		if (cam->id == CAMERA_WB)
+			fimc_hwset_sysreg_camblk_fimd0_wb(ctrl);
+		else
+			fimc_hwset_sysreg_camblk_fimd1_wb(ctrl);
+
+		ret = s3cfb_direct_ioctl(0, S3CFB_SET_WRITEBACK, 1);
+		if (ret) {
+			fimc_err("failed set writeback\n");
+			return ret;
+		}
+
+	}
+
+	if (ctrl->is.sd && fimc_cam_use) {
+		struct platform_device *pdev = to_platform_device(ctrl->dev);
+		struct clk *pxl_async = NULL;
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_OFFSET_X;
+		is_ctrl.value = 0;
+		v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+		ctrl->is.offset_x = is_ctrl.value;
+		is_ctrl.id = V4L2_CID_IS_GET_SENSOR_OFFSET_Y;
+		is_ctrl.value = 0;
+		v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+		ctrl->is.offset_y = is_ctrl.value;
+		fimc_dbg("CSI setting width = %d, height = %d\n",
+				ctrl->is.fmt.width + ctrl->is.offset_x,
+				ctrl->is.fmt.height + ctrl->is.offset_y);
+
+		if (ctrl->flite_sd && fimc_cam_use) {
+			ctrl->is.mbus_fmt.width += ctrl->is.offset_x;
+			ctrl->is.mbus_fmt.height += ctrl->is.offset_y;
+			ret = v4l2_subdev_call(ctrl->flite_sd, video,
+				s_mbus_fmt, &ctrl->is.mbus_fmt);
+		}
+
+		if (cam->id == CAMERA_CSI_C)
+			s3c_csis_start(CSI_CH_0, cam->mipi_lanes,
+			cam->mipi_settle, cam->mipi_align,
+			ctrl->is.fmt.width + ctrl->is.offset_x,
+			ctrl->is.fmt.height + ctrl->is.offset_y,
+			V4L2_PIX_FMT_SGRBG10);
+		else if (cam->id == CAMERA_CSI_D)
+			s3c_csis_start(CSI_CH_1, cam->mipi_lanes,
+			cam->mipi_settle, cam->mipi_align,
+			ctrl->is.fmt.width + ctrl->is.offset_x,
+			ctrl->is.fmt.height + ctrl->is.offset_y,
+			V4L2_PIX_FMT_SGRBG10);
+
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+		    dev_err(&pdev->dev, "failed to get pxl_async\n");
+		    return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+		fimc_hwset_sysreg_camblk_isp_wb(ctrl);
+	}
+
+	if (ctrl->flite_sd && fimc_cam_use)
+		v4l2_subdev_call(ctrl->flite_sd, video, s_stream, 1);
+
+	if (!ctrl->is.sd && cap->movie_mode &&
+		!((cam->width == 880 && cam->height == 720))) {
+		printk(KERN_INFO "\n\n\n%s pm_qos_req is called..\n", __func__ );
+		dev_lock(ctrl->bus_dev, ctrl->dev, (unsigned long)400200);
+		pm_qos_add_request(&bus_qos_pm_qos_req, PM_QOS_BUS_QOS, 1);
+
+		/* ioremap for register block */
+		qos_regs = ioremap(0x11a00400, 0x10);
+		if (!qos_regs) {
+			fimc_err("%s: failed to remap io region\n", __func__);
+			return -1;
+		}
+		writel(0x3, qos_regs + 0x0);
+		writel(0x1, qos_regs + 0x4);
+		fimc_err("0x11a00400 = 0x%x , 0x11a00404 = 0x%x \n", readl(qos_regs + 0), readl(qos_regs + 4));
+
+		iounmap(qos_regs);
+	}
+
+	fimc_hwset_camera_type(ctrl);
+	fimc_hwset_camera_polarity(ctrl);
+	fimc_hwset_enable_lastend(ctrl);
+
+	if (cap->fmt.pixelformat != V4L2_PIX_FMT_JPEG &&
+		cap->fmt.pixelformat != V4L2_PIX_FMT_INTERLEAVED) {
+		fimc_hwset_camera_source(ctrl);
+		fimc_hwset_camera_offset(ctrl);
+
+		fimc_capture_scaler_info(ctrl);
+		fimc_hwset_prescaler(ctrl, &ctrl->sc);
+		fimc_hwset_scaler(ctrl, &ctrl->sc);
+		fimc_hwset_output_colorspace(ctrl, cap->fmt.pixelformat);
+		fimc_hwset_output_addr_style(ctrl, cap->fmt.pixelformat);
+
+		if (cap->fmt.pixelformat == V4L2_PIX_FMT_RGB32 ||
+			cap->fmt.pixelformat == V4L2_PIX_FMT_RGB565)
+			fimc_hwset_output_rgb(ctrl, cap->fmt.pixelformat);
+		else
+			fimc_hwset_output_yuv(ctrl, cap->fmt.pixelformat);
+
+		fimc_hwset_output_area(ctrl, cap->fmt.width, cap->fmt.height);
+		fimc_hwset_output_scan(ctrl, &cap->fmt);
+
+		fimc_hwset_output_rot_flip(ctrl, cap->rotate, cap->flip);
+		rot = fimc_mapping_rot_flip(cap->rotate, cap->flip);
+
+		if (rot & FIMC_ROT) {
+			fimc_hwset_org_output_size(ctrl, cap->fmt.width,
+					cap->fmt.height);
+			fimc_hwset_output_size(ctrl, cap->fmt.height,
+					cap->fmt.width);
+		} else {
+			fimc_hwset_org_output_size(ctrl, cap->fmt.width,
+					cap->fmt.height);
+			fimc_hwset_output_size(ctrl, cap->fmt.width,
+					cap->fmt.height);
+		}
+
+		fimc_hwset_jpeg_mode(ctrl, false);
+	} else {
+		fimc_hwset_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+		if (rot & FIMC_ROT)
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.height, cap->fmt.width);
+		else
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+		if (cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG)
+			fimc_hwset_output_area_size(ctrl,
+				fimc_camera_get_jpeg_memsize(ctrl));
+		else if (cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED)
+			fimc_hwset_output_area_size(ctrl,
+				0xc00000);
+		fimc_hwset_jpeg_mode(ctrl, true);
+	}
+
+	if (pdata->hw_ver >= 0x51) {
+		for (i = 0; i < cap->nr_bufs; i++)
+			fimc_hwset_output_address(ctrl, &cap->bufs[i], i);
+	} else {
+		for (i = 0; i < FIMC_PINGPONG; i++)
+			fimc_add_outqueue(ctrl, i);
+	}
+
+	if (cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG ||
+		cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED) {
+		fimc_hwset_scaler_bypass(ctrl);
+	}
+
+	ctrl->cap->cnt = 0;
+	fimc_start_capture(ctrl);
+	ctrl->status = FIMC_STREAMON;
+
+	if (ctrl->is.sd && fimc_cam_use)
+		ret = v4l2_subdev_call(ctrl->is.sd, video, s_stream, 1);
+	printk(KERN_INFO "%s-- fimc%d\n", __func__, ctrl->id);
+
+	/* if available buffer did not remained */
+	return 0;
+}
+
+int fimc_streamoff_capture(void *fh)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret = 0;
+	void __iomem *qos_regs;
+
+	printk(KERN_INFO "%s++ fimc%d\n", __func__, ctrl->id);
+
+	if (ctrl->status == FIMC_STREAMOFF) {
+		fimc_err("%s: fimc%d already stopped.\n", __func__, ctrl->id);
+		return -ENODEV;
+	}
+
+	if (fimc_check_capture_source(ctrl)) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	ctrl->status = FIMC_READY_OFF;
+
+	fimc_stop_capture(ctrl);
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	if ((get_fimc_dev()->active_camera == 0) &&
+	    fimc_cam_use && ctrl->cam->sd)
+		v4l2_subdev_call(ctrl->cam->sd, video, s_stream, 0);
+#endif
+
+	/* wait for stop hardware */
+	fimc_wait_disable_capture(ctrl);
+
+	fimc_hwset_disable_irq(ctrl);
+	if (pdata->hw_ver < 0x51)
+		INIT_LIST_HEAD(&cap->inq);
+
+	ctrl->status = FIMC_STREAMOFF;
+	if (fimc_cam_use) {
+		if (ctrl->is.sd)
+			v4l2_subdev_call(ctrl->is.sd, video, s_stream, 0);
+
+		if (ctrl->flite_sd)
+			v4l2_subdev_call(ctrl->flite_sd, video, s_stream, 0);
+
+		if (ctrl->cam->type == CAM_TYPE_MIPI) {
+			if (ctrl->cam->id == CAMERA_CSI_C)
+				s3c_csis_stop(CSI_CH_0);
+			else
+				s3c_csis_stop(CSI_CH_1);
+		}
+		fimc_hwset_reset(ctrl);
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+		if (ctrl->cam->sd && (get_fimc_dev()->active_camera != 0))
+#else
+		if (ctrl->cam->sd)
+#endif
+			v4l2_subdev_call(ctrl->cam->sd, video, s_stream, 0);
+	} else {
+		fimc_hwset_reset(ctrl);
+	}
+
+	if (!ctrl->is.sd && cap->movie_mode &&
+		!(ctrl->cam->width == 880 && ctrl->cam->height == 720)) {
+		printk(KERN_INFO "\n\n\n%s pm_qos_req is removed..\n", __func__ );
+		pm_qos_remove_request(&bus_qos_pm_qos_req);
+		dev_unlock(ctrl->bus_dev, ctrl->dev);
+
+		/* ioremap for register block */
+		qos_regs = ioremap(0x11a00400, 0x10);
+		if (!qos_regs) {
+			fimc_err("%s: failed to remap io region\n", __func__);
+			return -1;
+		}
+		writel(0x0, qos_regs + 0x0);
+		writel(0x0, qos_regs + 0x4);
+		fimc_err("0x11a00400 = 0x%x , 0x11a00404 = 0x%x \n", readl(qos_regs + 0), readl(qos_regs + 4));
+
+		iounmap(qos_regs);
+	}
+
+	/* Set FIMD to write back */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B)) {
+		ret = s3cfb_direct_ioctl(0, S3CFB_SET_WRITEBACK, 0);
+		if (ret) {
+			fimc_err("failed set writeback\n");
+			return ret;
+		}
+	}
+	/* disable camera power */
+	/* cam power off should call in the subdev release function */
+	if (fimc_cam_use) {
+		if (ctrl->cam->reset_camera) {
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+			if (ctrl->power_status != FIMC_POWER_SUSPEND)
+				ctrl->cam->initialized = 0;
+		}
+	}
+	printk(KERN_INFO "%s-- fimc%d\n", __func__, ctrl->id);
+	return 0;
+}
+
+int fimc_is_set_zoom(struct fimc_control *ctrl, struct v4l2_control *c)
+{
+	struct v4l2_control is_ctrl;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	struct s3c_platform_camera *cam = NULL;
+	int ret = 0;
+
+	is_ctrl.id = 0;
+	is_ctrl.value = 0;
+
+	if (ctrl->cam)
+		cam = ctrl->cam;
+	else
+		return -ENODEV;
+
+	/* 0. Check zoom width and height */
+	if (!c->value) {
+		ctrl->is.zoom_in_width = ctrl->is.fmt.width;
+		ctrl->is.zoom_in_height = ctrl->is.fmt.height;
+	} else {
+		ctrl->is.zoom_in_width = ctrl->is.fmt.width - (16 * c->value);
+		ctrl->is.zoom_in_height =
+			(ctrl->is.zoom_in_width * ctrl->is.fmt.height)
+			/ ctrl->is.fmt.width;
+		/* bayer crop contraint */
+		switch (ctrl->is.zoom_in_height%4) {
+		case 1:
+			ctrl->is.zoom_in_height--;
+			break;
+		case 2:
+			ctrl->is.zoom_in_height += 2;
+			break;
+		case 3:
+			ctrl->is.zoom_in_height++;
+			break;
+		}
+		if ((ctrl->is.zoom_in_width < (ctrl->is.fmt.width/4))
+		|| (ctrl->is.zoom_in_height < (ctrl->is.fmt.height/4))) {
+			ctrl->is.zoom_in_width = ctrl->is.fmt.width/4;
+			ctrl->is.zoom_in_height = ctrl->is.fmt.height/4;
+		}
+	}
+	/* 1. fimc stop */
+	fimc_stop_zoom_capture(ctrl);
+	/* 2. Set zoom and calculate new width and height */
+	if (ctrl->is.sd && fimc_cam_use) {
+		ret = v4l2_subdev_call(ctrl->is.sd, core, s_ctrl, c);
+		/* 2. Set zoom */
+		is_ctrl.id = V4L2_CID_IS_ZOOM_STATE;
+		is_ctrl.value = 0;
+		while (!is_ctrl.value) {
+			v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+			fimc_dbg("V4L2_CID_IS_ZOOM_STATE - %d", is_ctrl.value);
+		}
+	}
+	/* 2. Change soruce size of FIMC */
+	fimc_hwset_camera_change_source(ctrl);
+	fimc_capture_change_scaler_info(ctrl);
+	fimc_hwset_prescaler(ctrl, &ctrl->sc);
+	fimc_hwset_scaler(ctrl, &ctrl->sc);
+	/* 4. Start FIMC */
+	fimc_start_zoom_capture(ctrl);
+	/* 5. FIMC-IS stream on */
+	if (ctrl->is.sd && fimc_cam_use)
+		ret = v4l2_subdev_call(ctrl->is.sd, video, s_stream, 1);
+
+	return 0;
+}
+
+static void fimc_buf2bs(struct fimc_buf_set *bs, struct fimc_buf *buf)
+{
+	bs->base[FIMC_ADDR_Y]	=  buf->base[FIMC_ADDR_Y];
+	bs->length[FIMC_ADDR_Y]	=  buf->length[FIMC_ADDR_Y];
+
+	bs->base[FIMC_ADDR_CB]	 =  buf->base[FIMC_ADDR_CB];
+	bs->length[FIMC_ADDR_CB] =  buf->length[FIMC_ADDR_CB];
+
+	bs->base[FIMC_ADDR_CR]	 =  buf->base[FIMC_ADDR_CR];
+	bs->length[FIMC_ADDR_CR] =  buf->length[FIMC_ADDR_CR];
+}
+
+int fimc_qbuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_buf *buf = (struct fimc_buf *)b->m.userptr;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	struct fimc_capinfo *cap = ctrl->cap;
+	int idx = b->index;
+	int framecnt_seq;
+	int available_bufnum;
+	size_t length = 0;
+	int i;
+
+	if (!cap || !ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	if (pdata->hw_ver >= 0x51) {
+		if (cap->bufs[idx].state != VIDEOBUF_IDLE) {
+			fimc_err("%s: invalid state idx : %d\n", __func__, idx);
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -EINVAL;
+		} else {
+			if (b->memory == V4L2_MEMORY_USERPTR) {
+				fimc_buf2bs(&cap->bufs[idx], buf);
+				fimc_hwset_output_address(ctrl,	&cap->bufs[idx], idx);
+			}
+
+			fimc_hwset_output_buf_sequence(ctrl, idx, FIMC_FRAMECNT_SEQ_ENABLE);
+			cap->bufs[idx].state = VIDEOBUF_QUEUED;
+			if (ctrl->status == FIMC_BUFFER_STOP) {
+				framecnt_seq = fimc_hwget_output_buf_sequence(ctrl);
+				available_bufnum =
+					fimc_hwget_number_of_bits(framecnt_seq);
+				if (available_bufnum >= 2) {
+					printk(KERN_INFO "fimc_qbuf_capture start again\n");
+					cap->cnt = 0;
+					fimc_start_capture(ctrl);
+					ctrl->status = FIMC_STREAMON;
+					ctrl->restart = true;
+				}
+			}
+		}
+	} else {
+		fimc_add_inqueue(ctrl, b->index);
+	}
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	if (!cap->cacheable)
+		return 0;
+
+	for (i = 0; i < 3; i++) {
+		if (cap->bufs[b->index].base[i])
+			length += cap->bufs[b->index].length[i];
+		else
+			break;
+	}
+
+	if (length > (unsigned long) L2_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+		outer_flush_all();      /* L2 */
+	} else if (length > (unsigned long) L1_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			outer_flush_range(start, end);  /* L2 */
+		}
+	} else {
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			dmac_flush_range(phys_to_virt(start), phys_to_virt(end));
+			outer_flush_range(start, end);  /* L2 */
+		}
+	}
+
+	return 0;
+}
+
+static void fimc_bs2buf(struct fimc_buf *buf, struct fimc_buf_set *bs)
+{
+	buf->base[FIMC_ADDR_Y]		=  bs->base[FIMC_ADDR_Y];
+	buf->length[FIMC_ADDR_Y]	=  bs->length[FIMC_ADDR_Y];
+
+	buf->base[FIMC_ADDR_CB]		=  bs->base[FIMC_ADDR_CB];
+	buf->length[FIMC_ADDR_CB]	=  bs->length[FIMC_ADDR_CB];
+
+	buf->base[FIMC_ADDR_CR]		=  bs->base[FIMC_ADDR_CR];
+	buf->length[FIMC_ADDR_CR]	=  bs->length[FIMC_ADDR_CR];
+}
+
+int fimc_dqbuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	unsigned long spin_flags;
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *bs;
+	struct fimc_buf *buf = (struct fimc_buf *)b->m.userptr;
+	size_t length = 0;
+	int i, pp, ret = 0;
+	phys_addr_t start, end;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	if (!cap || !ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (pdata->hw_ver >= 0x51) {
+		spin_lock_irqsave(&ctrl->outq_lock, spin_flags);
+
+		if (list_empty(&cap->outgoing_q)) {
+			fimc_info2("%s: outgoing_q is empty\n", __func__);
+			spin_unlock_irqrestore(&ctrl->outq_lock, spin_flags);
+			return -EAGAIN;
+		} else {
+			bs = list_first_entry(&cap->outgoing_q, struct fimc_buf_set,
+					list);
+			fimc_info2("%s[%d]: bs->id : %d\n", __func__, ctrl->id, bs->id);
+			b->index = bs->id;
+			bs->state = VIDEOBUF_IDLE;
+
+			if (b->memory == V4L2_MEMORY_USERPTR)
+				fimc_bs2buf(buf, bs);
+
+			list_del(&bs->list);
+		}
+
+		spin_unlock_irqrestore(&ctrl->outq_lock, spin_flags);
+	} else {
+		pp = ((fimc_hwget_frame_count(ctrl) + 2) % 4);
+		if (cap->fmt.field == V4L2_FIELD_INTERLACED_TB)
+			pp &= ~0x1;
+		b->index = cap->outq[pp];
+		fimc_info2("%s: buffer(%d) outq[%d]\n", __func__, b->index, pp);
+		ret = fimc_add_outqueue(ctrl, pp);
+		if (ret) {
+			b->index = -1;
+			fimc_err("%s: no inqueue buffer\n", __func__);
+		}
+	}
+
+	if (cap->pktdata_enable) {
+		flush_cache_all();	/* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+
+		start = cap->bufs[b->index].base[cap->pktdata_plane];
+		end   = cap->bufs[b->index].base[cap->pktdata_plane] +
+				    cap->bufs[b->index].length[cap->pktdata_plane] - 1;
+		fimc_info2("fimc_dqbuf interleaved mode cache flush... start 0x%x, size 0x%x\n",
+				start, cap->bufs[b->index].length[cap->pktdata_plane] );
+
+		outer_flush_range(start, end);	/* L2 */
+	}
+
+	if (!cap->cacheable)
+		return ret;
+
+	for (i = 0; i < 3; i++) {
+		if (cap->bufs[b->index].base[i])
+			length += cap->bufs[b->index].length[i];
+		else
+			break;
+	}
+
+	if (length > (unsigned long) L2_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+		outer_flush_all();      /* L2 */
+	} else if (length > (unsigned long) L1_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			outer_flush_range(start, end);  /* L2 */
+		}
+	} else {
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			dmac_flush_range(phys_to_virt(start), phys_to_virt(end));
+			outer_flush_range(start, end);  /* L2 */
+		}
+	}
+
+	return ret;
+}
+
+int fimc_enum_framesizes(struct file *filp, void *fh, struct v4l2_frmsizeenum *fsize)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i;
+	u32 index = 0;
+	for (i = 0; i < ARRAY_SIZE(capture_fmts); i++) {
+		if (fsize->pixel_format != capture_fmts[i].pixelformat)
+			continue;
+		if (fsize->index == index) {
+			fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+			/* this is camera sensor's width, height.
+			 * originally this should be filled each file format
+			 */
+			fsize->discrete.width = ctrl->cam->width;
+			fsize->discrete.height = ctrl->cam->height;
+
+			return 0;
+		}
+		index++;
+	}
+
+	return -EINVAL;
+}
+int fimc_enum_frameintervals(struct file *filp, void *fh,
+		struct v4l2_frmivalenum *fival)
+{
+	if (fival->index > 0)
+		return -EINVAL;
+	/* temporary only support 30fps */
+	fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+	fival->discrete.numerator = 1000;
+	fival->discrete.denominator = 30000;
+
+	return 0;
+}
+
+/*
+ * only used at mipi power func.
+ */
+struct device *fimc_get_active_device(void)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_control *ctrl;
+
+	if (!fimc || (fimc->active_camera < 0))
+		return NULL;
+
+	ctrl = get_fimc_ctrl(fimc->active_camera);
+
+	return ctrl->dev;
+}
diff --git a/drivers/media/video/samsung/fimc/fimc_capture_u1.c b/drivers/media/video/samsung/fimc/fimc_capture_u1.c
new file mode 100644
index 0000000..d21d877
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_capture_u1.c
@@ -0,0 +1,2317 @@
+/* linux/drivers/media/video/samsung/fimc_capture.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * V4L2 Capture device support file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/clk.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <plat/media.h>
+#include <plat/clock.h>
+#include <plat/fimc.h>
+#include <linux/delay.h>
+#include <mach/cpufreq.h>
+
+#include <asm/cacheflush.h>
+
+#include "fimc.h"
+
+#define FRM_RATIO(w, h)		((w)*10/(h))
+
+typedef enum {
+	FRM_RATIO_QCIF = 12,
+	FRM_RATIO_VGA = 13,
+	FRM_RATIO_D1 = 15,
+	FRM_RATIO_WVGA = 16,
+	FRM_RATIO_HD = 17,
+} frm_ratio_t;
+
+/* subdev handling macro */
+#define subdev_call(ctrl, o, f, args...) \
+	v4l2_subdev_call(ctrl->cam->sd, o, f, ##args)
+
+static const struct v4l2_fmtdesc capture_fmts[] = {
+	{
+		.index		= 0,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "RGB-5-6-5",
+		.pixelformat	= V4L2_PIX_FMT_RGB565,
+	}, {
+		.index		= 1,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "RGB-8-8-8, unpacked 24 bpp",
+		.pixelformat	= V4L2_PIX_FMT_RGB32,
+	}, {
+		.index		= 2,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, YCbYCr",
+		.pixelformat	= V4L2_PIX_FMT_YUYV,
+	}, {
+		.index		= 3,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, CbYCrY",
+		.pixelformat	= V4L2_PIX_FMT_UYVY,
+	}, {
+		.index		= 4,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, CrYCbY",
+		.pixelformat	= V4L2_PIX_FMT_VYUY,
+	}, {
+		.index		= 5,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PACKED,
+		.description	= "YUV 4:2:2 packed, YCrYCb",
+		.pixelformat	= V4L2_PIX_FMT_YVYU,
+	}, {
+		.index		= 6,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV422P,
+	}, {
+		.index		= 7,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV12,
+	}, {
+		.index		= 8,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CbCr, Tiled",
+		.pixelformat	= V4L2_PIX_FMT_NV12T,
+	}, {
+		.index		= 9,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV21,
+	}, {
+		.index		= 10,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/CbCr",
+		.pixelformat	= V4L2_PIX_FMT_NV16,
+	}, {
+		.index		= 11,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:2 planar, Y/CrCb",
+		.pixelformat	= V4L2_PIX_FMT_NV61,
+	}, {
+		.index		= 12,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YUV 4:2:0 planar, Y/Cb/Cr",
+		.pixelformat	= V4L2_PIX_FMT_YUV420,
+	}, {
+		.index		= 13,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.description	= "JPEG encoded data",
+		.pixelformat	= V4L2_PIX_FMT_JPEG,
+	}, {
+		.index		= 14,
+		.type		= V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.flags		= FORMAT_FLAGS_PLANAR,
+		.description	= "YVU 4:2:0 planar, Y/Cr/Cb",
+		.pixelformat	= V4L2_PIX_FMT_YVU420,
+	},
+};
+
+static const struct v4l2_queryctrl fimc_controls[] = {
+	{
+		.id = V4L2_CID_ROTATION,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Roataion",
+		.minimum = 0,
+		.maximum = 270,
+		.step = 90,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_HFLIP,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Horizontal Flip",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_VFLIP,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Vertical Flip",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	}, {
+		.id = V4L2_CID_PADDR_Y,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Y",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CB,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Cb",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CR,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address Cr",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_PADDR_CBCR,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Physical address CbCr",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+		.flags = V4L2_CTRL_FLAG_READ_ONLY,
+	}, {
+		.id = V4L2_CID_CACHEABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Cacheable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+};
+
+#ifndef CONFIG_VIDEO_FIMC_MIPI
+void s3c_csis_start(int csis_id, int lanes, int settle, \
+	int align, int width, int height, int pixel_format) {}
+void s3c_csis_stop(int csis_id) {}
+#endif
+
+static int fimc_init_camera(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata;
+	struct s3c_platform_camera *cam;
+	int ret = 0, retry_cnt = 0;
+	u32 pixelformat;
+
+	pdata = to_fimc_plat(ctrl->dev);
+
+	cam = ctrl->cam;
+
+	/* do nothing if already initialized */
+	if (ctrl->cam->initialized)
+		return 0;
+
+	/*
+	 * WriteBack mode doesn't need to set clock and power,
+	 * but it needs to set source width, height depend on LCD resolution.
+	*/
+	if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
+		s3cfb_direct_ioctl(0, S3CFB_GET_LCD_WIDTH, \
+					(unsigned long)&cam->width);
+		s3cfb_direct_ioctl(0, S3CFB_GET_LCD_HEIGHT, \
+					(unsigned long)&cam->height);
+		cam->window.width = cam->width;
+		cam->window.height = cam->height;
+		cam->initialized = 1;
+		return 0;
+	}
+
+retry:
+	/* set rate for mclk */
+	if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
+		clk_set_rate(cam->clk, cam->clk_rate);
+		clk_enable(cam->clk);
+		fimc->mclk_status = CAM_MCLK_ON;
+		fimc_info1("clock for camera: %d\n", cam->clk_rate);
+	}
+
+	/* enable camera power if needed */
+	if (cam->cam_power) {
+		ret = cam->cam_power(1);
+		if (unlikely(ret < 0))
+			fimc_err("fail to power on\n\n");
+	}
+
+	/* subdev call for init */
+#if !defined(CONFIG_MACH_PX)
+	do_gettimeofday(&ctrl->before_time);
+#endif
+	if (ctrl->cap->fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		ret = v4l2_subdev_call(cam->sd, core, init, 1);
+		pixelformat = V4L2_PIX_FMT_JPEG;
+	} else {
+		ret = v4l2_subdev_call(cam->sd, core, init, 0);
+		pixelformat = cam->pixelformat;
+	}
+
+	/* Retry camera power-up if first i2c fails. */
+	if (unlikely(ret < 0)) {
+		if (cam->cam_power)
+			cam->cam_power(0);
+
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+
+		if (retry_cnt++ < 3) {
+			msleep(100);
+			fimc_err("Retry power on(%d/3)\n\n", retry_cnt);
+			goto retry;
+		}
+	} else {
+		cam->initialized = 1;
+	}
+
+	return ret;
+}
+
+static int fimc_camera_get_jpeg_memsize(struct fimc_control *ctrl)
+{
+	int ret = 0;
+	struct v4l2_control cam_ctrl;
+	cam_ctrl.id = V4L2_CID_CAM_JPEG_MEMSIZE;
+
+	ret = subdev_call(ctrl, core, g_ctrl, &cam_ctrl);
+	if (ret < 0) {
+		fimc_err("%s: Subdev doesn't support JEPG encoding.\n", \
+				 __func__);
+		return 0;
+	}
+
+	return cam_ctrl.value;
+}
+
+
+static int fimc_capture_scaler_info(struct fimc_control *ctrl)
+{
+	struct fimc_scaler *sc = &ctrl->sc;
+	struct v4l2_rect *window = &ctrl->cam->window;
+	int tx, ty, sx, sy;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int rot = 0;
+
+	sx = window->width;
+	sy = window->height;
+
+	sc->real_width = sx;
+	sc->real_height = sy;
+
+	rot = fimc_mapping_rot_flip(ctrl->cap->rotate, ctrl->cap->flip);
+
+	if (rot & FIMC_ROT) {
+		tx = ctrl->cap->fmt.height;
+		ty = ctrl->cap->fmt.width;
+	} else {
+		tx = ctrl->cap->fmt.width;
+		ty = ctrl->cap->fmt.height;
+	}
+
+	fimc_warn("%s: CamOut (%d, %d), TargetOut (%d, %d)\n", __func__, sx, sy, tx, ty);
+
+	if (sx <= 0 || sy <= 0) {
+		fimc_err("%s: invalid source size\n", __func__);
+		return -EINVAL;
+	}
+
+	if (tx <= 0 || ty <= 0) {
+		fimc_err("%s: invalid target size\n", __func__);
+		return -EINVAL;
+	}
+
+	fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
+	fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
+
+	sc->pre_dst_width = sx / sc->pre_hratio;
+	sc->pre_dst_height = sy / sc->pre_vratio;
+
+	if (pdata->hw_ver >= 0x50) {
+		sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
+	} else {
+		sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
+		sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
+	}
+
+	sc->scaleup_h = (tx >= sx) ? 1 : 0;
+	sc->scaleup_v = (ty >= sy) ? 1 : 0;
+
+	return 0;
+}
+
+static int fimc_add_inqueue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *tmp_buf;
+	struct list_head *count;
+
+	/* PINGPONG_2ADDR_MODE Only */
+	list_for_each(count, &cap->inq) {
+		tmp_buf = list_entry(count, struct fimc_buf_set, list);
+		/* skip list_add_tail if already buffer is in cap->inq list*/
+		if (tmp_buf->id == i)
+			return 0;
+	}
+	list_add_tail(&cap->bufs[i].list, &cap->inq);
+
+	return 0;
+}
+
+static int fimc_add_outqueue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *buf;
+	unsigned int mask = 0x2;
+
+	/* PINGPONG_2ADDR_MODE Only */
+	/* pair_buf_index stands for pair index of i. (0<->2) (1<->3) */
+	int pair_buf_index = (i^mask);
+
+	/* FIMC have 4 h/w registers */
+	if (i < 0 || i >= FIMC_PHYBUFS) {
+		fimc_err("%s: invalid queue index : %d\n", __func__, i);
+		return -ENOENT;
+	}
+
+	if (list_empty(&cap->inq))
+		return -ENOENT;
+
+	buf = list_first_entry(&cap->inq, struct fimc_buf_set, list);
+
+	/* pair index buffer should be allocated first */
+	cap->outq[pair_buf_index] = buf->id;
+	fimc_hwset_output_address(ctrl, buf, pair_buf_index);
+
+	cap->outq[i] = buf->id;
+	fimc_hwset_output_address(ctrl, buf, i);
+
+	list_del(&buf->list);
+
+	return 0;
+}
+
+int fimc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	/* WriteBack doesn't have subdev_call */
+
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+		return 0;
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = subdev_call(ctrl, video, g_parm, a);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+	int new_fps = a->parm.capture.timeperframe.denominator /
+					a->parm.capture.timeperframe.numerator;
+
+	fimc_info2("%s fimc%d, %d\n", __func__, ctrl->id, new_fps);
+
+	/* WriteBack doesn't have subdev_call */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+		return 0;
+
+	mutex_lock(&ctrl->v4l2_lock);
+#ifdef CONFIG_MACH_S2PLUS
+	if (ctrl->id == FIMC0)
+#else
+	if (ctrl->id != FIMC2)
+#endif
+		ret = subdev_call(ctrl, video, s_parm, a);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+/* Enumerate controls */
+int fimc_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *qc)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i, ret;
+
+	fimc_dbg("%s\n", __func__);
+
+	for (i = 0; i < ARRAY_SIZE(fimc_controls); i++) {
+		if (fimc_controls[i].id == qc->id) {
+			memcpy(qc, &fimc_controls[i], \
+				sizeof(struct v4l2_queryctrl));
+			return 0;
+		}
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = subdev_call(ctrl, core, queryctrl, qc);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+/* Menu control items */
+int fimc_querymenu(struct file *file, void *fh, struct v4l2_querymenu *qm)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ret = subdev_call(ctrl, core, querymenu, qm);
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_enum_input(struct file *file, void *fh, struct v4l2_input *inp)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+
+	fimc_dbg("%s: index %d\n", __func__, inp->index);
+
+	if (inp->index < 0 || inp->index >= FIMC_MAXCAMS) {
+		fimc_err("%s: invalid input index, received = %d\n" \
+				, __func__, inp->index);
+		return -EINVAL;
+	}
+
+	if (!fimc->camera_isvalid[inp->index])
+		return -EINVAL;
+	mutex_lock(&ctrl->v4l2_lock);
+
+	strcpy(inp->name, fimc->camera[inp->index]->info->type);
+	inp->type = V4L2_INPUT_TYPE_CAMERA;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_input(struct file *file, void *fh, unsigned int *i)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_global *fimc = get_fimc_dev();
+
+	/* In case of isueing g_input before s_input */
+	if (!ctrl->cam) {
+		fimc_err("no camera device selected yet!" \
+				"do VIDIOC_S_INPUT first\n");
+		return -ENODEV;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	*i = (unsigned int) fimc->active_camera;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	fimc_dbg("%s: index %d\n", __func__, *i);
+
+	return 0;
+}
+
+int fimc_release_subdev(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct i2c_client *client;
+
+	if (ctrl && ctrl->cam && ctrl->cam->sd) {
+		fimc_dbg("%s called\n", __func__);
+
+		/* WriteBack doesn't need clock setting */
+		if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B)) {
+			ctrl->cam->initialized = 0;
+			ctrl->cam = NULL;
+			fimc->active_camera = -1;
+			return 0;
+		}
+
+		client = v4l2_get_subdevdata(ctrl->cam->sd);
+		i2c_unregister_device(client);
+		ctrl->cam->sd = NULL;
+		if (ctrl->cam->cam_power)
+			ctrl->cam->cam_power(0);
+
+		/* shutdown the MCLK */
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+
+		ctrl->cam->initialized = 0;
+		ctrl->cam = NULL;
+		fimc->active_camera = -1;
+	}
+	return 0;
+}
+
+static int fimc_configure_subdev(struct fimc_control *ctrl)
+{
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info *i2c_info;
+	struct v4l2_subdev *sd;
+	unsigned short addr;
+	char *name;
+
+	i2c_adap = i2c_get_adapter(ctrl->cam->get_i2c_busnum());
+	if (!i2c_adap) {
+		fimc_err("subdev i2c_adapter missing-skip registration\n");
+		return -ENODEV;
+	}
+
+	i2c_info = ctrl->cam->info;
+	if (!i2c_info) {
+		fimc_err("%s: subdev i2c board info missing\n", __func__);
+		return -ENODEV;
+	}
+
+	name = i2c_info->type;
+	if (!name) {
+		fimc_err("subdev i2c driver name missing-skip registration\n");
+		return -ENODEV;
+	}
+
+	addr = i2c_info->addr;
+	if (!addr) {
+		fimc_err("subdev i2c address missing-skip registration\n");
+		return -ENODEV;
+	}
+	/*
+	 * NOTE: first time subdev being registered,
+	 * s_config is called and try to initialize subdev device
+	 * but in this point, we are not giving MCLK and power to subdev
+	 * so nothing happens but pass platform data through
+	 */
+	sd = v4l2_i2c_new_subdev_board(&ctrl->v4l2_dev, i2c_adap,
+			i2c_info, &addr);
+	if (!sd) {
+		fimc_err("%s: v4l2 subdev board registering failed\n",
+				__func__);
+		return -ENODEV;
+	}
+
+	/* Assign subdev to proper camera device pointer */
+	ctrl->cam->sd = sd;
+
+	return 0;
+}
+
+int fimc_s_input(struct file *file, void *fh, unsigned int i)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	int ret = 0;
+
+	printk(KERN_INFO "%s: index %d FIMC%d\n", __func__, i, ctrl->id);
+
+	if (i < 0 || i >= FIMC_MAXCAMS) {
+		fimc_err("%s: invalid input index\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!fimc->camera_isvalid[i])
+		return -EINVAL;
+
+#ifdef CONFIG_MACH_S2PLUS
+	if (fimc->camera[i]->sd && ctrl->id == FIMC0) {
+#else
+	if (fimc->camera[i]->sd && ctrl->id != FIMC2) {
+#endif
+		fimc_err("%s: Camera already in use.\n", __func__);
+		return -EBUSY;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/* If ctrl->cam is not NULL, there is one subdev already registered.
+	 * We need to unregister that subdev first. */
+	if (i != fimc->active_camera) {
+		printk(KERN_INFO "\n\nfimc_s_input activating subdev\n");
+		fimc_release_subdev(ctrl);
+		ctrl->cam = fimc->camera[i];
+
+		if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+			ret = fimc_configure_subdev(ctrl);
+			if (ret < 0) {
+				mutex_unlock(&ctrl->v4l2_lock);
+				fimc_err("%s: Could not register camera" \
+						" sensor with V4L2.\n", __func__);
+				return -ENODEV;
+			}
+		}
+
+		fimc->active_camera = i;
+		printk(KERN_INFO "fimc_s_input activated subdev = %d\n", i);
+	}
+
+#ifdef CONFIG_MACH_S2PLUS
+	if (ctrl->id == FIMC1) {
+		if (i == fimc->active_camera) {
+			ctrl->cam = fimc->camera[i];
+			fimc_info2("fimc_s_input activating subdev FIMC1 %d\n",
+							ctrl->cam->initialized);
+		} else {
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -EINVAL;
+		}
+	}
+#else
+	if (ctrl->id == FIMC2) {
+		if (i == fimc->active_camera) {
+			ctrl->cam = fimc->camera[i];
+			fimc_info2("fimc_s_input activating subdev FIMC2 %d\n",
+							ctrl->cam->initialized);
+		} else {
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -EINVAL;
+		}
+	}
+#endif
+
+	/*
+	 * The first time alloc for struct cap_info, and will be
+	 * released at the file close.
+	 * Anyone has better idea to do this?
+	*/
+	if (!cap) {
+		cap = kzalloc(sizeof(*cap), GFP_KERNEL);
+		if (!cap) {
+			fimc_err("%s: no memory for "
+				"capture device info\n", __func__);
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -ENOMEM;
+		}
+
+		/* assign to ctrl */
+		ctrl->cap = cap;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_OFF) {
+			pm_runtime_get_sync(&pdev->dev);
+		}
+#endif
+	}
+
+#if !defined(CONFIG_MACH_PX)
+	if (fimc->active_camera == 0) {
+		if (!ctrl->cam->initialized)
+			ret = fimc_init_camera(ctrl);
+
+		if (unlikely(ret < 0)) {
+			if (ret == -ENOSYS) {
+				/* return no error If firmware is bad.
+				Because F/W update app should access the sensor through HAL instance */
+				fimc_warn("%s: please update the F/W\n", __func__);
+			} else {
+				mutex_unlock(&ctrl->v4l2_lock);
+				fimc_err("%s: fail to initialize subdev\n", __func__);
+				return ret;
+			}
+		}
+	}
+#endif
+
+	mutex_unlock(&ctrl->v4l2_lock);
+	printk(KERN_INFO "%s--: index %d FIMC%d\n", __func__, i, ctrl->id);
+
+	return 0;
+}
+
+int fimc_enum_fmt_vid_capture(struct file *file, void *fh,
+					struct v4l2_fmtdesc *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i = f->index;
+
+	/* printk(KERN_INFO "%s++\n", __func__); */
+
+	if (i >= ARRAY_SIZE(capture_fmts)) {
+		fimc_err("%s: There is no support format index %d\n", __func__, i);
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(f, 0, sizeof(*f));
+	memcpy(f, &capture_fmts[i], sizeof(*f));
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	/* printk(KERN_INFO "%s--\n", __func__); */
+	return 0;
+}
+
+int fimc_g_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+
+	printk(KERN_INFO "%s++\n", __func__);
+
+	if (!ctrl->cap) {
+		fimc_err("%s: no capture device info\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(&f->fmt.pix, 0, sizeof(f->fmt.pix));
+	memcpy(&f->fmt.pix, &ctrl->cap->fmt, sizeof(f->fmt.pix));
+
+	mutex_unlock(&ctrl->v4l2_lock);
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+/*
+ * Check for whether the requested format
+ * can be streamed out from FIMC
+ * depends on FIMC node
+ */
+static int fimc_fmt_avail(struct fimc_control *ctrl,
+		struct v4l2_pix_format *f)
+{
+	int i;
+
+	/*
+	 * TODO: check for which FIMC is used.
+	 * Available fmt should be varied for each FIMC
+	 */
+
+	for (i = 0; i < ARRAY_SIZE(capture_fmts); i++) {
+		if (capture_fmts[i].pixelformat == f->pixelformat)
+			return 0;
+	}
+
+	fimc_info1("Not supported pixelformat requested\n");
+
+	return -1;
+}
+
+/*
+ * figures out the depth of requested format
+ */
+static int fimc_fmt_depth(struct fimc_control *ctrl, struct v4l2_pix_format *f)
+{
+	int err, depth = 0;
+
+	/* First check for available format or not */
+	err = fimc_fmt_avail(ctrl, f);
+	if (err < 0)
+		return -1;
+
+	/* handles only supported pixelformats */
+	switch (f->pixelformat) {
+	case V4L2_PIX_FMT_RGB32:
+		depth = 32;
+		fimc_dbg("32bpp\n");
+		break;
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_YUYV:
+	case V4L2_PIX_FMT_UYVY:
+	case V4L2_PIX_FMT_VYUY:
+	case V4L2_PIX_FMT_YVYU:
+	case V4L2_PIX_FMT_YUV422P:
+	case V4L2_PIX_FMT_NV16:
+	case V4L2_PIX_FMT_NV61:
+		depth = 16;
+		fimc_dbg("16bpp\n");
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV12T:
+	case V4L2_PIX_FMT_NV21:
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		depth = 12;
+		fimc_dbg("12bpp\n");
+		break;
+	case V4L2_PIX_FMT_JPEG:
+		depth = -1;
+		fimc_dbg("Compressed format.\n");
+		break;
+	default:
+		fimc_dbg("why am I here?\n");
+		break;
+	}
+
+	return depth;
+}
+
+static int fimc_calc_frame_ratio(struct fimc_control *ctrl,
+				struct fimc_capinfo *cap)
+{
+	if (cap->fmt.priv != V4L2_PIX_FMT_MODE_PREVIEW)
+		return 0;
+
+	if ((cap->sensor_output_width != 0) &&
+	    (cap->sensor_output_height != 0)) {
+		cap->mbus_fmt.width = cap->sensor_output_width;
+		cap->mbus_fmt.height = cap->sensor_output_height;
+		cap->sensor_output_width = cap->sensor_output_height = 0;
+		pr_info("fimc: forced sensor output size: (%d, %d) to (%d, %d)\n",
+			cap->mbus_fmt.width, cap->mbus_fmt.height,
+			cap->fmt.width, cap->fmt.height);
+	} else if (cap->vt_mode) {
+		cap->mbus_fmt.width = 640;
+		cap->mbus_fmt.height = 480;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_MACH_PX) && defined(CONFIG_VIDEO_HD_SUPPORT)
+static int fimc_check_hd_mode(struct fimc_control *ctrl, struct v4l2_format *f)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	struct fimc_capinfo *cap = ctrl->cap;
+	u32 hd_mode = 0;
+	int ret = -EINVAL;
+
+	if (!cap->movie_mode || (fimc->active_camera != 0))
+		return 0;
+
+	if (f->fmt.pix.width == 1280 || cap->sensor_output_width == 1280)
+		hd_mode = 1;
+
+	printk(KERN_DEBUG "%s:movie_mode=%d, hd_mode=%d\n",
+			__func__, cap->movie_mode, hd_mode);
+
+	if (((cap->movie_mode == 2) && !hd_mode) ||
+	    ((cap->movie_mode == 1) && hd_mode)) {
+		fimc_warn("%s: mode change, power(%d) down\n",
+			__func__, ctrl->cam->initialized);
+		cap->movie_mode = hd_mode ? 2 : 1;
+
+		if (ctrl->cam->initialized) {
+			struct v4l2_control c;
+
+			subdev_call(ctrl, core, reset, 0);
+			c.id = V4L2_CID_CAMERA_SENSOR_MODE;
+			c.value = cap->movie_mode;
+			subdev_call(ctrl, core, s_ctrl, &c);
+
+			if (ctrl->cam->cam_power) {
+				ret = ctrl->cam->cam_power(0);
+				if (unlikely(ret))
+					return ret;
+			}
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+
+			ctrl->cam->initialized = 0;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+int fimc_s_fmt_vid_private(struct file *file, void *fh, struct v4l2_format *f)
+{
+	return -EINVAL;
+}
+
+int fimc_s_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct v4l2_mbus_framefmt *mbus_fmt;
+
+	int ret = 0;
+	int depth;
+	printk(KERN_INFO "%s FIMC%d\n", __func__, ctrl->id);
+
+	/* rotaton, flip, dtp_mode, movie_mode and vt_mode,
+	 * sensor_output_width,height should be maintained.(by TN) */
+	memset(cap, 0, sizeof(*cap) - sizeof(u32) * 7);
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	memset(&cap->fmt, 0, sizeof(cap->fmt));
+	memcpy(&cap->fmt, &f->fmt.pix, sizeof(cap->fmt));
+
+	mbus_fmt = &cap->mbus_fmt;
+#ifdef CONFIG_MACH_S2PLUS
+	if (ctrl->id == FIMC0) {
+#else
+	if (ctrl->id != FIMC2) {
+#endif
+		if (cap->movie_mode || cap->vt_mode ||
+		    cap->fmt.priv == V4L2_PIX_FMT_MODE_HDR) {
+#if defined(CONFIG_MACH_PX) && defined(CONFIG_VIDEO_HD_SUPPORT)
+			ret = fimc_check_hd_mode(ctrl, f);
+			if (unlikely(ret)) {
+				fimc_err("%s: error, check_hd_mode\n",
+					__func__);
+				return ret;
+			}
+#endif
+			fimc_calc_frame_ratio(ctrl, cap);
+		}
+#if defined(CONFIG_MACH_U1_BD) || defined(CONFIG_MACH_Q1_BD)
+		else {
+			fimc_calc_frame_ratio(ctrl, cap);
+		}
+#endif
+
+		if (!(mbus_fmt->width && mbus_fmt->height)) {
+			mbus_fmt->width = cap->fmt.width;
+			mbus_fmt->height = cap->fmt.height;
+		}
+		mbus_fmt->field = cap->fmt.priv;
+	}
+
+	/*
+	 * Note that expecting format only can be with
+	 * available output format from FIMC
+	 * Following items should be handled in driver
+	 * bytesperline = width * depth / 8
+	 * sizeimage = bytesperline * height
+	 */
+	/* This function may return 0 or -1 in case of error,
+	 * hence need to check here.
+	 */
+
+	depth = fimc_fmt_depth(ctrl, &cap->fmt);
+	if (depth == 0) {
+		mutex_unlock(&ctrl->v4l2_lock);
+		fimc_err("%s: Invalid pixel format\n", __func__);
+		return -EINVAL;
+	} else if (depth < 0) {
+		/*
+		 * When the pixelformat is JPEG,
+		 * the application is requesting for data
+		 * in JPEG compressed format
+		*/
+		cap->fmt.colorspace = V4L2_COLORSPACE_JPEG;
+		mbus_fmt->code = V4L2_MBUS_FMT_JPEG_1X8;
+	} else {
+		cap->fmt.bytesperline = (cap->fmt.width * depth) >> 3;
+		cap->fmt.sizeimage = (cap->fmt.bytesperline * cap->fmt.height);
+		mbus_fmt->code = V4L2_MBUS_FMT_VYUY8_2X8;
+	}
+	mbus_fmt->colorspace = cap->fmt.colorspace;
+
+
+	if (cap->fmt.colorspace == V4L2_COLORSPACE_JPEG) {
+		ctrl->sc.bypass = 1;
+		cap->lastirq = 0;
+		fimc_info1("fimc_s_fmt_vid_capture V4L2_COLORSPACE_JPEG\n");
+	} else {
+		ctrl->sc.bypass = 0;
+		cap->lastirq = 0;
+	}
+
+	fimc_info1("s_fmt width = %d, height = %d\n", \
+				cap->fmt.width, cap->fmt.height);
+
+	/* WriteBack doesn't have subdev_call */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B)) {
+		mutex_unlock(&ctrl->v4l2_lock);
+		return 0;
+	}
+
+#ifdef CONFIG_MACH_S2PLUS
+	if (ctrl->id == FIMC0)
+#else
+	if (ctrl->id != FIMC2)
+#endif
+		ret = subdev_call(ctrl, video, s_mbus_fmt, mbus_fmt);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+	printk(KERN_INFO "%s -- FIMC%d\n", __func__, ctrl->id);
+
+	return ret;
+}
+
+int fimc_try_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
+{
+	/* Not implement */
+	return -ENOTTY;
+}
+
+static int fimc_alloc_buffers(struct fimc_control *ctrl,
+				int plane, int size, int align, int bpp, int use_paddingbuf)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	int i, j;
+	int plane_length[4] = {0, };
+	if (plane < 1 || plane > 3)
+		return -ENOMEM;
+
+	switch (plane) {
+	case 1:
+		if (align) {
+			plane_length[0] = PAGE_ALIGN((size*bpp) >> 3);
+			plane_length[1] = 0;
+			plane_length[2] = 0;
+		} else {
+			plane_length[0] = (size*bpp) >> 3;
+			plane_length[1] = 0;
+			plane_length[2] = 0;
+		}
+		break;
+		/* In case of 2, only NV12 and NV12T is supported. */
+	case 2:
+		if (align) {
+			plane_length[0] = PAGE_ALIGN((size*8) >> 3);
+			plane_length[1] = PAGE_ALIGN((size*(bpp-8)) >> 3);
+			plane_length[2] = 0;
+			fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
+					, plane_length[0], plane_length[1]);
+		} else {
+			plane_length[0] = ((size*8) >> 3);
+			plane_length[1] = ((size*(bpp-8)) >> 3);
+			plane_length[2] = 0;
+			fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
+					, plane_length[0], plane_length[1]);
+		}
+
+		break;
+		/* In case of 3
+		 * YUV422 : 8 / 4 / 4 (bits)
+		 * YUV420 : 8 / 2 / 2 (bits)
+	 * 3rd plane have to consider page align for mmap */
+	case 3:
+		if (align) {
+			plane_length[0] = (size*8) >> 3;
+			plane_length[1] = (size*((bpp-8)/2)) >> 3;
+			plane_length[2] = PAGE_ALIGN((size*bpp)>>3) - plane_length[0] - plane_length[1];
+		} else {
+			plane_length[0] = (size*8) >> 3;
+			plane_length[1] = (size*((bpp-8)/2)) >> 3;
+			plane_length[2] = ((size*bpp)>>3) - plane_length[0] - plane_length[1];
+		}
+		break;
+	default:
+		fimc_err("impossible!\n");
+		return -ENOMEM;
+	}
+
+	if (use_paddingbuf)
+		plane_length[3] = 16;
+	else
+		plane_length[3] = 0;
+
+	for (i = 0; i < cap->nr_bufs; i++) {
+		for (j = 0; j < plane; j++) {
+			cap->bufs[i].length[j] = plane_length[j];
+			fimc_dma_alloc(ctrl, &cap->bufs[i], j, align);
+
+			if (!cap->bufs[i].base[j])
+				goto err_alloc;
+		}
+		if (use_paddingbuf) {
+			cap->bufs[i].length[3] = plane_length[3];
+			fimc_dma_alloc(ctrl, &cap->bufs[i], 3, align);
+
+			if (!cap->bufs[i].base[3])
+				goto err_alloc;
+		}
+		cap->bufs[i].state = VIDEOBUF_PREPARED;
+	}
+
+	return 0;
+
+err_alloc:
+	for (i = 0; i < cap->nr_bufs; i++) {
+		for (j = 0; j < plane; j++) {
+			if (cap->bufs[i].base[j])
+				fimc_dma_free(ctrl, &cap->bufs[i], j);
+		}
+		if (use_paddingbuf) {
+			if (cap->bufs[i].base[3])
+				fimc_dma_free(ctrl, &cap->bufs[i], 3);
+		}
+		memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
+	}
+
+	return -ENOMEM;
+}
+
+static void fimc_free_buffers(struct fimc_control *ctrl)
+{
+	struct fimc_capinfo *cap;
+	int i;
+
+	if (ctrl && ctrl->cap)
+		cap = ctrl->cap;
+	else
+		return;
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
+		cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+	}
+
+	ctrl->mem.curr = ctrl->mem.base;
+}
+
+int fimc_reqbufs_capture(void *fh, struct v4l2_requestbuffers *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+	int ret = 0, i;
+	int bpp = 0;
+	int size = 0;
+
+	if (!cap) {
+		fimc_err("%s: no capture device info\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/*  A count value of zero frees all buffers */
+	if ((b->count == 0) || (b->count >= FIMC_CAPBUFS)) {
+		/* aborting or finishing any DMA in progress */
+		if (ctrl->status == FIMC_STREAMON)
+			fimc_streamoff_capture(fh);
+		for (i = 0; i < FIMC_CAPBUFS; i++) {
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 2);
+		}
+
+		mutex_unlock(&ctrl->v4l2_lock);
+		return 0;
+	}
+	/* free previous buffers */
+	if ((cap->nr_bufs >= 0) && (cap->nr_bufs < FIMC_CAPBUFS)) {
+		fimc_info1("%s : remained previous buffer count is %d\n", __func__,
+				cap->nr_bufs);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			fimc_dma_free(ctrl, &cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &cap->bufs[i], 2);
+		}
+	}
+	fimc_free_buffers(ctrl);
+
+	cap->nr_bufs = b->count;
+	if (pdata->hw_ver >= 0x51) {
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_OFF) {
+			pm_runtime_get_sync(&pdev->dev);
+			/*vcm_set_pgtable_base(ctrl->vcm_id);*/
+		}
+#endif
+		fimc_hw_reset_output_buf_sequence(ctrl);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			fimc_hwset_output_buf_sequence(ctrl, i, 1);
+			cap->bufs[i].id = i;
+			cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+
+			/* initialize list */
+			INIT_LIST_HEAD(&cap->bufs[i].list);
+		}
+		fimc_info1("%s: requested %d buffers\n", __func__, b->count);
+		fimc_info1("%s: sequence[%d]\n", __func__, fimc_hwget_output_buf_sequence(ctrl));
+		INIT_LIST_HEAD(&cap->outgoing_q);
+	}
+	if (pdata->hw_ver < 0x51) {
+		INIT_LIST_HEAD(&cap->inq);
+		for (i = 0; i < cap->nr_bufs; i++) {
+			cap->bufs[i].id = i;
+			cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
+
+			/* initialize list */
+			INIT_LIST_HEAD(&cap->bufs[i].list);
+		}
+	}
+
+	bpp = fimc_fmt_depth(ctrl, &cap->fmt);
+
+	switch (cap->fmt.pixelformat) {
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:		/* fall through */
+	case V4L2_PIX_FMT_YVYU:		/* fall through */
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:		/* fall through */
+		fimc_info1("%s : 1plane\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 1,
+			cap->fmt.width * cap->fmt.height, SZ_4K, bpp, 0);
+		break;
+
+	case V4L2_PIX_FMT_NV21:
+		fimc_info1("%s : 2plane for NV21 w %d h %d\n", __func__, cap->fmt.width, cap->fmt.height);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			cap->fmt.width * cap->fmt.height, 0, bpp, 0);
+		break;
+
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+		fimc_info1("%s : 2plane for NV12\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			cap->fmt.width * cap->fmt.height, SZ_64K, bpp, 0);
+		break;
+
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+		fimc_info1("%s : 2plane for NV12T\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 2,
+			ALIGN(cap->fmt.width, 128) * ALIGN(cap->fmt.height, 32), SZ_64K, bpp, 0);
+		break;
+
+	case V4L2_PIX_FMT_YUV422P:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		fimc_info1("%s : 3plane\n", __func__);
+		ret = fimc_alloc_buffers(ctrl, 3,
+			cap->fmt.width * cap->fmt.height, 0, bpp, 0);
+		break;
+
+	case V4L2_PIX_FMT_JPEG:
+		fimc_info1("%s : JPEG 1plane\n", __func__);
+		size = fimc_camera_get_jpeg_memsize(ctrl);
+		fimc_info2("%s : JPEG 1plane size = %x\n",
+			 __func__, size);
+		ret = fimc_alloc_buffers(ctrl, 1,
+			size, 0, 8, 0);
+		break;
+	default:
+		break;
+	}
+
+	if (ret) {
+		fimc_err("%s: no memory for capture buffer\n", __func__);
+		mutex_unlock(&ctrl->v4l2_lock);
+		return -ENOMEM;
+	}
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_querybuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+
+	if (ctrl->status != FIMC_STREAMOFF) {
+		fimc_err("fimc is running\n");
+		return -EBUSY;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+
+	switch (cap->fmt.pixelformat) {
+	case V4L2_PIX_FMT_JPEG:		/* fall through */
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:		/* fall through */
+	case V4L2_PIX_FMT_YVYU:		/* fall through */
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:		/* fall through */
+		b->length = cap->bufs[b->index].length[0];
+		break;
+
+	case V4L2_PIX_FMT_NV21:
+		b->length = ctrl->cap->bufs[b->index].length[0]
+			+ ctrl->cap->bufs[b->index].length[1];
+		break;
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		b->length = ALIGN(ctrl->cap->bufs[b->index].length[0], SZ_64K)
+			+ ALIGN(ctrl->cap->bufs[b->index].length[1], SZ_64K);
+		break;
+	case V4L2_PIX_FMT_YUV422P:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		b->length = ctrl->cap->bufs[b->index].length[0]
+			+ ctrl->cap->bufs[b->index].length[1]
+			+ ctrl->cap->bufs[b->index].length[2];
+		break;
+
+	default:
+		b->length = cap->bufs[b->index].length[0];
+		break;
+	}
+	b->m.offset = b->index * PAGE_SIZE;
+	/* memory field should filled V4L2_MEMORY_MMAP */
+	b->memory = V4L2_MEMORY_MMAP;
+
+	ctrl->cap->bufs[b->index].state = VIDEOBUF_IDLE;
+
+	fimc_dbg("%s: %d bytes with offset: %d\n",
+		__func__, b->length, b->m.offset);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_ctrl_capture(void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = fh;
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	switch (c->id) {
+	case V4L2_CID_ROTATION:
+		c->value = ctrl->cap->rotate;
+		break;
+
+	case V4L2_CID_HFLIP:
+		c->value = (ctrl->cap->flip & FIMC_XFLIP) ? 1 : 0;
+		break;
+
+	case V4L2_CID_VFLIP:
+		c->value = (ctrl->cap->flip & FIMC_YFLIP) ? 1 : 0;
+		break;
+
+	case V4L2_CID_CACHEABLE:
+		c->value = ctrl->cap->cacheable;
+		break;
+
+	default:
+		/* get ctrl supported by subdev */
+		/* WriteBack doesn't have subdev_call */
+		if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+			break;
+		ret = subdev_call(ctrl, core, g_ctrl, c);
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_g_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+	printk(KERN_INFO "%s++\n", __func__);
+
+	/* try on subdev */
+	ret = subdev_call(ctrl, core, g_ext_ctrls, c);
+
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return ret;
+}
+
+int fimc_s_ctrl_capture(void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_global *fimc = get_fimc_dev();
+	int ret = 0;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam || !ctrl->cap ){
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+		if (!ctrl->cam->sd) {
+			fimc_err("%s: No subdevice.\n", __func__);
+			return -ENODEV;
+		}
+	}
+
+	switch (c->id) {
+	case V4L2_CID_CAM_UPDATE_FW:
+		if (fimc->mclk_status == CAM_MCLK_ON) {
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+
+			mdelay(5);
+		}
+
+		if ((clk_get_rate(ctrl->cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
+			clk_set_rate(ctrl->cam->clk, ctrl->cam->clk_rate);
+			clk_enable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_ON;
+			fimc_info1("clock for camera: %d\n", ctrl->cam->clk_rate);
+
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(1);
+		}
+
+		if (c->value == FW_MODE_UPDATE)
+			ret = subdev_call(ctrl, core, load_fw);
+		else
+			ret = subdev_call(ctrl, core, s_ctrl, c);
+		break;
+
+	case V4L2_CID_CAMERA_RESET:
+		fimc_warn("reset the camera sensor\n");
+		if (ctrl->cam->initialized) {
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+			ctrl->cam->initialized = 0;
+#if defined(CONFIG_MACH_PX)
+			/* 5ms -> 100ms: increase delay.
+			 * There are cases that sensor doesn't get revived
+			 * inspite of doing power reset.*/
+			msleep(100);
+#else
+			msleep(5);
+#endif
+		}
+		ret = fimc_init_camera(ctrl);
+		break;
+
+	case V4L2_CID_ROTATION:
+		ctrl->cap->rotate = c->value;
+		break;
+
+	case V4L2_CID_HFLIP:
+		if (c->value)
+			ctrl->cap->flip |= FIMC_XFLIP;
+		else
+			ctrl->cap->flip &= ~FIMC_XFLIP;
+		break;
+
+	case V4L2_CID_VFLIP:
+		if (c->value)
+			ctrl->cap->flip |= FIMC_YFLIP;
+		else
+			ctrl->cap->flip &= ~FIMC_YFLIP;
+		break;
+
+	case V4L2_CID_PADDR_Y:
+		if (ctrl->cap->bufs)
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_Y];
+		break;
+
+	case V4L2_CID_PADDR_CB:		/* fall through */
+	case V4L2_CID_PADDR_CBCR:
+		if (ctrl->cap->bufs)
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_CB];
+		break;
+
+	case V4L2_CID_PADDR_CR:
+		if (ctrl->cap->bufs)
+			c->value = ctrl->cap->bufs[c->value].base[FIMC_ADDR_CR];
+		break;
+	/* Implementation as per C100 FIMC driver */
+	case V4L2_CID_STREAM_PAUSE:
+		fimc_hwset_stop_processing(ctrl);
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_APPLY:
+		ctrl->fe.ie_on = c->value ? 1 : 0;
+		ctrl->fe.ie_after_sc = 0;
+		ret = fimc_hwset_image_effect(ctrl);
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_FN:
+		if (c->value < 0 || c->value > FIMC_EFFECT_FIN_SILHOUETTE)
+			return -EINVAL;
+		ctrl->fe.fin = c->value;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_CB:
+		ctrl->fe.pat_cb = c->value & 0xFF;
+		ret = 0;
+		break;
+
+	case V4L2_CID_IMAGE_EFFECT_CR:
+		ctrl->fe.pat_cr = c->value & 0xFF;
+		ret = 0;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		ctrl->cap->movie_mode = c->value;
+		ret = subdev_call(ctrl, core, s_ctrl, c);
+#if defined(CONFIG_VIDEO_HD_SUPPORT)
+		printk(KERN_INFO "%s: CAMERA_SENSOR_MODE=%d\n",
+				__func__, c->value);
+		if (!ctrl->cam->initialized)
+			ret = fimc_init_camera(ctrl);
+#endif /* CONFIG_VIDEO_HD_SUPPORT */
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		ctrl->cap->vt_mode = c->value;
+		ret = subdev_call(ctrl, core, s_ctrl, c);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+#ifdef CONFIG_MACH_PX
+		/* if camera type is MIPI,
+		 * we does not do any subdev_calll */
+		if ((ctrl->cam->type == CAM_TYPE_MIPI) ||
+		    (ctrl->cap->dtp_mode == c->value)) {
+#else
+		if (ctrl->cap->dtp_mode == c->value) {
+#endif
+			ret = 0;
+			break;
+		} else {
+			if (c->value == 0 && ctrl->cam->initialized) {
+				/* need to reset after dtp test is finished */
+				fimc_warn("DTP: reset the camera sensor\n");
+				if (ctrl->cam->cam_power)
+					ctrl->cam->cam_power(0);
+
+				/* shutdown the MCLK */
+				clk_disable(ctrl->cam->clk);
+				fimc->mclk_status = CAM_MCLK_OFF;
+				ctrl->cam->initialized = 0;
+
+				msleep(100);
+				ret = fimc_init_camera(ctrl);
+			}
+			ctrl->cap->dtp_mode = c->value;
+		}
+		ret = subdev_call(ctrl, core, s_ctrl, c);
+		break;
+
+	case V4L2_CID_CACHEABLE:
+		ctrl->cap->cacheable = c->value;
+		ret = 0;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_OUTPUT_SIZE:
+		ctrl->cap->sensor_output_width = (u32)c->value >> 16;
+		ctrl->cap->sensor_output_height = (u32)c->value & 0x0FFFF;
+		break;
+
+	default:
+		/* try on subdev */
+		/* WriteBack doesn't have subdev_call */
+
+		if ((ctrl->cam->id == CAMERA_WB) || \
+			 (ctrl->cam->id == CAMERA_WB_B))
+			break;
+#ifdef CONFIG_MACH_S2PLUS
+		if (FIMC0 == ctrl->id)
+#else
+		if (FIMC2 != ctrl->id)
+#endif
+			ret = subdev_call(ctrl, core, s_ctrl, c);
+		else
+			ret = 0;
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_s_ext_ctrls_capture(void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = 0;
+	mutex_lock(&ctrl->v4l2_lock);
+
+	/* try on subdev */
+	ret = subdev_call(ctrl, core, s_ext_ctrls, c);
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return ret;
+}
+
+int fimc_cropcap_capture(void *fh, struct v4l2_cropcap *a)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_global *fimc = get_fimc_dev();
+	struct s3c_platform_fimc *pdata;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam || !ctrl->cam->sd || !ctrl->cap) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+	mutex_lock(&ctrl->v4l2_lock);
+
+	pdata = to_fimc_plat(ctrl->dev);
+	if (!ctrl->cam)
+		ctrl->cam = fimc->camera[pdata->default_cam];
+
+	if (!cap) {
+		cap = kzalloc(sizeof(*cap), GFP_KERNEL);
+		if (!cap) {
+			fimc_err("%s: no memory for "
+				"capture device info\n", __func__);
+			return -ENOMEM;
+		}
+
+		/* assign to ctrl */
+		ctrl->cap = cap;
+	}
+
+	/* crop limitations */
+	cap->cropcap.bounds.left = 0;
+	cap->cropcap.bounds.top = 0;
+	cap->cropcap.bounds.width = ctrl->cam->width;
+	cap->cropcap.bounds.height = ctrl->cam->height;
+
+	/* crop default values */
+	cap->cropcap.defrect.left = 0;
+	cap->cropcap.defrect.top = 0;
+	cap->cropcap.defrect.width = ctrl->cam->width;
+	cap->cropcap.defrect.height = ctrl->cam->height;
+
+	a->bounds = cap->cropcap.bounds;
+	a->defrect = cap->cropcap.defrect;
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_g_crop_capture(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = fh;
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	a->c = ctrl->cap->crop;
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_s_crop_capture(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = fh;
+
+	fimc_dbg("%s\n", __func__);
+
+	mutex_lock(&ctrl->v4l2_lock);
+	ctrl->cap->crop = a->c;
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_start_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->sc.bypass)
+		fimc_hwset_start_scaler(ctrl);
+
+	fimc_hwset_enable_capture(ctrl, ctrl->sc.bypass);
+
+	return 0;
+}
+
+int fimc_stop_capture(struct fimc_control *ctrl)
+{
+	fimc_dbg("%s\n", __func__);
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+		if (!ctrl->cam->sd) {
+			fimc_err("%s: No subdevice.\n", __func__);
+			return -ENODEV;
+		}
+	}
+
+	if (!ctrl->cap) {
+		fimc_err("%s: No cappure format.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cap->lastirq) {
+		fimc_hwset_enable_lastirq(ctrl);
+		fimc_hwset_disable_capture(ctrl);
+		fimc_hwset_disable_lastirq(ctrl);
+	} else {
+		fimc_hwset_disable_capture(ctrl);
+	}
+
+	fimc_hwset_stop_scaler(ctrl);
+
+	return 0;
+}
+
+
+int fimc_streamon_capture(void *fh)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_global *fimc = get_fimc_dev();
+	struct v4l2_frmsizeenum cam_frmsize;
+
+	int rot = 0, i;
+	int ret = 0;
+	struct s3c_platform_camera *cam = NULL;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	unsigned int inner_elapsed_usec = 0;
+
+	printk(KERN_INFO "%s fimc%d\n", __func__, ctrl->id);
+	cam_frmsize.discrete.width = 0;
+	cam_frmsize.discrete.height = 0;
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+		if (!ctrl->cam->sd) {
+			fimc_err("%s: No subdevice.\n", __func__);
+			return -ENODEV;
+		}
+	}
+
+	if (pdata->hw_ver < 0x51)
+		fimc_hw_reset_camera(ctrl);
+#if (!defined(CONFIG_EXYNOS_DEV_PD) && !defined(CONFIG_PM_RUNTIME))
+	ctrl->status = FIMC_READY_ON;
+#endif
+	cap->irq = 0;
+
+	fimc_hwset_enable_irq(ctrl, 0, 1);
+
+	if (!ctrl->cam->initialized) {
+			ret = fimc_init_camera(ctrl);
+		if (unlikely(ret < 0)) {
+			fimc_err("%s: fail to initialize subdev\n", __func__);
+			return ret;
+		}
+	}
+
+	/* csi control position change because runtime pm */
+	if (ctrl->cam)
+		cam = ctrl->cam;
+
+	if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+#ifdef CONFIG_MACH_S2PLUS
+		if (ctrl->id == FIMC0) {
+#else
+		if (ctrl->id != FIMC2) {
+#endif
+			ret = subdev_call(ctrl, video, enum_framesizes, &cam_frmsize);
+			if (ret < 0) {
+				dev_err(ctrl->dev, "%s: enum_framesizes failed\n", __func__);
+				if (ret != -ENOIOCTLCMD)
+					return ret;
+			} else {
+#ifdef CONFIG_TARGET_LOCALE_KOR
+				if ((ctrl->cap->vt_mode != 0) &&
+#else
+				if ((ctrl->cap->vt_mode == 1) &&
+#endif
+						(cap->rotate == 90 || cap->rotate == 270)) {
+					ctrl->cam->window.left = 136;
+					ctrl->cam->window.top = 0;
+					ctrl->cam->window.width = 368;
+					ctrl->cam->window.height = 480;
+					ctrl->cam->width = cam_frmsize.discrete.width;
+					ctrl->cam->height = cam_frmsize.discrete.height;
+					dev_err(ctrl->dev, "vtmode = %d, rotate = %d,"
+						" cam->width = %d,"
+						" cam->height = %d\n", ctrl->cap->vt_mode, cap->rotate,
+						 ctrl->cam->width, ctrl->cam->height);
+				} else {
+					if (cam_frmsize.discrete.width > 0 && cam_frmsize.discrete.height > 0) {
+						ctrl->cam->window.left = 0;
+						ctrl->cam->window.top = 0;
+						ctrl->cam->width = ctrl->cam->window.width = cam_frmsize.discrete.width;
+						ctrl->cam->height = ctrl->cam->window.height = cam_frmsize.discrete.height;
+						fimc_info2("enum_framesizes width = %d, height = %d\n",
+								ctrl->cam->width, ctrl->cam->height);
+					}
+				}
+			}
+
+			if (cam->type == CAM_TYPE_MIPI) {
+				/*
+				 * subdev call for sleep/wakeup:
+				 * no error although no s_stream api support
+				*/
+#if defined(CONFIG_MACH_PX)
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+				v4l2_subdev_call(cam->sd, video, s_stream,
+						STREAM_MODE_WAIT_OFF);
+#endif /* CONFIG_VIDEO_IMPROVE_STREAMOFF */
+#else /* CONFIG_MACH_PX */
+				if (fimc->active_camera == 0) {
+					if (cap->fmt.priv != V4L2_PIX_FMT_MODE_PREVIEW) {
+						v4l2_subdev_call(cam->sd, video, s_stream,
+								STREAM_MODE_CAM_ON);
+					}
+				} else {
+					do_gettimeofday(&ctrl->curr_time);
+					inner_elapsed_usec = \
+						(ctrl->curr_time.tv_sec - ctrl->before_time.tv_sec) * USEC_PER_SEC \
+						+ ctrl->curr_time.tv_usec - ctrl->before_time.tv_usec;
+					inner_elapsed_usec = inner_elapsed_usec / 1000;
+
+					/* printk(KERN_INFO "\n\nfront cam stream off remain time = %dms\n",
+								inner_elapsed_usec);*/
+
+					if (150 > inner_elapsed_usec) {
+						/*printk(KERN_INFO "front cam stream off added msleep = %dms\n",
+							150 - inner_elapsed_usec);*/
+						msleep(150 - inner_elapsed_usec);
+					}
+				}
+#endif
+				if (cam->id == CAMERA_CSI_C) {
+					s3c_csis_start(CSI_CH_0, cam->mipi_lanes, cam->mipi_settle, \
+						cam->mipi_align, cam->width, cam->height, cap->fmt.pixelformat);
+				} else {
+					s3c_csis_start(CSI_CH_1, cam->mipi_lanes, cam->mipi_settle, \
+						cam->mipi_align, cam->width, cam->height, cap->fmt.pixelformat);
+				}
+#if defined(CONFIG_MACH_PX)
+				v4l2_subdev_call(cam->sd, video, s_stream,
+					STREAM_MODE_CAM_ON);
+#else /* CONFIG_MACH_PX */
+				if (fimc->active_camera == 0) {
+					if (cap->fmt.priv == V4L2_PIX_FMT_MODE_PREVIEW) {
+						v4l2_subdev_call(cam->sd, video, s_stream,
+								STREAM_MODE_CAM_ON);
+					}
+				} else {
+					v4l2_subdev_call(cam->sd, video, s_stream,
+							STREAM_MODE_CAM_ON);
+				}
+#endif
+			} else {
+				subdev_call(ctrl, video, s_stream, STREAM_MODE_CAM_ON);
+			}
+		} else {
+			if (cap->fmt.priv != V4L2_PIX_FMT_MODE_HDR)
+				v4l2_subdev_call(cam->sd, video, s_stream, STREAM_MODE_MOVIE_ON);
+		}
+	}
+
+	/* Set FIMD to write back */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B)) {
+		if (ctrl->cam->id == CAMERA_WB)
+			fimc_hwset_sysreg_camblk_fimd0_wb(ctrl);
+		else
+			fimc_hwset_sysreg_camblk_fimd1_wb(ctrl);
+
+		s3cfb_direct_ioctl(0, S3CFB_SET_WRITEBACK, 1);
+	}
+
+	fimc_hwset_camera_type(ctrl);
+	fimc_hwset_camera_polarity(ctrl);
+	fimc_hwset_enable_lastend(ctrl);
+
+	if (cap->fmt.pixelformat != V4L2_PIX_FMT_JPEG) {
+		fimc_hwset_camera_source(ctrl);
+		fimc_hwset_camera_offset(ctrl);
+
+		fimc_capture_scaler_info(ctrl);
+		fimc_hwset_prescaler(ctrl, &ctrl->sc);
+		fimc_hwset_scaler(ctrl, &ctrl->sc);
+		fimc_hwset_output_colorspace(ctrl, cap->fmt.pixelformat);
+		fimc_hwset_output_addr_style(ctrl, cap->fmt.pixelformat);
+
+		if (cap->fmt.pixelformat == V4L2_PIX_FMT_RGB32 ||
+			cap->fmt.pixelformat == V4L2_PIX_FMT_RGB565)
+			fimc_hwset_output_rgb(ctrl, cap->fmt.pixelformat);
+		else
+			fimc_hwset_output_yuv(ctrl, cap->fmt.pixelformat);
+
+		fimc_hwset_output_area(ctrl, cap->fmt.width, cap->fmt.height);
+		fimc_hwset_output_scan(ctrl, &cap->fmt);
+
+		fimc_hwset_output_rot_flip(ctrl, cap->rotate, cap->flip);
+		rot = fimc_mapping_rot_flip(cap->rotate, cap->flip);
+
+		if (rot & FIMC_ROT) {
+#ifndef CONFIG_VIDEO_CONFERENCE_CALL
+			if (cap->fmt.width > cap->fmt.height)
+				fimc_hwset_org_output_size(ctrl,
+					cap->fmt.width, cap->fmt.width);
+			else
+				fimc_hwset_org_output_size(ctrl,
+					cap->fmt.height, cap->fmt.height);
+
+			fimc_hwset_output_size(ctrl, cap->fmt.height, cap->fmt.width);
+#else
+			/* Fix codes 110723 */
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+			fimc_hwset_output_size(ctrl,
+				cap->fmt.height, cap->fmt.width);
+#endif
+		} else {
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+			fimc_hwset_output_size(ctrl, cap->fmt.width, cap->fmt.height);
+		}
+
+		fimc_hwset_jpeg_mode(ctrl, false);
+	} else {
+		fimc_hwset_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+		if (rot & FIMC_ROT)
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.height, cap->fmt.width);
+		else
+			fimc_hwset_org_output_size(ctrl,
+				cap->fmt.width, cap->fmt.height);
+
+		fimc_hwset_output_area_size(ctrl, fimc_camera_get_jpeg_memsize(ctrl));
+		fimc_hwset_jpeg_mode(ctrl, true);
+	}
+
+	if (pdata->hw_ver >= 0x51) {
+		for (i = 0; i < cap->nr_bufs; i++)
+			fimc_hwset_output_address(ctrl, &cap->bufs[i], i);
+	} else {
+		for (i = 0; i < FIMC_PINGPONG; i++)
+			fimc_add_outqueue(ctrl, i);
+	}
+
+	if (ctrl->cap->fmt.colorspace == V4L2_COLORSPACE_JPEG) {
+		fimc_hwset_scaler_bypass(ctrl);
+	}
+
+	ctrl->cap->cnt = 0;
+	fimc_start_capture(ctrl);
+	ctrl->status = FIMC_STREAMON;
+	printk(KERN_INFO "%s-- fimc%d\n", __func__, ctrl->id);
+
+	/* if available buffer did not remained */
+	return 0;
+}
+
+int fimc_streamoff_capture(void *fh)
+{
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	printk(KERN_INFO "%s fimc%d\n", __func__, ctrl->id);
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id != CAMERA_WB_B)) {
+		if (!ctrl->cam->sd) {
+			fimc_err("%s: No subdevice.\n", __func__);
+			return -ENODEV;
+		}
+	}
+
+	ctrl->status = FIMC_READY_OFF;
+
+	fimc_stop_capture(ctrl);
+
+#if defined(CONFIG_MACH_PX)
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+#ifdef CONFIG_MACH_S2PLUS
+	if ((ctrl->id == FIMC0) && (ctrl->cam->type == CAM_TYPE_MIPI))
+#else
+	if ((ctrl->id != FIMC2) && (ctrl->cam->type == CAM_TYPE_MIPI))
+#endif
+		v4l2_subdev_call(ctrl->cam->sd, video, s_stream,
+			STREAM_MODE_CAM_OFF);
+#endif /* CONFIG_VIDEO_IMPROVE_STREAMOFF */
+#else /* CONFIG_MACH_PX */
+	if (get_fimc_dev()->active_camera == 1)
+		v4l2_subdev_call(ctrl->cam->sd, video, s_stream, STREAM_MODE_CAM_OFF);
+
+	do_gettimeofday(&ctrl->before_time);
+#endif
+
+	/* wait for stop hardware */
+	fimc_wait_disable_capture(ctrl);
+
+	fimc_hwset_disable_irq(ctrl);
+	if (pdata->hw_ver < 0x51)
+		INIT_LIST_HEAD(&cap->inq);
+
+	ctrl->status = FIMC_STREAMOFF;
+#ifdef CONFIG_MACH_S2PLUS
+	if (ctrl->id == FIMC0) {
+#else
+	if (ctrl->id != FIMC2) {
+#endif
+		if (ctrl->cam->type == CAM_TYPE_MIPI) {
+			if (ctrl->cam->id == CAMERA_CSI_C)
+				s3c_csis_stop(CSI_CH_0);
+			else
+				s3c_csis_stop(CSI_CH_1);
+		}
+
+#if defined(CONFIG_MACH_PX)
+#ifndef CONFIG_VIDEO_IMPROVE_STREAMOFF
+		v4l2_subdev_call(ctrl->cam->sd, video, s_stream,
+				STREAM_MODE_CAM_OFF);
+#endif /* CONFIG_VIDEO_IMPROVE_STREAMOFF */
+#else /* CONFIG_MACH_PX */
+		if (get_fimc_dev()->active_camera == 0)
+			v4l2_subdev_call(ctrl->cam->sd, video, s_stream, STREAM_MODE_CAM_OFF);
+#endif
+		fimc_hwset_reset(ctrl);
+	} else {
+		fimc_hwset_reset(ctrl);
+		if (cap->fmt.priv != V4L2_PIX_FMT_MODE_HDR)
+			v4l2_subdev_call(ctrl->cam->sd, video, s_stream, STREAM_MODE_MOVIE_OFF);
+	}
+
+	/* Set FIMD to write back */
+	if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
+		s3cfb_direct_ioctl(0, S3CFB_SET_WRITEBACK, 0);
+
+	/* disable camera power */
+	/* cam power off should call in the subdev release function */
+	if (ctrl->cam->reset_camera) {
+		if (ctrl->cam->cam_power)
+			ctrl->cam->cam_power(0);
+		if (ctrl->power_status != FIMC_POWER_SUSPEND)
+			ctrl->cam->initialized = 0;
+	}
+
+	printk(KERN_INFO "%s -- fimc%d\n", __func__, ctrl->id);
+	return 0;
+}
+
+int fimc_qbuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = fh;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	struct fimc_capinfo *cap = ctrl->cap;
+
+	if (!cap || !ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (b->memory != V4L2_MEMORY_MMAP) {
+		fimc_err("%s: invalid memory type\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->v4l2_lock);
+	if (pdata->hw_ver >= 0x51) {
+		if (cap->bufs[b->index].state != VIDEOBUF_IDLE) {
+			fimc_err("%s: invalid state b->index : %d\n", __func__,
+					b->index);
+			mutex_unlock(&ctrl->v4l2_lock);
+			return -EINVAL;
+		} else {
+			fimc_info2("%s[%d] : b->index : %d\n", __func__, ctrl->id,
+					b->index);
+			fimc_hwset_output_buf_sequence(ctrl, b->index,
+					FIMC_FRAMECNT_SEQ_ENABLE);
+			cap->bufs[b->index].state = VIDEOBUF_QUEUED;
+			if (ctrl->status == FIMC_BUFFER_STOP) {
+				printk(KERN_INFO "fimc_qbuf_capture start fimc%d again\n",
+					ctrl->id);
+				fimc_start_capture(ctrl);
+				ctrl->status = FIMC_STREAMON;
+			}
+		}
+	} else {
+		fimc_add_inqueue(ctrl, b->index);
+	}
+
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_dqbuf_capture(void *fh, struct v4l2_buffer *b)
+{
+	unsigned long spin_flags;
+	struct fimc_control *ctrl = fh;
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *buf;
+	size_t length = 0;
+	int i, pp, ret = 0;
+	phys_addr_t start, end;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	if (!cap || !ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (b->memory != V4L2_MEMORY_MMAP) {
+		fimc_err("%s: invalid memory type\n", __func__);
+		return -EINVAL;
+	}
+
+	if (pdata->hw_ver >= 0x51) {
+		spin_lock_irqsave(&ctrl->outq_lock, spin_flags);
+
+		if (list_empty(&cap->outgoing_q)) {
+			fimc_info2("%s: outgoing_q is empty\n", __func__);
+			spin_unlock_irqrestore(&ctrl->outq_lock, spin_flags);
+			return -EAGAIN;
+		} else {
+			buf = list_first_entry(&cap->outgoing_q, struct fimc_buf_set,
+					list);
+			fimc_info2("%s[%d]: buf->id : %d\n", __func__, ctrl->id,
+					buf->id);
+			b->index = buf->id;
+			buf->state = VIDEOBUF_IDLE;
+
+			list_del(&buf->list);
+		}
+
+		spin_unlock_irqrestore(&ctrl->outq_lock, spin_flags);
+
+	} else {
+		pp = ((fimc_hwget_frame_count(ctrl) + 2) % 4);
+		if (cap->fmt.field == V4L2_FIELD_INTERLACED_TB)
+			pp &= ~0x1;
+		b->index = cap->outq[pp];
+		fimc_info2("%s: buffer(%d) outq[%d]\n", __func__, b->index, pp);
+		ret = fimc_add_outqueue(ctrl, pp);
+		if (ret) {
+			b->index = -1;
+			fimc_err("%s: no inqueue buffer\n", __func__);
+		}
+	}
+
+	if (!cap->cacheable)
+		return ret;
+
+	for (i = 0; i < 3; i++) {
+		if (cap->bufs[b->index].base[i])
+			length += cap->bufs[b->index].length[i];
+		else
+			break;
+	}
+
+	if (length > (unsigned long) L2_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+		outer_flush_all();      /* L2 */
+	} else if (length > (unsigned long) L1_FLUSH_ALL) {
+		flush_cache_all();      /* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			outer_flush_range(start, end);  /* L2 */
+		}
+	} else {
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = cap->bufs[b->index].base[i];
+			phys_addr_t end   = cap->bufs[b->index].base[i] +
+					    cap->bufs[b->index].length[i] - 1;
+
+			if (!start)
+				break;
+
+			dmac_flush_range(phys_to_virt(start), phys_to_virt(end));
+			outer_flush_range(start, end);  /* L2 */
+		}
+	}
+
+	return ret;
+}
+
+int fimc_enum_framesizes(struct file *filp, void *fh, struct v4l2_frmsizeenum *fsize)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int i;
+	u32 index = 0;
+	for (i = 0; i < ARRAY_SIZE(capture_fmts); i++) {
+		if (fsize->pixel_format != capture_fmts[i].pixelformat)
+			continue;
+		if (fsize->index == index) {
+			fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+			/* this is camera sensor's width, height.
+			 * originally this should be filled each file format
+			 */
+			fsize->discrete.width = ctrl->cam->width;
+			fsize->discrete.height = ctrl->cam->height;
+
+			return 0;
+		}
+		index++;
+	}
+
+	return -EINVAL;
+}
+int fimc_enum_frameintervals(struct file *filp, void *fh,
+		struct v4l2_frmivalenum *fival)
+{
+	if (fival->index > 0)
+		return -EINVAL;
+	/* temporary only support 30fps */
+	fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+	fival->discrete.numerator = 1000;
+	fival->discrete.denominator = 30000;
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/fimc/fimc_dev.c b/drivers/media/video/samsung/fimc/fimc_dev.c
new file mode 100644
index 0000000..a0a91cd
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_dev.c
@@ -0,0 +1,2378 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Core file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/poll.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/ctype.h>
+#include <linux/workqueue.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-device.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/delay.h>
+#include <linux/cma.h>
+#include <plat/fimc.h>
+#include <plat/clock.h>
+#include <mach/regs-pmu.h>
+
+#include "fimc.h"
+
+char buf[32];
+struct fimc_global *fimc_dev;
+
+#ifndef CONFIG_VIDEO_FIMC_MIPI
+int s3c_csis_get_pkt(int csis_id, void *pktdata) {}
+#endif
+
+void s3c_fimc_irq_work(struct work_struct *work)
+{
+	struct fimc_control *ctrl = container_of(work, struct fimc_control,
+			work_struct);
+	int ret, irq_cnt;
+
+	irq_cnt = atomic_read(&ctrl->irq_cnt);
+	if (irq_cnt > 0) {
+		do {
+			ret = atomic_dec_and_test((atomic_t *)&ctrl->irq_cnt);
+			if (atomic_read(&ctrl->dev->power.usage_count) > 0)
+				pm_runtime_put_sync(ctrl->dev);
+		} while (ret != 1);
+	}
+}
+
+int fimc_dma_alloc(struct fimc_control *ctrl, struct fimc_buf_set *bs,
+							int i, int align)
+{
+	dma_addr_t end, *curr;
+
+	mutex_lock(&ctrl->lock);
+
+	end = ctrl->mem.base + ctrl->mem.size;
+	curr = &ctrl->mem.curr;
+
+	if (!bs->length[i]) {
+		mutex_unlock(&ctrl->lock);
+		return -EINVAL;
+	}
+
+	if (!align) {
+		if (*curr + bs->length[i] > end) {
+			goto overflow;
+		} else {
+			bs->base[i] = *curr;
+			bs->garbage[i] = 0;
+			*curr += bs->length[i];
+		}
+	} else {
+		if (ALIGN(*curr, align) + bs->length[i] > end) {
+			goto overflow;
+		} else {
+			bs->base[i] = ALIGN(*curr, align);
+			bs->garbage[i] = ALIGN(*curr, align) - *curr;
+			*curr += (bs->length[i] + bs->garbage[i]);
+		}
+	}
+
+	mutex_unlock(&ctrl->lock);
+
+	return 0;
+
+overflow:
+	bs->base[i] = 0;
+	bs->length[i] = 0;
+	bs->garbage[i] = 0;
+
+	mutex_unlock(&ctrl->lock);
+
+	return -ENOMEM;
+}
+
+void fimc_dma_free(struct fimc_control *ctrl, struct fimc_buf_set *bs, int i)
+{
+	int total = bs->length[i] + bs->garbage[i];
+	mutex_lock(&ctrl->lock);
+
+	if (bs->base[i]) {
+		if (ctrl->mem.curr - total >= ctrl->mem.base)
+			ctrl->mem.curr -= total;
+
+		bs->base[i] = 0;
+		bs->length[i] = 0;
+		bs->garbage[i] = 0;
+	}
+
+	mutex_unlock(&ctrl->lock);
+}
+
+static inline u32 fimc_irq_out_single_buf(struct fimc_control *ctrl,
+					  struct fimc_ctx *ctx)
+{
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF || ctx->status == FIMC_STREAMOFF) {
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMOFF;
+		ctrl->status = FIMC_STREAMOFF;
+
+		return wakeup;
+	}
+	ctx->status = FIMC_STREAMON_IDLE;
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.active.idx);
+	if (ret < 0)
+		fimc_err("%s:Failed: fimc_push_outq\n", __func__);
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		if (ctx_num != ctrl->out->last_ctx) {
+			struct fimc_buf_set buf_set;	/* destination addr */
+			u32 format, width, height, y_size, c_size, rot;
+			int i, cfg;
+
+
+		    	ctx = &ctrl->out->ctx[ctx_num];
+			ctrl->out->last_ctx = ctx->ctx_num;
+			fimc_outdev_set_ctx_param(ctrl, ctx);
+
+			format = ctx->fbuf.fmt.pixelformat;
+			width = ctx->fbuf.fmt.width;
+			height = ctx->fbuf.fmt.height;
+			y_size = width * height;
+			c_size = y_size >> 2;
+			rot = ctx->rotate;
+
+			memset(&buf_set, 0x00, sizeof(buf_set));
+
+			switch (format) {
+				case V4L2_PIX_FMT_RGB32:
+				case V4L2_PIX_FMT_RGB565:
+				case V4L2_PIX_FMT_YUYV:
+					buf_set.base[FIMC_ADDR_Y] =
+						(dma_addr_t)ctx->fbuf.base;
+					break;
+				case V4L2_PIX_FMT_YUV420:
+					buf_set.base[FIMC_ADDR_Y] =
+						(dma_addr_t)ctx->fbuf.base;
+					buf_set.base[FIMC_ADDR_CB] =
+						buf_set.base[FIMC_ADDR_Y] + y_size;
+					buf_set.base[FIMC_ADDR_CR] =
+						buf_set.base[FIMC_ADDR_CB] + c_size;
+					break;
+				case V4L2_PIX_FMT_NV12:
+				case V4L2_PIX_FMT_NV21:
+					buf_set.base[FIMC_ADDR_Y] =
+						(dma_addr_t)ctx->fbuf.base;
+					buf_set.base[FIMC_ADDR_CB] =
+						buf_set.base[FIMC_ADDR_Y] + y_size;
+					break;
+				case V4L2_PIX_FMT_NV12M:
+					buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+					buf_set.base[FIMC_ADDR_CB] =
+						ALIGN(buf_set.base[FIMC_ADDR_Y] + y_size, PAGE_SIZE - 1);
+					break;
+				case V4L2_PIX_FMT_NV12T:
+					if (rot == 0 || rot == 180)
+						fimc_get_nv12t_size(width, height, &y_size, &c_size);
+					else
+						fimc_get_nv12t_size(height, width, &y_size, &c_size);
+					buf_set.base[FIMC_ADDR_Y] =
+						(dma_addr_t)ctx->fbuf.base;
+					buf_set.base[FIMC_ADDR_CB] =
+						buf_set.base[FIMC_ADDR_Y] + y_size;
+					break;
+				default:
+					fimc_err("%s: Invalid pixelformt : %d\n", __func__, format);
+					return -EINVAL;
+			}
+			cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+			for (i = 0; i < FIMC_PHYBUFS; i++) {
+				if (check_bit(cfg, i))
+					fimc_hwset_output_address(ctrl, &buf_set, i);
+			}
+		}
+
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+		ret = fimc_output_set_dst_addr(ctrl, ctx, next);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_output_set_dst_addr\n", __func__);
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_start_camif\n", __func__);
+	} else {	/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_multi_buf(struct fimc_control *ctrl,
+					 struct fimc_ctx *ctx)
+{
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF) {
+		if (ctrl->out->idxs.active.ctx == ctx->ctx_num) {
+			ctrl->out->idxs.active.ctx = -1;
+			ctrl->out->idxs.active.idx = -1;
+		}
+
+		ctx->status = FIMC_STREAMOFF;
+
+		return wakeup;
+	}
+	ctx->status = FIMC_STREAMON_IDLE;
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.active.idx);
+	if (ret < 0)
+		fimc_err("%s:Failed: fimc_push_outq\n", __func__);
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		if (ctx_num != ctrl->out->last_ctx) {
+			ctx = &ctrl->out->ctx[ctx_num];
+			ctrl->out->last_ctx = ctx->ctx_num;
+			fimc_outdev_set_ctx_param(ctrl, ctx);
+		}
+
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+		ret = fimc_output_set_dst_addr(ctrl, ctx, next);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_output_set_dst_addr\n", __func__);
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_start_camif\n", __func__);
+
+	} else {	/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_dma(struct fimc_control *ctrl,
+				   struct fimc_ctx *ctx)
+{
+	struct fimc_buf_set buf_set;
+	int idx = ctrl->out->idxs.active.idx;
+	int ret = -1, i, ctx_num, next;
+	int cfg;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF
+			|| ctx->status == FIMC_STREAMOFF) {
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMOFF;
+		ctrl->status = FIMC_STREAMOFF;
+		return wakeup;
+	}
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, idx);
+	if (ret < 0)
+		fimc_err("Failed: fimc_push_outq\n");
+
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ADDR,
+			(unsigned long)ctx->dst[idx].base[FIMC_ADDR_Y]);
+
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_ADDR) fail\n");
+			return -EINVAL;
+		}
+
+		if (ctrl->fb.is_enable == 0) {
+			ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ON,
+							(unsigned long)NULL);
+			if (ret < 0) {
+				fimc_err("direct_ioctl(S3CFB_SET_WIN_ON)"\
+						" fail\n");
+				return -EINVAL;
+			}
+
+			ctrl->fb.is_enable = 1;
+		}
+	}
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		ctx = &ctrl->out->ctx[ctx_num];
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+
+		memset(&buf_set, 0x00, sizeof(buf_set));
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[next].base[FIMC_ADDR_Y];
+
+		cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+		for (i = 0; i < FIMC_PHYBUFS; i++) {
+			if (check_bit(cfg, i))
+				fimc_hwset_output_address(ctrl, &buf_set, i);
+		}
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("Fail: fimc_start_camif\n");
+
+	} else {		/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_fimd(struct fimc_control *ctrl,
+				    struct fimc_ctx *ctx)
+{
+	struct fimc_idx prev;
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 0;
+
+	/* Attach done buffer to outgoing queue. */
+	if (ctrl->out->idxs.prev.idx != -1) {
+		ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.prev.idx);
+		if (ret < 0) {
+			fimc_err("Failed: fimc_push_outq\n");
+		} else {
+			ctrl->out->idxs.prev.ctx = -1;
+			ctrl->out->idxs.prev.idx = -1;
+			wakeup = 1;	/* To wake up fimc_v4l2_dqbuf */
+		}
+	}
+
+	/* Update index structure. */
+	if (ctrl->out->idxs.next.idx != -1) {
+		ctrl->out->idxs.active.ctx = ctrl->out->idxs.next.ctx;
+		ctrl->out->idxs.active.idx = ctrl->out->idxs.next.idx;
+		ctrl->out->idxs.next.idx = -1;
+		ctrl->out->idxs.next.ctx = -1;
+	}
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) { /* There is a buffer in incomming queue. */
+		prev.ctx = ctrl->out->idxs.active.ctx;
+		prev.idx = ctrl->out->idxs.active.idx;
+
+		ctrl->out->idxs.prev.ctx = prev.ctx;
+		ctrl->out->idxs.prev.idx = prev.idx;
+
+		ctrl->out->idxs.next.ctx = ctx_num;
+		ctrl->out->idxs.next.idx = next;
+
+		/* set source address */
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+	}
+
+	return wakeup;
+}
+
+static inline void fimc_irq_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	u32 wakeup = 1;
+	int ctx_num = ctrl->out->idxs.active.ctx;
+
+	/* Interrupt pendding clear */
+	fimc_hwset_clear_irq(ctrl);
+
+	/* check context num */
+	if (ctx_num < 0 || ctx_num >= FIMC_MAX_CTXS) {
+		fimc_err("fimc_irq_out: invalid ctx (ctx=%d)\n", ctx_num);
+		wake_up(&ctrl->wq);
+		return;
+	}
+
+	ctx = &ctrl->out->ctx[ctx_num];
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_NONE_SINGLE_BUF:
+		wakeup = fimc_irq_out_single_buf(ctrl, ctx);
+		break;
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		wakeup = fimc_irq_out_multi_buf(ctrl, ctx);
+		break;
+	case FIMC_OVLY_DMA_AUTO:	/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		wakeup = fimc_irq_out_dma(ctrl, ctx);
+		break;
+	case FIMC_OVLY_FIFO:
+		if (ctx->status != FIMC_READY_OFF)
+			wakeup = fimc_irq_out_fimd(ctrl, ctx);
+		break;
+	default:
+		fimc_err("[ctx=%d] fimc_irq_out: wrong overlay.mode (%d)\n",
+				ctx_num, ctx->overlay.mode);
+		break;
+	}
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	atomic_inc((atomic_t *)&ctrl->irq_cnt);
+	queue_work(ctrl->fimc_irq_wq, &ctrl->work_struct);
+#endif
+
+	if (wakeup == 1)
+		wake_up(&ctrl->wq);
+}
+
+int fimc_hwget_number_of_bits(u32 framecnt_seq)
+{
+	u32 bits = 0;
+	while (framecnt_seq) {
+		framecnt_seq = framecnt_seq & (framecnt_seq - 1);
+		bits++;
+	}
+	return bits;
+}
+
+static int fimc_add_outgoing_queue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *tmp_buf;
+	struct list_head *count;
+
+	spin_lock(&ctrl->outq_lock);
+
+	list_for_each(count, &cap->outgoing_q) {
+		tmp_buf = list_entry(count, struct fimc_buf_set, list);
+		if (tmp_buf->id == i) {
+			fimc_info1("%s: Exist id in outqueue\n", __func__);
+
+			spin_unlock(&ctrl->outq_lock);
+			return 0;
+		}
+	}
+	list_add_tail(&cap->bufs[i].list, &cap->outgoing_q);
+	spin_unlock(&ctrl->outq_lock);
+
+	return 0;
+}
+
+static inline void fimc_irq_cap(struct fimc_control *ctrl)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	int pp;
+	int buf_index;
+	int framecnt_seq;
+	int available_bufnum;
+	static int is_frame_end_irq;
+	struct v4l2_control is_ctrl;
+	u32 is_fn;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	is_ctrl.id = 0;
+	is_ctrl.value = 0;
+#ifdef DEBUG
+	static struct timeval curr_time, before_time;
+	if (!fimc_cam_use) {
+		do_gettimeofday(&curr_time);
+		printk(KERN_INFO "%s : time : %ld\n", __func__,
+				curr_time.tv_usec - before_time.tv_usec);
+		before_time.tv_usec = curr_time.tv_usec;
+	}
+#endif
+	fimc_hwset_clear_irq(ctrl);
+	if (fimc_hwget_overflow_state(ctrl)) {
+		ctrl->restart = true;
+		return;
+	}
+
+	if (pdata->hw_ver >= 0x51) {
+		if (is_frame_end_irq || ctrl->status == FIMC_BUFFER_STOP) {
+			pp = fimc_hwget_present_frame_count(ctrl);
+			is_frame_end_irq = 0;
+		} else {
+			pp = fimc_hwget_before_frame_count(ctrl);
+		}
+
+		if (cap->cnt < 20) {
+			printk(KERN_INFO "%s[%d], fimc%d, cnt[%d]\n", __func__,
+							pp, ctrl->id, cap->cnt);
+			cap->cnt++;
+		}
+
+		fimc_info2("%s[%d]\n", __func__, pp);
+		if (pp == 0 || ctrl->restart) {
+			printk(KERN_INFO "%s[%d] SKIPPED\n", __func__, pp);
+			if (ctrl->cap->nr_bufs == 1) {
+				fimc_stop_capture(ctrl);
+				is_frame_end_irq = 1;
+				ctrl->status = FIMC_BUFFER_STOP;
+			}
+			ctrl->restart = false;
+			return;
+		}
+
+		buf_index = pp - 1;
+		if (ctrl->cam->use_isp && fimc_cam_use) {
+			is_ctrl.id = V4L2_CID_IS_GET_FRAME_NUMBER;
+			is_ctrl.value = 0;
+			v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
+			is_fn = is_ctrl.value;
+			if (ctrl->is.frame_count == is_fn) {
+				is_ctrl.id = V4L2_CID_IS_GET_FRAME_VALID;
+				is_ctrl.value = 0;
+				v4l2_subdev_call(ctrl->is.sd, core, g_ctrl,
+					&is_ctrl);
+				if (is_ctrl.value) {
+					is_ctrl.id =
+						V4L2_CID_IS_SET_FRAME_VALID;
+					is_ctrl.value = 0;
+					v4l2_subdev_call(ctrl->is.sd,
+						core, s_ctrl, &is_ctrl);
+				} else {
+					fimc_info2(
+					"Invalid frame - fn %d\n", is_fn);
+					is_ctrl.id =
+						V4L2_CID_IS_SET_FRAME_VALID;
+					is_ctrl.value = 0;
+					v4l2_subdev_call(ctrl->is.sd,
+						core, s_ctrl, &is_ctrl);
+				}
+				ctrl->is.frame_count++;
+			} else {
+			/* Frame lost case */
+				is_ctrl.id =
+					V4L2_CID_IS_GET_LOSTED_FRAME_NUMBER;
+				is_ctrl.value = 0;
+				v4l2_subdev_call(ctrl->is.sd,
+					core, g_ctrl, &is_ctrl);
+				fimc_info2("%d Frame lost - %d,%d",
+					(is_ctrl.value-ctrl->is.frame_count),
+					ctrl->is.frame_count, is_ctrl.value);
+				ctrl->is.frame_count = is_ctrl.value;
+				is_ctrl.id = V4L2_CID_IS_CLEAR_FRAME_NUMBER;
+				is_ctrl.value = ctrl->is.frame_count;
+				v4l2_subdev_call(ctrl->is.sd,
+					core, s_ctrl, &is_ctrl);
+			}
+		}
+
+		if (cap->pktdata_enable) {
+			if (ctrl->cam->id == CAMERA_CSI_C)
+				s3c_csis_get_pkt(CSI_CH_0 , cap->bufs[buf_index].vaddr_pktdata);
+			else if (ctrl->cam->id == CAMERA_CSI_D)
+				s3c_csis_get_pkt(CSI_CH_1 , cap->bufs[buf_index].vaddr_pktdata);
+		}
+
+		fimc_add_outgoing_queue(ctrl, buf_index);
+		fimc_hwset_output_buf_sequence(ctrl, buf_index,
+				FIMC_FRAMECNT_SEQ_DISABLE);
+
+		framecnt_seq = fimc_hwget_output_buf_sequence(ctrl);
+		available_bufnum = fimc_hwget_number_of_bits(framecnt_seq);
+		fimc_info2("%s[%d] : framecnt_seq: %d, available_bufnum: %d\n",
+			__func__, ctrl->id, framecnt_seq, available_bufnum);
+		if (ctrl->status != FIMC_BUFFER_STOP) {
+			if (available_bufnum == 1) {
+				ctrl->cap->lastirq = 0;
+				fimc_stop_capture(ctrl);
+				is_frame_end_irq = 1;
+
+				printk(KERN_INFO "fimc_irq_cap available_bufnum = %d\n", available_bufnum);
+				ctrl->status = FIMC_BUFFER_STOP;
+			}
+		} else {
+			fimc_info1("%s : Aleady fimc stop\n", __func__);
+		}
+	} else
+		pp = ((fimc_hwget_frame_count(ctrl) + 2) % 4);
+
+	if (cap->fmt.field == V4L2_FIELD_INTERLACED_TB) {
+		/* odd value of pp means one frame is made with top/bottom */
+		if (pp & 0x1) {
+			cap->irq = 1;
+			wake_up(&ctrl->wq);
+		}
+	} else {
+		cap->irq = 1;
+		wake_up(&ctrl->wq);
+	}
+}
+
+static irqreturn_t fimc_irq(int irq, void *dev_id)
+{
+	struct fimc_control *ctrl = (struct fimc_control *) dev_id;
+	struct s3c_platform_fimc *pdata;
+
+	if (ctrl->cap)
+		fimc_irq_cap(ctrl);
+	else if (ctrl->out)
+		fimc_irq_out(ctrl);
+	else {
+		printk(KERN_ERR "%s this message must not be shown!!!"
+				" fimc%d\n", __func__, (int)dev_id);
+		pdata = to_fimc_plat(ctrl->dev);
+		pdata->clk_on(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+		fimc_hwset_clear_irq(ctrl);
+		pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct fimc_control *fimc_register_controller(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	struct resource *res;
+	int id, err;
+	struct cma_info mem_info;
+	struct clk *sclk_fimc_lclk = NULL;
+	struct clk *fimc_src_clk = NULL;
+
+	id = pdev->id;
+	pdata = to_fimc_plat(&pdev->dev);
+
+	ctrl = get_fimc_ctrl(id);
+	ctrl->id = id;
+	ctrl->dev = &pdev->dev;
+	ctrl->vd = &fimc_video_device[id];
+	ctrl->vd->minor = id;
+	ctrl->log = FIMC_LOG_DEFAULT;
+	ctrl->power_status = FIMC_POWER_OFF;
+
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	sprintf(ctrl->cma_name, "%s", FIMC_CMA_NAME);
+	ctrl->mem.size = 0;
+	ctrl->mem.base = 0;
+#else
+	/* CMA */
+#ifdef CONFIG_ION_EXYNOS
+	/* In Midas project, FIMC2 reserve memory is used by ION driver. */
+	if (id != 2) {
+#endif
+		sprintf(ctrl->cma_name, "%s%d", FIMC_CMA_NAME, ctrl->id);
+		err = cma_info(&mem_info, ctrl->dev, 0);
+		fimc_info1("%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+				"total_size : 0x%x, free_size : 0x%x\n",
+				__func__, mem_info.lower_bound, mem_info.upper_bound,
+				mem_info.total_size, mem_info.free_size);
+		if (err) {
+			fimc_err("%s: get cma info failed\n", __func__);
+			ctrl->mem.size = 0;
+			ctrl->mem.base = 0;
+		} else {
+			ctrl->mem.size = mem_info.total_size;
+			ctrl->mem.base = (dma_addr_t)cma_alloc
+				(ctrl->dev, ctrl->cma_name, (size_t)ctrl->mem.size, 0);
+		}
+#ifdef CONFIG_ION_EXYNOS
+	}
+#endif
+	printk(KERN_DEBUG "ctrl->mem.size = 0x%x\n", ctrl->mem.size);
+	printk(KERN_DEBUG "ctrl->mem.base = 0x%x\n", ctrl->mem.base);
+	ctrl->mem.curr = ctrl->mem.base;
+#endif
+	ctrl->status = FIMC_STREAMOFF;
+
+	switch (pdata->hw_ver) {
+	case 0x40:
+		ctrl->limit = &fimc40_limits[id];
+		break;
+	case 0x43:
+	case 0x45:
+		ctrl->limit = &fimc43_limits[id];
+		break;
+	case 0x50:
+		ctrl->limit = &fimc50_limits[id];
+		break;
+	case 0x51:
+		ctrl->limit = &fimc51_limits[id];
+		break;
+	default:
+		ctrl->limit = &fimc51_limits[id];
+		fimc_err("%s: failed to get HW version\n", __func__);
+		break;
+	}
+
+	sprintf(ctrl->name, "%s%d", FIMC_NAME, id);
+	strcpy(ctrl->vd->name, ctrl->name);
+
+	atomic_set(&ctrl->in_use, 0);
+	mutex_init(&ctrl->lock);
+	mutex_init(&ctrl->v4l2_lock);
+	spin_lock_init(&ctrl->outq_lock);
+	init_waitqueue_head(&ctrl->wq);
+
+	/* get resource for io memory */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		fimc_err("%s: failed to get io memory region\n", __func__);
+		return NULL;
+	}
+
+	/* request mem region */
+	res = request_mem_region(res->start, res->end - res->start + 1,
+			pdev->name);
+	if (!res) {
+		fimc_err("%s: failed to request io memory region\n", __func__);
+		return NULL;
+	}
+
+	/* ioremap for register block */
+	ctrl->regs = ioremap(res->start, res->end - res->start + 1);
+	if (!ctrl->regs) {
+		fimc_err("%s: failed to remap io region\n", __func__);
+		return NULL;
+	}
+
+	if (soc_is_exynos4210())
+		fimc_src_clk = clk_get(&pdev->dev, "mout_mpll");
+	else
+		fimc_src_clk = clk_get(&pdev->dev, "mout_mpll_user");
+
+	if (IS_ERR(fimc_src_clk)) {
+		dev_err(&pdev->dev, "failed to get parent clock\n");
+		iounmap(ctrl->regs);
+		return NULL;
+	}
+
+	sclk_fimc_lclk = clk_get(&pdev->dev, FIMC_CORE_CLK);
+	if (IS_ERR(sclk_fimc_lclk)) {
+		dev_err(&pdev->dev, "failed to get sclk_fimc_lclk\n");
+		iounmap(ctrl->regs);
+		clk_put(fimc_src_clk);
+		return NULL;
+	}
+
+	if (clk_set_parent(sclk_fimc_lclk, fimc_src_clk)) {
+		dev_err(&pdev->dev, "unable to set parent %s of clock %s.\n",
+				fimc_src_clk->name, sclk_fimc_lclk->name);
+		iounmap(ctrl->regs);
+		clk_put(sclk_fimc_lclk);
+		clk_put(fimc_src_clk);
+		return NULL;
+	}
+	clk_set_rate(sclk_fimc_lclk, FIMC_CLK_RATE);
+	clk_put(sclk_fimc_lclk);
+	clk_put(fimc_src_clk);
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	fimc_hwset_reset(ctrl);
+#endif
+
+	return ctrl;
+}
+
+static int fimc_unregister_controller(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	int id = pdev->id;
+
+	pdata = to_fimc_plat(&pdev->dev);
+	ctrl = get_fimc_ctrl(id);
+
+	if (ctrl->irq)
+		free_irq(ctrl->irq, ctrl);
+	mutex_destroy(&ctrl->lock);
+	mutex_destroy(&ctrl->v4l2_lock);
+
+	if (pdata->clk_off)
+		pdata->clk_off(pdev, &ctrl->clk);
+
+	iounmap(ctrl->regs);
+	memset(ctrl, 0, sizeof(*ctrl));
+
+	return 0;
+}
+
+static void fimc_mmap_open(struct vm_area_struct *vma)
+{
+	struct fimc_global *dev = fimc_dev;
+	int pri_data	= (int)vma->vm_private_data;
+	u32 id		= pri_data / 0x100;
+	u32 ctx		= (pri_data - (id * 0x100)) / 0x10;
+	u32 idx		= pri_data % 0x10;
+
+	BUG_ON(id >= FIMC_DEVICES);
+	BUG_ON(ctx >= FIMC_MAX_CTXS);
+	BUG_ON(idx >= FIMC_OUTBUFS);
+
+	atomic_inc(&dev->ctrl[id].out->ctx[ctx].src[idx].mapped_cnt);
+}
+
+static void fimc_mmap_close(struct vm_area_struct *vma)
+{
+	struct fimc_global *dev = fimc_dev;
+	int pri_data	= (int)vma->vm_private_data;
+	u32 id		= pri_data / 0x100;
+	u32 ctx		= (pri_data - (id * 0x100)) / 0x10;
+	u32 idx		= pri_data % 0x10;
+
+	BUG_ON(id >= FIMC_DEVICES);
+	BUG_ON(ctx >= FIMC_MAX_CTXS);
+	BUG_ON(idx >= FIMC_OUTBUFS);
+
+	atomic_dec(&dev->ctrl[id].out->ctx[ctx].src[idx].mapped_cnt);
+}
+
+static struct vm_operations_struct fimc_mmap_ops = {
+	.open	= fimc_mmap_open,
+	.close	= fimc_mmap_close,
+};
+
+static inline
+int fimc_mmap_out_src(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+	struct fimc_ctx *ctx = &ctrl->out->ctx[ctx_id];
+	u32 start_phy_addr = 0;
+	u32 size = vma->vm_end - vma->vm_start;
+	u32 pfn, idx = vma->vm_pgoff;
+	u32 buf_length = 0;
+	int pri_data = 0;
+
+	buf_length = PAGE_ALIGN(ctx->src[idx].length[FIMC_ADDR_Y] +
+				ctx->src[idx].length[FIMC_ADDR_CB] +
+				ctx->src[idx].length[FIMC_ADDR_CR]);
+	if (size > PAGE_ALIGN(buf_length)) {
+		fimc_err("Requested mmap size is too big\n");
+		return -EINVAL;
+	}
+
+	pri_data = (ctrl->id * 0x100) + (ctx_id * 0x10) + idx;
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_ops = &fimc_mmap_ops;
+	vma->vm_private_data = (void *)pri_data;
+
+	if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) {
+		fimc_err("writable mapping must be shared\n");
+		return -EINVAL;
+	}
+
+	start_phy_addr = ctx->src[idx].base[FIMC_ADDR_Y];
+	pfn = __phys_to_pfn(start_phy_addr);
+
+	if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) {
+		fimc_err("mmap fail\n");
+		return -EINVAL;
+	}
+
+	vma->vm_ops->open(vma);
+
+	ctx->src[idx].flags |= V4L2_BUF_FLAG_MAPPED;
+
+	return 0;
+}
+
+static inline
+int fimc_mmap_out_dst(struct file *filp, struct vm_area_struct *vma, u32 idx)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+	unsigned long pfn = 0, size;
+	int ret = 0;
+
+	size = vma->vm_end - vma->vm_start;
+
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+
+	if (ctrl->out->ctx[ctx_id].dst[idx].base[0])
+		pfn = __phys_to_pfn(ctrl->out->ctx[ctx_id].dst[idx].base[0]);
+	else
+		pfn = __phys_to_pfn(ctrl->mem.curr);
+
+	ret = remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot);
+	if (ret != 0)
+		fimc_err("remap_pfn_range fail.\n");
+
+	return ret;
+}
+
+static inline int fimc_mmap_out(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+	int idx = ctrl->out->ctx[ctx_id].overlay.req_idx;
+	int ret = -1;
+
+	if (idx >= 0)
+		ret = fimc_mmap_out_dst(filp, vma, idx);
+	else if (idx == FIMC_MMAP_IDX)
+		ret = fimc_mmap_out_src(filp, vma);
+
+	return ret;
+}
+
+static inline int fimc_mmap_cap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	u32 size = vma->vm_end - vma->vm_start;
+	u32 pfn, idx = vma->vm_pgoff;
+
+	if (!ctrl->cap->cacheable)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	vma->vm_flags |= VM_RESERVED;
+
+	/*
+	 * page frame number of the address for a source frame
+	 * to be stored at.
+	 */
+	pfn = __phys_to_pfn(ctrl->cap->bufs[idx].base[0]);
+
+	if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) {
+		fimc_err("%s: writable mapping must be shared\n", __func__);
+		return -EINVAL;
+	}
+
+	if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) {
+		fimc_err("%s: mmap fail\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ret;
+
+	if (ctrl->cap)
+		ret = fimc_mmap_cap(filp, vma);
+	else
+		ret = fimc_mmap_out(filp, vma);
+
+	return ret;
+}
+
+static u32 fimc_poll(struct file *filp, poll_table *wait)
+{
+	struct fimc_prv_data *prv_data =
+		(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	u32 mask = 0;
+
+	if (!cap)
+		return 0;
+
+	if (!list_empty(&cap->outgoing_q))
+		mask = POLLIN | POLLRDNORM;
+	else
+		poll_wait(filp, &ctrl->wq, wait);
+
+	return mask;
+}
+
+static
+ssize_t fimc_read(struct file *filp, char *buf, size_t count, loff_t *pos)
+{
+	return 0;
+}
+
+static
+ssize_t fimc_write(struct file *filp, const char *b, size_t c, loff_t *offset)
+{
+	return 0;
+}
+
+u32 fimc_mapping_rot_flip(u32 rot, u32 flip)
+{
+	u32 ret = 0;
+
+	switch (rot) {
+	case 0:
+		if (flip & FIMC_XFLIP)
+			ret |= FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret |= FIMC_YFLIP;
+		break;
+
+	case 90:
+		ret = FIMC_ROT;
+		if (flip & FIMC_XFLIP)
+			ret |= FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret |= FIMC_YFLIP;
+		break;
+
+	case 180:
+		ret = (FIMC_XFLIP | FIMC_YFLIP);
+		if (flip & FIMC_XFLIP)
+			ret &= ~FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret &= ~FIMC_YFLIP;
+		break;
+
+	case 270:
+		ret = (FIMC_XFLIP | FIMC_YFLIP | FIMC_ROT);
+		if (flip & FIMC_XFLIP)
+			ret &= ~FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret &= ~FIMC_YFLIP;
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
+{
+	if (src >= tar * 64) {
+		return -EINVAL;
+	} else if (src >= tar * 32) {
+		*ratio = 32;
+		*shift = 5;
+	} else if (src >= tar * 16) {
+		*ratio = 16;
+		*shift = 4;
+	} else if (src >= tar * 8) {
+		*ratio = 8;
+		*shift = 3;
+	} else if (src >= tar * 4) {
+		*ratio = 4;
+		*shift = 2;
+	} else if (src >= tar * 2) {
+		*ratio = 2;
+		*shift = 1;
+	} else {
+		*ratio = 1;
+		*shift = 0;
+	}
+
+	return 0;
+}
+
+void fimc_get_nv12t_size(int img_hres, int img_vres,
+				int *y_size, int *cb_size)
+{
+	int remain;
+	int y_hres_byte, y_vres_byte;
+	int cb_hres_byte, cb_vres_byte;
+	int y_hres_roundup, y_vres_roundup;
+	int cb_hres_roundup, cb_vres_roundup;
+
+	/* to make 'img_hres and img_vres' be 16 multiple */
+	remain = img_hres % 16;
+	if (remain != 0) {
+		remain = 16 - remain;
+		img_hres = img_hres + remain;
+	}
+	remain = img_vres % 16;
+	if (remain != 0) {
+		remain = 16 - remain;
+		img_vres = img_vres + remain;
+	}
+
+	cb_hres_byte = img_hres;
+	cb_vres_byte = img_vres;
+
+	y_hres_byte = img_hres - 1;
+	y_vres_byte = img_vres - 1;
+	y_hres_roundup = ((y_hres_byte >> 4) >> 3) + 1;
+	y_vres_roundup = ((y_vres_byte >> 4) >> 2) + 1;
+	if ((y_vres_byte & 0x20) == 0) {
+		y_hres_byte = y_hres_byte & 0x7f00;
+		y_hres_byte = y_hres_byte >> 8;
+		y_hres_byte = y_hres_byte & 0x7f;
+
+		y_vres_byte = y_vres_byte & 0x7fc0;
+		y_vres_byte = y_vres_byte >> 6;
+		y_vres_byte = y_vres_byte & 0x1ff;
+
+		*y_size = y_hres_byte +\
+		(y_vres_byte * y_hres_roundup) + 1;
+	} else {
+		*y_size = y_hres_roundup * y_vres_roundup;
+	}
+
+	*y_size = *(y_size) << 13;
+
+	cb_hres_byte = img_hres - 1;
+	cb_vres_byte = (img_vres >> 1) - 1;
+	cb_hres_roundup = ((cb_hres_byte >> 4) >> 3) + 1;
+	cb_vres_roundup = ((cb_vres_byte >> 4) >> 2) + 1;
+	if ((cb_vres_byte & 0x20) == 0) {
+		cb_hres_byte = cb_hres_byte & 0x7f00;
+		cb_hres_byte = cb_hres_byte >> 8;
+		cb_hres_byte = cb_hres_byte & 0x7f;
+
+		cb_vres_byte = cb_vres_byte & 0x7fc0;
+		cb_vres_byte = cb_vres_byte >> 6;
+		cb_vres_byte = cb_vres_byte & 0x1ff;
+
+		*cb_size = cb_hres_byte + (cb_vres_byte * cb_hres_roundup) + 1;
+	} else {
+		*cb_size = cb_hres_roundup * cb_vres_roundup;
+	}
+	*cb_size = (*cb_size) << 13;
+
+}
+
+static int fimc_open(struct file *filp)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct fimc_prv_data *prv_data;
+	int in_use, max_use;
+	int ret;
+	int i;
+
+	ctrl = video_get_drvdata(video_devdata(filp));
+	pdata = to_fimc_plat(ctrl->dev);
+
+	mutex_lock(&ctrl->lock);
+
+	in_use = atomic_read(&ctrl->in_use);
+	if (pdata->camera[0])
+		max_use = 1;
+	else
+		max_use = FIMC_MAX_CTXS + 1;
+
+	if (in_use >= max_use) {
+		ret = -EBUSY;
+		goto resource_busy;
+	} else {
+		atomic_inc(&ctrl->in_use);
+		fimc_warn("FIMC%d %d opened.\n",
+			 ctrl->id, atomic_read(&ctrl->in_use));
+	}
+	in_use = atomic_read(&ctrl->in_use);
+
+	prv_data = kzalloc(sizeof(struct fimc_prv_data), GFP_KERNEL);
+	if (!prv_data) {
+		fimc_err("%s: not enough memory\n", __func__);
+		ret = -ENOMEM;
+		goto kzalloc_err;
+	}
+
+	if (in_use == 1) {
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+		if (pdata->clk_on)
+			pdata->clk_on(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+
+		if (pdata->hw_ver == 0x40)
+			fimc_hw_reset_camera(ctrl);
+
+		/* Apply things to interface register */
+		fimc_hwset_reset(ctrl);
+#endif
+		ctrl->fb.open_fifo = s3cfb_open_fifo;
+		ctrl->fb.close_fifo = s3cfb_close_fifo;
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_GET_LCD_WIDTH,
+					(unsigned long)&ctrl->fb.lcd_hres);
+		if (ret < 0) {
+			fimc_err("Fail: S3CFB_GET_LCD_WIDTH\n");
+			goto resource_busy;
+		}
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_GET_LCD_HEIGHT,
+					(unsigned long)&ctrl->fb.lcd_vres);
+		if (ret < 0) {
+			fimc_err("Fail: S3CFB_GET_LCD_HEIGHT\n");
+			goto resource_busy;
+		}
+
+		ctrl->mem.curr = ctrl->mem.base;
+		ctrl->status = FIMC_STREAMOFF;
+	}
+	prv_data->ctrl = ctrl;
+	if (prv_data->ctrl->out != NULL) {
+		for (i = 0; i < FIMC_MAX_CTXS; i++)
+			if (prv_data->ctrl->out->ctx_used[i] == false) {
+				prv_data->ctx_id = i;
+				prv_data->ctrl->out->ctx_used[i] = true;
+				break;
+			}
+	} else {
+		prv_data->ctx_id = in_use - 1;
+	}
+
+	filp->private_data = prv_data;
+
+	mutex_unlock(&ctrl->lock);
+
+	return 0;
+
+kzalloc_err:
+	atomic_dec(&ctrl->in_use);
+
+resource_busy:
+	mutex_unlock(&ctrl->lock);
+	return ret;
+}
+
+static int fimc_release(struct file *filp)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	struct fimc_capinfo *cap;
+	int ctx_id = prv_data->ctx_id;
+	struct s3c_platform_fimc *pdata;
+	struct fimc_overlay_buf *buf;
+	struct mm_struct *mm = current->mm;
+	struct fimc_ctx *ctx;
+	int ret = 0, i;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	pdata = to_fimc_plat(ctrl->dev);
+
+	atomic_dec(&ctrl->in_use);
+
+	if (ctrl->cap && (ctrl->status != FIMC_STREAMOFF))
+		fimc_streamoff_capture((void *)ctrl);
+
+	/* FIXME: turning off actual working camera */
+	if (ctrl->cap && ctrl->cam) {
+		/* Unload the subdev (camera sensor) module,
+		 * reset related status flags */
+		fimc_release_subdev(ctrl);
+		fimc_is_release_subdev(ctrl);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		if (ctrl->power_status == FIMC_POWER_ON)
+			pm_runtime_put_sync(ctrl->dev);
+#endif
+	} else if (ctrl->is.sd) {
+		fimc_is_release_subdev(ctrl);
+	}
+	if (atomic_read(&ctrl->in_use) == 0) {
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+		if (pdata->clk_off) {
+			pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+			ctrl->power_status = FIMC_POWER_OFF;
+		}
+#endif
+	}
+	if (ctrl->out) {
+		if (ctx->status != FIMC_STREAMOFF) {
+			ret = fimc_outdev_stop_streaming(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_stop_streaming\n");
+				return -EINVAL;
+			}
+
+			ret = fimc_init_in_queue(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_init_in_queue\n");
+				return -EINVAL;
+			}
+
+			ret = fimc_init_out_queue(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_init_out_queue\n");
+				return -EINVAL;
+			}
+
+			/* Make all buffers DQUEUED state. */
+			for (i = 0; i < FIMC_OUTBUFS; i++) {
+				ctx->src[i].state = VIDEOBUF_IDLE;
+				ctx->src[i].flags = V4L2_BUF_FLAG_MAPPED;
+			}
+
+			if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+				ctrl->mem.curr = ctx->dst[0].base[FIMC_ADDR_Y];
+
+				for (i = 0; i < FIMC_OUTBUFS; i++) {
+					ctx->dst[i].base[FIMC_ADDR_Y] = 0;
+					ctx->dst[i].length[FIMC_ADDR_Y] = 0;
+
+					ctx->dst[i].base[FIMC_ADDR_CB] = 0;
+					ctx->dst[i].length[FIMC_ADDR_CB] = 0;
+
+					ctx->dst[i].base[FIMC_ADDR_CR] = 0;
+					ctx->dst[i].length[FIMC_ADDR_CR] = 0;
+				}
+			}
+
+			ctx->status = FIMC_STREAMOFF;
+		}
+	}
+
+	if (atomic_read(&ctrl->in_use) == 0) {
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+		if (pdata->clk_off) {
+			pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+			ctrl->power_status = FIMC_POWER_OFF;
+		}
+
+		/* Apply things to interface register */
+		fimc_hwset_reset(ctrl);
+#endif
+	}
+
+	if (ctrl->out) {
+		ctx->is_requested = 0;
+		buf = &ctx->overlay.buf;
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			if (buf->vir_addr[i]) {
+				ret = do_munmap(mm, buf->vir_addr[i],
+						buf->size[i]);
+				if (ret < 0)
+					fimc_err("%s: do_munmap fail\n",
+							__func__);
+			}
+		}
+
+		/* reset inq & outq of context */
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->inq[i] = -1;
+			ctx->outq[i] = -1;
+		}
+
+		if (atomic_read(&ctrl->in_use) == 0) {
+			ctrl->status = FIMC_STREAMOFF;
+			fimc_outdev_init_idxs(ctrl);
+
+			ctrl->mem.curr = ctrl->mem.base;
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+			if (ctrl->mem.base)
+				cma_free(ctrl->mem.base);
+#endif
+			kfree(ctrl->out);
+			ctrl->out = NULL;
+
+			kfree(filp->private_data);
+			filp->private_data = NULL;
+		} else {
+			ctrl->out->ctx_used[ctx_id] = false;
+		}
+	}
+
+	if (ctrl->cap) {
+		cap = ctrl->cap;
+		ctrl->mem.curr = ctrl->mem.base;
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+		if (ctrl->mem.base)
+			cma_free(ctrl->mem.base);
+#endif
+		kfree(filp->private_data);
+		filp->private_data = NULL;
+		if (pdata->hw_ver >= 0x51)
+			INIT_LIST_HEAD(&cap->outgoing_q);
+		for (i = 0; i < FIMC_CAPBUFS; i++) {
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 2);
+		}
+		kfree(ctrl->cap);
+		ctrl->cap = NULL;
+	}
+
+	/*
+	 * Close window for FIMC if window is enabled.
+	 */
+	if (ctrl->fb.is_enable == 1) {
+		fimc_warn("WIN_OFF for FIMC%d\n", ctrl->id);
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_OFF,
+						(unsigned long)NULL);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_OFF) fail\n");
+			return -EINVAL;
+		}
+
+		ctrl->fb.is_enable = 0;
+	}
+
+	fimc_warn("FIMC%d %d released.\n",
+			ctrl->id, atomic_read(&ctrl->in_use));
+
+	return 0;
+}
+
+static const struct v4l2_file_operations fimc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_open,
+	.release	= fimc_release,
+	.ioctl		= video_ioctl2,
+	.read		= fimc_read,
+	.write		= fimc_write,
+	.mmap		= fimc_mmap,
+	.poll		= fimc_poll,
+};
+
+static void fimc_vdev_release(struct video_device *vdev)
+{
+	kfree(vdev);
+}
+
+struct video_device fimc_video_device[FIMC_DEVICES] = {
+	[0] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+	[1] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+	[2] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+#ifdef CONFIG_ARCH_EXYNOS4
+	[3] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+#endif
+};
+
+static int fimc_init_global(struct platform_device *pdev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct s3c_platform_camera *cam;
+	struct clk *srclk;
+	int id, i;
+
+	pdata = to_fimc_plat(&pdev->dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	/* Registering external camera modules. re-arrange order to be sure */
+	for (i = 0; i < FIMC_MAXCAMS; i++) {
+		cam = pdata->camera[i];
+		if (!cam)
+			break;
+		/* WriteBack doesn't need clock setting */
+		if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
+			fimc_dev->camera[i] = cam;
+			fimc_dev->camera_isvalid[i] = 1;
+			fimc_dev->camera[i]->initialized = 0;
+			continue;
+		}
+
+		/* source clk for MCLK*/
+		srclk = clk_get(&pdev->dev, cam->srclk_name);
+		if (IS_ERR(srclk)) {
+			fimc_err("%s: failed to get srclk source\n", __func__);
+			return -EINVAL;
+		}
+
+		/* mclk */
+#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_SLP)
+		cam->clk = clk_get(&pdev->dev, cam->get_clk_name());
+#else
+		cam->clk = clk_get(&pdev->dev, cam->clk_name);
+#endif
+		if (IS_ERR(cam->clk)) {
+			fimc_err("%s: failed to get mclk source\n", __func__);
+			return -EINVAL;
+		}
+
+		if (clk_set_parent(cam->clk, srclk)) {
+			dev_err(&pdev->dev, "unable to set parent %s of clock %s.\n",
+					srclk->name, cam->clk->name);
+			clk_put(srclk);
+			clk_put(cam->clk);
+			return -EINVAL;
+		}
+
+		/* Assign camera device to fimc */
+		fimc_dev->camera[i] = cam;
+		fimc_dev->camera_isvalid[i] = 1;
+		fimc_dev->camera[i]->initialized = 0;
+	}
+
+	fimc_dev->mclk_status = CAM_MCLK_OFF;
+	fimc_dev->active_camera = -1;
+	fimc_dev->initialized = 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRM_EXYNOS_FIMD_WB
+static BLOCKING_NOTIFIER_HEAD(fimc_notifier_client_list);
+
+int fimc_register_client(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(
+			&fimc_notifier_client_list, nb);
+}
+EXPORT_SYMBOL(fimc_register_client);
+
+int fimc_unregister_client(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_unregister(
+			&fimc_notifier_client_list, nb);
+}
+EXPORT_SYMBOL(fimc_unregister_client);
+
+int fimc_send_event(unsigned long val, void *v)
+{
+	return blocking_notifier_call_chain(
+			&fimc_notifier_client_list, val, v);
+}
+#endif
+
+static int fimc_show_log_level(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	int id = -1;
+
+	char temp[150];
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	sprintf(temp, "\t");
+	strcat(buf, temp);
+	if (ctrl->log & FIMC_LOG_DEBUG) {
+		sprintf(temp, "FIMC_LOG_DEBUG | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_INFO_L2) {
+		sprintf(temp, "FIMC_LOG_INFO_L2 | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_INFO_L1) {
+		sprintf(temp, "FIMC_LOG_INFO_L1 | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_WARN) {
+		sprintf(temp, "FIMC_LOG_WARN | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_ERR) {
+		sprintf(temp, "FIMC_LOG_ERR\n");
+		strcat(buf, temp);
+	}
+
+	return strlen(buf);
+}
+
+static int fimc_store_log_level(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t len)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+
+	const char *p = buf;
+	char msg[150] = {0, };
+	int id = -1;
+	u32 match = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	while (*p != '\0') {
+		if (!isspace(*p))
+			strncat(msg, p, 1);
+		p++;
+	}
+
+	ctrl->log = 0;
+	printk(KERN_INFO "FIMC.%d log level is set as below.\n", id);
+
+	if (strstr(msg, "FIMC_LOG_ERR") != NULL) {
+		ctrl->log |= FIMC_LOG_ERR;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_ERR\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_WARN") != NULL) {
+		ctrl->log |= FIMC_LOG_WARN;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_WARN\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_INFO_L1") != NULL) {
+		ctrl->log |= FIMC_LOG_INFO_L1;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_INFO_L1\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_INFO_L2") != NULL) {
+		ctrl->log |= FIMC_LOG_INFO_L2;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_INFO_L2\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_DEBUG") != NULL) {
+		ctrl->log |= FIMC_LOG_DEBUG;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_DEBUG\n");
+	}
+
+	if (!match) {
+		printk(KERN_INFO "FIMC_LOG_ERR	\t: Error condition.\n");
+		printk(KERN_INFO "FIMC_LOG_WARN	\t: WARNING condition.\n");
+		printk(KERN_INFO "FIMC_LOG_INFO_L1 \t: V4L2 API without QBUF, DQBUF.\n");
+		printk(KERN_INFO "FIMC_LOG_INFO_L2 \t: V4L2 API QBUF, DQBUF.\n");
+		printk(KERN_INFO "FIMC_LOG_DEBUG \t: Queue status report.\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(log_level, 0644, fimc_show_log_level, fimc_store_log_level);
+
+static int fimc_show_range_mode(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	int id = -1;
+
+	char temp[150];
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	sprintf(temp, "\t");
+	strcat(buf, temp);
+	if (ctrl->range == FIMC_RANGE_NARROW) {
+		sprintf(temp, "FIMC_RANGE_NARROW\n");
+		strcat(buf, temp);
+	} else {
+		sprintf(temp, "FIMC_RANGE_WIDE\n");
+		strcat(buf, temp);
+	}
+
+	return strlen(buf);
+}
+
+static int fimc_store_range_mode(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t len)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+
+	const char *p = buf;
+	char msg[150] = {0, };
+	int id = -1;
+	u32 match = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	while (*p != '\0') {
+		if (!isspace(*p))
+			strncat(msg, p, 1);
+		p++;
+	}
+
+	ctrl->range = 0;
+	printk(KERN_INFO "FIMC.%d range mode is set as below.\n", id);
+
+	if (strstr(msg, "FIMC_RANGE_WIDE") != NULL) {
+		ctrl->range = FIMC_RANGE_WIDE;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_RANGE_WIDE\n");
+	}
+
+	if (strstr(msg, "FIMC_RANGE_NARROW") != NULL) {
+		ctrl->range = FIMC_RANGE_NARROW;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_RANGE_NARROW\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(range_mode, 0644, \
+			fimc_show_range_mode,
+			fimc_store_range_mode);
+
+static int __devinit fimc_probe(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	int ret;
+
+	if (!fimc_dev) {
+		fimc_dev = kzalloc(sizeof(*fimc_dev), GFP_KERNEL);
+		if (!fimc_dev) {
+			dev_err(&pdev->dev, "%s: not enough memory\n", __func__);
+			return -ENOMEM;
+		}
+	}
+
+	ctrl = fimc_register_controller(pdev);
+	if (!ctrl) {
+		printk(KERN_ERR "%s: cannot register fimc\n", __func__);
+		goto err_alloc;
+	}
+
+	pdata = to_fimc_plat(&pdev->dev);
+	if ((ctrl->id == FIMC0) && (pdata->cfg_gpio))
+		pdata->cfg_gpio(pdev);
+
+	/* V4L2 device-subdev registration */
+	ret = v4l2_device_register(&pdev->dev, &ctrl->v4l2_dev);
+	if (ret) {
+		fimc_err("%s: v4l2 device register failed\n", __func__);
+		goto err_fimc;
+	}
+	ctrl->vd->v4l2_dev = &ctrl->v4l2_dev;
+
+	ctrl->vd->v4l2_dev = &ctrl->v4l2_dev;
+
+	/* things to initialize once */
+	if (!fimc_dev->initialized) {
+		ret = fimc_init_global(pdev);
+		if (ret)
+			goto err_v4l2;
+	}
+
+	/* video device register */
+	ret = video_register_device(ctrl->vd, VFL_TYPE_GRABBER, ctrl->id);
+	if (ret) {
+		fimc_err("%s: cannot register video driver\n", __func__);
+		goto err_v4l2;
+	}
+
+	video_set_drvdata(ctrl->vd, ctrl);
+
+#ifdef CONFIG_VIDEO_FIMC_RANGE_WIDE
+	ctrl->range = FIMC_RANGE_WIDE;
+#else
+	ctrl->range = FIMC_RANGE_NARROW;
+#endif
+
+	ret = device_create_file(&(pdev->dev), &dev_attr_log_level);
+	if (ret < 0) {
+		fimc_err("failed to add sysfs entries for log level\n");
+		goto err_global;
+	}
+	ret = device_create_file(&(pdev->dev), &dev_attr_range_mode);
+	if (ret < 0) {
+		fimc_err("failed to add sysfs entries for range mode\n");
+		goto err_global;
+	}
+	printk(KERN_INFO "FIMC%d registered successfully\n", ctrl->id);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	sprintf(buf, "fimc%d_iqr_wq_name", ctrl->id);
+	ctrl->fimc_irq_wq = create_workqueue(buf);
+	if (ctrl->fimc_irq_wq == NULL) {
+		fimc_err("failed to create_workqueue\n");
+		goto err_global;
+	}
+
+	INIT_WORK(&ctrl->work_struct, s3c_fimc_irq_work);
+	atomic_set(&ctrl->irq_cnt, 0);
+
+	ctrl->power_status = FIMC_POWER_OFF;
+	pm_runtime_enable(&pdev->dev);
+#endif
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* To lock bus frequency in OPP mode */
+	ctrl->bus_dev = dev_get(EXYNOS_BUSFREQ_NAME);
+#endif
+
+	/* irq */
+	ctrl->irq = platform_get_irq(pdev, 0);
+	if (request_irq(ctrl->irq, fimc_irq, IRQF_DISABLED, ctrl->name, ctrl))
+		fimc_err("%s: request_irq failed\n", __func__);
+
+	return 0;
+
+err_global:
+	video_unregister_device(ctrl->vd);
+
+err_v4l2:
+	v4l2_device_unregister(&ctrl->v4l2_dev);
+
+err_fimc:
+	fimc_unregister_controller(pdev);
+
+err_alloc:
+	kfree(fimc_dev);
+	return -EINVAL;
+
+}
+
+static int fimc_remove(struct platform_device *pdev)
+{
+	fimc_unregister_controller(pdev);
+
+	device_remove_file(&(pdev->dev), &dev_attr_log_level);
+
+	kfree(fimc_dev);
+	fimc_dev = NULL;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	pm_runtime_disable(&pdev->dev);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static inline void fimc_suspend_out_ctx(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx)
+{
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_DMA_AUTO:		/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:		/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:		/* fall through */
+	case FIMC_OVLY_NONE_SINGLE_BUF:
+		if (ctx->status == FIMC_STREAMON) {
+			if (ctx->inq[0] != -1)
+				fimc_err("%s : %d in queue unstable\n",
+					__func__, __LINE__);
+
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_SLEEP;
+		} else if (ctx->status == FIMC_STREAMON_IDLE) {
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_IDLE_SLEEP;
+		} else {
+			ctx->status = FIMC_OFF_SLEEP;
+		}
+
+		break;
+	case FIMC_OVLY_FIFO:
+		if (ctx->status == FIMC_STREAMON) {
+			if (ctx->inq[0] != -1)
+				fimc_err("%s: %d in queue unstable\n",
+					 __func__, __LINE__);
+
+			if ((ctrl->out->idxs.next.idx != -1) ||
+			    (ctrl->out->idxs.prev.idx != -1))
+				fimc_err("%s: %d FIMC unstable\n",
+					__func__, __LINE__);
+
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_SLEEP;
+		} else {
+			ctx->status = FIMC_OFF_SLEEP;
+		}
+
+		break;
+	case FIMC_OVLY_NOT_FIXED:
+		ctx->status = FIMC_OFF_SLEEP;
+		break;
+	}
+}
+
+static inline int fimc_suspend_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	int i, on_sleep = 0, idle_sleep = 0, off_sleep = 0;
+
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		ctx = &ctrl->out->ctx[i];
+		fimc_suspend_out_ctx(ctrl, ctx);
+
+		switch (ctx->status) {
+		case FIMC_ON_SLEEP:
+			on_sleep++;
+			break;
+		case FIMC_ON_IDLE_SLEEP:
+			idle_sleep++;
+			break;
+		case FIMC_OFF_SLEEP:
+			off_sleep++;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (on_sleep)
+		ctrl->status = FIMC_ON_SLEEP;
+	else if (idle_sleep)
+		ctrl->status = FIMC_ON_IDLE_SLEEP;
+	else
+		ctrl->status = FIMC_OFF_SLEEP;
+
+	ctrl->out->last_ctx = -1;
+
+	return 0;
+}
+
+static inline int fimc_suspend_cap(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	printk(KERN_INFO "%s\n", __func__);
+	if (ctrl->power_status == FIMC_POWER_ON)
+		pm_runtime_put_sync(&pdev->dev);
+#endif
+
+	if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B)	{
+		fimc_dbg("%s\n", __func__);
+		ctrl->suspend_framecnt = fimc_hwget_output_buf_sequence(ctrl);
+		fimc_streamoff_capture((void *)ctrl);
+		fimc_info1("%s : framecnt_seq : %d\n",
+				__func__, ctrl->suspend_framecnt);
+	} else {
+		if (ctrl->id == FIMC0 && ctrl->cam->initialized) {
+			ctrl->cam->initialized = 0;
+			if (ctrl->cam->use_isp) {
+				printk(KERN_INFO "%s use_isp s_power down\n", __func__);
+				v4l2_subdev_call(ctrl->is.sd, core, s_power, 0);
+			} else
+				v4l2_subdev_call(ctrl->cam->sd, core, s_power, 0);
+
+			if (fimc->mclk_status == CAM_MCLK_ON) {
+				if (ctrl->cam->cam_power)
+					ctrl->cam->cam_power(0);
+				/* shutdown the MCLK */
+				clk_disable(ctrl->cam->clk);
+				fimc->mclk_status = CAM_MCLK_OFF;
+			}
+		}
+	}
+	ctrl->power_status = FIMC_POWER_OFF;
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+int fimc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	int id;
+
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+	pdata = to_fimc_plat(ctrl->dev);
+
+	printk(KERN_INFO "%s\n", __func__);
+	if (ctrl->out)
+		fimc_suspend_out(ctrl);
+
+	else if (ctrl->cap)
+		fimc_suspend_cap(ctrl);
+	else
+		ctrl->status = FIMC_OFF_SLEEP;
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	if (atomic_read(&ctrl->in_use) && pdata->clk_off)
+		pdata->clk_off(pdev, &ctrl->clk);
+#endif
+
+	printk(KERN_INFO "%s--\n", __func__);
+	return 0;
+}
+
+int fimc_suspend_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+	pm_message_t state;
+
+	state.event = 0;
+	pdev = to_platform_device(dev);
+	ret = fimc_suspend(pdev, state);
+
+	return 0;
+}
+
+static inline int fimc_resume_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	int i;
+	u32 state = 0;
+
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		ctx = &ctrl->out->ctx[i];
+		if (ctx->status == FIMC_ON_IDLE_SLEEP) {
+			ctx->status = FIMC_STREAMON_IDLE;
+			state |= FIMC_STREAMON_IDLE;
+		} else if (ctx->status == FIMC_OFF_SLEEP) {
+			ctx->status = FIMC_STREAMOFF;
+			state |= FIMC_STREAMOFF;
+		} else {
+			fimc_err("%s: Abnormal (%d)\n", __func__, ctx->status);
+		}
+	}
+
+	if ((state & FIMC_STREAMON_IDLE) == FIMC_STREAMON_IDLE)
+		ctrl->status = FIMC_STREAMON_IDLE;
+	else
+		ctrl->status = FIMC_STREAMOFF;
+
+	return 0;
+}
+
+static inline int fimc_resume_cap(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	int tmp;
+	u32 timeout;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+#endif
+	printk(KERN_INFO "%s\n", __func__);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (ctrl->power_status == FIMC_POWER_OFF)
+		pm_runtime_get_sync(&pdev->dev);
+#endif
+	__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_CAM_CONF);
+	/*  Wait max 1ms */
+	timeout = 10;
+	while ((__raw_readl(S5P_PMU_CAM_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN)
+	       != S5P_INT_LOCAL_PWR_EN) {
+		if (timeout == 0) {
+			printk(KERN_ERR "Power domain CAM enable failed.\n");
+			break;
+		}
+		timeout--;
+		udelay(100);
+	}
+
+	if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : framecnt_seq : %d\n",
+			   __func__, ctrl->suspend_framecnt);
+		fimc_hwset_output_buf_sequence_all(ctrl,
+						   ctrl->suspend_framecnt);
+		tmp = fimc_hwget_output_buf_sequence(ctrl);
+		fimc_info1("%s : real framecnt_seq : %d\n", __func__, tmp);
+
+		fimc_streamon_capture((void *)ctrl);
+	} else {
+		if (ctrl->id == FIMC0 && ctrl->cam->initialized == 0) {
+			if (!ctrl->cam->use_isp) {
+				clk_set_rate(ctrl->cam->clk, ctrl->cam->clk_rate);
+				clk_enable(ctrl->cam->clk);
+				fimc->mclk_status = CAM_MCLK_ON;
+				fimc_info1("clock for camera: %d\n", ctrl->cam->clk_rate);
+
+				if (ctrl->cam->cam_power)
+					ctrl->cam->cam_power(1);
+
+				v4l2_subdev_call(ctrl->cam->sd, core, s_power, 1);
+				ctrl->cam->initialized = 1;
+			}
+
+		}
+	}
+	/* fimc_streamon_capture((void *)ctrl); */
+	ctrl->power_status = FIMC_POWER_ON;
+	printk(KERN_INFO "%s--\n", __func__);
+
+	return 0;
+}
+
+int fimc_resume(struct platform_device *pdev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	int id = pdev->id;
+
+	ctrl = get_fimc_ctrl(id);
+	pdata = to_fimc_plat(ctrl->dev);
+	printk(KERN_INFO "%s", __func__);
+	if (atomic_read(&ctrl->in_use) && pdata->clk_on)
+		pdata->clk_on(pdev, &ctrl->clk);
+
+	if (ctrl->out)
+		fimc_resume_out(ctrl);
+
+	else if (ctrl->cap)
+		fimc_resume_cap(ctrl);
+	else
+		ctrl->status = FIMC_STREAMOFF;
+
+	printk(KERN_INFO "%s--", __func__);
+	return 0;
+}
+
+int fimc_resume_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = to_platform_device(dev);
+	ret = fimc_resume(pdev);
+	return 0;
+}
+
+
+#else
+#define fimc_suspend		NULL
+#define fimc_resume		NULL
+#define fimc_suspend_pd		NULL
+#define fimc_resume_pd		NULL
+#endif
+
+static int fimc_runtime_suspend_cap(struct fimc_control *ctrl)
+{
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	struct clk *pxl_async = NULL;
+	printk(KERN_INFO "%s FIMC%d\n", __func__, ctrl->id);
+
+	ctrl->power_status = FIMC_POWER_SUSPEND;
+
+	if (ctrl->cap && (ctrl->status != FIMC_STREAMOFF)) {
+		fimc_streamoff_capture((void *)ctrl);
+		ctrl->status = FIMC_STREAMOFF;
+	}
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cam->id == CAMERA_WB) {
+		fimc_info1("%s : writeback 0 suspend\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async0");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_disable(pxl_async);
+		clk_put(pxl_async);
+	} else if (ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : writeback 1 suspend\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_disable(pxl_async);
+		clk_put(pxl_async);
+	}
+	printk(KERN_INFO "%s FIMC%d --\n", __func__, ctrl->id);
+
+	return 0;
+}
+static int fimc_runtime_suspend(struct device *dev)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	struct s3c_platform_fimc *pdata;
+	int id;
+	int ret;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+	pdata = to_fimc_plat(ctrl->dev);
+
+	if (ctrl->out) {
+		fimc_info1("%s: fimc m2m\n", __func__);
+	} else if (ctrl->cap) {
+		fimc_info1("%s: fimc capture\n", __func__);
+		fimc_runtime_suspend_cap(ctrl);
+	} else
+		fimc_err("%s : invalid fimc control\n", __func__);
+
+	if (pdata->clk_off) {
+		ret = pdata->clk_off(pdev, &ctrl->clk);
+		if (ret == 0)
+			ctrl->power_status = FIMC_POWER_OFF;
+	}
+
+	return 0;
+}
+
+static int fimc_runtime_resume_cap(struct fimc_control *ctrl)
+{
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	struct clk *pxl_async = NULL;
+	printk(KERN_INFO "%s FIMC%d\n", __func__, ctrl->id);
+
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cam->id == CAMERA_WB) {
+		fimc_info1("%s : writeback 0 resume\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async0");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+	} else if (ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : writeback 1 resume\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+	}
+	printk(KERN_INFO "%s FIMC%d --\n", __func__, ctrl->id);
+	return 0;
+}
+static int fimc_runtime_resume(struct device *dev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct platform_device *pdev;
+	int id, ret = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	pdata = to_fimc_plat(ctrl->dev);
+	if (pdata->clk_on) {
+		ret = pdata->clk_on(pdev, &ctrl->clk);
+		if (ret == 0)
+			ctrl->power_status = FIMC_POWER_ON;
+	}
+
+	/* if status is FIMC_PROBE, not need to know differlence of out or
+	 * cap */
+
+	if (ctrl->out) {
+		/* do not need to sub function in m2m mode */
+		fimc_info1("%s: fimc m2m\n", __func__);
+	} else if (ctrl->cap) {
+		fimc_info1("%s: fimc cap\n", __func__);
+		fimc_runtime_resume_cap(ctrl);
+	}
+
+	return 0;
+}
+static const struct dev_pm_ops fimc_pm_ops = {
+	.suspend	= fimc_suspend_pd,
+	.resume		= fimc_resume_pd,
+	.runtime_suspend = fimc_runtime_suspend,
+	.runtime_resume = fimc_runtime_resume,
+};
+
+static struct platform_driver fimc_driver = {
+	.probe		= fimc_probe,
+	.remove		= fimc_remove,
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	.suspend	= fimc_suspend,
+	.resume		= fimc_resume,
+#endif
+	.driver		= {
+		.name	= FIMC_NAME,
+		.owner	= THIS_MODULE,
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		.pm = &fimc_pm_ops,
+#else
+		.pm = NULL,
+#endif
+
+	},
+};
+
+static int fimc_register(void)
+{
+	return platform_driver_register(&fimc_driver);
+}
+
+static void fimc_unregister(void)
+{
+	platform_driver_unregister(&fimc_driver);
+}
+
+late_initcall(fimc_register);
+module_exit(fimc_unregister);
+
+MODULE_AUTHOR("Dongsoo,	Kim <dongsoo45.kim@samsung.com>");
+MODULE_AUTHOR("Jinsung,	Yang <jsgood.yang@samsung.com>");
+MODULE_AUTHOR("Jonghun,	Han <jonghun.han@samsung.com>");
+MODULE_DESCRIPTION("Samsung Camera Interface (FIMC) driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimc/fimc_dev_u1.c b/drivers/media/video/samsung/fimc/fimc_dev_u1.c
new file mode 100644
index 0000000..f36db5d
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_dev_u1.c
@@ -0,0 +1,2341 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Core file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/poll.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <media/v4l2-device.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/ctype.h>
+#include <linux/workqueue.h>
+#include <plat/clock.h>
+#if defined(CONFIG_CMA)
+#include <linux/cma.h>
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+#include <plat/media.h>
+#include <mach/media.h>
+#endif
+#include <plat/fimc.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+
+#include <mach/regs-pmu.h>
+#include <linux/delay.h>
+
+#include "fimc.h"
+
+char buf[32];
+struct fimc_global *fimc_dev;
+void __iomem			*qos_regs0 , *qos_regs1;
+
+void s3c_fimc_irq_work(struct work_struct *work)
+{
+	struct fimc_control *ctrl = container_of(work, struct fimc_control,
+			work_struct);
+	int ret, irq_cnt;
+
+	irq_cnt = atomic_read(&ctrl->irq_cnt);
+	if (irq_cnt > 0) {
+		do {
+			ret = atomic_dec_and_test((atomic_t *)&ctrl->irq_cnt);
+			pm_runtime_put_sync(ctrl->dev);
+		} while (ret != 1);
+	}
+}
+
+int fimc_dma_alloc(struct fimc_control *ctrl, struct fimc_buf_set *bs,
+							int i, int align)
+{
+	dma_addr_t end, *curr;
+
+	mutex_lock(&ctrl->lock);
+
+	end = ctrl->mem.base + ctrl->mem.size;
+	curr = &ctrl->mem.curr;
+
+	if (!bs->length[i]) {
+		mutex_unlock(&ctrl->lock);
+		return -EINVAL;
+	}
+
+	if (!align) {
+		if (*curr + bs->length[i] > end) {
+			goto overflow;
+		} else {
+			bs->base[i] = *curr;
+			bs->garbage[i] = 0;
+			*curr += bs->length[i];
+		}
+	} else {
+		if (ALIGN(*curr, align) + bs->length[i] > end) {
+			goto overflow;
+		} else {
+			bs->base[i] = ALIGN(*curr, align);
+			bs->garbage[i] = ALIGN(*curr, align) - *curr;
+			*curr += (bs->length[i] + bs->garbage[i]);
+		}
+	}
+
+	mutex_unlock(&ctrl->lock);
+
+	return 0;
+
+overflow:
+	bs->base[i] = 0;
+	bs->length[i] = 0;
+	bs->garbage[i] = 0;
+
+	mutex_unlock(&ctrl->lock);
+
+	return -ENOMEM;
+}
+
+void fimc_dma_free(struct fimc_control *ctrl, struct fimc_buf_set *bs, int i)
+{
+	int total = bs->length[i] + bs->garbage[i];
+	mutex_lock(&ctrl->lock);
+
+	if (bs->base[i]) {
+		if (ctrl->mem.curr - total >= ctrl->mem.base)
+			ctrl->mem.curr -= total;
+
+		bs->base[i] = 0;
+		bs->length[i] = 0;
+		bs->garbage[i] = 0;
+	}
+
+	mutex_unlock(&ctrl->lock);
+}
+
+static inline u32 fimc_irq_out_single_buf(struct fimc_control *ctrl,
+					  struct fimc_ctx *ctx)
+{
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF || ctx->status == FIMC_STREAMOFF) {
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMOFF;
+		ctrl->status = FIMC_STREAMOFF;
+
+		return wakeup;
+	}
+	ctx->status = FIMC_STREAMON_IDLE;
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.active.idx);
+	if (ret < 0)
+		fimc_err("%s:Failed: fimc_push_outq\n", __func__);
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		if (ctx_num != ctrl->out->last_ctx) {
+			ctx = &ctrl->out->ctx[ctx_num];
+			ctrl->out->last_ctx = ctx->ctx_num;
+			fimc_outdev_set_ctx_param(ctrl, ctx);
+		}
+
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+		ret = fimc_output_set_dst_addr(ctrl, ctx, next);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_output_set_dst_addr\n", __func__);
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_start_camif\n", __func__);
+
+	} else {	/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_multi_buf(struct fimc_control *ctrl,
+					 struct fimc_ctx *ctx)
+{
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF) {
+		if (ctrl->out->idxs.active.ctx == ctx->ctx_num) {
+			ctrl->out->idxs.active.ctx = -1;
+			ctrl->out->idxs.active.idx = -1;
+		}
+
+		ctx->status = FIMC_STREAMOFF;
+
+		return wakeup;
+	}
+	ctx->status = FIMC_STREAMON_IDLE;
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.active.idx);
+	if (ret < 0)
+		fimc_err("%s:Failed: fimc_push_outq\n", __func__);
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		if (ctx_num != ctrl->out->last_ctx) {
+			ctx = &ctrl->out->ctx[ctx_num];
+			ctrl->out->last_ctx = ctx->ctx_num;
+			fimc_outdev_set_ctx_param(ctrl, ctx);
+		}
+
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+		ret = fimc_output_set_dst_addr(ctrl, ctx, next);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_output_set_dst_addr\n", __func__);
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("%s:Fail: fimc_start_camif\n", __func__);
+
+	} else {	/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_dma(struct fimc_control *ctrl,
+				   struct fimc_ctx *ctx)
+{
+	struct fimc_buf_set buf_set;
+	int idx = ctrl->out->idxs.active.idx;
+	int ret = -1, i, ctx_num, next;
+	int cfg;
+	u32 wakeup = 1;
+
+	if (ctx->status == FIMC_READY_OFF
+			|| ctx->status == FIMC_STREAMOFF) {
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctx->status = FIMC_STREAMOFF;
+		ctrl->status = FIMC_STREAMOFF;
+		return wakeup;
+	}
+
+	/* Attach done buffer to outgoing queue. */
+	ret = fimc_push_outq(ctrl, ctx, idx);
+	if (ret < 0)
+		fimc_err("Failed: fimc_push_outq\n");
+
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+			ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ADDR,
+				(unsigned long)ctx->dst[idx].base[FIMC_ADDR_Y]);
+
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_ADDR) fail\n");
+			return -EINVAL;
+		}
+
+		if (ctrl->fb.is_enable == 0) {
+			ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ON,
+							(unsigned long)NULL);
+			if (ret < 0) {
+				fimc_err("direct_ioctl(S3CFB_SET_WIN_ON)"\
+						" fail\n");
+				return -EINVAL;
+			}
+
+			ctrl->fb.is_enable = 1;
+		}
+	}
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) {		/* There is a buffer in incomming queue. */
+		ctx = &ctrl->out->ctx[ctx_num];
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+
+		memset(&buf_set, 0x00, sizeof(buf_set));
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[next].base[FIMC_ADDR_Y];
+
+		cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+		for (i = 0; i < FIMC_PHYBUFS; i++) {
+			if (check_bit(cfg, i))
+				fimc_hwset_output_address(ctrl, &buf_set, i);
+		}
+
+		ctrl->out->idxs.active.ctx = ctx_num;
+		ctrl->out->idxs.active.idx = next;
+
+		ctx->status = FIMC_STREAMON;
+		ctrl->status = FIMC_STREAMON;
+
+		ret = fimc_outdev_start_camif(ctrl);
+		if (ret < 0)
+			fimc_err("Fail: fimc_start_camif\n");
+
+	} else {		/* There is no buffer in incomming queue. */
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+
+		ctx->status = FIMC_STREAMON_IDLE;
+		ctrl->status = FIMC_STREAMON_IDLE;
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		ctrl->out->last_ctx = -1;
+#endif
+	}
+
+	return wakeup;
+}
+
+static inline u32 fimc_irq_out_fimd(struct fimc_control *ctrl,
+				    struct fimc_ctx *ctx)
+{
+	struct fimc_idx prev;
+	int ret = -1, ctx_num, next;
+	u32 wakeup = 0;
+
+	/* Attach done buffer to outgoing queue. */
+	if (ctrl->out->idxs.prev.idx != -1) {
+		ret = fimc_push_outq(ctrl, ctx, ctrl->out->idxs.prev.idx);
+		if (ret < 0) {
+			fimc_err("Failed: fimc_push_outq\n");
+		} else {
+			ctrl->out->idxs.prev.ctx = -1;
+			ctrl->out->idxs.prev.idx = -1;
+			wakeup = 1;	/* To wake up fimc_v4l2_dqbuf */
+		}
+	}
+
+	/* Update index structure. */
+	if (ctrl->out->idxs.next.idx != -1) {
+		ctrl->out->idxs.active.ctx = ctrl->out->idxs.next.ctx;
+		ctrl->out->idxs.active.idx = ctrl->out->idxs.next.idx;
+		ctrl->out->idxs.next.idx = -1;
+		ctrl->out->idxs.next.ctx = -1;
+	}
+
+	/* Detach buffer from incomming queue. */
+	ret = fimc_pop_inq(ctrl, &ctx_num, &next);
+	if (ret == 0) { /* There is a buffer in incomming queue. */
+		prev.ctx = ctrl->out->idxs.active.ctx;
+		prev.idx = ctrl->out->idxs.active.idx;
+
+		ctrl->out->idxs.prev.ctx = prev.ctx;
+		ctrl->out->idxs.prev.idx = prev.idx;
+
+		ctrl->out->idxs.next.ctx = ctx_num;
+		ctrl->out->idxs.next.idx = next;
+
+		/* set source address */
+		fimc_outdev_set_src_addr(ctrl, ctx->src[next].base);
+	}
+
+	return wakeup;
+}
+
+static inline void fimc_irq_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	u32 wakeup = 1;
+	int ctx_num = ctrl->out->idxs.active.ctx;
+
+	/* Interrupt pendding clear */
+	fimc_hwset_clear_irq(ctrl);
+
+	/* check context num */
+	if (ctx_num < 0 || ctx_num >= FIMC_MAX_CTXS) {
+		fimc_err("fimc_irq_out: invalid ctx (ctx=%d)\n", ctx_num);
+		wake_up(&ctrl->wq);
+		return;
+	}
+
+	ctx = &ctrl->out->ctx[ctx_num];
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_NONE_SINGLE_BUF:
+		wakeup = fimc_irq_out_single_buf(ctrl, ctx);
+		break;
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		wakeup = fimc_irq_out_multi_buf(ctrl, ctx);
+		break;
+	case FIMC_OVLY_DMA_AUTO:	/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		wakeup = fimc_irq_out_dma(ctrl, ctx);
+		break;
+	case FIMC_OVLY_FIFO:
+		if (ctx->status != FIMC_READY_OFF)
+			wakeup = fimc_irq_out_fimd(ctrl, ctx);
+		break;
+	default:
+		fimc_err("[ctx=%d] fimc_irq_out: wrong overlay.mode (%d)\n",
+				ctx_num, ctx->overlay.mode);
+		break;
+	}
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	atomic_inc((atomic_t *)&ctrl->irq_cnt);
+	queue_work(ctrl->fimc_irq_wq, &ctrl->work_struct);
+#endif
+
+	if (wakeup == 1)
+		wake_up(&ctrl->wq);
+}
+
+int fimc_hwget_number_of_bits(u32 framecnt_seq)
+{
+	u32 bits = 0;
+	while (framecnt_seq) {
+		framecnt_seq = framecnt_seq & (framecnt_seq - 1);
+		bits++;
+	}
+	return bits;
+}
+
+static int fimc_add_outgoing_queue(struct fimc_control *ctrl, int i)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	struct fimc_buf_set *tmp_buf;
+	struct list_head *count;
+
+	spin_lock(&ctrl->outq_lock);
+
+	list_for_each(count, &cap->outgoing_q) {
+		tmp_buf = list_entry(count, struct fimc_buf_set, list);
+		if (tmp_buf->id == i) {
+			fimc_info1("%s: Exist id in outqueue\n", __func__);
+
+			spin_unlock(&ctrl->outq_lock);
+			return 0;
+		}
+	}
+	list_add_tail(&cap->bufs[i].list, &cap->outgoing_q);
+	spin_unlock(&ctrl->outq_lock);
+
+	return 0;
+}
+
+static inline void fimc_irq_cap(struct fimc_control *ctrl)
+{
+	struct fimc_capinfo *cap = ctrl->cap;
+	int pp;
+	int buf_index;
+	int framecnt_seq;
+	int available_bufnum;
+
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+#ifdef DEBUG
+	static struct timeval curr_time, before_time;
+	if (ctrl->id == FIMC2) {
+		do_gettimeofday(&curr_time);
+		printk(KERN_INFO "%s : time : %ld\n", __func__,
+				curr_time.tv_usec - before_time.tv_usec);
+		before_time.tv_usec = curr_time.tv_usec;
+	}
+#endif
+	fimc_hwset_clear_irq(ctrl);
+	if (fimc_hwget_overflow_state(ctrl))
+		return;
+
+	if (pdata->hw_ver >= 0x51) {
+		pp = fimc_hwget_before_frame_count(ctrl);
+		if (cap->cnt < 20) {
+			printk(KERN_INFO "%s[%d], fimc%d, cnt[%d]\n", __func__,
+							pp, ctrl->id, cap->cnt);
+			cap->cnt++;
+		}
+		if (pp == 0 || cap->cnt == 1) {
+			if (ctrl->cap->nr_bufs == 1)
+				pp = fimc_hwget_present_frame_count(ctrl);
+			else
+				return;
+		}
+		buf_index = pp - 1;
+		fimc_add_outgoing_queue(ctrl, buf_index);
+		fimc_hwset_output_buf_sequence(ctrl, buf_index,
+				FIMC_FRAMECNT_SEQ_DISABLE);
+
+		framecnt_seq = fimc_hwget_output_buf_sequence(ctrl);
+		available_bufnum = fimc_hwget_number_of_bits(framecnt_seq);
+		fimc_info2("%s[%d] : framecnt_seq: %d, available_bufnum: %d\n",
+			__func__, ctrl->id, framecnt_seq, available_bufnum);
+
+		if (ctrl->status != FIMC_BUFFER_STOP) {
+			if (available_bufnum == 1 || ctrl->cap->nr_bufs == 1) {
+				cap->cnt=0;
+				ctrl->cap->lastirq = 0;
+				fimc_stop_capture(ctrl);
+				ctrl->status = FIMC_BUFFER_STOP;
+				printk(KERN_INFO "fimc_irq_cap[%d] available_bufnum = %d\n",
+					ctrl->id, available_bufnum);
+			}
+		} else {
+			fimc_info1("%s : Aleady fimc stop\n", __func__);
+		}
+	} else
+		pp = ((fimc_hwget_frame_count(ctrl) + 2) % 4);
+
+	if (cap->fmt.field == V4L2_FIELD_INTERLACED_TB) {
+		/* odd value of pp means one frame is made with top/bottom */
+		if (pp & 0x1) {
+			cap->irq = 1;
+			wake_up(&ctrl->wq);
+		}
+	} else {
+		cap->irq = 1;
+		wake_up(&ctrl->wq);
+	}
+}
+
+static irqreturn_t fimc_irq(int irq, void *dev_id)
+{
+	struct fimc_control *ctrl = (struct fimc_control *) dev_id;
+	struct s3c_platform_fimc *pdata;
+
+	if (ctrl->cap)
+		fimc_irq_cap(ctrl);
+	else if (ctrl->out)
+		fimc_irq_out(ctrl);
+	else {
+		printk(KERN_ERR "%s this message must not be shown!!!"
+				" fimc%d\n", __func__, ctrl->id);
+		pdata = to_fimc_plat(ctrl->dev);
+		pdata->clk_on(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+		fimc_hwset_clear_irq(ctrl);
+		pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static
+struct fimc_control *fimc_register_controller(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	struct resource *res;
+	int id, err;
+	struct cma_info mem_info;
+	struct clk *sclk_fimc_lclk = NULL;
+	struct clk *fimc_src_clk = NULL;
+
+	id = pdev->id;
+	pdata = to_fimc_plat(&pdev->dev);
+
+	ctrl = get_fimc_ctrl(id);
+	ctrl->id = id;
+	ctrl->dev = &pdev->dev;
+	ctrl->vd = &fimc_video_device[id];
+	ctrl->vd->minor = id;
+	ctrl->log = FIMC_LOG_DEFAULT;
+	ctrl->power_status = FIMC_POWER_OFF;
+
+	/* CMA */
+#ifdef CONFIG_ION_EXYNOS
+	if  (id != 2) {
+#endif
+		sprintf(ctrl->cma_name, "%s%d", FIMC_CMA_NAME, ctrl->id);
+	err = cma_info(&mem_info, ctrl->dev, 0);
+	fimc_info1("%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		fimc_err("%s: get cma info failed\n", __func__);
+		ctrl->mem.size = 0;
+		ctrl->mem.base = 0;
+	} else {
+		ctrl->mem.size = mem_info.total_size;
+		ctrl->mem.base = (dma_addr_t)cma_alloc
+			(ctrl->dev, ctrl->cma_name, (size_t)ctrl->mem.size, 0);
+	}
+#ifdef CONFIG_ION_EXYNOS
+	}
+#endif
+	printk(KERN_INFO "ctrl->mem.size = 0x%x\n", ctrl->mem.size);
+	printk(KERN_INFO "ctrl->mem.base = 0x%x\n", ctrl->mem.base);
+
+	ctrl->mem.curr = ctrl->mem.base;
+	ctrl->status = FIMC_STREAMOFF;
+
+	switch (pdata->hw_ver) {
+	case 0x40:
+		ctrl->limit = &fimc40_limits[id];
+		break;
+	case 0x43:
+	case 0x45:
+		ctrl->limit = &fimc43_limits[id];
+		break;
+	case 0x50:
+		ctrl->limit = &fimc50_limits[id];
+		break;
+	case 0x51:
+		ctrl->limit = &fimc51_limits[id];
+		break;
+	}
+
+	sprintf(ctrl->name, "%s%d", FIMC_NAME, id);
+	strcpy(ctrl->vd->name, ctrl->name);
+
+	atomic_set(&ctrl->in_use, 0);
+	mutex_init(&ctrl->lock);
+	mutex_init(&ctrl->v4l2_lock);
+	spin_lock_init(&ctrl->outq_lock);
+	init_waitqueue_head(&ctrl->wq);
+
+	/* get resource for io memory */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		fimc_err("%s: failed to get io memory region\n", __func__);
+		return NULL;
+	}
+
+	/* request mem region */
+	res = request_mem_region(res->start, res->end - res->start + 1,
+			pdev->name);
+	if (!res) {
+		fimc_err("%s: failed to request io memory region\n", __func__);
+		return NULL;
+	}
+
+	/* ioremap for register block */
+	ctrl->regs = ioremap(res->start, res->end - res->start + 1);
+	if (!ctrl->regs) {
+		fimc_err("%s: failed to remap io region\n", __func__);
+		return NULL;
+	}
+
+	fimc_dev->backup_regs[id] = ctrl->regs;
+	/* irq */
+	ctrl->irq = platform_get_irq(pdev, 0);
+	if (request_irq(ctrl->irq, fimc_irq, IRQF_DISABLED, ctrl->name, ctrl))
+		fimc_err("%s: request_irq failed\n", __func__);
+
+	if (soc_is_exynos4210())
+		fimc_src_clk = clk_get(&pdev->dev, "mout_mpll");
+	else
+		fimc_src_clk = clk_get(&pdev->dev, "mout_mpll_user");
+
+	if (IS_ERR(fimc_src_clk)) {
+		dev_err(&pdev->dev, "failed to get parent clock\n");
+		iounmap(ctrl->regs);
+		return NULL;
+	}
+
+	sclk_fimc_lclk = clk_get(&pdev->dev, FIMC_CORE_CLK);
+	if (IS_ERR(sclk_fimc_lclk)) {
+		dev_err(&pdev->dev, "failed to get sclk_fimc_lclk\n");
+		iounmap(ctrl->regs);
+		clk_put(fimc_src_clk);
+		return NULL;
+	}
+
+	if (clk_set_parent(sclk_fimc_lclk, fimc_src_clk)) {
+		dev_err(&pdev->dev, "unable to set parent %s of clock %s.\n",
+				fimc_src_clk->name, sclk_fimc_lclk->name);
+		iounmap(ctrl->regs);
+		clk_put(sclk_fimc_lclk);
+		clk_put(fimc_src_clk);
+		return NULL;
+	}
+	clk_set_rate(sclk_fimc_lclk, FIMC_CLK_RATE);
+	clk_put(sclk_fimc_lclk);
+	clk_put(fimc_src_clk);
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	fimc_hwset_reset(ctrl);
+#endif
+
+	return ctrl;
+}
+
+static int fimc_unregister_controller(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	int id = pdev->id;
+
+	pdata = to_fimc_plat(&pdev->dev);
+	ctrl = get_fimc_ctrl(id);
+
+	free_irq(ctrl->irq, ctrl);
+	mutex_destroy(&ctrl->lock);
+	mutex_destroy(&ctrl->v4l2_lock);
+
+	if (pdata->clk_off)
+		pdata->clk_off(pdev, &ctrl->clk);
+
+	iounmap(ctrl->regs);
+	memset(ctrl, 0, sizeof(*ctrl));
+
+	return 0;
+}
+
+static void fimc_mmap_open(struct vm_area_struct *vma)
+{
+	struct fimc_global *dev = fimc_dev;
+	int pri_data    = (int)vma->vm_private_data;
+	u32 id          = pri_data / 0x100;
+	u32 ctx         = (pri_data - (id * 0x100)) / 0x10;
+	u32 idx         = pri_data % 0x10;
+
+	BUG_ON(id >= FIMC_DEVICES);
+	BUG_ON(ctx >= FIMC_MAX_CTXS);
+	BUG_ON(idx >= FIMC_OUTBUFS);
+
+	atomic_inc(&dev->ctrl[id].out->ctx[ctx].src[idx].mapped_cnt);
+}
+
+static void fimc_mmap_close(struct vm_area_struct *vma)
+{
+	struct fimc_global *dev = fimc_dev;
+	int pri_data	= (int)vma->vm_private_data;
+	u32 id		= pri_data / 0x100;
+	u32 ctx		= (pri_data - (id * 0x100)) / 0x10;
+	u32 idx		= pri_data % 0x10;
+
+	BUG_ON(id >= FIMC_DEVICES);
+	BUG_ON(ctx >= FIMC_MAX_CTXS);
+	BUG_ON(idx >= FIMC_OUTBUFS);
+
+	atomic_dec(&dev->ctrl[id].out->ctx[ctx].src[idx].mapped_cnt);
+}
+
+static struct vm_operations_struct fimc_mmap_ops = {
+	.open	= fimc_mmap_open,
+	.close	= fimc_mmap_close,
+};
+
+static inline
+int fimc_mmap_out_src(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+	struct fimc_ctx *ctx = &ctrl->out->ctx[ctx_id];
+	u32 start_phy_addr = 0;
+	u32 size = vma->vm_end - vma->vm_start;
+	u32 pfn, idx = vma->vm_pgoff;
+	u32 buf_length = 0;
+	int pri_data = 0;
+
+	buf_length = PAGE_ALIGN(ctx->src[idx].length[FIMC_ADDR_Y] +
+				ctx->src[idx].length[FIMC_ADDR_CB] +
+				ctx->src[idx].length[FIMC_ADDR_CR]);
+	if (size > PAGE_ALIGN(buf_length)) {
+		fimc_err("Requested mmap size is too big\n");
+		return -EINVAL;
+	}
+
+	pri_data = (ctrl->id * 0x100) + (ctx_id * 0x10) + idx;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_ops = &fimc_mmap_ops;
+	vma->vm_private_data = (void *)pri_data;
+
+	if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) {
+		fimc_err("writable mapping must be shared\n");
+		return -EINVAL;
+	}
+
+	start_phy_addr = ctx->src[idx].base[FIMC_ADDR_Y];
+	pfn = __phys_to_pfn(start_phy_addr);
+
+	if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) {
+		fimc_err("mmap fail\n");
+		return -EINVAL;
+	}
+
+	vma->vm_ops->open(vma);
+
+	ctx->src[idx].flags |= V4L2_BUF_FLAG_MAPPED;
+
+	return 0;
+}
+
+static inline
+int fimc_mmap_out_dst(struct file *filp, struct vm_area_struct *vma, u32 idx)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+	unsigned long pfn = 0, size;
+	int ret = 0;
+
+	size = vma->vm_end - vma->vm_start;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+
+	if (ctrl->out->ctx[ctx_id].dst[idx].base[0])
+		pfn = __phys_to_pfn(ctrl->out->ctx[ctx_id].dst[idx].base[0]);
+	else
+		pfn = __phys_to_pfn(ctrl->mem.curr);
+
+	ret = remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot);
+	if (ret != 0)
+		fimc_err("remap_pfn_range fail.\n");
+
+	return ret;
+}
+
+static inline int fimc_mmap_out(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ctx_id = prv_data->ctx_id;
+
+	int idx = ctrl->out->ctx[ctx_id].overlay.req_idx;
+	int ret = -1;
+
+	if (idx >= 0)
+		ret = fimc_mmap_out_dst(filp, vma, idx);
+	else if (idx == FIMC_MMAP_IDX)
+		ret = fimc_mmap_out_src(filp, vma);
+
+	return ret;
+}
+
+static inline int fimc_mmap_cap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	u32 size = vma->vm_end - vma->vm_start;
+	u32 pfn, idx = vma->vm_pgoff;
+
+	if (ctrl->cap->fmt.priv != V4L2_PIX_FMT_MODE_HDR && !ctrl->cap->cacheable)
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+
+	/*
+	 * page frame number of the address for a source frame
+	 * to be stored at.
+	 */
+	pfn = __phys_to_pfn(ctrl->cap->bufs[idx].base[0]);
+
+	if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) {
+		fimc_err("%s: writable mapping must be shared\n", __func__);
+		return -EINVAL;
+	}
+
+	if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) {
+		fimc_err("%s: mmap fail\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	int ret;
+
+	if (ctrl->cap)
+		ret = fimc_mmap_cap(filp, vma);
+	else
+		ret = fimc_mmap_out(filp, vma);
+
+	return ret;
+}
+
+static u32 fimc_poll(struct file *filp, poll_table *wait)
+{
+	struct fimc_prv_data *prv_data =
+		(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	struct fimc_capinfo *cap = ctrl->cap;
+	u32 mask = 0;
+
+	if (!cap)
+		return 0;
+
+	if (!list_empty(&cap->outgoing_q)) {
+		mask = POLLIN | POLLRDNORM;
+		cap->poll_cnt = 0;
+	} else {
+		poll_wait(filp, &ctrl->wq, wait);
+		if (++cap->poll_cnt > 15)
+			fimc_hwset_sw_reset(ctrl);
+	}
+
+	return mask;
+}
+
+static
+ssize_t fimc_read(struct file *filp, char *buf, size_t count, loff_t *pos)
+{
+	return 0;
+}
+
+static
+ssize_t fimc_write(struct file *filp, const char *b, size_t c, loff_t *offset)
+{
+	return 0;
+}
+
+u32 fimc_mapping_rot_flip(u32 rot, u32 flip)
+{
+	u32 ret = 0;
+
+	switch (rot) {
+	case 0:
+		if (flip & FIMC_XFLIP)
+			ret |= FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret |= FIMC_YFLIP;
+		break;
+
+	case 90:
+		ret = FIMC_ROT;
+		if (flip & FIMC_XFLIP)
+			ret |= FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret |= FIMC_YFLIP;
+		break;
+
+	case 180:
+		ret = (FIMC_XFLIP | FIMC_YFLIP);
+		if (flip & FIMC_XFLIP)
+			ret &= ~FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret &= ~FIMC_YFLIP;
+		break;
+
+	case 270:
+		ret = (FIMC_XFLIP | FIMC_YFLIP | FIMC_ROT);
+		if (flip & FIMC_XFLIP)
+			ret &= ~FIMC_XFLIP;
+
+		if (flip & FIMC_YFLIP)
+			ret &= ~FIMC_YFLIP;
+		break;
+	}
+
+	return ret;
+}
+
+int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
+{
+	if (src >= tar * 64) {
+		return -EINVAL;
+	} else if (src >= tar * 32) {
+		*ratio = 32;
+		*shift = 5;
+	} else if (src >= tar * 16) {
+		*ratio = 16;
+		*shift = 4;
+	} else if (src >= tar * 8) {
+		*ratio = 8;
+		*shift = 3;
+	} else if (src >= tar * 4) {
+		*ratio = 4;
+		*shift = 2;
+	} else if (src >= tar * 2) {
+		*ratio = 2;
+		*shift = 1;
+	} else {
+		*ratio = 1;
+		*shift = 0;
+	}
+
+	return 0;
+}
+
+void fimc_get_nv12t_size(int img_hres, int img_vres,
+				int *y_size, int *cb_size)
+{
+	int remain;
+	int y_hres_byte, y_vres_byte;
+	int cb_hres_byte, cb_vres_byte;
+	int y_hres_roundup, y_vres_roundup;
+	int cb_hres_roundup, cb_vres_roundup;
+
+	/* to make 'img_hres and img_vres' be 16 multiple */
+	remain = img_hres % 16;
+	if (remain != 0) {
+		remain = 16 - remain;
+		img_hres = img_hres + remain;
+	}
+	remain = img_vres % 16;
+	if (remain != 0) {
+		remain = 16 - remain;
+		img_vres = img_vres + remain;
+	}
+
+	cb_hres_byte = img_hres;
+	cb_vres_byte = img_vres;
+
+	y_hres_byte = img_hres - 1;
+	y_vres_byte = img_vres - 1;
+	y_hres_roundup = ((y_hres_byte >> 4) >> 3) + 1;
+	y_vres_roundup = ((y_vres_byte >> 4) >> 2) + 1;
+	if ((y_vres_byte & 0x20) == 0) {
+		y_hres_byte = y_hres_byte & 0x7f00;
+		y_hres_byte = y_hres_byte >> 8;
+		y_hres_byte = y_hres_byte & 0x7f;
+
+		y_vres_byte = y_vres_byte & 0x7fc0;
+		y_vres_byte = y_vres_byte >> 6;
+		y_vres_byte = y_vres_byte & 0x1ff;
+
+		*y_size = y_hres_byte +\
+		(y_vres_byte * y_hres_roundup) + 1;
+	} else {
+		*y_size = y_hres_roundup * y_vres_roundup;
+	}
+
+	*y_size = *(y_size) << 13;
+
+	cb_hres_byte = img_hres - 1;
+	cb_vres_byte = (img_vres >> 1) - 1;
+	cb_hres_roundup = ((cb_hres_byte >> 4) >> 3) + 1;
+	cb_vres_roundup = ((cb_vres_byte >> 4) >> 2) + 1;
+	if ((cb_vres_byte & 0x20) == 0) {
+		cb_hres_byte = cb_hres_byte & 0x7f00;
+		cb_hres_byte = cb_hres_byte >> 8;
+		cb_hres_byte = cb_hres_byte & 0x7f;
+
+		cb_vres_byte = cb_vres_byte & 0x7fc0;
+		cb_vres_byte = cb_vres_byte >> 6;
+		cb_vres_byte = cb_vres_byte & 0x1ff;
+
+		*cb_size = cb_hres_byte + (cb_vres_byte * cb_hres_roundup) + 1;
+	} else {
+		*cb_size = cb_hres_roundup * cb_vres_roundup;
+	}
+	*cb_size = (*cb_size) << 13;
+
+}
+
+static int fimc_open(struct file *filp)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct fimc_prv_data *prv_data;
+	int in_use;
+	int ret;
+	int i;
+
+	ctrl = video_get_drvdata(video_devdata(filp));
+	pdata = to_fimc_plat(ctrl->dev);
+
+	mutex_lock(&ctrl->lock);
+
+	in_use = atomic_read(&ctrl->in_use);
+	if (in_use > FIMC_MAX_CTXS) {
+		ret = -EBUSY;
+		goto resource_busy;
+	} else {
+		atomic_inc(&ctrl->in_use);
+		fimc_warn("FIMC%d %d opened.\n",
+			 ctrl->id, atomic_read(&ctrl->in_use));
+	}
+	in_use = atomic_read(&ctrl->in_use);
+
+	prv_data = kzalloc(sizeof(struct fimc_prv_data), GFP_KERNEL);
+	if (!prv_data) {
+		fimc_err("%s: not enough memory\n", __func__);
+		ret = -ENOMEM;
+		goto kzalloc_err;
+	}
+
+	if (in_use == 1) {
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+		if (pdata->clk_on)
+			pdata->clk_on(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+
+		if (pdata->hw_ver == 0x40)
+			fimc_hw_reset_camera(ctrl);
+
+		/* Apply things to interface register */
+		fimc_hwset_reset(ctrl);
+#endif
+		ctrl->fb.open_fifo = s3cfb_open_fifo;
+		ctrl->fb.close_fifo = s3cfb_close_fifo;
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_GET_LCD_WIDTH,
+					(unsigned long)&ctrl->fb.lcd_hres);
+		if (ret < 0) {
+			fimc_err("Fail: S3CFB_GET_LCD_WIDTH\n");
+			goto resource_busy;
+		}
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_GET_LCD_HEIGHT,
+					(unsigned long)&ctrl->fb.lcd_vres);
+		if (ret < 0) {
+			fimc_err("Fail: S3CFB_GET_LCD_HEIGHT\n");
+			goto resource_busy;
+		}
+
+		ctrl->mem.curr = ctrl->mem.base;
+		ctrl->status = FIMC_STREAMOFF;
+
+	}
+
+	prv_data->ctrl = ctrl;
+	if (prv_data->ctrl->out != NULL) {
+		for (i = 0; i < FIMC_MAX_CTXS; i++)
+			if (prv_data->ctrl->out->ctx_used[i] == false) {
+				prv_data->ctx_id = i;
+				prv_data->ctrl->out->ctx_used[i] = true;
+				break;
+			}
+	} else
+		prv_data->ctx_id = in_use - 1;
+
+	filp->private_data = prv_data;
+
+	mutex_unlock(&ctrl->lock);
+
+	return 0;
+
+kzalloc_err:
+	atomic_dec(&ctrl->in_use);
+
+resource_busy:
+	mutex_unlock(&ctrl->lock);
+	return ret;
+}
+
+static int fimc_release(struct file *filp)
+{
+	struct fimc_prv_data *prv_data =
+				(struct fimc_prv_data *)filp->private_data;
+	struct fimc_control *ctrl = prv_data->ctrl;
+	struct fimc_capinfo *cap;
+
+	int ctx_id = prv_data->ctx_id;
+	struct s3c_platform_fimc *pdata;
+	struct fimc_overlay_buf *buf;
+	struct mm_struct *mm = current->mm;
+	struct fimc_ctx *ctx;
+	int ret = 0, i;
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	pdata = to_fimc_plat(ctrl->dev);
+
+	atomic_dec(&ctrl->in_use);
+
+	if (ctrl->cap && (ctrl->status != FIMC_STREAMOFF))
+		fimc_streamoff_capture((void *)ctrl);
+
+	/* FIXME: turning off actual working camera */
+	if (ctrl->cam && ctrl->id != FIMC2) {
+		/* Unload the subdev (camera sensor) module,
+		 * reset related status flags */
+		fimc_release_subdev(ctrl);
+	}
+
+	if (atomic_read(&ctrl->in_use) == 0) {
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+		if (pdata->clk_off) {
+			pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+			ctrl->power_status = FIMC_POWER_OFF;
+		}
+#endif
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+/* #ifdef SYSMMU_FIMC */
+		if (ctrl->power_status == FIMC_POWER_ON) {
+			pm_runtime_put_sync(ctrl->dev);
+		}
+/* #endif */
+#endif
+
+	}
+	if (ctrl->out) {
+		if (ctx->status != FIMC_STREAMOFF) {
+			ret = fimc_outdev_stop_streaming(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_stop_streaming\n");
+				return -EINVAL;
+			}
+
+			ret = fimc_init_in_queue(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_init_in_queue\n");
+				return -EINVAL;
+			}
+
+			ret = fimc_init_out_queue(ctrl, ctx);
+			if (ret < 0) {
+				fimc_err("Fail: fimc_init_out_queue\n");
+				return -EINVAL;
+			}
+
+			/* Make all buffers DQUEUED state. */
+			for (i = 0; i < FIMC_OUTBUFS; i++) {
+				ctx->src[i].state = VIDEOBUF_IDLE;
+				ctx->src[i].flags = V4L2_BUF_FLAG_MAPPED;
+			}
+
+			if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+				ctrl->mem.curr = ctx->dst[0].base[FIMC_ADDR_Y];
+
+				for (i = 0; i < FIMC_OUTBUFS; i++) {
+					ctx->dst[i].base[FIMC_ADDR_Y] = 0;
+					ctx->dst[i].length[FIMC_ADDR_Y] = 0;
+
+					ctx->dst[i].base[FIMC_ADDR_CB] = 0;
+					ctx->dst[i].length[FIMC_ADDR_CB] = 0;
+
+					ctx->dst[i].base[FIMC_ADDR_CR] = 0;
+					ctx->dst[i].length[FIMC_ADDR_CR] = 0;
+				}
+			}
+
+			ctx->status = FIMC_STREAMOFF;
+		}
+
+		ctx->is_requested = 0;
+		buf = &ctx->overlay.buf;
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			if (buf->vir_addr[i]) {
+				ret = do_munmap(mm, buf->vir_addr[i],
+						buf->size[i]);
+				if (ret < 0)
+					fimc_err("%s: do_munmap fail\n",
+							__func__);
+			}
+		}
+
+		/* reset inq & outq of context */
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->inq[i] = -1;
+			ctx->outq[i] = -1;
+		}
+
+		if (atomic_read(&ctrl->in_use) == 0) {
+			ctrl->status = FIMC_STREAMOFF;
+			fimc_outdev_init_idxs(ctrl);
+
+			ctrl->mem.curr = ctrl->mem.base;
+
+			kfree(ctrl->out);
+			ctrl->out = NULL;
+
+			kfree(filp->private_data);
+			filp->private_data = NULL;
+		} else {
+			ctrl->out->ctx_used[ctx_id] = false;
+		}
+	}
+
+	if (ctrl->cap) {
+		cap = ctrl->cap;
+		ctrl->mem.curr = ctrl->mem.base;
+		kfree(filp->private_data);
+		filp->private_data = NULL;
+		if (pdata->hw_ver >= 0x51)
+			INIT_LIST_HEAD(&cap->outgoing_q);
+		for (i = 0; i < FIMC_CAPBUFS; i++) {
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 0);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 1);
+			fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 2);
+		}
+		kfree(ctrl->cap);
+		ctrl->cap = NULL;
+	}
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	flush_workqueue(ctrl->fimc_irq_wq);
+#endif
+
+	/*
+	 * Close window for FIMC if window is enabled.
+	 */
+	if (ctrl->fb.is_enable == 1) {
+		fimc_warn("WIN_OFF for FIMC%d\n", ctrl->id);
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_OFF,
+						(unsigned long)NULL);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_OFF) fail\n");
+			return -EINVAL;
+		}
+
+		ctrl->fb.is_enable = 0;
+	}
+
+	fimc_warn("FIMC%d %d released.\n",
+			ctrl->id, atomic_read(&ctrl->in_use));
+
+	return 0;
+}
+
+static const struct v4l2_file_operations fimc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_open,
+	.release	= fimc_release,
+	.ioctl		= video_ioctl2,
+	.read		= fimc_read,
+	.write		= fimc_write,
+	.mmap		= fimc_mmap,
+	.poll		= fimc_poll,
+};
+
+static void fimc_vdev_release(struct video_device *vdev)
+{
+	kfree(vdev);
+}
+
+struct video_device fimc_video_device[FIMC_DEVICES] = {
+	[0] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+	[1] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+	[2] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+#ifdef CONFIG_ARCH_EXYNOS4
+	[3] = {
+		.fops = &fimc_fops,
+		.ioctl_ops = &fimc_v4l2_ops,
+		.release = fimc_vdev_release,
+	},
+#endif
+};
+
+static int fimc_init_global(struct platform_device *pdev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct s3c_platform_camera *cam;
+	struct clk *srclk;
+	int id, i;
+
+	pdata = to_fimc_plat(&pdev->dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	/* Registering external camera modules. re-arrange order to be sure */
+	for (i = 0; i < FIMC_MAXCAMS; i++) {
+		cam = pdata->camera[i];
+		if (!cam)
+			break;
+		/* WriteBack doesn't need clock setting */
+		if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
+			fimc_dev->camera[i] = cam;
+			fimc_dev->camera_isvalid[i] = 1;
+			fimc_dev->camera[i]->initialized = 0;
+			continue;
+		}
+
+		/* source clk for MCLK*/
+		srclk = clk_get(&pdev->dev, cam->srclk_name);
+		if (IS_ERR(srclk)) {
+			fimc_err("%s: failed to get srclk source\n", __func__);
+			return -EINVAL;
+		}
+
+		/* mclk */
+		cam->clk = clk_get(&pdev->dev, cam->clk_name);
+		if (IS_ERR(cam->clk)) {
+			fimc_err("%s: failed to get mclk source\n", __func__);
+			return -EINVAL;
+		}
+
+		if (clk_set_parent(cam->clk, srclk)) {
+			dev_err(&pdev->dev, "unable to set parent %s of clock %s.\n",
+					srclk->name, cam->clk->name);
+			clk_put(srclk);
+			clk_put(cam->clk);
+			return -EINVAL;
+		}
+
+		/* Assign camera device to fimc */
+		fimc_dev->camera[i] = cam;
+		fimc_dev->camera_isvalid[i] = 1;
+		fimc_dev->camera[i]->initialized = 0;
+	}
+
+	fimc_dev->mclk_status = CAM_MCLK_OFF;
+	fimc_dev->active_camera = -1;
+	fimc_dev->initialized = 1;
+
+	return 0;
+}
+
+static int fimc_show_log_level(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	int id = -1;
+
+	char temp[150];
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	sprintf(temp, "\t");
+	strcat(buf, temp);
+	if (ctrl->log & FIMC_LOG_DEBUG) {
+		sprintf(temp, "FIMC_LOG_DEBUG | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_INFO_L2) {
+		sprintf(temp, "FIMC_LOG_INFO_L2 | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_INFO_L1) {
+		sprintf(temp, "FIMC_LOG_INFO_L1 | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_WARN) {
+		sprintf(temp, "FIMC_LOG_WARN | ");
+		strcat(buf, temp);
+	}
+
+	if (ctrl->log & FIMC_LOG_ERR) {
+		sprintf(temp, "FIMC_LOG_ERR\n");
+		strcat(buf, temp);
+	}
+
+	return strlen(buf);
+}
+
+static int fimc_store_log_level(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t len)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+
+	const char *p = buf;
+	char msg[150] = {0, };
+	int id = -1;
+	u32 match = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	while (*p != '\0') {
+		if (!isspace(*p))
+			strncat(msg, p, 1);
+		p++;
+	}
+
+	ctrl->log = 0;
+	printk(KERN_INFO "FIMC.%d log level is set as below.\n", id);
+
+	if (strstr(msg, "FIMC_LOG_ERR") != NULL) {
+		ctrl->log |= FIMC_LOG_ERR;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_ERR\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_WARN") != NULL) {
+		ctrl->log |= FIMC_LOG_WARN;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_WARN\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_INFO_L1") != NULL) {
+		ctrl->log |= FIMC_LOG_INFO_L1;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_INFO_L1\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_INFO_L2") != NULL) {
+		ctrl->log |= FIMC_LOG_INFO_L2;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_INFO_L2\n");
+	}
+
+	if (strstr(msg, "FIMC_LOG_DEBUG") != NULL) {
+		ctrl->log |= FIMC_LOG_DEBUG;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_LOG_DEBUG\n");
+	}
+
+	if (!match) {
+		printk(KERN_INFO "FIMC_LOG_ERR		\t: Error condition.\n");
+		printk(KERN_INFO "FIMC_LOG_WARN		\t: WARNING condition.\n");
+		printk(KERN_INFO "FIMC_LOG_INFO_L1	\t: V4L2 API without QBUF, DQBUF.\n");
+		printk(KERN_INFO "FIMC_LOG_INFO_L2	\t: V4L2 API QBUF, DQBUF.\n");
+		printk(KERN_INFO "FIMC_LOG_DEBUG	\t: Queue status report.\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(log_level, 0644, \
+			fimc_show_log_level,
+			fimc_store_log_level);
+
+static int fimc_show_range_mode(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	int id = -1;
+
+	char temp[150];
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	sprintf(temp, "\t");
+	strcat(buf, temp);
+	if (ctrl->range == FIMC_RANGE_NARROW) {
+		sprintf(temp, "FIMC_RANGE_NARROW\n");
+		strcat(buf, temp);
+	} else {
+		sprintf(temp, "FIMC_RANGE_WIDE\n");
+		strcat(buf, temp);
+	}
+
+	return strlen(buf);
+}
+
+static int fimc_store_range_mode(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t len)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+
+	const char *p = buf;
+	char msg[150] = {0, };
+	int id = -1;
+	u32 match = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	while (*p != '\0') {
+		if (!isspace(*p))
+			strncat(msg, p, 1);
+		p++;
+	}
+
+	ctrl->range = 0;
+	printk(KERN_INFO "FIMC.%d range mode is set as below.\n", id);
+
+	if (strstr(msg, "FIMC_RANGE_WIDE") != NULL) {
+		ctrl->range = FIMC_RANGE_WIDE;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_RANGE_WIDE\n");
+	}
+
+	if (strstr(msg, "FIMC_RANGE_NARROW") != NULL) {
+		ctrl->range = FIMC_RANGE_NARROW;
+		match = 1;
+		printk(KERN_INFO "\tFIMC_RANGE_NARROW\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(range_mode, 0644, \
+			fimc_show_range_mode,
+			fimc_store_range_mode);
+
+static int __devinit fimc_probe(struct platform_device *pdev)
+{
+	struct s3c_platform_fimc *pdata;
+	struct fimc_control *ctrl;
+	int ret;
+
+	if (!fimc_dev) {
+		fimc_dev = kzalloc(sizeof(*fimc_dev), GFP_KERNEL);
+		if (!fimc_dev) {
+			dev_err(&pdev->dev, "%s: not enough memory\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+
+	ctrl = fimc_register_controller(pdev);
+	if (!ctrl) {
+		printk(KERN_ERR "%s: cannot register fimc\n", __func__);
+		goto err_alloc;
+	}
+
+	pdata = to_fimc_plat(&pdev->dev);
+	if ((ctrl->id == FIMC0) && (pdata->cfg_gpio))
+		pdata->cfg_gpio(pdev);
+
+	/* V4L2 device-subdev registration */
+	ret = v4l2_device_register(&pdev->dev, &ctrl->v4l2_dev);
+	if (ret) {
+		fimc_err("%s: v4l2 device register failed\n", __func__);
+		goto err_fimc;
+	}
+	ctrl->vd->v4l2_dev = &ctrl->v4l2_dev;
+
+	/* things to initialize once */
+	if (!fimc_dev->initialized) {
+		ret = fimc_init_global(pdev);
+		if (ret)
+			goto err_v4l2;
+	}
+
+	/* video device register */
+	ret = video_register_device(ctrl->vd, VFL_TYPE_GRABBER, ctrl->id);
+	if (ret) {
+		fimc_err("%s: cannot register video driver\n", __func__);
+		goto err_v4l2;
+	}
+
+	video_set_drvdata(ctrl->vd, ctrl);
+
+#ifdef CONFIG_VIDEO_FIMC_RANGE_WIDE
+	ctrl->range = FIMC_RANGE_WIDE;
+#else
+	ctrl->range = FIMC_RANGE_NARROW;
+#endif
+
+	ret = device_create_file(&(pdev->dev), &dev_attr_log_level);
+	if (ret < 0) {
+		fimc_err("failed to add sysfs entries for log level\n");
+		goto err_global;
+	}
+	ret = device_create_file(&(pdev->dev), &dev_attr_range_mode);
+	if (ret < 0) {
+		fimc_err("failed to add sysfs entries for range mode\n");
+		goto err_global;
+	}
+	printk(KERN_INFO "FIMC%d registered successfully\n", ctrl->id);
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	ctrl->power_status = FIMC_POWER_OFF;
+	pm_runtime_enable(&pdev->dev);
+
+	sprintf(buf, "fimc%d_iqr_wq_name", ctrl->id);
+	ctrl->fimc_irq_wq = create_workqueue(buf);
+
+	if (ctrl->fimc_irq_wq == NULL) {
+		fimc_err("Cannot create workqueue for fimc driver\n");
+		goto err_global;
+	}
+
+	INIT_WORK(&ctrl->work_struct, s3c_fimc_irq_work);
+	atomic_set(&ctrl->irq_cnt, 0);
+#endif
+
+	return 0;
+
+err_global:
+	video_unregister_device(ctrl->vd);
+
+err_v4l2:
+	v4l2_device_unregister(&ctrl->v4l2_dev);
+
+err_fimc:
+	fimc_unregister_controller(pdev);
+
+err_alloc:
+	kfree(fimc_dev);
+	return -EINVAL;
+
+}
+
+static int fimc_remove(struct platform_device *pdev)
+{
+	fimc_unregister_controller(pdev);
+
+	device_remove_file(&(pdev->dev), &dev_attr_log_level);
+
+	kfree(fimc_dev);
+	fimc_dev = NULL;
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	pm_runtime_disable(&pdev->dev);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static inline void fimc_suspend_out_ctx(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx)
+{
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_DMA_AUTO:		/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:		/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:		/* fall through */
+	case FIMC_OVLY_NONE_SINGLE_BUF:
+		if (ctx->status == FIMC_STREAMON) {
+			if (ctx->inq[0] != -1)
+				fimc_err("%s : %d in queue unstable\n",
+					__func__, __LINE__);
+
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_SLEEP;
+		} else if (ctx->status == FIMC_STREAMON_IDLE) {
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_IDLE_SLEEP;
+		} else {
+			ctx->status = FIMC_OFF_SLEEP;
+		}
+
+		break;
+	case FIMC_OVLY_FIFO:
+		if (ctx->status == FIMC_STREAMON) {
+			if (ctx->inq[0] != -1)
+				fimc_err("%s: %d in queue unstable\n",
+					 __func__, __LINE__);
+
+			if ((ctrl->out->idxs.next.idx != -1) ||
+			    (ctrl->out->idxs.prev.idx != -1))
+				fimc_err("%s: %d FIMC unstable\n",
+					__func__, __LINE__);
+
+			fimc_outdev_stop_streaming(ctrl, ctx);
+			ctx->status = FIMC_ON_SLEEP;
+		} else {
+			ctx->status = FIMC_OFF_SLEEP;
+		}
+
+		break;
+	case FIMC_OVLY_NOT_FIXED:
+		ctx->status = FIMC_OFF_SLEEP;
+		break;
+	}
+}
+
+static inline int fimc_suspend_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	int i, on_sleep = 0, idle_sleep = 0, off_sleep = 0;
+
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		ctx = &ctrl->out->ctx[i];
+		fimc_suspend_out_ctx(ctrl, ctx);
+
+		switch (ctx->status) {
+		case FIMC_ON_SLEEP:
+			on_sleep++;
+			break;
+		case FIMC_ON_IDLE_SLEEP:
+			idle_sleep++;
+			break;
+		case FIMC_OFF_SLEEP:
+			off_sleep++;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (on_sleep)
+		ctrl->status = FIMC_ON_SLEEP;
+	else if (idle_sleep)
+		ctrl->status = FIMC_ON_IDLE_SLEEP;
+	else
+		ctrl->status = FIMC_OFF_SLEEP;
+
+	ctrl->out->last_ctx = -1;
+
+	return 0;
+}
+
+static inline int fimc_suspend_cap(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+
+	fimc_dbg("%s\n", __func__);
+
+	if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B)	{
+		fimc_dbg("%s\n", __func__);
+		ctrl->suspend_framecnt = fimc_hwget_output_buf_sequence(ctrl);
+		fimc_streamoff_capture((void *)ctrl);
+		fimc_info1("%s : framecnt_seq : %d\n",
+				__func__, ctrl->suspend_framecnt);
+	} else {
+		if (ctrl->id == FIMC0 && ctrl->cam->initialized) {
+			ctrl->cam->initialized = 0;
+
+			v4l2_subdev_call(ctrl->cam->sd, core, s_power, 0);
+
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(0);
+
+			/* shutdown the MCLK */
+			clk_disable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_OFF;
+		}
+	}
+	ctrl->power_status = FIMC_POWER_OFF;
+
+	return 0;
+}
+
+int fimc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	int id;
+
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+	pdata = to_fimc_plat(ctrl->dev);
+
+	if (ctrl->out)
+		fimc_suspend_out(ctrl);
+
+	else if (ctrl->cap)
+		fimc_suspend_cap(ctrl);
+	else
+		ctrl->status = FIMC_OFF_SLEEP;
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	if (atomic_read(&ctrl->in_use) && pdata->clk_off)
+		pdata->clk_off(pdev, &ctrl->clk);
+#endif
+
+	return 0;
+}
+
+int fimc_suspend_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+	pm_message_t state;
+
+	state.event = 0;
+	pdev = to_platform_device(dev);
+	ret = fimc_suspend(pdev, state);
+
+	return 0;
+}
+
+static inline void fimc_resume_out_ctx(struct fimc_control *ctrl,
+				       struct fimc_ctx *ctx)
+{
+	int index = -1, ret = -1;
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:
+		if (ctx->status == FIMC_ON_SLEEP) {
+			ctx->status = FIMC_READY_ON;
+
+			ret = fimc_outdev_set_ctx_param(ctrl, ctx);
+			if (ret < 0)
+				fimc_err("Fail: fimc_outdev_set_ctx_param\n");
+
+#if defined(CONFIG_VIDEO_IPC)
+			if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB)
+				ipc_start();
+#endif
+			index = ctrl->out->idxs.active.idx;
+			fimc_outdev_set_src_addr(ctrl, ctx->src[index].base);
+
+			ret = fimc_start_fifo(ctrl, ctx);
+			if (ret < 0)
+				fimc_err("Fail: fimc_start_fifo\n");
+
+			ctx->status = FIMC_STREAMON;
+		} else if (ctx->status == FIMC_OFF_SLEEP) {
+			ctx->status = FIMC_STREAMOFF;
+		} else {
+			fimc_err("%s: Abnormal (%d)\n", __func__, ctx->status);
+		}
+
+		break;
+	case FIMC_OVLY_DMA_AUTO:
+		if (ctx->status == FIMC_ON_IDLE_SLEEP) {
+			fimc_outdev_resume_dma(ctrl, ctx);
+			ret = fimc_outdev_set_ctx_param(ctrl, ctx);
+			if (ret < 0)
+				fimc_err("Fail: fimc_outdev_set_ctx_param\n");
+
+			ctx->status = FIMC_STREAMON_IDLE;
+		} else if (ctx->status == FIMC_OFF_SLEEP) {
+			ctx->status = FIMC_STREAMOFF;
+		} else {
+			fimc_err("%s: Abnormal (%d)\n", __func__, ctx->status);
+		}
+
+		break;
+	case FIMC_OVLY_DMA_MANUAL:
+		if (ctx->status == FIMC_ON_IDLE_SLEEP) {
+			ret = fimc_outdev_set_ctx_param(ctrl, ctx);
+			if (ret < 0)
+				fimc_err("Fail: fimc_outdev_set_ctx_param\n");
+
+			ctx->status = FIMC_STREAMON_IDLE;
+
+		} else if (ctx->status == FIMC_OFF_SLEEP) {
+			ctx->status = FIMC_STREAMOFF;
+		} else {
+			fimc_err("%s: Abnormal (%d)\n", __func__, ctx->status);
+		}
+
+		break;
+	case FIMC_OVLY_NONE_SINGLE_BUF:		/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		if (ctx->status == FIMC_ON_IDLE_SLEEP) {
+			ret = fimc_outdev_set_ctx_param(ctrl, ctx);
+			if (ret < 0)
+				fimc_err("Fail: fimc_outdev_set_ctx_param\n");
+
+			ctx->status = FIMC_STREAMON_IDLE;
+		} else if (ctx->status == FIMC_OFF_SLEEP) {
+			ctx->status = FIMC_STREAMOFF;
+		} else {
+			fimc_err("%s: Abnormal (%d)\n", __func__, ctx->status);
+		}
+
+		break;
+	default:
+		ctx->status = FIMC_STREAMOFF;
+		break;
+	}
+}
+
+static inline int fimc_resume_out(struct fimc_control *ctrl)
+{
+	struct fimc_ctx *ctx;
+	int i;
+	u32 state = 0;
+	u32 timeout;
+	u32 tmp;
+	struct s3c_platform_fimc *pdata;
+
+	pdata = to_fimc_plat(ctrl->dev);
+
+	tmp = __raw_readl(S5P_PMU_CAM_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN;
+
+	if (tmp != S5P_INT_LOCAL_PWR_EN) {
+		__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_CAM_CONF);
+
+		/*  Wait max 1ms */
+		timeout = 10;
+		while ((__raw_readl(S5P_PMU_CAM_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN)
+					!= S5P_INT_LOCAL_PWR_EN) {
+			if (timeout == 0) {
+				printk(KERN_ERR "Power domain CAM enable failed.\n");
+				break;
+			}
+			timeout--;
+			udelay(100);
+		}
+	}
+
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		ctx = &ctrl->out->ctx[i];
+
+		if (pdata->clk_on) {
+			pdata->clk_on(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+		}
+
+		fimc_resume_out_ctx(ctrl, ctx);
+
+		if (pdata->clk_off) {
+			pdata->clk_off(to_platform_device(ctrl->dev),
+					&ctrl->clk);
+		}
+
+		switch (ctx->status) {
+		case FIMC_STREAMON:
+			state |= FIMC_STREAMON;
+			break;
+		case FIMC_STREAMON_IDLE:
+			state |= FIMC_STREAMON_IDLE;
+			break;
+		case FIMC_STREAMOFF:
+			state |= FIMC_STREAMOFF;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (tmp != S5P_INT_LOCAL_PWR_EN) {
+		__raw_writel(0, S5P_PMU_CAM_CONF);
+
+		/* Wait max 1ms */
+		timeout = 10;
+		while (__raw_readl(S5P_PMU_CAM_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN) {
+			if (timeout == 0) {
+				printk(KERN_ERR "Power domain CAM disable failed.\n");
+				break;
+			}
+			timeout--;
+			udelay(100);
+		}
+	}
+
+	if ((state & FIMC_STREAMON) == FIMC_STREAMON)
+		ctrl->status = FIMC_STREAMON;
+	else if ((state & FIMC_STREAMON_IDLE) == FIMC_STREAMON_IDLE)
+		ctrl->status = FIMC_STREAMON_IDLE;
+	else
+		ctrl->status = FIMC_STREAMOFF;
+
+	return 0;
+}
+
+static inline int fimc_resume_cap(struct fimc_control *ctrl)
+{
+	struct fimc_global *fimc = get_fimc_dev();
+	int tmp;
+	u32 timeout;
+
+	fimc_dbg("%s\n", __func__);
+
+	__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_CAM_CONF);
+	/*  Wait max 1ms */
+	timeout = 10;
+	while ((__raw_readl(S5P_PMU_CAM_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN)
+			!= S5P_INT_LOCAL_PWR_EN) {
+		if (timeout == 0) {
+			printk(KERN_ERR "Power domain CAM enable failed.\n");
+			break;
+		}
+		timeout--;
+		udelay(100);
+	}
+
+	if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : framecnt_seq : %d\n",
+				__func__, ctrl->suspend_framecnt);
+		fimc_hwset_output_buf_sequence_all(ctrl,
+				ctrl->suspend_framecnt);
+		tmp = fimc_hwget_output_buf_sequence(ctrl);
+		fimc_info1("%s : real framecnt_seq : %d\n", __func__, tmp);
+
+		fimc_streamon_capture((void *)ctrl);
+	} else {
+		if (ctrl->id == FIMC0 && ctrl->cam->initialized == 0) {
+			clk_set_rate(ctrl->cam->clk, ctrl->cam->clk_rate);
+			clk_enable(ctrl->cam->clk);
+			fimc->mclk_status = CAM_MCLK_ON;
+			fimc_info1("clock for camera: %d\n", ctrl->cam->clk_rate);
+
+			if (ctrl->cam->cam_power)
+				ctrl->cam->cam_power(1);
+
+			v4l2_subdev_call(ctrl->cam->sd, core, s_power, 1);
+
+			ctrl->cam->initialized = 1;
+		}
+	}
+	/* fimc_streamon_capture((void *)ctrl); */
+	ctrl->power_status = FIMC_POWER_ON;
+
+	return 0;
+}
+
+int fimc_resume(struct platform_device *pdev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	int id = pdev->id;
+
+	ctrl = get_fimc_ctrl(id);
+	pdata = to_fimc_plat(ctrl->dev);
+
+	if (atomic_read(&ctrl->in_use) && pdata->clk_on)
+		pdata->clk_on(pdev, &ctrl->clk);
+
+	if (ctrl->out)
+		fimc_resume_out(ctrl);
+
+	else if (ctrl->cap)
+		fimc_resume_cap(ctrl);
+	else
+		ctrl->status = FIMC_STREAMOFF;
+
+	return 0;
+}
+
+int fimc_resume_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = to_platform_device(dev);
+	ret = fimc_resume(pdev);
+	return 0;
+}
+
+
+#else
+#define fimc_suspend	NULL
+#define fimc_resume	NULL
+#endif
+
+static int fimc_runtime_suspend_out(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata;
+	int ret;
+
+	pdata = to_fimc_plat(ctrl->dev);
+
+	if (pdata->clk_off) {
+		ret = pdata->clk_off(to_platform_device(ctrl->dev), &ctrl->clk);
+		if (ret == 0)
+			ctrl->power_status = FIMC_POWER_OFF;
+	}
+
+	return 0;
+}
+static int fimc_runtime_suspend_cap(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata	= to_fimc_plat(ctrl->dev);
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	struct clk *pxl_async = NULL;
+	int ret = 0;
+	fimc_dbg("%s FIMC%d\n", __func__, ctrl->id);
+
+	ctrl->power_status = FIMC_POWER_SUSPEND;
+
+	if (ctrl->cap && (ctrl->status != FIMC_STREAMOFF)) {
+		fimc_streamoff_capture((void *)ctrl);
+		ctrl->status = FIMC_STREAMOFF;
+	}
+
+	if (pdata->clk_off) {
+		ret = pdata->clk_off(pdev, &ctrl->clk);
+		if (ret == 0)
+			ctrl->power_status = FIMC_POWER_OFF;
+	}
+
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cam->id == CAMERA_WB) {
+		fimc_info1("%s : writeback 0 suspend\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async0");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_disable(pxl_async);
+		clk_put(pxl_async);
+	} else if (ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : writeback 1 suspend\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_disable(pxl_async);
+		clk_put(pxl_async);
+	}
+
+
+	return 0;
+}
+static int fimc_runtime_suspend(struct device *dev)
+{
+	struct fimc_control *ctrl;
+	struct platform_device *pdev;
+	int id;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	fimc_dbg("%s FIMC%d\n", __func__, ctrl->id);
+
+	if (ctrl->out) {
+		fimc_info1("%s: fimc m2m\n", __func__);
+		fimc_runtime_suspend_out(ctrl);
+	} else if (ctrl->cap) {
+		fimc_info1("%s: fimc capture\n", __func__);
+		fimc_runtime_suspend_cap(ctrl);
+	} else
+		fimc_err("%s : invalid fimc control\n", __func__);
+
+	fimc_dev->backup_regs[id] = ctrl->regs;
+	ctrl->regs = NULL;
+
+	return 0;
+}
+
+static int fimc_runtime_resume_cap(struct fimc_control *ctrl)
+{
+	struct platform_device *pdev = to_platform_device(ctrl->dev);
+	struct clk *pxl_async = NULL;
+	fimc_dbg("%s\n", __func__);
+
+	if (!ctrl->cam) {
+		fimc_err("%s: No capture device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (ctrl->cam->id == CAMERA_WB) {
+		fimc_info1("%s : writeback 0 resume\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async0");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+	} else if (ctrl->cam->id == CAMERA_WB_B) {
+		fimc_info1("%s : writeback 1 resume\n", __func__);
+		pxl_async = clk_get(&pdev->dev, "pxl_async1");
+		if (IS_ERR(pxl_async)) {
+			dev_err(&pdev->dev, "failed to get pxl_async\n");
+			return -ENODEV;
+		}
+
+		clk_enable(pxl_async);
+		clk_put(pxl_async);
+	}
+
+	return 0;
+}
+static int fimc_runtime_resume(struct device *dev)
+{
+	struct fimc_control *ctrl;
+	struct s3c_platform_fimc *pdata;
+	struct platform_device *pdev;
+	int id, ret = 0;
+
+	pdev = to_platform_device(dev);
+	id = pdev->id;
+	ctrl = get_fimc_ctrl(id);
+
+	ctrl->regs = fimc_dev->backup_regs[id];
+	fimc_dev->backup_regs[id] = NULL;
+
+	fimc_dbg("%s\n", __func__);
+
+	pdata = to_fimc_plat(ctrl->dev);
+	if (pdata->clk_on) {
+		ret = pdata->clk_on(pdev, &ctrl->clk);
+		if (ret == 0)
+			ctrl->power_status = FIMC_POWER_ON;
+	}
+
+	/* if status is FIMC_PROBE, not need to know differlence of out or
+	 * cap */
+
+	if (ctrl->out) {
+		/* do not need to sub function in m2m mode */
+		fimc_info1("%s: fimc m2m\n", __func__);
+	} else if (ctrl->cap) {
+		fimc_info1("%s: fimc cap\n", __func__);
+		fimc_runtime_resume_cap(ctrl);
+	} else {
+		fimc_err("%s: runtime resume error\n", __func__);
+	}
+	return 0;
+}
+static const struct dev_pm_ops fimc_pm_ops = {
+	.suspend	= fimc_suspend_pd,
+	.resume		= fimc_resume_pd,
+	.runtime_suspend = fimc_runtime_suspend,
+	.runtime_resume = fimc_runtime_resume,
+};
+
+static struct platform_driver fimc_driver = {
+	.probe		= fimc_probe,
+	.remove		= fimc_remove,
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	.suspend	= fimc_suspend,
+	.resume		= fimc_resume,
+#endif
+	.driver		= {
+		.name	= FIMC_NAME,
+		.owner	= THIS_MODULE,
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		.pm = &fimc_pm_ops,
+#else
+		.pm = NULL,
+#endif
+
+	},
+};
+
+static int fimc_register(void)
+{
+	platform_driver_register(&fimc_driver);
+
+	return 0;
+}
+
+static void fimc_unregister(void)
+{
+	platform_driver_unregister(&fimc_driver);
+}
+
+late_initcall(fimc_register);
+module_exit(fimc_unregister);
+
+MODULE_AUTHOR("Dongsoo,	Kim <dongsoo45.kim@samsung.com>");
+MODULE_AUTHOR("Jinsung,	Yang <jsgood.yang@samsung.com>");
+MODULE_AUTHOR("Jonghun,	Han <jonghun.han@samsung.com>");
+MODULE_DESCRIPTION("Samsung Camera Interface (FIMC) driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimc/fimc_output.c b/drivers/media/video/samsung/fimc/fimc_output.c
new file mode 100644
index 0000000..895cb7f
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_output.c
@@ -0,0 +1,3274 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_output.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * V4L2 Output device support file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/videobuf-core.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/mman.h>
+#include <plat/media.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include "fimc.h"
+#include "fimc-ipc.h"
+
+static __u32 fimc_get_pixel_format_type(__u32 pixelformat)
+{
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_RGB32:
+	case V4L2_PIX_FMT_RGB565:
+		return FIMC_RGB;
+
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV12M:
+	case V4L2_PIX_FMT_NV12T:
+	case V4L2_PIX_FMT_NV21:
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		return FIMC_YUV420;
+
+	case V4L2_PIX_FMT_YUYV:
+	case V4L2_PIX_FMT_UYVY:
+	case V4L2_PIX_FMT_YVYU:
+	case V4L2_PIX_FMT_VYUY:
+	case V4L2_PIX_FMT_NV16:
+	case V4L2_PIX_FMT_NV61:
+	case V4L2_PIX_FMT_YUV422P:
+		return FIMC_YUV422;
+
+	default:
+		return FIMC_YUV444;
+	}
+}
+
+void fimc_outdev_set_src_addr(struct fimc_control *ctrl, dma_addr_t *base)
+{
+	if (ctrl && (ctrl->regs == NULL)) {
+		fimc_dbg("%s FIMC%d power is off: skip to set config\n",
+				__func__, ctrl->id);
+		return;
+	}
+	fimc_hwset_addr_change_disable(ctrl);
+	fimc_hwset_input_address(ctrl, base);
+	fimc_hwset_addr_change_enable(ctrl);
+}
+
+int fimc_outdev_start_camif(void *param)
+{
+	struct fimc_control *ctrl = (struct fimc_control *)param;
+
+	fimc_hwset_start_scaler(ctrl);
+	fimc_hwset_enable_capture(ctrl, 0);	/* bypass disable */
+	fimc_hwset_start_input_dma(ctrl);
+
+	return 0;
+}
+
+static int fimc_outdev_stop_camif(void *param)
+{
+	struct fimc_control *ctrl = (struct fimc_control *)param;
+
+	if (ctrl->regs == 0) {
+		fimc_err("%s: power offed", __func__);
+		return 0;
+	}
+	fimc_hwset_stop_input_dma(ctrl);
+	fimc_hwset_disable_autoload(ctrl);
+	fimc_hwset_stop_scaler(ctrl);
+	fimc_hwset_disable_capture(ctrl);
+
+	return 0;
+}
+
+static int fimc_outdev_stop_fifo(struct fimc_control *ctrl,
+				 struct fimc_ctx *ctx)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	int ret = -1;
+
+	fimc_dbg("%s: called\n", __func__);
+
+	if (pdata->hw_ver == 0x40) {		/* to support C100 */
+		ret = ctrl->fb.close_fifo(ctrl->id, fimc_outdev_stop_camif,
+				(void *)ctrl);
+		if (ret < 0)
+			fimc_err("FIMD FIFO close fail\n");
+	} else if ((pdata->hw_ver == 0x43) || (pdata->hw_ver >= 0x50)) {
+		ret = ctrl->fb.close_fifo(ctrl->id, NULL, NULL);
+		if (ret < 0)
+			fimc_err("FIMD FIFO close fail\n");
+		fimc_hw_wait_winoff(ctrl);
+		fimc_outdev_stop_camif(ctrl);
+		fimc_hw_wait_stop_input_dma(ctrl);
+#if defined(CONFIG_VIDEO_IPC)
+		if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB)
+			ipc_stop();
+#endif
+	}
+
+	return 0;
+}
+
+int fimc_outdev_stop_streaming(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	int ret = 0;
+
+	fimc_dbg("%s: called\n", __func__);
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:
+		ctx->status = FIMC_READY_OFF;
+		fimc_outdev_stop_fifo(ctrl, ctx);
+		break;
+	case FIMC_OVLY_DMA_AUTO:		/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		if (ctx->status == FIMC_STREAMON_IDLE)
+			ctx->status = FIMC_STREAMOFF;
+		else
+			ctx->status = FIMC_READY_OFF;
+		break;
+	case FIMC_OVLY_NONE_SINGLE_BUF:		/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		if (ctx->status == FIMC_STREAMON_IDLE)
+			ctx->status = FIMC_STREAMOFF;
+		else
+			ctx->status = FIMC_READY_OFF;
+
+		ret = wait_event_timeout(ctrl->wq,
+					(ctx->status == FIMC_STREAMOFF),
+					FIMC_ONESHOT_TIMEOUT);
+		if (ret == 0) {
+			if (ctrl->out == NULL) {
+				fimc_err("%s: ctrl->out is changed to null\n",
+						__func__);
+				return -EINVAL;
+			}
+			fimc_dump_context(ctrl, ctx);
+			fimc_err("fail %s: %d\n", __func__, ctx->ctx_num);
+		}
+
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_dma_auto_dst_resize(struct v4l2_rect *org)
+{
+	if (org->width % 16)
+		org->width = org->width + 16 - (org->width % 16);
+
+	return 0;
+}
+
+int fimc_outdev_resume_dma(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	struct v4l2_rect fimd_rect, fimd_rect_virtual;
+	struct fb_var_screeninfo var;
+	struct s3cfb_user_window window;
+	int ret = -1, idx;
+	u32 id = ctrl->id;
+
+	memset(&fimd_rect, 0, sizeof(struct v4l2_rect));
+	ret = fimc_fimd_rect(ctrl, ctx, &fimd_rect);
+	if (ret < 0) {
+		fimc_err("fimc_fimd_rect fail\n");
+		return -EINVAL;
+	}
+
+	/* Support any size */
+	memcpy(&fimd_rect_virtual, &fimd_rect, sizeof(fimd_rect));
+	fimc_outdev_dma_auto_dst_resize(&fimd_rect_virtual);
+
+	/* Get WIN var_screeninfo */
+	ret = s3cfb_direct_ioctl(id, FBIOGET_VSCREENINFO,
+						(unsigned long)&var);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(FBIOGET_VSCREENINFO) fail\n");
+		return -EINVAL;
+	}
+
+	/* window path : DMA */
+	ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_PATH, DATA_PATH_DMA);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_PATH) fail\n");
+		return -EINVAL;
+	}
+
+	/* Don't allocate the memory. */
+	ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_MEM, DMA_MEM_OTHER);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_MEM) fail\n");
+		return -EINVAL;
+	}
+
+	/* Update WIN size */
+	var.xres_virtual = fimd_rect_virtual.width;
+	var.yres_virtual = fimd_rect_virtual.height;
+	var.xres = fimd_rect.width;
+	var.yres = fimd_rect.height;
+
+	ret = s3cfb_direct_ioctl(id, FBIOPUT_VSCREENINFO,
+						(unsigned long)&var);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(FBIOPUT_VSCREENINFO) fail\n");
+		return -EINVAL;
+	}
+
+	/* Update WIN position */
+	window.x = fimd_rect.left;
+	window.y = fimd_rect.top;
+	ret = s3cfb_direct_ioctl(id, S3CFB_WIN_POSITION,
+			(unsigned long)&window);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_WIN_POSITION) fail\n");
+		return -EINVAL;
+	}
+
+	idx = ctx->outq[0];
+	if (idx == -1) {
+		fimc_err("out going queue is empty.\n");
+		return -EINVAL;
+	}
+
+	ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ADDR,
+			(unsigned long)ctx->dst[idx].base[FIMC_ADDR_Y]);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_ADDR) fail\n");
+		return -EINVAL;
+	}
+
+#if 0
+	/* Remarked for better screen display
+	 * when dynamic screen size change is requested
+	 */
+	ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ON,
+							(unsigned long)NULL);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_ON) fail\n");
+		return -EINVAL;
+	}
+#endif
+
+	ctrl->fb.is_enable = 1;
+
+	return 0;
+}
+
+static void fimc_init_out_buf(struct fimc_ctx *ctx)
+{
+	int i;
+
+	for (i = 0; i < FIMC_OUTBUFS; i++) {
+		ctx->src[i].state = VIDEOBUF_IDLE;
+		ctx->src[i].flags = 0x0;
+
+		ctx->inq[i] = -1;
+		ctx->outq[i] = -1;
+	}
+}
+
+static int fimc_outdev_set_src_buf(struct fimc_control *ctrl,
+				   struct fimc_ctx *ctx)
+{
+	u32 width = ctx->pix.width;
+	u32 height = ctx->pix.height;
+	u32 format = ctx->pix.pixelformat;
+	u32 y_size = width * height;
+	u32 cb_size = 0, cr_size = 0;
+	u32 i, size;
+	dma_addr_t *curr = &ctrl->mem.curr;
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	int err;
+	struct cma_info	mem_info;
+#endif
+
+	switch (format) {
+	case V4L2_PIX_FMT_RGB32:
+		size = PAGE_ALIGN(y_size << 2);
+		break;
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YUYV:
+		size = PAGE_ALIGN(y_size << 1);
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		cb_size = y_size >> 2;
+		cr_size = y_size >> 2;
+		size = PAGE_ALIGN(y_size + cb_size + cr_size);
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV21:
+		cb_size = y_size >> 1;
+		size = PAGE_ALIGN(y_size + cb_size);
+		break;
+	case V4L2_PIX_FMT_NV12T:
+		fimc_get_nv12t_size(width, height, &y_size, &cb_size);
+		size = PAGE_ALIGN(y_size + cb_size);
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n", __func__, format);
+		return -EINVAL;
+	}
+
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	ctrl->mem.size = size * FIMC_OUTBUFS;
+	err = cma_info(&mem_info, ctrl->dev, 0);
+	printk(KERN_DEBUG "%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x req_size : 0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size,
+			ctrl->mem.size);
+	if (err || (mem_info.free_size < ctrl->mem.size)) {
+		fimc_err("%s: get cma info failed\n", __func__);
+		ctrl->mem.size = 0;
+		ctrl->mem.base = 0;
+		return -ENOMEM;
+	} else {
+		ctrl->mem.base = (dma_addr_t)cma_alloc
+			(ctrl->dev, ctrl->cma_name, (size_t)ctrl->mem.size, 0);
+	}
+
+	fimc_dbg("%s : ctrl->mem.base = 0x%x\n", __func__, ctrl->mem.base);
+	fimc_dbg("%s : ctrl->mem.size = 0x%x\n", __func__, ctrl->mem.size);
+
+	ctrl->mem.curr = ctrl->mem.base;
+#endif
+
+	if ((*curr + size * FIMC_OUTBUFS) > (ctrl->mem.base + ctrl->mem.size)) {
+		fimc_err("%s: Reserved memory is not sufficient\n", __func__);
+		fimc_err("ctrl->mem.base = 0x%x\n", ctrl->mem.base);
+		fimc_err("ctrl->mem.size = 0x%x\n", ctrl->mem.size);
+		fimc_err("*curr          = 0x%x\n", *curr);
+		fimc_err("size           = 0x%x\n", size);
+		fimc_err("FIMC_OUTBUFS   = 0x%x\n", FIMC_OUTBUFS);
+		return -EINVAL;
+	}
+
+	/* Initialize source buffer addr */
+	switch (format) {
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YUYV:
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->src[i].base[FIMC_ADDR_Y] = *curr;
+			ctx->src[i].length[FIMC_ADDR_Y] = size;
+			ctx->src[i].base[FIMC_ADDR_CB] = 0;
+			ctx->src[i].length[FIMC_ADDR_CB] = 0;
+			ctx->src[i].base[FIMC_ADDR_CR] = 0;
+			ctx->src[i].length[FIMC_ADDR_CR] = 0;
+			*curr += size;
+		}
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV21:
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->src[i].base[FIMC_ADDR_Y] = *curr;
+			ctx->src[i].length[FIMC_ADDR_Y] = y_size;
+			ctx->src[i].base[FIMC_ADDR_CB] = *curr + y_size;
+			ctx->src[i].length[FIMC_ADDR_CB] = cb_size;
+			ctx->src[i].base[FIMC_ADDR_CR] = 0;
+			ctx->src[i].length[FIMC_ADDR_CR] = 0;
+			*curr += size;
+		}
+		break;
+	case V4L2_PIX_FMT_NV12T:
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->src[i].base[FIMC_ADDR_Y] = *curr;
+			ctx->src[i].base[FIMC_ADDR_CB] = *curr + y_size;
+			ctx->src[i].length[FIMC_ADDR_Y] = y_size;
+			ctx->src[i].length[FIMC_ADDR_CB] = cb_size;
+			ctx->src[i].base[FIMC_ADDR_CR] = 0;
+			ctx->src[i].length[FIMC_ADDR_CR] = 0;
+			*curr += size;
+		}
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->src[i].base[FIMC_ADDR_Y] = *curr;
+			ctx->src[i].base[FIMC_ADDR_CB] = *curr + y_size;
+			ctx->src[i].base[FIMC_ADDR_CR] = *curr + y_size + cb_size;
+			ctx->src[i].length[FIMC_ADDR_Y] = y_size;
+			ctx->src[i].length[FIMC_ADDR_CB] = cb_size;
+			ctx->src[i].length[FIMC_ADDR_CR] = cr_size;
+			*curr += size;
+		}
+		break;
+
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n", __func__, format);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_set_dst_buf(struct fimc_control *ctrl,
+				   struct fimc_ctx *ctx)
+{
+	dma_addr_t *curr = &ctrl->mem.curr;
+	dma_addr_t end;
+	u32 width = ctrl->fb.lcd_hres;
+	u32 height = ctrl->fb.lcd_vres;
+	u32 i, size;
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	int err;
+	struct cma_info	mem_info;
+#endif
+
+	end = ctrl->mem.base + ctrl->mem.size;
+	size = PAGE_ALIGN(width * height * 4);
+
+#ifdef	CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+	ctrl->mem.size = size * FIMC_OUTBUFS;
+	err = cma_info(&mem_info, ctrl->dev, 0);
+	printk(KERN_DEBUG "%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x req_size=0x%x\n",
+			__func__, mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size,
+			ctrl->mem.size);
+	if (err || (mem_info.free_size < ctrl->mem.size)) {
+		fimc_err("%s: get cma info failed\n", __func__);
+		ctrl->mem.size = 0;
+		ctrl->mem.base = 0;
+		return -ENOMEM;
+	} else {
+		ctrl->mem.base = (dma_addr_t)cma_alloc
+			(ctrl->dev, ctrl->cma_name,
+			(size_t) (size * FIMC_OUTBUFS), 0);
+	}
+
+	fimc_dbg("%s : ctrl->mem.base = 0x%x\n", __func__, ctrl->mem.base);
+	fimc_dbg("%s : ctrl->mem.size = 0x%x\n", __func__, ctrl->mem.size);
+
+	end = ctrl->mem.base + (size * FIMC_OUTBUFS);
+	ctrl->mem.curr = ctrl->mem.base;
+#endif
+
+	if ((*curr + (size * FIMC_OUTBUFS)) > end) {
+		fimc_err("%s: Reserved memory is not sufficient\n", __func__);
+		fimc_err("ctrl->mem.base = 0x%x\n", ctrl->mem.base);
+		fimc_err("ctrl->mem.size = 0x%x\n", ctrl->mem.size);
+		fimc_err("*curr          = 0x%x\n", *curr);
+		fimc_err("size           = 0x%x\n", size);
+		fimc_err("FIMC_OUTBUFS   = 0x%x\n", FIMC_OUTBUFS);
+		return -EINVAL;
+	}
+
+	/* Initialize destination buffer addr */
+	for (i = 0; i < FIMC_OUTBUFS; i++) {
+		ctx->dst[i].base[FIMC_ADDR_Y] = *curr;
+		ctx->dst[i].length[FIMC_ADDR_Y] = size;
+		ctx->dst[i].base[FIMC_ADDR_CB] = 0;
+		ctx->dst[i].length[FIMC_ADDR_CB] = 0;
+		ctx->dst[i].base[FIMC_ADDR_CR] = 0;
+		ctx->dst[i].length[FIMC_ADDR_CR] = 0;
+		*curr += size;
+	}
+
+	return 0;
+}
+
+static int fimc_set_rot_degree(struct fimc_control *ctrl,
+			       struct fimc_ctx *ctx,
+			       int degree)
+{
+	switch (degree) {
+	case 0:		/* fall through */
+	case 90:	/* fall through */
+	case 180:	/* fall through */
+	case 270:
+		ctx->rotate = degree;
+		break;
+
+	default:
+		fimc_err("Invalid rotate value : %d\n", degree);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int fimc_outdev_check_param(struct fimc_control *ctrl,
+			    struct fimc_ctx *ctx)
+{
+	struct v4l2_rect dst, bound;
+	u32 rot = 0;
+	int ret = 0, i, exclusive = 0;
+
+	rot = fimc_mapping_rot_flip(ctx->rotate, ctx->flip);
+	dst.top = ctx->win.w.top;
+	dst.left = ctx->win.w.left;
+	dst.width = ctx->win.w.width;
+	dst.height = ctx->win.w.height;
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:		/* fall through */
+	case FIMC_OVLY_DMA_AUTO:	/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		if (rot & FIMC_ROT) {
+			bound.width = ctrl->fb.lcd_vres;
+			bound.height = ctrl->fb.lcd_hres;
+		} else {
+			bound.width = ctrl->fb.lcd_hres;
+			bound.height = ctrl->fb.lcd_vres;
+		}
+		break;
+	case FIMC_OVLY_NONE_SINGLE_BUF:	/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		bound.width = ctx->fbuf.fmt.width;
+		bound.height = ctx->fbuf.fmt.height;
+		break;
+
+	default:
+		fimc_err("%s: invalid ovelay mode.\n", __func__);
+		return -EINVAL;
+	}
+
+	if ((dst.left + dst.width) > bound.width) {
+		fimc_err("Horizontal position setting is failed\n");
+		fimc_err("\tleft = %d, width = %d, bound width = %d,\n",
+				dst.left, dst.width, bound.width);
+		ret = -EINVAL;
+	} else if ((dst.top + dst.height) > bound.height) {
+		fimc_err("Vertical position setting is failed\n");
+		fimc_err("\ttop = %d, height = %d, bound height = %d,\n",
+				dst.top, dst.height, bound.height);
+		ret = -EINVAL;
+	}
+
+	if ((ctx->status != FIMC_STREAMOFF) &&
+	    (ctx->status != FIMC_READY_ON) &&
+	    (ctx->status != FIMC_STREAMON_IDLE) &&
+	    (ctx->status != FIMC_ON_IDLE_SLEEP)) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	/* check other open instance */
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		switch (ctrl->out->ctx[i].overlay.mode) {
+		case FIMC_OVLY_FIFO:		/* fall through */
+		case FIMC_OVLY_DMA_AUTO:	/* fall through */
+		case FIMC_OVLY_DMA_MANUAL:
+			exclusive++;
+			break;
+		case FIMC_OVLY_NONE_SINGLE_BUF:	/* fall through */
+		case FIMC_OVLY_NONE_MULTI_BUF:	/* fall through */
+		case FIMC_OVLY_NOT_FIXED:
+			break;
+		}
+	}
+
+	if (exclusive > 1) {
+		for (i = 0; i < FIMC_MAX_CTXS; i++)
+			fimc_err("%s: ctx %d mode = %d", __func__, i,
+					ctrl->out->ctx[i].overlay.mode);
+		return -EBUSY;
+	}
+
+	return ret;
+}
+
+static void fimc_outdev_set_src_format(struct fimc_control *ctrl,
+				       u32 pixfmt, enum v4l2_field field)
+{
+	fimc_hwset_input_burst_cnt(ctrl, 4);
+	fimc_hwset_input_colorspace(ctrl, pixfmt);
+	fimc_hwset_input_yuv(ctrl, pixfmt);
+	fimc_hwset_input_rgb(ctrl, pixfmt);
+	fimc_hwset_intput_field(ctrl, field);
+	fimc_hwset_ext_rgb(ctrl, 1);
+	fimc_hwset_input_addr_style(ctrl, pixfmt);
+}
+
+static void fimc_outdev_set_dst_format(struct fimc_control *ctrl,
+				       struct v4l2_pix_format *pixfmt)
+{
+	fimc_hwset_output_colorspace(ctrl, pixfmt->pixelformat);
+	fimc_hwset_output_yuv(ctrl, pixfmt->pixelformat);
+	fimc_hwset_output_rgb(ctrl, pixfmt->pixelformat);
+	fimc_hwset_output_scan(ctrl, pixfmt);
+	fimc_hwset_output_addr_style(ctrl, pixfmt->pixelformat);
+}
+
+static void fimc_outdev_set_format(struct fimc_control *ctrl,
+				   struct fimc_ctx *ctx)
+{
+	struct v4l2_pix_format pixfmt;
+	memset(&pixfmt, 0, sizeof(pixfmt));
+
+	fimc_outdev_set_src_format(ctrl, ctx->pix.pixelformat, ctx->pix.field);
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:		/* fall through */
+	case FIMC_OVLY_DMA_AUTO:	/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:	/* Non-destructive overlay mode */
+		if (ctx->pix.field == V4L2_FIELD_NONE) {
+			pixfmt.pixelformat = V4L2_PIX_FMT_RGB32;
+			pixfmt.field = V4L2_FIELD_NONE;
+		} else if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB) {
+			pixfmt.pixelformat = V4L2_PIX_FMT_YUV444;
+			pixfmt.field = V4L2_FIELD_INTERLACED_TB;
+		} else if (ctx->pix.field == V4L2_FIELD_ANY) {
+			pixfmt.pixelformat = V4L2_PIX_FMT_RGB32;
+			pixfmt.field = V4L2_FIELD_NONE;
+		}
+
+		break;
+	case FIMC_OVLY_NONE_SINGLE_BUF:	/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:	/* Destructive overlay mode */
+		pixfmt.pixelformat = ctx->fbuf.fmt.pixelformat;
+		pixfmt.field = V4L2_FIELD_NONE;
+
+		break;
+	default:
+		fimc_err("Invalid overlay mode %d\n", ctx->overlay.mode);
+		break;
+	}
+
+	fimc_outdev_set_dst_format(ctrl, &pixfmt);
+}
+
+static void fimc_outdev_set_path(struct fimc_control *ctrl,
+				 struct fimc_ctx *ctx)
+{
+	/* source path */
+	fimc_hwset_input_source(ctrl, FIMC_SRC_MSDMA);
+
+	if (ctx->overlay.mode == FIMC_OVLY_FIFO) {
+		fimc_hwset_enable_lcdfifo(ctrl);
+		fimc_hwset_enable_autoload(ctrl);
+	} else {
+		fimc_hwset_disable_lcdfifo(ctrl);
+		fimc_hwset_disable_autoload(ctrl);
+	}
+}
+
+static void fimc_outdev_set_rot(struct fimc_control *ctrl,
+				struct fimc_ctx *ctx)
+{
+	u32 rot = ctx->rotate;
+	u32 flip = ctx->flip;
+
+	if (ctx->overlay.mode == FIMC_OVLY_FIFO) {
+		fimc_hwset_input_rot(ctrl, rot, flip);
+		fimc_hwset_input_flip(ctrl, rot, flip);
+		fimc_hwset_output_rot_flip(ctrl, 0, 0);
+	} else {
+		fimc_hwset_input_rot(ctrl, 0, 0);
+		fimc_hwset_input_flip(ctrl, 0, 0);
+		fimc_hwset_output_rot_flip(ctrl, rot, flip);
+	}
+}
+
+static void fimc_outdev_set_src_dma_offset(struct fimc_control *ctrl,
+					   struct fimc_ctx *ctx)
+{
+	struct v4l2_rect bound, crop;
+	u32 pixfmt = ctx->pix.pixelformat;
+
+	bound.width = ctx->pix.width;
+	bound.height = ctx->pix.height;
+
+	crop.left = ctx->crop.left;
+	crop.top = ctx->crop.top;
+	crop.width = ctx->crop.width;
+	crop.height = ctx->crop.height;
+
+	fimc_hwset_input_offset(ctrl, pixfmt, &bound, &crop);
+}
+
+static int fimc4x_outdev_check_src_size(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx,
+					struct v4l2_rect *real,
+					struct v4l2_rect *org)
+{
+	u32 rot = ctx->rotate;
+
+	if ((ctx->overlay.mode == FIMC_OVLY_FIFO) &&
+	    ((rot == 90) || (rot == 270))) {
+		/* Input Rotator */
+		if (real->height % 16) {
+			fimc_err("SRC Real_H(%d): multiple of 16 !\n",
+					real->height);
+			return -EINVAL;
+		}
+
+		if (ctx->sc.pre_hratio) {
+			if (real->height % (ctx->sc.pre_hratio * 4)) {
+				fimc_err("SRC Real_H(%d): multiple of "
+						"4*pre_hratio(%d)\n",
+						real->height,
+						ctx->sc.pre_hratio);
+				return -EINVAL;
+			}
+		}
+
+		if (ctx->sc.pre_vratio) {
+			if (real->width % ctx->sc.pre_vratio) {
+				fimc_err("SRC Real_W(%d): multiple of "
+						"pre_vratio(%d)\n",
+						real->width,
+						ctx->sc.pre_vratio);
+				return -EINVAL;
+			}
+		}
+
+		if (real->height < 16) {
+			fimc_err("SRC Real_H(%d): Min 16\n", real->height);
+			return -EINVAL;
+		}
+		if (real->width < 8) {
+			fimc_err("SRC Real_W(%d): Min 8\n", real->width);
+			return -EINVAL;
+		}
+	} else {
+		/* No Input Rotator */
+		if (real->height < 8) {
+			fimc_err("SRC Real_H(%d): Min 8\n", real->height);
+			return -EINVAL;
+		}
+
+		if (real->width < 16) {
+			fimc_err("SRC Real_W(%d): Min 16\n", real->width);
+			return -EINVAL;
+		}
+
+		if (real->width > ctrl->limit->real_w_no_rot) {
+			fimc_err("SRC REAL_W(%d): Real_W <= %d\n", real->width,
+					ctrl->limit->real_w_no_rot);
+			return -EINVAL;
+		}
+	}
+
+	if (org->height < real->height) {
+		fimc_err("SRC Org_H(%d): larger than Real_H(%d)\n",
+				org->height, real->height);
+		return -EINVAL;
+	}
+
+	if (org->width < real->width) {
+		fimc_err("SRC Org_W: Org_W(%d) >= Real_W(%d)\n", org->width,
+				real->width);
+		return -EINVAL;
+	}
+
+	if (ctx->sc.pre_vratio) {
+		if (real->height % ctx->sc.pre_vratio) {
+			fimc_err("SRC Real_H(%d): multi of pre_vratio(%d)!\n",
+					real->height, ctx->sc.pre_vratio);
+			return -EINVAL;
+		}
+	}
+
+	if (real->width % 16) {
+		fimc_err("SRC Real_W(%d): multiple of 16 !\n", real->width);
+		return -EINVAL;
+	}
+
+	if (ctx->sc.pre_hratio) {
+		if (real->width % (ctx->sc.pre_hratio * 4)) {
+			fimc_err("SRC Real_W(%d): "
+					"multiple of 4 * pre_hratio(%d)!\n",
+					real->width, ctx->sc.pre_hratio);
+			return -EINVAL;
+		}
+	}
+
+	if (org->width % 16) {
+		fimc_err("SRC Org_W(%d): multiple of 16\n", org->width);
+		return -EINVAL;
+	}
+
+	if (org->height < 8) {
+		fimc_err("SRC Org_H(%d): Min 8\n", org->height);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc50_outdev_check_src_size(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx,
+					struct v4l2_rect *real,
+					struct v4l2_rect *org)
+{
+	u32 rot = ctx->rotate;
+	u32 pixelformat = ctx->pix.pixelformat;
+
+	if ((ctx->overlay.mode == FIMC_OVLY_FIFO) &&
+	    ((rot == 90) || (rot == 270))) {
+		/* Input Rotator */
+		switch (pixelformat) {
+		case V4L2_PIX_FMT_YUV422P:	/* fall through */
+		case V4L2_PIX_FMT_YVU420:
+			if (real->height % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->height);
+				return -EINVAL;
+			}
+		}
+
+		if (real->height < 16) {
+			fimc_err("SRC Real_H(%d): Min 16\n", real->height);
+			return -EINVAL;
+		}
+		if (real->width < 8) {
+			fimc_err("SRC Real_W(%d): Min 8\n", real->width);
+			return -EINVAL;
+		}
+	} else {
+		/* No Input Rotator */
+		if (real->height < 8) {
+			fimc_err("SRC Real_H(%d): Min 8\n", real->height);
+			return -EINVAL;
+		}
+
+		if (real->width < 16) {
+			fimc_err("SRC Real_W(%d): Min 16\n", real->width);
+			return -EINVAL;
+		}
+
+		if (real->width > ctrl->limit->real_w_no_rot) {
+			fimc_err("SRC REAL_W(%d): Real_W <= %d\n", real->width,
+					ctrl->limit->real_w_no_rot);
+			return -EINVAL;
+		}
+	}
+
+	if (org->height < real->height) {
+		fimc_err("SRC Org_H: larger than Real_H, "
+				"org %dx%d, real %dx%d\n",
+				org->width, org->height,
+				real->width, real->height);
+		return -EINVAL;
+	}
+
+	if (org->width < real->width) {
+		fimc_err("SRC Org_W: Org_W(%d) >= Real_W(%d)\n",
+				org->width, real->width);
+		return -EINVAL;
+	}
+
+	if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB) {
+		switch (pixelformat) {
+		case V4L2_PIX_FMT_YUV444:	/* fall through */
+		case V4L2_PIX_FMT_RGB32:
+			if (real->height % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->height);
+				return -EINVAL;
+			}
+			break;
+		case V4L2_PIX_FMT_YUV422P:
+			if (real->height % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->height);
+				return -EINVAL;
+			} else if (real->width % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->width);
+				return -EINVAL;
+			}
+			break;
+		case V4L2_PIX_FMT_YVU420:
+			if (real->height % 4) {
+				fimc_err("SRC Real_H(%d): multiple of 4\n",
+						real->height);
+				return -EINVAL;
+			} else if (real->width % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->width);
+				return -EINVAL;
+			}
+			break;
+		}
+	} else if (ctx->pix.field == V4L2_FIELD_NONE) {
+		if (pixelformat == V4L2_PIX_FMT_YUV422P) {
+			if (real->height % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->height);
+				return -EINVAL;
+			} else if (real->width % 2) {
+				fimc_err("SRC Real_H(%d): multiple of 2\n",
+						real->width);
+				return -EINVAL;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_set_src_dma_size(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	struct v4l2_rect real, org;
+	int ret = 0;
+
+	real.width = ctx->crop.width;
+	real.height = ctx->crop.height;
+	org.width = ctx->pix.width;
+	org.height = ctx->pix.height;
+
+	if (pdata->hw_ver >= 0x50)
+		ret = fimc50_outdev_check_src_size(ctrl, ctx, &real, &org);
+	else
+		ret = fimc4x_outdev_check_src_size(ctrl, ctx, &real, &org);
+
+	if (ret < 0)
+		return ret;
+
+	fimc_hwset_org_input_size(ctrl, org.width, org.height);
+	fimc_hwset_real_input_size(ctrl, real.width, real.height);
+
+	return 0;
+}
+
+static void fimc_outdev_set_dst_dma_offset(struct fimc_control *ctrl,
+					   struct fimc_ctx *ctx)
+{
+	struct v4l2_rect bound, win;
+	struct v4l2_rect *w = &ctx->win.w;
+	u32 pixfmt = ctx->fbuf.fmt.pixelformat;
+
+	memset(&bound, 0, sizeof(bound));
+	memset(&win, 0, sizeof(win));
+
+	switch (ctx->rotate) {
+	case 0:
+		bound.width = ctx->fbuf.fmt.width;
+		bound.height = ctx->fbuf.fmt.height;
+
+		win.left = w->left;
+		win.top = w->top;
+		win.width = w->width;
+		win.height = w->height;
+
+		break;
+	case 90:
+		bound.width = ctx->fbuf.fmt.height;
+		bound.height = ctx->fbuf.fmt.width;
+
+		win.left = ctx->fbuf.fmt.height - (w->height + w->top);
+		win.top = w->left;
+		win.width = w->height;
+		win.height = w->width;
+
+		break;
+	case 180:
+		bound.width = ctx->fbuf.fmt.width;
+		bound.height = ctx->fbuf.fmt.height;
+
+		win.left = ctx->fbuf.fmt.width - (w->left + w->width);
+		win.top = ctx->fbuf.fmt.height - (w->top + w->height);
+		win.width = w->width;
+		win.height = w->height;
+
+		break;
+	case 270:
+		bound.width = ctx->fbuf.fmt.height;
+		bound.height = ctx->fbuf.fmt.width;
+
+		win.left = ctx->win.w.top;
+		win.top = ctx->fbuf.fmt.width - (w->left + w->width);
+		win.width = w->height;
+		win.height = w->width;
+
+		break;
+	default:
+		fimc_err("Rotation degree is invalid(%d)\n", ctx->rotate);
+		break;
+	}
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:		/* fall through */
+	case FIMC_OVLY_DMA_AUTO:	/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		memset(&bound, 0, sizeof(bound));
+		memset(&win, 0, sizeof(win));
+		fimc_hwset_output_offset(ctrl, pixfmt, &bound, &win);
+		break;
+	default:
+		fimc_hwset_output_offset(ctrl, pixfmt, &bound, &win);
+		break;
+	}
+
+	fimc_dbg("bound:width(%d), height(%d)\n", bound.width, bound.height);
+	fimc_dbg("win:width(%d), height(%d)\n", win.width, win.height);
+	fimc_dbg("win:top(%d), left(%d)\n", win.top, win.left);
+}
+
+static int fimc_outdev_check_dst_size(struct fimc_control *ctrl,
+				      struct fimc_ctx *ctx,
+				      struct v4l2_rect *real,
+				      struct v4l2_rect *org)
+{
+	u32 rot = ctx->rotate;
+	__u32 pixel_type;
+
+	pixel_type = fimc_get_pixel_format_type(ctx->fbuf.fmt.pixelformat);
+
+	if (FIMC_YUV420 == pixel_type && real->height % 2) {
+		fimc_err("DST Real_H(%d): even number for YUV420 formats\n",
+				real->height);
+		return -EINVAL;
+	}
+
+	if ((ctx->overlay.mode != FIMC_OVLY_FIFO) &&
+	    ((rot == 90) || (rot == 270))) {
+		/* Use Output Rotator */
+		if (org->height < real->width) {
+			fimc_err("DST Org_H: Org_H(%d) >= Real_W(%d)\n",
+					org->height, real->width);
+			return -EINVAL;
+		}
+
+		if (org->width < real->height) {
+			fimc_err("DST Org_W: Org_W(%d) >= Real_H(%d)\n",
+					org->width, real->height);
+			return -EINVAL;
+		}
+
+		if (real->height > ctrl->limit->trg_h_rot) {
+			fimc_err("DST REAL_H: Real_H(%d) <= %d\n", real->height,
+					ctrl->limit->trg_h_rot);
+			return -EINVAL;
+		}
+	} else if (ctx->overlay.mode != FIMC_OVLY_FIFO) {
+		/* No Output Rotator */
+		if (org->height < 8) {
+			fimc_err("DST Org_H(%d): Min 8\n", org->height);
+			return -EINVAL;
+		}
+
+		if (org->height < real->height) {
+			fimc_err("DST Org_H: Org_H(%d) >= Real_H(%d)\n",
+					org->height, real->height);
+			return -EINVAL;
+		}
+		/*
+		if (org->width % 8) {
+			fimc_err("DST Org_W: multiple of 8\n");
+			return -EINVAL;
+		}*/
+
+		if (org->width < real->width) {
+			fimc_err("DST Org_W: Org_W(%d) >= Real_W(%d)\n",
+					org->width, real->width);
+			return -EINVAL;
+		}
+
+		if (real->height > ctrl->limit->trg_h_no_rot) {
+			fimc_err("DST REAL_H: Real_H(%d) <= %d\n", real->height,
+					ctrl->limit->trg_h_no_rot);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_set_dst_dma_size(struct fimc_control *ctrl,
+					struct fimc_ctx *ctx)
+{
+	struct v4l2_rect org, real;
+	int ret = -1;
+
+	memset(&org, 0, sizeof(org));
+	memset(&real, 0, sizeof(real));
+
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_NONE_MULTI_BUF:	/* fall through */
+	case FIMC_OVLY_NONE_SINGLE_BUF:
+		real.width = ctx->win.w.width;
+		real.height = ctx->win.w.height;
+
+		switch (ctx->rotate) {
+		case 0:		/* fall through */
+		case 180:
+			org.width = ctx->fbuf.fmt.width;
+			org.height = ctx->fbuf.fmt.height;
+			break;
+		case 90:	/* fall through */
+		case 270:
+			org.width = ctx->fbuf.fmt.height;
+			org.height = ctx->fbuf.fmt.width;
+			break;
+		default:
+			fimc_err("Rotation degree is invalid(%d)\n",
+					ctx->rotate);
+			break;
+		}
+
+		break;
+
+	case FIMC_OVLY_DMA_MANUAL:	/* fall through */
+	case FIMC_OVLY_DMA_AUTO:
+		real.width = ctx->win.w.width;
+		real.height = ctx->win.w.height;
+
+		switch (ctx->rotate) {
+		case 0:		/* fall through */
+		case 180:
+			org.width = ctx->win.w.width;
+			org.height = ctx->win.w.height;
+			break;
+		case 90:	/* fall through */
+		case 270:
+			org.width = ctx->win.w.height;
+			org.height = ctx->win.w.width;
+			break;
+		default:
+			fimc_err("Rotation degree is invalid(%d)\n",
+					ctx->rotate);
+			break;
+		}
+
+		break;
+	case FIMC_OVLY_FIFO:
+		switch (ctx->rotate) {
+		case 0:		/* fall through */
+		case 180:
+			real.width = ctx->win.w.width;
+			real.height = ctx->win.w.height;
+			org.width = ctrl->fb.lcd_hres;
+			org.height = ctrl->fb.lcd_vres;
+			break;
+		case 90:	/* fall through */
+		case 270:
+			real.width = ctx->win.w.height;
+			real.height = ctx->win.w.width;
+			org.width = ctrl->fb.lcd_vres;
+			org.height = ctrl->fb.lcd_hres;
+			break;
+
+		default:
+			fimc_err("Rotation degree is invalid(%d)\n",
+					ctx->rotate);
+			break;
+		}
+
+		break;
+	default:
+		break;
+	}
+
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO)
+		fimc_outdev_dma_auto_dst_resize(&org);
+
+	fimc_dbg("DST org: width(%d), height(%d)\n", org.width, org.height);
+	fimc_dbg("DST real: width(%d), height(%d)\n", real.width, real.height);
+
+	ret = fimc_outdev_check_dst_size(ctrl, ctx, &real, &org);
+	if (ret < 0)
+		return ret;
+
+	fimc_hwset_output_size(ctrl, real.width, real.height);
+	fimc_hwset_output_area(ctrl, real.width, real.height);
+	fimc_hwset_org_output_size(ctrl, org.width, org.height);
+	fimc_hwset_ext_output_size(ctrl, real.width, real.height);
+
+	return 0;
+}
+
+static void fimc_outdev_calibrate_scale_info(struct fimc_control *ctrl,
+					     struct fimc_ctx *ctx,
+					     struct v4l2_rect *src,
+					     struct v4l2_rect *dst)
+{
+	if (ctx->overlay.mode != FIMC_OVLY_FIFO) {
+		/* OUTPUT ROTATOR */
+		src->width = ctx->crop.width;
+		src->height = ctx->crop.height;
+		dst->width = ctx->win.w.width;
+		dst->height = ctx->win.w.height;
+	} else {
+		/* INPUT ROTATOR */
+		switch (ctx->rotate) {
+		case 0:		/* fall through */
+		case 180:
+			src->width = ctx->crop.width;
+			src->height = ctx->crop.height;
+			dst->width = ctx->win.w.width;
+			dst->height = ctx->win.w.height;
+			break;
+		case 90:	/* fall through */
+		case 270:
+			src->width = ctx->crop.height;
+			src->height = ctx->crop.width;
+			dst->width = ctx->win.w.height;
+			dst->height = ctx->win.w.width;
+			break;
+		default:
+			fimc_err("Rotation degree is invalid(%d)\n",
+					ctx->rotate);
+			break;
+		}
+	}
+
+	fimc_dbg("src->width(%d), src->height(%d)\n", src->width, src->height);
+	fimc_dbg("dst->width(%d), dst->height(%d)\n", dst->width, dst->height);
+}
+
+static int fimc_outdev_check_scaler(struct fimc_control *ctrl,
+				    struct fimc_ctx *ctx,
+				    struct v4l2_rect *src,
+				    struct v4l2_rect *dst)
+{
+	u32 pixels = 0, dstfmt = 0;
+
+	/* Check scaler limitation */
+	if (ctx->sc.pre_dst_width > ctrl->limit->pre_dst_w) {
+		fimc_err("MAX PreDstWidth(%d) is %d\n", ctx->sc.pre_dst_width,
+					ctrl->limit->pre_dst_w);
+		return -EDOM;
+	}
+
+	/* SRC width double boundary check */
+	switch (ctx->pix.pixelformat) {
+	case V4L2_PIX_FMT_RGB32:
+		pixels = 1;
+		break;
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_RGB565:
+		pixels = 2;
+		break;
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		pixels = 8;
+		break;
+	default:
+		fimc_err("Invalid color format(0x%x)\n", ctx->pix.pixelformat);
+		return -EINVAL;
+	}
+
+	if (src->width % pixels) {
+		fimc_err("source width(%d) multiple of %d pixels\n", src->width,
+				pixels);
+		return -EDOM;
+	}
+
+	/* DST width double boundary check */
+	switch (ctx->overlay.mode) {
+	case FIMC_OVLY_FIFO:			/* fall through */
+	case FIMC_OVLY_DMA_AUTO:		/* fall through */
+	case FIMC_OVLY_DMA_MANUAL:
+		dstfmt = V4L2_PIX_FMT_RGB32;
+		break;
+	case FIMC_OVLY_NONE_SINGLE_BUF:		/* fall through */
+	case FIMC_OVLY_NONE_MULTI_BUF:
+		dstfmt = ctx->fbuf.fmt.pixelformat;
+		break;
+	default:
+		break;
+	}
+
+	switch (dstfmt) {
+	case V4L2_PIX_FMT_RGB32:
+		pixels = 1;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+		pixels = 2;
+		break;
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12M:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		pixels = 8;
+		break;
+	default:
+		fimc_err("Invalid color format(0x%x)\n", dstfmt);
+		return -EINVAL;
+	}
+
+	if (dst->width % pixels) {
+		fimc_err("source width(%d) multiple of %d pixels\n",
+				dst->width, pixels);
+		return -EDOM;
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_set_scaler(struct fimc_control *ctrl,
+				  struct fimc_ctx *ctx)
+{
+	struct v4l2_rect src, dst;
+	int ret = 0;
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	memset(&src, 0, sizeof(src));
+	memset(&dst, 0, sizeof(dst));
+
+	fimc_outdev_calibrate_scale_info(ctrl, ctx, &src, &dst);
+
+	ret = fimc_get_scaler_factor(src.width, dst.width,
+			&ctx->sc.pre_hratio, &ctx->sc.hfactor);
+	if (ret < 0) {
+		fimc_err("Fail : Out of Width scale range(%d, %d)\n",
+				src.width, dst.width);
+		return ret;
+	}
+
+	ret = fimc_get_scaler_factor(src.height, dst.height,
+			&ctx->sc.pre_vratio, &ctx->sc.vfactor);
+	if (ret < 0) {
+		fimc_err("Fail : Out of Height scale range(%d, %d)\n",
+				src.height, dst.height);
+		return ret;
+	}
+
+	if (src.width == src.height) {
+		if ((src.width * 10 / dst.width) >= 15 &&
+					(src.width * 10 / dst.width) < 20) {
+			ctx->sc.pre_hratio = 2;
+			ctx->sc.hfactor = 1;
+		}
+		if ((src.height * 10 / dst.height) >= 15 &&
+					(src.height * 10 / dst.height) < 20) {
+			ctx->sc.pre_vratio = 2;
+			ctx->sc.vfactor = 1;
+		}
+	}
+
+	ctx->sc.pre_dst_width = src.width / ctx->sc.pre_hratio;
+	ctx->sc.pre_dst_height = src.height / ctx->sc.pre_vratio;
+
+	if (pdata->hw_ver >= 0x50) {
+		ctx->sc.main_hratio = (src.width << 14) /
+					(dst.width << ctx->sc.hfactor);
+		ctx->sc.main_vratio = (src.height << 14) /
+					(dst.height << ctx->sc.vfactor);
+	} else {
+		ctx->sc.main_hratio = (src.width << 8) /
+					(dst.width << ctx->sc.hfactor);
+		ctx->sc.main_vratio = (src.height << 8) /
+					(dst.height << ctx->sc.vfactor);
+	}
+
+	fimc_dbg("pre_hratio(%d), hfactor(%d), pre_vratio(%d), vfactor(%d)\n",
+		ctx->sc.pre_hratio, ctx->sc.hfactor,
+		ctx->sc.pre_vratio, ctx->sc.vfactor);
+
+
+	fimc_dbg("pre_dst_width(%d), main_hratio(%d), "
+		"pre_dst_height(%d), main_vratio(%d)\n",
+		ctx->sc.pre_dst_width, ctx->sc.main_hratio,
+		ctx->sc.pre_dst_height, ctx->sc.main_vratio);
+
+	ctx->sc.bypass = 0;	/* Input DMA cannot support scaler bypass. */
+	ctx->sc.scaleup_h = (dst.width >= src.width) ? 1 : 0;
+	ctx->sc.scaleup_v = (dst.height >= src.height) ? 1 : 0;
+	ctx->sc.shfactor = 10 - (ctx->sc.hfactor + ctx->sc.vfactor);
+
+	if (pdata->hw_ver < 0x50) {
+		ret = fimc_outdev_check_scaler(ctrl, ctx, &src, &dst);
+		if (ret < 0)
+			return ret;
+	}
+
+	fimc_hwset_prescaler(ctrl, &ctx->sc);
+	fimc_hwset_scaler(ctrl, &ctx->sc);
+
+	return 0;
+}
+
+int fimc_outdev_set_ctx_param(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	int ret;
+	if (ctrl && (ctrl->regs == NULL)) {
+		fimc_dbg("%s FIMC%d power is off: skip to set config\n",
+				__func__, ctrl->id);
+		return 0;
+	}
+#if defined(CONFIG_VIDEO_IPC)
+	u32 use_ipc = 0;
+	struct v4l2_rect src, dst;
+	memset(&src, 0, sizeof(src));
+	memset(&dst, 0, sizeof(dst));
+#endif
+
+	fimc_hwset_sw_reset(ctrl);
+
+	if ((ctrl->status == FIMC_READY_ON) ||
+			(ctrl->status == FIMC_STREAMON_IDLE))
+		fimc_hwset_enable_irq(ctrl, 0, 1);
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	fimc_hwset_output_buf_sequence_all(ctrl, FRAME_SEQ);
+#endif
+
+	fimc_outdev_set_format(ctrl, ctx);
+	fimc_outdev_set_path(ctrl, ctx);
+	fimc_outdev_set_rot(ctrl, ctx);
+
+	fimc_outdev_set_src_dma_offset(ctrl, ctx);
+	ret = fimc_outdev_set_src_dma_size(ctrl, ctx);
+	if (ret < 0)
+		return ret;
+
+	fimc_outdev_set_dst_dma_offset(ctrl, ctx);
+
+	ret = fimc_outdev_set_dst_dma_size(ctrl, ctx);
+	if (ret < 0)
+		return ret;
+
+	ret = fimc_outdev_set_scaler(ctrl, ctx);
+	if (ret < 0)
+		return ret;
+
+#if defined(CONFIG_VIDEO_IPC)
+	if (ctx->overlay.mode == FIMC_OVLY_FIFO)
+		if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB)
+			use_ipc = 1;
+
+	if (use_ipc) {
+		fimc_outdev_calibrate_scale_info(ctrl, ctx, &src, &dst);
+		ret = ipc_init(dst.width, dst.height/2, IPC_2D);
+		if (ret < 0)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+int fimc_fimd_rect(const struct fimc_control *ctrl,
+		   const struct fimc_ctx *ctx,
+		   struct v4l2_rect *fimd_rect)
+{
+	switch (ctx->rotate) {
+	case 0:
+		fimd_rect->left = ctx->win.w.left;
+		fimd_rect->top = ctx->win.w.top;
+		fimd_rect->width = ctx->win.w.width;
+		fimd_rect->height = ctx->win.w.height;
+
+		break;
+
+	case 90:
+		fimd_rect->left = ctrl->fb.lcd_hres -
+				(ctx->win.w.top + ctx->win.w.height);
+		fimd_rect->top = ctx->win.w.left;
+		fimd_rect->width = ctx->win.w.height;
+		fimd_rect->height = ctx->win.w.width;
+
+		break;
+
+	case 180:
+		fimd_rect->left = ctrl->fb.lcd_hres -
+				(ctx->win.w.left + ctx->win.w.width);
+		fimd_rect->top = ctrl->fb.lcd_vres -
+				(ctx->win.w.top + ctx->win.w.height);
+		fimd_rect->width = ctx->win.w.width;
+		fimd_rect->height = ctx->win.w.height;
+
+		break;
+
+	case 270:
+		fimd_rect->left = ctx->win.w.top;
+		fimd_rect->top = ctrl->fb.lcd_vres -
+				(ctx->win.w.left + ctx->win.w.width);
+		fimd_rect->width = ctx->win.w.height;
+		fimd_rect->height = ctx->win.w.width;
+
+		break;
+
+	default:
+		fimc_err("Rotation degree is invalid(%d)\n", ctx->rotate);
+		return -EINVAL;
+
+		break;
+	}
+
+	return 0;
+}
+
+int fimc_start_fifo(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	struct v4l2_rect fimd_rect;
+	struct fb_var_screeninfo var;
+	struct s3cfb_user_window window;
+	int ret = -1;
+	u32 id = ctrl->id;
+
+	memset(&fimd_rect, 0, sizeof(struct v4l2_rect));
+	ret = fimc_fimd_rect(ctrl, ctx, &fimd_rect);
+	if (ret < 0) {
+		fimc_err("fimc_fimd_rect fail\n");
+		return -EINVAL;
+	}
+
+	/* Get WIN var_screeninfo */
+	ret = s3cfb_direct_ioctl(id, FBIOGET_VSCREENINFO,
+						(unsigned long)&var);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(FBIOGET_VSCREENINFO) fail\n");
+		return -EINVAL;
+	}
+
+	/* Don't allocate the memory. */
+	if (ctx->pix.field == V4L2_FIELD_NONE)
+		ret = s3cfb_direct_ioctl(id,
+					S3CFB_SET_WIN_PATH, DATA_PATH_FIFO);
+	else if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB)
+		ret = s3cfb_direct_ioctl(id,
+					S3CFB_SET_WIN_PATH, DATA_PATH_IPC);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_PATH) fail\n");
+		return -EINVAL;
+	}
+
+	ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_MEM, DMA_MEM_NONE);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_MEM) fail\n");
+		return -EINVAL;
+	}
+
+	ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_ADDR, 0x00000000);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_SET_WIN_ADDR) fail\n");
+		return -EINVAL;
+	}
+
+	/* Update WIN size */
+	var.xres_virtual = fimd_rect.width;
+	var.yres_virtual = fimd_rect.height;
+	var.xres = fimd_rect.width;
+	var.yres = fimd_rect.height;
+	ret = s3cfb_direct_ioctl(id, FBIOPUT_VSCREENINFO,
+					(unsigned long)&var);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(FBIOPUT_VSCREENINFO) fail\n");
+		return -EINVAL;
+	}
+
+	/* Update WIN position */
+	window.x = fimd_rect.left;
+	window.y = fimd_rect.top;
+	ret = s3cfb_direct_ioctl(id, S3CFB_WIN_POSITION,
+			(unsigned long)&window);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_WIN_POSITION) fail\n");
+		return -EINVAL;
+	}
+
+	/* Open WIN FIFO */
+	ret = ctrl->fb.open_fifo(id, 0, fimc_outdev_start_camif, (void *)ctrl);
+	if (ret < 0) {
+		fimc_err("FIMD FIFO close fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int fimc_outdev_overlay_buf(struct file *filp,
+			    struct fimc_control *ctrl,
+			    struct fimc_ctx *ctx)
+{
+	int ret = 0, i;
+	struct fimc_overlay_buf *buf;
+
+	buf = &ctx->overlay.buf;
+
+	for (i = 0; i < FIMC_OUTBUFS; i++) {
+		ctx->overlay.req_idx = i;
+		buf->size[i] = ctx->dst[i].length[0];
+		buf->phy_addr[i] = ctx->dst[i].base[0];
+		buf->vir_addr[i] = do_mmap(filp, 0, buf->size[i],
+					PROT_READ|PROT_WRITE, MAP_SHARED, 0);
+		if (buf->vir_addr[i] == -EINVAL) {
+			fimc_err("%s: fail\n", __func__);
+			return -EINVAL;
+		}
+
+		fimc_dbg("idx : %d, size(0x%08x), phy_addr(0x%08x), "
+				"vir_addr(0x%08x)\n", i, buf->size[i],
+				buf->phy_addr[i], buf->vir_addr[i]);
+	}
+
+	ctx->overlay.req_idx = -1;
+
+	return ret;
+}
+
+int fimc_reqbufs_output(void *fh, struct v4l2_requestbuffers *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_ctx *ctx;
+	struct fimc_overlay_buf *buf;
+	struct mm_struct *mm = current->mm;
+	enum fimc_overlay_mode mode;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int ret = -1, i;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	buf = &ctx->overlay.buf;
+	mode = ctx->overlay.mode;
+
+	fimc_info1("%s: called\n", __func__);
+
+	if (ctx->status != FIMC_STREAMOFF && b->count != 0) {
+		fimc_dump_context(ctrl, ctx);
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	if (ctx->is_requested == 1 && b->count != 0) {
+		fimc_err("Buffers were already requested\n");
+		return -EBUSY;
+	}
+
+	if (b->count > FIMC_OUTBUFS) {
+		fimc_warn("The buffer count is modified by driver "
+				"from %d to %d\n", b->count, FIMC_OUTBUFS);
+		b->count = FIMC_OUTBUFS;
+	}
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	fimc_hwset_output_buf_sequence_all(ctrl, FRAME_SEQ);
+#endif
+
+	fimc_init_out_buf(ctx);
+	ctx->is_requested = 0;
+
+	if (b->count == 0) {
+		ctrl->mem.curr = ctrl->mem.base;
+		ctx->status = FIMC_STREAMOFF;
+#ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
+		if (ctrl->mem.base && b->memory == V4L2_MEMORY_MMAP) {
+			cma_free(ctrl->mem.base);
+			ctrl->mem.base = 0;
+			ctrl->mem.size = 0;
+		}
+#endif
+		switch (ctx->overlay.mode) {
+		case FIMC_OVLY_DMA_AUTO:	/* fall through */
+		case FIMC_OVLY_DMA_MANUAL:
+			for (i = 0; i < FIMC_OUTBUFS; i++) {
+				if (buf->vir_addr[i]) {
+					ret = do_munmap(mm,
+							buf->vir_addr[i],
+							buf->size[i]);
+					if (ret < 0)
+						fimc_err("%s: do_munmap fail. "
+						"vir_addr[%d](0x%08x)\n",
+						__func__, i, buf->vir_addr[i]);
+				}
+			}
+			break;
+		default:
+			break;
+		}
+	} else {
+		/* initialize source buffers */
+		if (b->memory == V4L2_MEMORY_MMAP) {
+			ret = fimc_outdev_set_src_buf(ctrl, ctx);
+			ctx->overlay.req_idx = FIMC_MMAP_IDX;
+			if (ret)
+				return ret;
+		} else if (b->memory == V4L2_MEMORY_USERPTR) {
+			if (mode == FIMC_OVLY_DMA_AUTO ||
+					mode == FIMC_OVLY_NOT_FIXED)
+				ctx->overlay.req_idx = FIMC_USERPTR_IDX;
+		}
+
+		ctx->is_requested = 1;
+	}
+
+	ctx->buf_num = b->count;
+
+	return 0;
+}
+
+int fimc_querybuf_output(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_ctx *ctx;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	u32 buf_length = 0;
+
+	fimc_info1("%s: called\n", __func__);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	if (b->index >= ctx->buf_num) {
+		fimc_err("The index is out of bounds. You requested %d buffers."
+			"But requested index is %d\n", ctx->buf_num, b->index);
+		return -EINVAL;
+	}
+
+	b->flags = ctx->src[b->index].flags;
+	b->m.offset = b->index * PAGE_SIZE;
+	buf_length = ctx->src[b->index].length[FIMC_ADDR_Y] +
+		ctx->src[b->index].length[FIMC_ADDR_CB] +
+		ctx->src[b->index].length[FIMC_ADDR_CR];
+	b->length = PAGE_ALIGN(buf_length);
+
+	return 0;
+}
+
+int fimc_g_ctrl_output(void *fh, struct v4l2_control *c)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct s3c_platform_fimc *pdata	= to_fimc_plat(ctrl->dev);
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	switch (c->id) {
+	case V4L2_CID_ROTATION:
+		c->value = ctx->rotate;
+		break;
+
+	case V4L2_CID_HFLIP:
+		if (ctx->flip & V4L2_CID_HFLIP)
+			c->value = 1;
+		else
+			c->value = 0;
+		break;
+
+	case V4L2_CID_VFLIP:
+		if (ctx->flip & V4L2_CID_VFLIP)
+			c->value = 1;
+		else
+			c->value = 0;
+		break;
+
+	case V4L2_CID_OVERLAY_VADDR0:
+		c->value = ctx->overlay.buf.vir_addr[0];
+		break;
+
+	case V4L2_CID_OVERLAY_VADDR1:
+		c->value = ctx->overlay.buf.vir_addr[1];
+		break;
+
+	case V4L2_CID_OVERLAY_VADDR2:
+		c->value = ctx->overlay.buf.vir_addr[2];
+		break;
+
+	case V4L2_CID_OVERLAY_AUTO:
+		if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO)
+			c->value = 1;
+		else
+			c->value = 0;
+		break;
+
+	case V4L2_CID_RESERVED_MEM_BASE_ADDR:
+		c->value = ctrl->mem.base;
+		break;
+
+	case V4L2_CID_RESERVED_MEM_SIZE:
+		/* return KB size */
+		c->value = (ctrl->mem.size) / 1024;
+		break;
+
+	case V4L2_CID_FIMC_VERSION:
+		c->value = pdata->hw_ver;
+		break;
+
+	default:
+		fimc_err("Invalid control id: %d\n", c->id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_set_dst_info(struct fimc_control *ctrl,
+			     struct fimc_ctx *ctx,
+			     struct fimc_buf *fimc_buf)
+{
+	struct fimc_buf *buf;
+	int i;
+
+	for (i = 0; i < ctx->buf_num; i++) {
+		buf = &fimc_buf[i];
+		ctx->dst[i].base[FIMC_ADDR_Y] = buf->base[FIMC_ADDR_Y];
+		ctx->dst[i].length[FIMC_ADDR_Y] = buf->length[FIMC_ADDR_Y];
+
+		ctx->dst[i].base[FIMC_ADDR_CB] = buf->base[FIMC_ADDR_CB];
+		ctx->dst[i].length[FIMC_ADDR_CB] = buf->length[FIMC_ADDR_CB];
+
+		ctx->dst[i].base[FIMC_ADDR_CR] = buf->base[FIMC_ADDR_CR];
+		ctx->dst[i].length[FIMC_ADDR_CR] = buf->length[FIMC_ADDR_CR];
+	}
+
+	for (i = ctx->buf_num; i < FIMC_OUTBUFS; i++) {
+		ctx->dst[i].base[FIMC_ADDR_Y] = 0;
+		ctx->dst[i].length[FIMC_ADDR_Y] = 0;
+
+		ctx->dst[i].base[FIMC_ADDR_CB] = 0;
+		ctx->dst[i].length[FIMC_ADDR_CB] = 0;
+
+		ctx->dst[i].base[FIMC_ADDR_CR] = 0;
+		ctx->dst[i].length[FIMC_ADDR_CR] = 0;
+	}
+
+	/* for debugging */
+	for (i = 0; i < FIMC_OUTBUFS; i++) {
+		fimc_dbg("dst[%d]: base[0]=0x%08x, size[0]=0x%08x\n",
+			i, ctx->dst[i].base[0], ctx->dst[i].length[0]);
+
+		fimc_dbg("dst[%d]: base[1]=0x%08x, size[1]=0x%08x\n",
+			i, ctx->dst[i].base[1], ctx->dst[i].length[2]);
+
+		fimc_dbg("dst[%d]: base[2]=0x%08x, size[2]=0x%08x\n",
+			i, ctx->dst[i].base[1], ctx->dst[i].length[2]);
+	}
+
+	return 0;
+}
+
+void fimc_cache_flush(struct fimc_buf *buf)
+{
+	size_t length = 0;
+	int i = 0;
+
+	for (i = 0; i < 3; i++) {
+		length += buf->length[i];
+	}
+	if (length > (unsigned long) L2_FLUSH_ALL) {
+		outer_flush_all();      /* L2 */
+	} else if (length > (unsigned long) L1_FLUSH_ALL) {
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = buf->base[i];
+			phys_addr_t end   = buf->base[i] +
+					    buf->length[i] - 1;
+
+			if (!start)
+				continue;
+
+			outer_flush_range(start, end);  /* L2 */
+		}
+	} else {
+		for (i = 0; i < 3; i++) {
+			phys_addr_t start = buf->base[i];
+			phys_addr_t end   = buf->base[i] +
+					    buf->length[i] - 1;
+
+			if (!start)
+				continue;
+
+			outer_flush_range(start, end);  /* L2 */
+		}
+	}
+}
+
+int fimc_s_ctrl_output(struct file *filp, void *fh, struct v4l2_control *c)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int ret = 0;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	switch (c->id) {
+	case V4L2_CID_ROTATION:
+		ret = fimc_set_rot_degree(ctrl, ctx, c->value);
+
+		break;
+	case V4L2_CID_HFLIP:
+		if (c->value)
+			ctx->flip |= FIMC_YFLIP;
+		else
+			ctx->flip &= ~FIMC_YFLIP;
+
+		break;
+	case V4L2_CID_VFLIP:
+		if (c->value)
+			ctx->flip |= FIMC_XFLIP;
+		else
+			ctx->flip &= ~FIMC_XFLIP;
+
+		break;
+	case V4L2_CID_OVERLAY_AUTO:
+		if (c->value == 1) {
+			ctx->overlay.mode = FIMC_OVLY_DMA_AUTO;
+		} else {
+			ctx->overlay.mode = FIMC_OVLY_DMA_MANUAL;
+			ret = fimc_outdev_set_dst_buf(ctrl, ctx);
+			fimc_outdev_overlay_buf(filp, ctrl, ctx);
+		}
+
+		break;
+	case V4L2_CID_OVLY_MODE:
+		ctx->overlay.mode = c->value;
+
+		break;
+	case V4L2_CID_DST_INFO:
+		ret = fimc_set_dst_info(ctrl, ctx,
+					(struct fimc_buf *)c->value);
+		break;
+	case V4L2_CID_GET_PHY_SRC_YADDR:
+		c->value = ctx->src[c->value].base[FIMC_ADDR_Y];
+		break;
+	case V4L2_CID_GET_PHY_SRC_CADDR:
+		c->value = ctx->src[c->value].base[FIMC_ADDR_CB];
+		break;
+	default:
+		fimc_err("Invalid control id: %d\n", c->id);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int fimc_cropcap_output(void *fh, struct v4l2_cropcap *a)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	u32 is_rotate = 0, max_w = 0, max_h = 0, pixelformat;
+
+	fimc_info1("%s: called\n", __func__);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	pixelformat = ctx->pix.pixelformat;
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	is_rotate = fimc_mapping_rot_flip(ctx->rotate, ctx->flip);
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+		max_w = FIMC_SRC_MAX_W;
+		max_h = FIMC_SRC_MAX_H;
+		break;
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+		if (is_rotate & FIMC_ROT) {		/* Landscape mode */
+			max_w = ctrl->fb.lcd_vres;
+			max_h = ctrl->fb.lcd_hres;
+		} else {				/* Portrait */
+			max_w = ctrl->fb.lcd_hres;
+			max_h = ctrl->fb.lcd_vres;
+		}
+
+		break;
+	default:
+		fimc_warn("Supported format : V4L2_PIX_FMT_YUYV, "
+			"V4L2_PIX_FMT_NV12, V4L2_PIX_FMT_NV12T, "
+			"V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB565\n");
+		return -EINVAL;
+	}
+
+	/* crop bounds */
+	ctx->cropcap.bounds.left = 0;
+	ctx->cropcap.bounds.top = 0;
+	ctx->cropcap.bounds.width = max_w;
+	ctx->cropcap.bounds.height = max_h;
+
+	/* crop default values */
+	ctx->cropcap.defrect.left = 0;
+	ctx->cropcap.defrect.top = 0;
+	ctx->cropcap.defrect.width = max_w;
+	ctx->cropcap.defrect.height = max_h;
+
+	/* crop pixel aspec values */
+	/* To Do : Have to modify but I don't know the meaning. */
+	ctx->cropcap.pixelaspect.numerator = 16;
+	ctx->cropcap.pixelaspect.denominator = 9;
+
+	a->bounds = ctx->cropcap.bounds;
+	a->defrect = ctx->cropcap.defrect;
+	a->pixelaspect = ctx->cropcap.pixelaspect;
+
+	return 0;
+}
+
+int fimc_g_crop_output(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: called\n", __func__);
+
+	mutex_lock(&ctrl->v4l2_lock);
+	a->c.left   = ctx->crop.left;
+	a->c.top    = ctx->crop.top;
+	a->c.width  = ctx->crop.width;
+	a->c.height = ctx->crop.height;
+	mutex_unlock(&ctrl->v4l2_lock);
+
+	return 0;
+}
+
+int fimc_s_crop_output(void *fh, struct v4l2_crop *a)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+
+	fimc_info1("%s: called: left(%d), top(%d), width(%d), height(%d),\n",
+		__func__, a->c.left, a->c.top, a->c.width, a->c.height);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	/* Check arguments : widht and height */
+	if ((a->c.width < 0) || (a->c.height < 0)) {
+		fimc_err("The crop rect must be bigger than 0\n");
+		fimc_err("width = %d, height = %d\n", a->c.width, a->c.height);
+		return -EINVAL;
+	}
+
+	if ((a->c.width > FIMC_SRC_MAX_W) || (a->c.height > FIMC_SRC_MAX_H)) {
+		fimc_err("The crop width/height must be smaller than "
+			"%d and %d\n", FIMC_SRC_MAX_W, FIMC_SRC_MAX_H);
+		fimc_err("width = %d, height = %d\n", a->c.width, a->c.height);
+		return -EINVAL;
+	}
+
+	/* Check arguments : left and top */
+	if ((a->c.left < 0) || (a->c.top < 0)) {
+		fimc_err("The crop left, top must be  bigger than 0\n");
+		fimc_err("left = %d, top = %d\n", a->c.left, a->c.top);
+		return -EINVAL;
+	}
+
+	if ((a->c.left > FIMC_SRC_MAX_W) || (a->c.top > FIMC_SRC_MAX_H)) {
+		fimc_err("The crop left, top must be smaller than %d, %d\n",
+			FIMC_SRC_MAX_W, FIMC_SRC_MAX_H);
+		fimc_err("left = %d, top = %d\n", a->c.left, a->c.top);
+		return -EINVAL;
+	}
+
+	if ((a->c.left + a->c.width) > FIMC_SRC_MAX_W) {
+		fimc_err("The crop rect must be in bound rect\n");
+		fimc_err("left = %d, width = %d\n", a->c.left, a->c.width);
+		return -EINVAL;
+	}
+
+	if ((a->c.top + a->c.height) > FIMC_SRC_MAX_H) {
+		fimc_err("The crop rect must be in bound rect\n");
+		fimc_err("top = %d, width = %d\n", a->c.top, a->c.height);
+		return -EINVAL;
+	}
+
+	ctx->crop.left = a->c.left;
+	ctx->crop.top = a->c.top;
+	ctx->crop.width = a->c.width;
+	ctx->crop.height = a->c.height;
+
+	return 0;
+}
+
+int fimc_streamon_output(void *fh)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int ret = -1;
+
+	fimc_info1("%s: called\n", __func__);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->overlay.mode == FIMC_OVLY_NOT_FIXED)
+		ctx->overlay.mode = FIMC_OVLY_MODE;
+
+	/* initialize destination buffers */
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+		ret = fimc_outdev_set_dst_buf(ctrl, ctx);
+		if (ret)
+			return ret;
+	}
+
+	ret = fimc_outdev_check_param(ctrl, ctx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_outdev_check_param\n");
+		return ret;
+	}
+
+	ctx->status = FIMC_READY_ON;
+	if (ctrl->status == FIMC_STREAMOFF)
+		ctrl->status = FIMC_READY_ON;
+
+	return ret;
+}
+
+void fimc_outdev_init_idxs(struct fimc_control *ctrl)
+{
+	ctrl->out->idxs.prev.ctx = -1;
+	ctrl->out->idxs.prev.idx = -1;
+	ctrl->out->idxs.active.ctx = -1;
+	ctrl->out->idxs.active.idx = -1;
+	ctrl->out->idxs.next.ctx = -1;
+	ctrl->out->idxs.next.idx = -1;
+}
+
+int fimc_streamoff_output(void *fh)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int ret = -1, i = 0, off_cnt = 0;
+	struct s3cfb_user_window window;
+	fimc_info1("%s: called\n", __func__);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	/* Move it to here to ignore fimc_irq_out_dma operation. */
+	ctx->status = FIMC_STREAMOFF;
+
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO ||
+			ctx->overlay.mode == FIMC_OVLY_DMA_MANUAL) {
+		/* Need some delay to waiting reamined operation */
+		msleep(100);
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_OFF,
+			(unsigned long)NULL);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_OFF) fail\n");
+			return -EINVAL;
+		}
+
+		/* reset WIN position */
+		memset(&window, 0, sizeof(window));
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_WIN_POSITION,
+				(unsigned long)&window);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_WIN_POSITION) fail\n");
+			return -EINVAL;
+		}
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_ADDR, 0x00000000);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_ADDR) fail\n");
+			return -EINVAL;
+		}
+
+		ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_SET_WIN_MEM, DMA_MEM_NONE);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_MEM) fail\n");
+			return -EINVAL;
+		}
+
+		ctrl->fb.is_enable = 0;
+	}
+
+	ret = fimc_init_in_queue(ctrl, ctx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_init_in_queue\n");
+		return -EINVAL;
+	}
+
+	ret = fimc_init_out_queue(ctrl, ctx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_init_out_queue\n");
+		return -EINVAL;
+	}
+
+	/* Make all buffers DQUEUED state. */
+	for (i = 0; i < FIMC_OUTBUFS; i++) {
+		ctx->src[i].state = VIDEOBUF_IDLE;
+		ctx->src[i].flags = V4L2_BUF_FLAG_MAPPED;
+	}
+
+	if (ctrl->out->last_ctx == ctx->ctx_num)
+		ctrl->out->last_ctx = -1;
+
+	if (ctx->overlay.mode == FIMC_OVLY_DMA_AUTO) {
+		ctrl->mem.curr = ctx->dst[0].base[FIMC_ADDR_Y];
+		for (i = 0; i < FIMC_OUTBUFS; i++) {
+			ctx->dst[i].base[FIMC_ADDR_Y] = 0;
+			ctx->dst[i].length[FIMC_ADDR_Y] = 0;
+
+			ctx->dst[i].base[FIMC_ADDR_CB] = 0;
+			ctx->dst[i].length[FIMC_ADDR_CB] = 0;
+
+			ctx->dst[i].base[FIMC_ADDR_CR] = 0;
+			ctx->dst[i].length[FIMC_ADDR_CR] = 0;
+		}
+	}
+
+	/* check all ctx to change ctrl->status from streamon to streamoff */
+	for (i = 0; i < FIMC_MAX_CTXS; i++) {
+		if (ctrl->out->ctx[i].status == FIMC_STREAMOFF)
+			off_cnt++;
+	}
+
+	if (off_cnt == FIMC_MAX_CTXS) {
+		ctrl->status = FIMC_STREAMOFF;
+		fimc_outdev_init_idxs(ctrl);
+	}
+
+#if (!defined(CONFIG_EXYNOS_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	if (off_cnt == FIMC_MAX_CTXS) {
+		ctrl->status = FIMC_STREAMOFF;
+		fimc_outdev_init_idxs(ctrl);
+		fimc_outdev_stop_camif(ctrl);
+	}
+#endif
+
+	return 0;
+}
+
+int fimc_output_set_dst_addr(struct fimc_control *ctrl,
+						struct fimc_ctx *ctx, int idx)
+{
+	struct fimc_buf_set buf_set;    /* destination addr */
+	u32 format = ctx->fbuf.fmt.pixelformat;
+	u32 width = ctx->fbuf.fmt.width;
+	u32 height = ctx->fbuf.fmt.height;
+	u32 y_size = width * height;
+	u32 c_size = y_size >> 2;
+	int i, cfg;
+	u32 rot = ctx->rotate;
+
+	memset(&buf_set, 0x00, sizeof(buf_set));
+
+	if (V4L2_PIX_FMT_NV12T == format)
+		fimc_get_nv12t_size(width, height, &y_size, &c_size);
+
+	switch (format) {
+	case V4L2_PIX_FMT_RGB32:
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_YUYV:         /* fall through */
+	case V4L2_PIX_FMT_UYVY:         /* fall through */
+	case V4L2_PIX_FMT_YVYU:         /* fall through */
+	case V4L2_PIX_FMT_VYUY:         /* fall through */
+		if (ctx->overlay.mode == FIMC_OVLY_NONE_SINGLE_BUF)
+			buf_set.base[FIMC_ADDR_Y] =
+				(dma_addr_t)ctx->fbuf.base;
+		else
+			buf_set.base[FIMC_ADDR_Y] =
+				ctx->dst[idx].base[FIMC_ADDR_Y];
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		if (ctx->overlay.mode == FIMC_OVLY_NONE_SINGLE_BUF) {
+			buf_set.base[FIMC_ADDR_Y] =
+				(dma_addr_t)ctx->fbuf.base;
+			buf_set.base[FIMC_ADDR_CB] =
+				buf_set.base[FIMC_ADDR_Y] + y_size;
+			buf_set.base[FIMC_ADDR_CR] =
+				buf_set.base[FIMC_ADDR_CB] + c_size;
+		} else {
+			buf_set.base[FIMC_ADDR_Y] =
+				ctx->dst[idx].base[FIMC_ADDR_Y];
+			buf_set.base[FIMC_ADDR_CB] =
+				ctx->dst[idx].base[FIMC_ADDR_CB];
+			buf_set.base[FIMC_ADDR_CR] =
+				ctx->dst[idx].base[FIMC_ADDR_CR];
+		}
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV21:
+	case V4L2_PIX_FMT_NV16:
+	case V4L2_PIX_FMT_NV61:
+		if (ctx->overlay.mode == FIMC_OVLY_NONE_SINGLE_BUF) {
+			buf_set.base[FIMC_ADDR_Y] =
+				(dma_addr_t)ctx->fbuf.base;
+			buf_set.base[FIMC_ADDR_CB] =
+				buf_set.base[FIMC_ADDR_Y] + y_size;
+		} else {
+			buf_set.base[FIMC_ADDR_Y] =
+				ctx->dst[idx].base[FIMC_ADDR_Y];
+			buf_set.base[FIMC_ADDR_CB] =
+				ctx->dst[idx].base[FIMC_ADDR_CB];
+		}
+		break;
+	case V4L2_PIX_FMT_NV12T:
+		if (ctx->overlay.mode == FIMC_OVLY_NONE_SINGLE_BUF) {
+			if (rot == 0 || rot == 180)
+				fimc_get_nv12t_size(width, height, &y_size, &c_size);
+			else
+				fimc_get_nv12t_size(height, width, &y_size, &c_size);
+			buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+			buf_set.base[FIMC_ADDR_CB] = buf_set.base[FIMC_ADDR_Y] + y_size;
+		} else {
+			buf_set.base[FIMC_ADDR_Y] =
+				ctx->dst[idx].base[FIMC_ADDR_Y];
+			buf_set.base[FIMC_ADDR_CB] =
+				ctx->dst[idx].base[FIMC_ADDR_CB];
+		}
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n", \
+				__func__, format);
+		return -EINVAL;
+	}
+
+	cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		if (check_bit(cfg, i))
+			fimc_hwset_output_address(ctrl, &buf_set, i);
+	}
+
+	return 0;
+}
+
+static int fimc_outdev_start_operation(struct fimc_control *ctrl,
+				       struct fimc_ctx *ctx, int idx)
+{
+	int ret = 0;
+	unsigned long spin_flags;
+
+	spin_lock_irqsave(&ctrl->out->slock, spin_flags);
+	ret = fimc_outdev_start_camif(ctrl);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_start_camif\n");
+		return -EINVAL;
+	}
+
+	ctrl->out->idxs.active.idx = idx;
+	ctrl->out->idxs.active.ctx = ctx->ctx_num;
+
+	ctrl->status = FIMC_STREAMON;
+	ctx->status = FIMC_STREAMON;
+	spin_unlock_irqrestore(&ctrl->out->slock, spin_flags);
+
+	return ret;
+}
+
+static int fimc_qbuf_output_single_buf(struct fimc_control *ctrl,
+				       struct fimc_ctx *ctx,
+				       int idx)
+{
+	struct fimc_buf_set buf_set;	/* destination addr */
+	u32 format = ctx->fbuf.fmt.pixelformat;
+	u32 width = ctx->fbuf.fmt.width;
+	u32 height = ctx->fbuf.fmt.height;
+	u32 y_size = width * height;
+	u32 c_size = y_size >> 2;
+	int ret = -1, i, cfg;
+	u32 rot = ctx->rotate;
+
+	fimc_outdev_set_src_addr(ctrl, ctx->src[idx].base);
+
+	memset(&buf_set, 0x00, sizeof(buf_set));
+
+	switch (format) {
+	case V4L2_PIX_FMT_RGB32:
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_YUYV:
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		buf_set.base[FIMC_ADDR_CB] = buf_set.base[FIMC_ADDR_Y] + y_size;
+		buf_set.base[FIMC_ADDR_CR] = buf_set.base[FIMC_ADDR_CB] + c_size;
+		break;
+	case V4L2_PIX_FMT_YVU420:
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		buf_set.base[FIMC_ADDR_CR] = buf_set.base[FIMC_ADDR_Y] + y_size;
+		buf_set.base[FIMC_ADDR_CB] = buf_set.base[FIMC_ADDR_CR] + c_size;
+		break;
+	case V4L2_PIX_FMT_NV12:
+	case V4L2_PIX_FMT_NV21:
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		buf_set.base[FIMC_ADDR_CB] = buf_set.base[FIMC_ADDR_Y] + y_size;
+		break;
+	case V4L2_PIX_FMT_NV12M:
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		buf_set.base[FIMC_ADDR_CB] =
+			ALIGN(buf_set.base[FIMC_ADDR_Y] + y_size, PAGE_SIZE - 1);
+		break;
+	case V4L2_PIX_FMT_NV12T:
+		if (rot == 0 || rot == 180)
+			fimc_get_nv12t_size(width, height, &y_size, &c_size);
+		else
+			fimc_get_nv12t_size(height, width, &y_size, &c_size);
+		buf_set.base[FIMC_ADDR_Y] = (dma_addr_t)ctx->fbuf.base;
+		buf_set.base[FIMC_ADDR_CB] = buf_set.base[FIMC_ADDR_Y] + y_size;
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n", __func__, format);
+		return -EINVAL;
+	}
+	cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		if (check_bit(cfg, i))
+			fimc_hwset_output_address(ctrl, &buf_set, i);
+	}
+
+	ret = fimc_outdev_start_operation(ctrl, ctx, idx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_start_operation\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_qbuf_output_multi_buf(struct fimc_control *ctrl,
+				      struct fimc_ctx *ctx,
+				      int idx)
+{
+	struct fimc_buf_set buf_set;	/* destination addr */
+	u32 format = ctx->fbuf.fmt.pixelformat;
+	int ret = -1, i, cfg;
+
+	fimc_outdev_set_src_addr(ctrl, ctx->src[idx].base);
+
+	memset(&buf_set, 0x00, sizeof(buf_set));
+
+	switch (format) {
+	case V4L2_PIX_FMT_RGB32:
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_YUYV:
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[idx].base[FIMC_ADDR_Y];
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[idx].base[FIMC_ADDR_Y];
+		buf_set.base[FIMC_ADDR_CB] = ctx->dst[idx].base[FIMC_ADDR_CB];
+		buf_set.base[FIMC_ADDR_CR] = ctx->dst[idx].base[FIMC_ADDR_CR];
+		break;
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[idx].base[FIMC_ADDR_Y];
+		buf_set.base[FIMC_ADDR_CB] = ctx->dst[idx].base[FIMC_ADDR_CB];
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n", __func__, format);
+		return -EINVAL;
+	}
+
+	cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		if (check_bit(cfg, i))
+			fimc_hwset_output_address(ctrl, &buf_set, i);
+	}
+
+	ret = fimc_outdev_start_operation(ctrl, ctx, idx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_start_operation\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_qbuf_output_dma_auto(struct fimc_control *ctrl,
+				      struct fimc_ctx *ctx,
+				      int idx)
+{
+	struct fb_var_screeninfo var;
+	struct s3cfb_user_window window;
+	struct v4l2_rect fimd_rect, fimd_rect_virtual;
+	struct fimc_buf_set buf_set;	/* destination addr */
+	u32 id = ctrl->id;
+	int ret = -1, i, cfg;
+
+	switch (ctx->status) {
+	case FIMC_READY_ON:
+		memset(&fimd_rect, 0, sizeof(struct v4l2_rect));
+		ret = fimc_fimd_rect(ctrl, ctx, &fimd_rect);
+		if (ret < 0) {
+			fimc_err("fimc_fimd_rect fail\n");
+			return -EINVAL;
+		}
+
+		/* Support any size */
+		memcpy(&fimd_rect_virtual, &fimd_rect, sizeof(fimd_rect));
+		fimc_outdev_dma_auto_dst_resize(&fimd_rect_virtual);
+
+		/* Get WIN var_screeninfo */
+		ret = s3cfb_direct_ioctl(id, FBIOGET_VSCREENINFO,
+						(unsigned long)&var);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(FBIOGET_VSCREENINFO) fail\n");
+			return -EINVAL;
+		}
+		/* window path : DMA */
+		ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_PATH,
+							DATA_PATH_DMA);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_PATH) fail\n");
+			return -EINVAL;
+		}
+
+		/* Don't allocate the memory. */
+		ret = s3cfb_direct_ioctl(id, S3CFB_SET_WIN_MEM, DMA_MEM_OTHER);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_SET_WIN_MEM) fail\n");
+			return -EINVAL;
+		}
+
+		/* Update WIN size */
+		var.xres_virtual = fimd_rect_virtual.width;
+		var.yres_virtual = fimd_rect_virtual.height;
+		var.xres = fimd_rect.width;
+		var.yres = fimd_rect.height;
+
+		ret = s3cfb_direct_ioctl(id, FBIOPUT_VSCREENINFO,
+							(unsigned long)&var);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(FBIOPUT_VSCREENINFO) fail\n");
+			return -EINVAL;
+		}
+
+		/* Update WIN position */
+		window.x = fimd_rect.left;
+		window.y = fimd_rect.top;
+		ret = s3cfb_direct_ioctl(id, S3CFB_WIN_POSITION,
+				(unsigned long)&window);
+		if (ret < 0) {
+			fimc_err("direct_ioctl(S3CFB_WIN_POSITION) fail\n");
+			return -EINVAL;
+		}
+
+		/* fall through */
+
+	case FIMC_STREAMON_IDLE:
+		fimc_outdev_set_src_addr(ctrl, ctx->src[idx].base);
+
+		memset(&buf_set, 0x00, sizeof(buf_set));
+		buf_set.base[FIMC_ADDR_Y] = ctx->dst[idx].base[FIMC_ADDR_Y];
+		cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+		for (i = 0; i < FIMC_PHYBUFS; i++) {
+			if (check_bit(cfg, i))
+				fimc_hwset_output_address(ctrl, &buf_set, i);
+		}
+
+		ret = fimc_outdev_start_operation(ctrl, ctx, idx);
+		if (ret < 0) {
+			fimc_err("Fail: fimc_start_operation\n");
+			return -EINVAL;
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int fimc_qbuf_output_dma_manual(struct fimc_control *ctrl,
+				      struct fimc_ctx *ctx,
+				      int idx)
+{
+	struct fimc_buf_set buf_set;	/* destination addr */
+	int ret = -1, i, cfg;
+
+	fimc_outdev_set_src_addr(ctrl, ctx->src[idx].base);
+
+	memset(&buf_set, 0x00, sizeof(buf_set));
+	buf_set.base[FIMC_ADDR_Y] = ctx->dst[idx].base[FIMC_ADDR_Y];
+	cfg = fimc_hwget_output_buf_sequence(ctrl);
+
+	for (i = 0; i < FIMC_PHYBUFS; i++) {
+		if (check_bit(cfg, i))
+			fimc_hwset_output_address(ctrl, &buf_set, i);
+	}
+
+	ctrl->out->idxs.active.idx = idx;
+	ctrl->out->idxs.active.ctx = ctx->ctx_num;
+
+	ctrl->status = FIMC_STREAMON;
+	ctx->status = FIMC_STREAMON;
+
+	ret = fimc_outdev_start_camif(ctrl);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_start_camif\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_qbuf_output_fifo(struct fimc_control *ctrl,
+				      struct fimc_ctx *ctx,
+				      int idx)
+{
+	int ret = -1;
+
+#if defined(CONFIG_VIDEO_IPC)
+	if (ctx->pix.field == V4L2_FIELD_INTERLACED_TB)
+		ipc_start();
+#endif
+
+	fimc_outdev_set_src_addr(ctrl, ctx->src[idx].base);
+
+	ctrl->out->idxs.active.idx = idx;
+	ctrl->out->idxs.active.ctx = ctx->ctx_num;
+
+	ctrl->status = FIMC_STREAMON;
+	ctx->status = FIMC_STREAMON;
+
+	ret = fimc_start_fifo(ctrl, ctx);
+	if (ret < 0) {
+		fimc_err("Fail: fimc_start_fifo\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_update_in_queue_addr(struct fimc_control *ctrl,
+				     struct fimc_ctx *ctx,
+				     u32 idx, dma_addr_t *addr)
+{
+	if (idx >= FIMC_OUTBUFS) {
+		fimc_err("%s: Failed (ctx=%d)\n", __func__, ctx->ctx_num);
+		return -EINVAL;
+	}
+
+	ctx->src[idx].base[FIMC_ADDR_Y] = addr[FIMC_ADDR_Y];
+	if (ctx->pix.pixelformat == V4L2_PIX_FMT_YVU420) {
+		ctx->src[idx].base[FIMC_ADDR_CB] = addr[FIMC_ADDR_CR];
+		ctx->src[idx].base[FIMC_ADDR_CR] = addr[FIMC_ADDR_CB];
+	} else {
+		ctx->src[idx].base[FIMC_ADDR_CB] = addr[FIMC_ADDR_CB];
+		ctx->src[idx].base[FIMC_ADDR_CR] = addr[FIMC_ADDR_CR];
+	}
+
+	return 0;
+}
+
+int fimc_qbuf_output(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_buf *buf = (struct fimc_buf *)b->m.userptr;
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int idx, ctx_num;
+	int ret = -1;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	fimc_info2("ctx(%d) queued idx = %d\n", ctx->ctx_num, b->index);
+	if (ctx->status == FIMC_STREAMOFF) {
+		fimc_err("[ctx=%d] %s:: can not queue bause status "
+				"is FIMC_STREAMOFF status)\n",
+				ctx->ctx_num, __func__);
+		return ret;
+	}
+
+	if (b->index >= ctx->buf_num) {
+		fimc_err("[ctx=%d] The index is out of bounds. "
+			"You requested %d buffers. "
+			"But you set the index as %d\n",
+			ctx_id, ctx->buf_num, b->index);
+		return -EINVAL;
+	}
+
+	/* Check the buffer state if the state is VIDEOBUF_IDLE. */
+	if (ctx->src[b->index].state != VIDEOBUF_IDLE) {
+		fimc_err("[ctx=%d] The index(%d) buffer must be "
+				"dequeued state(%d)\n",
+				 ctx_id, b->index, ctx->src[b->index].state);
+		return -EINVAL;
+	}
+
+	if ((ctrl->status == FIMC_READY_ON) ||
+	    (ctrl->status == FIMC_STREAMON) ||
+	    (ctrl->status == FIMC_STREAMON_IDLE)) {
+		if (b->memory == V4L2_MEMORY_USERPTR) {
+			ret = fimc_update_in_queue_addr(ctrl, ctx, b->index, buf->base);
+			if (ret < 0)
+				return ret;
+		}
+
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+		pm_runtime_get_sync(ctrl->dev);
+#endif
+
+		/* Attach the buffer to the incoming queue. */
+		ret = fimc_push_inq(ctrl, ctx, b->index);
+		if (ret < 0) {
+			fimc_err("Fail: fimc_push_inq (ctx=%d ctrl>status=%d "
+					"ctx->status=%d q_idx=%d)\n", ctx_id,
+					ctrl->status, ctx->status, b->index);
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+			pm_runtime_put_sync(ctrl->dev);
+#endif
+			return -EINVAL;
+		}
+	} else
+		fimc_err("[ctx=%d] qbuf[%d]: not call fimc_push_inq: "
+				"ctrl->status=%d ctx->status=%d q_idx=%d\n",
+				ctx_id, __LINE__, ctrl->status, ctx->status,
+				b->index);
+
+	if ((ctrl->status == FIMC_READY_ON) ||
+	    (ctrl->status == FIMC_STREAMON_IDLE)) {
+		ret = fimc_pop_inq(ctrl, &ctx_num, &idx);
+		if (ret < 0) {
+			fimc_err("Fail: fimc_pop_inq (ctx=%d ctrl>status=%d "
+				 "ctx->status=%d ret=%d)\n",
+				 ctx_id, ctrl->status, ctx->status, ret);
+			ret = -EINVAL;
+			goto err_routine;
+		}
+
+		if (ctrl->regs == NULL) {
+			fimc_err("%s:FIMC%d power is off!!! (ctx=%d)\n",
+				 __func__, ctrl->id, ctx_id);
+			return -EINVAL;
+		}
+
+		ctx = &ctrl->out->ctx[ctx_num];
+		if (ctx_num != ctrl->out->last_ctx) {
+			ctrl->out->last_ctx = ctx->ctx_num;
+			ret = fimc_outdev_set_ctx_param(ctrl, ctx);
+			if (ret < 0) {
+				ctx->src[b->index].state = VIDEOBUF_IDLE;
+				ctrl->out->last_ctx = -1;
+				fimc_err("Fail: fimc_outdev_set_ctx_param (ctx=%d)\n",
+					 ctx_id);
+				ret = -EINVAL;
+				goto err_routine;
+			}
+		}
+
+		switch (ctx->overlay.mode) {
+		case FIMC_OVLY_FIFO:
+			ret = fimc_qbuf_output_fifo(ctrl, ctx, idx);
+			break;
+		case FIMC_OVLY_DMA_AUTO:
+			ret = fimc_qbuf_output_dma_auto(ctrl, ctx, idx);
+			break;
+		case FIMC_OVLY_DMA_MANUAL:
+			ret = fimc_qbuf_output_dma_manual(ctrl, ctx, idx);
+			break;
+		case FIMC_OVLY_NONE_SINGLE_BUF:
+			ret = fimc_qbuf_output_single_buf(ctrl, ctx, idx);
+			break;
+		case FIMC_OVLY_NONE_MULTI_BUF:
+			ret = fimc_qbuf_output_multi_buf(ctrl, ctx, idx);
+			break;
+		default:
+			break;
+		}
+	}
+
+err_routine:
+#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME)
+	if (ret < 0)
+		pm_runtime_put_sync(ctrl->dev);
+#endif
+	return ret;
+}
+
+void fimc_recover_output(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	pm_runtime_get_sync(ctrl->dev);
+/*	fimc_sfr_dump(ctrl);*/
+	fimc_outdev_stop_camif(ctrl);
+	fimc_hwset_clear_irq(ctrl);
+	pm_runtime_put_sync(ctrl->dev);
+#endif
+
+	if (ctrl->out->idxs.active.ctx == ctx->ctx_num) {
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+	}
+
+	ctrl->status = FIMC_STREAMON_IDLE;
+	ctx->status = FIMC_STREAMON_IDLE;
+
+	return;
+}
+
+int fimc_dqbuf_output(void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int idx = -1, ret = -1;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	ret = fimc_pop_outq(ctrl, ctx, &idx);
+	if (ret < 0) {
+		ret = wait_event_timeout(ctrl->wq, (ctx->outq[0] != -1),
+							FIMC_DQUEUE_TIMEOUT);
+		if (ret == 0) {
+			fimc_dump_context(ctrl, ctx);
+			fimc_recover_output(ctrl, ctx);
+			pm_runtime_put_sync(ctrl->dev);
+			fimc_err("[0] out_queue is empty\n");
+			return -EAGAIN;
+		} else if (ret == -ERESTARTSYS) {
+			fimc_print_signal(ctrl);
+			pm_runtime_put_sync(ctrl->dev);
+		} else {
+			/* Normal case */
+			ret = fimc_pop_outq(ctrl, ctx, &idx);
+			if (ret < 0) {
+				fimc_err("[1] out_queue is empty\n");
+				fimc_dump_context(ctrl, ctx);
+				return -EINVAL;
+			}
+		}
+	}
+
+	b->index = idx;
+
+	fimc_info2("ctx(%d) dqueued idx = %d\n", ctx->ctx_num, b->index);
+
+	return ret;
+}
+
+int fimc_g_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	struct fimc_outinfo *out = ctrl->out;
+	struct fimc_ctx *ctx;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	int i, j;
+	int in_use;
+
+	fimc_info1("%s: called\n", __func__);
+
+	if (!out) {
+		out = kzalloc(sizeof(*out), GFP_KERNEL);
+		if (!out) {
+			fimc_err("%s: no memory for outdev info\n", __func__);
+			return -ENOMEM;
+		}
+		ctrl->out = out;
+
+		/* init: struct fimc_outinfo */
+		out->last_ctx = -1;
+
+		spin_lock_init(&ctrl->out->lock_in);
+		spin_lock_init(&ctrl->out->lock_out);
+		spin_lock_init(&ctrl->out->slock);
+
+		for (i = 0; i < FIMC_INQUEUES; i++) {
+			ctrl->out->inq[i].ctx = -1;
+			ctrl->out->inq[i].idx = -1;
+		}
+
+		for (i = 0; i < FIMC_MAX_CTXS; i++) {
+			ctx = &ctrl->out->ctx[i];
+			ctx->ctx_num = i;
+			ctx->overlay.mode = FIMC_OVLY_NOT_FIXED;
+			ctx->status = FIMC_STREAMOFF;
+
+			for (j = 0; j < FIMC_OUTBUFS; j++) {
+				ctx->inq[j] = -1;
+				ctx->outq[j] = -1;
+			}
+		}
+
+		ctrl->out->idxs.prev.ctx = -1;
+		ctrl->out->idxs.prev.idx = -1;
+		ctrl->out->idxs.active.ctx = -1;
+		ctrl->out->idxs.active.idx = -1;
+		ctrl->out->idxs.next.ctx = -1;
+		ctrl->out->idxs.next.idx = -1;
+
+		in_use = atomic_read(&ctrl->in_use);
+		for (i = 0; i < in_use; i++)
+			ctrl->out->ctx_used[i] = true;
+		for (i = in_use; i < FIMC_MAX_CTXS; i++)
+			ctrl->out->ctx_used[i] = false;
+	}
+
+	f->fmt.pix = ctrl->out->ctx[ctx_id].pix;
+
+	return 0;
+}
+
+int fimc_try_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+	u32 format = f->fmt.pix.pixelformat;
+
+	fimc_info1("%s: called. width(%d), height(%d)\n", __func__,
+				f->fmt.pix.width, f->fmt.pix.height);
+
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	/* Check pixel format */
+	switch (format) {
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_RGB32:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+		break;
+	default:
+		fimc_warn("Supported format : V4L2_PIX_FMT_YUYV, "
+			"V4L2_PIX_FMT_NV12, V4L2_PIX_FMT_NV12T, "
+			"V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB565\n");
+		fimc_warn("Changed format : V4L2_PIX_FMT_RGB32\n");
+		f->fmt.pix.pixelformat = V4L2_PIX_FMT_RGB32;
+		return -EINVAL;
+	}
+
+	/* Fill the return value. */
+	switch (format) {
+	case V4L2_PIX_FMT_RGB32:
+		f->fmt.pix.bytesperline = f->fmt.pix.width << 2;
+		break;
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:
+		f->fmt.pix.bytesperline = f->fmt.pix.width << 1;
+		break;
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		f->fmt.pix.bytesperline = (f->fmt.pix.width * 3) >> 1;
+		break;
+
+	default:
+		/* dummy value*/
+		f->fmt.pix.bytesperline = f->fmt.pix.width;
+	}
+
+	f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * f->fmt.pix.height;
+	ctx->crop.left = 0;
+	ctx->crop.top = 0;
+	ctx->crop.width = f->fmt.pix.width;
+	ctx->crop.height = f->fmt.pix.height;
+
+	return 0;
+}
+
+int fimc_s_fmt_vid_out(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+	int ret = -1;
+
+	fimc_info1("%s: called\n", __func__);
+
+	/* Check stream status */
+	ctx = &ctrl->out->ctx[ctx_id];
+	if (ctx->status != FIMC_STREAMOFF) {
+		fimc_dump_context(ctrl, ctx);
+		fimc_err("%s: FIMC is running\n", __func__);
+		return -EBUSY;
+	}
+
+	ret = fimc_try_fmt_vid_out(filp, fh, f);
+	if (ret < 0)
+		return ret;
+
+	ctx->pix = f->fmt.pix;
+
+	return ret;
+}
+
+int fimc_init_in_queue(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	struct fimc_idx swap_queue[FIMC_INQUEUES];
+	int swap_cnt = 0, i;
+	unsigned long spin_flags;
+
+	spin_lock_irqsave(&ctrl->out->lock_in, spin_flags);
+
+	/* init incoming queue */
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		ctx->inq[i] = -1;
+
+	/* init common incoming queue */
+	for (i = 0; i < FIMC_INQUEUES; i++) {
+		if (ctrl->out->inq[i].ctx != ctx->ctx_num) {
+			swap_queue[swap_cnt].ctx = ctrl->out->inq[i].ctx;
+			swap_queue[swap_cnt].idx = ctrl->out->inq[i].idx;
+			swap_cnt++;
+		}
+
+		ctrl->out->inq[i].ctx = -1;
+		ctrl->out->inq[i].idx = -1;
+	}
+
+	/* restore common incoming queue */
+	for (i = 0; i < swap_cnt; i++) {
+		ctrl->out->inq[i].ctx = swap_queue[i].ctx;
+		ctrl->out->inq[i].idx = swap_queue[i].idx;
+	}
+
+	spin_unlock_irqrestore(&ctrl->out->lock_in, spin_flags);
+
+	return 0;
+}
+
+int fimc_init_out_queue(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	unsigned long spin_flags;
+	int i;
+
+	spin_lock_irqsave(&ctrl->out->lock_out, spin_flags);
+
+	/* Init incoming queue */
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		ctx->outq[i] = -1;
+
+	spin_unlock_irqrestore(&ctrl->out->lock_out, spin_flags);
+
+	return 0;
+}
+
+int fimc_push_inq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int idx)
+{
+	struct fimc_idx swap_common_inq[FIMC_INQUEUES];
+	int swap_queue[FIMC_OUTBUFS];
+	int i;
+	unsigned long spin_flags;
+
+	fimc_dbg("%s: idx = %d\n", __func__, idx);
+
+	if (ctrl->out->inq[FIMC_INQUEUES-1].idx != -1) {
+		fimc_err("FULL: common incoming queue(%d)\n",
+				ctrl->out->inq[FIMC_INQUEUES-1].idx);
+		return -EBUSY;
+	}
+
+	spin_lock_irqsave(&ctrl->out->lock_in, spin_flags);
+
+	/* ctx own incoming queue */
+	/* Backup original queue */
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		swap_queue[i] = ctx->inq[i];
+
+	/* Attach new idx */
+	ctx->inq[0] = idx;
+	ctx->src[idx].state = VIDEOBUF_QUEUED;
+	ctx->src[idx].flags = V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_QUEUED;
+
+	/* Shift the origonal queue */
+	for (i = 1; i < FIMC_OUTBUFS; i++)
+		ctx->inq[i] = swap_queue[i-1];
+
+	/* Common incoming queue */
+	/* Backup original queue */
+	for (i = 0; i < FIMC_INQUEUES; i++) {
+		swap_common_inq[i].ctx = ctrl->out->inq[i].ctx;
+		swap_common_inq[i].idx = ctrl->out->inq[i].idx;
+	}
+
+	/* Attach new idx */
+	ctrl->out->inq[0].ctx = ctx->ctx_num;
+	ctrl->out->inq[0].idx = idx;
+
+	/* Shift the origonal queue */
+	for (i = 1; i < FIMC_INQUEUES; i++) {
+		ctrl->out->inq[i].ctx = swap_common_inq[i-1].ctx;
+		ctrl->out->inq[i].idx = swap_common_inq[i-1].idx;
+	}
+
+	spin_unlock_irqrestore(&ctrl->out->lock_in, spin_flags);
+
+	return 0;
+}
+
+int fimc_pop_inq(struct fimc_control *ctrl, int *ctx_num, int *idx)
+{
+	struct fimc_ctx *ctx;
+	unsigned long spin_flags;
+	int i, ret = 0;
+	int ctx_idx = -1;
+
+	spin_lock_irqsave(&ctrl->out->lock_in, spin_flags);
+
+	/* find valid index from common incoming queue */
+	for (i = (FIMC_INQUEUES-1); i >= 0; i--) {
+		if (ctrl->out->inq[i].ctx != -1) {
+			*ctx_num = ctrl->out->inq[i].ctx;
+			*idx = ctrl->out->inq[i].idx;
+			ctrl->out->inq[i].ctx = -1;
+			ctrl->out->inq[i].idx = -1;
+			break;
+		}
+	}
+
+	/* common incoming queue is empty. */
+	if (i < 0) {
+		spin_unlock_irqrestore(&ctrl->out->lock_in, spin_flags);
+		return -EINVAL;
+	}
+
+	/* find valid index from incoming queue. */
+	ctx = &ctrl->out->ctx[*ctx_num];
+	for (i = (FIMC_OUTBUFS-1); i >= 0; i--) {
+		if (ctx->inq[i] != -1) {
+			ctx_idx = ctx->inq[i];
+			ctx->inq[i] = -1;
+			ctx->src[ctx_idx].state = VIDEOBUF_ACTIVE;
+			ctx->src[ctx_idx].flags = V4L2_BUF_FLAG_MAPPED;
+			break;
+		}
+	}
+
+	if (*idx != ctx_idx)
+		fimc_err("common inq(%d) vs inq(%d) mismatch\n", *idx, ctx_idx);
+
+	/* incoming queue is empty. */
+	if (i < 0)
+		ret = -EINVAL;
+	else
+		fimc_dbg("%s: index = %d\n", __func__, *idx);
+
+	spin_unlock_irqrestore(&ctrl->out->lock_in, spin_flags);
+
+	return ret;
+}
+
+int fimc_push_outq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int idx)
+{
+	unsigned long spin_flags;
+	int swap_queue[FIMC_OUTBUFS];
+	int i;
+
+	fimc_dbg("%s: index = %d\n", __func__, idx);
+
+	spin_lock_irqsave(&ctrl->out->lock_out, spin_flags);
+
+	/* Backup original queue */
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		swap_queue[i] = ctx->outq[i];
+
+	/* Attach new index */
+	ctx->outq[0] = idx;
+	ctx->src[idx].state = VIDEOBUF_DONE;
+	ctx->src[idx].flags = V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_DONE;
+
+	/* Shift the origonal queue */
+	for (i = 1; i < FIMC_OUTBUFS; i++)
+		ctx->outq[i] = swap_queue[i-1];
+
+	spin_unlock_irqrestore(&ctrl->out->lock_out, spin_flags);
+
+	return 0;
+}
+
+int fimc_pop_outq(struct fimc_control *ctrl, struct fimc_ctx *ctx, int *idx)
+{
+	unsigned long spin_flags;
+	int i, ret = 0;
+
+	spin_lock_irqsave(&ctrl->out->lock_out, spin_flags);
+
+	/* Find last valid idx in outgoing queue. */
+	for (i = (FIMC_OUTBUFS-1); i >= 0; i--) {
+		if (ctx->outq[i] != -1) {
+			*idx = ctx->outq[i];
+			ctx->outq[i] = -1;
+			ctx->src[*idx].state = VIDEOBUF_IDLE;
+			ctx->src[*idx].flags = V4L2_BUF_FLAG_MAPPED;
+			break;
+		}
+	}
+
+	/* outgoing queue is empty. */
+	if (i < 0) {
+		ret = -EINVAL;
+		fimc_dbg("%s: outgoing queue : %d, %d, %d\n", __func__,
+				ctx->outq[0], ctx->outq[1], ctx->outq[2]);
+	} else
+		fimc_dbg("%s: idx = %d\n", __func__, *idx);
+
+
+	spin_unlock_irqrestore(&ctrl->out->lock_out, spin_flags);
+
+	return ret;
+}
+
+void fimc_dump_context(struct fimc_control *ctrl, struct fimc_ctx *ctx)
+{
+	int i = 0;
+
+	fimc_err("ctx%d, ctrl->status: %d, ctx->status: %d\n",
+		ctx->ctx_num, ctrl->status, ctx->status);
+
+	for (i = 0; i < FIMC_INQUEUES; i++)
+		fimc_err("ctrl->inq[%d]: ctx(%d) idx(%d)\n",
+			i, ctrl->out->inq[i].ctx, ctrl->out->inq[i].idx);
+
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		fimc_err("inq[%d] = %d\n", i, ctx->inq[i]);
+
+	for (i = 0; i < FIMC_OUTBUFS; i++)
+		fimc_err("outq[%d] = %d\n", i, ctx->outq[i]);
+
+	fimc_err("state : prev.ctx(%d), prev.idx(%d) "
+			"active.ctx(%d), active.idx(%d) "
+			"next.ctx(%d), next.idx(%d)\n",
+		ctrl->out->idxs.prev.ctx, ctrl->out->idxs.prev.idx,
+		ctrl->out->idxs.active.ctx, ctrl->out->idxs.active.idx,
+		ctrl->out->idxs.next.ctx, ctrl->out->idxs.next.idx);
+}
+
+void fimc_print_signal(struct fimc_control *ctrl)
+{
+	if (signal_pending(current)) {
+		fimc_dbg(".pend=%.8lx shpend=%.8lx\n",
+			current->pending.signal.sig[0],
+			current->signal->shared_pending.signal.sig[0]);
+	} else {
+		fimc_dbg(":pend=%.8lx shpend=%.8lx\n",
+			current->pending.signal.sig[0],
+			current->signal->shared_pending.signal.sig[0]);
+	}
+}
diff --git a/drivers/media/video/samsung/fimc/fimc_overlay.c b/drivers/media/video/samsung/fimc/fimc_overlay.c
new file mode 100644
index 0000000..743decc
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_overlay.c
@@ -0,0 +1,287 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_overlay.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * V4L2 Overlay device support file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <plat/media.h>
+
+#include "fimc.h"
+
+int fimc_try_fmt_overlay(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+
+	u32 is_rotate = 0;
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: top(%d) left(%d) width(%d) height(%d)\n", __func__,
+			f->fmt.win.w.top, f->fmt.win.w.left,
+			f->fmt.win.w.width, f->fmt.win.w.height);
+
+	if (ctx->overlay.mode == FIMC_OVLY_NONE_SINGLE_BUF ||
+		(ctx->overlay.mode == FIMC_OVLY_NONE_MULTI_BUF))
+		return 0;
+
+	/* Check Overlay Size : Overlay size must be smaller than LCD size. */
+	is_rotate = fimc_mapping_rot_flip(ctx->rotate, ctx->flip);
+	if (is_rotate & FIMC_ROT) {	/* Landscape mode */
+		if (f->fmt.win.w.width > ctrl->fb.lcd_vres) {
+			fimc_warn("The width is changed %d -> %d\n",
+				f->fmt.win.w.width, ctrl->fb.lcd_vres);
+				f->fmt.win.w.width = ctrl->fb.lcd_vres;
+		}
+
+		if (f->fmt.win.w.height > ctrl->fb.lcd_hres) {
+			fimc_warn("The height is changed %d -> %d\n",
+				f->fmt.win.w.height, ctrl->fb.lcd_hres);
+				f->fmt.win.w.height = ctrl->fb.lcd_hres;
+		}
+	} else {			/* Portrait mode */
+		if (f->fmt.win.w.width > ctrl->fb.lcd_hres) {
+			fimc_warn("The width is changed %d -> %d\n",
+				f->fmt.win.w.width, ctrl->fb.lcd_hres);
+				f->fmt.win.w.width = ctrl->fb.lcd_hres;
+		}
+
+		if (f->fmt.win.w.height > ctrl->fb.lcd_vres) {
+			fimc_warn("The height is changed %d -> %d\n",
+				f->fmt.win.w.height, ctrl->fb.lcd_vres);
+				f->fmt.win.w.height = ctrl->fb.lcd_vres;
+		}
+	}
+
+	return 0;
+}
+
+int fimc_g_fmt_vid_overlay(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: called\n", __func__);
+
+	f->fmt.win = ctx->win;
+
+	return 0;
+}
+
+static int fimc_check_pos(struct fimc_control *ctrl,
+			  struct fimc_ctx *ctx,
+			  struct v4l2_format *f)
+{
+	if (ctx->win.w.width != f->fmt.win.w.width) {
+		fimc_err("%s: cannot change width(%d,%d)\n", __func__,
+				ctx->win.w.width, f->fmt.win.w.width);
+		return -EINVAL;
+	} else if (ctx->win.w.height != f->fmt.win.w.height) {
+		fimc_err("%s: cannot change height(%d,%d)\n", __func__,
+				ctx->win.w.height, f->fmt.win.w.height);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fimc_change_fifo_position(struct fimc_control *ctrl,
+				     struct fimc_ctx *ctx) {
+	struct v4l2_rect fimd_rect;
+	struct s3cfb_user_window window;
+	int ret = -1;
+
+	memset(&fimd_rect, 0, sizeof(struct v4l2_rect));
+
+	ret = fimc_fimd_rect(ctrl, ctx, &fimd_rect);
+	if (ret < 0) {
+		fimc_err("fimc_fimd_rect fail\n");
+		return -EINVAL;
+	}
+
+	/* Update WIN position */
+	window.x = fimd_rect.left;
+	window.y = fimd_rect.top;
+	ret = s3cfb_direct_ioctl(ctrl->id, S3CFB_WIN_POSITION,
+			(unsigned long)&window);
+	if (ret < 0) {
+		fimc_err("direct_ioctl(S3CFB_WIN_POSITION) fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int fimc_s_fmt_vid_overlay(struct file *filp, void *fh, struct v4l2_format *f)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+	int ret = -1;
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: called\n", __func__);
+
+	switch (ctx->status) {
+	case FIMC_STREAMON:
+		ret = fimc_check_pos(ctrl, ctx, f);
+		if (ret < 0) {
+			fimc_err("When FIMC is running, "
+				"you can only move the position.\n");
+			return -EBUSY;
+		}
+
+		ret = fimc_try_fmt_overlay(filp, fh, f);
+		if (ret < 0)
+			return ret;
+
+		ctx->win = f->fmt.win;
+		fimc_change_fifo_position(ctrl, ctx);
+
+		break;
+	case FIMC_STREAMOFF:
+		ret = fimc_try_fmt_overlay(filp, fh, f);
+		if (ret < 0)
+			return ret;
+		ctx->win = f->fmt.win;
+
+		break;
+
+	default:
+		fimc_err("FIMC is running\n");
+		fimc_err("%s::FIMC is running(%d)\n", __func__, ctx->status);
+		return -EBUSY;
+	}
+
+	return ret;
+}
+
+int fimc_g_fbuf(struct file *filp, void *fh, struct v4l2_framebuffer *fb)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+	u32 bpp = 1, format;
+
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: called\n", __func__);
+
+	fb->capability = ctx->fbuf.capability;
+	fb->flags = 0;
+	fb->base = ctx->fbuf.base;
+
+	fb->fmt.width = ctx->fbuf.fmt.width;
+	fb->fmt.height = ctx->fbuf.fmt.height;
+	fb->fmt.pixelformat = ctx->fbuf.fmt.pixelformat;
+	format = ctx->fbuf.fmt.pixelformat;
+
+	switch (format) {
+	case V4L2_PIX_FMT_YUV420: /* fall through */
+	case V4L2_PIX_FMT_YVU420: /* fall through */
+	case V4L2_PIX_FMT_NV12:
+		bpp = 1;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+		bpp = 2;
+		break;
+	case V4L2_PIX_FMT_RGB32:
+		bpp = 4;
+		break;
+	}
+
+	ctx->fbuf.fmt.bytesperline = fb->fmt.width * bpp;
+	fb->fmt.bytesperline = ctx->fbuf.fmt.bytesperline;
+	fb->fmt.sizeimage = ctx->fbuf.fmt.sizeimage;
+	fb->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M;
+	fb->fmt.priv = 0;
+
+	return 0;
+}
+
+int fimc_s_fbuf(struct file *filp, void *fh, struct v4l2_framebuffer *fb)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ctx_id = ((struct fimc_prv_data *)fh)->ctx_id;
+	struct fimc_ctx *ctx;
+	u32 bpp = 1;
+	u32 format = fb->fmt.pixelformat;
+	ctx = &ctrl->out->ctx[ctx_id];
+
+	fimc_info1("%s: called. width(%d), height(%d)\n",
+			__func__, fb->fmt.width, fb->fmt.height);
+
+	ctx->fbuf.capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+	ctx->fbuf.flags = 0;
+	ctx->fbuf.base = fb->base;
+
+	if (ctx->overlay.mode == FIMC_OVLY_NONE_MULTI_BUF) {
+		ctx->fbuf.fmt.width = fb->fmt.width;
+		ctx->fbuf.fmt.height = fb->fmt.height;
+		ctx->fbuf.fmt.pixelformat = fb->fmt.pixelformat;
+
+		switch (format) {
+		case V4L2_PIX_FMT_NV21: 	/* fall through */
+		case V4L2_PIX_FMT_YUV420: /* fall through */
+		case V4L2_PIX_FMT_NV12:
+			bpp = 1;
+			break;
+		case V4L2_PIX_FMT_RGB565:
+			bpp = 2;
+			break;
+		case V4L2_PIX_FMT_RGB32:
+			bpp = 4;
+			break;
+		}
+
+		ctx->fbuf.fmt.bytesperline = fb->fmt.width * bpp;
+		ctx->fbuf.fmt.sizeimage = fb->fmt.sizeimage;
+		ctx->fbuf.fmt.colorspace = V4L2_COLORSPACE_SMPTE170M;
+		ctx->fbuf.fmt.priv = 0;
+	} else if (fb->base) {
+		ctx->fbuf.fmt.width = fb->fmt.width;
+		ctx->fbuf.fmt.height = fb->fmt.height;
+		ctx->fbuf.fmt.pixelformat = fb->fmt.pixelformat;
+
+		switch (format) {
+		case V4L2_PIX_FMT_NV21:		/* fall through */
+		case V4L2_PIX_FMT_YUV420:	/* fall through */
+		case V4L2_PIX_FMT_YVU420:	/* fall through */
+		case V4L2_PIX_FMT_NV12:
+			bpp = 1;
+			break;
+		case V4L2_PIX_FMT_RGB565:
+			bpp = 2;
+			break;
+		case V4L2_PIX_FMT_RGB32:
+			bpp = 4;
+			break;
+		}
+
+		ctx->fbuf.fmt.bytesperline = fb->fmt.width * bpp;
+		ctx->fbuf.fmt.sizeimage = fb->fmt.sizeimage;
+		ctx->fbuf.fmt.colorspace = V4L2_COLORSPACE_SMPTE170M;
+		ctx->fbuf.fmt.priv = 0;
+
+		ctx->overlay.mode = FIMC_OVLY_NONE_SINGLE_BUF;
+	} else {
+		ctx->overlay.mode = FIMC_OVLY_NOT_FIXED;
+	}
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/fimc/fimc_regs.c b/drivers/media/video/samsung/fimc/fimc_regs.c
new file mode 100644
index 0000000..332e5db
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_regs.c
@@ -0,0 +1,2119 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_regs.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register interface file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-fimc.h>
+#include <plat/fimc.h>
+
+#include "fimc.h"
+
+/* struct fimc_limit: Limits for FIMC */
+struct fimc_limit fimc40_limits[FIMC_DEVICES] = {
+	{
+		.pre_dst_w	= 3264,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 3264,
+		.trg_h_rot	= 1280,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1280,
+	}, {
+		.pre_dst_w	= 1280,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 1280,
+		.trg_h_rot	= 8192,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 768,
+	}, {
+		.pre_dst_w	= 1440,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 1440,
+		.trg_h_rot	= 0,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 0,
+	},
+};
+
+struct fimc_limit fimc43_limits[FIMC_DEVICES] = {
+	{
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 1920,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 1920,
+		.trg_h_rot	= 1280,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1280,
+	},
+};
+
+struct fimc_limit fimc50_limits[FIMC_DEVICES] = {
+	{
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 1920,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 1920,
+		.trg_h_rot	= 1280,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1280,
+	},
+};
+
+struct fimc_limit fimc51_limits[FIMC_DEVICES] = {
+	{
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+		.pre_dst_w	= 4224,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 4224,
+		.trg_h_rot	= 1920,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1920,
+	}, {
+
+		.pre_dst_w	= 1920,
+		.bypass_w	= 8192,
+		.trg_h_no_rot	= 1920,
+		.trg_h_rot	= 1280,
+		.real_w_no_rot	= 8192,
+		.real_h_rot	= 1280,
+	},
+};
+
+int fimc_hwset_camera_source(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg = 0;
+
+	/* for now, we support only ITU601 8 bit mode */
+	cfg |= S3C_CISRCFMT_ITU601_8BIT;
+	cfg |= cam->order422;
+
+	if (cam->type == CAM_TYPE_ITU)
+		cfg |= cam->fmt;
+
+	if (ctrl->is.sd) {
+		cfg |= S3C_CISRCFMT_SOURCEHSIZE(ctrl->is.fmt.width);
+		cfg |= S3C_CISRCFMT_SOURCEVSIZE(ctrl->is.fmt.height);
+	} else {
+		cfg |= S3C_CISRCFMT_SOURCEHSIZE(cam->width);
+		cfg |= S3C_CISRCFMT_SOURCEVSIZE(cam->height);
+	}
+
+	writel(cfg, ctrl->regs + S3C_CISRCFMT);
+
+	return 0;
+}
+
+int fimc_hwset_camera_change_source(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg = 0;
+
+	/* for now, we support only ITU601 8 bit mode */
+	cfg |= S3C_CISRCFMT_ITU601_8BIT;
+	cfg |= cam->order422;
+
+	if (cam->type == CAM_TYPE_ITU)
+		cfg |= cam->fmt;
+
+	if (ctrl->is.sd) {
+		cfg |= S3C_CISRCFMT_SOURCEHSIZE(ctrl->is.zoom_in_width);
+		cfg |= S3C_CISRCFMT_SOURCEVSIZE(ctrl->is.zoom_in_height);
+	} else {
+		cfg |= S3C_CISRCFMT_SOURCEHSIZE(cam->width);
+		cfg |= S3C_CISRCFMT_SOURCEVSIZE(cam->height);
+	}
+
+	writel(cfg, ctrl->regs + S3C_CISRCFMT);
+
+	return 0;
+}
+
+int fimc_hwset_enable_irq(struct fimc_control *ctrl, int overflow, int level)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIGCTRL);
+
+	cfg &= ~(S3C_CIGCTRL_IRQ_OVFEN | S3C_CIGCTRL_IRQ_LEVEL);
+	cfg |= S3C_CIGCTRL_IRQ_ENABLE;
+
+	if (overflow)
+		cfg |= S3C_CIGCTRL_IRQ_OVFEN;
+
+	if (level)
+		cfg |= S3C_CIGCTRL_IRQ_LEVEL;
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_disable_irq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIGCTRL);
+
+	cfg &= ~(S3C_CIGCTRL_IRQ_OVFEN | S3C_CIGCTRL_IRQ_ENABLE);
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_clear_irq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIGCTRL);
+
+	cfg |= S3C_CIGCTRL_IRQ_CLR;
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_output_area_size(struct fimc_control *ctrl, u32 size)
+{
+	u32 cfg = 0;
+
+	cfg = S3C_CITAREA_TARGET_AREA(size);
+
+	writel(cfg, ctrl->regs + S3C_CITAREA);
+
+	return 0;
+}
+
+
+int fimc_hwset_image_effect(struct fimc_control *ctrl)
+{
+	u32 cfg = 0;
+
+	if (ctrl->fe.ie_on) {
+		if (ctrl->fe.ie_after_sc)
+			cfg |= S3C_CIIMGEFF_IE_SC_AFTER;
+
+		cfg |= S3C_CIIMGEFF_FIN(ctrl->fe.fin);
+
+		if (ctrl->fe.fin == FIMC_EFFECT_FIN_ARBITRARY_CBCR) {
+			cfg |= S3C_CIIMGEFF_PAT_CB(ctrl->fe.pat_cb)
+					| S3C_CIIMGEFF_PAT_CR(ctrl->fe.pat_cr);
+		}
+
+		cfg |= S3C_CIIMGEFF_IE_ENABLE;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CIIMGEFF);
+
+	return 0;
+}
+
+static void fimc_reset_cfg(struct fimc_control *ctrl)
+{
+	int i;
+	u32 cfg[][2] = {
+		{ 0x018, 0x00000000 }, { 0x01c, 0x00000000 },
+		{ 0x020, 0x00000000 }, { 0x024, 0x00000000 },
+		{ 0x028, 0x00000000 }, { 0x02c, 0x00000000 },
+		{ 0x030, 0x00000000 }, { 0x034, 0x00000000 },
+		{ 0x038, 0x00000000 }, { 0x03c, 0x00000000 },
+		{ 0x040, 0x00000000 }, { 0x044, 0x00000000 },
+		{ 0x048, 0x00000000 }, { 0x04c, 0x00000000 },
+		{ 0x050, 0x00000000 }, { 0x054, 0x00000000 },
+		{ 0x058, 0x18000000 }, { 0x05c, 0x00000000 },
+		{ 0x064, 0x00000000 },
+		{ 0x0c0, 0x00000000 }, { 0x0c4, 0xffffffff },
+		{ 0x0d0, 0x00100080 }, { 0x0d4, 0x00000000 },
+		{ 0x0d8, 0x00000000 }, { 0x0dc, 0x00000000 },
+		{ 0x0f8, 0x00000000 }, { 0x0fc, 0x04000000 },
+		{ 0x168, 0x00000000 }, { 0x16c, 0x00000000 },
+		{ 0x170, 0x00000000 }, { 0x174, 0x00000000 },
+		{ 0x178, 0x00000000 }, { 0x17c, 0x00000000 },
+		{ 0x180, 0x00000000 }, { 0x184, 0x00000000 },
+		{ 0x188, 0x00000000 }, { 0x18c, 0x00000000 },
+		{ 0x194, 0x0000001e },
+	};
+
+	for (i = 0; i < sizeof(cfg) / 8; i++)
+		writel(cfg[i][1], ctrl->regs + cfg[i][0]);
+}
+
+int fimc_hwset_reset(struct fimc_control *ctrl)
+{
+	u32 cfg = 0;
+
+	cfg = readl(ctrl->regs + S3C_CISRCFMT);
+	cfg |= S3C_CISRCFMT_ITU601_8BIT;
+	writel(cfg, ctrl->regs + S3C_CISRCFMT);
+
+	/* s/w reset */
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg |= (S3C_CIGCTRL_SWRST);
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+	mdelay(1);
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~S3C_CIGCTRL_SWRST;
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	/* in case of ITU656, CISRCFMT[31] should be 0 */
+	if ((ctrl->cap != NULL) && (ctrl->cam != NULL)) {
+		if (ctrl->cam->fmt == ITU_656_YCBCR422_8BIT) {
+			cfg = readl(ctrl->regs + S3C_CISRCFMT);
+			cfg &= ~S3C_CISRCFMT_ITU601_8BIT;
+			writel(cfg, ctrl->regs + S3C_CISRCFMT);
+		}
+	}
+
+	fimc_reset_cfg(ctrl);
+
+	return 0;
+}
+
+int fimc_hwset_sw_reset(struct fimc_control *ctrl)
+{
+	u32 cfg = 0;
+	u32 status;
+	int i;
+
+	for (i = 0; i < 10; i++) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+		status = S3C_CISTATUS_GET_ENVID_STATUS(cfg);
+		if(status == 0)
+			break;
+		udelay(100);
+	}
+
+	if (i == 10)
+		fimc_err("%s: SWRST is called while Input DMA RUNNING\n", __func__);
+
+	cfg = readl(ctrl->regs + S3C_CISRCFMT);
+	cfg |= S3C_CISRCFMT_ITU601_8BIT;
+	writel(cfg, ctrl->regs + S3C_CISRCFMT);
+
+	/* s/w reset */
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg |= (S3C_CIGCTRL_SWRST);
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~S3C_CIGCTRL_SWRST;
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_clksrc(struct fimc_control *ctrl, int src_clk)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MISC_FIMC);
+	cfg &= ~S3C_CLKSRC_HCLK_MASK;
+
+	if (src_clk == FIMC_HCLK)
+		cfg |= S3C_CLKSRC_HCLK;
+	else if (src_clk == FIMC_SCLK)
+		cfg |= S3C_CLKSRC_SCLK;
+
+	writel(cfg, ctrl->regs + S3C_MISC_FIMC);
+	return 0;
+}
+
+int fimc_hwget_overflow_state(struct fimc_control *ctrl)
+{
+	u32 cfg, status, flag;
+
+	status = readl(ctrl->regs + S3C_CISTATUS);
+	flag = S3C_CISTATUS_OVFIY | S3C_CISTATUS_OVFICB | S3C_CISTATUS_OVFICR;
+
+	if (status & flag) {
+		cfg = readl(ctrl->regs + S3C_CIWDOFST);
+		cfg |= (S3C_CIWDOFST_CLROVFIY | S3C_CIWDOFST_CLROVFICB |
+			S3C_CIWDOFST_CLROVFICR);
+		writel(cfg, ctrl->regs + S3C_CIWDOFST);
+
+		cfg = readl(ctrl->regs + S3C_CIWDOFST);
+		cfg &= ~(S3C_CIWDOFST_CLROVFIY | S3C_CIWDOFST_CLROVFICB |
+			S3C_CIWDOFST_CLROVFICR);
+		writel(cfg, ctrl->regs + S3C_CIWDOFST);
+
+		printk(KERN_INFO "FIMC%d overflow is occured status 0x%x\n",
+				ctrl->id, status);
+		return 1;
+	}
+
+	return 0;
+}
+
+int fimc_hwset_camera_offset(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	struct v4l2_rect *rect = &cam->window;
+	u32 cfg, h1, h2, v1, v2;
+
+	if (!cam) {
+		fimc_err("%s: no active camera\n", __func__);
+		return -ENODEV;
+	}
+
+	h1 = rect->left;
+	h2 = cam->width - rect->width - rect->left;
+	v1 = rect->top;
+	v2 = cam->height - rect->height - rect->top;
+
+	cfg = readl(ctrl->regs + S3C_CIWDOFST);
+	cfg &= ~(S3C_CIWDOFST_WINHOROFST_MASK | S3C_CIWDOFST_WINVEROFST_MASK);
+	cfg |= S3C_CIWDOFST_WINHOROFST(h1);
+	cfg |= S3C_CIWDOFST_WINVEROFST(v1);
+	cfg |= S3C_CIWDOFST_WINOFSEN;
+	writel(cfg, ctrl->regs + S3C_CIWDOFST);
+
+	cfg = 0;
+	cfg |= S3C_CIWDOFST2_WINHOROFST2(h2);
+	cfg |= S3C_CIWDOFST2_WINVEROFST2(v2);
+	writel(cfg, ctrl->regs + S3C_CIWDOFST2);
+
+	return 0;
+}
+
+int fimc_hwset_camera_polarity(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg;
+
+	if (!cam) {
+		fimc_err("%s: no active camera\n", __func__);
+		return -ENODEV;
+	}
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+
+	cfg &= ~(S3C_CIGCTRL_INVPOLPCLK | S3C_CIGCTRL_INVPOLVSYNC |
+		 S3C_CIGCTRL_INVPOLHREF | S3C_CIGCTRL_INVPOLHSYNC);
+
+	if (cam->inv_pclk)
+		cfg |= S3C_CIGCTRL_INVPOLPCLK;
+
+	if (cam->inv_vsync)
+		cfg |= S3C_CIGCTRL_INVPOLVSYNC;
+
+	if (cam->inv_href)
+		cfg |= S3C_CIGCTRL_INVPOLHREF;
+
+	if (cam->inv_hsync)
+		cfg |= S3C_CIGCTRL_INVPOLHSYNC;
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc40_hwset_camera_type(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg;
+
+	if (!cam) {
+		fimc_err("%s: no active camera\n", __func__);
+		return -ENODEV;
+	}
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~(S3C_CIGCTRL_TESTPATTERN_MASK | S3C_CIGCTRL_SELCAM_ITU_MASK |
+		S3C_CIGCTRL_SELCAM_FIMC_MASK);
+
+	/* Interface selection */
+	if (cam->type == CAM_TYPE_MIPI) {
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_MIPI;
+		writel(cam->fmt, ctrl->regs + S3C_CSIIMGFMT);
+	} else if (cam->type == CAM_TYPE_ITU) {
+		if (cam->id == CAMERA_PAR_A)
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_A;
+		else
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_B;
+		/* switch to ITU interface */
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_ITU;
+	} else {
+		fimc_err("%s: invalid camera bus type selected\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc43_hwset_camera_type(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg;
+
+	if (!cam) {
+		fimc_err("%s: no active camera\n", __func__);
+		return -ENODEV;
+	}
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~(S3C_CIGCTRL_TESTPATTERN_MASK | S3C_CIGCTRL_SELCAM_ITU_MASK |
+		S3C_CIGCTRL_SELCAM_MIPI_MASK | S3C_CIGCTRL_SELCAM_FIMC_MASK |
+		S3C_CIGCTRL_SELWB_CAMIF_MASK);
+
+	/* Interface selection */
+	if (cam->id == CAMERA_WB) {
+		cfg |= S3C_CIGCTRL_SELWB_CAMIF_WRITEBACK;
+	} else if (cam->type == CAM_TYPE_MIPI) {
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_MIPI;
+
+		/* C110/V210 Support only MIPI A support */
+		cfg |= S3C_CIGCTRL_SELCAM_MIPI_A;
+
+		/* FIXME: Temporary MIPI CSIS Data 32 bit aligned */
+		if (ctrl->cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG ||
+			ctrl->cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED)
+			writel((MIPI_USER_DEF_PACKET_1 | (0x1 << 8)),
+					ctrl->regs + S3C_CSIIMGFMT);
+		else
+			writel(cam->fmt | (0x1 << 8), ctrl->regs + S3C_CSIIMGFMT);
+	} else if (cam->type == CAM_TYPE_ITU) {
+		if (cam->id == CAMERA_PAR_A)
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_A;
+		else
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_B;
+		/* switch to ITU interface */
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_ITU;
+	} else {
+		fimc_err("%s: invalid camera bus type selected\n", __func__);
+		return -EINVAL;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc51_hwset_camera_type(struct fimc_control *ctrl)
+{
+	struct s3c_platform_camera *cam = ctrl->cam;
+	u32 cfg;
+
+	if (!cam) {
+		fimc_err("%s: no active camera\n", __func__);
+		return -ENODEV;
+	}
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~(S3C_CIGCTRL_TESTPATTERN_MASK | S3C_CIGCTRL_SELCAM_ITU_MASK |
+		S3C_CIGCTRL_SELCAM_MIPI_MASK | S3C_CIGCTRL_SELCAM_FIMC_MASK |
+		S3C_CIGCTRL_SELWB_CAMIF_MASK | S3C_CIGCTRL_SELWRITEBACK_MASK);
+
+	/* Interface selection */
+	if (cam->id == CAMERA_WB) {
+		cfg |= S3C_CIGCTRL_SELWB_CAMIF_WRITEBACK;
+		cfg |= S3C_CIGCTRL_SELWRITEBACK_A;
+	} else if (cam->id == CAMERA_WB_B || cam->use_isp) {
+		cfg |= S3C_CIGCTRL_SELWB_CAMIF_WRITEBACK;
+		cfg |= S3C_CIGCTRL_SELWRITEBACK_B;
+	} else if (cam->type == CAM_TYPE_MIPI) {
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_MIPI;
+
+		/* V310 Support MIPI A/B support */
+		if (cam->id == CAMERA_CSI_C)
+			cfg |= S3C_CIGCTRL_SELCAM_MIPI_A;
+		else
+			cfg |= S3C_CIGCTRL_SELCAM_MIPI_B;
+
+		/* FIXME: Temporary MIPI CSIS Data 32 bit aligned */
+		if (ctrl->cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG ||
+			ctrl->cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED)
+			writel((MIPI_USER_DEF_PACKET_1 | (0x1 << 8)),
+					ctrl->regs + S3C_CSIIMGFMT);
+		else
+			writel(cam->fmt | (0x1 << 8), ctrl->regs + S3C_CSIIMGFMT);
+	} else if (cam->type == CAM_TYPE_ITU) {
+		if (cam->id == CAMERA_PAR_A)
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_A;
+		else
+			cfg |= S3C_CIGCTRL_SELCAM_ITU_B;
+		/* switch to ITU interface */
+		cfg |= S3C_CIGCTRL_SELCAM_FIMC_ITU;
+	} else {
+		fimc_err("%s: invalid camera bus type selected\n", __func__);
+		return -EINVAL;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+int fimc_hwset_camera_type(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	switch (pdata->hw_ver) {
+	case 0x40:
+		fimc40_hwset_camera_type(ctrl);
+		break;
+	case 0x43:
+	case 0x45:
+		fimc43_hwset_camera_type(ctrl);
+		break;
+	case 0x51:
+		fimc51_hwset_camera_type(ctrl);
+		break;
+	default:
+		fimc43_hwset_camera_type(ctrl);
+		break;
+	}
+
+	return 0;
+}
+
+
+int fimc_hwset_jpeg_mode(struct fimc_control *ctrl, bool enable)
+{
+	u32 cfg;
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+
+	if (enable)
+		cfg |= S3C_CIGCTRL_CAM_JPEG;
+	else
+		cfg &= ~S3C_CIGCTRL_CAM_JPEG;
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_output_size(struct fimc_control *ctrl, int width, int height)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CITRGFMT);
+
+	cfg &= ~(S3C_CITRGFMT_TARGETH_MASK | S3C_CITRGFMT_TARGETV_MASK);
+
+	cfg |= S3C_CITRGFMT_TARGETHSIZE(width);
+	cfg |= S3C_CITRGFMT_TARGETVSIZE(height);
+
+	writel(cfg, ctrl->regs + S3C_CITRGFMT);
+
+	return 0;
+}
+
+int fimc_hwset_output_colorspace(struct fimc_control *ctrl, u32 pixelformat)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg;
+
+	if (pdata->hw_ver != 0x40) {
+		if (pixelformat == V4L2_PIX_FMT_YUV444) {
+			cfg = readl(ctrl->regs + S3C_CIEXTEN);
+			cfg |= S3C_CIEXTEN_YUV444_OUT;
+			writel(cfg, ctrl->regs + S3C_CIEXTEN);
+
+			return 0;
+		} else {
+			cfg = readl(ctrl->regs + S3C_CIEXTEN);
+			cfg &= ~S3C_CIEXTEN_YUV444_OUT;
+			writel(cfg, ctrl->regs + S3C_CIEXTEN);
+		}
+	}
+
+	cfg = readl(ctrl->regs + S3C_CITRGFMT);
+	cfg &= ~S3C_CITRGFMT_OUTFORMAT_MASK;
+
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_JPEG:
+	case V4L2_PIX_FMT_INTERLEAVED:
+		break;
+	case V4L2_PIX_FMT_RGB565: /* fall through */
+	case V4L2_PIX_FMT_RGB32:
+		cfg |= S3C_CITRGFMT_OUTFORMAT_RGB;
+		break;
+
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:		/* fall through */
+	case V4L2_PIX_FMT_YVYU:
+		cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
+		break;
+
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:		/* fall through */
+	case V4L2_PIX_FMT_YUV422P:
+		cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422;
+		break;
+
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12M:	/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_NV21:
+		cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR420;
+		break;
+
+	default:
+		fimc_err("%s: invalid pixel format : %d\n",
+				__func__, pixelformat);
+		break;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CITRGFMT);
+
+	return 0;
+}
+
+int fimc_hwset_output_rot_flip(struct fimc_control *ctrl, u32 rot, u32 flip)
+{
+	u32 cfg, val;
+
+	cfg = readl(ctrl->regs + S3C_CITRGFMT);
+	cfg &= ~S3C_CITRGFMT_FLIP_MASK;
+	cfg &= ~S3C_CITRGFMT_OUTROT90_CLOCKWISE;
+
+	val = fimc_mapping_rot_flip(rot, flip);
+
+	if (val & FIMC_ROT)
+		cfg |= S3C_CITRGFMT_OUTROT90_CLOCKWISE;
+
+	if (val & FIMC_XFLIP)
+		cfg |= S3C_CITRGFMT_FLIP_X_MIRROR;
+
+	if (val & FIMC_YFLIP)
+		cfg |= S3C_CITRGFMT_FLIP_Y_MIRROR;
+
+	writel(cfg, ctrl->regs + S3C_CITRGFMT);
+
+	return 0;
+}
+
+int fimc_hwset_output_area(struct fimc_control *ctrl, u32 width, u32 height)
+{
+	u32 cfg = 0;
+
+	cfg = S3C_CITAREA_TARGET_AREA(width * height);
+	writel(cfg, ctrl->regs + S3C_CITAREA);
+
+	return 0;
+}
+
+int fimc_hwset_enable_lastirq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIOCTRL);
+
+	cfg |= S3C_CIOCTRL_LASTIRQ_ENABLE;
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_disable_lastirq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIOCTRL);
+
+	cfg &= ~S3C_CIOCTRL_LASTIRQ_ENABLE;
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_enable_lastend(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIOCTRL);
+
+	cfg |= S3C_CIOCTRL_LASTENDEN;
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_disable_lastend(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIOCTRL);
+
+	cfg &= ~S3C_CIOCTRL_LASTENDEN;
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_prescaler(struct fimc_control *ctrl, struct fimc_scaler *sc)
+{
+	u32 cfg = 0, shfactor;
+
+	shfactor = 10 - (sc->hfactor + sc->vfactor);
+
+	cfg |= S3C_CISCPRERATIO_SHFACTOR(shfactor);
+	cfg |= S3C_CISCPRERATIO_PREHORRATIO(sc->pre_hratio);
+	cfg |= S3C_CISCPRERATIO_PREVERRATIO(sc->pre_vratio);
+
+	writel(cfg, ctrl->regs + S3C_CISCPRERATIO);
+
+	cfg = 0;
+	cfg |= S3C_CISCPREDST_PREDSTWIDTH(sc->pre_dst_width);
+	cfg |= S3C_CISCPREDST_PREDSTHEIGHT(sc->pre_dst_height);
+
+	writel(cfg, ctrl->regs + S3C_CISCPREDST);
+
+	return 0;
+}
+
+int fimc_hwset_output_address(struct fimc_control *ctrl,
+			      struct fimc_buf_set *bs, int id)
+{
+	writel(bs->base[FIMC_ADDR_Y], ctrl->regs + S3C_CIOYSA(id));
+
+	if (ctrl->cap && ctrl->cap->fmt.pixelformat == V4L2_PIX_FMT_YVU420) {
+		writel(bs->base[FIMC_ADDR_CR], ctrl->regs + S3C_CIOCBSA(id));
+		writel(bs->base[FIMC_ADDR_CB], ctrl->regs + S3C_CIOCRSA(id));
+	} else {
+		writel(bs->base[FIMC_ADDR_CB], ctrl->regs + S3C_CIOCBSA(id));
+		writel(bs->base[FIMC_ADDR_CR], ctrl->regs + S3C_CIOCRSA(id));
+	}
+
+	return 0;
+}
+
+int fimc_hwset_output_yuv(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg;
+
+	cfg = readl(ctrl->regs + S3C_CIOCTRL);
+	cfg &= ~(S3C_CIOCTRL_ORDER2P_MASK | S3C_CIOCTRL_ORDER422_MASK |
+		S3C_CIOCTRL_YCBCR_PLANE_MASK);
+
+	switch (pixelformat) {
+	/* 1 plane formats */
+	case V4L2_PIX_FMT_YUYV:
+		cfg |= S3C_CIOCTRL_ORDER422_YCBYCR;
+		break;
+
+	case V4L2_PIX_FMT_UYVY:
+		cfg |= S3C_CIOCTRL_ORDER422_CBYCRY;
+		break;
+
+	case V4L2_PIX_FMT_VYUY:
+		cfg |= S3C_CIOCTRL_ORDER422_CRYCBY;
+		break;
+
+	case V4L2_PIX_FMT_YVYU:
+		cfg |= S3C_CIOCTRL_ORDER422_YCRYCB;
+		break;
+
+	/* 2 plane formats */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12M:	/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_NV16:
+		cfg |= S3C_CIOCTRL_ORDER2P_LSB_CBCR;
+		cfg |= S3C_CIOCTRL_YCBCR_2PLANE;
+		break;
+
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV61:
+		cfg |= S3C_CIOCTRL_ORDER2P_LSB_CRCB;
+		cfg |= S3C_CIOCTRL_YCBCR_2PLANE;
+		break;
+
+	/* 3 plane formats */
+	case V4L2_PIX_FMT_YUV422P:	/* fall through */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		cfg |= S3C_CIOCTRL_YCBCR_3PLANE;
+		break;
+
+	/*  Set alpha value to 0xff */
+	case V4L2_PIX_FMT_RGB565:       /*  fall through */
+	case V4L2_PIX_FMT_RGB32:
+		cfg |= (0xff << 4);
+		break;
+	}
+
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_output_scan(struct fimc_control *ctrl,
+			   struct v4l2_pix_format *fmt)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg;
+
+	/* nothing to do: FIMC40 not supported interlaced and weave output */
+	if (pdata->hw_ver == 0x40)
+		return 0;
+
+	cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	cfg &= ~S3C_CISCCTRL_SCAN_MASK;
+
+	if (fmt->field == V4L2_FIELD_INTERLACED ||
+		fmt->field == V4L2_FIELD_INTERLACED_TB)
+		cfg |= S3C_CISCCTRL_INTERLACE;
+	else
+		cfg |= S3C_CISCCTRL_PROGRESSIVE;
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	cfg = readl(ctrl->regs + S3C_CIOCTRL);
+	cfg &= ~S3C_CIOCTRL_WEAVE_MASK;
+
+	if ((ctrl->cap) && (fmt->field == V4L2_FIELD_INTERLACED_TB))
+		cfg |= S3C_CIOCTRL_WEAVE_OUT;
+
+	writel(cfg, ctrl->regs + S3C_CIOCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_rot(struct fimc_control *ctrl, u32 rot, u32 flip)
+{
+	u32 cfg, val;
+
+	cfg = readl(ctrl->regs + S3C_CITRGFMT);
+	cfg &= ~S3C_CITRGFMT_INROT90_CLOCKWISE;
+
+	val = fimc_mapping_rot_flip(rot, flip);
+
+	if (val & FIMC_ROT)
+		cfg |= S3C_CITRGFMT_INROT90_CLOCKWISE;
+
+	writel(cfg, ctrl->regs + S3C_CITRGFMT);
+
+	return 0;
+}
+
+int fimc40_hwset_scaler(struct fimc_control *ctrl, struct fimc_scaler *sc)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg &= ~(S3C_CISCCTRL_SCALERBYPASS |
+		S3C_CISCCTRL_SCALEUP_H | S3C_CISCCTRL_SCALEUP_V |
+		S3C_CISCCTRL_MAIN_V_RATIO_MASK |
+		S3C_CISCCTRL_MAIN_H_RATIO_MASK |
+		S3C_CISCCTRL_CSCR2Y_WIDE |
+		S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (ctrl->range == FIMC_RANGE_WIDE)
+		cfg |= (S3C_CISCCTRL_CSCR2Y_WIDE | S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (sc->bypass)
+		cfg |= S3C_CISCCTRL_SCALERBYPASS;
+
+	if (sc->scaleup_h)
+		cfg |= S3C_CISCCTRL_SCALEUP_H;
+
+	if (sc->scaleup_v)
+		cfg |= S3C_CISCCTRL_SCALEUP_V;
+
+	cfg |= S3C_CISCCTRL_MAINHORRATIO(sc->main_hratio);
+	cfg |= S3C_CISCCTRL_MAINVERRATIO(sc->main_vratio);
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc43_hwset_scaler(struct fimc_control *ctrl, struct fimc_scaler *sc)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	u32 cfg_ext = readl(ctrl->regs + S3C_CIEXTEN);
+
+	cfg &= ~(S3C_CISCCTRL_SCALERBYPASS |
+		S3C_CISCCTRL_SCALEUP_H | S3C_CISCCTRL_SCALEUP_V |
+		S3C_CISCCTRL_MAIN_V_RATIO_MASK |
+		S3C_CISCCTRL_MAIN_H_RATIO_MASK |
+		S3C_CISCCTRL_CSCR2Y_WIDE |
+		S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (ctrl->range == FIMC_RANGE_WIDE)
+		cfg |= (S3C_CISCCTRL_CSCR2Y_WIDE | S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (sc->bypass)
+		cfg |= S3C_CISCCTRL_SCALERBYPASS;
+
+	if (sc->scaleup_h)
+		cfg |= S3C_CISCCTRL_SCALEUP_H;
+
+	if (sc->scaleup_v)
+		cfg |= S3C_CISCCTRL_SCALEUP_V;
+
+	cfg |= S3C_CISCCTRL_MAINHORRATIO(sc->main_hratio);
+	cfg |= S3C_CISCCTRL_MAINVERRATIO(sc->main_vratio);
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	cfg_ext &= ~S3C_CIEXTEN_MAINHORRATIO_EXT_MASK;
+	cfg_ext &= ~S3C_CIEXTEN_MAINVERRATIO_EXT_MASK;
+
+	cfg_ext |= S3C_CIEXTEN_MAINHORRATIO_EXT(sc->main_hratio);
+	cfg_ext |= S3C_CIEXTEN_MAINVERRATIO_EXT(sc->main_vratio);
+
+	writel(cfg_ext, ctrl->regs + S3C_CIEXTEN);
+
+	return 0;
+}
+
+int fimc50_hwset_scaler(struct fimc_control *ctrl, struct fimc_scaler *sc)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	u32 cfg_ext = readl(ctrl->regs + S3C_CIEXTEN);
+
+	cfg &= ~(S3C_CISCCTRL_SCALERBYPASS |
+		S3C_CISCCTRL_SCALEUP_H | S3C_CISCCTRL_SCALEUP_V |
+		S3C_CISCCTRL_MAIN_V_RATIO_MASK |
+		S3C_CISCCTRL_MAIN_H_RATIO_MASK |
+		S3C_CISCCTRL_CSCR2Y_WIDE |
+		S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (ctrl->range == FIMC_RANGE_WIDE)
+		cfg |= (S3C_CISCCTRL_CSCR2Y_WIDE | S3C_CISCCTRL_CSCY2R_WIDE);
+
+	if (sc->bypass)
+		cfg |= S3C_CISCCTRL_SCALERBYPASS;
+
+	if (sc->scaleup_h)
+		cfg |= S3C_CISCCTRL_SCALEUP_H;
+
+	if (sc->scaleup_v)
+		cfg |= S3C_CISCCTRL_SCALEUP_V;
+
+	cfg |= S3C_CISCCTRL_MAINHORRATIO((sc->main_hratio >> 6));
+	cfg |= S3C_CISCCTRL_MAINVERRATIO((sc->main_vratio >> 6));
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	cfg_ext &= ~S3C_CIEXTEN_MAINHORRATIO_EXT_MASK;
+	cfg_ext &= ~S3C_CIEXTEN_MAINVERRATIO_EXT_MASK;
+
+	cfg_ext |= S3C_CIEXTEN_MAINHORRATIO_EXT(sc->main_hratio);
+	cfg_ext |= S3C_CIEXTEN_MAINVERRATIO_EXT(sc->main_vratio);
+
+	writel(cfg_ext, ctrl->regs + S3C_CIEXTEN);
+
+	return 0;
+}
+
+int fimc_hwset_scaler(struct fimc_control *ctrl, struct fimc_scaler *sc)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	switch (pdata->hw_ver) {
+	case 0x40:
+		fimc40_hwset_scaler(ctrl, sc);
+		break;
+	case 0x43:
+	case 0x45:
+		fimc43_hwset_scaler(ctrl, sc);
+		break;
+	case 0x50:
+	case 0x51:
+		fimc50_hwset_scaler(ctrl, sc);
+		break;
+	default:
+		fimc43_hwset_scaler(ctrl, sc);
+		break;
+	}
+
+	return 0;
+}
+
+
+int fimc_hwset_scaler_bypass(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg |= S3C_CISCCTRL_SCALERBYPASS;
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_enable_lcdfifo(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg |= S3C_CISCCTRL_LCDPATHEN_FIFO;
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_disable_lcdfifo(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg &= ~S3C_CISCCTRL_LCDPATHEN_FIFO;
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwget_frame_count(struct fimc_control *ctrl)
+{
+	return S3C_CISTATUS_GET_FRAME_COUNT(readl(ctrl->regs + S3C_CISTATUS));
+}
+
+int fimc_hwget_frame_end(struct fimc_control *ctrl)
+{
+	unsigned long timeo = jiffies;
+	u32 cfg;
+
+	timeo += 20;	/* waiting for 100ms */
+
+	cfg = readl(ctrl->regs + S3C_CISTATUS);
+	cfg &= ~S3C_CISTATUS_FRAMEEND;
+	writel(cfg, ctrl->regs + S3C_CISTATUS);
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+		if (S3C_CISTATUS_GET_FRAME_END(cfg)) {
+			cfg &= ~S3C_CISTATUS_FRAMEEND;
+			writel(cfg, ctrl->regs + S3C_CISTATUS);
+			break;
+		}
+		cond_resched();
+	}
+
+	return 0;
+}
+
+int fimc_hwget_last_frame_end(struct fimc_control *ctrl)
+{
+	unsigned long timeo = jiffies;
+	u32 cfg;
+
+	timeo += 20;	/* waiting for 100ms */
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+
+		if (S3C_CISTATUS_GET_LAST_CAPTURE_END(cfg)) {
+			cfg &= ~S3C_CISTATUS_LASTCAPTUREEND;
+			writel(cfg, ctrl->regs + S3C_CISTATUS);
+			break;
+		}
+		cond_resched();
+	}
+
+	return 0;
+}
+
+int fimc_hwset_start_scaler(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg |= S3C_CISCCTRL_SCALERSTART;
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_stop_scaler(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+
+	cfg &= ~S3C_CISCCTRL_SCALERSTART;
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_rgb(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	cfg &= ~S3C_CISCCTRL_INRGB_FMT_RGB_MASK;
+
+	if (pixelformat == V4L2_PIX_FMT_RGB32)
+		cfg |= S3C_CISCCTRL_INRGB_FMT_RGB888;
+	else if (pixelformat == V4L2_PIX_FMT_RGB565)
+		cfg |= S3C_CISCCTRL_INRGB_FMT_RGB565;
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_intput_field(struct fimc_control *ctrl, enum v4l2_field field)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg;
+
+	if (pdata->hw_ver == 0x40)
+		return 0;
+
+	cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~S3C_MSCTRL_FIELD_MASK;
+
+	if (field == V4L2_FIELD_NONE)
+		cfg |= S3C_MSCTRL_FIELD_NORMAL;
+	else if (field == V4L2_FIELD_INTERLACED_TB)
+		cfg |= S3C_MSCTRL_FIELD_WEAVE;
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_output_rgb(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	cfg &= ~S3C_CISCCTRL_OUTRGB_FMT_RGB_MASK;
+
+	if (pixelformat == V4L2_PIX_FMT_RGB32)
+		cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB888;
+	else if (pixelformat == V4L2_PIX_FMT_RGB565)
+		cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB565;
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_ext_rgb(struct fimc_control *ctrl, int enable)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CISCCTRL);
+	cfg &= ~S3C_CISCCTRL_EXTRGB_EXTENSION;
+
+	if (enable)
+		cfg |= S3C_CISCCTRL_EXTRGB_EXTENSION;
+
+	writel(cfg, ctrl->regs + S3C_CISCCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_enable_capture(struct fimc_control *ctrl, u32 bypass)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT);
+	cfg &= ~S3C_CIIMGCPT_IMGCPTEN_SC;
+	cfg |= S3C_CIIMGCPT_IMGCPTEN;
+
+	if (!bypass)
+		cfg |= S3C_CIIMGCPT_IMGCPTEN_SC;
+
+	writel(cfg, ctrl->regs + S3C_CIIMGCPT);
+
+	return 0;
+}
+
+int fimc_hwset_disable_capture(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT);
+
+	cfg &= ~(S3C_CIIMGCPT_IMGCPTEN_SC | S3C_CIIMGCPT_IMGCPTEN);
+
+	writel(cfg, ctrl->regs + S3C_CIIMGCPT);
+
+	return 0;
+}
+
+void fimc_wait_disable_capture(struct fimc_control *ctrl)
+{
+	unsigned long timeo = jiffies + 40; /* timeout of 200 ms */
+	u32 cfg;
+	if (!ctrl || !ctrl->cap)
+		return;
+	while (time_before(jiffies, timeo)) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+
+		if (0 == (cfg & S3C_CISTATUS_IMGCPTEN)	\
+			&& 0 == (cfg & S3C_CISTATUS_IMGCPTENSC)	\
+			&& 0 == (cfg & S3C_CISTATUS_SCALERSTART))
+			break;
+		msleep(5);
+	}
+	fimc_info2("IMGCPTEN: Wait time = %d ms\n"	\
+		, jiffies_to_msecs(jiffies - timeo + 20));
+	return;
+}
+
+int fimc_hwset_input_address(struct fimc_control *ctrl, dma_addr_t *base)
+{
+	writel(base[FIMC_ADDR_Y], ctrl->regs + S3C_CIIYSA0);
+	writel(base[FIMC_ADDR_CB], ctrl->regs + S3C_CIICBSA0);
+	writel(base[FIMC_ADDR_CR], ctrl->regs + S3C_CIICRSA0);
+
+	return 0;
+}
+
+int fimc_hwset_enable_autoload(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE);
+
+	cfg |= S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE;
+
+	writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_disable_autoload(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE);
+
+	cfg &= ~S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE;
+
+	writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_real_input_size(struct fimc_control *ctrl, u32 width, u32 height)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE);
+	cfg &= ~(S3C_CIREAL_ISIZE_HEIGHT_MASK | S3C_CIREAL_ISIZE_WIDTH_MASK);
+
+	cfg |= S3C_CIREAL_ISIZE_WIDTH(width);
+	cfg |= S3C_CIREAL_ISIZE_HEIGHT(height);
+
+	writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_addr_change_enable(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE);
+
+	cfg &= ~S3C_CIREAL_ISIZE_ADDR_CH_DISABLE;
+
+	writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_addr_change_disable(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE);
+
+	cfg |= S3C_CIREAL_ISIZE_ADDR_CH_DISABLE;
+
+	writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_input_burst_cnt(struct fimc_control *ctrl, u32 cnt)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~S3C_MSCTRL_BURST_CNT_MASK;
+
+	if (cnt > 4)
+		cnt = 4;
+	else if (cnt == 0)
+		cnt = 4;
+
+	cfg |= S3C_MSCTRL_SUCCESSIVE_COUNT(cnt);
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_colorspace(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~S3C_MSCTRL_INFORMAT_RGB;
+
+	/* Color format setting */
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:	/* fall through */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV21:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+		cfg |= S3C_MSCTRL_INFORMAT_YCBCR420;
+		break;
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+	case V4L2_PIX_FMT_UYVY: 	/* fall through */
+	case V4L2_PIX_FMT_YVYU:		/* fall through */
+	case V4L2_PIX_FMT_VYUY:
+		cfg |= S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE;
+		break;
+	case V4L2_PIX_FMT_NV16:		/* fall through */
+	case V4L2_PIX_FMT_NV61:
+		cfg |= S3C_MSCTRL_INFORMAT_YCBCR422;
+		break;
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_RGB32:
+		cfg |= S3C_MSCTRL_INFORMAT_RGB;
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n",
+				__func__, pixelformat);
+		return -EINVAL;
+	}
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_yuv(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~(S3C_MSCTRL_ORDER2P_SHIFT_MASK | S3C_MSCTRL_C_INT_IN_2PLANE |
+						S3C_MSCTRL_ORDER422_YCBYCR);
+
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_YUV420:	/* fall through */
+	case V4L2_PIX_FMT_YVU420:
+		cfg |= S3C_MSCTRL_C_INT_IN_3PLANE;
+		break;
+	case V4L2_PIX_FMT_YUYV:		/* fall through */
+		cfg |= S3C_MSCTRL_ORDER422_YCBYCR;
+		break;
+	case V4L2_PIX_FMT_UYVY:
+		cfg |= S3C_MSCTRL_ORDER422_CBYCRY;
+		break;
+	case V4L2_PIX_FMT_YVYU:
+		cfg |= S3C_MSCTRL_ORDER422_YCRYCB;
+		break;
+	case V4L2_PIX_FMT_VYUY:
+		cfg |= S3C_MSCTRL_ORDER422_CRYCBY;
+		break;
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:
+	case V4L2_PIX_FMT_NV16:
+		cfg |= S3C_MSCTRL_ORDER2P_LSB_CBCR;
+		cfg |= S3C_MSCTRL_C_INT_IN_2PLANE;
+		break;
+	case V4L2_PIX_FMT_NV21:
+	case V4L2_PIX_FMT_NV61:
+		cfg |= S3C_MSCTRL_ORDER2P_LSB_CRCB;
+		cfg |= S3C_MSCTRL_C_INT_IN_2PLANE;
+		break;
+	case V4L2_PIX_FMT_RGB565:	/* fall through */
+	case V4L2_PIX_FMT_RGB32:
+		break;
+	default:
+		fimc_err("%s: Invalid pixelformt : %d\n",
+				__func__, pixelformat);
+	}
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_flip(struct fimc_control *ctrl, u32 rot, u32 flip)
+{
+	u32 cfg, val;
+
+	cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~(S3C_MSCTRL_FLIP_X_MIRROR | S3C_MSCTRL_FLIP_Y_MIRROR);
+	val = fimc_mapping_rot_flip(rot, flip);
+
+	if (val & FIMC_XFLIP)
+		cfg |= S3C_MSCTRL_FLIP_X_MIRROR;
+
+	if (val & FIMC_YFLIP)
+		cfg |= S3C_MSCTRL_FLIP_Y_MIRROR;
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_input_source(struct fimc_control *ctrl, enum fimc_input path)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~S3C_MSCTRL_INPUT_MASK;
+
+	if (path == FIMC_SRC_MSDMA)
+		cfg |= S3C_MSCTRL_INPUT_MEMORY;
+	else if (path == FIMC_SRC_CAM)
+		cfg |= S3C_MSCTRL_INPUT_EXTCAM;
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+
+}
+
+int fimc_hwset_start_input_dma(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg |= S3C_MSCTRL_ENVID;
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+int fimc_hwset_stop_input_dma(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	cfg &= ~S3C_MSCTRL_ENVID;
+
+	writel(cfg, ctrl->regs + S3C_MSCTRL);
+
+	return 0;
+}
+
+void fimc_wait_stop_processing(struct fimc_control *ctrl)
+{
+	fimc_hwget_frame_end(ctrl);
+	fimc_hwget_last_frame_end(ctrl);
+}
+
+void fimc_hwset_stop_processing(struct fimc_control *ctrl)
+{
+	fimc_wait_stop_processing(ctrl);
+
+	fimc_hwset_stop_scaler(ctrl);
+	fimc_hwset_disable_capture(ctrl);
+	fimc_hwset_stop_input_dma(ctrl);
+
+	/* We need to wait for sometime after processing is stopped.
+	 * This is required for obtaining clean buffer for DMA processing. */
+	fimc_wait_stop_processing(ctrl);
+}
+
+int fimc40_hwset_output_offset(struct fimc_control *ctrl, u32 pixelformat,
+			       struct v4l2_rect *bounds,
+			       struct v4l2_rect *crop)
+{
+	u32 cfg_y = 0, cfg_cb = 0, cfg_cr = 0;
+
+	if (!crop->left && !crop->top && (bounds->width == crop->width) &&
+		(bounds->height == crop->height))
+		return -EINVAL;
+
+	fimc_dbg("%s: left: %d, top: %d, width: %d, height: %d\n",
+		__func__, crop->left, crop->top, crop->width, crop->height);
+
+	switch (pixelformat) {
+	/* 1 plane, 32 bits per pixel */
+	case V4L2_PIX_FMT_RGB32:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left * 4);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		break;
+
+	/* 1 plane, 16 bits per pixel */
+	case V4L2_PIX_FMT_YUYV:	/* fall through */
+	case V4L2_PIX_FMT_UYVY:	/* fall through */
+	case V4L2_PIX_FMT_VYUY:	/* fall through */
+	case V4L2_PIX_FMT_YVYU:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left * 2);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		break;
+
+	/* 2 planes, 16 bits per pixel */
+	case V4L2_PIX_FMT_NV16: /* fall through */
+	case V4L2_PIX_FMT_NV61:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left / 2);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top / 2);
+		break;
+
+	/* 2 planes, 12 bits per pixel */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_NV21:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left / 4);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top / 4);
+		break;
+
+	/* 3 planes, 16 bits per pixel */
+	case V4L2_PIX_FMT_YUV422P:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left / 2);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top / 2);
+		cfg_cr |= S3C_CIOCROFF_HORIZONTAL(crop->left / 2);
+		cfg_cr |= S3C_CIOCROFF_VERTICAL(crop->top / 2);
+		break;
+
+	/* 3 planes, 12 bits per pixel */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left / 4);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top / 4);
+		cfg_cr |= S3C_CIOCROFF_HORIZONTAL(crop->left / 4);
+		cfg_cr |= S3C_CIOCROFF_VERTICAL(crop->top / 4);
+		break;
+
+	default:
+		break;
+	}
+
+	writel(cfg_y, ctrl->regs + S3C_CIOYOFF);
+	writel(cfg_cb, ctrl->regs + S3C_CIOCBOFF);
+	writel(cfg_cr, ctrl->regs + S3C_CIOCROFF);
+
+	return 0;
+}
+
+int fimc50_hwset_output_offset(struct fimc_control *ctrl, u32 pixelformat,
+			       struct v4l2_rect *bounds,
+			       struct v4l2_rect *crop)
+{
+	u32 cfg_y = 0, cfg_cb = 0, cfg_cr = 0;
+
+	fimc_dbg("%s: left: %d, top: %d, width: %d, height: %d\n",
+		__func__, crop->left, crop->top, crop->width, crop->height);
+
+	switch (pixelformat) {
+	/* 1 plane, 32 bits per pixel */
+	case V4L2_PIX_FMT_RGB32:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		break;
+
+	/* 1 plane, 16 bits per pixel */
+	case V4L2_PIX_FMT_YUYV:	/* fall through */
+	case V4L2_PIX_FMT_UYVY:	/* fall through */
+	case V4L2_PIX_FMT_VYUY:	/* fall through */
+	case V4L2_PIX_FMT_YVYU:	/* fall through */
+	case V4L2_PIX_FMT_RGB565:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		break;
+
+	/* 2 planes, 16 bits per pixel */
+	case V4L2_PIX_FMT_NV16: /* fall through */
+	case V4L2_PIX_FMT_NV61:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top);
+		break;
+
+	/* 2 planes, 12 bits per pixel */
+	case V4L2_PIX_FMT_NV12:		/* fall through */
+	case V4L2_PIX_FMT_NV12M:	/* fall through */
+	case V4L2_PIX_FMT_NV12T:	/* fall through */
+	case V4L2_PIX_FMT_NV21:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top);
+		break;
+
+	/* 3 planes, 16 bits per pixel */
+	case V4L2_PIX_FMT_YUV422P:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top);
+		cfg_cr |= S3C_CIOCROFF_HORIZONTAL(crop->left);
+		cfg_cr |= S3C_CIOCROFF_VERTICAL(crop->top);
+		break;
+
+	/* 3 planes, 12 bits per pixel */
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_YVU420:
+		cfg_y |= S3C_CIOYOFF_HORIZONTAL(crop->left);
+		cfg_y |= S3C_CIOYOFF_VERTICAL(crop->top);
+		cfg_cb |= S3C_CIOCBOFF_HORIZONTAL(crop->left);
+		cfg_cb |= S3C_CIOCBOFF_VERTICAL(crop->top);
+		cfg_cr |= S3C_CIOCROFF_HORIZONTAL(crop->left);
+		cfg_cr |= S3C_CIOCROFF_VERTICAL(crop->top);
+		break;
+
+	default:
+		break;
+	}
+
+	writel(cfg_y, ctrl->regs + S3C_CIOYOFF);
+	writel(cfg_cb, ctrl->regs + S3C_CIOCBOFF);
+	writel(cfg_cr, ctrl->regs + S3C_CIOCROFF);
+
+	return 0;
+}
+
+int fimc_hwset_output_offset(struct fimc_control *ctrl, u32 pixelformat,
+			     struct v4l2_rect *bounds,
+			     struct v4l2_rect *crop)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	if (pdata->hw_ver >= 0x50)
+		fimc50_hwset_output_offset(ctrl, pixelformat, bounds, crop);
+	else
+		fimc40_hwset_output_offset(ctrl, pixelformat, bounds, crop);
+
+	return 0;
+}
+
+int fimc40_hwset_input_offset(struct fimc_control *ctrl, u32 pixelformat,
+			      struct v4l2_rect *bounds,
+			      struct v4l2_rect *crop)
+{
+	u32 cfg_y = 0, cfg_cb = 0;
+
+	if (crop->left || crop->top ||
+		(bounds->width != crop->width) ||
+		(bounds->height != crop->height)) {
+		switch (pixelformat) {
+		case V4L2_PIX_FMT_YUYV:		/* fall through */
+		case V4L2_PIX_FMT_RGB565:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left * 2);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_RGB32:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left * 4);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_NV12:		/* fall through */
+		case V4L2_PIX_FMT_NV21:		/* fall through */
+		case V4L2_PIX_FMT_NV12T:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			cfg_cb |= S3C_CIICBOFF_HORIZONTAL(crop->left);
+			cfg_cb |= S3C_CIICBOFF_VERTICAL(crop->top / 2);
+
+			break;
+		default:
+			fimc_err("%s: Invalid pixelformt : %d\n",
+					__func__, pixelformat);
+		}
+	}
+
+	writel(cfg_y, ctrl->regs + S3C_CIIYOFF);
+	writel(cfg_cb, ctrl->regs + S3C_CIICBOFF);
+
+	return 0;
+}
+
+int fimc50_hwset_input_offset(struct fimc_control *ctrl, u32 pixelformat,
+			      struct v4l2_rect *bounds,
+			      struct v4l2_rect *crop)
+{
+	u32 cfg_y = 0, cfg_cb = 0, cfg_cr = 0;
+
+	if (crop->left || crop->top ||
+		(bounds->width != crop->width) ||
+		(bounds->height != crop->height)) {
+		switch (pixelformat) {
+		case V4L2_PIX_FMT_YUYV:		/* fall through */
+		case V4L2_PIX_FMT_UYVY:		/* fall through */
+		case V4L2_PIX_FMT_YVYU:		/* fall through */
+		case V4L2_PIX_FMT_VYUY:		/* fall through */
+		case V4L2_PIX_FMT_RGB565:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_RGB32:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_NV12: /* fall through*/
+		case V4L2_PIX_FMT_NV21: /* fall through*/
+		case V4L2_PIX_FMT_NV12T:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			cfg_cb |= S3C_CIICBOFF_HORIZONTAL(crop->left);
+			cfg_cb |= S3C_CIICBOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_NV16:		/* fall through */
+		case V4L2_PIX_FMT_NV61:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			cfg_cb |= S3C_CIICBOFF_HORIZONTAL(crop->left);
+			cfg_cb |= S3C_CIICBOFF_VERTICAL(crop->top);
+			break;
+		case V4L2_PIX_FMT_YUV420:
+		case V4L2_PIX_FMT_YVU420:
+			cfg_y |= S3C_CIIYOFF_HORIZONTAL(crop->left);
+			cfg_y |= S3C_CIIYOFF_VERTICAL(crop->top);
+			cfg_cb |= S3C_CIICBOFF_HORIZONTAL(crop->left);
+			cfg_cb |= S3C_CIICBOFF_VERTICAL(crop->top);
+			cfg_cr |= S3C_CIICROFF_HORIZONTAL(crop->left);
+			cfg_cr |= S3C_CIICROFF_VERTICAL(crop->top);
+			break;
+		default:
+			fimc_err("%s: Invalid pixelformt : %d\n",
+					__func__, pixelformat);
+		}
+	}
+
+	writel(cfg_y, ctrl->regs + S3C_CIIYOFF);
+	writel(cfg_cb, ctrl->regs + S3C_CIICBOFF);
+	writel(cfg_cr, ctrl->regs + S3C_CIICROFF);
+
+	return 0;
+}
+
+int fimc_hwset_input_offset(struct fimc_control *ctrl, u32 pixelformat,
+			    struct v4l2_rect *bounds,
+			    struct v4l2_rect *crop)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+
+	if (pdata->hw_ver >= 0x50)
+		fimc50_hwset_input_offset(ctrl, pixelformat, bounds, crop);
+	else
+		fimc40_hwset_input_offset(ctrl, pixelformat, bounds, crop);
+
+	return 0;
+}
+
+int fimc_hwset_org_input_size(struct fimc_control *ctrl, u32 width, u32 height)
+{
+	u32 cfg = 0;
+
+	cfg |= S3C_ORGISIZE_HORIZONTAL(width);
+	cfg |= S3C_ORGISIZE_VERTICAL(height);
+
+	writel(cfg, ctrl->regs + S3C_ORGISIZE);
+
+	return 0;
+}
+
+int fimc_hwset_org_output_size(struct fimc_control *ctrl, u32 width, u32 height)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg = 0;
+
+	cfg |= S3C_ORGOSIZE_HORIZONTAL(width);
+	cfg |= S3C_ORGOSIZE_VERTICAL(height);
+
+	writel(cfg, ctrl->regs + S3C_ORGOSIZE);
+
+	if (pdata->hw_ver != 0x40) {
+		cfg = readl(ctrl->regs + S3C_CIGCTRL);
+		cfg &= ~S3C_CIGCTRL_CSC_MASK;
+
+		if (width >= FIMC_HD_WIDTH)
+			cfg |= S3C_CIGCTRL_CSC_ITU709;
+		else
+			cfg |= S3C_CIGCTRL_CSC_ITU601;
+
+		writel(cfg, ctrl->regs + S3C_CIGCTRL);
+	}
+
+	return 0;
+}
+
+int fimc_hwset_ext_output_size(struct fimc_control *ctrl, u32 width, u32 height)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIEXTEN);
+
+	cfg &= ~S3C_CIEXTEN_TARGETH_EXT_MASK;
+	cfg &= ~S3C_CIEXTEN_TARGETV_EXT_MASK;
+	cfg |= S3C_CIEXTEN_TARGETH_EXT(width);
+	cfg |= S3C_CIEXTEN_TARGETV_EXT(height);
+
+	writel(cfg, ctrl->regs + S3C_CIEXTEN);
+
+	return 0;
+}
+
+int fimc_hwset_input_addr_style(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIDMAPARAM);
+	cfg &= ~S3C_CIDMAPARAM_R_MODE_MASK;
+
+	if (pixelformat == V4L2_PIX_FMT_NV12T)
+		cfg |= S3C_CIDMAPARAM_R_MODE_64X32;
+	else
+		cfg |= S3C_CIDMAPARAM_R_MODE_LINEAR;
+
+	writel(cfg, ctrl->regs + S3C_CIDMAPARAM);
+
+	return 0;
+}
+
+int fimc_hwset_output_addr_style(struct fimc_control *ctrl, u32 pixelformat)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIDMAPARAM);
+	cfg &= ~S3C_CIDMAPARAM_W_MODE_MASK;
+
+	if (pixelformat == V4L2_PIX_FMT_NV12T)
+		cfg |= S3C_CIDMAPARAM_W_MODE_64X32;
+	else
+		cfg |= S3C_CIDMAPARAM_W_MODE_LINEAR;
+
+	writel(cfg, ctrl->regs + S3C_CIDMAPARAM);
+
+	return 0;
+}
+
+int fimc_hw_wait_winoff(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg = readl(ctrl->regs + S3C_CISTATUS);
+	u32 status = S3C_CISTATUS_GET_LCD_STATUS(cfg);
+	int i = FIMC_FIFOOFF_CNT;
+
+	if (pdata->hw_ver == 0x40)
+		return 0;
+
+	while (status && i--) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+		status = S3C_CISTATUS_GET_LCD_STATUS(cfg);
+	}
+
+	if (i < 1) {
+		fimc_err("Fail : %s\n", __func__);
+		return -EBUSY;
+	} else
+		return 0;
+}
+
+int fimc_hw_wait_stop_input_dma(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg = readl(ctrl->regs + S3C_MSCTRL);
+	u32 status = S3C_MSCTRL_GET_INDMA_STATUS(cfg);
+	int i = FIMC_FIFOOFF_CNT, j = FIMC_FIFOOFF_CNT;
+
+	if (pdata->hw_ver == 0x40)
+		return 0;
+
+	while (status && i--) {
+		cfg = readl(ctrl->regs + S3C_MSCTRL);
+		status = S3C_MSCTRL_GET_INDMA_STATUS(cfg);
+	}
+
+	cfg = readl(ctrl->regs + S3C_CISTATUS);
+	status = S3C_CISTATUS_GET_ENVID_STATUS(cfg);
+	while (status && j--) {
+		cfg = readl(ctrl->regs + S3C_CISTATUS);
+		status = S3C_CISTATUS_GET_ENVID_STATUS(cfg);
+	}
+
+	if ((i < 1) || (j < 1)) {
+		fimc_err("Fail : %s\n", __func__);
+		return -EBUSY;
+	} else {
+		return 0;
+	}
+}
+
+int fimc_hwset_input_lineskip(struct fimc_control *ctrl)
+{
+	struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
+	u32 cfg = 0;
+
+	if (pdata->hw_ver == 0x40)
+		return 0;
+
+	cfg = S3C_CIILINESKIP(ctrl->sc.skipline);
+
+	writel(cfg, ctrl->regs + S3C_CIILINESKIP_Y);
+	writel(cfg, ctrl->regs + S3C_CIILINESKIP_CB);
+	writel(cfg, ctrl->regs + S3C_CIILINESKIP_CR);
+
+	return 0;
+}
+
+int fimc_hw_reset_camera(struct fimc_control *ctrl)
+{
+	u32 cfg = 0;
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~S3C_CIGCTRL_CAMRST_A;
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg |= S3C_CIGCTRL_CAMRST_A;
+
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+
+	return 0;
+}
+
+/* Above FIMC v5.1 */
+int fimc_hwset_output_buf_sequence(struct fimc_control *ctrl, u32 shift, u32 enable)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIFCNTSEQ);
+	u32 mask = 0x00000001 << shift;
+
+	cfg &= (~mask);
+	cfg |= (enable << shift);
+	writel(cfg, ctrl->regs + S3C_CIFCNTSEQ);
+	return 0;
+}
+
+int fimc_hwget_output_buf_sequence(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIFCNTSEQ);
+	return cfg;
+}
+/* Above FIMC v5.1 */
+int fimc_hw_reset_output_buf_sequence(struct fimc_control *ctrl)
+{
+	writel(0x0, ctrl->regs + S3C_CIFCNTSEQ);
+	return 0;
+}
+
+void fimc_hwset_output_buf_sequence_all(struct fimc_control *ctrl, u32 framecnt_seq)
+{
+	writel(framecnt_seq, ctrl->regs + S3C_CIFCNTSEQ);
+}
+
+/* Above FIMC v5.1 */
+int fimc_hwget_before_frame_count(struct fimc_control *ctrl)
+{
+	u32 before = readl(ctrl->regs + S3C_CISTATUS2);
+	before &= 0x00001f80; /* [12:7] FrameCnt_before */
+	return before >> 7;
+}
+
+/* Above FIMC v5.1 */
+int fimc_hwget_present_frame_count(struct fimc_control *ctrl)
+{
+	u32 present = readl(ctrl->regs + S3C_CISTATUS2);
+	present &= 0x0000003f; /* [5:0] FrameCnt_present */
+	return present >> 0;
+}
+
+int fimc_hwget_check_framecount_sequence(struct fimc_control *ctrl, u32 frame)
+{
+	u32 framecnt_seq = readl(ctrl->regs + S3C_CIFCNTSEQ);
+	frame -= 1;
+	frame = 0x1 << frame;
+
+	if (framecnt_seq & frame)
+		return FIMC_FRAMECNT_SEQ_ENABLE;
+	else
+		return FIMC_FRAMECNT_SEQ_DISABLE;
+}
+
+int fimc_hwset_sysreg_camblk_fimd0_wb(struct fimc_control *ctrl)
+{
+	u32 camblk_cfg = readl(SYSREG_CAMERA_BLK);
+
+	if (soc_is_exynos4210()) {
+		camblk_cfg &= (~(0x3 << 14));
+		camblk_cfg |= ctrl->id << 14;
+	} else {
+		camblk_cfg &= (~(0x3 << 23));
+		camblk_cfg |= ctrl->id << 23;
+	}
+
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+
+	return 0;
+}
+
+int fimc_hwset_sysreg_camblk_fimd1_wb(struct fimc_control *ctrl)
+{
+	u32 camblk_cfg = readl(SYSREG_CAMERA_BLK);
+
+	camblk_cfg &= (~(0x3 << 10));
+	camblk_cfg |= ctrl->id << 10;
+
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+
+	return 0;
+}
+
+int fimc_hwset_sysreg_camblk_isp_wb(struct fimc_control *ctrl)
+{
+	u32 camblk_cfg = readl(SYSREG_CAMERA_BLK);
+	u32 ispblk_cfg = readl(SYSREG_ISP_BLK);
+	camblk_cfg = camblk_cfg & (~(0x7 << 20));
+	if (ctrl->id == 0)
+		camblk_cfg = camblk_cfg | (0x1 << 20);
+	else if (ctrl->id == 1)
+		camblk_cfg = camblk_cfg | (0x2 << 20);
+	else if (ctrl->id == 2)
+		camblk_cfg = camblk_cfg | (0x4 << 20);
+	else if (ctrl->id == 3)
+		camblk_cfg = camblk_cfg | (0x7 << 20); /* FIXME*/
+	else
+		fimc_err("%s: not supported id : %d\n", __func__, ctrl->id);
+
+	camblk_cfg = camblk_cfg & (~(0x1 << 15));
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+	udelay(1000);
+	camblk_cfg = camblk_cfg | (0x1 << 15);
+	writel(camblk_cfg, SYSREG_CAMERA_BLK);
+
+	ispblk_cfg = ispblk_cfg & (~(0x1 << 7));
+	writel(ispblk_cfg, SYSREG_ISP_BLK);
+	udelay(1000);
+	ispblk_cfg = ispblk_cfg | (0x1 << 7);
+	writel(ispblk_cfg, SYSREG_ISP_BLK);
+
+	return 0;
+}
+
+void fimc_hwset_enable_frame_end_irq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg |= S3C_CIGCTRL_IRQ_END_DISABLE;
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+}
+
+void fimc_hwset_disable_frame_end_irq(struct fimc_control *ctrl)
+{
+	u32 cfg = readl(ctrl->regs + S3C_CIGCTRL);
+	cfg &= ~S3C_CIGCTRL_IRQ_END_DISABLE;
+	writel(cfg, ctrl->regs + S3C_CIGCTRL);
+}
+
+void fimc_reset_status_reg(struct fimc_control *ctrl)
+{
+	writel(0x0, ctrl->regs + S3C_CISTATUS);
+}
+
+#if defined (CONFIG_ARCH_EXYNOS4)
+void fimc_sfr_dump(struct fimc_control *ctrl)
+{
+	int i;
+	u32 cfg[] = {0x0, 0x4, 0x8, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2c, 0x30,
+				0x34, 0x38, 0x3c, 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c,
+				0x60, 0x64, 0x68, 0xc0, 0xc4, 0xc8, 0xd0, 0xd4, 0xd8, 0xdc, 0xec,
+				0xf0, 0xf4, 0xf8, 0xfc, 0x144, 0x148, 0x14c, 0x168, 0x16c, 0x170,
+				0x174, 0x178, 0x180, 0x184,0x188, 0x18c, 0x194, 0x19c, 0x1a0, 0x1fc,};
+
+	for (i = 0; i < sizeof(cfg) / 4; i++) {
+		printk("idx = 0x%x \tval 0x%08x \n", cfg[i], readl(ctrl->regs + cfg[i]));
+	}
+
+}
+#endif
diff --git a/drivers/media/video/samsung/fimc/fimc_v4l2.c b/drivers/media/video/samsung/fimc/fimc_v4l2.c
new file mode 100644
index 0000000..510e2f1
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/fimc_v4l2.c
@@ -0,0 +1,327 @@
+/* linux/drivers/media/video/samsung/fimc/fimc_v4l2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * V4L2 interface support file for Samsung Camera Interface (FIMC) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <linux/videodev2_exynos_camera.h>
+#include <media/v4l2-ioctl.h>
+#include <plat/fimc.h>
+
+#include "fimc.h"
+
+static int fimc_querycap(struct file *filp, void *fh,
+			 struct v4l2_capability *cap)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+
+	fimc_info1("%s: called\n", __func__);
+
+	strcpy(cap->driver, "SEC FIMC Driver");
+	strlcpy(cap->card, ctrl->vd->name, sizeof(cap->card));
+	sprintf(cap->bus_info, "FIMC AHB-bus");
+
+	cap->version = 0;
+	cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
+				V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_STREAMING);
+
+	return 0;
+}
+
+static int fimc_reqbufs(struct file *filp, void *fh,
+			struct v4l2_requestbuffers *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_reqbufs_capture(ctrl, b);
+	} else if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_reqbufs_output(fh, b);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_querybuf(struct file *filp, void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_querybuf_capture(ctrl, b);
+	} else if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_querybuf_output(fh, b);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_g_ctrl(struct file *filp, void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (ctrl->cap != NULL) {
+		ret = fimc_g_ctrl_capture(ctrl, c);
+	} else if (ctrl->out != NULL) {
+		ret = fimc_g_ctrl_output(fh, c);
+	} else {
+		fimc_err("%s: Invalid case\n", __func__);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_s_ctrl(struct file *filp, void *fh, struct v4l2_control *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (ctrl->cap != NULL) {
+		ret = fimc_s_ctrl_capture(ctrl, c);
+	} else if (ctrl->out != NULL) {
+		ret = fimc_s_ctrl_output(filp, fh, c);
+	} else {
+		fimc_err("%s: Invalid case\n", __func__);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_g_ext_ctrls(struct file *filp, void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (ctrl->cap != NULL) {
+		ret = fimc_g_ext_ctrls_capture(fh, c);
+	} else {
+		fimc_err("%s: Invalid case\n", __func__);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+static int fimc_s_ext_ctrls(struct file *filp, void *fh, struct v4l2_ext_controls *c)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (ctrl->cap != NULL) {
+		ret = fimc_s_ext_ctrls_capture(fh, c);
+	} else if (ctrl->out != NULL) {
+		/* How about "ret = fimc_s_ext_ctrls_output(fh, c);"? */
+	} else {
+		fimc_err("%s: Invalid case\n", __func__);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_cropcap(struct file *filp, void *fh, struct v4l2_cropcap *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (a->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_cropcap_capture(ctrl, a);
+	} else if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_cropcap_output(fh, a);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_g_crop(struct file *filp, void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (a->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_g_crop_capture(ctrl, a);
+	} else if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_g_crop_output(fh, a);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_s_crop(struct file *filp, void *fh, struct v4l2_crop *a)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (a->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_s_crop_capture(ctrl, a);
+	} else if (a->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_s_crop_output(fh, a);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_streamon(struct file *filp, void *fh, enum v4l2_buf_type i)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (i == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_streamon_capture(ctrl);
+	} else if (i == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_streamon_output(fh);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_streamoff(struct file *filp, void *fh, enum v4l2_buf_type i)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (i == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_streamoff_capture(ctrl);
+	} else if (i == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_streamoff_output(fh);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_qbuf(struct file *filp, void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_qbuf_capture(ctrl, b);
+	} else if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_qbuf_output(fh, b);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_dqbuf(struct file *filp, void *fh, struct v4l2_buffer *b)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int ret = -1;
+
+	if (b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		ret = fimc_dqbuf_capture(ctrl, b);
+	} else if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ret = fimc_dqbuf_output(fh, b);
+	} else {
+		fimc_err("V4L2_BUF_TYPE_VIDEO_CAPTURE and "
+			"V4L2_BUF_TYPE_VIDEO_OUTPUT are only supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fimc_log_status(struct file *filp, void *fh)
+{
+	struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
+	int framecnt_seq;
+
+	printk(KERN_INFO "fimc%d ctrl->status is %d\n", ctrl->id, ctrl->status);
+
+#if defined (CONFIG_ARCH_EXYNOS4)
+	framecnt_seq = fimc_hwget_output_buf_sequence(ctrl);
+	printk(KERN_INFO "fimc(%d) framecnt_seq is %d\n", ctrl->id, framecnt_seq);
+	printk(KERN_INFO "fimc(%d) availble_buf is %d\n", ctrl->id, fimc_hwget_number_of_bits(framecnt_seq));
+
+	fimc_sfr_dump(ctrl);
+#endif
+	return 0;
+}
+
+const struct v4l2_ioctl_ops fimc_v4l2_ops = {
+	.vidioc_querycap		= fimc_querycap,
+	.vidioc_reqbufs			= fimc_reqbufs,
+	.vidioc_querybuf		= fimc_querybuf,
+	.vidioc_g_ctrl			= fimc_g_ctrl,
+	.vidioc_g_ext_ctrls		= fimc_g_ext_ctrls,
+	.vidioc_s_ctrl			= fimc_s_ctrl,
+	.vidioc_s_ext_ctrls		= fimc_s_ext_ctrls,
+	.vidioc_cropcap			= fimc_cropcap,
+	.vidioc_g_crop			= fimc_g_crop,
+	.vidioc_s_crop			= fimc_s_crop,
+	.vidioc_streamon		= fimc_streamon,
+	.vidioc_streamoff		= fimc_streamoff,
+	.vidioc_qbuf			= fimc_qbuf,
+	.vidioc_dqbuf			= fimc_dqbuf,
+	.vidioc_enum_fmt_vid_cap	= fimc_enum_fmt_vid_capture,
+	.vidioc_g_fmt_vid_cap		= fimc_g_fmt_vid_capture,
+	.vidioc_s_fmt_vid_cap		= fimc_s_fmt_vid_capture,
+	.vidioc_s_fmt_type_private	= fimc_s_fmt_vid_private,
+	.vidioc_try_fmt_vid_cap		= fimc_try_fmt_vid_capture,
+	.vidioc_enum_input		= fimc_enum_input,
+	.vidioc_g_input			= fimc_g_input,
+	.vidioc_s_input			= fimc_s_input,
+	.vidioc_g_parm			= fimc_g_parm,
+	.vidioc_s_parm			= fimc_s_parm,
+	.vidioc_queryctrl		= fimc_queryctrl,
+	.vidioc_querymenu		= fimc_querymenu,
+	.vidioc_g_fmt_vid_out		= fimc_g_fmt_vid_out,
+	.vidioc_s_fmt_vid_out		= fimc_s_fmt_vid_out,
+	.vidioc_try_fmt_vid_out		= fimc_try_fmt_vid_out,
+	.vidioc_g_fbuf			= fimc_g_fbuf,
+	.vidioc_s_fbuf			= fimc_s_fbuf,
+	.vidioc_try_fmt_vid_overlay	= fimc_try_fmt_overlay,
+	.vidioc_g_fmt_vid_overlay	= fimc_g_fmt_vid_overlay,
+	.vidioc_s_fmt_vid_overlay	= fimc_s_fmt_vid_overlay,
+	.vidioc_enum_framesizes		= fimc_enum_framesizes,
+	.vidioc_enum_frameintervals	= fimc_enum_frameintervals,
+	.vidioc_log_status		= fimc_log_status,
+};
diff --git a/drivers/media/video/samsung/fimc/ipc.c b/drivers/media/video/samsung/fimc/ipc.c
new file mode 100644
index 0000000..4bcbd5d
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/ipc.c
@@ -0,0 +1,472 @@
+/* linux/drivers/media/video/samsung/fimc/ipc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver file for Samsung IPC driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/memory.h>
+#include <plat/clock.h>
+#include <plat/regs-ipc.h>
+
+#include "fimc-ipc.h"
+#include "ipc_table.h"
+
+struct ipc_control *ipc;
+
+void shadow_update(void)
+{
+	writel(S3C_IPC_SHADOW_UPDATE_ENABLE,
+					ipc->regs + S3C_IPC_SHADOW_UPDATE);
+}
+
+void ipc_enable_postprocessing(u32 onoff)
+{
+	u32 cfg = readl(ipc->regs + S3C_IPC_BYPASS);
+
+	if (!onoff)
+		cfg |= S3C_IPC_PP_BYPASS_DISABLE;
+	else
+		cfg &= S3C_IPC_PP_BYPASS_ENABLE;
+
+	writel(cfg, ipc->regs + S3C_IPC_BYPASS);
+
+	shadow_update();
+}
+
+void ipc_enable(u32 onoff)
+{
+	u32 cfg = readl(ipc->regs + S3C_IPC_ENABLE);
+
+	if (!onoff)
+		cfg &= S3C_IPC_OFF;
+	else
+		cfg |= S3C_IPC_ON;
+
+	writel(cfg, ipc->regs + S3C_IPC_ENABLE);
+}
+
+void ipc_reset(void)
+{
+	u32 cfg;
+
+	do {
+		cfg = readl(ipc->regs + S3C_IPC_SRESET);
+	} while ((cfg & S3C_IPC_SRESET_MASK));
+
+	writel(S3C_IPC_SRESET_ENABLE, ipc->regs + S3C_IPC_SRESET);
+}
+
+void ipc_start(void)
+{
+	ipc_enable_postprocessing(ON);
+	ipc_enable(ON);
+}
+
+void ipc_stop(void)
+{
+	ipc_enable_postprocessing(OFF);
+	ipc_enable(OFF);
+	ipc_reset();
+
+#if 1
+	/* Jonghun Han
+	*  After clk_disalbe, we cannot set register although clk is enable.
+	*  Must be tested by System Application part.
+	*/
+	clk_disable(ipc->clk);
+#endif
+}
+
+void ipc_field_id_control(enum ipc_field_id id)
+{
+	writel(id, ipc->regs + S3C_IPC_FIELD_ID);
+	shadow_update();
+}
+
+void ipc_field_id_mode(enum ipc_field_id_sel sel,
+					enum ipc_field_id_togl toggle)
+{
+	u32 cfg;
+
+	cfg = readl(ipc->regs + S3C_IPC_MODE);
+	cfg |= S3C_IPC_FIELD_ID_SELECTION(sel);
+	writel(cfg, ipc->regs + S3C_IPC_MODE);
+
+	cfg = readl(ipc->regs + S3C_IPC_MODE);
+	cfg |= S3C_IPC_FIELD_ID_AUTO_TOGGLING(toggle);
+	writel(cfg, ipc->regs + S3C_IPC_MODE);
+
+	shadow_update();
+}
+
+void ipc_2d_enable(enum ipc_enoff onoff)
+{
+	u32 cfg;
+
+	cfg = readl(ipc->regs + S3C_IPC_MODE);
+	cfg &= ~S3C_IPC_2D_MASK;
+	cfg |= S3C_IPC_2D_CTRL(onoff);
+	writel(cfg, ipc->regs + S3C_IPC_MODE);
+
+	shadow_update();
+}
+
+void ipc_set_mode(struct ipc_controlvariable con_var)
+{
+	u32 cfg = 0;
+
+	/* Enalbed : 2D IPC , Disabled : Horizon Double Scailing */
+	ipc_field_id_control(IPC_BOTTOM_FIELD);
+	ipc_field_id_mode(CAM_FIELD_SIG, AUTO);
+	ipc_2d_enable(con_var.modeval);
+
+	if (con_var.modeval == IPC_2D)
+		cfg = IPC_2D_ENABLE;
+	else
+		cfg = IPC_HOR_SCALING_ENABLE;
+	writel(cfg, ipc->regs + S3C_IPC_H_RATIO);
+
+	cfg = IPC_2D_ENABLE;
+	writel(cfg, ipc->regs + S3C_IPC_V_RATIO);
+
+	shadow_update();
+}
+
+void ipc_set_imgsize(struct ipc_source src, struct ipc_destination dst)
+{
+	writel(S3C_IPC_SRC_WIDTH_SET(src.srchsz),
+						ipc->regs + S3C_IPC_SRC_WIDTH);
+	writel(S3C_IPC_SRC_HEIGHT_SET(src.srcvsz),
+						ipc->regs + S3C_IPC_SRC_HEIGHT);
+
+	writel(S3C_IPC_DST_WIDTH_SET(dst.dsthsz),
+						ipc->regs + S3C_IPC_DST_WIDTH);
+	writel(S3C_IPC_DST_HEIGHT_SET(dst.dstvsz),
+						ipc->regs + S3C_IPC_DST_HEIGHT);
+
+	shadow_update();
+}
+
+void ipc_set_enhance_param(void)
+{
+	u32 i;
+
+	for (i = 0; i < 8; i++) {
+		ipc->enhance_var.brightness[i] = 0x0;
+		ipc->enhance_var.contrast[i] = 0x80;
+	}
+
+	ipc->enhance_var.saturation = 0x80;
+	ipc->enhance_var.sharpness = NO_EFFECT;
+	ipc->enhance_var.thhnoise = 0x5;
+	ipc->enhance_var.brightoffset = 0x0;
+}
+
+void ipc_set_contrast(u32 *contrast)
+{
+	u32 i, line_eq[8];
+
+	for (i = 0; i < 8; i++) {
+		line_eq[i] = readl(ipc->regs + (S3C_IPC_PP_LINE_EQ0 + 4 * i));
+		line_eq[i] &= ~S3C_IPC_PP_LINE_CONTRAST_MASK;
+		line_eq[i] |= S3C_IPC_PP_LINE_CONTRAST(contrast[i]);
+		writel(line_eq[i], ipc->regs + (S3C_IPC_PP_LINE_EQ0 + 4 * i));
+	}
+
+	shadow_update();
+}
+
+void ipc_set_brightness(u32 *brightness)
+{
+	u32 i, line_eq[8];
+
+	for (i = 0; i < 8; i++) {
+		line_eq[i] = readl(ipc->regs + (S3C_IPC_PP_LINE_EQ0 + 4 * i));
+		line_eq[i] &= ~S3C_IPC_PP_LINE_BRIGTHNESS_MASK;
+		line_eq[i] |= S3C_IPC_PP_LINE_BRIGHT(brightness[i]);
+		writel(line_eq[i], ipc->regs + (S3C_IPC_PP_LINE_EQ0 + 4 * i));
+	}
+
+	shadow_update();
+}
+
+void ipc_set_bright_offset(u32 offset)
+{
+	writel(S3C_IPC_PP_BRIGHT_OFFSET_SET(offset),
+					ipc->regs + S3C_IPC_PP_BRIGHT_OFFSET);
+	shadow_update();
+}
+
+void ipc_set_saturation(u32 saturation)
+{
+	writel(S3C_IPC_PP_SATURATION_SET(saturation),
+					ipc->regs + S3C_IPC_PP_SATURATION);
+	shadow_update();
+}
+
+void ipc_set_sharpness(enum ipc_sharpness sharpness, u32 threshold)
+{
+	u32 sharpval;
+
+	switch (sharpness) {
+	case NO_EFFECT:
+		sharpval = 0x0;
+		break;
+	case MIN_EDGE:
+		sharpval = 0x1;
+		break;
+	case MODERATE_EDGE:
+		sharpval = 0x2;
+		break;
+	default:
+		sharpval = 0x3;
+		break;
+	}
+
+	writel(S3C_IPC_PP_TH_HNOISE_SET(threshold) | sharpval,
+					ipc->regs + S3C_IPC_PP_SHARPNESS);
+
+	shadow_update();
+}
+
+void ipc_set_polyphase_filter(u32 filter_reg,
+					const s8 *filter_coef, u16 tap)
+{
+	u32 base;
+	u32 i, j;
+	u16 tmp_tap;
+	u8 *coef;
+
+	base = (u32)ipc->regs + filter_reg;
+	coef = (u8 *)filter_coef;
+
+	for (i = 0; i < tap; i++) {
+		tmp_tap = tap - i - 1;
+
+		for (j = 0; j < 4; j++) {
+			writel(((coef[4 * j * tap + tmp_tap] << 24)
+				| (coef[(4 * j + 1) * tap + tmp_tap] << 16)
+				| (coef[(4 * j + 2) * tap + tmp_tap] << 8)
+				| (coef[(4 * j + 3) * tap + tmp_tap])), base);
+			base += 4;
+		}
+	}
+}
+
+void ipc_set_polyphase_filterset(enum ipc_filter_h_pp h_filter,
+						enum ipc_filter_v_pp v_filter)
+{
+	ipc_set_polyphase_filter(S3C_IPC_POLY8_Y0_LL,
+				ipc_8tap_coef_y_h + h_filter * 16 * 8, 8);
+	ipc_set_polyphase_filter(S3C_IPC_POLY4_C0_LL,
+				ipc_4tap_coef_c_h + h_filter * 16 * 4, 4);
+	ipc_set_polyphase_filter(S3C_IPC_POLY4_Y0_LL,
+				ipc_4tap_coef_y_v + v_filter * 16 * 4, 4);
+}
+
+/* For the real interlace mode,
+ *	the vertical ratio should be used after divided by 2.
+ * Because in the interlace mode,
+ *	all the IPC output is used for FIMD display
+ * and it should be the same as one field of the progressive mode.
+ * Therefore the same filter coefficients should be used for
+ *						the same final output video.
+ * When half of the interlace V_RATIO is same as the progressive V_RATIO,
+ *	the final output video scale is same. (20051104,ishan)
+*/
+void ipc_set_filter(void)
+{
+	enum ipc_filter_h_pp h_filter;
+	enum ipc_filter_v_pp v_filter;
+	u32 h_ratio, v_ratio;
+
+	h_ratio = readl(ipc->regs + S3C_IPC_H_RATIO);
+	v_ratio = readl(ipc->regs + S3C_IPC_V_RATIO);
+
+	/* Horizontal Y 8 tap , Horizontal C 4 tap */
+	if (h_ratio <= (0x1 << 16))		/* 720 -> 720 or zoom in */
+		h_filter = IPC_PP_H_NORMAL;
+	else if (h_ratio <= (0x9 << 13))	/* 720 -> 640 */
+		h_filter = IPC_PP_H_8_9 ;
+	else if (h_ratio <= (0x1 << 17))		/* 2 -> 1 */
+		h_filter = IPC_PP_H_1_2;
+	else if (h_ratio <= (0x3 << 16))		/* 2 -> 1 */
+		h_filter = IPC_PP_H_1_3;
+	else					/* 4 -> 1 */
+		h_filter = IPC_PP_H_1_4;
+
+	/* Vertical Y 4 tap */
+	if (v_ratio <= (0x1 << 16))		/* 720 -> 720 or zoom in */
+		v_filter = IPC_PP_V_NORMAL;
+	else if (v_ratio <= (0x3 << 15))	/* 6 -> 5 */
+		v_filter = IPC_PP_V_5_6;
+	else if (v_ratio <= (0x1 << 17))	/* 2 -> 1 */
+		v_filter = IPC_PP_V_1_2;
+	else if (v_ratio <= (0x3 << 16))	/* 3 -> 1 */
+		v_filter = IPC_PP_V_1_3;
+	else					/* 4 -> 1 */
+		v_filter = IPC_PP_V_1_4;
+
+	ipc_set_polyphase_filterset(h_filter, v_filter);
+}
+
+void ipc_set_pixel_rate(void)
+{
+	writel(S3C_IPC_PEL_RATE_SET, ipc->regs + S3C_IPC_PEL_RATE_CTRL);
+	shadow_update();
+}
+
+int ipc_init(u32 src_width, u32 src_height, enum ipc_2d ipc2d)
+{
+	if (src_width > IN_SC_MAX_WIDTH || src_height > IN_SC_MAX_HEIGHT) {
+		ipc_err("IPC input size error\n");
+		ipc_stop();
+		return -EINVAL;
+	}
+
+	ipc->src.imghsz = src_width;
+	ipc->src.imgvsz = src_height;
+	ipc->src.srchsz = src_width;
+	ipc->src.srcvsz = src_height;
+
+	ipc->dst.scanmode = PROGRESSIVE;
+
+	if (ipc2d == IPC_2D) {
+		ipc->dst.dsthsz = src_width;
+		ipc->dst.dstvsz = src_height * 2;
+	} else {
+		ipc->dst.dsthsz = src_width * 2;
+		ipc->dst.dstvsz = src_height;
+	}
+
+	ipc->control_var.modeval = ipc2d;
+
+	clk_enable(ipc->clk);
+
+	ipc_reset();
+	ipc_enable(OFF);
+	ipc_enable_postprocessing(OFF);
+
+	ipc_set_mode(ipc->control_var);
+	ipc_set_imgsize(ipc->src, ipc->dst);
+
+	ipc_set_enhance_param();
+	ipc_set_contrast(ipc->enhance_var.contrast);
+	ipc_set_brightness(ipc->enhance_var.brightness);
+	ipc_set_bright_offset(ipc->enhance_var.brightoffset);
+	ipc_set_saturation(ipc->enhance_var.saturation);
+	ipc_set_sharpness(ipc->enhance_var.sharpness,
+			ipc->enhance_var.thhnoise);
+
+	ipc_set_filter();
+	ipc_set_pixel_rate();
+
+	return 0;
+}
+
+static int ipc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	ipc = (struct ipc_control *) \
+			kmalloc(sizeof(struct ipc_control), GFP_KERNEL);
+	if (!ipc) {
+		ipc_err("no memory for configuration\n");
+		return -ENOMEM;
+	}
+	strcpy(ipc->name, IPC_NAME);
+
+	ipc->clk = clk_get(&pdev->dev, IPC_CLK_NAME);
+	if (IS_ERR(ipc->clk)) {
+		ipc_err("failed to get ipc clock source\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ipc_err("failed to get io memory region\n");
+		return -EINVAL;
+	}
+
+	res = request_mem_region(res->start, res->end - res->start + 1,
+								pdev->name);
+	if (!res) {
+		ipc_err("failed to request io memory region\n");
+		return -EINVAL;
+	}
+
+	/* ioremap for register block */
+	ipc->regs = ioremap(res->start, res->end - res->start + 1);
+	if (!ipc->regs) {
+		ipc_err("failed to remap io region\n");
+		return -EINVAL;
+	}
+
+	printk(KERN_INFO "IPC probe success\n");
+
+	return 0;
+}
+
+static int ipc_remove(struct platform_device *pdev)
+{
+	ipc_stop();
+	kfree(ipc);
+
+	return 0;
+}
+
+int ipc_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+int ipc_resume(struct platform_device *dev)
+{
+	return 0;
+}
+
+static struct platform_driver ipc_driver = {
+	.probe		= ipc_probe,
+	.remove		= ipc_remove,
+	.suspend	= ipc_suspend,
+	.resume		= ipc_resume,
+	.driver		= {
+		.name	= "s3c-ipc",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int ipc_register(void)
+{
+	platform_driver_register(&ipc_driver);
+
+	return 0;
+}
+
+static void ipc_unregister(void)
+{
+	platform_driver_unregister(&ipc_driver);
+}
+
+module_init(ipc_register);
+module_exit(ipc_unregister);
+
+MODULE_AUTHOR("Jonghun, Han <jonghun.han@samsung.com>");
+MODULE_AUTHOR("Youngmok, Song <ym.song@samsung.com>");
+MODULE_DESCRIPTION("IPC support for FIMC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimc/ipc_table.h b/drivers/media/video/samsung/fimc/ipc_table.h
new file mode 100644
index 0000000..d0e8969
--- /dev/null
+++ b/drivers/media/video/samsung/fimc/ipc_table.h
@@ -0,0 +1,314 @@
+/* linux/drivers/media/video/samsung/fimc/ipc_table.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file for Samsung IPC driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __IPC_TABLE_H
+#define __IPC_TABLE_H __FILE__
+
+/*  Horizontal Y 8tap  */
+const s8 ipc_8tap_coef_y_h[] = {
+	/* IPC_PP_H_NORMAL */
+	0,	0,	 0,	 0,	127,	0,	0,	0,
+	0,	1,	-2,	 8,	126,	-6,	2,	-1,
+	0,	1,	-5,	16,	125,	-12,	4,	-1,
+	0,	2,	-8,	25,	121,	-16,	5,	-1,
+	-1,	3,	-10,	35,	114,	-18,	6,	-1,
+	-1,	4,	-13,	46,	107,	-20,	6,	-1,
+	-1,	5,	-16,	57,	99,	-21,	6,	-1,
+	-1,	5,	-18,	68,	89,	-20,	6,	-1,
+	-1,	6,	-20,	79,	79,	-20,	6,	-1,
+	-1,	6,	-20,	89,	68,	-18,	5,	-1,
+	-1,	6,	-21,	99,	57,	-16,	5,	-1,
+	-1,	6,	-20,	107,	46,	-13,	4,	-1,
+	-1,	6,	-18,	114,	35,	-10,	3,	-1,
+	-1,	5,	-16,	121,	25,	-8,	2,	0,
+	-1,	4,	-12,	125,	16,	-5,	1,	0,
+	-1,	2,	-6,	126,	8,	-2,	1,	0,
+
+	/* IPC_PP_H_8_9 */
+	0,	3,	-7,	12,	112,	12,	-7,	3,
+	-1,	3,	-9,	19,	113,	6,	-5,	2,
+	-1,	3,	-11,	27,	111,	0,	-3,	2,
+	-1,	4,	-13,	35,	108,	-5,	-1,	1,
+	-1,	4,	-14,	43,	104,	-9,	0,	1,
+	-1,	5,	-16,	52,	99,	-12,	1,	0,
+	-1,	5,	-17,	61,	92,	-14,	2,	0,
+	0,	4,	-17,	69,	85,	-16,	3,	0,
+	0,	4,	-17,	77,	77,	-17,	4,	0,
+	0,	3,	-16,	85,	69,	-17,	4,	0,
+	0,	2,	-14,	92,	61,	-17,	5,	-1,
+	0,	1,	-12,	99,	52,	-16,	5,	-1,
+	1,	0,	-9,	104,	43,	-14,	4,	-1,
+	1,	-1,	-5,	108,	35,	-13,	4,	-1,
+	2,	-3,	0,	111,	27,	-11,	3,	-1,
+	2,	-5,	6,	113,	19,	-9,	3,	-1,
+
+	/* IPC_PP_H_1_2 */
+	0,	-3,	0,	35,	64,	35,	0,	-3,
+	0,	-3,	1,	38,	64,	32,	-1,	-3,
+	0,	-3,	2,	41,	63,	29,	-2,	-2,
+	0,	-4,	4,	43,	63,	27,	-3,	-2,
+	0,	-4,	5,	46,	62,	24,	-3,	-2,
+	0,	-4,	7,	49,	60,	21,	-3,	-2,
+	-1,	-4,	9,	51,	59,	19,	-4,	-1,
+	-1,	-4,	12,	53,	57,	16,	-4,	-1,
+	-1,	-4,	14,	55,	55,	14,	-4,	-1,
+	-1,	-4,	16,	57,	53,	12,	-4,	-1,
+	-1,	-4,	19,	59,	51,	9,	-4,	-1,
+	-2,	-3,	21,	60,	49,	7,	-4,	0,
+	-2,	-3,	24,	62,	46,	5,	-4,	0,
+	-2,	-3,	27,	63,	43,	4,	-4,	0,
+	-2,	-2,	29,	63,	41,	2,	-3,	0,
+	-3,	-1,	32,	64,	38,	1,	-3,	0,
+
+	/* IPC_PP_H_1_3 */
+	0,	0,	10,	32,	44,	32,	10,	0,
+	-1,	0,	11,	33,	45,	31,	9,	0,
+	-1,	0,	12,	35,	45,	29,	8,	0,
+	-1,	1,	13,	36,	44,	28,	7,	0,
+	-1,	1,	15,	37,	44,	26,	6,	0,
+	-1,	2,	16,	38,	43,	25,	5,	0,
+	-1,	2,	18,	39,	43,	23,	5,	-1,
+	-1,	3,	19,	40,	42,	22,	4,	-1,
+	-1,	3,	21,	41,	41,	21,	3,	-1,
+	-1,	4,	22,	42,	40,	19,	3,	-1,
+	-1,	5,	23,	43,	39,	18,	2,	-1,
+	0,	5,	25,	43,	38,	16,	2,	-1,
+	0,	6,	26,	44,	37,	15,	1,	-1,
+	0,	7,	28,	44,	36,	13,	1,	-1,
+	0,	8,	29,	45,	35,	12,	0,	-1,
+	0,	9,	31,	45,	33,	11,	0,	-1,
+
+	/* IPC_PP_H_1_4 */
+	0,	2,	13,	30,	38,	30,	13,	2,
+	0,	3,	14,	30,	38,	29,	12,	2,
+	0,	3,	15,	31,	38,	28,	11,	2,
+	0,	4,	16,	32,	38,	27,	10,	1,
+	0,	4,	17,	33,	37,	26,	10,	1,
+	0,	5,	18,	34,	37,	24,	9,	1,
+	0,	5,	19,	34,	37,	24,	8,	1,
+	1,	6,	20,	35,	36,	22,	7,	1,
+	1,	6,	21,	36,	36,	21,	6,	1,
+	1,	7,	22,	36,	35,	20,	6,	1,
+	1,	8,	24,	37,	34,	19,	5,	0,
+	1,	9,	24,	37,	34,	18,	5,	0,
+	1,	10,	26,	37,	33,	17,	4,	0,
+	1,	10,	27,	38,	32,	16,	4,	0,
+	2,	11,	28,	38,	31,	15,	3,	0,
+	2,	12,	29,	38,	30,	14,	3,	0
+};
+
+/* Horizontal C 4tap */
+const s8 ipc_4tap_coef_c_h[] = {
+	/* IPC_PP_H_NORMAL */
+	0,	0,	127,	0,
+	0,	5,	126,	-3,
+	-1,	11,	124,	-6,
+	-1,	19,	118,	-8,
+	-2,	27,	111,	-8,
+	-3,	37,	102,	-8,
+	-4,	48,	92,	-8,
+	-5,	59,	81,	-7,
+	-6,	70,	70,	-6,
+	-7,	81,	59,	-5,
+	-8,	92,	48,	-4,
+	-8,	102,	37,	-3,
+	-8,	111,	27,	-2,
+	-8,	118,	19,	-1,
+	-6,	124,	11,	-1,
+	-3,	126,	5,	0,
+
+	/* IPC_PP_H_8_9 */
+	0,	 8,	112,	8,
+	-1,	13,	113,	3,
+	-2,	19,	111,	0,
+	-2,	26,	107,	-3,
+	-3,	34,	101,	-4,
+	-3,	42,	94,	-5,
+	-4,	51,	86,	-5,
+	-5,	60,	78,	-5,
+	-5,	69,	69,	-5,
+	-5,	78,	60,	-5,
+	-5,	86,	51,	-4,
+	-5,	94,	42,	-3,
+	-4,	101,	34,	-3,
+	-3,	107,	26,	-2,
+	0,	111,	19,	-2,
+	3,	113,	13,	-1,
+
+	/* 	IPC_PP_H_1_2 */
+	0,	26,	76,	26,
+	0,	30,	76,	22,
+	0,	34,	75,	19,
+	1,	38,	73,	16,
+	1,	43,	71,	13,
+	2,	47,	69,	10,
+	3,	51,	66,	8,
+	4,	55,	63,	6,
+	5,	59,	59,	5,
+	6,	63,	55,	4,
+	8,	66,	51,	3,
+	10,	69,	47,	2,
+	13,	71,	43,	1,
+	16,	73,	38,	1,
+	19,	75,	34,	0,
+	22,	76,	30,	0,
+
+	/*	IPC_PP_H_1_3 */
+	0,	30,	68,	30,
+	2,	33,	66,	27,
+	3,	36,	66,	23,
+	3,	39,	65,	21,
+	4,	43,	63,	18,
+	5,	46,	62,	15,
+	6,	49,	60,	13,
+	8,	52,	57,	11,
+	9,	55,	55,	9,
+	11,	57,	52,	8,
+	13,	60,	49,	6,
+	15,	62,	46,	5,
+	18,	63,	43,	4,
+	21,	65,	39,	3,
+	23,	66,	36,	3,
+	27,	66,	33,	2,
+
+	/*  IPC_PP_H_1_4 */
+	0,	31,	66,	31,
+	3,	34,	63,	28,
+	4,	37,	62,	25,
+	4,	40,	62,	22,
+	5,	43,	61,	19,
+	6,	46,	59,	17,
+	7,	48,	58,	15,
+	9,	51,	55,	13,
+	11,	53,	53,	11,
+	13,	55,	51,	9,
+	15,	58,	48,	7,
+	17,	59,	46,	6,
+	19,	61,	43,	5,
+	22,	62,	40,	4,
+	25,	62,	37,	4,
+	28,	63,	34,	3,
+};
+
+
+/*  Vertical Y 8tap  */
+const s8 ipc_4tap_coef_y_v[] = {
+	/* IPC_PP_V_NORMAL  */
+	0,	0,	127,	0,
+	0,	5,	126,	-3,
+	-1,	11,	124,	-6,
+	-1,	19,	118,	-8,
+	-2,	27,	111,	-8,
+	-3,	37,	102,	-8,
+	-4,	48,	92,	-8,
+	-5,	59,	81,	-7,
+	-6,	70,	70,	-6,
+	-7,	81,	59,	-5,
+	-8,	92,	48,	-4,
+	-8,	102,	37,	-3,
+	-8,	111,	27,	-2,
+	-8,	118,	19,	-1,
+	-6,	124,	11,	-1,
+	-3,	126,	5,	0,
+
+	/* IPC_PP_V_5_6  */
+	0,	11,	106,	11,
+	-2,	16,	107,	7,
+	-2,	22,	105,	3,
+	-2,	29,	101,	0,
+	-3,	36,	96,	-1,
+	-3,	44,	90,	-3,
+	-4,	52,	84,	-4,
+	-4,	60,	76,	-4,
+	-4,	68,	68,	-4,
+	-4,	76,	60,	-4,
+	-4,	84,	52,	-4,
+	-3,	90,	44,	-3,
+	-1,	96,	36,	-3,
+	0,	101,	29,	-2,
+	3,	105,	22,	-2,
+	7,	107,	16,	-2,
+
+	/* IPC_PP_V_3_4  */
+	0,	15,	98,	15,
+	-2,	21,	97,	12,
+	-2,	26,	96,	8,
+	-2,	32,	93,	5,
+	-2,	39,	89,	2,
+	-2,	46,	84,	0,
+	-3,	53,	79,	-1,
+	-2,	59,	73,	-2,
+	-2,	66,	66,	-2,
+	-2,	73,	59,	-2,
+	-1,	79,	53,	-3,
+	0,	84,	46,	-2,
+	2,	89,	39,	-2,
+	5,	93,	32,	-2,
+	8,	96,	26,	-2,
+	12,	97,	21,	-2,
+
+	/* IPC_PP_V_1_2  */
+	0,	26,	76,	26,
+	0,	30,	76,	22,
+	0,	34,	75,	19,
+	1,	38,	73,	16,
+	1,	43,	71,	13,
+	2,	47,	69,	10,
+	3,	51,	66,	8,
+	4,	55,	63,	6,
+	5,	59,	59,	5,
+	6,	63,	55,	4,
+	8,	66,	51,	3,
+	10,	69,	47,	2,
+	13,	71,	43,	1,
+	16,	73,	38,	1,
+	19,	75,	34,	0,
+	22,	76,	30,	0,
+
+	/* IPC_PP_V_1_3 */
+	0,	30,	68,	30,
+	2,	33,	66,	27,
+	3,	36,	66,	23,
+	3,	39,	65,	21,
+	4,	43,	63,	18,
+	5,	46,	62,	15,
+	6,	49,	60,	13,
+	8,	52,	57,	11,
+	9,	55,	55,	9,
+	11,	57,	52,	8,
+	13,	60,	49,	6,
+	15,	62,	46,	5,
+	18,	63,	43,	4,
+	21,	65,	39,	3,
+	23,	66,	36,	3,
+	27,	66,	33,	2,
+
+	/* IPC_PP_V_1_4  */
+	0,	31,	66,	31,
+	3,	34,	63,	28,
+	4,	37,	62,	25,
+	4,	40,	62,	22,
+	5,	43,	61,	19,
+	6,	46,	59,	17,
+	7,	48,	58,	15,
+	9,	51,	55,	13,
+	11,	53,	53,	11,
+	13,	55,	51,	9,
+	15,	58,	48,	7,
+	17,	59,	46,	6,
+	19,	61,	43,	5,
+	22,	62,	40,	4,
+	25,	62,	37,	4,
+	28,	63,	34,	3
+};
+
+#endif /* __IPC_TABLE_H */
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/Kconfig b/drivers/media/video/samsung/fimg2d3x-exynos4/Kconfig
new file mode 100644
index 0000000..dccbc16
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/Kconfig
@@ -0,0 +1,22 @@
+# drivers/media/video/samsung/fimg2d3x/Kconfig
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+config VIDEO_FIMG2D3X
+	bool "Samsung Graphics 2D Driver"
+	select VIDEO_FIMG2D
+	depends on VIDEO_SAMSUNG && CPU_EXYNOS4210
+	default n
+	---help---
+	  This is a graphics 2D (FIMG2D 3.x) driver for Samsung ARM based SoC.
+
+config VIDEO_FIMG2D3X_DEBUG
+	bool "Enables FIMG2D debug messages"
+	depends on VIDEO_FIMG2D3X
+	default n
+	---help---
+	  This enables FIMG2D driver debug messages.
+
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/Makefile b/drivers/media/video/samsung/fimg2d3x-exynos4/Makefile
new file mode 100644
index 0000000..a24f530
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/Makefile
@@ -0,0 +1,17 @@
+# drivers/media/video/samsung/fimg2d3x/Makefile
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+obj-$(CONFIG_VIDEO_FIMG2D3X) += fimg2d_dev.o fimg2d_cache.o fimg2d3x_regs.o fimg2d_core.o
+
+ifeq ($(CONFIG_VIDEO_FIMG2D3X_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d.h b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d.h
new file mode 100644
index 0000000..2c2c07b
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d.h
@@ -0,0 +1,397 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d_3x.h
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved.
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+ 
+#ifndef __SEC_FIMG2D_H_
+#define __SEC_FIMG2D_H_
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/sched.h>
+
+#define G2D_SFR_SIZE    0x1000
+
+#define TRUE            (1)
+#define FALSE           (0)
+
+#define G2D_MINOR       240
+
+#define G2D_IOCTL_MAGIC 'G'
+
+#define G2D_BLIT                        _IO(G2D_IOCTL_MAGIC,0)
+#define G2D_GET_VERSION                 _IO(G2D_IOCTL_MAGIC,1)
+#define G2D_GET_MEMORY                  _IOR(G2D_IOCTL_MAGIC,2, unsigned int)
+#define G2D_GET_MEMORY_SIZE             _IOR(G2D_IOCTL_MAGIC,3, unsigned int)
+#define G2D_DMA_CACHE_CLEAN	        _IOWR(G2D_IOCTL_MAGIC,4, struct g2d_dma_info)
+#define G2D_DMA_CACHE_FLUSH	        _IOWR(G2D_IOCTL_MAGIC,5, struct g2d_dma_info)
+#define G2D_SYNC                    	_IO(G2D_IOCTL_MAGIC,6)
+#define G2D_RESET                    	_IO(G2D_IOCTL_MAGIC, 7)
+
+#define G2D_TIMEOUT             (1000)
+
+#define G2D_MAX_WIDTH   	(2048)
+#define G2D_MAX_HEIGHT  	(2048)
+
+#define G2D_ALPHA_VALUE_MAX 	(255)
+
+#define G2D_POLLING         	(1<<0)
+#define G2D_INTERRUPT       	(0<<0)
+#define G2D_CACHE_OP      	(1<<1)
+#define G2D_NONE_INVALIDATE 	(0<<1)
+#define G2D_HYBRID_MODE 	(1<<2)
+
+#define G2D_PT_NOTVALID		(0)
+#define G2D_PT_CACHED		(1)
+#define G2D_PT_UNCACHED		(2)
+
+#define GET_FRAME_SIZE(rect)    ((rect.full_w) * (rect.full_h) * (rect.bytes_per_pixel))
+#define GET_RECT_SIZE(rect)     ((rect.full_w) * (rect.h) * (rect.bytes_per_pixel))
+#define GET_REAL_SIZE(rect)     ((rect.full_w) * (rect.h) * (rect.bytes_per_pixel))
+#define GET_STRIDE(rect)		((rect.full_w) * (rect.bytes_per_pixel))
+#define GET_SPARE_BYTES(rect)	((rect.full_w - rect.w) * rect.bytes_per_pixel)
+#define GET_START_ADDR(rect)    (rect.addr + ((rect.y * rect.full_w) * rect.bytes_per_pixel))
+#define GET_REAL_START_ADDR(rect)    GET_START_ADDR(rect) + (rect.x * rect.bytes_per_pixel)
+#define GET_REAL_END_ADDR(rect)    GET_START_ADDR(rect) + GET_RECT_SIZE(rect) - ((rect.full_w - (rect.x + rect.w)) * rect.bytes_per_pixel)
+
+#define GET_RECT_SIZE_C(rect, clip)     ((rect.full_w) * (clip.b - clip.t) * (rect.bytes_per_pixel))
+#define GET_START_ADDR_C(rect, clip)    (rect.addr + ((clip.t * rect.full_w) * rect.bytes_per_pixel))
+#define GET_REAL_START_ADDR_C(rect, clip)    GET_START_ADDR_C(rect, clip) + (clip.l * rect.bytes_per_pixel)
+#define GET_REAL_END_ADDR_C(rect, clip)    GET_START_ADDR_C(rect, clip) + GET_RECT_SIZE_C(rect, clip) - ((rect.full_w - clip.r) * rect.bytes_per_pixel)
+
+#define GET_USEC(before, after) ((after.tv_sec - before.tv_sec) * 1000000 + (after.tv_usec - before.tv_usec))
+
+typedef enum {
+	G2D_ROT_0 = 0,
+	G2D_ROT_90,
+	G2D_ROT_180,
+	G2D_ROT_270,
+	G2D_ROT_X_FLIP,
+	G2D_ROT_Y_FLIP
+} G2D_ROT_DEG;
+
+typedef enum {
+	G2D_ALPHA_BLENDING_MIN    = 0,   // wholly transparent
+	G2D_ALPHA_BLENDING_MAX    = 255, // 255
+	G2D_ALPHA_BLENDING_OPAQUE = 256, // opaque
+} G2D_ALPHA_BLENDING_MODE;
+    
+typedef enum {
+	G2D_COLORKEY_NONE = 0,
+	G2D_COLORKEY_SRC_ON,
+	G2D_COLORKEY_DST_ON,
+	G2D_COLORKEY_SRC_DST_ON,
+}G2D_COLORKEY_MODE;
+
+typedef enum {
+	G2D_BLUE_SCREEN_NONE = 0,
+	G2D_BLUE_SCREEN_TRANSPARENT,
+	G2D_BLUE_SCREEN_WITH_COLOR,
+}G2D_BLUE_SCREEN_MODE;
+
+typedef enum {
+	G2D_ROP_SRC = 0,
+	G2D_ROP_DST,
+	G2D_ROP_SRC_AND_DST,
+	G2D_ROP_SRC_OR_DST,
+	G2D_ROP_3RD_OPRND,
+	G2D_ROP_SRC_AND_3RD_OPRND,
+	G2D_ROP_SRC_OR_3RD_OPRND,
+	G2D_ROP_SRC_XOR_3RD_OPRND,
+	G2D_ROP_DST_OR_3RD,
+}G2D_ROP_TYPE;
+
+typedef enum {
+	G2D_THIRD_OP_NONE = 0,
+	G2D_THIRD_OP_PATTERN,
+	G2D_THIRD_OP_FG,
+	G2D_THIRD_OP_BG
+}G2D_THIRD_OP_MODE;
+
+typedef enum {
+	G2D_BLACK = 0,
+	G2D_RED,
+	G2D_GREEN,
+	G2D_BLUE,
+	G2D_WHITE, 
+	G2D_YELLOW,
+	G2D_CYAN,
+	G2D_MAGENTA
+}G2D_COLOR;
+
+typedef enum {
+	G2D_RGB_565 = ((0<<4)|2),
+
+	G2D_ABGR_8888 = ((2<<4)|1),
+	G2D_BGRA_8888 = ((3<<4)|1),
+	G2D_ARGB_8888 = ((0<<4)|1),
+	G2D_RGBA_8888 = ((1<<4)|1),
+
+	G2D_XBGR_8888 = ((2<<4)|0),
+	G2D_BGRX_8888 = ((3<<4)|0),
+	G2D_XRGB_8888 = ((0<<4)|0),
+	G2D_RGBX_8888 = ((1<<4)|0),
+
+	G2D_ABGR_1555 = ((2<<4)|4),
+	G2D_BGRA_5551 = ((3<<4)|4),
+	G2D_ARGB_1555 = ((0<<4)|4),
+	G2D_RGBA_5551 = ((1<<4)|4),
+
+	G2D_XBGR_1555 = ((2<<4)|3),
+	G2D_BGRX_5551 = ((3<<4)|3),
+	G2D_XRGB_1555 = ((0<<4)|3),
+	G2D_RGBX_5551 = ((1<<4)|3),
+
+	G2D_ABGR_4444 = ((2<<4)|6),
+	G2D_BGRA_4444 = ((3<<4)|6),
+	G2D_ARGB_4444 = ((0<<4)|6),
+	G2D_RGBA_4444 = ((1<<4)|6),
+
+	G2D_XBGR_4444 = ((2<<4)|5),
+	G2D_BGRX_4444 = ((3<<4)|5),
+	G2D_XRGB_4444 = ((0<<4)|5),
+	G2D_RGBX_4444 = ((1<<4)|5),
+	
+	G2D_PACKED_BGR_888 = ((2<<4)|7),
+	G2D_PACKED_RGB_888 = ((0<<4)|7),
+
+	G2D_MAX_COLOR_SPACE
+}G2D_COLOR_SPACE;
+
+typedef enum {
+        G2D_Clear_Mode,    //!< [0, 0]
+        G2D_Src_Mode,      //!< [Sa, Sc]
+        G2D_Dst_Mode,      //!< [Da, Dc]
+        G2D_SrcOver_Mode,  //!< [Sa + Da - Sa*Da, Rc = Sc + (1 - Sa)*Dc]
+        G2D_DstOver_Mode,  //!< [Sa + Da - Sa*Da, Rc = Dc + (1 - Da)*Sc]
+        G2D_SrcIn_Mode,    //!< [Sa * Da, Sc * Da]
+        G2D_DstIn_Mode,    //!< [Sa * Da, Sa * Dc]
+        G2D_SrcOut_Mode,   //!< [Sa * (1 - Da), Sc * (1 - Da)]
+        G2D_DstOut_Mode,   //!< [Da * (1 - Sa), Dc * (1 - Sa)]
+        G2D_SrcATop_Mode,  //!< [Da, Sc * Da + (1 - Sa) * Dc]
+        G2D_DstATop_Mode,  //!< [Sa, Sa * Dc + Sc * (1 - Da)]
+        G2D_Xor_Mode,      //!< [Sa + Da - 2 * Sa * Da, Sc * (1 - Da) + (1 - Sa) * Dc]
+
+        // these modes are defined in the SVG Compositing standard
+        // http://www.w3.org/TR/2009/WD-SVGCompositing-20090430/
+        G2D_Plus_Mode,
+        G2D_Multiply_Mode,
+        G2D_Screen_Mode,
+        G2D_Overlay_Mode,
+        G2D_Darken_Mode,
+        G2D_Lighten_Mode,
+        G2D_ColorDodge_Mode,
+        G2D_ColorBurn_Mode,
+        G2D_HardLight_Mode,
+        G2D_SoftLight_Mode,
+        G2D_Difference_Mode,
+        G2D_Exclusion_Mode,
+
+        kLastMode = G2D_Exclusion_Mode
+}G2D_PORTTERDUFF_MODE;
+
+typedef enum {
+       G2D_MEMORY_KERNEL,
+       G2D_MEMORY_USER
+}G2D_MEMORY_TYPE;
+
+typedef struct {
+        int    x;
+        int    y;
+        unsigned int    w;
+        unsigned int    h;
+        unsigned int    full_w;
+        unsigned int    full_h;
+        int             color_format;
+        unsigned int    bytes_per_pixel;
+        unsigned char 	* addr;
+} g2d_rect;
+
+typedef struct {
+        unsigned int    t;
+        unsigned int    b;
+        unsigned int    l;
+        unsigned int    r;
+} g2d_clip;
+
+typedef struct {
+        unsigned int    rotate_val;
+        unsigned int    alpha_val;
+
+        unsigned int    blue_screen_mode;     //true : enable, false : disable
+        unsigned int    color_key_val;        //screen color value
+        unsigned int    color_switch_val;     //one color
+
+        unsigned int    src_color;            // when set one color on SRC
+        		
+        unsigned int    third_op_mode;
+        unsigned int    rop_mode;
+        unsigned int    mask_mode;
+        unsigned int    render_mode;    
+        unsigned int    potterduff_mode;
+        unsigned int    memory_type;
+} g2d_flag;
+
+typedef struct {
+        g2d_rect src_rect;
+        g2d_rect dst_rect;
+        g2d_clip clip;   
+        g2d_flag flag;
+} g2d_params;
+
+/* for reserved memory */
+struct g2d_reserved_mem {
+	/* buffer base */
+	unsigned int	base;
+	/* buffer size */
+	unsigned int	size;
+};
+
+
+struct g2d_dma_info {
+	unsigned long addr;
+	unsigned int  size;
+};
+
+struct g2d_platdata {
+	int hw_ver;
+	const char *parent_clkname;
+	const char *clkname;
+	const char *gate_clkname;
+	unsigned long clkrate;
+};
+
+struct g2d_timer {
+	int			cnt;
+	struct timeval		start_marker;
+	struct timeval		cur_marker;
+};
+
+struct g2d_global {
+	int             	irq_num;
+	struct resource 	* mem;
+	void   __iomem  	* base;
+	struct clk 		* clock;
+	atomic_t		clk_enable_flag;
+	wait_queue_head_t 	waitq;
+	atomic_t        	in_use;
+	atomic_t		num_of_object;
+	struct mutex		lock;
+	struct device		* dev;
+	atomic_t 		ready_to_run;
+	int 			src_attribute;
+	int 			dst_attribute;
+
+	struct g2d_reserved_mem	reserved_mem;		/* for reserved memory */
+	atomic_t		is_mmu_faulted;
+	unsigned int		faulted_addr;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend	early_suspend;
+#endif	
+	int                     irq_handled;
+};
+
+
+/****** debug message API *****/
+enum fimg2d_log {
+	FIMG2D_LOG_DEBUG	= 0x1000,
+	FIMG2D_LOG_INFO		= 0x0100,
+	FIMG2D_LOG_WARN		= 0x0010,
+	FIMG2D_LOG_ERR		= 0x0001,
+};
+
+/* debug macro */
+#define FIMG2D_LOG_DEFAULT	(FIMG2D_LOG_WARN | FIMG2D_LOG_ERR)
+
+#define FIMG2D_DEBUG(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_DEBUG)			\
+			printk(KERN_DEBUG "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define FIMG2D_INFO(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_INFO)			\
+			printk(KERN_INFO "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define FIMG2D_WARN(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_WARN)			\
+			printk(KERN_WARNING "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define FIMG2D_ERROR(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_ERR)			\
+			printk(KERN_ERR "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define fimg2d_dbg(fmt, ...)		FIMG2D_DEBUG(fmt, ##__VA_ARGS__)
+#define fimg2d_info(fmt, ...)		FIMG2D_INFO(fmt, ##__VA_ARGS__)
+#define fimg2d_warn(fmt, ...)		FIMG2D_WARN(fmt, ##__VA_ARGS__)
+#define fimg2d_err(fmt, ...)		FIMG2D_ERROR(fmt, ##__VA_ARGS__)
+
+
+/**** function declearation***************************/
+int g2d_check_params(g2d_params *params);
+void g2d_start_bitblt(struct g2d_global *g2d_dev, g2d_params *params);
+void g2d_check_fifo_state_wait(struct g2d_global *g2d_dev);
+u32  g2d_set_src_img(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag);
+u32  g2d_set_dst_img(struct g2d_global *g2d_dev, g2d_rect * rect);
+u32  g2d_set_pattern(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag);
+u32  g2d_set_clip_win(struct g2d_global *g2d_dev, g2d_clip * rect);
+u32  g2d_set_rotation(struct g2d_global *g2d_dev, g2d_flag * flag);
+u32  g2d_set_color_key(struct g2d_global *g2d_dev, g2d_flag * flag);
+u32  g2d_set_alpha(struct g2d_global *g2d_dev, g2d_flag * flag);
+void g2d_set_bitblt_cmd(struct g2d_global *g2d_dev, g2d_rect * src_rect, g2d_rect * dst_rect, g2d_clip * clip, u32 blt_cmd);
+void g2d_reset(struct g2d_global *g2d_dev);
+void g2d_disable_int(struct g2d_global *g2d_dev);
+void g2d_set_int_finish(struct g2d_global *g2d_dev);
+
+/* fimg2d_cache */
+void g2d_clip_for_src(g2d_rect *src_rect, g2d_rect *dst_rect, g2d_clip *clip, g2d_clip *src_clip);
+void g2d_mem_inner_cache(g2d_params *params);
+void g2d_mem_outer_cache(struct g2d_global *g2d_dev, g2d_params *params, int *need_dst_clean);
+void g2d_mem_cache_oneshot(void *src_addr,  void *dst_addr, unsigned long src_size, unsigned long dst_size);
+u32 g2d_mem_cache_op(unsigned int cmd, void * addr, unsigned int size);
+void g2d_mem_outer_cache_flush(void *start_addr, unsigned long size);                                      
+void g2d_mem_outer_cache_clean(const void *start_addr, unsigned long size);
+void g2d_mem_outer_cache_inv(g2d_params *params);
+u32 g2d_check_pagetable(void * vaddr, unsigned int size, unsigned long pgd);
+void g2d_pagetable_clean(const void *start_addr, unsigned long size, unsigned long pgd);
+int g2d_check_need_dst_cache_clean(g2d_params * params);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void g2d_early_suspend(struct early_suspend *h);
+void g2d_late_resume(struct early_suspend *h);
+#endif
+
+/* fimg2d_core */
+int g2d_clk_enable(struct g2d_global *g2d_dev);
+int g2d_clk_disable(struct g2d_global *g2d_dev);
+void g2d_sysmmu_on(struct g2d_global *g2d_dev);
+void g2d_sysmmu_off(struct g2d_global *g2d_dev);
+void g2d_sysmmu_set_pgd(u32 pgd);
+void g2d_fail_debug(g2d_params *params);
+int g2d_init_regs(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_do_blit(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_wait_for_finish(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_init_mem(struct device *dev, unsigned int *base, unsigned int *size);
+
+#endif /*__SEC_FIMG2D_H_*/
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.c b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.c
new file mode 100644
index 0000000..33ce53e
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.c
@@ -0,0 +1,376 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d register control functions.
+ */
+
+#include <mach/map.h>
+#include <asm/io.h>
+#include <mach/regs-fimg2d3x.h>
+
+#include "fimg2d3x_regs.h"
+#include "fimg2d.h"
+
+void get_rot_config(unsigned int rotate_value, u32 *rot, u32 *src_dir, u32 *dst_dir)
+{
+	switch(rotate_value) {
+	case G2D_ROT_90: 
+		*rot = 1;   	/* rotation = 1, src_y_dir == dst_y_dir, src_x_dir == dst_x_dir */
+		*src_dir = 0;		
+		*dst_dir = 0;		
+		break;
+
+	case G2D_ROT_270: 
+		*rot = 1;   	/* rotation = 1, src_y_dir != dst_y_dir, src_x_dir != dst_x_dir */
+		*src_dir = 0;
+		*dst_dir = 0x3;
+		break;			
+
+	case G2D_ROT_180: 
+		*rot = 0;    	/* rotation = 0, src_y_dir != dst_y_dir, src_x_dir != dst_x_dir */
+		*src_dir = 0;
+		*dst_dir = 0x3;
+		break;
+
+	case G2D_ROT_X_FLIP: 
+		*rot = 0;    	/* rotation = 0, src_y_dir != dst_y_dir */
+		*src_dir = 0;
+		*dst_dir = 0x2;
+		break;
+
+	case G2D_ROT_Y_FLIP: 
+		*rot = 0;    	/* rotation = 0, src_x_dir != dst_y_dir */
+		*src_dir = 0;
+		*dst_dir = 0x1;
+		break;
+
+	default :
+		*rot = 0;   	/* rotation = 0; */
+		*src_dir = 0;
+		*dst_dir = 0;
+		break;
+	}
+	
+	return ;
+}
+
+int g2d_check_params(g2d_params *params)
+{
+	g2d_rect * src_rect = &params->src_rect;
+	g2d_rect * dst_rect = &params->dst_rect;
+	g2d_flag * flag     = &params->flag;
+
+	/* source */
+	if (0 > src_rect->x || 0 > src_rect->y) {
+		return -1;
+	}
+
+	if (0 == src_rect->h || 0 == src_rect->w) {
+		return -1;
+	}
+
+	if (8000 < src_rect->x+src_rect->w || 8000 < src_rect->y+src_rect->h) {
+		return -1;
+	}
+
+	/* destination */
+	if (0 > dst_rect->x || 0 > dst_rect->y) {
+		return -1;
+	}
+
+	if (0 == dst_rect->h || 0 == dst_rect->w) {
+		return -1;
+	}
+
+	if (8000 < dst_rect->x+dst_rect->w || 8000 < dst_rect->y+dst_rect->h) {
+		return -1;
+	}
+
+	if (flag->alpha_val > G2D_ALPHA_BLENDING_OPAQUE) {
+		return -1; 
+	}
+
+	return 0;
+}
+
+void g2d_check_fifo_state_wait(struct g2d_global *g2d_dev)
+{
+	/* 1 = The graphics engine finishes the execution of command. */
+	/* 0 = in the middle of rendering process. */
+	while(!(readl(g2d_dev->base + FIFO_STAT_REG) & 0x1));
+
+	return;
+}
+
+
+u32 g2d_set_src_img(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+
+	/* set  source to one color */
+	//if(rect == NULL)
+	if (flag->potterduff_mode == G2D_Clear_Mode) {
+		/* select source */
+		writel(G2D_SRC_SELECT_R_USE_FG_COLOR, g2d_dev->base + SRC_SELECT_REG);
+
+		/* foreground color */
+		// writel(flag->src_color, g2d_dev->base + FG_COLOR_REG);		
+		writel(0, g2d_dev->base + FG_COLOR_REG);	
+	} else {
+		/* select source */
+		writel(G2D_SRC_SELECT_R_NORMAL, g2d_dev->base + SRC_SELECT_REG);
+
+		/* set base address of source image */
+		writel((u32)rect->addr,   g2d_dev->base + SRC_BASE_ADDR_REG);
+
+		/* set stride */
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + SRC_STRIDE_REG);
+
+		/* set color mode */
+		writel(rect->color_format, g2d_dev->base + SRC_COLOR_MODE_REG);
+
+		/* set coordinate of source image */
+		data = (rect->y << 16) | (rect->x);
+		writel(data, g2d_dev->base + SRC_LEFT_TOP_REG);
+
+		data = ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+		writel(data, g2d_dev->base + SRC_RIGHT_BOTTOM_REG);
+        
+	}
+
+	return blt_cmd;
+}
+
+u32 g2d_set_dst_img(struct g2d_global *g2d_dev, g2d_rect * rect)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+	
+	/* select destination */
+	writel(G2D_DST_SELECT_R_NORMAL, g2d_dev->base + DST_SELECT_REG);
+
+	/* set base address of destination image */
+	writel((u32)rect->addr,   g2d_dev->base + DST_BASE_ADDR_REG);
+
+	/* set stride */
+	writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + DST_STRIDE_REG);
+
+	/* set color mode */
+	writel(rect->color_format, g2d_dev->base + DST_COLOR_MODE_REG);
+
+	/* set coordinate of destination image */
+	data = (rect->y << 16) | (rect->x);
+	writel(data, g2d_dev->base + DST_LEFT_TOP_REG);
+
+	data = ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+	writel(data, g2d_dev->base + DST_RIGHT_BOTTOM_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_rotation(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+	u32 rot=0, src_dir=0, dst_dir=0;
+
+	get_rot_config(flag->rotate_val, &rot, &src_dir, &dst_dir);
+
+	writel(rot,     g2d_dev->base + ROTATE_REG);
+	writel(src_dir, g2d_dev->base + SRC_MSK_DIRECT_REG);
+	writel(dst_dir, g2d_dev->base + DST_PAT_DIRECT_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_clip_win(struct g2d_global *g2d_dev, g2d_clip * clip)
+{
+	u32 blt_cmd = 0;
+
+        //blt_cmd |= G2D_BLT_CMD_R_CW_ENABLE;
+	writel((clip->t << 16) | (clip->l), g2d_dev->base + CW_LEFT_TOP_REG);
+	writel((clip->b << 16) | (clip->r), g2d_dev->base + CW_RIGHT_BOTTOM_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_color_key(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+
+	/* Transparent Selection */
+	switch(flag->blue_screen_mode) {
+	case G2D_BLUE_SCREEN_TRANSPARENT :
+		writel(flag->color_key_val, g2d_dev->base + BS_COLOR_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_TRANS;
+		break;
+
+	case G2D_BLUE_SCREEN_WITH_COLOR :
+		writel(flag->color_switch_val,     g2d_dev->base + BG_COLOR_REG);
+		writel(flag->color_key_val, g2d_dev->base + BS_COLOR_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_BLUESCR;
+		break;
+
+	case G2D_BLUE_SCREEN_NONE :
+	default:
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_OPAQUE;
+		break;
+	}
+
+	blt_cmd |= G2D_BLT_CMD_R_COLOR_KEY_DISABLE;
+
+	return blt_cmd;
+}
+
+u32 g2d_set_pattern(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+
+	/* Third Operand Selection */
+	switch(flag->third_op_mode) {	
+	case G2D_THIRD_OP_PATTERN :
+		/* set base address of pattern image */
+		writel((u32)rect->addr, g2d_dev->base + PAT_BASE_ADDR_REG);
+
+		/* set size of pattern image */
+		data =   ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+		writel(data, g2d_dev->base + PAT_SIZE_REG);
+
+		/* set stride */
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + PAT_STRIDE_REG);
+
+		/* set color mode */
+		writel(rect->color_format, g2d_dev->base + PAT_COLOR_MODE_REG);
+
+		data =   (rect->y << 16) | rect->x;
+		writel(data, g2d_dev->base + PAT_OFFSET_REG);
+
+		data = G2D_THIRD_OP_REG_PATTERN;
+		break;
+	case G2D_THIRD_OP_FG :
+		data = G2D_THIRD_OP_REG_FG_COLOR;
+		break;
+	case G2D_THIRD_OP_BG :
+		data = G2D_THIRD_OP_REG_BG_COLOR;
+		break;
+	case G2D_THIRD_OP_NONE :
+	default:
+		data = G2D_THIRD_OP_REG_NONE;
+		break;
+	}
+
+	writel(data, g2d_dev->base + THIRD_OPERAND_REG);
+	
+	if(flag->third_op_mode == G2D_THIRD_OP_NONE) {
+		data = ((G2D_ROP_REG_SRC << 8) | G2D_ROP_REG_SRC);
+	} else {
+		switch(flag->rop_mode) {	
+		case G2D_ROP_DST:
+			data = ((G2D_ROP_REG_DST << 8) | G2D_ROP_REG_DST);
+			break;
+		case G2D_ROP_SRC_AND_DST:
+			data = ((G2D_ROP_REG_SRC_AND_DST << 8) | G2D_ROP_REG_SRC_AND_DST);
+			break;
+		case G2D_ROP_SRC_OR_DST:
+			data = ((G2D_ROP_REG_SRC_OR_DST << 8) | G2D_ROP_REG_SRC_OR_DST);
+			break;
+		case G2D_ROP_3RD_OPRND:
+			data = ((G2D_ROP_REG_3RD_OPRND << 8) | G2D_ROP_REG_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_AND_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_AND_3RD_OPRND << 8) | G2D_ROP_REG_SRC_AND_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_OR_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_OR_3RD_OPRND << 8) | G2D_ROP_REG_SRC_OR_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_XOR_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_XOR_3RD_OPRND << 8) | G2D_ROP_REG_SRC_XOR_3RD_OPRND);
+			break;
+		case G2D_ROP_DST_OR_3RD:
+			data = ((G2D_ROP_REG_DST_OR_3RD_OPRND << 8) | G2D_ROP_REG_DST_OR_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC:
+		default:
+			data = ((G2D_ROP_REG_SRC << 8) | G2D_ROP_REG_SRC);
+			break;
+		}
+	}
+	writel(data, g2d_dev->base + ROP4_REG);
+
+	/* Mask Operation */
+	if(flag->mask_mode == TRUE) {
+		writel((u32)rect->addr, g2d_dev->base + MASK_BASE_ADDR_REG);
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + MASK_STRIDE_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_MASK_ENABLE;
+	}
+
+	return blt_cmd;
+}
+
+u32 g2d_set_alpha(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+
+	/* Alpha Value */
+	if(flag->alpha_val <= G2D_ALPHA_VALUE_MAX) {
+		if ((flag->potterduff_mode == G2D_Clear_Mode) || (flag->potterduff_mode == G2D_Src_Mode))
+			blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_NONE;
+		else
+			blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_ALPHA_BLEND;
+		writel((flag->alpha_val & 0xff), g2d_dev->base + ALPHA_REG);
+	} else {
+		blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_NONE;
+	}
+
+	return blt_cmd;
+}
+
+void g2d_set_bitblt_cmd(struct g2d_global *g2d_dev, g2d_rect * src_rect, g2d_rect * dst_rect, g2d_clip * clip, u32 blt_cmd)
+{
+	if ((src_rect->w  != dst_rect->w)
+		|| (src_rect->h  != dst_rect->h)) {
+		blt_cmd |= G2D_BLT_CMD_R_STRETCH_ENABLE;
+	}
+	
+	if ((clip->t != dst_rect->y) || (clip->b != dst_rect->y + dst_rect->h) 
+		|| (clip->l != dst_rect->x) || (clip->r != dst_rect->x + dst_rect->w)) {
+		blt_cmd |= G2D_BLT_CMD_R_CW_ENABLE;
+	}
+	writel(blt_cmd, g2d_dev->base + BITBLT_COMMAND_REG);
+}
+
+void g2d_reset(struct g2d_global *g2d_dev)
+{
+	writel(G2D_SWRESET_R_RESET, g2d_dev->base + SOFT_RESET_REG);
+}
+
+void g2d_disable_int(struct g2d_global *g2d_dev)
+{
+	writel(G2D_INTEN_R_CF_DISABLE, g2d_dev->base + INTEN_REG);
+}
+
+void g2d_set_int_finish(struct g2d_global *g2d_dev)
+{
+	writel(G2D_INTC_PEND_R_INTP_CMD_FIN, g2d_dev->base + INTC_PEND_REG);
+}
+
+void g2d_start_bitblt(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	if (!(params->flag.render_mode & G2D_POLLING)) {
+		writel(G2D_INTEN_R_CF_ENABLE, g2d_dev->base + INTEN_REG);
+	}
+	writel(0x7, g2d_dev->base + CACHECTL_REG);
+
+	writel(G2D_BITBLT_R_START, g2d_dev->base + BITBLT_START_REG);
+}
+
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.h b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.h
new file mode 100644
index 0000000..f67f636
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d3x_regs.h
@@ -0,0 +1,278 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.*/
+
+#ifndef __SEC_FIMG2D3X_REGS_H
+#define __SEC_FIMG2D3X_REGS_H
+ 
+//**********************************************************
+//     Address Definition of SFR
+//**********************************************************
+#define SEC_G2DREG(x)           ((x))
+
+//**   General Register   *****************
+#define CONRTOL_REG             SEC_G2DREG(0x0000)
+#define SOFT_RESET_REG          SEC_G2DREG(0x0000)
+#define INTEN_REG               SEC_G2DREG(0x0004)
+#define INTC_PEND_REG           SEC_G2DREG(0x000C)
+#define FIFO_STAT_REG           SEC_G2DREG(0x0010)
+#define AXI_ID_MODE_REG         SEC_G2DREG(0x0014)
+#define CACHECTL_REG            SEC_G2DREG(0x0018)
+
+//**   G2D Command   *********************
+#define BITBLT_START_REG        SEC_G2DREG(0x0100)
+#define BITBLT_COMMAND_REG      SEC_G2DREG(0x0104)
+
+//**   Rotation & Direction   *************
+#define ROTATE_REG              SEC_G2DREG(0x0200)
+#define SRC_MSK_DIRECT_REG      SEC_G2DREG(0x0204)
+#define DST_PAT_DIRECT_REG      SEC_G2DREG(0x0208)
+// for old vector
+#define SRC_DIRECT_REG          SEC_G2DREG(0x0204)
+#define DST_DIRECT_REG          SEC_G2DREG(0x0208)
+
+//**   Source    **************************
+#define SRC_SELECT_REG          SEC_G2DREG(0x0300)
+#define SRC_BASE_ADDR_REG       SEC_G2DREG(0x0304)
+#define SRC_STRIDE_REG          SEC_G2DREG(0x0308)
+#define SRC_COLOR_MODE_REG      SEC_G2DREG(0x030C)
+#define SRC_LEFT_TOP_REG        SEC_G2DREG(0x0310)
+#define SRC_RIGHT_BOTTOM_REG    SEC_G2DREG(0x0314)
+
+//**   Destination  ***********************
+#define DST_SELECT_REG          SEC_G2DREG(0x0400)
+#define DST_BASE_ADDR_REG       SEC_G2DREG(0x0404)
+#define DST_STRIDE_REG          SEC_G2DREG(0x0408)
+#define DST_COLOR_MODE_REG      SEC_G2DREG(0x040C)
+#define DST_LEFT_TOP_REG        SEC_G2DREG(0x0410)
+#define DST_RIGHT_BOTTOM_REG    SEC_G2DREG(0x0414)
+
+//**   Pattern   **************************
+#define PAT_BASE_ADDR_REG       SEC_G2DREG(0x0500)
+#define PAT_SIZE_REG            SEC_G2DREG(0x0504)
+#define PAT_COLOR_MODE_REG      SEC_G2DREG(0x0508)
+#define PAT_OFFSET_REG          SEC_G2DREG(0x050C)
+#define PAT_STRIDE_REG          SEC_G2DREG(0x0510)
+
+//**   Mask   *****************************
+#define MASK_BASE_ADDR_REG      SEC_G2DREG(0x0520)
+#define MASK_STRIDE_REG         SEC_G2DREG(0x0524)
+
+//**   Clipping Window  *******************
+#define CW_LEFT_TOP_REG         SEC_G2DREG(0x0600)
+#define	CW_RIGHT_BOTTOM_REG     SEC_G2DREG(0x0604)
+
+//**   ROP4 & Blending   *****************
+#define THIRD_OPERAND_REG       SEC_G2DREG(0x0610)
+#define ROP4_REG                SEC_G2DREG(0x0614)
+#define ALPHA_REG               SEC_G2DREG(0x0618)
+
+//**   Color   ***************************
+#define FG_COLOR_REG            SEC_G2DREG(0x0700)
+#define BG_COLOR_REG            SEC_G2DREG(0x0704)
+#define BS_COLOR_REG            SEC_G2DREG(0x0708)
+
+//**   Color Key   ***********************
+#define SRC_COLORKEY_CTRL_REG   SEC_G2DREG(0x0710)
+#define SRC_COLORKEY_DR_MIN_REG SEC_G2DREG(0x0714)
+#define SRC_COLORKEY_DR_MAX_REG SEC_G2DREG(0x0718)
+#define DST_COLORKEY_CTRL_REG   SEC_G2DREG(0x071C)
+#define DST_COLORKEY_DR_MIN_REG SEC_G2DREG(0x0720)
+#define DST_COLORKEY_DR_MAX_REG SEC_G2DREG(0x0724)
+
+//**********************************************************
+//     Bit Definition part
+//**********************************************************
+ 
+/* software reset register (SOFT_RESET_REG : 0x0000) */
+#define	G2D_SWRESET_R_RESET                     (1<<0)
+
+/* interrupt enable register (INTEN_REG : 0x0004)) */
+#define G2D_INTEN_R_INT_TYPE_EDGE               (1<<1)
+#define G2D_INTEN_R_INT_TYPE_LEVEL              (0<<1)
+#define G2D_INTEN_R_CF_ENABLE                   (1<<0)
+#define G2D_INTEN_R_CF_DISABLE                  (0<<0)
+
+/* interrupt pending register (INTC_PEND_REG : 0x000C) */
+#define	G2D_INTC_PEND_R_INTP_CMD_FIN            (1<<0)
+
+/* AXI ID mode register (AXI_ID_MODE_REG : 0x0014) */
+#define	G2D_AXIID_MODE_R_MULTI_ID               (1<<0)
+#define G2D_AXIID_MODE_R_SIGNLE_ID              (0<<0)
+
+/* bitblit start register (BITBLT_START_REG : 0x0100) */
+#define	G2D_BITBLT_R_START                      (1<<0)
+
+/* bitblt command register (BITBLT_COMMAND_REG : 0x0104) */
+#define	G2D_BLT_CMD_R_COLOR_EXP_CORRECT         (0<<24)
+#define	G2D_BLT_CMD_R_COLOR_EXP_ZERO            (1<<24)
+
+#define	G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_DISLABE         (0<<22)
+#define G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_CONSTANT_ALPHA  (1<<22)
+#define G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_PERPIXEL_ALPHA  (2<<22)
+
+#define G2D_BLT_CMD_R_ALPHA_BLEND_NONE          (0<<20)
+#define	G2D_BLT_CMD_R_ALPHA_BLEND_ALPHA_BLEND   (1<<20)
+#define G2D_BLT_CMD_R_ALPHA_BLEND_FADE          (2<<20)
+// #define G2D_BLT_CMD_R_ALPHA_BLEND_PERPIXEL      (3<<20)
+
+#define G2D_BLT_CMD_R_ALPHA_BLEND_FAD_OFFSET    (8)
+
+#define G2D_BLT_CMD_R_COLOR_KEY_DISABLE         (0<<16)
+#define G2D_BLT_CMD_R_COLOR_KEY_ENABLE_SRC      (1<<16)
+#define	G2D_BLT_CMD_R_COLOR_KEY_ENABLE_DST      (2<<16)
+#define G2D_BLT_CMD_R_COLOP_KEY_ENABLE_SRC_DST  (3<<16)
+
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_OPAQUE   (0<<12)
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_TRANS    (1<<12)
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_BLUESCR  (2<<12)
+
+#define G2D_BLT_CMD_R_CW_ENABLE              (1<<8)
+#define G2D_BLT_CMD_R_STRETCH_ENABLE         (1<<4)
+#define	G2D_BLT_CMD_R_MASK_ENABLE            (1<<0)
+
+/* rotation register (ROTATE_REG : 0x02000) */
+#define	G2D_ROT_CMD_R_0                      (0<<0)
+#define	G2D_ROT_CMD_R_90                     (1<<0)
+
+/* source and mask direction register (SRC_MSK_DIRECT_REG : 0x0204) */
+#define	G2D_SRC_MSK_DIR_R_MSK_Y_POSITIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_MSK_Y_NEGATIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_SRC_Y_POSITIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_SRC_Y_POSITIVE     (0<<8)
+
+/* source image selection register (SRC_SELECT_REG : 0x0300) */
+#define G2D_SRC_SELECT_R_NORMAL              (0<<0)
+#define G2D_SRC_SELECT_R_USE_FG_COLOR        (1<<0)
+#define G2D_SRC_SELECT_R_USE_BG_COLOR        (2<<0)
+
+/* source image color mode register (SRC_COLOR_MODE_REG : 0x030C) */
+
+
+/* destination image selection register (DST_SELECT_REG : 0x0400) */
+#define G2D_DST_SELECT_R_NORMAL              (0<<0)
+#define G2D_DST_SELECT_R_USE_FG_COLOR        (1<<0)
+#define G2D_DST_SELECT_R_USE_BG_COLOR        (2<<0)
+
+#define	G2D_CMD0_REG_M_X                     (1<<8)
+
+#define	G2D_CMD0_REG_L                       (1<<1)
+#define	G2D_CMD0_REG_P                       (1<<0)
+
+/* BitBLT */
+#define	G2D_CMD1_REG_S                       (1<<1)
+#define	G2D_CMD1_REG_N                       (1<<0)
+
+/* resource color mode */
+#define G2D_COLOR_MODE_REG_C3_32BPP          (1<<3)
+#define G2D_COLOR_MODE_REG_C3_24BPP          (1<<3)
+#define G2D_COLOR_MODE_REG_C2_18BPP          (1<<2)
+#define G2D_COLOR_MODE_REG_C1_16BPP          (1<<1)
+#define G2D_COLOR_MODE_REG_C0_15BPP          (1<<0)
+
+#define G2D_COLOR_RGB_565                    (0x0<<0)
+#define G2D_COLOR_RGBA_5551                  (0x1<<0)
+#define G2D_COLOR_ARGB_1555                  (0x2<<0)
+#define G2D_COLOR_RGBA_8888                  (0x3<<0)
+#define G2D_COLOR_ARGB_8888                  (0x4<<0)
+#define G2D_COLOR_XRGB_8888                  (0x5<<0)
+#define G2D_COLOR_RGBX_8888                  (0x6<<0)
+#define G2D_COLOR_YUV422_SP                  (0x1<<3)
+
+#define G2D_CHL_ORDER_XRGB                   (0<<4) // ARGB,XRGB
+#define G2D_CHL_ORDER_RGBX                   (1<<4) // RGBA,RGBX
+#define G2D_CHL_ORDER_XBGR                   (2<<4) // ABGR,XBGR
+#define G2D_CHL_ORDER_BGRX                   (3<<4) // BGRA,BGRX
+
+#define G2D_FMT_XRGB_8888                    (0)
+#define G2D_FMT_ARGB_8888                    (1)
+#define G2D_FMT_RGB_565                      (2)
+#define G2D_FMT_XRGB_1555                    (3)
+#define G2D_FMT_ARGB_1555                    (4)
+#define G2D_FMT_XRGB_4444                    (5)
+#define G2D_FMT_ARGB_4444                    (6)
+#define G2D_FMT_PACKED_RGB_888               (7)
+
+/* rotation mode */
+#define G2D_ROTATRE_REG_FY                   (1<<5)
+#define G2D_ROTATRE_REG_FX                   (1<<4)
+#define G2D_ROTATRE_REG_R3_270               (1<<3)
+#define G2D_ROTATRE_REG_R2_180               (1<<2)
+#define G2D_ROTATRE_REG_R1_90                (1<<1)
+#define G2D_ROTATRE_REG_R0_0                 (1<<0)
+
+/* Endian select */
+#define G2D_ENDIAN_DST_BIG_ENDIAN            (1<<1)
+#define G2D_ENDIAN_DST_LITTLE_ENDIAN         (0<<1)
+
+#define G2D_ENDIAN_SRC_BIG_ENDIAN            (1<<0)
+#define G2D_ENDIAN_SRC_LITTLE_ENDIAN         (0<<0)
+
+/* read buffer size */
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_1      (0<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_4      (1<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_8      (2<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_16     (3<<0)
+
+/* Third Operans Select */
+/*
+#define G2D_ROP_REG_OS_PATTERN	             (0<<13)
+#define G2D_ROP_REG_OS_FG_COLOR	             (1<<13)
+#define G2D_ROP_REG_OS_PATTERN_MASK_SELECT   (0<<4)
+#define G2D_ROP_REG_OS_PATTERN_THIRD         (0)
+*/
+#define G2D_THIRD_OP_REG_PATTERN             ((0<<4) | (0))
+#define G2D_THIRD_OP_REG_FG_COLOR            ((1<<4) | (1))
+#define G2D_THIRD_OP_REG_BG_COLOR            ((2<<4) | (2))
+#define G2D_THIRD_OP_REG_NONE                ((3<<4) | (3))
+
+/* Alpha Blending Mode */
+#define G2D_ROP_REG_ABM_NO_BLENDING          (0<<10)
+#define G2D_ROP_REG_ABM_SRC_BITMAP           (1<<10)
+#define G2D_ROP_REG_ABM_REGISTER             (2<<10)
+#define G2D_ROP_REG_ABM_FADING               (4<<10)
+
+/* Raster operation mode */
+#define G2D_ROP_REG_T_OPAQUE_MODE            (0<<9)
+#define G2D_ROP_REG_T_TRANSP_MODE            (1<<9)
+
+#define G2D_ROP_REG_B_BS_MODE_OFF            (0<<8)
+#define G2D_ROP_REG_B_BS_MODE_ON             (1<<8)
+
+/*
+#define G2D_ROP_REG_SRC_ONLY                 (0xf0)
+#define G2D_ROP_REG_3RD_OPRND_ONLY           (0xaa)
+#define G2D_ROP_REG_DST_ONLY                 (0xcc)
+#define G2D_ROP_REG_SRC_OR_DST               (0xfc)
+#define G2D_ROP_REG_SRC_OR_3RD_OPRND         (0xfa)
+#define G2D_ROP_REG_SRC_AND_DST              (0xc0) //(pat==1)? src:dst
+#define G2D_ROP_REG_SRC_AND_3RD_OPRND        (0xa0)
+#define G2D_ROP_REG_SRC_XOR_3RD_OPRND        (0x5a)
+#define G2D_ROP_REG_DST_OR_3RD_OPRND         (0xee)
+*/
+#define G2D_ROP_REG_SRC                      (0xcc)
+#define G2D_ROP_REG_DST                      (0xaa)
+#define G2D_ROP_REG_SRC_AND_DST              (0x88) 
+#define G2D_ROP_REG_SRC_OR_DST               (0xee)
+#define G2D_ROP_REG_3RD_OPRND                (0xf0)
+#define G2D_ROP_REG_SRC_AND_3RD_OPRND        (0xc0)
+#define G2D_ROP_REG_SRC_OR_3RD_OPRND         (0xfc)
+#define G2D_ROP_REG_SRC_XOR_3RD_OPRND        (0x3c)
+#define G2D_ROP_REG_DST_OR_3RD_OPRND         (0xfa)
+
+
+/* stencil control */
+#define G2D_STENCIL_CNTL_REG_STENCIL_ON_ON   (1<<31)
+#define G2D_STENCIL_CNTL_REG_STENCIL_ON_OFF  (0<<31)
+
+#define G2D_STENCIL_CNTL_REG_STENCIL_INVERSE (1<<23)
+#define G2D_STENCIL_CNTL_REG_STENCIL_SWAP    (1<<0)
+
+/*********************************************************************************/
+
+#endif /* __SEC_FIMG2D3X_REGS_H */
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_cache.c b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_cache.c
new file mode 100644
index 0000000..639b3f8
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_cache.c
@@ -0,0 +1,379 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_cache.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d cache control functions.
+ */
+
+#include <linux/kernel.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+#include <asm/io.h>
+#include <linux/sched.h>
+#include <linux/poll.h>
+
+#include "fimg2d.h"
+
+#define L1_ALL_THRESHOLD_SIZE SZ_64K
+#define L2_ALL_THRESHOLD_SIZE SZ_1M
+
+#define L2_CACHE_SKIP_MARK 256*4
+
+void g2d_pagetable_clean(const void *start_addr, unsigned long size, unsigned long pgd)
+{
+	void *l1d_vir, *l1d_phy, *l2d_phy;
+	void *cur_addr, *end_addr;
+	size = ALIGN(size, SZ_1M);
+	cur_addr = (void *)((unsigned long)start_addr & ~(SZ_1M-1));
+	end_addr = cur_addr + size + SZ_1M;
+    
+	l1d_phy = (void *)((pgd & 0xffffc000) | (((u32)(cur_addr) & 0xfff00000)>>18)); 
+	
+	if (l1d_phy) {
+		l1d_vir = phys_to_virt((u32)l1d_phy);
+		dmac_map_area(l1d_vir, (size/SZ_1M)*4, DMA_TO_DEVICE);
+	}
+	
+	while (cur_addr < end_addr) {
+		outer_clean_range((u32)l1d_phy, (u32)l1d_phy + 4);
+
+		if (l1d_phy) {			
+			l2d_phy = (void *)((readl(phys_to_virt((u32)l1d_phy)) & 0xfffffc00) | 
+				(((u32)cur_addr & 0x000ff000) >> 10));
+			if (l2d_phy)
+				dmac_map_area(phys_to_virt((u32)l2d_phy), SZ_1K, DMA_TO_DEVICE);  
+			outer_clean_range((u32)l2d_phy, (u32)l2d_phy + SZ_1K);
+		}
+		cur_addr += SZ_1M; 
+		l1d_phy = (void *)((pgd & 0xffffc000) | (((u32)(cur_addr) & 0xfff00000)>>18));
+	}  
+}
+
+
+static unsigned long virt2phys(unsigned long addr)
+{
+	pgd_t *pgd;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	if(!current->mm) {
+		current->mm = &init_mm;
+	}
+
+	pgd = pgd_offset(current->mm, addr);
+
+	if ((pgd_val(*pgd) & 0x1) != 0x1) {
+		return 0;
+	}
+	
+	pmd = pmd_offset(pgd, addr);
+	pte = pte_offset_map(pmd, addr);
+
+	return (addr & 0xfff) | (pte_val(*pte) & 0xfffff000);
+}
+
+u32 g2d_check_pagetable(void * vaddr, unsigned int size, unsigned long pgd)
+{
+    unsigned int level_one_phy, level_two_phy;
+    unsigned int level_one_value, level_two_value; 
+    
+    for (;;) {
+	level_one_phy = (pgd & 0xffffc000) | (((u32)vaddr & 0xfff00000)>>18);
+	if ((int)phys_to_virt(level_one_phy) < 0xc0000000) {
+		FIMG2D_ERROR("Level1 page table mapping missed, missed address = %p", phys_to_virt(level_one_phy));
+		return G2D_PT_NOTVALID;
+	}
+	level_one_value = readl(phys_to_virt(level_one_phy));
+
+	level_two_phy = (level_one_value & 0xfffffc00) | (((u32)vaddr & 0x000ff000) >> 10);
+	if ((int)phys_to_virt(level_two_phy) < 0xc0000000) {
+		FIMG2D_ERROR("Level2 page table mapping missed, missed address = %p", phys_to_virt(level_two_phy));
+		return G2D_PT_NOTVALID;
+	}
+	level_two_value = readl(phys_to_virt(level_two_phy));
+
+	if (((level_one_value & 0x3) != 0x1) || ((level_two_value & 0x3) != 0x3)) {
+		FIMG2D_DEBUG("Surface memory mapping fail [L1: 0x%x, L2: 0x%x]\n",
+			level_one_value, level_two_value);
+		return G2D_PT_NOTVALID;
+	}
+	if (size == 0) {
+		if  ((level_two_value & 0x08) != 0x08)
+			return G2D_PT_UNCACHED;
+		return G2D_PT_CACHED;
+	}
+    
+	if (size <= PAGE_SIZE) {
+		vaddr += (size-1);
+		size = 0;
+	} else {
+		vaddr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+    }
+}
+
+void g2d_clip_for_src(g2d_rect *src_rect, g2d_rect *dst_rect, g2d_clip *clip, g2d_clip *src_clip)
+{
+	if ((src_rect->w == dst_rect->w) && (src_rect->h == dst_rect->h)) {
+		src_clip->t = src_rect->y + (clip->t - dst_rect->y);
+		src_clip->l = src_rect->x + (clip->l - dst_rect->x);
+		src_clip->b = src_clip->t + (clip->b - clip->t);
+		src_clip->r = src_clip->l + (clip->r - clip->l);
+	} else {
+		src_clip->t = src_rect->y;
+		src_clip->l = src_rect->x;
+		src_clip->b = src_clip->t + src_rect->h;
+		src_clip->r = src_clip->l + src_rect->w;
+	}
+}
+
+void g2d_mem_inner_cache(g2d_params * params)
+{
+	void *src_addr, *dst_addr;
+	unsigned long src_size, dst_size;
+	g2d_clip clip_src;
+	g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+	src_addr = (void *)GET_START_ADDR_C(params->src_rect, clip_src); 
+	dst_addr = (void *)GET_START_ADDR_C(params->dst_rect, params->clip);
+	src_size = (unsigned long)GET_RECT_SIZE_C(params->src_rect, clip_src); 
+	dst_size = (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	if((src_size + dst_size) < L1_ALL_THRESHOLD_SIZE) {
+		dmac_map_area(src_addr, src_size, DMA_TO_DEVICE);
+		dmac_flush_range(dst_addr, dst_addr + dst_size);
+	} else {
+		flush_all_cpu_caches();
+	}
+}
+
+void g2d_mem_outer_cache(struct g2d_global *g2d_dev, g2d_params * params, int *need_dst_clean)
+{
+ 	unsigned long start_paddr, end_paddr;
+	unsigned long cur_addr, end_addr;
+	unsigned long width_bytes;
+	unsigned long stride;
+	unsigned long src_size, dst_size;
+
+#if 0
+	if (((GET_RECT_SIZE(params->src_rect) + GET_RECT_SIZE(params->dst_rect)) > L2_ALL_THRESHOLD_SIZE)
+		&& ((*need_dst_clean == true) || ( GET_RECT_SIZE(params->src_rect) > 384*640*4))) {
+		outer_flush_all();
+		*need_dst_clean = true;
+		return;
+	}	
+#endif
+
+	g2d_clip clip_src;
+	g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+	src_size = GET_RECT_SIZE_C(params->src_rect, clip_src);
+	dst_size = GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	if ((src_size + dst_size) >= L2_ALL_THRESHOLD_SIZE) {
+		outer_flush_all();
+		*need_dst_clean = true;
+		return;
+	}
+
+	if((GET_SPARE_BYTES(params->src_rect) < L2_CACHE_SKIP_MARK) 
+		|| ((params->src_rect.w * params->src_rect.bytes_per_pixel) >= PAGE_SIZE)) {
+		g2d_mem_outer_cache_clean((void *)GET_START_ADDR_C(params->src_rect, clip_src), 
+			(unsigned int)GET_RECT_SIZE_C(params->src_rect, clip_src));
+	} else {
+		stride = GET_STRIDE(params->src_rect);
+		width_bytes = params->src_rect.w * params->src_rect.bytes_per_pixel;
+		cur_addr = (unsigned long)GET_REAL_START_ADDR_C(params->src_rect, clip_src);
+		end_addr = (unsigned long)GET_REAL_END_ADDR_C(params->src_rect, clip_src);
+
+		while (cur_addr <= end_addr) {
+			start_paddr = virt2phys((unsigned long)cur_addr);
+			end_paddr = virt2phys((unsigned long)cur_addr + width_bytes);
+			
+			if (((end_paddr - start_paddr) > 0) && ((end_paddr -start_paddr) < PAGE_SIZE)) {
+				outer_clean_range(start_paddr, end_paddr);
+			} else {
+				outer_clean_range(start_paddr, ((start_paddr + PAGE_SIZE) & PAGE_MASK) - 1);
+				outer_clean_range(end_paddr & PAGE_MASK, end_paddr);			
+			}
+			cur_addr += stride;
+		}
+	}
+
+	if (*need_dst_clean) {
+		if ((GET_SPARE_BYTES(params->dst_rect) < L2_CACHE_SKIP_MARK)
+			|| ((params->dst_rect.w * params->src_rect.bytes_per_pixel) >= PAGE_SIZE)) {		
+			g2d_mem_outer_cache_flush((void *)GET_START_ADDR_C(params->dst_rect, params->clip), 
+				(unsigned int)GET_RECT_SIZE_C(params->dst_rect, params->clip));
+		} else {
+			stride = GET_STRIDE(params->dst_rect);
+			width_bytes = (params->clip.r - params->clip.l) * params->dst_rect.bytes_per_pixel;
+			
+			cur_addr = (unsigned long)GET_REAL_START_ADDR_C(params->dst_rect, params->clip);
+			end_addr = (unsigned long)GET_REAL_END_ADDR_C(params->dst_rect, params->clip);
+
+			while (cur_addr <= end_addr) {
+				start_paddr = virt2phys((unsigned long)cur_addr);
+				end_paddr = virt2phys((unsigned long)cur_addr + width_bytes);
+				
+				if (((end_paddr - start_paddr) > 0) && ((end_paddr -start_paddr) < PAGE_SIZE)) {
+					outer_flush_range(start_paddr, end_paddr);
+				} else {
+					outer_flush_range(start_paddr, ((start_paddr + PAGE_SIZE) & PAGE_MASK) - 1);
+					outer_flush_range(end_paddr & PAGE_MASK, end_paddr);
+				}
+				cur_addr += stride;
+			}	
+		}
+	}
+}
+
+void g2d_mem_cache_oneshot(void *src_addr,  void *dst_addr, unsigned long src_size, unsigned long dst_size)
+{
+ 	unsigned long paddr;
+        	void *cur_addr, *end_addr;
+	unsigned long full_size;
+
+	full_size = src_size + dst_size;
+
+	if(full_size < L1_ALL_THRESHOLD_SIZE)
+		dmac_map_area(src_addr, src_size, DMA_TO_DEVICE);
+	else
+		flush_all_cpu_caches();
+
+	if(full_size > L2_ALL_THRESHOLD_SIZE) {
+		outer_flush_all();
+		return;
+	}
+
+	cur_addr = (void *)((unsigned long)src_addr & PAGE_MASK);
+	src_size = PAGE_ALIGN(src_size);
+	end_addr = cur_addr + src_size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}   
+
+	if(full_size < L1_ALL_THRESHOLD_SIZE)
+		dmac_flush_range(dst_addr, dst_addr + dst_size);
+
+	cur_addr = (void *)((unsigned long)dst_addr & PAGE_MASK);
+	dst_size = PAGE_ALIGN(dst_size);
+	end_addr = cur_addr + dst_size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_flush_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+u32 g2d_mem_cache_op(unsigned int cmd, void *addr, unsigned int size)
+{
+	switch(cmd) {
+	case G2D_DMA_CACHE_CLEAN :
+		g2d_mem_outer_cache_clean((void *)addr, size);
+		break;	
+	case G2D_DMA_CACHE_FLUSH :
+		g2d_mem_outer_cache_flush((void *)addr, size);
+		break;
+	default :
+		return false;
+		break;		
+	}	
+
+	return true;
+}
+
+void g2d_mem_outer_cache_flush(void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	size = PAGE_ALIGN(size);
+	end_addr = cur_addr + size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_flush_range(paddr, paddr + PAGE_SIZE);
+		}
+	cur_addr += PAGE_SIZE;
+	}   
+}
+
+void g2d_mem_outer_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	size = PAGE_ALIGN(size);
+	end_addr = cur_addr + size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+void g2d_mem_outer_cache_inv(g2d_params *params)
+{
+ 	unsigned long start_paddr, end_paddr;
+	unsigned long cur_addr, end_addr;
+	unsigned long stride;
+	
+	stride = GET_STRIDE(params->dst_rect);
+	cur_addr = (unsigned long)GET_START_ADDR_C(params->dst_rect, params->clip);
+	end_addr = cur_addr + (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	start_paddr = virt2phys((unsigned long)cur_addr);
+	outer_inv_range(start_paddr, (start_paddr & PAGE_MASK) + (PAGE_SIZE - 1));
+	cur_addr = ((unsigned long)cur_addr & PAGE_MASK) + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		start_paddr = virt2phys((unsigned long)cur_addr);		
+		if ((cur_addr + PAGE_SIZE) > end_addr) {		
+			end_paddr = virt2phys((unsigned long)end_addr);
+			outer_inv_range(start_paddr, end_paddr);
+			break;
+		}
+
+		if (start_paddr) {
+			outer_inv_range(start_paddr, start_paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+int g2d_check_need_dst_cache_clean(g2d_params * params)
+{
+	unsigned long cur_addr, end_addr;
+	cur_addr = (unsigned long)GET_START_ADDR_C(params->dst_rect, params->clip);
+	end_addr = cur_addr + (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+	
+	if ((params->src_rect.color_format == G2D_RGB_565) &&
+		(params->flag.alpha_val == G2D_ALPHA_BLENDING_OPAQUE) &&
+		(params->dst_rect.full_w == (params->clip.r - params->clip.l)) &&
+		(cur_addr % 32 == 0) && (end_addr % 32 == 0))   {
+		return false;
+	}
+	
+	return true;
+}
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_core.c b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_core.c
new file mode 100644
index 0000000..40508d5
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_core.c
@@ -0,0 +1,318 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d_core.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d core functions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <plat/s5p-sysmmu.h>
+#include <linux/sched.h>
+
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+#include <mach/media.h>
+#include <plat/media.h>
+#endif
+
+#include "fimg2d.h"
+
+int g2d_clk_enable(struct g2d_global *g2d_dev)
+{
+	if(!atomic_read(&g2d_dev->clk_enable_flag)) {
+		clk_enable(g2d_dev->clock);
+		atomic_set(&g2d_dev->clk_enable_flag, 1);
+		return 0;
+	}
+	return -1;
+}
+
+int g2d_clk_disable(struct g2d_global *g2d_dev)
+{
+	if(atomic_read(&g2d_dev->clk_enable_flag)) {
+		if(atomic_read(&g2d_dev->in_use) == 0) {
+			clk_disable(g2d_dev->clock);
+			atomic_set(&g2d_dev->clk_enable_flag, 0);
+			return 0;
+		} 
+	}
+	return -1;
+}
+
+void g2d_sysmmu_on(struct g2d_global *g2d_dev)
+{
+	g2d_clk_enable(g2d_dev);
+	s5p_sysmmu_enable(g2d_dev->dev,
+			(unsigned long)virt_to_phys((void *)init_mm.pgd));
+	g2d_clk_disable(g2d_dev);
+}
+
+void g2d_sysmmu_off(struct g2d_global *g2d_dev)
+{
+	g2d_clk_enable(g2d_dev);
+	s5p_sysmmu_disable(g2d_dev->dev);
+	g2d_clk_disable(g2d_dev);
+}
+
+void g2d_fail_debug(g2d_params *params)
+{
+	FIMG2D_ERROR("src : %d, %d, %d, %d / %d, %d / 0x%x, %d, 0x%x)\n",
+			params->src_rect.x,
+			params->src_rect.y,
+			params->src_rect.w,
+			params->src_rect.h,
+			params->src_rect.full_w,
+			params->src_rect.full_h,
+			params->src_rect.color_format,
+			params->src_rect.bytes_per_pixel,
+			(u32)params->src_rect.addr);
+	FIMG2D_ERROR("dst : %d, %d, %d, %d / %d, %d / 0x%x, %d, 0x%x)\n",
+			params->dst_rect.x,
+			params->dst_rect.y,
+			params->dst_rect.w,
+			params->dst_rect.h,
+			params->dst_rect.full_w,
+			params->dst_rect.full_h,
+			params->dst_rect.color_format,
+			params->dst_rect.bytes_per_pixel,
+			(u32)params->dst_rect.addr);
+	FIMG2D_ERROR("clip: %d, %d, %d, %d\n",
+			params->clip.t,
+			params->clip.b,
+			params->clip.l,
+			params->clip.r);
+	FIMG2D_ERROR("flag: %d, %d, %d, %d / %d, %d, %d, %d / %d, %d, %d, %d\n",
+			params->flag.rotate_val,
+			params->flag.alpha_val,
+			params->flag.blue_screen_mode,
+			params->flag.color_key_val,
+			params->flag.color_switch_val,
+			params->flag.src_color,
+			params->flag.third_op_mode,
+			params->flag.rop_mode,
+			params->flag.mask_mode,
+			params->flag.render_mode,
+			params->flag.potterduff_mode,
+			params->flag.memory_type);
+}
+
+int g2d_init_regs(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	u32 blt_cmd = 0;
+
+	g2d_rect * src_rect = &params->src_rect;
+	g2d_rect * dst_rect = &params->dst_rect;
+	g2d_clip * clip     = &params->clip;
+	g2d_flag * flag     = &params->flag;
+
+	if (g2d_check_params(params) < 0)
+		return -1;
+
+	g2d_reset(g2d_dev);
+
+	/* source image */	
+	blt_cmd |= g2d_set_src_img(g2d_dev, src_rect, flag);    
+
+	/* destination image */		
+	blt_cmd |= g2d_set_dst_img(g2d_dev, dst_rect);
+
+	/* rotation */
+	blt_cmd |= g2d_set_rotation(g2d_dev, flag);
+
+	/* clipping */
+	blt_cmd |= g2d_set_clip_win(g2d_dev, clip);
+
+	/* color key */
+	blt_cmd |= g2d_set_color_key(g2d_dev, flag);
+
+	/* pattern */	
+	blt_cmd |= g2d_set_pattern(g2d_dev, src_rect, flag);
+
+	/* rop & alpha blending */
+	blt_cmd |= g2d_set_alpha(g2d_dev, flag);
+
+	/* command */
+	g2d_set_bitblt_cmd(g2d_dev, src_rect, dst_rect, clip, blt_cmd);
+
+	return 0;
+}
+
+int g2d_check_overlap(g2d_rect src_rect, g2d_rect dst_rect, g2d_clip clip)
+{
+	unsigned int src_start_addr;
+	unsigned int src_end_addr;
+	unsigned int dst_start_addr;
+	unsigned int dst_end_addr;
+
+	src_start_addr = (unsigned int)GET_START_ADDR(src_rect);
+	src_end_addr = src_start_addr + (unsigned int)GET_RECT_SIZE(src_rect);
+	dst_start_addr = (unsigned int)GET_START_ADDR_C(dst_rect, clip);
+	dst_end_addr = dst_start_addr + (unsigned int)GET_RECT_SIZE_C(dst_rect, clip);
+
+	if ((dst_start_addr >= src_start_addr) && (dst_start_addr <= src_end_addr))
+		return true;
+	if ((dst_end_addr >= src_start_addr) && (dst_end_addr <= src_end_addr))
+		return true;
+	if ((src_start_addr >= dst_start_addr) && (src_end_addr <= dst_end_addr))
+		return true;
+
+	return false;
+}
+
+int g2d_do_blit(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	unsigned long 	pgd;
+	int need_dst_clean = true;
+
+	if ((params->src_rect.addr == NULL) 
+		|| (params->dst_rect.addr == NULL)) {
+		FIMG2D_ERROR("error : addr Null\n");
+		return false;
+	}		
+
+	if (params->flag.memory_type == G2D_MEMORY_KERNEL) {
+		params->src_rect.addr = (unsigned char *)phys_to_virt((unsigned long)params->src_rect.addr);
+		params->dst_rect.addr = (unsigned char *)phys_to_virt((unsigned long)params->dst_rect.addr);
+		pgd = (unsigned long)init_mm.pgd;
+	} else {
+		pgd = (unsigned long)current->mm->pgd;
+	}
+
+	if (params->flag.memory_type == G2D_MEMORY_USER)
+	{
+		g2d_clip clip_src;
+		g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+		if (g2d_check_overlap(params->src_rect, params->dst_rect, params->clip))
+			return false;
+
+		g2d_dev->src_attribute =
+			g2d_check_pagetable((unsigned char *)GET_START_ADDR(params->src_rect),
+				(unsigned int)GET_RECT_SIZE(params->src_rect) + 8,
+					(u32)virt_to_phys((void *)pgd));
+		if (g2d_dev->src_attribute == G2D_PT_NOTVALID) {
+			FIMG2D_DEBUG("Src is not in valid pagetable\n");
+			return false;
+		}
+
+		g2d_dev->dst_attribute = 
+			g2d_check_pagetable((unsigned char *)GET_START_ADDR_C(params->dst_rect, params->clip),
+				(unsigned int)GET_RECT_SIZE_C(params->dst_rect, params->clip),
+					(u32)virt_to_phys((void *)pgd));
+		if (g2d_dev->dst_attribute == G2D_PT_NOTVALID) {
+			FIMG2D_DEBUG("Dst is not in valid pagetable\n");
+			return false;
+		}
+
+		g2d_pagetable_clean((unsigned char *)GET_START_ADDR(params->src_rect),
+				(u32)GET_RECT_SIZE(params->src_rect) + 8,
+				(u32)virt_to_phys((void *)pgd));
+		g2d_pagetable_clean((unsigned char *)GET_START_ADDR_C(params->dst_rect, params->clip),
+				(u32)GET_RECT_SIZE_C(params->dst_rect, params->clip),
+				(u32)virt_to_phys((void *)pgd));
+
+		if (params->flag.render_mode & G2D_CACHE_OP) {
+			/*g2d_mem_cache_oneshot((void *)GET_START_ADDR(params->src_rect), 
+				(void *)GET_START_ADDR(params->dst_rect),
+				(unsigned int)GET_REAL_SIZE(params->src_rect), 
+				(unsigned int)GET_REAL_SIZE(params->dst_rect));*/
+		//	need_dst_clean = g2d_check_need_dst_cache_clean(params);
+			g2d_mem_inner_cache(params);
+			g2d_mem_outer_cache(g2d_dev, params, &need_dst_clean);
+		}
+	}
+
+	s5p_sysmmu_set_tablebase_pgd(g2d_dev->dev,
+					(u32)virt_to_phys((void *)pgd));
+
+	if(g2d_init_regs(g2d_dev, params) < 0) {
+		return false;
+	}
+
+	/* Do bitblit */
+	g2d_start_bitblt(g2d_dev, params);
+
+	if (!need_dst_clean)
+		g2d_mem_outer_cache_inv(params);
+
+	return true;
+}
+
+int g2d_wait_for_finish(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+		FIMG2D_ERROR("error : sysmmu_faulted early\n");
+		FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+		g2d_fail_debug(params);
+		atomic_set(&g2d_dev->is_mmu_faulted, 0);
+		return false;
+	}
+
+	if (params->flag.render_mode & G2D_POLLING) {
+		g2d_check_fifo_state_wait(g2d_dev);
+	} else {
+		if(wait_event_interruptible_timeout(g2d_dev->waitq,
+					g2d_dev->irq_handled == 1,
+					msecs_to_jiffies(G2D_TIMEOUT)) == 0) {
+			if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+				FIMG2D_ERROR("error : sysmmu_faulted\n");
+				FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+			} else {
+				g2d_reset(g2d_dev);
+				FIMG2D_ERROR("error : waiting for interrupt is timeout\n");
+			}
+			atomic_set(&g2d_dev->is_mmu_faulted, 0);
+			g2d_fail_debug(params);
+			return false;
+		} else if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+			FIMG2D_ERROR("error : sysmmu_faulted but auto recoveried\n");
+			FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+			g2d_fail_debug(params);
+			atomic_set(&g2d_dev->is_mmu_faulted, 0);
+			return false;
+		}
+	}
+	return true;
+}
+
+int g2d_init_mem(struct device *dev, unsigned int *base, unsigned int *size)
+{
+#ifdef CONFIG_S5P_MEM_CMA
+	struct cma_info mem_info;
+	int err;
+	char cma_name[8];
+#endif
+
+#ifdef CONFIG_S5P_MEM_CMA
+	/* CMA */
+	sprintf(cma_name, "fimg2d");
+	err = cma_info(&mem_info, dev, 0);
+	FIMG2D_DEBUG("[cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		FIMG2D_ERROR("%s: get cma info failed\n", __func__);
+		return -1;
+	}
+	*size = mem_info.total_size;
+	*base = (dma_addr_t)cma_alloc
+		(dev, cma_name, (size_t)(*size), 0);
+
+	FIMG2D_DEBUG("size = 0x%x\n", *size);
+	FIMG2D_DEBUG("*base phys= 0x%x\n", *base);
+	FIMG2D_DEBUG("*base virt = 0x%x\n", (u32)phys_to_virt(*base));
+
+#else
+	*base = s5p_get_media_memory_bank(S5P_MDEV_FIMG2D, 0);
+#endif
+	return 0;
+}
+
diff --git a/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_dev.c b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_dev.c
new file mode 100644
index 0000000..5ccde4a
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x-exynos4/fimg2d_dev.c
@@ -0,0 +1,609 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_dev.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d driver.
+ */
+
+#include <linux/init.h>
+
+#include <linux/moduleparam.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include <asm/uaccess.h>
+#include <linux/miscdevice.h>
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/init.h>
+#include <linux/semaphore.h>
+
+#include <asm/io.h>
+
+#include <mach/cpufreq.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+#include <linux/pm_runtime.h>
+#endif 
+
+#include "fimg2d.h"
+#include "fimg2d3x_regs.h"
+
+#include <linux/smp.h>
+
+struct g2d_global *g2d_dev;
+
+int g2d_sysmmu_fault(unsigned int faulted_addr, unsigned int pt_base)
+{
+	g2d_reset(g2d_dev);
+
+	atomic_set(&g2d_dev->is_mmu_faulted, 1);
+
+	g2d_dev->faulted_addr = faulted_addr;
+
+	wake_up_interruptible(&g2d_dev->waitq);
+
+	return 0;
+}
+
+
+irqreturn_t g2d_irq(int irq, void *dev_id)
+{
+	g2d_set_int_finish(g2d_dev);
+
+	g2d_dev->irq_handled = 1;
+
+	wake_up_interruptible(&g2d_dev->waitq);
+
+	atomic_set(&g2d_dev->in_use, 0);
+
+	return IRQ_HANDLED;
+}
+
+
+static int g2d_open(struct inode *inode, struct file *file)
+{
+	atomic_inc(&g2d_dev->num_of_object);
+
+	FIMG2D_DEBUG("Context Opened %d\n", atomic_read(&g2d_dev->num_of_object));
+
+	return 0;
+}
+
+
+static int g2d_release(struct inode *inode, struct file *file)
+{
+	atomic_dec(&g2d_dev->num_of_object);
+
+	FIMG2D_DEBUG("Context Closed %d\n", atomic_read(&g2d_dev->num_of_object));
+
+	return 0;
+}
+
+static int g2d_mmap(struct file* filp, struct vm_area_struct *vma) 
+{
+	return 0;
+}
+
+
+static long g2d_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	g2d_params params;
+	int ret = -1;
+
+	struct g2d_dma_info dma_info;
+
+	switch(cmd) {
+	case G2D_GET_MEMORY :
+		ret =  copy_to_user((unsigned int *)arg,
+			&(g2d_dev->reserved_mem.base), sizeof(g2d_dev->reserved_mem.base));
+		if (ret) {
+			FIMG2D_ERROR("error : copy_to_user\n");
+			return -EINVAL;
+		}
+		return 0;
+
+	case G2D_GET_MEMORY_SIZE :
+		ret =  copy_to_user((unsigned int *)arg,
+			&(g2d_dev->reserved_mem.size), sizeof(g2d_dev->reserved_mem.size));
+		if (ret) {
+			FIMG2D_ERROR("error : copy_to_user\n");
+			return -EINVAL;
+		}
+		return 0;
+
+	case G2D_DMA_CACHE_CLEAN :
+	case G2D_DMA_CACHE_FLUSH :
+		mutex_lock(&g2d_dev->lock);
+		ret = copy_from_user(&dma_info, (struct g2d_dma_info *)arg, sizeof(dma_info));
+
+		if (ret) {
+			FIMG2D_ERROR("error : copy_from_user\n");
+			mutex_unlock(&g2d_dev->lock);
+			return -EINVAL;
+		}
+
+		if (dma_info.addr == 0) {
+			FIMG2D_ERROR("addr Null Error!!!\n");                
+			mutex_unlock(&g2d_dev->lock);
+			return -EINVAL;
+		}
+
+		g2d_mem_cache_op(cmd, (void *)dma_info.addr, dma_info.size);
+		mutex_unlock(&g2d_dev->lock);
+		return 0;
+
+	case G2D_SYNC :
+		g2d_check_fifo_state_wait(g2d_dev);
+		ret = 0;
+		goto g2d_ioctl_done;
+
+	case G2D_RESET :
+		g2d_reset(g2d_dev);
+		FIMG2D_ERROR("G2D TimeOut Error\n");
+		ret = 0;
+		goto g2d_ioctl_done;
+		
+	case G2D_BLIT:
+		if  (atomic_read(&g2d_dev->ready_to_run) == 0)
+			goto g2d_ioctl_done2;
+		
+		mutex_lock(&g2d_dev->lock);
+		
+		g2d_clk_enable(g2d_dev);
+
+		if (copy_from_user(&params, (struct g2d_params *)arg, sizeof(g2d_params))) {
+			FIMG2D_ERROR("error : copy_from_user\n");
+			goto g2d_ioctl_done;
+		}
+
+		atomic_set(&g2d_dev->in_use, 1);
+		if (atomic_read(&g2d_dev->ready_to_run) == 0)
+			goto g2d_ioctl_done;
+
+		if (params.flag.memory_type == G2D_MEMORY_USER)
+			down_write(&page_alloc_slow_rwsem);
+
+		g2d_dev->irq_handled = 0;
+		if (!g2d_do_blit(g2d_dev, &params)) {
+			g2d_dev->irq_handled = 1;
+			if (params.flag.memory_type == G2D_MEMORY_USER)
+				up_write(&page_alloc_slow_rwsem);
+			goto g2d_ioctl_done;
+		}
+
+		if(!(file->f_flags & O_NONBLOCK)) {
+			if (!g2d_wait_for_finish(g2d_dev, &params)) {
+				if (params.flag.memory_type == G2D_MEMORY_USER)
+					up_write(&page_alloc_slow_rwsem);
+				goto g2d_ioctl_done;
+			}
+		}
+
+		if (params.flag.memory_type == G2D_MEMORY_USER)
+			up_write(&page_alloc_slow_rwsem);
+		ret = 0;
+
+		break;
+	default :
+		goto g2d_ioctl_done2;
+		break;
+	}
+
+g2d_ioctl_done :
+
+	g2d_clk_disable(g2d_dev);
+
+	mutex_unlock(&g2d_dev->lock);
+
+	atomic_set(&g2d_dev->in_use, 0);
+
+g2d_ioctl_done2 :
+
+	return ret;
+}
+
+static unsigned int g2d_poll(struct file *file, poll_table *wait)
+{
+	unsigned int mask = 0;
+
+	if (atomic_read(&g2d_dev->in_use) == 0) {
+		mask = POLLOUT | POLLWRNORM;
+		g2d_clk_disable(g2d_dev);
+		
+		mutex_unlock(&g2d_dev->lock);
+
+	} else {
+		poll_wait(file, &g2d_dev->waitq, wait);
+
+		if(atomic_read(&g2d_dev->in_use) == 0) {
+			mask = POLLOUT | POLLWRNORM;
+			g2d_clk_disable(g2d_dev);
+			
+			mutex_unlock(&g2d_dev->lock);
+		}
+	}
+	
+	return mask;
+}
+
+static struct file_operations fimg2d_fops = {
+	.owner 		= THIS_MODULE,
+	.open 		= g2d_open,
+	.release 	= g2d_release,
+	.mmap 		= g2d_mmap,
+	.unlocked_ioctl = g2d_ioctl,
+	.poll		= g2d_poll,
+};
+
+
+static struct miscdevice fimg2d_dev = {
+	.minor		= G2D_MINOR,
+	.name		= "fimg2d",
+	.fops		= &fimg2d_fops,
+};
+
+static int g2d_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+	struct clk *parent;
+	struct clk *sclk;
+	
+	FIMG2D_DEBUG("start probe : name=%s num=%d res[0].start=0x%x res[1].start=0x%x\n",
+	        			pdev->name, pdev->num_resources, 
+	        			pdev->resource[0].start, pdev->resource[1].start);
+
+	/* alloc g2d global */
+	g2d_dev = kzalloc(sizeof(*g2d_dev), GFP_KERNEL);
+	if (!g2d_dev) {
+		FIMG2D_ERROR( "not enough memory\n");
+		ret = -ENOENT;
+		goto probe_out;
+	}
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* to use the runtime PM helper functions */
+	pm_runtime_enable(&pdev->dev);
+	/* enable the power domain */
+	pm_runtime_get_sync(&pdev->dev);
+#endif
+
+	/* get the memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if(res == NULL) {
+		FIMG2D_ERROR("failed to get memory region resouce\n");
+		ret = -ENOENT;
+		goto err_get_res;
+	}
+
+	/* request momory region */
+	g2d_dev->mem = request_mem_region(res->start, 
+					          res->end - res->start + 1, 
+					          pdev->name);
+	if(g2d_dev->mem == NULL) {
+		FIMG2D_ERROR("failed to reserve memory region\n");
+		ret = -ENOENT;
+		goto err_mem_req;
+	}
+	
+	/* ioremap */
+	g2d_dev->base = ioremap(g2d_dev->mem->start, 
+				g2d_dev->mem->end - res->start + 1);
+	if(g2d_dev->base == NULL) {
+		FIMG2D_ERROR("failed ioremap\n");
+		ret = -ENOENT;
+		goto err_mem_map;
+	}
+
+	/* get irq */
+	g2d_dev->irq_num = platform_get_irq(pdev, 0);
+	if(g2d_dev->irq_num <= 0) {
+		FIMG2D_ERROR("failed to get irq resouce\n");
+		ret = -ENOENT;
+		goto err_irq_req;
+	}
+
+	/* blocking I/O */
+	init_waitqueue_head(&g2d_dev->waitq);
+
+	/* request irq */
+	ret = request_irq(g2d_dev->irq_num, g2d_irq, 
+			IRQF_DISABLED, pdev->name, NULL);
+	if (ret) {
+		FIMG2D_ERROR("request_irq(g2d) failed.\n");
+		ret = -ENOENT;
+		goto err_irq_req;
+	}
+
+	/* clock domain setting*/
+	parent = clk_get(&pdev->dev, "mout_mpll");
+	if (IS_ERR(parent)) {
+		FIMG2D_ERROR("failed to get parent clock\n");
+		ret = -ENOENT;
+		goto err_clk_get1;
+	}
+
+	sclk = clk_get(&pdev->dev, "sclk_fimg2d");
+	if (IS_ERR(sclk)) {
+		FIMG2D_ERROR("failed to get sclk_g2d clock\n");
+		ret = -ENOENT;
+		goto err_clk_get2;
+	}
+
+	clk_set_parent(sclk, parent);
+	clk_set_rate(sclk, 267 * MHZ);	/* 266 Mhz */
+
+	/* clock for gating  */
+	g2d_dev->clock = clk_get(&pdev->dev, "fimg2d");
+	if (IS_ERR(g2d_dev->clock)) {
+		FIMG2D_ERROR("failed to get clock clock\n");
+		ret = -ENOENT;
+		goto err_clk_get3;
+	}
+
+	ret = g2d_init_mem(&pdev->dev, &g2d_dev->reserved_mem.base, &g2d_dev->reserved_mem.size);
+
+	if (ret != 0) {
+		FIMG2D_ERROR("failed to init. fimg2d mem");
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	/* atomic init */
+	atomic_set(&g2d_dev->in_use, 0);
+	atomic_set(&g2d_dev->num_of_object, 0);
+	atomic_set(&g2d_dev->is_mmu_faulted, 0);
+	g2d_dev->faulted_addr = 0;
+
+	/* misc register */
+	ret = misc_register(&fimg2d_dev);
+	if (ret) {
+		FIMG2D_ERROR("cannot register miscdev on minor=%d (%d)\n",
+			G2D_MINOR, ret);
+		ret = -ENOMEM;
+		goto err_misc_reg;
+	}
+
+	mutex_init(&g2d_dev->lock);
+
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+	g2d_dev->early_suspend.suspend = g2d_early_suspend;
+	g2d_dev->early_suspend.resume = g2d_late_resume;
+	g2d_dev->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+	register_early_suspend(&g2d_dev->early_suspend);
+#endif
+
+	g2d_dev->dev = &pdev->dev;
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+	g2d_sysmmu_on(g2d_dev);
+
+	FIMG2D_DEBUG("g2d_probe ok!\n");
+
+	return 0;
+
+err_misc_reg:
+err_mem:
+	clk_put(g2d_dev->clock);
+	g2d_dev->clock = NULL;	
+err_clk_get3:
+	clk_put(sclk);
+err_clk_get2:
+	clk_put(parent);
+err_clk_get1:
+	free_irq(g2d_dev->irq_num, NULL);
+err_irq_req:
+	iounmap(g2d_dev->base);
+err_mem_map:
+	release_resource(g2d_dev->mem);
+	kfree(g2d_dev->mem);
+err_mem_req:	
+err_get_res:
+	kfree(g2d_dev);
+probe_out:
+	FIMG2D_ERROR("g2d: sec_g2d_probe fail!\n");
+	return ret;
+}
+
+
+static int g2d_remove(struct platform_device *dev)
+{
+	FIMG2D_DEBUG("g2d_remove called !\n");
+
+	free_irq(g2d_dev->irq_num, NULL);
+
+	if (g2d_dev->mem != NULL) {   
+		FIMG2D_INFO("releasing resource\n");
+		iounmap(g2d_dev->base);
+		release_resource(g2d_dev->mem);
+		kfree(g2d_dev->mem);
+	}
+
+	misc_deregister(&fimg2d_dev);
+
+	atomic_set(&g2d_dev->in_use, 0);
+	atomic_set(&g2d_dev->num_of_object, 0);
+
+	g2d_clk_disable(g2d_dev);
+
+	if (g2d_dev->clock) {
+		clk_put(g2d_dev->clock);
+		g2d_dev->clock = NULL;
+	}
+
+	mutex_destroy(&g2d_dev->lock);
+	
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+	unregister_early_suspend(&g2d_dev->early_suspend);
+#endif
+
+	kfree(g2d_dev);
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(&dev->dev);
+	pm_runtime_disable(&dev->dev);
+#endif
+
+	FIMG2D_DEBUG("g2d_remove ok!\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+void g2d_early_suspend(struct early_suspend *h)
+{
+	atomic_set(&g2d_dev->ready_to_run, 0);
+
+	/* wait until G2D running is finished */
+	while(1) {
+		if (!atomic_read(&g2d_dev->in_use))
+			break;
+		
+		msleep_interruptible(2);
+	}
+	
+	g2d_sysmmu_off(g2d_dev);
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(g2d_dev->dev);
+#endif
+}
+
+void g2d_late_resume(struct early_suspend *h)
+{
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* enable the power domain */
+	pm_runtime_get_sync(g2d_dev->dev);
+#endif
+
+	g2d_sysmmu_on(g2d_dev);
+
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+}
+#endif
+
+#if !defined(CONFIG_HAS_EARLYSUSPEND)
+static int g2d_suspend(struct platform_device *dev, pm_message_t state)
+{
+	atomic_set(&g2d_dev->ready_to_run, 0);
+
+	/* wait until G2D running is finished */
+	while(1) {
+		if (!atomic_read(&g2d_dev->in_use))
+			break;
+		
+		msleep_interruptible(2);
+	}
+	
+	g2d_sysmmu_off(g2d_dev);
+	
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(g2d_dev->dev);
+#endif	
+
+	return 0;
+}
+static int g2d_resume(struct platform_device *pdev)
+{
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* enable the power domain */
+	pm_runtime_get_sync(g2d_dev->dev);
+#endif
+
+	g2d_sysmmu_on(g2d_dev);
+
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+static int g2d_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int g2d_runtime_resume(struct device *dev)
+{
+	return 0;
+}
+
+static const struct dev_pm_ops g2d_pm_ops = {
+	.runtime_suspend = g2d_runtime_suspend,
+	.runtime_resume = g2d_runtime_resume,
+};
+#endif
+
+
+static struct platform_driver fimg2d_driver = {
+	.probe		= g2d_probe,
+	.remove		= g2d_remove,
+#if !defined(CONFIG_HAS_EARLYSUSPEND)
+	.suspend	= g2d_suspend,
+	.resume		= g2d_resume,
+#endif
+	.driver		= {
+				.owner	= THIS_MODULE,
+				.name	= "s5p-fimg2d",
+#if defined(CONFIG_EXYNOS_DEV_PD)
+				.pm	= &g2d_pm_ops,
+#endif
+			},
+};
+
+int __init g2d_init(void)
+{
+ 	if(platform_driver_register(&fimg2d_driver)!=0) {
+   		FIMG2D_ERROR("platform device register Failed \n");
+   		return -1;
+  	}
+
+	FIMG2D_DEBUG("ok!\n");
+
+	return 0;
+}
+
+void  g2d_exit(void)
+{
+	platform_driver_unregister(&fimg2d_driver);
+
+	FIMG2D_DEBUG("ok!\n");
+}
+
+module_init(g2d_init);
+module_exit(g2d_exit);
+
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("SEC G2D Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimg2d3x/Kconfig b/drivers/media/video/samsung/fimg2d3x/Kconfig
new file mode 100644
index 0000000..dccbc16
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/Kconfig
@@ -0,0 +1,22 @@
+# drivers/media/video/samsung/fimg2d3x/Kconfig
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+config VIDEO_FIMG2D3X
+	bool "Samsung Graphics 2D Driver"
+	select VIDEO_FIMG2D
+	depends on VIDEO_SAMSUNG && CPU_EXYNOS4210
+	default n
+	---help---
+	  This is a graphics 2D (FIMG2D 3.x) driver for Samsung ARM based SoC.
+
+config VIDEO_FIMG2D3X_DEBUG
+	bool "Enables FIMG2D debug messages"
+	depends on VIDEO_FIMG2D3X
+	default n
+	---help---
+	  This enables FIMG2D driver debug messages.
+
diff --git a/drivers/media/video/samsung/fimg2d3x/Makefile b/drivers/media/video/samsung/fimg2d3x/Makefile
new file mode 100644
index 0000000..a24f530
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/Makefile
@@ -0,0 +1,17 @@
+# drivers/media/video/samsung/fimg2d3x/Makefile
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+obj-$(CONFIG_VIDEO_FIMG2D3X) += fimg2d_dev.o fimg2d_cache.o fimg2d3x_regs.o fimg2d_core.o
+
+ifeq ($(CONFIG_VIDEO_FIMG2D3X_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d.h b/drivers/media/video/samsung/fimg2d3x/fimg2d.h
new file mode 100644
index 0000000..2c2c07b
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d.h
@@ -0,0 +1,397 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d_3x.h
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved.
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+ 
+#ifndef __SEC_FIMG2D_H_
+#define __SEC_FIMG2D_H_
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/sched.h>
+
+#define G2D_SFR_SIZE    0x1000
+
+#define TRUE            (1)
+#define FALSE           (0)
+
+#define G2D_MINOR       240
+
+#define G2D_IOCTL_MAGIC 'G'
+
+#define G2D_BLIT                        _IO(G2D_IOCTL_MAGIC,0)
+#define G2D_GET_VERSION                 _IO(G2D_IOCTL_MAGIC,1)
+#define G2D_GET_MEMORY                  _IOR(G2D_IOCTL_MAGIC,2, unsigned int)
+#define G2D_GET_MEMORY_SIZE             _IOR(G2D_IOCTL_MAGIC,3, unsigned int)
+#define G2D_DMA_CACHE_CLEAN	        _IOWR(G2D_IOCTL_MAGIC,4, struct g2d_dma_info)
+#define G2D_DMA_CACHE_FLUSH	        _IOWR(G2D_IOCTL_MAGIC,5, struct g2d_dma_info)
+#define G2D_SYNC                    	_IO(G2D_IOCTL_MAGIC,6)
+#define G2D_RESET                    	_IO(G2D_IOCTL_MAGIC, 7)
+
+#define G2D_TIMEOUT             (1000)
+
+#define G2D_MAX_WIDTH   	(2048)
+#define G2D_MAX_HEIGHT  	(2048)
+
+#define G2D_ALPHA_VALUE_MAX 	(255)
+
+#define G2D_POLLING         	(1<<0)
+#define G2D_INTERRUPT       	(0<<0)
+#define G2D_CACHE_OP      	(1<<1)
+#define G2D_NONE_INVALIDATE 	(0<<1)
+#define G2D_HYBRID_MODE 	(1<<2)
+
+#define G2D_PT_NOTVALID		(0)
+#define G2D_PT_CACHED		(1)
+#define G2D_PT_UNCACHED		(2)
+
+#define GET_FRAME_SIZE(rect)    ((rect.full_w) * (rect.full_h) * (rect.bytes_per_pixel))
+#define GET_RECT_SIZE(rect)     ((rect.full_w) * (rect.h) * (rect.bytes_per_pixel))
+#define GET_REAL_SIZE(rect)     ((rect.full_w) * (rect.h) * (rect.bytes_per_pixel))
+#define GET_STRIDE(rect)		((rect.full_w) * (rect.bytes_per_pixel))
+#define GET_SPARE_BYTES(rect)	((rect.full_w - rect.w) * rect.bytes_per_pixel)
+#define GET_START_ADDR(rect)    (rect.addr + ((rect.y * rect.full_w) * rect.bytes_per_pixel))
+#define GET_REAL_START_ADDR(rect)    GET_START_ADDR(rect) + (rect.x * rect.bytes_per_pixel)
+#define GET_REAL_END_ADDR(rect)    GET_START_ADDR(rect) + GET_RECT_SIZE(rect) - ((rect.full_w - (rect.x + rect.w)) * rect.bytes_per_pixel)
+
+#define GET_RECT_SIZE_C(rect, clip)     ((rect.full_w) * (clip.b - clip.t) * (rect.bytes_per_pixel))
+#define GET_START_ADDR_C(rect, clip)    (rect.addr + ((clip.t * rect.full_w) * rect.bytes_per_pixel))
+#define GET_REAL_START_ADDR_C(rect, clip)    GET_START_ADDR_C(rect, clip) + (clip.l * rect.bytes_per_pixel)
+#define GET_REAL_END_ADDR_C(rect, clip)    GET_START_ADDR_C(rect, clip) + GET_RECT_SIZE_C(rect, clip) - ((rect.full_w - clip.r) * rect.bytes_per_pixel)
+
+#define GET_USEC(before, after) ((after.tv_sec - before.tv_sec) * 1000000 + (after.tv_usec - before.tv_usec))
+
+typedef enum {
+	G2D_ROT_0 = 0,
+	G2D_ROT_90,
+	G2D_ROT_180,
+	G2D_ROT_270,
+	G2D_ROT_X_FLIP,
+	G2D_ROT_Y_FLIP
+} G2D_ROT_DEG;
+
+typedef enum {
+	G2D_ALPHA_BLENDING_MIN    = 0,   // wholly transparent
+	G2D_ALPHA_BLENDING_MAX    = 255, // 255
+	G2D_ALPHA_BLENDING_OPAQUE = 256, // opaque
+} G2D_ALPHA_BLENDING_MODE;
+    
+typedef enum {
+	G2D_COLORKEY_NONE = 0,
+	G2D_COLORKEY_SRC_ON,
+	G2D_COLORKEY_DST_ON,
+	G2D_COLORKEY_SRC_DST_ON,
+}G2D_COLORKEY_MODE;
+
+typedef enum {
+	G2D_BLUE_SCREEN_NONE = 0,
+	G2D_BLUE_SCREEN_TRANSPARENT,
+	G2D_BLUE_SCREEN_WITH_COLOR,
+}G2D_BLUE_SCREEN_MODE;
+
+typedef enum {
+	G2D_ROP_SRC = 0,
+	G2D_ROP_DST,
+	G2D_ROP_SRC_AND_DST,
+	G2D_ROP_SRC_OR_DST,
+	G2D_ROP_3RD_OPRND,
+	G2D_ROP_SRC_AND_3RD_OPRND,
+	G2D_ROP_SRC_OR_3RD_OPRND,
+	G2D_ROP_SRC_XOR_3RD_OPRND,
+	G2D_ROP_DST_OR_3RD,
+}G2D_ROP_TYPE;
+
+typedef enum {
+	G2D_THIRD_OP_NONE = 0,
+	G2D_THIRD_OP_PATTERN,
+	G2D_THIRD_OP_FG,
+	G2D_THIRD_OP_BG
+}G2D_THIRD_OP_MODE;
+
+typedef enum {
+	G2D_BLACK = 0,
+	G2D_RED,
+	G2D_GREEN,
+	G2D_BLUE,
+	G2D_WHITE, 
+	G2D_YELLOW,
+	G2D_CYAN,
+	G2D_MAGENTA
+}G2D_COLOR;
+
+typedef enum {
+	G2D_RGB_565 = ((0<<4)|2),
+
+	G2D_ABGR_8888 = ((2<<4)|1),
+	G2D_BGRA_8888 = ((3<<4)|1),
+	G2D_ARGB_8888 = ((0<<4)|1),
+	G2D_RGBA_8888 = ((1<<4)|1),
+
+	G2D_XBGR_8888 = ((2<<4)|0),
+	G2D_BGRX_8888 = ((3<<4)|0),
+	G2D_XRGB_8888 = ((0<<4)|0),
+	G2D_RGBX_8888 = ((1<<4)|0),
+
+	G2D_ABGR_1555 = ((2<<4)|4),
+	G2D_BGRA_5551 = ((3<<4)|4),
+	G2D_ARGB_1555 = ((0<<4)|4),
+	G2D_RGBA_5551 = ((1<<4)|4),
+
+	G2D_XBGR_1555 = ((2<<4)|3),
+	G2D_BGRX_5551 = ((3<<4)|3),
+	G2D_XRGB_1555 = ((0<<4)|3),
+	G2D_RGBX_5551 = ((1<<4)|3),
+
+	G2D_ABGR_4444 = ((2<<4)|6),
+	G2D_BGRA_4444 = ((3<<4)|6),
+	G2D_ARGB_4444 = ((0<<4)|6),
+	G2D_RGBA_4444 = ((1<<4)|6),
+
+	G2D_XBGR_4444 = ((2<<4)|5),
+	G2D_BGRX_4444 = ((3<<4)|5),
+	G2D_XRGB_4444 = ((0<<4)|5),
+	G2D_RGBX_4444 = ((1<<4)|5),
+	
+	G2D_PACKED_BGR_888 = ((2<<4)|7),
+	G2D_PACKED_RGB_888 = ((0<<4)|7),
+
+	G2D_MAX_COLOR_SPACE
+}G2D_COLOR_SPACE;
+
+typedef enum {
+        G2D_Clear_Mode,    //!< [0, 0]
+        G2D_Src_Mode,      //!< [Sa, Sc]
+        G2D_Dst_Mode,      //!< [Da, Dc]
+        G2D_SrcOver_Mode,  //!< [Sa + Da - Sa*Da, Rc = Sc + (1 - Sa)*Dc]
+        G2D_DstOver_Mode,  //!< [Sa + Da - Sa*Da, Rc = Dc + (1 - Da)*Sc]
+        G2D_SrcIn_Mode,    //!< [Sa * Da, Sc * Da]
+        G2D_DstIn_Mode,    //!< [Sa * Da, Sa * Dc]
+        G2D_SrcOut_Mode,   //!< [Sa * (1 - Da), Sc * (1 - Da)]
+        G2D_DstOut_Mode,   //!< [Da * (1 - Sa), Dc * (1 - Sa)]
+        G2D_SrcATop_Mode,  //!< [Da, Sc * Da + (1 - Sa) * Dc]
+        G2D_DstATop_Mode,  //!< [Sa, Sa * Dc + Sc * (1 - Da)]
+        G2D_Xor_Mode,      //!< [Sa + Da - 2 * Sa * Da, Sc * (1 - Da) + (1 - Sa) * Dc]
+
+        // these modes are defined in the SVG Compositing standard
+        // http://www.w3.org/TR/2009/WD-SVGCompositing-20090430/
+        G2D_Plus_Mode,
+        G2D_Multiply_Mode,
+        G2D_Screen_Mode,
+        G2D_Overlay_Mode,
+        G2D_Darken_Mode,
+        G2D_Lighten_Mode,
+        G2D_ColorDodge_Mode,
+        G2D_ColorBurn_Mode,
+        G2D_HardLight_Mode,
+        G2D_SoftLight_Mode,
+        G2D_Difference_Mode,
+        G2D_Exclusion_Mode,
+
+        kLastMode = G2D_Exclusion_Mode
+}G2D_PORTTERDUFF_MODE;
+
+typedef enum {
+       G2D_MEMORY_KERNEL,
+       G2D_MEMORY_USER
+}G2D_MEMORY_TYPE;
+
+typedef struct {
+        int    x;
+        int    y;
+        unsigned int    w;
+        unsigned int    h;
+        unsigned int    full_w;
+        unsigned int    full_h;
+        int             color_format;
+        unsigned int    bytes_per_pixel;
+        unsigned char 	* addr;
+} g2d_rect;
+
+typedef struct {
+        unsigned int    t;
+        unsigned int    b;
+        unsigned int    l;
+        unsigned int    r;
+} g2d_clip;
+
+typedef struct {
+        unsigned int    rotate_val;
+        unsigned int    alpha_val;
+
+        unsigned int    blue_screen_mode;     //true : enable, false : disable
+        unsigned int    color_key_val;        //screen color value
+        unsigned int    color_switch_val;     //one color
+
+        unsigned int    src_color;            // when set one color on SRC
+        		
+        unsigned int    third_op_mode;
+        unsigned int    rop_mode;
+        unsigned int    mask_mode;
+        unsigned int    render_mode;    
+        unsigned int    potterduff_mode;
+        unsigned int    memory_type;
+} g2d_flag;
+
+typedef struct {
+        g2d_rect src_rect;
+        g2d_rect dst_rect;
+        g2d_clip clip;   
+        g2d_flag flag;
+} g2d_params;
+
+/* for reserved memory */
+struct g2d_reserved_mem {
+	/* buffer base */
+	unsigned int	base;
+	/* buffer size */
+	unsigned int	size;
+};
+
+
+struct g2d_dma_info {
+	unsigned long addr;
+	unsigned int  size;
+};
+
+struct g2d_platdata {
+	int hw_ver;
+	const char *parent_clkname;
+	const char *clkname;
+	const char *gate_clkname;
+	unsigned long clkrate;
+};
+
+struct g2d_timer {
+	int			cnt;
+	struct timeval		start_marker;
+	struct timeval		cur_marker;
+};
+
+struct g2d_global {
+	int             	irq_num;
+	struct resource 	* mem;
+	void   __iomem  	* base;
+	struct clk 		* clock;
+	atomic_t		clk_enable_flag;
+	wait_queue_head_t 	waitq;
+	atomic_t        	in_use;
+	atomic_t		num_of_object;
+	struct mutex		lock;
+	struct device		* dev;
+	atomic_t 		ready_to_run;
+	int 			src_attribute;
+	int 			dst_attribute;
+
+	struct g2d_reserved_mem	reserved_mem;		/* for reserved memory */
+	atomic_t		is_mmu_faulted;
+	unsigned int		faulted_addr;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend	early_suspend;
+#endif	
+	int                     irq_handled;
+};
+
+
+/****** debug message API *****/
+enum fimg2d_log {
+	FIMG2D_LOG_DEBUG	= 0x1000,
+	FIMG2D_LOG_INFO		= 0x0100,
+	FIMG2D_LOG_WARN		= 0x0010,
+	FIMG2D_LOG_ERR		= 0x0001,
+};
+
+/* debug macro */
+#define FIMG2D_LOG_DEFAULT	(FIMG2D_LOG_WARN | FIMG2D_LOG_ERR)
+
+#define FIMG2D_DEBUG(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_DEBUG)			\
+			printk(KERN_DEBUG "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define FIMG2D_INFO(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_INFO)			\
+			printk(KERN_INFO "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define FIMG2D_WARN(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_WARN)			\
+			printk(KERN_WARNING "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define FIMG2D_ERROR(fmt, ...)						\
+	do {								\
+		if (FIMG2D_LOG_DEFAULT & FIMG2D_LOG_ERR)			\
+			printk(KERN_ERR "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define fimg2d_dbg(fmt, ...)		FIMG2D_DEBUG(fmt, ##__VA_ARGS__)
+#define fimg2d_info(fmt, ...)		FIMG2D_INFO(fmt, ##__VA_ARGS__)
+#define fimg2d_warn(fmt, ...)		FIMG2D_WARN(fmt, ##__VA_ARGS__)
+#define fimg2d_err(fmt, ...)		FIMG2D_ERROR(fmt, ##__VA_ARGS__)
+
+
+/**** function declearation***************************/
+int g2d_check_params(g2d_params *params);
+void g2d_start_bitblt(struct g2d_global *g2d_dev, g2d_params *params);
+void g2d_check_fifo_state_wait(struct g2d_global *g2d_dev);
+u32  g2d_set_src_img(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag);
+u32  g2d_set_dst_img(struct g2d_global *g2d_dev, g2d_rect * rect);
+u32  g2d_set_pattern(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag);
+u32  g2d_set_clip_win(struct g2d_global *g2d_dev, g2d_clip * rect);
+u32  g2d_set_rotation(struct g2d_global *g2d_dev, g2d_flag * flag);
+u32  g2d_set_color_key(struct g2d_global *g2d_dev, g2d_flag * flag);
+u32  g2d_set_alpha(struct g2d_global *g2d_dev, g2d_flag * flag);
+void g2d_set_bitblt_cmd(struct g2d_global *g2d_dev, g2d_rect * src_rect, g2d_rect * dst_rect, g2d_clip * clip, u32 blt_cmd);
+void g2d_reset(struct g2d_global *g2d_dev);
+void g2d_disable_int(struct g2d_global *g2d_dev);
+void g2d_set_int_finish(struct g2d_global *g2d_dev);
+
+/* fimg2d_cache */
+void g2d_clip_for_src(g2d_rect *src_rect, g2d_rect *dst_rect, g2d_clip *clip, g2d_clip *src_clip);
+void g2d_mem_inner_cache(g2d_params *params);
+void g2d_mem_outer_cache(struct g2d_global *g2d_dev, g2d_params *params, int *need_dst_clean);
+void g2d_mem_cache_oneshot(void *src_addr,  void *dst_addr, unsigned long src_size, unsigned long dst_size);
+u32 g2d_mem_cache_op(unsigned int cmd, void * addr, unsigned int size);
+void g2d_mem_outer_cache_flush(void *start_addr, unsigned long size);                                      
+void g2d_mem_outer_cache_clean(const void *start_addr, unsigned long size);
+void g2d_mem_outer_cache_inv(g2d_params *params);
+u32 g2d_check_pagetable(void * vaddr, unsigned int size, unsigned long pgd);
+void g2d_pagetable_clean(const void *start_addr, unsigned long size, unsigned long pgd);
+int g2d_check_need_dst_cache_clean(g2d_params * params);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void g2d_early_suspend(struct early_suspend *h);
+void g2d_late_resume(struct early_suspend *h);
+#endif
+
+/* fimg2d_core */
+int g2d_clk_enable(struct g2d_global *g2d_dev);
+int g2d_clk_disable(struct g2d_global *g2d_dev);
+void g2d_sysmmu_on(struct g2d_global *g2d_dev);
+void g2d_sysmmu_off(struct g2d_global *g2d_dev);
+void g2d_sysmmu_set_pgd(u32 pgd);
+void g2d_fail_debug(g2d_params *params);
+int g2d_init_regs(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_do_blit(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_wait_for_finish(struct g2d_global *g2d_dev, g2d_params *params);
+int g2d_init_mem(struct device *dev, unsigned int *base, unsigned int *size);
+
+#endif /*__SEC_FIMG2D_H_*/
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.c b/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.c
new file mode 100644
index 0000000..33ce53e
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.c
@@ -0,0 +1,376 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d register control functions.
+ */
+
+#include <mach/map.h>
+#include <asm/io.h>
+#include <mach/regs-fimg2d3x.h>
+
+#include "fimg2d3x_regs.h"
+#include "fimg2d.h"
+
+void get_rot_config(unsigned int rotate_value, u32 *rot, u32 *src_dir, u32 *dst_dir)
+{
+	switch(rotate_value) {
+	case G2D_ROT_90: 
+		*rot = 1;   	/* rotation = 1, src_y_dir == dst_y_dir, src_x_dir == dst_x_dir */
+		*src_dir = 0;		
+		*dst_dir = 0;		
+		break;
+
+	case G2D_ROT_270: 
+		*rot = 1;   	/* rotation = 1, src_y_dir != dst_y_dir, src_x_dir != dst_x_dir */
+		*src_dir = 0;
+		*dst_dir = 0x3;
+		break;			
+
+	case G2D_ROT_180: 
+		*rot = 0;    	/* rotation = 0, src_y_dir != dst_y_dir, src_x_dir != dst_x_dir */
+		*src_dir = 0;
+		*dst_dir = 0x3;
+		break;
+
+	case G2D_ROT_X_FLIP: 
+		*rot = 0;    	/* rotation = 0, src_y_dir != dst_y_dir */
+		*src_dir = 0;
+		*dst_dir = 0x2;
+		break;
+
+	case G2D_ROT_Y_FLIP: 
+		*rot = 0;    	/* rotation = 0, src_x_dir != dst_y_dir */
+		*src_dir = 0;
+		*dst_dir = 0x1;
+		break;
+
+	default :
+		*rot = 0;   	/* rotation = 0; */
+		*src_dir = 0;
+		*dst_dir = 0;
+		break;
+	}
+	
+	return ;
+}
+
+int g2d_check_params(g2d_params *params)
+{
+	g2d_rect * src_rect = &params->src_rect;
+	g2d_rect * dst_rect = &params->dst_rect;
+	g2d_flag * flag     = &params->flag;
+
+	/* source */
+	if (0 > src_rect->x || 0 > src_rect->y) {
+		return -1;
+	}
+
+	if (0 == src_rect->h || 0 == src_rect->w) {
+		return -1;
+	}
+
+	if (8000 < src_rect->x+src_rect->w || 8000 < src_rect->y+src_rect->h) {
+		return -1;
+	}
+
+	/* destination */
+	if (0 > dst_rect->x || 0 > dst_rect->y) {
+		return -1;
+	}
+
+	if (0 == dst_rect->h || 0 == dst_rect->w) {
+		return -1;
+	}
+
+	if (8000 < dst_rect->x+dst_rect->w || 8000 < dst_rect->y+dst_rect->h) {
+		return -1;
+	}
+
+	if (flag->alpha_val > G2D_ALPHA_BLENDING_OPAQUE) {
+		return -1; 
+	}
+
+	return 0;
+}
+
+void g2d_check_fifo_state_wait(struct g2d_global *g2d_dev)
+{
+	/* 1 = The graphics engine finishes the execution of command. */
+	/* 0 = in the middle of rendering process. */
+	while(!(readl(g2d_dev->base + FIFO_STAT_REG) & 0x1));
+
+	return;
+}
+
+
+u32 g2d_set_src_img(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+
+	/* set  source to one color */
+	//if(rect == NULL)
+	if (flag->potterduff_mode == G2D_Clear_Mode) {
+		/* select source */
+		writel(G2D_SRC_SELECT_R_USE_FG_COLOR, g2d_dev->base + SRC_SELECT_REG);
+
+		/* foreground color */
+		// writel(flag->src_color, g2d_dev->base + FG_COLOR_REG);		
+		writel(0, g2d_dev->base + FG_COLOR_REG);	
+	} else {
+		/* select source */
+		writel(G2D_SRC_SELECT_R_NORMAL, g2d_dev->base + SRC_SELECT_REG);
+
+		/* set base address of source image */
+		writel((u32)rect->addr,   g2d_dev->base + SRC_BASE_ADDR_REG);
+
+		/* set stride */
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + SRC_STRIDE_REG);
+
+		/* set color mode */
+		writel(rect->color_format, g2d_dev->base + SRC_COLOR_MODE_REG);
+
+		/* set coordinate of source image */
+		data = (rect->y << 16) | (rect->x);
+		writel(data, g2d_dev->base + SRC_LEFT_TOP_REG);
+
+		data = ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+		writel(data, g2d_dev->base + SRC_RIGHT_BOTTOM_REG);
+        
+	}
+
+	return blt_cmd;
+}
+
+u32 g2d_set_dst_img(struct g2d_global *g2d_dev, g2d_rect * rect)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+	
+	/* select destination */
+	writel(G2D_DST_SELECT_R_NORMAL, g2d_dev->base + DST_SELECT_REG);
+
+	/* set base address of destination image */
+	writel((u32)rect->addr,   g2d_dev->base + DST_BASE_ADDR_REG);
+
+	/* set stride */
+	writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + DST_STRIDE_REG);
+
+	/* set color mode */
+	writel(rect->color_format, g2d_dev->base + DST_COLOR_MODE_REG);
+
+	/* set coordinate of destination image */
+	data = (rect->y << 16) | (rect->x);
+	writel(data, g2d_dev->base + DST_LEFT_TOP_REG);
+
+	data = ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+	writel(data, g2d_dev->base + DST_RIGHT_BOTTOM_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_rotation(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+	u32 rot=0, src_dir=0, dst_dir=0;
+
+	get_rot_config(flag->rotate_val, &rot, &src_dir, &dst_dir);
+
+	writel(rot,     g2d_dev->base + ROTATE_REG);
+	writel(src_dir, g2d_dev->base + SRC_MSK_DIRECT_REG);
+	writel(dst_dir, g2d_dev->base + DST_PAT_DIRECT_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_clip_win(struct g2d_global *g2d_dev, g2d_clip * clip)
+{
+	u32 blt_cmd = 0;
+
+        //blt_cmd |= G2D_BLT_CMD_R_CW_ENABLE;
+	writel((clip->t << 16) | (clip->l), g2d_dev->base + CW_LEFT_TOP_REG);
+	writel((clip->b << 16) | (clip->r), g2d_dev->base + CW_RIGHT_BOTTOM_REG);
+
+	return blt_cmd;
+}
+
+u32 g2d_set_color_key(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+
+	/* Transparent Selection */
+	switch(flag->blue_screen_mode) {
+	case G2D_BLUE_SCREEN_TRANSPARENT :
+		writel(flag->color_key_val, g2d_dev->base + BS_COLOR_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_TRANS;
+		break;
+
+	case G2D_BLUE_SCREEN_WITH_COLOR :
+		writel(flag->color_switch_val,     g2d_dev->base + BG_COLOR_REG);
+		writel(flag->color_key_val, g2d_dev->base + BS_COLOR_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_BLUESCR;
+		break;
+
+	case G2D_BLUE_SCREEN_NONE :
+	default:
+		blt_cmd |= G2D_BLT_CMD_R_TRANSPARENT_MODE_OPAQUE;
+		break;
+	}
+
+	blt_cmd |= G2D_BLT_CMD_R_COLOR_KEY_DISABLE;
+
+	return blt_cmd;
+}
+
+u32 g2d_set_pattern(struct g2d_global *g2d_dev, g2d_rect * rect, g2d_flag * flag)
+{
+	u32 data    = 0;
+	u32 blt_cmd = 0;
+
+	/* Third Operand Selection */
+	switch(flag->third_op_mode) {	
+	case G2D_THIRD_OP_PATTERN :
+		/* set base address of pattern image */
+		writel((u32)rect->addr, g2d_dev->base + PAT_BASE_ADDR_REG);
+
+		/* set size of pattern image */
+		data =   ((rect->y + rect->h) << 16) | (rect->x + rect->w);
+		writel(data, g2d_dev->base + PAT_SIZE_REG);
+
+		/* set stride */
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + PAT_STRIDE_REG);
+
+		/* set color mode */
+		writel(rect->color_format, g2d_dev->base + PAT_COLOR_MODE_REG);
+
+		data =   (rect->y << 16) | rect->x;
+		writel(data, g2d_dev->base + PAT_OFFSET_REG);
+
+		data = G2D_THIRD_OP_REG_PATTERN;
+		break;
+	case G2D_THIRD_OP_FG :
+		data = G2D_THIRD_OP_REG_FG_COLOR;
+		break;
+	case G2D_THIRD_OP_BG :
+		data = G2D_THIRD_OP_REG_BG_COLOR;
+		break;
+	case G2D_THIRD_OP_NONE :
+	default:
+		data = G2D_THIRD_OP_REG_NONE;
+		break;
+	}
+
+	writel(data, g2d_dev->base + THIRD_OPERAND_REG);
+	
+	if(flag->third_op_mode == G2D_THIRD_OP_NONE) {
+		data = ((G2D_ROP_REG_SRC << 8) | G2D_ROP_REG_SRC);
+	} else {
+		switch(flag->rop_mode) {	
+		case G2D_ROP_DST:
+			data = ((G2D_ROP_REG_DST << 8) | G2D_ROP_REG_DST);
+			break;
+		case G2D_ROP_SRC_AND_DST:
+			data = ((G2D_ROP_REG_SRC_AND_DST << 8) | G2D_ROP_REG_SRC_AND_DST);
+			break;
+		case G2D_ROP_SRC_OR_DST:
+			data = ((G2D_ROP_REG_SRC_OR_DST << 8) | G2D_ROP_REG_SRC_OR_DST);
+			break;
+		case G2D_ROP_3RD_OPRND:
+			data = ((G2D_ROP_REG_3RD_OPRND << 8) | G2D_ROP_REG_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_AND_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_AND_3RD_OPRND << 8) | G2D_ROP_REG_SRC_AND_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_OR_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_OR_3RD_OPRND << 8) | G2D_ROP_REG_SRC_OR_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC_XOR_3RD_OPRND:
+			data = ((G2D_ROP_REG_SRC_XOR_3RD_OPRND << 8) | G2D_ROP_REG_SRC_XOR_3RD_OPRND);
+			break;
+		case G2D_ROP_DST_OR_3RD:
+			data = ((G2D_ROP_REG_DST_OR_3RD_OPRND << 8) | G2D_ROP_REG_DST_OR_3RD_OPRND);
+			break;
+		case G2D_ROP_SRC:
+		default:
+			data = ((G2D_ROP_REG_SRC << 8) | G2D_ROP_REG_SRC);
+			break;
+		}
+	}
+	writel(data, g2d_dev->base + ROP4_REG);
+
+	/* Mask Operation */
+	if(flag->mask_mode == TRUE) {
+		writel((u32)rect->addr, g2d_dev->base + MASK_BASE_ADDR_REG);
+		writel(rect->full_w * rect->bytes_per_pixel, g2d_dev->base + MASK_STRIDE_REG);
+
+		blt_cmd |= G2D_BLT_CMD_R_MASK_ENABLE;
+	}
+
+	return blt_cmd;
+}
+
+u32 g2d_set_alpha(struct g2d_global *g2d_dev, g2d_flag * flag)
+{
+	u32 blt_cmd = 0;
+
+	/* Alpha Value */
+	if(flag->alpha_val <= G2D_ALPHA_VALUE_MAX) {
+		if ((flag->potterduff_mode == G2D_Clear_Mode) || (flag->potterduff_mode == G2D_Src_Mode))
+			blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_NONE;
+		else
+			blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_ALPHA_BLEND;
+		writel((flag->alpha_val & 0xff), g2d_dev->base + ALPHA_REG);
+	} else {
+		blt_cmd |= G2D_BLT_CMD_R_ALPHA_BLEND_NONE;
+	}
+
+	return blt_cmd;
+}
+
+void g2d_set_bitblt_cmd(struct g2d_global *g2d_dev, g2d_rect * src_rect, g2d_rect * dst_rect, g2d_clip * clip, u32 blt_cmd)
+{
+	if ((src_rect->w  != dst_rect->w)
+		|| (src_rect->h  != dst_rect->h)) {
+		blt_cmd |= G2D_BLT_CMD_R_STRETCH_ENABLE;
+	}
+	
+	if ((clip->t != dst_rect->y) || (clip->b != dst_rect->y + dst_rect->h) 
+		|| (clip->l != dst_rect->x) || (clip->r != dst_rect->x + dst_rect->w)) {
+		blt_cmd |= G2D_BLT_CMD_R_CW_ENABLE;
+	}
+	writel(blt_cmd, g2d_dev->base + BITBLT_COMMAND_REG);
+}
+
+void g2d_reset(struct g2d_global *g2d_dev)
+{
+	writel(G2D_SWRESET_R_RESET, g2d_dev->base + SOFT_RESET_REG);
+}
+
+void g2d_disable_int(struct g2d_global *g2d_dev)
+{
+	writel(G2D_INTEN_R_CF_DISABLE, g2d_dev->base + INTEN_REG);
+}
+
+void g2d_set_int_finish(struct g2d_global *g2d_dev)
+{
+	writel(G2D_INTC_PEND_R_INTP_CMD_FIN, g2d_dev->base + INTC_PEND_REG);
+}
+
+void g2d_start_bitblt(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	if (!(params->flag.render_mode & G2D_POLLING)) {
+		writel(G2D_INTEN_R_CF_ENABLE, g2d_dev->base + INTEN_REG);
+	}
+	writel(0x7, g2d_dev->base + CACHECTL_REG);
+
+	writel(G2D_BITBLT_R_START, g2d_dev->base + BITBLT_START_REG);
+}
+
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.h b/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.h
new file mode 100644
index 0000000..f67f636
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.h
@@ -0,0 +1,278 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_regs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.*/
+
+#ifndef __SEC_FIMG2D3X_REGS_H
+#define __SEC_FIMG2D3X_REGS_H
+ 
+//**********************************************************
+//     Address Definition of SFR
+//**********************************************************
+#define SEC_G2DREG(x)           ((x))
+
+//**   General Register   *****************
+#define CONRTOL_REG             SEC_G2DREG(0x0000)
+#define SOFT_RESET_REG          SEC_G2DREG(0x0000)
+#define INTEN_REG               SEC_G2DREG(0x0004)
+#define INTC_PEND_REG           SEC_G2DREG(0x000C)
+#define FIFO_STAT_REG           SEC_G2DREG(0x0010)
+#define AXI_ID_MODE_REG         SEC_G2DREG(0x0014)
+#define CACHECTL_REG            SEC_G2DREG(0x0018)
+
+//**   G2D Command   *********************
+#define BITBLT_START_REG        SEC_G2DREG(0x0100)
+#define BITBLT_COMMAND_REG      SEC_G2DREG(0x0104)
+
+//**   Rotation & Direction   *************
+#define ROTATE_REG              SEC_G2DREG(0x0200)
+#define SRC_MSK_DIRECT_REG      SEC_G2DREG(0x0204)
+#define DST_PAT_DIRECT_REG      SEC_G2DREG(0x0208)
+// for old vector
+#define SRC_DIRECT_REG          SEC_G2DREG(0x0204)
+#define DST_DIRECT_REG          SEC_G2DREG(0x0208)
+
+//**   Source    **************************
+#define SRC_SELECT_REG          SEC_G2DREG(0x0300)
+#define SRC_BASE_ADDR_REG       SEC_G2DREG(0x0304)
+#define SRC_STRIDE_REG          SEC_G2DREG(0x0308)
+#define SRC_COLOR_MODE_REG      SEC_G2DREG(0x030C)
+#define SRC_LEFT_TOP_REG        SEC_G2DREG(0x0310)
+#define SRC_RIGHT_BOTTOM_REG    SEC_G2DREG(0x0314)
+
+//**   Destination  ***********************
+#define DST_SELECT_REG          SEC_G2DREG(0x0400)
+#define DST_BASE_ADDR_REG       SEC_G2DREG(0x0404)
+#define DST_STRIDE_REG          SEC_G2DREG(0x0408)
+#define DST_COLOR_MODE_REG      SEC_G2DREG(0x040C)
+#define DST_LEFT_TOP_REG        SEC_G2DREG(0x0410)
+#define DST_RIGHT_BOTTOM_REG    SEC_G2DREG(0x0414)
+
+//**   Pattern   **************************
+#define PAT_BASE_ADDR_REG       SEC_G2DREG(0x0500)
+#define PAT_SIZE_REG            SEC_G2DREG(0x0504)
+#define PAT_COLOR_MODE_REG      SEC_G2DREG(0x0508)
+#define PAT_OFFSET_REG          SEC_G2DREG(0x050C)
+#define PAT_STRIDE_REG          SEC_G2DREG(0x0510)
+
+//**   Mask   *****************************
+#define MASK_BASE_ADDR_REG      SEC_G2DREG(0x0520)
+#define MASK_STRIDE_REG         SEC_G2DREG(0x0524)
+
+//**   Clipping Window  *******************
+#define CW_LEFT_TOP_REG         SEC_G2DREG(0x0600)
+#define	CW_RIGHT_BOTTOM_REG     SEC_G2DREG(0x0604)
+
+//**   ROP4 & Blending   *****************
+#define THIRD_OPERAND_REG       SEC_G2DREG(0x0610)
+#define ROP4_REG                SEC_G2DREG(0x0614)
+#define ALPHA_REG               SEC_G2DREG(0x0618)
+
+//**   Color   ***************************
+#define FG_COLOR_REG            SEC_G2DREG(0x0700)
+#define BG_COLOR_REG            SEC_G2DREG(0x0704)
+#define BS_COLOR_REG            SEC_G2DREG(0x0708)
+
+//**   Color Key   ***********************
+#define SRC_COLORKEY_CTRL_REG   SEC_G2DREG(0x0710)
+#define SRC_COLORKEY_DR_MIN_REG SEC_G2DREG(0x0714)
+#define SRC_COLORKEY_DR_MAX_REG SEC_G2DREG(0x0718)
+#define DST_COLORKEY_CTRL_REG   SEC_G2DREG(0x071C)
+#define DST_COLORKEY_DR_MIN_REG SEC_G2DREG(0x0720)
+#define DST_COLORKEY_DR_MAX_REG SEC_G2DREG(0x0724)
+
+//**********************************************************
+//     Bit Definition part
+//**********************************************************
+ 
+/* software reset register (SOFT_RESET_REG : 0x0000) */
+#define	G2D_SWRESET_R_RESET                     (1<<0)
+
+/* interrupt enable register (INTEN_REG : 0x0004)) */
+#define G2D_INTEN_R_INT_TYPE_EDGE               (1<<1)
+#define G2D_INTEN_R_INT_TYPE_LEVEL              (0<<1)
+#define G2D_INTEN_R_CF_ENABLE                   (1<<0)
+#define G2D_INTEN_R_CF_DISABLE                  (0<<0)
+
+/* interrupt pending register (INTC_PEND_REG : 0x000C) */
+#define	G2D_INTC_PEND_R_INTP_CMD_FIN            (1<<0)
+
+/* AXI ID mode register (AXI_ID_MODE_REG : 0x0014) */
+#define	G2D_AXIID_MODE_R_MULTI_ID               (1<<0)
+#define G2D_AXIID_MODE_R_SIGNLE_ID              (0<<0)
+
+/* bitblit start register (BITBLT_START_REG : 0x0100) */
+#define	G2D_BITBLT_R_START                      (1<<0)
+
+/* bitblt command register (BITBLT_COMMAND_REG : 0x0104) */
+#define	G2D_BLT_CMD_R_COLOR_EXP_CORRECT         (0<<24)
+#define	G2D_BLT_CMD_R_COLOR_EXP_ZERO            (1<<24)
+
+#define	G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_DISLABE         (0<<22)
+#define G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_CONSTANT_ALPHA  (1<<22)
+#define G2D_BLT_CMD_R_SRC_NON_PRE_BLEND_PERPIXEL_ALPHA  (2<<22)
+
+#define G2D_BLT_CMD_R_ALPHA_BLEND_NONE          (0<<20)
+#define	G2D_BLT_CMD_R_ALPHA_BLEND_ALPHA_BLEND   (1<<20)
+#define G2D_BLT_CMD_R_ALPHA_BLEND_FADE          (2<<20)
+// #define G2D_BLT_CMD_R_ALPHA_BLEND_PERPIXEL      (3<<20)
+
+#define G2D_BLT_CMD_R_ALPHA_BLEND_FAD_OFFSET    (8)
+
+#define G2D_BLT_CMD_R_COLOR_KEY_DISABLE         (0<<16)
+#define G2D_BLT_CMD_R_COLOR_KEY_ENABLE_SRC      (1<<16)
+#define	G2D_BLT_CMD_R_COLOR_KEY_ENABLE_DST      (2<<16)
+#define G2D_BLT_CMD_R_COLOP_KEY_ENABLE_SRC_DST  (3<<16)
+
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_OPAQUE   (0<<12)
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_TRANS    (1<<12)
+#define	G2D_BLT_CMD_R_TRANSPARENT_MODE_BLUESCR  (2<<12)
+
+#define G2D_BLT_CMD_R_CW_ENABLE              (1<<8)
+#define G2D_BLT_CMD_R_STRETCH_ENABLE         (1<<4)
+#define	G2D_BLT_CMD_R_MASK_ENABLE            (1<<0)
+
+/* rotation register (ROTATE_REG : 0x02000) */
+#define	G2D_ROT_CMD_R_0                      (0<<0)
+#define	G2D_ROT_CMD_R_90                     (1<<0)
+
+/* source and mask direction register (SRC_MSK_DIRECT_REG : 0x0204) */
+#define	G2D_SRC_MSK_DIR_R_MSK_Y_POSITIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_MSK_Y_NEGATIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_SRC_Y_POSITIVE     (0<<8)
+#define	G2D_SRC_MSK_DIR_R_SRC_Y_POSITIVE     (0<<8)
+
+/* source image selection register (SRC_SELECT_REG : 0x0300) */
+#define G2D_SRC_SELECT_R_NORMAL              (0<<0)
+#define G2D_SRC_SELECT_R_USE_FG_COLOR        (1<<0)
+#define G2D_SRC_SELECT_R_USE_BG_COLOR        (2<<0)
+
+/* source image color mode register (SRC_COLOR_MODE_REG : 0x030C) */
+
+
+/* destination image selection register (DST_SELECT_REG : 0x0400) */
+#define G2D_DST_SELECT_R_NORMAL              (0<<0)
+#define G2D_DST_SELECT_R_USE_FG_COLOR        (1<<0)
+#define G2D_DST_SELECT_R_USE_BG_COLOR        (2<<0)
+
+#define	G2D_CMD0_REG_M_X                     (1<<8)
+
+#define	G2D_CMD0_REG_L                       (1<<1)
+#define	G2D_CMD0_REG_P                       (1<<0)
+
+/* BitBLT */
+#define	G2D_CMD1_REG_S                       (1<<1)
+#define	G2D_CMD1_REG_N                       (1<<0)
+
+/* resource color mode */
+#define G2D_COLOR_MODE_REG_C3_32BPP          (1<<3)
+#define G2D_COLOR_MODE_REG_C3_24BPP          (1<<3)
+#define G2D_COLOR_MODE_REG_C2_18BPP          (1<<2)
+#define G2D_COLOR_MODE_REG_C1_16BPP          (1<<1)
+#define G2D_COLOR_MODE_REG_C0_15BPP          (1<<0)
+
+#define G2D_COLOR_RGB_565                    (0x0<<0)
+#define G2D_COLOR_RGBA_5551                  (0x1<<0)
+#define G2D_COLOR_ARGB_1555                  (0x2<<0)
+#define G2D_COLOR_RGBA_8888                  (0x3<<0)
+#define G2D_COLOR_ARGB_8888                  (0x4<<0)
+#define G2D_COLOR_XRGB_8888                  (0x5<<0)
+#define G2D_COLOR_RGBX_8888                  (0x6<<0)
+#define G2D_COLOR_YUV422_SP                  (0x1<<3)
+
+#define G2D_CHL_ORDER_XRGB                   (0<<4) // ARGB,XRGB
+#define G2D_CHL_ORDER_RGBX                   (1<<4) // RGBA,RGBX
+#define G2D_CHL_ORDER_XBGR                   (2<<4) // ABGR,XBGR
+#define G2D_CHL_ORDER_BGRX                   (3<<4) // BGRA,BGRX
+
+#define G2D_FMT_XRGB_8888                    (0)
+#define G2D_FMT_ARGB_8888                    (1)
+#define G2D_FMT_RGB_565                      (2)
+#define G2D_FMT_XRGB_1555                    (3)
+#define G2D_FMT_ARGB_1555                    (4)
+#define G2D_FMT_XRGB_4444                    (5)
+#define G2D_FMT_ARGB_4444                    (6)
+#define G2D_FMT_PACKED_RGB_888               (7)
+
+/* rotation mode */
+#define G2D_ROTATRE_REG_FY                   (1<<5)
+#define G2D_ROTATRE_REG_FX                   (1<<4)
+#define G2D_ROTATRE_REG_R3_270               (1<<3)
+#define G2D_ROTATRE_REG_R2_180               (1<<2)
+#define G2D_ROTATRE_REG_R1_90                (1<<1)
+#define G2D_ROTATRE_REG_R0_0                 (1<<0)
+
+/* Endian select */
+#define G2D_ENDIAN_DST_BIG_ENDIAN            (1<<1)
+#define G2D_ENDIAN_DST_LITTLE_ENDIAN         (0<<1)
+
+#define G2D_ENDIAN_SRC_BIG_ENDIAN            (1<<0)
+#define G2D_ENDIAN_SRC_LITTLE_ENDIAN         (0<<0)
+
+/* read buffer size */
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_1      (0<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_4      (1<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_8      (2<<0)
+#define	G2D_ENDIAN_READSIZE_READ_SIZE_16     (3<<0)
+
+/* Third Operans Select */
+/*
+#define G2D_ROP_REG_OS_PATTERN	             (0<<13)
+#define G2D_ROP_REG_OS_FG_COLOR	             (1<<13)
+#define G2D_ROP_REG_OS_PATTERN_MASK_SELECT   (0<<4)
+#define G2D_ROP_REG_OS_PATTERN_THIRD         (0)
+*/
+#define G2D_THIRD_OP_REG_PATTERN             ((0<<4) | (0))
+#define G2D_THIRD_OP_REG_FG_COLOR            ((1<<4) | (1))
+#define G2D_THIRD_OP_REG_BG_COLOR            ((2<<4) | (2))
+#define G2D_THIRD_OP_REG_NONE                ((3<<4) | (3))
+
+/* Alpha Blending Mode */
+#define G2D_ROP_REG_ABM_NO_BLENDING          (0<<10)
+#define G2D_ROP_REG_ABM_SRC_BITMAP           (1<<10)
+#define G2D_ROP_REG_ABM_REGISTER             (2<<10)
+#define G2D_ROP_REG_ABM_FADING               (4<<10)
+
+/* Raster operation mode */
+#define G2D_ROP_REG_T_OPAQUE_MODE            (0<<9)
+#define G2D_ROP_REG_T_TRANSP_MODE            (1<<9)
+
+#define G2D_ROP_REG_B_BS_MODE_OFF            (0<<8)
+#define G2D_ROP_REG_B_BS_MODE_ON             (1<<8)
+
+/*
+#define G2D_ROP_REG_SRC_ONLY                 (0xf0)
+#define G2D_ROP_REG_3RD_OPRND_ONLY           (0xaa)
+#define G2D_ROP_REG_DST_ONLY                 (0xcc)
+#define G2D_ROP_REG_SRC_OR_DST               (0xfc)
+#define G2D_ROP_REG_SRC_OR_3RD_OPRND         (0xfa)
+#define G2D_ROP_REG_SRC_AND_DST              (0xc0) //(pat==1)? src:dst
+#define G2D_ROP_REG_SRC_AND_3RD_OPRND        (0xa0)
+#define G2D_ROP_REG_SRC_XOR_3RD_OPRND        (0x5a)
+#define G2D_ROP_REG_DST_OR_3RD_OPRND         (0xee)
+*/
+#define G2D_ROP_REG_SRC                      (0xcc)
+#define G2D_ROP_REG_DST                      (0xaa)
+#define G2D_ROP_REG_SRC_AND_DST              (0x88) 
+#define G2D_ROP_REG_SRC_OR_DST               (0xee)
+#define G2D_ROP_REG_3RD_OPRND                (0xf0)
+#define G2D_ROP_REG_SRC_AND_3RD_OPRND        (0xc0)
+#define G2D_ROP_REG_SRC_OR_3RD_OPRND         (0xfc)
+#define G2D_ROP_REG_SRC_XOR_3RD_OPRND        (0x3c)
+#define G2D_ROP_REG_DST_OR_3RD_OPRND         (0xfa)
+
+
+/* stencil control */
+#define G2D_STENCIL_CNTL_REG_STENCIL_ON_ON   (1<<31)
+#define G2D_STENCIL_CNTL_REG_STENCIL_ON_OFF  (0<<31)
+
+#define G2D_STENCIL_CNTL_REG_STENCIL_INVERSE (1<<23)
+#define G2D_STENCIL_CNTL_REG_STENCIL_SWAP    (1<<0)
+
+/*********************************************************************************/
+
+#endif /* __SEC_FIMG2D3X_REGS_H */
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d_cache.c b/drivers/media/video/samsung/fimg2d3x/fimg2d_cache.c
new file mode 100644
index 0000000..639b3f8
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d_cache.c
@@ -0,0 +1,379 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_cache.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d cache control functions.
+ */
+
+#include <linux/kernel.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+#include <asm/io.h>
+#include <linux/sched.h>
+#include <linux/poll.h>
+
+#include "fimg2d.h"
+
+#define L1_ALL_THRESHOLD_SIZE SZ_64K
+#define L2_ALL_THRESHOLD_SIZE SZ_1M
+
+#define L2_CACHE_SKIP_MARK 256*4
+
+void g2d_pagetable_clean(const void *start_addr, unsigned long size, unsigned long pgd)
+{
+	void *l1d_vir, *l1d_phy, *l2d_phy;
+	void *cur_addr, *end_addr;
+	size = ALIGN(size, SZ_1M);
+	cur_addr = (void *)((unsigned long)start_addr & ~(SZ_1M-1));
+	end_addr = cur_addr + size + SZ_1M;
+    
+	l1d_phy = (void *)((pgd & 0xffffc000) | (((u32)(cur_addr) & 0xfff00000)>>18)); 
+	
+	if (l1d_phy) {
+		l1d_vir = phys_to_virt((u32)l1d_phy);
+		dmac_map_area(l1d_vir, (size/SZ_1M)*4, DMA_TO_DEVICE);
+	}
+	
+	while (cur_addr < end_addr) {
+		outer_clean_range((u32)l1d_phy, (u32)l1d_phy + 4);
+
+		if (l1d_phy) {			
+			l2d_phy = (void *)((readl(phys_to_virt((u32)l1d_phy)) & 0xfffffc00) | 
+				(((u32)cur_addr & 0x000ff000) >> 10));
+			if (l2d_phy)
+				dmac_map_area(phys_to_virt((u32)l2d_phy), SZ_1K, DMA_TO_DEVICE);  
+			outer_clean_range((u32)l2d_phy, (u32)l2d_phy + SZ_1K);
+		}
+		cur_addr += SZ_1M; 
+		l1d_phy = (void *)((pgd & 0xffffc000) | (((u32)(cur_addr) & 0xfff00000)>>18));
+	}  
+}
+
+
+static unsigned long virt2phys(unsigned long addr)
+{
+	pgd_t *pgd;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	if(!current->mm) {
+		current->mm = &init_mm;
+	}
+
+	pgd = pgd_offset(current->mm, addr);
+
+	if ((pgd_val(*pgd) & 0x1) != 0x1) {
+		return 0;
+	}
+	
+	pmd = pmd_offset(pgd, addr);
+	pte = pte_offset_map(pmd, addr);
+
+	return (addr & 0xfff) | (pte_val(*pte) & 0xfffff000);
+}
+
+u32 g2d_check_pagetable(void * vaddr, unsigned int size, unsigned long pgd)
+{
+    unsigned int level_one_phy, level_two_phy;
+    unsigned int level_one_value, level_two_value; 
+    
+    for (;;) {
+	level_one_phy = (pgd & 0xffffc000) | (((u32)vaddr & 0xfff00000)>>18);
+	if ((int)phys_to_virt(level_one_phy) < 0xc0000000) {
+		FIMG2D_ERROR("Level1 page table mapping missed, missed address = %p", phys_to_virt(level_one_phy));
+		return G2D_PT_NOTVALID;
+	}
+	level_one_value = readl(phys_to_virt(level_one_phy));
+
+	level_two_phy = (level_one_value & 0xfffffc00) | (((u32)vaddr & 0x000ff000) >> 10);
+	if ((int)phys_to_virt(level_two_phy) < 0xc0000000) {
+		FIMG2D_ERROR("Level2 page table mapping missed, missed address = %p", phys_to_virt(level_two_phy));
+		return G2D_PT_NOTVALID;
+	}
+	level_two_value = readl(phys_to_virt(level_two_phy));
+
+	if (((level_one_value & 0x3) != 0x1) || ((level_two_value & 0x3) != 0x3)) {
+		FIMG2D_DEBUG("Surface memory mapping fail [L1: 0x%x, L2: 0x%x]\n",
+			level_one_value, level_two_value);
+		return G2D_PT_NOTVALID;
+	}
+	if (size == 0) {
+		if  ((level_two_value & 0x08) != 0x08)
+			return G2D_PT_UNCACHED;
+		return G2D_PT_CACHED;
+	}
+    
+	if (size <= PAGE_SIZE) {
+		vaddr += (size-1);
+		size = 0;
+	} else {
+		vaddr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+    }
+}
+
+void g2d_clip_for_src(g2d_rect *src_rect, g2d_rect *dst_rect, g2d_clip *clip, g2d_clip *src_clip)
+{
+	if ((src_rect->w == dst_rect->w) && (src_rect->h == dst_rect->h)) {
+		src_clip->t = src_rect->y + (clip->t - dst_rect->y);
+		src_clip->l = src_rect->x + (clip->l - dst_rect->x);
+		src_clip->b = src_clip->t + (clip->b - clip->t);
+		src_clip->r = src_clip->l + (clip->r - clip->l);
+	} else {
+		src_clip->t = src_rect->y;
+		src_clip->l = src_rect->x;
+		src_clip->b = src_clip->t + src_rect->h;
+		src_clip->r = src_clip->l + src_rect->w;
+	}
+}
+
+void g2d_mem_inner_cache(g2d_params * params)
+{
+	void *src_addr, *dst_addr;
+	unsigned long src_size, dst_size;
+	g2d_clip clip_src;
+	g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+	src_addr = (void *)GET_START_ADDR_C(params->src_rect, clip_src); 
+	dst_addr = (void *)GET_START_ADDR_C(params->dst_rect, params->clip);
+	src_size = (unsigned long)GET_RECT_SIZE_C(params->src_rect, clip_src); 
+	dst_size = (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	if((src_size + dst_size) < L1_ALL_THRESHOLD_SIZE) {
+		dmac_map_area(src_addr, src_size, DMA_TO_DEVICE);
+		dmac_flush_range(dst_addr, dst_addr + dst_size);
+	} else {
+		flush_all_cpu_caches();
+	}
+}
+
+void g2d_mem_outer_cache(struct g2d_global *g2d_dev, g2d_params * params, int *need_dst_clean)
+{
+ 	unsigned long start_paddr, end_paddr;
+	unsigned long cur_addr, end_addr;
+	unsigned long width_bytes;
+	unsigned long stride;
+	unsigned long src_size, dst_size;
+
+#if 0
+	if (((GET_RECT_SIZE(params->src_rect) + GET_RECT_SIZE(params->dst_rect)) > L2_ALL_THRESHOLD_SIZE)
+		&& ((*need_dst_clean == true) || ( GET_RECT_SIZE(params->src_rect) > 384*640*4))) {
+		outer_flush_all();
+		*need_dst_clean = true;
+		return;
+	}	
+#endif
+
+	g2d_clip clip_src;
+	g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+	src_size = GET_RECT_SIZE_C(params->src_rect, clip_src);
+	dst_size = GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	if ((src_size + dst_size) >= L2_ALL_THRESHOLD_SIZE) {
+		outer_flush_all();
+		*need_dst_clean = true;
+		return;
+	}
+
+	if((GET_SPARE_BYTES(params->src_rect) < L2_CACHE_SKIP_MARK) 
+		|| ((params->src_rect.w * params->src_rect.bytes_per_pixel) >= PAGE_SIZE)) {
+		g2d_mem_outer_cache_clean((void *)GET_START_ADDR_C(params->src_rect, clip_src), 
+			(unsigned int)GET_RECT_SIZE_C(params->src_rect, clip_src));
+	} else {
+		stride = GET_STRIDE(params->src_rect);
+		width_bytes = params->src_rect.w * params->src_rect.bytes_per_pixel;
+		cur_addr = (unsigned long)GET_REAL_START_ADDR_C(params->src_rect, clip_src);
+		end_addr = (unsigned long)GET_REAL_END_ADDR_C(params->src_rect, clip_src);
+
+		while (cur_addr <= end_addr) {
+			start_paddr = virt2phys((unsigned long)cur_addr);
+			end_paddr = virt2phys((unsigned long)cur_addr + width_bytes);
+			
+			if (((end_paddr - start_paddr) > 0) && ((end_paddr -start_paddr) < PAGE_SIZE)) {
+				outer_clean_range(start_paddr, end_paddr);
+			} else {
+				outer_clean_range(start_paddr, ((start_paddr + PAGE_SIZE) & PAGE_MASK) - 1);
+				outer_clean_range(end_paddr & PAGE_MASK, end_paddr);			
+			}
+			cur_addr += stride;
+		}
+	}
+
+	if (*need_dst_clean) {
+		if ((GET_SPARE_BYTES(params->dst_rect) < L2_CACHE_SKIP_MARK)
+			|| ((params->dst_rect.w * params->src_rect.bytes_per_pixel) >= PAGE_SIZE)) {		
+			g2d_mem_outer_cache_flush((void *)GET_START_ADDR_C(params->dst_rect, params->clip), 
+				(unsigned int)GET_RECT_SIZE_C(params->dst_rect, params->clip));
+		} else {
+			stride = GET_STRIDE(params->dst_rect);
+			width_bytes = (params->clip.r - params->clip.l) * params->dst_rect.bytes_per_pixel;
+			
+			cur_addr = (unsigned long)GET_REAL_START_ADDR_C(params->dst_rect, params->clip);
+			end_addr = (unsigned long)GET_REAL_END_ADDR_C(params->dst_rect, params->clip);
+
+			while (cur_addr <= end_addr) {
+				start_paddr = virt2phys((unsigned long)cur_addr);
+				end_paddr = virt2phys((unsigned long)cur_addr + width_bytes);
+				
+				if (((end_paddr - start_paddr) > 0) && ((end_paddr -start_paddr) < PAGE_SIZE)) {
+					outer_flush_range(start_paddr, end_paddr);
+				} else {
+					outer_flush_range(start_paddr, ((start_paddr + PAGE_SIZE) & PAGE_MASK) - 1);
+					outer_flush_range(end_paddr & PAGE_MASK, end_paddr);
+				}
+				cur_addr += stride;
+			}	
+		}
+	}
+}
+
+void g2d_mem_cache_oneshot(void *src_addr,  void *dst_addr, unsigned long src_size, unsigned long dst_size)
+{
+ 	unsigned long paddr;
+        	void *cur_addr, *end_addr;
+	unsigned long full_size;
+
+	full_size = src_size + dst_size;
+
+	if(full_size < L1_ALL_THRESHOLD_SIZE)
+		dmac_map_area(src_addr, src_size, DMA_TO_DEVICE);
+	else
+		flush_all_cpu_caches();
+
+	if(full_size > L2_ALL_THRESHOLD_SIZE) {
+		outer_flush_all();
+		return;
+	}
+
+	cur_addr = (void *)((unsigned long)src_addr & PAGE_MASK);
+	src_size = PAGE_ALIGN(src_size);
+	end_addr = cur_addr + src_size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}   
+
+	if(full_size < L1_ALL_THRESHOLD_SIZE)
+		dmac_flush_range(dst_addr, dst_addr + dst_size);
+
+	cur_addr = (void *)((unsigned long)dst_addr & PAGE_MASK);
+	dst_size = PAGE_ALIGN(dst_size);
+	end_addr = cur_addr + dst_size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_flush_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+u32 g2d_mem_cache_op(unsigned int cmd, void *addr, unsigned int size)
+{
+	switch(cmd) {
+	case G2D_DMA_CACHE_CLEAN :
+		g2d_mem_outer_cache_clean((void *)addr, size);
+		break;	
+	case G2D_DMA_CACHE_FLUSH :
+		g2d_mem_outer_cache_flush((void *)addr, size);
+		break;
+	default :
+		return false;
+		break;		
+	}	
+
+	return true;
+}
+
+void g2d_mem_outer_cache_flush(void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	size = PAGE_ALIGN(size);
+	end_addr = cur_addr + size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {            
+			outer_flush_range(paddr, paddr + PAGE_SIZE);
+		}
+	cur_addr += PAGE_SIZE;
+	}   
+}
+
+void g2d_mem_outer_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	size = PAGE_ALIGN(size);
+	end_addr = cur_addr + size + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		paddr = virt2phys((unsigned long)cur_addr);
+		if (paddr) {
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+void g2d_mem_outer_cache_inv(g2d_params *params)
+{
+ 	unsigned long start_paddr, end_paddr;
+	unsigned long cur_addr, end_addr;
+	unsigned long stride;
+	
+	stride = GET_STRIDE(params->dst_rect);
+	cur_addr = (unsigned long)GET_START_ADDR_C(params->dst_rect, params->clip);
+	end_addr = cur_addr + (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+
+	start_paddr = virt2phys((unsigned long)cur_addr);
+	outer_inv_range(start_paddr, (start_paddr & PAGE_MASK) + (PAGE_SIZE - 1));
+	cur_addr = ((unsigned long)cur_addr & PAGE_MASK) + PAGE_SIZE;
+
+	while (cur_addr < end_addr) {
+		start_paddr = virt2phys((unsigned long)cur_addr);		
+		if ((cur_addr + PAGE_SIZE) > end_addr) {		
+			end_paddr = virt2phys((unsigned long)end_addr);
+			outer_inv_range(start_paddr, end_paddr);
+			break;
+		}
+
+		if (start_paddr) {
+			outer_inv_range(start_paddr, start_paddr + PAGE_SIZE);
+		}
+		cur_addr += PAGE_SIZE;
+	}
+}
+
+int g2d_check_need_dst_cache_clean(g2d_params * params)
+{
+	unsigned long cur_addr, end_addr;
+	cur_addr = (unsigned long)GET_START_ADDR_C(params->dst_rect, params->clip);
+	end_addr = cur_addr + (unsigned long)GET_RECT_SIZE_C(params->dst_rect, params->clip);
+	
+	if ((params->src_rect.color_format == G2D_RGB_565) &&
+		(params->flag.alpha_val == G2D_ALPHA_BLENDING_OPAQUE) &&
+		(params->dst_rect.full_w == (params->clip.r - params->clip.l)) &&
+		(cur_addr % 32 == 0) && (end_addr % 32 == 0))   {
+		return false;
+	}
+	
+	return true;
+}
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d_core.c b/drivers/media/video/samsung/fimg2d3x/fimg2d_core.c
new file mode 100644
index 0000000..5b1fe07
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d_core.c
@@ -0,0 +1,314 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d_core.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d core functions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <plat/sysmmu.h>
+#include <linux/sched.h>
+
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+#include <mach/media.h>
+#include <plat/media.h>
+#endif
+
+#include "fimg2d.h"
+
+int g2d_clk_enable(struct g2d_global *g2d_dev)
+{
+	if(!atomic_read(&g2d_dev->clk_enable_flag)) {
+		clk_enable(g2d_dev->clock);
+		atomic_set(&g2d_dev->clk_enable_flag, 1);
+		return 0;
+	}
+	return -1;
+}
+
+int g2d_clk_disable(struct g2d_global *g2d_dev)
+{
+	if(atomic_read(&g2d_dev->clk_enable_flag)) {
+		if(atomic_read(&g2d_dev->in_use) == 0) {
+			clk_disable(g2d_dev->clock);
+			atomic_set(&g2d_dev->clk_enable_flag, 0);
+			return 0;
+		} 
+	}
+	return -1;
+}
+
+void g2d_sysmmu_on(struct g2d_global *g2d_dev)
+{
+	exynos_sysmmu_enable(g2d_dev->dev,
+			(unsigned long)virt_to_phys((void *)init_mm.pgd));
+}
+
+void g2d_sysmmu_off(struct g2d_global *g2d_dev)
+{
+	exynos_sysmmu_disable(g2d_dev->dev);
+}
+
+void g2d_fail_debug(g2d_params *params)
+{
+	FIMG2D_ERROR("src : %d, %d, %d, %d / %d, %d / 0x%x, %d, 0x%x)\n",
+			params->src_rect.x,
+			params->src_rect.y,
+			params->src_rect.w,
+			params->src_rect.h,
+			params->src_rect.full_w,
+			params->src_rect.full_h,
+			params->src_rect.color_format,
+			params->src_rect.bytes_per_pixel,
+			(u32)params->src_rect.addr);
+	FIMG2D_ERROR("dst : %d, %d, %d, %d / %d, %d / 0x%x, %d, 0x%x)\n",
+			params->dst_rect.x,
+			params->dst_rect.y,
+			params->dst_rect.w,
+			params->dst_rect.h,
+			params->dst_rect.full_w,
+			params->dst_rect.full_h,
+			params->dst_rect.color_format,
+			params->dst_rect.bytes_per_pixel,
+			(u32)params->dst_rect.addr);
+	FIMG2D_ERROR("clip: %d, %d, %d, %d\n",
+			params->clip.t,
+			params->clip.b,
+			params->clip.l,
+			params->clip.r);
+	FIMG2D_ERROR("flag: %d, %d, %d, %d / %d, %d, %d, %d / %d, %d, %d, %d\n",
+			params->flag.rotate_val,
+			params->flag.alpha_val,
+			params->flag.blue_screen_mode,
+			params->flag.color_key_val,
+			params->flag.color_switch_val,
+			params->flag.src_color,
+			params->flag.third_op_mode,
+			params->flag.rop_mode,
+			params->flag.mask_mode,
+			params->flag.render_mode,
+			params->flag.potterduff_mode,
+			params->flag.memory_type);
+}
+
+int g2d_init_regs(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	u32 blt_cmd = 0;
+
+	g2d_rect * src_rect = &params->src_rect;
+	g2d_rect * dst_rect = &params->dst_rect;
+	g2d_clip * clip     = &params->clip;
+	g2d_flag * flag     = &params->flag;
+
+	if (g2d_check_params(params) < 0)
+		return -1;
+
+	g2d_reset(g2d_dev);
+
+	/* source image */	
+	blt_cmd |= g2d_set_src_img(g2d_dev, src_rect, flag);    
+
+	/* destination image */		
+	blt_cmd |= g2d_set_dst_img(g2d_dev, dst_rect);
+
+	/* rotation */
+	blt_cmd |= g2d_set_rotation(g2d_dev, flag);
+
+	/* clipping */
+	blt_cmd |= g2d_set_clip_win(g2d_dev, clip);
+
+	/* color key */
+	blt_cmd |= g2d_set_color_key(g2d_dev, flag);
+
+	/* pattern */	
+	blt_cmd |= g2d_set_pattern(g2d_dev, src_rect, flag);
+
+	/* rop & alpha blending */
+	blt_cmd |= g2d_set_alpha(g2d_dev, flag);
+
+	/* command */
+	g2d_set_bitblt_cmd(g2d_dev, src_rect, dst_rect, clip, blt_cmd);
+
+	return 0;
+}
+
+int g2d_check_overlap(g2d_rect src_rect, g2d_rect dst_rect, g2d_clip clip)
+{
+	unsigned int src_start_addr;
+	unsigned int src_end_addr;
+	unsigned int dst_start_addr;
+	unsigned int dst_end_addr;
+
+	src_start_addr = (unsigned int)GET_START_ADDR(src_rect);
+	src_end_addr = src_start_addr + (unsigned int)GET_RECT_SIZE(src_rect);
+	dst_start_addr = (unsigned int)GET_START_ADDR_C(dst_rect, clip);
+	dst_end_addr = dst_start_addr + (unsigned int)GET_RECT_SIZE_C(dst_rect, clip);
+
+	if ((dst_start_addr >= src_start_addr) && (dst_start_addr <= src_end_addr))
+		return true;
+	if ((dst_end_addr >= src_start_addr) && (dst_end_addr <= src_end_addr))
+		return true;
+	if ((src_start_addr >= dst_start_addr) && (src_end_addr <= dst_end_addr))
+		return true;
+
+	return false;
+}
+
+int g2d_do_blit(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	unsigned long 	pgd;
+	int need_dst_clean = true;
+
+	if ((params->src_rect.addr == NULL) 
+		|| (params->dst_rect.addr == NULL)) {
+		FIMG2D_ERROR("error : addr Null\n");
+		return false;
+	}		
+
+	if (params->flag.memory_type == G2D_MEMORY_KERNEL) {
+		params->src_rect.addr = (unsigned char *)phys_to_virt((unsigned long)params->src_rect.addr);
+		params->dst_rect.addr = (unsigned char *)phys_to_virt((unsigned long)params->dst_rect.addr);
+		pgd = (unsigned long)init_mm.pgd;
+	} else {
+		pgd = (unsigned long)current->mm->pgd;
+	}
+
+	if (params->flag.memory_type == G2D_MEMORY_USER)
+	{
+		g2d_clip clip_src;
+		g2d_clip_for_src(&params->src_rect, &params->dst_rect, &params->clip, &clip_src);
+
+		if (g2d_check_overlap(params->src_rect, params->dst_rect, params->clip))
+			return false;
+
+		g2d_dev->src_attribute =
+			g2d_check_pagetable((unsigned char *)GET_START_ADDR(params->src_rect),
+				(unsigned int)GET_RECT_SIZE(params->src_rect) + 8,
+					(u32)virt_to_phys((void *)pgd));
+		if (g2d_dev->src_attribute == G2D_PT_NOTVALID) {
+			FIMG2D_DEBUG("Src is not in valid pagetable\n");
+			return false;
+		}
+
+		g2d_dev->dst_attribute = 
+			g2d_check_pagetable((unsigned char *)GET_START_ADDR_C(params->dst_rect, params->clip),
+				(unsigned int)GET_RECT_SIZE_C(params->dst_rect, params->clip),
+					(u32)virt_to_phys((void *)pgd));
+		if (g2d_dev->dst_attribute == G2D_PT_NOTVALID) {
+			FIMG2D_DEBUG("Dst is not in valid pagetable\n");
+			return false;
+		}
+
+		g2d_pagetable_clean((unsigned char *)GET_START_ADDR(params->src_rect),
+				(u32)GET_RECT_SIZE(params->src_rect) + 8,
+				(u32)virt_to_phys((void *)pgd));
+		g2d_pagetable_clean((unsigned char *)GET_START_ADDR_C(params->dst_rect, params->clip),
+				(u32)GET_RECT_SIZE_C(params->dst_rect, params->clip),
+				(u32)virt_to_phys((void *)pgd));
+
+		if (params->flag.render_mode & G2D_CACHE_OP) {
+			/*g2d_mem_cache_oneshot((void *)GET_START_ADDR(params->src_rect), 
+				(void *)GET_START_ADDR(params->dst_rect),
+				(unsigned int)GET_REAL_SIZE(params->src_rect), 
+				(unsigned int)GET_REAL_SIZE(params->dst_rect));*/
+		//	need_dst_clean = g2d_check_need_dst_cache_clean(params);
+			g2d_mem_inner_cache(params);
+			g2d_mem_outer_cache(g2d_dev, params, &need_dst_clean);
+		}
+	}
+
+	exynos_sysmmu_disable(g2d_dev->dev);
+	exynos_sysmmu_enable(g2d_dev->dev, (u32)virt_to_phys((void *)pgd));
+
+	if(g2d_init_regs(g2d_dev, params) < 0) {
+		return false;
+	}
+
+	/* Do bitblit */
+	g2d_start_bitblt(g2d_dev, params);
+
+	if (!need_dst_clean)
+		g2d_mem_outer_cache_inv(params);
+
+	return true;
+}
+
+int g2d_wait_for_finish(struct g2d_global *g2d_dev, g2d_params *params)
+{
+	if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+		FIMG2D_ERROR("error : sysmmu_faulted early\n");
+		FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+		g2d_fail_debug(params);
+		atomic_set(&g2d_dev->is_mmu_faulted, 0);
+		return false;
+	}
+
+	if (params->flag.render_mode & G2D_POLLING) {
+		g2d_check_fifo_state_wait(g2d_dev);
+	} else {
+		if(wait_event_interruptible_timeout(g2d_dev->waitq,
+					g2d_dev->irq_handled == 1,
+					msecs_to_jiffies(G2D_TIMEOUT)) == 0) {
+			if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+				FIMG2D_ERROR("error : sysmmu_faulted\n");
+				FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+			} else {
+				g2d_reset(g2d_dev);
+				FIMG2D_ERROR("error : waiting for interrupt is timeout\n");
+			}
+			atomic_set(&g2d_dev->is_mmu_faulted, 0);
+			g2d_fail_debug(params);
+			return false;
+		} else if(atomic_read(&g2d_dev->is_mmu_faulted) == 1) {
+			FIMG2D_ERROR("error : sysmmu_faulted but auto recoveried\n");
+			FIMG2D_ERROR("faulted addr: 0x%x\n", g2d_dev->faulted_addr);
+			g2d_fail_debug(params);
+			atomic_set(&g2d_dev->is_mmu_faulted, 0);
+			return false;
+		}
+	}
+	return true;
+}
+
+int g2d_init_mem(struct device *dev, unsigned int *base, unsigned int *size)
+{
+#ifdef CONFIG_S5P_MEM_CMA
+	struct cma_info mem_info;
+	int err;
+	char cma_name[8];
+#endif
+
+#ifdef CONFIG_S5P_MEM_CMA
+	/* CMA */
+	sprintf(cma_name, "fimg2d");
+	err = cma_info(&mem_info, dev, 0);
+	FIMG2D_DEBUG("[cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		FIMG2D_ERROR("%s: get cma info failed\n", __func__);
+		return -1;
+	}
+	*size = mem_info.total_size;
+	*base = (dma_addr_t)cma_alloc
+		(dev, cma_name, (size_t)(*size), 0);
+
+	FIMG2D_DEBUG("size = 0x%x\n", *size);
+	FIMG2D_DEBUG("*base phys= 0x%x\n", *base);
+	FIMG2D_DEBUG("*base virt = 0x%x\n", (u32)phys_to_virt(*base));
+
+#else
+	*base = s5p_get_media_memory_bank(S5P_MDEV_FIMG2D, 0);
+#endif
+	return 0;
+}
+
diff --git a/drivers/media/video/samsung/fimg2d3x/fimg2d_dev.c b/drivers/media/video/samsung/fimg2d3x/fimg2d_dev.c
new file mode 100644
index 0000000..5ccde4a
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d3x/fimg2d_dev.c
@@ -0,0 +1,609 @@
+/* drivers/media/video/samsung/fimg2d3x/fimg2d3x_dev.c
+ *
+ * Copyright  2010 Samsung Electronics Co, Ltd. All Rights Reserved. 
+ *		      http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file implements fimg2d driver.
+ */
+
+#include <linux/init.h>
+
+#include <linux/moduleparam.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include <asm/uaccess.h>
+#include <linux/miscdevice.h>
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/init.h>
+#include <linux/semaphore.h>
+
+#include <asm/io.h>
+
+#include <mach/cpufreq.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+#include <linux/pm_runtime.h>
+#endif 
+
+#include "fimg2d.h"
+#include "fimg2d3x_regs.h"
+
+#include <linux/smp.h>
+
+struct g2d_global *g2d_dev;
+
+int g2d_sysmmu_fault(unsigned int faulted_addr, unsigned int pt_base)
+{
+	g2d_reset(g2d_dev);
+
+	atomic_set(&g2d_dev->is_mmu_faulted, 1);
+
+	g2d_dev->faulted_addr = faulted_addr;
+
+	wake_up_interruptible(&g2d_dev->waitq);
+
+	return 0;
+}
+
+
+irqreturn_t g2d_irq(int irq, void *dev_id)
+{
+	g2d_set_int_finish(g2d_dev);
+
+	g2d_dev->irq_handled = 1;
+
+	wake_up_interruptible(&g2d_dev->waitq);
+
+	atomic_set(&g2d_dev->in_use, 0);
+
+	return IRQ_HANDLED;
+}
+
+
+static int g2d_open(struct inode *inode, struct file *file)
+{
+	atomic_inc(&g2d_dev->num_of_object);
+
+	FIMG2D_DEBUG("Context Opened %d\n", atomic_read(&g2d_dev->num_of_object));
+
+	return 0;
+}
+
+
+static int g2d_release(struct inode *inode, struct file *file)
+{
+	atomic_dec(&g2d_dev->num_of_object);
+
+	FIMG2D_DEBUG("Context Closed %d\n", atomic_read(&g2d_dev->num_of_object));
+
+	return 0;
+}
+
+static int g2d_mmap(struct file* filp, struct vm_area_struct *vma) 
+{
+	return 0;
+}
+
+
+static long g2d_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	g2d_params params;
+	int ret = -1;
+
+	struct g2d_dma_info dma_info;
+
+	switch(cmd) {
+	case G2D_GET_MEMORY :
+		ret =  copy_to_user((unsigned int *)arg,
+			&(g2d_dev->reserved_mem.base), sizeof(g2d_dev->reserved_mem.base));
+		if (ret) {
+			FIMG2D_ERROR("error : copy_to_user\n");
+			return -EINVAL;
+		}
+		return 0;
+
+	case G2D_GET_MEMORY_SIZE :
+		ret =  copy_to_user((unsigned int *)arg,
+			&(g2d_dev->reserved_mem.size), sizeof(g2d_dev->reserved_mem.size));
+		if (ret) {
+			FIMG2D_ERROR("error : copy_to_user\n");
+			return -EINVAL;
+		}
+		return 0;
+
+	case G2D_DMA_CACHE_CLEAN :
+	case G2D_DMA_CACHE_FLUSH :
+		mutex_lock(&g2d_dev->lock);
+		ret = copy_from_user(&dma_info, (struct g2d_dma_info *)arg, sizeof(dma_info));
+
+		if (ret) {
+			FIMG2D_ERROR("error : copy_from_user\n");
+			mutex_unlock(&g2d_dev->lock);
+			return -EINVAL;
+		}
+
+		if (dma_info.addr == 0) {
+			FIMG2D_ERROR("addr Null Error!!!\n");                
+			mutex_unlock(&g2d_dev->lock);
+			return -EINVAL;
+		}
+
+		g2d_mem_cache_op(cmd, (void *)dma_info.addr, dma_info.size);
+		mutex_unlock(&g2d_dev->lock);
+		return 0;
+
+	case G2D_SYNC :
+		g2d_check_fifo_state_wait(g2d_dev);
+		ret = 0;
+		goto g2d_ioctl_done;
+
+	case G2D_RESET :
+		g2d_reset(g2d_dev);
+		FIMG2D_ERROR("G2D TimeOut Error\n");
+		ret = 0;
+		goto g2d_ioctl_done;
+		
+	case G2D_BLIT:
+		if  (atomic_read(&g2d_dev->ready_to_run) == 0)
+			goto g2d_ioctl_done2;
+		
+		mutex_lock(&g2d_dev->lock);
+		
+		g2d_clk_enable(g2d_dev);
+
+		if (copy_from_user(&params, (struct g2d_params *)arg, sizeof(g2d_params))) {
+			FIMG2D_ERROR("error : copy_from_user\n");
+			goto g2d_ioctl_done;
+		}
+
+		atomic_set(&g2d_dev->in_use, 1);
+		if (atomic_read(&g2d_dev->ready_to_run) == 0)
+			goto g2d_ioctl_done;
+
+		if (params.flag.memory_type == G2D_MEMORY_USER)
+			down_write(&page_alloc_slow_rwsem);
+
+		g2d_dev->irq_handled = 0;
+		if (!g2d_do_blit(g2d_dev, &params)) {
+			g2d_dev->irq_handled = 1;
+			if (params.flag.memory_type == G2D_MEMORY_USER)
+				up_write(&page_alloc_slow_rwsem);
+			goto g2d_ioctl_done;
+		}
+
+		if(!(file->f_flags & O_NONBLOCK)) {
+			if (!g2d_wait_for_finish(g2d_dev, &params)) {
+				if (params.flag.memory_type == G2D_MEMORY_USER)
+					up_write(&page_alloc_slow_rwsem);
+				goto g2d_ioctl_done;
+			}
+		}
+
+		if (params.flag.memory_type == G2D_MEMORY_USER)
+			up_write(&page_alloc_slow_rwsem);
+		ret = 0;
+
+		break;
+	default :
+		goto g2d_ioctl_done2;
+		break;
+	}
+
+g2d_ioctl_done :
+
+	g2d_clk_disable(g2d_dev);
+
+	mutex_unlock(&g2d_dev->lock);
+
+	atomic_set(&g2d_dev->in_use, 0);
+
+g2d_ioctl_done2 :
+
+	return ret;
+}
+
+static unsigned int g2d_poll(struct file *file, poll_table *wait)
+{
+	unsigned int mask = 0;
+
+	if (atomic_read(&g2d_dev->in_use) == 0) {
+		mask = POLLOUT | POLLWRNORM;
+		g2d_clk_disable(g2d_dev);
+		
+		mutex_unlock(&g2d_dev->lock);
+
+	} else {
+		poll_wait(file, &g2d_dev->waitq, wait);
+
+		if(atomic_read(&g2d_dev->in_use) == 0) {
+			mask = POLLOUT | POLLWRNORM;
+			g2d_clk_disable(g2d_dev);
+			
+			mutex_unlock(&g2d_dev->lock);
+		}
+	}
+	
+	return mask;
+}
+
+static struct file_operations fimg2d_fops = {
+	.owner 		= THIS_MODULE,
+	.open 		= g2d_open,
+	.release 	= g2d_release,
+	.mmap 		= g2d_mmap,
+	.unlocked_ioctl = g2d_ioctl,
+	.poll		= g2d_poll,
+};
+
+
+static struct miscdevice fimg2d_dev = {
+	.minor		= G2D_MINOR,
+	.name		= "fimg2d",
+	.fops		= &fimg2d_fops,
+};
+
+static int g2d_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+	struct clk *parent;
+	struct clk *sclk;
+	
+	FIMG2D_DEBUG("start probe : name=%s num=%d res[0].start=0x%x res[1].start=0x%x\n",
+	        			pdev->name, pdev->num_resources, 
+	        			pdev->resource[0].start, pdev->resource[1].start);
+
+	/* alloc g2d global */
+	g2d_dev = kzalloc(sizeof(*g2d_dev), GFP_KERNEL);
+	if (!g2d_dev) {
+		FIMG2D_ERROR( "not enough memory\n");
+		ret = -ENOENT;
+		goto probe_out;
+	}
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* to use the runtime PM helper functions */
+	pm_runtime_enable(&pdev->dev);
+	/* enable the power domain */
+	pm_runtime_get_sync(&pdev->dev);
+#endif
+
+	/* get the memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if(res == NULL) {
+		FIMG2D_ERROR("failed to get memory region resouce\n");
+		ret = -ENOENT;
+		goto err_get_res;
+	}
+
+	/* request momory region */
+	g2d_dev->mem = request_mem_region(res->start, 
+					          res->end - res->start + 1, 
+					          pdev->name);
+	if(g2d_dev->mem == NULL) {
+		FIMG2D_ERROR("failed to reserve memory region\n");
+		ret = -ENOENT;
+		goto err_mem_req;
+	}
+	
+	/* ioremap */
+	g2d_dev->base = ioremap(g2d_dev->mem->start, 
+				g2d_dev->mem->end - res->start + 1);
+	if(g2d_dev->base == NULL) {
+		FIMG2D_ERROR("failed ioremap\n");
+		ret = -ENOENT;
+		goto err_mem_map;
+	}
+
+	/* get irq */
+	g2d_dev->irq_num = platform_get_irq(pdev, 0);
+	if(g2d_dev->irq_num <= 0) {
+		FIMG2D_ERROR("failed to get irq resouce\n");
+		ret = -ENOENT;
+		goto err_irq_req;
+	}
+
+	/* blocking I/O */
+	init_waitqueue_head(&g2d_dev->waitq);
+
+	/* request irq */
+	ret = request_irq(g2d_dev->irq_num, g2d_irq, 
+			IRQF_DISABLED, pdev->name, NULL);
+	if (ret) {
+		FIMG2D_ERROR("request_irq(g2d) failed.\n");
+		ret = -ENOENT;
+		goto err_irq_req;
+	}
+
+	/* clock domain setting*/
+	parent = clk_get(&pdev->dev, "mout_mpll");
+	if (IS_ERR(parent)) {
+		FIMG2D_ERROR("failed to get parent clock\n");
+		ret = -ENOENT;
+		goto err_clk_get1;
+	}
+
+	sclk = clk_get(&pdev->dev, "sclk_fimg2d");
+	if (IS_ERR(sclk)) {
+		FIMG2D_ERROR("failed to get sclk_g2d clock\n");
+		ret = -ENOENT;
+		goto err_clk_get2;
+	}
+
+	clk_set_parent(sclk, parent);
+	clk_set_rate(sclk, 267 * MHZ);	/* 266 Mhz */
+
+	/* clock for gating  */
+	g2d_dev->clock = clk_get(&pdev->dev, "fimg2d");
+	if (IS_ERR(g2d_dev->clock)) {
+		FIMG2D_ERROR("failed to get clock clock\n");
+		ret = -ENOENT;
+		goto err_clk_get3;
+	}
+
+	ret = g2d_init_mem(&pdev->dev, &g2d_dev->reserved_mem.base, &g2d_dev->reserved_mem.size);
+
+	if (ret != 0) {
+		FIMG2D_ERROR("failed to init. fimg2d mem");
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	/* atomic init */
+	atomic_set(&g2d_dev->in_use, 0);
+	atomic_set(&g2d_dev->num_of_object, 0);
+	atomic_set(&g2d_dev->is_mmu_faulted, 0);
+	g2d_dev->faulted_addr = 0;
+
+	/* misc register */
+	ret = misc_register(&fimg2d_dev);
+	if (ret) {
+		FIMG2D_ERROR("cannot register miscdev on minor=%d (%d)\n",
+			G2D_MINOR, ret);
+		ret = -ENOMEM;
+		goto err_misc_reg;
+	}
+
+	mutex_init(&g2d_dev->lock);
+
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+	g2d_dev->early_suspend.suspend = g2d_early_suspend;
+	g2d_dev->early_suspend.resume = g2d_late_resume;
+	g2d_dev->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+	register_early_suspend(&g2d_dev->early_suspend);
+#endif
+
+	g2d_dev->dev = &pdev->dev;
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+	g2d_sysmmu_on(g2d_dev);
+
+	FIMG2D_DEBUG("g2d_probe ok!\n");
+
+	return 0;
+
+err_misc_reg:
+err_mem:
+	clk_put(g2d_dev->clock);
+	g2d_dev->clock = NULL;	
+err_clk_get3:
+	clk_put(sclk);
+err_clk_get2:
+	clk_put(parent);
+err_clk_get1:
+	free_irq(g2d_dev->irq_num, NULL);
+err_irq_req:
+	iounmap(g2d_dev->base);
+err_mem_map:
+	release_resource(g2d_dev->mem);
+	kfree(g2d_dev->mem);
+err_mem_req:	
+err_get_res:
+	kfree(g2d_dev);
+probe_out:
+	FIMG2D_ERROR("g2d: sec_g2d_probe fail!\n");
+	return ret;
+}
+
+
+static int g2d_remove(struct platform_device *dev)
+{
+	FIMG2D_DEBUG("g2d_remove called !\n");
+
+	free_irq(g2d_dev->irq_num, NULL);
+
+	if (g2d_dev->mem != NULL) {   
+		FIMG2D_INFO("releasing resource\n");
+		iounmap(g2d_dev->base);
+		release_resource(g2d_dev->mem);
+		kfree(g2d_dev->mem);
+	}
+
+	misc_deregister(&fimg2d_dev);
+
+	atomic_set(&g2d_dev->in_use, 0);
+	atomic_set(&g2d_dev->num_of_object, 0);
+
+	g2d_clk_disable(g2d_dev);
+
+	if (g2d_dev->clock) {
+		clk_put(g2d_dev->clock);
+		g2d_dev->clock = NULL;
+	}
+
+	mutex_destroy(&g2d_dev->lock);
+	
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+	unregister_early_suspend(&g2d_dev->early_suspend);
+#endif
+
+	kfree(g2d_dev);
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(&dev->dev);
+	pm_runtime_disable(&dev->dev);
+#endif
+
+	FIMG2D_DEBUG("g2d_remove ok!\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_HAS_EARLYSUSPEND)
+void g2d_early_suspend(struct early_suspend *h)
+{
+	atomic_set(&g2d_dev->ready_to_run, 0);
+
+	/* wait until G2D running is finished */
+	while(1) {
+		if (!atomic_read(&g2d_dev->in_use))
+			break;
+		
+		msleep_interruptible(2);
+	}
+	
+	g2d_sysmmu_off(g2d_dev);
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(g2d_dev->dev);
+#endif
+}
+
+void g2d_late_resume(struct early_suspend *h)
+{
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* enable the power domain */
+	pm_runtime_get_sync(g2d_dev->dev);
+#endif
+
+	g2d_sysmmu_on(g2d_dev);
+
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+}
+#endif
+
+#if !defined(CONFIG_HAS_EARLYSUSPEND)
+static int g2d_suspend(struct platform_device *dev, pm_message_t state)
+{
+	atomic_set(&g2d_dev->ready_to_run, 0);
+
+	/* wait until G2D running is finished */
+	while(1) {
+		if (!atomic_read(&g2d_dev->in_use))
+			break;
+		
+		msleep_interruptible(2);
+	}
+	
+	g2d_sysmmu_off(g2d_dev);
+	
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* disable the power domain */
+	pm_runtime_put(g2d_dev->dev);
+#endif	
+
+	return 0;
+}
+static int g2d_resume(struct platform_device *pdev)
+{
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+	/* enable the power domain */
+	pm_runtime_get_sync(g2d_dev->dev);
+#endif
+
+	g2d_sysmmu_on(g2d_dev);
+
+	atomic_set(&g2d_dev->ready_to_run, 1);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_EXYNOS_DEV_PD)
+static int g2d_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int g2d_runtime_resume(struct device *dev)
+{
+	return 0;
+}
+
+static const struct dev_pm_ops g2d_pm_ops = {
+	.runtime_suspend = g2d_runtime_suspend,
+	.runtime_resume = g2d_runtime_resume,
+};
+#endif
+
+
+static struct platform_driver fimg2d_driver = {
+	.probe		= g2d_probe,
+	.remove		= g2d_remove,
+#if !defined(CONFIG_HAS_EARLYSUSPEND)
+	.suspend	= g2d_suspend,
+	.resume		= g2d_resume,
+#endif
+	.driver		= {
+				.owner	= THIS_MODULE,
+				.name	= "s5p-fimg2d",
+#if defined(CONFIG_EXYNOS_DEV_PD)
+				.pm	= &g2d_pm_ops,
+#endif
+			},
+};
+
+int __init g2d_init(void)
+{
+ 	if(platform_driver_register(&fimg2d_driver)!=0) {
+   		FIMG2D_ERROR("platform device register Failed \n");
+   		return -1;
+  	}
+
+	FIMG2D_DEBUG("ok!\n");
+
+	return 0;
+}
+
+void  g2d_exit(void)
+{
+	platform_driver_unregister(&fimg2d_driver);
+
+	FIMG2D_DEBUG("ok!\n");
+}
+
+module_init(g2d_init);
+module_exit(g2d_exit);
+
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("SEC G2D Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/Kconfig b/drivers/media/video/samsung/fimg2d4x-exynos4/Kconfig
new file mode 100644
index 0000000..51294d7
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/Kconfig
@@ -0,0 +1,23 @@
+# drivers/media/video/samsung/fimg2d4x/Kconfig
+#
+# Copyright (c) 2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+config VIDEO_FIMG2D4X
+	bool "Samsung Graphics 2D Driver"
+	select VIDEO_FIMG2D
+	depends on VIDEO_SAMSUNG && (CPU_EXYNOS4212 || CPU_EXYNOS4412 || CPU_EXYNOS5250)
+	default n
+	---help---
+	  This is a graphics 2D (FIMG2D 4.x) driver for Samsung ARM based SoC.
+
+config VIDEO_FIMG2D4X_DEBUG
+	bool "Enables FIMG2D debug messages"
+	select VIDEO_FIMG2D_DEBUG
+	depends on VIDEO_FIMG2D4X
+	default n
+	---help---
+	  This enables FIMG2D driver debug messages.
+
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/Makefile b/drivers/media/video/samsung/fimg2d4x-exynos4/Makefile
new file mode 100644
index 0000000..40b93a9
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/Makefile
@@ -0,0 +1,18 @@
+# drivers/media/video/samsung/fimg2d4x/Makefile
+#
+# Copyright (c) 2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+obj-$(CONFIG_VIDEO_FIMG2D) += fimg2d_drv.o fimg2d_ctx.o fimg2d_cache.o fimg2d_clk.o fimg2d_helper.o
+obj-$(CONFIG_VIDEO_FIMG2D4X) += fimg2d4x_blt.o fimg2d4x_hw.o
+
+ifeq ($(CONFIG_VIDEO_FIMG2D_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d.h
new file mode 100644
index 0000000..97fc4cb
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d.h
@@ -0,0 +1,509 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_H
+#define __FIMG2D_H __FILE__
+
+#ifdef __KERNEL__
+
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/atomic.h>
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+
+#define FIMG2D_MINOR			(240)
+#define to_fimg2d_plat(d)		(to_platform_device(d)->dev.platform_data)
+
+#ifdef CONFIG_VIDEO_FIMG2D_DEBUG
+#define fimg2d_debug(fmt, arg...)	printk(KERN_INFO "[%s] " fmt, __func__, ## arg)
+#else
+#define fimg2d_debug(fmt, arg...)	do { } while (0)
+#endif
+
+#endif /* __KERNEL__ */
+
+/* ioctl commands */
+#define FIMG2D_IOCTL_MAGIC	'F'
+#define FIMG2D_BITBLT_BLIT	_IOWR(FIMG2D_IOCTL_MAGIC, 0, struct fimg2d_blit)
+#define FIMG2D_BITBLT_SYNC	_IOW(FIMG2D_IOCTL_MAGIC, 1, int)
+#define FIMG2D_BITBLT_VERSION	_IOR(FIMG2D_IOCTL_MAGIC, 2, struct fimg2d_version)
+
+struct fimg2d_version {
+	unsigned int hw;
+	unsigned int sw;
+};
+
+/**
+ * @BLIT_SYNC: sync mode, to wait for blit done irq
+ * @BLIT_ASYNC: async mode, not to wait for blit done irq
+ *
+ */
+enum blit_sync {
+	BLIT_SYNC,
+	BLIT_ASYNC,
+};
+
+/**
+ * @ADDR_PHYS: physical address
+ * @ADDR_USER: user virtual address (physically Non-contiguous)
+ * @ADDR_USER_CONTIG: user virtual address (physically Contiguous)
+ * @ADDR_DEVICE: specific device virtual address
+ */
+enum addr_space {
+	ADDR_NONE,
+	ADDR_PHYS,
+	ADDR_KERN,
+	ADDR_USER,
+	ADDR_USER_CONTIG,
+	ADDR_DEVICE,
+};
+
+/**
+ * Pixel order complies with little-endian style
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum pixel_order {
+	AX_RGB = 0,
+	RGB_AX,
+	AX_BGR,
+	BGR_AX,
+	ARGB_ORDER_END,
+
+	P1_CRY1CBY0,
+	P1_CBY1CRY0,
+	P1_Y1CRY0CB,
+	P1_Y1CBY0CR,
+	P1_ORDER_END,
+
+	P2_CRCB,
+	P2_CBCR,
+	P2_ORDER_END,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum color_format {
+	CF_XRGB_8888 = 0,
+	CF_ARGB_8888,
+	CF_RGB_565,
+	CF_XRGB_1555,
+	CF_ARGB_1555,
+	CF_XRGB_4444,
+	CF_ARGB_4444,
+	CF_RGB_888,
+	CF_YCBCR_444,
+	CF_YCBCR_422,
+	CF_YCBCR_420,
+	CF_A8,
+	CF_L8,
+	SRC_DST_FORMAT_END,
+
+	CF_MSK_1BIT,
+	CF_MSK_4BIT,
+	CF_MSK_8BIT,
+	CF_MSK_16BIT_565,
+	CF_MSK_16BIT_1555,
+	CF_MSK_16BIT_4444,
+	CF_MSK_32BIT_8888,
+	MSK_FORMAT_END,
+};
+
+enum rotation {
+	ORIGIN,
+	ROT_90,	/* clockwise */
+	ROT_180,
+	ROT_270,
+	XFLIP,	/* x-axis flip */
+	YFLIP,	/* y-axis flip */
+};
+
+/**
+ * @NO_REPEAT: no effect
+ * @REPEAT_NORMAL: repeat horizontally and vertically
+ * @REPEAT_PAD: pad with pad color
+ * @REPEAT_REFLECT: reflect horizontally and vertically
+ * @REPEAT_CLAMP: pad with edge color of original image
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum repeat {
+	NO_REPEAT = 0,
+	REPEAT_NORMAL,	/* default setting */
+	REPEAT_PAD,
+	REPEAT_REFLECT, REPEAT_MIRROR = REPEAT_REFLECT,
+	REPEAT_CLAMP,
+};
+
+enum scaling {
+	NO_SCALING,
+	SCALING_NEAREST,
+	SCALING_BILINEAR,
+};
+
+/**
+ * @SCALING_PIXELS: ratio in pixels
+ * @SCALING_RATIO: ratio in fixed point 16
+ */
+enum scaling_factor {
+	SCALING_PIXELS,
+	SCALING_RATIO,
+};
+
+/**
+ * premultiplied alpha
+ */
+enum premultiplied {
+	PREMULTIPLIED,
+	NON_PREMULTIPLIED,
+};
+
+/**
+ * @TRANSP: discard bluescreen color
+ * @BLUSCR: replace bluescreen color with background color
+ */
+enum bluescreen {
+	OPAQUE,
+	TRANSP,
+	BLUSCR,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum blit_op {
+	BLIT_OP_SOLID_FILL = 0,
+
+	BLIT_OP_CLR,
+	BLIT_OP_SRC, BLIT_OP_SRC_COPY = BLIT_OP_SRC,
+	BLIT_OP_DST,
+	BLIT_OP_SRC_OVER,
+	BLIT_OP_DST_OVER, BLIT_OP_OVER_REV = BLIT_OP_DST_OVER,
+	BLIT_OP_SRC_IN,
+	BLIT_OP_DST_IN, BLIT_OP_IN_REV = BLIT_OP_DST_IN,
+	BLIT_OP_SRC_OUT,
+	BLIT_OP_DST_OUT, BLIT_OP_OUT_REV = BLIT_OP_DST_OUT,
+	BLIT_OP_SRC_ATOP,
+	BLIT_OP_DST_ATOP, BLIT_OP_ATOP_REV = BLIT_OP_DST_ATOP,
+	BLIT_OP_XOR,
+
+	BLIT_OP_ADD,
+	BLIT_OP_MULTIPLY,
+	BLIT_OP_SCREEN,
+	BLIT_OP_DARKEN,
+	BLIT_OP_LIGHTEN,
+
+	BLIT_OP_DISJ_SRC_OVER,
+	BLIT_OP_DISJ_DST_OVER, BLIT_OP_SATURATE = BLIT_OP_DISJ_DST_OVER,
+	BLIT_OP_DISJ_SRC_IN,
+	BLIT_OP_DISJ_DST_IN, BLIT_OP_DISJ_IN_REV = BLIT_OP_DISJ_DST_IN,
+	BLIT_OP_DISJ_SRC_OUT,
+	BLIT_OP_DISJ_DST_OUT, BLIT_OP_DISJ_OUT_REV = BLIT_OP_DISJ_DST_OUT,
+	BLIT_OP_DISJ_SRC_ATOP,
+	BLIT_OP_DISJ_DST_ATOP, BLIT_OP_DISJ_ATOP_REV = BLIT_OP_DISJ_DST_ATOP,
+	BLIT_OP_DISJ_XOR,
+
+	BLIT_OP_CONJ_SRC_OVER,
+	BLIT_OP_CONJ_DST_OVER, BLIT_OP_CONJ_OVER_REV = BLIT_OP_CONJ_DST_OVER,
+	BLIT_OP_CONJ_SRC_IN,
+	BLIT_OP_CONJ_DST_IN, BLIT_OP_CONJ_IN_REV = BLIT_OP_CONJ_DST_IN,
+	BLIT_OP_CONJ_SRC_OUT,
+	BLIT_OP_CONJ_DST_OUT, BLIT_OP_CONJ_OUT_REV = BLIT_OP_CONJ_DST_OUT,
+	BLIT_OP_CONJ_SRC_ATOP,
+	BLIT_OP_CONJ_DST_ATOP, BLIT_OP_CONJ_ATOP_REV = BLIT_OP_CONJ_DST_ATOP,
+	BLIT_OP_CONJ_XOR,
+
+	/* user select coefficient manually */
+	BLIT_OP_USER_COEFF,
+
+	BLIT_OP_USER_SRC_GA,
+
+	/* Add new operation type here */
+
+	/* end of blit operation */
+	BLIT_OP_END,
+};
+#define MAX_FIMG2D_BLIT_OP (int)BLIT_OP_END
+
+#ifdef __KERNEL__
+
+/**
+ * @TMP: temporary buffer for 2-step blit at a single command
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum image_object {
+	IMAGE_SRC = 0,
+	IMAGE_MSK,
+	IMAGE_TMP,
+	IMAGE_DST,
+	IMAGE_END,
+};
+#define MAX_IMAGES		IMAGE_END
+#define ISRC			IMAGE_SRC
+#define IMSK			IMAGE_MSK
+#define ITMP			IMAGE_TMP
+#define IDST			IMAGE_DST
+#define image_table(u)		\
+	{			\
+		(u)->src,	\
+		(u)->msk,	\
+		(u)->tmp,	\
+		(u)->dst	\
+	}
+
+/**
+ * @size: dma size of image
+ * @cached: cached dma size of image
+ */
+struct fimg2d_dma {
+	unsigned long addr;
+	size_t size;
+	size_t cached;
+};
+
+#endif /* __KERNEL__ */
+
+/**
+ * @start: start address or unique id of image
+ */
+struct fimg2d_addr {
+	enum addr_space type;
+	unsigned long start;
+};
+
+struct fimg2d_rect {
+	int x1;
+	int y1;
+	int x2;	/* x1 + width */
+	int y2; /* y1 + height */
+};
+
+/**
+ * pixels can be different from src, dst or clip rect
+ */
+struct fimg2d_scale {
+	enum scaling mode;
+
+	/* ratio in pixels */
+	int src_w, src_h;
+	int dst_w, dst_h;
+};
+
+struct fimg2d_clip {
+	bool enable;
+	int x1;
+	int y1;
+	int x2;	/* x1 + width */
+	int y2; /* y1 + height */
+};
+
+struct fimg2d_repeat {
+	enum repeat mode;
+	unsigned long pad_color;
+};
+
+/**
+ * @bg_color: bg_color is valid only if bluescreen mode is BLUSCR.
+ */
+struct fimg2d_bluscr {
+	enum bluescreen mode;
+	unsigned long bs_color;
+	unsigned long bg_color;
+};
+
+/**
+ * @plane2: address info for CbCr in YCbCr 2plane mode
+ * @rect: crop/clip rect
+ * @need_cacheopr: true if cache coherency is required
+ */
+struct fimg2d_image {
+	int width;
+	int height;
+	int stride;
+	enum pixel_order order;
+	enum color_format fmt;
+	struct fimg2d_addr addr;
+	struct fimg2d_addr plane2;
+	struct fimg2d_rect rect;
+	bool need_cacheopr;
+};
+
+/**
+ * @solid_color:
+ *         src color instead of src image
+ *         color format and order must be ARGB8888(A is MSB).
+ * @g_alpha: global(constant) alpha. 0xff is opaque, 0 is transparnet
+ * @dither: dithering
+ * @rotate: rotation degree in clockwise
+ * @premult: alpha premultiplied mode for read & write
+ * @scaling: common scaling info for src and mask image.
+ * @repeat: repeat type (tile mode)
+ * @bluscr: blue screen and transparent mode
+ * @clipping: clipping rect within dst rect
+ */
+struct fimg2d_param {
+	unsigned long solid_color;
+	unsigned char g_alpha;
+	bool dither;
+	enum rotation rotate;
+	enum premultiplied premult;
+	struct fimg2d_scale scaling;
+	struct fimg2d_repeat repeat;
+	struct fimg2d_bluscr bluscr;
+	struct fimg2d_clip clipping;
+};
+
+/**
+ * @op: blit operation mode
+ * @src: set when using src image
+ * @msk: set when using mask image
+ * @tmp: set when using 2-step blit at a single command
+ * @dst: dst must not be null
+ *         * tmp image must be the same to dst except memory address
+ * @seq_no: user debugging info.
+ *          for example, user can set sequence number or pid.
+ */
+struct fimg2d_blit {
+	enum blit_op op;
+	struct fimg2d_param param;
+	struct fimg2d_image *src;
+	struct fimg2d_image *msk;
+	struct fimg2d_image *tmp;
+	struct fimg2d_image *dst;
+	enum blit_sync sync;
+	unsigned int seq_no;
+};
+
+#ifdef __KERNEL__
+
+/**
+ * Enables definition to estimate performance.
+ * These debug codes includes printk, so perf
+ * data are unreliable under multi instance environment
+ */
+#undef PERF_PROFILE
+#define PERF_TIMEVAL
+
+enum perf_desc {
+	PERF_INNERCACHE,
+	PERF_OUTERCACHE,
+	PERF_BLIT,
+	PERF_END
+};
+#define MAX_PERF_DESCS		PERF_END
+
+struct fimg2d_perf {
+	int valid;
+#ifdef PERF_TIMEVAL
+	struct timeval start;
+	struct timeval end;
+#else
+	unsigned long long start;
+	unsigned long long end;
+#endif
+};
+
+/**
+ * @pgd: base address of arm mmu pagetable
+ * @ncmd: request count in blit command queue
+ * @wait_q: conext wait queue head
+*/
+struct fimg2d_context {
+	struct mm_struct *mm;
+	atomic_t ncmd;
+	wait_queue_head_t wait_q;
+	struct fimg2d_perf perf[MAX_PERF_DESCS];
+};
+
+/**
+ * @op: blit operation mode
+ * @sync: sync/async blit mode (currently support sync mode only)
+ * @image: array of image object.
+ *         [0] is for src image
+ *         [1] is for mask image
+ *         [2] is for temporary buffer
+ *             set when using 2-step blit at a single command
+ *         [3] is for dst, dst must not be null
+ *         * tmp image must be the same to dst except memory address
+ * @seq_no: user debugging info.
+ *          for example, user can set sequence number or pid.
+ * @dma_all: total dma size of src, msk, dst
+ * @dma: array of dma info for each src, msk, tmp and dst
+ * @ctx: context is created when user open fimg2d device.
+ * @node: list head of blit command queue
+ */
+struct fimg2d_bltcmd {
+	enum blit_op op;
+	enum blit_sync sync;
+	unsigned int seq_no;
+	size_t dma_all;
+	struct fimg2d_param param;
+	struct fimg2d_image image[MAX_IMAGES];
+	struct fimg2d_dma dma[MAX_IMAGES];
+	struct fimg2d_context *ctx;
+	struct list_head node;
+};
+
+/**
+ * @suspended: in suspend mode
+ * @clkon: power status for runtime pm
+ * @mem: resource platform device
+ * @regs: base address of hardware
+ * @dev: pointer to device struct
+ * @err: true if hardware is timed out while blitting
+ * @irq: irq number
+ * @nctx: context count
+ * @busy: 1 if hardware is running
+ * @bltlock: spinlock for blit
+ * @wait_q: blit wait queue head
+ * @cmd_q: blit command queue
+ * @workqueue: workqueue_struct for kfimg2dd
+*/
+struct fimg2d_control {
+	atomic_t suspended;
+	atomic_t clkon;
+	struct clk *clock;
+	struct device *dev;
+	struct device *bus_dev;
+	struct resource *mem;
+	void __iomem *regs;
+
+	bool err;
+	int irq;
+	atomic_t nctx;
+	atomic_t busy;
+	atomic_t active;
+	spinlock_t bltlock;
+	wait_queue_head_t wait_q;
+	struct list_head cmd_q;
+	struct workqueue_struct *work_q;
+
+	void (*blit)(struct fimg2d_control *info);
+	int (*configure)(struct fimg2d_control *info,
+			struct fimg2d_bltcmd *cmd);
+	void (*run)(struct fimg2d_control *info);
+	void (*stop)(struct fimg2d_control *info);
+	void (*dump)(struct fimg2d_control *info);
+	void (*finalize)(struct fimg2d_control *info);
+};
+
+int fimg2d_register_ops(struct fimg2d_control *info);
+
+#endif /* __KERNEL__ */
+
+#endif /* __FIMG2D_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x.h
new file mode 100644
index 0000000..9165d6f
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x.h
@@ -0,0 +1,225 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D4X_H
+#define __FIMG2D4X_H __FILE__
+
+#include "fimg2d4x_regs.h"
+
+/**
+ * @IMG_MEMORY: read from external memory
+ * @IMG_FGCOLOR: read from foreground color
+ * @IMG_BGCOLOR: read from background color
+ */
+enum image_sel {
+	IMG_MEMORY,
+	IMG_FGCOLOR,
+	IMG_BGCOLOR,
+};
+
+/**
+ * @FORWARD_ADDRESSING: read data in forward direction
+ * @REVERSE_ADDRESSING: read data in reverse direction
+ */
+enum addressing {
+	FORWARD_ADDRESSING,
+	REVERSE_ADDRESSING,
+};
+
+/**
+ * The other addressing modes can cause data corruption,
+ * if src and dst are overlapped.
+ */
+enum dir_addressing {
+	UP_FORWARD,
+	DOWN_REVERSE,
+	LEFT_FORWARD,
+	RIGHT_REVERSE,
+	VALID_ADDRESSING_END,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum max_burst_len {
+	MAX_BURST_2 = 0,
+	MAX_BURST_4,
+	MAX_BURST_8,	/* initial value */
+	MAX_BURST_16,
+};
+
+#define DEFAULT_MAX_BURST_LEN		MAX_BURST_8
+
+/**
+ * mask operation type for 16-bpp, 32-bpp mask image
+ * @MSK_ALPHA: use mask alpha for src argb
+ * @MSK_ARGB: use mask argb for src argb
+ * @MSK_MIXED: use mask alpha for src alpha and mask rgb for src rgb
+ */
+enum mask_opr {
+	MSK_ALPHA,	/* initial value */
+	MSK_ARGB,
+	MSK_MIXED,
+};
+
+#define DEFAULT_MSK_OPR		MSK_ALPHA
+
+/**
+ * @ALPHA_PERPIXEL: perpixel alpha
+ * @ALPHA_PERPIXEL_SUM_GLOBAL: perpixel + global
+ * @ALPHA_PERPIXEL_MUL_GLOBAL: perpixel x global
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum alpha_opr {
+	ALPHA_PERPIXEL = 0,	/* initial value */
+	ALPHA_PERPIXEL_SUM_GLOBAL,
+	ALPHA_PERPIXEL_MUL_GLOBAL,
+};
+
+#define DEFAULT_ALPHA_OPR	ALPHA_PERPIXEL
+
+/**
+ * sampling policy at boundary for bilinear scaling
+ * @FOLLOW_REPEAT_MODE: sampling 1 or 2 pixels within bounds
+ * @IGNORE_REPEAT_MODE: sampling 4 pixels according to repeat mode
+ */
+enum boundary_sampling_policy {
+	FOLLOW_REPEAT_MODE,
+	IGNORE_REPEAT_MODE,
+};
+
+#define DEFAULT_BOUNDARY_SAMPLING	FOLLOW_REPEAT_MODE
+
+/**
+ * @COEFF_ONE: 1
+ * @COEFF_ZERO: 0
+ * @COEFF_SA: src alpha
+ * @COEFF_SC: src color
+ * @COEFF_DA: dst alpha
+ * @COEFF_DC: dst color
+ * @COEFF_GA: global(constant) alpha
+ * @COEFF_GC: global(constant) color
+ * @COEFF_DISJ_S:
+ * @COEFF_DISJ_D:
+ * @COEFF_CONJ_S:
+ * @COEFF_CONJ_D:
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum fimg2d_coeff {
+	COEFF_ONE = 0,
+	COEFF_ZERO,
+	COEFF_SA,
+	COEFF_SC,
+	COEFF_DA,
+	COEFF_DC,
+	COEFF_GA,
+	COEFF_GC,
+	COEFF_DISJ_S,
+	COEFF_DISJ_D,
+	COEFF_CONJ_S,
+	COEFF_CONJ_D,
+};
+
+/**
+ * @PREMULT_ROUND_0: (A*B) >> 8
+ * @PREMULT_ROUND_1: (A+1)*B) >> 8
+ * @PREMULT_ROUND_2: (A+(A>>7))* B) >> 8
+ * @PREMULT_ROUND_3: TMP= A*8 + 0x80, (TMP + (TMP >> 8)) >> 8
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum premult_round {
+	PREMULT_ROUND_0 = 0,
+	PREMULT_ROUND_1,
+	PREMULT_ROUND_2,
+	PREMULT_ROUND_3,	/* initial value */
+};
+
+#define DEFAULT_PREMULT_ROUND_MODE	PREMULT_ROUND_3
+
+/**
+ * @BLEND_ROUND_0: (A+1)*B) >> 8
+ * @BLEND_ROUND_1: (A+(A>>7))* B) >> 8
+ * @BLEND_ROUND_2: TMP= A*8 + 0x80, (TMP + (TMP >> 8)) >> 8
+ * @BLEND_ROUND_3: TMP= (A*B + C*D + 0x80), (TMP + (TMP >> 8)) >> 8
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum blend_round {
+	BLEND_ROUND_0 = 0,
+	BLEND_ROUND_1,
+	BLEND_ROUND_2,
+	BLEND_ROUND_3,	/* initial value */
+};
+
+#define DEFAULT_BLEND_ROUND_MODE	BLEND_ROUND_3
+
+struct fimg2d_blend_coeff {
+	bool s_coeff_inv;
+	enum fimg2d_coeff s_coeff;
+	bool d_coeff_inv;
+	enum fimg2d_coeff d_coeff;
+};
+
+void fimg2d4x_reset(struct fimg2d_control *info);
+void fimg2d4x_enable_irq(struct fimg2d_control *info);
+void fimg2d4x_disable_irq(struct fimg2d_control *info);
+void fimg2d4x_clear_irq(struct fimg2d_control *info);
+int fimg2d4x_is_blit_done(struct fimg2d_control *info);
+int fimg2d4x_blit_done_status(struct fimg2d_control *info);
+void fimg2d4x_start_blit(struct fimg2d_control *info);
+void fimg2d4x_set_max_burst_length(struct fimg2d_control *info,
+				enum max_burst_len len);
+void fimg2d4x_set_src_type(struct fimg2d_control *info, enum image_sel type);
+void fimg2d4x_set_src_image(struct fimg2d_control *info,
+				struct fimg2d_image *s);
+void fimg2d4x_set_src_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_set_dst_type(struct fimg2d_control *info, enum image_sel type);
+void fimg2d4x_set_dst_image(struct fimg2d_control *info,
+				struct fimg2d_image *d);
+void fimg2d4x_set_dst_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_enable_msk(struct fimg2d_control *info);
+void fimg2d4x_set_msk_image(struct fimg2d_control *info,
+				struct fimg2d_image *m);
+void fimg2d4x_set_msk_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_set_color_fill(struct fimg2d_control *info, unsigned long color);
+void fimg2d4x_set_premultiplied(struct fimg2d_control *info);
+void fimg2d4x_src_premultiply(struct fimg2d_control *info);
+void fimg2d4x_dst_premultiply(struct fimg2d_control *info);
+void fimg2d4x_dst_depremultiply(struct fimg2d_control *info);
+void fimg2d4x_enable_transparent(struct fimg2d_control *info);
+void fimg2d4x_set_bluescreen(struct fimg2d_control *info,
+				struct fimg2d_bluscr *bluscr);
+void fimg2d4x_enable_clipping(struct fimg2d_control *info,
+				struct fimg2d_clip *clp);
+void fimg2d4x_enable_dithering(struct fimg2d_control *info);
+void fimg2d4x_set_src_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_msk_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_src_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_msk_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_rotation(struct fimg2d_control *info, enum rotation rot);
+void fimg2d4x_set_fgcolor(struct fimg2d_control *info, unsigned long fg);
+void fimg2d4x_set_bgcolor(struct fimg2d_control *info, unsigned long bg);
+void fimg2d4x_enable_alpha(struct fimg2d_control *info, unsigned char g_alpha);
+void fimg2d4x_set_alpha_composite(struct fimg2d_control *info,
+		enum blit_op op, unsigned char g_alpha);
+void fimg2d4x_dump_regs(struct fimg2d_control *info);
+
+#endif /* __FIMG2D4X_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_blt.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_blt.c
new file mode 100644
index 0000000..9a4f8ad
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_blt.c
@@ -0,0 +1,330 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_blt.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <linux/atomic.h>
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+#include <plat/s5p-sysmmu.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <plat/devs.h>
+#include <linux/pm_runtime.h>
+#endif
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+#include "fimg2d4x.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+#define BLIT_TIMEOUT	msecs_to_jiffies(500)
+
+static inline void fimg2d4x_blit_wait(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd)
+{
+	if (!wait_event_timeout(info->wait_q, !atomic_read(&info->busy), BLIT_TIMEOUT)) {
+		printk(KERN_ERR "[%s] blit wait timeout\n", __func__);
+		fimg2d_dump_command(cmd);
+
+		if (!fimg2d4x_blit_done_status(info))
+			info->err = true; /* device error */
+	}
+}
+
+static void fimg2d4x_pre_bitblt(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd)
+{
+	/* TODO */
+}
+
+void fimg2d4x_bitblt(struct fimg2d_control *info)
+{
+	struct fimg2d_context *ctx;
+	struct fimg2d_bltcmd *cmd;
+	unsigned long *pgd;
+	int ret;
+
+	fimg2d_debug("enter blitter\n");
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_get_sync(info->dev);
+	fimg2d_debug("pm_runtime_get_sync\n");
+#endif
+	fimg2d_clk_on(info);
+
+	while (1) {
+		cmd = fimg2d_get_first_command(info);
+		if (!cmd) {
+			spin_lock(&info->bltlock);
+			atomic_set(&info->active, 0);
+			spin_unlock(&info->bltlock);
+			break;
+		}
+
+		ctx = cmd->ctx;
+		if (info->err) {
+			printk(KERN_ERR "[%s] device error\n", __func__);
+			goto blitend;
+		}
+
+		atomic_set(&info->busy, 1);
+
+		ret = info->configure(info, cmd);
+		if (ret)
+			goto blitend;
+
+		if (cmd->image[IDST].addr.type != ADDR_PHYS) {
+			pgd = (unsigned long *)ctx->mm->pgd;
+			s5p_sysmmu_enable(info->dev, (unsigned long)virt_to_phys(pgd));
+			fimg2d_debug("sysmmu enable: pgd %p ctx %p seq_no(%u)\n",
+					pgd, ctx, cmd->seq_no);
+		}
+
+		fimg2d4x_pre_bitblt(info, cmd);
+
+#ifdef PERF_PROFILE
+		perf_start(cmd->ctx, PERF_BLIT);
+#endif
+		/* start blit */
+		info->run(info);
+		fimg2d4x_blit_wait(info, cmd);
+
+#ifdef PERF_PROFILE
+		perf_end(cmd->ctx, PERF_BLIT);
+#endif
+		if (cmd->image[IDST].addr.type != ADDR_PHYS) {
+			s5p_sysmmu_disable(info->dev);
+			fimg2d_debug("sysmmu disable\n");
+		}
+blitend:
+		spin_lock(&info->bltlock);
+		fimg2d_dequeue(&cmd->node);
+		kfree(cmd);
+		atomic_dec(&ctx->ncmd);
+
+		/* wake up context */
+		if (!atomic_read(&ctx->ncmd))
+			wake_up(&ctx->wait_q);
+		spin_unlock(&info->bltlock);
+	}
+
+	fimg2d_clk_off(info);
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_put_sync(info->dev);
+	fimg2d_debug("pm_runtime_put_sync\n");
+#endif
+
+	fimg2d_debug("exit blitter\n");
+}
+
+static int fast_op(struct fimg2d_bltcmd *cmd)
+{
+	int sa, da, ga;
+	int fop = cmd->op;
+	struct fimg2d_image *src, *msk, *dst;
+	struct fimg2d_param *p = &cmd->param;
+
+	src = &cmd->image[ISRC];
+	msk = &cmd->image[IMSK];
+	dst = &cmd->image[IDST];
+
+	if (msk->addr.type)
+		return fop;
+
+	ga = p->g_alpha;
+	da = is_opaque(dst->fmt) ? 0xff : 0;
+
+	if (!src->addr.type)
+		sa = (p->solid_color >> 24) & 0xff;
+	else
+		sa = is_opaque(src->fmt) ? 0xff : 0;
+
+	switch (cmd->op) {
+	case BLIT_OP_SRC_OVER:
+		/* Sc + (1-Sa)*Dc = Sc */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_OVER:
+		/* (1-Da)*Sc + Dc = Dc */
+		if (da == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	case BLIT_OP_SRC_IN:
+		/* Da*Sc = Sc */
+		if (da == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_IN:
+		/* Sa*Dc = Dc */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	case BLIT_OP_SRC_OUT:
+		/* (1-Da)*Sc = 0 */
+		if (da == 0xff)
+			fop = BLIT_OP_CLR;
+		break;
+	case BLIT_OP_DST_OUT:
+		/* (1-Sa)*Dc = 0 */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_CLR;
+		break;
+	case BLIT_OP_SRC_ATOP:
+		/* Da*Sc + (1-Sa)*Dc = Sc */
+		if (sa == 0xff && da == 0xff && ga == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_ATOP:
+		/* (1-Da)*Sc + Sa*Dc = Dc */
+		if (sa == 0xff && da == 0xff && ga == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	default:
+		break;
+	}
+
+	if (fop == BLIT_OP_SRC && !src->addr.type && ga == 0xff)
+		fop = BLIT_OP_SOLID_FILL;
+
+	return fop;
+}
+
+static int fimg2d4x_configure(struct fimg2d_control *info,
+				struct fimg2d_bltcmd *cmd)
+{
+	int op;
+	enum image_sel srcsel, dstsel;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *src, *msk, *dst;
+
+	fimg2d_debug("ctx %p seq_no(%u)\n", cmd->ctx, cmd->seq_no);
+
+	src = &cmd->image[ISRC];
+	msk = &cmd->image[IMSK];
+	dst = &cmd->image[IDST];
+
+	/* TODO: batch blit */
+	fimg2d4x_reset(info);
+
+	/* src and dst select */
+	srcsel = dstsel = IMG_MEMORY;
+
+	op = fast_op(cmd);
+
+	switch (op) {
+	case BLIT_OP_SOLID_FILL:
+		srcsel = dstsel = IMG_FGCOLOR;
+		fimg2d4x_set_fgcolor(info, p->solid_color);
+		break;
+	case BLIT_OP_CLR:
+		srcsel = dstsel = IMG_FGCOLOR;
+		fimg2d4x_set_color_fill(info, 0);
+		break;
+	case BLIT_OP_DST:
+		return -1;	/* nop */
+	default:
+		if (!src->addr.type) {
+			srcsel = IMG_FGCOLOR;
+			fimg2d4x_set_fgcolor(info, p->solid_color);
+		}
+
+		if (op == BLIT_OP_SRC)
+			dstsel = IMG_FGCOLOR;
+
+		fimg2d4x_enable_alpha(info, p->g_alpha);
+		fimg2d4x_set_alpha_composite(info, op, p->g_alpha);
+		if (p->premult == NON_PREMULTIPLIED)
+			fimg2d4x_set_premultiplied(info);
+		break;
+	}
+
+	fimg2d4x_set_src_type(info, srcsel);
+	fimg2d4x_set_dst_type(info, dstsel);
+
+	/* src */
+	if (src->addr.type) {
+		fimg2d4x_set_src_image(info, src);
+		fimg2d4x_set_src_rect(info, &src->rect);
+		fimg2d4x_set_src_repeat(info, &p->repeat);
+		if (p->scaling.mode)
+			fimg2d4x_set_src_scaling(info, &p->scaling, &p->repeat);
+	}
+
+	/* msk */
+	if (msk->addr.type) {
+		fimg2d4x_enable_msk(info);
+		fimg2d4x_set_msk_image(info, msk);
+		fimg2d4x_set_msk_rect(info, &msk->rect);
+		fimg2d4x_set_msk_repeat(info, &p->repeat);
+		if (p->scaling.mode)
+			fimg2d4x_set_msk_scaling(info, &p->scaling, &p->repeat);
+	}
+
+	/* dst */
+	if (dst->addr.type) {
+		fimg2d4x_set_dst_image(info, dst);
+		fimg2d4x_set_dst_rect(info, &dst->rect);
+		if (p->clipping.enable)
+			fimg2d4x_enable_clipping(info, &p->clipping);
+	}
+
+	/* bluescreen */
+	if (p->bluscr.mode)
+		fimg2d4x_set_bluescreen(info, &p->bluscr);
+
+	/* rotation */
+	if (p->rotate)
+		fimg2d4x_set_rotation(info, p->rotate);
+
+	/* dithering */
+	if (p->dither)
+		fimg2d4x_enable_dithering(info);
+
+	return 0;
+}
+
+static void fimg2d4x_run(struct fimg2d_control *info)
+{
+	fimg2d_debug("start blit\n");
+	fimg2d4x_enable_irq(info);
+	fimg2d4x_clear_irq(info);
+	fimg2d4x_start_blit(info);
+}
+
+static void fimg2d4x_stop(struct fimg2d_control *info)
+{
+	if (fimg2d4x_is_blit_done(info)) {
+		fimg2d_debug("blit done\n");
+		fimg2d4x_disable_irq(info);
+		fimg2d4x_clear_irq(info);
+		atomic_set(&info->busy, 0);
+		wake_up(&info->wait_q);
+	}
+}
+
+static void fimg2d4x_dump(struct fimg2d_control *info)
+{
+	fimg2d4x_dump_regs(info);
+}
+
+int fimg2d_register_ops(struct fimg2d_control *info)
+{
+	info->blit = fimg2d4x_bitblt;
+	info->configure = fimg2d4x_configure;
+	info->run = fimg2d4x_run;
+	info->dump = fimg2d4x_dump;
+	info->stop = fimg2d4x_stop;
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_hw.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_hw.c
new file mode 100644
index 0000000..8135ecd
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_hw.c
@@ -0,0 +1,839 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_hw.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/sched.h>
+
+#include "fimg2d.h"
+#include "fimg2d4x.h"
+#include "fimg2d_clk.h"
+
+#define wr(d, a)	writel((d), info->regs + (a))
+#define rd(a)		readl(info->regs + (a))
+
+#undef SOFT_RESET_ENABLED
+#undef FIMG2D_RESET_WA
+
+static const int a8_rgbcolor		= (int)0x0;
+static const int msk_oprmode		= (int)MSK_ARGB;
+static const int premult_round_mode	= (int)PREMULT_ROUND_1;	/* (A+1)*B) >> 8 */
+static const int blend_round_mode	= (int)BLEND_ROUND_0;	/* (A+1)*B) >> 8 */
+
+void fimg2d4x_reset(struct fimg2d_control *info)
+{
+#ifdef SOFT_RESET_ENABLED
+#ifdef FIMG2D_RESET_WA
+	fimg2d_clk_save(info);
+#endif
+	wr(FIMG2D_SOFT_RESET, FIMG2D_SOFT_RESET_REG);
+#ifdef FIMG2D_RESET_WA
+	fimg2d_clk_restore(info);
+#endif
+#else
+	wr(FIMG2D_SFR_CLEAR, FIMG2D_SOFT_RESET_REG);
+#endif
+	/* turn off wince option */
+	wr(0x0, FIMG2D_BLEND_FUNCTION_REG);
+
+	/* set default repeat mode to reflect(mirror) */
+	wr(FIMG2D_SRC_REPEAT_REFLECT, FIMG2D_SRC_REPEAT_MODE_REG);
+	wr(FIMG2D_MSK_REPEAT_REFLECT, FIMG2D_MSK_REPEAT_MODE_REG);
+}
+
+void fimg2d4x_enable_irq(struct fimg2d_control *info)
+{
+	wr(FIMG2D_BLIT_INT_ENABLE, FIMG2D_INTEN_REG);
+}
+
+void fimg2d4x_disable_irq(struct fimg2d_control *info)
+{
+	wr(0, FIMG2D_INTEN_REG);
+}
+
+void fimg2d4x_clear_irq(struct fimg2d_control *info)
+{
+	wr(FIMG2D_BLIT_INT_FLAG, FIMG2D_INTC_PEND_REG);
+}
+
+int fimg2d4x_is_blit_done(struct fimg2d_control *info)
+{
+	return rd(FIMG2D_INTC_PEND_REG) & FIMG2D_BLIT_INT_FLAG;
+}
+
+int fimg2d4x_blit_done_status(struct fimg2d_control *info)
+{
+	volatile unsigned long sts;
+
+	/* read twice */
+	sts = rd(FIMG2D_FIFO_STAT_REG);
+	sts = rd(FIMG2D_FIFO_STAT_REG);
+
+	return (int)(sts & FIMG2D_BLIT_FINISHED);
+}
+
+void fimg2d4x_start_blit(struct fimg2d_control *info)
+{
+	wr(FIMG2D_START_BITBLT, FIMG2D_BITBLT_START_REG);
+}
+
+void fimg2d4x_set_max_burst_length(struct fimg2d_control *info, enum max_burst_len len)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_AXI_MODE_REG);
+
+	cfg &= ~FIMG2D_MAX_BURST_LEN_MASK;
+	cfg |= len << FIMG2D_MAX_BURST_LEN_SHIFT;
+}
+
+void fimg2d4x_set_src_type(struct fimg2d_control *info, enum image_sel type)
+{
+	unsigned long cfg;
+
+	if (type == IMG_MEMORY)
+		cfg = FIMG2D_IMAGE_TYPE_MEMORY;
+	else if (type == IMG_FGCOLOR)
+		cfg = FIMG2D_IMAGE_TYPE_FGCOLOR;
+	else
+		cfg = FIMG2D_IMAGE_TYPE_BGCOLOR;
+
+	wr(cfg, FIMG2D_SRC_SELECT_REG);
+}
+
+void fimg2d4x_set_src_image(struct fimg2d_control *info, struct fimg2d_image *s)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(s->addr.start), FIMG2D_SRC_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(s->stride), FIMG2D_SRC_STRIDE_REG);
+
+	if (s->order < ARGB_ORDER_END) {	/* argb */
+		cfg = s->order << FIMG2D_RGB_ORDER_SHIFT;
+		if (s->fmt == CF_A8)
+			wr(a8_rgbcolor, FIMG2D_SRC_A8_RGB_EXT_REG);
+	} else if (s->order < P1_ORDER_END) {	/* YCbC1 1plane */
+		cfg = (s->order - P1_CRY1CBY0) << FIMG2D_YCBCR_ORDER_SHIFT;
+	} else {	/* YCbCr 2plane */
+		cfg = (s->order - P2_CRCB) << FIMG2D_YCBCR_ORDER_SHIFT;
+		cfg |= FIMG2D_YCBCR_2PLANE;
+
+		wr(FIMG2D_ADDR(s->plane2.start),
+				FIMG2D_SRC_PLANE2_BASE_ADDR_REG);
+	}
+
+	cfg |= s->fmt << FIMG2D_COLOR_FORMAT_SHIFT;
+
+	wr(cfg, FIMG2D_SRC_COLOR_MODE_REG);
+}
+
+void fimg2d4x_set_src_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_SRC_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_SRC_RIGHT_BOTTOM_REG);
+}
+
+void fimg2d4x_set_dst_type(struct fimg2d_control *info, enum image_sel type)
+{
+	unsigned long cfg;
+
+	if (type == IMG_MEMORY)
+		cfg = FIMG2D_IMAGE_TYPE_MEMORY;
+	else if (type == IMG_FGCOLOR)
+		cfg = FIMG2D_IMAGE_TYPE_FGCOLOR;
+	else
+		cfg = FIMG2D_IMAGE_TYPE_BGCOLOR;
+
+	wr(cfg, FIMG2D_DST_SELECT_REG);
+}
+
+/**
+ * @d: set base address, stride, color format, order
+ */
+void fimg2d4x_set_dst_image(struct fimg2d_control *info, struct fimg2d_image *d)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(d->addr.start), FIMG2D_DST_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(d->stride), FIMG2D_DST_STRIDE_REG);
+
+	if (d->order < ARGB_ORDER_END) {
+		cfg = d->order << FIMG2D_RGB_ORDER_SHIFT;
+		if (d->fmt == CF_A8)
+			wr(a8_rgbcolor, FIMG2D_DST_A8_RGB_EXT_REG);
+	} else if (d->order < P1_ORDER_END) {
+		cfg = (d->order - P1_CRY1CBY0) << FIMG2D_YCBCR_ORDER_SHIFT;
+	} else {
+		cfg = (d->order - P2_CRCB) << FIMG2D_YCBCR_ORDER_SHIFT;
+		cfg |= FIMG2D_YCBCR_2PLANE;
+
+		wr(FIMG2D_ADDR(d->plane2.start),
+				FIMG2D_DST_PLANE2_BASE_ADDR_REG);
+	}
+
+	cfg |= d->fmt << FIMG2D_COLOR_FORMAT_SHIFT;
+
+	wr(cfg, FIMG2D_DST_COLOR_MODE_REG);
+}
+
+void fimg2d4x_set_dst_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_DST_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_DST_RIGHT_BOTTOM_REG);
+}
+
+void fimg2d4x_enable_msk(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_NORMAL_MSK;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_set_msk_image(struct fimg2d_control *info, struct fimg2d_image *m)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(m->addr.start), FIMG2D_MSK_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(m->stride), FIMG2D_MSK_STRIDE_REG);
+
+	cfg = m->order << FIMG2D_MSK_ORDER_SHIFT;
+	cfg |= (m->fmt - CF_MSK_1BIT) << FIMG2D_MSK_FORMAT_SHIFT;
+
+	/* 16, 32bit mask only */
+	if (m->fmt >= CF_MSK_16BIT_565) {
+		if (msk_oprmode == MSK_ALPHA)
+			cfg |= FIMG2D_MSK_TYPE_ALPHA;
+		else if (msk_oprmode == MSK_ARGB)
+			cfg |= FIMG2D_MSK_TYPE_ARGB;
+		else
+			cfg |= FIMG2D_MSK_TYPE_MIXED;
+	}
+
+	wr(cfg, FIMG2D_MSK_MODE_REG);
+}
+
+void fimg2d4x_set_msk_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_MSK_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_MSK_RIGHT_BOTTOM_REG);
+}
+
+/**
+ * If solid color fill is enabled, other blit command is ignored.
+ * Color format of solid color is considered to be
+ *	the same as destination color format
+ * Channel order of solid color is A-R-G-B or Y-Cb-Cr
+ */
+void fimg2d4x_set_color_fill(struct fimg2d_control *info, unsigned long color)
+{
+	wr(FIMG2D_SOLID_FILL, FIMG2D_BITBLT_COMMAND_REG);
+
+	/* sf color */
+	wr(color, FIMG2D_SF_COLOR_REG);
+
+	/* set 16 burst for performance */
+	fimg2d4x_set_max_burst_length(info, MAX_BURST_16);
+}
+
+/**
+ * set alpha-multiply mode for src, dst, pat read (pre-bitblt)
+ * set alpha-demultiply for dst write (post-bitblt)
+ */
+void fimg2d4x_set_premultiplied(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_PREMULT_ALL;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_src_premultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_SRC_PREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_dst_premultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_DST_RD_PREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_dst_depremultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_DST_WR_DEPREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+/**
+ * set transp/bluscr mode, bs color, bg color
+ */
+void fimg2d4x_set_bluescreen(struct fimg2d_control *info,
+		struct fimg2d_bluscr *bluscr)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+
+	if (bluscr->mode == TRANSP)
+		cfg |= FIMG2D_TRANSP_MODE;
+	else if (bluscr->mode == BLUSCR)
+		cfg |= FIMG2D_BLUSCR_MODE;
+	else	/* opaque: initial value */
+		return;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	/* bs color */
+	if (bluscr->bs_color)
+		wr(bluscr->bs_color, FIMG2D_BS_COLOR_REG);
+
+	/* bg color */
+	if (bluscr->mode == BLUSCR && bluscr->bg_color)
+		wr(bluscr->bg_color, FIMG2D_BG_COLOR_REG);
+}
+
+/**
+ * @c: destination clipping region
+ */
+void fimg2d4x_enable_clipping(struct fimg2d_control *info,
+				struct fimg2d_clip *clp)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_CW;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	wr(FIMG2D_OFFSET(clp->x1, clp->y1), FIMG2D_CW_LT_REG);
+	wr(FIMG2D_OFFSET(clp->x2, clp->y2), FIMG2D_CW_RB_REG);
+}
+
+void fimg2d4x_enable_dithering(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_DITHER;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+#define MAX_PRECISION		16
+#define DEFAULT_SCALE_RATIO	0x10000
+
+/**
+ * scale_factor_to_fixed16 - convert scale factor to fixed pint 16
+ * @n: numerator
+ * @d: denominator
+ */
+static inline unsigned long scale_factor_to_fixed16(int n, int d)
+{
+	int i;
+	u32 fixed16;
+
+	if (!d)
+		return DEFAULT_SCALE_RATIO;
+
+	fixed16 = (n/d) << 16;
+	n %= d;
+
+	for (i = 0; i < MAX_PRECISION; i++) {
+		if (!n)
+			break;
+		n <<= 1;
+		if (n/d)
+			fixed16 |= 1 << (15-i);
+		n %= d;
+	}
+
+	return fixed16;
+}
+
+void fimg2d4x_set_src_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long wcfg, hcfg;
+	unsigned long mode;
+
+	/*
+	 * scaling ratio in pixels
+	 * e.g scale-up: src(1,1)-->dst(2,2), src factor: 0.5 (0x000080000)
+	 *     scale-down: src(2,2)-->dst(1,1), src factor: 2.0 (0x000200000)
+	 */
+
+	/* inversed scaling factor: src is numerator */
+	wcfg = scale_factor_to_fixed16(scl->src_w, scl->dst_w);
+	hcfg = scale_factor_to_fixed16(scl->src_h, scl->dst_h);
+
+	if (wcfg == DEFAULT_SCALE_RATIO && hcfg == DEFAULT_SCALE_RATIO)
+		return;
+
+	wr(wcfg, FIMG2D_SRC_XSCALE_REG);
+	wr(hcfg, FIMG2D_SRC_YSCALE_REG);
+
+	/* scaling algorithm */
+	if (scl->mode == SCALING_NEAREST)
+		mode = FIMG2D_SCALE_MODE_NEAREST;
+	else {
+		/* 0x3: ignore repeat mode at boundary */
+		if (rep->mode == REPEAT_PAD || rep->mode == REPEAT_CLAMP)
+			mode = 0x3;	/* hidden */
+		else
+			mode = FIMG2D_SCALE_MODE_BILINEAR;
+	}
+
+	wr(mode, FIMG2D_SRC_SCALE_CTRL_REG);
+}
+
+void fimg2d4x_set_msk_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long wcfg, hcfg;
+	unsigned long mode;
+
+	/*
+	 * scaling ratio in pixels
+	 * e.g scale-up: src(1,1)-->dst(2,2), msk factor: 0.5 (0x000080000)
+	 *     scale-down: src(2,2)-->dst(1,1), msk factor: 2.0 (0x000200000)
+	 */
+
+	/* inversed scaling factor: src is numerator */
+	wcfg = scale_factor_to_fixed16(scl->src_w, scl->dst_w);
+	hcfg = scale_factor_to_fixed16(scl->src_h, scl->dst_h);
+
+	if (wcfg == DEFAULT_SCALE_RATIO && hcfg == DEFAULT_SCALE_RATIO)
+		return;
+
+	wr(wcfg, FIMG2D_MSK_XSCALE_REG);
+	wr(hcfg, FIMG2D_MSK_YSCALE_REG);
+
+	/* scaling algorithm */
+	if (scl->mode == SCALING_NEAREST)
+		mode = FIMG2D_SCALE_MODE_NEAREST;
+	else {
+		/* 0x3: ignore repeat mode at boundary */
+		if (rep->mode == REPEAT_PAD || rep->mode == REPEAT_CLAMP)
+			mode = 0x3;	/* hidden */
+		else
+			mode = FIMG2D_SCALE_MODE_BILINEAR;
+	}
+
+	wr(mode, FIMG2D_MSK_SCALE_CTRL_REG);
+}
+
+void fimg2d4x_set_src_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long cfg;
+
+	if (rep->mode == NO_REPEAT)
+		return;
+
+	cfg = (rep->mode - REPEAT_NORMAL) << FIMG2D_SRC_REPEAT_SHIFT;
+
+	wr(cfg, FIMG2D_SRC_REPEAT_MODE_REG);
+
+	/* src pad color */
+	if (rep->mode == REPEAT_PAD)
+		wr(rep->pad_color, FIMG2D_SRC_PAD_VALUE_REG);
+}
+
+void fimg2d4x_set_msk_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long cfg;
+
+	if (rep->mode == NO_REPEAT)
+		return;
+
+	cfg = (rep->mode - REPEAT_NORMAL) << FIMG2D_MSK_REPEAT_SHIFT;
+
+	wr(cfg, FIMG2D_MSK_REPEAT_MODE_REG);
+
+	/* mask pad color */
+	if (rep->mode == REPEAT_PAD)
+		wr(rep->pad_color, FIMG2D_MSK_PAD_VALUE_REG);
+}
+
+void fimg2d4x_set_rotation(struct fimg2d_control *info, enum rotation rot)
+{
+	int rev_rot90;	/* counter clockwise, 4.1 specific */
+	unsigned long cfg;
+	enum addressing dirx, diry;
+
+	rev_rot90 = 0;
+	dirx = diry = FORWARD_ADDRESSING;
+
+	switch (rot) {
+	case ROT_90:	/* -270 degree */
+		rev_rot90 = 1;	/* fall through */
+	case ROT_180:
+		dirx = REVERSE_ADDRESSING;
+		diry = REVERSE_ADDRESSING;
+		break;
+	case ROT_270:	/* -90 degree */
+		rev_rot90 = 1;
+		break;
+	case XFLIP:
+		diry = REVERSE_ADDRESSING;
+		break;
+	case YFLIP:
+		dirx = REVERSE_ADDRESSING;
+		break;
+	case ORIGIN:
+	default:
+		break;
+	}
+
+	/* destination direction */
+	if (dirx == REVERSE_ADDRESSING || diry == REVERSE_ADDRESSING) {
+		cfg = rd(FIMG2D_DST_PAT_DIRECT_REG);
+
+		if (dirx == REVERSE_ADDRESSING)
+			cfg |= FIMG2D_DST_X_DIR_NEGATIVE;
+
+		if (diry == REVERSE_ADDRESSING)
+			cfg |= FIMG2D_DST_Y_DIR_NEGATIVE;
+
+		wr(cfg, FIMG2D_DST_PAT_DIRECT_REG);
+	}
+
+	/* rotation -90 */
+	if (rev_rot90) {
+		cfg = rd(FIMG2D_ROTATE_REG);
+		cfg |= FIMG2D_SRC_ROTATE_90;
+		cfg |= FIMG2D_MSK_ROTATE_90;
+
+		wr(cfg, FIMG2D_ROTATE_REG);
+	}
+}
+
+void fimg2d4x_set_fgcolor(struct fimg2d_control *info, unsigned long fg)
+{
+	wr(fg, FIMG2D_FG_COLOR_REG);
+}
+
+void fimg2d4x_set_bgcolor(struct fimg2d_control *info, unsigned long bg)
+{
+	wr(bg, FIMG2D_BG_COLOR_REG);
+}
+
+void fimg2d4x_enable_alpha(struct fimg2d_control *info, unsigned char g_alpha)
+{
+	unsigned long cfg;
+
+	/* enable alpha */
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ALPHA_BLEND_MODE;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	/*
+	 * global(constant) alpha
+	 * ex. if global alpha is 0x80, must set 0x80808080
+	 */
+	cfg = g_alpha;
+	cfg |= g_alpha << 8;
+	cfg |= g_alpha << 16;
+	cfg |= g_alpha << 24;
+	wr(cfg, FIMG2D_ALPHA_REG);
+}
+
+/**
+ * Four channels of the image are computed with:
+ *	R = [ coeff(S)*Sc  + coeff(D)*Dc ]
+ *	where
+ *	Rc is result color or alpha
+ *	Sc is source color or alpha
+ *	Dc is destination color or alpha
+ *
+ * Caution: supposed that Sc and Dc are perpixel-alpha-premultiplied value
+ *
+ * MODE:             Formula
+ * ----------------------------------------------------------------------------
+ * FILL:
+ * CLEAR:	     R = 0
+ * SRC:		     R = Sc
+ * DST:		     R = Dc
+ * SRC_OVER:         R = Sc + (1-Sa)*Dc
+ * DST_OVER:         R = (1-Da)*Sc + Dc
+ * SRC_IN:	     R = Da*Sc
+ * DST_IN:           R = Sa*Dc
+ * SRC_OUT:          R = (1-Da)*Sc
+ * DST_OUT:          R = (1-Sa)*Dc
+ * SRC_ATOP:         R = Da*Sc + (1-Sa)*Dc
+ * DST_ATOP:         R = (1-Da)*Sc + Sa*Dc
+ * XOR:              R = (1-Da)*Sc + (1-Sa)*Dc
+ * ADD:              R = Sc + Dc
+ * MULTIPLY:         R = Sc*Dc
+ * SCREEN:           R = Sc + (1-Sc)*Dc
+ * DARKEN:           R = (Da*Sc<Sa*Dc)? Sc+(1-Sa)*Dc : (1-Da)*Sc+Dc
+ * LIGHTEN:          R = (Da*Sc>Sa*Dc)? Sc+(1-Sa)*Dc : (1-Da)*Sc+Dc
+ * DISJ_SRC_OVER:    R = Sc + (min(1,(1-Sa)/Da))*Dc
+ * DISJ_DST_OVER:    R = (min(1,(1-Da)/Sa))*Sc + Dc
+ * DISJ_SRC_IN:      R = (max(1-(1-Da)/Sa,0))*Sc
+ * DISJ_DST_IN:      R = (max(1-(1-Sa)/Da,0))*Dc
+ * DISJ_SRC_OUT:     R = (min(1,(1-Da)/Sa))*Sc
+ * DISJ_DST_OUT:     R = (min(1,(1-Sa)/Da))*Dc
+ * DISJ_SRC_ATOP:    R = (max(1-(1-Da)/Sa,0))*Sc + (min(1,(1-Sa)/Da))*Dc
+ * DISJ_DST_ATOP:    R = (min(1,(1-Da)/Sa))*Sc + (max(1-(1-Sa)/Da,0))*Dc
+ * DISJ_XOR:         R = (min(1,(1-Da)/Sa))*Sc + (min(1,(1-Sa)/Da))*Dc
+ * CONJ_SRC_OVER:    R = Sc + (max(1-Sa/Da,0))*Dc
+ * CONJ_DST_OVER:    R = (max(1-Da/Sa,0))*Sc + Dc
+ * CONJ_SRC_IN:      R = (min(1,Da/Sa))*Sc
+ * CONJ_DST_IN:      R = (min(1,Sa/Da))*Dc
+ * CONJ_SRC_OUT:     R = (max(1-Da/Sa,0)*Sc
+ * CONJ_DST_OUT:     R = (max(1-Sa/Da,0))*Dc
+ * CONJ_SRC_ATOP:    R = (min(1,Da/Sa))*Sc + (max(1-Sa/Da,0))*Dc
+ * CONJ_DST_ATOP:    R = (max(1-Da/Sa,0))*Sc + (min(1,Sa/Da))*Dc
+ * CONJ_XOR:         R = (max(1-Da/Sa,0))*Sc + (max(1-Sa/Da,0))*Dc
+ */
+static struct fimg2d_blend_coeff const coeff_table[MAX_FIMG2D_BLIT_OP] = {
+	{ 0, 0, 0, 0 },		/* FILL */
+	{ 0, COEFF_ZERO,	0, COEFF_ZERO },	/* CLEAR */
+	{ 0, COEFF_ONE,		0, COEFF_ZERO },	/* SRC */
+	{ 0, COEFF_ZERO,	0, COEFF_ONE },		/* DST */
+	{ 0, COEFF_ONE,		1, COEFF_SA },		/* SRC_OVER */
+	{ 1, COEFF_DA,		0, COEFF_ONE },		/* DST_OVER */
+	{ 0, COEFF_DA,		0, COEFF_ZERO },	/* SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_SA },		/* DST_IN */
+	{ 1, COEFF_DA,		0, COEFF_ZERO },	/* SRC_OUT */
+	{ 0, COEFF_ZERO,	1, COEFF_SA },		/* DST_OUT */
+	{ 0, COEFF_DA,		1, COEFF_SA },		/* SRC_ATOP */
+	{ 1, COEFF_DA,		0, COEFF_SA },		/* DST_ATOP */
+	{ 1, COEFF_DA,		1, COEFF_SA },		/* XOR */
+	{ 0, COEFF_ONE,		0, COEFF_ONE },		/* ADD */
+	{ 0, COEFF_DC,		0, COEFF_ZERO },	/* MULTIPLY */
+	{ 0, COEFF_ONE,		1, COEFF_SC },		/* SCREEN */
+	{ 0, 0, 0, 0 },		/* DARKEN */
+	{ 0, 0, 0, 0 },		/* LIGHTEN */
+	{ 0, COEFF_ONE,		0, COEFF_DISJ_S },	/* DISJ_SRC_OVER */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_DST_OVER */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ZERO },	/* DISJ_SRC_IN */
+	{ 0, COEFF_ZERO,	1, COEFF_DISJ_S },	/* DISJ_DST_IN */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_SRC_OUT */
+	{ 0, COEFF_ZERO,	0, COEFF_DISJ_S },	/* DISJ_DST_OUT */
+	{ 1, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_SRC_ATOP */
+	{ 0, COEFF_DISJ_D,	1, COEFF_DISJ_S },	/* DISJ_DST_ATOP */
+	{ 0, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_XOR */
+	{ 0, COEFF_ONE,		1, COEFF_DISJ_S },	/* CONJ_SRC_OVER */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ONE },		/* CONJ_DST_OVER */
+	{ 0, COEFF_CONJ_D,	0, COEFF_ONE },		/* CONJ_SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_CONJ_S },	/* CONJ_DST_IN */
+	{ 1, COEFF_CONJ_D,	0, COEFF_ZERO },	/* CONJ_SRC_OUT */
+	{ 0, COEFF_ZERO,	1, COEFF_CONJ_S },	/* CONJ_DST_OUT */
+	{ 0, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_SRC_ATOP */
+	{ 1, COEFF_CONJ_D,	0, COEFF_CONJ_D },	/* CONJ_DST_ATOP */
+	{ 1, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_XOR */
+	{ 0, 0, 0, 0 },		/* USER */
+	{ 1, COEFF_GA,		1, COEFF_ZERO },	/* USER_SRC_GA */
+};
+
+/*
+ * coefficient table with global (constant) alpha
+ * replace COEFF_ONE with COEFF_GA
+ *
+ * MODE:             Formula with Global Alpha (Ga is multiplied to both Sc and Sa)
+ * ----------------------------------------------------------------------------
+ * FILL:
+ * CLEAR:	     R = 0
+ * SRC:		     R = Ga*Sc
+ * DST:		     R = Dc
+ * SRC_OVER:         R = Ga*Sc + (1-Sa*Ga)*Dc
+ * DST_OVER:         R = (1-Da)*Ga*Sc + Dc --> (W/A) 1st:Ga*Sc, 2nd:DST_OVER
+ * SRC_IN:	     R = Da*Ga*Sc
+ * DST_IN:           R = Sa*Ga*Dc
+ * SRC_OUT:          R = (1-Da)*Ga*Sc --> (W/A) 1st: Ga*Sc, 2nd:SRC_OUT
+ * DST_OUT:          R = (1-Sa*Ga)*Dc
+ * SRC_ATOP:         R = Da*Ga*Sc + (1-Sa*Ga)*Dc
+ * DST_ATOP:         R = (1-Da)*Ga*Sc + Sa*Ga*Dc --> (W/A) 1st: Ga*Sc, 2nd:DST_ATOP
+ * XOR:              R = (1-Da)*Ga*Sc + (1-Sa*Ga)*Dc --> (W/A) 1st: Ga*Sc, 2nd:XOR
+ * ADD:              R = Ga*Sc + Dc
+ * MULTIPLY:         R = Ga*Sc*Dc --> (W/A) 1st: Ga*Sc, 2nd: MULTIPLY
+ * SCREEN:           R = Ga*Sc + (1-Ga*Sc)*Dc --> (W/A) 1st: Ga*Sc, 2nd: SCREEN
+ * DARKEN:           R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * LIGHTEN:          R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_XOR:         R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_XOR:         R = (W/A) 1st: Ga*Sc, 2nd: OP
+ */
+static struct fimg2d_blend_coeff const ga_coeff_table[MAX_FIMG2D_BLIT_OP] = {
+	{ 0, 0, 0, 0 },		/* FILL */
+	{ 0, COEFF_ZERO,	0, COEFF_ZERO },	/* CLEAR */
+	{ 0, COEFF_GA,		0, COEFF_ZERO },	/* SRC */
+	{ 0, COEFF_ZERO,	0, COEFF_ONE },		/* DST */
+	{ 0, COEFF_GA,		1, COEFF_SA },		/* SRC_OVER */
+	{ 1, COEFF_DA,		0, COEFF_ONE },		/* DST_OVER (use W/A) */
+	{ 0, COEFF_DA,		0, COEFF_ZERO },	/* SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_SA },		/* DST_IN */
+	{ 1, COEFF_DA,		0, COEFF_ZERO },	/* SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_SA },		/* DST_OUT */
+	{ 0, COEFF_DA,		1, COEFF_SA },		/* SRC_ATOP */
+	{ 1, COEFF_DA,		0, COEFF_SA },		/* DST_ATOP (use W/A) */
+	{ 1, COEFF_DA,		1, COEFF_SA },		/* XOR (use W/A) */
+	{ 0, COEFF_GA,		0, COEFF_ONE },		/* ADD */
+	{ 0, COEFF_DC,		0, COEFF_ZERO },	/* MULTIPLY (use W/A) */
+	{ 0, COEFF_ONE,		1, COEFF_SC },		/* SCREEN (use W/A) */
+	{ 0, 0, 0, 0 },		/* DARKEN (use W/A) */
+	{ 0, 0, 0, 0 },		/* LIGHTEN (use W/A) */
+	{ 0, COEFF_ONE,		0, COEFF_DISJ_S },	/* DISJ_SRC_OVER (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_DST_OVER (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ZERO },	/* DISJ_SRC_IN (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_DISJ_S },	/* DISJ_DST_IN (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	0, COEFF_DISJ_S },	/* DISJ_DST_OUT (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_SRC_ATOP (use W/A) */
+	{ 0, COEFF_DISJ_D,	1, COEFF_DISJ_S },	/* DISJ_DST_ATOP (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_XOR (use W/A) */
+	{ 0, COEFF_ONE,		1, COEFF_DISJ_S },	/* CONJ_SRC_OVER (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ONE },		/* CONJ_DST_OVER (use W/A) */
+	{ 0, COEFF_CONJ_D,	0, COEFF_ONE },		/* CONJ_SRC_IN (use W/A) */
+	{ 0, COEFF_ZERO,	0, COEFF_CONJ_S },	/* CONJ_DST_IN (use W/A) */
+	{ 1, COEFF_CONJ_D,	0, COEFF_ZERO },	/* CONJ_SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_CONJ_S },	/* CONJ_DST_OUT (use W/A) */
+	{ 0, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_SRC_ATOP (use W/A) */
+	{ 1, COEFF_CONJ_D,	0, COEFF_CONJ_D },	/* CONJ_DST_ATOP (use W/A) */
+	{ 1, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_XOR (use W/A) */
+	{ 0, 0, 0, 0 },		/* USER */
+	{ 1, COEFF_GA,		1, COEFF_ZERO },	/* USER_SRC_GA */
+};
+
+void fimg2d4x_set_alpha_composite(struct fimg2d_control *info,
+		enum blit_op op, unsigned char g_alpha)
+{
+	int alphamode;
+	unsigned long cfg = 0;
+	struct fimg2d_blend_coeff const *tbl;
+
+	switch (op) {
+	case BLIT_OP_SOLID_FILL:
+	case BLIT_OP_CLR:
+		/* nop */
+		return;
+	case BLIT_OP_DARKEN:
+		cfg |= FIMG2D_DARKEN;
+		break;
+	case BLIT_OP_LIGHTEN:
+		cfg |= FIMG2D_LIGHTEN;
+		break;
+	case BLIT_OP_USER_COEFF:
+		/* TODO */
+		return;
+	default:
+		if (g_alpha < 0xff) {	/* with global alpha */
+			tbl = &ga_coeff_table[op];
+			alphamode = ALPHA_PERPIXEL_MUL_GLOBAL;
+		} else {
+			tbl = &coeff_table[op];
+			alphamode = ALPHA_PERPIXEL;
+		}
+
+		/* src coefficient */
+		cfg |= tbl->s_coeff << FIMG2D_SRC_COEFF_SHIFT;
+
+		cfg |= alphamode << FIMG2D_SRC_COEFF_SA_SHIFT;
+		cfg |= alphamode << FIMG2D_SRC_COEFF_DA_SHIFT;
+
+		if (tbl->s_coeff_inv)
+			cfg |= FIMG2D_INV_SRC_COEFF;
+
+		/* dst coefficient */
+		cfg |= tbl->d_coeff << FIMG2D_DST_COEFF_SHIFT;
+
+		cfg |= alphamode << FIMG2D_DST_COEFF_DA_SHIFT;
+		cfg |= alphamode << FIMG2D_DST_COEFF_SA_SHIFT;
+
+		if (tbl->d_coeff_inv)
+			cfg |= FIMG2D_INV_DST_COEFF;
+
+		break;
+	}
+
+	wr(cfg, FIMG2D_BLEND_FUNCTION_REG);
+
+	/* round mode: depremult round mode is not used */
+	cfg = rd(FIMG2D_ROUND_MODE_REG);
+
+	/* premult */
+	cfg &= ~FIMG2D_PREMULT_ROUND_MASK;
+	cfg |= premult_round_mode << FIMG2D_PREMULT_ROUND_SHIFT;
+
+	/* blend */
+	cfg &= ~FIMG2D_BLEND_ROUND_MASK;
+	cfg |= blend_round_mode << FIMG2D_BLEND_ROUND_SHIFT;
+
+	wr(cfg, FIMG2D_ROUND_MODE_REG);
+}
+
+void fimg2d4x_dump_regs(struct fimg2d_control *info)
+{
+	int i, offset;
+	unsigned long table[][2] = {
+		/* start, end */
+		{0x0000, 0x0030},	/* general */
+		{0x0080, 0x00a0},	/* host dma */
+		{0x0100, 0x0110},	/* commands */
+		{0x0200, 0x0210},	/* rotation & direction */
+		{0x0300, 0x0340},	/* source */
+		{0x0400, 0x0420},	/* dest */
+		{0x0500, 0x0550},	/* pattern & mask */
+		{0x0600, 0x0710},	/* clip, rop, alpha and color */
+		{0x0, 0x0}
+	};
+
+	for (i = 0; table[i][1] != 0x0; i++) {
+		offset = table[i][0];
+		do {
+			printk(KERN_INFO "[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", offset,
+				rd(offset),
+				rd(offset+0x4),
+				rd(offset+0x8),
+				rd(offset+0xc));
+			offset += 0x10;
+		} while (offset < table[i][1]);
+	}
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_regs.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_regs.h
new file mode 100644
index 0000000..91c7ac8
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d4x_regs.h
@@ -0,0 +1,460 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_regs.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Register Definitions for Samsung Graphics 2D Hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D4X_REGS_H
+#define __FIMG2D4x_REGS_H __FILE__
+
+/* Macros */
+#define FIMG2D_ADDR(v)		((v) << 0)
+#define FIMG2D_STRIDE(v)	(((v) & (0xffff)) << 0)
+#define FIMG2D_OFFSET(x, y)	((((y) & 0x1fff) << 16) | (((x) & 0x1fff) << 0))
+#define FIMG2D_SIZE(w, h)	((((h) & 0x1fff) << 16) | (((w) & 0x1fff) << 0))
+#define FIMG2D_COLOR(v)		((v) << 0)
+
+/* Registers */
+#define FIMG2D_SOFT_RESET_REG			(0x000)
+#define FIMG2D_INTEN_REG			(0x004)
+#define FIMG2D_INTC_PEND_REG			(0x00c)
+#define FIMG2D_FIFO_STAT_REG			(0x010)
+#define FIMG2D_AXI_MODE_REG			(0x01c)
+#define FIMG2D_DMA_SFR_BASE_ADDR_REG		(0x080)
+#define FIMG2D_DMA_COMMAND_REG			(0x084)
+#define FIMG2D_DMA_EXE_LIST_NUM_REG		(0x088)
+#define FIMG2D_DMA_STATUS_REG			(0x08c)
+#define FIMG2D_DMA_HOLD_CMD_REG			(0x090)
+#define FIMG2D_BITBLT_START_REG			(0x100)
+#define FIMG2D_BITBLT_COMMAND_REG		(0x104)
+#define FIMG2D_BLEND_FUNCTION_REG		(0x108)
+#define FIMG2D_ROUND_MODE_REG			(0x10c)
+#define FIMG2D_ROTATE_REG			(0x200)
+#define FIMG2D_SRC_MSK_DIRECT_REG		(0x204)
+#define FIMG2D_DST_PAT_DIRECT_REG		(0x208)
+#define FIMG2D_SRC_SELECT_REG			(0x300)
+#define FIMG2D_SRC_BASE_ADDR_REG		(0x304)
+#define FIMG2D_SRC_STRIDE_REG			(0x308)
+#define FIMG2D_SRC_COLOR_MODE_REG		(0x30c)
+#define FIMG2D_SRC_LEFT_TOP_REG			(0x310)
+#define FIMG2D_SRC_RIGHT_BOTTOM_REG		(0x314)
+#define FIMG2D_SRC_PLANE2_BASE_ADDR_REG		(0x318)
+#define FIMG2D_SRC_REPEAT_MODE_REG		(0x31c)
+#define FIMG2D_SRC_PAD_VALUE_REG		(0x320)
+#define FIMG2D_SRC_A8_RGB_EXT_REG		(0x324)
+#define FIMG2D_SRC_SCALE_CTRL_REG		(0x328)
+#define FIMG2D_SRC_XSCALE_REG			(0x32c)
+#define FIMG2D_SRC_YSCALE_REG			(0x330)
+#define FIMG2D_DST_SELECT_REG			(0x400)
+#define FIMG2D_DST_BASE_ADDR_REG		(0x404)
+#define FIMG2D_DST_STRIDE_REG			(0x408)
+#define FIMG2D_DST_COLOR_MODE_REG		(0x40c)
+#define FIMG2D_DST_LEFT_TOP_REG			(0x410)
+#define FIMG2D_DST_RIGHT_BOTTOM_REG		(0x414)
+#define FIMG2D_DST_PLANE2_BASE_ADDR_REG		(0x418)
+#define FIMG2D_DST_A8_RGB_EXT_REG		(0x41c)
+#define FIMG2D_PAT_BASE_ADDR_REG		(0x500)
+#define FIMG2D_PAT_SIZE_REG			(0x504)
+#define FIMG2D_PAT_COLOR_MODE_REG		(0x508)
+#define FIMG2D_PAT_OFFSET_REG			(0x50c)
+#define FIMG2D_PAT_STRIDE_REG			(0x510)
+#define FIMG2D_MSK_BASE_ADDR_REG		(0x520)
+#define FIMG2D_MSK_STRIDE_REG			(0x524)
+#define FIMG2D_MSK_LEFT_TOP_REG			(0x528)
+#define FIMG2D_MSK_RIGHT_BOTTOM_REG		(0x52c)
+#define FIMG2D_MSK_MODE_REG			(0x530)
+#define FIMG2D_MSK_REPEAT_MODE_REG		(0x534)
+#define FIMG2D_MSK_PAD_VALUE_REG		(0x538)
+#define FIMG2D_MSK_SCALE_CTRL_REG		(0x53c)
+#define FIMG2D_MSK_XSCALE_REG			(0x540)
+#define FIMG2D_MSK_YSCALE_REG			(0x544)
+#define FIMG2D_CW_LT_REG			(0x600)
+#define FIMG2D_CW_RB_REG			(0x604)
+#define FIMG2D_THIRD_OPERAND_REG		(0x610)
+#define FIMG2D_ROP4_REG				(0x614)
+#define FIMG2D_ALPHA_REG			(0x618)
+#define FIMG2D_FG_COLOR_REG			(0x700)
+#define FIMG2D_BG_COLOR_REG			(0x704)
+#define FIMG2D_BS_COLOR_REG			(0x708)
+#define FIMG2D_SF_COLOR_REG			(0x70c)
+#define FIMG2D_SRC_COLORKEY_CTRL_REG		(0x710)
+#define FIMG2D_SRC_COLORKEY_DR_MIN_REG		(0x714)
+#define FIMG2D_SRC_COLORKEY_DR_MAX_REG		(0x718)
+#define FIMG2D_DST_COLORKEY_CTRL_REG		(0x71c)
+#define FIMG2D_DST_COLORKEY_DR_MIN_REG		(0x720)
+#define FIMG2D_DST_COLORKEY_DR_MAX_REG		(0x724)
+#define FIMG2D_YCBCR_SRC_COLORKEY_CTRL_REG	(0x728)
+#define FIMG2D_YCBCR_SRC_COLORKEY_DR_MIN_REG	(0x72c)
+#define FIMG2D_YCBCR_SRC_COLORKEY_DR_MAX_REG	(0x730)
+#define FIMG2D_YCBCR_DST_COLORKEY_CTRL_REG	(0x734)
+#define FIMG2D_YCBCR_DST_COLORKEY_DR_MIN_REG	(0x738)
+#define FIMG2D_YCBCR_DST_COLORKEY_DR_MAX_REG	(0x73c)
+#define FIMG2D_GAMMA_TABLE0_0_REG		(0x800)
+#define FIMG2D_GAMMA_TABLE0_1_REG		(0x804)
+#define FIMG2D_GAMMA_TABLE0_2_REG		(0x808)
+#define FIMG2D_GAMMA_TABLE0_3_REG		(0x80c)
+#define FIMG2D_GAMMA_TABLE0_4_REG		(0x810)
+#define FIMG2D_GAMMA_TABLE0_5_REG		(0x814)
+#define FIMG2D_GAMMA_TABLE0_6_REG		(0x818)
+#define FIMG2D_GAMMA_TABLE0_7_REG		(0x81c)
+#define FIMG2D_GAMMA_TABLE0_8_REG		(0x820)
+#define FIMG2D_GAMMA_TABLE0_9_REG		(0x824)
+#define FIMG2D_GAMMA_TABLE0_10_REG		(0x828)
+#define FIMG2D_GAMMA_TABLE0_11_REG		(0x82c)
+#define FIMG2D_GAMMA_TABLE0_12_REG		(0x830)
+#define FIMG2D_GAMMA_TABLE0_13_REG		(0x834)
+#define FIMG2D_GAMMA_TABLE0_14_REG		(0x838)
+#define FIMG2D_GAMMA_TABLE0_15_REG		(0x83c)
+#define FIMG2D_GAMMA_TABLE1_0_REG		(0x840)
+#define FIMG2D_GAMMA_TABLE1_1_REG		(0x844)
+#define FIMG2D_GAMMA_TABLE1_2_REG		(0x848)
+#define FIMG2D_GAMMA_TABLE1_3_REG		(0x84c)
+#define FIMG2D_GAMMA_TABLE1_4_REG		(0x850)
+#define FIMG2D_GAMMA_TABLE1_5_REG		(0x854)
+#define FIMG2D_GAMMA_TABLE1_6_REG		(0x858)
+#define FIMG2D_GAMMA_TABLE1_7_REG		(0x85c)
+#define FIMG2D_GAMMA_TABLE1_8_REG		(0x860)
+#define FIMG2D_GAMMA_TABLE1_9_REG		(0x864)
+#define FIMG2D_GAMMA_TABLE1_10_REG		(0x868)
+#define FIMG2D_GAMMA_TABLE1_11_REG		(0x86c)
+#define FIMG2D_GAMMA_TABLE1_12_REG		(0x870)
+#define FIMG2D_GAMMA_TABLE1_13_REG		(0x874)
+#define FIMG2D_GAMMA_TABLE1_14_REG		(0x878)
+#define FIMG2D_GAMMA_TABLE1_15_REG		(0x87c)
+#define FIMG2D_GAMMA_REF_COLOR_REG		(0x880)
+
+/* Bit Definitions */
+
+/* FIMG2D_SOFT_RESET_REG */
+#define FIMG2D_SFR_CLEAR			(1 << 1)
+#define FIMG2D_SOFT_RESET			(1 << 0)
+
+/* FIMG2D_INTEN_REG */
+#define FIMG2D_INT_TYPE_EDGE			(1 << 4)
+#define FIMG2D_INT_TYPE_LEVEL			(0 << 4)
+
+#define FIMG2D_ACF_INT_ENABLE			(1 << 3)
+#define FIMG2D_UCF_INT_ENABLE			(1 << 2)
+#define FIMG2D_GCF_INT_ENABLE			(1 << 1)
+#define FIMG2D_BLIT_INT_ENABLE			(1 << 0)
+
+/* FIMG2D_INTC_PEND_REG */
+#define FIMG2D_ACMD_INT_FLAG			(1 << 3)
+#define FIMG2D_UCMD_INT_FLAG			(1 << 2)
+#define FIMG2D_GCMD_INT_FLAG			(1 << 1)
+#define FIMG2D_BLIT_INT_FLAG			(1 << 0)
+
+/* FIMG2D_FIFO_STAT_REG */
+#define FIMG2D_BLIT_FINISHED			(1 << 0)
+
+/* FIMG2D_AXI_MODE_REG */
+#define FIMG2D_MAX_BURST_LEN_2			(0 << 24)
+#define FIMG2D_MAX_BURST_LEN_4			(1 << 24)
+#define FIMG2D_MAX_BURST_LEN_8			(2 << 24)
+#define FIMG2D_MAX_BURST_LEN_16			(3 << 24)
+#define FIMG2D_MAX_BURST_LEN_MASK		(3 << 24)
+#define FIMG2D_MAX_BURST_LEN_SHIFT		(24)
+
+#define FIMG2D_AXI_AWUSERS_SHIFT		(16)
+#define FIMG2D_AXI_ARUSERS_SHIFT		(8)
+#define FIMG2D_AXI_AWCACHE_SHIFT		(4)
+#define FIMG2D_AXI_ARCACHE_SHIFT		(0)
+
+/* FIMG2D_DMA_SFR_BASE_ADDR_REG */
+
+/* FIMG2D_DMA_COMMAND_REG */
+#define FIMG2D_BATCH_BLIT_HALT			(1 << 2)
+#define FIMG2D_BATCH_BLIT_CONT			(1 << 1)
+#define FIMG2D_BATCH_BLIT_START			(1 << 0)
+
+/* FIMG2D_DMA_EXE_LIST_NUM_REG */
+#define FIMG2D_BATCH_BLIT_EXELIST_NUM_MASK	(0xff)
+#define FIMG2D_BATCH_BLIT_EXELIST_NUM_SHIFT	(0)
+
+/* FIMG2D_DMA_STATUS_REG */
+#define FIMG2D_BATCH_BLIT_DONELIST_CNT_MASK	(0xff)
+#define FIMG2D_BATCH_BLIT_DONELIST_CNT_SHIFT	(17)
+
+#define FIMG2D_BATCH_BLIT_DONEBLIT_CNT_MASK	(0xffff)
+#define FIMG2D_BATCH_BLIT_DONEBLIT_CNT_SHIFT	(1)
+
+#define FIMG2D_BATCH_BLIT_DONE_MASK		(1)
+#define FIMG2D_BATCH_BLIT_DONE_SHIFT		(0)
+
+/* FIMG2D_DMA_HOLD_CMD_REG */
+#define FIMG2D_BATCH_BLIT_USER_HOLD		(1 << 2)
+#define FIMG2D_BATCH_BLIT_LIST_HOLD		(1 << 1)
+#define FIMG2D_BATCH_BLIT_BLIT_HOLD		(1 << 0)
+
+/* FIMG2D_BITBLT_START_REG */
+#define FIMG2D_START_N_HOLD			(1 << 1)
+#define FIMG2D_START_BITBLT			(1 << 0)
+
+/* FIMG2D_BITBLT_COMMAND_REG */
+#define FIMG2D_SOLID_FILL			(1 << 28)
+
+#define FIMG2D_DST_WR_DEPREMULT			(1 << 27)
+#define FIMG2D_DST_RD_PREMULT			(1 << 26)
+#define FIMG2D_PAT_PREMULT			(1 << 25)
+#define FIMG2D_SRC_PREMULT			(1 << 24)
+#define FIMG2D_PREMULT_ALL			(0xf << 24)
+
+#define FIMG2D_ALPHA_BLEND_MODE			(1 << 20)
+
+#define FIMG2D_COLORKEY_SRC_RGBA		(1 << 16)
+#define FIMG2D_COLORKEY_DST_RGBA		(2 << 16)
+#define FIMG2D_COLORKEY_SRC_YCBCR		(4 << 16)
+#define FIMG2D_COLORKEY_DST_YCBCR		(8 << 16)
+
+#define FIMG2D_OPAQUE_MODE			(0 << 12)
+#define FIMG2D_TRANSP_MODE			(1 << 12)
+#define FIMG2D_BLUSCR_MODE			(2 << 12)
+
+#define FIMG2D_ENABLE_CW			(1 << 8)
+#define FIMG2D_ENABLE_DITHER			(1 << 3)
+
+#define FIMG2D_ENABLE_SRC_ALPHA			(0 << 2)
+#define FIMG2D_ENABLE_ROP_ALPHA			(1 << 2)
+
+#define FIMG2D_ENABLE_ROP4_MSK			(1 << 0)
+#define FIMG2D_ENABLE_NORMAL_MSK		(2 << 0)
+
+/* FIMG2D_BLEND_FUNCTION_REG */
+#define FIMG2D_WINCE_SRC_OVER			(1 << 22)
+#define FIMG2D_DARKEN				(1 << 21)
+#define FIMG2D_LIGHTEN				(1 << 20)
+#define FIMG2D_INV_DST_COEFF			(1 << 18)
+#define FIMG2D_INV_SRC_COEFF			(1 << 16)
+
+#define FIMG2D_DST_COEFF_DA_SHIFT		(14)
+#define FIMG2D_DST_COEFF_SA_SHIFT		(12)
+#define FIMG2D_SRC_COEFF_DA_SHIFT		(6)
+#define FIMG2D_SRC_COEFF_SA_SHIFT		(4)
+
+#define FIMG2D_DST_COEFF_SHIFT			(8)
+#define FIMG2D_SRC_COEFF_SHIFT			(0)
+
+/* FIMG2D_ROUND_MODE_REG */
+#define FIMG2D_PREMULT_ROUND_MASK		(3 << 4)
+#define FIMG2D_PREMULT_ROUND_SHIFT		(4)
+
+#define FIMG2D_BLEND_ROUND_MASK			(3 << 0)
+#define FIMG2D_BLEND_ROUND_SHIFT		(0)
+
+/* FIMG2D_ROTATE_REG */
+#define FIMG2D_MSK_ROTATE_90			(1 << 8)
+#define FIMG2D_PAT_ROTATE_90			(1 << 4)
+#define FIMG2D_SRC_ROTATE_90			(1 << 0)
+
+/* FIMG2D_SRC_MSK_DIRECT_REG */
+#define FIMG2D_MSK_Y_DIR_NEGATIVE		(1 << 5)
+#define FIMG2D_MSK_X_DIR_NEGATIVE		(1 << 4)
+
+#define FIMG2D_SRC_Y_DIR_NEGATIVE		(1 << 1)
+#define FIMG2D_SRC_X_DIR_NEGATIVE		(1 << 0)
+
+/* FIMG2D_DST_PAT_DIRECT_REG */
+#define FIMG2D_PAT_Y_DIR_NEGATIVE		(1 << 5)
+#define FIMG2D_PAT_X_DIR_NEGATIVE		(1 << 4)
+
+#define FIMG2D_DST_Y_DIR_NEGATIVE		(1 << 1)
+#define FIMG2D_DST_X_DIR_NEGATIVE		(1 << 0)
+
+/* FIMG2D_SRC_SELECT_REG & FIMG2D_DST_SELECT_REG */
+#define FIMG2D_IMAGE_TYPE_MEMORY		(0 << 0)
+#define FIMG2D_IMAGE_TYPE_FGCOLOR		(1 << 0)
+#define FIMG2D_IMAGE_TYPE_BGCOLOR		(2 << 0)
+
+/* FIMG2D_SRC_BASE_ADDR_REG */
+/* FIMG2D_DST_BASE_ADDR_REG */
+/* FIMG2D_PAT_BASE_ADDR_REG */
+/* FIMG2D_MSK_BASE_ADDR_REG */
+
+/* FIMG2D_SRC_STRIDE_REG */
+/* FIMG2D_DST_STRIDE_REG */
+/* FIMG2D_PAT_STRIDE_REG */
+/* FIMG2D_MSK_STRIDE_REG */
+
+/* FIMG2D_SRC_COLOR_MODE_REG & FIMG2D_DST_COLOR_MODE_REG */
+#define FIMG2D_YCBCR_NARROW			(0 << 17)
+#define FIMG2D_YCBCR_WIDE			(1 << 17)
+
+#define FIMG2D_CSC_601				(0 << 16)
+#define FIMG2D_CSC_709				(1 << 16)
+
+#define FIMG2D_YCBCR_ORDER_P1_CRY1CBY0		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_CBY1CRY0		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_Y1CRY0CB		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_Y1CBY0CR		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P2_CRCB		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P2_CBCR		(1 << 12)
+#define FIMG2D_YCBCR_ORDER_SHIFT		(12)
+
+#define FIMG2D_YCBCR_1PLANE			(0 << 8)
+#define FIMG2D_YCBCR_2PLANE			(1 << 8)
+
+#define FIMG2D_RGB_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_RGB_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_RGB_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_RGB_ORDER_BGRAX			(3 << 4)
+#define FIMG2D_RGB_ORDER_SHIFT			(4)
+
+#define FIMG2D_COLOR_FORMAT_XRGB_8888		(0 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_8888		(1 << 0)
+#define FIMG2D_COLOR_FORMAT_RGB_565		(2 << 0)
+#define FIMG2D_COLOR_FORMAT_XRGB_1555		(3 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_1555		(4 << 0)
+#define FIMG2D_COLOR_FORMAT_XRGB_4444		(5 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_4444		(6 << 0)
+#define FIMG2D_COLOR_FORMAT_PACKED_RGB_888	(7 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_444		(8 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_422		(9 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_420		(10 << 0)
+#define FIMG2D_COLOR_FORMAT_A8			(11 << 0)
+#define FIMG2D_COLOR_FORMAT_L8			(12 << 0)
+#define FIMG2D_COLOR_FORMAT_SHIFT		(0)
+
+/* FIMG2D_PAT_COLOR_MODE_REG */
+#define FIMG2D_PAT_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_PAT_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_PAT_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_PAT_ORDER_BGRAX			(3 << 4)
+
+#define FIMG2D_PAT_FORMAT_XRGB_8888		(0 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_8888		(1 << 0)
+#define FIMG2D_PAT_FORMAT_RGB_565		(2 << 0)
+#define FIMG2D_PAT_FORMAT_XRGB_1555		(3 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_1555		(4 << 0)
+#define FIMG2D_PAT_FORMAT_XRGB_4444		(5 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_4444		(6 << 0)
+#define FIMG2D_PAT_FORMAT_PACKED_RGB_888	(7 << 0)
+
+/* FIMG2D_SRC_LEFT_TOP_REG & FIMG2D_SRC_RIGHT_BOTTOM_REG */
+/* FIMG2D_DST_LEFT_TOP_REG & FIMG2D_DST_RIGHT_BOTTOM_REG */
+/* FIMG2D_MSK_LEFT_TOP_REG & FIMG2D_MSK_RIGHT_BOTTOM_REG */
+#define FIMG2D_COORD_LT_Y_SHIFT			(16)
+#define FIMG2D_COORD_LT_X_SHIFT			(0)
+#define FIMG2D_COORD_RB_Y_SHIFT			(16)
+#define FIMG2D_COORD_RB_X_SHIFT			(0)
+#define FIMG2D_COORD_MAX_HEIGHT			(8000)
+#define FIMG2D_COORD_MAX_WIDTH			(8000)
+
+/* FIMG2D_SRC_PLANE2_BASE_ADDR_REG */
+/* FIMG2D_DST_PLANE2_BASE_ADDR_REG */
+
+/* FIMG2D_SRC_REPEAT_MODE_REG */
+#define FIMG2D_SRC_REPEAT_NORMAL		(0 << 0)
+#define FIMG2D_SRC_REPEAT_PAD			(1 << 0)
+#define FIMG2D_SRC_REPEAT_REFLECT		(2 << 0)
+#define FIMG2D_SRC_REPEAT_CLAMP			(3 << 0)
+#define FIMG2D_SRC_REPEAT_NONE			(4 << 0)
+#define FIMG2D_SRC_REPEAT_SHIFT			(0)
+
+/* FIMG2D_MSK_REPEAT_MODE_REG */
+#define FIMG2D_MSK_REPEAT_NORMAL		(0 << 0)
+#define FIMG2D_MSK_REPEAT_PAD			(1 << 0)
+#define FIMG2D_MSK_REPEAT_REFLECT		(2 << 0)
+#define FIMG2D_MSK_REPEAT_CLAMP			(3 << 0)
+#define FIMG2D_MSK_REPEAT_SHIFT			(0)
+
+/* FIMG2D_SRC_PAD_VALUE_REG */
+/* FIMG2D_MSK_PAD_VALUE_REG */
+
+/* FIMG2D_SRC_A8_RGB_EXT_REG */
+/* FIMG2D_DST_A8_RGB_EXT_REG */
+
+/* FIMG2D_SRC_SCALE_CTRL_REG & FIMG2D_MSK_SCALE_CTRL_REG */
+#define FIMG2D_SCALE_MODE_NEAREST		(1 << 0)
+#define FIMG2D_SCALE_MODE_BILINEAR		(2 << 0)
+
+/* FIMG2D_SRC_XSCALE_REG & FIMG2D_SRC_YSCALE_REG */
+/* FIMG2D_MSK_XSCALE_REG & FIMG2D_MSK_YSCALE_REG */
+#define FIMG2D_SCALE_FACTOR_INTG_SHIFT		(16)
+#define FIMG2D_SCALE_FACTOR_FRAC_SHIFT		(0)
+
+/* FIMG2D_PAT_SIZE_REG */
+#define FIMG2D_PAT_HEIGHT_SHIFT			(16)
+#define FIMG2D_PAT_WIDTH_SHIFT			(0)
+#define FIMG2D_MAX_PAT_HEIGHT			(8000)
+#define FIMG2D_MAX_PAT_WIDTH			(8000)
+
+/* FIMG2D_PAT_OFFSET_REG */
+#define FIMG2D_PAT_Y_OFFSET_SHIFT		(16)
+#define FIMG2D_PAT_X_OFFSET_SHIFT		(0)
+#define FIMG2D_MAX_PAT_Y_OFFSET			(7999)
+#define FIMG2D_MAX_PAT_X_OFFSET			(7999)
+
+/* FIMG2D_MSK_MODE_REG */
+#define FIMG2D_MSK_TYPE_ALPHA			(0 << 8)
+#define FIMG2D_MSK_TYPE_ARGB			(1 << 8)
+#define FIMG2D_MSK_TYPE_MIXED			(2 << 8)
+
+#define FIMG2D_MSK_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_MSK_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_MSK_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_MSK_ORDER_BGRAX			(3 << 4)
+#define FIMG2D_MSK_ORDER_SHIFT			(4)
+
+#define FIMG2D_1BIT_MSK				(0 << 0)
+#define FIMG2D_4BIT_MSK				(1 << 0)
+#define FIMG2D_8BIT_MSK				(2 << 0)
+#define FIMG2D_16BIT_MSK_565			(3 << 0)
+#define FIMG2D_16BIT_MSK_1555			(4 << 0)
+#define FIMG2D_16BIT_MSK_4444			(5 << 0)
+#define FIMG2D_32BIT_MSK_8888			(6 << 0)
+#define FIMG2D_4BIT_MSK_WINCE_AA_FONT		(7 << 0)
+#define FIMG2D_MSK_FORMAT_SHIFT			(0)
+
+/* FIMG2D_CW_LT_REG */
+#define FIMG2D_CW_COORD_LT_Y_SHIFT		(16)
+#define FIMG2D_CW_COORD_LT_X_SHIFT		(0)
+#define FIMG2D_CW_COORD_RB_Y_SHIFT		(16)
+#define FIMG2D_CW_COORD_RB_X_SHIFT		(0)
+
+/* FIMG2D_THIRD_OPERAND_REG */
+#define FIMG2D_OPR3_MSKSEL_PAT			(0 << 4)
+#define FIMG2D_OPR3_MSKSEL_FGCOLOR		(1 << 4)
+#define FIMG2D_OPR3_MSKSEL_BGCOLOR		(2 << 4)
+#define FIMG2D_OPR3_UNMSKSEL_PAT		(0 << 0)
+#define FIMG2D_OPR3_UNMSKSEL_FGCOLOR		(1 << 0)
+#define FIMG2D_OPR3_UNMSKSEL_BGCOLOR		(2 << 0)
+
+/* FIMG2D_ROP4_REG */
+#define FIMG2D_MASKED_ROP3_SHIFT		(8)
+#define FIMG2D_UNMASKED_ROP3_SHIFT		(0)
+
+/* FIMG2D_ALPHA_REG */
+#define FIMG2D_GCOLOR_RGB_MASK			(0xffffff)
+#define FIMG2D_GCOLOR_SHIFT			(8)
+
+#define FIMG2D_GALPHA_MASK			(0xff)
+#define FIMG2D_GALPHA_SHIFT			(0)
+
+/* FIMG2D_FG_COLOR_REG */
+/* FIMG2D_BG_COLOR_REG */
+/* FIMG2D_BS_COLOR_REG */
+/* FIMG2D_SF_COLOR_REG */
+
+/* FIMG2D_SRC_COLORKEY_CTRL_REG */
+/* FIMG2D_SRC_COLORKEY_DR_MIN_REG */
+/* FIMG2D_SRC_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_DST_COLORKEY_CTRL_REG */
+/* FIMG2D_DST_COLORKEY_DR_MIN_REG */
+/* FIMG2D_DST_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_YCBCR_SRC_COLORKEY_CTRL_REG */
+/* FIMG2D_YCBCR_SRC_COLORKEY_DR_MIN_REG */
+/* FIMG2D_YCBCR_SRC_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_YCBCR_DST_COLORKEY_CTRL_REG */
+/* FIMG2D_YCBCR_DST_COLORKEY_DR_MIN_REG */
+/* FIMG2D_YCBCR_DST_COLORKEY_DR_MAX_REG */
+
+#endif /* __FIMG2D4X_REGS_H */
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.c
new file mode 100644
index 0000000..43489e4
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.c
@@ -0,0 +1,168 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/pgtable.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+#include "fimg2d.h"
+#include "fimg2d_cache.h"
+
+#define LV1_SHIFT		20
+#define LV1_PT_SIZE		SZ_1M
+#define LV2_PT_SIZE		SZ_1K
+#define LV2_BASE_MASK		0x3ff
+#define LV2_PT_MASK		0xff000
+#define LV2_SHIFT		12
+#define LV1_DESC_MASK		0x3
+#define LV2_DESC_MASK		0x2
+
+static inline unsigned long virt2phys(struct mm_struct *mm, unsigned long vaddr)
+{
+	unsigned long *pgd;
+	unsigned long *lv1d, *lv2d;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	lv1d = pgd + (vaddr >> LV1_SHIFT);
+
+	if ((*lv1d & LV1_DESC_MASK) != 0x1) {
+		fimg2d_debug("invalid LV1 descriptor, "
+				"pgd %p lv1d 0x%lx vaddr 0x%lx\n",
+				pgd, *lv1d, vaddr);
+		return 0;
+	}
+
+	lv2d = (unsigned long *)phys_to_virt(*lv1d & ~LV2_BASE_MASK) +
+				((vaddr & LV2_PT_MASK) >> LV2_SHIFT);
+
+	if ((*lv2d & LV2_DESC_MASK) != 0x2) {
+		fimg2d_debug("invalid LV2 descriptor, "
+				"pgd %p lv2d 0x%lx vaddr 0x%lx\n",
+				pgd, *lv2d, vaddr);
+		return 0;
+	}
+
+	return (*lv2d & PAGE_MASK) | (vaddr & (PAGE_SIZE-1));
+}
+
+#ifdef CONFIG_OUTER_CACHE
+void fimg2d_dma_sync_outer(struct mm_struct *mm, unsigned long vaddr,
+					size_t size, enum cache_opr opr)
+{
+	int len;
+	unsigned long cur, end, next, paddr;
+
+	cur = vaddr;
+	end = vaddr + size;
+
+	if (opr == CACHE_CLEAN) {
+		while (cur < end) {
+			next = (cur + PAGE_SIZE) & PAGE_MASK;
+			if (next > end)
+				next = end;
+			len = next - cur;
+
+			paddr = virt2phys(mm, cur);
+			if (paddr)
+				outer_clean_range(paddr, paddr + len);
+			cur += len;
+		}
+	} else if (opr == CACHE_FLUSH) {
+		while (cur < end) {
+			next = (cur + PAGE_SIZE) & PAGE_MASK;
+			if (next > end)
+				next = end;
+			len = next - cur;
+
+			paddr = virt2phys(mm, cur);
+			if (paddr)
+				outer_flush_range(paddr, paddr + len);
+			cur += len;
+		}
+	}
+}
+
+void fimg2d_clean_outer_pagetable(struct mm_struct *mm, unsigned long vaddr,
+					size_t size)
+{
+	unsigned long *pgd;
+	unsigned long *lv1, *lv1end;
+	unsigned long lv2pa;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	lv1 = pgd + (vaddr >> LV1_SHIFT);
+	lv1end = pgd + ((vaddr + size + LV1_PT_SIZE-1) >> LV1_SHIFT);
+
+	/* clean level1 page table */
+	outer_clean_range(virt_to_phys(lv1), virt_to_phys(lv1end));
+
+	do {
+		lv2pa = *lv1 & ~LV2_BASE_MASK;	/* lv2 pt base */
+		/* clean level2 page table */
+		outer_clean_range(lv2pa, lv2pa + LV2_PT_SIZE);
+		lv1++;
+	} while (lv1 != lv1end);
+}
+#endif /* CONFIG_OUTER_CACHE */
+
+enum pt_status fimg2d_check_pagetable(struct mm_struct *mm, unsigned long vaddr,
+					size_t size)
+{
+	unsigned long *pgd;
+	unsigned long *lv1d, *lv2d;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	size += offset_in_page(vaddr);
+	size = PAGE_ALIGN(size);
+
+	while ((long)size > 0) {
+		lv1d = pgd + (vaddr >> LV1_SHIFT);
+
+		/*
+		 * check level 1 descriptor
+		 *	lv1 desc[1:0] = 00 --> fault
+		 *	lv1 desc[1:0] = 01 --> page table
+		 *	lv1 desc[1:0] = 10 --> section or supersection
+		 *	lv1 desc[1:0] = 11 --> reserved
+		 */
+		if ((*lv1d & LV1_DESC_MASK) != 0x1) {
+			fimg2d_debug("invalid LV1 descriptor, "
+					"pgd %p lv1d 0x%lx vaddr 0x%lx\n",
+					pgd, *lv1d, vaddr);
+			return PT_FAULT;
+		}
+
+		lv2d = (unsigned long *)phys_to_virt(*lv1d & ~LV2_BASE_MASK) +
+				((vaddr & LV2_PT_MASK) >> LV2_SHIFT);
+
+		/*
+		 * check level 2 descriptor
+		 *	lv2 desc[1:0] = 00 --> fault
+		 *	lv2 desc[1:0] = 01 --> 64k pgae
+		 *	lv2 desc[1:0] = 1x --> 4k page
+		 */
+		if ((*lv2d & LV2_DESC_MASK) != 0x2) {
+			fimg2d_debug("invalid LV2 descriptor, "
+					"pgd %p lv2d 0x%lx vaddr 0x%lx\n",
+					pgd, *lv2d, vaddr);
+			return PT_FAULT;
+		}
+
+		vaddr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+
+	return PT_NORMAL;
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.h
new file mode 100644
index 0000000..f337ea5
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_cache.h
@@ -0,0 +1,96 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+#include <plat/cpu.h>
+#include "fimg2d.h"
+
+#define L1_CACHE_SIZE		SZ_64K
+#define L2_CACHE_SIZE		SZ_1M
+#define LINE_FLUSH_THRESHOLD	SZ_1K
+
+/**
+ * cache_opr - [kernel] cache operation mode
+ * @CACHE_INVAL: do cache invalidate
+ * @CACHE_CLEAN: do cache clean for src and msk image
+ * @CACHE_FLUSH: do cache clean and invalidate for dst image
+ * @CACHE_FLUSH_INNER_ALL: clean and invalidate for innercache
+ * @CACHE_FLUSH_ALL: clean and invalidate for whole caches
+ */
+enum cache_opr {
+	CACHE_INVAL,
+	CACHE_CLEAN,
+	CACHE_FLUSH,
+	CACHE_FLUSH_INNER_ALL,
+	CACHE_FLUSH_ALL
+};
+
+/**
+ * @PT_NORMAL: pagetable exists
+ * @PT_FAULT: invalid pagetable
+ */
+enum pt_status {
+	PT_NORMAL,
+	PT_FAULT,
+};
+
+static inline bool is_inner_flushall(size_t size)
+{
+	if (soc_is_exynos5250())
+		return (size >= SZ_1M * 25) ? true : false;
+	else
+		return (size >= L1_CACHE_SIZE) ? true : false;
+}
+
+static inline bool is_outer_flushall(size_t size)
+{
+	return (size >= L2_CACHE_SIZE) ? true : false;
+}
+
+static inline bool is_inner_flushrange(size_t hole)
+{
+	if (!soc_is_exynos5250())
+		return true;
+	else {
+		if (hole < LINE_FLUSH_THRESHOLD)
+			return true;
+		else
+			return false;	/* line-by-line flush */
+	}
+}
+
+static inline bool is_outer_flushrange(size_t hole)
+{
+	if (hole < LINE_FLUSH_THRESHOLD)
+		return true;
+	else
+		return false;	/* line-by-line flush */
+}
+
+static inline void fimg2d_dma_sync_inner(unsigned long addr, size_t size, int dir)
+{
+	if (dir == DMA_TO_DEVICE)
+		dmac_map_area((void *)addr, size, dir);
+	else if (dir == DMA_BIDIRECTIONAL)
+		dmac_flush_range((void *)addr, (void *)(addr + size));
+}
+
+static inline void fimg2d_dma_unsync_inner(unsigned long addr, size_t size, int dir)
+{
+	if (dir == DMA_TO_DEVICE)
+		dmac_unmap_area((void *)addr, size, dir);
+}
+
+void fimg2d_clean_outer_pagetable(struct mm_struct *mm, unsigned long addr, size_t size);
+void fimg2d_dma_sync_outer(struct mm_struct *mm, unsigned long addr, size_t size, enum cache_opr opr);
+enum pt_status fimg2d_check_pagetable(struct mm_struct *mm, unsigned long addr, size_t size);
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.c
new file mode 100644
index 0000000..24a80ae
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.c
@@ -0,0 +1,170 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/atomic.h>
+#include <linux/sched.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+
+void fimg2d_clk_on(struct fimg2d_control *info)
+{
+	spin_lock(&info->bltlock);
+	clk_enable(info->clock);
+	atomic_set(&info->clkon, 1);
+	spin_unlock(&info->bltlock);
+
+	fimg2d_debug("clock enable\n");
+}
+
+void fimg2d_clk_off(struct fimg2d_control *info)
+{
+	spin_lock(&info->bltlock);
+	atomic_set(&info->clkon, 0);
+	clk_disable(info->clock);
+	spin_unlock(&info->bltlock);
+
+	fimg2d_debug("clock disable\n");
+}
+
+void fimg2d_clk_save(struct fimg2d_control *info)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		struct clk *sclk;
+
+		pdata = to_fimg2d_plat(info->dev);
+
+		spin_lock(&info->bltlock);
+		sclk = clk_get(info->dev, pdata->clkname);
+		clk_set_rate(sclk, 50*MHZ); /* 800MHz/16=50MHz */
+		spin_unlock(&info->bltlock);
+
+		fimg2d_debug("%s clkrate=%lu\n", pdata->clkname, clk_get_rate(sclk));
+	}
+}
+
+void fimg2d_clk_restore(struct fimg2d_control *info)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		struct clk *sclk, *pclk;
+
+		pdata = to_fimg2d_plat(info->dev);
+
+		spin_lock(&info->bltlock);
+		sclk = clk_get(info->dev, pdata->clkname);
+		pclk = clk_get(NULL, "pclk_acp");
+		clk_set_rate(sclk, clk_get_rate(pclk) * 2);
+		spin_unlock(&info->bltlock);
+
+		fimg2d_debug("%s(%lu) pclk_acp(%lu)\n", pdata->clkname,
+				clk_get_rate(sclk), clk_get_rate(pclk));
+	}
+}
+
+void fimg2d_clk_dump(struct fimg2d_control *info)
+{
+	struct fimg2d_platdata *pdata;
+	struct clk *sclk, *pclk, *aclk;
+
+	pdata = to_fimg2d_plat(info->dev);
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		sclk = clk_get(info->dev, pdata->clkname);
+		pclk = clk_get(NULL, "pclk_acp");
+
+		printk(KERN_INFO "%s(%lu) pclk_acp(%lu)\n",
+				pdata->clkname,
+				clk_get_rate(sclk), clk_get_rate(pclk));
+	} else {
+		aclk = clk_get(NULL, "aclk_acp");
+		pclk = clk_get(NULL, "pclk_acp");
+
+		printk(KERN_INFO "aclk_acp(%lu) pclk_acp(%lu)\n",
+				clk_get_rate(aclk), clk_get_rate(pclk));
+	}
+}
+
+int fimg2d_clk_setup(struct fimg2d_control *info)
+{
+	struct fimg2d_platdata *pdata;
+	struct clk *parent, *sclk;
+	int ret = 0;
+
+	sclk = parent = NULL;
+	pdata = to_fimg2d_plat(info->dev);
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		/* clock for setting parent and rate */
+		parent = clk_get(info->dev, pdata->parent_clkname);
+		if (IS_ERR(parent)) {
+			printk(KERN_ERR "FIMG2D failed to get parent clk\n");
+			ret = -ENOENT;
+			goto err_clk1;
+		}
+		fimg2d_debug("parent clk: %s\n", pdata->parent_clkname);
+
+		sclk = clk_get(info->dev, pdata->clkname);
+		if (IS_ERR(sclk)) {
+			printk(KERN_ERR "FIMG2D failed to get sclk\n");
+			ret = -ENOENT;
+			goto err_clk2;
+		}
+		fimg2d_debug("sclk: %s\n", pdata->clkname);
+
+		if (clk_set_parent(sclk, parent))
+			printk(KERN_ERR "FIMG2D failed to set parent\n");
+
+		clk_set_rate(sclk, pdata->clkrate);
+		fimg2d_debug("clkrate: %ld parent clkrate: %ld\n",
+				clk_get_rate(sclk), clk_get_rate(parent));
+	} else {
+		fimg2d_debug("aclk_acp(%lu) pclk_acp(%lu)\n",
+				clk_get_rate(clk_get(NULL, "aclk_acp")),
+				clk_get_rate(clk_get(NULL, "pclk_acp")));
+	}
+
+	/* clock for gating */
+	info->clock = clk_get(info->dev, pdata->gate_clkname);
+	if (IS_ERR(info->clock)) {
+		printk(KERN_ERR "FIMG2D failed to get gate clk\n");
+		ret = -ENOENT;
+		goto err_clk3;
+	}
+	fimg2d_debug("gate clk: %s\n", pdata->gate_clkname);
+	return ret;
+
+err_clk3:
+	if (sclk)
+		clk_put(sclk);
+
+err_clk2:
+	if (parent)
+		clk_put(parent);
+
+err_clk1:
+	return ret;
+}
+
+void fimg2d_clk_release(struct fimg2d_control *info)
+{
+	clk_put(info->clock);
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		pdata = to_fimg2d_plat(info->dev);
+		clk_put(clk_get(info->dev, pdata->clkname));
+		clk_put(clk_get(info->dev, pdata->parent_clkname));
+	}
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.h
new file mode 100644
index 0000000..c3fbf67
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_clk.h
@@ -0,0 +1,26 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_CLK_H__
+#define __FIMG2D_CLK_H__
+
+#include "fimg2d.h"
+
+int fimg2d_clk_setup(struct fimg2d_control *info);
+void fimg2d_clk_release(struct fimg2d_control *info);
+void fimg2d_clk_on(struct fimg2d_control *info);
+void fimg2d_clk_off(struct fimg2d_control *info);
+void fimg2d_clk_save(struct fimg2d_control *info);
+void fimg2d_clk_restore(struct fimg2d_control *info);
+void fimg2d_clk_dump(struct fimg2d_control *info);
+
+#endif /* __FIMG2D_CLK_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.c
new file mode 100644
index 0000000..26ea56b
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.c
@@ -0,0 +1,368 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <plat/fimg2d.h>
+#include "fimg2d.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+static int fimg2d_check_params(struct fimg2d_bltcmd *cmd)
+{
+	int w, h, i;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_scale *scl;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+
+	/* dst is mandatory */
+	if (!cmd->image[IDST].addr.type)
+		return -1;
+
+	/* DST op makes no effect */
+	if (cmd->op < 0 || cmd->op == BLIT_OP_DST || cmd->op >= BLIT_OP_END)
+		return -1;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		w = img->width;
+		h = img->height;
+		r = &img->rect;
+
+		/* 8000: max width & height */
+		if (w > 8000 || h > 8000)
+			return -1;
+
+		if (r->x1 < 0 || r->y1 < 0 ||
+			r->x1 >= w || r->y1 >= h ||
+			r->x1 >= r->x2 || r->y1 >= r->y2)
+			return -1;
+	}
+
+	clp = &p->clipping;
+	if (clp->enable) {
+		img = &cmd->image[IDST];
+
+		w = img->width;
+		h = img->height;
+		r = &img->rect;
+
+		if (clp->x1 < 0 || clp->y1 < 0 ||
+			clp->x1 >= w || clp->y1 >= h ||
+			clp->x1 >= clp->x2 || clp->y1 >= clp->y2 ||
+			clp->x1 >= r->x2 || clp->x2 <= r->x1 ||
+			clp->y1 >= r->y2 || clp->y2 <= r->y1)
+			return -1;
+	}
+
+	scl = &p->scaling;
+	if (scl->mode) {
+		if (!scl->src_w || !scl->src_h || !scl->dst_w || !scl->dst_h)
+			return -1;
+	}
+
+	return 0;
+}
+
+static void fimg2d_fixup_params(struct fimg2d_bltcmd *cmd)
+{
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_scale *scl;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	int i;
+
+	clp = &p->clipping;
+	scl = &p->scaling;
+
+	/* fix dst/clip rect */
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		r = &img->rect;
+
+		if (i == IMAGE_DST && clp->enable) {
+			if (clp->x2 > img->width)
+				clp->x2 = img->width;
+			if (clp->y2 > img->height)
+				clp->y2 = img->height;
+		} else {
+			if (r->x2 > img->width)
+				r->x2 = img->width;
+			if (r->y2 > img->height)
+				r->y2 = img->height;
+		}
+	}
+
+	/* avoid devided-by-zero */
+	if (scl->mode &&
+		(scl->src_w == scl->dst_w && scl->src_h == scl->dst_h))
+		scl->mode = NO_SCALING;
+}
+
+static int fimg2d_check_dma_sync(struct fimg2d_bltcmd *cmd)
+{
+	struct mm_struct *mm = cmd->ctx->mm;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+	enum pt_status pt;
+	int clip_x, clip_w, clip_h, y, dir, i;
+	unsigned long clip_start;
+
+	clp = &p->clipping;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		c = &cmd->dma[i];
+		r = &img->rect;
+
+		if (!img->addr.type)
+			continue;
+
+		/* caculate horizontally clipped region */
+		if (i == IMAGE_DST && clp->enable) {
+			c->addr = img->addr.start + (img->stride * clp->y1);
+			c->size = img->stride * (clp->y2 - clp->y1);
+		} else {
+			c->addr = img->addr.start + (img->stride * r->y1);
+			c->size = img->stride * (r->y2 - r->y1);
+		}
+
+		/* check pagetable */
+		if (img->addr.type == ADDR_USER) {
+			pt = fimg2d_check_pagetable(mm, c->addr, c->size);
+			if (pt == PT_FAULT)
+				return -1;
+		}
+
+		if (img->need_cacheopr && i != IMAGE_TMP) {
+			c->cached = c->size;
+			cmd->dma_all += c->cached;
+		}
+	}
+
+#ifdef PERF_PROFILE
+	perf_start(cmd->ctx, PERF_INNERCACHE);
+#endif
+
+	if (is_inner_flushall(cmd->dma_all))
+		flush_all_cpu_caches();
+	else {
+		for (i = 0; i < MAX_IMAGES; i++) {
+			img = &cmd->image[i];
+			c = &cmd->dma[i];
+			r = &img->rect;
+
+			if (!img->addr.type || !c->cached)
+				continue;
+
+			if (i == IMAGE_DST)
+				dir = DMA_BIDIRECTIONAL;
+			else
+				dir = DMA_TO_DEVICE;
+
+			if (i == IDST && clp->enable) {
+				clip_w = width2bytes(clp->x2 - clp->x1,
+							img->fmt);
+				clip_x = pixel2offset(clp->x1, img->fmt);
+				clip_h = clp->y2 - clp->y1;
+			} else {
+				clip_w = width2bytes(r->x2 - r->x1, img->fmt);
+				clip_x = pixel2offset(r->x1, img->fmt);
+				clip_h = r->y2 - r->y1;
+			}
+
+			if (is_inner_flushrange(img->stride - clip_w))
+				fimg2d_dma_sync_inner(c->addr, c->cached, dir);
+			else {
+				for (y = 0; y < clip_h; y++) {
+					clip_start = c->addr +
+						(img->stride * y) + clip_x;
+					fimg2d_dma_sync_inner(clip_start,
+								clip_w, dir);
+				}
+			}
+		}
+	}
+#ifdef PERF_PROFILE
+	perf_end(cmd->ctx, PERF_INNERCACHE);
+#endif
+
+#ifdef CONFIG_OUTER_CACHE
+#ifdef PERF_PROFILE
+	perf_start(cmd->ctx, PERF_OUTERCACHE);
+#endif
+	if (is_outer_flushall(cmd->dma_all))
+		outer_flush_all();
+	else {
+		for (i = 0; i < MAX_IMAGES; i++) {
+			img = &cmd->image[i];
+			c = &cmd->dma[i];
+			r = &img->rect;
+
+			if (!img->addr.type)
+				continue;
+
+			/* clean pagetable */
+			if (img->addr.type == ADDR_USER)
+				fimg2d_clean_outer_pagetable(mm, c->addr, c->size);
+
+			if (!c->cached)
+				continue;
+
+			if (i == IMAGE_DST)
+				dir = CACHE_FLUSH;
+			else
+				dir = CACHE_CLEAN;
+
+			if (i == IDST && clp->enable) {
+				clip_w = width2bytes(clp->x2 - clp->x1,
+							img->fmt);
+				clip_x = pixel2offset(clp->x1, img->fmt);
+				clip_h = clp->y2 - clp->y1;
+			} else {
+				clip_w = width2bytes(r->x2 - r->x1, img->fmt);
+				clip_x = pixel2offset(r->x1, img->fmt);
+				clip_h = r->y2 - r->y1;
+			}
+
+			if (is_outer_flushrange(img->stride - clip_w))
+				fimg2d_dma_sync_outer(mm, c->addr,
+							c->cached, dir);
+			else {
+				for (y = 0; y < clip_h; y++) {
+					clip_start = c->addr +
+						(img->stride * y) + clip_x;
+					fimg2d_dma_sync_outer(mm, clip_start,
+								clip_w, dir);
+				}
+			}
+		}
+	}
+#ifdef PERF_PROFILE
+	perf_end(cmd->ctx, PERF_OUTERCACHE);
+#endif
+#endif
+
+	return 0;
+}
+
+int fimg2d_add_command(struct fimg2d_control *info, struct fimg2d_context *ctx,
+			struct fimg2d_blit *blit, enum addr_space type)
+{
+	int i, ret;
+	struct fimg2d_image *buf[MAX_IMAGES] = image_table(blit);
+	struct fimg2d_bltcmd *cmd;
+
+	if ((blit->dst) && (type == ADDR_USER))
+		up_write(&page_alloc_slow_rwsem);
+
+	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+
+	if (!cmd) {
+		if ((blit->dst) && (type == ADDR_USER))
+			if (!down_write_trylock(&page_alloc_slow_rwsem))
+				return -EAGAIN;
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		if (!buf[i])
+			continue;
+
+		if (copy_from_user(&cmd->image[i], buf[i],
+					sizeof(struct fimg2d_image))) {
+			if ((blit->dst) && (type == ADDR_USER))
+				if (!down_write_trylock(&page_alloc_slow_rwsem))
+					return -EAGAIN;
+			ret = -EFAULT;
+			goto err_user;
+		}
+	}
+
+	if ((blit->dst) && (type == ADDR_USER))
+		if (!down_write_trylock(&page_alloc_slow_rwsem))
+			return -EAGAIN;
+
+	cmd->ctx = ctx;
+	cmd->op = blit->op;
+	cmd->sync = blit->sync;
+	cmd->seq_no = blit->seq_no;
+	memcpy(&cmd->param, &blit->param, sizeof(cmd->param));
+
+#ifdef CONFIG_VIDEO_FIMG2D_DEBUG
+	fimg2d_dump_command(cmd);
+#endif
+
+	if (fimg2d_check_params(cmd)) {
+		printk(KERN_ERR "[%s] invalid params\n", __func__);
+		fimg2d_dump_command(cmd);
+		ret = -EINVAL;
+		goto err_user;
+	}
+
+	fimg2d_fixup_params(cmd);
+
+	if (fimg2d_check_dma_sync(cmd)) {
+		ret = -EFAULT;
+		goto err_user;
+	}
+
+	/* add command node and increase ncmd */
+	spin_lock(&info->bltlock);
+	if (atomic_read(&info->suspended)) {
+		fimg2d_debug("fimg2d suspended, do sw fallback\n");
+		spin_unlock(&info->bltlock);
+		ret = -EFAULT;
+		goto err_user;
+	}
+	atomic_inc(&ctx->ncmd);
+	fimg2d_enqueue(&cmd->node, &info->cmd_q);
+	fimg2d_debug("ctx %p pgd %p ncmd(%d) seq_no(%u)\n",
+			cmd->ctx, (unsigned long *)cmd->ctx->mm->pgd,
+			atomic_read(&ctx->ncmd), cmd->seq_no);
+	spin_unlock(&info->bltlock);
+
+	return 0;
+
+err_user:
+	kfree(cmd);
+	return ret;
+}
+
+void fimg2d_add_context(struct fimg2d_control *info, struct fimg2d_context *ctx)
+{
+	atomic_set(&ctx->ncmd, 0);
+	init_waitqueue_head(&ctx->wait_q);
+
+	atomic_inc(&info->nctx);
+	fimg2d_debug("ctx %p nctx(%d)\n", ctx, atomic_read(&info->nctx));
+}
+
+void fimg2d_del_context(struct fimg2d_control *info, struct fimg2d_context *ctx)
+{
+	atomic_dec(&info->nctx);
+	fimg2d_debug("ctx %p nctx(%d)\n", ctx, atomic_read(&info->nctx));
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.h
new file mode 100644
index 0000000..995303f
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_ctx.h
@@ -0,0 +1,42 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "fimg2d.h"
+#include "fimg2d_helper.h"
+
+static inline void fimg2d_enqueue(struct list_head *node, struct list_head *q)
+{
+	list_add_tail(node, q);
+}
+
+static inline void fimg2d_dequeue(struct list_head *node)
+{
+	list_del(node);
+}
+
+static inline int fimg2d_queue_is_empty(struct list_head *q)
+{
+	return list_empty(q);
+}
+
+static inline struct fimg2d_bltcmd *fimg2d_get_first_command(struct fimg2d_control *info)
+{
+	if (list_empty(&info->cmd_q))
+		return NULL;
+	else
+		return list_first_entry(&info->cmd_q, struct fimg2d_bltcmd, node);
+}
+
+void fimg2d_add_context(struct fimg2d_control *info, struct fimg2d_context *ctx);
+void fimg2d_del_context(struct fimg2d_control *info, struct fimg2d_context *ctx);
+int fimg2d_add_command(struct fimg2d_control *info, struct fimg2d_context *ctx,
+			struct fimg2d_blit *blit, enum addr_space type);
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_drv.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_drv.c
new file mode 100644
index 0000000..6ae4d6e
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_drv.c
@@ -0,0 +1,515 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_drv.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/dma-mapping.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/atomic.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+#include <plat/s5p-sysmmu.h>
+#include <mach/dev.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_helper.h"
+
+#define CTX_TIMEOUT	msecs_to_jiffies(1000)
+
+static struct fimg2d_control *info;
+
+static void fimg2d_worker(struct work_struct *work)
+{
+	fimg2d_debug("start kernel thread\n");
+	info->blit(info);
+}
+
+static DECLARE_WORK(fimg2d_work, fimg2d_worker);
+
+/**
+ * @irq: irq number
+ * @dev_id: pointer to private data
+ */
+static irqreturn_t fimg2d_irq(int irq, void *dev_id)
+{
+	fimg2d_debug("irq\n");
+	info->stop(info);
+
+	return IRQ_HANDLED;
+}
+
+static int fimg2d_sysmmu_fault_handler(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+		unsigned long pgtable_base, unsigned long fault_addr)
+{
+	struct fimg2d_bltcmd *cmd;
+
+	if (itype == SYSMMU_PAGEFAULT) {
+		printk(KERN_ERR "[%s] sysmmu page fault(0x%lx), pgd(0x%lx)\n",
+				__func__, fault_addr, pgtable_base);
+	} else {
+		printk(KERN_ERR "[%s] sysmmu interrupt "
+				"type(%d) pgd(0x%lx) addr(0x%lx)\n",
+				__func__, itype, pgtable_base, fault_addr);
+	}
+
+	cmd = fimg2d_get_first_command(info);
+	if (!cmd) {
+		printk(KERN_ERR "[%s] null command\n", __func__);
+		goto next;
+	}
+
+	if (cmd->ctx->mm->pgd != phys_to_virt(pgtable_base)) {
+		printk(KERN_ERR "[%s] pgtable base is different from current command\n",
+				__func__);
+		goto next;
+	}
+
+	fimg2d_dump_command(cmd);
+
+next:
+	fimg2d_clk_dump(info);
+	info->dump(info);
+
+	BUG();
+	return 0;
+}
+
+static void fimg2d_context_wait(struct fimg2d_context *ctx)
+{
+	while (atomic_read(&ctx->ncmd)) {
+		if (!wait_event_timeout(ctx->wait_q, !atomic_read(&ctx->ncmd), CTX_TIMEOUT)) {
+			atomic_set(&info->active, 1);
+			queue_work(info->work_q, &fimg2d_work);
+			printk(KERN_ERR "[%s] ctx %p cmd wait timeout\n", __func__, ctx);
+			if (info->err)
+				break;
+		}
+	}
+}
+
+static void fimg2d_request_bitblt(struct fimg2d_context *ctx)
+{
+	spin_lock(&info->bltlock);
+	if (!atomic_read(&info->active)) {
+		atomic_set(&info->active, 1);
+		fimg2d_debug("dispatch ctx %p to kernel thread\n", ctx);
+		queue_work(info->work_q, &fimg2d_work);
+	}
+	spin_unlock(&info->bltlock);
+	fimg2d_context_wait(ctx);
+}
+
+static int fimg2d_open(struct inode *inode, struct file *file)
+{
+	struct fimg2d_context *ctx;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx) {
+		printk(KERN_ERR "[%s] not enough memory for ctx\n", __func__);
+		return -ENOMEM;
+	}
+	file->private_data = (void *)ctx;
+
+	ctx->mm = current->mm;
+	fimg2d_debug("ctx %p current pgd %p init_mm pgd %p\n",
+			ctx, (unsigned long *)ctx->mm->pgd,
+			(unsigned long *)init_mm.pgd);
+
+	fimg2d_add_context(info, ctx);
+	return 0;
+}
+
+static int fimg2d_release(struct inode *inode, struct file *file)
+{
+	struct fimg2d_context *ctx = file->private_data;
+
+	fimg2d_debug("ctx %p\n", ctx);
+	while (1) {
+		if (!atomic_read(&ctx->ncmd))
+			break;
+
+		mdelay(2);
+	}
+	fimg2d_del_context(info, ctx);
+
+	kfree(ctx);
+	return 0;
+}
+
+static int fimg2d_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+static unsigned int fimg2d_poll(struct file *file, struct poll_table_struct *wait)
+{
+	return 0;
+}
+
+static long fimg2d_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	struct fimg2d_context *ctx;
+	struct fimg2d_platdata *pdata;
+	struct fimg2d_blit blit;
+	struct fimg2d_version ver;
+	struct fimg2d_image dst;
+
+	ctx = file->private_data;
+	if (!ctx) {
+		printk(KERN_ERR "[%s] missing ctx\n", __func__);
+		return -EFAULT;
+	}
+
+	switch (cmd) {
+	case FIMG2D_BITBLT_BLIT:
+		if (info->err) {
+			printk(KERN_ERR "[%s] device error, do sw fallback\n",
+					__func__);
+			return -EFAULT;
+		}
+
+		if (copy_from_user(&blit, (void *)arg, sizeof(blit)))
+			return -EFAULT;
+		if (blit.dst)
+			if (copy_from_user(&dst, (void *)blit.dst, sizeof(dst)))
+				return -EFAULT;
+
+#ifdef CONFIG_BUSFREQ_OPP
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			dev_lock(info->bus_dev, info->dev, 160160);
+#endif
+#endif
+		if ((blit.dst) && (dst.addr.type == ADDR_USER))
+			if (!down_write_trylock(&page_alloc_slow_rwsem))
+				ret = -EAGAIN;
+
+		if (ret != -EAGAIN)
+			ret = fimg2d_add_command(info, ctx, &blit, dst.addr.type);
+
+		if (!ret) {
+			fimg2d_request_bitblt(ctx);
+		}
+
+#ifdef PERF_PROFILE
+		perf_print(ctx, blit.seq_no);
+		perf_clear(ctx);
+#endif
+		if ((blit.dst) && (dst.addr.type == ADDR_USER) && ret != -EAGAIN)
+			up_write(&page_alloc_slow_rwsem);
+
+#ifdef CONFIG_BUSFREQ_OPP
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			dev_unlock(info->bus_dev, info->dev);
+#endif
+#endif
+		break;
+
+	case FIMG2D_BITBLT_SYNC:
+		fimg2d_debug("FIMG2D_BITBLT_SYNC ctx: %p\n", ctx);
+		/* FIXME: */
+		break;
+
+	case FIMG2D_BITBLT_VERSION:
+		pdata = to_fimg2d_plat(info->dev);
+		ver.hw = pdata->hw_ver;
+		ver.sw = 0;
+		fimg2d_debug("fimg2d version, hw: 0x%x sw: 0x%x\n",
+				ver.hw, ver.sw);
+		if (copy_to_user((void *)arg, &ver, sizeof(ver)))
+			return -EFAULT;
+		break;
+
+	default:
+		printk(KERN_ERR "[%s] unknown ioctl\n", __func__);
+		ret = -EFAULT;
+		break;
+	}
+
+	return ret;
+}
+
+/* fops */
+static const struct file_operations fimg2d_fops = {
+	.owner          = THIS_MODULE,
+	.open           = fimg2d_open,
+	.release        = fimg2d_release,
+	.mmap           = fimg2d_mmap,
+	.poll           = fimg2d_poll,
+	.unlocked_ioctl = fimg2d_ioctl,
+};
+
+/* miscdev */
+static struct miscdevice fimg2d_dev = {
+	.minor		= FIMG2D_MINOR,
+	.name		= "fimg2d",
+	.fops		= &fimg2d_fops,
+};
+
+static int fimg2d_setup_controller(struct fimg2d_control *info)
+{
+	atomic_set(&info->suspended, 0);
+	atomic_set(&info->clkon, 0);
+	atomic_set(&info->busy, 0);
+	atomic_set(&info->nctx, 0);
+	atomic_set(&info->active, 0);
+
+	spin_lock_init(&info->bltlock);
+
+	INIT_LIST_HEAD(&info->cmd_q);
+	init_waitqueue_head(&info->wait_q);
+	fimg2d_register_ops(info);
+
+	info->work_q = create_singlethread_workqueue("kfimg2dd");
+	if (!info->work_q)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int fimg2d_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct fimg2d_platdata *pdata;
+	int ret;
+
+	pdata = to_fimg2d_plat(&pdev->dev);
+	if (!pdata) {
+		printk(KERN_ERR "FIMG2D failed to get platform data\n");
+		ret = -ENOMEM;
+		goto err_plat;
+	}
+
+	/* global structure */
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		printk(KERN_ERR "FIMG2D failed to allocate memory for controller\n");
+		ret = -ENOMEM;
+		goto err_plat;
+	}
+
+	/* setup global info */
+	ret = fimg2d_setup_controller(info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to setup controller\n");
+		goto err_setup;
+	}
+	info->dev = &pdev->dev;
+
+	/* memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "FIMG2D failed to get resource\n");
+		ret = -ENOENT;
+		goto err_res;
+	}
+
+	info->mem = request_mem_region(res->start, resource_size(res),
+					pdev->name);
+	if (!info->mem) {
+		printk(KERN_ERR "FIMG2D failed to request memory region\n");
+		ret = -ENOMEM;
+		goto err_region;
+	}
+
+	/* ioremap */
+	info->regs = ioremap(res->start, resource_size(res));
+	if (!info->regs) {
+		printk(KERN_ERR "FIMG2D failed to ioremap for SFR\n");
+		ret = -ENOENT;
+		goto err_map;
+	}
+	fimg2d_debug("device name: %s base address: 0x%lx\n",
+			pdev->name, (unsigned long)res->start);
+
+	/* irq */
+	info->irq = platform_get_irq(pdev, 0);
+	if (!info->irq) {
+		printk(KERN_ERR "FIMG2D failed to get irq resource\n");
+		ret = -ENOENT;
+		goto err_map;
+	}
+	fimg2d_debug("irq: %d\n", info->irq);
+
+	ret = request_irq(info->irq, fimg2d_irq, IRQF_DISABLED, pdev->name, info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to request irq\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	ret = fimg2d_clk_setup(info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to setup clk\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_enable(info->dev);
+	fimg2d_debug("enable runtime pm\n");
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	/* To lock bus frequency in OPP mode */
+	info->bus_dev = dev_get("exynos-busfreq");
+#endif
+#endif
+	s5p_sysmmu_set_fault_handler(info->dev, fimg2d_sysmmu_fault_handler);
+	fimg2d_debug("register sysmmu page fault handler\n");
+
+	/* misc register */
+	ret = misc_register(&fimg2d_dev);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to register misc driver\n");
+		goto err_reg;
+	}
+
+	printk(KERN_INFO "Samsung Graphics 2D driver, (c) 2011 Samsung Electronics\n");
+	return 0;
+
+err_reg:
+	fimg2d_clk_release(info);
+
+err_clk:
+	free_irq(info->irq, NULL);
+
+err_irq:
+	iounmap(info->regs);
+
+err_map:
+	kfree(info->mem);
+
+err_region:
+	release_resource(info->mem);
+
+err_res:
+	destroy_workqueue(info->work_q);
+
+err_setup:
+	kfree(info);
+
+err_plat:
+	return ret;
+}
+
+static int fimg2d_remove(struct platform_device *pdev)
+{
+	free_irq(info->irq, NULL);
+
+	if (info->mem) {
+		iounmap(info->regs);
+		release_resource(info->mem);
+		kfree(info->mem);
+	}
+
+	destroy_workqueue(info->work_q);
+	misc_deregister(&fimg2d_dev);
+	kfree(info);
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(&pdev->dev);
+	fimg2d_debug("disable runtime pm\n");
+#endif
+
+	return 0;
+}
+
+static int fimg2d_suspend(struct device *dev)
+{
+	fimg2d_debug("suspend... start\n");
+	atomic_set(&info->suspended, 1);
+	while (1) {
+		if (fimg2d_queue_is_empty(&info->cmd_q))
+			break;
+
+		mdelay(2);
+	}
+	fimg2d_debug("suspend... done\n");
+	return 0;
+}
+
+static int fimg2d_resume(struct device *dev)
+{
+	fimg2d_debug("resume... start\n");
+	atomic_set(&info->suspended, 0);
+	fimg2d_debug("resume... done\n");
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int fimg2d_runtime_suspend(struct device *dev)
+{
+	fimg2d_debug("runtime suspend... done\n");
+	return 0;
+}
+
+static int fimg2d_runtime_resume(struct device *dev)
+{
+	fimg2d_debug("runtime resume... done\n");
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops fimg2d_pm_ops = {
+	.suspend		= fimg2d_suspend,
+	.resume			= fimg2d_resume,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_suspend	= fimg2d_runtime_suspend,
+	.runtime_resume		= fimg2d_runtime_resume,
+#endif
+};
+
+static struct platform_driver fimg2d_driver = {
+	.probe		= fimg2d_probe,
+	.remove		= fimg2d_remove,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "s5p-fimg2d",
+		.pm     = &fimg2d_pm_ops,
+	},
+};
+
+static int __init fimg2d_register(void)
+{
+	return platform_driver_register(&fimg2d_driver);
+}
+
+static void __exit fimg2d_unregister(void)
+{
+	platform_driver_unregister(&fimg2d_driver);
+}
+
+module_init(fimg2d_register);
+module_exit(fimg2d_unregister);
+
+MODULE_AUTHOR("Eunseok Choi <es10.choi@samsung.com>");
+MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
+MODULE_DESCRIPTION("Samsung Graphics 2D driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.c b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.c
new file mode 100644
index 0000000..9346d1b
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.c
@@ -0,0 +1,182 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "fimg2d.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+static int bpptable[MSK_FORMAT_END+1] = {
+	32, 32,	16, 16, 16, 16, 16, 24,	/* rgb */
+	8, 8, 8, 8, 8, 0,		/* yuv */
+	1, 4, 8, 16, 16, 16, 32, 0,	/* msk */
+};
+
+int pixel2offset(int pixel, enum color_format cf)
+{
+	return (pixel * bpptable[cf]) >> 3;
+}
+
+int width2bytes(int width, enum color_format cf)
+{
+	int bpp = bpptable[cf];
+
+	switch (bpp) {
+	case 1:
+		return (width + 7) >> 3;
+	case 4:
+		return (width + 1) >> 1;
+	case 8:
+	case 16:
+	case 24:
+	case 32:
+		return width * bpp >> 3;
+	default:
+		return 0;
+	}
+}
+
+void perf_print(struct fimg2d_context *ctx, int seq_no)
+{
+	int i;
+	long time;
+	struct fimg2d_perf *perf;
+
+	for (i = 0; i < MAX_PERF_DESCS; i++) {
+		perf = &ctx->perf[i];
+		if (perf->valid != 0x11)
+			continue;
+		time = elapsed_usec(ctx, i);
+		printk(KERN_INFO "[FIMG2D PERF (%8s)] ctx(0x%08x) seq(%d) "
+				"%8ld   usec\n",
+				perfname(i), (unsigned int)ctx, seq_no, time);
+	}
+	printk(KERN_INFO "[FIMG2D PERF **]\n");
+}
+
+void fimg2d_print_params(struct fimg2d_blit __user *u)
+{
+	int i;
+	struct fimg2d_param *p = &u->param;
+	struct fimg2d_image *img, *buf[MAX_IMAGES] = image_table(u);
+	struct fimg2d_rect *r;
+
+	printk(KERN_INFO "op: %d\n", u->op);
+	printk(KERN_INFO "solid color: 0x%lx\n", p->solid_color);
+	printk(KERN_INFO "g_alpha: 0x%x\n", p->g_alpha);
+	printk(KERN_INFO "premultiplied: %d\n", p->premult);
+	printk(KERN_INFO "dither: %d\n", p->dither);
+	printk(KERN_INFO "rotate: %d\n", p->rotate);
+	printk(KERN_INFO "repeat mode: %d, pad color: 0x%lx\n",
+			p->repeat.mode, p->repeat.pad_color);
+	printk(KERN_INFO "bluescreen mode: %d, bs_color: 0x%lx "
+			"bg_color: 0x%lx\n",
+			p->bluscr.mode,
+			p->bluscr.bs_color, p->bluscr.bg_color);
+	printk(KERN_INFO "scaling mode: %d, src:%d,%d dst:%d,%d\n",
+			p->scaling.mode,
+			p->scaling.src_w, p->scaling.src_h,
+			p->scaling.dst_w, p->scaling.dst_h);
+	printk(KERN_INFO "clipping mode: %d, LT(%d,%d) RB(%d,%d)\n",
+			p->clipping.enable,
+			p->clipping.x1, p->clipping.y1,
+			p->clipping.x2, p->clipping.y2);
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		if (!buf[i])
+			continue;
+
+		img = buf[i];
+		r = &img->rect;
+
+		printk(KERN_INFO "%s type: %d addr: 0x%lx\n",
+				imagename(i), img->addr.type,
+				img->addr.start);
+		printk(KERN_INFO "%s width: %d height: %d "
+				"stride: %d order: %d format: %d\n",
+				imagename(i), img->width, img->height,
+				img->stride, img->order, img->fmt);
+		printk(KERN_INFO "%s rect LT(%d,%d) RB(%d,%d) WH(%d,%d)\n",
+				imagename(i), r->x1, r->y1, r->x2, r->y2,
+				rect_w(r), rect_h(r));
+		printk(KERN_INFO "%s cacheopr: %d\n",
+				imagename(i), img->need_cacheopr);
+	}
+}
+
+void fimg2d_dump_command(struct fimg2d_bltcmd *cmd)
+{
+	int i;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+
+	printk(KERN_INFO " op: %d\n", cmd->op);
+	printk(KERN_INFO " solid color: 0x%lx\n", p->solid_color);
+	printk(KERN_INFO " g_alpha: 0x%x\n", p->g_alpha);
+	printk(KERN_INFO " premultiplied: %d\n", p->premult);
+	if (p->dither)
+		printk(KERN_INFO " dither: %d\n", p->dither);
+	if (p->rotate)
+		printk(KERN_INFO " rotate: %d\n", p->rotate);
+	if (p->repeat.mode) {
+		printk(KERN_INFO " repeat mode: %d, pad color: 0x%lx\n",
+				p->repeat.mode, p->repeat.pad_color);
+	}
+	if (p->bluscr.mode) {
+		printk(KERN_INFO " bluescreen mode: %d, bs_color: 0x%lx "
+				"bg_color: 0x%lx\n",
+				p->bluscr.mode, p->bluscr.bs_color,
+				p->bluscr.bg_color);
+	}
+	if (p->scaling.mode) {
+		printk(KERN_INFO " scaling mode: %d, s:%d,%d d:%d,%d\n",
+				p->scaling.mode,
+				p->scaling.src_w, p->scaling.src_h,
+				p->scaling.dst_w, p->scaling.dst_h);
+	}
+	if (p->clipping.enable) {
+		printk(KERN_INFO " clipping mode: %d, LT(%d,%d) RB(%d,%d)\n",
+				p->clipping.enable,
+				p->clipping.x1, p->clipping.y1,
+				p->clipping.x2, p->clipping.y2);
+	}
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		c = &cmd->dma[i];
+		r = &img->rect;
+
+		printk(KERN_INFO " %s type: %d addr: 0x%lx\n",
+				imagename(i), img->addr.type,
+				img->addr.start);
+		printk(KERN_INFO " %s width: %d height: %d "
+				"stride: %d order: %d format: %d\n",
+				imagename(i), img->width, img->height,
+				img->stride, img->order, img->fmt);
+		printk(KERN_INFO " %s rect LT(%d,%d) RB(%d,%d) WH(%d,%d)\n",
+				imagename(i), r->x1, r->y1, r->x2, r->y2,
+				rect_w(r), rect_h(r));
+		printk(KERN_INFO " %s dma addr: 0x%lx "
+				"size: 0x%x cached: 0x%x\n",
+				imagename(i), c->addr, c->size, c->cached);
+	}
+
+	if (cmd->dma_all) {
+		printk(KERN_INFO " dma size all: 0x%x bytes\n", cmd->dma_all);
+		printk(KERN_INFO " ctx: %p seq_no(%u) sync(%d)\n",
+				cmd->ctx, cmd->seq_no, cmd->sync);
+	}
+}
diff --git a/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.h b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.h
new file mode 100644
index 0000000..ebe9eae
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x-exynos4/fimg2d_helper.h
@@ -0,0 +1,151 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_HELPER_H
+#define __FIMG2D_HELPER_H
+
+#include <linux/sched.h>
+#include "fimg2d.h"
+
+static inline char *perfname(enum perf_desc id)
+{
+	switch (id) {
+	case PERF_INNERCACHE:
+		return "INNER$";
+	case PERF_OUTERCACHE:
+		return "OUTER$";
+	case PERF_BLIT:
+		return "BITBLT";
+	default:
+		return "";
+	}
+}
+
+static inline char *imagename(enum image_object image)
+{
+	switch (image) {
+	case IDST:
+		return "DST";
+	case ISRC:
+		return "SRC";
+	case IMSK:
+		return "MSK";
+	default:
+		return NULL;
+	}
+}
+
+static inline int is_opaque(enum color_format fmt)
+{
+	switch (fmt) {
+	case CF_ARGB_8888:
+	case CF_ARGB_1555:
+	case CF_ARGB_4444:
+		return 0;
+
+	case CF_XRGB_8888:
+	case CF_XRGB_1555:
+	case CF_XRGB_4444:
+		return 1;
+
+	case CF_RGB_565:
+	case CF_RGB_888:
+		return 1;
+
+	default:
+		break;
+	}
+
+	return 1;
+}
+
+static inline unsigned int rect_w(struct fimg2d_rect *r)
+{
+	return r->x2 - r->x1;
+}
+
+static inline unsigned int rect_h(struct fimg2d_rect *r)
+{
+	return r->y2 - r->y1;
+}
+
+static inline long elapsed_usec(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+#ifdef PERF_TIMEVAL
+	struct timeval *start = &perf->start;
+	struct timeval *end = &perf->end;
+	long sec, usec;
+
+	sec = end->tv_sec - start->tv_sec;
+	if (end->tv_usec >= start->tv_usec) {
+		usec = end->tv_usec - start->tv_usec;
+	} else {
+		usec = end->tv_usec + 1000000 - start->tv_usec;
+		sec--;
+	}
+	return sec * 1000000 + usec;
+#else
+	return (long)(perf->end - perf->start)/1000;
+#endif
+}
+
+static inline void perf_start(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+
+	if (!perf->valid) {
+#ifdef PERF_TIMEVAL
+		struct timeval time;
+		do_gettimeofday(&time);
+		perf->start = time;
+#else
+		long time;
+		perf->start = sched_clock();
+		time = perf->start / 1000;
+#endif
+		perf->valid = 0x01;
+	}
+}
+
+static inline void perf_end(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+
+	if (perf->valid == 0x01) {
+#ifdef PERF_TIMEVAL
+		struct timeval time;
+		do_gettimeofday(&time);
+		perf->end = time;
+#else
+		long time;
+		perf->end = sched_clock();
+		time = perf->end / 1000;
+#endif
+		perf->valid |= 0x10;
+	}
+}
+
+static inline void perf_clear(struct fimg2d_context *ctx)
+{
+	int i;
+	for (i = 0; i < MAX_PERF_DESCS; i++)
+		ctx->perf[i].valid = 0;
+}
+
+int pixel2offset(int pixel, enum color_format cf);
+int width2bytes(int width, enum color_format cf);
+void perf_print(struct fimg2d_context *ctx, int seq_no);
+void fimg2d_print_params(struct fimg2d_blit __user *u);
+void fimg2d_dump_command(struct fimg2d_bltcmd *cmd);
+
+#endif /* __FIMG2D_HELPER_H */
diff --git a/drivers/media/video/samsung/fimg2d4x/Kconfig b/drivers/media/video/samsung/fimg2d4x/Kconfig
new file mode 100644
index 0000000..fc6430c
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/Kconfig
@@ -0,0 +1,23 @@
+# drivers/media/video/samsung/fimg2d4x/Kconfig
+#
+# Copyright (c) 2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+config VIDEO_FIMG2D4X
+	bool "Samsung Graphics 2D Driver"
+	select VIDEO_FIMG2D
+	depends on VIDEO_SAMSUNG && (CPU_EXYNOS4212 || CPU_EXYNOS4412 || CPU_EXYNOS5210 || CPU_EXYNOS5250)
+	default n
+	---help---
+	  This is a graphics 2D (FIMG2D 4.x) driver for Samsung ARM based SoC.
+
+config VIDEO_FIMG2D4X_DEBUG
+	bool "Enables FIMG2D debug messages"
+	select VIDEO_FIMG2D_DEBUG
+	depends on VIDEO_FIMG2D4X
+	default n
+	---help---
+	  This enables FIMG2D driver debug messages.
+
diff --git a/drivers/media/video/samsung/fimg2d4x/Makefile b/drivers/media/video/samsung/fimg2d4x/Makefile
new file mode 100644
index 0000000..40b93a9
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/Makefile
@@ -0,0 +1,18 @@
+# drivers/media/video/samsung/fimg2d4x/Makefile
+#
+# Copyright (c) 2011 Samsung Electronics Co., Ltd.
+#	http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+obj-$(CONFIG_VIDEO_FIMG2D) += fimg2d_drv.o fimg2d_ctx.o fimg2d_cache.o fimg2d_clk.o fimg2d_helper.o
+obj-$(CONFIG_VIDEO_FIMG2D4X) += fimg2d4x_blt.o fimg2d4x_hw.o
+
+ifeq ($(CONFIG_VIDEO_FIMG2D_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d.h b/drivers/media/video/samsung/fimg2d4x/fimg2d.h
new file mode 100644
index 0000000..250dffd
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d.h
@@ -0,0 +1,514 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_H
+#define __FIMG2D_H __FILE__
+
+#ifdef __KERNEL__
+
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/atomic.h>
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+
+#define FIMG2D_MINOR			(240)
+#define to_fimg2d_plat(d)		(to_platform_device(d)->dev.platform_data)
+
+#ifdef CONFIG_VIDEO_FIMG2D_DEBUG
+#define fimg2d_debug(fmt, arg...)	printk(KERN_INFO "[%s] " fmt, __func__, ## arg)
+#else
+#define fimg2d_debug(fmt, arg...)	do { } while (0)
+#endif
+
+#endif /* __KERNEL__ */
+
+/* ioctl commands */
+#define FIMG2D_IOCTL_MAGIC	'F'
+#define FIMG2D_BITBLT_BLIT	_IOWR(FIMG2D_IOCTL_MAGIC, 0, struct fimg2d_blit)
+#define FIMG2D_BITBLT_SYNC	_IOW(FIMG2D_IOCTL_MAGIC, 1, int)
+#define FIMG2D_BITBLT_VERSION	_IOR(FIMG2D_IOCTL_MAGIC, 2, struct fimg2d_version)
+
+struct fimg2d_version {
+	unsigned int hw;
+	unsigned int sw;
+};
+
+/**
+ * @BLIT_SYNC: sync mode, to wait for blit done irq
+ * @BLIT_ASYNC: async mode, not to wait for blit done irq
+ *
+ */
+enum blit_sync {
+	BLIT_SYNC,
+	BLIT_ASYNC,
+};
+
+/**
+ * @ADDR_PHYS: physical address
+ * @ADDR_USER: user virtual address (physically Non-contiguous)
+ * @ADDR_USER_CONTIG: user virtual address (physically Contiguous)
+ * @ADDR_DEVICE: specific device virtual address
+ */
+enum addr_space {
+	ADDR_NONE,
+	ADDR_PHYS,
+	ADDR_KERN,
+	ADDR_USER,
+	ADDR_USER_CONTIG,
+	ADDR_DEVICE,
+};
+
+/**
+ * Pixel order complies with little-endian style
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum pixel_order {
+	AX_RGB = 0,
+	RGB_AX,
+	AX_BGR,
+	BGR_AX,
+	ARGB_ORDER_END,
+
+	P1_CRY1CBY0,
+	P1_CBY1CRY0,
+	P1_Y1CRY0CB,
+	P1_Y1CBY0CR,
+	P1_ORDER_END,
+
+	P2_CRCB,
+	P2_CBCR,
+	P2_ORDER_END,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum color_format {
+	CF_XRGB_8888 = 0,
+	CF_ARGB_8888,
+	CF_RGB_565,
+	CF_XRGB_1555,
+	CF_ARGB_1555,
+	CF_XRGB_4444,
+	CF_ARGB_4444,
+	CF_RGB_888,
+	CF_YCBCR_444,
+	CF_YCBCR_422,
+	CF_YCBCR_420,
+	CF_A8,
+	CF_L8,
+	SRC_DST_FORMAT_END,
+
+	CF_MSK_1BIT,
+	CF_MSK_4BIT,
+	CF_MSK_8BIT,
+	CF_MSK_16BIT_565,
+	CF_MSK_16BIT_1555,
+	CF_MSK_16BIT_4444,
+	CF_MSK_32BIT_8888,
+	MSK_FORMAT_END,
+};
+
+enum rotation {
+	ORIGIN,
+	ROT_90,	/* clockwise */
+	ROT_180,
+	ROT_270,
+	XFLIP,	/* x-axis flip */
+	YFLIP,	/* y-axis flip */
+};
+
+/**
+ * @NO_REPEAT: no effect
+ * @REPEAT_NORMAL: repeat horizontally and vertically
+ * @REPEAT_PAD: pad with pad color
+ * @REPEAT_REFLECT: reflect horizontally and vertically
+ * @REPEAT_CLAMP: pad with edge color of original image
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum repeat {
+	NO_REPEAT = 0,
+	REPEAT_NORMAL,	/* default setting */
+	REPEAT_PAD,
+	REPEAT_REFLECT, REPEAT_MIRROR = REPEAT_REFLECT,
+	REPEAT_CLAMP,
+};
+
+enum scaling {
+	NO_SCALING,
+	SCALING_NEAREST,
+	SCALING_BILINEAR,
+};
+
+/**
+ * @SCALING_PIXELS: ratio in pixels
+ * @SCALING_RATIO: ratio in fixed point 16
+ */
+enum scaling_factor {
+	SCALING_PIXELS,
+	SCALING_RATIO,
+};
+
+/**
+ * premultiplied alpha
+ */
+enum premultiplied {
+	PREMULTIPLIED,
+	NON_PREMULTIPLIED,
+};
+
+/**
+ * @TRANSP: discard bluescreen color
+ * @BLUSCR: replace bluescreen color with background color
+ */
+enum bluescreen {
+	OPAQUE,
+	TRANSP,
+	BLUSCR,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum blit_op {
+	BLIT_OP_SOLID_FILL = 0,
+
+	BLIT_OP_CLR,
+	BLIT_OP_SRC, BLIT_OP_SRC_COPY = BLIT_OP_SRC,
+	BLIT_OP_DST,
+	BLIT_OP_SRC_OVER,
+	BLIT_OP_DST_OVER, BLIT_OP_OVER_REV = BLIT_OP_DST_OVER,
+	BLIT_OP_SRC_IN,
+	BLIT_OP_DST_IN, BLIT_OP_IN_REV = BLIT_OP_DST_IN,
+	BLIT_OP_SRC_OUT,
+	BLIT_OP_DST_OUT, BLIT_OP_OUT_REV = BLIT_OP_DST_OUT,
+	BLIT_OP_SRC_ATOP,
+	BLIT_OP_DST_ATOP, BLIT_OP_ATOP_REV = BLIT_OP_DST_ATOP,
+	BLIT_OP_XOR,
+
+	BLIT_OP_ADD,
+	BLIT_OP_MULTIPLY,
+	BLIT_OP_SCREEN,
+	BLIT_OP_DARKEN,
+	BLIT_OP_LIGHTEN,
+
+	BLIT_OP_DISJ_SRC_OVER,
+	BLIT_OP_DISJ_DST_OVER, BLIT_OP_SATURATE = BLIT_OP_DISJ_DST_OVER,
+	BLIT_OP_DISJ_SRC_IN,
+	BLIT_OP_DISJ_DST_IN, BLIT_OP_DISJ_IN_REV = BLIT_OP_DISJ_DST_IN,
+	BLIT_OP_DISJ_SRC_OUT,
+	BLIT_OP_DISJ_DST_OUT, BLIT_OP_DISJ_OUT_REV = BLIT_OP_DISJ_DST_OUT,
+	BLIT_OP_DISJ_SRC_ATOP,
+	BLIT_OP_DISJ_DST_ATOP, BLIT_OP_DISJ_ATOP_REV = BLIT_OP_DISJ_DST_ATOP,
+	BLIT_OP_DISJ_XOR,
+
+	BLIT_OP_CONJ_SRC_OVER,
+	BLIT_OP_CONJ_DST_OVER, BLIT_OP_CONJ_OVER_REV = BLIT_OP_CONJ_DST_OVER,
+	BLIT_OP_CONJ_SRC_IN,
+	BLIT_OP_CONJ_DST_IN, BLIT_OP_CONJ_IN_REV = BLIT_OP_CONJ_DST_IN,
+	BLIT_OP_CONJ_SRC_OUT,
+	BLIT_OP_CONJ_DST_OUT, BLIT_OP_CONJ_OUT_REV = BLIT_OP_CONJ_DST_OUT,
+	BLIT_OP_CONJ_SRC_ATOP,
+	BLIT_OP_CONJ_DST_ATOP, BLIT_OP_CONJ_ATOP_REV = BLIT_OP_CONJ_DST_ATOP,
+	BLIT_OP_CONJ_XOR,
+
+	/* user select coefficient manually */
+	BLIT_OP_USER_COEFF,
+
+	BLIT_OP_USER_SRC_GA,
+
+	/* Add new operation type here */
+
+	/* end of blit operation */
+	BLIT_OP_END,
+};
+#define MAX_FIMG2D_BLIT_OP (int)BLIT_OP_END
+
+#ifdef __KERNEL__
+
+/**
+ * @TMP: temporary buffer for 2-step blit at a single command
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum image_object {
+	IMAGE_SRC = 0,
+	IMAGE_MSK,
+	IMAGE_TMP,
+	IMAGE_DST,
+	IMAGE_END,
+};
+#define MAX_IMAGES		IMAGE_END
+#define ISRC			IMAGE_SRC
+#define IMSK			IMAGE_MSK
+#define ITMP			IMAGE_TMP
+#define IDST			IMAGE_DST
+#define image_table(u)		\
+	{			\
+		(u)->src,	\
+		(u)->msk,	\
+		(u)->tmp,	\
+		(u)->dst	\
+	}
+
+/**
+ * @size: dma size of image
+ * @cached: cached dma size of image
+ */
+struct fimg2d_dma {
+	unsigned long addr;
+	size_t size;
+	size_t cached;
+};
+
+struct fimg2d_dma_group {
+	struct fimg2d_dma base;
+	struct fimg2d_dma plane2;
+};
+
+#endif /* __KERNEL__ */
+
+/**
+ * @start: start address or unique id of image
+ */
+struct fimg2d_addr {
+	enum addr_space type;
+	unsigned long start;
+};
+
+struct fimg2d_rect {
+	int x1;
+	int y1;
+	int x2;	/* x1 + width */
+	int y2; /* y1 + height */
+};
+
+/**
+ * pixels can be different from src, dst or clip rect
+ */
+struct fimg2d_scale {
+	enum scaling mode;
+
+	/* ratio in pixels */
+	int src_w, src_h;
+	int dst_w, dst_h;
+};
+
+struct fimg2d_clip {
+	bool enable;
+	int x1;
+	int y1;
+	int x2;	/* x1 + width */
+	int y2; /* y1 + height */
+};
+
+struct fimg2d_repeat {
+	enum repeat mode;
+	unsigned long pad_color;
+};
+
+/**
+ * @bg_color: bg_color is valid only if bluescreen mode is BLUSCR.
+ */
+struct fimg2d_bluscr {
+	enum bluescreen mode;
+	unsigned long bs_color;
+	unsigned long bg_color;
+};
+
+/**
+ * @plane2: address info for CbCr in YCbCr 2plane mode
+ * @rect: crop/clip rect
+ * @need_cacheopr: true if cache coherency is required
+ */
+struct fimg2d_image {
+	int width;
+	int height;
+	int stride;
+	enum pixel_order order;
+	enum color_format fmt;
+	struct fimg2d_addr addr;
+	struct fimg2d_addr plane2;
+	struct fimg2d_rect rect;
+	bool need_cacheopr;
+};
+
+/**
+ * @solid_color:
+ *         src color instead of src image
+ *         color format and order must be ARGB8888(A is MSB).
+ * @g_alpha: global(constant) alpha. 0xff is opaque, 0 is transparnet
+ * @dither: dithering
+ * @rotate: rotation degree in clockwise
+ * @premult: alpha premultiplied mode for read & write
+ * @scaling: common scaling info for src and mask image.
+ * @repeat: repeat type (tile mode)
+ * @bluscr: blue screen and transparent mode
+ * @clipping: clipping rect within dst rect
+ */
+struct fimg2d_param {
+	unsigned long solid_color;
+	unsigned char g_alpha;
+	bool dither;
+	enum rotation rotate;
+	enum premultiplied premult;
+	struct fimg2d_scale scaling;
+	struct fimg2d_repeat repeat;
+	struct fimg2d_bluscr bluscr;
+	struct fimg2d_clip clipping;
+};
+
+/**
+ * @op: blit operation mode
+ * @src: set when using src image
+ * @msk: set when using mask image
+ * @tmp: set when using 2-step blit at a single command
+ * @dst: dst must not be null
+ *         * tmp image must be the same to dst except memory address
+ * @seq_no: user debugging info.
+ *          for example, user can set sequence number or pid.
+ */
+struct fimg2d_blit {
+	enum blit_op op;
+	struct fimg2d_param param;
+	struct fimg2d_image *src;
+	struct fimg2d_image *msk;
+	struct fimg2d_image *tmp;
+	struct fimg2d_image *dst;
+	enum blit_sync sync;
+	unsigned int seq_no;
+};
+
+#ifdef __KERNEL__
+
+/**
+ * Enables definition to estimate performance.
+ * These debug codes includes printk, so perf
+ * data are unreliable under multi instance environment
+ */
+#undef PERF_PROFILE
+#define PERF_TIMEVAL
+
+enum perf_desc {
+	PERF_INNERCACHE,
+	PERF_OUTERCACHE,
+	PERF_BLIT,
+	PERF_END
+};
+#define MAX_PERF_DESCS		PERF_END
+
+struct fimg2d_perf {
+	int valid;
+#ifdef PERF_TIMEVAL
+	struct timeval start;
+	struct timeval end;
+#else
+	unsigned long long start;
+	unsigned long long end;
+#endif
+};
+
+/**
+ * @pgd: base address of arm mmu pagetable
+ * @ncmd: request count in blit command queue
+ * @wait_q: conext wait queue head
+*/
+struct fimg2d_context {
+	struct mm_struct *mm;
+	atomic_t ncmd;
+	wait_queue_head_t wait_q;
+	struct fimg2d_perf perf[MAX_PERF_DESCS];
+};
+
+/**
+ * @op: blit operation mode
+ * @sync: sync/async blit mode (currently support sync mode only)
+ * @image: array of image object.
+ *         [0] is for src image
+ *         [1] is for mask image
+ *         [2] is for temporary buffer
+ *             set when using 2-step blit at a single command
+ *         [3] is for dst, dst must not be null
+ *         * tmp image must be the same to dst except memory address
+ * @seq_no: user debugging info.
+ *          for example, user can set sequence number or pid.
+ * @dma_all: total dma size of src, msk, dst
+ * @dma: array of dma info for each src, msk, tmp and dst
+ * @ctx: context is created when user open fimg2d device.
+ * @node: list head of blit command queue
+ */
+struct fimg2d_bltcmd {
+	enum blit_op op;
+	enum blit_sync sync;
+	unsigned int seq_no;
+	size_t dma_all;
+	struct fimg2d_param param;
+	struct fimg2d_image image[MAX_IMAGES];
+	struct fimg2d_dma_group dma[MAX_IMAGES];
+	struct fimg2d_context *ctx;
+	struct list_head node;
+};
+
+/**
+ * @suspended: in suspend mode
+ * @clkon: power status for runtime pm
+ * @mem: resource platform device
+ * @regs: base address of hardware
+ * @dev: pointer to device struct
+ * @err: true if hardware is timed out while blitting
+ * @irq: irq number
+ * @nctx: context count
+ * @busy: 1 if hardware is running
+ * @bltlock: spinlock for blit
+ * @wait_q: blit wait queue head
+ * @cmd_q: blit command queue
+ * @workqueue: workqueue_struct for kfimg2dd
+*/
+struct fimg2d_control {
+	atomic_t suspended;
+	atomic_t clkon;
+	struct clk *clock;
+	struct device *dev;
+	struct device *bus_dev;
+	struct resource *mem;
+	void __iomem *regs;
+
+	bool err;
+	int irq;
+	atomic_t nctx;
+	atomic_t busy;
+	atomic_t active;
+	spinlock_t bltlock;
+	wait_queue_head_t wait_q;
+	struct list_head cmd_q;
+	struct workqueue_struct *work_q;
+
+	void (*blit)(struct fimg2d_control *info);
+	int (*configure)(struct fimg2d_control *info,
+			struct fimg2d_bltcmd *cmd);
+	void (*run)(struct fimg2d_control *info);
+	void (*stop)(struct fimg2d_control *info);
+	void (*dump)(struct fimg2d_control *info);
+	void (*finalize)(struct fimg2d_control *info);
+};
+
+int fimg2d_register_ops(struct fimg2d_control *info);
+
+#endif /* __KERNEL__ */
+
+#endif /* __FIMG2D_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d4x.h b/drivers/media/video/samsung/fimg2d4x/fimg2d4x.h
new file mode 100644
index 0000000..0b9128f
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d4x.h
@@ -0,0 +1,225 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D4X_H
+#define __FIMG2D4X_H __FILE__
+
+#include "fimg2d4x_regs.h"
+
+/**
+ * @IMG_MEMORY: read from external memory
+ * @IMG_FGCOLOR: read from foreground color
+ * @IMG_BGCOLOR: read from background color
+ */
+enum image_sel {
+	IMG_MEMORY,
+	IMG_FGCOLOR,
+	IMG_BGCOLOR,
+};
+
+/**
+ * @FORWARD_ADDRESSING: read data in forward direction
+ * @REVERSE_ADDRESSING: read data in reverse direction
+ */
+enum addressing {
+	FORWARD_ADDRESSING,
+	REVERSE_ADDRESSING,
+};
+
+/**
+ * The other addressing modes can cause data corruption,
+ * if src and dst are overlapped.
+ */
+enum dir_addressing {
+	UP_FORWARD,
+	DOWN_REVERSE,
+	LEFT_FORWARD,
+	RIGHT_REVERSE,
+	VALID_ADDRESSING_END,
+};
+
+/**
+ * DO NOT CHANGE THIS ORDER
+ */
+enum max_burst_len {
+	MAX_BURST_2 = 0,
+	MAX_BURST_4,
+	MAX_BURST_8,	/* initial value */
+	MAX_BURST_16,
+};
+
+#define DEFAULT_MAX_BURST_LEN		MAX_BURST_8
+
+/**
+ * mask operation type for 16-bpp, 32-bpp mask image
+ * @MSK_ALPHA: use mask alpha for src argb
+ * @MSK_ARGB: use mask argb for src argb
+ * @MSK_MIXED: use mask alpha for src alpha and mask rgb for src rgb
+ */
+enum mask_opr {
+	MSK_ALPHA,	/* initial value */
+	MSK_ARGB,
+	MSK_MIXED,
+};
+
+#define DEFAULT_MSK_OPR		MSK_ALPHA
+
+/**
+ * @ALPHA_PERPIXEL: perpixel alpha
+ * @ALPHA_PERPIXEL_SUM_GLOBAL: perpixel + global
+ * @ALPHA_PERPIXEL_MUL_GLOBAL: perpixel x global
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum alpha_opr {
+	ALPHA_PERPIXEL = 0,	/* initial value */
+	ALPHA_PERPIXEL_SUM_GLOBAL,
+	ALPHA_PERPIXEL_MUL_GLOBAL,
+};
+
+#define DEFAULT_ALPHA_OPR	ALPHA_PERPIXEL
+
+/**
+ * sampling policy at boundary for bilinear scaling
+ * @FOLLOW_REPEAT_MODE: sampling 1 or 2 pixels within bounds
+ * @IGNORE_REPEAT_MODE: sampling 4 pixels according to repeat mode
+ */
+enum boundary_sampling_policy {
+	FOLLOW_REPEAT_MODE,
+	IGNORE_REPEAT_MODE,
+};
+
+#define DEFAULT_BOUNDARY_SAMPLING	FOLLOW_REPEAT_MODE
+
+/**
+ * @COEFF_ONE: 1
+ * @COEFF_ZERO: 0
+ * @COEFF_SA: src alpha
+ * @COEFF_SC: src color
+ * @COEFF_DA: dst alpha
+ * @COEFF_DC: dst color
+ * @COEFF_GA: global(constant) alpha
+ * @COEFF_GC: global(constant) color
+ * @COEFF_DISJ_S:
+ * @COEFF_DISJ_D:
+ * @COEFF_CONJ_S:
+ * @COEFF_CONJ_D:
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum fimg2d_coeff {
+	COEFF_ONE = 0,
+	COEFF_ZERO,
+	COEFF_SA,
+	COEFF_SC,
+	COEFF_DA,
+	COEFF_DC,
+	COEFF_GA,
+	COEFF_GC,
+	COEFF_DISJ_S,
+	COEFF_DISJ_D,
+	COEFF_CONJ_S,
+	COEFF_CONJ_D,
+};
+
+/**
+ * @PREMULT_ROUND_0: (A*B) >> 8
+ * @PREMULT_ROUND_1: (A+1)*B) >> 8
+ * @PREMULT_ROUND_2: (A+(A>>7))* B) >> 8
+ * @PREMULT_ROUND_3: TMP= A*8 + 0x80, (TMP + (TMP >> 8)) >> 8
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum premult_round {
+	PREMULT_ROUND_0 = 0,
+	PREMULT_ROUND_1,
+	PREMULT_ROUND_2,
+	PREMULT_ROUND_3,	/* initial value */
+};
+
+#define DEFAULT_PREMULT_ROUND_MODE	PREMULT_ROUND_3
+
+/**
+ * @BLEND_ROUND_0: (A+1)*B) >> 8
+ * @BLEND_ROUND_1: (A+(A>>7))* B) >> 8
+ * @BLEND_ROUND_2: TMP= A*8 + 0x80, (TMP + (TMP >> 8)) >> 8
+ * @BLEND_ROUND_3: TMP= (A*B + C*D + 0x80), (TMP + (TMP >> 8)) >> 8
+ *
+ * DO NOT CHANGE THIS ORDER
+ */
+enum blend_round {
+	BLEND_ROUND_0 = 0,
+	BLEND_ROUND_1,
+	BLEND_ROUND_2,
+	BLEND_ROUND_3,	/* initial value */
+};
+
+#define DEFAULT_BLEND_ROUND_MODE	BLEND_ROUND_3
+
+struct fimg2d_blend_coeff {
+	bool s_coeff_inv;
+	enum fimg2d_coeff s_coeff;
+	bool d_coeff_inv;
+	enum fimg2d_coeff d_coeff;
+};
+
+void fimg2d4x_reset(struct fimg2d_control *info);
+void fimg2d4x_enable_irq(struct fimg2d_control *info);
+void fimg2d4x_disable_irq(struct fimg2d_control *info);
+void fimg2d4x_clear_irq(struct fimg2d_control *info);
+int fimg2d4x_is_blit_done(struct fimg2d_control *info);
+int fimg2d4x_blit_done_status(struct fimg2d_control *info);
+void fimg2d4x_start_blit(struct fimg2d_control *info);
+void fimg2d4x_set_max_burst_length(struct fimg2d_control *info,
+				enum max_burst_len len);
+void fimg2d4x_set_src_type(struct fimg2d_control *info, enum image_sel type);
+void fimg2d4x_set_src_image(struct fimg2d_control *info,
+				struct fimg2d_image *s);
+void fimg2d4x_set_src_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_set_dst_type(struct fimg2d_control *info, enum image_sel type);
+void fimg2d4x_set_dst_image(struct fimg2d_control *info,
+				struct fimg2d_image *d);
+void fimg2d4x_set_dst_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_enable_msk(struct fimg2d_control *info);
+void fimg2d4x_set_msk_image(struct fimg2d_control *info,
+				struct fimg2d_image *m);
+void fimg2d4x_set_msk_rect(struct fimg2d_control *info, struct fimg2d_rect *r);
+void fimg2d4x_set_color_fill(struct fimg2d_control *info, unsigned long color);
+void fimg2d4x_set_premultiplied(struct fimg2d_control *info);
+void fimg2d4x_src_premultiply(struct fimg2d_control *info);
+void fimg2d4x_dst_premultiply(struct fimg2d_control *info);
+void fimg2d4x_dst_depremultiply(struct fimg2d_control *info);
+void fimg2d4x_enable_transparent(struct fimg2d_control *info);
+void fimg2d4x_set_bluescreen(struct fimg2d_control *info,
+			     struct fimg2d_bluscr *bluscr);
+void fimg2d4x_enable_clipping(struct fimg2d_control *info,
+			      struct fimg2d_clip *clp);
+void fimg2d4x_enable_dithering(struct fimg2d_control *info);
+void fimg2d4x_set_src_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_msk_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_src_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_msk_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep);
+void fimg2d4x_set_rotation(struct fimg2d_control *info, enum rotation rot);
+void fimg2d4x_set_fgcolor(struct fimg2d_control *info, unsigned long fg);
+void fimg2d4x_set_bgcolor(struct fimg2d_control *info, unsigned long bg);
+void fimg2d4x_enable_alpha(struct fimg2d_control *info, unsigned char g_alpha);
+void fimg2d4x_set_alpha_composite(struct fimg2d_control *info,
+		enum blit_op op, unsigned char g_alpha);
+void fimg2d4x_dump_regs(struct fimg2d_control *info);
+
+#endif /* __FIMG2D4X_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d4x_blt.c b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_blt.c
new file mode 100644
index 0000000..97ea4c1
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_blt.c
@@ -0,0 +1,334 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_blt.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <linux/atomic.h>
+#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+#include <plat/sysmmu.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <plat/devs.h>
+#include <linux/pm_runtime.h>
+#endif
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+#include "fimg2d4x.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+#define BLIT_TIMEOUT	msecs_to_jiffies(500)
+
+static inline void fimg2d4x_blit_wait(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd)
+{
+	if (!wait_event_timeout(info->wait_q, !atomic_read(&info->busy), BLIT_TIMEOUT)) {
+		printk(KERN_ERR "[%s] blit wait timeout\n", __func__);
+		fimg2d_dump_command(cmd);
+
+		if (!fimg2d4x_blit_done_status(info))
+			info->err = true; /* device error */
+	}
+}
+
+static void fimg2d4x_pre_bitblt(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd)
+{
+	/* TODO */
+}
+
+void fimg2d4x_bitblt(struct fimg2d_control *info)
+{
+	struct fimg2d_context *ctx;
+	struct fimg2d_bltcmd *cmd;
+	unsigned long *pgd;
+	int ret;
+
+	fimg2d_debug("enter blitter\n");
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_get_sync(info->dev);
+	fimg2d_debug("pm_runtime_get_sync\n");
+#endif
+	fimg2d_clk_on(info);
+
+	while ((cmd = fimg2d_get_first_command(info))) {
+		ctx = cmd->ctx;
+		if (info->err) {
+			printk(KERN_ERR "[%s] device error\n", __func__);
+			goto blitend;
+		}
+
+		atomic_set(&info->busy, 1);
+
+		ret = info->configure(info, cmd);
+		if (ret)
+			goto blitend;
+
+		if (cmd->image[IDST].addr.type != ADDR_PHYS) {
+			pgd = (unsigned long *)ctx->mm->pgd;
+			exynos_sysmmu_enable(info->dev,
+					(unsigned long)virt_to_phys(pgd));
+			fimg2d_debug("sysmmu enable: pgd %p ctx %p seq_no(%u)\n",
+					pgd, ctx, cmd->seq_no);
+		}
+
+		fimg2d4x_pre_bitblt(info, cmd);
+
+#ifdef PERF_PROFILE
+		perf_start(cmd->ctx, PERF_BLIT);
+#endif
+		/* start blit */
+		info->run(info);
+		fimg2d4x_blit_wait(info, cmd);
+
+#ifdef PERF_PROFILE
+		perf_end(cmd->ctx, PERF_BLIT);
+#endif
+		if (cmd->image[IDST].addr.type != ADDR_PHYS) {
+			exynos_sysmmu_disable(info->dev);
+			fimg2d_debug("sysmmu disable\n");
+		}
+blitend:
+		fimg2d_del_command(info, cmd);
+
+		/* wake up context */
+		if (!atomic_read(&ctx->ncmd))
+			wake_up(&ctx->wait_q);
+	}
+
+	atomic_set(&info->active, 0);
+
+	fimg2d_clk_off(info);
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_put_sync(info->dev);
+	fimg2d_debug("pm_runtime_put_sync\n");
+#endif
+
+	fimg2d_debug("exit blitter\n");
+}
+
+static inline int is_opaque(enum color_format fmt)
+{
+	switch (fmt) {
+	case CF_ARGB_8888:
+	case CF_ARGB_1555:
+	case CF_ARGB_4444:
+		return 0;
+
+	default:
+		return 1;
+	}
+}
+
+static int fast_op(struct fimg2d_bltcmd *cmd)
+{
+	int sa, da, ga;
+	int fop = cmd->op;
+	struct fimg2d_image *src, *msk, *dst;
+	struct fimg2d_param *p = &cmd->param;
+
+	src = &cmd->image[ISRC];
+	msk = &cmd->image[IMSK];
+	dst = &cmd->image[IDST];
+
+	if (msk->addr.type)
+		return fop;
+
+	ga = p->g_alpha;
+	da = is_opaque(dst->fmt) ? 0xff : 0;
+
+	if (!src->addr.type)
+		sa = (p->solid_color >> 24) & 0xff;
+	else
+		sa = is_opaque(src->fmt) ? 0xff : 0;
+
+	switch (cmd->op) {
+	case BLIT_OP_SRC_OVER:
+		/* Sc + (1-Sa)*Dc = Sc */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_OVER:
+		/* (1-Da)*Sc + Dc = Dc */
+		if (da == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	case BLIT_OP_SRC_IN:
+		/* Da*Sc = Sc */
+		if (da == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_IN:
+		/* Sa*Dc = Dc */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	case BLIT_OP_SRC_OUT:
+		/* (1-Da)*Sc = 0 */
+		if (da == 0xff)
+			fop = BLIT_OP_CLR;
+		break;
+	case BLIT_OP_DST_OUT:
+		/* (1-Sa)*Dc = 0 */
+		if (sa == 0xff && ga == 0xff)
+			fop = BLIT_OP_CLR;
+		break;
+	case BLIT_OP_SRC_ATOP:
+		/* Da*Sc + (1-Sa)*Dc = Sc */
+		if (sa == 0xff && da == 0xff && ga == 0xff)
+			fop = BLIT_OP_SRC;
+		break;
+	case BLIT_OP_DST_ATOP:
+		/* (1-Da)*Sc + Sa*Dc = Dc */
+		if (sa == 0xff && da == 0xff && ga == 0xff)
+			fop = BLIT_OP_DST;	/* nop */
+		break;
+	default:
+		break;
+	}
+
+	if (fop == BLIT_OP_SRC && !src->addr.type && ga == 0xff)
+		fop = BLIT_OP_SOLID_FILL;
+
+	return fop;
+}
+
+static int fimg2d4x_configure(struct fimg2d_control *info,
+				struct fimg2d_bltcmd *cmd)
+{
+	int op;
+	enum image_sel srcsel, dstsel;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *src, *msk, *dst;
+
+	fimg2d_debug("ctx %p seq_no(%u)\n", cmd->ctx, cmd->seq_no);
+
+	src = &cmd->image[ISRC];
+	msk = &cmd->image[IMSK];
+	dst = &cmd->image[IDST];
+
+	/* TODO: batch blit */
+	fimg2d4x_reset(info);
+
+	/* src and dst select */
+	srcsel = dstsel = IMG_MEMORY;
+
+	op = fast_op(cmd);
+
+	switch (op) {
+	case BLIT_OP_SOLID_FILL:
+		srcsel = dstsel = IMG_FGCOLOR;
+		fimg2d4x_set_fgcolor(info, p->solid_color);
+		break;
+	case BLIT_OP_CLR:
+		srcsel = dstsel = IMG_FGCOLOR;
+		fimg2d4x_set_color_fill(info, 0);
+		break;
+	case BLIT_OP_DST:
+		return -1;	/* nop */
+	default:
+		if (!src->addr.type) {
+			srcsel = IMG_FGCOLOR;
+			fimg2d4x_set_fgcolor(info, p->solid_color);
+		}
+
+		if (op == BLIT_OP_SRC)
+			dstsel = IMG_FGCOLOR;
+
+		fimg2d4x_enable_alpha(info, p->g_alpha);
+		fimg2d4x_set_alpha_composite(info, op, p->g_alpha);
+		if (p->premult == NON_PREMULTIPLIED)
+			fimg2d4x_set_premultiplied(info);
+		break;
+	}
+
+	fimg2d4x_set_src_type(info, srcsel);
+	fimg2d4x_set_dst_type(info, dstsel);
+
+	/* src */
+	if (src->addr.type) {
+		fimg2d4x_set_src_image(info, src);
+		fimg2d4x_set_src_rect(info, &src->rect);
+		fimg2d4x_set_src_repeat(info, &p->repeat);
+		if (p->scaling.mode)
+			fimg2d4x_set_src_scaling(info, &p->scaling, &p->repeat);
+	}
+
+	/* msk */
+	if (msk->addr.type) {
+		fimg2d4x_enable_msk(info);
+		fimg2d4x_set_msk_image(info, msk);
+		fimg2d4x_set_msk_rect(info, &msk->rect);
+		fimg2d4x_set_msk_repeat(info, &p->repeat);
+		if (p->scaling.mode)
+			fimg2d4x_set_msk_scaling(info, &p->scaling, &p->repeat);
+	}
+
+	/* dst */
+	if (dst->addr.type) {
+		fimg2d4x_set_dst_image(info, dst);
+		fimg2d4x_set_dst_rect(info, &dst->rect);
+		if (p->clipping.enable)
+			fimg2d4x_enable_clipping(info, &p->clipping);
+	}
+
+	/* bluescreen */
+	if (p->bluscr.mode)
+		fimg2d4x_set_bluescreen(info, &p->bluscr);
+
+	/* rotation */
+	if (p->rotate)
+		fimg2d4x_set_rotation(info, p->rotate);
+
+	/* dithering */
+	if (p->dither)
+		fimg2d4x_enable_dithering(info);
+
+	return 0;
+}
+
+static void fimg2d4x_run(struct fimg2d_control *info)
+{
+	fimg2d_debug("start blit\n");
+	fimg2d4x_enable_irq(info);
+	fimg2d4x_clear_irq(info);
+	fimg2d4x_start_blit(info);
+}
+
+static void fimg2d4x_stop(struct fimg2d_control *info)
+{
+	if (fimg2d4x_is_blit_done(info)) {
+		fimg2d_debug("blit done\n");
+		fimg2d4x_disable_irq(info);
+		fimg2d4x_clear_irq(info);
+		atomic_set(&info->busy, 0);
+		wake_up(&info->wait_q);
+	}
+}
+
+static void fimg2d4x_dump(struct fimg2d_control *info)
+{
+	fimg2d4x_dump_regs(info);
+}
+
+int fimg2d_register_ops(struct fimg2d_control *info)
+{
+	info->blit = fimg2d4x_bitblt;
+	info->configure = fimg2d4x_configure;
+	info->run = fimg2d4x_run;
+	info->dump = fimg2d4x_dump;
+	info->stop = fimg2d4x_stop;
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d4x_hw.c b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_hw.c
new file mode 100644
index 0000000..155c67b
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_hw.c
@@ -0,0 +1,839 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_hw.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/sched.h>
+
+#include "fimg2d.h"
+#include "fimg2d4x.h"
+#include "fimg2d_clk.h"
+
+#define wr(d, a)	writel((d), info->regs + (a))
+#define rd(a)		readl(info->regs + (a))
+
+#undef SOFT_RESET_ENABLED
+#undef FIMG2D_RESET_WA
+
+static const int a8_rgbcolor		= (int)0x0;
+static const int msk_oprmode		= (int)MSK_ARGB;
+static const int premult_round_mode	= (int)PREMULT_ROUND_1;	/* (A+1)*B) >> 8 */
+static const int blend_round_mode	= (int)BLEND_ROUND_0;	/* (A+1)*B) >> 8 */
+
+void fimg2d4x_reset(struct fimg2d_control *info)
+{
+#ifdef SOFT_RESET_ENABLED
+#ifdef FIMG2D_RESET_WA
+	fimg2d_clk_save(info);
+#endif
+	wr(FIMG2D_SOFT_RESET, FIMG2D_SOFT_RESET_REG);
+#ifdef FIMG2D_RESET_WA
+	fimg2d_clk_restore(info);
+#endif
+#else
+	wr(FIMG2D_SFR_CLEAR, FIMG2D_SOFT_RESET_REG);
+#endif
+	/* turn off wince option */
+	wr(0x0, FIMG2D_BLEND_FUNCTION_REG);
+
+	/* set default repeat mode to reflect(mirror) */
+	wr(FIMG2D_SRC_REPEAT_REFLECT, FIMG2D_SRC_REPEAT_MODE_REG);
+	wr(FIMG2D_MSK_REPEAT_REFLECT, FIMG2D_MSK_REPEAT_MODE_REG);
+}
+
+void fimg2d4x_enable_irq(struct fimg2d_control *info)
+{
+	wr(FIMG2D_BLIT_INT_ENABLE, FIMG2D_INTEN_REG);
+}
+
+void fimg2d4x_disable_irq(struct fimg2d_control *info)
+{
+	wr(0, FIMG2D_INTEN_REG);
+}
+
+void fimg2d4x_clear_irq(struct fimg2d_control *info)
+{
+	wr(FIMG2D_BLIT_INT_FLAG, FIMG2D_INTC_PEND_REG);
+}
+
+int fimg2d4x_is_blit_done(struct fimg2d_control *info)
+{
+	return rd(FIMG2D_INTC_PEND_REG) & FIMG2D_BLIT_INT_FLAG;
+}
+
+int fimg2d4x_blit_done_status(struct fimg2d_control *info)
+{
+	volatile unsigned long sts;
+
+	/* read twice */
+	sts = rd(FIMG2D_FIFO_STAT_REG);
+	sts = rd(FIMG2D_FIFO_STAT_REG);
+
+	return (int)(sts & FIMG2D_BLIT_FINISHED);
+}
+
+void fimg2d4x_start_blit(struct fimg2d_control *info)
+{
+	wr(FIMG2D_START_BITBLT, FIMG2D_BITBLT_START_REG);
+}
+
+void fimg2d4x_set_max_burst_length(struct fimg2d_control *info, enum max_burst_len len)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_AXI_MODE_REG);
+
+	cfg &= ~FIMG2D_MAX_BURST_LEN_MASK;
+	cfg |= len << FIMG2D_MAX_BURST_LEN_SHIFT;
+}
+
+void fimg2d4x_set_src_type(struct fimg2d_control *info, enum image_sel type)
+{
+	unsigned long cfg;
+
+	if (type == IMG_MEMORY)
+		cfg = FIMG2D_IMAGE_TYPE_MEMORY;
+	else if (type == IMG_FGCOLOR)
+		cfg = FIMG2D_IMAGE_TYPE_FGCOLOR;
+	else
+		cfg = FIMG2D_IMAGE_TYPE_BGCOLOR;
+
+	wr(cfg, FIMG2D_SRC_SELECT_REG);
+}
+
+void fimg2d4x_set_src_image(struct fimg2d_control *info, struct fimg2d_image *s)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(s->addr.start), FIMG2D_SRC_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(s->stride), FIMG2D_SRC_STRIDE_REG);
+
+	if (s->order < ARGB_ORDER_END) {	/* argb */
+		cfg = s->order << FIMG2D_RGB_ORDER_SHIFT;
+		if (s->fmt == CF_A8)
+			wr(a8_rgbcolor, FIMG2D_SRC_A8_RGB_EXT_REG);
+	} else if (s->order < P1_ORDER_END) {	/* YCbC1 1plane */
+		cfg = (s->order - P1_CRY1CBY0) << FIMG2D_YCBCR_ORDER_SHIFT;
+	} else {	/* YCbCr 2plane */
+		cfg = (s->order - P2_CRCB) << FIMG2D_YCBCR_ORDER_SHIFT;
+		cfg |= FIMG2D_YCBCR_2PLANE;
+
+		wr(FIMG2D_ADDR(s->plane2.start),
+				FIMG2D_SRC_PLANE2_BASE_ADDR_REG);
+	}
+
+	cfg |= s->fmt << FIMG2D_COLOR_FORMAT_SHIFT;
+
+	wr(cfg, FIMG2D_SRC_COLOR_MODE_REG);
+}
+
+void fimg2d4x_set_src_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_SRC_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_SRC_RIGHT_BOTTOM_REG);
+}
+
+void fimg2d4x_set_dst_type(struct fimg2d_control *info, enum image_sel type)
+{
+	unsigned long cfg;
+
+	if (type == IMG_MEMORY)
+		cfg = FIMG2D_IMAGE_TYPE_MEMORY;
+	else if (type == IMG_FGCOLOR)
+		cfg = FIMG2D_IMAGE_TYPE_FGCOLOR;
+	else
+		cfg = FIMG2D_IMAGE_TYPE_BGCOLOR;
+
+	wr(cfg, FIMG2D_DST_SELECT_REG);
+}
+
+/**
+ * @d: set base address, stride, color format, order
+ */
+void fimg2d4x_set_dst_image(struct fimg2d_control *info, struct fimg2d_image *d)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(d->addr.start), FIMG2D_DST_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(d->stride), FIMG2D_DST_STRIDE_REG);
+
+	if (d->order < ARGB_ORDER_END) {
+		cfg = d->order << FIMG2D_RGB_ORDER_SHIFT;
+		if (d->fmt == CF_A8)
+			wr(a8_rgbcolor, FIMG2D_DST_A8_RGB_EXT_REG);
+	} else if (d->order < P1_ORDER_END) {
+		cfg = (d->order - P1_CRY1CBY0) << FIMG2D_YCBCR_ORDER_SHIFT;
+	} else {
+		cfg = (d->order - P2_CRCB) << FIMG2D_YCBCR_ORDER_SHIFT;
+		cfg |= FIMG2D_YCBCR_2PLANE;
+
+		wr(FIMG2D_ADDR(d->plane2.start),
+				FIMG2D_DST_PLANE2_BASE_ADDR_REG);
+	}
+
+	cfg |= d->fmt << FIMG2D_COLOR_FORMAT_SHIFT;
+
+	wr(cfg, FIMG2D_DST_COLOR_MODE_REG);
+}
+
+void fimg2d4x_set_dst_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_DST_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_DST_RIGHT_BOTTOM_REG);
+}
+
+void fimg2d4x_enable_msk(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_NORMAL_MSK;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_set_msk_image(struct fimg2d_control *info, struct fimg2d_image *m)
+{
+	unsigned long cfg;
+
+	wr(FIMG2D_ADDR(m->addr.start), FIMG2D_MSK_BASE_ADDR_REG);
+	wr(FIMG2D_STRIDE(m->stride), FIMG2D_MSK_STRIDE_REG);
+
+	cfg = m->order << FIMG2D_MSK_ORDER_SHIFT;
+	cfg |= (m->fmt - CF_MSK_1BIT) << FIMG2D_MSK_FORMAT_SHIFT;
+
+	/* 16, 32bit mask only */
+	if (m->fmt >= CF_MSK_16BIT_565) {
+		if (msk_oprmode == MSK_ALPHA)
+			cfg |= FIMG2D_MSK_TYPE_ALPHA;
+		else if (msk_oprmode == MSK_ARGB)
+			cfg |= FIMG2D_MSK_TYPE_ARGB;
+		else
+			cfg |= FIMG2D_MSK_TYPE_MIXED;
+	}
+
+	wr(cfg, FIMG2D_MSK_MODE_REG);
+}
+
+void fimg2d4x_set_msk_rect(struct fimg2d_control *info, struct fimg2d_rect *r)
+{
+	wr(FIMG2D_OFFSET(r->x1, r->y1), FIMG2D_MSK_LEFT_TOP_REG);
+	wr(FIMG2D_OFFSET(r->x2, r->y2), FIMG2D_MSK_RIGHT_BOTTOM_REG);
+}
+
+/**
+ * If solid color fill is enabled, other blit command is ignored.
+ * Color format of solid color is considered to be
+ *	the same as destination color format
+ * Channel order of solid color is A-R-G-B or Y-Cb-Cr
+ */
+void fimg2d4x_set_color_fill(struct fimg2d_control *info, unsigned long color)
+{
+	wr(FIMG2D_SOLID_FILL, FIMG2D_BITBLT_COMMAND_REG);
+
+	/* sf color */
+	wr(color, FIMG2D_SF_COLOR_REG);
+
+	/* set 16 burst for performance */
+	fimg2d4x_set_max_burst_length(info, MAX_BURST_16);
+}
+
+/**
+ * set alpha-multiply mode for src, dst, pat read (pre-bitblt)
+ * set alpha-demultiply for dst write (post-bitblt)
+ */
+void fimg2d4x_set_premultiplied(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_PREMULT_ALL;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_src_premultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_SRC_PREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_dst_premultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_DST_RD_PREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+void fimg2d4x_dst_depremultiply(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_DST_WR_DEPREMULT;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+/**
+ * set transp/bluscr mode, bs color, bg color
+ */
+void fimg2d4x_set_bluescreen(struct fimg2d_control *info,
+		struct fimg2d_bluscr *bluscr)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+
+	if (bluscr->mode == TRANSP)
+		cfg |= FIMG2D_TRANSP_MODE;
+	else if (bluscr->mode == BLUSCR)
+		cfg |= FIMG2D_BLUSCR_MODE;
+	else	/* opaque: initial value */
+		return;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	/* bs color */
+	if (bluscr->bs_color)
+		wr(bluscr->bs_color, FIMG2D_BS_COLOR_REG);
+
+	/* bg color */
+	if (bluscr->mode == BLUSCR && bluscr->bg_color)
+		wr(bluscr->bg_color, FIMG2D_BG_COLOR_REG);
+}
+
+/**
+ * @c: destination clipping region
+ */
+void fimg2d4x_enable_clipping(struct fimg2d_control *info,
+				struct fimg2d_clip *clp)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_CW;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	wr(FIMG2D_OFFSET(clp->x1, clp->y1), FIMG2D_CW_LT_REG);
+	wr(FIMG2D_OFFSET(clp->x2, clp->y2), FIMG2D_CW_RB_REG);
+}
+
+void fimg2d4x_enable_dithering(struct fimg2d_control *info)
+{
+	unsigned long cfg;
+
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ENABLE_DITHER;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+}
+
+#define MAX_PRECISION 16
+#define DEFAULT_SCALE_RATIO	0x10000
+
+/**
+ * scale_factor_to_fixed16 - convert scale factor to fixed pint 16
+ * @n: numerator
+ * @d: denominator
+ */
+static inline unsigned long scale_factor_to_fixed16(int n, int d)
+{
+	int i;
+	u32 fixed16;
+
+	if (!d)
+		return DEFAULT_SCALE_RATIO;
+
+	fixed16 = (n/d) << 16;
+	n %= d;
+
+	for (i = 0; i < MAX_PRECISION; i++) {
+		if (!n)
+			break;
+		n <<= 1;
+		if (n/d)
+			fixed16 |= 1 << (15-i);
+		n %= d;
+	}
+
+	return fixed16;
+}
+
+void fimg2d4x_set_src_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long wcfg, hcfg;
+	unsigned long mode;
+
+	/*
+	 * scaling ratio in pixels
+	 * e.g scale-up: src(1,1)-->dst(2,2), src factor: 0.5 (0x000080000)
+	 *     scale-down: src(2,2)-->dst(1,1), src factor: 2.0 (0x000200000)
+	 */
+
+	/* inversed scaling factor: src is numerator */
+	wcfg = scale_factor_to_fixed16(scl->src_w, scl->dst_w);
+	hcfg = scale_factor_to_fixed16(scl->src_h, scl->dst_h);
+
+	if (wcfg == DEFAULT_SCALE_RATIO && hcfg == DEFAULT_SCALE_RATIO)
+		return;
+
+	wr(wcfg, FIMG2D_SRC_XSCALE_REG);
+	wr(hcfg, FIMG2D_SRC_YSCALE_REG);
+
+	/* scaling algorithm */
+	if (scl->mode == SCALING_NEAREST)
+		mode = FIMG2D_SCALE_MODE_NEAREST;
+	else {
+		/* 0x3: ignore repeat mode at boundary */
+		if (rep->mode == REPEAT_PAD || rep->mode == REPEAT_CLAMP)
+			mode = 0x3;	/* hidden */
+		else
+			mode = FIMG2D_SCALE_MODE_BILINEAR;
+	}
+
+	wr(mode, FIMG2D_SRC_SCALE_CTRL_REG);
+}
+
+void fimg2d4x_set_msk_scaling(struct fimg2d_control *info,
+				struct fimg2d_scale *scl,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long wcfg, hcfg;
+	unsigned long mode;
+
+	/*
+	 * scaling ratio in pixels
+	 * e.g scale-up: src(1,1)-->dst(2,2), msk factor: 0.5 (0x000080000)
+	 *     scale-down: src(2,2)-->dst(1,1), msk factor: 2.0 (0x000200000)
+	 */
+
+	/* inversed scaling factor: src is numerator */
+	wcfg = scale_factor_to_fixed16(scl->src_w, scl->dst_w);
+	hcfg = scale_factor_to_fixed16(scl->src_h, scl->dst_h);
+
+	if (wcfg == DEFAULT_SCALE_RATIO && hcfg == DEFAULT_SCALE_RATIO)
+		return;
+
+	wr(wcfg, FIMG2D_MSK_XSCALE_REG);
+	wr(hcfg, FIMG2D_MSK_YSCALE_REG);
+
+	/* scaling algorithm */
+	if (scl->mode == SCALING_NEAREST)
+		mode = FIMG2D_SCALE_MODE_NEAREST;
+	else {
+		/* 0x3: ignore repeat mode at boundary */
+		if (rep->mode == REPEAT_PAD || rep->mode == REPEAT_CLAMP)
+			mode = 0x3;	/* hidden */
+		else
+			mode = FIMG2D_SCALE_MODE_BILINEAR;
+	}
+
+	wr(mode, FIMG2D_MSK_SCALE_CTRL_REG);
+}
+
+void fimg2d4x_set_src_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long cfg;
+
+	if (rep->mode == NO_REPEAT)
+		return;
+
+	cfg = (rep->mode - REPEAT_NORMAL) << FIMG2D_SRC_REPEAT_SHIFT;
+
+	wr(cfg, FIMG2D_SRC_REPEAT_MODE_REG);
+
+	/* src pad color */
+	if (rep->mode == REPEAT_PAD)
+		wr(rep->pad_color, FIMG2D_SRC_PAD_VALUE_REG);
+}
+
+void fimg2d4x_set_msk_repeat(struct fimg2d_control *info,
+				struct fimg2d_repeat *rep)
+{
+	unsigned long cfg;
+
+	if (rep->mode == NO_REPEAT)
+		return;
+
+	cfg = (rep->mode - REPEAT_NORMAL) << FIMG2D_MSK_REPEAT_SHIFT;
+
+	wr(cfg, FIMG2D_MSK_REPEAT_MODE_REG);
+
+	/* mask pad color */
+	if (rep->mode == REPEAT_PAD)
+		wr(rep->pad_color, FIMG2D_MSK_PAD_VALUE_REG);
+}
+
+void fimg2d4x_set_rotation(struct fimg2d_control *info, enum rotation rot)
+{
+	int rev_rot90;	/* counter clockwise, 4.1 specific */
+	unsigned long cfg;
+	enum addressing dirx, diry;
+
+	rev_rot90 = 0;
+	dirx = diry = FORWARD_ADDRESSING;
+
+	switch (rot) {
+	case ROT_90:	/* -270 degree */
+		rev_rot90 = 1;	/* fall through */
+	case ROT_180:
+		dirx = REVERSE_ADDRESSING;
+		diry = REVERSE_ADDRESSING;
+		break;
+	case ROT_270:	/* -90 degree */
+		rev_rot90 = 1;
+		break;
+	case XFLIP:
+		diry = REVERSE_ADDRESSING;
+		break;
+	case YFLIP:
+		dirx = REVERSE_ADDRESSING;
+		break;
+	case ORIGIN:
+	default:
+		break;
+	}
+
+	/* destination direction */
+	if (dirx == REVERSE_ADDRESSING || diry == REVERSE_ADDRESSING) {
+		cfg = rd(FIMG2D_DST_PAT_DIRECT_REG);
+
+		if (dirx == REVERSE_ADDRESSING)
+			cfg |= FIMG2D_DST_X_DIR_NEGATIVE;
+
+		if (diry == REVERSE_ADDRESSING)
+			cfg |= FIMG2D_DST_Y_DIR_NEGATIVE;
+
+		wr(cfg, FIMG2D_DST_PAT_DIRECT_REG);
+	}
+
+	/* rotation -90 */
+	if (rev_rot90) {
+		cfg = rd(FIMG2D_ROTATE_REG);
+		cfg |= FIMG2D_SRC_ROTATE_90;
+		cfg |= FIMG2D_MSK_ROTATE_90;
+
+		wr(cfg, FIMG2D_ROTATE_REG);
+	}
+}
+
+void fimg2d4x_set_fgcolor(struct fimg2d_control *info, unsigned long fg)
+{
+	wr(fg, FIMG2D_FG_COLOR_REG);
+}
+
+void fimg2d4x_set_bgcolor(struct fimg2d_control *info, unsigned long bg)
+{
+	wr(bg, FIMG2D_BG_COLOR_REG);
+}
+
+void fimg2d4x_enable_alpha(struct fimg2d_control *info, unsigned char g_alpha)
+{
+	unsigned long cfg;
+
+	/* enable alpha */
+	cfg = rd(FIMG2D_BITBLT_COMMAND_REG);
+	cfg |= FIMG2D_ALPHA_BLEND_MODE;
+
+	wr(cfg, FIMG2D_BITBLT_COMMAND_REG);
+
+	/*
+	 * global(constant) alpha
+	 * ex. if global alpha is 0x80, must set 0x80808080
+	 */
+	cfg = g_alpha;
+	cfg |= g_alpha << 8;
+	cfg |= g_alpha << 16;
+	cfg |= g_alpha << 24;
+	wr(cfg, FIMG2D_ALPHA_REG);
+}
+
+/**
+ * Four channels of the image are computed with:
+ *	R = [ coeff(S)*Sc  + coeff(D)*Dc ]
+ *	where
+ *	Rc is result color or alpha
+ *	Sc is source color or alpha
+ *	Dc is destination color or alpha
+ *
+ * Caution: supposed that Sc and Dc are perpixel-alpha-premultiplied value
+ *
+ * MODE:             Formula
+ * ----------------------------------------------------------------------------
+ * FILL:
+ * CLEAR:	     R = 0
+ * SRC:		     R = Sc
+ * DST:		     R = Dc
+ * SRC_OVER:         R = Sc + (1-Sa)*Dc
+ * DST_OVER:         R = (1-Da)*Sc + Dc
+ * SRC_IN:	     R = Da*Sc
+ * DST_IN:           R = Sa*Dc
+ * SRC_OUT:          R = (1-Da)*Sc
+ * DST_OUT:          R = (1-Sa)*Dc
+ * SRC_ATOP:         R = Da*Sc + (1-Sa)*Dc
+ * DST_ATOP:         R = (1-Da)*Sc + Sa*Dc
+ * XOR:              R = (1-Da)*Sc + (1-Sa)*Dc
+ * ADD:              R = Sc + Dc
+ * MULTIPLY:         R = Sc*Dc
+ * SCREEN:           R = Sc + (1-Sc)*Dc
+ * DARKEN:           R = (Da*Sc<Sa*Dc)? Sc+(1-Sa)*Dc : (1-Da)*Sc+Dc
+ * LIGHTEN:          R = (Da*Sc>Sa*Dc)? Sc+(1-Sa)*Dc : (1-Da)*Sc+Dc
+ * DISJ_SRC_OVER:    R = Sc + (min(1,(1-Sa)/Da))*Dc
+ * DISJ_DST_OVER:    R = (min(1,(1-Da)/Sa))*Sc + Dc
+ * DISJ_SRC_IN:      R = (max(1-(1-Da)/Sa,0))*Sc
+ * DISJ_DST_IN:      R = (max(1-(1-Sa)/Da,0))*Dc
+ * DISJ_SRC_OUT:     R = (min(1,(1-Da)/Sa))*Sc
+ * DISJ_DST_OUT:     R = (min(1,(1-Sa)/Da))*Dc
+ * DISJ_SRC_ATOP:    R = (max(1-(1-Da)/Sa,0))*Sc + (min(1,(1-Sa)/Da))*Dc
+ * DISJ_DST_ATOP:    R = (min(1,(1-Da)/Sa))*Sc + (max(1-(1-Sa)/Da,0))*Dc
+ * DISJ_XOR:         R = (min(1,(1-Da)/Sa))*Sc + (min(1,(1-Sa)/Da))*Dc
+ * CONJ_SRC_OVER:    R = Sc + (max(1-Sa/Da,0))*Dc
+ * CONJ_DST_OVER:    R = (max(1-Da/Sa,0))*Sc + Dc
+ * CONJ_SRC_IN:      R = (min(1,Da/Sa))*Sc
+ * CONJ_DST_IN:      R = (min(1,Sa/Da))*Dc
+ * CONJ_SRC_OUT:     R = (max(1-Da/Sa,0)*Sc
+ * CONJ_DST_OUT:     R = (max(1-Sa/Da,0))*Dc
+ * CONJ_SRC_ATOP:    R = (min(1,Da/Sa))*Sc + (max(1-Sa/Da,0))*Dc
+ * CONJ_DST_ATOP:    R = (max(1-Da/Sa,0))*Sc + (min(1,Sa/Da))*Dc
+ * CONJ_XOR:         R = (max(1-Da/Sa,0))*Sc + (max(1-Sa/Da,0))*Dc
+ */
+static struct fimg2d_blend_coeff const coeff_table[MAX_FIMG2D_BLIT_OP] = {
+	{ 0, 0, 0, 0 },		/* FILL */
+	{ 0, COEFF_ZERO,	0, COEFF_ZERO },	/* CLEAR */
+	{ 0, COEFF_ONE,		0, COEFF_ZERO },	/* SRC */
+	{ 0, COEFF_ZERO,	0, COEFF_ONE },		/* DST */
+	{ 0, COEFF_ONE,		1, COEFF_SA },		/* SRC_OVER */
+	{ 1, COEFF_DA,		0, COEFF_ONE },		/* DST_OVER */
+	{ 0, COEFF_DA,		0, COEFF_ZERO },	/* SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_SA },		/* DST_IN */
+	{ 1, COEFF_DA,		0, COEFF_ZERO },	/* SRC_OUT */
+	{ 0, COEFF_ZERO,	1, COEFF_SA },		/* DST_OUT */
+	{ 0, COEFF_DA,		1, COEFF_SA },		/* SRC_ATOP */
+	{ 1, COEFF_DA,		0, COEFF_SA },		/* DST_ATOP */
+	{ 1, COEFF_DA,		1, COEFF_SA },		/* XOR */
+	{ 0, COEFF_ONE,		0, COEFF_ONE },		/* ADD */
+	{ 0, COEFF_DC,		0, COEFF_ZERO },	/* MULTIPLY */
+	{ 0, COEFF_ONE,		1, COEFF_SC },		/* SCREEN */
+	{ 0, 0, 0, 0 },		/* DARKEN */
+	{ 0, 0, 0, 0 },		/* LIGHTEN */
+	{ 0, COEFF_ONE,		0, COEFF_DISJ_S },	/* DISJ_SRC_OVER */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_DST_OVER */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ZERO },	/* DISJ_SRC_IN */
+	{ 0, COEFF_ZERO,	1, COEFF_DISJ_S },	/* DISJ_DST_IN */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_SRC_OUT */
+	{ 0, COEFF_ZERO,	0, COEFF_DISJ_S },	/* DISJ_DST_OUT */
+	{ 1, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_SRC_ATOP */
+	{ 0, COEFF_DISJ_D,	1, COEFF_DISJ_S },	/* DISJ_DST_ATOP */
+	{ 0, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_XOR */
+	{ 0, COEFF_ONE,		1, COEFF_DISJ_S },	/* CONJ_SRC_OVER */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ONE },		/* CONJ_DST_OVER */
+	{ 0, COEFF_CONJ_D,	0, COEFF_ONE },		/* CONJ_SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_CONJ_S },	/* CONJ_DST_IN */
+	{ 1, COEFF_CONJ_D,	0, COEFF_ZERO },	/* CONJ_SRC_OUT */
+	{ 0, COEFF_ZERO,	1, COEFF_CONJ_S },	/* CONJ_DST_OUT */
+	{ 0, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_SRC_ATOP */
+	{ 1, COEFF_CONJ_D,	0, COEFF_CONJ_D },	/* CONJ_DST_ATOP */
+	{ 1, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_XOR */
+	{ 0, 0, 0, 0 },		/* USER */
+	{ 1, COEFF_GA,		1, COEFF_ZERO },	/* USER_SRC_GA */
+};
+
+/*
+ * coefficient table with global (constant) alpha
+ * replace COEFF_ONE with COEFF_GA
+ *
+ * MODE:             Formula with Global Alpha (Ga is multiplied to both Sc and Sa)
+ * ----------------------------------------------------------------------------
+ * FILL:
+ * CLEAR:	     R = 0
+ * SRC:		     R = Ga*Sc
+ * DST:		     R = Dc
+ * SRC_OVER:         R = Ga*Sc + (1-Sa*Ga)*Dc
+ * DST_OVER:         R = (1-Da)*Ga*Sc + Dc --> (W/A) 1st:Ga*Sc, 2nd:DST_OVER
+ * SRC_IN:	     R = Da*Ga*Sc
+ * DST_IN:           R = Sa*Ga*Dc
+ * SRC_OUT:          R = (1-Da)*Ga*Sc --> (W/A) 1st: Ga*Sc, 2nd:SRC_OUT
+ * DST_OUT:          R = (1-Sa*Ga)*Dc
+ * SRC_ATOP:         R = Da*Ga*Sc + (1-Sa*Ga)*Dc
+ * DST_ATOP:         R = (1-Da)*Ga*Sc + Sa*Ga*Dc --> (W/A) 1st: Ga*Sc, 2nd:DST_ATOP
+ * XOR:              R = (1-Da)*Ga*Sc + (1-Sa*Ga)*Dc --> (W/A) 1st: Ga*Sc, 2nd:XOR
+ * ADD:              R = Ga*Sc + Dc
+ * MULTIPLY:         R = Ga*Sc*Dc --> (W/A) 1st: Ga*Sc, 2nd: MULTIPLY
+ * SCREEN:           R = Ga*Sc + (1-Ga*Sc)*Dc --> (W/A) 1st: Ga*Sc, 2nd: SCREEN
+ * DARKEN:           R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * LIGHTEN:          R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_SRC_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_DST_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * DISJ_XOR:         R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_OVER:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_IN:      R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_OUT:     R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_SRC_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_DST_ATOP:    R = (W/A) 1st: Ga*Sc, 2nd: OP
+ * CONJ_XOR:         R = (W/A) 1st: Ga*Sc, 2nd: OP
+ */
+static struct fimg2d_blend_coeff const ga_coeff_table[MAX_FIMG2D_BLIT_OP] = {
+	{ 0, 0, 0, 0 },		/* FILL */
+	{ 0, COEFF_ZERO,	0, COEFF_ZERO },	/* CLEAR */
+	{ 0, COEFF_GA,		0, COEFF_ZERO },	/* SRC */
+	{ 0, COEFF_ZERO,	0, COEFF_ONE },		/* DST */
+	{ 0, COEFF_GA,		1, COEFF_SA },		/* SRC_OVER */
+	{ 1, COEFF_DA,		0, COEFF_ONE },		/* DST_OVER (use W/A) */
+	{ 0, COEFF_DA,		0, COEFF_ZERO },	/* SRC_IN */
+	{ 0, COEFF_ZERO,	0, COEFF_SA },		/* DST_IN */
+	{ 1, COEFF_DA,		0, COEFF_ZERO },	/* SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_SA },		/* DST_OUT */
+	{ 0, COEFF_DA,		1, COEFF_SA },		/* SRC_ATOP */
+	{ 1, COEFF_DA,		0, COEFF_SA },		/* DST_ATOP (use W/A) */
+	{ 1, COEFF_DA,		1, COEFF_SA },		/* XOR (use W/A) */
+	{ 0, COEFF_GA,		0, COEFF_ONE },		/* ADD */
+	{ 0, COEFF_DC,		0, COEFF_ZERO },	/* MULTIPLY (use W/A) */
+	{ 0, COEFF_ONE,		1, COEFF_SC },		/* SCREEN (use W/A) */
+	{ 0, 0, 0, 0 },		/* DARKEN (use W/A) */
+	{ 0, 0, 0, 0 },		/* LIGHTEN (use W/A) */
+	{ 0, COEFF_ONE,		0, COEFF_DISJ_S },	/* DISJ_SRC_OVER (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_DST_OVER (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ZERO },	/* DISJ_SRC_IN (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_DISJ_S },	/* DISJ_DST_IN (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_ONE },		/* DISJ_SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	0, COEFF_DISJ_S },	/* DISJ_DST_OUT (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_SRC_ATOP (use W/A) */
+	{ 0, COEFF_DISJ_D,	1, COEFF_DISJ_S },	/* DISJ_DST_ATOP (use W/A) */
+	{ 0, COEFF_DISJ_D,	0, COEFF_DISJ_S },	/* DISJ_XOR (use W/A) */
+	{ 0, COEFF_ONE,		1, COEFF_DISJ_S },	/* CONJ_SRC_OVER (use W/A) */
+	{ 1, COEFF_DISJ_D,	0, COEFF_ONE },		/* CONJ_DST_OVER (use W/A) */
+	{ 0, COEFF_CONJ_D,	0, COEFF_ONE },		/* CONJ_SRC_IN (use W/A) */
+	{ 0, COEFF_ZERO,	0, COEFF_CONJ_S },	/* CONJ_DST_IN (use W/A) */
+	{ 1, COEFF_CONJ_D,	0, COEFF_ZERO },	/* CONJ_SRC_OUT (use W/A) */
+	{ 0, COEFF_ZERO,	1, COEFF_CONJ_S },	/* CONJ_DST_OUT (use W/A) */
+	{ 0, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_SRC_ATOP (use W/A) */
+	{ 1, COEFF_CONJ_D,	0, COEFF_CONJ_D },	/* CONJ_DST_ATOP (use W/A) */
+	{ 1, COEFF_CONJ_D,	1, COEFF_CONJ_S },	/* CONJ_XOR (use W/A) */
+	{ 0, 0, 0, 0 },		/* USER */
+	{ 1, COEFF_GA,		1, COEFF_ZERO },	/* USER_SRC_GA */
+};
+
+void fimg2d4x_set_alpha_composite(struct fimg2d_control *info,
+		enum blit_op op, unsigned char g_alpha)
+{
+	int alphamode;
+	unsigned long cfg = 0;
+	struct fimg2d_blend_coeff const *tbl;
+
+	switch (op) {
+	case BLIT_OP_SOLID_FILL:
+	case BLIT_OP_CLR:
+		/* nop */
+		return;
+	case BLIT_OP_DARKEN:
+		cfg |= FIMG2D_DARKEN;
+		break;
+	case BLIT_OP_LIGHTEN:
+		cfg |= FIMG2D_LIGHTEN;
+		break;
+	case BLIT_OP_USER_COEFF:
+		/* TODO */
+		return;
+	default:
+		if (g_alpha < 0xff) {	/* with global alpha */
+			tbl = &ga_coeff_table[op];
+			alphamode = ALPHA_PERPIXEL_MUL_GLOBAL;
+		} else {
+			tbl = &coeff_table[op];
+			alphamode = ALPHA_PERPIXEL;
+		}
+
+		/* src coefficient */
+		cfg |= tbl->s_coeff << FIMG2D_SRC_COEFF_SHIFT;
+
+		cfg |= alphamode << FIMG2D_SRC_COEFF_SA_SHIFT;
+		cfg |= alphamode << FIMG2D_SRC_COEFF_DA_SHIFT;
+
+		if (tbl->s_coeff_inv)
+			cfg |= FIMG2D_INV_SRC_COEFF;
+
+		/* dst coefficient */
+		cfg |= tbl->d_coeff << FIMG2D_DST_COEFF_SHIFT;
+
+		cfg |= alphamode << FIMG2D_DST_COEFF_DA_SHIFT;
+		cfg |= alphamode << FIMG2D_DST_COEFF_SA_SHIFT;
+
+		if (tbl->d_coeff_inv)
+			cfg |= FIMG2D_INV_DST_COEFF;
+
+		break;
+	}
+
+	wr(cfg, FIMG2D_BLEND_FUNCTION_REG);
+
+	/* round mode: depremult round mode is not used */
+	cfg = rd(FIMG2D_ROUND_MODE_REG);
+
+	/* premult */
+	cfg &= ~FIMG2D_PREMULT_ROUND_MASK;
+	cfg |= premult_round_mode << FIMG2D_PREMULT_ROUND_SHIFT;
+
+	/* blend */
+	cfg &= ~FIMG2D_BLEND_ROUND_MASK;
+	cfg |= blend_round_mode << FIMG2D_BLEND_ROUND_SHIFT;
+
+	wr(cfg, FIMG2D_ROUND_MODE_REG);
+}
+
+void fimg2d4x_dump_regs(struct fimg2d_control *info)
+{
+	int i, offset;
+	unsigned long table[][2] = {
+		/* start, end */
+		{0x0000, 0x0030},	/* general */
+		{0x0080, 0x00a0},	/* host dma */
+		{0x0100, 0x0110},	/* commands */
+		{0x0200, 0x0210},	/* rotation & direction */
+		{0x0300, 0x0340},	/* source */
+		{0x0400, 0x0420},	/* dest */
+		{0x0500, 0x0550},	/* pattern & mask */
+		{0x0600, 0x0710},	/* clip, rop, alpha and color */
+		{0x0, 0x0}
+	};
+
+	for (i = 0; table[i][1] != 0x0; i++) {
+		offset = table[i][0];
+		do {
+			printk(KERN_INFO "[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", offset,
+				rd(offset),
+				rd(offset+0x4),
+				rd(offset+0x8),
+				rd(offset+0xc));
+			offset += 0x10;
+		} while (offset < table[i][1]);
+	}
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d4x_regs.h b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_regs.h
new file mode 100644
index 0000000..91c7ac8
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d4x_regs.h
@@ -0,0 +1,460 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d4x_regs.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Register Definitions for Samsung Graphics 2D Hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D4X_REGS_H
+#define __FIMG2D4x_REGS_H __FILE__
+
+/* Macros */
+#define FIMG2D_ADDR(v)		((v) << 0)
+#define FIMG2D_STRIDE(v)	(((v) & (0xffff)) << 0)
+#define FIMG2D_OFFSET(x, y)	((((y) & 0x1fff) << 16) | (((x) & 0x1fff) << 0))
+#define FIMG2D_SIZE(w, h)	((((h) & 0x1fff) << 16) | (((w) & 0x1fff) << 0))
+#define FIMG2D_COLOR(v)		((v) << 0)
+
+/* Registers */
+#define FIMG2D_SOFT_RESET_REG			(0x000)
+#define FIMG2D_INTEN_REG			(0x004)
+#define FIMG2D_INTC_PEND_REG			(0x00c)
+#define FIMG2D_FIFO_STAT_REG			(0x010)
+#define FIMG2D_AXI_MODE_REG			(0x01c)
+#define FIMG2D_DMA_SFR_BASE_ADDR_REG		(0x080)
+#define FIMG2D_DMA_COMMAND_REG			(0x084)
+#define FIMG2D_DMA_EXE_LIST_NUM_REG		(0x088)
+#define FIMG2D_DMA_STATUS_REG			(0x08c)
+#define FIMG2D_DMA_HOLD_CMD_REG			(0x090)
+#define FIMG2D_BITBLT_START_REG			(0x100)
+#define FIMG2D_BITBLT_COMMAND_REG		(0x104)
+#define FIMG2D_BLEND_FUNCTION_REG		(0x108)
+#define FIMG2D_ROUND_MODE_REG			(0x10c)
+#define FIMG2D_ROTATE_REG			(0x200)
+#define FIMG2D_SRC_MSK_DIRECT_REG		(0x204)
+#define FIMG2D_DST_PAT_DIRECT_REG		(0x208)
+#define FIMG2D_SRC_SELECT_REG			(0x300)
+#define FIMG2D_SRC_BASE_ADDR_REG		(0x304)
+#define FIMG2D_SRC_STRIDE_REG			(0x308)
+#define FIMG2D_SRC_COLOR_MODE_REG		(0x30c)
+#define FIMG2D_SRC_LEFT_TOP_REG			(0x310)
+#define FIMG2D_SRC_RIGHT_BOTTOM_REG		(0x314)
+#define FIMG2D_SRC_PLANE2_BASE_ADDR_REG		(0x318)
+#define FIMG2D_SRC_REPEAT_MODE_REG		(0x31c)
+#define FIMG2D_SRC_PAD_VALUE_REG		(0x320)
+#define FIMG2D_SRC_A8_RGB_EXT_REG		(0x324)
+#define FIMG2D_SRC_SCALE_CTRL_REG		(0x328)
+#define FIMG2D_SRC_XSCALE_REG			(0x32c)
+#define FIMG2D_SRC_YSCALE_REG			(0x330)
+#define FIMG2D_DST_SELECT_REG			(0x400)
+#define FIMG2D_DST_BASE_ADDR_REG		(0x404)
+#define FIMG2D_DST_STRIDE_REG			(0x408)
+#define FIMG2D_DST_COLOR_MODE_REG		(0x40c)
+#define FIMG2D_DST_LEFT_TOP_REG			(0x410)
+#define FIMG2D_DST_RIGHT_BOTTOM_REG		(0x414)
+#define FIMG2D_DST_PLANE2_BASE_ADDR_REG		(0x418)
+#define FIMG2D_DST_A8_RGB_EXT_REG		(0x41c)
+#define FIMG2D_PAT_BASE_ADDR_REG		(0x500)
+#define FIMG2D_PAT_SIZE_REG			(0x504)
+#define FIMG2D_PAT_COLOR_MODE_REG		(0x508)
+#define FIMG2D_PAT_OFFSET_REG			(0x50c)
+#define FIMG2D_PAT_STRIDE_REG			(0x510)
+#define FIMG2D_MSK_BASE_ADDR_REG		(0x520)
+#define FIMG2D_MSK_STRIDE_REG			(0x524)
+#define FIMG2D_MSK_LEFT_TOP_REG			(0x528)
+#define FIMG2D_MSK_RIGHT_BOTTOM_REG		(0x52c)
+#define FIMG2D_MSK_MODE_REG			(0x530)
+#define FIMG2D_MSK_REPEAT_MODE_REG		(0x534)
+#define FIMG2D_MSK_PAD_VALUE_REG		(0x538)
+#define FIMG2D_MSK_SCALE_CTRL_REG		(0x53c)
+#define FIMG2D_MSK_XSCALE_REG			(0x540)
+#define FIMG2D_MSK_YSCALE_REG			(0x544)
+#define FIMG2D_CW_LT_REG			(0x600)
+#define FIMG2D_CW_RB_REG			(0x604)
+#define FIMG2D_THIRD_OPERAND_REG		(0x610)
+#define FIMG2D_ROP4_REG				(0x614)
+#define FIMG2D_ALPHA_REG			(0x618)
+#define FIMG2D_FG_COLOR_REG			(0x700)
+#define FIMG2D_BG_COLOR_REG			(0x704)
+#define FIMG2D_BS_COLOR_REG			(0x708)
+#define FIMG2D_SF_COLOR_REG			(0x70c)
+#define FIMG2D_SRC_COLORKEY_CTRL_REG		(0x710)
+#define FIMG2D_SRC_COLORKEY_DR_MIN_REG		(0x714)
+#define FIMG2D_SRC_COLORKEY_DR_MAX_REG		(0x718)
+#define FIMG2D_DST_COLORKEY_CTRL_REG		(0x71c)
+#define FIMG2D_DST_COLORKEY_DR_MIN_REG		(0x720)
+#define FIMG2D_DST_COLORKEY_DR_MAX_REG		(0x724)
+#define FIMG2D_YCBCR_SRC_COLORKEY_CTRL_REG	(0x728)
+#define FIMG2D_YCBCR_SRC_COLORKEY_DR_MIN_REG	(0x72c)
+#define FIMG2D_YCBCR_SRC_COLORKEY_DR_MAX_REG	(0x730)
+#define FIMG2D_YCBCR_DST_COLORKEY_CTRL_REG	(0x734)
+#define FIMG2D_YCBCR_DST_COLORKEY_DR_MIN_REG	(0x738)
+#define FIMG2D_YCBCR_DST_COLORKEY_DR_MAX_REG	(0x73c)
+#define FIMG2D_GAMMA_TABLE0_0_REG		(0x800)
+#define FIMG2D_GAMMA_TABLE0_1_REG		(0x804)
+#define FIMG2D_GAMMA_TABLE0_2_REG		(0x808)
+#define FIMG2D_GAMMA_TABLE0_3_REG		(0x80c)
+#define FIMG2D_GAMMA_TABLE0_4_REG		(0x810)
+#define FIMG2D_GAMMA_TABLE0_5_REG		(0x814)
+#define FIMG2D_GAMMA_TABLE0_6_REG		(0x818)
+#define FIMG2D_GAMMA_TABLE0_7_REG		(0x81c)
+#define FIMG2D_GAMMA_TABLE0_8_REG		(0x820)
+#define FIMG2D_GAMMA_TABLE0_9_REG		(0x824)
+#define FIMG2D_GAMMA_TABLE0_10_REG		(0x828)
+#define FIMG2D_GAMMA_TABLE0_11_REG		(0x82c)
+#define FIMG2D_GAMMA_TABLE0_12_REG		(0x830)
+#define FIMG2D_GAMMA_TABLE0_13_REG		(0x834)
+#define FIMG2D_GAMMA_TABLE0_14_REG		(0x838)
+#define FIMG2D_GAMMA_TABLE0_15_REG		(0x83c)
+#define FIMG2D_GAMMA_TABLE1_0_REG		(0x840)
+#define FIMG2D_GAMMA_TABLE1_1_REG		(0x844)
+#define FIMG2D_GAMMA_TABLE1_2_REG		(0x848)
+#define FIMG2D_GAMMA_TABLE1_3_REG		(0x84c)
+#define FIMG2D_GAMMA_TABLE1_4_REG		(0x850)
+#define FIMG2D_GAMMA_TABLE1_5_REG		(0x854)
+#define FIMG2D_GAMMA_TABLE1_6_REG		(0x858)
+#define FIMG2D_GAMMA_TABLE1_7_REG		(0x85c)
+#define FIMG2D_GAMMA_TABLE1_8_REG		(0x860)
+#define FIMG2D_GAMMA_TABLE1_9_REG		(0x864)
+#define FIMG2D_GAMMA_TABLE1_10_REG		(0x868)
+#define FIMG2D_GAMMA_TABLE1_11_REG		(0x86c)
+#define FIMG2D_GAMMA_TABLE1_12_REG		(0x870)
+#define FIMG2D_GAMMA_TABLE1_13_REG		(0x874)
+#define FIMG2D_GAMMA_TABLE1_14_REG		(0x878)
+#define FIMG2D_GAMMA_TABLE1_15_REG		(0x87c)
+#define FIMG2D_GAMMA_REF_COLOR_REG		(0x880)
+
+/* Bit Definitions */
+
+/* FIMG2D_SOFT_RESET_REG */
+#define FIMG2D_SFR_CLEAR			(1 << 1)
+#define FIMG2D_SOFT_RESET			(1 << 0)
+
+/* FIMG2D_INTEN_REG */
+#define FIMG2D_INT_TYPE_EDGE			(1 << 4)
+#define FIMG2D_INT_TYPE_LEVEL			(0 << 4)
+
+#define FIMG2D_ACF_INT_ENABLE			(1 << 3)
+#define FIMG2D_UCF_INT_ENABLE			(1 << 2)
+#define FIMG2D_GCF_INT_ENABLE			(1 << 1)
+#define FIMG2D_BLIT_INT_ENABLE			(1 << 0)
+
+/* FIMG2D_INTC_PEND_REG */
+#define FIMG2D_ACMD_INT_FLAG			(1 << 3)
+#define FIMG2D_UCMD_INT_FLAG			(1 << 2)
+#define FIMG2D_GCMD_INT_FLAG			(1 << 1)
+#define FIMG2D_BLIT_INT_FLAG			(1 << 0)
+
+/* FIMG2D_FIFO_STAT_REG */
+#define FIMG2D_BLIT_FINISHED			(1 << 0)
+
+/* FIMG2D_AXI_MODE_REG */
+#define FIMG2D_MAX_BURST_LEN_2			(0 << 24)
+#define FIMG2D_MAX_BURST_LEN_4			(1 << 24)
+#define FIMG2D_MAX_BURST_LEN_8			(2 << 24)
+#define FIMG2D_MAX_BURST_LEN_16			(3 << 24)
+#define FIMG2D_MAX_BURST_LEN_MASK		(3 << 24)
+#define FIMG2D_MAX_BURST_LEN_SHIFT		(24)
+
+#define FIMG2D_AXI_AWUSERS_SHIFT		(16)
+#define FIMG2D_AXI_ARUSERS_SHIFT		(8)
+#define FIMG2D_AXI_AWCACHE_SHIFT		(4)
+#define FIMG2D_AXI_ARCACHE_SHIFT		(0)
+
+/* FIMG2D_DMA_SFR_BASE_ADDR_REG */
+
+/* FIMG2D_DMA_COMMAND_REG */
+#define FIMG2D_BATCH_BLIT_HALT			(1 << 2)
+#define FIMG2D_BATCH_BLIT_CONT			(1 << 1)
+#define FIMG2D_BATCH_BLIT_START			(1 << 0)
+
+/* FIMG2D_DMA_EXE_LIST_NUM_REG */
+#define FIMG2D_BATCH_BLIT_EXELIST_NUM_MASK	(0xff)
+#define FIMG2D_BATCH_BLIT_EXELIST_NUM_SHIFT	(0)
+
+/* FIMG2D_DMA_STATUS_REG */
+#define FIMG2D_BATCH_BLIT_DONELIST_CNT_MASK	(0xff)
+#define FIMG2D_BATCH_BLIT_DONELIST_CNT_SHIFT	(17)
+
+#define FIMG2D_BATCH_BLIT_DONEBLIT_CNT_MASK	(0xffff)
+#define FIMG2D_BATCH_BLIT_DONEBLIT_CNT_SHIFT	(1)
+
+#define FIMG2D_BATCH_BLIT_DONE_MASK		(1)
+#define FIMG2D_BATCH_BLIT_DONE_SHIFT		(0)
+
+/* FIMG2D_DMA_HOLD_CMD_REG */
+#define FIMG2D_BATCH_BLIT_USER_HOLD		(1 << 2)
+#define FIMG2D_BATCH_BLIT_LIST_HOLD		(1 << 1)
+#define FIMG2D_BATCH_BLIT_BLIT_HOLD		(1 << 0)
+
+/* FIMG2D_BITBLT_START_REG */
+#define FIMG2D_START_N_HOLD			(1 << 1)
+#define FIMG2D_START_BITBLT			(1 << 0)
+
+/* FIMG2D_BITBLT_COMMAND_REG */
+#define FIMG2D_SOLID_FILL			(1 << 28)
+
+#define FIMG2D_DST_WR_DEPREMULT			(1 << 27)
+#define FIMG2D_DST_RD_PREMULT			(1 << 26)
+#define FIMG2D_PAT_PREMULT			(1 << 25)
+#define FIMG2D_SRC_PREMULT			(1 << 24)
+#define FIMG2D_PREMULT_ALL			(0xf << 24)
+
+#define FIMG2D_ALPHA_BLEND_MODE			(1 << 20)
+
+#define FIMG2D_COLORKEY_SRC_RGBA		(1 << 16)
+#define FIMG2D_COLORKEY_DST_RGBA		(2 << 16)
+#define FIMG2D_COLORKEY_SRC_YCBCR		(4 << 16)
+#define FIMG2D_COLORKEY_DST_YCBCR		(8 << 16)
+
+#define FIMG2D_OPAQUE_MODE			(0 << 12)
+#define FIMG2D_TRANSP_MODE			(1 << 12)
+#define FIMG2D_BLUSCR_MODE			(2 << 12)
+
+#define FIMG2D_ENABLE_CW			(1 << 8)
+#define FIMG2D_ENABLE_DITHER			(1 << 3)
+
+#define FIMG2D_ENABLE_SRC_ALPHA			(0 << 2)
+#define FIMG2D_ENABLE_ROP_ALPHA			(1 << 2)
+
+#define FIMG2D_ENABLE_ROP4_MSK			(1 << 0)
+#define FIMG2D_ENABLE_NORMAL_MSK		(2 << 0)
+
+/* FIMG2D_BLEND_FUNCTION_REG */
+#define FIMG2D_WINCE_SRC_OVER			(1 << 22)
+#define FIMG2D_DARKEN				(1 << 21)
+#define FIMG2D_LIGHTEN				(1 << 20)
+#define FIMG2D_INV_DST_COEFF			(1 << 18)
+#define FIMG2D_INV_SRC_COEFF			(1 << 16)
+
+#define FIMG2D_DST_COEFF_DA_SHIFT		(14)
+#define FIMG2D_DST_COEFF_SA_SHIFT		(12)
+#define FIMG2D_SRC_COEFF_DA_SHIFT		(6)
+#define FIMG2D_SRC_COEFF_SA_SHIFT		(4)
+
+#define FIMG2D_DST_COEFF_SHIFT			(8)
+#define FIMG2D_SRC_COEFF_SHIFT			(0)
+
+/* FIMG2D_ROUND_MODE_REG */
+#define FIMG2D_PREMULT_ROUND_MASK		(3 << 4)
+#define FIMG2D_PREMULT_ROUND_SHIFT		(4)
+
+#define FIMG2D_BLEND_ROUND_MASK			(3 << 0)
+#define FIMG2D_BLEND_ROUND_SHIFT		(0)
+
+/* FIMG2D_ROTATE_REG */
+#define FIMG2D_MSK_ROTATE_90			(1 << 8)
+#define FIMG2D_PAT_ROTATE_90			(1 << 4)
+#define FIMG2D_SRC_ROTATE_90			(1 << 0)
+
+/* FIMG2D_SRC_MSK_DIRECT_REG */
+#define FIMG2D_MSK_Y_DIR_NEGATIVE		(1 << 5)
+#define FIMG2D_MSK_X_DIR_NEGATIVE		(1 << 4)
+
+#define FIMG2D_SRC_Y_DIR_NEGATIVE		(1 << 1)
+#define FIMG2D_SRC_X_DIR_NEGATIVE		(1 << 0)
+
+/* FIMG2D_DST_PAT_DIRECT_REG */
+#define FIMG2D_PAT_Y_DIR_NEGATIVE		(1 << 5)
+#define FIMG2D_PAT_X_DIR_NEGATIVE		(1 << 4)
+
+#define FIMG2D_DST_Y_DIR_NEGATIVE		(1 << 1)
+#define FIMG2D_DST_X_DIR_NEGATIVE		(1 << 0)
+
+/* FIMG2D_SRC_SELECT_REG & FIMG2D_DST_SELECT_REG */
+#define FIMG2D_IMAGE_TYPE_MEMORY		(0 << 0)
+#define FIMG2D_IMAGE_TYPE_FGCOLOR		(1 << 0)
+#define FIMG2D_IMAGE_TYPE_BGCOLOR		(2 << 0)
+
+/* FIMG2D_SRC_BASE_ADDR_REG */
+/* FIMG2D_DST_BASE_ADDR_REG */
+/* FIMG2D_PAT_BASE_ADDR_REG */
+/* FIMG2D_MSK_BASE_ADDR_REG */
+
+/* FIMG2D_SRC_STRIDE_REG */
+/* FIMG2D_DST_STRIDE_REG */
+/* FIMG2D_PAT_STRIDE_REG */
+/* FIMG2D_MSK_STRIDE_REG */
+
+/* FIMG2D_SRC_COLOR_MODE_REG & FIMG2D_DST_COLOR_MODE_REG */
+#define FIMG2D_YCBCR_NARROW			(0 << 17)
+#define FIMG2D_YCBCR_WIDE			(1 << 17)
+
+#define FIMG2D_CSC_601				(0 << 16)
+#define FIMG2D_CSC_709				(1 << 16)
+
+#define FIMG2D_YCBCR_ORDER_P1_CRY1CBY0		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_CBY1CRY0		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_Y1CRY0CB		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P1_Y1CBY0CR		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P2_CRCB		(0 << 12)
+#define FIMG2D_YCBCR_ORDER_P2_CBCR		(1 << 12)
+#define FIMG2D_YCBCR_ORDER_SHIFT		(12)
+
+#define FIMG2D_YCBCR_1PLANE			(0 << 8)
+#define FIMG2D_YCBCR_2PLANE			(1 << 8)
+
+#define FIMG2D_RGB_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_RGB_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_RGB_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_RGB_ORDER_BGRAX			(3 << 4)
+#define FIMG2D_RGB_ORDER_SHIFT			(4)
+
+#define FIMG2D_COLOR_FORMAT_XRGB_8888		(0 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_8888		(1 << 0)
+#define FIMG2D_COLOR_FORMAT_RGB_565		(2 << 0)
+#define FIMG2D_COLOR_FORMAT_XRGB_1555		(3 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_1555		(4 << 0)
+#define FIMG2D_COLOR_FORMAT_XRGB_4444		(5 << 0)
+#define FIMG2D_COLOR_FORMAT_ARGB_4444		(6 << 0)
+#define FIMG2D_COLOR_FORMAT_PACKED_RGB_888	(7 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_444		(8 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_422		(9 << 0)
+#define FIMG2D_COLOR_FORMAT_YCBCR_420		(10 << 0)
+#define FIMG2D_COLOR_FORMAT_A8			(11 << 0)
+#define FIMG2D_COLOR_FORMAT_L8			(12 << 0)
+#define FIMG2D_COLOR_FORMAT_SHIFT		(0)
+
+/* FIMG2D_PAT_COLOR_MODE_REG */
+#define FIMG2D_PAT_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_PAT_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_PAT_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_PAT_ORDER_BGRAX			(3 << 4)
+
+#define FIMG2D_PAT_FORMAT_XRGB_8888		(0 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_8888		(1 << 0)
+#define FIMG2D_PAT_FORMAT_RGB_565		(2 << 0)
+#define FIMG2D_PAT_FORMAT_XRGB_1555		(3 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_1555		(4 << 0)
+#define FIMG2D_PAT_FORMAT_XRGB_4444		(5 << 0)
+#define FIMG2D_PAT_FORMAT_ARGB_4444		(6 << 0)
+#define FIMG2D_PAT_FORMAT_PACKED_RGB_888	(7 << 0)
+
+/* FIMG2D_SRC_LEFT_TOP_REG & FIMG2D_SRC_RIGHT_BOTTOM_REG */
+/* FIMG2D_DST_LEFT_TOP_REG & FIMG2D_DST_RIGHT_BOTTOM_REG */
+/* FIMG2D_MSK_LEFT_TOP_REG & FIMG2D_MSK_RIGHT_BOTTOM_REG */
+#define FIMG2D_COORD_LT_Y_SHIFT			(16)
+#define FIMG2D_COORD_LT_X_SHIFT			(0)
+#define FIMG2D_COORD_RB_Y_SHIFT			(16)
+#define FIMG2D_COORD_RB_X_SHIFT			(0)
+#define FIMG2D_COORD_MAX_HEIGHT			(8000)
+#define FIMG2D_COORD_MAX_WIDTH			(8000)
+
+/* FIMG2D_SRC_PLANE2_BASE_ADDR_REG */
+/* FIMG2D_DST_PLANE2_BASE_ADDR_REG */
+
+/* FIMG2D_SRC_REPEAT_MODE_REG */
+#define FIMG2D_SRC_REPEAT_NORMAL		(0 << 0)
+#define FIMG2D_SRC_REPEAT_PAD			(1 << 0)
+#define FIMG2D_SRC_REPEAT_REFLECT		(2 << 0)
+#define FIMG2D_SRC_REPEAT_CLAMP			(3 << 0)
+#define FIMG2D_SRC_REPEAT_NONE			(4 << 0)
+#define FIMG2D_SRC_REPEAT_SHIFT			(0)
+
+/* FIMG2D_MSK_REPEAT_MODE_REG */
+#define FIMG2D_MSK_REPEAT_NORMAL		(0 << 0)
+#define FIMG2D_MSK_REPEAT_PAD			(1 << 0)
+#define FIMG2D_MSK_REPEAT_REFLECT		(2 << 0)
+#define FIMG2D_MSK_REPEAT_CLAMP			(3 << 0)
+#define FIMG2D_MSK_REPEAT_SHIFT			(0)
+
+/* FIMG2D_SRC_PAD_VALUE_REG */
+/* FIMG2D_MSK_PAD_VALUE_REG */
+
+/* FIMG2D_SRC_A8_RGB_EXT_REG */
+/* FIMG2D_DST_A8_RGB_EXT_REG */
+
+/* FIMG2D_SRC_SCALE_CTRL_REG & FIMG2D_MSK_SCALE_CTRL_REG */
+#define FIMG2D_SCALE_MODE_NEAREST		(1 << 0)
+#define FIMG2D_SCALE_MODE_BILINEAR		(2 << 0)
+
+/* FIMG2D_SRC_XSCALE_REG & FIMG2D_SRC_YSCALE_REG */
+/* FIMG2D_MSK_XSCALE_REG & FIMG2D_MSK_YSCALE_REG */
+#define FIMG2D_SCALE_FACTOR_INTG_SHIFT		(16)
+#define FIMG2D_SCALE_FACTOR_FRAC_SHIFT		(0)
+
+/* FIMG2D_PAT_SIZE_REG */
+#define FIMG2D_PAT_HEIGHT_SHIFT			(16)
+#define FIMG2D_PAT_WIDTH_SHIFT			(0)
+#define FIMG2D_MAX_PAT_HEIGHT			(8000)
+#define FIMG2D_MAX_PAT_WIDTH			(8000)
+
+/* FIMG2D_PAT_OFFSET_REG */
+#define FIMG2D_PAT_Y_OFFSET_SHIFT		(16)
+#define FIMG2D_PAT_X_OFFSET_SHIFT		(0)
+#define FIMG2D_MAX_PAT_Y_OFFSET			(7999)
+#define FIMG2D_MAX_PAT_X_OFFSET			(7999)
+
+/* FIMG2D_MSK_MODE_REG */
+#define FIMG2D_MSK_TYPE_ALPHA			(0 << 8)
+#define FIMG2D_MSK_TYPE_ARGB			(1 << 8)
+#define FIMG2D_MSK_TYPE_MIXED			(2 << 8)
+
+#define FIMG2D_MSK_ORDER_AXRGB			(0 << 4)
+#define FIMG2D_MSK_ORDER_RGBAX			(1 << 4)
+#define FIMG2D_MSK_ORDER_AXBGR			(2 << 4)
+#define FIMG2D_MSK_ORDER_BGRAX			(3 << 4)
+#define FIMG2D_MSK_ORDER_SHIFT			(4)
+
+#define FIMG2D_1BIT_MSK				(0 << 0)
+#define FIMG2D_4BIT_MSK				(1 << 0)
+#define FIMG2D_8BIT_MSK				(2 << 0)
+#define FIMG2D_16BIT_MSK_565			(3 << 0)
+#define FIMG2D_16BIT_MSK_1555			(4 << 0)
+#define FIMG2D_16BIT_MSK_4444			(5 << 0)
+#define FIMG2D_32BIT_MSK_8888			(6 << 0)
+#define FIMG2D_4BIT_MSK_WINCE_AA_FONT		(7 << 0)
+#define FIMG2D_MSK_FORMAT_SHIFT			(0)
+
+/* FIMG2D_CW_LT_REG */
+#define FIMG2D_CW_COORD_LT_Y_SHIFT		(16)
+#define FIMG2D_CW_COORD_LT_X_SHIFT		(0)
+#define FIMG2D_CW_COORD_RB_Y_SHIFT		(16)
+#define FIMG2D_CW_COORD_RB_X_SHIFT		(0)
+
+/* FIMG2D_THIRD_OPERAND_REG */
+#define FIMG2D_OPR3_MSKSEL_PAT			(0 << 4)
+#define FIMG2D_OPR3_MSKSEL_FGCOLOR		(1 << 4)
+#define FIMG2D_OPR3_MSKSEL_BGCOLOR		(2 << 4)
+#define FIMG2D_OPR3_UNMSKSEL_PAT		(0 << 0)
+#define FIMG2D_OPR3_UNMSKSEL_FGCOLOR		(1 << 0)
+#define FIMG2D_OPR3_UNMSKSEL_BGCOLOR		(2 << 0)
+
+/* FIMG2D_ROP4_REG */
+#define FIMG2D_MASKED_ROP3_SHIFT		(8)
+#define FIMG2D_UNMASKED_ROP3_SHIFT		(0)
+
+/* FIMG2D_ALPHA_REG */
+#define FIMG2D_GCOLOR_RGB_MASK			(0xffffff)
+#define FIMG2D_GCOLOR_SHIFT			(8)
+
+#define FIMG2D_GALPHA_MASK			(0xff)
+#define FIMG2D_GALPHA_SHIFT			(0)
+
+/* FIMG2D_FG_COLOR_REG */
+/* FIMG2D_BG_COLOR_REG */
+/* FIMG2D_BS_COLOR_REG */
+/* FIMG2D_SF_COLOR_REG */
+
+/* FIMG2D_SRC_COLORKEY_CTRL_REG */
+/* FIMG2D_SRC_COLORKEY_DR_MIN_REG */
+/* FIMG2D_SRC_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_DST_COLORKEY_CTRL_REG */
+/* FIMG2D_DST_COLORKEY_DR_MIN_REG */
+/* FIMG2D_DST_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_YCBCR_SRC_COLORKEY_CTRL_REG */
+/* FIMG2D_YCBCR_SRC_COLORKEY_DR_MIN_REG */
+/* FIMG2D_YCBCR_SRC_COLORKEY_DR_MAX_REG */
+
+/* FIMG2D_YCBCR_DST_COLORKEY_CTRL_REG */
+/* FIMG2D_YCBCR_DST_COLORKEY_DR_MIN_REG */
+/* FIMG2D_YCBCR_DST_COLORKEY_DR_MAX_REG */
+
+#endif /* __FIMG2D4X_REGS_H */
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.c b/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.c
new file mode 100644
index 0000000..b494175
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.c
@@ -0,0 +1,168 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/dma-mapping.h>
+#include <asm/pgtable.h>
+#include <asm/cacheflush.h>
+
+#include "fimg2d.h"
+#include "fimg2d_cache.h"
+
+#define LV1_SHIFT		20
+#define LV1_PT_SIZE		SZ_1M
+#define LV2_PT_SIZE		SZ_1K
+#define LV2_BASE_MASK		0x3ff
+#define LV2_PT_MASK		0xff000
+#define LV2_SHIFT		12
+#define LV1_DESC_MASK		0x3
+#define LV2_DESC_MASK		0x2
+
+static inline unsigned long virt2phys(struct mm_struct *mm, unsigned long vaddr)
+{
+	unsigned long *pgd;
+	unsigned long *lv1d, *lv2d;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	lv1d = pgd + (vaddr >> LV1_SHIFT);
+
+	if ((*lv1d & LV1_DESC_MASK) != 0x1) {
+		fimg2d_debug("invalid LV1 descriptor, "
+				"pgd %p lv1d 0x%lx vaddr 0x%lx\n",
+				pgd, *lv1d, vaddr);
+		return 0;
+	}
+
+	lv2d = (unsigned long *)phys_to_virt(*lv1d & ~LV2_BASE_MASK) +
+				((vaddr & LV2_PT_MASK) >> LV2_SHIFT);
+
+	if ((*lv2d & LV2_DESC_MASK) != 0x2) {
+		fimg2d_debug("invalid LV2 descriptor, "
+				"pgd %p lv2d 0x%lx vaddr 0x%lx\n",
+				pgd, *lv2d, vaddr);
+		return 0;
+	}
+
+	return (*lv2d & PAGE_MASK) | (vaddr & (PAGE_SIZE-1));
+}
+
+#ifdef CONFIG_OUTER_CACHE
+void fimg2d_dma_sync_outer(struct mm_struct *mm, unsigned long vaddr,
+					size_t size, enum cache_opr opr)
+{
+	int len;
+	unsigned long cur, end, next, paddr;
+
+	cur = vaddr;
+	end = vaddr + size;
+
+	if (opr == CACHE_CLEAN) {
+		while (cur < end) {
+			next = (cur + PAGE_SIZE) & PAGE_MASK;
+			if (next > end)
+				next = end;
+			len = next - cur;
+
+			paddr = virt2phys(mm, cur);
+			if (paddr)
+				outer_clean_range(paddr, paddr + len);
+			cur += len;
+		}
+	} else if (opr == CACHE_FLUSH) {
+		while (cur < end) {
+			next = (cur + PAGE_SIZE) & PAGE_MASK;
+			if (next > end)
+				next = end;
+			len = next - cur;
+
+			paddr = virt2phys(mm, cur);
+			if (paddr)
+				outer_flush_range(paddr, paddr + len);
+			cur += len;
+		}
+	}
+}
+
+void fimg2d_clean_outer_pagetable(struct mm_struct *mm, unsigned long vaddr,
+					size_t size)
+{
+	unsigned long *pgd;
+	unsigned long *lv1, *lv1end;
+	unsigned long lv2pa;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	lv1 = pgd + (vaddr >> LV1_SHIFT);
+	lv1end = pgd + ((vaddr + size + LV1_PT_SIZE-1) >> LV1_SHIFT);
+
+	/* clean level1 page table */
+	outer_clean_range(virt_to_phys(lv1), virt_to_phys(lv1end));
+
+	do {
+		lv2pa = *lv1 & ~LV2_BASE_MASK;	/* lv2 pt base */
+		/* clean level2 page table */
+		outer_clean_range(lv2pa, lv2pa + LV2_PT_SIZE);
+		lv1++;
+	} while (lv1 != lv1end);
+}
+#endif /* CONFIG_OUTER_CACHE */
+
+enum pt_status fimg2d_check_pagetable(struct mm_struct *mm,
+		unsigned long vaddr, size_t size)
+{
+	unsigned long *pgd;
+	unsigned long *lv1d, *lv2d;
+
+	pgd = (unsigned long *)mm->pgd;
+
+	size += offset_in_page(vaddr);
+	size = PAGE_ALIGN(size);
+
+	while ((long)size > 0) {
+		lv1d = pgd + (vaddr >> LV1_SHIFT);
+
+		/*
+		 * check level 1 descriptor
+		 *	lv1 desc[1:0] = 00 --> fault
+		 *	lv1 desc[1:0] = 01 --> page table
+		 *	lv1 desc[1:0] = 10 --> section or supersection
+		 *	lv1 desc[1:0] = 11 --> reserved
+		 */
+		if ((*lv1d & LV1_DESC_MASK) != 0x1) {
+			fimg2d_debug("invalid LV1 descriptor, "
+					"pgd %p lv1d 0x%lx vaddr 0x%lx\n",
+					pgd, *lv1d, vaddr);
+			return PT_FAULT;
+		}
+
+		lv2d = (unsigned long *)phys_to_virt(*lv1d & ~LV2_BASE_MASK) +
+				((vaddr & LV2_PT_MASK) >> LV2_SHIFT);
+
+		/*
+		 * check level 2 descriptor
+		 *	lv2 desc[1:0] = 00 --> fault
+		 *	lv2 desc[1:0] = 01 --> 64k pgae
+		 *	lv2 desc[1:0] = 1x --> 4k page
+		 */
+		if ((*lv2d & LV2_DESC_MASK) != 0x2) {
+			fimg2d_debug("invalid LV2 descriptor, "
+					"pgd %p lv2d 0x%lx vaddr 0x%lx\n",
+					pgd, *lv2d, vaddr);
+			return PT_FAULT;
+		}
+
+		vaddr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+
+	return PT_NORMAL;
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.h b/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.h
new file mode 100644
index 0000000..ac3cbe4
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.h
@@ -0,0 +1,101 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_cache.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+#include <plat/cpu.h>
+#include "fimg2d.h"
+
+#define L1_CACHE_SIZE		SZ_64K
+#define L2_CACHE_SIZE		SZ_1M
+#define LINE_FLUSH_THRESHOLD	SZ_1K
+
+/**
+ * cache_opr - [kernel] cache operation mode
+ * @CACHE_INVAL: do cache invalidate
+ * @CACHE_CLEAN: do cache clean for src and msk image
+ * @CACHE_FLUSH: do cache clean and invalidate for dst image
+ * @CACHE_FLUSH_INNER_ALL: clean and invalidate for innercache
+ * @CACHE_FLUSH_ALL: clean and invalidate for whole caches
+ */
+enum cache_opr {
+	CACHE_INVAL,
+	CACHE_CLEAN,
+	CACHE_FLUSH,
+	CACHE_FLUSH_INNER_ALL,
+	CACHE_FLUSH_ALL
+};
+
+/**
+ * @PT_NORMAL: pagetable exists
+ * @PT_FAULT: invalid pagetable
+ */
+enum pt_status {
+	PT_NORMAL,
+	PT_FAULT,
+};
+
+static inline bool is_inner_flushall(size_t size)
+{
+	if (soc_is_exynos5250())
+		return (size >= SZ_1M * 25) ? true : false;
+	else
+		return (size >= L1_CACHE_SIZE) ? true : false;
+}
+
+static inline bool is_outer_flushall(size_t size)
+{
+	return (size >= L2_CACHE_SIZE) ? true : false;
+}
+
+static inline bool is_inner_flushrange(size_t hole)
+{
+	if (!soc_is_exynos5250())
+		return true;
+	else {
+		if (hole < LINE_FLUSH_THRESHOLD)
+			return true;
+		else
+			return false;	/* line-by-line flush */
+	}
+}
+
+static inline bool is_outer_flushrange(size_t hole)
+{
+	if (hole < LINE_FLUSH_THRESHOLD)
+		return true;
+	else
+		return false;	/* line-by-line flush */
+}
+
+static inline void fimg2d_dma_sync_inner(unsigned long addr, size_t size,
+		int dir)
+{
+	if (dir == DMA_TO_DEVICE)
+		dmac_map_area((void *)addr, size, dir);
+	else if (dir == DMA_BIDIRECTIONAL)
+		dmac_flush_range((void *)addr, (void *)(addr + size));
+}
+
+static inline void fimg2d_dma_unsync_inner(unsigned long addr, size_t size,
+		int dir)
+{
+	if (dir == DMA_TO_DEVICE)
+		dmac_unmap_area((void *)addr, size, dir);
+}
+
+void fimg2d_clean_outer_pagetable(struct mm_struct *mm, unsigned long addr,
+		size_t size);
+void fimg2d_dma_sync_outer(struct mm_struct *mm, unsigned long addr,
+		size_t size, enum cache_opr opr);
+enum pt_status fimg2d_check_pagetable(struct mm_struct *mm, unsigned long addr,
+		size_t size);
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.c b/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.c
new file mode 100644
index 0000000..24a80ae
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.c
@@ -0,0 +1,170 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/atomic.h>
+#include <linux/sched.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+
+void fimg2d_clk_on(struct fimg2d_control *info)
+{
+	spin_lock(&info->bltlock);
+	clk_enable(info->clock);
+	atomic_set(&info->clkon, 1);
+	spin_unlock(&info->bltlock);
+
+	fimg2d_debug("clock enable\n");
+}
+
+void fimg2d_clk_off(struct fimg2d_control *info)
+{
+	spin_lock(&info->bltlock);
+	atomic_set(&info->clkon, 0);
+	clk_disable(info->clock);
+	spin_unlock(&info->bltlock);
+
+	fimg2d_debug("clock disable\n");
+}
+
+void fimg2d_clk_save(struct fimg2d_control *info)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		struct clk *sclk;
+
+		pdata = to_fimg2d_plat(info->dev);
+
+		spin_lock(&info->bltlock);
+		sclk = clk_get(info->dev, pdata->clkname);
+		clk_set_rate(sclk, 50*MHZ); /* 800MHz/16=50MHz */
+		spin_unlock(&info->bltlock);
+
+		fimg2d_debug("%s clkrate=%lu\n", pdata->clkname, clk_get_rate(sclk));
+	}
+}
+
+void fimg2d_clk_restore(struct fimg2d_control *info)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		struct clk *sclk, *pclk;
+
+		pdata = to_fimg2d_plat(info->dev);
+
+		spin_lock(&info->bltlock);
+		sclk = clk_get(info->dev, pdata->clkname);
+		pclk = clk_get(NULL, "pclk_acp");
+		clk_set_rate(sclk, clk_get_rate(pclk) * 2);
+		spin_unlock(&info->bltlock);
+
+		fimg2d_debug("%s(%lu) pclk_acp(%lu)\n", pdata->clkname,
+				clk_get_rate(sclk), clk_get_rate(pclk));
+	}
+}
+
+void fimg2d_clk_dump(struct fimg2d_control *info)
+{
+	struct fimg2d_platdata *pdata;
+	struct clk *sclk, *pclk, *aclk;
+
+	pdata = to_fimg2d_plat(info->dev);
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		sclk = clk_get(info->dev, pdata->clkname);
+		pclk = clk_get(NULL, "pclk_acp");
+
+		printk(KERN_INFO "%s(%lu) pclk_acp(%lu)\n",
+				pdata->clkname,
+				clk_get_rate(sclk), clk_get_rate(pclk));
+	} else {
+		aclk = clk_get(NULL, "aclk_acp");
+		pclk = clk_get(NULL, "pclk_acp");
+
+		printk(KERN_INFO "aclk_acp(%lu) pclk_acp(%lu)\n",
+				clk_get_rate(aclk), clk_get_rate(pclk));
+	}
+}
+
+int fimg2d_clk_setup(struct fimg2d_control *info)
+{
+	struct fimg2d_platdata *pdata;
+	struct clk *parent, *sclk;
+	int ret = 0;
+
+	sclk = parent = NULL;
+	pdata = to_fimg2d_plat(info->dev);
+
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		/* clock for setting parent and rate */
+		parent = clk_get(info->dev, pdata->parent_clkname);
+		if (IS_ERR(parent)) {
+			printk(KERN_ERR "FIMG2D failed to get parent clk\n");
+			ret = -ENOENT;
+			goto err_clk1;
+		}
+		fimg2d_debug("parent clk: %s\n", pdata->parent_clkname);
+
+		sclk = clk_get(info->dev, pdata->clkname);
+		if (IS_ERR(sclk)) {
+			printk(KERN_ERR "FIMG2D failed to get sclk\n");
+			ret = -ENOENT;
+			goto err_clk2;
+		}
+		fimg2d_debug("sclk: %s\n", pdata->clkname);
+
+		if (clk_set_parent(sclk, parent))
+			printk(KERN_ERR "FIMG2D failed to set parent\n");
+
+		clk_set_rate(sclk, pdata->clkrate);
+		fimg2d_debug("clkrate: %ld parent clkrate: %ld\n",
+				clk_get_rate(sclk), clk_get_rate(parent));
+	} else {
+		fimg2d_debug("aclk_acp(%lu) pclk_acp(%lu)\n",
+				clk_get_rate(clk_get(NULL, "aclk_acp")),
+				clk_get_rate(clk_get(NULL, "pclk_acp")));
+	}
+
+	/* clock for gating */
+	info->clock = clk_get(info->dev, pdata->gate_clkname);
+	if (IS_ERR(info->clock)) {
+		printk(KERN_ERR "FIMG2D failed to get gate clk\n");
+		ret = -ENOENT;
+		goto err_clk3;
+	}
+	fimg2d_debug("gate clk: %s\n", pdata->gate_clkname);
+	return ret;
+
+err_clk3:
+	if (sclk)
+		clk_put(sclk);
+
+err_clk2:
+	if (parent)
+		clk_put(parent);
+
+err_clk1:
+	return ret;
+}
+
+void fimg2d_clk_release(struct fimg2d_control *info)
+{
+	clk_put(info->clock);
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		struct fimg2d_platdata *pdata;
+		pdata = to_fimg2d_plat(info->dev);
+		clk_put(clk_get(info->dev, pdata->clkname));
+		clk_put(clk_get(info->dev, pdata->parent_clkname));
+	}
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.h b/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.h
new file mode 100644
index 0000000..c3fbf67
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.h
@@ -0,0 +1,26 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_clk.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_CLK_H__
+#define __FIMG2D_CLK_H__
+
+#include "fimg2d.h"
+
+int fimg2d_clk_setup(struct fimg2d_control *info);
+void fimg2d_clk_release(struct fimg2d_control *info);
+void fimg2d_clk_on(struct fimg2d_control *info);
+void fimg2d_clk_off(struct fimg2d_control *info);
+void fimg2d_clk_save(struct fimg2d_control *info);
+void fimg2d_clk_restore(struct fimg2d_control *info);
+void fimg2d_clk_dump(struct fimg2d_control *info);
+
+#endif /* __FIMG2D_CLK_H__ */
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.c b/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.c
new file mode 100644
index 0000000..63fd483
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.c
@@ -0,0 +1,551 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <plat/fimg2d.h>
+#include "fimg2d.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+static int bpptable[MSK_FORMAT_END+1] = {
+	32, 32,	16, 16, 16, 16, 16, 24,	/* rgb */
+	0, 0, 0, 8, 8, 0,		/* yuv */
+	1, 4, 8, 16, 16, 16, 32, 0,	/* msk */
+};
+
+static int fimg2d_check_params(struct fimg2d_bltcmd *cmd)
+{
+	int w, h, i;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_scale *scl;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+
+	/* dst is mandatory */
+	if (!cmd->image[IDST].addr.type)
+		return -1;
+
+	/* DST op makes no effect */
+	if (cmd->op < 0 || cmd->op == BLIT_OP_DST || cmd->op >= BLIT_OP_END)
+		return -1;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		w = img->width;
+		h = img->height;
+		r = &img->rect;
+
+		/* 8000: max width & height */
+		if (w > 8000 || h > 8000)
+			return -1;
+
+		if (r->x1 < 0 || r->y1 < 0 ||
+			r->x1 >= w || r->y1 >= h ||
+			r->x1 >= r->x2 || r->y1 >= r->y2)
+			return -1;
+	}
+
+	clp = &p->clipping;
+	if (clp->enable) {
+		img = &cmd->image[IDST];
+
+		w = img->width;
+		h = img->height;
+		r = &img->rect;
+
+		if (clp->x1 < 0 || clp->y1 < 0 ||
+			clp->x1 >= w || clp->y1 >= h ||
+			clp->x1 >= clp->x2 || clp->y1 >= clp->y2 ||
+			clp->x1 >= r->x2 || clp->x2 <= r->x1 ||
+			clp->y1 >= r->y2 || clp->y2 <= r->y1)
+			return -1;
+	}
+
+	scl = &p->scaling;
+	if (scl->mode) {
+		if (!scl->src_w || !scl->src_h || !scl->dst_w || !scl->dst_h)
+			return -1;
+	}
+
+	return 0;
+}
+
+static void fimg2d_fixup_params(struct fimg2d_bltcmd *cmd)
+{
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_scale *scl;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	int i;
+
+	clp = &p->clipping;
+	scl = &p->scaling;
+
+	/* fix dst/clip rect */
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		r = &img->rect;
+
+		if (i == IMAGE_DST && clp->enable) {
+			if (clp->x2 > img->width)
+				clp->x2 = img->width;
+			if (clp->y2 > img->height)
+				clp->y2 = img->height;
+		} else {
+			if (r->x2 > img->width)
+				r->x2 = img->width;
+			if (r->y2 > img->height)
+				r->y2 = img->height;
+		}
+	}
+
+	/* avoid devided-by-zero */
+	if (scl->mode &&
+		(scl->src_w == scl->dst_w && scl->src_h == scl->dst_h))
+		scl->mode = NO_SCALING;
+}
+
+static int pixel2offset(int pixel, enum color_format cf)
+{
+	return (pixel * bpptable[cf]) >> 3;
+}
+
+static int width2bytes(int width, enum color_format cf)
+{
+	int bpp = bpptable[cf];
+
+	switch (bpp) {
+	case 1:
+		return (width + 7) >> 3;
+	case 4:
+		return (width + 1) >> 1;
+	case 8:
+	case 16:
+	case 24:
+	case 32:
+		return width * bpp >> 3;
+	default:
+		return 0;
+	}
+}
+
+static inline int is_yuvfmt(enum color_format fmt)
+{
+	switch (fmt) {
+	case CF_YCBCR_420:
+	case CF_YCBCR_422:
+	case CF_YCBCR_444:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * @plane: 0 for 1st plane, 1 for 2nd plane
+ */
+static int yuv_stride(int width, enum color_format cf, enum pixel_order order,
+		int plane)
+{
+	int bpp;
+
+	switch (cf) {
+	case CF_YCBCR_420:
+		bpp = (!plane) ? 8 : 4;
+		break;
+	case CF_YCBCR_422:
+		if (order == P2_CRCB || order == P2_CBCR)
+			bpp = 8;
+		else
+			bpp = (!plane) ? 16 : 0;
+		break;
+	case CF_YCBCR_444:
+		bpp = (!plane) ? 8 : 16;
+		break;
+	default:
+		bpp = 0;
+		break;
+	}
+
+	return width * bpp >> 3;
+}
+
+static inline void fimg2d_calc_dma_size(struct fimg2d_bltcmd *cmd)
+{
+	struct fimg2d_image *img;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+	int i, y1, y2, stride;
+
+	clp = &cmd->param.clipping;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (img->addr.type != ADDR_USER &&
+				img->addr.type != ADDR_USER_CONTIG)
+			continue;
+
+		/* ! yuv format */
+		if (!is_yuvfmt(img->fmt)) {
+			r = &img->rect;
+
+			if (i == IMAGE_DST && clp->enable) {
+				y1 = clp->y1;
+				y2 = clp->y2;
+			} else {
+				y1 = r->y1;
+				y2 = r->y2;
+			}
+
+			c = &cmd->dma[i].base;
+			c->addr = img->addr.start + (img->stride * y1);
+			c->size = img->stride * (y2 - y1);
+
+			if (img->need_cacheopr) {
+				c->cached = c->size;
+				cmd->dma_all += c->cached;
+			}
+			continue;
+		}
+
+		stride = yuv_stride(img->width, img->fmt, img->order, 0);
+
+		c = &cmd->dma[i].base;
+		c->addr = img->addr.start;
+		c->size = stride * img->height;
+
+		if (img->need_cacheopr) {
+			c->cached = c->size;
+			cmd->dma_all += c->cached;
+		}
+
+		if (img->order == P2_CRCB || img->order == P2_CBCR) {
+			stride = yuv_stride(img->width, img->fmt,
+					img->order, 1);
+
+			c = &cmd->dma[i].plane2;
+			c->addr = img->plane2.start;
+			c->size = stride * img->height;
+
+			if (img->need_cacheopr) {
+				c->cached = c->size;
+				cmd->dma_all += c->cached;
+			}
+		}
+	}
+}
+
+static inline void inner_flush_clip_range(struct fimg2d_bltcmd *cmd)
+{
+	struct fimg2d_image *img;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+	int clp_x, clp_w, clp_h, y, i, dir;
+	int x1, y1, x2, y2;
+	unsigned long start;
+
+	clp = &cmd->param.clipping;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+
+		dir = (i == IMAGE_DST) ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+
+		/* yuv format */
+		if (is_yuvfmt(img->fmt)) {
+			c = &cmd->dma[i].base;
+			if (c->cached)
+				fimg2d_dma_sync_inner(c->addr, c->cached, dir);
+
+			c = &cmd->dma[i].plane2;
+			if (c->cached)
+				fimg2d_dma_sync_inner(c->addr, c->cached, dir);
+
+			continue;
+		}
+
+		c = &cmd->dma[i].base;
+		if (!c->cached)
+			continue;
+
+		r = &img->rect;
+
+		if (i == IMAGE_DST && clp->enable) {
+			x1 = clp->x1;
+			y1 = clp->y1;
+			x2 = clp->x2;
+			y2 = clp->y2;
+		} else {
+			x1 = r->x1;
+			y1 = r->y1;
+			x2 = r->x2;
+			y2 = r->y2;
+		}
+
+		clp_x = pixel2offset(x1, img->fmt);
+		clp_w = width2bytes(x2 - x1, img->fmt);
+		clp_h = y2 - y1;
+
+		if (is_inner_flushrange(img->stride - clp_w))
+			fimg2d_dma_sync_inner(c->addr, c->cached, dir);
+		else {
+			for (y = 0; y < clp_h; y++) {
+				start = c->addr + (img->stride * y) + clp_x;
+				fimg2d_dma_sync_inner(start, clp_w, dir);
+			}
+		}
+	}
+}
+
+static inline void outer_flush_clip_range(struct fimg2d_bltcmd *cmd)
+{
+	struct mm_struct *mm = cmd->ctx->mm;
+	struct fimg2d_image *img;
+	struct fimg2d_clip *clp;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+	int clp_x, clp_w, clp_h, y, i, dir;
+	int x1, y1, x2, y2;
+	unsigned long start;
+
+	clp = &cmd->param.clipping;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+
+		/* clean pagetable on outercache */
+		c = &cmd->dma[i].base;
+		if (c->size)
+			fimg2d_clean_outer_pagetable(mm, c->addr, c->size);
+
+		c = &cmd->dma[i].plane2;
+		if (c->size)
+			fimg2d_clean_outer_pagetable(mm, c->addr, c->size);
+
+		dir = (i == IMAGE_DST) ?  CACHE_FLUSH : CACHE_CLEAN;
+
+		/* yuv format */
+		if (is_yuvfmt(img->fmt)) {
+			c = &cmd->dma[i].base;
+			if (c->cached) {
+				fimg2d_dma_sync_outer(mm, c->addr, c->cached,
+						dir);
+			}
+
+			c = &cmd->dma[i].plane2;
+			if (c->cached) {
+				fimg2d_dma_sync_outer(mm, c->addr, c->cached,
+						dir);
+			}
+
+			continue;
+		}
+
+		c = &cmd->dma[i].base;
+		if (!c->cached)
+			continue;
+
+		r = &img->rect;
+
+		if (i == IMAGE_DST && clp->enable) {
+			x1 = clp->x1;
+			y1 = clp->y1;
+			x2 = clp->x2;
+			y2 = clp->y2;
+		} else {
+			x1 = r->x1;
+			y1 = r->y1;
+			x2 = r->x2;
+			y2 = r->y2;
+		}
+
+		clp_x = pixel2offset(x1, img->fmt);
+		clp_w = width2bytes(x2 - x1, img->fmt);
+		clp_h = y2 - y1;
+
+		if (is_outer_flushrange(img->stride - clp_w))
+			fimg2d_dma_sync_outer(mm, c->addr, c->cached, dir);
+		else {
+			for (y = 0; y < clp_h; y++) {
+				start = c->addr + (img->stride * y) + clp_x;
+				fimg2d_dma_sync_outer(mm, start, clp_w, dir);
+			}
+		}
+	}
+}
+
+static int fimg2d_check_dma_sync(struct fimg2d_bltcmd *cmd)
+{
+	struct mm_struct *mm = cmd->ctx->mm;
+	struct fimg2d_dma *c;
+	enum pt_status pt;
+	int i, ret;
+
+	fimg2d_calc_dma_size(cmd);
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		c = &cmd->dma[i].base;
+		if (!c->size)
+			continue;
+
+		pt = fimg2d_check_pagetable(mm, c->addr, c->size);
+		if (pt == PT_FAULT) {
+			ret = -EFAULT;
+			goto err_pgtable;
+		}
+	}
+
+#ifdef PERF_PROFILE
+	perf_start(cmd->ctx, PERF_INNERCACHE);
+#endif
+	if (is_inner_flushall(cmd->dma_all))
+		flush_all_cpu_caches();
+	else
+		inner_flush_clip_range(cmd);
+#ifdef PERF_PROFILE
+	perf_end(cmd->ctx, PERF_INNERCACHE);
+#endif
+
+#ifdef CONFIG_OUTER_CACHE
+#ifdef PERF_PROFILE
+	perf_start(cmd->ctx, PERF_OUTERCACHE);
+#endif
+	if (is_outer_flushall(cmd->dma_all))
+		outer_flush_all();
+	else
+		outer_flush_clip_range(cmd);
+#ifdef PERF_PROFILE
+	perf_end(cmd->ctx, PERF_OUTERCACHE);
+#endif
+#endif
+	return 0;
+
+err_pgtable:
+	return ret;
+}
+
+int fimg2d_add_command(struct fimg2d_control *info, struct fimg2d_context *ctx,
+			struct fimg2d_blit *blit)
+{
+	int i, ret;
+	struct fimg2d_image *buf[MAX_IMAGES] = image_table(blit);
+	struct fimg2d_bltcmd *cmd;
+	struct fimg2d_image dst;
+
+	if (blit->dst)
+		if (copy_from_user(&dst, (void *)blit->dst, sizeof(dst)))
+			return -EFAULT;
+
+	if ((blit->dst) && (dst.addr.type == ADDR_USER))
+		up_write(&page_alloc_slow_rwsem);
+	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+	if ((blit->dst) && (dst.addr.type == ADDR_USER))
+		down_write(&page_alloc_slow_rwsem);
+
+	if (!cmd)
+		return -ENOMEM;
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		if (!buf[i])
+			continue;
+
+		if (copy_from_user(&cmd->image[i], buf[i],
+					sizeof(struct fimg2d_image))) {
+			ret = -EFAULT;
+			goto err_user;
+		}
+	}
+
+	cmd->ctx = ctx;
+	cmd->op = blit->op;
+	cmd->sync = blit->sync;
+	cmd->seq_no = blit->seq_no;
+	memcpy(&cmd->param, &blit->param, sizeof(cmd->param));
+
+#ifdef CONFIG_VIDEO_FIMG2D_DEBUG
+	fimg2d_dump_command(cmd);
+#endif
+
+	if (fimg2d_check_params(cmd)) {
+		printk(KERN_ERR "[%s] invalid params\n", __func__);
+		fimg2d_dump_command(cmd);
+		ret = -EINVAL;
+		goto err_user;
+	}
+
+	fimg2d_fixup_params(cmd);
+
+	if (fimg2d_check_dma_sync(cmd)) {
+		ret = -EFAULT;
+		goto err_user;
+	}
+
+	/* add command node and increase ncmd */
+	spin_lock(&info->bltlock);
+	if (atomic_read(&info->suspended)) {
+		fimg2d_debug("fimg2d suspended, do sw fallback\n");
+		spin_unlock(&info->bltlock);
+		ret = -EFAULT;
+		goto err_user;
+	}
+	atomic_inc(&ctx->ncmd);
+	fimg2d_enqueue(&cmd->node, &info->cmd_q);
+	fimg2d_debug("ctx %p pgd %p ncmd(%d) seq_no(%u)\n",
+			cmd->ctx, (unsigned long *)cmd->ctx->mm->pgd,
+			atomic_read(&ctx->ncmd), cmd->seq_no);
+	spin_unlock(&info->bltlock);
+
+	return 0;
+
+err_user:
+	kfree(cmd);
+	return ret;
+}
+
+void fimg2d_del_command(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd)
+{
+	struct fimg2d_context *ctx = cmd->ctx;
+
+	spin_lock(&info->bltlock);
+	fimg2d_dequeue(&cmd->node);
+	kfree(cmd);
+	atomic_dec(&ctx->ncmd);
+	spin_unlock(&info->bltlock);
+}
+
+void fimg2d_add_context(struct fimg2d_control *info, struct fimg2d_context *ctx)
+{
+	atomic_set(&ctx->ncmd, 0);
+	init_waitqueue_head(&ctx->wait_q);
+
+	atomic_inc(&info->nctx);
+	fimg2d_debug("ctx %p nctx(%d)\n", ctx, atomic_read(&info->nctx));
+}
+
+void fimg2d_del_context(struct fimg2d_control *info, struct fimg2d_context *ctx)
+{
+	atomic_dec(&info->nctx);
+	fimg2d_debug("ctx %p nctx(%d)\n", ctx, atomic_read(&info->nctx));
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.h b/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.h
new file mode 100644
index 0000000..8a14607
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.h
@@ -0,0 +1,46 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_ctx.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "fimg2d.h"
+#include "fimg2d_helper.h"
+
+static inline void fimg2d_enqueue(struct list_head *node, struct list_head *q)
+{
+	list_add_tail(node, q);
+}
+
+static inline void fimg2d_dequeue(struct list_head *node)
+{
+	list_del(node);
+}
+
+static inline int fimg2d_queue_is_empty(struct list_head *q)
+{
+	return list_empty(q);
+}
+
+static inline
+struct fimg2d_bltcmd *fimg2d_get_first_command(struct fimg2d_control *info)
+{
+	if (list_empty(&info->cmd_q))
+		return NULL;
+
+	return list_first_entry(&info->cmd_q, struct fimg2d_bltcmd, node);
+}
+
+void fimg2d_add_context(struct fimg2d_control *info,
+		struct fimg2d_context *ctx);
+void fimg2d_del_context(struct fimg2d_control *info,
+		struct fimg2d_context *ctx);
+int fimg2d_add_command(struct fimg2d_control *info,
+		struct fimg2d_context *ctx, struct fimg2d_blit *blit);
+void fimg2d_del_command(struct fimg2d_control *info, struct fimg2d_bltcmd *cmd);
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_drv.c b/drivers/media/video/samsung/fimg2d4x/fimg2d_drv.c
new file mode 100644
index 0000000..0dc277e
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_drv.c
@@ -0,0 +1,507 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_drv.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/dma-mapping.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/atomic.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+#include <plat/cpu.h>
+#include <plat/fimg2d.h>
+#include <plat/sysmmu.h>
+#include <mach/dev.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#include "fimg2d.h"
+#include "fimg2d_clk.h"
+#include "fimg2d_ctx.h"
+#include "fimg2d_helper.h"
+
+#define CTX_TIMEOUT	msecs_to_jiffies(5000)
+
+static struct fimg2d_control *info;
+
+static void fimg2d_worker(struct work_struct *work)
+{
+	fimg2d_debug("start kernel thread\n");
+	info->blit(info);
+}
+
+static DECLARE_WORK(fimg2d_work, fimg2d_worker);
+
+/**
+ * @irq: irq number
+ * @dev_id: pointer to private data
+ */
+static irqreturn_t fimg2d_irq(int irq, void *dev_id)
+{
+	fimg2d_debug("irq\n");
+	info->stop(info);
+
+	return IRQ_HANDLED;
+}
+
+static int fimg2d_sysmmu_fault_handler(enum exynos_sysmmu_inttype itype,
+		unsigned long pgtable_base, unsigned long fault_addr)
+{
+	struct fimg2d_bltcmd *cmd;
+
+	if (itype == SYSMMU_PAGEFAULT) {
+		printk(KERN_ERR "[%s] sysmmu page fault(0x%lx), pgd(0x%lx)\n",
+				__func__, fault_addr, pgtable_base);
+	} else {
+		printk(KERN_ERR "[%s] sysmmu interrupt "
+				"type(%d) pgd(0x%lx) addr(0x%lx)\n",
+				__func__, itype, pgtable_base, fault_addr);
+	}
+
+	cmd = fimg2d_get_first_command(info);
+	if (!cmd) {
+		printk(KERN_ERR "[%s] null command\n", __func__);
+		goto next;
+	}
+
+	if (cmd->ctx->mm->pgd != phys_to_virt(pgtable_base)) {
+		printk(KERN_ERR "[%s] pgtable base is different from current command\n",
+				__func__);
+		goto next;
+	}
+
+	fimg2d_dump_command(cmd);
+
+next:
+	fimg2d_clk_dump(info);
+	info->dump(info);
+
+	BUG();
+	return 0;
+}
+
+static void fimg2d_context_wait(struct fimg2d_context *ctx)
+{
+	while (atomic_read(&ctx->ncmd)) {
+		if (!wait_event_timeout(ctx->wait_q, !atomic_read(&ctx->ncmd), CTX_TIMEOUT)) {
+			fimg2d_debug("[%s] ctx %p blit wait timeout\n", __func__, ctx);
+			if (info->err)
+				break;
+		}
+	}
+}
+
+static void fimg2d_request_bitblt(struct fimg2d_context *ctx)
+{
+	if (!atomic_read(&info->active)) {
+		atomic_set(&info->active, 1);
+		fimg2d_debug("dispatch ctx %p to kernel thread\n", ctx);
+		queue_work(info->work_q, &fimg2d_work);
+	}
+	fimg2d_context_wait(ctx);
+}
+
+static int fimg2d_open(struct inode *inode, struct file *file)
+{
+	struct fimg2d_context *ctx;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx) {
+		printk(KERN_ERR "[%s] not enough memory for ctx\n", __func__);
+		return -ENOMEM;
+	}
+	file->private_data = (void *)ctx;
+
+	ctx->mm = current->mm;
+	fimg2d_debug("ctx %p current pgd %p init_mm pgd %p\n",
+			ctx, (unsigned long *)ctx->mm->pgd,
+			(unsigned long *)init_mm.pgd);
+
+	fimg2d_add_context(info, ctx);
+	return 0;
+}
+
+static int fimg2d_release(struct inode *inode, struct file *file)
+{
+	struct fimg2d_context *ctx = file->private_data;
+
+	fimg2d_debug("ctx %p\n", ctx);
+	while (1) {
+		if (!atomic_read(&ctx->ncmd))
+			break;
+
+		mdelay(2);
+	}
+	fimg2d_del_context(info, ctx);
+
+	kfree(ctx);
+	return 0;
+}
+
+static int fimg2d_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+static unsigned int fimg2d_poll(struct file *file, struct poll_table_struct *wait)
+{
+	return 0;
+}
+
+static long fimg2d_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	struct fimg2d_context *ctx;
+	struct fimg2d_platdata *pdata;
+	struct fimg2d_blit blit;
+	struct fimg2d_version ver;
+	struct fimg2d_image dst;
+
+	ctx = file->private_data;
+	if (!ctx) {
+		printk(KERN_ERR "[%s] missing ctx\n", __func__);
+		return -EFAULT;
+	}
+
+	switch (cmd) {
+	case FIMG2D_BITBLT_BLIT:
+		if (info->err) {
+			printk(KERN_ERR "[%s] device error, do sw fallback\n",
+					__func__);
+			return -EFAULT;
+		}
+
+		if (copy_from_user(&blit, (void *)arg, sizeof(blit)))
+			return -EFAULT;
+		if (blit.dst)
+			if (copy_from_user(&dst, (void *)blit.dst, sizeof(dst)))
+				return -EFAULT;
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			dev_lock(info->bus_dev, info->dev, 160160);
+#endif
+#endif
+		if ((blit.dst) && (dst.addr.type == ADDR_USER))
+			down_write(&page_alloc_slow_rwsem);
+		ret = fimg2d_add_command(info, ctx, &blit);
+		if (!ret) {
+			fimg2d_request_bitblt(ctx);
+		}
+
+#ifdef PERF_PROFILE
+		perf_print(ctx, blit.seq_no);
+		perf_clear(ctx);
+#endif
+		if ((blit.dst) && (dst.addr.type == ADDR_USER))
+			up_write(&page_alloc_slow_rwsem);
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			dev_unlock(info->bus_dev, info->dev);
+#endif
+#endif
+		break;
+
+	case FIMG2D_BITBLT_SYNC:
+		fimg2d_debug("FIMG2D_BITBLT_SYNC ctx: %p\n", ctx);
+		/* FIXME: */
+		break;
+
+	case FIMG2D_BITBLT_VERSION:
+		pdata = to_fimg2d_plat(info->dev);
+		ver.hw = pdata->hw_ver;
+		ver.sw = 0;
+		fimg2d_debug("fimg2d version, hw: 0x%x sw: 0x%x\n",
+				ver.hw, ver.sw);
+		if (copy_to_user((void *)arg, &ver, sizeof(ver)))
+			return -EFAULT;
+		break;
+
+	default:
+#if 0
+		printk(KERN_ERR "[%s] unknown ioctl\n", __func__);
+#endif
+		ret = -EFAULT;
+		break;
+	}
+
+	return ret;
+}
+
+/* fops */
+static const struct file_operations fimg2d_fops = {
+	.owner          = THIS_MODULE,
+	.open           = fimg2d_open,
+	.release        = fimg2d_release,
+	.mmap           = fimg2d_mmap,
+	.poll           = fimg2d_poll,
+	.unlocked_ioctl = fimg2d_ioctl,
+};
+
+/* miscdev */
+static struct miscdevice fimg2d_dev = {
+	.minor		= FIMG2D_MINOR,
+	.name		= "fimg2d",
+	.fops		= &fimg2d_fops,
+};
+
+static int fimg2d_setup_controller(struct fimg2d_control *info)
+{
+	atomic_set(&info->suspended, 0);
+	atomic_set(&info->clkon, 0);
+	atomic_set(&info->busy, 0);
+	atomic_set(&info->nctx, 0);
+	atomic_set(&info->active, 0);
+
+	spin_lock_init(&info->bltlock);
+
+	INIT_LIST_HEAD(&info->cmd_q);
+	init_waitqueue_head(&info->wait_q);
+	fimg2d_register_ops(info);
+
+	info->work_q = create_singlethread_workqueue("kfimg2dd");
+	if (!info->work_q)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int fimg2d_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct fimg2d_platdata *pdata;
+	int ret;
+
+	pdata = to_fimg2d_plat(&pdev->dev);
+	if (!pdata) {
+		printk(KERN_ERR "FIMG2D failed to get platform data\n");
+		ret = -ENOMEM;
+		goto err_plat;
+	}
+
+	/* global structure */
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		printk(KERN_ERR "FIMG2D failed to allocate memory for controller\n");
+		ret = -ENOMEM;
+		goto err_plat;
+	}
+
+	/* setup global info */
+	ret = fimg2d_setup_controller(info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to setup controller\n");
+		goto err_setup;
+	}
+	info->dev = &pdev->dev;
+
+	/* memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "FIMG2D failed to get resource\n");
+		ret = -ENOENT;
+		goto err_region;
+	}
+
+	info->mem = request_mem_region(res->start, resource_size(res),
+					pdev->name);
+	if (!info->mem) {
+		printk(KERN_ERR "FIMG2D failed to request memory region\n");
+		ret = -ENOMEM;
+		goto err_region;
+	}
+
+	/* ioremap */
+	info->regs = ioremap(res->start, resource_size(res));
+	if (!info->regs) {
+		printk(KERN_ERR "FIMG2D failed to ioremap for SFR\n");
+		ret = -ENOENT;
+		goto err_map;
+	}
+	fimg2d_debug("device name: %s base address: 0x%lx\n",
+			pdev->name, (unsigned long)res->start);
+
+	/* irq */
+	info->irq = platform_get_irq(pdev, 0);
+	if (!info->irq) {
+		printk(KERN_ERR "FIMG2D failed to get irq resource\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+	fimg2d_debug("irq: %d\n", info->irq);
+
+	ret = request_irq(info->irq, fimg2d_irq, IRQF_DISABLED, pdev->name, info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to request irq\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	ret = fimg2d_clk_setup(info);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to setup clk\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_enable(info->dev);
+	fimg2d_debug("enable runtime pm\n");
+#endif
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	/* To lock bus frequency in OPP mode */
+	info->bus_dev = dev_get("exynos-busfreq");
+#endif
+#endif
+	exynos_sysmmu_set_fault_handler(info->dev, fimg2d_sysmmu_fault_handler);
+	fimg2d_debug("register sysmmu page fault handler\n");
+
+	/* misc register */
+	ret = misc_register(&fimg2d_dev);
+	if (ret) {
+		printk(KERN_ERR "FIMG2D failed to register misc driver\n");
+		goto err_reg;
+	}
+
+	printk(KERN_INFO "Samsung Graphics 2D driver, (c) 2011 Samsung Electronics\n");
+	return 0;
+
+err_reg:
+	fimg2d_clk_release(info);
+
+err_clk:
+	free_irq(info->irq, NULL);
+
+err_irq:
+	iounmap(info->regs);
+
+err_map:
+	release_resource(info->mem);
+	kfree(info->mem);
+
+err_region:
+	destroy_workqueue(info->work_q);
+
+err_setup:
+	kfree(info);
+
+err_plat:
+	return ret;
+}
+
+static int fimg2d_remove(struct platform_device *pdev)
+{
+	free_irq(info->irq, NULL);
+
+	if (info->mem) {
+		iounmap(info->regs);
+		release_resource(info->mem);
+		kfree(info->mem);
+	}
+
+	destroy_workqueue(info->work_q);
+	misc_deregister(&fimg2d_dev);
+	kfree(info);
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(&pdev->dev);
+	fimg2d_debug("disable runtime pm\n");
+#endif
+
+	return 0;
+}
+
+static int fimg2d_suspend(struct device *dev)
+{
+	fimg2d_debug("suspend... start\n");
+	atomic_set(&info->suspended, 1);
+	while (1) {
+		if (fimg2d_queue_is_empty(&info->cmd_q))
+			break;
+
+		mdelay(2);
+	}
+	fimg2d_debug("suspend... done\n");
+	return 0;
+}
+
+static int fimg2d_resume(struct device *dev)
+{
+	fimg2d_debug("resume... start\n");
+	atomic_set(&info->suspended, 0);
+	fimg2d_debug("resume... done\n");
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int fimg2d_runtime_suspend(struct device *dev)
+{
+	fimg2d_debug("runtime suspend... done\n");
+	return 0;
+}
+
+static int fimg2d_runtime_resume(struct device *dev)
+{
+	fimg2d_debug("runtime resume... done\n");
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops fimg2d_pm_ops = {
+	.suspend		= fimg2d_suspend,
+	.resume			= fimg2d_resume,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_suspend	= fimg2d_runtime_suspend,
+	.runtime_resume		= fimg2d_runtime_resume,
+#endif
+};
+
+static struct platform_driver fimg2d_driver = {
+	.probe		= fimg2d_probe,
+	.remove		= fimg2d_remove,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "s5p-fimg2d",
+		.pm     = &fimg2d_pm_ops,
+	},
+};
+
+static int __init fimg2d_register(void)
+{
+	return platform_driver_register(&fimg2d_driver);
+}
+
+static void __exit fimg2d_unregister(void)
+{
+	platform_driver_unregister(&fimg2d_driver);
+}
+
+module_init(fimg2d_register);
+module_exit(fimg2d_unregister);
+
+MODULE_AUTHOR("Eunseok Choi <es10.choi@samsung.com>");
+MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
+MODULE_DESCRIPTION("Samsung Graphics 2D driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.c b/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.c
new file mode 100644
index 0000000..61e2d53
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.c
@@ -0,0 +1,118 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "fimg2d.h"
+#include "fimg2d_cache.h"
+#include "fimg2d_helper.h"
+
+void perf_print(struct fimg2d_context *ctx, int seq_no)
+{
+	int i;
+	long time;
+	struct fimg2d_perf *perf;
+
+	for (i = 0; i < MAX_PERF_DESCS; i++) {
+		perf = &ctx->perf[i];
+		if (perf->valid != 0x11)
+			continue;
+		time = elapsed_usec(ctx, i);
+		printk(KERN_INFO "[FIMG2D PERF (%8s)] ctx(0x%08x) seq(%d) "
+				"%8ld   usec\n",
+				perfname(i), (unsigned int)ctx, seq_no, time);
+	}
+	printk(KERN_INFO "[FIMG2D PERF **]\n");
+}
+
+void fimg2d_dump_command(struct fimg2d_bltcmd *cmd)
+{
+	int i;
+	struct fimg2d_param *p = &cmd->param;
+	struct fimg2d_image *img;
+	struct fimg2d_rect *r;
+	struct fimg2d_dma *c;
+
+	printk(KERN_INFO " op: %d\n", cmd->op);
+	printk(KERN_INFO " solid color: 0x%lx\n", p->solid_color);
+	printk(KERN_INFO " g_alpha: 0x%x\n", p->g_alpha);
+	printk(KERN_INFO " premultiplied: %d\n", p->premult);
+	if (p->dither)
+		printk(KERN_INFO " dither: %d\n", p->dither);
+	if (p->rotate)
+		printk(KERN_INFO " rotate: %d\n", p->rotate);
+	if (p->repeat.mode) {
+		printk(KERN_INFO " repeat: %d, pad color: 0x%lx\n",
+				p->repeat.mode, p->repeat.pad_color);
+	}
+	if (p->bluscr.mode) {
+		printk(KERN_INFO " bluescreen: %d, bs_color: 0x%lx "
+				"bg_color: 0x%lx\n",
+				p->bluscr.mode, p->bluscr.bs_color,
+				p->bluscr.bg_color);
+	}
+	if (p->scaling.mode) {
+		printk(KERN_INFO " scaling %d, s:%d,%d d:%d,%d\n",
+				p->scaling.mode,
+				p->scaling.src_w, p->scaling.src_h,
+				p->scaling.dst_w, p->scaling.dst_h);
+	}
+	if (p->clipping.enable) {
+		printk(KERN_INFO " clipping LT(%d,%d) RB(%d,%d) WH(%d,%d)\n",
+				p->clipping.x1, p->clipping.y1,
+				p->clipping.x2, p->clipping.y2,
+				rect_w(&p->clipping), rect_h(&p->clipping));
+	}
+
+	for (i = 0; i < MAX_IMAGES; i++) {
+		img = &cmd->image[i];
+		if (!img->addr.type)
+			continue;
+
+		r = &img->rect;
+
+		printk(KERN_INFO " %s type: %d addr: 0x%lx\n",
+				imagename(i), img->addr.type, img->addr.start);
+		if (img->plane2.type) {
+			printk(KERN_INFO " %s type: %d plane2: 0x%lx\n",
+					imagename(i), img->plane2.type,
+					img->plane2.start);
+		}
+		printk(KERN_INFO " %s width: %d height: %d "
+				"stride: %d order: %d format: %d\n",
+				imagename(i), img->width, img->height,
+				img->stride, img->order, img->fmt);
+		printk(KERN_INFO " %s rect LT(%d,%d) RB(%d,%d) WH(%d,%d)\n",
+				imagename(i), r->x1, r->y1, r->x2, r->y2,
+				rect_w(r), rect_h(r));
+
+		c = &cmd->dma[i].base;
+		if (c->size) {
+			printk(KERN_INFO " %s dma base addr: 0x%lx "
+					"size: 0x%x cached: 0x%x\n",
+					imagename(i), c->addr, c->size,
+					c->cached);
+		}
+
+		c = &cmd->dma[i].plane2;
+		if (c->size) {
+			printk(KERN_INFO " %s dma plane2 addr: 0x%lx "
+					"size: 0x%x cached: 0x%x\n",
+					imagename(i), c->addr, c->size,
+					c->cached);
+		}
+	}
+
+	if (cmd->dma_all)
+		printk(KERN_INFO " dma size all: 0x%x bytes\n", cmd->dma_all);
+
+	printk(KERN_INFO " ctx: %p seq_no(%u) sync(%d)\n",
+				cmd->ctx, cmd->seq_no, cmd->sync);
+}
diff --git a/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.h b/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.h
new file mode 100644
index 0000000..83f794c
--- /dev/null
+++ b/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.h
@@ -0,0 +1,117 @@
+/* linux/drivers/media/video/samsung/fimg2d4x/fimg2d_helper.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *	http://www.samsung.com/
+ *
+ * Samsung Graphics 2D driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __FIMG2D_HELPER_H
+#define __FIMG2D_HELPER_H
+
+#include <linux/sched.h>
+#include "fimg2d.h"
+
+#define rect_w(r)	((r)->x2 - (r)->x1)
+#define rect_h(r)	((r)->y2 - (r)->y1)
+
+static inline char *perfname(enum perf_desc id)
+{
+	switch (id) {
+	case PERF_INNERCACHE:
+		return "INNER$";
+	case PERF_OUTERCACHE:
+		return "OUTER$";
+	case PERF_BLIT:
+		return "BITBLT";
+	default:
+		return "";
+	}
+}
+
+static inline char *imagename(enum image_object image)
+{
+	switch (image) {
+	case IDST:
+		return "DST";
+	case ISRC:
+		return "SRC";
+	case IMSK:
+		return "MSK";
+	default:
+		return NULL;
+	}
+}
+
+static inline long elapsed_usec(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+#ifdef PERF_TIMEVAL
+	struct timeval *start = &perf->start;
+	struct timeval *end = &perf->end;
+	long sec, usec;
+
+	sec = end->tv_sec - start->tv_sec;
+	if (end->tv_usec >= start->tv_usec) {
+		usec = end->tv_usec - start->tv_usec;
+	} else {
+		usec = end->tv_usec + 1000000 - start->tv_usec;
+		sec--;
+	}
+	return sec * 1000000 + usec;
+#else
+	return (long)(perf->end - perf->start)/1000;
+#endif
+}
+
+static inline void perf_start(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+
+	if (!perf->valid) {
+#ifdef PERF_TIMEVAL
+		struct timeval time;
+		do_gettimeofday(&time);
+		perf->start = time;
+#else
+		long time;
+		perf->start = sched_clock();
+		time = perf->start / 1000;
+#endif
+		perf->valid = 0x01;
+	}
+}
+
+static inline void perf_end(struct fimg2d_context *ctx, enum perf_desc desc)
+{
+	struct fimg2d_perf *perf = &ctx->perf[desc];
+
+	if (perf->valid == 0x01) {
+#ifdef PERF_TIMEVAL
+		struct timeval time;
+		do_gettimeofday(&time);
+		perf->end = time;
+#else
+		long time;
+		perf->end = sched_clock();
+		time = perf->end / 1000;
+#endif
+		perf->valid |= 0x10;
+	}
+}
+
+static inline void perf_clear(struct fimg2d_context *ctx)
+{
+	int i;
+	for (i = 0; i < MAX_PERF_DESCS; i++)
+		ctx->perf[i].valid = 0;
+}
+
+void perf_print(struct fimg2d_context *ctx, int seq_no);
+void fimg2d_dump_command(struct fimg2d_bltcmd *cmd);
+
+#endif /* __FIMG2D_HELPER_H */
diff --git a/drivers/media/video/samsung/jpeg/Kconfig b/drivers/media/video/samsung/jpeg/Kconfig
new file mode 100644
index 0000000..35ba86d
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/Kconfig
@@ -0,0 +1,15 @@
+#
+# Configuration for JPEG
+#
+
+config VIDEO_JPEG
+	bool "Samsung JPEG driver"
+	depends on VIDEO_SAMSUNG
+	default n
+	---help---
+	  This is a JPEG for Samsung S5PV210 or S5PV310
+
+config VIDEO_JPEG_DEBUG
+	bool "print JPEG debug message"
+	depends on VIDEO_JPEG
+	default n
diff --git a/drivers/media/video/samsung/jpeg/Makefile b/drivers/media/video/samsung/jpeg/Makefile
new file mode 100644
index 0000000..0f166c9
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/Makefile
@@ -0,0 +1,10 @@
+#################################################
+# Makefile for JPEG
+# 2009 (C) Samsung Electronics
+# Author : Hyunmin Kwak <hyunmin.kwak@samsung.com>
+#################################################
+
+obj-$(CONFIG_VIDEO_JPEG)	+= jpeg_dev.o jpeg_mem.o jpeg_core.o jpeg_regs.o
+
+EXTRA_CFLAGS += -Idrivers/media/video
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_conf.h b/drivers/media/video/samsung/jpeg/jpeg_conf.h
new file mode 100644
index 0000000..a82d1f6
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_conf.h
@@ -0,0 +1,363 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_conf.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition Quantization Table for Jpeg encoder/docoder
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_CONF_H__
+#define __JPEG_CONF_H__
+
+/* coefficients of color space converter. */
+#define COEF1_RGB_2_YUV         0x4d971e
+#define COEF2_RGB_2_YUV         0x2c5783
+#define COEF3_RGB_2_YUV         0x836e13
+
+const unsigned char qtbl_luminance[4][64] = {
+#if 1
+	/* LSI Q-table has very high compression rate.
+	 * It does not satisfy the spec of Reliablity Test Group
+	 * belonging to TN. So We use the below Q-table.
+	 * - DSLIM
+	 */
+	{ /* Very high quality Customized  by Samsung TN */
+		0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x03, 0x03,
+		0x01, 0x01, 0x01, 0x01, 0x01, 0x03, 0x03, 0x03,
+		0x01, 0x01, 0x01, 0x01, 0x02, 0x03, 0x03, 0x03,
+		0x01, 0x01, 0x01, 0x01, 0x02, 0x04, 0x04, 0x03,
+		0x01, 0x01, 0x03, 0x04, 0x04, 0x06, 0x06, 0x04,
+		0x01, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x05,
+		0x02, 0x03, 0x04, 0x04, 0x05, 0x06, 0x06, 0x05,
+		0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05
+	},
+	{
+		0x03, 0x02, 0x02, 0x02, 0x03, 0x08, 0x0B, 0x10,
+		0x03, 0x02, 0x02, 0x02, 0x03, 0x0F, 0x10, 0x0E,
+		0x02, 0x02, 0x02, 0x03, 0x08, 0x0E, 0x13, 0x0E,
+		0x02, 0x02, 0x02, 0x04, 0x0C, 0x18, 0x17, 0x10,
+		0x03, 0x07, 0x0E, 0x11, 0x17, 0x1F, 0x23, 0x1B,
+		0x03, 0x07, 0x0E, 0x11, 0x17, 0x1F, 0x23, 0x1B,
+		0x0C, 0x11, 0x16, 0x19, 0x1F, 0x1C, 0x1C, 0x1E,
+		0x14, 0x1B, 0x1C, 0x1D, 0x23, 0x20, 0x1F, 0x1E
+	},
+	{
+		0x05, 0x02, 0x02, 0x05, 0x0A, 0x16, 0x1E, 0x25,
+		0x02, 0x02, 0x03, 0x07, 0x0C, 0x23, 0x25, 0x21,
+		0x03, 0x02, 0x05, 0x0A, 0x16, 0x22, 0x2B, 0x22,
+		0x03, 0x05, 0x09, 0x0E, 0x1E, 0x39, 0x33, 0x26,
+		0x06, 0x09, 0x14, 0x22, 0x2A, 0x38, 0x44, 0x31,
+		0x0A, 0x12, 0x21, 0x18, 0x34, 0x45, 0x4B, 0x3C,
+		0x1D, 0x28, 0x32, 0x38, 0x44, 0x52, 0x51, 0x42,
+		0x2D, 0x3C, 0x3E, 0x40, 0x4A, 0x42, 0x44, 0x41,
+	},
+	{/* LSI - level 1 - high quality */
+		8, 6, 6, 8, 12, 14, 16, 17,
+		6, 6, 6, 8, 10, 13, 12, 15,
+		6, 6, 7, 8, 13, 14, 18, 24,
+		8, 8, 8, 14, 13, 19, 24, 35,
+		12, 10, 13, 13, 20, 26, 34, 39,
+		14, 13, 14, 19, 26, 34, 39, 39,
+		16, 12, 18, 24, 34, 39, 39, 39,
+		17, 15, 24, 35, 39, 39, 39, 39
+	},
+#else
+	{/* level 1 - high quality */
+		8, 6, 6, 8, 12, 14, 16, 17,
+		6, 6, 6, 8, 10, 13, 12, 15,
+		6, 6, 7, 8, 13, 14, 18, 24,
+		8, 8, 8, 14, 13, 19, 24, 35,
+		12, 10, 13, 13, 20, 26, 34, 39,
+		14, 13, 14, 19, 26, 34, 39, 39,
+		16, 12, 18, 24, 34, 39, 39, 39,
+		17, 15, 24, 35, 39, 39, 39, 39
+	},
+	{/* level 2 */
+		12, 8, 8, 12, 17, 21, 24, 23,
+		8, 9, 9, 11, 15, 19, 18, 23,
+		8, 9, 10, 12, 19, 20, 27, 36,
+		12, 11, 12, 21, 20, 28, 36, 53,
+		17, 15, 19, 20, 30, 39, 51, 59,
+		21, 19, 20, 28, 39, 51, 59, 59,
+		24, 18, 27, 36, 51, 59, 59, 59,
+		23, 23, 36, 53, 59, 59, 59, 59
+	},
+	{/* level 3 */
+		16, 11, 11, 16, 23, 27, 31, 30,
+		11, 12, 12, 15, 20, 23, 23, 30,
+		11, 12, 13, 16, 23, 26, 35, 47,
+		16, 15, 16, 23, 26, 37, 47, 64,
+		23, 20, 23, 26, 39, 51, 64, 64,
+		27, 23, 26, 37, 51, 64, 64, 64,
+		31, 23, 35, 47, 64, 64, 64, 64,
+		30, 30, 47, 64, 64, 64, 64, 64
+
+	},
+	{/*level 4 - low quality */
+		20, 16, 25, 39, 50, 46, 62, 68,
+		16, 18, 23, 38, 38, 53, 65, 68,
+		25, 23, 31, 38, 53, 65, 68, 68,
+		39, 38, 38, 53, 65, 68, 68, 68,
+		50, 38, 53, 65, 68, 68, 68, 68,
+		46, 53, 65, 68, 68, 68, 68, 68,
+		62, 65, 68, 68, 68, 68, 68, 68,
+		68, 68, 68, 68, 68, 68, 68, 68
+	}
+#endif
+};
+
+const unsigned char qtbl_chrominance[4][64] = {
+#if 1
+	/* LSI Q-table has very high compression rate.
+	 * It does not satisfy the spec of Reliablity Test Group
+	 * belonging to TN. So We use the below Q-table.
+	 * - DSLIM
+	 */
+	{ /* Very high quality Customized  by Samsung TN */
+		0x01, 0x01, 0x02, 0x04, 0x06, 0x11, 0x11, 0x11,
+		0x01, 0x01, 0x02, 0x04, 0x08, 0x11, 0x11, 0x11,
+		0x02, 0x02, 0x03, 0x04, 0x11, 0x11, 0x11, 0x11,
+		0x04, 0x04, 0x04, 0x05, 0x11, 0x11, 0x11, 0x11,
+		0x06, 0x08, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+		0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+		0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+		0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11
+	},
+	{
+		0x02, 0x02, 0x05, 0x0B, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x02, 0x02, 0x03, 0x12, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x03, 0x03, 0x10, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x0B, 0x14, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+		0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E,
+	},
+	{
+		0x05, 0x06, 0x0A, 0x1B, 0x41, 0x41, 0x41, 0x41,
+		0x06, 0x08, 0x0C, 0x29, 0x41, 0x41, 0x41, 0x41,
+		0x09, 0x0C, 0x22, 0x41, 0x41, 0x41, 0x41, 0x41,
+		0x1B, 0x29, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
+		0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
+		0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
+		0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
+		0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
+	},
+	{/* LSI - level 1 - high quality */
+		9, 8, 9, 11, 14, 17, 19, 24,
+		8, 10, 9, 11, 14, 13, 17, 22,
+		9, 9, 13, 14, 13, 15, 23, 26,
+		11, 11, 14, 14, 15, 20, 26, 33,
+		14, 14, 13, 15, 20, 24, 33, 39,
+		17, 13, 15, 20, 24, 32, 39, 39,
+		19, 17, 23, 26, 33, 39, 39, 39,
+		24, 22, 26, 33, 39, 39, 39, 39
+	},
+#else
+	{/* level 1 - high quality */
+		9, 8, 9, 11, 14, 17, 19, 24,
+		8, 10, 9, 11, 14, 13, 17, 22,
+		9, 9, 13, 14, 13, 15, 23, 26,
+		11, 11, 14, 14, 15, 20, 26, 33,
+		14, 14, 13, 15, 20, 24, 33, 39,
+		17, 13, 15, 20, 24, 32, 39, 39,
+		19, 17, 23, 26, 33, 39, 39, 39,
+		24, 22, 26, 33, 39, 39, 39, 39
+	},
+	{/* level 2 */
+		13, 11, 13, 16, 20, 20, 29, 37,
+		11, 14, 14, 14, 16, 20, 26, 32,
+		13, 14, 15, 17, 20, 23, 35, 40,
+		16, 14, 17, 21, 23, 30, 40, 50,
+		20, 16, 20, 23, 30, 37, 50, 59,
+		20, 20, 23, 30, 37, 48, 59, 59,
+		29, 26, 35, 40, 50, 59, 59, 59,
+		37, 32, 40, 50, 59, 59, 59, 59
+	},
+	{/* level 3 */
+		17, 15, 17, 21, 20, 26, 38, 48,
+		15, 19, 18, 17, 20, 26, 35, 43,
+		17, 18, 20, 22, 26, 30, 46, 53,
+		21, 17, 22, 28, 30, 39, 53, 64,
+		20, 20, 26, 30, 39, 48, 64, 64,
+		26, 26, 30, 39, 48, 63, 64, 64,
+		38, 35, 46, 53, 64, 64, 64, 64,
+		48, 43, 53, 64, 64, 64, 64, 64
+
+
+	},
+	{/*level 4 - low quality */
+		21, 25, 32, 38, 54, 68, 68, 68,
+		25, 28, 24, 38, 54, 68, 68, 68,
+		32, 24, 32, 43, 66, 68, 68, 68,
+		38, 38, 43, 53, 68, 68, 68, 68,
+		54, 54, 66, 68, 68, 68, 68, 68,
+		68, 68, 68, 68, 68, 68, 68, 68,
+		68, 68, 68, 68, 68, 68, 68, 68,
+		68, 68, 68, 68, 68, 68, 68, 68
+
+	}
+#endif
+};
+
+const unsigned char qtbl0[64] = {
+	0x10, 0x0B, 0x0A, 0x10, 0x18, 0x28, 0x33, 0x3D,
+	0x0C, 0x0C, 0x0E, 0x13, 0x1A, 0x3A, 0x3C, 0x37,
+	0x0E, 0x0D, 0x10, 0x18, 0x28, 0x39, 0x45, 0x38,
+	0x0E, 0x11, 0x16, 0x1D, 0x33, 0x57, 0x50, 0x3E,
+	0x12, 0x16, 0x25, 0x38, 0x44, 0x6D, 0x67, 0x4D,
+	0x18, 0x23, 0x37, 0x40, 0x51, 0x68, 0x71, 0x5C,
+	0x31, 0x40, 0x4E, 0x57, 0x67, 0x79, 0x78, 0x65,
+	0x48, 0x5C, 0x5F, 0x62, 0x70, 0x64, 0x67, 0x63
+};
+
+/* Added Quantization Table */
+const unsigned char std_chrominance_quant_tbl_plus[64] = {
+	0x11, 0x12, 0x18, 0x2F, 0x63, 0x63, 0x63, 0x63,
+	0x12, 0x15, 0x1A, 0x42, 0x63, 0x63, 0x63, 0x63,
+	0x18, 0x1A, 0x38, 0x63, 0x63, 0x63, 0x63, 0x63,
+	0x2F, 0x42, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
+	0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
+	0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
+	0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
+	0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63
+};
+
+/* Quantization Table0 */
+unsigned char std_luminance_quant_tbl[64] = {
+	1,   1,   2,   1,   1,   2,   2,   2,
+	2,   3,   2,   2,   3,   3,   6,   4,
+	3,   3,   3,   3,   7,   5,   8,   4,
+	6,   8,   8,  10,   9,   8,   7,  11,
+	8,  10,  14,  13,  11,  10,  10,  12,
+	10,   8,   8,  11,  16,  12,  12,  13,
+	15,  15,  15,  15,   9,  11,  16,  17,
+	15,  14,  17,  13,  14,  14,  14,   1
+};
+
+/* uantization Table1 */
+unsigned char std_chrominance_quant_tbl[64] = {
+	4,   4,   4,   5,   4,   5,   9,   5,
+	5,   9,  15,  10,   8,  10,  15,  26,
+	19,   9,   9,  19,  26,  26,  26,  26,
+	13,  26,  26,  26,  26,  26,  26,  26,
+	26,  26,  26,  26,  26,  26,  26,  26,
+	26,  26,  26,  26,  26,  26,  26,  26,
+	26,  26,  26,  26,  26,  26,  26,  26,
+	26,  26,  26,  26,  26,  26,  26,  26
+};
+
+/* Huffman Table */
+unsigned char hdctbl0[16]  = {0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0};
+unsigned char hdctblg0[12] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb};
+
+unsigned char hactbl0[16] = {0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d};
+const unsigned char hactblg0[162] = {
+	0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
+	0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+	0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
+	0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
+	0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
+	0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
+	0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+	0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+	0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+	0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
+	0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+	0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
+	0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
+	0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
+	0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
+	0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
+	0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+	0xf9, 0xfa
+};
+
+/* Huffman Table0 */
+unsigned char len_dc_luminance[16] = {
+	0, 1, 5, 1, 1, 1, 1, 1,
+	1, 0, 0, 0, 0, 0, 0, 0
+};
+
+unsigned char val_dc_luminance[12] = {
+	0, 1, 2, 3, 4, 5,
+	6, 7, 8, 9, 10, 11
+};
+
+unsigned char len_ac_luminance[16] = {
+	0, 2, 1, 3, 3, 2, 4, 3,
+	5, 5, 4, 4, 0, 0, 1, 0x7d
+};
+
+unsigned char val_ac_luminance[162] = {
+	0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
+	0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+	0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
+	0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
+	0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
+	0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
+	0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+	0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+	0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+	0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
+	0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+	0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
+	0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
+	0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
+	0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
+	0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
+	0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+	0xf9, 0xfa
+};
+
+/* Huffman Table1 */
+unsigned char len_dc_chrominance[16] = {
+	0, 3, 1, 1, 1, 1, 1, 1,
+	1, 1, 1, 0, 0, 0, 0, 0
+};
+
+unsigned char val_dc_chrominance[12] = {
+	0, 1, 2, 3, 4, 5,
+	6, 7, 8, 9, 10, 11
+};
+
+unsigned char len_ac_chrominance[16] = {
+	0, 2, 1, 2, 4, 4, 3, 4,
+	7, 5, 4, 4, 0, 1, 2, 0x77
+};
+
+unsigned char val_ac_chrominance[162] = {
+	0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,
+	0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+	0x13, 0x22, 0x32, 0x81, 0x81, 0x08, 0x14, 0x42,
+	0x91, 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52,
+	0xf0, 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24,
+	0x34, 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a,
+	0x26, 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37,
+	0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47,
+	0x48, 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57,
+	0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67,
+	0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77,
+	0x78, 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86,
+	0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4,
+	0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3,
+	0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2,
+	0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca,
+	0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9,
+	0xda, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
+	0xe9, 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
+	0xf8, 0xf9
+};
+
+#endif /* __JPEG_CONF_H__ */
diff --git a/drivers/media/video/samsung/jpeg/jpeg_core.c b/drivers/media/video/samsung/jpeg/jpeg_core.c
new file mode 100644
index 0000000..86203ca
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_core.c
@@ -0,0 +1,126 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_core.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Core file for operation of the jpeg driver encoder/docoder
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+
+#include "jpeg_core.h"
+#include "jpeg_regs.h"
+#include "jpeg_mem.h"
+
+int jpeg_int_pending(struct jpeg_control *ctrl)
+{
+	unsigned int	int_status;
+
+	int_status = jpeg_get_int_status(ctrl->reg_base);
+	jpeg_dbg("state(%d)\n", int_status);
+
+	jpeg_clear_int(ctrl->reg_base);
+
+	return int_status;
+}
+
+int jpeg_set_dec_param(struct jpeg_control *ctrl)
+{
+	if (ctrl) {
+		jpeg_sw_reset(ctrl->reg_base);
+	} else {
+		jpeg_err("jpeg ctrl is NULL\n");
+		return -1;
+	}
+
+	jpeg_set_clk_power_on(ctrl->reg_base);
+	jpeg_set_mode(ctrl->reg_base, 1);
+	jpeg_set_dec_out_fmt(ctrl->reg_base, ctrl->dec_param.out_fmt);
+	jpeg_set_stream_buf(&ctrl->mem.stream_data_addr, ctrl->mem.base);
+	jpeg_set_stream_addr(ctrl->reg_base, ctrl->mem.stream_data_addr);
+	jpeg_set_frame_buf(&ctrl->mem.frame_data_addr, ctrl->mem.base);
+	jpeg_set_frame_addr(ctrl->reg_base, ctrl->mem.frame_data_addr);
+
+	jpeg_info("jpeg_set_dec_param fmt(%d)\
+			img_addr(0x%08x) jpeg_addr(0x%08x)\n",
+			ctrl->dec_param.out_fmt,
+			ctrl->mem.frame_data_addr,
+			ctrl->mem.stream_data_addr);
+
+	return 0;
+}
+
+int jpeg_set_enc_param(struct jpeg_control *ctrl)
+{
+	if (ctrl) {
+		jpeg_sw_reset(ctrl->reg_base);
+	} else {
+		jpeg_err("jpeg ctrl is NULL\n");
+		return -1;
+	}
+
+	jpeg_set_clk_power_on(ctrl->reg_base);
+	jpeg_set_mode(ctrl->reg_base, 0);
+	jpeg_set_enc_in_fmt(ctrl->reg_base, ctrl->enc_param.in_fmt);
+	jpeg_set_enc_out_fmt(ctrl->reg_base, ctrl->enc_param.out_fmt);
+	jpeg_set_enc_dri(ctrl->reg_base, 2);
+	jpeg_set_frame_size(ctrl->reg_base,
+		ctrl->enc_param.width, ctrl->enc_param.height);
+	jpeg_set_stream_buf(&ctrl->mem.stream_data_addr, ctrl->mem.base);
+	jpeg_set_stream_addr(ctrl->reg_base, ctrl->mem.stream_data_addr);
+	jpeg_set_frame_buf(&ctrl->mem.frame_data_addr, ctrl->mem.base);
+	jpeg_set_frame_addr(ctrl->reg_base, ctrl->mem.frame_data_addr);
+	jpeg_set_enc_coef(ctrl->reg_base);
+	jpeg_set_enc_qtbl(ctrl->reg_base, ctrl->enc_param.quality);
+	jpeg_set_enc_htbl(ctrl->reg_base);
+
+	return 0;
+}
+
+int jpeg_exe_dec(struct jpeg_control *ctrl)
+{
+
+	jpeg_start_decode(ctrl->reg_base);
+
+	if (interruptible_sleep_on_timeout(&ctrl->wq, INT_TIMEOUT) == 0)
+		jpeg_err("waiting for interrupt is timeout\n");
+
+
+	if (ctrl->irq_ret != OK_ENC_OR_DEC) {
+		jpeg_err("jpeg decode error(%d)\n", ctrl->irq_ret);
+		return -1;
+	}
+
+	jpeg_get_frame_size(ctrl->reg_base,
+		&ctrl->dec_param.width, &ctrl->dec_param.height);
+
+	ctrl->dec_param.in_fmt = jpeg_get_stream_fmt(ctrl->reg_base);
+
+	jpeg_info("decode img in_fmt(%d) width(%d) height(%d)\n",
+			ctrl->dec_param.in_fmt , ctrl->dec_param.width,
+			ctrl->dec_param.height);
+	return 0;
+}
+
+int jpeg_exe_enc(struct jpeg_control *ctrl)
+{
+
+	jpeg_start_encode(ctrl->reg_base);
+
+	if (interruptible_sleep_on_timeout(&ctrl->wq, INT_TIMEOUT) == 0)
+		jpeg_err("waiting for interrupt is timeout\n");
+
+	if (ctrl->irq_ret != OK_ENC_OR_DEC) {
+		jpeg_err("jpeg encode error(%d)\n", ctrl->irq_ret);
+		return -1;
+	}
+
+	ctrl->enc_param.size = jpeg_get_stream_size(ctrl->reg_base);
+
+	return 0;
+}
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_core.h b/drivers/media/video/samsung/jpeg/jpeg_core.h
new file mode 100644
index 0000000..73c44e2
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_core.h
@@ -0,0 +1,138 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition for core file of the jpeg operation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_CORE_H__
+#define __JPEG_CORE_H__
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+
+#include "jpeg_mem.h"
+
+#define INT_TIMEOUT		1000
+
+enum jpeg_result {
+	OK_ENC_OR_DEC,
+	ERR_ENC_OR_DEC,
+	ERR_UNKNOWN,
+};
+
+enum  jpeg_img_quality_level {
+	QUALITY_LEVEL_1 = 0,	/* high */
+	QUALITY_LEVEL_2,
+	QUALITY_LEVEL_3,
+	QUALITY_LEVEL_4,	/* low */
+};
+
+/* raw data image format */
+enum jpeg_frame_format {
+	YUV_422,	/* decode output, encode input */
+	YUV_420,	/* decode output, encode output */
+	RGB_565,	/* encode input */
+};
+
+/* jpeg data format */
+enum jpeg_stream_format {
+	JPEG_422,	/* decode input, encode output */
+	JPEG_420,	/* decode input, encode output */
+	JPEG_444,	/* decode input*/
+	JPEG_GRAY,	/* decode input*/
+	JPEG_RESERVED,
+};
+
+struct jpeg_dec_param {
+	unsigned int width;
+	unsigned int height;
+	unsigned int size;
+	enum jpeg_stream_format in_fmt;
+	enum jpeg_frame_format out_fmt;
+};
+
+struct jpeg_enc_param {
+	unsigned int width;
+	unsigned int height;
+	unsigned int size;
+	enum jpeg_frame_format in_fmt;
+	enum jpeg_stream_format out_fmt;
+	enum jpeg_img_quality_level quality;
+};
+
+struct jpeg_control {
+	struct clk		*clk;
+	atomic_t		in_use;
+	struct mutex		lock;
+	int			irq_no;
+	enum jpeg_result	irq_ret;
+	wait_queue_head_t	wq;
+	void __iomem		*reg_base;	/* register i/o */
+	struct jpeg_mem		mem;		/* for reserved memory */
+	struct jpeg_dec_param	dec_param;
+	struct jpeg_enc_param	enc_param;
+};
+
+enum jpeg_log {
+	JPEG_LOG_DEBUG		= 0x1000,
+	JPEG_LOG_INFO		= 0x0100,
+	JPEG_LOG_WARN		= 0x0010,
+	JPEG_LOG_ERR		= 0x0001,
+};
+
+/* debug macro */
+#define JPEG_LOG_DEFAULT	(JPEG_LOG_WARN | JPEG_LOG_ERR)
+
+#define JPEG_DEBUG(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_DEBUG)			\
+			printk(KERN_DEBUG "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define JPEG_INFO(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_INFO)			\
+			printk(KERN_INFO "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define JPEG_WARN(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_WARN)			\
+			printk(KERN_WARNING "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define JPEG_ERROR(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_ERR)			\
+			printk(KERN_ERR "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define jpeg_dbg(fmt, ...)		JPEG_DEBUG(fmt, ##__VA_ARGS__)
+#define jpeg_info(fmt, ...)		JPEG_INFO(fmt, ##__VA_ARGS__)
+#define jpeg_warn(fmt, ...)		JPEG_WARN(fmt, ##__VA_ARGS__)
+#define jpeg_err(fmt, ...)		JPEG_ERROR(fmt, ##__VA_ARGS__)
+
+/*=====================================================================*/
+int jpeg_int_pending(struct jpeg_control *ctrl);
+int jpeg_set_dec_param(struct jpeg_control *ctrl);
+int jpeg_set_enc_param(struct jpeg_control *ctrl);
+int jpeg_exe_dec(struct jpeg_control *ctrl);
+int jpeg_exe_enc(struct jpeg_control *ctrl);
+
+
+#endif /*__JPEG_CORE_H__*/
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_dev.c b/drivers/media/video/samsung/jpeg/jpeg_dev.c
new file mode 100644
index 0000000..4038fd2
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_dev.c
@@ -0,0 +1,556 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Core file for Samsung Jpeg Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/vmalloc.h>
+#include <asm/page.h>
+#include <linux/sched.h>
+
+#include <plat/regs_jpeg.h>
+#include <mach/irqs.h>
+#if defined(CONFIG_CPU_S5PV210)
+#include <mach/pd.h>
+#endif
+
+#if defined(CONFIG_S5P_SYSMMU_JPEG)
+#include <plat/sysmmu.h>
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+
+#include "jpeg_core.h"
+#include "jpeg_dev.h"
+#include "jpeg_mem.h"
+
+struct jpeg_control *jpeg_ctrl;
+static struct device *jpeg_pm;
+
+static int jpeg_open(struct inode *inode, struct file *file)
+{
+	int ret;
+	int in_use;
+
+	mutex_lock(&jpeg_ctrl->lock);
+
+	in_use = atomic_read(&jpeg_ctrl->in_use);
+
+	if (in_use > JPEG_MAX_INSTANCE) {
+		ret = -EBUSY;
+		goto resource_busy;
+	} else {
+		atomic_inc(&jpeg_ctrl->in_use);
+		jpeg_info("jpeg driver opened.\n");
+	}
+
+	mutex_unlock(&jpeg_ctrl->lock);
+#if defined(CONFIG_CPU_S5PV210)
+	ret = s5pv210_pd_enable("jpeg_pd");
+	if (ret < 0) {
+		jpeg_err("failed to enable jpeg power domain\n");
+		return -EINVAL;
+	}
+#endif
+
+	/* clock enable */
+	clk_enable(jpeg_ctrl->clk);
+
+	file->private_data = (struct jpeg_control *)jpeg_ctrl;
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_get_sync(jpeg_pm);
+#endif
+
+	return 0;
+resource_busy:
+	mutex_unlock(&jpeg_ctrl->lock);
+	return ret;
+}
+
+static int jpeg_release(struct inode *inode, struct file *file)
+{
+	atomic_dec(&jpeg_ctrl->in_use);
+
+	jpeg_mem_free();
+
+	clk_disable(jpeg_ctrl->clk);
+
+#if defined(CONFIG_CPU_S5PV210)
+	if (s5pv210_pd_disable("jpeg_pd") < 0) {
+		jpeg_err("failed to disable jpeg power domain\n");
+		return -EINVAL;
+	}
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_put_sync(jpeg_pm);
+#endif
+
+	return 0;
+}
+
+static long jpeg_ioctl(struct file *file,
+			unsigned int cmd, unsigned long arg)
+{
+	int ret;
+	struct jpeg_control	*ctrl;
+
+	ctrl  = (struct jpeg_control *)file->private_data;
+	if (!ctrl) {
+		jpeg_err("jpeg invalid input argument\n");
+		return -1;
+	}
+
+	switch (cmd) {
+
+	case IOCTL_JPEG_DEC_EXE:
+		ret = copy_from_user(&ctrl->dec_param,
+			(struct jpeg_dec_param *)arg,
+			sizeof(struct jpeg_dec_param));
+
+		jpeg_exe_dec(ctrl);
+		ret = copy_to_user((void *)arg,
+			(void *) &ctrl->dec_param,
+			sizeof(struct jpeg_dec_param));
+		break;
+
+	case IOCTL_JPEG_ENC_EXE:
+		ret = copy_from_user(&ctrl->enc_param,
+			(struct jpeg_enc_param *)arg,
+			sizeof(struct jpeg_enc_param));
+
+		jpeg_exe_enc(ctrl);
+		ret = copy_to_user((void *)arg,
+			(void *) &ctrl->enc_param,
+			sizeof(struct jpeg_enc_param));
+		break;
+
+	case IOCTL_GET_DEC_IN_BUF:
+	case IOCTL_GET_ENC_OUT_BUF:
+		return jpeg_get_stream_buf(arg);
+
+	case IOCTL_GET_DEC_OUT_BUF:
+	case IOCTL_GET_ENC_IN_BUF:
+		return jpeg_get_frame_buf(arg);
+
+	case IOCTL_GET_PHYADDR:
+		return jpeg_ctrl->mem.frame_data_addr;
+
+	case IOCTL_GET_PHYMEM_BASE:
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		if (copy_to_user((void *)arg, &jpeg_ctrl->mem.base, sizeof(unsigned int))) {
+			jpeg_err("IOCTL_GET_PHYMEM_BASE:::copy_to_user error\n");
+			return -1;
+		}
+		return 0;
+#else
+		return -1;
+#endif
+
+	case IOCTL_GET_PHYMEM_SIZE:
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG
+		ret = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * 1024;
+		if (copy_to_user((void *)arg, &ret, sizeof(unsigned int))) {
+			jpeg_err("IOCTL_GET_PHYMEM_SIZE:::copy_to_user error\n");
+			return -1;
+		}
+		return 0;
+#else
+		return -1;
+#endif
+
+	case IOCTL_SET_DEC_PARAM:
+		ret = copy_from_user(&ctrl->dec_param,
+			(struct jpeg_dec_param *)arg,
+			sizeof(struct jpeg_dec_param));
+
+		ret = jpeg_set_dec_param(ctrl);
+
+		break;
+
+	case IOCTL_SET_ENC_PARAM:
+		ret = copy_from_user(&ctrl->enc_param,
+			(struct jpeg_enc_param *)arg,
+			sizeof(struct jpeg_enc_param));
+
+		ret = jpeg_set_enc_param(ctrl);
+		break;
+
+	default:
+		break;
+	}
+	return 0;
+}
+
+int jpeg_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG)
+#if !defined(CONFIG_S5P_VMEM)
+	unsigned long	page_frame_no;
+	unsigned long	start;
+	unsigned long	size;
+	char		*ptr;	/* vmalloc */
+
+	size = vma->vm_end - vma->vm_start;
+	ptr = (char *)jpeg_ctrl->mem.base;
+	start = 0;
+
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	while (size > 0) {
+		page_frame_no = vmalloc_to_pfn(ptr);
+		if (remap_pfn_range(vma, vma->vm_start + start, page_frame_no,
+			PAGE_SIZE, vma->vm_page_prot)) {
+			jpeg_err("failed to remap jpeg pfn range.\n");
+			return -ENOMEM;
+		}
+
+		start += PAGE_SIZE;
+		ptr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+#endif /* CONFIG_S5P_VMEM */
+#else
+	unsigned long	page_frame_no;
+	unsigned long	size;
+	int		ret;
+
+	size = vma->vm_end - vma->vm_start;
+
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	page_frame_no = __phys_to_pfn(jpeg_ctrl->mem.base);
+	ret = remap_pfn_range(vma, vma->vm_start, page_frame_no,
+					size, vma->vm_page_prot);
+	if (ret != 0) {
+		jpeg_err("failed to remap jpeg pfn range.\n");
+		return -ENOMEM;
+	}
+#endif /* SYSMMU_JPEG_ON */
+
+	return 0;
+}
+
+static const struct file_operations jpeg_fops = {
+	.owner = THIS_MODULE,
+	.open =	jpeg_open,
+	.release = jpeg_release,
+	.unlocked_ioctl = jpeg_ioctl,
+	.mmap =	jpeg_mmap,
+};
+
+static struct miscdevice jpeg_miscdev = {
+	.minor = JPEG_MINOR_NUMBER,
+	.name =	JPEG_NAME,
+	.fops =	&jpeg_fops,
+};
+
+static irqreturn_t jpeg_irq(int irq, void *dev_id)
+{
+	unsigned int int_status;
+	struct jpeg_control *ctrl = (struct jpeg_control *) dev_id;
+
+	int_status = jpeg_int_pending(ctrl);
+
+	if (int_status) {
+		switch (int_status) {
+		case 0x40:
+			ctrl->irq_ret = OK_ENC_OR_DEC;
+			break;
+		case 0x20:
+			ctrl->irq_ret = ERR_ENC_OR_DEC;
+			break;
+		default:
+			ctrl->irq_ret = ERR_UNKNOWN;
+		}
+		wake_up_interruptible(&ctrl->wq);
+	} else {
+		ctrl->irq_ret = ERR_UNKNOWN;
+		wake_up_interruptible(&ctrl->wq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int jpeg_setup_controller(struct jpeg_control *ctrl)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG)
+	s5p_sysmmu_enable(jpeg_pm);
+	jpeg_dbg("sysmmu on\n");
+	/* jpeg hw uses kernel virtual address */
+	s5p_sysmmu_set_tablebase_pgd(jpeg_pm, __pa(swapper_pg_dir));
+#endif
+	atomic_set(&ctrl->in_use, 0);
+	mutex_init(&ctrl->lock);
+	init_waitqueue_head(&ctrl->wq);
+
+	return 0;
+}
+
+static int jpeg_probe(struct platform_device *pdev)
+{
+	struct	resource *res;
+	int	ret;
+
+	/* global structure */
+	jpeg_ctrl = kzalloc(sizeof(*jpeg_ctrl), GFP_KERNEL);
+	if (!jpeg_ctrl) {
+		dev_err(&pdev->dev, "%s: not enough memory\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	/* setup jpeg control */
+	ret = jpeg_setup_controller(jpeg_ctrl);
+	if (ret) {
+		jpeg_err("failed to setup controller\n");
+		goto err_setup;
+	}
+
+	/* memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		jpeg_err("failed to get jpeg memory region resource\n");
+		ret = -ENOENT;
+		goto err_res;
+	}
+
+	res = request_mem_region(res->start,
+				res->end - res->start + 1, pdev->name);
+	if (!res) {
+		jpeg_err("failed to request jpeg io memory region\n");
+		ret = -ENOMEM;
+		goto err_region;
+	}
+
+	/* ioremap */
+	jpeg_ctrl->reg_base = ioremap(res->start, res->end - res->start + 1);
+	if (!jpeg_ctrl->reg_base) {
+		jpeg_err("failed to remap jpeg io region\n");
+		ret = -ENOENT;
+		goto err_map;
+	}
+
+	/* irq */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		jpeg_err("failed to request jpeg irq resource\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	jpeg_ctrl->irq_no = res->start;
+	ret = request_irq(jpeg_ctrl->irq_no, (void *)jpeg_irq,
+			IRQF_DISABLED, pdev->name, jpeg_ctrl);
+	if (ret != 0) {
+		jpeg_err("failed to jpeg request irq\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	/* clock */
+	jpeg_ctrl->clk = clk_get(&pdev->dev, "jpeg");
+	if (IS_ERR(jpeg_ctrl->clk)) {
+		jpeg_err("failed to find jpeg clock source\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+	ret = jpeg_init_mem(&pdev->dev, &jpeg_ctrl->mem.base);
+	if (ret != 0) {
+		jpeg_err("failed to init. jpeg mem");
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	ret = misc_register(&jpeg_miscdev);
+	if (ret) {
+		jpeg_err("failed to register misc driver\n");
+		goto err_reg;
+	}
+
+	jpeg_pm = &pdev->dev;
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_enable(jpeg_pm);
+#endif
+	return 0;
+
+err_reg:
+	clk_put(jpeg_ctrl->clk);
+err_mem:
+err_clk:
+	free_irq(jpeg_ctrl->irq_no, NULL);
+err_irq:
+	iounmap(jpeg_ctrl->reg_base);
+err_map:
+err_region:
+	kfree(res);
+err_res:
+	mutex_destroy(&jpeg_ctrl->lock);
+err_setup:
+	kfree(jpeg_ctrl);
+err_alloc:
+	return ret;
+
+}
+
+static int jpeg_remove(struct platform_device *dev)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG)
+	s5p_sysmmu_disable(jpeg_pm);
+	jpeg_dbg("sysmmu off\n");
+#endif
+	free_irq(jpeg_ctrl->irq_no, dev);
+	mutex_destroy(&jpeg_ctrl->lock);
+	iounmap(jpeg_ctrl->reg_base);
+
+	kfree(jpeg_ctrl);
+	misc_deregister(&jpeg_miscdev);
+
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(jpeg_pm);
+#endif
+	return 0;
+}
+
+static int jpeg_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	/* clock disable */
+	clk_disable(jpeg_ctrl->clk);
+#if defined(CONFIG_CPU_S5PV210)
+	if (s5pv210_pd_disable("jpeg_pd") < 0) {
+		jpeg_err("failed to disable jpeg power domain\n");
+		return -EINVAL;
+	}
+#endif
+	return 0;
+}
+
+static int jpeg_resume(struct platform_device *pdev)
+{
+#if defined(CONFIG_CPU_S5PV210)
+	if (s5pv210_pd_enable("jpeg_pd") < 0) {
+		jpeg_err("failed to enable jpeg power domain\n");
+		return -EINVAL;
+	}
+#endif
+	/* clock enable */
+	clk_enable(jpeg_ctrl->clk);
+
+	return 0;
+}
+
+int jpeg_suspend_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+	pm_message_t state;
+
+	state.event = 0;
+	pdev = to_platform_device(dev);
+	ret = jpeg_suspend(pdev, state);
+
+	return 0;
+}
+
+int jpeg_resume_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = to_platform_device(dev);
+	ret = jpeg_resume(pdev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int jpeg_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int jpeg_runtime_resume(struct device *dev)
+{
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops jpeg_pm_ops = {
+	.suspend	= jpeg_suspend_pd,
+	.resume		= jpeg_resume_pd,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_suspend = jpeg_runtime_suspend,
+	.runtime_resume = jpeg_runtime_resume,
+#endif
+};
+static struct platform_driver jpeg_driver = {
+	.probe		= jpeg_probe,
+	.remove		= jpeg_remove,
+#if (!defined(CONFIG_S5PV310_DEV_PD) || !defined(CONFIG_PM_RUNTIME))
+	.suspend	= jpeg_suspend,
+	.resume		= jpeg_resume,
+#endif
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= JPEG_NAME,
+#if (defined(CONFIG_S5PV310_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+		.pm = &jpeg_pm_ops,
+#else
+		.pm = NULL,
+#endif
+	},
+};
+
+static int __init jpeg_init(void)
+{
+	printk("Initialize JPEG driver\n");
+
+	platform_driver_register(&jpeg_driver);
+
+	return 0;
+}
+
+static void __exit jpeg_exit(void)
+{
+	platform_driver_unregister(&jpeg_driver);
+}
+
+module_init(jpeg_init);
+module_exit(jpeg_exit);
+
+MODULE_AUTHOR("Hyunmin, Kwak <hyunmin.kwak@samsung.com>");
+MODULE_DESCRIPTION("JPEG Codec Device Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_dev.h b/drivers/media/video/samsung/jpeg/jpeg_dev.h
new file mode 100644
index 0000000..20fba9c
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_dev.h
@@ -0,0 +1,36 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_dev.h
+  *
+  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+  * http://www.samsung.com/
+  *
+  * Header file for Samsung Jpeg Interface driver
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+ */
+
+
+#ifndef __JPEG_DEV_H__
+#define __JPEG_DEV_H__
+
+
+#define JPEG_MINOR_NUMBER	254
+#define JPEG_NAME		"s5p-jpeg"
+#define JPEG_MAX_INSTANCE	1
+
+#define JPEG_IOCTL_MAGIC 'J'
+
+#define IOCTL_JPEG_DEC_EXE			_IO(JPEG_IOCTL_MAGIC, 1)
+#define IOCTL_JPEG_ENC_EXE			_IO(JPEG_IOCTL_MAGIC, 2)
+#define IOCTL_GET_DEC_IN_BUF			_IO(JPEG_IOCTL_MAGIC, 3)
+#define IOCTL_GET_DEC_OUT_BUF			_IO(JPEG_IOCTL_MAGIC, 4)
+#define IOCTL_GET_ENC_IN_BUF			_IO(JPEG_IOCTL_MAGIC, 5)
+#define IOCTL_GET_ENC_OUT_BUF			_IO(JPEG_IOCTL_MAGIC, 6)
+#define IOCTL_SET_DEC_PARAM			_IO(JPEG_IOCTL_MAGIC, 7)
+#define IOCTL_SET_ENC_PARAM			_IO(JPEG_IOCTL_MAGIC, 8)
+#define IOCTL_GET_PHYADDR			_IO(JPEG_IOCTL_MAGIC, 9)
+#define IOCTL_GET_PHYMEM_BASE		_IOR(JPEG_IOCTL_MAGIC, 10, unsigned int)
+#define IOCTL_GET_PHYMEM_SIZE		_IOR(JPEG_IOCTL_MAGIC, 11, unsigned int)
+#endif /*__JPEG_DEV_H__*/
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_mem.c b/drivers/media/video/samsung/jpeg/jpeg_mem.c
new file mode 100644
index 0000000..9214c10
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_mem.c
@@ -0,0 +1,131 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_mem.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Managent memory of the jpeg driver for encoder/docoder.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/page.h>
+#include <linux/errno.h>
+#include <linux/vmalloc.h>
+#include <linux/device.h>
+
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+#include <mach/media.h>
+#include <plat/media.h>
+#endif
+#include "jpeg_mem.h"
+#include "jpeg_core.h"
+
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+unsigned int s_cookie;	/* for stream buffer */
+unsigned int f_cookie;	/* for frame buffer */
+#endif
+
+int jpeg_init_mem(struct device *dev, unsigned int *base)
+{
+#ifdef CONFIG_S5P_MEM_CMA
+	struct cma_info mem_info;
+	int err;
+	int size;
+	char cma_name[8];
+#endif
+#if defined(CONFIG_S5P_SYSMMU_JPEG)
+#if !defined(CONFIG_S5P_VMEM)
+	unsigned char *addr;
+	addr = vmalloc(JPEG_MEM_SIZE);
+	if (addr == NULL)
+		return -1;
+	*base = (unsigned int)addr;
+#endif /* CONFIG_S5P_VMEM */
+#else
+#ifdef CONFIG_S5P_MEM_CMA
+	/* CMA */
+	sprintf(cma_name, "jpeg");
+	err = cma_info(&mem_info, dev, 0);
+	jpeg_info("[cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+			"total_size : 0x%x, free_size : 0x%x\n",
+			mem_info.lower_bound, mem_info.upper_bound,
+			mem_info.total_size, mem_info.free_size);
+	if (err) {
+		printk("%s: get cma info failed\n", __func__);
+		return -1;
+	}
+	size = mem_info.total_size;
+	*base = (dma_addr_t)cma_alloc
+		(dev, cma_name, (size_t)size, 0);
+	jpeg_info("size = 0x%x\n", size);
+	jpeg_info("*base = 0x%x\n", *base);
+#else
+	*base = s5p_get_media_memory_bank(S5P_MDEV_JPEG, 0);
+#endif
+#endif /* CONFIG_S5P_SYSMMU_JPEG */
+	return 0;
+}
+
+int jpeg_mem_free(void)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+	if (s_cookie != 0) {
+		s5p_vfree(s_cookie);
+		s_cookie = 0;
+	}
+	if (f_cookie != 0) {
+		s5p_vfree(f_cookie);
+		f_cookie = 0;
+	}
+#endif
+	return 0;
+}
+
+unsigned long jpeg_get_stream_buf(unsigned long arg)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+	arg = ((arg / PAGE_SIZE + 1) * PAGE_SIZE);
+	s_cookie = (unsigned int)s5p_vmalloc(arg);
+		if (s_cookie == 0)
+			return -1;
+	return (unsigned long)s_cookie;
+#else
+	return arg + JPEG_MAIN_START;
+#endif
+}
+
+unsigned long jpeg_get_frame_buf(unsigned long arg)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+	arg = ((arg / PAGE_SIZE + 1) * PAGE_SIZE);
+	f_cookie = (unsigned int)s5p_vmalloc(arg);
+		if (f_cookie == 0)
+			return -1;
+	return (unsigned long)f_cookie;
+#else
+	return arg + JPEG_S_BUF_SIZE;
+#endif
+}
+
+void jpeg_set_stream_buf(unsigned int *str_buf, unsigned int base)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+	*str_buf = (unsigned int)s5p_getaddress(s_cookie);
+#else
+	*str_buf = base;
+#endif
+}
+
+void jpeg_set_frame_buf(unsigned int *fra_buf, unsigned int base)
+{
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+	*fra_buf = (unsigned int)s5p_getaddress(f_cookie);
+#else
+	*fra_buf = base + JPEG_S_BUF_SIZE;
+#endif
+}
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_mem.h b/drivers/media/video/samsung/jpeg/jpeg_mem.h
new file mode 100644
index 0000000..6874992
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_mem.h
@@ -0,0 +1,66 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_mem.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition for Operation of Jpeg encoder/docoder with memory
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_MEM_H__
+#define __JPEG_MEM_H__
+
+// JYSHIN for google demo 20101014
+#define MAX_JPEG_WIDTH		3264
+#define MAX_JPEG_HEIGHT		2448
+
+//#define MAX_JPEG_WIDTH	3072
+//#define MAX_JPEG_HEIGHT	2048
+#ifdef CONFIG_UMP_VCM_ALLOC
+#include <plat/s5p-vcm.h>
+#include "ump_kernel_interface.h"
+#include "ump_kernel_interface_ref_drv.h"
+#endif
+
+#define MAX_JPEG_RES	(MAX_JPEG_WIDTH * MAX_JPEG_HEIGHT)
+
+/* jpeg stream buf */
+#define JPEG_S_BUF_SIZE	((MAX_JPEG_RES / PAGE_SIZE + 1) * PAGE_SIZE)
+/* jpeg frame buf */
+#define JPEG_F_BUF_SIZE	(((MAX_JPEG_RES * 3) / PAGE_SIZE + 1) * PAGE_SIZE)
+
+#define JPEG_MEM_SIZE		(JPEG_S_BUF_SIZE + JPEG_F_BUF_SIZE)
+#define JPEG_MAIN_START		0x00
+
+#define SYSMMU_JPEG_ON
+
+/* for reserved memory */
+struct jpeg_mem {
+	/* buffer base */
+	unsigned int	base;
+	/* for jpeg stream data */
+	unsigned int	stream_data_addr;
+	unsigned int	stream_data_size;
+	/* for raw data */
+	unsigned int	frame_data_addr;
+	unsigned int	frame_data_size;
+};
+
+int jpeg_init_mem(struct device *dev, unsigned int *base);
+int jpeg_mem_free(void);
+unsigned long jpeg_get_stream_buf(unsigned long arg);
+unsigned long jpeg_get_frame_buf(unsigned long arg);
+void jpeg_set_stream_buf(unsigned int *str_buf, unsigned int base);
+void jpeg_set_frame_buf(unsigned int *fra_buf, unsigned int base);
+
+#if defined(CONFIG_S5P_SYSMMU_JPEG) && defined(CONFIG_S5P_VMEM)
+extern unsigned int *s5p_vmalloc(size_t size);
+extern void *s5p_getaddress(unsigned int cookie);
+extern void s5p_vfree(unsigned int cookie);
+#endif
+
+#endif /* __JPEG_MEM_H__ */
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_regs.c b/drivers/media/video/samsung/jpeg/jpeg_regs.c
new file mode 100644
index 0000000..d83326f
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_regs.c
@@ -0,0 +1,289 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_regs.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register interface file for jpeg driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/io.h>
+#include <plat/regs_jpeg.h>
+
+#include "jpeg_regs.h"
+#include "jpeg_conf.h"
+
+void jpeg_sw_reset(void __iomem *base)
+{
+	writel(S5P_JPEG_SW_RESET_REG_ENABLE,
+			base + S5P_JPEG_SW_RESET_REG);
+
+	do {
+		writel(S5P_JPEG_SW_RESET_REG_ENABLE,
+				base + S5P_JPEG_SW_RESET_REG);
+	} while (((readl(base + S5P_JPEG_SW_RESET_REG))
+		& S5P_JPEG_SW_RESET_REG_ENABLE)
+		== S5P_JPEG_SW_RESET_REG_ENABLE);
+
+}
+
+void jpeg_set_clk_power_on(void __iomem *base)
+{
+	/* set jpeg clock register : power on */
+	writel(readl(base + S5P_JPEG_CLKCON_REG) |
+			(S5P_JPEG_CLKCON_REG_POWER_ON_ACTIVATE),
+			base + S5P_JPEG_CLKCON_REG);
+}
+
+void jpeg_set_mode(void __iomem *base, int mode)
+{
+	/* set jpeg mod register */
+	if (mode) {/* decode */
+		writel(readl(base + S5P_JPEG_MOD_REG) |
+			(S5P_JPEG_MOD_REG_PROC_DEC),
+			base + S5P_JPEG_MOD_REG);
+	} else {/* encode */
+		writel(readl(base + S5P_JPEG_MOD_REG) |
+			(S5P_JPEG_MOD_REG_PROC_ENC),
+			base + S5P_JPEG_MOD_REG);
+	}
+
+}
+
+void jpeg_set_dec_out_fmt(void __iomem *base,
+					enum jpeg_frame_format out_fmt)
+{
+	/* set jpeg deocde ouput format register */
+	writel(readl(base + S5P_JPEG_OUTFORM_REG) &
+			~(S5P_JPEG_OUTFORM_REG_YCBCY420),
+			base + S5P_JPEG_OUTFORM_REG);
+	if (out_fmt == YUV_422) {
+		writel(readl(base + S5P_JPEG_OUTFORM_REG) |
+				(S5P_JPEG_OUTFORM_REG_YCBCY422),
+				base + S5P_JPEG_OUTFORM_REG);
+	} else { /* default YUV420 */
+		writel(readl(base + S5P_JPEG_OUTFORM_REG) |
+				(S5P_JPEG_OUTFORM_REG_YCBCY420),
+				base + S5P_JPEG_OUTFORM_REG);
+	}
+
+}
+
+void jpeg_set_enc_in_fmt(void __iomem *base,
+					enum jpeg_frame_format in_fmt)
+{
+	if (in_fmt == YUV_422) {
+		writel(readl(base + S5P_JPEG_CMOD_REG) |
+			(S5P_JPEG_CMOD_REG_MOD_SEL_YCBCR422),
+			base + S5P_JPEG_CMOD_REG);
+	} else {
+		writel(readl(base + S5P_JPEG_CMOD_REG) |
+			(S5P_JPEG_CMOD_REG_MOD_SEL_RGB),
+			base + S5P_JPEG_CMOD_REG);
+	}
+
+}
+
+void jpeg_set_enc_out_fmt(void __iomem *base,
+					enum jpeg_stream_format out_fmt)
+{
+	if (out_fmt == JPEG_422) {
+		writel(readl(base + S5P_JPEG_MOD_REG) |
+			(S5P_JPEG_MOD_REG_SUBSAMPLE_422),
+			base + S5P_JPEG_MOD_REG);
+	} else {
+		writel(readl(base + S5P_JPEG_MOD_REG) |
+			(S5P_JPEG_MOD_REG_SUBSAMPLE_420),
+			base + S5P_JPEG_MOD_REG);
+	}
+}
+
+void jpeg_set_enc_dri(void __iomem *base, unsigned int value)
+{
+	/* set JPEG Restart Interval */
+	writel(value, base + S5P_JPEG_DRI_L_REG);
+	writel((value >> 8), base + S5P_JPEG_DRI_U_REG);
+}
+
+void jpeg_set_enc_qtbl(void __iomem *base,
+				enum  jpeg_img_quality_level level)
+{
+	/* set quantization table index for jpeg encode */
+	unsigned int val;
+	int i;
+
+	switch (level) {
+	case QUALITY_LEVEL_1:
+		val = S5P_JPEG_QHTBL_REG_QT_NUM1;
+		break;
+	case QUALITY_LEVEL_2:
+		val = S5P_JPEG_QHTBL_REG_QT_NUM2;
+		break;
+	case QUALITY_LEVEL_3:
+		val = S5P_JPEG_QHTBL_REG_QT_NUM3;
+		break;
+	case QUALITY_LEVEL_4:
+		val = S5P_JPEG_QHTBL_REG_QT_NUM4;
+		break;
+	default:
+		val = S5P_JPEG_QHTBL_REG_QT_NUM1;
+		break;
+	}
+	writel(val, base + S5P_JPEG_QTBL_REG);
+
+	for (i = 0; i < 64; i++) {
+		writel((unsigned int)qtbl_luminance[level][i],
+			base + S5P_JPEG_QTBL0_REG + (i*0x04));
+	}
+	for (i = 0; i < 64; i++) {
+		writel((unsigned int)qtbl_chrominance[level][i],
+			base + S5P_JPEG_QTBL1_REG + (i*0x04));
+	}
+
+}
+
+void jpeg_set_enc_htbl(void __iomem *base)
+{
+	int i;
+
+	/* set huffman table index for jpeg encode */
+	writel(0x00, base + S5P_JPEG_HTBL_REG);
+
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)hdctbl0[i],
+			base + S5P_JPEG_HDCTBL0_REG + (i*0x04));
+	}
+	for (i = 0; i < 12; i++) {
+		writel((unsigned int)hdctblg0[i],
+			base + S5P_JPEG_HDCTBLG0_REG + (i*0x04));
+	}
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)hactbl0[i],
+			base + S5P_JPEG_HACTBL0_REG + (i*0x04));
+	}
+	for (i = 0; i < 162; i++) {
+		writel((unsigned int)hactblg0[i],
+			base + S5P_JPEG_HACTBLG0_REG + (i*0x04));
+	}
+}
+
+void jpeg_set_enc_coef(void __iomem *base)
+{
+	/* set coefficient value for RGB-to-YCbCr */
+	writel(COEF1_RGB_2_YUV, base + S5P_JPEG_COEF1_REG);
+	writel(COEF2_RGB_2_YUV, base + S5P_JPEG_COEF2_REG);
+	writel(COEF3_RGB_2_YUV, base + S5P_JPEG_COEF3_REG);
+}
+
+void jpeg_set_frame_addr(void __iomem *base, unsigned int fra_addr)
+{
+	/* set the address of compressed input data */
+	writel(fra_addr, base + S5P_JPEG_IMGADR_REG);
+}
+
+void jpeg_set_stream_addr(void __iomem *base, unsigned int str_addr)
+{
+	/* set the address of compressed input data */
+	writel(str_addr, base + S5P_JPEG_JPGADR_REG);
+}
+
+void jpeg_get_frame_size(void __iomem *base,
+			unsigned int *width, unsigned int *height)
+{
+	*width = (readl(base + S5P_JPEG_X_U_REG)<<8)|
+		readl(base + S5P_JPEG_X_L_REG);
+	*height = (readl(base + S5P_JPEG_Y_U_REG)<<8)|
+		readl(base + S5P_JPEG_Y_L_REG);
+}
+
+void jpeg_set_frame_size(void __iomem *base,
+			unsigned int width, unsigned int height)
+{
+	/* Horizontal resolution */
+	writel((width >> 8), base + S5P_JPEG_X_U_REG);
+	writel(width, base + S5P_JPEG_X_L_REG);
+
+	/* Vertical resolution */
+	writel((height >> 8), base + S5P_JPEG_Y_U_REG);
+	writel(height, base + S5P_JPEG_Y_L_REG);
+}
+
+enum jpeg_stream_format jpeg_get_stream_fmt(void __iomem *base)
+{
+	enum jpeg_stream_format		out_fmt;
+	unsigned long			jpeg_mode;
+
+	jpeg_mode = readl(base + S5P_JPEG_MOD_REG);
+
+	out_fmt =
+		((jpeg_mode & 0x07) == 0x00) ? JPEG_444 :
+		((jpeg_mode & 0x07) == 0x01) ? JPEG_422 :
+		((jpeg_mode & 0x07) == 0x02) ? JPEG_420 :
+		((jpeg_mode & 0x07) == 0x03) ? JPEG_GRAY : JPEG_RESERVED;
+
+	return out_fmt;
+
+}
+
+unsigned int jpeg_get_stream_size(void __iomem *base)
+{
+	unsigned int size;
+
+	size = readl(base + S5P_JPEG_CNT_U_REG) << 16;
+	size |= readl(base + S5P_JPEG_CNT_M_REG) << 8;
+	size |= readl(base + S5P_JPEG_CNT_L_REG);
+
+	return size;
+}
+
+void jpeg_start_decode(void __iomem *base)
+{
+	/* set jpeg interrupt */
+	writel(readl(base  + S5P_JPEG_INTSE_REG) |
+			(S5P_JPEG_INTSE_REG_RSTM_INT_EN	|
+			S5P_JPEG_INTSE_REG_DATA_NUM_INT_EN |
+			S5P_JPEG_INTSE_REG_FINAL_MCU_NUM_INT_EN),
+			base  + S5P_JPEG_INTSE_REG);
+
+	/* start decoding */
+	writel(readl(base + S5P_JPEG_JRSTART_REG) |
+			S5P_JPEG_JRSTART_REG_ENABLE,
+			base + S5P_JPEG_JSTART_REG);
+}
+
+void jpeg_start_encode(void __iomem *base)
+{
+	/* set jpeg interrupt */
+	writel(readl(base + S5P_JPEG_INTSE_REG) |
+			(S5P_JPEG_INTSE_REG_RSTM_INT_EN	|
+			S5P_JPEG_INTSE_REG_DATA_NUM_INT_EN |
+			S5P_JPEG_INTSE_REG_FINAL_MCU_NUM_INT_EN),
+			base + S5P_JPEG_INTSE_REG);
+
+	/* start encoding */
+	writel(readl(base + S5P_JPEG_JSTART_REG) |
+			S5P_JPEG_JSTART_REG_ENABLE,
+			base + S5P_JPEG_JSTART_REG);
+}
+
+unsigned int jpeg_get_int_status(void __iomem *base)
+{
+	unsigned int	int_status;
+	unsigned int	status;
+
+	int_status = readl(base + S5P_JPEG_INTST_REG);
+
+	do {
+		status = readl(base + S5P_JPEG_OPR_REG);
+	} while (status);
+
+	return int_status;
+}
+
+void jpeg_clear_int(void __iomem *base)
+{
+	writel(S5P_JPEG_COM_INT_RELEASE, base + S5P_JPEG_COM_REG);
+}
+
diff --git a/drivers/media/video/samsung/jpeg/jpeg_regs.h b/drivers/media/video/samsung/jpeg/jpeg_regs.h
new file mode 100644
index 0000000..93ac2d0
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg/jpeg_regs.h
@@ -0,0 +1,46 @@
+/* linux/drivers/media/video/samsung/jpeg/jpeg_regs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file of the register interface for jpeg driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_REGS_H__
+#define __JPEG_REGS_H__
+
+#include "jpeg_core.h"
+
+void jpeg_sw_reset(void __iomem *base);
+void jpeg_set_clk_power_on(void __iomem *base);
+void jpeg_set_mode(void __iomem *base, int mode);
+void jpeg_set_dec_out_fmt(void __iomem *base,
+			enum jpeg_frame_format out_fmt);
+void jpeg_set_enc_in_fmt(void __iomem *base,
+			enum jpeg_frame_format in_fmt);
+void jpeg_set_enc_out_fmt(void __iomem *base,
+			enum jpeg_stream_format out_fmt);
+void jpeg_set_enc_dri(void __iomem *base, unsigned int value);
+void jpeg_set_enc_qtbl(void __iomem *base,
+			enum jpeg_img_quality_level level);
+void jpeg_set_enc_htbl(void __iomem *base);
+void jpeg_set_enc_coef(void __iomem *base);
+void jpeg_set_frame_addr(void __iomem *base, unsigned int fra_addr);
+void jpeg_set_stream_addr(void __iomem *base, unsigned int str_addr);
+void jpeg_get_frame_size(void __iomem *base,
+			unsigned int *width, unsigned int *height);
+void jpeg_set_frame_size(void __iomem *base,
+			unsigned int width, unsigned int height);
+enum jpeg_stream_format jpeg_get_stream_fmt(void __iomem *base);
+unsigned int jpeg_get_stream_size(void __iomem *base);
+void jpeg_start_decode(void __iomem *base);
+void jpeg_start_encode(void __iomem *base);
+unsigned int jpeg_get_int_status(void __iomem *base);
+void jpeg_clear_int(void __iomem *base);
+
+#endif /* __JPEG_REGS_H__ */
+
diff --git a/drivers/media/video/samsung/jpeg_v2x/Kconfig b/drivers/media/video/samsung/jpeg_v2x/Kconfig
new file mode 100644
index 0000000..2738ca3
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/Kconfig
@@ -0,0 +1,29 @@
+#
+# Configuration for JPEG
+#
+
+config VIDEO_JPEG_V2X
+	bool "Samsung JPEG_v2.x driver"
+	depends on VIDEO_SAMSUNG
+	default n
+	depends on VIDEO_DEV && VIDEO_V4L2
+	select V4L2_MEM2MEM_DEV
+	---help---
+	  This is a Samsung JPEG H/W driver for V2.x
+choice
+	prompt "JPEG V2X VERSION"
+	default S5P_JPEG_V2_1
+	depends on VIDEO_JPEG_V2X
+	---help---
+	  Select version of JPEG driver
+
+config JPEG_V2_1
+	bool "JPEG 2.1"
+	---help---
+	  Use JPEG 2.1 Pegasus/Gaia evt 0.0
+
+config JPEG_V2_2
+	bool "JPEG 2.2"
+	---help---
+	  Use JPEG 2.2 Gaia evt 1.0
+endchoice
diff --git a/drivers/media/video/samsung/jpeg_v2x/Makefile b/drivers/media/video/samsung/jpeg_v2x/Makefile
new file mode 100644
index 0000000..369ee75
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/Makefile
@@ -0,0 +1,8 @@
+#################################################
+# Makefile for JPEG
+# 2009 (C) Samsung Electronics
+#################################################
+
+obj-$(CONFIG_VIDEO_JPEG_V2X)	+= jpeg_dev.o jpeg_dec.o jpeg_enc.o jpeg_regs.o jpeg_mem.o
+
+EXTRA_CFLAGS += -Idrivers/media/video
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_conf.h b/drivers/media/video/samsung/jpeg_v2x/jpeg_conf.h
new file mode 100644
index 0000000..6fcc276
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_conf.h
@@ -0,0 +1,92 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_conf.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition Quantization Table for Jpeg encoder/docoder
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_CONF_H__
+#define __JPEG_CONF_H__
+
+/* Q-table for JPEG */
+/*  ITU standard Q-table */
+const unsigned int ITU_Q_tbl[4][16] = {
+	{
+	0x01010101, 0x01020303, 0x01010101, 0x01030303, /* Y */
+	0x01010101, 0x02030303, 0x01010101, 0x03040403,
+	0x01010203, 0x03050504, 0x01020303, 0x04050605,
+	0x02030404, 0x05060605, 0x04050505, 0x06050505
+	} , {
+	0x01010102, 0x05050505, 0x01010103, 0x05050505, /* CbCr */
+	0x01010503, 0x05050505, 0x02030505, 0x05050505,
+	0x05050505, 0x05050505, 0x05050505, 0x05050505,
+	0x05050505, 0x05050505, 0x05050505, 0x05050505
+	} , {
+	0x05020205, 0x0a161e25, 0x02020307, 0x0c232521, /* Y */
+	0x0302050a, 0x16222b22, 0x0305090e, 0x1e393326,
+	0x06091422, 0x2a384431, 0x0a122118, 0x34454b3c,
+	0x1d283238, 0x44525142, 0x2d3c3e40, 0x4a424441
+	} , {
+	0x05020205, 0x251e160a, 0x07030202, 0x2125230c, /* CbCr */
+	0x0a050203, 0x222b2216, 0x0e090503, 0x2633391e,
+	0x22140906, 0x3144382a, 0x1821120a, 0x3c4b4534,
+	0x3832281d, 0x42515244, 0x403e3c2d, 0x4144424a
+	}
+};
+
+/* ITU Luminace Huffman Table */
+static unsigned int ITU_H_tbl_len_DC_luminance[4] = {
+	0x01050100, 0x01010101, 0x00000001, 0x00000000
+};
+static unsigned int ITU_H_tbl_val_DC_luminance[3] = {
+	0x03020100, 0x07060504, 0x0b0a0908
+};
+
+/* ITU Chrominace Huffman Table */
+static unsigned int ITU_H_tbl_len_DC_chrominance[4] = {
+	0x01010300, 0x01010101, 0x00010101, 0x00000000
+};
+static unsigned int ITU_H_tbl_val_DC_chrominance[3] = {
+	0x03020100, 0x07060504, 0x0b0a0908
+};
+
+static unsigned int ITU_H_tbl_len_AC_luminance[4] = {
+	0x03010200, 0x03040203, 0x04040505, 0x7d010000
+};
+
+static unsigned int ITU_H_tbl_val_AC_luminance[41] = {
+	0x00030201, 0x12051104, 0x06413121, 0x07615113,
+	0x32147122, 0x08a19181, 0xc1b14223, 0xf0d15215,
+	0x72623324, 0x160a0982, 0x1a191817, 0x28272625,
+	0x35342a29, 0x39383736, 0x4544433a, 0x49484746,
+	0x5554534a, 0x59585756, 0x6564635a, 0x69686766,
+	0x7574736a, 0x79787776, 0x8584837a, 0x89888786,
+	0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4,
+	0xb2aaa9a8, 0xb6b5b4b3, 0xbab9b8b7, 0xc5c4c3c2,
+	0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9,
+	0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5,
+	0x0000faf9
+};
+
+static u32 ITU_H_tbl_len_AC_chrominance[4] = {
+	0x02010200, 0x04030404, 0x04040507, 0x77020100
+};
+static u32 ITU_H_tbl_val_AC_chrominance[41] = {
+	0x03020100, 0x21050411, 0x41120631, 0x71610751,
+	0x81322213, 0x91421408, 0x09c1b1a1, 0xf0523323,
+	0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918,
+	0x2a292827, 0x38373635, 0x44433a39, 0x48474645,
+	0x54534a49, 0x58575655, 0x64635a59, 0x68676665,
+	0x74736a69, 0x78777675, 0x83827a79, 0x87868584,
+	0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2,
+	0xa9a8a7a6, 0xb4b3b2aa, 0xb8b7b6b5, 0xc3c2bab9,
+	0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7,
+	0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5,
+	0x0000faf9
+};
+#endif /* __JPEG_CONF_H__ */
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_core.h b/drivers/media/video/samsung/jpeg_v2x/jpeg_core.h
new file mode 100644
index 0000000..8208235
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_core.h
@@ -0,0 +1,278 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition for core file of the jpeg operation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_CORE_H__
+#define __JPEG_CORE_H__
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+
+#include <linux/videodev2.h>
+#include <linux/videodev2_exynos_media.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+#include <media/v4l2-ioctl.h>
+
+#include <media/videobuf2-core.h>
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+#include <media/videobuf2-cma-phys.h>
+#elif defined(CONFIG_VIDEOBUF2_ION)
+#include <media/videobuf2-ion.h>
+#endif
+#include "jpeg_mem.h"
+
+#define INT_TIMEOUT		1000
+
+#define JPEG_NUM_INST		4
+#define JPEG_MAX_PLANE		3
+
+enum jpeg_state {
+	JPEG_IDLE,
+	JPEG_SRC_ADDR,
+	JPEG_DST_ADDR,
+	JPEG_ISR,
+	JPEG_STREAM,
+};
+
+enum jpeg_mode {
+	ENCODING,
+	DECODING,
+};
+
+enum jpeg_result {
+	OK_ENC_OR_DEC,
+	ERR_PROT,
+	ERR_DEC_INVALID_FORMAT,
+	ERR_MULTI_SCAN,
+	ERR_FRAME,
+	ERR_TIME_OUT,
+	ERR_UNKNOWN,
+};
+
+enum  jpeg_img_quality_level {
+	QUALITY_LEVEL_1 = 0,	/* high */
+	QUALITY_LEVEL_2,
+	QUALITY_LEVEL_3,
+	QUALITY_LEVEL_4,	/* low */
+};
+
+/* raw data image format */
+enum jpeg_frame_format {
+	YCRCB_444_2P,
+	YCBCR_444_2P,
+	YCBCR_444_3P,
+	YCBYCR_422_1P,
+	YCRYCB_422_1P,
+	CBYCRY_422_1P,
+	CRYCBY_422_1P,
+	YCBCR_422_2P,
+	YCRCB_422_2P,
+	YCBYCR_422_3P,
+	YCBCR_420_3P,
+	YCRCB_420_3P,
+	YCBCR_420_2P,
+	YCRCB_420_2P,
+	YCBCR_420_2P_M,
+	YCRCB_420_2P_M,
+	RGB_565,
+	RGB_888,
+	BGR_888,
+	GRAY,
+};
+
+/* jpeg data format */
+enum jpeg_stream_format {
+	JPEG_422,	/* decode input, encode output */
+	JPEG_420,	/* decode input, encode output */
+	JPEG_444,	/* decode input*/
+	JPEG_GRAY,	/* decode input*/
+	JPEG_RESERVED,
+};
+
+enum jpeg_scale_value {
+	JPEG_SCALE_NORMAL,
+	JPEG_SCALE_2,
+	JPEG_SCALE_4,
+};
+
+enum jpeg_interface {
+	M2M_OUTPUT,
+	M2M_CAPTURE,
+};
+
+enum jpeg_node_type {
+	JPEG_NODE_INVALID = -1,
+	JPEG_NODE_DECODER = 11,
+	JPEG_NODE_ENCODER = 12,
+};
+
+struct jpeg_fmt {
+	char			*name;
+	unsigned int			fourcc;
+	int			depth[JPEG_MAX_PLANE];
+	int			color;
+	int			memplanes;
+	int			colplanes;
+	enum jpeg_interface	types;
+};
+
+struct jpeg_dec_param {
+	unsigned int in_width;
+	unsigned int in_height;
+	unsigned int out_width;
+	unsigned int out_height;
+	unsigned int size;
+	unsigned int mem_size;
+	unsigned int in_plane;
+	unsigned int out_plane;
+	unsigned int in_depth;
+	unsigned int out_depth[JPEG_MAX_PLANE];
+
+	enum jpeg_stream_format in_fmt;
+	enum jpeg_frame_format out_fmt;
+};
+
+struct jpeg_enc_param {
+	unsigned int in_width;
+	unsigned int in_height;
+	unsigned int out_width;
+	unsigned int out_height;
+	unsigned int size;
+	unsigned int in_plane;
+	unsigned int out_plane;
+	unsigned int in_depth[JPEG_MAX_PLANE];
+	unsigned int out_depth;
+
+	enum jpeg_frame_format in_fmt;
+	enum jpeg_stream_format out_fmt;
+	enum jpeg_img_quality_level quality;
+};
+
+struct jpeg_ctx {
+	spinlock_t			slock;
+	struct jpeg_dev		*dev;
+	struct v4l2_m2m_ctx	*m2m_ctx;
+
+	union {
+		struct jpeg_dec_param	dec_param;
+		struct jpeg_enc_param	enc_param;
+	} param;
+
+	int			index;
+	unsigned long		payload[VIDEO_MAX_PLANES];
+	bool			input_cacheable;
+	bool			output_cacheable;
+};
+
+struct jpeg_vb2 {
+	const struct vb2_mem_ops *ops;
+	void *(*init)(struct jpeg_dev *dev);
+	void (*cleanup)(void *alloc_ctx);
+
+	unsigned long (*plane_addr)(struct vb2_buffer *vb, u32 plane_no);
+
+	int (*resume)(void *alloc_ctx);
+	void (*suspend)(void *alloc_ctx);
+
+	int (*cache_flush)(struct vb2_buffer *vb, u32 num_planes);
+	void (*set_cacheable)(void *alloc_ctx, bool cacheable);
+};
+
+struct jpeg_dev {
+	spinlock_t			slock;
+	struct v4l2_device	v4l2_dev;
+	struct video_device	*vfd_enc;
+	struct video_device	*vfd_dec;
+	struct v4l2_m2m_dev	*m2m_dev_enc;
+	struct v4l2_m2m_dev	*m2m_dev_dec;
+	struct jpeg_ctx		*ctx;
+	struct vb2_alloc_ctx	*alloc_ctx;
+
+	struct platform_device	*plat_dev;
+
+	struct clk		*clk;
+
+	struct mutex		lock;
+
+	int			irq_no;
+	enum jpeg_result	irq_ret;
+	wait_queue_head_t	 wq;
+	void __iomem		*reg_base;	/* register i/o */
+	enum jpeg_mode		mode;
+	const struct jpeg_vb2	*vb2;
+
+	unsigned long		hw_run;
+	atomic_t		watchdog_cnt;
+	struct timer_list	watchdog_timer;
+	struct workqueue_struct	*watchdog_workqueue;
+	struct work_struct	watchdog_work;
+	struct device			*bus_dev;
+};
+
+enum jpeg_log {
+	JPEG_LOG_DEBUG		= 0x1000,
+	JPEG_LOG_INFO		= 0x0100,
+	JPEG_LOG_WARN		= 0x0010,
+	JPEG_LOG_ERR		= 0x0001,
+};
+
+/* debug macro */
+#define JPEG_LOG_DEFAULT       (JPEG_LOG_WARN | JPEG_LOG_ERR)
+
+#define JPEG_DEBUG(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_DEBUG)			\
+			printk(KERN_DEBUG "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define JPEG_INFO(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_INFO)			\
+			printk(KERN_INFO "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+#define JPEG_WARN(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_WARN)			\
+			printk(KERN_WARNING "%s: "			\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define JPEG_ERROR(fmt, ...)						\
+	do {								\
+		if (JPEG_LOG_DEFAULT & JPEG_LOG_ERR)			\
+			printk(KERN_ERR "%s: "				\
+				fmt, __func__, ##__VA_ARGS__);		\
+	} while (0)
+
+
+#define jpeg_dbg(fmt, ...)		JPEG_DEBUG(fmt, ##__VA_ARGS__)
+#define jpeg_info(fmt, ...)		JPEG_INFO(fmt, ##__VA_ARGS__)
+#define jpeg_warn(fmt, ...)		JPEG_WARN(fmt, ##__VA_ARGS__)
+#define jpeg_err(fmt, ...)		JPEG_ERROR(fmt, ##__VA_ARGS__)
+
+/*=====================================================================*/
+const struct v4l2_ioctl_ops *get_jpeg_dec_v4l2_ioctl_ops(void);
+const struct v4l2_ioctl_ops *get_jpeg_enc_v4l2_ioctl_ops(void);
+
+int jpeg_int_pending(struct jpeg_dev *ctrl);
+
+#endif /*__JPEG_CORE_H__*/
+
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_dec.c b/drivers/media/video/samsung/jpeg_v2x/jpeg_dec.c
new file mode 100644
index 0000000..7020f39
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_dec.c
@@ -0,0 +1,542 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_dec.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Core file for Samsung Jpeg v2.x Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+
+#include <asm/page.h>
+
+#include <plat/regs_jpeg_v2_x.h>
+#include <mach/irqs.h>
+
+#include <media/v4l2-ioctl.h>
+
+#include "jpeg_core.h"
+#include "jpeg_dev.h"
+
+#include "jpeg_mem.h"
+#include "jpeg_regs.h"
+
+static struct jpeg_fmt formats[] = {
+	{
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_444,
+		.depth		= {8},
+		.color		= JPEG_444,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_422,
+		.depth		= {8},
+		.color		= JPEG_422,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_420,
+		.depth		= {8},
+		.color		= JPEG_420,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_GRAY,
+		.depth		= {8},
+		.color		= JPEG_GRAY,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "RGB565",
+		.fourcc		= V4L2_PIX_FMT_RGB565X,
+		.depth		= {16},
+		.color		= RGB_565,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "XRGB-8-8-8-8, 32 bpp",
+		.fourcc		= V4L2_PIX_FMT_RGB32,
+		.depth		= {32},
+		.color		= RGB_888,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_YUV444_2P,
+		.depth		= {8, 16},
+		.color		= YCBCR_444_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_YVU444_2P,
+		.depth		= {8, 16},
+		.color		= YCRCB_444_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/Cb/Cr",
+		.fourcc		= V4L2_PIX_FMT_YUV444_3P,
+		.depth		= {8, 8, 8},
+		.color		= YCBCR_444_3P,
+		.memplanes	= 3,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCrYCb",
+		.fourcc		= V4L2_PIX_FMT_YVYU,
+		.depth		= {16},
+		.color		= YCRYCB_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCbYCr",
+		.fourcc		= V4L2_PIX_FMT_YUYV,
+		.depth		= {16},
+		.color		= YCBYCR_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_NV61,
+		.depth		= {8, 8},
+		.color		= YCRCB_422_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_NV16,
+		.depth		= {8, 8},
+		.color		= YCBCR_422_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_NV12,
+		.depth		= {8, 4},
+		.color		= YCBCR_420_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_NV21,
+		.depth		= {8, 4},
+		.color		= YCRCB_420_2P,
+		.memplanes	= 2,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:0 contiguous 3-planar, Y/Cb/Cr",
+		.fourcc		= V4L2_PIX_FMT_YUV420,
+		.depth		= {8, 2, 2},
+		.color		= YCBCR_420_3P,
+		.memplanes	= 3,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:0 contiguous 3-planar, Y/Cr/Cb",
+		.fourcc		= V4L2_PIX_FMT_YVU420,
+		.depth		= {8, 2, 2},
+		.color		= YCRCB_420_3P,
+		.memplanes	= 3,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "Gray",
+		.fourcc		= V4L2_PIX_FMT_GREY,
+		.depth		= {8},
+		.color		= GRAY,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	},
+#ifdef CONFIG_JPEG_V2_2
+	{
+		.name		= "YUV 4:2:2 packed, CrYCbY",
+		.fourcc		= V4L2_PIX_FMT_VYUY,
+		.depth		= {16},
+		.color		= CRYCBY_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "YUV 4:2:2 packed, CbYCrY",
+		.fourcc		= V4L2_PIX_FMT_UYVY,
+		.depth		= {16},
+		.color		= CRYCBY_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "XBGR-8-8-8-8, 32 bpp",
+		.fourcc		= V4L2_PIX_FMT_BGR32,
+		.depth		= {32},
+		.color		= BGR_888,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	},
+#endif
+};
+
+static struct jpeg_fmt *find_format(struct v4l2_format *f)
+{
+	struct jpeg_fmt *fmt;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+		fmt = &formats[i];
+		if (fmt->fourcc == f->fmt.pix_mp.pixelformat)
+			break;
+	}
+
+	return (i == ARRAY_SIZE(formats)) ? NULL : fmt;
+}
+
+static int jpeg_dec_vidioc_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct jpeg_ctx *ctx = file->private_data;
+	struct jpeg_dev *dev = ctx->dev;
+
+	strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
+		V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+	return 0;
+}
+
+int jpeg_dec_vidioc_enum_fmt(struct file *file, void *priv,
+				struct v4l2_fmtdesc *f)
+{
+	struct jpeg_fmt *fmt;
+
+	if (f->index >= ARRAY_SIZE(formats))
+		return -EINVAL;
+
+	fmt = &formats[f->index];
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->color;
+
+	return 0;
+}
+
+int jpeg_dec_vidioc_g_fmt(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct v4l2_pix_format_mplane *pixm;
+	struct jpeg_dec_param *dec_param = &ctx->param.dec_param;
+	unsigned int width, height;
+
+	pixm = &f->fmt.pix_mp;
+
+	pixm->field	= V4L2_FIELD_NONE;
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		pixm->pixelformat = dec_param->in_fmt;
+		pixm->num_planes = dec_param->in_plane;
+		pixm->width = dec_param->in_width;
+		pixm->height = dec_param->in_height;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		jpeg_get_frame_size(ctx->dev->reg_base, &width, &height);
+		pixm->pixelformat =
+			dec_param->out_fmt;
+		pixm->num_planes = dec_param->out_plane;
+		pixm->width = width;
+		pixm->height = height;
+	} else {
+		v4l2_err(&ctx->dev->v4l2_dev,
+			"Wrong buffer/video queue type (%d)\n", f->type);
+	}
+
+	return 0;
+}
+
+static int jpeg_dec_vidioc_try_fmt(struct file *file, void *priv,
+			       struct v4l2_format *f)
+{
+	struct jpeg_fmt *fmt;
+	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
+	struct jpeg_ctx *ctx = priv;
+	int i;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+		f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+			return -EINVAL;
+
+	fmt = find_format(f);
+
+	if (!fmt) {
+		v4l2_err(&ctx->dev->v4l2_dev,
+			 "Fourcc format (0x%08x) invalid.\n",
+			 f->fmt.pix.pixelformat);
+		return -EINVAL;
+	}
+
+	if (pix->field == V4L2_FIELD_ANY)
+		pix->field = V4L2_FIELD_NONE;
+	else if (V4L2_FIELD_NONE != pix->field)
+		return -EINVAL;
+
+	pix->num_planes = fmt->memplanes;
+
+	for (i = 0; i < pix->num_planes; ++i) {
+		int bpl = pix->plane_fmt[i].bytesperline;
+
+		jpeg_dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
+		    i, bpl, fmt->depth[i], pix->width, pix->height);
+		if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
+			bpl = (pix->width * fmt->depth[i]) >> 3;
+
+		if (!pix->plane_fmt[i].sizeimage)
+			pix->plane_fmt[i].sizeimage = pix->height * bpl;
+
+		pix->plane_fmt[i].bytesperline = bpl;
+
+		jpeg_dbg("[%d]: bpl: %d, sizeimage: %d",
+		    i, pix->plane_fmt[i].bytesperline,
+		    pix->plane_fmt[i].sizeimage);
+	}
+
+	if (f->fmt.pix.height > MAX_JPEG_HEIGHT)
+		f->fmt.pix.height = MAX_JPEG_HEIGHT;
+
+	if (f->fmt.pix.width > MAX_JPEG_WIDTH)
+		f->fmt.pix.width = MAX_JPEG_WIDTH;
+
+	return 0;
+}
+
+static int jpeg_dec_vidioc_s_fmt_cap(struct file *file, void *priv,
+				struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+	struct v4l2_pix_format_mplane *pix;
+	struct jpeg_fmt *fmt;
+	int ret;
+	int i;
+
+	ret = jpeg_dec_vidioc_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&ctx->dev->v4l2_dev, "queue (%d) busy\n", f->type);
+		return -EBUSY;
+	}
+
+	/* TODO: width & height has to be multiple of two */
+	pix = &f->fmt.pix_mp;
+	fmt = find_format(f);
+
+	for (i = 0; i < fmt->memplanes; i++) {
+		ctx->payload[i] =
+			pix->plane_fmt[i].bytesperline * pix->height;
+		ctx->param.dec_param.out_depth[i] = fmt->depth[i];
+	}
+	ctx->param.dec_param.out_width = pix->width;
+	ctx->param.dec_param.out_height = pix->height;
+	ctx->param.dec_param.out_plane = fmt->memplanes;
+	ctx->param.dec_param.out_fmt = fmt->color;
+
+	return 0;
+}
+
+static int jpeg_dec_vidioc_s_fmt_out(struct file *file, void *priv,
+			struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+	struct v4l2_pix_format_mplane *pix;
+	struct jpeg_fmt *fmt;
+	int ret;
+	int i;
+
+	ret = jpeg_dec_vidioc_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&ctx->dev->v4l2_dev, "queue (%d) busy\n", f->type);
+		return -EBUSY;
+	}
+
+	/* TODO: width & height has to be multiple of two */
+	pix = &f->fmt.pix_mp;
+	fmt = find_format(f);
+
+	for (i = 0; i < fmt->memplanes; i++)
+		ctx->payload[i] =
+			pix->plane_fmt[i].bytesperline * pix->height;
+
+	ctx->param.dec_param.in_width = pix->width;
+	ctx->param.dec_param.in_height = pix->height;
+	ctx->param.dec_param.in_plane = fmt->memplanes;
+	ctx->param.dec_param.in_depth = fmt->depth[0];
+	ctx->param.dec_param.in_fmt = fmt->color;
+	if((pix->plane_fmt[0].sizeimage % 32) == 0)
+		ctx->param.dec_param.size = (pix->plane_fmt[0].sizeimage / 32);
+	else
+		ctx->param.dec_param.size = (pix->plane_fmt[0].sizeimage / 32) + 1;
+	ctx->param.dec_param.mem_size = pix->plane_fmt[0].sizeimage;
+
+	return 0;
+}
+
+static int jpeg_dec_m2m_reqbufs(struct file *file, void *priv,
+			  struct v4l2_requestbuffers *reqbufs)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, reqbufs->type);
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ctx->dev->vb2->set_cacheable(ctx->dev->alloc_ctx, ctx->input_cacheable);
+	else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		ctx->dev->vb2->set_cacheable(ctx->dev->alloc_ctx, ctx->output_cacheable);
+
+	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
+}
+
+static int jpeg_dec_m2m_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_dec_m2m_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_dec_m2m_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_dec_m2m_streamon(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
+}
+
+static int jpeg_dec_m2m_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
+}
+
+static int vidioc_dec_s_jpegcomp(struct file *file, void *priv,
+			struct v4l2_jpegcompression *jpegcomp)
+{
+	struct jpeg_ctx *ctx = priv;
+	ctx->param.enc_param.quality = jpegcomp->quality;
+	return 0;
+}
+
+static int jpeg_dec_vidioc_s_ctrl(struct file *file, void *priv,
+			struct v4l2_control *ctrl)
+{
+	struct jpeg_ctx *ctx = priv;
+/*
+*	0 : input/output noncacheable
+*	1 : input/output cacheable
+*	2 : input cacheable / output noncacheable
+*	3 : input noncacheable / output cacheable
+*/
+	switch (ctrl->id) {
+	case V4L2_CID_CACHEABLE:
+		if (ctrl->value == 0) {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 0;
+		} else if (ctrl->value == 1) {
+			ctx->input_cacheable = 1;
+			ctx->output_cacheable = 1;
+		} else if (ctrl->value == 2) {
+			ctx->input_cacheable = 1;
+			ctx->output_cacheable = 0;
+		} else if (ctrl->value == 3) {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 1;
+		} else {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 0;
+		}
+		break;
+	default:
+		v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
+		break;
+	}
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops jpeg_dec_ioctl_ops = {
+	.vidioc_querycap		= jpeg_dec_vidioc_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= jpeg_dec_vidioc_enum_fmt,
+	.vidioc_enum_fmt_vid_out_mplane	= jpeg_dec_vidioc_enum_fmt,
+
+	.vidioc_g_fmt_vid_cap_mplane	= jpeg_dec_vidioc_g_fmt,
+	.vidioc_g_fmt_vid_out_mplane	= jpeg_dec_vidioc_g_fmt,
+
+	.vidioc_try_fmt_vid_cap_mplane		= jpeg_dec_vidioc_try_fmt,
+	.vidioc_try_fmt_vid_out_mplane		= jpeg_dec_vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap_mplane		= jpeg_dec_vidioc_s_fmt_cap,
+	.vidioc_s_fmt_vid_out_mplane		= jpeg_dec_vidioc_s_fmt_out,
+
+	.vidioc_reqbufs		= jpeg_dec_m2m_reqbufs,
+	.vidioc_querybuf		= jpeg_dec_m2m_querybuf,
+	.vidioc_qbuf			= jpeg_dec_m2m_qbuf,
+	.vidioc_dqbuf			= jpeg_dec_m2m_dqbuf,
+	.vidioc_streamon		= jpeg_dec_m2m_streamon,
+	.vidioc_streamoff		= jpeg_dec_m2m_streamoff,
+	.vidioc_s_jpegcomp		= vidioc_dec_s_jpegcomp,
+	.vidioc_s_ctrl			= jpeg_dec_vidioc_s_ctrl,
+};
+const struct v4l2_ioctl_ops *get_jpeg_dec_v4l2_ioctl_ops(void)
+{
+	return &jpeg_dec_ioctl_ops;
+}
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.c b/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.c
new file mode 100644
index 0000000..1e6b085
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.c
@@ -0,0 +1,1122 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Core file for Samsung Jpeg v2.x Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+
+#include <asm/page.h>
+
+#include <plat/regs_jpeg_v2_x.h>
+#include <plat/cpu.h>
+#include <mach/irqs.h>
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+
+#include <media/v4l2-ioctl.h>
+#include <mach/dev.h>
+
+#include "jpeg_core.h"
+#include "jpeg_dev.h"
+
+#include "jpeg_mem.h"
+#include "jpeg_regs.h"
+
+#if defined (CONFIG_JPEG_V2_1)
+void jpeg_watchdog(unsigned long arg)
+{
+	struct jpeg_dev *dev = (struct jpeg_dev *)arg;
+
+	printk(KERN_DEBUG "jpeg_watchdog\n");
+	if (test_bit(0, &dev->hw_run)) {
+		atomic_inc(&dev->watchdog_cnt);
+		printk(KERN_DEBUG "jpeg_watchdog_count.\n");
+	}
+
+	if (atomic_read(&dev->watchdog_cnt) >= JPEG_WATCHDOG_CNT)
+		queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
+
+	dev->watchdog_timer.expires = jiffies +
+					msecs_to_jiffies(JPEG_WATCHDOG_INTERVAL);
+	add_timer(&dev->watchdog_timer);
+}
+
+static void jpeg_watchdog_worker(struct work_struct *work)
+{
+	struct jpeg_dev *dev;
+	struct jpeg_ctx *ctx;
+	unsigned long flags;
+	struct vb2_buffer *src_vb, *dst_vb;
+
+	printk(KERN_DEBUG "jpeg_watchdog_worker\n");
+	dev = container_of(work, struct jpeg_dev, watchdog_work);
+
+	clear_bit(0, &dev->hw_run);
+	if (dev->mode == ENCODING)
+		ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev_enc);
+	else
+		ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev_dec);
+
+	if (ctx) {
+		spin_lock_irqsave(&ctx->slock, flags);
+		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+
+		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
+		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
+		if (dev->mode == ENCODING)
+			v4l2_m2m_job_finish(dev->m2m_dev_enc, ctx->m2m_ctx);
+		else
+			v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
+		spin_unlock_irqrestore(&ctx->slock, flags);
+	} else {
+		printk(KERN_ERR "watchdog_ctx is NULL\n");
+	}
+}
+#endif
+static int jpeg_dec_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+			    unsigned int *num_planes, unsigned long sizes[],
+			    void *allocators[])
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+
+	int i;
+
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		*num_planes = ctx->param.dec_param.in_plane;
+		for (i = 0; i < ctx->param.dec_param.in_plane; i++) {
+			sizes[i] = ctx->param.dec_param.mem_size;
+			allocators[i] = ctx->dev->alloc_ctx;
+		}
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		*num_planes = ctx->param.dec_param.out_plane;
+		for (i = 0; i < ctx->param.dec_param.out_plane; i++) {
+			sizes[i] = (ctx->param.dec_param.out_width *
+				ctx->param.dec_param.out_height *
+				ctx->param.dec_param.out_depth[i]) / 8;
+			allocators[i] = ctx->dev->alloc_ctx;
+		}
+	}
+
+	return 0;
+}
+
+static int jpeg_dec_buf_prepare(struct vb2_buffer *vb)
+{
+	int i;
+	int num_plane = 0;
+
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		num_plane = ctx->param.dec_param.in_plane;
+		if (ctx->input_cacheable == 1)
+			ctx->dev->vb2->cache_flush(vb, num_plane);
+	} else if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		num_plane = ctx->param.dec_param.out_plane;
+		if (ctx->output_cacheable == 1)
+			ctx->dev->vb2->cache_flush(vb, num_plane);
+	}
+
+	for (i = 0; i < num_plane; i++)
+		vb2_set_plane_payload(vb, i, ctx->payload[i]);
+
+	return 0;
+}
+
+static void jpeg_dec_buf_queue(struct vb2_buffer *vb)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (ctx->m2m_ctx)
+		v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
+}
+
+static void jpeg_dec_lock(struct vb2_queue *vq)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_lock(&ctx->dev->lock);
+}
+
+static void jpeg_dec_unlock(struct vb2_queue *vq)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_unlock(&ctx->dev->lock);
+}
+
+static int jpeg_dec_stop_streaming(struct vb2_queue *q)
+{
+	struct jpeg_ctx *ctx = q->drv_priv;
+	struct jpeg_dev *dev = ctx->dev;
+
+	v4l2_m2m_get_next_job(dev->m2m_dev_dec, ctx->m2m_ctx);
+
+	return 0;
+}
+
+static int jpeg_enc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+			    unsigned int *num_planes, unsigned long sizes[],
+			    void *allocators[])
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+
+	int i;
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		*num_planes = ctx->param.enc_param.in_plane;
+		for (i = 0; i < ctx->param.enc_param.in_plane; i++) {
+			sizes[i] = (ctx->param.enc_param.in_width *
+				ctx->param.enc_param.in_height *
+				ctx->param.enc_param.in_depth[i]) / 8;
+			allocators[i] = ctx->dev->alloc_ctx;
+		}
+
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		*num_planes = ctx->param.enc_param.out_plane;
+		for (i = 0; i < ctx->param.enc_param.in_plane; i++) {
+			sizes[i] = (ctx->param.enc_param.out_width *
+				ctx->param.enc_param.out_height *
+				ctx->param.enc_param.out_depth * 22 / 10) / 8;
+			allocators[i] = ctx->dev->alloc_ctx;
+		}
+	}
+
+	return 0;
+}
+
+static int jpeg_enc_buf_prepare(struct vb2_buffer *vb)
+{
+	int i;
+	int num_plane = 0;
+
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+		num_plane = ctx->param.enc_param.in_plane;
+		if (ctx->input_cacheable == 1)
+			ctx->dev->vb2->cache_flush(vb, num_plane);
+	} else if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
+		num_plane = ctx->param.enc_param.out_plane;
+		if (ctx->output_cacheable == 1)
+			ctx->dev->vb2->cache_flush(vb, num_plane);
+	}
+
+	for (i = 0; i < num_plane; i++)
+		vb2_set_plane_payload(vb, i, ctx->payload[i]);
+
+	return 0;
+}
+
+static void jpeg_enc_buf_queue(struct vb2_buffer *vb)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (ctx->m2m_ctx)
+		v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
+}
+
+static void jpeg_enc_lock(struct vb2_queue *vq)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_lock(&ctx->dev->lock);
+}
+
+static void jpeg_enc_unlock(struct vb2_queue *vq)
+{
+	struct jpeg_ctx *ctx = vb2_get_drv_priv(vq);
+	mutex_unlock(&ctx->dev->lock);
+}
+
+static int jpeg_enc_stop_streaming(struct vb2_queue *q)
+{
+	struct jpeg_ctx *ctx = q->drv_priv;
+	struct jpeg_dev *dev = ctx->dev;
+
+	v4l2_m2m_get_next_job(dev->m2m_dev_enc, ctx->m2m_ctx);
+
+	return 0;
+}
+
+static struct vb2_ops jpeg_enc_vb2_qops = {
+	.queue_setup		= jpeg_enc_queue_setup,
+	.buf_prepare		= jpeg_enc_buf_prepare,
+	.buf_queue		= jpeg_enc_buf_queue,
+	.wait_prepare		= jpeg_enc_lock,
+	.wait_finish		= jpeg_enc_unlock,
+	.stop_streaming		= jpeg_enc_stop_streaming,
+};
+
+static struct vb2_ops jpeg_dec_vb2_qops = {
+	.queue_setup		= jpeg_dec_queue_setup,
+	.buf_prepare		= jpeg_dec_buf_prepare,
+	.buf_queue		= jpeg_dec_buf_queue,
+	.wait_prepare		= jpeg_dec_lock,
+	.wait_finish		= jpeg_dec_unlock,
+	.stop_streaming		= jpeg_dec_stop_streaming,
+};
+
+static inline enum jpeg_node_type jpeg_get_node_type(struct file *file)
+{
+	struct video_device *vdev = video_devdata(file);
+
+	if (!vdev) {
+		jpeg_err("failed to get video_device\n");
+		return JPEG_NODE_INVALID;
+	}
+
+	jpeg_dbg("video_device index: %d\n", vdev->num);
+
+	if (vdev->num == JPEG_NODE_DECODER)
+		return JPEG_NODE_DECODER;
+	else if (vdev->num == JPEG_NODE_ENCODER)
+		return JPEG_NODE_ENCODER;
+	else
+		return JPEG_NODE_INVALID;
+}
+
+static int queue_init_dec(void *priv, struct vb2_queue *src_vq,
+		      struct vb2_queue *dst_vq)
+{
+	struct jpeg_ctx *ctx = priv;
+	int ret;
+
+	memset(src_vq, 0, sizeof(*src_vq));
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	src_vq->drv_priv = ctx;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	src_vq->ops = &jpeg_dec_vb2_qops;
+	src_vq->mem_ops = ctx->dev->vb2->ops;
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	memset(dst_vq, 0, sizeof(*dst_vq));
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	dst_vq->drv_priv = ctx;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->ops = &jpeg_dec_vb2_qops;
+	dst_vq->mem_ops = ctx->dev->vb2->ops;
+
+	return vb2_queue_init(dst_vq);
+}
+
+static int queue_init_enc(void *priv, struct vb2_queue *src_vq,
+		      struct vb2_queue *dst_vq)
+{
+	struct jpeg_ctx *ctx = priv;
+	int ret;
+
+	memset(src_vq, 0, sizeof(*src_vq));
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	src_vq->drv_priv = ctx;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	src_vq->ops = &jpeg_enc_vb2_qops;
+	src_vq->mem_ops = ctx->dev->vb2->ops;
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	memset(dst_vq, 0, sizeof(*dst_vq));
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
+	dst_vq->drv_priv = ctx;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->ops = &jpeg_enc_vb2_qops;
+	dst_vq->mem_ops = ctx->dev->vb2->ops;
+
+	return vb2_queue_init(dst_vq);
+}
+static int jpeg_m2m_open(struct file *file)
+{
+	struct jpeg_dev *dev = video_drvdata(file);
+	struct jpeg_ctx *ctx = NULL;
+	int ret = 0;
+	enum jpeg_node_type node;
+
+	node = jpeg_get_node_type(file);
+
+	if (node == JPEG_NODE_INVALID) {
+		jpeg_err("cannot specify node type\n");
+		ret = -ENOENT;
+		goto err_node_type;
+	}
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	file->private_data = ctx;
+	ctx->dev = dev;
+
+	if (node == JPEG_NODE_DECODER)
+		ctx->m2m_ctx =
+			v4l2_m2m_ctx_init(dev->m2m_dev_dec, ctx,
+				queue_init_dec);
+	else
+		ctx->m2m_ctx =
+			v4l2_m2m_ctx_init(dev->m2m_dev_enc, ctx,
+				queue_init_enc);
+
+	if (IS_ERR(ctx->m2m_ctx)) {
+		int err = PTR_ERR(ctx->m2m_ctx);
+		kfree(ctx);
+		return err;
+	}
+
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+	clk_enable(dev->clk);
+	dev->vb2->resume(dev->alloc_ctx);
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_lock(dev->bus_dev, &dev->plat_dev->dev, BUSFREQ_400MHZ);
+#endif
+#else
+	pm_runtime_get_sync(&dev->plat_dev->dev);
+#endif
+#endif
+
+	return 0;
+
+err_node_type:
+	kfree(ctx);
+	return ret;
+}
+
+static int jpeg_m2m_release(struct file *file)
+{
+	struct jpeg_ctx *ctx = file->private_data;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctx->dev->slock, flags);
+#ifdef CONFIG_JPEG_V2_1
+	if (test_bit(0, &ctx->dev->hw_run) == 0)
+		del_timer_sync(&ctx->dev->watchdog_timer);
+#endif
+	v4l2_m2m_ctx_release(ctx->m2m_ctx);
+	spin_unlock_irqrestore(&ctx->dev->slock, flags);
+
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+	ctx->dev->vb2->suspend(ctx->dev->alloc_ctx);
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* Unlock bus frequency */
+	dev_unlock(ctx->dev->bus_dev, &ctx->dev->plat_dev->dev);
+#endif
+	clk_disable(ctx->dev->clk);
+#else
+	pm_runtime_put_sync(&ctx->dev->plat_dev->dev);
+#endif
+#endif
+	kfree(ctx);
+
+	return 0;
+}
+
+static unsigned int jpeg_m2m_poll(struct file *file,
+				     struct poll_table_struct *wait)
+{
+	struct jpeg_ctx *ctx = file->private_data;
+
+	return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
+}
+
+
+static int jpeg_m2m_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct jpeg_ctx *ctx = file->private_data;
+
+	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
+}
+
+static const struct v4l2_file_operations jpeg_fops = {
+	.owner		= THIS_MODULE,
+	.open		= jpeg_m2m_open,
+	.release		= jpeg_m2m_release,
+	.poll			= jpeg_m2m_poll,
+	.unlocked_ioctl = video_ioctl2,
+	.mmap		= jpeg_m2m_mmap,
+};
+
+static struct video_device jpeg_enc_videodev = {
+	.name = JPEG_ENC_NAME,
+	.fops = &jpeg_fops,
+	.minor = 12,
+	.release = video_device_release,
+};
+
+static struct video_device jpeg_dec_videodev = {
+	.name = JPEG_DEC_NAME,
+	.fops = &jpeg_fops,
+	.minor = 11,
+	.release = video_device_release,
+};
+
+static void jpeg_device_enc_run(void *priv)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct jpeg_dev *dev = ctx->dev;
+	struct jpeg_enc_param enc_param;
+	struct vb2_buffer *vb = NULL;
+	unsigned long flags;
+
+	dev = ctx->dev;
+	spin_lock_irqsave(&ctx->dev->slock, flags);
+
+	dev->mode = ENCODING;
+	enc_param = ctx->param.enc_param;
+
+	jpeg_sw_reset(dev->reg_base);
+	jpeg_set_interrupt(dev->reg_base);
+	jpeg_set_huf_table_enable(dev->reg_base, 1);
+	jpeg_set_enc_tbl(dev->reg_base);
+	jpeg_set_encode_tbl_select(dev->reg_base, enc_param.quality);
+	jpeg_set_stream_size(dev->reg_base,
+		enc_param.in_width, enc_param.in_height);
+	jpeg_set_enc_out_fmt(dev->reg_base, enc_param.out_fmt);
+	jpeg_set_enc_in_fmt(dev->reg_base, enc_param.in_fmt);
+	vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
+	jpeg_set_stream_buf_address(dev->reg_base, dev->vb2->plane_addr(vb, 0));
+
+	vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
+	if (enc_param.in_plane == 1)
+		jpeg_set_frame_buf_address(dev->reg_base,
+			enc_param.in_fmt, dev->vb2->plane_addr(vb, 0), 0, 0);
+	if (enc_param.in_plane == 2)
+		jpeg_set_frame_buf_address(dev->reg_base,
+			enc_param.in_fmt, dev->vb2->plane_addr(vb, 0),
+			dev->vb2->plane_addr(vb, 1), 0);
+	if (enc_param.in_plane == 3)
+		jpeg_set_frame_buf_address(dev->reg_base,
+			enc_param.in_fmt, dev->vb2->plane_addr(vb, 0),
+			dev->vb2->plane_addr(vb, 1), dev->vb2->plane_addr(vb, 2));
+
+	jpeg_set_encode_hoff_cnt(dev->reg_base, enc_param.out_fmt);
+
+#ifdef CONFIG_JPEG_V2_2
+		jpeg_set_timer_count(dev->reg_base, enc_param.in_width * enc_param.in_height * 32 + 0xff);
+#endif
+	jpeg_set_enc_dec_mode(dev->reg_base, ENCODING);
+
+	spin_unlock_irqrestore(&ctx->dev->slock, flags);
+}
+
+static void jpeg_device_dec_run(void *priv)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct jpeg_dev *dev = ctx->dev;
+	struct jpeg_dec_param dec_param;
+	struct vb2_buffer *vb = NULL;
+	unsigned long flags;
+
+	dev = ctx->dev;
+
+	spin_lock_irqsave(&ctx->dev->slock, flags);
+
+#ifdef CONFIG_JPEG_V2_1
+		printk(KERN_DEBUG "dec_run.\n");
+
+		if (timer_pending(&ctx->dev->watchdog_timer) == 0) {
+			ctx->dev->watchdog_timer.expires = jiffies +
+						msecs_to_jiffies(JPEG_WATCHDOG_INTERVAL);
+			add_timer(&ctx->dev->watchdog_timer);
+		}
+
+		set_bit(0, &ctx->dev->hw_run);
+#endif
+	dev->mode = DECODING;
+	dec_param = ctx->param.dec_param;
+
+	jpeg_sw_reset(dev->reg_base);
+	jpeg_set_interrupt(dev->reg_base);
+
+	jpeg_set_encode_tbl_select(dev->reg_base, 0);
+
+	vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
+	jpeg_set_stream_buf_address(dev->reg_base, dev->vb2->plane_addr(vb, 0));
+
+	vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
+	if (dec_param.out_plane == 1)
+		jpeg_set_frame_buf_address(dev->reg_base,
+			dec_param.out_fmt, dev->vb2->plane_addr(vb, 0), 0, 0);
+	else if (dec_param.out_plane == 2)
+		jpeg_set_frame_buf_address(dev->reg_base,
+		dec_param.out_fmt, dev->vb2->plane_addr(vb, 0), dev->vb2->plane_addr(vb, 1), 0);
+	else if (dec_param.out_plane == 3)
+		jpeg_set_frame_buf_address(dev->reg_base,
+			dec_param.out_fmt, dev->vb2->plane_addr(vb, 0),
+			dev->vb2->plane_addr(vb, 1), dev->vb2->plane_addr(vb, 2));
+
+	if (dec_param.out_width > 0 && dec_param.out_height > 0) {
+		if ((dec_param.out_width * 2 == dec_param.in_width) &&
+			(dec_param.out_height * 2 == dec_param.in_height))
+			jpeg_set_dec_scaling(dev->reg_base, JPEG_SCALE_2, JPEG_SCALE_2);
+		else if ((dec_param.out_width * 4 == dec_param.in_width) &&
+			(dec_param.out_height * 4 == dec_param.in_height))
+			jpeg_set_dec_scaling(dev->reg_base, JPEG_SCALE_4, JPEG_SCALE_4);
+		else
+			jpeg_set_dec_scaling(dev->reg_base, JPEG_SCALE_NORMAL, JPEG_SCALE_NORMAL);
+	}
+
+	jpeg_set_dec_out_fmt(dev->reg_base, dec_param.out_fmt);
+	jpeg_set_dec_bitstream_size(dev->reg_base, dec_param.size);
+#ifdef CONFIG_JPEG_V2_2
+	jpeg_set_timer_count(dev->reg_base, dec_param.in_width * dec_param.in_height * 8 + 0xff);
+#endif
+	jpeg_set_enc_dec_mode(dev->reg_base, DECODING);
+
+	spin_unlock_irqrestore(&ctx->dev->slock, flags);
+}
+
+static void jpeg_job_enc_abort(void *priv)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct jpeg_dev *dev = ctx->dev;
+	v4l2_m2m_get_next_job(dev->m2m_dev_enc, ctx->m2m_ctx);
+}
+
+static void jpeg_job_dec_abort(void *priv)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct jpeg_dev *dev = ctx->dev;
+	v4l2_m2m_get_next_job(dev->m2m_dev_dec, ctx->m2m_ctx);
+}
+
+static struct v4l2_m2m_ops jpeg_m2m_enc_ops = {
+	.device_run	= jpeg_device_enc_run,
+	.job_abort	= jpeg_job_enc_abort,
+};
+
+static struct v4l2_m2m_ops jpeg_m2m_dec_ops = {
+	.device_run	= jpeg_device_dec_run,
+	.job_abort	= jpeg_job_dec_abort,
+};
+
+int jpeg_int_pending(struct jpeg_dev *ctrl)
+{
+	unsigned int	int_status;
+
+	int_status = jpeg_get_int_status(ctrl->reg_base);
+	jpeg_dbg("state(%d)\n", int_status);
+
+	return int_status;
+}
+
+static irqreturn_t jpeg_irq(int irq, void *priv)
+{
+	unsigned int int_status;
+	struct vb2_buffer *src_vb, *dst_vb;
+	struct jpeg_dev *ctrl = priv;
+	struct jpeg_ctx *ctx;
+
+	spin_lock(&ctrl->slock);
+
+#ifdef CONFIG_JPEG_V2_2
+	jpeg_clean_interrupt(ctrl->reg_base);
+#endif
+
+	if (ctrl->mode == ENCODING)
+		ctx = v4l2_m2m_get_curr_priv(ctrl->m2m_dev_enc);
+	else
+		ctx = v4l2_m2m_get_curr_priv(ctrl->m2m_dev_dec);
+
+	if (ctx == 0) {
+		printk(KERN_ERR "ctx is null.\n");
+		int_status = jpeg_int_pending(ctrl);
+		jpeg_sw_reset(ctrl->reg_base);
+		goto ctx_err;
+	}
+
+	src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+	dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+
+	int_status = jpeg_int_pending(ctrl);
+
+	if (int_status) {
+		switch (int_status & 0x1f) {
+		case 0x1:
+			ctrl->irq_ret = ERR_PROT;
+			break;
+		case 0x2:
+			ctrl->irq_ret = OK_ENC_OR_DEC;
+			break;
+		case 0x4:
+			ctrl->irq_ret = ERR_DEC_INVALID_FORMAT;
+			break;
+		case 0x8:
+			ctrl->irq_ret = ERR_MULTI_SCAN;
+			break;
+		case 0x10:
+			ctrl->irq_ret = ERR_FRAME;
+			break;
+		case 0x20:
+			ctrl->irq_ret = ERR_TIME_OUT;
+			break;
+		default:
+			ctrl->irq_ret = ERR_UNKNOWN;
+			break;
+		}
+	} else {
+		ctrl->irq_ret = ERR_UNKNOWN;
+	}
+
+	if (ctrl->irq_ret == OK_ENC_OR_DEC) {
+		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
+		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
+	} else {
+		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
+		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
+	}
+
+#ifdef CONFIG_JPEG_V2_1
+		clear_bit(0, &ctx->dev->hw_run);
+#endif
+	if (ctrl->mode == ENCODING)
+		v4l2_m2m_job_finish(ctrl->m2m_dev_enc, ctx->m2m_ctx);
+	else
+		v4l2_m2m_job_finish(ctrl->m2m_dev_dec, ctx->m2m_ctx);
+ctx_err:
+	spin_unlock(&ctrl->slock);
+	return IRQ_HANDLED;
+}
+
+static int jpeg_setup_controller(struct jpeg_dev *ctrl)
+{
+	mutex_init(&ctrl->lock);
+	init_waitqueue_head(&ctrl->wq);
+
+	return 0;
+}
+
+static int jpeg_probe(struct platform_device *pdev)
+{
+	struct jpeg_dev *dev;
+	struct video_device *vfd;
+	struct resource *res;
+	int ret;
+
+	/* global structure */
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "%s: not enough memory\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	dev->plat_dev = pdev;
+
+	/* setup jpeg control */
+	ret = jpeg_setup_controller(dev);
+	if (ret) {
+		jpeg_err("failed to setup controller\n");
+		goto err_setup;
+	}
+
+	/* memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		jpeg_err("failed to get jpeg memory region resource\n");
+		ret = -ENOENT;
+		goto err_res;
+	}
+
+	res = request_mem_region(res->start, resource_size(res),
+				pdev->name);
+	if (!res) {
+		jpeg_err("failed to request jpeg io memory region\n");
+		ret = -ENOMEM;
+		goto err_region;
+	}
+
+	/* ioremap */
+	dev->reg_base = ioremap(res->start, resource_size(res));
+	if (!dev->reg_base) {
+		jpeg_err("failed to remap jpeg io region\n");
+		ret = -ENOENT;
+		goto err_map;
+	}
+
+	spin_lock_init(&dev->slock);
+	/* irq */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		jpeg_err("failed to request jpeg irq resource\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	dev->irq_no = res->start;
+	ret = request_irq(dev->irq_no, (void *)jpeg_irq,
+			IRQF_DISABLED, pdev->name, dev);
+	if (ret != 0) {
+		jpeg_err("failed to jpeg request irq\n");
+		ret = -ENOENT;
+		goto err_irq;
+	}
+
+	/* clock */
+	dev->clk = clk_get(&pdev->dev, "jpeg");
+	if (IS_ERR(dev->clk)) {
+		jpeg_err("failed to find jpeg clock source\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+#ifdef CONFIG_PM_RUNTIME
+#ifndef CONFIG_CPU_EXYNOS5250
+	pm_runtime_enable(&pdev->dev);
+#endif
+#endif
+
+	/* clock enable */
+	clk_enable(dev->clk);
+
+	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev, "Failed to register v4l2 device\n");
+		goto err_v4l2;
+	}
+
+	/* encoder */
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto err_vd_alloc_enc;
+	}
+
+	*vfd = jpeg_enc_videodev;
+	vfd->ioctl_ops = get_jpeg_enc_v4l2_ioctl_ops();
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, 12);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev,
+			 "%s(): failed to register video device\n", __func__);
+		video_device_release(vfd);
+		goto err_vd_alloc_enc;
+	}
+	v4l2_info(&dev->v4l2_dev,
+		"JPEG driver is registered to /dev/video%d\n", vfd->num);
+
+	dev->vfd_enc = vfd;
+	dev->m2m_dev_enc = v4l2_m2m_init(&jpeg_m2m_enc_ops);
+	if (IS_ERR(dev->m2m_dev_enc)) {
+		v4l2_err(&dev->v4l2_dev,
+			"failed to initialize v4l2-m2m device\n");
+		ret = PTR_ERR(dev->m2m_dev_enc);
+		goto err_m2m_init_enc;
+	}
+	video_set_drvdata(vfd, dev);
+
+	/* decoder */
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto err_vd_alloc_dec;
+	}
+
+	*vfd = jpeg_dec_videodev;
+	vfd->ioctl_ops = get_jpeg_dec_v4l2_ioctl_ops();
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, 11);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev,
+			 "%s(): failed to register video device\n", __func__);
+		video_device_release(vfd);
+		goto err_vd_alloc_dec;
+	}
+	v4l2_info(&dev->v4l2_dev,
+		"JPEG driver is registered to /dev/video%d\n", vfd->num);
+
+	dev->vfd_dec = vfd;
+	dev->m2m_dev_dec = v4l2_m2m_init(&jpeg_m2m_dec_ops);
+	if (IS_ERR(dev->m2m_dev_dec)) {
+		v4l2_err(&dev->v4l2_dev,
+			"failed to initialize v4l2-m2m device\n");
+		ret = PTR_ERR(dev->m2m_dev_dec);
+		goto err_m2m_init_dec;
+	}
+	video_set_drvdata(vfd, dev);
+
+	platform_set_drvdata(pdev, dev);
+
+#ifdef CONFIG_VIDEOBUF2_CMA_PHYS
+	dev->vb2 = &jpeg_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+	dev->vb2 = &jpeg_vb2_ion;
+#endif
+	dev->alloc_ctx = dev->vb2->init(dev);
+
+	if (IS_ERR(dev->alloc_ctx)) {
+		ret = PTR_ERR(dev->alloc_ctx);
+		goto err_video_reg;
+	}
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* To lock bus frequency in OPP mode */
+	dev->bus_dev = dev_get("exynos-busfreq");
+#endif
+
+#ifdef CONFIG_JPEG_V2_1
+		dev->watchdog_workqueue = create_singlethread_workqueue(JPEG_NAME);
+		INIT_WORK(&dev->watchdog_work, jpeg_watchdog_worker);
+		atomic_set(&dev->watchdog_cnt, 0);
+		init_timer(&dev->watchdog_timer);
+		dev->watchdog_timer.data = (unsigned long)dev;
+		dev->watchdog_timer.function = jpeg_watchdog;
+#endif
+	/* clock disable */
+	clk_disable(dev->clk);
+
+	return 0;
+
+err_video_reg:
+	v4l2_m2m_release(dev->m2m_dev_dec);
+err_m2m_init_dec:
+	video_unregister_device(dev->vfd_dec);
+	video_device_release(dev->vfd_dec);
+err_vd_alloc_dec:
+	v4l2_m2m_release(dev->m2m_dev_enc);
+err_m2m_init_enc:
+	video_unregister_device(dev->vfd_enc);
+	video_device_release(dev->vfd_enc);
+err_vd_alloc_enc:
+	v4l2_device_unregister(&dev->v4l2_dev);
+err_v4l2:
+	clk_disable(dev->clk);
+	clk_put(dev->clk);
+err_clk:
+	free_irq(dev->irq_no, NULL);
+err_irq:
+	iounmap(dev->reg_base);
+err_map:
+err_region:
+	kfree(res);
+err_res:
+	mutex_destroy(&dev->lock);
+err_setup:
+	kfree(dev);
+err_alloc:
+	return ret;
+
+}
+
+static int jpeg_remove(struct platform_device *pdev)
+{
+	struct jpeg_dev *dev = platform_get_drvdata(pdev);
+#ifdef CONFIG_JPEG_V2_1
+		del_timer_sync(&dev->watchdog_timer);
+		flush_workqueue(dev->watchdog_workqueue);
+		destroy_workqueue(dev->watchdog_workqueue);
+#endif
+	v4l2_m2m_release(dev->m2m_dev_enc);
+	video_unregister_device(dev->vfd_enc);
+
+	v4l2_m2m_release(dev->m2m_dev_dec);
+	video_unregister_device(dev->vfd_dec);
+
+	v4l2_device_unregister(&dev->v4l2_dev);
+
+	dev->vb2->cleanup(dev->alloc_ctx);
+
+	free_irq(dev->irq_no, pdev);
+	mutex_destroy(&dev->lock);
+	iounmap(dev->reg_base);
+
+	clk_put(dev->clk);
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_unlock(dev->bus_dev, &pdev->dev);
+#endif
+#else
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+#endif
+#endif
+	kfree(dev);
+	return 0;
+}
+
+static int jpeg_suspend(struct platform_device *pdev, pm_message_t state)
+{
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+	struct jpeg_dev *dev = platform_get_drvdata(pdev);
+
+	if (dev->ctx) {
+		dev->vb2->suspend(dev->alloc_ctx);
+		clk_disable(dev->clk);
+	}
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_unlock(dev->bus_dev, &pdev->dev);
+#endif
+#else
+	pm_runtime_put_sync(&pdev->dev);
+#endif
+#endif
+	return 0;
+}
+
+static int jpeg_resume(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+	struct jpeg_dev *dev = platform_get_drvdata(pdev);
+
+	if (dev->ctx) {
+	clk_enable(dev->clk);
+		dev->vb2->resume(dev->alloc_ctx);
+	}
+#else
+	pm_runtime_get_sync(&pdev->dev);
+#endif
+#endif
+	return 0;
+}
+
+int jpeg_suspend_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+	pm_message_t state;
+
+	state.event = 0;
+	pdev = to_platform_device(dev);
+	ret = jpeg_suspend(pdev, state);
+
+	return 0;
+}
+
+int jpeg_resume_pd(struct device *dev)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = to_platform_device(dev);
+	ret = jpeg_resume(pdev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int jpeg_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct jpeg_dev *jpeg_drv = platform_get_drvdata(pdev);
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_unlock(jpeg_drv->bus_dev, dev);
+#endif
+	jpeg_drv->vb2->suspend(jpeg_drv->alloc_ctx);
+	/* clock disable */
+	clk_disable(jpeg_drv->clk);
+	return 0;
+}
+
+static int jpeg_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct jpeg_dev *jpeg_drv = platform_get_drvdata(pdev);
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* lock bus frequency */
+	dev_lock(jpeg_drv->bus_dev, &jpeg_drv->plat_dev->dev, BUSFREQ_400MHZ);
+#endif
+	clk_enable(jpeg_drv->clk);
+	jpeg_drv->vb2->resume(jpeg_drv->alloc_ctx);
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops jpeg_pm_ops = {
+	.suspend	= jpeg_suspend_pd,
+	.resume		= jpeg_resume_pd,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_suspend = jpeg_runtime_suspend,
+	.runtime_resume = jpeg_runtime_resume,
+#endif
+};
+static struct platform_driver jpeg_driver = {
+	.probe		= jpeg_probe,
+	.remove		= jpeg_remove,
+#if defined (CONFIG_CPU_EXYNOS5250)
+	.suspend	= jpeg_suspend,
+	.resume		= jpeg_resume,
+#else
+#ifndef CONFIG_PM_RUNTIME
+	.suspend	= jpeg_suspend,
+	.resume		= jpeg_resume,
+#endif
+#endif
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= JPEG_NAME,
+#ifdef CONFIG_PM_RUNTIME
+#if defined (CONFIG_CPU_EXYNOS5250)
+		.pm = NULL,
+#else
+		.pm = &jpeg_pm_ops,
+#endif
+#else
+		.pm = NULL,
+#endif
+	},
+};
+
+static int __init jpeg_init(void)
+{
+	printk(KERN_CRIT "Initialize JPEG driver\n");
+
+	platform_driver_register(&jpeg_driver);
+
+	return 0;
+}
+
+static void __exit jpeg_exit(void)
+{
+	platform_driver_unregister(&jpeg_driver);
+}
+
+module_init(jpeg_init);
+module_exit(jpeg_exit);
+
+MODULE_AUTHOR("ym.song@samsung.com>");
+MODULE_DESCRIPTION("JPEG v2.x H/W Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.h b/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.h
new file mode 100644
index 0000000..a708293
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.h
@@ -0,0 +1,26 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.h
+  *
+  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+  * http://www.samsung.com/
+  *
+  * Header file for Samsung Jpeg v2.x Interface driver
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+ */
+
+#ifndef __JPEG_DEV_H__
+#define __JPEG_DEV_H__
+
+#define JPEG_NAME		"s5p-jpeg"
+#define JPEG_ENC_NAME		"video12"
+#define JPEG_DEC_NAME		"video11"
+
+#define JPEG_WATCHDOG_CNT 10
+#define JPEG_WATCHDOG_INTERVAL   1000
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#define BUSFREQ_400MHZ	400266
+#endif
+
+#endif /*__JPEG_DEV_H__*/
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_enc.c b/drivers/media/video/samsung/jpeg_v2x/jpeg_enc.c
new file mode 100644
index 0000000..98dba01
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_enc.c
@@ -0,0 +1,572 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Core file for Samsung Jpeg v2.x Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+
+#include <asm/page.h>
+
+#include <plat/regs_jpeg_v2_x.h>
+#include <mach/irqs.h>
+
+#include <media/v4l2-ioctl.h>
+
+#include "jpeg_core.h"
+#include "jpeg_dev.h"
+
+#include "jpeg_mem.h"
+#include "jpeg_regs.h"
+
+static struct jpeg_fmt formats[] = {
+	{
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_444,
+		.depth		= {8},
+		.color		= JPEG_444,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_422,
+		.depth		= {8},
+		.color		= JPEG_422,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_420,
+		.depth		= {8},
+		.color		= JPEG_420,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "JPEG compressed format",
+		.fourcc		= V4L2_PIX_FMT_JPEG_GRAY,
+		.depth		= {8},
+		.color		= JPEG_GRAY,
+		.memplanes	= 1,
+		.types		= M2M_CAPTURE,
+	}, {
+		.name		= "RGB565",
+		.fourcc		= V4L2_PIX_FMT_RGB565X,
+		.depth		= {16},
+		.color		= RGB_565,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_YUV444_2P,
+		.depth		= {8, 16},
+		.color		= YCBCR_444_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_YVU444_2P,
+		.depth		= {8, 16},
+		.color		= YCRCB_444_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:4:4 packed, Y/Cb/Cr",
+		.fourcc		= V4L2_PIX_FMT_YUV444_3P,
+		.depth		= {8, 8, 8},
+		.color		= YCBCR_444_3P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "XRGB-8-8-8-8, 32 bpp",
+		.fourcc		= V4L2_PIX_FMT_RGB32,
+		.depth		= {32},
+		.color		= RGB_888,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCrYCb",
+		.fourcc		= V4L2_PIX_FMT_YVYU,
+		.depth		= {16},
+		.color		= YCRYCB_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:2 packed, YCbYCr",
+		.fourcc		= V4L2_PIX_FMT_YUYV,
+		.depth		= {16},
+		.color		= YCBYCR_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_NV61,
+		.depth		= {8, 8},
+		.color		= YCRCB_422_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:2 planar, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_NV16,
+		.depth		= {8, 8},
+		.color		= YCBCR_422_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CbCr",
+		.fourcc		= V4L2_PIX_FMT_NV12,
+		.depth		= {8, 4},
+		.color		= YCBCR_420_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:0 planar, Y/CrCb",
+		.fourcc		= V4L2_PIX_FMT_NV21,
+		.depth		= {8, 4},
+		.color		= YCRCB_420_2P,
+		.memplanes	= 2,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:0 contiguous 3-planar, Y/Cb/Cr",
+		.fourcc		= V4L2_PIX_FMT_YUV420,
+		.depth		= {8, 2, 2},
+		.color		= YCBCR_420_3P,
+		.memplanes	= 3,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:0 contiguous 3-planar, Y/Cr/Cb",
+		.fourcc		= V4L2_PIX_FMT_YVU420,
+		.depth		= {8, 2, 2},
+		.color		= YCRCB_420_3P,
+		.memplanes	= 3,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "Gray",
+		.fourcc		= V4L2_PIX_FMT_GREY,
+		.depth		= {8},
+		.color		= GRAY,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	},
+#ifdef CONFIG_JPEG_V2_2
+	{
+		.name		= "YUV 4:2:2 packed, CrYCbY",
+		.fourcc		= V4L2_PIX_FMT_VYUY,
+		.depth		= {16},
+		.color		= CRYCBY_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "YUV 4:2:2 packed, CbYCrY",
+		.fourcc		= V4L2_PIX_FMT_UYVY,
+		.depth		= {16},
+		.color		= CRYCBY_422_1P,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	}, {
+		.name		= "XBGR-8-8-8-8, 32 bpp",
+		.fourcc		= V4L2_PIX_FMT_BGR32,
+		.depth		= {32},
+		.color		= BGR_888,
+		.memplanes	= 1,
+		.types		= M2M_OUTPUT,
+	},
+#endif
+};
+
+static struct jpeg_fmt *find_format(struct v4l2_format *f)
+{
+	struct jpeg_fmt *fmt;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+		fmt = &formats[i];
+		if (fmt->fourcc == f->fmt.pix_mp.pixelformat)
+			break;
+	}
+
+	return (i == ARRAY_SIZE(formats)) ? NULL : fmt;
+}
+
+static int jpeg_enc_vidioc_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct jpeg_ctx *ctx = file->private_data;
+	struct jpeg_dev *dev = ctx->dev;
+
+	strncpy(cap->driver, dev->plat_dev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->plat_dev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
+		V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
+	return 0;
+}
+
+int jpeg_enc_vidioc_enum_fmt(struct file *file, void *priv,
+				struct v4l2_fmtdesc *f)
+{
+	struct jpeg_fmt *fmt;
+
+	if (f->index >= ARRAY_SIZE(formats))
+		return -EINVAL;
+
+	fmt = &formats[f->index];
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+int jpeg_enc_vidioc_g_fmt(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct v4l2_pix_format_mplane *pixm;
+	struct jpeg_enc_param *enc_param = &ctx->param.enc_param;
+
+	pixm = &f->fmt.pix_mp;
+
+	pixm->field	= V4L2_FIELD_NONE;
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		pixm->pixelformat =
+			enc_param->in_fmt;
+		pixm->num_planes =
+			enc_param->in_plane;
+		pixm->width =
+			enc_param->in_width;
+		pixm->height =
+			enc_param->in_height;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		pixm->pixelformat =
+			enc_param->out_fmt;
+		pixm->num_planes =
+			enc_param->out_plane;
+		pixm->width =
+			enc_param->out_width;
+		pixm->height =
+			enc_param->out_height;
+	} else {
+		v4l2_err(&ctx->dev->v4l2_dev,
+			"Wrong buffer/video queue type (%d)\n", f->type);
+	}
+
+	return 0;
+}
+
+static int jpeg_enc_vidioc_try_fmt(struct file *file, void *priv,
+			       struct v4l2_format *f)
+{
+	struct jpeg_fmt *fmt;
+	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
+	struct jpeg_ctx *ctx = priv;
+	int i;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+		f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		return -EINVAL;
+
+	fmt = find_format(f);
+
+	if (!fmt) {
+		v4l2_err(&ctx->dev->v4l2_dev,
+			 "Fourcc format (0x%08x) invalid.\n",
+			 f->fmt.pix.pixelformat);
+		return -EINVAL;
+	}
+
+	if (pix->field == V4L2_FIELD_ANY)
+		pix->field = V4L2_FIELD_NONE;
+	else if (V4L2_FIELD_NONE != pix->field)
+		return -EINVAL;
+
+
+	pix->num_planes = fmt->memplanes;
+
+	for (i = 0; i < pix->num_planes; ++i) {
+		int bpl = pix->plane_fmt[i].bytesperline;
+
+		jpeg_dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
+		    i, bpl, fmt->depth[i], pix->width, pix->height);
+
+		if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
+			bpl = (pix->width * fmt->depth[i]) >> 3;
+
+		if (!pix->plane_fmt[i].sizeimage)
+			pix->plane_fmt[i].sizeimage = pix->height * bpl;
+
+		pix->plane_fmt[i].bytesperline = bpl;
+
+		jpeg_dbg("[%d]: bpl: %d, sizeimage: %d",
+		    i, pix->plane_fmt[i].bytesperline,
+		    pix->plane_fmt[i].sizeimage);
+	}
+
+	if (f->fmt.pix.height > MAX_JPEG_HEIGHT)
+		f->fmt.pix.height = MAX_JPEG_HEIGHT;
+
+	if (f->fmt.pix.width > MAX_JPEG_WIDTH)
+		f->fmt.pix.width = MAX_JPEG_WIDTH;
+
+	return 0;
+}
+
+static int jpeg_enc_vidioc_s_fmt_cap(struct file *file, void *priv,
+				struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+	struct v4l2_pix_format_mplane *pix;
+	struct jpeg_fmt *fmt;
+	int ret;
+	int i;
+
+	ret = jpeg_enc_vidioc_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&ctx->dev->v4l2_dev, "queue (%d) busy\n", f->type);
+		return -EBUSY;
+	}
+
+	pix = &f->fmt.pix_mp;
+	fmt = find_format(f);
+
+	for (i = 0; i < fmt->memplanes; i++)
+		ctx->payload[i] =
+			pix->plane_fmt[i].bytesperline * pix->height;
+
+	ctx->param.enc_param.out_width = pix->height;
+	ctx->param.enc_param.out_height = pix->width;
+	ctx->param.enc_param.out_plane = fmt->memplanes;
+	ctx->param.enc_param.out_depth = fmt->depth[0];
+	ctx->param.enc_param.out_fmt = fmt->color;
+
+	return 0;
+}
+
+static int jpeg_enc_vidioc_s_fmt_out(struct file *file, void *priv,
+			struct v4l2_format *f)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+	struct v4l2_pix_format_mplane *pix;
+	struct jpeg_fmt *fmt;
+	int ret;
+	int i;
+
+	ret = jpeg_enc_vidioc_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&ctx->dev->v4l2_dev, "queue (%d) busy\n", f->type);
+		return -EBUSY;
+	}
+
+	/* TODO: width & height has to be multiple of two */
+	pix = &f->fmt.pix_mp;
+	fmt = find_format(f);
+
+	for (i = 0; i < fmt->memplanes; i++) {
+		ctx->payload[i] =
+			pix->plane_fmt[i].bytesperline * pix->height;
+		ctx->param.enc_param.in_depth[i] = fmt->depth[i];
+	}
+	ctx->param.enc_param.in_width = pix->width;
+	ctx->param.enc_param.in_height = pix->height;
+	ctx->param.enc_param.in_plane = fmt->memplanes;
+	ctx->param.enc_param.in_fmt = fmt->color;
+
+	return 0;
+}
+
+static int jpeg_enc_m2m_reqbufs(struct file *file, void *priv,
+			  struct v4l2_requestbuffers *reqbufs)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct vb2_queue *vq;
+
+	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, reqbufs->type);
+	if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+		ctx->dev->vb2->set_cacheable(ctx->dev->alloc_ctx, ctx->input_cacheable);
+	else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+		ctx->dev->vb2->set_cacheable(ctx->dev->alloc_ctx, ctx->output_cacheable);
+
+	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
+}
+
+static int jpeg_enc_m2m_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_enc_m2m_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+
+	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_enc_m2m_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int jpeg_enc_m2m_streamon(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
+}
+
+static int jpeg_enc_m2m_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct jpeg_ctx *ctx = priv;
+	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
+}
+
+static int jpeg_enc_vidioc_g_ctrl(struct file *file, void *priv,
+			    struct v4l2_control *ctrl)
+{
+	struct jpeg_ctx *ctx = priv;
+	struct jpeg_dev *dev = ctx->dev;
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_JPEG_ENCODEDSIZE:
+		ctrl->value = jpeg_get_stream_size(dev->reg_base);
+		break;
+	default:
+		break;
+	}
+	return ctrl->value;
+}
+
+static int vidioc_enc_s_jpegcomp(struct file *file, void *priv,
+			struct v4l2_jpegcompression *jpegcomp)
+{
+	struct jpeg_ctx *ctx = priv;
+
+	ctx->param.enc_param.quality = jpegcomp->quality;
+	return 0;
+}
+
+static int vidioc_enc_g_jpegcomp(struct file *file, void *priv,
+			struct v4l2_jpegcompression *jpegcomp)
+{
+	struct jpeg_ctx *ctx = priv;
+
+	jpegcomp->quality = ctx->param.enc_param.quality;
+	return 0;
+}
+
+static int jpeg_enc_vidioc_s_ctrl(struct file *file, void *priv,
+			struct v4l2_control *ctrl)
+{
+	struct jpeg_ctx *ctx = priv;
+/*
+*	0 : input/output noncacheable
+*	1 : input/output cacheable
+*	2 : input cacheable / output noncacheable
+*	3 : input noncacheable / output cacheable
+*/
+	switch (ctrl->id) {
+	case V4L2_CID_CACHEABLE:
+		if (ctrl->value == 0) {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 0;
+		} else if (ctrl->value == 1) {
+			ctx->input_cacheable = 1;
+			ctx->output_cacheable = 1;
+		} else if (ctrl->value == 2) {
+			ctx->input_cacheable = 1;
+			ctx->output_cacheable = 0;
+		} else if (ctrl->value == 3) {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 1;
+		} else {
+			ctx->input_cacheable = 0;
+			ctx->output_cacheable = 0;
+		}
+		break;
+	default:
+		v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
+		break;
+	}
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops jpeg_enc_ioctl_ops = {
+	.vidioc_querycap		= jpeg_enc_vidioc_querycap,
+
+	.vidioc_enum_fmt_vid_cap_mplane	= jpeg_enc_vidioc_enum_fmt,
+	.vidioc_enum_fmt_vid_out_mplane	= jpeg_enc_vidioc_enum_fmt,
+
+	.vidioc_g_fmt_vid_cap_mplane	= jpeg_enc_vidioc_g_fmt,
+	.vidioc_g_fmt_vid_out_mplane	= jpeg_enc_vidioc_g_fmt,
+
+	.vidioc_try_fmt_vid_cap_mplane		= jpeg_enc_vidioc_try_fmt,
+	.vidioc_try_fmt_vid_out_mplane		= jpeg_enc_vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap_mplane		= jpeg_enc_vidioc_s_fmt_cap,
+	.vidioc_s_fmt_vid_out_mplane		= jpeg_enc_vidioc_s_fmt_out,
+
+	.vidioc_reqbufs		= jpeg_enc_m2m_reqbufs,
+	.vidioc_querybuf		= jpeg_enc_m2m_querybuf,
+	.vidioc_qbuf			= jpeg_enc_m2m_qbuf,
+	.vidioc_dqbuf			= jpeg_enc_m2m_dqbuf,
+	.vidioc_streamon		= jpeg_enc_m2m_streamon,
+	.vidioc_streamoff		= jpeg_enc_m2m_streamoff,
+	.vidioc_g_ctrl			= jpeg_enc_vidioc_g_ctrl,
+	.vidioc_g_jpegcomp		= vidioc_enc_g_jpegcomp,
+	.vidioc_s_jpegcomp		= vidioc_enc_s_jpegcomp,
+	.vidioc_s_ctrl			= jpeg_enc_vidioc_s_ctrl,
+};
+const struct v4l2_ioctl_ops *get_jpeg_enc_v4l2_ioctl_ops(void)
+{
+	return &jpeg_enc_ioctl_ops;
+}
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.c b/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.c
new file mode 100644
index 0000000..994da07
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.c
@@ -0,0 +1,79 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Managent memory of the jpeg driver for encoder/docoder.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/errno.h>
+#include <linux/vmalloc.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/page.h>
+
+#include <linux/cma.h>
+
+#include "jpeg_mem.h"
+#include "jpeg_core.h"
+
+#if defined(CONFIG_VIDEOBUF2_ION)
+#define	JPEG_ION_NAME	"s5p-jpeg"
+#endif
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+void *jpeg_cma_init(struct jpeg_dev *dev)
+{
+	return vb2_cma_phys_init(&dev->plat_dev->dev, NULL, SZ_8K, false);
+}
+
+int jpeg_cma_resume(void *alloc_ctx)
+{
+	return 1;
+}
+void jpeg_cma_suspend(void *alloc_ctx) {}
+
+const struct jpeg_vb2 jpeg_vb2_cma = {
+	.ops		= &vb2_cma_phys_memops,
+	.init		= jpeg_cma_init,
+	.cleanup	= vb2_cma_phys_cleanup,
+	.plane_addr	= vb2_cma_phys_plane_paddr,
+	.resume		= jpeg_cma_resume,
+	.suspend	= jpeg_cma_suspend,
+	.cache_flush	= vb2_cma_phys_cache_flush,
+	.set_cacheable	= vb2_cma_phys_set_cacheable,
+};
+#elif defined(CONFIG_VIDEOBUF2_ION)
+static void *jpeg_ion_init(struct jpeg_dev *dev)
+{
+	return vb2_ion_create_context(&dev->plat_dev->dev, SZ_8K,
+					VB2ION_CTX_VMCONTIG | VB2ION_CTX_IOMMU);
+}
+
+static unsigned long jpeg_vb2_plane_addr(struct vb2_buffer *vb, u32 plane_no)
+{
+	void *cookie = vb2_plane_cookie(vb, plane_no);
+	dma_addr_t dva = 0;
+
+	WARN_ON(vb2_ion_dma_address(cookie, &dva) != 0);
+
+	return dva;
+}
+
+const struct jpeg_vb2 jpeg_vb2_ion = {
+	.ops		= &vb2_ion_memops,
+	.init		= jpeg_ion_init,
+	.cleanup	= vb2_ion_destroy_context,
+	.plane_addr	= jpeg_vb2_plane_addr,
+	.resume		= vb2_ion_attach_iommu,
+	.suspend	= vb2_ion_detach_iommu,
+	.cache_flush	= vb2_ion_cache_flush,
+	.set_cacheable	= vb2_ion_set_cached,
+};
+#endif
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.h b/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.h
new file mode 100644
index 0000000..d912628
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.h
@@ -0,0 +1,39 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_mem.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Definition for Operation of Jpeg encoder/docoder with memory
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_MEM_H__
+#define __JPEG_MEM_H__
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/cma.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/file.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-memops.h>
+
+#include <asm/cacheflush.h>
+
+#if defined(CONFIG_VIDEOBUF2_CMA_PHYS)
+extern const struct jpeg_vb2 jpeg_vb2_cma;
+#elif defined(CONFIG_VIDEOBUF2_ION)
+extern const struct jpeg_vb2 jpeg_vb2_ion;
+#endif
+
+#define MAX_JPEG_WIDTH	3264
+#define MAX_JPEG_HEIGHT	2448
+
+#endif /* __JPEG_MEM_H__ */
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.c b/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.c
new file mode 100644
index 0000000..e3300cc
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.c
@@ -0,0 +1,629 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register interface file for jpeg v2.x driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <plat/regs_jpeg_v2_x.h>
+#include <plat/cpu.h>
+
+#include "jpeg_regs.h"
+#include "jpeg_conf.h"
+#include "jpeg_core.h"
+
+void jpeg_sw_reset(void __iomem *base)
+{
+	unsigned int reg;
+
+#ifdef CONFIG_JPEG_V2_2
+	reg = readl(base + S5P_JPEG_CNTL_REG);
+	writel((reg & S5P_JPEG_ENC_DEC_MODE_MASK),
+			base + S5P_JPEG_CNTL_REG);
+#endif
+	reg = readl(base + S5P_JPEG_CNTL_REG);
+	writel(reg & ~S5P_JPEG_SOFT_RESET_HI,
+			base + S5P_JPEG_CNTL_REG);
+
+	ndelay(100000);
+
+	writel(reg | S5P_JPEG_SOFT_RESET_HI,
+			base + S5P_JPEG_CNTL_REG);
+}
+
+void jpeg_set_enc_dec_mode(void __iomem *base, enum jpeg_mode mode)
+{
+	unsigned int reg;
+
+	reg = readl(base + S5P_JPEG_CNTL_REG);
+	/* set jpeg mod register */
+	if (mode == DECODING) {
+		writel((reg & S5P_JPEG_ENC_DEC_MODE_MASK) | S5P_JPEG_DEC_MODE,
+			base + S5P_JPEG_CNTL_REG);
+	} else {/* encode */
+		writel((reg & S5P_JPEG_ENC_DEC_MODE_MASK) | S5P_JPEG_ENC_MODE,
+			base + S5P_JPEG_CNTL_REG);
+	}
+}
+
+void jpeg_set_dec_out_fmt(void __iomem *base,
+					enum jpeg_frame_format out_fmt)
+{
+	unsigned int reg = 0;
+
+	writel(0, base + S5P_JPEG_IMG_FMT_REG); /* clear */
+
+	/* set jpeg deocde ouput format register */
+	switch (out_fmt) {
+	case GRAY:
+		reg = S5P_JPEG_DEC_GRAY_IMG  |
+				S5P_JPEG_GRAY_IMG_IP;
+		break;
+
+	case RGB_565:
+		reg = S5P_JPEG_DEC_RGB_IMG |
+				S5P_JPEG_RGB_IP_RGB_16BIT_IMG;
+		break;
+
+	case YCRCB_444_2P:
+		reg = S5P_JPEG_DEC_YUV_444_IMG |
+				S5P_JPEG_YUV_444_IP_YUV_444_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_444_2P:
+		reg = S5P_JPEG_DEC_YUV_444_IMG |
+				S5P_JPEG_YUV_444_IP_YUV_444_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBCR_444_3P:
+		reg = S5P_JPEG_DEC_YUV_444_IMG |
+			S5P_JPEG_YUV_444_IP_YUV_444_3P_IMG;
+		break;
+#if defined (CONFIG_JPEG_V2_2)
+	case RGB_888:
+		reg = S5P_JPEG_DEC_RGB_IMG |
+			S5P_JPEG_RGB_IP_RGB_32BIT_IMG
+				|S5P_JPEG_ENC_FMT_RGB;
+		break;
+	case BGR_888:
+		reg = S5P_JPEG_DEC_RGB_IMG |
+			S5P_JPEG_RGB_IP_RGB_32BIT_IMG
+				|S5P_JPEG_ENC_FMT_BGR;
+			break;
+
+	case CRYCBY_422_1P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+				S5P_JPEG_ENC_FMT_VYUY;
+			break;
+
+	case CBYCRY_422_1P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+				S5P_JPEG_ENC_FMT_UYVY;
+			break;
+	case YCRYCB_422_1P:
+			reg = S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+				S5P_JPEG_ENC_FMT_YVYU;
+		break;
+	case YCBYCR_422_1P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_ENC_FMT_YUYV;
+		break;
+
+#elif defined (CONFIG_JPEG_V2_1)
+	case RGB_888:
+		reg = S5P_JPEG_DEC_RGB_IMG |
+			S5P_JPEG_RGB_IP_RGB_32BIT_IMG;
+		break;
+	case YCRYCB_422_1P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+	case YCBYCR_422_1P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+#endif
+
+	case YCRCB_422_2P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_422_2P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBYCR_422_3P:
+		reg = S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_3P_IMG;
+		break;
+
+	case YCRCB_420_2P:
+		reg = S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_420_2P:
+		reg = S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBCR_420_3P:
+	case YCRCB_420_3P:
+		reg = S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_3P_IMG;
+		break;
+
+	default:
+		break;
+	}
+
+	writel(reg, base + S5P_JPEG_IMG_FMT_REG);
+}
+
+void jpeg_set_enc_in_fmt(void __iomem *base,
+					enum jpeg_frame_format in_fmt)
+{
+	unsigned int reg;
+
+	reg = readl(base + S5P_JPEG_IMG_FMT_REG) &
+			S5P_JPEG_ENC_IN_FMT_MASK; /* clear except enc format */
+
+	switch (in_fmt) {
+	case GRAY:
+		reg = reg | S5P_JPEG_ENC_GRAY_IMG | S5P_JPEG_GRAY_IMG_IP;
+		break;
+
+	case RGB_565:
+		reg = reg | S5P_JPEG_ENC_RGB_IMG |
+				S5P_JPEG_RGB_IP_RGB_16BIT_IMG;
+		break;
+
+	case YCRCB_444_2P:
+		reg = reg | S5P_JPEG_ENC_YUV_444_IMG |
+				S5P_JPEG_YUV_444_IP_YUV_444_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_444_2P:
+		reg = reg | S5P_JPEG_ENC_YUV_444_IMG |
+				S5P_JPEG_YUV_444_IP_YUV_444_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBCR_444_3P:
+		reg = reg | S5P_JPEG_ENC_YUV_444_IMG |
+				S5P_JPEG_YUV_444_IP_YUV_444_3P_IMG;
+		break;
+
+#if defined (CONFIG_JPEG_V2_2)
+	case RGB_888:
+		reg = reg | S5P_JPEG_DEC_RGB_IMG |
+				S5P_JPEG_RGB_IP_RGB_32BIT_IMG
+				|S5P_JPEG_ENC_FMT_RGB;
+		break;
+	case BGR_888:
+		reg = reg | S5P_JPEG_DEC_RGB_IMG |
+				S5P_JPEG_RGB_IP_RGB_32BIT_IMG
+				|S5P_JPEG_ENC_FMT_BGR;
+		break;
+	case CRYCBY_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+				S5P_JPEG_ENC_FMT_VYUY;
+		break;
+	case CBYCRY_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+				S5P_JPEG_ENC_FMT_UYVY;
+		break;
+
+	case YCRYCB_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_ENC_FMT_YVYU;
+		break;
+	case YCBYCR_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_ENC_FMT_YUYV;
+		break;
+
+#elif defined (CONFIG_JPEG_V2_1)
+	case RGB_888:
+		reg = reg | S5P_JPEG_ENC_RGB_IMG |
+				S5P_JPEG_RGB_IP_RGB_32BIT_IMG;
+		break;
+	case YCRYCB_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+	case YCBYCR_422_1P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+			S5P_JPEG_YUV_422_IP_YUV_422_1P_IMG |
+			S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+#endif
+
+	case YCRCB_422_2P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_422_2P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBYCR_422_3P:
+		reg = reg | S5P_JPEG_DEC_YUV_422_IMG |
+				S5P_JPEG_YUV_422_IP_YUV_422_3P_IMG;
+		break;
+
+	case YCRCB_420_2P:
+		reg = reg | S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CrCb;
+		break;
+
+	case YCBCR_420_2P:
+		reg = reg | S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_2P_IMG |
+				S5P_JPEG_SWAP_CHROMA_CbCr;
+		break;
+
+	case YCBCR_420_3P:
+	case YCRCB_420_3P:
+		reg = reg | S5P_JPEG_DEC_YUV_420_IMG |
+				S5P_JPEG_YUV_420_IP_YUV_420_3P_IMG;
+		break;
+
+	default:
+		break;
+
+	}
+
+	writel(reg, base + S5P_JPEG_IMG_FMT_REG);
+
+}
+
+void jpeg_set_enc_out_fmt(void __iomem *base,
+					enum jpeg_stream_format out_fmt)
+{
+	unsigned int reg;
+
+	reg = readl(base + S5P_JPEG_IMG_FMT_REG) &
+			~S5P_JPEG_ENC_FMT_MASK; /* clear enc format */
+
+	switch (out_fmt) {
+	case JPEG_GRAY:
+		reg = reg | S5P_JPEG_ENC_FMT_GRAY;
+		break;
+
+	case JPEG_444:
+		reg = reg | S5P_JPEG_ENC_FMT_YUV_444;
+		break;
+
+	case JPEG_422:
+		reg = reg | S5P_JPEG_ENC_FMT_YUV_422;
+		break;
+
+	case JPEG_420:
+		reg = reg | S5P_JPEG_ENC_FMT_YUV_420;
+		break;
+
+	default:
+		break;
+	}
+
+	writel(reg, base + S5P_JPEG_IMG_FMT_REG);
+}
+
+void jpeg_set_enc_tbl(void __iomem *base)
+{
+	int i;
+
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)ITU_Q_tbl[0][i],
+			base + S5P_JPEG_QUAN_TBL_ENTRY_REG + (i*0x04));
+	}
+
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)ITU_Q_tbl[1][i],
+			base + S5P_JPEG_QUAN_TBL_ENTRY_REG + 0x40 + (i*0x04));
+	}
+
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)ITU_Q_tbl[2][i],
+			base + S5P_JPEG_QUAN_TBL_ENTRY_REG + 0x80 + (i*0x04));
+	}
+
+	for (i = 0; i < 16; i++) {
+		writel((unsigned int)ITU_Q_tbl[3][i],
+			base + S5P_JPEG_QUAN_TBL_ENTRY_REG + 0xc0 + (i*0x04));
+	}
+
+	for (i = 0; i < 4; i++) {
+		writel((unsigned int)ITU_H_tbl_len_DC_luminance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + (i*0x04));
+	}
+
+	for (i = 0; i < 3; i++) {
+		writel((unsigned int)ITU_H_tbl_val_DC_luminance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x10 + (i*0x04));
+	}
+
+	for (i = 0; i < 4; i++) {
+		writel((unsigned int)ITU_H_tbl_len_DC_chrominance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x20 + (i*0x04));
+	}
+
+	for (i = 0; i < 3; i++) {
+		writel((unsigned int)ITU_H_tbl_val_DC_chrominance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x30 + (i*0x04));
+	}
+
+	for (i = 0; i < 4; i++) {
+		writel((unsigned int)ITU_H_tbl_len_AC_luminance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x40 + (i*0x04));
+	}
+
+	for (i = 0; i < 41; i++) {
+		writel((unsigned int)ITU_H_tbl_val_AC_luminance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x50 + (i*0x04));
+	}
+
+	for (i = 0; i < 4; i++) {
+		writel((unsigned int)ITU_H_tbl_len_AC_chrominance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x100 + (i*0x04));
+	}
+
+	for (i = 0; i < 41; i++) {
+		writel((unsigned int)ITU_H_tbl_val_AC_chrominance[i],
+			base + S5P_JPEG_HUFF_TBL_ENTRY_REG + 0x110 + (i*0x04));
+	}
+
+}
+
+void jpeg_set_interrupt(void __iomem *base)
+{
+	unsigned int reg;
+	reg = readl(base + S5P_JPEG_INT_EN_REG) & ~S5P_JPEG_INT_EN_MASK;
+	writel(S5P_JPEG_INT_EN_ALL, base + S5P_JPEG_INT_EN_REG);
+}
+
+void jpeg_clean_interrupt(void __iomem *base)
+{
+	writel(0, base + S5P_JPEG_INT_EN_REG);
+}
+
+unsigned int jpeg_get_int_status(void __iomem *base)
+{
+	unsigned int	int_status;
+
+	int_status = readl(base + S5P_JPEG_INT_STATUS_REG);
+
+	return int_status;
+}
+
+void jpeg_set_huf_table_enable(void __iomem *base, int value)
+{
+	unsigned int	reg;
+
+	reg = readl(base + S5P_JPEG_CNTL_REG) & ~S5P_JPEG_HUF_TBL_EN;
+
+	if (value == 1)
+		writel(reg | S5P_JPEG_HUF_TBL_EN, base + S5P_JPEG_CNTL_REG);
+	else
+		writel(reg | ~S5P_JPEG_HUF_TBL_EN, base + S5P_JPEG_CNTL_REG);
+}
+
+void jpeg_set_dec_scaling(void __iomem *base,
+		enum jpeg_scale_value x_value, enum jpeg_scale_value y_value)
+{
+	unsigned int	reg;
+
+	reg = readl(base + S5P_JPEG_CNTL_REG) &
+			~(S5P_JPEG_HOR_SCALING_MASK |
+				S5P_JPEG_VER_SCALING_MASK);
+
+	writel(reg | S5P_JPEG_HOR_SCALING(x_value) |
+			S5P_JPEG_VER_SCALING(y_value),
+				base + S5P_JPEG_CNTL_REG);
+}
+
+void jpeg_set_sys_int_enable(void __iomem *base, int value)
+{
+	unsigned int	reg;
+
+	reg = readl(base + S5P_JPEG_CNTL_REG) & ~(S5P_JPEG_SYS_INT_EN);
+
+	if (value == 1)
+		writel(S5P_JPEG_SYS_INT_EN, base + S5P_JPEG_CNTL_REG);
+	else
+		writel(~S5P_JPEG_SYS_INT_EN, base + S5P_JPEG_CNTL_REG);
+}
+
+void jpeg_set_stream_buf_address(void __iomem *base, unsigned int address)
+{
+	writel(address, base + S5P_JPEG_OUT_MEM_BASE_REG);
+}
+
+void jpeg_set_stream_size(void __iomem *base,
+		unsigned int x_value, unsigned int y_value)
+{
+	writel(0x0, base + S5P_JPEG_IMG_SIZE_REG); /* clear */
+	writel(S5P_JPEG_X_SIZE(x_value) | S5P_JPEG_Y_SIZE(y_value),
+			base + S5P_JPEG_IMG_SIZE_REG);
+}
+
+void jpeg_set_frame_buf_address(void __iomem *base,
+		enum jpeg_frame_format fmt, unsigned int address_1p,
+		unsigned int address_2p, unsigned int address_3p)
+{
+	switch (fmt) {
+	case GRAY:
+	case RGB_565:
+	case RGB_888:
+	case YCRYCB_422_1P:
+	case YCBYCR_422_1P:
+#if defined (CONFIG_JPEG_V2_2)
+	case BGR_888:
+	case CBYCRY_422_1P:
+	case CRYCBY_422_1P:
+#endif
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(0, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(0, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	case YCBCR_444_2P:
+	case YCRCB_444_2P:
+	case YCRCB_422_2P:
+	case YCBCR_422_2P:
+	case YCBCR_420_2P:
+	case YCRCB_420_2P:
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(address_2p, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(0, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	case YCBCR_444_3P:
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(address_2p, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(address_3p, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	case YCBYCR_422_3P:
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(address_2p, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(address_3p, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	case YCBCR_420_3P:
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(address_2p, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(address_3p, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	case YCRCB_420_3P:
+		writel(address_1p, base + S5P_JPEG_IMG_BA_PLANE_1_REG);
+		writel(address_3p, base + S5P_JPEG_IMG_BA_PLANE_2_REG);
+		writel(address_2p, base + S5P_JPEG_IMG_BA_PLANE_3_REG);
+		break;
+	default:
+		break;
+	}
+}
+void jpeg_set_encode_tbl_select(void __iomem *base,
+		enum jpeg_img_quality_level level)
+{
+	unsigned int	reg;
+
+	switch (level) {
+	case QUALITY_LEVEL_1:
+		reg = S5P_JPEG_Q_TBL_COMP1_0 | S5P_JPEG_Q_TBL_COMP2_1 |
+			S5P_JPEG_Q_TBL_COMP3_1 |
+			S5P_JPEG_HUFF_TBL_COMP1_AC_0_DC_0 |
+			S5P_JPEG_HUFF_TBL_COMP2_AC_1_DC_1 |
+			S5P_JPEG_HUFF_TBL_COMP3_AC_1_DC_1;
+		break;
+	case QUALITY_LEVEL_2:
+		reg = S5P_JPEG_Q_TBL_COMP1_0 | S5P_JPEG_Q_TBL_COMP2_3 |
+			S5P_JPEG_Q_TBL_COMP3_3 |
+			S5P_JPEG_HUFF_TBL_COMP1_AC_0_DC_0 |
+			S5P_JPEG_HUFF_TBL_COMP2_AC_1_DC_1 |
+			S5P_JPEG_HUFF_TBL_COMP3_AC_1_DC_1;
+		break;
+	case QUALITY_LEVEL_3:
+		reg = S5P_JPEG_Q_TBL_COMP1_2 | S5P_JPEG_Q_TBL_COMP2_1 |
+			S5P_JPEG_Q_TBL_COMP3_1 |
+			S5P_JPEG_HUFF_TBL_COMP1_AC_0_DC_0 |
+			S5P_JPEG_HUFF_TBL_COMP2_AC_1_DC_1 |
+			S5P_JPEG_HUFF_TBL_COMP3_AC_1_DC_1;
+		break;
+	case QUALITY_LEVEL_4:
+		reg = S5P_JPEG_Q_TBL_COMP1_2 | S5P_JPEG_Q_TBL_COMP2_3 |
+			S5P_JPEG_Q_TBL_COMP3_3 |
+			S5P_JPEG_HUFF_TBL_COMP1_AC_0_DC_0 |
+			S5P_JPEG_HUFF_TBL_COMP2_AC_1_DC_1 |
+			S5P_JPEG_HUFF_TBL_COMP3_AC_1_DC_1;
+		break;
+	default:
+		reg = S5P_JPEG_Q_TBL_COMP1_0 | S5P_JPEG_Q_TBL_COMP2_1 |
+			S5P_JPEG_Q_TBL_COMP3_1 |
+			S5P_JPEG_HUFF_TBL_COMP1_AC_0_DC_0 |
+			S5P_JPEG_HUFF_TBL_COMP2_AC_1_DC_1 |
+			S5P_JPEG_HUFF_TBL_COMP3_AC_1_DC_1;
+		break;
+	}
+	writel(reg, base + S5P_JPEG_TBL_SEL_REG);
+}
+
+void jpeg_set_encode_hoff_cnt(void __iomem *base, enum jpeg_stream_format fmt)
+{
+	if (fmt == JPEG_GRAY)
+		writel(0xd2, base + S5P_JPEG_HUFF_CNT_REG);
+	else
+		writel(0x1a2, base + S5P_JPEG_HUFF_CNT_REG);
+}
+
+unsigned int jpeg_get_stream_size(void __iomem *base)
+{
+	unsigned int size;
+
+	size = readl(base + S5P_JPEG_BITSTREAM_SIZE_REG);
+	return size;
+}
+
+void jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size)
+{
+	writel(size, base + S5P_JPEG_BITSTREAM_SIZE_REG);
+}
+
+void jpeg_set_timer_count(void __iomem *base, unsigned int size)
+{
+	writel(size, base + S5P_JPEG_INT_TIMER_COUNT_REG);
+}
+
+void jpeg_get_frame_size(void __iomem *base,
+			unsigned int *width, unsigned int *height)
+{
+	*width = (readl(base + S5P_JPEG_DECODE_XY_SIZE_REG) &
+				S5P_JPEG_DECODED_SIZE_MASK);
+	*height = (readl(base + S5P_JPEG_DECODE_XY_SIZE_REG) >> 16) &
+				S5P_JPEG_DECODED_SIZE_MASK ;
+}
+
+enum jpeg_stream_format jpeg_get_frame_fmt(void __iomem *base)
+{
+	unsigned int	reg;
+	enum jpeg_stream_format out_format;
+
+	reg = readl(base + S5P_JPEG_DECODE_IMG_FMT_REG);
+
+	out_format =
+		((reg & 0x03) == 0x01) ? JPEG_444 :
+		((reg & 0x03) == 0x02) ? JPEG_422 :
+		((reg & 0x03) == 0x03) ? JPEG_420 :
+		((reg & 0x03) == 0x00) ? JPEG_GRAY : JPEG_RESERVED;
+
+	return out_format;
+}
diff --git a/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.h b/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.h
new file mode 100644
index 0000000..535a3f9
--- /dev/null
+++ b/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.h
@@ -0,0 +1,51 @@
+/* linux/drivers/media/video/samsung/jpeg_v2x/jpeg_regs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file of the register interface for jpeg v2.x driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __JPEG_REGS_H__
+#define __JPEG_REGS_H__
+
+#include "jpeg_core.h"
+
+void jpeg_sw_reset(void __iomem *base);
+void jpeg_set_enc_dec_mode(void __iomem *base, enum jpeg_mode mode);
+void jpeg_set_dec_out_fmt(void __iomem *base,
+					enum jpeg_frame_format out_fmt);
+void jpeg_set_enc_in_fmt(void __iomem *base,
+					enum jpeg_frame_format in_fmt);
+void jpeg_set_enc_out_fmt(void __iomem *base,
+					enum jpeg_stream_format out_fmt);
+void jpeg_set_enc_tbl(void __iomem *base);
+void jpeg_set_interrupt(void __iomem *base);
+void jpeg_clean_interrupt(void __iomem *base);
+unsigned int jpeg_get_int_status(void __iomem *base);
+void jpeg_set_huf_table_enable(void __iomem *base, int value);
+void jpeg_set_dec_scaling(void __iomem *base,
+		enum jpeg_scale_value x_value, enum jpeg_scale_value y_value);
+void jpeg_set_sys_int_enable(void __iomem *base, int value);
+void jpeg_set_stream_buf_address(void __iomem *base, unsigned int address);
+void jpeg_set_stream_size(void __iomem *base,
+		unsigned int x_value, unsigned int y_value);
+void jpeg_set_frame_buf_address(void __iomem *base,
+		enum jpeg_frame_format fmt, unsigned int address,
+		unsigned int address_2p, unsigned int address_3p);
+void jpeg_set_encode_tbl_select(void __iomem *base,
+		enum jpeg_img_quality_level level);
+void jpeg_set_encode_hoff_cnt(void __iomem *base, enum jpeg_stream_format fmt);
+void jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size);
+void jpeg_set_timer_count(void __iomem *base, unsigned int size);
+unsigned int jpeg_get_stream_size(void __iomem *base);
+void jpeg_get_frame_size(void __iomem *base,
+			unsigned int *width, unsigned int *height);
+
+enum jpeg_stream_format jpeg_get_frame_fmt(void __iomem *base);
+
+#endif /* __JPEG_REGS_H__ */
diff --git a/drivers/media/video/samsung/mali/Kconfig b/drivers/media/video/samsung/mali/Kconfig
new file mode 100644
index 0000000..b93bccf
--- /dev/null
+++ b/drivers/media/video/samsung/mali/Kconfig
@@ -0,0 +1,63 @@
+#
+## S3C Multimedia Mali configuration
+##
+#
+# For Mali
+config VIDEO_MALI400MP
+	bool "Enable MALI integration"
+	depends on VIDEO_SAMSUNG
+	default n
+	---help---
+                This enables MALI integration in the multimedia device driver
+
+choice
+depends on VIDEO_MALI400MP
+prompt "MALI MEMORY OPTION"
+default MALI_OSMEM_ONLY
+config MALI_DED_ONLY
+  bool "mali dedicated memory only"
+   ---help---
+       This enables MALI dedicated memory only option
+config MALI_DED_MMU
+  bool "mali dedicated memory with mmu enable"
+   ---help---
+       This enables MALI dedicated memory with mmu enable option
+config MALI_OSMEM_ONLY
+   bool "mali OS memory only"
+   ---help---
+       This enables MALI OS memory only option
+config MALI_DED_OSMEM
+   bool "mali dedicated memory and OS memory"
+   ---help---
+       This enables MALI dedicated memory and OS memory option
+
+endchoice
+config MALI_MEM_SIZE
+int "Dedicated Memory Size"
+   depends on VIDEO_MALI400MP && (MALI_DED_ONLY || MALI_DED_MMU || MALI_DED_OSMEM)
+   default "128"
+   ---help---
+       This value is dedicated memory size of Mali GPU(unit is MByte).
+
+
+# For DEBUG
+config VIDEO_MALI400MP_DEBUG
+	bool "Enables debug messages"
+	depends on VIDEO_MALI400MP
+	default n
+	help
+	  This enables Mali driver debug messages.
+
+config VIDEO_MALI400MP_STREAMLINE_PROFILING
+	bool "Enables mali streamline profiling"
+	depends on VIDEO_MALI400MP
+	default n
+	help
+	  This enables Mali streamline profiling.
+
+config VIDEO_MALI400MP_DVFS
+	bool "Enables DVFS"
+	depends on VIDEO_MALI400MP && PM 
+	default y
+	help
+	  This enables Mali driver DVFS.
diff --git a/drivers/media/video/samsung/mali/Makefile b/drivers/media/video/samsung/mali/Makefile
new file mode 100644
index 0000000..0ce60a3
--- /dev/null
+++ b/drivers/media/video/samsung/mali/Makefile
@@ -0,0 +1,282 @@
+#
+# Copyright (C) 2010 ARM Limited. All rights reserved.
+# 
+# This program is free software and is provided to you under the terms of the GNU General Public License version 2
+# as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+# 
+# A copy of the licence is included with the program, and can also be obtained from Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+
+OSKOS :=linux
+FILES_PREFIX=
+MALI_FILE_PREFIX := drivers/media/video/samsung/mali
+KBUILDROOT =
+
+ifeq ($(CONFIG_MALI_DED_ONLY),y)
+USING_OS_MEMORY=0
+USING_MMU=0
+USING_DED=1
+endif
+
+ifeq ($(CONFIG_MALI_DED_MMU),y)
+USING_OS_MEMORY=0
+USING_MMU=1
+USING_DED=1
+endif
+
+ifeq ($(CONFIG_MALI_OSMEM_ONLY),y)
+USING_MMU=1
+USING_DED=0
+USING_OS_MEMORY=1
+endif
+
+ifeq ($(CONFIG_MALI_DED_OSMEM),y)
+USING_MMU=1
+USING_DED=1
+USING_OS_MEMORY=1
+endif
+
+ifeq ($(CONFIG_PM),y)
+USING_PMM=1
+endif
+
+ifeq ($(CONFIG_PM_RUNTIME),y)  
+USING_MALI_RUN_TIME_PM=1
+endif
+
+ifeq ($(CONFIG_VIDEO_MALI400MP_DVFS),y)
+USING_GPU_UTILIZATION=1
+USING_MALI_DVFS_ENABLED=1
+endif
+
+ifeq ($(CONFIG_VIDEO_MALI400MP_DEBUG),y)
+BUILD=debug
+endif
+
+ifeq ($(CONFIG_VIDEO_MALI400MP_STREAMLINE_PROFILING),y)
+USING_PROFILING=1
+USING_TRACEPOINTS=1
+endif
+
+# set up defaults if not defined by the user
+PANIC_ON_WATCHDOG_TIMEOUT ?= 1 
+USING_MALI400 ?= 1
+USING_MMU ?= 1
+USING_DED ?= 0
+USING_UMP ?= 0
+ONLY_ZBT ?= 0
+USING_ZBT ?= 0
+USING_OS_MEMORY ?= 1
+USING_PMM ?= 0
+USING_MALI_RUN_TIME_PM ?= 0
+USING_MALI_PMM_TESTSUITE ?= 0
+USING_MALI_PMU ?= 0
+USING_GPU_UTILIZATION ?= 0
+OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB ?= 6
+USING_PROFILING ?= 0
+USING_TRACEPOINTS ?= 0
+USING_MALI_MAJOR_PREDEFINE = 1
+USING_MALI_DVFS_ENABLED ?= 0
+TIMESTAMP ?= default
+BUILD ?= release 
+USING_MALI_PMM_EARLYSUSPEND ?= 0
+#USING_KERNEL_WITH_DMA_ALLOC_PHYS_PAGE ?= 0
+CONFIG_MALI_MEM_SIZE ?= 64
+
+#config validtion check
+ifeq ($(USING_OS_MEMORY),1)
+        USING_MMU = 1
+endif
+# Check if a Mali Core sub module should be enabled, true or false returned
+#submodule_enabled = $(shell gcc $(DEFINES) -E $(MALI_FILE_PREFIX)/arch/config.h | grep type | grep -c $(2))
+
+# Inside the kernel build system
+
+# This conditional makefile exports the global definition ARM_INTERNAL_BUILD. Customer releases will not include arm_internal.mak
+-include ../../../arm_internal.mak
+
+# Set up our defines, which will be passed to gcc
+DEFINES += -DUSING_ZBT=$(USING_ZBT)
+DEFINES += -DUSING_OS_MEMORY=$(USING_OS_MEMORY)
+DEFINES += -DUSING_MMU=$(USING_MMU)
+DEFINES += -DUSING_DED=$(USING_DED)
+DEFINES += -DUSING_UMP=$(USING_UMP)
+DEFINES += -DONLY_ZBT=$(ONLY_ZBT)
+DEFINES += -D_MALI_OSK_SPECIFIC_INDIRECT_MMAP
+DEFINES += -DUSING_MALI_PMU=$(USING_MALI_PMU)
+DEFINES += -DMALI_PMM_RUNTIME_JOB_CONTROL_ON=$(USING_MALI_RUN_TIME_PM)
+DEFINES += -DUSING_MALI_PMM=$(USING_PMM)
+DEFINES += -DMALI_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
+DEFINES += -DCONFIG_MALI_MEM_SIZE=$(CONFIG_MALI_MEM_SIZE)
+DEFINES += -D_MALI_OSK_SPECIFIC_INDIRECT_MMAP
+DEFINES += -DMALI_TIMELINE_PROFILING_ENABLED=$(USING_PROFILING)
+DEFINES += -DMALI_POWER_MGMT_TEST_SUITE=$(USING_MALI_PMM_TESTSUITE)
+DEFINES += -DMALI_MAJOR_PREDEFINE=$(USING_MALI_MAJOR_PREDEFINE)
+DEFINES += -DMALI_DVFS_ENABLED=$(USING_MALI_DVFS_ENABLED)
+DEFINES += -DUSING_MALI_PMM_EARLYSUSPEND=$(USING_MALI_PMM_EARLYSUSPEND)
+DEFINES += -DMALI_STATE_TRACKING=1
+DEFINES += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
+DEFINES += -DMALI_TRACEPOINTS_ENABLED=$(USING_TRACEPOINTS)
+DEFINES += -DMALI_REBOOTNOTIFIER
+
+ifeq ($(BUILD),debug)
+DEFINES += -DDEBUG
+endif
+
+# Linux has its own mmap cleanup handlers (see mali_kernel_mem_mmu.o)
+DEFINES += -DMALI_UKK_HAS_IMPLICIT_MMAP_CLEANUP
+
+# UMP
+ifeq ($(CONFIG_VIDEO_UMP),y)
+	DEFINES += -DMALI_USE_UNIFIED_MEMORY_PROVIDER=1 -DHAVE_UNLOCKED_IOCTL
+	EXTRA_CFLAGS += -I$(MALI_FILE_PREFIX)/../ump/include
+else
+	DEFINES += -DMALI_USE_UNIFIED_MEMORY_PROVIDER=0
+endif
+
+# Target build file
+obj-$(CONFIG_VIDEO_MALI400MP)		+= mali.o
+
+# Use our defines when compiling
+# MALI
+INCLUDES = \
+		-I$(MALI_FILE_PREFIX)\
+		-I$(MALI_FILE_PREFIX)/platform\
+		-I$(MALI_FILE_PREFIX)/common \
+		-I$(MALI_FILE_PREFIX)/linux 
+
+EXTRA_CFLAGS += $(INCLUDES)\
+		$(DEFINES) 
+
+
+EXTRA_CFLAGS += -I$(MALI_FILE_PREFIX)/linux/license/gpl
+EXTRA_CFLAGS += -I$(MALI_FILE_PREFIX)/common/pmm
+
+# Source files which always are included in a build
+ifeq ($(CONFIG_VIDEO_UMP),y)
+OSKFILES=\
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_irq.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_low_level_mem.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_mali.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_notification.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_time.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_timers.o
+else
+OSKFILES=\
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_atomics.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_irq.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_locks.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_low_level_mem.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_math.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_memory.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_misc.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_mali.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_notification.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_time.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_osk_timers.o
+endif #($(CONFIG_VIDEO_UMP),y)
+
+ifeq ($(CONFIG_CPU_EXYNOS4210),y)
+	MALI_PLATFORM_FILE = platform/orion-m400/mali_platform.o
+else
+	MALI_PLATFORM_FILE = platform/pegasus-m400/mali_platform.o
+endif #($(CONFIG_CPU_EXYNOS4210),y)
+
+UKKFILES=\
+        $(FILES_PREFIX)$(OSKOS)/mali_ukk_mem.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_ukk_gp.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_ukk_pp.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_ukk_core.o \
+        $(FILES_PREFIX)$(OSKOS)/mali_ukk_vsync.o
+
+mali-y := \
+	$(KBUILDROOT)common/mali_kernel_core.o \
+	$(KBUILDROOT)linux/mali_kernel_linux.o \
+	$(KBUILDROOT)linux/mali_osk_indir_mmap.o \
+	$(KBUILDROOT)common/mali_kernel_rendercore.o \
+	$(KBUILDROOT)common/mali_kernel_descriptor_mapping.o \
+	$(KBUILDROOT)common/mali_kernel_vsync.o \
+    $(KBUILDROOT)linux/mali_kernel_sysfs.o \
+	$(KBUILDROOT)$(MALI_PLATFORM_FILE) \
+	$(KBUILDROOT)$(OSKFILES) \
+	$(KBUILDROOT)$(UKKFILES) 
+	#__malidrv_build_info.o
+
+ifeq ($(USING_PROFILING),1)
+EXTRA_CFLAGS += -I$(MALI_FILE_PREFIX)/timestamp-default
+EXTRA_CFLAGS += -I$(MALI_FILE_PREFIX)/profiling/include
+mali-y += \
+	common/mali_kernel_profiling.o \
+	timestamp-$(TIMESTAMP)/mali_timestamp.o \
+	linux/mali_ukk_profiling.o
+
+EXTRA_CFLAGS += -I$(KBUILD_EXTMOD)/timestamp-$(TIMESTAMP)
+endif
+
+ifeq ($(USING_TRACEPOINTS),1)
+mali-y += \
+	linux/mali_osk_profiling.o
+endif
+
+# Selecting files to compile by parsing the config file
+
+ifeq ($(USING_PMM),1)
+mali-y += \
+	common/pmm/mali_pmm.o \
+	common/pmm/mali_pmm_policy.o \
+	common/pmm/mali_pmm_policy_alwayson.o \
+	common/pmm/mali_pmm_policy_jobcontrol.o \
+	common/pmm/mali_pmm_state.o \
+	linux/mali_kernel_pm.o \
+	linux/mali_osk_pm.o \
+	linux/mali_device_pause_resume.o
+endif
+ifeq ($(USING_MALI_PMU),1)
+mali-y += \
+	common/pmm/mali_pmm_pmu.o
+endif
+
+ifeq ($(USING_GPU_UTILIZATION),1)
+mali-y += \
+	common/mali_kernel_utilization.o
+endif
+
+# Mali-400 PP in use
+EXTRA_CFLAGS += -DUSING_MALI400
+mali-y += common/mali_kernel_MALI200.o
+
+# Mali-400 GP in use
+mali-y += common/mali_kernel_GP2.o
+
+# Mali MMU in use
+mali-y += \
+	common/mali_kernel_mem_mmu.o \
+	common/mali_kernel_memory_engine.o \
+	common/mali_block_allocator.o \
+	common/mali_kernel_mem_os.o
+
+# Mali Level2 cache in use
+EXTRA_CFLAGS += -DUSING_MALI400_L2_CACHE
+mali-y += common/mali_kernel_l2_cache.o
+
+ifeq ($(USING_MALI_DVFS_ENABLED),1)
+ifeq ($(CONFIG_CPU_EXYNOS4210),y)
+mali-y += \
+	platform/orion-m400/mali_platform_dvfs.o
+else
+mali-y += \
+	platform/pegasus-m400/mali_platform_dvfs.o
+endif #($(CONFIG_CPU_EXYNOS4210),y)
+endif #($(USING_MALI_DVFS_ENABLED),1)
+
+ifeq ($(PANIC_ON_WATCHDOG_TIMEOUT),1)
+	EXTRA_CFLAGS += -DUSING_KERNEL_PANIC
+endif
+
+# Get subversion revision number, fall back to 0000 if no svn info is available
+SVN_REV:=$(shell ((svnversion | grep -qv exported && echo -n 'Revision: ' && svnversion) || git svn info | sed -e 's/$$$$/M/' | grep '^Revision: ' || echo ${MALI_RELEASE_NAME}) 2>/dev/null | sed -e 's/^Revision: //')
+
+EXTRA_CFLAGS += -DSVN_REV=$(SVN_REV)
+EXTRA_CFLAGS += -DSVN_REV_STRING=\"$(SVN_REV)\"
+
diff --git a/drivers/media/video/samsung/mali/Makefile.common b/drivers/media/video/samsung/mali/Makefile.common
new file mode 100644
index 0000000..53d4e5b
--- /dev/null
+++ b/drivers/media/video/samsung/mali/Makefile.common
@@ -0,0 +1,59 @@
+#
+# Copyright (C) 2010 ARM Limited. All rights reserved.
+# 
+# This program is free software and is provided to you under the terms of the GNU General Public License version 2
+# as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+# 
+# A copy of the licence is included with the program, and can also be obtained from Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+
+# Check if a Mali Core sub module should be enabled, true or false returned
+submodule_enabled = $(shell gcc $(DEFINES) -E $1/arch/config.h | grep type | grep -c $(2))
+
+OSKFILES=\
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_atomics.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_irq.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_locks.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_low_level_mem.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_math.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_memory.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_misc.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_mali.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_notification.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_time.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_osk_timers.c
+
+UKKFILES=\
+	$(FILES_PREFIX)$(OSKOS)/mali_ukk_mem.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_ukk_gp.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_ukk_pp.c \
+	$(FILES_PREFIX)$(OSKOS)/mali_ukk_core.c
+	
+ifeq ($(USING_PROFILING),1)
+UKKFILES+=\
+	$(FILES_PREFIX)$(OSKOS)/mali_ukk_profiling.c
+endif
+
+ifeq ($(MALI_PLATFORM_FILE),)
+MALI_PLATFORM_FILE=platform/default/mali_platform.c
+endif
+
+# Get subversion revision number, fall back to only ${MALI_RELEASE_NAME} if no svn info is available
+SVN_REV := $(shell (cd $(DRIVER_DIR); (svnversion | grep -qv exported && svnversion) || git svn info | grep '^Revision: '| sed -e 's/^Revision: //' ) 2>/dev/null )
+ifeq ($(SVN_REV),)
+SVN_REV := $(MALI_RELEASE_NAME)
+else
+SVN_REV := $(MALI_RELEASE_NAME)-r$(SVN_REV)
+endif
+
+# Common version-string, will be extended by OS-specifc sections
+VERSION_STRINGS :=
+VERSION_STRINGS += CONFIG=$(CONFIG)
+VERSION_STRINGS += USING_OS_MEMORY=$(USING_OS_MEMORY)
+VERSION_STRINGS += API_VERSION=$(shell cd $(DRIVER_DIR); grep "\#define _MALI_API_VERSION" $(FILES_PREFIX)common\/mali_uk_types.h | cut -d' ' -f 3 )
+VERSION_STRINGS += REPO_URL=$(shell cd $(DRIVER_DIR); (svn info || git svn info || echo 'URL: $(MALI_RELEASE_NAME)') 2>/dev/null | grep '^URL: ' | cut -d: -f2- | cut -b2-)
+VERSION_STRINGS += REVISION=$(SVN_REV)
+VERSION_STRINGS += CHANGED_REVISION=$(shell cd $(DRIVER_DIR); (svn info || git svn info || echo 'Last Changed Rev: $(MALI_RELEASE_NAME)') 2>/dev/null | grep '^Last Changed Rev: ' | cut -d: -f2- | cut -b2-)
+VERSION_STRINGS += CHANGE_DATE=$(shell cd $(DRIVER_DIR); (svn info || git svn info || echo 'Last Changed Date: $(MALI_RELEASE_NAME)') 2>/dev/null | grep '^Last Changed Date: ' | cut -d: -f2- | cut -b2-)
+VERSION_STRINGS += BUILD_DATE=$(shell date)
diff --git a/drivers/media/video/samsung/mali/arch b/drivers/media/video/samsung/mali/arch
new file mode 120000
index 0000000..6154ca4
--- /dev/null
+++ b/drivers/media/video/samsung/mali/arch
@@ -0,0 +1 @@
+arch-orion-m400
\ No newline at end of file
diff --git a/drivers/media/video/samsung/mali/arch-orion-m400/config.h b/drivers/media/video/samsung/mali/arch-orion-m400/config.h
new file mode 100644
index 0000000..5c4d79d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/arch-orion-m400/config.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARCH_CONFIG_H__
+#define __ARCH_CONFIG_H__
+
+/* Configuration for the EB platform with ZBT memory enabled */
+/*zepplin added 2010.08.17 for orion configuration*/
+#define MALI_BASE_ADDR 		   0x13000000
+#define GP_ADDR 	MALI_BASE_ADDR
+#define L2_ADDR 	MALI_BASE_ADDR+0x1000
+#define PMU_ADDR 	MALI_BASE_ADDR+0x2000
+#define GP_MMU_ADDR 	MALI_BASE_ADDR+0x3000
+#define PP0_MMU_ADDR 	MALI_BASE_ADDR+0x4000
+#define PP1_MMU_ADDR 	MALI_BASE_ADDR+0x5000
+#define PP2_MMU_ADDR 	MALI_BASE_ADDR+0x6000
+#define PP3_MMU_ADDR 	MALI_BASE_ADDR+0x7000
+#define PP0_ADDR 	MALI_BASE_ADDR+0x8000
+#define PP1_ADDR 	MALI_BASE_ADDR+0xA000
+#define PP2_ADDR 	MALI_BASE_ADDR+0xC000
+#define PP3_ADDR 	MALI_BASE_ADDR+0xE000
+
+/*for mmu and os memory*/
+#define MEM_BASE_ADDR    0x40000000
+#define MEM_TOTAL_SIZE   0x40000000
+#define MEM_MALI_OS_SIZE 0x40000000
+
+/*for dedicated memory*/
+//#define MEM_MALI_BASE    0x58000000
+//#define MEM_MALI_SIZE 	 0x08000000
+#define MEM_MALI_SIZE 	 CONFIG_MALI_MEM_SIZE*1024*1024
+#define MEM_MALI_BASE    0x80000000 - MEM_MALI_SIZE 
+
+static _mali_osk_resource_t arch_configuration [] =
+{
+	{
+		.type = MALI400GP,
+		.description = "Mali-400 GP",
+		.base = GP_ADDR,
+		.irq = IRQ_GP_3D,
+		.mmu_id = 1
+	},
+	{
+		.type = MALI400PP,
+		.base = PP0_ADDR,
+		.irq = IRQ_PP0_3D,
+		.description = "Mali-400 PP 0",
+		.mmu_id = 2
+	},
+	{
+		.type = MALI400PP,
+		.base = PP1_ADDR,
+		.irq = IRQ_PP1_3D,
+		.description = "Mali-400 PP 1",
+		.mmu_id = 3
+	},
+	{
+		.type = MALI400PP,
+		.base = PP2_ADDR,
+		.irq = IRQ_PP2_3D,
+		.description = "Mali-400 PP 2",
+		.mmu_id = 4
+	},
+	{
+		.type = MALI400PP,
+		.base = PP3_ADDR,
+		.irq = IRQ_PP3_3D,
+		.description = "Mali-400 PP 3",
+		.mmu_id = 5
+	},
+#if USING_MMU
+	{
+		.type = MMU,
+		.base = GP_MMU_ADDR,
+		.irq = IRQ_GPMMU_3D,
+		.description = "Mali-400 MMU for GP",
+		.mmu_id = 1
+	},
+	{
+		.type = MMU,
+		.base = PP0_MMU_ADDR,
+		.irq = IRQ_PPMMU0_3D,
+		.description = "Mali-400 MMU for PP 0",
+		.mmu_id = 2
+	},
+	{
+		.type = MMU,
+		.base = PP1_MMU_ADDR,
+		.irq = IRQ_PPMMU1_3D,
+		.description = "Mali-400 MMU for PP 1",
+		.mmu_id = 3
+	},
+	{
+		.type = MMU,
+		.base = PP2_MMU_ADDR,
+		.irq = IRQ_PPMMU2_3D,
+		.description = "Mali-400 MMU for PP 2",
+		.mmu_id = 4
+	},
+	{
+		.type = MMU,
+		.base = PP3_MMU_ADDR,
+		.irq = IRQ_PPMMU3_3D,
+		.description = "Mali-400 MMU for PP 3",
+		.mmu_id = 5
+	},
+#if USING_OS_MEMORY 
+	{
+		.type = OS_MEMORY,
+		.description = "System Memory",
+		.size = MEM_MALI_OS_SIZE,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE
+	},
+#endif
+#if USING_DED /* Dedicated Memory */
+	{
+		.type = MEMORY,
+		.description = "Dedicated Memory",
+		.base = MEM_MALI_BASE,
+		.size = MEM_MALI_SIZE,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE
+	},
+#endif/* if USING_OS_MEMORY*/
+	{
+		.type = MEM_VALIDATION,
+		.description = "memory validation",
+		.base = MEM_BASE_ADDR,
+		.size = MEM_TOTAL_SIZE,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE
+	},
+#else /* Not using MMU */
+	{
+		.type = MEMORY,
+		.description = "Dedicated Memory",
+		.base = MEM_MALI_BASE,
+		.size = MEM_MALI_SIZE,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE
+	},
+#endif
+	{
+		.type = MALI400L2,
+		.base = L2_ADDR,
+		.description = "Mali-400 L2 cache"
+	},
+};
+
+#endif /* __ARCH_CONFIG_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_block_allocator.c b/drivers/media/video/samsung/mali/common/mali_block_allocator.c
new file mode 100644
index 0000000..5f421f0
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_block_allocator.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include "mali_kernel_common.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_memory_engine.h"
+#include "mali_block_allocator.h"
+#include "mali_osk.h"
+
+#define MALI_BLOCK_SIZE (256UL * 1024UL)  /* 256 kB, remember to keep the ()s */
+
+typedef struct block_info
+{
+	struct block_info * next;
+} block_info;
+
+/* The structure used as the handle produced by block_allocator_allocate,
+ * and removed by block_allocator_release */
+typedef struct block_allocator_allocation
+{
+	/* The list will be released in reverse order */
+	block_info *last_allocated;
+	mali_allocation_engine * engine;
+	mali_memory_allocation * descriptor;
+	u32 start_offset;
+	u32 mapping_length;
+} block_allocator_allocation;
+
+
+typedef struct block_allocator
+{
+    _mali_osk_lock_t *mutex;
+	block_info * all_blocks;
+	block_info * first_free;
+	u32 base;
+	u32 cpu_usage_adjust;
+	u32 num_blocks;
+} block_allocator;
+
+MALI_STATIC_INLINE u32 get_phys(block_allocator * info, block_info * block);
+static mali_physical_memory_allocation_result block_allocator_allocate(void* ctx, mali_allocation_engine * engine,  mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info);
+static void block_allocator_release(void * ctx, void * handle);
+static mali_physical_memory_allocation_result block_allocator_allocate_page_table_block(void * ctx, mali_page_table_block * block);
+static void block_allocator_release_page_table_block( mali_page_table_block *page_table_block );
+static void block_allocator_destroy(mali_physical_memory_allocator * allocator);
+static u32 block_allocator_stat(mali_physical_memory_allocator * allocator);
+
+mali_physical_memory_allocator * mali_block_allocator_create(u32 base_address, u32 cpu_usage_adjust, u32 size, const char *name)
+{
+	mali_physical_memory_allocator * allocator;
+	block_allocator * info;
+	u32 usable_size;
+	u32 num_blocks;
+
+	usable_size = size & ~(MALI_BLOCK_SIZE - 1);
+	MALI_DEBUG_PRINT(3, ("Mali block allocator create for region starting at 0x%08X length 0x%08X\n", base_address, size));
+	MALI_DEBUG_PRINT(4, ("%d usable bytes\n", usable_size));
+	num_blocks = usable_size / MALI_BLOCK_SIZE;
+	MALI_DEBUG_PRINT(4, ("which becomes %d blocks\n", num_blocks));
+
+	if (usable_size == 0)
+	{
+		MALI_DEBUG_PRINT(1, ("Memory block of size %d is unusable\n", size));
+		return NULL;
+	}
+
+	allocator = _mali_osk_malloc(sizeof(mali_physical_memory_allocator));
+	if (NULL != allocator)
+	{
+		info = _mali_osk_malloc(sizeof(block_allocator));
+		if (NULL != info)
+		{
+            info->mutex = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_ORDERED, 0, 105);
+            if (NULL != info->mutex)
+            {
+        		info->all_blocks = _mali_osk_malloc(sizeof(block_info) * num_blocks);
+			    if (NULL != info->all_blocks)
+			    {
+				    u32 i;
+				    info->first_free = NULL;
+				    info->num_blocks = num_blocks;
+
+				    info->base = base_address;
+				    info->cpu_usage_adjust = cpu_usage_adjust;
+
+				    for ( i = 0; i < num_blocks; i++)
+				    {
+					    info->all_blocks[i].next = info->first_free;
+					    info->first_free = &info->all_blocks[i];
+				    }
+
+				    allocator->allocate = block_allocator_allocate;
+				    allocator->allocate_page_table_block = block_allocator_allocate_page_table_block;
+				    allocator->destroy = block_allocator_destroy;
+				    allocator->stat = block_allocator_stat;
+				    allocator->ctx = info;
+					allocator->name = name;
+
+				    return allocator;
+			    }
+                _mali_osk_lock_term(info->mutex);
+            }
+			_mali_osk_free(info);
+		}
+		_mali_osk_free(allocator);
+	}
+
+	return NULL;
+}
+
+static void block_allocator_destroy(mali_physical_memory_allocator * allocator)
+{
+	block_allocator * info;
+	MALI_DEBUG_ASSERT_POINTER(allocator);
+	MALI_DEBUG_ASSERT_POINTER(allocator->ctx);
+	info = (block_allocator*)allocator->ctx;
+
+	_mali_osk_free(info->all_blocks);
+    _mali_osk_lock_term(info->mutex);
+	_mali_osk_free(info);
+	_mali_osk_free(allocator);
+}
+
+MALI_STATIC_INLINE u32 get_phys(block_allocator * info, block_info * block)
+{
+	return info->base + ((block - info->all_blocks) * MALI_BLOCK_SIZE);
+}
+
+static mali_physical_memory_allocation_result block_allocator_allocate(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info)
+{
+	block_allocator * info;
+	u32 left;
+	block_info * last_allocated = NULL;
+	mali_physical_memory_allocation_result result = MALI_MEM_ALLOC_NONE;
+	block_allocator_allocation *ret_allocation;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+	MALI_DEBUG_ASSERT_POINTER(offset);
+	MALI_DEBUG_ASSERT_POINTER(alloc_info);
+
+	info = (block_allocator*)ctx;
+	left = descriptor->size - *offset;
+	MALI_DEBUG_ASSERT(0 != left);
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW)) return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	ret_allocation = _mali_osk_malloc( sizeof(block_allocator_allocation) );
+
+	if ( NULL == ret_allocation )
+	{
+		/* Failure; try another allocator by returning MALI_MEM_ALLOC_NONE */
+		_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+		return result;
+	}
+
+	ret_allocation->start_offset = *offset;
+	ret_allocation->mapping_length = 0;
+
+	while ((left > 0) && (info->first_free))
+	{
+		block_info * block;
+		u32 phys_addr;
+		u32 padding;
+		u32 current_mapping_size;
+
+		block = info->first_free;
+		info->first_free = info->first_free->next;
+		block->next = last_allocated;
+		last_allocated = block;
+
+		phys_addr = get_phys(info, block);
+
+		padding = *offset & (MALI_BLOCK_SIZE-1);
+
+ 		if (MALI_BLOCK_SIZE - padding < left)
+		{
+			current_mapping_size = MALI_BLOCK_SIZE - padding;
+		}
+		else
+		{
+			current_mapping_size = left;
+		}
+
+		if (_MALI_OSK_ERR_OK != mali_allocation_engine_map_physical(engine, descriptor, *offset, phys_addr + padding, info->cpu_usage_adjust, current_mapping_size))
+		{
+			MALI_DEBUG_PRINT(1, ("Mapping of physical memory  failed\n"));
+			result = MALI_MEM_ALLOC_INTERNAL_FAILURE;
+			mali_allocation_engine_unmap_physical(engine, descriptor, ret_allocation->start_offset, ret_allocation->mapping_length, (_mali_osk_mem_mapregion_flags_t)0);
+
+			/* release all memory back to the pool */
+			while (last_allocated)
+			{
+				/* This relinks every block we've just allocated back into the free-list */
+				block = last_allocated->next;
+				last_allocated->next = info->first_free;
+				info->first_free = last_allocated;
+				last_allocated = block;
+			}
+
+			break;
+		}
+
+		*offset += current_mapping_size;
+		left -= current_mapping_size;
+		ret_allocation->mapping_length += current_mapping_size;
+	}
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	if (last_allocated)
+	{
+		if (left) result = MALI_MEM_ALLOC_PARTIAL;
+		else result = MALI_MEM_ALLOC_FINISHED;
+
+		/* Record all the information about this allocation */
+		ret_allocation->last_allocated = last_allocated;
+		ret_allocation->engine = engine;
+		ret_allocation->descriptor = descriptor;
+
+		alloc_info->ctx = info;
+		alloc_info->handle = ret_allocation;
+		alloc_info->release = block_allocator_release;
+	}
+	else
+	{
+		/* Free the allocation information - nothing to be passed back */
+		_mali_osk_free( ret_allocation );
+	}
+
+	return result;
+}
+
+static void block_allocator_release(void * ctx, void * handle)
+{
+	block_allocator * info;
+	block_info * block, * next;
+	block_allocator_allocation *allocation;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	MALI_DEBUG_ASSERT_POINTER(handle);
+
+	info = (block_allocator*)ctx;
+	allocation = (block_allocator_allocation*)handle;
+	block = allocation->last_allocated;
+
+	MALI_DEBUG_ASSERT_POINTER(block);
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW))
+	{
+		MALI_DEBUG_PRINT(1, ("allocator release: Failed to get mutex\n"));
+		return;
+	}
+
+	/* unmap */
+	mali_allocation_engine_unmap_physical(allocation->engine, allocation->descriptor, allocation->start_offset, allocation->mapping_length, (_mali_osk_mem_mapregion_flags_t)0);
+
+	while (block)
+	{
+		MALI_DEBUG_ASSERT(!((block < info->all_blocks) || (block > (info->all_blocks + info->num_blocks))));
+
+		next = block->next;
+
+		/* relink into free-list */
+		block->next = info->first_free;
+		info->first_free = block;
+
+		/* advance the loop */
+		block = next;
+	}
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	_mali_osk_free( allocation );
+}
+
+
+static mali_physical_memory_allocation_result block_allocator_allocate_page_table_block(void * ctx, mali_page_table_block * block)
+{
+	block_allocator * info;
+	mali_physical_memory_allocation_result result = MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	MALI_DEBUG_ASSERT_POINTER(block);
+	info = (block_allocator*)ctx;
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW)) return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	if (NULL != info->first_free)
+	{
+		void * virt;
+		u32 phys;
+		u32 size;
+		block_info * alloc;
+		alloc = info->first_free;
+
+		phys = get_phys(info, alloc); /* Does not modify info or alloc */
+		size = MALI_BLOCK_SIZE; /* Must be multiple of MALI_MMU_PAGE_SIZE */
+		virt = _mali_osk_mem_mapioregion( phys, size, "Mali block allocator page tables" );
+
+		/* Failure of _mali_osk_mem_mapioregion will result in MALI_MEM_ALLOC_INTERNAL_FAILURE,
+		 * because it's unlikely another allocator will be able to map in. */
+
+		if ( NULL != virt )
+		{
+			block->ctx = info; /* same as incoming ctx */
+			block->handle = alloc;
+			block->phys_base = phys;
+			block->size = size;
+			block->release = block_allocator_release_page_table_block;
+			block->mapping = virt;
+
+			info->first_free = alloc->next;
+
+			alloc->next = NULL; /* Could potentially link many blocks together instead */
+
+			result = MALI_MEM_ALLOC_FINISHED;
+		}
+	}
+	else result = MALI_MEM_ALLOC_NONE;
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	return result;
+}
+
+
+static void block_allocator_release_page_table_block( mali_page_table_block *page_table_block )
+{
+	block_allocator * info;
+	block_info * block, * next;
+
+	MALI_DEBUG_ASSERT_POINTER( page_table_block );
+
+	info = (block_allocator*)page_table_block->ctx;
+	block = (block_info*)page_table_block->handle;
+
+	MALI_DEBUG_ASSERT_POINTER(info);
+	MALI_DEBUG_ASSERT_POINTER(block);
+
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW))
+	{
+		MALI_DEBUG_PRINT(1, ("allocator release: Failed to get mutex\n"));
+		return;
+	}
+
+	/* Unmap all the physical memory at once */
+	_mali_osk_mem_unmapioregion( page_table_block->phys_base, page_table_block->size, page_table_block->mapping );
+
+	/** @note This loop handles the case where more than one block_info was linked.
+	 * Probably unnecssary for page table block releasing. */
+	while (block)
+	{
+		next = block->next;
+
+		MALI_DEBUG_ASSERT(!((block < info->all_blocks) || (block > (info->all_blocks + info->num_blocks))));
+
+		block->next = info->first_free;
+		info->first_free = block;
+
+		block = next;
+	}
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+}
+
+static u32 block_allocator_stat(mali_physical_memory_allocator * allocator)
+{
+	block_allocator * info;
+	block_info *block;
+	u32 free_blocks = 0;
+
+	MALI_DEBUG_ASSERT_POINTER(allocator);
+
+	info = (block_allocator*)allocator->ctx;
+	block = info->first_free;
+
+	while(block)
+	{
+		free_blocks++;
+		block = block->next;
+	}
+	return (info->num_blocks - free_blocks) * MALI_BLOCK_SIZE;
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_block_allocator.h b/drivers/media/video/samsung/mali/common/mali_block_allocator.h
new file mode 100644
index 0000000..d3f0f9b
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_block_allocator.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_BLOCK_ALLOCATOR_H__
+#define __MALI_BLOCK_ALLOCATOR_H__
+
+#include "mali_kernel_memory_engine.h"
+
+mali_physical_memory_allocator * mali_block_allocator_create(u32 base_address, u32 cpu_usage_adjust, u32 size, const char *name);
+
+#endif /* __MALI_BLOCK_ALLOCATOR_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_GP2.c b/drivers/media/video/samsung/mali/common/mali_kernel_GP2.c
new file mode 100644
index 0000000..cfd70f4
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_GP2.c
@@ -0,0 +1,1493 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+//added for SPI
+#include <linux/kernel.h>
+
+#include "mali_kernel_common.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_subsystem.h"
+#include "regs/mali_gp_regs.h"
+#include "mali_kernel_rendercore.h"
+#include "mali_osk.h"
+#include "mali_osk_list.h"
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+#if defined(USING_MALI400_L2_CACHE)
+#include "mali_kernel_l2_cache.h"
+#endif
+#if USING_MMU
+#include "mali_kernel_mem_mmu.h" /* Needed for mali_kernel_mmu_force_bus_reset() */
+#endif
+
+#if defined(USING_MALI200)
+#define MALI_GP_SUBSYSTEM_NAME "MaliGP2"
+#define MALI_GP_CORE_TYPE      _MALI_GP2
+#elif defined(USING_MALI400)
+#define MALI_GP_SUBSYSTEM_NAME "Mali-400 GP"
+#define MALI_GP_CORE_TYPE      _MALI_400_GP
+#else
+#error "No supported mali core defined"
+#endif
+
+#define GET_JOB_EMBEDDED_PTR(job) (&((job)->embedded_core_job))
+#define GET_JOBGP2_PTR(job_extern) _MALI_OSK_CONTAINER_OF(job_extern, maligp_job, embedded_core_job)
+
+/* Initialized when this subsystem is initialized. This is determined by the
+ * position in subsystems[], and so the value used to initialize this is
+ * determined at compile time */
+static mali_kernel_subsystem_identifier mali_subsystem_gp_id = -1;
+
+static mali_core_renderunit * last_gp_core_cookie = NULL;
+
+/* Describing a maligp job settings */
+typedef struct maligp_job
+{
+	/* The general job struct common for all mali cores */
+	mali_core_job embedded_core_job;
+	_mali_uk_gp_start_job_s user_input;
+
+	u32 irq_status;
+	u32 status_reg_on_stop;
+	u32 perf_counter0;
+	u32 perf_counter1;
+	u32 vscl_stop_addr;
+	u32 plbcl_stop_addr;
+	u32 heap_current_addr;
+
+	/* The data we will return back to the user */
+	_mali_osk_notification_t *notification_obj;
+
+	int is_stalled_waiting_for_more_memory;
+
+	u32 active_mask;
+	/* progress checking */
+	u32 last_vscl;
+	u32 last_plbcl;
+	/* extended progress checking, only enabled when we can use one of the performance counters */
+	u32 have_extended_progress_checking;
+	u32 vertices;
+
+#if defined(USING_MALI400_L2_CACHE)
+	u32 perf_counter_l2_src0;
+	u32 perf_counter_l2_src1;
+	u32 perf_counter_l2_val0;
+	u32 perf_counter_l2_val1;
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	u32 pid;
+	u32 tid;
+#endif
+} maligp_job;
+
+/*Functions Exposed to the General External System through
+  function pointers.*/
+
+static _mali_osk_errcode_t maligp_subsystem_startup(mali_kernel_subsystem_identifier id);
+#if USING_MMU
+static _mali_osk_errcode_t maligp_subsystem_mmu_connect(mali_kernel_subsystem_identifier id);
+#endif
+static void maligp_subsystem_terminate(mali_kernel_subsystem_identifier id);
+static _mali_osk_errcode_t maligp_subsystem_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+static void maligp_subsystem_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot);
+static _mali_osk_errcode_t maligp_subsystem_core_system_info_fill(_mali_system_info* info);
+static _mali_osk_errcode_t maligp_renderunit_create(_mali_osk_resource_t * resource);
+#if USING_MMU
+static void maligp_subsystem_broadcast_notification(mali_core_notification_message message, u32 data);
+#endif
+#if MALI_STATE_TRACKING
+u32 maligp_subsystem_dump_state(char *buf, u32 size);
+#endif
+
+/* Internal support functions  */
+static _mali_osk_errcode_t maligp_core_version_legal( mali_core_renderunit *core );
+static void maligp_raw_reset( mali_core_renderunit *core);
+static void maligp_reset_hard(struct mali_core_renderunit * core);
+static void maligp_reset(mali_core_renderunit *core);
+static void maligp_initialize_registers_mgmt(mali_core_renderunit *core );
+
+#ifdef DEBUG
+static void maligp_print_regs(int debug_level, mali_core_renderunit *core);
+#endif
+
+/* Functions exposed to mali_core system through functionpointers
+   in the subsystem struct. */
+static _mali_osk_errcode_t subsystem_maligp_start_job(mali_core_job * job, mali_core_renderunit * core);
+static u32 subsystem_maligp_irq_handler_upper_half(mali_core_renderunit * core);
+static int subsystem_maligp_irq_handler_bottom_half(mali_core_renderunit* core);
+static _mali_osk_errcode_t subsystem_maligp_get_new_job_from_user(struct mali_core_session * session, void * argument);
+static _mali_osk_errcode_t subsystem_maligp_suspend_response(struct mali_core_session * session, void * argument);
+static void subsystem_maligp_return_job_to_user(mali_core_job * job, mali_subsystem_job_end_code end_status);
+static void subsystem_maligp_renderunit_delete(mali_core_renderunit * core);
+static void subsystem_maligp_renderunit_reset_core(struct mali_core_renderunit * core, mali_core_reset_style style );
+static void subsystem_maligp_renderunit_probe_core_irq_trigger(struct mali_core_renderunit* core);
+static _mali_osk_errcode_t subsystem_maligp_renderunit_probe_core_irq_finished(struct mali_core_renderunit* core);
+static void subsystem_maligp_renderunit_stop_bus(struct mali_core_renderunit* core);
+
+/* Variables */
+static register_address_and_value default_mgmt_regs[] =
+{
+	{ MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED }
+};
+
+
+/* This will be one of the subsystems in the array of subsystems:
+	static struct mali_kernel_subsystem * subsystems[];
+  found in file: mali_kernel_core.c
+*/
+
+struct mali_kernel_subsystem mali_subsystem_gp2=
+{
+	maligp_subsystem_startup,                   /* startup */
+	NULL, /*maligp_subsystem_terminate,*/                 /* shutdown */
+#if USING_MMU
+	maligp_subsystem_mmu_connect,               /* load_complete */
+#else
+    NULL,
+#endif
+	maligp_subsystem_core_system_info_fill,     /* system_info_fill */
+	maligp_subsystem_session_begin,             /* session_begin */
+	maligp_subsystem_session_end,               /* session_end */
+#if USING_MMU
+	maligp_subsystem_broadcast_notification,    /* broadcast_notification */
+#else
+    NULL,
+#endif
+#if MALI_STATE_TRACKING
+	maligp_subsystem_dump_state,                /* dump_state */
+#endif
+} ;
+
+static mali_core_subsystem subsystem_maligp ;
+
+static _mali_osk_errcode_t maligp_subsystem_startup(mali_kernel_subsystem_identifier id)
+{
+	mali_core_subsystem * subsystem;
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: maligp_subsystem_startup\n") ) ;
+
+    mali_subsystem_gp_id = id;
+
+    /* All values get 0 as default */
+	_mali_osk_memset(&subsystem_maligp, 0, sizeof(*subsystem));
+
+	subsystem = &subsystem_maligp;
+	subsystem->start_job = &subsystem_maligp_start_job;
+	subsystem->irq_handler_upper_half = &subsystem_maligp_irq_handler_upper_half;
+	subsystem->irq_handler_bottom_half = &subsystem_maligp_irq_handler_bottom_half;
+	subsystem->get_new_job_from_user = &subsystem_maligp_get_new_job_from_user;
+	subsystem->suspend_response = &subsystem_maligp_suspend_response;
+	subsystem->return_job_to_user = &subsystem_maligp_return_job_to_user;
+	subsystem->renderunit_delete = &subsystem_maligp_renderunit_delete;
+	subsystem->reset_core = &subsystem_maligp_renderunit_reset_core;
+	subsystem->stop_bus = &subsystem_maligp_renderunit_stop_bus;
+	subsystem->probe_core_irq_trigger = &subsystem_maligp_renderunit_probe_core_irq_trigger;
+	subsystem->probe_core_irq_acknowledge = &subsystem_maligp_renderunit_probe_core_irq_finished;
+
+	/* Setting variables in the general core part of the subsystem.*/
+	subsystem->name = MALI_GP_SUBSYSTEM_NAME;
+	subsystem->core_type = MALI_GP_CORE_TYPE;
+	subsystem->id = id;
+
+	/* Initiates the rest of the general core part of the subsystem */
+    MALI_CHECK_NO_ERROR(mali_core_subsystem_init( subsystem ));
+
+	/* This will register the function for adding MALIGP2 cores to the subsystem */
+#if defined(USING_MALI200)
+    MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MALIGP2, maligp_renderunit_create));
+#endif
+#if defined(USING_MALI400)
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MALI400GP, maligp_renderunit_create));
+#endif
+
+	MALI_DEBUG_PRINT(6, ("Mali GP: maligp_subsystem_startup\n") ) ;
+
+	MALI_SUCCESS;
+}
+
+#if USING_MMU
+static _mali_osk_errcode_t maligp_subsystem_mmu_connect(mali_kernel_subsystem_identifier id)
+{
+       mali_core_subsystem_attach_mmu(&subsystem_maligp);
+       MALI_SUCCESS; /* OK */
+}
+#endif
+
+static void maligp_subsystem_terminate(mali_kernel_subsystem_identifier id)
+{
+	MALI_DEBUG_PRINT(3, ("Mali GP: maligp_subsystem_terminate\n") ) ;
+	mali_core_subsystem_cleanup(&subsystem_maligp);
+}
+
+static _mali_osk_errcode_t maligp_subsystem_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue)
+{
+	mali_core_session * session;
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: maligp_subsystem_session_begin\n") ) ;
+    MALI_CHECK_NON_NULL(session = _mali_osk_malloc( sizeof(*session) ), _MALI_OSK_ERR_FAULT);
+
+	_mali_osk_memset(session, 0, sizeof(*session) );
+	*slot = (mali_kernel_subsystem_session_slot)session;
+
+	session->subsystem = &subsystem_maligp;
+
+	session->notification_queue = queue;
+
+#if USING_MMU
+	session->mmu_session = mali_session_data;
+#endif
+
+	mali_core_session_begin(session);
+
+	MALI_DEBUG_PRINT(6, ("Mali GP: maligp_subsystem_session_begin\n") ) ;
+
+    MALI_SUCCESS;
+}
+
+static void maligp_subsystem_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot)
+{
+	mali_core_session * session;
+	/** @note mali_session_data not needed here */
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: maligp_subsystem_session_end\n") ) ;
+	if ( NULL==slot || NULL==*slot)
+	{
+		MALI_PRINT_ERROR(("Input slot==NULL"));
+		return;
+	}
+	session = (mali_core_session *)*slot;
+	mali_core_session_close(session);
+
+	_mali_osk_free(session);
+	*slot = NULL;
+
+	MALI_DEBUG_PRINT(6, ("Mali GP: maligp_subsystem_session_end\n") ) ;
+}
+
+/**
+ * We fill in info about all the cores we have
+ * @param info Pointer to system info struct to update
+ * @return _MALI_OSK_ERR_OK on success, or another _mali_osk_errcode_t for errors.
+ */
+static _mali_osk_errcode_t maligp_subsystem_core_system_info_fill(_mali_system_info* info)
+{
+	return mali_core_subsystem_system_info_fill(&subsystem_maligp, info);
+}
+
+static _mali_osk_errcode_t maligp_renderunit_create(_mali_osk_resource_t * resource)
+{
+	mali_core_renderunit *core;
+	int err;
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: maligp_renderunit_create\n") ) ;
+	/* Checking that the resource settings are correct */
+#if defined(USING_MALI200)
+	if(MALIGP2 != resource->type)
+	{
+		MALI_PRINT_ERROR(("Can not register this resource as a " MALI_GP_SUBSYSTEM_NAME " core."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#elif defined(USING_MALI400)
+	if(MALI400GP != resource->type)
+	{
+		MALI_PRINT_ERROR(("Can not register this resource as a " MALI_GP_SUBSYSTEM_NAME " core."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#endif
+	if ( 0 != resource->size )
+	{
+		MALI_PRINT_ERROR(("Memory size set to " MALI_GP_SUBSYSTEM_NAME " core should be zero."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	if ( NULL == resource->description )
+	{
+		MALI_PRINT_ERROR(("A " MALI_GP_SUBSYSTEM_NAME " core needs a unique description field"));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Create a new core object */
+	core = (mali_core_renderunit*) _mali_osk_malloc(sizeof(*core));
+	if ( NULL == core )
+	{
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Variables set to be able to open and register the core */
+	core->subsystem             = &subsystem_maligp ;
+	core->registers_base_addr   = resource->base ;
+	core->size                  = MALIGP2_REGISTER_ADDRESS_SPACE_SIZE ;
+	core->description           = resource->description;
+	core->irq_nr                = resource->irq ;
+#if USING_MMU
+	core->mmu_id                = resource->mmu_id;
+	core->mmu                   = NULL;
+#endif
+#if USING_MALI_PMM
+	/* Set up core's PMM id */
+	core->pmm_id = MALI_PMM_CORE_GP;
+#endif
+
+	err = mali_core_renderunit_init( core );
+    if (_MALI_OSK_ERR_OK != err)
+    {
+		MALI_DEBUG_PRINT(1, ("Failed to initialize renderunit\n"));
+		goto exit_on_error0;
+    }
+
+	/* Map the new core object, setting: core->registers_mapped  */
+	err = mali_core_renderunit_map_registers(core);
+	if (_MALI_OSK_ERR_OK != err) goto exit_on_error1;
+
+	/* Check that the register mapping of the core works.
+	Return 0 if maligp core is present and accessible. */
+	if (mali_benchmark) {
+		core->core_version = MALI_GP_PRODUCT_ID << 16;
+	} else {
+		core->core_version = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VERSION);
+	}
+
+	err = maligp_core_version_legal(core);
+	if (_MALI_OSK_ERR_OK != err) goto exit_on_error2;
+
+	/* Reset the core. Put the core into a state where it can start to render. */
+	maligp_reset(core);
+
+	/* Registering IRQ, init the work_queue_irq_handle */
+	/* Adding this core as an available renderunit in the subsystem. */
+	err = mali_core_subsystem_register_renderunit(&subsystem_maligp, core);
+	if (_MALI_OSK_ERR_OK != err) goto exit_on_error2;
+
+#ifdef DEBUG
+	MALI_DEBUG_PRINT(4, ("Mali GP: Initial Register settings:\n"));
+	maligp_print_regs(4, core);
+#endif
+
+	MALI_DEBUG_PRINT(6, ("Mali GP: maligp_renderunit_create\n") ) ;
+
+	MALI_SUCCESS;
+
+exit_on_error2:
+	mali_core_renderunit_unmap_registers(core);
+exit_on_error1:
+    mali_core_renderunit_term(core);
+exit_on_error0:
+	_mali_osk_free( core ) ;
+	MALI_PRINT_ERROR(("Renderunit NOT created."));
+    MALI_ERROR((_mali_osk_errcode_t)err);
+}
+
+#if USING_MMU
+/* Used currently only for signalling when MMU has a pagefault */
+static void maligp_subsystem_broadcast_notification(mali_core_notification_message message, u32 data)
+{
+	mali_core_subsystem_broadcast_notification(&subsystem_maligp, message, data);
+}
+#endif
+
+#ifdef DEBUG
+static void maligp_print_regs(int debug_level, mali_core_renderunit *core)
+{
+	if (debug_level <= mali_debug_level)
+	{
+		MALI_DEBUG_PRINT(1, ("  VS 0x%08X 0x%08X, PLBU 0x%08X 0x%08X ALLOC 0x%08X 0x%08X\n",
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR),
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VSCL_END_ADDR),
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBUCL_START_ADDR),
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBUCL_END_ADDR),
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR),
+			mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR))
+		);
+		MALI_DEBUG_PRINT(1, ("  IntRaw 0x%08X  IntMask 0x%08X, Status 0x%02X  Ver: 0x%08X \n",
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_MASK),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_STATUS),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VERSION)));
+
+		MALI_DEBUG_PRINT(1, ("  PERF_CNT Enbl:%d %d Src: %02d %02d  VAL: 0x%08X 0x%08X\n",
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE)));
+
+		MALI_DEBUG_PRINT(1, ("  VS_START 0x%08X PLBU_START 0x%08X  AXI_ERR 0x%08X\n",
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR_READ),
+				mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBCL_START_ADDR_READ),
+				mali_core_renderunit_register_read(core, MALIGP2_CONTR_AXI_BUS_ERROR_STAT)));
+	}
+}
+#endif
+
+static _mali_osk_errcode_t maligp_core_version_legal( mali_core_renderunit *core )
+{
+	u32 mali_type;
+
+	mali_type = core->core_version >> 16;
+
+#if defined(USING_MALI400)
+	if (  MALI400_GP_PRODUCT_ID != mali_type && MALI300_GP_PRODUCT_ID != mali_type )
+#else
+	if (  MALI_GP_PRODUCT_ID != mali_type )
+#endif
+	{
+		MALI_PRINT_ERROR(("Error: reading this from maligp version register: 0x%x\n", core->core_version));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+	MALI_DEBUG_PRINT(3, ("Mali GP: core_version_legal: Reads correct mali version: %d\n", core->core_version )) ;
+    MALI_SUCCESS;
+}
+
+static void subsystem_maligp_renderunit_stop_bus(struct mali_core_renderunit* core)
+{
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_STOP_BUS);
+}
+
+static void maligp_reset( mali_core_renderunit *core )
+{
+	if (!mali_benchmark) {
+		maligp_raw_reset(core);
+		maligp_initialize_registers_mgmt(core);
+	}
+}
+
+
+static void maligp_reset_hard( mali_core_renderunit *core )
+{
+	const int reset_finished_loop_count = 15;
+	const u32 reset_wait_target_register = MALIGP2_REG_ADDR_MGMT_WRITE_BOUND_LOW;
+	const u32 reset_invalid_value = 0xC0FFE000;
+	const u32 reset_check_value = 0xC01A0000;
+	const u32 reset_default_value = 0;
+	int i;
+
+	mali_core_renderunit_register_write(core, reset_wait_target_register, reset_invalid_value);
+
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_RESET);
+
+	for (i = 0; i < reset_finished_loop_count; i++)
+	{
+		mali_core_renderunit_register_write(core, reset_wait_target_register, reset_check_value);
+		if (reset_check_value == mali_core_renderunit_register_read(core, reset_wait_target_register))
+		{
+			MALI_DEBUG_PRINT(5, ("Reset loop exiting after %d iterations\n", i));
+			break;
+		}
+	}
+
+	if (i == reset_finished_loop_count)
+	{
+		MALI_DEBUG_PRINT(1, ("The reset loop didn't work\n"));
+	}
+
+	mali_core_renderunit_register_write(core, reset_wait_target_register, reset_default_value); /* set it back to the default */
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_MASK_ALL);
+	
+
+}
+
+static void maligp_raw_reset( mali_core_renderunit *core )
+{
+	int i;
+	const int request_loop_count = 20;
+
+	MALI_DEBUG_PRINT(4, ("Mali GP: maligp_raw_reset: %s\n", core->description)) ;
+	if (mali_benchmark) return;
+
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, 0); /* disable the IRQs */
+
+#if defined(USING_MALI200)
+
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_STOP_BUS);
+
+	for (i = 0; i < request_loop_count; i++)
+	{
+		if (mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_STATUS) & MALIGP2_REG_VAL_STATUS_BUS_STOPPED) break;
+		_mali_osk_time_ubusydelay(10);
+	}
+
+	MALI_DEBUG_PRINT_IF(1, request_loop_count == i, ("Mali GP: Bus was never stopped during core reset\n"));
+
+	if (request_loop_count==i)
+	{
+		/* Could not stop bus connections from core, probably because some of the already pending
+		bus request has had a page fault, and therefore can not complete before the MMU does PageFault
+		handling. This can be treated as a heavier reset function - which unfortunately reset all
+		the cores on this MMU in addition to the MMU itself */
+#if USING_MMU
+		if ((NULL!=core->mmu) && (MALI_FALSE == core->error_recovery))
+		{
+			MALI_DEBUG_PRINT(1, ("Mali GP: Forcing MMU bus reset\n"));
+			mali_kernel_mmu_force_bus_reset(core->mmu);
+			return;
+		}
+#endif
+		MALI_PRINT(("A MMU reset did not allow GP to stop its bus, system failure, unable to recover\n"));
+		return;
+	}
+
+	/* the bus was stopped OK, complete the reset */
+	/* use the hard reset routine to do the actual reset */
+	maligp_reset_hard(core);
+
+#elif defined(USING_MALI400)
+
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALI400GP_REG_VAL_IRQ_RESET_COMPLETED);
+	mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_CMD, MALI400GP_REG_VAL_CMD_SOFT_RESET);
+
+	for (i = 0; i < request_loop_count; i++)
+	{
+		if (mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT) & /*Bitwise OR*/
+				MALI400GP_REG_VAL_IRQ_RESET_COMPLETED) break;
+		_mali_osk_time_ubusydelay(10);
+	}
+
+	if ( request_loop_count==i )
+	{
+#if USING_MMU
+		/* Could not stop bus connections from core, probably because some of the already pending
+		   bus request has had a page fault, and therefore can not complete before the MMU does PageFault
+		   handling. This can be treated as a heavier reset function - which unfortunately reset all
+		   the cores on this MMU in addition to the MMU itself */
+		if ((NULL!=core->mmu) && (MALI_FALSE == core->error_recovery))
+		{
+			MALI_DEBUG_PRINT(1, ("Mali GP: Forcing Bus reset\n"));
+			mali_kernel_mmu_force_bus_reset(core->mmu);
+			return;
+		}
+#endif
+		MALI_PRINT(("A MMU reset did not allow GP to stop its bus, system failure, unable to recover\n"));
+	}
+	else
+	{
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_MASK_ALL);
+	}
+
+#else
+#error "no supported mali core defined"
+#endif
+}
+
+/* Sets the registers on maligp according to the const default_mgmt_regs array. */
+static void maligp_initialize_registers_mgmt(mali_core_renderunit *core )
+{
+	int i;
+
+	MALI_DEBUG_PRINT(6, ("Mali GP: maligp_initialize_registers_mgmt: %s\n", core->description)) ;
+	for(i=0 ; i< (sizeof(default_mgmt_regs)/sizeof(*default_mgmt_regs)) ; ++i)
+	{
+		mali_core_renderunit_register_write_relaxed(core, default_mgmt_regs[i].address, default_mgmt_regs[i].value);
+	}
+	_mali_osk_write_mem_barrier();
+}
+
+
+/* Start this job on this core. Return MALI_TRUE if the job was started. */
+static _mali_osk_errcode_t subsystem_maligp_start_job(mali_core_job * job, mali_core_renderunit * core)
+{
+	maligp_job 	*jobgp;
+	u32 startcmd;
+	/* The local extended version of the general structs */
+	jobgp  = _MALI_OSK_CONTAINER_OF(job, maligp_job, embedded_core_job);
+
+	startcmd = 0;
+	if ( jobgp->user_input.frame_registers[0] != jobgp->user_input.frame_registers[1] )
+	{
+		startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
+	}
+
+	if ( jobgp->user_input.frame_registers[2] != jobgp->user_input.frame_registers[3] )
+	{
+		startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
+	}
+
+	if(0 == startcmd)
+	{
+		MALI_DEBUG_PRINT(4, ("Mali GP: Job: 0x%08x  WILL NOT START SINCE JOB HAS ILLEGAL ADDRESSES\n",
+				(u32)jobgp->user_input.user_job_ptr));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+
+#ifdef DEBUG
+	MALI_DEBUG_PRINT(4, ("Mali GP: Registers Start\n"));
+	maligp_print_regs(4, core);
+#endif
+
+
+	mali_core_renderunit_register_write_array(
+			core,
+			MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR,
+			&(jobgp->user_input.frame_registers[0]),
+			sizeof(jobgp->user_input.frame_registers)/sizeof(jobgp->user_input.frame_registers[0]));
+
+#if MALI_TRACEPOINTS_ENABLED
+	jobgp->user_input.perf_counter_flag = 0;
+
+	if( counter_table[7] != 0xFFFFFFFF ) {
+		jobgp->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE;
+		jobgp->user_input.perf_counter_src0 = counter_table[7];
+	}
+	if( counter_table[8] != 0xFFFFFFFF ) {
+		jobgp->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE; 
+		jobgp->user_input.perf_counter_src1 = counter_table[8];
+	}
+#endif
+
+	/* This selects which performance counters we are reading */
+	if ( 0 != jobgp->user_input.perf_counter_flag )
+	{
+		if ( jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
+		{
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC,
+					jobgp->user_input.perf_counter_src0);
+
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE,
+					MALIGP2_REG_VAL_PERF_CNT_ENABLE);
+		}
+
+		if ( jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
+		{
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC,
+					jobgp->user_input.perf_counter_src1);
+
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE,
+					MALIGP2_REG_VAL_PERF_CNT_ENABLE);
+		}
+
+#if defined(USING_MALI400_L2_CACHE)
+		if ( jobgp->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
+		{
+			int force_reset = ( jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET ) ? 1 : 0;
+			u32 src0 = 0;
+			u32 src1 = 0;
+
+			if ( jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE )
+			{
+				src0 = jobgp->user_input.perf_counter_l2_src0;
+			}
+			if ( jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE )
+			{
+				src1 = jobgp->user_input.perf_counter_l2_src1;
+			}
+
+			mali_kernel_l2_cache_set_perf_counters(src0, src1, force_reset); /* will activate and possibly reset counters */
+
+			/* Now, retrieve the current values, so we can substract them when the job has completed */
+			mali_kernel_l2_cache_get_perf_counters(&jobgp->perf_counter_l2_src0,
+			                                       &jobgp->perf_counter_l2_val0,
+			                                       &jobgp->perf_counter_l2_src1,
+			                                       &jobgp->perf_counter_l2_val1);
+		}
+#endif
+	}
+
+	if ( 0 == (jobgp->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE))
+	{
+		/* extended progress checking can be enabled */
+
+		jobgp->have_extended_progress_checking = 1;
+
+		mali_core_renderunit_register_write_relaxed(
+				core,
+		MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC,
+		MALIGP2_REG_VAL_PERF_CNT1_SRC_NUMBER_OF_VERTICES_PROCESSED
+										   );
+
+		mali_core_renderunit_register_write_relaxed(
+				core,
+		MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE,
+		MALIGP2_REG_VAL_PERF_CNT_ENABLE);
+	}
+
+	subsystem_flush_mapped_mem_cache();
+
+	MALI_DEBUG_PRINT(4, ("Mali GP: STARTING GP WITH CMD: 0x%x\n", startcmd));
+#if MALI_STATE_TRACKING
+	 _mali_osk_atomic_inc(&job->session->jobs_started);
+#endif
+
+	/* This is the command that starts the Core */
+	mali_core_renderunit_register_write(core,
+										MALIGP2_REG_ADDR_MGMT_CMD,
+										startcmd);
+	_mali_osk_write_mem_barrier();
+
+	pr_debug("SPI_GPU_GP Start\n");
+#if MALI_TIMELINE_PROFILING_ENABLED
+	_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH,
+	                          jobgp->user_input.frame_builder_id, jobgp->user_input.flush_id, 0, 0, 0);
+	_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), jobgp->pid, jobgp->tid, 0, 0, 0);
+#endif
+
+	MALI_SUCCESS;
+}
+
+/* Check if given core has an interrupt pending. Return MALI_TRUE and set mask to 0 if pending */
+
+static u32 subsystem_maligp_irq_handler_upper_half(mali_core_renderunit * core)
+{
+	u32 irq_readout;
+
+	if (mali_benchmark) {
+		return (core->current_job ? 1 : 0); /* simulate irq is pending when a job is pending */
+	}
+
+	irq_readout = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_STAT);
+
+	MALI_DEBUG_PRINT(5, ("Mali GP: IRQ: %04x\n", irq_readout)) ;
+
+	if ( MALIGP2_REG_VAL_IRQ_MASK_NONE != irq_readout )
+	{
+		/* Mask out all IRQs from this core until IRQ is handled */
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_NONE);
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number)|MALI_PROFILING_EVENT_REASON_SINGLE_HW_INTERRUPT, irq_readout, 0, 0, 0, 0);
+#endif
+
+		/* We do need to handle this in a bottom half, return 1 */
+		return 1;
+	}
+	return 0;
+}
+
+/* This function should check if the interrupt indicates that job was finished.
+If so it should update the job-struct, reset the core registers, and return MALI_TRUE, .
+If the job is still working after this function it should return MALI_FALSE.
+The function must also enable the bits in the interrupt mask for the core.
+Called by the bottom half interrupt function. */
+static int subsystem_maligp_irq_handler_bottom_half(mali_core_renderunit* core)
+{
+	mali_core_job * job;
+	maligp_job * jobgp;
+	u32 irq_readout;
+	u32 core_status;
+	u32 vscl;
+	u32 plbcl;
+
+	job = core->current_job;
+
+	if (mali_benchmark) {
+		MALI_DEBUG_PRINT(3, ("MaliGP: Job: Benchmark\n") );
+		irq_readout = MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST;
+		core_status = 0;
+	} else {
+		irq_readout = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT) & MALIGP2_REG_VAL_IRQ_MASK_USED;
+		core_status = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_STATUS);
+	}
+
+	if (NULL == job)
+	{
+		MALI_DEBUG_ASSERT(CORE_IDLE==core->state);
+		if ( 0 != irq_readout )
+		{
+			MALI_PRINT_ERROR(("Interrupt from a core not running a job. IRQ: 0x%04x Status: 0x%04x", irq_readout, core_status));
+		}
+		return JOB_STATUS_END_UNKNOWN_ERR;
+	}
+	MALI_DEBUG_ASSERT(CORE_IDLE!=core->state);
+
+	jobgp = GET_JOBGP2_PTR(job);
+
+	jobgp->heap_current_addr = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR);
+
+	vscl = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR);
+	plbcl = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBUCL_START_ADDR);
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: Job: 0x%08x  IRQ RECEIVED  Rawstat: 0x%x Status: 0x%x\n",
+			(u32)jobgp->user_input.user_job_ptr, irq_readout , core_status )) ;
+
+	jobgp->irq_status |= irq_readout;
+	jobgp->status_reg_on_stop = core_status;
+
+	if ( 0 != jobgp->is_stalled_waiting_for_more_memory )
+	{
+		/* Readback the performance counters */
+		if (jobgp->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE) )
+		{
+			jobgp->perf_counter0 = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
+			jobgp->perf_counter1 = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
+
+#if MALI_TRACEPOINTS_ENABLED
+			//TODO magic numbers should come from mali_linux_trace.h instead
+			_mali_profiling_add_counter(7, jobgp->perf_counter0);
+			_mali_profiling_add_counter(8, jobgp->perf_counter1);
+#endif
+		}
+
+#if defined(USING_MALI400_L2_CACHE)
+		if (jobgp->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
+		{
+			u32 src0;
+			u32 val0;
+			u32 src1;
+			u32 val1;
+			mali_kernel_l2_cache_get_perf_counters(&src0, &val0, &src1, &val1);
+
+			if (jobgp->perf_counter_l2_src0 == src0)
+			{
+				jobgp->perf_counter_l2_val0 = val0 - jobgp->perf_counter_l2_val0;
+			}
+			else
+			{
+				jobgp->perf_counter_l2_val0 = 0;
+			}
+
+			if (jobgp->perf_counter_l2_src1 == src1)
+			{
+				jobgp->perf_counter_l2_val1 = val1 - jobgp->perf_counter_l2_val1;
+			}
+			else
+			{
+				jobgp->perf_counter_l2_val1 = 0;
+			}
+		}
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status? */
+#endif
+
+		MALI_DEBUG_PRINT(2, ("Mali GP: Job aborted - userspace would not provide more heap memory.\n"));
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		return JOB_STATUS_END_OOM; /* Core is ready for more jobs.*/
+	}
+	/* finished ? */
+	else if (0 == (core_status & MALIGP2_REG_VAL_STATUS_MASK_ACTIVE))
+	{
+#ifdef DEBUG
+		MALI_DEBUG_PRINT(4, ("Mali GP: Registers On job end:\n"));
+		maligp_print_regs(4, core);
+#endif
+		MALI_DEBUG_PRINT_IF(5, irq_readout & 0x04, ("OOM when done, ignoring (reg.current = 0x%x, reg.end = 0x%x)\n",
+		           (void*)mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR),
+		           (void*)mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR))
+		          );
+
+
+		if (0 != jobgp->user_input.perf_counter_flag )
+		{
+			/* Readback the performance counters */
+			if (jobgp->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE) )
+			{
+				jobgp->perf_counter0 = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
+				jobgp->perf_counter1 = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
+
+#if MALI_TRACEPOINTS_ENABLED
+                //TODO magic numbers should come from mali_linux_trace.h instead
+                _mali_profiling_add_counter(7, jobgp->perf_counter0);
+                _mali_profiling_add_counter(8, jobgp->perf_counter1);
+#endif
+			}
+
+#if defined(USING_MALI400_L2_CACHE)
+			if (jobgp->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
+			{
+				u32 src0;
+				u32 val0;
+				u32 src1;
+				u32 val1;
+				mali_kernel_l2_cache_get_perf_counters(&src0, &val0, &src1, &val1);
+
+				if (jobgp->perf_counter_l2_src0 == src0)
+				{
+					jobgp->perf_counter_l2_val0 = val0 - jobgp->perf_counter_l2_val0;
+				}
+				else
+				{
+					jobgp->perf_counter_l2_val0 = 0;
+				}
+
+				if (jobgp->perf_counter_l2_src1 == src1)
+				{
+					jobgp->perf_counter_l2_val1 = val1 - jobgp->perf_counter_l2_val1;
+				}
+				else
+				{
+					jobgp->perf_counter_l2_val1 = 0;
+				}
+			}
+#endif
+		}
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number),
+				jobgp->perf_counter0, jobgp->perf_counter1,
+				jobgp->user_input.perf_counter_src0 | (jobgp->user_input.perf_counter_src1 << 8)
+#if defined(USING_MALI400_L2_CACHE)
+				| (jobgp->user_input.perf_counter_l2_src0 << 16) | (jobgp->user_input.perf_counter_l2_src1 << 24),
+				jobgp->perf_counter_l2_val0,
+				jobgp->perf_counter_l2_val1
+#else
+				,0, 0
+#endif
+				);
+#endif
+
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_MASK_ALL);
+
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		pr_debug("SPI_GPU_GP Idle\n");
+		return JOB_STATUS_END_SUCCESS; /* core idle */
+	}
+	/* sw watchdog timeout handling or time to do hang checking ? */
+	else if (
+	         (CORE_WATCHDOG_TIMEOUT == core->state) ||
+	         (
+	          (CORE_HANG_CHECK_TIMEOUT == core->state) &&
+              (
+	           (jobgp->have_extended_progress_checking ? (mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE) == jobgp->vertices) : 1/*TRUE*/) &&
+	           ((core_status & MALIGP2_REG_VAL_STATUS_VS_ACTIVE) ? (vscl == jobgp->last_vscl) : 1/*TRUE*/) &&
+	           ((core_status & MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE) ? (plbcl == jobgp->last_plbcl) : 1/*TRUE*/)
+	          )
+	         )
+	        )
+	{
+		/* no progress detected, killed by the watchdog */
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status? */
+#endif
+
+		MALI_PRINT( ("Mali GP: SW-Timeout.\n"));
+		if (core_status & MALIGP2_REG_VAL_STATUS_VS_ACTIVE) MALI_DEBUG_PRINT(1, ("vscl current = 0x%x last = 0x%x\n", (void*)vscl, (void*)jobgp->last_vscl));
+		if (core_status & MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE) MALI_DEBUG_PRINT(1, ("plbcl current = 0x%x last = 0x%x\n", (void*)plbcl, (void*)jobgp->last_plbcl));
+		if (jobgp->have_extended_progress_checking) MALI_DEBUG_PRINT(1, ("vertices processed = %d, last = %d\n", mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE),
+		jobgp->vertices));
+#ifdef DEBUG
+		maligp_print_regs(2, core);
+#endif
+
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		MALI_PANIC("%s Watchdog timeout\n", MALI_GP_SUBSYSTEM_NAME);
+		return JOB_STATUS_END_HANG;
+	}
+	/* if hang timeout checking was enabled and we detected progress, will be fall down to this check */
+	/* check for PLBU OOM before the hang check to avoid the race condition of the hw wd trigging while waiting for us to handle the OOM interrupt */
+	else if ( 0 != (irq_readout & MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM))
+	{
+		mali_core_session *session;
+		_mali_osk_notification_t *notific;
+		_mali_uk_gp_job_suspended_s * suspended_job;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SUSPEND|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status? */
+#endif
+
+		session = job->session;
+
+		MALI_DEBUG_PRINT(4, ("OOM, new heap requested by GP\n"));
+		MALI_DEBUG_PRINT(4, ("Status when OOM: current = 0x%x, end = 0x%x\n",
+		         (void*)mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR),
+		         (void*)mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR))
+		       );
+
+		notific = _mali_osk_notification_create(
+
+		                                       _MALI_NOTIFICATION_GP_STALLED,
+		                                       sizeof( _mali_uk_gp_job_suspended_s )
+		                                      );
+        if ( NULL == notific)
+		{
+			MALI_PRINT_ERROR( ("Mali GP: Could not get notification object\n")) ;
+			return JOB_STATUS_END_OOM; /* Core is ready for more jobs.*/
+		}
+
+		core->state = CORE_WORKING;
+		jobgp->is_stalled_waiting_for_more_memory = 1;
+		suspended_job = (_mali_uk_gp_job_suspended_s *)notific->result_buffer; /* this is ok - result_buffer was malloc'd */
+
+		suspended_job->user_job_ptr = jobgp->user_input.user_job_ptr;
+		suspended_job->reason = _MALIGP_JOB_SUSPENDED_OUT_OF_MEMORY ;
+		suspended_job->cookie = (u32) core;
+		last_gp_core_cookie = core;
+
+		_mali_osk_notification_queue_send( session->notification_queue, notific);
+
+#ifdef DEBUG
+		maligp_print_regs(4, core);
+#endif
+
+		/* stop all active timers */
+		_mali_osk_timer_del( core->timer);
+		_mali_osk_timer_del( core->timer_hang_detection);
+		MALI_DEBUG_PRINT(4, ("Mali GP: PLBU heap empty, sending memory request to userspace\n"));
+		/* save to watchdog_jiffies what was remaining WD timeout value when OOM was triggered */
+		job->watchdog_jiffies = (long)job->watchdog_jiffies - (long)_mali_osk_time_tickcount();
+		/* reuse core->timer as the userspace response timeout handler */
+		_mali_osk_timer_add( core->timer, _mali_osk_time_mstoticks(1000) ); /* wait max 1 sec for userspace to respond */
+		return JOB_STATUS_CONTINUE_RUN; /* The core is NOT available for new jobs. */
+	}
+	/* hw watchdog is reporting a new hang or an existing progress-during-hang check passed? */
+	else if	((CORE_HANG_CHECK_TIMEOUT == core->state) || (irq_readout & jobgp->active_mask & MALIGP2_REG_VAL_IRQ_HANG))
+	{
+		/* check interval in ms */
+		u32 timeout = mali_core_hang_check_timeout_get();
+		MALI_DEBUG_PRINT(3, ("Mali GP: HW/SW Watchdog triggered, checking for progress in %d ms\n", timeout));
+		core->state = CORE_WORKING;
+
+		/* save state for the progress checking */
+		jobgp->last_vscl = vscl;
+		jobgp->last_plbcl = plbcl;
+		if (jobgp->have_extended_progress_checking)
+		{
+			jobgp->vertices = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
+		}
+        /* hw watchdog triggered, set up a progress checker every HANGCHECK ms */
+        _mali_osk_timer_add( core->timer_hang_detection, _mali_osk_time_mstoticks(timeout));
+		jobgp->active_mask &= ~MALIGP2_REG_VAL_IRQ_HANG; /* ignore the hw watchdog from now on */
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, irq_readout);
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, jobgp->active_mask);
+		return JOB_STATUS_CONTINUE_RUN; /* not finihsed */ }
+	/* no errors, but still working */
+	else if ( ( 0 == (core_status & MALIGP2_REG_VAL_STATUS_MASK_ERROR)) &&
+	          ( 0 != (core_status & MALIGP2_REG_VAL_STATUS_MASK_ACTIVE ))
+	        )
+	{
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, irq_readout);
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, jobgp->active_mask);
+		return JOB_STATUS_CONTINUE_RUN;
+	}
+	/* Else there must be some error */
+	else
+	{
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status? */
+#endif
+
+		MALI_PRINT( ("Mali GP: Core crashed? *IRQ: 0x%x Status: 0x%x\n", irq_readout, core_status ));
+		#ifdef DEBUG
+		MALI_DEBUG_PRINT(1, ("Mali GP: Registers Before reset:\n"));
+		maligp_print_regs(1, core);
+		#endif
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		return JOB_STATUS_END_UNKNOWN_ERR;
+	}
+}
+
+
+/* This function is called from the ioctl function and should return a mali_core_job pointer
+to a created mali_core_job object with the data given from userspace */
+static _mali_osk_errcode_t subsystem_maligp_get_new_job_from_user(struct mali_core_session * session, void * argument)
+{
+	maligp_job *jobgp;
+	mali_core_job *job = NULL;
+	mali_core_job *previous_replaced_job;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+	_mali_uk_gp_start_job_s * user_ptr_job_input;
+
+	user_ptr_job_input = (_mali_uk_gp_start_job_s *)argument;
+
+    MALI_CHECK_NON_NULL(jobgp = (maligp_job *) _mali_osk_calloc(1, sizeof(maligp_job)), _MALI_OSK_ERR_FAULT);
+
+	/* Copy the job data from the U/K interface */
+	if ( NULL == _mali_osk_memcpy(&jobgp->user_input, user_ptr_job_input, sizeof(_mali_uk_gp_start_job_s) ) )
+	{
+		MALI_PRINT_ERROR( ("Mali GP: Could not copy data from U/K interface.\n")) ;
+        err = _MALI_OSK_ERR_FAULT;
+		goto function_exit;
+	}
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: subsystem_maligp_get_new_job_from_user 0x%x\n", (void*)jobgp->user_input.user_job_ptr));
+
+	MALI_DEBUG_PRINT(3, ("Mali GP: Job Regs: 0x%08X 0x%08X, 0x%08X 0x%08X 0x%08X 0x%08X\n",
+			jobgp->user_input.frame_registers[0],
+			jobgp->user_input.frame_registers[1],
+			jobgp->user_input.frame_registers[2],
+			jobgp->user_input.frame_registers[3],
+			jobgp->user_input.frame_registers[4],
+			jobgp->user_input.frame_registers[5])  );
+
+
+	job = GET_JOB_EMBEDDED_PTR(jobgp);
+
+	job->session = session;
+	job->flags = MALI_UK_START_JOB_FLAG_DEFAULT; /* Current flags only make sence for PP jobs */
+	job_priority_set(job, jobgp->user_input.priority);
+	job_watchdog_set(job, jobgp->user_input.watchdog_msecs );
+	jobgp->heap_current_addr = jobgp->user_input.frame_registers[4];
+
+	job->abort_id = jobgp->user_input.abort_id;
+
+	jobgp->is_stalled_waiting_for_more_memory = 0;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	jobgp->pid = _mali_osk_get_pid();
+	jobgp->tid = _mali_osk_get_tid();
+#endif
+
+	if (mali_job_queue_full(session))
+	{
+		/* Cause jobgp to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE;
+		goto function_exit;
+	}
+
+	/* We now know that we have a job, and a slot to put it in */
+
+	jobgp->active_mask = MALIGP2_REG_VAL_IRQ_MASK_USED;
+
+	/* Allocating User Return Data */
+	jobgp->notification_obj = _mali_osk_notification_create(
+			_MALI_NOTIFICATION_GP_FINISHED,
+			sizeof(_mali_uk_gp_job_finished_s) );
+
+	if ( NULL == jobgp->notification_obj )
+	{
+		MALI_PRINT_ERROR( ("Mali GP: Could not get notification_obj.\n")) ;
+		err = _MALI_OSK_ERR_NOMEM;
+		goto function_exit;
+	}
+
+	_MALI_OSK_INIT_LIST_HEAD( &(job->list) ) ;
+
+	MALI_DEBUG_PRINT(4, ("Mali GP: Job: 0x%08x INPUT from user.\n", (u32)jobgp->user_input.user_job_ptr)) ;
+
+	/* This should not happen since we have the checking of priority above */
+	err = mali_core_session_add_job(session, job, &previous_replaced_job);
+	if ( _MALI_OSK_ERR_OK != err )
+	{
+		MALI_PRINT_ERROR( ("Mali GP: Internal error\n")) ;
+		/* Cause jobgp to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE;
+		_mali_osk_notification_delete( jobgp->notification_obj );
+		goto function_exit;
+	}
+
+	/* If MALI_TRUE: This session had a job with lower priority which were removed.
+	This replaced job is given back to userspace. */
+	if ( NULL != previous_replaced_job )
+	{
+		maligp_job *previous_replaced_jobgp;
+
+		previous_replaced_jobgp = GET_JOBGP2_PTR(previous_replaced_job);
+
+		MALI_DEBUG_PRINT(4, ("Mali GP: Replacing job: 0x%08x\n", (u32)previous_replaced_jobgp->user_input.user_job_ptr)) ;
+
+		/* Copy to the input data (which also is output data) the
+		pointer to the job that were replaced, so that the userspace
+		driver can put this job in the front of its job-queue */
+		user_ptr_job_input->returned_user_job_ptr = previous_replaced_jobgp->user_input.user_job_ptr;
+
+		/** @note failure to 'copy to user' at this point must not free jobgp,
+		 * and so no transaction rollback required in the U/K interface */
+
+		/* This does not cause jobgp to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED;
+		MALI_DEBUG_PRINT(5, ("subsystem_maligp_get_new_job_from_user: Job added, prev returned\n")) ;
+	}
+	else
+	{
+		/* This does not cause jobgp to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_STARTED;
+		MALI_DEBUG_PRINT(5, ("subsystem_maligp_get_new_job_from_user: Job added\n")) ;
+	}
+
+function_exit:
+	if ( _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE == user_ptr_job_input->status
+		|| _MALI_OSK_ERR_OK != err )
+	{
+		_mali_osk_free(jobgp);
+	}
+#if MALI_STATE_TRACKING
+	if (_MALI_UK_START_JOB_STARTED==user_ptr_job_input->status)
+	{
+		if(job)
+		{
+			job->job_nr=_mali_osk_atomic_inc_return(&session->jobs_received);
+		}
+	}
+#endif
+
+	MALI_ERROR(err);
+}
+
+
+static _mali_osk_errcode_t subsystem_maligp_suspend_response(struct mali_core_session * session, void * argument)
+{
+	mali_core_renderunit *core;
+	maligp_job *jobgp;
+	mali_core_job *job;
+
+	_mali_uk_gp_suspend_response_s * suspend_response;
+
+	MALI_DEBUG_PRINT(5, ("subsystem_maligp_suspend_response\n"));
+
+	suspend_response = (_mali_uk_gp_suspend_response_s *)argument;
+
+	/* We read job data from User */
+	/* On a single mali_gp system we can only have one Stalled GP,
+	and therefore one stalled request with a cookie. This checks
+	that we get the correct cookie */
+	if ( last_gp_core_cookie != (mali_core_renderunit *)suspend_response->cookie )
+	{
+		MALI_DEBUG_PRINT(2, ("Mali GP: Got an illegal cookie from Userspace.\n")) ;
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+	core = (mali_core_renderunit *)suspend_response->cookie;
+	last_gp_core_cookie = NULL;
+	job = core->current_job;
+	jobgp = GET_JOBGP2_PTR(job);
+
+	switch( suspend_response->code )
+	{
+		case _MALIGP_JOB_RESUME_WITH_NEW_HEAP :
+			MALI_DEBUG_PRINT(5, ("MALIGP_JOB_RESUME_WITH_NEW_HEAP jiffies: %li\n", _mali_osk_time_tickcount()));
+			MALI_DEBUG_PRINT(4, ("New Heap addr 0x%08x - 0x%08x\n", suspend_response->arguments[0], suspend_response->arguments[1]));
+
+			jobgp->is_stalled_waiting_for_more_memory = 0;
+			job->watchdog_jiffies += _mali_osk_time_tickcount(); /* convert to absolute time again */
+			_mali_osk_timer_mod( core->timer, job->watchdog_jiffies); /* update the timer */
+
+
+			mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, (MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | MALIGP2_REG_VAL_IRQ_HANG));
+			mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, jobgp->active_mask);
+			mali_core_renderunit_register_write_relaxed(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR, suspend_response->arguments[0]);
+			mali_core_renderunit_register_write_relaxed(core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR, suspend_response->arguments[1]);
+			mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC);
+			_mali_osk_write_mem_barrier();
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+			_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_RESUME|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(core->core_number), 0, 0, 0, 0, 0);
+#endif
+
+			MALI_DEBUG_PRINT(4, ("GP resumed with new heap\n"));
+
+			break;
+
+		case _MALIGP_JOB_ABORT:
+			MALI_DEBUG_PRINT(3, ("MALIGP_JOB_ABORT on heap extend request\n"));
+			_mali_osk_irq_schedulework( core->irq );
+			break;
+
+		default:
+			MALI_PRINT_ERROR(("Wrong Suspend response from userspace\n"));
+	}
+    MALI_SUCCESS;
+}
+
+/* This function is called from the ioctl function and should write the necessary data
+to userspace telling which job was finished and the status and debuginfo for this job.
+The function must also free and cleanup the input job object. */
+static void subsystem_maligp_return_job_to_user( mali_core_job * job, mali_subsystem_job_end_code end_status )
+{
+	maligp_job 	*jobgp;
+	_mali_uk_gp_job_finished_s * job_out;
+	_mali_uk_gp_start_job_s* job_input;
+	mali_core_session *session;
+
+
+	jobgp  = _MALI_OSK_CONTAINER_OF(job, maligp_job, embedded_core_job);
+	job_out =  (_mali_uk_gp_job_finished_s *)jobgp->notification_obj->result_buffer; /* OK - this should've been malloc'd */
+	job_input= &(jobgp->user_input);
+	session = job->session;
+
+	MALI_DEBUG_PRINT(5, ("Mali GP: Job: 0x%08x OUTPUT to user. Runtime: %d us, irq readout %x\n",
+			(u32)jobgp->user_input.user_job_ptr,
+			job->render_time_usecs,
+		   	jobgp->irq_status)) ;
+
+	_mali_osk_memset(job_out, 0 , sizeof(_mali_uk_gp_job_finished_s));
+
+	job_out->user_job_ptr = job_input->user_job_ptr;
+
+	switch( end_status )
+	{
+		case JOB_STATUS_CONTINUE_RUN:
+		case JOB_STATUS_END_SUCCESS:
+		case JOB_STATUS_END_OOM:
+		case JOB_STATUS_END_ABORT:
+		case JOB_STATUS_END_TIMEOUT_SW:
+		case JOB_STATUS_END_HANG:
+		case JOB_STATUS_END_SEG_FAULT:
+		case JOB_STATUS_END_ILLEGAL_JOB:
+		case JOB_STATUS_END_UNKNOWN_ERR:
+		case JOB_STATUS_END_SHUTDOWN:
+		case JOB_STATUS_END_SYSTEM_UNUSABLE:
+			job_out->status = (mali_subsystem_job_end_code) end_status;
+			break;
+		default:
+			job_out->status = JOB_STATUS_END_UNKNOWN_ERR ;
+	}
+
+	job_out->irq_status = jobgp->irq_status;
+	job_out->status_reg_on_stop = jobgp->status_reg_on_stop;
+	job_out->vscl_stop_addr  = 0;
+	job_out->plbcl_stop_addr = 0;
+	job_out->heap_current_addr  = jobgp->heap_current_addr;
+	job_out->perf_counter0 = jobgp->perf_counter0;
+	job_out->perf_counter1 = jobgp->perf_counter1;
+	job_out->perf_counter_src0 = jobgp->user_input.perf_counter_src0 ;
+	job_out->perf_counter_src1 = jobgp->user_input.perf_counter_src1 ;
+	job_out->render_time = job->render_time_usecs;
+#if defined(USING_MALI400_L2_CACHE)
+	job_out->perf_counter_l2_src0 = jobgp->perf_counter_l2_src0;
+	job_out->perf_counter_l2_src1 = jobgp->perf_counter_l2_src1;
+	job_out->perf_counter_l2_val0 = jobgp->perf_counter_l2_val0;
+	job_out->perf_counter_l2_val1 = jobgp->perf_counter_l2_val1;
+#endif
+
+#if MALI_STATE_TRACKING
+	_mali_osk_atomic_inc(&session->jobs_returned);
+#endif
+	_mali_osk_notification_queue_send( session->notification_queue, jobgp->notification_obj);
+	jobgp->notification_obj = NULL;
+
+	_mali_osk_free(jobgp);
+
+	last_gp_core_cookie = NULL;
+}
+
+static void subsystem_maligp_renderunit_delete(mali_core_renderunit * core)
+{
+	MALI_DEBUG_PRINT(5, ("Mali GP: maligp_renderunit_delete\n"));
+	_mali_osk_free(core);
+}
+
+static void subsystem_maligp_renderunit_reset_core(struct mali_core_renderunit * core, mali_core_reset_style style)
+{
+	MALI_DEBUG_PRINT(5, ("Mali GP: renderunit_reset_core\n"));
+
+	switch (style)
+	{
+		case MALI_CORE_RESET_STYLE_RUNABLE:
+			maligp_reset(core);
+			break;
+		case MALI_CORE_RESET_STYLE_DISABLE:
+			maligp_raw_reset(core); /* do the raw reset */
+			mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_MASK, 0); /* then disable the IRQs */
+			break;
+		case MALI_CORE_RESET_STYLE_HARD:
+			maligp_reset_hard(core);
+			maligp_initialize_registers_mgmt(core);
+			break;
+		default:
+			MALI_DEBUG_PRINT(1, ("Unknown reset type %d\n", style));
+			break;
+	}
+}
+
+static void subsystem_maligp_renderunit_probe_core_irq_trigger(struct mali_core_renderunit* core)
+{
+    mali_core_renderunit_register_write(core , MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED);
+	mali_core_renderunit_register_write(core , MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT, MALIGP2_REG_VAL_CMD_FORCE_HANG );
+	_mali_osk_mem_barrier();
+}
+
+static _mali_osk_errcode_t subsystem_maligp_renderunit_probe_core_irq_finished(struct mali_core_renderunit* core)
+{
+	u32 irq_readout;
+
+	irq_readout = mali_core_renderunit_register_read(core, MALIGP2_REG_ADDR_MGMT_INT_STAT);
+
+	if ( MALIGP2_REG_VAL_IRQ_FORCE_HANG & irq_readout )
+	{
+		mali_core_renderunit_register_write(core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_FORCE_HANG);
+		_mali_osk_mem_barrier();
+		MALI_SUCCESS;
+	}
+
+    MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+_mali_osk_errcode_t _mali_ukk_gp_start_job( _mali_uk_gp_start_job_s *args )
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_gp_id);
+    MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+    return mali_core_subsystem_ioctl_start_job(session, args);
+}
+
+_mali_osk_errcode_t _mali_ukk_get_gp_number_of_cores( _mali_uk_get_gp_number_of_cores_s *args )
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_gp_id);
+    MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+    return mali_core_subsystem_ioctl_number_of_cores_get(session, &args->number_of_cores);
+}
+
+_mali_osk_errcode_t _mali_ukk_get_gp_core_version( _mali_uk_get_gp_core_version_s *args )
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_gp_id);
+    MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+    return mali_core_subsystem_ioctl_core_version_get(session, &args->version);
+}
+
+_mali_osk_errcode_t _mali_ukk_gp_suspend_response( _mali_uk_gp_suspend_response_s *args )
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_gp_id);
+    MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+    return mali_core_subsystem_ioctl_suspend_response(session, args);
+}
+
+void _mali_ukk_gp_abort_job( _mali_uk_gp_abort_job_s * args)
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    if (NULL == args->ctx) return;
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_gp_id);
+    if (NULL == session) return;
+    mali_core_subsystem_ioctl_abort_job(session, args->abort_id);
+
+}
+
+#if USING_MALI_PMM
+
+_mali_osk_errcode_t maligp_signal_power_up( mali_bool queue_only )
+{
+	MALI_DEBUG_PRINT(4, ("Mali GP: signal power up core - queue_only: %d\n", queue_only ));
+
+	return( mali_core_subsystem_signal_power_up( &subsystem_maligp, 0, queue_only ) );
+}
+	
+_mali_osk_errcode_t maligp_signal_power_down( mali_bool immediate_only )
+{
+	MALI_DEBUG_PRINT(4, ("Mali GP: signal power down core - immediate_only: %d\n", immediate_only ));
+
+	return( mali_core_subsystem_signal_power_down( &subsystem_maligp, 0, immediate_only ) );
+}
+
+#endif
+
+#if MALI_STATE_TRACKING
+u32 maligp_subsystem_dump_state(char *buf, u32 size)
+{
+	return mali_core_renderunit_dump_state(&subsystem_maligp, buf, size);
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_MALI200.c b/drivers/media/video/samsung/mali/common/mali_kernel_MALI200.c
new file mode 100644
index 0000000..0f5ebd0
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_MALI200.c
@@ -0,0 +1,1304 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+//added for SPI
+#include <linux/kernel.h>
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_kernel_pp.h"
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_core.h"
+#include "regs/mali_200_regs.h"
+#include "mali_kernel_rendercore.h"
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+#ifdef USING_MALI400_L2_CACHE
+#include "mali_kernel_l2_cache.h"
+#endif
+#if USING_MMU
+#include "mali_kernel_mem_mmu.h" /* Needed for mali_kernel_mmu_force_bus_reset() */
+#endif
+
+#include "mali_osk_list.h"
+
+#if defined(USING_MALI200)
+#define MALI_PP_SUBSYSTEM_NAME "Mali200"
+#define MALI_PP_CORE_TYPE      _MALI_200
+#elif defined(USING_MALI400)
+#define MALI_PP_SUBSYSTEM_NAME "Mali-400 PP"
+#define MALI_PP_CORE_TYPE      _MALI_400_PP
+#else
+#error "No supported mali core defined"
+#endif
+
+#define GET_JOB_EMBEDDED_PTR(job) (&((job)->embedded_core_job))
+#define GET_JOB200_PTR(job_extern) _MALI_OSK_CONTAINER_OF(job_extern, mali200_job, embedded_core_job)
+
+/* Initialized when this subsystem is initialized. This is determined by the
+ * position in subsystems[], and so the value used to initialize this is
+ * determined at compile time */
+static mali_kernel_subsystem_identifier mali_subsystem_mali200_id = -1;
+
+/* Describing a mali200 job settings */
+typedef struct mali200_job
+{
+	/* The general job struct common for all mali cores */
+	mali_core_job embedded_core_job;
+	_mali_uk_pp_start_job_s user_input;
+
+	u32 irq_status;
+	u32 perf_counter0;
+	u32 perf_counter1;
+	u32 last_tile_list_addr; /* Neccessary to continue a stopped job */
+
+	u32 active_mask;
+
+	/* The data we will return back to the user */
+	_mali_osk_notification_t *notification_obj;
+
+#if defined(USING_MALI400_L2_CACHE)
+	u32 perf_counter_l2_src0;
+	u32 perf_counter_l2_src1;
+	u32 perf_counter_l2_val0;
+	u32 perf_counter_l2_val1;
+	u32 perf_counter_l2_val0_raw;
+	u32 perf_counter_l2_val1_raw;
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	u32 pid;
+	u32 tid;
+#endif
+} mali200_job;
+
+
+/*Functions Exposed to the General External System through
+  funciont pointers.*/
+
+static _mali_osk_errcode_t mali200_subsystem_startup(mali_kernel_subsystem_identifier id);
+#if USING_MMU
+static _mali_osk_errcode_t mali200_subsystem_mmu_connect(mali_kernel_subsystem_identifier id);
+#endif
+static void mali200_subsystem_terminate(mali_kernel_subsystem_identifier id);
+static _mali_osk_errcode_t mali200_subsystem_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+static void mali200_subsystem_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot);
+static _mali_osk_errcode_t mali200_subsystem_core_system_info_fill(_mali_system_info* info);
+static _mali_osk_errcode_t mali200_renderunit_create(_mali_osk_resource_t * resource);
+#if USING_MMU
+static void mali200_subsystem_broadcast_notification(mali_core_notification_message message, u32 data);
+#endif
+#if MALI_STATE_TRACKING
+u32 mali200_subsystem_dump_state(char *buf, u32 size);
+#endif
+
+/* Internal support functions  */
+static _mali_osk_errcode_t mali200_core_version_legal( mali_core_renderunit *core );
+static void mali200_reset(mali_core_renderunit *core);
+static void mali200_reset_hard(struct mali_core_renderunit * core);
+static void mali200_raw_reset(mali_core_renderunit * core);
+static void mali200_initialize_registers_mgmt(mali_core_renderunit *core );
+
+/* Functions exposed to mali_core system through functionpointers
+   in the subsystem struct. */
+static _mali_osk_errcode_t subsystem_mali200_start_job(mali_core_job * job, mali_core_renderunit * core);
+static _mali_osk_errcode_t subsystem_mali200_get_new_job_from_user(struct mali_core_session * session, void * argument);
+static void subsystem_mali200_return_job_to_user( mali_core_job * job, mali_subsystem_job_end_code end_status);
+static void subsystem_mali200_renderunit_delete(mali_core_renderunit * core);
+static void subsystem_mali200_renderunit_reset_core(struct mali_core_renderunit * core, mali_core_reset_style style);
+static void subsystem_mali200_renderunit_probe_core_irq_trigger(struct mali_core_renderunit* core);
+static _mali_osk_errcode_t subsystem_mali200_renderunit_probe_core_irq_finished(struct mali_core_renderunit* core);
+
+static void subsystem_mali200_renderunit_stop_bus(struct mali_core_renderunit* core);
+static u32 subsystem_mali200_irq_handler_upper_half(struct mali_core_renderunit * core);
+static int subsystem_mali200_irq_handler_bottom_half(struct mali_core_renderunit* core);
+
+/* This will be one of the subsystems in the array of subsystems:
+	static struct mali_kernel_subsystem * subsystems[];
+  found in file: mali_kernel_core.c
+*/
+
+struct mali_kernel_subsystem mali_subsystem_mali200=
+{
+	mali200_subsystem_startup,                  /* startup */
+	NULL, /*mali200_subsystem_terminate,*/                /* shutdown */
+#if USING_MMU
+	mali200_subsystem_mmu_connect,              /* load_complete */
+#else
+    NULL,
+#endif
+	mali200_subsystem_core_system_info_fill,    /* system_info_fill */
+    mali200_subsystem_session_begin,            /* session_begin */
+	mali200_subsystem_session_end,              /* session_end */
+#if USING_MMU
+	mali200_subsystem_broadcast_notification,   /* broadcast_notification */
+#else
+    NULL,
+#endif
+#if MALI_STATE_TRACKING
+	mali200_subsystem_dump_state,               /* dump_state */
+#endif
+} ;
+
+static mali_core_subsystem subsystem_mali200 ;
+
+static _mali_osk_errcode_t mali200_subsystem_startup(mali_kernel_subsystem_identifier id)
+{
+	mali_core_subsystem * subsystem;
+
+	MALI_DEBUG_PRINT(3, ("Mali PP: mali200_subsystem_startup\n") ) ;
+
+    mali_subsystem_mali200_id = id;
+
+	/* All values get 0 as default */
+	_mali_osk_memset(&subsystem_mali200, 0, sizeof(subsystem_mali200));
+
+	subsystem = &subsystem_mali200;
+	subsystem->start_job = &subsystem_mali200_start_job;
+	subsystem->irq_handler_upper_half = &subsystem_mali200_irq_handler_upper_half;
+	subsystem->irq_handler_bottom_half = &subsystem_mali200_irq_handler_bottom_half;
+	subsystem->get_new_job_from_user = &subsystem_mali200_get_new_job_from_user;
+	subsystem->return_job_to_user = &subsystem_mali200_return_job_to_user;
+	subsystem->renderunit_delete = &subsystem_mali200_renderunit_delete;
+	subsystem->reset_core = &subsystem_mali200_renderunit_reset_core;
+	subsystem->stop_bus = &subsystem_mali200_renderunit_stop_bus;
+	subsystem->probe_core_irq_trigger = &subsystem_mali200_renderunit_probe_core_irq_trigger;
+	subsystem->probe_core_irq_acknowledge = &subsystem_mali200_renderunit_probe_core_irq_finished;
+
+	/* Setting variables in the general core part of the subsystem.*/
+	subsystem->name = MALI_PP_SUBSYSTEM_NAME;
+	subsystem->core_type = MALI_PP_CORE_TYPE;
+	subsystem->id = id;
+
+	/* Initiates the rest of the general core part of the subsystem */
+    MALI_CHECK_NO_ERROR(mali_core_subsystem_init( subsystem ));
+
+	/* This will register the function for adding MALI200 cores to the subsystem */
+#if defined(USING_MALI200)
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MALI200, mali200_renderunit_create));
+#endif
+#if defined(USING_MALI400)
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MALI400PP, mali200_renderunit_create));
+#endif
+
+	MALI_DEBUG_PRINT(6, ("Mali PP: mali200_subsystem_startup\n") ) ;
+
+	MALI_SUCCESS;
+}
+
+#if USING_MMU
+static _mali_osk_errcode_t mali200_subsystem_mmu_connect(mali_kernel_subsystem_identifier id)
+{
+	mali_core_subsystem_attach_mmu(&subsystem_mali200);
+    MALI_SUCCESS; /* OK */
+}
+#endif
+
+static void mali200_subsystem_terminate(mali_kernel_subsystem_identifier id)
+{
+	MALI_DEBUG_PRINT(3, ("Mali PP: mali200_subsystem_terminate\n") ) ;
+	mali_core_subsystem_cleanup(&subsystem_mali200);
+}
+
+static _mali_osk_errcode_t mali200_subsystem_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue)
+{
+	mali_core_session * session;
+
+	MALI_DEBUG_PRINT(3, ("Mali PP: mali200_subsystem_session_begin\n") ) ;
+    MALI_CHECK_NON_NULL(session = _mali_osk_malloc( sizeof(mali_core_session) ), _MALI_OSK_ERR_NOMEM);
+
+	_mali_osk_memset(session, 0, sizeof(*session) );
+	*slot = (mali_kernel_subsystem_session_slot)session;
+
+	session->subsystem = &subsystem_mali200;
+
+	session->notification_queue = queue;
+
+#if USING_MMU
+	session->mmu_session = mali_session_data;
+#endif
+
+	mali_core_session_begin(session);
+
+	MALI_DEBUG_PRINT(6, ("Mali PP: mali200_subsystem_session_begin\n") ) ;
+
+	MALI_SUCCESS;
+}
+
+static void mali200_subsystem_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot)
+{
+	mali_core_session * session;
+
+	MALI_DEBUG_PRINT(3, ("Mali PP: mali200_subsystem_session_end\n") ) ;
+	if ( NULL==slot || NULL==*slot)
+	{
+		MALI_PRINT_ERROR(("Input slot==NULL"));
+		return;
+	}
+	session = (mali_core_session*) *slot;
+	mali_core_session_close(session);
+
+	_mali_osk_free(session);
+	*slot = NULL;
+
+	MALI_DEBUG_PRINT(6, ("Mali PP: mali200_subsystem_session_end\n") ) ;
+}
+
+/**
+ * We fill in info about all the cores we have
+ * @param info Pointer to system info struct to update
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali200_subsystem_core_system_info_fill(_mali_system_info* info)
+{
+	return mali_core_subsystem_system_info_fill(&subsystem_mali200, info);
+}
+
+
+static _mali_osk_errcode_t mali200_renderunit_create(_mali_osk_resource_t * resource)
+{
+	mali_core_renderunit *core;
+	_mali_osk_errcode_t err;
+
+	MALI_DEBUG_PRINT(3, ("Mali PP: mali200_renderunit_create\n") ) ;
+	/* Checking that the resource settings are correct */
+#if defined(USING_MALI200)
+	if(MALI200 != resource->type)
+	{
+		MALI_PRINT_ERROR(("Can not register this resource as a " MALI_PP_SUBSYSTEM_NAME " core."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#elif defined(USING_MALI400)
+	if(MALI400PP != resource->type)
+	{
+		MALI_PRINT_ERROR(("Can not register this resource as a " MALI_PP_SUBSYSTEM_NAME " core."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#endif
+	if ( 0 != resource->size )
+	{
+		MALI_PRINT_ERROR(("Memory size set to " MALI_PP_SUBSYSTEM_NAME " core should be zero."));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	if ( NULL == resource->description )
+	{
+		MALI_PRINT_ERROR(("A " MALI_PP_SUBSYSTEM_NAME " core needs a unique description field"));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Create a new core object */
+	core = (mali_core_renderunit*) _mali_osk_malloc(sizeof(*core));
+	if ( NULL == core )
+	{
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	/* Variables set to be able to open and register the core */
+	core->subsystem = &subsystem_mali200 ;
+	core->registers_base_addr 	= resource->base ;
+	core->size 					= MALI200_REG_SIZEOF_REGISTER_BANK ;
+	core->irq_nr 				= resource->irq ;
+	core->description 			= resource->description;
+#if USING_MMU
+	core->mmu_id                = resource->mmu_id;
+	core->mmu                   = NULL;
+#endif
+#if USING_MALI_PMM
+	/* Set up core's PMM id */
+	switch( subsystem_mali200.number_of_cores )
+	{
+	case 0:
+		core->pmm_id = MALI_PMM_CORE_PP0;
+		break;
+	case 1:
+		core->pmm_id = MALI_PMM_CORE_PP1;
+		break;
+	case 2:
+		core->pmm_id = MALI_PMM_CORE_PP2;
+		break;
+	case 3:
+		core->pmm_id = MALI_PMM_CORE_PP3;
+		break;
+	default:
+		MALI_DEBUG_PRINT(1, ("Unknown supported core for PMM\n"));
+		err = _MALI_OSK_ERR_FAULT;
+		goto exit_on_error0;
+	}
+#endif
+
+	err = mali_core_renderunit_init( core );
+    if (_MALI_OSK_ERR_OK != err)
+    {
+		MALI_DEBUG_PRINT(1, ("Failed to initialize renderunit\n"));
+		goto exit_on_error0;
+    }
+
+	/* Map the new core object, setting: core->registers_mapped  */
+	err = mali_core_renderunit_map_registers(core);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to map register\n"));
+		goto exit_on_error1;
+	}
+
+	/* Check that the register mapping of the core works.
+	Return 0 if Mali PP core is present and accessible. */
+	if (mali_benchmark) {
+#if defined(USING_MALI200)
+		core->core_version = (((u32)MALI_PP_PRODUCT_ID) << 16) | 5 /* Fake Mali200-r0p5 */;
+#elif defined(USING_MALI400)
+		core->core_version = (((u32)MALI_PP_PRODUCT_ID) << 16) | 0x0101 /* Fake Mali400-r1p1 */;
+#else
+#error "No supported mali core defined"
+#endif
+	} else {
+		core->core_version = mali_core_renderunit_register_read(
+		                     core,
+		                     MALI200_REG_ADDR_MGMT_VERSION);
+	}
+
+	err = mali200_core_version_legal(core);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		MALI_DEBUG_PRINT(1, ("Invalid core\n"));
+		goto exit_on_error2;
+	}
+
+	/* Reset the core. Put the core into a state where it can start to render. */
+	mali200_reset(core);
+
+	/* Registering IRQ, init the work_queue_irq_handle */
+	/* Adding this core as an available renderunit in the subsystem. */
+	err = mali_core_subsystem_register_renderunit(&subsystem_mali200, core);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to register with core\n"));
+		goto exit_on_error2;
+	}
+	MALI_DEBUG_PRINT(6, ("Mali PP: mali200_renderunit_create\n") ) ;
+
+	MALI_SUCCESS;
+
+exit_on_error2:
+	mali_core_renderunit_unmap_registers(core);
+exit_on_error1:
+    mali_core_renderunit_term(core);
+exit_on_error0:
+	_mali_osk_free( core ) ;
+	MALI_PRINT_ERROR(("Renderunit NOT created."));
+    MALI_ERROR(err);
+}
+
+#if USING_MMU
+/* Used currently only for signalling when MMU has a pagefault */
+static void mali200_subsystem_broadcast_notification(mali_core_notification_message message, u32 data)
+{
+	mali_core_subsystem_broadcast_notification(&subsystem_mali200, message, data);
+}
+#endif
+
+static _mali_osk_errcode_t mali200_core_version_legal( mali_core_renderunit *core )
+{
+	u32 mali_type;
+
+	mali_type = core->core_version >> 16;
+#if defined(USING_MALI400)
+	/* Mali300 and Mali400 is compatible, accept either core. */
+	if (MALI400_PP_PRODUCT_ID != mali_type && MALI300_PP_PRODUCT_ID != mali_type)
+#else
+	if (MALI_PP_PRODUCT_ID != mali_type)
+#endif
+	{
+		MALI_PRINT_ERROR(("Error: reading this from " MALI_PP_SUBSYSTEM_NAME " version register: 0x%x\n", core->core_version));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+	MALI_DEBUG_PRINT(3, ("Mali PP: core_version_legal: Reads correct mali version: %d\n", mali_type) ) ;
+	MALI_SUCCESS;
+}
+
+static void subsystem_mali200_renderunit_stop_bus(struct mali_core_renderunit* core)
+{
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_STOP_BUS);
+}
+
+static void mali200_raw_reset( mali_core_renderunit *core )
+{
+	int i;
+	const int request_loop_count = 20;
+
+	MALI_DEBUG_PRINT(4, ("Mali PP: mali200_raw_reset: %s\n", core->description));
+	if (mali_benchmark) return;
+
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, 0); /* disable IRQs */
+
+#if defined(USING_MALI200)
+
+    mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_STOP_BUS);
+
+	for (i = 0; i < request_loop_count; i++)
+	{
+		if (mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_STATUS) & MALI200_REG_VAL_STATUS_BUS_STOPPED) break;
+		_mali_osk_time_ubusydelay(10);
+	}
+
+	MALI_DEBUG_PRINT_IF(1, request_loop_count == i, ("Mali PP: Bus was never stopped during core reset\n"));
+
+
+	if (request_loop_count==i)
+	{
+#if USING_MMU
+		if ((NULL!=core->mmu) && (MALI_FALSE == core->error_recovery))
+		{
+			/* Could not stop bus connections from core, probably because some of the already pending
+			   bus request has had a page fault, and therefore can not complete before the MMU does PageFault
+			   handling. This can be treated as a heavier reset function - which unfortunately reset all
+			   the cores on this MMU in addition to the MMU itself */
+			MALI_DEBUG_PRINT(1, ("Mali PP: Forcing Bus reset\n"));
+			mali_kernel_mmu_force_bus_reset(core->mmu);
+			return;
+		}
+#endif
+		MALI_PRINT(("A MMU reset did not allow PP  to stop its bus, system failure, unable to recover\n"));
+		return;
+	}
+
+	/* use the hard reset routine to do the actual reset */
+	mali200_reset_hard(core);
+
+#elif defined(USING_MALI400)
+
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI400PP_REG_VAL_IRQ_RESET_COMPLETED);
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET);
+
+	for (i = 0; i < request_loop_count; i++)
+	{
+		if (mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & MALI400PP_REG_VAL_IRQ_RESET_COMPLETED) break;
+		_mali_osk_time_ubusydelay(10);
+	}
+
+	if (request_loop_count==i)
+	{
+#if USING_MMU
+		if ((NULL!=core->mmu) && (MALI_FALSE == core->error_recovery))
+		{
+			/* Could not stop bus connections from core, probably because some of the already pending
+			   bus request has had a page fault, and therefore can not complete before the MMU does PageFault
+			   handling. This can be treated as a heavier reset function - which unfortunately reset all
+			   the cores on this MMU in addition to the MMU itself */
+			MALI_DEBUG_PRINT(1, ("Mali PP: Forcing Bus reset\n"));
+			mali_kernel_mmu_force_bus_reset(core->mmu);
+			return;
+		}
+#endif
+		MALI_PRINT(("A MMU reset did not allow PP  to stop its bus, system failure, unable to recover\n"));
+		return;
+	}
+	else
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_MASK_ALL);
+
+#else
+#error "no supported mali core defined"
+#endif
+}
+
+static void mali200_reset( mali_core_renderunit *core )
+{
+	if (!mali_benchmark) {
+		mali200_raw_reset(core);
+		mali200_initialize_registers_mgmt(core);
+	}
+}
+
+/* Sets the registers on mali200 according to the const default_mgmt_regs array. */
+static void mali200_initialize_registers_mgmt(mali_core_renderunit *core )
+{
+	MALI_DEBUG_PRINT(6, ("Mali PP: mali200_initialize_registers_mgmt: %s\n", core->description)) ;
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED);
+}
+
+/* Start this job on this core. Return MALI_TRUE if the job was started. */
+static _mali_osk_errcode_t subsystem_mali200_start_job(mali_core_job * job, mali_core_renderunit * core)
+{
+	mali200_job 	*job200;
+
+	/* The local extended version of the general structs */
+	job200  = _MALI_OSK_CONTAINER_OF(job, mali200_job, embedded_core_job);
+
+	if ( (0 == job200->user_input.frame_registers[0]) ||
+	     (0 == job200->user_input.frame_registers[1]) )
+	{
+		MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x  WILL NOT START SINCE JOB HAS ILLEGAL ADDRESSES\n",
+				(u32)job200->user_input.user_job_ptr));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x  START_RENDER  Tile_list: 0x%08x\n",
+			(u32)job200->user_input.user_job_ptr,
+			job200->user_input.frame_registers[0]));
+	MALI_DEBUG_PRINT(6, ("Mali PP:      RSW base addr: 0x%08x  Vertex base addr: 0x%08x\n",
+			job200->user_input.frame_registers[1], job200->user_input.frame_registers[2]));
+
+	/* Frame registers. Copy from mem to physical registers */
+	mali_core_renderunit_register_write_array(
+			core,
+			MALI200_REG_ADDR_FRAME,
+			&(job200->user_input.frame_registers[0]),
+			MALI200_NUM_REGS_FRAME);
+
+	/* Write Back unit 0. Copy from mem to physical registers only if the WB unit will be used. */
+	if (job200->user_input.wb0_registers[0])
+	{
+		mali_core_renderunit_register_write_array(
+				core,
+				MALI200_REG_ADDR_WB0,
+				&(job200->user_input.wb0_registers[0]),
+				MALI200_NUM_REGS_WBx);
+	}
+
+	/* Write Back unit 1. Copy from mem to physical registers only if the WB unit will be used. */
+	if (job200->user_input.wb1_registers[0])
+	{
+		mali_core_renderunit_register_write_array(
+				core,
+				MALI200_REG_ADDR_WB1,
+				&(job200->user_input.wb1_registers[0]),
+				MALI200_NUM_REGS_WBx);
+	}
+
+	/* Write Back unit 2. Copy from mem to physical registers only if the WB unit will be used. */
+	if (job200->user_input.wb2_registers[0])
+	{
+		mali_core_renderunit_register_write_array(
+				core,
+				MALI200_REG_ADDR_WB2,
+				&(job200->user_input.wb2_registers[0]),
+				MALI200_NUM_REGS_WBx);
+	}
+
+#if MALI_TRACEPOINTS_ENABLED
+	{
+		int counter = ((core->core_number)*2)+9; /* magic numbers for FP0 are 9 & 10 */
+
+		//printk("FP core->number = %d\n", core->core_number);
+		//TODO we are using magic numbers again... these are from gator_events_mali.c
+		job200->user_input.perf_counter_flag = 0;
+
+		if( counter>=9 && counter<=16) {
+
+			if( counter_table[counter] != 0xFFFFFFFF ) {
+				job200->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE;
+				job200->user_input.perf_counter_src0 = counter_table[counter];
+			}
+			if( counter_table[counter+1] != 0xFFFFFFFF ) {
+				job200->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE;
+				job200->user_input.perf_counter_src1 = counter_table[counter+1];
+			}
+
+		} else {
+			MALI_DEBUG_PRINT(2, ("core->core_number out of the range (0-3) (%d)\n", core->core_number));
+		}
+	}
+#if defined(USING_MALI400_L2_CACHE)
+	if( counter_table[5] != 0xFFFFFFFF ) {
+		job200->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE | _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET;
+		job200->user_input.perf_counter_l2_src0 = counter_table[5];
+	}
+	if( counter_table[6] != 0xFFFFFFFF ) {
+		job200->user_input.perf_counter_flag |= _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE | _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET;
+		job200->user_input.perf_counter_l2_src1 = counter_table[6];
+	}
+#endif
+#endif
+
+	/* This selects which performance counters we are reading */
+	if ( 0 != job200->user_input.perf_counter_flag )
+	{
+		if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
+		{
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE,
+					MALI200_REG_VAL_PERF_CNT_ENABLE);
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC,
+					job200->user_input.perf_counter_src0);
+
+		}
+
+		if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
+		{
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE,
+					MALI200_REG_VAL_PERF_CNT_ENABLE);
+			mali_core_renderunit_register_write_relaxed(
+					core,
+					MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC,
+					job200->user_input.perf_counter_src1);
+
+		}
+
+#if defined(USING_MALI400_L2_CACHE)
+		if ( job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
+		{
+			int force_reset = ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET ) ? 1 : 0;
+			u32 src0 = 0;
+			u32 src1 = 0;
+
+			if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE )
+			{
+				src0 = job200->user_input.perf_counter_l2_src0;
+			}
+			if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE )
+			{
+				src1 = job200->user_input.perf_counter_l2_src1;
+			}
+
+			mali_kernel_l2_cache_set_perf_counters(src0, src1, force_reset); /* will activate and possibly reset counters */
+
+			/* Now, retrieve the current values, so we can substract them when the job has completed */
+			mali_kernel_l2_cache_get_perf_counters(&job200->perf_counter_l2_src0,
+			                                       &job200->perf_counter_l2_val0,
+			                                       &job200->perf_counter_l2_src1,
+			                                       &job200->perf_counter_l2_val1);
+		}
+#endif
+	}
+
+	subsystem_flush_mapped_mem_cache();
+
+#if MALI_STATE_TRACKING
+	_mali_osk_atomic_inc(&job->session->jobs_started);
+#endif
+
+	/* This is the command that starts the Core */
+	mali_core_renderunit_register_write(
+			core,
+			MALI200_REG_ADDR_MGMT_CTRL_MGMT,
+			MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
+	_mali_osk_write_mem_barrier();
+
+
+	pr_debug("SPI_GPU_PP%u Start\n", core->core_number);
+#if MALI_TIMELINE_PROFILING_ENABLED
+	_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, job200->user_input.frame_builder_id, job200->user_input.flush_id, 0, 0, 0); 
+	_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), job200->pid, job200->tid,
+#if defined(USING_MALI400_L2_CACHE)
+				(job200->user_input.perf_counter_l2_src0 << 16) | (job200->user_input.perf_counter_l2_src1 << 24),
+				job200->perf_counter_l2_val0, job200->perf_counter_l2_val1
+#else
+				0, 0, 0
+#endif
+				);
+#endif
+
+    MALI_SUCCESS;
+}
+
+static u32 subsystem_mali200_irq_handler_upper_half(mali_core_renderunit * core)
+{
+	u32 irq_readout;
+
+	if (mali_benchmark) {
+		return (core->current_job ? 1 : 0); /* simulate irq is pending when a job is pending */
+	}
+
+	MALI_DEBUG_PRINT(5, ("Mali PP: subsystem_mali200_irq_handler_upper_half: %s\n", core->description)) ;
+	irq_readout = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_INT_STATUS);
+
+	if ( MALI200_REG_VAL_IRQ_MASK_NONE != irq_readout )
+	{
+		/* Mask out all IRQs from this core until IRQ is handled */
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_NONE);
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number)|MALI_PROFILING_EVENT_REASON_SINGLE_HW_INTERRUPT, irq_readout, 0, 0, 0, 0);
+#endif
+
+		return 1;
+	}
+	return 0;
+}
+
+static int subsystem_mali200_irq_handler_bottom_half(struct mali_core_renderunit* core)
+{
+	u32 irq_readout;
+	u32 current_tile_addr;
+	u32 core_status;
+	mali_core_job * job;
+	mali200_job * job200;
+
+	job = core->current_job;
+	job200 = GET_JOB200_PTR(job);
+
+
+	if (mali_benchmark) {
+		irq_readout = MALI200_REG_VAL_IRQ_END_OF_FRAME;
+		current_tile_addr = 0;
+		core_status = 0;
+	} else {
+		irq_readout = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & MALI200_REG_VAL_IRQ_MASK_USED;
+		current_tile_addr = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR);
+		core_status = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_STATUS);
+	}
+
+	if (NULL == job)
+	{
+		MALI_DEBUG_ASSERT(CORE_IDLE==core->state);
+		if ( 0 != irq_readout )
+		{
+			MALI_PRINT_ERROR(("Interrupt from a core not running a job. IRQ: 0x%04x Status: 0x%04x", irq_readout, core_status));
+		}
+		return JOB_STATUS_END_UNKNOWN_ERR;
+	}
+	MALI_DEBUG_ASSERT(CORE_IDLE!=core->state);
+
+	job200->irq_status |= irq_readout;
+
+	MALI_DEBUG_PRINT_IF( 3, ( 0 != irq_readout ),
+	            ("Mali PP: Job: 0x%08x  IRQ RECEIVED  Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x\n",
+	            (u32)job200->user_input.user_job_ptr, irq_readout ,current_tile_addr ,core_status));
+
+	if ( MALI200_REG_VAL_IRQ_END_OF_FRAME & irq_readout)
+	{
+#if defined(USING_MALI200)
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES);
+#endif
+
+		if (0 != job200->user_input.perf_counter_flag )
+		{
+			if (job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE) )
+			{
+#if MALI_TRACEPOINTS_ENABLED
+				//TODO magic numbers should come from mali_linux_trace.h instead
+				unsigned int counter = (core->core_number * 2) + 9;
+#endif
+
+				job200->perf_counter0 = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
+				job200->perf_counter1 = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
+
+#if MALI_TRACEPOINTS_ENABLED
+				_mali_profiling_add_counter(counter, job200->perf_counter0);
+				_mali_profiling_add_counter(counter + 1, job200->perf_counter1);
+#endif
+
+			}
+
+#if defined(USING_MALI400_L2_CACHE)
+			if (job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
+			{
+				u32 src0;
+				u32 val0;
+				u32 src1;
+				u32 val1;
+				mali_kernel_l2_cache_get_perf_counters(&src0, &val0, &src1, &val1);
+
+				if (job200->perf_counter_l2_src0 == src0)
+				{
+					job200->perf_counter_l2_val0_raw = val0;
+					job200->perf_counter_l2_val0 = val0 - job200->perf_counter_l2_val0;
+				}
+				else
+				{
+					job200->perf_counter_l2_val0_raw = 0;
+					job200->perf_counter_l2_val0 = 0;
+				}
+
+				if (job200->perf_counter_l2_src1 == src1)
+				{
+					job200->perf_counter_l2_val1_raw = val1;
+					job200->perf_counter_l2_val1 = val1 - job200->perf_counter_l2_val1;
+				}
+				else
+				{
+					job200->perf_counter_l2_val1_raw = 0;
+					job200->perf_counter_l2_val1 = 0;
+				}
+
+#if MALI_TRACEPOINTS_ENABLED
+				//TODO magic numbers should come from mali_linux_trace.h instead
+				_mali_profiling_add_counter(5, val0);
+				_mali_profiling_add_counter(6, val1);
+#endif
+			}
+#endif
+
+		}
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number),
+				job200->perf_counter0, job200->perf_counter1,
+				job200->user_input.perf_counter_src0 | (job200->user_input.perf_counter_src1 << 8)
+#if defined(USING_MALI400_L2_CACHE)
+				| (job200->user_input.perf_counter_l2_src0 << 16) | (job200->user_input.perf_counter_l2_src1 << 24),
+				job200->perf_counter_l2_val0, job200->perf_counter_l2_val1
+#else
+				, 0, 0
+#endif
+				);
+#endif
+
+
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		
+		pr_debug("SPI_GPU_PP%u Idle\n", core->core_number);
+             
+		return JOB_STATUS_END_SUCCESS; /* reschedule */
+	}
+	/* Overall SW watchdog timeout or (time to do hang checking and progress detected)? */
+	else if (
+	         (CORE_WATCHDOG_TIMEOUT == core->state) ||
+	         ((CORE_HANG_CHECK_TIMEOUT == core->state) && (current_tile_addr == job200->last_tile_list_addr))
+	        )
+	{
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status */
+#endif
+		/* no progress detected, killed by the watchdog */
+		MALI_PRINT( ("M200: SW-Timeout Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x.\n", irq_readout ,current_tile_addr ,core_status) );
+		/* In this case will the system outside cleanup and reset the core */
+
+		MALI_PANIC("%s Watchdog timeout (rawstat: 0x%x tile_addr: 0x%x status: 0x%x)\n", MALI_PP_SUBSYSTEM_NAME, irq_readout, current_tile_addr, core_status);
+
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+
+		return JOB_STATUS_END_HANG;
+   	}
+	/* HW watchdog triggered or an existing hang check passed? */
+	else if	((CORE_HANG_CHECK_TIMEOUT == core->state) || (irq_readout & job200->active_mask & MALI200_REG_VAL_IRQ_HANG))
+	{
+		/* check interval in ms */
+		u32 timeout = mali_core_hang_check_timeout_get();
+		MALI_PRINT( ("M200: HW/SW Watchdog triggered, checking for progress in %d ms\n", timeout));
+		job200->last_tile_list_addr = current_tile_addr;
+		/* hw watchdog triggered, set up a progress checker every HANGCHECK ms */
+		_mali_osk_timer_add(core->timer_hang_detection, _mali_osk_time_mstoticks(timeout));
+		job200->active_mask &= ~MALI200_REG_VAL_IRQ_HANG; /* ignore the hw watchdoig from now on */
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, irq_readout & ~MALI200_REG_VAL_IRQ_HANG);
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, job200->active_mask);
+		return JOB_STATUS_CONTINUE_RUN; /* not finished */
+	}
+	/* No irq pending, core still busy */
+	else if ((0 == (irq_readout & MALI200_REG_VAL_IRQ_MASK_USED)) && ( 0 != (core_status & MALI200_REG_VAL_STATUS_RENDERING_ACTIVE)))
+	{
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, irq_readout);
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, job200->active_mask);
+		return JOB_STATUS_CONTINUE_RUN; /* Not finished */
+	}
+	else
+	{
+#if MALI_TIMELINE_PROFILING_ENABLED
+		_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), 0, 0, 0, 0, 0); /* add GP and L2 counters and return status */
+#endif
+
+		MALI_PRINT( ("Mali PP: Job: 0x%08x  CRASH?  Rawstat: 0x%x Tile_addr: 0x%x Status: 0x%x\n",
+				(u32)job200->user_input.user_job_ptr, irq_readout ,current_tile_addr ,core_status) ) ;
+
+		if (irq_readout & MALI200_REG_VAL_IRQ_BUS_ERROR)
+		{
+			u32 bus_error = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS);
+
+			MALI_PRINT(("Bus error status: 0x%08X\n", bus_error));
+			MALI_DEBUG_PRINT_IF(1, (bus_error & 0x01), ("Bus write error from id 0x%02x\n", (bus_error>>2) & 0x0F));
+			MALI_DEBUG_PRINT_IF(1, (bus_error & 0x02), ("Bus read error from id 0x%02x\n", (bus_error>>6) & 0x0F));
+			MALI_DEBUG_PRINT_IF(1, (0 == (bus_error & 0x03)), ("Bus error but neither read or write was set as the error reason\n"));
+			(void)bus_error;
+		}
+
+#if MALI_STATE_TRACKING
+		_mali_osk_atomic_inc(&job->session->jobs_ended);
+#endif
+		return JOB_STATUS_END_UNKNOWN_ERR; /* reschedule */
+	}
+}
+
+
+/* This function is called from the ioctl function and should return a mali_core_job pointer
+to a created mali_core_job object with the data given from userspace */
+static _mali_osk_errcode_t subsystem_mali200_get_new_job_from_user(struct mali_core_session * session, void * argument)
+{
+	mali200_job *job200;
+	mali_core_job *job = NULL;
+	mali_core_job *previous_replaced_job;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+	_mali_uk_pp_start_job_s * user_ptr_job_input;
+
+    user_ptr_job_input = (_mali_uk_pp_start_job_s *)argument;
+
+    MALI_CHECK_NON_NULL(job200 = (mali200_job *) _mali_osk_malloc(sizeof(mali200_job)), _MALI_OSK_ERR_NOMEM);
+	_mali_osk_memset(job200, 0 , sizeof(mali200_job) );
+
+	/* We read job data from Userspace pointer */
+    if ( NULL == _mali_osk_memcpy((void*)&job200->user_input, user_ptr_job_input, sizeof(job200->user_input)) )
+	{
+		MALI_PRINT_ERROR( ("Mali PP: Could not copy data from U/K interface.\n")) ;
+        err = _MALI_OSK_ERR_FAULT;
+		goto function_exit;
+	}
+
+	MALI_DEBUG_PRINT(5, ("Mali PP: subsystem_mali200_get_new_job_from_user 0x%x\n", (void*)job200->user_input.user_job_ptr));
+
+	MALI_DEBUG_PRINT(5, ("Mali PP: Frameregs: 0x%x 0x%x 0x%x Writeback[1] 0x%x, Pri:%d; Watchd:%d\n",
+			job200->user_input.frame_registers[0], job200->user_input.frame_registers[1], job200->user_input.frame_registers[2],
+			job200->user_input.wb0_registers[1], job200->user_input.priority,
+			job200->user_input.watchdog_msecs));
+
+	if ( job200->user_input.perf_counter_flag)
+	{
+#if defined(USING_MALI400_L2_CACHE)
+		MALI_DEBUG_PRINT(5, ("Mali PP: Performance counters: flag:0x%x src0:0x%x src1:0x%x l2_src0:0x%x l2_src1:0x%x\n",
+				job200->user_input.perf_counter_flag,
+				job200->user_input.perf_counter_src0,
+				job200->user_input.perf_counter_src1,
+				job200->user_input.perf_counter_l2_src0,
+				job200->user_input.perf_counter_l2_src1));
+#else
+		MALI_DEBUG_PRINT(5, ("Mali PP: Performance counters: flag:0x%x src0:0x%x src1:0x%x\n",
+				job200->user_input.perf_counter_flag,
+				job200->user_input.perf_counter_src0,
+				job200->user_input.perf_counter_src1));
+#endif
+	}
+
+	job = GET_JOB_EMBEDDED_PTR(job200);
+
+	job->session = session;
+	job->flags = user_ptr_job_input->flags;
+	job_priority_set(job, job200->user_input.priority);
+	job_watchdog_set(job, job200->user_input.watchdog_msecs );
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	job200->pid = _mali_osk_get_pid();
+	job200->tid = _mali_osk_get_tid();
+#endif
+
+	job->abort_id = job200->user_input.abort_id;
+	if (mali_job_queue_full(session))
+	{
+		user_ptr_job_input->status = _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE;
+		goto function_exit;
+	}
+
+	/* We now know that we has a job, and a empty session slot to put it in */
+
+	job200->active_mask = MALI200_REG_VAL_IRQ_MASK_USED;
+
+	/* Allocating User Return Data */
+	job200->notification_obj = _mali_osk_notification_create(
+			_MALI_NOTIFICATION_PP_FINISHED,
+			sizeof(_mali_uk_pp_job_finished_s) );
+
+	if ( NULL == job200->notification_obj )
+	{
+		MALI_PRINT_ERROR( ("Mali PP: Could not get notification_obj.\n")) ;
+		err = _MALI_OSK_ERR_NOMEM;
+		goto function_exit;
+	}
+
+	_MALI_OSK_INIT_LIST_HEAD( &(job->list) ) ;
+
+	MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x INPUT from user.\n", (u32)job200->user_input.user_job_ptr)) ;
+
+	/* This should not happen since we have the checking of priority above */
+	if ( _MALI_OSK_ERR_OK != mali_core_session_add_job(session, job, &previous_replaced_job))
+	{
+		MALI_PRINT_ERROR( ("Mali PP: Internal error\n")) ;
+		user_ptr_job_input->status = _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE;
+		_mali_osk_notification_delete( job200->notification_obj );
+		goto function_exit;
+	}
+
+	/* If MALI_TRUE: This session had a job with lower priority which were removed.
+	This replaced job is given back to userspace. */
+	if ( NULL != previous_replaced_job )
+	{
+		mali200_job *previous_replaced_job200;
+
+		previous_replaced_job200 = GET_JOB200_PTR(previous_replaced_job);
+
+		MALI_DEBUG_PRINT(4, ("Mali PP: Replacing job: 0x%08x\n", (u32)previous_replaced_job200->user_input.user_job_ptr)) ;
+
+		/* Copy to the input data (which also is output data) the
+		pointer to the job that were replaced, so that the userspace
+		driver can put this job in the front of its job-queue */
+
+		user_ptr_job_input->returned_user_job_ptr = previous_replaced_job200->user_input.user_job_ptr;
+
+		/** @note failure to 'copy to user' at this point must not free job200,
+		 * and so no transaction rollback required in the U/K interface */
+
+		/* This does not cause job200 to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED;
+		MALI_DEBUG_PRINT(5, ("subsystem_mali200_get_new_job_from_user: Job added, prev returned\n")) ;
+	}
+	else
+	{
+		/* This does not cause job200 to free: */
+		user_ptr_job_input->status = _MALI_UK_START_JOB_STARTED;
+		MALI_DEBUG_PRINT(5, ("subsystem_mali200_get_new_job_from_user: Job added\n")) ;
+	}
+
+function_exit:
+	if (_MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE == user_ptr_job_input->status
+		|| _MALI_OSK_ERR_OK != err )
+	{
+		_mali_osk_free(job200);
+	}
+#if MALI_STATE_TRACKING
+	if (_MALI_UK_START_JOB_STARTED==user_ptr_job_input->status)
+	{
+		if(job)
+		{
+			job->job_nr=_mali_osk_atomic_inc_return(&session->jobs_received);
+		}
+	}
+#endif
+
+	MALI_ERROR(err);
+}
+
+/* This function is called from the ioctl function and should write the necessary data
+to userspace telling which job was finished and the status and debuginfo for this job.
+The function must also free and cleanup the input job object. */
+static void subsystem_mali200_return_job_to_user( mali_core_job * job, mali_subsystem_job_end_code end_status)
+{
+	mali200_job 	*job200;
+	_mali_uk_pp_job_finished_s * job_out;
+	_mali_uk_pp_start_job_s * job_input;
+	mali_core_session *session;
+
+	if (NULL == job)
+	{
+		MALI_DEBUG_PRINT(1, ("subsystem_mali200_return_job_to_user received a NULL ptr\n"));
+		return;
+	}
+
+	job200  = _MALI_OSK_CONTAINER_OF(job, mali200_job, embedded_core_job);
+
+	if (NULL == job200->notification_obj)
+	{
+		MALI_DEBUG_PRINT(1, ("Found job200 with NULL notification object, abandoning userspace sending\n"));
+		return;
+	}
+
+	job_out =  job200->notification_obj->result_buffer;
+	job_input= &(job200->user_input);
+	session = job->session;
+
+	MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x OUTPUT to user. Runtime: %dus\n",
+			(u32)job200->user_input.user_job_ptr,
+			job->render_time_usecs)) ;
+
+	_mali_osk_memset(job_out, 0 , sizeof(_mali_uk_pp_job_finished_s));
+
+	job_out->user_job_ptr = job_input->user_job_ptr;
+
+	switch( end_status )
+	{
+		case JOB_STATUS_CONTINUE_RUN:
+		case JOB_STATUS_END_SUCCESS:
+		case JOB_STATUS_END_OOM:
+		case JOB_STATUS_END_ABORT:
+		case JOB_STATUS_END_TIMEOUT_SW:
+		case JOB_STATUS_END_HANG:
+		case JOB_STATUS_END_SEG_FAULT:
+		case JOB_STATUS_END_ILLEGAL_JOB:
+		case JOB_STATUS_END_UNKNOWN_ERR:
+		case JOB_STATUS_END_SHUTDOWN:
+		case JOB_STATUS_END_SYSTEM_UNUSABLE:
+			job_out->status = (mali_subsystem_job_end_code) end_status;
+			break;
+
+		default:
+			job_out->status = JOB_STATUS_END_UNKNOWN_ERR ;
+	}
+	job_out->irq_status = job200->irq_status;
+	job_out->perf_counter0 = job200->perf_counter0;
+	job_out->perf_counter1 = job200->perf_counter1;
+	job_out->render_time = job->render_time_usecs;
+
+#if defined(USING_MALI400_L2_CACHE)
+	job_out->perf_counter_l2_src0 = job200->perf_counter_l2_src0;
+	job_out->perf_counter_l2_src1 = job200->perf_counter_l2_src1;
+	job_out->perf_counter_l2_val0 = job200->perf_counter_l2_val0;
+	job_out->perf_counter_l2_val1 = job200->perf_counter_l2_val1;
+	job_out->perf_counter_l2_val0_raw = job200->perf_counter_l2_val0_raw;
+	job_out->perf_counter_l2_val1_raw = job200->perf_counter_l2_val1_raw;
+#endif
+
+#if MALI_STATE_TRACKING
+	_mali_osk_atomic_inc(&session->jobs_returned);
+#endif
+	_mali_osk_notification_queue_send( session->notification_queue, job200->notification_obj);
+	job200->notification_obj = NULL;
+
+	_mali_osk_free(job200);
+}
+
+static void subsystem_mali200_renderunit_delete(mali_core_renderunit * core)
+{
+	MALI_DEBUG_PRINT(5, ("Mali PP: mali200_renderunit_delete\n"));
+	_mali_osk_free(core);
+}
+
+static void mali200_reset_hard(struct mali_core_renderunit * core)
+{
+	const int reset_finished_loop_count = 15;
+	const u32 reset_wait_target_register = MALI200_REG_ADDR_MGMT_WRITE_BOUNDARY_LOW;
+	const u32 reset_invalid_value = 0xC0FFE000;
+	const u32 reset_check_value = 0xC01A0000;
+	const u32 reset_default_value = 0;
+	int i;
+
+	MALI_DEBUG_PRINT(5, ("subsystem_mali200_renderunit_reset_core_hard called for core %s\n", core->description));
+
+	mali_core_renderunit_register_write(core, reset_wait_target_register, reset_invalid_value);
+
+	mali_core_renderunit_register_write(
+			core,
+			MALI200_REG_ADDR_MGMT_CTRL_MGMT,
+			MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET);
+
+	for (i = 0; i < reset_finished_loop_count; i++)
+	{
+		mali_core_renderunit_register_write(core, reset_wait_target_register, reset_check_value);
+		if (reset_check_value == mali_core_renderunit_register_read(core, reset_wait_target_register))
+		{
+			MALI_DEBUG_PRINT(5, ("Reset loop exiting after %d iterations\n", i));
+			break;
+		}
+		_mali_osk_time_ubusydelay(10);
+	}
+
+	if (i == reset_finished_loop_count)
+	{
+		MALI_DEBUG_PRINT(1, ("The reset loop didn't work\n"));
+	}
+
+	mali_core_renderunit_register_write(core, reset_wait_target_register, reset_default_value); /* set it back to the default */
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_MASK_ALL);
+}
+
+static void subsystem_mali200_renderunit_reset_core(struct mali_core_renderunit * core, mali_core_reset_style style)
+{
+	MALI_DEBUG_PRINT(5, ("Mali PP: renderunit_reset_core\n"));
+
+	switch (style)
+	{
+		case MALI_CORE_RESET_STYLE_RUNABLE:
+			mali200_reset(core);
+			break;
+		case MALI_CORE_RESET_STYLE_DISABLE:
+			mali200_raw_reset(core); /* do the raw reset */
+			mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, 0); /* then disable the IRQs */
+			break;
+		case MALI_CORE_RESET_STYLE_HARD:
+			mali200_reset_hard(core);
+			break;
+		default:
+			MALI_DEBUG_PRINT(1, ("Unknown reset type %d\n", style));
+	}
+}
+
+static void subsystem_mali200_renderunit_probe_core_irq_trigger(struct mali_core_renderunit* core)
+{
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED);
+	mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT, MALI200_REG_VAL_IRQ_FORCE_HANG);
+	_mali_osk_mem_barrier();
+}
+
+static _mali_osk_errcode_t subsystem_mali200_renderunit_probe_core_irq_finished(struct mali_core_renderunit* core)
+{
+	u32 irq_readout;
+
+	irq_readout = mali_core_renderunit_register_read(core, MALI200_REG_ADDR_MGMT_INT_STATUS);
+
+	if ( MALI200_REG_VAL_IRQ_FORCE_HANG & irq_readout )
+	{
+		mali_core_renderunit_register_write(core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_FORCE_HANG);
+		_mali_osk_mem_barrier();
+		MALI_SUCCESS;
+	}
+
+    MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+_mali_osk_errcode_t _mali_ukk_pp_start_job( _mali_uk_pp_start_job_s *args )
+{
+	mali_core_session * session;
+	MALI_DEBUG_ASSERT_POINTER(args);
+	MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+	session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_mali200_id);
+	MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+	return mali_core_subsystem_ioctl_start_job(session, args);
+}
+
+_mali_osk_errcode_t _mali_ukk_get_pp_number_of_cores( _mali_uk_get_pp_number_of_cores_s *args )
+{
+	mali_core_session * session;
+	MALI_DEBUG_ASSERT_POINTER(args);
+	MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+	session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_mali200_id);
+	MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+	return mali_core_subsystem_ioctl_number_of_cores_get(session, &args->number_of_cores);
+}
+
+_mali_osk_errcode_t _mali_ukk_get_pp_core_version( _mali_uk_get_pp_core_version_s *args )
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_mali200_id);
+    MALI_CHECK_NON_NULL(session, _MALI_OSK_ERR_FAULT);
+    return mali_core_subsystem_ioctl_core_version_get(session, &args->version);
+}
+
+void _mali_ukk_pp_abort_job( _mali_uk_pp_abort_job_s * args)
+{
+	mali_core_session * session;
+    MALI_DEBUG_ASSERT_POINTER(args);
+    if (NULL == args->ctx) return;
+    session = (mali_core_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_mali200_id);
+    if (NULL == session) return;
+    mali_core_subsystem_ioctl_abort_job(session, args->abort_id);
+
+}
+
+#if USING_MALI_PMM
+
+_mali_osk_errcode_t malipp_signal_power_up( u32 core_num, mali_bool queue_only )
+{
+	MALI_DEBUG_PRINT(4, ("Mali PP: signal power up core: %d - queue_only: %d\n", core_num, queue_only ));
+
+	return( mali_core_subsystem_signal_power_up( &subsystem_mali200, core_num, queue_only ) );
+}
+	
+_mali_osk_errcode_t malipp_signal_power_down( u32 core_num, mali_bool immediate_only )
+{
+	MALI_DEBUG_PRINT(4, ("Mali PP: signal power down core: %d - immediate_only: %d\n", core_num, immediate_only ));
+
+	return( mali_core_subsystem_signal_power_down( &subsystem_mali200, core_num, immediate_only ) );
+}
+
+#endif
+
+#if MALI_STATE_TRACKING
+u32 mali200_subsystem_dump_state(char *buf, u32 size)
+{
+	return mali_core_renderunit_dump_state(&subsystem_mali200, buf, size);
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_common.h b/drivers/media/video/samsung/mali/common/mali_kernel_common.h
new file mode 100644
index 0000000..ab6f143
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_common.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_COMMON_H__
+#define __MALI_KERNEL_COMMON_H__
+
+/* Make sure debug is defined when it should be */
+#ifndef DEBUG
+	#if defined(_DEBUG)
+		#define DEBUG
+	#endif
+#endif
+
+/* Macro for generating a kernel panic.
+ * Turned on off by compile-time Makefile settings
+ */
+#if defined(USING_KERNEL_PANIC)
+#include <linux/kernel.h>
+	#define MALI_PANIC(fmt, args...) panic( fmt, ## args );
+#else
+	#define MALI_PANIC(fmt, args...) 
+#endif
+
+
+/* The file include several useful macros for error checking, debugging and printing.
+ * - MALI_PRINTF(...)           Do not use this function: Will be included in Release builds.
+ * - MALI_DEBUG_PRINT(nr, (X) ) Prints the second argument if nr<=MALI_DEBUG_LEVEL.
+ * - MALI_DEBUG_ERROR( (X) )    Prints an errortext, a source trace, and the given error message.
+ * - MALI_DEBUG_ASSERT(exp,(X)) If the asserted expr is false, the program will exit.
+ * - MALI_DEBUG_ASSERT_POINTER(pointer)  Triggers if the pointer is a zero pointer.
+ * - MALI_DEBUG_CODE( X )       The code inside the macro is only compiled in Debug builds.
+ *
+ * The (X) means that you must add an extra parenthesis around the argumentlist.
+ *
+ * The  printf function: MALI_PRINTF(...) is routed to _mali_osk_debugmsg
+ *
+ * Suggested range for the DEBUG-LEVEL is [1:6] where
+ * [1:2] Is messages with highest priority, indicate possible errors.
+ * [3:4] Is messages with medium priority, output important variables.
+ * [5:6] Is messages with low priority, used during extensive debugging.
+ */
+
+ /**
+ *  Fundamental error macro. Reports an error code. This is abstracted to allow us to
+ *  easily switch to a different error reporting method if we want, and also to allow
+ *  us to search for error returns easily.
+ *
+ *  Note no closing semicolon - this is supplied in typical usage:
+ *
+ *  MALI_ERROR(MALI_ERROR_OUT_OF_MEMORY);
+ */
+#define MALI_ERROR(error_code) return (error_code)
+
+/**
+ *  Basic error macro, to indicate success.
+ *  Note no closing semicolon - this is supplied in typical usage:
+ *
+ *  MALI_SUCCESS;
+ */
+#define MALI_SUCCESS MALI_ERROR(_MALI_OSK_ERR_OK)
+
+/**
+ *	Basic error macro. This checks whether the given condition is true, and if not returns
+ *	from this function with the supplied error code. This is a macro so that we can override it
+ *	for stress testing.
+ *
+ *	Note that this uses the do-while-0 wrapping to ensure that we don't get problems with dangling
+ *	else clauses. Note also no closing semicolon - this is supplied in typical usage:
+ *
+ *	MALI_CHECK((p!=NULL), ERROR_NO_OBJECT);
+ */
+#define MALI_CHECK(condition, error_code) do { if(!(condition)) MALI_ERROR(error_code); } while(0)
+
+/**
+ *	Error propagation macro. If the expression given is anything other than _MALI_OSK_NO_ERROR,
+ *	then the value is returned from the enclosing function as an error code. This effectively
+ *	acts as a guard clause, and propagates error values up the call stack. This uses a
+ *	temporary value to ensure that the error expression is not evaluated twice.
+ *  If the counter for forcing a failure has been set using _mali_force_error, this error will be
+ *  returned without evaluating the expression in MALI_CHECK_NO_ERROR
+ */
+#define MALI_CHECK_NO_ERROR(expression) \
+    do { _mali_osk_errcode_t _check_no_error_result=(expression); \
+         if(_check_no_error_result != _MALI_OSK_ERR_OK) \
+         MALI_ERROR(_check_no_error_result); \
+    } while(0)
+
+/**
+ *  Pointer check macro. Checks non-null pointer.
+ */
+#define MALI_CHECK_NON_NULL(pointer, error_code) MALI_CHECK( ((pointer)!=NULL), (error_code) )
+
+/**
+ *	Error macro with goto. This checks whether the given condition is true, and if not jumps
+ *	to the specified label using a goto. The label must therefore be local to the function in
+ *	which this macro appears. This is most usually used to execute some clean-up code before
+ *	exiting with a call to ERROR.
+ *
+ *	Like the other macros, this is a macro to allow us to override the condition if we wish,
+ *	e.g. to force an error during stress testing.
+ */
+#define MALI_CHECK_GOTO(condition, label) do { if(!(condition)) goto label; } while(0)
+
+/**
+ *  Explicitly ignore a parameter passed into a function, to suppress compiler warnings.
+ *  Should only be used with parameter names.
+ */
+#define MALI_IGNORE(x) x=x
+
+#define MALI_PRINTF(args) _mali_osk_dbgmsg args;
+
+#define MALI_PRINT_ERROR(args) do{ \
+	MALI_PRINTF(("Mali: ERR: %s\n" ,__FILE__)); \
+	MALI_PRINTF(("           %s()%4d\n           ", __FUNCTION__, __LINE__)) ; \
+	MALI_PRINTF(args); \
+	MALI_PRINTF(("\n")); \
+	} while(0)
+
+#define MALI_PRINT(args) do{ \
+	MALI_PRINTF(("Mali: ")); \
+	MALI_PRINTF(args); \
+	} while (0)
+
+#ifdef DEBUG
+extern int mali_debug_level;
+
+#define MALI_DEBUG_CODE(code) code
+#define MALI_DEBUG_PRINT(level, args)  do { \
+	if((level) <=  mali_debug_level)\
+        {MALI_PRINTF(("Mali<" #level ">: ")); MALI_PRINTF(args); } \
+	} while (0)
+
+#define MALI_DEBUG_PRINT_ERROR(args) MALI_PRINT_ERROR(args)
+
+#define MALI_DEBUG_PRINT_IF(level,condition,args)  \
+	if((condition)&&((level) <=  mali_debug_level))\
+        {MALI_PRINTF(("Mali<" #level ">: ")); MALI_PRINTF(args); }
+
+#define MALI_DEBUG_PRINT_ELSE(level, args)\
+	else if((level) <=  mali_debug_level)\
+    { MALI_PRINTF(("Mali<" #level ">: ")); MALI_PRINTF(args); }
+
+/**
+ * @note these variants of DEBUG ASSERTS will cause a debugger breakpoint
+ * to be entered (see _mali_osk_break() ). An alternative would be to call
+ * _mali_osk_abort(), on OSs that support it.
+ */
+#define MALI_DEBUG_PRINT_ASSERT(condition, args) do  {if( !(condition)) { MALI_PRINT_ERROR(args); _mali_osk_break(); } } while(0)
+#define MALI_DEBUG_ASSERT_POINTER(pointer) do  {if( (pointer)== NULL) {MALI_PRINT_ERROR(("NULL pointer " #pointer)); _mali_osk_break();} } while(0)
+#define MALI_DEBUG_ASSERT(condition) do  {if( !(condition)) {MALI_PRINT_ERROR(("ASSERT failed: " #condition )); _mali_osk_break();} } while(0)
+
+#else /* DEBUG */
+
+#define MALI_DEBUG_CODE(code)
+#define MALI_DEBUG_PRINT(string,args) do {} while(0)
+#define MALI_DEBUG_PRINT_ERROR(args) do {} while(0)
+#define MALI_DEBUG_PRINT_IF(level,condition,args) do {} while(0)
+#define MALI_DEBUG_PRINT_ELSE(level,condition,args) do {} while(0)
+#define MALI_DEBUG_PRINT_ASSERT(condition,args) do {} while(0)
+#define MALI_DEBUG_ASSERT_POINTER(pointer) do {} while(0)
+#define MALI_DEBUG_ASSERT(condition) do {} while(0)
+
+#endif /* DEBUG */
+
+/**
+ * variables from user space cannot be dereferenced from kernel space; tagging them
+ * with __user allows the GCC compiler to generate a warning. Other compilers may
+ * not support this so we define it here as an empty macro if the compiler doesn't
+ * define it.
+ */
+#ifndef __user
+#define __user
+#endif
+
+#endif /* __MALI_KERNEL_COMMON_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_core.c b/drivers/media/video/samsung/mali/common/mali_kernel_core.c
new file mode 100644
index 0000000..be1889d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_core.c
@@ -0,0 +1,911 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_mem.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_kernel_pp.h"
+#include "mali_kernel_gp.h"
+#include "mali_osk.h"
+#include "mali_osk_mali.h"
+#include "mali_ukk.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_rendercore.h"
+#if defined USING_MALI400_L2_CACHE
+#include "mali_kernel_l2_cache.h"
+#endif
+#if USING_MALI_PMM
+#include "mali_pmm.h"
+#endif /* USING_MALI_PMM */
+
+/* platform specific set up */
+#include "mali_platform.h"
+
+/* Initialized when this subsystem is initialized. This is determined by the
+ * position in subsystems[], and so the value used to initialize this is
+ * determined at compile time */
+static mali_kernel_subsystem_identifier mali_subsystem_core_id = -1;
+
+/** Pointer to table of resource definitions available to the Mali driver.
+ *  _mali_osk_resources_init() sets up the pointer to this table.
+ */
+static _mali_osk_resource_t *arch_configuration = NULL;
+
+/** Number of resources initialized by _mali_osk_resources_init() */
+static u32 num_resources;
+
+static _mali_osk_errcode_t register_resources( _mali_osk_resource_t **arch_configuration, u32 num_resources );
+
+static _mali_osk_errcode_t initialize_subsystems(void);
+static void terminate_subsystems(void);
+
+static _mali_osk_errcode_t mali_kernel_subsystem_core_setup(mali_kernel_subsystem_identifier id);
+static void mali_kernel_subsystem_core_cleanup(mali_kernel_subsystem_identifier id);
+static _mali_osk_errcode_t mali_kernel_subsystem_core_system_info_fill(_mali_system_info* info);
+static _mali_osk_errcode_t mali_kernel_subsystem_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+
+static _mali_osk_errcode_t build_system_info(void);
+static void cleanup_system_info(_mali_system_info *cleanup);
+
+/**
+ * @brief handler for MEM_VALIDATION resources
+ *
+ * This resource handler is common to all memory systems. It provides a default
+ * means for validating requests to map in external memory via
+ * _mali_ukk_map_external_mem. In addition, if _mali_ukk_va_to_pa is
+ * implemented, then _mali_ukk_va_to_pa can make use of this MEM_VALIDATION
+ * resource.
+ *
+ * MEM_VALIDATION also provide a CPU physical to Mali physical address
+ * translation, for use by _mali_ukk_map_external_mem.
+ *
+ * @note MEM_VALIDATION resources are only to handle simple cases where a
+ * certain physical address range is allowed to be mapped in by any process,
+ * e.g. a framebuffer at a fixed location. If the implementor has more complex
+ * mapping requirements, then they must either:
+ * - implement their own memory validation function
+ * - or, integrate with UMP.
+ *
+ * @param resource The resource to handle (type MEM_VALIDATION)
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+static _mali_osk_errcode_t mali_kernel_core_resource_mem_validation(_mali_osk_resource_t * resource);
+
+/* MEM_VALIDATION handler state */
+typedef struct
+{
+	u32 phys_base;        /**< Mali physical base of the memory, page aligned */
+	u32 size;             /**< size in bytes of the memory, multiple of page size */
+	s32 cpu_usage_adjust; /**< Offset to add to Mali Physical address to obtain CPU physical address */
+} _mali_mem_validation_t;
+
+#define INVALID_MEM 0xffffffff
+
+static _mali_mem_validation_t mem_validator = { INVALID_MEM, INVALID_MEM, -1 };
+
+static struct mali_kernel_subsystem mali_subsystem_core =
+{
+	mali_kernel_subsystem_core_setup,               /* startup */
+    mali_kernel_subsystem_core_cleanup,             /* shutdown */
+    NULL,                                           /* load_complete */
+    mali_kernel_subsystem_core_system_info_fill,    /* system_info_fill */
+	mali_kernel_subsystem_core_session_begin,       /* session_begin */
+    NULL,                                           /* session_end */
+    NULL,                                           /* broadcast_notification */
+#if MALI_STATE_TRACKING
+	NULL,                                           /* dump_state */
+#endif
+};
+
+static struct mali_kernel_subsystem * subsystems[] =
+{
+
+#if USING_MALI_PMM
+	/* The PMM must be initialized before any cores - including L2 cache */
+	&mali_subsystem_pmm,
+#endif
+
+	/* always included */
+	&mali_subsystem_memory,
+
+	/* The rendercore subsystem must be initialized before any subsystem based on the
+	 * rendercores is started e.g. mali_subsystem_mali200 and mali_subsystem_gp2 */
+	&mali_subsystem_rendercore,
+
+ 	/* add reference to the subsystem */
+	&mali_subsystem_mali200,
+
+ 	/* add reference to the subsystem */
+	&mali_subsystem_gp2,
+
+#if defined USING_MALI400_L2_CACHE
+	&mali_subsystem_l2_cache,
+#endif
+
+	/* always included */
+	/* NOTE Keep the core entry at the tail of the list */
+	&mali_subsystem_core
+};
+
+#define SUBSYSTEMS_COUNT ( sizeof(subsystems) / sizeof(subsystems[0]) )
+
+/* Pointers to this type available as incomplete struct in mali_kernel_session_manager.h */
+struct mali_session_data
+{
+	void * subsystem_data[SUBSYSTEMS_COUNT];
+	_mali_osk_notification_queue_t * ioctl_queue;
+};
+
+static mali_kernel_resource_registrator resource_handler[RESOURCE_TYPE_COUNT] = { NULL, };
+
+/* system info variables */
+static _mali_osk_lock_t *system_info_lock = NULL;
+static _mali_system_info * system_info = NULL;
+static u32 system_info_size = 0;
+
+/* is called from OS specific driver entry point */
+_mali_osk_errcode_t mali_kernel_constructor( void )
+{
+    _mali_osk_errcode_t err;
+
+	err = mali_platform_init();
+	if (_MALI_OSK_ERR_OK != err) goto error1;
+
+    err = _mali_osk_init();
+    if (_MALI_OSK_ERR_OK != err) goto error2;
+
+	MALI_DEBUG_PRINT(2, ("\n"));
+	MALI_DEBUG_PRINT(2, ("Inserting Mali v%d device driver. \n",_MALI_API_VERSION));
+	MALI_DEBUG_PRINT(2, ("Compiled: %s, time: %s.\n", __DATE__, __TIME__));
+	MALI_DEBUG_PRINT(2, ("Svn revision: %s\n", SVN_REV_STRING));
+
+    err  = initialize_subsystems();
+    if (_MALI_OSK_ERR_OK != err) goto error3;
+
+    MALI_PRINT(("Mali device driver %s loaded\n", SVN_REV_STRING));
+
+	MALI_SUCCESS;
+
+error3:
+	MALI_PRINT(("Mali subsystems failed\n"));
+    _mali_osk_term();
+error2:
+	MALI_PRINT(("Mali device driver init failed\n"));
+	if (_MALI_OSK_ERR_OK != mali_platform_deinit())
+	{
+		MALI_PRINT(("Failed to deinit platform\n"));
+	}
+error1:
+	MALI_PRINT(("Failed to init platform\n"));
+	MALI_ERROR(err);
+}
+
+/* is called from OS specific driver exit point */
+void mali_kernel_destructor( void )
+{
+	MALI_DEBUG_PRINT(2, ("\n"));
+	MALI_DEBUG_PRINT(2, ("Unloading Mali v%d device driver.\n",_MALI_API_VERSION));
+#if USING_MALI_PMM
+	malipmm_force_powerup();
+#endif
+	terminate_subsystems(); /* subsystems are responsible for their registered resources */
+    _mali_osk_term();
+
+	if (_MALI_OSK_ERR_OK != mali_platform_deinit())
+	{
+		MALI_PRINT(("Failed to deinit platform\n"));
+	}
+	MALI_DEBUG_PRINT(2, ("Module unloaded.\n"));
+}
+
+_mali_osk_errcode_t register_resources( _mali_osk_resource_t **arch_configuration, u32 num_resources )
+{
+	_mali_osk_resource_t *arch_resource = *arch_configuration;
+	u32 i;
+#if USING_MALI_PMM
+	u32 is_pmu_first_resource = 1;
+#endif /* USING_MALI_PMM */
+
+	/* loop over arch configuration */
+	for (i = 0; i < num_resources; ++i, arch_resource++)
+	{
+		if (  (arch_resource->type >= RESOURCE_TYPE_FIRST) &&
+		      (arch_resource->type < RESOURCE_TYPE_COUNT) &&
+		      (NULL != resource_handler[arch_resource->type])
+		   )
+		{	
+#if USING_MALI_PMM
+			if((arch_resource->type != PMU) && (is_pmu_first_resource == 1))
+			{
+				_mali_osk_resource_t mali_pmu_virtual_resource;
+				mali_pmu_virtual_resource.type = PMU;
+				mali_pmu_virtual_resource.description = "Virtual PMU";
+				mali_pmu_virtual_resource.base = 0x00000000;
+				mali_pmu_virtual_resource.cpu_usage_adjust = 0;
+				mali_pmu_virtual_resource.size = 0;
+				mali_pmu_virtual_resource.irq = 0;
+				mali_pmu_virtual_resource.flags = 0;
+				mali_pmu_virtual_resource.mmu_id = 0;
+				mali_pmu_virtual_resource.alloc_order = 0;
+				MALI_CHECK_NO_ERROR(resource_handler[mali_pmu_virtual_resource.type](&mali_pmu_virtual_resource));
+			}
+			is_pmu_first_resource = 0;
+#endif /* USING_MALI_PMM */
+
+			MALI_CHECK_NO_ERROR(resource_handler[arch_resource->type](arch_resource));
+			/* the subsystem shutdown process will release all the resources already registered */
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(1, ("No handler installed for resource %s, type %d\n", arch_resource->description, arch_resource->type));
+			MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+		}
+	}
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t initialize_subsystems(void)
+{
+	int i, j;
+    _mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT; /* default error code */
+
+    MALI_CHECK_NON_NULL(system_info_lock = _mali_osk_lock_init( (_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_SPINLOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE), 0, 0 ), _MALI_OSK_ERR_FAULT);
+
+	for (i = 0; i < (int)SUBSYSTEMS_COUNT; ++i)
+	{
+		if (NULL != subsystems[i]->startup)
+		{
+			/* the subsystem has a startup function defined */
+			err = subsystems[i]->startup(i); /* the subsystem identifier is the offset in our subsystems array */
+			if (_MALI_OSK_ERR_OK != err) goto cleanup;
+		}
+	}
+
+	for (j = 0; j < (int)SUBSYSTEMS_COUNT; ++j)
+	{
+		if (NULL != subsystems[j]->load_complete)
+		{
+			/* the subsystem has a load_complete function defined */
+			err = subsystems[j]->load_complete(j);
+			if (_MALI_OSK_ERR_OK != err) goto cleanup;
+		}
+	}
+
+	/* All systems loaded and resources registered */
+	/* Build system info */
+	if (_MALI_OSK_ERR_OK != build_system_info()) goto cleanup;
+
+	MALI_SUCCESS; /* all ok */
+
+cleanup:
+	/* i is index of subsystem which failed to start, all indices before that has to be shut down */
+	for (i = i - 1; i >= 0; --i)
+	{
+		/* the subsystem identifier is the offset in our subsystems array */
+		/* Call possible shutdown notficiation functions */
+		if (NULL != subsystems[i]->shutdown) subsystems[i]->shutdown(i);
+	}
+
+    _mali_osk_lock_term( system_info_lock );
+    MALI_ERROR(err); /* err is what the module which failed its startup returned, or the default */
+}
+
+static void terminate_subsystems(void)
+{
+	int i;
+	/* shut down subsystems in reverse order from startup */
+	for (i = SUBSYSTEMS_COUNT - 1; i >= 0; --i)
+	{
+		/* the subsystem identifier is the offset in our subsystems array */
+		if (NULL != subsystems[i]->shutdown) subsystems[i]->shutdown(i);
+	}
+    if (system_info_lock) _mali_osk_lock_term( system_info_lock );
+
+	/* Free _mali_system_info struct */
+	cleanup_system_info(system_info);
+}
+
+void _mali_kernel_core_broadcast_subsystem_message(mali_core_notification_message message, u32 data)
+{
+	int i;
+
+	for (i = 0; i < (int)SUBSYSTEMS_COUNT; ++i)
+	{
+		if (NULL != subsystems[i]->broadcast_notification)
+		{
+			subsystems[i]->broadcast_notification(message, data);
+		}
+	}
+}
+
+static _mali_osk_errcode_t mali_kernel_subsystem_core_setup(mali_kernel_subsystem_identifier id)
+{
+    mali_subsystem_core_id = id;
+
+	/* Register our own resources */
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MEM_VALIDATION, mali_kernel_core_resource_mem_validation));
+
+    /* parse the arch resource definition and tell all the subsystems */
+	/* this is why the core subsystem has to be specified last in the subsystem array */
+    MALI_CHECK_NO_ERROR(_mali_osk_resources_init(&arch_configuration, &num_resources));
+
+    MALI_CHECK_NO_ERROR(register_resources(&arch_configuration, num_resources));
+
+    /* resource parsing succeeded and the subsystem have corretly accepted their resources */
+	MALI_SUCCESS;
+}
+
+static void mali_kernel_subsystem_core_cleanup(mali_kernel_subsystem_identifier id)
+{
+    _mali_osk_resources_term(&arch_configuration, num_resources);
+}
+
+static void cleanup_system_info(_mali_system_info *cleanup)
+{
+	_mali_core_info * current_core;
+	_mali_mem_info * current_mem;
+
+	/* delete all the core info structs */
+	while (NULL != cleanup->core_info)
+	{
+		current_core = cleanup->core_info;
+		cleanup->core_info = cleanup->core_info->next;
+		_mali_osk_free(current_core);
+	}
+
+	/* delete all the mem info struct */
+	while (NULL != cleanup->mem_info)
+	{
+		current_mem = cleanup->mem_info;
+		cleanup->mem_info = cleanup->mem_info->next;
+		_mali_osk_free(current_mem);
+	}
+
+	/* delete the system info struct itself */
+	_mali_osk_free(cleanup);
+}
+
+static _mali_osk_errcode_t build_system_info(void)
+{
+	unsigned int i;
+	int err = _MALI_OSK_ERR_FAULT;
+	_mali_system_info * new_info, * cleanup;
+	_mali_core_info * current_core;
+	_mali_mem_info * current_mem;
+	u32 new_size = 0;
+
+	/* create a new system info struct */
+	MALI_CHECK_NON_NULL(new_info = (_mali_system_info *)_mali_osk_malloc(sizeof(_mali_system_info)), _MALI_OSK_ERR_NOMEM);
+
+	_mali_osk_memset(new_info, 0, sizeof(_mali_system_info));
+
+	/* if an error happens during any of the system_info_fill calls cleanup the new info structs */
+	cleanup = new_info;
+
+	/* ask each subsystems to fill in their info */
+	for (i = 0; i < SUBSYSTEMS_COUNT; ++i)
+	{
+		if (NULL != subsystems[i]->system_info_fill)
+		{
+			err = subsystems[i]->system_info_fill(new_info);
+			if (_MALI_OSK_ERR_OK != err) goto error_exit;
+		}
+	}
+
+	/* building succeeded, calculate the size */
+
+	/* size needed of the system info struct itself */
+	new_size = sizeof(_mali_system_info);
+
+	/* size needed for the cores */
+	for (current_core = new_info->core_info; NULL != current_core; current_core = current_core->next)
+	{
+		new_size += sizeof(_mali_core_info);
+	}
+
+	/* size needed for the memory banks */
+	for (current_mem = new_info->mem_info; NULL != current_mem; current_mem = current_mem->next)
+	{
+		new_size += sizeof(_mali_mem_info);
+	}
+
+	/* lock system info access so a user wont't get a corrupted version */
+	_mali_osk_lock_wait( system_info_lock, _MALI_OSK_LOCKMODE_RW );
+
+	/* cleanup the old one */
+	cleanup = system_info;
+	/* set new info */
+	system_info = new_info;
+	system_info_size = new_size;
+
+	/* we're safe */
+	_mali_osk_lock_signal( system_info_lock, _MALI_OSK_LOCKMODE_RW );
+
+	/* ok result */
+	err = _MALI_OSK_ERR_OK;
+
+	/* we share the cleanup routine with the error case */
+error_exit:
+	if (NULL == cleanup) MALI_ERROR((_mali_osk_errcode_t)err); /* no cleanup needed, return what err contains */
+
+	/* cleanup */
+	cleanup_system_info(cleanup);
+
+	/* return whatever err is, we could end up here in both the error and success cases */
+	MALI_ERROR((_mali_osk_errcode_t)err);
+}
+
+_mali_osk_errcode_t _mali_ukk_get_api_version( _mali_uk_get_api_version_s *args )
+{
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    /* check compatability */
+	if ( args->version == _MALI_UK_API_VERSION )
+	{
+		args->compatible = 1;
+	}
+	else
+	{
+		args->compatible = 0;
+	}
+
+	args->version = _MALI_UK_API_VERSION; /* report our version */
+
+	/* success regardless of being compatible or not */
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_get_system_info_size(_mali_uk_get_system_info_size_s *args)
+{
+    MALI_DEBUG_ASSERT_POINTER(args);
+    args->size = system_info_size;
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_get_system_info( _mali_uk_get_system_info_s *args )
+{
+	_mali_core_info * current_core;
+	_mali_mem_info * current_mem;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
+	void * current_write_pos, ** current_patch_pos;
+    u32 adjust_ptr_base;
+
+	/* check input */
+	MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    MALI_CHECK_NON_NULL(args->system_info, _MALI_OSK_ERR_INVALID_ARGS);
+
+	/* lock the system info */
+	_mali_osk_lock_wait( system_info_lock, _MALI_OSK_LOCKMODE_RW );
+
+	/* first check size */
+	if (args->size < system_info_size) goto exit_when_locked;
+
+	/* we build a copy of system_info in the user space buffer specified by the user and
+     * patch up the pointers. The ukk_private members of _mali_uk_get_system_info_s may
+     * indicate a different base address for patching the pointers (normally the
+     * address of the provided system_info buffer would be used). This is helpful when
+     * the system_info buffer needs to get copied to user space and the pointers need
+     * to be in user space.
+     */
+    if (0 == args->ukk_private)
+    {
+        adjust_ptr_base = (u32)args->system_info;
+    }
+    else
+    {
+        adjust_ptr_base = args->ukk_private;
+    }
+
+	/* copy each struct into the buffer, and update its pointers */
+	current_write_pos = (void *)args->system_info;
+
+	/* first, the master struct */
+	_mali_osk_memcpy(current_write_pos, system_info, sizeof(_mali_system_info));
+
+	/* advance write pointer */
+	current_write_pos = (void *)((u32)current_write_pos + sizeof(_mali_system_info));
+
+	/* first we write the core info structs, patch starts at master's core_info pointer */
+	current_patch_pos = (void **)((u32)args->system_info + offsetof(_mali_system_info, core_info));
+
+	for (current_core = system_info->core_info; NULL != current_core; current_core = current_core->next)
+	{
+
+		/* patch the pointer pointing to this core */
+		*current_patch_pos = (void*)(adjust_ptr_base + ((u32)current_write_pos - (u32)args->system_info));
+
+		/* copy the core info */
+		_mali_osk_memcpy(current_write_pos, current_core, sizeof(_mali_core_info));
+
+		/* update patch pos */
+		current_patch_pos = (void **)((u32)current_write_pos + offsetof(_mali_core_info, next));
+
+		/* advance write pos in memory */
+		current_write_pos = (void *)((u32)current_write_pos + sizeof(_mali_core_info));
+	}
+	/* patching of last patch pos is not needed, since we wrote NULL there in the first place */
+
+	/* then we write the mem info structs, patch starts at master's mem_info pointer */
+	current_patch_pos = (void **)((u32)args->system_info + offsetof(_mali_system_info, mem_info));
+
+	for (current_mem = system_info->mem_info; NULL != current_mem; current_mem = current_mem->next)
+	{
+		/* patch the pointer pointing to this core */
+		*current_patch_pos = (void*)(adjust_ptr_base + ((u32)current_write_pos - (u32)args->system_info));
+
+		/* copy the core info */
+		_mali_osk_memcpy(current_write_pos, current_mem, sizeof(_mali_mem_info));
+
+		/* update patch pos */
+		current_patch_pos = (void **)((u32)current_write_pos + offsetof(_mali_mem_info, next));
+
+		/* advance write pos in memory */
+		current_write_pos = (void *)((u32)current_write_pos + sizeof(_mali_mem_info));
+	}
+	/* patching of last patch pos is not needed, since we wrote NULL there in the first place */
+
+	err = _MALI_OSK_ERR_OK;
+exit_when_locked:
+	_mali_osk_lock_signal( system_info_lock, _MALI_OSK_LOCKMODE_RW );
+    MALI_ERROR(err);
+}
+
+_mali_osk_errcode_t _mali_ukk_wait_for_notification( _mali_uk_wait_for_notification_s *args )
+{
+	_mali_osk_errcode_t err;
+	_mali_osk_notification_t * notification;
+    _mali_osk_notification_queue_t *queue;
+
+    /* check input */
+	MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    queue = (_mali_osk_notification_queue_t *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_core_id);
+
+	/* if the queue does not exist we're currently shutting down */
+	if (NULL == queue)
+	{
+		MALI_DEBUG_PRINT(1, ("No notification queue registered with the session. Asking userspace to stop querying\n"));
+        args->type = _MALI_NOTIFICATION_CORE_SHUTDOWN_IN_PROGRESS;
+		MALI_SUCCESS;
+	}
+
+    /* receive a notification, might sleep */
+	err = _mali_osk_notification_queue_receive(queue, &notification);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+        MALI_ERROR(err); /* errcode returned, pass on to caller */
+    }
+
+	/* copy the buffer to the user */
+    args->type = (_mali_uk_notification_type)notification->notification_type;
+    _mali_osk_memcpy(&args->data, notification->result_buffer, notification->result_buffer_size);
+
+	/* finished with the notification */
+	_mali_osk_notification_delete( notification );
+
+    MALI_SUCCESS; /* all ok */
+}
+
+_mali_osk_errcode_t _mali_ukk_post_notification( _mali_uk_post_notification_s *args )
+{
+	_mali_osk_notification_t * notification;
+    _mali_osk_notification_queue_t *queue;
+
+    /* check input */
+	MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    queue = (_mali_osk_notification_queue_t *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_core_id);
+
+	/* if the queue does not exist we're currently shutting down */
+	if (NULL == queue)
+	{
+		MALI_DEBUG_PRINT(1, ("No notification queue registered with the session. Asking userspace to stop querying\n"));
+		MALI_SUCCESS;
+	}
+
+	notification = _mali_osk_notification_create(args->type, 0);
+	if ( NULL == notification)
+	{
+		MALI_PRINT_ERROR( ("Failed to create notification object\n")) ;
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	_mali_osk_notification_queue_send(queue, notification);
+
+    MALI_SUCCESS; /* all ok */
+}
+
+static _mali_osk_errcode_t mali_kernel_subsystem_core_system_info_fill(_mali_system_info* info)
+{
+    MALI_CHECK_NON_NULL(info, _MALI_OSK_ERR_INVALID_ARGS);
+
+	info->drivermode = _MALI_DRIVER_MODE_NORMAL;
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_kernel_subsystem_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue)
+{
+    MALI_CHECK_NON_NULL(slot, _MALI_OSK_ERR_INVALID_ARGS);
+	*slot = queue;
+	MALI_SUCCESS;
+}
+
+/* MEM_VALIDATION resource handler */
+static _mali_osk_errcode_t mali_kernel_core_resource_mem_validation(_mali_osk_resource_t * resource)
+{
+	/* Check that no other MEM_VALIDATION resources exist */
+	MALI_CHECK( ((u32)-1) == mem_validator.phys_base, _MALI_OSK_ERR_FAULT );
+
+	/* Check restrictions on page alignment */
+	MALI_CHECK( 0 == (resource->base & (~_MALI_OSK_CPU_PAGE_MASK)), _MALI_OSK_ERR_FAULT );
+	MALI_CHECK( 0 == (resource->size & (~_MALI_OSK_CPU_PAGE_MASK)), _MALI_OSK_ERR_FAULT );
+	MALI_CHECK( 0 == (resource->cpu_usage_adjust & (~_MALI_OSK_CPU_PAGE_MASK)), _MALI_OSK_ERR_FAULT );
+
+	mem_validator.phys_base = resource->base;
+	mem_validator.size = resource->size;
+	mem_validator.cpu_usage_adjust = resource->cpu_usage_adjust;
+	MALI_DEBUG_PRINT( 2, ("Memory Validator '%s' installed for Mali physical address base==0x%08X, size==0x%08X, cpu_adjust==0x%08X\n",
+						  resource->description, mem_validator.phys_base, mem_validator.size, mem_validator.cpu_usage_adjust ));
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_kernel_core_translate_cpu_to_mali_phys_range( u32 *phys_base, u32 size )
+{
+	u32 mali_phys_base;
+
+	mali_phys_base = *phys_base - mem_validator.cpu_usage_adjust;
+
+	MALI_CHECK( 0 == ( mali_phys_base & (~_MALI_OSK_CPU_PAGE_MASK)), _MALI_OSK_ERR_FAULT );
+	MALI_CHECK( 0 == ( size & (~_MALI_OSK_CPU_PAGE_MASK)), _MALI_OSK_ERR_FAULT );
+
+	MALI_CHECK_NO_ERROR( mali_kernel_core_validate_mali_phys_range( mali_phys_base, size ) );
+
+	*phys_base = mali_phys_base;
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_kernel_core_validate_mali_phys_range( u32 phys_base, u32 size )
+{
+	MALI_CHECK_GOTO( 0 == ( phys_base & (~_MALI_OSK_CPU_PAGE_MASK)), failure );
+	MALI_CHECK_GOTO( 0 == ( size & (~_MALI_OSK_CPU_PAGE_MASK)), failure );
+
+	if ( phys_base             >= mem_validator.phys_base
+		 && (phys_base + size) >= mem_validator.phys_base
+		 && phys_base          <= (mem_validator.phys_base + mem_validator.size)
+		 && (phys_base + size) <= (mem_validator.phys_base + mem_validator.size) )
+	{
+		MALI_SUCCESS;
+	}
+
+ failure:
+	MALI_PRINTF( ("*******************************************************************************\n") );
+	MALI_PRINTF( ("MALI PHYSICAL RANGE VALIDATION ERROR!\n") );
+	MALI_PRINTF( ("\n") );
+	MALI_PRINTF( ("We failed to validate a Mali-Physical range that the user-side wished to map in\n") );
+	MALI_PRINTF( ("\n") );
+	MALI_PRINTF( ("It is likely that the user-side wished to do Direct Rendering, but a suitable\n") );
+	MALI_PRINTF( ("address range validation mechanism has not been correctly setup\n") );
+	MALI_PRINTF( ("\n") );
+	MALI_PRINTF( ("The range supplied was: phys_base=0x%08X, size=0x%08X\n", phys_base, size) );
+	MALI_PRINTF( ("\n") );
+	MALI_PRINTF( ("Please refer to the ARM Mali Software Integration Guide for more information.\n") );
+	MALI_PRINTF( ("\n") );
+	MALI_PRINTF( ("*******************************************************************************\n") );
+
+	MALI_ERROR( _MALI_OSK_ERR_FAULT );
+}
+
+
+_mali_osk_errcode_t _mali_kernel_core_register_resource_handler(_mali_osk_resource_type_t type, mali_kernel_resource_registrator handler)
+{
+	MALI_CHECK(type < RESOURCE_TYPE_COUNT, _MALI_OSK_ERR_INVALID_ARGS);
+	MALI_DEBUG_ASSERT(NULL == resource_handler[type]); /* A handler for resource already exists */
+	resource_handler[type] = handler;
+	MALI_SUCCESS;
+}
+
+void * mali_kernel_session_manager_slot_get(struct mali_session_data * session_data, int id)
+{
+	MALI_DEBUG_ASSERT_POINTER(session_data);
+	if(id >= SUBSYSTEMS_COUNT) { MALI_DEBUG_PRINT(3, ("mali_kernel_session_manager_slot_get: id %d out of range\n", id)); return NULL; }
+
+	if (NULL == session_data) { MALI_DEBUG_PRINT(3, ("mali_kernel_session_manager_slot_get: got NULL session data\n")); return NULL; }
+	return session_data->subsystem_data[id];
+}
+
+_mali_osk_errcode_t _mali_ukk_open(void **context)
+{
+	int i;
+    _mali_osk_errcode_t err;
+	struct mali_session_data * session_data;
+
+	/* allocated struct to track this session */
+	session_data = (struct mali_session_data *)_mali_osk_malloc(sizeof(struct mali_session_data));
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_NOMEM);
+
+	_mali_osk_memset(session_data->subsystem_data, 0, sizeof(session_data->subsystem_data));
+
+	/* create a response queue for this session */
+	session_data->ioctl_queue = _mali_osk_notification_queue_init();
+	if (NULL == session_data->ioctl_queue)
+	{
+		_mali_osk_free(session_data);
+        MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	MALI_DEBUG_PRINT(3, ("Session starting\n"));
+
+	/* call session_begin on all subsystems */
+	for (i = 0; i < (int)SUBSYSTEMS_COUNT; ++i)
+	{
+		if (NULL != subsystems[i]->session_begin)
+		{
+			/* subsystem has a session_begin */
+			err = subsystems[i]->session_begin(session_data, &session_data->subsystem_data[i], session_data->ioctl_queue);
+            MALI_CHECK_GOTO(err == _MALI_OSK_ERR_OK, cleanup);
+		}
+	}
+
+    *context = (void*)session_data;
+
+	MALI_DEBUG_PRINT(3, ("Session started\n"));
+	MALI_SUCCESS;
+
+cleanup:
+	MALI_DEBUG_PRINT(2, ("Session startup failed\n"));
+	/* i is index of subsystem which failed session begin, all indices before that has to be ended */
+	/* end subsystem sessions in the reverse order they where started in */
+	for (i = i - 1; i >= 0; --i)
+	{
+		if (NULL != subsystems[i]->session_end) subsystems[i]->session_end(session_data, &session_data->subsystem_data[i]);
+	}
+
+	_mali_osk_notification_queue_term(session_data->ioctl_queue);
+	_mali_osk_free(session_data);
+
+	/* return what the subsystem which failed session start returned */
+    MALI_ERROR(err);
+}
+
+_mali_osk_errcode_t _mali_ukk_close(void **context)
+{
+    int i;
+	struct mali_session_data * session_data;
+
+    MALI_CHECK_NON_NULL(context, _MALI_OSK_ERR_INVALID_ARGS);
+
+	session_data = (struct mali_session_data *)*context;
+
+	MALI_DEBUG_PRINT(2, ("Session ending\n"));
+
+	/* end subsystem sessions in the reverse order they where started in */
+	for (i = SUBSYSTEMS_COUNT - 1; i >= 0; --i)
+    {
+		if (NULL != subsystems[i]->session_end) subsystems[i]->session_end(session_data, &session_data->subsystem_data[i]);
+	}
+
+	_mali_osk_notification_queue_term(session_data->ioctl_queue);
+	_mali_osk_free(session_data);
+
+    *context = NULL;
+
+	MALI_DEBUG_PRINT(2, ("Session has ended\n"));
+
+    MALI_SUCCESS;
+}
+
+#if USING_MALI_PMM
+
+_mali_osk_errcode_t mali_core_signal_power_up( mali_pmm_core_id core, mali_bool queue_only )
+{
+	switch( core )
+	{
+	case MALI_PMM_CORE_GP:
+		MALI_CHECK_NO_ERROR(maligp_signal_power_up(queue_only));
+		break;
+#if defined USING_MALI400_L2_CACHE
+	case MALI_PMM_CORE_L2:
+		if( !queue_only )
+		{
+			/* Enable L2 cache due to power up */			
+			mali_kernel_l2_cache_do_enable();
+
+			/* Invalidate the cache on power up */
+			MALI_DEBUG_PRINT(5, ("L2 Cache: Invalidate all\n"));
+			MALI_CHECK_NO_ERROR(mali_kernel_l2_cache_invalidate_all());
+		}
+		break;
+#endif
+	case MALI_PMM_CORE_PP0:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_up(0, queue_only));
+		break;
+	case MALI_PMM_CORE_PP1:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_up(1, queue_only));
+		break;
+	case MALI_PMM_CORE_PP2:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_up(2, queue_only));
+		break;
+	case MALI_PMM_CORE_PP3:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_up(3, queue_only));
+		break;
+	default:
+		/* Unknown core */
+		MALI_DEBUG_PRINT_ERROR( ("Unknown core signalled with power up: %d\n", core) );
+		MALI_ERROR( _MALI_OSK_ERR_INVALID_ARGS );
+	}
+	
+	MALI_SUCCESS;
+}
+	
+_mali_osk_errcode_t mali_core_signal_power_down( mali_pmm_core_id core, mali_bool immediate_only )
+{
+	switch( core )
+	{
+	case MALI_PMM_CORE_GP:
+		MALI_CHECK_NO_ERROR(maligp_signal_power_down(immediate_only));
+		break;
+#if defined USING_MALI400_L2_CACHE
+	case MALI_PMM_CORE_L2:
+		/* Nothing to do */
+		break;
+#endif
+	case MALI_PMM_CORE_PP0:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_down(0, immediate_only));
+		break;
+	case MALI_PMM_CORE_PP1:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_down(1, immediate_only));
+		break;
+	case MALI_PMM_CORE_PP2:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_down(2, immediate_only));
+		break;
+	case MALI_PMM_CORE_PP3:
+		MALI_CHECK_NO_ERROR(malipp_signal_power_down(3, immediate_only));
+		break;
+	default:
+		/* Unknown core */
+		MALI_DEBUG_PRINT_ERROR( ("Unknown core signalled with power down: %d\n", core) );
+		MALI_ERROR( _MALI_OSK_ERR_INVALID_ARGS );
+	}
+	
+	MALI_SUCCESS;
+}
+
+#endif
+
+
+#if MALI_STATE_TRACKING
+u32 _mali_kernel_core_dump_state(char* buf, u32 size)
+{
+	int i, n;
+	char *original_buf = buf;
+	for (i = 0; i < SUBSYSTEMS_COUNT; ++i)
+	{
+		if (NULL != subsystems[i]->dump_state)
+		{
+			n = subsystems[i]->dump_state(buf, size);
+			size -= n;
+			buf += n;
+		}
+	}
+#if USING_MALI_PMM
+	n = mali_pmm_dump_os_thread_state(buf, size);
+	size -= n;
+	buf += n;
+#endif
+	/* Return number of bytes written to buf */
+	return (u32)(buf - original_buf);
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_core.h b/drivers/media/video/samsung/mali/common/mali_kernel_core.h
new file mode 100644
index 0000000..715c1cd
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_core.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_CORE_H__
+#define __MALI_KERNEL_CORE_H__
+
+#include "mali_osk.h"
+
+#if USING_MALI_PMM
+#include "mali_ukk.h"
+#include "mali_pmm.h"
+#include "mali_pmm_system.h"
+#endif
+
+_mali_osk_errcode_t mali_kernel_constructor( void );
+void mali_kernel_destructor( void );
+
+/**
+ * @brief Tranlate CPU physical to Mali physical addresses.
+ *
+ * This function is used to convert CPU physical addresses to Mali Physical
+ * addresses, such that _mali_ukk_map_external_mem may be used to map them
+ * into Mali. This will be used by _mali_ukk_va_to_mali_pa.
+ *
+ * This function only supports physically contiguous regions.
+ *
+ * A default implementation is provided, which uses a registered MEM_VALIDATION
+ * resource to do a static translation. Only an address range which will lie
+ * in the range specified by MEM_VALIDATION will be successfully translated.
+ *
+ * If a more complex, or non-static translation is required, then the
+ * implementor has the following options:
+ * - Rewrite this function to provide such a translation
+ * - Integrate the provider of the memory with UMP.
+ *
+ * @param[in,out] phys_base pointer to the page-aligned base address of the
+ * physical range to be translated
+ *
+ * @param[in] size size of the address range to be translated, which must be a
+ * multiple of the physical page size.
+ *
+ * @return on success, _MALI_OSK_ERR_OK and *phys_base is translated. If the
+ * cpu physical address range is not in the valid range, then a suitable
+ * _mali_osk_errcode_t error.
+ *
+ */
+_mali_osk_errcode_t mali_kernel_core_translate_cpu_to_mali_phys_range( u32 *phys_base, u32 size );
+
+
+/**
+ * @brief Validate a Mali physical address range.
+ *
+ * This function is used to ensure that an address range passed to
+ * _mali_ukk_map_external_mem is allowed to be mapped into Mali.
+ *
+ * This function only supports physically contiguous regions.
+ *
+ * A default implementation is provided, which uses a registered MEM_VALIDATION
+ * resource to do a static translation. Only an address range which will lie
+ * in the range specified by MEM_VALIDATION will be successfully validated.
+ *
+ * If a more complex, or non-static validation is required, then the
+ * implementor has the following options:
+ * - Rewrite this function to provide such a validation
+ * - Integrate the provider of the memory with UMP.
+ *
+ * @param phys_base page-aligned base address of the Mali physical range to be
+ * validated.
+ *
+ * @param size size of the address range to be validated, which must be a
+ * multiple of the physical page size.
+ *
+ * @return _MALI_OSK_ERR_OK if the Mali physical range is valid. Otherwise, a
+ * suitable _mali_osk_errcode_t error.
+ *
+ */
+_mali_osk_errcode_t mali_kernel_core_validate_mali_phys_range( u32 phys_base, u32 size );
+
+#if USING_MALI_PMM
+/**
+ * @brief Signal a power up on a Mali core.
+ *
+ * This function flags a core as powered up.
+ * For PP and GP cores it calls functions that move the core from a power off
+ * queue into the idle queue ready to run jobs. It also tries to schedule any
+ * pending jobs to run on it.
+ *
+ * This function will fail if the core is not powered off - either running or
+ * already idle.
+ *
+ * @param core The PMM core id to power up.
+ * @param queue_only When MALI_TRUE only re-queue the core - do not reset.
+ *
+ * @return _MALI_OSK_ERR_OK if the core has been powered up. Otherwise a
+ * suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_core_signal_power_up( mali_pmm_core_id core, mali_bool queue_only );
+
+/**
+ * @brief Signal a power down on a Mali core.
+ *
+ * This function flags a core as powered down.
+ * For PP and GP cores it calls functions that move the core from an idle
+ * queue into the power off queue.
+ *
+ * This function will fail if the core is not idle - either running or
+ * already powered down.
+ *
+ * @param core The PMM core id to power up.
+ * @param immediate_only Do not set the core to pending power down if it can't
+ * power down immediately
+ *
+ * @return _MALI_OSK_ERR_OK if the core has been powered up. Otherwise a
+ * suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_core_signal_power_down( mali_pmm_core_id core, mali_bool immediate_only );
+
+#endif
+
+/**
+ * Flag to indicate whether or not mali_benchmark is turned on.
+ */
+extern int mali_benchmark;
+
+
+#endif /* __MALI_KERNEL_CORE_H__ */
+
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.c b/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.c
new file mode 100644
index 0000000..8b2a97d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_kernel_descriptor_mapping.h"
+#include "mali_osk.h"
+#include "mali_osk_bitops.h"
+
+#define MALI_PAD_INT(x) (((x) + (BITS_PER_LONG - 1)) & ~(BITS_PER_LONG - 1))
+
+/**
+ * Allocate a descriptor table capable of holding 'count' mappings
+ * @param count Number of mappings in the table
+ * @return Pointer to a new table, NULL on error
+ */
+static mali_descriptor_table * descriptor_table_alloc(int count);
+
+/**
+ * Free a descriptor table
+ * @param table The table to free
+ */
+static void descriptor_table_free(mali_descriptor_table * table);
+
+mali_descriptor_mapping * mali_descriptor_mapping_create(int init_entries, int max_entries)
+{
+	mali_descriptor_mapping * map = _mali_osk_calloc(1, sizeof(mali_descriptor_mapping));
+
+	init_entries = MALI_PAD_INT(init_entries);
+	max_entries = MALI_PAD_INT(max_entries);
+
+	if (NULL != map)
+	{
+		map->table = descriptor_table_alloc(init_entries);
+		if (NULL != map->table)
+		{
+#if !USING_MMU
+            map->lock = _mali_osk_lock_init( (_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_READERWRITER | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE), 0, 20);
+#else
+            map->lock = _mali_osk_lock_init( (_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_READERWRITER | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE), 0, 116);
+#endif
+            if (NULL != map->lock)
+            {
+			    _mali_osk_set_nonatomic_bit(0, map->table->usage); /* reserve bit 0 to prevent NULL/zero logic to kick in */
+			    map->max_nr_mappings_allowed = max_entries;
+			    map->current_nr_mappings = init_entries;
+			    return map;
+            }
+        	descriptor_table_free(map->table);
+		}
+		_mali_osk_free(map);
+	}
+	return NULL;
+}
+
+void mali_descriptor_mapping_destroy(mali_descriptor_mapping * map)
+{
+	descriptor_table_free(map->table);
+    _mali_osk_lock_term(map->lock);
+	_mali_osk_free(map);
+}
+
+_mali_osk_errcode_t mali_descriptor_mapping_allocate_mapping(mali_descriptor_mapping * map, void * target, int *odescriptor)
+{
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
+	int new_descriptor;
+
+    MALI_DEBUG_ASSERT_POINTER(map);
+    MALI_DEBUG_ASSERT_POINTER(odescriptor);
+
+    _mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RW);
+	new_descriptor = _mali_osk_find_first_zero_bit(map->table->usage, map->current_nr_mappings);
+	if (new_descriptor == map->current_nr_mappings)
+	{
+		/* no free descriptor, try to expand the table */
+		mali_descriptor_table * new_table, * old_table;
+		if (map->current_nr_mappings >= map->max_nr_mappings_allowed) goto unlock_and_exit;
+
+        map->current_nr_mappings += BITS_PER_LONG;
+		new_table = descriptor_table_alloc(map->current_nr_mappings);
+		if (NULL == new_table) goto unlock_and_exit;
+
+        old_table = map->table;
+		_mali_osk_memcpy(new_table->usage, old_table->usage, (sizeof(unsigned long)*map->current_nr_mappings) / BITS_PER_LONG);
+		_mali_osk_memcpy(new_table->mappings, old_table->mappings, map->current_nr_mappings * sizeof(void*));
+		map->table = new_table;
+		descriptor_table_free(old_table);
+	}
+
+	/* we have found a valid descriptor, set the value and usage bit */
+	_mali_osk_set_nonatomic_bit(new_descriptor, map->table->usage);
+	map->table->mappings[new_descriptor] = target;
+	*odescriptor = new_descriptor;
+    err = _MALI_OSK_ERR_OK;
+
+unlock_and_exit:
+    _mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RW);
+    MALI_ERROR(err);
+}
+
+void mali_descriptor_mapping_call_for_each(mali_descriptor_mapping * map, void (*callback)(int, void*))
+{
+	int i;
+
+	MALI_DEBUG_ASSERT_POINTER(map);
+	MALI_DEBUG_ASSERT_POINTER(callback);
+
+    _mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RO);
+	/* id 0 is skipped as it's an reserved ID not mapping to anything */
+	for (i = 1; i < map->current_nr_mappings; ++i)
+	{
+		if (_mali_osk_test_bit(i, map->table->usage))
+		{
+			callback(i, map->table->mappings[i]);
+		}
+	}
+    _mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RO);
+}
+
+_mali_osk_errcode_t mali_descriptor_mapping_get(mali_descriptor_mapping * map, int descriptor, void** target)
+{
+	_mali_osk_errcode_t result = _MALI_OSK_ERR_FAULT;
+	MALI_DEBUG_ASSERT_POINTER(map);
+    _mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RO);
+	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		*target = map->table->mappings[descriptor];
+		result = _MALI_OSK_ERR_OK;
+	}
+	else *target = NULL;
+    _mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RO);
+	MALI_ERROR(result);
+}
+
+_mali_osk_errcode_t mali_descriptor_mapping_set(mali_descriptor_mapping * map, int descriptor, void * target)
+{
+	_mali_osk_errcode_t result = _MALI_OSK_ERR_FAULT;
+    _mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RO);
+	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		map->table->mappings[descriptor] = target;
+		result = _MALI_OSK_ERR_OK;
+	}
+    _mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RO);
+	MALI_ERROR(result);
+}
+
+void mali_descriptor_mapping_free(mali_descriptor_mapping * map, int descriptor)
+{
+    _mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RW);
+	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		map->table->mappings[descriptor] = NULL;
+		_mali_osk_clear_nonatomic_bit(descriptor, map->table->usage);
+	}
+    _mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RW);
+}
+
+static mali_descriptor_table * descriptor_table_alloc(int count)
+{
+	mali_descriptor_table * table;
+
+	table = _mali_osk_calloc(1, sizeof(mali_descriptor_table) + ((sizeof(unsigned long) * count)/BITS_PER_LONG) + (sizeof(void*) * count));
+
+	if (NULL != table)
+	{
+		table->usage = (u32*)((u8*)table + sizeof(mali_descriptor_table));
+		table->mappings = (void**)((u8*)table + sizeof(mali_descriptor_table) + ((sizeof(unsigned long) * count)/BITS_PER_LONG));
+	}
+
+	return table;
+}
+
+static void descriptor_table_free(mali_descriptor_table * table)
+{
+	_mali_osk_free(table);
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.h b/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.h
new file mode 100644
index 0000000..745be92
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_descriptor_mapping.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_kernel_descriptor_mapping.h
+ */
+
+#ifndef __MALI_KERNEL_DESCRIPTOR_MAPPING_H__
+#define __MALI_KERNEL_DESCRIPTOR_MAPPING_H__
+
+#include "mali_osk.h"
+
+/**
+ * The actual descriptor mapping table, never directly accessed by clients
+ */
+typedef struct mali_descriptor_table
+{
+	u32 * usage; /**< Pointer to bitpattern indicating if a descriptor is valid/used or not */
+	void** mappings; /**< Array of the pointers the descriptors map to */
+} mali_descriptor_table;
+
+/**
+ * The descriptor mapping object
+ * Provides a separate namespace where we can map an integer to a pointer
+ */
+typedef struct mali_descriptor_mapping
+{
+    _mali_osk_lock_t *lock; /**< Lock protecting access to the mapping object */
+	int max_nr_mappings_allowed; /**< Max number of mappings to support in this namespace */
+	int current_nr_mappings; /**< Current number of possible mappings */
+	mali_descriptor_table * table; /**< Pointer to the current mapping table */
+} mali_descriptor_mapping;
+
+/**
+ * Create a descriptor mapping object
+ * Create a descriptor mapping capable of holding init_entries growable to max_entries
+ * @param init_entries Number of entries to preallocate memory for
+ * @param max_entries Number of entries to max support
+ * @return Pointer to a descriptor mapping object, NULL on failure
+ */
+mali_descriptor_mapping * mali_descriptor_mapping_create(int init_entries, int max_entries);
+
+/**
+ * Destroy a descriptor mapping object
+ * @param map The map to free
+ */
+void mali_descriptor_mapping_destroy(mali_descriptor_mapping * map);
+
+/**
+ * Allocate a new mapping entry (descriptor ID)
+ * Allocates a new entry in the map.
+ * @param map The map to allocate a new entry in
+ * @param target The value to map to
+ * @return The descriptor allocated, a negative value on error
+ */
+_mali_osk_errcode_t mali_descriptor_mapping_allocate_mapping(mali_descriptor_mapping * map, void * target, int *descriptor);
+
+/**
+ * Get the value mapped to by a descriptor ID
+ * @param map The map to lookup the descriptor id in
+ * @param descriptor The descriptor ID to lookup
+ * @param target Pointer to a pointer which will receive the stored value
+ * @return 0 on successful lookup, negative on error
+ */
+_mali_osk_errcode_t mali_descriptor_mapping_get(mali_descriptor_mapping * map, int descriptor, void** target);
+
+/**
+ * Set the value mapped to by a descriptor ID
+ * @param map The map to lookup the descriptor id in
+ * @param descriptor The descriptor ID to lookup
+ * @param target Pointer to replace the current value with
+ * @return 0 on successful lookup, negative on error
+ */
+_mali_osk_errcode_t mali_descriptor_mapping_set(mali_descriptor_mapping * map, int descriptor, void * target);
+
+/**
+ * Call the specified callback function for each descriptor in map.
+ * Entire function is mutex protected.
+ * @param map The map to do callbacks for
+ * @param callback A callback function which will be calle for each entry in map
+ */
+void mali_descriptor_mapping_call_for_each(mali_descriptor_mapping * map, void (*callback)(int, void*));
+
+/**
+ * Free the descriptor ID
+ * For the descriptor to be reused it has to be freed
+ * @param map The map to free the descriptor from
+ * @param descriptor The descriptor ID to free
+ */
+void mali_descriptor_mapping_free(mali_descriptor_mapping * map, int descriptor);
+
+#endif /* __MALI_KERNEL_DESCRIPTOR_MAPPING_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_gp.h b/drivers/media/video/samsung/mali/common/mali_kernel_gp.h
new file mode 100644
index 0000000..efd3b43
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_gp.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_GP2_H__
+#define __MALI_KERNEL_GP2_H__
+
+extern struct mali_kernel_subsystem mali_subsystem_gp2;
+
+#if USING_MALI_PMM
+_mali_osk_errcode_t maligp_signal_power_up( mali_bool queue_only );
+_mali_osk_errcode_t maligp_signal_power_down( mali_bool immediate_only );
+#endif
+
+#endif /* __MALI_KERNEL_GP2_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.c b/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.c
new file mode 100644
index 0000000..e4d4ab1
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_osk_list.h"
+
+#include "mali_kernel_core.h"
+#include "mali_kernel_pp.h"
+#include "mali_kernel_subsystem.h"
+#include "regs/mali_200_regs.h"
+#include "mali_kernel_rendercore.h"
+#include "mali_kernel_l2_cache.h"
+
+/**
+ * Size of the Mali L2 cache registers in bytes
+ */
+#define MALI400_L2_CACHE_REGISTERS_SIZE 0x30
+
+/**
+ * Mali L2 cache register numbers
+ * Used in the register read/write routines.
+ * See the hardware documentation for more information about each register
+ */
+typedef enum mali_l2_cache_register {
+	MALI400_L2_CACHE_REGISTER_STATUS       = 0x0002,
+	/*unused                               = 0x0003 */
+	MALI400_L2_CACHE_REGISTER_COMMAND      = 0x0004, /**< Misc cache commands, e.g. clear */
+	MALI400_L2_CACHE_REGISTER_CLEAR_PAGE   = 0x0005,
+	MALI400_L2_CACHE_REGISTER_MAX_READS    = 0x0006, /**< Limit of outstanding read requests */
+	MALI400_L2_CACHE_REGISTER_ENABLE       = 0x0007, /**< Enable misc cache features */
+	MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0 = 0x0008,
+	MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0 = 0x0009,
+	MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1 = 0x000A,
+	MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1 = 0x000B,
+} mali_l2_cache_register;
+
+
+/**
+ * Mali L2 cache commands
+ * These are the commands that can be sent to the Mali L2 cache unit
+ */
+typedef enum mali_l2_cache_command
+{
+	MALI400_L2_CACHE_COMMAND_CLEAR_ALL = 0x01, /**< Clear the entire cache */
+	/* Read HW TRM carefully before adding/using other commands than the clear above */
+} mali_l2_cache_command;
+
+/**
+ * Mali L2 cache commands
+ * These are the commands that can be sent to the Mali L2 cache unit
+ */
+typedef enum mali_l2_cache_enable
+{
+	MALI400_L2_CACHE_ENABLE_DEFAULT = 0x0, /**< Default state of enable register */
+	MALI400_L2_CACHE_ENABLE_ACCESS = 0x01, /**< Permit cacheable accesses */
+	MALI400_L2_CACHE_ENABLE_READ_ALLOCATE = 0x02, /**< Permit cache read allocate */
+} mali_l2_cache_enable;
+
+/**
+ * Mali L2 cache status bits
+ */
+typedef enum mali_l2_cache_status
+{
+	MALI400_L2_CACHE_STATUS_COMMAND_BUSY = 0x01, /**< Command handler of L2 cache is busy */
+	MALI400_L2_CACHE_STATUS_DATA_BUSY    = 0x02, /**< L2 cache is busy handling data requests */
+} mali_l2_cache_status;
+
+
+/**
+ * Definition of the L2 cache core struct
+ * Used to track a L2 cache unit in the system.
+ * Contains information about the mapping of the registers
+ */
+typedef struct mali_kernel_l2_cache_core
+{
+	unsigned long base; /**< Physical address of the registers */
+	mali_io_address mapped_registers; /**< Virtual mapping of the registers */
+	u32 mapping_size; /**< Size of registers in bytes */
+	_mali_osk_list_t list; /**< Used to link multiple cache cores into a list */
+	_mali_osk_lock_t *lock; /**< Serialize all L2 cache commands */
+} mali_kernel_l2_cache_core;
+
+
+#define MALI400_L2_MAX_READS_DEFAULT 0x1C
+
+int mali_l2_max_reads = MALI400_L2_MAX_READS_DEFAULT;
+
+
+/**
+ * Mali L2 cache subsystem startup function
+ * Called by the driver core when the driver is loaded.
+ *
+ * @param id Identifier assigned by the core to the L2 cache subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_l2_cache_initialize(mali_kernel_subsystem_identifier id);
+
+/**
+ * Mali L2 cache subsystem shutdown function
+ * Called by the driver core when the driver is unloaded.
+ * Cleans up
+ * @param id Identifier assigned by the core to the L2 cache subsystem
+ */
+static void mali_l2_cache_terminate(mali_kernel_subsystem_identifier id);
+
+/**
+ * L2 cache subsystem complete notification function.
+ * Called by the driver core when all drivers have loaded and all resources has been registered
+ * @param id Identifier assigned by the core to the L2 cache subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_l2_cache_load_complete(mali_kernel_subsystem_identifier id);
+
+/**
+ * Mali L2 cache subsystem's notification handler for a Mali L2 cache resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each Mali L2 cache described in the active architecture's config.h file.
+ * @param resource The resource to handle (type MALI400L2)
+ * @return 0 if the Mali L2 cache was found and initialized, negative on error
+ */
+static _mali_osk_errcode_t mali_l2_cache_core_create(_mali_osk_resource_t * resource);
+
+/**
+ * Write to a L2 cache register
+ * Writes the given value to the specified register
+ * @param unit The L2 cache to write to
+ * @param reg The register to write to
+ * @param val The value to write to the register
+ */
+static void mali_l2_cache_register_write(mali_kernel_l2_cache_core * unit, mali_l2_cache_register reg, u32 val);
+
+
+
+/**
+ * Invalidate specified L2 cache
+ * @param cache The L2 cache to invalidate
+ * @return 0 if Mali L2 cache was successfully invalidated, otherwise error
+ */
+static _mali_osk_errcode_t mali_kernel_l2_cache_invalidate_all_cache(mali_kernel_l2_cache_core *cache);
+
+
+/*
+	The fixed Mali L2 cache system's mali subsystem interface implementation.
+	We currently handle module and session life-time management.
+*/
+struct mali_kernel_subsystem mali_subsystem_l2_cache =
+{
+	mali_l2_cache_initialize,    /**< startup */
+	NULL, /*mali_l2_cache_terminate,*/     /**< shutdown */
+	mali_l2_cache_load_complete, /**< load_complete */
+	NULL,                        /**< system_info_fill */
+	NULL,                        /**< session_begin */
+	NULL,                        /**< session_end */
+	NULL,                        /**< broadcast_notification */
+#if MALI_STATE_TRACKING
+	NULL,                        /**< dump_state */
+#endif
+};
+
+
+
+static _MALI_OSK_LIST_HEAD(caches_head);
+
+
+
+
+/* called during module init */
+static _mali_osk_errcode_t mali_l2_cache_initialize(mali_kernel_subsystem_identifier id)
+{
+	_mali_osk_errcode_t err;
+
+	MALI_IGNORE( id );
+
+	MALI_DEBUG_PRINT(2, ( "Mali L2 cache system initializing\n"));
+
+	_MALI_OSK_INIT_LIST_HEAD(&caches_head);
+
+	/* This will register the function for adding Mali L2 cache cores to the subsystem */
+	err = _mali_kernel_core_register_resource_handler(MALI400L2, mali_l2_cache_core_create);
+
+	MALI_ERROR(err);
+}
+
+
+
+/* called if/when our module is unloaded */
+static void mali_l2_cache_terminate(mali_kernel_subsystem_identifier id)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+
+	MALI_DEBUG_PRINT(2, ( "Mali L2 cache system terminating\n"));
+
+	/* loop over all L2 cache units and shut them down */
+	_MALI_OSK_LIST_FOREACHENTRY( cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list )
+	{
+		/* reset to defaults */
+		mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_MAX_READS, (u32)MALI400_L2_MAX_READS_DEFAULT);
+		mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_ENABLE, (u32)MALI400_L2_CACHE_ENABLE_DEFAULT);
+
+		/* remove from the list of cacges on the system */
+		_mali_osk_list_del( &cache->list );
+
+		/* release resources */
+		_mali_osk_mem_unmapioregion( cache->base, cache->mapping_size, cache->mapped_registers );
+		_mali_osk_mem_unreqregion( cache->base, cache->mapping_size );
+		_mali_osk_lock_term( cache->lock );
+		_mali_osk_free( cache );
+
+		#if USING_MALI_PMM
+			/* Unregister the L2 cache with the PMM */
+			malipmm_core_unregister( MALI_PMM_CORE_L2 );
+		#endif
+	}
+}
+
+static _mali_osk_errcode_t mali_l2_cache_core_create(_mali_osk_resource_t * resource)
+{
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT ;
+	mali_kernel_l2_cache_core * cache = NULL;
+
+	MALI_DEBUG_PRINT(2, ( "Creating Mali L2 cache: %s\n", resource->description));
+
+#if USING_MALI_PMM
+	/* Register the L2 cache with the PMM */
+	err = malipmm_core_register( MALI_PMM_CORE_L2 );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MALI_DEBUG_PRINT(1, ( "Failed to register L2 cache unit with PMM"));
+		return err;
+	}
+#endif
+
+	err = _mali_osk_mem_reqregion( resource->base, MALI400_L2_CACHE_REGISTERS_SIZE, resource->description);
+
+	MALI_CHECK_GOTO( _MALI_OSK_ERR_OK == err, err_cleanup_requestmem_failed);
+
+	/* Reset error that might be passed out */
+	err = _MALI_OSK_ERR_FAULT;
+
+	cache = _mali_osk_malloc(sizeof(mali_kernel_l2_cache_core));
+
+	MALI_CHECK_GOTO( NULL != cache, err_cleanup);
+
+	cache->lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_SPINLOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 104 );
+
+	MALI_CHECK_GOTO( NULL != cache->lock, err_cleanup);
+
+	/* basic setup */
+	_MALI_OSK_INIT_LIST_HEAD(&cache->list);
+
+	cache->base = resource->base;
+	cache->mapping_size = MALI400_L2_CACHE_REGISTERS_SIZE;
+
+	/* map the registers */
+	cache->mapped_registers = _mali_osk_mem_mapioregion( cache->base, cache->mapping_size, resource->description );
+
+	MALI_CHECK_GOTO( NULL != cache->mapped_registers, err_cleanup);
+
+	/* Invalidate cache (just to keep it in a known state at startup) */
+	err = mali_kernel_l2_cache_invalidate_all_cache(cache);
+
+	MALI_CHECK_GOTO( _MALI_OSK_ERR_OK == err, err_cleanup);
+
+	/* add to our list of L2 caches */
+	_mali_osk_list_add( &cache->list, &caches_head );
+
+	MALI_SUCCESS;
+
+err_cleanup:
+	/* This cleanup used when resources have been requested successfully */
+
+	if ( NULL != cache )
+	{
+		if (NULL != cache->mapped_registers)
+		{
+			_mali_osk_mem_unmapioregion( cache->base, cache->mapping_size, cache->mapped_registers);
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(1, ( "Failed to map Mali L2 cache registers at 0x%08lX\n", cache->base));
+		}
+
+		if( NULL != cache->lock )
+		{
+			_mali_osk_lock_term( cache->lock );
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(1, ( "Failed to allocate a lock for handling a L2 cache unit"));
+		}
+
+		_mali_osk_free( cache );
+	}
+	else
+	{
+		MALI_DEBUG_PRINT(1, ( "Failed to allocate memory for handling a L2 cache unit"));
+	}
+
+	/* A call is to request region, so this must always be reversed */
+	_mali_osk_mem_unreqregion( resource->base, MALI400_L2_CACHE_REGISTERS_SIZE);
+#if USING_MALI_PMM
+	malipmm_core_unregister( MALI_PMM_CORE_L2 );
+#endif
+	return err;
+
+err_cleanup_requestmem_failed:
+	MALI_DEBUG_PRINT(1, ("Failed to request Mali L2 cache '%s' register address space at (0x%08X - 0x%08X)\n",
+						 resource->description, resource->base, resource->base + MALI400_L2_CACHE_REGISTERS_SIZE - 1) );
+#if USING_MALI_PMM
+	malipmm_core_unregister( MALI_PMM_CORE_L2 );
+#endif
+	return err;
+
+}
+
+
+static void mali_l2_cache_register_write(mali_kernel_l2_cache_core * unit, mali_l2_cache_register reg, u32 val)
+{
+	_mali_osk_mem_iowrite32(unit->mapped_registers, (u32)reg * sizeof(u32), val);
+}
+
+
+static u32 mali_l2_cache_register_read(mali_kernel_l2_cache_core * unit, mali_l2_cache_register reg)
+{
+	return _mali_osk_mem_ioread32(unit->mapped_registers, (u32)reg * sizeof(u32));
+}
+
+void mali_kernel_l2_cache_do_enable(void)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+
+	/* loop over all L2 cache units and enable them*/
+	_MALI_OSK_LIST_FOREACHENTRY( cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list)
+	{
+		mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_ENABLE, (u32)MALI400_L2_CACHE_ENABLE_ACCESS | (u32)MALI400_L2_CACHE_ENABLE_READ_ALLOCATE);
+		mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_MAX_READS, (u32)mali_l2_max_reads);
+	}
+}
+
+
+static _mali_osk_errcode_t mali_l2_cache_load_complete(mali_kernel_subsystem_identifier id)
+{
+	mali_kernel_l2_cache_do_enable();
+	MALI_DEBUG_PRINT(2, ( "Mali L2 cache system load complete\n"));
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_kernel_l2_cache_send_command(mali_kernel_l2_cache_core *cache, u32 reg, u32 val)
+{
+	int i = 0;
+	const int loop_count = 100000;
+
+	/*
+	 * Grab lock in order to send commands to the L2 cache in a serialized fashion.
+	 * The L2 cache will ignore commands if it is busy.
+	 */
+	_mali_osk_lock_wait(cache->lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* First, wait for L2 cache command handler to go idle */
+
+	for (i = 0; i < loop_count; i++)
+	{
+		if (!(_mali_osk_mem_ioread32(cache->mapped_registers , (u32)MALI400_L2_CACHE_REGISTER_STATUS * sizeof(u32)) & (u32)MALI400_L2_CACHE_STATUS_COMMAND_BUSY))
+		{
+			break;
+		}
+	}
+
+	if (i == loop_count)
+	{
+		_mali_osk_lock_signal(cache->lock, _MALI_OSK_LOCKMODE_RW);
+		MALI_DEBUG_PRINT(1, ( "Mali L2 cache: aborting wait for command interface to go idle\n"));
+		MALI_ERROR( _MALI_OSK_ERR_FAULT );
+	}
+
+	/* then issue the command */
+	mali_l2_cache_register_write(cache, reg, val);
+
+	_mali_osk_lock_signal(cache->lock, _MALI_OSK_LOCKMODE_RW);
+	MALI_SUCCESS;
+}
+
+
+static _mali_osk_errcode_t mali_kernel_l2_cache_invalidate_all_cache(mali_kernel_l2_cache_core *cache)
+{
+	return mali_kernel_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND, MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
+}
+
+_mali_osk_errcode_t mali_kernel_l2_cache_invalidate_all(void)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+
+	/* loop over all L2 cache units and invalidate them */
+
+	_MALI_OSK_LIST_FOREACHENTRY( cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list)
+	{
+		MALI_CHECK_NO_ERROR( mali_kernel_l2_cache_invalidate_all_cache(cache) );
+	}
+
+	MALI_SUCCESS;
+}
+
+
+static _mali_osk_errcode_t mali_kernel_l2_cache_invalidate_page_cache(mali_kernel_l2_cache_core *cache, u32 page)
+{
+	return mali_kernel_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_CLEAR_PAGE, page);
+}
+
+_mali_osk_errcode_t mali_kernel_l2_cache_invalidate_page(u32 page)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+
+	/* loop over all L2 cache units and invalidate them */
+
+	_MALI_OSK_LIST_FOREACHENTRY( cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list)
+	{
+		MALI_CHECK_NO_ERROR( mali_kernel_l2_cache_invalidate_page_cache(cache, page) );
+	}
+
+	MALI_SUCCESS;
+}
+
+
+void mali_kernel_l2_cache_set_perf_counters(u32 src0, u32 src1, int force_reset)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+	int reset0 = force_reset;
+	int reset1 = force_reset;
+	MALI_DEBUG_CODE(
+		int changed0 = 0;
+		int changed1 = 0;
+	)
+
+	/* loop over all L2 cache units and activate the counters on them */
+	_MALI_OSK_LIST_FOREACHENTRY(cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list)
+	{
+		u32 cur_src0 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0);
+		u32 cur_src1 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1);
+
+		if (src0 != cur_src0)
+		{
+			mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0, src0);
+			MALI_DEBUG_CODE(changed0 = 1;)
+			reset0 = 1;
+		}
+
+		if (src1 != cur_src1)
+		{
+			mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1, src1);
+			MALI_DEBUG_CODE(changed1 = 1;)
+			reset1 = 1;
+		}
+
+		if (reset0)
+		{
+			mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0, 0);
+		}
+
+		if (reset1)
+		{
+			mali_l2_cache_register_write(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1, 0);
+		}
+
+		MALI_DEBUG_PRINT(5, ("L2 cache counters set: SRC0=%u, CHANGED0=%d, RESET0=%d, SRC1=%u, CHANGED1=%d, RESET1=%d\n",
+			src0, changed0, reset0,
+			src1, changed1, reset1));
+	}
+}
+
+
+void mali_kernel_l2_cache_get_perf_counters(u32 *src0, u32 *val0, u32 *src1, u32 *val1)
+{
+	mali_kernel_l2_cache_core * cache, *temp_cache;
+	int first_time = 1;
+	*src0 = 0;
+	*src1 = 0;
+	*val0 = 0;
+	*val1 = 0;
+
+	/* loop over all L2 cache units and read the counters */
+	_MALI_OSK_LIST_FOREACHENTRY(cache, temp_cache, &caches_head, mali_kernel_l2_cache_core, list)
+	{
+		u32 cur_src0 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0);
+		u32 cur_src1 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1);
+		u32 cur_val0 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0);
+		u32 cur_val1 = mali_l2_cache_register_read(cache, MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1);
+
+		MALI_DEBUG_PRINT(5, ("L2 cache counters get: SRC0=%u, VAL0=%u, SRC1=%u, VAL1=%u\n", cur_src0, cur_val0, cur_src1, cur_val1));
+
+		/* Only update the counter source once, with the value from the first L2 cache unit. */
+		if (first_time)
+		{
+			*src0 = cur_src0;
+			*src1 = cur_src1;
+			first_time = 0;
+		}
+
+		/* Bail out if the L2 cache units have different counters set. */
+		if (*src0 == cur_src0 && *src1 == cur_src1)
+		{
+			*val0 += cur_val0;
+			*val1 += cur_val1;
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(1, ("Warning: Mali L2 caches has different performance counters set, not retrieving data\n"));
+		}
+	}
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.h b/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.h
new file mode 100644
index 0000000..8c12b50
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_l2_cache.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_L2_CACHE_H__
+#define __MALI_KERNEL_L2_CACHE_H__
+
+#include "mali_osk.h"
+#include "mali_kernel_subsystem.h"
+extern struct mali_kernel_subsystem mali_subsystem_l2_cache;
+
+_mali_osk_errcode_t mali_kernel_l2_cache_invalidate_all(void);
+_mali_osk_errcode_t mali_kernel_l2_cache_invalidate_page(u32 page);
+
+void mali_kernel_l2_cache_do_enable(void);
+void mali_kernel_l2_cache_set_perf_counters(u32 src0, u32 src1, int force_reset);
+void mali_kernel_l2_cache_get_perf_counters(u32 *src0, u32 *val0, u32 *src1, u32 *val1);
+
+#endif /* __MALI_KERNEL_L2_CACHE_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem.h b/drivers/media/video/samsung/mali/common/mali_kernel_mem.h
new file mode 100644
index 0000000..8caafe3
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_MEM_H__
+#define __MALI_KERNEL_MEM_H__
+
+#include "mali_kernel_subsystem.h"
+extern struct mali_kernel_subsystem mali_subsystem_memory;
+
+#endif /* __MALI_KERNEL_MEM_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem_buddy.c b/drivers/media/video/samsung/mali/common/mali_kernel_mem_buddy.c
new file mode 100644
index 0000000..e378f03
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem_buddy.c
@@ -0,0 +1,1427 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_core.h"
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_mem.h"
+#include "mali_kernel_descriptor_mapping.h"
+#include "mali_kernel_session_manager.h"
+
+/* kernel side OS functions and user-kernel interface */
+#include "mali_osk.h"
+#include "mali_osk_mali.h"
+#include "mali_osk_list.h"
+#include "mali_ukk.h"
+
+#ifdef _MALI_OSK_SPECIFIC_INDIRECT_MMAP
+#include "mali_osk_indir_mmap.h"
+#endif
+
+#error Support for non-MMU builds is no longer supported and is planned for removal.
+
+/**
+ * Minimum memory allocation size
+ */
+#define MIN_BLOCK_SIZE (1024*1024UL)
+
+/**
+ * Per-session memory descriptor mapping table sizes
+ */
+#define MALI_MEM_DESCRIPTORS_INIT 64
+#define MALI_MEM_DESCRIPTORS_MAX 4096
+
+/**
+ * Enum uses to store multiple fields in one u32 to keep the memory block struct small
+ */
+enum MISC_SHIFT { MISC_SHIFT_FREE = 0, MISC_SHIFT_ORDER = 1, MISC_SHIFT_TOPLEVEL = 6 };
+enum MISC_MASK { MISC_MASK_FREE = 0x01, MISC_MASK_ORDER = 0x1F, MISC_MASK_TOPLEVEL = 0x1F };
+
+/* forward declaration of the block struct */
+struct mali_memory_block;
+
+/**
+ * Definition of memory bank type.
+ * Represents a memory bank (separate address space)
+ * Each bank keeps track of its block usage.
+ * A buddy system used to track the usage
+*/
+typedef struct mali_memory_bank
+{
+	_mali_osk_list_t list; /* links multiple banks together */
+	_mali_osk_lock_t *lock;
+	u32 base_addr; /* Mali seen address of bank */
+	u32 cpu_usage_adjust; /* Adjustment factor for what the CPU sees */
+	u32 size; /* the effective size */
+	u32 real_size; /* the real size of the bank, as given by to the subsystem */
+	int min_order;
+	int max_order;
+	struct mali_memory_block * blocklist;
+	_mali_osk_list_t *freelist;
+	_mali_osk_atomic_t num_active_allocations;
+	u32 used_for_flags;
+	u32 alloc_order; /**< Order in which the bank will be used for allocations */
+	const char *name; /**< Descriptive name of the bank */
+} mali_memory_bank;
+
+/**
+ * Definition of the memory block type
+ * Represents a memory block, which is the smallest memory unit operated on.
+ * A block keeps info about its mapping, if in use by a user process
+ */
+typedef struct mali_memory_block
+{
+	_mali_osk_list_t link; /* used for freelist and process usage list*/
+	mali_memory_bank * bank; /* the bank it belongs to */
+	void __user * mapping; /* possible user space mapping of this block */
+	u32 misc; /* used while a block is free to track the number blocks it represents */
+	int descriptor;
+	u32 mmap_cookie; /**< necessary for interaction with _mali_ukk_mem_mmap/munmap */
+} mali_memory_block;
+
+/**
+ * Defintion of the type used to represent memory used by a session.
+ * Containts the head of the list of memory currently in use by a session.
+ */
+typedef struct memory_session
+{
+	_mali_osk_lock_t *lock;
+	_mali_osk_list_t memory_head; /* List of the memory blocks used by this session. */
+	mali_descriptor_mapping * descriptor_mapping; /**< Mapping between userspace descriptors and our pointers */
+} memory_session;
+
+/*
+	Subsystem interface implementation
+*/
+/**
+ * Buddy block memory subsystem startup function
+ * Called by the driver core when the driver is loaded.
+ * Registers the memory systems ioctl handler, resource handlers and memory map function with the core.
+ *
+ * @param id Identifier assigned by the core to the memory subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_initialize(mali_kernel_subsystem_identifier id);
+
+/**
+ * Buddy block memory subsystem shutdown function
+ * Called by the driver core when the driver is unloaded.
+ * Cleans up
+ * @param id Identifier assigned by the core to the memory subsystem
+ */
+static void mali_memory_core_terminate(mali_kernel_subsystem_identifier id);
+
+/**
+ * Buddy block memory load complete notification function.
+ * Called by the driver core when all drivers have loaded and all resources has been registered
+ * Reports on the memory resources registered
+ * @param id Identifier assigned by the core to the memory subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_load_complete(mali_kernel_subsystem_identifier id);
+
+
+/**
+ * Buddy block memory subsystem session begin notification
+ * Called by the core when a new session to the driver is started.
+ * Creates a memory session object and sets it as the subsystem slot data for this session
+ * @param slot Pointer to the slot to use for storing per-session data
+ * @param queue The user space event sink
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+
+/**
+ * Buddy block memory subsystem session end notification
+ * Called by the core when a session to the driver has ended.
+ * Cleans up per session data, which includes checking and fixing memory leaks
+ *
+ * @param slot Pointer to the slot to use for storing per-session data
+ */
+static void mali_memory_core_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot);
+
+/**
+ * Buddy block memory subsystem system info filler
+ * Called by the core when a system info update is needed
+ * We fill in info about all the memory types we have
+ * @param info Pointer to system info struct to update
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_system_info_fill(_mali_system_info* info);
+
+/* our registered resource handlers */
+/**
+ * Buddy block memory subsystem's notification handler for MEMORY resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each memory bank described in the active architecture's config.h file.
+ * Requests memory region ownership and calls backend.
+ * @param resource The resource to handle (type MEMORY)
+ * @return 0 if the memory was claimed and accepted, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_resource_memory(_mali_osk_resource_t * resource);
+
+/**
+ * Buddy block memory subsystem's notification handler for MMU resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each mmu described in the active architecture's config.h file.
+ * @param resource The resource to handle (type MMU)
+ * @return 0 if the MMU was found and initialized, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_resource_mmu(_mali_osk_resource_t * resource);
+
+/**
+ * Buddy block memory subsystem's notification handler for FPGA_FRAMEWORK resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each fpga framework described in the active architecture's config.h file.
+ * @param resource The resource to handle (type FPGA_FRAMEWORK)
+ * @return 0 if the FPGA framework was found and initialized, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_resource_fpga(_mali_osk_resource_t * resource);
+
+/* ioctl command implementations */
+/**
+ * Buddy block memory subsystem's handler for MALI_IOC_MEM_GET_BIG_BLOCK ioctl
+ * Called by the generic ioctl handler when the MALI_IOC_MEM_GET_BIG_BLOCK command is received.
+ * Finds an available memory block and maps into the current process' address space.
+ * @param ukk_private private word for use by the User/Kernel interface
+ * @param session_data Pointer to the per-session object which will track the memory usage
+ * @param argument The argument from the user. A pointer to an struct mali_dd_get_big_block in user space
+ * @return Zero if successful, a standard Linux error value value on error (a negative value)
+ */
+_mali_osk_errcode_t _mali_ukk_get_big_block( _mali_uk_get_big_block_s *args );
+
+/**
+ * Buddy block memory subsystem's handler for MALI_IOC_MEM_FREE_BIG_BLOCK ioctl
+ * Called by the generic ioctl handler when the MALI_IOC_MEM_FREE_BIG_BLOCK command is received.
+ * Unmaps the memory from the process' address space and marks the block as free.
+ * @param session_data Pointer to the per-session object which tracks the memory usage
+ * @param argument The argument from the user. A pointer to an struct mali_dd_get_big_block in user space
+ * @return Zero if successful, a standard Linux error value value on error (a negative value)
+ */
+
+/* this static version allows us to make use of it while holding the memory_session lock.
+ * This is required  for the session_end code */
+static _mali_osk_errcode_t _mali_ukk_free_big_block_internal( struct mali_session_data * mali_session_data, memory_session * session_data, _mali_uk_free_big_block_s *args);
+
+_mali_osk_errcode_t _mali_ukk_free_big_block( _mali_uk_free_big_block_s *args );
+
+/**
+ * Buddy block memory subsystem's memory bank registration routine
+ * Called when a MEMORY resource has been found.
+ * The memory region has already been reserved for use by this driver.
+ * Create a bank object to represent this region and initialize its slots.
+ * @note Can only be called in an module atomic scope, i.e. during module init since no locking is performed
+ * @param phys_base Physical base address of this bank
+ * @param cpu_usage_adjust Adjustment factor for CPU seen address
+ * @param size Size of the bank in bytes
+ * @param flags Memory type bits
+ * @param alloc_order Order in which the bank will be used for allocations
+ * @param name descriptive name of the bank
+ * @return Zero on success, negative on error
+ */
+static int mali_memory_bank_register(u32 phys_base, u32 cpu_usage_adjust, u32 size, u32 flags, u32 alloc_order, const char *name);
+
+/**
+ * Get a block of mali memory of at least the given size and of the given type
+ * This is the backend for get_big_block.
+ * @param type_id The type id of memory requested.
+ * @param minimum_size The size requested
+ * @return Pointer to a block on success, NULL on failure
+ */
+static mali_memory_block * mali_memory_block_get(u32 type_id, u32 minimum_size);
+
+/**
+ * Get the mali seen address of the memory described by the block
+ * @param block The memory block to return the address of
+ * @return The mali seen address of the memory block
+ */
+MALI_STATIC_INLINE u32 block_mali_addr_get(mali_memory_block * block);
+
+/**
+ * Get the cpu seen address of the memory described by the block
+ * The cpu_usage_adjust will be used to change the mali seen phys address
+ * @param block The memory block to return the address of
+ * @return The mali seen address of the memory block
+ */
+MALI_STATIC_INLINE u32 block_cpu_addr_get(mali_memory_block * block);
+
+/**
+ * Get the size of the memory described by the given block
+ * @param block The memory block to return the size of
+ * @return The size of the memory block described by the object
+ */
+MALI_STATIC_INLINE u32 block_size_get(mali_memory_block * block);
+
+/**
+ * Get the user space accessible mapping the memory described by the given memory block
+ * Returns a pointer in user space to the memory, if one has been created.
+ * @param block The memory block to return the mapping of
+ * @return User space pointer to cpu accessible memory or NULL if not mapped
+ */
+MALI_STATIC_INLINE void __user * block_mapping_get(mali_memory_block * block);
+
+/**
+ * Set the user space accessible mapping the memory described by the given memory block.
+ * Sets the stored pointer to user space for the memory described by this block.
+ * @param block The memory block to set mapping info for
+ * @param ptr User space pointer to cpu accessible memory or NULL if not mapped
+ */
+MALI_STATIC_INLINE void block_mapping_set(mali_memory_block * block, void __user * ptr);
+
+/**
+ * Get the cookie for use with _mali_ukk_mem_munmap().
+ * @param block The memory block to get the cookie from
+ * @return the cookie. A return of 0 is still a valid cookie.
+ */
+MALI_STATIC_INLINE u32 block_mmap_cookie_get(mali_memory_block * block);
+
+/**
+ * Set the cookie returned via _mali_ukk_mem_mmap().
+ * @param block The memory block to set the cookie for
+ * @param cookie the cookie
+ */
+MALI_STATIC_INLINE void block_mmap_cookie_set(mali_memory_block * block, u32 cookie);
+
+
+/**
+ * Get a memory block's free status
+ * @param block The block to get the state of
+ */
+MALI_STATIC_INLINE u32 get_block_free(mali_memory_block * block);
+
+/**
+ * Set a memory block's free status
+ * @param block The block to set the state for
+ * @param state The state to set
+ */
+MALI_STATIC_INLINE void set_block_free(mali_memory_block * block, int state);
+
+/**
+ * Set a memory block's order
+ * @param block The block to set the order for
+ * @param order The order to set
+ */
+MALI_STATIC_INLINE void set_block_order(mali_memory_block * block, u32 order);
+
+/**
+ * Get a memory block's order
+ * @param block The block to get the order for
+ * @return The order this block exists on
+ */
+MALI_STATIC_INLINE u32 get_block_order(mali_memory_block * block);
+
+/**
+ * Tag a block as being a toplevel block.
+ * A toplevel block has no buddy and no parent
+ * @param block The block to tag as being toplevel
+ */
+MALI_STATIC_INLINE void set_block_toplevel(mali_memory_block * block, u32 level);
+
+/**
+ * Check if a block is a toplevel block
+ * @param block The block to check
+ * @return 1 if toplevel, 0 else
+ */
+MALI_STATIC_INLINE u32 get_block_toplevel(mali_memory_block * block);
+
+/**
+ * Checks if the given block is a buddy at the given order and that it's free
+ * @param block The block to check
+ * @param order The order to check against
+ * @return 0 if not valid, else 1
+ */
+MALI_STATIC_INLINE int block_is_valid_buddy(mali_memory_block * block, int order);
+
+/*
+ The buddy system uses the following rules to quickly find a blocks buddy
+ and parent (block representing this block at a higher order level):
+ - Given a block with index i the blocks buddy is at index i ^ ( 1 << order)
+ - Given a block with index i the blocks parent is at i & ~(1 << order)
+*/
+
+/**
+ * Get a blocks buddy
+ * @param block The block to find the buddy for
+ * @param order The order to operate on
+ * @return Pointer to the buddy block
+ */
+MALI_STATIC_INLINE mali_memory_block * block_get_buddy(mali_memory_block * block, u32 order);
+
+/**
+ * Get a blocks parent
+ * @param block The block to find the parent for
+ * @param order The order to operate on
+ * @return Pointer to the parent block
+ */
+MALI_STATIC_INLINE mali_memory_block * block_get_parent(mali_memory_block * block, u32 order);
+
+/**
+ * Release mali memory
+ * Backend for free_big_block.
+ * Will release the mali memory described by the given block struct.
+ * @param block Memory block to free
+ */
+static void block_release(mali_memory_block * block);
+
+/* end interface implementation */
+
+/**
+ * List of all the memory banks registerd with the subsystem.
+ * Access to this list is NOT synchronized since it's only
+ * written to during module init and termination.
+ */
+static _MALI_OSK_LIST_HEAD(memory_banks_list);
+
+/*
+	The buddy memory system's mali subsystem interface implementation.
+	We currently handle module and session life-time management.
+*/
+struct mali_kernel_subsystem mali_subsystem_memory =
+{
+	mali_memory_core_initialize,                /* startup */
+	NULL, /*mali_memory_core_terminate,*/                 /* shutdown */
+    mali_memory_core_load_complete,             /* load_complete */
+	mali_memory_core_system_info_fill,          /* system_info_fill */
+    mali_memory_core_session_begin,             /* session_begin */
+	mali_memory_core_session_end,               /* session_end */
+    NULL,                                       /* broadcast_notification */
+#if MALI_STATE_TRACKING
+	NULL,                                       /* dump_state */
+#endif
+};
+
+/* Initialized when this subsystem is initialized. This is determined by the
+ * position in subsystems[], and so the value used to initialize this is
+ * determined at compile time */
+static mali_kernel_subsystem_identifier mali_subsystem_memory_id = -1;
+
+/* called during module init */
+static _mali_osk_errcode_t mali_memory_core_initialize(mali_kernel_subsystem_identifier id)
+{
+    _MALI_OSK_INIT_LIST_HEAD(&memory_banks_list);
+
+	mali_subsystem_memory_id = id;
+
+	/* register our handlers */
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MEMORY, mali_memory_core_resource_memory));
+
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(MMU, mali_memory_core_resource_mmu));
+
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(FPGA_FRAMEWORK, mali_memory_core_resource_fpga));
+
+	MALI_SUCCESS;
+}
+
+/* called if/when our module is unloaded */
+static void mali_memory_core_terminate(mali_kernel_subsystem_identifier id)
+{
+	mali_memory_bank * bank, *temp;
+
+	/* loop over all memory banks to free them */
+	/* we use the safe version since we delete the current bank in the body */
+	_MALI_OSK_LIST_FOREACHENTRY(bank, temp, &memory_banks_list, mali_memory_bank, list)
+	{
+		MALI_DEBUG_CODE(int usage_count = _mali_osk_atomic_read(&bank->num_active_allocations));
+ 		/*
+			Report leaked memory
+			If this happens we have a bug in our session cleanup code.
+		*/
+		MALI_DEBUG_PRINT_IF(1, 0 != usage_count,  ("%d allocation(s) from memory bank at 0x%X still in use\n", usage_count, bank->base_addr));
+
+        _mali_osk_atomic_term(&bank->num_active_allocations);
+
+	    _mali_osk_lock_term(bank->lock);
+
+        /* unlink from bank list */
+		_mali_osk_list_del(&bank->list);
+
+		/* release kernel resources used by the bank */
+		_mali_osk_mem_unreqregion(bank->base_addr, bank->real_size);
+
+		/* remove all resources used to represent this bank*/
+		_mali_osk_free(bank->freelist);
+		_mali_osk_free(bank->blocklist);
+
+		/* destroy the bank object itself */
+		_mali_osk_free(bank);
+	}
+
+	/* No need to de-initialize mali_subsystem_memory_id - it could only be
+	 * re-initialized to the same value */
+}
+
+/* load_complete handler */
+static _mali_osk_errcode_t mali_memory_core_load_complete(mali_kernel_subsystem_identifier id)
+{
+	mali_memory_bank * bank, *temp;
+
+	MALI_DEBUG_PRINT( 1, ("Mali memory allocators will be used in this order of preference (lowest number first) :\n"));
+
+	_MALI_OSK_LIST_FOREACHENTRY(bank, temp, &memory_banks_list, mali_memory_bank, list)
+	{
+		if ( NULL != bank->name )
+		{
+			MALI_DEBUG_PRINT( 1, ("\t%d: %s\n", bank->alloc_order, bank->name) );
+		}
+		else
+		{
+			MALI_DEBUG_PRINT( 1, ("\t%d: (UNNAMED ALLOCATOR)\n", bank->alloc_order ) );
+		}
+	}
+	MALI_SUCCESS;
+}
+
+MALI_STATIC_INLINE u32 order_needed_for_size(u32 size, struct mali_memory_bank * bank)
+{
+    u32 order = 0;
+
+    if (0 < size)
+    {
+        for ( order = sizeof(u32)*8 - 1; ((1UL<<order) & size) == 0; --order)
+            /* nothing */;
+
+        /* check if size is pow2, if not we need increment order by one */
+        if (0 != (size & ((1UL<<order)-1))) ++order;
+    }
+
+    if ((NULL != bank) && (order < bank->min_order)) order = bank->min_order;
+    /* Not capped to max order, that doesn't make sense */
+
+    return order;
+}
+
+MALI_STATIC_INLINE u32 maximum_order_which_fits(u32 size)
+{
+	u32 order = 0;
+	u32 powsize = 1;
+	while (powsize < size)
+	{
+		powsize <<= 1;
+		if (powsize > size) break;
+		order++;
+	}
+
+	return order;
+}
+
+/* called for new MEMORY resources */
+static _mali_osk_errcode_t mali_memory_bank_register(u32 phys_base, u32 cpu_usage_adjust, u32 size, u32 flags, u32 alloc_order, const char *name)
+{
+	/* no locking performed due to function contract */
+	int i;
+	u32 left, offset;
+	mali_memory_bank * bank;
+	mali_memory_bank * bank_enum, *temp;
+
+    _mali_osk_errcode_t err;
+
+	/* Only a multiple of MIN_BLOCK_SIZE is usable */
+	u32 usable_size = size & ~(MIN_BLOCK_SIZE - 1);
+
+	/* handle zero sized banks and bank smaller than the fixed block size */
+	if (0 == usable_size)
+	{
+		MALI_PRINT(("Usable size == 0\n"));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	/* warn for banks not a muliple of the block size  */
+	MALI_DEBUG_PRINT_IF(1, usable_size != size, ("Memory bank @ 0x%X not a multiple of minimum block size. %d bytes wasted\n", phys_base, size - usable_size));
+
+	/* check against previous registrations */
+	MALI_DEBUG_CODE(
+        {
+		    _MALI_OSK_LIST_FOREACHENTRY(bank, temp, &memory_banks_list, mali_memory_bank, list)
+		    {
+			    /* duplicate ? */
+			    if (bank->base_addr == phys_base)
+			    {
+				    MALI_PRINT(("Duplicate registration of a memory bank at 0x%X detected\n", phys_base));
+				    MALI_ERROR(_MALI_OSK_ERR_FAULT);
+			    }
+			    /* overlapping ? */
+			    else if (
+						    ( (phys_base > bank->base_addr) && (phys_base < (bank->base_addr + bank->real_size)) ) ||
+						    ( (phys_base + size) > bank->base_addr && ((phys_base + size) < (bank->base_addr + bank->real_size)) )
+					    )
+			    {
+				    MALI_PRINT(("Overlapping memory blocks found. Memory at 0x%X overlaps with memory at 0x%X size 0x%X\n", bank->base_addr, phys_base, size));
+				    MALI_ERROR(_MALI_OSK_ERR_FAULT);
+			    }
+		    }
+        }
+	);
+
+	/* create an object to represent this memory bank */
+	MALI_CHECK_NON_NULL(bank = (mali_memory_bank*)_mali_osk_malloc(sizeof(mali_memory_bank)), _MALI_OSK_ERR_NOMEM);
+
+	/* init the fields */
+	_MALI_OSK_INIT_LIST_HEAD(&bank->list);
+	bank->base_addr = phys_base;
+	bank->cpu_usage_adjust = cpu_usage_adjust;
+	bank->size = usable_size;
+	bank->real_size = size;
+	bank->alloc_order = alloc_order;
+	bank->name = name;
+
+    err = _mali_osk_atomic_init(&bank->num_active_allocations, 0);
+    if (err != _MALI_OSK_ERR_OK)
+    {
+		_mali_osk_free(bank);
+        MALI_ERROR(err);
+    }
+
+	bank->used_for_flags = flags;
+	bank->min_order = order_needed_for_size(MIN_BLOCK_SIZE, NULL);
+	bank->max_order = maximum_order_which_fits(usable_size);
+	bank->lock = _mali_osk_lock_init((_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_SPINLOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE), 0, 0);
+    if (NULL == bank->lock)
+    {
+        _mali_osk_atomic_term(&bank->num_active_allocations);
+		_mali_osk_free(bank);
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+    }
+
+	bank->blocklist = _mali_osk_calloc(1, sizeof(struct mali_memory_block) * (usable_size / MIN_BLOCK_SIZE));
+	if (NULL == bank->blocklist)
+	{
+        _mali_osk_lock_term(bank->lock);
+        _mali_osk_atomic_term(&bank->num_active_allocations);
+		_mali_osk_free(bank);
+        MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	for (i = 0; i < (usable_size / MIN_BLOCK_SIZE); i++)
+	{
+		bank->blocklist[i].bank = bank;
+	}
+
+	bank->freelist = _mali_osk_calloc(1, sizeof(_mali_osk_list_t) * (bank->max_order - bank->min_order + 1));
+	if (NULL == bank->freelist)
+	{
+        _mali_osk_lock_term(bank->lock);
+		_mali_osk_free(bank->blocklist);
+        _mali_osk_atomic_term(&bank->num_active_allocations);
+		_mali_osk_free(bank);
+        MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	for (i = 0; i < (bank->max_order - bank->min_order + 1); i++) _MALI_OSK_INIT_LIST_HEAD(&bank->freelist[i]);
+
+	/* init slot info */
+	for (offset = 0, left = usable_size; offset < (usable_size / MIN_BLOCK_SIZE); /* updated inside the body */)
+	{
+		u32 block_order;
+		mali_memory_block * block;
+
+		/* the maximum order which fits in the remaining area */
+		block_order = maximum_order_which_fits(left);
+
+		/* find the block pointer */
+		block = &bank->blocklist[offset];
+
+		/* tag the block as being toplevel */
+		set_block_toplevel(block, block_order);
+
+		/* tag it as being free */
+		set_block_free(block, 1);
+
+		/* set the order */
+		set_block_order(block, block_order);
+
+		_mali_osk_list_addtail(&block->link, bank->freelist + (block_order - bank->min_order));
+
+		left -= (1 << block_order);
+		offset += ((1 << block_order) / MIN_BLOCK_SIZE);
+	}
+
+	/* add bank to list of banks on the system */
+	_MALI_OSK_LIST_FOREACHENTRY( bank_enum, temp, &memory_banks_list, mali_memory_bank, list )
+	{
+		if ( bank_enum->alloc_order >= alloc_order )
+		{
+			/* Found insertion point - our item must go before this one */
+			break;
+		}
+	}
+    _mali_osk_list_addtail(&bank->list, &bank_enum->list);
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_memory_mmu_register(u32 type, u32 phys_base)
+{
+	/* not supported */
+	return _MALI_OSK_ERR_INVALID_FUNC;
+}
+
+void mali_memory_mmu_unregister(u32 phys_base)
+{
+	/* not supported */
+	return;
+}
+
+static mali_memory_block * mali_memory_block_get(u32 type_id, u32 minimum_size)
+{
+	mali_memory_bank * bank;
+	mali_memory_block * block = NULL;
+	u32 requested_order, current_order;
+
+	/* input validation */
+	if (0 == minimum_size)
+	{
+		/* bad size */
+		MALI_DEBUG_PRINT(2, ("Zero size block requested by mali_memory_block_get\n"));
+		return NULL;
+	}
+
+	bank = (mali_memory_bank*)type_id;
+
+	requested_order = order_needed_for_size(minimum_size, bank);
+
+	MALI_DEBUG_PRINT(4, ("For size %d we need order %d (%d)\n", minimum_size, requested_order, 1 << requested_order));
+
+	_mali_osk_lock_wait(bank->lock, _MALI_OSK_LOCKMODE_RW);
+	/* ! critical section begin */
+
+	MALI_DEBUG_PRINT(7, ("Bank 0x%x locked\n", bank));
+
+	for (current_order = requested_order; current_order <= bank->max_order; ++current_order)
+	{
+		_mali_osk_list_t * list = bank->freelist + (current_order - bank->min_order);
+		MALI_DEBUG_PRINT(7, ("Checking freelist 0x%x for order %d\n", list, current_order));
+		if (0 != _mali_osk_list_empty(list)) continue; /* empty list */
+
+		MALI_DEBUG_PRINT(7, ("Found an entry on the freelist for order %d\n", current_order));
+
+
+		block = _MALI_OSK_LIST_ENTRY(list->next, mali_memory_block, link);
+		_mali_osk_list_delinit(&block->link);
+
+		while (current_order > requested_order)
+		{
+			mali_memory_block * buddy_block;
+			MALI_DEBUG_PRINT(7, ("Splitting block 0x%x\n", block));
+			current_order--;
+			list--;
+			buddy_block = block_get_buddy(block, current_order - bank->min_order);
+			set_block_order(buddy_block, current_order);
+			set_block_free(buddy_block, 1);
+			_mali_osk_list_add(&buddy_block->link, list);
+		}
+
+		set_block_order(block, current_order);
+		set_block_free(block, 0);
+
+		/* update usage count */
+		_mali_osk_atomic_inc(&bank->num_active_allocations);
+
+		break;
+	}
+
+	/* ! critical section end */
+	_mali_osk_lock_signal(bank->lock, _MALI_OSK_LOCKMODE_RW);
+
+	MALI_DEBUG_PRINT(7, ("Lock released for bank 0x%x\n", bank));
+
+	MALI_DEBUG_PRINT_IF(7, NULL != block, ("Block 0x%x allocated\n", block));
+
+	return block;
+}
+
+
+static void block_release(mali_memory_block * block)
+{
+	mali_memory_bank * bank;
+	u32 current_order;
+
+	if (NULL == block) return;
+
+	bank = block->bank;
+
+	/* we're manipulating the free list, so we need to lock it */
+	_mali_osk_lock_wait(bank->lock, _MALI_OSK_LOCKMODE_RW);
+	/* ! critical section begin */
+
+	set_block_free(block, 1);
+	current_order = get_block_order(block);
+
+	while (current_order <= bank->max_order)
+	{
+		mali_memory_block * buddy_block;
+		buddy_block = block_get_buddy(block, current_order - bank->min_order);
+		if (!block_is_valid_buddy(buddy_block, current_order)) break;
+		_mali_osk_list_delinit(&buddy_block->link); /* remove from free list */
+		/* clear tracked data in both blocks */
+		set_block_order(block, 0);
+		set_block_free(block, 0);
+		set_block_order(buddy_block, 0);
+		set_block_free(buddy_block, 0);
+		/* make the parent control the new state */
+		block = block_get_parent(block, current_order - bank->min_order);
+		set_block_order(block, current_order + 1); /* merged has a higher order */
+		set_block_free(block, 1); /* mark it as free */
+		current_order++;
+ 		if (get_block_toplevel(block) == current_order) break; /* stop the merge if we've arrived at a toplevel block */
+	}
+
+	_mali_osk_list_add(&block->link, &bank->freelist[current_order - bank->min_order]);
+
+	/* update bank usage statistics */
+	_mali_osk_atomic_dec(&block->bank->num_active_allocations);
+
+	/* !critical section end */
+	_mali_osk_lock_signal(bank->lock, _MALI_OSK_LOCKMODE_RW);
+
+	return;
+}
+
+MALI_STATIC_INLINE u32 block_get_offset(mali_memory_block * block)
+{
+	return block - block->bank->blocklist;
+}
+
+MALI_STATIC_INLINE u32 block_mali_addr_get(mali_memory_block * block)
+{
+	if (NULL != block) return block->bank->base_addr + MIN_BLOCK_SIZE * block_get_offset(block);
+	else return 0;
+}
+
+MALI_STATIC_INLINE u32 block_cpu_addr_get(mali_memory_block * block)
+{
+	if (NULL != block) return (block->bank->base_addr + MIN_BLOCK_SIZE * block_get_offset(block)) + block->bank->cpu_usage_adjust;
+	else return 0;
+}
+
+MALI_STATIC_INLINE u32 block_size_get(mali_memory_block * block)
+{
+	if (NULL != block) return 1 << get_block_order(block);
+	else return 0;
+}
+
+MALI_STATIC_INLINE void __user * block_mapping_get(mali_memory_block * block)
+{
+	if (NULL != block) return block->mapping;
+	else return NULL;
+}
+
+MALI_STATIC_INLINE void block_mapping_set(mali_memory_block * block, void __user * ptr)
+{
+	if (NULL != block) block->mapping = ptr;
+}
+
+MALI_STATIC_INLINE u32 block_mmap_cookie_get(mali_memory_block * block)
+{
+	if (NULL != block) return block->mmap_cookie;
+	else return 0;
+}
+
+/**
+ * Set the cookie returned via _mali_ukk_mem_mmap().
+ * @param block The memory block to set the cookie for
+ * @param cookie the cookie
+ */
+MALI_STATIC_INLINE void block_mmap_cookie_set(mali_memory_block * block, u32 cookie)
+{
+	if (NULL != block) block->mmap_cookie = cookie;
+}
+
+
+static _mali_osk_errcode_t mali_memory_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue)
+{
+	memory_session * session_data;
+
+	/* validate input */
+	if (NULL == slot)
+	{
+		MALI_DEBUG_PRINT(1, ("NULL slot given to memory session begin\n"));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	if (NULL != *slot)
+	{
+		MALI_DEBUG_PRINT(1, ("The slot given to memory session begin already contains data"));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	/* create the session data object */
+	MALI_CHECK_NON_NULL(session_data = _mali_osk_malloc(sizeof(memory_session)), _MALI_OSK_ERR_NOMEM);
+
+	/* create descriptor mapping table */
+	session_data->descriptor_mapping = mali_descriptor_mapping_create(MALI_MEM_DESCRIPTORS_INIT, MALI_MEM_DESCRIPTORS_MAX);
+
+    if (NULL == session_data->descriptor_mapping)
+	{
+		_mali_osk_free(session_data);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	_MALI_OSK_INIT_LIST_HEAD(&session_data->memory_head); /* no memory in use */
+	session_data->lock = _mali_osk_lock_init((_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_ONELOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE), 0, 0);
+    if (NULL == session_data->lock)
+    {
+		_mali_osk_free(session_data);
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+    }
+
+	*slot = session_data; /* slot will point to our data object */
+
+	MALI_SUCCESS;
+}
+
+static void mali_memory_core_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot)
+{
+	memory_session * session_data;
+
+	/* validate input */
+	if (NULL == slot)
+	{
+		MALI_DEBUG_PRINT(1, ("NULL slot given to memory session begin\n"));
+		return;
+	}
+
+	if (NULL == *slot)
+	{
+		MALI_DEBUG_PRINT(1, ("NULL memory_session found in current session object"));
+		return;
+	}
+
+	_mali_osk_lock_wait(((memory_session*)*slot)->lock, _MALI_OSK_LOCKMODE_RW);
+	session_data = (memory_session *)*slot;
+	 /* clear our slot */
+        *slot = NULL;
+
+	/*
+		First free all memory still being used.
+		This can happen if the caller has leaked memory or
+		the application has crashed forcing an auto-session end.
+	*/
+	if (0 == _mali_osk_list_empty(&session_data->memory_head))
+	{
+		mali_memory_block * block, * temp;
+		MALI_DEBUG_PRINT(1, ("Memory found on session usage list during session termination\n"));
+
+		/* use the _safe version since fre_big_block removes the active block from the list we're iterating */
+		_MALI_OSK_LIST_FOREACHENTRY(block, temp, &session_data->memory_head, mali_memory_block, link)
+		{
+			_mali_osk_errcode_t err;
+			_mali_uk_free_big_block_s uk_args;
+
+			MALI_DEBUG_PRINT(4, ("Freeing block 0x%x with mali address 0x%x size %d mapped in user space at 0x%x\n",
+						block,
+						(void*)block_mali_addr_get(block),
+						block_size_get(block),
+						block_mapping_get(block))
+				   	);
+
+			/* free the block */
+			/** @note manual type safety check-point */
+    		uk_args.ctx = mali_session_data;
+			uk_args.cookie = (u32)block->descriptor;
+			err = _mali_ukk_free_big_block_internal( mali_session_data, session_data, &uk_args );
+
+			if ( _MALI_OSK_ERR_OK != err )
+			{
+				MALI_DEBUG_PRINT_ERROR(("_mali_ukk_free_big_block_internal() failed during session termination on block with cookie==0x%X\n",
+										uk_args.cookie)
+									   );
+			}
+		}
+	}
+
+	if (NULL != session_data->descriptor_mapping)
+	{
+		mali_descriptor_mapping_destroy(session_data->descriptor_mapping);
+		session_data->descriptor_mapping = NULL;
+	}
+
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_lock_term(session_data->lock);
+
+    /* free the session data object */
+	_mali_osk_free(session_data);
+
+	return;
+}
+
+static _mali_osk_errcode_t mali_memory_core_system_info_fill(_mali_system_info* info)
+{
+	mali_memory_bank * bank, *temp;
+	_mali_mem_info **mem_info_tail;
+
+	/* check input */
+    MALI_CHECK_NON_NULL(info, _MALI_OSK_ERR_INVALID_ARGS);
+
+	/* make sure we won't leak any memory. It could also be that it's an uninitialized variable, but that would be a bug in the caller */
+	MALI_DEBUG_ASSERT(NULL == info->mem_info);
+
+	mem_info_tail = &info->mem_info;
+
+	_MALI_OSK_LIST_FOREACHENTRY(bank, temp, &memory_banks_list, mali_memory_bank, list)
+	{
+		_mali_mem_info * mem_info;
+
+        mem_info = (_mali_mem_info *)_mali_osk_calloc(1, sizeof(_mali_mem_info));
+		if (NULL == mem_info) return _MALI_OSK_ERR_NOMEM; /* memory already allocated will be freed by the caller */
+
+		/* set info */
+		mem_info->size = bank->size;
+		mem_info->flags = (_mali_bus_usage)bank->used_for_flags;
+		mem_info->maximum_order_supported = bank->max_order;
+		mem_info->identifier = (u32)bank;
+
+		/* add to system info linked list */
+		(*mem_info_tail) = mem_info;
+		mem_info_tail = &mem_info->next;
+	}
+
+	/* all OK */
+    MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_memory(_mali_osk_resource_t * resource)
+{
+	_mali_osk_errcode_t err;
+
+    /* Request ownership of the memory */
+	if (_MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(resource->base, resource->size, resource->description))
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to request memory region %s (0x%08X - 0x%08X)\n", resource->description, resource->base, resource->base + resource->size - 1));
+        MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	/* call backend */
+	err = mali_memory_bank_register(resource->base, resource->cpu_usage_adjust, resource->size, resource->flags, resource->alloc_order, resource->description);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		/* if backend refused the memory we have to release the region again */
+		MALI_DEBUG_PRINT(1, ("Memory bank registration failed\n"));
+		_mali_osk_mem_unreqregion(resource->base, resource->size);
+        MALI_ERROR(err);
+	}
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_mmu(_mali_osk_resource_t * resource)
+{
+	/* Not supported by the fixed block memory system */
+	MALI_DEBUG_PRINT(1, ("MMU resource not supported by non-MMU driver!\n"));
+	MALI_ERROR(_MALI_OSK_ERR_INVALID_FUNC);
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_fpga(_mali_osk_resource_t * resource)
+{
+	mali_io_address mapping;
+
+	MALI_DEBUG_PRINT(5, ("FPGA framework '%s' @ (0x%08X - 0x%08X)\n",
+			resource->description, resource->base, resource->base + sizeof(u32) * 2 - 1
+		   ));
+
+	mapping = _mali_osk_mem_mapioregion(resource->base + 0x1000, sizeof(u32) * 2, "fpga framework");
+	if (mapping)
+	{
+		u32 data;
+		data = _mali_osk_mem_ioread32(mapping, 0);
+		MALI_DEBUG_PRINT(2, ("FPGA framwork '%s' @ 0x%08X:\n", resource->description, resource->base));
+		MALI_DEBUG_PRINT(2, ("\tBitfile date: %d%02d%02d_%02d%02d\n",
+					  (data >> 20),
+					  (data >> 16) & 0xF,
+					  (data >> 11) & 0x1F,
+					  (data >> 6)  & 0x1F,
+					  (data >> 0)  & 0x3F));
+		data = _mali_osk_mem_ioread32(mapping, sizeof(u32));
+		MALI_DEBUG_PRINT(2, ("\tBitfile SCCS rev: %d\n", data));
+
+		_mali_osk_mem_unmapioregion(resource->base + 0x1000, sizeof(u32) *2, mapping);
+	}
+	else MALI_DEBUG_PRINT(1, ("Failed to access FPGA framwork '%s' @ 0x%08X\n", resource->description, resource->base));
+
+	MALI_SUCCESS;
+}
+
+/* static _mali_osk_errcode_t get_big_block(void * ukk_private, struct mali_session_data * mali_session_data, void __user * argument) */
+_mali_osk_errcode_t _mali_ukk_get_big_block( _mali_uk_get_big_block_s *args )
+{
+	_mali_uk_mem_mmap_s args_mmap = {0, };
+	int md;
+	mali_memory_block * block;
+	_mali_osk_errcode_t err;
+	memory_session * session_data;
+
+	MALI_DEBUG_ASSERT_POINTER( args );
+
+	MALI_DEBUG_ASSERT_POINTER( args->ctx );
+
+	/** @note manual type safety check-point */
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+    if (!args->type_id)
+	{
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* at least min block size */
+	if (MIN_BLOCK_SIZE > args->minimum_size_requested) args->minimum_size_requested = MIN_BLOCK_SIZE;
+
+	/* perform the actual allocation */
+	block = mali_memory_block_get(args->type_id, args->minimum_size_requested);
+	if ( NULL == block )
+	{
+		/* no memory available with requested type_id */
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+    if (_MALI_OSK_ERR_OK != mali_descriptor_mapping_allocate_mapping(session_data->descriptor_mapping, block, &md))
+    {
+		block_release(block);
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+       MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+	block->descriptor = md;
+
+
+	/* fill in response */
+	args->mali_address = block_mali_addr_get(block);
+	args->block_size = block_size_get(block);
+	args->cookie = (u32)md;
+	args->flags = block->bank->used_for_flags;
+
+	/* map the block into the process' address space */
+
+	/** @note manual type safety check-point */
+	args_mmap.ukk_private = (void *)args->ukk_private;
+	args_mmap.ctx = args->ctx;
+	args_mmap.size = args->block_size;
+	args_mmap.phys_addr = block_cpu_addr_get(block);
+
+#ifndef _MALI_OSK_SPECIFIC_INDIRECT_MMAP
+	err = _mali_ukk_mem_mmap( &args_mmap );
+#else
+	err = _mali_osk_specific_indirect_mmap( &args_mmap );
+#endif
+
+	/* check if the mapping failed */
+	if ( _MALI_OSK_ERR_OK != err )
+	{
+		MALI_DEBUG_PRINT(1, ("Memory mapping failed 0x%x\n", args->cpuptr));
+		/* mapping failed */
+
+		/* remove descriptor entry */
+		mali_descriptor_mapping_free(session_data->descriptor_mapping, md);
+
+		/* free the mali memory */
+		block_release(block);
+
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+        return err;
+	}
+
+	args->cpuptr = args_mmap.mapping;
+	block_mmap_cookie_set(block, args_mmap.cookie);
+	block_mapping_set(block, args->cpuptr);
+
+	MALI_DEBUG_PRINT(2, ("Mali memory 0x%x (size %d) mapped in process memory space at 0x%x\n", (void*)args->mali_address, args->block_size, args->cpuptr));
+
+	/* track memory in use for the session */
+	_mali_osk_list_addtail(&block->link, &session_data->memory_head);
+
+	/* memory assigned to the session, memory mapped into the process' view */
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	MALI_SUCCESS;
+}
+
+/* Internal code that assumes the memory session lock is held */
+static _mali_osk_errcode_t _mali_ukk_free_big_block_internal( struct mali_session_data * mali_session_data, memory_session * session_data, _mali_uk_free_big_block_s *args)
+{
+	mali_memory_block * block = NULL;
+	_mali_osk_errcode_t err;
+	_mali_uk_mem_munmap_s args_munmap = {0,};
+
+	MALI_DEBUG_ASSERT_POINTER( mali_session_data );
+	MALI_DEBUG_ASSERT_POINTER( session_data );
+	MALI_DEBUG_ASSERT_POINTER( args );
+
+	err = mali_descriptor_mapping_get(session_data->descriptor_mapping, (int)args->cookie, (void**)&block);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		MALI_DEBUG_PRINT(1, ("Invalid memory descriptor %d used to release memory pages\n", (int)args->cookie));
+		MALI_ERROR(err);
+	}
+
+    MALI_DEBUG_ASSERT_POINTER(block);
+
+	MALI_DEBUG_PRINT(4, ("Asked to free block 0x%x with mali address 0x%x size %d mapped in user space at 0x%x\n",
+			block,
+			(void*)block_mali_addr_get(block),
+			block_size_get(block),
+			block_mapping_get(block))
+		   );
+
+	/** @note manual type safety check-point */
+	args_munmap.ctx = (void*)mali_session_data;
+	args_munmap.mapping = block_mapping_get( block );
+	args_munmap.size = block_size_get( block );
+	args_munmap.cookie = block_mmap_cookie_get( block );
+
+#ifndef _MALI_OSK_SPECIFIC_INDIRECT_MMAP
+		_mali_ukk_mem_munmap( &args_munmap );
+#else
+		_mali_osk_specific_indirect_munmap( &args_munmap );
+#endif
+
+	MALI_DEBUG_PRINT(6, ("Session data 0x%x, lock 0x%x\n", session_data, &session_data->lock));
+
+	/* unlink from session usage list */
+	MALI_DEBUG_PRINT(5, ("unlink from session usage list\n"));
+	_mali_osk_list_delinit(&block->link);
+
+	/* remove descriptor entry */
+	mali_descriptor_mapping_free(session_data->descriptor_mapping, (int)args->cookie);
+
+	/* free the mali memory */
+	block_release(block);
+	MALI_DEBUG_PRINT(5, ("Block freed\n"));
+
+	MALI_SUCCESS;
+}
+
+/* static _mali_osk_errcode_t free_big_block( struct mali_session_data * mali_session_data, void __user * argument) */
+_mali_osk_errcode_t _mali_ukk_free_big_block( _mali_uk_free_big_block_s *args )
+{
+	_mali_osk_errcode_t err;
+	struct mali_session_data * mali_session_data;
+	memory_session * session_data;
+
+	MALI_DEBUG_ASSERT_POINTER( args );
+
+	MALI_DEBUG_ASSERT_POINTER( args->ctx );
+
+	/** @note manual type safety check-point */
+	mali_session_data = (struct mali_session_data *)args->ctx;
+
+	/* Must always verify this, since these are provided by the user */
+    MALI_CHECK_NON_NULL(mali_session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+	session_data = mali_kernel_session_manager_slot_get(mali_session_data, mali_subsystem_memory_id);
+
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	/** @note this has been separated out so that the session_end handler can call this while it has the memory_session lock held */
+	err = _mali_ukk_free_big_block_internal( mali_session_data, session_data, args );
+
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+    return err;
+}
+
+MALI_STATIC_INLINE u32 get_block_free(mali_memory_block * block)
+{
+	return (block->misc >> MISC_SHIFT_FREE) & MISC_MASK_FREE;
+}
+
+MALI_STATIC_INLINE void set_block_free(mali_memory_block * block, int state)
+{
+	if (state) block->misc |= (MISC_MASK_FREE << MISC_SHIFT_FREE);
+	else block->misc &= ~(MISC_MASK_FREE << MISC_SHIFT_FREE);
+}
+
+MALI_STATIC_INLINE void set_block_order(mali_memory_block * block, u32 order)
+{
+	block->misc &= ~(MISC_MASK_ORDER << MISC_SHIFT_ORDER);
+	block->misc |= ((order & MISC_MASK_ORDER) << MISC_SHIFT_ORDER);
+}
+
+MALI_STATIC_INLINE u32 get_block_order(mali_memory_block * block)
+{
+	return (block->misc >> MISC_SHIFT_ORDER) & MISC_MASK_ORDER;
+}
+
+MALI_STATIC_INLINE void set_block_toplevel(mali_memory_block * block, u32 level)
+{
+	block->misc |= ((level & MISC_MASK_TOPLEVEL) << MISC_SHIFT_TOPLEVEL);
+}
+
+MALI_STATIC_INLINE u32 get_block_toplevel(mali_memory_block * block)
+{
+	return (block->misc >> MISC_SHIFT_TOPLEVEL) & MISC_MASK_TOPLEVEL;
+}
+
+MALI_STATIC_INLINE int block_is_valid_buddy(mali_memory_block * block, int order)
+{
+	if (get_block_free(block) && (get_block_order(block) == order)) return 1;
+	else return 0;
+}
+
+MALI_STATIC_INLINE mali_memory_block * block_get_buddy(mali_memory_block * block, u32 order)
+{
+	return block + ( (block_get_offset(block) ^ (1 << order)) - block_get_offset(block));
+}
+
+MALI_STATIC_INLINE mali_memory_block * block_get_parent(mali_memory_block * block, u32 order)
+{
+	return block + ((block_get_offset(block) & ~(1 << order)) - block_get_offset(block));
+}
+
+/* This handler registered to mali_mmap for non-MMU builds */
+_mali_osk_errcode_t _mali_ukk_mem_mmap( _mali_uk_mem_mmap_s *args )
+{
+	_mali_osk_errcode_t ret;
+	struct mali_session_data * mali_session_data;
+	mali_memory_allocation * descriptor;
+	memory_session * session_data;
+
+	/* validate input */
+	if (NULL == args) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: args was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS); }
+
+	/* Unpack arguments */
+	mali_session_data = (struct mali_session_data *)args->ctx;
+
+	if (NULL == mali_session_data) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: mali_session data was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS); }
+
+	MALI_DEBUG_ASSERT( mali_subsystem_memory_id >= 0 );
+
+	session_data = mali_kernel_session_manager_slot_get(mali_session_data, mali_subsystem_memory_id);
+	/* validate input */
+	if (NULL == session_data) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: session data was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_FAULT); }
+
+	descriptor = (mali_memory_allocation*) _mali_osk_calloc( 1, sizeof(mali_memory_allocation) );
+	if (NULL == descriptor) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: descriptor was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_NOMEM); }
+
+	descriptor->size = args->size;
+	descriptor->mali_address = args->phys_addr;
+	descriptor->mali_addr_mapping_info = (void*)session_data;
+	descriptor->process_addr_mapping_info = args->ukk_private; /* save to be used during physical manager callback */
+	descriptor->flags = MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE;
+
+	ret = _mali_osk_mem_mapregion_init( descriptor );
+	if ( _MALI_OSK_ERR_OK != ret )
+	{
+		MALI_DEBUG_PRINT(3, ("_mali_osk_mem_mapregion_init() failed\n"));
+		_mali_osk_free(descriptor);
+        MALI_ERROR(ret);
+	}
+
+	ret = _mali_osk_mem_mapregion_map( descriptor, 0, &descriptor->mali_address, descriptor->size );
+	if ( _MALI_OSK_ERR_OK != ret )
+	{
+		MALI_DEBUG_PRINT(3, ("_mali_osk_mem_mapregion_map() failed\n"));
+		_mali_osk_mem_mapregion_term( descriptor );
+		_mali_osk_free(descriptor);
+        MALI_ERROR(ret);
+	}
+
+	args->mapping = descriptor->mapping;
+
+	/**
+	 * @note we do not require use of mali_descriptor_mapping here:
+	 * the cookie gets stored in the mali_memory_block struct, which itself is
+	 * protected by mali_descriptor_mapping, and so this cookie never leaves
+	 * kernel space (on any OS).
+	 *
+	 * In the MMU case, we must use a mali_descriptor_mapping, since on _some_
+	 * OSs, the cookie leaves kernel space.
+	 */
+	args->cookie = (u32)descriptor;
+    MALI_SUCCESS;
+}
+
+/* This handler registered to mali_munmap for non-MMU builds */
+_mali_osk_errcode_t _mali_ukk_mem_munmap( _mali_uk_mem_munmap_s *args )
+{
+	mali_memory_allocation * descriptor;
+
+	/** see note in _mali_ukk_mem_mmap() - no need to use descriptor mapping */
+	descriptor = (mali_memory_allocation *)args->cookie;
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+	/* args->mapping and args->size are also discarded. They are only necessary for certain do_munmap implementations. However, they could be used to check the descriptor at this point. */
+	_mali_osk_mem_mapregion_unmap( descriptor, 0, descriptor->size, (_mali_osk_mem_mapregion_flags_t)0 );
+
+	_mali_osk_mem_mapregion_term( descriptor );
+
+	_mali_osk_free(descriptor);
+
+	return _MALI_OSK_ERR_OK;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_init_mem( _mali_uk_init_mem_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_term_mem( _mali_uk_term_mem_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_map_external_mem( _mali_uk_map_external_mem_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_unmap_external_mem( _mali_uk_unmap_external_mem_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_query_mmu_page_table_dump_size( _mali_uk_query_mmu_page_table_dump_size_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_dump_mmu_page_table( _mali_uk_dump_mmu_page_table_s * args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.c b/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.c
new file mode 100644
index 0000000..c993ad5
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.c
@@ -0,0 +1,3157 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_mem.h"
+#include "mali_kernel_ioctl.h"
+#include "mali_kernel_descriptor_mapping.h"
+#include "mali_kernel_mem_mmu.h"
+#include "mali_kernel_memory_engine.h"
+#include "mali_block_allocator.h"
+#include "mali_kernel_mem_os.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_rendercore.h"
+
+#if defined USING_MALI400_L2_CACHE
+#include "mali_kernel_l2_cache.h"
+#endif
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+#include "ump_kernel_interface.h"
+#endif
+
+/* kernel side OS functions and user-kernel interface */
+#include "mali_osk.h"
+#include "mali_osk_mali.h"
+#include "mali_ukk.h"
+#include "mali_osk_bitops.h"
+#include "mali_osk_list.h"
+
+/**
+ * Size of the MMU registers in bytes
+ */
+#define MALI_MMU_REGISTERS_SIZE 0x24
+
+/**
+ * Size of an MMU page in bytes
+ */
+#define MALI_MMU_PAGE_SIZE 0x1000
+
+/**
+ * Page directory index from address
+ * Calculates the page directory index from the given address
+ */
+#define MALI_MMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
+
+/**
+ * Page table index from address
+ * Calculates the page table index from the given address
+ */
+#define MALI_MMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
+
+/**
+ * Extract the memory address from an PDE/PTE entry
+ */
+#define MALI_MMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
+
+/**
+ * Calculate memory address from PDE and PTE
+ */
+#define MALI_MMU_ADDRESS(pde, pte) (((pde)<<22) | ((pte)<<12))
+
+/**
+ * Linux kernel version has marked SA_SHIRQ as deprecated, IRQF_SHARED should be used.
+ * This is to handle older kernels which haven't done this swap.
+ */
+#ifndef IRQF_SHARED
+#define IRQF_SHARED SA_SHIRQ
+#endif /* IRQF_SHARED */
+
+/**
+ * Per-session memory descriptor mapping table sizes
+ */
+#define MALI_MEM_DESCRIPTORS_INIT 64
+#define MALI_MEM_DESCRIPTORS_MAX 65536
+
+/**
+ * Used to disallow more than one core to run a MMU at the same time
+ *
+ * @note This value is hardwired into some systems' configuration files,
+ * which \em might not be a header file (e.g. some external data configuration
+ * file). Therefore, if this value is modified, its occurance must be
+ * \b manually checked for in the entire driver source tree.
+ */
+#define MALI_MMU_DISALLOW_PARALLELL_WORK_OF_MALI_CORES 1
+
+#define MALI_INVALID_PAGE ((u32)(~0))
+
+/**
+ *
+ */
+typedef enum mali_mmu_entry_flags
+{
+	MALI_MMU_FLAGS_PRESENT = 0x01,
+	MALI_MMU_FLAGS_READ_PERMISSION = 0x02,
+	MALI_MMU_FLAGS_WRITE_PERMISSION = 0x04,
+	MALI_MMU_FLAGS_MASK = 0x07
+} mali_mmu_entry_flags;
+
+/**
+ * MMU register numbers
+ * Used in the register read/write routines.
+ * See the hardware documentation for more information about each register
+ */
+typedef enum mali_mmu_register {
+	MALI_MMU_REGISTER_DTE_ADDR = 0x0000, /**< Current Page Directory Pointer */
+	MALI_MMU_REGISTER_STATUS = 0x0001, /**< Status of the MMU */
+	MALI_MMU_REGISTER_COMMAND = 0x0002, /**< Command register, used to control the MMU */
+	MALI_MMU_REGISTER_PAGE_FAULT_ADDR = 0x0003, /**< Logical address of the last page fault */
+	MALI_MMU_REGISTER_ZAP_ONE_LINE = 0x004, /**< Used to invalidate the mapping of a single page from the MMU */
+	MALI_MMU_REGISTER_INT_RAWSTAT = 0x0005, /**< Raw interrupt status, all interrupts visible */
+	MALI_MMU_REGISTER_INT_CLEAR = 0x0006, /**< Indicate to the MMU that the interrupt has been received */
+	MALI_MMU_REGISTER_INT_MASK = 0x0007, /**< Enable/disable types of interrupts */
+	MALI_MMU_REGISTER_INT_STATUS = 0x0008 /**< Interrupt status based on the mask */
+} mali_mmu_register;
+
+/**
+ * MMU interrupt register bits
+ * Each cause of the interrupt is reported
+ * through the (raw) interrupt status registers.
+ * Multiple interrupts can be pending, so multiple bits
+ * can be set at once.
+ */
+typedef enum mali_mmu_interrupt
+{
+	MALI_MMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
+	MALI_MMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
+} mali_mmu_interrupt;
+
+/**
+ * MMU commands
+ * These are the commands that can be sent
+ * to the MMU unit.
+ */
+typedef enum mali_mmu_command
+{
+	MALI_MMU_COMMAND_ENABLE_PAGING = 0x00, /**< Enable paging (memory translation) */
+	MALI_MMU_COMMAND_DISABLE_PAGING = 0x01, /**< Disable paging (memory translation) */
+	MALI_MMU_COMMAND_ENABLE_STALL = 0x02, /**<  Enable stall on page fault */
+	MALI_MMU_COMMAND_DISABLE_STALL = 0x03, /**< Disable stall on page fault */
+	MALI_MMU_COMMAND_ZAP_CACHE = 0x04, /**< Zap the entire page table cache */
+	MALI_MMU_COMMAND_PAGE_FAULT_DONE = 0x05, /**< Page fault processed */
+	MALI_MMU_COMMAND_SOFT_RESET = 0x06 /**< Reset the MMU back to power-on settings */
+} mali_mmu_command;
+
+typedef enum mali_mmu_status_bits
+{
+	MALI_MMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
+	MALI_MMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
+	MALI_MMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
+	MALI_MMU_STATUS_BIT_IDLE                = 1 << 3,
+	MALI_MMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
+	MALI_MMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
+} mali_mmu_status_bits;
+
+/**
+ * Defintion of the type used to represent memory used by a session.
+ * Containts the pointer to the huge user space virtual memory area
+ * used to access the Mali memory.
+ */
+typedef struct memory_session
+{
+	_mali_osk_lock_t *lock; /**< Lock protecting the vm manipulation */
+
+	u32 mali_base_address; /**< Mali virtual memory area used by this session */
+	mali_descriptor_mapping * descriptor_mapping; /**< Mapping between userspace descriptors and our pointers */
+
+	u32 page_directory; /**< Physical address of the memory session's page directory */
+
+	mali_io_address page_directory_mapped; /**< Pointer to the mapped version of the page directory into the kernel's address space */
+	mali_io_address page_entries_mapped[1024]; /**< Pointers to the page tables which exists in the page directory mapped into the kernel's address space */
+	u32   page_entries_usage_count[1024]; /**< Tracks usage count of the page table pages, so they can be releases on the last reference */
+
+	_mali_osk_list_t active_mmus; /**< The MMUs in this session, in increasing order of ID (so we can lock them in the correct order when necessary) */
+	_mali_osk_list_t memory_head; /**< Track all the memory allocated in this session, for freeing on abnormal termination */
+} memory_session;
+
+typedef struct mali_kernel_memory_mmu_idle_callback
+{
+	_mali_osk_list_t link;
+	void (*callback)(void*);
+	void * callback_argument;
+} mali_kernel_memory_mmu_idle_callback;
+
+/**
+ * Definition of the MMU struct
+ * Used to track a MMU unit in the system.
+ * Contains information about the mapping of the registers
+ */
+typedef struct mali_kernel_memory_mmu
+{
+	int id; /**< ID of the MMU, no duplicate IDs may exist on the system */
+	const char * description; /**< Description text received from the resource manager to help identify the resource for people */
+	int irq_nr; /**< IRQ number */
+	u32 base; /**< Physical address of the registers */
+	mali_io_address mapped_registers; /**< Virtual mapping of the registers */
+	u32 mapping_size; /**< Size of registers in bytes */
+	_mali_osk_list_t list; /**< Used to link multiple MMU's into a list */
+	_mali_osk_irq_t *irq;
+	u32 flags; /**< Used to store if there is something special with this mmu. */
+
+	_mali_osk_lock_t *lock; /**< Lock protecting access to the usage fields */
+	/* usage fields */
+	memory_session * active_session; /**< Active session, NULL if no session is active */
+	u32 usage_count; /**< Number of nested activations of the active session */
+	_mali_osk_list_t callbacks; /**< Callback registered for MMU idle notification */
+	void *core;
+
+	int in_page_fault_handler;
+
+	_mali_osk_list_t session_link;
+} mali_kernel_memory_mmu;
+
+typedef struct dedicated_memory_info
+{
+	u32 base;
+	u32 size;
+	struct dedicated_memory_info * next;
+} dedicated_memory_info;
+
+/* types used for external_memory and ump_memory physical memory allocators, which are using the mali_allocation_engine */
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+typedef struct ump_mem_allocation
+{
+	mali_allocation_engine * engine;
+	mali_memory_allocation * descriptor;
+	u32 initial_offset;
+	u32 size_allocated;
+	ump_dd_handle ump_mem;
+} ump_mem_allocation ;
+#endif
+
+typedef struct external_mem_allocation
+{
+	mali_allocation_engine * engine;
+	mali_memory_allocation * descriptor;
+	u32 initial_offset;
+	u32 size;
+} external_mem_allocation;
+
+/*
+   Subsystem interface implementation
+*/
+/**
+ * Fixed block memory subsystem startup function.
+ * Called by the driver core when the driver is loaded.
+ * Registers the memory systems ioctl handler, resource handlers and memory map function with the core.
+ *
+ * @param id Identifier assigned by the core to the memory subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_initialize(mali_kernel_subsystem_identifier id);
+
+/**
+ * Fixed block memory subsystem shutdown function.
+ * Called by the driver core when the driver is unloaded.
+ * Cleans up
+ * @param id Identifier assigned by the core to the memory subsystem
+ */
+static void mali_memory_core_terminate(mali_kernel_subsystem_identifier id);
+
+/**
+ * MMU Memory load complete notification function.
+ * Called by the driver core when all drivers have loaded and all resources has been registered
+ * Builds the memory overall memory list
+ * @param id Identifier assigned by the core to the memory subsystem
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_load_complete(mali_kernel_subsystem_identifier id);
+
+/**
+ * Fixed block memory subsystem session begin notification
+ * Called by the core when a new session to the driver is started.
+ * Creates a memory session object and sets it as the subsystem slot data for this session
+ * @param slot Pointer to the slot to use for storing per-session data
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+
+/**
+ * Fixed block memory subsystem session end notification
+ * Called by the core when a session to the driver has ended.
+ * Cleans up per session data, which includes checking and fixing memory leaks
+ *
+ * @param slot Pointer to the slot to use for storing per-session data
+ */
+static void mali_memory_core_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot);
+
+/**
+ * Fixed block memory subsystem system info filler
+ * Called by the core when a system info update is needed
+ * We fill in info about all the memory types we have
+ * @param info Pointer to system info struct to update
+ * @return 0 on success, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_system_info_fill(_mali_system_info* info);
+
+/* our registered resource handlers */
+
+/**
+ * Fixed block memory subsystem's notification handler for MMU resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each mmu described in the active architecture's config.h file.
+ * @param resource The resource to handle (type MMU)
+ * @return 0 if the MMU was found and initialized, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_resource_mmu(_mali_osk_resource_t * resource);
+
+/**
+ * Fixed block memory subsystem's notification handler for FPGA_FRAMEWORK resource instances.
+ * Registered with the core during startup.
+ * Called by the core for each fpga framework described in the active architecture's config.h file.
+ * @param resource The resource to handle (type FPGA_FRAMEWORK)
+ * @return 0 if the FPGA framework was found and initialized, negative on error
+ */
+static _mali_osk_errcode_t mali_memory_core_resource_fpga(_mali_osk_resource_t * resource);
+
+
+static _mali_osk_errcode_t mali_memory_core_resource_dedicated_memory(_mali_osk_resource_t * resource);
+static _mali_osk_errcode_t mali_memory_core_resource_os_memory(_mali_osk_resource_t * resource);
+
+/**
+ * @brief Internal function for unmapping memory
+ *
+ * Worker function for unmapping memory from a user-process. We assume that the
+ * session/descriptor's lock was obtained before entry. For example, the
+ * wrapper _mali_ukk_mem_munmap() will lock the descriptor, then call this
+ * function to do the actual unmapping. mali_memory_core_session_end() could
+ * also call this directly (depending on compilation options), having locked
+ * the descriptor.
+ *
+ * This function will fail if it is unable to put the MMU in stall mode (which
+ * might be the case if a page fault is also being processed).
+ *
+ * @param args see _mali_uk_mem_munmap_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+static _mali_osk_errcode_t _mali_ukk_mem_munmap_internal( _mali_uk_mem_munmap_s *args );
+
+/**
+ * The MMU interrupt handler
+ * Upper half of the MMU interrupt processing.
+ * Called by the kernel when the MMU has triggered an interrupt.
+ * The interrupt function supports IRQ sharing. So it'll probe the MMU in question
+ * @param irq The irq number (not used)
+ * @param dev_id Points to the MMU object being handled
+ * @param regs Registers of interrupted process (not used)
+ * @return Standard Linux interrupt result.
+ *         Subset used by the driver is IRQ_HANDLED processed
+ *                                      IRQ_NONE Not processed
+ */
+static _mali_osk_errcode_t mali_kernel_memory_mmu_interrupt_handler_upper_half(void * data);
+
+/**
+ * The MMU reset hander
+ * Bottom half of the MMU interrupt processing for page faults and bus errors
+ * @param work The item to operate on, NULL in our case
+ */
+static void mali_kernel_memory_mmu_interrupt_handler_bottom_half ( void *data );
+
+/**
+ * Read MMU register value
+ * Reads the contents of the specified register.
+ * @param unit The MMU to read from
+ * @param reg The register to read
+ * @return The contents of the register
+ */
+static u32 mali_mmu_register_read(mali_kernel_memory_mmu * unit, mali_mmu_register reg);
+
+/**
+ * Write to a MMU register
+ * Writes the given value to the specified register
+ * @param unit The MMU to write to
+ * @param reg The register to write to
+ * @param val The value to write to the register
+ */
+static void mali_mmu_register_write(mali_kernel_memory_mmu * unit, mali_mmu_register reg, u32 val);
+
+/**
+ * Issues the reset command to the MMU and waits for HW to be ready again
+ * @param mmu The MMU to reset
+ */
+static void mali_mmu_raw_reset(mali_kernel_memory_mmu * mmu);
+
+/**
+ * Issues the enable paging command to the MMU and waits for HW to complete the request
+ * @param mmu The MMU to enable paging for
+ */
+static void mali_mmu_enable_paging(mali_kernel_memory_mmu * mmu);
+
+/**
+ * Issues the enable stall command to the MMU and waits for HW to complete the request
+ * @param mmu The MMU to enable paging for
+ * @return MALI_TRUE if HW stall was successfully engaged, otherwise MALI_FALSE (req timed out)
+ */
+static mali_bool mali_mmu_enable_stall(mali_kernel_memory_mmu * mmu);
+
+/**
+ * Issues the disable stall command to the MMU and waits for HW to complete the request
+ * @param mmu The MMU to enable paging for
+ */
+static void mali_mmu_disable_stall(mali_kernel_memory_mmu * mmu);
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+static void ump_memory_release(void * ctx, void * handle);
+static mali_physical_memory_allocation_result ump_memory_commit(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info);
+#endif /* MALI_USE_UNIFIED_MEMORY_PROVIDER != 0*/
+
+
+static void external_memory_release(void * ctx, void * handle);
+static mali_physical_memory_allocation_result external_memory_commit(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info);
+
+
+
+
+/* nop functions */
+
+/* mali address manager needs to allocate page tables on allocate, write to page table(s) on map, write to page table(s) and release page tables on release */
+static _mali_osk_errcode_t  mali_address_manager_allocate(mali_memory_allocation * descriptor); /* validates the range, allocates memory for the page tables if needed */
+static _mali_osk_errcode_t  mali_address_manager_map(mali_memory_allocation * descriptor, u32 offset, u32 *phys_addr, u32 size);
+static void mali_address_manager_release(mali_memory_allocation * descriptor);
+
+static void mali_mmu_activate_address_space(mali_kernel_memory_mmu * mmu, u32 page_directory);
+
+_mali_osk_errcode_t mali_mmu_page_table_cache_create(void);
+void mali_mmu_page_table_cache_destroy(void);
+
+_mali_osk_errcode_t mali_mmu_get_table_page(u32 *table_page, mali_io_address *mapping);
+void mali_mmu_release_table_page(u32 pa);
+
+static _mali_osk_errcode_t mali_allocate_empty_page_directory(void);
+
+static void mali_free_empty_page_directory(void);
+
+static _mali_osk_errcode_t fill_page(mali_io_address mapping, u32 data);
+
+static _mali_osk_errcode_t mali_allocate_fault_flush_pages(void);
+
+static void mali_free_fault_flush_pages(void);
+
+static void mali_mmu_probe_irq_trigger(mali_kernel_memory_mmu * mmu);
+static _mali_osk_errcode_t mali_mmu_probe_irq_acknowledge(mali_kernel_memory_mmu * mmu);
+
+/* MMU variables */
+
+typedef struct mali_mmu_page_table_allocation
+{
+	_mali_osk_list_t list;
+	u32 * usage_map;
+	u32 usage_count;
+	u32 num_pages;
+	mali_page_table_block pages;
+} mali_mmu_page_table_allocation;
+
+typedef struct mali_mmu_page_table_allocations
+{
+	_mali_osk_lock_t *lock;
+	_mali_osk_list_t partial;
+	_mali_osk_list_t full;
+	/* we never hold on to a empty allocation */
+} mali_mmu_page_table_allocations;
+
+/* Head of the list of MMUs */
+static _MALI_OSK_LIST_HEAD(mmu_head);
+
+/* the mmu page table cache */
+static struct mali_mmu_page_table_allocations page_table_cache;
+
+/* page fault queue flush helper pages
+ * note that the mapping pointers are currently unused outside of the initialization functions */
+static u32 mali_page_fault_flush_page_directory = MALI_INVALID_PAGE;
+static mali_io_address mali_page_fault_flush_page_directory_mapping = NULL;
+static u32 mali_page_fault_flush_page_table = MALI_INVALID_PAGE;
+static mali_io_address mali_page_fault_flush_page_table_mapping = NULL;
+static u32 mali_page_fault_flush_data_page = MALI_INVALID_PAGE;
+static mali_io_address mali_page_fault_flush_data_page_mapping = NULL;
+
+/* an empty page directory (no address valid) which is active on any MMU not currently marked as in use */
+static u32 mali_empty_page_directory = MALI_INVALID_PAGE;
+
+/*
+   The fixed memory system's mali subsystem interface implementation.
+   We currently handle module and session life-time management.
+*/
+struct mali_kernel_subsystem mali_subsystem_memory =
+{
+	mali_memory_core_initialize,        /* startup */
+	NULL, /*mali_memory_core_terminate,*/         /* shutdown */
+	mali_memory_core_load_complete,     /* load_complete */
+	mali_memory_core_system_info_fill,  /* system_info_fill */
+	mali_memory_core_session_begin,     /* session_begin */
+	mali_memory_core_session_end,       /* session_end */
+	NULL,                               /* broadcast_notification */
+#if MALI_STATE_TRACKING
+	NULL,                               /* dump_state */
+#endif
+};
+
+static mali_kernel_mem_address_manager mali_address_manager =
+{
+	mali_address_manager_allocate, /* allocate */
+	mali_address_manager_release,  /* release */
+	mali_address_manager_map,      /* map_physical */
+	NULL                           /* unmap_physical not present*/
+};
+
+static mali_kernel_mem_address_manager process_address_manager =
+{
+	_mali_osk_mem_mapregion_init,  /* allocate */
+	_mali_osk_mem_mapregion_term,  /* release */
+	_mali_osk_mem_mapregion_map,   /* map_physical */
+	_mali_osk_mem_mapregion_unmap  /* unmap_physical */
+};
+
+static mali_allocation_engine memory_engine = NULL;
+static mali_physical_memory_allocator * physical_memory_allocators = NULL;
+
+static dedicated_memory_info * mem_region_registrations = NULL;
+
+/* Initialized when this subsystem is initialized. This is determined by the
+ * position in subsystems[], and so the value used to initialize this is
+ * determined at compile time */
+static mali_kernel_subsystem_identifier mali_subsystem_memory_id = (mali_kernel_subsystem_identifier)-1;
+
+/* called during module init */
+static _mali_osk_errcode_t mali_memory_core_initialize(mali_kernel_subsystem_identifier id)
+{
+	MALI_DEBUG_PRINT(2, ("MMU memory system initializing\n"));
+
+	/* save our subsystem id for later for use in slot lookup during session activation */
+	mali_subsystem_memory_id = id;
+
+	_MALI_OSK_INIT_LIST_HEAD(&mmu_head);
+
+	MALI_CHECK_NO_ERROR( mali_mmu_page_table_cache_create() );
+
+	/* register our handlers */
+	MALI_CHECK_NO_ERROR( _mali_kernel_core_register_resource_handler(MMU, mali_memory_core_resource_mmu) );
+
+	MALI_CHECK_NO_ERROR( _mali_kernel_core_register_resource_handler(FPGA_FRAMEWORK, mali_memory_core_resource_fpga) );
+
+	MALI_CHECK_NO_ERROR( _mali_kernel_core_register_resource_handler(MEMORY, mali_memory_core_resource_dedicated_memory) );
+
+	MALI_CHECK_NO_ERROR( _mali_kernel_core_register_resource_handler(OS_MEMORY, mali_memory_core_resource_os_memory) );
+
+	memory_engine = mali_allocation_engine_create(&mali_address_manager, &process_address_manager);
+	MALI_CHECK_NON_NULL( memory_engine, _MALI_OSK_ERR_FAULT);
+
+	MALI_SUCCESS;
+}
+
+/* called if/when our module is unloaded */
+static void mali_memory_core_terminate(mali_kernel_subsystem_identifier id)
+{
+	mali_kernel_memory_mmu * mmu, *temp_mmu;
+
+	MALI_DEBUG_PRINT(2, ("MMU memory system terminating\n"));
+
+	/* loop over all MMU units and shut them down */
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &mmu_head, mali_kernel_memory_mmu, list)
+	{
+		/* reset to defaults */
+		mali_mmu_raw_reset(mmu);
+
+		/* unregister the irq */
+		_mali_osk_irq_term(mmu->irq);
+
+		/* remove from the list of MMU's on the system */
+		_mali_osk_list_del(&mmu->list);
+
+		/* release resources */
+		_mali_osk_mem_unmapioregion(mmu->base, mmu->mapping_size, mmu->mapped_registers);
+		_mali_osk_mem_unreqregion(mmu->base, mmu->mapping_size);
+		_mali_osk_lock_term(mmu->lock);
+		_mali_osk_free(mmu);
+	}
+
+	/* free global helper pages */
+	mali_free_empty_page_directory();
+	mali_free_fault_flush_pages();
+
+	/* destroy the page table cache before shutting down backends in case we have a page table leak to report */
+	mali_mmu_page_table_cache_destroy();
+
+	while ( NULL != mem_region_registrations)
+	{
+		dedicated_memory_info * m;
+		m = mem_region_registrations;
+		mem_region_registrations = m->next;
+		_mali_osk_mem_unreqregion(m->base, m->size);
+		_mali_osk_free(m);
+	}
+
+	while ( NULL != physical_memory_allocators)
+	{
+		mali_physical_memory_allocator * m;
+		m = physical_memory_allocators;
+		physical_memory_allocators = m->next;
+		m->destroy(m);
+	}
+
+	if (NULL != memory_engine)
+	{
+		mali_allocation_engine_destroy(memory_engine);
+		memory_engine = NULL;
+	}
+
+}
+
+static _mali_osk_errcode_t mali_memory_core_session_begin(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue)
+{
+	memory_session * session_data;
+	_mali_osk_errcode_t err;
+	int i;
+	mali_io_address pd_mapped;
+
+	/* validate input */
+	if (NULL == slot)
+	{
+		MALI_DEBUG_PRINT(1, ("NULL slot given to memory session begin\n"));
+		MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	if (NULL != *slot)
+	{
+		MALI_DEBUG_PRINT(1, ("The slot given to memory session begin already contains data"));
+		MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	MALI_DEBUG_PRINT(2, ("MMU session begin\n"));
+
+	/* create the session data object */
+	session_data = _mali_osk_calloc(1, sizeof(memory_session));
+	MALI_CHECK_NON_NULL( session_data, _MALI_OSK_ERR_NOMEM );
+
+	/* create descriptor mapping table */
+	session_data->descriptor_mapping = mali_descriptor_mapping_create(MALI_MEM_DESCRIPTORS_INIT, MALI_MEM_DESCRIPTORS_MAX);
+
+	if (NULL == session_data->descriptor_mapping)
+	{
+		_mali_osk_free(session_data);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	err = mali_mmu_get_table_page(&session_data->page_directory, &pd_mapped);
+
+	session_data->page_directory_mapped = pd_mapped;
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		mali_descriptor_mapping_destroy(session_data->descriptor_mapping);
+		_mali_osk_free(session_data);
+		MALI_ERROR(err);
+	}
+	MALI_DEBUG_ASSERT_POINTER( session_data->page_directory_mapped );
+
+	MALI_DEBUG_PRINT(2, ("Page directory for session 0x%x placed at physical address 0x%08X\n", mali_session_data, session_data->page_directory));
+
+	for (i = 0; i < MALI_MMU_PAGE_SIZE/4; i++)
+	{
+		/* mark each page table as not present */
+		_mali_osk_mem_iowrite32_relaxed(session_data->page_directory_mapped, sizeof(u32) * i, 0);
+	}
+	_mali_osk_write_mem_barrier();
+
+	/* page_table_mapped[] is already set to NULL by _mali_osk_calloc call */
+
+	_MALI_OSK_INIT_LIST_HEAD(&session_data->active_mmus);
+	session_data->lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_ONELOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 128);
+	if (NULL == session_data->lock)
+	{
+		mali_mmu_release_table_page(session_data->page_directory);
+		mali_descriptor_mapping_destroy(session_data->descriptor_mapping);
+		_mali_osk_free(session_data);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Init the session's memory allocation list */
+	_MALI_OSK_INIT_LIST_HEAD( &session_data->memory_head );
+
+	*slot = session_data; /* slot will point to our data object */
+	MALI_DEBUG_PRINT(2, ("MMU session begin: success\n"));
+	MALI_SUCCESS;
+}
+
+static void descriptor_table_cleanup_callback(int descriptor_id, void* map_target)
+{
+	mali_memory_allocation * descriptor;
+
+	descriptor = (mali_memory_allocation*)map_target;
+
+	MALI_DEBUG_PRINT(1, ("Cleanup of descriptor %d mapping to 0x%x in descriptor table\n", descriptor_id, map_target));
+	MALI_DEBUG_ASSERT(descriptor);
+
+	mali_allocation_engine_release_memory(memory_engine, descriptor);
+	_mali_osk_free(descriptor);
+}
+
+static void mali_memory_core_session_end(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot)
+{
+	memory_session * session_data;
+	int i;
+	const int num_page_table_entries = sizeof(session_data->page_entries_mapped) / sizeof(session_data->page_entries_mapped[0]);
+
+	MALI_DEBUG_PRINT(2, ("MMU session end\n"));
+
+	/* validate input */
+	if (NULL == slot)
+	{
+		MALI_DEBUG_PRINT(1, ("NULL slot given to memory session begin\n"));
+		return;
+	}
+
+	session_data = (memory_session *)*slot;
+
+	if (NULL == session_data)
+	{
+		MALI_DEBUG_PRINT(1, ("No session data found during session end\n"));
+		return;
+	}
+	/* Lock the session so we can modify the memory list */
+	_mali_osk_lock_wait( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+	/* Noninterruptable spinlock type, so must always have locked. Checking should've been done in OSK function. */
+
+#ifndef MALI_UKK_HAS_IMPLICIT_MMAP_CLEANUP
+#if _MALI_OSK_SPECIFIC_INDIRECT_MMAP
+#error Indirect MMAP specified, but UKK does not have implicit MMAP cleanup. Current implementation does not handle this.
+#else
+
+	/* Free all memory engine allocations */
+	if (0 == _mali_osk_list_empty(&session_data->memory_head))
+	{
+		mali_memory_allocation *descriptor;
+		mali_memory_allocation *temp;
+		_mali_uk_mem_munmap_s unmap_args;
+
+		MALI_DEBUG_PRINT(1, ("Memory found on session usage list during session termination\n"));
+
+		unmap_args.ctx = mali_session_data;
+
+		/* use the 'safe' list iterator, since freeing removes the active block from the list we're iterating */
+		_MALI_OSK_LIST_FOREACHENTRY(descriptor, temp, &session_data->memory_head, mali_memory_allocation, list)
+		{
+			MALI_DEBUG_PRINT(4, ("Freeing block with mali address 0x%x size %d mapped in user space at 0x%x\n",
+						descriptor->mali_address, descriptor->size, descriptor->size, descriptor->mapping)
+					);
+			/* ASSERT that the descriptor's lock references the correct thing */
+			MALI_DEBUG_ASSERT(  descriptor->lock == session_data->lock );
+			/* Therefore, we have already locked the descriptor */
+
+			unmap_args.size = descriptor->size;
+			unmap_args.mapping = descriptor->mapping;
+			unmap_args.cookie = (u32)descriptor;
+
+			/*
+			 * This removes the descriptor from the list, and frees the descriptor
+			 *
+			 * Does not handle the _MALI_OSK_SPECIFIC_INDIRECT_MMAP case, since
+			 * the only OS we are aware of that requires indirect MMAP also has
+			 * implicit mmap cleanup.
+			 */
+			_mali_ukk_mem_munmap_internal( &unmap_args );
+		}
+	}
+
+	/* Assert that we really did free everything */
+	MALI_DEBUG_ASSERT( _mali_osk_list_empty(&session_data->memory_head) );
+#endif /* _MALI_OSK_SPECIFIC_INDIRECT_MMAP */
+#endif /* MALI_UKK_HAS_IMPLICIT_MMAP_CLEANUP */
+
+	if (NULL != session_data->descriptor_mapping)
+	{
+		mali_descriptor_mapping_call_for_each(session_data->descriptor_mapping, descriptor_table_cleanup_callback);
+		mali_descriptor_mapping_destroy(session_data->descriptor_mapping);
+		session_data->descriptor_mapping = NULL;
+	}
+
+	for (i = 0; i < num_page_table_entries; i++)
+	{
+		/* free PTE memory */
+		if (session_data->page_directory_mapped && (_mali_osk_mem_ioread32(session_data->page_directory_mapped, sizeof(u32)*i) & MALI_MMU_FLAGS_PRESENT))
+		{
+			mali_mmu_release_table_page( _mali_osk_mem_ioread32(session_data->page_directory_mapped, i*sizeof(u32)) & ~MALI_MMU_FLAGS_MASK);
+			_mali_osk_mem_iowrite32(session_data->page_directory_mapped, i * sizeof(u32), 0);
+		}
+	}
+
+	if (MALI_INVALID_PAGE != session_data->page_directory)
+	{
+		mali_mmu_release_table_page(session_data->page_directory);
+		session_data->page_directory = MALI_INVALID_PAGE;
+	}
+
+	_mali_osk_lock_signal( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+
+	/**
+	 * @note Could the VMA close handler mean that we use the session data after it was freed?
+	 * In which case, would need to refcount the session data, and free on VMA close
+	 */
+
+	/* Free the lock */
+	_mali_osk_lock_term( session_data->lock );
+	/* free the session data object */
+	_mali_osk_free(session_data);
+
+	/* clear our slot */
+	*slot = NULL;
+
+	return;
+}
+
+static _mali_osk_errcode_t mali_allocate_empty_page_directory(void)
+{
+	_mali_osk_errcode_t err;
+	mali_io_address mapping;
+
+	MALI_CHECK_NO_ERROR(mali_mmu_get_table_page(&mali_empty_page_directory, &mapping));
+
+	MALI_DEBUG_ASSERT_POINTER( mapping );
+
+	err = fill_page(mapping, 0);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		mali_mmu_release_table_page(mali_empty_page_directory);
+		mali_empty_page_directory = MALI_INVALID_PAGE;
+	}
+	return err;
+}
+
+static void mali_free_empty_page_directory(void)
+{
+	if (MALI_INVALID_PAGE != mali_empty_page_directory)
+	{
+		mali_mmu_release_table_page(mali_empty_page_directory);
+		mali_empty_page_directory = MALI_INVALID_PAGE;
+	}
+}
+
+static _mali_osk_errcode_t fill_page(mali_io_address mapping, u32 data)
+{
+	int i;
+	MALI_DEBUG_ASSERT_POINTER( mapping );
+
+	for(i = 0; i < MALI_MMU_PAGE_SIZE/4; i++)
+	{
+		_mali_osk_mem_iowrite32_relaxed( mapping, i * sizeof(u32), data);
+	}
+	_mali_osk_mem_barrier();
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_allocate_fault_flush_pages(void)
+{
+	_mali_osk_errcode_t err;
+
+	err = mali_mmu_get_table_page(&mali_page_fault_flush_data_page, &mali_page_fault_flush_data_page_mapping);
+	if (_MALI_OSK_ERR_OK == err)
+	{
+		err = mali_mmu_get_table_page(&mali_page_fault_flush_page_table, &mali_page_fault_flush_page_table_mapping);
+		if (_MALI_OSK_ERR_OK == err)
+		{
+			err = mali_mmu_get_table_page(&mali_page_fault_flush_page_directory, &mali_page_fault_flush_page_directory_mapping);
+			if (_MALI_OSK_ERR_OK == err)
+			{
+				fill_page(mali_page_fault_flush_data_page_mapping, 0);
+				fill_page(mali_page_fault_flush_page_table_mapping, mali_page_fault_flush_data_page | MALI_MMU_FLAGS_WRITE_PERMISSION | MALI_MMU_FLAGS_READ_PERMISSION | MALI_MMU_FLAGS_PRESENT);
+				fill_page(mali_page_fault_flush_page_directory_mapping, mali_page_fault_flush_page_table | MALI_MMU_FLAGS_PRESENT);
+				MALI_SUCCESS;
+			}
+			mali_mmu_release_table_page(mali_page_fault_flush_page_table);
+			mali_page_fault_flush_page_table = MALI_INVALID_PAGE;
+			mali_page_fault_flush_page_table_mapping = NULL;
+		}
+		mali_mmu_release_table_page(mali_page_fault_flush_data_page);
+		mali_page_fault_flush_data_page = MALI_INVALID_PAGE;
+		mali_page_fault_flush_data_page_mapping = NULL;
+	}
+	MALI_ERROR(err);
+}
+
+static void mali_free_fault_flush_pages(void)
+{
+	if (MALI_INVALID_PAGE != mali_page_fault_flush_page_directory)
+	{
+		mali_mmu_release_table_page(mali_page_fault_flush_page_directory);
+		mali_page_fault_flush_page_directory = MALI_INVALID_PAGE;
+	}
+
+	if (MALI_INVALID_PAGE != mali_page_fault_flush_page_table)
+	{
+		mali_mmu_release_table_page(mali_page_fault_flush_page_table);
+		mali_page_fault_flush_page_table = MALI_INVALID_PAGE;
+	}
+
+	if (MALI_INVALID_PAGE != mali_page_fault_flush_data_page)
+	{
+		mali_mmu_release_table_page(mali_page_fault_flush_data_page);
+		mali_page_fault_flush_data_page = MALI_INVALID_PAGE;
+	}
+}
+
+static _mali_osk_errcode_t mali_memory_core_load_complete(mali_kernel_subsystem_identifier id)
+{
+	mali_kernel_memory_mmu * mmu, * temp_mmu;
+
+	/* Report the allocators */
+	mali_allocation_engine_report_allocators( physical_memory_allocators );
+
+	/* allocate the helper pages */
+	MALI_CHECK_NO_ERROR( mali_allocate_empty_page_directory() );
+	if (_MALI_OSK_ERR_OK != mali_allocate_fault_flush_pages())
+	{
+		mali_free_empty_page_directory();
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* activate the empty page directory on all MMU's */
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &mmu_head, mali_kernel_memory_mmu, list)
+	{
+		mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, mali_empty_page_directory);
+		mali_mmu_enable_paging(mmu);
+	}
+
+	MALI_DEBUG_PRINT(4, ("MMUs activated\n"));
+	/* the MMU system is now active */
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_system_info_fill(_mali_system_info* info)
+{
+	_mali_mem_info * mem_info;
+
+	/* Make sure we won't leak any memory. It could also be that it's an
+	 * uninitialized variable, but the caller should have zeroed the
+	 * variable. */
+	MALI_DEBUG_ASSERT(NULL == info->mem_info);
+
+	info->has_mmu = 1;
+
+	mem_info = _mali_osk_calloc(1,sizeof(_mali_mem_info));
+	MALI_CHECK_NON_NULL( mem_info, _MALI_OSK_ERR_NOMEM );
+
+	mem_info->size = 2048UL * 1024UL * 1024UL;
+	mem_info->maximum_order_supported = 30;
+	mem_info->flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE |_MALI_GP_READABLE | _MALI_GP_WRITEABLE;
+	mem_info->identifier = 0;
+
+	info->mem_info = mem_info;
+
+	/* all OK */
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_mmu(_mali_osk_resource_t * resource)
+{
+	mali_kernel_memory_mmu * mmu;
+
+	MALI_DEBUG_PRINT(4, ("MMU '%s' @ (0x%08X - 0x%08X)\n",
+				resource->description, resource->base, resource->base + MALI_MMU_REGISTERS_SIZE - 1
+				));
+
+	if (NULL != mali_memory_core_mmu_lookup(resource->mmu_id))
+	{
+		MALI_DEBUG_PRINT(1, ("Duplicate MMU ids found. The id %d is already in use\n", resource->mmu_id));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(resource->base, MALI_MMU_REGISTERS_SIZE, resource->description))
+	{
+		/* specified addresses are already in used by another driver / the kernel */
+		MALI_DEBUG_PRINT(
+				1, ("Failed to request MMU '%s' register address space at (0x%08X - 0x%08X)\n",
+					resource->description, resource->base, resource->base + MALI_MMU_REGISTERS_SIZE - 1
+				   ));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	mmu = _mali_osk_calloc(1, sizeof(mali_kernel_memory_mmu));
+
+	if (NULL == mmu)
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to allocate memory for handling a MMU unit"));
+		_mali_osk_mem_unreqregion(resource->base, MALI_MMU_REGISTERS_SIZE);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	/* basic setup */
+	_MALI_OSK_INIT_LIST_HEAD(&mmu->list);
+
+	mmu->id = resource->mmu_id;
+	mmu->irq_nr = resource->irq;
+	mmu->flags = resource->flags;
+	mmu->base = resource->base;
+	mmu->mapping_size = MALI_MMU_REGISTERS_SIZE;
+	mmu->description = resource->description; /* no need to copy */
+	_MALI_OSK_INIT_LIST_HEAD(&mmu->callbacks);
+	_MALI_OSK_INIT_LIST_HEAD(&mmu->session_link);
+	mmu->in_page_fault_handler = 0;
+
+	mmu->lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_ONELOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 127-mmu->id);
+	if (NULL == mmu->lock)
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to create mmu lock\n"));
+		_mali_osk_mem_unreqregion(mmu->base, mmu->mapping_size);
+		_mali_osk_free(mmu);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* map the registers */
+	mmu->mapped_registers = _mali_osk_mem_mapioregion( mmu->base, mmu->mapping_size, mmu->description );
+	if (NULL == mmu->mapped_registers)
+	{
+		/* failed to map the registers */
+		MALI_DEBUG_PRINT(1, ("Failed to map MMU registers at 0x%08X\n", mmu->base));
+		_mali_osk_lock_term(mmu->lock);
+		_mali_osk_mem_unreqregion(mmu->base, MALI_MMU_REGISTERS_SIZE);
+		_mali_osk_free(mmu);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	MALI_DEBUG_PRINT(4, ("MMU '%s' @ (0x%08X - 0x%08X) mapped to 0x%08X\n",
+				resource->description, resource->base, resource->base + MALI_MMU_REGISTERS_SIZE - 1,  mmu->mapped_registers
+				));
+
+	/* setup MMU interrupt mask */
+	/* set all values to known defaults */
+	mali_mmu_raw_reset(mmu);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, MALI_MMU_INTERRUPT_PAGE_FAULT | MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+	/* setup MMU page directory pointer */
+	/* The mali_page_directory pointer is guaranteed to be 4kb aligned because we've used get_zeroed_page to accquire it */
+	/* convert the kernel virtual address into a physical address and set */
+
+	/* add to our list of MMU's */
+	_mali_osk_list_addtail(&mmu->list, &mmu_head);
+
+	mmu->irq = _mali_osk_irq_init(
+			mmu->irq_nr,
+			mali_kernel_memory_mmu_interrupt_handler_upper_half,
+			mali_kernel_memory_mmu_interrupt_handler_bottom_half,
+			(_mali_osk_irq_trigger_t)mali_mmu_probe_irq_trigger,
+			(_mali_osk_irq_ack_t)mali_mmu_probe_irq_acknowledge,
+			mmu,
+			"mali_mmu_irq_handlers"
+			);
+	if (NULL == mmu->irq)
+	{
+		_mali_osk_list_del(&mmu->list);
+		_mali_osk_lock_term(mmu->lock);
+		_mali_osk_mem_unmapioregion( mmu->base, mmu->mapping_size, mmu->mapped_registers );
+		_mali_osk_mem_unreqregion(resource->base, MALI_MMU_REGISTERS_SIZE);
+		_mali_osk_free(mmu);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* set to a known state */
+	mali_mmu_raw_reset(mmu);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, MALI_MMU_INTERRUPT_PAGE_FAULT | MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+
+	MALI_DEBUG_PRINT(2, ("MMU registered\n"));
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_fpga(_mali_osk_resource_t * resource)
+{
+	mali_io_address mapping;
+
+	MALI_DEBUG_PRINT(5, ("FPGA framework '%s' @ (0x%08X - 0x%08X)\n",
+				resource->description, resource->base, resource->base + sizeof(u32) * 2 - 1
+				));
+
+	mapping = _mali_osk_mem_mapioregion(resource->base + 0x1000, sizeof(u32) * 2, "fpga framework");
+	if (mapping)
+	{
+		MALI_DEBUG_CODE(u32 data = )
+			_mali_osk_mem_ioread32(mapping, 0);
+		MALI_DEBUG_PRINT(2, ("FPGA framwork '%s' @ 0x%08X:\n", resource->description, resource->base));
+		MALI_DEBUG_PRINT(2, ("\tBitfile date: %d%02d%02d_%02d%02d\n",
+					(data >> 20),
+					(data >> 16) & 0xF,
+					(data >> 11) & 0x1F,
+					(data >> 6)  & 0x1F,
+					(data >> 0)  & 0x3F));
+		MALI_DEBUG_CODE(data = )
+			_mali_osk_mem_ioread32(mapping, sizeof(u32));
+		MALI_DEBUG_PRINT(2, ("\tBitfile SCCS rev: %d\n", data));
+
+		_mali_osk_mem_unmapioregion(resource->base + 0x1000, sizeof(u32) *2, mapping);
+	}
+	else MALI_DEBUG_PRINT(1, ("Failed to access FPGA framwork '%s' @ 0x%08X\n", resource->description, resource->base));
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_os_memory(_mali_osk_resource_t * resource)
+{
+	mali_physical_memory_allocator * allocator;
+	mali_physical_memory_allocator ** next_allocator_list;
+
+	u32 alloc_order = resource->alloc_order;
+
+	allocator = mali_os_allocator_create(resource->size, resource->cpu_usage_adjust, resource->description);
+	if (NULL == allocator)
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to create OS memory allocator\n"));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	allocator->alloc_order = alloc_order;
+
+	/* link in the allocator: insertion into ordered list
+	 * resources of the same alloc_order will be Last-in-first */
+	next_allocator_list = &physical_memory_allocators;
+
+	while ( NULL != *next_allocator_list &&
+			(*next_allocator_list)->alloc_order < alloc_order )
+	{
+		next_allocator_list = &((*next_allocator_list)->next);
+	}
+
+	allocator->next = (*next_allocator_list);
+	(*next_allocator_list) = allocator;
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_memory_core_resource_dedicated_memory(_mali_osk_resource_t * resource)
+{
+	mali_physical_memory_allocator * allocator;
+	mali_physical_memory_allocator ** next_allocator_list;
+	dedicated_memory_info * cleanup_data;
+
+	u32 alloc_order = resource->alloc_order;
+
+	/* do the lowlevel linux operation first */
+
+	/* Request ownership of the memory */
+	if (_MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(resource->base, resource->size, resource->description))
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to request memory region %s (0x%08X - 0x%08X)\n", resource->description, resource->base, resource->base + resource->size - 1));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* create generic block allocator object to handle it */
+	allocator = mali_block_allocator_create(resource->base, resource->cpu_usage_adjust, resource->size, resource->description );
+
+	if (NULL == allocator)
+	{
+		MALI_DEBUG_PRINT(1, ("Memory bank registration failed\n"));
+		_mali_osk_mem_unreqregion(resource->base, resource->size);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* save lowlevel cleanup info */
+	allocator->alloc_order = alloc_order;
+
+	cleanup_data = _mali_osk_malloc(sizeof(dedicated_memory_info));
+
+	if (NULL == cleanup_data)
+	{
+		_mali_osk_mem_unreqregion(resource->base, resource->size);
+		allocator->destroy(allocator);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	cleanup_data->base = resource->base;
+	cleanup_data->size = resource->size;
+
+	cleanup_data->next = mem_region_registrations;
+	mem_region_registrations = cleanup_data;
+
+	/* link in the allocator: insertion into ordered list
+	 * resources of the same alloc_order will be Last-in-first */
+	next_allocator_list = &physical_memory_allocators;
+
+	while ( NULL != *next_allocator_list &&
+			(*next_allocator_list)->alloc_order < alloc_order )
+	{
+		next_allocator_list = &((*next_allocator_list)->next);
+	}
+
+	allocator->next = (*next_allocator_list);
+	(*next_allocator_list) = allocator;
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t mali_kernel_memory_mmu_interrupt_handler_upper_half(void * data)
+{
+	mali_kernel_memory_mmu * mmu;
+	u32 int_stat;
+	mali_core_renderunit *core;
+
+	if (mali_benchmark) MALI_SUCCESS;
+
+	mmu = (mali_kernel_memory_mmu *)data;
+
+	MALI_DEBUG_ASSERT_POINTER(mmu);
+
+	/* Pointer to core holding this MMU */
+	core = (mali_core_renderunit *)mmu->core;
+	if(core && (CORE_OFF == core->state))
+	{
+		MALI_SUCCESS;
+	}
+
+
+	/* check if it was our device which caused the interrupt (we could be sharing the IRQ line) */
+	int_stat = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_INT_STATUS);
+	if (0 == int_stat)
+	{
+		MALI_ERROR(_MALI_OSK_ERR_FAULT); /* no bits set, we are sharing the IRQ line and someone else caused the interrupt */
+	}
+
+
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, 0);
+
+	mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS);
+
+	if (int_stat & MALI_MMU_INTERRUPT_PAGE_FAULT)
+	{
+		_mali_osk_irq_schedulework(mmu->irq);
+	}
+	if (int_stat & MALI_MMU_INTERRUPT_READ_BUS_ERROR)
+	{
+		/* clear interrupt flag */
+		mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_CLEAR, MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+		/* reenable it */
+		mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, mali_mmu_register_read(mmu, MALI_MMU_REGISTER_INT_MASK) | MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+	}
+
+	MALI_SUCCESS;
+}
+
+
+static void mali_kernel_mmu_bus_reset(mali_kernel_memory_mmu * mmu)
+{
+
+#if defined(USING_MALI200)
+	int i;
+	const int replay_buffer_check_interval = 10; /* must be below 1000 */
+	const int replay_buffer_max_number_of_checks = 100;
+#endif
+
+	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	/* add an extra reference while handling the page fault */
+	mmu->usage_count++;
+	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+	MALI_DEBUG_PRINT(4, ("Sending stop bus request to cores\n"));
+	/* request to stop the bus, but don't wait for it to actually stop */
+	_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP1_STOP_BUS_FOR_ALL_CORES, (u32)mmu);
+
+#if defined(USING_MALI200)
+	/* no new request will come from any of the connected cores from now
+	 * we must now flush the playback buffer for any requests queued already
+	 */
+
+	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+	MALI_DEBUG_PRINT(4, ("Switching to the special page fault flush page directory\n"));
+	/* don't use the mali_mmu_activate_address_space function here as we can't stall the MMU */
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, mali_page_fault_flush_page_directory);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ZAP_CACHE);
+	/* resume the MMU */
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_CLEAR, MALI_MMU_INTERRUPT_PAGE_FAULT);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_PAGE_FAULT_DONE);
+	/* the MMU will now play back all the requests, all going to our special page fault flush data page */
+
+	/* just to be safe, check that the playback buffer is empty before continuing */
+	if (!mali_benchmark) {
+		for (i = 0; i < replay_buffer_max_number_of_checks; i++)
+		{
+			if (mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_REPLAY_BUFFER_EMPTY) break;
+			_mali_osk_time_ubusydelay(replay_buffer_check_interval);
+		}
+
+		MALI_DEBUG_PRINT_IF(1, i == replay_buffer_max_number_of_checks, ("MMU: %s: Failed to flush replay buffer on page fault\n", mmu->description));
+		MALI_DEBUG_PRINT(1, ("Replay playback took %ld usec\n", i * replay_buffer_check_interval));
+	}
+
+	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+#endif
+	/* notify all subsystems that the core should be reset once the bus is actually stopped */
+	MALI_DEBUG_PRINT(4,("Sending job abort command to subsystems\n"));
+	_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP2_RESET_ALL_CORES_AND_ABORT_THEIR_JOBS, (u32)mmu);
+
+	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* reprogram the MMU */
+	mali_mmu_raw_reset(mmu);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, MALI_MMU_INTERRUPT_PAGE_FAULT | MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, mali_empty_page_directory); /* no session is active, so just activate the empty page directory */
+	mali_mmu_enable_paging(mmu);
+
+	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* release the extra address space reference, will schedule */
+	mali_memory_core_mmu_release_address_space_reference(mmu);
+
+	/* resume normal operation */
+	_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP3_CONTINUE_JOB_HANDLING, (u32)mmu);
+	MALI_DEBUG_PRINT(4, ("Page fault handling complete\n"));
+}
+
+static void mali_mmu_raw_reset(mali_kernel_memory_mmu * mmu)
+{
+	const int max_loop_count = 100;
+	const int delay_in_usecs = 1;
+
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, 0xCAFEBABE);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_SOFT_RESET);
+
+	if (!mali_benchmark)
+	{
+		int i;
+		for (i = 0; i < max_loop_count; ++i)
+		{
+			if (mali_mmu_register_read(mmu, MALI_MMU_REGISTER_DTE_ADDR) == 0)
+			{
+				break;
+			}
+			_mali_osk_time_ubusydelay(delay_in_usecs);
+		}
+		MALI_DEBUG_PRINT_IF(1, (max_loop_count == i), ("Reset request failed, MMU status is 0x%08X\n", mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS)));
+	}
+}
+
+static void mali_mmu_enable_paging(mali_kernel_memory_mmu * mmu)
+{
+	const int max_loop_count = 100;
+	const int delay_in_usecs = 1;
+
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ENABLE_PAGING);
+
+	if (!mali_benchmark)
+	{
+		int i;
+		for (i = 0; i < max_loop_count; ++i)
+		{
+			if (mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_PAGING_ENABLED)
+			{
+				break;
+			}
+			_mali_osk_time_ubusydelay(delay_in_usecs);
+		}
+		MALI_DEBUG_PRINT_IF(1, (max_loop_count == i), ("Enable paging request failed, MMU status is 0x%08X\n", mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS)));
+	}
+}
+
+static mali_bool mali_mmu_enable_stall(mali_kernel_memory_mmu * mmu)
+{
+	const int max_loop_count = 100;
+	const int delay_in_usecs = 999;
+	int i;
+
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ENABLE_STALL);
+
+	if (!mali_benchmark)
+	{
+		for (i = 0; i < max_loop_count; ++i)
+		{
+			if (mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_STALL_ACTIVE)
+			{
+				break;
+			}
+			_mali_osk_time_ubusydelay(delay_in_usecs);
+		}
+		MALI_DEBUG_PRINT_IF(1, (max_loop_count == i), ("Enable stall request failed, MMU status is 0x%08X\n", mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS)));
+		if (max_loop_count == i)
+		{
+			return MALI_FALSE;
+		}
+	}
+
+	return MALI_TRUE;
+}
+
+static void mali_mmu_disable_stall(mali_kernel_memory_mmu * mmu)
+{
+	const int max_loop_count = 100;
+	const int delay_in_usecs = 1;
+	int i;
+
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_DISABLE_STALL);
+
+	if (!mali_benchmark)
+	{
+		for (i = 0; i < max_loop_count; ++i)
+		{
+			if ((mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_STALL_ACTIVE) == 0)
+			{
+				break;
+			}
+			_mali_osk_time_ubusydelay(delay_in_usecs);
+		}
+		MALI_DEBUG_PRINT_IF(1, (max_loop_count == i), ("Disable stall request failed, MMU status is 0x%08X\n", mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS)));
+	}
+}
+
+void mali_kernel_mmu_reset(void * input_mmu)
+{
+	mali_kernel_memory_mmu * mmu;
+	MALI_DEBUG_ASSERT_POINTER(input_mmu);
+	mmu = (mali_kernel_memory_mmu *)input_mmu;
+
+	MALI_DEBUG_PRINT(4, ("Mali MMU: mali_kernel_mmu_reset: %s\n", mmu->description));
+
+	if ( 0 != mmu->in_page_fault_handler)
+	{
+		/* This is possible if the bus can never be stopped for some reason */
+		MALI_PRINT_ERROR(("Stopping the Memory bus not possible. Mali reset could not be performed."));
+		return;
+	}
+	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	mali_mmu_raw_reset(mmu);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, MALI_MMU_INTERRUPT_PAGE_FAULT | MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, mali_empty_page_directory); /* no session is active, so just activate the empty page directory */
+	mali_mmu_enable_paging(mmu);
+	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+}
+
+void mali_kernel_mmu_force_bus_reset(void * input_mmu)
+{
+	mali_kernel_memory_mmu * mmu;
+	MALI_DEBUG_ASSERT_POINTER(input_mmu);
+	mmu = (mali_kernel_memory_mmu *)input_mmu;
+	if ( 0 != mmu->in_page_fault_handler)
+	{
+		/* This is possible if the bus can never be stopped for some reason */
+		MALI_PRINT_ERROR(("Stopping the Memory bus not possible. Mali reset could not be performed."));
+		return;
+	}
+	MALI_DEBUG_PRINT(1, ("Mali MMU: Force_bus_reset.\n"));
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_MASK, 0);
+	mali_kernel_mmu_bus_reset(mmu);
+}
+
+
+static void mali_kernel_memory_mmu_interrupt_handler_bottom_half(void * data)
+{
+	mali_kernel_memory_mmu * mmu;
+	u32 raw, fault_address, status;
+	mali_core_renderunit *core;
+
+	MALI_DEBUG_PRINT(1, ("mali_kernel_memory_mmu_interrupt_handler_bottom_half\n"));
+	if (NULL == data)
+	{
+		MALI_PRINT_ERROR(("MMU IRQ work queue: NULL argument"));
+		return; /* Error */
+	}
+	mmu = (mali_kernel_memory_mmu*)data;
+
+	MALI_DEBUG_PRINT(4, ("Locking subsystems\n"));
+	/* lock all subsystems */
+	_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP0_LOCK_SUBSYSTEM, (u32)mmu);
+
+	/* Pointer to core holding this MMU */
+	core = (mali_core_renderunit *)mmu->core;
+
+	if(CORE_OFF == core->state)
+	{
+		_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP4_UNLOCK_SUBSYSTEM, (u32)mmu);
+		return;
+	}
+
+	raw = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_INT_RAWSTAT);
+	status = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS);
+
+	if ( (0==(raw & MALI_MMU_INTERRUPT_PAGE_FAULT)) &&  (0==(status & MALI_MMU_STATUS_BIT_PAGE_FAULT_ACTIVE)) )
+	{
+		MALI_DEBUG_PRINT(1, ("MMU: Page fault bottom half: No Irq found.\n"));
+		MALI_DEBUG_PRINT(4, ("Unlocking subsystems"));
+		_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP4_UNLOCK_SUBSYSTEM, (u32)mmu);
+		return;
+	}
+
+	mmu->in_page_fault_handler = 1;
+
+	fault_address = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_PAGE_FAULT_ADDR);
+	MALI_PRINT(("Page fault detected at 0x%x from bus id %d of type %s on %s\n",
+				(void*)fault_address,
+				(status >> 6) & 0x1F,
+				(status & 32) ? "write" : "read",
+				mmu->description)
+			  );
+
+	if (NULL == mmu->active_session)
+	{
+		MALI_PRINT(("Spurious memory access detected from MMU %s\n", mmu->description));
+	}
+	else
+	{
+		MALI_PRINT(("Active page directory at 0x%08X\n", mmu->active_session->page_directory));
+		MALI_PRINT(("Info from page table for VA 0x%x:\n", (void*)fault_address));
+		MALI_PRINT(("DTE entry: PTE at 0x%x marked as %s\n",
+					(void*)(_mali_osk_mem_ioread32(mmu->active_session->page_directory_mapped,
+					MALI_MMU_PDE_ENTRY(fault_address) * sizeof(u32)) & ~MALI_MMU_FLAGS_MASK),
+					_mali_osk_mem_ioread32(mmu->active_session->page_directory_mapped,
+					MALI_MMU_PDE_ENTRY(fault_address) * sizeof(u32)) & MALI_MMU_FLAGS_PRESENT ? "present" : "not present"
+				   ));
+
+		if (_mali_osk_mem_ioread32(mmu->active_session->page_directory_mapped, MALI_MMU_PDE_ENTRY(fault_address) * sizeof(u32)) & MALI_MMU_FLAGS_PRESENT)
+		{
+			mali_io_address pte;
+			u32 data;
+			pte = mmu->active_session->page_entries_mapped[MALI_MMU_PDE_ENTRY(fault_address)];
+			data = _mali_osk_mem_ioread32(pte, MALI_MMU_PTE_ENTRY(fault_address) * sizeof(u32));
+			MALI_PRINT(("PTE entry: Page at 0x%x, %s %s %s\n",
+						(void*)(data & ~MALI_MMU_FLAGS_MASK),
+						data & MALI_MMU_FLAGS_PRESENT ? "present" : "not present",
+						data & MALI_MMU_FLAGS_READ_PERMISSION ? "readable" : "",
+						data & MALI_MMU_FLAGS_WRITE_PERMISSION ? "writable" : ""
+					   ));
+		}
+		else
+		{
+			MALI_PRINT(("PTE entry: Not present\n"));
+		}
+	}
+
+
+	mali_kernel_mmu_bus_reset(mmu);
+
+	mmu->in_page_fault_handler = 0;
+
+	/* unlock all subsystems */
+	MALI_DEBUG_PRINT(4, ("Unlocking subsystems"));
+	_mali_kernel_core_broadcast_subsystem_message(MMU_KILL_STEP4_UNLOCK_SUBSYSTEM, (u32)mmu);
+
+}
+
+
+static u32 mali_mmu_register_read(mali_kernel_memory_mmu * unit, mali_mmu_register reg)
+{
+	u32 val;
+
+	if (mali_benchmark) return 0;
+
+	val = _mali_osk_mem_ioread32(unit->mapped_registers, (u32)reg * sizeof(u32));
+
+	MALI_DEBUG_PRINT(6, ("mali_mmu_register_read addr:0x%04X val:0x%08x\n", (u32)reg * sizeof(u32),val));
+
+	return val;
+}
+
+static void mali_mmu_register_write(mali_kernel_memory_mmu * unit, mali_mmu_register reg, u32 val)
+{
+	if (mali_benchmark) return;
+
+	MALI_DEBUG_PRINT(6, ("mali_mmu_register_write  addr:0x%04X val:0x%08x\n", (u32)reg * sizeof(u32), val));
+
+	_mali_osk_mem_iowrite32(unit->mapped_registers, (u32)reg * sizeof(u32), val);
+}
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+static mali_physical_memory_allocation_result ump_memory_commit(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info)
+{
+	ump_dd_handle ump_mem;
+	u32 nr_blocks;
+	u32 i;
+	ump_dd_physical_block * ump_blocks;
+	ump_mem_allocation *ret_allocation;
+
+    MALI_DEBUG_ASSERT_POINTER(ctx);
+    MALI_DEBUG_ASSERT_POINTER(engine);
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+    MALI_DEBUG_ASSERT_POINTER(alloc_info);
+
+	ret_allocation = _mali_osk_malloc( sizeof( ump_mem_allocation ) );
+	if ( NULL==ret_allocation ) return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	ump_mem = (ump_dd_handle)ctx;
+
+	MALI_DEBUG_PRINT(4, ("In ump_memory_commit\n"));
+
+	nr_blocks = ump_dd_phys_block_count_get(ump_mem);
+
+	MALI_DEBUG_PRINT(4, ("Have %d blocks\n", nr_blocks));
+
+	if (nr_blocks == 0)
+	{
+		MALI_DEBUG_PRINT(1, ("No block count\n"));
+		_mali_osk_free( ret_allocation );
+		return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+	}
+
+	ump_blocks = _mali_osk_malloc(sizeof(*ump_blocks)*nr_blocks );
+	if ( NULL==ump_blocks )
+	{
+		_mali_osk_free( ret_allocation );
+		return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+	}
+
+	if (UMP_DD_INVALID == ump_dd_phys_blocks_get(ump_mem, ump_blocks, nr_blocks))
+	{
+		_mali_osk_free(ump_blocks);
+		_mali_osk_free( ret_allocation );
+		return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+	}
+
+	/* Store away the initial offset for unmapping purposes */
+	ret_allocation->initial_offset = *offset;
+
+	for(i=0; i<nr_blocks; ++i)
+	{
+		MALI_DEBUG_PRINT(4, ("Mapping in 0x%08x size %d\n", ump_blocks[i].addr , ump_blocks[i].size));
+		if (_MALI_OSK_ERR_OK != mali_allocation_engine_map_physical(engine, descriptor, *offset, ump_blocks[i].addr , 0, ump_blocks[i].size ))
+		{
+			u32 size_allocated = *offset - ret_allocation->initial_offset;
+			MALI_DEBUG_PRINT(1, ("Mapping of external memory failed\n"));
+
+			/* unmap all previous blocks (if any) */
+			mali_allocation_engine_unmap_physical(engine, descriptor, ret_allocation->initial_offset, size_allocated, (_mali_osk_mem_mapregion_flags_t)0 );
+
+			_mali_osk_free(ump_blocks);
+			_mali_osk_free(ret_allocation);
+			return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+		}
+		*offset += ump_blocks[i].size;
+	}
+
+	if (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE)
+	{
+		/* Map in an extra virtual guard page at the end of the VMA */
+		MALI_DEBUG_PRINT(4, ("Mapping in extra guard page\n"));
+		if (_MALI_OSK_ERR_OK != mali_allocation_engine_map_physical(engine, descriptor, *offset, ump_blocks[0].addr , 0, _MALI_OSK_MALI_PAGE_SIZE ))
+		{
+			u32 size_allocated = *offset - ret_allocation->initial_offset;
+			MALI_DEBUG_PRINT(1, ("Mapping of external memory (guard page) failed\n"));
+
+			/* unmap all previous blocks (if any) */
+			mali_allocation_engine_unmap_physical(engine, descriptor, ret_allocation->initial_offset, size_allocated, (_mali_osk_mem_mapregion_flags_t)0 );
+
+			_mali_osk_free(ump_blocks);
+			_mali_osk_free(ret_allocation);
+			return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+		}
+		*offset += _MALI_OSK_MALI_PAGE_SIZE;
+	}
+
+	_mali_osk_free( ump_blocks );
+
+	ret_allocation->engine = engine;
+	ret_allocation->descriptor = descriptor;
+	ret_allocation->ump_mem = ump_mem;
+	ret_allocation->size_allocated = *offset - ret_allocation->initial_offset;
+
+	alloc_info->ctx = NULL;
+	alloc_info->handle = ret_allocation;
+	alloc_info->next = NULL;
+	alloc_info->release = ump_memory_release;
+
+	return MALI_MEM_ALLOC_FINISHED;
+}
+
+static void ump_memory_release(void * ctx, void * handle)
+{
+	ump_dd_handle ump_mem;
+	ump_mem_allocation *allocation;
+
+	allocation = (ump_mem_allocation *)handle;
+
+	MALI_DEBUG_ASSERT_POINTER( allocation );
+
+	ump_mem = allocation->ump_mem;
+
+	MALI_DEBUG_ASSERT(UMP_DD_HANDLE_INVALID!=ump_mem);
+
+	/* At present, this is a no-op. But, it allows the mali_address_manager to
+	 * do unmapping of a subrange in future. */
+	mali_allocation_engine_unmap_physical( allocation->engine,
+										   allocation->descriptor,
+										   allocation->initial_offset,
+										   allocation->size_allocated,
+										   (_mali_osk_mem_mapregion_flags_t)0
+										   );
+	_mali_osk_free( allocation );
+
+
+	ump_dd_reference_release(ump_mem) ;
+	return;
+}
+
+_mali_osk_errcode_t _mali_ukk_attach_ump_mem( _mali_uk_attach_ump_mem_s *args )
+{
+	ump_dd_handle ump_mem;
+	mali_physical_memory_allocator external_memory_allocator;
+	memory_session * session_data;
+	mali_memory_allocation * descriptor;
+	int md;
+
+  	MALI_DEBUG_ASSERT_POINTER(args);
+  	MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+	session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+	MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+	/* check arguments */
+	/* NULL might be a valid Mali address */
+	if ( ! args->size) MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+
+	/* size must be a multiple of the system page size */
+	if ( args->size % _MALI_OSK_MALI_PAGE_SIZE ) MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+
+	MALI_DEBUG_PRINT(3,
+	                 ("Requested to map ump memory with secure id %d into virtual memory 0x%08X, size 0x%08X\n",
+	                  args->secure_id, args->mali_address, args->size));
+
+	ump_mem = ump_dd_handle_create_from_secure_id( (int)args->secure_id ) ;
+
+	if ( UMP_DD_HANDLE_INVALID==ump_mem ) MALI_ERROR(_MALI_OSK_ERR_FAULT);
+
+	descriptor = _mali_osk_calloc(1, sizeof(mali_memory_allocation));
+	if (NULL == descriptor)
+	{
+		ump_dd_reference_release(ump_mem);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	descriptor->size = args->size;
+	descriptor->mapping = NULL;
+	descriptor->mali_address = args->mali_address;
+	descriptor->mali_addr_mapping_info = (void*)session_data;
+	descriptor->process_addr_mapping_info = NULL; /* do not map to process address space */
+	descriptor->lock = session_data->lock;
+	if (args->flags & _MALI_MAP_EXTERNAL_MAP_GUARD_PAGE)
+	{
+		descriptor->flags = MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE;
+	}
+	_mali_osk_list_init( &descriptor->list );
+
+	if (_MALI_OSK_ERR_OK != mali_descriptor_mapping_allocate_mapping(session_data->descriptor_mapping, descriptor, &md))
+	{
+		ump_dd_reference_release(ump_mem);
+		_mali_osk_free(descriptor);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	external_memory_allocator.allocate = ump_memory_commit;
+	external_memory_allocator.allocate_page_table_block = NULL;
+	external_memory_allocator.ctx = ump_mem;
+	external_memory_allocator.name = "UMP Memory";
+	external_memory_allocator.next = NULL;
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (_MALI_OSK_ERR_OK != mali_allocation_engine_allocate_memory(memory_engine, descriptor, &external_memory_allocator, NULL))
+	{
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+		mali_descriptor_mapping_free(session_data->descriptor_mapping, md);
+		ump_dd_reference_release(ump_mem);
+		_mali_osk_free(descriptor);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	args->cookie = md;
+
+	MALI_DEBUG_PRINT(5,("Returning from UMP attach\n"));
+
+	/* All OK */
+	MALI_SUCCESS;
+}
+
+
+_mali_osk_errcode_t _mali_ukk_release_ump_mem( _mali_uk_release_ump_mem_s *args )
+{
+	mali_memory_allocation * descriptor;
+    memory_session * session_data;
+
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+    if (_MALI_OSK_ERR_OK != mali_descriptor_mapping_get(session_data->descriptor_mapping, args->cookie, (void**)&descriptor))
+	{
+		MALI_DEBUG_PRINT(1, ("Invalid memory descriptor %d used to release ump memory\n", args->cookie));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	mali_descriptor_mapping_free(session_data->descriptor_mapping, args->cookie);
+
+	_mali_osk_lock_wait( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+
+	mali_allocation_engine_release_memory(memory_engine, descriptor);
+
+	_mali_osk_lock_signal( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+
+	_mali_osk_free(descriptor);
+
+	MALI_SUCCESS;
+
+}
+#endif /* MALI_USE_UNIFIED_MEMORY_PROVIDER != 0 */
+
+
+static mali_physical_memory_allocation_result external_memory_commit(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info)
+{
+	u32 * data;
+	external_mem_allocation * ret_allocation;
+
+    MALI_DEBUG_ASSERT_POINTER(ctx);
+    MALI_DEBUG_ASSERT_POINTER(engine);
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+    MALI_DEBUG_ASSERT_POINTER(alloc_info);
+
+	ret_allocation = _mali_osk_malloc( sizeof(external_mem_allocation) );
+
+	if ( NULL == ret_allocation )
+	{
+		return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+	}
+
+	data = (u32*)ctx;
+
+	ret_allocation->engine = engine;
+	ret_allocation->descriptor = descriptor;
+	ret_allocation->initial_offset = *offset;
+
+	alloc_info->ctx = NULL;
+	alloc_info->handle = ret_allocation;
+	alloc_info->next = NULL;
+	alloc_info->release = external_memory_release;
+
+	MALI_DEBUG_PRINT(3, ("External map: mapping phys 0x%08X at mali virtual address 0x%08X staring at offset 0x%08X length 0x%08X\n", data[0], descriptor->mali_address, *offset, data[1]));
+
+	if (_MALI_OSK_ERR_OK != mali_allocation_engine_map_physical(engine, descriptor, *offset, data[0], 0, data[1]))
+	{
+		MALI_DEBUG_PRINT(1, ("Mapping of external memory failed\n"));
+		_mali_osk_free(ret_allocation);
+		return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+	}
+	*offset += data[1];
+
+	if (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE)
+	{
+		/* Map in an extra virtual guard page at the end of the VMA */
+		MALI_DEBUG_PRINT(4, ("Mapping in extra guard page\n"));
+		if (_MALI_OSK_ERR_OK != mali_allocation_engine_map_physical(engine, descriptor, *offset, data[0], 0, _MALI_OSK_MALI_PAGE_SIZE))
+		{
+			u32 size_allocated = *offset - ret_allocation->initial_offset;
+			MALI_DEBUG_PRINT(1, ("Mapping of external memory (guard page) failed\n"));
+
+			/* unmap what we previously mapped */
+			mali_allocation_engine_unmap_physical(engine, descriptor, ret_allocation->initial_offset, size_allocated, (_mali_osk_mem_mapregion_flags_t)0 );
+			_mali_osk_free(ret_allocation);
+			return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+		}
+		*offset += _MALI_OSK_MALI_PAGE_SIZE;
+	}
+
+	ret_allocation->size = *offset - ret_allocation->initial_offset;
+
+	return MALI_MEM_ALLOC_FINISHED;
+}
+
+static void external_memory_release(void * ctx, void * handle)
+{
+	external_mem_allocation * allocation;
+
+	allocation = (external_mem_allocation *) handle;
+	MALI_DEBUG_ASSERT_POINTER( allocation );
+
+	/* At present, this is a no-op. But, it allows the mali_address_manager to
+	 * do unmapping of a subrange in future. */
+
+	mali_allocation_engine_unmap_physical( allocation->engine,
+										   allocation->descriptor,
+										   allocation->initial_offset,
+										   allocation->size,
+										   (_mali_osk_mem_mapregion_flags_t)0
+										   );
+
+	_mali_osk_free( allocation );
+
+	return;
+}
+
+_mali_osk_errcode_t _mali_ukk_map_external_mem( _mali_uk_map_external_mem_s *args )
+{
+	mali_physical_memory_allocator external_memory_allocator;
+    memory_session * session_data;
+    u32 info[2];
+	mali_memory_allocation * descriptor;
+	int md;
+
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+    external_memory_allocator.allocate = external_memory_commit;
+	external_memory_allocator.allocate_page_table_block = NULL;
+	external_memory_allocator.ctx = &info[0];
+	external_memory_allocator.name = "External Memory";
+	external_memory_allocator.next = NULL;
+
+	/* check arguments */
+	/* NULL might be a valid Mali address */
+	if ( ! args->size) MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+
+	/* size must be a multiple of the system page size */
+	if ( args->size % _MALI_OSK_MALI_PAGE_SIZE ) MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+
+	MALI_DEBUG_PRINT(3,
+	        ("Requested to map physical memory 0x%x-0x%x into virtual memory 0x%x\n",
+	        (void*)args->phys_addr,
+	        (void*)(args->phys_addr + args->size -1),
+	        (void*)args->mali_address)
+	);
+
+	/* Validate the mali physical range */
+	MALI_CHECK_NO_ERROR( mali_kernel_core_validate_mali_phys_range( args->phys_addr, args->size ) );
+
+	info[0] = args->phys_addr;
+	info[1] = args->size;
+
+	descriptor = _mali_osk_calloc(1, sizeof(mali_memory_allocation));
+	if (NULL == descriptor) MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+
+	descriptor->size = args->size;
+	descriptor->mapping = NULL;
+	descriptor->mali_address = args->mali_address;
+	descriptor->mali_addr_mapping_info = (void*)session_data;
+	descriptor->process_addr_mapping_info = NULL; /* do not map to process address space */
+	descriptor->lock = session_data->lock;
+	if (args->flags & _MALI_MAP_EXTERNAL_MAP_GUARD_PAGE)
+	{
+		descriptor->flags = MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE;
+	}
+	_mali_osk_list_init( &descriptor->list );
+
+	if (_MALI_OSK_ERR_OK != mali_descriptor_mapping_allocate_mapping(session_data->descriptor_mapping, descriptor, &md))
+	{
+		_mali_osk_free(descriptor);
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (_MALI_OSK_ERR_OK != mali_allocation_engine_allocate_memory(memory_engine, descriptor, &external_memory_allocator, NULL))
+	{
+		_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+		mali_descriptor_mapping_free(session_data->descriptor_mapping, md);
+		_mali_osk_free(descriptor);
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	args->cookie = md;
+
+	MALI_DEBUG_PRINT(5,("Returning from range_map_external_memory\n"));
+
+	/* All OK */
+	MALI_SUCCESS;
+}
+
+
+_mali_osk_errcode_t _mali_ukk_unmap_external_mem( _mali_uk_unmap_external_mem_s *args )
+{
+	mali_memory_allocation * descriptor;
+    memory_session * session_data;
+
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+    MALI_CHECK_NON_NULL(session_data, _MALI_OSK_ERR_INVALID_ARGS);
+
+    if (_MALI_OSK_ERR_OK != mali_descriptor_mapping_get(session_data->descriptor_mapping, args->cookie, (void**)&descriptor))
+	{
+		MALI_DEBUG_PRINT(1, ("Invalid memory descriptor %d used to unmap external memory\n", args->cookie));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	mali_descriptor_mapping_free(session_data->descriptor_mapping, args->cookie);
+
+	_mali_osk_lock_wait( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+
+	mali_allocation_engine_release_memory(memory_engine, descriptor);
+
+	_mali_osk_lock_signal( session_data->lock, _MALI_OSK_LOCKMODE_RW );
+
+	_mali_osk_free(descriptor);
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_init_mem( _mali_uk_init_mem_s *args )
+{
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+	args->memory_size = 2 * 1024 * 1024 * 1024UL; /* 2GB address space */
+	args->mali_address_base = 1 * 1024 * 1024 * 1024UL; /* staring at 1GB, causing this layout: (0-1GB unused)(1GB-3G usage by Mali)(3G-4G unused) */
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_term_mem( _mali_uk_term_mem_s *args )
+{
+    MALI_DEBUG_ASSERT_POINTER(args);
+    MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_mmu_page_table_cache_create(void)
+{
+    page_table_cache.lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_ORDERED | _MALI_OSK_LOCKFLAG_ONELOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 110);
+    MALI_CHECK_NON_NULL( page_table_cache.lock, _MALI_OSK_ERR_FAULT );
+	_MALI_OSK_INIT_LIST_HEAD(&page_table_cache.partial);
+	_MALI_OSK_INIT_LIST_HEAD(&page_table_cache.full);
+    MALI_SUCCESS;
+}
+
+void mali_mmu_page_table_cache_destroy(void)
+{
+	mali_mmu_page_table_allocation * alloc, *temp;
+
+	_MALI_OSK_LIST_FOREACHENTRY(alloc, temp, &page_table_cache.partial, mali_mmu_page_table_allocation, list)
+	{
+		MALI_DEBUG_PRINT_IF(1, 0 != alloc->usage_count, ("Destroying page table cache while pages are tagged as in use. %d allocations still marked as in use.\n", alloc->usage_count));
+		_mali_osk_list_del(&alloc->list);
+		alloc->pages.release(&alloc->pages);
+		_mali_osk_free(alloc->usage_map);
+		_mali_osk_free(alloc);
+	}
+
+	MALI_DEBUG_PRINT_IF(1, 0 == _mali_osk_list_empty(&page_table_cache.full), ("Page table cache full list contains one or more elements \n"));
+
+	_MALI_OSK_LIST_FOREACHENTRY(alloc, temp, &page_table_cache.full, mali_mmu_page_table_allocation, list)
+	{
+		MALI_DEBUG_PRINT(1, ("Destroy alloc 0x%08X with usage count %d\n", (u32)alloc, alloc->usage_count));
+		_mali_osk_list_del(&alloc->list);
+		alloc->pages.release(&alloc->pages);
+		_mali_osk_free(alloc->usage_map);
+		_mali_osk_free(alloc);
+	}
+
+	_mali_osk_lock_term(page_table_cache.lock);
+}
+
+_mali_osk_errcode_t mali_mmu_get_table_page(u32 *table_page, mali_io_address *mapping)
+{
+	_mali_osk_lock_wait(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (0 == _mali_osk_list_empty(&page_table_cache.partial))
+	{
+		mali_mmu_page_table_allocation * alloc = _MALI_OSK_LIST_ENTRY(page_table_cache.partial.next, mali_mmu_page_table_allocation, list);
+		int page_number = _mali_osk_find_first_zero_bit(alloc->usage_map, alloc->num_pages);
+		MALI_DEBUG_PRINT(6, ("Partial page table allocation found, using page offset %d\n", page_number));
+		_mali_osk_set_nonatomic_bit(page_number, alloc->usage_map);
+		alloc->usage_count++;
+		if (alloc->num_pages == alloc->usage_count)
+		{
+			/* full, move alloc to full list*/
+			_mali_osk_list_move(&alloc->list, &page_table_cache.full);
+		}
+    	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+
+        *table_page = (MALI_MMU_PAGE_SIZE * page_number) + alloc->pages.phys_base;
+		*mapping =  (mali_io_address)((MALI_MMU_PAGE_SIZE * page_number) + (u32)alloc->pages.mapping);
+		MALI_DEBUG_PRINT(4, ("Page table allocated for VA=0x%08X, MaliPA=0x%08X\n", *mapping, *table_page ));
+        MALI_SUCCESS;
+	}
+	else
+	{
+		mali_mmu_page_table_allocation * alloc;
+		/* no free pages, allocate a new one */
+
+		alloc = (mali_mmu_page_table_allocation *)_mali_osk_calloc(1, sizeof(mali_mmu_page_table_allocation));
+		if (NULL == alloc)
+		{
+        	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+            *table_page = MALI_INVALID_PAGE;
+			MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+		}
+
+		_MALI_OSK_INIT_LIST_HEAD(&alloc->list);
+
+		if (_MALI_OSK_ERR_OK != mali_allocation_engine_allocate_page_tables(memory_engine, &alloc->pages, physical_memory_allocators))
+		{
+			MALI_DEBUG_PRINT(1, ("No more memory for page tables\n"));
+			_mali_osk_free(alloc);
+        	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+            *table_page = MALI_INVALID_PAGE;
+			*mapping = NULL;
+			MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+		}
+
+		/* create the usage map */
+		alloc->num_pages = alloc->pages.size / MALI_MMU_PAGE_SIZE;
+		alloc->usage_count = 1;
+		MALI_DEBUG_PRINT(3, ("New page table cache expansion, %d pages in new cache allocation\n", alloc->num_pages));
+		alloc->usage_map = _mali_osk_calloc(1, ((alloc->num_pages + BITS_PER_LONG - 1) & ~(BITS_PER_LONG-1) / BITS_PER_LONG) * sizeof(unsigned long));
+		if (NULL == alloc->usage_map)
+		{
+			MALI_DEBUG_PRINT(1, ("Failed to allocate memory to describe MMU page table cache usage\n"));
+			alloc->pages.release(&alloc->pages);
+			_mali_osk_free(alloc);
+        	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+            *table_page = MALI_INVALID_PAGE;
+			*mapping = NULL;
+            MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+		}
+
+		/* clear memory allocation */
+		fill_page(alloc->pages.mapping, 0);
+
+		_mali_osk_set_nonatomic_bit(0, alloc->usage_map);
+
+		if (alloc->num_pages > 1)
+		{
+			_mali_osk_list_add(&alloc->list, &page_table_cache.partial);
+		}
+		else
+		{
+			_mali_osk_list_add(&alloc->list, &page_table_cache.full);
+		}
+
+    	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+		*table_page = alloc->pages.phys_base; /* return the first page */
+		*mapping = alloc->pages.mapping; /* Mapping for first page */
+		MALI_DEBUG_PRINT(4, ("Page table allocated for VA=0x%08X, MaliPA=0x%08X\n", *mapping, *table_page ));
+        MALI_SUCCESS;
+	}
+}
+
+void mali_mmu_release_table_page(u32 pa)
+{
+	mali_mmu_page_table_allocation * alloc, * temp_alloc;
+
+	MALI_DEBUG_PRINT_IF(1, pa & 4095, ("Bad page address 0x%x given to mali_mmu_release_table_page\n", (void*)pa));
+
+	MALI_DEBUG_PRINT(4, ("Releasing table page 0x%08X to the cache\n", pa));
+
+   	_mali_osk_lock_wait(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* find the entry this address belongs to */
+	/* first check the partial list */
+	_MALI_OSK_LIST_FOREACHENTRY(alloc, temp_alloc, &page_table_cache.partial, mali_mmu_page_table_allocation, list)
+	{
+		u32 start = alloc->pages.phys_base;
+		u32 last = start + (alloc->num_pages - 1) * MALI_MMU_PAGE_SIZE;
+		if (pa >= start && pa <= last)
+		{
+            MALI_DEBUG_ASSERT(0 != _mali_osk_test_bit((pa - start)/MALI_MMU_PAGE_SIZE, alloc->usage_map));
+			_mali_osk_clear_nonatomic_bit((pa - start)/MALI_MMU_PAGE_SIZE, alloc->usage_map);
+			alloc->usage_count--;
+
+			_mali_osk_memset((void*)( ((u32)alloc->pages.mapping) + (pa - start) ), 0, MALI_MMU_PAGE_SIZE);
+
+			if (0 == alloc->usage_count)
+			{
+				/* empty, release whole page alloc */
+				_mali_osk_list_del(&alloc->list);
+				alloc->pages.release(&alloc->pages);
+				_mali_osk_free(alloc->usage_map);
+				_mali_osk_free(alloc);
+			}
+           	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+        	MALI_DEBUG_PRINT(4, ("(partial list)Released table page 0x%08X to the cache\n", pa));
+			return;
+		}
+	}
+
+	/* the check the full list */
+	_MALI_OSK_LIST_FOREACHENTRY(alloc, temp_alloc, &page_table_cache.full, mali_mmu_page_table_allocation, list)
+	{
+		u32 start = alloc->pages.phys_base;
+		u32 last = start + (alloc->num_pages - 1) * MALI_MMU_PAGE_SIZE;
+		if (pa >= start && pa <= last)
+		{
+			_mali_osk_clear_nonatomic_bit((pa - start)/MALI_MMU_PAGE_SIZE, alloc->usage_map);
+			alloc->usage_count--;
+
+			_mali_osk_memset((void*)( ((u32)alloc->pages.mapping) + (pa - start) ), 0, MALI_MMU_PAGE_SIZE);
+
+
+			if (0 == alloc->usage_count)
+			{
+				/* empty, release whole page alloc */
+				_mali_osk_list_del(&alloc->list);
+				alloc->pages.release(&alloc->pages);
+				_mali_osk_free(alloc->usage_map);
+				_mali_osk_free(alloc);
+			}
+			else
+			{
+				/* transfer to partial list */
+				_mali_osk_list_move(&alloc->list, &page_table_cache.partial);
+			}
+
+           	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+        	MALI_DEBUG_PRINT(4, ("(full list)Released table page 0x%08X to the cache\n", pa));
+			return;
+		}
+	}
+
+	MALI_DEBUG_PRINT(1, ("pa 0x%x not found in the page table cache\n", (void*)pa));
+
+   	_mali_osk_lock_signal(page_table_cache.lock, _MALI_OSK_LOCKMODE_RW);
+}
+
+void* mali_memory_core_mmu_lookup(u32 id)
+{
+	mali_kernel_memory_mmu * mmu, * temp_mmu;
+
+	/* find an MMU with a matching id */
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &mmu_head, mali_kernel_memory_mmu, list)
+	{
+		if (id == mmu->id) return mmu;
+	}
+
+	/* not found */
+	return NULL;
+}
+
+void mali_memory_core_mmu_owner(void *core, void *mmu_ptr)
+{
+        mali_kernel_memory_mmu *mmu;
+
+        MALI_DEBUG_ASSERT_POINTER(mmu_ptr);
+        MALI_DEBUG_ASSERT_POINTER(core);
+
+        mmu = (mali_kernel_memory_mmu *)mmu_ptr;
+        mmu->core = core;
+}
+
+void mali_mmu_activate_address_space(mali_kernel_memory_mmu * mmu, u32 page_directory)
+{
+	mali_mmu_enable_stall(mmu); /* this might fail, but changing the DTE address and ZAP should work anyway... */
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_DTE_ADDR, page_directory);
+	mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ZAP_CACHE);
+	mali_mmu_disable_stall(mmu);
+}
+
+_mali_osk_errcode_t mali_memory_core_mmu_activate_page_table(void* mmu_ptr, struct mali_session_data * mali_session_data, void(*callback)(void*), void * callback_argument)
+{
+	memory_session * requested_memory_session;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
+	mali_kernel_memory_mmu * mmu;
+
+	MALI_DEBUG_ASSERT_POINTER(mmu_ptr);
+	MALI_DEBUG_ASSERT_POINTER(mali_session_data);
+
+	mmu = (mali_kernel_memory_mmu *)mmu_ptr;
+
+	MALI_DEBUG_PRINT(4, ("Asked to activate page table for session 0x%x on MMU %s\n", mali_session_data, mmu->description));
+	requested_memory_session = mali_kernel_session_manager_slot_get(mali_session_data, mali_subsystem_memory_id);
+	MALI_DEBUG_PRINT(5, ("Session 0x%x looked up as using memory session 0x%x\n", mali_session_data, requested_memory_session));
+
+	MALI_DEBUG_ASSERT_POINTER(requested_memory_session);
+
+	MALI_DEBUG_PRINT(7, ("Taking locks\n"));
+
+	_mali_osk_lock_wait(requested_memory_session->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	if (0 == mmu->usage_count)
+	{
+		/* no session currently active, activate the requested session */
+		MALI_DEBUG_ASSERT(NULL == mmu->active_session);
+		mmu->active_session = requested_memory_session;
+		mmu->usage_count = 1;
+		MALI_DEBUG_PRINT(4, ("MMU idle, activating page directory 0x%08X on MMU %s\n", requested_memory_session->page_directory, mmu->description));
+		mali_mmu_activate_address_space(mmu, requested_memory_session->page_directory);
+		{
+			/* Insert mmu into the right place in the active_mmus list so that
+			 * it is still sorted. The list must be sorted by ID so we can get
+			 * the mutexes in the right order in
+			 * _mali_ukk_mem_munmap_internal().
+			 */
+			_mali_osk_list_t *entry;
+			for (entry = requested_memory_session->active_mmus.next;
+				 entry != &requested_memory_session->active_mmus;
+				 entry = entry->next)
+			{
+				mali_kernel_memory_mmu *temp = _MALI_OSK_LIST_ENTRY(entry, mali_kernel_memory_mmu, session_link);
+				if (mmu->id < temp->id)
+					break;
+			}
+			/* If we broke out, then 'entry' points to the list node of the
+			 * first mmu with a greater ID; otherwise, it points to
+			 * active_mmus. We want to add *before* this node.
+			 */
+			_mali_osk_list_addtail(&mmu->session_link, entry);
+		}
+		err = _MALI_OSK_ERR_OK;
+	}
+
+	/* Allow two cores to run in parallel if they come from the same session */
+	else if (
+	           (mmu->in_page_fault_handler == 0) &&
+	           (requested_memory_session == mmu->active_session ) &&
+	           (0==(MALI_MMU_DISALLOW_PARALLELL_WORK_OF_MALI_CORES & mmu->flags))
+	        )
+	{
+		/* nested activation detected, just update the reference count */
+		MALI_DEBUG_PRINT(4, ("Nested activation detected, %d previous activations found\n", mmu->usage_count));
+		mmu->usage_count++;
+		err = _MALI_OSK_ERR_OK;
+	}
+
+	else if (NULL != callback)
+	{
+		/* can't activate right now, notify caller on idle via callback */
+		mali_kernel_memory_mmu_idle_callback * callback_object, * temp_callback_object;
+		int found = 0;
+
+		MALI_DEBUG_PRINT(3, ("The MMU is busy and is using a different address space, callback given\n"));
+		/* check for existing registration */
+		_MALI_OSK_LIST_FOREACHENTRY(callback_object, temp_callback_object, &mmu->callbacks, mali_kernel_memory_mmu_idle_callback, link)
+		{
+			if (callback_object->callback == callback)
+			{
+				found = 1;
+				break;
+			}
+		}
+
+		if (found)
+		{
+			MALI_DEBUG_PRINT(5, ("Duplicate callback registration found, ignoring\n"));
+			/* callback already registered */
+			err = _MALI_OSK_ERR_BUSY;
+		}
+	 	else
+		{
+			MALI_DEBUG_PRINT(5,("New callback, registering\n"));
+			/* register the new callback */
+			callback_object = _mali_osk_malloc(sizeof(mali_kernel_memory_mmu_idle_callback));
+			if (NULL != callback_object)
+			{
+				MALI_DEBUG_PRINT(7,("Callback struct setup\n"));
+				callback_object->callback = callback;
+				callback_object->callback_argument = callback_argument;
+				_mali_osk_list_addtail(&callback_object->link, &mmu->callbacks);
+				err = _MALI_OSK_ERR_BUSY;
+			}
+		}
+	}
+
+	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_lock_signal(requested_memory_session->lock, _MALI_OSK_LOCKMODE_RW);
+
+    MALI_ERROR(err);
+}
+
+void mali_memory_core_mmu_release_address_space_reference(void* mmu_ptr)
+{
+	mali_kernel_memory_mmu_idle_callback * callback_object, * temp;
+	mali_kernel_memory_mmu * mmu;
+	memory_session * session;
+
+	_MALI_OSK_LIST_HEAD(callbacks);
+
+    MALI_DEBUG_ASSERT_POINTER(mmu_ptr);
+	mmu = (mali_kernel_memory_mmu *)mmu_ptr;
+
+	session = mmu->active_session;
+
+	/* support that we handle spurious page faults */
+	if (NULL != session)
+	{
+		_mali_osk_lock_wait(session->lock, _MALI_OSK_LOCKMODE_RW);
+	}
+
+  	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	MALI_DEBUG_PRINT(4, ("Deactivation of address space on MMU %s, %d references exists\n", mmu->description, mmu->usage_count));
+    MALI_DEBUG_ASSERT(0 != mmu->usage_count);
+	mmu->usage_count--;
+	if (0 != mmu->usage_count)
+	{
+		MALI_DEBUG_PRINT(4, ("MMU still in use by this address space, %d references still exists\n", mmu->usage_count));
+      	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+		/* support that we handle spurious page faults */
+		if (NULL != session)
+		{
+			_mali_osk_lock_signal(session->lock, _MALI_OSK_LOCKMODE_RW);
+		}
+		return;
+	}
+
+	MALI_DEBUG_PRINT(4, ("Activating the empty page directory on %s\n", mmu->description));
+
+	/* last reference gone, deactivate current address space */
+	mali_mmu_activate_address_space(mmu, mali_empty_page_directory);
+
+	/* unlink from session */
+	_mali_osk_list_delinit(&mmu->session_link);
+	/* remove the active session pointer */
+	mmu->active_session = NULL;
+
+	/* Notify all registered callbacks.
+	 * We have to be clever here:
+	 * We must call the callbacks with the spinlock unlocked and
+	 * the callback list emptied to allow them to re-register.
+	 * So we make a copy of the list, clears the list and then later call the callbacks on the local copy
+	 */
+	/* copy list */
+	_MALI_OSK_INIT_LIST_HEAD(&callbacks);
+	_mali_osk_list_splice(&mmu->callbacks, &callbacks);
+	/* clear the original, allowing new registrations during the callback */
+	_MALI_OSK_INIT_LIST_HEAD(&mmu->callbacks);
+
+	/* end of mmu manipulation, so safe to unlock */
+   	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* then finally remove the (possible) session lock, supporting that no session was active (spurious page fault handling) */
+	if (NULL != session)
+	{
+		_mali_osk_lock_signal(session->lock, _MALI_OSK_LOCKMODE_RW);
+	}
+
+	_MALI_OSK_LIST_FOREACHENTRY(callback_object, temp, &callbacks, mali_kernel_memory_mmu_idle_callback, link)
+	{
+        MALI_DEBUG_ASSERT_POINTER(callback_object->callback);
+		(callback_object->callback)(callback_object->callback_argument);
+		_mali_osk_list_del(&callback_object->link);
+		_mali_osk_free(callback_object);
+	}
+}
+
+void mali_memory_core_mmu_unregister_callback(void* mmu_ptr, void(*callback)(void*))
+{
+	mali_kernel_memory_mmu_idle_callback * callback_object, * temp_callback_object;
+	mali_kernel_memory_mmu * mmu;
+    MALI_DEBUG_ASSERT_POINTER(mmu_ptr);
+
+    MALI_DEBUG_ASSERT_POINTER(callback);
+    MALI_DEBUG_ASSERT_POINTER(mmu_ptr);
+
+	mmu = (mali_kernel_memory_mmu *)mmu_ptr;
+
+  	_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	_MALI_OSK_LIST_FOREACHENTRY(callback_object, temp_callback_object, &mmu->callbacks, mali_kernel_memory_mmu_idle_callback, link)
+	{
+        MALI_DEBUG_ASSERT_POINTER(callback_object->callback);
+		if (callback_object->callback == callback)
+		{
+			_mali_osk_list_del(&callback_object->link);
+			_mali_osk_free(callback_object);
+			break;
+		}
+	}
+  	_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+}
+
+static _mali_osk_errcode_t mali_address_manager_allocate(mali_memory_allocation * descriptor)
+{
+	/* allocate page tables, if needed */
+	int i;
+	const int first_pde_idx = MALI_MMU_PDE_ENTRY(descriptor->mali_address);
+	int last_pde_idx;
+	memory_session * session_data;
+#if defined USING_MALI400_L2_CACHE
+	int has_active_mmus = 0;
+	int page_dir_updated = 0;
+#endif
+
+
+	if (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE)
+	{
+		last_pde_idx = MALI_MMU_PDE_ENTRY(descriptor->mali_address + _MALI_OSK_MALI_PAGE_SIZE + descriptor->size - 1);
+	}
+	else
+	{
+		last_pde_idx = MALI_MMU_PDE_ENTRY(descriptor->mali_address + descriptor->size - 1);
+	}
+
+	session_data = (memory_session*)descriptor->mali_addr_mapping_info;
+    MALI_DEBUG_ASSERT_POINTER(session_data);
+
+	MALI_DEBUG_PRINT(4, ("allocating page tables for Mali virtual address space 0x%08X to 0x%08X\n", descriptor->mali_address, descriptor->mali_address + descriptor->size - 1));
+
+#if defined USING_MALI400_L2_CACHE
+	if (0 == _mali_osk_list_empty(&session_data->active_mmus))
+	{
+		/*
+		 * We have active MMUs, so we are probably in the process of alocating more memory for a suspended GP job (PLBU heap)
+		 * From Mali-400 MP r1p0, MMU page directory/tables are also cached by the Mali L2 cache, thus we need to invalidate the page directory
+		 * from the L2 cache if we add new page directory entries (PDEs) to the page directory.
+		 * We only need to do this when we have an active MMU, because we otherwise invalidate the entire Mali L2 cache before at job start
+		 */
+		has_active_mmus = 1;
+	}
+#endif
+
+	for (i = first_pde_idx; i <= last_pde_idx; i++)
+	{
+		if ( 0 == (_mali_osk_mem_ioread32(session_data->page_directory_mapped, i * sizeof(u32)) & MALI_MMU_FLAGS_PRESENT) )
+		{
+			u32 pte_phys;
+			mali_io_address pte_mapped;
+            _mali_osk_errcode_t err;
+
+			/* allocate a new page table */
+            MALI_DEBUG_ASSERT(0 == session_data->page_entries_usage_count[i]);
+            MALI_DEBUG_ASSERT(NULL == session_data->page_entries_mapped[i]);
+
+			err = mali_mmu_get_table_page(&pte_phys, &pte_mapped);
+            if (_MALI_OSK_ERR_OK == err)
+			{
+				session_data->page_entries_mapped[i] = pte_mapped;
+				MALI_DEBUG_ASSERT_POINTER( session_data->page_entries_mapped[i] );
+
+				_mali_osk_mem_iowrite32(session_data->page_directory_mapped, i * sizeof(u32), pte_phys | MALI_MMU_FLAGS_PRESENT); /* mark page table as present */
+
+				/* update usage count */
+				session_data->page_entries_usage_count[i]++;
+#if defined USING_MALI400_L2_CACHE
+				page_dir_updated = 1;
+#endif
+				continue; /* continue loop */
+			}
+
+			MALI_DEBUG_PRINT(1, ("Page table alloc failed\n"));
+			break; /* abort loop, failed to allocate one or more page tables */
+		}
+		else
+		{
+			session_data->page_entries_usage_count[i]++;
+		}
+	}
+
+	if (i <= last_pde_idx)
+	{
+		/* one or more pages could not be allocated, release reference count for the ones we added one for */
+		/* adjust for the one which caused the for loop to be aborted */
+		i--;
+
+		while (i >= first_pde_idx)
+		{
+            MALI_DEBUG_ASSERT(0 != session_data->page_entries_usage_count[i]);
+			session_data->page_entries_usage_count[i]--;
+			if (0 == session_data->page_entries_usage_count[i])
+			{
+				/* last reference removed */
+				mali_mmu_release_table_page(MALI_MMU_ENTRY_ADDRESS(_mali_osk_mem_ioread32(session_data->page_directory_mapped, i * sizeof(u32))));
+				session_data->page_entries_mapped[i] = NULL;
+				_mali_osk_mem_iowrite32(session_data->page_directory_mapped, i * sizeof(u32), 0); /* mark as not present in the page directory */
+			}
+			i--;
+		}
+
+		MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+
+#if defined USING_MALI400_L2_CACHE
+	if (1 == has_active_mmus && 1 == page_dir_updated)
+	{
+		/*
+		 * We have updated the page directory and have an active MMU using it, so invalidate it in the Mali L2 cache.
+		 */
+		mali_kernel_l2_cache_invalidate_page(session_data->page_directory);
+	}
+#endif
+
+	/* all OK */
+	MALI_SUCCESS;
+}
+
+static void mali_address_manager_release(mali_memory_allocation * descriptor)
+{
+	int first_pde_idx;
+	int last_pde_idx;
+	memory_session * session_data;
+	u32 mali_address;
+	u32 mali_address_end;
+	u32 left;
+	int i;
+#if defined USING_MALI400_L2_CACHE
+	int has_active_mmus = 0;
+	int page_dir_updated = 0;
+#endif
+
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+	session_data = (memory_session*)descriptor->mali_addr_mapping_info;
+    MALI_DEBUG_ASSERT_POINTER(session_data);
+    MALI_DEBUG_ASSERT_POINTER(session_data->page_directory_mapped);
+
+	mali_address = descriptor->mali_address;
+	mali_address_end = descriptor->mali_address + descriptor->size;
+	left = descriptor->size;
+
+	first_pde_idx = MALI_MMU_PDE_ENTRY(mali_address);
+	last_pde_idx = MALI_MMU_PDE_ENTRY(mali_address_end - 1);
+
+	MALI_DEBUG_PRINT(3, ("Zapping Mali MMU table for address 0x%08X size 0x%08X\n", mali_address, left));
+	MALI_DEBUG_PRINT(4, ("Zapping PDE %d through %d\n", first_pde_idx, last_pde_idx));
+
+#if defined USING_MALI400_L2_CACHE
+	if (0 == _mali_osk_list_empty(&session_data->active_mmus))
+	{
+		/*
+		 * From Mali-400 MP r1p0, MMU page directory/tables are also cached by the Mali L2 cache, thus we need to invalidate the page tables
+		 * from the L2 cache to ensure that the memory is unmapped.
+		 * We only need to do this when we have an active MMU, because we otherwise invalidate the entire Mali L2 cache before at job start
+		 */
+		has_active_mmus = 1;
+	}
+#endif
+
+
+	for (i = first_pde_idx; i <= last_pde_idx; i++)
+	{
+		int size_inside_pte = left < 0x400000 ? left : 0x400000;
+		const int first_pte_idx = MALI_MMU_PTE_ENTRY(mali_address);
+		int last_pte_idx = MALI_MMU_PTE_ENTRY(mali_address + size_inside_pte - 1);
+
+		if (last_pte_idx < first_pte_idx)
+		{
+			/* The last_pte_idx is into the next PTE, crop it to fit into this */
+			last_pte_idx = 1023; /* 1024 PTE entries, so 1023 is the last one */
+			size_inside_pte = MALI_MMU_ADDRESS(i + 1, 0) - mali_address;
+		}
+
+		MALI_DEBUG_ASSERT_POINTER(session_data->page_entries_mapped[i]);
+		MALI_DEBUG_ASSERT(0 != session_data->page_entries_usage_count[i]);
+		MALI_DEBUG_PRINT(4, ("PDE %d: zapping entries %d through %d, address 0x%08X, size 0x%08X, left 0x%08X (page table at 0x%08X)\n",
+		                     i, first_pte_idx, last_pte_idx, mali_address, size_inside_pte, left,
+		                     MALI_MMU_ENTRY_ADDRESS(_mali_osk_mem_ioread32(session_data->page_directory_mapped, i * sizeof(u32)))));
+
+		session_data->page_entries_usage_count[i]--;
+
+		if (0 == session_data->page_entries_usage_count[i])
+		{
+			MALI_DEBUG_PRINT(4, ("Releasing page table as this is the last reference\n"));
+			/* last reference removed, no need to zero out each PTE  */
+			mali_mmu_release_table_page(MALI_MMU_ENTRY_ADDRESS(_mali_osk_mem_ioread32(session_data->page_directory_mapped, i * sizeof(u32))));
+			session_data->page_entries_mapped[i] = NULL;
+			_mali_osk_mem_iowrite32(session_data->page_directory_mapped, i * sizeof(u32), 0); /* mark as not present in the page directory */
+#if defined USING_MALI400_L2_CACHE
+			page_dir_updated = 1;
+#endif
+		}
+		else
+		{
+			int j;
+
+			for (j = first_pte_idx; j <= last_pte_idx; j++)
+			{
+				_mali_osk_mem_iowrite32(session_data->page_entries_mapped[i], j * sizeof(u32), 0);
+			}
+
+#if defined USING_MALI400_L2_CACHE
+			if (1 == has_active_mmus)
+			{
+				/* Invalidate the page we've just modified */
+				mali_kernel_l2_cache_invalidate_page( _mali_osk_mem_ioread32(session_data->page_directory_mapped, i*sizeof(u32)) & ~MALI_MMU_FLAGS_MASK);
+			}
+#endif
+		}
+		left -= size_inside_pte;
+		mali_address += size_inside_pte;
+	}
+
+#if defined USING_MALI400_L2_CACHE
+	if ((1 == page_dir_updated) && (1== has_active_mmus))
+	{
+		/* The page directory was also updated */
+		mali_kernel_l2_cache_invalidate_page(session_data->page_directory);
+	}
+#endif
+}
+
+static _mali_osk_errcode_t mali_address_manager_map(mali_memory_allocation * descriptor, u32 offset, u32 *phys_addr, u32 size)
+{
+	memory_session * session_data;
+	u32 mali_address;
+	u32 mali_address_end;
+	u32 current_phys_addr;
+#if defined USING_MALI400_L2_CACHE
+	int has_active_mmus = 0;
+#endif
+
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+	MALI_DEBUG_ASSERT_POINTER( phys_addr );
+
+	current_phys_addr = *phys_addr;
+
+	session_data = (memory_session*)descriptor->mali_addr_mapping_info;
+    MALI_DEBUG_ASSERT_POINTER(session_data);
+
+	mali_address = descriptor->mali_address + offset;
+	mali_address_end = descriptor->mali_address + offset + size;
+
+#if defined USING_MALI400_L2_CACHE
+	if (0 == _mali_osk_list_empty(&session_data->active_mmus))
+	{
+		/*
+		 * We have active MMUs, so we are probably in the process of alocating more memory for a suspended GP job (PLBU heap)
+		 * From Mali-400 MP r1p0, MMU page directory/tables are also cached by the Mali L2 cache, thus we need to invalidate the page tables
+		 * from the L2 cache when we have allocated more heap memory.
+		 * We only need to do this when we have an active MMU, because we otherwise invalidate the entire Mali L2 cache before at job start
+		 */
+		has_active_mmus = 1;
+	}
+#endif
+
+	MALI_DEBUG_PRINT(6, ("Mali map: mapping 0x%08X to Mali address 0x%08X length 0x%08X\n", current_phys_addr, mali_address, size));
+
+    MALI_DEBUG_ASSERT_POINTER(session_data->page_entries_mapped);
+
+	for ( ; mali_address < mali_address_end; mali_address += MALI_MMU_PAGE_SIZE, current_phys_addr += MALI_MMU_PAGE_SIZE)
+	{
+        MALI_DEBUG_ASSERT_POINTER(session_data->page_entries_mapped[MALI_MMU_PDE_ENTRY(mali_address)]);
+		_mali_osk_mem_iowrite32_relaxed(session_data->page_entries_mapped[MALI_MMU_PDE_ENTRY(mali_address)], MALI_MMU_PTE_ENTRY(mali_address) * sizeof(u32), current_phys_addr | MALI_MMU_FLAGS_WRITE_PERMISSION | MALI_MMU_FLAGS_READ_PERMISSION | MALI_MMU_FLAGS_PRESENT);
+	}
+	_mali_osk_write_mem_barrier();
+
+#if defined USING_MALI400_L2_CACHE
+	if (1 == has_active_mmus)
+	{
+		int i;
+		const int first_pde_idx = MALI_MMU_PDE_ENTRY(mali_address);
+		const int last_pde_idx = MALI_MMU_PDE_ENTRY(mali_address_end - 1);
+
+		/*
+		 * Invalidate the updated page table(s), incase they have been used for something
+		 * else since last job start (invalidation of entire Mali L2 cache)
+		 */
+		for (i = first_pde_idx; i <= last_pde_idx; i++)
+		{
+			mali_kernel_l2_cache_invalidate_page( _mali_osk_mem_ioread32(session_data->page_directory_mapped, i*sizeof(u32)) & ~MALI_MMU_FLAGS_MASK);
+		}
+	}
+#endif
+
+	MALI_SUCCESS;
+}
+
+/* This handler registered to mali_mmap for MMU builds */
+_mali_osk_errcode_t _mali_ukk_mem_mmap( _mali_uk_mem_mmap_s *args )
+{
+	struct mali_session_data * mali_session_data;
+	mali_memory_allocation * descriptor;
+	memory_session * session_data;
+
+	/* validate input */
+	if (NULL == args) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: args was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS); }
+
+	/* Unpack arguments */
+	mali_session_data = (struct mali_session_data *)args->ctx;
+
+	if (NULL == mali_session_data) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: mali_session data was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS); }
+
+	MALI_DEBUG_ASSERT( mali_subsystem_memory_id >= 0 );
+
+	session_data = mali_kernel_session_manager_slot_get(mali_session_data, mali_subsystem_memory_id);
+	/* validate input */
+	if (NULL == session_data) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: session data was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_FAULT); }
+
+	descriptor = (mali_memory_allocation*) _mali_osk_calloc( 1, sizeof(mali_memory_allocation) );
+	if (NULL == descriptor) { MALI_DEBUG_PRINT(3,("mali_ukk_mem_mmap: descriptor was NULL\n")); MALI_ERROR(_MALI_OSK_ERR_NOMEM); }
+
+	descriptor->size = args->size;
+	descriptor->mali_address = args->phys_addr;
+	descriptor->mali_addr_mapping_info = (void*)session_data;
+
+	descriptor->process_addr_mapping_info = args->ukk_private; /* save to be used during physical manager callback */
+	descriptor->flags = MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE;
+    descriptor->lock = session_data->lock;
+	_mali_osk_list_init( &descriptor->list );
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (0 == mali_allocation_engine_allocate_memory(memory_engine, descriptor, physical_memory_allocators, &session_data->memory_head))
+	{
+		mali_kernel_memory_mmu * mmu, * temp_mmu;
+
+		_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &session_data->active_mmus, mali_kernel_memory_mmu, session_link)
+		{
+			/* no need to lock the MMU as we own it already */
+			MALI_DEBUG_PRINT(5, ("Zapping the cache of mmu %s as it's using the page table we have updated\n", mmu->description));
+
+			_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+			mali_mmu_enable_stall(mmu); /* this might fail, but ZAP should work anyway... */
+			mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ZAP_CACHE);
+			mali_mmu_disable_stall(mmu);
+
+			_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+		}
+
+       	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+        /* All ok, write out any information generated from this call */
+        args->mapping = descriptor->mapping;
+        args->cookie = (u32)descriptor;
+
+        MALI_DEBUG_PRINT(7, ("MMAP OK\n"));
+		/* All done */
+		MALI_SUCCESS;
+	}
+	else
+	{
+       	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+		/* OOM, but not a fatal error */
+		MALI_DEBUG_PRINT(4, ("Memory allocation failure, OOM\n"));
+		_mali_osk_free(descriptor);
+		/* Linux will free the CPU address allocation, userspace client the Mali address allocation */
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+}
+
+static _mali_osk_errcode_t _mali_ukk_mem_munmap_internal( _mali_uk_mem_munmap_s *args )
+{
+	memory_session * session_data;
+	mali_kernel_memory_mmu * mmu, * temp_mmu;
+	mali_memory_allocation * descriptor;
+
+	descriptor = (mali_memory_allocation *)args->cookie;
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+    /** @note args->context unused; we use the memory_session from the cookie */
+    /* args->mapping and args->size are also discarded. They are only necessary
+    for certain do_munmap implementations. However, they could be used to check the
+    descriptor at this point. */
+
+    session_data = (memory_session*)descriptor->mali_addr_mapping_info;
+    MALI_DEBUG_ASSERT_POINTER(session_data);
+
+	/* Stall the MMU(s) which is using the address space we're operating on.
+	 * Note that active_mmus must be sorted in order of ID to avoid a mutex
+	 * ordering violation.
+	 */
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &session_data->active_mmus, mali_kernel_memory_mmu, session_link)
+	{
+		u32 status;
+		status = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_STATUS);
+		if ( MALI_MMU_STATUS_BIT_PAGE_FAULT_ACTIVE == (status & MALI_MMU_STATUS_BIT_PAGE_FAULT_ACTIVE) ) {
+			MALI_DEBUG_PRINT(2, ("Stopped stall attempt for mmu with id %d since it is in page fault mode.\n", mmu->id));
+			continue;
+		}
+		_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+
+		/*
+		 * If we're unable to stall, then make sure we tell our caller that,
+		 * the caller should then release the session lock for a while,
+		 * then this function again.
+		 * This function will fail if we're in page fault mode, and to get
+		 * out of page fault mode, the page fault handler must be able to
+		 * take the session lock.
+		 */
+		if (!mali_mmu_enable_stall(mmu))
+		{
+			_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+			return _MALI_OSK_ERR_BUSY;
+		}
+
+		_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	}
+
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &session_data->active_mmus, mali_kernel_memory_mmu, session_link)
+	{
+		_mali_osk_lock_wait(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	}
+
+	/* This function also removes the memory from the session's memory list */
+	mali_allocation_engine_release_memory(memory_engine, descriptor);
+	_mali_osk_free(descriptor);
+
+	/* any L2 maintenance was done during mali_allocation_engine_release_memory */
+	/* the session is locked, so the active mmu list should be the same */
+	/* zap the TLB and resume operation */
+	_MALI_OSK_LIST_FOREACHENTRY(mmu, temp_mmu, &session_data->active_mmus, mali_kernel_memory_mmu, session_link)
+	{
+		mali_mmu_register_write(mmu, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ZAP_CACHE);
+		mali_mmu_disable_stall(mmu);
+
+		_mali_osk_lock_signal(mmu->lock, _MALI_OSK_LOCKMODE_RW);
+	}
+
+	return _MALI_OSK_ERR_OK;
+}
+
+/* Handler for unmapping memory for MMU builds */
+_mali_osk_errcode_t _mali_ukk_mem_munmap( _mali_uk_mem_munmap_s *args )
+{
+	mali_memory_allocation * descriptor;
+	_mali_osk_lock_t *descriptor_lock;
+	_mali_osk_errcode_t err;
+
+	descriptor = (mali_memory_allocation *)args->cookie;
+    MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+    /** @note args->context unused; we use the memory_session from the cookie */
+    /* args->mapping and args->size are also discarded. They are only necessary
+    for certain do_munmap implementations. However, they could be used to check the
+    descriptor at this point. */
+
+    MALI_DEBUG_ASSERT_POINTER((memory_session*)descriptor->mali_addr_mapping_info);
+    
+	descriptor_lock = descriptor->lock; /* should point to the session data lock... */
+
+	err = _MALI_OSK_ERR_BUSY;
+	while (err == _MALI_OSK_ERR_BUSY)
+	{
+		if (descriptor_lock)
+		{
+			_mali_osk_lock_wait( descriptor_lock, _MALI_OSK_LOCKMODE_RW );
+		}
+
+		err = _mali_ukk_mem_munmap_internal( args );
+
+		if (descriptor_lock)
+		{
+			_mali_osk_lock_signal( descriptor_lock, _MALI_OSK_LOCKMODE_RW );
+		}
+
+		if (err == _MALI_OSK_ERR_BUSY)
+		{
+			/*
+			 * Reason for this;
+			 * We where unable to stall the MMU, probably because we are in page fault handling.
+			 * Sleep for a while with the session lock released, then try again.
+			 * Abnormal termination of programs with running Mali jobs is a normal reason for this.
+			 */
+			_mali_osk_time_ubusydelay(10);
+		}
+	}
+
+	return err;
+}
+
+/* Is called when the rendercore wants the mmu to give an interrupt */
+static void mali_mmu_probe_irq_trigger(mali_kernel_memory_mmu * mmu)
+{
+    MALI_DEBUG_PRINT(2, ("mali_mmu_probe_irq_trigger\n"));
+    mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_RAWSTAT, MALI_MMU_INTERRUPT_PAGE_FAULT|MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+}
+
+/* Is called when the irq probe wants the mmu to acknowledge an interrupt from the hw */
+static _mali_osk_errcode_t mali_mmu_probe_irq_acknowledge(mali_kernel_memory_mmu * mmu)
+{
+	u32 int_stat;
+
+    int_stat = mali_mmu_register_read(mmu, MALI_MMU_REGISTER_INT_STATUS);
+
+    MALI_DEBUG_PRINT(2, ("mali_mmu_probe_irq_acknowledge: intstat 0x%x\n", int_stat));
+    if (int_stat & MALI_MMU_INTERRUPT_PAGE_FAULT)
+    {
+	    MALI_DEBUG_PRINT(2, ("Probe: Page fault detect: PASSED\n"));
+	    mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_CLEAR, MALI_MMU_INTERRUPT_PAGE_FAULT);
+    }
+    else MALI_DEBUG_PRINT(1, ("Probe: Page fault detect: FAILED\n"));
+
+    if (int_stat & MALI_MMU_INTERRUPT_READ_BUS_ERROR)
+    {
+	    MALI_DEBUG_PRINT(2, ("Probe: Bus read error detect: PASSED\n"));
+	    mali_mmu_register_write(mmu, MALI_MMU_REGISTER_INT_CLEAR, MALI_MMU_INTERRUPT_READ_BUS_ERROR);
+    }
+    else MALI_DEBUG_PRINT(1, ("Probe: Bus read error detect: FAILED\n"));
+
+    if ( (int_stat & (MALI_MMU_INTERRUPT_PAGE_FAULT|MALI_MMU_INTERRUPT_READ_BUS_ERROR)) ==
+                     (MALI_MMU_INTERRUPT_PAGE_FAULT|MALI_MMU_INTERRUPT_READ_BUS_ERROR))
+    {
+        MALI_SUCCESS;
+    }
+
+    MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+struct dump_info
+{
+	u32 buffer_left;
+	u32 register_writes_size;
+	u32 page_table_dump_size;
+	u32 *buffer;
+};
+
+static _mali_osk_errcode_t writereg(u32 where, u32 what, const char * comment, struct dump_info * info, int dump_to_serial)
+{
+	if (dump_to_serial) MALI_DEBUG_PRINT(1, ("writereg %08X %08X # %s\n", where, what, comment));
+
+	if (NULL != info)
+	{
+		info->register_writes_size += sizeof(u32)*2; /* two 32-bit words */
+
+		if (NULL != info->buffer)
+		{
+			/* check that we have enough space */
+			if (info->buffer_left < sizeof(u32)*2) MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+
+			*info->buffer = where;
+			info->buffer++;
+
+			*info->buffer = what;
+			info->buffer++;
+
+			info->buffer_left -= sizeof(u32)*2;
+		}
+	}
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t dump_page(mali_io_address page, u32 phys_addr, struct dump_info * info, int dump_to_serial)
+{
+	if (dump_to_serial)
+	{
+		int i;
+		for (i = 0; i < 256; i++)
+		{
+			MALI_DEBUG_PRINT(1, ("%08X: %08X %08X %08X %08X\n", phys_addr + 16*i, _mali_osk_mem_ioread32(page, (i*4 + 0) * sizeof(u32)),
+			                                                                      _mali_osk_mem_ioread32(page, (i*4 + 1) * sizeof(u32)),
+			                                                                      _mali_osk_mem_ioread32(page, (i*4 + 2) * sizeof(u32)),
+			                                                                      _mali_osk_mem_ioread32(page, (i*4 + 3) * sizeof(u32))));
+
+		}
+	}
+
+	if (NULL != info)
+	{
+		/* 4096 for the page and 4 bytes for the address */
+		const u32 page_size_in_elements = MALI_MMU_PAGE_SIZE / 4;
+		const u32 page_size_in_bytes = MALI_MMU_PAGE_SIZE;
+		const u32 dump_size_in_bytes = MALI_MMU_PAGE_SIZE + 4;
+
+		info->page_table_dump_size += dump_size_in_bytes;
+
+		if (NULL != info->buffer)
+		{
+			if (info->buffer_left < dump_size_in_bytes) MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+
+			*info->buffer = phys_addr;
+			info->buffer++;
+
+			_mali_osk_memcpy(info->buffer, page, page_size_in_bytes);
+			info->buffer += page_size_in_elements;
+
+			info->buffer_left -= dump_size_in_bytes;
+		}
+	}
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t dump_mmu_page_table(memory_session * session_data, struct dump_info * info)
+{
+	MALI_DEBUG_ASSERT_POINTER(session_data);
+	MALI_DEBUG_ASSERT_POINTER(info);
+
+	if (NULL != session_data->page_directory_mapped)
+	{
+		int i;
+
+		MALI_CHECK_NO_ERROR(
+            dump_page(session_data->page_directory_mapped, session_data->page_directory, info, 0)
+            );
+
+		for (i = 0; i < 1024; i++)
+		{
+			if (NULL != session_data->page_entries_mapped[i])
+			{
+				MALI_CHECK_NO_ERROR(
+                    dump_page(session_data->page_entries_mapped[i], _mali_osk_mem_ioread32(session_data->page_directory_mapped, i * sizeof(u32)) & ~MALI_MMU_FLAGS_MASK, info, 0)
+                    );
+			}
+		}
+	}
+
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t dump_mmu_registers(memory_session * session_data, struct dump_info * info)
+{
+	MALI_CHECK_NO_ERROR(writereg(0x00000000, session_data->page_directory, "set the page directory address", info, 0));
+	MALI_CHECK_NO_ERROR(writereg(0x00000008, 4, "zap???", info, 0));
+	MALI_CHECK_NO_ERROR(writereg(0x00000008, 0, "enable paging", info, 0));
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_query_mmu_page_table_dump_size( _mali_uk_query_mmu_page_table_dump_size_s *args )
+{
+	struct dump_info info = { 0, 0, 0, NULL };
+	memory_session * session_data;
+
+    MALI_DEBUG_ASSERT_POINTER(args);
+  	MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+
+    MALI_CHECK_NO_ERROR(dump_mmu_registers(session_data, &info));
+	MALI_CHECK_NO_ERROR(dump_mmu_page_table(session_data, &info));
+	args->size = info.register_writes_size + info.page_table_dump_size;
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t _mali_ukk_dump_mmu_page_table( _mali_uk_dump_mmu_page_table_s * args )
+{
+	struct dump_info info = { 0, 0, 0, NULL };
+	memory_session * session_data;
+
+  	MALI_DEBUG_ASSERT_POINTER(args);
+  	MALI_CHECK_NON_NULL(args->ctx, _MALI_OSK_ERR_INVALID_ARGS);
+    MALI_CHECK_NON_NULL(args->buffer, _MALI_OSK_ERR_INVALID_ARGS);
+
+    session_data = (memory_session *)mali_kernel_session_manager_slot_get(args->ctx, mali_subsystem_memory_id);
+
+	info.buffer_left = args->size;
+	info.buffer = args->buffer;
+
+	args->register_writes = info.buffer;
+	MALI_CHECK_NO_ERROR(dump_mmu_registers(session_data, &info));
+
+	args->page_table_dump = info.buffer;
+	MALI_CHECK_NO_ERROR(dump_mmu_page_table(session_data, &info));
+
+	args->register_writes_size = info.register_writes_size;
+	args->page_table_dump_size = info.page_table_dump_size;
+
+    MALI_SUCCESS;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_get_big_block( _mali_uk_get_big_block_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+/**
+ * Stub function to satisfy UDD interface exclusion requirement.
+ * This is because the Base code compiles in \b both MMU and non-MMU calls,
+ * so both sets must be declared (but the 'unused' set may be stub)
+ */
+_mali_osk_errcode_t _mali_ukk_free_big_block( _mali_uk_free_big_block_s *args )
+{
+	MALI_IGNORE( args );
+	return _MALI_OSK_ERR_FAULT;
+}
+
+u32 _mali_ukk_report_memory_usage(void)
+{
+	return mali_allocation_engine_memory_usage(physical_memory_allocators);
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.h b/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.h
new file mode 100644
index 0000000..6a110d0
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem_mmu.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_MEM_MMU_H__
+#define __MALI_KERNEL_MEM_MMU_H__
+
+#include "mali_kernel_session_manager.h"
+
+/**
+ * Lookup a MMU core by ID.
+ * @param id ID of the MMU to find
+ * @return NULL if ID not found or valid, non-NULL if a core was found.
+ */
+void* mali_memory_core_mmu_lookup(u32 id);
+
+/**
+ * Set the core pointer of MMU to core owner of MMU
+ *
+ * @param core Core holding this MMU
+ * @param mmu_ptr The MMU whose core pointer needs set to core holding the MMU
+ *
+ */
+void mali_memory_core_mmu_owner(void *core, void *mmu_ptr);
+
+/**
+ * Activate a user session with its address space on the given MMU.
+ * If the session can't be activated due to that the MMU is busy and
+ * a callback pointer is given, the callback will be called once the MMU becomes idle.
+ * If the same callback pointer is registered multiple time it will only be called once.
+ * Nested activations are supported.
+ * Each call must be matched by a call to @see mali_memory_core_mmu_release_address_space_reference
+ *
+ * @param mmu The MMU to activate the address space on
+ * @param mali_session_data The user session object which address space to activate
+ * @param callback Pointer to the function to call when the MMU becomes idle
+ * @param callback_arg Argument given to the callback
+ * @return 0 if the address space was activated, -EBUSY if the MMU was busy, -EFAULT in all other cases.
+ */
+int mali_memory_core_mmu_activate_page_table(void* mmu_ptr, struct mali_session_data * mali_session_data, void(*callback)(void*), void * callback_argument);
+
+/**
+ * Release a reference to the current active address space.
+ * Once the last reference is released any callback(s) registered will be called before the function returns
+ *
+ * @note Caution must be shown calling this function with locks held due to that callback can be called
+ * @param mmu The mmu to release a reference to the active address space of
+ */
+void mali_memory_core_mmu_release_address_space_reference(void* mmu);
+
+/**
+ * Soft reset of MMU - needed after power up
+ *
+ * @param mmu_ptr The MMU pointer registered with the relevant core
+ */
+void mali_kernel_mmu_reset(void * mmu_ptr);
+
+void mali_kernel_mmu_force_bus_reset(void * mmu_ptr);
+
+/**
+ * Unregister a previously registered callback.
+ * @param mmu The MMU to unregister the callback on
+ * @param callback The function to unregister
+ */
+void mali_memory_core_mmu_unregister_callback(void* mmu, void(*callback)(void*));
+
+
+
+#endif /* __MALI_KERNEL_MEM_MMU_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.c b/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.c
new file mode 100644
index 0000000..324fcab
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_memory_engine.h"
+#include "mali_osk.h"
+
+typedef struct os_allocation
+{
+	u32 num_pages;
+	u32 offset_start;
+	mali_allocation_engine * engine;
+	mali_memory_allocation * descriptor;
+} os_allocation;
+
+typedef struct os_allocator
+{
+	_mali_osk_lock_t *mutex;
+
+	/**
+	 * Maximum number of pages to allocate from the OS
+	 */
+	u32 num_pages_max;
+
+	/**
+	 * Number of pages allocated from the OS
+	 */
+	u32 num_pages_allocated;
+
+	/** CPU Usage adjustment (add to mali physical address to get cpu physical address) */
+	u32 cpu_usage_adjust;
+} os_allocator;
+
+static mali_physical_memory_allocation_result os_allocator_allocate(void* ctx, mali_allocation_engine * engine,  mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info);
+static mali_physical_memory_allocation_result os_allocator_allocate_page_table_block(void * ctx, mali_page_table_block * block);
+static void os_allocator_release(void * ctx, void * handle);
+static void os_allocator_page_table_block_release( mali_page_table_block *page_table_block );
+static void os_allocator_destroy(mali_physical_memory_allocator * allocator);
+static u32 os_allocator_stat(mali_physical_memory_allocator * allocator);
+
+mali_physical_memory_allocator * mali_os_allocator_create(u32 max_allocation, u32 cpu_usage_adjust, const char *name)
+{
+	mali_physical_memory_allocator * allocator;
+	os_allocator * info;
+
+	max_allocation = (max_allocation + _MALI_OSK_CPU_PAGE_SIZE-1) & ~(_MALI_OSK_CPU_PAGE_SIZE-1);
+
+	MALI_DEBUG_PRINT(2, ("Mali OS memory allocator created with max allocation size of 0x%X bytes, cpu_usage_adjust 0x%08X\n", max_allocation, cpu_usage_adjust));
+
+	allocator = _mali_osk_malloc(sizeof(mali_physical_memory_allocator));
+	if (NULL != allocator)
+	{
+		info = _mali_osk_malloc(sizeof(os_allocator));
+		if (NULL != info)
+		{
+			info->num_pages_max = max_allocation / _MALI_OSK_CPU_PAGE_SIZE;
+			info->num_pages_allocated = 0;
+			info->cpu_usage_adjust = cpu_usage_adjust;
+
+			info->mutex = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ORDERED, 0, 106);
+			if (NULL != info->mutex)
+			{
+				allocator->allocate = os_allocator_allocate;
+				allocator->allocate_page_table_block = os_allocator_allocate_page_table_block;
+				allocator->destroy = os_allocator_destroy;
+				allocator->stat = os_allocator_stat;
+				allocator->ctx = info;
+				allocator->name = name;
+
+				return allocator;
+			}
+			_mali_osk_free(info);
+		}
+		_mali_osk_free(allocator);
+	}
+
+	return NULL;
+}
+
+static u32 os_allocator_stat(mali_physical_memory_allocator * allocator)
+{
+	os_allocator * info;
+	info = (os_allocator*)allocator->ctx;
+	return info->num_pages_allocated * _MALI_OSK_MALI_PAGE_SIZE;
+}
+
+static void os_allocator_destroy(mali_physical_memory_allocator * allocator)
+{
+	os_allocator * info;
+	MALI_DEBUG_ASSERT_POINTER(allocator);
+	MALI_DEBUG_ASSERT_POINTER(allocator->ctx);
+	info = (os_allocator*)allocator->ctx;
+	_mali_osk_lock_term(info->mutex);
+	_mali_osk_free(info);
+	_mali_osk_free(allocator);
+}
+
+static mali_physical_memory_allocation_result os_allocator_allocate(void* ctx, mali_allocation_engine * engine,  mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info)
+{
+	mali_physical_memory_allocation_result result = MALI_MEM_ALLOC_NONE;
+	u32 left;
+	os_allocator * info;
+	os_allocation * allocation;
+	int pages_allocated = 0;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+	MALI_DEBUG_ASSERT_POINTER(offset);
+	MALI_DEBUG_ASSERT_POINTER(alloc_info);
+
+	info = (os_allocator*)ctx;
+	left = descriptor->size - *offset;
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW)) return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	/** @note this code may not work on Linux, or may require a more complex Linux implementation */
+	allocation = _mali_osk_malloc(sizeof(os_allocation));
+	if (NULL != allocation)
+	{
+		u32 os_mem_max_usage = info->num_pages_max * _MALI_OSK_CPU_PAGE_SIZE;
+		allocation->offset_start = *offset;
+		allocation->num_pages = ((left + _MALI_OSK_CPU_PAGE_SIZE - 1) & ~(_MALI_OSK_CPU_PAGE_SIZE - 1)) >> _MALI_OSK_CPU_PAGE_ORDER;
+		MALI_DEBUG_PRINT(6, ("Allocating page array of size %d bytes\n", allocation->num_pages * sizeof(struct page*)));
+
+		while (left > 0 && ((info->num_pages_allocated + pages_allocated) < info->num_pages_max) && _mali_osk_mem_check_allocated(os_mem_max_usage))
+		{
+			err = mali_allocation_engine_map_physical(engine, descriptor, *offset, MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC, info->cpu_usage_adjust, _MALI_OSK_CPU_PAGE_SIZE);
+			if ( _MALI_OSK_ERR_OK != err)
+			{
+				if (  _MALI_OSK_ERR_NOMEM == err)
+				{
+					/* 'Partial' allocation (or, out-of-memory on first page) */
+					break;
+				}
+
+				MALI_DEBUG_PRINT(1, ("Mapping of physical memory failed\n"));
+
+				/* Fatal error, cleanup any previous pages allocated. */
+				if ( pages_allocated > 0 )
+				{
+					mali_allocation_engine_unmap_physical( engine, descriptor, allocation->offset_start, _MALI_OSK_CPU_PAGE_SIZE*pages_allocated, _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR );
+					/* (*offset) doesn't need to be restored; it will not be used by the caller on failure */
+				}
+
+				pages_allocated = 0;
+
+				result = MALI_MEM_ALLOC_INTERNAL_FAILURE;
+				break;
+			}
+
+			/* Loop iteration */
+			if (left < _MALI_OSK_CPU_PAGE_SIZE) left = 0;
+			else left -= _MALI_OSK_CPU_PAGE_SIZE;
+
+			pages_allocated++;
+
+			*offset += _MALI_OSK_CPU_PAGE_SIZE;
+		}
+
+		if (left) MALI_PRINT(("Out of memory. Mali memory allocated: %d kB  Configured maximum OS memory usage: %d kB\n",
+				 (info->num_pages_allocated * _MALI_OSK_CPU_PAGE_SIZE)/1024, (info->num_pages_max* _MALI_OSK_CPU_PAGE_SIZE)/1024));
+
+		/* Loop termination; decide on result */
+		if (pages_allocated)
+		{
+			MALI_DEBUG_PRINT(6, ("Allocated %d pages\n", pages_allocated));
+			if (left) result = MALI_MEM_ALLOC_PARTIAL;
+			else result = MALI_MEM_ALLOC_FINISHED;
+
+            /* Some OS do not perform a full cache flush (including all outer caches) for uncached mapped memory.
+             * They zero the memory through a cached mapping, then flush the inner caches but not the outer caches.
+             * This is required for MALI to have the correct view of the memory.
+             */
+            _mali_osk_cache_ensure_uncached_range_flushed( (void *)descriptor, allocation->offset_start, pages_allocated *_MALI_OSK_CPU_PAGE_SIZE );
+			allocation->num_pages = pages_allocated;
+			allocation->engine = engine;         /* Necessary to make the engine's unmap call */
+			allocation->descriptor = descriptor; /* Necessary to make the engine's unmap call */
+			info->num_pages_allocated += pages_allocated;
+
+			MALI_DEBUG_PRINT(6, ("%d out of %d pages now allocated\n", info->num_pages_allocated, info->num_pages_max));
+
+			alloc_info->ctx = info;
+			alloc_info->handle = allocation;
+			alloc_info->release = os_allocator_release;
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(6, ("Releasing pages array due to no pages allocated\n"));
+			_mali_osk_free( allocation );
+		}
+	}
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	return result;
+}
+
+static void os_allocator_release(void * ctx, void * handle)
+{
+	os_allocator * info;
+	os_allocation * allocation;
+	mali_allocation_engine * engine;
+	mali_memory_allocation * descriptor;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	MALI_DEBUG_ASSERT_POINTER(handle);
+
+	info = (os_allocator*)ctx;
+	allocation = (os_allocation*)handle;
+	engine = allocation->engine;
+	descriptor = allocation->descriptor;
+
+	MALI_DEBUG_ASSERT_POINTER( engine );
+	MALI_DEBUG_ASSERT_POINTER( descriptor );
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW))
+	{
+		MALI_DEBUG_PRINT(1, ("allocator release: Failed to get mutex\n"));
+		return;
+	}
+
+	MALI_DEBUG_PRINT(6, ("Releasing %d os pages\n", allocation->num_pages));
+
+	MALI_DEBUG_ASSERT( allocation->num_pages <= info->num_pages_allocated);
+	info->num_pages_allocated -= allocation->num_pages;
+
+	mali_allocation_engine_unmap_physical( engine, descriptor, allocation->offset_start, _MALI_OSK_CPU_PAGE_SIZE*allocation->num_pages, _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR );
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	_mali_osk_free(allocation);
+}
+
+static mali_physical_memory_allocation_result os_allocator_allocate_page_table_block(void * ctx, mali_page_table_block * block)
+{
+	int allocation_order = 11; /* _MALI_OSK_CPU_PAGE_SIZE << 6 */
+	void *virt = NULL;
+	u32 size = _MALI_OSK_CPU_PAGE_SIZE << allocation_order;
+	os_allocator * info;
+
+	u32 cpu_phys_base;
+
+	MALI_DEBUG_ASSERT_POINTER(ctx);
+	info = (os_allocator*)ctx;
+
+	/* Ensure we don't allocate more than we're supposed to from the ctx */
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW)) return MALI_MEM_ALLOC_INTERNAL_FAILURE;
+
+	/* if the number of pages to be requested lead to exceeding the memory
+	 * limit in info->num_pages_max, reduce the size that is to be requested. */
+	while ( (info->num_pages_allocated + (1 << allocation_order) > info->num_pages_max)
+	        && _mali_osk_mem_check_allocated(info->num_pages_max * _MALI_OSK_CPU_PAGE_SIZE) )
+	{
+		if ( allocation_order > 0 ) {
+			--allocation_order;
+		} else {
+			/* return OOM */
+			_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+			return MALI_MEM_ALLOC_NONE;
+		}
+	}
+
+	/* try to allocate 2^(allocation_order) pages, if that fails, try
+	 * allocation_order-1 to allocation_order 0 (inclusive) */
+	while ( allocation_order >= 0 )
+	{
+		size = _MALI_OSK_CPU_PAGE_SIZE << allocation_order;
+		virt = _mali_osk_mem_allocioregion( &cpu_phys_base, size );
+
+		if (NULL != virt) break;
+
+		--allocation_order;
+	}
+
+	if ( NULL == virt )
+	{
+		MALI_DEBUG_PRINT(1, ("Failed to allocate consistent memory. Is CONSISTENT_DMA_SIZE set too low?\n"));
+		/* return OOM */
+		_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+		return MALI_MEM_ALLOC_NONE;
+	}
+
+	MALI_DEBUG_PRINT(5, ("os_allocator_allocate_page_table_block: Allocation of order %i succeeded\n",
+				allocation_order));
+
+	/* we now know the size of the allocation since we know for what
+	 * allocation_order the allocation succeeded */
+	size = _MALI_OSK_CPU_PAGE_SIZE << allocation_order;
+
+
+	block->release = os_allocator_page_table_block_release;
+	block->ctx = ctx;
+	block->handle = (void*)allocation_order;
+	block->size = size;
+	block->phys_base = cpu_phys_base - info->cpu_usage_adjust;
+	block->mapping = virt;
+
+	info->num_pages_allocated += (1 << allocation_order);
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+
+	return MALI_MEM_ALLOC_FINISHED;
+}
+
+static void os_allocator_page_table_block_release( mali_page_table_block *page_table_block )
+{
+	os_allocator * info;
+	u32 allocation_order;
+	u32 pages_allocated;
+
+	MALI_DEBUG_ASSERT_POINTER( page_table_block );
+
+	info = (os_allocator*)page_table_block->ctx;
+
+	MALI_DEBUG_ASSERT_POINTER( info );
+
+	allocation_order = (u32)page_table_block->handle;
+
+	pages_allocated = 1 << allocation_order;
+
+	MALI_DEBUG_ASSERT( pages_allocated * _MALI_OSK_CPU_PAGE_SIZE == page_table_block->size );
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_lock_wait(info->mutex, _MALI_OSK_LOCKMODE_RW))
+	{
+		MALI_DEBUG_PRINT(1, ("allocator release: Failed to get mutex\n"));
+		return;
+	}
+
+	MALI_DEBUG_ASSERT( pages_allocated <= info->num_pages_allocated);
+	info->num_pages_allocated -= pages_allocated;
+
+	/* Adjust phys_base from mali physical address to CPU physical address */
+	_mali_osk_mem_freeioregion( page_table_block->phys_base + info->cpu_usage_adjust, page_table_block->size, page_table_block->mapping );
+
+	_mali_osk_lock_signal(info->mutex, _MALI_OSK_LOCKMODE_RW);
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.h b/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.h
new file mode 100644
index 0000000..0946169
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_mem_os.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_MEM_OS_H__
+#define __MALI_KERNEL_MEM_OS_H__
+
+/**
+ * @brief Creates an object that manages allocating OS memory
+ *
+ * Creates an object that provides an interface to allocate OS memory and
+ * have it mapped into the Mali virtual memory space.
+ *
+ * The object exposes pointers to
+ * - allocate OS memory
+ * - allocate Mali page tables in OS memory
+ * - destroy the object
+ *
+ * Allocations from OS memory are of type mali_physical_memory_allocation
+ * which provides a function to release the allocation.
+ *
+ * @param max_allocation max. number of bytes that can be allocated from OS memory
+ * @param cpu_usage_adjust value to add to mali physical addresses to obtain CPU physical addresses
+ * @param name description of the allocator
+ * @return pointer to mali_physical_memory_allocator object. NULL on failure.
+ **/
+mali_physical_memory_allocator * mali_os_allocator_create(u32 max_allocation, u32 cpu_usage_adjust, const char *name);
+
+#endif /* __MALI_KERNEL_MEM_OS_H__ */
+
+
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.c b/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.c
new file mode 100644
index 0000000..ff105a4
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_memory_engine.h"
+#include "mali_osk.h"
+#include "mali_osk_list.h"
+
+typedef struct memory_engine
+{
+	mali_kernel_mem_address_manager * mali_address;
+	mali_kernel_mem_address_manager * process_address;
+} memory_engine;
+
+mali_allocation_engine mali_allocation_engine_create(mali_kernel_mem_address_manager * mali_address_manager, mali_kernel_mem_address_manager * process_address_manager)
+{
+	memory_engine * engine;
+
+	/* Mali Address Manager need not support unmap_physical */
+	MALI_DEBUG_ASSERT_POINTER(mali_address_manager);
+	MALI_DEBUG_ASSERT_POINTER(mali_address_manager->allocate);
+	MALI_DEBUG_ASSERT_POINTER(mali_address_manager->release);
+	MALI_DEBUG_ASSERT_POINTER(mali_address_manager->map_physical);
+
+	/* Process Address Manager must support unmap_physical for OS allocation
+	 * error path handling */
+	MALI_DEBUG_ASSERT_POINTER(process_address_manager);
+	MALI_DEBUG_ASSERT_POINTER(process_address_manager->allocate);
+	MALI_DEBUG_ASSERT_POINTER(process_address_manager->release);
+	MALI_DEBUG_ASSERT_POINTER(process_address_manager->map_physical);
+	MALI_DEBUG_ASSERT_POINTER(process_address_manager->unmap_physical);
+
+
+	engine = (memory_engine*)_mali_osk_malloc(sizeof(memory_engine));
+	if (NULL == engine) return NULL;
+
+	engine->mali_address = mali_address_manager;
+	engine->process_address = process_address_manager;
+
+	return (mali_allocation_engine)engine;
+}
+
+void mali_allocation_engine_destroy(mali_allocation_engine engine)
+{
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	_mali_osk_free(engine);
+}
+
+_mali_osk_errcode_t mali_allocation_engine_allocate_memory(mali_allocation_engine mem_engine, mali_memory_allocation * descriptor, mali_physical_memory_allocator * physical_allocators, _mali_osk_list_t *tracking_list )
+{
+	memory_engine * engine = (memory_engine*)mem_engine;
+
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+	MALI_DEBUG_ASSERT_POINTER(physical_allocators);
+	/* ASSERT that the list member has been initialized, even if it won't be
+	 * used for tracking. We need it to be initialized to see if we need to
+	 * delete it from a list in the release function. */
+	MALI_DEBUG_ASSERT( NULL != descriptor->list.next && NULL != descriptor->list.prev );
+
+	if (_MALI_OSK_ERR_OK == engine->mali_address->allocate(descriptor))
+	{
+		_mali_osk_errcode_t res = _MALI_OSK_ERR_OK;
+		if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+		{
+			res = engine->process_address->allocate(descriptor);
+		}
+		if ( _MALI_OSK_ERR_OK == res )
+		{
+			/* address space setup OK, commit physical memory to the allocation */
+			mali_physical_memory_allocator * active_allocator = physical_allocators;
+			struct mali_physical_memory_allocation * active_allocation_tracker = &descriptor->physical_allocation;
+			u32 offset = 0;
+
+			while ( NULL != active_allocator )
+			{
+				switch (active_allocator->allocate(active_allocator->ctx, mem_engine, descriptor, &offset, active_allocation_tracker))
+				{
+					case MALI_MEM_ALLOC_FINISHED:
+						if ( NULL != tracking_list )
+						{
+							/* Insert into the memory session list */
+							/* ASSERT that it is not already part of a list */
+							MALI_DEBUG_ASSERT( _mali_osk_list_empty( &descriptor->list ) );
+							_mali_osk_list_add( &descriptor->list, tracking_list );
+						}
+
+						MALI_SUCCESS; /* all done */
+					case MALI_MEM_ALLOC_NONE:
+						/* reuse current active_allocation_tracker */
+						MALI_DEBUG_PRINT( 4, ("Memory Engine Allocate: No allocation on %s, resorting to %s\n",
+											  ( active_allocator->name ) ? active_allocator->name : "UNNAMED",
+											  ( active_allocator->next ) ? (( active_allocator->next->name )? active_allocator->next->name : "UNNAMED") : "NONE") );
+						active_allocator = active_allocator->next;
+						break;
+					case MALI_MEM_ALLOC_PARTIAL:
+						if (NULL != active_allocator->next)
+						{
+							/* need a new allocation tracker */
+							active_allocation_tracker->next = _mali_osk_calloc(1, sizeof(mali_physical_memory_allocation));
+							if (NULL != active_allocation_tracker->next)
+							{
+								active_allocation_tracker = active_allocation_tracker->next;
+								MALI_DEBUG_PRINT( 2, ("Memory Engine Allocate: Partial allocation on %s, resorting to %s\n",
+													  ( active_allocator->name ) ? active_allocator->name : "UNNAMED",
+													  ( active_allocator->next ) ? (( active_allocator->next->name )? active_allocator->next->name : "UNNAMED") : "NONE") );
+								active_allocator = active_allocator->next;
+								break;
+							}
+						}
+					   /* FALL THROUGH */
+					case MALI_MEM_ALLOC_INTERNAL_FAILURE:
+					   active_allocator = NULL; /* end the while loop */
+					   break;
+				}
+			}
+
+			MALI_PRINT(("Memory allocate failed, could not allocate size %d kB.\n", descriptor->size/1024));
+
+			/* allocation failure, start cleanup */
+			/* loop over any potential partial allocations */
+			active_allocation_tracker = &descriptor->physical_allocation;
+			while (NULL != active_allocation_tracker)
+			{
+				/* handle blank trackers which will show up during failure */
+				if (NULL != active_allocation_tracker->release)
+				{
+					active_allocation_tracker->release(active_allocation_tracker->ctx, active_allocation_tracker->handle);
+				}
+				active_allocation_tracker = active_allocation_tracker->next;
+			}
+
+			/* free the allocation tracker objects themselves, skipping the tracker stored inside the descriptor itself */
+			for ( active_allocation_tracker = descriptor->physical_allocation.next; active_allocation_tracker != NULL; )
+			{
+				void * buf = active_allocation_tracker;
+				active_allocation_tracker = active_allocation_tracker->next;
+				_mali_osk_free(buf);
+			}
+
+			/* release the address spaces */
+
+			if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+			{
+				engine->process_address->release(descriptor);
+			}
+		}
+		engine->mali_address->release(descriptor);
+	}
+
+	MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+void mali_allocation_engine_release_memory(mali_allocation_engine mem_engine, mali_memory_allocation * descriptor)
+{
+	memory_engine * engine = (memory_engine*)mem_engine;
+	mali_physical_memory_allocation * active_allocation_tracker;
+
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+	/* Determine whether we need to remove this from a tracking list */
+	if ( ! _mali_osk_list_empty( &descriptor->list ) )
+	{
+		_mali_osk_list_del( &descriptor->list );
+		/* Clear the list for debug mode, catch use-after-free */
+		MALI_DEBUG_CODE( descriptor->list.next = descriptor->list.prev = NULL; )
+	}
+
+	engine->mali_address->release(descriptor);
+
+	active_allocation_tracker = &descriptor->physical_allocation;
+	while (NULL != active_allocation_tracker)
+	{
+		MALI_DEBUG_ASSERT_POINTER(active_allocation_tracker->release);
+		active_allocation_tracker->release(active_allocation_tracker->ctx, active_allocation_tracker->handle);
+		active_allocation_tracker = active_allocation_tracker->next;
+	}
+
+	/* free the allocation tracker objects themselves, skipping the tracker stored inside the descriptor itself */
+	for ( active_allocation_tracker = descriptor->physical_allocation.next; active_allocation_tracker != NULL; )
+	{
+		void * buf = active_allocation_tracker;
+		active_allocation_tracker = active_allocation_tracker->next;
+		_mali_osk_free(buf);
+	}
+
+	if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+	{
+		engine->process_address->release(descriptor);
+	}
+}
+
+
+_mali_osk_errcode_t mali_allocation_engine_map_physical(mali_allocation_engine mem_engine, mali_memory_allocation * descriptor, u32 offset, u32 phys, u32 cpu_usage_adjust, u32 size)
+{
+	_mali_osk_errcode_t err;
+	memory_engine * engine = (memory_engine*)mem_engine;
+	_mali_osk_mem_mapregion_flags_t unmap_flags = (_mali_osk_mem_mapregion_flags_t)0;
+
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+	MALI_DEBUG_PRINT(7, ("Mapping phys 0x%08X length 0x%08X at offset 0x%08X\n", phys, size, offset));
+
+	MALI_DEBUG_ASSERT_POINTER(engine->mali_address);
+	MALI_DEBUG_ASSERT_POINTER(engine->mali_address->map_physical);
+
+	/* Handle process address manager first, because we may need them to
+	 * allocate the physical page */
+	if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+	{
+		/* Handle OS-allocated specially, since an adjustment may be required */
+		if ( MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC == phys )
+		{
+			MALI_DEBUG_ASSERT( _MALI_OSK_CPU_PAGE_SIZE == size );
+
+			/* Set flags to use on error path */
+			unmap_flags |= _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR;
+
+			err = engine->process_address->map_physical(descriptor, offset, &phys, size);
+			/* Adjust for cpu physical address to mali physical address */
+			phys -= cpu_usage_adjust;
+		}
+		else
+		{
+			u32 cpu_phys;
+			/* Adjust mali physical address to cpu physical address */
+			cpu_phys = phys + cpu_usage_adjust;
+			err = engine->process_address->map_physical(descriptor, offset, &cpu_phys, size);
+		}
+
+		if ( _MALI_OSK_ERR_OK != err )
+		{
+			MALI_ERROR( err );
+		}
+	}
+
+	MALI_DEBUG_PRINT(4, ("Mapping phys 0x%08X length 0x%08X at offset 0x%08X to CPUVA 0x%08X\n", phys, size, offset, (u32)(descriptor->mapping) + offset));
+
+	/* Mali address manager must use the physical address - no point in asking
+	 * it to allocate another one for us */
+	MALI_DEBUG_ASSERT( MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC != phys );
+
+	err = engine->mali_address->map_physical(descriptor, offset, &phys, size);
+
+	if ( _MALI_OSK_ERR_OK != err )
+	{
+		if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+		{
+			MALI_DEBUG_PRINT( 2, ("Process address manager succeeded, but Mali Address manager failed for phys=0x%08X size=0x%08X, offset=0x%08X. Will unmap.\n", phys, size, offset));
+			engine->process_address->unmap_physical(descriptor, offset, size, unmap_flags);
+		}
+
+		MALI_ERROR( err );
+	}
+
+	MALI_SUCCESS;
+}
+
+void mali_allocation_engine_unmap_physical(mali_allocation_engine mem_engine, mali_memory_allocation * descriptor, u32 offset, u32 size, _mali_osk_mem_mapregion_flags_t unmap_flags )
+{
+	memory_engine * engine = (memory_engine*)mem_engine;
+
+	MALI_DEBUG_ASSERT_POINTER(engine);
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+
+	MALI_DEBUG_PRINT(7, ("UnMapping length 0x%08X at offset 0x%08X\n", size, offset));
+
+	MALI_DEBUG_ASSERT_POINTER(engine->mali_address);
+	MALI_DEBUG_ASSERT_POINTER(engine->process_address);
+
+	if ( descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE )
+	{
+		/* Mandetory for process_address manager to have an unmap function*/
+		engine->process_address->unmap_physical( descriptor, offset, size, unmap_flags );
+	}
+
+	/* Optional for mali_address manager to have an unmap function*/
+	if ( NULL != engine->mali_address->unmap_physical )
+	{
+		engine->mali_address->unmap_physical( descriptor, offset, size, unmap_flags );
+	}
+}
+
+
+_mali_osk_errcode_t mali_allocation_engine_allocate_page_tables(mali_allocation_engine engine, mali_page_table_block * descriptor, mali_physical_memory_allocator * physical_provider)
+{
+	mali_physical_memory_allocator * active_allocator = physical_provider;
+
+	MALI_DEBUG_ASSERT_POINTER(descriptor);
+	MALI_DEBUG_ASSERT_POINTER(physical_provider);
+
+	while ( NULL != active_allocator )
+	{
+		switch (active_allocator->allocate_page_table_block(active_allocator->ctx, descriptor))
+		{
+			case MALI_MEM_ALLOC_FINISHED:
+				MALI_SUCCESS; /* all done */
+			case MALI_MEM_ALLOC_NONE:
+				/* try next */
+				MALI_DEBUG_PRINT( 2, ("Memory Engine Allocate PageTables: No allocation on %s, resorting to %s\n",
+									  ( active_allocator->name ) ? active_allocator->name : "UNNAMED",
+									  ( active_allocator->next ) ? (( active_allocator->next->name )? active_allocator->next->name : "UNNAMED") : "NONE") );
+				active_allocator = active_allocator->next;
+				break;
+			case MALI_MEM_ALLOC_PARTIAL:
+				MALI_DEBUG_PRINT(1, ("Invalid return value from allocate_page_table_block call: MALI_MEM_ALLOC_PARTIAL\n"));
+				/* FALL THROUGH */
+			case MALI_MEM_ALLOC_INTERNAL_FAILURE:
+				MALI_DEBUG_PRINT(1, ("Aborting due to allocation failure\n"));
+				active_allocator = NULL; /* end the while loop */
+				break;
+		}
+	}
+
+	MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+
+void mali_allocation_engine_report_allocators( mali_physical_memory_allocator * physical_provider )
+{
+	mali_physical_memory_allocator * active_allocator = physical_provider;
+	MALI_DEBUG_ASSERT_POINTER(physical_provider);
+
+	MALI_DEBUG_PRINT( 1, ("Mali memory allocators will be used in this order of preference (lowest numbered first) :\n"));
+	while ( NULL != active_allocator )
+	{
+		if ( NULL != active_allocator->name )
+		{
+			MALI_DEBUG_PRINT( 1, ("\t%d: %s\n", active_allocator->alloc_order, active_allocator->name) );
+		}
+		else
+		{
+			MALI_DEBUG_PRINT( 1, ("\t%d: (UNNAMED ALLOCATOR)\n", active_allocator->alloc_order) );
+		}
+		active_allocator = active_allocator->next;
+	}
+
+}
+
+u32 mali_allocation_engine_memory_usage(mali_physical_memory_allocator *allocator)
+{
+	u32 sum = 0;
+	while(NULL != allocator)
+	{
+		/* Only count allocators that have set up a stat function. */
+		if(allocator->stat)
+			sum += allocator->stat(allocator);
+
+		allocator = allocator->next;
+	}
+
+	return sum;
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.h b/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.h
new file mode 100644
index 0000000..0173c78
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_memory_engine.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_MEMORY_ENGINE_H__
+#define  __MALI_KERNEL_MEMORY_ENGINE_H__
+
+typedef void * mali_allocation_engine;
+
+typedef enum { MALI_MEM_ALLOC_FINISHED, MALI_MEM_ALLOC_PARTIAL, MALI_MEM_ALLOC_NONE, MALI_MEM_ALLOC_INTERNAL_FAILURE } mali_physical_memory_allocation_result;
+
+typedef struct mali_physical_memory_allocation
+{
+	void (*release)(void * ctx, void * handle); /**< Function to call on to release the physical memory */
+	void * ctx;
+	void * handle;
+	struct mali_physical_memory_allocation * next;
+} mali_physical_memory_allocation;
+
+struct mali_page_table_block;
+
+typedef struct mali_page_table_block
+{
+	void (*release)(struct mali_page_table_block *page_table_block);
+	void * ctx;
+	void * handle;
+	u32 size; /**< In bytes, should be a multiple of MALI_MMU_PAGE_SIZE to avoid internal fragementation */
+	u32 phys_base; /**< Mali physical address */
+	mali_io_address mapping;
+} mali_page_table_block;
+
+
+/** @addtogroup _mali_osk_low_level_memory
+ * @{ */
+
+typedef enum
+{
+	MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE = 0x1,
+	MALI_MEMORY_ALLOCATION_FLAG_MAP_GUARD_PAGE     = 0x2,
+} mali_memory_allocation_flag;
+
+/**
+ * Supplying this 'magic' physical address requests that the OS allocate the
+ * physical address at page commit time, rather than committing a specific page
+ */
+#define MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC ((u32)(-1))
+
+typedef struct mali_memory_allocation
+{
+	/* Information about the allocation */
+	void * mapping; /**< CPU virtual address where the memory is mapped at */
+	u32 mali_address; /**< The Mali seen address of the memory allocation */
+	u32 size; /**< Size of the allocation */
+	u32 permission; /**< Permission settings */
+	mali_memory_allocation_flag flags;
+
+	_mali_osk_lock_t * lock;
+
+	/* Manager specific information pointers */
+	void * mali_addr_mapping_info; /**< Mali address allocation specific info */
+	void * process_addr_mapping_info; /**< Mapping manager specific info */
+
+	mali_physical_memory_allocation physical_allocation;
+
+	_mali_osk_list_t list; /**< List for linking together memory allocations into the session's memory head */
+} mali_memory_allocation;
+/** @} */ /* end group _mali_osk_low_level_memory */
+
+
+typedef struct mali_physical_memory_allocator
+{
+	mali_physical_memory_allocation_result (*allocate)(void* ctx, mali_allocation_engine * engine, mali_memory_allocation * descriptor, u32* offset, mali_physical_memory_allocation * alloc_info);
+	mali_physical_memory_allocation_result (*allocate_page_table_block)(void * ctx, mali_page_table_block * block); /* MALI_MEM_ALLOC_PARTIAL not allowed */
+	void (*destroy)(struct mali_physical_memory_allocator * allocator);
+	u32 (*stat)(struct mali_physical_memory_allocator * allocator);
+	void * ctx;
+	const char * name; /**< Descriptive name for use in mali_allocation_engine_report_allocators, or NULL */
+	u32 alloc_order; /**< Order in which the allocations should happen */
+	struct mali_physical_memory_allocator * next;
+} mali_physical_memory_allocator;
+
+typedef struct mali_kernel_mem_address_manager
+{
+	_mali_osk_errcode_t (*allocate)(mali_memory_allocation *); /**< Function to call to reserve an address */
+	void (*release)(mali_memory_allocation *); /**< Function to call to free the address allocated */
+
+	 /**
+	  * Function called for each physical sub allocation.
+	  * Called for each physical block allocated by the physical memory manager.
+	  * @param[in] descriptor The memory descriptor in question
+	  * @param[in] off Offset from the start of range
+	  * @param[in,out] phys_addr A pointer to the physical address of the start of the
+	  * physical block. When *phys_addr == MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC
+	  * is used, this requests the function to allocate the physical page
+	  * itself, and return it through the pointer provided.
+	  * @param[in] size Length in bytes of the physical block
+	  * @return _MALI_OSK_ERR_OK on success.
+	  * A value of type _mali_osk_errcode_t other than _MALI_OSK_ERR_OK indicates failure.
+	  * Specifically, _MALI_OSK_ERR_UNSUPPORTED indicates that the function
+	  * does not support allocating physical pages itself.
+	  */
+	 _mali_osk_errcode_t (*map_physical)(mali_memory_allocation * descriptor, u32 offset, u32 *phys_addr, u32 size);
+
+	 /**
+	  * Function called to remove a physical sub allocation.
+	  * Called on error paths where one of the address managers fails.
+	  *
+	  * @note this is optional. For address managers where this is not
+	  * implemented, the value of this member is NULL. The memory engine
+	  * currently does not require the mali address manager to be able to
+	  * unmap individual pages, but the process address manager must have this
+	  * capability.
+	  *
+	  * @param[in] descriptor The memory descriptor in question
+	  * @param[in] off Offset from the start of range
+	  * @param[in] size Length in bytes of the physical block
+	  * @param[in] flags flags to use on a per-page basis. For OS-allocated
+	  * physical pages, this must include _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR.
+	  * @return _MALI_OSK_ERR_OK on success.
+	  * A value of type _mali_osk_errcode_t other than _MALI_OSK_ERR_OK indicates failure.
+	  */
+	void (*unmap_physical)(mali_memory_allocation * descriptor, u32 offset, u32 size, _mali_osk_mem_mapregion_flags_t flags);
+
+} mali_kernel_mem_address_manager;
+
+mali_allocation_engine mali_allocation_engine_create(mali_kernel_mem_address_manager * mali_address_manager, mali_kernel_mem_address_manager * process_address_manager);
+
+void mali_allocation_engine_destroy(mali_allocation_engine engine);
+
+int mali_allocation_engine_allocate_memory(mali_allocation_engine engine, mali_memory_allocation * descriptor, mali_physical_memory_allocator * physical_provider, _mali_osk_list_t *tracking_list );
+void mali_allocation_engine_release_memory(mali_allocation_engine engine, mali_memory_allocation * descriptor);
+
+int mali_allocation_engine_map_physical(mali_allocation_engine engine, mali_memory_allocation * descriptor, u32 offset, u32 phys, u32 cpu_usage_adjust, u32 size);
+void mali_allocation_engine_unmap_physical(mali_allocation_engine engine, mali_memory_allocation * descriptor, u32 offset, u32 size, _mali_osk_mem_mapregion_flags_t unmap_flags);
+
+int mali_allocation_engine_allocate_page_tables(mali_allocation_engine, mali_page_table_block * descriptor, mali_physical_memory_allocator * physical_provider);
+
+void mali_allocation_engine_report_allocators(mali_physical_memory_allocator * physical_provider);
+
+u32 mali_allocation_engine_memory_usage(mali_physical_memory_allocator *allocator);
+
+#endif /* __MALI_KERNEL_MEMORY_ENGINE_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_pp.h b/drivers/media/video/samsung/mali/common/mali_kernel_pp.h
new file mode 100644
index 0000000..8cf7bf7
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_pp.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_PP_H__
+#define __MALI_KERNEL_PP_H__
+
+extern struct mali_kernel_subsystem mali_subsystem_mali200;
+
+#if USING_MALI_PMM
+_mali_osk_errcode_t malipp_signal_power_up( u32 core_num, mali_bool queue_only );
+_mali_osk_errcode_t malipp_signal_power_down( u32 core_num, mali_bool immediate_only );
+#endif
+
+#endif /* __MALI_KERNEL_PP_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_profiling.c b/drivers/media/video/samsung/mali/common/mali_kernel_profiling.c
new file mode 100644
index 0000000..ca04b5f
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_profiling.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_osk_mali.h"
+#include "mali_ukk.h"
+#include "mali_timestamp.h"
+#include "mali_kernel_profiling.h"
+#include "mali_linux_trace.h"
+
+typedef struct mali_profiling_entry
+{
+	u64 timestamp;
+	u32 event_id;
+	u32 data[5];
+} mali_profiling_entry;
+
+
+typedef enum mali_profiling_state
+{
+	MALI_PROFILING_STATE_UNINITIALIZED,
+	MALI_PROFILING_STATE_IDLE,
+	MALI_PROFILING_STATE_RUNNING,
+	MALI_PROFILING_STATE_RETURN,
+} mali_profiling_state;
+
+
+static _mali_osk_lock_t *lock = NULL;
+static mali_profiling_state prof_state = MALI_PROFILING_STATE_UNINITIALIZED;
+static mali_profiling_entry* profile_entries = NULL;
+static u32 profile_entry_count = 0;
+static _mali_osk_atomic_t profile_insert_index;
+static _mali_osk_atomic_t profile_entries_written;
+static mali_bool mali_profiling_default_enable = MALI_FALSE;
+
+_mali_osk_errcode_t _mali_profiling_init(mali_bool auto_start)
+{
+	profile_entries = NULL;
+	profile_entry_count = 0;
+	_mali_osk_atomic_init(&profile_insert_index, 0);
+	_mali_osk_atomic_init(&profile_entries_written, 0);
+
+	lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_SPINLOCK | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 0 );
+	if (NULL == lock)
+	{
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	prof_state = MALI_PROFILING_STATE_IDLE;
+
+	if (MALI_TRUE == auto_start)
+	{
+		u32 limit = MALI_PROFILING_MAX_BUFFER_ENTRIES; /* Use maximum buffer size */
+
+		mali_profiling_default_enable = MALI_TRUE; /* save this so user space can query this on their startup */
+		if (_MALI_OSK_ERR_OK != _mali_profiling_start(&limit))
+		{
+			return _MALI_OSK_ERR_FAULT;
+		}
+	}
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void _mali_profiling_term(void)
+{
+	prof_state = MALI_PROFILING_STATE_UNINITIALIZED;
+
+	/* wait for all elements to be completely inserted into array */
+	while (_mali_osk_atomic_read(&profile_insert_index) != _mali_osk_atomic_read(&profile_entries_written))
+	{
+		/* do nothing */;
+	}
+
+	if (NULL != profile_entries)
+	{
+		_mali_osk_vfree(profile_entries);
+		profile_entries = NULL;
+	}
+
+	if (NULL != lock)
+	{
+		_mali_osk_lock_term(lock);
+		lock = NULL;
+	}
+}
+
+inline _mali_osk_errcode_t _mali_profiling_start(u32 * limit)
+{
+	_mali_osk_errcode_t ret;
+
+	mali_profiling_entry *new_profile_entries = _mali_osk_valloc(*limit * sizeof(mali_profiling_entry));
+
+	if(NULL == new_profile_entries)
+	{
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (prof_state != MALI_PROFILING_STATE_IDLE)
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		_mali_osk_vfree(new_profile_entries);
+		return _MALI_OSK_ERR_INVALID_ARGS; /* invalid to call this function in this state */
+	}
+
+	if (*limit > MALI_PROFILING_MAX_BUFFER_ENTRIES)
+	{
+		*limit = MALI_PROFILING_MAX_BUFFER_ENTRIES;
+	}
+
+	profile_entries = new_profile_entries;
+	profile_entry_count = *limit;
+
+	ret = _mali_timestamp_reset();
+
+	if (ret == _MALI_OSK_ERR_OK)
+	{
+		prof_state = MALI_PROFILING_STATE_RUNNING;
+	}
+	else
+	{
+		_mali_osk_vfree(profile_entries);
+		profile_entries = NULL;
+	}
+
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return ret;
+}
+
+inline void _mali_profiling_add_counter(u32 event_id, u32 data0)
+{
+#if MALI_TRACEPOINTS_ENABLED
+	_mali_osk_profiling_add_counter(event_id, data0);	
+#endif
+}
+
+inline _mali_osk_errcode_t _mali_profiling_add_event(u32 event_id, u32 data0, u32 data1, u32 data2, u32 data3, u32 data4)
+{
+	u32 cur_index = _mali_osk_atomic_inc_return(&profile_insert_index) - 1;
+
+#if MALI_TRACEPOINTS_ENABLED
+	_mali_osk_profiling_add_event(event_id, data0);
+#endif
+
+	if (prof_state != MALI_PROFILING_STATE_RUNNING || cur_index >= profile_entry_count)
+	{
+		/*
+		 * Not in recording mode, or buffer is full
+		 * Decrement index again, and early out
+		 */
+		_mali_osk_atomic_dec(&profile_insert_index);
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	profile_entries[cur_index].timestamp = _mali_timestamp_get();
+	profile_entries[cur_index].event_id = event_id;
+	profile_entries[cur_index].data[0] = data0;
+	profile_entries[cur_index].data[1] = data1;
+	profile_entries[cur_index].data[2] = data2;
+	profile_entries[cur_index].data[3] = data3;
+	profile_entries[cur_index].data[4] = data4;
+
+	_mali_osk_atomic_inc(&profile_entries_written);
+
+	return _MALI_OSK_ERR_OK;
+}
+
+#if MALI_TRACEPOINTS_ENABLED
+/*
+ * The following code uses a bunch of magic numbers taken from the userspace
+ * side of the DDK; they are re-used here verbatim. They are taken from the 
+ * file mali_instrumented_counter_types.h.
+ */
+#define MALI_GLES_COUNTER_OFFSET   1000
+#define MALI_VG_COUNTER_OFFSET     2000
+#define MALI_EGL_COUNTER_OFFSET    3000
+#define MALI_SHARED_COUNTER_OFFSET 4000
+
+/* These offsets are derived from the gator driver; see gator_events_mali.c. */
+#define GATOR_EGL_COUNTER_OFFSET    17
+#define GATOR_GLES_COUNTER_OFFSET   18
+
+_mali_osk_errcode_t _mali_ukk_transfer_sw_counters(_mali_uk_sw_counters_s *args)
+{
+	/* Convert the DDK counter ID to what gator expects */
+	unsigned int gator_counter_value = 0;
+
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (args->id >= MALI_EGL_COUNTER_OFFSET && args->id <= MALI_SHARED_COUNTER_OFFSET)
+	{
+		gator_counter_value = (args->id - MALI_EGL_COUNTER_OFFSET) + GATOR_EGL_COUNTER_OFFSET;
+	}
+	else if (args->id >= MALI_GLES_COUNTER_OFFSET && args->id <= MALI_VG_COUNTER_OFFSET)
+	{
+		gator_counter_value = (args->id - MALI_GLES_COUNTER_OFFSET) + GATOR_GLES_COUNTER_OFFSET;
+	}
+	else 
+	{
+		/* Pass it straight through; gator will ignore it anyway. */
+		gator_counter_value = args->id;
+	}
+
+	trace_mali_sw_counter(gator_counter_value, args->value);
+
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+
+	return _MALI_OSK_ERR_OK;
+}
+#endif
+
+inline _mali_osk_errcode_t _mali_profiling_stop(u32 * count)
+{
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (prof_state != MALI_PROFILING_STATE_RUNNING)
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return _MALI_OSK_ERR_INVALID_ARGS; /* invalid to call this function in this state */
+	}
+
+	/* go into return state (user to retreive events), no more events will be added after this */
+	prof_state = MALI_PROFILING_STATE_RETURN;
+
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* wait for all elements to be completely inserted into array */
+	while (_mali_osk_atomic_read(&profile_insert_index) != _mali_osk_atomic_read(&profile_entries_written))
+	{
+		/* do nothing */;
+	}
+
+	*count = _mali_osk_atomic_read(&profile_insert_index);
+
+	return _MALI_OSK_ERR_OK;
+}
+
+inline u32 _mali_profiling_get_count(void)
+{
+	u32 retval = 0;
+
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+	if (prof_state == MALI_PROFILING_STATE_RETURN)
+	{
+		retval = _mali_osk_atomic_read(&profile_entries_written);
+	}
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+
+	return retval;
+}
+
+inline _mali_osk_errcode_t _mali_profiling_get_event(u32 index, u64* timestamp, u32* event_id, u32 data[5])
+{
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (prof_state != MALI_PROFILING_STATE_RETURN)
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return _MALI_OSK_ERR_INVALID_ARGS; /* invalid to call this function in this state */
+	}
+
+	if (index >= _mali_osk_atomic_read(&profile_entries_written))
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	*timestamp = profile_entries[index].timestamp;
+	*event_id = profile_entries[index].event_id;
+	data[0] = profile_entries[index].data[0];
+	data[1] = profile_entries[index].data[1];
+	data[2] = profile_entries[index].data[2];
+	data[3] = profile_entries[index].data[3];
+	data[4] = profile_entries[index].data[4];
+
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return _MALI_OSK_ERR_OK;
+}
+
+inline _mali_osk_errcode_t _mali_profiling_clear(void)
+{
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (prof_state != MALI_PROFILING_STATE_RETURN)
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return _MALI_OSK_ERR_INVALID_ARGS; /* invalid to call this function in this state */
+	}
+
+	prof_state = MALI_PROFILING_STATE_IDLE;
+	profile_entry_count = 0;
+	_mali_osk_atomic_init(&profile_insert_index, 0);
+	_mali_osk_atomic_init(&profile_entries_written, 0);
+	if (NULL != profile_entries)
+	{
+		_mali_osk_vfree(profile_entries);
+		profile_entries = NULL;
+	}
+
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return _MALI_OSK_ERR_OK;
+}
+
+mali_bool _mali_profiling_is_recording(void)
+{
+	return prof_state == MALI_PROFILING_STATE_RUNNING ? MALI_TRUE : MALI_FALSE;
+}
+
+mali_bool _mali_profiling_have_recording(void)
+{
+	return prof_state == MALI_PROFILING_STATE_RETURN ? MALI_TRUE : MALI_FALSE;
+}
+
+void _mali_profiling_set_default_enable_state(mali_bool enable)
+{
+	mali_profiling_default_enable = enable;
+}
+
+mali_bool _mali_profiling_get_default_enable_state(void)
+{
+	return mali_profiling_default_enable;
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_start(_mali_uk_profiling_start_s *args)
+{
+	return _mali_profiling_start(&args->limit);
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_add_event(_mali_uk_profiling_add_event_s *args)
+{
+	/* Always add process and thread identificator in the first two data elements for events from user space */
+	return _mali_profiling_add_event(args->event_id, _mali_osk_get_pid(), _mali_osk_get_tid(), args->data[2], args->data[3], args->data[4]);
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_stop(_mali_uk_profiling_stop_s *args)
+{
+	return _mali_profiling_stop(&args->count);
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_get_event(_mali_uk_profiling_get_event_s *args)
+{
+	return _mali_profiling_get_event(args->index, &args->timestamp, &args->event_id, args->data);
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_clear(_mali_uk_profiling_clear_s *args)
+{
+	return _mali_profiling_clear();
+}
+
+_mali_osk_errcode_t _mali_ukk_profiling_get_config(_mali_uk_profiling_get_config_s *args)
+{
+	args->enable_events = mali_profiling_default_enable;
+	return _MALI_OSK_ERR_OK;
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_profiling.h b/drivers/media/video/samsung/mali/common/mali_kernel_profiling.h
new file mode 100644
index 0000000..eb1e6c2
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_profiling.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_PROFILING_H__
+#define __MALI_KERNEL_PROFILING_H__
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+
+#include "cinstr/mali_cinstr_profiling_events_m200.h"
+
+#define MALI_PROFILING_MAX_BUFFER_ENTRIES 1048576
+
+/**
+ * Initialize the profiling module.
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t _mali_profiling_init(mali_bool auto_start);
+
+/*
+ * Terminate the profiling module.
+ */
+void _mali_profiling_term(void);
+
+/** Add a counter event
+ * @param event_id - Magic counter id
+ * @param data0 - Value of counter
+ */
+void _mali_profiling_add_counter(u32 event_id, u32 data0);
+
+/**
+ * Start recording profiling data
+ *
+ * The specified limit will determine how large the capture buffer is.
+ * MALI_PROFILING_MAX_BUFFER_ENTRIES determines the maximum size allowed by the device driver.
+ *
+ * @param limit The desired maximum number of events to record on input, the actual maximum on output.
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t _mali_profiling_start(u32 * limit);
+
+/**
+ * Add an profiling event
+ *
+ * @param event_id The event identificator.
+ * @param data0 First data parameter, depending on event_id specified.
+ * @param data1 Second data parameter, depending on event_id specified.
+ * @param data2 Third data parameter, depending on event_id specified.
+ * @param data3 Fourth data parameter, depending on event_id specified.
+ * @param data4 Fifth data parameter, depending on event_id specified.
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t _mali_profiling_add_event(u32 event_id, u32 data0, u32 data1, u32 data2, u32 data3, u32 data4);
+
+/**
+ * Stop recording profiling data
+ *
+ * @param count Returns the number of recorded events.
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t _mali_profiling_stop(u32 * count);
+
+/**
+ * Retrieves the number of events that can be retrieved
+ *
+ * @return The number of recorded events that can be retrieved.
+ */
+u32 _mali_profiling_get_count(void);
+
+/**
+ * Retrieve an event
+ *
+ * @param index Event index (start with 0 and continue until this function fails to retrieve all events)
+ * @param timestamp The timestamp for the retrieved event will be stored here.
+ * @param event_id The event ID for the retrieved event will be stored here.
+ * @param data The 5 data values for the retrieved event will be stored here.
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */_mali_osk_errcode_t _mali_profiling_get_event(u32 index, u64* timestamp, u32* event_id, u32 data[5]);
+
+/**
+ * Clear the recorded buffer.
+ *
+ * This is needed in order to start another recording.
+ *
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t _mali_profiling_clear(void);
+
+/**
+ * Checks if a recording of profiling data is in progress
+ *
+ * @return MALI_TRUE if recording of profiling data is in progress, MALI_FALSE if not
+ */
+mali_bool _mali_profiling_is_recording(void);
+
+/**
+ * Checks if profiling data is available for retrival
+ *
+ * @return MALI_TRUE if profiling data is avaiable, MALI_FALSE if not
+ */
+mali_bool _mali_profiling_have_recording(void);
+
+/**
+ * Enable or disable profiling events as default for new sessions (applications)
+ *
+ * @param enable MALI_TRUE if profiling events should be turned on, otherwise MALI_FALSE
+ */
+void _mali_profiling_set_default_enable_state(mali_bool enable);
+
+/**
+ * Get current default enable state for new sessions (applications)
+ *
+ * @return MALI_TRUE if profiling events should be turned on, otherwise MALI_FALSE
+ */
+mali_bool _mali_profiling_get_default_enable_state(void);
+
+#endif /* MALI_TIMELINE_PROFILING_ENABLED */
+
+#endif /* __MALI_KERNEL_PROFILING_H__ */
+
+
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.c b/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.c
new file mode 100644
index 0000000..cfc5ec1
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.c
@@ -0,0 +1,2031 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_kernel_core.h"
+#include "mali_osk.h"
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_rendercore.h"
+#include "mali_osk_list.h"
+#if MALI_GPU_UTILIZATION
+#include "mali_kernel_utilization.h"
+#endif
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+#if USING_MMU
+#include "mali_kernel_mem_mmu.h"
+#endif /* USING_MMU */
+#if defined USING_MALI400_L2_CACHE
+#include "mali_kernel_l2_cache.h"
+#endif /* USING_MALI400_L2_CACHE */
+
+#define HANG_CHECK_MSECS_MIN 100
+#define HANG_CHECK_MSECS_MAX 2000 /* 2 secs */
+#define HANG_CHECK_MSECS_DEFAULT 500 /* 500 ms */
+
+#define WATCHDOG_MSECS_MIN (10*HANG_CHECK_MSECS_MIN)
+#define WATCHDOG_MSECS_MAX 3600000 /* 1 hour */
+#define WATCHDOG_MSECS_DEFAULT 4000 /* 4 secs */
+
+/* max value that will be converted from jiffies to micro seconds and written to job->render_time_usecs */
+#define JOB_MAX_JIFFIES 100000
+
+int mali_hang_check_interval = HANG_CHECK_MSECS_DEFAULT;
+int mali_max_job_runtime = WATCHDOG_MSECS_DEFAULT;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+int mali_boot_profiling = 0;
+#endif
+
+#ifdef MALI_REBOOTNOTIFIER
+extern _mali_osk_atomic_t mali_shutdown_state;
+#endif
+
+/* Subsystem entrypoints: */
+static _mali_osk_errcode_t rendercore_subsystem_startup(mali_kernel_subsystem_identifier id);
+static void rendercore_subsystem_terminate(mali_kernel_subsystem_identifier id);
+#if USING_MMU
+static void rendercore_subsystem_broadcast_notification(mali_core_notification_message message, u32 data);
+#endif
+
+
+static void mali_core_subsystem_cleanup_all_renderunits(struct mali_core_subsystem* subsys);
+static void mali_core_subsystem_move_core_set_idle(struct mali_core_renderunit *core);
+
+static mali_core_session * mali_core_subsystem_get_waiting_session(mali_core_subsystem *subsystem);
+static mali_core_job * mali_core_subsystem_release_session_get_job(mali_core_subsystem *subsystem, mali_core_session * session);
+
+static void find_and_abort(mali_core_session* session, u32 abort_id);
+
+static void mali_core_job_start_on_core(mali_core_job *job, mali_core_renderunit *core);
+#if USING_MMU
+static void mali_core_subsystem_callback_schedule_wrapper(void* sub);
+#endif
+static void mali_core_subsystem_schedule(mali_core_subsystem*subsystem);
+static void mali_core_renderunit_detach_job_from_core(mali_core_renderunit* core, mali_subsystem_reschedule_option reschedule, mali_subsystem_job_end_code end_status);
+
+static void  mali_core_renderunit_irq_handler_remove(struct mali_core_renderunit *core);
+
+static _mali_osk_errcode_t  mali_core_irq_handler_upper_half (void * data);
+static void mali_core_irq_handler_bottom_half ( void *data );
+
+#if USING_MMU
+static void lock_subsystem(struct mali_core_subsystem * subsys);
+static void unlock_subsystem(struct mali_core_subsystem * subsys);
+#endif
+
+
+/**
+ * This will be one of the subsystems in the array of subsystems:
+ * static struct mali_kernel_subsystem * subsystems[];
+ * found in file: mali_kernel_core.c
+ *
+ * This subsystem is necessary for operations common to all rendercore
+ * subsystems. For example, mali_subsystem_mali200 and mali_subsystem_gp2 may
+ * share a mutex when RENDERCORES_USE_GLOBAL_MUTEX is non-zero.
+ */
+struct mali_kernel_subsystem mali_subsystem_rendercore=
+{
+	rendercore_subsystem_startup,                  /* startup */
+	NULL, /*rendercore_subsystem_terminate,*/                /* shutdown */
+	NULL,                                          /* load_complete */
+	NULL,                                          /* system_info_fill */
+	NULL,                                          /* session_begin */
+	NULL,                                          /* session_end */
+#if USING_MMU
+	rendercore_subsystem_broadcast_notification,  /* broadcast_notification */
+#else
+	NULL,
+#endif
+#if MALI_STATE_TRACKING
+	NULL,                                          /* dump_state */
+#endif
+} ;
+
+static _mali_osk_lock_t *rendercores_global_mutex = NULL;
+static u32 rendercores_global_mutex_is_held = 0;
+static u32 rendercores_global_mutex_owner = 0;
+
+/** The 'dummy' rendercore subsystem to allow global subsystem mutex to be
+ * locked for all subsystems that extend the ''rendercore'' */
+static mali_core_subsystem rendercore_dummy_subsystem = {0,};
+
+/*
+ * Rendercore Subsystem functions.
+ *
+ * These are exposed by mali_subsystem_rendercore
+ */
+
+/**
+ * @brief Initialize the Rendercore subsystem.
+ *
+ * This must be called before any other subsystem that extends the
+ * ''rendercore'' may be initialized. For example, this must be called before
+ * the following functions:
+ * - mali200_subsystem_startup(), from mali_subsystem_mali200
+ * - maligp_subsystem_startup(), from mali_subsystem_gp2
+ *
+ * @note This function is separate from mali_core_subsystem_init(). They
+ * are related, in that mali_core_subsystem_init() may use the structures
+ * initialized by rendercore_subsystem_startup()
+ */
+static _mali_osk_errcode_t rendercore_subsystem_startup(mali_kernel_subsystem_identifier id)
+{
+	rendercores_global_mutex_is_held = 0;
+	rendercores_global_mutex = _mali_osk_lock_init(
+					(_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ORDERED),
+					0, 129);
+
+    if (NULL == rendercores_global_mutex)
+    {
+		MALI_PRINT_ERROR(("Failed: _mali_osk_lock_init\n")) ;
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+    }
+
+	rendercore_dummy_subsystem.name = "Rendercore Global Subsystem"; /* On the constant pool, do not free */
+	rendercore_dummy_subsystem.magic_nr = SUBSYSTEM_MAGIC_NR; /* To please the Subsystem Mutex code */
+
+#if MALI_GPU_UTILIZATION
+	if (mali_utilization_init() != _MALI_OSK_ERR_OK)
+	{
+		_mali_osk_lock_term(rendercores_global_mutex);
+		rendercores_global_mutex = NULL;
+		MALI_PRINT_ERROR(("Failed: mali_utilization_init\n")) ;
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	if (_mali_profiling_init(mali_boot_profiling ? MALI_TRUE : MALI_FALSE) != _MALI_OSK_ERR_OK)
+	{
+		/* No biggie if we wheren't able to initialize the profiling */
+		MALI_PRINT_ERROR(("Rendercore: Failed to initialize profiling, feature will be unavailable\n")) ;
+	}
+#endif
+
+	MALI_DEBUG_PRINT(2, ("Rendercore: subsystem global mutex initialized\n")) ;
+	MALI_SUCCESS;
+}
+
+/**
+ * @brief Terminate the Rendercore subsystem.
+ *
+ * This must only be called \b after any other subsystem that extends the
+ * ''rendercore'' has been terminated. For example, this must be called \b after
+ * the following functions:
+ * - mali200_subsystem_terminate(), from mali_subsystem_mali200
+ * - maligp_subsystem_terminate(), from mali_subsystem_gp2
+ *
+ * @note This function is separate from mali_core_subsystem_cleanup(), though,
+ * the subsystems that extend ''rendercore'' must still call
+ * mali_core_subsystem_cleanup() when they terminate.
+ */
+static void rendercore_subsystem_terminate(mali_kernel_subsystem_identifier id)
+{
+	/* Catch double-terminate */
+	MALI_DEBUG_ASSERT_POINTER( rendercores_global_mutex );
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	_mali_profiling_term();
+#endif
+
+#if MALI_GPU_UTILIZATION
+	mali_utilization_term();
+#endif
+
+	rendercore_dummy_subsystem.name = NULL; /* The original string was on the constant pool, do not free */
+	rendercore_dummy_subsystem.magic_nr = 0;
+
+	/* ASSERT that no-one's holding this */
+	MALI_DEBUG_PRINT_ASSERT( 0 == rendercores_global_mutex_is_held,
+							 ("Rendercores' Global Mutex was held at termination time. Have the subsystems that extend ''rendercore'' been terminated?\n") );
+
+	_mali_osk_lock_term( rendercores_global_mutex );
+	rendercores_global_mutex = NULL;
+
+	MALI_DEBUG_PRINT(2, ("Rendercore: subsystem global mutex terminated\n")) ;
+}
+
+
+#if USING_MMU
+/**
+ * @brief Handle certain Rendercore subsystem broadcast notifications
+ *
+ * When RENDERCORES_USE_GLOBAL_MUTEX is non-zero, this handles the following messages:
+ * - MMU_KILL_STEP0_LOCK_SUBSYSTEM
+ * - MMU_KILL_STEP4_UNLOCK_SUBSYSTEM
+ *
+ * The purpose is to manage the Rendercode Global Mutex, which cannot be
+ * managed by any system that extends the ''rendercore''.
+ *
+ * All other messages must be handled by mali_core_subsystem_broadcast_notification()
+ *
+ *
+ * When RENDERCORES_USE_GLOBAL_MUTEX is 0, this function does nothing.
+ * Instead, the subsystem that extends the ''rendercore' \b must handle its
+ * own mutexes - refer to mali_core_subsystem_broadcast_notification().
+ *
+ * Used currently only for signalling when MMU has a pagefault
+ */
+static void rendercore_subsystem_broadcast_notification(mali_core_notification_message message, u32 data)
+{
+	switch(message)
+	{
+		case MMU_KILL_STEP0_LOCK_SUBSYSTEM:
+			lock_subsystem( &rendercore_dummy_subsystem );
+			break;
+		case MMU_KILL_STEP4_UNLOCK_SUBSYSTEM:
+			unlock_subsystem( &rendercore_dummy_subsystem );
+			break;
+
+		case MMU_KILL_STEP1_STOP_BUS_FOR_ALL_CORES:
+			/** FALLTHROUGH */
+		case MMU_KILL_STEP2_RESET_ALL_CORES_AND_ABORT_THEIR_JOBS:
+			/** FALLTHROUGH */
+		case MMU_KILL_STEP3_CONTINUE_JOB_HANDLING:
+			break;
+
+		default:
+			MALI_PRINT_ERROR(("Illegal message: 0x%x, data: 0x%x\n", (u32)message, data));
+			break;
+	}
+
+}
+#endif
+
+/*
+ * Functions inherited by the subsystems that extend the ''rendercore''.
+ */
+
+void mali_core_renderunit_timeout_function_hang_detection(void *arg)
+{
+	mali_bool action = MALI_FALSE;
+	mali_core_renderunit * core;
+
+	core = (mali_core_renderunit *) arg;
+	if( !core ) return;
+
+	/* if NOT idle OR NOT powered off OR has TIMED_OUT */
+	if ( !((CORE_WATCHDOG_TIMEOUT == core->state ) || (CORE_IDLE== core->state) || (CORE_OFF == core->state)) )
+	{
+		core->state = CORE_HANG_CHECK_TIMEOUT;
+		action = MALI_TRUE;
+	}
+
+	if(action) _mali_osk_irq_schedulework(core->irq);
+}
+
+
+void mali_core_renderunit_timeout_function(void *arg)
+{
+	mali_core_renderunit * core;
+	mali_bool is_watchdog;
+
+	core = (mali_core_renderunit *)arg;
+	if( !core ) return;
+
+	is_watchdog = MALI_TRUE;
+	if (mali_benchmark)
+	{
+		/* poll based core */
+		mali_core_job *job;
+		job = core->current_job;
+		if ( (NULL != job) &&
+		     (0 != _mali_osk_time_after(job->watchdog_jiffies,_mali_osk_time_tickcount()))
+		   )
+		{
+			core->state = CORE_POLL;
+			is_watchdog = MALI_FALSE;
+		}
+	}
+
+	if (is_watchdog)
+	{
+		MALI_DEBUG_PRINT(3, ("SW-Watchdog timeout: Core:%s\n", core->description));
+		core->state = CORE_WATCHDOG_TIMEOUT;
+	}
+
+	_mali_osk_irq_schedulework(core->irq);
+}
+
+/* Used by external renderunit_create<> function */
+_mali_osk_errcode_t mali_core_renderunit_init(mali_core_renderunit * core)
+{
+	MALI_DEBUG_PRINT(5, ("Core: renderunit_init: Core:%s\n", core->description));
+
+	_MALI_OSK_INIT_LIST_HEAD(&core->list) ;
+	core->timer = _mali_osk_timer_init();
+    if (NULL == core->timer)
+    {
+	    MALI_PRINT_ERROR(("Core: renderunit_init: Core:%s -- cannot init timer\n", core->description));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+    }
+
+    _mali_osk_timer_setcallback(core->timer, mali_core_renderunit_timeout_function, (void *)core);
+
+	core->timer_hang_detection = _mali_osk_timer_init();
+    if (NULL == core->timer_hang_detection)
+    {
+        _mali_osk_timer_term(core->timer);
+	    MALI_PRINT_ERROR(("Core: renderunit_init: Core:%s -- cannot init hang detection timer\n", core->description));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+    }
+
+    _mali_osk_timer_setcallback(core->timer_hang_detection, mali_core_renderunit_timeout_function_hang_detection, (void *)core);
+
+#if USING_MALI_PMM
+	/* Init no pending power downs */
+	core->pend_power_down = MALI_FALSE;
+	
+	/* Register the core with the PMM - which powers it up */
+	if (_MALI_OSK_ERR_OK != malipmm_core_register( core->pmm_id ))
+	{
+		_mali_osk_timer_term(core->timer);
+		_mali_osk_timer_term(core->timer_hang_detection);
+	    MALI_PRINT_ERROR(("Core: renderunit_init: Core:%s -- cannot register with PMM\n", core->description));        
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#endif /* USING_MALI_PMM */
+
+	core->error_recovery = MALI_FALSE;
+	core->in_detach_function = MALI_FALSE;
+	core->state = CORE_IDLE;
+	core->current_job = NULL;
+	core->magic_nr = CORE_MAGIC_NR;
+#if USING_MMU
+	core->mmu = NULL;
+#endif /* USING_MMU */
+
+    MALI_SUCCESS;
+}
+
+void mali_core_renderunit_term(mali_core_renderunit * core)
+{
+	MALI_DEBUG_PRINT(5, ("Core: renderunit_term: Core:%s\n", core->description));
+
+    if (NULL != core->timer)
+    {
+        _mali_osk_timer_term(core->timer);
+        core->timer = NULL;
+    }
+    if (NULL != core->timer_hang_detection)
+    {
+        _mali_osk_timer_term(core->timer_hang_detection);
+        core->timer_hang_detection = NULL;
+    }
+
+#if USING_MALI_PMM
+	/* Unregister the core with the PMM */
+	malipmm_core_unregister( core->pmm_id );
+#endif
+}
+
+/* Used by external renderunit_create<> function */
+_mali_osk_errcode_t mali_core_renderunit_map_registers(mali_core_renderunit *core)
+{
+	MALI_DEBUG_PRINT(3, ("Core: renderunit_map_registers: Core:%s\n", core->description)) ;
+	if( (0 == core->registers_base_addr) ||
+	    (0 == core->size) ||
+	    (NULL == core->description)
+	  )
+	{
+		MALI_PRINT_ERROR(("Missing fields in the core structure %u %u 0x%x;\n", core->registers_base_addr, core->size, core->description));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	if (_MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(core->registers_base_addr, core->size, core->description))
+	{
+		MALI_PRINT_ERROR(("Could not request register region (0x%08X - 0x%08X) to core: %s\n",
+		         core->registers_base_addr, core->registers_base_addr + core->size - 1, core->description));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+	else
+	{
+		MALI_DEBUG_PRINT(6, ("Success: request_mem_region: (0x%08X - 0x%08X) Core:%s\n",
+		        core->registers_base_addr, core->registers_base_addr + core->size - 1, core->description));
+	}
+
+	core->registers_mapped = _mali_osk_mem_mapioregion( core->registers_base_addr, core->size, core->description );
+
+	if ( 0 == core->registers_mapped )
+	{
+		MALI_PRINT_ERROR(("Could not ioremap registers for %s .\n", core->description));
+		_mali_osk_mem_unreqregion(core->registers_base_addr, core->size);
+        MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+	}
+	else
+	{
+		MALI_DEBUG_PRINT(6, ("Success: ioremap_nocache: Internal ptr: (0x%08X - 0x%08X) Core:%s\n",
+		        (u32) core->registers_mapped,
+		        ((u32)core->registers_mapped)+ core->size - 1,
+		        core->description));
+	}
+
+	MALI_DEBUG_PRINT(4, ("Success: Mapping registers to core: %s\n",core->description));
+
+	MALI_SUCCESS;
+}
+
+/* Used by external renderunit_create<> function + other places */
+void mali_core_renderunit_unmap_registers(mali_core_renderunit *core)
+{
+	MALI_DEBUG_PRINT(3, ("Core: renderunit_unmap_registers: Core:%s\n", core->description));
+	if (0 == core->registers_mapped)
+	{
+		MALI_PRINT_ERROR(("Trying to unmap register-mapping with NULL from core: %s\n", core->description));
+		return;
+	}
+	_mali_osk_mem_unmapioregion(core->registers_base_addr, core->size, core->registers_mapped);
+	core->registers_mapped = 0;
+	_mali_osk_mem_unreqregion(core->registers_base_addr, core->size);
+}
+
+static void mali_core_renderunit_irq_handler_remove(mali_core_renderunit *core)
+{
+	MALI_DEBUG_PRINT(3, ("Core: renderunit_irq_handler_remove: Core:%s\n", core->description));
+    _mali_osk_irq_term(core->irq);
+}
+
+mali_core_renderunit * mali_core_renderunit_get_mali_core_nr(mali_core_subsystem *subsys, u32 mali_core_nr)
+{
+	mali_core_renderunit * core;
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+	if (subsys->number_of_cores <= mali_core_nr)
+	{
+		MALI_PRINT_ERROR(("Trying to get illegal mali_core_nr: 0x%x for %s", mali_core_nr, subsys->name));
+		return NULL;
+	}
+	core = (subsys->mali_core_array)[mali_core_nr];
+	MALI_DEBUG_PRINT(6, ("Core: renderunit_get_mali_core_nr: Core:%s\n", core->description));
+	MALI_CHECK_CORE(core);
+	return core;
+}
+
+/* Is used by external function:
+	subsystem_startup<> */
+_mali_osk_errcode_t mali_core_subsystem_init(mali_core_subsystem* new_subsys)
+{
+	int i;
+
+	/* These function pointers must have been set on before calling this function */
+	if (
+	       ( NULL == new_subsys->name ) ||
+	       ( NULL == new_subsys->start_job ) ||
+	       ( NULL == new_subsys->irq_handler_upper_half ) ||
+	       ( NULL == new_subsys->irq_handler_bottom_half ) ||
+	       ( NULL == new_subsys->get_new_job_from_user ) ||
+	       ( NULL == new_subsys->return_job_to_user )
+	   )
+	{
+		MALI_PRINT_ERROR(("Missing functions in subsystem."));
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	MALI_DEBUG_PRINT(2, ("Core: subsystem_init: %s\n", new_subsys->name)) ;
+
+	/* Catch use-before-initialize/use-after-terminate */
+	MALI_DEBUG_ASSERT_POINTER( rendercores_global_mutex );
+
+	new_subsys->magic_nr = SUBSYSTEM_MAGIC_NR;
+
+	_MALI_OSK_INIT_LIST_HEAD(&new_subsys->renderunit_idle_head); /* Idle cores of this type */
+	_MALI_OSK_INIT_LIST_HEAD(&new_subsys->renderunit_off_head);  /* Powered off cores of this type */
+
+	/* Linked list for each priority of sessions with a job ready for scheduleing */
+	for(i=0; i<PRIORITY_LEVELS; ++i)
+	{
+		_MALI_OSK_INIT_LIST_HEAD(&new_subsys->awaiting_sessions_head[i]);
+	}
+
+	/* Linked list of all sessions connected to this coretype */
+	_MALI_OSK_INIT_LIST_HEAD(&new_subsys->all_sessions_head);
+
+	MALI_SUCCESS;
+}
+
+#if USING_MMU
+void mali_core_subsystem_attach_mmu(mali_core_subsystem* subsys)
+{
+	u32 i;
+	mali_core_renderunit * core;
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+		if ( NULL==core ) break;
+		core->mmu = mali_memory_core_mmu_lookup(core->mmu_id);
+		mali_memory_core_mmu_owner(core,core->mmu);
+		MALI_DEBUG_PRINT(2, ("Attach mmu: 0x%x to core: %s in subsystem: %s\n", core->mmu, core->description, subsys->name));
+	}
+
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+}
+#endif
+
+/* This will register an IRQ handler, and add the core to the list of available cores for this subsystem. */
+_mali_osk_errcode_t mali_core_subsystem_register_renderunit(mali_core_subsystem* subsys, mali_core_renderunit * core)
+{
+	mali_core_renderunit ** mali_core_array;
+	u32 previous_nr;
+	u32 previous_size;
+	u32 new_nr;
+	u32 new_size;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
+
+	/* If any of these are 0 there is an error */
+	if(0 == core->subsystem ||
+	   0 == core->registers_base_addr ||
+	   0 == core->size ||
+	   0 == core->description)
+	{
+		MALI_PRINT_ERROR(("Missing fields in the core structure 0x%x 0x%x 0x%x;\n",
+		        core->registers_base_addr, core->size, core->description));
+        MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+
+	MALI_DEBUG_PRINT(3, ("Core: subsystem_register_renderunit: %s\n", core->description));
+
+	MALI_CHECK_NON_NULL(
+        core->irq = _mali_osk_irq_init(
+                            core->irq_nr,
+                            mali_core_irq_handler_upper_half,
+                            mali_core_irq_handler_bottom_half,
+                            (_mali_osk_irq_trigger_t)subsys->probe_core_irq_trigger,
+                            (_mali_osk_irq_ack_t)subsys->probe_core_irq_acknowledge,
+                            core,
+                            "mali_core_irq_handlers"
+                            ),
+        _MALI_OSK_ERR_FAULT
+        );
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+
+	/* Update which core number this is */
+	core->core_number = subsys->number_of_cores;
+
+	/* Update the array of cores in the subsystem. */
+	previous_nr   = subsys->number_of_cores;
+	previous_size = sizeof(mali_core_renderunit*)*previous_nr;
+	new_nr        = previous_nr + 1;
+	new_size      = sizeof(mali_core_renderunit*)*new_nr;
+
+	if (0 != previous_nr)
+	{
+		if (NULL == subsys->mali_core_array)
+		{
+			MALI_PRINT_ERROR(("Internal error"));
+			goto exit_function;
+		}
+
+		mali_core_array = (mali_core_renderunit **) _mali_osk_malloc( new_size );
+		if (NULL == mali_core_array )
+		{
+			MALI_PRINT_ERROR(("Out of mem"));
+            err = _MALI_OSK_ERR_NOMEM;
+			goto exit_function;
+		}
+		_mali_osk_memcpy(mali_core_array, subsys->mali_core_array, previous_size);
+		_mali_osk_free( subsys->mali_core_array);
+		MALI_DEBUG_PRINT(5, ("Success: adding a new core to subsystem array %s\n", core->description) ) ;
+	}
+	else
+	{
+		mali_core_array = (mali_core_renderunit **) _mali_osk_malloc( new_size );
+		if (NULL == mali_core_array )
+		{
+			MALI_PRINT_ERROR(("Out of mem"));
+            err = _MALI_OSK_ERR_NOMEM;
+			goto exit_function;
+		}
+		MALI_DEBUG_PRINT(6, ("Success: adding first core to subsystem array %s\n", core->description) ) ;
+	}
+	subsys->mali_core_array = mali_core_array;
+	mali_core_array[previous_nr] = core;
+
+	/* Add the core to the list of available cores on the system */
+	_mali_osk_list_add(&(core->list), &(subsys->renderunit_idle_head));
+
+	/* Update total number of cores */
+	subsys->number_of_cores = new_nr;
+	MALI_DEBUG_PRINT(6, ("Success: mali_core_subsystem_register_renderunit %s\n", core->description));
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+    MALI_SUCCESS;
+
+exit_function:
+	mali_core_renderunit_irq_handler_remove(core);
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+    MALI_ERROR(err);
+}
+
+
+/**
+ * Called by the core when a system info update is needed
+ * We fill in info about all the core types available
+ * @param subsys Pointer to the core's @a mali_core_subsystem data structure
+ * @param info Pointer to system info struct to update
+ * @return _MALI_OSK_ERR_OK on success, or another _mali_osk_errcode_t error code on failure
+ */
+_mali_osk_errcode_t mali_core_subsystem_system_info_fill(mali_core_subsystem* subsys, _mali_system_info* info)
+{
+ 	u32 i;
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;  /* OK if no cores to update info for */
+	mali_core_renderunit * core;
+	_mali_core_info **core_info_nextp;
+	_mali_core_info * cinfo;
+
+	MALI_DEBUG_PRINT(4, ("mali_core_subsystem_system_info_fill: %s\n", subsys->name) ) ;
+
+	/* check input */
+    MALI_CHECK_NON_NULL(info, _MALI_OSK_ERR_INVALID_ARGS);
+
+	core_info_nextp = &(info->core_info);
+	cinfo = info->core_info;
+
+	while(NULL!=cinfo)
+	{
+		core_info_nextp = &(cinfo->next);
+		cinfo = cinfo->next;
+	}
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+		if ( NULL==core )
+		{
+			err = _MALI_OSK_ERR_FAULT;
+			goto early_exit;
+		}
+		cinfo = (_mali_core_info *)_mali_osk_calloc(1, sizeof(_mali_core_info));
+		if ( NULL==cinfo )
+		{
+			err = _MALI_OSK_ERR_NOMEM;
+			goto early_exit;
+		}
+		cinfo->version = core->core_version;
+		cinfo->type =subsys->core_type;
+		cinfo->reg_address = core->registers_base_addr;
+		cinfo->core_nr     = i;
+		cinfo->next = NULL;
+		/* Writing this address to the previous' *(&next) ptr */
+		*core_info_nextp = cinfo;
+		/* Setting the next_ptr to point to &this->next_ptr */
+		core_info_nextp = &(cinfo->next);
+	}
+early_exit:
+	if ( _MALI_OSK_ERR_OK != err) MALI_PRINT_ERROR(("Error: In mali_core_subsystem_system_info_fill %d\n", err));
+	MALI_DEBUG_CODE(
+		cinfo = info->core_info;
+
+		MALI_DEBUG_PRINT(3, ("Current list of cores\n"));
+		while( NULL != cinfo )
+		{
+			MALI_DEBUG_PRINT(3, ("Type:     0x%x\n", cinfo->type));
+			MALI_DEBUG_PRINT(3, ("Version:  0x%x\n", cinfo->version));
+			MALI_DEBUG_PRINT(3, ("Reg_addr: 0x%x\n", cinfo->reg_address));
+			MALI_DEBUG_PRINT(3, ("Core_nr:  0x%x\n", cinfo->core_nr));
+			MALI_DEBUG_PRINT(3, ("Flags:    0x%x\n", cinfo->flags));
+			MALI_DEBUG_PRINT(3, ("*****\n"));
+			cinfo  = cinfo->next;
+		}
+	);
+
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+    MALI_ERROR(err);
+}
+
+
+/* Is used by external function:
+	subsystem_terminate<> */
+void mali_core_subsystem_cleanup(mali_core_subsystem* subsys)
+{
+	u32 i;
+	mali_core_renderunit * core;
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+	MALI_DEBUG_PRINT(2, ("Core: subsystem_cleanup: %s\n", subsys->name )) ;
+
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+
+#if USING_MMU
+			if (NULL != core->mmu)
+			{
+				/* the MMU is attached in the load_complete callback, which will never be called if the module fails to load, handle that case */
+				mali_memory_core_mmu_unregister_callback(core->mmu, mali_core_subsystem_callback_schedule_wrapper);
+			}
+#endif
+
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+
+		mali_core_renderunit_irq_handler_remove(core);
+
+		/* When a process terminates, all cores running jobs from that process is reset and put to idle.
+			That means that when the module is unloading (this code) we are guaranteed that all cores are idle.
+			However: if something (we can't think of) is really wrong, a core may give an interrupt during this
+			unloading, and we may now in the code have a bottom-half-processing pending from the interrupts
+			we deregistered above. To be sure that the bottom halves do not access the structures after they
+			are deallocated we flush the bottom-halves processing here, before the deallocation. */
+
+		MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+
+#if USING_MALI_PMM
+			/* Only reset when we are using PMM and the core is not off */
+#if MALI_PMM_NO_PMU
+				/* We need to reset when there is no PMU - but this will
+				 * cause the register read/write functions to report an
+				 * error (hence the if to check for CORE_OFF below) we 
+				 * change state to allow the reset to happen.
+				 */
+				core->state = CORE_IDLE;
+#endif
+			if( core->state != CORE_OFF )
+			{
+				subsys->reset_core( core, MALI_CORE_RESET_STYLE_DISABLE );
+			}
+#else
+			/* Always reset the core */
+			subsys->reset_core( core, MALI_CORE_RESET_STYLE_DISABLE );
+#endif
+
+		mali_core_renderunit_unmap_registers(core);
+
+		_mali_osk_list_delinit(&core->list);
+
+		mali_core_renderunit_term(core);
+
+		subsys->renderunit_delete(core);
+	}
+
+	mali_core_subsystem_cleanup_all_renderunits(subsys);
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+	MALI_DEBUG_PRINT(6, ("SUCCESS: mali_core_subsystem_cleanup: %s\n", subsys->name )) ;
+}
+
+_mali_osk_errcode_t mali_core_subsystem_ioctl_number_of_cores_get(mali_core_session * session, u32 *number_of_cores)
+{
+	mali_core_subsystem * subsystem;
+
+	subsystem = session->subsystem;
+	if ( NULL != number_of_cores )
+	{
+		*number_of_cores = subsystem->number_of_cores;
+
+		MALI_DEBUG_PRINT(4, ("Core: ioctl_number_of_cores_get: %s: %u\n", subsystem->name, *number_of_cores) ) ;
+	}
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_core_subsystem_ioctl_start_job(mali_core_session * session, void *job_data)
+{
+    mali_core_subsystem * subsystem;
+    _mali_osk_errcode_t err;
+
+    /* need the subsystem to run callback function */
+    subsystem = session->subsystem;
+    MALI_CHECK_NON_NULL(subsystem, _MALI_OSK_ERR_FAULT);
+
+    MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsystem);
+    err = subsystem->get_new_job_from_user(session, job_data);
+    MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+
+    MALI_ERROR(err);
+}
+
+
+/* We return the version number to the first core in this subsystem */
+_mali_osk_errcode_t mali_core_subsystem_ioctl_core_version_get(mali_core_session * session, _mali_core_version *version)
+{
+	mali_core_subsystem * subsystem;
+	mali_core_renderunit * core0;
+	u32 nr_return;
+
+	subsystem = session->subsystem;
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsystem);
+
+	core0 = mali_core_renderunit_get_mali_core_nr(subsystem, 0);
+
+	if( NULL == core0 )
+	{
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	nr_return = core0->core_version;
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+
+	MALI_DEBUG_PRINT(4, ("Core: ioctl_core_version_get: %s: %u\n", subsystem->name, nr_return )) ;
+
+	*version = nr_return;
+
+	MALI_SUCCESS;
+}
+
+void mali_core_subsystem_ioctl_abort_job(mali_core_session * session, u32 id)
+{
+	find_and_abort(session, id);
+}
+
+static mali_bool job_should_be_aborted(mali_core_job *job, u32 abort_id)
+{
+	if ( job->abort_id == abort_id ) return MALI_TRUE;
+	else return MALI_FALSE;
+}
+
+static void find_and_abort(mali_core_session* session, u32 abort_id)
+{
+	mali_core_subsystem * subsystem;
+	mali_core_renderunit *core;
+	mali_core_renderunit *tmp;
+	mali_core_job *job;
+
+	subsystem = session->subsystem;
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB( subsystem );
+
+	job = mali_job_queue_abort_job(session, abort_id);
+	if (NULL != job)
+	{
+		MALI_DEBUG_PRINT(3, ("Core: Aborting %s job, with id nr: %u, from the waiting_to_run slot.\n", subsystem->name, abort_id ));
+		if (mali_job_queue_empty(session))
+		{
+			_mali_osk_list_delinit(&(session->awaiting_sessions_list));
+		}
+		subsystem->awaiting_sessions_sum_all_priorities--;
+		subsystem->return_job_to_user(job , JOB_STATUS_END_ABORT);
+	}
+
+	_MALI_OSK_LIST_FOREACHENTRY( core, tmp, &session->renderunits_working_head, mali_core_renderunit, list )
+	{
+		job = core->current_job;
+		if ( (job!=NULL) && (job_should_be_aborted (job, abort_id) ) )
+		{
+			MALI_DEBUG_PRINT(3, ("Core: Aborting %s job, with id nr: %u, which is currently running on mali.\n", subsystem->name, abort_id ));
+			if ( core->state==CORE_IDLE )
+			{
+				MALI_PRINT_ERROR(("Aborting core with running job which is idle. Must be something very wrong."));
+				goto end_bug;
+			}
+			mali_core_renderunit_detach_job_from_core(core, SUBSYSTEM_RESCHEDULE, JOB_STATUS_END_ABORT);
+		}
+	}
+end_bug:
+
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE( subsystem );
+}
+
+
+_mali_osk_errcode_t mali_core_subsystem_ioctl_suspend_response(mali_core_session * session, void *argument)
+{
+    mali_core_subsystem * subsystem;
+    _mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
+
+    /* need the subsystem to run callback function */
+    subsystem = session->subsystem;
+    MALI_CHECK_NON_NULL(subsystem, _MALI_OSK_ERR_FAULT);
+
+    MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsystem);
+	if ( NULL != subsystem->suspend_response)
+	{
+		MALI_DEBUG_PRINT(4, ("MALI_IOC_CORE_CMD_SUSPEND_RESPONSE start\n"));
+		err = subsystem->suspend_response(session, argument);
+		MALI_DEBUG_PRINT(4, ("MALI_IOC_CORE_CMD_SUSPEND_RESPONSE end\n"));
+	}
+
+    MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+
+    return err;
+}
+
+
+/* Is used by internal function:
+	mali_core_subsystem_cleanup<>s */
+/* All cores should be removed before calling this function
+Must hold subsystem_mutex before entering this function */
+static void mali_core_subsystem_cleanup_all_renderunits(mali_core_subsystem* subsys)
+{
+	int i;
+	_mali_osk_free(subsys->mali_core_array);
+	subsys->number_of_cores = 0;
+
+	MALI_DEBUG_PRINT(5, ("Core: subsystem_cleanup_all_renderunits: %s\n", subsys->name) ) ;
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+
+	if ( ! _mali_osk_list_empty(&(subsys->renderunit_idle_head)))
+	{
+		MALI_PRINT_ERROR(("List renderunit_list_idle should be empty."));
+		_MALI_OSK_INIT_LIST_HEAD(&(subsys->renderunit_idle_head)) ;
+	}
+
+	if ( ! _mali_osk_list_empty(&(subsys->renderunit_off_head)))
+	{
+		MALI_PRINT_ERROR(("List renderunit_list_off should be empty."));
+		_MALI_OSK_INIT_LIST_HEAD(&(subsys->renderunit_off_head)) ;
+	}
+
+	for(i=0; i<PRIORITY_LEVELS; ++i)
+	{
+		if ( ! _mali_osk_list_empty(&(subsys->awaiting_sessions_head[i])))
+		{
+			MALI_PRINT_ERROR(("List awaiting_sessions_linkedlist should be empty."));
+			_MALI_OSK_INIT_LIST_HEAD(&(subsys->awaiting_sessions_head[i])) ;
+			subsys->awaiting_sessions_sum_all_priorities = 0;
+		}
+	}
+
+	if ( ! _mali_osk_list_empty(&(subsys->all_sessions_head)))
+	{
+		MALI_PRINT_ERROR(("List all_sessions_linkedlist should be empty."));
+		_MALI_OSK_INIT_LIST_HEAD(&(subsys->all_sessions_head)) ;
+	}
+}
+
+/* Is used by internal functions:
+	mali_core_irq_handler_bottom_half<>;
+	mali_core_subsystem_schedule<>;	*/
+/* Will release the core.*/
+/* Must hold subsystem_mutex before entering this function */
+static void mali_core_subsystem_move_core_set_idle(mali_core_renderunit *core)
+{
+	mali_core_subsystem *subsystem;
+#if USING_MALI_PMM
+	mali_core_status oldstatus;
+#endif
+	subsystem = core->subsystem;
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+	MALI_CHECK_CORE(core);
+	MALI_CHECK_SUBSYSTEM(subsystem);
+
+    _mali_osk_timer_del(core->timer);
+    _mali_osk_timer_del(core->timer_hang_detection);
+
+    MALI_DEBUG_PRINT(5, ("Core: subsystem_move_core_set_idle: %s\n", core->description) ) ;
+
+	core->current_job = NULL ;
+
+#if USING_MALI_PMM
+
+	oldstatus = core->state;
+
+	if ( !core->pend_power_down )
+	{
+		core->state = CORE_IDLE ;
+		_mali_osk_list_move( &core->list, &subsystem->renderunit_idle_head );
+	}
+
+	if( CORE_OFF != oldstatus )
+	{
+		/* Message that this core is now idle or in fact off */
+		_mali_uk_pmm_message_s event = {
+			NULL,
+			MALI_PMM_EVENT_JOB_FINISHED,
+			0 };
+		event.data = core->pmm_id;
+		_mali_ukk_pmm_event_message( &event );
+#if USING_MMU
+		/* Only free the reference when entering idle state from
+		 * anything other than power off
+		 */
+		mali_memory_core_mmu_release_address_space_reference(core->mmu);
+#endif /* USING_MMU */
+	}
+
+	if( core->pend_power_down )
+	{
+		core->state = CORE_OFF ;
+		_mali_osk_list_move( &core->list, &subsystem->renderunit_off_head );
+
+		/* Done the move from the active queues, so the pending power down can be done */
+		core->pend_power_down = MALI_FALSE;
+		malipmm_core_power_down_okay( core->pmm_id );
+	}
+
+#else /* !USING_MALI_PMM */
+
+	core->state = CORE_IDLE ;
+	_mali_osk_list_move( &core->list, &subsystem->renderunit_idle_head );
+
+#if USING_MMU
+		mali_memory_core_mmu_release_address_space_reference(core->mmu);
+#endif
+
+#endif /* USING_MALI_PMM */
+}
+
+/* Must hold subsystem_mutex before entering this function */
+static void mali_core_subsystem_move_set_working(mali_core_renderunit *core, mali_core_job *job)
+{
+	mali_core_subsystem *subsystem;
+	mali_core_session *session;
+	u64 time_now;
+
+	session   = job->session;
+	subsystem = core->subsystem;
+
+	MALI_CHECK_CORE(core);
+	MALI_CHECK_JOB(job);
+	MALI_CHECK_SUBSYSTEM(subsystem);
+
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	MALI_DEBUG_PRINT(5, ("Core: subsystem_move_set_working: %s\n", core->description) ) ;
+
+	time_now = _mali_osk_time_get_ns();
+	job->start_time = time_now;
+#if MALI_GPU_UTILIZATION
+	mali_utilization_core_start(time_now);
+#endif
+
+	core->current_job = job ;
+	core->state = CORE_WORKING ;
+	_mali_osk_list_move( &core->list, &session->renderunits_working_head );
+
+}
+
+#if USING_MALI_PMM
+
+/* Must hold subsystem_mutex before entering this function */
+static void mali_core_subsystem_move_core_set_off(mali_core_renderunit *core)
+{
+	mali_core_subsystem *subsystem;
+	subsystem = core->subsystem;
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+	MALI_CHECK_CORE(core);
+	MALI_CHECK_SUBSYSTEM(subsystem);
+
+	/* Cores must be idle before powering off */
+	MALI_DEBUG_ASSERT(core->state == CORE_IDLE);
+
+	MALI_DEBUG_PRINT(5, ("Core: subsystem_move_core_set_off: %s\n", core->description) ) ;
+
+	core->current_job = NULL ;
+	core->state = CORE_OFF ;
+	_mali_osk_list_move( &core->list, &subsystem->renderunit_off_head );
+}
+
+#endif /* USING_MALI_PMM */
+
+/* Is used by internal function:
+	mali_core_subsystem_schedule<>;	*/
+/* Returns the job with the highest priority for the subsystem. NULL if none*/
+/* Must hold subsystem_mutex before entering this function */
+static mali_core_session * mali_core_subsystem_get_waiting_session(mali_core_subsystem *subsystem)
+{
+	int i;
+
+	MALI_CHECK_SUBSYSTEM(subsystem);
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	if ( 0 == subsystem->awaiting_sessions_sum_all_priorities )
+	{
+		MALI_DEBUG_PRINT(5, ("Core: subsystem_get_waiting_job: No awaiting session found\n"));
+		return NULL;
+	}
+
+	for( i=0; i<PRIORITY_LEVELS ; ++i)
+	{
+		if (!_mali_osk_list_empty(&subsystem->awaiting_sessions_head[i]))
+		{
+			return _MALI_OSK_LIST_ENTRY(subsystem->awaiting_sessions_head[i].next, mali_core_session, awaiting_sessions_list);
+		}
+	}
+
+	return NULL;
+}
+
+static mali_core_job * mali_core_subsystem_release_session_get_job(mali_core_subsystem *subsystem, mali_core_session * session)
+{
+	mali_core_job *job;
+	MALI_CHECK_SUBSYSTEM(subsystem);
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	job = mali_job_queue_get_job(session);
+	subsystem->awaiting_sessions_sum_all_priorities--;
+
+	if(mali_job_queue_empty(session))
+	{
+		/* This is the last job, so remove it from the list */
+		_mali_osk_list_delinit(&session->awaiting_sessions_list);
+	}
+	else
+	{
+		if (0 == (job->flags & MALI_UK_START_JOB_FLAG_MORE_JOBS_FOLLOW))
+		{
+			/* There are more jobs, but the follow flag is not set, so let other sessions run their jobs first */
+			_mali_osk_list_del(&(session->awaiting_sessions_list));
+			_mali_osk_list_addtail(&(session->awaiting_sessions_list), &(subsystem->awaiting_sessions_head[
+			                       session->queue[session->queue_head]->priority]));
+		}
+		/* else; keep on list, follow flag is set and there are more jobs in queue for this session */
+	}
+
+	MALI_CHECK_JOB(job);
+	return job;
+}
+
+/* Is used by internal functions:
+	mali_core_subsystem_schedule<> */
+/* This will start the job on the core. It will also release the core if it did not start.*/
+/* Must hold subsystem_mutex before entering this function */
+static void mali_core_job_start_on_core(mali_core_job *job, mali_core_renderunit *core)
+{
+	mali_core_session *session;
+	mali_core_subsystem *subsystem;
+	_mali_osk_errcode_t err;
+	session   = job->session;
+	subsystem = core->subsystem;
+
+	MALI_CHECK_CORE(core);
+	MALI_CHECK_JOB(job);
+	MALI_CHECK_SUBSYSTEM(subsystem);
+	MALI_CHECK_SESSION(session);
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	MALI_DEBUG_PRINT(4, ("Core: job_start_on_core: job=0x%x, session=0x%x, core=%s\n", job, session, core->description));
+
+	MALI_DEBUG_ASSERT(NULL == core->current_job) ;
+	MALI_DEBUG_ASSERT(CORE_IDLE == core->state );
+
+	mali_core_subsystem_move_set_working(core, job);
+
+#if defined USING_MALI400_L2_CACHE
+	if (0 == (job->flags & MALI_UK_START_JOB_FLAG_NO_FLUSH))
+	{
+		/* Invalidate the L2 cache */
+		if (_MALI_OSK_ERR_OK != mali_kernel_l2_cache_invalidate_all() )
+		{
+			MALI_DEBUG_PRINT(4, ("Core: Clear of L2 failed, return job. System may not be usable for some reason.\n"));
+			mali_core_subsystem_move_core_set_idle(core);
+			subsystem->return_job_to_user(job,JOB_STATUS_END_SYSTEM_UNUSABLE );
+			return;
+		}
+	}
+#endif
+
+	/* Tries to start job on the core. Returns MALI_FALSE if the job could not be started */
+	err = subsystem->start_job(job, core);
+
+	if ( _MALI_OSK_ERR_OK != err )
+	{
+		/* This will happen only if there is something in the job object
+		which make it inpossible to start. Like if it require illegal memory.*/
+		MALI_DEBUG_PRINT(4, ("Core: start_job failed, return job and putting core back into idle list\n"));
+		mali_core_subsystem_move_core_set_idle(core);
+		subsystem->return_job_to_user(job,JOB_STATUS_END_ILLEGAL_JOB );
+	}
+	else
+	{
+		u32 delay = _mali_osk_time_mstoticks(job->watchdog_msecs)+1;
+		job->watchdog_jiffies = _mali_osk_time_tickcount() + delay;
+		if (mali_benchmark)
+		{
+			_mali_osk_timer_add(core->timer, 1);
+		}
+		else
+		{
+			_mali_osk_timer_add(core->timer, delay);
+		}
+	}
+}
+
+#if USING_MMU
+static void mali_core_subsystem_callback_schedule_wrapper(void* sub)
+{
+	mali_core_subsystem * subsystem;
+	subsystem = (mali_core_subsystem *)sub;
+	MALI_DEBUG_PRINT(3, ("MMU: Is schedulling subsystem: %s\n", subsystem->name));
+	mali_core_subsystem_schedule(subsystem);
+}
+#endif
+
+/* Is used by internal function:
+	mali_core_irq_handler_bottom_half
+	mali_core_session_add_job
+*/
+/* Must hold subsystem_mutex before entering this function */
+static void mali_core_subsystem_schedule(mali_core_subsystem * subsystem)
+{
+	mali_core_renderunit *core, *tmp;
+	mali_core_session *session;
+	mali_core_job *job;
+#ifdef MALI_REBOOTNOTIFIER
+	if (_mali_osk_atomic_read(&mali_shutdown_state) > 0) {
+		MALI_DEBUG_PRINT(3, ("Core: mali already under shutdown process!!")) ;
+		return;
+	}
+#endif
+
+	MALI_DEBUG_PRINT(5, ("Core: subsystem_schedule: %s\n", subsystem->name )) ;
+
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	/* First check that there are sessions with jobs waiting to run */
+	if ( 0 == subsystem->awaiting_sessions_sum_all_priorities)
+	{
+		MALI_DEBUG_PRINT(6, ("Core: No jobs available for %s\n", subsystem->name) ) ;
+		return;
+	}
+
+	/* Returns the session with the highest priority job for the subsystem. NULL if none*/
+	session = mali_core_subsystem_get_waiting_session(subsystem);
+
+	if (NULL == session)
+	{
+		MALI_DEBUG_PRINT(6, ("Core: Schedule: No runnable job found\n"));
+		return;
+	}
+
+	_MALI_OSK_LIST_FOREACHENTRY(core, tmp, &subsystem->renderunit_idle_head, mali_core_renderunit, list)
+	{
+#if USING_MMU
+		int err = mali_memory_core_mmu_activate_page_table(core->mmu, session->mmu_session, mali_core_subsystem_callback_schedule_wrapper, subsystem);
+		if (0 == err)
+		{
+			/* core points to a core where the MMU page table activation succeeded */
+#endif
+			/* This will remove the job from queue system */
+			job = mali_core_subsystem_release_session_get_job(subsystem, session);
+			MALI_DEBUG_ASSERT_POINTER(job);
+
+			MALI_DEBUG_PRINT(6, ("Core: Schedule: Got a job 0x%x\n", job));
+
+#if USING_MALI_PMM
+			{
+				/* Message that there is a job scheduled to run 
+				 * NOTE: mali_core_job_start_on_core() can fail to start
+				 * the job for several reasons, but it will move the core
+				 * back to idle which will create the FINISHED message
+				 * so we can still say that the job is SCHEDULED
+				 */
+				_mali_uk_pmm_message_s event = {
+					NULL,
+					MALI_PMM_EVENT_JOB_SCHEDULED,
+					0 };
+				event.data = core->pmm_id;
+				_mali_ukk_pmm_event_message( &event );
+			}
+#endif
+			/* This will {remove core from freelist AND start the job on the core}*/
+			mali_core_job_start_on_core(job, core);
+
+			MALI_DEBUG_PRINT(6, ("Core: Schedule: Job started, done\n"));
+			return;
+#if USING_MMU
+		}
+#endif
+	}
+	MALI_DEBUG_PRINT(6, ("Core: Schedule: Could not activate MMU. Scheduelling postponed to MMU, checking next.\n"));
+
+#if USING_MALI_PMM
+	{
+		/* Message that there are jobs to run */
+		_mali_uk_pmm_message_s event = {
+			NULL,
+			MALI_PMM_EVENT_JOB_QUEUED,
+			0 };
+		if( subsystem->core_type == _MALI_GP2 || subsystem->core_type == _MALI_400_GP )
+		{
+			event.data = MALI_PMM_CORE_GP;
+		}
+		else
+		{
+			/* Check the PP is supported by the PMM */
+			MALI_DEBUG_ASSERT( subsystem->core_type == _MALI_200 || subsystem->core_type == _MALI_400_PP );
+			/* We state that all PP cores are scheduled to inform the PMM
+			 * that it may need to power something up!
+			 */
+			event.data = MALI_PMM_CORE_PP_ALL;
+		}
+		_mali_ukk_pmm_event_message( &event );
+	}
+#endif /* USING_MALI_PMM */
+
+}
+
+/* Is used by external function:
+	session_begin<> */
+void mali_core_session_begin(mali_core_session * session)
+{
+	mali_core_subsystem * subsystem;
+	int i;
+
+	subsystem = session->subsystem;
+	if ( NULL == subsystem )
+	{
+		MALI_PRINT_ERROR(("Missing data in struct\n"));
+		return;
+	}
+	MALI_DEBUG_PRINT(2, ("Core: session_begin: for %s\n", session->subsystem->name )) ;
+
+	session->magic_nr = SESSION_MAGIC_NR;
+
+	_MALI_OSK_INIT_LIST_HEAD(&session->renderunits_working_head);
+
+	for (i = 0; i < MALI_JOB_QUEUE_SIZE; i++)
+	{
+		session->queue[i] = NULL;
+	}
+	session->queue_head = 0;
+	session->queue_tail = 0;
+	_MALI_OSK_INIT_LIST_HEAD(&session->awaiting_sessions_list);
+	_MALI_OSK_INIT_LIST_HEAD(&session->all_sessions_list);
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsystem);
+	_mali_osk_list_add(&session->all_sessions_list, &session->subsystem->all_sessions_head);
+
+#if MALI_STATE_TRACKING
+	_mali_osk_atomic_init(&session->jobs_received, 0);
+	_mali_osk_atomic_init(&session->jobs_returned, 0);
+	session->pid = _mali_osk_get_pid();
+#endif
+
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+
+	MALI_DEBUG_PRINT(5, ("Core: session_begin: for %s DONE\n", session->subsystem->name) ) ;
+}
+
+#if USING_MMU
+static void mali_core_renderunit_stop_bus(mali_core_renderunit* core)
+{
+	core->subsystem->stop_bus(core);
+}
+#endif
+
+void mali_core_session_close(mali_core_session * session)
+{
+	mali_core_subsystem * subsystem;
+	mali_core_renderunit *core;
+
+	subsystem = session->subsystem;
+	MALI_DEBUG_ASSERT_POINTER(subsystem);
+
+	MALI_DEBUG_PRINT(2, ("Core: session_close: for %s\n", session->subsystem->name) ) ;
+
+	/* We must grab subsystem mutex since the list this session belongs to
+	is owned by the subsystem */
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB( subsystem );
+
+	/* Remove this session from the global sessionlist */
+	_mali_osk_list_delinit(&session->all_sessions_list);
+
+	_mali_osk_list_delinit(&(session->awaiting_sessions_list));
+
+	/* Return the potensial waiting job to user */
+	while ( !mali_job_queue_empty(session) )
+	{
+		/* Queue not empty */
+		mali_core_job *job = mali_job_queue_get_job(session);
+		subsystem->return_job_to_user( job, JOB_STATUS_END_SHUTDOWN );
+		subsystem->awaiting_sessions_sum_all_priorities--;
+	}
+
+	/* Kill active cores working for this session - freeing their jobs
+	   Since the handling of one core also could stop jobs from another core, there is a while loop */
+	while ( ! _mali_osk_list_empty(&session->renderunits_working_head) )
+	{
+		core = _MALI_OSK_LIST_ENTRY(session->renderunits_working_head.next, mali_core_renderunit, list);
+		MALI_DEBUG_PRINT(3, ("Core: session_close: Core was working: %s\n", core->description )) ;
+		mali_core_renderunit_detach_job_from_core(core, SUBSYSTEM_RESCHEDULE, JOB_STATUS_END_SHUTDOWN );
+	}
+	_MALI_OSK_INIT_LIST_HEAD(&session->renderunits_working_head); /* Not necessary - we will _mali_osk_free session*/
+
+	MALI_DEBUG_PRINT(5, ("Core: session_close: for %s FINISHED\n", session->subsystem->name )) ;
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE( subsystem );
+}
+
+/* Must hold subsystem_mutex before entering this function */
+_mali_osk_errcode_t mali_core_session_add_job(mali_core_session * session, mali_core_job *job, mali_core_job **job_return)
+{
+	mali_core_subsystem * subsystem;
+
+	job->magic_nr = JOB_MAGIC_NR;
+	MALI_CHECK_SESSION(session);
+
+	subsystem = session->subsystem;
+	MALI_CHECK_SUBSYSTEM(subsystem);
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsystem);
+
+	MALI_DEBUG_PRINT(5, ("Core: session_add_job: for %s\n", subsystem->name )) ;
+
+	/* Setting the default value; No job to return */
+	MALI_DEBUG_ASSERT_POINTER(job_return);
+	*job_return = NULL;
+
+	if (mali_job_queue_empty(session))
+	{
+		/* Add session to the wait list only if it didn't already have a job waiting. */
+		_mali_osk_list_addtail( &(session->awaiting_sessions_list), &(subsystem->awaiting_sessions_head[job->priority]));
+	}
+
+
+	if (_MALI_OSK_ERR_OK != mali_job_queue_add_job(session, job))
+	{
+		if (mali_job_queue_empty(session))
+		{
+			_mali_osk_list_delinit(&(session->awaiting_sessions_list));
+		}
+		MALI_DEBUG_PRINT(4, ("Core: session_add_job: %s queue is full\n", subsystem->name));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Continue to add the new job as the next job from this session */
+	MALI_DEBUG_PRINT(6, ("Core: session_add_job job=0x%x\n", job));
+
+	subsystem->awaiting_sessions_sum_all_priorities++;
+
+	mali_core_subsystem_schedule(subsystem);
+
+	MALI_DEBUG_PRINT(6, ("Core: session_add_job: for %s FINISHED\n", session->subsystem->name )) ;
+
+	MALI_SUCCESS;
+}
+
+static void mali_core_job_set_run_time(mali_core_job * job, u64 end_time)
+{
+	u32 time_used_nano_seconds;
+
+	time_used_nano_seconds = end_time - job->start_time;
+	job->render_time_usecs = time_used_nano_seconds / 1000;
+}
+
+static void mali_core_renderunit_detach_job_from_core(mali_core_renderunit* core, mali_subsystem_reschedule_option reschedule, mali_subsystem_job_end_code end_status)
+{
+	mali_core_job * job;
+	mali_core_subsystem * subsystem;
+	mali_bool already_in_detach_function;
+	u64 time_now;
+
+	MALI_DEBUG_ASSERT(CORE_IDLE != core->state);
+	time_now = _mali_osk_time_get_ns();
+	job = core->current_job;
+	subsystem = core->subsystem;
+
+	/* The reset_core() called some lines below might call this detach
+	 * funtion again. To protect the core object from being modified by 
+	 * recursive calls, the in_detach_function would track if it is an recursive call
+	 */
+	already_in_detach_function = core->in_detach_function;
+	
+
+	if ( MALI_FALSE == already_in_detach_function )
+	{
+		core->in_detach_function = MALI_TRUE;
+		if ( NULL != job )
+		{
+			mali_core_job_set_run_time(job, time_now);
+			core->current_job = NULL;
+		}
+	}
+
+	if (JOB_STATUS_END_SEG_FAULT == end_status)
+	{
+		subsystem->reset_core( core, MALI_CORE_RESET_STYLE_HARD );
+	}
+	else
+	{
+		subsystem->reset_core( core, MALI_CORE_RESET_STYLE_RUNABLE );
+	}
+
+	if ( MALI_FALSE == already_in_detach_function )
+	{
+		if ( CORE_IDLE != core->state )
+		{
+			#if MALI_GPU_UTILIZATION
+			mali_utilization_core_end(time_now);
+			#endif
+			mali_core_subsystem_move_core_set_idle(core);
+		}
+
+		core->in_detach_function = MALI_FALSE;
+
+		if ( SUBSYSTEM_RESCHEDULE == reschedule )
+		{
+			mali_core_subsystem_schedule(subsystem);
+		}
+		if ( NULL != job )
+		{
+			core->subsystem->return_job_to_user(job, end_status);
+		}
+	}
+}
+
+#if USING_MMU
+/* This function intentionally does not release the semaphore. You must run
+   stop_bus_for_all_cores(), reset_all_cores_on_mmu() and continue_job_handling()
+   after calling this function, and then call unlock_subsystem() to release the
+   semaphore. */
+
+static void lock_subsystem(struct mali_core_subsystem * subsys)
+{
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+}
+
+/* You must run lock_subsystem() before entering this function, to ensure that
+   the subsystem mutex is held.
+   Later, unlock_subsystem() can be called to release the mutex.
+
+   This function only stops cores behind the given MMU, unless "mmu" is NULL, in
+   which case all cores are stopped.
+*/
+static void stop_bus_for_all_cores_on_mmu(struct mali_core_subsystem * subsys, void* mmu)
+{
+	u32 i;
+
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+	MALI_DEBUG_PRINT(2,("Handling: bus stop %s\n", subsys->name ));
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		mali_core_renderunit * core;
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+
+		/* We stop only cores behind the given MMU, unless MMU is NULL */
+		if ( (NULL!=mmu) && (core->mmu != mmu) ) continue;
+
+		if ( CORE_IDLE != core->state )
+		{
+			MALI_DEBUG_PRINT(4, ("Stopping bus on core %s\n", core->description));
+			mali_core_renderunit_stop_bus(core);
+			core->error_recovery = MALI_TRUE;
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(4,("Core: not active %s\n", core->description ));
+		}
+	}
+	/* Mutex is still being held, to prevent things to happen while we do cleanup */
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+}
+
+/* You must run lock_subsystem() before entering this function, to ensure that
+   the subsystem mutex is held.
+   Later, unlock_subsystem() can be called to release the mutex.
+
+   This function only resets cores behind the given MMU, unless "mmu" is NULL, in
+   which case all cores are reset.
+*/
+static void reset_all_cores_on_mmu(struct mali_core_subsystem * subsys, void* mmu)
+{
+	u32 i;
+
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+	MALI_DEBUG_PRINT(3, ("Handling: reset cores from mmu: 0x%x on %s\n", mmu, subsys->name ));
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		mali_core_renderunit * core;
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+
+		/* We reset only cores behind the given MMU, unless MMU is NULL */
+		if ( (NULL!=mmu) && (core->mmu != mmu) ) continue;
+
+		if ( CORE_IDLE != core->state )
+		{
+			MALI_DEBUG_PRINT(4, ("Abort and reset core: %s\n", core->description ));
+			mali_core_renderunit_detach_job_from_core(core, SUBSYSTEM_WAIT, JOB_STATUS_END_SEG_FAULT);
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(4, ("Core: not active %s\n", core->description ));
+		}
+	}
+	MALI_DEBUG_PRINT(4, ("Handling: done %s\n", subsys->name ));
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+}
+
+/* You must run lock_subsystem() before entering this function, to ensure that
+   the subsystem mutex is held.
+   Later, unlock_subsystem() can be called to release the mutex. */
+static void continue_job_handling(struct mali_core_subsystem * subsys)
+{
+	u32 i, j;
+
+	MALI_DEBUG_PRINT(3, ("Handling: Continue: %s\n", subsys->name ));
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+
+
+	for(i=0 ; i < subsys->number_of_cores ; ++i)
+	{
+		mali_core_renderunit * core;
+		core = mali_core_renderunit_get_mali_core_nr(subsys,i);
+		core->error_recovery = MALI_FALSE;
+	}
+
+	i = subsys->number_of_cores;
+	j = subsys->awaiting_sessions_sum_all_priorities;
+	
+	/* Schedule MIN(nr_waiting_jobs , number of cores) times */
+	while( i-- && j--)
+	{
+		mali_core_subsystem_schedule(subsys);
+	}
+ 	MALI_DEBUG_PRINT(4, ("Handling: done %s\n", subsys->name ));
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+}
+
+/* Unlock the subsystem. */
+static void unlock_subsystem(struct mali_core_subsystem * subsys)
+{
+	MALI_ASSERT_MUTEX_IS_GRABBED(subsys);
+ 	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+}
+
+void mali_core_subsystem_broadcast_notification(struct mali_core_subsystem * subsys, mali_core_notification_message message, u32 data)
+{
+	void * mmu;
+	mmu = (void*) data;
+
+	switch(message)
+	{
+		case MMU_KILL_STEP0_LOCK_SUBSYSTEM:
+			break;
+		case MMU_KILL_STEP1_STOP_BUS_FOR_ALL_CORES:
+			stop_bus_for_all_cores_on_mmu(subsys, mmu);
+			break;
+		case MMU_KILL_STEP2_RESET_ALL_CORES_AND_ABORT_THEIR_JOBS:
+			reset_all_cores_on_mmu(subsys, mmu );
+			break;
+		case MMU_KILL_STEP3_CONTINUE_JOB_HANDLING:
+			continue_job_handling(subsys);
+			break;
+		case MMU_KILL_STEP4_UNLOCK_SUBSYSTEM:
+			break;
+
+		default:
+			MALI_PRINT_ERROR(("Illegal message: 0x%x, data: 0x%x\n", (u32)message, data));
+			break;
+	}
+}
+#endif /* USING_MMU */
+
+void job_watchdog_set(mali_core_job * job, u32 watchdog_msecs)
+{
+	if (watchdog_msecs == 0) job->watchdog_msecs = mali_max_job_runtime; /* use the default */
+	else if (watchdog_msecs > WATCHDOG_MSECS_MAX) job->watchdog_msecs = WATCHDOG_MSECS_MAX; /* no larger than max */
+	else if (watchdog_msecs < WATCHDOG_MSECS_MIN) job->watchdog_msecs = WATCHDOG_MSECS_MIN; /* not below min */
+	else job->watchdog_msecs = watchdog_msecs;
+}
+
+u32 mali_core_hang_check_timeout_get(void)
+{
+	/* check the value. The user might have set the value outside the allowed range */
+	if (mali_hang_check_interval > HANG_CHECK_MSECS_MAX) mali_hang_check_interval = HANG_CHECK_MSECS_MAX; /* cap to max */
+	else if (mali_hang_check_interval < HANG_CHECK_MSECS_MIN) mali_hang_check_interval = HANG_CHECK_MSECS_MIN; /* cap to min */
+
+	/* return the active value */
+	return mali_hang_check_interval;
+}
+
+static _mali_osk_errcode_t  mali_core_irq_handler_upper_half (void * data)
+{
+	mali_core_renderunit *core;
+	u32 has_pending_irq;
+
+    core  = (mali_core_renderunit * )data;
+
+	if(core && (CORE_OFF == core->state))
+	{
+		MALI_SUCCESS;
+	}
+
+	if ( (NULL == core) ||
+		 (NULL == core->subsystem) ||
+		 (NULL == core->subsystem->irq_handler_upper_half) )
+	{
+		MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}
+	MALI_CHECK_CORE(core);
+	MALI_CHECK_SUBSYSTEM(core->subsystem);
+
+	has_pending_irq = core->subsystem->irq_handler_upper_half(core);
+
+	if ( has_pending_irq )
+	{
+		_mali_osk_irq_schedulework( core->irq ) ;
+		MALI_SUCCESS;
+	}
+
+	if (mali_benchmark) MALI_SUCCESS;
+
+	MALI_ERROR(_MALI_OSK_ERR_FAULT);
+}
+
+static void mali_core_irq_handler_bottom_half ( void *data )
+{
+	mali_core_renderunit *core;
+	mali_core_subsystem* subsystem;
+
+	mali_subsystem_job_end_code job_status;
+
+    core  = (mali_core_renderunit * )data;
+
+	MALI_CHECK_CORE(core);
+	subsystem = core->subsystem;
+	MALI_CHECK_SUBSYSTEM(subsystem);
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB( subsystem );
+	if ( CORE_IDLE == core->state || CORE_OFF == core->state ) goto end_function;
+
+	MALI_DEBUG_PRINT(5, ("IRQ: handling irq from core %s\n", core->description )) ;
+
+	_mali_osk_cache_flushall();
+
+	/* This function must also update the job status flag */
+	job_status = subsystem->irq_handler_bottom_half( core );
+
+	/* Retval is nonzero if the job is finished. */
+	if ( JOB_STATUS_CONTINUE_RUN != job_status )
+	{
+		mali_core_renderunit_detach_job_from_core(core, SUBSYSTEM_RESCHEDULE, job_status);
+	}
+	else
+	{
+		switch ( core->state )
+		{
+			case CORE_WATCHDOG_TIMEOUT:
+				MALI_DEBUG_PRINT(2, ("Watchdog SW Timeout of job from core: %s\n", core->description ));
+				mali_core_renderunit_detach_job_from_core(core, SUBSYSTEM_RESCHEDULE, JOB_STATUS_END_TIMEOUT_SW );
+				break;
+
+			case CORE_POLL:
+				MALI_DEBUG_PRINT(5, ("Poll core: %s\n", core->description )) ;
+				core->state = CORE_WORKING;
+				_mali_osk_timer_add( core->timer, 1);
+				break;
+
+			default:
+				MALI_DEBUG_PRINT(4, ("IRQ: The job on the core continue to run: %s\n", core->description )) ;
+				break;
+		}
+	}
+end_function:
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsystem);
+}
+
+void subsystem_flush_mapped_mem_cache(void)
+{
+	_mali_osk_cache_flushall();
+	_mali_osk_mem_barrier();
+}
+
+#if USING_MALI_PMM
+
+_mali_osk_errcode_t mali_core_subsystem_signal_power_down(mali_core_subsystem *subsys, u32 mali_core_nr, mali_bool immediate_only)
+{
+	mali_core_renderunit * core = NULL;
+
+	MALI_CHECK_SUBSYSTEM(subsys);
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+
+	/* It is possible that this signal funciton can be called during a driver exit, 
+	 * and so the requested core may now be destroyed. (This is due to us not having
+	 * the subsys lock before signalling power down).
+	 * mali_core_renderunit_get_mali_core_nr() will report a Mali ERR because
+	 * the core number is out of range (which is a valid error in other cases). 
+	 * So instead we check here (now that we have the subsys lock) and let the 
+	 * caller cope with the core get failure and check that the core has 
+	 * been unregistered in the PMM as part of its destruction.
+	 */
+	if ( subsys->number_of_cores > mali_core_nr )
+	{
+		core = mali_core_renderunit_get_mali_core_nr(subsys, mali_core_nr);
+	}
+
+	if ( NULL == core )
+	{
+		/* Couldn't find the core */
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+		MALI_DEBUG_PRINT( 1, ("Core: Failed to find core to power down\n") );
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+	else if ( core->state != CORE_IDLE )
+	{
+		/* When powering down we either set a pending power down flag here so we
+		 * can power down cleanly after the job completes or we don't set the 
+		 * flag if we have been asked to only do a power down right now
+		 * In either case, return that the core is busy
+		 */
+		if ( !immediate_only ) core->pend_power_down = MALI_TRUE;
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+		MALI_DEBUG_PRINT( 5, ("Core: No idle core to power down\n") );
+        MALI_ERROR(_MALI_OSK_ERR_BUSY);
+	}
+
+	/* Shouldn't have a pending power down flag set */
+	MALI_DEBUG_ASSERT( !core->pend_power_down );
+
+	/* Move core to off queue */
+	mali_core_subsystem_move_core_set_off(core);
+	
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+
+    MALI_SUCCESS;
+}
+	
+_mali_osk_errcode_t mali_core_subsystem_signal_power_up(mali_core_subsystem *subsys, u32 mali_core_nr, mali_bool queue_only)
+{
+	mali_core_renderunit * core;
+
+	MALI_CHECK_SUBSYSTEM(subsys);
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys);
+
+	core = mali_core_renderunit_get_mali_core_nr(subsys, mali_core_nr);
+
+	if( core == NULL )
+	{
+		/* Couldn't find the core */
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+		MALI_DEBUG_PRINT( 1, ("Core: Failed to find core to power up\n") );
+        MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+	else if( core->state != CORE_OFF )
+	{
+		/* This will usually happen because we are trying to cancel a pending power down */
+		core->pend_power_down = MALI_FALSE;
+		MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+		MALI_DEBUG_PRINT( 1, ("Core: No powered off core to power up (cancelled power down?)\n") );
+        MALI_ERROR(_MALI_OSK_ERR_BUSY);
+	}
+
+	/* Shouldn't have a pending power down set */
+	MALI_DEBUG_ASSERT( !core->pend_power_down );
+
+	/* Move core to idle queue */
+	mali_core_subsystem_move_core_set_idle(core);
+
+	if( !queue_only )
+	{
+		/* Reset MMU & core - core must be idle to allow this */
+#if USING_MMU
+		if ( NULL!=core->mmu )
+		{
+#if defined(USING_MALI200)
+			if (core->pmm_id != MALI_PMM_CORE_PP0)
+			{
+#endif
+				mali_kernel_mmu_reset(core->mmu);
+#if defined(USING_MALI200)
+			}
+#endif
+
+		}
+#endif /* USING_MMU */
+		subsys->reset_core( core, MALI_CORE_RESET_STYLE_RUNABLE );
+	}
+
+	/* Need to schedule work to start on this core */
+	mali_core_subsystem_schedule(subsys);
+	
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys);
+
+    MALI_SUCCESS;
+}
+
+#endif /* USING_MALI_PMM */
+
+#if MALI_STATE_TRACKING
+u32 mali_core_renderunit_dump_state(mali_core_subsystem* subsystem, char *buf, u32 size)
+{
+	u32 i, len = 0;
+	mali_core_renderunit *core;
+	mali_core_renderunit *tmp_core;
+	
+	mali_core_session* session;
+	mali_core_session* tmp_session;
+
+	if (0 >= size)
+	{
+		return 0;
+	}
+
+	MALI_CORE_SUBSYSTEM_MUTEX_GRAB( subsystem );
+
+	len += _mali_osk_snprintf(buf + len, size - len, "Subsystem:\n");
+	len += _mali_osk_snprintf(buf + len, size - len, "  Name: %s\n", subsystem->name);
+
+	for (i = 0; i < subsystem->number_of_cores; i++)
+	{
+		len += _mali_osk_snprintf(buf + len, size - len, "  Core: #%u\n",
+		                          subsystem->mali_core_array[i]->core_number);
+		len += _mali_osk_snprintf(buf + len, size - len, "    Description: %s\n",
+		                          subsystem->mali_core_array[i]->description);
+		switch(subsystem->mali_core_array[i]->state)
+		{
+			case CORE_IDLE:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_IDLE\n");
+				break;
+			case CORE_WORKING:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_WORKING\n");
+					break;
+			case CORE_WATCHDOG_TIMEOUT:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_WATCHDOG_TIMEOUT\n");
+				break;
+			case CORE_POLL:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_POLL\n");
+				break;
+			case CORE_HANG_CHECK_TIMEOUT:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_HANG_CHECK_TIMEOUT\n");
+				break;
+			case CORE_OFF:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: CORE_OFF\n");
+				break;
+			default:
+				len += _mali_osk_snprintf(buf + len, size - len, "    State: Unknown (0x%X)\n",
+				                          subsystem->mali_core_array[i]->state);
+				break;
+		}
+		len += _mali_osk_snprintf(buf + len, size - len, "    Current job: 0x%X\n",
+		                          (u32)(subsystem->mali_core_array[i]->current_job));
+		if (subsystem->mali_core_array[i]->current_job)
+		{
+			u64 time_used_nano_seconds;
+			u32 time_used_micro_seconds;
+			u64 time_now = _mali_osk_time_get_ns();
+
+			time_used_nano_seconds = time_now - subsystem->mali_core_array[i]->current_job->start_time;
+			time_used_micro_seconds = ((u32)(time_used_nano_seconds)) / 1000;
+
+			len += _mali_osk_snprintf(buf + len, size - len, "      Current job session: 0x%X\n",
+			                          subsystem->mali_core_array[i]->current_job->session);
+			len += _mali_osk_snprintf(buf + len, size - len, "      Current job number: %d\n",
+			                          subsystem->mali_core_array[i]->current_job->job_nr);
+			len += _mali_osk_snprintf(buf + len, size - len, "      Current job render_time micro seconds: %d\n",
+			                          time_used_micro_seconds  );
+			len += _mali_osk_snprintf(buf + len, size - len, "      Current job start time micro seconds: %d\n",
+			                          (u32) (subsystem->mali_core_array[i]->current_job->start_time >>10)  );
+		}
+		len += _mali_osk_snprintf(buf + len, size - len, "    Core version: 0x%X\n",
+		                          subsystem->mali_core_array[i]->core_version);
+#if USING_MALI_PMM
+		len += _mali_osk_snprintf(buf + len, size - len, "    PMM id: 0x%X\n",
+		                          subsystem->mali_core_array[i]->pmm_id);
+		len += _mali_osk_snprintf(buf + len, size - len, "    Power down requested: %s\n",
+		                          subsystem->mali_core_array[i]->pend_power_down ? "TRUE" : "FALSE");
+#endif
+	}
+
+	len += _mali_osk_snprintf(buf + len, size - len, "  Cores on idle list:\n");
+	_MALI_OSK_LIST_FOREACHENTRY(core, tmp_core, &subsystem->renderunit_idle_head, mali_core_renderunit, list)
+	{
+		len += _mali_osk_snprintf(buf + len, size - len, "    Core #%u\n", core->core_number);
+	}
+
+	len += _mali_osk_snprintf(buf + len, size - len, "  Cores on off list:\n");
+	_MALI_OSK_LIST_FOREACHENTRY(core, tmp_core, &subsystem->renderunit_off_head, mali_core_renderunit, list)
+	{
+		len += _mali_osk_snprintf(buf + len, size - len, "    Core #%u\n", core->core_number);
+	}
+
+	len += _mali_osk_snprintf(buf + len, size - len, "  Connected sessions:\n");
+	_MALI_OSK_LIST_FOREACHENTRY(session, tmp_session, &subsystem->all_sessions_head, mali_core_session, all_sessions_list)
+	{
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"    Session 0x%X:\n", (u32)session);
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      Queue depth: %u\n", mali_job_queue_size(session));
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      First waiting job: 0x%p\n", session->queue[session->queue_head]);
+		len += _mali_osk_snprintf(buf + len, size - len, "      Notification queue: %s\n",
+				_mali_osk_notification_queue_is_empty(session->notification_queue) ? "EMPTY" : "NON-EMPTY");
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      Jobs received:%4d\n", _mali_osk_atomic_read(&session->jobs_received));
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      Jobs started :%4d\n", _mali_osk_atomic_read(&session->jobs_started));
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      Jobs ended   :%4d\n", _mali_osk_atomic_read(&session->jobs_ended));
+		len += _mali_osk_snprintf(buf + len, size - len,
+				"      Jobs returned:%4d\n", _mali_osk_atomic_read(&session->jobs_returned));
+		len += _mali_osk_snprintf(buf + len, size - len, "      PID:  %d\n", session->pid);
+	}
+
+	len += _mali_osk_snprintf(buf + len, size - len, "  Waiting sessions sum all priorities: %u\n",
+			subsystem->awaiting_sessions_sum_all_priorities);
+	for (i = 0; i < PRIORITY_LEVELS; i++)
+	{
+		len += _mali_osk_snprintf(buf + len, size - len, "    Waiting sessions with priority %u:\n", i);
+		_MALI_OSK_LIST_FOREACHENTRY(session, tmp_session, &subsystem->awaiting_sessions_head[i],
+				mali_core_session, awaiting_sessions_list)
+		{
+			len += _mali_osk_snprintf(buf + len, size - len, "      Session 0x%X:\n", (u32)session);
+			len += _mali_osk_snprintf(buf + len, size - len, "        Waiting job: 0x%X\n",
+					(u32)session->queue[session->queue_head]);
+			len += _mali_osk_snprintf(buf + len, size - len, "        Notification queue: %s\n",
+					_mali_osk_notification_queue_is_empty(session->notification_queue) ? "EMPTY" : "NON-EMPTY");
+		}
+	}
+
+	MALI_CORE_SUBSYSTEM_MUTEX_RELEASE( subsystem );
+	return len;
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.h b/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.h
new file mode 100644
index 0000000..5fbe686
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_rendercore.h
@@ -0,0 +1,565 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_RENDERCORE_H__
+#define __MALI_RENDERCORE_H__
+
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_subsystem.h"
+
+#define PRIORITY_LEVELS 3
+#define PRIORITY_MAX 0
+#define PRIORITY_MIN (PRIORITY_MAX+PRIORITY_LEVELS-1)
+
+/* This file contains what we need in kernel for all core types. */
+
+typedef enum
+{
+	CORE_IDLE,              /**< Core is ready for a new job */
+	CORE_WORKING,           /**< Core is working on a job */
+	CORE_WATCHDOG_TIMEOUT,  /**< Core is working but it has timed out */
+	CORE_POLL,              /**< Poll timer triggered, pending handling */
+	CORE_HANG_CHECK_TIMEOUT,/**< Timeout for hang detection */
+	CORE_OFF                /**< Core is powered off */
+} mali_core_status;
+
+typedef enum
+{
+	SUBSYSTEM_RESCHEDULE,
+	SUBSYSTEM_WAIT
+} mali_subsystem_reschedule_option;
+
+typedef enum
+{
+	MALI_CORE_RESET_STYLE_RUNABLE,
+	MALI_CORE_RESET_STYLE_DISABLE,
+	MALI_CORE_RESET_STYLE_HARD
+} mali_core_reset_style;
+
+typedef enum
+{
+	JOB_STATUS_CONTINUE_RUN			= 0x01,
+	JOB_STATUS_END_SUCCESS			= 1<<(16+0),
+	JOB_STATUS_END_OOM				= 1<<(16+1),
+	JOB_STATUS_END_ABORT			= 1<<(16+2),
+	JOB_STATUS_END_TIMEOUT_SW		= 1<<(16+3),
+	JOB_STATUS_END_HANG				= 1<<(16+4),
+	JOB_STATUS_END_SEG_FAULT		= 1<<(16+5),
+	JOB_STATUS_END_ILLEGAL_JOB		= 1<<(16+6),
+	JOB_STATUS_END_UNKNOWN_ERR		= 1<<(16+7),
+	JOB_STATUS_END_SHUTDOWN			= 1<<(16+8),
+	JOB_STATUS_END_SYSTEM_UNUSABLE	= 1<<(16+9)
+} mali_subsystem_job_end_code;
+
+
+struct mali_core_job;
+struct mali_core_subsystem;
+struct mali_core_renderunit;
+struct mali_core_session;
+
+/* We have one of these subsystems for each core type */
+typedef struct mali_core_subsystem
+{
+	struct mali_core_renderunit ** mali_core_array; /* An array of all cores of this type */
+	u32 number_of_cores; /* Number of cores in this list */
+
+	_mali_core_type core_type;
+
+	u32 magic_nr;
+
+	_mali_osk_list_t renderunit_idle_head; /* Idle cores of this type */
+	_mali_osk_list_t renderunit_off_head;  /* Powered off cores of this type */
+
+	/* Linked list for each priority of sessions with a job ready for scheduelling */
+	_mali_osk_list_t awaiting_sessions_head[PRIORITY_LEVELS];
+	u32 awaiting_sessions_sum_all_priorities;
+
+	/* Linked list of all sessions connected to this coretype */
+	_mali_osk_list_t all_sessions_head;
+
+	/* Linked list of all sessions connected to this coretype */
+    struct _mali_osk_notification_queue_t * notification_queue;
+
+	const char * name;
+	mali_kernel_subsystem_identifier id;
+
+	/**** Functions registered for this core type. Set during mali_core_init ******/
+	/* Start this job on this core. Return MALI_TRUE if the job was started. */
+	_mali_osk_errcode_t (*start_job)(struct mali_core_job * job, struct mali_core_renderunit * core);
+
+	/* Check if given core has an interrupt pending. Return MALI_TRUE and set mask to 0 if pending */
+	u32 (*irq_handler_upper_half)(struct mali_core_renderunit * core);
+
+	/* This function should check if the interrupt indicates that job was finished.
+	If so it should update the job-struct, reset the core registers, and return MALI_TRUE, .
+	If the job is still working after this function it should return MALI_FALSE.
+	The function must also enable the bits in the interrupt mask for the core.
+	Called by the bottom half interrupt function.	*/
+	int (*irq_handler_bottom_half)(struct mali_core_renderunit* core);
+
+	/* This function is called from the ioctl function and should return a mali_core_job pointer
+	to a created mali_core_job object with the data given from userspace */
+	_mali_osk_errcode_t (*get_new_job_from_user)(struct mali_core_session * session, void * argument);
+
+	_mali_osk_errcode_t (*suspend_response)(struct mali_core_session * session, void * argument);
+
+	/* This function is called from the ioctl function and should write the necessary data
+	 to userspace telling which job was finished and the status and debuginfo for this job.
+	 The function must also free and cleanup the input job object. */
+	void (*return_job_to_user)(struct mali_core_job * job, mali_subsystem_job_end_code end_status);
+
+	/* Is called when a subsystem shuts down. This function needs to
+	   release internal pointers in the core struct, and free the
+	   core struct before returning.
+	   It is not allowed to write to any registers, since this
+	   unmapping is already done. */
+	void (*renderunit_delete)(struct mali_core_renderunit * core);
+
+	/* Is called when we want to abort a job that is running on the core.
+	   This is done if program exits while core is running */
+	void (*reset_core)(struct mali_core_renderunit * core, mali_core_reset_style style);
+
+	/* Is called when the rendercore wants the core to give an interrupt */
+	void (*probe_core_irq_trigger)(struct mali_core_renderunit* core);
+
+	/* Is called when the irq probe wants the core to acknowledge an interrupt from the hw */
+	_mali_osk_errcode_t (*probe_core_irq_acknowledge)(struct mali_core_renderunit* core);
+
+	/* Called when the rendercore want to issue a bus stop request to a core */
+	void (*stop_bus)(struct mali_core_renderunit* core);
+} mali_core_subsystem;
+
+
+/* Per core data. This must be embedded into each core type internal core info. */
+typedef struct mali_core_renderunit
+{
+	struct mali_core_subsystem * subsystem; /* The core belongs to this subsystem */
+	_mali_osk_list_t list;                  /* Is always in subsystem->idle_list OR session->renderunits_working */
+	mali_core_status  state;
+	mali_bool error_recovery;               /* Indicates if the core is waiting for external help to recover (typically the MMU) */
+	mali_bool in_detach_function;
+	struct mali_core_job * current_job;     /* Current job being processed on this core ||NULL */
+	u32 magic_nr;
+ 	_mali_osk_timer_t * timer;
+	_mali_osk_timer_t * timer_hang_detection;
+
+	mali_io_address registers_mapped;       /* IO-mapped pointer to registers */
+	u32   registers_base_addr;              /* Base addres of the registers */
+	u32 size;                               /* The size of registers_mapped */
+	const char * description;               /* Description of this core. */
+	u32 irq_nr;                             /* The IRQ nr for this core */
+	u32 core_version;
+#if USING_MMU
+	u32 mmu_id;
+	void * mmu;                             /* The MMU this rendercore is behind.*/
+#endif
+#if USING_MALI_PMM
+	mali_pmm_core_id pmm_id;                /* The PMM core id */
+	mali_bool pend_power_down;              /* Power down is requested */
+#endif
+
+	u32 core_number;                        /* 0 for first detected core of this type, 1 for second and so on */
+
+    _mali_osk_irq_t *irq;
+} mali_core_renderunit;
+
+
+#define MALI_JOB_QUEUE_SIZE 8
+/* Per open FILE data. */
+/* You must held subsystem->mutex before any transactions to this datatype. */
+typedef struct mali_core_session
+{
+	struct mali_core_subsystem * subsystem;	   /* The session belongs to this subsystem */
+	_mali_osk_list_t renderunits_working_head; /* List of renderunits working for this session */
+	struct mali_core_job *queue[MALI_JOB_QUEUE_SIZE];  /* The next job from this session to run */
+	int queue_head;
+	int queue_tail;
+	int queue_size;
+
+	_mali_osk_list_t awaiting_sessions_list; /* Linked list of sessions with jobs, for each priority */
+	_mali_osk_list_t all_sessions_list;      /* Linked list of all sessions on the system. */
+
+    _mali_osk_notification_queue_t * notification_queue; /* Messages back to Base in userspace*/
+#if USING_MMU
+	struct mali_session_data * mmu_session; /* The session associated with the MMU page tables for this core */
+#endif
+	u32 magic_nr;
+#if MALI_STATE_TRACKING
+	_mali_osk_atomic_t jobs_received;
+	_mali_osk_atomic_t jobs_started;
+	_mali_osk_atomic_t jobs_ended;
+	_mali_osk_atomic_t jobs_returned;
+	u32 pid;
+#endif
+} mali_core_session;
+
+/* This must be embedded into a specific mali_core_job struct */
+/* use this macro to get spesific mali_core_job:  container_of(ptr, type, member)*/
+typedef struct mali_core_job
+{
+	_mali_osk_list_t list; /* Linked list of jobs. Used by struct mali_core_session */
+	struct mali_core_session *session;
+	u32 magic_nr;
+	u32 priority;
+	u32 watchdog_msecs;
+	u32 render_time_usecs ;
+	u64 start_time;
+	unsigned long watchdog_jiffies;
+	u32 abort_id;
+	u32 job_nr;
+	_mali_uk_start_job_flags flags;
+} mali_core_job;
+
+MALI_STATIC_INLINE mali_bool mali_job_queue_empty(mali_core_session *session)
+{
+	if (0 == session->queue_size)
+	{
+		return MALI_TRUE;
+	}
+	return MALI_FALSE;
+}
+
+MALI_STATIC_INLINE mali_bool mali_job_queue_full(mali_core_session *session)
+{
+	if (MALI_JOB_QUEUE_SIZE == session->queue_size)
+	{
+		return MALI_TRUE;
+	}
+	return MALI_FALSE;
+}
+
+
+MALI_STATIC_INLINE _mali_osk_errcode_t mali_job_queue_add_job(mali_core_session *session, struct mali_core_job *job)
+{
+	if (mali_job_queue_full(session))
+	{
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	session->queue[session->queue_tail] = job;
+	session->queue_tail = (session->queue_tail + 1) % MALI_JOB_QUEUE_SIZE;
+	session->queue_size++;
+
+	MALI_SUCCESS;
+}
+
+MALI_STATIC_INLINE struct mali_core_job *mali_job_queue_get_job(mali_core_session *session)
+{
+	struct mali_core_job *job;
+	MALI_DEBUG_ASSERT(!mali_job_queue_empty(session));
+
+	job = session->queue[session->queue_head];
+
+	MALI_DEBUG_ASSERT_POINTER(job);
+
+	session->queue[session->queue_head] = NULL;
+	session->queue_head = (session->queue_head + 1) % MALI_JOB_QUEUE_SIZE;
+	session->queue_size--;
+
+	return job;
+}
+
+MALI_STATIC_INLINE u32 mali_job_queue_size(mali_core_session *session)
+{
+	return (u32)(session->queue_size);
+}
+
+MALI_STATIC_INLINE struct mali_core_job *mali_job_queue_abort_job(mali_core_session *session, u32 abort_id)
+{
+	int i;
+	int n;
+	struct mali_core_job *job = NULL;
+
+	for (i = session->queue_head, n = session->queue_size; n > 0; n--, i = (i+1)%MALI_JOB_QUEUE_SIZE)
+	{
+		if (session->queue[i]->abort_id == abort_id)
+		{
+			/* Remove job from queue */
+			job = session->queue[i];
+			session->queue[i] = NULL;
+
+			session->queue_size -= 1;
+			n--;
+			break;
+		}
+	}
+	if (NULL == job)
+	{
+		return NULL;
+	}
+
+	/* Rearrange queue */
+	while (n > 0)
+	{
+		int next = (i + 1) % MALI_JOB_QUEUE_SIZE;
+		session->queue[i] = session->queue[next];
+		i = next;
+		n--;
+	}
+	session->queue_tail = i;
+
+	return job;
+}
+
+
+/*
+ * The rendercode subsystem is included in the subsystems[] array.
+ */
+extern struct mali_kernel_subsystem mali_subsystem_rendercore;
+
+void subsystem_flush_mapped_mem_cache(void);
+
+
+#define SUBSYSTEM_MAGIC_NR 	0xdeadbeef
+#define CORE_MAGIC_NR 		0xcafebabe
+#define SESSION_MAGIC_NR 	0xbabe1234
+#define JOB_MAGIC_NR 		0x0123abcd
+
+
+#define MALI_CHECK_SUBSYSTEM(subsystem)\
+	do { \
+		if ( SUBSYSTEM_MAGIC_NR != subsystem->magic_nr) MALI_PRINT_ERROR(("Wrong magic number"));\
+	} while (0)
+
+#define MALI_CHECK_CORE(CORE)\
+	do { \
+		if ( CORE_MAGIC_NR != CORE->magic_nr) MALI_PRINT_ERROR(("Wrong magic number"));\
+} while (0)
+
+#define MALI_CHECK_SESSION(SESSION)\
+	do { \
+		if ( SESSION_MAGIC_NR != SESSION->magic_nr) MALI_PRINT_ERROR(("Wrong magic number"));\
+} while (0)
+
+#define MALI_CHECK_JOB(JOB)\
+	do { \
+		if ( JOB_MAGIC_NR != JOB->magic_nr) MALI_PRINT_ERROR(("Wrong magic number"));\
+} while (0)
+
+
+/* Check if job_a has higher priority than job_b */
+MALI_STATIC_INLINE int job_has_higher_priority(mali_core_job * job_a, mali_core_job * job_b)
+{
+	/* The lowest number has the highest priority */
+	return (int) (job_a->priority < job_b->priority);
+}
+
+MALI_STATIC_INLINE void job_priority_set(mali_core_job * job, u32 priority)
+{
+	if (priority > PRIORITY_MIN) job->priority = PRIORITY_MIN;
+	else job->priority = priority;
+}
+
+void job_watchdog_set(mali_core_job * job, u32 watchdog_msecs);
+
+/* For use by const default register settings (e.g. set these after reset) */
+typedef struct register_address_and_value
+{
+	u32 address;
+	u32 value;
+} register_address_and_value ;
+
+
+/* For use by dynamic default register settings (e.g. set these after reset) */
+typedef struct register_address_and_value_list
+{
+	_mali_osk_list_t list;
+	register_address_and_value item;
+} register_address_and_value_list ;
+
+/* Used if the user wants to set a continious block of registers */
+typedef struct register_array_user
+{
+	u32 entries_in_array;
+	u32 start_address;
+	void __user * reg_array;
+}register_array_user;
+
+
+#define MALI_CORE_SUBSYSTEM_MUTEX_GRAB(subsys) \
+	do { \
+		MALI_DEBUG_PRINT(5, ("MUTEX: GRAB %s() %d on %s\n",__FUNCTION__, __LINE__, subsys->name)); \
+		_mali_osk_lock_wait( rendercores_global_mutex, _MALI_OSK_LOCKMODE_RW); \
+		MALI_DEBUG_PRINT(5, ("MUTEX: GRABBED %s() %d on %s\n",__FUNCTION__, __LINE__, subsys->name)); \
+		if ( SUBSYSTEM_MAGIC_NR != subsys->magic_nr ) MALI_PRINT_ERROR(("Wrong magic number"));\
+		rendercores_global_mutex_is_held = 1; \
+		rendercores_global_mutex_owner = _mali_osk_get_tid();  \
+	} while (0) ;
+
+#define MALI_CORE_SUBSYSTEM_MUTEX_RELEASE(subsys) \
+	do { \
+		MALI_DEBUG_PRINT(5, ("MUTEX: RELEASE %s() %d on %s\n",__FUNCTION__, __LINE__, subsys->name)); \
+		rendercores_global_mutex_is_held = 0; \
+		 rendercores_global_mutex_owner = 0; \
+		if ( SUBSYSTEM_MAGIC_NR != subsys->magic_nr ) MALI_PRINT_ERROR(("Wrong magic number"));\
+		_mali_osk_lock_signal( rendercores_global_mutex, _MALI_OSK_LOCKMODE_RW); \
+		MALI_DEBUG_PRINT(5, ("MUTEX: RELEASED %s() %d on %s\n",__FUNCTION__, __LINE__, subsys->name)); \
+		if ( SUBSYSTEM_MAGIC_NR != subsys->magic_nr ) MALI_PRINT_ERROR(("Wrong magic number"));\
+	} while (0) ;
+
+
+#define MALI_ASSERT_MUTEX_IS_GRABBED(input_pointer)\
+	do { \
+		if ( 0 == rendercores_global_mutex_is_held ) MALI_PRINT_ERROR(("ASSERT MUTEX SHOULD BE GRABBED"));\
+		if ( SUBSYSTEM_MAGIC_NR != input_pointer->magic_nr ) MALI_PRINT_ERROR(("Wrong magic number"));\
+		if ( rendercores_global_mutex_owner != _mali_osk_get_tid() ) MALI_PRINT_ERROR(("Owner mismatch"));\
+	} while (0)
+
+MALI_STATIC_INLINE _mali_osk_errcode_t mali_core_renderunit_register_rw_check(mali_core_renderunit *core,
+                                                                                 u32 relative_address)
+{
+#if USING_MALI_PMM
+	if( core->state == CORE_OFF )
+	{
+		MALI_PRINT_ERROR(("Core is OFF during access: Core: %s Addr: 0x%04X\n",
+			core->description,relative_address));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+#endif
+
+	MALI_DEBUG_ASSERT((relative_address & 0x03) == 0);
+
+	if (mali_benchmark) MALI_ERROR(_MALI_OSK_ERR_FAULT);
+
+	MALI_DEBUG_CODE(if (relative_address >= core->size)
+	{
+		MALI_PRINT_ERROR(("Trying to access illegal register: 0x%04x in core: %s",
+			relative_address, core->description));
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	})
+
+	MALI_SUCCESS;
+}
+
+
+MALI_STATIC_INLINE u32 mali_core_renderunit_register_read(struct mali_core_renderunit *core, u32 relative_address)
+{
+	u32 read_val;
+
+	if(_MALI_OSK_ERR_FAULT == mali_core_renderunit_register_rw_check(core, relative_address))
+		return 0xDEADBEEF;
+
+	read_val = _mali_osk_mem_ioread32(core->registers_mapped, relative_address);
+
+	MALI_DEBUG_PRINT(6, ("Core: renderunit_register_read: Core:%s Addr:0x%04X Val:0x%08x\n",
+	        core->description,relative_address, read_val));
+
+	return read_val;
+}
+
+MALI_STATIC_INLINE void mali_core_renderunit_register_read_array(struct mali_core_renderunit *core,
+                                                                 u32 relative_address,
+                                                                 u32 * result_array,
+                                                                 u32 nr_of_regs)
+{
+	/* NOTE Do not use burst reads against the registers */
+	u32 i;
+
+	MALI_DEBUG_PRINT(6, ("Core: renderunit_register_read_array: Core:%s Addr:0x%04X Nr_regs: %u\n",
+	        core->description,relative_address, nr_of_regs));
+
+	for(i=0; i<nr_of_regs; ++i)
+	{
+		result_array[i] = mali_core_renderunit_register_read(core, relative_address + i*4);
+	}
+}
+
+/*
+ * Write to a core register, and bypass implied memory barriers.
+ *
+ * On some systems, _mali_osk_mem_iowrite32() implies a memory barrier. This
+ * can be a performance problem when doing many writes in sequence.
+ *
+ * When using this function, ensure proper barriers are put in palce. Most
+ * likely a _mali_osk_mem_barrier() is needed after all related writes are
+ * completed.
+ *
+ */
+MALI_STATIC_INLINE void mali_core_renderunit_register_write_relaxed(mali_core_renderunit *core,
+                                                                u32 relative_address,
+                                                                u32 new_val)
+{
+	if(_MALI_OSK_ERR_FAULT == mali_core_renderunit_register_rw_check(core, relative_address))
+		return;
+
+	MALI_DEBUG_PRINT(6, ("mali_core_renderunit_register_write_relaxed: Core:%s Addr:0x%04X Val:0x%08x\n",
+		core->description,relative_address, new_val));
+
+	_mali_osk_mem_iowrite32_relaxed(core->registers_mapped, relative_address, new_val);
+}
+
+MALI_STATIC_INLINE void mali_core_renderunit_register_write(struct mali_core_renderunit *core,
+                                                            u32 relative_address,
+                                                            u32 new_val)
+{
+	MALI_DEBUG_PRINT(6, ("mali_core_renderunit_register_write: Core:%s Addr:0x%04X Val:0x%08x\n",
+            core->description,relative_address, new_val));
+
+	if(_MALI_OSK_ERR_FAULT == mali_core_renderunit_register_rw_check(core, relative_address))
+		return;
+
+	_mali_osk_mem_iowrite32(core->registers_mapped, relative_address, new_val);
+}
+
+MALI_STATIC_INLINE void mali_core_renderunit_register_write_array(struct mali_core_renderunit *core,
+                                                                  u32 relative_address,
+                                                                  u32 * write_array,
+                                                                  u32 nr_of_regs)
+{
+	u32 i;
+	MALI_DEBUG_PRINT(6, ("Core: renderunit_register_write_array: Core:%s Addr:0x%04X Nr_regs: %u\n",
+	        core->description,relative_address, nr_of_regs));
+
+	/* Do not use burst writes against the registers */
+	for( i = 0; i< nr_of_regs; i++)
+	{
+		mali_core_renderunit_register_write_relaxed(core, relative_address + i*4, write_array[i]);
+	}
+}
+
+_mali_osk_errcode_t  mali_core_renderunit_init(struct mali_core_renderunit * core);
+void  mali_core_renderunit_term(struct mali_core_renderunit * core);
+int   mali_core_renderunit_map_registers(struct mali_core_renderunit *core);
+void  mali_core_renderunit_unmap_registers(struct mali_core_renderunit *core);
+int   mali_core_renderunit_irq_handler_add(struct mali_core_renderunit *core);
+mali_core_renderunit * mali_core_renderunit_get_mali_core_nr(mali_core_subsystem *subsys, u32 mali_core_nr);
+
+int mali_core_subsystem_init(struct mali_core_subsystem * new_subsys);
+#if USING_MMU
+void mali_core_subsystem_attach_mmu(mali_core_subsystem* subsys);
+#endif
+int mali_core_subsystem_register_renderunit(struct mali_core_subsystem * subsys, struct mali_core_renderunit * core);
+int mali_core_subsystem_system_info_fill(mali_core_subsystem* subsys, _mali_system_info* info);
+void mali_core_subsystem_cleanup(struct mali_core_subsystem * subsys);
+#if USING_MMU
+void mali_core_subsystem_broadcast_notification(struct mali_core_subsystem * subsys, mali_core_notification_message message, u32 data);
+#endif
+void mali_core_session_begin(mali_core_session *session);
+void mali_core_session_close(mali_core_session * session);
+int mali_core_session_add_job(mali_core_session * session, mali_core_job *job, mali_core_job **job_return);
+u32 mali_core_hang_check_timeout_get(void);
+
+_mali_osk_errcode_t mali_core_subsystem_ioctl_start_job(mali_core_session * session, void *job_data);
+_mali_osk_errcode_t mali_core_subsystem_ioctl_number_of_cores_get(mali_core_session * session, u32 *number_of_cores);
+_mali_osk_errcode_t mali_core_subsystem_ioctl_core_version_get(mali_core_session * session, _mali_core_version *version);
+_mali_osk_errcode_t mali_core_subsystem_ioctl_suspend_response(mali_core_session * session, void* argument);
+void mali_core_subsystem_ioctl_abort_job(mali_core_session * session, u32 id);
+
+#if USING_MALI_PMM
+_mali_osk_errcode_t mali_core_subsystem_signal_power_down(mali_core_subsystem *subsys, u32 mali_core_nr, mali_bool immediate_only);
+_mali_osk_errcode_t mali_core_subsystem_signal_power_up(mali_core_subsystem *subsys, u32 mali_core_nr, mali_bool queue_only);
+#endif
+
+#if MALI_STATE_TRACKING
+u32 mali_core_renderunit_dump_state(mali_core_subsystem* subsystem, char *buf, u32 size);
+#endif
+
+#endif /* __MALI_RENDERCORE_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_session_manager.h b/drivers/media/video/samsung/mali/common/mali_kernel_session_manager.h
new file mode 100644
index 0000000..8cc41d7
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_session_manager.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_SESSION_MANAGER_H__
+#define __MALI_KERNEL_SESSION_MANAGER_H__
+
+/* Incomplete struct to pass around pointers to it */
+struct mali_session_data;
+
+void * mali_kernel_session_manager_slot_get(struct mali_session_data * session, int id);
+
+#endif /* __MALI_KERNEL_SESSION_MANAGER_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_subsystem.h b/drivers/media/video/samsung/mali/common/mali_kernel_subsystem.h
new file mode 100644
index 0000000..8f05216
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_subsystem.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_kernel_subsystem.h
+ */
+
+#ifndef __MALI_KERNEL_SUBSYSTEM_H__
+#define __MALI_KERNEL_SUBSYSTEM_H__
+
+#include "mali_osk.h"
+#include "mali_uk_types.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+
+/* typedefs of the datatypes used in the hook functions */
+typedef void * mali_kernel_subsystem_session_slot;
+typedef int mali_kernel_subsystem_identifier;
+typedef _mali_osk_errcode_t (*mali_kernel_resource_registrator)(_mali_osk_resource_t *);
+
+/**
+ * Broadcast notification messages
+ */
+typedef enum mali_core_notification_message
+{
+	MMU_KILL_STEP0_LOCK_SUBSYSTEM,                        /**< Request to lock subsystem */
+	MMU_KILL_STEP1_STOP_BUS_FOR_ALL_CORES,                /**< Request to stop all buses */
+	MMU_KILL_STEP2_RESET_ALL_CORES_AND_ABORT_THEIR_JOBS,  /**< Request kill all jobs, and not start more jobs */
+	MMU_KILL_STEP3_CONTINUE_JOB_HANDLING,                 /**< Request to continue with new jobs on all cores */
+	MMU_KILL_STEP4_UNLOCK_SUBSYSTEM                       /**< Request to unlock subsystem */
+} mali_core_notification_message;
+
+/**
+ * A function pointer can be NULL if the subsystem isn't interested in the event.
+ */
+typedef struct mali_kernel_subsystem
+{
+	/* subsystem control */
+	_mali_osk_errcode_t (*startup)(mali_kernel_subsystem_identifier id); /**< Called during module load or system startup*/
+	void (*shutdown)(mali_kernel_subsystem_identifier id); /**< Called during module unload or system shutdown */
+
+	/**
+	 * Called during module load or system startup.
+	 * Called when all subsystems have reported startup OK and all resources where successfully initialized
+	*/
+	_mali_osk_errcode_t (*load_complete)(mali_kernel_subsystem_identifier id);
+
+	/* per subsystem handlers */
+	_mali_osk_errcode_t (*system_info_fill)(_mali_system_info* info); /**< Fill info into info struct. MUST allocate memory with kmalloc, since it's kfree'd */
+
+	/* per session handlers */
+	/**
+	 * Informs about a new session.
+	 * slot can be used to track per-session per-subsystem data.
+	 * queue can be used to send events to user space.
+	 * _mali_osk_errcode_t error return value.
+	 */
+	_mali_osk_errcode_t (*session_begin)(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot, _mali_osk_notification_queue_t * queue);
+	/**
+	 * Informs that a session is ending
+	 * slot was the same as given during session_begin
+	 */
+	void (*session_end)(struct mali_session_data * mali_session_data, mali_kernel_subsystem_session_slot * slot);
+
+	/* Used by subsystems to send messages to each other. This is the receiving end */
+	void (*broadcast_notification)(mali_core_notification_message message, u32 data);
+
+#if MALI_STATE_TRACKING
+	/** Dump the current state of the subsystem */
+	u32 (*dump_state)(char *buf, u32 size);
+#endif
+} mali_kernel_subsystem;
+
+/* functions used by the subsystems to interact with the core */
+/**
+ * Register a resouce handler
+ * @param type The resoruce type to register a handler for
+ * @param handler Pointer to the function handling this resource
+ * @return _MALI_OSK_ERR_OK on success. Otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t _mali_kernel_core_register_resource_handler(_mali_osk_resource_type_t type, mali_kernel_resource_registrator handler);
+
+/* function used to interact with other subsystems */
+/**
+ * Broadcast a message
+ * Sends a message to all subsystems which have registered a broadcast notification handler
+ * @param message The message to send
+ * @param data Message specific extra data
+ */
+void _mali_kernel_core_broadcast_subsystem_message(mali_core_notification_message message, u32 data);
+
+#if MALI_STATE_TRACKING
+/**
+ * Tell all subsystems to dump their current state
+ */
+u32 _mali_kernel_core_dump_state(char *buf, u32 size);
+#endif
+
+
+#endif /* __MALI_KERNEL_SUBSYSTEM_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_utilization.c b/drivers/media/video/samsung/mali/common/mali_kernel_utilization.c
new file mode 100644
index 0000000..b43b872
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_utilization.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_utilization.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+
+/* Define how often to calculate and report GPU utilization, in milliseconds */
+#define MALI_GPU_UTILIZATION_TIMEOUT 1000
+
+static _mali_osk_lock_t *time_data_lock;
+
+static _mali_osk_atomic_t num_running_cores;
+
+static u64 period_start_time = 0;
+static u64 work_start_time = 0;
+static u64 accumulated_work_time = 0;
+
+static _mali_osk_timer_t *utilization_timer = NULL;
+static mali_bool timer_running = MALI_FALSE;
+
+
+static void calculate_gpu_utilization(void *arg)
+{
+	u64 time_now;
+	u64 time_period;
+	u32 leading_zeroes;
+	u32 shift_val;
+	u32 work_normalized;
+	u32 period_normalized;
+	u32 utilization;
+
+	_mali_osk_lock_wait(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (accumulated_work_time == 0 && work_start_time == 0)	{
+		/* Don't reschedule timer, this will be started if new work arrives */
+		timer_running = MALI_FALSE;
+
+		_mali_osk_lock_signal(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+		/* No work done for this period, report zero usage */
+		mali_gpu_utilization_handler(0);
+
+		return;
+	}
+
+	time_now = _mali_osk_time_get_ns();
+	time_period = time_now - period_start_time;
+
+	/* If we are currently busy, update working period up to now */
+	if (work_start_time != 0) {
+		accumulated_work_time += (time_now - work_start_time);
+		work_start_time = time_now;
+	}
+
+	/*
+	 * We have two 64-bit values, a dividend and a divisor.
+	 * To avoid dependencies to a 64-bit divider, we shift down the two values
+	 * equally first.
+	 * We shift the dividend up and possibly the divisor down, making the result X in 256.
+	 */
+
+	/* Shift the 64-bit values down so they fit inside a 32-bit integer */
+	leading_zeroes = _mali_osk_clz((u32)(time_period >> 32));
+	shift_val = 32 - leading_zeroes;
+	work_normalized = (u32)(accumulated_work_time >> shift_val);
+	period_normalized = (u32)(time_period >> shift_val);
+
+	/*
+	 * Now, we should report the usage in parts of 256
+	 * this means we must shift up the dividend or down the divisor by 8
+	 * (we could do a combination, but we just use one for simplicity,
+	 * but the end result should be good enough anyway)
+	 */
+	if (period_normalized > 0x00FFFFFF)	{
+		/* The divisor is so big that it is safe to shift it down */
+		period_normalized >>= 8;
+	} else {
+		/*
+		 * The divisor is so small that we can shift up the dividend, without loosing any data.
+		 * (dividend is always smaller than the divisor)
+		 */
+		work_normalized <<= 8;
+	}
+
+	utilization = work_normalized / period_normalized;
+
+	accumulated_work_time = 0;
+	period_start_time = time_now; /* starting a new period */
+
+	_mali_osk_lock_signal(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+	_mali_osk_timer_add(utilization_timer, _mali_osk_time_mstoticks(MALI_GPU_UTILIZATION_TIMEOUT));
+
+	mali_gpu_utilization_handler(utilization);
+}
+
+
+
+_mali_osk_errcode_t mali_utilization_init(void)
+{
+	time_data_lock = _mali_osk_lock_init( _MALI_OSK_LOCKFLAG_SPINLOCK_IRQ|_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 0 );
+	if (NULL == time_data_lock)
+		return _MALI_OSK_ERR_FAULT;
+
+
+	_mali_osk_atomic_init(&num_running_cores, 0);
+
+	utilization_timer = _mali_osk_timer_init();
+	if (NULL == utilization_timer) {
+		_mali_osk_lock_term(time_data_lock);
+		return _MALI_OSK_ERR_FAULT;
+	}
+	_mali_osk_timer_setcallback(utilization_timer, calculate_gpu_utilization, NULL);
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void mali_utilization_suspend(void)
+{
+	if (NULL != utilization_timer) {
+		_mali_osk_timer_del(utilization_timer);
+		timer_running = MALI_FALSE;
+	}
+}
+
+void mali_utilization_term(void)
+{
+	if (NULL != utilization_timer) {
+		_mali_osk_timer_del(utilization_timer);
+		timer_running = MALI_FALSE;
+		_mali_osk_timer_term(utilization_timer);
+		utilization_timer = NULL;
+	}
+
+	_mali_osk_atomic_term(&num_running_cores);
+
+	_mali_osk_lock_term(time_data_lock);
+}
+
+
+
+void mali_utilization_core_start(u64 time_now)
+{
+	if (_mali_osk_atomic_inc_return(&num_running_cores) == 1) {
+		/*
+		 * We went from zero cores working, to one core working,
+		 * we now consider the entire GPU for being busy
+		 */
+
+		_mali_osk_lock_wait(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+		if (time_now < period_start_time)
+		{
+			/*
+			 * This might happen if the calculate_gpu_utilization() was able
+			 * to run between the sampling of time_now and us grabbing the lock above
+			 */
+			time_now = period_start_time;
+		}
+
+		work_start_time = time_now;
+
+		if (timer_running != MALI_TRUE) {
+			timer_running = MALI_TRUE;
+			period_start_time = work_start_time; /* starting a new period */
+
+			_mali_osk_lock_signal(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+			_mali_osk_timer_del(utilization_timer);
+
+			_mali_osk_timer_add(utilization_timer, _mali_osk_time_mstoticks(MALI_GPU_UTILIZATION_TIMEOUT));
+		} else {
+			_mali_osk_lock_signal(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+		}
+	}
+}
+
+
+
+void mali_utilization_core_end(u64 time_now)
+{
+	if (_mali_osk_atomic_dec_return(&num_running_cores) == 0) {
+		/*
+		 * No more cores are working, so accumulate the time we was busy.
+		 */
+		_mali_osk_lock_wait(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+
+		if (time_now < work_start_time)
+		{
+			/*
+			 * This might happen if the calculate_gpu_utilization() was able
+			 * to run between the sampling of time_now and us grabbing the lock above
+			 */
+			time_now = work_start_time;
+		}
+
+		accumulated_work_time += (time_now - work_start_time);
+		work_start_time = 0;
+
+		_mali_osk_lock_signal(time_data_lock, _MALI_OSK_LOCKMODE_RW);
+	}
+}
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_utilization.h b/drivers/media/video/samsung/mali/common/mali_kernel_utilization.h
new file mode 100644
index 0000000..c779978
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_utilization.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_UTILIZATION_H__
+#define __MALI_KERNEL_UTILIZATION_H__
+
+#include "mali_osk.h"
+
+/**
+ * Initialize/start the Mali GPU utilization metrics reporting.
+ *
+ * @return _MALI_OSK_ERR_OK on success, otherwise failure.
+ */
+_mali_osk_errcode_t mali_utilization_init(void);
+
+/**
+ * Terminate the Mali GPU utilization metrics reporting
+ */
+void mali_utilization_term(void);
+
+/**
+ * Should be called when a job is about to execute a job
+ */
+void mali_utilization_core_start(u64 time_now);
+
+/**
+ * Should be called to stop the utilization timer during system suspend
+ */
+void mali_utilization_suspend(void);
+
+/**
+ * Should be called when a job has completed executing a job
+ */
+void mali_utilization_core_end(u64 time_now);
+
+
+#endif /* __MALI_KERNEL_UTILIZATION_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_kernel_vsync.c b/drivers/media/video/samsung/mali/common/mali_kernel_vsync.c
new file mode 100644
index 0000000..dc39e01
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_kernel_vsync.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_osk_mali.h"
+#include "mali_ukk.h"
+/*#include "mali_timestamp.h"*/
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+
+_mali_osk_errcode_t _mali_ukk_vsync_event_report(_mali_uk_vsync_event_report_s *args)
+{
+	_mali_uk_vsync_event event = (_mali_uk_vsync_event)args->event;
+	MALI_IGNORE(event); /* event is not used for release code, and that is OK */
+/*	u64 ts = _mali_timestamp_get();
+ */
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+	if ( event==_MALI_UK_VSYNC_EVENT_BEGIN_WAIT)
+	{
+		_mali_profiling_add_event(  MALI_PROFILING_EVENT_TYPE_SUSPEND |
+		                            MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+		                            MALI_PROFILING_EVENT_REASON_SUSPEND_RESUME_SW_VSYNC,
+		                            0, 0, 0, 0, 0);
+	}
+
+	if ( event==_MALI_UK_VSYNC_EVENT_END_WAIT)
+	{
+
+		_mali_profiling_add_event(  MALI_PROFILING_EVENT_TYPE_RESUME |
+		                            MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+		                            MALI_PROFILING_EVENT_REASON_SUSPEND_RESUME_SW_VSYNC,
+		                            0, 0, 0, 0, 0);
+	}
+#endif
+	MALI_DEBUG_PRINT(4, ("Received VSYNC event: %d\n", event));
+	MALI_SUCCESS;
+}
+
diff --git a/drivers/media/video/samsung/mali/common/mali_osk.h b/drivers/media/video/samsung/mali/common/mali_osk.h
new file mode 100644
index 0000000..72d851d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_osk.h
@@ -0,0 +1,1716 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk.h
+ * Defines the OS abstraction layer for the kernel device driver (OSK)
+ */
+
+#ifndef __MALI_OSK_H__
+#define __MALI_OSK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup uddapi Unified Device Driver (UDD) APIs
+ *
+ * @{
+ */
+
+/**
+ * @addtogroup oskapi UDD OS Abstraction for Kernel-side (OSK) APIs
+ *
+ * @{
+ */
+
+/** @defgroup _mali_osk_miscellaneous OSK Miscellaneous functions, constants and types
+ * @{ */
+
+/* Define integer types used by OSK. Note: these currently clash with Linux so we only define them if not defined already */
+#ifndef __KERNEL__
+	typedef unsigned char      u8;
+	typedef signed char        s8;
+	typedef unsigned short     u16;
+	typedef signed short       s16;
+	typedef unsigned int       u32;
+	typedef signed int         s32;
+	typedef unsigned long long u64;
+	#define BITS_PER_LONG (sizeof(long)*8)
+#else
+	/* Ensure Linux types u32, etc. are defined */
+	#include <linux/types.h>
+#endif
+
+/** @brief Mali Boolean type which uses MALI_TRUE and MALI_FALSE
+  */
+	typedef unsigned long mali_bool;
+
+#ifndef MALI_TRUE
+	#define MALI_TRUE ((mali_bool)1)
+#endif
+
+#ifndef MALI_FALSE
+	#define MALI_FALSE ((mali_bool)0)
+#endif
+
+/**
+ * @brief OSK Error codes
+ *
+ * Each OS may use its own set of error codes, and may require that the
+ * User/Kernel interface take certain error code. This means that the common
+ * error codes need to be sufficiently rich to pass the correct error code
+ * thorugh from the OSK to U/K layer, across all OSs.
+ *
+ * The result is that some error codes will appear redundant on some OSs.
+ * Under all OSs, the OSK layer must translate native OS error codes to
+ * _mali_osk_errcode_t codes. Similarly, the U/K layer must translate from
+ * _mali_osk_errcode_t codes to native OS error codes.
+ */
+typedef enum
+{
+    _MALI_OSK_ERR_OK = 0, /**< Success. */
+    _MALI_OSK_ERR_FAULT = -1, /**< General non-success */
+    _MALI_OSK_ERR_INVALID_FUNC = -2, /**< Invalid function requested through User/Kernel interface (e.g. bad IOCTL number) */
+    _MALI_OSK_ERR_INVALID_ARGS = -3, /**< Invalid arguments passed through User/Kernel interface */
+    _MALI_OSK_ERR_NOMEM = -4, /**< Insufficient memory */
+    _MALI_OSK_ERR_TIMEOUT = -5, /**< Timeout occurred */
+    _MALI_OSK_ERR_RESTARTSYSCALL = -6, /**< Special: On certain OSs, must report when an interruptable mutex is interrupted. Ignore otherwise. */
+    _MALI_OSK_ERR_ITEM_NOT_FOUND = -7, /**< Table Lookup failed */
+    _MALI_OSK_ERR_BUSY = -8, /**< Device/operation is busy. Try again later */
+	_MALI_OSK_ERR_UNSUPPORTED = -9, /**< Optional part of the interface used, and is unsupported */
+} _mali_osk_errcode_t;
+
+/** @} */ /* end group _mali_osk_miscellaneous */
+
+
+/** @defgroup _mali_osk_irq OSK IRQ handling
+ * @{ */
+
+/** @brief Private type for IRQ handling objects */
+typedef struct _mali_osk_irq_t_struct _mali_osk_irq_t;
+
+/** @brief Optional function to trigger an irq from a resource
+ *
+ * This function is implemented by the common layer to allow probing of a resource's IRQ.
+ * @param arg resource-specific data */
+typedef void  (*_mali_osk_irq_trigger_t)( void * arg );
+
+/** @brief Optional function to acknowledge an irq from a resource
+ *
+ * This function is implemented by the common layer to allow probing of a resource's IRQ.
+ * @param arg resource-specific data
+ * @return _MALI_OSK_ERR_OK if the IRQ was successful, or a suitable _mali_osk_errcode_t on failure. */
+typedef _mali_osk_errcode_t (*_mali_osk_irq_ack_t)( void * arg );
+
+/** @brief IRQ 'upper-half' handler callback.
+ *
+ * This function is implemented by the common layer to do the initial handling of a
+ * resource's IRQ. This maps on to the concept of an ISR that does the minimum
+ * work necessary before handing off to an IST.
+ *
+ * The communication of the resource-specific data from the ISR to the IST is
+ * handled by the OSK implementation.
+ *
+ * On most systems, the IRQ upper-half handler executes in IRQ context.
+ * Therefore, the system may have restrictions about what can be done in this
+ * context
+ *
+ * If an IRQ upper-half handler requires more work to be done than can be
+ * acheived in an IRQ context, then it may defer the work with
+ * _mali_osk_irq_schedulework(). Refer to \ref _mali_osk_irq_schedulework() for
+ * more information.
+ *
+ * @param arg resource-specific data
+ * @return _MALI_OSK_ERR_OK if the IRQ was correctly handled, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+typedef _mali_osk_errcode_t  (*_mali_osk_irq_uhandler_t)( void * arg );
+
+/** @brief IRQ 'bottom-half' handler callback.
+ *
+ * This function is implemented by the common layer to do the deferred handling
+ * of a resource's IRQ. Usually, this work cannot be carried out in IRQ context
+ * by the IRQ upper-half handler.
+ *
+ * The IRQ bottom-half handler maps on to the concept of an IST that may
+ * execute some time after the actual IRQ has fired.
+ *
+ * All OSK-registered IRQ bottom-half handlers will be serialized, across all
+ * CPU-cores in the system.
+ *
+ * Refer to \ref _mali_osk_irq_schedulework() for more information on the
+ * IRQ work-queue, and the calling of the IRQ bottom-half handler.
+ *
+ * @param arg resource-specific data
+ */
+typedef void (*_mali_osk_irq_bhandler_t)( void * arg );
+/** @} */ /* end group _mali_osk_irq */
+
+
+/** @defgroup _mali_osk_atomic OSK Atomic counters
+ * @{ */
+
+/** @brief Public type of atomic counters
+ *
+ * This is public for allocation on stack. On systems that support it, this is just a single 32-bit value.
+ * On others, it could be encapsulating an object stored elsewhere.
+ *
+ * Even though the structure has space for a u32, the counters will only
+ * represent signed 24-bit integers.
+ *
+ * Regardless of implementation, the \ref _mali_osk_atomic functions \b must be used
+ * for all accesses to the variable's value, even if atomicity is not required.
+ * Do not access u.val or u.obj directly.
+ */
+typedef struct
+{
+    union
+    {
+        u32 val;
+        void *obj;
+    } u;
+} _mali_osk_atomic_t;
+/** @} */ /* end group _mali_osk_atomic */
+
+
+/** @defgroup _mali_osk_lock OSK Mutual Exclusion Locks
+ * @{ */
+
+/** @brief OSK Mutual Exclusion Lock flags type
+ *
+ * Flags are supplied at the point where the Lock is initialized. Each flag can
+ * be combined with others using bitwise OR, '|'.
+ *
+ * The flags must be sufficiently rich to cope with all our OSs. This means
+ * that on some OSs, certain flags can be completely ignored. We define a
+ * number of terms that are significant across all OSs:
+ *
+ * - Sleeping/non-sleeping mutexs. Sleeping mutexs can block on waiting, and so
+ * schedule out the current thread. This is significant on OSs where there are
+ * situations in which the current thread must not be put to sleep. On OSs
+ * without this restriction, sleeping and non-sleeping mutexes can be treated
+ * as the same (if that is required).
+ * - Interruptable/non-interruptable mutexes. For sleeping mutexes, it may be
+ * possible for the sleep to be interrupted for a reason other than the thread
+ * being able to obtain the lock. OSs behaving in this way may provide a
+ * mechanism to control whether sleeping mutexes can be interrupted. On OSs
+ * that do not support the concept of interruption, \b or they do not support
+ * control of mutex interruption, then interruptable mutexes may be treated
+ * as non-interruptable.
+ *
+ * Some constrains apply to the lock type flags:
+ *
+ * - Spinlocks are by nature, non-interruptable. Hence, they must always be
+ * combined with the NONINTERRUPTABLE flag, because it is meaningless to ask
+ * for a spinlock that is interruptable (and this highlights its
+ * non-interruptable-ness). For example, on certain OSs they should be used when
+ * you must not sleep.
+ * - Reader/writer is an optimization hint, and any type of lock can be
+ * reader/writer. Since this is an optimization hint, the implementation need
+ * not respect this for any/all types of lock. For example, on certain OSs,
+ * there's no interruptable reader/writer mutex. If such a thing were requested
+ * on that OS, the fact that interruptable was requested takes priority over the
+ * reader/writer-ness, because reader/writer-ness is not necessary for correct
+ * operation.
+ * - Any lock can use the order parameter.
+ * - A onelock is an optimization hint specific to certain OSs. It can be
+ * specified when it is known that only one lock will be held by the thread,
+ * and so can provide faster mutual exclusion. This can be safely ignored if
+ * such optimization is not required/present.
+ *
+ * The absence of any flags (the value 0) results in a sleeping-mutex, which is interruptable.
+ */
+typedef enum
+{
+	_MALI_OSK_LOCKFLAG_SPINLOCK = 0x1,          /**< Specifically, don't sleep on those architectures that require it */
+	_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE = 0x2,  /**< The mutex cannot be interrupted, e.g. delivery of signals on those architectures where this is required */
+	_MALI_OSK_LOCKFLAG_READERWRITER = 0x4,      /**< Optimise for readers/writers */
+	_MALI_OSK_LOCKFLAG_ORDERED = 0x8,           /**< Use the order parameter; otherwise use automatic ordering */
+	_MALI_OSK_LOCKFLAG_ONELOCK = 0x10,          /**< Each thread can only hold one lock at a time */
+	_MALI_OSK_LOCKFLAG_SPINLOCK_IRQ = 0x20,    /**<  IRQ version of spinlock */
+	/** @enum _mali_osk_lock_flags_t
+	 *
+	 * Flags from 0x10000--0x80000000 are RESERVED for User-mode */
+
+} _mali_osk_lock_flags_t;
+
+/** @brief Mutual Exclusion Lock Mode Optimization hint
+ *
+ * The lock mode is used to implement the read/write locking of locks specified
+ * as _MALI_OSK_LOCKFLAG_READERWRITER. In this case, the RO mode can be used
+ * to allow multiple concurrent readers, but no writers. The RW mode is used for
+ * writers, and so will wait for all readers to release the lock (if any present).
+ * Further readers and writers will wait until the writer releases the lock.
+ *
+ * The mode is purely an optimization hint: for example, it is permissible for
+ * all locks to behave in RW mode, regardless of that supplied.
+ *
+ * It is an error to attempt to use locks in anything other that RW mode when
+ * _MALI_OSK_LOCKFLAG_READERWRITER is not supplied.
+ *
+ */
+typedef enum
+{
+	_MALI_OSK_LOCKMODE_UNDEF = -1,  /**< Undefined lock mode. For internal use only */
+	_MALI_OSK_LOCKMODE_RW    = 0x0, /**< Read-write mode, default. All readers and writers are mutually-exclusive */
+	_MALI_OSK_LOCKMODE_RO,          /**< Read-only mode, to support multiple concurrent readers, but mutual exclusion in the presence of writers. */
+	/** @enum _mali_osk_lock_mode_t
+	 *
+	 * Lock modes 0x40--0x7F are RESERVED for User-mode */
+} _mali_osk_lock_mode_t;
+
+/** @brief Private type for Mutual Exclusion lock objects */
+typedef struct _mali_osk_lock_t_struct _mali_osk_lock_t;
+/** @} */ /* end group _mali_osk_lock */
+
+/** @defgroup _mali_osk_low_level_memory OSK Low-level Memory Operations
+ * @{ */
+
+/**
+ * @brief Private data type for use in IO accesses to/from devices.
+ *
+ * This represents some range that is accessible from the device. Examples
+ * include:
+ * - Device Registers, which could be readable and/or writeable.
+ * - Memory that the device has access to, for storing configuration structures.
+ *
+ * Access to this range must be made through the _mali_osk_mem_ioread32() and
+ * _mali_osk_mem_iowrite32() functions.
+ */
+typedef struct _mali_io_address * mali_io_address;
+
+/** @defgroup _MALI_OSK_CPU_PAGE CPU Physical page size macros.
+ *
+ * The order of the page size is supplied for
+ * ease of use by algorithms that might require it, since it is easier to know
+ * it ahead of time rather than calculating it.
+ *
+ * The Mali Page Mask macro masks off the lower bits of a physical address to
+ * give the start address of the page for that physical address.
+ *
+ * @note The Mali device driver code is designed for systems with 4KB page size.
+ * Changing these macros will not make the entire Mali device driver work with
+ * page sizes other than 4KB.
+ *
+ * @note The CPU Physical Page Size has been assumed to be the same as the Mali
+ * Physical Page Size.
+ *
+ * @{
+ */
+
+/** CPU Page Order, as log to base 2 of the Page size. @see _MALI_OSK_CPU_PAGE_SIZE */
+#define _MALI_OSK_CPU_PAGE_ORDER ((u32)12)
+/** CPU Page Size, in bytes.               */
+#define _MALI_OSK_CPU_PAGE_SIZE (((u32)1) << (_MALI_OSK_CPU_PAGE_ORDER))
+/** CPU Page Mask, which masks off the offset within a page */
+#define _MALI_OSK_CPU_PAGE_MASK (~((((u32)1) << (_MALI_OSK_CPU_PAGE_ORDER)) - ((u32)1)))
+/** @} */ /* end of group _MALI_OSK_CPU_PAGE */
+
+/** @defgroup _MALI_OSK_MALI_PAGE Mali Physical Page size macros
+ *
+ * Mali Physical page size macros. The order of the page size is supplied for
+ * ease of use by algorithms that might require it, since it is easier to know
+ * it ahead of time rather than calculating it.
+ *
+ * The Mali Page Mask macro masks off the lower bits of a physical address to
+ * give the start address of the page for that physical address.
+ *
+ * @note The Mali device driver code is designed for systems with 4KB page size.
+ * Changing these macros will not make the entire Mali device driver work with
+ * page sizes other than 4KB.
+ *
+ * @note The Mali Physical Page Size has been assumed to be the same as the CPU
+ * Physical Page Size.
+ *
+ * @{
+ */
+
+/** Mali Page Order, as log to base 2 of the Page size. @see _MALI_OSK_MALI_PAGE_SIZE */
+#define _MALI_OSK_MALI_PAGE_ORDER ((u32)12)
+/** Mali Page Size, in bytes.               */
+#define _MALI_OSK_MALI_PAGE_SIZE (((u32)1) << (_MALI_OSK_MALI_PAGE_ORDER))
+/** Mali Page Mask, which masks off the offset within a page */
+#define _MALI_OSK_MALI_PAGE_MASK (~((((u32)1) << (_MALI_OSK_MALI_PAGE_ORDER)) - ((u32)1)))
+/** @} */ /* end of group _MALI_OSK_MALI_PAGE*/
+
+/** @brief flags for mapping a user-accessible memory range
+ *
+ * Where a function with prefix '_mali_osk_mem_mapregion' accepts flags as one
+ * of the function parameters, it will use one of these. These allow per-page
+ * control over mappings. Compare with the mali_memory_allocation_flag type,
+ * which acts over an entire range
+ *
+ * These may be OR'd together with bitwise OR (|), but must be cast back into
+ * the type after OR'ing.
+ */
+typedef enum
+{
+	_MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR = 0x1, /**< Physical address is OS Allocated */
+} _mali_osk_mem_mapregion_flags_t;
+/** @} */ /* end group _mali_osk_low_level_memory */
+
+/** @defgroup _mali_osk_notification OSK Notification Queues
+ * @{ */
+
+/** @brief Private type for notification queue objects */
+typedef struct _mali_osk_notification_queue_t_struct _mali_osk_notification_queue_t;
+
+/** @brief Public notification data object type */
+typedef struct _mali_osk_notification_t_struct
+{
+	u32 magic_code;
+	u32 notification_type;   /**< The notification type */
+	u32 result_buffer_size; /**< Size of the result buffer to copy to user space */
+	void * result_buffer;   /**< Buffer containing any type specific data */
+} _mali_osk_notification_t;
+
+/** @} */ /* end group _mali_osk_notification */
+
+
+/** @defgroup _mali_osk_timer OSK Timer Callbacks
+ * @{ */
+
+/** @brief Function to call when a timer expires
+ *
+ * When a timer expires, this function is called. Note that on many systems,
+ * a timer callback will be executed in IRQ context. Therefore, restrictions
+ * may apply on what can be done inside the timer callback.
+ *
+ * If a timer requires more work to be done than can be acheived in an IRQ
+ * context, then it may defer the work with a work-queue. For example, it may
+ * use \ref _mali_osk_irq_schedulework() to make use of the IRQ bottom-half handler
+ * to carry out the remaining work.
+ *
+ * Stopping the timer with \ref _mali_osk_timer_del() blocks on compeletion of
+ * the callback. Therefore, the callback may not obtain any mutexes also held
+ * by any callers of _mali_osk_timer_del(). Otherwise, a deadlock may occur.
+ *
+ * @param arg Function-specific data */
+typedef void (*_mali_osk_timer_callback_t)(void * arg );
+
+/** @brief Private type for Timer Callback Objects */
+typedef struct _mali_osk_timer_t_struct _mali_osk_timer_t;
+/** @} */ /* end group _mali_osk_timer */
+
+
+/** @addtogroup _mali_osk_list OSK Doubly-Linked Circular Lists
+ * @{ */
+
+/** @brief Public List objects.
+ *
+ * To use, add a _mali_osk_list_t member to the structure that may become part
+ * of a list. When traversing the _mali_osk_list_t objects, use the
+ * _MALI_OSK_CONTAINER_OF() macro to recover the structure from its
+ *_mali_osk_list_t member
+ *
+ * Each structure may have multiple _mali_osk_list_t members, so that the
+ * structure is part of multiple lists. When traversing lists, ensure that the
+ * correct _mali_osk_list_t member is used, because type-checking will be
+ * lost by the compiler.
+ */
+typedef struct _mali_osk_list_s
+{
+	struct _mali_osk_list_s *next;
+	struct _mali_osk_list_s *prev;
+} _mali_osk_list_t;
+
+/** @brief Initialize a list to be a head of an empty list
+ * @param exp the list to initialize. */
+#define _MALI_OSK_INIT_LIST_HEAD(exp) _mali_osk_list_init(exp)
+
+/** @brief Define a list variable, which is uninitialized.
+ * @param exp the name of the variable that the list will be defined as. */
+#define _MALI_OSK_LIST_HEAD(exp)      _mali_osk_list_t exp
+
+/** @brief Find the containing structure of another structure
+ *
+ * This is the reverse of the operation 'offsetof'. This means that the
+ * following condition is satisfied:
+ *
+ *   ptr == _MALI_OSK_CONTAINER_OF( &ptr->member, type, member )
+ *
+ * When ptr is of type 'type'.
+ *
+ * Its purpose it to recover a larger structure that has wrapped a smaller one.
+ *
+ * @note no type or memory checking occurs to ensure that a wrapper structure
+ * does in fact exist, and that it is being recovered with respect to the
+ * correct member.
+ *
+ * @param ptr the pointer to the member that is contained within the larger
+ * structure
+ * @param type the type of the structure that contains the member
+ * @param member the name of the member in the structure that ptr points to.
+ * @return a pointer to a \a type object which contains \a member, as pointed
+ * to by \a ptr.
+ */
+#define _MALI_OSK_CONTAINER_OF(ptr, type, member) \
+             ((type *)( ((char *)ptr) - offsetof(type,member) ))
+
+/** @brief Find the containing structure of a list
+ *
+ * When traversing a list, this is used to recover the containing structure,
+ * given that is contains a _mali_osk_list_t member.
+ *
+ * Each list must be of structures of one type, and must link the same members
+ * together, otherwise it will not be possible to correctly recover the
+ * sturctures that the lists link.
+ *
+ * @note no type or memory checking occurs to ensure that a structure does in
+ * fact exist for the list entry, and that it is being recovered with respect
+ * to the correct list member.
+ *
+ * @param ptr the pointer to the _mali_osk_list_t member in this structure
+ * @param type the type of the structure that contains the member
+ * @param member the member of the structure that ptr points to.
+ * @return a pointer to a \a type object which contains the _mali_osk_list_t
+ * \a member, as pointed to by the _mali_osk_list_t \a *ptr.
+ */
+#define _MALI_OSK_LIST_ENTRY(ptr, type, member) \
+            _MALI_OSK_CONTAINER_OF(ptr, type, member)
+
+/** @brief Enumerate a list safely
+ *
+ * With this macro, lists can be enumerated in a 'safe' manner. That is,
+ * entries can be deleted from the list without causing an error during
+ * enumeration. To achieve this, a 'temporary' pointer is required, which must
+ * be provided to the macro.
+ *
+ * Use it like a 'for()', 'while()' or 'do()' construct, and so it must be
+ * followed by a statement or compound-statement which will be executed for
+ * each list entry.
+ *
+ * Upon loop completion, providing that an early out was not taken in the
+ * loop body, then it is guaranteed that ptr->member == list, even if the loop
+ * body never executed.
+ *
+ * @param ptr a pointer to an object of type 'type', which points to the
+ * structure that contains the currently enumerated list entry.
+ * @param tmp a pointer to an object of type 'type', which must not be used
+ * inside the list-execution statement.
+ * @param list a pointer to a _mali_osk_list_t, from which enumeration will
+ * begin
+ * @param type the type of the structure that contains the _mali_osk_list_t
+ * member that is part of the list to be enumerated.
+ * @param member the _mali_osk_list_t member of the structure that is part of
+ * the list to be enumerated.
+ */
+#define _MALI_OSK_LIST_FOREACHENTRY(ptr, tmp, list, type, member)         \
+        for (ptr = _MALI_OSK_LIST_ENTRY((list)->next, type, member),      \
+             tmp = _MALI_OSK_LIST_ENTRY(ptr->member.next, type, member); \
+             &ptr->member != (list);                                    \
+             ptr = tmp, tmp = _MALI_OSK_LIST_ENTRY(tmp->member.next, type, member))
+/** @} */ /* end group _mali_osk_list */
+
+
+/** @addtogroup _mali_osk_miscellaneous
+ * @{ */
+
+/** @brief The known resource types
+ *
+ * @note \b IMPORTANT: these must remain fixed, and only be extended. This is
+ * because not all systems use a header file for reading in their resources.
+ * The resources may instead come from a data file where these resources are
+ * 'hard-coded' in, because there's no easy way of transferring the enum values
+ * into such data files. E.g. the C-Pre-processor does \em not process enums.
+ */
+typedef enum _mali_osk_resource_type
+{
+	RESOURCE_TYPE_FIRST =0,  /**< Duplicate resource marker for the first resource*/
+	MEMORY              =0,  /**< Physically contiguous memory block, not managed by the OS */
+	OS_MEMORY           =1,  /**< Memory managed by and shared with the OS */
+	MALI200             =3,  /**< Mali200 Programmable Fragment Shader */
+	MALIGP2             =4,  /**< MaliGP2 Programmable Vertex Shader */
+	MMU                 =5,  /**< Mali MMU (Memory Management Unit) */
+	FPGA_FRAMEWORK      =6,  /**< Mali registers specific to FPGA implementations */
+	MALI400L2           =7,  /**< Mali400 L2 Cache */
+	MALI300L2           =7, /**< Mali300 L2 Cache */
+	MALI400GP           =8,  /**< Mali400 Programmable Vertex Shader Core */
+	MALI300GP           =8, /**< Mali300 Programmable Vertex Shader Core */
+	MALI400PP           =9,  /**< Mali400 Programmable Fragment Shader Core */
+	MALI300PP           =9, /**< Mali300 Programmable Fragment Shader Core */
+	MEM_VALIDATION      =10, /**< External Memory Validator */
+	PMU                 =11, /**< Power Manangement Unit */
+	RESOURCE_TYPE_COUNT      /**< The total number of known resources */
+} _mali_osk_resource_type_t;
+
+/** @brief resource description struct
+ *
+ * _mali_osk_resources_init() will enumerate objects of this type. Not all
+ * members have a valid meaning across all types.
+ *
+ * The mmu_id is used to group resources to a certain MMU, since there may be
+ * more than one MMU in the system, and each resource may be using a different
+ * MMU:
+ * - For MMU resources, the setting of mmu_id is a uniquely identifying number.
+ * - For Other resources, the setting of mmu_id determines which MMU the
+ * resource uses.
+ */
+typedef struct _mali_osk_resource
+{
+	_mali_osk_resource_type_t type; /**< type of the resource */
+	const char * description;       /**< short description of the resource */
+	u32 base;                       /**< Physical base address of the resource, as seen by Mali resources. */
+	s32 cpu_usage_adjust;           /**< Offset added to the base address of the resource to arrive at the CPU physical address of the resource (if different from the Mali physical address) */
+	u32 size;                       /**< Size in bytes of the resource - either the size of its register range, or the size of the memory block. */
+	u32 irq;                        /**< IRQ number delivered to the CPU, or -1 to tell the driver to probe for it (if possible) */
+	u32 flags;                      /**< Resources-specific flags. */
+	u32 mmu_id;                     /**< Identifier for Mali MMU resources. */
+	u32 alloc_order;                /**< Order in which MEMORY/OS_MEMORY resources are used */
+} _mali_osk_resource_t;
+/** @} */ /* end group _mali_osk_miscellaneous */
+
+
+#include "mali_kernel_memory_engine.h"   /* include for mali_memory_allocation and mali_physical_memory_allocation type */
+
+/** @addtogroup _mali_osk_irq
+ * @{ */
+
+/** @brief Fake IRQ number for testing purposes
+ */
+#define _MALI_OSK_IRQ_NUMBER_FAKE ((u32)0xFFFFFFF1)
+
+/** @addtogroup _mali_osk_irq
+ * @{ */
+
+/** @brief PMM Virtual IRQ number
+ */
+#define _MALI_OSK_IRQ_NUMBER_PMM ((u32)0xFFFFFFF2)
+
+
+/** @brief Initialize IRQ handling for a resource
+ *
+ * The _mali_osk_irq_t returned must be written into the resource-specific data
+ * pointed to by data. This is so that the upper and lower handlers can call
+ * _mali_osk_irq_schedulework().
+ *
+ * @note The caller must ensure that the resource does not generate an
+ * interrupt after _mali_osk_irq_init() finishes, and before the
+ * _mali_osk_irq_t is written into the resource-specific data. Otherwise,
+ * the upper-half handler will fail to call _mali_osk_irq_schedulework().
+ *
+ * @param irqnum The IRQ number that the resource uses, as seen by the CPU.
+ * The value -1 has a special meaning which indicates the use of probing, and trigger_func and ack_func must be
+ * non-NULL.
+ * @param uhandler The upper-half handler, corresponding to a ISR handler for
+ * the resource
+ * @param bhandler The lower-half handler, corresponding to an IST handler for
+ * the resource
+ * @param trigger_func Optional: a function to trigger the resource's irq, to
+ * probe for the interrupt. Use NULL if irqnum != -1.
+ * @param ack_func Optional: a function to acknowledge the resource's irq, to
+ * probe for the interrupt. Use NULL if irqnum != -1.
+ * @param data resource-specific data, which will be passed to uhandler,
+ * bhandler and (if present) trigger_func and ack_funnc
+ * @param description textual description of the IRQ resource.
+ * @return on success, a pointer to a _mali_osk_irq_t object, which represents
+ * the IRQ handling on this resource. NULL on failure.
+ */
+_mali_osk_irq_t *_mali_osk_irq_init( u32 irqnum, _mali_osk_irq_uhandler_t uhandler,	_mali_osk_irq_bhandler_t bhandler, _mali_osk_irq_trigger_t trigger_func, _mali_osk_irq_ack_t ack_func, void *data, const char *description );
+
+/** @brief Cause a queued, deferred call of the IRQ bottom-half.
+ *
+ * _mali_osk_irq_schedulework provides a mechanism for enqueuing deferred calls
+ * to the IRQ bottom-half handler. The queue is known as the IRQ work-queue.
+ * After calling _mali_osk_irq_schedulework(), the IRQ bottom-half handler will
+ * be scheduled to run at some point in the future.
+ *
+ * This is called by the IRQ upper-half to defer further processing of
+ * IRQ-related work to the IRQ bottom-half handler. This is necessary for work
+ * that cannot be done in an IRQ context by the IRQ upper-half handler. Timer
+ * callbacks also use this mechanism, because they are treated as though they
+ * operate in an IRQ context. Refer to \ref _mali_osk_timer_t for more
+ * information.
+ *
+ * Code that operates in a kernel-process context (with no IRQ context
+ * restrictions) may also enqueue deferred calls to the IRQ bottom-half. The
+ * advantage over direct calling is that deferred calling allows the caller and
+ * IRQ bottom half to hold the same mutex, with a guarantee that they will not
+ * deadlock just by using this mechanism.
+ *
+ * _mali_osk_irq_schedulework() places deferred call requests on a queue, to
+ * allow for more than one thread to make a deferred call. Therfore, if it is
+ * called 'K' times, then the IRQ bottom-half will be scheduled 'K' times too.
+ * 'K' is a number that is implementation-specific.
+ *
+ * _mali_osk_irq_schedulework() is guaranteed to not block on:
+ * - enqueuing a deferred call request.
+ * - the completion of the IRQ bottom-half handler.
+ *
+ * This is to prevent deadlock. For example, if _mali_osk_irq_schedulework()
+ * blocked, then it would cause a deadlock when the following two conditions
+ * hold:
+ * - The IRQ bottom-half callback (of type _mali_osk_irq_bhandler_t) locks
+ * a mutex
+ * - And, at the same time, the caller of _mali_osk_irq_schedulework() also
+ * holds the same mutex
+ *
+ * @note care must be taken to not overflow the queue that
+ * _mali_osk_irq_schedulework() operates on. Code must be structured to
+ * ensure that the number of requests made to the queue is bounded. Otherwise,
+ * IRQs will be lost.
+ *
+ * The queue that _mali_osk_irq_schedulework implements is a FIFO of N-writer,
+ * 1-reader type. The writers are the callers of _mali_osk_irq_schedulework
+ * (all OSK-registered IRQ upper-half handlers in the system, watchdog timers,
+ * callers from a Kernel-process context). The reader is a single thread that
+ * handles all OSK-registered IRQs.
+ *
+ * The consequence of the queue being a 1-reader type is that calling
+ * _mali_osk_irq_schedulework() on different _mali_osk_irq_t objects causes
+ * their IRQ bottom-halves to be serialized, across all CPU-cores in the
+ * system.
+ *
+ * @param irq a pointer to the _mali_osk_irq_t object corresponding to the
+ * resource whose IRQ bottom-half must begin processing.
+ */
+void _mali_osk_irq_schedulework( _mali_osk_irq_t *irq );
+
+/** @brief Terminate IRQ handling on a resource.
+ *
+ * This will disable the interrupt from the device, and then waits for the
+ * IRQ work-queue to finish the work that is currently in the queue. That is,
+ * for every deferred call currently in the IRQ work-queue, it waits for each
+ * of those to be processed by their respective IRQ bottom-half handler.
+ *
+ * This function is used to ensure that the bottom-half handler of the supplied
+ * IRQ object will not be running at the completion of this function call.
+ * However, the caller must ensure that no other sources could call the
+ * _mali_osk_irq_schedulework() on the same IRQ object. For example, the
+ * relevant timers must be stopped.
+ *
+ * @note While this function is being called, other OSK-registered IRQs in the
+ * system may enqueue work for their respective bottom-half handlers. This
+ * function will not wait for those entries in the work-queue to be flushed.
+ *
+ * Since this blocks on the completion of work in the IRQ work-queue, the
+ * caller of this function \b must \b not hold any mutexes that are taken by
+ * any OSK-registered IRQ bottom-half handler. To do so may cause a deadlock.
+ *
+ * @param irq a pointer to the _mali_osk_irq_t object corresponding to the
+ * resource whose IRQ handling is to be terminated.
+ */
+void _mali_osk_irq_term( _mali_osk_irq_t *irq );
+
+/** @brief flushing workqueue.
+ *
+ * This will flush the workqueue.
+ *
+ * @param irq a pointer to the _mali_osk_irq_t object corresponding to the
+ * resource whose IRQ handling is to be terminated.
+ */
+void _mali_osk_flush_workqueue( _mali_osk_irq_t *irq );
+
+/** @} */ /* end group _mali_osk_irq */
+
+
+/** @addtogroup _mali_osk_atomic
+ * @{ */
+
+/** @brief Decrement an atomic counter
+ *
+ * @note It is an error to decrement the counter beyond -(1<<23)
+ *
+ * @param atom pointer to an atomic counter */
+void _mali_osk_atomic_dec( _mali_osk_atomic_t *atom );
+
+/** @brief Decrement an atomic counter, return new value
+ *
+ * Although the value returned is a u32, only numbers with signed 24-bit
+ * precision (sign extended to u32) are returned.
+ *
+ * @note It is an error to decrement the counter beyond -(1<<23)
+ *
+ * @param atom pointer to an atomic counter
+ * @return The new value, after decrement */
+u32 _mali_osk_atomic_dec_return( _mali_osk_atomic_t *atom );
+
+/** @brief Increment an atomic counter
+ *
+ * @note It is an error to increment the counter beyond (1<<23)-1
+ *
+ * @param atom pointer to an atomic counter */
+void _mali_osk_atomic_inc( _mali_osk_atomic_t *atom );
+
+/** @brief Increment an atomic counter, return new value
+ *
+ * Although the value returned is a u32, only numbers with signed 24-bit
+ * precision (sign extended to u32) are returned.
+ *
+ * @note It is an error to increment the counter beyond (1<<23)-1
+ *
+ * @param atom pointer to an atomic counter */
+u32 _mali_osk_atomic_inc_return( _mali_osk_atomic_t *atom );
+
+/** @brief Initialize an atomic counter
+ *
+ * The counters have storage for signed 24-bit integers. Initializing to signed
+ * values requiring more than 24-bits storage will fail.
+ *
+ * @note the parameter required is a u32, and so signed integers should be
+ * cast to u32.
+ *
+ * @param atom pointer to an atomic counter
+ * @param val the value to initialize the atomic counter.
+ * @return _MALI_OSK_ERR_OK on success, otherwise, a suitable
+ * _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_osk_atomic_init( _mali_osk_atomic_t *atom, u32 val );
+
+/** @brief Read a value from an atomic counter
+ *
+ * Although the value returned is a u32, only numbers with signed 24-bit
+ * precision (sign extended to u32) are returned.
+ *
+ * This can only be safely used to determine the value of the counter when it
+ * is guaranteed that other threads will not be modifying the counter. This
+ * makes its usefulness limited.
+ *
+ * @param atom pointer to an atomic counter
+ */
+u32 _mali_osk_atomic_read( _mali_osk_atomic_t *atom );
+
+/** @brief Terminate an atomic counter
+ *
+ * @param atom pointer to an atomic counter
+ */
+void _mali_osk_atomic_term( _mali_osk_atomic_t *atom );
+/** @} */  /* end group _mali_osk_atomic */
+
+
+/** @defgroup _mali_osk_memory OSK Memory Allocation
+ * @{ */
+
+/** @brief Allocate zero-initialized memory.
+ *
+ * Returns a buffer capable of containing at least \a n elements of \a size
+ * bytes each. The buffer is initialized to zero.
+ *
+ * If there is a need for a bigger block of memory (16KB or bigger), then
+ * consider to use _mali_osk_vmalloc() instead, as this function might
+ * map down to a OS function with size limitations.
+ *
+ * The buffer is suitably aligned for storage and subsequent access of every
+ * type that the compiler supports. Therefore, the pointer to the start of the
+ * buffer may be cast into any pointer type, and be subsequently accessed from
+ * such a pointer, without loss of information.
+ *
+ * When the buffer is no longer in use, it must be freed with _mali_osk_free().
+ * Failure to do so will cause a memory leak.
+ *
+ * @note Most toolchains supply memory allocation functions that meet the
+ * compiler's alignment requirements.
+ *
+ * @param n Number of elements to allocate
+ * @param size Size of each element
+ * @return On success, the zero-initialized buffer allocated. NULL on failure
+ */
+void *_mali_osk_calloc( u32 n, u32 size );
+
+/** @brief Allocate memory.
+ *
+ * Returns a buffer capable of containing at least \a size bytes. The
+ * contents of the buffer are undefined.
+ *
+ * If there is a need for a bigger block of memory (16KB or bigger), then
+ * consider to use _mali_osk_vmalloc() instead, as this function might
+ * map down to a OS function with size limitations.
+ *
+ * The buffer is suitably aligned for storage and subsequent access of every
+ * type that the compiler supports. Therefore, the pointer to the start of the
+ * buffer may be cast into any pointer type, and be subsequently accessed from
+ * such a pointer, without loss of information.
+ *
+ * When the buffer is no longer in use, it must be freed with _mali_osk_free().
+ * Failure to do so will cause a memory leak.
+ *
+ * @note Most toolchains supply memory allocation functions that meet the
+ * compiler's alignment requirements.
+ *
+ * Remember to free memory using _mali_osk_free().
+ * @param size Number of bytes to allocate
+ * @return On success, the buffer allocated. NULL on failure.
+ */
+void *_mali_osk_malloc( u32 size );
+
+/** @brief Free memory.
+ *
+ * Reclaims the buffer pointed to by the parameter \a ptr for the system.
+ * All memory returned from _mali_osk_malloc() and _mali_osk_calloc()
+ * must be freed before the application exits. Otherwise,
+ * a memory leak will occur.
+ *
+ * Memory must be freed once. It is an error to free the same non-NULL pointer
+ * more than once.
+ *
+ * It is legal to free the NULL pointer.
+ *
+ * @param ptr Pointer to buffer to free
+ */
+void _mali_osk_free( void *ptr );
+
+/** @brief Allocate memory.
+ *
+ * Returns a buffer capable of containing at least \a size bytes. The
+ * contents of the buffer are undefined.
+ *
+ * This function is potentially slower than _mali_osk_malloc() and _mali_osk_calloc(),
+ * but do support bigger sizes.
+ *
+ * The buffer is suitably aligned for storage and subsequent access of every
+ * type that the compiler supports. Therefore, the pointer to the start of the
+ * buffer may be cast into any pointer type, and be subsequently accessed from
+ * such a pointer, without loss of information.
+ *
+ * When the buffer is no longer in use, it must be freed with _mali_osk_free().
+ * Failure to do so will cause a memory leak.
+ *
+ * @note Most toolchains supply memory allocation functions that meet the
+ * compiler's alignment requirements.
+ *
+ * Remember to free memory using _mali_osk_free().
+ * @param size Number of bytes to allocate
+ * @return On success, the buffer allocated. NULL on failure.
+ */
+void *_mali_osk_valloc( u32 size );
+
+/** @brief Free memory.
+ *
+ * Reclaims the buffer pointed to by the parameter \a ptr for the system.
+ * All memory returned from _mali_osk_valloc() must be freed before the
+ * application exits. Otherwise a memory leak will occur.
+ *
+ * Memory must be freed once. It is an error to free the same non-NULL pointer
+ * more than once.
+ *
+ * It is legal to free the NULL pointer.
+ *
+ * @param ptr Pointer to buffer to free
+ */
+void _mali_osk_vfree( void *ptr );
+
+/** @brief Copies memory.
+ *
+ * Copies the \a len bytes from the buffer pointed by the parameter \a src
+ * directly to the buffer pointed by \a dst.
+ *
+ * It is an error for \a src to overlap \a dst anywhere in \a len bytes.
+ *
+ * @param dst Pointer to the destination array where the content is to be
+ * copied.
+ * @param src Pointer to the source of data to be copied.
+ * @param len Number of bytes to copy.
+ * @return \a dst is always passed through unmodified.
+ */
+void *_mali_osk_memcpy( void *dst, const void *src, u32 len );
+
+/** @brief Fills memory.
+ *
+ * Sets the first \a n bytes of the block of memory pointed to by \a s to
+ * the specified value
+ * @param s Pointer to the block of memory to fill.
+ * @param c Value to be set, passed as u32. Only the 8 Least Significant Bits (LSB)
+ * are used.
+ * @param n Number of bytes to be set to the value.
+ * @return \a s is always passed through unmodified
+ */
+void *_mali_osk_memset( void *s, u32 c, u32 n );
+/** @} */ /* end group _mali_osk_memory */
+
+
+/** @brief Checks the amount of memory allocated
+ *
+ * Checks that not more than \a max_allocated bytes are allocated.
+ *
+ * Some OS bring up an interactive out of memory dialogue when the
+ * system runs out of memory. This can stall non-interactive
+ * apps (e.g. automated test runs). This function can be used to
+ * not trigger the OOM dialogue by keeping allocations
+ * within a certain limit.
+ *
+ * @return MALI_TRUE when \a max_allocated bytes are not in use yet. MALI_FALSE
+ * when at least \a max_allocated bytes are in use.
+ */
+mali_bool _mali_osk_mem_check_allocated( u32 max_allocated );
+
+/** @addtogroup _mali_osk_lock
+ * @{ */
+
+/** @brief Initialize a Mutual Exclusion Lock
+ *
+ * Locks are created in the signalled (unlocked) state.
+ *
+ * initial must be zero, since there is currently no means of expressing
+ * whether a reader/writer lock should be initially locked as a reader or
+ * writer. This would require some encoding to be used.
+ *
+ * 'Automatic' ordering means that locks must be obtained in the order that
+ * they were created. For all locks that can be held at the same time, they must
+ * either all provide the order parameter, or they all must use 'automatic'
+ * ordering - because there is no way of mixing 'automatic' and 'manual'
+ * ordering.
+ *
+ * @param flags flags combined with bitwise OR ('|'), or zero. There are
+ * restrictions on which flags can be combined, @see _mali_osk_lock_flags_t.
+ * @param initial For future expansion into semaphores. SBZ.
+ * @param order The locking order of the mutex. That is, locks obtained by the
+ * same thread must have been created with an increasing order parameter, for
+ * deadlock prevention. Setting to zero causes 'automatic' ordering to be used.
+ * @return On success, a pointer to a _mali_osk_lock_t object. NULL on failure.
+ */
+_mali_osk_lock_t *_mali_osk_lock_init( _mali_osk_lock_flags_t flags, u32 initial, u32 order );
+
+/** @brief Wait for a lock to be signalled (obtained)
+
+ * After a thread has successfully waited on the lock, the lock is obtained by
+ * the thread, and is marked as unsignalled. The thread releases the lock by
+ * signalling it.
+ *
+ * In the case of Reader/Writer locks, multiple readers can obtain a lock in
+ * the absence of writers, which is a performance optimization (providing that
+ * the readers never write to the protected resource).
+ *
+ * To prevent deadlock, locks must always be obtained in the same order.
+ *
+ * For locks marked as _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, it is a
+ * programming error for the function to exit without obtaining the lock. This
+ * means that the error code must only be checked for interruptible locks.
+ *
+ * @param lock the lock to wait upon (obtain).
+ * @param mode the mode in which the lock should be obtained. Unless the lock
+ * was created with _MALI_OSK_LOCKFLAG_READERWRITER, this must be
+ * _MALI_OSK_LOCKMODE_RW.
+ * @return On success, _MALI_OSK_ERR_OK. For interruptible locks, a suitable
+ * _mali_osk_errcode_t will be returned on failure, and the lock will not be
+ * obtained. In this case, the error code must be propagated up to the U/K
+ * interface.
+ */
+_mali_osk_errcode_t _mali_osk_lock_wait( _mali_osk_lock_t *lock, _mali_osk_lock_mode_t mode);
+
+
+/** @brief Signal (release) a lock
+ *
+ * Locks may only be signalled by the thread that originally waited upon the
+ * lock.
+ *
+ * @note In the OSU, a flag exists to allow any thread to signal a
+ * lock. Such functionality is not present in the OSK.
+ *
+ * @param lock the lock to signal (release).
+ * @param mode the mode in which the lock should be obtained. This must match
+ * the mode in which the lock was waited upon.
+ */
+void _mali_osk_lock_signal( _mali_osk_lock_t *lock, _mali_osk_lock_mode_t mode );
+
+/** @brief Terminate a lock
+ *
+ * This terminates a lock and frees all associated resources.
+ *
+ * It is a programming error to terminate the lock when it is held (unsignalled)
+ * by a thread.
+ *
+ * @param lock the lock to terminate.
+ */
+void _mali_osk_lock_term( _mali_osk_lock_t *lock );
+/** @} */ /* end group _mali_osk_lock */
+
+
+/** @addtogroup _mali_osk_low_level_memory
+ * @{ */
+
+/** @brief Issue a memory barrier
+ *
+ * This defines an arbitrary memory barrier operation, which forces an ordering constraint
+ * on memory read and write operations.
+ */
+void _mali_osk_mem_barrier( void );
+
+/** @brief Issue a write memory barrier
+ *
+ * This defines an write memory barrier operation which forces an ordering constraint
+ * on memory write operations.
+ */
+void _mali_osk_write_mem_barrier( void );
+
+/** @brief Map a physically contiguous region into kernel space
+ *
+ * This is primarily used for mapping in registers from resources, and Mali-MMU
+ * page tables. The mapping is only visable from kernel-space.
+ *
+ * Access has to go through _mali_osk_mem_ioread32 and _mali_osk_mem_iowrite32
+ *
+ * @param phys CPU-physical base address of the memory to map in. This must
+ * be aligned to the system's page size, which is assumed to be 4K.
+ * @param size the number of bytes of physically contiguous address space to
+ * map in
+ * @param description A textual description of the memory being mapped in.
+ * @return On success, a Mali IO address through which the mapped-in
+ * memory/registers can be accessed. NULL on failure.
+ */
+mali_io_address _mali_osk_mem_mapioregion( u32 phys, u32 size, const char *description );
+
+/** @brief Unmap a physically contiguous address range from kernel space.
+ *
+ * The address range should be one previously mapped in through
+ * _mali_osk_mem_mapioregion.
+ *
+ * It is a programming error to do (but not limited to) the following:
+ * - attempt an unmap twice
+ * - unmap only part of a range obtained through _mali_osk_mem_mapioregion
+ * - unmap more than the range obtained through  _mali_osk_mem_mapioregion
+ * - unmap an address range that was not successfully mapped using
+ * _mali_osk_mem_mapioregion
+ * - provide a mapping that does not map to phys.
+ *
+ * @param phys CPU-physical base address of the memory that was originally
+ * mapped in. This must be aligned to the system's page size, which is assumed
+ * to be 4K
+ * @param size The number of bytes that were originally mapped in.
+ * @param mapping The Mali IO address through which the mapping is
+ * accessed.
+ */
+void _mali_osk_mem_unmapioregion( u32 phys, u32 size, mali_io_address mapping );
+
+/** @brief Allocate and Map a physically contiguous region into kernel space
+ *
+ * This is used for allocating physically contiguous regions (such as Mali-MMU
+ * page tables) and mapping them into kernel space. The mapping is only
+ * visible from kernel-space.
+ *
+ * The alignment of the returned memory is guaranteed to be at least
+ * _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * Access must go through _mali_osk_mem_ioread32 and _mali_osk_mem_iowrite32
+ *
+ * @note This function is primarily to provide support for OSs that are
+ * incapable of separating the tasks 'allocate physically contiguous memory'
+ * and 'map it into kernel space'
+ *
+ * @param[out] phys CPU-physical base address of memory that was allocated.
+ * (*phys) will be guaranteed to be aligned to at least
+ * _MALI_OSK_CPU_PAGE_SIZE on success.
+ *
+ * @param[in] size the number of bytes of physically contiguous memory to
+ * allocate. This must be a multiple of _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * @return On success, a Mali IO address through which the mapped-in
+ * memory/registers can be accessed. NULL on failure, and (*phys) is unmodified.
+ */
+mali_io_address _mali_osk_mem_allocioregion( u32 *phys, u32 size );
+
+/** @brief Free a physically contiguous address range from kernel space.
+ *
+ * The address range should be one previously mapped in through
+ * _mali_osk_mem_allocioregion.
+ *
+ * It is a programming error to do (but not limited to) the following:
+ * - attempt a free twice on the same ioregion
+ * - free only part of a range obtained through _mali_osk_mem_allocioregion
+ * - free more than the range obtained through  _mali_osk_mem_allocioregion
+ * - free an address range that was not successfully mapped using
+ * _mali_osk_mem_allocioregion
+ * - provide a mapping that does not map to phys.
+ *
+ * @param phys CPU-physical base address of the memory that was originally
+ * mapped in, which was aligned to _MALI_OSK_CPU_PAGE_SIZE.
+ * @param size The number of bytes that were originally mapped in, which was
+ * a multiple of _MALI_OSK_CPU_PAGE_SIZE.
+ * @param mapping The Mali IO address through which the mapping is
+ * accessed.
+ */
+void _mali_osk_mem_freeioregion( u32 phys, u32 size, mali_io_address mapping );
+
+/** @brief Request a region of physically contiguous memory
+ *
+ * This is used to ensure exclusive access to a region of physically contigous
+ * memory.
+ *
+ * It is acceptable to implement this as a stub. However, it is then the job
+ * of the System Integrator to ensure that no other device driver will be using
+ * the physical address ranges used by Mali, while the Mali device driver is
+ * loaded.
+ *
+ * @param phys CPU-physical base address of the memory to request. This must
+ * be aligned to the system's page size, which is assumed to be 4K.
+ * @param size the number of bytes of physically contiguous address space to
+ * request.
+ * @param description A textual description of the memory being requested.
+ * @return _MALI_OSK_ERR_OK on success. Otherwise, a suitable
+ * _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_osk_mem_reqregion( u32 phys, u32 size, const char *description );
+
+/** @brief Un-request a region of physically contiguous memory
+ *
+ * This is used to release a regious of physically contiguous memory previously
+ * requested through _mali_osk_mem_reqregion, so that other device drivers may
+ * use it. This will be called at time of Mali device driver termination.
+ *
+ * It is a programming error to attempt to:
+ * - unrequest a region twice
+ * - unrequest only part of a range obtained through _mali_osk_mem_reqregion
+ * - unrequest more than the range obtained through  _mali_osk_mem_reqregion
+ * - unrequest an address range that was not successfully requested using
+ * _mali_osk_mem_reqregion
+ *
+ * @param phys CPU-physical base address of the memory to un-request. This must
+ * be aligned to the system's page size, which is assumed to be 4K
+ * @param size the number of bytes of physically contiguous address space to
+ * un-request.
+ */
+void _mali_osk_mem_unreqregion( u32 phys, u32 size );
+
+/** @brief Read from a location currently mapped in through
+ * _mali_osk_mem_mapioregion
+ *
+ * This reads a 32-bit word from a 32-bit aligned location. It is a programming
+ * error to provide unaligned locations, or to read from memory that is not
+ * mapped in, or not mapped through either _mali_osk_mem_mapioregion() or
+ * _mali_osk_mem_allocioregion().
+ *
+ * @param mapping Mali IO address to read from
+ * @param offset Byte offset from the given IO address to operate on, must be a multiple of 4
+ * @return the 32-bit word from the specified location.
+ */
+u32 _mali_osk_mem_ioread32( volatile mali_io_address mapping, u32 offset );
+
+/** @brief Write to a location currently mapped in through
+ * _mali_osk_mem_mapioregion without memory barriers
+ *
+ * This write a 32-bit word to a 32-bit aligned location without using memory barrier.
+ * It is a programming error to provide unaligned locations, or to write to memory that is not
+ * mapped in, or not mapped through either _mali_osk_mem_mapioregion() or
+ * _mali_osk_mem_allocioregion().
+ *
+ * @param mapping Mali IO address to write to
+ * @param offset Byte offset from the given IO address to operate on, must be a multiple of 4
+ * @param val the 32-bit word to write.
+ */
+void _mali_osk_mem_iowrite32_relaxed( volatile mali_io_address addr, u32 offset, u32 val );
+
+/** @brief Write to a location currently mapped in through
+ * _mali_osk_mem_mapioregion with write memory barrier
+ *
+ * This write a 32-bit word to a 32-bit aligned location. It is a programming
+ * error to provide unaligned locations, or to write to memory that is not
+ * mapped in, or not mapped through either _mali_osk_mem_mapioregion() or
+ * _mali_osk_mem_allocioregion().
+ *
+ * @param mapping Mali IO address to write to
+ * @param offset Byte offset from the given IO address to operate on, must be a multiple of 4
+ * @param val the 32-bit word to write.
+ */
+void _mali_osk_mem_iowrite32( volatile mali_io_address mapping, u32 offset, u32 val );
+
+/** @brief Flush all CPU caches
+ *
+ * This should only be implemented if flushing of the cache is required for
+ * memory mapped in through _mali_osk_mem_mapregion.
+ */
+void _mali_osk_cache_flushall( void );
+
+/** @brief Flush any caches necessary for the CPU and MALI to have the same view of a range of uncached mapped memory
+ *
+ * This should only be implemented if your OS doesn't do a full cache flush (inner & outer)
+ * after allocating uncached mapped memory.
+ *
+ * Some OS do not perform a full cache flush (including all outer caches) for uncached mapped memory.
+ * They zero the memory through a cached mapping, then flush the inner caches but not the outer caches.
+ * This is required for MALI to have the correct view of the memory.
+ */
+void _mali_osk_cache_ensure_uncached_range_flushed( void *uncached_mapping, u32 offset, u32 size );
+
+/** @} */ /* end group _mali_osk_low_level_memory */
+
+
+/** @addtogroup _mali_osk_notification
+ *
+ * User space notification framework
+ *
+ * Communication with user space of asynchronous events is performed through a
+ * synchronous call to the \ref u_k_api.
+ *
+ * Since the events are asynchronous, the events have to be queued until a
+ * synchronous U/K API call can be made by user-space. A U/K API call might also
+ * be received before any event has happened. Therefore the notifications the
+ * different subsystems wants to send to user space has to be queued for later
+ * reception, or a U/K API call has to be blocked until an event has occured.
+ *
+ * Typical uses of notifications are after running of jobs on the hardware or
+ * when changes to the system is detected that needs to be relayed to user
+ * space.
+ *
+ * After an event has occured user space has to be notified using some kind of
+ * message. The notification framework supports sending messages to waiting
+ * threads or queueing of messages until a U/K API call is made.
+ *
+ * The notification queue is a FIFO. There are no restrictions on the numbers
+ * of readers or writers in the queue.
+ *
+ * A message contains what user space needs to identifiy how to handle an
+ * event. This includes a type field and a possible type specific payload.
+ *
+ * A notification to user space is represented by a
+ * \ref _mali_osk_notification_t object. A sender gets hold of such an object
+ * using _mali_osk_notification_create(). The buffer given by the
+ * _mali_osk_notification_t::result_buffer field in the object is used to store
+ * any type specific data. The other fields are internal to the queue system
+ * and should not be touched.
+ *
+ * @{ */
+
+/** @brief Create a notification object
+ *
+ * Returns a notification object which can be added to the queue of
+ * notifications pending for user space transfer.
+ *
+ * The implementation will initialize all members of the
+ * \ref _mali_osk_notification_t object. In particular, the
+ * _mali_osk_notification_t::result_buffer member will be initialized to point
+ * to \a size bytes of storage, and that storage will be suitably aligned for
+ * storage of any structure. That is, the created buffer meets the same
+ * requirements as _mali_osk_malloc().
+ *
+ * The notification object must be deleted when not in use. Use
+ * _mali_osk_notification_delete() for deleting it.
+ *
+ * @note You \b must \b not call _mali_osk_free() on a \ref _mali_osk_notification_t,
+ * object, or on a _mali_osk_notification_t::result_buffer. You must only use
+ * _mali_osk_notification_delete() to free the resources assocaited with a
+ * \ref _mali_osk_notification_t object.
+ *
+ * @param type The notification type
+ * @param size The size of the type specific buffer to send
+ * @return Pointer to a notification object with a suitable buffer, or NULL on error.
+ */
+_mali_osk_notification_t *_mali_osk_notification_create( u32 type, u32 size );
+
+/** @brief Delete a notification object
+ *
+ * This must be called to reclaim the resources of a notification object. This
+ * includes:
+ * - The _mali_osk_notification_t::result_buffer
+ * - The \ref _mali_osk_notification_t itself.
+ *
+ * A notification object \b must \b not be used after it has been deleted by
+ * _mali_osk_notification_delete().
+ *
+ * In addition, the notification object may not be deleted while it is in a
+ * queue. That is, if it has been placed on a queue with
+ * _mali_osk_notification_queue_send(), then it must not be deleted until
+ * it has been received by a call to _mali_osk_notification_queue_receive().
+ * Otherwise, the queue may be corrupted.
+ *
+ * @param object the notification object to delete.
+ */
+void _mali_osk_notification_delete( _mali_osk_notification_t *object );
+
+/** @brief Create a notification queue
+ *
+ * Creates a notification queue which can be used to queue messages for user
+ * delivery and get queued messages from
+ *
+ * The queue is a FIFO, and has no restrictions on the numbers of readers or
+ * writers.
+ *
+ * When the queue is no longer in use, it must be terminated with
+ * \ref _mali_osk_notification_queue_term(). Failure to do so will result in a
+ * memory leak.
+ *
+ * @return Pointer to a new notification queue or NULL on error.
+ */
+_mali_osk_notification_queue_t *_mali_osk_notification_queue_init( void );
+
+/** @brief Destroy a notification queue
+ *
+ * Destroys a notification queue and frees associated resources from the queue.
+ *
+ * A notification queue \b must \b not be destroyed in the following cases:
+ * - while there are \ref _mali_osk_notification_t objects in the queue.
+ * - while there are writers currently acting upon the queue. That is, while
+ * a thread is currently calling \ref _mali_osk_notification_queue_send() on
+ * the queue, or while a thread may call
+ * \ref _mali_osk_notification_queue_send() on the queue in the future.
+ * - while there are readers currently waiting upon the queue. That is, while
+ * a thread is currently calling \ref _mali_osk_notification_queue_receive() on
+ * the queue, or while a thread may call
+ * \ref _mali_osk_notification_queue_receive() on the queue in the future.
+ *
+ * Therefore, all \ref _mali_osk_notification_t objects must be flushed and
+ * deleted by the code that makes use of the notification queues, since only
+ * they know the structure of the _mali_osk_notification_t::result_buffer
+ * (even if it may only be a flat sturcture).
+ *
+ * @note Since the queue is a FIFO, the code using notification queues may
+ * create its own 'flush' type of notification, to assist in flushing the
+ * queue.
+ *
+ * Once the queue has been destroyed, it must not be used again.
+ *
+ * @param queue The queue to destroy
+ */
+void _mali_osk_notification_queue_term( _mali_osk_notification_queue_t *queue );
+
+/** @brief Schedule notification for delivery
+ *
+ * When a \ref _mali_osk_notification_t object has been created successfully
+ * and set up, it may be added to the queue of objects waiting for user space
+ * transfer.
+ *
+ * The sending will not block if the queue is full.
+ *
+ * A \ref _mali_osk_notification_t object \b must \b not be put on two different
+ * queues at the same time, or enqueued twice onto a single queue before
+ * reception. However, it is acceptable for it to be requeued \em after reception
+ * from a call to _mali_osk_notification_queue_receive(), even onto the same queue.
+ *
+ * Again, requeuing must also not enqueue onto two different queues at the same
+ * time, or enqueue onto the same queue twice before reception.
+ *
+ * @param queue The notification queue to add this notification to
+ * @param object The entry to add
+ */
+void _mali_osk_notification_queue_send( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t *object );
+
+#if MALI_STATE_TRACKING
+/** @brief Receive a notification from a queue
+ *
+ * Check if a notification queue is empty.
+ *
+ * @param queue The queue to check.
+ * @return MALI_TRUE if queue is empty, otherwise MALI_FALSE.
+ */
+mali_bool _mali_osk_notification_queue_is_empty( _mali_osk_notification_queue_t *queue );
+#endif
+
+/** @brief Receive a notification from a queue
+ *
+ * Receives a single notification from the given queue.
+ *
+ * If no notifciations are ready the thread will sleep until one becomes ready.
+ * Therefore, notifications may not be received into an
+ * IRQ or 'atomic' context (that is, a context where sleeping is disallowed).
+ *
+ * @param queue The queue to receive from
+ * @param result Pointer to storage of a pointer of type
+ * \ref _mali_osk_notification_t*. \a result will be written to such that the
+ * expression \a (*result) will evaluate to a pointer to a valid
+ * \ref _mali_osk_notification_t object, or NULL if none were received.
+ * @return _MALI_OSK_ERR_OK on success. _MALI_OSK_ERR_RESTARTSYSCALL if the sleep was interrupted.
+ */
+_mali_osk_errcode_t _mali_osk_notification_queue_receive( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t **result );
+
+/** @brief Dequeues a notification from a queue
+ *
+ * Receives a single notification from the given queue.
+ *
+ * If no notifciations are ready the function call will return an error code.
+ *
+ * @param queue The queue to receive from
+ * @param result Pointer to storage of a pointer of type
+ * \ref _mali_osk_notification_t*. \a result will be written to such that the
+ * expression \a (*result) will evaluate to a pointer to a valid
+ * \ref _mali_osk_notification_t object, or NULL if none were received.
+ * @return _MALI_OSK_ERR_OK on success, _MALI_OSK_ERR_ITEM_NOT_FOUND if queue was empty.
+ */
+_mali_osk_errcode_t _mali_osk_notification_queue_dequeue( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t **result );
+
+/** @} */ /* end group _mali_osk_notification */
+
+
+/** @addtogroup _mali_osk_timer
+ *
+ * Timers use the OS's representation of time, which are 'ticks'. This is to
+ * prevent aliasing problems between the internal timer time, and the time
+ * asked for.
+ *
+ * @{ */
+
+/** @brief Initialize a timer
+ *
+ * Allocates resources for a new timer, and initializes them. This does not
+ * start the timer.
+ *
+ * @return a pointer to the allocated timer object, or NULL on failure.
+ */
+_mali_osk_timer_t *_mali_osk_timer_init(void);
+
+/** @brief Start a timer
+ *
+ * It is an error to start a timer without setting the callback via
+ * _mali_osk_timer_setcallback().
+ *
+ * It is an error to use this to start an already started timer.
+ *
+ * The timer will expire in \a ticks_to_expire ticks, at which point, the
+ * callback function will be invoked with the callback-specific data,
+ * as registered by _mali_osk_timer_setcallback().
+ *
+ * @param tim the timer to start
+ * @param ticks_to_expire the amount of time in ticks for the timer to run
+ * before triggering.
+ */
+void _mali_osk_timer_add( _mali_osk_timer_t *tim, u32 ticks_to_expire );
+
+/** @brief Modify a timer
+ *
+ * Set the absolute time at which a timer will expire, and start it if it is
+ * stopped. If \a expiry_tick is in the past (determined by
+ * _mali_osk_time_after() ), the timer fires immediately.
+ *
+ * It is an error to modify a timer without setting the callback via
+ *  _mali_osk_timer_setcallback().
+ *
+ * The timer will expire at absolute time \a expiry_tick, at which point, the
+ * callback function will be invoked with the callback-specific data, as set
+ * by _mali_osk_timer_setcallback().
+ *
+ * @param tim the timer to modify, and start if necessary
+ * @param expiry_tick the \em absolute time in ticks at which this timer should
+ * trigger.
+ *
+ */
+void _mali_osk_timer_mod( _mali_osk_timer_t *tim, u32 expiry_tick);
+
+/** @brief Stop a timer, and block on its completion.
+ *
+ * Stop the timer. When the function returns, it is guaranteed that the timer's
+ * callback will not be running on any CPU core.
+ *
+ * Since stoping the timer blocks on compeletion of the callback, the callback
+ * may not obtain any mutexes that the caller holds. Otherwise, a deadlock will
+ * occur.
+ *
+ * @note While the callback itself is guaranteed to not be running, work
+ * enqueued on the IRQ work-queue by the timer (with
+ * \ref _mali_osk_irq_schedulework()) may still run. The timer callback and IRQ
+ * bottom-half handler must take this into account.
+ *
+ * It is legal to stop an already stopped timer.
+ *
+ * @param tim the timer to stop.
+ *
+ */
+void _mali_osk_timer_del( _mali_osk_timer_t *tim );
+
+/** @brief Set a timer's callback parameters.
+ *
+ * This must be called at least once before a timer is started/modified.
+ *
+ * After a timer has been stopped or expires, the callback remains set. This
+ * means that restarting the timer will call the same function with the same
+ * parameters on expiry.
+ *
+ * @param tim the timer to set callback on.
+ * @param callback Function to call when timer expires
+ * @param data Function-specific data to supply to the function on expiry.
+ */
+void _mali_osk_timer_setcallback( _mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data );
+
+/** @brief Terminate a timer, and deallocate resources.
+ *
+ * The timer must first be stopped by calling _mali_osk_timer_del().
+ *
+ * It is a programming error for _mali_osk_timer_term() to be called on:
+ * - timer that is currently running
+ * - a timer that is currently executing its callback.
+ *
+ * @param tim the timer to deallocate.
+ */
+void _mali_osk_timer_term( _mali_osk_timer_t *tim );
+/** @} */ /* end group _mali_osk_timer */
+
+
+/** @defgroup _mali_osk_time OSK Time functions
+ *
+ * \ref _mali_osk_time use the OS's representation of time, which are
+ * 'ticks'. This is to prevent aliasing problems between the internal timer
+ * time, and the time asked for.
+ *
+ * OS tick time is measured as a u32. The time stored in a u32 may either be
+ * an absolute time, or a time delta between two events. Whilst it is valid to
+ * use math opeartors to \em change the tick value represented as a u32, it
+ * is often only meaningful to do such operations on time deltas, rather than
+ * on absolute time. However, it is meaningful to add/subtract time deltas to
+ * absolute times.
+ *
+ * Conversion between tick time and milliseconds (ms) may not be loss-less,
+ * and are \em implementation \em depenedant.
+ *
+ * Code use OS time must take this into account, since:
+ * - a small OS time may (or may not) be rounded
+ * - a large time may (or may not) overflow
+ *
+ * @{ */
+
+/** @brief Return whether ticka occurs after tickb
+ *
+ * Some OSs handle tick 'rollover' specially, and so can be more robust against
+ * tick counters rolling-over. This function must therefore be called to
+ * determine if a time (in ticks) really occurs after another time (in ticks).
+ *
+ * @param ticka ticka
+ * @param tickb tickb
+ * @return non-zero if ticka represents a time that occurs after tickb.
+ * Zero otherwise.
+ */
+int	_mali_osk_time_after( u32 ticka, u32 tickb );
+
+/** @brief Convert milliseconds to OS 'ticks'
+ *
+ * @param ms time interval in milliseconds
+ * @return the corresponding time interval in OS ticks.
+ */
+u32	_mali_osk_time_mstoticks( u32 ms );
+
+/** @brief Convert OS 'ticks' to milliseconds
+ *
+ * @param ticks time interval in OS ticks.
+ * @return the corresponding time interval in milliseconds
+ */
+u32	_mali_osk_time_tickstoms( u32 ticks );
+
+
+/** @brief Get the current time in OS 'ticks'.
+ * @return the current time in OS 'ticks'.
+ */
+u32	_mali_osk_time_tickcount( void );
+
+/** @brief Cause a microsecond delay
+ *
+ * The delay will have microsecond resolution, and is necessary for correct
+ * operation of the driver. At worst, the delay will be \b at least \a usecs
+ * microseconds, and so may be (significantly) more.
+ *
+ * This function may be implemented as a busy-wait, which is the most sensible
+ * implementation. On OSs where there are situations in which a thread must not
+ * sleep, this is definitely implemented as a busy-wait.
+ *
+ * @param usecs the number of microseconds to wait for.
+ */
+void _mali_osk_time_ubusydelay( u32 usecs );
+
+/** @brief Return time in nano seconds, since any given reference.
+ *
+ * @return Time in nano seconds
+ */
+u64 _mali_osk_time_get_ns( void );
+
+
+/** @} */ /* end group _mali_osk_time */
+
+/** @defgroup _mali_osk_math OSK Math
+ * @{ */
+
+/** @brief Count Leading Zeros (Little-endian)
+ *
+ * @note This function must be implemented to support the reference
+ * implementation of _mali_osk_find_first_zero_bit, as defined in
+ * mali_osk_bitops.h.
+ *
+ * @param val 32-bit words to count leading zeros on
+ * @return the number of leading zeros.
+ */
+u32 _mali_osk_clz( u32 val );
+/** @} */ /* end group _mali_osk_math */
+
+
+/** @addtogroup _mali_osk_miscellaneous
+ * @{ */
+
+/** @brief Output a device driver debug message.
+ *
+ * The interpretation of \a fmt is the same as the \c format parameter in
+ * _mali_osu_vsnprintf().
+ *
+ * @param fmt a _mali_osu_vsnprintf() style format string
+ * @param ... a variable-number of parameters suitable for \a fmt
+ */
+void _mali_osk_dbgmsg( const char *fmt, ... );
+
+/** @brief Print fmt into buf.
+ *
+ * The interpretation of \a fmt is the same as the \c format parameter in
+ * _mali_osu_vsnprintf().
+ *
+ * @param buf a pointer to the result buffer
+ * @param size the total number of bytes allowed to write to \a buf
+ * @param fmt a _mali_osu_vsnprintf() style format string
+ * @param ... a variable-number of parameters suitable for \a fmt
+ */
+u32 _mali_osk_snprintf( char *buf, u32 size, const char *fmt, ... );
+
+/** @brief Abnormal process abort.
+ *
+ * Terminates the caller-process if this function is called.
+ *
+ * This function will be called from Debug assert-macros in mali_kernel_common.h.
+ *
+ * This function will never return - because to continue from a Debug assert
+ * could cause even more problems, and hinder debugging of the initial problem.
+ *
+ * This function is only used in Debug builds, and is not used in Release builds.
+ */
+void _mali_osk_abort(void);
+
+/** @brief Sets breakpoint at point where function is called.
+ *
+ * This function will be called from Debug assert-macros in mali_kernel_common.h,
+ * to assist in debugging. If debugging at this level is not required, then this
+ * function may be implemented as a stub.
+ *
+ * This function is only used in Debug builds, and is not used in Release builds.
+ */
+void _mali_osk_break(void);
+
+/** @brief Return an identificator for calling process.
+ *
+ * @return Identificator for calling process.
+ */
+u32 _mali_osk_get_pid(void);
+
+/** @brief Return an identificator for calling thread.
+ *
+ * @return Identificator for calling thread.
+ */
+u32 _mali_osk_get_tid(void);
+
+void _mali_osk_profiling_add_event(u32 event_id, u32 data0);
+void _mali_osk_profiling_add_counter(u32 event_id, u32 data0);
+int _mali_osk_counter_event(u32 counter, u32 event);
+extern u32 counter_table[];
+
+/** @} */ /* end group  _mali_osk_miscellaneous */
+
+
+/** @} */ /* end group osuapi */
+
+/** @} */ /* end group uddapi */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#include "mali_osk_specific.h"           /* include any per-os specifics */
+
+/* Check standard inlines */
+#ifndef MALI_STATIC_INLINE
+	#error MALI_STATIC_INLINE not defined on your OS
+#endif
+
+#ifndef MALI_NON_STATIC_INLINE
+	#error MALI_NON_STATIC_INLINE not defined on your OS
+#endif
+
+#endif /* __MALI_OSK_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_osk_bitops.h b/drivers/media/video/samsung/mali/common/mali_osk_bitops.h
new file mode 100644
index 0000000..f262f7d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_osk_bitops.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_bitops.h
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#ifndef __MALI_OSK_BITOPS_H__
+#define __MALI_OSK_BITOPS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+MALI_STATIC_INLINE void _mali_internal_clear_bit( u32 bit, u32 *addr )
+{
+	MALI_DEBUG_ASSERT( bit < 32 );
+	MALI_DEBUG_ASSERT( NULL != addr );
+
+	(*addr) &= ~(1 << bit);
+}
+
+MALI_STATIC_INLINE void _mali_internal_set_bit( u32 bit, u32 *addr )
+{
+	MALI_DEBUG_ASSERT( bit < 32 );
+	MALI_DEBUG_ASSERT( NULL != addr );
+
+	(*addr) |= (1 << bit);
+}
+
+MALI_STATIC_INLINE u32 _mali_internal_test_bit( u32 bit, u32 value )
+{
+	MALI_DEBUG_ASSERT( bit < 32 );
+	return value & (1 << bit);
+}
+
+MALI_STATIC_INLINE int _mali_internal_find_first_zero_bit( u32 value )
+{
+	u32 inverted;
+	u32 negated;
+	u32 isolated;
+	u32 leading_zeros;
+
+	/* Begin with xxx...x0yyy...y, where ys are 1, number of ys is in range  0..31 */
+	inverted = ~value; /* zzz...z1000...0 */
+	/* Using count_trailing_zeros on inverted value -
+	 * See ARM System Developers Guide for details of count_trailing_zeros */
+
+	/* Isolate the zero: it is preceeded by a run of 1s, so add 1 to it */
+	negated = (u32)-inverted ; /* -a == ~a + 1 (mod 2^n) for n-bit numbers */
+    /* negated = xxx...x1000...0 */
+
+	isolated = negated & inverted ; /* xxx...x1000...0 & zzz...z1000...0, zs are ~xs */
+	/* And so the first zero bit is in the same position as the 1 == number of 1s that preceeded it
+	 * Note that the output is zero if value was all 1s */
+
+	leading_zeros = _mali_osk_clz( isolated );
+
+	return 31 - leading_zeros;
+}
+
+
+/** @defgroup _mali_osk_bitops OSK Non-atomic Bit-operations
+ * @{ */
+
+/**
+ * These bit-operations do not work atomically, and so locks must be used if
+ * atomicity is required.
+ *
+ * Reference implementations for Little Endian are provided, and so it should
+ * not normally be necessary to re-implement these. Efficient bit-twiddling
+ * techniques are used where possible, implemented in portable C.
+ *
+ * Note that these reference implementations rely on _mali_osk_clz() being
+ * implemented.
+ */
+
+/** @brief Clear a bit in a sequence of 32-bit words
+ * @param nr bit number to clear, starting from the (Little-endian) least
+ * significant bit
+ * @param addr starting point for counting.
+ */
+MALI_STATIC_INLINE void _mali_osk_clear_nonatomic_bit( u32 nr, u32 *addr )
+{
+	addr += nr >> 5; /* find the correct word */
+	nr = nr & ((1 << 5)-1); /* The bit number within the word */
+
+	_mali_internal_clear_bit( nr, addr );
+}
+
+/** @brief Set a bit in a sequence of 32-bit words
+ * @param nr bit number to set, starting from the (Little-endian) least
+ * significant bit
+ * @param addr starting point for counting.
+ */
+MALI_STATIC_INLINE void _mali_osk_set_nonatomic_bit( u32 nr, u32 *addr )
+{
+	addr += nr >> 5; /* find the correct word */
+	nr = nr & ((1 << 5)-1); /* The bit number within the word */
+
+	_mali_internal_set_bit( nr, addr );
+}
+
+/** @brief Test a bit in a sequence of 32-bit words
+ * @param nr bit number to test, starting from the (Little-endian) least
+ * significant bit
+ * @param addr starting point for counting.
+ * @return zero if bit was clear, non-zero if set. Do not rely on the return
+ * value being related to the actual word under test.
+ */
+MALI_STATIC_INLINE u32 _mali_osk_test_bit( u32 nr, u32 *addr )
+{
+	addr += nr >> 5; /* find the correct word */
+	nr = nr & ((1 << 5)-1); /* The bit number within the word */
+
+	return _mali_internal_test_bit( nr, *addr );
+}
+
+/* Return maxbit if not found */
+/** @brief Find the first zero bit in a sequence of 32-bit words
+ * @param addr starting point for search.
+ * @param maxbit the maximum number of bits to search
+ * @return the number of the first zero bit found, or maxbit if none were found
+ * in the specified range.
+ */
+MALI_STATIC_INLINE u32 _mali_osk_find_first_zero_bit( const u32 *addr, u32 maxbit )
+{
+	u32 total;
+
+	for ( total = 0; total < maxbit; total += 32, ++addr )
+	{
+		int result;
+		result = _mali_internal_find_first_zero_bit( *addr );
+
+		/* non-negative signifies the bit was found */
+		if ( result >= 0 )
+		{
+			total += (u32)result;
+			break;
+		}
+	}
+
+	/* Now check if we reached maxbit or above */
+	if ( total >= maxbit )
+	{
+		total = maxbit;
+	}
+
+	return total; /* either the found bit nr, or maxbit if not found */
+}
+/** @} */ /* end group _mali_osk_bitops */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_OSK_BITOPS_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_osk_list.h b/drivers/media/video/samsung/mali/common/mali_osk_list.h
new file mode 100644
index 0000000..3a562bb
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_osk_list.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_list.h
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#ifndef __MALI_OSK_LIST_H__
+#define __MALI_OSK_LIST_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+MALI_STATIC_INLINE void __mali_osk_list_add(_mali_osk_list_t *new_entry, _mali_osk_list_t *prev, _mali_osk_list_t *next)
+{
+    next->prev = new_entry;
+    new_entry->next = next;
+    new_entry->prev = prev;
+    prev->next = new_entry;
+}
+
+MALI_STATIC_INLINE void __mali_osk_list_del(_mali_osk_list_t *prev, _mali_osk_list_t *next)
+{
+    next->prev = prev;
+    prev->next = next;
+}
+
+/** @addtogroup _mali_osk_list
+ * @{ */
+
+/** Reference implementations of Doubly-linked Circular Lists are provided.
+ * There is often no need to re-implement these.
+ *
+ * @note The implementation may differ subtly from any lists the OS provides.
+ * For this reason, these lists should not be mixed with OS-specific lists
+ * inside the OSK/UKK implementation. */
+
+/** @brief Initialize a list element.
+ *
+ * All list elements must be initialized before use.
+ *
+ * Do not use on any list element that is present in a list without using
+ * _mali_osk_list_del first, otherwise this will break the list.
+ *
+ * @param list the list element to initialize
+ */
+MALI_STATIC_INLINE void _mali_osk_list_init( _mali_osk_list_t *list )
+{
+    list->next = list;
+    list->prev = list;
+}
+
+/** @brief Insert a single list element after an entry in a list
+ *
+ * As an example, if this is inserted to the head of a list, then this becomes
+ * the first element of the list.
+ *
+ * Do not use to move list elements from one list to another, as it will break
+ * the originating list.
+ *
+ *
+ * @param newlist the list element to insert
+ * @param list the list in which to insert. The new element will be the next
+ * entry in this list
+ */
+MALI_STATIC_INLINE void _mali_osk_list_add( _mali_osk_list_t *new_entry, _mali_osk_list_t *list )
+{
+    __mali_osk_list_add(new_entry, list, list->next);
+}
+
+/** @brief Insert a single list element before an entry in a list
+ *
+ * As an example, if this is inserted to the head of a list, then this becomes
+ * the last element of the list.
+ *
+ * Do not use to move list elements from one list to another, as it will break
+ * the originating list.
+ *
+ * @param newlist the list element to insert
+ * @param list the list in which to insert. The new element will be the previous
+ * entry in this list
+ */
+MALI_STATIC_INLINE void _mali_osk_list_addtail( _mali_osk_list_t *new_entry, _mali_osk_list_t *list )
+{
+    __mali_osk_list_add(new_entry, list->prev, list);
+}
+
+/** @brief Remove a single element from a list
+ *
+ * The element will no longer be present in the list. The removed list element
+ * will be uninitialized, and so should not be traversed. It must be
+ * initialized before further use.
+ *
+ * @param list the list element to remove.
+ */
+MALI_STATIC_INLINE void _mali_osk_list_del( _mali_osk_list_t *list )
+{
+    __mali_osk_list_del(list->prev, list->next);
+}
+
+/** @brief Remove a single element from a list, and re-initialize it
+ *
+ * The element will no longer be present in the list. The removed list element
+ * will initialized, and so can be used as normal.
+ *
+ * @param list the list element to remove and initialize.
+ */
+MALI_STATIC_INLINE void _mali_osk_list_delinit( _mali_osk_list_t *list )
+{
+    __mali_osk_list_del(list->prev, list->next);
+    _mali_osk_list_init(list);
+}
+
+/** @brief Determine whether a list is empty.
+ *
+ * An empty list is one that contains a single element that points to itself.
+ *
+ * @param list the list to check.
+ * @return non-zero if the list is empty, and zero otherwise.
+ */
+MALI_STATIC_INLINE int _mali_osk_list_empty( _mali_osk_list_t *list )
+{
+    return list->next == list;
+}
+
+/** @brief Move a list element from one list to another.
+ *
+ * The list element must be initialized.
+ *
+ * As an example, moving a list item to the head of a new list causes this item
+ * to be the first element in the new list.
+ *
+ * @param move the list element to move
+ * @param list the new list into which the element will be inserted, as the next
+ * element in the list.
+ */
+MALI_STATIC_INLINE void _mali_osk_list_move( _mali_osk_list_t *move_entry, _mali_osk_list_t *list )
+{
+    __mali_osk_list_del(move_entry->prev, move_entry->next);
+    _mali_osk_list_add(move_entry, list);
+}
+
+/** @brief Join two lists
+ *
+ * The list element must be initialized.
+ *
+ * Allows you to join a list into another list at a specific location
+ *
+ * @param list the new list to add
+ * @param at the location in a list to add the new list into
+ */
+MALI_STATIC_INLINE void _mali_osk_list_splice( _mali_osk_list_t *list, _mali_osk_list_t *at )
+{
+    if (!_mali_osk_list_empty(list))
+    {
+        /* insert all items from 'list' after 'at'  */
+        _mali_osk_list_t *first = list->next;
+        _mali_osk_list_t *last = list->prev;
+        _mali_osk_list_t *split = at->next;
+
+        first->prev = at;
+        at->next = first;
+
+        last->next  = split;
+        split->prev = last;
+    }
+}
+/** @} */ /* end group _mali_osk_list */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_OSK_LIST_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_osk_mali.h b/drivers/media/video/samsung/mali/common/mali_osk_mali.h
new file mode 100644
index 0000000..0b1d13a
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_osk_mali.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_mali.h
+ * Defines the OS abstraction layer which is specific for the Mali kernel device driver (OSK)
+ */
+
+#ifndef __MALI_OSK_MALI_H__
+#define __MALI_OSK_MALI_H__
+
+#include <mali_osk.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup _mali_osk_miscellaneous
+ * @{ */
+
+/** @brief Initialize the OSK layer
+ *
+ * This function is used to setup any initialization of OSK functionality, if
+ * required.
+ *
+ * This must be the first function called from the common code, specifically,
+ * from the common code entry-point, mali_kernel_constructor.
+ *
+ * The OS-integration into the OS's kernel must handle calling of
+ * mali_kernel_constructor when the device driver is loaded.
+ *
+ * @return _MALI_OSK_ERR_OK on success, or a suitable _mali_osk_errcode_t on
+ * failure.
+ */
+_mali_osk_errcode_t _mali_osk_init( void );
+
+/** @brief Terminate the OSK layer
+ *
+ * This function is used to terminate any resources initialized by
+ * _mali_osk_init.
+ *
+ * This must be the last function called from the common code, specifically,
+ * from the common code closedown function, mali_kernel_destructor, and the
+ * error path in mali_kernel_constructor.
+ *
+ * The OS-integration into the OS's kernel must handle calling of
+ * mali_kernel_destructor when the device driver is terminated.
+ */
+void _mali_osk_term( void );
+
+/** @brief Read the Mali Resource configuration
+ *
+ * Populates a _mali_arch_resource_t array from configuration settings, which
+ * are stored in an OS-specific way.
+ *
+ * For example, these may be compiled in to a static structure, or read from
+ * the filesystem at startup.
+ *
+ * On failure, do not call _mali_osk_resources_term.
+ *
+ * @param arch_config a pointer to the store the pointer to the resources
+ * @param num_resources the number of resources read
+ * @return _MALI_OSK_ERR_OK on success. _MALI_OSK_ERR_NOMEM on allocation
+ * error. For other failures, a suitable _mali_osk_errcode_t is returned.
+ */
+_mali_osk_errcode_t _mali_osk_resources_init( _mali_osk_resource_t **arch_config, u32 *num_resources );
+
+/** @brief Free resources allocated by _mali_osk_resources_init.
+ *
+ * Frees the _mali_arch_resource_t array allocated by _mali_osk_resources_init
+ *
+ * @param arch_config a pointer to the stored the pointer to the resources
+ * @param num_resources the number of resources in the array
+ */
+void _mali_osk_resources_term( _mali_osk_resource_t **arch_config, u32 num_resources);
+/** @} */ /* end group _mali_osk_miscellaneous */
+
+/** @addtogroup _mali_osk_low_level_memory
+ * @{ */
+
+/** @brief Initialize a user-space accessible memory range
+ *
+ * This initializes a virtual address range such that it is reserved for the
+ * current process, but does not map any physical pages into this range.
+ *
+ * This function may initialize or adjust any members of the
+ * mali_memory_allocation \a descriptor supplied, before the physical pages are
+ * mapped in with _mali_osk_mem_mapregion_map().
+ *
+ * The function will always be called with MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE
+ * set in \a descriptor->flags. It is an error to call this function without
+ * setting this flag. Otherwise, \a descriptor->flags bits are reserved for
+ * future expansion
+ *
+ * The \a descriptor's process_addr_mapping_info member can be modified to
+ * allocate OS-specific information. Note that on input, this will be a
+ * ukk_private word from the U/K inteface, as inserted by _mali_ukk_mem_mmap().
+ * This is used to pass information from the U/K interface to the OSK interface,
+ * if necessary. The precise usage of the process_addr_mapping_info member
+ * depends on the U/K implementation of _mali_ukk_mem_mmap().
+ *
+ * Therefore, the U/K implementation of _mali_ukk_mem_mmap() and the OSK
+ * implementation of  _mali_osk_mem_mapregion_init() must agree on the meaning and
+ * usage of the ukk_private word and process_addr_mapping_info member.
+ *
+ * Refer to \ref u_k_api for more information on the U/K interface.
+ *
+ * On successful return, \a descriptor's mapping member will be correct for
+ * use with _mali_osk_mem_mapregion_term() and _mali_osk_mem_mapregion_map().
+ *
+ * @param descriptor the mali_memory_allocation to initialize.
+ */
+_mali_osk_errcode_t _mali_osk_mem_mapregion_init( mali_memory_allocation * descriptor );
+
+/** @brief Terminate a user-space accessible memory range
+ *
+ * This terminates a virtual address range reserved in the current user process,
+ * where none, some or all of the virtual address ranges have mappings to
+ * physical pages.
+ *
+ * It will unmap any physical pages that had been mapped into a reserved
+ * virtual address range for the current process, and then releases the virtual
+ * address range. Any extra book-keeping information or resources allocated
+ * during _mali_osk_mem_mapregion_init() will also be released.
+ *
+ * The \a descriptor itself is not freed - this must be handled by the caller of
+ * _mali_osk_mem_mapregion_term().
+ *
+ * The function will always be called with MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE
+ * set in descriptor->flags. It is an error to call this function without
+ * setting this flag. Otherwise, descriptor->flags bits are reserved for
+ * future expansion
+ *
+ * @param descriptor the mali_memory_allocation to terminate.
+ */
+void _mali_osk_mem_mapregion_term( mali_memory_allocation * descriptor );
+
+/** @brief Map physical pages into a user process's virtual address range
+ *
+ * This is used to map a number of physically contigous pages into a
+ * user-process's virtual address range, which was previously reserved by a
+ * call to _mali_osk_mem_mapregion_init().
+ *
+ * This need not provide a mapping for the entire virtual address range
+ * reserved for \a descriptor - it may be used to map single pages per call.
+ *
+ * The function will always be called with MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE
+ * set in \a descriptor->flags. It is an error to call this function without
+ * setting this flag. Otherwise, \a descriptor->flags bits are reserved for
+ * future expansion
+ *
+ * The function may supply \a *phys_addr == \ref MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC.
+ * In this case, \a size must be set to \ref _MALI_OSK_CPU_PAGE_SIZE, and the function
+ * will allocate the physical page itself. The physical address of the
+ * allocated page will be returned through \a phys_addr.
+ *
+ * It is an error to set \a size != \ref _MALI_OSK_CPU_PAGE_SIZE while
+ * \a *phys_addr == \ref MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC,
+ * since it is not always possible for OSs to support such a setting through this
+ * interface.
+ *
+ * @note \b IMPORTANT: This code must validate the input parameters. If the
+ * range defined by \a offset and \a size is outside the range allocated in
+ * \a descriptor, then this function \b MUST not attempt any mapping, and must
+ * instead return a suitable \ref _mali_osk_errcode_t \b failure code.
+ *
+ * @param[in,out] descriptor the mali_memory_allocation representing the
+ * user-process's virtual address range to map into.
+ *
+ * @param[in] offset the offset into the virtual address range. This is only added
+ * to the mapping member of the \a descriptor, and not the \a phys_addr parameter.
+ * It must be a multiple of \ref _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * @param[in,out] phys_addr a pointer to the physical base address to begin the
+ * mapping from. If \a size == \ref _MALI_OSK_CPU_PAGE_SIZE and
+ * \a *phys_addr == \ref MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC, then this
+ * function will allocate the physical page itself, and return the
+ * physical address of the page through \a phys_addr, which will be aligned to
+ * \ref _MALI_OSK_CPU_PAGE_SIZE. Otherwise, \a *phys_addr must be aligned to
+ * \ref _MALI_OSK_CPU_PAGE_SIZE, and is unmodified after the call.
+ * \a phys_addr is unaffected by the \a offset parameter.
+ *
+ * @param[in] size the number of bytes to map in. This must be a multiple of
+ * \ref _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * @return _MALI_OSK_ERR_OK on sucess, otherwise a _mali_osk_errcode_t value
+ * on failure
+ *
+ * @note could expand to use _mali_osk_mem_mapregion_flags_t instead of
+ * \ref MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC, but note that we must
+ * also modify the mali process address manager in the mmu/memory engine code.
+ */
+_mali_osk_errcode_t _mali_osk_mem_mapregion_map( mali_memory_allocation * descriptor, u32 offset, u32 *phys_addr, u32 size );
+
+
+/** @brief Unmap physical pages from a user process's virtual address range
+ *
+ * This is used to unmap a number of physically contigous pages from a
+ * user-process's virtual address range, which were previously mapped by a
+ * call to _mali_osk_mem_mapregion_map(). If the range specified was allocated
+ * from OS memory, then that memory will be returned to the OS. Whilst pages
+ * will be mapped out, the Virtual address range remains reserved, and at the
+ * same base address.
+ *
+ * When this function is used to unmap pages from OS memory
+ * (_mali_osk_mem_mapregion_map() was called with *phys_addr ==
+ * \ref MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC), then the \a flags must
+ * include \ref _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR. This is because
+ * it is not always easy for an OS implementation to discover whether the
+ * memory was OS allocated or not (and so, how it should release the memory).
+ *
+ * For this reason, only a range of pages of the same allocation type (all OS
+ * allocated, or none OS allocacted) may be unmapped in one call. Multiple
+ * calls must be made if allocations of these different types exist across the
+ * entire region described by the \a descriptor.
+ *
+ * The function will always be called with MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE
+ * set in \a descriptor->flags. It is an error to call this function without
+ * setting this flag. Otherwise, \a descriptor->flags bits are reserved for
+ * future expansion
+ *
+ * @param[in,out] descriptor the mali_memory_allocation representing the
+ * user-process's virtual address range to map into.
+ *
+ * @param[in] offset the offset into the virtual address range. This is only added
+ * to the mapping member of the \a descriptor. \a offset must be a multiple of
+ * \ref _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * @param[in] size the number of bytes to unmap. This must be a multiple of
+ * \ref _MALI_OSK_CPU_PAGE_SIZE.
+ *
+ * @param[in] flags specifies how the memory should be unmapped. For a range
+ * of pages that were originally OS allocated, this must have
+ * \ref _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR set.
+ */
+void _mali_osk_mem_mapregion_unmap( mali_memory_allocation * descriptor, u32 offset, u32 size, _mali_osk_mem_mapregion_flags_t flags );
+/** @} */ /* end group _mali_osk_low_level_memory */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_OSK_MALI_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_uk_types.h b/drivers/media/video/samsung/mali/common/mali_uk_types.h
new file mode 100644
index 0000000..e114fa8
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_uk_types.h
@@ -0,0 +1,1176 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_uk_types.h
+ * Defines the types and constants used in the user-kernel interface
+ */
+
+#ifndef __MALI_UK_TYPES_H__
+#define __MALI_UK_TYPES_H__
+
+/*
+ * NOTE: Because this file can be included from user-side and kernel-side,
+ * it is up to the includee to ensure certain typedefs (e.g. u32) are already
+ * defined when #including this.
+ */
+#include "regs/mali_200_regs.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup uddapi Unified Device Driver (UDD) APIs
+ *
+ * @{
+ */
+
+/**
+ * @addtogroup u_k_api UDD User/Kernel Interface (U/K) APIs
+ *
+ * @{
+ */
+
+/** @defgroup _mali_uk_core U/K Core
+ * @{ */
+
+/** Definition of subsystem numbers, to assist in creating a unique identifier
+ * for each U/K call.
+ *
+ * @see _mali_uk_functions */
+typedef enum
+{
+    _MALI_UK_CORE_SUBSYSTEM,      /**< Core Group of U/K calls */
+    _MALI_UK_MEMORY_SUBSYSTEM,    /**< Memory Group of U/K calls */
+    _MALI_UK_PP_SUBSYSTEM,        /**< Fragment Processor Group of U/K calls */
+    _MALI_UK_GP_SUBSYSTEM,        /**< Vertex Processor Group of U/K calls */
+	_MALI_UK_PROFILING_SUBSYSTEM, /**< Profiling Group of U/K calls */
+    _MALI_UK_PMM_SUBSYSTEM,       /**< Power Management Module Group of U/K calls */
+	_MALI_UK_VSYNC_SUBSYSTEM,     /**< VSYNC Group of U/K calls */
+} _mali_uk_subsystem_t;
+
+/** Within a function group each function has its unique sequence number
+ * to assist in creating a unique identifier for each U/K call.
+ *
+ * An ordered pair of numbers selected from
+ * ( \ref _mali_uk_subsystem_t,\ref  _mali_uk_functions) will uniquely identify the
+ * U/K call across all groups of functions, and all functions. */
+typedef enum
+{
+	/** Core functions */
+
+    _MALI_UK_OPEN                    = 0, /**< _mali_ukk_open() */
+    _MALI_UK_CLOSE,                       /**< _mali_ukk_close() */
+    _MALI_UK_GET_SYSTEM_INFO_SIZE,        /**< _mali_ukk_get_system_info_size() */
+    _MALI_UK_GET_SYSTEM_INFO,             /**< _mali_ukk_get_system_info() */
+    _MALI_UK_WAIT_FOR_NOTIFICATION,       /**< _mali_ukk_wait_for_notification() */
+    _MALI_UK_GET_API_VERSION,             /**< _mali_ukk_get_api_version() */
+    _MALI_UK_POST_NOTIFICATION,           /**< _mali_ukk_post_notification() */
+
+	/** Memory functions */
+
+    _MALI_UK_INIT_MEM                = 0, /**< _mali_ukk_init_mem() */
+    _MALI_UK_TERM_MEM,                    /**< _mali_ukk_term_mem() */
+    _MALI_UK_GET_BIG_BLOCK,               /**< _mali_ukk_get_big_block() */
+    _MALI_UK_FREE_BIG_BLOCK,              /**< _mali_ukk_free_big_block() */
+    _MALI_UK_MAP_MEM,                     /**< _mali_ukk_mem_mmap() */
+    _MALI_UK_UNMAP_MEM,                   /**< _mali_ukk_mem_munmap() */
+    _MALI_UK_QUERY_MMU_PAGE_TABLE_DUMP_SIZE, /**< _mali_ukk_mem_get_mmu_page_table_dump_size() */
+    _MALI_UK_DUMP_MMU_PAGE_TABLE,         /**< _mali_ukk_mem_dump_mmu_page_table() */
+    _MALI_UK_ATTACH_UMP_MEM,             /**< _mali_ukk_attach_ump_mem() */
+    _MALI_UK_RELEASE_UMP_MEM,           /**< _mali_ukk_release_ump_mem() */
+    _MALI_UK_MAP_EXT_MEM,                 /**< _mali_uku_map_external_mem() */
+    _MALI_UK_UNMAP_EXT_MEM,               /**< _mali_uku_unmap_external_mem() */
+    _MALI_UK_VA_TO_MALI_PA,               /**< _mali_uku_va_to_mali_pa() */
+
+    /** Common functions for each core */
+
+    _MALI_UK_START_JOB           = 0,     /**< Start a Fragment/Vertex Processor Job on a core */
+	_MALI_UK_ABORT_JOB,                   /**< Abort a job */
+    _MALI_UK_GET_NUMBER_OF_CORES,         /**< Get the number of Fragment/Vertex Processor cores */
+    _MALI_UK_GET_CORE_VERSION,            /**< Get the Fragment/Vertex Processor version compatible with all cores */
+
+    /** Fragment Processor Functions  */
+
+    _MALI_UK_PP_START_JOB            = _MALI_UK_START_JOB,            /**< _mali_ukk_pp_start_job() */
+    _MALI_UK_PP_ABORT_JOB            = _MALI_UK_ABORT_JOB,            /**< _mali_ukk_pp_abort_job() */
+    _MALI_UK_GET_PP_NUMBER_OF_CORES  = _MALI_UK_GET_NUMBER_OF_CORES,  /**< _mali_ukk_get_pp_number_of_cores() */
+    _MALI_UK_GET_PP_CORE_VERSION     = _MALI_UK_GET_CORE_VERSION,     /**< _mali_ukk_get_pp_core_version() */
+
+    /** Vertex Processor Functions  */
+
+    _MALI_UK_GP_START_JOB            = _MALI_UK_START_JOB,            /**< _mali_ukk_gp_start_job() */
+    _MALI_UK_GP_ABORT_JOB            = _MALI_UK_ABORT_JOB,            /**< _mali_ukk_gp_abort_job() */
+    _MALI_UK_GET_GP_NUMBER_OF_CORES  = _MALI_UK_GET_NUMBER_OF_CORES,  /**< _mali_ukk_get_gp_number_of_cores() */
+    _MALI_UK_GET_GP_CORE_VERSION     = _MALI_UK_GET_CORE_VERSION,     /**< _mali_ukk_get_gp_core_version() */
+    _MALI_UK_GP_SUSPEND_RESPONSE,                                     /**< _mali_ukk_gp_suspend_response() */
+
+	/** Profiling functions */
+
+	_MALI_UK_PROFILING_START         = 0, /**< __mali_uku_profiling_start() */
+	_MALI_UK_PROFILING_ADD_EVENT,         /**< __mali_uku_profiling_add_event() */
+	_MALI_UK_PROFILING_STOP,              /**< __mali_uku_profiling_stop() */
+	_MALI_UK_PROFILING_GET_EVENT,         /**< __mali_uku_profiling_get_event() */
+	_MALI_UK_PROFILING_CLEAR,             /**< __mali_uku_profiling_clear() */
+	_MALI_UK_PROFILING_GET_CONFIG,        /**< __mali_uku_profiling_get_config() */
+	_MALI_UK_TRANSFER_SW_COUNTERS,
+
+#if USING_MALI_PMM
+    /** Power Management Module Functions */
+    _MALI_UK_PMM_EVENT_MESSAGE = 0,       /**< Raise an event message */
+#endif
+
+	/** VSYNC reporting fuctions */
+	_MALI_UK_VSYNC_EVENT_REPORT      = 0, /**< _mali_ukk_vsync_event_report() */
+
+} _mali_uk_functions;
+
+/** @brief Get the size necessary for system info
+ *
+ * @see _mali_ukk_get_system_info_size()
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 size;                       /**< [out] size of buffer necessary to hold system information data, in bytes */
+} _mali_uk_get_system_info_size_s;
+
+
+/** @defgroup _mali_uk_getsysteminfo U/K Get System Info
+ * @{ */
+
+/**
+ * Type definition for the core version number.
+ * Used when returning the version number read from a core
+ *
+ * Its format is that of the 32-bit Version register for a particular core.
+ * Refer to the "Mali200 and MaliGP2 3D Graphics Processor Technical Reference
+ * Manual", ARM DDI 0415C, for more information.
+ */
+typedef u32 _mali_core_version;
+
+/**
+ * Enum values for the different modes the driver can be put in.
+ * Normal is the default mode. The driver then uses a job queue and takes job objects from the clients.
+ * Job completion is reported using the _mali_ukk_wait_for_notification call.
+ * The driver blocks this io command until a job has completed or failed or a timeout occurs.
+ *
+ * The 'raw' mode is reserved for future expansion.
+ */
+typedef enum _mali_driver_mode
+{
+	_MALI_DRIVER_MODE_RAW = 1,    /**< Reserved for future expansion */
+	_MALI_DRIVER_MODE_NORMAL = 2  /**< Normal mode of operation */
+} _mali_driver_mode;
+
+/** @brief List of possible cores
+ *
+ * add new entries to the end of this enum */
+typedef enum _mali_core_type
+{
+	_MALI_GP2 = 2,                /**< MaliGP2 Programmable Vertex Processor */
+	_MALI_200 = 5,                /**< Mali200 Programmable Fragment Processor */
+	_MALI_400_GP = 6,             /**< Mali400 Programmable Vertex Processor */
+	_MALI_400_PP = 7,             /**< Mali400 Programmable Fragment Processor */
+	/* insert new core here, do NOT alter the existing values */
+} _mali_core_type;
+
+/** @brief Information about each Mali Core
+ *
+ * Information is stored in a linked list, which is stored entirely in the
+ * buffer pointed to by the system_info member of the
+ * _mali_uk_get_system_info_s arguments provided to _mali_ukk_get_system_info()
+ *
+ * Both Fragment Processor (PP) and Vertex Processor (GP) cores are represented
+ * by this struct.
+ *
+ * The type is reported by the type field, _mali_core_info::_mali_core_type.
+ *
+ * Each core is given a unique Sequence number identifying it, the core_nr
+ * member.
+ *
+ * Flags are taken directly from the resource's flags, and are currently unused.
+ *
+ * Multiple mali_core_info structs are linked in a single linked list using the next field
+ */
+typedef struct _mali_core_info
+{
+	_mali_core_type type;            /**< Type of core */
+	_mali_core_version version;      /**< Core Version, as reported by the Core's Version Register */
+	u32 reg_address;                 /**< Address of Registers */
+	u32 core_nr;                     /**< Sequence number */
+	u32 flags;                       /**< Flags. Currently Unused. */
+	struct _mali_core_info * next;   /**< Next core in Linked List */
+} _mali_core_info;
+
+/** @brief Capabilities of Memory Banks
+ *
+ * These may be used to restrict memory banks for certain uses. They may be
+ * used when access is not possible (e.g. Bus does not support access to it)
+ * or when access is possible but not desired (e.g. Access is slow).
+ *
+ * In the case of 'possible but not desired', there is no way of specifying
+ * the flags as an optimization hint, so that the memory could be used as a
+ * last resort.
+ *
+ * @see _mali_mem_info
+ */
+typedef enum _mali_bus_usage
+{
+
+	_MALI_PP_READABLE   = (1<<0),  /** Readable by the Fragment Processor */
+	_MALI_PP_WRITEABLE  = (1<<1),  /** Writeable by the Fragment Processor */
+	_MALI_GP_READABLE   = (1<<2),  /** Readable by the Vertex Processor */
+	_MALI_GP_WRITEABLE  = (1<<3),  /** Writeable by the Vertex Processor */
+	_MALI_CPU_READABLE  = (1<<4),  /** Readable by the CPU */
+	_MALI_CPU_WRITEABLE = (1<<5),  /** Writeable by the CPU */
+	_MALI_MMU_READABLE  = _MALI_PP_READABLE | _MALI_GP_READABLE,   /** Readable by the MMU (including all cores behind it) */
+	_MALI_MMU_WRITEABLE = _MALI_PP_WRITEABLE | _MALI_GP_WRITEABLE, /** Writeable by the MMU (including all cores behind it) */
+} _mali_bus_usage;
+
+/** @brief Information about the Mali Memory system
+ *
+ * Information is stored in a linked list, which is stored entirely in the
+ * buffer pointed to by the system_info member of the
+ * _mali_uk_get_system_info_s arguments provided to _mali_ukk_get_system_info()
+ *
+ * Each element of the linked list describes a single Mali Memory bank.
+ * Each allocation can only come from one bank, and will not cross multiple
+ * banks.
+ *
+ * Each bank is uniquely identified by its identifier member. On Mali-nonMMU
+ * systems, to allocate from this bank, the value of identifier must be passed
+ * as the type_id member of the  _mali_uk_get_big_block_s arguments to
+ * _mali_ukk_get_big_block.
+ *
+ * On Mali-MMU systems, there is only one bank, which describes the maximum
+ * possible address range that could be allocated (which may be much less than
+ * the available physical memory)
+ *
+ * The flags member describes the capabilities of the memory. It is an error
+ * to attempt to build a job for a particular core (PP or GP) when the memory
+ * regions used do not have the capabilities for supporting that core. This
+ * would result in a job abort from the Device Driver.
+ *
+ * For example, it is correct to build a PP job where read-only data structures
+ * are taken from a memory with _MALI_PP_READABLE set and
+ * _MALI_PP_WRITEABLE clear, and a framebuffer with  _MALI_PP_WRITEABLE set and
+ * _MALI_PP_READABLE clear. However, it would be incorrect to use a framebuffer
+ * where _MALI_PP_WRITEABLE is clear.
+ */
+typedef struct _mali_mem_info
+{
+	u32 size;                     /**< Size of the memory bank in bytes */
+	_mali_bus_usage flags;        /**< Capabilitiy flags of the memory */
+	u32 maximum_order_supported;  /**< log2 supported size */
+	u32 identifier;               /**< Unique identifier, to be used in allocate calls */
+	struct _mali_mem_info * next; /**< Next List Link */
+} _mali_mem_info;
+
+/** @brief Info about the whole Mali system.
+ *
+ * This Contains a linked list of the cores and memory banks available. Each
+ * list pointer will remain inside the system_info buffer supplied in the
+ * _mali_uk_get_system_info_s arguments to a _mali_ukk_get_system_info call.
+ *
+ * The has_mmu member must be inspected to ensure the correct group of
+ * Memory function calls is obtained - that is, those for either Mali-MMU
+ * or Mali-nonMMU. @see _mali_uk_memory
+ */
+typedef struct _mali_system_info
+{
+	_mali_core_info * core_info;  /**< List of _mali_core_info structures */
+	_mali_mem_info * mem_info;    /**< List of _mali_mem_info structures */
+	u32 has_mmu;                  /**< Non-zero if Mali-MMU present. Zero otherwise. */
+	_mali_driver_mode drivermode; /**< Reserved. Must always be _MALI_DRIVER_MODE_NORMAL */
+} _mali_system_info;
+
+/** @brief Arguments to _mali_ukk_get_system_info()
+ *
+ * A buffer of the size returned by _mali_ukk_get_system_info_size() must be
+ * allocated, and the pointer to this buffer must be written into the
+ * system_info member. The buffer must be suitably aligned for storage of
+ * the _mali_system_info structure - for example, one returned by
+ * _mali_osk_malloc(), which will be suitably aligned for any structure.
+ *
+ * The ukk_private member must be set to zero by the user-side. Under an OS
+ * implementation, the U/K interface must write in the user-side base address
+ * into the ukk_private member, so that the common code in
+ * _mali_ukk_get_system_info() can determine how to adjust the pointers such
+ * that they are sensible from user space. Leaving ukk_private as NULL implies
+ * that no pointer adjustment is necessary - which will be the case on a
+ * bare-metal/RTOS system.
+ *
+ * @see _mali_system_info
+ */
+typedef struct
+{
+    void *ctx;                              /**< [in,out] user-kernel context (trashed on output) */
+	u32 size;                               /**< [in] size of buffer provided to store system information data */
+	_mali_system_info * system_info;        /**< [in,out] pointer to buffer to store system information data. No initialisation of buffer required on input. */
+	u32 ukk_private;                        /**< [in] Kernel-side private word inserted by certain U/K interface implementations. Caller must set to Zero. */
+} _mali_uk_get_system_info_s;
+/** @} */ /* end group _mali_uk_getsysteminfo */
+
+/** @} */ /* end group _mali_uk_core */
+
+
+/** @defgroup _mali_uk_gp U/K Vertex Processor
+ * @{ */
+
+/** @defgroup _mali_uk_gp_suspend_response_s Vertex Processor Suspend Response
+ * @{ */
+
+/** @brief Arguments for _mali_ukk_gp_suspend_response()
+ *
+ * When _mali_wait_for_notification() receives notification that a
+ * Vertex Processor job was suspended, you need to send a response to indicate
+ * what needs to happen with this job. You can either abort or resume the job.
+ *
+ * - set @c code to indicate response code. This is either @c _MALIGP_JOB_ABORT or
+ * @c _MALIGP_JOB_RESUME_WITH_NEW_HEAP to indicate you will provide a new heap
+ * for the job that will resolve the out of memory condition for the job.
+ * - copy the @c cookie value from the @c _mali_uk_gp_job_suspended_s notification;
+ * this is an identifier for the suspended job
+ * - set @c arguments[0] and @c arguments[1] to zero if you abort the job. If
+ * you resume it, @c argument[0] should specify the Mali start address for the new
+ * heap and @c argument[1] the Mali end address of the heap.
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ *
+ */
+typedef enum _maligp_job_suspended_response_code
+{
+	_MALIGP_JOB_ABORT,                  /**< Abort the Vertex Processor job */
+	_MALIGP_JOB_RESUME_WITH_NEW_HEAP    /**< Resume the Vertex Processor job with a new heap */
+} _maligp_job_suspended_response_code;
+
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 cookie;                     /**< [in] cookie from the _mali_uk_gp_job_suspended_s notification */
+	_maligp_job_suspended_response_code code; /**< [in] abort or resume response code, see \ref _maligp_job_suspended_response_code */
+	u32 arguments[2];               /**< [in] 0 when aborting a job. When resuming a job, the Mali start and end address for a new heap to resume the job with */
+} _mali_uk_gp_suspend_response_s;
+
+/** @} */ /* end group _mali_uk_gp_suspend_response_s */
+
+/** @defgroup _mali_uk_gpstartjob_s Vertex Processor Start Job
+ * @{ */
+
+/** @brief Status indicating the result of starting a Vertex or Fragment processor job */
+typedef enum
+{
+    _MALI_UK_START_JOB_STARTED,                         /**< Job started */
+    _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED,    /**< Job started and bumped a lower priority job that was pending execution */
+    _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE           /**< Job could not be started at this time. Try starting the job again */
+} _mali_uk_start_job_status;
+
+/** @brief Status indicating the result of starting a Vertex or Fragment processor job */
+typedef enum
+{
+	MALI_UK_START_JOB_FLAG_DEFAULT = 0,          /**< Default behaviour; Flush L2 caches before start, no following jobs */
+	MALI_UK_START_JOB_FLAG_NO_FLUSH = 1,         /**< No need to flush L2 caches before start */
+	MALI_UK_START_JOB_FLAG_MORE_JOBS_FOLLOW = 2, /**< More related jobs follows, try to schedule them as soon as possible after this job */
+} _mali_uk_start_job_flags;
+
+/** @brief Status indicating the result of the execution of a Vertex or Fragment processor job  */
+
+typedef enum
+{
+	_MALI_UK_JOB_STATUS_END_SUCCESS         = 1<<(16+0),
+	_MALI_UK_JOB_STATUS_END_OOM             = 1<<(16+1),
+	_MALI_UK_JOB_STATUS_END_ABORT           = 1<<(16+2),
+	_MALI_UK_JOB_STATUS_END_TIMEOUT_SW      = 1<<(16+3),
+	_MALI_UK_JOB_STATUS_END_HANG            = 1<<(16+4),
+	_MALI_UK_JOB_STATUS_END_SEG_FAULT       = 1<<(16+5),
+	_MALI_UK_JOB_STATUS_END_ILLEGAL_JOB     = 1<<(16+6),
+	_MALI_UK_JOB_STATUS_END_UNKNOWN_ERR     = 1<<(16+7),
+	_MALI_UK_JOB_STATUS_END_SHUTDOWN        = 1<<(16+8),
+	_MALI_UK_JOB_STATUS_END_SYSTEM_UNUSABLE = 1<<(16+9)
+} _mali_uk_job_status;
+
+#define MALIGP2_NUM_REGS_FRAME (6)
+
+/** @brief Arguments for _mali_ukk_gp_start_job()
+ *
+ * To start a Vertex Processor job
+ * - associate the request with a reference to a @c mali_gp_job_info by setting
+ * user_job_ptr to the address of the @c mali_gp_job_info of the job.
+ * - set @c priority to the priority of the @c mali_gp_job_info
+ * - specify a timeout for the job by setting @c watchdog_msecs to the number of
+ * milliseconds the job is allowed to run. Specifying a value of 0 selects the
+ * default timeout in use by the device driver.
+ * - copy the frame registers from the @c mali_gp_job_info into @c frame_registers.
+ * - set the @c perf_counter_flag, @c perf_counter_src0 and @c perf_counter_src1 to zero
+ * for a non-instrumented build. For an instrumented build you can use up
+ * to two performance counters. Set the corresponding bit in @c perf_counter_flag
+ * to enable them. @c perf_counter_src0 and @c perf_counter_src1 specify
+ * the source of what needs to get counted (e.g. number of vertex loader
+ * cache hits). For source id values, see ARM DDI0415A, Table 3-60.
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ *
+ * When @c _mali_ukk_gp_start_job() returns @c _MALI_OSK_ERR_OK, status contains the
+ * result of the request (see \ref _mali_uk_start_job_status). If the job could
+ * not get started (@c _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE) it should be
+ * tried again. If the job had a higher priority than the one currently pending
+ * execution (@c _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED), it will bump
+ * the lower priority job and returns the address of the @c mali_gp_job_info
+ * for that job in @c returned_user_job_ptr. That job should get requeued.
+ *
+ * After the job has started, @c _mali_wait_for_notification() will be notified
+ * that the job finished or got suspended. It may get suspended due to
+ * resource shortage. If it finished (see _mali_ukk_wait_for_notification())
+ * the notification will contain a @c _mali_uk_gp_job_finished_s result. If
+ * it got suspended the notification will contain a @c _mali_uk_gp_job_suspended_s
+ * result.
+ *
+ * The @c _mali_uk_gp_job_finished_s contains the job status (see \ref _mali_uk_job_status),
+ * the number of milliseconds the job took to render, and values of core registers
+ * when the job finished (irq status, performance counters, renderer list
+ * address). A job has finished succesfully when its status is
+ * @c _MALI_UK_JOB_STATUS_FINISHED. If the hardware detected a timeout while rendering
+ * the job, or software detected the job is taking more than watchdog_msecs to
+ * complete, the status will indicate @c _MALI_UK_JOB_STATUS_HANG.
+ * If the hardware detected a bus error while accessing memory associated with the
+ * job, status will indicate @c _MALI_UK_JOB_STATUS_SEG_FAULT.
+ * status will indicate @c _MALI_UK_JOB_STATUS_NOT_STARTED if the driver had to
+ * stop the job but the job didn't start on the hardware yet, e.g. when the
+ * driver shutdown.
+ *
+ * In case the job got suspended, @c _mali_uk_gp_job_suspended_s contains
+ * the @c user_job_ptr identifier used to start the job with, the @c reason
+ * why the job stalled (see \ref _maligp_job_suspended_reason) and a @c cookie
+ * to identify the core on which the job stalled.  This @c cookie will be needed
+ * when responding to this nofication by means of _mali_ukk_gp_suspend_response().
+ * (see _mali_ukk_gp_suspend_response()). The response is either to abort or
+ * resume the job. If the job got suspended due to an out of memory condition
+ * you may be able to resolve this by providing more memory and resuming the job.
+ *
+ */
+typedef struct
+{
+    void *ctx;                          /**< [in,out] user-kernel context (trashed on output) */
+    u32 user_job_ptr;                   /**< [in] identifier for the job in user space, a @c mali_gp_job_info* */
+    u32 priority;                       /**< [in] job priority. A lower number means higher priority */
+    u32 watchdog_msecs;                 /**< [in] maximum allowed runtime in milliseconds. The job gets killed if it runs longer than this. A value of 0 selects the default used by the device driver. */
+    u32 frame_registers[MALIGP2_NUM_REGS_FRAME]; /**< [in] core specific registers associated with this job */
+    u32 perf_counter_flag;              /**< [in] bitmask indicating which performance counters to enable, see \ref _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE and related macro definitions */
+    u32 perf_counter_src0;              /**< [in] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter_src1;              /**< [in] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
+    u32 returned_user_job_ptr;          /**< [out] identifier for the returned job in user space, a @c mali_gp_job_info* */
+    _mali_uk_start_job_status status;   /**< [out] indicates job start status (success, previous job returned, requeue) */
+	u32 abort_id;                       /**< [in] abort id of this job, used to identify this job for later abort requests */
+	u32 perf_counter_l2_src0;           /**< [in] soruce id for Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_src1;           /**< [in] source id for Mali-400 MP L2 cache performance counter 1 */
+	u32 frame_builder_id;				/**< [in] id of the originating frame builder */
+	u32 flush_id;						/**< [in] flush id within the originating frame builder */
+} _mali_uk_gp_start_job_s;
+
+#define _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE (1<<0) /**< Enable performance counter SRC0 for a job */
+#define _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE (1<<1) /**< Enable performance counter SRC1 for a job */
+#define _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE (1<<2) /**< Enable performance counter L2_SRC0 for a job */
+#define _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE (1<<3) /**< Enable performance counter L2_SRC1 for a job */
+#define _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET       (1<<4) /**< Enable performance counter L2_RESET for a job */
+
+/** @} */ /* end group _mali_uk_gpstartjob_s */
+
+typedef struct
+{
+    u32 user_job_ptr;               /**< [out] identifier for the job in user space */
+    _mali_uk_job_status status;     /**< [out] status of finished job */
+    u32 irq_status;                 /**< [out] value of the GP interrupt rawstat register (see ARM DDI0415A) */
+    u32 status_reg_on_stop;         /**< [out] value of the GP control register */
+    u32 vscl_stop_addr;             /**< [out] value of the GP VLSCL start register */
+    u32 plbcl_stop_addr;            /**< [out] value of the GP PLBCL start register */
+    u32 heap_current_addr;          /**< [out] value of the GP PLB PL heap start address register */
+    u32 perf_counter_src0;          /**< [out] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter_src1;          /**< [out] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter0;              /**< [out] value of perfomance counter 0 (see ARM DDI0415A) */
+    u32 perf_counter1;              /**< [out] value of perfomance counter 1 (see ARM DDI0415A) */
+    u32 render_time;                /**< [out] number of microseconds it took for the job to render */
+	u32 perf_counter_l2_src0;       /**< [out] soruce id for Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_src1;       /**< [out] soruce id for Mali-400 MP L2 cache performance counter 1 */
+	u32 perf_counter_l2_val0;       /**< [out] Value of the Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_val1;       /**< [out] Value of the Mali-400 MP L2 cache performance counter 1 */
+} _mali_uk_gp_job_finished_s;
+
+typedef enum _maligp_job_suspended_reason
+{
+	_MALIGP_JOB_SUSPENDED_OUT_OF_MEMORY  /**< Polygon list builder unit (PLBU) has run out of memory */
+} _maligp_job_suspended_reason;
+
+typedef struct
+{
+	u32 user_job_ptr;                    /**< [out] identifier for the job in user space */
+	_maligp_job_suspended_reason reason; /**< [out] reason why the job stalled */
+	u32 cookie;                          /**< [out] identifier for the core in kernel space on which the job stalled */
+} _mali_uk_gp_job_suspended_s;
+
+/** @} */ /* end group _mali_uk_gp */
+
+
+/** @defgroup _mali_uk_pp U/K Fragment Processor
+ * @{ */
+
+/** @defgroup _mali_uk_ppstartjob_s Fragment Processor Start Job
+ * @{ */
+
+/** @brief Arguments for _mali_ukk_pp_start_job()
+ *
+ * To start a Fragment Processor job
+ * - associate the request with a reference to a mali_pp_job by setting
+ * @c user_job_ptr to the address of the @c mali_pp_job of the job.
+ * - set @c priority to the priority of the mali_pp_job
+ * - specify a timeout for the job by setting @c watchdog_msecs to the number of
+ * milliseconds the job is allowed to run. Specifying a value of 0 selects the
+ * default timeout in use by the device driver.
+ * - copy the frame registers from the @c mali_pp_job into @c frame_registers.
+ * For MALI200 you also need to copy the write back 0,1 and 2 registers.
+ * - set the @c perf_counter_flag, @c perf_counter_src0 and @c perf_counter_src1 to zero
+ * for a non-instrumented build. For an instrumented build you can use up
+ * to two performance counters. Set the corresponding bit in @c perf_counter_flag
+ * to enable them. @c perf_counter_src0 and @c perf_counter_src1 specify
+ * the source of what needs to get counted (e.g. number of vertex loader
+ * cache hits). For source id values, see ARM DDI0415A, Table 3-60.
+ * - pass in the user-kernel context in @c ctx that was returned from _mali_ukk_open()
+ *
+ * When _mali_ukk_pp_start_job() returns @c _MALI_OSK_ERR_OK, @c status contains the
+ * result of the request (see \ref _mali_uk_start_job_status). If the job could
+ * not get started (@c _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE) it should be
+ * tried again. If the job had a higher priority than the one currently pending
+ * execution (@c _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED), it will bump
+ * the lower priority job and returns the address of the @c mali_pp_job
+ * for that job in @c returned_user_job_ptr. That job should get requeued.
+ *
+ * After the job has started, _mali_wait_for_notification() will be notified
+ * when the job finished. The notification will contain a
+ * @c _mali_uk_pp_job_finished_s result. It contains the @c user_job_ptr
+ * identifier used to start the job with, the job @c status (see \ref _mali_uk_job_status),
+ * the number of milliseconds the job took to render, and values of core registers
+ * when the job finished (irq status, performance counters, renderer list
+ * address). A job has finished succesfully when its status is
+ * @c _MALI_UK_JOB_STATUS_FINISHED. If the hardware detected a timeout while rendering
+ * the job, or software detected the job is taking more than @c watchdog_msecs to
+ * complete, the status will indicate @c _MALI_UK_JOB_STATUS_HANG.
+ * If the hardware detected a bus error while accessing memory associated with the
+ * job, status will indicate @c _MALI_UK_JOB_STATUS_SEG_FAULT.
+ * status will indicate @c _MALI_UK_JOB_STATUS_NOT_STARTED if the driver had to
+ * stop the job but the job didn't start on the hardware yet, e.g. when the
+ * driver shutdown.
+ *
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    u32 user_job_ptr;               /**< [in] identifier for the job in user space */
+    u32 priority;                   /**< [in] job priority. A lower number means higher priority */
+    u32 watchdog_msecs;             /**< [in] maximum allowed runtime in milliseconds. The job gets killed if it runs longer than this. A value of 0 selects the default used by the device driver. */
+    u32 frame_registers[MALI200_NUM_REGS_FRAME]; /**< [in] core specific registers associated with this job, see ARM DDI0415A */
+    u32 wb0_registers[MALI200_NUM_REGS_WBx];
+    u32 wb1_registers[MALI200_NUM_REGS_WBx];
+    u32 wb2_registers[MALI200_NUM_REGS_WBx];
+    u32 perf_counter_flag;              /**< [in] bitmask indicating which performance counters to enable, see \ref _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE and related macro definitions */
+    u32 perf_counter_src0;              /**< [in] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter_src1;              /**< [in] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
+    u32 returned_user_job_ptr;          /**< [out] identifier for the returned job in user space */
+    _mali_uk_start_job_status status;   /**< [out] indicates job start status (success, previous job returned, requeue) */
+	u32 abort_id;                       /**< [in] abort id of this job, used to identify this job for later abort requests */
+	u32 perf_counter_l2_src0;           /**< [in] soruce id for Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_src1;           /**< [in] source id for Mali-400 MP L2 cache performance counter 1 */
+	u32 frame_builder_id;				/**< [in] id of the originating frame builder */
+	u32 flush_id;						/**< [in] flush id within the originating frame builder */
+	_mali_uk_start_job_flags flags;     /**< [in] Flags for job, see _mali_uk_start_job_flags for more information */
+} _mali_uk_pp_start_job_s;
+/** @} */ /* end group _mali_uk_ppstartjob_s */
+
+typedef struct
+{
+    u32 user_job_ptr;               /**< [out] identifier for the job in user space */
+    _mali_uk_job_status status;     /**< [out] status of finished job */
+    u32 irq_status;                 /**< [out] value of interrupt rawstat register (see ARM DDI0415A) */
+    u32 last_tile_list_addr;        /**< [out] value of renderer list register (see ARM DDI0415A); necessary to restart a stopped job */
+    u32 perf_counter_src0;          /**< [out] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter_src1;          /**< [out] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
+    u32 perf_counter0;              /**< [out] value of perfomance counter 0 (see ARM DDI0415A) */
+    u32 perf_counter1;              /**< [out] value of perfomance counter 1 (see ARM DDI0415A) */
+    u32 render_time;                /**< [out] number of microseconds it took for the job to render */
+	u32 perf_counter_l2_src0;       /**< [out] soruce id for Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_src1;       /**< [out] soruce id for Mali-400 MP L2 cache performance counter 1 */
+	u32 perf_counter_l2_val0;       /**< [out] Value of the Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_val1;       /**< [out] Value of the Mali-400 MP L2 cache performance counter 1 */
+	u32 perf_counter_l2_val0_raw;   /**< [out] Raw value of the Mali-400 MP L2 cache performance counter 0 */
+	u32 perf_counter_l2_val1_raw;   /**< [out] Raw value of the Mali-400 MP L2 cache performance counter 1 */
+} _mali_uk_pp_job_finished_s;
+/** @} */ /* end group _mali_uk_pp */
+
+
+/** @addtogroup _mali_uk_core U/K Core
+ * @{ */
+
+/** @defgroup _mali_uk_waitfornotification_s Wait For Notification
+ * @{ */
+
+/** @brief Notification type encodings
+ *
+ * Each Notification type is an ordered pair of (subsystem,id), and is unique.
+ *
+ * The encoding of subsystem,id into a 32-bit word is:
+ * encoding = (( subsystem << _MALI_NOTIFICATION_SUBSYSTEM_SHIFT ) & _MALI_NOTIFICATION_SUBSYSTEM_MASK)
+ *            | (( id <<  _MALI_NOTIFICATION_ID_SHIFT ) & _MALI_NOTIFICATION_ID_MASK)
+ *
+ * @see _mali_uk_wait_for_notification_s
+ */
+typedef enum
+{
+	/** core notifications */
+
+	_MALI_NOTIFICATION_CORE_SHUTDOWN_IN_PROGRESS =  (_MALI_UK_CORE_SUBSYSTEM << 16) | 0x20,
+	_MALI_NOTIFICATION_APPLICATION_QUIT =           (_MALI_UK_CORE_SUBSYSTEM << 16) | 0x40,
+
+	/** Fragment Processor notifications */
+
+	_MALI_NOTIFICATION_PP_FINISHED =                (_MALI_UK_PP_SUBSYSTEM << 16) | 0x10,
+
+	/** Vertex Processor notifications */
+
+	_MALI_NOTIFICATION_GP_FINISHED =                (_MALI_UK_GP_SUBSYSTEM << 16) | 0x10,
+	_MALI_NOTIFICATION_GP_STALLED =                 (_MALI_UK_GP_SUBSYSTEM << 16) | 0x20,
+} _mali_uk_notification_type;
+
+/** to assist in splitting up 32-bit notification value in subsystem and id value */
+#define _MALI_NOTIFICATION_SUBSYSTEM_MASK 0xFFFF0000
+#define _MALI_NOTIFICATION_SUBSYSTEM_SHIFT 16
+#define _MALI_NOTIFICATION_ID_MASK 0x0000FFFF
+#define _MALI_NOTIFICATION_ID_SHIFT 0
+
+
+/** @brief Arguments for _mali_ukk_wait_for_notification()
+ *
+ * On successful return from _mali_ukk_wait_for_notification(), the members of
+ * this structure will indicate the reason for notification.
+ *
+ * Specifically, the source of the notification can be identified by the
+ * subsystem and id fields of the mali_uk_notification_type in the code.type
+ * member. The type member is encoded in a way to divide up the types into a
+ * subsystem field, and a per-subsystem ID field. See
+ * _mali_uk_notification_type for more information.
+ *
+ * Interpreting the data union member depends on the notification type:
+ *
+ * - type == _MALI_NOTIFICATION_CORE_SHUTDOWN_IN_PROGRESS
+ *     - The kernel side is shutting down. No further
+ * _mali_uk_wait_for_notification() calls should be made.
+ *     - In this case, the value of the data union member is undefined.
+ *     - This is used to indicate to the user space client that it should close
+ * the connection to the Mali Device Driver.
+ * - type == _MALI_NOTIFICATION_PP_FINISHED
+ *    - The notification data is of type _mali_uk_pp_job_finished_s. It contains the user_job_ptr
+ * identifier used to start the job with, the job status, the number of milliseconds the job took to render,
+ * and values of core registers when the job finished (irq status, performance counters, renderer list
+ * address).
+ *    - A job has finished succesfully when its status member is _MALI_UK_JOB_STATUS_FINISHED.
+ *    - If the hardware detected a timeout while rendering the job, or software detected the job is
+ * taking more than watchdog_msecs (see _mali_ukk_pp_start_job()) to complete, the status member will
+ * indicate _MALI_UK_JOB_STATUS_HANG.
+ *    - If the hardware detected a bus error while accessing memory associated with the job, status will
+ * indicate _MALI_UK_JOB_STATUS_SEG_FAULT.
+ *    - Status will indicate MALI_UK_JOB_STATUS_NOT_STARTED if the driver had to stop the job but the job
+ * didn't start the hardware yet, e.g. when the driver closes.
+ * - type == _MALI_NOTIFICATION_GP_FINISHED
+ *     - The notification data is of type _mali_uk_gp_job_finished_s. The notification is similar to that of
+ * type == _MALI_NOTIFICATION_PP_FINISHED, except that several other GP core register values are returned.
+ * The status values have the same meaning for type == _MALI_NOTIFICATION_PP_FINISHED.
+ * - type == _MALI_NOTIFICATION_GP_STALLED
+ *     - The nofication data is of type _mali_uk_gp_job_suspended_s. It contains the user_job_ptr
+ * identifier used to start the job with, the reason why the job stalled and a cookie to identify the core on
+ * which the job stalled.
+ *     - The reason member of gp_job_suspended is set to _MALIGP_JOB_SUSPENDED_OUT_OF_MEMORY
+ * when the polygon list builder unit has run out of memory.
+ */
+typedef struct
+{
+    void *ctx;                       /**< [in,out] user-kernel context (trashed on output) */
+	_mali_uk_notification_type type; /**< [out] Type of notification available */
+    union
+    {
+        _mali_uk_gp_job_suspended_s gp_job_suspended;/**< [out] Notification data for _MALI_NOTIFICATION_GP_STALLED notification type */
+        _mali_uk_gp_job_finished_s  gp_job_finished; /**< [out] Notification data for _MALI_NOTIFICATION_GP_FINISHED notification type */
+        _mali_uk_pp_job_finished_s  pp_job_finished; /**< [out] Notification data for _MALI_NOTIFICATION_PP_FINISHED notification type */
+    } data;
+} _mali_uk_wait_for_notification_s;
+
+/** @brief Arguments for _mali_ukk_post_notification()
+ *
+ * Posts the specified notification to the notification queue for this application.
+ * This is used to send a quit message to the callback thread.
+ */
+typedef struct
+{
+    void *ctx;                       /**< [in,out] user-kernel context (trashed on output) */
+	_mali_uk_notification_type type; /**< [in] Type of notification to post */
+} _mali_uk_post_notification_s;
+/** @} */ /* end group _mali_uk_waitfornotification_s */
+
+/** @defgroup _mali_uk_getapiversion_s Get API Version
+ * @{ */
+
+/** helpers for Device Driver API version handling */
+
+/** @brief Encode a version ID from a 16-bit input
+ *
+ * @note the input is assumed to be 16 bits. It must not exceed 16 bits. */
+#define _MAKE_VERSION_ID(x) (((x) << 16UL) | (x))
+
+/** @brief Check whether a 32-bit value is likely to be Device Driver API
+ * version ID. */
+#define _IS_VERSION_ID(x) (((x) & 0xFFFF) == (((x) >> 16UL) & 0xFFFF))
+
+/** @brief Decode a 16-bit version number from a 32-bit Device Driver API version
+ * ID */
+#define _GET_VERSION(x) (((x) >> 16UL) & 0xFFFF)
+
+/** @brief Determine whether two 32-bit encoded version IDs match */
+#define _IS_API_MATCH(x, y) (IS_VERSION_ID((x)) && IS_VERSION_ID((y)) && (GET_VERSION((x)) == GET_VERSION((y))))
+
+/**
+ * API version define.
+ * Indicates the version of the kernel API
+ * The version is a 16bit integer incremented on each API change.
+ * The 16bit integer is stored twice in a 32bit integer
+ * For example, for version 1 the value would be 0x00010001
+ */
+#define _MALI_API_VERSION 10
+#define _MALI_UK_API_VERSION _MAKE_VERSION_ID(_MALI_API_VERSION)
+
+/**
+ * The API version is a 16-bit integer stored in both the lower and upper 16-bits
+ * of a 32-bit value. The 16-bit API version value is incremented on each API
+ * change. Version 1 would be 0x00010001. Used in _mali_uk_get_api_version_s.
+ */
+typedef u32 _mali_uk_api_version;
+
+/** @brief Arguments for _mali_uk_get_api_version()
+ *
+ * The user-side interface version must be written into the version member,
+ * encoded using _MAKE_VERSION_ID(). It will be compared to the API version of
+ * the kernel-side interface.
+ *
+ * On successful return, the version member will be the API version of the
+ * kernel-side interface. _MALI_UK_API_VERSION macro defines the current version
+ * of the API.
+ *
+ * The compatible member must be checked to see if the version of the user-side
+ * interface is compatible with the kernel-side interface, since future versions
+ * of the interface may be backwards compatible.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	_mali_uk_api_version version;   /**< [in,out] API version of user-side interface. */
+	int compatible;                 /**< [out] @c 1 when @version is compatible, @c 0 otherwise */
+} _mali_uk_get_api_version_s;
+/** @} */ /* end group _mali_uk_getapiversion_s */
+
+/** @} */ /* end group _mali_uk_core */
+
+
+/** @defgroup _mali_uk_memory U/K Memory
+ * @{ */
+
+/** @brief Arguments for _mali_ukk_init_mem(). */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 mali_address_base;          /**< [out] start of MALI address space */
+	u32 memory_size;                /**< [out] total MALI address space available */
+} _mali_uk_init_mem_s;
+
+/** @brief Arguments for _mali_ukk_term_mem(). */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+} _mali_uk_term_mem_s;
+
+/** @brief Arguments for _mali_ukk_get_big_block()
+ *
+ * - type_id should be set to the value of the identifier member of one of the
+ * _mali_mem_info structures returned through _mali_ukk_get_system_info()
+ * - ukk_private must be zero when calling from user-side. On Kernel-side, the
+ * OS implementation of the U/K interface can use it to communicate data to the
+ * OS implementation of the OSK layer. Specifically, ukk_private will be placed
+ * into the ukk_private member of the _mali_uk_mem_mmap_s structure. See
+ * _mali_ukk_mem_mmap() for more details.
+ * - minimum_size_requested will be updated if it is too small
+ * - block_size will always be >= minimum_size_requested, because the underlying
+ * allocation mechanism may only be able to divide up memory regions in certain
+ * ways. To avoid wasting memory, block_size should always be taken into account
+ * rather than assuming minimum_size_requested was really allocated.
+ * - to free the memory, the returned cookie member must be stored, and used to
+ * refer to it.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 type_id;                    /**< [in] the type id of the memory bank to allocate memory from */
+	u32 minimum_size_requested;     /**< [in,out] minimum size of the allocation */
+	u32 ukk_private;                /**< [in] Kernel-side private word inserted by certain U/K interface implementations. Caller must set to Zero. */
+	u32 mali_address;               /**< [out] address of the allocation in mali address space */
+	void *cpuptr;                   /**< [out] address of the allocation in the current process address space */
+	u32 block_size;                 /**< [out] size of the block that got allocated */
+	u32 flags;                      /**< [out] flags associated with the allocated block, of type _mali_bus_usage */
+	u32 cookie;                     /**< [out] identifier for the allocated block in kernel space  */
+} _mali_uk_get_big_block_s;
+
+/** @brief Arguments for _mali_ukk_free_big_block()
+ *
+ * All that is required is that the cookie member must be set to the value of
+ * the cookie member returned through _mali_ukk_get_big_block()
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 cookie;                     /**< [in] identifier for mapped memory object in kernel space  */
+} _mali_uk_free_big_block_s;
+
+/** @note Mali-MMU only */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 phys_addr;                  /**< [in] physical address */
+	u32 size;                       /**< [in] size */
+	u32 mali_address;               /**< [in] mali address to map the physical memory to */
+	u32 rights;                     /**< [in] rights necessary for accessing memory */
+	u32 flags;                      /**< [in] flags, see \ref _MALI_MAP_EXTERNAL_MAP_GUARD_PAGE */
+	u32 cookie;                     /**< [out] identifier for mapped memory object in kernel space  */
+} _mali_uk_map_external_mem_s;
+
+/** Flag for _mali_uk_map_external_mem_s and _mali_uk_attach_ump_mem_s */
+#define _MALI_MAP_EXTERNAL_MAP_GUARD_PAGE (1<<0)
+
+/** @note Mali-MMU only */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 cookie;                     /**< [out] identifier for mapped memory object in kernel space  */
+} _mali_uk_unmap_external_mem_s;
+
+/** @note This is identical to _mali_uk_map_external_mem_s above, however phys_addr is replaced by secure_id */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 secure_id;                  /**< [in] secure id */
+	u32 size;                       /**< [in] size */
+	u32 mali_address;               /**< [in] mali address to map the physical memory to */
+	u32 rights;                     /**< [in] rights necessary for accessing memory */
+	u32 flags;                      /**< [in] flags, see \ref _MALI_MAP_EXTERNAL_MAP_GUARD_PAGE */
+	u32 cookie;                     /**< [out] identifier for mapped memory object in kernel space  */
+} _mali_uk_attach_ump_mem_s;
+
+/** @note Mali-MMU only; will be supported in future version */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 cookie;                     /**< [in] identifier for mapped memory object in kernel space  */
+} _mali_uk_release_ump_mem_s;
+
+/** @brief Arguments for _mali_ukk_va_to_mali_pa()
+ *
+ * if size is zero or not a multiple of the system's page size, it will be
+ * rounded up to the next multiple of the page size. This will occur before
+ * any other use of the size parameter.
+ *
+ * if va is not PAGE_SIZE aligned, it will be rounded down to the next page
+ * boundary.
+ *
+ * The range (va) to ((u32)va)+(size-1) inclusive will be checked for physical
+ * contiguity.
+ *
+ * The implementor will check that the entire physical range is allowed to be mapped
+ * into user-space.
+ *
+ * Failure will occur if either of the above are not satisfied.
+ *
+ * Otherwise, the physical base address of the range is returned through pa,
+ * va is updated to be page aligned, and size is updated to be a non-zero
+ * multiple of the system's pagesize.
+ */
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	void *va;                       /**< [in,out] Virtual address of the start of the range */
+	u32 pa;                         /**< [out] Physical base address of the range */
+	u32 size;                       /**< [in,out] Size of the range, in bytes. */
+} _mali_uk_va_to_mali_pa_s;
+
+
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 size;                       /**< [out] size of MMU page table information (registers + page tables) */
+} _mali_uk_query_mmu_page_table_dump_size_s;
+
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 size;                       /**< [in] size of buffer to receive mmu page table information */
+    void *buffer;                   /**< [in,out] buffer to receive mmu page table information */
+    u32 register_writes_size;       /**< [out] size of MMU register dump */
+	u32 *register_writes;           /**< [out] pointer within buffer where MMU register dump is stored */
+	u32 page_table_dump_size;       /**< [out] size of MMU page table dump */
+	u32 *page_table_dump;           /**< [out] pointer within buffer where MMU page table dump is stored */
+} _mali_uk_dump_mmu_page_table_s;
+
+/** @} */ /* end group _mali_uk_memory */
+
+
+/** @addtogroup _mali_uk_pp U/K Fragment Processor
+ * @{ */
+
+/** @brief Arguments for _mali_ukk_get_pp_number_of_cores()
+ *
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ * - Upon successful return from _mali_ukk_get_pp_number_of_cores(), @c number_of_cores
+ * will contain the number of Fragment Processor cores in the system.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    u32 number_of_cores;            /**< [out] number of Fragment Processor cores in the system */
+} _mali_uk_get_pp_number_of_cores_s;
+
+/** @brief Arguments for _mali_ukk_get_pp_core_version()
+ *
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ * - Upon successful return from _mali_ukk_get_pp_core_version(), @c version contains
+ * the version that all Fragment Processor cores are compatible with.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    _mali_core_version version;     /**< [out] version returned from core, see \ref _mali_core_version  */
+} _mali_uk_get_pp_core_version_s;
+
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    u32 abort_id;                   /**< [in] ID of job(s) to abort */
+} _mali_uk_pp_abort_job_s;
+
+/** @} */ /* end group _mali_uk_pp */
+
+
+/** @addtogroup _mali_uk_gp U/K Vertex Processor
+ * @{ */
+
+/** @brief Arguments for _mali_ukk_get_gp_number_of_cores()
+ *
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ * - Upon successful return from _mali_ukk_get_gp_number_of_cores(), @c number_of_cores
+ * will contain the number of Vertex Processor cores in the system.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    u32 number_of_cores;            /**< [out] number of Vertex Processor cores in the system */
+} _mali_uk_get_gp_number_of_cores_s;
+
+/** @brief Arguments for _mali_ukk_get_gp_core_version()
+ *
+ * - pass in the user-kernel context @c ctx that was returned from _mali_ukk_open()
+ * - Upon successful return from _mali_ukk_get_gp_core_version(), @c version contains
+ * the version that all Vertex Processor cores are compatible with.
+ */
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    _mali_core_version version;     /**< [out] version returned from core, see \ref _mali_core_version */
+} _mali_uk_get_gp_core_version_s;
+
+typedef struct
+{
+    void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+    u32 abort_id;                   /**< [in] ID of job(s) to abort */
+} _mali_uk_gp_abort_job_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 limit;                      /**< [in,out] The desired limit for number of events to record on input, actual limit on output */
+} _mali_uk_profiling_start_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 event_id;                   /**< [in] event id to register (see  enum mali_profiling_events for values) */
+	u32 data[5];                    /**< [in] event specific data */
+} _mali_uk_profiling_add_event_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 count;                      /**< [out] The number of events sampled */
+} _mali_uk_profiling_stop_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 index;                      /**< [in] which index to get (starting at zero) */
+	u64 timestamp;                  /**< [out] timestamp of event */
+	u32 event_id;                   /**< [out] event id of event (see  enum mali_profiling_events for values) */
+	u32 data[5];                    /**< [out] event specific data */
+} _mali_uk_profiling_get_event_s;
+
+typedef struct
+{
+	void *ctx;
+
+	u32 id;
+	s64 value;
+} _mali_uk_sw_counters_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+} _mali_uk_profiling_clear_s;
+
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	u32 enable_events;              /**< [out] 1 if user space process should generate events, 0 if not */
+} _mali_uk_profiling_get_config_s;
+
+
+/** @} */ /* end group _mali_uk_gp */
+
+
+/** @addtogroup _mali_uk_memory U/K Memory
+ * @{ */
+
+/** @brief Arguments to _mali_ukk_mem_mmap()
+ *
+ * Use of the phys_addr member depends on whether the driver is compiled for
+ * Mali-MMU or nonMMU:
+ * - in the nonMMU case, this is the physical address of the memory as seen by
+ * the CPU (which may be a constant offset from that used by Mali)
+ * - in the MMU case, this is the Mali Virtual base address of the memory to
+ * allocate, and the particular physical pages used to back the memory are
+ * entirely determined by _mali_ukk_mem_mmap(). The details of the physical pages
+ * are not reported to user-space for security reasons.
+ *
+ * The cookie member must be stored for use later when freeing the memory by
+ * calling _mali_ukk_mem_munmap(). In the Mali-MMU case, the cookie is secure.
+ *
+ * The ukk_private word must be set to zero when calling from user-space. On
+ * Kernel-side, the  OS implementation of the U/K interface can use it to
+ * communicate data to the OS implementation of the OSK layer. In particular,
+ * _mali_ukk_get_big_block() directly calls _mali_ukk_mem_mmap directly, and
+ * will communicate its own ukk_private word through the ukk_private member
+ * here. The common code itself will not inspect or modify the ukk_private
+ * word, and so it may be safely used for whatever purposes necessary to
+ * integrate Mali Memory handling into the OS.
+ *
+ * The uku_private member is currently reserved for use by the user-side
+ * implementation of the U/K interface. Its value must be zero.
+ */
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	void *mapping;                  /**< [out] Returns user-space virtual address for the mapping */
+	u32 size;                       /**< [in] Size of the requested mapping */
+	u32 phys_addr;                  /**< [in] Physical address - could be offset, depending on caller+callee convention */
+	u32 cookie;                     /**< [out] Returns a cookie for use in munmap calls */
+	void *uku_private;              /**< [in] User-side Private word used by U/K interface */
+	void *ukk_private;              /**< [in] Kernel-side Private word used by U/K interface */
+} _mali_uk_mem_mmap_s;
+
+/** @brief Arguments to _mali_ukk_mem_munmap()
+ *
+ * The cookie and mapping members must be that returned from the same previous
+ * call to _mali_ukk_mem_mmap(). The size member must correspond to cookie
+ * and mapping - that is, it must be the value originally supplied to a call to
+ * _mali_ukk_mem_mmap that returned the values of mapping and cookie.
+ *
+ * An error will be returned if an attempt is made to unmap only part of the
+ * originally obtained range, or to unmap more than was originally obtained.
+ */
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	void *mapping;                  /**< [in] The mapping returned from mmap call */
+	u32 size;                       /**< [in] The size passed to mmap call */
+	u32 cookie;                     /**< [in] Cookie from mmap call */
+} _mali_uk_mem_munmap_s;
+/** @} */ /* end group _mali_uk_memory */
+
+#if USING_MALI_PMM
+
+/** @defgroup _mali_uk_pmm U/K Power Management Module
+ * @{ */
+
+/** @brief Power management event message identifiers.
+ *
+ * U/K events start after id 200, and can range up to 999
+ * Adding new events will require updates to the PMM mali_pmm_event_id type
+ */
+#define _MALI_PMM_EVENT_UK_EXAMPLE 201
+
+/** @brief Generic PMM message data type, that will be dependent on the event msg
+ */
+typedef u32 mali_pmm_message_data;
+
+
+/** @brief Arguments to _mali_ukk_pmm_event_message()
+ */
+typedef struct
+{
+	void *ctx;                          /**< [in,out] user-kernel context (trashed on output) */
+	u32 id;                             /**< [in] event id */
+	mali_pmm_message_data data;         /**< [in] specific data associated with the event */
+} _mali_uk_pmm_message_s;
+
+/** @} */ /* end group _mali_uk_pmm */
+#endif /* USING_MALI_PMM */
+
+/** @defgroup _mali_uk_vsync U/K VSYNC Wait Reporting Module
+ * @{ */
+
+/** @brief VSYNC events
+ *
+ * These events are reported when DDK starts to wait for vsync and when the
+ * vsync has occured and the DDK can continue on the next frame.
+ */
+typedef enum _mali_uk_vsync_event
+{
+	_MALI_UK_VSYNC_EVENT_BEGIN_WAIT = 0,
+	_MALI_UK_VSYNC_EVENT_END_WAIT
+} _mali_uk_vsync_event;
+
+/** @brief Arguments to _mali_ukk_vsync_event()
+ *
+ */
+typedef struct
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	_mali_uk_vsync_event event;     /**< [in] VSYNCH event type */
+} _mali_uk_vsync_event_report_s;
+
+/** @} */ /* end group _mali_uk_vsync */
+
+/** @} */ /* end group u_k_api */
+
+/** @} */ /* end group uddapi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_UK_TYPES_H__ */
diff --git a/drivers/media/video/samsung/mali/common/mali_ukk.h b/drivers/media/video/samsung/mali/common/mali_ukk.h
new file mode 100644
index 0000000..94efdf5
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/mali_ukk.h
@@ -0,0 +1,723 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_ukk.h
+ * Defines the kernel-side interface of the user-kernel interface
+ */
+
+#ifndef __MALI_UKK_H__
+#define __MALI_UKK_H__
+
+#include "mali_osk.h"
+#include "mali_uk_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup uddapi Unified Device Driver (UDD) APIs
+ *
+ * @{
+ */
+
+/**
+ * @addtogroup u_k_api UDD User/Kernel Interface (U/K) APIs
+ *
+ * - The _mali_uk functions are an abstraction of the interface to the device
+ * driver. On certain OSs, this would be implemented via the IOCTL interface.
+ * On other OSs, it could be via extension of some Device Driver Class, or
+ * direct function call for Bare metal/RTOSs.
+ * - It is important to note that:
+ *   -  The Device Driver has implemented the _mali_ukk set of functions
+ *   -  The Base Driver calls the corresponding set of _mali_uku functions.
+ * - What requires porting is solely the calling mechanism from User-side to
+ * Kernel-side, and propagating back the results.
+ * - Each U/K function is associated with a (group, number) pair from
+ * \ref _mali_uk_functions to make it possible for a common function in the
+ * Base Driver and Device Driver to route User/Kernel calls from/to the
+ * correct _mali_uk function. For example, in an IOCTL system, the IOCTL number
+ * would be formed based on the group and number assigned to the _mali_uk
+ * function, as listed in \ref _mali_uk_functions. On the user-side, each
+ * _mali_uku function would just make an IOCTL with the IOCTL-code being an
+ * encoded form of the (group, number) pair. On the kernel-side, the Device
+ * Driver's IOCTL handler decodes the IOCTL-code back into a (group, number)
+ * pair, and uses this to determine which corresponding _mali_ukk should be
+ * called.
+ *   - Refer to \ref _mali_uk_functions for more information about this
+ * (group, number) pairing.
+ * - In a system where there is no distinction between user and kernel-side,
+ * the U/K interface may be implemented as:@code
+ * MALI_STATIC_INLINE _mali_osk_errcode_t _mali_uku_examplefunction( _mali_uk_examplefunction_s *args )
+ * {
+ *     return mali_ukk_examplefunction( args );
+ * }
+ * @endcode
+ * - Therefore, all U/K calls behave \em as \em though they were direct
+ * function calls (but the \b implementation \em need \em not be a direct
+ * function calls)
+ *
+ * @note Naming the _mali_uk functions the same on both User and Kernel sides
+ * on non-RTOS systems causes debugging issues when setting breakpoints. In
+ * this case, it is not clear which function the breakpoint is put on.
+ * Therefore the _mali_uk functions in user space are prefixed with \c _mali_uku
+ * and in kernel space with \c _mali_ukk. The naming for the argument
+ * structures is unaffected.
+ *
+ * - The _mali_uk functions are synchronous.
+ * - Arguments to the _mali_uk functions are passed in a structure. The only
+ * parameter passed to the _mali_uk functions is a pointer to this structure.
+ * This first member of this structure, ctx, is a pointer to a context returned
+ * by _mali_uku_open(). For example:@code
+ * typedef struct
+ * {
+ *     void *ctx;
+ *     u32 number_of_cores;
+ * } _mali_uk_get_gp_number_of_cores_s;
+ * @endcode
+ *
+ * - Each _mali_uk function has its own argument structure named after the
+ *  function. The argument is distinguished by the _s suffix.
+ * - The argument types are defined by the base driver and user-kernel
+ *  interface.
+ * - All _mali_uk functions return a standard \ref _mali_osk_errcode_t.
+ * - Only arguments of type input or input/output need be initialized before
+ * calling a _mali_uk function.
+ * - Arguments of type output and input/output are only valid when the
+ * _mali_uk function returns \ref _MALI_OSK_ERR_OK.
+ * - The \c ctx member is always invalid after it has been used by a
+ * _mali_uk function, except for the context management functions
+ *
+ *
+ * \b Interface \b restrictions
+ *
+ * The requirements of the interface mean that an implementation of the
+ * User-kernel interface may do no 'real' work. For example, the following are
+ * illegal in the User-kernel implementation:
+ * - Calling functions necessary for operation on all systems,  which would
+ * not otherwise get called on RTOS systems.
+ *     - For example, a  U/K interface that calls multiple _mali_ukk functions
+ * during one particular U/K call. This could not be achieved by the same code
+ * which uses direct function calls for the U/K interface.
+ * -  Writing in values to the args members, when otherwise these members would
+ * not hold a useful value for a direct function call U/K interface.
+ *     - For example, U/K interface implementation that take NULL members in
+ * their arguments structure from the user side, but those members are
+ * replaced with non-NULL values in the kernel-side of the U/K interface
+ * implementation. A scratch area for writing data is one such example. In this
+ * case, a direct function call U/K interface would segfault, because no code
+ * would be present to replace the NULL pointer with a meaningful pointer.
+ *     - Note that we discourage the case where the U/K implementation changes
+ * a NULL argument member to non-NULL, and then the Device Driver code (outside
+ * of the U/K layer) re-checks this member for NULL, and corrects it when
+ * necessary. Whilst such code works even on direct function call U/K
+ * intefaces, it reduces the testing coverage of the Device Driver code. This
+ * is because we have no way of testing the NULL == value path on an OS
+ * implementation.
+ *
+ * A number of allowable examples exist where U/K interfaces do 'real' work:
+ * - The 'pointer switching' technique for \ref _mali_ukk_get_system_info
+ *     - In this case, without the pointer switching on direct function call
+ * U/K interface, the Device Driver code still sees the same thing: a pointer
+ * to which it can write memory. This is because such a system has no
+ * distinction between a user and kernel pointer.
+ * - Writing an OS-specific value into the ukk_private member for
+ * _mali_ukk_mem_mmap().
+ *     - In this case, this value is passed around by Device Driver code, but
+ * its actual value is never checked. Device Driver code simply passes it from
+ * the U/K layer to the OSK layer, where it can be acted upon. In this case,
+ * \em some OS implementations of the U/K (_mali_ukk_mem_mmap()) and OSK
+ * (_mali_osk_mem_mapregion_init()) functions will collaborate on the
+ *  meaning of ukk_private member. On other OSs, it may be unused by both
+ * U/K and OSK layers
+ * - On OS systems (not including direct function call U/K interface
+ * implementations), _mali_ukk_get_big_block() may succeed, but the subsequent
+ * copying to user space may fail.
+ *     - A problem scenario exists: some memory has been reserved by
+ * _mali_ukk_get_big_block(), but the user-mode will be unaware of it (it will
+ * never receive any information about this memory). In this case, the U/K
+ * implementation must do everything necessary to 'rollback' the \em atomic
+ * _mali_ukk_get_big_block() transaction.
+ *     - Therefore, on error inside the U/K interface implementation itself,
+ * it will be as though the _mali_ukk function itself had failed, and cleaned
+ * up after itself.
+ *     - Compare this to a direct function call U/K implementation, where all
+ * error cleanup is handled by the _mali_ukk function itself. The direct
+ * function call U/K interface implementation is automatically atomic.
+ *
+ * The last example highlights a consequence of all U/K interface
+ * implementations: they must be atomic with respect to the Device Driver code.
+ * And therefore, should Device Driver code succeed but the U/K implementation
+ * fail afterwards (but before return to user-space), then the U/K
+ * implementation must cause appropriate cleanup actions to preserve the
+ * atomicity of the interface.
+ *
+ * @{
+ */
+
+
+/** @defgroup _mali_uk_context U/K Context management
+ *
+ * These functions allow for initialisation of the user-kernel interface once per process.
+ *
+ * Generally the context will store the OS specific object to communicate with the kernel device driver and further
+ * state information required by the specific implementation. The context is shareable among all threads in the caller process.
+ *
+ * On IOCTL systems, this is likely to be a file descriptor as a result of opening the kernel device driver.
+ *
+ * On a bare-metal/RTOS system with no distinction between kernel and
+ * user-space, the U/K interface simply calls the _mali_ukk variant of the
+ * function by direct function call. In this case, the context returned is the
+ * mali_session_data from _mali_ukk_open().
+ *
+ * The kernel side implementations of the U/K interface expect the first member of the argument structure to
+ * be the context created by _mali_uku_open(). On some OS implementations, the meaning of this context
+ * will be different between user-side and kernel-side. In which case, the kernel-side will need to replace this context
+ * with the kernel-side equivalent, because user-side will not have access to kernel-side data. The context parameter
+ * in the argument structure therefore has to be of type input/output.
+ *
+ * It should be noted that the caller cannot reuse the \c ctx member of U/K
+ * argument structure after a U/K call, because it may be overwritten. Instead,
+ * the context handle must always be stored  elsewhere, and copied into
+ * the appropriate U/K argument structure for each user-side call to
+ * the U/K interface. This is not usually a problem, since U/K argument
+ * structures are usually placed on the stack.
+ *
+ * @{ */
+
+/** @brief Begin a new Mali Device Driver session
+ *
+ * This is used to obtain a per-process context handle for all future U/K calls.
+ *
+ * @param context pointer to storage to return a (void*)context handle.
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_open( void **context );
+
+/** @brief End a Mali Device Driver session
+ *
+ * This should be called when the process no longer requires use of the Mali Device Driver.
+ *
+ * The context handle must not be used after it has been closed.
+ *
+ * @param context pointer to a stored (void*)context handle.
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_close( void **context );
+
+/** @} */ /* end group _mali_uk_context */
+
+
+/** @addtogroup _mali_uk_core U/K Core
+ *
+ * The core functions provide the following functionality:
+ * - verify that the user and kernel API are compatible
+ * - retrieve information about the cores and memory banks in the system
+ * - wait for the result of jobs started on a core
+ *
+ * @{ */
+
+/** @brief Returns the size of the buffer needed for a _mali_ukk_get_system_info call
+ *
+ * This function must be called before a call is made to
+ * _mali_ukk_get_system_info, so that memory of the correct size can be
+ * allocated, and a pointer to this memory written into the system_info member
+ * of _mali_uk_get_system_info_s.
+ *
+ * @param args see _mali_uk_get_system_info_size_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_system_info_size( _mali_uk_get_system_info_size_s *args );
+
+/** @brief Returns information about the system (cores and memory banks)
+ *
+ * A buffer for this needs to be allocated by the caller. The size of the buffer required is returned by
+ * _mali_ukk_get_system_info_size(). The user is responsible for freeing the buffer.
+ *
+ * The _mali_system_info structure will be written to the start of this buffer,
+ * and the core_info and mem_info lists will be written to locations inside
+ * the buffer, and will be suitably aligned.
+ *
+ * Under OS implementations of the U/K interface we need to pack/unpack
+ * pointers across the user/kernel boundary. This has required that we malloc()
+ * an intermediate buffer inside the kernel-side U/K interface, and free it
+ * before returning to user-side. To avoid modifying common code, we do the
+ * following pseudo-code, which we shall call 'pointer switching':
+ *
+ * @code
+ * {
+ *     Copy_From_User(kargs, args, ... );
+ *     void __user * local_ptr = kargs->system_info;
+ *     kargs->system_info = _mali_osk_malloc( ... );
+ *     _mali_ukk_get_system_info( kargs );
+ *     Copy_To_User( local_ptr, kargs->system_info, ... );
+ *     _mali_osk_free( kargs->system_info );
+ * }
+ * @endcode
+ * @note The user-side's args->system_info members was unmodified here.
+ *
+ * However, the current implementation requires an extra ukk_private word so that the common code can work out
+ * how to patch pointers to user-mode for an OS's U/K implementation, this should be set to the user-space
+ * destination address for pointer-patching to occur. When NULL, it is unused, an no pointer-patching occurs in the
+ * common code.
+ *
+ * @param args see _mali_uk_get_system_info_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_system_info( _mali_uk_get_system_info_s *args );
+
+/** @brief Waits for a job notification.
+ *
+ * Sleeps until notified or a timeout occurs. Returns information about the notification.
+ *
+ * @param args see _mali_uk_wait_for_notification_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_wait_for_notification( _mali_uk_wait_for_notification_s *args );
+
+/** @brief Post a notification to the notification queue of this application.
+ *
+ * @param args see _mali_uk_post_notification_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_post_notification( _mali_uk_post_notification_s *args );
+
+/** @brief Verifies if the user and kernel side of this API are compatible.
+ *
+ * @param args see _mali_uk_get_api_version_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_api_version( _mali_uk_get_api_version_s *args );
+/** @} */ /* end group _mali_uk_core */
+
+
+/** @addtogroup _mali_uk_memory U/K Memory
+ *
+ * The memory functions provide functionality with and without a Mali-MMU present.
+ *
+ * For Mali-MMU based systems, the following functionality is provided:
+ * - Initialize and terminate MALI virtual address space
+ * - Allocate/deallocate physical memory to a MALI virtual address range and map into/unmap from the
+ * current process address space
+ * - Map/unmap external physical memory into the MALI virtual address range
+ *
+ * For Mali-nonMMU based systems:
+ * - Allocate/deallocate MALI memory
+ *
+ * @{ */
+
+/**
+ * @brief Initialize the Mali-MMU Memory system
+ *
+ * For Mali-MMU builds of the drivers, this function must be called before any
+ * other functions in the \ref _mali_uk_memory group are called.
+ *
+ * @note This function is for Mali-MMU builds \b only. It should not be called
+ * when the drivers are built without Mali-MMU support.
+ *
+ * @param args see \ref _mali_uk_init_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable
+ * _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_init_mem( _mali_uk_init_mem_s *args );
+
+/**
+ * @brief Terminate the MMU Memory system
+ *
+ * For Mali-MMU builds of the drivers, this function must be called when
+ * functions in the \ref _mali_uk_memory group will no longer be called. This
+ * function must be called before the application terminates.
+ *
+ * @note This function is for Mali-MMU builds \b only. It should not be called
+ * when the drivers are built without Mali-MMU support.
+ *
+ * @param args see \ref _mali_uk_term_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable
+ * _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_term_mem( _mali_uk_term_mem_s *args );
+
+/** @brief Map a block of memory into the current user process
+ *
+ * Allocates a minimum of minimum_size_requested bytes of MALI memory and maps it into the current
+ * process space. The number of bytes allocated is returned in args->block_size.
+ *
+ * This is only used for Mali-nonMMU mode.
+ *
+ * @param args see _mali_uk_get_big_block_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_big_block( _mali_uk_get_big_block_s *args );
+
+/** @brief Unmap a block of memory from the current user process
+ *
+ * Frees allocated MALI memory and unmaps it from the current process space. The previously allocated memory
+ * is indicated by the cookie as returned by _mali_ukk_get_big_block().
+ *
+ * This is only used for Mali-nonMMU mode.
+ *
+ * @param args see _mali_uk_free_big_block_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_free_big_block( _mali_uk_free_big_block_s *args );
+
+/** @brief Map Mali Memory into the current user process
+ *
+ * Maps Mali memory into the current user process in a generic way.
+ *
+ * This function is to be used for Mali-MMU mode. The function is available in both Mali-MMU and Mali-nonMMU modes,
+ * but should not be called by a user process in Mali-nonMMU mode. In Mali-nonMMU mode, the function is callable
+ * from the kernel side, and is used to implement _mali_ukk_get_big_block() in this case.
+ *
+ * The implementation and operation of _mali_ukk_mem_mmap() is dependant on whether the driver is built for Mali-MMU
+ * or Mali-nonMMU:
+ * - In the nonMMU case, _mali_ukk_mem_mmap() requires a physical address to be specified. For this reason, an OS U/K
+ * implementation should not allow this to be called from user-space. In any case, nonMMU implementations are
+ * inherently insecure, and so the overall impact is minimal. Mali-MMU mode should be used if security is desired.
+ * - In the MMU case, _mali_ukk_mem_mmap() the _mali_uk_mem_mmap_s::phys_addr
+ * member is used for the \em Mali-virtual address desired for the mapping. The
+ * implementation of _mali_ukk_mem_mmap() will allocate both the CPU-virtual
+ * and CPU-physical addresses, and can cope with mapping a contiguous virtual
+ * address range to a sequence of non-contiguous physical pages. In this case,
+ * the CPU-physical addresses are not communicated back to the user-side, as
+ * they are unnecsessary; the \em Mali-virtual address range must be used for
+ * programming Mali structures.
+ *
+ * This means that in the first (nonMMU) case, the caller must manage the physical address allocations. The caller
+ * in this case is _mali_ukk_get_big_block(), which does indeed manage the Mali physical address ranges.
+ *
+ * In the second (MMU) case, _mali_ukk_mem_mmap() handles management of
+ * CPU-virtual and CPU-physical ranges, but the \em caller must manage the
+ * \em Mali-virtual address range from the user-side.
+ *
+ * @note Mali-virtual address ranges are entirely separate between processes.
+ * It is not possible for a process to accidentally corrupt another process'
+ * \em Mali-virtual address space.
+ *
+ * @param args see _mali_uk_mem_mmap_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_mem_mmap( _mali_uk_mem_mmap_s *args );
+
+/** @brief Unmap Mali Memory from the current user process
+ *
+ * Unmaps Mali memory from the current user process in a generic way. This only operates on Mali memory supplied
+ * from _mali_ukk_mem_mmap().
+ *
+ * @param args see _mali_uk_mem_munmap_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_mem_munmap( _mali_uk_mem_munmap_s *args );
+
+/** @brief Determine the buffer size necessary for an MMU page table dump.
+ * @param args see _mali_uk_query_mmu_page_table_dump_size_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_query_mmu_page_table_dump_size( _mali_uk_query_mmu_page_table_dump_size_s *args );
+/** @brief Dump MMU Page tables.
+ * @param args see _mali_uk_dump_mmu_page_table_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_dump_mmu_page_table( _mali_uk_dump_mmu_page_table_s * args );
+
+/** @brief Map a physically contiguous range of memory into Mali
+ * @param args see _mali_uk_map_external_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_map_external_mem( _mali_uk_map_external_mem_s *args );
+
+/** @brief Unmap a physically contiguous range of memory from Mali
+ * @param args see _mali_uk_unmap_external_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_unmap_external_mem( _mali_uk_unmap_external_mem_s *args );
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+/** @brief Map UMP memory into Mali
+ * @param args see _mali_uk_attach_ump_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_attach_ump_mem( _mali_uk_attach_ump_mem_s *args );
+/** @brief Unmap UMP memory from Mali
+ * @param args see _mali_uk_release_ump_mem_s in mali_uk_types.h
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_release_ump_mem( _mali_uk_release_ump_mem_s *args );
+#endif /* MALI_USE_UNIFIED_MEMORY_PROVIDER */
+
+/** @brief Determine virtual-to-physical mapping of a contiguous memory range
+ * (optional)
+ *
+ * This allows the user-side to do a virtual-to-physical address translation.
+ * In conjunction with _mali_uku_map_external_mem, this can be used to do
+ * direct rendering.
+ *
+ * This function will only succeed on a virtual range that is mapped into the
+ * current process, and that is contigious.
+ *
+ * If va is not page-aligned, then it is rounded down to the next page
+ * boundary. The remainer is added to size, such that ((u32)va)+size before
+ * rounding is equal to ((u32)va)+size after rounding. The rounded modified
+ * va and size will be written out into args on success.
+ *
+ * If the supplied size is zero, or not a multiple of the system's PAGE_SIZE,
+ * then size will be rounded up to the next multiple of PAGE_SIZE before
+ * translation occurs. The rounded up size will be written out into args on
+ * success.
+ *
+ * On most OSs, virtual-to-physical address translation is a priveledged
+ * function. Therefore, the implementer must validate the range supplied, to
+ * ensure they are not providing arbitrary virtual-to-physical address
+ * translations. While it is unlikely such a mechanism could be used to
+ * compromise the security of a system on its own, it is possible it could be
+ * combined with another small security risk to cause a much larger security
+ * risk.
+ *
+ * @note This is an optional part of the interface, and is only used by certain
+ * implementations of libEGL. If the platform layer in your libEGL
+ * implementation does not require Virtual-to-Physical address translation,
+ * then this function need not be implemented. A stub implementation should not
+ * be required either, as it would only be removed by the compiler's dead code
+ * elimination.
+ *
+ * @note if implemented, this function is entirely platform-dependant, and does
+ * not exist in common code.
+ *
+ * @param args see _mali_uk_va_to_mali_pa_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_va_to_mali_pa( _mali_uk_va_to_mali_pa_s * args );
+
+/** @} */ /* end group _mali_uk_memory */
+
+
+/** @addtogroup _mali_uk_pp U/K Fragment Processor
+ *
+ * The Fragment Processor (aka PP (Pixel Processor)) functions provide the following functionality:
+ * - retrieving version of the fragment processors
+ * - determine number of fragment processors
+ * - starting a job on a fragment processor
+ *
+ * @{ */
+
+/** @brief Issue a request to start a new job on a Fragment Processor.
+ *
+ * If the request fails args->status is set to _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE and you can
+ * try to start the job again.
+ *
+ * An existing job could be returned for requeueing if the new job has a higher priority than a previously started job
+ * which the hardware hasn't actually started processing yet. In this case the new job will be started instead and the
+ * existing one returned, otherwise the new job is started and the status field args->status is set to
+ * _MALI_UK_START_JOB_STARTED.
+ *
+ * If an existing lower priority job is returned, args->returned_user_job_ptr contains a
+ * pointer to the returned job and the status field args->status is set to
+ * _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED.
+ *
+ * Job completion can be awaited with _mali_ukk_wait_for_notification().
+ *
+ * @param args see _mali_uk_pp_start_job_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_pp_start_job( _mali_uk_pp_start_job_s *args );
+
+/** @brief Returns the number of Fragment Processors in the system
+ *
+ * @param args see _mali_uk_get_pp_number_of_cores_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_pp_number_of_cores( _mali_uk_get_pp_number_of_cores_s *args );
+
+/** @brief Returns the version that all Fragment Processor cores are compatible with.
+ *
+ * This function may only be called when _mali_ukk_get_pp_number_of_cores() indicated at least one Fragment
+ * Processor core is available.
+ *
+ * @param args see _mali_uk_get_pp_core_version_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_pp_core_version( _mali_uk_get_pp_core_version_s *args );
+
+/** @brief Abort any PP jobs with the given ID.
+ *
+ * Jobs internally queued or currently running on the hardware is to be stopped/aborted.
+ * Jobs aborted are reported via the normal job completion system.
+ * Any jobs, running or internally queued should be aborted imediately.
+ * Normal notifiction procedures to report on the status of these jobs.
+ *
+ *
+ * @param args see _malu_uk_pp_abort_job_s in "mali_uk_types.h"
+ */
+void _mali_ukk_pp_abort_job( _mali_uk_pp_abort_job_s *args );
+/** @} */ /* end group _mali_uk_pp */
+
+
+/** @addtogroup _mali_uk_gp U/K Vertex Processor
+ *
+ * The Vertex Processor (aka GP (Geometry Processor)) functions provide the following functionality:
+ * - retrieving version of the Vertex Processors
+ * - determine number of Vertex Processors available
+ * - starting a job on a Vertex Processor
+ *
+ * @{ */
+
+/** @brief Issue a request to start a new job on a Vertex Processor.
+ *
+ * If the request fails args->status is set to _MALI_UK_START_JOB_NOT_STARTED_DO_REQUEUE and you can
+ * try to start the job again.
+ *
+ * An existing job could be returned for requeueing if the new job has a higher priority than a previously started job
+ * which the hardware hasn't actually started processing yet. In this case the new job will be started and the
+ * existing one returned, otherwise the new job is started and the status field args->status is set to
+ * _MALI_UK_START_JOB_STARTED.
+ *
+ * If an existing lower priority job is returned, args->returned_user_job_ptr contains a pointer to
+ * the returned job and the status field args->status is set to
+ * _MALI_UK_START_JOB_STARTED_LOW_PRI_JOB_RETURNED.
+ *
+ * Job completion can be awaited with _mali_ukk_wait_for_notification().
+ *
+ * @param args see _mali_uk_gp_start_job_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_gp_start_job( _mali_uk_gp_start_job_s *args );
+
+/** @brief Returns the number of Vertex Processors in the system.
+ *
+ * @param args see _mali_uk_get_gp_number_of_cores_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_gp_number_of_cores( _mali_uk_get_gp_number_of_cores_s *args );
+
+/** @brief Returns the version that all Vertex Processor cores are compatible with.
+ *
+ * This function may only be called when _mali_uk_get_gp_number_of_cores() indicated at least one Vertex
+ * Processor core is available.
+ *
+ * @param args see _mali_uk_get_gp_core_version_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_get_gp_core_version( _mali_uk_get_gp_core_version_s *args );
+
+/** @brief Resume or abort suspended Vertex Processor jobs.
+ *
+ * After receiving notification that a Vertex Processor job was suspended from
+ * _mali_ukk_wait_for_notification() you can use this function to resume or abort the job.
+ *
+ * @param args see _mali_uk_gp_suspend_response_s in "mali_uk_types.h"
+ * @return _MALI_OSK_ERR_OK on success, otherwise a suitable _mali_osk_errcode_t on failure.
+ */
+_mali_osk_errcode_t _mali_ukk_gp_suspend_response( _mali_uk_gp_suspend_response_s *args );
+
+/** @brief Abort any GP jobs with the given ID.
+ *
+ * Jobs internally queued or currently running on the hardware is to be stopped/aborted.
+ * Jobs aborted are reported via the normal job completion system.
+ *
+ * Any jobs, running or internally queued should be aborted imediately.
+ * Normal notifiction procedures to report on the status of these jobs.
+ *
+ * @param args see _mali_uk_gp_abort_job_s in "mali_uk_types.h"
+ */
+void _mali_ukk_gp_abort_job( _mali_uk_gp_abort_job_s *args );
+/** @} */ /* end group _mali_uk_gp */
+
+#if USING_MALI_PMM
+/** @addtogroup _mali_uk_pmm U/K Power Management Module
+ * @{ */
+
+/* @brief Power Management Module event message
+ *
+ * @note The event message can fail to be sent due to OOM but this is
+ * stored in the PMM state machine to be handled later
+ *
+ * @param args see _mali_uk_pmm_event_message_s in "mali_uk_types.h"
+ */
+void _mali_ukk_pmm_event_message( _mali_uk_pmm_message_s *args );
+/** @} */ /* end group _mali_uk_pmm */
+#endif /* USING_MALI_PMM */
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+/** @addtogroup _mali_uk_profiling U/K Timeline profiling module
+ * @{ */
+
+/** @brief Start recording profiling events.
+ *
+ * @param args see _mali_uk_profiling_start_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_start(_mali_uk_profiling_start_s *args);
+
+/** @brief Add event to profiling buffer.
+ *
+ * @param args see _mali_uk_profiling_add_event_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_add_event(_mali_uk_profiling_add_event_s *args);
+
+/** @brief Stop recording profiling events.
+ *
+ * @param args see _mali_uk_profiling_stop_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_stop(_mali_uk_profiling_stop_s *args);
+
+/** @brief Retrieve a recorded profiling event.
+ *
+ * @param args see _mali_uk_profiling_get_event_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_get_event(_mali_uk_profiling_get_event_s *args);
+
+/** @brief Clear recorded profiling events.
+ *
+ * @param args see _mali_uk_profiling_clear_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_clear(_mali_uk_profiling_clear_s *args);
+
+/** @brief Get the profiling config applicable for calling process.
+ *
+ * @param args see _mali_uk_profiling_get_config_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_profiling_get_config(_mali_uk_profiling_get_config_s *args);
+
+/** @brief Transfer software counters from user to kernel space 
+ * 
+ * @param args see _mali_uk_transfer_sw_counters_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_transfer_sw_counters(_mali_uk_sw_counters_s *args);
+
+/** @} */ /* end group _mali_uk_profiling */
+#endif
+
+/** @addtogroup _mali_uk_vsync U/K VSYNC reporting module
+ * @{ */
+
+/** @brief Report events related to vsync.
+ *
+ * @note Events should be reported when starting to wait for vsync and when the
+ * waiting is finished. This information can then be used in kernel space to
+ * complement the GPU utilization metric.
+ *
+ * @param args see _mali_uk_vsync_event_report_s in "mali_uk_types.h"
+ */
+_mali_osk_errcode_t _mali_ukk_vsync_event_report(_mali_uk_vsync_event_report_s *args);
+
+/** @} */ /* end group _mali_uk_vsync */
+
+/** @} */ /* end group u_k_api */
+
+/** @} */ /* end group uddapi */
+
+u32 _mali_ukk_report_memory_usage(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_UKK_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm.c
new file mode 100644
index 0000000..7041391
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm.c
@@ -0,0 +1,1024 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm.c
+ * Implementation of the power management module for the kernel device driver
+ */
+
+#if USING_MALI_PMM
+
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_subsystem.h"
+
+#include "mali_pmm.h"
+#include "mali_pmm_system.h"
+#include "mali_pmm_state.h"
+#include "mali_pmm_policy.h"
+#include "mali_pmm_pmu.h"
+#include "mali_platform.h"
+#include "mali_kernel_pm.h"
+
+/* Internal PMM subsystem state */
+static _mali_pmm_internal_state_t *pmm_state = NULL;
+/* Mali kernel subsystem id */
+static mali_kernel_subsystem_identifier mali_subsystem_pmm_id = -1;
+
+#define GET_PMM_STATE_PTR (pmm_state)
+
+/* Internal functions */
+static _mali_osk_errcode_t malipmm_create(_mali_osk_resource_t *resource);
+static void pmm_event_process( void );
+_mali_osk_errcode_t malipmm_irq_uhandler(void *data);
+void malipmm_irq_bhandler(void *data);
+
+/** @brief Start the PMM subsystem
+ *
+ * @param id Subsystem id to uniquely identify this subsystem
+ * @return _MALI_OSK_ERR_OK if the system started successfully, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t malipmm_kernel_subsystem_start( mali_kernel_subsystem_identifier id );
+
+/** @brief Perform post start up of the PMM subsystem
+ *
+ * Post start up includes initializing the current policy, now that the system is
+ * completely started - to stop policies turning off hardware during the start up
+ * 
+ * @param id the unique subsystem id
+ * @return _MALI_OSK_ERR_OK if the post startup was successful, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t malipmm_kernel_load_complete( mali_kernel_subsystem_identifier id );
+
+/** @brief Terminate the PMM subsystem
+ *
+ * @param id the unique subsystem id
+ */
+void malipmm_kernel_subsystem_terminate( mali_kernel_subsystem_identifier id );
+
+#if MALI_STATE_TRACKING
+u32 malipmm_subsystem_dump_state( char *buf, u32 size );
+#endif
+
+
+/* This will be one of the subsystems in the array of subsystems:
+	static struct mali_kernel_subsystem * subsystems[];
+  found in file: mali_kernel_core.c
+*/
+struct mali_kernel_subsystem mali_subsystem_pmm=
+{
+	malipmm_kernel_subsystem_start,                     /* startup */
+	NULL, /*malipmm_kernel_subsystem_terminate,*/                 /* shutdown */
+	malipmm_kernel_load_complete,                       /* loaded all subsystems */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+#if MALI_STATE_TRACKING
+	malipmm_subsystem_dump_state,                       /* dump_state */
+#endif
+};
+
+#if PMM_OS_TEST
+
+u32 power_test_event = 0;
+mali_bool power_test_flag = MALI_FALSE;
+_mali_osk_timer_t *power_test_timer = NULL;
+
+void _mali_osk_pmm_power_up_done(mali_pmm_message_data data)
+{
+	MALI_PRINT(("POWER TEST OS UP DONE\n"));
+}
+
+void _mali_osk_pmm_power_down_done(mali_pmm_message_data data)
+{
+	MALI_PRINT(("POWER TEST OS DOWN DONE\n"));
+}
+
+/**
+ * Symbian OS Power Up call to the driver
+ */
+void power_test_callback( void *arg )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	power_test_flag = MALI_TRUE;
+	_mali_osk_irq_schedulework( pmm->irq );
+}
+
+void power_test_start()
+{
+	power_test_timer = _mali_osk_timer_init();
+	_mali_osk_timer_setcallback( power_test_timer, power_test_callback, NULL );
+	
+	/* First event is power down */
+	power_test_event = MALI_PMM_EVENT_OS_POWER_DOWN;
+	_mali_osk_timer_add( power_test_timer, 10000 );
+}
+
+mali_bool power_test_check()
+{
+	if( power_test_flag )
+	{
+		_mali_uk_pmm_message_s event = {
+					NULL,
+					0,
+					1 };
+		event.id = power_test_event;
+
+		power_test_flag = MALI_FALSE;
+
+		/* Send event */
+		_mali_ukk_pmm_event_message( &event );
+
+		/* Switch to next event to test */
+		if( power_test_event == MALI_PMM_EVENT_OS_POWER_DOWN )
+		{
+			power_test_event = MALI_PMM_EVENT_OS_POWER_UP;
+		}
+		else
+		{
+			power_test_event = MALI_PMM_EVENT_OS_POWER_DOWN;
+		}
+		_mali_osk_timer_add( power_test_timer, 5000 );
+		
+		return MALI_TRUE;
+	}
+	
+	return MALI_FALSE;
+}
+
+void power_test_end()
+{
+	_mali_osk_timer_del( power_test_timer );
+	_mali_osk_timer_term( power_test_timer );
+	power_test_timer = NULL;
+}
+
+#endif
+
+void _mali_ukk_pmm_event_message( _mali_uk_pmm_message_s *args )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	_mali_osk_notification_t *msg;
+	mali_pmm_message_t *event;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(args);
+
+	MALIPMM_DEBUG_PRINT( ("PMM: sending message\n") );
+
+#if MALI_PMM_TRACE && MALI_PMM_TRACE_SENT_EVENTS
+	_mali_pmm_trace_event_message( args, MALI_FALSE );
+#endif
+
+	msg = _mali_osk_notification_create( MALI_PMM_NOTIFICATION_TYPE, sizeof( mali_pmm_message_t ) );
+
+	if( msg )
+	{
+		event = (mali_pmm_message_t *)msg->result_buffer;
+		event->id = args->id;
+		event->ts = _mali_osk_time_tickcount();
+		event->data = args->data;
+		
+		_mali_osk_atomic_inc( &(pmm->messages_queued) );
+
+		if( args->id > MALI_PMM_EVENT_INTERNALS )
+		{
+			/* Internal PMM message */
+			_mali_osk_notification_queue_send( pmm->iqueue, msg );
+			#if (MALI_PMM_TRACE || MALI_STATE_TRACKING)
+				pmm->imessages_sent++;
+			#endif
+		}
+		else
+		{
+			/* Real event */
+			_mali_osk_notification_queue_send( pmm->queue, msg );
+			#if (MALI_PMM_TRACE || MALI_STATE_TRACKING)
+				pmm->messages_sent++;
+			#endif
+		}
+	}
+	else
+	{
+		MALI_PRINT_ERROR( ("PMM: Could not send message %d", args->id) );
+		/* Make note of this OOM - which has caused a missed event */
+		pmm->missed++;
+	}
+	
+	/* Schedule time to look at the event or the fact we couldn't create an event */
+	_mali_osk_irq_schedulework( pmm->irq );
+}
+
+mali_pmm_state _mali_pmm_state( void )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	if( pmm && (mali_subsystem_pmm_id != -1) )
+	{
+		return pmm->state;
+	}
+
+	/* No working subsystem yet */
+	return MALI_PMM_STATE_UNAVAILABLE;
+}
+
+
+mali_pmm_core_mask _mali_pmm_cores_list( void )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	return pmm->cores_registered;
+}
+
+mali_pmm_core_mask _mali_pmm_cores_powered( void )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	return pmm->cores_powered;
+}
+
+
+_mali_osk_errcode_t _mali_pmm_list_policies(
+		u32 policy_list_size,
+		mali_pmm_policy *policy_list,
+		u32 *policies_available )
+{
+	/* TBD - This is currently a stub function for basic power management */
+
+	MALI_ERROR( _MALI_OSK_ERR_UNSUPPORTED );
+}
+
+_mali_osk_errcode_t _mali_pmm_set_policy( mali_pmm_policy policy )
+{
+	/* TBD - This is currently a stub function for basic power management */
+
+/* TBD - When this is not a stub... include tracing...
+#if MALI_PMM_TRACE
+	_mali_pmm_trace_policy_change( old, newpolicy );
+#endif
+*/
+	MALI_ERROR( _MALI_OSK_ERR_UNSUPPORTED );
+}
+
+_mali_osk_errcode_t _mali_pmm_get_policy( mali_pmm_policy *policy )
+{
+	if( policy )
+	{
+		_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+		MALI_DEBUG_ASSERT_POINTER(pmm);
+
+		if( pmm )
+		{
+			*policy = pmm->policy;
+			MALI_SUCCESS;
+		}
+		else
+		{
+			 *policy = MALI_PMM_POLICY_NONE;
+			 MALI_ERROR( _MALI_OSK_ERR_FAULT );
+		}
+	}
+
+	/* No return argument */
+	MALI_ERROR( _MALI_OSK_ERR_INVALID_ARGS );
+}
+
+#if ( MALI_PMM_TRACE || MALI_STATE_TRACKING )
+
+/* Event names - order must match mali_pmm_event_id enum */
+static char *pmm_trace_events[] = {
+	"OS_POWER_UP",
+	"OS_POWER_DOWN",
+	"JOB_SCHEDULED",
+	"JOB_QUEUED",
+	"JOB_FINISHED",
+	"TIMEOUT",
+};
+
+/* State names - order must match mali_pmm_state enum */
+static char *pmm_trace_state[] = {
+	"UNAVAILABLE",
+	"SYSTEM ON",
+	"SYSTEM OFF",
+	"SYSTEM TRANSITION",
+};
+
+/* Policy names - order must match mali_pmm_policy enum */
+static char *pmm_trace_policy[] = {
+	"NONE",
+	"ALWAYS ON",
+	"JOB CONTROL",
+};
+
+/* Status names - order must match mali_pmm_status enum */
+static char *pmm_trace_status[] = {
+	"MALI_PMM_STATUS_IDLE",                       /**< PMM is waiting next event */
+	"MALI_PMM_STATUS_POLICY_POWER_DOWN",          /**< Policy initiated power down */
+	"MALI_PMM_STATUS_POLICY_POWER_UP",            /**< Policy initiated power down */
+	"MALI_PMM_STATUS_OS_WAITING",                 /**< PMM is waiting for OS power up */
+	"MALI_PMM_STATUS_OS_POWER_DOWN",              /**< OS initiated power down */
+	"MALI_PMM_STATUS_RUNTIME_IDLE_IN_PROGRESS",
+	"MALI_PMM_STATUS_DVFS_PAUSE",                 /**< PMM DVFS Status Pause */
+	"MALI_PMM_STATUS_OS_POWER_UP",                /**< OS initiated power up */
+	"MALI_PMM_STATUS_OFF",                        /**< PMM is not active */
+};
+
+#endif /* MALI_PMM_TRACE || MALI_STATE_TRACKING */
+#if MALI_PMM_TRACE
+
+/* UK event names - order must match mali_pmm_event_id enum */
+static char *pmm_trace_events_uk[] = {
+	"UKS",
+	"UK_EXAMPLE",
+};
+
+/* Internal event names - order must match mali_pmm_event_id enum */
+static char *pmm_trace_events_internal[] = {
+	"INTERNALS",
+	"INTERNAL_POWER_UP_ACK",
+	"INTERNAL_POWER_DOWN_ACK",
+};
+
+void _mali_pmm_trace_hardware_change( mali_pmm_core_mask old, mali_pmm_core_mask newstate )
+{
+	const char *dname;
+	const char *cname;
+	const char *ename;
+
+	if( old != newstate )
+	{
+		if( newstate == 0 )
+		{
+			dname = "NO cores";
+		}
+		else
+		{
+			dname = pmm_trace_get_core_name( newstate );
+		}
+			
+		/* These state checks only work if the assumption that only cores can be
+		 * turned on or turned off in seperate actions is true. If core power states can
+		 * be toggled (some one, some off) at the same time, this check does not work
+		 */
+		if( old > newstate )
+		{
+			/* Cores have turned off */
+			cname = pmm_trace_get_core_name( old - newstate );
+			ename = "OFF";
+		}
+		else
+		{
+			/* Cores have turned on */
+			cname = pmm_trace_get_core_name( newstate - old );
+			ename = "ON";
+		}
+		MALI_PRINT( ("PMM Trace: Hardware %s ON, %s just turned %s. { 0x%08x -> 0x%08x }", dname, cname, ename, old, newstate) );
+	}
+}
+
+void _mali_pmm_trace_state_change( mali_pmm_state old, mali_pmm_state newstate )
+{
+	if( old != newstate )
+	{
+		MALI_PRINT( ("PMM Trace: State changed from %s to %s", pmm_trace_state[old], pmm_trace_state[newstate]) );
+	}
+}
+
+void _mali_pmm_trace_policy_change( mali_pmm_policy old, mali_pmm_policy newpolicy )
+{
+	if( old != newpolicy )
+	{
+		MALI_PRINT( ("PMM Trace: Policy changed from %s to %s", pmm_trace_policy[old], pmm_trace_policy[newpolicy]) );
+	}
+}
+
+void _mali_pmm_trace_event_message( mali_pmm_message_t *event, mali_bool received )
+{
+	const char *ename;
+	const char *dname;
+	const char *tname;
+	const char *format = "PMM Trace: Event %s { (%d) %s, %d ticks, (0x%x) %s }";
+
+	MALI_DEBUG_ASSERT_POINTER(event);
+
+	tname = (received) ? "received" : "sent";
+
+	if( event->id >= MALI_PMM_EVENT_INTERNALS )
+	{
+		ename = pmm_trace_events_internal[((int)event->id) - MALI_PMM_EVENT_INTERNALS];
+	}
+	else if( event->id >= MALI_PMM_EVENT_UKS )
+	{
+		ename = pmm_trace_events_uk[((int)event->id) - MALI_PMM_EVENT_UKS];
+	}
+	else
+	{
+		ename = pmm_trace_events[event->id];
+	}
+
+	switch( event->id )
+	{
+		case MALI_PMM_EVENT_OS_POWER_UP:
+		case MALI_PMM_EVENT_OS_POWER_DOWN:
+			dname = "os event";
+			break;
+
+		case MALI_PMM_EVENT_JOB_SCHEDULED:
+		case MALI_PMM_EVENT_JOB_QUEUED:
+		case MALI_PMM_EVENT_JOB_FINISHED:
+		case MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK:
+		case MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK:
+			dname = pmm_trace_get_core_name( (mali_pmm_core_mask)event->data );
+			break;
+			
+		case MALI_PMM_EVENT_TIMEOUT:
+			dname = "timeout start";
+			/* Print data with a different format */
+			format = "PMM Trace: Event %s { (%d) %s, %d ticks, %d ticks %s }";
+			break;
+		default:
+			dname = "unknown data";
+	}
+
+	MALI_PRINT( (format, tname, (u32)event->id, ename, event->ts, (u32)event->data, dname) );
+}
+
+#endif /* MALI_PMM_TRACE */
+
+
+/****************** Mali Kernel API *****************/
+
+_mali_osk_errcode_t malipmm_kernel_subsystem_start( mali_kernel_subsystem_identifier id )
+{
+	mali_subsystem_pmm_id = id;
+	MALI_CHECK_NO_ERROR(_mali_kernel_core_register_resource_handler(PMU, malipmm_create));
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t malipmm_create(_mali_osk_resource_t *resource)
+{
+	/* Create PMM state memory */
+	MALI_DEBUG_ASSERT( pmm_state == NULL );
+	pmm_state = (_mali_pmm_internal_state_t *) _mali_osk_malloc(sizeof(*pmm_state));
+	MALI_CHECK_NON_NULL( pmm_state, _MALI_OSK_ERR_NOMEM );	
+
+	/* All values get 0 as default */
+	_mali_osk_memset(pmm_state, 0, sizeof(*pmm_state));
+
+	/* Set up the initial PMM state */
+	pmm_state->waiting = 0;
+	pmm_state->status = MALI_PMM_STATUS_IDLE;
+	pmm_state->state = MALI_PMM_STATE_UNAVAILABLE; /* Until a core registers */
+
+	/* Set up policy via compile time option for the moment */
+#if MALI_PMM_ALWAYS_ON
+	pmm_state->policy = MALI_PMM_POLICY_ALWAYS_ON;
+#else 
+	pmm_state->policy = MALI_PMM_POLICY_JOB_CONTROL;
+#endif
+	
+#if MALI_PMM_TRACE
+	_mali_pmm_trace_policy_change( MALI_PMM_POLICY_NONE, pmm_state->policy );
+#endif
+
+	/* Set up assumes all values are initialized to NULL or MALI_FALSE, so
+	 * we can exit halfway through set up and perform clean up
+	 */
+
+#if USING_MALI_PMU
+        if( mali_pmm_pmu_init(resource) != _MALI_OSK_ERR_OK ) goto pmm_fail_cleanup;
+        pmm_state->pmu_initialized = MALI_TRUE;
+#endif
+	pmm_state->queue = _mali_osk_notification_queue_init();
+	if( !pmm_state->queue ) goto pmm_fail_cleanup;
+
+	pmm_state->iqueue = _mali_osk_notification_queue_init();
+	if( !pmm_state->iqueue ) goto pmm_fail_cleanup;
+
+	/* We are creating an IRQ handler just for the worker thread it gives us */
+	pmm_state->irq = _mali_osk_irq_init( _MALI_OSK_IRQ_NUMBER_PMM,
+		malipmm_irq_uhandler,
+		malipmm_irq_bhandler,
+		NULL,
+		NULL,
+		(void *)pmm_state,            /* PMM state is passed to IRQ */
+		"PMM handler" );
+
+	if( !pmm_state->irq ) goto pmm_fail_cleanup;
+
+	pmm_state->lock = _mali_osk_lock_init((_mali_osk_lock_flags_t)(_MALI_OSK_LOCKFLAG_READERWRITER | _MALI_OSK_LOCKFLAG_ORDERED), 0, 75);
+	if( !pmm_state->lock ) goto pmm_fail_cleanup;
+
+	if( _mali_osk_atomic_init( &(pmm_state->messages_queued), 0 ) != _MALI_OSK_ERR_OK )
+	{
+		goto pmm_fail_cleanup;
+	}
+
+	MALIPMM_DEBUG_PRINT( ("PMM: subsystem created, policy=%d\n", pmm_state->policy) );
+
+	MALI_SUCCESS;
+
+pmm_fail_cleanup:
+	MALI_PRINT_ERROR( ("PMM: subsystem failed to be created\n") );
+	if( pmm_state )
+	{
+		if( pmm_state->lock ) _mali_osk_lock_term( pmm_state->lock );
+		if( pmm_state->irq ) _mali_osk_irq_term( pmm_state->irq );
+		if( pmm_state->queue ) _mali_osk_notification_queue_term( pmm_state->queue );
+		if( pmm_state->iqueue ) _mali_osk_notification_queue_term( pmm_state->iqueue );		
+#if USING_MALI_PMU
+                if( pmm_state->pmu_initialized )
+                {
+                        _mali_osk_resource_type_t t = PMU;
+                        mali_pmm_pmu_deinit(&t);
+                }
+#endif /* USING_MALI_PMU */
+
+		_mali_osk_free(pmm_state);
+		pmm_state = NULL; 
+	}
+	MALI_ERROR( _MALI_OSK_ERR_FAULT );
+}
+
+_mali_osk_errcode_t malipmm_kernel_load_complete( mali_kernel_subsystem_identifier id )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	MALIPMM_DEBUG_PRINT( ("PMM: subsystem loaded, policy initializing\n") );
+
+#if PMM_OS_TEST
+	power_test_start();
+#endif
+
+	/* Initialize the profile now the system has loaded - so that cores are 
+	 * not turned off during start up 
+	 */
+	return pmm_policy_init( pmm );
+}
+
+void malipmm_force_powerup( void )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_LOCK(pmm);
+	pmm->status = MALI_PMM_STATUS_OFF;
+	MALI_PMM_UNLOCK(pmm);
+
+	/* flush PMM workqueue */
+	_mali_osk_flush_workqueue( pmm->irq );
+
+	if (pmm->cores_powered == 0)
+	{
+		malipmm_powerup(pmm->cores_registered);
+	}
+}
+
+void malipmm_kernel_subsystem_terminate( mali_kernel_subsystem_identifier id )
+{
+	/* Check this is the right system */
+	MALI_DEBUG_ASSERT( id == mali_subsystem_pmm_id );
+	MALI_DEBUG_ASSERT_POINTER(pmm_state);
+
+	if( pmm_state )
+	{
+#if PMM_OS_TEST
+		power_test_end();
+#endif
+		/* Get the lock so we can shutdown */
+		MALI_PMM_LOCK(pmm_state);
+#if MALI_STATE_TRACKING
+		pmm_state->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+		pmm_state->status = MALI_PMM_STATUS_OFF;
+#if MALI_STATE_TRACKING
+		pmm_state->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+		MALI_PMM_UNLOCK(pmm_state);
+		_mali_osk_pmm_ospmm_cleanup();
+		pmm_policy_term(pmm_state);
+		_mali_osk_irq_term( pmm_state->irq );
+		_mali_osk_notification_queue_term( pmm_state->queue );
+		_mali_osk_notification_queue_term( pmm_state->iqueue );
+		if (pmm_state->cores_registered) malipmm_powerdown(pmm_state->cores_registered,MALI_POWER_MODE_LIGHT_SLEEP);
+#if USING_MALI_PMU
+		if( pmm_state->pmu_initialized )
+		{
+			_mali_osk_resource_type_t t = PMU;
+			mali_pmm_pmu_deinit(&t);
+		}
+#endif /* USING_MALI_PMU */
+
+		_mali_osk_atomic_term( &(pmm_state->messages_queued) );
+		MALI_PMM_LOCK_TERM(pmm_state);
+		_mali_osk_free(pmm_state);
+		pmm_state = NULL; 
+	}
+
+	MALIPMM_DEBUG_PRINT( ("PMM: subsystem terminated\n") );
+}
+
+_mali_osk_errcode_t malipmm_powerup( u32 cores )
+{
+        _mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+        _mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+
+	/* If all the cores are powered down, power up the MALI */
+        if (pmm->cores_powered == 0) {
+		mali_platform_power_mode_change(MALI_POWER_MODE_ON);
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		/* Initiate the power up */
+		if (_mali_osk_pmm_dev_activate() < 0) {
+			MALI_PRINT(("PMM: Try again PD_G3D enable\n"));
+			if (mali_pd_enable() < 0) {
+				MALI_PRINT(("PMM: Mali PMM device activate failed\n"));
+				err = _MALI_OSK_ERR_FAULT;
+				return err;
+			}
+		}
+#endif
+        }
+
+#if USING_MALI_PMU
+        err = mali_pmm_pmu_powerup( cores );
+#endif
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		mali_platform_powerup(cores);
+#endif
+
+        return err;
+}
+
+_mali_osk_errcode_t malipmm_powerdown( u32 cores, mali_power_mode power_mode )
+{
+        _mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+        _mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		mali_platform_powerdown(cores);
+#endif
+
+#if USING_MALI_PMU
+        err = mali_pmm_pmu_powerdown( cores );
+#endif
+
+	/* If all cores are powered down, power off the MALI */
+        if (pmm->cores_powered == 0)
+        {
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		/* Initiate the power down */
+                _mali_osk_pmm_dev_idle();
+#endif
+                mali_platform_power_mode_change(power_mode);
+        }
+        return err;
+}
+
+_mali_osk_errcode_t malipmm_core_register( mali_pmm_core_id core )
+{
+	_mali_osk_errcode_t err;
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+
+	if( pmm == NULL )
+	{
+		/* PMM state has not been created, this is because the PMU resource has not been 
+		 * created yet.
+		 * This probably means that the PMU resource has not been specfied as the first 
+		 * resource in the config file
+		 */
+		MALI_PRINT_ERROR( ("PMM: Cannot register core %s because the PMU resource has not been\n initialized. Please make sure the PMU resource is the first resource in the\n resource configuration.\n", 
+							pmm_trace_get_core_name(core)) );
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	MALI_PMM_LOCK(pmm);
+
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+
+	/* Check if the core is registered more than once in PMM */
+	MALI_DEBUG_ASSERT( (pmm->cores_registered & core) == 0 );
+
+	MALIPMM_DEBUG_PRINT( ("PMM: core registered: (0x%x) %s\n", core, pmm_trace_get_core_name(core)) );
+
+#if !MALI_PMM_NO_PMU
+	/* Make sure the core is powered up */
+	err = malipmm_powerup( core );
+#else
+	err = _MALI_OSK_ERR_OK;
+#endif
+	if( _MALI_OSK_ERR_OK == err )
+	{
+#if MALI_PMM_TRACE
+		mali_pmm_core_mask old_power = pmm->cores_powered;
+#endif
+		/* Assume a registered core is now powered up and idle */
+		pmm->cores_registered |= core;
+		pmm->cores_idle |= core;
+		pmm->cores_powered |= core;
+		pmm_update_system_state( pmm );
+
+#if MALI_PMM_TRACE
+		_mali_pmm_trace_hardware_change( old_power, pmm->cores_powered );
+#endif		
+	}
+	else
+	{
+		MALI_PRINT_ERROR( ("PMM: Error(%d) powering up registered core: (0x%x) %s\n", 
+								err, core, pmm_trace_get_core_name(core)) );
+	}
+
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+	MALI_PMM_UNLOCK(pmm);
+	
+	return err;
+}
+
+void malipmm_core_unregister( mali_pmm_core_id core )
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	MALI_PMM_LOCK(pmm);
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+
+	/* Check if the core is registered in PMM */
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, core );
+
+	MALIPMM_DEBUG_PRINT( ("PMM: core unregistered: (0x%x) %s\n", core, pmm_trace_get_core_name(core)) );
+
+	{
+#if MALI_PMM_TRACE
+		mali_pmm_core_mask old_power = pmm->cores_powered;
+#endif
+
+		/* Remove the core from the system */
+		pmm->cores_idle &= (~core);
+		pmm->cores_powered &= (~core);
+		pmm->cores_pend_down &= (~core);
+		pmm->cores_pend_up &= (~core);
+		pmm->cores_ack_down &= (~core);
+		pmm->cores_ack_up &= (~core);
+
+		pmm_update_system_state( pmm );
+
+#if MALI_PMM_TRACE
+		_mali_pmm_trace_hardware_change( old_power, pmm->cores_powered );
+#endif		
+	}
+
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+	MALI_PMM_UNLOCK(pmm);
+}
+void malipmm_core_power_down_okay( mali_pmm_core_id core )
+{
+	_mali_uk_pmm_message_s event = {
+		NULL,
+		MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK,
+		0 };
+
+	event.data = core;
+
+	_mali_ukk_pmm_event_message( &event );
+}
+
+void malipmm_set_policy_check()
+{
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	pmm->check_policy = MALI_TRUE;
+
+	/* To check the policy we need to schedule some work */
+	_mali_osk_irq_schedulework( pmm->irq );
+}
+
+_mali_osk_errcode_t malipmm_irq_uhandler(void *data)
+{
+	MALIPMM_DEBUG_PRINT( ("PMM: uhandler - not expected to be used\n") );
+
+	MALI_SUCCESS;
+}
+
+void malipmm_irq_bhandler(void *data)
+{
+	_mali_pmm_internal_state_t *pmm;
+	pmm = (_mali_pmm_internal_state_t *)data;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+#if PMM_OS_TEST
+	if( power_test_check() ) return;
+#endif
+
+	MALI_PMM_LOCK(pmm);
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+	/* Quick out when we are shutting down */
+	if( pmm->status == MALI_PMM_STATUS_OFF )
+	{
+
+	#if MALI_STATE_TRACKING
+		pmm->mali_pmm_lock_acquired = 0;
+	#endif /* MALI_STATE_TRACKING */
+
+		MALI_PMM_UNLOCK(pmm);
+		return;
+	}
+
+	MALIPMM_DEBUG_PRINT( ("PMM: bhandler - Processing event\n") );
+
+	if( pmm->missed > 0 )
+	{
+		MALI_PRINT_ERROR( ("PMM: Failed to send %d events", pmm->missed) );
+		pmm_fatal_reset( pmm );
+	}
+	
+	if( pmm->check_policy )
+	{
+		pmm->check_policy = MALI_FALSE;
+		pmm_policy_check_policy(pmm);
+	}
+	else
+	{
+		/* Perform event processing */
+		pmm_event_process();
+		if( pmm->fatal_power_err )
+		{
+			/* Try a reset */
+			pmm_fatal_reset( pmm );
+		}
+	}
+
+#if MALI_STATE_TRACKING
+	pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+	MALI_PMM_UNLOCK(pmm);
+}
+
+static void pmm_event_process( void )
+{
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+	_mali_osk_notification_t *msg = NULL;
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+	mali_pmm_message_t *event;
+	u32 process_messages;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+
+	/* Max number of messages to process before exiting - as we shouldn't stay
+	 * processing the messages for a long time
+	 */
+	process_messages = _mali_osk_atomic_read( &(pmm->messages_queued) );
+
+	while( process_messages > 0 )
+	{
+		/* Check internal message queue first */
+		err = _mali_osk_notification_queue_dequeue( pmm->iqueue, &msg );
+
+		if( err != _MALI_OSK_ERR_OK )
+		{
+			if( pmm->status == MALI_PMM_STATUS_IDLE || pmm->status == MALI_PMM_STATUS_OS_WAITING || pmm->status == MALI_PMM_STATUS_DVFS_PAUSE) 	
+			{
+				if( pmm->waiting > 0 ) pmm->waiting--;
+
+				/* We aren't busy changing state, so look at real events */
+				err = _mali_osk_notification_queue_dequeue( pmm->queue, &msg );
+
+				if( err != _MALI_OSK_ERR_OK )
+				{
+					pmm->no_events++;
+					MALIPMM_DEBUG_PRINT( ("PMM: event_process - No message to process\n") );
+					/* Nothing to do - so return */
+					return;
+				}
+				else
+				{
+					#if (MALI_PMM_TRACE || MALI_STATE_TRACKING)
+						pmm->messages_received++;
+					#endif
+				}
+			}
+			else
+			{
+				/* Waiting for an internal message */
+				pmm->waiting++;
+				MALIPMM_DEBUG_PRINT( ("PMM: event_process - Waiting for internal message, messages queued=%d\n", pmm->waiting) );
+				return;
+			}
+		}
+		else
+		{
+			#if (MALI_PMM_TRACE || MALI_STATE_TRACKING)
+				pmm->imessages_received++;
+			#endif
+		}
+
+		MALI_DEBUG_ASSERT_POINTER( msg );
+		/* Check the message type matches */
+		MALI_DEBUG_ASSERT( msg->notification_type == MALI_PMM_NOTIFICATION_TYPE );
+
+		event = msg->result_buffer;
+
+		_mali_osk_atomic_dec( &(pmm->messages_queued) );
+		process_messages--;
+
+		#if MALI_PMM_TRACE
+			/* Trace before we process the event in case we have an error */
+			_mali_pmm_trace_event_message( event, MALI_TRUE );
+		#endif
+		err = pmm_policy_process( pmm, event );
+
+
+		if( err != _MALI_OSK_ERR_OK )
+		{
+			MALI_PRINT_ERROR( ("PMM: Error(%d) in policy %d when processing event message with id: %d", 
+					err, pmm->policy, event->id) );
+		}
+
+		/* Delete notification */
+		_mali_osk_notification_delete ( msg );
+
+		if( pmm->fatal_power_err )
+		{
+			/* Nothing good has happened - exit */
+			return;
+		}
+
+
+		#if MALI_PMM_TRACE
+			MALI_PRINT( ("PMM Trace: Event processed, msgs (sent/read) = %d/%d, int msgs (sent/read) = %d/%d, no events = %d, waiting = %d\n", 
+					pmm->messages_sent, pmm->messages_received, pmm->imessages_sent, pmm->imessages_received, pmm->no_events, pmm->waiting) );
+		#endif
+	}
+
+	if( pmm->status == MALI_PMM_STATUS_IDLE && pmm->waiting > 0 )
+	{
+		/* For events we ignored whilst we were busy, add a new
+		 * scheduled time to look at them */
+		_mali_osk_irq_schedulework( pmm->irq );
+	}
+}
+
+#if MALI_STATE_TRACKING
+u32 malipmm_subsystem_dump_state(char *buf, u32 size)
+{
+	int len = 0;
+	_mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR;
+
+	if( !pmm )
+	{
+		len += _mali_osk_snprintf(buf + len, size + len, "PMM: Null state\n");
+	}
+	else
+	{
+		len += _mali_osk_snprintf(buf+len, size+len, "Locks:\n  PMM lock acquired: %s\n",
+				pmm->mali_pmm_lock_acquired ? "true" : "false");
+		len += _mali_osk_snprintf(buf+len, size+len,
+				"PMM state:\n  Previous status: %s\n  Status: %s\n  Current event: %s\n  Policy: %s\n  Check policy: %s\n  State: %s\n",
+				pmm_trace_status[pmm->mali_last_pmm_status], pmm_trace_status[pmm->status],
+				pmm_trace_events[pmm->mali_new_event_status], pmm_trace_policy[pmm->policy],
+				pmm->check_policy ? "true" : "false", pmm_trace_state[pmm->state]);
+		len += _mali_osk_snprintf(buf+len, size+len,
+				"PMM cores:\n  Cores registered: %d\n  Cores powered: %d\n  Cores idle: %d\n"
+				"  Cores pending down: %d\n  Cores pending up: %d\n  Cores ack down: %d\n  Cores ack up: %d\n",
+				pmm->cores_registered, pmm->cores_powered, pmm->cores_idle, pmm->cores_pend_down,
+				pmm->cores_pend_up, pmm->cores_ack_down, pmm->cores_ack_up);
+		len += _mali_osk_snprintf(buf+len, size+len, "PMM misc:\n  PMU init: %s\n  Messages queued: %d\n"
+				"  Waiting: %d\n  No events: %d\n  Missed events: %d\n  Fatal power error: %s\n",
+				pmm->pmu_initialized ? "true" : "false", _mali_osk_atomic_read(&(pmm->messages_queued)),
+				pmm->waiting, pmm->no_events, pmm->missed, pmm->fatal_power_err ? "true" : "false");
+	}
+	return len;
+}
+#endif /* MALI_STATE_TRACKING */
+
+#endif /* USING_MALI_PMM */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm.h
new file mode 100644
index 0000000..5170650
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm.h
+ * Defines the power management module for the kernel device driver
+ */
+
+#ifndef __MALI_PMM_H__
+#define __MALI_PMM_H__
+
+/* For mali_pmm_message_data and MALI_PMM_EVENT_UK_* defines */
+#include "mali_uk_types.h"
+#include "mali_platform.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup pmmapi Power Management Module APIs
+ *
+ * @{
+ */
+
+/** OS event tester */
+#define PMM_OS_TEST 0
+
+/** @brief Compile option to turn on/off tracing */
+#define MALI_PMM_TRACE 0
+#define MALI_PMM_TRACE_SENT_EVENTS 0
+
+/** @brief Compile option to switch between always on or job control PMM policy */
+#define MALI_PMM_ALWAYS_ON 0
+
+/** @brief Overrides hardware PMU and uses software simulation instead
+ *  @note This even stops intialization of PMU and cores being powered on at start up
+ */
+#define MALI_PMM_NO_PMU 0
+
+/** @brief PMM debug print to control debug message level */
+#define MALIPMM_DEBUG_PRINT(args) \
+	MALI_DEBUG_PRINT(3, args)
+
+
+/** @brief power management event message identifiers.
+ */
+/* These must match up with the pmm_trace_events & pmm_trace_events_internal
+ * arrays
+ */
+typedef enum mali_pmm_event_id
+{
+	MALI_PMM_EVENT_OS_POWER_UP             =    0,   /**< OS power up event */
+	MALI_PMM_EVENT_OS_POWER_DOWN           =    1,   /**< OS power down event */
+	MALI_PMM_EVENT_JOB_SCHEDULED           =    2,   /**< Job scheduled to run event */
+	MALI_PMM_EVENT_JOB_QUEUED              =    3,   /**< Job queued (but not run) event */
+	MALI_PMM_EVENT_JOB_FINISHED            =    4,   /**< Job finished event */
+	MALI_PMM_EVENT_TIMEOUT                 =    5,   /**< Time out timer has expired */
+	MALI_PMM_EVENT_DVFS_PAUSE              =    6,   /**< Mali device pause event */
+	MALI_PMM_EVENT_DVFS_RESUME             =    7,   /**< Mali device resume event */
+
+	MALI_PMM_EVENT_UKS                     =  200,   /**< Events from the user-side start here */
+	MALI_PMM_EVENT_UK_EXAMPLE              =  _MALI_PMM_EVENT_UK_EXAMPLE,
+
+	MALI_PMM_EVENT_INTERNALS               = 1000,
+	MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK   = 1001,   /**< Internal power up acknowledgement */
+	MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK = 1002,   /**< Internal power down acknowledgment */
+} mali_pmm_event_id;
+
+
+/** @brief Use this when the power up/down callbacks do not need any OS data. */
+#define MALI_PMM_NO_OS_DATA 1
+
+
+/* @brief Geometry and pixel processor identifiers for the PMM
+ *
+ * @note these match the ARM Mali 400 PMU hardware definitions, apart from the "SYSTEM"
+ */
+typedef enum mali_pmm_core_id_tag
+{
+	MALI_PMM_CORE_SYSTEM = 0x00000000,          /**< All of the Mali hardware */
+	MALI_PMM_CORE_GP     = 0x00000001,          /**< Mali GP2 */
+	MALI_PMM_CORE_L2     = 0x00000002,          /**< Level 2 cache */
+	MALI_PMM_CORE_PP0    = 0x00000004,          /**< Mali 200 pixel processor 0 */
+	MALI_PMM_CORE_PP1    = 0x00000008,          /**< Mali 200 pixel processor 1 */
+	MALI_PMM_CORE_PP2    = 0x00000010,          /**< Mali 200 pixel processor 2 */
+	MALI_PMM_CORE_PP3    = 0x00000020,          /**< Mali 200 pixel processor 3 */
+	MALI_PMM_CORE_PP_ALL = 0x0000003C           /**< Mali 200 pixel processors 0-3 */
+} mali_pmm_core_id;
+
+
+/* @brief PMM bitmask of mali_pmm_core_ids
+ */
+typedef u32 mali_pmm_core_mask;
+
+/* @brief PMM event timestamp type
+ */
+typedef u32 mali_pmm_timestamp;
+
+/** @brief power management event message struct
+ */
+typedef struct _mali_pmm_message
+{
+	mali_pmm_event_id id;               /**< event id */
+	mali_pmm_message_data data;         /**< specific data associated with the event */
+	mali_pmm_timestamp ts;              /**< timestamp the event was placed in the event queue */
+} mali_pmm_message_t;
+
+
+
+/** @brief the state of the power management module.
+ */
+/* These must match up with the pmm_trace_state array */
+typedef enum mali_pmm_state_tag
+{
+	MALI_PMM_STATE_UNAVAILABLE       = 0,       /**< PMM is not available */
+	MALI_PMM_STATE_SYSTEM_ON         = 1,       /**< All of the Mali hardware is on */
+	MALI_PMM_STATE_SYSTEM_OFF        = 2,       /**< All of the Mali hardware is off */
+	MALI_PMM_STATE_SYSTEM_TRANSITION = 3        /**< System is changing state */
+} mali_pmm_state;
+
+
+/** @brief a power management policy.
+ */
+/* These must match up with the pmm_trace_policy array */
+typedef enum mali_pmm_policy_tag
+{
+	MALI_PMM_POLICY_NONE        = 0,            /**< No policy */
+	MALI_PMM_POLICY_ALWAYS_ON   = 1,            /**< Always on policy */
+	MALI_PMM_POLICY_JOB_CONTROL = 2,            /**< Job control policy */
+	MALI_PMM_POLICY_RUNTIME_JOB_CONTROL = 3     /**< Run time power management control policy */
+} mali_pmm_policy;
+
+/** @brief Function to power up MALI
+ *
+ * @param cores core mask to power up the cores
+ *
+ * @return error code if MALI fails to power up
+ */
+_mali_osk_errcode_t malipmm_powerup( u32 cores );
+
+/** @brief Function to power down MALI
+ *
+ * @param cores core mask to power down the cores
+ * @param The power mode to which MALI transitions
+ *
+ * @return error code if MALI fails to power down
+ */
+_mali_osk_errcode_t malipmm_powerdown( u32 cores, mali_power_mode power_mode );
+
+/** @brief Function to report to the OS when the power down has finished
+ *
+ * @param data The event message data that initiated the power down
+ */
+void _mali_osk_pmm_power_down_done(mali_pmm_message_data data);
+
+/** @brief Function to report to the OS when the power up has finished
+ *
+ * @param data The event message data that initiated the power up
+ */
+void _mali_osk_pmm_power_up_done(mali_pmm_message_data data);
+
+/** @brief Function to report that DVFS operation done
+ *
+ * @param data The event message data
+ */
+void _mali_osk_pmm_dvfs_operation_done(mali_pmm_message_data data);
+
+#if MALI_POWER_MGMT_TEST_SUITE
+/** @brief Function to notify power management events
+ *
+ * @param data The event message data
+ */
+void _mali_osk_pmm_policy_events_notifications(mali_pmm_event_id event_id);
+
+#endif
+
+/** @brief Function to power up MALI
+ *
+ *  @note powers up the MALI during MALI device driver is unloaded
+ */
+void malipmm_force_powerup( void );
+
+/** @brief Function to report the OS that device is idle
+ *
+ *  @note inform the OS that device is idle
+ */
+_mali_osk_errcode_t _mali_osk_pmm_dev_idle( void );
+
+/** @brief Function to report the OS to activate device
+ *
+ * @note inform the os that device needs to be activated
+ */
+int _mali_osk_pmm_dev_activate( void );
+
+/** @brief Function to report OS PMM for cleanup
+ *
+ * @note Function to report OS PMM for cleanup
+ */
+void _mali_osk_pmm_ospmm_cleanup( void );
+
+/** @brief Queries the current state of the PMM software
+ *
+ * @note the state of the PMM can change after this call has returned
+ *
+ * @return the current PMM state value
+ */
+mali_pmm_state _mali_pmm_state( void );
+
+/** @brief List of cores that are registered with the PMM
+ *
+ * This will return the cores that have been currently registered with the PMM,
+ * which is a bitwise OR of the mali_pmm_core_id_tags. A value of 0x0 means that
+ * there are no cores registered.
+ *
+ * @note the list of cores can change after this call has returned
+ *
+ * @return a bit mask representing all the cores that have been registered with the PMM
+ */
+mali_pmm_core_mask _mali_pmm_cores_list( void );
+
+/** @brief List of cores that are powered up in the PMM
+ *
+ * This will return the subset of the cores that can be listed using mali_pmm_cores_
+ * list, that have power. It is a bitwise OR of the mali_pmm_core_id_tags. A value of
+ * 0x0 means that none of the cores registered are powered.
+ *
+ * @note the list of cores can change after this call has returned
+ *
+ * @return a bit mask representing all the cores that are powered up
+ */
+mali_pmm_core_mask _mali_pmm_cores_powered( void );
+
+
+/** @brief List of power management policies that are supported by the PMM
+ *
+ * Given an empty array of policies - policy_list - which contains the number
+ * of entries as specified by - policy_list_size, this function will populate
+ * the list with the available policies. If the policy_list is too small for
+ * all the policies then only policy_list_size entries will be returned. If the
+ * policy_list is bigger than the number of available policies then, the extra
+ * entries will be set to MALI_PMM_POLICY_NONE.
+ * The function will also update available_policies with the number of policies
+ * that are available, even if it exceeds the policy_list_size.
+ * The function will succeed if all policies could be returned, else it will
+ * fail if none or only a subset of policies could be returned.
+ * The function will also fail if no policy_list is supplied, though
+ * available_policies is optional.
+ *
+ * @note this is a STUB function and is not yet implemented
+ *
+ * @param policy_list_size is the number of policies that can be returned in
+ * the policy_list argument
+ * @param policy_list is an array of policies that should be populated with
+ * the list of policies that are supported by the PMM
+ * @param policies_available optional argument, if non-NULL will be set to the
+ * number of policies available
+ * @return _MALI_OSK_ERR_OK if the policies could be listed, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t _mali_pmm_list_policies(
+		u32 policy_list_size,
+		mali_pmm_policy *policy_list,
+		u32 *policies_available );
+
+/** @brief Set the power management policy in the PMM
+ *
+ * Given a valid supported policy, this function will change the PMM to use
+ * this new policy
+ * The function will fail if the policy given is invalid or unsupported.
+ *
+ * @note this is a STUB function and is not yet implemented
+ *
+ * @param policy the new policy to be set
+ * @return _MALI_OSK_ERR_OK if the policy could be set, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t _mali_pmm_set_policy( mali_pmm_policy policy );
+
+/** @brief Get the current power management policy in the PMM
+ *
+ * Given a pointer to a policy data type, this function will return the current
+ * policy that is in effect for the PMM. This maybe out of date if there is a
+ * pending set policy call that has not been serviced.
+ * The function will fail if the policy given is NULL.
+ *
+ * @note the policy of the PMM can change after this call has returned
+ *
+ * @param policy a pointer to a policy that can be updated to the current
+ * policy
+ * @return _MALI_OSK_ERR_OK if the policy could be returned, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t _mali_pmm_get_policy( mali_pmm_policy *policy );
+
+#if MALI_PMM_TRACE
+
+/** @brief Indicates when a hardware state change occurs in the PMM
+ *
+ * @param old a mask of the cores indicating the previous state of the cores
+ * @param newstate a mask of the cores indicating the new current state of the cores
+ */
+void _mali_pmm_trace_hardware_change( mali_pmm_core_mask old, mali_pmm_core_mask newstate );
+
+/** @brief Indicates when a state change occurs in the PMM
+ *
+ * @param old the previous state for the PMM
+ * @param newstate the new current state of the PMM
+ */
+void _mali_pmm_trace_state_change( mali_pmm_state old, mali_pmm_state newstate );
+
+/** @brief Indicates when a policy change occurs in the PMM
+ *
+ * @param old the previous policy for the PMM
+ * @param newpolicy the new current policy of the PMM
+ */
+void _mali_pmm_trace_policy_change( mali_pmm_policy old, mali_pmm_policy newpolicy );
+
+/** @brief Records when an event message is read by the event system
+ *
+ * @param event the message details
+ * @param received MALI_TRUE when the message is received by the PMM, else it is being sent
+ */
+void _mali_pmm_trace_event_message( mali_pmm_message_t *event, mali_bool received );
+
+#endif /* MALI_PMM_TRACE */
+
+/** @brief Dumps the current state of OS PMM thread
+ */
+#if MALI_STATE_TRACKING
+u32 mali_pmm_dump_os_thread_state( char *buf, u32 size );
+#endif /* MALI_STATE_TRACKING */
+
+/** @} */ /* end group pmmapi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.c
new file mode 100644
index 0000000..a8160ac
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_pmu.c
+ * Mali driver functions for Mali 400 PMU hardware
+ */
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+
+#if USING_MALI_PMU
+#if USING_MALI_PMM
+
+#include "mali_pmm.h"
+
+/* Internal test on/off */
+#define PMU_TEST 0
+
+#if MALI_POWER_MGMT_TEST_SUITE
+#include "mali_platform_pmu_internal_testing.h"
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+
+/** @brief PMU hardware info
+ */
+typedef struct platform_pmu
+{
+	u32 reg_base_addr;              /**< PMU registers base address */
+	u32 reg_size;                   /**< PMU registers size */
+	const char *name;               /**< PMU name */
+	u32 irq_num;                    /**< PMU irq number */
+
+	mali_io_address reg_mapped;     /**< IO-mapped pointer to registers */
+} platform_pmu_t;
+
+static platform_pmu_t *pmu_info = NULL;
+
+/** @brief Register layout for hardware PMU
+ */
+typedef enum {
+	PMU_REG_ADDR_MGMT_POWER_UP                  = 0x00,     /*< Power up register */
+	PMU_REG_ADDR_MGMT_POWER_DOWN                = 0x04,     /*< Power down register */
+	PMU_REG_ADDR_MGMT_STATUS                    = 0x08,     /*< Core sleep status register */
+	PMU_REG_ADDR_MGMT_INT_MASK                  = 0x0C,     /*< Interrupt mask register */
+	PMU_REG_ADDR_MGMT_INT_RAWSTAT               = 0x10,     /*< Interrupt raw status register */
+	PMU_REG_ADDR_MGMT_INT_STAT                  = 0x14,     /*< Interrupt status register */
+	PMU_REG_ADDR_MGMT_INT_CLEAR                 = 0x18,     /*< Interrupt clear register */
+	PMU_REG_ADDR_MGMT_SW_DELAY                  = 0x1C,     /*< Software delay register */
+	PMU_REG_ADDR_MGMT_MASTER_PWR_UP             = 0x24,     /*< Master power up register */
+	PMU_REGISTER_ADDRESS_SPACE_SIZE             = 0x28,     /*< Size of register space */
+} pmu_reg_addr_mgmt_addr;
+
+/* Internal functions */
+static u32 pmu_reg_read(platform_pmu_t *pmu, u32 relative_address);
+static void pmu_reg_write(platform_pmu_t *pmu, u32 relative_address, u32 new_val);
+static mali_pmm_core_mask pmu_translate_cores_to_pmu(mali_pmm_core_mask cores);
+#if PMU_TEST
+static void pmm_pmu_dump_regs( platform_pmu_t *pmu );
+static pmm_pmu_test( platform_pmu_t *pmu, u32 cores );
+#endif
+
+_mali_osk_errcode_t mali_pmm_pmu_init(_mali_osk_resource_t *resource)
+{
+
+	if( resource->type == PMU )
+	{
+		if( (resource->base == 0) ||
+			(resource->description == NULL) )
+		{
+			/* NOTE: We currently don't care about any other resource settings */
+			MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Missing PMU set up information\n"));
+			MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+		}
+		pmu_info = (platform_pmu_t *)_mali_osk_malloc(sizeof(*pmu_info));
+		MALI_CHECK_NON_NULL( pmu_info, _MALI_OSK_ERR_NOMEM );	
+
+		/* All values get 0 as default */
+		_mali_osk_memset(pmu_info, 0, sizeof(*pmu_info));
+		
+		pmu_info->reg_base_addr = resource->base;
+		pmu_info->reg_size = (u32)PMU_REGISTER_ADDRESS_SPACE_SIZE;
+		pmu_info->name = resource->description; 
+		pmu_info->irq_num = resource->irq;
+
+		if( _MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name) )
+		{
+			MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not request register region (0x%08X - 0x%08X) for %s\n",
+					 pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
+			goto cleanup;
+		}
+		else
+		{
+			MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: request_mem_region: (0x%08X - 0x%08X) for %s\n",
+					 pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
+		}
+
+		pmu_info->reg_mapped = _mali_osk_mem_mapioregion( pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name );
+
+		if( 0 == pmu_info->reg_mapped )
+		{
+			MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not ioremap registers for %s .\n", pmu_info->name));
+			_mali_osk_mem_unreqregion( pmu_info->reg_base_addr, pmu_info->reg_size );
+			goto cleanup;
+		}
+		else
+		{
+			MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: ioremap_nocache: Internal ptr: (0x%08X - 0x%08X) for %s\n",
+					(u32) pmu_info->reg_mapped,
+					((u32)pmu_info->reg_mapped)+ pmu_info->reg_size - 1,
+					pmu_info->name));
+		}
+
+		MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: Mapping registers to %s\n", pmu_info->name));
+
+#if PMU_TEST
+		pmu_test(pmu_info, (MALI_PMM_CORE_GP));
+		pmu_test(pmu_info, (MALI_PMM_CORE_GP|MALI_PMM_CORE_L2|MALI_PMM_CORE_PP0));
+#endif
+
+		MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Initialized - %s\n", pmu_info->name) );		
+	}
+	else
+	{
+		/* Didn't expect a different resource */
+		MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}	
+
+	MALI_SUCCESS;
+	
+cleanup:
+	_mali_osk_free(pmu_info);
+	pmu_info = NULL;
+	MALI_ERROR(_MALI_OSK_ERR_NOMEM);
+}
+
+_mali_osk_errcode_t mali_pmm_pmu_deinit(_mali_osk_resource_type_t *type)
+{
+	if (*type == PMU)
+	{
+		if( pmu_info )
+		{
+			_mali_osk_mem_unmapioregion(pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->reg_mapped);
+			_mali_osk_mem_unreqregion(pmu_info->reg_base_addr, pmu_info->reg_size);
+			_mali_osk_free(pmu_info);
+			pmu_info = NULL;
+			MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Terminated PMU\n") );
+		}
+	}
+	else
+	{
+		/* Didn't expect a different resource */
+		MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
+	}	
+		
+	MALI_SUCCESS;
+
+}
+
+_mali_osk_errcode_t mali_pmm_pmu_powerdown(u32 cores)
+{
+	u32 stat;
+	u32 timeout;
+	u32 cores_pmu;
+
+	MALI_DEBUG_ASSERT_POINTER(pmu_info);
+	MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
+	MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power down (0x%x)\n", cores) );
+
+	cores_pmu = pmu_translate_cores_to_pmu(cores);
+	pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_DOWN, cores_pmu );
+
+	/* Wait for cores to be powered down */
+	timeout = 10; /* 10ms */ 
+	do
+	{
+		/* Get status of sleeping cores */
+		stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
+		stat &= cores_pmu;
+		if( stat == cores_pmu ) break; /* All cores we wanted are now asleep */
+		_mali_osk_time_ubusydelay(1000); /* 1ms */
+		timeout--;
+	} while( timeout > 0 );
+
+	if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_pmm_pmu_powerup(u32 cores)
+{
+	u32 cores_pmu;
+	u32 stat;
+	u32 timeout;
+	
+	MALI_DEBUG_ASSERT_POINTER(pmu_info);
+	MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
+	MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power up (0x%x)\n", cores) );
+
+	/* Don't use interrupts - just poll status */
+	pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_INT_MASK, 0 );
+	cores_pmu = pmu_translate_cores_to_pmu(cores);
+	pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_UP, cores_pmu );
+
+	timeout = 10; /* 10ms */ 
+	do
+	{
+		/* Get status of sleeping cores */
+		stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
+		stat &= cores_pmu;
+		if( stat == 0 ) break; /* All cores we wanted are now awake */
+		_mali_osk_time_ubusydelay(1000); /* 1ms */
+		timeout--;
+	} while( timeout > 0 );
+
+	if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
+
+	MALI_SUCCESS;
+}
+
+
+/***** INTERNAL *****/
+
+/** @brief Internal PMU function to translate the cores bit mask
+ *         into something the hardware PMU understands
+ *
+ * @param cores PMM cores bitmask
+ * @return PMU hardware cores bitmask
+ */
+static u32 pmu_translate_cores_to_pmu(mali_pmm_core_mask cores)
+{
+	/* For Mali 400 PMU the cores mask is already the same as what
+	 * the hardware PMU expects.
+	 * For other hardware, some translation can be done here, by
+	 * translating the MALI_PMM_CORE_* bits into specific hardware
+	 * bits
+	 */
+	 return cores;
+}
+
+/** @brief Internal PMU function to read a PMU register
+ *
+ * @param pmu handle that identifies the PMU hardware
+ * @param relative_address relative PMU hardware address to read from
+ * @return 32-bit value that was read from the address
+ */
+static u32 pmu_reg_read(platform_pmu_t *pmu, u32 relative_address)
+{
+	u32 read_val;
+
+	MALI_DEBUG_ASSERT_POINTER(pmu);
+	MALI_DEBUG_ASSERT((relative_address & 0x03) == 0);
+	MALI_DEBUG_ASSERT(relative_address < pmu->reg_size);
+
+	read_val = _mali_osk_mem_ioread32(pmu->reg_mapped, relative_address);
+
+	MALI_DEBUG_PRINT( 5, ("PMU: reg_read: %s Addr:0x%04X Val:0x%08x\n",
+			pmu->name, relative_address, read_val));
+
+	return read_val;
+}
+
+/** @brief Internal PMU function to write to a PMU register
+ *
+ * @param pmu handle that identifies the PMU hardware
+ * @param relative_address relative PMU hardware address to write to
+ * @param new_val new 32-bit value to write into the address
+ */
+static void pmu_reg_write(platform_pmu_t *pmu, u32 relative_address, u32 new_val)
+{
+	MALI_DEBUG_ASSERT_POINTER(pmu);
+	MALI_DEBUG_ASSERT((relative_address & 0x03) == 0);
+	MALI_DEBUG_ASSERT(relative_address < pmu->reg_size);
+
+	MALI_DEBUG_PRINT( 5, ("PMU: reg_write: %s Addr:0x%04X Val:0x%08x\n",
+			pmu->name, relative_address, new_val));
+
+	_mali_osk_mem_iowrite32(pmu->reg_mapped, relative_address, new_val);
+}
+
+#if PMU_TEST
+
+/***** TEST *****/
+
+static void pmu_dump_regs( platform_pmu_t *pmu )
+{
+	u32 addr;
+	for( addr = 0x0; addr < PMU_REGISTER_ADDRESS_SPACE_SIZE; addr += 0x4 )
+	{
+		MALI_PRINT( ("PMU_REG: 0x%08x: 0x%04x\n", (addr + pmu->reg_base_addr), pmu_reg_read( pmu, addr ) ) );
+	}
+}
+
+/* This function is an internal test for the PMU without any Mali h/w interaction */
+static void pmu_test( platform_pmu_t *pmu, u32 cores )
+{
+	u32 stat;
+	u32 timeout;
+	
+	MALI_PRINT( ("PMU_TEST: Start\n") );
+	
+	pmu_dump_regs( pmu );
+	
+	MALI_PRINT( ("PMU_TEST: Power down cores: 0x%x\n", cores) );
+	_mali_pmm_pmu_power_down( pmu, cores, MALI_TRUE );
+	
+	stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
+	MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == cores ? "SUCCESS" : "FAIL" ) );
+	
+	pmu_dump_regs( pmu );
+	
+	MALI_PRINT( ("PMU_TEST: Power up cores: 0x%x\n", cores) );
+	_mali_pmm_pmu_power_up( pmu, cores, MALI_FALSE );
+	
+	MALI_PRINT( ("PMU_TEST: Waiting for power up...\n") );
+	timeout = 1000; /* 1 sec */
+	while( !_mali_pmm_pmu_irq_power_up(pmu) && timeout > 0 )
+	{
+		_mali_osk_time_ubusydelay(1000); /* 1ms */
+		timeout--;		
+	} 
+
+	MALI_PRINT( ("PMU_TEST: Waited %dms for interrupt\n", (1000-timeout)) );
+	stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
+	MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == 0 ? "SUCCESS" : "FAIL" ) );
+
+	_mali_pmm_pmu_irq_power_up_clear(pmu);
+
+	pmu_dump_regs( pmu );
+
+	MALI_PRINT( ("PMU_TEST: Finish\n") );
+}
+#endif /* PMU_TEST */
+
+#if MALI_POWER_MGMT_TEST_SUITE
+
+u32 pmu_get_power_up_down_info(void)
+{
+        return pmu_reg_read(pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS);
+}
+
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+#endif /* USING_MALI_PMM */
+#endif /* USING_MALI_PMU */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.h
new file mode 100644
index 0000000..7525cac
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_pmu.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+/**
+ * @file mali_platform.h
+ * Platform specific Mali driver functions
+ */
+
+#include "mali_osk.h"
+
+#if !USING_MALI_PMM
+/* @brief System power up/down cores that can be passed into mali_platform_powerdown/up() */
+#define MALI_PLATFORM_SYSTEM  0
+#endif
+
+#if USING_MALI_PMM
+#if USING_MALI_PMU
+#include "mali_pmm.h"
+
+/** @brief Platform specific setup and initialisation of MALI
+ * 
+ * This is called from the entrypoint of the driver to initialize the platform
+ * When using PMM, it is also called from the PMM start up to initialise the 
+ * system PMU
+ *
+ * @param resource This is NULL when called on first driver start up, else it will
+ * be a pointer to a PMU resource
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_pmm_pmu_init(_mali_osk_resource_t *resource);
+
+/** @brief Platform specific deinitialisation of MALI
+ * 
+ * This is called on the exit of the driver to terminate the platform
+ * When using PMM, it is also called from the PMM termination code to clean up the
+ * system PMU
+ *
+ * @param type This is NULL when called on driver exit, else it will
+ * be a pointer to a PMU resource type (not the full resource)
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_pmm_pmu_deinit(_mali_osk_resource_type_t *type);
+
+/** @brief Platform specific powerdown sequence of MALI
+ * 
+ * Called as part of platform init if there is no PMM support, else the
+ * PMM will call it.
+ *
+ * @param cores This is MALI_PLATFORM_SYSTEM when called without PMM, else it will
+ * be a mask of cores to power down based on the mali_pmm_core_id enum
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_pmm_pmu_powerdown(u32 cores);
+
+/** @brief Platform specific powerup sequence of MALI
+ * 
+ * Called as part of platform deinit if there is no PMM support, else the
+ * PMM will call it.
+ *
+ * @param cores This is MALI_PLATFORM_SYSTEM when called without PMM, else it will
+ * be a mask of cores to power down based on the mali_pmm_core_id enum
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_pmm_pmu_powerup(u32 cores);
+
+#if MALI_POWER_MGMT_TEST_SUITE
+#if USING_MALI_PMM
+#if USING_MALI_PMU
+/** @brief function to get status of individual cores
+ *
+ * This function is used by power management test suite to get the status of powered up/down the number
+ * of cores
+ * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
+ */
+u32 pmu_get_power_up_down_info(void);
+#endif
+#endif
+#endif
+#endif
+#endif
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.c
new file mode 100644
index 0000000..87b6ec2
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy.c
+ * Implementation of the common routines for power management module 
+ * policies
+ */
+
+#if USING_MALI_PMM
+
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+
+#include "mali_pmm.h"
+#include "mali_pmm_system.h"
+#include "mali_pmm_state.h"
+#include "mali_pmm_policy.h"
+
+#include "mali_pmm_policy_alwayson.h"
+#include "mali_pmm_policy_jobcontrol.h"
+
+/* Call back function for timer expiration */
+static void pmm_policy_timer_callback( void *arg );
+
+_mali_osk_errcode_t pmm_policy_timer_init( _pmm_policy_timer_t *pptimer, u32 timeout, mali_pmm_event_id id )
+{
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+	
+	/* All values get 0 as default */
+	_mali_osk_memset(pptimer, 0, sizeof(*pptimer));
+	
+	pptimer->timer = _mali_osk_timer_init();
+	if( pptimer->timer )
+	{
+		_mali_osk_timer_setcallback( pptimer->timer, pmm_policy_timer_callback, (void *)pptimer );
+		pptimer->timeout = timeout;
+		pptimer->event_id = id;
+		MALI_SUCCESS;
+	}
+	
+	return _MALI_OSK_ERR_FAULT;
+}
+
+static void pmm_policy_timer_callback( void *arg )
+{
+	_pmm_policy_timer_t *pptimer = (_pmm_policy_timer_t *)arg;
+	
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+	MALI_DEBUG_ASSERT( pptimer->set );
+
+	/* Set timer expired and flag there is a policy to check */
+	pptimer->expired = MALI_TRUE;
+	malipmm_set_policy_check();
+}
+
+
+void pmm_policy_timer_term( _pmm_policy_timer_t *pptimer )
+{
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+
+	_mali_osk_timer_del( pptimer->timer );
+	_mali_osk_timer_term( pptimer->timer );
+	pptimer->timer = NULL;
+}
+
+mali_bool pmm_policy_timer_start( _pmm_policy_timer_t *pptimer )
+{
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+	MALI_DEBUG_ASSERT_POINTER(pptimer->timer);
+
+	if( !(pptimer->set) )
+	{
+		pptimer->set = MALI_TRUE;
+		pptimer->expired = MALI_FALSE;
+		pptimer->start = _mali_osk_time_tickcount();
+		_mali_osk_timer_add( pptimer->timer, pptimer->timeout );
+		return MALI_TRUE;
+	}
+	
+	return MALI_FALSE;
+}
+
+mali_bool pmm_policy_timer_stop( _pmm_policy_timer_t *pptimer )
+{
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+	MALI_DEBUG_ASSERT_POINTER(pptimer->timer);
+
+	if( pptimer->set )
+	{
+		_mali_osk_timer_del( pptimer->timer );
+		pptimer->set = MALI_FALSE;
+		pptimer->expired = MALI_FALSE;
+		return MALI_TRUE;
+	}
+	
+	return MALI_FALSE;
+}
+
+mali_bool pmm_policy_timer_raise_event( _pmm_policy_timer_t *pptimer )
+{
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+
+	if( pptimer->expired )
+	{
+		_mali_uk_pmm_message_s event = {
+			NULL,
+			MALI_PMM_EVENT_TIMEOUT, /* Assume timeout id, but set it below */
+			0 };
+
+		event.id = pptimer->event_id;
+		event.data = (mali_pmm_message_data)pptimer->start;
+
+		/* Don't need to do any other notification with this timer */
+		pptimer->expired = MALI_FALSE;
+		/* Unset timer so it is free to be set again */
+		pptimer->set = MALI_FALSE;
+		
+		_mali_ukk_pmm_event_message( &event );
+				
+		return MALI_TRUE;
+	}
+	
+	return MALI_FALSE;
+}
+
+mali_bool pmm_policy_timer_valid( u32 timer_start, u32 other_start )
+{
+	return (_mali_osk_time_after( other_start, timer_start ) == 0);
+}
+
+
+_mali_osk_errcode_t pmm_policy_init(_mali_pmm_internal_state_t *pmm)
+{
+	_mali_osk_errcode_t err;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	switch( pmm->policy )
+	{
+		case MALI_PMM_POLICY_ALWAYS_ON:
+		{
+			err = pmm_policy_init_always_on();
+		}
+		break;
+
+		case MALI_PMM_POLICY_JOB_CONTROL:
+		{
+			err = pmm_policy_init_job_control(pmm);
+		}
+		break;
+
+		case MALI_PMM_POLICY_NONE:
+		default:
+			err = _MALI_OSK_ERR_FAULT;
+	}
+	
+	return err;
+}
+
+void pmm_policy_term(_mali_pmm_internal_state_t *pmm)
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	switch( pmm->policy )
+	{
+		case MALI_PMM_POLICY_ALWAYS_ON:
+		{
+			pmm_policy_term_always_on();
+		}
+		break;
+
+		case MALI_PMM_POLICY_JOB_CONTROL:
+		{
+			pmm_policy_term_job_control();
+		}
+		break;
+
+		case MALI_PMM_POLICY_NONE:
+		default:
+			MALI_PRINT_ERROR( ("PMM: Invalid policy terminated %d\n", pmm->policy) );
+	}
+}
+
+
+_mali_osk_errcode_t pmm_policy_process(_mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event)
+{
+	_mali_osk_errcode_t err;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(event);
+
+	switch( pmm->policy )
+	{
+		case MALI_PMM_POLICY_ALWAYS_ON:
+		{
+			err = pmm_policy_process_always_on( pmm, event );
+		}
+		break;
+
+		case MALI_PMM_POLICY_JOB_CONTROL:
+		{
+			err = pmm_policy_process_job_control( pmm, event );
+		}
+		break;
+
+		case MALI_PMM_POLICY_NONE:
+		default:
+			err = _MALI_OSK_ERR_FAULT;
+	}
+	
+	return err;
+}
+
+
+void pmm_policy_check_policy( _mali_pmm_internal_state_t *pmm )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	switch( pmm->policy )
+	{
+		case MALI_PMM_POLICY_JOB_CONTROL:
+		{
+			pmm_policy_check_job_control();
+		}
+		break;
+
+		default:
+			/* Nothing needs to be done */
+			break;
+	}
+}
+
+
+#endif /* USING_MALI_PMM */
+
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.h
new file mode 100644
index 0000000..75ac8c8
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy.h
+ * Defines the power management module policies
+ */
+
+#ifndef __MALI_PMM_POLICY_H__
+#define __MALI_PMM_POLICY_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup pmmapi Power Management Module APIs
+ *
+ * @{
+ *
+ * @defgroup pmmapi_policy Power Management Module Policies
+ *
+ * @{
+ */
+
+/** @brief Generic timer for use with policies
+ */
+typedef struct _pmm_policy_timer
+{
+	u32 timeout;                    /**< Timeout for this timer in ticks */
+	mali_pmm_event_id event_id;     /**< Event id that will be raised when timer expires */
+	_mali_osk_timer_t *timer;       /**< Timer */
+	mali_bool set;                  /**< Timer set */
+	mali_bool expired;              /**< Timer expired - event needs to be raised */
+	u32 start;                      /**< Timer start ticks */
+} _pmm_policy_timer_t;
+
+/** @brief Policy timer initialization
+ *
+ * This will create a timer for use in policies, but won't start it
+ *
+ * @param pptimer An empty timer structure to be initialized
+ * @param timeout Timeout in ticks for the timer
+ * @param id Event id that will be raised on timeout
+ * @return _MALI_OSK_ERR_OK if the policy could be initialized, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_timer_init( _pmm_policy_timer_t *pptimer, u32 timeout, mali_pmm_event_id id );
+
+/** @brief Policy timer termination
+ *
+ * This will clean up a timer that was previously used in policies, it
+ * will also stop it if started
+ *
+ * @param pptimer An initialized timer structure to be terminated
+ */
+void pmm_policy_timer_term( _pmm_policy_timer_t *pptimer );
+
+/** @brief Policy timer start
+ *
+ * This will start a previously created timer for use in policies
+ * When the timer expires after the initialized timeout it will raise
+ * a PMM event of the event id given on initialization
+ * As data for the event it will pass the start time of the timer
+ *
+ * @param pptimer A previously initialized policy timer
+ * @return MALI_TRUE if the timer was started, MALI_FALSE if it is already started
+ */
+mali_bool pmm_policy_timer_start( _pmm_policy_timer_t *pptimer );
+
+/** @brief Policy timer stop
+ *
+ * This will stop a previously created timer for use in policies
+ *
+ * @param pptimer A previously started policy timer
+ * @return MALI_TRUE if the timer was stopped, MALI_FALSE if it is already stopped
+ */
+mali_bool pmm_policy_timer_stop( _pmm_policy_timer_t *pptimer );
+
+/** @brief Policy timer stop
+ *
+ * This raise an event for an expired timer
+ *
+ * @param pptimer An expired policy timer
+ * @return MALI_TRUE if an event was raised, else MALI_FALSE
+ */
+mali_bool pmm_policy_timer_raise_event( _pmm_policy_timer_t *pptimer );
+
+/** @brief Policy timer valid checker
+ *
+ * This will check that a timer was started after a given time
+ *
+ * @param timer_start Time the timer was started
+ * @param other_start Time when another event or action occurred
+ * @return MALI_TRUE if the timer was started after the other time, else MALI_FALSE
+ */
+mali_bool pmm_policy_timer_valid( u32 timer_start, u32 other_start );
+
+
+/** @brief Common policy initialization
+ *
+ * This will initialize the current policy
+ *
+ * @note Any previously initialized policy should be terminated first
+ *
+ * @return _MALI_OSK_ERR_OK if the policy could be initialized, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_init( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Common policy termination
+ *
+ * This will terminate the current policy.
+ * @note This can be called when a policy has not been initialized
+ */
+void pmm_policy_term( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Common policy state changer
+ *
+ * Given the next available event message, this routine passes it to
+ * the current policy for processing
+ *
+ * @param pmm internal PMM state
+ * @param event PMM event to process
+ * @return _MALI_OSK_ERR_OK if the policy state completed okay, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_process( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event );
+
+
+/** @brief Common policy checker
+ *
+ * If a policy timer fires then this function will be called to
+ * allow the policy to take the correct action
+ *
+ * @param pmm internal PMM state
+ */
+void pmm_policy_check_policy( _mali_pmm_internal_state_t *pmm );
+
+/** @} */ /* End group pmmapi_policy */
+/** @} */ /* End group pmmapi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_POLICY_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.c
new file mode 100644
index 0000000..0a6b471
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy_alwayson.c
+ * Implementation of the power management module policy - always on
+ */
+
+#if USING_MALI_PMM
+
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+
+#include "mali_pmm.h"
+#include "mali_pmm_system.h"
+#include "mali_pmm_state.h"
+#include "mali_pmm_policy_alwayson.h"
+
+_mali_osk_errcode_t pmm_policy_init_always_on(void)
+{
+	/* Nothing to set up */
+	MALI_SUCCESS;
+}
+
+void pmm_policy_term_always_on(void)
+{
+	/* Nothing to tear down */
+}
+
+_mali_osk_errcode_t pmm_policy_process_always_on( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(event);
+
+	switch( event->id )
+	{
+		case MALI_PMM_EVENT_OS_POWER_DOWN:
+			/* We aren't going to do anything, but signal so we don't block the OS
+			 * NOTE: This may adversely affect any jobs Mali is currently running
+			 */
+			_mali_osk_pmm_power_down_done( event->data );
+		break;
+
+		case MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK:
+		case MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK:
+			/* Not expected in this policy */
+			MALI_DEBUG_ASSERT( MALI_FALSE );
+		break;
+
+		case MALI_PMM_EVENT_OS_POWER_UP:
+			/* Nothing to do */
+			_mali_osk_pmm_power_up_done( event->data );
+		break;
+		
+		case MALI_PMM_EVENT_JOB_SCHEDULED:
+		case MALI_PMM_EVENT_JOB_QUEUED:
+		case MALI_PMM_EVENT_JOB_FINISHED:
+			/* Nothing to do - we are always on */
+		break;
+	
+		case MALI_PMM_EVENT_TIMEOUT:
+			/* Not expected in this policy */
+			MALI_DEBUG_ASSERT( MALI_FALSE );
+		break;
+
+		default:
+		MALI_ERROR(_MALI_OSK_ERR_ITEM_NOT_FOUND);
+	}
+
+	MALI_SUCCESS;
+}
+
+#endif
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.h
new file mode 100644
index 0000000..da13224
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_alwayson.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy_alwayson.h
+ * Defines the power management module policy for always on
+ */
+
+#ifndef __MALI_PMM_POLICY_ALWAYSON_H__
+#define __MALI_PMM_POLICY_ALWAYSON_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup pmmapi_policy Power Management Module Policies
+ *
+ * @{
+ */
+
+/** @brief Always on policy initialization
+ *
+ * @return _MALI_OSK_ERR_OK if the policy could be initialized, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_init_always_on(void);
+
+/** @brief Always on policy termination
+ */
+void pmm_policy_term_always_on(void);
+
+/** @brief Always on policy state changer
+ *
+ * Given the next available event message, this routine processes it
+ * for the policy and changes state as needed.
+ *
+ * Always on policy will ignore all events and keep the Mali cores on
+ * all the time
+ *
+ * @param pmm internal PMM state
+ * @param event PMM event to process
+ * @return _MALI_OSK_ERR_OK if the policy state completed okay, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_process_always_on( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event );
+
+/** @} */ /* End group pmmapi_policies */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_POLICY_ALWAYSON_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.c
new file mode 100644
index 0000000..237d702
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy_jobcontrol.c
+ * Implementation of the power management module policy - job control
+ */
+
+#if USING_MALI_PMM
+
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+#include "mali_platform.h"
+
+#include "mali_pmm.h"
+#include "mali_pmm_system.h"
+#include "mali_pmm_state.h"
+#include "mali_pmm_policy.h"
+#include "mali_pmm_policy_jobcontrol.h"
+
+typedef struct _pmm_policy_data_job_control
+{
+	_pmm_policy_timer_t latency;  /**< Latency timeout timer for all cores */
+	u32 core_active_start;        /**< Last time a core was set to active */
+	u32 timeout;                  /**< Timeout in ticks for latency timer */
+} _pmm_policy_data_job_control_t;
+
+
+/* @ brief Local data for this policy 
+ */
+static _pmm_policy_data_job_control_t *data_job_control = NULL;
+
+/* @brief Set up the timeout if it hasn't already been set and if there are active cores */
+static void job_control_timeout_setup( _mali_pmm_internal_state_t *pmm, _pmm_policy_timer_t *pptimer )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+
+	/* Do we have an inactivity time out and some powered cores? */
+	if( pptimer->timeout > 0 && pmm->cores_powered != 0 )
+	{
+		/* Is the system idle and all the powered cores are idle? */
+		if( pmm->status == MALI_PMM_STATUS_IDLE && pmm->cores_idle == pmm->cores_powered )
+		{
+			if( pmm_policy_timer_start(pptimer) )
+			{
+				MALIPMM_DEBUG_PRINT( ("PMM policy - Job control: Setting in-activity latency timer\n") );
+			}
+		}
+		else
+		{
+			/* We are not idle so there is no need for an inactivity timer
+			 */
+			if( pmm_policy_timer_stop(pptimer) )
+			{
+				MALIPMM_DEBUG_PRINT( ("PMM policy - Job control: Removing in-activity latency timer\n") );
+			}
+		}
+	}
+}
+
+/* @brief Check the validity of the timeout - and if there is one set */
+static mali_bool job_control_timeout_valid( _mali_pmm_internal_state_t *pmm, _pmm_policy_timer_t *pptimer, u32 timer_start )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(pptimer);
+
+	/* Not a valid timer! */
+	if( pptimer->timeout == 0 ) return MALI_FALSE;
+
+	/* Are some cores powered and are they all idle? */
+	if( (pmm->cores_powered != 0) && (pmm->cores_idle == pmm->cores_powered) )
+	{
+		/* Has latency timeout started after the last core was active? */
+		if( pmm_policy_timer_valid( timer_start, data_job_control->core_active_start ) )
+		{
+			 return MALI_TRUE;
+		}
+		else
+		{
+			MALIPMM_DEBUG_PRINT( ("PMM: In-activity latency time out ignored - out of date\n") );
+		}
+	}
+	else
+	{
+		if( pmm->cores_powered == 0 )
+		{
+			MALIPMM_DEBUG_PRINT( ("PMM: In-activity latency time out ignored - cores already off\n") );
+		}
+		else
+		{
+			MALIPMM_DEBUG_PRINT( ("PMM: In-activity latency time out ignored - cores active\n") );
+		}
+	}
+
+	return MALI_FALSE;
+}
+
+_mali_osk_errcode_t pmm_policy_init_job_control( _mali_pmm_internal_state_t *pmm )
+{
+	_mali_osk_errcode_t err;
+	MALI_DEBUG_ASSERT_POINTER( pmm );
+	MALI_DEBUG_ASSERT( data_job_control == NULL );
+	
+	data_job_control = (_pmm_policy_data_job_control_t *) _mali_osk_malloc(sizeof(*data_job_control));
+	MALI_CHECK_NON_NULL( data_job_control, _MALI_OSK_ERR_NOMEM );
+
+	data_job_control->core_active_start = _mali_osk_time_tickcount();
+	data_job_control->timeout = MALI_PMM_POLICY_JOBCONTROL_INACTIVITY_TIMEOUT;
+	
+	err = pmm_policy_timer_init( &data_job_control->latency, data_job_control->timeout, MALI_PMM_EVENT_TIMEOUT );
+	if( err != _MALI_OSK_ERR_OK )
+	{
+		_mali_osk_free( data_job_control );
+		data_job_control = NULL;
+		return err;
+	}
+	
+	/* Start the latency timeout */
+	job_control_timeout_setup( pmm, &data_job_control->latency );
+	
+	MALI_SUCCESS;
+}
+
+void pmm_policy_term_job_control(void)
+{
+	if( data_job_control != NULL )
+	{
+		pmm_policy_timer_term( &data_job_control->latency );
+		_mali_osk_free( data_job_control );
+		data_job_control = NULL;
+	}
+}
+
+static void pmm_policy_job_control_job_queued( _mali_pmm_internal_state_t *pmm )
+{
+	mali_pmm_core_mask cores;
+	mali_pmm_core_mask cores_subset;
+
+	/* Make sure that all cores are powered in this
+	 * simple policy
+	 */
+	cores = pmm->cores_registered;
+	cores_subset = pmm_cores_to_power_up( pmm, cores );
+	if( cores_subset != 0 )
+	{
+		/* There are some cores that need powering up */
+		if( !pmm_invoke_power_up( pmm ) )
+		{
+			/* Need to wait until finished */
+			pmm->status = MALI_PMM_STATUS_POLICY_POWER_UP;
+		}
+	}
+}
+
+_mali_osk_errcode_t pmm_policy_process_job_control( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event )
+{
+	mali_pmm_core_mask cores;
+	mali_pmm_core_mask cores_subset;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(event);
+	MALI_DEBUG_ASSERT_POINTER(data_job_control);
+
+	MALIPMM_DEBUG_PRINT( ("PMM: Job control policy process start - status=%d\n", pmm->status) );
+
+	/* Mainly the data is the cores */
+	cores = pmm_cores_from_event_data( pmm, event );
+
+#if MALI_STATE_TRACKING
+	pmm->mali_last_pmm_status = pmm->status;
+#endif /* MALI_STATE_TRACKING */
+
+	switch( pmm->status )
+	{
+	/**************** IDLE ****************/
+	case MALI_PMM_STATUS_IDLE:
+		switch( event->id )
+		{
+		case MALI_PMM_EVENT_OS_POWER_UP:
+			/* Not expected in this state */
+			break;
+
+		case MALI_PMM_EVENT_JOB_SCHEDULED:
+
+			/* Update idle cores to indicate active - remove these! */
+			pmm_cores_set_active( pmm, cores );
+			/* Remember when this happened */
+			data_job_control->core_active_start = event->ts;
+#if MALI_POWER_MGMT_TEST_SUITE
+			_mali_osk_pmm_policy_events_notifications(MALI_PMM_EVENT_JOB_SCHEDULED);
+#endif
+
+			/*** FALL THROUGH to QUEUED to check POWER UP ***/
+
+		case MALI_PMM_EVENT_JOB_QUEUED:
+
+			pmm_policy_job_control_job_queued( pmm );
+#if MALI_POWER_MGMT_TEST_SUITE
+			_mali_osk_pmm_policy_events_notifications(MALI_PMM_EVENT_JOB_QUEUED);
+#endif
+			break;
+		
+		case MALI_PMM_EVENT_DVFS_PAUSE:
+
+			cores_subset = pmm_cores_to_power_down( pmm, cores, MALI_FALSE );
+			if ( cores_subset != 0 )
+			{
+				if ( !pmm_power_down_okay( pmm ) )
+				{
+					pmm->is_dvfs_active = 1;
+					pmm->status = MALI_PMM_STATUS_OS_POWER_DOWN;
+					pmm_save_os_event_data( pmm, event->data );
+					break;
+				}
+			}
+			pmm->status = MALI_PMM_STATUS_DVFS_PAUSE;
+			_mali_osk_pmm_dvfs_operation_done(0);
+			break;
+
+		case MALI_PMM_EVENT_OS_POWER_DOWN:
+
+			/* Need to power down all cores even if we need to wait for them */
+			cores_subset = pmm_cores_to_power_down( pmm, cores, MALI_FALSE );
+			if( cores_subset != 0 )
+			{
+				/* There are some cores that need powering down */
+				if( !pmm_invoke_power_down( pmm, MALI_POWER_MODE_DEEP_SLEEP ) )
+				{
+					/* We need to wait until they are idle */
+					
+					pmm->status = MALI_PMM_STATUS_OS_POWER_DOWN;
+					/* Save the OS data to respond later */
+					pmm_save_os_event_data( pmm, event->data );
+					/* Exit this case - as we have to wait */
+					break;
+				}
+			}
+			else
+			{
+				 mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
+
+			}
+			/* Set waiting status */
+			pmm->status = MALI_PMM_STATUS_OS_WAITING;
+			/* All cores now down - respond to OS power event */
+			_mali_osk_pmm_power_down_done( event->data );
+			break;
+
+		case MALI_PMM_EVENT_JOB_FINISHED:
+
+			/* Update idle cores - add these! */
+			pmm_cores_set_idle( pmm, cores );
+#if MALI_POWER_MGMT_TEST_SUITE
+			 _mali_osk_pmm_policy_events_notifications(MALI_PMM_EVENT_JOB_FINISHED);
+#endif
+			if( data_job_control->timeout > 0 )
+			{
+				/* Wait for time out to fire */
+				break;
+			}
+			/* For job control policy - turn off all cores */
+			cores = pmm->cores_powered;
+			
+			/*** FALL THROUGH to TIMEOUT TEST as NO TIMEOUT ***/
+
+		case MALI_PMM_EVENT_TIMEOUT:
+
+			/* Main job control policy - turn off cores after inactivity */
+			if( job_control_timeout_valid( pmm, &data_job_control->latency, (u32)event->data ) )
+ 			{
+				/* Valid timeout of inactivity - so find out if we can power down 
+				 * immedately - if we can't then this means the cores are still in fact
+				 * active 
+				 */
+				cores_subset = pmm_cores_to_power_down( pmm, cores, MALI_TRUE );
+				if( cores_subset != 0 )
+				{
+					/* Check if we can really power down, if not then we are not
+					 * really in-active
+					 */
+					if( !pmm_invoke_power_down( pmm, MALI_POWER_MODE_LIGHT_SLEEP ) )
+					{
+						pmm_power_down_cancel( pmm );
+					}
+				}
+				/* else there are no cores powered up! */
+			}
+#if MALI_POWER_MGMT_TEST_SUITE
+			_mali_osk_pmm_policy_events_notifications(MALI_PMM_EVENT_TIMEOUT);
+#endif
+			break;
+
+		default:
+			/* Unexpected event */
+			MALI_ERROR(_MALI_OSK_ERR_ITEM_NOT_FOUND);
+		}
+		break;
+
+	/******************DVFS PAUSE**************/
+	case MALI_PMM_STATUS_DVFS_PAUSE:
+		switch ( event->id )
+		{
+		case MALI_PMM_EVENT_DVFS_RESUME:
+
+			if ( pmm->cores_powered != 0 )
+			{
+				pmm->cores_ack_down =0;
+				pmm_power_down_cancel( pmm );
+				pmm->status = MALI_PMM_STATUS_IDLE;
+			}
+			else
+			{
+				pmm_policy_job_control_job_queued( pmm );
+			}
+			_mali_osk_pmm_dvfs_operation_done( 0 );
+			break;
+
+		case MALI_PMM_EVENT_OS_POWER_DOWN:
+			/* Set waiting status */
+			pmm->status = MALI_PMM_STATUS_OS_WAITING;
+			if ( pmm->cores_powered != 0 )
+			{
+				if ( pmm_invoke_power_down( pmm, MALI_POWER_MODE_DEEP_SLEEP ) )
+				{
+					_mali_osk_pmm_power_down_done( 0 );
+					break;
+				}
+			}
+			else
+			{
+				 mali_platform_power_mode_change(MALI_POWER_MODE_DEEP_SLEEP);
+			}
+			_mali_osk_pmm_power_down_done( 0 );
+			break;
+		default:
+			break;
+		}
+	break;
+
+	/**************** POWER UP ****************/
+	case MALI_PMM_STATUS_OS_POWER_UP:
+	case MALI_PMM_STATUS_POLICY_POWER_UP:
+		switch( event->id )
+		{
+		case MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK:
+			/* Make sure cores powered off equal what we expect */
+			MALI_DEBUG_ASSERT( cores == pmm->cores_pend_up );
+			pmm_cores_set_up_ack( pmm, cores );
+
+			if( pmm_invoke_power_up( pmm ) )
+			{
+				if( pmm->status == MALI_PMM_STATUS_OS_POWER_UP )
+				{
+					/* Get the OS data and respond to the power up */
+					_mali_osk_pmm_power_up_done( pmm_retrieve_os_event_data( pmm ) );
+				}
+				pmm->status = MALI_PMM_STATUS_IDLE;
+			}
+			break;
+
+		default:
+			/* Unexpected event */
+			MALI_ERROR(_MALI_OSK_ERR_ITEM_NOT_FOUND);
+		}
+		break;
+
+	/**************** POWER DOWN ****************/
+	case MALI_PMM_STATUS_OS_POWER_DOWN:
+	case MALI_PMM_STATUS_POLICY_POWER_DOWN:
+		switch( event->id )
+		{
+
+		case MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK:
+			
+			pmm_cores_set_down_ack( pmm, cores );
+			
+			if ( pmm->is_dvfs_active == 1 )
+			{
+				if( pmm_power_down_okay( pmm ) )
+				{
+					pmm->is_dvfs_active = 0;
+					pmm->status = MALI_PMM_STATUS_DVFS_PAUSE;
+					_mali_osk_pmm_dvfs_operation_done( pmm_retrieve_os_event_data( pmm ) );
+				}
+				break;
+			}
+			
+			/* Now check if we can power down */
+			if( pmm_invoke_power_down( pmm, MALI_POWER_MODE_DEEP_SLEEP ) )
+			{
+				if( pmm->status == MALI_PMM_STATUS_OS_POWER_DOWN )
+				{
+					/* Get the OS data and respond to the power down */
+					_mali_osk_pmm_power_down_done( pmm_retrieve_os_event_data( pmm ) );
+				}
+				pmm->status = MALI_PMM_STATUS_OS_WAITING;
+			}
+			break;
+
+		default:
+			/* Unexpected event */
+			MALI_ERROR(_MALI_OSK_ERR_ITEM_NOT_FOUND);
+		}
+		break;
+		
+	case MALI_PMM_STATUS_OS_WAITING:
+		switch( event->id )
+		{
+		case MALI_PMM_EVENT_OS_POWER_UP:
+			cores_subset = pmm_cores_to_power_up( pmm, cores );
+			if( cores_subset != 0 )
+			{
+				/* There are some cores that need powering up */
+				if( !pmm_invoke_power_up( pmm ) )
+				{
+					/* Need to wait until power up complete */
+					pmm->status = MALI_PMM_STATUS_OS_POWER_UP;
+					/* Save the OS data to respond later */
+					pmm_save_os_event_data( pmm, event->data );
+					/* Exit this case - as we have to wait */
+					break;
+				}
+			}
+			pmm->status = MALI_PMM_STATUS_IDLE;
+			/* All cores now up - respond to OS power up event */
+			_mali_osk_pmm_power_up_done( event->data );
+			break;
+			
+		default:
+			/* All other messages are ignored in this state */
+			break;
+		}
+		break;	
+	
+	default:
+		/* Unexpected state */
+		MALI_ERROR(_MALI_OSK_ERR_FAULT);
+	}
+
+	/* Set in-activity latency timer - if required */
+	job_control_timeout_setup( pmm, &data_job_control->latency );
+
+	/* Update the PMM state */
+	pmm_update_system_state( pmm );
+#if MALI_STATE_TRACKING
+	pmm->mali_new_event_status = event->id;
+#endif /* MALI_STATE_TRACKING */
+
+	MALIPMM_DEBUG_PRINT( ("PMM: Job control policy process end - status=%d and event=%d\n", pmm->status,event->id) );
+
+	MALI_SUCCESS;
+}
+
+void pmm_policy_check_job_control()
+{
+	MALI_DEBUG_ASSERT_POINTER(data_job_control);
+
+	/* Latency timer must have expired raise the event */
+	pmm_policy_timer_raise_event(&data_job_control->latency);
+}
+
+
+#endif /* USING_MALI_PMM */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.h
new file mode 100644
index 0000000..dcfa438
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_policy_jobcontrol.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_pmm_policy.h
+ * Defines the power management module policies
+ */
+
+#ifndef __MALI_PMM_POLICY_JOBCONTROL_H__
+#define __MALI_PMM_POLICY_JOBCONTROL_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup pmmapi_policy Power Management Module Policies
+ *
+ * @{
+ */
+
+/** @brief The jobcontrol policy inactivity latency timeout (in ticks)
+ * before the hardware is switched off
+ *
+ * @note Setting this low whilst tracing or producing debug output can
+ * cause alot of timeouts to fire which can affect the PMM behaviour
+ */
+#define MALI_PMM_POLICY_JOBCONTROL_INACTIVITY_TIMEOUT 50
+
+/** @brief Job control policy initialization
+ *
+ * @return _MALI_OSK_ERR_OK if the policy could be initialized, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_init_job_control(_mali_pmm_internal_state_t *pmm);
+
+/** @brief Job control policy termination
+ */
+void pmm_policy_term_job_control(void);
+
+/** @brief Job control policy state changer
+ *
+ * Given the next available event message, this routine processes it
+ * for the policy and changes state as needed.
+ *
+ * Job control policy depends on events from the Mali cores, and will
+ * power down all cores after an inactivity latency timeout. It will
+ * power the cores back on again when a job is scheduled to run.
+ *
+ * @param pmm internal PMM state
+ * @param event PMM event to process
+ * @return _MALI_OSK_ERR_OK if the policy state completed okay, or a suitable
+ * _mali_osk_errcode_t otherwise.
+ */
+_mali_osk_errcode_t pmm_policy_process_job_control( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event );
+
+/** @brief Job control policy checker
+ *
+ * The latency timer has fired and we need to raise the correct event to
+ * handle it
+ *
+ * @param pmm internal PMM state
+ */
+void pmm_policy_check_job_control(void);
+
+/** @} */ /* End group pmmapi_policy */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_POLICY_JOBCONTROL_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.c b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.c
new file mode 100644
index 0000000..d529b9a
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.c
@@ -0,0 +1,716 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#if USING_MALI_PMM
+
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_subsystem.h"
+
+#include "mali_pmm.h"
+#include "mali_pmm_state.h"
+#include "mali_pmm_system.h"
+
+#include "mali_kernel_core.h"
+#include "mali_platform.h"
+
+#define SIZEOF_CORES_LIST 6
+
+/* NOTE: L2 *MUST* be first on the list so that it
+ * is correctly powered on first and powered off last
+ */
+static mali_pmm_core_id cores_list[] = { MALI_PMM_CORE_L2,
+										MALI_PMM_CORE_GP,
+										MALI_PMM_CORE_PP0,
+										MALI_PMM_CORE_PP1,
+										MALI_PMM_CORE_PP2,
+										MALI_PMM_CORE_PP3 };
+
+
+
+void pmm_update_system_state( _mali_pmm_internal_state_t *pmm )
+{
+	mali_pmm_state state;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	if( pmm->cores_registered == 0 )
+	{
+		state = MALI_PMM_STATE_UNAVAILABLE;
+	}
+	else if( pmm->cores_powered == 0 )
+	{
+		state = MALI_PMM_STATE_SYSTEM_OFF;
+	}
+	else if( pmm->cores_powered == pmm->cores_registered )
+	{
+		state = MALI_PMM_STATE_SYSTEM_ON;
+	}
+	else
+	{
+		/* Some other state where not everything is on or off */
+		state = MALI_PMM_STATE_SYSTEM_TRANSITION;
+	}
+
+#if MALI_PMM_TRACE
+	_mali_pmm_trace_state_change( pmm->state, state );
+#endif
+	pmm->state = state;
+}
+
+mali_pmm_core_mask pmm_cores_from_event_data( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event )
+{
+	mali_pmm_core_mask cores;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_DEBUG_ASSERT_POINTER(event);
+
+	switch( event->id )
+	{
+	case MALI_PMM_EVENT_OS_POWER_UP:
+	case MALI_PMM_EVENT_OS_POWER_DOWN:
+		/* All cores - the system */
+		cores = pmm->cores_registered;
+		break;
+
+	case MALI_PMM_EVENT_JOB_SCHEDULED:
+	case MALI_PMM_EVENT_JOB_QUEUED:
+	case MALI_PMM_EVENT_JOB_FINISHED:
+	case MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK:
+	case MALI_PMM_EVENT_INTERNAL_POWER_DOWN_ACK:
+		/* Currently the main event data is only the cores
+		 * for these messages
+		 */
+		cores = (mali_pmm_core_mask)event->data;
+		if( cores == MALI_PMM_CORE_SYSTEM )
+		{
+			cores = pmm->cores_registered;
+		}
+		else if( cores == MALI_PMM_CORE_PP_ALL )
+		{
+			/* Get the subset of registered PP cores */
+			cores = (pmm->cores_registered & MALI_PMM_CORE_PP_ALL);
+		}
+		MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+		break;
+
+	default:
+		/* Assume timeout messages - report cores still powered */
+		cores = pmm->cores_powered;
+		break;
+	}
+
+	return cores;
+}
+
+mali_pmm_core_mask pmm_cores_to_power_up( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores )
+{
+	mali_pmm_core_mask cores_subset;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	/* Check that cores aren't pending power down when asked for power up */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_down == 0 );
+
+	cores_subset = (~(pmm->cores_powered) & cores);
+	if( cores_subset != 0 )
+	{
+		/* There are some cores that need powering up */
+		pmm->cores_pend_up = cores_subset;
+	}
+
+	return cores_subset;
+}
+
+mali_pmm_core_mask pmm_cores_to_power_down( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores, mali_bool immediate_only )
+{
+	mali_pmm_core_mask cores_subset;
+	_mali_osk_errcode_t err;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	/* Check that cores aren't pending power up when asked for power down */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_up == 0 );
+
+	cores_subset = (pmm->cores_powered & cores);
+	if( cores_subset != 0 )
+	{
+		int n;
+		volatile mali_pmm_core_mask *ppowered = &(pmm->cores_powered);
+
+		/* There are some cores that need powering up, but we may
+		 * need to wait until they are idle
+		 */
+		for( n = SIZEOF_CORES_LIST-1; n >= 0; n-- )
+		{
+			if( (cores_list[n] & cores_subset) != 0 )
+			{
+				/* Core is to be powered down */
+				pmm->cores_pend_down |= cores_list[n];
+
+				/* Can't hold the power lock, when acessing subsystem mutex via
+				 * the core power call.
+				 * Due to terminatation of driver requiring a subsystem mutex
+				 * and then power lock held to unregister a core.
+				 * This does mean that the following function could fail
+				 * as the core is unregistered before we tell it to power
+				 * down, but it does not matter as we are terminating
+				 */
+#if MALI_STATE_TRACKING
+                pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+				MALI_PMM_UNLOCK(pmm);
+				/* Signal the core to power down
+				 * If it is busy (not idle) it will set a pending power down flag 
+				 * (as long as we don't want to only immediately power down). 
+				 * If it isn't busy it will move out of the idle queue right
+				 * away
+				 */
+				err = mali_core_signal_power_down( cores_list[n], immediate_only );
+				MALI_PMM_LOCK(pmm);
+
+#if MALI_STATE_TRACKING
+                pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+			
+
+				/* Re-read cores_subset in case it has changed */
+				cores_subset = (*ppowered & cores);
+
+				if( err == _MALI_OSK_ERR_OK )
+				{
+					/* We moved an idle core to the power down queue
+					 * which means it is now acknowledged (if it is still 
+					 * registered)
+					 */
+					pmm->cores_ack_down |= (cores_list[n] & cores_subset);
+				}
+				else
+				{
+					MALI_DEBUG_PRINT(1,("PMM: In pmm_cores_to_power_down, the error and cores powered are..%x....%x",err,*ppowered));
+					MALI_DEBUG_ASSERT( err == _MALI_OSK_ERR_BUSY ||
+										(err == _MALI_OSK_ERR_FAULT &&
+										(*ppowered & cores_list[n]) == 0) );
+					/* If we didn't move a core - it must be active, so
+					 * leave it pending, so we get an acknowledgement (when
+					 * not in immediate only mode)
+					 * Alternatively we are shutting down and the core has
+					 * been unregistered
+					 */
+				}
+			}
+		}
+	}
+
+	return cores_subset;
+}
+
+void pmm_power_down_cancel( _mali_pmm_internal_state_t *pmm )
+{
+	int n;
+	mali_pmm_core_mask pd, ad;
+	_mali_osk_errcode_t err;
+	volatile mali_pmm_core_mask *pregistered;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	MALIPMM_DEBUG_PRINT( ("PMM: Cancelling power down\n") );
+
+	pd = pmm->cores_pend_down;
+	ad = pmm->cores_ack_down;
+	/* Clear the pending cores so that they don't move to the off
+	 * queue if they haven't already
+	 */
+	pmm->cores_pend_down = 0;
+	pmm->cores_ack_down = 0;
+	pregistered = &(pmm->cores_registered);
+
+	/* Power up all the pending power down cores - just so
+	 * we make sure the system is in a known state, as a
+	 * pending core might have sent an acknowledged message
+	 * which hasn't been read yet.
+	 */
+	for( n = 0; n < SIZEOF_CORES_LIST; n++ )
+	{
+		if( (cores_list[n] & pd) != 0 )
+		{
+			/* Can't hold the power lock, when acessing subsystem mutex via
+			 * the core power call.
+			 * Due to terminatation of driver requiring a subsystem mutex
+			 * and then power lock held to unregister a core.
+			 * This does mean that the following power up function could fail
+			 * as the core is unregistered before we tell it to power
+			 * up, but it does not matter as we are terminating
+			 */
+#if MALI_STATE_TRACKING
+			pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+			MALI_PMM_UNLOCK(pmm);
+			/* As we are cancelling - only move the cores back to the queue - 
+			 * no reset needed
+			 */
+			err = mali_core_signal_power_up( cores_list[n], MALI_TRUE );
+			MALI_PMM_LOCK(pmm);
+#if MALI_STATE_TRACKING
+			pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+			/* Update pending list with the current registered cores */
+			pd &= (*pregistered);
+
+			if( err != _MALI_OSK_ERR_OK )
+			{
+				MALI_DEBUG_ASSERT( (err == _MALI_OSK_ERR_BUSY && 
+										((cores_list[n] & ad) == 0))  ||
+										(err == _MALI_OSK_ERR_FAULT &&
+										(*pregistered & cores_list[n]) == 0) );
+				/* If we didn't power up a core - it must be active and 
+				 * hasn't actually tried to power down - this is expected
+				 * for cores that haven't acknowledged
+				 * Alternatively we are shutting down and the core has
+				 * been unregistered
+				 */
+			}
+		}
+	}
+	/* Only used in debug builds */
+	MALI_IGNORE(ad);
+}
+
+
+mali_bool pmm_power_down_okay( _mali_pmm_internal_state_t *pmm )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	return ( pmm->cores_pend_down == pmm->cores_ack_down ? MALI_TRUE : MALI_FALSE );
+}
+
+mali_bool pmm_invoke_power_down( _mali_pmm_internal_state_t *pmm, mali_power_mode power_mode )
+{
+	_mali_osk_errcode_t err;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	/* Check that cores are pending power down during power down invoke */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_down != 0 );
+	/* Check that cores are not pending power up during power down invoke */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_up == 0 );
+
+	if( !pmm_power_down_okay( pmm ) )
+	{
+		MALIPMM_DEBUG_PRINT( ("PMM: Waiting for cores to go idle for power off - 0x%08x / 0x%08x\n", 
+				pmm->cores_pend_down, pmm->cores_ack_down) );
+		return MALI_FALSE;
+	}
+	else
+	{
+		pmm->cores_powered &= ~(pmm->cores_pend_down);
+#if !MALI_PMM_NO_PMU
+		err = malipmm_powerdown( pmm->cores_pend_down, power_mode);
+#else
+		err = _MALI_OSK_ERR_OK;
+#endif
+		
+		if( err == _MALI_OSK_ERR_OK )
+		{
+#if MALI_PMM_TRACE
+			mali_pmm_core_mask old_power = pmm->cores_powered;
+#endif
+			/* Remove powered down cores from idle and powered list */
+			pmm->cores_idle &= ~(pmm->cores_pend_down);
+			/* Reset pending/acknowledged status */
+			pmm->cores_pend_down = 0;
+			pmm->cores_ack_down = 0;
+#if MALI_PMM_TRACE
+			_mali_pmm_trace_hardware_change( old_power, pmm->cores_powered );
+#endif
+		}
+		else
+		{
+			pmm->cores_powered |= pmm->cores_pend_down;
+			MALI_PRINT_ERROR( ("PMM: Failed to get PMU to power down cores - (0x%x) %s", 
+					pmm->cores_pend_down, pmm_trace_get_core_name(pmm->cores_pend_down)) );
+			pmm->fatal_power_err = MALI_TRUE;
+		}
+	}
+
+	return MALI_TRUE;
+}
+
+
+mali_bool pmm_power_up_okay( _mali_pmm_internal_state_t *pmm )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	return ( pmm->cores_pend_up == pmm->cores_ack_up ? MALI_TRUE : MALI_FALSE );
+}
+
+
+mali_bool pmm_invoke_power_up( _mali_pmm_internal_state_t *pmm )
+{
+	_mali_osk_errcode_t err;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+
+	/* Check that cores are pending power up during power up invoke */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_up != 0 );
+	/* Check that cores are not pending power down during power up invoke */
+	MALI_DEBUG_ASSERT( pmm->cores_pend_down == 0 );
+
+	if( pmm_power_up_okay( pmm ) )
+	{
+		/* Power up has completed - sort out subsystem core status */
+		
+		int n;
+		/* Use volatile to access, so that it is updated if any cores are unregistered */
+		volatile mali_pmm_core_mask *ppendup = &(pmm->cores_pend_up);
+#if MALI_PMM_TRACE
+		mali_pmm_core_mask old_power = pmm->cores_powered;
+#endif
+		/* Move cores into idle queues */
+		for( n = 0; n < SIZEOF_CORES_LIST; n++ )
+		{
+			if( (cores_list[n] & (*ppendup)) != 0 )
+			{
+				/* Can't hold the power lock, when acessing subsystem mutex via
+				 * the core power call.
+				 * Due to terminatation of driver requiring a subsystem mutex
+				 * and then power lock held to unregister a core.
+				 * This does mean that the following function could fail
+				 * as the core is unregistered before we tell it to power
+				 * up, but it does not matter as we are terminating
+				 */
+#if MALI_STATE_TRACKING
+				pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+				MALI_PMM_UNLOCK(pmm);
+				err = mali_core_signal_power_up( cores_list[n], MALI_FALSE );
+				MALI_PMM_LOCK(pmm);
+
+#if MALI_STATE_TRACKING
+				pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+
+				if( err != _MALI_OSK_ERR_OK )
+				{
+					MALI_DEBUG_PRINT(1,("In pmm_invoke_power_up:: The error and pending cores to be powered up are...%x...%x",err,*ppendup));
+					MALI_DEBUG_ASSERT( (err == _MALI_OSK_ERR_FAULT &&
+										(*ppendup & cores_list[n]) == 0) );
+					/* We only expect this to fail when we are shutting down 
+					 * and the core has been unregistered
+					 */
+				}
+			}
+		}
+		/* Finished power up - add cores to idle and powered list */
+		pmm->cores_powered |= (*ppendup);
+		pmm->cores_idle |= (*ppendup);
+		/* Reset pending/acknowledge status */
+		pmm->cores_pend_up = 0;
+		pmm->cores_ack_up = 0;
+
+#if MALI_PMM_TRACE
+		_mali_pmm_trace_hardware_change( old_power, pmm->cores_powered );
+#endif
+		return MALI_TRUE;
+	}
+	else
+	{
+#if !MALI_PMM_NO_PMU
+		/* Power up must now be done */
+		err = malipmm_powerup( pmm->cores_pend_up );
+#else
+		err = _MALI_OSK_ERR_OK;
+#endif
+		if( err != _MALI_OSK_ERR_OK )
+		{
+			MALI_PRINT_ERROR( ("PMM: Failed to get PMU to power up cores - (0x%x) %s", 
+					pmm->cores_pend_up, pmm_trace_get_core_name(pmm->cores_pend_up)) );
+			pmm->fatal_power_err = MALI_TRUE;
+		}
+		else
+		{
+			/* TBD - Update core status immediately rather than use event message */
+			_mali_uk_pmm_message_s event = {
+				NULL,
+				MALI_PMM_EVENT_INTERNAL_POWER_UP_ACK,
+				0 };
+			/* All the cores that were pending power up, have now completed power up */
+			event.data = pmm->cores_pend_up;
+			_mali_ukk_pmm_event_message( &event );
+			MALIPMM_DEBUG_PRINT( ("PMM: Sending ACK to power up") );
+		}
+	}
+
+	/* Always return false, as we need an interrupt to acknowledge
+	 * when power up is complete
+	 */
+	return MALI_FALSE;
+}
+
+mali_pmm_core_mask pmm_cores_set_active( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	pmm->cores_idle &= (~cores);
+	return pmm->cores_idle;
+}
+
+mali_pmm_core_mask pmm_cores_set_idle( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	pmm->cores_idle |= (cores);
+	return pmm->cores_idle;
+}
+
+mali_pmm_core_mask pmm_cores_set_down_ack( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	/* Check core is not pending a power down */
+	MALI_DEBUG_ASSERT( (pmm->cores_pend_down & cores) != 0 );
+	/* Check core has not acknowledged power down more than once */
+	MALI_DEBUG_ASSERT( (pmm->cores_ack_down & cores) == 0 );
+
+	pmm->cores_ack_down |= (cores);
+
+	return pmm->cores_ack_down;
+}
+
+void pmm_fatal_reset( _mali_pmm_internal_state_t *pmm )
+{
+	_mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+	_mali_osk_notification_t *msg = NULL;
+	mali_pmm_status status;
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALIPMM_DEBUG_PRINT( ("PMM: Fatal Reset called") ); 
+
+	MALI_DEBUG_ASSERT( pmm->status != MALI_PMM_STATUS_OFF );
+
+	/* Reset the common status */
+	pmm->waiting = 0;
+	pmm->missed = 0;
+	pmm->fatal_power_err = MALI_FALSE;
+	pmm->no_events = 0;
+	pmm->check_policy = MALI_FALSE;
+	pmm->cores_pend_down = 0;
+	pmm->cores_pend_up = 0;
+	pmm->cores_ack_down = 0;
+	pmm->cores_ack_up = 0;
+	pmm->is_dvfs_active = 0; 
+#if MALI_PMM_TRACE
+	pmm->messages_sent = 0;
+	pmm->messages_received = 0;
+	pmm->imessages_sent = 0;
+	pmm->imessages_received = 0;
+	MALI_PRINT( ("PMM Trace: *** Fatal reset occurred ***") );
+#endif
+
+	/* Set that we are unavailable whilst resetting */
+	pmm->state = MALI_PMM_STATE_UNAVAILABLE;
+	status = pmm->status;
+	pmm->status = MALI_PMM_STATUS_OFF;
+
+	/* We want all cores powered */
+	pmm->cores_powered = pmm->cores_registered;
+	/* The cores may not be idle, but this state will be rectified later */
+	pmm->cores_idle = pmm->cores_registered;
+	
+	/* So power on any cores that are registered */
+	if( pmm->cores_registered != 0 )
+	{
+		int n;
+		volatile mali_pmm_core_mask *pregistered = &(pmm->cores_registered);
+#if !MALI_PMM_NO_PMU
+		err = malipmm_powerup( pmm->cores_registered );
+#endif
+		if( err != _MALI_OSK_ERR_OK )
+		{
+			/* This is very bad as we can't even be certain the cores are now 
+			 * powered up
+			 */
+			MALI_PRINT_ERROR( ("PMM: Failed to perform PMM reset!\n") );
+			/* TBD driver exit? */
+		}
+
+		for( n = SIZEOF_CORES_LIST-1; n >= 0; n-- )
+		{
+			if( (cores_list[n] & (*pregistered)) != 0 )
+			{
+#if MALI_STATE_TRACKING
+				pmm->mali_pmm_lock_acquired = 0;
+#endif /* MALI_STATE_TRACKING */
+
+				MALI_PMM_UNLOCK(pmm);
+				/* Core is now active - so try putting it in the idle queue */
+				err = mali_core_signal_power_up( cores_list[n], MALI_FALSE );
+				MALI_PMM_LOCK(pmm);
+#if MALI_STATE_TRACKING
+                pmm->mali_pmm_lock_acquired = 1;
+#endif /* MALI_STATE_TRACKING */
+
+				/* We either succeeded, or we were not off anyway, or we have
+				 * just be deregistered 
+				 */
+				MALI_DEBUG_ASSERT( (err == _MALI_OSK_ERR_OK) ||
+									(err == _MALI_OSK_ERR_BUSY) ||
+									(err == _MALI_OSK_ERR_FAULT && 
+									(*pregistered & cores_list[n]) == 0) );
+			}
+		}
+	}
+
+	/* Unblock any pending OS event */
+	if( status == MALI_PMM_STATUS_OS_POWER_UP )
+	{
+		/* Get the OS data and respond to the power up */
+		_mali_osk_pmm_power_up_done( pmm_retrieve_os_event_data( pmm ) );
+	}
+	if( status == MALI_PMM_STATUS_OS_POWER_DOWN )
+	{
+		/* Get the OS data and respond to the power down 
+		 * NOTE: We are not powered down at this point due to power problems,
+		 * so we are lying to the system, but something bad has already 
+		 * happened and we are trying unstick things
+		 * TBD - Add busy loop to power down cores?
+		 */
+		_mali_osk_pmm_power_down_done( pmm_retrieve_os_event_data( pmm ) );
+	}
+		
+	/* Purge the event queues */
+	do
+	{
+		if( _mali_osk_notification_queue_dequeue( pmm->iqueue, &msg ) == _MALI_OSK_ERR_OK )
+		{
+			_mali_osk_notification_delete ( msg );
+			break;
+		}
+	} while (MALI_TRUE);
+
+	do
+	{
+		if( _mali_osk_notification_queue_dequeue( pmm->queue, &msg ) == _MALI_OSK_ERR_OK )
+		{
+			_mali_osk_notification_delete ( msg );
+			break;
+		}
+	} while (MALI_TRUE);
+
+	/* Return status/state to normal */
+	pmm->status = MALI_PMM_STATUS_IDLE;
+	pmm_update_system_state(pmm);
+}
+
+mali_pmm_core_mask pmm_cores_set_up_ack( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores )
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( pmm->cores_registered, cores );
+
+	/* Check core is not pending a power up */
+	MALI_DEBUG_ASSERT( (pmm->cores_pend_up & cores) != 0 );
+	/* Check core has not acknowledged power up more than once */
+	MALI_DEBUG_ASSERT( (pmm->cores_ack_up & cores) == 0 );
+
+	pmm->cores_ack_up |= (cores);
+
+	return pmm->cores_ack_up;
+}
+
+void pmm_save_os_event_data(_mali_pmm_internal_state_t *pmm, mali_pmm_message_data data)
+{
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	/* Check that there is no saved data */
+	MALI_DEBUG_ASSERT( pmm->os_data == 0 );
+	/* Can't store zero data - as retrieve check will fail */
+	MALI_DEBUG_ASSERT( data != 0 );
+
+	pmm->os_data = data;
+}
+
+mali_pmm_message_data pmm_retrieve_os_event_data(_mali_pmm_internal_state_t *pmm)
+{
+	mali_pmm_message_data data;
+
+	MALI_DEBUG_ASSERT_POINTER(pmm);
+	/* Check that there is saved data */
+	MALI_DEBUG_ASSERT( pmm->os_data != 0 );
+
+	/* Get data, and clear the saved version */
+	data = pmm->os_data;
+	pmm->os_data = 0;
+
+	return data;
+}
+
+/* Create list of core names to look up
+ * We are doing it this way to overcome the need for
+ * either string allocation, or stack space, so we
+ * use constant strings instead
+ */
+typedef struct pmm_trace_corelist
+{
+	mali_pmm_core_mask id;
+	const char *name;
+} pmm_trace_corelist_t;
+
+static pmm_trace_corelist_t pmm_trace_cores[] = {
+	{ MALI_PMM_CORE_SYSTEM,  "SYSTEM" },
+	{ MALI_PMM_CORE_GP,      "GP" },
+	{ MALI_PMM_CORE_L2,      "L2" },
+	{ MALI_PMM_CORE_PP0,     "PP0" },
+	{ MALI_PMM_CORE_PP1,     "PP1" },
+	{ MALI_PMM_CORE_PP2,     "PP2" },
+	{ MALI_PMM_CORE_PP3,     "PP3" },
+	{ MALI_PMM_CORE_PP_ALL,  "PP (all)" },
+	{ (MALI_PMM_CORE_GP | MALI_PMM_CORE_L2 | MALI_PMM_CORE_PP0),
+		"GP+L2+PP0" },
+	{ (MALI_PMM_CORE_GP | MALI_PMM_CORE_PP0),
+		"GP+PP0" },	
+	{ (MALI_PMM_CORE_GP | MALI_PMM_CORE_L2 | MALI_PMM_CORE_PP0 | MALI_PMM_CORE_PP1),
+		"GP+L2+PP0+PP1" },
+	{ (MALI_PMM_CORE_GP | MALI_PMM_CORE_PP0 | MALI_PMM_CORE_PP1),
+		"GP+PP0+PP1" },
+	{ 0, NULL } /* Terminator of list */
+};
+
+const char *pmm_trace_get_core_name( mali_pmm_core_mask cores )
+{
+	const char *dname = NULL;
+	int cl;
+	
+	/* Look up name in corelist */
+	cl = 0;
+	while( pmm_trace_cores[cl].name != NULL )
+	{
+		if( pmm_trace_cores[cl].id == cores )
+		{
+			dname = pmm_trace_cores[cl].name;
+			break;
+		}
+		cl++;
+	}
+	
+	if( dname == NULL )
+	{
+		/* We don't know a good short-hand for the configuration */
+		dname = "[multi-core]";
+	}
+
+	return dname;
+}
+
+#endif /* USING_MALI_PMM */
+
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.h
new file mode 100644
index 0000000..4768344
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_state.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_PMM_STATE_H__
+#define __MALI_PMM_STATE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup pmmapi Power Management Module APIs
+ *
+ * @{
+ *
+ * @defgroup pmmapi_state Power Management Module State
+ *
+ * @{
+ */
+
+/* Check that the subset is really a subset of cores */
+#define MALI_PMM_DEBUG_ASSERT_CORES_SUBSET( cores, subset ) \
+	MALI_DEBUG_ASSERT( ((~(cores)) & (subset)) == 0 )
+
+
+/* Locking macros */
+#define MALI_PMM_LOCK(pmm) \
+	_mali_osk_lock_wait( pmm->lock, _MALI_OSK_LOCKMODE_RW )
+#define MALI_PMM_UNLOCK(pmm) \
+	_mali_osk_lock_signal( pmm->lock, _MALI_OSK_LOCKMODE_RW )
+#define MALI_PMM_LOCK_TERM(pmm) \
+        _mali_osk_lock_term( pmm->lock )
+
+/* Notification type for messages */
+#define MALI_PMM_NOTIFICATION_TYPE 0
+
+/** @brief Status of the PMM state machine
+ */
+typedef enum mali_pmm_status_tag
+{
+	MALI_PMM_STATUS_IDLE,                       /**< PMM is waiting next event */
+	MALI_PMM_STATUS_POLICY_POWER_DOWN,          /**< Policy initiated power down */
+	MALI_PMM_STATUS_POLICY_POWER_UP,            /**< Policy initiated power down */
+        MALI_PMM_STATUS_OS_WAITING,                 /**< PMM is waiting for OS power up */
+	MALI_PMM_STATUS_OS_POWER_DOWN,              /**< OS initiated power down */
+	MALI_PMM_STATUS_DVFS_PAUSE,                 /**< PMM DVFS Status Pause */
+	MALI_PMM_STATUS_OS_POWER_UP,                /**< OS initiated power up */
+	MALI_PMM_STATUS_OFF,                        /**< PMM is not active */
+} mali_pmm_status;
+
+
+/** @brief Internal state of the PMM
+ */
+typedef struct _mali_pmm_internal_state
+{
+	mali_pmm_status status;                 /**< PMM state machine */
+	mali_pmm_policy policy;                 /**< PMM policy */
+	mali_bool check_policy;                 /**< PMM policy needs checking */
+	mali_pmm_state state;                   /**< PMM state */
+	mali_pmm_core_mask cores_registered;    /**< Bitmask of cores registered */
+	mali_pmm_core_mask cores_powered;       /**< Bitmask of cores powered up */
+	mali_pmm_core_mask cores_idle;          /**< Bitmask of cores idle */
+	mali_pmm_core_mask cores_pend_down;     /**< Bitmask of cores pending power down */
+	mali_pmm_core_mask cores_pend_up;       /**< Bitmask of cores pending power up */
+	mali_pmm_core_mask cores_ack_down;      /**< Bitmask of cores acknowledged power down */
+	mali_pmm_core_mask cores_ack_up;        /**< Bitmask of cores acknowledged power up */
+
+	_mali_osk_notification_queue_t *queue;  /**< PMM event queue */
+	_mali_osk_notification_queue_t *iqueue; /**< PMM internal event queue */
+	_mali_osk_irq_t *irq;                   /**< PMM irq handler */
+	_mali_osk_lock_t *lock;                 /**< PMM lock */
+
+	mali_pmm_message_data os_data;          /**< OS data sent via the OS events */
+
+	mali_bool pmu_initialized;              /**< PMU initialized */
+
+	_mali_osk_atomic_t messages_queued;     /**< PMM event messages queued */
+	u32 waiting;                            /**< PMM waiting events - due to busy */
+	u32 no_events;                          /**< PMM called to process when no events */
+
+	u32 missed;                             /**< PMM missed events due to OOM */
+	mali_bool fatal_power_err;				/**< PMM has had a fatal power error? */
+	u32 is_dvfs_active;			/**< PMM DVFS activity */
+
+#if MALI_STATE_TRACKING
+	mali_pmm_status mali_last_pmm_status;  /**< The previous PMM status */
+	mali_pmm_event_id mali_new_event_status;/**< The type of the last PMM event */
+	mali_bool mali_pmm_lock_acquired;      /**< Is the PMM lock held somewhere or not */
+#endif
+
+#if (MALI_PMM_TRACE || MALI_STATE_TRACKING)
+	u32 messages_sent;                      /**< Total event messages sent */
+	u32 messages_received;                  /**< Total event messages received */
+	u32 imessages_sent;                     /**< Total event internal messages sent */
+	u32 imessages_received;                 /**< Total event internal messages received */
+#endif
+} _mali_pmm_internal_state_t;
+
+/** @brief Sets that a policy needs a check before processing events
+ *
+ * A timer or something has expired that needs dealing with
+ */
+void malipmm_set_policy_check(void);
+
+/** @brief Update the PMM externally viewable state depending on the current PMM internal state
+ *
+ * @param pmm internal PMM state
+ * @return MALI_TRUE if the timeout is valid, else MALI_FALSE
+ */
+void pmm_update_system_state( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Returns the core mask from the event data - if applicable
+ *
+ * @param pmm internal PMM state
+ * @param event event message to get the core mask from
+ * @return mask of cores that is relevant to this event message
+ */
+mali_pmm_core_mask pmm_cores_from_event_data( _mali_pmm_internal_state_t *pmm, mali_pmm_message_t *event );
+
+/** @brief Sort out which cores need to be powered up from the given core mask
+ *
+ * All cores that can be powered up will be put into a pending state
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores to check if they need to be powered up
+ * @return mask of cores that need to be powered up, this can be 0 if all cores
+ * are powered up already
+ */
+mali_pmm_core_mask pmm_cores_to_power_up( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores );
+
+/** @brief Sort out which cores need to be powered down from the given core mask
+ *
+ * All cores that can be powered down will be put into a pending state. If they
+ * can be powered down immediately they will also be acknowledged that they can be
+ * powered down. If the immediate_only flag is set, then only those cores that
+ * can be acknowledged for power down will be put into a pending state.
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores to check if they need to be powered down
+ * @param immediate_only MALI_TRUE means that only cores that can power down now will
+ * be put into a pending state
+ * @return mask of cores that need to be powered down, this can be 0 if all cores
+ * are powered down already
+ */
+mali_pmm_core_mask pmm_cores_to_power_down( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores, mali_bool immediate_only );
+
+/** @brief Cancel an invokation to power down (pmm_invoke_power_down)
+ *
+ * @param pmm internal PMM state
+ */
+void pmm_power_down_cancel( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Check if a call to invoke power down should succeed, or fail
+ *
+ * This will report MALI_FALSE if some of the cores are still active and need
+ * to acknowledge that they are ready to power down
+ *
+ * @param pmm internal PMM state
+ * @return MALI_TRUE if the pending cores to power down have acknowledged they
+ * can power down, else MALI_FALSE
+ */
+mali_bool pmm_power_down_okay( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Try to make all the pending cores power down
+ *
+ * If all the pending cores have acknowledged they can power down, this will call the
+ * PMU power down function to turn them off
+ *
+ * @param pmm internal PMM state
+ * @return MALI_TRUE if the pending cores have been powered down, else MALI_FALSE
+ */
+mali_bool pmm_invoke_power_down( _mali_pmm_internal_state_t *pmm,  mali_power_mode power_mode );
+
+/** @brief Check if all the pending cores to power up have done so
+ *
+ * This will report MALI_FALSE if some of the cores are still powered off
+ * and have not acknowledged that they have powered up
+ *
+ * @param pmm internal PMM state
+ * @return MALI_TRUE if the pending cores to power up have acknowledged they
+ * are now powered up, else MALI_FALSE
+ */
+mali_bool pmm_power_up_okay( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Try to make all the pending cores power up
+ *
+ * If all the pending cores have acknowledged they have powered up, this will
+ * make the cores start processing jobs again, else this will call the PMU
+ * power up function to turn them on, and the PMM is then expected to wait for an
+ * interrupt to acknowledge the power up
+ *
+ * @param pmm internal PMM state
+ * @return MALI_TRUE if the pending cores have been powered up, else MALI_FALSE
+ */
+mali_bool pmm_invoke_power_up( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Set the cores that are now active in the system
+ *
+ * Updates which cores are active and returns which cores are still idle
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores to set to active
+ * @return mask of all the cores that are idle
+ */
+mali_pmm_core_mask pmm_cores_set_active( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores );
+
+/** @brief Set the cores that are now idle in the system
+ *
+ * Updates which cores are idle and returns which cores are still idle
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores to set to idle
+ * @return mask of all the cores that are idle
+ */
+mali_pmm_core_mask pmm_cores_set_idle( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores );
+
+/** @brief Set the cores that have acknowledged a pending power down
+ *
+ * Updates which cores have acknowledged the pending power down and are now ready
+ * to be turned off
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores that have acknowledged the pending power down
+ * @return mask of all the cores that have acknowledged the power down
+ */
+mali_pmm_core_mask pmm_cores_set_down_ack( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores );
+
+/** @brief Set the cores that have acknowledged a pending power up
+ *
+ * Updates which cores have acknowledged the pending power up and are now
+ * fully powered and ready to run jobs
+ *
+ * @param pmm internal PMM state
+ * @param cores mask of cores that have acknowledged the pending power up
+ * @return mask of all the cores that have acknowledged the power up
+ */
+mali_pmm_core_mask pmm_cores_set_up_ack( _mali_pmm_internal_state_t *pmm, mali_pmm_core_mask cores );
+
+
+/** @brief Tries to reset the PMM and PMU hardware to a known state after any fatal issues
+ *
+ * This will try and make all the cores powered up and reset the PMM state
+ * to its initial state after core registration - all cores powered but not
+ * pending or active.
+ * All events in the event queues will be thrown away.
+ *
+ * @note: Any pending power down will be cancelled including the OS calling for power down
+ */
+void pmm_fatal_reset( _mali_pmm_internal_state_t *pmm );
+
+/** @brief Save the OS specific data for an OS power up/down event
+ *
+ * @param pmm internal PMM state
+ * @param data OS specific event data
+ */
+void pmm_save_os_event_data(_mali_pmm_internal_state_t *pmm, mali_pmm_message_data data);
+
+/** @brief Retrieve the OS specific data for an OS power up/down event
+ *
+ * This will clear the stored OS data, as well as return it.
+ *
+ * @param pmm internal PMM state
+ * @return OS specific event data that was saved previously
+ */
+mali_pmm_message_data pmm_retrieve_os_event_data(_mali_pmm_internal_state_t *pmm);
+
+
+/** @brief Get a human readable name for the cores in a core mask
+ *
+ * @param core the core mask
+ * @return string containing a name relating to the given core mask
+ */
+const char *pmm_trace_get_core_name( mali_pmm_core_mask core );
+
+/** @} */ /* End group pmmapi_state */
+/** @} */ /* End group pmmapi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_STATE_H__ */
diff --git a/drivers/media/video/samsung/mali/common/pmm/mali_pmm_system.h b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_system.h
new file mode 100644
index 0000000..eccd35b
--- /dev/null
+++ b/drivers/media/video/samsung/mali/common/pmm/mali_pmm_system.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_PMM_SYSTEM_H__
+#define __MALI_PMM_SYSTEM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @addtogroup pmmapi Power Management Module APIs
+ *
+ * @{
+ *
+ * @defgroup pmmapi_system Power Management Module System Functions
+ *
+ * @{
+ */
+
+extern struct mali_kernel_subsystem mali_subsystem_pmm;
+
+/** @brief Register a core with the PMM, which will power up
+ * the core
+ *
+ * @param core the core to register with the PMM
+ * @return error if the core cannot be powered up
+ */
+_mali_osk_errcode_t malipmm_core_register( mali_pmm_core_id core );
+
+/** @brief Unregister a core with the PMM
+ *
+ * @param core the core to unregister with the PMM
+ */
+void malipmm_core_unregister( mali_pmm_core_id core );
+
+/** @brief Acknowledge that a power down is okay to happen
+ *
+ * A core should not be running a job, or be in the idle queue when this
+ * is called.
+ *
+ * @param core the core that can now be powered down
+ */
+void malipmm_core_power_down_okay( mali_pmm_core_id core );
+
+/** @} */ /* End group pmmapi_system */
+/** @} */ /* End group pmmapi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_PMM_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/license/gpl/mali_kernel_license.h b/drivers/media/video/samsung/mali/linux/license/gpl/mali_kernel_license.h
new file mode 100644
index 0000000..e9e5e55
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/license/gpl/mali_kernel_license.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_kernel_license.h
+ * Defines for the macro MODULE_LICENSE.
+ */
+
+#ifndef __MALI_KERNEL_LICENSE_H__
+#define __MALI_KERNEL_LICENSE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MALI_KERNEL_LINUX_LICENSE     "GPL"
+#define MALI_LICENSE_IS_GPL 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_KERNEL_LICENSE_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.c b/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.c
new file mode 100644
index 0000000..04f57d9
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_device_pause_resume.c
+ * Implementation of the Mali pause/resume functionality
+ */
+#if USING_MALI_PMM
+#include <linux/version.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_platform.h"
+#include "mali_linux_pm.h"
+#include "mali_device_pause_resume.h"
+#include "mali_pmm.h"
+#include "mali_kernel_license.h"
+#ifdef CONFIG_PM
+#if MALI_LICENSE_IS_GPL
+
+/* Mali Pause Resume APIs */
+int mali_dev_pause()
+{
+	int err = 0;
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+	if ((mali_dvfs_device_state ==  _MALI_DEVICE_SUSPEND)
+	      || (mali_device_state == _MALI_DEVICE_SUSPEND) )
+	{
+		err = -EPERM;
+	}
+	if ((mali_dvfs_device_state ==  _MALI_DEVICE_RESUME) && (!err))
+	{
+		mali_device_suspend(MALI_PMM_EVENT_DVFS_PAUSE, &dvfs_pm_thread);
+		mali_dvfs_device_state = _MALI_DEVICE_SUSPEND;
+	}
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return err;
+}
+
+EXPORT_SYMBOL(mali_dev_pause);
+
+int mali_dev_resume()
+{
+	int err = 0;
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+	if ((mali_dvfs_device_state == _MALI_DEVICE_RESUME)
+	     || (mali_device_state == _MALI_DEVICE_SUSPEND) )
+	{
+		err = -EPERM;
+	}
+	if (!err)
+	{
+		mali_device_resume(MALI_PMM_EVENT_DVFS_RESUME, &dvfs_pm_thread);
+		mali_dvfs_device_state = _MALI_DEVICE_RESUME;
+	}
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return err;
+}
+
+EXPORT_SYMBOL(mali_dev_resume);
+
+#endif /* MALI_LICENSE_IS_GPL */
+#endif /* CONFIG_PM */
+#endif /* USING_MALI_PMM */
diff --git a/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.h b/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.h
new file mode 100644
index 0000000..155a3e6
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_device_pause_resume.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_DEVICE_PAUSE_RESUME_H__
+#define __MALI_DEVICE_PAUSE_RESUME_H__
+
+#if USING_MALI_PMM
+int mali_dev_pause(void);
+int mali_dev_resume(void);
+#endif /* USING_MALI_PMM */
+
+#endif /* __MALI_DEVICE_PAUSE_RESUME_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_ioctl.h b/drivers/media/video/samsung/mali/linux/mali_kernel_ioctl.h
new file mode 100644
index 0000000..7e3a216
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_ioctl.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_IOCTL_H__
+#define __MALI_KERNEL_IOCTL_H__
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/fs.h>       /* file system operations */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @file mali_kernel_ioctl.h
+ * Interface to the Linux device driver.
+ * This file describes the interface needed to use the Linux device driver.
+ * Its interface is designed to used by the HAL implementation through a thin arch layer.
+ */
+
+/**
+ * ioctl commands
+ */
+
+#define MALI_IOC_BASE           0x82
+#define MALI_IOC_CORE_BASE      (_MALI_UK_CORE_SUBSYSTEM      + MALI_IOC_BASE)
+#define MALI_IOC_MEMORY_BASE    (_MALI_UK_MEMORY_SUBSYSTEM    + MALI_IOC_BASE)
+#define MALI_IOC_PP_BASE        (_MALI_UK_PP_SUBSYSTEM        + MALI_IOC_BASE)
+#define MALI_IOC_GP_BASE        (_MALI_UK_GP_SUBSYSTEM        + MALI_IOC_BASE)
+#define MALI_IOC_PROFILING_BASE (_MALI_UK_PROFILING_SUBSYSTEM + MALI_IOC_BASE)
+#define MALI_IOC_VSYNC_BASE     (_MALI_UK_VSYNC_SUBSYSTEM + MALI_IOC_BASE)
+
+#define MALI_IOC_GET_SYSTEM_INFO_SIZE       _IOR (MALI_IOC_CORE_BASE, _MALI_UK_GET_SYSTEM_INFO_SIZE, _mali_uk_get_system_info_s *)
+#define MALI_IOC_GET_SYSTEM_INFO            _IOR (MALI_IOC_CORE_BASE, _MALI_UK_GET_SYSTEM_INFO, _mali_uk_get_system_info_s *)
+#define MALI_IOC_WAIT_FOR_NOTIFICATION      _IOWR(MALI_IOC_CORE_BASE, _MALI_UK_WAIT_FOR_NOTIFICATION, _mali_uk_wait_for_notification_s *)
+#define MALI_IOC_GET_API_VERSION            _IOWR(MALI_IOC_CORE_BASE, _MALI_UK_GET_API_VERSION, _mali_uk_get_api_version_s *)
+#define MALI_IOC_POST_NOTIFICATION          _IOWR(MALI_IOC_CORE_BASE, _MALI_UK_POST_NOTIFICATION, _mali_uk_post_notification_s *)
+#define MALI_IOC_MEM_GET_BIG_BLOCK          _IOWR(MALI_IOC_MEMORY_BASE, _MALI_UK_GET_BIG_BLOCK, _mali_uk_get_big_block_s *)
+#define MALI_IOC_MEM_FREE_BIG_BLOCK         _IOW (MALI_IOC_MEMORY_BASE, _MALI_UK_FREE_BIG_BLOCK, _mali_uk_free_big_block_s *)
+#define MALI_IOC_MEM_INIT                   _IOR (MALI_IOC_MEMORY_BASE, _MALI_UK_INIT_MEM, _mali_uk_init_mem_s *)
+#define MALI_IOC_MEM_TERM                   _IOW (MALI_IOC_MEMORY_BASE, _MALI_UK_TERM_MEM, _mali_uk_term_mem_s *)
+#define MALI_IOC_MEM_MAP_EXT                _IOWR(MALI_IOC_MEMORY_BASE, _MALI_UK_MAP_EXT_MEM, _mali_uk_map_external_mem_s *)
+#define MALI_IOC_MEM_UNMAP_EXT              _IOW (MALI_IOC_MEMORY_BASE, _MALI_UK_UNMAP_EXT_MEM, _mali_uk_unmap_external_mem_s *)
+#define MALI_IOC_MEM_QUERY_MMU_PAGE_TABLE_DUMP_SIZE _IOR (MALI_IOC_MEMORY_BASE, _MALI_UK_QUERY_MMU_PAGE_TABLE_DUMP_SIZE, _mali_uk_query_mmu_page_table_dump_size_s *)
+#define MALI_IOC_MEM_DUMP_MMU_PAGE_TABLE    _IOWR(MALI_IOC_MEMORY_BASE, _MALI_UK_DUMP_MMU_PAGE_TABLE, _mali_uk_dump_mmu_page_table_s *)
+#define MALI_IOC_MEM_ATTACH_UMP             _IOWR(MALI_IOC_MEMORY_BASE, _MALI_UK_ATTACH_UMP_MEM, _mali_uk_attach_ump_mem_s *)
+#define MALI_IOC_MEM_RELEASE_UMP            _IOW(MALI_IOC_MEMORY_BASE, _MALI_UK_RELEASE_UMP_MEM, _mali_uk_release_ump_mem_s *)
+#define MALI_IOC_PP_START_JOB               _IOWR(MALI_IOC_PP_BASE, _MALI_UK_PP_START_JOB, _mali_uk_pp_start_job_s *)
+#define MALI_IOC_PP_NUMBER_OF_CORES_GET	    _IOR (MALI_IOC_PP_BASE, _MALI_UK_GET_PP_NUMBER_OF_CORES, _mali_uk_get_pp_number_of_cores_s *)
+#define MALI_IOC_PP_CORE_VERSION_GET	    _IOR (MALI_IOC_PP_BASE, _MALI_UK_GET_PP_CORE_VERSION, _mali_uk_get_pp_core_version_s * )
+#define MALI_IOC_PP_ABORT_JOB	            _IOW (MALI_IOC_PP_BASE, _MALI_UK_PP_ABORT_JOB, _mali_uk_pp_abort_job_s * )
+#define MALI_IOC_GP2_START_JOB              _IOWR(MALI_IOC_GP_BASE, _MALI_UK_GP_START_JOB, _mali_uk_gp_start_job_s *)
+#define MALI_IOC_GP2_ABORT_JOB              _IOWR(MALI_IOC_GP_BASE, _MALI_UK_GP_ABORT_JOB, _mali_uk_gp_abort_job_s *)
+#define MALI_IOC_GP2_NUMBER_OF_CORES_GET    _IOR (MALI_IOC_GP_BASE, _MALI_UK_GET_GP_NUMBER_OF_CORES, _mali_uk_get_gp_number_of_cores_s *)
+#define MALI_IOC_GP2_CORE_VERSION_GET	    _IOR (MALI_IOC_GP_BASE, _MALI_UK_GET_GP_CORE_VERSION, _mali_uk_get_gp_core_version_s *)
+#define MALI_IOC_GP2_SUSPEND_RESPONSE	    _IOW (MALI_IOC_GP_BASE, _MALI_UK_GP_SUSPEND_RESPONSE,_mali_uk_gp_suspend_response_s *)
+#define MALI_IOC_PROFILING_START            _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_START, _mali_uk_profiling_start_s *)
+#define MALI_IOC_PROFILING_ADD_EVENT        _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_ADD_EVENT, _mali_uk_profiling_add_event_s*)
+#define MALI_IOC_PROFILING_STOP             _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_STOP, _mali_uk_profiling_stop_s *)
+#define MALI_IOC_PROFILING_GET_EVENT        _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_GET_EVENT, _mali_uk_profiling_get_event_s *)
+#define MALI_IOC_PROFILING_CLEAR            _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_CLEAR, _mali_uk_profiling_clear_s *)
+#define MALI_IOC_TRANSFER_SW_COUNTERS       _IOW (MALI_IOC_PROFILING_BASE, _MALI_UK_TRANSFER_SW_COUNTERS, _mali_uk_sw_counters_s *)
+#define MALI_IOC_PROFILING_GET_CONFIG       _IOWR(MALI_IOC_PROFILING_BASE, _MALI_UK_PROFILING_GET_CONFIG, _mali_uk_profiling_get_config_s *)
+#define MALI_IOC_VSYNC_EVENT_REPORT         _IOW (MALI_IOC_VSYNC_BASE, _MALI_UK_VSYNC_EVENT_REPORT, _mali_uk_vsync_event_report_s *)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_KERNEL_IOCTL_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_linux.c b/drivers/media/video/samsung/mali/linux/mali_kernel_linux.c
new file mode 100644
index 0000000..05762ca
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_linux.c
@@ -0,0 +1,594 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_kernel_linux.c
+ * Implementation of the Linux device driver entrypoints
+ */
+#include <linux/module.h>   /* kernel module definitions */
+#include <linux/fs.h>       /* file system operations */
+#include <linux/cdev.h>     /* character device definitions */
+#include <linux/mm.h> /* memory mananger definitions */
+#include <linux/device.h>
+
+/* the mali kernel subsystem types */
+#include "mali_kernel_subsystem.h"
+
+/* A memory subsystem always exists, so no need to conditionally include it */
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_kernel_core.h"
+
+#include "mali_osk.h"
+#include "mali_kernel_linux.h"
+#include "mali_ukk.h"
+#include "mali_kernel_ioctl.h"
+#include "mali_ukk_wrappers.h"
+#include "mali_kernel_pm.h"
+#include "mali_linux_pm.h"
+
+#include "mali_kernel_sysfs.h"
+
+/* */
+#include "mali_kernel_license.h"
+
+#include "mali_platform.h"
+
+/* from the __malidrv_build_info.c file that is generated during build */
+extern const char *__malidrv_build_info(void);
+
+/* Module parameter to control log level */
+int mali_debug_level = 2;
+module_param(mali_debug_level, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_debug_level, "Higher number, more dmesg output");
+
+/* By default the module uses any available major, but it's possible to set it at load time to a specific number */
+#if MALI_MAJOR_PREDEFINE
+int mali_major = 244;
+#else
+int mali_major = 0;
+#endif
+module_param(mali_major, int, S_IRUGO); /* r--r--r-- */
+MODULE_PARM_DESC(mali_major, "Device major number");
+
+int mali_benchmark = 0;
+module_param(mali_benchmark, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_benchmark, "Bypass Mali hardware when non-zero");
+
+extern int mali_hang_check_interval;
+module_param(mali_hang_check_interval, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH);
+MODULE_PARM_DESC(mali_hang_check_interval, "Interval at which to check for progress after the hw watchdog has been triggered");
+
+extern int mali_max_job_runtime;
+module_param(mali_max_job_runtime, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH);
+MODULE_PARM_DESC(mali_max_job_runtime, "Maximum allowed job runtime in msecs.\nJobs will be killed after this no matter what");
+
+#if defined(USING_MALI400_L2_CACHE)
+extern int mali_l2_max_reads;
+module_param(mali_l2_max_reads, int, S_IRUSR | S_IRGRP | S_IROTH);
+MODULE_PARM_DESC(mali_l2_max_reads, "Maximum reads for Mali L2 cache");
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+extern int mali_boot_profiling;
+module_param(mali_boot_profiling, int, S_IRUSR | S_IRGRP | S_IROTH);
+MODULE_PARM_DESC(mali_boot_profiling, "Start profiling as a part of Mali driver initialization");
+#endif
+
+#if MALI_DVFS_ENABLED
+extern int mali_dvfs_control;
+module_param(mali_dvfs_control, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(mali_dvfs_control, "Mali Current DVFS");
+#if defined(CONFIG_CPU_EXYNOS4210)
+#else
+extern int step0_clk;
+module_param(step0_clk, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step0_clk, "Mali Current step0_clk");
+#ifdef DEBUG
+extern int step0_vol;
+module_param(step0_vol, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step0_vol, "Mali Current step0_vol");
+#endif
+
+#if (MALI_DVFS_STEPS > 1)
+extern int step1_clk;
+module_param(step1_clk, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step1_clk, "Mali Current step1_clk");
+
+extern int step0_up;
+module_param(step0_up, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step0_up, "Mali Current step0_up");
+
+extern int step1_down;
+module_param(step1_down, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step1_down, "Mali Current step1_down");
+#ifdef DEBUG
+extern int step1_vol;
+module_param(step1_vol, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step1_vol, "Mali Current step1_vol");
+#endif
+
+#if (MALI_DVFS_STEPS > 2)
+extern int step2_clk;
+module_param(step2_clk, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step2_clk, "Mali Current step2_clk");
+
+extern int step1_up;
+module_param(step1_up, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step1_up, "Mali Current step1_up");
+
+extern int step2_down;
+module_param(step2_down, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step2_down, "Mali Current step2_down");
+#ifdef DEBUG
+extern int step2_vol;
+module_param(step2_vol, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step2_vol, "Mali Current step2_vol");
+#endif
+
+#if (MALI_DVFS_STEPS > 3)
+extern int step3_clk;
+module_param(step3_clk, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step3_clk, "Mali Current step3_clk");
+
+extern int step2_up;
+module_param(step2_up, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step2_up, "Mali Current step2_up");
+
+extern int step3_down;
+module_param(step3_down, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step3_down, "Mali Current step3_down");
+#ifdef DEBUG
+extern int step3_vol;
+module_param(step3_vol, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP| S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(step3_vol, "Mali Current step3_vol");
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+
+extern int mali_gpu_clk;
+module_param(mali_gpu_clk, int, S_IRUSR | S_IRGRP | S_IROTH); /* r--r--r-- */
+MODULE_PARM_DESC(mali_gpu_clk, "Mali Current Clock");
+
+extern int mali_gpu_vol;
+module_param(mali_gpu_vol, int, S_IRUSR | S_IRGRP | S_IROTH); /* r--r--r-- */
+MODULE_PARM_DESC(mali_gpu_vol, "Mali Current Voltage");
+
+extern int gpu_power_state;
+module_param(gpu_power_state, int, S_IRUSR | S_IRGRP | S_IROTH); /* r--r--r-- */
+MODULE_PARM_DESC(gpu_power_state, "Mali Power State");
+extern _mali_device_power_states mali_dvfs_device_state;
+
+static char mali_dev_name[] = "mali"; /* should be const, but the functions we call requires non-cost */
+
+/* the mali device */
+static struct mali_dev device;
+
+
+static int mali_open(struct inode *inode, struct file *filp);
+static int mali_release(struct inode *inode, struct file *filp);
+#ifdef HAVE_UNLOCKED_IOCTL
+static long mali_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+#else
+static int mali_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
+#endif
+
+static int mali_mmap(struct file * filp, struct vm_area_struct * vma);
+
+/* Linux char file operations provided by the Mali module */
+struct file_operations mali_fops =
+{
+	.owner = THIS_MODULE,
+	.open = mali_open,
+	.release = mali_release,
+#ifdef HAVE_UNLOCKED_IOCTL
+	.unlocked_ioctl = mali_ioctl,
+#else
+	.ioctl = mali_ioctl,
+#endif
+	.mmap = mali_mmap
+};
+
+
+int mali_driver_init(void)
+{
+	int err;
+#if USING_MALI_PMM
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	err = _mali_dev_platform_register();
+	if (err)
+	{
+		return err;
+	}
+#endif
+#endif
+#endif
+	err = mali_kernel_constructor();
+	if (_MALI_OSK_ERR_OK != err)
+	{
+#if USING_MALI_PMM
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+		_mali_dev_platform_unregister();
+#endif
+#endif
+#endif
+		MALI_PRINT(("Failed to initialize driver (error %d)\n", err));
+		return -EFAULT;
+	}
+
+	/* print build options */
+	MALI_DEBUG_PRINT(2, ("%s\n", __malidrv_build_info()));
+
+    return 0;
+}
+
+void mali_driver_exit(void)
+{
+	mali_kernel_destructor();
+
+#if USING_MALI_PMM
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	_mali_dev_platform_unregister();
+#endif
+#endif
+#endif
+}
+
+/* called from _mali_osk_init */
+int initialize_kernel_device(void)
+{
+	int err;
+	dev_t dev = 0;
+	if (0 == mali_major)
+	{
+		/* auto select a major */
+		err = alloc_chrdev_region(&dev, 0/*first minor*/, 1/*count*/, mali_dev_name);
+		mali_major = MAJOR(dev);
+	}
+	else
+	{
+		/* use load time defined major number */
+		dev = MKDEV(mali_major, 0);
+		err = register_chrdev_region(dev, 1/*count*/, mali_dev_name);
+	}
+
+	if (err)
+	{
+			goto init_chrdev_err;
+	}
+
+	memset(&device, 0, sizeof(device));
+
+	/* initialize our char dev data */
+	cdev_init(&device.cdev, &mali_fops);
+	device.cdev.owner = THIS_MODULE;
+	device.cdev.ops = &mali_fops;
+
+	/* register char dev with the kernel */
+	err = cdev_add(&device.cdev, dev, 1/*count*/);
+	if (err)
+	{
+			goto init_cdev_err;
+	}
+
+	err = mali_sysfs_register(&device, dev, mali_dev_name);
+	if (err)
+	{
+			goto init_sysfs_err;
+	}
+
+	/* Success! */
+	return 0;
+
+init_sysfs_err:
+	cdev_del(&device.cdev);
+init_cdev_err:
+	unregister_chrdev_region(dev, 1/*count*/);
+init_chrdev_err:
+	return err;
+}
+
+/* called from _mali_osk_term */
+void terminate_kernel_device(void)
+{
+	dev_t dev = MKDEV(mali_major, 0);
+	
+	mali_sysfs_unregister(&device, dev, mali_dev_name);
+
+	/* unregister char device */
+	cdev_del(&device.cdev);
+	/* free major */
+	unregister_chrdev_region(dev, 1/*count*/);
+	return;
+}
+
+/** @note munmap handler is done by vma close handler */
+static int mali_mmap(struct file * filp, struct vm_area_struct * vma)
+{
+	struct mali_session_data * session_data;
+	_mali_uk_mem_mmap_s args = {0, };
+
+    session_data = (struct mali_session_data *)filp->private_data;
+	if (NULL == session_data)
+	{
+		MALI_PRINT_ERROR(("mmap called without any session data available\n"));
+		return -EFAULT;
+	}
+
+	MALI_DEBUG_PRINT(3, ("MMap() handler: start=0x%08X, phys=0x%08X, size=0x%08X\n", (unsigned int)vma->vm_start, (unsigned int)(vma->vm_pgoff << PAGE_SHIFT), (unsigned int)(vma->vm_end - vma->vm_start)) );
+
+	/* Re-pack the arguments that mmap() packed for us */
+	args.ctx = session_data;
+	args.phys_addr = vma->vm_pgoff << PAGE_SHIFT;
+	args.size = vma->vm_end - vma->vm_start;
+	args.ukk_private = vma;
+
+	/* Call the common mmap handler */
+	MALI_CHECK(_MALI_OSK_ERR_OK ==_mali_ukk_mem_mmap( &args ), -EFAULT);
+
+    return 0;
+}
+
+static int mali_open(struct inode *inode, struct file *filp)
+{
+	struct mali_session_data * session_data;
+    _mali_osk_errcode_t err;
+
+	/* input validation */
+	if (0 != MINOR(inode->i_rdev)) return -ENODEV;
+
+	/* allocated struct to track this session */
+    err = _mali_ukk_open((void **)&session_data);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	/* initialize file pointer */
+	filp->f_pos = 0;
+
+	/* link in our session data */
+	filp->private_data = (void*)session_data;
+
+	return 0;
+}
+
+static int mali_release(struct inode *inode, struct file *filp)
+{
+    _mali_osk_errcode_t err;
+
+    /* input validation */
+	if (0 != MINOR(inode->i_rdev)) return -ENODEV;
+
+    err = _mali_ukk_close((void **)&filp->private_data);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	return 0;
+}
+
+int map_errcode( _mali_osk_errcode_t err )
+{
+    switch(err)
+    {
+        case _MALI_OSK_ERR_OK : return 0;
+        case _MALI_OSK_ERR_FAULT: return -EFAULT;
+        case _MALI_OSK_ERR_INVALID_FUNC: return -ENOTTY;
+        case _MALI_OSK_ERR_INVALID_ARGS: return -EINVAL;
+        case _MALI_OSK_ERR_NOMEM: return -ENOMEM;
+        case _MALI_OSK_ERR_TIMEOUT: return -ETIMEDOUT;
+        case _MALI_OSK_ERR_RESTARTSYSCALL: return -ERESTARTSYS;
+        case _MALI_OSK_ERR_ITEM_NOT_FOUND: return -ENOENT;
+        default: return -EFAULT;
+    }
+}
+
+#ifdef HAVE_UNLOCKED_IOCTL
+static long mali_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+#else
+static int mali_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+#endif
+{
+	int err;
+	struct mali_session_data *session_data;
+
+#ifndef HAVE_UNLOCKED_IOCTL
+	/* inode not used */
+	(void)inode;
+#endif
+
+	MALI_DEBUG_PRINT(7, ("Ioctl received 0x%08X 0x%08lX\n", cmd, arg));
+
+	session_data = (struct mali_session_data *)filp->private_data;
+	if (NULL == session_data)
+	{
+		MALI_DEBUG_PRINT(7, ("filp->private_data was NULL\n"));
+		return -ENOTTY;
+	}
+
+	if (NULL == (void *)arg)
+	{
+		MALI_DEBUG_PRINT(7, ("arg was NULL\n"));
+		return -ENOTTY;
+	}
+
+	if (_MALI_DEVICE_SHUTDOWN == mali_dvfs_device_state)
+	{
+		MALI_DEBUG_PRINT(7, ("system is shutdown \n"));
+		return 0;
+	}
+
+	switch(cmd)
+	{
+		case MALI_IOC_GET_SYSTEM_INFO_SIZE:
+			err = get_system_info_size_wrapper(session_data, (_mali_uk_get_system_info_size_s __user *)arg);
+			break;
+
+		case MALI_IOC_GET_SYSTEM_INFO:
+			err = get_system_info_wrapper(session_data, (_mali_uk_get_system_info_s __user *)arg);
+			break;
+
+		case MALI_IOC_WAIT_FOR_NOTIFICATION:
+			err = wait_for_notification_wrapper(session_data, (_mali_uk_wait_for_notification_s __user *)arg);
+			break;
+
+		case MALI_IOC_GET_API_VERSION:
+			err = get_api_version_wrapper(session_data, (_mali_uk_get_api_version_s __user *)arg);
+			break;
+
+		case MALI_IOC_POST_NOTIFICATION:
+			err = post_notification_wrapper(session_data, (_mali_uk_post_notification_s __user *)arg);
+			break;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+		case MALI_IOC_PROFILING_START:
+			err = profiling_start_wrapper(session_data, (_mali_uk_profiling_start_s __user *)arg);
+			break;
+
+		case MALI_IOC_PROFILING_ADD_EVENT:
+			err = profiling_add_event_wrapper(session_data, (_mali_uk_profiling_add_event_s __user *)arg);
+			break;
+
+		case MALI_IOC_PROFILING_STOP:
+			err = profiling_stop_wrapper(session_data, (_mali_uk_profiling_stop_s __user *)arg);
+			break;
+
+		case MALI_IOC_PROFILING_GET_EVENT:
+			err = profiling_get_event_wrapper(session_data, (_mali_uk_profiling_get_event_s __user *)arg);
+			break;
+
+		case MALI_IOC_PROFILING_CLEAR:
+			err = profiling_clear_wrapper(session_data, (_mali_uk_profiling_clear_s __user *)arg);
+			break;
+
+		case MALI_IOC_PROFILING_GET_CONFIG:
+			err = profiling_get_config_wrapper(session_data, (_mali_uk_profiling_get_config_s __user *)arg);
+			break;
+#endif
+
+		case MALI_IOC_MEM_INIT:
+			err = mem_init_wrapper(session_data, (_mali_uk_init_mem_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_TERM:
+			err = mem_term_wrapper(session_data, (_mali_uk_term_mem_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_MAP_EXT:
+			err = mem_map_ext_wrapper(session_data, (_mali_uk_map_external_mem_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_UNMAP_EXT:
+			err = mem_unmap_ext_wrapper(session_data, (_mali_uk_unmap_external_mem_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_QUERY_MMU_PAGE_TABLE_DUMP_SIZE:
+			err = mem_query_mmu_page_table_dump_size_wrapper(session_data, (_mali_uk_query_mmu_page_table_dump_size_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_DUMP_MMU_PAGE_TABLE:
+			err = mem_dump_mmu_page_table_wrapper(session_data, (_mali_uk_dump_mmu_page_table_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_GET_BIG_BLOCK:
+			err = mem_get_big_block_wrapper(filp, (_mali_uk_get_big_block_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_FREE_BIG_BLOCK:
+			err = mem_free_big_block_wrapper(session_data, (_mali_uk_free_big_block_s __user *)arg);
+			break;
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+
+		case MALI_IOC_MEM_ATTACH_UMP:
+			err = mem_attach_ump_wrapper(session_data, (_mali_uk_attach_ump_mem_s __user *)arg);
+			break;
+
+		case MALI_IOC_MEM_RELEASE_UMP:
+			err = mem_release_ump_wrapper(session_data, (_mali_uk_release_ump_mem_s __user *)arg);
+			break;
+
+#else
+
+		case MALI_IOC_MEM_ATTACH_UMP:
+		case MALI_IOC_MEM_RELEASE_UMP: /* FALL-THROUGH */
+			MALI_DEBUG_PRINT(2, ("UMP not supported\n"));
+			err = -ENOTTY;
+			break;
+#endif
+
+		case MALI_IOC_PP_START_JOB:
+			err = pp_start_job_wrapper(session_data, (_mali_uk_pp_start_job_s __user *)arg);
+			break;
+
+		case MALI_IOC_PP_ABORT_JOB:
+			err = pp_abort_job_wrapper(session_data, (_mali_uk_pp_abort_job_s __user *)arg);
+			break;
+
+		case MALI_IOC_PP_NUMBER_OF_CORES_GET:
+			err = pp_get_number_of_cores_wrapper(session_data, (_mali_uk_get_pp_number_of_cores_s __user *)arg);
+			break;
+
+		case MALI_IOC_PP_CORE_VERSION_GET:
+			err = pp_get_core_version_wrapper(session_data, (_mali_uk_get_pp_core_version_s __user *)arg);
+			break;
+
+		case MALI_IOC_GP2_START_JOB:
+			err = gp_start_job_wrapper(session_data, (_mali_uk_gp_start_job_s __user *)arg);
+			break;
+
+		case MALI_IOC_GP2_ABORT_JOB:
+			err = gp_abort_job_wrapper(session_data, (_mali_uk_gp_abort_job_s __user *)arg);
+			break;
+
+		case MALI_IOC_GP2_NUMBER_OF_CORES_GET:
+			err = gp_get_number_of_cores_wrapper(session_data, (_mali_uk_get_gp_number_of_cores_s __user *)arg);
+			break;
+
+		case MALI_IOC_GP2_CORE_VERSION_GET:
+			err = gp_get_core_version_wrapper(session_data, (_mali_uk_get_gp_core_version_s __user *)arg);
+			break;
+
+		case MALI_IOC_GP2_SUSPEND_RESPONSE:
+			err = gp_suspend_response_wrapper(session_data, (_mali_uk_gp_suspend_response_s __user *)arg);
+			break;
+
+		case MALI_IOC_VSYNC_EVENT_REPORT:
+			err = vsync_event_report_wrapper(session_data, (_mali_uk_vsync_event_report_s __user *)arg);
+			break;
+#if MALI_TRACEPOINTS_ENABLED
+		case MALI_IOC_TRANSFER_SW_COUNTERS:
+			err = transfer_sw_counters_wrapper(session_data, (_mali_uk_sw_counters_s __user *)arg);
+#endif
+			break;
+
+		default:
+			MALI_DEBUG_PRINT(2, ("No handler for ioctl 0x%08X 0x%08lX\n", cmd, arg));
+			err = -ENOTTY;
+	};
+
+	return err;
+}
+
+
+module_init(mali_driver_init);
+module_exit(mali_driver_exit);
+
+MODULE_LICENSE(MALI_KERNEL_LINUX_LICENSE);
+MODULE_AUTHOR("ARM Ltd.");
+MODULE_VERSION(SVN_REV_STRING);
+
+#if MALI_TRACEPOINTS_ENABLED
+/* Create the trace points (otherwise we just get code to call a tracepoint) */
+#define CREATE_TRACE_POINTS
+#include "mali_linux_trace.h"
+#endif
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_linux.h b/drivers/media/video/samsung/mali/linux/mali_kernel_linux.h
new file mode 100644
index 0000000..9c7668c
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_linux.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_LINUX_H__
+#define __MALI_KERNEL_LINUX_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <linux/cdev.h>     /* character device definitions */
+#include "mali_kernel_license.h"
+#include "mali_osk.h"
+
+struct mali_dev
+{
+	struct cdev cdev;
+#if MALI_LICENSE_IS_GPL
+	struct class *  mali_class;
+#endif
+};
+
+_mali_osk_errcode_t initialize_kernel_device(void);
+void terminate_kernel_device(void);
+
+void mali_osk_low_level_mem_init(void);
+void mali_osk_low_level_mem_term(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_KERNEL_LINUX_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_pm.c b/drivers/media/video/samsung/mali/linux/mali_kernel_pm.c
new file mode 100644
index 0000000..f06ea4b
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_pm.c
@@ -0,0 +1,709 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_kernel_pm.c
+ * Implementation of the Linux Power Management for Mali GPU kernel driver
+ */
+
+#if USING_MALI_PMM
+#include <linux/sched.h>
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif /* CONFIG_PM_RUNTIME */
+
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <asm/current.h>
+#include <linux/suspend.h>
+
+#include <plat/cpu.h>
+#include <plat/pd.h>
+#include <plat/devs.h>
+
+#include "mali_platform.h"
+#include "mali_osk.h"
+#include "mali_uk_types.h"
+#include "mali_pmm.h"
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_license.h"
+#include "mali_kernel_pm.h"
+#include "mali_device_pause_resume.h"
+#include "mali_linux_pm.h"
+
+#ifdef MALI_REBOOTNOTIFIER
+_mali_osk_atomic_t mali_shutdown_state;
+#include <linux/reboot.h>
+#endif
+
+#if MALI_GPU_UTILIZATION
+#include "mali_kernel_utilization.h"
+#endif /* MALI_GPU_UTILIZATION */
+
+#if MALI_POWER_MGMT_TEST_SUITE
+#ifdef CONFIG_PM
+#include "mali_linux_pm_testsuite.h"
+#include "mali_platform_pmu_internal_testing.h"
+unsigned int pwr_mgmt_status_reg = 0;
+#endif /* CONFIG_PM */
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+
+static int is_os_pmm_thread_waiting = 0;
+
+/* kernel should be configured with power management support */
+#ifdef CONFIG_PM
+
+/* License should be GPL */
+#if MALI_LICENSE_IS_GPL
+
+/* Linux kernel major version */
+#define LINUX_KERNEL_MAJOR_VERSION 2
+
+/* Linux kernel minor version */
+#define LINUX_KERNEL_MINOR_VERSION 6
+
+/* Linux kernel development version */
+#define LINUX_KERNEL_DEVELOPMENT_VERSION 29
+
+#ifdef CONFIG_PM_DEBUG
+static const char* const mali_states[_MALI_MAX_DEBUG_OPERATIONS] = {
+	[_MALI_DEVICE_SUSPEND] = "suspend",
+	[_MALI_DEVICE_RESUME] = "resume",
+	[_MALI_DVFS_PAUSE_EVENT] = "dvfs_pause",
+	[_MALI_DVFS_RESUME_EVENT] = "dvfs_resume",
+};
+
+#endif /* CONFIG_PM_DEBUG */
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+extern void set_mali_parent_power_domain(struct platform_device* dev);
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+static int mali_pwr_suspend_notifier(struct notifier_block *nb,unsigned long event,void* dummy);
+
+static struct notifier_block mali_pwr_notif_block = {
+	.notifier_call = mali_pwr_suspend_notifier
+};
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+/* Power management thread pointer */
+struct task_struct *pm_thread;
+
+/* dvfs power management thread */
+struct task_struct *dvfs_pm_thread;
+
+/* is wake up needed */
+short is_wake_up_needed = 0;
+int timeout_fired = 2;
+unsigned int is_mali_pmm_testsuite_enabled = 0;
+
+_mali_device_power_states mali_device_state = _MALI_DEVICE_RESUME;
+_mali_device_power_states mali_dvfs_device_state = _MALI_DEVICE_RESUME;
+_mali_osk_lock_t *lock;
+
+#if MALI_POWER_MGMT_TEST_SUITE
+
+const char* const mali_pmm_recording_events[_MALI_DEVICE_MAX_PMM_EVENTS] = {
+	[_MALI_DEVICE_PMM_TIMEOUT_EVENT] = "timeout",
+	[_MALI_DEVICE_PMM_JOB_SCHEDULING_EVENTS] = "job_scheduling",
+	[_MALI_DEVICE_PMM_REGISTERED_CORES] = "cores",
+
+};
+
+unsigned int mali_timeout_event_recording_on = 0;
+unsigned int mali_job_scheduling_events_recording_on = 0;
+unsigned int is_mali_pmu_present = 0;
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+
+/* Function prototypes */
+static int mali_pm_probe(struct platform_device *pdev);
+static int mali_pm_remove(struct platform_device *pdev);
+static void mali_pm_shutdown(struct platform_device *pdev);
+
+/* Mali device suspend function */
+static int mali_pm_suspend(struct device *dev);
+
+/* Mali device resume function */
+static int mali_pm_resume(struct device *dev);
+
+/* Run time suspend and resume functions */
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+static int mali_device_runtime_suspend(struct device *dev);
+static int mali_device_runtime_resume(struct device *dev);
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+/* OS suspend and resume callbacks */
+#if !MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#ifndef CONFIG_PM_RUNTIME
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+static int mali_pm_os_suspend(struct platform_device *pdev, pm_message_t state);
+#else
+static int mali_pm_os_suspend(struct device *dev);
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+static int mali_pm_os_resume(struct platform_device *pdev);
+#else
+static int mali_pm_os_resume(struct device *dev);
+#endif
+#endif /* CONFIG_PM_RUNTIME */
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+
+/* OS Hibernation suspend callback */
+static int mali_pm_os_suspend_on_hibernation(struct device *dev);
+
+/* OS Hibernation resume callback */
+static int mali_pm_os_resume_on_hibernation(struct device *dev);
+
+static void _mali_release_pm(struct device* device);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+static const struct dev_pm_ops mali_dev_pm_ops = {
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	.runtime_suspend = mali_device_runtime_suspend,
+	.runtime_resume = mali_device_runtime_resume,
+#endif  /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif  /* CONFIG_PM_RUNTIME */
+
+#ifndef CONFIG_PM_RUNTIME
+#if !MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	.suspend = mali_pm_os_suspend,
+	.resume = mali_pm_os_resume,
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+	.freeze = mali_pm_os_suspend_on_hibernation,
+	.poweroff = mali_pm_os_suspend_on_hibernation,
+	.thaw = mali_pm_os_resume_on_hibernation,
+	.restore = mali_pm_os_resume_on_hibernation,
+};
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+struct pm_ext_ops mali_pm_operations = {
+	.base = {
+		.freeze = mali_pm_os_suspend_on_hibernation,
+		.thaw =   mali_pm_os_resume_on_hibernation,
+		.poweroff = mali_pm_os_resume_on_hibernation,
+		.restore = mali_pm_os_resume_on_hibernation,
+	},
+};
+#endif
+
+static struct platform_driver mali_plat_driver = {
+	.probe  = mali_pm_probe,
+	.remove = mali_pm_remove,
+	.shutdown = mali_pm_shutdown,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+#ifndef CONFIG_PM_RUNTIME
+#if !MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	.suspend = mali_pm_os_suspend,
+	.resume  = mali_pm_os_resume,
+#endif /* CONFIG_PM_RUNTIME */
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+	.pm = &mali_pm_operations,
+#endif
+
+	.driver         = {
+		.name   = "mali_dev",
+		.owner  = THIS_MODULE,
+		.bus = &platform_bus_type,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+		.pm = &mali_dev_pm_ops,
+#endif
+		},
+};
+
+/* Mali GPU platform device */
+struct platform_device mali_gpu_device = {
+	.name = "mali_dev",
+	.id = 0,
+	.dev.release = _mali_release_pm
+};
+
+/** This function is called when platform device is unregistered. This function
+ * is necessary when the platform device is unregistered.
+ */
+static void _mali_release_pm(struct device *device)
+{
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI Platform device removed\n" ));
+}
+
+#if MALI_POWER_MGMT_TEST_SUITE
+void mali_is_pmu_present(void)
+{
+	int temp = 0;
+	temp = pmu_get_power_up_down_info();
+	if (4095 == temp)
+	{
+		is_mali_pmu_present = 0;
+	}
+	else
+	{
+		is_mali_pmu_present = 1;
+	}
+}
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+#endif /* MALI_LICENSE_IS_GPL */
+
+#if MALI_LICENSE_IS_GPL
+
+static int mali_wait_for_power_management_policy_event(void)
+{
+	int err = 0;
+	for (; ;)
+	{
+		set_current_state(TASK_INTERRUPTIBLE);
+		if (signal_pending(current))
+		{
+			err = -EINTR;
+			break;
+		}
+		if (is_wake_up_needed == 1)
+		{
+			break;
+		}
+		schedule();
+	}
+	__set_current_state(TASK_RUNNING);
+	is_wake_up_needed =0;
+	return err;
+}
+
+/** This function is invoked when mali device is suspended
+ */
+int mali_device_suspend(unsigned int event_id, struct task_struct **pwr_mgmt_thread)
+{
+	int err = 0;	
+	_mali_uk_pmm_message_s event = {
+	                               NULL,
+	                               event_id,
+	                               timeout_fired};
+	*pwr_mgmt_thread = current;
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI device is being suspended\n" ));
+	_mali_ukk_pmm_event_message(&event);
+	is_os_pmm_thread_waiting = 1;
+	err = mali_wait_for_power_management_policy_event();
+	is_os_pmm_thread_waiting = 0;
+	return err;
+}
+
+/** This function is called when Operating system wants to power down
+ * the mali GPU device.
+ */
+static int mali_pm_suspend(struct device *dev)
+{
+	int err = 0;
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+	if ((mali_device_state == _MALI_DEVICE_SUSPEND))
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return err;
+	}
+#if MALI_DVFS_ENABLED
+	mali_utilization_suspend();
+#endif
+	err = mali_device_suspend(MALI_PMM_EVENT_OS_POWER_DOWN, &pm_thread);
+	mali_device_state = _MALI_DEVICE_SUSPEND;
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return err;
+}
+
+#ifndef CONFIG_PM_RUNTIME
+#if !MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+static int mali_pm_os_suspend(struct platform_device *pdev, pm_message_t state)
+#else
+static int mali_pm_os_suspend(struct device *dev)
+#endif
+{
+	int err = 0;
+	err = mali_pm_suspend(NULL);
+	return err;
+}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+static int mali_pwr_suspend_notifier(struct notifier_block *nb,unsigned long event,void* dummy)
+{
+	int err = 0;
+	switch (event)
+	{
+		case PM_SUSPEND_PREPARE:
+			err = mali_pm_suspend(NULL);
+		break;
+
+		case PM_POST_SUSPEND:
+			err = mali_pm_resume(NULL);
+		break;
+		default:
+		break;
+	}
+	return 0;
+}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+/** This function is called when mali GPU device is to be resumed.
+ */
+int mali_device_resume(unsigned int event_id, struct task_struct **pwr_mgmt_thread)
+{
+	int err = 0;
+	_mali_uk_pmm_message_s event = {
+	                               NULL,
+	                               event_id,
+	                               timeout_fired};
+	*pwr_mgmt_thread = current;
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI device is being resumed\n" ));
+	_mali_ukk_pmm_event_message(&event);
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI Power up  event is scheduled\n" ));
+	is_os_pmm_thread_waiting = 1;
+	err = mali_wait_for_power_management_policy_event();
+	is_os_pmm_thread_waiting = 0;
+	return err;
+}
+
+/** This function is called when mali GPU device is to be resumed
+ */
+static int mali_pm_resume(struct device *dev)
+{
+	int err = 0;
+
+	_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
+
+#ifdef CONFIG_REGULATOR
+	mali_regulator_enable();
+#endif
+
+	if (mali_device_state == _MALI_DEVICE_RESUME)
+	{
+		_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+		return err;
+	}
+	err = mali_device_resume(MALI_PMM_EVENT_OS_POWER_UP, &pm_thread);
+	mali_device_state = _MALI_DEVICE_RESUME;
+	mali_dvfs_device_state = _MALI_DEVICE_RESUME;
+	_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
+	return err;
+}
+
+#ifndef CONFIG_PM_RUNTIME
+#if !MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(LINUX_KERNEL_MAJOR_VERSION,LINUX_KERNEL_MINOR_VERSION,LINUX_KERNEL_DEVELOPMENT_VERSION))
+static int mali_pm_os_resume(struct platform_device *pdev)
+#else
+static int mali_pm_os_resume(struct device *dev)
+#endif
+{
+	int err = 0;
+	err = mali_pm_resume(NULL);
+	return err;
+}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+static int mali_pm_os_suspend_on_hibernation(struct device *dev)
+{
+	int err = 0;
+	err = mali_pm_suspend(NULL);
+	return err;
+}
+
+static int mali_pm_os_resume_on_hibernation(struct device *dev)
+{
+	int err = 0;
+	err = mali_pm_resume(NULL);
+	return err;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+/** This function is called when runtime suspend of mali device is required.
+ */
+static int mali_device_runtime_suspend(struct device *dev)
+{
+	MALI_DEBUG_PRINT(4, ("PMMDEBUG: Mali device Run time suspended \n" ));
+	return 0;
+}
+
+/** This function is called when runtime resume of mali device is required.
+ */
+static int mali_device_runtime_resume(struct device *dev)
+{
+	MALI_DEBUG_PRINT(4, ("PMMDEBUG: Mali device Run time Resumed \n" ));
+	return 0;
+}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /*  CONFIG_PM_RUNTIME */
+
+#ifdef CONFIG_PM_DEBUG
+
+/** This function is used for debugging purposes when the user want to see
+ * which power management operations are supported for
+ * mali device.
+ */
+static ssize_t show_file(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	char *str = buf;
+#if !MALI_POWER_MGMT_TEST_SUITE
+	int pm_counter = 0;
+	for (pm_counter = 0; pm_counter<_MALI_MAX_DEBUG_OPERATIONS; pm_counter++) 
+	{
+		str += sprintf(str, "%s  ", mali_states[pm_counter]);
+	}
+#else
+	str += sprintf(str, "%d  ",pwr_mgmt_status_reg);
+#endif
+	if (str != buf)
+	{
+		*(str-1) = '\n';
+	}
+	return (str-buf);
+}
+
+/** This function is called when user wants to suspend the mali GPU device in order
+ * to simulate the power up and power down events.
+ */
+static ssize_t store_file(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+	int err = 0;
+
+#if MALI_POWER_MGMT_TEST_SUITE
+	int test_flag_dvfs = 0;
+        pwr_mgmt_status_reg = 0;
+        mali_is_pmu_present();
+
+#endif
+	if (!strncmp(buf,mali_states[_MALI_DEVICE_SUSPEND],strlen(mali_states[_MALI_DEVICE_SUSPEND])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI suspend Power operation is scheduled\n" ));
+		err = mali_pm_suspend(NULL);
+	}
+
+#if MALI_POWER_MGMT_TEST_SUITE
+	else if (!strncmp(buf,mali_pmm_recording_events[_MALI_DEVICE_PMM_REGISTERED_CORES],strlen(mali_pmm_recording_events[_MALI_DEVICE_PMM_REGISTERED_CORES])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI Device get number of registerd cores\n" ));
+		pwr_mgmt_status_reg = _mali_pmm_cores_list();
+		return count;
+	}
+	else if (!strncmp(buf,mali_pmm_recording_events[_MALI_DEVICE_PMM_TIMEOUT_EVENT],strlen(mali_pmm_recording_events[_MALI_DEVICE_PMM_TIMEOUT_EVENT])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI timeout event recording is enabled\n" ));
+		mali_timeout_event_recording_on = 1;
+	}
+	else if (!strncmp(buf,mali_pmm_recording_events[_MALI_DEVICE_PMM_JOB_SCHEDULING_EVENTS],strlen(mali_pmm_recording_events[_MALI_DEVICE_PMM_JOB_SCHEDULING_EVENTS])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI Job scheduling  events recording is enabled\n" ));
+		mali_job_scheduling_events_recording_on = 1;
+	}
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+
+	else if (!strncmp(buf,mali_states[_MALI_DEVICE_RESUME],strlen(mali_states[_MALI_DEVICE_RESUME]))) 
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI Resume Power operation is scheduled\n" ));
+		err = mali_pm_resume(NULL);
+	}
+	else if (!strncmp(buf,mali_states[_MALI_DVFS_PAUSE_EVENT],strlen(mali_states[_MALI_DVFS_PAUSE_EVENT])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI DVFS Pause Power operation is scheduled\n" ));
+		err = mali_dev_pause();
+#if MALI_POWER_MGMT_TEST_SUITE
+		test_flag_dvfs = 1;
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+	}
+	else if (!strncmp(buf,mali_states[_MALI_DVFS_RESUME_EVENT],strlen(mali_states[_MALI_DVFS_RESUME_EVENT])))
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: MALI DVFS Resume Power operation is scheduled\n" ));
+		err = mali_dev_resume();
+#if MALI_POWER_MGMT_TEST_SUITE
+		test_flag_dvfs = 1;
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+	}
+	else 
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: Invalid Power Mode Operation selected\n" ));
+	}
+#if MALI_POWER_MGMT_TEST_SUITE
+	if (test_flag_dvfs == 1)
+	{
+		if (err)
+		{
+			pwr_mgmt_status_reg = 2;
+		}
+		else
+		{
+			pwr_mgmt_status_reg = 1;
+		}
+	}
+	else
+	{
+		if (1 == is_mali_pmu_present)
+		{
+			pwr_mgmt_status_reg = pmu_get_power_up_down_info();
+		}
+	}
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+	return count;
+}
+
+/* Device attribute file */
+static DEVICE_ATTR(file, 0644, show_file, store_file);
+#endif /* CONFIG_PM_DEBUG */
+
+static int mali_pm_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_DEBUG
+	device_remove_file(&mali_gpu_device.dev, &dev_attr_file);
+#endif /* CONFIG_PM_DEBUG */
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	pm_runtime_disable(&pdev->dev);
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+	return 0;
+}
+
+int mali_pd_enable(void)
+{
+	return exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev);
+}
+
+static void mali_pm_shutdown(struct platform_device *pdev)
+{
+	MALI_PRINT(("Mali shutdown!!\n"));
+	mali_dvfs_device_state =_MALI_DEVICE_SHUTDOWN;
+	exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev);
+	return;
+}
+
+/** This function is called when the device is probed */
+static int mali_pm_probe(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_DEBUG
+	int err;
+	err = device_create_file(&mali_gpu_device.dev, &dev_attr_file);
+	if (err)
+	{
+		MALI_DEBUG_PRINT(4, ("PMMDEBUG: Error in creating device file\n" ));
+	}
+#endif /* CONFIG_PM_DEBUG */
+	return 0;
+}
+#ifdef MALI_REBOOTNOTIFIER
+static int mali_reboot_notify(struct notifier_block *this,
+	unsigned long code, void *unused)
+{
+	_mali_osk_atomic_inc_return(&mali_shutdown_state);
+	mali_dvfs_device_state = _MALI_DEVICE_SHUTDOWN;
+	MALI_PRINT(("REBOOT Notifier for mali\n"));
+	return NOTIFY_DONE;
+}
+static struct notifier_block mali_reboot_notifier = {
+	.notifier_call = mali_reboot_notify,
+};
+#endif
+
+/** This function is called when Mali GPU device is initialized
+ */
+int _mali_dev_platform_register(void)
+{
+	int err;
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON	
+	set_mali_parent_power_domain((void *)&mali_gpu_device);
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	err = register_pm_notifier(&mali_pwr_notif_block);
+	if (err)
+	{
+		return err;
+	}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+#ifdef MALI_REBOOTNOTIFIER
+	_mali_osk_atomic_init(&mali_shutdown_state, 0);
+	err = register_reboot_notifier(&mali_reboot_notifier);
+	if (err) {
+		MALI_PRINT(("Failed to setup reboot notifier\n"));
+		return err;
+	}
+#endif
+
+	err = platform_device_register(&mali_gpu_device);
+	lock = _mali_osk_lock_init((_mali_osk_lock_flags_t)( _MALI_OSK_LOCKFLAG_READERWRITER | _MALI_OSK_LOCKFLAG_ORDERED), 0, 0);
+	if (!err) 
+	{
+		err = platform_driver_register(&mali_plat_driver);
+		if (err)
+		{
+			_mali_osk_lock_term(lock);
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+			unregister_pm_notifier(&mali_pwr_notif_block);
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+#ifdef MALI_REBOOTNOTIFIER
+	unregister_reboot_notifier(&mali_reboot_notifier);
+#endif
+
+			platform_device_unregister(&mali_gpu_device);
+		}
+	}
+	return err;
+}
+
+/** This function is called when Mali GPU device is unloaded
+ */
+void _mali_dev_platform_unregister(void)
+{
+	_mali_osk_lock_term(lock);
+
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	unregister_pm_notifier(&mali_pwr_notif_block);
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+
+#ifdef MALI_REBOOTNOTIFIER
+	unregister_reboot_notifier(&mali_reboot_notifier);
+#endif
+	platform_driver_unregister(&mali_plat_driver);
+	platform_device_unregister(&mali_gpu_device);
+}
+
+int mali_get_ospmm_thread_state(void)
+{
+	return is_os_pmm_thread_waiting;
+}
+
+#endif /* MALI_LICENSE_IS_GPL */
+#endif /* CONFIG_PM */
+
+#if MALI_STATE_TRACKING
+u32 mali_pmm_dump_os_thread_state( char *buf, u32 size )
+{
+	return snprintf(buf, size, "OSPMM: OS PMM thread is waiting: %s\n", is_os_pmm_thread_waiting ? "true" : "false");
+}
+#endif /* MALI_STATE_TRACKING */
+#endif /* USING_MALI_PMM */
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_pm.h b/drivers/media/video/samsung/mali/linux/mali_kernel_pm.h
new file mode 100644
index 0000000..1c44439
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_pm.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_PM_H__
+#define __MALI_KERNEL_PM_H__
+
+#ifdef USING_MALI_PMM
+int _mali_dev_platform_register(void);
+void _mali_dev_platform_unregister(void);
+#endif /* USING_MALI_PMM */
+int mali_pd_enable(void);
+
+#endif /* __MALI_KERNEL_PM_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.c b/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.c
new file mode 100644
index 0000000..6dcf052
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+
+/**
+ * @file mali_kernel_sysfs.c
+ * Implementation of some sysfs data exports
+ */
+
+#include <linux/fs.h>
+#include <linux/device.h>
+#include "mali_kernel_license.h"
+#include "mali_kernel_linux.h"
+#include "mali_ukk.h"
+
+#if MALI_LICENSE_IS_GPL
+
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
+#include <asm/uaccess.h>
+#include <linux/slab.h>
+#include "mali_kernel_subsystem.h"
+#include "mali_kernel_sysfs.h"
+#include "mali_kernel_profiling.h"
+
+static struct dentry *mali_debugfs_dir = NULL;
+
+#if MALI_STATE_TRACKING
+static int mali_seq_internal_state_show(struct seq_file *seq_file, void *v)
+{
+	u32 len = 0;
+	u32 size;
+	char *buf;
+
+	size = seq_get_buf(seq_file, &buf);
+
+	if(!size)
+	{
+			return -ENOMEM;
+	}
+
+	/* Create the internal state dump. */
+	len  = snprintf(buf+len, size-len, "Mali device driver %s\n", SVN_REV_STRING);
+	len += snprintf(buf+len, size-len, "License: %s\n\n", MALI_KERNEL_LINUX_LICENSE);
+
+	len += _mali_kernel_core_dump_state(buf + len, size - len);
+
+	seq_commit(seq_file, len);
+
+	return 0;
+}
+
+static int mali_seq_internal_state_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mali_seq_internal_state_show, NULL);
+}
+
+static const struct file_operations mali_seq_internal_state_fops = {
+	.owner = THIS_MODULE,
+	.open = mali_seq_internal_state_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+#endif /* MALI_STATE_TRACKING */
+
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+static ssize_t profiling_record_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char buf[64];
+	int r;
+
+	r = sprintf(buf, "%u\n", _mali_profiling_is_recording() ? 1 : 0);
+	return simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
+}
+
+static ssize_t profiling_record_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char buf[64];
+	unsigned long val;
+	int ret;
+
+	if (cnt >= sizeof(buf))
+	{
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&buf, ubuf, cnt))
+	{
+		return -EFAULT;
+	}
+
+	buf[cnt] = 0;
+
+	ret = strict_strtoul(buf, 10, &val);
+	if (ret < 0)
+	{
+		return ret;
+	}
+
+	if (val != 0)
+	{
+		u32 limit = MALI_PROFILING_MAX_BUFFER_ENTRIES; /* This can be made configurable at a later stage if we need to */
+
+		/* check if we are already recording */
+		if (MALI_TRUE == _mali_profiling_is_recording())
+		{
+			MALI_DEBUG_PRINT(3, ("Recording of profiling events already in progress\n"));
+			return -EFAULT;
+		}
+
+		/* check if we need to clear out an old recording first */
+		if (MALI_TRUE == _mali_profiling_have_recording())
+		{
+			if (_MALI_OSK_ERR_OK != _mali_profiling_clear())
+			{
+				MALI_DEBUG_PRINT(3, ("Failed to clear existing recording of profiling events\n"));
+				return -EFAULT;
+			}
+		}
+
+		/* start recording profiling data */
+		if (_MALI_OSK_ERR_OK != _mali_profiling_start(&limit))
+		{
+			MALI_DEBUG_PRINT(3, ("Failed to start recording of profiling events\n"));
+			return -EFAULT;
+		}
+
+		MALI_DEBUG_PRINT(3, ("Profiling recording started (max %u events)\n", limit));
+	}
+	else
+	{
+		/* stop recording profiling data */
+		u32 count = 0;
+		if (_MALI_OSK_ERR_OK != _mali_profiling_stop(&count))
+		{
+			MALI_DEBUG_PRINT(2, ("Failed to stop recording of profiling events\n"));
+			return -EFAULT;
+		}
+		
+		MALI_DEBUG_PRINT(2, ("Profiling recording stopped (recorded %u events)\n", count));
+	}
+
+	*ppos += cnt;
+	return cnt;
+}
+
+static const struct file_operations profiling_record_fops = {
+	.owner = THIS_MODULE,
+	.read  = profiling_record_read,
+	.write = profiling_record_write,
+};
+
+static void *profiling_events_start(struct seq_file *s, loff_t *pos)
+{
+	loff_t *spos;
+
+	/* check if we have data avaiable */
+	if (MALI_TRUE != _mali_profiling_have_recording())
+	{
+		return NULL;
+	}
+
+	spos = kmalloc(sizeof(loff_t), GFP_KERNEL);
+	if (NULL == spos)
+	{
+		return NULL;
+	}
+
+	*spos = *pos;
+	return spos;
+}
+
+static void *profiling_events_next(struct seq_file *s, void *v, loff_t *pos)
+{
+	loff_t *spos = v;
+
+	/* check if we have data avaiable */
+	if (MALI_TRUE != _mali_profiling_have_recording())
+	{
+		return NULL;
+	}
+
+	/* check if the next entry actually is avaiable */
+	if (_mali_profiling_get_count() <= (u32)(*spos + 1))
+	{
+		return NULL;
+	}
+
+	*pos = ++*spos;
+	return spos;
+}
+
+static void profiling_events_stop(struct seq_file *s, void *v)
+{
+	kfree(v);
+}
+
+static int profiling_events_show(struct seq_file *seq_file, void *v)
+{
+	loff_t *spos = v;
+	u32 index;
+	u64 timestamp;
+	u32 event_id;
+	u32 data[5];
+
+	index = (u32)*spos;
+
+	/* Retrieve all events */
+	if (_MALI_OSK_ERR_OK == _mali_profiling_get_event(index, &timestamp, &event_id, data))
+	{
+		seq_printf(seq_file, "%llu %u %u %u %u %u %u\n", timestamp, event_id, data[0], data[1], data[2], data[3], data[4]);
+		return 0;
+	}
+
+	return 0;
+}
+
+static const struct seq_operations profiling_events_seq_ops = {
+	.start = profiling_events_start,
+	.next  = profiling_events_next,
+	.stop  = profiling_events_stop,
+	.show  = profiling_events_show
+};
+
+static int profiling_events_open(struct inode *inode, struct file *file)
+{
+	return seq_open(file, &profiling_events_seq_ops);
+}
+
+static const struct file_operations profiling_events_fops = {
+	.owner = THIS_MODULE,
+	.open = profiling_events_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+};
+
+static ssize_t profiling_proc_default_enable_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char buf[64];
+	int r;
+
+	r = sprintf(buf, "%u\n", _mali_profiling_get_default_enable_state() ? 1 : 0);
+	return simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
+}
+
+static ssize_t profiling_proc_default_enable_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char buf[64];
+	unsigned long val;
+	int ret;
+
+	if (cnt >= sizeof(buf))
+	{
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&buf, ubuf, cnt))
+	{
+		return -EFAULT;
+	}
+
+	buf[cnt] = 0;
+
+	ret = strict_strtoul(buf, 10, &val);
+	if (ret < 0)
+	{
+		return ret;
+	}
+
+	_mali_profiling_set_default_enable_state(val != 0 ? MALI_TRUE : MALI_FALSE);
+
+	*ppos += cnt;
+	return cnt;
+}
+
+static const struct file_operations profiling_proc_default_enable_fops = {
+	.owner = THIS_MODULE,
+	.read  = profiling_proc_default_enable_read,
+	.write = profiling_proc_default_enable_write,
+};
+#endif
+
+static ssize_t memory_used_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char buf[64];
+	size_t r;
+	u32 mem = _mali_ukk_report_memory_usage();
+
+	r = snprintf(buf, 64, "%u\n", mem);
+	return simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
+}
+
+static const struct file_operations memory_usage_fops = {
+	.owner = THIS_MODULE,
+	.read = memory_used_read,
+};
+
+int mali_sysfs_register(struct mali_dev *device, dev_t dev, const char *mali_dev_name)
+{
+	int err = 0;
+	struct device * mdev;
+
+	device->mali_class = class_create(THIS_MODULE, mali_dev_name);
+	if (IS_ERR(device->mali_class))
+	{
+		err = PTR_ERR(device->mali_class);
+		goto init_class_err;
+	}
+	mdev = device_create(device->mali_class, NULL, dev, NULL, mali_dev_name);
+	if (IS_ERR(mdev))
+	{
+		err = PTR_ERR(mdev);
+		goto init_mdev_err;
+	}
+
+	mali_debugfs_dir = debugfs_create_dir(mali_dev_name, NULL);
+	if(ERR_PTR(-ENODEV) == mali_debugfs_dir)
+	{
+		/* Debugfs not supported. */
+		mali_debugfs_dir = NULL;
+	}
+	else
+	{
+		if(NULL != mali_debugfs_dir)
+		{
+			/* Debugfs directory created successfully; create files now */
+#if MALI_TIMELINE_PROFILING_ENABLED
+			struct dentry *mali_profiling_dir = debugfs_create_dir("profiling", mali_debugfs_dir);
+			if (mali_profiling_dir != NULL)
+			{
+				struct dentry *mali_profiling_proc_dir = debugfs_create_dir("proc", mali_profiling_dir);
+				if (mali_profiling_proc_dir != NULL)
+				{
+					struct dentry *mali_profiling_proc_default_dir = debugfs_create_dir("default", mali_profiling_proc_dir);
+					if (mali_profiling_proc_default_dir != NULL)
+					{
+						debugfs_create_file("enable", 0600, mali_profiling_proc_default_dir, NULL, &profiling_proc_default_enable_fops);
+					}
+				}
+				debugfs_create_file("record", 0600, mali_profiling_dir, NULL, &profiling_record_fops);
+				debugfs_create_file("events", 0400, mali_profiling_dir, NULL, &profiling_events_fops);
+			}
+#endif
+
+#if MALI_STATE_TRACKING
+			debugfs_create_file("state_dump", 0400, mali_debugfs_dir, NULL, &mali_seq_internal_state_fops);
+#endif
+
+			debugfs_create_file("memory_usage", 0400, mali_debugfs_dir, NULL, &memory_usage_fops);
+		}
+	}
+
+	/* Success! */
+	return 0;
+
+	/* Error handling */
+init_mdev_err:
+	class_destroy(device->mali_class);
+init_class_err:
+
+	return err;
+}
+
+int mali_sysfs_unregister(struct mali_dev *device, dev_t dev, const char *mali_dev_name)
+{
+	if(NULL != mali_debugfs_dir)
+	{
+		debugfs_remove_recursive(mali_debugfs_dir);
+	}
+	device_destroy(device->mali_class, dev);
+	class_destroy(device->mali_class);
+
+	return 0;
+}
+
+#else
+
+/* Dummy implementations for when the sysfs API isn't available. */
+
+int mali_sysfs_register(struct mali_dev *device, dev_t dev, const char *mali_dev_name)
+{
+	return 0;
+}
+
+int mali_sysfs_unregister(struct mali_dev *device, dev_t dev, const char *mali_dev_name)
+{
+	return 0;
+}
+
+
+#endif
diff --git a/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.h b/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.h
new file mode 100644
index 0000000..f68b4e1
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_kernel_sysfs.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_KERNEL_SYSFS_H__
+#define __MALI_KERNEL_SYSFS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MALI_PROC_DIR "driver/mali"
+
+int mali_sysfs_register(struct mali_dev *mali_class, dev_t dev, const char *mali_dev_name);
+
+int mali_sysfs_unregister(struct mali_dev *mali_class, dev_t dev, const char *mali_dev_name);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_KERNEL_LINUX_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_linux_pm.h b/drivers/media/video/samsung/mali/linux/mali_linux_pm.h
new file mode 100644
index 0000000..a8c0c52
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_linux_pm.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_LINUX_PM_H__
+#define __MALI_LINUX_PM_H__
+
+#if USING_MALI_PMM
+
+#ifdef CONFIG_PM
+/* Number of power states supported for making power up and down */
+typedef enum
+{
+	_MALI_DEVICE_SUSPEND,                         /* Suspend */
+	_MALI_DEVICE_RESUME,                          /* Resume */
+	_MALI_DEVICE_MAX_POWER_STATES,                /* Maximum power states */
+	_MALI_DEVICE_SHUTDOWN,			      /* Power off states*/
+} _mali_device_power_states;
+
+/* Number of DVFS events */
+typedef enum
+{
+	_MALI_DVFS_PAUSE_EVENT = _MALI_DEVICE_MAX_POWER_STATES,     /* DVFS Pause event */
+	_MALI_DVFS_RESUME_EVENT,                                        /* DVFS Resume event */
+	_MALI_MAX_DEBUG_OPERATIONS,
+} _mali_device_dvfs_events;
+
+extern _mali_device_power_states mali_device_state;
+extern _mali_device_power_states mali_dvfs_device_state;
+extern  _mali_osk_lock_t *lock;
+extern short is_wake_up_needed;
+extern int timeout_fired;
+extern struct platform_device mali_gpu_device;
+
+/* dvfs pm thread */
+extern struct task_struct *dvfs_pm_thread;
+
+/* Power management thread */
+extern struct task_struct *pm_thread;
+
+int mali_device_suspend(u32 event_id, struct task_struct **pwr_mgmt_thread);
+int mali_device_resume(u32 event_id, struct task_struct **pwr_mgmt_thread);
+int mali_get_ospmm_thread_state(void);
+
+#endif /* CONFIG_PM */
+#endif /* USING_MALI_PMM */
+#endif /* __MALI_LINUX_PM_H___ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_linux_pm_testsuite.h b/drivers/media/video/samsung/mali/linux/mali_linux_pm_testsuite.h
new file mode 100644
index 0000000..7b1bff9
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_linux_pm_testsuite.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __MALI_LINUX_PM_TESTSUITE_H__
+#define __MALI_LINUX_PM_TESTSUITE_H__
+
+#if USING_MALI_PMM
+#if MALI_POWER_MGMT_TEST_SUITE
+#ifdef CONFIG_PM
+
+typedef enum
+{
+        _MALI_DEVICE_PMM_TIMEOUT_EVENT,
+        _MALI_DEVICE_PMM_JOB_SCHEDULING_EVENTS,
+	_MALI_DEVICE_PMM_REGISTERED_CORES,
+        _MALI_DEVICE_MAX_PMM_EVENTS
+
+} _mali_device_pmm_recording_events;
+
+extern unsigned int mali_timeout_event_recording_on;
+extern unsigned int mali_job_scheduling_events_recording_on;
+extern unsigned int pwr_mgmt_status_reg;
+extern unsigned int is_mali_pmm_testsuite_enabled;
+extern unsigned int is_mali_pmu_present;
+
+#endif /* CONFIG_PM */
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+#endif /* USING_MALI_PMM */
+#endif /* __MALI_LINUX_PM_TESTSUITE_H__ */
+
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_linux_trace.h b/drivers/media/video/samsung/mali/linux/mali_linux_trace.h
new file mode 100644
index 0000000..3ce1e50
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_linux_trace.h
@@ -0,0 +1,93 @@
+#if !defined(_TRACE_MALI_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_MALI_H
+
+#include <linux/stringify.h>
+#include <linux/tracepoint.h>
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM mali
+#define TRACE_SYSTEM_STRING __stringify(TRACE_SYSTEM)
+#define TRACE_INCLUDE_FILE mali_linux_trace
+
+/**
+ * mali_timeline_event - called from the central collection point (_mali_profiling_add_event)
+ * @event_id: ORed together bitfields representing a type of event
+ * In the future we might add
+ * @timestamp
+ * @data[5] - this currently includes thread and process id's - we should have EGLConfig or similar too
+ *
+ * Just make a record of the event_id, we'll decode it elsewhere
+ */
+TRACE_EVENT(mali_timeline_event,
+
+	TP_PROTO(unsigned int event_id),
+
+	TP_ARGS(event_id),
+
+	TP_STRUCT__entry(
+		__field(	int,	event_id	)
+	),
+
+	TP_fast_assign(
+		__entry->event_id = event_id;
+	),
+
+	TP_printk("event=%d", __entry->event_id)
+);
+
+/**
+ * mali_hw_counter - called from the ????
+ * @event_id: event being counted
+ * In the future we might add
+ * @timestamp ??
+ *
+ * Just make a record of the event_id and value
+ */
+TRACE_EVENT(mali_hw_counter, 
+
+	TP_PROTO(unsigned int event_id, unsigned int value),
+
+	TP_ARGS(event_id, value),
+
+	TP_STRUCT__entry(
+		__field(	int, 	event_id	)
+		__field(	int,	value	)
+	),
+
+	TP_fast_assign(
+		__entry->event_id = event_id;
+	),
+
+	TP_printk("event %d = %d", __entry->event_id, __entry->value)
+);
+
+/**
+ * mali_sw_counter
+ * @event_id: counter id
+ */
+TRACE_EVENT(mali_sw_counter,
+
+    TP_PROTO(unsigned int event_id, signed long long value),
+
+    TP_ARGS(event_id, value),
+
+    TP_STRUCT__entry(
+        __field(    int,    event_id    )
+        __field(    long long,  value   )
+    ),
+
+    TP_fast_assign(
+        __entry->event_id = event_id;
+    ),
+
+    TP_printk("event %d = %lld", __entry->event_id, __entry->value)
+);
+
+#endif /*  _TRACE_MALI_H */
+
+#undef TRACE_INCLUDE_PATH
+#undef linux
+#define TRACE_INCLUDE_PATH .
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_atomics.c b/drivers/media/video/samsung/mali/linux/mali_osk_atomics.c
new file mode 100644
index 0000000..05831c5
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_atomics.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_atomics.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include "mali_osk.h"
+#include <asm/atomic.h>
+#include "mali_kernel_common.h"
+
+void _mali_osk_atomic_dec( _mali_osk_atomic_t *atom )
+{
+    atomic_dec((atomic_t *)&atom->u.val);
+}
+
+u32 _mali_osk_atomic_dec_return( _mali_osk_atomic_t *atom )
+{
+    return atomic_dec_return((atomic_t *)&atom->u.val);
+}
+
+void _mali_osk_atomic_inc( _mali_osk_atomic_t *atom )
+{
+    atomic_inc((atomic_t *)&atom->u.val);
+}
+
+u32 _mali_osk_atomic_inc_return( _mali_osk_atomic_t *atom )
+{
+    return atomic_inc_return((atomic_t *)&atom->u.val);
+}
+
+_mali_osk_errcode_t _mali_osk_atomic_init( _mali_osk_atomic_t *atom, u32 val )
+{
+    MALI_CHECK_NON_NULL(atom, _MALI_OSK_ERR_INVALID_ARGS);
+    atomic_set((atomic_t *)&atom->u.val, val);
+    return _MALI_OSK_ERR_OK;
+}
+
+u32 _mali_osk_atomic_read( _mali_osk_atomic_t *atom )
+{
+    return atomic_read((atomic_t *)&atom->u.val);
+}
+
+void _mali_osk_atomic_term( _mali_osk_atomic_t *atom )
+{
+    MALI_IGNORE(atom);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.c b/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.c
new file mode 100644
index 0000000..7297218
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/slab.h>
+#include <linux/pagemap.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/sched.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/atomic.h>
+
+#include "mali_osk.h"
+#include "mali_ukk.h"
+#include "mali_kernel_common.h"
+
+/**
+ * @file mali_osk_specific.c
+ * Implementation of per-OS Kernel level specifics
+ */
+
+_mali_osk_errcode_t _mali_osk_specific_indirect_mmap( _mali_uk_mem_mmap_s *args )
+{
+	/* args->ctx ignored here; args->ukk_private required instead */
+	/* we need to lock the mmap semaphore before calling the do_mmap function */
+    down_write(&current->mm->mmap_sem);
+
+    args->mapping = (void __user *)do_mmap(
+											(struct file *)args->ukk_private,
+											0, /* start mapping from any address after NULL */
+											args->size,
+											PROT_READ | PROT_WRITE,
+											MAP_SHARED,
+											args->phys_addr
+										   );
+
+	/* and unlock it after the call */
+	up_write(&current->mm->mmap_sem);
+
+	/* No cookie required here */
+	args->cookie = 0;
+	/* uku_private meaningless, so zero */
+	args->uku_private = NULL;
+
+	if ( (NULL == args->mapping) || IS_ERR((void *)args->mapping) )
+	{
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	/* Success */
+	return _MALI_OSK_ERR_OK;
+}
+
+
+_mali_osk_errcode_t _mali_osk_specific_indirect_munmap( _mali_uk_mem_munmap_s *args )
+{
+	/* args->ctx and args->cookie ignored here */
+
+	if ((NULL != current) && (NULL != current->mm))
+	{
+		/* remove mapping of mali memory from the process' view */
+		/* lock mmap semaphore before call */
+		/* lock mmap_sem before calling do_munmap */
+		down_write(&current->mm->mmap_sem);
+		do_munmap(
+					current->mm,
+					(unsigned long)args->mapping,
+					args->size
+				);
+		/* and unlock after call */
+		up_write(&current->mm->mmap_sem);
+		MALI_DEBUG_PRINT(5, ("unmapped\n"));
+	}
+	else
+	{
+		MALI_DEBUG_PRINT(2, ("Freeing of a big block while no user process attached, assuming crash cleanup in progress\n"));
+	}
+
+	return _MALI_OSK_ERR_OK; /* always succeeds */
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.h b/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.h
new file mode 100644
index 0000000..41cb462
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_indir_mmap.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_specific.h
+ * Defines per-OS Kernel level specifics, such as unusual workarounds for
+ * certain OSs.
+ */
+
+#ifndef __MALI_OSK_INDIR_MMAP_H__
+#define __MALI_OSK_INDIR_MMAP_H__
+
+#include "mali_uk_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * Linux specific means for calling _mali_ukk_mem_mmap/munmap
+ *
+ * The presence of _MALI_OSK_SPECIFIC_INDIRECT_MMAP indicates that
+ * _mali_osk_specific_indirect_mmap and _mali_osk_specific_indirect_munmap
+ * should be used instead of _mali_ukk_mem_mmap/_mali_ukk_mem_munmap.
+ *
+ * The arguments are the same as _mali_ukk_mem_mmap/_mali_ukk_mem_munmap.
+ *
+ * In ALL operating system other than Linux, it is expected that common code
+ * should be able to call _mali_ukk_mem_mmap/_mali_ukk_mem_munmap directly.
+ * Such systems should NOT define _MALI_OSK_SPECIFIC_INDIRECT_MMAP.
+ */
+_mali_osk_errcode_t _mali_osk_specific_indirect_mmap( _mali_uk_mem_mmap_s *args );
+_mali_osk_errcode_t _mali_osk_specific_indirect_munmap( _mali_uk_mem_munmap_s *args );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_OSK_INDIR_MMAP_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_irq.c b/drivers/media/video/samsung/mali/linux/mali_osk_irq.c
new file mode 100644
index 0000000..c597b9e
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_irq.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_irq.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include <linux/slab.h>	/* For memory allocation */
+#include <linux/workqueue.h>
+
+#include "mali_osk.h"
+#include "mali_kernel_core.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_license.h"
+#include "linux/interrupt.h"
+
+typedef struct _mali_osk_irq_t_struct
+{
+	u32 irqnum;
+	void *data;
+	_mali_osk_irq_uhandler_t uhandler;
+	_mali_osk_irq_bhandler_t bhandler;
+	struct work_struct work_queue_irq_handle; /* Workqueue for the bottom half of the IRQ-handling. This job is activated when this core gets an IRQ.*/
+} mali_osk_irq_object_t;
+
+static struct workqueue_struct *mali_irq_wq=NULL;
+
+typedef void (*workqueue_func_t)(void *);
+typedef irqreturn_t (*irq_handler_func_t)(int, void *, struct pt_regs *);
+static irqreturn_t irq_handler_upper_half (int port_name, void* dev_id ); /* , struct pt_regs *regs*/
+
+#if defined(INIT_DELAYED_WORK)
+static void irq_handler_bottom_half ( struct work_struct *work );
+#else
+static void irq_handler_bottom_half ( void *  input );
+#endif
+
+/**
+ * Linux kernel version has marked SA_SHIRQ as deprecated, IRQF_SHARED should be used.
+ * This is to handle older kernels which haven't done this swap.
+ */
+#ifndef IRQF_SHARED
+#define IRQF_SHARED SA_SHIRQ
+#endif /* IRQF_SHARED */
+
+_mali_osk_irq_t *_mali_osk_irq_init( u32 irqnum, _mali_osk_irq_uhandler_t uhandler,	_mali_osk_irq_bhandler_t bhandler, _mali_osk_irq_trigger_t trigger_func, _mali_osk_irq_ack_t ack_func, void *data, const char *description )
+{
+	mali_osk_irq_object_t *irq_object;
+
+	irq_object = kmalloc(sizeof(mali_osk_irq_object_t), GFP_KERNEL);
+	if (NULL == irq_object) return NULL;
+
+	/* workqueue API changed in 2.6.20, support both versions: */
+#if defined(INIT_DELAYED_WORK)
+	/* New syntax: INIT_WORK( struct work_struct *work, void (*function)(struct work_struct *)) */
+	INIT_WORK( &irq_object->work_queue_irq_handle, irq_handler_bottom_half);
+#else
+	/* Old syntax: INIT_WORK( struct work_struct *work, void (*function)(void *), void *data) */
+	INIT_WORK( &irq_object->work_queue_irq_handle, irq_handler_bottom_half, irq_object);
+#endif /* defined(INIT_DELAYED_WORK) */
+
+	if (-1 == irqnum)
+	{
+		/* Probe for IRQ */
+		if ( (NULL != trigger_func) && (NULL != ack_func) )
+		{
+			unsigned long probe_count = 3;
+			_mali_osk_errcode_t err;
+			int irq;
+
+			MALI_DEBUG_PRINT(2, ("Probing for irq\n"));
+
+			do
+			{
+				unsigned long mask;
+
+				mask = probe_irq_on();
+				trigger_func(data);
+
+				_mali_osk_time_ubusydelay(5);
+
+				irq = probe_irq_off(mask);
+				err = ack_func(data);
+			}
+			while (irq < 0 && (err == _MALI_OSK_ERR_OK) && probe_count--);
+
+			if (irq < 0 || (_MALI_OSK_ERR_OK != err)) irqnum = -1;
+			else irqnum = irq;
+		}
+		else irqnum = -1; /* no probe functions, fault */
+
+		if (-1 != irqnum)
+		{
+			/* found an irq */
+			MALI_DEBUG_PRINT(2, ("Found irq %d\n", irqnum));
+		}
+		else
+		{
+			MALI_DEBUG_PRINT(2, ("Probe for irq failed\n"));
+		}
+	}
+
+	irq_object->irqnum = irqnum;
+	irq_object->uhandler = uhandler;
+	irq_object->bhandler = bhandler;
+	irq_object->data = data;
+
+	/* Is this a real IRQ handler we need? */
+	if (!mali_benchmark && irqnum != _MALI_OSK_IRQ_NUMBER_FAKE && irqnum != _MALI_OSK_IRQ_NUMBER_PMM)
+	{
+		if (-1 == irqnum)
+		{
+			MALI_DEBUG_PRINT(2, ("No IRQ for core '%s' found during probe\n", description));
+			kfree(irq_object);
+			return NULL;
+		}
+
+		if (0 != request_irq(irqnum, irq_handler_upper_half, IRQF_SHARED, description, irq_object))
+		{
+			MALI_DEBUG_PRINT(2, ("Unable to install IRQ handler for core '%s'\n", description));
+			kfree(irq_object);
+			return NULL;
+		}
+	}
+
+	if (mali_irq_wq == NULL)
+	{
+		mali_irq_wq = create_singlethread_workqueue("mali-pmm-wq");
+	}
+
+	return irq_object;
+}
+
+void _mali_osk_irq_schedulework( _mali_osk_irq_t *irq )
+{
+	mali_osk_irq_object_t *irq_object = (mali_osk_irq_object_t *)irq;
+	queue_work_on(0, mali_irq_wq,&irq_object->work_queue_irq_handle);
+}
+
+void _mali_osk_flush_workqueue( _mali_osk_irq_t *irq )
+{
+		flush_workqueue(mali_irq_wq );
+}
+
+void _mali_osk_irq_term( _mali_osk_irq_t *irq )
+{
+	mali_osk_irq_object_t *irq_object = (mali_osk_irq_object_t *)irq;
+
+	if(mali_irq_wq != NULL)
+	{
+		flush_workqueue(mali_irq_wq);
+		destroy_workqueue(mali_irq_wq);
+		mali_irq_wq = NULL;
+	}	
+
+	if (!mali_benchmark)
+	{
+		free_irq(irq_object->irqnum, irq_object);
+	}
+	kfree(irq_object);
+	flush_scheduled_work();
+}
+
+
+/** This function is called directly in interrupt context from the OS just after
+ * the CPU get the hw-irq from mali, or other devices on the same IRQ-channel.
+ * It is registered one of these function for each mali core. When an interrupt
+ * arrives this function will be called equal times as registered mali cores.
+ * That means that we only check one mali core in one function call, and the
+ * core we check for each turn is given by the \a dev_id variable.
+ * If we detect an pending interrupt on the given core, we mask the interrupt
+ * out by settging the core's IRQ_MASK register to zero.
+ * Then we schedule the mali_core_irq_handler_bottom_half to run as high priority
+ * work queue job.
+ */
+static irqreturn_t irq_handler_upper_half (int port_name, void* dev_id ) /* , struct pt_regs *regs*/
+{
+	mali_osk_irq_object_t *irq_object = (mali_osk_irq_object_t *)dev_id;
+
+	if (irq_object->uhandler(irq_object->data) == _MALI_OSK_ERR_OK)
+	{
+		return IRQ_HANDLED;
+	}
+	return IRQ_NONE;
+}
+
+/* Is executed when an interrupt occur on one core */
+/* workqueue API changed in 2.6.20, support both versions: */
+#if defined(INIT_DELAYED_WORK)
+static void irq_handler_bottom_half ( struct work_struct *work )
+#else
+static void irq_handler_bottom_half ( void *  input )
+#endif
+{
+	mali_osk_irq_object_t *irq_object;
+
+#if defined(INIT_DELAYED_WORK)
+	irq_object = _MALI_OSK_CONTAINER_OF(work, mali_osk_irq_object_t, work_queue_irq_handle);
+#else
+	if ( NULL == input )
+	{
+		MALI_PRINT_ERROR(("IRQ: Null pointer! Illegal!"));
+		return; /* Error */
+	}
+	irq_object = (mali_osk_irq_object_t *) input;
+#endif
+
+	irq_object->bhandler(irq_object->data);
+}
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_locks.c b/drivers/media/video/samsung/mali/linux/mali_osk_locks.c
new file mode 100644
index 0000000..aad6fc6
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_locks.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_locks.c
+ * Implemenation of the OS abstraction layer for the kernel device driver
+ */
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#include <linux/spinlock.h>
+#include <linux/rwsem.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+#include <linux/semaphore.h>
+#else /* pre 2.6.26 the file was in the arch specific location */
+#include <asm/semaphore.h>
+#endif
+
+#include <linux/slab.h>
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+
+/* These are all the locks we implement: */
+typedef enum
+{
+	_MALI_OSK_INTERNAL_LOCKTYPE_SPIN,            /* Mutex, implicitly non-interruptable, use spin_lock/spin_unlock */
+	_MALI_OSK_INTERNAL_LOCKTYPE_SPIN_IRQ,        /* Mutex, IRQ version of spinlock, use spin_lock_irqsave/spin_unlock_irqrestore */
+	_MALI_OSK_INTERNAL_LOCKTYPE_MUTEX,           /* Interruptable, use up()/down_interruptable() */
+	_MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT,    /* Non-Interruptable, use up()/down() */
+	_MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT_RW, /* Non-interruptable, Reader/Writer, use {up,down}{read,write}() */
+
+	/* Linux supports, but we do not support:
+	 * Non-Interruptable Reader/Writer spinlock mutexes - RW optimization will be switched off
+	 */
+
+	/* Linux does not support:
+	 * One-locks, of any sort - no optimization for this fact will be made.
+	 */
+
+} _mali_osk_internal_locktype;
+
+struct _mali_osk_lock_t_struct
+{
+    _mali_osk_internal_locktype type;
+	unsigned long flags; 
+    union
+    {
+        spinlock_t spinlock;
+        struct semaphore sema;
+        struct rw_semaphore rw_sema;
+    } obj;
+	MALI_DEBUG_CODE(
+				  /** original flags for debug checking */
+				  _mali_osk_lock_flags_t orig_flags;
+	); /* MALI_DEBUG_CODE */
+};
+
+_mali_osk_lock_t *_mali_osk_lock_init( _mali_osk_lock_flags_t flags, u32 initial, u32 order )
+{
+    _mali_osk_lock_t *lock = NULL;
+
+	/* Validate parameters: */
+	/* Flags acceptable */
+	MALI_DEBUG_ASSERT( 0 == ( flags & ~(_MALI_OSK_LOCKFLAG_SPINLOCK
+									  | _MALI_OSK_LOCKFLAG_SPINLOCK_IRQ
+									  | _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE
+									  | _MALI_OSK_LOCKFLAG_READERWRITER
+									  | _MALI_OSK_LOCKFLAG_ORDERED
+									  | _MALI_OSK_LOCKFLAG_ONELOCK )) );
+	/* Spinlocks are always non-interruptable */
+	MALI_DEBUG_ASSERT( (((flags & _MALI_OSK_LOCKFLAG_SPINLOCK) || (flags & _MALI_OSK_LOCKFLAG_SPINLOCK_IRQ)) && (flags & _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE))
+					 || !(flags & _MALI_OSK_LOCKFLAG_SPINLOCK));
+	/* Parameter initial SBZ - for future expansion */
+	MALI_DEBUG_ASSERT( 0 == initial );
+
+	lock = kmalloc(sizeof(_mali_osk_lock_t), GFP_KERNEL);
+
+	if ( NULL == lock )
+	{
+		return lock;
+	}
+
+	/* Determine type of mutex: */
+    /* defaults to interruptable mutex if no flags are specified */
+
+	if ( (flags & _MALI_OSK_LOCKFLAG_SPINLOCK) )
+	{
+		/* Non-interruptable Spinlocks override all others */
+		lock->type = _MALI_OSK_INTERNAL_LOCKTYPE_SPIN;
+		spin_lock_init( &lock->obj.spinlock );
+	}
+	else if ( (flags & _MALI_OSK_LOCKFLAG_SPINLOCK_IRQ ) )
+	{
+		lock->type = _MALI_OSK_INTERNAL_LOCKTYPE_SPIN_IRQ;
+		lock->flags = 0;
+		spin_lock_init( &lock->obj.spinlock );
+	}
+	else if ( (flags & _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE)
+			  && (flags & _MALI_OSK_LOCKFLAG_READERWRITER) )
+	{
+		lock->type = _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT_RW;
+		init_rwsem( &lock->obj.rw_sema );
+	}
+	else
+	{
+		/* Usual mutex types */
+		if ( (flags & _MALI_OSK_LOCKFLAG_NONINTERRUPTABLE) )
+		{
+			lock->type = _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT;
+		}
+		else
+		{
+			lock->type = _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX;
+		}
+
+		/* Initially unlocked */
+		sema_init( &lock->obj.sema, 1 );
+	}
+
+	MALI_DEBUG_CODE(
+				  /* Debug tracking of flags */
+				  lock->orig_flags = flags;
+				  ); /* MALI_DEBUG_CODE */
+
+    return lock;
+}
+
+_mali_osk_errcode_t _mali_osk_lock_wait( _mali_osk_lock_t *lock, _mali_osk_lock_mode_t mode)
+{
+    _mali_osk_errcode_t err = _MALI_OSK_ERR_OK;
+
+	/* Parameter validation */
+	MALI_DEBUG_ASSERT_POINTER( lock );
+
+	MALI_DEBUG_ASSERT( _MALI_OSK_LOCKMODE_RW == mode
+					 || _MALI_OSK_LOCKMODE_RO == mode );
+
+	/* Only allow RO locks when the initial object was a Reader/Writer lock
+	 * Since information is lost on the internal locktype, we use the original
+	 * information, which is only stored when built for DEBUG */
+	MALI_DEBUG_ASSERT( _MALI_OSK_LOCKMODE_RW == mode
+					 || (_MALI_OSK_LOCKMODE_RO == mode && (_MALI_OSK_LOCKFLAG_READERWRITER & lock->orig_flags)) );
+
+	switch ( lock->type )
+	{
+	case _MALI_OSK_INTERNAL_LOCKTYPE_SPIN:
+		spin_lock(&lock->obj.spinlock);
+		break;
+	case _MALI_OSK_INTERNAL_LOCKTYPE_SPIN_IRQ:
+		spin_lock_irqsave(&lock->obj.spinlock, lock->flags);
+		break;
+
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX:
+		if ( down_interruptible(&lock->obj.sema) )
+		{
+			err = _MALI_OSK_ERR_RESTARTSYSCALL;
+		}
+		break;
+
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT:
+		down(&lock->obj.sema);
+		break;
+
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT_RW:
+		if (mode == _MALI_OSK_LOCKMODE_RO)
+        {
+            down_read(&lock->obj.rw_sema);
+        }
+        else
+        {
+            down_write(&lock->obj.rw_sema);
+        }
+		break;
+
+	default:
+		/* Reaching here indicates a programming error, so you will not get here
+		 * on non-DEBUG builds */
+		MALI_DEBUG_PRINT_ERROR( ("Invalid internal lock type: %.8X", lock->type ) );
+		break;
+	}
+
+    return err;
+}
+
+void _mali_osk_lock_signal( _mali_osk_lock_t *lock, _mali_osk_lock_mode_t mode )
+{
+	/* Parameter validation */
+	MALI_DEBUG_ASSERT_POINTER( lock );
+
+	MALI_DEBUG_ASSERT( _MALI_OSK_LOCKMODE_RW == mode
+					 || _MALI_OSK_LOCKMODE_RO == mode );
+
+	/* Only allow RO locks when the initial object was a Reader/Writer lock
+	 * Since information is lost on the internal locktype, we use the original
+	 * information, which is only stored when built for DEBUG */
+	MALI_DEBUG_ASSERT( _MALI_OSK_LOCKMODE_RW == mode
+					 || (_MALI_OSK_LOCKMODE_RO == mode && (_MALI_OSK_LOCKFLAG_READERWRITER & lock->orig_flags)) );
+
+	switch ( lock->type )
+	{
+	case _MALI_OSK_INTERNAL_LOCKTYPE_SPIN:
+		spin_unlock(&lock->obj.spinlock);
+		break;
+	case _MALI_OSK_INTERNAL_LOCKTYPE_SPIN_IRQ:
+		spin_unlock_irqrestore(&lock->obj.spinlock, lock->flags);
+		break;
+
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX:
+		/* FALLTHROUGH */
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT:
+		up(&lock->obj.sema);
+		break;
+
+	case _MALI_OSK_INTERNAL_LOCKTYPE_MUTEX_NONINT_RW:
+		if (mode == _MALI_OSK_LOCKMODE_RO)
+        {
+            up_read(&lock->obj.rw_sema);
+        }
+        else
+        {
+            up_write(&lock->obj.rw_sema);
+        }
+		break;
+
+	default:
+		/* Reaching here indicates a programming error, so you will not get here
+		 * on non-DEBUG builds */
+		MALI_DEBUG_PRINT_ERROR( ("Invalid internal lock type: %.8X", lock->type ) );
+		break;
+	}
+}
+
+void _mali_osk_lock_term( _mali_osk_lock_t *lock )
+{
+	/* Parameter validation  */
+	MALI_DEBUG_ASSERT_POINTER( lock );
+
+	/* Linux requires no explicit termination of spinlocks, semaphores, or rw_semaphores */
+    kfree(lock);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_low_level_mem.c b/drivers/media/video/samsung/mali/linux/mali_osk_low_level_mem.c
new file mode 100644
index 0000000..c0aecb8
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_low_level_mem.c
@@ -0,0 +1,599 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_low_level_mem.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+
+#include "mali_osk.h"
+#include "mali_ukk.h" /* required to hook in _mali_ukk_mem_mmap handling */
+#include "mali_kernel_common.h"
+#include "mali_kernel_linux.h"
+
+static void mali_kernel_memory_vma_open(struct vm_area_struct * vma);
+static void mali_kernel_memory_vma_close(struct vm_area_struct * vma);
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+static int mali_kernel_memory_cpu_page_fault_handler(struct vm_area_struct *vma, struct vm_fault *vmf);
+#else
+static unsigned long mali_kernel_memory_cpu_page_fault_handler(struct vm_area_struct * vma, unsigned long address);
+#endif
+
+
+typedef struct mali_vma_usage_tracker
+{
+	int references;
+	u32 cookie;
+} mali_vma_usage_tracker;
+
+
+/* Linked list structure to hold details of all OS allocations in a particular
+ * mapping
+ */
+struct AllocationList
+{
+	struct AllocationList *next;
+	u32 offset;
+	u32 physaddr;
+};
+
+typedef struct AllocationList AllocationList;
+
+/* Private structure to store details of a mapping region returned
+ * from _mali_osk_mem_mapregion_init
+ */
+struct MappingInfo
+{
+	struct vm_area_struct *vma;
+	struct AllocationList *list;
+};
+
+typedef struct MappingInfo MappingInfo;
+
+
+static u32 _kernel_page_allocate(void);
+static void _kernel_page_release(u32 physical_address);
+static AllocationList * _allocation_list_item_get(void);
+static void _allocation_list_item_release(AllocationList * item);
+
+
+/* Variable declarations */
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
+spinlock_t allocation_list_spinlock = SPIN_LOCK_UNLOCKED;
+#else
+DEFINE_SPINLOCK(allocation_list_spinlock);
+#endif
+
+static AllocationList * pre_allocated_memory = (AllocationList*) NULL ;
+static int pre_allocated_memory_size_current  = 0;
+#ifdef MALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB
+	static int pre_allocated_memory_size_max      = MALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB * 1024 * 1024;
+#else
+	static int pre_allocated_memory_size_max      = 6 * 1024 * 1024; /* 6 MiB */
+#endif
+
+static struct vm_operations_struct mali_kernel_vm_ops =
+{
+	.open = mali_kernel_memory_vma_open,
+	.close = mali_kernel_memory_vma_close,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	.fault = mali_kernel_memory_cpu_page_fault_handler
+#else
+	.nopfn = mali_kernel_memory_cpu_page_fault_handler
+#endif
+};
+
+
+void mali_osk_low_level_mem_init(void)
+{
+	pre_allocated_memory = (AllocationList*) NULL ;
+}
+
+void mali_osk_low_level_mem_term(void)
+{
+	while ( NULL != pre_allocated_memory )
+	{
+		AllocationList *item;
+		item = pre_allocated_memory;
+		pre_allocated_memory = item->next;
+		_kernel_page_release(item->physaddr);
+		_mali_osk_free( item );
+	}
+	pre_allocated_memory_size_current  = 0;
+}
+
+static u32 _kernel_page_allocate(void)
+{
+	struct page *new_page;
+	u32 linux_phys_addr;
+	
+	new_page = alloc_page(GFP_HIGHUSER | __GFP_ZERO | __GFP_REPEAT | __GFP_NOWARN | __GFP_COLD);
+	
+	if ( NULL == new_page )
+	{
+		return 0;
+	}
+
+	/* Ensure page is flushed from CPU caches. */
+	linux_phys_addr = dma_map_page(NULL, new_page, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
+
+	return linux_phys_addr;
+}
+
+static void _kernel_page_release(u32 physical_address)
+{
+	struct page *unmap_page;
+
+	#if 1
+	dma_unmap_page(NULL, physical_address, PAGE_SIZE, DMA_BIDIRECTIONAL);
+	#endif
+	
+	unmap_page = pfn_to_page( physical_address >> PAGE_SHIFT );
+	MALI_DEBUG_ASSERT_POINTER( unmap_page );
+	__free_page( unmap_page );
+}
+
+static AllocationList * _allocation_list_item_get(void)
+{
+	AllocationList *item = NULL;
+	unsigned long flags;
+	
+	spin_lock_irqsave(&allocation_list_spinlock,flags);
+	if ( pre_allocated_memory )
+	{
+		item = pre_allocated_memory;
+		pre_allocated_memory = pre_allocated_memory->next;
+		pre_allocated_memory_size_current -= PAGE_SIZE;
+		
+		spin_unlock_irqrestore(&allocation_list_spinlock,flags);
+		return item;
+	}
+	spin_unlock_irqrestore(&allocation_list_spinlock,flags);
+	
+	item = _mali_osk_malloc( sizeof(AllocationList) );
+	if ( NULL == item)
+	{
+		return NULL;
+	}
+
+	item->physaddr = _kernel_page_allocate();
+	if ( 0 == item->physaddr )
+	{
+		/* Non-fatal error condition, out of memory. Upper levels will handle this. */
+		_mali_osk_free( item );
+		return NULL;
+	}
+	return item;
+}
+
+static void _allocation_list_item_release(AllocationList * item)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&allocation_list_spinlock,flags);
+	if ( pre_allocated_memory_size_current < pre_allocated_memory_size_max)
+	{
+		item->next = pre_allocated_memory;
+		pre_allocated_memory = item;
+		pre_allocated_memory_size_current += PAGE_SIZE;
+		spin_unlock_irqrestore(&allocation_list_spinlock,flags);
+		return;
+	}
+	spin_unlock_irqrestore(&allocation_list_spinlock,flags);
+	
+	_kernel_page_release(item->physaddr);
+	_mali_osk_free( item );
+}
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+static int mali_kernel_memory_cpu_page_fault_handler(struct vm_area_struct *vma, struct vm_fault *vmf)
+#else
+static unsigned long mali_kernel_memory_cpu_page_fault_handler(struct vm_area_struct * vma, unsigned long address)
+#endif
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	void __user * address;
+	address = vmf->virtual_address;
+#endif
+	/*
+	 * We always fail the call since all memory is pre-faulted when assigned to the process.
+	 * Only the Mali cores can use page faults to extend buffers.
+	*/
+
+	MALI_DEBUG_PRINT(1, ("Page-fault in Mali memory region caused by the CPU.\n"));
+	MALI_DEBUG_PRINT(1, ("Tried to access %p (process local virtual address) which is not currently mapped to any Mali memory.\n", (void*)address));
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	return VM_FAULT_SIGBUS;
+#else
+	return NOPFN_SIGBUS;
+#endif
+}
+
+static void mali_kernel_memory_vma_open(struct vm_area_struct * vma)
+{
+	mali_vma_usage_tracker * vma_usage_tracker;
+	MALI_DEBUG_PRINT(4, ("Open called on vma %p\n", vma));
+
+	vma_usage_tracker = (mali_vma_usage_tracker*)vma->vm_private_data;
+	vma_usage_tracker->references++;
+
+	return;
+}
+
+static void mali_kernel_memory_vma_close(struct vm_area_struct * vma)
+{
+	_mali_uk_mem_munmap_s args = {0, };
+	mali_memory_allocation * descriptor;
+	mali_vma_usage_tracker * vma_usage_tracker;
+	MappingInfo *mappingInfo;
+	MALI_DEBUG_PRINT(3, ("Close called on vma %p\n", vma));
+
+	vma_usage_tracker = (mali_vma_usage_tracker*)vma->vm_private_data;
+
+	BUG_ON(!vma_usage_tracker);
+	BUG_ON(0 == vma_usage_tracker->references);
+
+	vma_usage_tracker->references--;
+
+	descriptor = (mali_memory_allocation *)vma_usage_tracker->cookie;
+
+	mappingInfo = (MappingInfo *)descriptor->process_addr_mapping_info;
+	mappingInfo->vma = vma;
+
+	if (0 != vma_usage_tracker->references)
+	{
+		MALI_DEBUG_PRINT(3, ("Ignoring this close, %d references still exists\n", vma_usage_tracker->references));
+		return;
+	}
+
+	/** @note args->context unused, initialized to 0.
+	 * Instead, we use the memory_session from the cookie */
+
+	args.cookie = (u32)descriptor;
+	args.mapping = descriptor->mapping;
+	args.size = descriptor->size;
+
+	_mali_ukk_mem_munmap( &args );
+
+	/* vma_usage_tracker is free()d by _mali_osk_mem_mapregion_term().
+	 * In the case of the memory engine, it is called as the release function that has been registered with the engine*/
+}
+
+
+void _mali_osk_mem_barrier( void )
+{
+	mb();
+}
+
+void _mali_osk_write_mem_barrier( void )
+{
+	wmb();
+}
+
+mali_io_address _mali_osk_mem_mapioregion( u32 phys, u32 size, const char *description )
+{
+	return (mali_io_address)ioremap_nocache(phys, size);
+}
+
+void _mali_osk_mem_unmapioregion( u32 phys, u32 size, mali_io_address virt )
+{
+	iounmap((void*)virt);
+}
+
+mali_io_address _mali_osk_mem_allocioregion( u32 *phys, u32 size )
+{
+	void * virt;
+ 	MALI_DEBUG_ASSERT_POINTER( phys );
+ 	MALI_DEBUG_ASSERT( 0 == (size & ~_MALI_OSK_CPU_PAGE_MASK) );
+ 	MALI_DEBUG_ASSERT( 0 != size );
+
+	/* dma_alloc_* uses a limited region of address space. On most arch/marchs
+	 * 2 to 14 MiB is available. This should be enough for the page tables, which
+	 * currently is the only user of this function. */
+	virt = dma_alloc_coherent(NULL, size, phys, GFP_KERNEL | GFP_DMA );
+
+	MALI_DEBUG_PRINT(3, ("Page table virt: 0x%x = dma_alloc_coherent(size:%d, phys:0x%x, )\n", virt, size, phys));
+
+ 	if ( NULL == virt )
+ 	{
+		MALI_DEBUG_PRINT(5, ("allocioregion: Failed to allocate Pagetable memory, size=0x%.8X\n", size ));
+ 		return 0;
+ 	}
+
+	MALI_DEBUG_ASSERT( 0 == (*phys & ~_MALI_OSK_CPU_PAGE_MASK) );
+
+ 	return (mali_io_address)virt;
+}
+
+void _mali_osk_mem_freeioregion( u32 phys, u32 size, mali_io_address virt )
+{
+ 	MALI_DEBUG_ASSERT_POINTER( (void*)virt );
+ 	MALI_DEBUG_ASSERT( 0 != size );
+ 	MALI_DEBUG_ASSERT( 0 == (phys & ( (1 << PAGE_SHIFT) - 1 )) );
+
+	dma_free_coherent(NULL, size, virt, phys);
+}
+
+_mali_osk_errcode_t inline _mali_osk_mem_reqregion( u32 phys, u32 size, const char *description )
+{
+	return ((NULL == request_mem_region(phys, size, description)) ? _MALI_OSK_ERR_NOMEM : _MALI_OSK_ERR_OK);
+}
+
+void inline _mali_osk_mem_unreqregion( u32 phys, u32 size )
+{
+	release_mem_region(phys, size);
+}
+
+void inline _mali_osk_mem_iowrite32_relaxed( volatile mali_io_address addr, u32 offset, u32 val )
+{
+	__raw_writel(cpu_to_le32(val),((u8*)addr) + offset);
+}
+
+u32 inline _mali_osk_mem_ioread32( volatile mali_io_address addr, u32 offset )
+{
+	return ioread32(((u8*)addr) + offset);
+}
+
+void inline _mali_osk_mem_iowrite32( volatile mali_io_address addr, u32 offset, u32 val )
+{
+	iowrite32(val, ((u8*)addr) + offset);
+}
+
+void _mali_osk_cache_flushall( void )
+{
+	/** @note Cached memory is not currently supported in this implementation */
+}
+
+void _mali_osk_cache_ensure_uncached_range_flushed( void *uncached_mapping, u32 offset, u32 size )
+{
+	_mali_osk_write_mem_barrier();
+}
+
+_mali_osk_errcode_t _mali_osk_mem_mapregion_init( mali_memory_allocation * descriptor )
+{
+	struct vm_area_struct *vma;
+	mali_vma_usage_tracker * vma_usage_tracker;
+	MappingInfo *mappingInfo;
+
+	if (NULL == descriptor) return _MALI_OSK_ERR_FAULT;
+
+	MALI_DEBUG_ASSERT( 0 != (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE) );
+
+	vma = (struct vm_area_struct*)descriptor->process_addr_mapping_info;
+
+	if (NULL == vma ) return _MALI_OSK_ERR_FAULT;
+
+	/* Re-write the process_addr_mapping_info */
+	mappingInfo = _mali_osk_calloc( 1, sizeof(MappingInfo) );
+
+	if ( NULL == mappingInfo ) return _MALI_OSK_ERR_FAULT;
+
+	vma_usage_tracker = _mali_osk_calloc( 1, sizeof(mali_vma_usage_tracker) );
+
+	if (NULL == vma_usage_tracker)
+	{
+		MALI_DEBUG_PRINT(2, ("Failed to allocate memory to track memory usage\n"));
+		_mali_osk_free( mappingInfo );
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	mappingInfo->vma = vma;
+	descriptor->process_addr_mapping_info = mappingInfo;
+
+	/* Do the va range allocation - in this case, it was done earlier, so we copy in that information */
+	descriptor->mapping = (void __user*)vma->vm_start;
+	/* list member is already NULL */
+
+	/*
+	  set some bits which indicate that:
+	  The memory is IO memory, meaning that no paging is to be performed and the memory should not be included in crash dumps
+	  The memory is reserved, meaning that it's present and can never be paged out (see also previous entry)
+	*/
+	vma->vm_flags |= VM_IO;
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_flags |= VM_DONTCOPY;
+
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_ops = &mali_kernel_vm_ops; /* Operations used on any memory system */
+
+	vma_usage_tracker->references = 1; /* set initial reference count to be 1 as vma_open won't be called for the first mmap call */
+	vma_usage_tracker->cookie = (u32)descriptor; /* cookie for munmap */
+
+	vma->vm_private_data = vma_usage_tracker;
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void _mali_osk_mem_mapregion_term( mali_memory_allocation * descriptor )
+{
+	struct vm_area_struct* vma;
+	mali_vma_usage_tracker * vma_usage_tracker;
+	MappingInfo *mappingInfo;
+
+	if (NULL == descriptor) return;
+
+	MALI_DEBUG_ASSERT( 0 != (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE) );
+
+	mappingInfo = (MappingInfo *)descriptor->process_addr_mapping_info;
+
+	MALI_DEBUG_ASSERT_POINTER( mappingInfo );
+
+	/* Linux does the right thing as part of munmap to remove the mapping
+	 * All that remains is that we remove the vma_usage_tracker setup in init() */
+	vma = mappingInfo->vma;
+
+	MALI_DEBUG_ASSERT_POINTER( vma );
+
+	/* ASSERT that there are no allocations on the list. Unmap should've been
+	 * called on all OS allocations. */
+	MALI_DEBUG_ASSERT( NULL == mappingInfo->list );
+
+	vma_usage_tracker = vma->vm_private_data;
+
+	/* We only get called if mem_mapregion_init succeeded */
+	_mali_osk_free(vma_usage_tracker);
+
+	_mali_osk_free( mappingInfo );
+	return;
+}
+
+_mali_osk_errcode_t _mali_osk_mem_mapregion_map( mali_memory_allocation * descriptor, u32 offset, u32 *phys_addr, u32 size )
+{
+	struct vm_area_struct *vma;
+	MappingInfo *mappingInfo;
+
+	if (NULL == descriptor) return _MALI_OSK_ERR_FAULT;
+
+	MALI_DEBUG_ASSERT_POINTER( phys_addr );
+
+	MALI_DEBUG_ASSERT( 0 != (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE) );
+
+	MALI_DEBUG_ASSERT( 0 == (size & ~_MALI_OSK_CPU_PAGE_MASK) );
+
+	MALI_DEBUG_ASSERT( 0 == (offset & ~_MALI_OSK_CPU_PAGE_MASK));
+
+	if (NULL == descriptor->mapping) return _MALI_OSK_ERR_INVALID_ARGS;
+
+	if (size > (descriptor->size - offset))
+	{
+		MALI_DEBUG_PRINT(1,("_mali_osk_mem_mapregion_map: virtual memory area not large enough to map physical 0x%x size %x into area 0x%x at offset 0x%xr\n",
+		                    *phys_addr, size, descriptor->mapping, offset));
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	mappingInfo = (MappingInfo *)descriptor->process_addr_mapping_info;
+
+	MALI_DEBUG_ASSERT_POINTER( mappingInfo );
+
+	vma = mappingInfo->vma;
+
+	if (NULL == vma ) return _MALI_OSK_ERR_FAULT;
+
+	MALI_DEBUG_PRINT(7, ("Process map: mapping 0x%08X to process address 0x%08lX length 0x%08X\n", *phys_addr, (long unsigned int)(descriptor->mapping + offset), size));
+
+	if ( MALI_MEMORY_ALLOCATION_OS_ALLOCATED_PHYSADDR_MAGIC == *phys_addr )
+	{
+		_mali_osk_errcode_t ret;
+		AllocationList *alloc_item;
+		u32 linux_phys_frame_num;
+
+		alloc_item = _allocation_list_item_get();
+		if (NULL == alloc_item)
+		{
+			MALI_DEBUG_PRINT(1, ("Failed to allocate list item\n"));
+			return _MALI_OSK_ERR_NOMEM;
+		}
+
+		linux_phys_frame_num = alloc_item->physaddr >> PAGE_SHIFT;
+
+		ret = ( remap_pfn_range( vma, ((u32)descriptor->mapping) + offset, linux_phys_frame_num, size, vma->vm_page_prot) ) ? _MALI_OSK_ERR_FAULT : _MALI_OSK_ERR_OK;
+
+		if ( ret != _MALI_OSK_ERR_OK)
+		{
+			_allocation_list_item_release(alloc_item);
+			return ret;
+		}
+
+		/* Put our alloc_item into the list of allocations on success */
+		alloc_item->next = mappingInfo->list;
+		alloc_item->offset = offset;
+
+		/*alloc_item->physaddr = linux_phys_addr;*/
+		mappingInfo->list = alloc_item;
+
+		/* Write out new physical address on success */
+		*phys_addr = alloc_item->physaddr;
+
+		return ret;
+	}
+
+	/* Otherwise, Use the supplied physical address */
+
+	/* ASSERT that supplied phys_addr is page aligned */
+	MALI_DEBUG_ASSERT( 0 == ((*phys_addr) & ~_MALI_OSK_CPU_PAGE_MASK) );
+
+	return ( remap_pfn_range( vma, ((u32)descriptor->mapping) + offset, *phys_addr >> PAGE_SHIFT, size, vma->vm_page_prot) ) ? _MALI_OSK_ERR_FAULT : _MALI_OSK_ERR_OK;
+
+}
+
+void _mali_osk_mem_mapregion_unmap( mali_memory_allocation * descriptor, u32 offset, u32 size, _mali_osk_mem_mapregion_flags_t flags )
+{
+	MappingInfo *mappingInfo;
+
+   if (NULL == descriptor) return;
+
+	MALI_DEBUG_ASSERT( 0 != (descriptor->flags & MALI_MEMORY_ALLOCATION_FLAG_MAP_INTO_USERSPACE) );
+
+	MALI_DEBUG_ASSERT( 0 == (size & ~_MALI_OSK_CPU_PAGE_MASK) );
+
+	MALI_DEBUG_ASSERT( 0 == (offset & ~_MALI_OSK_CPU_PAGE_MASK) );
+
+	if (NULL == descriptor->mapping) return;
+
+	if (size > (descriptor->size - offset))
+	{
+		MALI_DEBUG_PRINT(1,("_mali_osk_mem_mapregion_unmap: virtual memory area not large enough to unmap size %x from area 0x%x at offset 0x%x\n",
+							size, descriptor->mapping, offset));
+		return;
+	}
+	mappingInfo = (MappingInfo *)descriptor->process_addr_mapping_info;
+
+	MALI_DEBUG_ASSERT_POINTER( mappingInfo );
+
+	if ( 0 != (flags & _MALI_OSK_MEM_MAPREGION_FLAG_OS_ALLOCATED_PHYSADDR) )
+	{
+		/* This physical RAM was allocated in _mali_osk_mem_mapregion_map and
+		 * so needs to be unmapped
+		 */
+		while (size)
+		{
+			/* First find the allocation in the list of allocations */
+			AllocationList *alloc = mappingInfo->list;
+			AllocationList **prev = &(mappingInfo->list);
+			while (NULL != alloc && alloc->offset != offset)
+			{
+				prev = &(alloc->next);
+				alloc = alloc->next;
+			}
+			if (alloc == NULL) {
+				MALI_DEBUG_PRINT(1, ("Unmapping memory that isn't mapped\n"));
+				size -= _MALI_OSK_CPU_PAGE_SIZE;
+				offset += _MALI_OSK_CPU_PAGE_SIZE;
+				continue;
+			}
+
+			_kernel_page_release(alloc->physaddr);
+
+			/* Remove the allocation from the list */
+			*prev = alloc->next;
+			_mali_osk_free( alloc );
+
+			/* Move onto the next allocation */
+			size -= _MALI_OSK_CPU_PAGE_SIZE;
+			offset += _MALI_OSK_CPU_PAGE_SIZE;
+		}
+	}
+
+	/* Linux does the right thing as part of munmap to remove the mapping */
+
+	return;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_mali.c b/drivers/media/video/samsung/mali/linux/mali_osk_mali.c
new file mode 100644
index 0000000..ab571c1
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_mali.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_mali.c
+ * Implementation of the OS abstraction layer which is specific for the Mali kernel device driver
+ */
+#include <linux/kernel.h>
+#include <asm/uaccess.h>
+
+#include "mali_kernel_common.h" /* MALI_xxx macros */
+#include "mali_osk.h"           /* kernel side OS functions */
+#include "mali_uk_types.h"
+#include "mali_kernel_linux.h"  /* exports initialize/terminate_kernel_device() definition of mali_osk_low_level_mem_init() and term */
+#include <mach/irqs.h>
+#include "arch/config.h"        /* contains the configuration of the arch we are compiling for */
+
+/* is called from mali_kernel_constructor in common code */
+_mali_osk_errcode_t _mali_osk_init( void )
+{
+	if (0 != initialize_kernel_device()) MALI_ERROR(_MALI_OSK_ERR_FAULT);
+
+	mali_osk_low_level_mem_init();
+	
+	MALI_SUCCESS;
+}
+
+/* is called from mali_kernel_deconstructor in common code */
+void _mali_osk_term( void )
+{
+	mali_osk_low_level_mem_term();
+	terminate_kernel_device();
+}
+
+_mali_osk_errcode_t _mali_osk_resources_init( _mali_osk_resource_t **arch_config, u32 *num_resources )
+{
+    *num_resources = sizeof(arch_configuration) / sizeof(arch_configuration[0]);
+    *arch_config = arch_configuration;
+    return _MALI_OSK_ERR_OK;
+}
+
+void _mali_osk_resources_term( _mali_osk_resource_t **arch_config, u32 num_resources )
+{
+    /* Nothing to do */
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_math.c b/drivers/media/video/samsung/mali/linux/mali_osk_math.c
new file mode 100644
index 0000000..3e62e51
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_math.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_math.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include "mali_osk.h"
+#include <linux/bitops.h>
+
+u32 inline _mali_osk_clz( u32 input )
+{
+	return 32-fls(input);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_memory.c b/drivers/media/video/samsung/mali/linux/mali_osk_memory.c
new file mode 100644
index 0000000..871505a
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_memory.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_memory.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include "mali_osk.h"
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+void inline *_mali_osk_calloc( u32 n, u32 size )
+{
+    return kcalloc(n, size, GFP_KERNEL);
+}
+
+void inline *_mali_osk_malloc( u32 size )
+{
+    return kmalloc(size, GFP_KERNEL);
+}
+
+void inline _mali_osk_free( void *ptr )
+{
+    kfree(ptr);
+}
+
+void inline *_mali_osk_valloc( u32 size )
+{
+    return vmalloc(size);
+}
+
+void inline _mali_osk_vfree( void *ptr )
+{
+    vfree(ptr);
+}
+
+void inline *_mali_osk_memcpy( void *dst, const void *src, u32	len )
+{
+    return memcpy(dst, src, len);
+}
+
+void inline *_mali_osk_memset( void *s, u32 c, u32 n )
+{
+    return memset(s, c, n);
+}
+
+mali_bool _mali_osk_mem_check_allocated( u32 max_allocated )
+{
+	/* No need to prevent an out-of-memory dialogue appearing on Linux,
+	 * so we always return MALI_TRUE.
+	 */
+	return MALI_TRUE;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_misc.c b/drivers/media/video/samsung/mali/linux/mali_osk_misc.c
new file mode 100644
index 0000000..e37e8c0
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_misc.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_misc.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+#include <linux/kernel.h>
+#include <asm/uaccess.h>
+#include <asm/cacheflush.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include "mali_osk.h"
+
+void _mali_osk_dbgmsg( const char *fmt, ... )
+{
+    va_list args;
+    va_start(args, fmt);
+    vprintk(fmt, args);
+	va_end(args);
+}
+
+u32 _mali_osk_snprintf( char *buf, u32 size, const char *fmt, ... )
+{
+	int res;
+	va_list args;
+	va_start(args, fmt);
+
+	res = vsnprintf(buf, (size_t)size, fmt, args);
+
+	va_end(args);
+	return res;
+}
+
+void _mali_osk_abort(void)
+{
+	/* make a simple fault by dereferencing a NULL pointer */
+	*(int *)0 = 0;
+}
+
+void _mali_osk_break(void)
+{
+	_mali_osk_abort();
+}
+
+u32 _mali_osk_get_pid(void)
+{
+	/* Thread group ID is the process ID on Linux */
+	return (u32)current->tgid;
+}
+
+u32 _mali_osk_get_tid(void)
+{
+	/* pid is actually identifying the thread on Linux */
+	return (u32)current->pid;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_notification.c b/drivers/media/video/samsung/mali/linux/mali_osk_notification.c
new file mode 100644
index 0000000..74a18e8
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_notification.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_notification.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#include <linux/sched.h>
+#include <linux/slab.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+#include <linux/semaphore.h>
+#else /* pre 2.6.26 the file was in the arch specific location */
+#include <asm/semaphore.h>
+#endif
+
+/**
+ * Declaration of the notification queue object type
+ * Contains a linked list of notification pending delivery to user space.
+ * It also contains a wait queue of exclusive waiters blocked in the ioctl
+ * When a new notification is posted a single thread is resumed.
+ */
+struct _mali_osk_notification_queue_t_struct
+{
+	struct semaphore mutex; /**< Mutex protecting the list */
+	wait_queue_head_t receive_queue; /**< Threads waiting for new entries to the queue */
+	struct list_head head; /**< List of notifications waiting to be picked up */
+};
+
+typedef struct _mali_osk_notification_wrapper_t_struct
+{
+    struct list_head list;           /**< Internal linked list variable */
+    _mali_osk_notification_t data;   /**< Notification data */
+} _mali_osk_notification_wrapper_t;
+
+_mali_osk_notification_queue_t *_mali_osk_notification_queue_init( void )
+{
+	_mali_osk_notification_queue_t *	result;
+
+	result = (_mali_osk_notification_queue_t *)kmalloc(sizeof(_mali_osk_notification_queue_t), GFP_KERNEL);
+	if (NULL == result) return NULL;
+
+	sema_init(&result->mutex, 1);
+	init_waitqueue_head(&result->receive_queue);
+	INIT_LIST_HEAD(&result->head);
+
+	return result;
+}
+
+_mali_osk_notification_t *_mali_osk_notification_create( u32 type, u32 size )
+{
+	/* OPT Recycling of notification objects */
+    _mali_osk_notification_wrapper_t *notification;
+
+	notification = (_mali_osk_notification_wrapper_t *)kmalloc( sizeof(_mali_osk_notification_wrapper_t) + size, GFP_KERNEL );
+    if (NULL == notification)
+    {
+		MALI_DEBUG_PRINT(1, ("Failed to create a notification object\n"));
+		return NULL;
+    }
+
+	/* Init the list */
+	INIT_LIST_HEAD(&notification->list);
+
+	if (0 != size)
+	{
+		notification->data.result_buffer = ((u8*)notification) + sizeof(_mali_osk_notification_wrapper_t);
+	}
+	else
+	{
+		notification->data.result_buffer = NULL;
+	}
+
+	/* set up the non-allocating fields */
+	notification->data.magic_code = 0x31415926;
+	notification->data.notification_type = type;
+	notification->data.result_buffer_size = size;
+
+	/* all ok */
+    return &(notification->data);
+}
+
+void _mali_osk_notification_delete( _mali_osk_notification_t *object )
+{
+	_mali_osk_notification_wrapper_t *notification;
+	MALI_DEBUG_ASSERT_POINTER( object );
+
+    notification = container_of( object, _mali_osk_notification_wrapper_t, data );
+
+	/* Remove from the list */
+	list_del(&notification->list);
+	/* Free the container */
+	kfree(notification);
+}
+
+void _mali_osk_notification_queue_term( _mali_osk_notification_queue_t *queue )
+{
+	MALI_DEBUG_ASSERT_POINTER( queue );
+
+	/* not much to do, just free the memory */
+	kfree(queue);
+}
+
+void _mali_osk_notification_queue_send( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t *object )
+{
+	_mali_osk_notification_wrapper_t *notification;
+	MALI_DEBUG_ASSERT_POINTER( queue );
+	MALI_DEBUG_ASSERT_POINTER( object );
+
+    notification = container_of( object, _mali_osk_notification_wrapper_t, data );
+
+	/* lock queue access */
+	down(&queue->mutex);
+	/* add to list */
+	list_add_tail(&notification->list, &queue->head);
+	/* unlock the queue */
+	up(&queue->mutex);
+
+	/* and wake up one possible exclusive waiter */
+	wake_up(&queue->receive_queue);
+}
+
+static int _mali_notification_queue_is_empty( _mali_osk_notification_queue_t *queue )
+{
+	int ret;
+
+	down(&queue->mutex);
+	ret = list_empty(&queue->head);
+	up(&queue->mutex);
+	return ret;
+}
+
+#if MALI_STATE_TRACKING
+mali_bool _mali_osk_notification_queue_is_empty( _mali_osk_notification_queue_t *queue )
+{
+	return _mali_notification_queue_is_empty(queue) ? MALI_TRUE : MALI_FALSE;
+}
+#endif
+
+_mali_osk_errcode_t _mali_osk_notification_queue_dequeue( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t **result )
+{
+	_mali_osk_errcode_t ret = _MALI_OSK_ERR_ITEM_NOT_FOUND;
+	_mali_osk_notification_wrapper_t *wrapper_object;
+
+	down(&queue->mutex);
+
+	if (!list_empty(&queue->head))
+	{
+		wrapper_object = list_entry(queue->head.next, _mali_osk_notification_wrapper_t, list);
+		*result = &(wrapper_object->data);
+		list_del_init(&wrapper_object->list);
+
+		if (wrapper_object->data.magic_code != 0x31415926) {
+			MALI_PRINT(("SEC WARNING : list entry magic_code not match : %x\n", wrapper_object->data.magic_code));
+			MALI_PRINT(("SEC WARNING : list entry notification type : %x\n", wrapper_object->data.notification_type));
+			MALI_PRINT(("SEC WARNING : list entry result buffer size : %x\n", wrapper_object->data.result_buffer_size));
+			MALI_PRINT(("SEC WARNING : list entry result buffer : %x\n", wrapper_object->data.result_buffer));
+		} else {
+			ret = _MALI_OSK_ERR_OK;
+		}
+	}
+
+	up(&queue->mutex);
+
+	return ret;
+}
+
+_mali_osk_errcode_t _mali_osk_notification_queue_receive( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t **result )
+{
+    /* check input */
+	MALI_DEBUG_ASSERT_POINTER( queue );
+	MALI_DEBUG_ASSERT_POINTER( result );
+
+    /* default result */
+	*result = NULL;
+
+	while (_MALI_OSK_ERR_OK != _mali_osk_notification_queue_dequeue(queue, result))
+	{
+		if (wait_event_interruptible(queue->receive_queue, !_mali_notification_queue_is_empty(queue)))
+		{
+			return _MALI_OSK_ERR_RESTARTSYSCALL;
+		}
+	}
+
+	return _MALI_OSK_ERR_OK; /* all ok */
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_pm.c b/drivers/media/video/samsung/mali/linux/mali_osk_pm.c
new file mode 100644
index 0000000..2438cbc
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_pm.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_pm.c
+ * Implementation of the callback functions from common power management
+ */
+
+#include <linux/sched.h>
+
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif /* CONFIG_PM_RUNTIME */
+
+#include <linux/platform_device.h>
+
+#include "mali_platform.h"
+#include "mali_osk.h"
+#include "mali_uk_types.h"
+#include "mali_pmm.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_license.h"
+#include "mali_linux_pm.h"
+#include "mali_linux_pm_testsuite.h"
+
+#if MALI_LICENSE_IS_GPL
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#ifdef CONFIG_PM_RUNTIME
+static int is_runtime =0;
+#endif /* CONFIG_PM_RUNTIME */
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* MALI_LICENSE_IS_GPL */
+
+#if MALI_POWER_MGMT_TEST_SUITE
+
+#ifdef CONFIG_PM
+unsigned int mali_pmm_events_triggered_mask = 0;
+#endif /* CONFIG_PM */
+
+void _mali_osk_pmm_policy_events_notifications(mali_pmm_event_id mali_pmm_event)
+{
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+
+	switch (mali_pmm_event)
+	{
+		case MALI_PMM_EVENT_JOB_QUEUED:
+			if (mali_job_scheduling_events_recording_on == 1)
+			{
+				mali_pmm_events_triggered_mask |= (1<<0);
+			}
+		break;
+
+		case MALI_PMM_EVENT_JOB_SCHEDULED:
+			if (mali_job_scheduling_events_recording_on == 1)
+			{
+				mali_pmm_events_triggered_mask |= (1<<1);
+			}
+		break;
+
+		case MALI_PMM_EVENT_JOB_FINISHED:
+			if (mali_job_scheduling_events_recording_on == 1)
+			{
+				mali_pmm_events_triggered_mask |= (1<<2);
+				mali_job_scheduling_events_recording_on = 0;
+				pwr_mgmt_status_reg = mali_pmm_events_triggered_mask;
+			}
+		break;
+
+		case MALI_PMM_EVENT_TIMEOUT:
+			if (mali_timeout_event_recording_on == 1)
+			{
+				pwr_mgmt_status_reg = (1<<3);
+				mali_timeout_event_recording_on = 0;
+			}
+		break;
+
+		default:
+
+		break;
+
+	}
+#endif /* CONFIG_PM */
+
+#endif /* MALI_LICENSE_IS_GPL */
+}
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+
+/** This function is called when the Mali device has completed power up
+ * operation.
+ */
+void _mali_osk_pmm_power_up_done(mali_pmm_message_data data)
+{
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	is_wake_up_needed = 1;
+	wake_up_process(pm_thread);
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI OSK Power up Done\n" ));
+	return;
+#endif /* CONFIG_PM */
+#endif /* MALI_LICENSE_IS_GPL */
+}
+
+/** This function is called when the Mali device has completed power down
+ * operation.
+ */
+void _mali_osk_pmm_power_down_done(mali_pmm_message_data data)
+{
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	is_wake_up_needed = 1;
+#if MALI_POWER_MGMT_TEST_SUITE
+	if (is_mali_pmu_present == 0)
+	{
+		pwr_mgmt_status_reg = _mali_pmm_cores_list();
+	}
+#endif /* MALI_POWER_MGMT_TEST_SUITE */
+	wake_up_process(pm_thread);
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI Power down Done\n" ));
+	return;
+
+#endif /* CONFIG_PM */
+#endif /* MALI_LICENSE_IS_GPL */
+}
+
+/** This function is invoked when mali device is idle.
+*/
+_mali_osk_errcode_t _mali_osk_pmm_dev_idle(void)
+{
+	_mali_osk_errcode_t err = 0;
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+
+	err = pm_runtime_put_sync(&(mali_gpu_device.dev));	
+	if(err)
+	{
+		MALI_DEBUG_PRINT(4, ("OSPMM: Error in _mali_osk_pmm_dev_idle\n" ));	
+	}
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+#endif /* MALI_LICENSE_IS_GPL */
+	return err;
+}
+
+/** This funtion is invoked when mali device needs to be activated.
+*/
+int _mali_osk_pmm_dev_activate(void)
+{
+	
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM_RUNTIME
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	int err = 0;
+	if(is_runtime == 0)
+	{
+		pm_suspend_ignore_children(&(mali_gpu_device.dev), true);
+		pm_runtime_enable(&(mali_gpu_device.dev));
+		err = pm_runtime_get_sync(&(mali_gpu_device.dev));
+		is_runtime = 1;
+	}
+	else
+	{
+		err = pm_runtime_get_sync(&(mali_gpu_device.dev));
+	}
+	if(err < 0)
+        {
+		MALI_PRINT(("OSPMM: Error in _mali_osk_pmm_dev_activate, err : %d\n",err ));
+        }
+#endif /* MALI_PMM_RUNTIME_JOB_CONTROL_ON */
+#endif /* CONFIG_PM_RUNTIME */
+#endif /* MALI_LICENSE_IS_GPL */
+
+	return err;
+}
+
+void _mali_osk_pmm_ospmm_cleanup( void )
+{
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	int thread_state;
+	thread_state = mali_get_ospmm_thread_state();
+	if (thread_state)
+	{
+		_mali_osk_pmm_dvfs_operation_done(0);
+	}
+#endif /* CONFIG_PM */
+#endif /* MALI_LICENSE_IS_GPL */
+}
+
+void _mali_osk_pmm_dvfs_operation_done(mali_pmm_message_data data)
+{
+#if MALI_LICENSE_IS_GPL
+#ifdef CONFIG_PM
+	is_wake_up_needed = 1;
+	wake_up_process(dvfs_pm_thread);
+	MALI_DEBUG_PRINT(4, ("OSPMM: MALI OSK DVFS Operation done\n" ));
+	return;
+#endif /* CONFIG_PM */
+#endif /* MALI_LICENSE_IS_GPL */
+}
+
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_profiling.c b/drivers/media/video/samsung/mali/linux/mali_osk_profiling.c
new file mode 100644
index 0000000..98d3937
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_profiling.c
@@ -0,0 +1,47 @@
+#include <linux/module.h>
+#include "mali_linux_trace.h"
+#include "mali_osk.h"
+
+/* The Linux trace point for hardware activity (idle vs running) */
+void _mali_osk_profiling_add_event(u32 event_id, u32 data0)
+{
+    trace_mali_timeline_event(event_id);
+}
+
+/* The Linux trace point for hardware counters */
+void _mali_osk_profiling_add_counter(u32 event_id, u32 data0)
+{
+    trace_mali_hw_counter(event_id, data0);
+}
+
+/* This table stores the event to be counted by each counter
+ * 0xFFFFFFFF is a special value which means disable counter
+ */
+//TODO at the moment this table is indexed by the magic numbers
+//listed in gator_events_mali.c. In future these numbers should
+//be shared through the mali_linux_trace.h header
+u32 counter_table[17] = {0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
+                         0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
+                         0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
+                         0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
+                                                          0xFFFFFFFF};
+
+/* Called by gator.ko to populate the table above */
+int _mali_osk_counter_event(u32 counter, u32 event)
+{
+    /* Remember what has been set, and that a change has occured
+     * When a job actually starts the code will program the registers
+     */
+    //TODO as above these magic numbers need to be moved to a header file
+    if( counter >=5 && counter < 17 ) {
+        counter_table[counter] = event;
+
+        return 1;
+	} else {
+		printk("mali rjc: counter out of range (%d,%d)\n", counter, event);
+    }
+
+    return 0;
+}	
+EXPORT_SYMBOL(_mali_osk_counter_event);
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_specific.h b/drivers/media/video/samsung/mali/linux/mali_osk_specific.h
new file mode 100644
index 0000000..6aacf17
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_specific.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_specific.h
+ * Defines per-OS Kernel level specifics, such as unusual workarounds for
+ * certain OSs.
+ */
+
+#ifndef __MALI_OSK_SPECIFIC_H__
+#define __MALI_OSK_SPECIFIC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MALI_STATIC_INLINE     static inline
+#define MALI_NON_STATIC_INLINE inline
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_OSK_SPECIFIC_H__ */
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_time.c b/drivers/media/video/samsung/mali/linux/mali_osk_time.c
new file mode 100644
index 0000000..da9b865
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_time.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_time.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include "mali_osk.h"
+#include <linux/jiffies.h>
+#include <linux/time.h>
+#include <asm/delay.h>
+
+int	_mali_osk_time_after( u32 ticka, u32 tickb )
+{
+    return time_after((unsigned long)ticka, (unsigned long)tickb);
+}
+
+u32	_mali_osk_time_mstoticks( u32 ms )
+{
+    return msecs_to_jiffies(ms);
+}
+
+u32	_mali_osk_time_tickstoms( u32 ticks )
+{
+    return jiffies_to_msecs(ticks);
+}
+
+u32	_mali_osk_time_tickcount( void )
+{
+    return jiffies;
+}
+
+void _mali_osk_time_ubusydelay( u32 usecs )
+{
+    udelay(usecs);
+}
+
+u64 _mali_osk_time_get_ns( void )
+{
+	struct timespec tsval;
+	getnstimeofday(&tsval);
+	return (u64)timespec_to_ns(&tsval);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_osk_timers.c b/drivers/media/video/samsung/mali/linux/mali_osk_timers.c
new file mode 100644
index 0000000..0454756
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_osk_timers.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_osk_timers.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+#include <linux/timer.h>
+#include <linux/slab.h>
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+
+struct _mali_osk_timer_t_struct
+{
+    struct timer_list timer;
+};
+
+typedef void (*timer_timeout_function_t)(unsigned long);
+
+_mali_osk_timer_t *_mali_osk_timer_init(void)
+{
+    _mali_osk_timer_t *t = (_mali_osk_timer_t*)kmalloc(sizeof(_mali_osk_timer_t), GFP_KERNEL);
+    if (NULL != t) init_timer(&t->timer);
+    return t;
+}
+
+void _mali_osk_timer_add( _mali_osk_timer_t *tim, u32 ticks_to_expire )
+{
+    MALI_DEBUG_ASSERT_POINTER(tim);
+    tim->timer.expires = _mali_osk_time_tickcount() + ticks_to_expire;
+    add_timer(&(tim->timer));
+}
+
+void _mali_osk_timer_mod( _mali_osk_timer_t *tim, u32 expiry_tick)
+{
+    MALI_DEBUG_ASSERT_POINTER(tim);
+    mod_timer(&(tim->timer), expiry_tick);
+}
+
+void _mali_osk_timer_del( _mali_osk_timer_t *tim )
+{
+    MALI_DEBUG_ASSERT_POINTER(tim);
+    del_timer_sync(&(tim->timer));
+}
+
+void _mali_osk_timer_setcallback( _mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data )
+{
+    MALI_DEBUG_ASSERT_POINTER(tim);
+    tim->timer.data = (unsigned long)data;
+    tim->timer.function = (timer_timeout_function_t)callback;
+}
+
+void _mali_osk_timer_term( _mali_osk_timer_t *tim )
+{
+    MALI_DEBUG_ASSERT_POINTER(tim);
+    kfree(tim);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_core.c b/drivers/media/video/samsung/mali/linux/mali_ukk_core.c
new file mode 100644
index 0000000..59eafe2
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_core.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <linux/slab.h>     /* memort allocation functions */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+int get_api_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_api_version_s __user *uargs)
+{
+	_mali_uk_get_api_version_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    if (0 != get_user(kargs.version, &uargs->version)) return -EFAULT;
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_get_api_version(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.version, &uargs->version)) return -EFAULT;
+    if (0 != put_user(kargs.compatible, &uargs->compatible)) return -EFAULT;
+
+    return 0;
+}
+
+int get_system_info_size_wrapper(struct mali_session_data *session_data, _mali_uk_get_system_info_size_s __user *uargs)
+{
+	_mali_uk_get_system_info_size_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_get_system_info_size(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.size, &uargs->size)) return -EFAULT;
+
+    return 0;
+}
+
+int get_system_info_wrapper(struct mali_session_data *session_data, _mali_uk_get_system_info_s __user *uargs)
+{
+	_mali_uk_get_system_info_s kargs;
+    _mali_osk_errcode_t err;
+    _mali_system_info *system_info_user;
+    _mali_system_info *system_info_kernel;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    if (0 != get_user(kargs.system_info, &uargs->system_info)) return -EFAULT;
+    if (0 != get_user(kargs.size, &uargs->size)) return -EFAULT;
+
+    /* A temporary kernel buffer for the system_info datastructure is passed through the system_info
+     * member. The ukk_private member will point to the user space destination of this buffer so
+     * that _mali_ukk_get_system_info() can correct the pointers in the system_info correctly
+     * for user space.
+     */
+    system_info_kernel = kmalloc(kargs.size, GFP_KERNEL);
+    if (NULL == system_info_kernel) return -EFAULT;
+
+    system_info_user = kargs.system_info;
+    kargs.system_info = system_info_kernel;
+    kargs.ukk_private = (u32)system_info_user;
+    kargs.ctx = session_data;
+
+    err = _mali_ukk_get_system_info(&kargs);
+    if (_MALI_OSK_ERR_OK != err)
+    {
+        kfree(system_info_kernel);
+        return map_errcode(err);
+    }
+
+    if (0 != copy_to_user(system_info_user, system_info_kernel, kargs.size))
+    {
+        kfree(system_info_kernel);
+        return -EFAULT;
+    }
+
+    kfree(system_info_kernel);
+    return 0;
+}
+
+int wait_for_notification_wrapper(struct mali_session_data *session_data, _mali_uk_wait_for_notification_s __user *uargs)
+{
+    _mali_uk_wait_for_notification_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_wait_for_notification(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	if(_MALI_NOTIFICATION_CORE_SHUTDOWN_IN_PROGRESS != kargs.type)
+	{
+		kargs.ctx = NULL; /* prevent kernel address to be returned to user space */
+		if (0 != copy_to_user(uargs, &kargs, sizeof(_mali_uk_wait_for_notification_s))) return -EFAULT;
+	}
+	else
+	{
+		if (0 != put_user(kargs.type, &uargs->type)) return -EFAULT;
+	}
+
+    return 0;
+}
+
+int post_notification_wrapper(struct mali_session_data *session_data, _mali_uk_post_notification_s __user *uargs)
+{
+	_mali_uk_post_notification_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	kargs.ctx = session_data;
+
+	if (0 != get_user(kargs.type, &uargs->type))
+	{
+		return -EFAULT;
+	}
+
+	err = _mali_ukk_post_notification(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_gp.c b/drivers/media/video/samsung/mali/linux/mali_ukk_gp.c
new file mode 100644
index 0000000..58ff1de
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_gp.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+int gp_start_job_wrapper(struct mali_session_data *session_data, _mali_uk_gp_start_job_s __user *uargs)
+{
+    _mali_uk_gp_start_job_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+	if (!access_ok(VERIFY_WRITE, uargs, sizeof(_mali_uk_gp_start_job_s)))
+	{
+		return -EFAULT;
+	}
+
+    if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_gp_start_job_s))) return -EFAULT;
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_gp_start_job(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    kargs.ctx = NULL; /* prevent kernel address to be returned to user space */
+    if (0 != copy_to_user(uargs, &kargs, sizeof(_mali_uk_gp_start_job_s)))
+	{
+		/*
+		 * If this happens, then user space will not know that the job was actually started,
+		 * and if we return a queued job, then user space will still think that one is still queued.
+		 * This will typically lead to a deadlock in user space.
+		 * This could however only happen if user space deliberately passes a user buffer which
+		 * passes the access_ok(VERIFY_WRITE) check, but isn't fully writable at the time of copy_to_user().
+		 * The official Mali driver will never attempt to do that, and kernel space should not be affected.
+		 * That is why we do not bother to do a complex rollback in this very very very rare case.
+		 */
+		return -EFAULT;
+	}
+
+    return 0;
+}
+
+int gp_abort_job_wrapper(struct mali_session_data *session_data, _mali_uk_gp_abort_job_s __user *uargs)
+{
+    _mali_uk_gp_abort_job_s kargs;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_gp_abort_job_s))) return -EFAULT;
+
+    kargs.ctx = session_data;
+    _mali_ukk_gp_abort_job(&kargs);
+
+    return 0;
+}
+
+
+int gp_get_core_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_gp_core_version_s __user *uargs)
+{
+    _mali_uk_get_gp_core_version_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    kargs.ctx = session_data;
+    err =  _mali_ukk_get_gp_core_version(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	/* no known transactions to roll-back */
+
+    if (0 != put_user(kargs.version, &uargs->version)) return -EFAULT;
+
+    return 0;
+}
+
+int gp_suspend_response_wrapper(struct mali_session_data *session_data, _mali_uk_gp_suspend_response_s __user *uargs)
+{
+    _mali_uk_gp_suspend_response_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_gp_suspend_response_s))) return -EFAULT;
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_gp_suspend_response(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.cookie, &uargs->cookie)) return -EFAULT;
+
+    /* no known transactions to roll-back */
+    return 0;
+}
+
+int gp_get_number_of_cores_wrapper(struct mali_session_data *session_data, _mali_uk_get_gp_number_of_cores_s __user *uargs)
+{
+    _mali_uk_get_gp_number_of_cores_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_get_gp_number_of_cores(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	/* no known transactions to roll-back */
+
+    if (0 != put_user(kargs.number_of_cores, &uargs->number_of_cores)) return -EFAULT;
+
+    return 0;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_mem.c b/drivers/media/video/samsung/mali/linux/mali_ukk_mem.c
new file mode 100644
index 0000000..0b98e41
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_mem.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+int mem_init_wrapper(struct mali_session_data *session_data, _mali_uk_init_mem_s __user *uargs)
+{
+    _mali_uk_init_mem_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_init_mem(&kargs);
+    if (_MALI_OSK_ERR_OK != err)
+    {
+        return map_errcode(err);
+    }
+
+    if (0 != put_user(kargs.mali_address_base, &uargs->mali_address_base)) goto mem_init_rollback;
+    if (0 != put_user(kargs.memory_size, &uargs->memory_size)) goto mem_init_rollback;
+
+    return 0;
+
+mem_init_rollback:
+	{
+		_mali_uk_term_mem_s kargs;
+		kargs.ctx = session_data;
+		err = _mali_ukk_term_mem(&kargs);
+		if (_MALI_OSK_ERR_OK != err)
+		{
+			MALI_DEBUG_PRINT(4, ("reverting _mali_ukk_init_mem, as a result of failing put_user(), failed\n"));
+		}
+	}
+    return -EFAULT;
+}
+
+int mem_term_wrapper(struct mali_session_data *session_data, _mali_uk_term_mem_s __user *uargs)
+{
+    _mali_uk_term_mem_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_term_mem(&kargs);
+    if (_MALI_OSK_ERR_OK != err)
+    {
+        return map_errcode(err);
+    }
+
+    return 0;
+}
+
+int mem_map_ext_wrapper(struct mali_session_data *session_data, _mali_uk_map_external_mem_s __user * argument)
+{
+	_mali_uk_map_external_mem_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL);
+
+	/* get call arguments from user space. copy_from_user returns how many bytes which where NOT copied */
+	if ( 0 != copy_from_user(&uk_args, (void __user *)argument, sizeof(_mali_uk_map_external_mem_s)) )
+	{
+		return -EFAULT;
+	}
+
+    uk_args.ctx = session_data;
+	err_code = _mali_ukk_map_external_mem( &uk_args );
+
+    if (0 != put_user(uk_args.cookie, &argument->cookie))
+    {
+        if (_MALI_OSK_ERR_OK == err_code)
+        {
+            /* Rollback */
+           	_mali_uk_unmap_external_mem_s uk_args_unmap;
+
+            uk_args_unmap.ctx = session_data;
+            uk_args_unmap.cookie = uk_args.cookie;
+            err_code = _mali_ukk_unmap_external_mem( &uk_args_unmap );
+            if (_MALI_OSK_ERR_OK != err_code)
+            {
+                MALI_DEBUG_PRINT(4, ("reverting _mali_ukk_unmap_external_mem, as a result of failing put_user(), failed\n"));
+            }
+        }
+        return -EFAULT;
+    }
+
+    /* Return the error that _mali_ukk_free_big_block produced */
+	return map_errcode(err_code);
+}
+
+int mem_unmap_ext_wrapper(struct mali_session_data *session_data, _mali_uk_unmap_external_mem_s __user * argument)
+{
+	_mali_uk_unmap_external_mem_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL);
+
+	/* get call arguments from user space. copy_from_user returns how many bytes which where NOT copied */
+	if ( 0 != copy_from_user(&uk_args, (void __user *)argument, sizeof(_mali_uk_unmap_external_mem_s)) )
+	{
+		return -EFAULT;
+	}
+
+    uk_args.ctx = session_data;
+	err_code = _mali_ukk_unmap_external_mem( &uk_args );
+
+	/* Return the error that _mali_ukk_free_big_block produced */
+	return map_errcode(err_code);
+}
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+int mem_release_ump_wrapper(struct mali_session_data *session_data, _mali_uk_release_ump_mem_s __user * argument)
+{
+	_mali_uk_release_ump_mem_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL);
+
+	/* get call arguments from user space. copy_from_user returns how many bytes which where NOT copied */
+	if ( 0 != copy_from_user(&uk_args, (void __user *)argument, sizeof(_mali_uk_release_ump_mem_s)) )
+	{
+		return -EFAULT;
+	}
+
+    uk_args.ctx = session_data;
+	err_code = _mali_ukk_release_ump_mem( &uk_args );
+
+	/* Return the error that _mali_ukk_free_big_block produced */
+	return map_errcode(err_code);
+}
+
+int mem_attach_ump_wrapper(struct mali_session_data *session_data, _mali_uk_attach_ump_mem_s __user * argument)
+{
+	_mali_uk_attach_ump_mem_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL);
+
+	/* get call arguments from user space. copy_from_user returns how many bytes which where NOT copied */
+	if ( 0 != copy_from_user(&uk_args, (void __user *)argument, sizeof(_mali_uk_attach_ump_mem_s)) )
+	{
+		return -EFAULT;
+	}
+
+    uk_args.ctx = session_data;
+	err_code = _mali_ukk_attach_ump_mem( &uk_args );
+
+    if (0 != put_user(uk_args.cookie, &argument->cookie))
+    {
+        if (_MALI_OSK_ERR_OK == err_code)
+        {
+            /* Rollback */
+           	_mali_uk_release_ump_mem_s uk_args_unmap;
+
+            uk_args_unmap.ctx = session_data;
+            uk_args_unmap.cookie = uk_args.cookie;
+            err_code = _mali_ukk_release_ump_mem( &uk_args_unmap );
+            if (_MALI_OSK_ERR_OK != err_code)
+            {
+                MALI_DEBUG_PRINT(4, ("reverting _mali_ukk_attach_mem, as a result of failing put_user(), failed\n"));
+            }
+        }
+        return -EFAULT;
+    }
+
+    /* Return the error that _mali_ukk_map_external_ump_mem produced */
+	return map_errcode(err_code);
+}
+#endif /* MALI_USE_UNIFIED_MEMORY_PROVIDER */
+
+int mem_query_mmu_page_table_dump_size_wrapper(struct mali_session_data *session_data, _mali_uk_query_mmu_page_table_dump_size_s __user * uargs)
+{
+    _mali_uk_query_mmu_page_table_dump_size_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    kargs.ctx = session_data;
+
+    err = _mali_ukk_query_mmu_page_table_dump_size(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.size, &uargs->size)) return -EFAULT;
+
+    return 0;
+}
+
+int mem_dump_mmu_page_table_wrapper(struct mali_session_data *session_data, _mali_uk_dump_mmu_page_table_s __user * uargs)
+{
+    _mali_uk_dump_mmu_page_table_s kargs;
+    _mali_osk_errcode_t err;
+    void *buffer;
+    int rc = -EFAULT;
+
+	/* validate input */
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+	/* the session_data pointer was validated by caller */
+
+    kargs.buffer = NULL;
+
+    /* get location of user buffer */
+	if (0 != get_user(buffer, &uargs->buffer)) goto err_exit;
+	/* get size of mmu page table info buffer from user space */
+	if ( 0 != get_user(kargs.size, &uargs->size) ) goto err_exit;
+    /* verify we can access the whole of the user buffer */
+    if (!access_ok(VERIFY_WRITE, buffer, kargs.size)) goto err_exit;
+
+    /* allocate temporary buffer (kernel side) to store mmu page table info */
+    kargs.buffer = _mali_osk_valloc(kargs.size);
+    if (NULL == kargs.buffer)
+    {
+        rc = -ENOMEM;
+        goto err_exit;
+    }
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_dump_mmu_page_table(&kargs);
+    if (_MALI_OSK_ERR_OK != err)
+    {
+        rc = map_errcode(err);
+        goto err_exit;
+    }
+
+    /* copy mmu page table info back to user space and update pointers */
+	if (0 != copy_to_user(uargs->buffer, kargs.buffer, kargs.size) ) goto err_exit;
+    if (0 != put_user((kargs.register_writes - (u32 *)kargs.buffer) + (u32 *)uargs->buffer, &uargs->register_writes)) goto err_exit;
+    if (0 != put_user((kargs.page_table_dump - (u32 *)kargs.buffer) + (u32 *)uargs->buffer, &uargs->page_table_dump)) goto err_exit;
+    if (0 != put_user(kargs.register_writes_size, &uargs->register_writes_size)) goto err_exit;
+    if (0 != put_user(kargs.page_table_dump_size, &uargs->page_table_dump_size)) goto err_exit;
+    rc = 0;
+
+err_exit:
+    if (kargs.buffer) _mali_osk_vfree(kargs.buffer);
+    return rc;
+}
+
+
+
+int mem_get_big_block_wrapper( struct file * filp, _mali_uk_get_big_block_s __user * argument )
+{
+	_mali_uk_get_big_block_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL);
+
+	/* get call arguments from user space. copy_from_user returns how many bytes which where NOT copied */
+	if ( 0 != copy_from_user(&uk_args, (void __user *)argument, sizeof(_mali_uk_get_big_block_s)) )
+	{
+		return -EFAULT;
+	}
+
+	/* This interface inserts something into the ukk_private word */
+    uk_args.ukk_private = (u32)filp;
+    uk_args.ctx = filp->private_data;
+	err_code = _mali_ukk_get_big_block( &uk_args );
+
+	/* Do not leak the private word back into user space */
+	uk_args.ukk_private = 0;
+
+	if ( _MALI_OSK_ERR_OK != err_code )
+	{
+		return map_errcode(err_code);
+	}
+
+	/* From this point on, we must roll-back any failing action to preserve the
+	 * meaning of the U/K interface (e.g. when excluded) */
+
+	/* transfer response back to user space */
+	if ( 0 != copy_to_user(argument, &uk_args, sizeof(_mali_uk_get_big_block_s)) )
+	{
+		/* Roll-back - the _mali_uk_get_big_block call succeeded, so all
+		 * values in uk_args will be correct */
+		_mali_uk_free_big_block_s uk_args_rollback = {0, };
+
+		uk_args_rollback.ctx = uk_args.ctx;
+		uk_args_rollback.cookie = uk_args.cookie;
+		err_code = _mali_ukk_free_big_block( &uk_args_rollback );
+
+		if ( _MALI_OSK_ERR_OK != err_code )
+		{
+			/* error in DEBUG and RELEASE */
+			MALI_PRINT_ERROR( ("Failed to rollback get_big_block: %.8X\n", (u32)err_code) );
+		}
+        return -EFAULT;
+	}
+
+    return 0;
+}
+
+int mem_free_big_block_wrapper(struct mali_session_data *session_data, _mali_uk_free_big_block_s __user * argument)
+{
+	_mali_uk_free_big_block_s uk_args;
+	_mali_osk_errcode_t err_code;
+
+	/* validate input */
+	/* the session_data pointer was validated by caller */
+    MALI_CHECK_NON_NULL( argument, -EINVAL );
+
+	/* get call arguments from user space. get_user returns 0 on success */
+	if ( 0 != get_user(uk_args.cookie, &argument->cookie) )
+	{
+		return -EFAULT;
+	}
+
+    uk_args.ctx = session_data;
+	err_code = _mali_ukk_free_big_block( &uk_args );
+
+	/* Return the error that _mali_ukk_free_big_block produced */
+	return map_errcode(err_code);
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_pp.c b/drivers/media/video/samsung/mali/linux/mali_ukk_pp.c
new file mode 100644
index 0000000..31e2a6a
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_pp.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+int pp_start_job_wrapper(struct mali_session_data *session_data, _mali_uk_pp_start_job_s __user *uargs)
+{
+	_mali_uk_pp_start_job_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+	MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+	if (!access_ok(VERIFY_WRITE, uargs, sizeof(_mali_uk_pp_start_job_s)))
+	{
+		return -EFAULT;
+	}
+
+	if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_pp_start_job_s))) return -EFAULT;
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_pp_start_job(&kargs);
+	if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+	if (0 != put_user(kargs.returned_user_job_ptr, &uargs->returned_user_job_ptr) ||
+	    0 != put_user(kargs.status, &uargs->status))
+	{
+		/*
+		 * If this happens, then user space will not know that the job was actually started,
+		 * and if we return a queued job, then user space will still think that one is still queued.
+		 * This will typically lead to a deadlock in user space.
+		 * This could however only happen if user space deliberately passes a user buffer which
+		 * passes the access_ok(VERIFY_WRITE) check, but isn't fully writable at the time of copy_to_user().
+		 * The official Mali driver will never attempt to do that, and kernel space should not be affected.
+		 * That is why we do not bother to do a complex rollback in this very very very rare case.
+		 */
+		return -EFAULT;
+	}
+
+    return 0;
+}
+
+int pp_abort_job_wrapper(struct mali_session_data *session_data, _mali_uk_pp_abort_job_s __user *uargs)
+{
+    _mali_uk_pp_abort_job_s kargs;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_pp_abort_job_s))) return -EFAULT;
+
+    kargs.ctx = session_data;
+    _mali_ukk_pp_abort_job(&kargs);
+
+    return 0;
+}
+
+int pp_get_number_of_cores_wrapper(struct mali_session_data *session_data, _mali_uk_get_pp_number_of_cores_s __user *uargs)
+{
+    _mali_uk_get_pp_number_of_cores_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_get_pp_number_of_cores(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.number_of_cores, &uargs->number_of_cores)) return -EFAULT;
+
+    return 0;
+}
+
+int pp_get_core_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_pp_core_version_s __user *uargs)
+{
+    _mali_uk_get_pp_core_version_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    MALI_CHECK_NON_NULL(session_data, -EINVAL);
+
+    kargs.ctx = session_data;
+    err = _mali_ukk_get_pp_core_version(&kargs);
+    if (_MALI_OSK_ERR_OK != err) return map_errcode(err);
+
+    if (0 != put_user(kargs.version, &uargs->version)) return -EFAULT;
+
+    return 0;
+}
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_profiling.c b/drivers/media/video/samsung/mali/linux/mali_ukk_profiling.c
new file mode 100644
index 0000000..17366be
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_profiling.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+int profiling_start_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_start_s __user *uargs)
+{
+	_mali_uk_profiling_start_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_profiling_start_s)))
+	{
+		return -EFAULT;
+	}
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_profiling_start(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	if (0 != put_user(kargs.limit, &uargs->limit))
+	{
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int profiling_add_event_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_add_event_s __user *uargs)
+{
+	_mali_uk_profiling_add_event_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_profiling_add_event_s)))
+	{
+		return -EFAULT;
+	}
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_profiling_add_event(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	return 0;
+}
+
+int profiling_stop_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_stop_s __user *uargs)
+{
+	_mali_uk_profiling_stop_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_profiling_stop(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	if (0 != put_user(kargs.count, &uargs->count))
+	{
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int profiling_get_event_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_get_event_s __user *uargs)
+{
+	_mali_uk_profiling_get_event_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	if (0 != get_user(kargs.index, &uargs->index))
+	{
+		return -EFAULT;
+	}
+
+	kargs.ctx = session_data;
+
+	err = _mali_ukk_profiling_get_event(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	kargs.ctx = NULL; /* prevent kernel address to be returned to user space */
+	if (0 != copy_to_user(uargs, &kargs, sizeof(_mali_uk_profiling_get_event_s)))
+	{
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int profiling_clear_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_clear_s __user *uargs)
+{
+	_mali_uk_profiling_clear_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_profiling_clear(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	return 0;
+}
+
+int profiling_get_config_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_get_config_s __user *uargs)
+{
+	_mali_uk_profiling_get_config_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_profiling_get_config(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	if (0 != put_user(kargs.enable_events, &uargs->enable_events))
+	{
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+#if MALI_TRACEPOINTS_ENABLED
+int transfer_sw_counters_wrapper(struct mali_session_data *session_data, _mali_uk_sw_counters_s __user *uargs)
+{
+    _mali_uk_sw_counters_s kargs;
+    _mali_osk_errcode_t err;
+
+    MALI_CHECK_NON_NULL(uargs, -EINVAL);
+    
+    kargs.ctx = session_data;
+
+    if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_sw_counters_s)))
+    {
+        return -EFAULT;
+    }
+
+    err = _mali_ukk_transfer_sw_counters(&kargs);
+
+    if (_MALI_OSK_ERR_OK != err)
+    {
+        return map_errcode(err);
+    }
+
+    return 0;
+}
+#endif
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_vsync.c b/drivers/media/video/samsung/mali/linux/mali_ukk_vsync.c
new file mode 100644
index 0000000..80a6afd
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_vsync.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/fs.h>       /* file system operations */
+#include <asm/uaccess.h>    /* user space access */
+
+#include "mali_ukk.h"
+#include "mali_osk.h"
+#include "mali_kernel_common.h"
+#include "mali_kernel_session_manager.h"
+#include "mali_ukk_wrappers.h"
+
+
+int vsync_event_report_wrapper(struct mali_session_data *session_data, _mali_uk_vsync_event_report_s __user *uargs)
+{
+	_mali_uk_vsync_event_report_s kargs;
+	_mali_osk_errcode_t err;
+
+	MALI_CHECK_NON_NULL(uargs, -EINVAL);
+
+	if (0 != copy_from_user(&kargs, uargs, sizeof(_mali_uk_vsync_event_report_s)))
+	{
+		return -EFAULT;
+	}
+
+	kargs.ctx = session_data;
+	err = _mali_ukk_vsync_event_report(&kargs);
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		return map_errcode(err);
+	}
+
+	return 0;
+}
+
diff --git a/drivers/media/video/samsung/mali/linux/mali_ukk_wrappers.h b/drivers/media/video/samsung/mali/linux/mali_ukk_wrappers.h
new file mode 100644
index 0000000..184ce8d
--- /dev/null
+++ b/drivers/media/video/samsung/mali/linux/mali_ukk_wrappers.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_ukk_wrappers.h
+ * Defines the wrapper functions for each user-kernel function
+ */
+
+#ifndef __MALI_UKK_WRAPPERS_H__
+#define __MALI_UKK_WRAPPERS_H__
+
+#include "mali_uk_types.h"
+#include "mali_osk.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+int get_system_info_size_wrapper(struct mali_session_data *session_data, _mali_uk_get_system_info_size_s __user *uargs);
+int get_system_info_wrapper(struct mali_session_data *session_data, _mali_uk_get_system_info_s __user *uargs);
+int wait_for_notification_wrapper(struct mali_session_data *session_data, _mali_uk_wait_for_notification_s __user *uargs);
+int get_api_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_api_version_s __user *uargs);
+int post_notification_wrapper(struct mali_session_data *session_data, _mali_uk_post_notification_s __user *uargs);
+int mem_init_wrapper(struct mali_session_data *session_data, _mali_uk_init_mem_s __user *uargs);
+int mem_term_wrapper(struct mali_session_data *session_data, _mali_uk_term_mem_s __user *uargs);
+int mem_map_ext_wrapper(struct mali_session_data *session_data, _mali_uk_map_external_mem_s __user * argument);
+int mem_unmap_ext_wrapper(struct mali_session_data *session_data, _mali_uk_unmap_external_mem_s __user * argument);
+int mem_query_mmu_page_table_dump_size_wrapper(struct mali_session_data *session_data, _mali_uk_query_mmu_page_table_dump_size_s __user * uargs);
+int mem_dump_mmu_page_table_wrapper(struct mali_session_data *session_data, _mali_uk_dump_mmu_page_table_s __user * uargs);
+
+#if MALI_USE_UNIFIED_MEMORY_PROVIDER != 0
+int mem_attach_ump_wrapper(struct mali_session_data *session_data, _mali_uk_attach_ump_mem_s __user * argument);
+int mem_release_ump_wrapper(struct mali_session_data *session_data, _mali_uk_release_ump_mem_s __user * argument);
+#endif /* MALI_USE_UNIFIED_MEMORY_PROVIDER */
+
+int mem_get_big_block_wrapper( struct file * filp, _mali_uk_get_big_block_s __user * argument );
+int mem_free_big_block_wrapper( struct mali_session_data *session_data, _mali_uk_free_big_block_s __user * argument);
+int pp_start_job_wrapper(struct mali_session_data *session_data, _mali_uk_pp_start_job_s __user *uargs);
+int pp_abort_job_wrapper(struct mali_session_data *session_data, _mali_uk_pp_abort_job_s __user *uargs);
+int pp_get_number_of_cores_wrapper(struct mali_session_data *session_data, _mali_uk_get_pp_number_of_cores_s __user *uargs);
+int pp_get_core_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_pp_core_version_s __user *uargs);
+int gp_start_job_wrapper(struct mali_session_data *session_data, _mali_uk_gp_start_job_s __user *uargs);
+int gp_abort_job_wrapper(struct mali_session_data *session_data, _mali_uk_gp_abort_job_s __user *uargs);
+int gp_get_number_of_cores_wrapper(struct mali_session_data *session_data, _mali_uk_get_gp_number_of_cores_s __user *uargs);
+int gp_get_core_version_wrapper(struct mali_session_data *session_data, _mali_uk_get_gp_core_version_s __user *uargs);
+int gp_suspend_response_wrapper(struct mali_session_data *session_data, _mali_uk_gp_suspend_response_s __user *uargs);
+
+int profiling_start_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_start_s __user *uargs);
+int profiling_add_event_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_add_event_s __user *uargs);
+int profiling_stop_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_stop_s __user *uargs);
+int profiling_get_event_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_get_event_s __user *uargs);
+int profiling_clear_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_clear_s __user *uargs);
+int profiling_get_config_wrapper(struct mali_session_data *session_data, _mali_uk_profiling_get_config_s __user *uargs);
+
+int vsync_event_report_wrapper(struct mali_session_data *session_data, _mali_uk_vsync_event_report_s __user *uargs);
+
+#if MALI_TRACEPOINTS_ENABLED
+int transfer_sw_counters_wrapper(struct mali_session_data *session_data, _mali_uk_sw_counters_s __user *uargs);
+#endif
+
+int map_errcode( _mali_osk_errcode_t err );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALI_UKK_WRAPPERS_H__ */
diff --git a/drivers/media/video/samsung/mali/platform/default/mali_platform.c b/drivers/media/video/samsung/mali/platform/default/mali_platform.c
new file mode 100644
index 0000000..44f877e
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/default/mali_platform.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform.c
+ * Platform specific Mali driver functions for a default platform
+ */
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+
+
+_mali_osk_errcode_t mali_platform_init(void)
+{
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_deinit(void)
+{
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
+{
+    MALI_SUCCESS;
+}
+
+void mali_gpu_utilization_handler(u32 utilization)
+{
+}
+
+void set_mali_parent_power_domain(void* dev)
+{
+}
diff --git a/drivers/media/video/samsung/mali/platform/mali_platform.h b/drivers/media/video/samsung/mali/platform/mali_platform.h
new file mode 100644
index 0000000..70cfa14
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/mali_platform.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform.h
+ * Platform specific Mali driver functions
+ */
+
+#ifndef __MALI_PLATFORM_H__
+#define __MALI_PLATFORM_H__
+
+#include "mali_osk.h"
+
+#ifdef CONFIG_CPU_EXYNOS4210
+#define MALI_DVFS_STEPS 2
+#else
+#define MALI_DVFS_STEPS 4
+#endif
+
+#if !USING_MALI_PMM
+/* @brief System power up/down cores that can be passed into mali_platform_powerdown/up() */
+#define MALI_PLATFORM_SYSTEM  0
+#endif
+
+/* @Enable or Disable Mali GPU Bottom Lock feature */
+#define MALI_GPU_BOTTOM_LOCK 1
+
+#define MALI_VOLTAGE_LOCK 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief description of power change reasons
+ */
+typedef enum mali_power_mode_tag
+{
+	MALI_POWER_MODE_ON,
+	MALI_POWER_MODE_LIGHT_SLEEP,
+	MALI_POWER_MODE_DEEP_SLEEP,
+} mali_power_mode;
+
+/** @brief Platform specific setup and initialisation of MALI
+ *
+ * This is called from the entrypoint of the driver to initialize the platform
+ *
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_init(void);
+
+/** @brief Platform specific deinitialisation of MALI
+ *
+ * This is called on the exit of the driver to terminate the platform
+ *
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_deinit(void);
+
+/** @brief Platform specific powerdown sequence of MALI
+ *
+ * Call as part of platform init if there is no PMM support, else the
+ * PMM will call it.
+ * There are three power modes defined:
+ *  1) MALI_POWER_MODE_ON
+ *  2) MALI_POWER_MODE_LIGHT_SLEEP
+ *  3) MALI_POWER_MODE_DEEP_SLEEP
+ * MALI power management module transitions to MALI_POWER_MODE_LIGHT_SLEEP mode when MALI is idle
+ * for idle timer (software timer defined in mali_pmm_policy_jobcontrol.h) duration, MALI transitions
+ * to MALI_POWER_MODE_LIGHT_SLEEP mode during timeout if there are no more jobs queued.
+ * MALI power management module transitions to MALI_POWER_MODE_DEEP_SLEEP mode when OS does system power
+ * off.
+ * Customer has to add power down code when MALI transitions to MALI_POWER_MODE_LIGHT_SLEEP or MALI_POWER_MODE_DEEP_SLEEP
+ * mode.
+ * MALI_POWER_MODE_ON mode is entered when the MALI is to powered up. Some customers want to control voltage regulators during
+ * the whole system powers on/off. Customer can track in this function whether the MALI is powered up from
+ * MALI_POWER_MODE_LIGHT_SLEEP or MALI_POWER_MODE_DEEP_SLEEP mode and manage the voltage regulators as well.
+ * @param power_mode defines the power modes
+ * @return _MALI_OSK_ERR_OK on success otherwise, a suitable _mali_osk_errcode_t error.
+ */
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode);
+
+
+/** @brief Platform specific handling of GPU utilization data
+ *
+ * When GPU utilization data is enabled, this function will be
+ * periodically called.
+ *
+ * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
+ */
+void mali_gpu_utilization_handler(u32 utilization);
+
+/** @brief Setting the power domain of MALI
+ *
+ * This function sets the power domain of MALI if Linux run time power management is enabled
+ *
+ * @param dev Reference to struct platform_device (defined in linux) used by MALI GPU
+ */
+//void set_mali_parent_power_domain(void* dev);
+void mali_utilization_suspend(void);
+
+#ifdef CONFIG_REGULATOR
+int mali_regulator_get_usecount(void);
+void mali_regulator_disable(void);
+void mali_regulator_enable(void);
+void mali_regulator_set_voltage(int min_uV, int max_uV);
+#endif
+mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz);
+unsigned long mali_clk_get_rate(void);
+void mali_clk_put(mali_bool binc_mali_clk);
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+_mali_osk_errcode_t mali_platform_powerdown(u32 cores);
+_mali_osk_errcode_t mali_platform_powerup(u32 cores);
+#endif
+
+
+#if USING_MALI_PMM
+#if MALI_POWER_MGMT_TEST_SUITE
+/** @brief function to get status of individual cores
+ *
+ * This function is used by power management test suite to get the status of powered up/down the number
+ * of cores
+ * @param utilization The workload utilization of the Mali GPU. 0 = no utilization, 256 = full utilization.
+ */
+u32 pmu_get_power_up_down_info(void);
+#endif
+#endif
+
+#if MALI_DVFS_ENABLED
+mali_bool init_mali_dvfs_status(int step);
+void deinit_mali_dvfs_status(void);
+mali_bool mali_dvfs_handler(u32 utilization);
+int mali_dvfs_is_running(void);
+void mali_dvfs_late_resume(void);
+int get_mali_dvfs_control_status(void);
+mali_bool set_mali_dvfs_current_step(unsigned int step);
+void mali_default_step_set(int step, mali_bool boostup);
+int change_dvfs_tableset(int change_clk, int change_step);
+#ifdef CONFIG_CPU_EXYNOS4210
+#if MALI_GPU_BOTTOM_LOCK
+int mali_dvfs_bottom_lock_push(void);
+int mali_dvfs_bottom_lock_pop(void);
+#endif
+#else
+int mali_dvfs_bottom_lock_push(int lock_step);
+int mali_dvfs_bottom_lock_pop(void);
+#endif
+#endif
+
+#if MALI_VOLTAGE_LOCK
+int mali_voltage_lock_push(int lock_vol);
+int mali_voltage_lock_pop(void);
+int mali_voltage_lock_init(void);
+int mali_vol_get_from_table(int vol);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c
new file mode 100644
index 0000000..0fc4503
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform.c
+ * Platform specific Mali driver functions for a default platform
+ */
+#include <linux/version.h>
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+#include "mali_linux_pm.h"
+
+#if USING_MALI_PMM
+#include "mali_pmm.h"
+#endif
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#include <plat/pd.h>
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+
+#include <asm/io.h>
+#include <mach/regs-pmu.h>
+
+#define EXTXTALCLK_NAME 		"ext_xtal"
+#define VPLLSRCCLK_NAME 		"vpll_src"
+#define FOUTVPLLCLK_NAME 		"fout_vpll"
+#define SCLVPLLCLK_NAME 		"sclk_vpll"
+#define GPUMOUT1CLK_NAME 		"mout_g3d1"
+
+#define MPLLCLK_NAME 		"mout_mpll"
+#define GPUMOUT0CLK_NAME 	"mout_g3d0"
+#define GPUCLK_NAME 		"sclk_g3d"
+#define CLK_DIV_STAT_G3D 	0x1003C62C
+#define CLK_DESC 		"clk-divider-status"
+
+static struct clk               *ext_xtal_clock = 0;
+static struct clk               *vpll_src_clock = 0;
+static struct clk               *fout_vpll_clock = 0;
+static struct clk               *sclk_vpll_clock = 0;
+
+static struct clk               *mpll_clock = 0;
+static struct clk               *mali_parent_clock = 0;
+static struct clk               *mali_clock = 0;
+
+int mali_gpu_clk 	=		160;
+static unsigned int GPU_MHZ	=		1000000;
+#ifdef CONFIG_S5PV310_ASV
+int mali_gpu_vol     =               1100000;        /* 1.10V for ASV */
+#else
+int mali_gpu_vol     =               1100000;        /* 1.10V */
+#endif
+
+#if MALI_DVFS_ENABLED
+#define MALI_DVFS_DEFAULT_STEP 0 // 134Mhz default
+#endif
+
+int  gpu_power_state;
+static int bPoweroff;
+
+#ifdef CONFIG_REGULATOR
+struct regulator {
+	struct device *dev;
+	struct list_head list;
+	int uA_load;
+	int min_uV;
+	int max_uV;
+	char *supply_name;
+	struct device_attribute dev_attr;
+	struct regulator_dev *rdev;
+};
+
+struct regulator *g3d_regulator=NULL;
+#endif
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
+extern struct platform_device s5pv310_device_pd[];
+#else
+extern struct platform_device exynos4_device_pd[];
+#endif
+#endif
+
+mali_io_address clk_register_map=0;
+
+#if MALI_GPU_BOTTOM_LOCK
+_mali_osk_lock_t *mali_dvfs_lock;
+#else
+static _mali_osk_lock_t *mali_dvfs_lock;
+#endif
+
+#ifdef CONFIG_REGULATOR
+int mali_regulator_get_usecount(void)
+{
+	struct regulator_dev *rdev;
+
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_get_usecount : g3d_regulator is null\n"));
+		return 0;
+	}
+	rdev = g3d_regulator->rdev;
+	return rdev->use_count;
+}
+
+void mali_regulator_disable(void)
+{
+	bPoweroff = 1;
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_disable : g3d_regulator is null\n"));
+		return;
+	}
+	regulator_disable(g3d_regulator);
+	MALI_DEBUG_PRINT(1, ("regulator_disable -> use cnt: %d \n",mali_regulator_get_usecount()));
+}
+
+void mali_regulator_enable(void)
+{
+	bPoweroff = 0;
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_enable : g3d_regulator is null\n"));
+		return;
+	}
+	regulator_enable(g3d_regulator);
+	MALI_DEBUG_PRINT(1, ("regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount()));
+}
+
+void mali_regulator_set_voltage(int min_uV, int max_uV)
+{
+	int voltage;
+
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_set_voltage : g3d_regulator is null\n"));
+		return;
+	}
+	MALI_DEBUG_PRINT(2, ("= regulator_set_voltage: %d, %d \n",min_uV, max_uV));
+	
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
+                               min_uV, max_uV, 0, 0, 0);
+#endif
+
+	regulator_set_voltage(g3d_regulator,min_uV,max_uV);
+	voltage = regulator_get_voltage(g3d_regulator);
+	
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
+                               voltage, 0, 1, 0, 0);
+#endif
+	mali_gpu_vol = voltage;
+	MALI_DEBUG_PRINT(1, ("= regulator_get_voltage: %d \n",mali_gpu_vol));
+
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+}
+#endif  
+
+unsigned long mali_clk_get_rate(void)
+{
+	return clk_get_rate(mali_clock);
+}
+
+mali_bool mali_clk_get(mali_bool bis_vpll)
+{
+	if (bis_vpll == MALI_TRUE)
+	{
+		if (ext_xtal_clock == NULL)
+		{
+			ext_xtal_clock = clk_get(NULL,EXTXTALCLK_NAME);
+			if (IS_ERR(ext_xtal_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source ext_xtal_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (vpll_src_clock == NULL)
+		{
+			vpll_src_clock = clk_get(NULL,VPLLSRCCLK_NAME);
+			if (IS_ERR(vpll_src_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source vpll_src_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (fout_vpll_clock == NULL)
+		{
+			fout_vpll_clock = clk_get(NULL,FOUTVPLLCLK_NAME);
+			if (IS_ERR(fout_vpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source fout_vpll_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (sclk_vpll_clock == NULL)
+		{
+			sclk_vpll_clock = clk_get(NULL,SCLVPLLCLK_NAME);
+			if (IS_ERR(sclk_vpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source sclk_vpll_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (mali_parent_clock == NULL)
+		{
+			mali_parent_clock = clk_get(NULL, GPUMOUT1CLK_NAME);
+		
+			if (IS_ERR(mali_parent_clock)) {
+				MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n"));
+				return MALI_FALSE;
+			}
+		}
+	}
+	else // mpll
+	{
+		if (mpll_clock == NULL)
+		{
+			mpll_clock = clk_get(NULL,MPLLCLK_NAME);
+
+			if (IS_ERR(mpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source mpll clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (mali_parent_clock == NULL)
+		{
+			mali_parent_clock = clk_get(NULL, GPUMOUT0CLK_NAME);
+		
+			if (IS_ERR(mali_parent_clock)) {
+				MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n"));
+				return MALI_FALSE;
+			}
+		}
+	}
+
+	// mali clock get always.
+	if (mali_clock == NULL)
+	{
+		mali_clock = clk_get(NULL, GPUCLK_NAME);
+
+		if (IS_ERR(mali_clock)) {
+			MALI_PRINT( ("MALI Error : failed to get source mali clock\n"));
+			return MALI_FALSE;
+		}
+	}
+
+	return MALI_TRUE;
+}
+
+void mali_clk_put(mali_bool binc_mali_clock)
+{
+	if (mali_parent_clock)
+	{
+		clk_put(mali_parent_clock);
+		mali_parent_clock = 0;
+	}
+	
+	if (mpll_clock)
+	{
+		clk_put(mpll_clock);
+		mpll_clock = 0;
+	}
+
+	if (sclk_vpll_clock)
+	{
+		clk_put(sclk_vpll_clock);
+		sclk_vpll_clock = 0;
+	}
+
+	if (fout_vpll_clock)
+	{
+		clk_put(fout_vpll_clock);
+		fout_vpll_clock = 0;
+	}
+
+	if (vpll_src_clock)
+	{
+		clk_put(vpll_src_clock);
+		vpll_src_clock = 0;
+	}
+	
+	if (ext_xtal_clock)
+	{
+		clk_put(ext_xtal_clock);
+		ext_xtal_clock = 0;
+	}
+
+	if (binc_mali_clock == MALI_TRUE && mali_clock)
+	{
+		clk_put(mali_clock);
+		mali_clock = 0;
+	}
+
+}
+
+
+mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
+{ 
+	unsigned long rate = 0;
+	mali_bool bis_vpll = MALI_FALSE;
+
+#ifdef CONFIG_VPLL_USE_FOR_TVENC
+	bis_vpll = MALI_TRUE;
+#endif
+
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (mali_clk_get(bis_vpll) == MALI_FALSE)
+		return MALI_FALSE;
+	
+	rate = (unsigned long)clk * (unsigned long)mhz;
+	MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz ));
+
+	if (bis_vpll)
+	{
+		clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ);
+		clk_set_parent(vpll_src_clock, ext_xtal_clock);
+		clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
+
+		clk_set_parent(mali_parent_clock, sclk_vpll_clock);
+		clk_set_parent(mali_clock, mali_parent_clock);
+	}
+	else
+	{
+		clk_set_parent(mali_parent_clock, mpll_clock);
+		clk_set_parent(mali_clock, mali_parent_clock);
+	}
+
+	if (clk_enable(mali_clock) < 0)
+		return MALI_FALSE;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
+                               rate, 0, 0, 0, 0);
+#endif
+
+	clk_set_rate(mali_clock, rate);
+	rate = clk_get_rate(mali_clock);
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
+                               rate, 0, 0, 0, 0);
+#endif
+
+	if (bis_vpll)
+		mali_gpu_clk = (int)(rate / mhz);
+	else
+		mali_gpu_clk = (int)((rate + 500000) / mhz);
+
+	GPU_MHZ = mhz;
+	MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk));
+
+	mali_clk_put(MALI_FALSE);
+
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+	
+	return MALI_TRUE;
+}
+
+static mali_bool init_mali_clock(void)
+{
+	mali_bool ret = MALI_TRUE;
+	
+	gpu_power_state = 0;
+
+	if (mali_clock != 0)
+		return ret; // already initialized
+
+	mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE
+			| _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0);
+	if (mali_dvfs_lock == NULL)
+		return _MALI_OSK_ERR_FAULT;
+
+	if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE)
+	{
+		ret = MALI_FALSE;
+		goto err_clock_get;
+	}
+
+	MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock));
+
+
+#ifdef CONFIG_REGULATOR
+#if USING_MALI_PMM
+	g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d");
+#else
+	g3d_regulator = regulator_get(NULL, "vdd_g3d");
+#endif
+
+	if (IS_ERR(g3d_regulator)) 
+	{
+		MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n"));
+		ret = MALI_FALSE;
+		goto err_regulator;
+	}
+
+	regulator_enable(g3d_regulator);
+	MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount()));
+	mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol);
+#endif
+
+	MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n"));
+	
+
+	MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__));
+	MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock  - normal\n", __FUNCTION__));
+
+	mali_clk_put(MALI_FALSE);
+
+	return MALI_TRUE;
+
+
+#ifdef CONFIG_REGULATOR
+err_regulator:
+	regulator_put(g3d_regulator);
+#endif
+	
+err_clock_get:
+	mali_clk_put(MALI_TRUE);
+
+	return ret;
+}
+
+static mali_bool deinit_mali_clock(void)
+{
+	if (mali_clock == 0)
+		return MALI_TRUE;
+
+#ifdef CONFIG_REGULATOR
+	if (g3d_regulator) 
+	{
+		regulator_put(g3d_regulator);
+		g3d_regulator=NULL;
+	}
+#endif
+
+	mali_clk_put(MALI_TRUE);
+
+	return MALI_TRUE;
+}
+
+
+static _mali_osk_errcode_t enable_mali_clocks(void)
+{
+	int err;
+	err = clk_enable(mali_clock);
+	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));
+
+	// set clock rate
+	mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
+	
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t disable_mali_clocks(void)
+{
+	clk_disable(mali_clock);
+	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));
+	
+	MALI_SUCCESS;
+}
+
+void set_mali_parent_power_domain(struct platform_device* dev)
+{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
+	dev->dev.parent = &s5pv310_device_pd[PD_G3D].dev;
+#else
+	dev->dev.parent = &exynos4_device_pd[PD_G3D].dev;
+#endif
+
+#endif
+}
+
+_mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
+{
+	if (bpower_on)
+	{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		MALI_DEBUG_PRINT(3,("_mali_osk_pmm_dev_activate \n"));
+		_mali_osk_pmm_dev_activate();
+#else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		void __iomem *status;
+		u32 timeout;
+		__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_G3D_CONF);
+                status = S5P_PMU_G3D_CONF + 0x4;
+
+		timeout = 10;
+		while ((__raw_readl(status) & S5P_INT_LOCAL_PWR_EN)
+			!= S5P_INT_LOCAL_PWR_EN) {
+			if (timeout == 0) {
+				MALI_PRINTF(("Power domain  enable failed.\n"));
+				return -ETIMEDOUT;
+			}
+			timeout--;
+			_mali_osk_time_ubusydelay(100);
+        }
+#endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	}
+	else
+	{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		MALI_DEBUG_PRINT( 4,("_mali_osk_pmm_dev_idle\n"));
+		_mali_osk_pmm_dev_idle();
+
+#else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		void __iomem *status;
+		u32 timeout;
+		__raw_writel(0, S5P_PMU_G3D_CONF);
+		
+		status = S5P_PMU_G3D_CONF + 0x4;
+		/* Wait max 1ms */
+		timeout = 10;
+		while (__raw_readl(status) & S5P_INT_LOCAL_PWR_EN) 
+		{
+			if (timeout == 0) {
+				MALI_PRINTF(("Power domain  disable failed.\n" ));
+        	                	return -ETIMEDOUT;
+			}
+			timeout--;
+			_mali_osk_time_ubusydelay( 100);
+		}
+#endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	}
+
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_init()
+{
+	MALI_CHECK(init_mali_clock(), _MALI_OSK_ERR_FAULT);
+#if MALI_DVFS_ENABLED
+	if (!clk_register_map) clk_register_map = _mali_osk_mem_mapioregion( CLK_DIV_STAT_G3D, 0x20, CLK_DESC );
+	if(!init_mali_dvfs_status(MALI_DVFS_DEFAULT_STEP))
+		MALI_DEBUG_PRINT(1, ("mali_platform_init failed\n"));        
+#endif
+
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_deinit()
+{
+	deinit_mali_clock();
+
+#if MALI_DVFS_ENABLED
+	deinit_mali_dvfs_status();
+	if (clk_register_map )
+	{
+		_mali_osk_mem_unmapioregion(CLK_DIV_STAT_G3D, 0x20, clk_register_map);
+		clk_register_map=0;
+	}
+#endif
+
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_powerdown(u32 cores)
+{
+	MALI_DEBUG_PRINT(3,("power down is called in mali_platform_powerdown state %x core %x \n", gpu_power_state, cores));
+
+	if (gpu_power_state != 0) // power down after state is 0
+	{
+		gpu_power_state = gpu_power_state & (~cores);
+		if (gpu_power_state == 0)
+		{
+			MALI_DEBUG_PRINT( 3,("disable clock\n"));
+			disable_mali_clocks();			
+		}
+	}
+	else
+	{
+		MALI_PRINT(("mali_platform_powerdown gpu_power_state == 0 and cores %x \n", cores));
+	}
+
+	bPoweroff=1;
+
+
+
+    MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_powerup(u32 cores)
+{
+	MALI_DEBUG_PRINT(3,("power up is called in mali_platform_powerup state %x core %x \n", gpu_power_state, cores));
+
+	if (gpu_power_state == 0) // power up only before state is 0
+	{
+		gpu_power_state = gpu_power_state | cores;
+
+		if (gpu_power_state != 0)
+		{
+			MALI_DEBUG_PRINT(4,("enable clock \n"));
+			enable_mali_clocks();
+		}
+	}
+	else
+	{
+		gpu_power_state = gpu_power_state | cores;
+	}
+	
+  	bPoweroff=0;
+
+
+	MALI_SUCCESS;
+}
+
+void mali_gpu_utilization_handler(u32 utilization)
+{
+	if (bPoweroff==0) 
+	{
+#if MALI_DVFS_ENABLED
+		if(!mali_dvfs_handler(utilization))
+			MALI_DEBUG_PRINT(1,( "error on mali dvfs status in utilization\n"));
+#endif
+	}
+}
+
+#if MALI_POWER_MGMT_TEST_SUITE
+u32 pmu_get_power_up_down_info(void)
+{
+	return 4095;
+}
+
+#endif
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
+{
+    MALI_SUCCESS;
+}
+
diff --git a/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform_dvfs.c b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform_dvfs.c
new file mode 100644
index 0000000..9e6edba
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/orion-m400/mali_platform_dvfs.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform_dvfs.c
+ * Platform specific Mali driver dvfs functions
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+
+#include <asm/io.h>
+
+#ifdef CONFIG_CPU_FREQ
+#include <mach/asv.h>
+#include <mach/regs-pmu.h>
+#define EXYNOS4_ASV_ENABLED
+#endif
+
+#include "mali_device_pause_resume.h"
+#include <linux/workqueue.h>
+
+#define MALI_DVFS_WATING 10 // msec
+
+static int bMaliDvfsRun=0;
+
+#if MALI_GPU_BOTTOM_LOCK
+static _mali_osk_atomic_t bottomlock_status;
+#endif
+
+typedef struct mali_dvfs_tableTag{
+	unsigned int clock;
+	unsigned int freq;
+	unsigned int vol;
+}mali_dvfs_table;
+
+typedef struct mali_dvfs_statusTag{
+	unsigned int currentStep;
+	mali_dvfs_table * pCurrentDvfs;
+
+}mali_dvfs_currentstatus;
+
+typedef struct mali_dvfs_thresholdTag{
+	unsigned int downthreshold;
+	unsigned int upthreshold;
+}mali_dvfs_threshold_table;
+
+typedef struct mali_dvfs_staycount{
+	unsigned int staycount;
+}mali_dvfs_staycount_table;
+
+mali_dvfs_staycount_table mali_dvfs_staycount[MALI_DVFS_STEPS]={
+	/*step 0*/{1},
+	/*step 1*/{1},};
+
+/*dvfs threshold*/
+mali_dvfs_threshold_table mali_dvfs_threshold[MALI_DVFS_STEPS]={
+	/*step 0*/{((int)((255*0)/100)), ((int)((255*85)/100))},
+	/*step 1*/{((int)((255*75)/100)), ((int)((255*100)/100))} };
+
+/*dvfs status*/
+mali_dvfs_currentstatus maliDvfsStatus;
+int mali_dvfs_control=0;
+
+/*dvfs table*/
+mali_dvfs_table mali_dvfs[MALI_DVFS_STEPS]={
+	/*step 0*/{160  ,1000000    , 950000},
+	/*step 1*/{267  ,1000000    ,1000000} };
+
+#ifdef EXYNOS4_ASV_ENABLED
+
+#define ASV_8_LEVEL	8
+#define ASV_5_LEVEL	5
+
+static unsigned int asv_3d_volt_5_table[ASV_5_LEVEL][MALI_DVFS_STEPS] = {
+	/* L3(160MHz), L2(266MHz) */
+	{1000000, 1100000},	/* S */
+	{1000000, 1100000},	/* A */
+	{ 950000, 1000000},	/* B */
+	{ 950000, 1000000},	/* C */
+	{ 950000,  950000},	/* D */
+};
+
+static unsigned int asv_3d_volt_8_table[ASV_8_LEVEL][MALI_DVFS_STEPS] = {
+	/* L3(160MHz), L2(266MHz)) */
+	{1000000, 1100000},	/* SS */
+	{1000000, 1100000},	/* A1 */
+	{1000000, 1100000},	/* A2 */
+	{ 950000, 1000000},	/* B1 */
+	{ 950000, 1000000},	/* B2 */
+	{ 950000, 1000000},	/* C1 */
+	{ 950000, 1000000},	/* C2 */
+	{ 950000,  950000},	/* D1 */
+};
+#endif
+
+static u32 mali_dvfs_utilization = 255;
+
+static void mali_dvfs_work_handler(struct work_struct *w);
+
+static struct workqueue_struct *mali_dvfs_wq = 0;
+extern mali_io_address clk_register_map;
+
+#if MALI_GPU_BOTTOM_LOCK
+extern _mali_osk_lock_t *mali_dvfs_lock;
+#endif
+
+static DECLARE_WORK(mali_dvfs_work, mali_dvfs_work_handler);
+
+static unsigned int get_mali_dvfs_status(void)
+{
+	return maliDvfsStatus.currentStep;
+}
+
+#if MALI_GPU_BOTTOM_LOCK
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+int get_mali_dvfs_control_status(void)
+{
+	return mali_dvfs_control;
+}
+
+mali_bool set_mali_dvfs_current_step(unsigned int step)
+{
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+	maliDvfsStatus.currentStep = step;
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+	return MALI_TRUE;
+}
+#endif
+#endif
+
+static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
+{
+	u32 validatedStep=step;
+
+#ifdef CONFIG_REGULATOR
+	if (mali_regulator_get_usecount()==0) {
+		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
+		return MALI_FALSE;
+	}
+#endif
+
+	if (boostup) {
+#ifdef CONFIG_REGULATOR
+		/*change the voltage*/
+		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
+#endif
+		/*change the clock*/
+		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+	} else {
+		/*change the clock*/
+		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+#ifdef CONFIG_REGULATOR
+		/*change the voltage*/
+		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
+#endif
+	}
+
+	maliDvfsStatus.currentStep = validatedStep;
+	/*for future use*/
+	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];
+
+	return MALI_TRUE;
+}
+
+static void mali_platform_wating(u32 msec)
+{
+	/*sample wating
+	change this in the future with proper check routine.
+	*/
+	unsigned int read_val;
+	while(1) {
+		read_val = _mali_osk_mem_ioread32(clk_register_map, 0x00);
+		if ((read_val & 0x8000)==0x0000) break;
+
+		_mali_osk_time_ubusydelay(100); // 1000 -> 100 : 20101218
+	}
+	/* _mali_osk_time_ubusydelay(msec*1000);*/
+}
+
+static mali_bool change_mali_dvfs_status(u32 step, mali_bool boostup )
+{
+
+	MALI_DEBUG_PRINT(1, ("> change_mali_dvfs_status: %d, %d \n",step, boostup));
+
+	if (!set_mali_dvfs_status(step, boostup)) {
+		MALI_DEBUG_PRINT(1, ("error on set_mali_dvfs_status: %d, %d \n",step, boostup));
+		return MALI_FALSE;
+	}
+
+	/*wait until clock and voltage is stablized*/
+	mali_platform_wating(MALI_DVFS_WATING); /*msec*/
+
+	return MALI_TRUE;
+}
+
+static unsigned int decideNextStatus(unsigned int utilization)
+{
+	unsigned int level=0; // 0:stay, 1:up
+
+	if (!mali_dvfs_control) {
+#if MALI_GPU_BOTTOM_LOCK
+		if (_mali_osk_atomic_read(&bottomlock_status) > 0)
+			level = 1;	/* or bigger */
+		else if (utilization > mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold)
+#else
+		if (utilization > mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold)
+#endif
+			level=1;
+		else if (utilization < mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold)
+			level=0;
+		else
+			level = maliDvfsStatus.currentStep;
+	} else	{
+		if ((mali_dvfs_control > 0) && (mali_dvfs_control < mali_dvfs[1].clock))
+			level=0;
+		else
+			level=1;
+	}
+
+	return level;
+}
+
+#ifdef EXYNOS4_ASV_ENABLED
+static mali_bool mali_dvfs_table_update(void)
+{
+	unsigned int exynos_result_of_asv_group;
+	unsigned int target_asv;
+	unsigned int i;
+	exynos_result_of_asv_group = exynos_result_of_asv & 0xf;
+	target_asv = exynos_result_of_asv >> 28;
+	MALI_PRINT(("exynos_result_of_asv_group = 0x%x, target_asv = 0x%x\n", exynos_result_of_asv_group, target_asv));
+
+	if (target_asv == 0x8) { //SUPPORT_1400MHZ
+		for (i = 0; i < MALI_DVFS_STEPS; i++) {
+			mali_dvfs[i].vol = asv_3d_volt_5_table[exynos_result_of_asv_group][i];
+			MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
+		}
+	} else if (target_asv == 0x4){ //SUPPORT_1200MHZ
+		for (i = 0; i < MALI_DVFS_STEPS; i++) {
+			mali_dvfs[i].vol = asv_3d_volt_8_table[exynos_result_of_asv_group][i];
+			MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
+		}
+	}
+
+	return MALI_TRUE;
+
+}
+#endif
+
+static mali_bool mali_dvfs_status(u32 utilization)
+{
+	unsigned int nextStatus = 0;
+	unsigned int curStatus = 0;
+	mali_bool boostup = MALI_FALSE;
+#ifdef EXYNOS4_ASV_ENABLED
+	static mali_bool asv_applied = MALI_FALSE;
+#endif
+	static int stay_count = 0; // to prevent frequent switch
+
+	MALI_DEBUG_PRINT(1, ("> mali_dvfs_status: %d \n",utilization));
+#ifdef EXYNOS4_ASV_ENABLED
+	if (asv_applied == MALI_FALSE) {
+		mali_dvfs_table_update();
+		change_mali_dvfs_status(0,0);
+		asv_applied = MALI_TRUE;
+
+		return MALI_TRUE;
+	}
+#endif
+
+	/*decide next step*/
+	curStatus = get_mali_dvfs_status();
+	nextStatus = decideNextStatus(utilization);
+
+	MALI_DEBUG_PRINT(1, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d \n", curStatus, nextStatus, maliDvfsStatus.currentStep));
+
+	/*if next status is same with current status, don't change anything*/
+	if ((curStatus!=nextStatus && stay_count==0)) {
+		/*check if boost up or not*/
+		if (nextStatus > maliDvfsStatus.currentStep)
+			boostup = 1;
+
+		/*change mali dvfs status*/
+		if (!change_mali_dvfs_status(nextStatus,boostup)) {
+			MALI_DEBUG_PRINT(1, ("error on change_mali_dvfs_status \n"));
+			return MALI_FALSE;
+		}
+		stay_count = mali_dvfs_staycount[maliDvfsStatus.currentStep].staycount;
+	} else {
+		if (stay_count>0)
+			stay_count--;
+	}
+
+	return MALI_TRUE;
+}
+
+
+
+int mali_dvfs_is_running(void)
+{
+	return bMaliDvfsRun;
+}
+
+
+
+void mali_dvfs_late_resume(void)
+{
+	// set the init clock as low when resume
+	set_mali_dvfs_status(0,0);
+}
+
+
+static void mali_dvfs_work_handler(struct work_struct *w)
+{
+	bMaliDvfsRun=1;
+
+	MALI_DEBUG_PRINT(3, ("=== mali_dvfs_work_handler\n"));
+
+	if (!mali_dvfs_status(mali_dvfs_utilization))
+		MALI_DEBUG_PRINT(1,( "error on mali dvfs status in mali_dvfs_work_handler"));
+
+	bMaliDvfsRun=0;
+}
+
+
+mali_bool init_mali_dvfs_status(int step)
+{
+	/*default status
+	add here with the right function to get initilization value.
+	*/
+	if (!mali_dvfs_wq)
+		mali_dvfs_wq = create_singlethread_workqueue("mali_dvfs");
+
+#if MALI_GPU_BOTTOM_LOCK
+	_mali_osk_atomic_init(&bottomlock_status, 0);
+#endif
+
+	/*add a error handling here*/
+	maliDvfsStatus.currentStep = step;
+
+	return MALI_TRUE;
+}
+
+void deinit_mali_dvfs_status(void)
+{
+#if MALI_GPU_BOTTOM_LOCK
+	_mali_osk_atomic_term(&bottomlock_status);
+#endif
+
+	if (mali_dvfs_wq)
+		destroy_workqueue(mali_dvfs_wq);
+	mali_dvfs_wq = NULL;
+}
+
+mali_bool mali_dvfs_handler(u32 utilization)
+{
+	mali_dvfs_utilization = utilization;
+	queue_work_on(0, mali_dvfs_wq,&mali_dvfs_work);
+
+	/*add error handle here*/
+	return MALI_TRUE;
+}
+
+void mali_default_step_set(int step, mali_bool boostup)
+{
+	mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+
+	if (maliDvfsStatus.currentStep == 1)
+		set_mali_dvfs_status(step, boostup);
+}
+
+#if MALI_GPU_BOTTOM_LOCK
+int mali_dvfs_bottom_lock_push(void)
+{
+	int prev_status = _mali_osk_atomic_read(&bottomlock_status);
+
+	if (prev_status < 0) {
+		MALI_PRINT(("gpu bottom lock status is not valid for push"));
+		return -1;
+	}
+
+	if (prev_status == 0) {
+		mali_regulator_set_voltage(mali_dvfs[1].vol, mali_dvfs[1].vol);
+		mali_clk_set_rate(mali_dvfs[1].clock, mali_dvfs[1].freq);
+		set_mali_dvfs_current_step(1);
+	}
+
+	return _mali_osk_atomic_inc_return(&bottomlock_status);
+}
+
+int mali_dvfs_bottom_lock_pop(void)
+{
+	if (_mali_osk_atomic_read(&bottomlock_status) <= 0) {
+		MALI_PRINT(("gpu bottom lock status is not valid for pop"));
+		return -1;
+	}
+
+	return _mali_osk_atomic_dec_return(&bottomlock_status);
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c
new file mode 100644
index 0000000..397ba942
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c
@@ -0,0 +1,756 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform.c
+ * Platform specific Mali driver functions for a default platform
+ */
+#include <linux/version.h>
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+#include "mali_linux_pm.h"
+
+#if USING_MALI_PMM
+#include "mali_pmm.h"
+#endif
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#include <plat/pd.h>
+#endif
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+#include "mali_kernel_profiling.h"
+#endif
+
+#include <asm/io.h>
+#include <mach/regs-pmu.h>
+
+#define EXTXTALCLK_NAME 	"ext_xtal"
+#define VPLLSRCCLK_NAME 	"vpll_src"
+#define FOUTVPLLCLK_NAME	"fout_vpll"
+#define SCLVPLLCLK_NAME 	"sclk_vpll"
+#define GPUMOUT1CLK_NAME	"mout_g3d1"
+
+#define MPLLCLK_NAME 		"mout_mpll"
+#define GPUMOUT0CLK_NAME 	"mout_g3d0"
+#define GPUCLK_NAME 		"sclk_g3d"
+#define CLK_DIV_STAT_G3D 	0x1003C62C
+#define CLK_DESC 			"clk-divider-status"
+
+#define MALI_BOTTOMLOCK_VOL	900000
+
+typedef struct mali_runtime_resumeTag{
+	int clk;
+	int vol;
+}mali_runtime_resume_table;
+
+mali_runtime_resume_table mali_runtime_resume = {266, 900000};
+
+/* lock/unlock CPU freq by Mali */
+extern int cpufreq_lock_by_mali(unsigned int freq);
+extern void cpufreq_unlock_by_mali(void);
+
+static struct clk  *ext_xtal_clock = 0;
+static struct clk  *vpll_src_clock = 0;
+static struct clk  *fout_vpll_clock = 0;
+static struct clk  *sclk_vpll_clock = 0;
+
+static struct clk  *mpll_clock = 0;
+static struct clk  *mali_parent_clock = 0;
+static struct clk  *mali_clock = 0;
+
+
+static unsigned int GPU_MHZ	= 1000000;
+
+int mali_gpu_clk = 266;
+int mali_gpu_vol = 900000;
+
+#if MALI_DVFS_ENABLED
+#define MALI_DVFS_DEFAULT_STEP 0
+#endif
+#if MALI_VOLTAGE_LOCK
+int mali_lock_vol = 0;
+static _mali_osk_atomic_t voltage_lock_status;
+static mali_bool mali_vol_lock_flag = 0;
+#endif
+
+int  gpu_power_state;
+static int bPoweroff;
+
+#ifdef CONFIG_REGULATOR
+struct regulator {
+	struct device *dev;
+	struct list_head list;
+	int uA_load;
+	int min_uV;
+	int max_uV;
+	char *supply_name;
+	struct device_attribute dev_attr;
+	struct regulator_dev *rdev;
+};
+
+struct regulator *g3d_regulator=NULL;
+#endif
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
+extern struct platform_device s5pv310_device_pd[];
+#else
+extern struct platform_device exynos4_device_pd[];
+#endif
+#endif
+
+mali_io_address clk_register_map=0;
+
+_mali_osk_lock_t *mali_dvfs_lock = 0;
+
+#ifdef CONFIG_REGULATOR
+int mali_regulator_get_usecount(void)
+{
+	struct regulator_dev *rdev;
+
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_get_usecount : g3d_regulator is null\n"));
+		return 0;
+	}
+	rdev = g3d_regulator->rdev;
+	return rdev->use_count;
+}
+
+void mali_regulator_disable(void)
+{
+	bPoweroff = 1;
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_disable : g3d_regulator is null\n"));
+		return;
+	}
+	regulator_disable(g3d_regulator);
+	MALI_DEBUG_PRINT(1, ("regulator_disable -> use cnt: %d \n",mali_regulator_get_usecount()));
+}
+
+void mali_regulator_enable(void)
+{
+	bPoweroff = 0;
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_enable : g3d_regulator is null\n"));
+		return;
+	}
+	regulator_enable(g3d_regulator);
+	MALI_DEBUG_PRINT(1, ("regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount()));
+}
+
+void mali_regulator_set_voltage(int min_uV, int max_uV)
+{
+	int voltage;
+#if !MALI_DVFS_ENABLED
+	min_uV = mali_gpu_vol;
+	max_uV = mali_gpu_vol;
+#endif
+#if MALI_VOLTAGE_LOCK
+	if (mali_vol_lock_flag == MALI_FALSE) {
+		if (min_uV < MALI_BOTTOMLOCK_VOL || max_uV < MALI_BOTTOMLOCK_VOL) {
+			min_uV = MALI_BOTTOMLOCK_VOL;
+			max_uV = MALI_BOTTOMLOCK_VOL;
+		}
+	} else if (_mali_osk_atomic_read(&voltage_lock_status) > 0 ) {
+		if (min_uV < mali_lock_vol || max_uV < mali_lock_vol) {
+#if MALI_DVFS_ENABLED
+			int mali_vol_get;
+			mali_vol_get = mali_vol_get_from_table(mali_lock_vol);
+			if (mali_vol_get) {
+				min_uV = mali_vol_get;
+				max_uV = mali_vol_get;
+			}
+#else
+			min_uV = mali_lock_vol;
+			max_uV = mali_lock_vol;
+#endif
+		}
+	}
+#endif
+
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if( IS_ERR_OR_NULL(g3d_regulator) )
+	{
+		MALI_DEBUG_PRINT(1, ("error on mali_regulator_set_voltage : g3d_regulator is null\n"));
+		return;
+	}
+
+    MALI_DEBUG_PRINT(2, ("= regulator_set_voltage: %d, %d \n",min_uV, max_uV));
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
+                               min_uV, max_uV, 1, 0, 0);
+#endif
+
+    regulator_set_voltage(g3d_regulator,min_uV,max_uV);
+	voltage = regulator_get_voltage(g3d_regulator);
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS,
+                               voltage, 0, 2, 0, 0);
+#endif
+
+	mali_gpu_vol = voltage;
+	MALI_DEBUG_PRINT(1, ("= regulator_get_voltage: %d \n",mali_gpu_vol));
+
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+}
+#endif
+
+unsigned long mali_clk_get_rate(void)
+{
+	return clk_get_rate(mali_clock);
+}
+
+mali_bool mali_clk_get(mali_bool bis_vpll)
+{
+	if (bis_vpll == MALI_TRUE)
+	{
+		if (ext_xtal_clock == NULL)
+		{
+			ext_xtal_clock = clk_get(NULL,EXTXTALCLK_NAME);
+			if (IS_ERR(ext_xtal_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source ext_xtal_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (vpll_src_clock == NULL)
+		{
+			vpll_src_clock = clk_get(NULL,VPLLSRCCLK_NAME);
+			if (IS_ERR(vpll_src_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source vpll_src_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (fout_vpll_clock == NULL)
+		{
+			fout_vpll_clock = clk_get(NULL,FOUTVPLLCLK_NAME);
+			if (IS_ERR(fout_vpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source fout_vpll_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (sclk_vpll_clock == NULL)
+		{
+			sclk_vpll_clock = clk_get(NULL,SCLVPLLCLK_NAME);
+			if (IS_ERR(sclk_vpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source sclk_vpll_clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (mali_parent_clock == NULL)
+		{
+			mali_parent_clock = clk_get(NULL, GPUMOUT1CLK_NAME);
+
+			if (IS_ERR(mali_parent_clock)) {
+				MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n"));
+				return MALI_FALSE;
+			}
+		}
+	}
+	else // mpll
+	{
+		if (mpll_clock == NULL)
+		{
+			mpll_clock = clk_get(NULL,MPLLCLK_NAME);
+
+			if (IS_ERR(mpll_clock)) {
+				MALI_PRINT( ("MALI Error : failed to get source mpll clock\n"));
+				return MALI_FALSE;
+			}
+		}
+
+		if (mali_parent_clock == NULL)
+		{
+			mali_parent_clock = clk_get(NULL, GPUMOUT0CLK_NAME);
+
+			if (IS_ERR(mali_parent_clock)) {
+				MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n"));
+				return MALI_FALSE;
+			}
+		}
+	}
+
+	// mali clock get always.
+	if (mali_clock == NULL)
+	{
+		mali_clock = clk_get(NULL, GPUCLK_NAME);
+
+		if (IS_ERR(mali_clock)) {
+			MALI_PRINT( ("MALI Error : failed to get source mali clock\n"));
+			return MALI_FALSE;
+		}
+	}
+
+	return MALI_TRUE;
+}
+
+void mali_clk_put(mali_bool binc_mali_clock)
+{
+	if (mali_parent_clock)
+	{
+		clk_put(mali_parent_clock);
+		mali_parent_clock = 0;
+	}
+
+	if (mpll_clock)
+	{
+		clk_put(mpll_clock);
+		mpll_clock = 0;
+	}
+
+	if (sclk_vpll_clock)
+	{
+		clk_put(sclk_vpll_clock);
+		sclk_vpll_clock = 0;
+	}
+
+	if (fout_vpll_clock)
+	{
+		clk_put(fout_vpll_clock);
+		fout_vpll_clock = 0;
+	}
+
+	if (vpll_src_clock)
+	{
+		clk_put(vpll_src_clock);
+		vpll_src_clock = 0;
+	}
+
+	if (ext_xtal_clock)
+	{
+		clk_put(ext_xtal_clock);
+		ext_xtal_clock = 0;
+	}
+
+	if (binc_mali_clock == MALI_TRUE && mali_clock)
+	{
+		clk_put(mali_clock);
+		mali_clock = 0;
+	}
+
+}
+
+
+mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
+{
+	unsigned long rate = 0;
+	mali_bool bis_vpll = MALI_TRUE;
+
+#ifndef CONFIG_VPLL_USE_FOR_TVENC
+	bis_vpll = MALI_TRUE;
+#endif
+
+#if !MALI_DVFS_ENABLED
+	clk = mali_gpu_clk;
+#endif
+
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (mali_clk_get(bis_vpll) == MALI_FALSE)
+		return MALI_FALSE;
+
+	rate = (unsigned long)clk * (unsigned long)mhz;
+	MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz ));
+
+	if (bis_vpll)
+	{
+		clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ);
+		clk_set_parent(vpll_src_clock, ext_xtal_clock);
+		clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
+
+		clk_set_parent(mali_parent_clock, sclk_vpll_clock);
+		clk_set_parent(mali_clock, mali_parent_clock);
+	}
+	else
+	{
+		clk_set_parent(mali_parent_clock, mpll_clock);
+		clk_set_parent(mali_clock, mali_parent_clock);
+	}
+
+	if (clk_enable(mali_clock) < 0)
+		return MALI_FALSE;
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
+                               rate, 0, 0, 0, 0);
+#endif
+
+	clk_set_rate(mali_clock, rate);
+	rate = clk_get_rate(mali_clock);
+
+#if MALI_TIMELINE_PROFILING_ENABLED
+    _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
+                               MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
+                               MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
+                               rate, 1, 0, 0, 0);
+#endif
+
+	if (bis_vpll)
+		mali_gpu_clk = (int)(rate / mhz);
+	else
+		mali_gpu_clk = (int)((rate + 500000) / mhz);
+
+	GPU_MHZ = mhz;
+	MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk));
+
+	mali_clk_put(MALI_FALSE);
+
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+
+	return MALI_TRUE;
+}
+
+static mali_bool init_mali_clock(void)
+{
+	mali_bool ret = MALI_TRUE;
+
+	gpu_power_state = 0;
+
+	if (mali_clock != 0)
+		return ret; // already initialized
+
+	mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE
+			| _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0);
+	if (mali_dvfs_lock == NULL)
+		return _MALI_OSK_ERR_FAULT;
+
+	if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE)
+	{
+		ret = MALI_FALSE;
+		goto err_clock_get;
+	}
+
+	MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock));
+
+
+#ifdef CONFIG_REGULATOR
+#if USING_MALI_PMM
+	g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d");
+#else
+	g3d_regulator = regulator_get(NULL, "vdd_g3d");
+#endif
+
+	if (IS_ERR(g3d_regulator))
+	{
+		MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n"));
+		ret = MALI_FALSE;
+		goto err_regulator;
+	}
+
+	regulator_enable(g3d_regulator);
+
+	MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount()));
+	mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol);
+#endif
+
+	MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n"));
+
+
+	MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__));
+	MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock  - normal\n", __FUNCTION__));
+
+	mali_clk_put(MALI_FALSE);
+
+	return MALI_TRUE;
+
+
+#ifdef CONFIG_REGULATOR
+err_regulator:
+	regulator_put(g3d_regulator);
+#endif
+
+err_clock_get:
+	mali_clk_put(MALI_TRUE);
+
+	return ret;
+}
+
+static mali_bool deinit_mali_clock(void)
+{
+	if (mali_clock == 0)
+		return MALI_TRUE;
+
+#ifdef CONFIG_REGULATOR
+	if (g3d_regulator)
+	{
+		regulator_put(g3d_regulator);
+		g3d_regulator=NULL;
+	}
+#endif
+
+	mali_clk_put(MALI_TRUE);
+
+	return MALI_TRUE;
+}
+static _mali_osk_errcode_t enable_mali_clocks(void)
+{
+	int err;
+	err = clk_enable(mali_clock);
+	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));
+
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if MALI_DVFS_ENABLED
+	// set clock rate
+	if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk)
+		mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
+	else {
+		mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
+		mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
+	}
+	if (mali_gpu_clk <= mali_runtime_resume.clk)
+		set_mali_dvfs_current_step(5);
+	/* lock/unlock CPU freq by Mali */
+	if (mali_gpu_clk == 440)
+		err = cpufreq_lock_by_mali(1200);
+#else
+	mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
+	mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
+#endif
+#else
+	mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
+#endif
+	MALI_SUCCESS;
+}
+
+static _mali_osk_errcode_t disable_mali_clocks(void)
+{
+	clk_disable(mali_clock);
+	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));
+
+	/* lock/unlock CPU freq by Mali */
+	cpufreq_unlock_by_mali();
+	MALI_SUCCESS;
+}
+
+void set_mali_parent_power_domain(struct platform_device* dev)
+{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
+	dev->dev.parent = &s5pv310_device_pd[PD_G3D].dev;
+#else
+	dev->dev.parent = &exynos4_device_pd[PD_G3D].dev;
+#endif
+#endif
+}
+
+_mali_osk_errcode_t g3d_power_domain_control(int bpower_on)
+{
+	if (bpower_on)
+	{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		MALI_DEBUG_PRINT(3,("_mali_osk_pmm_dev_activate \n"));
+		_mali_osk_pmm_dev_activate();
+#else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		void __iomem *status;
+		u32 timeout;
+		__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_G3D_CONF);
+		status = S5P_PMU_G3D_CONF + 0x4;
+
+		timeout = 10;
+		while ((__raw_readl(status) & S5P_INT_LOCAL_PWR_EN)
+				!= S5P_INT_LOCAL_PWR_EN) {
+			if (timeout == 0) {
+				MALI_PRINTF(("Power domain  enable failed.\n"));
+				return -ETIMEDOUT;
+			}
+			timeout--;
+			_mali_osk_time_ubusydelay(100);
+		}
+#endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	}
+	else
+	{
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		MALI_DEBUG_PRINT( 4,("_mali_osk_pmm_dev_idle\n"));
+		_mali_osk_pmm_dev_idle();
+
+#else //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+		void __iomem *status;
+		u32 timeout;
+		__raw_writel(0, S5P_PMU_G3D_CONF);
+
+		status = S5P_PMU_G3D_CONF + 0x4;
+		/* Wait max 1ms */
+		timeout = 10;
+		while (__raw_readl(status) & S5P_INT_LOCAL_PWR_EN)
+		{
+			if (timeout == 0) {
+				MALI_PRINTF(("Power domain  disable failed.\n" ));
+				return -ETIMEDOUT;
+			}
+			timeout--;
+			_mali_osk_time_ubusydelay( 100);
+		}
+#endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON
+	}
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_init()
+{
+	MALI_CHECK(init_mali_clock(), _MALI_OSK_ERR_FAULT);
+#if MALI_VOLTAGE_LOCK
+	_mali_osk_atomic_init(&voltage_lock_status, 0);
+#endif
+#if MALI_DVFS_ENABLED
+	if (!clk_register_map) clk_register_map = _mali_osk_mem_mapioregion( CLK_DIV_STAT_G3D, 0x20, CLK_DESC );
+	if(!init_mali_dvfs_status(MALI_DVFS_DEFAULT_STEP))
+		MALI_DEBUG_PRINT(1, ("mali_platform_init failed\n"));
+#endif
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_deinit()
+{
+	deinit_mali_clock();
+#if MALI_VOLTAGE_LOCK
+	_mali_osk_atomic_term(&voltage_lock_status);
+#endif
+#if MALI_DVFS_ENABLED
+	deinit_mali_dvfs_status();
+	if (clk_register_map )
+	{
+		_mali_osk_mem_unmapioregion(CLK_DIV_STAT_G3D, 0x20, clk_register_map);
+		clk_register_map=0;
+	}
+#endif
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_powerdown(u32 cores)
+{
+	MALI_DEBUG_PRINT(3,("power down is called in mali_platform_powerdown state %x core %x \n", gpu_power_state, cores));
+
+	if (gpu_power_state != 0) // power down after state is 0
+	{
+		gpu_power_state = gpu_power_state & (~cores);
+		if (gpu_power_state == 0)
+		{
+			MALI_DEBUG_PRINT( 3,("disable clock\n"));
+			disable_mali_clocks();
+		}
+	}
+	else
+	{
+		MALI_PRINT(("mali_platform_powerdown gpu_power_state == 0 and cores %x \n", cores));
+	}
+
+	MALI_SUCCESS;
+}
+
+_mali_osk_errcode_t mali_platform_powerup(u32 cores)
+{
+	MALI_DEBUG_PRINT(3,("power up is called in mali_platform_powerup state %x core %x \n", gpu_power_state, cores));
+
+	if (gpu_power_state == 0) // power up only before state is 0
+	{
+		gpu_power_state = gpu_power_state | cores;
+
+		if (gpu_power_state != 0)
+		{
+			MALI_DEBUG_PRINT(4,("enable clock \n"));
+			enable_mali_clocks();
+		}
+	}
+	else
+	{
+		gpu_power_state = gpu_power_state | cores;
+	}
+
+	MALI_SUCCESS;
+}
+
+void mali_gpu_utilization_handler(u32 utilization)
+{
+	if (bPoweroff==0)
+	{
+#if MALI_DVFS_ENABLED
+		if(!mali_dvfs_handler(utilization))
+			MALI_DEBUG_PRINT(1,( "error on mali dvfs status in utilization\n"));
+#endif
+	}
+}
+
+#if MALI_POWER_MGMT_TEST_SUITE
+u32 pmu_get_power_up_down_info(void)
+{
+	return 4095;
+}
+
+#endif
+
+_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
+{
+    MALI_SUCCESS;
+}
+
+#if MALI_VOLTAGE_LOCK
+int mali_voltage_lock_push(int lock_vol)
+{
+	int prev_status = _mali_osk_atomic_read(&voltage_lock_status);
+
+	if (prev_status < 0) {
+		MALI_PRINT(("gpu voltage lock status is not valid for push\n"));
+		return -1;
+	}
+	if (prev_status == 0) {
+		mali_lock_vol = lock_vol;
+		if (mali_gpu_vol < mali_lock_vol)
+			mali_regulator_set_voltage(mali_lock_vol, mali_lock_vol);
+	} else {
+		MALI_PRINT(("gpu voltage lock status is already pushed, current lock voltage : %d\n", mali_lock_vol));
+		return -1;
+	}
+
+	return _mali_osk_atomic_inc_return(&voltage_lock_status);
+}
+
+int mali_voltage_lock_pop(void)
+{
+	if (_mali_osk_atomic_read(&voltage_lock_status) <= 0) {
+		MALI_PRINT(("gpu voltage lock status is not valid for pop\n"));
+		return -1;
+	}
+	return _mali_osk_atomic_dec_return(&voltage_lock_status);
+}
+
+int mali_voltage_lock_init(void)
+{
+	mali_vol_lock_flag = MALI_TRUE;
+
+	MALI_SUCCESS;
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c
new file mode 100644
index 0000000..8293d6e
--- /dev/null
+++ b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform_dvfs.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ *
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ *
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file mali_platform_dvfs.c
+ * Platform specific Mali driver dvfs functions
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_platform.h"
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+
+#include <asm/io.h>
+
+#include "mali_device_pause_resume.h"
+#include <linux/workqueue.h>
+
+#define MAX_MALI_DVFS_STEPS 4
+#define MALI_DVFS_WATING 10 // msec
+
+#ifdef CONFIG_CPU_FREQ
+#include <mach/asv.h>
+#define EXYNOS4_ASV_ENABLED
+#endif
+
+static int bMaliDvfsRun=0;
+
+static _mali_osk_atomic_t bottomlock_status;
+static int bottom_lock_step;
+
+typedef struct mali_dvfs_tableTag{
+	unsigned int clock;
+	unsigned int freq;
+	unsigned int vol;
+}mali_dvfs_table;
+
+typedef struct mali_dvfs_statusTag{
+	unsigned int currentStep;
+	mali_dvfs_table * pCurrentDvfs;
+
+}mali_dvfs_currentstatus;
+
+typedef struct mali_dvfs_thresholdTag{
+	unsigned int downthreshold;
+	unsigned int upthreshold;
+}mali_dvfs_threshold_table;
+
+typedef struct mali_dvfs_staycount{
+	unsigned int staycount;
+}mali_dvfs_staycount_table;
+
+typedef struct mali_dvfs_stepTag{
+	int clk;
+	int vol;
+}mali_dvfs_step;
+
+mali_dvfs_step step[MALI_DVFS_STEPS]={
+	/*step 0 clk*/ {160,   875000},
+#if (MALI_DVFS_STEPS > 1)
+	/*step 1 clk*/ {266,   900000},
+#if (MALI_DVFS_STEPS > 2)
+	/*step 2 clk*/ {350,   950000},
+#if (MALI_DVFS_STEPS > 3)
+	/*step 3 clk*/ {440,  1025000}
+#endif
+#endif
+#endif
+};
+
+mali_dvfs_staycount_table mali_dvfs_staycount[MALI_DVFS_STEPS]={
+	/*step 0*/{0},
+#if (MALI_DVFS_STEPS > 1)
+	/*step 1*/{0},
+#if (MALI_DVFS_STEPS > 2)
+	/*step 2*/{0},
+#if (MALI_DVFS_STEPS > 3)
+	/*step 3*/{0}
+#endif
+#endif
+#endif
+};
+
+/* dvfs information */
+// L0 = 440Mhz, 1.025V
+// L1 = 350Mhz, 0.95V
+// L2 = 266Mhz, 0.90V
+// L3 = 160Mhz, 0.875V
+
+int step0_clk = 160;
+int step0_vol = 875000;
+#if (MALI_DVFS_STEPS > 1)
+int step1_clk = 266;
+int step1_vol = 900000;
+int step0_up = 70;
+int step1_down = 62;
+#if (MALI_DVFS_STEPS > 2)
+int step2_clk = 350;
+int step2_vol = 950000;
+int step1_up = 90;
+int step2_down = 85;
+#if (MALI_DVFS_STEPS > 3)
+int step3_clk = 440;
+int step3_vol = 1025000;
+int step2_up = 90;
+int step3_down = 90;
+#endif
+#endif
+#endif
+
+mali_dvfs_table mali_dvfs_all[MAX_MALI_DVFS_STEPS]={
+	{160   ,1000000   ,  875000},
+	{266   ,1000000   ,  900000},
+	{350   ,1000000   ,  950000},
+	{440   ,1000000   , 1025000} };
+
+mali_dvfs_table mali_dvfs[MALI_DVFS_STEPS]={
+	{160   ,1000000   , 875000},
+#if (MALI_DVFS_STEPS > 1)
+	{266   ,1000000   , 900000},
+#if (MALI_DVFS_STEPS > 2)
+	{350   ,1000000   , 950000},
+#if (MALI_DVFS_STEPS > 3)
+	{440   ,1000000   ,1025000}
+#endif
+#endif
+#endif
+};
+
+mali_dvfs_threshold_table mali_dvfs_threshold[MALI_DVFS_STEPS]={
+	{0   , 70},
+#if (MALI_DVFS_STEPS > 1)
+	{62  , 90},
+#if (MALI_DVFS_STEPS > 2)
+	{85  , 90},
+#if (MALI_DVFS_STEPS > 3)
+	{90  ,100}
+#endif
+#endif
+#endif
+};
+
+#ifdef EXYNOS4_ASV_ENABLED
+#define ASV_LEVEL     12	/* ASV0, 1, 11 is reserved */
+
+static unsigned int asv_3d_volt_9_table[MALI_DVFS_STEPS][ASV_LEVEL] = {
+	{  950000,  925000,  900000,  900000,  875000,  875000,  875000,  875000,  850000,  850000,  850000,  850000},  /* L3(160Mhz) */
+#if (MALI_DVFS_STEPS > 1)
+	{  975000,  950000,  925000,  925000,  925000,  900000,  900000,  875000,  875000,  875000,  875000,  850000},	/* L2(266Mhz) */
+#if (MALI_DVFS_STEPS > 2)
+	{ 1050000, 1025000, 1000000, 1000000,  975000,  950000,  950000,  950000,  925000,  925000,  925000,  900000},	/* L1(350Mhz) */
+#if (MALI_DVFS_STEPS > 3)
+	{ 1100000, 1075000, 1050000, 1050000, 1050000, 1025000, 1025000, 1000000, 1000000, 1000000,  975000,  950000},	/* L0(440Mhz) */
+#endif
+#endif
+#endif
+};
+#endif
+
+/*dvfs status*/
+mali_dvfs_currentstatus maliDvfsStatus;
+int mali_dvfs_control=0;
+
+static u32 mali_dvfs_utilization = 255;
+
+static void mali_dvfs_work_handler(struct work_struct *w);
+
+static struct workqueue_struct *mali_dvfs_wq = 0;
+extern mali_io_address clk_register_map;
+extern _mali_osk_lock_t *mali_dvfs_lock;
+
+int mali_runtime_resumed = -1;
+
+static DECLARE_WORK(mali_dvfs_work, mali_dvfs_work_handler);
+
+/* lock/unlock CPU freq by Mali */
+#include <linux/types.h>
+#include <mach/cpufreq.h>
+
+atomic_t mali_cpufreq_lock;
+
+int cpufreq_lock_by_mali(unsigned int freq)
+{
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+/* #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_ARCH_EXYNOS4) */
+	unsigned int level;
+
+	if (atomic_read(&mali_cpufreq_lock) == 0) {
+		if (exynos_cpufreq_get_level(freq * 1000, &level)) {
+			printk(KERN_ERR
+				"Mali: failed to get cpufreq level for %dMHz",
+				freq);
+			return -EINVAL;
+		}
+
+		if (exynos_cpufreq_lock(DVFS_LOCK_ID_G3D, level)) {
+			printk(KERN_ERR
+				"Mali: failed to cpufreq lock for L%d", level);
+			return -EINVAL;
+		}
+
+		atomic_set(&mali_cpufreq_lock, 1);
+		printk(KERN_DEBUG "Mali: cpufreq locked on <%d>%dMHz\n", level,
+									freq);
+	}
+#endif
+	return 0;
+}
+
+void cpufreq_unlock_by_mali(void)
+{
+#ifdef CONFIG_EXYNOS4_CPUFREQ
+/* #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_ARCH_EXYNOS4) */
+	if (atomic_read(&mali_cpufreq_lock) == 1) {
+		exynos_cpufreq_lock_free(DVFS_LOCK_ID_G3D);
+		atomic_set(&mali_cpufreq_lock, 0);
+		printk(KERN_DEBUG "Mali: cpufreq locked off\n");
+	}
+#endif
+}
+
+static unsigned int get_mali_dvfs_status(void)
+{
+	return maliDvfsStatus.currentStep;
+}
+#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
+int get_mali_dvfs_control_status(void)
+{
+	return mali_dvfs_control;
+}
+
+mali_bool set_mali_dvfs_current_step(unsigned int step)
+{
+	_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+	maliDvfsStatus.currentStep = step % MAX_MALI_DVFS_STEPS;
+	if (step >= MAX_MALI_DVFS_STEPS)
+		mali_runtime_resumed = maliDvfsStatus.currentStep;
+	_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
+	return MALI_TRUE;
+}
+#endif
+static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
+{
+	u32 validatedStep=step;
+	int err;
+
+#ifdef CONFIG_REGULATOR
+	if (mali_regulator_get_usecount() == 0) {
+		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
+		return MALI_FALSE;
+	}
+#endif
+
+	if (boostup) {
+#ifdef CONFIG_REGULATOR
+		/*change the voltage*/
+		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
+#endif
+		/*change the clock*/
+		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+	} else {
+		/*change the clock*/
+		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+#ifdef CONFIG_REGULATOR
+		/*change the voltage*/
+		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
+#endif
+	}
+
+#ifdef EXYNOS4_ASV_ENABLED
+	if (mali_dvfs[step].clock == 160)
+		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
+	else
+		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
+#endif
+
+
+	set_mali_dvfs_current_step(validatedStep);
+	/*for future use*/
+	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];
+
+	/* lock/unlock CPU freq by Mali */
+	if (mali_dvfs[step].clock == 440)
+		err = cpufreq_lock_by_mali(1200);
+	else
+		cpufreq_unlock_by_mali();
+
+	return MALI_TRUE;
+}
+
+static void mali_platform_wating(u32 msec)
+{
+	/*sample wating
+	change this in the future with proper check routine.
+	*/
+	unsigned int read_val;
+	while(1) {
+		read_val = _mali_osk_mem_ioread32(clk_register_map, 0x00);
+		if ((read_val & 0x8000)==0x0000) break;
+			_mali_osk_time_ubusydelay(100); // 1000 -> 100 : 20101218
+		}
+		/* _mali_osk_time_ubusydelay(msec*1000);*/
+}
+
+static mali_bool change_mali_dvfs_status(u32 step, mali_bool boostup )
+{
+
+	MALI_DEBUG_PRINT(1, ("> change_mali_dvfs_status: %d, %d \n",step, boostup));
+
+	if (!set_mali_dvfs_status(step, boostup)) {
+		MALI_DEBUG_PRINT(1, ("error on set_mali_dvfs_status: %d, %d \n",step, boostup));
+		return MALI_FALSE;
+	}
+
+	/*wait until clock and voltage is stablized*/
+	mali_platform_wating(MALI_DVFS_WATING); /*msec*/
+
+	return MALI_TRUE;
+}
+
+#ifdef EXYNOS4_ASV_ENABLED
+extern unsigned int exynos_result_of_asv;
+
+static mali_bool mali_dvfs_table_update(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < MALI_DVFS_STEPS; i++) {
+		MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
+		mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
+		MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
+	}
+
+	return MALI_TRUE;
+}
+#endif
+
+static unsigned int decideNextStatus(unsigned int utilization)
+{
+	static unsigned int level = 0; // 0:stay, 1:up
+	static int mali_dvfs_clk = 0;
+
+	if (mali_runtime_resumed >= 0) {
+		level = mali_runtime_resumed;
+		mali_runtime_resumed = -1;
+		return level;
+	}
+
+	if (mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold
+			<= mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold) {
+		MALI_PRINT(("upthreadshold is smaller than downthreshold: %d < %d\n",
+				mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold,
+				mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold));
+		return level;
+	}
+
+	if (!mali_dvfs_control && level == maliDvfsStatus.currentStep) {
+		if (utilization > (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold / 100) &&
+				level < MALI_DVFS_STEPS - 1) {
+			level++;
+		}
+		if (utilization < (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold / 100) &&
+				level > 0) {
+			level--;
+		}
+	} else if (mali_dvfs_control == 999) {
+		int i = 0;
+		for (i = 0; i < MALI_DVFS_STEPS; i++) {
+			step[i].clk = mali_dvfs_all[i].clock;
+		}
+#ifdef EXYNOS4_ASV_ENABLED
+		mali_dvfs_table_update();
+#endif
+		i = 0;
+		for (i = 0; i < MALI_DVFS_STEPS; i++) {
+			mali_dvfs[i].clock = step[i].clk;
+		}
+		mali_dvfs_control = 0;
+		level = 0;
+
+		step0_clk = step[0].clk;
+		change_dvfs_tableset(step0_clk, 0);
+#if (MALI_DVFS_STEPS > 1)
+		step1_clk = step[1].clk;
+		change_dvfs_tableset(step1_clk, 1);
+#if (MALI_DVFS_STEPS > 2)
+		step2_clk = step[2].clk;
+		change_dvfs_tableset(step2_clk, 2);
+#if (MALI_DVFS_STEPS > 3)
+		step3_clk = step[3].clk;
+		change_dvfs_tableset(step3_clk, 3);
+#endif
+#endif
+#endif
+	} else if (mali_dvfs_control != mali_dvfs_clk && mali_dvfs_control != 999) {
+		if (mali_dvfs_control < mali_dvfs_all[1].clock && mali_dvfs_control > 0) {
+			int i = 0;
+			for (i = 0; i < MALI_DVFS_STEPS; i++) {
+				step[i].clk = mali_dvfs_all[0].clock;
+			}
+			maliDvfsStatus.currentStep = 0;
+		} else if (mali_dvfs_control < mali_dvfs_all[2].clock && mali_dvfs_control >= mali_dvfs_all[1].clock) {
+			int i = 0;
+			for (i = 0; i < MALI_DVFS_STEPS; i++) {
+				step[i].clk = mali_dvfs_all[1].clock;
+			}
+			maliDvfsStatus.currentStep = 1;
+		} else if (mali_dvfs_control < mali_dvfs_all[3].clock && mali_dvfs_control >= mali_dvfs_all[2].clock) {
+			int i = 0;
+			for (i = 0; i < MALI_DVFS_STEPS; i++) {
+				step[i].clk = mali_dvfs_all[2].clock;
+			}
+			maliDvfsStatus.currentStep = 2;
+		} else {
+			int i = 0;
+			for (i = 0; i < MALI_DVFS_STEPS; i++) {
+				step[i].clk  = mali_dvfs_all[3].clock;
+			}
+			maliDvfsStatus.currentStep = 3;
+		}
+		step0_clk = step[0].clk;
+		change_dvfs_tableset(step0_clk, 0);
+#if (MALI_DVFS_STEPS > 1)
+		step1_clk = step[1].clk;
+		change_dvfs_tableset(step1_clk, 1);
+#if (MALI_DVFS_STEPS > 2)
+		step2_clk = step[2].clk;
+		change_dvfs_tableset(step2_clk, 2);
+#if (MALI_DVFS_STEPS > 3)
+		step3_clk = step[3].clk;
+		change_dvfs_tableset(step3_clk, 3);
+#endif
+#endif
+#endif
+		level = maliDvfsStatus.currentStep;
+	}
+
+	mali_dvfs_clk = mali_dvfs_control;
+
+	if (_mali_osk_atomic_read(&bottomlock_status) > 0) {
+		if (level < bottom_lock_step)
+			level = bottom_lock_step;
+	}
+
+	return level;
+}
+
+static mali_bool mali_dvfs_status(u32 utilization)
+{
+	unsigned int nextStatus = 0;
+	unsigned int curStatus = 0;
+	mali_bool boostup = MALI_FALSE;
+	static int stay_count = 0;
+#ifdef EXYNOS4_ASV_ENABLED
+	static mali_bool asv_applied = MALI_FALSE;
+#endif
+
+	MALI_DEBUG_PRINT(1, ("> mali_dvfs_status: %d \n",utilization));
+#ifdef EXYNOS4_ASV_ENABLED
+	if (asv_applied == MALI_FALSE) {
+		mali_dvfs_table_update();
+		change_mali_dvfs_status(1, 0);
+		asv_applied = MALI_TRUE;
+
+		return MALI_TRUE;
+	}
+#endif
+
+	/*decide next step*/
+	curStatus = get_mali_dvfs_status();
+	nextStatus = decideNextStatus(utilization);
+
+	MALI_DEBUG_PRINT(1, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d \n", curStatus, nextStatus, maliDvfsStatus.currentStep));
+
+	/*if next status is same with current status, don't change anything*/
+	if ((curStatus != nextStatus && stay_count == 0)) {
+		/*check if boost up or not*/
+		if (nextStatus > maliDvfsStatus.currentStep) boostup = 1;
+
+		/*change mali dvfs status*/
+		if (!change_mali_dvfs_status(nextStatus,boostup)) {
+			MALI_DEBUG_PRINT(1, ("error on change_mali_dvfs_status \n"));
+			return MALI_FALSE;
+		}
+		stay_count = mali_dvfs_staycount[maliDvfsStatus.currentStep].staycount;
+	} else {
+		if (stay_count > 0)
+			stay_count--;
+	}
+
+	return MALI_TRUE;
+}
+
+
+
+int mali_dvfs_is_running(void)
+{
+	return bMaliDvfsRun;
+
+}
+
+
+
+void mali_dvfs_late_resume(void)
+{
+	// set the init clock as low when resume
+	set_mali_dvfs_status(0,0);
+}
+
+
+static void mali_dvfs_work_handler(struct work_struct *w)
+{
+	int change_clk = 0;
+	int change_step = 0;
+	bMaliDvfsRun=1;
+
+	/* dvfs table change when clock was changed */
+	if (step0_clk != mali_dvfs[0].clock) {
+		MALI_PRINT(("::: step0_clk change to %d Mhz\n", step0_clk));
+		change_clk = step0_clk;
+		change_step = 0;
+		step0_clk = change_dvfs_tableset(change_clk, change_step);
+	}
+#if (MALI_DVFS_STEPS > 1)
+	if (step1_clk != mali_dvfs[1].clock) {
+		MALI_PRINT(("::: step1_clk change to %d Mhz\n", step1_clk));
+		change_clk = step1_clk;
+		change_step = 1;
+		step1_clk = change_dvfs_tableset(change_clk, change_step);
+	}
+	if (step0_up != mali_dvfs_threshold[0].upthreshold) {
+		MALI_PRINT(("::: step0_up change to %d %\n", step0_up));
+		mali_dvfs_threshold[0].upthreshold = step0_up;
+	}
+	if (step1_down != mali_dvfs_threshold[1].downthreshold) {
+		MALI_PRINT((":::step1_down change to %d %\n", step1_down));
+		mali_dvfs_threshold[1].downthreshold = step1_down;
+	}
+#if (MALI_DVFS_STEPS > 2)
+	if (step2_clk != mali_dvfs[2].clock) {
+		MALI_PRINT(("::: step2_clk change to %d Mhz\n", step2_clk));
+		change_clk = step2_clk;
+		change_step = 2;
+		step2_clk = change_dvfs_tableset(change_clk, change_step);
+	}
+	if (step1_up != mali_dvfs_threshold[1].upthreshold) {
+		MALI_PRINT((":::step1_up change to %d %\n", step1_up));
+		mali_dvfs_threshold[1].upthreshold = step1_up;
+	}
+	if (step2_down != mali_dvfs_threshold[2].downthreshold) {
+		MALI_PRINT((":::step2_down change to %d %\n", step2_down));
+		mali_dvfs_threshold[2].downthreshold = step2_down;
+	}
+#if (MALI_DVFS_STEPS > 3)
+	if (step3_clk != mali_dvfs[3].clock) {
+		MALI_PRINT(("::: step3_clk change to %d Mhz\n", step3_clk));
+		change_clk = step3_clk;
+		change_step = 3;
+		step3_clk = change_dvfs_tableset(change_clk, change_step);
+	}
+	if (step2_up != mali_dvfs_threshold[2].upthreshold) {
+		MALI_PRINT((":::step2_up change to %d %\n", step2_up));
+		mali_dvfs_threshold[2].upthreshold = step2_up;
+	}
+	if (step3_down != mali_dvfs_threshold[3].downthreshold) {
+		MALI_PRINT((":::step3_down change to %d %\n", step3_down));
+		mali_dvfs_threshold[3].downthreshold = step3_down;
+	}
+#endif
+#endif
+#endif
+
+
+#ifdef DEBUG
+	mali_dvfs[0].vol = step0_vol;
+	mali_dvfs[1].vol = step1_vol;
+	mali_dvfs[2].vol = step2_vol;
+	mali_dvfs[3].vol = step3_vol;
+#endif
+	MALI_DEBUG_PRINT(3, ("=== mali_dvfs_work_handler\n"));
+
+	if (!mali_dvfs_status(mali_dvfs_utilization))
+		MALI_DEBUG_PRINT(1,( "error on mali dvfs status in mali_dvfs_work_handler"));
+
+	bMaliDvfsRun=0;
+}
+
+mali_bool init_mali_dvfs_status(int step)
+{
+	/*default status
+	add here with the right function to get initilization value.
+	*/
+	if (!mali_dvfs_wq)
+		mali_dvfs_wq = create_singlethread_workqueue("mali_dvfs");
+
+	_mali_osk_atomic_init(&bottomlock_status, 0);
+
+	/*add a error handling here*/
+	set_mali_dvfs_current_step(step);
+
+	return MALI_TRUE;
+}
+
+void deinit_mali_dvfs_status(void)
+{
+	if (mali_dvfs_wq)
+		destroy_workqueue(mali_dvfs_wq);
+
+	_mali_osk_atomic_term(&bottomlock_status);
+
+	mali_dvfs_wq = NULL;
+}
+
+mali_bool mali_dvfs_handler(u32 utilization)
+{
+	mali_dvfs_utilization = utilization;
+	queue_work_on(0, mali_dvfs_wq,&mali_dvfs_work);
+
+	/*add error handle here*/
+	return MALI_TRUE;
+}
+
+int change_dvfs_tableset(int change_clk, int change_step)
+{
+	int err;
+
+	if (change_clk < mali_dvfs_all[1].clock) {
+		mali_dvfs[change_step].clock = mali_dvfs_all[0].clock;
+	} else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) {
+		mali_dvfs[change_step].clock = mali_dvfs_all[1].clock;
+	} else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) {
+		mali_dvfs[change_step].clock = mali_dvfs_all[2].clock;
+	} else {
+		mali_dvfs[change_step].clock = mali_dvfs_all[3].clock;
+	}
+
+	MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol));
+
+	if (maliDvfsStatus.currentStep == change_step) {
+#ifdef CONFIG_REGULATOR
+		/*change the voltage*/
+		mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol);
+#endif
+		/*change the clock*/
+		mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq);
+
+		/* lock/unlock CPU freq by Mali */
+		if (mali_dvfs[change_step].clock == 440)
+			err = cpufreq_lock_by_mali(1200);
+		else
+			cpufreq_unlock_by_mali();
+	}
+
+	return mali_dvfs[change_step].clock;
+}
+
+void mali_default_step_set(int step, mali_bool boostup)
+{
+	mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
+
+	if (maliDvfsStatus.currentStep == 1)
+		set_mali_dvfs_status(step, boostup);
+}
+
+int mali_dvfs_bottom_lock_push(int lock_step)
+{
+	int prev_status = _mali_osk_atomic_read(&bottomlock_status);
+
+	if (prev_status < 0) {
+		MALI_PRINT(("gpu bottom lock status is not valid for push\n"));
+		return -1;
+	}
+	if (bottom_lock_step < lock_step) {
+		bottom_lock_step = lock_step;
+		if (get_mali_dvfs_status() < lock_step) {
+			mali_regulator_set_voltage(mali_dvfs[lock_step].vol,
+						   mali_dvfs[lock_step].vol);
+			mali_clk_set_rate(mali_dvfs[lock_step].clock,
+					  mali_dvfs[lock_step].freq);
+			set_mali_dvfs_current_step(lock_step);
+		}
+	}
+	return _mali_osk_atomic_inc_return(&bottomlock_status);
+}
+
+int mali_dvfs_bottom_lock_pop(void)
+{
+	int prev_status = _mali_osk_atomic_read(&bottomlock_status);
+	if (prev_status <= 0) {
+		MALI_PRINT(("gpu bottom lock status is not valid for pop\n"));
+		return -1;
+	} else if (prev_status == 1) {
+		bottom_lock_step = 0;
+		MALI_PRINT(("gpu bottom lock release\n"));
+	}
+
+	return _mali_osk_atomic_dec_return(&bottomlock_status);
+}
+
+#if MALI_VOLTAGE_LOCK
+int mali_vol_get_from_table(int vol)
+{
+	int i;
+	for (i = 0; i < MALI_DVFS_STEPS; i++) {
+		if (mali_dvfs[i].vol >= vol)
+			return mali_dvfs[i].vol;
+	}
+	MALI_PRINT(("Failed to get voltage from mali_dvfs table, maximum voltage is %d uV\n", mali_dvfs[MALI_DVFS_STEPS-1].vol));
+	return 0;
+}
+#endif
diff --git a/drivers/media/video/samsung/mali/regs/mali_200_regs.h b/drivers/media/video/samsung/mali/regs/mali_200_regs.h
new file mode 100644
index 0000000..e9da7ab
--- /dev/null
+++ b/drivers/media/video/samsung/mali/regs/mali_200_regs.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MALI200_REGS_H_
+#define _MALI200_REGS_H_
+
+/**
+ *  Enum for management register addresses.
+ */
+enum mali200_mgmt_reg
+{
+	MALI200_REG_ADDR_MGMT_VERSION                              = 0x1000,
+	MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR               = 0x1004,
+	MALI200_REG_ADDR_MGMT_STATUS                               = 0x1008,
+	MALI200_REG_ADDR_MGMT_CTRL_MGMT                            = 0x100c,
+
+	MALI200_REG_ADDR_MGMT_INT_RAWSTAT                          = 0x1020,
+	MALI200_REG_ADDR_MGMT_INT_CLEAR                            = 0x1024,
+	MALI200_REG_ADDR_MGMT_INT_MASK                             = 0x1028,
+	MALI200_REG_ADDR_MGMT_INT_STATUS                           = 0x102c,
+
+	MALI200_REG_ADDR_MGMT_WRITE_BOUNDARY_LOW                   = 0x1044,
+
+	MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS                     = 0x1050,
+
+	MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE                    = 0x1080,
+	MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC                       = 0x1084,
+	MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE                     = 0x108c,
+
+	MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE                    = 0x10a0,
+	MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC                       = 0x10a4,
+	MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE                     = 0x10ac,
+
+	MALI200_REG_SIZEOF_REGISTER_BANK                           = 0x10f0
+
+};
+
+#define MALI200_REG_VAL_PERF_CNT_ENABLE 1
+
+enum mali200_mgmt_ctrl_mgmt {
+	MALI200_REG_VAL_CTRL_MGMT_STOP_BUS         = (1<<0),
+#if defined(USING_MALI200)
+	MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES     = (1<<3),
+#endif
+	MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET      = (1<<5),
+	MALI200_REG_VAL_CTRL_MGMT_START_RENDERING  = (1<<6),
+#if defined(USING_MALI400)
+	MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET     = (1<<7),
+#endif
+};
+
+enum mali200_mgmt_irq {
+	MALI200_REG_VAL_IRQ_END_OF_FRAME          = (1<<0),
+	MALI200_REG_VAL_IRQ_END_OF_TILE           = (1<<1),
+	MALI200_REG_VAL_IRQ_HANG                  = (1<<2),
+	MALI200_REG_VAL_IRQ_FORCE_HANG            = (1<<3),
+	MALI200_REG_VAL_IRQ_BUS_ERROR             = (1<<4),
+	MALI200_REG_VAL_IRQ_BUS_STOP              = (1<<5),
+	MALI200_REG_VAL_IRQ_CNT_0_LIMIT           = (1<<6),
+	MALI200_REG_VAL_IRQ_CNT_1_LIMIT           = (1<<7),
+	MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR  = (1<<8),
+	MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1<<9),
+	MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW  = (1<<10),
+	MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW   = (1<<11),
+	MALI400PP_REG_VAL_IRQ_RESET_COMPLETED       = (1<<12),
+};
+
+#if defined USING_MALI200
+#define MALI200_REG_VAL_IRQ_MASK_ALL  ((enum mali200_mgmt_irq) (\
+    MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
+    MALI200_REG_VAL_IRQ_END_OF_TILE                            |\
+    MALI200_REG_VAL_IRQ_HANG                                   |\
+    MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
+    MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
+    MALI200_REG_VAL_IRQ_BUS_STOP                               |\
+    MALI200_REG_VAL_IRQ_CNT_0_LIMIT                            |\
+    MALI200_REG_VAL_IRQ_CNT_1_LIMIT                            |\
+    MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR))
+#elif defined USING_MALI400
+#define MALI200_REG_VAL_IRQ_MASK_ALL  ((enum mali200_mgmt_irq) (\
+    MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
+    MALI200_REG_VAL_IRQ_END_OF_TILE                            |\
+    MALI200_REG_VAL_IRQ_HANG                                   |\
+    MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
+    MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
+    MALI200_REG_VAL_IRQ_BUS_STOP                               |\
+    MALI200_REG_VAL_IRQ_CNT_0_LIMIT                            |\
+    MALI200_REG_VAL_IRQ_CNT_1_LIMIT                            |\
+    MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR                   |\
+    MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND                  |\
+    MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW                   |\
+    MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW                    |\
+    MALI400PP_REG_VAL_IRQ_RESET_COMPLETED))
+#else
+#error "No supported mali core defined"
+#endif
+
+#if defined USING_MALI200
+#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
+    MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
+    MALI200_REG_VAL_IRQ_HANG                                   |\
+    MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
+    MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
+    MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR))
+#elif defined USING_MALI400
+#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
+    MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
+    MALI200_REG_VAL_IRQ_HANG                                   |\
+    MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
+    MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
+    MALI200_REG_VAL_IRQ_BUS_STOP                               |\
+    MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR                   |\
+    MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND                  |\
+    MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW                   |\
+    MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW))
+#else
+#error "No supported mali core defined"
+#endif
+
+#define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0))
+
+enum mali200_mgmt_status {
+	MALI200_REG_VAL_STATUS_RENDERING_ACTIVE     = (1<<0),
+	MALI200_REG_VAL_STATUS_BUS_STOPPED          = (1<<4),
+};
+
+enum mali200_render_unit
+{
+	MALI200_REG_ADDR_FRAME = 0x0000,
+};
+
+#if defined USING_MALI200
+#define MALI200_NUM_REGS_FRAME ((0x04C/4)+1)
+#elif defined USING_MALI400
+#define MALI200_NUM_REGS_FRAME ((0x058/4)+1)
+#else
+#error "No supported mali core defined"
+#endif
+
+enum mali200_wb_unit {
+    MALI200_REG_ADDR_WB0 = 0x0100,
+    MALI200_REG_ADDR_WB1 = 0x0200,
+    MALI200_REG_ADDR_WB2 = 0x0300
+};
+
+/** The number of registers in one single writeback unit */
+#ifndef MALI200_NUM_REGS_WBx
+#define MALI200_NUM_REGS_WBx ((0x02C/4)+1)
+#endif
+
+/* This should be in the top 16 bit of the version register of Mali PP */
+#if defined USING_MALI200
+#define MALI_PP_PRODUCT_ID 0xC807
+#elif defined USING_MALI400
+#define MALI300_PP_PRODUCT_ID 0xCE07
+#define MALI400_PP_PRODUCT_ID 0xCD07
+#define MALI_PP_PRODUCT_ID MALI400_PP_PRODUCT_ID
+#else
+#error "No supported mali core defined"
+#endif
+
+
+#endif /* _MALI200_REGS_H_ */
diff --git a/drivers/media/video/samsung/mali/regs/mali_gp_regs.h b/drivers/media/video/samsung/mali/regs/mali_gp_regs.h
new file mode 100644
index 0000000..14719a3
--- /dev/null
+++ b/drivers/media/video/samsung/mali/regs/mali_gp_regs.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MALIGP2_CONROL_REGS_H_
+#define _MALIGP2_CONROL_REGS_H_
+
+/**
+ * These are the different geometry processor controll registers.
+ * Their usage is to control and monitor the operation of the
+ * Vertex Shader and the Polygon List Builer in the geometry processor.
+ * Addresses are in 32-bit word relative sizes.
+ * @see [P0081] "Geometry Processor Data Structures" for details
+ */
+
+typedef enum {
+	MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR           = 0x00,
+	MALIGP2_REG_ADDR_MGMT_VSCL_END_ADDR             = 0x04,
+	MALIGP2_REG_ADDR_MGMT_PLBUCL_START_ADDR         = 0x08,
+	MALIGP2_REG_ADDR_MGMT_PLBUCL_END_ADDR           = 0x0c,
+	MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR     = 0x10,
+	MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR       = 0x14,
+	MALIGP2_REG_ADDR_MGMT_CMD                       = 0x20,
+	MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT               = 0x24,
+	MALIGP2_REG_ADDR_MGMT_INT_CLEAR                 = 0x28,
+	MALIGP2_REG_ADDR_MGMT_INT_MASK                  = 0x2C,
+	MALIGP2_REG_ADDR_MGMT_INT_STAT                  = 0x30,
+	MALIGP2_REG_ADDR_MGMT_WRITE_BOUND_LOW           = 0x34,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE         = 0x3C,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE         = 0x40,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC            = 0x44,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC            = 0x48,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE          = 0x4C,
+	MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE          = 0x50,
+	MALIGP2_REG_ADDR_MGMT_STATUS                    = 0x68,
+	MALIGP2_REG_ADDR_MGMT_VERSION                   = 0x6C,
+	MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR_READ      = 0x80,
+	MALIGP2_REG_ADDR_MGMT_PLBCL_START_ADDR_READ     = 0x84,
+	MALIGP2_CONTR_AXI_BUS_ERROR_STAT                = 0x94,
+	MALIGP2_REGISTER_ADDRESS_SPACE_SIZE             = 0x98,
+} maligp_reg_addr_mgmt_addr;
+
+#define MALIGP2_REG_VAL_PERF_CNT_ENABLE 1
+
+/**
+ * Commands to geometry processor.
+ *  @see MALIGP2_CTRL_REG_CMD
+ */
+typedef enum
+{
+	MALIGP2_REG_VAL_CMD_START_VS			= (1<< 0),
+	MALIGP2_REG_VAL_CMD_START_PLBU			= (1<< 1),
+	MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC	= (1<< 4),
+	MALIGP2_REG_VAL_CMD_RESET				= (1<< 5),
+	MALIGP2_REG_VAL_CMD_FORCE_HANG			= (1<< 6),
+	MALIGP2_REG_VAL_CMD_STOP_BUS 			= (1<< 9),
+#if defined(USING_MALI400)
+	MALI400GP_REG_VAL_CMD_SOFT_RESET		= (1<<10),
+#endif
+} mgp_contr_reg_val_cmd;
+
+
+/**  @defgroup MALIGP2_IRQ
+ * Interrupt status of geometry processor.
+ *  @see MALIGP2_CTRL_REG_INT_RAWSTAT, MALIGP2_REG_ADDR_MGMT_INT_CLEAR,
+ *       MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_ADDR_MGMT_INT_STAT
+ * @{
+ */
+#define MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      (1 << 0)
+#define MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    (1 << 1)
+#define MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     (1 << 2)
+#define MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ          (1 << 3)
+#define MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ        (1 << 4)
+#define MALIGP2_REG_VAL_IRQ_HANG                (1 << 5)
+#define MALIGP2_REG_VAL_IRQ_FORCE_HANG          (1 << 6)
+#define MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT    (1 << 7)
+#define MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT    (1 << 8)
+#define MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     (1 << 9)
+#define MALIGP2_REG_VAL_IRQ_SYNC_ERROR          (1 << 10)
+#define MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       (1 << 11)
+#if defined USING_MALI400
+#define MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED     (1 << 12)
+#define MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      (1 << 13)
+#define MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     (1 << 14)
+#define MALI400GP_REG_VAL_IRQ_RESET_COMPLETED     (1 << 19)
+#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW (1 << 20)
+#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  (1 << 21)
+#define MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS  (1 << 22)
+#elif !defined USING_MALI200
+#error "No supported mali core defined"
+#endif
+
+/* Mask defining all IRQs in MaliGP2 */
+#if defined USING_MALI200
+#define MALIGP2_REG_VAL_IRQ_MASK_ALL \
+	(\
+		MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+		MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+		MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+		MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ          | \
+		MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ        | \
+		MALIGP2_REG_VAL_IRQ_HANG                | \
+		MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+		MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT    | \
+		MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT    | \
+		MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+		MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
+		MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR)
+#elif defined USING_MALI400
+#define MALIGP2_REG_VAL_IRQ_MASK_ALL \
+	(\
+		MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+		MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+		MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+		MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ          | \
+		MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ        | \
+		MALIGP2_REG_VAL_IRQ_HANG                | \
+		MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+		MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT    | \
+		MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT    | \
+		MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+		MALIGP2_REG_VAL_IRQ_SYNC_ERROR          | \
+		MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
+		MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED     | \
+		MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
+		MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
+		MALI400GP_REG_VAL_IRQ_RESET_COMPLETED     | \
+		MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
+		MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
+		MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+#else
+#error "No supported mali core defined"
+#endif
+
+/* Mask defining the IRQs in MaliGP2 which we use*/
+#if defined USING_MALI200
+#define MALIGP2_REG_VAL_IRQ_MASK_USED \
+	(\
+		MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+		MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+		MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+		MALIGP2_REG_VAL_IRQ_HANG                | \
+		MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+		MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+		MALIGP2_REG_VAL_IRQ_SYNC_ERROR 			| \
+		MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR)
+#elif defined USING_MALI400
+#define MALIGP2_REG_VAL_IRQ_MASK_USED \
+	(\
+		MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST      | \
+		MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST    | \
+		MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM     | \
+		MALIGP2_REG_VAL_IRQ_HANG                | \
+		MALIGP2_REG_VAL_IRQ_FORCE_HANG          | \
+		MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR     | \
+		MALIGP2_REG_VAL_IRQ_SYNC_ERROR 			| \
+		MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR       | \
+		MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD      | \
+		MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD     | \
+		MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
+		MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW  | \
+		MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+#else
+#error "No supported mali core defined"
+#endif
+
+/* Mask defining non IRQs on MaliGP2*/
+#define MALIGP2_REG_VAL_IRQ_MASK_NONE 0
+
+/** }@ defgroup MALIGP2_IRQ*/
+
+/** @defgroup MALIGP2_STATUS
+ * The different Status values to the geometry processor.
+ *  @see MALIGP2_CTRL_REG_STATUS
+ * @{
+ */
+#define MALIGP2_REG_VAL_STATUS_VS_ACTIVE         0x0002
+#define MALIGP2_REG_VAL_STATUS_BUS_STOPPED       0x0004
+#define MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE       0x0008
+#define MALIGP2_REG_VAL_STATUS_BUS_ERROR         0x0040
+#define MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR   0x0100
+/** }@ defgroup MALIGP2_STATUS*/
+
+#define MALIGP2_REG_VAL_STATUS_MASK_ACTIVE (\
+	MALIGP2_REG_VAL_STATUS_VS_ACTIVE|\
+	MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE)
+
+
+#define MALIGP2_REG_VAL_STATUS_MASK_ERROR (\
+	MALIGP2_REG_VAL_STATUS_BUS_ERROR |\
+	MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR )
+
+/* This should be in the top 16 bit of the version register of gp.*/
+#if defined(USING_MALI200)
+#define MALI_GP_PRODUCT_ID 0xA07
+#elif defined(USING_MALI400)
+#define MALI300_GP_PRODUCT_ID 0xC07
+#define MALI400_GP_PRODUCT_ID 0xB07
+#define MALI_GP_PRODUCT_ID MALI400_GP_PRODUCT_ID
+#else
+#error "No supported mali core defined"
+#endif
+
+/**
+ * The different sources for instrumented on the geometry processor.
+ *  @see MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC
+ */
+
+enum MALIGP2_cont_reg_perf_cnt_src {
+	MALIGP2_REG_VAL_PERF_CNT1_SRC_NUMBER_OF_VERTICES_PROCESSED = 0x0a,
+};
+
+#endif
diff --git a/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.c b/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.c
new file mode 100644
index 0000000..cddfa58
--- /dev/null
+++ b/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_timestamp.h"
+
+/* This file is intentionally left empty, as all functions are inlined in mali_profiling_sampler.h */
diff --git a/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.h b/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.h
new file mode 100644
index 0000000..442c6e0
--- /dev/null
+++ b/drivers/media/video/samsung/mali/timestamp-arm11-cc/mali_timestamp.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_TIMESTAMP_H__
+#define __MALI_TIMESTAMP_H__
+
+#include "mali_osk.h"
+
+MALI_STATIC_INLINE _mali_osk_errcode_t _mali_timestamp_reset(void)
+{
+	/*
+	 * reset counters and overflow flags
+	 */
+
+    u32 mask = (1 << 0) | /* enable all three counters */
+	           (0 << 1) | /* reset both Count Registers to 0x0 */
+	           (1 << 2) | /* reset the Cycle Counter Register to 0x0 */
+	           (0 << 3) | /* 1 = Cycle Counter Register counts every 64th processor clock cycle */
+	           (0 << 4) | /* Count Register 0 interrupt enable */
+	           (0 << 5) | /* Count Register 1 interrupt enable */
+	           (0 << 6) | /* Cycle Counter interrupt enable */
+	           (0 << 8) | /* Count Register 0 overflow flag (clear or write, flag on read) */
+	           (0 << 9) | /* Count Register 1 overflow flag (clear or write, flag on read) */
+	           (1 << 10); /* Cycle Counter Register overflow flag (clear or write, flag on read) */
+
+	__asm__ __volatile__ ("MCR    p15, 0, %0, c15, c12, 0" : : "r" (mask) );
+
+	return _MALI_OSK_ERR_OK;
+}
+
+MALI_STATIC_INLINE u64 _mali_timestamp_get(void)
+{
+	u32 result;
+
+	/* this is for the clock cycles */
+	__asm__ __volatile__ ("MRC    p15, 0, %0, c15, c12, 1" : "=r" (result));
+
+	return (u64)result;
+}
+
+#endif /* __MALI_TIMESTAMP_H__ */
diff --git a/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.c b/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.c
new file mode 100644
index 0000000..cddfa58
--- /dev/null
+++ b/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_timestamp.h"
+
+/* This file is intentionally left empty, as all functions are inlined in mali_profiling_sampler.h */
diff --git a/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.h b/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.h
new file mode 100644
index 0000000..470eac9
--- /dev/null
+++ b/drivers/media/video/samsung/mali/timestamp-default/mali_timestamp.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MALI_TIMESTAMP_H__
+#define __MALI_TIMESTAMP_H__
+
+#include "mali_osk.h"
+
+MALI_STATIC_INLINE _mali_osk_errcode_t _mali_timestamp_reset(void)
+{
+	return _MALI_OSK_ERR_OK;
+}
+
+MALI_STATIC_INLINE u64 _mali_timestamp_get(void)
+{
+	return _mali_osk_time_get_ns();
+}
+
+#endif /* __MALI_TIMESTAMP_H__ */
diff --git a/drivers/media/video/samsung/mfc5x/Kconfig b/drivers/media/video/samsung/mfc5x/Kconfig
new file mode 100644
index 0000000..0ff8a60
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/Kconfig
@@ -0,0 +1,39 @@
+#
+# Configuration for Multi Format Codecs (MFC)
+#
+config VIDEO_MFC5X
+	bool "Samsung MFC (Multi Format Codec - FIMV 5.x) Driver"
+	depends on USE_LEGACY_MFC
+	default n
+	---help---
+	  This is a Samsung Multi Format Codecs (MFC) FIMV V5.x
+
+config VIDEO_MFC_MAX_INSTANCE
+	int "Maximum size of MFC instance (1-4)"
+	range 1 4
+	depends on VIDEO_MFC5X
+	default 4
+
+config VIDEO_MFC_MEM_PORT_COUNT
+	int "Default number of MFC memory ports (1-2)"
+	range 1 2
+	depends on VIDEO_MFC5X && (!EXYNOS_CONTENT_PATH_PROTECTION)
+	default 2
+
+config VIDEO_MFC_VCM_UMP
+	bool "Support UMP over VCM for MFC"
+	depends on VIDEO_MFC5X && VCM_MMU && VIDEO_UMP
+	default y
+
+config VIDEO_MFC5X_DEBUG
+	bool "MFC driver debug message"
+	depends on VIDEO_MFC5X
+	default n
+
+config VIDEO_MFC5X_DEC_CHROMA_LUMA_4K_ALIGN
+	bool "4k align for chroma and luma size in dec"
+	depends on VIDEO_MFC5X && SLP
+	---help---
+	  To use physical address on the gem interface.
+
+
diff --git a/drivers/media/video/samsung/mfc5x/Makefile b/drivers/media/video/samsung/mfc5x/Makefile
new file mode 100644
index 0000000..eee420e
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/Makefile
@@ -0,0 +1,19 @@
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_dev.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_dec.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_enc.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_inst.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_cmd.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_shm.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_reg.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_buf.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_pm.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_ctrl.o
+obj-$(CONFIG_VIDEO_MFC5X) += mfc_mem.o
+
+ifeq ($(CONFIG_VIDEO_MFC5X_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
+
+ifeq ($(CONFIG_VIDEO_MFC_VCM_UMP),y)
+EXTRA_CFLAGS += -Idrivers/media/video/samsung/ump/include
+endif
diff --git a/drivers/media/video/samsung/mfc5x/SsbSipMfcApi.h b/drivers/media/video/samsung/mfc5x/SsbSipMfcApi.h
new file mode 100644
index 0000000..495f1ba
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/SsbSipMfcApi.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * user interface header for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _SSBSIP_MFC_API_H_
+#define _SSBSIP_MFC_API_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Definition                                                                     */
+/*--------------------------------------------------------------------------------*/
+#define MAX_DECODER_INPUT_BUFFER_SIZE  (1024 * 3072)
+#define MAX_ENCODER_OUTPUT_BUFFER_SIZE (1024 * 3072)
+
+#define SUPPORT_1080P        1
+
+#if SUPPORT_1080P
+#define MMAP_BUFFER_SIZE_MMAP          (70*1024*1024) /* only C110 use this value. in C210, memory size is decided in menuconfig*/
+#else
+#define MMAP_BUFFER_SIZE_MMAP          (62*1024*1024)
+#endif
+
+#define SAMSUNG_MFC_DEV_NAME           "/dev/s3c-mfc"
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+#define SUPPORT_SLICE_ENCODING        1
+#else
+#define SUPPORT_SLICE_ENCODING        0
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Structure and Type                                                             */
+/*--------------------------------------------------------------------------------*/
+typedef enum {
+    H264_DEC,
+    VC1_DEC,     /* VC1 advaced Profile decoding  */
+    MPEG4_DEC,
+    XVID_DEC,
+    MPEG1_DEC,
+    MPEG2_DEC,
+    H263_DEC,
+    VC1RCV_DEC,  /* VC1 simple/main profile decoding  */
+    FIMV1_DEC,
+    FIMV2_DEC,
+    FIMV3_DEC,
+    FIMV4_DEC,
+    H264_ENC,
+    MPEG4_ENC,
+    H263_ENC,
+    UNKNOWN_TYPE
+} SSBSIP_MFC_CODEC_TYPE;
+
+typedef enum {
+    DONT_CARE = 0,
+    I_FRAME = 1,
+    NOT_CODED = 2
+} SSBSIP_MFC_FORCE_SET_FRAME_TYPE;
+
+typedef enum {
+    NV12_LINEAR = 0,
+    NV12_TILE,
+    NV21_LINEAR,
+} SSBSIP_MFC_INSTRM_MODE_TYPE;
+
+#if SUPPORT_SLICE_ENCODING
+typedef enum {
+    FRAME = 0,
+    SLICE = 1,
+} SSBSIP_MFC_OUTSTRM_MODE_TYPE;
+#endif
+
+typedef enum {
+	NO_CACHE = 0,
+	CACHE = 1
+} SSBIP_MFC_BUFFER_TYPE;
+
+typedef enum {
+    MFC_DEC_SETCONF_POST_ENABLE = 1,
+    MFC_DEC_SETCONF_EXTRA_BUFFER_NUM,
+    MFC_DEC_SETCONF_DISPLAY_DELAY,
+    MFC_DEC_SETCONF_IS_LAST_FRAME,
+    MFC_DEC_SETCONF_SLICE_ENABLE,
+    MFC_DEC_SETCONF_CRC_ENABLE,
+    MFC_DEC_SETCONF_FIMV1_WIDTH_HEIGHT,
+    MFC_DEC_SETCONF_FRAME_TAG,
+    MFC_DEC_GETCONF_CRC_DATA,
+    MFC_DEC_GETCONF_BUF_WIDTH_HEIGHT,
+    MFC_DEC_GETCONF_CROP_INFO,
+    MFC_DEC_GETCONF_FRAME_TAG,
+
+    /* C210 specific feature */
+    MFC_DEC_SETCONF_IMMEDIATELY_DISPLAY,
+    MFC_DEC_SETCONF_DPB_FLUSH,
+    MFC_DEC_SETCONF_PIXEL_CACHE,
+    MFC_DEC_GETCONF_WIDTH_HEIGHT,
+
+    MFC_DEC_SETCONF_SEI_PARSE,
+    MFC_DEC_GETCONF_FRAME_PACKING,
+} SSBSIP_MFC_DEC_CONF;
+
+typedef enum {
+    MFC_ENC_SETCONF_FRAME_TYPE = 100,
+    MFC_ENC_SETCONF_CHANGE_FRAME_RATE,
+    MFC_ENC_SETCONF_CHANGE_BIT_RATE,
+    MFC_ENC_SETCONF_FRAME_TAG,
+    MFC_ENC_SETCONF_ALLOW_FRAME_SKIP,
+    MFC_ENC_GETCONF_FRAME_TAG,
+
+    /* C210 specific feature */
+    MFC_ENC_SETCONF_VUI_INFO,
+    MFC_ENC_SETCONF_I_PERIOD,
+    MFC_ENC_SETCONF_HIER_P,
+
+    MFC_ENC_SETCONF_SEI_GEN,
+    MFC_ENC_SETCONF_FRAME_PACKING,
+} SSBSIP_MFC_ENC_CONF;
+
+typedef enum {
+    MFC_GETOUTBUF_STATUS_NULL = 0,
+    MFC_GETOUTBUF_DECODING_ONLY = 1,
+    MFC_GETOUTBUF_DISPLAY_DECODING,
+    MFC_GETOUTBUF_DISPLAY_ONLY,
+    MFC_GETOUTBUF_DISPLAY_END,
+    MFC_GETOUTBUF_CHANGE_RESOL
+} SSBSIP_MFC_DEC_OUTBUF_STATUS;
+
+typedef enum {
+    MFC_FRAME_TYPE_NOT_CODED,
+    MFC_FRAME_TYPE_I_FRAME,
+    MFC_FRAME_TYPE_P_FRAME,
+    MFC_FRAME_TYPE_B_FRAME,
+    MFC_FRAME_TYPE_OTHERS
+} SSBSIP_MFC_FRAME_TYPE;
+
+typedef enum {
+    MFC_RET_OK                      = 1,
+    MFC_RET_FAIL                    = -1000,
+    MFC_RET_OPEN_FAIL               = -1001,
+    MFC_RET_CLOSE_FAIL              = -1002,
+
+    MFC_RET_DEC_INIT_FAIL           = -2000,
+    MFC_RET_DEC_EXE_TIME_OUT        = -2001,
+    MFC_RET_DEC_EXE_ERR             = -2002,
+    MFC_RET_DEC_GET_INBUF_FAIL      = -2003,
+    MFC_RET_DEC_SET_INBUF_FAIL      = -2004,
+    MFC_RET_DEC_GET_OUTBUF_FAIL     = -2005,
+    MFC_RET_DEC_GET_CONF_FAIL       = -2006,
+    MFC_RET_DEC_SET_CONF_FAIL       = -2007,
+
+    MFC_RET_ENC_INIT_FAIL           = -3000,
+    MFC_RET_ENC_EXE_TIME_OUT        = -3001,
+    MFC_RET_ENC_EXE_ERR             = -3002,
+    MFC_RET_ENC_GET_INBUF_FAIL      = -3003,
+    MFC_RET_ENC_SET_INBUF_FAIL      = -3004,
+    MFC_RET_ENC_GET_OUTBUF_FAIL     = -3005,
+    MFC_RET_ENC_SET_OUTBUF_FAIL     = -3006,
+    MFC_RET_ENC_GET_CONF_FAIL       = -3007,
+    MFC_RET_ENC_SET_CONF_FAIL       = -3008,
+
+    MFC_RET_INVALID_PARAM           = -4000
+} SSBSIP_MFC_ERROR_CODE;
+
+typedef struct {
+    void *YPhyAddr;                     /* [OUT] physical address of Y */
+    void *CPhyAddr;                     /* [OUT] physical address of CbCr */
+    void *YVirAddr;                     /* [OUT] virtual address of Y */
+    void *CVirAddr;                     /* [OUT] virtual address of CbCr */
+
+    int img_width;                      /* [OUT] width of real image */
+    int img_height;                     /* [OUT] height of real image */
+    int buf_width;                      /* [OUT] width aligned to 16 */
+    int buf_height;                     /* [OUT] height alighed to 16 */
+
+    int timestamp_top;                  /* [OUT] timestamp of top filed(This is used for interlaced stream) */
+    int timestamp_bottom;               /* [OUT] timestamp of bottom filed(This is used for interlaced stream) */
+    int consumedByte;                   /* [OUT] the number of byte consumed during decoding */
+    int res_change;                     /* [OUT] whether resolution is changed or not. 0: not change, 1: increased, 2: decreased */
+    int crop_top_offset;                /* [OUT] crop information, top_offset */
+    int crop_bottom_offset;             /* [OUT] crop information, bottom_offset */
+    int crop_left_offset;               /* [OUT] crop information, left_offset */
+    int crop_right_offset;              /* [OUT] crop information, right_offset */
+    int disp_pic_frame_type;            /* [OUT] display picture frame type information */
+
+    /* C210 UMP feature */
+    unsigned int y_cookie;              /* [OUT] cookie for Y address */
+    unsigned int c_cookie;              /* [OUT] cookie for CbCr address, If it is 0, Y and CbCr is in continous memory */
+} SSBSIP_MFC_DEC_OUTPUT_INFO;
+
+typedef struct {
+    void *YPhyAddr;                     /* [IN/OUT] physical address of Y */
+    void *CPhyAddr;                     /* [IN/OUT] physical address of CbCr */
+    void *YVirAddr;                     /* [IN/OUT] virtual address of Y */
+    void *CVirAddr;                     /* [IN/OUT] virtual address of CbCr */
+    int YSize;                          /* [IN/OUT] input size of Y data */
+    int CSize;                          /* [IN/OUT] input size of CbCr data */
+
+    /* C210 UMP feature */
+    unsigned int y_cookie;              /* [OUT] cookie for Y address */
+    unsigned int c_cookie;              /* [OUT] cookie for CbCr address, If it is 0, Y and CbCr is in continous memory */
+} SSBSIP_MFC_ENC_INPUT_INFO;
+
+typedef struct {
+    unsigned int dataSize;              /* [OUT] encoded data size(without header) */
+    unsigned int headerSize;            /* [OUT] encoded header size */
+    unsigned int frameType;             /* [OUT] frame type of encoded stream */
+    void *StrmPhyAddr;                  /* [OUT] physical address of Y */
+    void *StrmVirAddr;                  /* [OUT] virtual address of Y */
+    void *encodedYPhyAddr;              /* [OUT] physical address of Y which is flushed */
+    void *encodedCPhyAddr;              /* [OUT] physical address of C which is flushed */
+
+    /* C210 UMP feature */
+	unsigned int strm_cookie;			/* [OUT] cooke for stream buffer */
+    unsigned int y_encoded_cookie;      /* [OUT] cookie for Y address */
+    unsigned int c_encoded_cookie;      /* [OUT] cookie for CbCr address, If it is 0, Y and CbCr is in continous memory */
+} SSBSIP_MFC_ENC_OUTPUT_INFO;
+
+typedef struct {
+    /* common parameters */
+    SSBSIP_MFC_CODEC_TYPE codecType;    /* [IN] codec type */
+    int SourceWidth;                    /* [IN] width of video to be encoded */
+    int SourceHeight;                   /* [IN] height of video to be encoded */
+    int IDRPeriod;                      /* [IN] GOP number(interval of I-frame) */
+    int SliceMode;                      /* [IN] Multi slice mode */
+    int RandomIntraMBRefresh;           /* [IN] cyclic intra refresh */
+    int EnableFRMRateControl;           /* [IN] frame based rate control enable */
+    int Bitrate;                        /* [IN] rate control parameter(bit rate) */
+    int FrameQp;                        /* [IN] The quantization parameter of the frame */
+    int FrameQp_P;                      /* [IN] The quantization parameter of the P frame */
+    int QSCodeMax;                      /* [IN] Maximum Quantization value */
+    int QSCodeMin;                      /* [IN] Minimum Quantization value */
+    int CBRPeriodRf;                    /* [IN] Reaction coefficient parameter for rate control */
+    int PadControlOn;                   /* [IN] Enable padding control */
+    int LumaPadVal;                     /* [IN] Luma pel value used to fill padding area */
+    int CbPadVal;                       /* [IN] CB pel value used to fill padding area */
+    int CrPadVal;                       /* [IN] CR pel value used to fill padding area */
+    int FrameMap;                       /* [IN] Encoding input mode(tile mode or linear mode) */
+#if SUPPORT_SLICE_ENCODING
+    int OutputMode;                     /* [IN] Output mode: Frame/Slice */
+#endif
+
+    /* H.264 specific parameters */
+    int ProfileIDC;                     /* [IN] profile */
+    int LevelIDC;                       /* [IN] level */
+    int FrameQp_B;                      /* [IN] The quantization parameter of the B frame */
+    int FrameRate;                      /* [IN] rate control parameter(frame rate) */
+    int SliceArgument;                  /* [IN] MB number or byte number */
+    int NumberBFrames;                  /* [IN] The number of consecutive B frame inserted */
+    int NumberReferenceFrames;          /* [IN] The number of reference pictures used */
+    int NumberRefForPframes;            /* [IN] The number of reference pictures used for encoding P pictures */
+    int LoopFilterDisable;              /* [IN] disable the loop filter */
+    int LoopFilterAlphaC0Offset;        /* [IN] Alpha & C0 offset for H.264 loop filter */
+    int LoopFilterBetaOffset;           /* [IN] Beta offset for H.264 loop filter */
+    int SymbolMode;                     /* [IN] The mode of entropy coding(CABAC, CAVLC) */
+    int PictureInterlace;               /* [IN] Enables the interlace mode */
+    int Transform8x8Mode;               /* [IN] Allow 8x8 transform(This is allowed only for high profile) */
+    int EnableMBRateControl;            /* [IN] Enable macroblock-level rate control */
+    int DarkDisable;                    /* [IN] Disable adaptive rate control on dark region */
+    int SmoothDisable;                  /* [IN] Disable adaptive rate control on smooth region */
+    int StaticDisable;                  /* [IN] Disable adaptive rate control on static region */
+    int ActivityDisable;                /* [IN] Disable adaptive rate control on high activity region */
+} SSBSIP_MFC_ENC_H264_PARAM;
+
+typedef struct {
+    /* common parameters */
+    SSBSIP_MFC_CODEC_TYPE codecType;    /* [IN] codec type */
+    int SourceWidth;                    /* [IN] width of video to be encoded */
+    int SourceHeight;                   /* [IN] height of video to be encoded */
+    int IDRPeriod;                      /* [IN] GOP number(interval of I-frame) */
+    int SliceMode;                      /* [IN] Multi slice mode */
+    int RandomIntraMBRefresh;           /* [IN] cyclic intra refresh */
+    int EnableFRMRateControl;           /* [IN] frame based rate control enable */
+    int Bitrate;                        /* [IN] rate control parameter(bit rate) */
+    int FrameQp;                        /* [IN] The quantization parameter of the frame */
+    int FrameQp_P;                      /* [IN] The quantization parameter of the P frame */
+    int QSCodeMax;                      /* [IN] Maximum Quantization value */
+    int QSCodeMin;                      /* [IN] Minimum Quantization value */
+    int CBRPeriodRf;                    /* [IN] Reaction coefficient parameter for rate control */
+    int PadControlOn;                   /* [IN] Enable padding control */
+    int LumaPadVal;                     /* [IN] Luma pel value used to fill padding area */
+    int CbPadVal;                       /* [IN] CB pel value used to fill padding area */
+    int CrPadVal;                       /* [IN] CR pel value used to fill padding area */
+    int FrameMap;                       /* [IN] Encoding input mode(tile mode or linear mode) */
+#if SUPPORT_SLICE_ENCODING
+    int OutputMode;                     /* [IN] Output mode: Frame/Slice */
+#endif
+
+    /* MPEG4 specific parameters */
+    int ProfileIDC;                     /* [IN] profile */
+    int LevelIDC;                       /* [IN] level */
+    int FrameQp_B;                      /* [IN] The quantization parameter of the B frame */
+    int TimeIncreamentRes;              /* [IN] frame rate */
+    int VopTimeIncreament;              /* [IN] frame rate */
+    int SliceArgument;                  /* [IN] MB number or byte number */
+    int NumberBFrames;                  /* [IN] The number of consecutive B frame inserted */
+    int DisableQpelME;                  /* [IN] disable quarter-pixel motion estimation */
+} SSBSIP_MFC_ENC_MPEG4_PARAM;
+
+typedef struct {
+    /* common parameters */
+    SSBSIP_MFC_CODEC_TYPE codecType;    /* [IN] codec type */
+    int SourceWidth;                    /* [IN] width of video to be encoded */
+    int SourceHeight;                   /* [IN] height of video to be encoded */
+    int IDRPeriod;                      /* [IN] GOP number(interval of I-frame) */
+    int SliceMode;                      /* [IN] Multi slice mode */
+    int RandomIntraMBRefresh;           /* [IN] cyclic intra refresh */
+    int EnableFRMRateControl;           /* [IN] frame based rate control enable */
+    int Bitrate;                        /* [IN] rate control parameter(bit rate) */
+    int FrameQp;                        /* [IN] The quantization parameter of the frame */
+    int FrameQp_P;                      /* [IN] The quantization parameter of the P frame */
+    int QSCodeMax;                      /* [IN] Maximum Quantization value */
+    int QSCodeMin;                      /* [IN] Minimum Quantization value */
+    int CBRPeriodRf;                    /* [IN] Reaction coefficient parameter for rate control */
+    int PadControlOn;                   /* [IN] Enable padding control */
+    int LumaPadVal;                     /* [IN] Luma pel value used to fill padding area */
+    int CbPadVal;                       /* [IN] CB pel value used to fill padding area */
+    int CrPadVal;                       /* [IN] CR pel value used to fill padding area */
+    int FrameMap;                       /* [IN] Encoding input mode(tile mode or linear mode) */
+#if SUPPORT_SLICE_ENCODING
+    int OutputMode;                     /* [IN] Output mode: Frame/Slice */
+#endif
+
+    /* H.263 specific parameters */
+    int FrameRate;                      /* [IN] rate control parameter(frame rate) */
+} SSBSIP_MFC_ENC_H263_PARAM;
+
+typedef struct {
+    int width;
+    int height;
+    int buf_width;
+    int buf_height;
+} SSBSIP_MFC_IMG_RESOLUTION;
+
+typedef struct {
+    int crop_top_offset;
+    int crop_bottom_offset;
+    int crop_left_offset;
+    int crop_right_offset;
+} SSBSIP_MFC_CROP_INFORMATION;
+
+typedef struct {
+    int		  available;
+    unsigned int  arrangement_id;
+    int		  arrangement_cancel_flag;
+    unsigned char arrangement_type;
+    int		  quincunx_sampling_flag;
+    unsigned char content_interpretation_type;
+    int		  spatial_flipping_flag;
+    int		  frame0_flipped_flag;
+    int		  field_views_flag;
+    int		  current_frame_is_frame0_flag;
+    unsigned char frame0_grid_pos_x;
+    unsigned char frame0_grid_pos_y;
+    unsigned char frame1_grid_pos_x;
+    unsigned char frame1_grid_pos_y;
+} SSBSIP_MFC_FRAME_PACKING;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Format Conversion API                                                          */
+/*--------------------------------------------------------------------------------*/
+/* Format Conversion API */
+void Y_tile_to_linear_4x2(unsigned char *p_linear_addr, unsigned char *p_tiled_addr, unsigned int x_size, unsigned int y_size);
+void CbCr_tile_to_linear_4x2(unsigned char *p_linear_addr, unsigned char *p_tiled_addr, unsigned int x_size, unsigned int y_size);
+
+/* C210 specific feature */
+void tile_to_linear_64x32_4x2_neon(unsigned char *p_linear_addr, unsigned char *p_tiled_addr, unsigned int x_size, unsigned int y_size);
+void tile_to_linear_64x32_4x2_uv_neon(unsigned char *p_linear_addr, unsigned char *p_tiled_addr, unsigned int x_size, unsigned int y_size);
+void Convert_NV12_to_I420_NEON(unsigned char *YUV420p, unsigned char *YVU420sp,	unsigned int YSize, unsigned int UVPlaneSize);
+
+/*--------------------------------------------------------------------------------*/
+/* Decoding APIs                                                                  */
+/*--------------------------------------------------------------------------------*/
+void *SsbSipMfcDecOpen(void);
+void *SsbSipMfcDecOpenExt(void *value);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecInit(void *openHandle, SSBSIP_MFC_CODEC_TYPE codec_type, int Frameleng);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecExe(void *openHandle, int lengthBufFill);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecClose(void *openHandle);
+void  *SsbSipMfcDecGetInBuf(void *openHandle, void **phyInBuf, int inputBufferSize);
+
+
+#if (defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(USE_UMP))
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecSetInBuf(void *openHandle, unsigned int secure_id, int size);
+#else
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecSetInBuf(void *openHandle, void *phyInBuf, void *virInBuf, int size);
+#endif
+
+SSBSIP_MFC_DEC_OUTBUF_STATUS SsbSipMfcDecGetOutBuf(void *openHandle, SSBSIP_MFC_DEC_OUTPUT_INFO *output_info);
+
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecSetConfig(void *openHandle, SSBSIP_MFC_DEC_CONF conf_type, void *value);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcDecGetConfig(void *openHandle, SSBSIP_MFC_DEC_CONF conf_type, void *value);
+
+/*--------------------------------------------------------------------------------*/
+/* Encoding APIs                                                                  */
+/*--------------------------------------------------------------------------------*/
+void *SsbSipMfcEncOpen(void);
+void *SsbSipMfcEncOpenExt(void *value);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncInit(void *openHandle, void *param);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncExe(void *openHandle);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncClose(void *openHandle);
+
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncGetInBuf(void *openHandle, SSBSIP_MFC_ENC_INPUT_INFO *input_info);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncSetInBuf(void *openHandle, SSBSIP_MFC_ENC_INPUT_INFO *input_info);
+
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncGetOutBuf(void *openHandle, SSBSIP_MFC_ENC_OUTPUT_INFO *output_info);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncSetOutBuf (void *openHandle, void *phyOutbuf, void *virOutbuf, int outputBufferSize);
+
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncSetConfig(void *openHandle, SSBSIP_MFC_ENC_CONF conf_type, void *value);
+SSBSIP_MFC_ERROR_CODE SsbSipMfcEncGetConfig(void *openHandle, SSBSIP_MFC_ENC_CONF conf_type, void *value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SSBSIP_MFC_API_H_ */
diff --git a/drivers/media/video/samsung/mfc5x/mfc.h b/drivers/media/video/samsung/mfc5x/mfc.h
new file mode 100644
index 0000000..de1849c
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc.h
@@ -0,0 +1,101 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Global header for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_H_
+#define __MFC_H_ __FILE__
+
+#define MAX_HOR_SIZE	1920
+#define MAX_VER_SIZE	1088
+#define MAX_HOR_RES	1920
+#define MAX_VER_RES	1080
+
+#define MAX_MEM_OFFSET	0x10000000
+
+#ifdef CONFIG_VIDEO_MFC_MAX_INSTANCE
+#define MFC_MAX_INSTANCE_NUM	(CONFIG_VIDEO_MFC_MAX_INSTANCE)
+#else
+#define MFC_MAX_INSTANCE_NUM	(1)
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+
+#define MFC_MAX_MEM_CHUNK_NUM	(2)
+
+#define MFC_MAX_MEM_PORT_NUM	(1)
+
+#define MFC_MEMSIZE_PORT_A	(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE << 10)
+#define MFC_MEMSIZE_PORT_B	(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL << 10)
+
+#define MFC_MEMSIZE_DRM		0x20000
+#define MFC_SHM_OFS_DRM		0x400
+
+#else
+
+#ifdef CONFIG_VIDEO_MFC_MEM_PORT_COUNT
+#define MFC_MAX_MEM_PORT_NUM	(CONFIG_VIDEO_MFC_MEM_PORT_COUNT)
+#else
+#define MFC_MAX_MEM_PORT_NUM	(2)
+#endif
+
+#if (CONFIG_VIDEO_MFC_MEM_PORT_COUNT == 1)
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
+#define MFC_MEMSIZE_PORT_A	(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC << 10)
+#define MFC_MEMSIZE_PORT_B	0
+#else
+#define MFC_MEMSIZE_PORT_A	0x4000000
+#define MFC_MEMSIZE_PORT_B	0
+#endif
+
+#else
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
+#define MFC_MEMSIZE_PORT_A	(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 << 10)
+#else
+#define MFC_MEMSIZE_PORT_A	0x2000000
+#endif
+
+#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
+#define MFC_MEMSIZE_PORT_B	(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 << 10)
+#else
+#define MFC_MEMSIZE_PORT_B	0x2000000
+#endif
+
+#endif
+
+#endif
+
+#if defined(CONFIG_S5P_SYSMMU_MFC_L) && defined(CONFIG_S5P_SYSMMU_MFC_R)
+#define SYSMMU_MFC_ON
+#endif
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP) && !defined(SYSMMU_MFC_ON)
+#error In order to use UMP over VCM, you must configure System MMU for MFC_L and MFC_R!
+#endif
+
+#if defined(CONFIG_S5P_VMEM) && !defined(SYSMMU_MFC_ON)
+#error In order to use S5PVEM, you must configure System MMU for MFC_L and MFC_R!
+#endif
+
+/* if possible, the free virtual addr. for MFC be aligned with 128KB */
+#if defined(CONFIG_S5P_VMEM)
+#if defined(CONFIG_VMSPLIT_3G)
+#define MFC_FREEBASE	0xF0000000
+#elif defined(CONFIG_VMSPLIT_2G)
+#define MFC_FREEBASE	0xE0000000
+#else
+#error Not support current memory split configuration
+#endif
+#endif
+
+#endif /* __MFC_H_ */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_buf.c b/drivers/media/video/samsung/mfc5x/mfc_buf.c
new file mode 100644
index 0000000..e0e243d
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_buf.c
@@ -0,0 +1,1037 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_buf.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Buffer manager for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/err.h>
+
+#include "mfc.h"
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+#include "mfc_log.h"
+#include "mfc_errno.h"
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+#include <plat/s5p-vcm.h>
+
+#include "ump_kernel_interface.h"
+#include "ump_kernel_interface_ref_drv.h"
+#include "ump_kernel_interface_vcm.h"
+#endif
+
+#define PRINT_BUF
+#undef DEBUG_ALLOC_FREE
+
+static struct list_head mfc_alloc_head[MFC_MAX_MEM_PORT_NUM];
+/* The free node list sorted by real address */
+static struct list_head mfc_free_head[MFC_MAX_MEM_PORT_NUM];
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+static enum MFC_BUF_ALLOC_SCHEME buf_alloc_scheme = MBS_FIRST_FIT;
+#else
+static enum MFC_BUF_ALLOC_SCHEME buf_alloc_scheme = MBS_BEST_FIT;
+#endif
+
+/* FIXME: test locking, add locking mechanisim */
+/*
+static spinlock_t lock;
+*/
+
+
+void mfc_print_buf(void)
+{
+#ifdef PRINT_BUF
+	struct list_head *pos;
+	struct mfc_alloc_buffer *alloc = NULL;
+	struct mfc_free_buffer *free = NULL;
+	int port, i;
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		mfc_dbg("---- port %d buffer list ----", port);
+
+		i = 0;
+		list_for_each(pos, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+			mfc_dbg("[A #%04d] addr: 0x%08x, size: %d",
+				i, (unsigned int)alloc->addr, alloc->size);
+			mfc_dbg("\t  real: 0x%08lx", alloc->real);
+			mfc_dbg("\t  type: 0x%08x, owner: %d",
+				alloc->type, alloc->owner);
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+			mfc_dbg("\t* vcm sysmmu");
+			if (alloc->vcm_s) {
+				mfc_dbg("\t  start: 0x%08x, res_size  : 0x%08x\n",
+					(unsigned int)alloc->vcm_s->res.start,
+					(unsigned int)alloc->vcm_s->res.res_size);
+				mfc_dbg("\t  bound_size: 0x%08x\n",
+					(unsigned int)alloc->vcm_s->res.bound_size);
+			}
+
+			mfc_dbg("\t* vcm kernel");
+			if (alloc->vcm_k) {
+				mfc_dbg("\t  start: 0x%08x, res_size  : 0x%08x\n",
+					(unsigned int)alloc->vcm_k->start,
+					(unsigned int)alloc->vcm_k->res_size);
+				mfc_dbg("\t  bound_size: 0x%08x\n",
+					(unsigned int)alloc->vcm_k->bound_size);
+			}
+
+			mfc_dbg("\t* ump");
+			if (alloc->ump_handle) {
+				mfc_dbg("\t  secure id: 0x%08x",
+					mfc_ump_get_id(alloc->ump_handle));
+			}
+#elif defined(CONFIG_S5P_VMEM)
+			mfc_dbg("\t  vmem cookie: 0x%08x addr: 0x%08lx, size: %d",
+				alloc->vmem_cookie, alloc->vmem_addr,
+				alloc->vmem_size);
+#else
+			mfc_dbg("\t  offset: 0x%08x", alloc->ofs);
+#endif
+			i++;
+		}
+
+		i = 0;
+		list_for_each(pos, &mfc_free_head[port]) {
+			free = list_entry(pos, struct mfc_free_buffer, list);
+			mfc_dbg("[F #%04d] addr: 0x%08lx, size: %d",
+				i, free->real, free->size);
+			i++;
+		}
+	}
+#endif
+}
+
+static int mfc_put_free_buf(unsigned long addr, unsigned int size, int port)
+{
+	struct list_head *pos, *nxt;
+	struct mfc_free_buffer *free;
+	struct mfc_free_buffer *next = NULL;
+	struct mfc_free_buffer *prev;
+	/* 0x00: not merged, 0x01: prev merged, 0x02: next merged */
+	int merged = 0x00;
+
+	if (!size)
+		return -EINVAL;
+
+	mfc_dbg("addr: 0x%08lx, size: %d, port: %d\n", addr, size, port);
+
+	list_for_each_safe(pos, nxt, &mfc_free_head[port]) {
+		next = list_entry(pos, struct mfc_free_buffer, list);
+
+		/*
+		 * When the allocated address must be align without VMEM,
+		 * the free buffer can be overlap
+		 * previous free buffer temporaily
+		 * Target buffer will be shrink after this operation
+		 */
+		if (addr <= next->real) {
+			prev = list_entry(pos->prev, struct mfc_free_buffer, list);
+
+			mfc_dbg("prev->addr: 0x%08lx, size: %d", prev->real, prev->size);
+			/* merge previous free buffer */
+			if (prev && ((prev->real + prev->size) == addr)) {
+				addr  = prev->real;
+				size += prev->size;
+
+				prev->size = size;
+
+				merged |= 0x01;
+				mfc_dbg("auto merge free buffer[p]: addr: 0x%08lx, size: %d",
+					prev->real, prev->size);
+			}
+
+			mfc_dbg("next->addr: 0x%08lx, size: %d", next->real, next->size);
+			/* merge next free buffer */
+			if ((addr + size) == next->real) {
+				next->real  = addr;
+				next->size += size;
+
+				if (merged)
+					prev->size = next->size;
+
+				merged |= 0x02;
+				mfc_dbg("auto merge free buffer[n]: addr: 0x%08lx, size: %d",
+					next->real, next->size);
+			}
+
+			break;
+		}
+	}
+
+	if (!merged) {
+		free = (struct mfc_free_buffer *)
+			kzalloc(sizeof(struct mfc_free_buffer), GFP_KERNEL);
+
+		if (unlikely(free == NULL))
+			return -ENOMEM;
+
+		free->real = addr;
+		free->size = size;
+
+		list_add_tail(&free->list, pos);
+	}
+
+	/* bi-directional merged */
+	else if ((merged & 0x03) == 0x03) {
+		list_del(&next->list);
+		kfree(next);
+	}
+
+	return 0;
+}
+
+static unsigned long mfc_get_free_buf(unsigned int size, int align, int port)
+{
+	struct list_head *pos, *nxt;
+	struct mfc_free_buffer *free;
+	struct mfc_free_buffer *match = NULL;
+	int align_size = 0;
+	unsigned long addr = 0;
+
+	mfc_dbg("size: %d, align: %d, port: %d\n",
+			size, align, port);
+
+	if (list_empty(&mfc_free_head[port])) {
+		mfc_err("no free node in mfc buffer\n");
+
+		return 0;
+	}
+
+	/* find best fit area */
+	list_for_each_safe(pos, nxt, &mfc_free_head[port]) {
+		free = list_entry(pos, struct mfc_free_buffer, list);
+
+#if (defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(CONFIG_S5P_VMEM))
+		/*
+		 * Align the start address.
+		 * We assume the start address of free buffer aligned with 4KB
+		 */
+		align_size = ALIGN(align_size + size, PAGE_SIZE) - size;
+
+		if (align > PAGE_SIZE) {
+			align_size  = ALIGN(free->real, align) - free->real;
+			align_size += ALIGN(align_size + size, PAGE_SIZE) - size;
+		} else {
+			align_size = ALIGN(align_size + size, PAGE_SIZE) - size;
+		}
+#else
+		align_size = ALIGN(free->real, align) - free->real;
+#endif
+		if (free->size >= (size + align_size)) {
+			if (buf_alloc_scheme == MBS_BEST_FIT) {
+				if (match != NULL) {
+					if (free->size < match->size)
+						match = free;
+				} else {
+					match = free;
+				}
+			} else if (buf_alloc_scheme == MBS_FIRST_FIT) {
+				match = free;
+				break;
+			}
+		}
+	}
+
+	if (match != NULL) {
+		addr = match->real;
+		align_size = ALIGN(addr, align) - addr;
+
+#if !(defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(CONFIG_S5P_VMEM))
+		if (align_size > 0) {
+			/*
+			 * When the allocated address must be align without VMEM,
+			 * the free buffer can be overlap
+			 * previous free buffer temporaily
+			 */
+			if (mfc_put_free_buf(match->real, align_size, port) < 0)
+				return 0;
+		}
+#endif
+		/* change allocated buffer address & size */
+		match->real += (size + align_size);
+		match->size -= (size + align_size);
+
+		if (match->size == 0) {
+			list_del(&match->list);
+			kfree(match);
+		}
+	} else {
+		mfc_err("no suitable free node in mfc buffer\n");
+
+		return 0;
+	}
+
+	return addr;
+}
+
+int mfc_init_buf(void)
+{
+#ifndef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	int port;
+#endif
+	int ret = 0;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	INIT_LIST_HEAD(&mfc_alloc_head[0]);
+	INIT_LIST_HEAD(&mfc_free_head[0]);
+
+	if (mfc_put_free_buf(mfc_mem_data_base(0),
+		mfc_mem_data_size(0), 0) < 0)
+		mfc_err("failed to add free buffer: [0x%08lx: %d]\n",
+			mfc_mem_data_base(0), mfc_mem_data_size(0));
+
+	if (mfc_put_free_buf(mfc_mem_data_base(1),
+		mfc_mem_data_size(1), 0) < 0)
+		mfc_dbg("failed to add free buffer: [0x%08lx: %d]\n",
+			mfc_mem_data_base(1), mfc_mem_data_size(1));
+
+	if (list_empty(&mfc_free_head[0]))
+		ret = -1;
+
+#else
+	for (port = 0; port < mfc_mem_count(); port++) {
+		INIT_LIST_HEAD(&mfc_alloc_head[port]);
+		INIT_LIST_HEAD(&mfc_free_head[port]);
+
+		if (mfc_put_free_buf(mfc_mem_data_base(port),
+			mfc_mem_data_size(port), port) < 0)
+			mfc_err("failed to add free buffer: [0x%08lx: %d]\n",
+				mfc_mem_data_base(port),
+				mfc_mem_data_size(port));
+	}
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		if (list_empty(&mfc_free_head[port]))
+			ret = -1;
+	}
+#endif
+
+	/*
+	spin_lock_init(&lock);
+	*/
+
+	mfc_print_buf();
+
+	return ret;
+}
+
+void mfc_final_buf(void)
+{
+	struct list_head *pos, *nxt;
+	struct mfc_alloc_buffer *alloc;
+	struct mfc_free_buffer *free;
+	int port;
+	/*
+	unsigned long flags;
+	*/
+
+	/*
+	spin_lock_irqsave(&lock, flags);
+	*/
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+			if (alloc->ump_handle)
+				mfc_ump_unmap(alloc->ump_handle);
+
+			if (alloc->vcm_k)
+				mfc_vcm_unmap(alloc->vcm_k);
+
+			if (alloc->vcm_s)
+				mfc_vcm_unbind(alloc->vcm_s,
+						alloc->type & MBT_OTHER);
+
+			if (mfc_put_free_buf(alloc->vcm_addr,
+				alloc->vcm_size, port) < 0) {
+
+				mfc_err("failed to add free buffer\n");
+			} else {
+				list_del(&alloc->list);
+				kfree(alloc);
+			}
+#elif defined(CONFIG_S5P_VMEM)
+			if (alloc->vmem_cookie)
+				s5p_vfree(alloc->vmem_cookie);
+
+			if (mfc_put_free_buf(alloc->vmem_addr,
+				alloc->vmem_size, port) < 0) {
+
+				mfc_err("failed to add free buffer\n");
+			} else {
+				list_del(&alloc->list);
+				kfree(alloc);
+			}
+#else
+			if (mfc_put_free_buf(alloc->real,
+				alloc->size, port) < 0) {
+
+				mfc_err("failed to add free buffer\n");
+			} else {
+				list_del(&alloc->list);
+				kfree(alloc);
+			}
+#endif
+		}
+	}
+
+	/*
+	spin_unlock_irqrestore(&lock, flags);
+	*/
+
+	mfc_print_buf();
+
+	/*
+	spin_lock_irqsave(&lock, flags);
+	*/
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_free_head[port]) {
+			free = list_entry(pos, struct mfc_free_buffer, list);
+			list_del(&free->list);
+			kfree(free);
+		}
+	}
+
+	/*
+	spin_unlock_irqrestore(&lock, flags);
+	*/
+
+	mfc_print_buf();
+}
+
+void mfc_set_buf_alloc_scheme(enum MFC_BUF_ALLOC_SCHEME scheme)
+{
+	buf_alloc_scheme = scheme;
+}
+
+void mfc_merge_buf(void)
+{
+	struct list_head *pos, *nxt;
+	struct mfc_free_buffer *n1;
+	struct mfc_free_buffer *n2;
+	int port;
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_free_head[port]) {
+			n1 = list_entry(pos, struct mfc_free_buffer, list);
+			n2 = list_entry(nxt, struct mfc_free_buffer, list);
+
+			mfc_dbg("merge pre: n1: 0x%08lx, n2: 0x%08lx",
+				n1->real, n2->real);
+
+			if (!list_is_last(pos, &mfc_free_head[port])) {
+				if ((n1->real + n1->size) == n2->real) {
+					n2->real  = n1->real;
+					n2->size += n1->size;
+					list_del(&n1->list);
+					kfree(n1);
+				}
+			}
+
+			mfc_dbg("merge aft: n1: 0x%08lx, n2: 0x%08lx, last: %d",
+				n1->real, n2->real,
+				list_is_last(pos, &mfc_free_head[port]));
+		}
+	}
+
+#ifdef DEBUG_ALLOC_FREE
+	mfc_print_buf();
+#endif
+}
+
+/* FIXME: port auto select, return values */
+struct mfc_alloc_buffer *_mfc_alloc_buf(
+	struct mfc_inst_ctx *ctx, unsigned int size, int align, int flag)
+{
+	unsigned long addr;
+	struct mfc_alloc_buffer *alloc;
+	int port = flag & 0xFFFF;
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	int align_size = 0;
+	struct ump_vcm ump_vcm;
+#elif defined(CONFIG_S5P_VMEM)
+	int align_size = 0;
+#endif
+	/*
+	unsigned long flags;
+	*/
+
+	if (!size)
+		return NULL;
+
+	alloc = (struct mfc_alloc_buffer *)
+		kzalloc(sizeof(struct mfc_alloc_buffer), GFP_KERNEL);
+
+	if (unlikely(alloc == NULL))
+		return NULL;
+
+	/* FIXME: right position? */
+	if (port > (mfc_mem_count() - 1))
+		port = mfc_mem_count() - 1;
+
+	/*
+	spin_lock_irqsave(&lock, flags);
+	*/
+
+	addr = mfc_get_free_buf(size, align, port);
+
+	mfc_dbg("mfc_get_free_buf: 0x%08lx\n", addr);
+
+	if (!addr) {
+		mfc_dbg("cannot get suitable free buffer\n");
+		/* FIXME: is it need?
+		mfc_put_free_buf(addr, size, port);
+		*/
+		kfree(alloc);
+		/*
+		spin_unlock_irqrestore(&lock, flags);
+		*/
+
+		return NULL;
+	}
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	if (align > PAGE_SIZE) {
+		align_size = ALIGN(addr, align) - addr;
+		align_size += ALIGN(align_size + size, PAGE_SIZE) - size;
+	} else {
+		align_size = ALIGN(align_size + size, PAGE_SIZE) - size;
+	}
+
+	alloc->vcm_s = mfc_vcm_bind(addr, size + align_size);
+	if (IS_ERR(alloc->vcm_s)) {
+		mfc_put_free_buf(addr, size, port);
+		kfree(alloc);
+
+		return NULL;
+		/*
+		return PTR_ERR(alloc->vcm_s);
+		*/
+	}
+
+	if (flag & MBT_KERNEL) {
+		alloc->vcm_k = mfc_vcm_map(alloc->vcm_s->res.phys);
+		if (IS_ERR(alloc->vcm_k)) {
+			mfc_vcm_unbind(alloc->vcm_s,
+					alloc->type & MBT_OTHER);
+			mfc_put_free_buf(addr, size, port);
+			kfree(alloc);
+
+			return NULL;
+			/*
+			return PTR_ERR(alloc->vcm_k);
+			*/
+		}
+	}
+
+	if (flag & MBT_USER) {
+		ump_vcm.vcm = alloc->vcm_s->res.vcm;
+		ump_vcm.vcm_res = &(alloc->vcm_s->res);
+		ump_vcm.dev_id = VCM_DEV_MFC;
+
+		alloc->ump_handle = mfc_ump_map(alloc->vcm_s->res.phys, (unsigned long)&ump_vcm);
+		if (IS_ERR(alloc->ump_handle)) {
+			mfc_vcm_unmap(alloc->vcm_k);
+			mfc_vcm_unbind(alloc->vcm_s,
+					alloc->type & MBT_OTHER);
+			mfc_put_free_buf(addr, size, port);
+			kfree(alloc);
+
+		return NULL;
+			/*
+			return PTR_ERR(alloc->vcm_k);
+			*/
+		}
+	}
+
+	alloc->vcm_addr = addr;
+	alloc->vcm_size = size + align_size;
+#elif defined(CONFIG_S5P_VMEM)
+	if (align > PAGE_SIZE) {
+		align_size = ALIGN(addr, align) - addr;
+		align_size += ALIGN(align_size + size, PAGE_SIZE) - size;
+	} else {
+		align_size = ALIGN(align_size + size, PAGE_SIZE) - size;
+	}
+
+	alloc->vmem_cookie = s5p_vmem_vmemmap(size + align_size,
+			addr, addr + (size + align_size));
+
+	if (!alloc->vmem_cookie) {
+		mfc_dbg("cannot map free buffer to memory\n");
+		mfc_put_free_buf(addr, size, port);
+		kfree(alloc);
+
+		return NULL;
+	}
+
+	alloc->vmem_addr = addr;
+	alloc->vmem_size = size + align_size;
+#endif
+	alloc->real = ALIGN(addr, align);
+	alloc->size = size;
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	if (alloc->vcm_k)
+		alloc->addr = (unsigned char *)alloc->vcm_k->start;
+	else
+		alloc->addr = NULL;
+#elif defined(CONFIG_S5P_VMEM)
+	alloc->addr = (unsigned char *)(mfc_mem_addr(port) +
+		mfc_mem_base_ofs(alloc->real));
+#else
+	alloc->addr = (unsigned char *)(mfc_mem_addr(port) +
+		mfc_mem_base_ofs(alloc->real));
+	/*
+	alloc->user = (unsigned char *)(ctx->userbase +
+		mfc_mem_data_ofs(alloc->real, 1));
+	*/
+	alloc->ofs = mfc_mem_data_ofs(alloc->real, 1);
+#endif
+	alloc->type = flag & 0xFFFF0000;
+	alloc->owner = ctx->id;
+
+	list_add(&alloc->list, &mfc_alloc_head[port]);
+
+	/*
+	spin_unlock_irqrestore(&lock, flags);
+	*/
+
+#ifdef DEBUG_ALLOC_FREE
+	mfc_print_buf();
+#endif
+
+	return alloc;
+}
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+unsigned int mfc_vcm_bind_from_others(struct mfc_inst_ctx *ctx,
+				struct mfc_buf_alloc_arg *args, int flag)
+{
+	int ret;
+	unsigned long addr;
+	unsigned int size;
+	unsigned int secure_id = args->secure_id;
+	int port = flag & 0xFFFF;
+
+	struct vcm_res *vcm_res;
+	struct vcm_mmu_res *s_res;
+	struct mfc_alloc_buffer *alloc;
+
+	ump_dd_handle ump_mem;
+
+	/* FIXME: right position? */
+	if (port > (mfc_mem_count() - 1))
+		port = mfc_mem_count() - 1;
+
+	ump_mem = ump_dd_handle_create_from_secure_id(secure_id);
+	ump_dd_reference_add(ump_mem);
+
+	vcm_res = (struct vcm_res *)
+		ump_dd_meminfo_get(secure_id, (void*)VCM_DEV_MFC);
+	if (!vcm_res) {
+		mfc_dbg("%s: Failed to get vcm_res\n", __func__);
+		goto err_ret;
+	}
+
+	size = vcm_res->bound_size;
+
+	alloc = (struct mfc_alloc_buffer *)
+		kzalloc(sizeof(struct mfc_alloc_buffer), GFP_KERNEL);
+	if(!alloc) {
+		mfc_dbg("%s: Failed to get mfc_alloc_buffer\n", __func__);
+		goto err_ret;
+	}
+
+	addr = mfc_get_free_buf(size, ALIGN_2KB, port);
+	if (!addr) {
+		mfc_dbg("cannot get suitable free buffer\n");
+		goto err_ret_alloc;
+	}
+	mfc_dbg("mfc_get_free_buf: 0x%08lx\n", addr);
+
+	s_res = kzalloc(sizeof(struct vcm_mmu_res), GFP_KERNEL);
+	if (!s_res) {
+		mfc_dbg("%s: Failed to get vcm_mmu_res\n", __func__);
+		goto err_ret_alloc;
+	}
+
+	s_res->res.start = addr;
+	s_res->res.res_size = size;
+	s_res->res.vcm = ctx->dev->vcm_info.sysmmu_vcm;
+	INIT_LIST_HEAD(&s_res->bound);
+
+	ret = vcm_bind(&s_res->res, vcm_res->phys);
+	if (ret < 0) {
+		mfc_dbg("%s: Failed to vcm_bind\n", __func__);
+		goto err_ret_s_res;
+	}
+
+	alloc->vcm_s = s_res;
+	alloc->vcm_addr = addr;
+	alloc->ump_handle = ump_mem;
+	alloc->vcm_size = size;
+	alloc->real = addr;
+	alloc->size = size;
+	alloc->type = flag & 0xFFFF0000;
+	alloc->owner = ctx->id;
+
+	list_add(&alloc->list, &mfc_alloc_head[port]);
+
+	mfc_print_buf();
+
+	return 0;
+
+err_ret_s_res:
+	kfree(s_res);
+err_ret_alloc:
+	kfree(alloc);
+err_ret:
+	return -1;
+}
+#endif
+
+int
+mfc_alloc_buf(struct mfc_inst_ctx *ctx, struct mfc_buf_alloc_arg *args, int flag)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, args->size, args->align, flag);
+
+	if (unlikely(alloc == NULL))
+		return MFC_MEM_ALLOC_FAIL;
+	/*
+	args->phys = (unsigned int)alloc->real;
+	*/
+	args->addr = (unsigned int)alloc->addr;
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	if (alloc->ump_handle)
+		args->secure_id = mfc_ump_get_id(alloc->ump_handle);
+#elif defined(CONFIG_S5P_VMEM)
+	args->cookie = (unsigned int)alloc->vmem_cookie;
+#else
+	args->offset = alloc->ofs;
+#endif
+	return MFC_OK;
+}
+
+int _mfc_free_buf(unsigned long real)
+{
+	struct list_head *pos, *nxt;
+	struct mfc_alloc_buffer *alloc;
+	int port;
+	int found = 0;
+	/*
+	unsigned long flags;
+	*/
+
+	mfc_dbg("addr: 0x%08lx\n", real);
+
+	/*
+	spin_lock_irqsave(&lock, flags);
+	*/
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if (alloc->real == real) {
+				found = 1;
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+				if (alloc->ump_handle)
+					mfc_ump_unmap(alloc->ump_handle);
+
+				if (alloc->vcm_k)
+					mfc_vcm_unmap(alloc->vcm_k);
+
+				if (alloc->vcm_s)
+					mfc_vcm_unbind(alloc->vcm_s,
+							alloc->type & MBT_OTHER);
+
+				if (mfc_put_free_buf(alloc->vcm_addr,
+					alloc->vcm_size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#elif defined(CONFIG_S5P_VMEM)
+				if (alloc->vmem_cookie)
+					s5p_vfree(alloc->vmem_cookie);
+
+				if (mfc_put_free_buf(alloc->vmem_addr,
+					alloc->vmem_size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#else
+				if (mfc_put_free_buf(alloc->real,
+					alloc->size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#endif
+				break;
+			}
+		}
+
+		if (found)
+			break;
+	}
+
+	/*
+	spin_unlock_irqrestore(&lock, flags);
+	*/
+
+#ifdef DEBUG_ALLOC_FREE
+	mfc_print_buf();
+#endif
+
+	if (found)
+		return 0;
+
+	return -1;
+}
+
+int mfc_free_buf(struct mfc_inst_ctx *ctx, unsigned int key)
+{
+	unsigned long real;
+
+	real = mfc_get_buf_real(ctx->id, key);
+	if (unlikely(real == 0))
+		return MFC_MEM_INVALID_ADDR_FAIL;
+
+	if (_mfc_free_buf(real) < 0)
+		return MFC_MEM_INVALID_ADDR_FAIL;
+
+	return MFC_OK;
+}
+
+void mfc_free_buf_type(int owner, int type)
+{
+	int port;
+	struct list_head *pos, *nxt;
+	struct mfc_alloc_buffer *alloc;
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if ((alloc->owner == owner) && (alloc->type == type)) {
+				if (mfc_put_free_buf(alloc->real,
+					alloc->size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+			}
+		}
+	}
+}
+
+/* FIXME: add MFC Buffer Type */
+void mfc_free_buf_inst(int owner)
+{
+	struct list_head *pos, *nxt;
+	int port;
+	struct mfc_alloc_buffer *alloc;
+	/*
+	unsigned long flags;
+	*/
+
+	mfc_dbg("owner: %d\n", owner);
+
+	/*
+	spin_lock_irqsave(&lock, flags);
+	*/
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if (alloc->owner == owner) {
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+				if (alloc->ump_handle)
+					mfc_ump_unmap(alloc->ump_handle);
+
+				if (alloc->vcm_k)
+					mfc_vcm_unmap(alloc->vcm_k);
+
+				if (alloc->vcm_s)
+					mfc_vcm_unbind(alloc->vcm_s,
+							alloc->type & MBT_OTHER);
+
+				if (mfc_put_free_buf(alloc->vcm_addr,
+					alloc->vcm_size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#elif defined(CONFIG_S5P_VMEM)
+				if (alloc->vmem_cookie)
+					s5p_vfree(alloc->vmem_cookie);
+
+				if (mfc_put_free_buf(alloc->vmem_addr,
+					alloc->vmem_size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#else
+				if (mfc_put_free_buf(alloc->real,
+					alloc->size, port) < 0) {
+
+					mfc_err("failed to add free buffer\n");
+				} else {
+					list_del(&alloc->list);
+					kfree(alloc);
+				}
+#endif
+			}
+		}
+	}
+
+	/*
+	spin_unlock_irqrestore(&lock, flags);
+	*/
+
+#ifdef DEBUG_ALLOC_FREE
+	mfc_print_buf();
+#endif
+}
+
+unsigned long mfc_get_buf_real(int owner, unsigned int key)
+{
+	struct list_head *pos, *nxt;
+	int port;
+	struct mfc_alloc_buffer *alloc;
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+		mfc_dbg("owner: %d, secure id: 0x%08x\n", owner, key);
+#elif defined(CONFIG_S5P_VMEM)
+		mfc_dbg("owner: %d, cookie: 0x%08x\n", owner, key);
+#else
+		mfc_dbg("owner: %d, offset: 0x%08x\n", owner, key);
+#endif
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if (alloc->owner == owner) {
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+				if (alloc->ump_handle) {
+					if (mfc_ump_get_id(alloc->ump_handle) == key)
+						return alloc->real;
+				}
+#elif defined(CONFIG_S5P_VMEM)
+				if (alloc->vmem_cookie == key)
+					return alloc->real;
+#else
+				if (alloc->ofs == key)
+					return alloc->real;
+#endif
+			}
+		}
+	}
+
+	return 0;
+}
+
+#if 0
+unsigned char *mfc_get_buf_addr(int owner, unsigned char *user)
+{
+	struct list_head *pos, *nxt;
+	int port;
+	struct mfc_alloc_buffer *alloc;
+
+	mfc_dbg("owner: %d, user: 0x%08x\n", owner, (unsigned int)user);
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if ((alloc->owner == owner)
+				&& (alloc->user == user)){
+
+				return alloc->addr;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+unsigned char *_mfc_get_buf_addr(int owner, unsigned char *user)
+{
+	struct list_head *pos, *nxt;
+	int port;
+	struct mfc_alloc_buffer *alloc;
+
+	mfc_dbg("owner: %d, user: 0x%08x\n", owner, (unsigned int)user);
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if ((alloc->owner == owner)
+				&& ((alloc->user <= user) || ((alloc->user + alloc->size) > user))){
+
+				return alloc->addr;
+			}
+		}
+	}
+
+	return NULL;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+void *mfc_get_buf_ump_handle(unsigned long real)
+{
+	struct list_head *pos, *nxt;
+	int port;
+	struct mfc_alloc_buffer *alloc;
+
+	mfc_dbg("real: 0x%08lx\n", real);
+
+	for (port = 0; port < mfc_mem_count(); port++) {
+		list_for_each_safe(pos, nxt, &mfc_alloc_head[port]) {
+			alloc = list_entry(pos, struct mfc_alloc_buffer, list);
+
+			if (alloc->real == real)
+				return alloc->ump_handle;
+		}
+	}
+
+	return NULL;
+}
+#endif
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_buf.h b/drivers/media/video/samsung/mfc5x/mfc_buf.h
new file mode 100644
index 0000000..7fafb94
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_buf.h
@@ -0,0 +1,195 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_buf.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Buffer manager for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_BUF_H_
+#define __MFC_BUF_H_ __FILE__
+
+#include <linux/list.h>
+
+#include "mfc.h"
+#include "mfc_inst.h"
+#include "mfc_interface.h"
+
+/* FIXME */
+#define ALIGN_4B	(1 <<  2)
+#define ALIGN_2KB	(1 << 11)
+#define ALIGN_4KB	(1 << 12)
+#define ALIGN_8KB	(1 << 13)
+#define ALIGN_64KB	(1 << 16)
+#define ALIGN_128KB	(1 << 17)
+
+#define ALIGN_W		128	/* Tile, Horizontal, Luma & Chroma	*/
+#define ALIGN_H		32	/* Tile, Vertical, Luma & Chroma	*/
+#define ALIGN_W_L	16	/* Linear, Horizontal, Luma & Chroma	*/
+#define ALIGN_H_L_L	16	/* Linear, Vertical, Luma		*/
+#define ALIGN_H_L_C	8	/* Linear, Vertical, Chroma		*/
+
+/* System */					/* Size, Port, Align */
+#define MFC_FW_SYSTEM_SIZE	(0x80000)	/* 512KB, A, N(4KB for VMEM) */
+
+/* Instance */
+#define MFC_CTX_SIZE_L		(0x96000)	/* 600KB, N, 2KB, H.264 Decoding only */
+#define MFC_CTX_SIZE		(0x2800)	/* 10KB, N, 2KB */
+#define MFC_SHM_SIZE		(0x400)		/* 1KB, N, 4B */
+
+/* Decoding */
+#define MFC_CPB_SIZE		(0x400000)	/* Max.4MB, A, 2KB */
+#define MFC_DESC_SIZE		(0x20000)	/* Max.128KB, A, 2KB */
+
+#define MFC_DEC_NBMV_SIZE	(0x4000)	/* 16KB, A, 2KB */
+#define MFC_DEC_NBIP_SIZE	(0x8000)	/* 32KB, A, 2KB */
+#define MFC_DEC_NBDCAC_SIZE	(0x4000)	/* 16KB, A, 2KB */
+#define MFC_DEC_UPNBMV_SIZE	(0x11000)	/* 68KB, A, 2KB */
+#define MFC_DEC_SAMV_SIZE	(0x40000)	/* 256KB, A, 2KB */
+#define MFC_DEC_OTLINE_SIZE	(0x8000)	/* 32KB, A, 2KB */
+#define MFC_DEC_SYNPAR_SIZE	(0x11000)	/* 68KB, A, 2KB */
+#define MFC_DEC_BITPLANE_SIZE	(0x800)		/* 2KB, A, 2KB */
+
+/* Encoding */
+#define MFC_STRM_SIZE		(0x300000)	/* 3MB, A, 2KB (multi. 4KB) */
+
+/* FIXME: variable size */
+#define MFC_ENC_UPMV_SIZE	(0x10000)	/* Var, A, 2KB */
+#define MFC_ENC_COLFLG_SIZE	(0x10000)	/* Var, A, 2KB */
+#define MFC_ENC_INTRAMD_SIZE	(0x10000)	/* Var, A, 2KB */
+#define MFC_ENC_INTRAPRED_SIZE	(0x4000)	/* 16KB, A, 2KB */
+#define MFC_ENC_NBORINFO_SIZE	(0x10000)	/* Var, A, 2KB */
+#define MFC_ENC_ACDCCOEF_SIZE	(0x10000)	/* Var, A, 2KB */
+
+#define MFC_LUMA_ALIGN		ALIGN_8KB
+#define MFC_CHROMA_ALIGN	ALIGN_8KB
+#define MFC_MV_ALIGN		ALIGN_8KB	/* H.264 Decoding only */
+
+#define PORT_A			0
+#define PORT_B			1
+
+/* FIXME: MFC Buffer Type add as allocation parameter */
+/*
+#define MBT_ACCESS_MASK	(0xFF << 24)
+#define MBT_SYSMMU	(0x01 << 24)
+*/
+#define MBT_KERNEL	(0x02 << 24)
+#define MBT_USER	(0x04 << 24)
+#define MBT_OTHER	(0x08 << 24)
+#if 0
+#define MBT_TYPE_MASK	(0xFF << 16)
+#define MBT_CTX		(MBT_SYSMMU | MBT_KERNEL | (0x01 << 16))/* S, K */
+#define MBT_DESC	(MBT_SYSMMU | (0x02 << 16))		/* S */
+#define MBT_CODEC	(MBT_SYSMMU | (0x04 << 16))		/* S */
+#define MBT_SHM		(MBT_SYSMMU | MBT_KERNEL | (0x08 << 16))/* S, K */
+#define MBT_CPB		(MBT_SYSMMU | MBT_USER   | (0x10 << 16))/* D: S, [K], U E: */
+#define MBT_DPB		(MBT_SYSMMU | MBT_USER   | (0x20 << 16))/* D: S, [K], U E: */
+#endif
+#define MBT_CTX		(MBT_KERNEL | (0x01 << 16))	/* S, K */
+#define MBT_DESC		      (0x02 << 16)	/* S */
+#define MBT_CODEC		      (0x04 << 16)	/* S */
+#define MBT_SHM		(MBT_KERNEL | (0x08 << 16))	/* S, K */
+#if 0
+#define MBT_CPB		(MBT_USER | (0x10 << 16))	/* D: S, [K], U E: */
+#define MBT_DPB		(MBT_USER | (0x20 << 16))	/* D: S, [K], U E: */
+#endif
+#define MBT_CPB		(MBT_KERNEL | MBT_USER | (0x10 << 16))	/* D: S, [K], U E: */
+#define MBT_DPB		(MBT_KERNEL | MBT_USER | (0x20 << 16))	/* D: S, [K], U E: */
+
+enum MFC_BUF_ALLOC_SCHEME {
+	MBS_BEST_FIT	= 0,
+	MBS_FIRST_FIT	= 1,
+};
+
+/* Remove before Release */
+#if 0
+#define CPB_BUF_SIZE	(0x400000)       /* 3MB   : 3x1024x1024 for decoder    */
+#define DESC_BUF_SIZE         (0x20000)        /* 128KB : 128x1024                   */
+#define SHARED_BUF_SIZE       (0x10000)        /* 64KB  :  64x1024                   */
+#define PRED_BUF_SIZE         (0x10000)        /* 64KB  :  64x1024                   */
+#define DEC_CODEC_BUF_SIZE    (0x80000)        /* 512KB : 512x1024 size per instance */
+#define ENC_CODEC_BUF_SIZE    (0x50000)        /* 320KB : 512x1024 size per instance */
+
+#define STREAM_BUF_SIZE       (0x200000)       /* 2MB   : 2x1024x1024 for encoder    */
+#define MV_BUF_SIZE           (0x10000)        /* 64KB  : 64x1024 for encoder        */
+
+#define MFC_CONTEXT_SIZE_L  (640 * 1024)     /* 600KB -> 640KB for alignment       */
+#define VC1DEC_CONTEXT_SIZE   (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define MPEG2DEC_CONTEXT_SIZE (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define H263DEC_CONTEXT_SIZE  (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define MPEG4DEC_CONTEXT_SIZE (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define H264ENC_CONTEXT_SIZE  (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define MPEG4ENC_CONTEXT_SIZE (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+#define H263ENC_CONTEXT_SIZE  (64 * 1024)      /* 10KB  ->  64KB for alignment       */
+
+#define DESC_BUF_SIZE		(0x20000)	/* 128KB : 128x1024 */
+#define SHARED_MEM_SIZE		(0x1000)	/* 4KB   : 4x1024 size */
+
+#define CPB_BUF_SIZE		(0x400000)	/* 4MB : 4x1024x1024 for decoder */
+#define STREAM_BUF_SIZE		(0x200000)	/* 2MB : 2x1024x1024 for encoder */
+#define ENC_UP_INTRA_PRED_SIZE	(0x10000)	/* 64KB : 64x1024 for encoder */
+#endif
+
+struct mfc_alloc_buffer {
+	struct list_head list;
+	unsigned long real;	/* phys. or virt. addr for MFC	*/
+	unsigned int size;	/* allocation size		*/
+	unsigned char *addr;	/* kernel virtual address space */
+	unsigned int type;	/* buffer type			*/
+	int owner;		/* instance context id		*/
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	struct vcm_mmu_res *vcm_s;
+	struct vcm_res *vcm_k;
+	unsigned long vcm_addr;
+	size_t vcm_size;
+	void *ump_handle;
+#elif defined(CONFIG_S5P_VMEM)
+	unsigned int vmem_cookie;
+	unsigned long vmem_addr;
+	size_t vmem_size;
+#else
+	unsigned int ofs;	/*
+				 * offset phys. or virt. contiguous memory
+				 * phys.[bootmem, memblock] virt.[vmalloc]
+				 * when user use mmap,
+				 * user can access whole of memory by offset.
+				 */
+#endif
+};
+
+struct mfc_free_buffer {
+	struct list_head list;
+	unsigned long real;	/* phys. or virt. addr for MFC	*/
+	unsigned int size;
+};
+
+void mfc_print_buf(void);
+
+int mfc_init_buf(void);
+void mfc_final_buf(void);
+void mfc_set_buf_alloc_scheme(enum MFC_BUF_ALLOC_SCHEME scheme);
+void mfc_merge_buf(void);
+struct mfc_alloc_buffer *_mfc_alloc_buf(
+	struct mfc_inst_ctx *ctx, unsigned int size, int align, int flag);
+int mfc_alloc_buf(
+	struct mfc_inst_ctx *ctx, struct mfc_buf_alloc_arg* args, int flag);
+int _mfc_free_buf(unsigned long real);
+int mfc_free_buf(struct mfc_inst_ctx *ctx, unsigned int key);
+void mfc_free_buf_type(int owner, int type);
+void mfc_free_buf_inst(int owner);
+unsigned long mfc_get_buf_real(int owner, unsigned int key);
+/*
+unsigned char *mfc_get_buf_addr(int owner, unsigned char *user);
+unsigned char *_mfc_get_buf_addr(int owner, unsigned char *user);
+*/
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+unsigned int mfc_vcm_bind_from_others(struct mfc_inst_ctx *ctx,
+				struct mfc_buf_alloc_arg *args, int flag);
+void *mfc_get_buf_ump_handle(unsigned long real);
+#endif
+#endif /* __MFC_BUF_H_ */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_cmd.c b/drivers/media/video/samsung/mfc5x/mfc_cmd.c
new file mode 100644
index 0000000..38b4757
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_cmd.c
@@ -0,0 +1,504 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_cmd.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Command interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/jiffies.h>
+#include <linux/sched.h>
+
+#include <mach/regs-mfc.h>
+
+#include "mfc_cmd.h"
+#include "mfc_reg.h"
+#include "mfc_log.h"
+#include "mfc_dec.h"
+#include "mfc_enc.h"
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+
+static unsigned int r2h_cmd;
+static struct mfc_cmd_args r2h_args;
+
+#undef MFC_PERF
+
+#ifdef MFC_PERF
+static int framecnt = 0;
+struct timeval tv1, tv2;
+#endif
+
+irqreturn_t mfc_irq(int irq, void *dev_id)
+{
+	struct mfc_dev *dev = (struct mfc_dev *)dev_id;
+
+	r2h_cmd = read_reg(MFC_RISC2HOST_CMD);
+	mfc_dbg("MFC IRQ: %d\n", r2h_cmd);
+
+	if (((r2h_cmd >= OPEN_CH_RET) && (r2h_cmd <= CLOSE_CH_RET)) ||
+	    ((r2h_cmd >= SEQ_DONE_RET) && (r2h_cmd <= EDFU_INIT_RET)) ||
+	    ( r2h_cmd == ERR_RET)) {
+		memset(&r2h_args, 0, sizeof(struct mfc_cmd_args));
+
+		r2h_args.arg[0] = read_reg(MFC_RISC2HOST_ARG1);
+		r2h_args.arg[1] = read_reg(MFC_RISC2HOST_ARG2);
+		r2h_args.arg[2] = read_reg(MFC_RISC2HOST_ARG3);
+		r2h_args.arg[3] = read_reg(MFC_RISC2HOST_ARG4);
+
+		if (r2h_cmd == ERR_RET)
+			mfc_dbg("F/W error code: disp: %d, dec: %d",
+				(r2h_args.arg[1] >> 16) & 0xFFFF,
+				(r2h_args.arg[1]        & 0xFFFF));
+	} else {
+		mfc_dbg("Unknown R2H return value: %d\n", r2h_cmd);
+#if 0
+		mfc_err("== (0x64: 0x%08x) (0x68: 0x%08x) (0xE4: 0x%08x)  (0xE8: 0x%08x)\n", read_reg(0x64), read_reg(0x68),read_reg(0xe4), read_reg(0xe8));
+		mfc_err("== (0xF0: 0x%08x) (0xF4: 0x%08x) (0xF8: 0x%08x)  (0xFC: 0x%08x)\n", read_reg(0xf0), read_reg(0xf4), read_reg(0xf8), read_reg(0xfc));
+		mfc_err("== PWR 0x%08x CLK 0x%08x MASK 0x%08x PEND 0x%08x\n", __raw_readl(S5P_PMU_MFC_CONF),__raw_readl(EXYNOS4_CLKGATE_IP_MFC),
+									__raw_readl(S5P_VA_GIC_CPU + 0x1010c), __raw_readl(S5P_VA_GIC_CPU + 0x1020c));
+#endif
+	}
+
+#ifdef MFC_PERF
+	if (framecnt > 0) {
+		do_gettimeofday(&tv2);
+
+		mfc_info("%d, %ld", framecnt,
+			(long)(((tv2.tv_sec * 1000000) + tv2.tv_usec) - ((tv1.tv_sec * 1000000) + tv1.tv_usec)));
+
+		framecnt++;
+	}
+#endif
+
+	/*
+	 * FIXME: check is codec command return or error
+	 * move to mfc_wait_codec() ?
+	 */
+
+	write_reg(0xFFFF, MFC_SI_RTN_CHID);
+
+	write_reg(0, MFC_RISC2HOST_CMD);
+	write_reg(0, MFC_RISC_HOST_INT);
+
+	/* FIXME: codec wait_queue processing */
+	dev->irq_sys = 1;
+	wake_up(&dev->wait_sys);
+
+	return IRQ_HANDLED;
+}
+
+#if 0
+static bool mfc_wait_codec(struct mfc_inst_ctx *ctx, enum mfc_r2h_ret ret)
+{
+	/*
+	if (wait_event_timeout(dev->wait_codec[0], 0, timeout) == 0) {
+		mfc_err("F/W timeout: 0x%02x\n", ret);
+
+		return false;
+	}
+
+	if (r2h_cmd == ERR_RET)
+		mfc_err("F/W error code: 0x%02x", r2h_args.arg[1] & 0xFFFF);
+
+		return false;
+	}
+
+	if (r2h_cmd != ret) {
+		mfc_err("F/W return (0x%02x) waiting for (0x%02x)\n",
+			r2h_cmd, ret);
+
+		return false;
+	}
+	*/
+	return true;
+}
+#endif
+
+static bool
+mfc_wait_sys(struct mfc_dev *dev, enum mfc_r2h_ret ret, long timeout)
+{
+
+	if (wait_event_timeout(dev->wait_sys, dev->irq_sys, timeout) == 0) {
+		mfc_err("F/W timeout waiting for: %d\n", ret);
+		dev->irq_sys = 0;
+
+		return false;
+	}
+
+	dev->irq_sys = 0;
+
+	if (r2h_cmd == ERR_RET) {
+		mfc_err("F/W error code: disp: %d, dec: %d",
+			(r2h_args.arg[1] >> 16) & 0xFFFF,
+			(r2h_args.arg[1]        & 0xFFFF));
+
+		return false;
+	}
+
+#if SUPPORT_SLICE_ENCODING
+	if ((ret == FRAME_DONE_RET) && (r2h_cmd == EDFU_INIT_RET)
+		&& (dev->slice_encoding_flag == 0)) {
+		mfc_dbg("Slice encoding start : %d\n", r2h_cmd);
+		dev->slice_encoding_flag = 1;
+		dev->slice_sys = 0;
+	} else if ((ret == FRAME_DONE_RET) && (r2h_cmd == FRAME_DONE_RET)
+		&& (dev->slice_encoding_flag)) {
+		mfc_dbg("Slice encoding done : %d\n", r2h_cmd);
+		dev->slice_sys = 1;
+		dev->slice_encoding_flag = 0;
+		if (dev->wait_slice_timeout == 1)
+			wake_up(&dev->wait_slice);
+	}
+#endif
+
+	if (r2h_cmd != ret) {
+#if SUPPORT_SLICE_ENCODING
+		/* exceptional case: FRAME_START -> EDFU_INIT_RET */
+		if ((ret == FRAME_DONE_RET) && (r2h_cmd == EDFU_INIT_RET))
+			return true;
+
+		/* exceptional case: CLOSE_CH_RET -> ABORT_RET */
+		if ((ret == CLOSE_CH_RET) && (r2h_cmd == ABORT_RET))
+			return true;
+#endif
+		mfc_err("F/W return (%d) waiting for (%d)\n",
+			r2h_cmd, ret);
+
+		return false;
+	}
+
+	return true;
+}
+
+static bool write_h2r_cmd(enum mfc_h2r_cmd cmd, struct mfc_cmd_args *args)
+{
+	enum mfc_h2r_cmd pending_cmd;
+	unsigned long timeo = jiffies;
+
+	timeo += msecs_to_jiffies(H2R_CMD_TIMEOUT);
+
+	/* wait until host to risc command register becomes 'NOP' */
+	do {
+		pending_cmd = read_reg(MFC_HOST2RISC_CMD);
+
+		if (pending_cmd == H2R_NOP)
+			break;
+
+		schedule_timeout_uninterruptible(1);
+		/* FiXME: cpu_relax() */
+	} while (time_before(jiffies, timeo));
+
+	if (pending_cmd != H2R_NOP)
+		return false;
+
+	write_reg(args->arg[0], MFC_HOST2RISC_ARG1);
+	write_reg(args->arg[1], MFC_HOST2RISC_ARG2);
+	write_reg(args->arg[2], MFC_HOST2RISC_ARG3);
+	write_reg(args->arg[3], MFC_HOST2RISC_ARG4);
+
+	write_reg(cmd, MFC_HOST2RISC_CMD);
+
+	return true;
+}
+
+int mfc_cmd_fw_start(struct mfc_dev *dev)
+{
+	/* release RISC reset */
+	write_reg(0x3FF, MFC_SW_RESET);
+
+	if (mfc_wait_sys(dev, FW_STATUS_RET,
+		msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		mfc_err("failed to check F/W\n");
+		return MFC_FW_LOAD_FAIL;
+	}
+
+	return MFC_OK;
+}
+
+int mfc_cmd_sys_init(struct mfc_dev *dev)
+{
+	struct mfc_cmd_args h2r_args;
+	unsigned int fw_version, fw_memsize;
+
+	memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+	h2r_args.arg[0] = MFC_FW_SYSTEM_SIZE;
+
+	if (write_h2r_cmd(SYS_INIT, &h2r_args) == false)
+		return MFC_CMD_FAIL;
+
+	if (mfc_wait_sys(dev, SYS_INIT_RET,
+		msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		mfc_err("failed to init system\n");
+		return MFC_FW_INIT_FAIL;
+	}
+
+	fw_version = read_reg(MFC_FW_VERSION);
+	fw_memsize = r2h_args.arg[0];
+
+	mfc_info("MFC F/W version: %02x-%02x-%02x, %dkB\n",
+		 (fw_version >> 16) & 0xff,
+		 (fw_version >> 8) & 0xff,
+		 (fw_version) & 0xff,
+		 (fw_memsize) >> 10);
+
+	return MFC_OK;
+}
+
+int mfc_cmd_sys_sleep(struct mfc_dev *dev)
+{
+	struct mfc_cmd_args h2r_args;
+
+	memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+
+	if (write_h2r_cmd(SLEEP, &h2r_args) == false)
+		return MFC_CMD_FAIL;
+
+	if (mfc_wait_sys(dev, SLEEP_RET,
+		msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		mfc_err("failed to sleep\n");
+		return MFC_SLEEP_FAIL;
+	}
+
+	return MFC_OK;
+}
+
+int mfc_cmd_sys_wakeup(struct mfc_dev *dev)
+{
+	struct mfc_cmd_args h2r_args;
+
+	memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+
+	if (write_h2r_cmd(WAKEUP, &h2r_args) == false)
+		return MFC_CMD_FAIL;
+
+	/* release RISC reset */
+	write_reg(0x3FF, MFC_SW_RESET);
+
+	if (mfc_wait_sys(dev, WAKEUP_RET,
+		//msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		msecs_to_jiffies(20000)) == false) {
+		mfc_err("failed to wakeup\n");
+		return MFC_WAKEUP_FAIL;
+	}
+
+	return MFC_OK;
+}
+
+int mfc_cmd_inst_open(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_cmd_args h2r_args;
+	unsigned int crc = 0;
+	unsigned int pixelcache = 0;
+	struct mfc_dec_ctx *dec_ctx;
+	struct mfc_enc_ctx *enc_ctx;
+
+	if (ctx->type == DECODER) {
+		dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+
+		crc = dec_ctx->crc & 0x1;
+		pixelcache = dec_ctx->pixelcache & 0x3;
+	} else {
+		enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+		pixelcache = enc_ctx->pixelcache & 0x3;
+	}
+
+	memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+	h2r_args.arg[0] = ctx->codecid;
+	h2r_args.arg[1] = crc << 31 | pixelcache;
+	h2r_args.arg[2] = ctx->ctxbufofs;
+	h2r_args.arg[3] = ctx->ctxbufsize;
+
+	if (write_h2r_cmd(OPEN_CH, &h2r_args) == false)
+		return MFC_CMD_FAIL;
+
+	if (mfc_wait_sys(ctx->dev, OPEN_CH_RET,
+		msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		mfc_err("failed to open instance\n");
+		return MFC_OPEN_FAIL;
+	}
+
+	ctx->cmd_id = r2h_args.arg[0];
+
+	mfc_dbg("inst id: %d, cmd id: %d, codec id: %d",
+		ctx->id, ctx->cmd_id, ctx->codecid);
+
+#ifdef MFC_PERF
+	framecnt = 0;
+#endif
+
+	return ctx->cmd_id;
+}
+
+int mfc_cmd_inst_close(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_cmd_args h2r_args;
+
+	memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+	h2r_args.arg[0] = ctx->cmd_id;
+
+	if (write_h2r_cmd(CLOSE_CH, &h2r_args) == false)
+		return MFC_CMD_FAIL;
+
+	if (mfc_wait_sys(ctx->dev, CLOSE_CH_RET,
+		msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+		mfc_err("failed to close instance\n");
+		return MFC_CLOSE_FAIL;
+	}
+#if SUPPORT_SLICE_ENCODING
+	/* retry instance close */
+	if (r2h_cmd == ABORT_RET) {
+		if (write_h2r_cmd(CLOSE_CH, &h2r_args) == false)
+			return MFC_CMD_FAIL;
+
+		if (mfc_wait_sys(ctx->dev, CLOSE_CH_RET,
+			msecs_to_jiffies(H2R_INT_TIMEOUT)) == false) {
+			mfc_err("failed to close instance\n");
+			return MFC_CLOSE_FAIL;
+		}
+	}
+#endif
+
+	return MFC_OK;
+}
+
+int mfc_cmd_seq_start(struct mfc_inst_ctx *ctx)
+{
+	/* all codec command pass the shared mem addrees */
+	write_reg(ctx->shmofs, MFC_SI_CH1_HOST_WR_ADR);
+
+	write_reg((SEQ_HEADER << 16 & 0x70000) | ctx->cmd_id,
+		  MFC_SI_CH1_INST_ID);
+
+	/* FIXME: close_instance ? */
+	/* FIXME: mfc_wait_codec */
+	if (mfc_wait_sys(ctx->dev, SEQ_DONE_RET,
+		msecs_to_jiffies(CODEC_INT_TIMEOUT)) == false) {
+		mfc_err("failed to init seq start\n");
+		return MFC_DEC_INIT_FAIL;
+	}
+
+	if ((r2h_args.arg[1] & 0xFFFF) == 175) {
+		mfc_err("Non compliant feature detected\n");
+		return MFC_DEC_INIT_FAIL;
+	}
+
+	return MFC_OK;
+}
+
+int mfc_cmd_init_buffers(struct mfc_inst_ctx *ctx)
+{
+	/* all codec command pass the shared mem addrees */
+	write_reg(ctx->shmofs, MFC_SI_CH1_HOST_WR_ADR);
+
+	write_reg((INIT_BUFFERS << 16 & 0x70000) | ctx->cmd_id,
+		  MFC_SI_CH1_INST_ID);
+
+	/* FIXME: close_instance ? */
+	/* FIXME: mfc_wait_codec */
+	if (mfc_wait_sys(ctx->dev, INIT_BUFFERS_RET,
+		msecs_to_jiffies(CODEC_INT_TIMEOUT)) == false) {
+		mfc_err("failed to init buffers\n");
+		return MFC_DEC_INIT_FAIL;
+	}
+
+#ifdef MFC_PERF
+	framecnt = 1;
+#endif
+
+	return MFC_OK;
+}
+
+int mfc_cmd_frame_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx;
+
+	/* all codec command pass the shared mem addrees */
+	write_reg(ctx->shmofs, MFC_SI_CH1_HOST_WR_ADR);
+
+	if (ctx->type == DECODER) {
+		dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+
+		mfc_dbg("dec_ctx->lastframe: %d", dec_ctx->lastframe);
+
+		if (dec_ctx->lastframe) {
+			write_reg((LAST_SEQ << 16 & 0x70000) | ctx->cmd_id,
+				  MFC_SI_CH1_INST_ID);
+			dec_ctx->lastframe = 0;
+		} else if (ctx->resolution_status == RES_SET_CHANGE) {
+			mfc_dbg("FRAME_START_REALLOC\n");
+			write_reg((FRAME_START_REALLOC << 16 & 0x70000) | ctx->cmd_id,
+				  MFC_SI_CH1_INST_ID);
+			ctx->resolution_status = RES_WAIT_FRAME_DONE;
+		} else {
+			write_reg((FRAME_START << 16 & 0x70000) | ctx->cmd_id,
+				  MFC_SI_CH1_INST_ID);
+		}
+	} else { /* == ENCODER */
+		write_reg((FRAME_START << 16 & 0x70000) | ctx->cmd_id,
+			  MFC_SI_CH1_INST_ID);
+	}
+
+#ifdef MFC_PERF
+	do_gettimeofday(&tv1);
+#endif
+
+	/* FIXME: close_instance ? */
+	/* FIXME: mfc_wait_codec */
+	if (mfc_wait_sys(ctx->dev, FRAME_DONE_RET,
+		msecs_to_jiffies(CODEC_INT_TIMEOUT)) == false) {
+		mfc_err("failed to frame start\n");
+		return MFC_DEC_EXE_TIME_OUT;
+	}
+
+	return MFC_OK;
+}
+
+#if SUPPORT_SLICE_ENCODING
+int mfc_cmd_slice_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	struct mfc_cmd_args h2r_args;
+
+	/* all codec command pass the shared mem addrees */
+	write_reg(ctx->shmofs, MFC_SI_CH1_HOST_WR_ADR);
+
+	if (enc_ctx->slicecount == 0) {
+		write_reg((FRAME_START << 16 & 0x70000) | ctx->cmd_id,
+			MFC_SI_CH1_INST_ID);
+
+		enc_ctx->slicecount = 1;
+	} else {
+		memset(&h2r_args, 0, sizeof(struct mfc_cmd_args));
+		h2r_args.arg[0] = enc_ctx->streamaddr >> 11;
+
+		if (write_h2r_cmd(CONTINUE_ENC, &h2r_args) == false)
+			return MFC_CMD_FAIL;
+	}
+
+#ifdef MFC_PERF
+	do_gettimeofday(&tv1);
+#endif
+
+	if (mfc_wait_sys(ctx->dev, FRAME_DONE_RET,
+		msecs_to_jiffies(CODEC_INT_TIMEOUT)) == false) {
+		mfc_err("failed to slice start\n");
+		return MFC_DEC_EXE_TIME_OUT;
+	}
+
+	if (r2h_cmd == EDFU_INIT_RET)
+		enc_ctx->slicecount++;
+	else /* FRAME_DONE_RET */
+		enc_ctx->slicecount = 0;
+
+	enc_ctx->slicesize = r2h_args.arg[2];
+
+	return MFC_OK;
+}
+#endif
diff --git a/drivers/media/video/samsung/mfc5x/mfc_cmd.h b/drivers/media/video/samsung/mfc5x/mfc_cmd.h
new file mode 100644
index 0000000..ac1f0c9
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_cmd.h
@@ -0,0 +1,90 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_cmd.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Command interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_CMD_H
+#define __MFC_CMD_H __FILE__
+
+#include <linux/interrupt.h>
+
+#include "mfc_dev.h"
+
+#define MAX_H2R_ARG		4
+#define H2R_CMD_TIMEOUT		1000	/* ms */
+#define H2R_INT_TIMEOUT		5000	/* ms */
+#define CODEC_INT_TIMEOUT	1000	/* ms */
+#define SLICE_ENC_TIMEOUT	1000	/* ms */
+
+enum mfc_h2r_cmd {
+	H2R_NOP		= 0,
+	OPEN_CH		= 1,
+	CLOSE_CH	= 2,
+	SYS_INIT	= 3,
+	FLUSH		= 4,
+	SLEEP		= 5,
+	WAKEUP		= 6,
+	CONTINUE_ENC	= 7,
+	ABORT_ENC	= 8,
+};
+
+enum mfc_codec_cmd {
+	SEQ_HEADER		= 1,
+	FRAME_START		= 2,
+	LAST_SEQ		= 3,
+	INIT_BUFFERS		= 4,
+	FRAME_START_REALLOC	= 5,
+	FRAME_BATCH_START	= 6,
+};
+
+enum mfc_r2h_ret {
+	R2H_NOP			= 0,
+	OPEN_CH_RET		= 1,
+	CLOSE_CH_RET		= 2,
+
+	SEQ_DONE_RET		= 4,
+	FRAME_DONE_RET		= 5,
+	SLICE_DONE_RET		= 6,
+	ENC_COMPLETE_RET	= 7,
+	SYS_INIT_RET		= 8,
+	FW_STATUS_RET		= 9,
+	SLEEP_RET		= 10,
+	WAKEUP_RET		= 11,
+	FLUSH_CMD_RET		= 12,
+	ABORT_RET		= 13,
+	BATCH_ENC_RET		= 14,
+	INIT_BUFFERS_RET	= 15,
+	EDFU_INIT_RET		= 16,
+
+	ERR_RET			= 32,
+};
+
+struct mfc_cmd_args {
+	unsigned int	arg[MAX_H2R_ARG];
+};
+
+irqreturn_t mfc_irq(int irq, void *dev_id);
+
+int mfc_cmd_fw_start(struct mfc_dev *dev);
+int mfc_cmd_sys_init(struct mfc_dev *dev);
+int mfc_cmd_sys_sleep(struct mfc_dev *dev);
+int mfc_cmd_sys_wakeup(struct mfc_dev *dev);
+
+int mfc_cmd_inst_open(struct mfc_inst_ctx *ctx);
+int mfc_cmd_inst_close(struct mfc_inst_ctx *ctx);
+int mfc_cmd_seq_start(struct mfc_inst_ctx *ctx);
+int mfc_cmd_init_buffers(struct mfc_inst_ctx *ctx);
+int mfc_cmd_frame_start(struct mfc_inst_ctx *ctx);
+#if SUPPORT_SLICE_ENCODING
+int mfc_cmd_slice_start(struct mfc_inst_ctx *ctx);
+#endif
+
+#endif /* __MFC_CMD_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_ctrl.c b/drivers/media/video/samsung/mfc5x/mfc_ctrl.c
new file mode 100644
index 0000000..11d35d3
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_ctrl.c
@@ -0,0 +1,186 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_ctrl.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Control interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <mach/regs-mfc.h>
+
+#include "mfc.h"
+#include "mfc_mem.h"
+#include "mfc_reg.h"
+#include "mfc_log.h"
+#include "mfc_cmd.h"
+#include "mfc_dev.h"
+#include "mfc_errno.h"
+#include "mfc_pm.h"
+
+#define MC_STATUS_TIMEOUT	1000	/* ms */
+
+static bool mfc_reset(void)
+{
+	unsigned int mc_status;
+	unsigned long timeo = jiffies;
+
+	timeo += msecs_to_jiffies(MC_STATUS_TIMEOUT);
+
+	/* Stop procedure */
+	/* FIXME: F/W can be access invalid address */
+	/* Reset VI */
+	/*
+	write_reg(0x3F7, MFC_SW_RESET);
+	*/
+	write_reg(0x3F6, MFC_SW_RESET);	/* Reset RISC */
+	write_reg(0x3E2, MFC_SW_RESET);	/* All reset except for MC */
+	mdelay(10);
+
+	/* Check MC status */
+	do {
+		mc_status = (read_reg(MFC_MC_STATUS) & 0x3);
+
+		if (mc_status == 0)
+			break;
+
+		schedule_timeout_uninterruptible(1);
+		/* FiXME: cpu_relax() */
+	} while (time_before(jiffies, timeo));
+
+	if (mc_status != 0)
+		return false;
+
+	write_reg(0x0, MFC_SW_RESET);
+	write_reg(0x3FE, MFC_SW_RESET);
+
+	return true;
+}
+
+static void mfc_init_memctrl(void)
+{
+	/* Channel A, Port 0 */
+	write_reg(mfc_mem_base(0), MFC_MC_DRAMBASE_ADR_A);
+#if MFC_MAX_MEM_PORT_NUM == 1
+	/* Channel B, Port 0 */
+	write_reg(mfc_mem_base(0), MFC_MC_DRAMBASE_ADR_B);
+#else
+	/* Channel B, Port 1 */
+	write_reg(mfc_mem_base(1), MFC_MC_DRAMBASE_ADR_B);
+#endif
+	mfc_dbg("Master A - 0x%08x\n",
+		  read_reg(MFC_MC_DRAMBASE_ADR_A));
+	mfc_dbg("Master B - 0x%08x\n",
+		  read_reg(MFC_MC_DRAMBASE_ADR_B));
+}
+
+static void mfc_clear_cmds(void)
+{
+	write_reg(0xFFFFFFFF, MFC_SI_CH1_INST_ID);
+	write_reg(0xFFFFFFFF, MFC_SI_CH2_INST_ID);
+
+	write_reg(H2R_NOP, MFC_RISC2HOST_CMD);
+	write_reg(R2H_NOP, MFC_HOST2RISC_CMD);
+}
+
+int mfc_load_firmware(const unsigned char *data, size_t size)
+{
+	volatile unsigned char *fw;
+
+	if (!data || size == 0)
+		return 0;
+
+	/* MFC F/W area already 128KB aligned */
+	fw = mfc_mem_addr(0);
+
+	memcpy((void *)fw, data, size);
+
+	mfc_mem_cache_clean((void *)fw, size);
+
+	return 1;
+}
+
+int mfc_start(struct mfc_dev *dev)
+{
+	int ret;
+
+	/* FIXME: when MFC start, load firmware again */
+	/*
+	dev->fw.state = mfc_load_firmware(dev->fw.info->data, dev->fw.info->size);
+	*/
+
+	mfc_clock_on(dev);
+
+	if (mfc_reset() == false) {
+		mfc_clock_off(dev);
+		return MFC_FAIL;
+	}
+
+	mfc_init_memctrl();
+	mfc_clear_cmds();
+
+	ret = mfc_cmd_fw_start(dev);
+	if (ret < 0) {
+		mfc_clock_off(dev);
+		return ret;
+	}
+
+	ret = mfc_cmd_sys_init(dev);
+
+	mfc_clock_off(dev);
+
+	return ret;
+}
+
+int mfc_sleep(struct mfc_dev *dev)
+{
+	int ret;
+
+	mfc_clock_on(dev);
+
+	/* FIXME: add SFR backup? */
+
+	ret = mfc_cmd_sys_sleep(dev);
+
+	mfc_clock_off(dev);
+
+	/* FIXME: add mfc_power_off()? */
+
+	/* FIXME: ret = 0 */
+	return ret;
+}
+
+int mfc_wakeup(struct mfc_dev *dev)
+{
+	int ret;
+
+	/* FIXME: add mfc_power_on()? */
+
+	mfc_clock_on(dev);
+
+	if (mfc_reset() == false) {
+		mfc_clock_off(dev);
+		return MFC_FAIL;
+	}
+
+	mfc_init_memctrl();
+	mfc_clear_cmds();
+
+	ret = mfc_cmd_sys_wakeup(dev);
+
+	mfc_clock_off(dev);
+
+	/* FIXME: ret = 0 */
+	return ret;
+}
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_ctrl.h b/drivers/media/video/samsung/mfc5x/mfc_ctrl.h
new file mode 100644
index 0000000..7822f59
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_ctrl.h
@@ -0,0 +1,22 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_ctrl.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Control interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_CTRL_H
+#define __MFC_CTRL_H __FILE__
+
+int mfc_load_firmware(const unsigned char *data, size_t size);
+int mfc_start(struct mfc_dev *dev);
+int mfc_sleep(struct mfc_dev *dev);
+int mfc_wakeup(struct mfc_dev *dev);
+
+#endif /* __MFC_CTRL_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_dec.c b/drivers/media/video/samsung/mfc5x/mfc_dec.c
new file mode 100644
index 0000000..6e0645d
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_dec.c
@@ -0,0 +1,2416 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_dec.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Decoder interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/cacheflush.h>
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_BUSFREQ_OPP
+#include <plat/cpu.h>
+#include <mach/busfreq_exynos4.h>
+#define HD_MOVIE_SIZE_MULTIPLY_WIDTH_HEIGHT (1281*721)
+#endif
+
+#if defined(CONFIG_BUSFREQ) || defined(CONFIG_EXYNOS4_CPUFREQ)
+#include <mach/cpufreq.h>
+#endif
+#include <mach/regs-mfc.h>
+
+#include "mfc_dec.h"
+#include "mfc_cmd.h"
+#include "mfc_log.h"
+
+#include "mfc_shm.h"
+#include "mfc_reg.h"
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+
+#undef DUMP_STREAM
+
+#ifdef DUMP_STREAM
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+#include <linux/file.h>
+
+static void mfc_fw_debug(void);
+static void dump_stream(unsigned long address, unsigned int size);
+#endif
+static LIST_HEAD(mfc_decoders);
+
+#if 0
+#define MPEG4_START_CODE_PREFIX_SIZE	3
+#define MPEG4_START_CODE_PREFIX		0x000001
+#define MPEG4_START_CODE_MASK		0x000000FF
+static int find_mpeg4_startcode(unsigned long addr, unsigned int size)
+{
+	unsigned char *data;
+	unsigned int i = 0;
+
+	/* FIXME: optimize cache operation size */
+	mfc_mem_cache_inv((void *)addr, size);
+
+	/* FIXME: optimize matching algorithm */
+	data = (unsigned char *)addr;
+
+	for (i = 0; i < (size - MPEG4_START_CODE_PREFIX_SIZE); i++) {
+		if ((data[i] == 0x00) && (data[i + 1] == 0x00) && (data[i + 2] == 0x01))
+			return i;
+	}
+
+	return -1;
+}
+
+static int check_vcl(unsigned long addr, unsigned int size)
+{
+	return -1;
+}
+#endif
+
+#ifdef DUMP_STREAM
+static void mfc_fw_debug(void)
+{
+	mfc_err("============= MFC FW Debug (Ver: 0x%08x)  ================\n",
+			read_reg(0x58));
+	mfc_err("== (0x64: 0x%08x) (0x68: 0x%08x) (0xE4: 0x%08x) \
+			 (0xE8: 0x%08x)\n", read_reg(0x64), read_reg(0x68),
+			read_reg(0xe4), read_reg(0xe8));
+	mfc_err("== (0xF0: 0x%08x) (0xF4: 0x%08x) (0xF8: 0x%08x) \
+			 (0xFC: 0x%08x)\n", read_reg(0xf0), read_reg(0xf4),
+			read_reg(0xf8), read_reg(0xfc));
+}
+
+static void dump_stream(unsigned long address, unsigned int size)
+{
+	int i, j;
+	struct file *file;
+	loff_t pos = 0;
+	int fd;
+	unsigned long addr  = (unsigned long) phys_to_virt(address);
+	mm_segment_t old_fs;
+	char filename[] = "/data/mfc_decinit_instream.raw";
+
+	printk(KERN_INFO "---- start stream dump ----\n");
+	printk(KERN_INFO "size: 0x%04x\n", size);
+	for (i = 0; i < size; i += 16) {
+		mfc_dbg("0x%04x: ", i);
+
+		if ((size - i) >= 16) {
+			for (j = 0; j < 16; j++)
+				mfc_dbg("0x%02x ",
+					 (u8)(*(u8 *)(addr + i + j)));
+		} else {
+			for (j = 0; j < (size - i); j++)
+				mfc_dbg("0x%02x ",
+					 (u8)(*(u8 *)(addr + i + j)));
+		}
+		mfc_dbg("\n");
+	}
+	printk(KERN_INFO "---- end stream dump ----\n");
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	fd = sys_open(filename, O_WRONLY|O_CREAT, 0644);
+	if (fd >= 0) {
+		sys_write(fd, (u8 *)addr, size);
+		file = fget(fd);
+		if (file) {
+			vfs_write(file, (u8 *)addr, size, &pos);
+			fput(file);
+		}
+		sys_close(fd);
+	} else {
+		mfc_err("........Open fail : %d\n", fd);
+	}
+
+	set_fs(old_fs);
+}
+#endif
+
+/*
+ * [1] alloc_ctx_buf() implementations
+ */
+ static int alloc_ctx_buf(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_CTX_SIZE, ALIGN_2KB, MBT_CTX | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc context buffer\n");
+
+		return -1;
+	}
+
+	ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
+	ctx->ctxbufsize = alloc->size;
+
+	memset((void *)alloc->addr, 0, alloc->size);
+
+	mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+
+	return 0;
+}
+
+static int h264_alloc_ctx_buf(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_CTX_SIZE_L, ALIGN_2KB, MBT_CTX | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc context buffer\n");
+
+		return -1;
+	}
+
+	ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
+	ctx->ctxbufsize = alloc->size;
+
+	memset((void *)alloc->addr, 0, alloc->size);
+
+	mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+
+	return 0;
+}
+
+/*
+ * [2] alloc_desc_buf() implementations
+ */
+static int alloc_desc_buf(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	/* FIXME: size fixed? */
+	alloc = _mfc_alloc_buf(ctx, MFC_DESC_SIZE, ALIGN_2KB, MBT_DESC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc descriptor buffer\n");
+
+		return -1;
+	}
+
+	ctx->descbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
+	/* FIXME: size fixed? */
+	ctx->descbufsize = MFC_DESC_SIZE;
+
+	return 0;
+}
+
+/*
+ * [3] pre_seq_start() implementations
+ */
+static int pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	unsigned reg;
+
+	/* slice interface */
+	reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
+	if (dec_ctx->slice)
+		reg |= (1 << 31);
+	else
+		reg &= ~(1 << 31);
+	write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
+
+	return 0;
+}
+
+static int h264_pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	unsigned int reg;
+
+	pre_seq_start(ctx);
+
+	/* display delay */
+	reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
+	if (h264->dispdelay_en > 0) {
+		/* enable */
+		reg |= (1 << 30);
+		/* value */
+		reg &= ~(0x3FFF << 16);
+		reg |= ((h264->dispdelay_val & 0x3FFF) << 16);
+	} else {
+		/* disable & value clear */
+		reg &= ~(0x7FFF << 16);
+	}
+	write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
+
+	write_shm(ctx, h264->sei_parse, SEI_ENABLE);
+
+	return 0;
+}
+
+static int mpeg4_pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
+	unsigned int reg;
+
+	pre_seq_start(ctx);
+
+	/* loop filter, this register can be used by both decoders & encoders */
+	reg = read_reg(MFC_ENC_LF_CTRL);
+	if (mpeg4->postfilter)
+		reg |= (1 << 0);
+	else
+		reg &= ~(1 << 0);
+	write_reg(reg, MFC_ENC_LF_CTRL);
+
+	return 0;
+}
+
+static int fimv1_pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
+
+	pre_seq_start(ctx);
+
+	/* set width, height for FIMV1 */
+	write_reg(fimv1->width, MFC_SI_FIMV1_HRESOL);
+	write_reg(fimv1->height, MFC_SI_FIMV1_VRESOL);
+
+	return 0;
+}
+
+/*
+ * [4] post_seq_start() implementations
+ */
+static int post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	unsigned int shm;
+
+	/* CHKME: case of FIMV1 */
+	ctx->width = read_reg(MFC_SI_HRESOL);
+	ctx->height = read_reg(MFC_SI_VRESOL);
+
+	dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
+	dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
+
+	shm = read_shm(ctx, DISP_PIC_PROFILE);
+	dec_ctx->level = (shm >> 8) & 0xFF;
+	dec_ctx->profile = shm & 0x1F;
+
+	return 0;
+}
+
+static int h264_post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	unsigned int shm;
+
+	/*
+	post_seq_start(ctx);
+	*/
+	ctx->width = read_reg(MFC_SI_HRESOL);
+	ctx->height = read_reg(MFC_SI_VRESOL);
+
+	dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
+	dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
+
+	mfc_dbg("nummindpb: %d, numextradpb: %d\n", dec_ctx->nummindpb,
+			dec_ctx->numextradpb);
+
+	shm = read_shm(ctx, DISP_PIC_PROFILE);
+	dec_ctx->level = (shm >> 8) & 0xFF;
+	dec_ctx->profile = shm & 0x1F;
+
+	/* FIXME: consider it */
+	/*
+	h264->dispdelay_en > 0
+
+	if (dec_ctx->numtotaldpb < h264->dispdelay_val)
+		dec_ctx->numtotaldpb = h264->dispdelay_val;
+	*/
+
+	h264->crop_r_ofs = (read_shm(ctx, CROP_INFO1) >> 16) & 0xFFFF;
+	h264->crop_l_ofs = read_shm(ctx, CROP_INFO1) & 0xFFFF;
+	h264->crop_b_ofs = (read_shm(ctx, CROP_INFO2) >> 16) & 0xFFFF;
+	h264->crop_t_ofs = read_shm(ctx, CROP_INFO2) & 0xFFFF;
+
+	return 0;
+}
+
+static int mpeg4_post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
+	unsigned int shm;
+
+	/*
+	post_seq_start(ctx);
+	*/
+	ctx->width = read_reg(MFC_SI_HRESOL);
+	ctx->height = read_reg(MFC_SI_VRESOL);
+
+	dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
+	dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
+
+	shm = read_shm(ctx, DISP_PIC_PROFILE);
+	dec_ctx->level = (shm >> 8) & 0xFF;
+	dec_ctx->profile = shm & 0x1F;
+
+	mpeg4->aspect_ratio = read_shm(ctx, ASPECT_RATIO_INFO) & 0xF;
+	if (mpeg4->aspect_ratio == 0xF) {
+		shm = read_shm(ctx, EXTENDED_PAR);
+		mpeg4->ext_par_width = (shm >> 16) & 0xFFFF;
+		mpeg4->ext_par_height = shm & 0xFFFF;
+	} else {
+		mpeg4->ext_par_width = 0;
+		mpeg4->ext_par_height = 0;
+	}
+
+	return 0;
+}
+
+static int vc1_post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	unsigned int shm;
+
+	/*
+	post_seq_start(ctx);
+	*/
+	ctx->width = read_reg(MFC_SI_HRESOL);
+	ctx->height = read_reg(MFC_SI_VRESOL);
+
+	dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
+	dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
+
+	shm = read_shm(ctx, DISP_PIC_PROFILE);
+	dec_ctx->level = (shm >> 8) & 0xFF;
+	dec_ctx->profile = shm & 0x1F;
+
+	return 0;
+}
+
+static int fimv1_post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
+	unsigned int shm;
+
+	/*
+	post_seq_start(ctx);
+	*/
+	ctx->width = read_reg(MFC_SI_HRESOL);
+	ctx->height = read_reg(MFC_SI_VRESOL);
+
+	dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
+	dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
+
+	shm = read_shm(ctx, DISP_PIC_PROFILE);
+	dec_ctx->level = (shm >> 8) & 0xFF;
+	dec_ctx->profile = shm & 0x1F;
+
+	fimv1->aspect_ratio = read_shm(ctx, ASPECT_RATIO_INFO) & 0xF;
+	if (fimv1->aspect_ratio == 0xF) {
+		shm = read_shm(ctx, EXTENDED_PAR);
+		fimv1->ext_par_width = (shm >> 16) & 0xFFFF;
+		fimv1->ext_par_height = shm & 0xFFFF;
+	} else {
+		fimv1->ext_par_width = 0;
+		fimv1->ext_par_height = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * [5] set_init_arg() implementations
+ */
+static int set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
+
+	dec_init_arg->out_frm_width = ctx->width;
+	dec_init_arg->out_frm_height = ctx->height;
+	dec_init_arg->out_buf_width = ALIGN(ctx->width, ALIGN_W);
+	dec_init_arg->out_buf_height = ALIGN(ctx->height, ALIGN_H);
+
+	dec_init_arg->out_dpb_cnt = dec_ctx->numtotaldpb;
+
+	return 0;
+}
+
+static int h264_set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
+
+	set_init_arg(ctx, arg);
+
+	dec_init_arg->out_crop_right_offset = h264->crop_r_ofs;
+	dec_init_arg->out_crop_left_offset = h264->crop_l_ofs;
+	dec_init_arg->out_crop_bottom_offset = h264->crop_b_ofs;
+	dec_init_arg->out_crop_top_offset = h264->crop_t_ofs;
+
+	return 0;
+}
+
+static int mpeg4_set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	/*
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
+	struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
+	*/
+
+	set_init_arg(ctx, arg);
+
+	/*
+	dec_init_arg->out_aspect_ratio = mpeg4->aspect_ratio;
+	dec_init_arg->out_ext_par_width = mpeg4->ext_par_width;
+	dec_init_arg->out_ext_par_height = mpeg4->ext_par_height;
+	*/
+
+	return 0;
+}
+
+/*
+ * [6] set_codec_bufs() implementations
+ */
+static int set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+static int h264_set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_VERT_NB_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBIP_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_VERT_NB_IP_ADR);
+
+	return 0;
+}
+
+static int vc1_set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE3_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE2_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE1_ADR);
+
+	return 0;
+}
+
+static int mpeg4_set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_SYNPAR_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SP_ADR);
+
+	return 0;
+}
+
+static int h263_set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_free_buf_type(ctx->id, MBT_CODEC);
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
+
+	return 0;
+}
+
+/*
+ * [7] set_dpbs() implementations
+ */
+static int set_dpbs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+	int i;
+	unsigned int reg;
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+
+	/* width: 128B align, height: 32B align, size: 8KB align */
+	/* add some guard buffers to luma & chroma */
+	dec_ctx->lumasize = ALIGN(ctx->width + 24, ALIGN_W) * ALIGN(ctx->height + 16, ALIGN_H);
+	dec_ctx->lumasize = ALIGN(dec_ctx->lumasize, ALIGN_8KB);
+	dec_ctx->chromasize = ALIGN(ctx->width + 16, ALIGN_W) * ALIGN((ctx->height >> 1) + 4, ALIGN_H);
+	dec_ctx->chromasize = ALIGN(dec_ctx->chromasize, ALIGN_8KB);
+
+	for (i = 0; i < dec_ctx->numtotaldpb; i++) {
+		/*
+		 * allocate chroma buffer
+		 */
+#ifdef CONFIG_VIDEO_MFC5X_DEC_CHROMA_LUMA_4K_ALIGN
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, \
+					ALIGN_4KB, MBT_DPB | PORT_A);
+#else
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, ALIGN_2KB, MBT_DPB | PORT_A);
+#endif
+		if (alloc == NULL) {
+			mfc_free_buf_type(ctx->id, MBT_DPB);
+			mfc_err("failed alloc chroma buffer\n");
+
+			return -1;
+		}
+
+		/* clear first DPB chroma buffer, referrence buffer for
+		   vectors starting with p-frame */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		if ((i == 0) && (!ctx->drm_flag)) {
+#else
+		if (i == 0) {
+#endif
+			memset((void *)alloc->addr, 0x80, alloc->size);
+			mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+		}
+
+		/*
+		 * set chroma buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_CHROMA_ADR + (4 * i));
+
+		/*
+		 * allocate luma buffer
+		 */
+#ifdef CONFIG_VIDEO_MFC5X_DEC_CHROMA_LUMA_4K_ALIGN
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, \
+					ALIGN_4KB, MBT_DPB | PORT_B);
+#else
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_B);
+#endif
+		if (alloc == NULL) {
+			mfc_free_buf_type(ctx->id, MBT_DPB);
+			mfc_err("failed alloc luma buffer\n");
+
+			return -1;
+		}
+
+		/* clear first DPB luma buffer, referrence buffer for
+		   vectors starting with p-frame */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		if ((i == 0) && (!ctx->drm_flag)) {
+#else
+		if (i == 0) {
+#endif
+			memset((void *)alloc->addr, 0x0, alloc->size);
+			mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+		}
+
+		/*
+		 * set luma buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_LUMA_ADR + (4 * i));
+	}
+
+	write_shm(ctx, dec_ctx->lumasize, ALLOCATED_LUMA_DPB_SIZE);
+	write_shm(ctx, dec_ctx->chromasize, ALLOCATED_CHROMA_DPB_SIZE);
+	write_shm(ctx, 0, ALLOCATED_MV_SIZE);
+
+	/* set DPB number */
+	reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
+	reg &= ~(0x3FFF);
+	reg |= dec_ctx->numtotaldpb;
+	write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
+
+	return 0;
+}
+
+static int h264_set_dpbs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+	int i;
+	unsigned int reg;
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+
+	/* width: 128B align, height: 32B align, size: 8KB align */
+	dec_ctx->lumasize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height, ALIGN_H);
+	dec_ctx->lumasize = ALIGN(dec_ctx->lumasize, ALIGN_8KB);
+	dec_ctx->chromasize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height >> 1, ALIGN_H);
+	dec_ctx->chromasize = ALIGN(dec_ctx->chromasize, ALIGN_8KB);
+
+	h264->mvsize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height >> 2, ALIGN_H);
+	h264->mvsize = ALIGN(h264->mvsize, ALIGN_8KB);
+
+	for (i = 0; i < dec_ctx->numtotaldpb; i++) {
+		/*
+		 * allocate chroma buffer
+		 */
+#ifdef CONFIG_VIDEO_MFC5X_DEC_CHROMA_LUMA_4K_ALIGN
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, \
+					ALIGN_4KB, MBT_DPB | PORT_A);
+#else
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, ALIGN_2KB, MBT_DPB | PORT_A);
+#endif
+
+
+		if (alloc == NULL) {
+			mfc_free_buf_type(ctx->id, MBT_DPB);
+			mfc_err("failed alloc chroma buffer\n");
+
+			return -1;
+		}
+
+		/* clear last DPB chroma buffer, referrence buffer for
+		   vectors starting with p-frame */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		if ((i == (dec_ctx->numtotaldpb - 1)) && (!ctx->drm_flag)) {
+#else
+		if (i == (dec_ctx->numtotaldpb - 1)) {
+#endif
+			memset((void *)alloc->addr, 0x80, alloc->size);
+			mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+		}
+
+		/*
+		 * set chroma buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_CHROMA_ADR + (4 * i));
+
+		/*
+		 * allocate luma buffer
+		 */
+#ifdef CONFIG_VIDEO_MFC5X_DEC_CHROMA_LUMA_4K_ALIGN
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, \
+					ALIGN_4KB, MBT_DPB | PORT_B);
+#else
+		alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_B);
+#endif
+		if (alloc == NULL) {
+			mfc_free_buf_type(ctx->id, MBT_DPB);
+			mfc_err("failed alloc luma buffer\n");
+
+			return -1;
+		}
+
+		/* clear last DPB luma buffer, referrence buffer for
+		   vectors starting with p-frame */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		if ((i == (dec_ctx->numtotaldpb - 1)) && (!ctx->drm_flag)) {
+#else
+		if (i == (dec_ctx->numtotaldpb - 1)) {
+#endif
+			memset((void *)alloc->addr, 0x0, alloc->size);
+			mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+		}
+
+		/*
+		 * set luma buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_LUMA_ADR + (4 * i));
+
+		/*
+		 * allocate mv buffer
+		 */
+		alloc = _mfc_alloc_buf(ctx, h264->mvsize, ALIGN_2KB, MBT_DPB | PORT_B);
+		if (alloc == NULL) {
+			mfc_free_buf_type(ctx->id, MBT_DPB);
+			mfc_err("failed alloc mv buffer\n");
+
+			return -1;
+		}
+		/*
+		 * set mv buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_MV_ADR + (4 * i));
+	}
+
+	write_shm(ctx, dec_ctx->lumasize, ALLOCATED_LUMA_DPB_SIZE);
+	write_shm(ctx, dec_ctx->chromasize, ALLOCATED_CHROMA_DPB_SIZE);
+
+	write_shm(ctx, h264->mvsize, ALLOCATED_MV_SIZE);
+
+	/* set DPB number */
+	reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
+	reg &= ~(0x3FFF);
+	reg |= dec_ctx->numtotaldpb;
+	write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
+
+	return 0;
+}
+
+/*
+ * [8] pre_frame_start() implementations
+ */
+static int pre_frame_start(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+/*
+ * [9] post_frame_start() implementations
+ */
+static int post_frame_start(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+static int h264_post_frame_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	unsigned int shm;
+
+	/* h264->sei_parse */
+	h264->fp.available = read_shm(ctx, FRAME_PACK_SEI_AVAIL) & 0x1;
+
+	if (h264->fp.available) {
+		h264->fp.arrangement_id = read_shm(ctx, FRAME_PACK_ARRGMENT_ID);
+
+		shm = read_shm(ctx, FRAME_PACK_DEC_INFO);
+		h264->fp.arrangement_cancel_flag =	(shm >>  0) & 0x1;
+		h264->fp.arrangement_type =		(shm >>  1) & 0x7F;
+		h264->fp.quincunx_sampling_flag =	(shm >>  8) & 0x1;
+		h264->fp.content_interpretation_type =	(shm >>  9) & 0x3F;
+		h264->fp.spatial_flipping_flag =	(shm >> 15) & 0x1;
+		h264->fp.frame0_flipped_flag =		(shm >> 16) & 0x1;
+		h264->fp.field_views_flag =		(shm >> 17) & 0x1;
+		h264->fp.current_frame_is_frame0_flag =	(shm >> 18) & 0x1;
+
+		shm = read_shm(ctx, FRAME_PACK_GRID_POS);
+		h264->fp.frame0_grid_pos_x = (shm >>  0) & 0xF;
+		h264->fp.frame0_grid_pos_y = (shm >>  4) & 0xF;
+		h264->fp.frame1_grid_pos_x = (shm >>  8) & 0xF;
+		h264->fp.frame1_grid_pos_y = (shm >> 12) & 0xF;
+	} else {
+		memset((void *)&h264->fp, 0x00, sizeof(struct mfc_frame_packing));
+	}
+
+	return 0;
+}
+
+/*
+ * [10] multi_frame_start() implementations
+ */
+static int multi_data_frame(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+static int mpeg4_multi_data_frame(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
+
+	if (!mpeg4->packedpb)
+		return 0;
+
+	/* FIXME: I_FRAME is valid? */
+	if ((dec_ctx->decframetype == DEC_FRM_I) || (dec_ctx->decframetype == DEC_FRM_P)) {
+
+	}
+
+	return 0;
+}
+
+/*
+ * [11] set_exe_arg() implementations
+ */
+static int set_exe_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	/*
+	struct mfc_dec_exe_arg *dec_exe_arg = (struct mfc_dec_exe_arg *)arg;
+	*/
+
+	return 0;
+}
+
+/*
+ * [12] get_codec_cfg() implementations
+ */
+static int get_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	/*struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;*/
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+
+	int ret = 0;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	/*
+	MFC_DEC_GETCONF_CRC_DATA	= DEC_GET,
+	MFC_DEC_GETCONF_BUF_WIDTH_HEIGHT
+	MFC_DEC_GETCONF_FRAME_TAG,
+	MFC_DEC_GETCONF_PIC_TIME,
+
+	MFC_DEC_GETCONF_ASPECT_RATIO:
+	MFC_DEC_GETCONF_EXTEND_PAR:
+	*/
+
+	switch (type) {
+	case MFC_DEC_GETCONF_CRC_DATA:
+		usercfg->basic.values[0] = 0x12;
+		usercfg->basic.values[1] = 0x34;
+		usercfg->basic.values[2] = 0x56;
+		usercfg->basic.values[3] = 0x78;
+
+		break;
+
+	default:
+		mfc_dbg("not common cfg, try to codec specific: 0x%08x\n", type);
+		ret = 1;
+
+		break;
+	}
+
+	return ret;
+}
+
+static int h264_get_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret = 0;
+
+	mfc_dbg("type: 0x%08x", type);
+	ret = get_codec_cfg(ctx, type, arg);
+	if (ret <= 0)
+		return ret;
+
+	switch (type) {
+	case MFC_DEC_GETCONF_FRAME_PACKING:
+		if (ctx->state < INST_STATE_EXE) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		memcpy(&usercfg->frame_packing, &h264->fp, sizeof(struct mfc_frame_packing));
+
+		break;
+
+	default:
+		mfc_err("invalid get config type: 0x%08x\n", type);
+		ret = -2;
+
+		break;
+	}
+
+	return ret;
+}
+/*
+ * [13] set_codec_cfg() implementations
+ */
+static int set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret = 0;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	/*
+	MFC_DEC_SETCONF_FRAME_TAG,
+	...
+	*/
+
+	switch (type) {
+	/*
+	case MFC_DEC_SETCONF_EXTRA_BUFFER_NUM:
+		if (ctx->state >= INST_STATE_INIT)
+			return MFC_STATE_INVALID;
+
+		if ((usercfg->basic.values[0] >= 0) && (usercfg->basic.values[0] <= MFC_MAX_EXTRA_DPB)) {
+			dec_ctx->numextradpb = usercfg->basic.values[0];
+		} else {
+			dec_ctx->numextradpb = MFC_MAX_EXTRA_DPB;
+			mfc_warn("invalid extra dpb buffer number: %d", usercfg->basic.values[0]);
+			mfc_warn("set %d by default", MFC_MAX_EXTRA_DPB);
+		}
+
+		break;
+	*/
+	case MFC_DEC_SETCONF_IS_LAST_FRAME:
+		mfc_dbg("ctx->state: 0x%08x", ctx->state);
+
+		if (ctx->state < INST_STATE_EXE) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		if (usercfg->basic.values[0] > 0)
+			dec_ctx->lastframe = 1;
+		else
+			dec_ctx->lastframe = 0;
+
+		break;
+	/*
+	case MFC_DEC_SETCONF_SLICE_ENABLE:
+		if (ctx->state >= INST_STATE_INIT)
+			return MFC_STATE_INVALID;
+
+		if (usercfg->basic.values[0] > 0)
+			dec_ctx->slice = 1;
+		else
+			dec_ctx->slice = 0;
+
+		break;
+	*/
+	/*
+	case MFC_DEC_SETCONF_CRC_ENABLE:
+		if (ctx->state >= INST_STATE_INIT)
+			return MFC_STATE_INVALID;
+
+		if (usercfg->basic.values[0] > 0)
+			dec_ctx->crc = 1;
+		else
+			dec_ctx->crc = 0;
+
+		break;
+	*/
+	case MFC_DEC_SETCONF_DPB_FLUSH:
+		if (ctx->state < INST_STATE_EXE) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		if (usercfg->basic.values[0] > 0) {
+			dec_ctx->dpbflush = 1;
+		}
+		break;
+
+	default:
+		mfc_dbg("not common cfg, try to codec specific: 0x%08x\n", type);
+		ret = 1;
+
+		break;
+	}
+
+	return ret;
+}
+
+static int h264_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	ret = set_codec_cfg(ctx, type, arg);
+	if (ret <= 0)
+		return ret;
+
+	ret = 0;
+
+	switch (type) {
+	case MFC_DEC_SETCONF_DISPLAY_DELAY:
+		if (ctx->state >= INST_STATE_INIT) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		h264->dispdelay_en = 1;
+		if ((usercfg->basic.values[0] >= 0) && (usercfg->basic.values[0] <= MFC_MAX_DISP_DELAY)) {
+			h264->dispdelay_val = usercfg->basic.values[0];
+		} else {
+			h264->dispdelay_val = MFC_MAX_DISP_DELAY;
+			mfc_warn("invalid diplay delay count: %d", usercfg->basic.values[0]);
+			mfc_warn("set %d by default", MFC_MAX_DISP_DELAY);
+		}
+
+		break;
+
+	case MFC_DEC_SETCONF_SEI_PARSE:
+		mfc_dbg("ctx->state: 0x%08x", ctx->state);
+
+		if (ctx->state >= INST_STATE_INIT) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		if (usercfg->basic.values[0] > 0)
+			h264->sei_parse = 1;
+		else
+			h264->sei_parse = 0;
+
+		break;
+
+	default:
+		mfc_err("invalid set cfg type: 0x%08x\n", type);
+		ret = -2;
+
+		break;
+	}
+
+	return ret;
+}
+
+static int mpeg4_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	ret = set_codec_cfg(ctx, type, arg);
+	if (ret <= 0)
+		return ret;
+
+	ret = 0;
+
+	switch (type) {
+	case MFC_DEC_SETCONF_POST_ENABLE:
+		if (ctx->state >= INST_STATE_INIT)
+			return MFC_STATE_INVALID;
+
+		if (usercfg->basic.values[0] > 0)
+			mpeg4->postfilter = 1;
+		else
+			mpeg4->postfilter = 0;
+
+		break;
+/* JYSHIN
+	case MFC_DEC_SETCONF_PACKEDPB:
+		if (ctx->state < INST_STATE_OPEN)
+			return -1;
+
+		if (usercfg->basic.values[0] > 0)
+			mpeg4->packedpb = 1;
+		else
+			mpeg4->packedpb = 1;
+
+		break;
+*/
+	default:
+		mfc_err("invalid set cfg type: 0x%08x\n", type);
+		ret = -2;
+
+		break;
+	}
+
+	return ret;
+}
+
+static int fimv1_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	ret = set_codec_cfg(ctx, type, arg);
+	if (ret <= 0)
+		return ret;
+
+	ret = 0;
+
+	switch (type) {
+	case MFC_DEC_SETCONF_FIMV1_WIDTH_HEIGHT:
+		if (ctx->state >= INST_STATE_INIT)
+			return MFC_STATE_INVALID;
+
+		fimv1->width = usercfg->basic.values[0];
+		fimv1->height = usercfg->basic.values[1];
+
+		break;
+/* JYSHIN
+	case MFC_DEC_SETCONF_PACKEDPB:
+		if (ctx->state < INST_STATE_OPEN)
+			return -1;
+
+		if (usercfg->basic.[0] > 0)
+			fimv1->packedpb = 1;
+		else
+			fimv1->packedpb = 1;
+
+		break;
+*/
+	default:
+		mfc_err("invalid set cfg type: 0x%08x\n", type);
+		ret = -2;
+
+		break;
+	}
+
+	return ret;
+}
+
+static struct mfc_dec_info unknown_dec = {
+	.name		= "UNKNOWN",
+	.codectype	= UNKNOWN_TYPE,
+	.codecid	= -1,
+	.d_priv_size	= 0,
+	/*
+	 * The unknown codec operations will be not call,
+	 * unused default operations raise build warning.
+	 */
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= pre_frame_start,
+		.post_frame_start	= post_frame_start,
+		.multi_data_frame	= multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info h264_dec = {
+	.name		= "H264",
+	.codectype	= H264_DEC,
+	.codecid	= 0,
+	.d_priv_size	= sizeof(struct mfc_dec_h264),
+	.c_ops		= {
+		.alloc_ctx_buf		= h264_alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= h264_pre_seq_start,
+		.post_seq_start		= h264_post_seq_start,
+		.set_init_arg		= h264_set_init_arg,
+		.set_codec_bufs		= h264_set_codec_bufs,
+		.set_dpbs		= h264_set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= h264_post_frame_start,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= h264_get_codec_cfg,
+		.set_codec_cfg		= h264_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info vc1_dec = {
+	.name		= "VC1",
+	.codectype	= VC1_DEC,
+	.codecid	= 1,
+	.d_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= vc1_post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= vc1_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info mpeg4_dec = {
+	.name		= "MPEG4",
+	.codectype	= MPEG4_DEC,
+	.codecid	= 2,
+	.d_priv_size	= sizeof(struct mfc_dec_mpeg4),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= mpeg4_pre_seq_start,
+		.post_seq_start		= mpeg4_post_seq_start,
+		.set_init_arg		= mpeg4_set_init_arg,
+		.set_codec_bufs		= mpeg4_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,	/* FIXME: mpeg4_multi_data_frame */
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= mpeg4_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info xvid_dec = {
+	.name           = "XVID",
+	.codectype      = XVID_DEC,
+	.codecid        = 2,
+	.d_priv_size	= sizeof(struct mfc_dec_mpeg4),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= mpeg4_pre_seq_start,
+		.post_seq_start		= mpeg4_post_seq_start,
+		.set_init_arg		= mpeg4_set_init_arg,
+		.set_codec_bufs		= mpeg4_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,	/* FIXME: mpeg4_multi_data_frame */
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= mpeg4_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info mpeg1_dec = {
+	.name		= "MPEG1",
+	.codectype	= MPEG1_DEC,
+	.codecid	= 3,
+	.d_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= NULL,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info mpeg2_dec = {
+	.name		= "MPEG2",
+	.codectype	= MPEG2_DEC,
+	.codecid	= 3,
+	.d_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= NULL,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info h263_dec = {
+	.name		= "H263",
+	.codectype	= H263_DEC,
+	.codecid	= 4,
+	.d_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= h263_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info vc1rcv_dec = {
+	.name		= "VC1RCV",
+	.codectype	= VC1RCV_DEC,
+	.codecid	= 5,
+	.d_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= vc1_post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= vc1_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= NULL,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info fimv1_dec = {
+	.name		= "FIMV1",
+	.codectype	= FIMV1_DEC,
+	.codecid	= 6,
+	.d_priv_size	= sizeof(struct mfc_dec_fimv1),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= fimv1_pre_seq_start,
+		.post_seq_start		= fimv1_post_seq_start,
+		.set_init_arg		= set_init_arg,		/* FIMXE */
+		.set_codec_bufs		= mpeg4_set_codec_bufs, /* FIXME */
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= mpeg4_multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= fimv1_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info fimv2_dec = {
+	.name		= "FIMV2",
+	.codectype	= FIMV2_DEC,
+	.codecid	= 7,
+	.d_priv_size	= sizeof(struct mfc_dec_mpeg4),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= mpeg4_pre_seq_start,
+		.post_seq_start		= mpeg4_post_seq_start,
+		.set_init_arg		= mpeg4_set_init_arg,
+		.set_codec_bufs		= mpeg4_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= mpeg4_multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= mpeg4_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info fimv3_dec = {
+	.name		= "FIMV3",
+	.codectype	= FIMV3_DEC,
+	.codecid	= 8,
+	.d_priv_size	= sizeof(struct mfc_dec_mpeg4),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= mpeg4_pre_seq_start,
+		.post_seq_start		= mpeg4_post_seq_start,
+		.set_init_arg		= mpeg4_set_init_arg,
+		.set_codec_bufs		= mpeg4_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= mpeg4_multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= mpeg4_set_codec_cfg,
+	},
+};
+
+static struct mfc_dec_info fimv4_dec = {
+	.name		= "FIMV4",
+	.codectype	= FIMV4_DEC,
+	.codecid	= 9,
+	.d_priv_size	= sizeof(struct mfc_dec_mpeg4),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= alloc_desc_buf,
+		.pre_seq_start		= mpeg4_pre_seq_start,
+		.post_seq_start		= mpeg4_post_seq_start,
+		.set_init_arg		= mpeg4_set_init_arg,
+		.set_codec_bufs		= mpeg4_set_codec_bufs,
+		.set_dpbs		= set_dpbs,
+		.pre_frame_start	= NULL,
+		.post_frame_start	= NULL,
+		.multi_data_frame	= mpeg4_multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= mpeg4_set_codec_cfg,
+	},
+};
+
+static int CheckMPEG4StartCode(unsigned char *src_mem, unsigned int remainSize)
+{
+    unsigned int index = 0;
+
+	for (index = 0; index < remainSize-3; index++) {
+		if ((src_mem[index] == 0x00) && (src_mem[index+1] == 0x00) &&
+				(src_mem[index+2] == 0x01))
+			return index;
+	}
+
+	return -1;
+}
+
+static int CheckDecStartCode(unsigned char *src_mem,
+				unsigned int nstreamSize,
+				SSBSIP_MFC_CODEC_TYPE nCodecType)
+{
+	unsigned int	index = 0;
+	/* Check Start Code within "isearchSize" bytes */
+	unsigned int	isearchSize = 20;
+	unsigned int	nShift = 0;
+	unsigned char	nFlag = 0xFF;
+
+	if (nCodecType == H263_DEC) {
+		nFlag = 0x08;
+		nShift = 4;
+	} else if (nCodecType == MPEG4_DEC) {
+		nFlag = 0x01;
+		nShift = 0;
+	} else if (nCodecType == H264_DEC) {
+		nFlag = 0x01;
+		nShift = 0;
+	} else
+		nFlag = 0xFF;
+
+	/* Last frame detection from user */
+	if (nstreamSize == 0)
+		nFlag = 0xFF;
+
+	if (nFlag == 0xFF)
+		return 0;
+
+	if (nstreamSize > 3) {
+		if (nstreamSize > isearchSize) {
+			for (index = 0; index < isearchSize-3; index++) {
+				if ((src_mem[index] == 0x00) &&
+					(src_mem[index+1] == 0x00) &&
+					((src_mem[index+2] >> nShift) == nFlag))
+					return index;
+			}
+		} else {
+			for (index = 0; index < nstreamSize - 3; index++) {
+				if ((src_mem[index] == 0x00) &&
+					(src_mem[index+1] == 0x00) &&
+					((src_mem[index+2] >> nShift) == nFlag))
+					return index;
+			}
+		}
+	}
+
+	return -1;
+}
+
+void mfc_init_decoders(void)
+{
+	list_add_tail(&unknown_dec.list, &mfc_decoders);
+
+	list_add_tail(&h264_dec.list, &mfc_decoders);
+	list_add_tail(&vc1_dec.list, &mfc_decoders);
+	list_add_tail(&mpeg4_dec.list, &mfc_decoders);
+	list_add_tail(&xvid_dec.list, &mfc_decoders);
+	list_add_tail(&mpeg1_dec.list, &mfc_decoders);
+	list_add_tail(&mpeg2_dec.list, &mfc_decoders);
+	list_add_tail(&h263_dec.list, &mfc_decoders);
+	list_add_tail(&vc1rcv_dec.list, &mfc_decoders);
+	list_add_tail(&fimv1_dec.list, &mfc_decoders);
+	list_add_tail(&fimv2_dec.list, &mfc_decoders);
+	list_add_tail(&fimv3_dec.list, &mfc_decoders);
+	list_add_tail(&fimv4_dec.list, &mfc_decoders);
+
+	/* FIXME: 19, 20 */
+}
+
+static int mfc_set_decoder(struct mfc_inst_ctx *ctx, SSBSIP_MFC_CODEC_TYPE codectype)
+{
+	struct list_head *pos;
+	struct mfc_dec_info *decoder;
+	struct mfc_dec_ctx *dec_ctx;
+
+	ctx->codecid = -1;
+
+	/* find and set codec private */
+	list_for_each(pos, &mfc_decoders) {
+		decoder = list_entry(pos, struct mfc_dec_info, list);
+
+		if (decoder->codectype == codectype) {
+			if (decoder->codecid < 0)
+				break;
+
+			/* Allocate Decoder context memory */
+			dec_ctx = kzalloc(sizeof(struct mfc_dec_ctx), GFP_KERNEL);
+			if (!dec_ctx) {
+				mfc_err("failed to allocate codec private\n");
+				return -ENOMEM;
+			}
+			ctx->c_priv = dec_ctx;
+
+			/* Allocate Decoder context private memory */
+			dec_ctx->d_priv = kzalloc(decoder->d_priv_size, GFP_KERNEL);
+			if (!dec_ctx->d_priv) {
+				mfc_err("failed to allocate decoder private\n");
+				kfree(dec_ctx);
+				ctx->c_priv = NULL;
+				return -ENOMEM;
+			}
+
+			ctx->codecid = decoder->codecid;
+			ctx->type = DECODER;
+			ctx->c_ops = (struct codec_operations *)&decoder->c_ops;
+
+			break;
+		}
+	}
+
+	if (ctx->codecid < 0)
+		mfc_err("couldn't find proper decoder codec type: %d\n", codectype);
+
+	return ctx->codecid;
+}
+
+static void mfc_set_stream_info(
+	struct mfc_inst_ctx *ctx,
+	unsigned int addr,
+	unsigned int size,
+	unsigned int ofs)
+{
+
+	if (ctx->buf_cache_type == CACHE) {
+		flush_all_cpu_caches();
+		outer_flush_all();
+	}
+
+	write_reg(addr, MFC_SI_CH1_ES_ADR);
+	write_reg(size, MFC_SI_CH1_ES_SIZE);
+
+	/* FIXME: IOCTL_MFC_GET_IN_BUF size */
+	write_reg(MFC_CPB_SIZE, MFC_SI_CH1_CPB_SIZE);
+
+	write_reg(ctx->descbufofs, MFC_SI_CH1_DESC_ADR);
+	write_reg(ctx->descbufsize, MFC_SI_CH1_DESC_SIZE);
+
+	/* FIXME: right position */
+	write_shm(ctx, ofs, START_BYTE_NUM);
+}
+
+int mfc_init_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
+{
+	struct mfc_dec_init_arg *init_arg = (struct mfc_dec_init_arg *)args;
+	struct mfc_dec_ctx *dec_ctx = NULL;
+	struct mfc_pre_cfg *precfg;
+	struct list_head *pos, *nxt;
+	int ret;
+	long mem_ofs;
+
+	ret = mfc_set_decoder(ctx, init_arg->in_codec_type);
+	if (ret < 0) {
+		mfc_err("failed to setup decoder codec\n");
+		ret = MFC_DEC_INIT_FAIL;
+		goto err_codec_setup;
+	}
+
+	dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+
+	dec_ctx->streamaddr = init_arg->in_strm_buf;
+	dec_ctx->streamsize = init_arg->in_strm_size;
+
+	mfc_dbg("stream size: %d", init_arg->in_strm_size);
+
+	dec_ctx->crc = init_arg->in_crc;
+	dec_ctx->pixelcache = init_arg->in_pixelcache;
+	dec_ctx->slice = 0;
+	mfc_warn("Slice Mode disabled forcefully\n");
+	dec_ctx->numextradpb = init_arg->in_numextradpb;
+	dec_ctx->dpbflush = 0;
+	dec_ctx->ispackedpb = init_arg->in_packed_PB;
+
+	/*
+	 * assign pre configuration values to instance context
+	 */
+	list_for_each_safe(pos, nxt, &ctx->presetcfgs) {
+		precfg = list_entry(pos, struct mfc_pre_cfg, list);
+
+		if (ctx->c_ops->set_codec_cfg) {
+			ret = ctx->c_ops->set_codec_cfg(ctx, precfg->type, precfg->values);
+			if (ret < 0)
+				mfc_warn("cannot set preset config type: 0x%08x: %d",
+					precfg->type, ret);
+		}
+	}
+
+	mfc_set_inst_state(ctx, INST_STATE_SETUP);
+
+	/*
+	 * allocate context buffer
+	 */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if ((!ctx->drm_flag) && (ctx->c_ops->alloc_ctx_buf)) {
+#else
+	if (ctx->c_ops->alloc_ctx_buf) {
+#endif
+		if (ctx->c_ops->alloc_ctx_buf(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_ctx_buf;
+		}
+	}
+
+	/* [crc, pixelcache] */
+	ret = mfc_cmd_inst_open(ctx);
+	if (ret < 0)
+		goto err_inst_open;
+
+	mfc_set_inst_state(ctx, INST_STATE_OPEN);
+
+	if (init_shm(ctx) < 0) {
+		ret = MFC_DEC_INIT_FAIL;
+		goto err_shm_init;
+	}
+
+	/*
+	 * allocate descriptor buffer
+	 */
+	if (ctx->c_ops->alloc_desc_buf) {
+		if (ctx->c_ops->alloc_desc_buf(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_desc_buf;
+		}
+	}
+
+	/*
+	 * execute pre sequence start operation
+	 * [slice]
+	 */
+	if (ctx->c_ops->pre_seq_start) {
+		if (ctx->c_ops->pre_seq_start(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_pre_seq;
+		}
+	}
+
+	/* FIXME: move to pre_seq_start */
+	mem_ofs = mfc_mem_ext_ofs(dec_ctx->streamaddr, dec_ctx->streamsize, PORT_A);
+	if (mem_ofs < 0) {
+		ret = MFC_DEC_INIT_FAIL;
+		goto err_mem_ofs;
+	} else  {
+		mfc_set_stream_info(ctx, mem_ofs >> 11, dec_ctx->streamsize, 0);
+	}
+
+	ret = mfc_cmd_seq_start(ctx);
+	if (ret < 0)
+		goto err_seq_start;
+
+	/* [numextradpb] */
+	if (ctx->c_ops->post_seq_start) {
+		if (ctx->c_ops->post_seq_start(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_post_seq;
+		}
+	}
+
+	if (ctx->height > MAX_VER_SIZE) {
+		if (ctx->height > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_chk_res;
+		}
+
+		if (ctx->width > MAX_VER_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_chk_res;
+		}
+	} else {
+		if (ctx->width > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_chk_res;
+		}
+	}
+
+	if (ctx->c_ops->set_init_arg) {
+		if (ctx->c_ops->set_init_arg(ctx, (void *)init_arg) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_set_arg;
+		}
+	}
+
+	if (dec_ctx->numtotaldpb < 7)
+		dec_ctx->numtotaldpb = 7;
+
+	mfc_dbg("H: %d, W: %d, DPB_Count: %d", ctx->width, ctx->height,
+		dec_ctx->numtotaldpb);
+
+#if defined(CONFIG_BUSFREQ)
+#if defined(CONFIG_CPU_EXYNOS4210)
+	/* Fix MFC & Bus Frequency for better performance */
+	if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
+		exynos4_busfreq_lock(DVFS_LOCK_ID_MFC, BUS_L1);
+		mfc_dbg("Bus FREQ locked to L1\n");
+	}
+	atomic_inc(&ctx->dev->busfreq_lock_cnt);
+	ctx->busfreq_flag = true;
+#else
+	/* Lock MFC & Bus FREQ for high resolution */
+	if (ctx->width >= MAX_HOR_RES || ctx->height >= MAX_VER_RES) {
+		if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
+			exynos4_busfreq_lock(DVFS_LOCK_ID_MFC, BUS_L0);
+			mfc_dbg("Bus FREQ locked to L0\n");
+		}
+
+		atomic_inc(&ctx->dev->busfreq_lock_cnt);
+		ctx->busfreq_flag = true;
+	}
+#endif
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	if ((ctx->width >= 1280 && ctx->height >= 720)
+		|| (ctx->width >= 720 && ctx->height >= 1280)) {
+		if (atomic_read(&ctx->dev->cpufreq_lock_cnt) == 0) {
+			if (0 == ctx->dev->cpufreq_level) /* 500MHz */
+				exynos_cpufreq_get_level(500000, &ctx->dev->cpufreq_level);
+			exynos_cpufreq_lock(DVFS_LOCK_ID_MFC, ctx->dev->cpufreq_level);
+			mfc_dbg("[%s] CPU Freq Locked 500MHz!\n", __func__);
+		}
+		atomic_inc(&ctx->dev->cpufreq_lock_cnt);
+		ctx->cpufreq_flag = true;
+	}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	if (HD_MOVIE_SIZE_MULTIPLY_WIDTH_HEIGHT > (ctx->width * ctx->height)) {
+		if (atomic_read(&ctx->dev->dmcthreshold_lock_cnt) == 0) {
+			mfc_info("Implement set dmc_max_threshold\n");
+			if (soc_is_exynos4212()) {
+				dmc_max_threshold =
+					EXYNOS4212_DMC_MAX_THRESHOLD + 5;
+			} else if (soc_is_exynos4412()) {
+				dmc_max_threshold =
+					EXYNOS4412_DMC_MAX_THRESHOLD + 5;
+			} else {
+				pr_err("Unsupported model.\n");
+				return -EINVAL;
+			}
+		}
+		atomic_inc(&ctx->dev->dmcthreshold_lock_cnt);
+		ctx->dmcthreshold_flag = true;
+	}
+#endif
+	/*
+	 * allocate & set codec buffers
+	 */
+	if (ctx->c_ops->set_codec_bufs) {
+		if (ctx->c_ops->set_codec_bufs(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_codec_bufs;
+		}
+	}
+
+	/*
+	 * allocate & set DPBs
+	 */
+	if (ctx->c_ops->set_dpbs) {
+		if (ctx->c_ops->set_dpbs(ctx) < 0) {
+			ret = MFC_DEC_INIT_FAIL;
+			goto err_dpbs_set;
+		}
+	}
+
+	ret = mfc_cmd_init_buffers(ctx);
+	if (ret < 0)
+		goto err_buf_init;
+
+	mfc_set_inst_state(ctx, INST_STATE_INIT);
+
+	while (!list_empty(&ctx->presetcfgs)) {
+		precfg = list_entry((&ctx->presetcfgs)->next,
+				struct mfc_pre_cfg, list);
+
+		mfc_dbg("remove used preset config [0x%08x]\n",
+				precfg->type);
+
+		list_del(&precfg->list);
+		kfree(precfg);
+	}
+	INIT_LIST_HEAD(&ctx->presetcfgs);
+
+	mfc_print_buf();
+
+	return MFC_OK;
+
+err_buf_init:
+	mfc_free_buf_type(ctx->id, MBT_DPB);
+
+err_dpbs_set:
+	mfc_free_buf_type(ctx->id, MBT_CODEC);
+
+err_codec_bufs:
+#if defined(CONFIG_BUSFREQ)
+	/* Release MFC & Bus Frequency lock for High resolution */
+	if (ctx->busfreq_flag == true) {
+		atomic_dec(&ctx->dev->busfreq_lock_cnt);
+		ctx->busfreq_flag = false;
+
+		if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
+			exynos4_busfreq_lock_free(DVFS_LOCK_ID_MFC);
+			mfc_dbg("Bus FREQ released\n");
+		}
+	}
+#endif
+
+err_set_arg:
+err_chk_res:
+err_post_seq:
+err_seq_start:
+#ifdef DUMP_STREAM
+	mfc_fw_debug();
+	dump_stream(dec_ctx->streamaddr, dec_ctx->streamsize);
+#endif
+
+err_mem_ofs:
+err_pre_seq:
+	mfc_free_buf_type(ctx->id, MBT_DESC);
+
+err_desc_buf:
+	mfc_free_buf_type(ctx->id, MBT_SHM);
+
+	ctx->shm = NULL;
+	ctx->shmofs = 0;
+
+err_shm_init:
+	mfc_cmd_inst_close(ctx);
+
+	ctx->state = INST_STATE_SETUP;
+
+err_inst_open:
+	mfc_free_buf_type(ctx->id, MBT_CTX);
+
+err_ctx_buf:
+	if (dec_ctx->d_priv)
+		kfree(dec_ctx->d_priv);
+
+	kfree(dec_ctx);
+	ctx->c_priv = NULL;
+
+	ctx->codecid = -1;
+	ctx->type = 0;
+	ctx->c_ops = NULL;
+
+	ctx->state = INST_STATE_CREATE;
+
+err_codec_setup:
+	return ret;
+}
+
+int mfc_change_resolution(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg)
+{
+	int ret;
+
+	mfc_free_buf_type(ctx->id, MBT_DPB);
+
+	ret = mfc_cmd_seq_start(ctx);
+	if (ret < 0)
+		return ret;
+
+	/* [numextradpb] */
+	if (ctx->c_ops->post_seq_start) {
+		if (ctx->c_ops->post_seq_start(ctx) < 0)
+			return MFC_DEC_INIT_FAIL;
+	}
+
+	if (ctx->height > MAX_VER_SIZE) {
+		if (ctx->height > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			return MFC_DEC_INIT_FAIL;
+		}
+
+		if (ctx->width > MAX_VER_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			return MFC_DEC_INIT_FAIL;
+		}
+	} else {
+		if (ctx->width > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			return MFC_DEC_INIT_FAIL;
+		}
+	}
+
+	exe_arg->out_img_width = ctx->width;
+	exe_arg->out_img_height = ctx->height;
+	exe_arg->out_buf_width = ALIGN(ctx->width, ALIGN_W);
+	exe_arg->out_buf_height = ALIGN(ctx->height, ALIGN_H);
+
+	/*
+	 * allocate & set DPBs
+	 */
+	if (ctx->c_ops->set_dpbs) {
+		if (ctx->c_ops->set_dpbs(ctx) < 0)
+			return MFC_DEC_INIT_FAIL;
+	}
+
+	ret = mfc_cmd_init_buffers(ctx);
+	if (ret < 0)
+		return ret;
+
+	return MFC_OK;
+}
+
+int mfc_check_resolution_change(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg)
+{
+	int resol_status;
+
+	if (exe_arg->out_display_status != DISP_S_DECODING)
+		return 0;
+
+	resol_status = (read_reg(MFC_SI_DISPLAY_STATUS) >> DISP_RC_SHIFT) & DISP_RC_MASK;
+
+	if (resol_status == DISP_RC_INC || resol_status == DISP_RC_DEC) {
+		ctx->resolution_status = RES_SET_CHANGE;
+		mfc_dbg("Change Resolution status: %d\n", resol_status);
+	}
+
+	return 0;
+}
+
+static int mfc_decoding_frame(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg, int *consumed)
+{
+	int start_ofs = *consumed;
+	int display_luma_addr;
+	int display_chroma_addr;
+	int display_frame_type;
+	int display_frame_tag;
+	unsigned char *stream_vir;
+	int ret;
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	unsigned long mem_ofs;
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	void *ump_handle;
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (!ctx->drm_flag) {
+#endif
+		/* Check Frame Start code */
+		stream_vir = phys_to_virt(exe_arg->in_strm_buf + start_ofs);
+		ret = CheckDecStartCode(stream_vir, exe_arg->in_strm_size,
+				exe_arg->in_codec_type);
+		if (ret < 0) {
+			mfc_err("Frame Check start Code Failed\n");
+			/* FIXME: Need to define proper error */
+			return MFC_FRM_BUF_SIZE_FAIL;
+		}
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	}
+#endif
+
+	/* Set Frame Tag */
+	write_shm(ctx, dec_ctx->frametag, SET_FRAME_TAG);
+
+	/* FIXME: */
+	write_reg(0xFFFFFFFF, MFC_SI_CH1_RELEASE_BUF);
+	if (dec_ctx->dpbflush) {
+		unsigned int reg;
+		reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
+		reg &= ~(1<<14);
+		reg |= (1<<14);
+		write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL); /* for DPB Flush*/
+		/*clear dbp flush in context*/
+		dec_ctx->dpbflush = 0;
+	}
+
+	mem_ofs = mfc_mem_ext_ofs(exe_arg->in_strm_buf, exe_arg->in_strm_size,
+			PORT_A);
+	if (mem_ofs < 0)
+		return MFC_DEC_EXE_ERR;
+	else
+		mfc_set_stream_info(ctx, mem_ofs >> 11, exe_arg->in_strm_size,
+			start_ofs);
+
+	/* lastframe: mfc_dec_cfg */
+	ret = mfc_cmd_frame_start(ctx);
+	if (ret < 0)
+		return ret;
+
+	if (ctx->c_ops->post_frame_start) {
+		if (ctx->c_ops->post_frame_start(ctx) < 0)
+			return MFC_DEC_EXE_ERR;
+	}
+
+	/* update display status information */
+	dec_ctx->dispstatus = read_reg(MFC_SI_DISPLAY_STATUS) & DISP_S_MASK;
+
+	/* get decode status, frame type */
+	dec_ctx->decstatus = read_reg(MFC_SI_DECODE_STATUS) & DEC_S_MASK;
+	dec_ctx->decframetype = read_reg(MFC_SI_FRAME_TYPE) & DEC_FRM_MASK;
+
+	if (dec_ctx->dispstatus == DISP_S_DECODING) {
+		display_luma_addr = 0;
+		display_chroma_addr = 0;
+
+		display_frame_type = DISP_FRM_X;
+		display_frame_tag = read_shm(ctx, GET_FRAME_TAG_TOP);
+	} else {
+		display_luma_addr = read_reg(MFC_SI_DISPLAY_Y_ADR);
+		display_chroma_addr = read_reg(MFC_SI_DISPLAY_C_ADR);
+
+		display_frame_type = get_disp_frame_type();
+		display_frame_tag = read_shm(ctx, GET_FRAME_TAG_TOP);
+
+		if (dec_ctx->ispackedpb) {
+			if ((dec_ctx->decframetype == DEC_FRM_P) || (dec_ctx->decframetype == DEC_FRM_I)) {
+				if (display_frame_type == DISP_FRM_N)
+					display_frame_type = dec_ctx->predispframetype;
+			} else {
+				if (dec_ctx->predisplumaaddr != 0) {
+					display_luma_addr = dec_ctx->predisplumaaddr;
+					display_chroma_addr = dec_ctx->predispchromaaddr;
+					display_frame_type = dec_ctx->predispframetype;
+					/* over write frame tag */
+					display_frame_tag = dec_ctx->predispframetag;
+				}
+			}
+
+			/* save the display addr */
+			dec_ctx->predisplumaaddr = read_reg(MFC_SI_DISPLAY_Y_ADR);
+			dec_ctx->predispchromaaddr = read_reg(MFC_SI_DISPLAY_C_ADR);
+
+			/* save the display frame type */
+			if (get_disp_frame_type() != DISP_FRM_N) {
+				dec_ctx->predispframetype = get_disp_frame_type();
+				/* Set Frame Tag */
+				dec_ctx->predispframetag =
+					read_shm(ctx, GET_FRAME_TAG_TOP);
+			}
+
+			mfc_dbg("pre_luma_addr: 0x%08x, pre_chroma_addr:"
+					"0x%08x, pre_disp_frame_type: %d\n",
+					(dec_ctx->predisplumaaddr << 11),
+					(dec_ctx->predispchromaaddr << 11),
+					dec_ctx->predispframetype);
+		}
+	}
+
+	/* handle ImmeidatelyDisplay for Seek, I frame only */
+	if (dec_ctx->immediatelydisplay) {
+		mfc_dbg("Immediately display\n");
+		dec_ctx->dispstatus = dec_ctx->decstatus;
+		/* update frame tag information with current ID */
+		exe_arg->out_frametag_top = dec_ctx->frametag;
+		/* FIXME : need to check this */
+		exe_arg->out_frametag_bottom = 0;
+
+		if (dec_ctx->decstatus == DEC_S_DD) {
+			mfc_dbg("Immediately display status: DEC_S_DD\n");
+			display_luma_addr = read_reg(MFC_SI_DECODE_Y_ADR);
+			display_chroma_addr = read_reg(MFC_SI_DECODE_C_ADR);
+		}
+
+		display_frame_type = dec_ctx->decframetype;
+
+		/* clear Immediately Display in decode context */
+		dec_ctx->immediatelydisplay = 0;
+	} else {
+		/* Get Frame Tag top and bottom */
+		exe_arg->out_frametag_top = display_frame_tag;
+		exe_arg->out_frametag_bottom = read_shm(ctx, GET_FRAME_TAG_BOT);
+	}
+
+	mfc_dbg("decode y: 0x%08x, c: 0x%08x\n",
+		  read_reg(MFC_SI_DECODE_Y_ADR) << 11,
+		  read_reg(MFC_SI_DECODE_C_ADR) << 11);
+
+	exe_arg->out_display_status = dec_ctx->dispstatus;
+
+	exe_arg->out_display_Y_addr = (display_luma_addr << 11);
+	exe_arg->out_display_C_addr = (display_chroma_addr << 11);
+
+	exe_arg->out_disp_pic_frame_type = display_frame_type;
+
+	exe_arg->out_y_offset = mfc_mem_data_ofs(display_luma_addr << 11, 1);
+	exe_arg->out_c_offset = mfc_mem_data_ofs(display_chroma_addr << 11, 1);
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	exe_arg->out_y_secure_id = 0;
+	exe_arg->out_c_secure_id = 0;
+
+	ump_handle = mfc_get_buf_ump_handle(out_display_Y_addr << 11);
+	if (ump_handle != NULL)
+		exe_arg->out_y_secure_id = mfc_ump_get_id(ump_handle);
+
+	ump_handle = mfc_get_buf_ump_handle(out_display_C_addr << 11);
+	if (ump_handle != NULL)
+		exe_arg->out_c_secure_id = mfc_ump_get_id(ump_handle);
+
+	mfc_dbg("secure IDs Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_secure_id,
+		exe_arg->out_c_secure_id);
+#elif defined(CONFIG_S5P_VMEM)
+	exe_arg->out_y_cookie = s5p_getcookie((void *)(out_display_Y_addr << 11));
+	exe_arg->out_c_cookie = s5p_getcookie((void *)(out_display_C_addr << 11));
+
+	mfc_dbg("cookie Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_cookie,
+		exe_arg->out_c_cookie);
+#endif
+
+	exe_arg->out_pic_time_top = read_shm(ctx, PIC_TIME_TOP);
+	exe_arg->out_pic_time_bottom = read_shm(ctx, PIC_TIME_BOT);
+
+	exe_arg->out_consumed_byte = read_reg(MFC_SI_FRM_COUNT);
+
+	if (ctx->codecid == H264_DEC) {
+		exe_arg->out_crop_right_offset = (read_shm(ctx, CROP_INFO1) >> 16) & 0xFFFF;
+		exe_arg->out_crop_left_offset = read_shm(ctx, CROP_INFO1) & 0xFFFF;
+		exe_arg->out_crop_bottom_offset = (read_shm(ctx, CROP_INFO2) >> 16) & 0xFFFF;
+		exe_arg->out_crop_top_offset = read_shm(ctx, CROP_INFO2)  & 0xFFFF;
+
+		mfc_dbg("crop info t: %d, r: %d, b: %d, l: %d\n",
+			exe_arg->out_crop_top_offset,
+			exe_arg->out_crop_right_offset,
+			exe_arg->out_crop_bottom_offset,
+			exe_arg->out_crop_left_offset);
+	}
+/*
+	mfc_dbg("decode frame type: %d\n", dec_ctx->decframetype);
+	mfc_dbg("display frame type: %d\n", exe_arg->out_disp_pic_frame_type);
+	mfc_dbg("display y: 0x%08x, c: 0x%08x\n",
+		exe_arg->out_display_Y_addr, exe_arg->out_display_C_addr);
+		*/
+
+	mfc_dbg("decode frame type: %d\n", dec_ctx->decframetype);
+	mfc_dbg("display frame type: %d,%d\n",
+			exe_arg->out_disp_pic_frame_type,
+			exe_arg->out_frametag_top);
+	mfc_dbg("display y: 0x%08x, c: 0x%08x\n",
+			exe_arg->out_display_Y_addr,
+			exe_arg->out_display_C_addr);
+
+	*consumed = read_reg(MFC_SI_FRM_COUNT);
+	mfc_dbg("stream size: %d, consumed: %d\n",
+		exe_arg->in_strm_size, *consumed);
+
+	return MFC_OK;
+}
+
+int mfc_exec_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
+{
+	struct mfc_dec_exe_arg *exe_arg;
+	int ret;
+	int consumed = 0;
+	struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
+	int sec_try_tag; /* tag store for second try */
+
+	exe_arg = (struct mfc_dec_exe_arg *)args;
+
+	/* set pre-decoding informations */
+	dec_ctx->streamaddr = exe_arg->in_strm_buf;
+	dec_ctx->streamsize = exe_arg->in_strm_size;
+	dec_ctx->frametag = exe_arg->in_frametag;
+	dec_ctx->immediatelydisplay = exe_arg->in_immediately_disp;
+
+	mfc_set_inst_state(ctx, INST_STATE_EXE);
+
+	ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
+	sec_try_tag = exe_arg->out_frametag_top;
+
+	mfc_set_inst_state(ctx, INST_STATE_EXE_DONE);
+
+	if (ret == MFC_OK) {
+		mfc_check_resolution_change(ctx, exe_arg);
+		if (ctx->resolution_status == RES_SET_CHANGE) {
+			ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
+		} else if ((ctx->resolution_status == RES_WAIT_FRAME_DONE) &&
+			(exe_arg->out_display_status == DISP_S_FINISH)) {
+			exe_arg->out_display_status = DISP_S_RES_CHANGE;
+			ret = mfc_change_resolution(ctx, exe_arg);
+			if (ret != MFC_OK)
+				return ret;
+			ctx->resolution_status = RES_NO_CHANGE;
+		}
+
+		if ((dec_ctx->ispackedpb) &&
+				(dec_ctx->decframetype == DEC_FRM_P) &&
+				(exe_arg->in_strm_size - consumed > 4)) {
+			unsigned char *stream_vir;
+			int offset = 0;
+
+			mfc_dbg("[%s] strmsize : %d consumed : %d\n", __func__,
+					exe_arg->in_strm_size, consumed);
+
+			stream_vir = phys_to_virt(exe_arg->in_strm_buf);
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+			if (!ctx->drm_flag)
+#endif
+			mfc_mem_cache_inv((void *)stream_vir,
+					exe_arg->in_strm_size);
+
+			offset = CheckMPEG4StartCode(stream_vir+consumed,
+					dec_ctx->streamsize - consumed);
+			if (offset > 4)
+				consumed += offset;
+
+			exe_arg->in_strm_size -= consumed;
+			dec_ctx->frametag = exe_arg->in_frametag;
+			dec_ctx->immediatelydisplay =
+				exe_arg->in_immediately_disp;
+
+			mfc_set_inst_state(ctx, INST_STATE_EXE);
+
+			ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
+			exe_arg->out_frametag_top = sec_try_tag;
+
+			mfc_set_inst_state(ctx, INST_STATE_EXE_DONE);
+		}
+	}
+
+	/*
+	if (ctx->c_ops->set_dpbs) {
+		if (ctx->c_ops->set_dpbs(ctx) < 0)
+			return MFC_DEC_INIT_FAIL;
+	}
+	*/
+
+	return ret;
+}
diff --git a/drivers/media/video/samsung/mfc5x/mfc_dec.h b/drivers/media/video/samsung/mfc5x/mfc_dec.h
new file mode 100644
index 0000000..f59795b
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_dec.h
@@ -0,0 +1,223 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_dec.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Decoder interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_DEC_H
+#define __MFC_DEC_H __FILE__
+
+#include <linux/list.h>
+
+#include "mfc.h"
+#include "mfc_interface.h"
+#include "mfc_inst.h"
+
+/* display status */
+/* cropping information */
+#define DISP_CROP_MASK		0x1
+#define DISP_CROP_SHIFT		6
+
+/* resolution change */
+#define DISP_RC_MASK		0x3
+#define DISP_RC_SHIFT		4
+#define DISP_RC_NO		0
+#define DISP_RC_INC		1
+#define DISP_RC_DEC		2
+
+/* progressive/interface */
+#define DISP_PI_MASK		0x1
+#define DISP_PI_SHIFT		3
+#define DISP_PI_PROGRESSIVE	0
+#define DISP_PI_INTERFACE	1
+
+#define DISP_S_MASK		0x7
+enum disp_status {
+	DISP_S_DECODING		= 0,
+	DISP_S_DD		= 1,
+	DISP_S_DISPLAY		= 2,
+	DISP_S_FINISH		= 3,
+	DISP_S_RES_CHANGE	= 4,	/* not H/W bit */
+};
+
+/* decoding status */
+/* CRC */
+#define DEC_CRC_G_MASK		0x1
+#define DEC_CRC_G_SHIFT		5
+
+#define DEC_CRC_N_MASK		0x1
+#define DEC_CRC_N_SHIFT		4
+#define DEC_CRC_TWO		0
+#define DEC_CRC_FOUR		1
+
+/* progressive/interface */
+#define DEC_PI_MASK		0x1
+#define DEC_PI_SHIFT		3
+#define DEC_PI_PROGRESSIVE	0
+#define DEC_PI_INTERFACE	1
+
+#define DEC_S_MASK	0x7
+enum dec_status {
+	DEC_S_DECODING	= 0,
+	DEC_S_DD	= 1,
+	DEC_S_DISPLAY	= 2,
+	DEC_S_FINISH	= 3,
+	DEC_S_NO	= 4,
+};
+
+/* decode frame type in SFR */
+#define DEC_FRM_MASK	0x7
+enum dec_frame {
+	DEC_FRM_N	= 0,
+	DEC_FRM_I	= 1,
+	DEC_FRM_P	= 2,
+	DEC_FRM_B	= 3,
+	DEC_FRM_OTHER	= 4,
+};
+
+/* display frame type in SHM */
+#define DISP_IDR_MASK	0x1
+#define DISP_IDR_SHIFT	5
+
+#define DISP_FRM_MASK	0x7
+#define DISP_FRM_SHIFT	2
+enum disp_frame {
+	DISP_FRM_X	= -1,	/* not H/W bit */
+	DISP_FRM_N	= 0,
+	DISP_FRM_I	= 1,
+	DISP_FRM_P	= 2,
+	DISP_FRM_B	= 3,
+	DISP_FRM_OTHER	= 4,
+};
+#define get_disp_frame_type()	((read_shm(ctx, DISP_PIC_FRAME_TYPE) >> DISP_FRM_SHIFT) & DISP_FRM_MASK)
+
+#define DISP_CODED_MASK	0x3
+
+enum dec_pc {
+	DPC_ONLY_P	= 0,
+	DPC_ONLY_B	= 1,
+	DPC_BOTH_P_B	= 2,
+	DPC_DISABLE	= 3,
+};
+
+struct mfc_dec_ctx {
+	unsigned int lumasize;		/* C */
+	unsigned int chromasize;	/* C */
+
+	/* init */
+	unsigned int crc;		/* I */
+	enum dec_pc pixelcache;		/* I */
+	unsigned int slice;		/* I */
+
+	unsigned int numextradpb;	/* I */
+	unsigned int nummindpb;		/* H */
+	unsigned int numtotaldpb;	/* C */
+
+	unsigned int level;		/* H */
+	unsigned int profile;		/* H */
+
+	/* init | exec */
+	unsigned long streamaddr;	/* I */
+	unsigned int streamsize;	/* I */
+	unsigned int frametag;	/* I */
+
+	/* exec */
+	unsigned int consumed;		/* H */
+	int predisplumaaddr;		/* H */
+	int predispchromaaddr;		/* H */
+	int predispframetype;		/* H */
+	int predispframetag;		/* H */
+
+	enum dec_frame decframetype;	/* H */
+
+	enum disp_status dispstatus;	/* H */
+	enum dec_status decstatus;	/* H */
+
+	unsigned int lastframe;		/* I */
+
+	unsigned int dpbflush;		/* I */
+	/* etc */
+	unsigned int immediatelydisplay;
+
+	/* init | exec */
+	unsigned int ispackedpb;	/* I */
+
+	void *d_priv;
+};
+
+/* decoder private data */
+struct mfc_dec_h264 {
+	/* init */
+	unsigned int mvsize;		/* C */
+
+	unsigned int dispdelay_en;	/* I */
+	unsigned int dispdelay_val;	/* I */
+
+	/* init | exec */
+	unsigned int crop_r_ofs;	/* H */
+	unsigned int crop_l_ofs;	/* H */
+	unsigned int crop_b_ofs;	/* H */
+	unsigned int crop_t_ofs;	/* H */
+
+	unsigned int sei_parse;		/* H */
+	struct mfc_frame_packing fp;	/* H */
+};
+
+struct mfc_dec_mpeg4 {
+	/* init */
+	unsigned int postfilter;	/* I */
+
+	unsigned int aspect_ratio;	/* H */
+	unsigned int ext_par_width;	/* H */
+	unsigned int ext_par_height;	/* H */
+
+	/* init | exec */
+	unsigned int packedpb;		/* I */
+};
+
+struct mfc_dec_fimv1 {
+	/* init */
+	unsigned int postfilter;	/* I */
+
+	unsigned int aspect_ratio;	/* H */
+	unsigned int ext_par_width;	/* H */
+	unsigned int ext_par_height;	/* H */
+
+	unsigned int width;		/* I */
+	unsigned int height;		/* I */
+
+	/* init | exec */
+	unsigned int packedpb;		/* I */
+};
+
+int mfc_init_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args);
+/*
+int mfc_init_decoding(struct mfc_inst_ctx *ctx, struct mfc_dec_init_arg *init_arg);
+*/
+int mfc_exec_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args);
+/*
+int mfc_exec_decoding(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg);
+*/
+
+/*---------------------------------------------------------------------------*/
+
+struct mfc_dec_info {
+	struct list_head list;
+	const char *name;
+	SSBSIP_MFC_CODEC_TYPE codectype;
+	int codecid;
+	unsigned int d_priv_size;
+
+	const struct codec_operations c_ops;
+};
+
+void mfc_init_decoders(void);
+
+#endif /* __MFC_CMD_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_dev.c b/drivers/media/video/samsung/mfc5x/mfc_dev.c
new file mode 100644
index 0000000..e3a0b60
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_dev.c
@@ -0,0 +1,1684 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_dev.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/firmware.h>
+#include <linux/proc_fs.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/clk.h>
+#endif
+#include <linux/pm_qos_params.h>
+
+#ifdef CONFIG_BUSFREQ_OPP
+#include <mach/busfreq_exynos4.h>
+#endif
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#include <mach/dev.h>
+#endif
+#include <plat/cpu.h>
+
+#if defined(CONFIG_BUSFREQ) || defined(CONFIG_EXYNOS4_CPUFREQ)
+#include <mach/cpufreq.h>
+#endif
+#include <mach/regs-pmu.h>
+
+#include <asm/uaccess.h>
+
+#include "mfc_dev.h"
+#include "mfc_interface.h"
+#include "mfc_reg.h"
+#include "mfc_log.h"
+#include "mfc_ctrl.h"
+#include "mfc_buf.h"
+#include "mfc_inst.h"
+#include "mfc_pm.h"
+#include "mfc_dec.h"
+#include "mfc_enc.h"
+#include "mfc_mem.h"
+#include "mfc_cmd.h"
+
+#ifdef SYSMMU_MFC_ON
+#include <plat/sysmmu.h>
+#endif
+
+#define MFC_MINOR	252
+#define MFC_FW_NAME	"mfc_fw.bin"
+
+static struct mfc_dev *mfcdev;
+static struct proc_dir_entry *mfc_proc_entry;
+
+#define MFC_PROC_ROOT		"mfc"
+#define MFC_PROC_TOTAL_INSTANCE_NUMBER	"total_instance_number"
+
+#ifdef CONFIG_BUSFREQ
+static struct pm_qos_request_list bus_qos_pm_qos_req;
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#define MFC_DRM_MAGIC_SIZE	0x10
+#define MFC_DRM_MAGIC_CHUNK0	0x13cdbf16
+#define MFC_DRM_MAGIC_CHUNK1	0x8b803342
+#define MFC_DRM_MAGIC_CHUNK2	0x5e87f4f5
+#define MFC_DRM_MAGIC_CHUNK3	0x3bd05317
+
+static int check_magic(unsigned char *addr)
+{
+	if (((u32)*(u32 *)(addr) == MFC_DRM_MAGIC_CHUNK0) &&
+	    ((u32)*(u32 *)(addr + 0x4) == MFC_DRM_MAGIC_CHUNK1) &&
+	    ((u32)*(u32 *)(addr + 0x8) == MFC_DRM_MAGIC_CHUNK2) &&
+	    ((u32)*(u32 *)(addr + 0xC) == MFC_DRM_MAGIC_CHUNK3))
+		return 0;
+	else if (((u32)*(u32 *)(addr+0x10) == MFC_DRM_MAGIC_CHUNK0) &&
+	    ((u32)*(u32 *)(addr + 0x14) == MFC_DRM_MAGIC_CHUNK1) &&
+	    ((u32)*(u32 *)(addr + 0x18) == MFC_DRM_MAGIC_CHUNK2) &&
+	    ((u32)*(u32 *)(addr + 0x1C) == MFC_DRM_MAGIC_CHUNK3))
+		return 0x10;
+	else
+		return -1;
+}
+
+static inline void clear_magic(unsigned char *addr)
+{
+	memset((void *)addr, 0x00, MFC_DRM_MAGIC_SIZE);
+}
+#endif
+
+static int get_free_inst_id(struct mfc_dev *dev)
+{
+	int slot = 0;
+
+	while (dev->inst_ctx[slot]) {
+		slot++;
+		if (slot >= MFC_MAX_INSTANCE_NUM)
+			return -1;
+	}
+
+	return slot;
+}
+
+static int mfc_open(struct inode *inode, struct file *file)
+{
+	struct mfc_inst_ctx *mfc_ctx;
+	int ret;
+	enum mfc_ret_code retcode;
+	int inst_id;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	struct mfc_alloc_buffer *alloc;
+#endif
+
+	/* prevent invalid reference */
+	file->private_data = NULL;
+
+	mutex_lock(&mfcdev->lock);
+#if SUPPORT_SLICE_ENCODING
+	mfcdev->frame_working_flag = 1;
+	mfcdev->frame_sys = 0;
+#endif
+
+	if (!mfcdev->fw.state) {
+		if (mfcdev->fw.requesting) {
+			printk(KERN_INFO "MFC F/W request is on-going, try again\n");
+			ret = -ENODEV;
+			goto err_fw_state;
+		}
+
+		printk(KERN_INFO "MFC F/W is not existing, requesting...\n");
+		ret = request_firmware(&mfcdev->fw.info, MFC_FW_NAME, mfcdev->device);
+
+		if (ret < 0) {
+			printk(KERN_INFO "failed to copy MFC F/W during open\n");
+			ret = -ENODEV;
+			goto err_fw_state;
+		}
+
+		if (soc_is_exynos4212() || soc_is_exynos4412()) {
+			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);
+			if (!mfcdev->fw.state) {
+				printk(KERN_ERR "failed to load MFC F/W, MFC will not working\n");
+				ret = -ENODEV;
+				goto err_fw_state;
+			} else {
+				printk(KERN_INFO "MFC F/W loaded successfully (size: %d)\n", mfcdev->fw.info->size);
+			}
+		}
+	}
+
+	if (atomic_read(&mfcdev->inst_cnt) == 0) {
+		/* reload F/W for first instance again */
+		if (soc_is_exynos4210()) {
+			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);
+			if (!mfcdev->fw.state) {
+				printk(KERN_ERR "failed to reload MFC F/W, MFC will not working\n");
+				ret = -ENODEV;
+				goto err_fw_state;
+			} else {
+				printk(KERN_INFO "MFC F/W reloaded successfully (size: %d)\n", mfcdev->fw.info->size);
+			}
+		}
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+		dev_lock(mfcdev->bus_dev, mfcdev->device, 133133);
+#endif
+#ifdef CONFIG_BUSFREQ
+		pm_qos_add_request(&bus_qos_pm_qos_req, PM_QOS_BUS_QOS, 1);
+#endif
+
+		ret = mfc_power_on();
+		if (ret < 0) {
+			mfc_err("power enable failed\n");
+			goto err_pwr_enable;
+		}
+
+#ifndef CONFIG_PM_RUNTIME
+#ifdef SYSMMU_MFC_ON
+		mfc_clock_on(mfcdev);
+
+		s5p_sysmmu_enable(mfcdev->device);
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+		vcm_set_pgtable_base(VCM_DEV_MFC);
+#else /* CONFIG_S5P_VMEM or kernel virtual memory allocator */
+		s5p_sysmmu_set_tablebase_pgd(mfcdev->device,
+							__pa(swapper_pg_dir));
+
+		/*
+		 * RMVME: the power-gating work really (on <-> off),
+		 * all TBL entry was invalidated already when the power off
+		 */
+		s5p_sysmmu_tlb_invalidate(mfcdev->device, SYSMMU_MFC_R);
+#endif
+		mfc_clock_off(mfcdev);
+#endif
+#endif
+		/* MFC hardware initialization */
+		retcode = mfc_start(mfcdev);
+		if (retcode != MFC_OK) {
+			mfc_err("MFC H/W init failed: %d\n", retcode);
+			ret = -ENODEV;
+			goto err_start_hw;
+		}
+	}
+
+	if (atomic_read(&mfcdev->inst_cnt) >= MFC_MAX_INSTANCE_NUM) {
+		mfc_err("exceed max instance number, too many instance opened already\n");
+		ret = -EINVAL;
+		goto err_inst_cnt;
+	}
+
+	inst_id = get_free_inst_id(mfcdev);
+	if (inst_id < 0) {
+		mfc_err("failed to get instance ID\n");
+		ret = -EINVAL;
+		goto err_inst_id;
+	}
+
+	mfc_ctx = mfc_create_inst();
+	if (!mfc_ctx) {
+		mfc_err("failed to create instance context\n");
+		ret = -ENOMEM;
+		goto err_inst_ctx;
+	}
+
+	atomic_inc(&mfcdev->inst_cnt);
+	mfcdev->inst_ctx[inst_id] = mfc_ctx;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (check_magic(mfcdev->drm_info.addr) >= 0) {
+		mfc_info("DRM instance starting\n");
+		clear_magic(mfcdev->drm_info.addr + check_magic(mfcdev->drm_info.addr));
+		mfc_ctx->drm_flag = 1;
+		mfc_set_buf_alloc_scheme(MBS_FIRST_FIT);
+	} else {
+		mfc_ctx->drm_flag = 0;
+	}
+#endif
+
+	mfc_ctx->id = inst_id;
+	mfc_ctx->dev = mfcdev;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (mfc_ctx->drm_flag) {
+		alloc = _mfc_alloc_buf(mfc_ctx, MFC_CTX_SIZE_L, ALIGN_2KB, MBT_CTX | PORT_A);
+		if (alloc == NULL) {
+			mfc_err("failed to alloc context buffer\n");
+			ret = -ENOMEM;
+			goto err_drm_ctx;
+		}
+
+		mfc_ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
+		mfc_ctx->ctxbufsize = alloc->size;
+		memset((void *)alloc->addr, 0, alloc->size);
+		mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+	}
+#endif
+
+	file->private_data = (struct mfc_inst_ctx *)mfc_ctx;
+
+#if SUPPORT_SLICE_ENCODING
+	if (atomic_read(&mfcdev->inst_cnt) == 1) {
+		mfcdev->slice_encoding_flag = 0;
+		mfcdev->slice_sys = 0;
+		mfcdev->wait_slice_timeout = 0;
+		mfcdev->wait_frame_timeout = 0;
+	}
+	mfc_ctx->slice_flag = 0;
+	mfcdev->frame_sys = 1;
+	mfcdev->frame_working_flag = 0;
+	if (mfcdev->wait_frame_timeout == 1)
+		wake_up(&mfcdev->wait_frame);
+#endif
+
+	mfc_info("MFC instance [%d:%d] opened", mfc_ctx->id,
+		atomic_read(&mfcdev->inst_cnt));
+
+	mutex_unlock(&mfcdev->lock);
+
+	return 0;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+err_drm_ctx:
+#endif
+err_inst_ctx:
+err_inst_id:
+err_inst_cnt:
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#endif
+err_start_hw:
+	if (atomic_read(&mfcdev->inst_cnt) == 0) {
+		if (mfc_power_off() < 0)
+			mfc_err("power disable failed\n");
+	}
+
+err_pwr_enable:
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	dev_unlock(mfcdev->bus_dev, mfcdev->device);
+#endif
+
+err_fw_state:
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+#endif
+	mutex_unlock(&mfcdev->lock);
+
+	return ret;
+}
+
+static int mfc_release(struct inode *inode, struct file *file)
+{
+	struct mfc_inst_ctx *mfc_ctx;
+	struct mfc_dev *dev;
+	int ret;
+
+	mfc_ctx = (struct mfc_inst_ctx *)file->private_data;
+	if (!mfc_ctx)
+		return -EINVAL;
+
+	dev = mfc_ctx->dev;
+
+	mutex_lock(&dev->lock);
+#if SUPPORT_SLICE_ENCODING
+	dev->frame_working_flag = 1;
+	dev->frame_sys = 0;
+	if (dev->slice_encoding_flag == 1) {
+		mutex_unlock(&dev->lock);
+		dev->wait_slice_timeout = 1;
+		if (wait_event_timeout(dev->wait_slice, dev->slice_sys,
+			SLICE_ENC_TIMEOUT) == 0) {
+			mfc_err("Slice encoding done timeout : %d\n",
+				dev->slice_sys);
+			dev->slice_encoding_flag = 0;
+			dev->slice_sys = 0;
+			dev->wait_slice_timeout = 0;
+		}
+		mutex_lock(&dev->lock);
+		dev->slice_sys = 0;
+		dev->wait_slice_timeout = 0;
+	}
+#endif
+
+#if defined(CONFIG_BUSFREQ)
+	/* Release MFC & Bus Frequency lock for High resolution */
+	if (mfc_ctx->busfreq_flag == true) {
+		atomic_dec(&dev->busfreq_lock_cnt);
+		mfc_ctx->busfreq_flag = false;
+		if (atomic_read(&dev->busfreq_lock_cnt) == 0) {
+			/* release Freq lock back to normal */
+			exynos4_busfreq_lock_free(DVFS_LOCK_ID_MFC);
+			mfc_dbg("[%s] Bus Freq lock Released Normal!\n", __func__);
+		}
+	}
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	/* Release MFC & CPU Frequency lock for High resolution */
+	if (mfc_ctx->cpufreq_flag == true) {
+		atomic_dec(&dev->cpufreq_lock_cnt);
+		mfc_ctx->cpufreq_flag = false;
+		if (atomic_read(&dev->cpufreq_lock_cnt) == 0) {
+			/* release Freq lock back to normal */
+			exynos_cpufreq_lock_free(DVFS_LOCK_ID_MFC);
+			mfc_dbg("[%s] CPU Freq lock Released Normal!\n", __func__);
+		}
+	}
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	if (mfc_ctx->dmcthreshold_flag == true) {
+		atomic_dec(&dev->dmcthreshold_lock_cnt);
+		mfc_ctx->dmcthreshold_flag = false;
+		if (atomic_read(&dev->dmcthreshold_lock_cnt) == 0) {
+			mfc_info("[%s] Restore dmc_max_threshold\n", __func__);
+			if (soc_is_exynos4212()) {
+				dmc_max_threshold =
+					EXYNOS4212_DMC_MAX_THRESHOLD;
+			} else if (soc_is_exynos4412()) {
+				dmc_max_threshold =
+					EXYNOS4412_DMC_MAX_THRESHOLD;
+			} else {
+				pr_err("Unsupported model.\n");
+				return -EINVAL;
+			}
+		}
+	}
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (mfc_ctx->drm_flag) {
+		mfc_set_buf_alloc_scheme(MBS_FIRST_FIT);
+	}
+#endif
+	mfc_info("MFC instance [%d:%d] released\n", mfc_ctx->id,
+		atomic_read(&mfcdev->inst_cnt));
+
+	file->private_data = NULL;
+
+	dev->inst_ctx[mfc_ctx->id] = NULL;
+	atomic_dec(&dev->inst_cnt);
+
+	mfc_destroy_inst(mfc_ctx);
+
+	if (atomic_read(&dev->inst_cnt) == 0) {
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+		dev_unlock(mfcdev->bus_dev, mfcdev->device);
+#endif
+#ifdef CONFIG_BUSFREQ
+		pm_qos_remove_request(&bus_qos_pm_qos_req);
+#endif
+#if SUPPORT_SLICE_ENCODING
+		dev->slice_encoding_flag = 0;
+		dev->slice_sys = 0;
+		dev->wait_slice_timeout = 0;
+		dev->wait_frame_timeout = 0;
+#endif
+		ret = mfc_power_off();
+		if (ret < 0) {
+			mfc_err("power disable failed\n");
+			goto err_pwr_disable;
+		}
+	} else {
+#if defined(SYSMMU_MFC_ON) && !defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	mfc_clock_on(mfcdev);
+
+	s5p_sysmmu_tlb_invalidate(dev->device);
+
+	mfc_clock_off(mfcdev);
+#endif
+	}
+
+	ret = 0;
+#if SUPPORT_SLICE_ENCODING
+	dev->frame_sys = 1;
+	dev->frame_working_flag = 0;
+	if (mfcdev->wait_frame_timeout == 1)
+		wake_up(&dev->wait_frame);
+#endif
+
+err_pwr_disable:
+	mutex_unlock(&dev->lock);
+
+	return ret;
+}
+
+/* FIXME: add request firmware ioctl */
+static long mfc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+
+	struct mfc_inst_ctx *mfc_ctx;
+	int ret, ex_ret;
+	struct mfc_common_args in_param;
+	struct mfc_buf_alloc_arg buf_arg;
+	struct mfc_config_arg *cfg_arg;
+	int port;
+
+	struct mfc_dev *dev;
+	int i;
+
+	mfc_ctx = (struct mfc_inst_ctx *)file->private_data;
+	if (!mfc_ctx)
+		return -EINVAL;
+
+	dev = mfc_ctx->dev;
+
+	mutex_lock(&dev->lock);
+
+	ret = copy_from_user(&in_param, (struct mfc_common_args *)arg,
+			sizeof(struct mfc_common_args));
+	if (ret < 0) {
+		mfc_err("failed to copy parameters\n");
+		ret = -EIO;
+		in_param.ret_code = MFC_INVALID_PARAM_FAIL;
+		goto out_ioctl;
+	}
+
+	mutex_unlock(&dev->lock);
+
+	/* FIXME: add locking */
+
+	mfc_dbg("cmd: 0x%08x\n", cmd);
+
+	switch (cmd) {
+
+	case IOCTL_MFC_DEC_INIT:
+		mutex_lock(&dev->lock);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_working_flag = 1;
+		dev->frame_sys = 0;
+		if (dev->slice_encoding_flag == 1) {
+			mutex_unlock(&dev->lock);
+			dev->wait_slice_timeout = 1;
+			if (wait_event_timeout(dev->wait_slice, dev->slice_sys,
+				SLICE_ENC_TIMEOUT) == 0) {
+				mfc_err("Slice encoding done timeout : %d\n",
+					dev->slice_sys);
+				dev->slice_encoding_flag = 0;
+				dev->slice_sys = 0;
+				dev->wait_slice_timeout = 0;
+				ret = -EINVAL;
+
+				mutex_lock(&dev->lock);
+				break;
+			}
+			mutex_lock(&dev->lock);
+			dev->slice_sys = 0;
+			dev->wait_slice_timeout = 0;
+		}
+#endif
+		if (mfc_chk_inst_state(mfc_ctx, INST_STATE_CREATE) < 0) {
+			mfc_err("IOCTL_MFC_DEC_INIT invalid state: 0x%08x\n",
+				 mfc_ctx->state);
+			in_param.ret_code = MFC_STATE_INVALID;
+			ret = -EINVAL;
+
+			mutex_unlock(&dev->lock);
+			break;
+		}
+
+		mfc_clock_on(mfcdev);
+		in_param.ret_code = mfc_init_decoding(mfc_ctx, &(in_param.args));
+		ret = in_param.ret_code;
+		mfc_clock_off(mfcdev);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_sys = 1;
+		dev->frame_working_flag = 0;
+		if (dev->wait_frame_timeout == 1)
+			wake_up(&dev->wait_frame);
+#endif
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_ENC_INIT:
+		mutex_lock(&dev->lock);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_working_flag = 1;
+		dev->frame_sys = 0;
+		if (dev->slice_encoding_flag == 1) {
+			mutex_unlock(&dev->lock);
+			dev->wait_slice_timeout = 1;
+			if (wait_event_timeout(dev->wait_slice, dev->slice_sys,
+				SLICE_ENC_TIMEOUT) == 0) {
+				mfc_err("Slice encoding done timeout : %d\n",
+					dev->slice_sys);
+				dev->slice_encoding_flag = 0;
+				dev->slice_sys = 0;
+				dev->wait_slice_timeout = 0;
+				ret = -EINVAL;
+
+				mutex_lock(&dev->lock);
+				break;
+			}
+			mutex_lock(&dev->lock);
+			dev->slice_sys = 0;
+			dev->wait_slice_timeout = 0;
+		}
+#endif
+
+		if (mfc_chk_inst_state(mfc_ctx, INST_STATE_CREATE) < 0) {
+			mfc_err("IOCTL_MFC_ENC_INIT invalid state: 0x%08x\n",
+				 mfc_ctx->state);
+			in_param.ret_code = MFC_STATE_INVALID;
+			ret = -EINVAL;
+
+			mutex_unlock(&dev->lock);
+			break;
+		}
+
+		mfc_clock_on(mfcdev);
+		in_param.ret_code = mfc_init_encoding(mfc_ctx, &(in_param.args));
+		ret = in_param.ret_code;
+		mfc_clock_off(mfcdev);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_sys = 1;
+		dev->frame_working_flag = 0;
+		if (dev->wait_frame_timeout == 1)
+			wake_up(&dev->wait_frame);
+#endif
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_DEC_EXE:
+		mutex_lock(&dev->lock);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_working_flag = 1;
+		dev->frame_sys = 0;
+		if (dev->slice_encoding_flag == 1) {
+			mutex_unlock(&dev->lock);
+			dev->wait_slice_timeout = 1;
+			if (wait_event_timeout(dev->wait_slice, dev->slice_sys,
+				SLICE_ENC_TIMEOUT) == 0) {
+				mfc_err("Slice encoding done timeout : %d\n",
+					dev->slice_sys);
+				dev->slice_encoding_flag = 0;
+				dev->slice_sys = 0;
+				dev->wait_slice_timeout = 0;
+				ret = -EINVAL;
+
+				mutex_lock(&dev->lock);
+				break;
+			}
+			mutex_lock(&dev->lock);
+			dev->slice_sys = 0;
+			dev->wait_slice_timeout = 0;
+		}
+#endif
+
+		if (mfc_ctx->state < INST_STATE_INIT) {
+			mfc_err("IOCTL_MFC_DEC_EXE invalid state: 0x%08x\n",
+					mfc_ctx->state);
+			in_param.ret_code = MFC_STATE_INVALID;
+			ret = -EINVAL;
+
+			mutex_unlock(&dev->lock);
+			break;
+		}
+
+		mfc_clock_on(mfcdev);
+		in_param.ret_code = mfc_exec_decoding(mfc_ctx, &(in_param.args));
+		ret = in_param.ret_code;
+		mfc_clock_off(mfcdev);
+#if SUPPORT_SLICE_ENCODING
+		dev->frame_sys = 1;
+		dev->frame_working_flag = 0;
+		if (dev->wait_frame_timeout == 1)
+			wake_up(&dev->wait_frame);
+#endif
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_ENC_EXE:
+		mutex_lock(&dev->lock);
+#if SUPPORT_SLICE_ENCODING
+		if (mfc_ctx->slice_flag == 0) {
+			dev->frame_working_flag = 1;
+			dev->frame_sys = 0;
+		}
+
+		if ((dev->slice_encoding_flag == 1)
+			&& (mfc_ctx->slice_flag == 0)) {
+			mutex_unlock(&dev->lock);
+			dev->wait_slice_timeout = 1;
+			if (wait_event_timeout(dev->wait_slice, dev->slice_sys,
+				SLICE_ENC_TIMEOUT) == 0) {
+				mfc_err("Slice encoding done timeout : %d\n",
+					dev->slice_sys);
+				dev->slice_encoding_flag = 0;
+				dev->slice_sys = 0;
+				dev->wait_slice_timeout = 0;
+				ret = -EINVAL;
+
+				mutex_lock(&dev->lock);
+				break;
+			}
+			mutex_lock(&dev->lock);
+			dev->slice_sys = 0;
+			dev->wait_slice_timeout = 0;
+		}
+
+		if ((dev->frame_working_flag == 1) && (mfc_ctx->slice_flag == 1)
+			&& (dev->slice_encoding_flag == 0)) {
+			mutex_unlock(&dev->lock);
+			dev->wait_frame_timeout = 1;
+			if (wait_event_timeout(dev->wait_frame, dev->frame_sys,
+				SLICE_ENC_TIMEOUT) == 0) {
+				mfc_err("frame working done timeout : %d\n",
+					dev->frame_sys);
+				dev->frame_working_flag = 0;
+				dev->frame_sys = 0;
+				dev->wait_frame_timeout = 0;
+				ret = -EINVAL;
+
+				mutex_lock(&dev->lock);
+				break;
+			}
+			mutex_lock(&dev->lock);
+			dev->frame_sys = 0;
+			dev->wait_frame_timeout = 0;
+		}
+#endif
+
+		if (mfc_ctx->state < INST_STATE_INIT) {
+			mfc_err("IOCTL_MFC_DEC_EXE invalid state: 0x%08x\n",
+					mfc_ctx->state);
+			in_param.ret_code = MFC_STATE_INVALID;
+			ret = -EINVAL;
+
+			mutex_unlock(&dev->lock);
+			break;
+		}
+
+		mfc_clock_on(mfcdev);
+		in_param.ret_code = mfc_exec_encoding(mfc_ctx, &(in_param.args));
+		ret = in_param.ret_code;
+		mfc_clock_off(mfcdev);
+#if SUPPORT_SLICE_ENCODING
+		if (mfc_ctx->slice_flag == 0) {
+			dev->frame_sys = 1;
+			dev->frame_working_flag = 0;
+			if (dev->wait_frame_timeout == 1)
+				wake_up(&dev->wait_frame);
+		}
+#endif
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_GET_IN_BUF:
+		mutex_lock(&dev->lock);
+
+		if (in_param.args.mem_alloc.type == ENCODER) {
+			buf_arg.type = ENCODER;
+			port = 1;
+		} else {
+			buf_arg.type = DECODER;
+			port = 0;
+		}
+
+		/* FIXME: consider the size */
+		buf_arg.size = in_param.args.mem_alloc.buff_size;
+		/*
+		buf_arg.mapped = in_param.args.mem_alloc.mapped_addr;
+		*/
+		/* FIXME: encodeing linear: 2KB, tile: 8KB */
+		buf_arg.align = ALIGN_2KB;
+
+		if (buf_arg.type == ENCODER)
+			in_param.ret_code = mfc_alloc_buf(mfc_ctx, &buf_arg, MBT_DPB | port);
+		else
+			in_param.ret_code = mfc_alloc_buf(mfc_ctx, &buf_arg, MBT_CPB | port);
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+		in_param.args.mem_alloc.secure_id = buf_arg.secure_id;
+#elif defined(CONFIG_S5P_VMEM)
+		in_param.args.mem_alloc.cookie = buf_arg.cookie;
+#else
+		in_param.args.mem_alloc.offset = buf_arg.offset;
+#endif
+		ret = in_param.ret_code;
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_FREE_BUF:
+		mutex_lock(&dev->lock);
+
+		in_param.ret_code =
+			mfc_free_buf(mfc_ctx, in_param.args.mem_free.key);
+		ret = in_param.ret_code;
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_GET_REAL_ADDR:
+		mutex_lock(&dev->lock);
+
+		in_param.args.real_addr.addr =
+			mfc_get_buf_real(mfc_ctx->id, in_param.args.real_addr.key);
+
+		mfc_dbg("real addr: 0x%08x", in_param.args.real_addr.addr);
+
+		if (in_param.args.real_addr.addr)
+			in_param.ret_code = MFC_OK;
+		else
+			in_param.ret_code = MFC_MEM_INVALID_ADDR_FAIL;
+
+		ret = in_param.ret_code;
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_GET_MMAP_SIZE:
+		if (mfc_chk_inst_state(mfc_ctx, INST_STATE_CREATE) < 0) {
+			mfc_err("IOCTL_MFC_GET_MMAP_SIZE invalid state: \
+				0x%08x\n", mfc_ctx->state);
+			in_param.ret_code = MFC_STATE_INVALID;
+			ret = -EINVAL;
+
+			break;
+		}
+
+		in_param.ret_code = MFC_OK;
+		ret = 0;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+		for (i = 0; i < MFC_MAX_MEM_CHUNK_NUM; i++)
+			ret += mfc_mem_data_size(i);
+
+		ret += mfc_mem_hole_size();
+#else
+		for (i = 0; i < dev->mem_ports; i++)
+			ret += mfc_mem_data_size(i);
+#endif
+
+		break;
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	case IOCTL_MFC_SET_IN_BUF:
+		if (in_param.args.mem_alloc.type == ENCODER) {
+			buf_arg.secure_id = in_param.args.mem_alloc.secure_id;
+			buf_arg.align = ALIGN_2KB;
+			port = 1;
+			ret = mfc_vcm_bind_from_others(mfc_ctx, &buf_arg, MBT_OTHER | port);
+		} else {
+		in_param.args.real_addr.addr =
+			mfc_ump_get_virt(in_param.args.real_addr.key);
+
+		mfc_dbg("real addr: 0x%08x", in_param.args.real_addr.addr);
+
+		if (in_param.args.real_addr.addr)
+			in_param.ret_code = MFC_OK;
+		else
+			in_param.ret_code = MFC_MEM_INVALID_ADDR_FAIL;
+
+		ret = in_param.ret_code;
+		}
+
+		break;
+#endif
+
+	case IOCTL_MFC_SET_CONFIG:
+		/* FIXME: mfc_chk_inst_state*/
+		/* RMVME: need locking ? */
+		mutex_lock(&dev->lock);
+
+		/* in_param.ret_code = mfc_set_config(mfc_ctx, &(in_param.args)); */
+
+		cfg_arg = (struct mfc_config_arg *)&in_param.args;
+
+		in_param.ret_code = mfc_set_inst_cfg(mfc_ctx, cfg_arg->type,
+				(void *)&cfg_arg->args);
+		ret = in_param.ret_code;
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_GET_CONFIG:
+		/* FIXME: mfc_chk_inst_state */
+		/* RMVME: need locking ? */
+		mutex_lock(&dev->lock);
+
+		cfg_arg = (struct mfc_config_arg *)&in_param.args;
+
+		in_param.ret_code = mfc_get_inst_cfg(mfc_ctx, cfg_arg->type,
+				(void *)&cfg_arg->args);
+		ret = in_param.ret_code;
+
+		mutex_unlock(&dev->lock);
+		break;
+
+	case IOCTL_MFC_SET_BUF_CACHE:
+		mfc_ctx->buf_cache_type = in_param.args.mem_alloc.buf_cache_type;
+		in_param.ret_code = MFC_OK;
+		break;
+
+	default:
+		mfc_err("failed to execute ioctl cmd: 0x%08x\n", cmd);
+
+		in_param.ret_code = MFC_INVALID_PARAM_FAIL;
+		ret = -EINVAL;
+	}
+
+out_ioctl:
+	ex_ret = copy_to_user((struct mfc_common_args *)arg,
+			&in_param,
+			sizeof(struct mfc_common_args));
+	if (ex_ret < 0) {
+		mfc_err("Outparm copy to user error\n");
+		ret = -EIO;
+	}
+
+	mfc_dbg("return = %d\n", ret);
+
+	return ret;
+}
+
+static void mfc_vm_open(struct vm_area_struct *vma)
+{
+	/* FIXME:
+	struct mfc_inst_ctx *mfc_ctx = (struct mfc_inst_ctx *)vma->vm_private_data;
+
+	mfc_dbg("id: %d\n", mfc_ctx->id);
+	*/
+
+	/* FIXME: atomic_inc(mapped count) */
+}
+
+static void mfc_vm_close(struct vm_area_struct *vma)
+{
+	/* FIXME:
+	struct mfc_inst_ctx *mfc_ctx = (struct mfc_inst_ctx *)vma->vm_private_data;
+
+	mfc_dbg("id: %d\n", mfc_ctx->id);
+	*/
+
+	/* FIXME: atomic_dec(mapped count) */
+}
+
+static int mfc_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+
+	/* FIXME:
+	struct mfc_inst_ctx *mfc_ctx = (struct mfc_inst_ctx *)vma->vm_private_data;
+	struct page *pg = NULL;
+
+	mfc_dbg("id: %d, pgoff: 0x%08lx, user: 0x%08lx\n",
+		mfc_ctx->id, vmf->pgoff, (unsigned long)(vmf->virtual_address));
+
+	if (mfc_ctx == NULL)
+		return VM_FAULT_SIGBUS;
+
+	mfc_dbg("addr: 0x%08lx\n",
+		(unsigned long)(_mfc_get_buf_addr(mfc_ctx->id, vmf->virtual_address)));
+
+	pg = vmalloc_to_page(_mfc_get_buf_addr(mfc_ctx->id, vmf->virtual_address));
+
+	if (!pg)
+		return VM_FAULT_SIGBUS;
+
+	vmf->page = pg;
+	*/
+
+	return 0;
+}
+
+static const struct vm_operations_struct mfc_vm_ops = {
+	.open	= mfc_vm_open,
+	.close	= mfc_vm_close,
+	.fault	= mfc_vm_fault,
+};
+
+static int mfc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	unsigned long user_size = vma->vm_end - vma->vm_start;
+	unsigned long real_size;
+	struct mfc_inst_ctx *mfc_ctx;
+#if !(defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(CONFIG_S5P_VMEM))
+	/* mmap support */
+	unsigned long pfn;
+	unsigned long remap_offset, remap_size;
+	struct mfc_dev *dev;
+#ifdef SYSMMU_MFC_ON
+	/* kernel virtual memory allocator */
+	char *ptr;
+	unsigned long start, size;
+#endif
+#endif
+	mfc_ctx = (struct mfc_inst_ctx *)file->private_data;
+	if (!mfc_ctx)
+		return -EINVAL;
+
+#if !(defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(CONFIG_S5P_VMEM))
+	dev = mfc_ctx->dev;
+#endif
+
+	mfc_dbg("vm_start: 0x%08lx, vm_end: 0x%08lx, size: %ld(%ldMB)\n",
+		vma->vm_start, vma->vm_end, user_size, (user_size >> 20));
+
+	real_size = (unsigned long)(mfc_mem_data_size(0) + mfc_mem_data_size(1));
+
+	mfc_dbg("port 0 size: %d, port 1 size: %d, total: %ld\n",
+		mfc_mem_data_size(0),
+		mfc_mem_data_size(1),
+		real_size);
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	real_size += mfc_mem_hole_size();
+#endif
+
+	/*
+	 * if memory size required from appl. mmap() is bigger than max data memory
+	 * size allocated in the driver.
+	 */
+	if (user_size > real_size) {
+		mfc_err("user requeste mem(%ld) is bigger than available mem(%ld)\n",
+			user_size, real_size);
+		return -EINVAL;
+	}
+#ifdef SYSMMU_MFC_ON
+#if (defined(CONFIG_VIDEO_MFC_VCM_UMP) || defined(CONFIG_S5P_VMEM))
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_ops = &mfc_vm_ops;
+	vma->vm_private_data = mfc_ctx;
+
+	mfc_ctx->userbase = vma->vm_start;
+#else	/* not CONFIG_VIDEO_MFC_VCM_UMP && not CONFIG_S5P_VMEM */
+	/* kernel virtual memory allocator */
+	if (dev->mem_ports == 1) {
+		remap_offset = 0;
+		remap_size = user_size;
+
+		vma->vm_flags |= VM_RESERVED | VM_IO;
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+		/*
+		 * Port 0 mapping for stream buf & frame buf (chroma + MV + luma)
+		 */
+		ptr = (char *)mfc_mem_data_base(0);
+		start = remap_offset;
+		size = remap_size;
+		while (size > 0) {
+			pfn = vmalloc_to_pfn(ptr);
+			if (remap_pfn_range(vma, vma->vm_start + start, pfn,
+				PAGE_SIZE, vma->vm_page_prot)) {
+
+				mfc_err("failed to remap port 0\n");
+				return -EAGAIN;
+			}
+
+			start += PAGE_SIZE;
+			ptr += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+	} else {
+		remap_offset = 0;
+		remap_size = min((unsigned long)mfc_mem_data_size(0), user_size);
+
+		vma->vm_flags |= VM_RESERVED | VM_IO;
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+		/*
+		 * Port 0 mapping for stream buf & frame buf (chroma + MV)
+		 */
+		ptr = (char *)mfc_mem_data_base(0);
+		start = remap_offset;
+		size = remap_size;
+		while (size > 0) {
+			pfn = vmalloc_to_pfn(ptr);
+			if (remap_pfn_range(vma, vma->vm_start + start, pfn,
+				PAGE_SIZE, vma->vm_page_prot)) {
+
+				mfc_err("failed to remap port 0\n");
+				return -EAGAIN;
+			}
+
+			start += PAGE_SIZE;
+			ptr += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+
+		remap_offset = remap_size;
+		remap_size = min((unsigned long)mfc_mem_data_size(1),
+			user_size - remap_offset);
+
+		vma->vm_flags |= VM_RESERVED | VM_IO;
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+		/*
+		 * Port 1 mapping for frame buf (luma)
+		 */
+		ptr = (void *)mfc_mem_data_base(1);
+		start = remap_offset;
+		size = remap_size;
+		while (size > 0) {
+			pfn = vmalloc_to_pfn(ptr);
+			if (remap_pfn_range(vma, vma->vm_start + start, pfn,
+				PAGE_SIZE, vma->vm_page_prot)) {
+
+				mfc_err("failed to remap port 1\n");
+				return -EAGAIN;
+			}
+
+			start += PAGE_SIZE;
+			ptr += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+	}
+
+	mfc_ctx->userbase = vma->vm_start;
+
+	mfc_dbg("user request mem = %ld, available data mem = %ld\n",
+		  user_size, real_size);
+
+	if ((remap_offset + remap_size) < real_size)
+		mfc_warn("The MFC reserved memory dose not mmap fully [%ld: %ld]\n",
+		  real_size, (remap_offset + remap_size));
+#endif	/* end of CONFIG_VIDEO_MFC_VCM_UMP */
+#else	/* not SYSMMU_MFC_ON */
+	/* early allocator */
+	/* CMA or bootmem(memblock) */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	if (mfc_ctx->buf_cache_type == NO_CACHE)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	mfc_info("MFC buffers are %scacheable\n",
+			mfc_ctx->buf_cache_type ? "" : "non-");
+
+	remap_offset = 0;
+	remap_size = min((unsigned long)mfc_mem_data_size(0), user_size);
+	/*
+	 * Chunk 0 mapping
+	 */
+	if (remap_size <= 0) {
+		mfc_err("invalid remap size of chunk 0\n");
+		return -EINVAL;
+	}
+
+	pfn = __phys_to_pfn(mfc_mem_data_base(0));
+	if (remap_pfn_range(vma, vma->vm_start + remap_offset, pfn,
+				remap_size, vma->vm_page_prot)) {
+
+		mfc_err("failed to remap chunk 0\n");
+		return -EINVAL;
+	}
+
+	/* skip the hole between the chunk */
+	remap_offset += remap_size;
+	remap_size = min((unsigned long)mfc_mem_hole_size(),
+			user_size - remap_offset);
+
+	remap_offset += remap_size;
+	remap_size = min((unsigned long)mfc_mem_data_size(1),
+			user_size - remap_offset);
+	/*
+	 * Chunk 1 mapping if it's available
+	 */
+	if (remap_size > 0) {
+		pfn = __phys_to_pfn(mfc_mem_data_base(1));
+		if (remap_pfn_range(vma, vma->vm_start + remap_offset, pfn,
+					remap_size, vma->vm_page_prot)) {
+
+			mfc_err("failed to remap chunk 1\n");
+			return -EINVAL;
+		}
+	}
+#else
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	if (mfc_ctx->buf_cache_type == NO_CACHE)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	mfc_info("MFC buffers are %scacheable\n",
+			mfc_ctx->buf_cache_type ? "" : "non-");
+
+	if (dev->mem_ports == 1) {
+		remap_offset = 0;
+		remap_size = min((unsigned long)mfc_mem_data_size(0), user_size);
+		/*
+		 * Port 0 mapping for stream buf & frame buf (chroma + MV + luma)
+		 */
+		pfn = __phys_to_pfn(mfc_mem_data_base(0));
+		if (remap_pfn_range(vma, vma->vm_start + remap_offset, pfn,
+			remap_size, vma->vm_page_prot)) {
+
+			mfc_err("failed to remap port 0\n");
+			return -EINVAL;
+		}
+	} else {
+		remap_offset = 0;
+		remap_size = min((unsigned long)mfc_mem_data_size(0), user_size);
+		/*
+		 * Port 0 mapping for stream buf & frame buf (chroma + MV)
+		 */
+		pfn = __phys_to_pfn(mfc_mem_data_base(0));
+		if (remap_pfn_range(vma, vma->vm_start + remap_offset, pfn,
+			remap_size, vma->vm_page_prot)) {
+
+			mfc_err("failed to remap port 0\n");
+			return -EINVAL;
+		}
+
+		remap_offset = remap_size;
+		remap_size = min((unsigned long)mfc_mem_data_size(1),
+			user_size - remap_offset);
+		/*
+		 * Port 1 mapping for frame buf (luma)
+		 */
+		pfn = __phys_to_pfn(mfc_mem_data_base(1));
+		if (remap_pfn_range(vma, vma->vm_start + remap_offset, pfn,
+			remap_size, vma->vm_page_prot)) {
+
+			mfc_err("failed to remap port 1\n");
+			return -EINVAL;
+		}
+	}
+#endif
+	mfc_ctx->userbase = vma->vm_start;
+
+	mfc_dbg("user request mem = %ld, available data mem = %ld\n",
+		  user_size, real_size);
+
+	if ((remap_offset + remap_size) < real_size)
+		mfc_warn("The MFC reserved memory dose not mmap fully [%ld: %ld]\n",
+		  real_size, (remap_offset + remap_size));
+#endif	/* end of SYSMMU_MFC_ON */
+	return 0;
+}
+
+static const struct file_operations mfc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= mfc_open,
+	.release	= mfc_release,
+	.unlocked_ioctl	= mfc_ioctl,
+	.mmap		= mfc_mmap,
+};
+
+static struct miscdevice mfc_miscdev = {
+	.minor	= MFC_MINOR,
+	.name	= MFC_DEV_NAME,
+	.fops	= &mfc_fops,
+};
+
+static void mfc_firmware_request_complete_handler(const struct firmware *fw,
+						  void *context)
+{
+	if (fw != NULL) {
+		mfcdev->fw.info = fw;
+
+		mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data,
+				mfcdev->fw.info->size);
+		if (mfcdev->fw.state)
+			printk(KERN_INFO "MFC F/W loaded successfully (size: %d)\n", fw->size);
+		else
+			printk(KERN_ERR "failed to load MFC F/W, MFC will not working\n");
+	} else {
+		printk(KERN_INFO "failed to copy MFC F/W during init\n");
+	}
+
+	mfcdev->fw.requesting = 0;
+}
+
+static int proc_read_inst_number(char *buf, char **start,
+								off_t off, int count,
+								int *eof, void *data)
+{
+	int len = 0;
+
+	len += sprintf(buf + len, "%d\n", atomic_read(&mfcdev->inst_cnt));
+
+	return len;
+}
+
+/* FIXME: check every exception case (goto) */
+static int __devinit mfc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	mfcdev = kzalloc(sizeof(struct mfc_dev), GFP_KERNEL);
+	if (unlikely(mfcdev == NULL)) {
+		dev_err(&pdev->dev, "failed to allocate control memory\n");
+		return -ENOMEM;
+	}
+
+	mfc_proc_entry = proc_mkdir(MFC_PROC_ROOT, NULL);
+
+	if (!mfc_proc_entry) {
+		dev_err(&pdev->dev, "unable to create /proc/%s\n",
+			MFC_PROC_ROOT);
+		kfree(mfcdev);
+		return -ENOMEM;
+	}
+
+	if (!create_proc_read_entry(MFC_PROC_TOTAL_INSTANCE_NUMBER, 0,
+				mfc_proc_entry, proc_read_inst_number, NULL)) {
+		dev_err(&pdev->dev, "unable to create /proc/%s/%s\n",
+			MFC_PROC_ROOT, MFC_PROC_TOTAL_INSTANCE_NUMBER);
+		ret = -ENOMEM;
+		goto err_proc;
+	}
+
+	/* init. control structure */
+	sprintf(mfcdev->name, "%s", MFC_DEV_NAME);
+
+	mutex_init(&mfcdev->lock);
+	init_waitqueue_head(&mfcdev->wait_sys);
+	init_waitqueue_head(&mfcdev->wait_codec[0]);
+	init_waitqueue_head(&mfcdev->wait_codec[1]);
+#if SUPPORT_SLICE_ENCODING
+	init_waitqueue_head(&mfcdev->wait_slice);
+	init_waitqueue_head(&mfcdev->wait_frame);
+#endif
+	atomic_set(&mfcdev->inst_cnt, 0);
+#if defined(CONFIG_BUSFREQ)
+	atomic_set(&mfcdev->busfreq_lock_cnt, 0);
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	atomic_set(&mfcdev->cpufreq_lock_cnt, 0);
+	mfcdev->cpufreq_level = 0;
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	atomic_set(&mfcdev->dmcthreshold_lock_cnt, 0);
+#endif
+	mfcdev->device = &pdev->dev;
+#if SUPPORT_SLICE_ENCODING
+	mfcdev->slice_encoding_flag = 0;
+	mfcdev->slice_sys = 0;
+	mfcdev->frame_sys = 0;
+	mfcdev->wait_slice_timeout = 0;
+	mfcdev->wait_frame_timeout = 0;
+#endif
+
+	platform_set_drvdata(pdev, mfcdev);
+
+	/* get the memory region */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (unlikely(res == NULL)) {
+		dev_err(&pdev->dev, "no memory resource specified\n");
+		ret = -ENOENT;
+		goto err_mem_res;
+	}
+
+	mfcdev->reg.rsrc_start = res->start;
+	mfcdev->reg.rsrc_len = resource_size(res);
+
+	/* request mem region for MFC register (0x0000 ~ 0xE008) */
+	res = request_mem_region(mfcdev->reg.rsrc_start,
+			mfcdev->reg.rsrc_len, pdev->name);
+	if (unlikely(res == NULL)) {
+		dev_err(&pdev->dev, "failed to get memory region\n");
+		ret = -ENOENT;
+		goto err_mem_req;
+	}
+
+	/* ioremap for MFC register */
+	mfcdev->reg.base = ioremap(mfcdev->reg.rsrc_start, mfcdev->reg.rsrc_len);
+
+	if (unlikely(!mfcdev->reg.base)) {
+		dev_err(&pdev->dev, "failed to ioremap memory region\n");
+		ret = -EINVAL;
+		goto err_mem_map;
+	}
+
+	init_reg(mfcdev->reg.base);
+
+	mfcdev->irq = platform_get_irq(pdev, 0);
+	if (unlikely(mfcdev->irq < 0)) {
+		dev_err(&pdev->dev, "no irq resource specified\n");
+		ret = -ENOENT;
+		goto err_irq_res;
+	}
+
+	ret = request_irq(mfcdev->irq, mfc_irq, IRQF_DISABLED, mfcdev->name, mfcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to allocate irq (%d)\n", ret);
+		goto err_irq_req;
+	}
+
+	/*
+	 * initialize PM(power, clock) interface
+	 */
+	ret = mfc_init_pm(mfcdev);
+	if (ret < 0) {
+		printk(KERN_ERR "failed to init. MFC PM interface\n");
+		goto err_pm_if;
+	}
+
+	/*
+	 * initialize memory manager
+	 */
+	ret = mfc_init_mem_mgr(mfcdev);
+	if (ret < 0) {
+		printk(KERN_ERR "failed to init. MFC memory manager\n");
+		goto err_mem_mgr;
+	}
+
+	/*
+	 * loading firmware
+	 */
+	mfcdev->fw.requesting = 1;
+	ret = request_firmware_nowait(THIS_MODULE,
+				      FW_ACTION_HOTPLUG,
+				      MFC_FW_NAME,
+				      &pdev->dev,
+				      GFP_KERNEL,
+				      pdev,
+				      mfc_firmware_request_complete_handler);
+	if (ret) {
+		mfcdev->fw.requesting = 0;
+		dev_err(&pdev->dev, "could not load firmware (err=%d)\n", ret);
+		goto err_fw_req;
+	}
+
+#if defined(SYSMMU_MFC_ON) && defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	ret = vcm_activate(mfcdev->vcm_info.sysmmu_vcm);
+	if (ret < 0) {
+		mfc_err("failed to activate VCM: %d", ret);
+
+		goto err_act_vcm;
+	}
+#endif
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* To lock bus frequency in OPP mode */
+	mfcdev->bus_dev = dev_get("exynos-busfreq");
+#endif
+	/*
+	 * initialize buffer manager
+	 */
+	ret = mfc_init_buf();
+	if (ret < 0) {
+		printk(KERN_ERR "failed to init. MFC buffer manager\n");
+		goto err_buf_mgr;
+	}
+
+	/* FIXME: final dec & enc */
+	mfc_init_decoders();
+	mfc_init_encoders();
+
+	ret = misc_register(&mfc_miscdev);
+	if (ret) {
+		mfc_err("MFC can't misc register on minor=%d\n", MFC_MINOR);
+		goto err_misc_reg;
+	}
+
+	if ((soc_is_exynos4212() && (samsung_rev() < EXYNOS4212_REV_1_0)) ||
+		(soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_1)))
+		mfc_pd_enable();
+
+	disable_irq(mfcdev->irq);
+
+	mfc_info("MFC(Multi Function Codec - FIMV v5.x) registered successfully\n");
+
+	return 0;
+
+err_misc_reg:
+	mfc_final_buf();
+
+err_buf_mgr:
+#ifdef SYSMMU_MFC_ON
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	mfc_clock_on(mfcdev);
+
+	vcm_deactivate(mfcdev->vcm_info.sysmmu_vcm);
+
+	mfc_clock_off(mfcdev);
+
+err_act_vcm:
+#endif
+	mfc_clock_on(mfcdev);
+
+	s5p_sysmmu_disable(mfcdev->device);
+
+	mfc_clock_off(mfcdev);
+#endif
+	if (mfcdev->fw.info)
+		release_firmware(mfcdev->fw.info);
+
+err_fw_req:
+	/* FIXME: make kenel dump when probe fail */
+	mfc_clock_on(mfcdev);
+
+	mfc_final_mem_mgr(mfcdev);
+
+	mfc_clock_off(mfcdev);
+
+err_mem_mgr:
+	mfc_final_pm(mfcdev);
+
+err_pm_if:
+	free_irq(mfcdev->irq, mfcdev);
+
+err_irq_req:
+err_irq_res:
+	iounmap(mfcdev->reg.base);
+
+err_mem_map:
+	release_mem_region(mfcdev->reg.rsrc_start, mfcdev->reg.rsrc_len);
+
+err_mem_req:
+err_mem_res:
+	platform_set_drvdata(pdev, NULL);
+	mutex_destroy(&mfcdev->lock);
+	remove_proc_entry(MFC_PROC_TOTAL_INSTANCE_NUMBER, mfc_proc_entry);
+err_proc:
+	remove_proc_entry(MFC_PROC_ROOT, NULL);
+	kfree(mfcdev);
+
+	return ret;
+}
+
+/* FIXME: check mfc_remove funtionalilty */
+static int __devexit mfc_remove(struct platform_device *pdev)
+{
+	struct mfc_dev *dev = platform_get_drvdata(pdev);
+
+	/* FIXME: close all instance? or check active instance? */
+
+	misc_deregister(&mfc_miscdev);
+
+	mfc_final_buf();
+#ifdef SYSMMU_MFC_ON
+	mfc_clock_on(mfcdev);
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	vcm_deactivate(mfcdev->vcm_info.sysmmu_vcm);
+#endif
+
+	s5p_sysmmu_disable(mfcdev->device);
+
+	mfc_clock_off(mfcdev);
+#endif
+	if (dev->fw.info)
+		release_firmware(dev->fw.info);
+	mfc_final_mem_mgr(dev);
+	mfc_final_pm(dev);
+	free_irq(dev->irq, dev);
+	iounmap(dev->reg.base);
+	release_mem_region(dev->reg.rsrc_start, dev->reg.rsrc_len);
+	platform_set_drvdata(pdev, NULL);
+	mutex_destroy(&dev->lock);
+	remove_proc_entry(MFC_PROC_TOTAL_INSTANCE_NUMBER, mfc_proc_entry);
+	remove_proc_entry(MFC_PROC_ROOT, NULL);
+	kfree(dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mfc_suspend(struct device *dev)
+{
+	struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int ret;
+
+	if (atomic_read(&m_dev->inst_cnt) == 0)
+		return 0;
+
+	mutex_lock(&m_dev->lock);
+
+	ret = mfc_sleep(m_dev);
+
+	mutex_unlock(&m_dev->lock);
+
+	if (ret != MFC_OK)
+		return ret;
+
+	return 0;
+}
+
+static int mfc_resume(struct device *dev)
+{
+	struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int ret;
+
+	if (atomic_read(&m_dev->inst_cnt) == 0)
+		return 0;
+
+#ifdef SYSMMU_MFC_ON
+	mfc_clock_on(dev);
+
+	s5p_sysmmu_enable(dev);
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	vcm_set_pgtable_base(VCM_DEV_MFC);
+#else /* CONFIG_S5P_VMEM or kernel virtual memory allocator */
+	s5p_sysmmu_set_tablebase_pgd(dev, __pa(swapper_pg_dir));
+#endif
+
+	mfc_clock_off(mfcdev);
+#endif
+
+	mutex_lock(&m_dev->lock);
+
+	if (soc_is_exynos4210())
+		mfc_pd_enable();
+
+	ret = mfc_wakeup(m_dev);
+
+	mutex_unlock(&m_dev->lock);
+
+	if (ret != MFC_OK)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int mfc_runtime_suspend(struct device *dev)
+{
+	struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+
+	atomic_set(&m_dev->pm.power, 0);
+
+	return 0;
+}
+
+static int mfc_runtime_idle(struct device *dev)
+{
+	return 0;
+}
+
+static int mfc_runtime_resume(struct device *dev)
+{
+	struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev));
+	int pre_power;
+
+	pre_power = atomic_read(&m_dev->pm.power);
+	atomic_set(&m_dev->pm.power, 1);
+
+#ifdef SYSMMU_MFC_ON
+	if (pre_power == 0) {
+		mfc_clock_on(dev);
+
+		s5p_sysmmu_enable(dev);
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+		vcm_set_pgtable_base(VCM_DEV_MFC);
+#else /* CONFIG_S5P_VMEM or kernel virtual memory allocator */
+		s5p_sysmmu_set_tablebase_pgd(dev, __pa(swapper_pg_dir));
+#endif
+
+		mfc_clock_off(dev);
+	}
+#endif
+
+	return 0;
+}
+#endif
+
+#else
+#define mfc_suspend NULL
+#define mfc_resume NULL
+#ifdef CONFIG_PM_RUNTIME
+#define mfc_runtime_idle	NULL
+#define mfc_runtime_suspend	NULL
+#define mfc_runtime_resume	NULL
+#endif
+#endif
+
+static const struct dev_pm_ops mfc_pm_ops = {
+	.suspend		= mfc_suspend,
+	.resume			= mfc_resume,
+#ifdef CONFIG_PM_RUNTIME
+	.runtime_idle		= mfc_runtime_idle,
+	.runtime_suspend	= mfc_runtime_suspend,
+	.runtime_resume		= mfc_runtime_resume,
+#endif
+};
+
+static struct platform_driver mfc_driver = {
+	.probe		= mfc_probe,
+	.remove		= __devexit_p(mfc_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= MFC_DEV_NAME,
+		.pm	= &mfc_pm_ops,
+	},
+};
+
+static int __init mfc_init(void)
+{
+	if (platform_driver_register(&mfc_driver) != 0) {
+		printk(KERN_ERR "FIMV MFC platform device registration failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static void __exit mfc_exit(void)
+{
+	platform_driver_unregister(&mfc_driver);
+	mfc_info("FIMV MFC(Multi Function Codec) V5.x exit\n");
+}
+
+module_init(mfc_init);
+module_exit(mfc_exit);
+
+MODULE_AUTHOR("Jeongtae, Park");
+MODULE_AUTHOR("Jaeryul, Oh");
+MODULE_DESCRIPTION("FIMV MFC(Multi Function Codec) V5.x Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/mfc5x/mfc_dev.h b/drivers/media/video/samsung/mfc5x/mfc_dev.h
new file mode 100644
index 0000000..c82c26c
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_dev.h
@@ -0,0 +1,130 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_dev.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Driver interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_DEV_H
+#define __MFC_DEV_H __FILE__
+
+#include <linux/mutex.h>
+#include <linux/firmware.h>
+
+#include "mfc_inst.h"
+
+#define MFC_DEV_NAME	"s3c-mfc"
+#define MFC_NAME_LEN	16
+
+struct mfc_reg {
+	resource_size_t	rsrc_start;
+	resource_size_t	rsrc_len;
+	void __iomem	*base;
+};
+
+struct mfc_pm {
+	char		pd_name[MFC_NAME_LEN];
+	char		clk_name[MFC_NAME_LEN];
+	struct clk	*clock;
+	atomic_t	power;
+#ifdef CONFIG_PM_RUNTIME
+	struct device	*device;
+#endif
+};
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+struct mfc_vcm {
+	struct vcm	*sysmmu_vcm;
+	unsigned long	*sysmmu_pgd;
+};
+#endif
+
+struct mfc_mem {
+	unsigned long	base;	/* phys. or virt. addr for MFC	*/
+	size_t		size;	/* total size			*/
+	unsigned char	*addr;	/* kernel virtual address space */
+#if (defined(SYSMMU_MFC_ON) && !defined(CONFIG_VIDEO_MFC_VCM_UMP) && !defined(CONFIG_S5P_VMEM))
+	void		*vmalloc_addr;	/* not aligned vmalloc alloc. addr */
+#endif
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	struct vcm_res	*vcm_s;
+#endif
+};
+
+struct mfc_fw {
+	const struct firmware	*info;
+	int			requesting;
+	int			state;
+	int			ver;
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	struct vcm_mmu_res	*vcm_s;
+	struct vcm_res		*vcm_k;
+#elif defined(CONFIG_S5P_VMEM)
+	int			vmem_cookie;
+#endif
+};
+
+struct mfc_dev {
+	char			name[MFC_NAME_LEN];
+	struct mfc_reg		reg;
+	int			irq;
+	struct mfc_pm		pm;
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	struct mfc_vcm		vcm_info;
+#endif
+	int			mem_ports;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	struct mfc_mem		mem_infos[MFC_MAX_MEM_CHUNK_NUM];
+	struct mfc_mem		drm_info;
+#else
+	struct mfc_mem		mem_infos[MFC_MAX_MEM_PORT_NUM];
+#endif
+
+	atomic_t		inst_cnt;
+	struct mfc_inst_ctx	*inst_ctx[MFC_MAX_INSTANCE_NUM];
+
+	struct mutex		lock;
+	wait_queue_head_t	wait_sys;
+	int			irq_sys;
+	/* FIXME: remove or use 2 codec channel */
+	wait_queue_head_t	wait_codec[2];
+	int			irq_codec[2];
+
+	struct mfc_fw		fw;
+
+	struct s5p_vcm_mmu	*_vcm_mmu;
+
+	struct device		*device;
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	struct device           *bus_dev;
+#endif
+#if defined(CONFIG_BUSFREQ)
+	atomic_t		busfreq_lock_cnt; /* Bus frequency Lock count */
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	atomic_t		cpufreq_lock_cnt; /* CPU frequency Lock count */
+	int				cpufreq_level; /* CPU frequency leve */
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	atomic_t  dmcthreshold_lock_cnt; /* dmc max threshold Lock count */
+#endif
+#if SUPPORT_SLICE_ENCODING
+	int			slice_encoding_flag;
+	wait_queue_head_t	wait_slice;
+	int			slice_sys;
+	int			wait_slice_timeout;
+	int			frame_working_flag;
+	wait_queue_head_t	wait_frame;
+	int			frame_sys;
+	int			wait_frame_timeout;
+#endif
+};
+
+#endif /* __MFC_DEV_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_enc.c b/drivers/media/video/samsung/mfc5x/mfc_enc.c
new file mode 100644
index 0000000..53f24c9
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_enc.c
@@ -0,0 +1,1792 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_enc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Encoder interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/cacheflush.h>
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#if defined(CONFIG_BUSFREQ) || defined(CONFIG_EXYNOS4_CPUFREQ)
+#include <mach/cpufreq.h>
+#endif
+#include <mach/regs-mfc.h>
+
+#include "mfc_enc.h"
+#include "mfc_cmd.h"
+#include "mfc_log.h"
+
+#include "mfc_shm.h"
+#include "mfc_reg.h"
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+#include "mfc_interface.h"
+
+static LIST_HEAD(mfc_encoders);
+
+/*
+ * [1] alloc_ctx_buf() implementations
+ */
+ static int alloc_ctx_buf(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_CTX_SIZE, ALIGN_2KB, MBT_CTX | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc context buffer\n");
+
+		return -1;
+	}
+
+	ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
+	ctx->ctxbufsize = alloc->size;
+
+	memset((void *)alloc->addr, 0, alloc->size);
+
+	mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
+
+	return 0;
+}
+
+/*
+ * [2] get_init_arg() implementations
+ */
+int get_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_enc_init_arg *init_arg;
+	struct mfc_enc_ctx *enc_ctx;
+	unsigned int reg;
+
+	init_arg = (struct mfc_enc_init_arg *)arg;
+	enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	enc_ctx->inputformat = init_arg->cmn.in_frame_map;
+
+	/* Check input stream mode NV12_LINEAR OR NV12_TILE */
+	if (init_arg->cmn.in_frame_map == NV12_TILE)
+		enc_ctx->framemap = 3;	/* MFC_ENC_MAP_FOR_CUR 0: Linear mode 3: Tile mode */
+	else
+		enc_ctx->framemap = 0;	/* Default is Linear mode */
+#if SUPPORT_SLICE_ENCODING
+	enc_ctx->outputmode = init_arg->cmn.in_output_mode ? 1 : 0;
+#endif
+
+	/* width */
+	write_reg(init_arg->cmn.in_width, MFC_ENC_HSIZE_PX);
+	/* height */
+	write_reg(init_arg->cmn.in_height, MFC_ENC_VSIZE_PX);
+
+	/* FIXME: MFC_B_RECON_*_ADR */
+	write_reg(0, MFC_ENC_B_RECON_WRITE_ON);
+
+	/* multi-slice control 0 / 1 / 3 */
+	/* multi-slice MB number or multi-slice bit size */
+	if (init_arg->cmn.in_ms_mode == 1) {
+		write_reg((0 << 1) | 0x1, MFC_ENC_MSLICE_CTRL);
+		write_reg(init_arg->cmn.in_ms_arg & 0xFFFF, MFC_ENC_MSLICE_MB);
+	} else if (init_arg->cmn.in_ms_mode == 2) {
+		write_reg((1 << 1) | 0x1, MFC_ENC_MSLICE_CTRL);
+		if (init_arg->cmn.in_ms_arg < 1900)
+			init_arg->cmn.in_ms_arg = 1900;
+		write_reg(init_arg->cmn.in_ms_arg, MFC_ENC_MSLICE_BIT);
+	} else {
+		write_reg(0, MFC_ENC_MSLICE_CTRL);
+		write_reg(0, MFC_ENC_MSLICE_MB);
+		write_reg(0, MFC_ENC_MSLICE_BIT);
+	}
+#if SUPPORT_SLICE_ENCODING
+	/* slice interface */
+	write_reg((enc_ctx->outputmode) << 31, MFC_ENC_SI_CH1_INPUT_FLUSH);
+#endif
+
+	/* cyclic intra refresh */
+	write_reg(init_arg->cmn.in_mb_refresh & 0xFFFF, MFC_ENC_CIR_CTRL);
+	/* memory structure of the current frame - 0 -> Linear  or 3 -> Tile mode */
+	write_reg(enc_ctx->framemap, MFC_ENC_MAP_FOR_CUR);
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	if (init_arg->cmn.in_frame_map == NV21_LINEAR)
+		 write_reg(1, MFC_ENC_NV21_SEL);
+	else if (init_arg->cmn.in_frame_map == NV12_LINEAR)
+		 write_reg(0, MFC_ENC_NV21_SEL);
+#endif
+
+	/* padding control & value */
+	reg = read_reg(MFC_ENC_PADDING_CTRL);
+	if (init_arg->cmn.in_pad_ctrl_on > 0) {
+		/** enable */
+		reg |= (1 << 31);
+		/** cr value */
+		reg &= ~(0xFF << 16);
+		reg |= ((init_arg->cmn.in_cr_pad_val & 0xFF) << 16);
+		/** cb value */
+		reg &= ~(0xFF << 8);
+		reg |= ((init_arg->cmn.in_cb_pad_val & 0xFF) << 8);
+		/** y value */
+		reg &= ~(0xFF << 0);
+		reg |= ((init_arg->cmn.in_y_pad_val & 0xFF) << 0);
+	} else {
+		/** disable & all value clear */
+		reg = 0;
+	}
+	write_reg(reg, MFC_ENC_PADDING_CTRL);
+
+	/* reaction coefficient */
+	if (init_arg->cmn.in_rc_fr_en > 0) {
+		if (init_arg->cmn.in_rc_rpara != 0)
+			write_reg(init_arg->cmn.in_rc_rpara & 0xFFFF, MFC_ENC_RC_RPARA);
+	} else {
+		write_reg(0, MFC_ENC_RC_RPARA);
+	}
+
+	/* FIXME: update shm parameters? */
+
+	return 0;
+}
+
+int h263_get_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_enc_init_arg *init_arg;
+	struct mfc_enc_init_h263_arg *init_h263_arg;
+	unsigned int reg;
+	unsigned int shm;
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;;
+
+	get_init_arg(ctx, arg);
+
+	init_arg = (struct mfc_enc_init_arg *)arg;
+	init_h263_arg = &init_arg->codec.h263;
+
+	enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	enc_ctx->numdpb = 2;
+
+	/* pictype : number of B, IDR period */
+	reg = read_reg(MFC_ENC_PIC_TYPE_CTRL);
+	/** enable - 0 / 1*/
+	reg |= (1 << 18);
+	/** numbframe - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	/** idrperiod - 0 ~ */
+	reg &= ~(0xFFFF << 0);
+	reg |= ((init_arg->cmn.in_gop_num & 0xFFFF) << 0);
+	write_reg(reg, MFC_ENC_PIC_TYPE_CTRL);
+
+	/* rate control config. */
+	reg = read_reg(MFC_ENC_RC_CONFIG);
+	/** frame-level rate control */
+	reg &= ~(0x1 << 9);
+	reg |= ((init_arg->cmn.in_rc_fr_en & 0x1) << 9);
+	/** macroblock-level rate control */
+	reg &= ~(0x1 << 8);
+	/** frame QP */
+	if (init_arg->cmn.in_vop_quant < 1)
+		init_arg->cmn.in_vop_quant = 1;
+	else if (init_arg->cmn.in_vop_quant > 31)
+		init_arg->cmn.in_vop_quant = 31;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_vop_quant & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_CONFIG);
+
+	/* frame rate and bit rate */
+	if (init_arg->cmn.in_rc_fr_en > 0) {
+		if (init_h263_arg->in_rc_framerate != 0)
+			write_reg(init_h263_arg->in_rc_framerate * 1000,
+				MFC_ENC_RC_FRAME_RATE);
+
+		if (init_arg->cmn.in_rc_bitrate != 0)
+			write_reg(init_arg->cmn.in_rc_bitrate,
+				MFC_ENC_RC_BIT_RATE);
+	} else {
+		write_reg(0, MFC_ENC_RC_FRAME_RATE);
+		write_reg(0, MFC_ENC_RC_BIT_RATE);
+	}
+
+	/* max & min value of QP */
+	reg = read_reg(MFC_ENC_RC_QBOUND);
+	/** max QP */
+	if (init_arg->cmn.in_rc_qbound_max < 1)
+		init_arg->cmn.in_rc_qbound_max = 1;
+	else if (init_arg->cmn.in_rc_qbound_max > 31)
+		init_arg->cmn.in_rc_qbound_max = 31;
+	reg &= ~(0x3F << 8);
+	reg |= ((init_arg->cmn.in_rc_qbound_max & 0x3F) << 8);
+	/** min QP */
+	if (init_arg->cmn.in_rc_qbound_min < 1)
+		init_arg->cmn.in_rc_qbound_min = 1;
+	else if (init_arg->cmn.in_rc_qbound_min > 31)
+		init_arg->cmn.in_rc_qbound_min = 31;
+	if (init_arg->cmn.in_rc_qbound_min > init_arg->cmn.in_rc_qbound_max)
+		init_arg->cmn.in_rc_qbound_min = init_arg->cmn.in_rc_qbound_max;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_rc_qbound_min & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_QBOUND);
+
+	if (init_arg->cmn.in_rc_fr_en == 0) {
+		shm = read_shm(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF << 0);
+		shm |= ((init_arg->cmn.in_vop_quant_p & 0x3F) << 0);
+		write_shm(ctx, shm, P_B_FRAME_QP);
+	}
+
+	return 0;
+}
+
+int mpeg4_get_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_enc_init_arg *init_arg;
+	struct mfc_enc_init_mpeg4_arg *init_mpeg4_arg;
+	unsigned int reg;
+	unsigned int shm;
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	get_init_arg(ctx, arg);
+
+	init_arg = (struct mfc_enc_init_arg *)arg;
+	init_mpeg4_arg = &init_arg->codec.mpeg4;
+
+	if (init_mpeg4_arg->in_bframenum > 0)
+		enc_ctx->numdpb = 4;
+	else
+		enc_ctx->numdpb = 2;
+
+	/* profile & level */
+	reg = read_reg(MFC_ENC_PROFILE);
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= ((init_mpeg4_arg->in_level & 0xFF) << 8);
+	/** profile - 0 ~ 2 */
+	reg &= ~(0x3 << 0);
+	reg |= ((init_mpeg4_arg->in_profile & 0x3) << 0);
+	write_reg(reg, MFC_ENC_PROFILE);
+
+	/* pictype : number of B, IDR period */
+	reg = read_reg(MFC_ENC_PIC_TYPE_CTRL);
+	/** enable - 0 / 1*/
+	reg |= (1 << 18);
+	/** numbframe - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= ((init_mpeg4_arg->in_bframenum & 0x3) << 16);
+	/** idrperiod - 0 ~ */
+	reg &= ~(0xFFFF << 0);
+	reg |= ((init_arg->cmn.in_gop_num & 0xFFFF) << 0);
+	write_reg(reg, MFC_ENC_PIC_TYPE_CTRL);
+
+	/* rate control config. */
+	reg = read_reg(MFC_ENC_RC_CONFIG);
+	/** frame-level rate control */
+	reg &= ~(0x1 << 9);
+	reg |= ((init_arg->cmn.in_rc_fr_en & 0x1) << 9);
+	/** macroblock-level rate control */
+	reg &= ~(0x1 << 8);
+	/** frame QP */
+	if (init_arg->cmn.in_vop_quant < 1)
+		init_arg->cmn.in_vop_quant = 1;
+	else if (init_arg->cmn.in_vop_quant > 31)
+		init_arg->cmn.in_vop_quant = 31;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_vop_quant & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_CONFIG);
+
+	/* frame rate and bit rate */
+	if (init_arg->cmn.in_rc_fr_en > 0) {
+		if (init_mpeg4_arg->in_VopTimeIncreament > 0)
+			write_reg((init_mpeg4_arg->in_TimeIncreamentRes /
+				init_mpeg4_arg->in_VopTimeIncreament) * 1000,
+				MFC_ENC_RC_FRAME_RATE);
+
+		if (init_arg->cmn.in_rc_bitrate != 0)
+			write_reg(init_arg->cmn.in_rc_bitrate,
+				MFC_ENC_RC_BIT_RATE);
+	} else {
+		write_reg(0, MFC_ENC_RC_FRAME_RATE);
+		write_reg(0, MFC_ENC_RC_BIT_RATE);
+	}
+
+	/* max & min value of QP */
+	reg = read_reg(MFC_ENC_RC_QBOUND);
+	/** max QP */
+	if (init_arg->cmn.in_rc_qbound_max < 1)
+		init_arg->cmn.in_rc_qbound_max = 1;
+	else if (init_arg->cmn.in_rc_qbound_max > 31)
+		init_arg->cmn.in_rc_qbound_max = 31;
+	reg &= ~(0x3F << 8);
+	reg |= ((init_arg->cmn.in_rc_qbound_max & 0x3F) << 8);
+	/** min QP */
+	if (init_arg->cmn.in_rc_qbound_min < 1)
+		init_arg->cmn.in_rc_qbound_min = 1;
+	else if (init_arg->cmn.in_rc_qbound_min > 31)
+		init_arg->cmn.in_rc_qbound_min = 31;
+	if (init_arg->cmn.in_rc_qbound_min > init_arg->cmn.in_rc_qbound_max)
+		init_arg->cmn.in_rc_qbound_min = init_arg->cmn.in_rc_qbound_max;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_rc_qbound_min & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_QBOUND);
+
+	write_reg(init_mpeg4_arg->in_quart_pixel, MFC_ENC_MPEG4_QUART_PXL);
+
+	if (init_arg->cmn.in_rc_fr_en == 0) {
+		shm = read_shm(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF << 0);
+		shm |= ((init_mpeg4_arg->in_vop_quant_b & 0x3F) << 6);
+		shm |= ((init_arg->cmn.in_vop_quant_p & 0x3F) << 0);
+		write_shm(ctx, shm, P_B_FRAME_QP);
+	}
+
+	return 0;
+}
+
+int h264_get_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_enc_init_arg *init_arg;
+	struct mfc_enc_init_h264_arg *init_h264_arg;
+	unsigned int reg;
+	unsigned int shm;
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	get_init_arg(ctx, arg);
+
+	init_arg = (struct mfc_enc_init_arg *)arg;
+	init_h264_arg = &init_arg->codec.h264;
+
+	if ((init_h264_arg->in_bframenum > 0) || (init_h264_arg->in_ref_num_p > 1))
+		enc_ctx->numdpb = 4;
+	else
+		enc_ctx->numdpb = 2;
+
+	/* height */
+	if (init_h264_arg->in_interlace_mode)
+		write_reg(init_arg->cmn.in_height >> 1, MFC_ENC_VSIZE_PX);
+	else
+		write_reg(init_arg->cmn.in_height, MFC_ENC_VSIZE_PX);
+
+	/* profile & level */
+	reg = read_reg(MFC_ENC_PROFILE);
+	/** level */
+	reg &= ~(0xFF << 8);
+	reg |= ((init_h264_arg->in_level & 0xFF) << 8);
+	/** profile - 0 ~ 2 */
+	reg &= ~(0x3 << 0);
+	reg |= ((init_h264_arg->in_profile & 0x3) << 0);
+	/* set constraint_set0_flag */
+	reg |= (1 << 3);
+	write_reg(reg, MFC_ENC_PROFILE);
+
+	/* interface - 0 / 1 */
+	write_reg(init_h264_arg->in_interlace_mode & 0x1, MFC_ENC_PIC_STRUCT);
+
+	/* loopfilter disable - 0 ~ 2 */
+	write_reg((init_h264_arg->in_deblock_dis & 0x3), MFC_ENC_LF_CTRL);
+
+	/* loopfilter alpha & C0 offset - -6 ~ 6 */
+	write_reg((init_h264_arg->in_deblock_alpha_c0 & 0x1F) * 2, MFC_ENC_ALPHA_OFF);
+
+	/* loopfilter beta offset - -6 ~ 6 */
+	write_reg((init_h264_arg->in_deblock_beta & 0x1F) * 2, MFC_ENC_BETA_OFF);
+
+	/* pictype : number of B, IDR period */
+	reg = read_reg(MFC_ENC_PIC_TYPE_CTRL);
+	/** enable - 0 / 1*/
+	reg |= (1 << 18);
+	/** numbframe - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= ((init_h264_arg->in_bframenum & 0x3) << 16);
+	/** idrperiod - 0 ~ */
+	reg &= ~(0xFFFF << 0);
+	reg |= ((init_arg->cmn.in_gop_num & 0xFFFF) << 0);
+	write_reg(reg, MFC_ENC_PIC_TYPE_CTRL);
+
+	/* rate control config. */
+	reg = read_reg(MFC_ENC_RC_CONFIG);
+	/** frame-level rate control */
+	reg &= ~(0x1 << 9);
+	reg |= ((init_arg->cmn.in_rc_fr_en & 0x1) << 9);
+	/** macroblock-level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= ((init_h264_arg->in_rc_mb_en & 0x1) << 8);
+	/** frame QP */
+	if (init_arg->cmn.in_vop_quant < 1)
+		init_arg->cmn.in_vop_quant = 1;
+	else if (init_arg->cmn.in_vop_quant > 51)
+		init_arg->cmn.in_vop_quant = 51;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_vop_quant & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_CONFIG);
+
+	/* frame rate and bit rate */
+	if (init_arg->cmn.in_rc_fr_en > 0) {
+		if (init_h264_arg->in_rc_framerate != 0)
+			write_reg(init_h264_arg->in_rc_framerate * 1000,
+				MFC_ENC_RC_FRAME_RATE);
+
+		if (init_arg->cmn.in_rc_bitrate != 0)
+			write_reg(init_arg->cmn.in_rc_bitrate,
+				MFC_ENC_RC_BIT_RATE);
+	} else {
+		write_reg(0, MFC_ENC_RC_FRAME_RATE);
+		write_reg(0, MFC_ENC_RC_BIT_RATE);
+	}
+
+	/* max & min value of QP */
+	reg = read_reg(MFC_ENC_RC_QBOUND);
+	/** max QP */
+	if (init_arg->cmn.in_rc_qbound_max < 1)
+		init_arg->cmn.in_rc_qbound_max = 1;
+	else if (init_arg->cmn.in_rc_qbound_max > 51)
+		init_arg->cmn.in_rc_qbound_max = 51;
+	reg &= ~(0x3F << 8);
+	reg |= ((init_arg->cmn.in_rc_qbound_max & 0x3F) << 8);
+	/** min QP */
+	if (init_arg->cmn.in_rc_qbound_min < 1)
+		init_arg->cmn.in_rc_qbound_min = 1;
+	else if (init_arg->cmn.in_rc_qbound_min > 51)
+		init_arg->cmn.in_rc_qbound_min = 51;
+	if (init_arg->cmn.in_rc_qbound_min > init_arg->cmn.in_rc_qbound_max)
+		init_arg->cmn.in_rc_qbound_min = init_arg->cmn.in_rc_qbound_max;
+	reg &= ~(0x3F << 0);
+	reg |= ((init_arg->cmn.in_rc_qbound_min & 0x3F) << 0);
+	write_reg(reg, MFC_ENC_RC_QBOUND);
+
+	/* macroblock adaptive scaling features */
+	if (init_h264_arg->in_rc_mb_en > 0) {
+		reg = read_reg(MFC_ENC_RC_MB_CTRL);
+		/** dark region */
+		reg &= ~(0x1 << 3);
+		reg |= ((init_h264_arg->in_rc_mb_dark_dis & 0x1) << 3);
+		/** smooth region */
+		reg &= ~(0x1 << 2);
+		reg |= ((init_h264_arg->in_rc_mb_smooth_dis & 0x1) << 2);
+		/** static region */
+		reg &= ~(0x1 << 1);
+		reg |= ((init_h264_arg->in_rc_mb_static_dis & 0x1) << 1);
+		/** high activity region */
+		reg &= ~(0x1 << 0);
+		reg |= ((init_h264_arg->in_rc_mb_activity_dis & 0x1) << 0);
+		write_reg(reg, MFC_ENC_RC_MB_CTRL);
+	}
+
+	/* entropy coding mode 0: CAVLC, 1: CABAC */
+	write_reg(init_h264_arg->in_symbolmode & 0x1, MFC_ENC_H264_ENTRP_MODE);
+
+	/* number of ref. picture */
+	reg = read_reg(MFC_ENC_H264_NUM_OF_REF);
+	/** num of ref. pictures of P */
+	reg &= ~(0x3 << 5);
+	reg |= ((init_h264_arg->in_ref_num_p & 0x3) << 5);
+	write_reg(reg, MFC_ENC_H264_NUM_OF_REF);
+
+	/* 8x8 transform enable */
+	write_reg(init_h264_arg->in_transform8x8_mode & 0x1, MFC_ENC_H264_TRANS_FLAG);
+
+	if ((init_arg->cmn.in_rc_fr_en == 0) && (init_h264_arg->in_rc_mb_en == 0)) {
+		shm = read_shm(ctx, P_B_FRAME_QP);
+		shm &= ~(0xFFF << 0);
+		shm |= ((init_h264_arg->in_vop_quant_b & 0x3F) << 6);
+		shm |= ((init_arg->cmn.in_vop_quant_p & 0x3F) << 0);
+		write_shm(ctx, shm, P_B_FRAME_QP);
+	}
+
+	return 0;
+}
+
+/*
+ * [3] pre_seq_start() implementations
+ */
+static int pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	/* Set stream buffer addr */
+	write_reg(mfc_mem_base_ofs(enc_ctx->streamaddr) >> 11, MFC_ENC_SI_CH1_SB_ADR);
+	write_reg(enc_ctx->streamsize, MFC_ENC_SI_CH1_SB_SIZE);
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	write_shm(ctx, 1, HW_VERSRION);
+#endif
+
+	return 0;
+}
+
+static int h264_pre_seq_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	struct mfc_enc_h264 *h264 = (struct mfc_enc_h264 *)enc_ctx->e_priv;
+	unsigned int shm;
+
+	pre_seq_start(ctx);
+
+	/*
+	unsigned int reg;
+	*/
+
+	#if 0
+	/* MFC fw 9/30, set the QP for P/B */
+	if (mfc_ctx->MfcCodecType == H263_ENC)
+		init_arg->in_vop_quant_b = 0;
+	write_shm((init_arg->
+			   in_vop_quant_p) | (init_arg->in_vop_quant_b << 6),
+			  mfc_ctx->shared_mem_vir_addr + 0x70);
+
+	/* MFC fw 11/10 */
+	if (mfc_ctx->MfcCodecType == H264_ENC) {
+		write_shm((mfc_ctx->vui_enable << 15) |
+				  (mfc_ctx->hier_p_enable << 4) |
+				  (mfc_ctx->frameSkipEnable << 1),
+				  mfc_ctx->shared_mem_vir_addr + 0x28);
+		if (mfc_ctx->vui_enable)
+			write_shm((mfc_ctx->
+					   vui_info.aspect_ratio_idc & 0xff),
+					  mfc_ctx->shared_mem_vir_addr + 0x74);
+		/* MFC fw 2010/04/09 */
+		if (mfc_ctx->hier_p_enable)
+			write_shm((mfc_ctx->hier_p_qp.t3_frame_qp << 12) |
+					  (mfc_ctx->hier_p_qp.t2_frame_qp << 6) |
+					  (mfc_ctx->hier_p_qp.t0_frame_qp),
+					  mfc_ctx->shared_mem_vir_addr + 0xe0);
+	} else
+		write_shm((mfc_ctx->frameSkipEnable << 1),
+				  mfc_ctx->shared_mem_vir_addr + 0x28);
+
+	/* MFC fw 10/30, set vop_time_resolution, frame_delta */
+	if (mfc_ctx->MfcCodecType == MPEG4_ENC)
+		write_shm((1 << 31) |
+				  (init_arg->in_TimeIncreamentRes << 16) |
+				  (init_arg->in_VopTimeIncreament),
+				  mfc_ctx->shared_mem_vir_addr + 0x30);
+
+	if ((mfc_ctx->MfcCodecType == H264_ENC)
+	    && (mfc_ctx->h264_i_period_enable)) {
+		write_shm((1 << 16) | (mfc_ctx->h264_i_period),
+				  mfc_ctx->shared_mem_vir_addr + 0x9c);
+	}
+	#endif
+
+	write_shm(ctx, h264->sei_gen << 1, SEI_ENABLE);
+
+	if (h264->change & CHG_FRAME_PACKING) {
+		/* change type value to meet standard */
+		shm = (h264->fp.arrangement_type - 3) & 0x3;
+		/* only valid when type is temporal interleaving (5) */
+		shm |= ((h264->fp.current_frame_is_frame0_flag & 0x1) << 2);
+		write_shm(ctx, shm, FRAME_PACK_ENC_INFO);
+
+		h264->change &= ~(CHG_FRAME_PACKING);
+	}
+
+	return 0;
+}
+
+/*
+ * [4] post_seq_start() implementations
+ */
+static int post_seq_start(struct mfc_inst_ctx *ctx)
+{
+	/*
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	int i;
+	*/
+
+	/*
+	unsigned int shm;
+	*/
+
+	/*
+	mfc_dbg("header size: %d", read_reg(MFC_ENC_SI_STRM_SIZE));
+
+	for (i = 0; i < read_reg(MFC_ENC_SI_STRM_SIZE); i++)
+		mfc_dbg("0x%02x", (unsigned char)(*(enc_ctx->kstrmaddr + i)));
+	*/
+
+	return 0;
+}
+
+/*
+ * [5] set_init_arg() implementations
+ */
+static int set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	struct mfc_enc_init_arg *init_arg = (struct mfc_enc_init_arg *)arg;
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	void *ump_handle;
+#endif
+
+	init_arg->cmn.out_header_size = read_reg(MFC_ENC_SI_STRM_SIZE);
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	init_arg->cmn.out_u_addr.strm_ref_y = 0;
+	ump_handle = mfc_get_buf_ump_handle(enc_ctx->streamaddr);
+
+	mfc_dbg("secure id: 0x%08x", mfc_ump_get_id(ump_handle));
+
+	if (ump_handle != NULL)
+		init_arg->cmn.out_u_addr.strm_ref_y = mfc_ump_get_id(ump_handle);
+	init_arg->cmn.out_u_addr.mv_ref_yc = 0;
+
+#elif defined(CONFIG_S5P_VMEM)
+	mfc_dbg("cookie: 0x%08x", s5p_getcookie((void *)(enc_ctx->streamaddr)));
+
+	init_arg->cmn.out_u_addr.strm_ref_y = s5p_getcookie((void *)(enc_ctx->streamaddr));
+	init_arg->cmn.out_u_addr.mv_ref_yc = 0;
+#else
+	init_arg->cmn.out_u_addr.strm_ref_y = mfc_mem_data_ofs(enc_ctx->streamaddr, 1);
+	init_arg->cmn.out_u_addr.mv_ref_yc = 0;
+	init_arg->cmn.out_p_addr.strm_ref_y = enc_ctx->streamaddr;
+	init_arg->cmn.out_p_addr.mv_ref_yc = 0;
+#endif
+
+	/*
+	init_arg->cmn.out_buf_size.strm_ref_y = 0;
+	init_arg->cmn.out_buf_size.mv_ref_yc = 0;
+
+	init_arg->cmn.out_p_addr.strm_ref_y = 0;
+	init_arg->cmn.out_p_addr.mv_ref_yc = 0;
+	*/
+
+	return 0;
+}
+
+/*
+ * [6] set_codec_bufs() implementations
+ */
+static int set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+static int h264_set_codec_bufs(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_ENC_UPMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_MV_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_ENC_COLFLG_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_COLZERO_FLAG_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_ENC_INTRAMD_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_INTRA_MD_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_ENC_INTRAPRED_SIZE, ALIGN_2KB, MBT_CODEC | PORT_B);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_INTRA_PRED_ADR);
+
+	alloc = _mfc_alloc_buf(ctx, MFC_ENC_NBORINFO_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc codec buffer\n");
+
+		return -1;
+	}
+	write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NBOR_INFO_ADR);
+
+	return 0;
+}
+
+/*
+ * [7] set_dpbs() implementations
+ */
+#if 0
+static int set_dpbs(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+#endif
+
+/*
+ * [8] pre_frame_start() implementations
+ */
+static int pre_frame_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	if (enc_ctx->setflag == 1) {
+		if (enc_ctx->FrameTypeCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - Frame Type : %d\n", enc_ctx->forceframe);
+
+			write_reg(enc_ctx->forceframe, MFC_ENC_SI_CH1_FRAME_INS);
+		}
+
+		if (enc_ctx->FrameRateCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - Frame rate : %d\n", enc_ctx->framerate);
+
+			write_shm(ctx, 1000 * enc_ctx->framerate, NEW_RC_FRAME_RATE);
+			write_shm(ctx, ((1 << 31)|(enc_ctx->framerate << 16)|(1 & 0xFFFF)), VOP_TIMING);
+			write_reg(1000 * enc_ctx->framerate, MFC_ENC_RC_FRAME_RATE);
+			write_shm(ctx, (0x1 << 1), ENC_PARAM_CHANGE);
+		}
+
+		if (enc_ctx->BitRateCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - Bit rate : %d\n", enc_ctx->bitrate);
+
+			write_shm(ctx, enc_ctx->bitrate, NEW_RC_BIT_RATE);
+			write_reg(enc_ctx->bitrate, MFC_ENC_RC_BIT_RATE);
+			write_shm(ctx, (0x1 << 2), ENC_PARAM_CHANGE);
+		}
+	}
+
+	return 0;
+}
+
+static int h264_pre_frame_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	struct mfc_enc_h264 *h264 = (struct mfc_enc_h264 *)enc_ctx->e_priv;
+	unsigned int shm;
+
+	pre_frame_start(ctx);
+
+	if (h264->change & CHG_FRAME_PACKING) {
+		/* change type value to meet standard */
+		shm = (h264->fp.arrangement_type - 3) & 0x3;
+		/* only valid when type is temporal interleaving (5) */
+		shm |= ((h264->fp.current_frame_is_frame0_flag & 0x1) << 2);
+		write_shm(ctx, shm, FRAME_PACK_ENC_INFO);
+
+		h264->change &= ~(CHG_FRAME_PACKING);
+	}
+
+	return 0;
+}
+/*
+ * [9] post_frame_start() implementations
+ */
+static int post_frame_start(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	if (enc_ctx->setflag == 1) {
+		enc_ctx->setflag = 0;
+
+		enc_ctx->FrameTypeCngTag = 0;
+		enc_ctx->FrameRateCngTag = 0;
+		enc_ctx->BitRateCngTag = 0;
+
+		write_shm(ctx, 0, ENC_PARAM_CHANGE);	/*RC_BIT_RATE_CHANGE = 4*/
+		write_reg(0, MFC_ENC_SI_CH1_FRAME_INS);
+	}
+
+	return 0;
+}
+
+/*
+ * [10] multi_frame_start() implementations
+ */
+static int multi_data_frame(struct mfc_inst_ctx *ctx)
+{
+	return 0;
+}
+
+/*
+ * [11] set_exe_arg() implementations
+ */
+static int set_exe_arg(struct mfc_inst_ctx *ctx, void *arg)
+{
+	return 0;
+}
+
+/*
+ * [12] get_codec_cfg() implementations
+ */
+static int get_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	/*struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;*/
+	int ret = 0;
+
+	mfc_dbg("type: 0x%08x", type);
+
+	/*
+	MFC_ENC_GETCONF_FRAME_TAG	= ENC_GET,
+	...
+	*/
+
+	switch (type) {
+
+	default:
+		mfc_dbg("not common cfg, try to codec specific: 0x%08x\n", type);
+		ret = 1;
+
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * [13] set_codec_cfg() implementations
+ */
+static int set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret = 0;
+
+	mfc_dbg("type: 0x%08x", type);
+	/*
+	MFC_ENC_SETCONF_FRAME_TYPE	= ENC_SET,
+	MFC_ENC_SETCONF_CHANGE_FRAME_RATE,
+	MFC_ENC_SETCONF_CHANGE_BIT_RATE,
+	MFC_ENC_SETCONF_FRAME_TAG,
+	MFC_ENC_SETCONF_ALLOW_FRAME_SKIP,
+	MFC_ENC_SETCONF_VUI_INFO,
+	MFC_ENC_SETCONF_I_PERIOD,
+	MFC_ENC_SETCONF_HIER_P,
+	...
+	*/
+
+	switch (type) {
+		case MFC_ENC_SETCONF_FRAME_TYPE:
+			mfc_dbg("MFC_ENC_SETCONF_FRAME_TYPE : %d\n", ctx->state);
+
+			if (ctx->state < INST_STATE_INIT) {
+				mfc_err("MFC_ENC_SETCONF_CHANGE_FRAME_TYPE : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if ((usercfg->basic.values[0] >= DONT_CARE) && (usercfg->basic.values[0] <= NOT_CODED))	{
+				mfc_dbg("Frame Type : %d\n", usercfg->basic.values[0]);
+				enc_ctx->forceframe = usercfg->basic.values[0];
+				enc_ctx->FrameTypeCngTag = 1;
+				enc_ctx->setflag = 1;
+			} else {
+				mfc_warn("FRAME_TYPE should be between 0 and 2\n");
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_CHANGE_FRAME_RATE:
+			mfc_dbg("MFC_ENC_SETCONF_CHANGE_FRAME_RATE : %d\n", ctx->state);
+
+			if (ctx->state < INST_STATE_INIT) {
+				mfc_err("MFC_ENC_SETCONF_CHANGE_FRAME_RATE : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0] > 0) {
+				mfc_dbg("Frame rate : %d\n", usercfg->basic.values[0]);
+				enc_ctx->framerate = usercfg->basic.values[0];
+				enc_ctx->FrameRateCngTag = 1;
+				enc_ctx->setflag = 1;
+			} else {
+				mfc_warn("MFCSetConfig, FRAME_RATE should be biger than 0\n");
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_CHANGE_BIT_RATE:
+			mfc_dbg("MFC_ENC_SETCONF_CHANGE_BIT_RATE : %d\n", ctx->state);
+
+			if (ctx->state < INST_STATE_INIT) {
+				mfc_err("MFC_ENC_SETCONF_CHANGE_BIT_RATE : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0] > 0) {
+				mfc_dbg("Bit rate : %d\n", usercfg->basic.values[0]);
+				enc_ctx->bitrate = usercfg->basic.values[0];
+				enc_ctx->BitRateCngTag = 1;
+				enc_ctx->setflag = 1;
+			} else {
+				mfc_warn("MFCSetConfig, BIT_RATE should be biger than 0\n");
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_ALLOW_FRAME_SKIP:
+			mfc_dbg("MFC_ENC_SETCONF_ALLOW_FRAME_SKIP : %d\n", ctx->state);
+
+			if ((ctx->state < INST_STATE_CREATE) || (ctx->state > INST_STATE_EXE)) {
+				mfc_err("MFC_ENC_SETCONF_ALLOW_FRAME_SKIP : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0] > 0) {
+				mfc_dbg("Allow_frame_skip enable : %d\n", usercfg->basic.values[0]);
+				enc_ctx->frame_skip_enable = usercfg->basic.values[0];
+				if (enc_ctx->frame_skip_enable == 2)
+					enc_ctx->frameskip = usercfg->basic.values[1];
+				enc_ctx->FrameSkipCngTag = 1;
+				enc_ctx->setflag = 1;
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_VUI_INFO:
+			mfc_dbg("MFC_ENC_SETCONF_VUI_INFO : %d\n", ctx->state);
+
+			if ((ctx->state < INST_STATE_CREATE) || (ctx->state > INST_STATE_EXE)) {
+				mfc_err("MFC_ENC_SETCONF_VUI_INFO_SET : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0] > 0) {
+				mfc_dbg("VUI_info enable : %d\n", usercfg->basic.values[1]);
+				enc_ctx->vuiinfoval = usercfg->basic.values[0];
+				if (enc_ctx->vuiinfoval == 255)
+					enc_ctx->vuiextendsar = usercfg->basic.values[1];
+				enc_ctx->vui_info_enable = 1;
+				enc_ctx->VUIInfoCngTag = 1;
+				enc_ctx->setflag = 1;
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_I_PERIOD:
+			mfc_dbg("MFC_ENC_SETCONF_I_PERIOD : %d\n", ctx->state);
+
+			if ((ctx->state < INST_STATE_CREATE) || (ctx->state > INST_STATE_EXE)) {
+				mfc_err("MFC_ENC_SETCONF_I_PERIOD_CHANGE : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0]) {
+				mfc_dbg("I_PERIOD value : %d\n", usercfg->basic.values[0]);
+				enc_ctx->iperiodval = usercfg->basic.values[0];
+				enc_ctx->IPeriodCngTag = 1;
+				enc_ctx->setflag = 1;
+			}
+
+			break;
+
+		case MFC_ENC_SETCONF_HIER_P:
+			mfc_dbg("MFC_ENC_SETCONF_FRAME_TYPE : %d\n", ctx->state);
+
+			if ((ctx->state < INST_STATE_CREATE) || (ctx->state > INST_STATE_EXE)) {
+				mfc_err("MFC_ENC_SETCONF_HIER_P_SET : state is invalid\n");
+				return MFC_STATE_INVALID;
+			}
+
+			if (usercfg->basic.values[0]) {
+				mfc_dbg("HIER_P enable : %d\n", usercfg->basic.values[0]);
+				enc_ctx->hier_p_enable = usercfg->basic.values[0];
+				enc_ctx->HierPCngTag = 1;
+				enc_ctx->setflag = 1;
+			}
+
+			break;
+
+		default:
+			mfc_dbg("not common cfg, try to codec specific: 0x%08x\n", type);
+			ret = 1;
+
+			break;
+	}
+
+	return ret;
+}
+
+static int h264_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	struct mfc_enc_h264 *h264 = (struct mfc_enc_h264 *)enc_ctx->e_priv;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	int ret;
+
+	mfc_dbg("type: 0x%08x", type);
+	mfc_dbg("ctx->state: 0x%08x", ctx->state);
+
+	ret = set_codec_cfg(ctx, type, arg);
+	if (ret <= 0)
+		return ret;
+
+	ret = 0;
+
+	switch (type) {
+	case MFC_ENC_SETCONF_SEI_GEN:
+		mfc_dbg("ctx->state: 0x%08x", ctx->state);
+
+		if (ctx->state >= INST_STATE_INIT) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		if (usercfg->basic.values[0] > 0)
+			h264->sei_gen = 1;
+		else
+			h264->sei_gen = 0;
+
+		break;
+
+	case MFC_ENC_SETCONF_FRAME_PACKING:
+		if (ctx->state >= INST_STATE_EXE) {
+			mfc_dbg("invalid instance state: 0x%08x\n", type);
+			return MFC_STATE_INVALID;
+		}
+
+		if ((usercfg->basic.values[0] < 3) || (usercfg->basic.values[0] > 5)) {
+			mfc_err("invalid param: FRAME_PACKING: %d\n",
+				usercfg->basic.values[0]);
+			return MFC_ENC_GET_CONF_FAIL;
+		}
+
+		h264->fp.arrangement_type = usercfg->basic.values[0] & 0x7F;
+		h264->fp.current_frame_is_frame0_flag = usercfg->basic.values[1] & 0x1;
+
+		h264->change |= CHG_FRAME_PACKING;
+
+		break;
+	default:
+		mfc_dbg("invalid set cfg type: 0x%08x\n", type);
+		ret = -2;
+
+		break;
+	}
+
+	return ret;
+}
+
+static struct mfc_enc_info unknown_enc = {
+	.name		= "UNKNOWN",
+	.codectype	= UNKNOWN_TYPE,
+	.codecid	= -1,
+	.e_priv_size	= 0,
+	/*
+	 * The unknown codec operations will be not call,
+	 * unused default operations raise build warning.
+	 */
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= NULL,
+		.get_init_arg		= get_init_arg,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= set_codec_bufs,
+		.set_dpbs		= NULL,
+		.get_exe_arg		= NULL,
+		.pre_frame_start	= pre_frame_start,
+		.post_frame_start	= post_frame_start,
+		.multi_data_frame	= multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_enc_info h264_enc = {
+	.name		= "H264",
+	.codectype	= H264_ENC,
+	.codecid	= 16,
+	.e_priv_size	= sizeof(struct mfc_enc_h264),
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= NULL,
+		.get_init_arg		= h264_get_init_arg,
+		.pre_seq_start		= h264_pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= h264_set_codec_bufs,
+		.set_dpbs		= NULL,
+		.get_exe_arg		= NULL,
+		.pre_frame_start	= h264_pre_frame_start,
+		.post_frame_start	= post_frame_start,
+		.multi_data_frame	= multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= h264_set_codec_cfg,
+	},
+};
+
+static struct mfc_enc_info mpeg4_enc = {
+	.name		= "MPEG4",
+	.codectype	= MPEG4_ENC,
+	.codecid	= 17,
+	.e_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= NULL,
+		.get_init_arg		= mpeg4_get_init_arg,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= h264_set_codec_bufs,
+		.set_dpbs		= NULL,
+		.get_exe_arg		= NULL,
+		.pre_frame_start	= pre_frame_start,
+		.post_frame_start	= post_frame_start,
+		.multi_data_frame	= multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+static struct mfc_enc_info h263_enc = {
+	.name		= "H263",
+	.codectype	= H263_ENC,
+	.codecid	= 18,
+	.e_priv_size	= 0,
+	.c_ops		= {
+		.alloc_ctx_buf		= alloc_ctx_buf,
+		.alloc_desc_buf		= NULL,
+		.get_init_arg		= h263_get_init_arg,
+		.pre_seq_start		= pre_seq_start,
+		.post_seq_start		= post_seq_start,
+		.set_init_arg		= set_init_arg,
+		.set_codec_bufs		= h264_set_codec_bufs,
+		.set_dpbs		= NULL,
+		.get_exe_arg		= NULL,
+		.pre_frame_start	= pre_frame_start,
+		.post_frame_start	= post_frame_start,
+		.multi_data_frame	= multi_data_frame,
+		.set_exe_arg		= set_exe_arg,
+		.get_codec_cfg		= get_codec_cfg,
+		.set_codec_cfg		= set_codec_cfg,
+	},
+};
+
+void mfc_init_encoders(void)
+{
+	list_add_tail(&unknown_enc.list, &mfc_encoders);
+
+	list_add_tail(&h264_enc.list, &mfc_encoders);
+	list_add_tail(&mpeg4_enc.list, &mfc_encoders);
+	list_add_tail(&h263_enc.list, &mfc_encoders);
+}
+
+static int mfc_set_encoder(struct mfc_inst_ctx *ctx, SSBSIP_MFC_CODEC_TYPE codectype)
+{
+	struct list_head *pos;
+	struct mfc_enc_info *encoder;
+	struct mfc_enc_ctx *enc_ctx;
+
+	ctx->codecid = -1;
+
+	/* find and set codec private */
+	list_for_each(pos, &mfc_encoders) {
+		encoder = list_entry(pos, struct mfc_enc_info, list);
+
+		if (encoder->codectype == codectype) {
+			if (encoder->codecid < 0)
+				break;
+
+			/* Allocate Encoder Context memory */
+			enc_ctx = kzalloc(sizeof(struct mfc_enc_ctx), GFP_KERNEL);
+			if (!enc_ctx) {
+				mfc_err("failed to allocate codec private\n");
+				return -ENOMEM;
+			}
+			ctx->c_priv = enc_ctx;
+
+			/* Allocate Encoder context private memory */
+			enc_ctx->e_priv = kzalloc(encoder->e_priv_size, GFP_KERNEL);
+			if (!enc_ctx->e_priv) {
+				mfc_err("failed to allocate encoder private\n");
+				kfree(enc_ctx);
+				ctx->c_priv = NULL;
+				return -ENOMEM;
+			}
+
+			ctx->codecid = encoder->codecid;
+			ctx->type = ENCODER;
+			ctx->c_ops = (struct codec_operations *)&encoder->c_ops;
+
+			break;
+		}
+	}
+
+	if (ctx->codecid < 0)
+		mfc_err("couldn't find proper encoder codec type: %d\n", codectype);
+
+	return ctx->codecid;
+}
+
+int set_strm_ref_buf(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_alloc_buffer *alloc;
+	int i;
+	/*
+	unsigned int reg;
+	*/
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	/* width: 128B align, height: 32B align, size: 8KB align */
+	enc_ctx->lumasize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height, ALIGN_H);
+	enc_ctx->lumasize = ALIGN(enc_ctx->lumasize, ALIGN_8KB);
+	enc_ctx->chromasize = ALIGN(ctx->width + 16, ALIGN_W) * ALIGN((ctx->height >> 1) + 4, ALIGN_H);
+	enc_ctx->chromasize = ALIGN(enc_ctx->chromasize, ALIGN_8KB);
+
+	/*
+	 * allocate stream buffer
+	 */
+	alloc = _mfc_alloc_buf(ctx, MFC_STRM_SIZE, ALIGN_2KB, MBT_CPB | PORT_A);
+	if (alloc == NULL) {
+		mfc_err("failed alloc stream buffer\n");
+
+		return -1;
+	}
+
+	enc_ctx->streamaddr = alloc->real;
+	enc_ctx->streamsize = MFC_STRM_SIZE;
+
+	/* FIXME: temp. */
+	enc_ctx->kstrmaddr = alloc->addr;
+
+	for (i = 0; i < 2; i++) {
+		/*
+		 * allocate Y0, Y1 ref buffer
+		 */
+		alloc = _mfc_alloc_buf(ctx, enc_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_A);
+		if (alloc == NULL) {
+			mfc_err("failed alloc luma ref buffer\n");
+
+			return -1;
+		}
+		/*
+		 * set luma ref buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_ENC_REF0_LUMA_ADR + (4 * i));
+	}
+
+	if (enc_ctx->numdpb == 4) {
+		for (i = 0; i < 2; i++) {
+			/*
+			 * allocate Y2, Y3 ref buffer
+			 */
+			alloc = _mfc_alloc_buf(ctx, enc_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_B);
+			if (alloc == NULL) {
+				mfc_err("failed alloc luma ref buffer\n");
+
+				return -1;
+			}
+			/*
+			 * set luma ref buffer address
+			 */
+			write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_ENC_REF2_LUMA_ADR + (4 * i));
+		}
+	}
+
+	/*
+	 * allocate C0 ~ C3 ref buffer
+	 */
+	for (i = 0; i < enc_ctx->numdpb; i++) {
+		alloc = _mfc_alloc_buf(ctx, enc_ctx->chromasize, ALIGN_2KB, MBT_DPB | PORT_B);
+		if (alloc == NULL) {
+			mfc_err("failed alloc chroma ref buffer\n");
+
+			return -1;
+		}
+		/*
+		 * set chroma ref buffer address
+		 */
+		write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_ENC_REF0_CHROMA_ADR + (4 * i));
+	}
+
+	return 0;
+}
+
+int mfc_init_encoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
+{
+	struct mfc_enc_init_arg *init_arg = (struct mfc_enc_init_arg *)args;
+	struct mfc_enc_ctx *enc_ctx = NULL;
+	struct mfc_pre_cfg *precfg;
+	struct list_head *pos, *nxt;
+	int ret;
+	unsigned char *in_vir;
+
+	ret = mfc_set_encoder(ctx, init_arg->cmn.in_codec_type);
+	if (ret < 0) {
+		mfc_err("failed to setup encoder codec\n");
+		ret = MFC_ENC_INIT_FAIL;
+		goto err_handling;
+	}
+
+	ctx->width = init_arg->cmn.in_width;
+	ctx->height = init_arg->cmn.in_height;
+
+	if (ctx->height > MAX_VER_SIZE) {
+		if (ctx->height > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_handling;
+		}
+
+		if (ctx->width > MAX_VER_SIZE) {
+			mfc_err("Not support resolutioni: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_handling;
+		}
+	} else {
+		if (ctx->width > MAX_HOR_SIZE) {
+			mfc_err("Not support resolution: %dx%d\n",
+				ctx->width, ctx->height);
+			goto err_handling;
+		}
+	}
+
+	enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	enc_ctx->pixelcache = init_arg->cmn.in_pixelcache;
+
+	/*
+	 * assign pre configuration values to instance context
+	 */
+	list_for_each_safe(pos, nxt, &ctx->presetcfgs) {
+		precfg = list_entry(pos, struct mfc_pre_cfg, list);
+
+		if (ctx->c_ops->set_codec_cfg) {
+			ret = ctx->c_ops->set_codec_cfg(ctx, precfg->type, precfg->values);
+			if (ret < 0)
+				mfc_warn("cannot set preset config type: 0x%08x: %d",
+					precfg->type, ret);
+		}
+
+		list_del(&precfg->list);
+		kfree(precfg);
+	}
+	INIT_LIST_HEAD(&ctx->presetcfgs);
+
+	mfc_set_inst_state(ctx, INST_STATE_SETUP);
+
+	/*
+	 * allocate context buffer
+	 */
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if ((ctx->c_ops->alloc_ctx_buf) && (!ctx->drm_flag)) {
+#else
+	if (ctx->c_ops->alloc_ctx_buf) {
+#endif
+		if (ctx->c_ops->alloc_ctx_buf(ctx) < 0) {
+			mfc_err("Context buffer allocation Failed");
+			ret = MFC_ENC_INIT_FAIL;
+			goto err_handling;
+		}
+	}
+
+	/* [pixelcache] */
+	ret = mfc_cmd_inst_open(ctx);
+	if (ret < 0) {
+		mfc_err("Open Instance Failed");
+		goto err_handling;
+	}
+
+	mfc_set_inst_state(ctx, INST_STATE_OPEN);
+
+	if (init_shm(ctx) < 0) {
+		mfc_err("Shared Memory Initialization Failed");
+		ret = MFC_ENC_INIT_FAIL;
+		goto err_handling;
+	}
+
+#if SUPPORT_SLICE_ENCODING
+	if (init_arg->cmn.in_output_mode == 1)
+		ctx->slice_flag = 1;
+#endif
+	/*
+	 * get init. argumnets
+	 */
+	if (ctx->c_ops->get_init_arg) {
+		if (ctx->c_ops->get_init_arg(ctx, (void *)init_arg) < 0) {
+			mfc_err("Get Initial Arguments Failed");
+			ret = MFC_ENC_INIT_FAIL;
+			goto err_handling;
+		}
+	}
+
+	/*
+	 * allocate & set codec buffers
+	 */
+	if (ctx->c_ops->set_codec_bufs) {
+		if (ctx->c_ops->set_codec_bufs(ctx) < 0) {
+			mfc_err("Set Codec Buffers Failed");
+			ret = MFC_ENC_INIT_FAIL;
+			goto err_handling;
+		}
+	}
+
+	set_strm_ref_buf(ctx);
+
+	/*
+	 * execute pre sequence start operation
+	 */
+	if (ctx->c_ops->pre_seq_start) {
+		if (ctx->c_ops->pre_seq_start) {
+			if (ctx->c_ops->pre_seq_start(ctx) < 0) {
+				mfc_err("Pre-Sequence Start Failed");
+				ret = MFC_ENC_INIT_FAIL;
+				goto err_handling;
+			}
+		}
+	}
+
+	if (enc_ctx->setflag == 1) {
+		if (enc_ctx->FrameSkipCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - Allow_frame_skip enable : %d - number : %d \n",
+					enc_ctx->frame_skip_enable, enc_ctx->frameskip);
+
+			if (enc_ctx->frame_skip_enable == 2)
+				write_shm(ctx,
+					((enc_ctx->frame_skip_enable << 1) | (enc_ctx->frameskip << 16) | read_shm(ctx, EXT_ENC_CONTROL)),
+					EXT_ENC_CONTROL);
+			else
+				write_shm(ctx, ((enc_ctx->frame_skip_enable << 1)|read_shm(ctx, EXT_ENC_CONTROL)), EXT_ENC_CONTROL);
+		}
+
+		if (enc_ctx->VUIInfoCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - VUI_info enable : %d\n", enc_ctx->vui_info_enable);
+
+			write_shm(ctx, enc_ctx->vuiinfoval, ASPECT_RATIO_IDC);
+			write_shm(ctx, enc_ctx->vuiextendsar, EXTENDED_SAR);
+			write_shm(ctx, ((enc_ctx->vui_info_enable << 15)|read_shm(ctx, EXT_ENC_CONTROL)), EXT_ENC_CONTROL);	/*ASPECT_RATIO_VUI_ENABLE = 1<<15*/
+		}
+
+		if (enc_ctx->IPeriodCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - I_PERIOD : %d\n", enc_ctx->iperiodval);
+			write_shm(ctx, enc_ctx->iperiodval, NEW_I_PERIOD);
+			write_shm(ctx, ((1<<16)|enc_ctx->iperiodval), H264_I_PERIOD);
+			write_reg(enc_ctx->iperiodval, MFC_ENC_PIC_TYPE_CTRL);
+			write_shm(ctx, (0x1 << 0), ENC_PARAM_CHANGE);
+		}
+
+		if (enc_ctx->HierPCngTag == 1) {
+			mfc_dbg("Encoding Param Setting - HIER_P enable : %d\n", enc_ctx->hier_p_enable);
+
+			write_shm(ctx,
+				((enc_ctx->hier_p_enable << 4) |
+				read_shm(ctx, EXT_ENC_CONTROL)),
+				EXT_ENC_CONTROL);
+				/*HIERARCHICAL_P_ENABLE = 1<<4*/
+		}
+	}
+
+	ret = mfc_cmd_seq_start(ctx);
+	if (ret < 0) {
+		mfc_err("Sequence Start Failed");
+		goto err_handling;
+	}
+
+	if (ctx->c_ops->post_seq_start) {
+		if (ctx->c_ops->post_seq_start(ctx) < 0) {
+			mfc_err("Post Sequence Start Failed");
+			ret = MFC_ENC_INIT_FAIL;
+			goto err_handling;
+		}
+	}
+
+	if (ctx->c_ops->set_init_arg) {
+		if (ctx->c_ops->set_init_arg(ctx, (void *)init_arg) < 0) {
+			mfc_err("Setting Initialized Arguments Failed");
+			ret = MFC_ENC_INIT_FAIL;
+			goto err_handling;
+		}
+	}
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if ((ctx->buf_cache_type == CACHE) && (!ctx->drm_flag)) {
+#else
+	if (ctx->buf_cache_type == CACHE) {
+#endif
+		in_vir = phys_to_virt(enc_ctx->streamaddr);
+		mfc_mem_cache_inv(in_vir, init_arg->cmn.out_header_size);
+		mfc_dbg("cache invalidate\n");
+	}
+#if defined(CONFIG_BUSFREQ)
+	/* Fix MFC & Bus Frequency for High resolution for better performance */
+	if (ctx->width >= MAX_HOR_RES || ctx->height >= MAX_VER_RES) {
+		if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
+			/* For fixed MFC & Bus Freq to 200 & 400 MHz for 1080p Contents */
+			exynos4_busfreq_lock(DVFS_LOCK_ID_MFC, BUS_L0);
+			mfc_dbg("[%s] Bus Freq Locked L0\n", __func__);
+		}
+
+		atomic_inc(&ctx->dev->busfreq_lock_cnt);
+		ctx->busfreq_flag = true;
+	}
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	if ((ctx->width >= 320 && ctx->height >= 240)
+		|| (ctx->width >= 240 && ctx->height >= 320)) {
+		if (atomic_read(&ctx->dev->cpufreq_lock_cnt) == 0) {
+			if (0 == ctx->dev->cpufreq_level) /* 500MHz */
+				exynos_cpufreq_get_level(500000,
+						&ctx->dev->cpufreq_level);
+			exynos_cpufreq_lock(DVFS_LOCK_ID_MFC,
+					ctx->dev->cpufreq_level);
+			mfc_dbg("[%s] CPU Freq Locked 500MHz!\n", __func__);
+		}
+		atomic_inc(&ctx->dev->cpufreq_lock_cnt);
+		ctx->cpufreq_flag = true;
+	}
+#endif
+
+	/*
+	 * allocate & set DPBs
+	 */
+	/*
+	if (ctx->c_ops->set_dpbs) {
+		if (ctx->c_ops->set_dpbs(ctx) < 0)
+			return MFC_ENC_INIT_FAIL;
+	}
+	*/
+
+	/*
+	ret = mfc_cmd_init_buffers(ctx);
+	if (ret < 0)
+		return ret;
+	*/
+
+	mfc_set_inst_state(ctx, INST_STATE_INIT);
+
+	if (enc_ctx->setflag == 1) {
+		enc_ctx->setflag = 0;
+		enc_ctx->FrameSkipCngTag = 0;
+		enc_ctx->VUIInfoCngTag = 0;
+		enc_ctx->HierPCngTag = 0;
+
+		if (enc_ctx->IPeriodCngTag == 1) {
+			write_shm(ctx, 0, ENC_PARAM_CHANGE);
+			enc_ctx->IPeriodCngTag = 0;
+		}
+	}
+
+	mfc_print_buf();
+
+	return MFC_OK;
+
+err_handling:
+	if (ctx->state > INST_STATE_CREATE) {
+		mfc_cmd_inst_close(ctx);
+		ctx->state = INST_STATE_CREATE;
+	}
+
+	mfc_free_buf_inst(ctx->id);
+
+	if (enc_ctx) {
+		kfree(enc_ctx->e_priv);
+		enc_ctx->e_priv = NULL;
+	}
+
+	if (ctx->c_priv) {
+		kfree(ctx->c_priv);
+		ctx->c_priv = NULL;
+	}
+
+	return ret;
+}
+
+static int mfc_encoding_frame(struct mfc_inst_ctx *ctx, struct mfc_enc_exe_arg *exe_arg)
+{
+	int ret;
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+	void *ump_handle;
+#endif
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+
+	/* Set Frame Tag */
+	write_shm(ctx, exe_arg->in_frametag, SET_FRAME_TAG);
+
+	/* Set stream buffer addr */
+	enc_ctx->streamaddr = mfc_mem_base_ofs(exe_arg->in_strm_st);
+	enc_ctx->streamsize = exe_arg->in_strm_end - exe_arg->in_strm_st;
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	if (enc_ctx->inputformat == NV21_LINEAR)
+		write_reg(1, MFC_ENC_NV21_SEL);
+	else if (enc_ctx->inputformat == NV12_LINEAR)
+		write_reg(0, MFC_ENC_NV21_SEL);
+#endif
+#if SUPPORT_SLICE_ENCODING
+	write_reg((enc_ctx->outputmode) << 31, MFC_ENC_SI_CH1_INPUT_FLUSH);
+#endif
+
+	write_reg(enc_ctx->streamaddr >> 11, MFC_ENC_SI_CH1_SB_ADR);
+	write_reg(enc_ctx->streamsize, MFC_ENC_SI_CH1_SB_SIZE);
+
+	#if 0
+	/* force I frame or Not-coded frame */
+	if (mfc_ctx->forceSetFrameType == I_FRAME)
+		write_reg(1, MFC_ENC_SI_CH1_FRAME_INS);
+	else if (mfc_ctx->forceSetFrameType == NOT_CODED)
+		write_reg(1 << 1, MFC_ENC_SI_CH1_FRAME_INS);
+
+	if (mfc_ctx->dynamic_framerate != 0) {
+		write_shm((1 << 1), mfc_ctx->shared_mem_vir_addr + 0x2c);
+		/* MFC fw 2010/04/09 */
+		write_shm(mfc_ctx->dynamic_framerate*SCALE_NUM,
+				  mfc_ctx->shared_mem_vir_addr + 0x94);
+		if (mfc_ctx->MfcCodecType == MPEG4_ENC) {
+			time_increment_res = mfc_ctx->dynamic_framerate *
+						MPEG4_TIME_RES;
+			write_shm((1 << 31) |
+				  (time_increment_res << 16) |
+				  (MPEG4_TIME_RES),
+				  mfc_ctx->shared_mem_vir_addr + 0x30);
+		}
+	}
+
+	if (mfc_ctx->dynamic_bitrate != 0) {
+		write_shm((1 << 2), mfc_ctx->shared_mem_vir_addr + 0x2c);
+		write_shm(mfc_ctx->dynamic_bitrate,
+				  mfc_ctx->shared_mem_vir_addr + 0x90);
+	}
+	#endif
+
+	/* Set current frame buffer addr */
+#if (MFC_MAX_MEM_PORT_NUM == 2)
+	write_reg((exe_arg->in_Y_addr - mfc_mem_base(1)) >> 11, MFC_ENC_SI_CH1_CUR_Y_ADR);
+	write_reg((exe_arg->in_CbCr_addr - mfc_mem_base(1)) >> 11, MFC_ENC_SI_CH1_CUR_C_ADR);
+#else
+	write_reg((exe_arg->in_Y_addr - mfc_mem_base(0)) >> 11, MFC_ENC_SI_CH1_CUR_Y_ADR);
+	write_reg((exe_arg->in_CbCr_addr - mfc_mem_base(0)) >> 11, MFC_ENC_SI_CH1_CUR_C_ADR);
+#endif
+
+	#if 0
+	write_reg(1, MFC_ENC_STR_BF_U_EMPTY);
+	write_reg(1, MFC_ENC_STR_BF_L_EMPTY);
+
+	/* buf reset command if stream buffer is frame mode */
+	write_reg(0x1 << 1, MFC_ENC_SF_BUF_CTRL);
+	#endif
+
+	if (ctx->buf_cache_type == CACHE) {
+		flush_all_cpu_caches();
+		outer_flush_all();
+	}
+
+#if SUPPORT_SLICE_ENCODING
+	if (enc_ctx->outputmode == 0) { /* frame */
+#endif
+		ret = mfc_cmd_frame_start(ctx);
+		if (ret < 0)
+			return ret;
+
+		exe_arg->out_frame_type = read_reg(MFC_ENC_SI_SLICE_TYPE);
+		exe_arg->out_encoded_size = read_reg(MFC_ENC_SI_STRM_SIZE);
+
+		/* FIXME: port must be checked */
+		exe_arg->out_Y_addr = mfc_mem_addr_ofs(read_reg(MFC_ENCODED_Y_ADDR) << 11, 1);
+		exe_arg->out_CbCr_addr = mfc_mem_addr_ofs(read_reg(MFC_ENCODED_C_ADDR) << 11, 1);
+#if SUPPORT_SLICE_ENCODING
+	} else {			/* slice */
+		ret = mfc_cmd_slice_start(ctx);
+		if (ret < 0)
+			return ret;
+
+		if (enc_ctx->slicecount) {
+			exe_arg->out_frame_type = -1;
+			exe_arg->out_encoded_size = enc_ctx->slicesize;
+
+			exe_arg->out_Y_addr = 0;
+			exe_arg->out_CbCr_addr = 0;
+		} else {
+			exe_arg->out_frame_type = read_reg(MFC_ENC_SI_SLICE_TYPE);
+			exe_arg->out_encoded_size = enc_ctx->slicesize;
+
+			/* FIXME: port must be checked */
+			exe_arg->out_Y_addr = mfc_mem_addr_ofs(read_reg(MFC_ENCODED_Y_ADDR) << 11, 1);
+			exe_arg->out_CbCr_addr = mfc_mem_addr_ofs(read_reg(MFC_ENCODED_C_ADDR) << 11, 1);
+		}
+	}
+
+	mfc_dbg("frame type: %d, encoded size: %d, slice size: %d, stream size: %d\n",
+		exe_arg->out_frame_type, exe_arg->out_encoded_size,
+		enc_ctx->slicesize, read_reg(MFC_ENC_SI_STRM_SIZE));
+#endif
+
+	/* Get Frame Tag top and bottom */
+	exe_arg->out_frametag_top = read_shm(ctx, GET_FRAME_TAG_TOP);
+	exe_arg->out_frametag_bottom = read_shm(ctx, GET_FRAME_TAG_BOT);
+
+	/* MFC fw 9/30 */
+	/*
+	enc_arg->out_Y_addr =
+	    cur_frm_base + (read_reg(MFC_ENCODED_Y_ADDR) << 11);
+	enc_arg->out_CbCr_addr =
+	    cur_frm_base + (read_reg(MFC_ENCODED_C_ADDR) << 11);
+	*/
+
+	/* FIXME: cookie may be invalide */
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	exe_arg->out_y_secure_id = 0;
+	exe_arg->out_c_secure_id = 0;
+
+	ump_handle = mfc_get_buf_ump_handle(read_reg(MFC_ENCODED_Y_ADDR) << 11);
+	if (ump_handle != NULL)
+		exe_arg->out_y_secure_id = mfc_ump_get_id(ump_handle);
+
+	ump_handle = mfc_get_buf_ump_handle(read_reg(MFC_ENCODED_C_ADDR) << 11);
+	if (ump_handle != NULL)
+		exe_arg->out_c_secure_id = mfc_ump_get_id(ump_handle);
+
+	mfc_dbg("secure IDs Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_secure_id,
+		exe_arg->out_c_secure_id);
+#elif defined(CONFIG_S5P_VMEM)
+	exe_arg->out_y_cookie = s5p_getcookie((void *)(read_reg(MFC_ENCODED_Y_ADDR) << 11));
+	exe_arg->out_c_cookie = s5p_getcookie((void *)(read_reg(MFC_ENCODED_C_ADDR) << 11));
+
+	mfc_dbg("cookie Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_cookie,
+		exe_arg->out_c_cookie);
+#endif
+
+	#if 0
+	write_reg(0, MFC_ENC_SI_CH1_FRAME_INS);
+	mfc_ctx->forceSetFrameType = 0;
+
+	write_shm(0, mfc_ctx->shared_mem_vir_addr + 0x2c);
+	mfc_ctx->dynamic_framerate = 0;
+	mfc_ctx->dynamic_bitrate = 0;
+	#endif
+
+	mfc_dbg
+	    ("- frame type(%d) encoded frame size(%d) encoded Y_addr(0x%08x) / C_addr(0x%08x)\r\n",
+	     exe_arg->out_frame_type, exe_arg->out_encoded_size,
+	     exe_arg->out_Y_addr, exe_arg->out_CbCr_addr);
+
+	return MFC_OK;
+}
+
+int mfc_exec_encoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
+{
+	struct mfc_enc_exe_arg *exe_arg;
+	int ret;
+	/*
+	struct mfc_enc_ctx *enc_ctx = (struct mfc_enc_ctx *)ctx->c_priv;
+	*/
+
+	exe_arg = (struct mfc_enc_exe_arg *)args;
+
+	mfc_set_inst_state(ctx, INST_STATE_EXE);
+
+	if (ctx->c_ops->pre_frame_start) {
+		if (ctx->c_ops->pre_frame_start(ctx) < 0)
+			return MFC_ENC_INIT_FAIL;
+	}
+
+	ret = mfc_encoding_frame(ctx, exe_arg);
+
+	if (ctx->c_ops->post_frame_start) {
+		if (ctx->c_ops->post_frame_start(ctx) < 0)
+			return MFC_ENC_INIT_FAIL;
+	}
+
+	mfc_set_inst_state(ctx, INST_STATE_EXE_DONE);
+
+	return ret;
+}
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_enc.h b/drivers/media/video/samsung/mfc5x/mfc_enc.h
new file mode 100644
index 0000000..4bca251
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_enc.h
@@ -0,0 +1,115 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_enc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Encoder interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_ENC_H
+#define __MFC_ENC_H __FILE__
+
+#include <linux/list.h>
+
+#include "mfc.h"
+#include "mfc_interface.h"
+#include "mfc_inst.h"
+
+enum enc_pc {
+	EPC_ENABLE	= 0,
+	EPC_DISABLE	= 3,
+};
+
+struct mfc_enc_ctx {
+	unsigned int lumasize;		/* C */
+	unsigned int chromasize;	/* C */
+
+	unsigned long streamaddr;	/* K */
+	unsigned int streamsize;	/* K */
+
+	/* FIXME: temp. */
+	unsigned char *kstrmaddr;
+
+	/* init */
+	enum enc_pc pixelcache;
+	unsigned int numdpb;
+
+	/* init | exec */
+	unsigned int framemap;
+	unsigned int inputformat;
+#if SUPPORT_SLICE_ENCODING
+	unsigned int outputmode;
+#endif
+
+	/* exec */
+	unsigned int interlace;
+	unsigned int forceframe;
+	unsigned int frameskip;
+	unsigned int framerate;
+	unsigned int bitrate;
+	unsigned int iperiodval;
+	unsigned int vuiinfoval;
+	unsigned int vuiextendsar;
+
+	unsigned int frame_skip_enable;
+	unsigned int vui_info_enable;
+	unsigned int hier_p_enable;
+#if SUPPORT_SLICE_ENCODING
+	unsigned int slicecount;
+	unsigned int slicesize;
+#endif
+	/* change flag */
+	unsigned int setflag;
+	unsigned int FrameTypeCngTag;
+	unsigned int FrameRateCngTag;
+	unsigned int BitRateCngTag;
+	unsigned int FrameSkipCngTag;
+	unsigned int VUIInfoCngTag;
+	unsigned int IPeriodCngTag;
+	unsigned int HierPCngTag;
+
+	void *e_priv;
+};
+
+#define CHG_FRAME_PACKING	0x00000001
+#define CHG_I_PERIOD		0x00000002
+struct mfc_enc_h264 {
+	unsigned int change;
+	unsigned int vui_enable;
+	unsigned int hier_p_enable;
+
+	unsigned int i_period;
+
+	unsigned int sei_gen;		/* H */
+	struct mfc_frame_packing fp;	/* H */
+};
+
+int mfc_init_encoding(struct mfc_inst_ctx *ctx, union mfc_args *args);
+/*
+int mfc_init_encoding(struct mfc_inst_ctx *ctx, struct mfc_dec_init_arg *init_arg);
+*/
+int mfc_exec_encoding(struct mfc_inst_ctx *ctx, union mfc_args *args);
+/*
+int mfc_exec_encoding(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg);
+*/
+
+/*---------------------------------------------------------------------------*/
+
+struct mfc_enc_info {
+	struct list_head list;
+	const char *name;
+	SSBSIP_MFC_CODEC_TYPE codectype;
+	int codecid;
+	unsigned int e_priv_size;
+
+	const struct codec_operations c_ops;
+};
+
+void mfc_init_encoders(void);
+
+#endif /* __MFC_ENC_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_errno.h b/drivers/media/video/samsung/mfc5x/mfc_errno.h
new file mode 100644
index 0000000..55754d6
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_errno.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Global header for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MFC_ERRNO_H
+#define __MFC_ERRNO_H __FILE__
+
+enum mfc_ret_code {
+	MFC_OK = 1,
+	MFC_FAIL = -1000,
+	MFC_OPEN_FAIL = -1001,
+	MFC_CLOSE_FAIL = -1002,
+
+	MFC_DEC_INIT_FAIL = -2000,
+	MFC_DEC_EXE_TIME_OUT = -2001,
+	MFC_DEC_EXE_ERR = -2002,
+	MFC_DEC_GET_INBUF_FAIL = 2003,
+	MFC_DEC_SET_INBUF_FAIL = 2004,
+	MFC_DEC_GET_OUTBUF_FAIL = -2005,
+	MFC_DEC_GET_CONF_FAIL = -2006,
+	MFC_DEC_SET_CONF_FAIL = -2007,
+
+	MFC_ENC_INIT_FAIL = -3000,
+	MFC_ENC_EXE_TIME_OUT = -3001,
+	MFC_ENC_EXE_ERR = -3002,
+	MFC_ENC_GET_INBUF_FAIL = -3003,
+	MFC_ENC_SET_INBUF_FAIL = -3004,
+	MFC_ENC_GET_OUTBUF_FAIL = -3005,
+	MFC_ENC_SET_OUTBUF_FAIL = -3006,
+	MFC_ENC_GET_CONF_FAIL = -3007,
+	MFC_ENC_SET_CONF_FAIL = -3008,
+
+	MFC_STATE_INVALID = -4000,
+	MFC_DEC_HEADER_FAIL = -4001,
+	MFC_DEC_INIT_BUF_FAIL = -4002,
+	MFC_ENC_HEADER_FAIL = -5000,
+	MFC_ENC_PARAM_FAIL = -5001,
+	MFC_FRM_BUF_SIZE_FAIL = -6000,
+	MFC_FW_LOAD_FAIL = -6001,
+	MFC_FW_INIT_FAIL = -6002,
+	MFC_INST_NUM_EXCEEDED_FAIL = -6003,
+	MFC_MEM_ALLOC_FAIL = -6004,
+	MFC_MEM_INVALID_ADDR_FAIL = -6005,
+	MFC_MEM_MAPPING_FAIL = -6006,
+	MFC_GET_CONF_FAIL = -6007,
+	MFC_SET_CONF_FAIL = -6008,
+	MFC_INVALID_PARAM_FAIL = -6009,
+	MFC_API_FAIL = -9000,
+
+	MFC_CMD_FAIL = -1003,
+	MFC_SLEEP_FAIL = -1010,
+	MFC_WAKEUP_FAIL = -1020,
+
+	MFC_CLK_ON_FAIL = -1030,
+	MFC_CLK_OFF_FAIL = -1030,
+	MFC_PWR_ON_FAIL = -1040,
+	MFC_PWR_OFF_FAIL = -1041,
+} ;
+
+#endif /* __MFC_ERRNO_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_inst.c b/drivers/media/video/samsung/mfc5x/mfc_inst.c
new file mode 100644
index 0000000..518fbfc
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_inst.c
@@ -0,0 +1,258 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_inst.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Instance manager for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/mm.h>
+
+#include "mfc_inst.h"
+#include "mfc_log.h"
+#include "mfc_buf.h"
+#include "mfc_cmd.h"
+#include "mfc_pm.h"
+#include "mfc_dec.h"
+#include "mfc_enc.h"
+
+#ifdef SYSMMU_MFC_ON
+#include <linux/interrupt.h>
+#endif
+
+/*
+ * the sematic both of mfc_create_inst() and mfc_destory_inst()
+ * be symmetric, but MFC channel open operation will be execute
+ * while init. sequence. (decoding and encoding)
+ * create -	just allocate context memory and initialize state
+ *
+ * destory -	execute channel close operation
+ *		free allocated buffer for instance
+ *		free allocated context memory
+ */
+
+struct mfc_inst_ctx *mfc_create_inst(void)
+{
+	struct mfc_inst_ctx *ctx;
+
+	ctx = kzalloc(sizeof(struct mfc_inst_ctx), GFP_KERNEL);
+	if (!ctx) {
+		mfc_err("failed to create instance\n");
+		return NULL;
+	}
+
+	/* FIXME: set default values */
+	ctx->state = INST_STATE_CREATE;
+
+	ctx->codecid = -1;
+	ctx->resolution_status = RES_NO_CHANGE;
+#ifdef CONFIG_BUSFREQ
+	ctx->busfreq_flag = false;
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	ctx->cpufreq_flag = false;
+#endif
+#ifdef CONFIG_BUSFREQ_OPP
+	ctx->dmcthreshold_flag = false;
+#endif
+#ifdef SYSMMU_MFC_ON
+	/*
+	ctx->pgd = __pa(current->mm->pgd);
+	*/
+	ctx->pgd = __pa(swapper_pg_dir);
+#endif
+
+	INIT_LIST_HEAD(&ctx->presetcfgs);
+
+	return ctx;
+}
+
+void mfc_destroy_inst(struct mfc_inst_ctx *ctx)
+{
+	struct mfc_dec_ctx *dec_ctx;
+	struct mfc_enc_ctx *enc_ctx;
+	struct mfc_pre_cfg *precfg;
+
+	if (ctx) {
+		if (ctx->state < INST_STATE_SETUP) {
+			while (!list_empty(&ctx->presetcfgs)) {
+				precfg = list_entry((&ctx->presetcfgs)->next,
+						struct mfc_pre_cfg, list);
+
+				mfc_dbg("remove unused preset config [0x%08x]\n",
+					precfg->type);
+
+				list_del(&precfg->list);
+				kfree(precfg);
+			}
+		} else {
+			/* free (decoder/encoder & context) private memory */
+			if (ctx->type == DECODER) {
+				dec_ctx = ctx->c_priv;
+				if (dec_ctx->d_priv)
+					kfree(dec_ctx->d_priv);
+
+				kfree(dec_ctx);
+			} else if (ctx->type == ENCODER) {
+				enc_ctx = ctx->c_priv;
+				if (enc_ctx->e_priv)
+					kfree(enc_ctx->e_priv);
+
+				kfree(enc_ctx);
+			}
+		}
+
+		if (ctx->state >= INST_STATE_OPEN) {
+			mfc_clock_on(ctx->dev);
+			mfc_cmd_inst_close(ctx);
+			mfc_clock_off(ctx->dev);
+		}
+
+		mfc_free_buf_inst(ctx->id);
+
+		/* free instance context memory */
+		kfree(ctx);
+	}
+}
+
+int mfc_set_inst_state(struct mfc_inst_ctx *ctx, enum instance_state state)
+{
+	mfc_dbg("state: 0x%08x", state);
+
+	/* only allow EXE_DONE to EXE transition */
+	if (ctx->state == INST_STATE_EXE_DONE && state == INST_STATE_EXE)
+		ctx->state = state;
+
+	if (ctx->state > state) {
+		mfc_err("failed to change state of instance [0x%08x:0x%08x]\n",
+			ctx->state, state);
+		return -1;
+	}
+
+	ctx->state = state;
+
+	return 0;
+}
+
+int mfc_chk_inst_state(struct mfc_inst_ctx *ctx, enum instance_state state)
+{
+	if (ctx->state != state)
+		return -1;
+	else
+		return 0;
+}
+
+int mfc_set_inst_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	int ret = MFC_OK;
+	struct mfc_pre_cfg *precfg;
+	union _mfc_config_arg *usercfg = (union _mfc_config_arg *)arg;
+	struct list_head *pos, *nxt;
+
+	mfc_dbg("type: 0x%08x, ctx->type: 0x%08x", type, ctx->type);
+
+	/* pre-configuration supports only basic type */
+	if (ctx->state <= INST_STATE_CREATE) {
+		precfg = (struct mfc_pre_cfg *)
+			kzalloc(sizeof(struct mfc_pre_cfg), GFP_KERNEL);
+
+		if (unlikely(precfg == NULL)) {
+			mfc_err("no more kernel memory");
+
+			return MFC_SET_CONF_FAIL;
+		}
+
+		precfg->type = type;
+		memcpy(precfg->values, usercfg->basic.values, sizeof(precfg->values));
+
+		mfc_dbg("precfg new entry");
+		mfc_dbg("type: 0x%08x", precfg->type);
+		mfc_dbg("values: %d %d %d %d", precfg->values[0],
+			precfg->values[1], precfg->values[2], precfg->values[3]);
+
+		list_add_tail(&precfg->list, &ctx->presetcfgs);
+
+		mfc_dbg("precfg entries...");
+		precfg = NULL;
+
+		list_for_each_safe(pos, nxt, &ctx->presetcfgs) {
+			precfg = list_entry(pos, struct mfc_pre_cfg, list);
+
+			mfc_dbg("type: 0x%08x", precfg->type);
+			mfc_dbg("values: %d %d %d %d", precfg->values[0],
+				precfg->values[1], precfg->values[2], precfg->values[3]);
+		}
+
+		return MFC_OK;
+	}
+
+	switch (type) {
+		case MFC_DEC_SETCONF_POST_ENABLE:
+		case MFC_DEC_SETCONF_EXTRA_BUFFER_NUM:
+		case MFC_DEC_SETCONF_DISPLAY_DELAY:
+		case MFC_DEC_SETCONF_IS_LAST_FRAME:
+		case MFC_DEC_SETCONF_SLICE_ENABLE:
+		case MFC_DEC_SETCONF_CRC_ENABLE:
+		case MFC_DEC_SETCONF_FIMV1_WIDTH_HEIGHT:
+		case MFC_DEC_SETCONF_FRAME_TAG:
+		case MFC_DEC_SETCONF_IMMEDIATELY_DISPLAY:
+		case MFC_DEC_SETCONF_DPB_FLUSH:
+		case MFC_DEC_SETCONF_SEI_PARSE:
+		case MFC_DEC_SETCONF_PIXEL_CACHE:
+		case MFC_ENC_SETCONF_FRAME_TYPE:
+		case MFC_ENC_SETCONF_CHANGE_FRAME_RATE:
+		case MFC_ENC_SETCONF_CHANGE_BIT_RATE:
+		case MFC_ENC_SETCONF_FRAME_TAG:
+		case MFC_ENC_SETCONF_ALLOW_FRAME_SKIP:
+		case MFC_ENC_SETCONF_VUI_INFO:
+		case MFC_ENC_SETCONF_I_PERIOD:
+		case MFC_ENC_SETCONF_HIER_P:
+		case MFC_ENC_SETCONF_SEI_GEN:
+		case MFC_ENC_SETCONF_FRAME_PACKING:
+			if (ctx->c_ops->set_codec_cfg) {
+				if ((ctx->c_ops->set_codec_cfg(ctx, type, arg)) < 0)
+					return MFC_SET_CONF_FAIL;
+			}
+			break;
+
+		default:
+			mfc_err("invalid set config type: 0x%08x\n", type);
+			return MFC_FAIL;
+	}
+
+	return ret;
+}
+
+int mfc_get_inst_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
+{
+	int ret = MFC_OK;
+
+	mfc_dbg("type: 0x%08x, ctx->type: 0x%08x", type, ctx->type);
+
+	switch (type) {
+		case MFC_DEC_GETCONF_CRC_DATA:
+		case MFC_DEC_GETCONF_BUF_WIDTH_HEIGHT:
+		case MFC_DEC_GETCONF_CROP_INFO:
+		case MFC_DEC_GETCONF_FRAME_TAG:
+		case MFC_DEC_GETCONF_WIDTH_HEIGHT:
+		case MFC_DEC_GETCONF_FRAME_PACKING:
+		case MFC_ENC_GETCONF_FRAME_TAG:
+			if (ctx->c_ops->get_codec_cfg) {
+				if ((ctx->c_ops->get_codec_cfg(ctx, type, arg)) < 0)
+					return MFC_GET_CONF_FAIL;
+			}
+			break;
+
+		default:
+			mfc_err("invalid get config type: 0x%08x\n", type);
+			return MFC_FAIL;
+	}
+
+	return ret;
+}
diff --git a/drivers/media/video/samsung/mfc5x/mfc_inst.h b/drivers/media/video/samsung/mfc5x/mfc_inst.h
new file mode 100644
index 0000000..e297c55
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_inst.h
@@ -0,0 +1,182 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_inst.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Instance manager file for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_INST_H
+#define __MFC_INST_H __FILE__
+
+#include <linux/list.h>
+
+#include "mfc.h"
+#include "mfc_interface.h"
+
+
+/* FIXME: instance state should be more specific */
+enum instance_state {
+	INST_STATE_NULL		= 0,
+
+	/* open */
+	INST_STATE_CREATE	= 0x0001,
+
+	/* ioctl - *_INIT */
+	INST_STATE_SETUP	= 0x0004,
+
+	/* ioctl - *_INIT */
+	INST_STATE_OPEN		= 0x0010,
+	INST_STATE_INIT,
+
+	/* ioctl - *_EXE */
+	INST_STATE_EXE		= 0x0020,
+	INST_STATE_EXE_DONE,
+};
+
+struct mfc_inst_ctx;
+
+struct codec_operations {
+	/* initialization routines */
+	int (*alloc_ctx_buf) (struct mfc_inst_ctx *ctx);
+	int (*alloc_desc_buf) (struct mfc_inst_ctx *ctx);
+	int (*get_init_arg) (struct mfc_inst_ctx *ctx, void *arg);
+	int (*pre_seq_start) (struct mfc_inst_ctx *ctx);
+	int (*post_seq_start) (struct mfc_inst_ctx *ctx);
+	int (*set_init_arg) (struct mfc_inst_ctx *ctx, void *arg);
+	int (*set_codec_bufs) (struct mfc_inst_ctx *ctx);
+	int (*set_dpbs) (struct mfc_inst_ctx *ctx);		/* decoder */
+	/* execution routines */
+	int (*get_exe_arg) (struct mfc_inst_ctx *ctx, void *arg);
+	int (*pre_frame_start) (struct mfc_inst_ctx *ctx);
+	int (*post_frame_start) (struct mfc_inst_ctx *ctx);
+	int (*multi_data_frame) (struct mfc_inst_ctx *ctx);
+	int (*set_exe_arg) (struct mfc_inst_ctx *ctx, void *arg);
+	/* configuration routines */
+	int (*get_codec_cfg) (struct mfc_inst_ctx *ctx, int type, void *arg);
+	int (*set_codec_cfg) (struct mfc_inst_ctx *ctx, int type, void *arg);
+};
+
+struct mfc_pre_cfg {
+	struct list_head list;
+	unsigned int type;
+	unsigned int values[4];
+};
+
+struct mfc_dec_cfg {
+	unsigned int crc;
+	unsigned int pixelcache;
+	unsigned int slice;
+	unsigned int numextradpb;
+
+	unsigned int postfilter;	/* MPEG4 */
+	unsigned int dispdelay_en;	/* H.264 */
+	unsigned int dispdelay_val;	/* H.264 */
+	unsigned int width;		/* FIMV1 */
+	unsigned int height;		/* FIMV1 */
+};
+
+struct mfc_enc_cfg {
+	/*
+	type:
+	  init
+	  runtime
+	  init + runtime
+	*/
+
+	/* init */
+	unsigned int pixelcache;
+
+	unsigned int frameskip;
+	unsigned int frammode;
+	unsigned int hier_p;
+
+	/* runtime ? */
+	#if 0
+	unsigned int frametype;
+	unsigned int framerate;
+	unsigned int bitrate;
+	unsigned int vui;		/* H.264 */
+	unsigned int hec;		/* MPEG4 */
+	unsigned int seqhdrctrl;
+
+	unsigned int i_period;
+	#endif
+};
+
+enum mfc_resolution_status {
+	RES_INCREASED = 1,
+	RES_DECERASED = 2,
+};
+
+enum mfc_resolution_change_status {
+	RES_NO_CHANGE = 0,
+	RES_SET_CHANGE = 1,
+	RES_SET_REALLOC = 2,
+	RES_WAIT_FRAME_DONE = 3,
+};
+
+struct mfc_inst_ctx {
+	int id;				/* assigned by driver */
+	int cmd_id;			/* assigned by F/W */
+	int codecid;
+	unsigned int type;
+	enum instance_state state;
+	unsigned int width;
+	unsigned int height;
+	volatile unsigned char *shm;
+	unsigned int shmofs;
+	unsigned int ctxbufofs;
+	unsigned int ctxbufsize;
+	unsigned int descbufofs;	/* FIXME: move to decoder context */
+	unsigned int descbufsize;	/* FIXME: move to decoder context */
+	unsigned long userbase;
+	SSBIP_MFC_BUFFER_TYPE buf_cache_type;
+
+	int resolution_status;
+	/*
+	struct mfc_dec_cfg deccfg;
+	struct mfc_enc_cfg enccfg;
+	*/
+	struct list_head presetcfgs;
+
+	void *c_priv;
+	struct codec_operations *c_ops;
+	struct mfc_dev *dev;
+#ifdef SYSMMU_MFC_ON
+	unsigned long pgd;
+#endif
+#if defined(CONFIG_BUSFREQ)
+	int busfreq_flag;		/* context bus frequency flag */
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	int cpufreq_flag; /* context CPU frequency flag*/
+#endif
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	int drm_flag;
+#endif
+
+#ifdef CONFIG_BUSFREQ_OPP
+	int dmcthreshold_flag;  /* context dmc max threshold flag */
+#endif
+
+#if SUPPORT_SLICE_ENCODING
+	int slice_flag;
+#endif
+};
+
+struct mfc_inst_ctx *mfc_create_inst(void);
+void mfc_destroy_inst(struct mfc_inst_ctx *ctx);
+int mfc_set_inst_state(struct mfc_inst_ctx *ctx, enum instance_state state);
+int mfc_chk_inst_state(struct mfc_inst_ctx *ctx, enum instance_state state);
+int mfc_set_inst_cfg(struct mfc_inst_ctx *ctx, int type, void *arg);
+int mfc_get_inst_cfg(struct mfc_inst_ctx *ctx, int type, void *arg);
+
+#endif /* __MFC_INST_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_interface.h b/drivers/media/video/samsung/mfc5x/mfc_interface.h
new file mode 100644
index 0000000..61116e5
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_interface.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Global header for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MFC_INTERFACE_H
+#define __MFC_INTERFACE_H __FILE__
+
+#include "mfc_errno.h"
+#include "SsbSipMfcApi.h"
+
+#define IOCTL_MFC_DEC_INIT		(0x00800001)
+#define IOCTL_MFC_ENC_INIT		(0x00800002)
+#define IOCTL_MFC_DEC_EXE		(0x00800003)
+#define IOCTL_MFC_ENC_EXE		(0x00800004)
+
+#define IOCTL_MFC_GET_IN_BUF		(0x00800010)
+#define IOCTL_MFC_FREE_BUF		(0x00800011)
+#define IOCTL_MFC_GET_REAL_ADDR		(0x00800012)
+#define IOCTL_MFC_GET_MMAP_SIZE		(0x00800014)
+#define IOCTL_MFC_SET_IN_BUF		(0x00800018)
+
+#define IOCTL_MFC_SET_CONFIG		(0x00800101)
+#define IOCTL_MFC_GET_CONFIG		(0x00800102)
+
+#define IOCTL_MFC_SET_BUF_CACHE		(0x00800201)
+
+/* MFC H/W support maximum 32 extra DPB. */
+#define MFC_MAX_EXTRA_DPB               5
+#define MFC_MAX_DISP_DELAY              0xF
+
+#define MFC_LIB_VER_MAJOR               1
+#define MFC_LIB_VER_MINOR               00
+
+#define BUF_L_UNIT			(1024)
+#define Align(x, alignbyte)		(((x)+(alignbyte)-1)/(alignbyte)*(alignbyte))
+
+
+enum inst_type {
+    DECODER = 0x1,
+    ENCODER = 0x2,
+};
+
+typedef enum {
+    MFC_UNPACKED_PB = 0,
+    MFC_PACKED_PB = 1
+} mfc_packed_mode;
+
+
+typedef enum
+{
+	MFC_USE_NONE = 0x00,
+	MFC_USE_YUV_BUFF = 0x01,
+	MFC_USE_STRM_BUFF = 0x10
+} s3c_mfc_interbuff_status;
+
+#ifndef FPS
+typedef struct
+{
+	int luma0;	/* per frame (or top field)*/
+	int chroma0;	/* per frame (or top field)*/
+	int luma1;	/* per frame (or bottom field)*/
+	int chroma1;	/* per frame (or bottom field)*/
+} SSBSIP_MFC_CRC_DATA;
+#endif
+
+struct mfc_strm_ref_buf_arg {
+	unsigned int strm_ref_y;
+	unsigned int mv_ref_yc;
+};
+
+struct mfc_frame_buf_arg {
+	unsigned int luma;
+	unsigned int chroma;
+};
+
+
+struct mfc_enc_init_common_arg {
+	SSBSIP_MFC_CODEC_TYPE in_codec_type;	/* [IN] codec type */
+
+	int in_width;		/* [IN] width of YUV420 frame to be encoded */
+	int in_height;		/* [IN] height of YUV420 frame to be encoded */
+
+	int in_gop_num;		/* [IN] GOP Number (interval of I-frame) */
+	int in_vop_quant;	/* [IN] VOP quant */
+	int in_vop_quant_p;	/* [IN] VOP quant for P frame */
+
+	/* [IN] RC enable */
+	/* [IN] RC enable (0:disable, 1:frame level RC) */
+	int in_rc_fr_en;
+	int in_rc_bitrate;	/* [IN]  RC parameter (bitrate in kbps) */
+
+	int in_rc_qbound_min;	/* [IN]  RC parameter (Q bound Min) */
+	int in_rc_qbound_max;	/* [IN]  RC parameter (Q bound Max) */
+	int in_rc_rpara;	/* [IN]  RC parameter (Reaction Coefficient) */
+
+	/* [IN] Multi-slice mode (0:single, 1:multiple) */
+	int in_ms_mode;
+	/* [IN] Multi-slice size (in num. of mb or byte) */
+	int in_ms_arg;
+
+	int in_mb_refresh;	/* [IN]  Macroblock refresh */
+
+	/* [IN] Enable (1) / Disable (0) padding with the specified values */
+	int in_pad_ctrl_on;
+
+	/* [IN] pad value if pad_ctrl_on is Enable */
+	int in_y_pad_val;
+	int in_cb_pad_val;
+	int in_cr_pad_val;
+
+	/* linear or tiled */
+	int in_frame_map;
+
+	unsigned int in_pixelcache;
+	unsigned int in_mapped_addr;
+
+	struct mfc_strm_ref_buf_arg out_u_addr;
+	struct mfc_strm_ref_buf_arg out_p_addr;
+	struct mfc_strm_ref_buf_arg out_buf_size;
+	unsigned int out_header_size;
+
+#if SUPPORT_SLICE_ENCODING
+	unsigned int in_output_mode;
+#endif
+};
+
+struct mfc_enc_init_h263_arg {
+	int in_rc_framerate;	/* [IN]  RC parameter (framerate) */
+};
+
+struct mfc_enc_init_mpeg4_arg {
+	int in_profile;		/* [IN] profile */
+	int in_level;		/* [IN] level */
+
+	int in_vop_quant_b;	/* [IN] VOP quant for B frame */
+
+	/* [IN] B frame number */
+	int in_bframenum;
+
+	/* [IN] Quarter-pel MC enable (1:enabled, 0:disabled) */
+	int in_quart_pixel;
+
+	int in_TimeIncreamentRes;	/* [IN] VOP time resolution */
+	int in_VopTimeIncreament;	/* [IN] Frame delta */
+};
+
+struct mfc_enc_init_h264_arg {
+	int in_profile;		/* [IN] profile */
+	int in_level;		/* [IN] level */
+
+	int in_vop_quant_b;	/* [IN] VOP quant for B frame */
+
+	/* [IN] B frame number */
+	int in_bframenum;
+
+	/* [IN] interlace mode(0:progressive, 1:interlace) */
+	int in_interlace_mode;
+
+	/* [IN]  reference number */
+	int in_reference_num;
+	/* [IN]  reference number of P frame */
+	int in_ref_num_p;
+
+	int in_rc_framerate;	/* [IN]  RC parameter (framerate) */
+	int in_rc_mb_en;	/* [IN] RC enable (0:disable, 1:MB level RC) */
+	/* [IN] MB level rate control dark region adaptive feature */
+	int in_rc_mb_dark_dis;	/* (0:enable, 1:disable) */
+	/* [IN] MB level rate control smooth region adaptive feature */
+	int in_rc_mb_smooth_dis;	/* (0:enable, 1:disable) */
+	/* [IN] MB level rate control static region adaptive feature */
+	int in_rc_mb_static_dis;	/* (0:enable, 1:disable) */
+	/* [IN] MB level rate control activity region adaptive feature */
+	int in_rc_mb_activity_dis;	/* (0:enable, 1:disable) */
+
+	/* [IN]  disable deblocking filter idc */
+	int in_deblock_dis;	/* (0: enable,1: disable, 2:Disable at slice boundary) */
+	/* [IN]  slice alpha c0 offset of deblocking filter */
+	int in_deblock_alpha_c0;
+	/* [IN]  slice beta offset of deblocking filter */
+	int in_deblock_beta;
+
+	/* [IN]  ( 0 : CAVLC, 1 : CABAC ) */
+	int in_symbolmode;
+	/* [IN] (0: only 4x4 transform, 1: allow using 8x8 transform) */
+	int in_transform8x8_mode;
+
+	/* [IN] Inter weighted parameter for mode decision */
+	int in_md_interweight_pps;
+	/* [IN] Intra weighted parameter for mode decision */
+	int in_md_intraweight_pps;
+};
+
+struct mfc_enc_init_arg {
+	struct mfc_enc_init_common_arg cmn;
+	union {
+		struct mfc_enc_init_h264_arg h264;
+		struct mfc_enc_init_mpeg4_arg mpeg4;
+		struct mfc_enc_init_h263_arg h263;
+	} codec;
+};
+
+struct mfc_enc_exe_arg {
+	SSBSIP_MFC_CODEC_TYPE in_codec_type;	/* [IN] codec type */
+	unsigned int in_Y_addr;   /*[IN]In-buffer addr of Y component */
+	unsigned int in_CbCr_addr;/*[IN]In-buffer addr of CbCr component */
+	unsigned int in_Y_addr_vir;   /*[IN]In-buffer addr of Y component */
+	unsigned int in_CbCr_addr_vir;/*[IN]In-buffer addr of CbCr component */
+	unsigned int in_strm_st;  /*[IN]Out-buffer start addr of encoded strm*/
+	unsigned int in_strm_end; /*[IN]Out-buffer end addr of encoded strm */
+	unsigned int in_frametag;	/* [IN]  unique frame ID */
+
+	unsigned int out_frame_type; /* [OUT] frame type  */
+	int out_encoded_size;        /* [OUT] Length of Encoded video stream */
+	unsigned int out_Y_addr;    /*[OUT]Out-buffer addr of encoded Y component */
+	unsigned int out_CbCr_addr; /*[OUT]Out-buffer addr of encoded CbCr component */
+	unsigned int out_frametag_top;	/* [OUT] unique frame ID of an output frame or top field */
+	unsigned int out_frametag_bottom;/* [OUT] unique frame ID of bottom field */
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	unsigned int out_y_secure_id;
+	unsigned int out_c_secure_id;
+#elif defined(CONFIG_S5P_VMEM)
+	unsigned int out_y_cookie;
+	unsigned int out_c_cookie;
+#endif
+};
+
+struct mfc_dec_init_arg {
+	SSBSIP_MFC_CODEC_TYPE in_codec_type;	/* [IN] codec type */
+	int in_strm_buf;		/* [IN] address of stream buffer */
+	int in_strm_size;		/* [IN] filled size in stream buffer */
+	int in_packed_PB;		/* [IN]  Is packed PB frame or not, 1: packedPB  0: unpacked    */
+
+	unsigned int in_crc;		/* [IN] */
+	unsigned int in_pixelcache;	/* [IN] */
+	unsigned int in_slice;		/* [IN] */
+	unsigned int in_numextradpb;	/* [IN] */
+
+	unsigned int in_mapped_addr;
+
+	int out_frm_width;		/* [OUT] width  of YUV420 frame */
+	int out_frm_height;		/* [OUT] height of YUV420 frame */
+	int out_buf_width;	/* [OUT] width  of YUV420 frame */
+	int out_buf_height;	/* [OUT] height of YUV420 frame */
+
+	int out_dpb_cnt;	/* [OUT] the number of buffers which is nessary during decoding. */
+
+	int out_crop_right_offset;	/* [OUT] crop information for h264 */
+	int out_crop_left_offset;
+	int out_crop_bottom_offset;
+	int out_crop_top_offset;
+};
+
+struct mfc_dec_exe_arg {
+	SSBSIP_MFC_CODEC_TYPE in_codec_type;	/* [IN]  codec type */
+	int in_strm_buf;  /* [IN]  the physical address of STRM_BUF */
+	/* [IN]  Size of video stream filled in STRM_BUF */
+	int in_strm_size;
+	/* [IN] the address of dpb FRAME_BUF */
+	struct mfc_frame_buf_arg in_frm_buf;
+	/* [IN] size of dpb FRAME_BUF */
+	struct mfc_frame_buf_arg in_frm_size;
+	/* [IN] Unique frame ID eg. application specific timestamp */
+	unsigned int in_frametag;
+	/* [IN] immdiate Display for seek,thumbnail and one frame */
+	int in_immediately_disp;
+	/* [OUT]  the physical address of display buf */
+	int out_display_Y_addr;
+	/* [OUT]  the physical address of display buf */
+	int out_display_C_addr;
+	int out_display_status;
+	/* [OUT] unique frame ID of an output frame or top field */
+	unsigned int out_frametag_top;
+	/* [OUT] unique frame ID of bottom field */
+	unsigned int out_frametag_bottom;
+	int out_pic_time_top;
+	int out_pic_time_bottom;
+	int out_consumed_byte;
+
+	int out_crop_right_offset;
+	int out_crop_left_offset;
+	int out_crop_bottom_offset;
+	int out_crop_top_offset;
+
+	/* in new driver, each buffer offset must be return to the user */
+	int out_y_offset;
+	int out_c_offset;
+
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	unsigned int out_y_secure_id;
+	unsigned int out_c_secure_id;
+#elif defined(CONFIG_S5P_VMEM)
+	unsigned int out_y_cookie;
+	unsigned int out_c_cookie;
+#endif
+	int out_img_width;	/* [OUT] width	of YUV420 frame */
+	int out_img_height;	/* [OUT] height of YUV420 frame */
+	int out_buf_width;	/* [OUT] width	of YUV420 frame */
+	int out_buf_height;	/* [OUT] height of YUV420 frame */
+
+	int out_disp_pic_frame_type;		 /* [OUT] display picture frame type information */
+};
+
+struct mfc_basic_config {
+	int values[4];
+};
+
+struct mfc_frame_packing {
+	int		available;
+	unsigned int	arrangement_id;
+	int		arrangement_cancel_flag;
+	unsigned char	arrangement_type;
+	int		quincunx_sampling_flag;
+	unsigned char	content_interpretation_type;
+	int		spatial_flipping_flag;
+	int		frame0_flipped_flag;
+	int		field_views_flag;
+	int		current_frame_is_frame0_flag;
+	unsigned char	frame0_grid_pos_x;
+	unsigned char	frame0_grid_pos_y;
+	unsigned char	frame1_grid_pos_x;
+	unsigned char	frame1_grid_pos_y;
+};
+
+union _mfc_config_arg {
+	struct mfc_basic_config basic;
+	struct mfc_frame_packing frame_packing;
+};
+
+struct mfc_config_arg {
+	int type;
+	union _mfc_config_arg args;
+};
+
+struct mfc_get_real_addr_arg {
+	unsigned int key;
+	unsigned int addr;
+};
+
+struct mfc_buf_alloc_arg {
+	enum inst_type type;
+	int size;
+	/*
+	unsigned int mapped;
+	*/
+	unsigned int align;
+
+	unsigned int addr;
+	/*
+	unsigned int phys;
+	*/
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	/* FIMXE: invalid secure id == -1 */
+	unsigned int secure_id;
+#elif defined(CONFIG_S5P_VMEM)
+	unsigned int cookie;
+#else
+	unsigned int offset;
+#endif
+};
+
+struct mfc_buf_free_arg {
+	unsigned int addr;
+};
+
+
+/* RMVME */
+struct mfc_mem_alloc_arg {
+	enum inst_type type;
+	int buff_size;
+	SSBIP_MFC_BUFFER_TYPE buf_cache_type;
+	unsigned int mapped_addr;
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	unsigned int secure_id;
+#elif defined(CONFIG_S5P_VMEM)
+	unsigned int cookie;
+#else
+	unsigned int offset;
+#endif
+};
+
+struct mfc_mem_free_arg {
+	unsigned int key;
+};
+/* RMVME */
+
+union mfc_args {
+	/*
+	struct mfc_enc_init_arg enc_init;
+
+	struct mfc_enc_init_mpeg4_arg enc_init_mpeg4;
+	struct mfc_enc_init_mpeg4_arg enc_init_h263;
+	struct mfc_enc_init_h264_arg enc_init_h264;
+	*/
+	struct mfc_enc_init_arg enc_init;
+	struct mfc_enc_exe_arg enc_exe;
+
+	struct mfc_dec_init_arg dec_init;
+	struct mfc_dec_exe_arg dec_exe;
+
+	struct mfc_config_arg config;
+
+	struct mfc_buf_alloc_arg buf_alloc;
+	struct mfc_buf_free_arg buf_free;
+	struct mfc_get_real_addr_arg real_addr;
+
+	/* RMVME */
+	struct mfc_mem_alloc_arg mem_alloc;
+	struct mfc_mem_free_arg mem_free;
+	/* RMVME */
+};
+
+struct mfc_common_args {
+	enum mfc_ret_code ret_code;	/* [OUT] error code */
+	union mfc_args args;
+};
+
+struct mfc_enc_vui_info {
+	int aspect_ratio_idc;
+};
+
+struct mfc_dec_fimv1_info {
+	int width;
+	int height;
+};
+
+struct mfc_enc_hier_p_qp {
+	int t0_frame_qp;
+	int t2_frame_qp;
+	int t3_frame_qp;
+};
+
+struct mfc_enc_set_config {
+	int enable;
+	int number;
+};
+
+typedef struct
+{
+	int magic;
+	int hMFC;
+	int hVMEM;
+	int width;
+	int height;
+	int sizeStrmBuf;
+	struct mfc_frame_buf_arg sizeFrmBuf;
+	int displayStatus;
+	int inter_buff_status;
+	unsigned int virFreeStrmAddr;
+	unsigned int phyStrmBuf;
+	unsigned int virStrmBuf;
+	unsigned int virMvRefYC;
+	struct mfc_frame_buf_arg phyFrmBuf;
+	struct mfc_frame_buf_arg virFrmBuf;
+	unsigned int mapped_addr;
+	unsigned int mapped_size;
+	struct mfc_common_args MfcArg;
+	SSBSIP_MFC_CODEC_TYPE codecType;
+	SSBSIP_MFC_DEC_OUTPUT_INFO decOutInfo;
+	unsigned int inframetag;
+	unsigned int outframetagtop;
+	unsigned int outframetagbottom;
+	unsigned int immediatelydisp;
+	unsigned int encodedHeaderSize;
+	int encodedDataSize;
+	unsigned int encodedframeType;
+	struct mfc_frame_buf_arg encodedphyFrmBuf;
+
+	unsigned int dec_crc;
+	unsigned int dec_pixelcache;
+	unsigned int dec_slice;
+	unsigned int dec_numextradpb;
+	unsigned int dec_packedPB_detect;
+
+	int input_cookie;
+	int input_secure_id;
+	int input_size;
+
+	unsigned int encode_cnt;
+	int enc_frame_map;
+} _MFCLIB;
+
+#define ENC_PROFILE_LEVEL(profile, level)      ((profile) | ((level) << 8))
+#define ENC_RC_QBOUND(min_qp, max_qp)          ((min_qp) | ((max_qp) << 8))
+
+#endif /* __MFC_INTERFACE_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_log.h b/drivers/media/video/samsung/mfc5x/mfc_log.h
new file mode 100644
index 0000000..872cdeb
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_log.h
@@ -0,0 +1,59 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_log.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Logging interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_LOG_H
+#define __MFC_LOG_H __FILE__
+
+/* debug macros */
+#define MFC_DEBUG(fmt, ...)					\
+	do {							\
+		printk(KERN_DEBUG				\
+			"%s-> " fmt, __func__, ##__VA_ARGS__);	\
+	} while(0)
+
+#define MFC_ERROR(fmt, ...)					\
+	do {							\
+		printk(KERN_INFO				\
+			"%s-> " fmt, __func__, ##__VA_ARGS__);	\
+	} while (0)
+
+#define MFC_NOTICE(fmt, ...)					\
+	do {							\
+		printk(KERN_NOTICE				\
+			fmt, ##__VA_ARGS__);			\
+	} while (0)
+
+#define MFC_INFO(fmt, ...)					\
+	do {							\
+		printk(KERN_INFO				\
+			fmt, ##__VA_ARGS__);			\
+	} while (0)
+
+#define MFC_WARN(fmt, ...)					\
+	do {							\
+		printk(KERN_WARNING				\
+			fmt, ##__VA_ARGS__);			\
+	} while (0)
+
+#ifdef CONFIG_VIDEO_MFC5X_DEBUG
+#define mfc_dbg(fmt, ...)		MFC_DEBUG(fmt, ##__VA_ARGS__)
+#else
+#define mfc_dbg(fmt, ...)
+#endif
+
+#define mfc_err(fmt, ...)		MFC_ERROR(fmt, ##__VA_ARGS__)
+#define mfc_notice(fmt, ...)		MFC_NOTICE(fmt, ##__VA_ARGS__)
+#define mfc_info(fmt, ...)		MFC_INFO(fmt, ##__VA_ARGS__)
+#define mfc_warn(fmt, ...)		MFC_WARN(fmt, ##__VA_ARGS__)
+
+#endif /* __MFC_LOG_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_mem.c b/drivers/media/video/samsung/mfc5x/mfc_mem.c
new file mode 100644
index 0000000..bdf7148
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_mem.c
@@ -0,0 +1,944 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_mem.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Memory manager for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/string.h>
+#include <linux/vmalloc.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_ARCH_EXYNOS4
+#include <mach/media.h>
+#endif
+#include <plat/media.h>
+
+#ifndef CONFIG_S5P_VMEM
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#endif
+
+#ifdef CONFIG_S5P_MEM_CMA
+#include <linux/cma.h>
+#endif
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+#include <plat/s5p-vcm.h>
+
+#include "ump_kernel_interface.h"
+#include "ump_kernel_interface_ref_drv.h"
+#include "ump_kernel_interface_vcm.h"
+#endif
+
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+#include "mfc_log.h"
+#include "mfc_pm.h"
+
+static int mem_ports = -1;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+static struct mfc_mem mem_infos[MFC_MAX_MEM_CHUNK_NUM];
+#else
+static struct mfc_mem mem_infos[MFC_MAX_MEM_PORT_NUM];
+#endif
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+static struct mfc_vcm vcm_info;
+#endif
+
+static int mfc_mem_addr_port(unsigned long addr)
+{
+	int i;
+	int port = -1;
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	for (i = 0; i < MFC_MAX_MEM_CHUNK_NUM; i++) {
+#else
+	for (i = 0; i < mem_ports; i++) {
+#endif
+		if ((addr >= mem_infos[i].base)
+		 && (addr < (mem_infos[i].base + mem_infos[i].size))) {
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+			port = 0;
+#else
+			port = i;
+#endif
+			break;
+		}
+	}
+
+	return port;
+}
+
+int mfc_mem_count(void)
+{
+	return mem_ports;
+}
+
+unsigned long mfc_mem_base(int port)
+{
+	if ((port < 0) || (port >= mem_ports))
+		return 0;
+
+	return mem_infos[port].base;
+}
+
+unsigned char *mfc_mem_addr(int port)
+{
+	if ((port < 0) || (port >= mem_ports))
+		return 0;
+
+	return mem_infos[port].addr;
+}
+
+unsigned long mfc_mem_data_base(int port)
+{
+	unsigned long addr;
+
+#ifndef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if ((port < 0) || (port >= mem_ports))
+		return 0;
+#endif
+	if (port == 0)
+		addr = mem_infos[port].base + MFC_FW_SYSTEM_SIZE;
+	else
+		addr = mem_infos[port].base;
+
+	return addr;
+}
+
+unsigned int mfc_mem_data_size(int port)
+{
+	unsigned int size;
+
+#ifndef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if ((port < 0) || (port >= mem_ports))
+		return 0;
+#endif
+	if (port == 0)
+		size = mem_infos[port].size - MFC_FW_SYSTEM_SIZE;
+	else
+		size = mem_infos[port].size;
+
+	return size;
+}
+
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+unsigned int mfc_mem_hole_size(void)
+{
+	if (mfc_mem_data_size(1))
+		return mfc_mem_data_base(1) -
+			(mfc_mem_data_base(0) + mfc_mem_data_size(0));
+	else
+		return 0;
+}
+#endif
+
+unsigned long mfc_mem_data_ofs(unsigned long addr, int contig)
+{
+	unsigned int offset;
+	int i;
+	int port;
+
+	port = mfc_mem_addr_port(addr);
+	if (port < 0)
+		return 0;
+
+	offset = addr - mfc_mem_data_base(port);
+
+	if (contig) {
+		for (i = 0; i < port; i++)
+			offset += mfc_mem_data_size(i);
+	}
+
+	return offset;
+}
+
+unsigned long mfc_mem_base_ofs(unsigned long addr)
+{
+	int port;
+
+	port = mfc_mem_addr_port(addr);
+	if (port < 0)
+		return 0;
+
+	return addr - mem_infos[port].base;
+}
+
+unsigned long mfc_mem_addr_ofs(unsigned long ofs, int from)
+{
+	if (from >= mem_ports)
+		from = mem_ports - 1;
+
+	return mem_infos[from].base + ofs;
+}
+
+long mfc_mem_ext_ofs(unsigned long addr, unsigned int size, int from)
+{
+	int port;
+	long ofs;
+
+	if (from >= mem_ports)
+		from = mem_ports - 1;
+
+	port = mfc_mem_addr_port(addr);
+	if (port < 0) {
+		mfc_dbg("given address is out of MFC: "
+			"0x%08lx\n", addr);
+		port = from;
+	} else if (port != from) {
+		mfc_warn("given address is in the port#%d [%d]",
+			port, from);
+		port = from;
+	}
+
+	ofs = addr - mem_infos[port].base;
+
+	if ((ofs < 0) || (ofs >= MAX_MEM_OFFSET)) {
+		mfc_err("given address cannot access by MFC: "
+			"0x%08lx\n", addr);
+		ofs = -MAX_MEM_OFFSET;
+	} else if ((ofs + size) > MAX_MEM_OFFSET) {
+		mfc_warn("some part of given address cannot access: "
+			"0x%08lx\n", addr);
+	}
+
+	return ofs;
+}
+
+#ifdef SYSMMU_MFC_ON
+#ifdef CONFIG_S5P_VMEM
+void mfc_mem_cache_clean(const void *start_addr, unsigned long size)
+{
+	s5p_vmem_dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+}
+
+void mfc_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	s5p_vmem_dmac_map_area(start_addr, size, DMA_FROM_DEVICE);
+}
+#else /* CONFIG_VIDEO_MFC_VCM_UMP or kernel virtual memory allocator */
+void mfc_mem_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	end_addr = cur_addr + PAGE_ALIGN(size);
+
+	while (cur_addr < end_addr) {
+		paddr = page_to_pfn(vmalloc_to_page(cur_addr));
+		paddr <<= PAGE_SHIFT;
+		if (paddr)
+			outer_clean_range(paddr, paddr + PAGE_SIZE);
+		cur_addr += PAGE_SIZE;
+	}
+
+	/* FIXME: L2 operation optimization */
+	/*
+	unsigned long start, end, unitsize;
+	unsigned long cur_addr, remain;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+
+	cur_addr = (unsigned long)start_addr;
+	remain = size;
+
+	start = page_to_pfn(vmalloc_to_page(cur_addr));
+	start <<= PAGE_SHIFT;
+	if (start & PAGE_MASK) {
+		unitsize = min((start | PAGE_MASK) - start + 1, remain);
+		end = start + unitsize;
+		outer_clean_range(start, end);
+		remain -= unitsize;
+		cur_addr += unitsize;
+	}
+
+	while (remain >= PAGE_SIZE) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + PAGE_SIZE;
+		outer_clean_range(start, end);
+		remain -= PAGE_SIZE;
+		cur_addr += PAGE_SIZE;
+	}
+
+	if (remain) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + remain;
+		outer_clean_range(start, end);
+	}
+	*/
+
+}
+
+void mfc_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+	void *cur_addr, *end_addr;
+
+	cur_addr = (void *)((unsigned long)start_addr & PAGE_MASK);
+	end_addr = cur_addr + PAGE_ALIGN(size);
+
+	while (cur_addr < end_addr) {
+		paddr = page_to_pfn(vmalloc_to_page(cur_addr));
+		paddr <<= PAGE_SHIFT;
+		if (paddr)
+			outer_inv_range(paddr, paddr + PAGE_SIZE);
+		cur_addr += PAGE_SIZE;
+	}
+
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+
+	/* FIXME: L2 operation optimization */
+	/*
+	unsigned long start, end, unitsize;
+	unsigned long cur_addr, remain;
+
+	cur_addr = (unsigned long)start_addr;
+	remain = size;
+
+	start = page_to_pfn(vmalloc_to_page(cur_addr));
+	start <<= PAGE_SHIFT;
+	if (start & PAGE_MASK) {
+		unitsize = min((start | PAGE_MASK) - start + 1, remain);
+		end = start + unitsize;
+		outer_inv_range(start, end);
+		remain -= unitsize;
+		cur_addr += unitsize;
+	}
+
+	while (remain >= PAGE_SIZE) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + PAGE_SIZE;
+		outer_inv_range(start, end);
+		remain -= PAGE_SIZE;
+		cur_addr += PAGE_SIZE;
+	}
+
+	if (remain) {
+		start = page_to_pfn(vmalloc_to_page(cur_addr));
+		start <<= PAGE_SHIFT;
+		end = start + remain;
+		outer_inv_range(start, end);
+	}
+
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+	*/
+}
+#endif	/* end of CONFIG_S5P_VMEM */
+#else	/* not SYSMMU_MFC_ON */
+	/* early allocator */
+	/* CMA or bootmem(memblock) */
+void mfc_mem_cache_clean(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+
+	dmac_map_area(start_addr, size, DMA_TO_DEVICE);
+	/*
+	 * virtual & phsical addrees mapped directly, so we can convert
+	 * the address just using offset
+	 */
+	paddr = __pa((unsigned long)start_addr);
+	outer_clean_range(paddr, paddr + size);
+
+	/* OPT#1: kernel provide below function */
+	/*
+	dma_map_single(NULL, (void *)start_addr, size, DMA_TO_DEVICE);
+	*/
+}
+
+void mfc_mem_cache_inv(const void *start_addr, unsigned long size)
+{
+	unsigned long paddr;
+
+	paddr = __pa((unsigned long)start_addr);
+	outer_inv_range(paddr, paddr + size);
+	dmac_unmap_area(start_addr, size, DMA_FROM_DEVICE);
+
+	/* OPT#1: kernel provide below function */
+	/*
+	dma_unmap_single(NULL, (void *)start_addr, size, DMA_FROM_DEVICE);
+	*/
+}
+#endif /* end of SYSMMU_MFC_ON */
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+static void mfc_tlb_invalidate(enum vcm_dev_id id)
+{
+	if (mfc_power_chk()) {
+		/*mfc_clock_on();*/
+
+		s5p_sysmmu_tlb_invalidate(NULL);
+
+		/*mfc_clock_off();*/
+	}
+}
+
+static void mfc_set_pagetable(enum vcm_dev_id id, unsigned long base)
+{
+	if (mfc_power_chk()) {
+		/*mfc_clock_on();*/
+
+		s5p_sysmmu_set_tablebase_pgd(NULL, base);
+
+		/*mfc_clock_off();*/
+	}
+}
+
+const static struct s5p_vcm_driver mfc_vcm_driver = {
+	.tlb_invalidator = &mfc_tlb_invalidate,
+	.pgd_base_specifier = &mfc_set_pagetable,
+	.phys_alloc = NULL,
+	.phys_free = NULL,
+};
+#endif
+
+#define MAX_ALLOCATION	3
+int mfc_init_mem_mgr(struct mfc_dev *dev)
+{
+	int i;
+#if !defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	dma_addr_t base[MAX_ALLOCATION];
+#else
+	/* FIXME: for support user-side allocation. it's temporary solution */
+	struct vcm_res	*hole;
+#endif
+#ifndef SYSMMU_MFC_ON
+	size_t size;
+#endif
+#ifdef CONFIG_S5P_MEM_CMA
+	struct cma_info cma_infos[2];
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	size_t bound_size;
+	size_t available_size;
+	size_t hole_size;
+#else
+	int cma_index = 0;
+#endif
+#else
+	unsigned int align_margin;
+#endif
+
+	dev->mem_ports = MFC_MAX_MEM_PORT_NUM;
+	memset(dev->mem_infos, 0, sizeof(dev->mem_infos));
+
+#ifdef SYSMMU_MFC_ON
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	dev->vcm_info.sysmmu_vcm = vcm_create_unified(
+		SZ_256M * dev->mem_ports,
+			VCM_DEV_MFC,
+			&mfc_vcm_driver);
+
+	memcpy(&vcm_info, &dev->vcm_info, sizeof(struct mfc_vcm));
+
+	dev->mem_infos[0].vcm_s = vcm_reserve(dev->vcm_info.sysmmu_vcm,
+		MFC_MEMSIZE_PORT_A, 0);
+
+	if (IS_ERR(dev->mem_infos[0].vcm_s))
+		return PTR_ERR(dev->mem_infos[0].vcm_s);
+
+	dev->mem_infos[0].base = ALIGN(dev->mem_infos[0].vcm_s->start,
+		ALIGN_128KB);
+	align_margin = dev->mem_infos[0].base - dev->mem_infos[0].vcm_s->start;
+	/* FIXME: for offset operation. it's temporary solution */
+	/*
+	dev->mem_infos[0].size = MFC_MEMSIZE_PORT_A - align_margin;
+	*/
+	dev->mem_infos[0].size = SZ_256M - align_margin;
+	dev->mem_infos[0].addr = NULL;
+
+	/* FIXME: for support user-side allocation. it's temporary solution */
+	if (MFC_MEMSIZE_PORT_A < SZ_256M)
+		hole = vcm_reserve(dev->vcm_info.sysmmu_vcm,
+			SZ_256M - MFC_MEMSIZE_PORT_A, 0);
+
+	if (dev->mem_ports == 2) {
+		dev->mem_infos[1].vcm_s = vcm_reserve(dev->vcm_info.sysmmu_vcm,
+			MFC_MEMSIZE_PORT_B, 0);
+
+		if (IS_ERR(dev->mem_infos[1].vcm_s)) {
+			vcm_unreserve(dev->mem_infos[0].vcm_s);
+			return PTR_ERR(dev->mem_infos[1].vcm_s);
+		}
+
+		dev->mem_infos[1].base = ALIGN(dev->mem_infos[1].vcm_s->start,
+			ALIGN_128KB);
+		align_margin = dev->mem_infos[1].base - dev->mem_infos[1].vcm_s->start;
+		dev->mem_infos[1].size = MFC_MEMSIZE_PORT_B - align_margin;
+		dev->mem_infos[1].addr = NULL;
+	}
+
+	/* FIXME: for support user-side allocation. it's temporary solution */
+	vcm_unreserve(hole);
+
+	dev->fw.vcm_s = mfc_vcm_bind(dev->mem_infos[0].base, MFC_FW_SYSTEM_SIZE);
+	if (IS_ERR(dev->fw.vcm_s))
+		return PTR_ERR(dev->fw.vcm_s);
+
+	dev->fw.vcm_k = mfc_vcm_map(dev->fw.vcm_s->res.phys);
+	if (IS_ERR(dev->fw.vcm_k)) {
+		mfc_vcm_unbind(dev->fw.vcm_s, 0);
+		return PTR_ERR(dev->fw.vcm_k);
+	}
+
+	/* FIXME: it's very tricky! MUST BE FIX */
+	dev->mem_infos[0].addr = (unsigned char *)dev->fw.vcm_k->start;
+#elif defined(CONFIG_S5P_VMEM)
+	base[0] = MFC_FREEBASE;
+
+	dev->mem_infos[0].base = ALIGN(base[0], ALIGN_128KB);
+	align_margin = dev->mem_infos[0].base - base[0];
+	dev->mem_infos[0].size = MFC_MEMSIZE_PORT_A - align_margin;
+	dev->mem_infos[0].addr = (unsigned char *)dev->mem_infos[0].base;
+
+	if (dev->mem_ports == 2) {
+		base[1] = dev->mem_infos[0].base + dev->mem_infos[0].size;
+		dev->mem_infos[1].base = ALIGN(base[1], ALIGN_128KB);
+		align_margin = dev->mem_infos[1].base - base[1];
+		dev->mem_infos[1].size = MFC_MEMSIZE_PORT_B - align_margin;
+		dev->mem_infos[1].addr = (unsigned char *)dev->mem_infos[1].base;
+	}
+
+	dev->fw.vmem_cookie = s5p_vmem_vmemmap(MFC_FW_SYSTEM_SIZE,
+		dev->mem_infos[0].base,
+		dev->mem_infos[0].base + MFC_FW_SYSTEM_SIZE);
+
+	if (!dev->fw.vmem_cookie)
+		return -ENOMEM;
+#else	/* not CONFIG_VIDEO_MFC_VCM_UMP && not CONFIG_S5P_VMEM */
+	/* kernel virtual memory allocator */
+
+	dev->mem_infos[0].vmalloc_addr = vmalloc(MFC_MEMSIZE_PORT_A);
+	if (dev->mem_infos[0].vmalloc_addr == NULL)
+		return -ENOMEM;
+
+	base[0] = (unsigned long)dev->mem_infos[0].vmalloc_addr;
+	dev->mem_infos[0].base = ALIGN(base[0], ALIGN_128KB);
+	align_margin = dev->mem_infos[0].base - base[0];
+	dev->mem_infos[0].size = MFC_MEMSIZE_PORT_A - align_margin;
+	dev->mem_infos[0].addr = (unsigned char *)dev->mem_infos[0].base;
+
+	if (dev->mem_ports == 2) {
+		dev->mem_infos[1].vmalloc_addr = vmalloc(MFC_MEMSIZE_PORT_B);
+		if (dev->mem_infos[1].vmalloc_addr == NULL) {
+			vfree(dev->mem_infos[0].vmalloc_addr);
+			return -ENOMEM;
+		}
+
+		base[1] = (unsigned long)dev->mem_infos[1].vmalloc_addr;
+		dev->mem_infos[1].base = ALIGN(base[1], ALIGN_128KB);
+		align_margin = dev->mem_infos[1].base - base[1];
+		dev->mem_infos[1].size = MFC_MEMSIZE_PORT_B - align_margin;
+		dev->mem_infos[1].addr = (unsigned char *)dev->mem_infos[1].base;
+	}
+#endif	/* end of CONFIG_VIDEO_MFC_VCM_UMP */
+#else	/* not SYSMMU_MFC_ON */
+	/* early allocator */
+#if defined(CONFIG_S5P_MEM_CMA)
+#ifdef  CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	if (cma_info(&cma_infos[0], dev->device, "A")) {
+		mfc_info("failed to get CMA info of 'mfc-secure'\n");
+		return -ENOMEM;
+	}
+
+	if (cma_info(&cma_infos[1], dev->device, "B")) {
+		mfc_info("failed to get CMA info of 'mfc-normal'\n");
+		return -ENOMEM;
+	}
+
+	if (cma_infos[0].lower_bound > cma_infos[1].lower_bound) {
+		mfc_info("'mfc-secure' region must be lower than 'mfc-normal' region\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * available = secure + normal
+	 * bound = secure + hole + normal
+	 * hole = bound - available
+	 */
+	available_size = cma_infos[0].free_size + cma_infos[1].free_size;
+	bound_size = cma_infos[1].upper_bound - cma_infos[0].lower_bound;
+	hole_size = bound_size - available_size;
+	mfc_dbg("avail: 0x%08x, bound: 0x%08x offset: 0x%08x, hole: 0x%08x\n",
+		available_size, bound_size, MAX_MEM_OFFSET, hole_size);
+
+	/* re-assign actually available size */
+	if (bound_size > MAX_MEM_OFFSET) {
+		if (cma_infos[0].free_size > MAX_MEM_OFFSET)
+			/* it will be return error */
+			available_size = MAX_MEM_OFFSET;
+		else if ((cma_infos[0].free_size + hole_size) >= MAX_MEM_OFFSET)
+			/* it will be return error */
+			available_size = cma_infos[0].free_size;
+		else
+			available_size -= (bound_size - MAX_MEM_OFFSET);
+	}
+	mfc_dbg("avail: 0x%08x\n", available_size);
+
+	size = cma_infos[0].free_size;
+	if (size > available_size) {
+		mfc_info("'mfc-secure' region is too large (%d:%d)",
+			size >> 10,
+			MAX_MEM_OFFSET >> 10);
+		return -ENOMEM;
+	}
+
+	base[0] = cma_alloc(dev->device, "A", size, ALIGN_128KB);
+	if (IS_ERR_VALUE(base[0])) {
+		mfc_err("failed to get rsv. memory from CMA on mfc-secure");
+		return -ENOMEM;
+	}
+
+	dev->mem_infos[0].base = base[0];
+	dev->mem_infos[0].size = size;
+	dev->mem_infos[0].addr = cma_get_virt(base[0], size, 0);
+
+	available_size -= dev->mem_infos[0].size;
+	mfc_dbg("avail: 0x%08x\n", available_size);
+
+	size = MFC_MEMSIZE_DRM;
+	if (size > available_size) {
+		mfc_info("failed to allocate DRM shared area (%d:%d)\n",
+			size >> 10, available_size >> 10);
+		return -ENOMEM;
+	}
+
+	base[1] = cma_alloc(dev->device, "B", size, 0);
+	if (IS_ERR_VALUE(base[1])) {
+		mfc_err("failed to get rsv. memory from CMA for DRM on mfc-normal");
+		cma_free(base[0]);
+		return -ENOMEM;
+	}
+
+	dev->drm_info.base = base[1];
+	dev->drm_info.size = size;
+	dev->drm_info.addr = cma_get_virt(base[1], size, 0);
+
+	available_size -= dev->drm_info.size;
+	mfc_dbg("avail: 0x%08x\n", available_size);
+
+	if (available_size > 0) {
+		size = cma_infos[1].free_size - MFC_MEMSIZE_DRM;
+		if (size > available_size) {
+			mfc_warn("<Warning> large hole between reserved memory, "
+				"'mfc-normal' size will be shrink (%d:%d)\n",
+					size >> 10,
+					available_size >> 10);
+			size = available_size;
+		}
+
+		base[2] = cma_alloc(dev->device, "B", size, ALIGN_128KB);
+		if (IS_ERR_VALUE(base[2])) {
+			mfc_err("failed to get rsv. memory from CMA on mfc-normal");
+			cma_free(base[1]);
+			cma_free(base[0]);
+			return -ENOMEM;
+		}
+
+		dev->mem_infos[1].base = base[2];
+		dev->mem_infos[1].size = size;
+		dev->mem_infos[1].addr = cma_get_virt(base[2], size, 0);
+	}
+#else
+	if (dev->mem_ports == 1) {
+		if (cma_info(&cma_infos[0], dev->device, "AB")) {
+			mfc_info("failed to get CMA info of 'mfc'\n");
+			return -ENOMEM;
+		}
+
+		size = cma_infos[0].free_size;
+		if (size > MAX_MEM_OFFSET) {
+			mfc_warn("<Warning> too large 'mfc' reserved memory, "
+				"size will be shrink (%d:%d)\n",
+				size >> 10,
+				MAX_MEM_OFFSET >> 10);
+			size = MAX_MEM_OFFSET;
+		}
+
+		base[0] = cma_alloc(dev->device, "AB", size, ALIGN_128KB);
+		if (IS_ERR_VALUE(base[0])) {
+			mfc_err("failed to get rsv. memory from CMA");
+			return -ENOMEM;
+		}
+
+		dev->mem_infos[0].base = base[0];
+		dev->mem_infos[0].size = size;
+		dev->mem_infos[0].addr = cma_get_virt(base[0], size, 0);
+	} else if (dev->mem_ports == 2) {
+		if (cma_info(&cma_infos[0], dev->device, "A")) {
+			mfc_info("failed to get CMA info of 'mfc0'\n");
+			return -ENOMEM;
+		}
+
+		if (cma_info(&cma_infos[1], dev->device, "B")) {
+			mfc_info("failed to get CMA info of 'mfc1'\n");
+			return -ENOMEM;
+		}
+
+		if (cma_infos[0].lower_bound > cma_infos[1].lower_bound)
+			cma_index = 1;
+
+		size = cma_infos[cma_index].free_size;
+		if (size > MAX_MEM_OFFSET) {
+			mfc_warn("<Warning> too large 'mfc%d' reserved memory, "
+				"size will be shrink (%d:%d)\n",
+				cma_index, size >> 10,
+				MAX_MEM_OFFSET >> 10);
+			size = MAX_MEM_OFFSET;
+		}
+
+		base[0] = cma_alloc(dev->device, cma_index ? "B" : "A", size, ALIGN_128KB);
+		if (IS_ERR_VALUE(base[0])) {
+			mfc_err("failed to get rsv. memory from CMA on port #0");
+			return -ENOMEM;
+		}
+
+		dev->mem_infos[0].base = base[0];
+		dev->mem_infos[0].size = size;
+		dev->mem_infos[0].addr = cma_get_virt(base[0], size, 0);
+
+		/* swap CMA index */
+		cma_index = !cma_index;
+
+		size = cma_infos[cma_index].free_size;
+		if (size > MAX_MEM_OFFSET) {
+			mfc_warn("<Warning> too large 'mfc%d' reserved memory, "
+				"size will be shrink (%d:%d)\n",
+					cma_index, size >> 10,
+					MAX_MEM_OFFSET >> 10);
+			size = MAX_MEM_OFFSET;
+		}
+
+		base[1] = cma_alloc(dev->device, cma_index ? "B" : "A", size, ALIGN_128KB);
+		if (IS_ERR_VALUE(base[1])) {
+			mfc_err("failed to get rsv. memory from CMA on port #1");
+			cma_free(base[0]);
+			return -ENOMEM;
+		}
+
+		dev->mem_infos[1].base = base[1];
+		dev->mem_infos[1].size = size;
+		dev->mem_infos[1].addr = cma_get_virt(base[1], size, 0);
+	} else {
+		mfc_err("failed to get reserved memory from CMA");
+		return -EPERM;
+	}
+#endif
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+	for (i = 0; i < dev->mem_ports; i++) {
+#ifdef CONFIG_ARCH_EXYNOS4
+		base[i] = s5p_get_media_memory_bank(S5P_MDEV_MFC, i);
+#else
+		base[i] = s3c_get_media_memory_bank(S3C_MDEV_MFC, i);
+#endif
+		if (base[i] == 0) {
+			mfc_err("failed to get rsv. memory from bootmem on port #%d", i);
+			return -EPERM;
+		}
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		size = s5p_get_media_memsize_bank(S5P_MDEV_MFC, i);
+#else
+		size = s3c_get_media_memsize_bank(S3C_MDEV_MFC, i);
+#endif
+		if (size == 0) {
+			mfc_err("failed to get rsv. size from bootmem on port #%d", i);
+			return -EPERM;
+		}
+
+		dev->mem_infos[i].base = ALIGN(base[i], ALIGN_128KB);
+		align_margin = dev->mem_infos[i].base - base[i];
+		dev->mem_infos[i].size = size - align_margin;
+		/* kernel direct mapped memory address */
+		dev->mem_infos[i].addr = phys_to_virt(dev->mem_infos[i].base);
+	}
+#else
+	mfc_err("failed to find valid memory allocator for MFC");
+	return -EPERM;
+#endif	/* end of CONFIG_S5P_MEM_CMA */
+#endif	/* end of SYSMMU_MFC_ON */
+
+	mem_ports = dev->mem_ports;
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	for (i = 0; i < MFC_MAX_MEM_CHUNK_NUM; i++)
+		memcpy(&mem_infos[i], &dev->mem_infos[i], sizeof(struct mfc_mem));
+#else
+	for (i = 0; i < mem_ports; i++)
+		memcpy(&mem_infos[i], &dev->mem_infos[i], sizeof(struct mfc_mem));
+#endif
+	return 0;
+}
+
+void mfc_final_mem_mgr(struct mfc_dev *dev)
+{
+#ifdef SYSMMU_MFC_ON
+#if defined(CONFIG_VIDEO_MFC_VCM_UMP)
+	vcm_unreserve(dev->mem_infos[0].vcm_s);
+	if (dev->mem_ports == 2)
+		vcm_unreserve(dev->mem_infos[1].vcm_s);
+
+	vcm_destroy(dev->vcm_info.sysmmu_vcm);
+#elif defined(CONFIG_S5P_VMEM)
+	s5p_vfree(dev->fw.vmem_cookie);
+#else
+	vfree(dev->mem_infos[0].vmalloc_addr);
+	if (dev->mem_ports == 2)
+		vfree(dev->mem_infos[1].vmalloc_addr);
+#endif	/* CONFIG_VIDEO_MFC_VCM_UMP */
+#else
+	/* no action */
+#endif /* SYSMMU_MFC_ON */
+}
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+void mfc_vcm_dump_res(struct vcm_res *res)
+{
+	mfc_dbg("vcm_res -\n");
+	mfc_dbg("\tstart: 0x%08x, res_size  : 0x%08x\n", (unsigned int)res->start, (unsigned int)res->res_size);
+	mfc_dbg("\tphys : 0x%08x, bound_size: 0x%08x\n", (unsigned int)res->phys, (unsigned int)res->bound_size);
+}
+
+struct vcm_mmu_res *mfc_vcm_bind(unsigned long addr, unsigned int size)
+{
+	struct vcm_mmu_res *s_res;
+	struct vcm_phys *phys;
+	int ret;
+
+	int i;
+
+	s_res = kzalloc(sizeof(struct vcm_mmu_res), GFP_KERNEL);
+	if (unlikely(s_res == NULL)) {
+		mfc_err("no more kernel memory");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	s_res->res.start = addr;
+	s_res->res.res_size = size;
+	s_res->res.vcm = vcm_info.sysmmu_vcm;
+	INIT_LIST_HEAD(&s_res->bound);
+
+	phys = vcm_alloc(vcm_info.sysmmu_vcm, size, 0);
+	if (IS_ERR(phys))
+		return ERR_PTR(PTR_ERR(phys));
+
+	mfc_dbg("phys->size: 0x%08x\n", phys->size);
+	for (i = 0; i < phys->count; i++)
+		mfc_dbg("start 0x%08x, size: 0x%08x\n",
+			(unsigned int)phys->parts[i].start,
+			(unsigned int)phys->parts[i].size);
+
+	ret = vcm_bind(&s_res->res, phys);
+	if (ret < 0)
+		return ERR_PTR(ret);
+
+	mfc_vcm_dump_res(&s_res->res);
+
+	return s_res;
+}
+
+void mfc_vcm_unbind(struct vcm_mmu_res *s_res, int flag)
+{
+	struct vcm_phys *phys;
+
+	phys = vcm_unbind(&s_res->res);
+
+	/* Flag means...
+	 * 0 : allocated by MFC
+	 * 1 : allocated by other IP */
+	if (flag == 0)
+	vcm_free(phys);
+
+	kfree(s_res);
+}
+
+struct vcm_res *mfc_vcm_map(struct vcm_phys *phys)
+{
+	struct vcm_res *res;
+
+	res = vcm_map(vcm_vmm, phys, 0);
+
+	mfc_vcm_dump_res(res);
+
+	return res;
+}
+
+void mfc_vcm_unmap(struct vcm_res *res)
+{
+	vcm_unmap(res);
+}
+
+void *mfc_ump_map(struct vcm_phys *phys, unsigned long vcminfo)
+{
+	struct vcm_phys_part *part = phys->parts;
+	int num_blocks = phys->count;
+	ump_dd_physical_block *blocks;
+	ump_dd_handle handle;
+	int i;
+
+	blocks = (ump_dd_physical_block *)vmalloc(sizeof(ump_dd_physical_block) * num_blocks);
+
+	for(i = 0; i < num_blocks; i++) {
+		blocks[i].addr = part->start;
+		blocks[i].size = part->size;
+		++part;
+
+		mfc_dbg("\tblock 0x%08lx, size: 0x%08lx\n", blocks[i].addr, blocks[i].size);
+	}
+
+	handle = ump_dd_handle_create_from_phys_blocks(blocks, num_blocks);
+	/*
+	ump_dd_reference_add(handle);
+	*/
+
+	vfree(blocks);
+
+	if (handle == UMP_DD_HANDLE_INVALID)
+		return ERR_PTR(-ENOMEM);
+
+	if (ump_dd_meminfo_set(handle, (void*)vcminfo) != UMP_DD_SUCCESS)
+		return ERR_PTR(-ENOMEM);
+
+	return (void *)handle;
+}
+
+void mfc_ump_unmap(void *handle)
+{
+	ump_dd_reference_release(handle);
+}
+
+unsigned int mfc_ump_get_id(void *handle)
+{
+	return ump_dd_secure_id_get(handle);
+}
+
+unsigned long mfc_ump_get_virt(unsigned int secure_id)
+{
+	struct vcm_res *res = (struct vcm_res *)
+		ump_dd_meminfo_get(secure_id, (void*)VCM_DEV_MFC);
+
+	if (res) {
+		return res->start;
+	} else {
+		mfc_err("failed to get device virtual, id: %d",
+			(unsigned int)secure_id);
+
+		return 0;
+	}
+}
+#endif /* CONFIG_VIDEO_MFC_VCM_UMP */
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_mem.h b/drivers/media/video/samsung/mfc5x/mfc_mem.h
new file mode 100644
index 0000000..bc1bc6d
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_mem.h
@@ -0,0 +1,76 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_mem.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Memory manager for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_MEM_H_
+#define __MFC_MEM_H_ __FILE__
+
+#include "mfc.h"
+#include "mfc_dev.h"
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+#include <plat/s5p-vcm.h>
+#endif
+
+#ifdef CONFIG_S5P_VMEM
+#include <linux/dma-mapping.h>
+
+extern unsigned int s5p_vmem_vmemmap(size_t size, unsigned long va_start,
+		unsigned long va_end);
+extern void s5p_vfree(unsigned int cookie);
+extern unsigned int s5p_getcookie(void *addr);
+extern void *s5p_getaddress(unsigned int cookie);
+extern void s5p_vmem_dmac_map_area(const void *start_addr,
+		unsigned long size, int dir);
+#endif
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+struct vcm_res;
+
+struct vcm_mmu_res {
+	struct vcm_res			res;
+	struct list_head		bound;
+};
+#endif
+
+int mfc_mem_count(void);
+unsigned long mfc_mem_base(int port);
+unsigned char *mfc_mem_addr(int port);
+unsigned long mfc_mem_data_base(int port);
+unsigned int mfc_mem_data_size(int port);
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+unsigned int mfc_mem_hole_size(void);
+#endif
+unsigned long mfc_mem_data_ofs(unsigned long addr, int contig);
+unsigned long mfc_mem_base_ofs(unsigned long addr);
+unsigned long mfc_mem_addr_ofs(unsigned long ofs, int from);
+long mfc_mem_ext_ofs(unsigned long addr, unsigned int size, int from);
+
+void mfc_mem_cache_clean(const void *start_addr, unsigned long size);
+void mfc_mem_cache_inv(const void *start_addr, unsigned long size);
+
+int mfc_init_mem_mgr(struct mfc_dev *dev);
+void mfc_final_mem_mgr(struct mfc_dev *dev);
+
+#ifdef CONFIG_VIDEO_MFC_VCM_UMP
+void mfc_vcm_dump_res(struct vcm_res *res);
+struct vcm_mmu_res *mfc_vcm_bind(unsigned int addr, unsigned int size);
+void mfc_vcm_unbind(struct vcm_mmu_res *s_res, int flag);
+struct vcm_res *mfc_vcm_map(struct vcm_phys *phys);
+void mfc_vcm_unmap(struct vcm_res *res);
+void *mfc_ump_map(struct vcm_phys *phys, unsigned long vcminfo);
+void mfc_ump_unmap(void *handle);
+unsigned int mfc_ump_get_id(void *handle);
+unsigned long mfc_ump_get_virt(unsigned int secure_id);
+#endif
+
+#endif /* __MFC_MEM_H_ */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_pm.c b/drivers/media/video/samsung/mfc5x/mfc_pm.c
new file mode 100644
index 0000000..6f40437
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_pm.c
@@ -0,0 +1,198 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Power management module for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#ifdef CONFIG_PM_RUNTIME
+#include <linux/pm_runtime.h>
+#endif
+#include <linux/interrupt.h>
+
+#include <plat/clock.h>
+#include <plat/s5p-mfc.h>
+#include <plat/cpu.h>
+
+#include <mach/regs-pmu.h>
+
+#include <asm/io.h>
+
+#include "mfc_dev.h"
+#include "mfc_log.h"
+
+#define MFC_PARENT_CLK_NAME	"mout_mfc0"
+#define MFC_CLKNAME		"sclk_mfc"
+#define MFC_GATE_CLK_NAME	"mfc"
+
+#undef CLK_DEBUG
+
+static struct mfc_pm *pm;
+
+#ifdef CLK_DEBUG
+atomic_t clk_ref;
+#endif
+
+int mfc_init_pm(struct mfc_dev *mfcdev)
+{
+	struct clk *parent, *sclk;
+	int ret = 0;
+
+	pm = &mfcdev->pm;
+
+	parent = clk_get(mfcdev->device, MFC_PARENT_CLK_NAME);
+	if (IS_ERR(parent)) {
+		printk(KERN_ERR "failed to get parent clock\n");
+		ret = -ENOENT;
+		goto err_gp_clk;
+	}
+
+	sclk = clk_get(mfcdev->device, MFC_CLKNAME);
+	if (IS_ERR(sclk)) {
+		printk(KERN_ERR "failed to get source clock\n");
+		ret = -ENOENT;
+		goto err_gs_clk;
+	}
+
+	ret = clk_set_parent(sclk, parent);
+	if (ret) {
+		printk(KERN_ERR "unable to set parent %s of clock %s\n",
+				parent->name, sclk->name);
+		goto err_sp_clk;
+	}
+
+	/* FIXME: clock name & rate have to move to machine code */
+	ret = clk_set_rate(sclk, mfc_clk_rate);
+	if (ret) {
+		printk(KERN_ERR "%s rate change failed: %u\n", sclk->name, 200 * 1000000);
+		goto err_ss_clk;
+	}
+
+	/* clock for gating */
+	pm->clock = clk_get(mfcdev->device, MFC_GATE_CLK_NAME);
+	if (IS_ERR(pm->clock)) {
+		printk(KERN_ERR "failed to get clock-gating control\n");
+		ret = -ENOENT;
+		goto err_gg_clk;
+	}
+
+	atomic_set(&pm->power, 0);
+
+#ifdef CONFIG_PM_RUNTIME
+	pm->device = mfcdev->device;
+	pm_runtime_enable(pm->device);
+#endif
+
+#ifdef CLK_DEBUG
+	atomic_set(&clk_ref, 0);
+#endif
+
+	return 0;
+
+err_gg_clk:
+err_ss_clk:
+err_sp_clk:
+	clk_put(sclk);
+err_gs_clk:
+	clk_put(parent);
+err_gp_clk:
+	return ret;
+}
+
+void mfc_final_pm(struct mfc_dev *mfcdev)
+{
+#ifdef CONFIG_PM_RUNTIME
+	pm_runtime_disable(pm->device);
+#endif
+}
+
+int mfc_clock_on(struct mfc_dev *mfcdev)
+{
+	int ret;
+#ifdef CLK_DEBUG
+	atomic_inc(&clk_ref);
+	mfc_dbg("+ %d", atomic_read(&clk_ref));
+#endif
+
+	ret = clk_enable(pm->clock);
+	enable_irq(mfcdev->irq);
+	return  ret;
+}
+
+void mfc_clock_off(struct mfc_dev *mfcdev)
+{
+#ifdef CLK_DEBUG
+	atomic_dec(&clk_ref);
+	mfc_dbg("- %d", atomic_read(&clk_ref));
+#endif
+	disable_irq(mfcdev->irq);
+	clk_disable(pm->clock);
+}
+
+int mfc_power_on(void)
+{
+#ifdef CONFIG_PM_RUNTIME
+	if ((soc_is_exynos4212() && (samsung_rev() < EXYNOS4212_REV_1_0)) ||
+		(soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_1)))
+		return 0;
+	else
+		return pm_runtime_get_sync(pm->device);
+#else
+	atomic_set(&pm->power, 1);
+
+	return 0;
+#endif
+}
+
+int mfc_power_off(void)
+{
+#ifdef CONFIG_PM_RUNTIME
+	if ((soc_is_exynos4212() && (samsung_rev() < EXYNOS4212_REV_1_0)) ||
+		(soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_1)))
+		return 0;
+	else
+		return pm_runtime_put_sync(pm->device);
+#else
+	atomic_set(&pm->power, 0);
+
+	return 0;
+#endif
+}
+
+bool mfc_power_chk(void)
+{
+	mfc_dbg("%s", atomic_read(&pm->power) ? "on" : "off");
+
+	return atomic_read(&pm->power) ? true : false;
+}
+
+void mfc_pd_enable(void)
+{
+	u32 timeout;
+
+	__raw_writel(S5P_INT_LOCAL_PWR_EN, S5P_PMU_MFC_CONF);
+
+	/* Wait max 1ms */
+	timeout = 10;
+	while ((__raw_readl(S5P_PMU_MFC_CONF + 0x4) & S5P_INT_LOCAL_PWR_EN)
+		!= S5P_INT_LOCAL_PWR_EN) {
+		if (timeout == 0) {
+			printk(KERN_ERR "Power domain MFC enable failed.\n");
+			break;
+		}
+
+		timeout--;
+
+		udelay(100);
+	}
+}
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_pm.h b/drivers/media/video/samsung/mfc5x/mfc_pm.h
new file mode 100644
index 0000000..ac370ca
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_pm.h
@@ -0,0 +1,29 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_pm.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Power management module for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_PM_H
+#define __MFC_PM_H __FILE__
+
+int mfc_init_pm(struct mfc_dev *mfcdev);
+void mfc_final_pm(struct mfc_dev *mfcdev);
+
+int mfc_clock_on(struct mfc_dev *mfcdev);
+void mfc_clock_off(struct mfc_dev *mfcdev);
+int mfc_power_on(void);
+int mfc_power_off(void);
+#ifdef CONFIG_CPU_EXYNOS4210
+bool mfc_power_chk(void);
+#endif
+void mfc_pd_enable(void);
+
+#endif /* __MFC_PM_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_reg.c b/drivers/media/video/samsung/mfc5x/mfc_reg.c
new file mode 100644
index 0000000..91375f1
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_reg.c
@@ -0,0 +1,32 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_regs.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+
+static void __iomem *regs;
+
+void init_reg(void __iomem *base)
+{
+	regs = base;
+}
+
+void write_reg(unsigned int data, unsigned int offset)
+{
+	__raw_writel(data, regs + offset);
+}
+
+unsigned int read_reg(unsigned int offset)
+{
+	return __raw_readl(regs + offset);
+}
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_reg.h b/drivers/media/video/samsung/mfc5x/mfc_reg.h
new file mode 100644
index 0000000..11d9ab0
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_reg.h
@@ -0,0 +1,21 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_regs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Register interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_REGS_H
+#define __MFC_REGS_H __FILE__
+
+void init_reg(void __iomem *base);
+void write_reg(unsigned int data, unsigned int offset);
+unsigned int read_reg(unsigned int offset);
+
+#endif /* __MFC_REGS_H */
diff --git a/drivers/media/video/samsung/mfc5x/mfc_shm.c b/drivers/media/video/samsung/mfc5x/mfc_shm.c
new file mode 100644
index 0000000..58638f1
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_shm.c
@@ -0,0 +1,88 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_shm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Shared memory interface file for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+
+#include "mfc_inst.h"
+#include "mfc_mem.h"
+#include "mfc_buf.h"
+#include "mfc_log.h"
+
+int init_shm(struct mfc_inst_ctx *ctx)
+{
+#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION
+	struct mfc_dev *dev = ctx->dev;
+	struct mfc_alloc_buffer *alloc;
+
+	if (ctx->drm_flag) {
+		ctx->shm = (unsigned char *)(dev->drm_info.addr + MFC_SHM_OFS_DRM
+			+ MFC_SHM_SIZE*ctx->id);
+		ctx->shmofs = mfc_mem_ext_ofs(dev->drm_info.base + MFC_SHM_OFS_DRM
+			+ MFC_SHM_SIZE*ctx->id, MFC_SHM_SIZE, PORT_A);
+
+		if (ctx->shmofs >= 0) {
+			memset((void *)ctx->shm, 0, MFC_SHM_SIZE);
+			mfc_mem_cache_clean((void *)ctx->shm, MFC_SHM_SIZE);
+
+			return 0;
+		}
+	} else {
+		alloc = _mfc_alloc_buf(ctx, MFC_SHM_SIZE, ALIGN_4B, MBT_SHM | PORT_A);
+
+		if (alloc != NULL) {
+			ctx->shm = alloc->addr;
+			ctx->shmofs = mfc_mem_base_ofs(alloc->real);
+
+			memset((void *)ctx->shm, 0, MFC_SHM_SIZE);
+			mfc_mem_cache_clean((void *)ctx->shm, MFC_SHM_SIZE);
+
+			return 0;
+		}
+	}
+#else
+	struct mfc_alloc_buffer *alloc;
+
+	alloc = _mfc_alloc_buf(ctx, MFC_SHM_SIZE, ALIGN_4B, MBT_SHM | PORT_A);
+
+	if (alloc != NULL) {
+		ctx->shm = alloc->addr;
+		ctx->shmofs = mfc_mem_base_ofs(alloc->real);
+
+		memset((void *)ctx->shm, 0, MFC_SHM_SIZE);
+		mfc_mem_cache_clean((void *)ctx->shm, MFC_SHM_SIZE);
+
+		return 0;
+	}
+#endif
+	mfc_err("failed alloc shared memory buffer\n");
+
+	ctx->shm = NULL;
+	ctx->shmofs = 0;
+
+	return -1;
+}
+
+void write_shm(struct mfc_inst_ctx *ctx, unsigned int data, unsigned int offset)
+{
+	writel(data, (ctx->shm + offset));
+
+	mfc_mem_cache_clean((void *)((unsigned int)(ctx->shm) + offset), 4);
+}
+
+unsigned int read_shm(struct mfc_inst_ctx *ctx, unsigned int offset)
+{
+	mfc_mem_cache_inv((void *)((unsigned int)(ctx->shm) + offset), 4);
+
+	return readl(ctx->shm + offset);
+}
+
diff --git a/drivers/media/video/samsung/mfc5x/mfc_shm.h b/drivers/media/video/samsung/mfc5x/mfc_shm.h
new file mode 100644
index 0000000..e5d7ba7
--- /dev/null
+++ b/drivers/media/video/samsung/mfc5x/mfc_shm.h
@@ -0,0 +1,82 @@
+/*
+ * linux/drivers/media/video/samsung/mfc5x/mfc_shm.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Shared memory interface for Samsung MFC (Multi Function Codec - FIMV) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFC_SHM_H
+#define __MFC_SHM_H __FILE__
+
+enum MFC_SHM_OFS
+{
+	EXTENEDED_DECODE_STATUS		= 0x0000, /* D */
+	SET_FRAME_TAG			= 0x0004, /* D */
+	GET_FRAME_TAG_TOP		= 0x0008, /* D */
+	GET_FRAME_TAG_BOT		= 0x000C, /* D */
+	PIC_TIME_TOP			= 0x0010, /* D */
+	PIC_TIME_BOT			= 0x0014, /* D */
+	START_BYTE_NUM			= 0x0018, /* D */
+	CROP_INFO1			= 0x0020, /* D, H.264 */
+	CROP_INFO2			= 0x0024, /* D, H.264 */
+	EXT_ENC_CONTROL			= 0x0028, /* E */
+	ENC_PARAM_CHANGE		= 0x002C, /* E */
+	VOP_TIMING			= 0x0030, /* E, MPEG4 */
+	HEC_PERIOD			= 0x0034, /* E, MPEG4 */
+	METADATA_ENABLE			= 0x0038, /* C */
+	METADATA_STATUS			= 0x003C, /* C */
+	METADATA_DISPLAY_INDEX		= 0x0040, /* C */
+	EXT_METADATA_START_ADDR		= 0x0044, /* C */
+	PUT_EXTRADATA			= 0x0048, /* C */
+	EXTRADATA_ADDR			= 0x004C, /* C */
+	ALLOCATED_LUMA_DPB_SIZE		= 0x0064, /* D */
+	ALLOCATED_CHROMA_DPB_SIZE	= 0x0068, /* D */
+	ALLOCATED_MV_SIZE		= 0x006C, /* D */
+	P_B_FRAME_QP			= 0x0070, /* E */
+	ASPECT_RATIO_IDC		= 0x0074, /* E, H.264, depend on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+	EXTENDED_SAR			= 0x0078, /* E, H.264, depned on ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
+	DISP_PIC_PROFILE		= 0x007C, /* D */
+	FLUSH_CMD_TYPE			= 0x0080, /* C */
+	FLUSH_CMD_INBUF1		= 0x0084, /* C */
+	FLUSH_CMD_INBUF2		= 0x0088, /* C */
+	FLUSH_CMD_OUTBUF		= 0x008C, /* E */
+	NEW_RC_BIT_RATE			= 0x0090, /* E, format as RC_BIT_RATE(0xC5A8) depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
+	NEW_RC_FRAME_RATE		= 0x0094, /* E, format as RC_FRAME_RATE(0xD0D0) depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
+	NEW_I_PERIOD			= 0x0098, /* E, format as I_FRM_CTRL(0xC504) depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
+	H264_I_PERIOD			= 0x009C, /* E, H.264, open GOP */
+	RC_CONTROL_CONFIG		= 0x00A0, /* E */
+	BATCH_INPUT_ADDR		= 0x00A4, /* E */
+	BATCH_OUTPUT_ADDR		= 0x00A8, /* E */
+	BATCH_OUTPUT_SIZE		= 0x00AC, /* E */
+	MIN_LUMA_DPB_SIZE		= 0x00B0, /* D */
+	DEVICE_FORMAT_ID		= 0x00B4, /* C */
+	H264_POC_TYPE			= 0x00B8, /* D */
+	MIN_CHROMA_DPB_SIZE		= 0x00BC, /* D */
+	DISP_PIC_FRAME_TYPE		= 0x00C0, /* D */
+	FREE_LUMA_DPB			= 0x00C4, /* D, VC1 MPEG4 */
+	ASPECT_RATIO_INFO		= 0x00C8, /* D, MPEG4 */
+	EXTENDED_PAR			= 0x00CC, /* D, MPEG4 */
+	DBG_HISTORY_INPUT0		= 0x00D0, /* C */
+	DBG_HISTORY_INPUT1		= 0x00D4, /* C */
+	DBG_HISTORY_OUTPUT		= 0x00D8, /* C */
+	HIERARCHICAL_P_QP		= 0x00E0, /* E, H.264 */
+	HW_VERSRION			= 0x010C, /* C */
+	SEI_ENABLE			= 0x0168, /* C, H.264 */
+	FRAME_PACK_SEI_AVAIL		= 0x016C, /* D, H.264 */
+	FRAME_PACK_ARRGMENT_ID		= 0x0170, /* D, H.264 */
+	FRAME_PACK_DEC_INFO		= 0x0174, /* D, H.264 */
+	FRAME_PACK_GRID_POS		= 0x0178, /* D, H.264 */
+	FRAME_PACK_ENC_INFO		= 0x017C, /* E, H.264 */
+};
+
+int init_shm(struct mfc_inst_ctx *ctx);
+void write_shm(struct mfc_inst_ctx *ctx, unsigned int data, unsigned int offset);
+unsigned int read_shm(struct mfc_inst_ctx *ctx, unsigned int offset);
+
+#endif /* __MFC_SHM_H */
diff --git a/drivers/media/video/samsung/tsi/Kconfig b/drivers/media/video/samsung/tsi/Kconfig
new file mode 100644
index 0000000..6de7906
--- /dev/null
+++ b/drivers/media/video/samsung/tsi/Kconfig
@@ -0,0 +1,19 @@
+#
+# Configuration for rotator
+#
+
+config VIDEO_TSI
+	bool "Samsung Transport Stream Interface"
+	depends on VIDEO_SAMSUNG && (CPU_EXYNOS4210 || CPU_S5PC100 || CPU_S5PC110 || CPU_S5PV210 || CPU_S5PV310)
+	default n
+	---help---
+	  This is a Transport Stream Interface for Samsung  S5PC110.
+
+config VIDEO_TSI_DEBUG
+	bool "print TSI debug message"
+	depends on VIDEO_TSI
+	default n
+config TSI_LIST_DEBUG
+	bool "print TSI list debug message"
+	depends on VIDEO_TSI
+	default n
diff --git a/drivers/media/video/samsung/tsi/Makefile b/drivers/media/video/samsung/tsi/Makefile
new file mode 100644
index 0000000..9bbac3e
--- /dev/null
+++ b/drivers/media/video/samsung/tsi/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for the tsi device drivers.
+#
+obj-$(CONFIG_VIDEO_TSI)	+= s3c-tsi.o
diff --git a/drivers/media/video/samsung/tsi/s3c-tsi.c b/drivers/media/video/samsung/tsi/s3c-tsi.c
new file mode 100644
index 0000000..50a1ae0
--- /dev/null
+++ b/drivers/media/video/samsung/tsi/s3c-tsi.c
@@ -0,0 +1,959 @@
+/* linux/drivers/media/video/samsung/s3c-tsi.c
+ *
+ * Driver file for Samsung Transport Stream Interface
+ *
+ *  Copyright (c) 2009 Samsung Electronics
+ *	http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/miscdevice.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-tsi.h>
+#else
+#include <plat/map.h>
+#include <plat/regs-clock.h>
+#include <plat/regs-tsi.h>
+#endif
+#include <plat/gpio-cfg.h>
+
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/poll.h>
+#include <linux/slab.h>
+#endif
+
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+#define TSI_BUF_SIZE	(128*1024)
+#define TSI_PKT_CNT      16
+#else
+#define TSI_BUF_SIZE	(256*1024)
+#endif
+
+enum filter_mode	{
+	OFF,
+	ON
+};
+
+enum pid_filter_mode	{
+	BYPASS = 0,
+	FILTERING
+};
+
+enum data_byte_order	{
+	MSB2LSB = 0,
+	LSB2MSB
+};
+typedef struct	{
+  struct list_head list;
+  dma_addr_t addr;
+  void *buf;
+  u32 len;
+} tsi_pkt;
+
+
+typedef struct	{
+	enum filter_mode flt_mode;
+	enum pid_filter_mode pid_flt_mode;
+	enum data_byte_order byte_order;
+	u16  burst_len;
+	u8  sync_detect;
+	u8  byte_swap;
+	u16 pad_pattern;
+	u16 num_packet;
+} s3c_tsi_conf;
+
+
+typedef struct {
+	spinlock_t tsi_lock;
+	struct clk *tsi_clk;
+	struct resource *tsi_mem;
+/*	struct resource *tsi_irq;	*/
+	void __iomem	*tsi_base;
+	int tsi_irq;
+	int running;
+#if defined(CONFIG_PM) && defined(CONFIG_TARGET_LOCALE_NTT)
+	int last_running_state;
+#endif
+	int new_pkt;
+	dma_addr_t	tsi_buf_phy;
+	void	*tsi_buf_virt;
+	u32		tsi_buf_size;
+	s3c_tsi_conf *tsi_conf;
+	struct list_head free_list;
+	struct list_head full_list;
+	struct list_head partial_list;
+	wait_queue_head_t read_wq;
+} tsi_dev;
+
+tsi_dev *tsi_priv;
+
+static struct platform_device *s3c_tsi_dev;
+
+/* #define DRIVER_LOGIC_CHK */
+#ifdef DRIVER_LOGIC_CHK
+static struct timer_list tsi_timer;
+#endif
+
+
+/* debug macro */
+#define TSI_DEBUG(fmt, ...)                                     \
+		do {                                                    \
+			printk(								\
+			"%s: " fmt, __func__, ##__VA_ARGS__);				\
+		} while (0)
+
+#define TSI_WARN(fmt, ...)                                      \
+		do {                                                    \
+			printk(KERN_WARNING					\
+			fmt, ##__VA_ARGS__);						\
+		} while (0)
+
+#define TSI_ERROR(fmt, ...)                                     \
+		do {                                                    \
+			printk(KERN_ERR						\
+			"%s: " fmt, __func__, ##__VA_ARGS__);				\
+		} while (0)
+
+
+/*#define CONFIG_VIDEO_TSI_DEBUG */
+#ifdef CONFIG_VIDEO_TSI_DEBUG
+#define tsi_dbg(fmt, ...)               TSI_DEBUG(fmt, ##__VA_ARGS__)
+#else
+#define tsi_dbg(fmt, ...)
+#endif
+
+#define tsi_warn(fmt, ...)              TSI_WARN(fmt, ##__VA_ARGS__)
+#define tsi_err(fmt, ...)               TSI_ERROR(fmt, ##__VA_ARGS__)
+
+#define tsi_list_dbg(fmt, ...)		TSI_DEBUG(fmt, ##__VA_ARGS__)
+
+
+#ifdef CONFIG_TSI_LIST_DEBUG
+void list_debug(struct list_head *head)
+{
+	int i;
+	tsi_pkt *pkt;
+	/* tsi_list_dbg("DEBUGGING FREE LIST\n"); */
+    i = 1;
+	list_for_each_entry(pkt, head, list)	{
+	tsi_list_dbg(" node %d node_addr %x physical add %p virt add %p size %d\n",
+					i, pkt, pkt->addr, pkt->buf, pkt->len);
+		i++;
+	}
+}
+#endif
+
+/*This should be done in platform*/
+void s3c_tsi_set_gpio(void)
+{
+	/*  CLK */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE0(0), S3C_GPIO_SFN(4));
+	s3c_gpio_setpull(EXYNOS4210_GPE0(0), S3C_GPIO_PULL_NONE);
+
+	/*  DTEN */
+	s3c_gpio_cfgpin(EXYNOS4210_GPE0(2), S3C_GPIO_SFN(4));
+	s3c_gpio_setpull(EXYNOS4210_GPE0(2), S3C_GPIO_PULL_NONE);
+
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+	printk(" %s : system_rev %d\n", __func__, system_rev);
+
+	if (system_rev >= 11) {
+		/*  DATA */
+		s3c_gpio_cfgpin(EXYNOS4210_GPE0(3), S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(EXYNOS4210_GPE0(3), S3C_GPIO_PULL_NONE);
+	}
+#else
+	/*  DATA */
+	s3c_gpio_cfgpin(S5PV310_GPE0(3), S3C_GPIO_SFN(4));
+	s3c_gpio_setpull(S5PV310_GPE0(3), S3C_GPIO_PULL_NONE);
+#endif
+
+#if !defined(CONFIG_TARGET_LOCALE_NTT)
+	/*  SYNC */
+	s3c_gpio_cfgpin(S5PV310_GPE0(1), S3C_GPIO_SFN(4));
+	s3c_gpio_setpull(S5PV310_GPE0(1), S3C_GPIO_PULL_NONE);
+#endif
+}
+
+
+void s3c_tsi_reset(tsi_dev *tsi)
+{
+	u32 tscon;
+	tscon = readl((tsi->tsi_base + S3C_TS_CON));
+	tscon |= S3C_TSI_SWRESET  ;
+	writel(tscon, (tsi->tsi_base + S3C_TS_CON));
+}
+
+void s3c_tsi_set_timeout(u32 count, tsi_dev *tsi)
+{
+	writel(count, (tsi->tsi_base + S3C_TS_CNT));
+}
+
+tsi_pkt *tsi_get_pkt(tsi_dev *tsi, struct list_head *head)
+{
+	unsigned long flags;
+	tsi_pkt *pkt;
+	spin_lock_irqsave(&tsi->tsi_lock, flags);
+
+	if (list_empty(head))	{
+		tsi_err("TSI %p list is null\n", head);
+		spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+		return NULL;
+	}
+	pkt = list_first_entry(head, tsi_pkt, list);
+	spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+
+	return pkt;
+}
+
+void s3c_tsi_set_dest_addr(dma_addr_t addr, u32 reg)
+{
+	 writel(addr, reg);
+}
+
+void s3c_tsi_set_sync_mode(u8 mode, u32 reg)
+{
+	writel(mode, reg);
+}
+
+void s3c_tsi_set_clock(u8 enable, u32 reg)
+{
+	u32 val = 0;
+	if (enable)
+		val |= 0x1;
+	writel(val, reg);
+}
+
+void tsi_enable_interrupts(tsi_dev *tsi)
+{
+	u32 mask;
+	/* Enable all the interrupts... */
+	mask = 0xFF;
+	writel(mask, (tsi->tsi_base + S3C_TS_INTMASK));
+}
+
+void tsi_disable_interrupts(tsi_dev *tsi)
+{
+	writel(0, (tsi->tsi_base + S3C_TS_INTMASK));
+}
+
+static int s3c_tsi_start(tsi_dev *tsi)
+{
+	unsigned long flags;
+	u32 pkt_size;
+	tsi_pkt *pkt1;
+	pkt1 =	tsi_get_pkt(tsi, &tsi->free_list);
+	if (pkt1 == NULL)	{
+		tsi_err("Failed to start TSI--No buffers avaialble\n");
+		return -1;
+	}
+	pkt_size = pkt1->len;
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	/*	when set the TS BUF SIZE to the S3C_TS_SIZE,
+	if you want get a 10-block TS from TSIF,
+	you should set the value of S3C_TS_SIZE as 47*10(not 188*10)
+	This register get a value of word-multiple values.
+	So, pkt_size which is counted to BYTES must be divided by 4
+	(2 bit shift lefted)
+	Commented by sjinu, 2009_03_18
+	*/
+	writel(pkt_size>>2, (tsi->tsi_base+S3C_TS_SIZE));
+#else
+	writel(pkt_size, (tsi->tsi_base+S3C_TS_SIZE));
+#endif
+	s3c_tsi_set_dest_addr(pkt1->addr, (u32)(tsi->tsi_base+S3C_TS_BASE));
+
+	spin_lock_irqsave(&tsi->tsi_lock, flags);
+	list_move_tail(&pkt1->list, &tsi->partial_list);
+	spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+	/* start the clock */
+	s3c_tsi_set_clock(TSI_CLK_START, (u32)(tsi->tsi_base+S3C_TS_CLKCON));
+	/* set the next buffer immediatly */
+	pkt1 =	tsi_get_pkt(tsi, &tsi->free_list);
+	if (pkt1 == NULL)	{
+		tsi_err("Failed to start TSI--No buffers avaialble\n");
+		return -1;
+	}
+	s3c_tsi_set_dest_addr(pkt1->addr, (u32)(tsi->tsi_base+S3C_TS_BASE));
+	spin_lock_irqsave(&tsi->tsi_lock, flags);
+	list_move_tail(&pkt1->list, &tsi->partial_list);
+	spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+	tsi_enable_interrupts(tsi);
+
+#ifdef CONFIG_TSI_LIST_DEBUG1
+	tsi_list_dbg("Debugging Partial list\n");
+	list_debug(&tsi->partial_list);
+	tsi_list_dbg("Debugging free list\n");
+	list_debug(&tsi->free_list);
+#endif
+	return 0;
+}
+
+static int s3c_tsi_stop(tsi_dev *tsi)
+{
+	unsigned long flags;
+	tsi_pkt *pkt;
+	struct list_head *full = &tsi->full_list;
+	struct list_head *partial = &tsi->partial_list;
+
+	spin_lock_irqsave(&tsi->tsi_lock, flags);
+	#ifdef DRIVER_LOGIC_CHK
+	del_timer(&tsi_timer);
+	#endif
+
+	tsi_disable_interrupts(tsi);
+	s3c_tsi_set_clock(TSI_CLK_STOP, (u32)(tsi->tsi_base+S3C_TS_CLKCON));
+	/* move all the packets from partial and full list to free list */
+	while (!list_empty(full))	{
+		pkt = list_entry(full->next, tsi_pkt, list);
+		list_move_tail(&pkt->list, &tsi->free_list);
+	}
+
+	while (!list_empty(partial))	{
+		pkt = list_entry(partial->next, tsi_pkt, list);
+		list_move_tail(&pkt->list, &tsi->free_list);
+	}
+	tsi->running = 0;
+	tsi_priv->new_pkt = 0;
+	spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+
+	return 0;
+}
+
+void s3c_tsi_setup(tsi_dev *tsi)
+{
+	u32 tscon;
+	s3c_tsi_conf *conf = tsi->tsi_conf;
+	s3c_tsi_reset(tsi);
+	s3c_tsi_set_timeout(TS_TIMEOUT_CNT_MAX, tsi);
+
+	tscon = readl((tsi->tsi_base+S3C_TS_CON));
+
+	tscon &= ~(S3C_TSI_SWRESET_MASK|S3C_TSI_CLKFILTER_MASK|
+		S3C_TSI_BURST_LEN_MASK | S3C_TSI_INT_FIFO_FULL_INT_ENA_MASK |
+		S3C_TSI_SYNC_MISMATCH_INT_MASK | S3C_TSI_PSUF_INT_MASK|
+		S3C_TSI_PSOF_INT_MASK | S3C_TSI_TS_CLK_TIME_OUT_INT_MASK |
+		S3C_TSI_TS_ERROR_MASK | S3C_TSI_PID_FILTER_MASK |
+		S3C_TSI_ERROR_ACTIVE_MASK | S3C_TSI_DATA_BYTE_ORDER_MASK |
+		S3C_TSI_TS_VALID_ACTIVE_MASK | S3C_TSI_SYNC_ACTIVE_MASK |
+		S3C_TSI_CLK_INVERT_MASK);
+
+	tscon |= (conf->flt_mode << S3C_TSI_CLKFILTER_SHIFT);
+	tscon |= (conf->pid_flt_mode << S3C_TSI_PID_FILTER_SHIFT);
+	tscon |= (conf->byte_order << S3C_TSI_DATA_BYTE_ORDER_SHIFT);
+	tscon |= (conf->burst_len << S3C_TSI_BURST_LEN_SHIFT);
+	tscon |= (conf->pad_pattern << S3C_TSI_PAD_PATTERN_SHIFT);
+
+	tscon |= (S3C_TSI_OUT_BUF_FULL_INT_ENA | S3C_TSI_INT_FIFO_FULL_INT_ENA);
+	tscon |= (S3C_TSI_SYNC_MISMATCH_INT_SKIP | S3C_TSI_PSUF_INT_SKIP |
+					S3C_TSI_PSOF_INT_SKIP);
+	tscon |= (S3C_TSI_TS_CLK_TIME_OUT_INT);
+	/* These values are bd dependent? */
+	tscon |= (S3C_TSI_TS_VALID_ACTIVE_HIGH | S3C_TSI_CLK_INVERT_HIGH);
+	writel(tscon, (tsi->tsi_base+S3C_TS_CON));
+	s3c_tsi_set_sync_mode(conf->sync_detect, (u32)(tsi->tsi_base+S3C_TS_SYNC));
+}
+
+void s3c_tsi_rx_int(tsi_dev *tsi)
+{
+	tsi_pkt *pkt;
+	/* deque the pcket from partial list to full list
+		incase the free list is empty, stop the tsi.. */
+
+	pkt = tsi_get_pkt(tsi, &tsi->partial_list);
+
+	/* this situation should not come.. stop_tsi */
+	if (pkt == NULL)	{
+		tsi_err("TSI..Receive interrupt without buffer\n");
+		s3c_tsi_stop(tsi);
+		return;
+	}
+
+	tsi_dbg("moving %p node %x phy %p virt to full list\n",
+			pkt, pkt->addr, pkt->buf);
+
+	list_move_tail(&pkt->list, &tsi->full_list);
+
+	pkt = tsi_get_pkt(tsi, &tsi->free_list);
+	if (pkt == NULL)	{
+		/* this situation should not come.. stop_tsi */
+		tsi_err("TSI..No more free bufs..stopping channel\n");
+		s3c_tsi_stop(tsi);
+		return;
+	}
+	list_move_tail(&pkt->list, &tsi->partial_list);
+
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	/*	namkh, request from Abraham
+		If there arise a buffer-full interrupt,
+		a new ts buffer address should be set.
+
+		Commented by sjinu, 2009_03_18	*/
+	s3c_tsi_set_dest_addr(pkt->addr, (u32)(tsi->tsi_base+S3C_TS_BASE));
+#endif
+
+#ifdef CONFIG_TSI_LIST_DEBUG
+	tsi_list_dbg("Debugging Full list\n");
+	list_debug(&tsi->full_list);
+	tsi_list_dbg("Debugging Partial list\n");
+	list_debug(&tsi->partial_list);
+#endif
+	tsi->new_pkt = 1;
+	wake_up(&tsi->read_wq);
+}
+
+
+static irqreturn_t s3c_tsi_irq(int irq, void *dev_id)
+{
+	u32 intpnd;
+	tsi_dev *tsi = platform_get_drvdata((struct platform_device *)dev_id);
+	intpnd = readl(tsi->tsi_base + S3C_TS_INT);
+	tsi_dbg("INTPND is %x\n", intpnd);
+	writel(intpnd, (tsi->tsi_base+S3C_TS_INT));
+
+	if (intpnd & S3C_TSI_OUT_BUF_FULL)
+		s3c_tsi_rx_int(tsi);
+	return IRQ_HANDLED;
+}
+
+static int s3c_tsi_release(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+	tsi_dev *tsi = file->private_data;
+	tsi_dbg("TSI_RELEASE\n");
+	if (tsi->running)	{
+		tsi_dbg("TSI_RELEASE stopping\n");
+		tsi->running = 0;
+		ret = s3c_tsi_stop(tsi);
+		tsi_dbg("TSI_RELEASE LIST cleaned\n");
+	}
+
+#ifdef CONFIG_TSI_LIST_DEBUG
+	tsi_list_dbg("Debugging Full list\n");
+	list_debug(&tsi->full_list);
+	tsi_list_dbg("Debugging Partial list\n");
+	list_debug(&tsi->partial_list);
+#endif
+
+	return ret;
+}
+
+int s3c_tsi_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+static unsigned int	s3c_tsi_poll(struct file *file, poll_table *wait)
+{
+	unsigned int mask = 0;
+	tsi_dev *tsi = file->private_data;
+
+	poll_wait(file, &tsi->read_wq, wait);
+
+	if (tsi->new_pkt)
+		mask |= (POLLIN | POLLRDNORM);
+
+	return mask;
+}
+#endif
+
+static ssize_t s3c_tsi_read(struct file *file, char *buf, size_t count, loff_t *pos)
+{
+	unsigned long flags;
+	int ret = 0;
+	u32 len = 0, pkt_size = 0;
+	tsi_pkt *pkt;
+	tsi_dev *tsi = file->private_data;
+	struct list_head *full = &tsi->full_list;
+
+#ifdef CONFIG_TSI_LIST_DEBUG
+	tsi_list_dbg("Debugging Full list\n");
+	tsi_dbg("count is %d\n", count);
+	list_debug(&tsi->full_list);
+#endif
+
+#if defined(CONFIG_CPU_S5PV210)  || defined(CONFIG_TARGET_LOCALE_NTT)
+	ret = wait_event_interruptible(tsi->read_wq, tsi->new_pkt);
+	if (ret < 0)	{
+		tsi_dbg("woken up from signal..returning\n");
+		return ret;
+	}
+	pkt = tsi_get_pkt(tsi, full);
+
+	pkt_size = pkt->len;	/* pkt_size should be multiple of 188 bytes. */
+
+	tsi_dbg("pkt_size is %d\n", pkt_size);
+		if (pkt_size > count)
+			pkt_size = count;
+
+		if (copy_to_user((buf+len), pkt->buf, pkt_size)) {
+			tsi_dbg("copy user fail\n");
+			ret = -EFAULT;
+			return ret;
+		}
+
+		len += pkt_size;
+		count -= pkt_size;
+		tsi_dbg("len is%d count %d pkt_size %d\n", len, count, pkt_size);
+		ret = len;
+		spin_lock_irqsave(&tsi->tsi_lock, flags);
+		list_move(&pkt->list, &tsi->free_list);
+		spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+
+		if (list_empty(full))
+			tsi->new_pkt = 0;
+#else
+	while (count > 0)	{
+		/* deque packet from full list */
+		pkt = tsi_get_pkt(tsi, full);
+		if (pkt == NULL)	{
+			ret = wait_event_interruptible(tsi->read_wq, tsi->new_pkt);
+
+			if (ret < 0)		{
+				tsi_dbg("woken up from signal..returning\n");
+				return ret;
+			}
+			tsi_dbg("woken up proprt\n");
+			pkt = tsi_get_pkt(tsi, full);
+
+		}
+		pkt_size = pkt->len * 4;
+		if (pkt_size > count)
+			pkt_size = count;
+
+		if (copy_to_user((buf+len), pkt->buf, pkt_size))	{
+			tsi_dbg("copy user fail\n");
+			ret = -EFAULT;
+			break;
+		}
+
+		len += pkt_size;
+		count -= pkt_size;
+		tsi_dbg("len is%d count %d pkt_size %d\n", len, count, pkt_size);
+		ret = len;
+		spin_lock_irqsave(&tsi->tsi_lock, flags);
+		list_move(&pkt->list, &tsi->free_list);
+		spin_unlock_irqrestore(&tsi->tsi_lock, flags);
+
+		if (list_empty(full))
+			tsi->new_pkt = 0;
+	}
+#endif
+
+#ifdef CONFIG_TSI_LIST_DEBUG1
+	tsi_list_dbg("Debugging Free list\n");
+	list_debug(&tsi->free_list);
+#endif
+	return ret;
+}
+
+#define TSI_TRIGGER	0xAABB
+#define TSI_STOP	0xAACC
+
+static long s3c_tsi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	tsi_dev *tsi = platform_get_drvdata(s3c_tsi_dev);
+	/* currently only two ioctl for tigger and stop are provided.. */
+	tsi_dbg("TSI cmd is %x\n", cmd);
+	switch (cmd)	{
+		case TSI_TRIGGER:
+			if (tsi->running)
+				return -EBUSY;
+			tsi->running = 1;
+			ret = s3c_tsi_start(tsi);
+		#ifdef DRIVER_LOGIC_CHK
+			tsi_timer.expires = jiffies + HZ/10;
+			add_timer(&tsi_timer);
+		#endif
+			break;
+		case TSI_STOP:
+			tsi->running = 0;
+			ret =	s3c_tsi_stop(tsi);
+			break;
+		default:
+			break;
+	}
+	return ret;
+}
+
+static int s3c_tsi_open(struct inode *inode, struct file *file)
+{
+	tsi_dev *s3c_tsi = platform_get_drvdata(s3c_tsi_dev);
+	tsi_dbg(" %s\n", __func__);
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	/* Fix the TSI data problem (Don't generated waking up sleep state)
+	clk_enable(s3c_tsi->tsi_clk);
+	*/
+	s3c_tsi_setup(s3c_tsi);
+#endif
+	file->private_data = s3c_tsi;
+	return 0;
+}
+
+static struct file_operations tsi_fops = {
+	owner:		THIS_MODULE,
+	open :		s3c_tsi_open,
+	release :	s3c_tsi_release,
+	unlocked_ioctl		:	s3c_tsi_ioctl,
+	read :		s3c_tsi_read,
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	poll :		s3c_tsi_poll,
+#endif
+	mmap :		s3c_tsi_mmap,
+};
+
+
+static struct miscdevice s3c_tsi_miscdev = {
+	minor:		MISC_DYNAMIC_MINOR,
+	name :		"s3c-tsi",
+	fops :		&tsi_fops
+};
+
+static int tsi_setup_bufs(tsi_dev *dev, struct list_head *head)
+{
+	tsi_pkt *pkt;
+	u32 tsi_virt, tsi_size, buf_size;
+	u16 num_buf;
+	dma_addr_t tsi_phy;
+	int i;
+
+	tsi_phy = dev->tsi_buf_phy;
+	tsi_virt = (u32) dev->tsi_buf_virt;
+	tsi_size = dev->tsi_buf_size;
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	/* TSI generates interrupt after filling this many bytes */
+	buf_size = dev->tsi_conf->num_packet * TS_PKT_SIZE*TSI_PKT_CNT;
+#else
+	/* TSI generates interrupt after filling this many bytes */
+	buf_size = dev->tsi_conf->num_packet * TS_PKT_SIZE;
+#endif
+	num_buf = (tsi_size / buf_size);
+
+	for (i = 0; i < num_buf; i++)	{
+		pkt = kmalloc(sizeof(tsi_pkt), GFP_KERNEL);
+		if (!pkt)
+			return list_empty(head) ? -ENOMEM : 0 ;
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+		/*	Address should be byte-aligned
+			Commented by sjinu, 2009_03_18	*/
+		pkt->addr = ((u32)tsi_phy + i*buf_size);
+		pkt->buf = (void *)(u8 *)((u32)tsi_virt + i*buf_size);
+#else
+		pkt->addr = (tsi_phy + i*4*buf_size);
+		pkt->buf = (void *)(tsi_virt + i*4*buf_size);
+#endif
+		pkt->len = buf_size;
+		list_add_tail(&pkt->list, head);
+	}
+
+	tsi_dbg("total nodes calulated %d buf_size %d\n", num_buf, buf_size);
+#ifdef CONFIG_TSI_LIST_DEBUG1
+	list_debug(head);
+#endif
+
+return 0;
+
+}
+
+#ifdef DRIVER_LOGIC_CHK
+int timer_count = 100;
+
+void tsi_timer_function(u32 dev)
+{
+	tsi_dev *tsi = (tsi_dev *)(dev);
+	s3c_tsi_rx_int(tsi);
+	tsi_timer.expires = jiffies + HZ/100;
+	timer_count--;
+	if (timer_count > 0)
+		add_timer(&tsi_timer);
+}
+#endif
+
+static int s3c_tsi_probe(struct platform_device *pdev)
+{
+	struct resource	*res;
+	static int		size;
+	static int		ret;
+	s3c_tsi_conf	*conf;
+	dma_addr_t		map_dma;
+	struct device *dev = &pdev->dev;
+
+	tsi_dbg(" %s\n", __func__);
+	tsi_priv = kmalloc(sizeof(tsi_dev), GFP_KERNEL);
+	if (tsi_priv == NULL)	{
+		printk("NO Memory for tsi allocation\n");
+		return -ENOMEM;
+	}
+	conf = kmalloc(sizeof(s3c_tsi_conf), GFP_KERNEL);
+	if (conf == NULL)	{
+		printk("NO Memory for tsi conf allocation\n");
+		kfree(tsi_priv);
+		return -ENOMEM;
+	}
+	/* Initialise the dafault conf parameters..
+	 * this should be obtained from the platform data and ioctl
+	 * move this to platform later */
+
+	conf->flt_mode    = OFF;
+	conf->pid_flt_mode = BYPASS;
+	conf->byte_order = MSB2LSB;
+#if defined(CONFIG_TARGET_LOCALE_NTT)
+	conf->sync_detect = S3C_TSI_SYNC_DET_MODE_TS_SYNC_BYTE;
+#else
+	conf->sync_detect = S3C_TSI_SYNC_DET_MODE_TS_SYNC8;
+#endif
+
+#if defined(CONFIG_CPU_S5PV210) || defined(CONFIG_TARGET_LOCALE_NTT)
+	/*
+	 to avoid making interrupt during getting the TS from TS buffer,
+	 we use the burst-length as 8 beat.
+	 This burst-length may be changed next time.
+	 Commented by sjinu, 2009_03_18
+	*/
+	conf->burst_len = 2;
+#else
+	conf->burst_len = 0;
+#endif
+	conf->byte_swap = 1;	/* little endian */
+	conf->pad_pattern = 0;	/* this might vary from bd to bd */
+	conf->num_packet = TS_NUM_PKT;	/* this might vary from bd to bd */
+
+	tsi_priv->tsi_conf = conf;
+	tsi_priv->tsi_buf_size = TSI_BUF_SIZE;
+
+	tsi_priv->tsi_clk = clk_get(NULL, "tsi");
+	//printk("Clk Get Result %x\n", tsi_priv->tsi_clk);
+	if (tsi_priv->tsi_clk == NULL)	{
+			printk(KERN_ERR "Failed to get TSI clock\n");
+			return -ENOENT;
+	}
+	clk_enable(tsi_priv->tsi_clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (res == NULL)	{
+		tsi_err("failed to get memory region resouce\n");
+		return -ENOENT;
+	}
+
+	size = (res->end - res->start) + 1;
+	tsi_priv->tsi_mem = request_mem_region(res->start, size, pdev->name);
+
+	if (tsi_priv->tsi_mem  == NULL)	{
+		tsi_err("failed to get memory region\n");
+		return -ENOENT;
+	}
+
+	ret = platform_get_irq(pdev, 0);
+
+	if (ret == 0)	{
+		tsi_err("failed to get irq resource\n");
+		ret = -ENOENT;
+		goto err_res;
+	}
+
+	tsi_priv->tsi_irq = ret;
+	ret = request_irq(tsi_priv->tsi_irq, (void *)s3c_tsi_irq, 0, pdev->name, pdev);
+
+	if (ret != 0)	{
+		tsi_err("failed to install irq (%d)\n", ret);
+		goto err_res;
+	}
+
+	tsi_priv->tsi_base = ioremap(tsi_priv->tsi_mem->start, size);
+
+	if (tsi_priv->tsi_base == 0)	{
+		tsi_err("failed to ioremap() region\n");
+		ret = -EINVAL;
+		goto err_irq;
+	}
+
+	INIT_LIST_HEAD(&tsi_priv->free_list);
+	INIT_LIST_HEAD(&tsi_priv->full_list);
+	INIT_LIST_HEAD(&tsi_priv->partial_list);
+	spin_lock_init(&tsi_priv->tsi_lock);
+	init_waitqueue_head(&tsi_priv->read_wq);
+	tsi_priv->new_pkt = 0;
+	tsi_priv->running = 0;
+#if defined(CONFIG_PM) && defined(CONFIG_TARGET_LOCALE_NTT)
+	tsi_priv->last_running_state = tsi_priv->running;
+#endif
+
+	/* get the dma coherent mem */
+	tsi_priv->tsi_buf_virt = dma_alloc_coherent(dev, tsi_priv->tsi_buf_size, &map_dma, GFP_KERNEL);
+	if (tsi_priv->tsi_buf_virt == NULL)	{
+		tsi_err("Failed to claim TSI memory\n");
+		ret = -ENOMEM;
+		goto err_map;
+	}
+
+	tsi_dbg("TSI dev dma mem phy %x virt %p\n", map_dma, tsi_priv->tsi_buf_virt);
+
+	tsi_priv->tsi_buf_phy = map_dma;
+
+	ret = tsi_setup_bufs(tsi_priv, &tsi_priv->free_list);
+	if (ret)	{
+		tsi_err("TSI failed to setup pkt list");
+		goto err_clk;
+	}
+
+	platform_set_drvdata(pdev, tsi_priv);
+	s3c_tsi_set_gpio();
+	s3c_tsi_setup(tsi_priv);
+	s3c_tsi_dev = pdev;
+	ret = misc_register(&s3c_tsi_miscdev);
+	if (ret)	{
+		tsi_err("Unable to register the s3c-tsi driver\n");
+		goto err_clk;
+	}
+
+#ifdef DRIVER_LOGIC_CHK
+	init_timer(&tsi_timer);
+	tsi_timer.function = tsi_timer_function;
+	tsi_timer.data = (unsigned long) tsi_priv;
+/*
+	s3c_tsi_start(tsi_priv);
+	s3c_tsi_rx_int(tsi_priv);
+*/
+#endif
+
+	return 0;
+
+err_clk:
+	  clk_disable(tsi_priv->tsi_clk);
+err_map:
+	iounmap(tsi_priv->tsi_base);
+err_irq:
+	free_irq(tsi_priv->tsi_irq, pdev);
+err_res:
+	release_resource(tsi_priv->tsi_mem);
+	kfree(tsi_priv);
+
+	return ret;
+}
+
+static void tsi_free_packets(tsi_dev *tsi)
+{
+	tsi_pkt *pkt;
+	struct list_head *head = &(tsi->free_list);
+
+	while (!list_empty(head))	{
+		pkt = list_entry(head->next, tsi_pkt, list);
+		list_del(&pkt->list);
+		kfree(pkt);
+	}
+}
+
+static int s3c_tsi_remove(struct platform_device *dev)
+{
+	tsi_dev *tsi = platform_get_drvdata((struct platform_device *)dev);
+	if (tsi->running)
+		s3c_tsi_stop(tsi);
+
+	/* free allocated memory and nodes */
+	tsi_free_packets(tsi);
+	free_irq(tsi->tsi_irq, dev);
+	dma_free_coherent(&dev->dev, tsi->tsi_buf_size, tsi->tsi_buf_virt, tsi->tsi_buf_phy);
+	kfree(tsi);
+	return 0;
+}
+
+
+#if defined(CONFIG_PM) && defined(CONFIG_TARGET_LOCALE_NTT)
+static int s3c_tsi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	tsi_dev *tsi = platform_get_drvdata(s3c_tsi_dev);
+
+	tsi->last_running_state = tsi->running;
+	if (tsi_priv->last_running_state)
+		s3c_tsi_stop(tsi_priv);
+
+	clk_disable(tsi_priv->tsi_clk);
+
+	return 0;
+}
+
+static int s3c_tsi_resume(struct platform_device *pdev)
+{
+	tsi_dev *tsi = platform_get_drvdata(s3c_tsi_dev);
+
+	clk_enable(tsi_priv->tsi_clk);
+	s3c_tsi_set_gpio();
+	s3c_tsi_setup(tsi_priv);
+
+	if (tsi->last_running_state) {
+		tsi->running = 1;
+		s3c_tsi_start(tsi);
+		s3c_tsi_rx_int(tsi);
+	}
+	return 0;
+}
+
+#endif
+
+static struct platform_driver s3c_tsi_driver = {
+	.probe		= s3c_tsi_probe,
+	.remove		= s3c_tsi_remove,
+	.shutdown	= NULL,
+#if defined(CONFIG_PM) && defined(CONFIG_TARGET_LOCALE_NTT)
+	.suspend	= s3c_tsi_suspend,
+	.resume		= s3c_tsi_resume,
+#else
+	.suspend	= NULL,
+	.resume		= NULL,
+#endif
+	.driver		= {
+			.owner	= THIS_MODULE,
+			.name	= "s3c-tsi",
+	},
+};
+
+
+
+const char banner[] __initdata =  "TSI Driver Version 1.0\n";
+
+static int __init s3c_tsi_init(void)
+{
+	printk(banner);
+	tsi_dbg(" %s\n", __func__);
+	return platform_driver_register(&s3c_tsi_driver);
+}
+
+
+
+
+static void __exit s3c_tsi_exit(void)
+{
+
+	platform_driver_unregister(&s3c_tsi_driver);
+}
+
+
+
+module_init(s3c_tsi_init);
+module_exit(s3c_tsi_exit);
+
+MODULE_AUTHOR("Samsung");
+MODULE_DESCRIPTION("S3C TSI Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/tvout/Kconfig b/drivers/media/video/samsung/tvout/Kconfig
new file mode 100644
index 0000000..176efeb
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/Kconfig
@@ -0,0 +1,174 @@
+#
+# Configuration for TV driver
+#
+
+config VIDEO_TVOUT
+	bool "Samsung TVOUT Driver"
+	depends on VIDEO_SAMSUNG
+	default y
+	---help---
+	  This is a TVOUT driver for Samsung S5P platform
+
+choice
+depends on VIDEO_TVOUT
+prompt "Select default audio channel"
+default VIDEO_TVOUT_2CH_AUDIO
+config VIDEO_TVOUT_2CH_AUDIO
+	bool "2ch audio mode"
+	depends on VIDEO_TVOUT
+	---help---
+	  TV out supports 2 channel audio
+
+config VIDEO_TVOUT_5_1CH_AUDIO
+	bool "5.1ch audio mode"
+	depends on VIDEO_TVOUT
+	---help---
+	  TV out supports 5.1 channel audio
+endchoice
+
+config HDMI_CEC
+	bool "HDMI CEC driver support."
+	depends on VIDEO_TVOUT && ARCH_EXYNOS4
+	default n
+	---help---
+	  This is a HDMI CEC driver for Samsung S5P platform.
+	  Check dev node (major 10, minor 242)
+
+config HDMI_EARJACK_MUTE
+	bool "HDMI Earjack support"
+	depends on VIDEO_TVOUT
+	default n
+	---help---
+	  Say y here if you intend to provide sysfs interface for audio
+	  framework to control HDMI audio. Android audio framework will
+	  refer to the following node:
+	  "sys/class/hdmi_audio/hdmi_audio/hdmi_audio_set_ext"
+
+config HDMI_HPD
+	bool "HDMI HPD driver support."
+	depends on VIDEO_TVOUT && ARCH_EXYNOS4
+	default y
+	---help---
+	  This is a HDMI HPD driver for Samsung S5P platform.
+	  Check dev node (major 10, minor 243)
+
+config HDMI_CONTROLLED_BY_EXT_IC
+	bool "External HDMI related IC support"
+	depends on HDMI_HPD
+	default n
+	---help---
+	  Say y here if the H/W has external IC to control HDMI hpd and
+	  it needs to be controlled by HPD interrupt.
+	  For example, the H/W has HDMI level shifter then it should be turned
+	  on when HPD interrupt comes.
+
+config HDMI_SWITCH_HPD
+	bool "HDMI HPD switch uevent driver support"
+	depends on HDMI_HPD
+	default y
+	---help---
+	  Say y here if you intend to use switch uevent instaed of
+	  costumized kobject uevent. Android framework will refer to
+	  the following device node to get HPD event:
+	  "/sys/devices/virtual/switch/hdmi/state"
+
+config HDMI_14A_3D
+	bool "HDMI 14A driver support."
+	depends on VIDEO_TVOUT && ARCH_EXYNOS4 && CPU_EXYNOS4212
+	default y
+	---help---
+	  This is a HDMI 1.4A 3D driver for Samsung S5P platform.
+
+config HDMI_PHY_32N
+	bool "HDMI PHY 32N driver support."
+	depends on VIDEO_TVOUT && HDMI_14A_3D && ARCH_EXYNOS4
+	default y
+	---help---
+	  This is a HDMI PHY version for Samsung S5P platform.
+
+config ANALOG_TVENC
+	bool "Analog driver support."
+	depends on VIDEO_TVOUT && ARCH_EXYNOS4 && CPU_EXYNOS4210
+	default n
+	---help---
+	  This is a analog TVENC driver for Samsung S5P platform.
+
+config VPLL_USE_FOR_TVENC
+	bool "VPLL use for TVENC."
+	depends on VIDEO_TVOUT && ANALOG_TVENC && ARCH_EXYNOS4
+	default n
+	---help---
+	  This is a VPLL use of TVENC for Samsung S5P platform.
+
+config TV_FB
+	bool "TVOUT frame buffer driver support."
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+
+	depends on VIDEO_TVOUT && FB && ARCH_EXYNOS4
+	default y
+	---help---
+
+config USER_ALLOC_TVOUT
+	bool "Support pre allocated frame buffer memory."
+	depends on VIDEO_TVOUT && TV_FB
+	default y
+	---help---
+	  TV Driver doesn't allocate memory for frame buffer.
+	  So, before enabling TV out, the frame buffer should be allocated.
+
+config TV_FB_NUM
+	int "Index of TVOUT frame buffer"
+	depends on VIDEO_TVOUT && TV_FB && !USER_ALLOC_TVOUT
+	default 5
+	---help---
+
+config LSI_HDMI_AUDIO_CH_EVENT
+	bool "Support uevent of multi-channel audio info for hdmi"
+	default n
+	---help---
+	  receive audio channel info from platform using ioctl.
+	  	#define AUDIO_CH_SET_STATE _IOR('H', 101, unsigned int)
+	  and send this to platform using uevent
+	  	audio_ch_switch.name = "hdmi_audio_ch";
+
+config TV_DEBUG
+	bool "TVOUT driver debug message"
+	depends on VIDEO_TVOUT
+	default n
+
+config VP_DEBUG
+	bool "Video Processor debug message"
+	depends on TV_DEBUG
+	default n
+
+config MIXER_DEBUG
+	bool "Mixer debug message"
+	depends on TV_DEBUG
+	default n
+
+config HDMI_DEBUG
+	bool "HDMI debug message"
+	depends on TV_DEBUG
+	default n
+
+config SDO_DEBUG
+	bool "SDO(Composite) debug message"
+	depends on TV_DEBUG
+	default n
+
+config HDCP_DEBUG
+	bool "HDCP debug message"
+	depends on TV_DEBUG
+	default n
+
+config CEC_DEBUG
+	bool "CEC debug message"
+	depends on TV_DEBUG
+	default n
+
+config HPD_DEBUG
+	bool "HPD debug message"
+	depends on TV_DEBUG
+	default n
diff --git a/drivers/media/video/samsung/tvout/Makefile b/drivers/media/video/samsung/tvout/Makefile
new file mode 100644
index 0000000..81d358f
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/Makefile
@@ -0,0 +1,27 @@
+# linux/drivers/media/video/samsung/tvout/Makefile
+#
+# Copyright (c) 2009 Samsung Electronics
+#		http://www.samsung.com/
+#
+# Makefile for Samsung TVOUT driver
+
+ifeq ($(CONFIG_VIDEO_TVOUT_DEBUG), y)
+EXTRA_CFLAGS += -DDEBUG
+endif
+ifeq ($(CONFIG_VIDEO_UMP),y)
+    EXTRA_CFLAGS += -Idrivers/media/video/samsung/ump/include
+endif
+
+obj-$(CONFIG_VIDEO_TVOUT) :=	s5p_tvout.o		\
+				s5p_tvout_v4l2.o	\
+				s5p_tvout_fb.o		\
+				s5p_tvout_common_lib.o	\
+				s5p_mixer_ctrl.o	\
+				s5p_vp_ctrl.o		\
+				s5p_tvif_ctrl.o
+
+obj-$(CONFIG_HDMI_HPD) +=	s5p_tvout_hpd.o
+
+obj-$(CONFIG_HDMI_CEC) +=	s5p_tvout_cec.o
+
+obj-$(CONFIG_VIDEO_TVOUT) += hw_if/
diff --git a/drivers/media/video/samsung/tvout/hw_if/Makefile b/drivers/media/video/samsung/tvout/hw_if/Makefile
new file mode 100644
index 0000000..d416a7d
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/Makefile
@@ -0,0 +1,19 @@
+# linux/drivers/media/video/samsung/tvout/hw_if/Makefile
+#
+# Copyright (c) 2009 Samsung Electronics
+#		http://www.samsung.com/
+#
+# Makefile for Samsung TVOUT driver
+
+ifeq ($(CONFIG_VIDEO_TVOUT_DEBUG), y)
+EXTRA_CFLAGS += -DDEBUG
+endif
+obj-$(CONFIG_VIDEO_TVOUT) +=	mixer.o		\
+				vp.o		\
+				hdmi.o		\
+				hdcp.o
+
+obj-$(CONFIG_ANALOG_TVENC) +=	sdo.o
+
+
+obj-$(CONFIG_HDMI_CEC) +=	cec.o
diff --git a/drivers/media/video/samsung/tvout/hw_if/cec.c b/drivers/media/video/samsung/tvout/hw_if/cec.c
new file mode 100644
index 0000000..5554459
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/cec.c
@@ -0,0 +1,262 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/cec.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * cec ftn file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-cec.h>
+
+#include "../s5p_tvout_common_lib.h"
+#include "hw_if.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_CEC_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "\t\t[CEC] %s(): " fmt,	\
+			__func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+
+#define S5P_HDMI_FIN			24000000
+#define CEC_DIV_RATIO			320000
+
+#define CEC_MESSAGE_BROADCAST_MASK	0x0F
+#define CEC_MESSAGE_BROADCAST		0x0F
+#define CEC_FILTER_THRESHOLD		0x15
+
+static struct resource	*cec_mem;
+void __iomem		*cec_base;
+
+struct cec_rx_struct cec_rx_struct;
+struct cec_tx_struct cec_tx_struct;
+
+
+void s5p_cec_set_divider(void)
+{
+	u32 div_ratio, reg, div_val;
+
+	div_ratio  = S5P_HDMI_FIN / CEC_DIV_RATIO - 1;
+
+	reg = readl(S5P_HDMI_PHY_CONTROL);
+	reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16);
+
+	writel(reg, S5P_HDMI_PHY_CONTROL);
+
+	div_val = CEC_DIV_RATIO * 0.00005 - 1;
+
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_3);
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_2);
+	writeb(0x0, cec_base + S5P_CES_DIVISOR_1);
+	writeb(div_val, cec_base + S5P_CES_DIVISOR_0);
+}
+
+void s5p_cec_enable_rx(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_RX_CTRL);
+	reg |= S5P_CES_RX_CTRL_ENABLE;
+	writeb(reg, cec_base + S5P_CES_RX_CTRL);
+}
+
+void s5p_cec_mask_rx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg |= S5P_CES_IRQ_RX_DONE;
+	reg |= S5P_CES_IRQ_RX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_unmask_rx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg &= ~S5P_CES_IRQ_RX_DONE;
+	reg &= ~S5P_CES_IRQ_RX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_mask_tx_interrupts(void)
+{
+	u8 reg;
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg |= S5P_CES_IRQ_TX_DONE;
+	reg |= S5P_CES_IRQ_TX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+
+}
+
+void s5p_cec_unmask_tx_interrupts(void)
+{
+	u8 reg;
+
+	reg = readb(cec_base + S5P_CES_IRQ_MASK);
+	reg &= ~S5P_CES_IRQ_TX_DONE;
+	reg &= ~S5P_CES_IRQ_TX_ERROR;
+	writeb(reg, cec_base + S5P_CES_IRQ_MASK);
+}
+
+void s5p_cec_reset(void)
+{
+	writeb(S5P_CES_RX_CTRL_RESET, cec_base + S5P_CES_RX_CTRL);
+	writeb(S5P_CES_TX_CTRL_RESET, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_tx_reset(void)
+{
+	writeb(S5P_CES_TX_CTRL_RESET, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_rx_reset(void)
+{
+	writeb(S5P_CES_RX_CTRL_RESET, cec_base + S5P_CES_RX_CTRL);
+}
+
+void s5p_cec_threshold(void)
+{
+	writeb(CEC_FILTER_THRESHOLD, cec_base + S5P_CES_RX_FILTER_TH);
+	writeb(0, cec_base + S5P_CES_RX_FILTER_CTRL);
+}
+
+void s5p_cec_set_tx_state(enum cec_state state)
+{
+	atomic_set(&cec_tx_struct.state, state);
+}
+
+void s5p_cec_set_rx_state(enum cec_state state)
+{
+	atomic_set(&cec_rx_struct.state, state);
+}
+
+void s5p_cec_copy_packet(char *data, size_t count)
+{
+	int i = 0;
+	u8 reg;
+
+	while (i < count) {
+		writeb(data[i], cec_base + (S5P_CES_TX_BUFF0 + (i * 4)));
+		i++;
+	}
+
+	writeb(count, cec_base + S5P_CES_TX_BYTES);
+	s5p_cec_set_tx_state(STATE_TX);
+	reg = readb(cec_base + S5P_CES_TX_CTRL);
+	reg |= S5P_CES_TX_CTRL_START;
+
+	if ((data[0] & CEC_MESSAGE_BROADCAST_MASK) == CEC_MESSAGE_BROADCAST)
+		reg |= S5P_CES_TX_CTRL_BCAST;
+	else
+		reg &= ~S5P_CES_TX_CTRL_BCAST;
+
+	reg |= 0x50;
+	writeb(reg, cec_base + S5P_CES_TX_CTRL);
+}
+
+void s5p_cec_set_addr(u32 addr)
+{
+	writeb(addr & 0x0F, cec_base + S5P_CES_LOGIC_ADDR);
+}
+
+u32 s5p_cec_get_status(void)
+{
+	u32 status = 0;
+
+	status = readb(cec_base + S5P_CES_STATUS_0);
+	status |= readb(cec_base + S5P_CES_STATUS_1) << 8;
+	status |= readb(cec_base + S5P_CES_STATUS_2) << 16;
+	status |= readb(cec_base + S5P_CES_STATUS_3) << 24;
+
+	tvout_dbg("status = 0x%x!\n", status);
+
+	return status;
+}
+
+void s5p_clr_pending_tx(void)
+{
+	writeb(S5P_CES_IRQ_TX_DONE | S5P_CES_IRQ_TX_ERROR,
+					cec_base + S5P_CES_IRQ_CLEAR);
+}
+
+void s5p_clr_pending_rx(void)
+{
+	writeb(S5P_CES_IRQ_RX_DONE | S5P_CES_IRQ_RX_ERROR,
+					cec_base + S5P_CES_IRQ_CLEAR);
+}
+
+void s5p_cec_get_rx_buf(u32 size, u8 *buffer)
+{
+	u32 i = 0;
+
+	while (i < size) {
+		buffer[i] = readb(cec_base + S5P_CES_RX_BUFF0 + (i * 4));
+		i++;
+	}
+}
+
+int __init s5p_cec_mem_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	size_t	size;
+	int	ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (res == NULL) {
+		dev_err(&pdev->dev,
+			"failed to get memory region resource for cec\n");
+		return -ENOENT;
+	}
+
+	size = (res->end - res->start) + 1;
+	cec_mem = request_mem_region(res->start, size, pdev->name);
+
+	if (cec_mem == NULL) {
+		dev_err(&pdev->dev,
+			"failed to get memory region for cec\n");
+		return -ENOENT;
+	}
+
+	cec_base = ioremap(res->start, size);
+
+	if (cec_base == NULL) {
+		dev_err(&pdev->dev,
+			"failed to ioremap address region for cec\n");
+		return -ENOENT;
+	}
+
+	return ret;
+}
+
+int __init s5p_cec_mem_release(struct platform_device *pdev)
+{
+	iounmap(cec_base);
+
+	if (cec_mem != NULL) {
+		if (release_resource(cec_mem))
+			dev_err(&pdev->dev,
+				"Can't remove tvout drv !!\n");
+
+		kfree(cec_mem);
+
+		cec_mem = NULL;
+	}
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/tvout/hw_if/hdcp.c b/drivers/media/video/samsung/tvout/hw_if/hdcp.c
new file mode 100644
index 0000000..569de28
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/hdcp.c
@@ -0,0 +1,1123 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/hdcp.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * HDCP function for Samsung TVOUT driver
+ *
+ * This program is free software. you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <mach/regs-hdmi.h>
+
+#include "hw_if.h"
+#include "../s5p_tvout_common_lib.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_TVOUT_DEBUG
+#define tvout_dbg(fmt, ...)						\
+do {									\
+	if (unlikely(tvout_dbg_flag & (1 << DBG_FLAG_HDCP))) {		\
+		printk(KERN_INFO "\t\t[HDCP] %s(): " fmt,		\
+			__func__, ##__VA_ARGS__);			\
+	}								\
+} while (0)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+#define AN_SZ			8
+#define AKSV_SZ			5
+#define BKSV_SZ			5
+#define MAX_KEY_SZ		16
+
+#define BKSV_RETRY_CNT		14
+#define BKSV_DELAY		100
+
+#define DDC_RETRY_CNT		400000
+#define DDC_DELAY		25
+
+#define KEY_LOAD_RETRY_CNT	1000
+#define ENCRYPT_CHECK_CNT	10
+
+#define KSV_FIFO_RETRY_CNT	50
+#define KSV_FIFO_CHK_DELAY	100 /* ms */
+#define KSV_LIST_RETRY_CNT	10000
+#define SHA_1_RETRY_CNT		4
+
+#define BCAPS_SIZE		1
+#define BSTATUS_SIZE		2
+#define SHA_1_HASH_SIZE		20
+#define HDCP_MAX_DEVS		128
+#define HDCP_KSV_SIZE		5
+
+#define HDCP_Bksv		0x00
+#define HDCP_Ri			0x08
+#define HDCP_Aksv		0x10
+#define HDCP_Ainfo		0x15
+#define HDCP_An			0x18
+#define HDCP_SHA1		0x20
+#define HDCP_Bcaps		0x40
+#define HDCP_BStatus		0x41
+#define HDCP_KSVFIFO		0x43
+
+#define KSV_FIFO_READY			(0x1 << 5)
+
+#define MAX_CASCADE_EXCEEDED_ERROR	(-2)
+#define MAX_DEVS_EXCEEDED_ERROR		(-3)
+#define REPEATER_ILLEGAL_DEVICE_ERROR	(-4)
+#define REPEATER_TIMEOUT_ERROR		(-5)
+
+#define MAX_CASCADE_EXCEEDED		(0x1 << 3)
+#define MAX_DEVS_EXCEEDED		(0x1 << 7)
+
+
+#define DDC_BUF_SIZE		32
+
+enum hdcp_event {
+	HDCP_EVENT_STOP			= 1 << 0,
+	HDCP_EVENT_START		= 1 << 1,
+	HDCP_EVENT_READ_BKSV_START	= 1 << 2,
+	HDCP_EVENT_WRITE_AKSV_START	= 1 << 4,
+	HDCP_EVENT_CHECK_RI_START	= 1 << 8,
+	HDCP_EVENT_SECOND_AUTH_START	= 1 << 16
+};
+
+enum hdcp_state {
+	NOT_AUTHENTICATED,
+	RECEIVER_READ_READY,
+	BCAPS_READ_DONE,
+	BKSV_READ_DONE,
+	AN_WRITE_DONE,
+	AKSV_WRITE_DONE,
+	FIRST_AUTHENTICATION_DONE,
+	SECOND_AUTHENTICATION_RDY,
+	SECOND_AUTHENTICATION_DONE,
+};
+
+struct s5p_hdcp_info {
+	u8			is_repeater;
+	u32			hdcp_enable;
+
+	spinlock_t		reset_lock;
+
+	enum hdcp_event		event;
+	enum hdcp_state		auth_status;
+
+	struct work_struct	work;
+};
+
+struct i2c_client *ddc_port;
+
+static bool sw_reset;
+extern bool s5p_hdmi_ctrl_status(void);
+
+static struct s5p_hdcp_info hdcp_info = {
+	.is_repeater	= false,
+	.hdcp_enable	= false,
+	.event		= HDCP_EVENT_STOP,
+	.auth_status	= NOT_AUTHENTICATED,
+};
+
+static struct workqueue_struct *hdcp_wq;
+
+/* start: external functions for HDMI */
+extern void __iomem *hdmi_base;
+
+
+/* end: external functions for HDMI */
+
+/* ddc i2c */
+static int s5p_ddc_read(u8 reg, int bytes, u8 *dest)
+{
+	struct i2c_client *i2c = ddc_port;
+	u8 addr = reg;
+	int ret, cnt = 0;
+
+	struct i2c_msg msg[] = {
+		[0] = {
+			.addr = i2c->addr,
+			.flags = 0,
+			.len = 1,
+			.buf = &addr
+		},
+		[1] = {
+			.addr = i2c->addr,
+			.flags = I2C_M_RD,
+			.len = bytes,
+			.buf = dest
+		}
+	};
+
+	do {
+		if (s5p_hdmi_ctrl_status() == false ||
+		    !s5p_hdmi_reg_get_hpd_status() ||
+		    on_stop_process)
+			goto ddc_read_err;
+
+		ret = i2c_transfer(i2c->adapter, msg, 2);
+
+		if (ret < 0 || ret != 2)
+			tvout_dbg("ddc : can't read data, retry %d\n", cnt);
+		else
+			break;
+
+		if (hdcp_info.auth_status == FIRST_AUTHENTICATION_DONE
+			|| hdcp_info.auth_status == SECOND_AUTHENTICATION_DONE)
+			goto ddc_read_err;
+
+		msleep(DDC_DELAY);
+		cnt++;
+	} while (cnt < DDC_RETRY_CNT);
+
+	if (cnt == DDC_RETRY_CNT)
+		goto ddc_read_err;
+
+	tvout_dbg("ddc : read data ok\n");
+
+	return 0;
+ddc_read_err:
+	tvout_err("ddc : can't read data, timeout\n");
+	return -1;
+}
+
+static int s5p_ddc_write(u8 reg, int bytes, u8 *src)
+{
+	struct i2c_client *i2c = ddc_port;
+	u8 msg[bytes + 1];
+	int ret, cnt = 0;
+
+	msg[0] = reg;
+	memcpy(&msg[1], src, bytes);
+
+	do {
+		if (s5p_hdmi_ctrl_status() == false ||
+		    !s5p_hdmi_reg_get_hpd_status() ||
+		    on_stop_process)
+			goto ddc_write_err;
+
+		ret = i2c_master_send(i2c, msg, bytes + 1);
+
+		if (ret < 0 || ret < bytes + 1)
+			tvout_dbg("ddc : can't write data, retry %d\n", cnt);
+		else
+			break;
+
+		msleep(DDC_DELAY);
+		cnt++;
+	} while (cnt < DDC_RETRY_CNT);
+
+	if (cnt == DDC_RETRY_CNT)
+		goto ddc_write_err;
+
+	tvout_dbg("ddc : write data ok\n");
+	return 0;
+ddc_write_err:
+	tvout_err("ddc : can't write data, timeout\n");
+	return -1;
+}
+
+static ssize_t sysfs_hdcp_ddc_i2c_num_show(struct class *class,
+		struct class_attribute *attr, char *buf)
+{
+	int size;
+	int ddc_i2c_num = ddc_port->adapter->nr;
+
+	pr_info("%s() ddc_i2c_num : %d\n",
+			__func__, ddc_i2c_num);
+	size = sprintf(buf, "DDC %d\n", ddc_i2c_num);
+
+	return size;
+}
+
+static CLASS_ATTR(ddc_i2c_num, 0664 , sysfs_hdcp_ddc_i2c_num_show, NULL);
+
+static int __devinit s5p_ddc_probe(struct i2c_client *client,
+			const struct i2c_device_id *dev_id)
+{
+	int ret = 0;
+	struct class *sec_hdcp;
+
+	ddc_port = client;
+
+	sec_hdcp = class_create(THIS_MODULE, "hdcp");
+	if (IS_ERR(sec_hdcp)) {
+		pr_err("Failed to create class(sec_hdcp)!\n");
+		ret = -ENOMEM;
+		goto err_exit1;
+	}
+
+	ret = class_create_file(sec_hdcp, &class_attr_ddc_i2c_num);
+	if (ret) {
+		pr_err("Failed to create device file in sysfs entries!\n");
+		ret = -ENOMEM;
+		goto err_exit2;
+	}
+
+	dev_info(&client->adapter->dev, "attached s5p_ddc "
+		"into i2c adapter successfully\n");
+	return ret;
+
+err_exit2:
+	class_destroy(sec_hdcp);
+
+err_exit1:
+	return ret;
+}
+
+static int s5p_ddc_remove(struct i2c_client *client)
+{
+	dev_info(&client->adapter->dev, "detached s5p_ddc "
+		"from i2c adapter successfully\n");
+
+	return 0;
+}
+
+static int s5p_ddc_suspend(struct i2c_client *cl, pm_message_t mesg)
+{
+	return 0;
+};
+
+static int s5p_ddc_resume(struct i2c_client *cl)
+{
+	return 0;
+};
+
+static struct i2c_device_id ddc_idtable[] = {
+	{"s5p_ddc", 0},
+};
+MODULE_DEVICE_TABLE(i2c, ddc_idtable);
+
+static struct i2c_driver ddc_driver = {
+	.driver = {
+		.name = "s5p_ddc",
+		.owner = THIS_MODULE,
+	},
+	.id_table	= ddc_idtable,
+	.probe		= s5p_ddc_probe,
+	.remove		= __devexit_p(s5p_ddc_remove),
+	.suspend	= s5p_ddc_suspend,
+	.resume		= s5p_ddc_resume,
+};
+
+static int __init s5p_ddc_init(void)
+{
+	return i2c_add_driver(&ddc_driver);
+}
+
+static void __exit s5p_ddc_exit(void)
+{
+	i2c_del_driver(&ddc_driver);
+}
+
+
+module_init(s5p_ddc_init);
+module_exit(s5p_ddc_exit);
+
+/* hdcp */
+static int s5p_hdcp_encryption(bool on)
+{
+	u8 reg;
+	if (on)
+		reg = S5P_HDMI_HDCP_ENC_ENABLE;
+	else
+		reg = S5P_HDMI_HDCP_ENC_DISABLE;
+
+	writeb(reg, hdmi_base + S5P_HDMI_ENC_EN);
+	s5p_hdmi_reg_mute(!on);
+
+	return 0;
+}
+
+static int s5p_hdcp_write_key(int sz, int reg, int type)
+{
+	u8 buff[MAX_KEY_SZ] = {0,};
+	int cnt = 0, zero = 0;
+
+	hdmi_read_l(buff, hdmi_base, reg, sz);
+
+	for (cnt = 0; cnt < sz; cnt++)
+		if (buff[cnt] == 0)
+			zero++;
+
+	if (zero == sz) {
+		tvout_dbg("%s : null\n", type == HDCP_An ? "an" : "aksv");
+		goto write_key_err;
+	}
+
+	if (s5p_ddc_write(type, sz, buff) < 0)
+		goto write_key_err;
+
+#ifdef CONFIG_HDCP_DEBUG
+	{
+		u16 i = 0;
+
+		for (i = 1; i < sz + 1; i++)
+			tvout_dbg("%s[%d] : 0x%02x\n",
+				type == HDCP_An ? "an" : "aksv", i, buff[i]);
+	}
+#endif
+
+	return 0;
+write_key_err:
+	tvout_err("write %s : failed\n", type == HDCP_An ? "an" : "aksv");
+	return -1;
+}
+
+static int s5p_hdcp_read_bcaps(void)
+{
+	u8 bcaps = 0;
+
+	if (s5p_ddc_read(HDCP_Bcaps, BCAPS_SIZE, &bcaps) < 0)
+		goto bcaps_read_err;
+
+	if (s5p_hdmi_ctrl_status() == false || !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		goto bcaps_read_err;
+
+	writeb(bcaps, hdmi_base + S5P_HDMI_HDCP_BCAPS);
+
+	if (bcaps & S5P_HDMI_HDCP_BCAPS_REPEATER)
+		hdcp_info.is_repeater = 1;
+	else
+		hdcp_info.is_repeater = 0;
+
+	tvout_dbg("device : %s\n", hdcp_info.is_repeater ? "REPEAT" : "SINK");
+	tvout_dbg("[i2c] bcaps : 0x%02x\n", bcaps);
+	tvout_dbg("[sfr] bcaps : 0x%02x\n",
+		readb(hdmi_base + S5P_HDMI_HDCP_BCAPS));
+
+	return 0;
+
+bcaps_read_err:
+	tvout_err("can't read bcaps : timeout\n");
+	return -1;
+}
+
+static int s5p_hdcp_read_bksv(void)
+{
+	u8 bksv[BKSV_SZ] = {0, };
+	int i = 0, j = 0;
+	u32 one = 0, zero = 0, res = 0;
+	u32 cnt = 0;
+
+	do {
+		if (s5p_ddc_read(HDCP_Bksv, BKSV_SZ, bksv) < 0)
+			goto bksv_read_err;
+
+#ifdef CONFIG_HDCP_DEBUG
+		for (i = 0; i < BKSV_SZ; i++)
+			tvout_dbg("i2c read : bksv[%d]: 0x%x\n", i, bksv[i]);
+#endif
+
+		for (i = 0; i < BKSV_SZ; i++) {
+
+			for (j = 0; j < 8; j++) {
+				res = bksv[i] & (0x1 << j);
+
+				if (res == 0)
+					zero++;
+				else
+					one++;
+			}
+
+		}
+
+		if (s5p_hdmi_ctrl_status() == false ||
+		    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+			goto bksv_read_err;
+
+		if ((zero == 20) && (one == 20)) {
+			hdmi_write_l(bksv, hdmi_base,
+				S5P_HDMI_HDCP_BKSV_0_0, BKSV_SZ);
+			break;
+		}
+		tvout_dbg("invalid bksv, retry : %d\n", cnt);
+
+		msleep(BKSV_DELAY);
+		cnt++;
+	} while (cnt < BKSV_RETRY_CNT);
+
+	if (cnt == BKSV_RETRY_CNT)
+		goto bksv_read_err;
+
+	tvout_dbg("bksv read OK, retry : %d\n", cnt);
+	return 0;
+
+bksv_read_err:
+	tvout_err("can't read bksv : timeout\n");
+	return -1;
+}
+
+static int s5p_hdcp_read_ri(void)
+{
+	static unsigned long int cnt;
+	u8 ri[2] = {0, 0};
+	u8 rj[2] = {0, 0};
+
+	cnt++;
+	ri[0] = readb(hdmi_base + S5P_HDMI_HDCP_Ri_0);
+	ri[1] = readb(hdmi_base + S5P_HDMI_HDCP_Ri_1);
+
+	if (s5p_ddc_read(HDCP_Ri, 2, rj) < 0)
+		goto compare_err;
+
+	tvout_dbg("Rx(ddc) -> rj[0]: 0x%02x, rj[1]: 0x%02x\n",
+		rj[0], rj[1]);
+	tvout_dbg("Tx(register) -> ri[0]: 0x%02x, ri[1]: 0x%02x\n",
+		ri[0], ri[1]);
+
+	if ((ri[0] == rj[0]) && (ri[1] == rj[1]) && (ri[0] | ri[1]))
+		writeb(S5P_HDMI_HDCP_Ri_MATCH_RESULT_Y,
+			hdmi_base + S5P_HDMI_HDCP_CHECK_RESULT);
+	else {
+		writeb(S5P_HDMI_HDCP_Ri_MATCH_RESULT_N,
+			hdmi_base + S5P_HDMI_HDCP_CHECK_RESULT);
+		goto compare_err;
+	}
+
+	ri[0] = 0;
+	ri[1] = 0;
+	rj[0] = 0;
+	rj[1] = 0;
+
+	tvout_dbg("ri, ri' : matched\n");
+
+	return 0;
+compare_err:
+	hdcp_info.event		= HDCP_EVENT_STOP;
+	hdcp_info.auth_status	= NOT_AUTHENTICATED;
+	tvout_err("read ri : failed - missmatch "
+			"Rx(ddc) rj[0]:0x%02x, rj[1]:0x%02x "
+			"Tx(register) ri[0]:0x%02x, ri[1]:0x%02x "
+			"cnt = %lu\n",
+			rj[0], rj[1], ri[0], ri[1], cnt);
+	msleep(10);
+	return -1;
+}
+
+static void s5p_hdcp_reset_sw(void)
+{
+	u8 reg;
+
+	sw_reset = true;
+	reg = s5p_hdmi_reg_intc_get_enabled();
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 0);
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 0);
+
+	s5p_hdmi_reg_sw_hpd_enable(true);
+	s5p_hdmi_reg_set_hpd_onoff(false);
+	s5p_hdmi_reg_set_hpd_onoff(true);
+	s5p_hdmi_reg_sw_hpd_enable(false);
+
+	if (reg & 1<<HDMI_IRQ_HPD_PLUG)
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 1);
+	if (reg & 1<<HDMI_IRQ_HPD_UNPLUG)
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 1);
+
+	sw_reset = false;
+}
+
+static void s5p_hdcp_reset_auth(void)
+{
+	u8 reg;
+	unsigned long spin_flags;
+
+	if (s5p_hdmi_ctrl_status() == false ||
+            !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		return;
+	spin_lock_irqsave(&hdcp_info.reset_lock, spin_flags);
+
+	hdcp_info.event		= HDCP_EVENT_STOP;
+	hdcp_info.auth_status	= NOT_AUTHENTICATED;
+
+	writeb(0x0, hdmi_base + S5P_HDMI_HDCP_CTRL1);
+	writeb(0x0, hdmi_base + S5P_HDMI_HDCP_CTRL2);
+	s5p_hdmi_reg_mute(true);
+
+	s5p_hdcp_encryption(false);
+
+	tvout_err("reset authentication\n");
+
+	reg = readb(hdmi_base + S5P_HDMI_STATUS_EN);
+	reg &= S5P_HDMI_INT_DIS_ALL;
+	writeb(reg, hdmi_base + S5P_HDMI_STATUS_EN);
+
+	writeb(S5P_HDMI_HDCP_CLR_ALL_RESULTS,
+				hdmi_base + S5P_HDMI_HDCP_CHECK_RESULT);
+
+	/* need some delay (at least 1 frame) */
+	mdelay(16);
+
+	s5p_hdcp_reset_sw();
+
+	reg = readb(hdmi_base + S5P_HDMI_STATUS_EN);
+	reg |= S5P_HDMI_WTFORACTIVERX_INT_OCC |
+		S5P_HDMI_WATCHDOG_INT_OCC |
+		S5P_HDMI_WRITE_INT_OCC |
+		S5P_HDMI_UPDATE_RI_INT_OCC;
+	writeb(reg, hdmi_base + S5P_HDMI_STATUS_EN);
+	writeb(S5P_HDMI_HDCP_CP_DESIRED_EN, hdmi_base + S5P_HDMI_HDCP_CTRL1);
+	spin_unlock_irqrestore(&hdcp_info.reset_lock, spin_flags);
+}
+
+static int s5p_hdcp_loadkey(void)
+{
+	u8 reg;
+	int cnt = 0;
+
+	writeb(S5P_HDMI_EFUSE_CTRL_HDCP_KEY_READ,
+				hdmi_base + S5P_HDMI_EFUSE_CTRL);
+
+	do {
+		reg = readb(hdmi_base + S5P_HDMI_EFUSE_STATUS);
+		if (reg & S5P_HDMI_EFUSE_ECC_DONE)
+			break;
+		cnt++;
+		mdelay(1);
+	} while (cnt < KEY_LOAD_RETRY_CNT);
+
+	if (cnt == KEY_LOAD_RETRY_CNT)
+		goto key_load_err;
+
+	reg = readb(hdmi_base + S5P_HDMI_EFUSE_STATUS);
+
+	if (reg & S5P_HDMI_EFUSE_ECC_FAIL)
+		goto key_load_err;
+
+	tvout_dbg("load key : OK\n");
+	return 0;
+key_load_err:
+	tvout_err("can't load key\n");
+	return -1;
+}
+
+static int s5p_hdmi_start_encryption(void)
+{
+	u8 reg;
+	u32 cnt = 0;
+
+	do {
+		reg = readb(hdmi_base + S5P_HDMI_SYS_STATUS);
+
+		if (reg & S5P_HDMI_AUTHEN_ACK_AUTH) {
+			s5p_hdcp_encryption(true);
+			break;
+		}
+
+		mdelay(1);
+
+		cnt++;
+	} while (cnt < ENCRYPT_CHECK_CNT);
+
+	if (cnt == ENCRYPT_CHECK_CNT)
+		goto encrypt_err;
+
+
+	tvout_dbg("encrypt : start\n");
+	return 0;
+
+encrypt_err:
+	s5p_hdcp_encryption(false);
+	tvout_err("encrypt : failed\n");
+	return -1;
+}
+
+static int s5p_hdmi_check_repeater(void)
+{
+	int reg = 0;
+	int cnt = 0, cnt2 = 0;
+
+	u8 bcaps = 0;
+	u8 status[BSTATUS_SIZE] = {0, 0};
+	u8 rx_v[SHA_1_HASH_SIZE] = {0};
+	u8 ksv_list[HDCP_MAX_DEVS * HDCP_KSV_SIZE] = {0};
+
+	u32 dev_cnt;
+
+	memset(rx_v, 0x0, SHA_1_HASH_SIZE);
+	memset(ksv_list, 0x0, HDCP_MAX_DEVS * HDCP_KSV_SIZE);
+
+	do {
+		if (s5p_hdcp_read_bcaps() < 0)
+			goto check_repeater_err;
+
+		bcaps = readb(hdmi_base + S5P_HDMI_HDCP_BCAPS);
+
+		if (bcaps & KSV_FIFO_READY)
+			break;
+
+		msleep(KSV_FIFO_CHK_DELAY);
+
+		cnt++;
+	} while (cnt < KSV_FIFO_RETRY_CNT);
+
+	if (cnt == KSV_FIFO_RETRY_CNT) {
+		tvout_dbg("repeater : ksv fifo not ready, timeout error");
+		tvout_dbg(", retries : %d\n", cnt);
+		return REPEATER_TIMEOUT_ERROR;
+	}
+
+	tvout_dbg("repeater : ksv fifo ready\n");
+	tvout_dbg(", retries : %d\n", cnt);
+
+
+	if (s5p_ddc_read(HDCP_BStatus, BSTATUS_SIZE, status) < 0)
+		goto check_repeater_err;
+
+	if (status[1] & MAX_CASCADE_EXCEEDED)
+		return MAX_CASCADE_EXCEEDED_ERROR;
+	else if (status[0] & MAX_DEVS_EXCEEDED)
+		return MAX_DEVS_EXCEEDED_ERROR;
+
+	writeb(status[0], hdmi_base + S5P_HDMI_HDCP_BSTATUS_0);
+	writeb(status[1], hdmi_base + S5P_HDMI_HDCP_BSTATUS_1);
+
+	tvout_dbg("status[0] :0x%02x\n", status[0]);
+	tvout_dbg("status[1] :0x%02x\n", status[1]);
+
+	dev_cnt = status[0] & 0x7f;
+
+	tvout_dbg("repeater : dev cnt = %d\n", dev_cnt);
+
+	if (dev_cnt) {
+
+		if (s5p_ddc_read(HDCP_KSVFIFO, dev_cnt * HDCP_KSV_SIZE,
+				ksv_list) < 0)
+			goto check_repeater_err;
+
+		cnt = 0;
+
+		do {
+			hdmi_write_l(&ksv_list[cnt*5], hdmi_base,
+				S5P_HDMI_HDCP_RX_KSV_0_0, HDCP_KSV_SIZE);
+
+			reg = S5P_HDMI_HDCP_KSV_WRITE_DONE;
+
+			if (cnt == dev_cnt - 1)
+				reg |= S5P_HDMI_HDCP_KSV_END;
+
+			writeb(reg, hdmi_base + S5P_HDMI_HDCP_KSV_LIST_CON);
+
+			if (cnt < dev_cnt - 1) {
+				cnt2 = 0;
+				do {
+					reg = readb(hdmi_base
+						+ S5P_HDMI_HDCP_KSV_LIST_CON);
+
+					if (reg & S5P_HDMI_HDCP_KSV_READ)
+						break;
+					cnt2++;
+				} while (cnt2 < KSV_LIST_RETRY_CNT);
+
+				if (cnt2 == KSV_LIST_RETRY_CNT)
+					tvout_dbg("ksv list not readed\n");
+			}
+			cnt++;
+		} while (cnt < dev_cnt);
+	} else {
+		writeb(S5P_HDMI_HDCP_KSV_LIST_EMPTY,
+			hdmi_base + S5P_HDMI_HDCP_KSV_LIST_CON);
+	}
+
+	if (s5p_ddc_read(HDCP_SHA1, SHA_1_HASH_SIZE, rx_v) < 0)
+		goto check_repeater_err;
+
+#ifdef S5P_HDCP_DEBUG
+	for (i = 0; i < SHA_1_HASH_SIZE; i++)
+		tvout_dbg("[i2c] SHA-1 rx :: %02x\n", rx_v[i]);
+#endif
+
+	hdmi_write_l(rx_v, hdmi_base, S5P_HDMI_HDCP_RX_SHA1_0_0,
+		SHA_1_HASH_SIZE);
+
+	reg = readb(hdmi_base + S5P_HDMI_HDCP_SHA_RESULT);
+	if (reg & S5P_HDMI_HDCP_SHA_VALID_RD) {
+		if (reg & S5P_HDMI_HDCP_SHA_VALID) {
+			tvout_dbg("SHA-1 result : OK\n");
+			writeb(0x0, hdmi_base + S5P_HDMI_HDCP_SHA_RESULT);
+		} else {
+			tvout_dbg("SHA-1 result : not vaild\n");
+			writeb(0x0, hdmi_base + S5P_HDMI_HDCP_SHA_RESULT);
+			goto check_repeater_err;
+		}
+	} else {
+		tvout_dbg("SHA-1 result : not ready\n");
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_SHA_RESULT);
+		goto check_repeater_err;
+	}
+
+	tvout_dbg("check repeater : OK\n");
+	return 0;
+check_repeater_err:
+	tvout_err("check repeater : failed\n");
+	return -1;
+}
+
+int s5p_hdcp_stop(void)
+{
+	u32  sfr_val = 0;
+
+	tvout_dbg("HDCP ftn. Stop!!\n");
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HDCP, 0);
+
+	hdcp_info.event		= HDCP_EVENT_STOP;
+	hdcp_info.auth_status	= NOT_AUTHENTICATED;
+	hdcp_info.hdcp_enable	= false;
+
+	writeb(0x0, hdmi_base + S5P_HDMI_HDCP_CTRL1);
+
+	s5p_hdmi_reg_sw_hpd_enable(false);
+
+	sfr_val = readb(hdmi_base + S5P_HDMI_STATUS_EN);
+	sfr_val &= S5P_HDMI_INT_DIS_ALL;
+	writeb(sfr_val, hdmi_base + S5P_HDMI_STATUS_EN);
+
+	sfr_val = readb(hdmi_base + S5P_HDMI_SYS_STATUS);
+	sfr_val |= S5P_HDMI_INT_EN_ALL;
+	writeb(sfr_val, hdmi_base + S5P_HDMI_SYS_STATUS);
+
+	tvout_dbg("Stop Encryption by Stop!!\n");
+	s5p_hdcp_encryption(false);
+
+	writeb(S5P_HDMI_HDCP_Ri_MATCH_RESULT_N,
+			hdmi_base + S5P_HDMI_HDCP_CHECK_RESULT);
+	writeb(S5P_HDMI_HDCP_CLR_ALL_RESULTS,
+			hdmi_base + S5P_HDMI_HDCP_CHECK_RESULT);
+
+	return 0;
+}
+
+int s5p_hdcp_start(void)
+{
+	u32  sfr_val;
+
+	hdcp_info.event		= HDCP_EVENT_STOP;
+	hdcp_info.auth_status	= NOT_AUTHENTICATED;
+
+	tvout_dbg("HDCP ftn. Start\n");
+
+	s5p_hdcp_reset_sw();
+
+	tvout_dbg("Stop Encryption by Start\n");
+
+	s5p_hdcp_encryption(false);
+
+	msleep(120);
+	if (s5p_hdcp_loadkey() < 0)
+		return -1;
+
+	writeb(S5P_HDMI_GCP_CON_NO_TRAN, hdmi_base + S5P_HDMI_GCP_CON);
+	writeb(S5P_HDMI_INT_EN_ALL, hdmi_base + S5P_HDMI_STATUS_EN);
+
+	sfr_val = S5P_HDMI_HDCP_CP_DESIRED_EN;
+	writeb(sfr_val, hdmi_base + S5P_HDMI_HDCP_CTRL1);
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HDCP, 1);
+
+	hdcp_info.hdcp_enable = 1;
+
+	return 0;
+}
+
+static int s5p_hdcp_bksv(void)
+{
+	tvout_dbg("bksv start : start\n");
+
+	hdcp_info.auth_status = RECEIVER_READ_READY;
+
+	msleep(100);
+
+	if (s5p_hdcp_read_bcaps() < 0)
+		goto bksv_start_err;
+
+	hdcp_info.auth_status = BCAPS_READ_DONE;
+
+	if (s5p_hdcp_read_bksv() < 0)
+		goto bksv_start_err;
+
+	hdcp_info.auth_status = BKSV_READ_DONE;
+
+	tvout_dbg("bksv start : OK\n");
+
+	return 0;
+
+bksv_start_err:
+	tvout_err("bksv start : failed\n");
+	msleep(100);
+	return -1;
+}
+
+static int s5p_hdcp_second_auth(void)
+{
+	int ret = 0;
+
+	tvout_dbg("second auth : start\n");
+
+	if (!hdcp_info.hdcp_enable)
+		goto second_auth_err;
+
+	if (s5p_hdmi_ctrl_status() == false ||
+	    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		goto second_auth_err;
+
+	ret = s5p_hdmi_check_repeater();
+	if (ret)
+		goto second_auth_err;
+
+	hdcp_info.auth_status = SECOND_AUTHENTICATION_DONE;
+	s5p_hdmi_start_encryption();
+
+	tvout_dbg("second auth : OK\n");
+	return 0;
+
+second_auth_err:
+	hdcp_info.auth_status = NOT_AUTHENTICATED;
+	tvout_err("second auth : failed\n");
+	return -1;
+}
+
+static int s5p_hdcp_write_aksv(void)
+{
+	tvout_dbg("aksv start : start\n");
+
+	if (hdcp_info.auth_status != BKSV_READ_DONE) {
+		tvout_dbg("aksv start : bksv is not ready\n");
+		goto aksv_write_err;
+	}
+	if (s5p_hdmi_ctrl_status() == false ||
+	    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		goto aksv_write_err;
+
+	if (s5p_hdcp_write_key(AN_SZ, S5P_HDMI_HDCP_An_0_0, HDCP_An) < 0)
+		goto aksv_write_err;
+
+	hdcp_info.auth_status = AN_WRITE_DONE;
+
+	tvout_dbg("write an : done\n");
+
+	if (s5p_hdcp_write_key(AKSV_SZ, S5P_HDMI_HDCP_AKSV_0_0, HDCP_Aksv) < 0)
+		goto aksv_write_err;
+
+	msleep(100);
+
+	hdcp_info.auth_status = AKSV_WRITE_DONE;
+
+	tvout_dbg("write aksv : done\n");
+	tvout_dbg("aksv start : OK\n");
+	return 0;
+
+aksv_write_err:
+	tvout_err("aksv start : failed\n");
+	return -1;
+}
+
+static int s5p_hdcp_check_ri(void)
+{
+	tvout_dbg("ri check : start\n");
+
+	if (hdcp_info.auth_status < AKSV_WRITE_DONE) {
+		tvout_dbg("ri check : not ready\n");
+		goto check_ri_err;
+	}
+
+	if (s5p_hdmi_ctrl_status() == false ||
+	    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		goto check_ri_err;
+
+	if (s5p_hdcp_read_ri() < 0)
+		goto check_ri_err;
+
+	if (hdcp_info.is_repeater)
+		hdcp_info.auth_status
+			= SECOND_AUTHENTICATION_RDY;
+	else {
+		hdcp_info.auth_status
+			= FIRST_AUTHENTICATION_DONE;
+		s5p_hdmi_start_encryption();
+	}
+
+	tvout_dbg("ri check : OK\n");
+	return 0;
+
+check_ri_err:
+	tvout_err("ri check : failed\n");
+	return -1;
+}
+
+static void s5p_hdcp_work(void *arg)
+{
+	if (!hdcp_info.hdcp_enable || s5p_hdmi_ctrl_status() == false ||
+	    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)
+		return;
+
+	if (hdcp_info.event & HDCP_EVENT_READ_BKSV_START) {
+		if (s5p_hdcp_bksv() < 0)
+			goto work_err;
+		else
+			hdcp_info.event &= ~HDCP_EVENT_READ_BKSV_START;
+	}
+
+	if (hdcp_info.event & HDCP_EVENT_SECOND_AUTH_START) {
+		if (s5p_hdcp_second_auth() < 0)
+			goto work_err;
+		else
+			hdcp_info.event &= ~HDCP_EVENT_SECOND_AUTH_START;
+	}
+
+	if (hdcp_info.event & HDCP_EVENT_WRITE_AKSV_START) {
+		if (s5p_hdcp_write_aksv() < 0)
+			goto work_err;
+		else
+			hdcp_info.event  &= ~HDCP_EVENT_WRITE_AKSV_START;
+	}
+
+	if (hdcp_info.event & HDCP_EVENT_CHECK_RI_START) {
+		if (s5p_hdcp_check_ri() < 0)
+			goto work_err;
+		else
+			hdcp_info.event &= ~HDCP_EVENT_CHECK_RI_START;
+	}
+	return;
+work_err:
+	if (!hdcp_info.hdcp_enable || s5p_hdmi_ctrl_status() == false ||
+	    !s5p_hdmi_reg_get_hpd_status() || on_stop_process)	{
+		return;
+	}
+	s5p_hdcp_reset_auth();
+}
+
+irqreturn_t s5p_hdcp_irq_handler(int irq, void *dev_id)
+{
+	u32 event = 0;
+	u8 flag;
+
+	event = 0;
+
+	if (s5p_hdmi_ctrl_status() == false) {
+		hdcp_info.event		= HDCP_EVENT_STOP;
+		hdcp_info.auth_status	= NOT_AUTHENTICATED;
+		tvout_dbg("[WARNING] s5p_hdmi_ctrl_status fail\n");
+		return IRQ_HANDLED;
+	}
+
+	flag = readb(hdmi_base + S5P_HDMI_SYS_STATUS);
+	tvout_dbg("flag = 0x%x\n", flag);
+
+	if (flag & S5P_HDMI_WTFORACTIVERX_INT_OCC) {
+		event |= HDCP_EVENT_READ_BKSV_START;
+		writeb(flag | S5P_HDMI_WTFORACTIVERX_INT_OCC,
+			 hdmi_base + S5P_HDMI_SYS_STATUS);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_I2C_INT);
+	}
+
+	if (flag & S5P_HDMI_WRITE_INT_OCC) {
+		event |= HDCP_EVENT_WRITE_AKSV_START;
+		writeb(flag | S5P_HDMI_WRITE_INT_OCC,
+			hdmi_base + S5P_HDMI_SYS_STATUS);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_AN_INT);
+	}
+
+	if (flag & S5P_HDMI_UPDATE_RI_INT_OCC) {
+		event |= HDCP_EVENT_CHECK_RI_START;
+		writeb(flag | S5P_HDMI_UPDATE_RI_INT_OCC,
+			hdmi_base + S5P_HDMI_SYS_STATUS);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_RI_INT);
+	}
+
+	if (flag & S5P_HDMI_WATCHDOG_INT_OCC) {
+		event |= HDCP_EVENT_SECOND_AUTH_START;
+		writeb(flag | S5P_HDMI_WATCHDOG_INT_OCC,
+			hdmi_base + S5P_HDMI_SYS_STATUS);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_WDT_INT);
+	}
+
+	if (!event) {
+		tvout_dbg("unknown irq\n");
+		return IRQ_HANDLED;
+	}
+
+	if (hdcp_info.hdcp_enable && s5p_hdmi_ctrl_status() == true &&
+	    s5p_hdmi_reg_get_hpd_status() && !on_stop_process) {
+		hdcp_info.event |= event;
+		queue_work_on(0, hdcp_wq, &hdcp_info.work);
+	} else {
+		hdcp_info.event		= HDCP_EVENT_STOP;
+		hdcp_info.auth_status	= NOT_AUTHENTICATED;
+	}
+
+	return IRQ_HANDLED;
+}
+
+int s5p_hdcp_init(void)
+{
+	hdcp_wq = create_freezable_workqueue("hdcp work");
+	if (!hdcp_wq)
+		return -1;
+	INIT_WORK(&hdcp_info.work, (work_func_t) s5p_hdcp_work);
+
+	spin_lock_init(&hdcp_info.reset_lock);
+
+	s5p_hdmi_reg_intc_set_isr(s5p_hdcp_irq_handler,
+					(u8) HDMI_IRQ_HDCP);
+
+	return 0;
+}
+
+int s5p_hdcp_encrypt_stop(bool on)
+{
+	u32 reg;
+	unsigned long spin_flags;
+
+	tvout_dbg("\n");
+	spin_lock_irqsave(&hdcp_info.reset_lock, spin_flags);
+
+
+	if (s5p_hdmi_ctrl_status() == false) {
+		hdcp_info.event	= HDCP_EVENT_STOP;
+		hdcp_info.auth_status = NOT_AUTHENTICATED;
+		spin_unlock_irqrestore(&hdcp_info.reset_lock, spin_flags);
+		return -1;
+	}
+
+	if (hdcp_info.hdcp_enable) {
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_I2C_INT);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_AN_INT);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_RI_INT);
+		writeb(0x0, hdmi_base + S5P_HDMI_HDCP_WDT_INT);
+
+		s5p_hdcp_encryption(false);
+
+		if (!sw_reset) {
+			reg = readb(hdmi_base + S5P_HDMI_HDCP_CTRL1);
+
+			if (on) {
+				writeb(reg | S5P_HDMI_HDCP_CP_DESIRED_EN,
+					hdmi_base + S5P_HDMI_HDCP_CTRL1);
+				s5p_hdmi_reg_intc_enable(HDMI_IRQ_HDCP, 1);
+			} else {
+				hdcp_info.event	= HDCP_EVENT_STOP;
+				hdcp_info.auth_status = NOT_AUTHENTICATED;
+
+				writeb(reg & ~S5P_HDMI_HDCP_CP_DESIRED_EN,
+					hdmi_base + S5P_HDMI_HDCP_CTRL1);
+				s5p_hdmi_reg_intc_enable(HDMI_IRQ_HDCP, 0);
+			}
+		}
+
+		tvout_dbg("stop encryption by HPD\n");
+	}
+
+	spin_unlock_irqrestore(&hdcp_info.reset_lock, spin_flags);
+
+	return 0;
+}
diff --git a/drivers/media/video/samsung/tvout/hw_if/hdmi.c b/drivers/media/video/samsung/tvout/hw_if/hdmi.c
new file mode 100644
index 0000000..dfb3152
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/hdmi.c
@@ -0,0 +1,2182 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/hdmi.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Functions for HDMI of Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <mach/map.h>
+#include <mach/regs-hdmi.h>
+#include <mach/regs-pmu.h>
+
+#include "../s5p_tvout_common_lib.h"
+#include "hw_if.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_TVOUT_DEBUG
+#define tvout_dbg(fmt, ...)						\
+do {									\
+	if (unlikely(tvout_dbg_flag & (1 << DBG_FLAG_HDMI))) {		\
+		printk(KERN_INFO "\t\t[HDMI] %s(): " fmt,		\
+			__func__, ##__VA_ARGS__);			\
+	}								\
+} while (0)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+
+/****************************************
+ * Definitions for HDMI_PHY
+ ***************************************/
+
+#define PHY_I2C_ADDRESS		0x70
+#define PHY_REG_MODE_SET_DONE	0x1F
+
+#define I2C_ACK			(1 << 7)
+#define I2C_INT			(1 << 5)
+#define I2C_PEND		(1 << 4)
+#define I2C_INT_CLEAR		(0 << 4)
+#define I2C_CLK			(0x41)
+#define I2C_CLK_PEND_INT	(I2C_CLK | I2C_INT_CLEAR | I2C_INT)
+#define I2C_ENABLE		(1 << 4)
+#define I2C_START		(1 << 5)
+#define I2C_MODE_MTX		0xC0
+#define I2C_MODE_MRX		0x80
+#define I2C_IDLE		0
+
+#define STATE_IDLE		0
+#define STATE_TX_EDDC_SEGADDR	1
+#define STATE_TX_EDDC_SEGNUM	2
+#define STATE_TX_DDC_ADDR	3
+#define STATE_TX_DDC_OFFSET	4
+#define STATE_RX_DDC_ADDR	5
+#define STATE_RX_DDC_DATA	6
+#define STATE_RX_ADDR		7
+#define STATE_RX_DATA		8
+#define STATE_TX_ADDR		9
+#define STATE_TX_DATA		10
+#define STATE_TX_STOP		11
+#define STATE_RX_STOP		12
+
+
+
+
+static struct {
+	s32	state;
+	u8	*buffer;
+	s32	bytes;
+} i2c_hdmi_phy_context;
+
+
+
+
+/****************************************
+ * Definitions for HDMI
+ ***************************************/
+#define HDMI_IRQ_TOTAL_NUM	6
+
+
+/* private data area */
+void __iomem	*hdmi_base;
+void __iomem	*i2c_hdmi_phy_base;
+
+irqreturn_t	(*s5p_hdmi_isr_ftn[HDMI_IRQ_TOTAL_NUM])(int irq, void *);
+spinlock_t	lock_hdmi;
+
+#ifdef	CONFIG_HDMI_PHY_32N
+static u8 phy_config[][3][32] = {
+	{/* freq = 25.200 MHz */
+		{
+		    0x01, 0x51, 0x2a, 0x75, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0x52, 0x69, 0x75, 0x57, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0x3b, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0x52, 0x3f, 0x35, 0x63, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0xbd, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xa3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 25.175 MHz */
+		{
+		    0x01, 0xd1, 0x1f, 0x50, 0x40, 0x20, 0x1e, 0x08,
+		    0x81, 0xa0, 0xbd, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x51, 0x15, 0x40, 0x2b, 0x08,
+		    0x81, 0xa0, 0xec, 0xd8, 0x45, 0xa0, 0x34, 0x80,
+		    0x08, 0x80, 0x32, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x1f, 0x30, 0x23, 0x20, 0x1e, 0x08,
+		    0x81, 0xa0, 0xbd, 0xd8, 0x45, 0xa0, 0x34, 0x80,
+		    0x08, 0x80, 0x32, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xa3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 27 MHz */
+		{
+		    0x01, 0x51, 0x2d, 0x75, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x38, 0x74, 0x57, 0x08, 0x04, 0x08,
+		    0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xb4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x22, 0x31, 0x63, 0x08, 0xfc, 0x08,
+		    0x86, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x98, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 27.027 MHz */
+		{
+		    0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
+		    0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x38, 0x74, 0x57, 0x50, 0x31, 0x01,
+		    0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xb6, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd4, 0x87, 0x31, 0x63, 0x64, 0x1b, 0x20,
+		    0x19, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x98, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 54 MHz */
+		{
+		    0x01, 0x51, 0x2d, 0x35, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xe4, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x38, 0x35, 0x53, 0x08, 0x04, 0x08,
+		    0x88, 0xa0, 0x52, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xb6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x22, 0x11, 0x61, 0x08, 0xfc, 0x08,
+		    0x86, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x98, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 54.054 MHz */
+		{
+		    0x01, 0xd1, 0x2d, 0x32, 0x40, 0x64, 0x12, 0x08,
+		    0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xe3, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd2, 0x70, 0x34, 0x53, 0x50, 0x31, 0x08,
+		    0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xb6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd4, 0x87, 0x11, 0x61, 0x64, 0x1b, 0x20,
+		    0x19, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x98, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 74.250 MHz */
+		{
+		    0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
+		    0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x11, 0x51, 0x40, 0xd6, 0x08,
+		    0x81, 0xa0, 0xe8, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x84, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x2e, 0x12, 0x61, 0x40, 0x34, 0x08,
+		    0x82, 0xa0, 0x16, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xb9, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 74.176 MHz */
+		{
+		    0x01, 0xd1, 0x1f, 0x10, 0x40, 0x5b, 0xef, 0x08,
+		    0x81, 0xa0, 0xb9, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x14, 0x51, 0x5b, 0xa7, 0x08,
+		    0x84, 0xa0, 0xe8, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x85, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd2, 0x5d, 0x12, 0x61, 0x5b, 0xcd, 0x10,
+		    0x43, 0xa0, 0x16, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xba, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 148.500 MHz  - Pre-emph + Higher Tx amp. */
+		{
+		    0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
+		    0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x01, 0x50, 0x40, 0xd6, 0x08,
+		    0x81, 0xa0, 0xe8, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x09, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x2e, 0x02, 0x60, 0x40, 0x34, 0x08,
+		    0x82, 0xa0, 0x16, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xdd, 0x24, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 148.352 MHz */
+		{
+		    0x01, 0xd2, 0x3e, 0x00, 0x40, 0x5b, 0xef, 0x08,
+		    0x81, 0xa0, 0xb9, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x04, 0x10, 0x5b, 0xa7, 0x08,
+		    0x84, 0xa0, 0xe8, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x09, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd2, 0x5d, 0x02, 0x20, 0x5b, 0xcd, 0x10,
+		    0x43, 0xa0, 0x16, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xdd, 0x24, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 108.108 MHz */
+		{
+		    0x01, 0xd1, 0x2d, 0x12, 0x40, 0x64, 0x12, 0x08,
+		    0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd2, 0x70, 0x14, 0x51, 0x50, 0x31, 0x08,
+		    0x80, 0x80, 0x5e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x6c, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd4, 0x87, 0x01, 0x60, 0x64, 0x1b, 0x20,
+		    0x19, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x2f, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 72 MHz */
+		{
+		    0x01, 0x51, 0x1e, 0x15, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0xb4, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xab, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0x52, 0x4b, 0x15, 0x51, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0xe1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x89, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0x51, 0x2d, 0x15, 0x61, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 25 MHz */
+		{
+		    0x01, 0xd1, 0x2a, 0x72, 0x40, 0x3c, 0xd8, 0x08,
+		    0x86, 0xa0, 0xfa, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xf6, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x27, 0x51, 0x55, 0x40, 0x08, 0x08,
+		    0x81, 0xa0, 0xea, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc5, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd2, 0x1f, 0x30, 0x63, 0x40, 0x20, 0x08,
+		    0x81, 0x80, 0xbc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xa4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 65 MHz */
+		{
+		    0x01, 0xd1, 0x36, 0x34, 0x40, 0x0c, 0x04, 0x08,
+		    0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x22, 0x11, 0x51, 0x30, 0xf2, 0x08,
+		    0x86, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x97, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x29, 0x12, 0x61, 0x40, 0xd0, 0x08,
+		    0x87, 0xa0, 0xf4, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x7e, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 108 MHz */
+		{
+		    0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x38, 0x14, 0x51, 0x08, 0x04, 0x08,
+		    0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x6c, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x22, 0x01, 0x60, 0x08, 0xfc, 0x08,
+		    0x86, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0x5a, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x2f, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	}, {/* freq = 162 MHz */
+		{
+		    0x01, 0x54, 0x87, 0x05, 0x40, 0x01, 0x00, 0x08,
+		    0x82, 0x80, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0x2f, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x2a, 0x02, 0x50, 0x40, 0x18, 0x08,
+		    0x86, 0xa0, 0xfd, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xf3, 0x24, 0x03, 0x00, 0x00, 0x01, 0x00,
+		}, {
+		    0x01, 0xd1, 0x33, 0x04, 0x60, 0x40, 0xd0, 0x08,
+		    0x85, 0xa0, 0x32, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+		    0xad, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
+		    0x54, 0xca, 0x24, 0x03, 0x00, 0x00, 0x01, 0x00,
+		},
+	},
+};
+#else
+static const u8 phy_config[][3][32] = {
+	{ /* freq = 25.200 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x02, 0x51, 0x5f, 0xF1, 0x54, 0x7e,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xf3, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x02, 0x51, 0x9f, 0xF6, 0x54, 0x9e,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xB8, 0x10, 0xE0,
+			0x22, 0x40, 0xc2, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x02, 0x51, 0xFf, 0xF3, 0x54, 0xbd,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xA4, 0x10, 0xE0,
+			0x22, 0x40, 0xa2, 0x26, 0x00, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 25.175 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x1e, 0x20,
+			0x6B, 0x50, 0x10, 0x51, 0xf1, 0x31, 0x54, 0xbd,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xf3, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x2b, 0x40,
+			0x6B, 0x50, 0x10, 0x51, 0xF2, 0x32, 0x54, 0xec,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xB8, 0x10, 0xE0,
+			0x22, 0x40, 0xc2, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x1e, 0x20,
+			0x6B, 0x10, 0x02, 0x51, 0xf1, 0x31, 0x54, 0xbd,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xA4, 0x10, 0xE0,
+			0x22, 0x40, 0xa2, 0x26, 0x00, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 27 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x02, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe3, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x02, 0x08,
+			0x6A, 0x10, 0x02, 0x51, 0xCf, 0xF1, 0x54, 0xa9,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xB8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xfc, 0x08,
+			0x6B, 0x10, 0x02, 0x51, 0x2f, 0xF2, 0x54, 0xcb,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xA4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x00, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 27.027 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
+			0x6B, 0x10, 0x02, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe2, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x31, 0x50,
+			0x6B, 0x10, 0x02, 0x51, 0x8f, 0xF3, 0x54, 0xa9,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xB8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0x10, 0x10, 0x9C, 0x1b, 0x64,
+			0x6F, 0x10, 0x02, 0x51, 0x7f, 0xF8, 0x54, 0xcb,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xA4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x00, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 54 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x01, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe3, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x02, 0x08,
+			0x6A, 0x10, 0x01, 0x51, 0xCf, 0xF1, 0x54, 0xa9,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xfc, 0x08,
+			0x6B, 0x10, 0x01, 0x51, 0x2f, 0xF2, 0x54, 0xcb,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x01, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 54.054 MHz */
+		{
+			0x01, 0x05, 0x00, 0xd4, 0x10, 0x9C, 0x09, 0x64,
+			0x6B, 0x10, 0x01, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe2, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xd4, 0x10, 0x9C, 0x31, 0x50,
+			0x6B, 0x10, 0x01, 0x51, 0x8f, 0xF3, 0x54, 0xa9,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0x10, 0x10, 0x9C, 0x1b, 0x64,
+			0x6F, 0x10, 0x01, 0x51, 0x7f, 0xF8, 0x54, 0xcb,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x01, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 74.250 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
+			0x6A, 0x10, 0x01, 0x51, 0xff, 0xF1, 0x54, 0xba,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xd6, 0x40,
+			0x6B, 0x10, 0x01, 0x51, 0x7f, 0xF2, 0x54, 0xe8,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0x83, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x34, 0x40,
+			0x6B, 0x10, 0x01, 0x51, 0xef, 0xF2, 0x54, 0x16,
+			0x85, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0xdc, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 74.176 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
+			0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0x10, 0x10, 0x9C, 0xab, 0x5B,
+			0x6F, 0x10, 0x01, 0x51, 0xbf, 0xF9, 0x54, 0xe8,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0x84, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0xcd, 0x5B,
+			0x6F, 0x10, 0x01, 0x51, 0xdf, 0xF5, 0x54, 0x16,
+			0x85, 0x00, 0x30, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0xdc, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 148.500 MHz  - Pre-emph + Higher Tx amp. */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
+			0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xd6, 0x40,
+			0x6B, 0x18, 0x00, 0x51, 0x7f, 0xF2, 0x54, 0xe8,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x23, 0x41, 0x83, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x34, 0x40,
+			0x6B, 0x18, 0x00, 0x51, 0xef, 0xF2, 0x54, 0x16,
+			0x85, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x23, 0x41, 0x6d, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 148.352 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
+			0x6D, 0x18, 0x00, 0x51, 0xef, 0xF3, 0x54, 0xb9,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xa5, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0x10, 0x10, 0x9C, 0xab, 0x5B,
+			0x6F, 0x18, 0x00, 0x51, 0xbf, 0xF9, 0x54, 0xe8,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x23, 0x41, 0x84, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0xcd, 0x5B,
+			0x6F, 0x18, 0x00, 0x51, 0xdf, 0xF5, 0x54, 0x16,
+			0x85, 0x00, 0x30, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x23, 0x41, 0x6d, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 108.108 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
+			0x6B, 0x18, 0x00, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe2, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x31, 0x50,
+			0x6D, 0x18, 0x00, 0x51, 0x8f, 0xF3, 0x54, 0xa9,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0x10, 0x10, 0x9C, 0x1b, 0x64,
+			0x6F, 0x18, 0x00, 0x51, 0x7f, 0xF8, 0x54, 0xcb,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 72 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x10, 0x01, 0x51, 0xEf, 0xF1, 0x54, 0xb4,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xaa, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6F, 0x10, 0x01, 0x51, 0xBf, 0xF4, 0x54, 0xe1,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0x88, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6B, 0x18, 0x00, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0xe3, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 25 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x20, 0x40,
+			0x6B, 0x50, 0x10, 0x51, 0xff, 0xF1, 0x54, 0xbc,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xf5, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x08, 0x40,
+			0x6B, 0x50, 0x10, 0x51, 0x7f, 0xF2, 0x54, 0xea,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xB8, 0x10, 0xE0,
+			0x22, 0x40, 0xc4, 0x26, 0x00, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x20, 0x40,
+			0x6B, 0x10, 0x02, 0x51, 0xff, 0xF1, 0x54, 0xbc,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xA4, 0x10, 0xE0,
+			0x22, 0x40, 0xa3, 0x26, 0x00, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 65 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x02, 0x0c,
+			0x6B, 0x10, 0x01, 0x51, 0xBf, 0xF1, 0x54, 0xa3,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xbc, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf2, 0x30,
+			0x6A, 0x10, 0x01, 0x51, 0x2f, 0xF2, 0x54, 0xcb,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0x96, 0x26, 0x01, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xd0, 0x40,
+			0x6B, 0x10, 0x01, 0x51, 0x9f, 0xF2, 0x54, 0xf4,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0x7D, 0x26, 0x01, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 108 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6D, 0x18, 0x00, 0x51, 0xDf, 0xF2, 0x54, 0x87,
+			0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0xe3, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x02, 0x08,
+			0x6A, 0x18, 0x00, 0x51, 0xCf, 0xF1, 0x54, 0xa9,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x22, 0x40, 0xb5, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xfc, 0x08,
+			0x6B, 0x18, 0x00, 0x51, 0x2f, 0xF2, 0x54, 0xcb,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	}, { /* freq = 162 MHz */
+		{
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+			0x6F, 0x18, 0x00, 0x51, 0x7f, 0xF8, 0x54, 0xcb,
+			0x84, 0x00, 0x32, 0x38, 0x00, 0x08, 0x10, 0xE0,
+			0x22, 0x40, 0x97, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0x18, 0x40,
+			0x6B, 0x18, 0x00, 0x51, 0xAf, 0xF2, 0x54, 0xfd,
+			0x84, 0x00, 0x10, 0x38, 0x00, 0xF8, 0x10, 0xE0,
+			0x23, 0x41, 0x78, 0x26, 0x02, 0x00, 0x00, 0x80,
+		}, {
+			0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xd0, 0x40,
+			0x6B, 0x18, 0x00, 0x51, 0x3f, 0xF3, 0x54, 0x30,
+			0x85, 0x00, 0x10, 0x38, 0x00, 0xE4, 0x10, 0xE0,
+			0x23, 0x41, 0x64, 0x26, 0x02, 0x00, 0x00, 0x80,
+		},
+	},
+};
+#endif
+
+#ifndef CONFIG_HDMI_PHY_32N
+static void s5p_hdmi_reg_core_reset(void)
+{
+	writeb(0x0, hdmi_base + S5P_HDMI_CORE_RSTOUT);
+
+	mdelay(10);
+
+	writeb(0x1, hdmi_base + S5P_HDMI_CORE_RSTOUT);
+}
+#endif
+
+static s32 s5p_hdmi_i2c_phy_interruptwait(void)
+{
+	u8 status, reg;
+	s32 retval = 0;
+
+	do {
+		status = readb(i2c_hdmi_phy_base + HDMI_I2C_CON);
+
+		if (status & I2C_PEND) {
+			reg = readb(i2c_hdmi_phy_base + HDMI_I2C_STAT);
+			break;
+		}
+
+	} while (1);
+
+	return retval;
+}
+
+static s32 s5p_hdmi_i2c_phy_read(u8 addr, u8 nbytes, u8 *buffer)
+{
+	u8 reg;
+	s32 ret = 0;
+	u32 proc = true;
+
+	i2c_hdmi_phy_context.state = STATE_RX_ADDR;
+	i2c_hdmi_phy_context.buffer = buffer;
+	i2c_hdmi_phy_context.bytes = nbytes;
+
+	writeb(I2C_CLK | I2C_INT | I2C_ACK, i2c_hdmi_phy_base + HDMI_I2C_CON);
+	writeb(I2C_ENABLE | I2C_MODE_MRX, i2c_hdmi_phy_base + HDMI_I2C_STAT);
+	writeb(addr & 0xFE, i2c_hdmi_phy_base + HDMI_I2C_DS);
+	writeb(I2C_ENABLE | I2C_START | I2C_MODE_MRX,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+
+	while (proc) {
+
+		if (i2c_hdmi_phy_context.state != STATE_RX_STOP) {
+
+			if (s5p_hdmi_i2c_phy_interruptwait() != 0) {
+				tvout_err("interrupt wait failed!!!\n");
+				ret = -1;
+				break;
+			}
+
+		}
+
+		switch (i2c_hdmi_phy_context.state) {
+		case STATE_RX_DATA:
+			reg = readb(i2c_hdmi_phy_base + HDMI_I2C_DS);
+			*(i2c_hdmi_phy_context.buffer) = reg;
+
+			i2c_hdmi_phy_context.buffer++;
+			--(i2c_hdmi_phy_context.bytes);
+
+			if (i2c_hdmi_phy_context.bytes == 1) {
+				i2c_hdmi_phy_context.state = STATE_RX_STOP;
+				writeb(I2C_CLK_PEND_INT,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			} else {
+				writeb(I2C_CLK_PEND_INT | I2C_ACK,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			}
+
+			break;
+
+		case STATE_RX_ADDR:
+			i2c_hdmi_phy_context.state = STATE_RX_DATA;
+
+			if (i2c_hdmi_phy_context.bytes == 1) {
+				i2c_hdmi_phy_context.state = STATE_RX_STOP;
+				writeb(I2C_CLK_PEND_INT,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			} else {
+				writeb(I2C_CLK_PEND_INT | I2C_ACK,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			}
+
+			break;
+
+		case STATE_RX_STOP:
+			i2c_hdmi_phy_context.state = STATE_IDLE;
+
+			reg = readb(i2c_hdmi_phy_base + HDMI_I2C_DS);
+
+			*(i2c_hdmi_phy_context.buffer) = reg;
+
+			writeb(I2C_MODE_MRX|I2C_ENABLE,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+			writeb(I2C_CLK_PEND_INT,
+				i2c_hdmi_phy_base + HDMI_I2C_CON);
+			writeb(I2C_MODE_MRX,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+
+			while (readb(i2c_hdmi_phy_base + HDMI_I2C_STAT) &
+					I2C_START)
+				usleep_range(1000, 1000);
+
+			proc = false;
+			break;
+
+		case STATE_IDLE:
+		default:
+			tvout_err("error state!!!\n");
+
+			ret = -1;
+
+			proc = false;
+			break;
+		}
+
+	}
+
+	return ret;
+}
+
+static s32 s5p_hdmi_i2c_phy_write(u8 addr, u8 nbytes, u8 *buffer)
+{
+	u8 reg;
+	s32 ret = 0;
+	u32 proc = true;
+
+	i2c_hdmi_phy_context.state = STATE_TX_ADDR;
+	i2c_hdmi_phy_context.buffer = buffer;
+	i2c_hdmi_phy_context.bytes = nbytes;
+
+	writeb(I2C_CLK | I2C_INT | I2C_ACK, i2c_hdmi_phy_base + HDMI_I2C_CON);
+	writeb(I2C_ENABLE | I2C_MODE_MTX, i2c_hdmi_phy_base + HDMI_I2C_STAT);
+	writeb(addr & 0xFE, i2c_hdmi_phy_base + HDMI_I2C_DS);
+	writeb(I2C_ENABLE | I2C_START | I2C_MODE_MTX,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+
+	while (proc) {
+
+		if (s5p_hdmi_i2c_phy_interruptwait() != 0) {
+			tvout_err("interrupt wait failed!!!\n");
+			ret = -1;
+
+			break;
+		}
+
+		switch (i2c_hdmi_phy_context.state) {
+		case STATE_TX_ADDR:
+		case STATE_TX_DATA:
+			i2c_hdmi_phy_context.state = STATE_TX_DATA;
+
+			reg = *(i2c_hdmi_phy_context.buffer);
+
+			writeb(reg, i2c_hdmi_phy_base + HDMI_I2C_DS);
+
+			i2c_hdmi_phy_context.buffer++;
+			--(i2c_hdmi_phy_context.bytes);
+
+			if (i2c_hdmi_phy_context.bytes == 0) {
+				i2c_hdmi_phy_context.state = STATE_TX_STOP;
+				writeb(I2C_CLK_PEND_INT,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			} else {
+				writeb(I2C_CLK_PEND_INT | I2C_ACK,
+					i2c_hdmi_phy_base + HDMI_I2C_CON);
+			}
+
+			break;
+
+		case STATE_TX_STOP:
+			i2c_hdmi_phy_context.state = STATE_IDLE;
+
+			writeb(I2C_MODE_MTX | I2C_ENABLE,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+			writeb(I2C_CLK_PEND_INT,
+				i2c_hdmi_phy_base + HDMI_I2C_CON);
+			writeb(I2C_MODE_MTX,
+				i2c_hdmi_phy_base + HDMI_I2C_STAT);
+
+			while (readb(i2c_hdmi_phy_base + HDMI_I2C_STAT) &
+					I2C_START)
+				usleep_range(1000, 1000);
+
+			proc = false;
+			break;
+
+		case STATE_IDLE:
+		default:
+			tvout_err("error state!!!\n");
+
+			ret = -1;
+
+			proc = false;
+			break;
+		}
+
+	}
+
+	return ret;
+}
+
+#ifdef S5P_HDMI_DEBUG
+static void s5p_hdmi_print_phy_config(void)
+{
+	s32 size;
+	int i = 0;
+	u8 read_buffer[0x40] = {0, };
+	size = sizeof(phy_config[0][0])
+		/ sizeof(phy_config[0][0][0]);
+
+
+	/* read data */
+	if (s5p_hdmi_i2c_phy_read(PHY_I2C_ADDRESS, size, read_buffer) != 0) {
+		tvout_err("s5p_hdmi_i2c_phy_read failed.\n");
+		return;
+	}
+
+	printk(KERN_WARNING "read buffer :\n");
+
+	for (i = 1; i < size; i++) {
+		printk("0x%02x", read_buffer[i]);
+
+		if (i % 8)
+			printk(" ");
+		else
+			printk("\n");
+	}
+	printk(KERN_WARNING "\n");
+}
+#else
+static inline void s5p_hdmi_print_phy_config(void) {}
+#endif
+
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+static void s5p_hdmi_audio_set_config(
+		enum s5p_tvout_audio_codec_type audio_codec)
+{
+	u32 data_type = (audio_codec == PCM) ?
+			S5P_HDMI_SPDIFIN_CFG_LINEAR_PCM_TYPE :
+			(audio_codec == AC3) ?
+				S5P_HDMI_SPDIFIN_CFG_NO_LINEAR_PCM_TYPE : 0xff;
+
+	tvout_dbg("audio codec type = %s\n",
+		(audio_codec & PCM) ? "PCM" :
+		(audio_codec & AC3) ? "AC3" :
+		(audio_codec & MP3) ? "MP3" :
+		(audio_codec & WMA) ? "WMA" : "Unknown");
+
+	/* open SPDIF path on HDMI_I2S */
+	writeb(S5P_HDMI_I2S_CLK_EN, hdmi_base + S5P_HDMI_I2S_CLK_CON);
+	writeb(readl(hdmi_base + S5P_HDMI_I2S_MUX_CON) |
+		S5P_HDMI_I2S_CUV_I2S_ENABLE |
+		S5P_HDMI_I2S_MUX_ENABLE,
+		hdmi_base + S5P_HDMI_I2S_MUX_CON);
+	writeb(S5P_HDMI_I2S_CH_ALL_EN, hdmi_base + S5P_HDMI_I2S_MUX_CH);
+	writeb(S5P_HDMI_I2S_CUV_RL_EN, hdmi_base + S5P_HDMI_I2S_MUX_CUV);
+
+	writeb(S5P_HDMI_SPDIFIN_CFG_FILTER_2_SAMPLE | data_type |
+		S5P_HDMI_SPDIFIN_CFG_PCPD_MANUAL_SET |
+		S5P_HDMI_SPDIFIN_CFG_WORD_LENGTH_M_SET |
+		S5P_HDMI_SPDIFIN_CFG_U_V_C_P_REPORT |
+		S5P_HDMI_SPDIFIN_CFG_BURST_SIZE_2 |
+		S5P_HDMI_SPDIFIN_CFG_DATA_ALIGN_32BIT,
+		hdmi_base + S5P_HDMI_SPDIFIN_CONFIG_1);
+
+	writeb(S5P_HDMI_SPDIFIN_CFG2_NO_CLK_DIV,
+		hdmi_base + S5P_HDMI_SPDIFIN_CONFIG_2);
+}
+
+static void s5p_hdmi_audio_clock_enable(void)
+{
+	writeb(S5P_HDMI_SPDIFIN_CLK_ON, hdmi_base + S5P_HDMI_SPDIFIN_CLK_CTRL);
+	writeb(S5P_HDMI_SPDIFIN_STATUS_CHK_OP_MODE,
+		hdmi_base + S5P_HDMI_SPDIFIN_OP_CTRL);
+}
+
+static void s5p_hdmi_audio_set_repetition_time(
+				enum s5p_tvout_audio_codec_type audio_codec,
+				u32 bits, u32 frame_size_code)
+{
+	/* Only 4'b1011 24bit */
+	u32 wl = 5 << 1 | 1;
+	u32 rpt_cnt = (audio_codec == AC3) ? 1536 * 2 - 1 : 0;
+
+	tvout_dbg("repetition count = %d\n", rpt_cnt);
+
+	/* 24bit and manual mode */
+	writeb(((rpt_cnt & 0xf) << 4) | wl,
+		hdmi_base + S5P_HDMI_SPDIFIN_USER_VALUE_1);
+	/* if PCM this value is 0 */
+	writeb((rpt_cnt >> 4) & 0xff,
+		hdmi_base + S5P_HDMI_SPDIFIN_USER_VALUE_2);
+	/* if PCM this value is 0 */
+	writeb(frame_size_code & 0xff,
+		hdmi_base + S5P_HDMI_SPDIFIN_USER_VALUE_3);
+	/* if PCM this value is 0 */
+	writeb((frame_size_code >> 8) & 0xff,
+		hdmi_base + S5P_HDMI_SPDIFIN_USER_VALUE_4);
+}
+
+static void s5p_hdmi_audio_irq_enable(u32 irq_en)
+{
+	writeb(irq_en, hdmi_base + S5P_HDMI_SPDIFIN_IRQ_MASK);
+}
+#else
+static void s5p_hdmi_audio_i2s_config(
+		enum s5p_tvout_audio_codec_type audio_codec,
+		u32 sample_rate, u32 bits_per_sample,
+		u32 frame_size_code,
+		struct s5p_hdmi_audio *audio)
+{
+	u32 data_num, bit_ch, sample_frq;
+
+	if (bits_per_sample == 20) {
+		data_num = 2;
+		bit_ch  = 1;
+	} else if (bits_per_sample == 24) {
+		data_num = 3;
+		bit_ch  = 1;
+	} else {
+		data_num = 1;
+		bit_ch  = 0;
+	}
+
+	writeb((S5P_HDMI_I2S_IN_DISABLE | S5P_HDMI_I2S_AUD_I2S |
+		S5P_HDMI_I2S_CUV_I2S_ENABLE | S5P_HDMI_I2S_MUX_ENABLE),
+		hdmi_base + S5P_HDMI_I2S_MUX_CON);
+
+	writeb(S5P_HDMI_I2S_CH0_EN | S5P_HDMI_I2S_CH1_EN | S5P_HDMI_I2S_CH2_EN,
+		hdmi_base + S5P_HDMI_I2S_MUX_CH);
+
+	writeb(S5P_HDMI_I2S_CUV_RL_EN, hdmi_base + S5P_HDMI_I2S_MUX_CUV);
+
+	sample_frq = (sample_rate == 44100) ? 0 :
+			(sample_rate == 48000) ? 2 :
+			(sample_rate == 32000) ? 3 :
+			(sample_rate == 96000) ? 0xa : 0x0;
+
+	/* readl(hdmi_base + S5P_HDMI_YMAX) */
+	writeb(S5P_HDMI_I2S_CLK_DIS, hdmi_base + S5P_HDMI_I2S_CLK_CON);
+	writeb(S5P_HDMI_I2S_CLK_EN, hdmi_base + S5P_HDMI_I2S_CLK_CON);
+
+	writeb(readl(hdmi_base + S5P_HDMI_I2S_DSD_CON) | 0x01,
+		hdmi_base + S5P_HDMI_I2S_DSD_CON);
+
+	/* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
+	writeb(S5P_HDMI_I2S_SEL_SCLK(5) | S5P_HDMI_I2S_SEL_LRCK(6),
+			hdmi_base + S5P_HDMI_I2S_PIN_SEL_0);
+	if (audio->channel == 2)
+		/* I2S 2 channel */
+		writeb(S5P_HDMI_I2S_SEL_SDATA1(1) | S5P_HDMI_I2S_SEL_SDATA2(4),
+				hdmi_base + S5P_HDMI_I2S_PIN_SEL_1);
+	else
+		/* I2S 5.1 channel */
+		writeb(S5P_HDMI_I2S_SEL_SDATA1(3) | S5P_HDMI_I2S_SEL_SDATA2(4),
+				hdmi_base + S5P_HDMI_I2S_PIN_SEL_1);
+
+	writeb(S5P_HDMI_I2S_SEL_SDATA3(1) | S5P_HDMI_I2S_SEL_SDATA2(2),
+			hdmi_base + S5P_HDMI_I2S_PIN_SEL_2);
+	writeb(S5P_HDMI_I2S_SEL_DSD(0), hdmi_base + S5P_HDMI_I2S_PIN_SEL_3);
+
+	/* I2S_CON_1 & 2 */
+	writeb(S5P_HDMI_I2S_SCLK_FALLING_EDGE | S5P_HDMI_I2S_L_CH_LOW_POL,
+		hdmi_base + S5P_HDMI_I2S_CON_1);
+	writeb(S5P_HDMI_I2S_MSB_FIRST_MODE |
+		S5P_HDMI_I2S_SET_BIT_CH(bit_ch) |
+		S5P_HDMI_I2S_SET_SDATA_BIT(data_num) |
+		S5P_HDMI_I2S_BASIC_FORMAT,
+		hdmi_base + S5P_HDMI_I2S_CON_2);
+
+	/* Configure register related to CUV information */
+	writeb(S5P_HDMI_I2S_CH_STATUS_MODE_0 |
+		S5P_HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH |
+		S5P_HDMI_I2S_COPYRIGHT |
+		S5P_HDMI_I2S_LINEAR_PCM |
+		S5P_HDMI_I2S_CONSUMER_FORMAT,
+		hdmi_base + S5P_HDMI_I2S_CH_ST_0);
+	writeb(S5P_HDMI_I2S_CD_PLAYER,
+		hdmi_base + S5P_HDMI_I2S_CH_ST_1);
+
+	if (audio->channel == 2)
+		/* Audio channel to 5.1 */
+		writeb(S5P_HDMI_I2S_SET_SOURCE_NUM(0),
+				hdmi_base + S5P_HDMI_I2S_CH_ST_2);
+	else
+		writeb(S5P_HDMI_I2S_SET_SOURCE_NUM(0) |
+				S5P_HDMI_I2S_SET_CHANNEL_NUM(0x6),
+				hdmi_base + S5P_HDMI_I2S_CH_ST_2);
+
+	writeb(S5P_HDMI_I2S_CLK_ACCUR_LEVEL_2 |
+		S5P_HDMI_I2S_SET_SAMPLING_FREQ(sample_frq),
+		hdmi_base + S5P_HDMI_I2S_CH_ST_3);
+	writeb(S5P_HDMI_I2S_ORG_SAMPLING_FREQ_44_1 |
+		S5P_HDMI_I2S_WORD_LENGTH_MAX24_24BITS |
+		S5P_HDMI_I2S_WORD_LENGTH_MAX_24BITS,
+		hdmi_base + S5P_HDMI_I2S_CH_ST_4);
+
+	writeb(S5P_HDMI_I2S_CH_STATUS_RELOAD,
+		hdmi_base + S5P_HDMI_I2S_CH_ST_CON);
+}
+#endif
+
+static u8 s5p_hdmi_checksum(int sum, int size, u8 *data)
+{
+	u32 i;
+
+	for (i = 0; i < size; i++)
+		sum += (u32)(data[i]);
+
+	return (u8)(0x100 - (sum & 0xff));
+}
+
+
+static int s5p_hdmi_phy_control(bool on, u8 addr, u8 offset, u8 *read_buffer)
+{
+	u8 buff[2] = {0};
+
+	buff[0] = addr;
+	buff[1] = (on) ? (read_buffer[addr] & (~(1 << offset))) :
+			(read_buffer[addr] | (1 << offset));
+	read_buffer[addr] = buff[1];
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, 2, buff) != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int s5p_hdmi_phy_enable_oscpad(bool on, u8 *read_buffer)
+{
+	u8 buff[2];
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	buff[0] = 0x0b;
+	if (on)
+		buff[1] = 0xd8;
+	else
+		buff[1] = 0x18;
+	read_buffer[0x0b] = buff[1];
+#else
+	buff[0] = 0x19;
+	if (on)
+		buff[1] = (read_buffer[0x19] & (~(3<<6))) | (1<<6);
+	else
+		buff[1] = (read_buffer[0x19] & (~(3<<6))) | (2<<6);
+	read_buffer[0x19] = buff[1];
+#endif
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, 2, buff) != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static bool s5p_hdmi_phy_is_enable(void)
+{
+	u32 reg;
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	reg = readl(S5P_HDMI_PHY_CONTROL);
+#endif
+
+	return reg & (1 << 0);
+}
+
+static void s5p_hdmi_phy_enable(bool on)
+{
+	u32 reg;
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	reg = readl(S5P_HDMI_PHY_CONTROL);
+
+	if (on)
+		reg |= (1 << 0);
+	else
+		reg &= ~(1 << 0);
+
+	writeb(reg, S5P_HDMI_PHY_CONTROL);
+#endif
+
+}
+
+void s5p_hdmi_reg_sw_reset(void)
+{
+	tvout_dbg("\n");
+	s5p_hdmi_ctrl_clock(1);
+
+	writeb(0x1, hdmi_base + S5P_HDMI_PHY_RSTOUT);
+	mdelay(10);
+	writeb(0x0, hdmi_base + S5P_HDMI_PHY_RSTOUT);
+
+	s5p_hdmi_ctrl_clock(0);
+}
+
+int s5p_hdmi_phy_power(bool on)
+{
+	u32 size;
+	u8 *buffer;
+	u8 read_buffer[0x40] = {0, };
+
+	size = sizeof(phy_config[0][0])
+		/ sizeof(phy_config[0][0][0]);
+
+	buffer = (u8 *) phy_config[0][0];
+
+	tvout_dbg("(on:%d)\n", on);
+	if (on) {
+		if (!s5p_hdmi_phy_is_enable()) {
+			s5p_hdmi_phy_enable(1);
+			s5p_hdmi_reg_sw_reset();
+
+			if (s5p_hdmi_i2c_phy_write(
+				PHY_I2C_ADDRESS, 1, buffer) != 0)
+				goto ret_on_err;
+
+			if (s5p_hdmi_i2c_phy_read(
+				PHY_I2C_ADDRESS, size, read_buffer) != 0) {
+				tvout_err("s5p_hdmi_i2c_phy_read failed.\n");
+				goto ret_on_err;
+			}
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			s5p_hdmi_phy_control(true, 0x1d, 0x7, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x0, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x1, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x2, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x4, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x5, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1d, 0x6, read_buffer);
+#else
+			s5p_hdmi_phy_control(true, 0x1, 0x5, read_buffer);
+			s5p_hdmi_phy_control(true, 0x1, 0x7, read_buffer);
+			s5p_hdmi_phy_control(true, 0x5, 0x5, read_buffer);
+			s5p_hdmi_phy_control(true, 0x17, 0x0, read_buffer);
+			s5p_hdmi_phy_control(true, 0x17, 0x1, read_buffer);
+#endif
+
+			s5p_hdmi_print_phy_config();
+		}
+	} else {
+		if (s5p_hdmi_phy_is_enable()) {
+			if (s5p_hdmi_i2c_phy_write(
+				PHY_I2C_ADDRESS, 1, buffer) != 0)
+				goto ret_on_err;
+
+			if (s5p_hdmi_i2c_phy_read(
+				PHY_I2C_ADDRESS, size, read_buffer) != 0) {
+				tvout_err("s5p_hdmi_i2c_phy_read failed.\n");
+				goto ret_on_err;
+			}
+			/* Disable OSC pad */
+			s5p_hdmi_phy_enable_oscpad(false, read_buffer);
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+			s5p_hdmi_phy_control(false, 0x1d, 0x7, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x0, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x1, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x2, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x4, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x5, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1d, 0x6, read_buffer);
+			s5p_hdmi_phy_control(false, 0x4, 0x3, read_buffer);
+#else
+			s5p_hdmi_phy_control(false, 0x1, 0x5, read_buffer);
+			s5p_hdmi_phy_control(false, 0x1, 0x7, read_buffer);
+			s5p_hdmi_phy_control(false, 0x5, 0x5, read_buffer);
+			s5p_hdmi_phy_control(false, 0x17, 0x0, read_buffer);
+			s5p_hdmi_phy_control(false, 0x17, 0x1, read_buffer);
+#endif
+
+			s5p_hdmi_print_phy_config();
+
+			s5p_hdmi_phy_enable(0);
+		}
+	}
+
+	return 0;
+
+ret_on_err:
+	return -1;
+}
+
+s32 s5p_hdmi_phy_config(
+		enum phy_freq freq, enum s5p_hdmi_color_depth cd)
+{
+	s32 index;
+	s32 size;
+	u8 buffer[32] = {0, };
+	u8 reg;
+
+	switch (cd) {
+	case HDMI_CD_24:
+		index = 0;
+		break;
+
+	case HDMI_CD_30:
+		index = 1;
+		break;
+
+	case HDMI_CD_36:
+		index = 2;
+		break;
+
+	default:
+		return -1;
+	}
+
+	buffer[0] = PHY_REG_MODE_SET_DONE;
+	buffer[1] = 0x00;
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, 2, buffer) != 0) {
+		tvout_err("s5p_hdmi_i2c_phy_write failed.\n");
+		return -1;
+	}
+
+	writeb(0x5, i2c_hdmi_phy_base + HDMI_I2C_LC);
+
+	size = sizeof(phy_config[freq][index])
+		/ sizeof(phy_config[freq][index][0]);
+
+	memcpy(buffer, phy_config[freq][index], sizeof(buffer));
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, size, buffer) != 0)
+		return -1;
+
+#ifdef CONFIG_HDMI_PHY_32N
+	buffer[0] = PHY_REG_MODE_SET_DONE;
+	buffer[1] = 0x80;
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, 2, buffer) != 0) {
+		tvout_err("s5p_hdmi_i2c_phy_write failed.\n");
+		return -1;
+	}
+#else
+	buffer[0] = 0x01;
+
+	if (s5p_hdmi_i2c_phy_write(PHY_I2C_ADDRESS, 1, buffer) != 0) {
+		tvout_err("s5p_hdmi_i2c_phy_write failed.\n");
+		return -1;
+	}
+#endif
+
+	s5p_hdmi_print_phy_config();
+
+#ifndef CONFIG_HDMI_PHY_32N
+	s5p_hdmi_reg_core_reset();
+#endif
+
+#ifdef CONFIG_HDMI_PHY_32N
+	do {
+		reg = readb(hdmi_base + S5P_HDMI_PHY_STATUS0);
+	} while (!(reg & S5P_HDMI_PHY_STATUS_READY));
+#else
+	do {
+		reg = readb(hdmi_base + S5P_HDMI_PHY_STATUS);
+	} while (!(reg & S5P_HDMI_PHY_STATUS_READY));
+#endif
+
+	writeb(I2C_CLK_PEND_INT, i2c_hdmi_phy_base + HDMI_I2C_CON);
+	writeb(I2C_IDLE, i2c_hdmi_phy_base + HDMI_I2C_STAT);
+
+	return 0;
+}
+
+void s5p_hdmi_set_gcp(enum s5p_hdmi_color_depth	depth, u8 *gcp)
+{
+	switch (depth) {
+	case HDMI_CD_48:
+		gcp[1] = S5P_HDMI_GCP_48BPP; break;
+	case HDMI_CD_36:
+		gcp[1] = S5P_HDMI_GCP_36BPP; break;
+	case HDMI_CD_30:
+		gcp[1] = S5P_HDMI_GCP_30BPP; break;
+	case HDMI_CD_24:
+		gcp[1] = S5P_HDMI_GCP_24BPP; break;
+
+	default:
+		break;
+	}
+}
+
+void s5p_hdmi_reg_acr(u8 *acr)
+{
+	u32 n	= acr[4] << 16 | acr[5] << 8 | acr[6];
+	u32 cts	= acr[1] << 16 | acr[2] << 8 | acr[3];
+
+	hdmi_write_24(n, hdmi_base + S5P_HDMI_ACR_N0);
+	hdmi_write_24(cts, hdmi_base + S5P_HDMI_ACR_MCTS0);
+	hdmi_write_24(cts, hdmi_base + S5P_HDMI_ACR_CTS0);
+
+	writeb(4, hdmi_base + S5P_HDMI_ACR_CON);
+}
+
+void s5p_hdmi_reg_asp(u8 *asp, struct s5p_hdmi_audio *audio)
+{
+	if (audio->channel == 2)
+		writeb(S5P_HDMI_AUD_NO_DST_DOUBLE | S5P_HDMI_AUD_TYPE_SAMPLE |
+			S5P_HDMI_AUD_MODE_TWO_CH | S5P_HDMI_AUD_SP_ALL_DIS,
+			hdmi_base + S5P_HDMI_ASP_CON);
+	else
+		writeb(S5P_HDMI_AUD_MODE_MULTI_CH | S5P_HDMI_AUD_SP_AUD2_EN |
+			S5P_HDMI_AUD_SP_AUD1_EN | S5P_HDMI_AUD_SP_AUD0_EN,
+			hdmi_base + S5P_HDMI_ASP_CON);
+
+	writeb(S5P_HDMI_ASP_SP_FLAT_AUD_SAMPLE,
+		hdmi_base + S5P_HDMI_ASP_SP_FLAT);
+
+	if (audio->channel == 2) {
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM0R | S5P_HDMI_SPK0L_SEL_I_PCM0L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG0);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM0R | S5P_HDMI_SPK0L_SEL_I_PCM0L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG1);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM0R | S5P_HDMI_SPK0L_SEL_I_PCM0L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG2);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM0R | S5P_HDMI_SPK0L_SEL_I_PCM0L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG3);
+	} else {
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM0R | S5P_HDMI_SPK0L_SEL_I_PCM0L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG0);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM1L | S5P_HDMI_SPK0L_SEL_I_PCM1R,
+				hdmi_base + S5P_HDMI_ASP_CHCFG1);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM2R | S5P_HDMI_SPK0L_SEL_I_PCM2L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG2);
+		writeb(S5P_HDMI_SPK0R_SEL_I_PCM3R | S5P_HDMI_SPK0L_SEL_I_PCM3L,
+				hdmi_base + S5P_HDMI_ASP_CHCFG3);
+	}
+}
+
+void s5p_hdmi_reg_gcp(u8 i_p, u8 *gcp)
+{
+	u32 gcp_con;
+
+	writeb(gcp[2], hdmi_base + S5P_HDMI_GCP_BYTE2);
+
+	gcp_con = readb(hdmi_base + S5P_HDMI_GCP_CON);
+
+	if (i_p)
+		gcp_con |= S5P_HDMI_GCP_CON_EN_1ST_VSYNC |
+				S5P_HDMI_GCP_CON_EN_2ST_VSYNC;
+	else
+		gcp_con &= (~(S5P_HDMI_GCP_CON_EN_1ST_VSYNC |
+				S5P_HDMI_GCP_CON_EN_2ST_VSYNC));
+
+	writeb(gcp_con, hdmi_base + S5P_HDMI_GCP_CON);
+
+}
+
+void s5p_hdmi_reg_acp(u8 *header, u8 *acp)
+{
+	writeb(header[1], hdmi_base + S5P_HDMI_ACP_TYPE);
+}
+
+void s5p_hdmi_reg_isrc(u8 *isrc1, u8 *isrc2)
+{
+}
+
+void s5p_hdmi_reg_gmp(u8 *gmp)
+{
+}
+
+#ifdef CONFIG_HDMI_14A_3D
+
+#define VENDOR_HEADER00			0x81
+#define VENDOR_HEADER01			0x01
+#define VENDOR_HEADER02			0x05
+#define VENDOR_INFOFRAME_HEADER		(0x1 + 0x01 + 0x06)
+#define VENDOR_PACKET_BYTE_LENGTH 0x06
+#define TRANSMIT_EVERY_VSYNC		(1<<1)
+
+void s5p_hdmi_reg_infoframe(struct s5p_hdmi_infoframe *info,
+	u8 *data, u8 type_3D)
+{
+	u32 start_addr = 0, sum_addr = 0;
+	u8 sum;
+	u32 uSpdCon;
+	u8 ucChecksum, i;
+
+	switch (info->type) {
+	case HDMI_VSI_INFO:
+		writeb((u8)VENDOR_HEADER00, hdmi_base + S5P_HDMI_VSI_HEADER0);
+		writeb((u8)VENDOR_HEADER01, hdmi_base + S5P_HDMI_VSI_HEADER1);
+
+		if (type_3D == HDMI_3D_FP_FORMAT) {
+			writeb((u8)VENDOR_HEADER02,
+				hdmi_base + S5P_HDMI_VSI_HEADER2);
+			ucChecksum = VENDOR_HEADER00 +
+				VENDOR_HEADER01 + VENDOR_HEADER02;
+
+			for (i = 0; i < VENDOR_PACKET_BYTE_LENGTH; i++)
+				ucChecksum += readb(hdmi_base +
+					S5P_HDMI_VSI_DATA01+4*i);
+
+			writeb((u8)0x2a, hdmi_base + S5P_HDMI_VSI_DATA00);
+			writeb((u8)0x03, hdmi_base + S5P_HDMI_VSI_DATA01);
+			writeb((u8)0x0c, hdmi_base + S5P_HDMI_VSI_DATA02);
+			writeb((u8)0x00, hdmi_base + S5P_HDMI_VSI_DATA03);
+			writeb((u8)0x40, hdmi_base + S5P_HDMI_VSI_DATA04);
+			writeb((u8)0x00, hdmi_base + S5P_HDMI_VSI_DATA05);
+
+		} else if (type_3D == HDMI_3D_TB_FORMAT) {
+			writeb((u8)VENDOR_HEADER02, hdmi_base +
+				S5P_HDMI_VSI_HEADER2);
+			ucChecksum = VENDOR_HEADER00 +
+				VENDOR_HEADER01 + VENDOR_HEADER02;
+
+			for (i = 0; i < VENDOR_PACKET_BYTE_LENGTH; i++)
+				ucChecksum += readb(hdmi_base +
+					S5P_HDMI_VSI_DATA01+4*i);
+
+			writeb((u8)0xca, hdmi_base + S5P_HDMI_VSI_DATA00);
+			writeb((u8)0x03, hdmi_base + S5P_HDMI_VSI_DATA01);
+			writeb((u8)0x0c, hdmi_base + S5P_HDMI_VSI_DATA02);
+			writeb((u8)0x00, hdmi_base + S5P_HDMI_VSI_DATA03);
+			writeb((u8)0x40, hdmi_base + S5P_HDMI_VSI_DATA04);
+			writeb((u8)0x60, hdmi_base + S5P_HDMI_VSI_DATA05);
+
+		} else if (type_3D == HDMI_3D_SSH_FORMAT) {
+			writeb((u8)0x06, hdmi_base + S5P_HDMI_VSI_HEADER2);
+			ucChecksum = VENDOR_HEADER00 + VENDOR_HEADER01 + 0x06;
+
+			for (i = 0; i < 7; i++)
+				ucChecksum += readb(hdmi_base +
+					S5P_HDMI_VSI_DATA01+4*i);
+
+			writeb((u8)0x99, hdmi_base + S5P_HDMI_VSI_DATA00);
+			writeb((u8)0x03, hdmi_base + S5P_HDMI_VSI_DATA01);
+			writeb((u8)0x0c, hdmi_base + S5P_HDMI_VSI_DATA02);
+			writeb((u8)0x00, hdmi_base + S5P_HDMI_VSI_DATA03);
+			writeb((u8)0x40, hdmi_base + S5P_HDMI_VSI_DATA04);
+			writeb((u8)0x80, hdmi_base + S5P_HDMI_VSI_DATA05);
+			writeb((u8)0x10, hdmi_base + S5P_HDMI_VSI_DATA06);
+
+		} else {
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_HEADER2);
+			ucChecksum = VENDOR_HEADER00 + VENDOR_HEADER01 + 0x06;
+
+			for (i = 0; i < 7; i++)
+				ucChecksum += readb(hdmi_base +
+					S5P_HDMI_VSI_DATA01+4*i);
+
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA00);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA01);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA02);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA03);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA04);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA05);
+			writeb((u8)0x0, hdmi_base + S5P_HDMI_VSI_DATA06);
+			tvout_dbg("2D format is supported.\n");
+			return ;
+		}
+
+		uSpdCon = readb(hdmi_base + S5P_HDMI_VSI_CON);
+		uSpdCon = (uSpdCon&(~(3<<0)))|(TRANSMIT_EVERY_VSYNC);
+		writeb((u8)uSpdCon, hdmi_base + S5P_HDMI_VSI_CON);
+		break;
+	case HDMI_AVI_INFO:
+		writeb((u8)0x82, hdmi_base + S5P_HDMI_AVI_HEADER0);
+		writeb((u8)0x02, hdmi_base + S5P_HDMI_AVI_HEADER1);
+		writeb((u8)0x0d, hdmi_base + S5P_HDMI_AVI_HEADER2);
+
+		sum_addr	= S5P_HDMI_AVI_CHECK_SUM;
+		start_addr	= S5P_HDMI_AVI_BYTE1;
+		break;
+	case HDMI_SPD_INFO:
+		sum_addr	= S5P_HDMI_SPD_DATA00;
+		start_addr	= S5P_HDMI_SPD_DATA01 + 4;
+		/* write header */
+		writeb((u8)info->type, hdmi_base + S5P_HDMI_SPD_HEADER0);
+		writeb((u8)info->version, hdmi_base + S5P_HDMI_SPD_HEADER1);
+		writeb((u8)info->length, hdmi_base + S5P_HDMI_SPD_HEADER2);
+		break;
+	case HDMI_AUI_INFO:
+		writeb((u8)0x84, hdmi_base + S5P_HDMI_AUI_HEADER0);
+		writeb((u8)0x01, hdmi_base + S5P_HDMI_AUI_HEADER1);
+		writeb((u8)0x0a, hdmi_base + S5P_HDMI_AUI_HEADER2);
+		sum_addr	= S5P_HDMI_AUI_CHECK_SUM;
+		start_addr	= S5P_HDMI_AUI_BYTE1;
+		break;
+	case HDMI_MPG_INFO:
+		sum_addr	= S5P_HDMI_MPG_CHECK_SUM;
+		start_addr	= S5P_HDMI_MPG_BYTE1;
+		break;
+	default:
+		tvout_dbg("undefined infoframe\n");
+		return;
+	}
+
+	/* calculate checksum */
+	sum = (u8)info->type + info->version + info->length;
+	sum = s5p_hdmi_checksum(sum, info->length, data);
+
+	/* write checksum */
+	writeb(sum, hdmi_base + sum_addr);
+	/* write data */
+	hdmi_write_l(data, hdmi_base, start_addr, info->length);
+}
+
+void s5p_hdmi_reg_tg(struct s5p_hdmi_v_format *v)
+{
+	u8 tg;
+	struct s5p_hdmi_v_frame	*frame = &(v->frame);
+
+	hdmi_write_16(v->tg_H_FSZ, hdmi_base + S5P_HDMI_TG_H_FSZ_L);
+	hdmi_write_16(v->tg_HACT_ST, hdmi_base + S5P_HDMI_TG_HACT_ST_L);
+	hdmi_write_16(v->tg_HACT_SZ, hdmi_base + S5P_HDMI_TG_HACT_SZ_L);
+
+	hdmi_write_16(v->tg_V_FSZ, hdmi_base + S5P_HDMI_TG_V_FSZ_L);
+	hdmi_write_16(v->tg_VACT_SZ, hdmi_base + S5P_HDMI_TG_VACT_SZ_L);
+	hdmi_write_16(v->tg_VACT_ST, hdmi_base + S5P_HDMI_TG_VACT_ST_L);
+	hdmi_write_16(v->tg_VACT_ST2, hdmi_base + S5P_HDMI_TG_VACT_ST2_L);
+	hdmi_write_16(v->tg_VACT_ST3, hdmi_base + S5P_HDMI_TG_VACT_ST3_L);
+	hdmi_write_16(v->tg_VACT_ST4, hdmi_base + S5P_HDMI_TG_VACT_ST4_L);
+
+	hdmi_write_16(v->tg_VSYNC_BOT_HDMI, hdmi_base +
+		S5P_HDMI_TG_VSYNC_BOT_HDMI_L);
+	hdmi_write_16(v->tg_VSYNC_TOP_HDMI, hdmi_base +
+		S5P_HDMI_TG_VSYNC_TOP_HDMI_L);
+	hdmi_write_16(v->tg_FIELD_TOP_HDMI, hdmi_base +
+		S5P_HDMI_TG_FIELD_TOP_HDMI_L);
+	hdmi_write_16(v->tg_FIELD_BOT_HDMI, hdmi_base +
+		S5P_HDMI_TG_FIELD_BOT_HDMI_L);
+
+	/* write reg default value */
+	hdmi_write_16(v->tg_VSYNC, hdmi_base + S5P_HDMI_TG_VSYNC_L);
+	hdmi_write_16(v->tg_VSYNC2, hdmi_base + S5P_HDMI_TG_VSYNC2_L);
+	hdmi_write_16(v->tg_FIELD_CHG, hdmi_base + S5P_HDMI_TG_FIELD_CHG_L);
+
+	tg = readb(hdmi_base + S5P_HDMI_TG_CMD);
+
+	hdmi_bit_set(frame->interlaced, tg, S5P_HDMI_FIELD);
+
+	writeb(tg, hdmi_base + S5P_HDMI_TG_CMD);
+}
+
+void s5p_hdmi_reg_v_timing(struct s5p_hdmi_v_format *v)
+{
+	u32 uTemp32;
+
+	struct s5p_hdmi_v_frame	*frame = &(v->frame);
+
+	uTemp32 = frame->vH_Line;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_H_LINE_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_H_LINE_1);
+
+	uTemp32 = frame->vV_Line;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_LINE_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_LINE_1);
+
+	uTemp32 = frame->vH_SYNC_START;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_H_SYNC_START_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_H_SYNC_START_1);
+
+	uTemp32 = frame->vH_SYNC_END;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_H_SYNC_END_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_H_SYNC_END_1);
+
+	uTemp32 = frame->vV1_Blank;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V1_BLANK_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V1_BLANK_1);
+
+	uTemp32 = frame->vV2_Blank;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V2_BLANK_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V2_BLANK_1);
+
+	uTemp32 = frame->vHBlank;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_H_BLANK_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_H_BLANK_1);
+
+	uTemp32 = frame->VBLANK_F0;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F0_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F0_1);
+
+	uTemp32 = frame->VBLANK_F1;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F1_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F1_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F2_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F2_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F3_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F3_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F4_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F4_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_BLANK_F5_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_BLANK_F5_1);
+
+	uTemp32 = frame->vVSYNC_LINE_BEF_1;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_BEF_1_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_BEF_1_1);
+
+	uTemp32 = frame->vVSYNC_LINE_BEF_2;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_BEF_2_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_BEF_2_1);
+
+	uTemp32 = frame->vVSYNC_LINE_AFT_1;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_1_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_1_1);
+
+	uTemp32 = frame->vVSYNC_LINE_AFT_2;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_2_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_2_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_3_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_3_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_4_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_4_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_5_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_5_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_6_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_V_SYNC_LINE_AFT_6_1);
+
+	uTemp32 = frame->vVSYNC_LINE_AFT_PXL_1;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_1_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_1_1);
+
+	uTemp32 = frame->vVSYNC_LINE_AFT_PXL_2;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_2_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_2_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_3_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_3_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_4_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_4_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_5_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_5_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_6_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base +
+		S5P_HDMI_V_SYNC_LINE_AFT_PXL_6_1);
+
+	uTemp32 = frame->vVACT_SPACE_1;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_1_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_1_1);
+
+	uTemp32 = frame->vVACT_SPACE_2;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_2_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_2_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_3_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_3_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_4_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_4_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_5_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_5_1);
+
+	uTemp32 = 0xffff;
+	writeb((u8)(uTemp32&0xff), hdmi_base + S5P_HDMI_VACT_SPACE_6_0);
+	writeb((u8)(uTemp32 >> 8), hdmi_base + S5P_HDMI_VACT_SPACE_6_1);
+
+	writeb(frame->Hsync_polarity, hdmi_base + S5P_HDMI_HSYNC_POL);
+
+	writeb(frame->Vsync_polarity, hdmi_base + S5P_HDMI_VSYNC_POL);
+
+	writeb(frame->interlaced, hdmi_base + S5P_HDMI_INT_PRO_MODE);
+}
+
+void s5p_hdmi_reg_bluescreen_clr(u16 b, u16 g, u16 r)
+{
+	writeb((u8)(b>>8), hdmi_base + S5P_HDMI_BLUE_SCREEN_B_0);
+	writeb((u8)(b&0xff), hdmi_base + S5P_HDMI_BLUE_SCREEN_B_0);
+	writeb((u8)(g>>8), hdmi_base + S5P_HDMI_BLUE_SCREEN_G_0);
+	writeb((u8)(g&0xff), hdmi_base + S5P_HDMI_BLUE_SCREEN_G_1);
+	writeb((u8)(r>>8), hdmi_base + S5P_HDMI_BLUE_SCREEN_R_0);
+	writeb((u8)(r&0xff), hdmi_base + S5P_HDMI_BLUE_SCREEN_R_1);
+}
+
+#else
+void s5p_hdmi_reg_infoframe(struct s5p_hdmi_infoframe *info, u8 *data)
+{
+	u32 start_addr = 0, sum_addr = 0;
+	u8 sum;
+
+	switch (info->type) {
+	case HDMI_VSI_INFO:
+		break;
+	case HDMI_AVI_INFO:
+		sum_addr	= S5P_HDMI_AVI_CHECK_SUM;
+		start_addr	= S5P_HDMI_AVI_DATA;
+		break;
+	case HDMI_SPD_INFO:
+		sum_addr	= S5P_HDMI_SPD_DATA;
+		start_addr	= S5P_HDMI_SPD_DATA + 4;
+		/* write header */
+		writeb((u8)info->type, hdmi_base + S5P_HDMI_SPD_HEADER);
+		writeb((u8)info->version, hdmi_base + S5P_HDMI_SPD_HEADER + 4);
+		writeb((u8)info->length, hdmi_base + S5P_HDMI_SPD_HEADER + 8);
+		break;
+	case HDMI_AUI_INFO:
+		sum_addr	= S5P_HDMI_AUI_CHECK_SUM;
+		start_addr	= S5P_HDMI_AUI_BYTE1;
+		break;
+	case HDMI_MPG_INFO:
+		sum_addr	= S5P_HDMI_MPG_CHECK_SUM;
+		start_addr	= S5P_HDMI_MPG_DATA;
+		break;
+	default:
+		tvout_dbg("undefined infoframe\n");
+		return;
+	}
+
+	/* calculate checksum */
+	sum = (u8)info->type + info->version + info->length;
+	sum = s5p_hdmi_checksum(sum, info->length, data);
+
+	/* write checksum */
+	writeb(sum, hdmi_base + sum_addr);
+
+	/* write data */
+	hdmi_write_l(data, hdmi_base, start_addr, info->length);
+}
+
+void s5p_hdmi_reg_tg(struct s5p_hdmi_v_frame *frame)
+{
+	u16 reg;
+	u8 tg;
+
+	hdmi_write_16(frame->h_total, hdmi_base + S5P_HDMI_TG_H_FSZ_L);
+	hdmi_write_16((frame->h_blank)-1, hdmi_base + S5P_HDMI_TG_HACT_ST_L);
+	hdmi_write_16((frame->h_active)+1, hdmi_base + S5P_HDMI_TG_HACT_SZ_L);
+
+	hdmi_write_16(frame->v_total, hdmi_base + S5P_HDMI_TG_V_FSZ_L);
+	hdmi_write_16(frame->v_active, hdmi_base + S5P_HDMI_TG_VACT_SZ_L);
+
+
+	reg = (frame->i_p) ? (frame->v_total - frame->v_active*2) / 2 :
+				frame->v_total - frame->v_active;
+	hdmi_write_16(reg, hdmi_base + S5P_HDMI_TG_VACT_ST_L);
+
+	reg = (frame->i_p) ? 0x249 : 0x248;
+	hdmi_write_16(reg, hdmi_base + S5P_HDMI_TG_VACT_ST2_L);
+
+	reg = (frame->i_p) ? 0x233 : 1;
+	hdmi_write_16(reg, hdmi_base + S5P_HDMI_TG_VSYNC_BOT_HDMI_L);
+
+	/* write reg default value */
+	hdmi_write_16(0x1, hdmi_base + S5P_HDMI_TG_VSYNC_L);
+	hdmi_write_16(0x233, hdmi_base + S5P_HDMI_TG_VSYNC2_L);
+	hdmi_write_16(0x233, hdmi_base + S5P_HDMI_TG_FIELD_CHG_L);
+	hdmi_write_16(0x1, hdmi_base + S5P_HDMI_TG_VSYNC_TOP_HDMI_L);
+	hdmi_write_16(0x1, hdmi_base + S5P_HDMI_TG_FIELD_TOP_HDMI_L);
+	hdmi_write_16(0x233, hdmi_base + S5P_HDMI_TG_FIELD_BOT_HDMI_L);
+
+	tg = readb(hdmi_base + S5P_HDMI_TG_CMD);
+
+	hdmi_bit_set(frame->i_p, tg, S5P_HDMI_FIELD);
+
+	writeb(tg, hdmi_base + S5P_HDMI_TG_CMD);
+}
+
+void s5p_hdmi_reg_v_timing(struct s5p_hdmi_v_format *v)
+{
+	u32 reg32;
+
+	struct s5p_hdmi_v_frame	*frame = &(v->frame);
+
+	writeb(frame->polarity, hdmi_base + S5P_HDMI_SYNC_MODE);
+	writeb(frame->i_p, hdmi_base + S5P_HDMI_INT_PRO_MODE);
+
+	hdmi_write_16(frame->h_blank, hdmi_base + S5P_HDMI_H_BLANK_0);
+
+	reg32 = (frame->v_blank << 11) | (frame->v_blank + frame->v_active);
+	hdmi_write_24(reg32, hdmi_base + S5P_HDMI_V_BLANK_0);
+
+	reg32 = (frame->h_total << 12) | frame->v_total;
+	hdmi_write_24(reg32, hdmi_base + S5P_HDMI_H_V_LINE_0);
+
+	reg32 = frame->polarity << 20 | v->h_sync.end << 10 | v->h_sync.begin;
+	hdmi_write_24(reg32, hdmi_base + S5P_HDMI_H_SYNC_GEN_0);
+
+	reg32 = v->v_sync_top.begin << 12 | v->v_sync_top.end;
+	hdmi_write_24(reg32, hdmi_base + S5P_HDMI_V_SYNC_GEN_1_0);
+
+	if (frame->i_p) {
+		reg32 = v->v_blank_f.end << 11 | v->v_blank_f.begin;
+		hdmi_write_24(reg32, hdmi_base + S5P_HDMI_V_BLANK_F_0);
+
+		reg32 = v->v_sync_bottom.begin << 12 | v->v_sync_bottom.end;
+		hdmi_write_24(reg32, hdmi_base + S5P_HDMI_V_SYNC_GEN_2_0);
+
+		reg32 = v->v_sync_h_pos.begin << 12 | v->v_sync_h_pos.end;
+		hdmi_write_24(reg32, hdmi_base + S5P_HDMI_V_SYNC_GEN_3_0);
+	} else {
+		hdmi_write_24(0x0, hdmi_base + S5P_HDMI_V_BLANK_F_0);
+		hdmi_write_24(0x1001, hdmi_base + S5P_HDMI_V_SYNC_GEN_2_0);
+		hdmi_write_24(0x1001, hdmi_base + S5P_HDMI_V_SYNC_GEN_3_0);
+	}
+}
+
+void s5p_hdmi_reg_bluescreen_clr(u8 cb_b, u8 y_g, u8 cr_r)
+{
+	writeb(cb_b, hdmi_base + S5P_HDMI_BLUE_SCREEN_0);
+	writeb(y_g, hdmi_base + S5P_HDMI_BLUE_SCREEN_1);
+	writeb(cr_r, hdmi_base + S5P_HDMI_BLUE_SCREEN_2);
+}
+#endif
+
+void s5p_hdmi_reg_bluescreen(bool en)
+{
+	u8 reg = readl(hdmi_base + S5P_HDMI_CON_0);
+
+	hdmi_bit_set(en, reg, S5P_HDMI_BLUE_SCR_EN);
+
+	writeb(reg, hdmi_base + S5P_HDMI_CON_0);
+}
+
+void s5p_hdmi_reg_clr_range(u8 y_min, u8 y_max, u8 c_min, u8 c_max)
+{
+	writeb(y_max, hdmi_base + S5P_HDMI_YMAX);
+	writeb(y_min, hdmi_base + S5P_HDMI_YMIN);
+	writeb(c_max, hdmi_base + S5P_HDMI_CMAX);
+	writeb(c_min, hdmi_base + S5P_HDMI_CMIN);
+}
+
+void s5p_hdmi_reg_tg_cmd(bool time, bool bt656, bool tg)
+{
+	u8 reg = 0;
+
+	reg = readb(hdmi_base + S5P_HDMI_TG_CMD);
+
+	hdmi_bit_set(time, reg, S5P_HDMI_GETSYNC_TYPE);
+	hdmi_bit_set(bt656, reg, S5P_HDMI_GETSYNC);
+	hdmi_bit_set(tg, reg, S5P_HDMI_TG);
+
+	writeb(reg, hdmi_base + S5P_HDMI_TG_CMD);
+}
+
+void s5p_hdmi_reg_enable(bool en)
+{
+	u8 reg;
+
+	reg = readb(hdmi_base + S5P_HDMI_CON_0);
+
+	if (en)
+		reg |= S5P_HDMI_EN;
+	else
+		reg &= ~(S5P_HDMI_EN | S5P_HDMI_ASP_EN);
+
+	writeb(reg, hdmi_base + S5P_HDMI_CON_0);
+
+	if (!en) {
+		do {
+			reg = readb(hdmi_base + S5P_HDMI_CON_0);
+		} while (reg & S5P_HDMI_EN);
+	}
+}
+
+u8 s5p_hdmi_reg_intc_status(void)
+{
+#ifdef CONFIG_HDMI_14A_3D
+	return readb(hdmi_base + S5P_HDMI_INTC_FLAG0);
+#else
+	return readb(hdmi_base + S5P_HDMI_INTC_FLAG);
+#endif
+}
+
+u8 s5p_hdmi_reg_intc_get_enabled(void)
+{
+#ifdef CONFIG_HDMI_14A_3D
+	return readb(hdmi_base + S5P_HDMI_INTC_CON0);
+#else
+	return readb(hdmi_base + S5P_HDMI_INTC_CON);
+#endif
+}
+
+void s5p_hdmi_reg_intc_clear_pending(enum s5p_hdmi_interrrupt intr)
+{
+	u8 reg;
+#ifdef CONFIG_HDMI_14A_3D
+	reg = readb(hdmi_base + S5P_HDMI_INTC_FLAG0);
+	writeb(reg | (1 << intr), hdmi_base + S5P_HDMI_INTC_FLAG0);
+#else
+	reg = readb(hdmi_base + S5P_HDMI_INTC_FLAG);
+	writeb(reg | (1 << intr), hdmi_base + S5P_HDMI_INTC_FLAG);
+#endif
+}
+
+
+void s5p_hdmi_reg_sw_hpd_enable(bool enable)
+{
+	u8 reg;
+
+	reg = readb(hdmi_base + S5P_HDMI_HPD);
+	reg &= ~S5P_HDMI_HPD_SEL_I_HPD;
+
+	if (enable)
+		writeb(reg | S5P_HDMI_HPD_SEL_I_HPD, hdmi_base + S5P_HDMI_HPD);
+	else
+		writeb(reg, hdmi_base + S5P_HDMI_HPD);
+}
+
+void s5p_hdmi_reg_set_hpd_onoff(bool on_off)
+{
+	u8 reg;
+
+	reg = readb(hdmi_base + S5P_HDMI_HPD);
+	reg &= ~S5P_HDMI_SW_HPD_PLUGGED;
+
+	if (on_off)
+		writel(reg | S5P_HDMI_SW_HPD_PLUGGED,
+			hdmi_base + S5P_HDMI_HPD);
+	else
+		writel(reg | S5P_HDMI_SW_HPD_UNPLUGGED,
+			hdmi_base + S5P_HDMI_HPD);
+
+}
+
+u8 s5p_hdmi_reg_get_hpd_status(void)
+{
+	return readb(hdmi_base + S5P_HDMI_HPD_STATUS);
+}
+
+void s5p_hdmi_reg_hpd_gen(void)
+{
+#ifdef CONFIG_HDMI_14A_3D
+	writeb(0xFF, hdmi_base + S5P_HDMI_HPD_GEN0);
+#else
+	writeb(0xFF, hdmi_base + S5P_HDMI_HPD_GEN);
+#endif
+}
+
+int s5p_hdmi_reg_intc_set_isr(irqreturn_t (*isr)(int, void *), u8 num)
+{
+	if (!isr) {
+		tvout_err("invalid irq routine\n");
+		return -1;
+	}
+
+	if (num >= HDMI_IRQ_TOTAL_NUM) {
+		tvout_err("max irq_num exceeded\n");
+		return -1;
+	}
+
+	if (s5p_hdmi_isr_ftn[num])
+		tvout_dbg("irq %d already registered\n", num);
+
+	s5p_hdmi_isr_ftn[num] = isr;
+
+	tvout_dbg("success to register irq : %d\n", num);
+
+	return 0;
+}
+EXPORT_SYMBOL(s5p_hdmi_reg_intc_set_isr);
+
+void s5p_hdmi_reg_intc_enable(enum s5p_hdmi_interrrupt intr, u8 en)
+{
+	u8 reg;
+
+	reg = s5p_hdmi_reg_intc_get_enabled();
+
+	if (en) {
+		if (!reg)
+			reg |= S5P_HDMI_INTC_EN_GLOBAL;
+
+		reg |= (1 << intr);
+	} else {
+		reg &= ~(1 << intr);
+
+		if (!reg)
+			reg &= ~S5P_HDMI_INTC_EN_GLOBAL;
+	}
+#ifdef CONFIG_HDMI_14A_3D
+	writeb(reg, hdmi_base + S5P_HDMI_INTC_CON0);
+#else
+	writeb(reg, hdmi_base + S5P_HDMI_INTC_CON);
+#endif
+}
+
+void s5p_hdmi_reg_audio_enable(u8 en)
+{
+	u8 con, mod;
+	con = readb(hdmi_base + S5P_HDMI_CON_0);
+	mod = readb(hdmi_base + S5P_HDMI_MODE_SEL);
+
+	if (en) {
+#ifndef CONFIG_HDMI_EARJACK_MUTE
+		if (mod & S5P_HDMI_DVI_MODE_EN)
+#else
+		if ((mod & S5P_HDMI_DVI_MODE_EN) || hdmi_audio_ext)
+#endif
+			return;
+
+		con |= S5P_HDMI_ASP_EN;
+		writeb(HDMI_TRANS_EVERY_SYNC, hdmi_base + S5P_HDMI_AUI_CON);
+	} else {
+		con &= ~S5P_HDMI_ASP_EN;
+		writeb(HDMI_DO_NOT_TANS, hdmi_base + S5P_HDMI_AUI_CON);
+	}
+
+	writeb(con, hdmi_base + S5P_HDMI_CON_0);
+}
+
+int s5p_hdmi_audio_init(
+		enum s5p_tvout_audio_codec_type audio_codec,
+		u32 sample_rate, u32 bits, u32 frame_size_code,
+		struct s5p_hdmi_audio *audio)
+{
+#ifdef CONFIG_SND_SAMSUNG_SPDIF
+	s5p_hdmi_audio_set_config(audio_codec);
+	s5p_hdmi_audio_set_repetition_time(audio_codec, bits, frame_size_code);
+	s5p_hdmi_audio_irq_enable(S5P_HDMI_SPDIFIN_IRQ_OVERFLOW_EN);
+	s5p_hdmi_audio_clock_enable();
+#else
+	s5p_hdmi_audio_i2s_config(audio_codec, sample_rate, bits,
+				frame_size_code, audio);
+#endif
+	return 0;
+}
+
+void s5p_hdmi_reg_mute(bool en)
+{
+	s5p_hdmi_reg_bluescreen(en);
+
+	s5p_hdmi_reg_audio_enable(!en);
+}
+
+irqreturn_t s5p_hdmi_irq(int irq, void *dev_id)
+{
+	u8 state, num = 0;
+	unsigned long spin_flags;
+
+	spin_lock_irqsave(&lock_hdmi, spin_flags);
+
+#ifdef CONFIG_HDMI_14A_3D
+	state = readb(hdmi_base + S5P_HDMI_INTC_FLAG0);
+#else
+	state = readb(hdmi_base + S5P_HDMI_INTC_FLAG);
+#endif
+
+	if (!state) {
+		tvout_err("undefined irq : %d\n", state);
+		goto irq_handled;
+	}
+
+	for (num = 0; num < HDMI_IRQ_TOTAL_NUM; num++) {
+
+		if (!(state & (1 << num)))
+			continue;
+
+		if (s5p_hdmi_isr_ftn[num]) {
+			tvout_dbg("call by s5p_hdmi_isr_ftn num : %d\n", num);
+			(s5p_hdmi_isr_ftn[num])(num, NULL);
+		} else
+			tvout_dbg("unregistered irq : %d\n", num);
+	}
+
+irq_handled:
+	spin_unlock_irqrestore(&lock_hdmi, spin_flags);
+
+	return IRQ_HANDLED;
+}
+
+void s5p_hdmi_init(void __iomem *hdmi_addr)
+{
+	hdmi_base = hdmi_addr;
+	spin_lock_init(&lock_hdmi);
+}
+
+void s5p_hdmi_phy_init(void __iomem *hdmi_phy_addr)
+{
+	i2c_hdmi_phy_base = hdmi_phy_addr;
+	if (i2c_hdmi_phy_base != NULL)
+		writeb(0x5, i2c_hdmi_phy_base + HDMI_I2C_LC);
+}
+
+void s5p_hdmi_reg_output(struct s5p_hdmi_o_reg *reg)
+{
+	writeb(reg->pxl_limit, hdmi_base + S5P_HDMI_CON_1);
+	writeb(reg->preemble, hdmi_base + S5P_HDMI_CON_2);
+	writeb(reg->mode, hdmi_base + S5P_HDMI_MODE_SEL);
+}
+
+void s5p_hdmi_reg_packet_trans(struct s5p_hdmi_o_trans *trans)
+{
+	u8 reg;
+
+	writeb(trans->avi, hdmi_base + S5P_HDMI_AVI_CON);
+	writeb(trans->mpg, hdmi_base + S5P_HDMI_MPG_CON);
+	writeb(trans->spd, hdmi_base + S5P_HDMI_SPD_CON);
+	writeb(trans->gmp, hdmi_base + S5P_HDMI_GAMUT_CON);
+	writeb(trans->aui, hdmi_base + S5P_HDMI_AUI_CON);
+
+	reg = trans->gcp | readb(hdmi_base + S5P_HDMI_GCP_CON);
+	writeb(reg, hdmi_base + S5P_HDMI_GCP_CON);
+
+	reg = trans->isrc | readb(hdmi_base + S5P_HDMI_ISRC_CON);
+	writeb(reg, hdmi_base + S5P_HDMI_ISRC_CON);
+
+	reg = trans->acp | readb(hdmi_base + S5P_HDMI_ACP_CON);
+	writeb(reg, hdmi_base + S5P_HDMI_ACP_CON);
+
+	reg = trans->acr | readb(hdmi_base + S5P_HDMI_ACP_CON);
+	writeb(reg, hdmi_base + S5P_HDMI_ACR_CON);
+}
diff --git a/drivers/media/video/samsung/tvout/hw_if/hw_if.h b/drivers/media/video/samsung/tvout/hw_if/hw_if.h
new file mode 100644
index 0000000..11bda99
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/hw_if.h
@@ -0,0 +1,1005 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/hw_if.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Header file for interface of Samsung TVOUT-related hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _SAMSUNG_TVOUT_HW_IF_H_
+#define _SAMSUNG_TVOUT_HW_IF_H_ __FILE__
+
+/*****************************************************************************
+ * This file includes declarations for external functions of
+ * Samsung TVOUT-related hardware. So only external functions
+ * to be used by higher layer must exist in this file.
+ *
+ * Higher layer must use only the declarations included in this file.
+ ****************************************************************************/
+
+#include <linux/irqreturn.h>
+#include <linux/stddef.h>
+
+#include "../s5p_tvout_common_lib.h"
+
+/*****************************************************************************
+ * Common
+ ****************************************************************************/
+enum s5p_tvout_endian {
+	TVOUT_LITTLE_ENDIAN = 0,
+	TVOUT_BIG_ENDIAN = 1
+};
+
+
+
+/*****************************************************************************
+ * for MIXER
+ ****************************************************************************/
+enum s5p_mixer_layer {
+	MIXER_VIDEO_LAYER = 2,
+	MIXER_GPR0_LAYER = 0,
+	MIXER_GPR1_LAYER = 1
+};
+
+enum s5p_mixer_bg_color_num {
+	MIXER_BG_COLOR_0 = 0,
+	MIXER_BG_COLOR_1 = 1,
+	MIXER_BG_COLOR_2 = 2
+};
+
+enum s5p_mixer_color_fmt {
+	MIXER_RGB565  = 4,
+	MIXER_RGB1555 = 5,
+	MIXER_RGB4444 = 6,
+	MIXER_RGB8888 = 7
+};
+
+enum s5p_mixer_rgb {
+	MIXER_RGB601_0_255 = 0,
+	MIXER_RGB601_16_235,
+	MIXER_RGB709_0_255,
+	MIXER_RGB709_16_235
+};
+
+enum s5p_mixer_out_type {
+	MIXER_YUV444,
+	MIXER_RGB888
+};
+
+extern int s5p_mixer_set_show(enum s5p_mixer_layer layer, bool show);
+extern int s5p_mixer_set_priority(enum s5p_mixer_layer layer, u32 priority);
+extern void s5p_mixer_set_pre_mul_mode(enum s5p_mixer_layer layer, bool enable);
+extern int s5p_mixer_set_pixel_blend(enum s5p_mixer_layer layer, bool enable);
+extern int s5p_mixer_set_layer_blend(enum s5p_mixer_layer layer, bool enable);
+extern int s5p_mixer_set_alpha(enum s5p_mixer_layer layer, u32 alpha);
+extern int s5p_mixer_set_grp_base_address(enum s5p_mixer_layer layer,
+		u32 baseaddr);
+extern int s5p_mixer_set_grp_layer_dst_pos(enum s5p_mixer_layer layer,
+		u32 dst_offs_x, u32 dst_offs_y);
+extern int s5p_mixer_set_grp_layer_src_pos(enum s5p_mixer_layer layer, u32 span,
+		u32 width, u32 height, u32 src_offs_x, u32 src_offs_y);
+extern void s5p_mixer_set_bg_color(enum s5p_mixer_bg_color_num colornum,
+		u32 color_y, u32 color_cb, u32 color_cr);
+extern void s5p_mixer_set_video_limiter(u32 upper_y, u32 lower_y,
+		u32 upper_c, u32 lower_c, bool enable);
+extern void s5p_mixer_init_status_reg(enum s5p_mixer_burst_mode burst,
+		enum s5p_tvout_endian endian);
+extern int s5p_mixer_init_display_mode(enum s5p_tvout_disp_mode mode,
+		enum s5p_tvout_o_mode output_mode, enum s5p_mixer_rgb
+		rgb_type);
+extern void s5p_mixer_scaling(enum s5p_mixer_layer layer,
+		struct s5ptvfb_user_scaling scaling);
+extern void s5p_mixer_set_color_format(enum s5p_mixer_layer layer,
+		enum s5p_mixer_color_fmt format);
+extern void s5p_mixer_set_chroma_key(enum s5p_mixer_layer layer, bool enabled,
+		u32 key);
+extern void s5p_mixer_init_bg_dither_enable(bool cr_dither_enable,
+		bool cdither_enable, bool y_dither_enable);
+extern void s5p_mixer_init_csc_coef_default(enum s5p_mixer_rgb csc_type);
+extern void s5p_mixer_start(void);
+extern void s5p_mixer_stop(void);
+extern void s5p_mixer_set_underflow_int_enable(enum s5p_mixer_layer layer,
+		bool en);
+extern void s5p_mixer_set_vsync_interrupt(bool);
+extern void s5p_mixer_clear_pend_all(void);
+extern irqreturn_t s5p_mixer_irq(int irq, void *dev_id);
+extern void s5p_mixer_init(void __iomem *addr);
+
+
+/*****************************************************************************
+ * for HDMI
+ ****************************************************************************/
+#define hdmi_mask_8(x)		((x) & 0xFF)
+#define hdmi_mask_16(x)		(((x) >> 8) & 0xFF)
+#define hdmi_mask_24(x)		(((x) >> 16) & 0xFF)
+#define hdmi_mask_32(x)		(((x) >> 24) & 0xFF)
+
+#define hdmi_write_16(x, y)				\
+	do {						\
+		writeb(hdmi_mask_8(x), y);		\
+		writeb(hdmi_mask_16(x), y + 4);		\
+	} while (0);
+
+#define hdmi_write_24(x, y)				\
+	do {						\
+		writeb(hdmi_mask_8(x), y);		\
+		writeb(hdmi_mask_16(x), y + 4);		\
+		writeb(hdmi_mask_24(x), y + 8);		\
+	} while (0);
+
+#define hdmi_write_32(x, y)				\
+	do {						\
+		writeb(hdmi_mask_8(x), y);		\
+		writeb(hdmi_mask_16(x), y + 4);		\
+		writeb(hdmi_mask_24(x), y + 8);		\
+		writeb(hdmi_mask_32(x), y + 12);	\
+	} while (0);
+
+#define hdmi_write_l(buff, base, start, count)		\
+	do {						\
+		u8 *ptr = buff;				\
+		int i = 0;				\
+		int a = start;				\
+		do {					\
+			writeb(ptr[i], base + a);	\
+			a += 4;				\
+			i++;				\
+		} while (i <= (count - 1));		\
+	} while (0);
+
+#define hdmi_read_l(buff, base, start, count)		\
+	do {						\
+		u8 *ptr = buff;				\
+		int i = 0;				\
+		int a = start;				\
+		do {					\
+			ptr[i] = readb(base + a);	\
+			a += 4;				\
+			i++;				\
+		} while (i <= (count - 1));		\
+	} while (0);
+
+#define hdmi_bit_set(en, reg, val)			\
+	do {						\
+		if (en)					\
+			reg |= val;			\
+		else					\
+			reg &= ~val;			\
+	} while (0);
+
+enum s5p_hdmi_transmit {
+	HDMI_DO_NOT_TANS,
+	HDMI_TRANS_ONCE,
+	HDMI_TRANS_EVERY_SYNC,
+};
+
+enum s5p_tvout_audio_codec_type {
+	PCM = 1,
+	AC3,
+	MP3,
+	WMA
+};
+
+enum s5p_hdmi_infoframe_type {
+	HDMI_VSI_INFO = 0x81,
+	HDMI_AVI_INFO,
+	HDMI_SPD_INFO,
+	HDMI_AUI_INFO,
+	HDMI_MPG_INFO,
+};
+
+enum s5p_hdmi_color_depth {
+	HDMI_CD_48,
+	HDMI_CD_36,
+	HDMI_CD_30,
+	HDMI_CD_24
+};
+
+enum s5p_hdmi_q_range {
+	HDMI_Q_DEFAULT = 0,
+	HDMI_Q_LIMITED_RANGE,
+	HDMI_Q_FULL_RANGE,
+	HDMI_Q_RESERVED,
+};
+
+enum s5p_hdmi_avi_yq {
+	HDMI_AVI_YQ_LIMITED_RANGE = 0,
+	HDMI_AVI_YQ_FULL_RANGE,
+};
+
+enum s5p_hdmi_interrrupt {
+	HDMI_IRQ_PIN_POLAR_CTL	= 7,
+	HDMI_IRQ_GLOBAL		= 6,
+	HDMI_IRQ_I2S		= 5,
+	HDMI_IRQ_CEC		= 4,
+	HDMI_IRQ_HPD_PLUG	= 3,
+	HDMI_IRQ_HPD_UNPLUG	= 2,
+	HDMI_IRQ_SPDIF		= 1,
+	HDMI_IRQ_HDCP		= 0
+};
+
+enum phy_freq {
+	ePHY_FREQ_25_200,
+	ePHY_FREQ_25_175,
+	ePHY_FREQ_27,
+	ePHY_FREQ_27_027,
+	ePHY_FREQ_54,
+	ePHY_FREQ_54_054,
+	ePHY_FREQ_74_250,
+	ePHY_FREQ_74_176,
+	ePHY_FREQ_148_500,
+	ePHY_FREQ_148_352,
+	ePHY_FREQ_108_108,
+	ePHY_FREQ_72,
+	ePHY_FREQ_25,
+	ePHY_FREQ_65,
+	ePHY_FREQ_108,
+	ePHY_FREQ_162
+};
+
+struct s5p_hdmi_infoframe {
+	enum s5p_hdmi_infoframe_type	type;
+	u8				version;
+	u8				length;
+};
+
+struct s5p_hdmi_o_trans {
+	enum s5p_hdmi_transmit	avi;
+	enum s5p_hdmi_transmit	mpg;
+	enum s5p_hdmi_transmit	spd;
+	enum s5p_hdmi_transmit	gcp;
+	enum s5p_hdmi_transmit	gmp;
+	enum s5p_hdmi_transmit	isrc;
+	enum s5p_hdmi_transmit	acp;
+	enum s5p_hdmi_transmit	aui;
+	enum s5p_hdmi_transmit	acr;
+};
+
+struct s5p_hdmi_o_reg {
+	u8			pxl_fmt;
+	u8			preemble;
+	u8			mode;
+	u8			pxl_limit;
+	u8			dvi;
+};
+
+struct s5p_hdmi_v_frame {
+#ifdef	CONFIG_HDMI_14A_3D
+	u32			vH_Line;
+	u32			vV_Line;
+	u32			vH_SYNC_START;
+	u32			vH_SYNC_END;
+	u32			vV1_Blank;
+	u32			vV2_Blank;
+	u16			vHBlank;
+	u32			VBLANK_F0;
+	u32			VBLANK_F1;
+	u32			vVSYNC_LINE_BEF_1;
+	u32			vVSYNC_LINE_BEF_2;
+	u32			vVSYNC_LINE_AFT_1;
+	u32			vVSYNC_LINE_AFT_2;
+	u32			vVSYNC_LINE_AFT_PXL_1;
+	u32			vVSYNC_LINE_AFT_PXL_2;
+	u32			vVACT_SPACE_1;
+	u32			vVACT_SPACE_2;
+	u8			Hsync_polarity;
+	u8			Vsync_polarity;
+	u8			interlaced;
+	u8			vAVI_VIC;
+	u8			vAVI_VIC_16_9;
+	u8			repetition;
+#else
+	u8			vic;
+	u8			vic_16_9;
+	u8			repetition;
+	u8			polarity;
+	u8			i_p;
+
+	u16			h_active;
+	u16			v_active;
+
+	u16			h_total;
+	u16			h_blank;
+
+	u16			v_total;
+	u16			v_blank;
+#endif
+	enum phy_freq		pixel_clock;
+};
+
+enum s5p_hdmi_audio_type {
+	HDMI_GENERIC_AUDIO,
+	HDMI_60958_AUDIO,
+	HDMI_DVD_AUDIO,
+	HDMI_SUPER_AUDIO,
+};
+
+struct s5p_hdmi_audio {
+	enum s5p_hdmi_audio_type	type;
+	u32				freq;
+	u32				bit;
+	u32				channel;
+
+	u8				on;
+};
+
+struct s5p_hdmi_tg_sync {
+	u16			begin;
+	u16			end;
+};
+
+struct s5p_hdmi_v_format {
+	struct s5p_hdmi_v_frame	frame;
+
+#ifdef	CONFIG_HDMI_14A_3D
+	u16	tg_H_FSZ;
+	u16	tg_HACT_ST;
+	u16	tg_HACT_SZ;
+	u16	tg_V_FSZ;
+	u16	tg_VSYNC;
+	u16	tg_VSYNC2;
+	u16	tg_VACT_ST;
+	u16	tg_VACT_SZ;
+	u16	tg_FIELD_CHG;
+	u16	tg_VACT_ST2;
+	u16	tg_VACT_ST3;
+	u16	tg_VACT_ST4;
+	u16	tg_VSYNC_TOP_HDMI;
+	u16	tg_VSYNC_BOT_HDMI;
+	u16	tg_FIELD_TOP_HDMI;
+	u16	tg_FIELD_BOT_HDMI;
+#else
+	struct s5p_hdmi_tg_sync	h_sync;
+	struct s5p_hdmi_tg_sync	v_sync_top;
+	struct s5p_hdmi_tg_sync	v_sync_bottom;
+	struct s5p_hdmi_tg_sync	v_sync_h_pos;
+
+	struct s5p_hdmi_tg_sync	v_blank_f;
+#endif
+	u8			mhl_hsync;
+	u8			mhl_vsync;
+};
+
+extern int s5p_hdmi_phy_power(bool on);
+extern s32 s5p_hdmi_phy_config(
+		enum phy_freq freq, enum s5p_hdmi_color_depth cd);
+
+extern void s5p_hdmi_set_gcp(enum s5p_hdmi_color_depth depth, u8 *gcp);
+extern void s5p_hdmi_reg_acr(u8 *acr);
+extern void s5p_hdmi_reg_asp(u8 *asp, struct s5p_hdmi_audio *audio);
+extern void s5p_hdmi_reg_gcp(u8 i_p, u8 *gcp);
+extern void s5p_hdmi_reg_acp(u8 *header, u8 *acp);
+extern void s5p_hdmi_reg_isrc(u8 *isrc1, u8 *isrc2);
+extern void s5p_hdmi_reg_gmp(u8 *gmp);
+#ifdef CONFIG_HDMI_14A_3D
+extern void s5p_hdmi_reg_infoframe(
+	struct s5p_hdmi_infoframe *info, u8 *data, u8 type_3D);
+extern void s5p_hdmi_reg_tg(struct s5p_hdmi_v_format *v);
+#else
+extern void s5p_hdmi_reg_infoframe(struct s5p_hdmi_infoframe *info, u8 *data);
+extern void s5p_hdmi_reg_tg(struct s5p_hdmi_v_frame *frame);
+#endif
+extern void s5p_hdmi_reg_v_timing(struct s5p_hdmi_v_format *v);
+#ifdef CONFIG_HDMI_14A_3D
+extern void s5p_hdmi_reg_bluescreen_clr(u16 b, u16 g, u16 r);
+#else
+extern void s5p_hdmi_reg_bluescreen_clr(u8 cb_b, u8 y_g, u8 cr_r);
+#endif
+extern void s5p_hdmi_reg_bluescreen(bool en);
+extern void s5p_hdmi_reg_clr_range(u8 y_min, u8 y_max, u8 c_min, u8 c_max);
+extern void s5p_hdmi_reg_tg_cmd(bool time, bool bt656, bool tg);
+extern void s5p_hdmi_reg_enable(bool en);
+extern u8 s5p_hdmi_reg_intc_status(void);
+extern u8 s5p_hdmi_reg_intc_get_enabled(void);
+extern void s5p_hdmi_reg_intc_clear_pending(enum s5p_hdmi_interrrupt intr);
+extern void s5p_hdmi_reg_sw_hpd_enable(bool enable);
+extern void s5p_hdmi_reg_set_hpd_onoff(bool on_off);
+extern u8 s5p_hdmi_reg_get_hpd_status(void);
+extern void s5p_hdmi_reg_hpd_gen(void);
+extern int s5p_hdmi_reg_intc_set_isr(irqreturn_t (*isr)(int, void *), u8 num);
+extern void s5p_hdmi_reg_intc_enable(enum s5p_hdmi_interrrupt intr, u8 en);
+#ifdef CONFIG_HDMI_EARJACK_MUTE
+extern bool hdmi_audio_ext;
+#endif
+extern void s5p_hdmi_reg_audio_enable(u8 en);
+extern int s5p_hdmi_audio_init(
+		enum s5p_tvout_audio_codec_type audio_codec,
+		u32 sample_rate, u32 bits, u32 frame_size_code,
+		struct s5p_hdmi_audio *audio);
+extern irqreturn_t s5p_hdmi_irq(int irq, void *dev_id);
+extern void s5p_hdmi_init(void __iomem *hdmi_addr);
+extern void s5p_hdmi_phy_init(void __iomem *hdmi_phy_addr);
+extern void s5p_hdmi_reg_output(struct s5p_hdmi_o_reg *reg);
+extern void s5p_hdmi_reg_packet_trans(struct s5p_hdmi_o_trans *trans);
+extern void s5p_hdmi_reg_mute(bool en);
+
+
+
+
+
+/*****************************************************************************
+ * for SDO
+ ****************************************************************************/
+#ifdef CONFIG_ANALOG_TVENC
+
+enum s5p_sdo_level {
+	SDO_LEVEL_0IRE,
+	SDO_LEVEL_75IRE
+};
+
+enum s5p_sdo_vsync_ratio {
+	SDO_VTOS_RATIO_10_4,
+	SDO_VTOS_RATIO_7_3
+};
+
+enum s5p_sdo_order {
+	SDO_O_ORDER_COMPONENT_RGB_PRYPB,
+	SDO_O_ORDER_COMPONENT_RBG_PRPBY,
+	SDO_O_ORDER_COMPONENT_BGR_PBYPR,
+	SDO_O_ORDER_COMPONENT_BRG_PBPRY,
+	SDO_O_ORDER_COMPONENT_GRB_YPRPB,
+	SDO_O_ORDER_COMPONENT_GBR_YPBPR,
+	SDO_O_ORDER_COMPOSITE_CVBS_Y_C,
+	SDO_O_ORDER_COMPOSITE_CVBS_C_Y,
+	SDO_O_ORDER_COMPOSITE_Y_C_CVBS,
+	SDO_O_ORDER_COMPOSITE_Y_CVBS_C,
+	SDO_O_ORDER_COMPOSITE_C_CVBS_Y,
+	SDO_O_ORDER_COMPOSITE_C_Y_CVBS
+};
+
+enum s5p_sdo_sync_sig_pin {
+	SDO_SYNC_SIG_NO,
+	SDO_SYNC_SIG_YG,
+	SDO_SYNC_SIG_ALL
+};
+
+enum s5p_sdo_closed_caption_type {
+	SDO_NO_INS,
+	SDO_INS_1,
+	SDO_INS_2,
+	SDO_INS_OTHERS
+};
+
+enum s5p_sdo_525_copy_permit {
+	SDO_525_COPY_PERMIT,
+	SDO_525_ONECOPY_PERMIT,
+	SDO_525_NOCOPY_PERMIT
+};
+
+enum s5p_sdo_525_mv_psp {
+	SDO_525_MV_PSP_OFF,
+	SDO_525_MV_PSP_ON_2LINE_BURST,
+	SDO_525_MV_PSP_ON_BURST_OFF,
+	SDO_525_MV_PSP_ON_4LINE_BURST,
+};
+
+enum s5p_sdo_525_copy_info {
+	SDO_525_COPY_INFO,
+	SDO_525_DEFAULT,
+};
+
+enum s5p_sdo_525_aspect_ratio {
+	SDO_525_4_3_NORMAL,
+	SDO_525_16_9_ANAMORPIC,
+	SDO_525_4_3_LETTERBOX
+};
+
+enum s5p_sdo_625_subtitles {
+	SDO_625_NO_OPEN_SUBTITLES,
+	SDO_625_INACT_OPEN_SUBTITLES,
+	SDO_625_OUTACT_OPEN_SUBTITLES
+};
+
+enum s5p_sdo_625_camera_film {
+	SDO_625_CAMERA,
+	SDO_625_FILM
+};
+
+enum s5p_sdo_625_color_encoding {
+	SDO_625_NORMAL_PAL,
+	SDO_625_MOTION_ADAPTIVE_COLORPLUS
+};
+
+enum s5p_sdo_625_aspect_ratio {
+	SDO_625_4_3_FULL_576,
+	SDO_625_14_9_LETTERBOX_CENTER_504,
+	SDO_625_14_9_LETTERBOX_TOP_504,
+	SDO_625_16_9_LETTERBOX_CENTER_430,
+	SDO_625_16_9_LETTERBOX_TOP_430,
+	SDO_625_16_9_LETTERBOX_CENTER,
+	SDO_625_14_9_FULL_CENTER_576,
+	SDO_625_16_9_ANAMORPIC_576
+};
+
+struct s5p_sdo_cvbs_compensation {
+	bool cvbs_color_compen;
+	u32 y_lower_mid;
+	u32 y_bottom;
+	u32 y_top;
+	u32 y_upper_mid;
+	u32 radius;
+};
+
+struct s5p_sdo_bright_hue_saturation {
+	bool bright_hue_sat_adj;
+	u32 gain_brightness;
+	u32 offset_brightness;
+	u32 gain0_cb_hue_sat;
+	u32 gain1_cb_hue_sat;
+	u32 gain0_cr_hue_sat;
+	u32 gain1_cr_hue_sat;
+	u32 offset_cb_hue_sat;
+	u32 offset_cr_hue_sat;
+};
+
+struct s5p_sdo_525_data {
+	bool				analog_on;
+	enum s5p_sdo_525_copy_permit	copy_permit;
+	enum s5p_sdo_525_mv_psp		mv_psp;
+	enum s5p_sdo_525_copy_info	copy_info;
+	enum s5p_sdo_525_aspect_ratio	display_ratio;
+};
+
+struct s5p_sdo_625_data {
+	bool				surround_sound;
+	bool				copyright;
+	bool				copy_protection;
+	bool				text_subtitles;
+	enum s5p_sdo_625_subtitles	open_subtitles;
+	enum s5p_sdo_625_camera_film	camera_film;
+	enum s5p_sdo_625_color_encoding	color_encoding;
+	bool				helper_signal;
+	enum s5p_sdo_625_aspect_ratio	display_ratio;
+};
+
+extern int s5p_sdo_set_video_scale_cfg(
+		enum s5p_sdo_level composite_level,
+		enum s5p_sdo_vsync_ratio composite_ratio);
+extern int s5p_sdo_set_vbi(
+		bool wss_cvbs, enum s5p_sdo_closed_caption_type caption_cvbs);
+extern void s5p_sdo_set_offset_gain(u32 offset, u32 gain);
+extern void s5p_sdo_set_delay(
+		u32 delay_y, u32 offset_video_start, u32 offset_video_end);
+extern void s5p_sdo_set_schlock(bool color_sucarrier_pha_adj);
+extern void s5p_sdo_set_brightness_hue_saturation(
+		struct s5p_sdo_bright_hue_saturation bri_hue_sat);
+extern void s5p_sdo_set_cvbs_color_compensation(
+		struct s5p_sdo_cvbs_compensation cvbs_comp);
+extern void s5p_sdo_set_component_porch(
+		u32 back_525, u32 front_525, u32 back_625, u32 front_625);
+extern void s5p_sdo_set_ch_xtalk_cancel_coef(u32 coeff2, u32 coeff1);
+extern void s5p_sdo_set_closed_caption(u32 display_cc, u32 non_display_cc);
+
+extern int s5p_sdo_set_wss525_data(struct s5p_sdo_525_data wss525);
+extern int s5p_sdo_set_wss625_data(struct s5p_sdo_625_data wss625);
+extern int s5p_sdo_set_cgmsa525_data(struct s5p_sdo_525_data cgmsa525);
+extern int s5p_sdo_set_cgmsa625_data(struct s5p_sdo_625_data cgmsa625);
+extern int s5p_sdo_set_display_mode(
+		enum s5p_tvout_disp_mode disp_mode, enum s5p_sdo_order order);
+extern void s5p_sdo_clock_on(bool on);
+extern void s5p_sdo_dac_on(bool on);
+extern void s5p_sdo_sw_reset(bool active);
+extern void s5p_sdo_set_interrupt_enable(bool vsync_intc_en);
+extern void s5p_sdo_clear_interrupt_pending(void);
+extern void s5p_sdo_init(void __iomem *addr);
+#endif
+
+/*****************************************************************************
+ * for VP
+ ****************************************************************************/
+enum s5p_vp_field {
+	VP_TOP_FIELD,
+	VP_BOTTOM_FIELD
+};
+
+enum s5p_vp_line_eq {
+	VP_LINE_EQ_0,
+	VP_LINE_EQ_1,
+	VP_LINE_EQ_2,
+	VP_LINE_EQ_3,
+	VP_LINE_EQ_4,
+	VP_LINE_EQ_5,
+	VP_LINE_EQ_6,
+	VP_LINE_EQ_7,
+	VP_LINE_EQ_DEFAULT
+};
+
+enum s5p_vp_mem_type {
+	VP_YUV420_NV12,
+	VP_YUV420_NV21
+};
+
+enum s5p_vp_mem_mode {
+	VP_LINEAR_MODE,
+	VP_2D_TILE_MODE
+};
+
+enum s5p_vp_chroma_expansion {
+	VP_C_TOP,
+	VP_C_TOP_BOTTOM
+};
+
+enum s5p_vp_pxl_rate {
+	VP_PXL_PER_RATE_1_1,
+	VP_PXL_PER_RATE_1_2,
+	VP_PXL_PER_RATE_1_3,
+	VP_PXL_PER_RATE_1_4
+};
+
+enum s5p_vp_sharpness_control {
+	VP_SHARPNESS_NO,
+	VP_SHARPNESS_MIN,
+	VP_SHARPNESS_MOD,
+	VP_SHARPNESS_MAX
+};
+
+enum s5p_vp_csc_type {
+	VP_CSC_SD_HD,
+	VP_CSC_HD_SD
+};
+
+enum s5p_vp_csc_coeff {
+	VP_CSC_Y2Y_COEF,
+	VP_CSC_CB2Y_COEF,
+	VP_CSC_CR2Y_COEF,
+	VP_CSC_Y2CB_COEF,
+	VP_CSC_CB2CB_COEF,
+	VP_CSC_CR2CB_COEF,
+	VP_CSC_Y2CR_COEF,
+	VP_CSC_CB2CR_COEF,
+	VP_CSC_CR2CR_COEF
+};
+
+
+extern void s5p_vp_set_poly_filter_coef_default(
+		u32 src_width, u32 src_height,
+		u32 dst_width, u32 dst_height, bool ipc_2d);
+extern void s5p_vp_set_field_id(enum s5p_vp_field mode);
+extern int s5p_vp_set_top_field_address(u32 top_y_addr, u32 top_c_addr);
+extern int s5p_vp_set_bottom_field_address(
+		u32 bottom_y_addr, u32 bottom_c_addr);
+extern int s5p_vp_set_img_size(u32 img_width, u32 img_height);
+extern void s5p_vp_set_src_position(
+		u32 src_off_x, u32 src_x_fract_step, u32 src_off_y);
+extern void s5p_vp_set_dest_position(u32 dst_off_x, u32 dst_off_y);
+extern void s5p_vp_set_src_dest_size(
+		u32 src_width, u32 src_height,
+		u32 dst_width, u32 dst_height, bool ipc_2d);
+extern void s5p_vp_set_op_mode(
+		bool line_skip,
+		enum s5p_vp_mem_type mem_type,
+		enum s5p_vp_mem_mode mem_mode,
+		enum s5p_vp_chroma_expansion chroma_exp,
+		bool auto_toggling);
+extern void s5p_vp_set_pixel_rate_control(enum s5p_vp_pxl_rate rate);
+extern void s5p_vp_set_endian(enum s5p_tvout_endian endian);
+extern void s5p_vp_set_bypass_post_process(bool bypass);
+extern void s5p_vp_set_saturation(u32 sat);
+extern void s5p_vp_set_sharpness(
+		u32 th_h_noise,	enum s5p_vp_sharpness_control sharpness);
+extern void s5p_vp_set_brightness_contrast(u16 b, u8 c);
+extern void s5p_vp_set_brightness_offset(u32 offset);
+extern int s5p_vp_set_brightness_contrast_control(
+		enum s5p_vp_line_eq eq_num, u32 intc, u32 slope);
+extern void s5p_vp_set_csc_control(bool sub_y_offset_en, bool csc_en);
+extern int s5p_vp_set_csc_coef(enum s5p_vp_csc_coeff csc_coeff, u32 coeff);
+extern int s5p_vp_set_csc_coef_default(enum s5p_vp_csc_type csc_type);
+extern int s5p_vp_update(void);
+extern int s5p_vp_get_update_status(void);
+extern void s5p_vp_sw_reset(void);
+extern int s5p_vp_start(void);
+extern int s5p_vp_stop(void);
+extern void s5p_vp_init(void __iomem *addr);
+
+/*****************************************************************************
+ * for CEC
+ ****************************************************************************/
+enum cec_state {
+	STATE_RX,
+	STATE_TX,
+	STATE_DONE,
+	STATE_ERROR
+};
+
+struct cec_rx_struct {
+	spinlock_t lock;
+	wait_queue_head_t waitq;
+	atomic_t state;
+	u8 *buffer;
+	unsigned int size;
+};
+
+struct cec_tx_struct {
+	wait_queue_head_t waitq;
+	atomic_t state;
+};
+
+extern struct cec_rx_struct cec_rx_struct;
+extern struct cec_tx_struct cec_tx_struct;
+
+void s5p_cec_set_divider(void);
+void s5p_cec_enable_rx(void);
+void s5p_cec_mask_rx_interrupts(void);
+void s5p_cec_unmask_rx_interrupts(void);
+void s5p_cec_mask_tx_interrupts(void);
+void s5p_cec_unmask_tx_interrupts(void);
+void s5p_cec_reset(void);
+void s5p_cec_tx_reset(void);
+void s5p_cec_rx_reset(void);
+void s5p_cec_threshold(void);
+void s5p_cec_set_tx_state(enum cec_state state);
+void s5p_cec_set_rx_state(enum cec_state state);
+void s5p_cec_copy_packet(char *data, size_t count);
+void s5p_cec_set_addr(u32 addr);
+u32 s5p_cec_get_status(void);
+void s5p_clr_pending_tx(void);
+void s5p_clr_pending_rx(void);
+void s5p_cec_get_rx_buf(u32 size, u8 *buffer);
+int __init s5p_cec_mem_probe(struct platform_device *pdev);
+
+
+
+/*****************************************************************************
+ * for HDCP
+ ****************************************************************************/
+extern int s5p_hdcp_encrypt_stop(bool on);
+extern int __init s5p_hdcp_init(void);
+extern int s5p_hdcp_start(void);
+extern int s5p_hdcp_stop(void);
+
+/****************************************
+ * Definitions for sdo ctrl class
+ ***************************************/
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#define BUSFREQ_400MHZ	400200
+#define BUSFREQ_133MHZ	133133
+#endif
+
+#ifdef CONFIG_ANALOG_TVENC
+
+enum {
+	SDO_PCLK = 0,
+	SDO_MUX,
+	SDO_NO_OF_CLK
+};
+
+struct s5p_sdo_vscale_cfg {
+	enum s5p_sdo_level		composite_level;
+	enum s5p_sdo_vsync_ratio	composite_ratio;
+};
+
+struct s5p_sdo_vbi {
+	bool wss_cvbs;
+	enum s5p_sdo_closed_caption_type caption_cvbs;
+};
+
+struct s5p_sdo_offset_gain {
+	u32 offset;
+	u32 gain;
+};
+
+struct s5p_sdo_delay {
+	u32 delay_y;
+	u32 offset_video_start;
+	u32 offset_video_end;
+};
+
+struct s5p_sdo_component_porch {
+	u32 back_525;
+	u32 front_525;
+	u32 back_625;
+	u32 front_625;
+};
+
+struct s5p_sdo_ch_xtalk_cancellat_coeff {
+	u32 coeff1;
+	u32 coeff2;
+};
+
+struct s5p_sdo_closed_caption {
+	u32 display_cc;
+	u32 nondisplay_cc;
+};
+
+#endif
+
+
+
+/****************************************
+ * Definitions for hdmi ctrl class
+ ***************************************/
+
+#define AVI_SAME_WITH_PICTURE_AR	(0x1<<3)
+
+enum {
+	HDMI_PCLK = 0,
+	HDMI_MUX,
+	HDMI_NO_OF_CLK
+};
+
+enum {
+	HDMI = 0,
+	HDMI_PHY,
+	HDMI_NO_OF_MEM_RES
+};
+
+enum s5p_hdmi_pic_aspect {
+	HDMI_PIC_RATIO_4_3	= 1,
+	HDMI_PIC_RATIO_16_9	= 2
+};
+
+enum s5p_hdmi_colorimetry {
+	HDMI_CLRIMETRY_NO	= 0x00,
+	HDMI_CLRIMETRY_601	= 0x40,
+	HDMI_CLRIMETRY_709	= 0x80,
+	HDMI_CLRIMETRY_X_VAL	= 0xc0,
+};
+
+enum s5p_hdmi_v_mode {
+	v640x480p_60Hz,
+	v720x480p_60Hz,
+	v1280x720p_60Hz,
+	v1920x1080i_60Hz,
+	v720x480i_60Hz,
+	v720x240p_60Hz,
+	v2880x480i_60Hz,
+	v2880x240p_60Hz,
+	v1440x480p_60Hz,
+	v1920x1080p_60Hz,
+	v720x576p_50Hz,
+	v1280x720p_50Hz,
+	v1920x1080i_50Hz,
+	v720x576i_50Hz,
+	v720x288p_50Hz,
+	v2880x576i_50Hz,
+	v2880x288p_50Hz,
+	v1440x576p_50Hz,
+	v1920x1080p_50Hz,
+	v1920x1080p_24Hz,
+	v1920x1080p_25Hz,
+	v1920x1080p_30Hz,
+	v2880x480p_60Hz,
+	v2880x576p_50Hz,
+	v1920x1080i_50Hz_1250,
+	v1920x1080i_100Hz,
+	v1280x720p_100Hz,
+	v720x576p_100Hz,
+	v720x576i_100Hz,
+	v1920x1080i_120Hz,
+	v1280x720p_120Hz,
+	v720x480p_120Hz,
+	v720x480i_120Hz,
+	v720x576p_200Hz,
+	v720x576i_200Hz,
+	v720x480p_240Hz,
+	v720x480i_240Hz,
+	v720x480p_59Hz,
+	v1280x720p_59Hz,
+	v1920x1080i_59Hz,
+	v1920x1080p_59Hz,
+#ifdef CONFIG_HDMI_14A_3D
+	v1280x720p_60Hz_SBS_HALF,
+	v1280x720p_59Hz_SBS_HALF,
+	v1280x720p_50Hz_TB,
+	v1920x1080p_24Hz_TB,
+	v1920x1080p_23Hz_TB,
+#endif
+};
+
+#ifdef CONFIG_HDMI_14A_3D
+struct s5p_hdmi_bluescreen {
+	bool	enable;
+	u16	b;
+	u16	g;
+	u16	r;
+};
+#else
+struct s5p_hdmi_bluescreen {
+	bool	enable;
+	u8	cb_b;
+	u8	y_g;
+	u8	cr_r;
+};
+#endif
+
+struct s5p_hdmi_packet {
+	u8				acr[7];
+	u8				asp[7];
+	u8				gcp[7];
+	u8				acp[28];
+	u8				isrc1[16];
+	u8				isrc2[16];
+	u8				obas[7];
+	u8				dst[28];
+	u8				gmp[28];
+
+	u8				spd_vendor[8];
+	u8				spd_product[16];
+
+	u8				vsi[27];
+	u8				avi[27];
+	u8				spd[27];
+	u8				aui[27];
+	u8				mpg[27];
+
+	struct s5p_hdmi_infoframe	vsi_info;
+	struct s5p_hdmi_infoframe	avi_info;
+	struct s5p_hdmi_infoframe	spd_info;
+	struct s5p_hdmi_infoframe	aui_info;
+	struct s5p_hdmi_infoframe	mpg_info;
+
+	u8				h_asp[3];
+	u8				h_acp[3];
+	u8				h_isrc[3];
+};
+
+struct s5p_hdmi_color_range {
+	u8	y_min;
+	u8	y_max;
+	u8	c_min;
+	u8	c_max;
+};
+
+struct s5p_hdmi_tg {
+	bool correction_en;
+	bool bt656_en;
+};
+
+struct s5p_hdmi_video {
+	struct s5p_hdmi_color_range	color_r;
+	enum s5p_hdmi_pic_aspect	aspect;
+	enum s5p_hdmi_colorimetry	colorimetry;
+	enum s5p_hdmi_color_depth	depth;
+	enum s5p_hdmi_q_range		q_range;
+};
+
+struct s5p_hdmi_o_params {
+	struct s5p_hdmi_o_trans	trans;
+	struct s5p_hdmi_o_reg	reg;
+};
+
+struct s5p_hdmi_ctrl_private_data {
+	u8				vendor[8];
+	u8				product[16];
+
+	enum s5p_tvout_o_mode		out;
+	enum s5p_hdmi_v_mode		mode;
+
+	struct s5p_hdmi_bluescreen	blue_screen;
+	struct s5p_hdmi_packet		packet;
+	struct s5p_hdmi_tg		tg;
+	struct s5p_hdmi_audio		audio;
+	struct s5p_hdmi_video		video;
+
+	bool				hpd_status;
+	bool				hdcp_en;
+
+	bool				av_mute;
+
+	bool				running;
+	char				*pow_name;
+	struct s5p_tvout_clk_info		clk[HDMI_NO_OF_CLK];
+	struct reg_mem_info		reg_mem[HDMI_NO_OF_MEM_RES];
+	struct irq_info			irq;
+};
+
+/****************************************
+ * Definitions for tvif ctrl class
+ ***************************************/
+struct s5p_tvif_ctrl_private_data {
+	enum s5p_tvout_disp_mode	curr_std;
+	enum s5p_tvout_o_mode		curr_if;
+
+	bool				running;
+
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	struct device *bus_dev; /* for BusFreq with Opp */
+#endif
+	struct device *dev; /* hpd device pointer */
+};
+
+#endif /* _SAMSUNG_TVOUT_HW_IF_H_ */
diff --git a/drivers/media/video/samsung/tvout/hw_if/mixer.c b/drivers/media/video/samsung/tvout/hw_if/mixer.c
new file mode 100644
index 0000000..b2753f2
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/mixer.c
@@ -0,0 +1,874 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/mixer.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Mixer raw ftn  file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/sched.h>
+
+#include <mach/regs-mixer.h>
+
+#include "../s5p_tvout_common_lib.h"
+#include "../s5p_tvout_ctrl.h"
+#include "hw_if.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_MIXER_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "\t[MIXER] %s(): " fmt,	\
+			__func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+void __iomem	*mixer_base;
+spinlock_t	lock_mixer;
+
+
+extern int s5p_vp_ctrl_get_src_addr(u32* top_y_addr, u32* top_c_addr);
+int s5p_mixer_set_show(enum s5p_mixer_layer layer, bool show)
+{
+	u32 mxr_config;
+
+	tvout_dbg("%d, %d\n", layer, show);
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		mxr_config = (show) ?
+				(readl(mixer_base + S5P_MXR_CFG) |
+					S5P_MXR_CFG_VIDEO_ENABLE) :
+				(readl(mixer_base + S5P_MXR_CFG) &
+					~S5P_MXR_CFG_VIDEO_ENABLE);
+		break;
+
+	case MIXER_GPR0_LAYER:
+		mxr_config = (show) ?
+				(readl(mixer_base + S5P_MXR_CFG) |
+					S5P_MXR_CFG_GRAPHIC0_ENABLE) :
+				(readl(mixer_base + S5P_MXR_CFG) &
+					~S5P_MXR_CFG_GRAPHIC0_ENABLE);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		mxr_config = (show) ?
+				(readl(mixer_base + S5P_MXR_CFG) |
+					S5P_MXR_CFG_GRAPHIC1_ENABLE) :
+				(readl(mixer_base + S5P_MXR_CFG) &
+					~S5P_MXR_CFG_GRAPHIC1_ENABLE);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	writel(mxr_config, mixer_base + S5P_MXR_CFG);
+
+	return 0;
+}
+
+int s5p_mixer_set_priority(enum s5p_mixer_layer layer, u32 priority)
+{
+	u32 layer_cfg;
+
+	tvout_dbg("%d, %d\n", layer, priority);
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		layer_cfg = S5P_MXR_LAYER_CFG_VID_PRIORITY_CLR(
+				readl(mixer_base + S5P_MXR_LAYER_CFG)) |
+				S5P_MXR_LAYER_CFG_VID_PRIORITY(priority);
+		break;
+
+	case MIXER_GPR0_LAYER:
+		layer_cfg = S5P_MXR_LAYER_CFG_GRP0_PRIORITY_CLR(
+				readl(mixer_base + S5P_MXR_LAYER_CFG)) |
+				S5P_MXR_LAYER_CFG_GRP0_PRIORITY(priority);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		layer_cfg = S5P_MXR_LAYER_CFG_GRP1_PRIORITY_CLR(
+				readl(mixer_base + S5P_MXR_LAYER_CFG)) |
+				S5P_MXR_LAYER_CFG_GRP1_PRIORITY(priority);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	writel(layer_cfg, mixer_base + S5P_MXR_LAYER_CFG);
+
+	return 0;
+}
+
+void s5p_mixer_set_pre_mul_mode(enum s5p_mixer_layer layer, bool enable)
+{
+	u32 reg;
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG);
+
+		if (enable)
+			reg |= S5P_MXR_PRE_MUL_MODE;
+		else
+			reg &= ~S5P_MXR_PRE_MUL_MODE;
+
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		break;
+	case MIXER_GPR1_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG);
+
+		if (enable)
+			reg |= S5P_MXR_PRE_MUL_MODE;
+		else
+			reg &= ~S5P_MXR_PRE_MUL_MODE;
+
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		break;
+	case MIXER_VIDEO_LAYER:
+		break;
+	}
+}
+
+int s5p_mixer_set_pixel_blend(enum s5p_mixer_layer layer, bool enable)
+{
+	u32 temp_reg;
+
+	tvout_dbg("%d, %d\n", layer, enable);
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG)
+			& (~S5P_MXR_PIXEL_BLEND_ENABLE) ;
+
+		if (enable)
+			temp_reg |= S5P_MXR_PIXEL_BLEND_ENABLE;
+		else
+			temp_reg |= S5P_MXR_PIXEL_BLEND_DISABLE;
+
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG)
+			& (~S5P_MXR_PIXEL_BLEND_ENABLE) ;
+
+		if (enable)
+			temp_reg |= S5P_MXR_PIXEL_BLEND_ENABLE;
+		else
+			temp_reg |= S5P_MXR_PIXEL_BLEND_DISABLE;
+
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_set_layer_blend(enum s5p_mixer_layer layer, bool enable)
+{
+	u32 temp_reg;
+
+	tvout_dbg("%d, %d\n", layer, enable);
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_VIDEO_CFG)
+			   & (~S5P_MXR_VIDEO_CFG_BLEND_EN) ;
+
+		if (enable)
+			temp_reg |= S5P_MXR_VIDEO_CFG_BLEND_EN;
+		else
+			temp_reg |= S5P_MXR_VIDEO_CFG_BLEND_DIS;
+
+		writel(temp_reg, mixer_base + S5P_MXR_VIDEO_CFG);
+		break;
+
+	case MIXER_GPR0_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG)
+			   & (~S5P_MXR_WIN_BLEND_ENABLE) ;
+
+		if (enable)
+			temp_reg |= S5P_MXR_WIN_BLEND_ENABLE;
+		else
+			temp_reg |= S5P_MXR_WIN_BLEND_DISABLE;
+
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG)
+			   & (~S5P_MXR_WIN_BLEND_ENABLE) ;
+
+		if (enable)
+			temp_reg |= S5P_MXR_WIN_BLEND_ENABLE;
+		else
+			temp_reg |= S5P_MXR_WIN_BLEND_DISABLE;
+
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_set_alpha(enum s5p_mixer_layer layer, u32 alpha)
+{
+	u32 temp_reg;
+
+	tvout_dbg("%d, %d\n", layer, alpha);
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_VIDEO_CFG)
+			   & (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
+		temp_reg |= S5P_MXR_VIDEO_CFG_ALPHA_VALUE(alpha);
+		writel(temp_reg, mixer_base + S5P_MXR_VIDEO_CFG);
+		break;
+
+	case MIXER_GPR0_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG)
+			   & (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
+		temp_reg |= S5P_MXR_GRP_ALPHA_VALUE(alpha);
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG)
+			   & (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
+		temp_reg |= S5P_MXR_GRP_ALPHA_VALUE(alpha);
+		writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_set_grp_base_address(enum s5p_mixer_layer layer, u32 base_addr)
+{
+	tvout_dbg("%d, 0x%x\n", layer, base_addr);
+
+	if (S5P_MXR_GRP_ADDR_ILLEGAL(base_addr)) {
+		tvout_err("address is not word align = %d\n", base_addr);
+		return -1;
+	}
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		writel(S5P_MXR_GPR_BASE(base_addr),
+			mixer_base + S5P_MXR_GRAPHIC0_BASE);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		writel(S5P_MXR_GPR_BASE(base_addr),
+			mixer_base + S5P_MXR_GRAPHIC1_BASE);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_set_grp_layer_dst_pos(enum s5p_mixer_layer layer,
+					u32 dst_offs_x, u32 dst_offs_y)
+{
+	tvout_dbg("%d, %d, %d\n", layer, dst_offs_x, dst_offs_y);
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		writel(S5P_MXR_GRP_DESTX(dst_offs_x) |
+			S5P_MXR_GRP_DESTY(dst_offs_y),
+			mixer_base + S5P_MXR_GRAPHIC0_DXY);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		writel(S5P_MXR_GRP_DESTX(dst_offs_x) |
+			S5P_MXR_GRP_DESTY(dst_offs_y),
+			mixer_base + S5P_MXR_GRAPHIC1_DXY);
+		break;
+
+	default:
+		tvout_err("invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_set_grp_layer_src_pos(enum s5p_mixer_layer layer, u32 src_offs_x,
+			u32 src_offs_y, u32 span, u32 width, u32 height)
+{
+	tvout_dbg("%d, %d, %d, %d, %d, %d\n", layer, span, width, height,
+		 src_offs_x, src_offs_y);
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		writel(S5P_MXR_GRP_SPAN(span),
+			mixer_base + S5P_MXR_GRAPHIC0_SPAN);
+		writel(S5P_MXR_GRP_WIDTH(width) | S5P_MXR_GRP_HEIGHT(height),
+		       mixer_base + S5P_MXR_GRAPHIC0_WH);
+		writel(S5P_MXR_GRP_STARTX(src_offs_x) |
+			S5P_MXR_GRP_STARTY(src_offs_y),
+		       mixer_base + S5P_MXR_GRAPHIC0_SXY);
+		break;
+
+	case MIXER_GPR1_LAYER:
+		writel(S5P_MXR_GRP_SPAN(span),
+			mixer_base + S5P_MXR_GRAPHIC1_SPAN);
+		writel(S5P_MXR_GRP_WIDTH(width) | S5P_MXR_GRP_HEIGHT(height),
+		       mixer_base + S5P_MXR_GRAPHIC1_WH);
+		writel(S5P_MXR_GRP_STARTX(src_offs_x) |
+			S5P_MXR_GRP_STARTY(src_offs_y),
+		       mixer_base + S5P_MXR_GRAPHIC1_SXY);
+		break;
+
+	default:
+		tvout_err(" invalid layer parameter = %d\n", layer);
+		return -1;
+	}
+
+	return 0;
+}
+
+void s5p_mixer_set_bg_color(enum s5p_mixer_bg_color_num colornum,
+				u32 color_y, u32 color_cb, u32 color_cr)
+{
+	u32 reg_value;
+
+	reg_value = S5P_MXR_BG_COLOR_Y(color_y) |
+			S5P_MXR_BG_COLOR_CB(color_cb) |
+			S5P_MXR_BG_COLOR_CR(color_cr);
+
+	switch (colornum) {
+	case MIXER_BG_COLOR_0:
+		writel(reg_value, mixer_base + S5P_MXR_BG_COLOR0);
+		break;
+
+	case MIXER_BG_COLOR_1:
+		writel(reg_value, mixer_base + S5P_MXR_BG_COLOR1);
+		break;
+
+	case MIXER_BG_COLOR_2:
+		writel(reg_value, mixer_base + S5P_MXR_BG_COLOR2);
+		break;
+	}
+}
+void s5p_mixer_set_video_limiter(u32 y_min, u32 y_max,
+		u32 c_min, u32 c_max, bool enable)
+{
+	u32 reg_value;
+
+	reg_value = readl(mixer_base + S5P_MXR_VIDEO_CFG)
+		& (~S5P_MXR_VIDEO_CFG_LIMITER_EN) ;
+
+	if (enable)
+		reg_value |= S5P_MXR_VIDEO_CFG_LIMITER_EN;
+	else
+		reg_value |= S5P_MXR_VIDEO_CFG_LIMITER_DIS;
+
+	writel(reg_value, mixer_base + S5P_MXR_VIDEO_CFG);
+
+	reg_value = S5P_MXR_VIDEO_LIMITER_PARA_Y_UPPER(y_max) |
+		S5P_MXR_VIDEO_LIMITER_PARA_Y_LOWER(y_min) |
+		S5P_MXR_VIDEO_LIMITER_PARA_C_UPPER(c_max) |
+		S5P_MXR_VIDEO_LIMITER_PARA_C_LOWER(c_min);
+
+	writel(reg_value, mixer_base + S5P_MXR_VIDEO_LIMITER_PARA_CFG);
+
+}
+
+void s5p_mixer_init_status_reg(enum s5p_mixer_burst_mode burst,
+				enum s5p_tvout_endian endian)
+{
+	u32 temp_reg = 0;
+
+	temp_reg = S5P_MXR_STATUS_SYNC_ENABLE | S5P_MXR_STATUS_OPERATING;
+
+	switch (burst) {
+	case MIXER_BURST_8:
+		temp_reg |= S5P_MXR_STATUS_8_BURST;
+		break;
+	case MIXER_BURST_16:
+		temp_reg |= S5P_MXR_STATUS_16_BURST;
+		break;
+	}
+
+	switch (endian) {
+	case TVOUT_BIG_ENDIAN:
+		temp_reg |= S5P_MXR_STATUS_BIG_ENDIAN;
+		break;
+	case TVOUT_LITTLE_ENDIAN:
+		temp_reg |= S5P_MXR_STATUS_LITTLE_ENDIAN;
+		break;
+	}
+
+	writel(temp_reg, mixer_base + S5P_MXR_STATUS);
+}
+
+int s5p_mixer_init_display_mode(enum s5p_tvout_disp_mode mode,
+				enum s5p_tvout_o_mode output_mode,
+				enum s5p_mixer_rgb rgb_type)
+{
+	u32 temp_reg = readl(mixer_base + S5P_MXR_CFG);
+
+	tvout_dbg("%d, %d\n", mode, output_mode);
+
+	switch (mode) {
+	case TVOUT_NTSC_M:
+	case TVOUT_NTSC_443:
+		temp_reg &= ~S5P_MXR_CFG_HD;
+		temp_reg &= ~S5P_MXR_CFG_PAL;
+		temp_reg &= S5P_MXR_CFG_INTERLACE;
+		break;
+
+	case TVOUT_PAL_BDGHI:
+	case TVOUT_PAL_M:
+	case TVOUT_PAL_N:
+	case TVOUT_PAL_NC:
+	case TVOUT_PAL_60:
+		temp_reg &= ~S5P_MXR_CFG_HD;
+		temp_reg |= S5P_MXR_CFG_PAL;
+		temp_reg &= S5P_MXR_CFG_INTERLACE;
+		break;
+
+	case TVOUT_480P_60_16_9:
+	case TVOUT_480P_60_4_3:
+	case TVOUT_480P_59:
+		temp_reg &= ~S5P_MXR_CFG_HD;
+		temp_reg &= ~S5P_MXR_CFG_PAL;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+
+	case TVOUT_576P_50_16_9:
+	case TVOUT_576P_50_4_3:
+		temp_reg &= ~S5P_MXR_CFG_HD;
+		temp_reg |= S5P_MXR_CFG_PAL;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+
+	case TVOUT_720P_50:
+	case TVOUT_720P_59:
+	case TVOUT_720P_60:
+		temp_reg |= S5P_MXR_CFG_HD;
+		temp_reg &= ~S5P_MXR_CFG_HD_1080I;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_720P_60_SBS_HALF:
+	case TVOUT_720P_59_SBS_HALF:
+	case TVOUT_720P_50_TB:
+		temp_reg |= S5P_MXR_CFG_HD;
+		temp_reg &= ~S5P_MXR_CFG_HD_1080I;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+#endif
+
+	case TVOUT_1080I_50:
+	case TVOUT_1080I_59:
+	case TVOUT_1080I_60:
+		temp_reg |= S5P_MXR_CFG_HD;
+		temp_reg |= S5P_MXR_CFG_HD_1080I;
+		temp_reg &= S5P_MXR_CFG_INTERLACE;
+		break;
+
+	case TVOUT_1080P_50:
+	case TVOUT_1080P_59:
+	case TVOUT_1080P_60:
+	case TVOUT_1080P_30:
+		temp_reg |= S5P_MXR_CFG_HD;
+		temp_reg |= S5P_MXR_CFG_HD_1080P;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_1080P_24_TB:
+	case TVOUT_1080P_23_TB:
+		temp_reg |= S5P_MXR_CFG_HD;
+		temp_reg |= S5P_MXR_CFG_HD_1080P;
+		temp_reg |= S5P_MXR_CFG_PROGRASSIVE;
+		break;
+#endif
+	default:
+		tvout_err("invalid mode parameter = %d\n", mode);
+		return -1;
+	}
+
+	switch (output_mode) {
+	case TVOUT_COMPOSITE:
+		temp_reg &= S5P_MXR_CFG_TV_OUT;
+		temp_reg &= ~(0x1<<8);
+		temp_reg |= MIXER_YUV444<<8;
+		break;
+
+	case TVOUT_HDMI_RGB:
+	case TVOUT_DVI:
+		temp_reg |= S5P_MXR_CFG_HDMI_OUT;
+		temp_reg &= ~(0x1<<8);
+		temp_reg |= MIXER_RGB888<<8;
+		break;
+
+	case TVOUT_HDMI:
+		temp_reg |= S5P_MXR_CFG_HDMI_OUT;
+		temp_reg &= ~(0x1<<8);
+		temp_reg |= MIXER_YUV444<<8;
+		break;
+
+	default:
+		tvout_err("invalid mode parameter = %d\n", mode);
+		return -1;
+	}
+
+	if (0 <= rgb_type  && rgb_type <= 3)
+		temp_reg |= rgb_type<<9;
+	else
+		printk(KERN_INFO "Wrong rgb type!!\n");
+
+	tvout_dbg(KERN_INFO "Color range RGB Type : %x\n", rgb_type);
+	writel(temp_reg, mixer_base + S5P_MXR_CFG);
+
+	return 0;
+}
+
+void s5p_mixer_scaling(enum s5p_mixer_layer layer,
+		struct s5ptvfb_user_scaling scaling)
+{
+	u32 reg, ver_val = 0, hor_val = 0;
+
+	switch (scaling.ver) {
+	case VERTICAL_X1:
+		ver_val = 0;
+		break;
+	case VERTICAL_X2:
+		ver_val = 1;
+		break;
+	}
+
+	switch (scaling.hor) {
+	case HORIZONTAL_X1:
+		hor_val = 0;
+		break;
+	case HORIZONTAL_X2:
+		hor_val = 1;
+		break;
+	}
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC0_WH);
+		reg |= S5P_MXR_GRP_V_SCALE(ver_val);
+		reg |= S5P_MXR_GRP_H_SCALE(hor_val);
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC0_WH);
+		break;
+	case MIXER_GPR1_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC1_WH);
+		reg |= S5P_MXR_GRP_V_SCALE(ver_val);
+		reg |= S5P_MXR_GRP_H_SCALE(hor_val);
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC1_WH);
+		break;
+	case MIXER_VIDEO_LAYER:
+		break;
+	}
+}
+
+void s5p_mixer_set_color_format(enum s5p_mixer_layer layer,
+	enum s5p_mixer_color_fmt format)
+{
+	u32 reg;
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		reg &= ~(S5P_MXR_EG_COLOR_FORMAT(0xf));
+		reg |= S5P_MXR_EG_COLOR_FORMAT(format);
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		break;
+	case MIXER_GPR1_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		reg &= ~(S5P_MXR_EG_COLOR_FORMAT(0xf));
+		reg |= S5P_MXR_EG_COLOR_FORMAT(format);
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		break;
+	case MIXER_VIDEO_LAYER:
+		break;
+	}
+}
+
+void s5p_mixer_set_chroma_key(enum s5p_mixer_layer layer, bool enabled, u32 key)
+{
+	u32 reg;
+
+	switch (layer) {
+	case MIXER_GPR0_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG);
+
+		if (enabled)
+			reg &= ~S5P_MXR_BLANK_CHANGE_NEW_PIXEL;
+		else
+			reg |= S5P_MXR_BLANK_CHANGE_NEW_PIXEL;
+
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
+		writel(S5P_MXR_GPR_BLANK_COLOR(key),
+			mixer_base + S5P_MXR_GRAPHIC0_BLANK);
+		break;
+	case MIXER_GPR1_LAYER:
+		reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG);
+
+		if (enabled)
+			reg &= ~S5P_MXR_BLANK_CHANGE_NEW_PIXEL;
+		else
+			reg |= S5P_MXR_BLANK_CHANGE_NEW_PIXEL;
+
+		writel(reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
+		writel(S5P_MXR_GPR_BLANK_COLOR(key),
+				mixer_base + S5P_MXR_GRAPHIC1_BLANK);
+		break;
+	case MIXER_VIDEO_LAYER:
+		break;
+	}
+}
+
+void s5p_mixer_init_bg_dither_enable(bool cr_dither_enable,
+					bool cb_dither_enable,
+					bool y_dither_enable)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d\n", cr_dither_enable, cb_dither_enable,
+		y_dither_enable);
+
+	temp_reg = (cr_dither_enable) ?
+		   (temp_reg | S5P_MXR_BG_CR_DIHER_EN) :
+		   (temp_reg & ~S5P_MXR_BG_CR_DIHER_EN);
+	temp_reg = (cb_dither_enable) ?
+		   (temp_reg | S5P_MXR_BG_CB_DIHER_EN) :
+		   (temp_reg & ~S5P_MXR_BG_CB_DIHER_EN);
+	temp_reg = (y_dither_enable) ?
+		   (temp_reg | S5P_MXR_BG_Y_DIHER_EN) :
+		   (temp_reg & ~S5P_MXR_BG_Y_DIHER_EN);
+
+	writel(temp_reg, mixer_base + S5P_MXR_BG_CFG);
+
+}
+
+void s5p_mixer_init_csc_coef_default(enum s5p_mixer_rgb csc_type)
+{
+	tvout_dbg("%d\n", csc_type);
+
+	switch (csc_type) {
+	case MIXER_RGB601_16_235:
+		writel((0 << 30) | (153 << 20) | (300 << 10) | (58 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_Y);
+		writel((936 << 20) | (851 << 10) | (262 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CB);
+		writel((262 << 20) | (805 << 10) | (982 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CR);
+		break;
+
+	case MIXER_RGB601_0_255:
+		writel((1 << 30) | (132 << 20) | (258 << 10) | (50 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_Y);
+		writel((949 << 20) | (876 << 10) | (225 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CB);
+		writel((225 << 20) | (836 << 10) | (988 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CR);
+		break;
+
+	case MIXER_RGB709_16_235:
+		writel((0 << 30) | (109 << 20) | (366 << 10) | (36 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_Y);
+		writel((964 << 20) | (822 << 10) | (216 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CB);
+		writel((262 << 20) | (787 << 10) | (1000 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CR);
+		break;
+
+	case MIXER_RGB709_0_255:
+		writel((1 << 30) | (94 << 20) | (314 << 10) | (32 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_Y);
+		writel((972 << 20) | (851 << 10) | (225 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CB);
+		writel((225 << 20) | (820 << 10) | (1004 << 0),
+			mixer_base + S5P_MXR_CM_COEFF_CR);
+		break;
+
+	default:
+		tvout_err("invalid csc_type parameter = %d\n", csc_type);
+		break;
+	}
+}
+
+void s5p_mixer_start(void)
+{
+	writel((readl(mixer_base + S5P_MXR_STATUS) | S5P_MXR_STATUS_RUN),
+		mixer_base + S5P_MXR_STATUS);
+}
+
+void s5p_mixer_stop(void)
+{
+	u32 reg = readl(mixer_base + S5P_MXR_STATUS);
+
+	reg &= ~S5P_MXR_STATUS_RUN;
+
+	writel(reg, mixer_base + S5P_MXR_STATUS);
+
+	do {
+		reg = readl(mixer_base + S5P_MXR_STATUS);
+	} while (!(reg & S5P_MXR_STATUS_IDLE_MODE));
+}
+
+void s5p_mixer_set_underflow_int_enable(enum s5p_mixer_layer layer, bool en)
+{
+	u32 enable_mask = 0;
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		enable_mask = S5P_MXR_INT_EN_VP_ENABLE;
+		break;
+
+	case MIXER_GPR0_LAYER:
+		enable_mask = S5P_MXR_INT_EN_GRP0_ENABLE;
+		break;
+
+	case MIXER_GPR1_LAYER:
+		enable_mask = S5P_MXR_INT_EN_GRP1_ENABLE;
+		break;
+	}
+
+	if (en) {
+		writel((readl(mixer_base + S5P_MXR_INT_EN) | enable_mask),
+			mixer_base + S5P_MXR_INT_EN);
+	} else {
+		writel((readl(mixer_base + S5P_MXR_INT_EN) & ~enable_mask),
+			mixer_base + S5P_MXR_INT_EN);
+	}
+}
+
+void s5p_mixer_set_vsync_interrupt(bool en)
+{
+	if (en) {
+		writel(S5P_MXR_INT_STATUS_VSYNC_CLEARED, mixer_base +
+			S5P_MXR_INT_STATUS);
+		writel((readl(mixer_base + S5P_MXR_INT_EN) |
+			S5P_MXR_INT_EN_VSYNC_ENABLE),
+			mixer_base + S5P_MXR_INT_EN);
+	} else {
+		writel((readl(mixer_base + S5P_MXR_INT_EN) &
+			~S5P_MXR_INT_EN_VSYNC_ENABLE),
+			mixer_base + S5P_MXR_INT_EN);
+	}
+
+	tvout_dbg("%s mixer VSYNC interrupt.\n", en? "Enable": "Disable");
+}
+
+void s5p_mixer_clear_pend_all(void)
+{
+	writel(S5P_MXR_INT_STATUS_INT_FIRED | S5P_MXR_INT_STATUS_VP_FIRED |
+		S5P_MXR_INT_STATUS_GRP0_FIRED | S5P_MXR_INT_STATUS_GRP1_FIRED,
+			mixer_base + S5P_MXR_INT_STATUS);
+}
+
+irqreturn_t s5p_mixer_irq(int irq, void *dev_id)
+{
+	bool v_i_f;
+	bool g0_i_f;
+	bool g1_i_f;
+	bool mxr_i_f;
+	u32 temp_reg = 0;
+	unsigned long spin_flags;
+	u32 top_y_addr, top_c_addr;
+	int i = 0;
+	unsigned int pre_vp_buff_idx;
+
+	spin_lock_irqsave(&lock_mixer, spin_flags);
+
+	v_i_f = (readl(mixer_base + S5P_MXR_INT_STATUS)
+			& S5P_MXR_INT_STATUS_VP_FIRED) ? true : false;
+	g0_i_f = (readl(mixer_base + S5P_MXR_INT_STATUS)
+			& S5P_MXR_INT_STATUS_GRP0_FIRED) ? true : false;
+	g1_i_f = (readl(mixer_base + S5P_MXR_INT_STATUS)
+			& S5P_MXR_INT_STATUS_GRP1_FIRED) ? true : false;
+	mxr_i_f = (readl(mixer_base + S5P_MXR_INT_STATUS)
+			& S5P_MXR_INT_STATUS_INT_FIRED) ? true : false;
+
+	if (mxr_i_f) {
+		temp_reg |= S5P_MXR_INT_STATUS_INT_FIRED;
+
+		if (v_i_f) {
+			temp_reg |= S5P_MXR_INT_STATUS_VP_FIRED;
+			tvout_dbg("VP fifo under run!!\n");
+		}
+
+		if (g0_i_f) {
+			temp_reg |= S5P_MXR_INT_STATUS_GRP0_FIRED;
+			tvout_dbg("GRP0 fifo under run!!\n");
+		}
+
+		if (g1_i_f) {
+			temp_reg |= S5P_MXR_INT_STATUS_GRP1_FIRED;
+			tvout_dbg("GRP1 fifo under run!!\n");
+		}
+
+		if (!v_i_f && !g0_i_f && !g1_i_f) {
+			writel(S5P_MXR_INT_STATUS_VSYNC_CLEARED,
+				mixer_base + S5P_MXR_INT_STATUS);
+			s5p_vp_ctrl_get_src_addr(&top_y_addr, &top_c_addr);
+
+			pre_vp_buff_idx = s5ptv_vp_buff.vp_access_buff_idx;
+			for (i = 0; i < S5PTV_VP_BUFF_CNT; i++) {
+				if (top_y_addr == s5ptv_vp_buff.vp_buffs[i].phy_base) {
+					s5ptv_vp_buff.vp_access_buff_idx = i;
+					break;
+				}
+			}
+
+			for (i = 0; i < S5PTV_VP_BUFF_CNT - 1; i++) {
+				if (s5ptv_vp_buff.copy_buff_idxs[i]
+					== s5ptv_vp_buff.vp_access_buff_idx) {
+					s5ptv_vp_buff.copy_buff_idxs[i] = pre_vp_buff_idx;
+					break;
+				}
+			}
+			wake_up(&s5ptv_wq);
+		} else {
+			writel(temp_reg, mixer_base + S5P_MXR_INT_STATUS);
+		}
+	}
+	spin_unlock_irqrestore(&lock_mixer, spin_flags);
+
+	return IRQ_HANDLED;
+}
+
+void s5p_mixer_init(void __iomem *addr)
+{
+	mixer_base = addr;
+
+	spin_lock_init(&lock_mixer);
+}
diff --git a/drivers/media/video/samsung/tvout/hw_if/sdo.c b/drivers/media/video/samsung/tvout/hw_if/sdo.c
new file mode 100644
index 0000000..8d6b661
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/sdo.c
@@ -0,0 +1,1122 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/sdo.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Hardware interface functions for SDO (Standard Definition Output)
+ *	- SDO: Analog TV encoder + DAC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-sdo.h>
+
+#include "../s5p_tvout_common_lib.h"
+#include "hw_if.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_SDO_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "\t\t[SDO] %s(): " fmt,	\
+			__func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+void __iomem *sdo_base;
+
+static u32 s5p_sdo_calc_wss_cgms_crc(u32 value)
+{
+	u8 i;
+	u8 cgms[14], crc[6], old_crc;
+	u32 temp_in;
+
+	temp_in = value;
+
+	for (i = 0; i < 14; i++)
+		cgms[i] = (u8)(temp_in >> i) & 0x1;
+
+	/* initialize state */
+	for (i = 0; i < 6; i++)
+		crc[i] = 0x1;
+
+	/* round 20 */
+	for (i = 0; i < 14; i++) {
+		old_crc = crc[0];
+		crc[0] = crc[1];
+		crc[1] = crc[2];
+		crc[2] = crc[3];
+		crc[3] = crc[4];
+		crc[4] = old_crc ^ cgms[i] ^ crc[5];
+		crc[5] = old_crc ^ cgms[i];
+	}
+
+	/* recompose to return crc */
+	temp_in &= 0x3fff;
+
+	for (i = 0; i < 6; i++)
+		temp_in |= ((u32)(crc[i] & 0x1) << i);
+
+	return temp_in;
+}
+
+static int s5p_sdo_set_antialias_filter_coeff_default(
+		enum s5p_sdo_level composite_level,
+		enum s5p_sdo_vsync_ratio composite_ratio)
+{
+	tvout_dbg("%d, %d\n", composite_level, composite_ratio);
+
+	switch (composite_level) {
+	case SDO_LEVEL_0IRE:
+		switch (composite_ratio) {
+		case SDO_VTOS_RATIO_10_4:
+			writel(0x00000000, sdo_base + S5P_SDO_Y3);
+			writel(0x00000000, sdo_base + S5P_SDO_Y4);
+			writel(0x00000000, sdo_base + S5P_SDO_Y5);
+			writel(0x00000000, sdo_base + S5P_SDO_Y6);
+			writel(0x00000000, sdo_base + S5P_SDO_Y7);
+			writel(0x00000000, sdo_base + S5P_SDO_Y8);
+			writel(0x00000000, sdo_base + S5P_SDO_Y9);
+			writel(0x00000000, sdo_base + S5P_SDO_Y10);
+			writel(0x0000029a, sdo_base + S5P_SDO_Y11);
+			writel(0x00000000, sdo_base + S5P_SDO_CB0);
+			writel(0x00000000, sdo_base + S5P_SDO_CB1);
+			writel(0x00000000, sdo_base + S5P_SDO_CB2);
+			writel(0x00000000, sdo_base + S5P_SDO_CB3);
+			writel(0x00000000, sdo_base + S5P_SDO_CB4);
+			writel(0x00000001, sdo_base + S5P_SDO_CB5);
+			writel(0x00000007, sdo_base + S5P_SDO_CB6);
+			writel(0x00000015, sdo_base + S5P_SDO_CB7);
+			writel(0x0000002b, sdo_base + S5P_SDO_CB8);
+			writel(0x00000045, sdo_base + S5P_SDO_CB9);
+			writel(0x00000059, sdo_base + S5P_SDO_CB10);
+			writel(0x00000061, sdo_base + S5P_SDO_CB11);
+			writel(0x00000000, sdo_base + S5P_SDO_CR1);
+			writel(0x00000000, sdo_base + S5P_SDO_CR2);
+			writel(0x00000000, sdo_base + S5P_SDO_CR3);
+			writel(0x00000000, sdo_base + S5P_SDO_CR4);
+			writel(0x00000002, sdo_base + S5P_SDO_CR5);
+			writel(0x0000000a, sdo_base + S5P_SDO_CR6);
+			writel(0x0000001e, sdo_base + S5P_SDO_CR7);
+			writel(0x0000003d, sdo_base + S5P_SDO_CR8);
+			writel(0x00000061, sdo_base + S5P_SDO_CR9);
+			writel(0x0000007a, sdo_base + S5P_SDO_CR10);
+			writel(0x0000008f, sdo_base + S5P_SDO_CR11);
+			break;
+
+		case SDO_VTOS_RATIO_7_3:
+			writel(0x00000000, sdo_base + S5P_SDO_Y0);
+			writel(0x00000000, sdo_base + S5P_SDO_Y1);
+			writel(0x00000000, sdo_base + S5P_SDO_Y2);
+			writel(0x00000000, sdo_base + S5P_SDO_Y3);
+			writel(0x00000000, sdo_base + S5P_SDO_Y4);
+			writel(0x00000000, sdo_base + S5P_SDO_Y5);
+			writel(0x00000000, sdo_base + S5P_SDO_Y6);
+			writel(0x00000000, sdo_base + S5P_SDO_Y7);
+			writel(0x00000000, sdo_base + S5P_SDO_Y8);
+			writel(0x00000000, sdo_base + S5P_SDO_Y9);
+			writel(0x00000000, sdo_base + S5P_SDO_Y10);
+			writel(0x00000281, sdo_base + S5P_SDO_Y11);
+			writel(0x00000000, sdo_base + S5P_SDO_CB0);
+			writel(0x00000000, sdo_base + S5P_SDO_CB1);
+			writel(0x00000000, sdo_base + S5P_SDO_CB2);
+			writel(0x00000000, sdo_base + S5P_SDO_CB3);
+			writel(0x00000000, sdo_base + S5P_SDO_CB4);
+			writel(0x00000001, sdo_base + S5P_SDO_CB5);
+			writel(0x00000007, sdo_base + S5P_SDO_CB6);
+			writel(0x00000015, sdo_base + S5P_SDO_CB7);
+			writel(0x0000002a, sdo_base + S5P_SDO_CB8);
+			writel(0x00000044, sdo_base + S5P_SDO_CB9);
+			writel(0x00000057, sdo_base + S5P_SDO_CB10);
+			writel(0x0000005f, sdo_base + S5P_SDO_CB11);
+			writel(0x00000000, sdo_base + S5P_SDO_CR1);
+			writel(0x00000000, sdo_base + S5P_SDO_CR2);
+			writel(0x00000000, sdo_base + S5P_SDO_CR3);
+			writel(0x00000000, sdo_base + S5P_SDO_CR4);
+			writel(0x00000002, sdo_base + S5P_SDO_CR5);
+			writel(0x0000000a, sdo_base + S5P_SDO_CR6);
+			writel(0x0000001d, sdo_base + S5P_SDO_CR7);
+			writel(0x0000003c, sdo_base + S5P_SDO_CR8);
+			writel(0x0000005f, sdo_base + S5P_SDO_CR9);
+			writel(0x0000007b, sdo_base + S5P_SDO_CR10);
+			writel(0x00000086, sdo_base + S5P_SDO_CR11);
+			break;
+
+		default:
+			tvout_err("invalid composite_ratio parameter(%d)\n",
+				composite_ratio);
+			return -1;
+		}
+
+		break;
+
+	case SDO_LEVEL_75IRE:
+		switch (composite_ratio) {
+		case SDO_VTOS_RATIO_10_4:
+			writel(0x00000000, sdo_base + S5P_SDO_Y0);
+			writel(0x00000000, sdo_base + S5P_SDO_Y1);
+			writel(0x00000000, sdo_base + S5P_SDO_Y2);
+			writel(0x00000000, sdo_base + S5P_SDO_Y3);
+			writel(0x00000000, sdo_base + S5P_SDO_Y4);
+			writel(0x00000000, sdo_base + S5P_SDO_Y5);
+			writel(0x00000000, sdo_base + S5P_SDO_Y6);
+			writel(0x00000000, sdo_base + S5P_SDO_Y7);
+			writel(0x00000000, sdo_base + S5P_SDO_Y8);
+			writel(0x00000000, sdo_base + S5P_SDO_Y9);
+			writel(0x00000000, sdo_base + S5P_SDO_Y10);
+			writel(0x0000025d, sdo_base + S5P_SDO_Y11);
+			writel(0x00000000, sdo_base + S5P_SDO_CB0);
+			writel(0x00000000, sdo_base + S5P_SDO_CB1);
+			writel(0x00000000, sdo_base + S5P_SDO_CB2);
+			writel(0x00000000, sdo_base + S5P_SDO_CB3);
+			writel(0x00000000, sdo_base + S5P_SDO_CB4);
+			writel(0x00000001, sdo_base + S5P_SDO_CB5);
+			writel(0x00000007, sdo_base + S5P_SDO_CB6);
+			writel(0x00000014, sdo_base + S5P_SDO_CB7);
+			writel(0x00000028, sdo_base + S5P_SDO_CB8);
+			writel(0x0000003f, sdo_base + S5P_SDO_CB9);
+			writel(0x00000052, sdo_base + S5P_SDO_CB10);
+			writel(0x0000005a, sdo_base + S5P_SDO_CB11);
+			writel(0x00000000, sdo_base + S5P_SDO_CR1);
+			writel(0x00000000, sdo_base + S5P_SDO_CR2);
+			writel(0x00000000, sdo_base + S5P_SDO_CR3);
+			writel(0x00000000, sdo_base + S5P_SDO_CR4);
+			writel(0x00000001, sdo_base + S5P_SDO_CR5);
+			writel(0x00000009, sdo_base + S5P_SDO_CR6);
+			writel(0x0000001c, sdo_base + S5P_SDO_CR7);
+			writel(0x00000039, sdo_base + S5P_SDO_CR8);
+			writel(0x0000005a, sdo_base + S5P_SDO_CR9);
+			writel(0x00000074, sdo_base + S5P_SDO_CR10);
+			writel(0x0000007e, sdo_base + S5P_SDO_CR11);
+			break;
+
+		case SDO_VTOS_RATIO_7_3:
+			writel(0x00000000, sdo_base + S5P_SDO_Y0);
+			writel(0x00000000, sdo_base + S5P_SDO_Y1);
+			writel(0x00000000, sdo_base + S5P_SDO_Y2);
+			writel(0x00000000, sdo_base + S5P_SDO_Y3);
+			writel(0x00000000, sdo_base + S5P_SDO_Y4);
+			writel(0x00000000, sdo_base + S5P_SDO_Y5);
+			writel(0x00000000, sdo_base + S5P_SDO_Y6);
+			writel(0x00000000, sdo_base + S5P_SDO_Y7);
+			writel(0x00000000, sdo_base + S5P_SDO_Y8);
+			writel(0x00000000, sdo_base + S5P_SDO_Y9);
+			writel(0x00000000, sdo_base + S5P_SDO_Y10);
+			writel(0x00000251, sdo_base + S5P_SDO_Y11);
+			writel(0x00000000, sdo_base + S5P_SDO_CB0);
+			writel(0x00000000, sdo_base + S5P_SDO_CB1);
+			writel(0x00000000, sdo_base + S5P_SDO_CB2);
+			writel(0x00000000, sdo_base + S5P_SDO_CB3);
+			writel(0x00000000, sdo_base + S5P_SDO_CB4);
+			writel(0x00000001, sdo_base + S5P_SDO_CB5);
+			writel(0x00000006, sdo_base + S5P_SDO_CB6);
+			writel(0x00000013, sdo_base + S5P_SDO_CB7);
+			writel(0x00000028, sdo_base + S5P_SDO_CB8);
+			writel(0x0000003f, sdo_base + S5P_SDO_CB9);
+			writel(0x00000051, sdo_base + S5P_SDO_CB10);
+			writel(0x00000056, sdo_base + S5P_SDO_CB11);
+			writel(0x00000000, sdo_base + S5P_SDO_CR1);
+			writel(0x00000000, sdo_base + S5P_SDO_CR2);
+			writel(0x00000000, sdo_base + S5P_SDO_CR3);
+			writel(0x00000000, sdo_base + S5P_SDO_CR4);
+			writel(0x00000002, sdo_base + S5P_SDO_CR5);
+			writel(0x00000005, sdo_base + S5P_SDO_CR6);
+			writel(0x00000018, sdo_base + S5P_SDO_CR7);
+			writel(0x00000037, sdo_base + S5P_SDO_CR8);
+			writel(0x0000005A, sdo_base + S5P_SDO_CR9);
+			writel(0x00000076, sdo_base + S5P_SDO_CR10);
+			writel(0x0000007e, sdo_base + S5P_SDO_CR11);
+			break;
+
+		default:
+			tvout_err("invalid composite_ratio parameter(%d)\n",
+				composite_ratio);
+			return -1;
+		}
+
+		break;
+
+	default:
+		tvout_err("invalid composite_level parameter(%d)\n",
+			composite_level);
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int s5p_sdo_set_video_scale_cfg(
+		enum s5p_sdo_level composite_level,
+		enum s5p_sdo_vsync_ratio composite_ratio)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d\n", composite_level, composite_ratio);
+
+	switch (composite_level) {
+	case SDO_LEVEL_0IRE:
+		temp_reg |= S5P_SDO_COMPOSITE_LEVEL_SEL_0IRE;
+		break;
+
+	case SDO_LEVEL_75IRE:
+		temp_reg |= S5P_SDO_COMPOSITE_LEVEL_SEL_75IRE;
+		break;
+
+	default:
+		tvout_err("invalid composite_level parameter(%d)\n",
+			composite_ratio);
+		return -1;
+	}
+
+	switch (composite_ratio) {
+	case SDO_VTOS_RATIO_10_4:
+		temp_reg |= S5P_SDO_COMPOSITE_VTOS_RATIO_10_4;
+		break;
+
+	case SDO_VTOS_RATIO_7_3:
+		temp_reg |= S5P_SDO_COMPOSITE_VTOS_RATIO_7_3;
+		break;
+
+	default:
+		tvout_err("invalid composite_ratio parameter(%d)\n",
+			composite_ratio);
+		return -1;
+	}
+
+	writel(temp_reg, sdo_base + S5P_SDO_SCALE);
+
+	return 0;
+}
+
+int s5p_sdo_set_vbi(
+		bool wss_cvbs, enum s5p_sdo_closed_caption_type caption_cvbs)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d\n", wss_cvbs, caption_cvbs);
+
+	if (wss_cvbs)
+		temp_reg = S5P_SDO_CVBS_WSS_INS;
+	else
+		temp_reg = S5P_SDO_CVBS_NO_WSS;
+
+	switch (caption_cvbs) {
+	case SDO_NO_INS:
+		temp_reg |= S5P_SDO_CVBS_NO_CLOSED_CAPTION;
+		break;
+
+	case SDO_INS_1:
+		temp_reg |= S5P_SDO_CVBS_21H_CLOSED_CAPTION;
+		break;
+
+	case SDO_INS_2:
+		temp_reg |= S5P_SDO_CVBS_21H_284H_CLOSED_CAPTION;
+		break;
+
+	case SDO_INS_OTHERS:
+		temp_reg |= S5P_SDO_CVBS_USE_OTHERS;
+		break;
+
+	default:
+		tvout_err("invalid caption_cvbs parameter(%d)\n",
+			caption_cvbs);
+		return -1;
+	}
+
+
+	writel(temp_reg, sdo_base + S5P_SDO_VBI);
+
+	return 0;
+}
+
+void s5p_sdo_set_offset_gain(u32 offset, u32 gain)
+{
+	tvout_dbg("%d, %d\n", offset, gain);
+
+	writel(S5P_SDO_SCALE_CONV_OFFSET(offset) |
+		S5P_SDO_SCALE_CONV_GAIN(gain),
+		sdo_base + S5P_SDO_SCALE_CH0);
+}
+
+void s5p_sdo_set_delay(
+		u32 delay_y, u32 offset_video_start, u32 offset_video_end)
+{
+	tvout_dbg("%d, %d, %d\n", delay_y, offset_video_start,
+		offset_video_end);
+
+	writel(S5P_SDO_DELAY_YTOC(delay_y) |
+		S5P_SDO_ACTIVE_START_OFFSET(offset_video_start) |
+		S5P_SDO_ACTIVE_END_OFFSET(offset_video_end),
+		sdo_base + S5P_SDO_YCDELAY);
+}
+
+void s5p_sdo_set_schlock(bool color_sucarrier_pha_adj)
+{
+	tvout_dbg("%d\n", color_sucarrier_pha_adj);
+
+	if (color_sucarrier_pha_adj)
+		writel(S5P_SDO_COLOR_SC_PHASE_ADJ,
+			sdo_base + S5P_SDO_SCHLOCK);
+	else
+		writel(S5P_SDO_COLOR_SC_PHASE_NOADJ,
+			sdo_base + S5P_SDO_SCHLOCK);
+}
+
+void s5p_sdo_set_brightness_hue_saturation(
+		struct s5p_sdo_bright_hue_saturation bri_hue_sat)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d, %d, %d, %d, %d, %d\n",
+		bri_hue_sat.bright_hue_sat_adj,	bri_hue_sat.gain_brightness,
+		bri_hue_sat.offset_brightness, bri_hue_sat.gain0_cb_hue_sat,
+		bri_hue_sat.gain1_cb_hue_sat, bri_hue_sat.gain0_cr_hue_sat,
+		bri_hue_sat.gain1_cr_hue_sat, bri_hue_sat.offset_cb_hue_sat,
+		bri_hue_sat.offset_cr_hue_sat);
+
+	temp_reg = readl(sdo_base + S5P_SDO_CCCON);
+
+	if (bri_hue_sat.bright_hue_sat_adj)
+		temp_reg &= ~S5P_SDO_COMPENSATION_BHS_ADJ_OFF;
+	else
+		temp_reg |= S5P_SDO_COMPENSATION_BHS_ADJ_OFF;
+
+	writel(temp_reg, sdo_base + S5P_SDO_CCCON);
+
+
+	writel(S5P_SDO_BRIGHTNESS_GAIN(bri_hue_sat.gain_brightness) |
+		S5P_SDO_BRIGHTNESS_OFFSET(bri_hue_sat.offset_brightness),
+			sdo_base + S5P_SDO_YSCALE);
+
+	writel(S5P_SDO_HS_CB_GAIN0(bri_hue_sat.gain0_cb_hue_sat) |
+		S5P_SDO_HS_CB_GAIN1(bri_hue_sat.gain1_cb_hue_sat),
+			sdo_base + S5P_SDO_CBSCALE);
+
+	writel(S5P_SDO_HS_CR_GAIN0(bri_hue_sat.gain0_cr_hue_sat) |
+		S5P_SDO_HS_CR_GAIN1(bri_hue_sat.gain1_cr_hue_sat),
+			sdo_base + S5P_SDO_CRSCALE);
+
+	writel(S5P_SDO_HS_CR_OFFSET(bri_hue_sat.offset_cr_hue_sat) |
+		S5P_SDO_HS_CB_OFFSET(bri_hue_sat.offset_cb_hue_sat),
+			sdo_base + S5P_SDO_CB_CR_OFFSET);
+}
+
+void s5p_sdo_set_cvbs_color_compensation(
+		struct s5p_sdo_cvbs_compensation cvbs_comp)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d, %d, %d\n",
+		cvbs_comp.cvbs_color_compen, cvbs_comp.y_lower_mid,
+		cvbs_comp.y_bottom, cvbs_comp.y_top,
+		cvbs_comp.y_upper_mid, cvbs_comp.radius);
+
+	temp_reg = readl(sdo_base + S5P_SDO_CCCON);
+
+	if (cvbs_comp.cvbs_color_compen)
+		temp_reg &= ~S5P_SDO_COMPENSATION_CVBS_COMP_OFF;
+	else
+		temp_reg |= S5P_SDO_COMPENSATION_CVBS_COMP_OFF;
+
+	writel(temp_reg, sdo_base + S5P_SDO_CCCON);
+
+
+	writel(S5P_SDO_Y_LOWER_MID_CVBS_CORN(cvbs_comp.y_lower_mid) |
+		S5P_SDO_Y_BOTTOM_CVBS_CORN(cvbs_comp.y_bottom),
+			sdo_base + S5P_SDO_CVBS_CC_Y1);
+
+	writel(S5P_SDO_Y_TOP_CVBS_CORN(cvbs_comp.y_top) |
+		S5P_SDO_Y_UPPER_MID_CVBS_CORN(cvbs_comp.y_upper_mid),
+			sdo_base + S5P_SDO_CVBS_CC_Y2);
+
+	writel(S5P_SDO_RADIUS_CVBS_CORN(cvbs_comp.radius),
+			sdo_base + S5P_SDO_CVBS_CC_C);
+}
+
+void s5p_sdo_set_component_porch(
+		u32 back_525, u32 front_525, u32 back_625, u32 front_625)
+{
+	tvout_dbg("%d, %d, %d, %d\n",
+			back_525, front_525, back_625, front_625);
+
+	writel(S5P_SDO_COMPONENT_525_BP(back_525) |
+		S5P_SDO_COMPONENT_525_FP(front_525),
+			sdo_base + S5P_SDO_CSC_525_PORCH);
+	writel(S5P_SDO_COMPONENT_625_BP(back_625) |
+		S5P_SDO_COMPONENT_625_FP(front_625),
+			sdo_base + S5P_SDO_CSC_625_PORCH);
+}
+
+void s5p_sdo_set_ch_xtalk_cancel_coef(u32 coeff2, u32 coeff1)
+{
+	tvout_dbg("%d, %d\n", coeff2, coeff1);
+
+	writel(S5P_SDO_XTALK_COEF02(coeff2) |
+		S5P_SDO_XTALK_COEF01(coeff1),
+			sdo_base + S5P_SDO_XTALK0);
+}
+
+void s5p_sdo_set_closed_caption(u32 display_cc, u32 non_display_cc)
+{
+	tvout_dbg("%d, %d\n", display_cc, non_display_cc);
+
+	writel(S5P_SDO_DISPLAY_CC_CAPTION(display_cc) |
+		S5P_SDO_NON_DISPLAY_CC_CAPTION(non_display_cc),
+		sdo_base + S5P_SDO_ARMCC);
+}
+
+int s5p_sdo_set_wss525_data(struct s5p_sdo_525_data wss525)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d\n",
+		wss525.copy_permit, wss525.mv_psp,
+		wss525.copy_info, wss525.display_ratio);
+
+	switch (wss525.copy_permit) {
+	case SDO_525_COPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_WSS525_COPY_PERMIT;
+		break;
+
+	case SDO_525_ONECOPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_WSS525_ONECOPY_PERMIT;
+		break;
+
+	case SDO_525_NOCOPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_WSS525_NOCOPY_PERMIT;
+		break;
+
+	default:
+		tvout_err("invalid copy_permit parameter(%d)\n",
+			wss525.copy_permit);
+		return -1;
+	}
+
+	switch (wss525.mv_psp) {
+	case SDO_525_MV_PSP_OFF:
+		temp_reg |= S5P_SDO_WORD2_WSS525_MV_PSP_OFF;
+		break;
+
+	case SDO_525_MV_PSP_ON_2LINE_BURST:
+		temp_reg |= S5P_SDO_WORD2_WSS525_MV_PSP_ON_2LINE_BURST;
+		break;
+
+	case SDO_525_MV_PSP_ON_BURST_OFF:
+		temp_reg |= S5P_SDO_WORD2_WSS525_MV_PSP_ON_BURST_OFF;
+		break;
+
+	case SDO_525_MV_PSP_ON_4LINE_BURST:
+		temp_reg |= S5P_SDO_WORD2_WSS525_MV_PSP_ON_4LINE_BURST;
+		break;
+
+	default:
+		tvout_err("invalid mv_psp parameter(%d)\n", wss525.mv_psp);
+		return -1;
+	}
+
+	switch (wss525.copy_info) {
+	case SDO_525_COPY_INFO:
+		temp_reg |= S5P_SDO_WORD1_WSS525_COPY_INFO;
+		break;
+
+	case SDO_525_DEFAULT:
+		temp_reg |= S5P_SDO_WORD1_WSS525_DEFAULT;
+		break;
+
+	default:
+		tvout_err("invalid copy_info parameter(%d)\n",
+				wss525.copy_info);
+		return -1;
+	}
+
+	if (wss525.analog_on)
+		temp_reg |= S5P_SDO_WORD2_WSS525_ANALOG_ON;
+	else
+		temp_reg |= S5P_SDO_WORD2_WSS525_ANALOG_OFF;
+
+	switch (wss525.display_ratio) {
+	case SDO_525_COPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_WSS525_4_3_NORMAL;
+		break;
+
+	case SDO_525_ONECOPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_WSS525_16_9_ANAMORPIC;
+		break;
+
+	case SDO_525_NOCOPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_WSS525_4_3_LETTERBOX;
+		break;
+
+	default:
+		tvout_err("invalid display_ratio parameter(%d)\n",
+			wss525.display_ratio);
+		return -1;
+	}
+
+	writel(temp_reg |
+		S5P_SDO_CRC_WSS525(s5p_sdo_calc_wss_cgms_crc(temp_reg)),
+		sdo_base + S5P_SDO_WSS525);
+
+	return 0;
+}
+
+int s5p_sdo_set_wss625_data(struct s5p_sdo_625_data wss625)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d, %d, %d, %d, %d, %d\n",
+		wss625.surround_sound, wss625.copyright,
+		wss625.copy_protection, wss625.text_subtitles,
+		wss625.open_subtitles, wss625.camera_film,
+		wss625.color_encoding, wss625.helper_signal,
+		wss625.display_ratio);
+
+	if (wss625.surround_sound)
+		temp_reg = S5P_SDO_WSS625_SURROUND_SOUND_ENABLE;
+	else
+		temp_reg = S5P_SDO_WSS625_SURROUND_SOUND_DISABLE;
+
+	if (wss625.copyright)
+		temp_reg |= S5P_SDO_WSS625_COPYRIGHT;
+	else
+		temp_reg |= S5P_SDO_WSS625_NO_COPYRIGHT;
+
+	if (wss625.copy_protection)
+		temp_reg |= S5P_SDO_WSS625_COPY_RESTRICTED;
+	else
+		temp_reg |= S5P_SDO_WSS625_COPY_NOT_RESTRICTED;
+
+	if (wss625.text_subtitles)
+		temp_reg |= S5P_SDO_WSS625_TELETEXT_SUBTITLES;
+	else
+		temp_reg |= S5P_SDO_WSS625_TELETEXT_NO_SUBTITLES;
+
+	switch (wss625.open_subtitles) {
+	case SDO_625_NO_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_WSS625_NO_OPEN_SUBTITLES;
+		break;
+
+	case SDO_625_INACT_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_WSS625_INACT_OPEN_SUBTITLES;
+		break;
+
+	case SDO_625_OUTACT_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_WSS625_OUTACT_OPEN_SUBTITLES;
+		break;
+
+	default:
+		tvout_err("invalid open_subtitles parameter(%d)\n",
+			wss625.open_subtitles);
+		return -1;
+	}
+
+	switch (wss625.camera_film) {
+	case SDO_625_CAMERA:
+		temp_reg |= S5P_SDO_WSS625_CAMERA;
+		break;
+
+	case SDO_625_FILM:
+		temp_reg |= S5P_SDO_WSS625_FILM;
+		break;
+
+	default:
+		tvout_err("invalid camera_film parameter(%d)\n",
+			wss625.camera_film);
+		return -1;
+	}
+
+	switch (wss625.color_encoding) {
+	case SDO_625_NORMAL_PAL:
+		temp_reg |= S5P_SDO_WSS625_NORMAL_PAL;
+		break;
+
+	case SDO_625_MOTION_ADAPTIVE_COLORPLUS:
+		temp_reg |= S5P_SDO_WSS625_MOTION_ADAPTIVE_COLORPLUS;
+		break;
+
+	default:
+		tvout_err("invalid color_encoding parameter(%d)\n",
+			wss625.color_encoding);
+		return -1;
+	}
+
+	if (wss625.helper_signal)
+		temp_reg |= S5P_SDO_WSS625_HELPER_SIG;
+	else
+		temp_reg |= S5P_SDO_WSS625_HELPER_NO_SIG;
+
+	switch (wss625.display_ratio) {
+	case SDO_625_4_3_FULL_576:
+		temp_reg |= S5P_SDO_WSS625_4_3_FULL_576;
+		break;
+
+	case SDO_625_14_9_LETTERBOX_CENTER_504:
+		temp_reg |= S5P_SDO_WSS625_14_9_LETTERBOX_CENTER_504;
+		break;
+
+	case SDO_625_14_9_LETTERBOX_TOP_504:
+		temp_reg |= S5P_SDO_WSS625_14_9_LETTERBOX_TOP_504;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_CENTER_430:
+		temp_reg |= S5P_SDO_WSS625_16_9_LETTERBOX_CENTER_430;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_TOP_430:
+		temp_reg |= S5P_SDO_WSS625_16_9_LETTERBOX_TOP_430;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_CENTER:
+		temp_reg |= S5P_SDO_WSS625_16_9_LETTERBOX_CENTER;
+		break;
+
+	case SDO_625_14_9_FULL_CENTER_576:
+		temp_reg |= S5P_SDO_WSS625_14_9_FULL_CENTER_576;
+		break;
+
+	case SDO_625_16_9_ANAMORPIC_576:
+		temp_reg |= S5P_SDO_WSS625_16_9_ANAMORPIC_576;
+		break;
+
+	default:
+		tvout_err("invalid display_ratio parameter(%d)\n",
+			wss625.display_ratio);
+		return -1;
+	}
+
+	writel(temp_reg, sdo_base + S5P_SDO_WSS625);
+
+	return 0;
+}
+
+int s5p_sdo_set_cgmsa525_data(struct s5p_sdo_525_data cgmsa525)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d\n",
+		cgmsa525.copy_permit, cgmsa525.mv_psp,
+		cgmsa525.copy_info, cgmsa525.display_ratio);
+
+	switch (cgmsa525.copy_permit) {
+	case SDO_525_COPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_CGMS525_COPY_PERMIT;
+		break;
+
+	case SDO_525_ONECOPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_CGMS525_ONECOPY_PERMIT;
+		break;
+
+	case SDO_525_NOCOPY_PERMIT:
+		temp_reg = S5P_SDO_WORD2_CGMS525_NOCOPY_PERMIT;
+		break;
+
+	default:
+		tvout_err("invalid copy_permit parameter(%d)\n",
+			cgmsa525.copy_permit);
+		return -1;
+	}
+
+	switch (cgmsa525.mv_psp) {
+	case SDO_525_MV_PSP_OFF:
+		temp_reg |= S5P_SDO_WORD2_CGMS525_MV_PSP_OFF;
+		break;
+
+	case SDO_525_MV_PSP_ON_2LINE_BURST:
+		temp_reg |= S5P_SDO_WORD2_CGMS525_MV_PSP_ON_2LINE_BURST;
+		break;
+
+	case SDO_525_MV_PSP_ON_BURST_OFF:
+		temp_reg |= S5P_SDO_WORD2_CGMS525_MV_PSP_ON_BURST_OFF;
+		break;
+
+	case SDO_525_MV_PSP_ON_4LINE_BURST:
+		temp_reg |= S5P_SDO_WORD2_CGMS525_MV_PSP_ON_4LINE_BURST;
+		break;
+
+	default:
+		tvout_err("invalid mv_psp parameter(%d)\n", cgmsa525.mv_psp);
+		return -1;
+	}
+
+	switch (cgmsa525.copy_info) {
+	case SDO_525_COPY_INFO:
+		temp_reg |= S5P_SDO_WORD1_CGMS525_COPY_INFO;
+		break;
+
+	case SDO_525_DEFAULT:
+		temp_reg |= S5P_SDO_WORD1_CGMS525_DEFAULT;
+		break;
+
+	default:
+		tvout_err("invalid copy_info parameter(%d)\n",
+				cgmsa525.copy_info);
+		return -1;
+	}
+
+	if (cgmsa525.analog_on)
+		temp_reg |= S5P_SDO_WORD2_CGMS525_ANALOG_ON;
+	else
+		temp_reg |= S5P_SDO_WORD2_CGMS525_ANALOG_OFF;
+
+	switch (cgmsa525.display_ratio) {
+	case SDO_525_COPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_CGMS525_4_3_NORMAL;
+		break;
+
+	case SDO_525_ONECOPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_CGMS525_16_9_ANAMORPIC;
+		break;
+
+	case SDO_525_NOCOPY_PERMIT:
+		temp_reg |= S5P_SDO_WORD0_CGMS525_4_3_LETTERBOX;
+		break;
+
+	default:
+		tvout_err("invalid display_ratio parameter(%d)\n",
+			cgmsa525.display_ratio);
+		return -1;
+	}
+
+	writel(temp_reg | S5P_SDO_CRC_CGMS525(
+		s5p_sdo_calc_wss_cgms_crc(temp_reg)),
+		sdo_base + S5P_SDO_CGMS525);
+
+	return 0;
+}
+
+
+int s5p_sdo_set_cgmsa625_data(struct s5p_sdo_625_data cgmsa625)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d, %d, %d, %d, %d, %d, %d, %d\n",
+		cgmsa625.surround_sound, cgmsa625.copyright,
+		cgmsa625.copy_protection, cgmsa625.text_subtitles,
+		cgmsa625.open_subtitles, cgmsa625.camera_film,
+		cgmsa625.color_encoding, cgmsa625.helper_signal,
+		cgmsa625.display_ratio);
+
+	if (cgmsa625.surround_sound)
+		temp_reg = S5P_SDO_CGMS625_SURROUND_SOUND_ENABLE;
+	else
+		temp_reg = S5P_SDO_CGMS625_SURROUND_SOUND_DISABLE;
+
+	if (cgmsa625.copyright)
+		temp_reg |= S5P_SDO_CGMS625_COPYRIGHT;
+	else
+		temp_reg |= S5P_SDO_CGMS625_NO_COPYRIGHT;
+
+	if (cgmsa625.copy_protection)
+		temp_reg |= S5P_SDO_CGMS625_COPY_RESTRICTED;
+	else
+		temp_reg |= S5P_SDO_CGMS625_COPY_NOT_RESTRICTED;
+
+	if (cgmsa625.text_subtitles)
+		temp_reg |= S5P_SDO_CGMS625_TELETEXT_SUBTITLES;
+	else
+		temp_reg |= S5P_SDO_CGMS625_TELETEXT_NO_SUBTITLES;
+
+	switch (cgmsa625.open_subtitles) {
+	case SDO_625_NO_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_CGMS625_NO_OPEN_SUBTITLES;
+		break;
+
+	case SDO_625_INACT_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_CGMS625_INACT_OPEN_SUBTITLES;
+		break;
+
+	case SDO_625_OUTACT_OPEN_SUBTITLES:
+		temp_reg |= S5P_SDO_CGMS625_OUTACT_OPEN_SUBTITLES;
+		break;
+
+	default:
+		tvout_err("invalid open_subtitles parameter(%d)\n",
+			cgmsa625.open_subtitles);
+		return -1;
+	}
+
+	switch (cgmsa625.camera_film) {
+	case SDO_625_CAMERA:
+		temp_reg |= S5P_SDO_CGMS625_CAMERA;
+		break;
+
+	case SDO_625_FILM:
+		temp_reg |= S5P_SDO_CGMS625_FILM;
+		break;
+
+	default:
+		tvout_err("invalid camera_film parameter(%d)\n",
+			cgmsa625.camera_film);
+		return -1;
+	}
+
+	switch (cgmsa625.color_encoding) {
+	case SDO_625_NORMAL_PAL:
+		temp_reg |= S5P_SDO_CGMS625_NORMAL_PAL;
+		break;
+
+	case SDO_625_MOTION_ADAPTIVE_COLORPLUS:
+		temp_reg |= S5P_SDO_CGMS625_MOTION_ADAPTIVE_COLORPLUS;
+		break;
+
+	default:
+		tvout_err("invalid color_encoding parameter(%d)\n",
+			cgmsa625.color_encoding);
+		return -1;
+	}
+
+	if (cgmsa625.helper_signal)
+		temp_reg |= S5P_SDO_CGMS625_HELPER_SIG;
+	else
+		temp_reg |= S5P_SDO_CGMS625_HELPER_NO_SIG;
+
+	switch (cgmsa625.display_ratio) {
+	case SDO_625_4_3_FULL_576:
+		temp_reg |= S5P_SDO_CGMS625_4_3_FULL_576;
+		break;
+
+	case SDO_625_14_9_LETTERBOX_CENTER_504:
+		temp_reg |= S5P_SDO_CGMS625_14_9_LETTERBOX_CENTER_504;
+		break;
+
+	case SDO_625_14_9_LETTERBOX_TOP_504:
+		temp_reg |= S5P_SDO_CGMS625_14_9_LETTERBOX_TOP_504;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_CENTER_430:
+		temp_reg |= S5P_SDO_CGMS625_16_9_LETTERBOX_CENTER_430;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_TOP_430:
+		temp_reg |= S5P_SDO_CGMS625_16_9_LETTERBOX_TOP_430;
+		break;
+
+	case SDO_625_16_9_LETTERBOX_CENTER:
+		temp_reg |= S5P_SDO_CGMS625_16_9_LETTERBOX_CENTER;
+		break;
+
+	case SDO_625_14_9_FULL_CENTER_576:
+		temp_reg |= S5P_SDO_CGMS625_14_9_FULL_CENTER_576;
+		break;
+
+	case SDO_625_16_9_ANAMORPIC_576:
+		temp_reg |= S5P_SDO_CGMS625_16_9_ANAMORPIC_576;
+		break;
+
+	default:
+		tvout_err("invalid display_ratio parameter(%d)\n",
+			cgmsa625.display_ratio);
+		return -1;
+	}
+
+	writel(temp_reg, sdo_base + S5P_SDO_CGMS625);
+
+	return 0;
+}
+
+int s5p_sdo_set_display_mode(
+		enum s5p_tvout_disp_mode disp_mode, enum s5p_sdo_order order)
+{
+	u32 temp_reg = 0;
+
+	tvout_dbg("%d, %d\n", disp_mode, order);
+
+	switch (disp_mode) {
+	case TVOUT_NTSC_M:
+		temp_reg |= S5P_SDO_NTSC_M;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_75IRE,
+			SDO_VTOS_RATIO_10_4);
+
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_75IRE,
+			SDO_VTOS_RATIO_10_4);
+		break;
+
+	case TVOUT_PAL_BDGHI:
+		temp_reg |= S5P_SDO_PAL_BGHID;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+		break;
+
+	case TVOUT_PAL_M:
+		temp_reg |= S5P_SDO_PAL_M;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+		break;
+
+	case TVOUT_PAL_N:
+		temp_reg |= S5P_SDO_PAL_N;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_75IRE,
+			SDO_VTOS_RATIO_10_4);
+		break;
+
+	case TVOUT_PAL_NC:
+		temp_reg |= S5P_SDO_PAL_NC;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+		break;
+
+	case TVOUT_PAL_60:
+		temp_reg |= S5P_SDO_PAL_60;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_0IRE,
+			SDO_VTOS_RATIO_7_3);
+		break;
+
+	case TVOUT_NTSC_443:
+		temp_reg |= S5P_SDO_NTSC_443;
+		s5p_sdo_set_video_scale_cfg(
+			SDO_LEVEL_75IRE,
+			SDO_VTOS_RATIO_10_4);
+		s5p_sdo_set_antialias_filter_coeff_default(
+			SDO_LEVEL_75IRE,
+			SDO_VTOS_RATIO_10_4);
+		break;
+
+	default:
+		tvout_err("invalid disp_mode parameter(%d)\n", disp_mode);
+		return -1;
+	}
+
+	temp_reg |= S5P_SDO_COMPOSITE | S5P_SDO_INTERLACED;
+
+	switch (order) {
+
+	case SDO_O_ORDER_COMPOSITE_CVBS_Y_C:
+		temp_reg |= S5P_SDO_DAC2_CVBS | S5P_SDO_DAC1_Y |
+				S5P_SDO_DAC0_C;
+		break;
+
+	case SDO_O_ORDER_COMPOSITE_CVBS_C_Y:
+		temp_reg |= S5P_SDO_DAC2_CVBS | S5P_SDO_DAC1_C |
+				S5P_SDO_DAC0_Y;
+		break;
+
+	case SDO_O_ORDER_COMPOSITE_Y_C_CVBS:
+		temp_reg |= S5P_SDO_DAC2_Y | S5P_SDO_DAC1_C |
+				S5P_SDO_DAC0_CVBS;
+		break;
+
+	case SDO_O_ORDER_COMPOSITE_Y_CVBS_C:
+		temp_reg |= S5P_SDO_DAC2_Y | S5P_SDO_DAC1_CVBS |
+				S5P_SDO_DAC0_C;
+		break;
+
+	case SDO_O_ORDER_COMPOSITE_C_CVBS_Y:
+		temp_reg |= S5P_SDO_DAC2_C | S5P_SDO_DAC1_CVBS |
+				S5P_SDO_DAC0_Y;
+		break;
+
+	case SDO_O_ORDER_COMPOSITE_C_Y_CVBS:
+		temp_reg |= S5P_SDO_DAC2_C | S5P_SDO_DAC1_Y |
+				S5P_SDO_DAC0_CVBS;
+		break;
+
+	default:
+		tvout_err("invalid order parameter(%d)\n", order);
+		return -1;
+	}
+
+	writel(temp_reg, sdo_base + S5P_SDO_CONFIG);
+
+	return 0;
+}
+
+void s5p_sdo_clock_on(bool on)
+{
+	tvout_dbg("%d\n", on);
+
+	if (on)
+		writel(S5P_SDO_TVOUT_CLOCK_ON, sdo_base + S5P_SDO_CLKCON);
+	else {
+		mdelay(100);
+
+		writel(S5P_SDO_TVOUT_CLOCK_OFF, sdo_base + S5P_SDO_CLKCON);
+	}
+}
+
+void s5p_sdo_dac_on(bool on)
+{
+	tvout_dbg("%d\n", on);
+
+	if (on) {
+		writel(S5P_SDO_POWER_ON_DAC, sdo_base + S5P_SDO_DAC);
+
+		writel(S5P_DAC_ENABLE, S5P_DAC_CONTROL);
+	} else {
+		writel(S5P_DAC_DISABLE, S5P_DAC_CONTROL);
+
+		writel(S5P_SDO_POWER_DOWN_DAC, sdo_base + S5P_SDO_DAC);
+	}
+}
+
+void s5p_sdo_sw_reset(bool active)
+{
+	tvout_dbg("%d\n", active);
+
+	if (active)
+		writel(readl(sdo_base + S5P_SDO_CLKCON) |
+			S5P_SDO_TVOUT_SW_RESET,
+				sdo_base + S5P_SDO_CLKCON);
+	else
+		writel(readl(sdo_base + S5P_SDO_CLKCON) &
+			~S5P_SDO_TVOUT_SW_RESET,
+				sdo_base + S5P_SDO_CLKCON);
+}
+
+void s5p_sdo_set_interrupt_enable(bool vsync_intc_en)
+{
+	tvout_dbg("%d\n", vsync_intc_en);
+
+	if (vsync_intc_en)
+		writel(readl(sdo_base + S5P_SDO_IRQMASK) &
+			~S5P_SDO_VSYNC_IRQ_DISABLE,
+				sdo_base + S5P_SDO_IRQMASK);
+	else
+		writel(readl(sdo_base + S5P_SDO_IRQMASK) |
+			S5P_SDO_VSYNC_IRQ_DISABLE,
+				sdo_base + S5P_SDO_IRQMASK);
+}
+
+void s5p_sdo_clear_interrupt_pending(void)
+{
+	writel(readl(sdo_base + S5P_SDO_IRQ) | S5P_SDO_VSYNC_IRQ_PEND,
+			sdo_base + S5P_SDO_IRQ);
+}
+
+void s5p_sdo_init(void __iomem *addr)
+{
+	sdo_base = addr;
+}
diff --git a/drivers/media/video/samsung/tvout/hw_if/vp.c b/drivers/media/video/samsung/tvout/hw_if/vp.c
new file mode 100644
index 0000000..71d137f
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/hw_if/vp.c
@@ -0,0 +1,747 @@
+/* linux/drivers/media/video/samsung/tvout/hw_if/vp.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Hardware interface functions for video processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <mach/regs-vp.h>
+
+#include "../s5p_tvout_common_lib.h"
+#include "hw_if.h"
+
+#undef tvout_dbg
+
+#ifdef CONFIG_VP_DEBUG
+#define tvout_dbg(fmt, ...)					\
+		printk(KERN_INFO "\t[VP] %s(): " fmt,		\
+			__func__, ##__VA_ARGS__)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+
+/*
+ * Area for definitions to be used in only this file.
+ * This area can include #define, enum and struct defintition.
+ */
+#define H_RATIO(s_w, d_w) (((s_w) << 16) / (d_w))
+#define V_RATIO(s_h, d_h, ipc_2d) (((s_h) << ((ipc_2d) ? 17 : 16)) / (d_h))
+
+enum s5p_vp_poly_coeff {
+	VP_POLY8_Y0_LL = 0,
+	VP_POLY8_Y0_LH,
+	VP_POLY8_Y0_HL,
+	VP_POLY8_Y0_HH,
+	VP_POLY8_Y1_LL,
+	VP_POLY8_Y1_LH,
+	VP_POLY8_Y1_HL,
+	VP_POLY8_Y1_HH,
+	VP_POLY8_Y2_LL,
+	VP_POLY8_Y2_LH,
+	VP_POLY8_Y2_HL,
+	VP_POLY8_Y2_HH,
+	VP_POLY8_Y3_LL,
+	VP_POLY8_Y3_LH,
+	VP_POLY8_Y3_HL,
+	VP_POLY8_Y3_HH,
+	VP_POLY4_Y0_LL = 32,
+	VP_POLY4_Y0_LH,
+	VP_POLY4_Y0_HL,
+	VP_POLY4_Y0_HH,
+	VP_POLY4_Y1_LL,
+	VP_POLY4_Y1_LH,
+	VP_POLY4_Y1_HL,
+	VP_POLY4_Y1_HH,
+	VP_POLY4_Y2_LL,
+	VP_POLY4_Y2_LH,
+	VP_POLY4_Y2_HL,
+	VP_POLY4_Y2_HH,
+	VP_POLY4_Y3_LL,
+	VP_POLY4_Y3_LH,
+	VP_POLY4_Y3_HL,
+	VP_POLY4_Y3_HH,
+	VP_POLY4_C0_LL,
+	VP_POLY4_C0_LH,
+	VP_POLY4_C0_HL,
+	VP_POLY4_C0_HH,
+	VP_POLY4_C1_LL,
+	VP_POLY4_C1_LH,
+	VP_POLY4_C1_HL,
+	VP_POLY4_C1_HH
+};
+
+enum s5p_vp_filter_h_pp {
+	VP_PP_H_NORMAL,
+	VP_PP_H_8_9,
+	VP_PP_H_1_2,
+	VP_PP_H_1_3,
+	VP_PP_H_1_4
+};
+
+enum s5p_vp_filter_v_pp {
+	VP_PP_V_NORMAL,
+	VP_PP_V_5_6,
+	VP_PP_V_3_4,
+	VP_PP_V_1_2,
+	VP_PP_V_1_3,
+	VP_PP_V_1_4
+};
+
+/*
+ * Area for global variables to be used in only this file.
+ */
+
+static void __iomem *vp_base;
+
+/*  Horizontal Y 8tap  */
+const signed char g_s_vp8tap_coef_y_h[] = {
+	/* VP_PP_H_NORMAL */
+	0,	0,	0,	0,	127,	0,	0,	0,
+	0,	1,	-2,	8,	126,	-6,	2,	-1,
+	0,	1,	-5,	16,	125,	-12,	4,	-1,
+	0,	2,	-8,	25,	121,	-16,	5,	-1,
+	-1,	3,	-10,	35,	114,	-18,	6,	-1,
+	-1,	4,	-13,	46,	107,	-20,	6,	-1,
+	-1,	5,	-16,	57,	99,	-21,	6,	-1,
+	-1,	5,	-18,	68,	89,	-20,	6,	-1,
+	-1,	6,	-20,	79,	79,	-20,	6,	-1,
+	-1,	6,	-20,	89,	68,	-18,	5,	-1,
+	-1,	6,	-21,	99,	57,	-16,	5,	-1,
+	-1,	6,	-20,	107,	46,	-13,	4,	-1,
+	-1,	6,	-18,	114,	35,	-10,	3,	-1,
+	-1,	5,	-16,	121,	25,	-8,	2,	0,
+	-1,	4,	-12,	125,	16,	-5,	1,	0,
+	-1,	2,	-6,	126,	8,	-2,	1,	0,
+
+	/* VP_PP_H_8_9 */
+	0,	3,	-7,	12,	112,	12,	-7,	3,
+	-1,	3,	-9,	19,	113,	6,	-5,	2,
+	-1,	3,	-11,	27,	111,	0,	-3,	2,
+	-1,	4,	-13,	35,	108,	-5,	-1,	1,
+	-1,	4,	-14,	43,	104,	-9,	0,	1,
+	-1,	5,	-16,	52,	99,	-12,	1,	0,
+	-1,	5,	-17,	61,	92,	-14,	2,	0,
+	0,	4,	-17,	69,	85,	-16,	3,	0,
+	0,	4,	-17,	77,	77,	-17,	4,	0,
+	0,	3,	-16,	85,	69,	-17,	4,	0,
+	0,	2,	-14,	92,	61,	-17,	5,	-1,
+	0,	1,	-12,	99,	52,	-16,	5,	-1,
+	1,	0,	-9,	104,	43,	-14,	4,	-1,
+	1,	-1,	-5,	108,	35,	-13,	4,	-1,
+	2,	-3,	0,	111,	27,	-11,	3,	-1,
+	2,	-5,	6,	113,	19,	-9,	3,	-1,
+
+	/* VP_PP_H_1_2 */
+	0,	-3,	0,	35,	64,	35,	0,	-3,
+	0,	-3,	1,	38,	64,	32,	-1,	-3,
+	0,	-3,	2,	41,	63,	29,	-2,	-2,
+	0,	-4,	4,	43,	63,	27,	-3,	-2,
+	0,	-4,	5,	46,	62,	24,	-3,	-2,
+	0,	-4,	7,	49,	60,	21,	-3,	-2,
+	-1,	-4,	9,	51,	59,	19,	-4,	-1,
+	-1,	-4,	12,	53,	57,	16,	-4,	-1,
+	-1,	-4,	14,	55,	55,	14,	-4,	-1,
+	-1,	-4,	16,	57,	53,	12,	-4,	-1,
+	-1,	-4,	19,	59,	51,	9,	-4,	-1,
+	-2,	-3,	21,	60,	49,	7,	-4,	0,
+	-2,	-3,	24,	62,	46,	5,	-4,	0,
+	-2,	-3,	27,	63,	43,	4,	-4,	0,
+	-2,	-2,	29,	63,	41,	2,	-3,	0,
+	-3,	-1,	32,	64,	38,	1,	-3,	0,
+
+	/* VP_PP_H_1_3 */
+	0,	0,	10,	32,	44,	32,	10,	0,
+	-1,	0,	11,	33,	45,	31,	9,	0,
+	-1,	0,	12,	35,	45,	29,	8,	0,
+	-1,	1,	13,	36,	44,	28,	7,	0,
+	-1,	1,	15,	37,	44,	26,	6,	0,
+	-1,	2,	16,	38,	43,	25,	5,	0,
+	-1,	2,	18,	39,	43,	23,	5,	-1,
+	-1,	3,	19,	40,	42,	22,	4,	-1,
+	-1,	3,	21,	41,	41,	21,	3,	-1,
+	-1,	4,	22,	42,	40,	19,	3,	-1,
+	-1,	5,	23,	43,	39,	18,	2,	-1,
+	0,	5,	25,	43,	38,	16,	2,	-1,
+	0,	6,	26,	44,	37,	15,	1,	-1,
+	0,	7,	28,	44,	36,	13,	1,	-1,
+	0,	8,	29,	45,	35,	12,	0,	-1,
+	0,	9,	31,	45,	33,	11,	0,	-1,
+
+	/* VP_PP_H_1_4 */
+	0,	2,	13,	30,	38,	30,	13,	2,
+	0,	3,	14,	30,	38,	29,	12,	2,
+	0,	3,	15,	31,	38,	28,	11,	2,
+	0,	4,	16,	32,	38,	27,	10,	1,
+	0,	4,	17,	33,	37,	26,	10,	1,
+	0,	5,	18,	34,	37,	24,	9,	1,
+	0,	5,	19,	34,	37,	24,	8,	1,
+	1,	6,	20,	35,	36,	22,	7,	1,
+	1,	6,	21,	36,	36,	21,	6,	1,
+	1,	7,	22,	36,	35,	20,	6,	1,
+	1,	8,	24,	37,	34,	19,	5,	0,
+	1,	9,	24,	37,	34,	18,	5,	0,
+	1,	10,	26,	37,	33,	17,	4,	0,
+	1,	10,	27,	38,	32,	16,	4,	0,
+	2,	11,	28,	38,	31,	15,	3,	0,
+	2,	12,	29,	38,	30,	14,	3,	0
+};
+
+/* Horizontal C 4tap */
+const signed char g_s_vp4tap_coef_c_h[] = {
+	/* VP_PP_H_NORMAL */
+	0,	0,	128,	0,	0,	5,	126,	-3,
+	-1,	11,	124,	-6,	-1,	19,	118,	-8,
+	-2,	27,	111,	-8,	-3,	37,	102,	-8,
+	-4,	48,	92,	-8,	-5,	59,	81,	-7,
+	-6,	70,	70,	-6,	-7,	81,	59,	-5,
+	-8,	92,	48,	-4,	-8,	102,	37,	-3,
+	-8,	111,	27,	-2,	-8,	118,	19,	-1,
+	-6,	124,	11,	-1,	-3,	126,	5,	0,
+
+	/* VP_PP_H_8_9 */
+	0,	8,	112,	8,	-1,	13,	113,	3,
+	-2,	19,	111,	0,	-2,	26,	107,	-3,
+	-3,	34,	101,	-4,	-3,	42,	94,	-5,
+	-4,	51,	86,	-5,	-5,	60,	78,	-5,
+	-5,	69,	69,	-5,	-5,	78,	60,	-5,
+	-5,	86,	51,	-4,	-5,	94,	42,	-3,
+	-4,	101,	34,	-3,	-3,	107,	26,	-2,
+	0,	111,	19,	-2,	3,	113,	13,	-1,
+
+	/* VP_PP_H_1_2 */
+	0,	26,	76,	26,	0,	30,	76,	22,
+	0,	34,	75,	19,	1,	38,	73,	16,
+	1,	43,	71,	13,	2,	47,	69,	10,
+	3,	51,	66,	8,	4,	55,	63,	6,
+	5,	59,	59,	5,	6,	63,	55,	4,
+	8,	66,	51,	3,	10,	69,	47,	2,
+	13,	71,	43,	1,	16,	73,	38,	1,
+	19,	75,	34,	0,	22,	76,	30,	0,
+
+	/* VP_PP_H_1_3 */
+	0,	30,	68,	30,	2,	33,	66,	27,
+	3,	36,	66,	23,	3,	39,	65,	21,
+	4,	43,	63,	18,	5,	46,	62,	15,
+	6,	49,	60,	13,	8,	52,	57,	11,
+	9,	55,	55,	9,	11,	57,	52,	8,
+	13,	60,	49,	6,	15,	62,	46,	5,
+	18,	63,	43,	4,	21,	65,	39,	3,
+	23,	66,	36,	3,	27,	66,	33,	2,
+
+	/*  VP_PP_H_1_4 */
+	0,	31,	66,	31,	3,	34,	63,	28,
+	4,	37,	62,	25,	4,	40,	62,	22,
+	5,	43,	61,	19,	6,	46,	59,	17,
+	7,	48,	58,	15,	9,	51,	55,	13,
+	11,	53,	53,	11,	13,	55,	51,	9,
+	15,	58,	48,	7,	17,	59,	46,	6,
+	19,	61,	43,	5,	22,	62,	40,	4,
+	25,	62,	37,	4,	28,	63,	34,	3,
+};
+
+
+/*  Vertical Y 8tap  */
+const signed char g_s_vp4tap_coef_y_v[] = {
+	/* VP_PP_V_NORMAL  */
+	0,	0,	127,	0,	0,	5,	126,	-3,
+	-1,	11,	124,	-6,	-1,	19,	118,	-8,
+	-2,	27,	111,	-8,	-3,	37,	102,	-8,
+	-4,	48,	92,	-8,	-5,	59,	81,	-7,
+	-6,	70,	70,	-6,	-7,	81,	59,	-5,
+	-8,	92,	48,	-4,	-8,	102,	37,	-3,
+	-8,	111,	27,	-2,	-8,	118,	19,	-1,
+	-6,	124,	11,	-1,	-3,	126,	5,	0,
+
+	/* VP_PP_V_5_6  */
+	0,	11,	106,	11,	-2,	16,	107,	7,
+	-2,	22,	105,	3,	-2,	29,	101,	0,
+	-3,	36,	96,	-1,	-3,	44,	90,	-3,
+	-4,	52,	84,	-4,	-4,	60,	76,	-4,
+	-4,	68,	68,	-4,	-4,	76,	60,	-4,
+	-4,	84,	52,	-4,	-3,	90,	44,	-3,
+	-1,	96,	36,	-3,	0,	101,	29,	-2,
+	3,	105,	22,	-2,	7,	107,	16,	-2,
+
+	/* VP_PP_V_3_4  */
+	0,	15,	98,	15,	-2,	21,	97,	12,
+	-2,	26,	96,	8,	-2,	32,	93,	5,
+	-2,	39,	89,	2,	-2,	46,	84,	0,
+	-3,	53,	79,	-1,	-2,	59,	73,	-2,
+	-2,	66,	66,	-2,	-2,	73,	59,	-2,
+	-1,	79,	53,	-3,	0,	84,	46,	-2,
+	2,	89,	39,	-2,	5,	93,	32,	-2,
+	8,	96,	26,	-2,	12,	97,	21,	-2,
+
+	/* VP_PP_V_1_2  */
+	0,	26,	76,	26,	0,	30,	76,	22,
+	0,	34,	75,	19,	1,	38,	73,	16,
+	1,	43,	71,	13,	2,	47,	69,	10,
+	3,	51,	66,	8,	4,	55,	63,	6,
+	5,	59,	59,	5,	6,	63,	55,	4,
+	8,	66,	51,	3,	10,	69,	47,	2,
+	13,	71,	43,	1,	16,	73,	38,	1,
+	19,	75,	34,	0,	22,	76,	30,	0,
+
+	/* VP_PP_V_1_3  */
+	0,	30,	68,	30,	2,	33,	66,	27,
+	3,	36,	66,	23,	3,	39,	65,	21,
+	4,	43,	63,	18,	5,	46,	62,	15,
+	6,	49,	60,	13,	8,	52,	57,	11,
+	9,	55,	55,	9,	11,	57,	52,	8,
+	13,	60,	49,	6,	15,	62,	46,	5,
+	18,	63,	43,	4,	21,	65,	39,	3,
+	23,	66,	36,	3,	27,	66,	33,	2,
+
+	/* VP_PP_V_1_4  */
+	0,	31,	66,	31,	3,	34,	63,	28,
+	4,	37,	62,	25,	4,	40,	62,	22,
+	5,	43,	61,	19,	6,	46,	59,	17,
+	7,	48,	58,	15,	9,	51,	55,	13,
+	11,	53,	53,	11,	13,	55,	51,	9,
+	15,	58,	48,	7,	17,	59,	46,	6,
+	19,	61,	43,	5,	22,	62,	40,	4,
+	25,	62,	37,	4,	28,	63,	34,	3
+};
+
+/*
+ * Area for functions to be used in only this file.
+ * Functions of this area are defined by static
+ */
+static int s5p_vp_set_poly_filter_coef(
+		enum s5p_vp_poly_coeff poly_coeff,
+		signed char ch0, signed char ch1,
+		signed char ch2, signed char ch3)
+{
+	if (poly_coeff > VP_POLY4_C1_HH || poly_coeff < VP_POLY8_Y0_LL ||
+	   (poly_coeff > VP_POLY8_Y3_HH && poly_coeff < VP_POLY4_Y0_LL)) {
+		tvout_err("invaild poly_coeff parameter\n");
+
+		return -1;
+	}
+
+	writel((((0xff & ch0) << 24) | ((0xff & ch1) << 16) |
+		((0xff & ch2) << 8) | (0xff & ch3)),
+			vp_base + S5P_VP_POLY8_Y0_LL + poly_coeff * 4);
+
+	return 0;
+}
+
+/*
+ * Area for functions to be used by other files.
+ * Functions of this area must be defined in header file.
+ */
+void s5p_vp_set_poly_filter_coef_default(
+		u32 src_width, u32 src_height,
+		u32 dst_width, u32 dst_height, bool ipc_2d)
+{
+	enum s5p_vp_filter_h_pp e_h_filter;
+	enum s5p_vp_filter_v_pp e_v_filter;
+	u8 *poly_flt_coeff;
+	int i, j;
+
+	u32 h_ratio = H_RATIO(src_width, dst_width);
+	u32 v_ratio = V_RATIO(src_height, dst_height, ipc_2d);
+
+	/*
+	* For the real interlace mode, the vertical ratio should be
+	* used after divided by 2. Because in the interlace mode, all
+	* the VP output is used for SDOUT display and it should be the
+	* same as one field of the progressive mode. Therefore the same
+	* filter coefficients should be used for the same the final
+	* output video. When half of the interlace V_RATIO is same as
+	* the progressive V_RATIO, the final output video scale is same.
+	*/
+
+	if (h_ratio <= (0x1 << 16))		/* 720->720 or zoom in */
+		e_h_filter = VP_PP_H_NORMAL;
+	else if (h_ratio <= (0x9 << 13))	/* 720->640 */
+		e_h_filter = VP_PP_H_8_9;
+	else if (h_ratio <= (0x1 << 17))	/* 2->1 */
+		e_h_filter = VP_PP_H_1_2;
+	else if (h_ratio <= (0x3 << 16))	/* 2->1 */
+		e_h_filter = VP_PP_H_1_3;
+	else
+		e_h_filter = VP_PP_H_1_4;	/* 4->1 */
+
+	/* Vertical Y 4tap */
+
+	if (v_ratio <= (0x1 << 16))		/* 720->720 or zoom in*/
+		e_v_filter = VP_PP_V_NORMAL;
+	else if (v_ratio <= (0x5 << 14))	/* 4->3*/
+		e_v_filter = VP_PP_V_3_4;
+	else if (v_ratio <= (0x3 << 15))	/*6->5*/
+		e_v_filter = VP_PP_V_5_6;
+	else if (v_ratio <= (0x1 << 17))	/* 2->1*/
+		e_v_filter = VP_PP_V_1_2;
+	else if (v_ratio <= (0x3 << 16))	/* 3->1*/
+		e_v_filter = VP_PP_V_1_3;
+	else
+		e_v_filter = VP_PP_V_1_4;
+
+	poly_flt_coeff = (u8 *)(g_s_vp8tap_coef_y_h + e_h_filter * 16 * 8);
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			s5p_vp_set_poly_filter_coef(
+				VP_POLY8_Y0_LL + (i*4) + j,
+				*(poly_flt_coeff + 4*j*8 + (7 - i)),
+				*(poly_flt_coeff + (4*j + 1)*8 + (7 - i)),
+				*(poly_flt_coeff + (4*j + 2)*8 + (7 - i)),
+				*(poly_flt_coeff + (4*j + 3)*8 + (7 - i)));
+		}
+	}
+
+	poly_flt_coeff = (u8 *)(g_s_vp4tap_coef_c_h + e_h_filter * 16 * 4);
+
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < 4; j++) {
+			s5p_vp_set_poly_filter_coef(
+				VP_POLY4_C0_LL + (i*4) + j,
+				*(poly_flt_coeff + 4*j*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 1)*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 2)*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 3)*4 + (3 - i)));
+		}
+	}
+
+	poly_flt_coeff = (u8 *)(g_s_vp4tap_coef_y_v + e_v_filter * 16 * 4);
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			s5p_vp_set_poly_filter_coef(
+				VP_POLY4_Y0_LL + (i*4) + j,
+				*(poly_flt_coeff + 4*j*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 1)*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 2)*4 + (3 - i)),
+				*(poly_flt_coeff + (4*j + 3)*4 + (3 - i)));
+		}
+	}
+}
+
+void s5p_vp_set_field_id(enum s5p_vp_field mode)
+{
+	writel((mode == VP_TOP_FIELD) ? VP_TOP_FIELD : VP_BOTTOM_FIELD,
+		vp_base + S5P_VP_FIELD_ID);
+}
+
+int s5p_vp_set_top_field_address(u32 top_y_addr, u32 top_c_addr)
+{
+	if (S5P_VP_PTR_ILLEGAL(top_y_addr) || S5P_VP_PTR_ILLEGAL(top_c_addr)) {
+		tvout_err("address is not double word align = 0x%x, 0x%x\n",
+			top_y_addr, top_c_addr);
+
+		return -1;
+	}
+
+	writel(top_y_addr, vp_base + S5P_VP_TOP_Y_PTR);
+	writel(top_c_addr, vp_base + S5P_VP_TOP_C_PTR);
+
+	return 0;
+}
+
+int s5p_vp_get_top_field_address(u32* top_y_addr, u32* top_c_addr)
+{
+	*top_y_addr = readl(vp_base + S5P_VP_TOP_Y_PTR);
+	*top_c_addr = readl(vp_base + S5P_VP_TOP_C_PTR);
+
+	return 0;
+}
+
+int s5p_vp_set_bottom_field_address(
+		u32 bottom_y_addr, u32 bottom_c_addr)
+{
+	if (S5P_VP_PTR_ILLEGAL(bottom_y_addr) ||
+			S5P_VP_PTR_ILLEGAL(bottom_c_addr)) {
+		tvout_err("address is not double word align = 0x%x, 0x%x\n",
+			bottom_y_addr, bottom_c_addr);
+
+		return -1;
+	}
+
+	writel(bottom_y_addr, vp_base + S5P_VP_BOT_Y_PTR);
+	writel(bottom_c_addr, vp_base + S5P_VP_BOT_C_PTR);
+
+	return 0;
+}
+
+int s5p_vp_set_img_size(u32 img_width, u32 img_height)
+{
+	if (S5P_VP_IMG_SIZE_ILLEGAL(img_width) ||
+			S5P_VP_IMG_SIZE_ILLEGAL(img_height)) {
+		tvout_err("full image size is not double word align ="
+			"%d, %d\n", img_width, img_height);
+
+		return -1;
+	}
+
+	writel(S5P_VP_IMG_HSIZE(img_width) | S5P_VP_IMG_VSIZE(img_height),
+		vp_base + S5P_VP_IMG_SIZE_Y);
+	writel(S5P_VP_IMG_HSIZE(img_width) | S5P_VP_IMG_VSIZE(img_height / 2),
+		vp_base + S5P_VP_IMG_SIZE_C);
+
+	return 0;
+}
+
+void s5p_vp_set_src_position(
+		u32 src_off_x, u32 src_x_fract_step, u32 src_off_y)
+{
+	writel(S5P_VP_SRC_H_POSITION_VAL(src_off_x) |
+		S5P_VP_SRC_X_FRACT_STEP(src_x_fract_step),
+			vp_base + S5P_VP_SRC_H_POSITION);
+	writel(S5P_VP_SRC_V_POSITION_VAL(src_off_y),
+			vp_base + S5P_VP_SRC_V_POSITION);
+}
+
+void s5p_vp_set_dest_position(u32 dst_off_x, u32 dst_off_y)
+{
+	writel(S5P_VP_DST_H_POSITION_VAL(dst_off_x),
+			vp_base + S5P_VP_DST_H_POSITION);
+	writel(S5P_VP_DST_V_POSITION_VAL(dst_off_y),
+			vp_base + S5P_VP_DST_V_POSITION);
+}
+
+void s5p_vp_set_src_dest_size(
+		u32 src_width, u32 src_height,
+		u32 dst_width, u32 dst_height, bool ipc_2d)
+{
+	u32 h_ratio = H_RATIO(src_width, dst_width);
+	u32 v_ratio = V_RATIO(src_height, dst_height, ipc_2d);
+
+	writel(S5P_VP_SRC_WIDTH_VAL(src_width), vp_base + S5P_VP_SRC_WIDTH);
+	writel(S5P_VP_SRC_HEIGHT_VAL(src_height), vp_base + S5P_VP_SRC_HEIGHT);
+	writel(S5P_VP_DST_WIDTH_VAL(dst_width), vp_base + S5P_VP_DST_WIDTH);
+	writel(S5P_VP_DST_HEIGHT_VAL(dst_height), vp_base + S5P_VP_DST_HEIGHT);
+	writel(S5P_VP_H_RATIO_VAL(h_ratio), vp_base + S5P_VP_H_RATIO);
+	writel(S5P_VP_V_RATIO_VAL(v_ratio), vp_base + S5P_VP_V_RATIO);
+
+	writel((ipc_2d) ?
+		(readl(vp_base + S5P_VP_MODE) | S5P_VP_MODE_2D_IPC_ENABLE) :
+		(readl(vp_base + S5P_VP_MODE) & ~S5P_VP_MODE_2D_IPC_ENABLE),
+		vp_base + S5P_VP_MODE);
+}
+
+void s5p_vp_set_op_mode(
+		bool line_skip,
+		enum s5p_vp_mem_type mem_type,
+		enum s5p_vp_mem_mode mem_mode,
+		enum s5p_vp_chroma_expansion chroma_exp,
+		bool auto_toggling)
+{
+	u32 temp_reg;
+
+	temp_reg = (mem_type) ?
+		S5P_VP_MODE_IMG_TYPE_YUV420_NV21 :
+		S5P_VP_MODE_IMG_TYPE_YUV420_NV12;
+	temp_reg |= (line_skip) ?
+		S5P_VP_MODE_LINE_SKIP_ON : S5P_VP_MODE_LINE_SKIP_OFF;
+	temp_reg |= (mem_mode == VP_2D_TILE_MODE) ?
+		S5P_VP_MODE_MEM_MODE_2D_TILE :
+		S5P_VP_MODE_MEM_MODE_LINEAR;
+	temp_reg |= (chroma_exp == VP_C_TOP_BOTTOM) ?
+		S5P_VP_MODE_CROMA_EXP_C_TOPBOTTOM_PTR :
+		S5P_VP_MODE_CROMA_EXP_C_TOP_PTR;
+	temp_reg |= (auto_toggling) ?
+		S5P_VP_MODE_FIELD_ID_AUTO_TOGGLING :
+		S5P_VP_MODE_FIELD_ID_MAN_TOGGLING;
+
+	writel(temp_reg, vp_base + S5P_VP_MODE);
+}
+
+void s5p_vp_set_pixel_rate_control(enum s5p_vp_pxl_rate rate)
+{
+	writel(S5P_VP_PEL_RATE_CTRL(rate), vp_base + S5P_VP_PER_RATE_CTRL);
+}
+
+void s5p_vp_set_endian(enum s5p_tvout_endian endian)
+{
+	writel(endian, vp_base + S5P_VP_ENDIAN_MODE);
+}
+
+void s5p_vp_set_bypass_post_process(bool bypass)
+{
+	writel((bypass) ? S5P_VP_BY_PASS_ENABLE : S5P_VP_BY_PASS_DISABLE,
+			vp_base + S5P_PP_BYPASS);
+}
+
+void s5p_vp_set_saturation(u32 sat)
+{
+	writel(S5P_VP_SATURATION(sat), vp_base + S5P_PP_SATURATION);
+}
+
+void s5p_vp_set_sharpness(
+		u32 th_h_noise,	enum s5p_vp_sharpness_control sharpness)
+{
+	writel(S5P_VP_TH_HNOISE(th_h_noise) | S5P_VP_SHARPNESS(sharpness),
+			vp_base + S5P_PP_SHARPNESS);
+}
+
+void s5p_vp_set_brightness_contrast(u16 b, u8 c)
+{
+	int i;
+
+	for (i = 0; i < 8; i++)
+		writel(S5P_VP_LINE_INTC(b) | S5P_VP_LINE_SLOPE(c),
+			vp_base + S5P_PP_LINE_EQ0 + i*4);
+}
+
+void s5p_vp_set_brightness_offset(u32 offset)
+{
+	writel(S5P_VP_BRIGHT_OFFSET(offset), vp_base + S5P_PP_BRIGHT_OFFSET);
+}
+
+int s5p_vp_set_brightness_contrast_control(
+		enum s5p_vp_line_eq eq_num, u32 intc, u32 slope)
+{
+	if (eq_num > VP_LINE_EQ_7 || eq_num < VP_LINE_EQ_0) {
+		tvout_err("invaild eq_num parameter\n");
+
+		return -1;
+	}
+
+	writel(S5P_VP_LINE_INTC(intc) | S5P_VP_LINE_SLOPE(slope),
+	       vp_base + S5P_PP_LINE_EQ0 + eq_num*4);
+
+	return 0;
+}
+
+void s5p_vp_set_csc_control(bool sub_y_offset_en, bool csc_en)
+{
+	u32 temp_reg;
+
+	temp_reg = (sub_y_offset_en) ? S5P_VP_SUB_Y_OFFSET_ENABLE :
+					S5P_VP_SUB_Y_OFFSET_DISABLE;
+	temp_reg |= (csc_en) ? S5P_VP_CSC_ENABLE : S5P_VP_CSC_DISABLE;
+
+	writel(temp_reg, vp_base + S5P_PP_CSC_EN);
+}
+
+int s5p_vp_set_csc_coef(enum s5p_vp_csc_coeff csc_coeff, u32 coeff)
+{
+	if (csc_coeff > VP_CSC_CR2CR_COEF ||
+			csc_coeff < VP_CSC_Y2Y_COEF) {
+		tvout_err("invaild csc_coeff parameter\n");
+
+		return -1;
+	}
+
+	writel(S5P_PP_CSC_COEF(coeff),
+			vp_base + S5P_PP_CSC_Y2Y_COEF + csc_coeff*4);
+
+	return 0;
+}
+
+int s5p_vp_set_csc_coef_default(enum s5p_vp_csc_type csc_type)
+{
+	switch (csc_type) {
+	case VP_CSC_SD_HD:
+		writel(S5P_PP_Y2Y_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_Y2Y_COEF);
+		writel(S5P_PP_CB2Y_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CB2Y_COEF);
+		writel(S5P_PP_CR2Y_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CR2Y_COEF);
+		writel(S5P_PP_Y2CB_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_Y2CB_COEF);
+		writel(S5P_PP_CB2CB_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CB2CB_COEF);
+		writel(S5P_PP_CR2CB_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CR2CB_COEF);
+		writel(S5P_PP_Y2CR_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_Y2CR_COEF);
+		writel(S5P_PP_CB2CR_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CB2CR_COEF);
+		writel(S5P_PP_CR2CR_COEF_601_TO_709,
+				vp_base + S5P_PP_CSC_CR2CR_COEF);
+		break;
+
+	case VP_CSC_HD_SD:
+		writel(S5P_PP_Y2Y_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_Y2Y_COEF);
+		writel(S5P_PP_CB2Y_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CB2Y_COEF);
+		writel(S5P_PP_CR2Y_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CR2Y_COEF);
+		writel(S5P_PP_Y2CB_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_Y2CB_COEF);
+		writel(S5P_PP_CB2CB_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CB2CB_COEF);
+		writel(S5P_PP_CR2CB_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CR2CB_COEF);
+		writel(S5P_PP_Y2CR_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_Y2CR_COEF);
+		writel(S5P_PP_CB2CR_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CB2CR_COEF);
+		writel(S5P_PP_CR2CR_COEF_709_TO_601,
+				vp_base + S5P_PP_CSC_CR2CR_COEF);
+		break;
+
+	default:
+		tvout_err("invalid csc_type parameter = %d\n", csc_type);
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_vp_update(void)
+{
+	writel(readl(vp_base + S5P_VP_SHADOW_UPDATE) |
+		S5P_VP_SHADOW_UPDATE_ENABLE,
+			vp_base + S5P_VP_SHADOW_UPDATE);
+
+	return 0;
+}
+
+int s5p_vp_get_update_status(void)
+{
+	if (readl(vp_base + S5P_VP_SHADOW_UPDATE) & S5P_VP_SHADOW_UPDATE_ENABLE)
+		return 0;
+	else
+		return -1;
+}
+
+void s5p_vp_sw_reset(void)
+{
+	writel((readl(vp_base + S5P_VP_SRESET) | S5P_VP_SRESET_PROCESSING),
+		vp_base + S5P_VP_SRESET);
+
+	while (readl(vp_base + S5P_VP_SRESET) & S5P_VP_SRESET_PROCESSING)
+		msleep(10);
+}
+
+int s5p_vp_start(void)
+{
+	writel(S5P_VP_ENABLE_ON, vp_base + S5P_VP_ENABLE);
+
+	s5p_vp_update();
+
+	return 0;
+}
+
+int s5p_vp_stop(void)
+{
+	u32 val;
+
+	val = readl(vp_base + S5P_VP_ENABLE);
+	val &= ~S5P_VP_ENABLE_ON;
+	writel(val, vp_base + S5P_VP_ENABLE);
+
+	do {
+		val = readl(vp_base + S5P_VP_ENABLE);
+	} while (!(val & S5P_VP_ENABLE_OPERATING));
+
+	return 0;
+}
+
+void s5p_vp_init(void __iomem *addr)
+{
+	vp_base = addr;
+}
diff --git a/drivers/media/video/samsung/tvout/s5p_mixer_ctrl.c b/drivers/media/video/samsung/tvout/s5p_mixer_ctrl.c
new file mode 100644
index 0000000..a0169cb
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_mixer_ctrl.c
@@ -0,0 +1,1146 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_mixer_ctrl.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Functions of mixer ctrl class for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+
+#include <plat/clock.h>
+
+#include "hw_if/hw_if.h"
+#include "s5p_tvout_ctrl.h"
+
+enum {
+	ACLK = 0,
+	MUX,
+	NO_OF_CLK
+};
+
+struct s5p_bg_color {
+	u32 color_y;
+	u32 color_cb;
+	u32 color_cr;
+};
+
+struct s5p_mixer_video_layer_info {
+	bool layer_blend;
+	u32 alpha;
+	u32 priority;
+	u32 y_min;
+	u32 y_max;
+	u32 c_min;
+	u32 c_max;
+
+	bool use_video_layer;
+};
+
+struct s5p_mixer_grp_layer_info {
+	bool pixel_blend;
+	bool layer_blend;
+	u32 alpha;
+
+	bool chroma_enable;
+	u32 chroma_key;
+
+	bool pre_mul_mode;
+
+	u32 src_x;
+	u32 src_y;
+	u32 dst_x;
+	u32 dst_y;
+	u32 width;
+	u32 height;
+	dma_addr_t fb_addr;
+
+	bool use_grp_layer;
+
+	u32 priority;
+	enum s5p_mixer_color_fmt format;
+
+	enum s5ptvfb_ver_scaling_t ver;
+	enum s5ptvfb_hor_scaling_t hor;
+};
+
+struct s5p_mixer_ctrl_private_data {
+	char			*pow_name;
+	struct s5p_tvout_clk_info	clk[NO_OF_CLK];
+	struct irq_info		irq;
+	struct reg_mem_info	reg_mem;
+
+	enum s5p_mixer_burst_mode	burst;
+	enum s5p_tvout_endian		endian;
+	struct s5p_bg_color		bg_color[3];
+
+	struct s5p_mixer_video_layer_info	v_layer;
+	struct s5p_mixer_grp_layer_info		layer[S5PTV_FB_CNT];
+
+	bool running;
+	bool vsync_interrupt_enable;
+};
+
+static struct s5p_mixer_ctrl_private_data s5p_mixer_ctrl_private = {
+	.pow_name		= "mixer_pd",
+	.clk[ACLK] = {
+		.name		= "mixer",
+		.ptr		= NULL
+	},
+	.clk[MUX] = {
+		.name		= "sclk_mixer",
+		.ptr		= NULL
+	},
+	.irq = {
+		.name		= "s5p-mixer",
+		.handler	= s5p_mixer_irq,
+		.no		= -1
+	},
+	.reg_mem = {
+		.name = "s5p-mixer",
+		.res = NULL,
+		.base = NULL
+	},
+
+	.burst = MIXER_BURST_16,
+	.endian = TVOUT_LITTLE_ENDIAN,
+	.bg_color[0].color_y = 16,
+	.bg_color[0].color_cb = 128,
+	.bg_color[0].color_cr = 128,
+	.bg_color[1].color_y = 16,
+	.bg_color[1].color_cb = 128,
+	.bg_color[1].color_cr = 128,
+	.bg_color[2].color_y = 16,
+	.bg_color[2].color_cb = 128,
+	.bg_color[2].color_cr = 128,
+
+	.v_layer = {
+		.layer_blend = false,
+		.alpha = 0xff,
+		.priority = 10,
+		.y_min = 0x10,
+		.y_max = 0xeb,
+		.c_min = 0x10,
+		.c_max = 0xf0,
+	},
+	.layer[MIXER_GPR0_LAYER] = {
+		.pixel_blend = false,
+		.layer_blend = false,
+		.alpha = 0xff,
+		.chroma_enable = false,
+		.chroma_key = 0x0,
+		.pre_mul_mode = false,
+		.src_x = 0,
+		.src_y = 0,
+		.dst_x = 0,
+		.dst_y = 0,
+		.width = 0,
+		.height = 0,
+		.priority = 10,
+		.format = MIXER_RGB8888,
+		.ver = VERTICAL_X1,
+		.hor = HORIZONTAL_X1
+	},
+	.layer[MIXER_GPR1_LAYER] = {
+		.pixel_blend = false,
+		.layer_blend = false,
+		.alpha = 0xff,
+		.chroma_enable = false,
+		.chroma_key = 0x0,
+		.pre_mul_mode = false,
+		.src_x = 0,
+		.src_y = 0,
+		.dst_x = 0,
+		.dst_y = 0,
+		.width = 0,
+		.height = 0,
+		.priority = 10,
+		.format = MIXER_RGB8888,
+		.ver = VERTICAL_X1,
+		.hor = HORIZONTAL_X1
+	},
+
+	.running = false,
+	.vsync_interrupt_enable = false,
+};
+
+static int s5p_mixer_ctrl_set_reg(enum s5p_mixer_layer layer)
+{
+	bool layer_blend;
+	u32 alpha;
+	u32 priority;
+	struct s5ptvfb_user_scaling scaling;
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		layer_blend = s5p_mixer_ctrl_private.v_layer.layer_blend;
+		alpha = s5p_mixer_ctrl_private.v_layer.alpha;
+		priority = s5p_mixer_ctrl_private.v_layer.priority;
+		break;
+	case MIXER_GPR0_LAYER:
+	case MIXER_GPR1_LAYER:
+		layer_blend = s5p_mixer_ctrl_private.layer[layer].layer_blend;
+		alpha = s5p_mixer_ctrl_private.layer[layer].alpha;
+		priority = s5p_mixer_ctrl_private.layer[layer].priority;
+
+		s5p_mixer_set_pre_mul_mode(layer,
+			s5p_mixer_ctrl_private.layer[layer].pre_mul_mode);
+		s5p_mixer_set_chroma_key(layer,
+			s5p_mixer_ctrl_private.layer[layer].chroma_enable,
+			s5p_mixer_ctrl_private.layer[layer].chroma_key);
+		s5p_mixer_set_grp_layer_dst_pos(layer,
+			s5p_mixer_ctrl_private.layer[layer].dst_x,
+			s5p_mixer_ctrl_private.layer[layer].dst_y);
+
+		scaling.ver = s5p_mixer_ctrl_private.layer[layer].ver;
+		scaling.hor = s5p_mixer_ctrl_private.layer[layer].hor;
+		s5p_mixer_scaling(layer, scaling);
+		s5p_mixer_set_grp_base_address(layer,
+			s5p_mixer_ctrl_private.layer[layer].fb_addr);
+
+		s5p_mixer_set_color_format(layer,
+			s5p_mixer_ctrl_private.layer[layer].format);
+
+		s5p_mixer_set_grp_layer_src_pos(layer,
+			s5p_mixer_ctrl_private.layer[layer].src_x,
+			s5p_mixer_ctrl_private.layer[layer].src_y,
+			s5p_mixer_ctrl_private.layer[layer].width,
+			s5p_mixer_ctrl_private.layer[layer].width,
+			s5p_mixer_ctrl_private.layer[layer].height);
+
+		s5p_mixer_set_pixel_blend(layer,
+			s5p_mixer_ctrl_private.layer[layer].pixel_blend);
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	s5p_mixer_set_layer_blend(layer, layer_blend);
+	s5p_mixer_set_alpha(layer, alpha);
+	s5p_mixer_set_priority(layer, priority);
+
+	return 0;
+}
+
+static void s5p_mixer_ctrl_clock(bool on)
+{
+	/* power control function is not implemented yet */
+	if (on) {
+		clk_enable(s5p_mixer_ctrl_private.clk[MUX].ptr);
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_get();
+#endif
+
+		clk_enable(s5p_mixer_ctrl_private.clk[ACLK].ptr);
+
+		// Restore mixer_base address
+		s5p_mixer_init(s5p_mixer_ctrl_private.reg_mem.base);
+	} else {
+		clk_disable(s5p_mixer_ctrl_private.clk[ACLK].ptr);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_put();
+#endif
+
+		clk_disable(s5p_mixer_ctrl_private.clk[MUX].ptr);
+
+		// Set mixer_base address to NULL
+		s5p_mixer_init(NULL);
+	}
+}
+
+void s5p_mixer_ctrl_init_fb_addr_phy(enum s5p_mixer_layer layer,
+				dma_addr_t fb_addr)
+{
+	s5p_mixer_ctrl_private.layer[layer].fb_addr = fb_addr;
+}
+
+void s5p_mixer_ctrl_init_grp_layer(enum s5p_mixer_layer layer)
+{
+	struct s5ptvfb_user_scaling scaling;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	} else
+#endif
+	{
+		if (s5p_mixer_ctrl_private.running) {
+			s5p_mixer_set_priority(layer,
+				s5p_mixer_ctrl_private.layer[layer].priority);
+			s5p_mixer_set_pre_mul_mode(layer,
+				s5p_mixer_ctrl_private.layer[layer].pre_mul_mode);
+			s5p_mixer_set_chroma_key(layer,
+				s5p_mixer_ctrl_private.layer[layer].chroma_enable,
+				s5p_mixer_ctrl_private.layer[layer].chroma_key);
+			s5p_mixer_set_layer_blend(layer,
+				s5p_mixer_ctrl_private.layer[layer].layer_blend);
+			s5p_mixer_set_alpha(layer,
+				s5p_mixer_ctrl_private.layer[layer].alpha);
+			s5p_mixer_set_grp_layer_dst_pos(layer,
+				s5p_mixer_ctrl_private.layer[layer].dst_x,
+				s5p_mixer_ctrl_private.layer[layer].dst_y);
+
+			scaling.ver = s5p_mixer_ctrl_private.layer[layer].ver;
+			scaling.hor = s5p_mixer_ctrl_private.layer[layer].hor;
+			s5p_mixer_scaling(layer, scaling);
+			s5p_mixer_set_grp_base_address(layer,
+				s5p_mixer_ctrl_private.layer[layer].fb_addr);
+		}
+	}
+}
+
+int s5p_mixer_ctrl_set_pixel_format(enum s5p_mixer_layer layer, u32 bpp, u32 trans_len)
+{
+	enum s5p_mixer_color_fmt format;
+
+	switch (bpp) {
+	case 16:
+		if (trans_len == 1)
+			format = MIXER_RGB1555;
+		else if (trans_len == 4)
+			format = MIXER_RGB4444;
+		else
+			format = MIXER_RGB565;
+		break;
+	case 32:
+		format = MIXER_RGB8888;
+		break;
+	default:
+		tvout_err("invalid bits per pixel\n");
+		return -1;
+	}
+
+	s5p_mixer_ctrl_private.layer[layer].format = format;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	} else
+#endif
+	{
+		if (s5p_mixer_ctrl_private.running)
+			s5p_mixer_set_color_format(layer, format);
+
+	}
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_enable_layer(enum s5p_mixer_layer layer)
+{
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		s5p_mixer_ctrl_private.v_layer.use_video_layer = true;
+		break;
+	case MIXER_GPR0_LAYER:
+	case MIXER_GPR1_LAYER:
+		s5p_mixer_ctrl_private.layer[layer].use_grp_layer = true;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+
+	if (s5p_mixer_ctrl_private.running) {
+		s5p_mixer_ctrl_set_reg(layer);
+
+		s5p_mixer_set_show(layer, true);
+	}
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_disable_layer(enum s5p_mixer_layer layer)
+{
+	bool use_vid, use_grp0, use_grp1;
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		s5p_mixer_ctrl_private.v_layer.use_video_layer = false;
+		break;
+	case MIXER_GPR0_LAYER:
+	case MIXER_GPR1_LAYER:
+		s5p_mixer_ctrl_private.layer[layer].use_grp_layer = false;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+
+	use_vid = s5p_mixer_ctrl_private.v_layer.use_video_layer;
+	use_grp0 = s5p_mixer_ctrl_private.layer[MIXER_GPR0_LAYER].use_grp_layer;
+	use_grp1 = s5p_mixer_ctrl_private.layer[MIXER_GPR1_LAYER].use_grp_layer;
+
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_show(layer, false);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_priority(enum s5p_mixer_layer layer, u32 prio)
+{
+	if (prio > 15) {
+		tvout_err("layer priority range : 0 - 15\n");
+		return -1;
+	}
+
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		s5p_mixer_ctrl_private.v_layer.priority = prio;
+		break;
+	case MIXER_GPR0_LAYER:
+	case MIXER_GPR1_LAYER:
+		s5p_mixer_ctrl_private.layer[layer].priority = prio;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_priority(layer, prio);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_dst_win_pos(enum s5p_mixer_layer layer,
+				int dst_x, int dst_y, u32 w, u32 h)
+{
+	u32 w_t, h_t;
+	enum s5p_tvout_disp_mode std;
+	enum s5p_tvout_o_mode inf;
+
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	s5p_tvif_ctrl_get_std_if(&std, &inf);
+	tvout_dbg("standard no = %d, output mode no = %d\n", std, inf);
+
+	/*
+	 * When tvout resolution was overscanned, there is no
+	 * adjust method in H/W. So, framebuffer should be resized.
+	 * In this case - TV w/h is greater than FB w/h, grp layer's
+	 * dst offset must be changed to fix tv screen.
+	 */
+
+	switch (std) {
+	case TVOUT_NTSC_M:
+	case TVOUT_480P_60_16_9:
+	case TVOUT_480P_60_4_3:
+	case TVOUT_480P_59:
+		w_t = 720;
+		h_t = 480;
+		break;
+
+	case TVOUT_576P_50_16_9:
+	case TVOUT_576P_50_4_3:
+		w_t = 720;
+		h_t = 576;
+		break;
+
+	case TVOUT_720P_60:
+	case TVOUT_720P_59:
+	case TVOUT_720P_50:
+		w_t = 1280;
+		h_t = 720;
+		break;
+
+	case TVOUT_1080I_60:
+	case TVOUT_1080I_59:
+	case TVOUT_1080I_50:
+	case TVOUT_1080P_60:
+	case TVOUT_1080P_59:
+	case TVOUT_1080P_50:
+	case TVOUT_1080P_30:
+		w_t = 1920;
+		h_t = 1080;
+		break;
+
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_720P_60_SBS_HALF:
+	case TVOUT_720P_59_SBS_HALF:
+	case TVOUT_720P_50_TB:
+		w_t = 1280;
+		h_t = 720;
+		break;
+
+	case TVOUT_1080P_24_TB:
+	case TVOUT_1080P_23_TB:
+		w_t = 1920;
+		h_t = 1080;
+		break;
+
+#endif
+	default:
+		w_t = 0;
+		h_t = 0;
+		break;
+	}
+
+	if (dst_x < 0)
+		dst_x = 0;
+
+	if (dst_y < 0)
+		dst_y = 0;
+
+	if (dst_x + w > w_t)
+		dst_x = w_t - w;
+
+	if (dst_y + h > h_t)
+		dst_y = h_t - h;
+
+	tvout_dbg("destination coordinates : x = %d, y = %d\n",
+			dst_x, dst_y);
+	tvout_dbg("output device screen size : width = %d, height = %d",
+			w_t, h_t);
+
+	s5p_mixer_ctrl_private.layer[layer].dst_x = (u32)dst_x;
+	s5p_mixer_ctrl_private.layer[layer].dst_y = (u32)dst_y;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_grp_layer_dst_pos(layer, (u32)dst_x, (u32)dst_y);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_src_win_pos(enum s5p_mixer_layer layer,
+				u32 src_x, u32 src_y, u32 w, u32 h)
+{
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	tvout_dbg("source coordinates : x = %d, y = %d\n", src_x, src_y);
+	tvout_dbg("source size : width = %d, height = %d\n", w, h);
+
+	s5p_mixer_ctrl_private.layer[layer].src_x = src_x;
+	s5p_mixer_ctrl_private.layer[layer].src_y = src_y;
+	s5p_mixer_ctrl_private.layer[layer].width = w;
+	s5p_mixer_ctrl_private.layer[layer].height = h;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	} else
+#endif
+	{
+		if (s5p_mixer_ctrl_private.running)
+			s5p_mixer_set_grp_layer_src_pos(layer, src_x, src_y, w, w, h);
+	}
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_buffer_address(enum s5p_mixer_layer layer,
+				dma_addr_t start_addr)
+{
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	tvout_dbg("TV frame buffer base address = 0x%x\n", start_addr);
+
+	s5p_mixer_ctrl_private.layer[layer].fb_addr = start_addr;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_grp_base_address(layer, start_addr);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_chroma_key(enum s5p_mixer_layer layer,
+				struct s5ptvfb_chroma chroma)
+{
+	bool enabled = (chroma.enabled) ? true : false;
+
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	s5p_mixer_ctrl_private.layer[layer].chroma_enable = enabled;
+	s5p_mixer_ctrl_private.layer[layer].chroma_key = chroma.key;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_chroma_key(layer, enabled, chroma.key);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_alpha(enum s5p_mixer_layer layer, u32 alpha)
+{
+	switch (layer) {
+	case MIXER_VIDEO_LAYER:
+		s5p_mixer_ctrl_private.v_layer.alpha = alpha;
+		break;
+	case MIXER_GPR0_LAYER:
+	case MIXER_GPR1_LAYER:
+		s5p_mixer_ctrl_private.layer[layer].alpha = alpha;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	tvout_dbg("alpha value = 0x%x\n", alpha);
+
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_alpha(layer, alpha);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_blend_mode(enum s5p_mixer_layer layer,
+				enum s5ptvfb_alpha_t mode)
+{
+	if ((layer != MIXER_VIDEO_LAYER) && (layer != MIXER_GPR0_LAYER) &&
+		(layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	if ((layer == MIXER_VIDEO_LAYER) && (mode == PIXEL_BLENDING)) {
+		tvout_err("video layer doesn't support pixel blending\n");
+		return -1;
+	}
+
+	switch (mode) {
+	case PIXEL_BLENDING:
+		tvout_dbg("pixel blending\n");
+		s5p_mixer_ctrl_private.layer[layer].pixel_blend = true;
+
+		if (s5p_mixer_ctrl_private.running)
+			s5p_mixer_set_pixel_blend(layer, true);
+		break;
+
+	case LAYER_BLENDING:
+		tvout_dbg("layer blending\n");
+		if (layer == MIXER_VIDEO_LAYER)
+			s5p_mixer_ctrl_private.v_layer.layer_blend = true;
+		else /* graphic layer */
+			s5p_mixer_ctrl_private.layer[layer].layer_blend = true;
+
+		if (s5p_mixer_ctrl_private.running)
+			s5p_mixer_set_layer_blend(layer, true);
+		break;
+
+	case NONE_BLENDING:
+		tvout_dbg("alpha blending off\n");
+		if (layer == MIXER_VIDEO_LAYER) {
+			s5p_mixer_ctrl_private.v_layer.layer_blend = false;
+
+			if (s5p_mixer_ctrl_private.running)
+				s5p_mixer_set_layer_blend(layer, false);
+		} else { /* graphic layer */
+			s5p_mixer_ctrl_private.layer[layer].pixel_blend = false;
+			s5p_mixer_ctrl_private.layer[layer].layer_blend = false;
+
+			if (s5p_mixer_ctrl_private.running) {
+				s5p_mixer_set_layer_blend(layer, false);
+				s5p_mixer_set_pixel_blend(layer, false);
+			}
+		}
+		break;
+
+	default:
+		tvout_err("invalid blending mode\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_set_alpha_blending(enum s5p_mixer_layer layer,
+			enum s5ptvfb_alpha_t blend_mode, unsigned int alpha)
+{
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	switch (blend_mode) {
+	case PIXEL_BLENDING:
+		tvout_dbg("pixel blending\n");
+		s5p_mixer_ctrl_private.layer[layer].pixel_blend = true;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+			return 0;
+		}
+#endif
+		if (s5p_mixer_ctrl_private.running)
+			s5p_mixer_set_pixel_blend(layer, true);
+		break;
+
+	case LAYER_BLENDING:
+		tvout_dbg("layer blending : alpha value = 0x%x\n", alpha);
+		s5p_mixer_ctrl_private.layer[layer].layer_blend = true;
+		s5p_mixer_ctrl_private.layer[layer].alpha = alpha;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+			return 0;
+		}
+#endif
+		if (s5p_mixer_ctrl_private.running) {
+			s5p_mixer_set_layer_blend(layer, true);
+			s5p_mixer_set_alpha(layer, alpha);
+		}
+		break;
+
+	case NONE_BLENDING:
+		tvout_dbg("alpha blending off\n");
+		s5p_mixer_ctrl_private.layer[layer].pixel_blend = false;
+		s5p_mixer_ctrl_private.layer[layer].layer_blend = false;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+			return 0;
+		}
+#endif
+		if (s5p_mixer_ctrl_private.running) {
+			s5p_mixer_set_pixel_blend(layer, false);
+			s5p_mixer_set_layer_blend(layer, false);
+		}
+		break;
+
+	default:
+		tvout_err("invalid blending mode\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_scaling(enum s5p_mixer_layer layer,
+			struct s5ptvfb_user_scaling scaling)
+{
+	if ((layer != MIXER_GPR0_LAYER) && (layer != MIXER_GPR1_LAYER)) {
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	if ((scaling.ver != VERTICAL_X1) && (scaling.ver != VERTICAL_X2)) {
+		tvout_err("invalid vertical size\n");
+		return -1;
+	}
+
+	if ((scaling.hor != HORIZONTAL_X1) && (scaling.hor != HORIZONTAL_X2)) {
+		tvout_err("invalid horizontal size\n");
+		return -1;
+	}
+
+	s5p_mixer_ctrl_private.layer[layer].ver = scaling.ver;
+	s5p_mixer_ctrl_private.layer[layer].hor = scaling.hor;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return 0;
+	}
+#endif
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_scaling(layer, scaling);
+
+	return 0;
+}
+
+int s5p_mixer_ctrl_mux_clk(struct clk *ptr)
+{
+	if (clk_set_parent(s5p_mixer_ctrl_private.clk[MUX].ptr, ptr)) {
+		tvout_err("unable to set parent %s of clock %s.\n",
+				ptr->name, s5p_mixer_ctrl_private.clk[MUX].ptr->name);
+		return -1;
+	}
+
+	return 0;
+}
+
+void s5p_mixer_ctrl_set_int_enable(bool en)
+{
+	tvout_dbg("mixer layers' underflow interrupts are %s, running %d\n",
+				en ? "enabled" : "disabled",
+				s5p_mixer_ctrl_private.running);
+
+	if (s5p_mixer_ctrl_private.running) {
+		s5p_mixer_set_underflow_int_enable(MIXER_VIDEO_LAYER, en);
+		s5p_mixer_set_underflow_int_enable(MIXER_GPR0_LAYER, en);
+		s5p_mixer_set_underflow_int_enable(MIXER_GPR1_LAYER, en);
+	}
+}
+
+void s5p_mixer_ctrl_set_vsync_interrupt(bool en)
+{
+	s5p_mixer_ctrl_private.vsync_interrupt_enable = en;
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_set_vsync_interrupt(en);
+}
+
+bool s5p_mixer_ctrl_get_vsync_interrupt()
+{
+	return s5p_mixer_ctrl_private.vsync_interrupt_enable;
+}
+
+void s5p_mixer_ctrl_clear_pend_all(void)
+{
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_clear_pend_all();
+}
+
+void s5p_mixer_ctrl_stop(void)
+{
+	int i;
+
+	tvout_dbg("running(%d)\n", s5p_mixer_ctrl_private.running);
+	if (s5p_mixer_ctrl_private.running) {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+		} else
+#endif
+		{
+			s5p_mixer_set_vsync_interrupt(false);
+
+			for (i = 0; i < S5PTV_VP_BUFF_CNT -1; i++)
+				s5ptv_vp_buff.copy_buff_idxs[i] = i;
+
+			s5ptv_vp_buff.curr_copy_idx = 0;
+			s5ptv_vp_buff.vp_access_buff_idx = S5PTV_VP_BUFF_CNT - 1;
+
+			s5p_mixer_stop();
+			s5p_mixer_ctrl_clock(0);
+		}
+		s5p_mixer_ctrl_private.running = false;
+	}
+}
+
+void s5p_mixer_ctrl_internal_start(void)
+{
+	tvout_dbg("running(%d)\n", s5p_mixer_ctrl_private.running);
+	if (s5p_mixer_ctrl_private.running)
+		s5p_mixer_start();
+}
+
+int s5p_mixer_ctrl_start(
+	enum s5p_tvout_disp_mode disp, enum s5p_tvout_o_mode out)
+{
+	int i;
+
+	int csc = MIXER_RGB601_16_235;
+	int csc_for_coeff = MIXER_RGB601_0_255;
+	enum s5p_mixer_burst_mode burst = s5p_mixer_ctrl_private.burst;
+	enum s5p_tvout_endian endian = s5p_mixer_ctrl_private.endian;
+	struct clk *sclk_mixer = s5p_mixer_ctrl_private.clk[MUX].ptr;
+	bool mixer_video_limiter = true;
+
+	/*
+	 * Getting mega struct member variable will be replaced another tvout
+	 * interface
+	 */
+	struct s5p_tvout_status *st = &s5ptv_status;
+
+	tvout_dbg("running(%d)\n", s5p_mixer_ctrl_private.running);
+
+	switch (out) {
+	case TVOUT_COMPOSITE:
+		if (clk_set_parent(sclk_mixer, st->sclk_dac)) {
+			tvout_err("unable to set parent %s of clock %s.\n",
+				   st->sclk_dac->name, sclk_mixer->name);
+			return -1;
+		}
+
+		if (!s5p_mixer_ctrl_private.running) {
+			s5p_mixer_ctrl_clock(true);
+			s5p_mixer_ctrl_private.running = true;
+		}
+
+		csc = MIXER_RGB601_0_255;
+		csc_for_coeff = MIXER_RGB601_0_255;
+		break;
+
+	case TVOUT_HDMI_RGB:
+	case TVOUT_HDMI:
+	case TVOUT_DVI:
+		if (clk_set_parent(sclk_mixer, st->sclk_hdmi)) {
+			tvout_err("unable to set parent %s of clock %s.\n",
+				   st->sclk_hdmi->name, sclk_mixer->name);
+			return -1;
+		}
+
+		if (clk_set_parent(st->sclk_hdmi, st->sclk_hdmiphy)) {
+			tvout_err("unable to set parent %s of clock %s.\n",
+				   st->sclk_hdmiphy->name, st->sclk_hdmi->name);
+			return -1;
+		}
+
+		if (!s5p_mixer_ctrl_private.running) {
+			s5p_mixer_ctrl_clock(true);
+			s5p_mixer_ctrl_private.running = true;
+		}
+
+		switch (disp) {
+
+		case TVOUT_480P_60_4_3:
+			if (s5p_tvif_get_q_range() || out == TVOUT_HDMI_RGB)
+				csc = MIXER_RGB601_0_255;
+			else
+				csc = MIXER_RGB601_16_235;
+			csc_for_coeff = MIXER_RGB601_0_255;
+			break;
+		case TVOUT_480P_60_16_9:
+		case TVOUT_480P_59:
+		case TVOUT_576P_50_16_9:
+		case TVOUT_576P_50_4_3:
+			if (s5p_tvif_get_q_range() && out != TVOUT_HDMI_RGB)
+				csc = MIXER_RGB601_0_255;
+			else
+				csc = MIXER_RGB601_16_235;
+			csc_for_coeff = MIXER_RGB601_0_255;
+			break;
+		case TVOUT_720P_60:
+		case TVOUT_720P_50:
+		case TVOUT_720P_59:
+		case TVOUT_1080I_60:
+		case TVOUT_1080I_59:
+		case TVOUT_1080I_50:
+		case TVOUT_1080P_60:
+		case TVOUT_1080P_30:
+		case TVOUT_1080P_59:
+		case TVOUT_1080P_50:
+			if (!s5p_tvif_get_q_range() || out == TVOUT_HDMI_RGB)
+				csc = MIXER_RGB709_16_235;
+			else
+				csc = MIXER_RGB709_0_255;
+			csc_for_coeff = MIXER_RGB709_0_255;
+			break;
+#ifdef CONFIG_HDMI_14A_3D
+		case TVOUT_720P_60_SBS_HALF:
+		case TVOUT_720P_59_SBS_HALF:
+		case TVOUT_720P_50_TB:
+		case TVOUT_1080P_24_TB:
+		case TVOUT_1080P_23_TB:
+			if (!s5p_tvif_get_q_range() || out == TVOUT_HDMI_RGB)
+				csc = MIXER_RGB709_16_235;
+			else
+				csc = MIXER_RGB709_0_255;
+			csc_for_coeff = MIXER_RGB709_0_255;
+			break;
+
+#endif
+		default:
+			break;
+		}
+		break;
+
+	default:
+		tvout_err("invalid tvout output mode = %d\n", out);
+		return -1;
+	}
+
+	tvout_dbg("%s burst mode\n", burst ? "16" : "8");
+	tvout_dbg("%s endian\n", endian ? "big" : "little");
+
+	if ((burst != MIXER_BURST_8) && (burst != MIXER_BURST_16)) {
+		tvout_err("invalid burst mode\n");
+		return -1;
+	}
+
+	if ((endian != TVOUT_BIG_ENDIAN) && (endian != TVOUT_LITTLE_ENDIAN)) {
+		tvout_err("invalid endian\n");
+		return -1;
+	}
+
+	s5p_mixer_init_status_reg(burst, endian);
+
+	tvout_dbg("tvout standard = 0x%X, output mode = %d\n", disp, out);
+	/* error handling will be implemented */
+	tvout_dbg(KERN_INFO "Color range mode set : %d\n",
+		s5p_tvif_get_q_range());
+	s5p_mixer_init_csc_coef_default(csc_for_coeff);
+	s5p_mixer_init_display_mode(disp, out, csc);
+
+	if (!s5p_tvif_get_q_range() || out == TVOUT_HDMI_RGB)
+		mixer_video_limiter = true;
+	else
+		mixer_video_limiter = false;
+
+	s5p_mixer_set_video_limiter(s5p_mixer_ctrl_private.v_layer.y_min,
+			s5p_mixer_ctrl_private.v_layer.y_max,
+			s5p_mixer_ctrl_private.v_layer.c_min,
+			s5p_mixer_ctrl_private.v_layer.c_max,
+			mixer_video_limiter);
+
+	for (i = MIXER_BG_COLOR_0; i <= MIXER_BG_COLOR_2; i++) {
+		s5p_mixer_set_bg_color(i,
+			s5p_mixer_ctrl_private.bg_color[i].color_y,
+			s5p_mixer_ctrl_private.bg_color[i].color_cb,
+			s5p_mixer_ctrl_private.bg_color[i].color_cr);
+	}
+
+	if (s5p_mixer_ctrl_private.v_layer.use_video_layer) {
+		s5p_mixer_ctrl_set_reg(MIXER_VIDEO_LAYER);
+		s5p_mixer_set_show(MIXER_VIDEO_LAYER, true);
+	}
+	if (s5p_mixer_ctrl_private.layer[MIXER_GPR0_LAYER].use_grp_layer) {
+		s5p_mixer_ctrl_set_reg(MIXER_GPR0_LAYER);
+		s5p_mixer_set_show(MIXER_GPR0_LAYER, true);
+	}
+	if (s5p_mixer_ctrl_private.layer[MIXER_GPR1_LAYER].use_grp_layer) {
+		s5p_mixer_ctrl_set_reg(MIXER_GPR1_LAYER);
+		s5p_mixer_set_show(MIXER_GPR1_LAYER, true);
+	}
+
+	s5p_mixer_start();
+	if (s5p_mixer_ctrl_private.vsync_interrupt_enable)
+		s5p_mixer_set_vsync_interrupt(true);
+
+	return 0;
+}
+
+wait_queue_head_t s5ptv_wq;
+
+int s5p_mixer_ctrl_constructor(struct platform_device *pdev)
+{
+	int ret = 0, i;
+
+	ret = s5p_tvout_map_resource_mem(
+		pdev,
+		s5p_mixer_ctrl_private.reg_mem.name,
+		&(s5p_mixer_ctrl_private.reg_mem.base),
+		&(s5p_mixer_ctrl_private.reg_mem.res));
+
+	if (ret)
+		goto err_on_res;
+
+	for (i = ACLK; i < NO_OF_CLK; i++) {
+		s5p_mixer_ctrl_private.clk[i].ptr =
+			clk_get(&pdev->dev, s5p_mixer_ctrl_private.clk[i].name);
+
+		if (IS_ERR(s5p_mixer_ctrl_private.clk[i].ptr)) {
+			printk(KERN_ERR "Failed to find clock %s\n",
+				s5p_mixer_ctrl_private.clk[i].name);
+			ret = -ENOENT;
+			goto err_on_clk;
+		}
+	}
+
+	s5p_mixer_ctrl_private.irq.no =
+		platform_get_irq_byname(pdev, s5p_mixer_ctrl_private.irq.name);
+
+	if (s5p_mixer_ctrl_private.irq.no < 0) {
+		tvout_err("Failed to call platform_get_irq_byname() for %s\n",
+			s5p_mixer_ctrl_private.irq.name);
+		ret = s5p_mixer_ctrl_private.irq.no;
+		goto err_on_irq;
+	}
+
+	/* Initializing wait queue for mixer vsync interrupt */
+	init_waitqueue_head(&s5ptv_wq);
+
+	s5p_mixer_init(s5p_mixer_ctrl_private.reg_mem.base);
+
+	ret = request_irq(
+			s5p_mixer_ctrl_private.irq.no,
+			s5p_mixer_ctrl_private.irq.handler,
+			IRQF_DISABLED,
+			s5p_mixer_ctrl_private.irq.name,
+			NULL);
+	if (ret) {
+		tvout_err("Failed to call request_irq() for %s\n",
+			s5p_mixer_ctrl_private.irq.name);
+		goto err_on_irq;
+	}
+
+	return 0;
+
+err_on_irq:
+err_on_clk:
+	iounmap(s5p_mixer_ctrl_private.reg_mem.base);
+	release_resource(s5p_mixer_ctrl_private.reg_mem.res);
+	kfree(s5p_mixer_ctrl_private.reg_mem.res);
+
+err_on_res:
+	return ret;
+}
+
+void s5p_mixer_ctrl_destructor(void)
+{
+	int i;
+	int irq_no = s5p_mixer_ctrl_private.irq.no;
+
+	if (irq_no >= 0)
+		free_irq(irq_no, NULL);
+
+	s5p_tvout_unmap_resource_mem(
+		s5p_mixer_ctrl_private.reg_mem.base,
+		s5p_mixer_ctrl_private.reg_mem.res);
+
+	for (i = ACLK; i < NO_OF_CLK; i++) {
+		if (s5p_mixer_ctrl_private.clk[i].ptr) {
+			clk_disable(s5p_mixer_ctrl_private.clk[i].ptr);
+			clk_put(s5p_mixer_ctrl_private.clk[i].ptr);
+			s5p_mixer_init(NULL);
+		}
+	}
+}
+
+bool pm_running;
+
+void s5p_mixer_ctrl_suspend(void)
+{
+	tvout_dbg("running(%d)\n", s5p_mixer_ctrl_private.running);
+	/* Mixer clock will be gated by tvif_ctrl */
+}
+
+void s5p_mixer_ctrl_resume(void)
+{
+	tvout_dbg("running(%d)\n", s5p_mixer_ctrl_private.running);
+	/* Mixer clock will be gated by tvif_ctrl */
+}
diff --git a/drivers/media/video/samsung/tvout/s5p_tvif_ctrl.c b/drivers/media/video/samsung/tvout/s5p_tvif_ctrl.c
new file mode 100644
index 0000000..93cb640
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvif_ctrl.c
@@ -0,0 +1,2952 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvif_ctrl.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Tvout ctrl class for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*****************************************************************************
+ * This file includes functions for ctrl classes of TVOUT driver.
+ * There are 3 ctrl classes. (tvif, hdmi, sdo)
+ *	- tvif ctrl class: controls hdmi and sdo ctrl class.
+ *      - hdmi ctrl class: contrls hdmi hardware by using hw_if/hdmi.c
+ *      - sdo  ctrl class: contrls sdo hardware by using hw_if/sdo.c
+ *
+ *                      +-----------------+
+ *                      | tvif ctrl class |
+ *                      +-----------------+
+ *                             |   |
+ *                  +----------+   +----------+		    ctrl class layer
+ *                  |                         |
+ *                  V                         V
+ *         +-----------------+       +-----------------+
+ *         | sdo ctrl class  |       | hdmi ctrl class |
+ *         +-----------------+       +-----------------+
+ *                  |                         |
+ *   ---------------+-------------------------+------------------------------
+ *                  V                         V
+ *         +-----------------+       +-----------------+
+ *         |   hw_if/sdo.c   |       |   hw_if/hdmi.c  |         hw_if layer
+ *         +-----------------+       +-----------------+
+ *                  |                         |
+ *   ---------------+-------------------------+------------------------------
+ *                  V                         V
+ *         +-----------------+       +-----------------+
+ *         |   sdo hardware  |       |   hdmi hardware |	  Hardware
+ *         +-----------------+       +-----------------+
+ *
+ ****************************************************************************/
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <plat/clock.h>
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+#include <mach/dev.h>
+#endif
+
+#include "s5p_tvout_common_lib.h"
+#include "hw_if/hw_if.h"
+#include "s5p_tvout_ctrl.h"
+
+#ifdef CONFIG_HDMI_14A_3D
+static struct s5p_hdmi_v_format s5p_hdmi_v_fmt[] = {
+	[v720x480p_60Hz] = {
+		.frame = {
+			.vH_Line = 0x035a,
+			.vV_Line = 0x020d,
+			.vH_SYNC_START = 0x000e,
+			.vH_SYNC_END = 0x004c,
+			.vV1_Blank = 0x002d,
+			.vV2_Blank = 0x020d,
+			.vHBlank = 0x008a,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x9,
+			.vVSYNC_LINE_BEF_2 = 0x000f,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 1,
+			.Vsync_polarity = 1,
+			.interlaced = 0,
+			.vAVI_VIC = 2,
+			.vAVI_VIC_16_9 = 3,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_27_027,
+		},
+		.tg_H_FSZ = 0x35a,
+		.tg_HACT_ST = 0x8a,
+		.tg_HACT_SZ = 0x2d0,
+		.tg_V_FSZ = 0x20d,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x1e0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_60Hz] = {
+		.frame = {
+			.vH_Line = 0x0672,
+			.vV_Line = 0x02ee,
+			.vH_SYNC_START = 0x006c,
+			.vH_SYNC_END = 0x0094,
+			.vV1_Blank = 0x001e,
+			.vV2_Blank = 0x02ee,
+			.vHBlank = 0x0172,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 4,
+			.vAVI_VIC_16_9 = 4,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x672,
+		.tg_HACT_ST = 0x172,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_60Hz] = {
+		.frame = {
+			.vH_Line = 0x0898,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x0056,
+			.vH_SYNC_END = 0x0082,
+			.vV1_Blank = 0x0016,
+			.vV2_Blank = 0x0232,
+			.vHBlank = 0x0118,
+			.VBLANK_F0 = 0x0249,
+			.VBLANK_F1 = 0x0465,
+			.vVSYNC_LINE_BEF_1 = 0x2,
+			.vVSYNC_LINE_BEF_2 = 0x0007,
+			.vVSYNC_LINE_AFT_1 = 0x0234,
+			.vVSYNC_LINE_AFT_2 = 0x0239,
+			.vVSYNC_LINE_AFT_PXL_1 = 0x04a4,
+			.vVSYNC_LINE_AFT_PXL_2 = 0x04a4,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 1,
+			.vAVI_VIC = 5,
+			.vAVI_VIC_16_9 = 5,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x898,
+		.tg_HACT_ST = 0x118,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x16,
+		.tg_VACT_SZ = 0x21c,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x249,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x233,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_60Hz] = {
+		.frame = {
+			.vH_Line = 0x0898,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x0056,
+			.vH_SYNC_END = 0x0082,
+			.vV1_Blank = 0x002d,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x0118,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 16,
+			.vAVI_VIC_16_9 = 16,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_148_500,
+		},
+		.tg_H_FSZ = 0x898,
+		.tg_HACT_ST = 0x118,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v720x576p_50Hz] = {
+		.frame = {
+			.vH_Line = 0x0360,
+			.vV_Line = 0x0271,
+			.vH_SYNC_START = 0x000a,
+			.vH_SYNC_END = 0x004a,
+			.vV1_Blank = 0x0031,
+			.vV2_Blank = 0x0271,
+			.vHBlank = 0x0090,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 1,
+			.Vsync_polarity = 1,
+			.interlaced = 0,
+			.vAVI_VIC = 17,
+			.vAVI_VIC_16_9 = 18,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_27,
+		},
+		.tg_H_FSZ = 0x360,
+		.tg_HACT_ST = 0x90,
+		.tg_HACT_SZ = 0x2d0,
+		.tg_V_FSZ = 0x271,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x31,
+		.tg_VACT_SZ = 0x240,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_50Hz] = {
+		.frame = {
+			.vH_Line = 0x07BC,
+			.vV_Line = 0x02EE,
+			.vH_SYNC_START = 0x01b6,
+			.vH_SYNC_END = 0x01de,
+			.vV1_Blank = 0x001E,
+			.vV2_Blank = 0x02EE,
+			.vHBlank = 0x02BC,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 19,
+			.vAVI_VIC_16_9 = 19,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x7bc,
+		.tg_HACT_ST = 0x2bc,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_50Hz] = {
+		.frame = {
+			.vH_Line = 0x0A50,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x020e,
+			.vH_SYNC_END = 0x023a,
+			.vV1_Blank = 0x0016,
+			.vV2_Blank = 0x0232,
+			.vHBlank = 0x02D0,
+			.VBLANK_F0 = 0x0249,
+			.VBLANK_F1 = 0x0465,
+			.vVSYNC_LINE_BEF_1 = 0x2,
+			.vVSYNC_LINE_BEF_2 = 0x0007,
+			.vVSYNC_LINE_AFT_1 = 0x0234,
+			.vVSYNC_LINE_AFT_2 = 0x0239,
+			.vVSYNC_LINE_AFT_PXL_1 = 0x0738,
+			.vVSYNC_LINE_AFT_PXL_2 = 0x0738,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 1,
+			.vAVI_VIC = 20,
+			.vAVI_VIC_16_9 = 20,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0xa50,
+		.tg_HACT_ST = 0x2d0,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x16,
+		.tg_VACT_SZ = 0x21c,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x249,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x233,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_50Hz] = {
+		.frame = {
+			.vH_Line = 0x0A50,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x020e,
+			.vH_SYNC_END = 0x023a,
+			.vV1_Blank = 0x002D,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x02D0,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 31,
+			.vAVI_VIC_16_9 = 31,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_148_500,
+		},
+		.tg_H_FSZ = 0xa50,
+		.tg_HACT_ST = 0x2d0,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_30Hz] = {
+		.frame = {
+			.vH_Line = 0x0898,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x056,
+			.vH_SYNC_END = 0x082,
+			.vV1_Blank = 0x002D,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x0118,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 34,
+			.vAVI_VIC_16_9 = 34,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_176,
+		},
+		.tg_H_FSZ = 0x898,
+		.tg_HACT_ST = 0x118,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v720x480p_59Hz] = {
+		.frame = {
+			.vH_Line = 0x035a,
+			.vV_Line = 0x020d,
+			.vH_SYNC_START = 0x000e,
+			.vH_SYNC_END = 0x004c,
+			.vV1_Blank = 0x002D,
+			.vV2_Blank = 0x020d,
+			.vHBlank = 0x008a,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x9,
+			.vVSYNC_LINE_BEF_2 = 0x000f,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 1,
+			.Vsync_polarity = 1,
+			.interlaced = 0,
+			.vAVI_VIC = 2,
+			.vAVI_VIC_16_9 = 3,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_27,
+		},
+		.tg_H_FSZ = 0x35a,
+		.tg_HACT_ST = 0x8a,
+		.tg_HACT_SZ = 0x2d0,
+		.tg_V_FSZ = 0x20d,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x1e0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_59Hz] = {
+		.frame = {
+			.vH_Line = 0x0672,
+			.vV_Line = 0x02ee,
+			.vH_SYNC_START = 0x006c,
+			.vH_SYNC_END = 0x0094,
+			.vV1_Blank = 0x001e,
+			.vV2_Blank = 0x02ee,
+			.vHBlank = 0x0172,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 4,
+			.vAVI_VIC_16_9 = 4,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_176,
+		},
+		.tg_H_FSZ = 0x672,
+		.tg_HACT_ST = 0x172,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_59Hz] = {
+		.frame = {
+			.vH_Line = 0x0898,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x0056,
+			.vH_SYNC_END = 0x0082,
+			.vV1_Blank = 0x0016,
+			.vV2_Blank = 0x0232,
+			.vHBlank = 0x0118,
+			.VBLANK_F0 = 0x0249,
+			.VBLANK_F1 = 0x0465,
+			.vVSYNC_LINE_BEF_1 = 0x2,
+			.vVSYNC_LINE_BEF_2 = 0x0007,
+			.vVSYNC_LINE_AFT_1 = 0x0234,
+			.vVSYNC_LINE_AFT_2 = 0x0239,
+			.vVSYNC_LINE_AFT_PXL_1 = 0x04a4,
+			.vVSYNC_LINE_AFT_PXL_2 = 0x04a4,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 1,
+			.vAVI_VIC = 5,
+			.vAVI_VIC_16_9 = 5,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_176,
+		},
+		.tg_H_FSZ = 0x898,
+		.tg_HACT_ST = 0x118,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x16,
+		.tg_VACT_SZ = 0x21c,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x249,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x233,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_59Hz] = {
+		.frame = {
+			.vH_Line = 0x0898,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x0056,
+			.vH_SYNC_END = 0x0082,
+			.vV1_Blank = 0x002d,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x0118,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 16,
+			.vAVI_VIC_16_9 = 16,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_148_352,
+		},
+		.tg_H_FSZ = 0x898,
+		.tg_HACT_ST = 0x118,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_60Hz_SBS_HALF] = {
+		.frame = {
+			.vH_Line = 0x0672,
+			.vV_Line = 0x02ee,
+			.vH_SYNC_START = 0x006c,
+			.vH_SYNC_END = 0x0094,
+			.vV1_Blank = 0x001e,
+			.vV2_Blank = 0x02ee,
+			.vHBlank = 0x0172,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 4,
+			.vAVI_VIC_16_9 = 4,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x672,
+		.tg_HACT_ST = 0x172,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x30c,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_59Hz_SBS_HALF] = {
+		.frame = {
+			.vH_Line = 0x0672,
+			.vV_Line = 0x02ee,
+			.vH_SYNC_START = 0x006c,
+			.vH_SYNC_END = 0x0094,
+			.vV1_Blank = 0x001e,
+			.vV2_Blank = 0x02ee,
+			.vHBlank = 0x0172,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 4,
+			.vAVI_VIC_16_9 = 4,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x672,
+		.tg_HACT_ST = 0x172,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x0,
+		.tg_VACT_ST2 = 0x30c,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_50Hz_TB] = {
+		.frame = {
+			.vH_Line = 0x07bc,
+			.vV_Line = 0x02ee,
+			.vH_SYNC_START = 0x01b6,
+			.vH_SYNC_END = 0x01de,
+			.vV1_Blank = 0x001e,
+			.vV2_Blank = 0x02ee,
+			.vHBlank = 0x02bc,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x5,
+			.vVSYNC_LINE_BEF_2 = 0x000a,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 19,
+			.vAVI_VIC_16_9 = 19,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0x7bc,
+		.tg_HACT_ST = 0x2bc,
+		.tg_HACT_SZ = 0x500,
+		.tg_V_FSZ = 0x2ee,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x1e,
+		.tg_VACT_SZ = 0x2d0,
+		.tg_FIELD_CHG = 0x0,
+		.tg_VACT_ST2 = 0x30c,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_24Hz_TB] = {
+		.frame = {
+			.vH_Line = 0x0abe,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x027c,
+			.vH_SYNC_END = 0x02a8,
+			.vV1_Blank = 0x002d,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x033e,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 32,
+			.vAVI_VIC_16_9 = 32,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0xabe,
+		.tg_HACT_ST = 0x33e,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_23Hz_TB] = {
+		.frame = {
+			.vH_Line = 0x0abe,
+			.vV_Line = 0x0465,
+			.vH_SYNC_START = 0x027c,
+			.vH_SYNC_END = 0x02a8,
+			.vV1_Blank = 0x002d,
+			.vV2_Blank = 0x0465,
+			.vHBlank = 0x033e,
+			.VBLANK_F0 = 0xffff,
+			.VBLANK_F1 = 0xffff,
+			.vVSYNC_LINE_BEF_1 = 0x4,
+			.vVSYNC_LINE_BEF_2 = 0x0009,
+			.vVSYNC_LINE_AFT_1 = 0xffff,
+			.vVSYNC_LINE_AFT_2 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_1 = 0xffff,
+			.vVSYNC_LINE_AFT_PXL_2 = 0xffff,
+			.vVACT_SPACE_1 = 0xffff,
+			.vVACT_SPACE_2 = 0xffff,
+			.Hsync_polarity = 0,
+			.Vsync_polarity = 0,
+			.interlaced = 0,
+			.vAVI_VIC = 32,
+			.vAVI_VIC_16_9 = 32,
+			.repetition = 0,
+			.pixel_clock = ePHY_FREQ_74_250,
+		},
+		.tg_H_FSZ = 0xabe,
+		.tg_HACT_ST = 0x33e,
+		.tg_HACT_SZ = 0x780,
+		.tg_V_FSZ = 0x465,
+		.tg_VSYNC = 0x1,
+		.tg_VSYNC2 = 0x233,
+		.tg_VACT_ST = 0x2d,
+		.tg_VACT_SZ = 0x438,
+		.tg_FIELD_CHG = 0x233,
+		.tg_VACT_ST2 = 0x248,
+		.tg_VACT_ST3 = 0x0,
+		.tg_VACT_ST4 = 0x0,
+		.tg_VSYNC_TOP_HDMI = 0x1,
+		.tg_VSYNC_BOT_HDMI = 0x1,
+		.tg_FIELD_TOP_HDMI = 0x1,
+		.tg_FIELD_BOT_HDMI = 0x233,
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+};
+#else
+static struct s5p_hdmi_v_format s5p_hdmi_v_fmt[] = {
+	[v720x480p_60Hz] = {
+		.frame = {
+			.vic		= 2,
+			.vic_16_9	= 3,
+			.repetition	= 0,
+			.polarity	= 1,
+			.i_p		= 0,
+			.h_active	= 720,
+			.v_active	= 480,
+			.h_total	= 858,
+			.h_blank	= 138,
+			.v_total	= 525,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_27_027,
+		},
+		.h_sync = {
+			.begin		= 0xe,
+			.end		= 0x4c,
+		},
+		.v_sync_top = {
+			.begin		= 0x9,
+			.end		= 0xf,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_60Hz] = {
+		.frame = {
+			.vic		= 4,
+			.vic_16_9	= 4,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1280,
+			.v_active	= 720,
+			.h_total	= 1650,
+			.h_blank	= 370,
+			.v_total	= 750,
+			.v_blank	= 30,
+			.pixel_clock	= ePHY_FREQ_74_250,
+		},
+		.h_sync = {
+			.begin		= 0x6c,
+			.end		= 0x94,
+		},
+		.v_sync_top = {
+			.begin		= 0x5,
+			.end		= 0xa,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_60Hz] = {
+		.frame = {
+			.vic		= 5,
+			.vic_16_9	= 5,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 1,
+			.h_active	= 1920,
+			.v_active	= 540,
+			.h_total	= 2200,
+			.h_blank	= 280,
+			.v_total	= 1125,
+			.v_blank	= 22,
+			.pixel_clock	= ePHY_FREQ_74_250,
+		},
+		.h_sync = {
+			.begin		= 0x56,
+			.end		= 0x82,
+		},
+		.v_sync_top = {
+			.begin		= 0x2,
+			.end		= 0x7,
+		},
+		.v_sync_bottom = {
+			.begin		= 0x234,
+			.end		= 0x239,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0x4a4,
+			.end		= 0x4a4,
+		},
+		.v_blank_f = {
+			.begin		= 0x249,
+			.end		= 0x465,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_60Hz] = {
+		.frame = {
+			.vic		= 16,
+			.vic_16_9	= 16,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1920,
+			.v_active	= 1080,
+			.h_total	= 2200,
+			.h_blank	= 280,
+			.v_total	= 1125,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_148_500,
+		},
+		.h_sync = {
+			.begin		= 0x56,
+			.end		= 0x82,
+		},
+		.v_sync_top = {
+			.begin		= 0x4,
+			.end		= 0x9,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v720x576p_50Hz] = {
+		.frame = {
+			.vic		= 17,
+			.vic_16_9	= 18,
+			.repetition	= 0,
+			.polarity	= 1,
+			.i_p		= 0,
+			.h_active	= 720,
+			.v_active	= 576,
+			.h_total	= 864,
+			.h_blank	= 144,
+			.v_total	= 625,
+			.v_blank	= 49,
+			.pixel_clock	= ePHY_FREQ_27,
+		},
+		.h_sync = {
+			.begin		= 0xa,
+			.end		= 0x4a,
+		},
+		.v_sync_top = {
+			.begin		= 0x5,
+			.end		= 0xa,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_50Hz] = {
+		.frame = {
+			.vic		= 19,
+			.vic_16_9	= 19,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1280,
+			.v_active	= 720,
+			.h_total	= 1980,
+			.h_blank	= 700,
+			.v_total	= 750,
+			.v_blank	= 30,
+			.pixel_clock	= ePHY_FREQ_74_250,
+		},
+		.h_sync = {
+			.begin		= 0x1b6,
+			.end		= 0x1de,
+		},
+		.v_sync_top = {
+			.begin		= 0x5,
+			.end		= 0xa,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_50Hz] = {
+		.frame = {
+			.vic		= 20,
+			.vic_16_9	= 20,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 1,
+			.h_active	= 1920,
+			.v_active	= 540,
+			.h_total	= 2640,
+			.h_blank	= 720,
+			.v_total	= 1125,
+			.v_blank	= 22,
+			.pixel_clock	= ePHY_FREQ_74_250,
+		},
+		.h_sync = {
+			.begin		= 0x20e,
+			.end		= 0x23a,
+		},
+		.v_sync_top = {
+			.begin		= 0x2,
+			.end		= 0x7,
+		},
+		.v_sync_bottom = {
+			.begin		= 0x234,
+			.end		= 0x239,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0x738,
+			.end		= 0x738,
+		},
+		.v_blank_f = {
+			.begin		= 0x249,
+			.end		= 0x465,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_50Hz] = {
+		.frame = {
+			.vic		= 31,
+			.vic_16_9	= 31,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1920,
+			.v_active	= 1080,
+			.h_total	= 2640,
+			.h_blank	= 720,
+			.v_total	= 1125,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_148_500,
+		},
+		.h_sync = {
+			.begin		= 0x20e,
+			.end		= 0x23a,
+		},
+		.v_sync_top = {
+			.begin		= 0x4,
+			.end		= 0x9,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_30Hz] = {
+		.frame = {
+			.vic		= 34,
+			.vic_16_9	= 34,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1920,
+			.v_active	= 1080,
+			.h_total	= 2200,
+			.h_blank	= 280,
+			.v_total	= 1125,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_74_250,
+		},
+		.h_sync = {
+			.begin		= 0x56,
+			.end		= 0x82,
+		},
+		.v_sync_top = {
+			.begin		= 0x4,
+			.end		= 0x9,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v720x480p_59Hz] = {
+		.frame = {
+			.vic		= 2,
+			.vic_16_9	= 3,
+			.repetition	= 0,
+			.polarity	= 1,
+			.i_p		= 0,
+			.h_active	= 720,
+			.v_active	= 480,
+			.h_total	= 858,
+			.h_blank	= 138,
+			.v_total	= 525,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_27,
+		},
+		.h_sync = {
+			.begin		= 0xe,
+			.end		= 0x4c,
+		},
+		.v_sync_top = {
+			.begin		= 0x9,
+			.end		= 0xf,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1280x720p_59Hz] = {
+		.frame = {
+			.vic		= 4,
+			.vic_16_9	= 4,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1280,
+			.v_active	= 720,
+			.h_total	= 1650,
+			.h_blank	= 370,
+			.v_total	= 750,
+			.v_blank	= 30,
+			.pixel_clock	= ePHY_FREQ_74_176,
+		},
+		.h_sync = {
+			.begin		= 0x6c,
+			.end		= 0x94,
+		},
+		.v_sync_top = {
+			.begin		= 0x5,
+			.end		= 0xa,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080i_59Hz] = {
+		.frame = {
+			.vic		= 5,
+			.vic_16_9	= 5,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 1,
+			.h_active	= 1920,
+			.v_active	= 540,
+			.h_total	= 2200,
+			.h_blank	= 280,
+			.v_total	= 1125,
+			.v_blank	= 22,
+			.pixel_clock	= ePHY_FREQ_74_176,
+		},
+		.h_sync = {
+			.begin		= 0x56,
+			.end		= 0x82,
+		},
+		.v_sync_top = {
+			.begin		= 0x2,
+			.end		= 0x7,
+		},
+		.v_sync_bottom = {
+			.begin		= 0x234,
+			.end		= 0x239,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0x4a4,
+			.end		= 0x4a4,
+		},
+		.v_blank_f = {
+			.begin		= 0x249,
+			.end		= 0x465,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+
+	[v1920x1080p_59Hz] = {
+		.frame = {
+			.vic		= 16,
+			.vic_16_9	= 16,
+			.repetition	= 0,
+			.polarity	= 0,
+			.i_p		= 0,
+			.h_active	= 1920,
+			.v_active	= 1080,
+			.h_total	= 2200,
+			.h_blank	= 280,
+			.v_total	= 1125,
+			.v_blank	= 45,
+			.pixel_clock	= ePHY_FREQ_148_352,
+		},
+		.h_sync = {
+			.begin		= 0x56,
+			.end		= 0x82,
+		},
+		.v_sync_top = {
+			.begin		= 0x4,
+			.end		= 0x9,
+		},
+		.v_sync_bottom = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_sync_h_pos = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.v_blank_f = {
+			.begin		= 0,
+			.end		= 0,
+		},
+		.mhl_hsync = 0xf,
+		.mhl_vsync = 0x1,
+	},
+};
+#endif
+
+static struct s5p_hdmi_o_params s5p_hdmi_output[] = {
+	{
+		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x00, 0x00, 0x00, 0x00},
+	}, {
+		{0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04},
+		{0x40, 0x00, 0x02, 0x40, 0x00},
+	}, {
+		{0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04},
+		{0x00, 0x00, 0x02, 0x20, 0x00},
+	}, {
+		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+		{0x00, 0x22, 0x01, 0x20, 0x01},
+	},
+};
+
+static struct s5p_hdmi_ctrl_private_data s5p_hdmi_ctrl_private = {
+	.vendor		= "SAMSUNG",
+	.product	= "S5PC210",
+
+	.blue_screen = {
+		.enable = false,
+#ifdef	CONFIG_HDMI_14A_3D
+		.b	= 0,
+		.g	= 0,
+		.r	= 0,
+#else
+		.cb_b	= 0,
+		.y_g	= 0,
+		.cr_r	= 0,
+#endif
+	},
+
+	.video = {
+		.color_r = {
+			.y_min = 0x10,
+			.y_max = 0xeb,
+			.c_min = 0x10,
+			.c_max = 0xf0,
+		},
+		.depth	= HDMI_CD_24,
+		.q_range = HDMI_Q_LIMITED_RANGE,
+	},
+
+	.packet = {
+		.vsi_info = {0x81, 0x1, 27},
+		.avi_info = {0x82, 0x2, 13},
+		.spd_info = {0x83, 0x1, 27},
+		.aui_info = {0x84, 0x1, 0x0a},
+		.mpg_info = {0x85, 0x1, 5},
+	},
+
+	.tg = {
+		.correction_en	= false,
+		.bt656_en	= false,
+	},
+
+	.hdcp_en = false,
+
+	.audio = {
+		.type	= HDMI_60958_AUDIO,
+		.bit	= 16,
+		.freq	= 44100,
+		/* Support audio 5.1Ch */
+#if defined(CONFIG_VIDEO_TVOUT_2CH_AUDIO)
+		.channel = 2,
+#else
+		.channel = 6,
+#endif
+	},
+
+	.av_mute	= false,
+	.running	= false,
+
+	.pow_name = "hdmi_pd",
+
+	.clk[HDMI_PCLK] = {
+		.name = "hdmi",
+		.ptr = NULL
+	},
+
+	.clk[HDMI_MUX] = {
+		.name = "sclk_hdmi",
+		.ptr = NULL
+	},
+
+	.reg_mem[HDMI] = {
+		.name = "s5p-hdmi",
+		.res = NULL,
+		.base = NULL
+	},
+
+	.reg_mem[HDMI_PHY] = {
+		.name = "s5p-i2c-hdmi-phy",
+		.res = NULL,
+		.base = NULL
+	},
+
+	.irq = {
+		.name = "s5p-hdmi",
+		.handler = s5p_hdmi_irq,
+		.no = -1
+	}
+
+};
+
+static struct s5p_tvif_ctrl_private_data s5p_tvif_ctrl_private = {
+	.curr_std = TVOUT_INIT_DISP_VALUE,
+	.curr_if = TVOUT_INIT_O_VALUE,
+
+	.running = false
+};
+
+#ifdef CONFIG_ANALOG_TVENC
+struct s5p_sdo_ctrl_private_data {
+	struct s5p_sdo_vscale_cfg		video_scale_cfg;
+	struct s5p_sdo_vbi			vbi;
+	struct s5p_sdo_offset_gain		offset_gain;
+	struct s5p_sdo_delay			delay;
+	struct s5p_sdo_bright_hue_saturation	bri_hue_sat;
+	struct s5p_sdo_cvbs_compensation	cvbs_compen;
+	struct s5p_sdo_component_porch		compo_porch;
+	struct s5p_sdo_ch_xtalk_cancellat_coeff	xtalk_cc;
+	struct s5p_sdo_closed_caption		closed_cap;
+	struct s5p_sdo_525_data			wss_525;
+	struct s5p_sdo_625_data			wss_625;
+	struct s5p_sdo_525_data			cgms_525;
+	struct s5p_sdo_625_data			cgms_625;
+
+	bool			color_sub_carrier_phase_adj;
+
+	bool			running;
+
+	struct s5p_tvout_clk_info	clk[SDO_NO_OF_CLK];
+	char			*pow_name;
+	struct reg_mem_info	reg_mem;
+};
+
+static struct s5p_sdo_ctrl_private_data s5p_sdo_ctrl_private = {
+	.clk[SDO_PCLK] = {
+		.name			= "tvenc",
+		.ptr			= NULL
+	},
+	.clk[SDO_MUX] = {
+		.name			= "sclk_dac",
+		.ptr			= NULL
+	},
+		.pow_name		= "tv_enc_pd",
+	.reg_mem = {
+		.name			= "s5p-sdo",
+		.res			= NULL,
+		.base			= NULL
+	},
+
+	.running			= false,
+
+	.color_sub_carrier_phase_adj	= false,
+
+	.vbi = {
+		.wss_cvbs		= true,
+		.caption_cvbs		= SDO_INS_OTHERS
+	},
+
+	.offset_gain = {
+		.offset			= 0,
+		.gain			= 0x800
+	},
+
+	.delay = {
+		.delay_y		= 0x00,
+		.offset_video_start	= 0xfa,
+		.offset_video_end	= 0x00
+	},
+
+	.bri_hue_sat = {
+		.bright_hue_sat_adj	= false,
+		.gain_brightness	= 0x80,
+		.offset_brightness	= 0x00,
+		.gain0_cb_hue_sat	= 0x00,
+		.gain1_cb_hue_sat	= 0x00,
+		.gain0_cr_hue_sat	= 0x00,
+		.gain1_cr_hue_sat	= 0x00,
+		.offset_cb_hue_sat	= 0x00,
+		.offset_cr_hue_sat	= 0x00
+	},
+
+	.cvbs_compen = {
+		.cvbs_color_compen	= false,
+		.y_lower_mid		= 0x200,
+		.y_bottom		= 0x000,
+		.y_top			= 0x3ff,
+		.y_upper_mid		= 0x200,
+		.radius			= 0x1ff
+	},
+
+	.compo_porch = {
+		.back_525		= 0x8a,
+		.front_525		= 0x359,
+		.back_625		= 0x96,
+		.front_625		= 0x35c
+	},
+
+	.xtalk_cc = {
+		.coeff2			= 0,
+		.coeff1			= 0
+	},
+
+	.closed_cap = {
+		.display_cc		= 0,
+		.nondisplay_cc		= 0
+	},
+
+	.wss_525 = {
+		.copy_permit		= SDO_525_COPY_PERMIT,
+		.mv_psp			= SDO_525_MV_PSP_OFF,
+		.copy_info		= SDO_525_COPY_INFO,
+		.analog_on		= false,
+		.display_ratio		= SDO_525_4_3_NORMAL
+	},
+
+	.wss_625 = {
+		.surround_sound		= false,
+		.copyright		= false,
+		.copy_protection	= false,
+		.text_subtitles		= false,
+		.open_subtitles		= SDO_625_NO_OPEN_SUBTITLES,
+		.camera_film		= SDO_625_CAMERA,
+		.color_encoding		= SDO_625_NORMAL_PAL,
+		.helper_signal		= false,
+		.display_ratio		= SDO_625_4_3_FULL_576
+	},
+
+	.cgms_525 = {
+		.copy_permit		= SDO_525_COPY_PERMIT,
+		.mv_psp			= SDO_525_MV_PSP_OFF,
+		.copy_info		= SDO_525_COPY_INFO,
+		.analog_on		= false,
+		.display_ratio		= SDO_525_4_3_NORMAL
+	},
+
+	.cgms_625 = {
+		.surround_sound		= false,
+		.copyright		= false,
+		.copy_protection	= false,
+		.text_subtitles		= false,
+		.open_subtitles		= SDO_625_NO_OPEN_SUBTITLES,
+		.camera_film		= SDO_625_CAMERA,
+		.color_encoding		= SDO_625_NORMAL_PAL,
+		.helper_signal		= false,
+		.display_ratio		= SDO_625_4_3_FULL_576
+	},
+};
+#endif
+
+/****************************************
+ * Functions for sdo ctrl class
+ ***************************************/
+#ifdef CONFIG_ANALOG_TVENC
+
+static void s5p_sdo_ctrl_init_private(void)
+{
+}
+
+static int s5p_sdo_ctrl_set_reg(enum s5p_tvout_disp_mode disp_mode)
+{
+	struct s5p_sdo_ctrl_private_data *private = &s5p_sdo_ctrl_private;
+
+	s5p_sdo_sw_reset(1);
+
+	if (s5p_sdo_set_display_mode(disp_mode, SDO_O_ORDER_COMPOSITE_Y_C_CVBS))
+		return -1;
+
+	if (s5p_sdo_set_video_scale_cfg(
+		private->video_scale_cfg.composite_level,
+		private->video_scale_cfg.composite_ratio))
+		return -1;
+
+	if (s5p_sdo_set_vbi(
+		private->vbi.wss_cvbs, private->vbi.caption_cvbs))
+		return -1;
+
+	s5p_sdo_set_offset_gain(
+		private->offset_gain.offset, private->offset_gain.gain);
+
+	s5p_sdo_set_delay(
+		private->delay.delay_y,
+		private->delay.offset_video_start,
+		private->delay.offset_video_end);
+
+	s5p_sdo_set_schlock(private->color_sub_carrier_phase_adj);
+
+	s5p_sdo_set_brightness_hue_saturation(private->bri_hue_sat);
+
+	s5p_sdo_set_cvbs_color_compensation(private->cvbs_compen);
+
+	s5p_sdo_set_component_porch(
+		private->compo_porch.back_525,
+		private->compo_porch.front_525,
+		private->compo_porch.back_625,
+		private->compo_porch.front_625);
+
+	s5p_sdo_set_ch_xtalk_cancel_coef(
+		private->xtalk_cc.coeff2, private->xtalk_cc.coeff1);
+
+	s5p_sdo_set_closed_caption(
+		private->closed_cap.display_cc,
+		private->closed_cap.nondisplay_cc);
+
+	if (s5p_sdo_set_wss525_data(private->wss_525))
+		return -1;
+
+	if (s5p_sdo_set_wss625_data(private->wss_625))
+		return -1;
+
+	if (s5p_sdo_set_cgmsa525_data(private->cgms_525))
+		return -1;
+
+	if (s5p_sdo_set_cgmsa625_data(private->cgms_625))
+		return -1;
+
+	s5p_sdo_set_interrupt_enable(0);
+
+	s5p_sdo_clear_interrupt_pending();
+
+	s5p_sdo_clock_on(1);
+	s5p_sdo_dac_on(1);
+
+	return 0;
+}
+
+static void s5p_sdo_ctrl_internal_stop(void)
+{
+	s5p_sdo_clock_on(0);
+	s5p_sdo_dac_on(0);
+}
+
+static void s5p_sdo_ctrl_clock(bool on)
+{
+	if (on) {
+		clk_enable(s5p_sdo_ctrl_private.clk[SDO_MUX].ptr);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_get();
+#endif
+		// Restore sdo_base address
+		s5p_sdo_init(s5p_sdo_ctrl_private.reg_mem.base);
+
+		clk_enable(s5p_sdo_ctrl_private.clk[SDO_PCLK].ptr);
+	} else {
+		clk_disable(s5p_sdo_ctrl_private.clk[SDO_PCLK].ptr);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_put();
+#endif
+
+		clk_disable(s5p_sdo_ctrl_private.clk[SDO_MUX].ptr);
+
+		// Set sdo_base address to NULL
+		s5p_sdo_init(NULL);
+	}
+
+	mdelay(50);
+}
+
+#ifdef CONFIG_ANALOG_TVENC
+#ifndef CONFIG_VPLL_USE_FOR_TVENC
+static void s5p_tvenc_src_to_hdmiphy_on(void);
+static void s5p_tvenc_src_to_hdmiphy_off(void);
+#endif
+#endif
+
+void s5p_sdo_ctrl_stop(void)
+{
+	if (s5p_sdo_ctrl_private.running) {
+		s5p_sdo_ctrl_internal_stop();
+		s5p_sdo_ctrl_clock(0);
+
+#ifdef CONFIG_ANALOG_TVENC
+#ifndef CONFIG_VPLL_USE_FOR_TVENC
+		s5p_tvenc_src_to_hdmiphy_off();
+#endif
+#endif
+
+		s5p_sdo_ctrl_private.running = false;
+	}
+}
+
+int s5p_sdo_ctrl_start(enum s5p_tvout_disp_mode disp_mode)
+{
+	struct s5p_sdo_ctrl_private_data *sdo_private = &s5p_sdo_ctrl_private;
+
+	switch (disp_mode) {
+	case TVOUT_NTSC_M:
+	case TVOUT_NTSC_443:
+		sdo_private->video_scale_cfg.composite_level =
+			SDO_LEVEL_75IRE;
+		sdo_private->video_scale_cfg.composite_ratio =
+			SDO_VTOS_RATIO_10_4;
+		break;
+
+	case TVOUT_PAL_BDGHI:
+	case TVOUT_PAL_M:
+	case TVOUT_PAL_N:
+	case TVOUT_PAL_NC:
+	case TVOUT_PAL_60:
+		sdo_private->video_scale_cfg.composite_level =
+			SDO_LEVEL_0IRE;
+		sdo_private->video_scale_cfg.composite_ratio =
+			SDO_VTOS_RATIO_7_3;
+		break;
+
+	default:
+		tvout_err("invalid disp_mode(%d) for SDO\n",
+			disp_mode);
+		goto err_on_s5p_sdo_start;
+	}
+
+	if (sdo_private->running)
+		s5p_sdo_ctrl_internal_stop();
+	else {
+		s5p_sdo_ctrl_clock(1);
+
+#ifdef CONFIG_ANALOG_TVENC
+#ifndef CONFIG_VPLL_USE_FOR_TVENC
+		s5p_tvenc_src_to_hdmiphy_on();
+#endif
+#endif
+
+		sdo_private->running = true;
+	}
+
+	if (s5p_sdo_ctrl_set_reg(disp_mode))
+		goto err_on_s5p_sdo_start;
+
+	return 0;
+
+err_on_s5p_sdo_start:
+	return -1;
+}
+
+int s5p_sdo_ctrl_constructor(struct platform_device *pdev)
+{
+	int ret;
+	int i, j;
+
+	ret = s5p_tvout_map_resource_mem(
+		pdev,
+		s5p_sdo_ctrl_private.reg_mem.name,
+		&(s5p_sdo_ctrl_private.reg_mem.base),
+		&(s5p_sdo_ctrl_private.reg_mem.res));
+
+	if (ret)
+		goto err_on_res;
+
+	for (i = SDO_PCLK; i < SDO_NO_OF_CLK; i++) {
+		s5p_sdo_ctrl_private.clk[i].ptr =
+			clk_get(&pdev->dev, s5p_sdo_ctrl_private.clk[i].name);
+
+		if (IS_ERR(s5p_sdo_ctrl_private.clk[i].ptr)) {
+			tvout_err("Failed to find clock %s\n",
+					s5p_sdo_ctrl_private.clk[i].name);
+			ret = -ENOENT;
+			goto err_on_clk;
+		}
+	}
+
+	s5p_sdo_ctrl_init_private();
+	s5p_sdo_init(s5p_sdo_ctrl_private.reg_mem.base);
+
+	return 0;
+
+err_on_clk:
+	for (j = 0; j < i; j++)
+		clk_put(s5p_sdo_ctrl_private.clk[j].ptr);
+
+	s5p_tvout_unmap_resource_mem(
+		s5p_sdo_ctrl_private.reg_mem.base,
+		s5p_sdo_ctrl_private.reg_mem.res);
+
+err_on_res:
+	return ret;
+}
+
+void s5p_sdo_ctrl_destructor(void)
+{
+	int i;
+
+	s5p_tvout_unmap_resource_mem(
+		s5p_sdo_ctrl_private.reg_mem.base,
+		s5p_sdo_ctrl_private.reg_mem.res);
+
+	for (i = SDO_PCLK; i < SDO_NO_OF_CLK; i++)
+		if (s5p_sdo_ctrl_private.clk[i].ptr) {
+			if (s5p_sdo_ctrl_private.running)
+				clk_disable(s5p_sdo_ctrl_private.clk[i].ptr);
+			clk_put(s5p_sdo_ctrl_private.clk[i].ptr);
+	}
+	s5p_sdo_init(NULL);
+}
+#endif
+
+
+
+
+/****************************************
+ * Functions for hdmi ctrl class
+ ***************************************/
+
+static enum s5p_hdmi_v_mode s5p_hdmi_check_v_fmt(enum s5p_tvout_disp_mode disp)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct s5p_hdmi_video			*video = &ctrl->video;
+	enum s5p_hdmi_v_mode			mode;
+
+	video->aspect		= HDMI_PIC_RATIO_16_9;
+	video->colorimetry	= HDMI_CLRIMETRY_601;
+
+	switch (disp) {
+	case TVOUT_480P_60_16_9:
+		mode = v720x480p_60Hz;
+		break;
+
+	case TVOUT_480P_60_4_3:
+		mode = v720x480p_60Hz;
+		video->aspect = HDMI_PIC_RATIO_4_3;
+		break;
+
+	case TVOUT_480P_59:
+		mode = v720x480p_59Hz;
+		break;
+
+	case TVOUT_576P_50_16_9:
+		mode = v720x576p_50Hz;
+		break;
+
+	case TVOUT_576P_50_4_3:
+		mode = v720x576p_50Hz;
+		video->aspect = HDMI_PIC_RATIO_4_3;
+		break;
+
+	case TVOUT_720P_60:
+		mode = v1280x720p_60Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_720P_59:
+		mode = v1280x720p_59Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_720P_50:
+		mode = v1280x720p_50Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080P_30:
+		mode = v1920x1080p_30Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080P_60:
+		mode = v1920x1080p_60Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080P_59:
+		mode = v1920x1080p_59Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080P_50:
+		mode = v1920x1080p_50Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080I_60:
+		mode = v1920x1080i_60Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080I_59:
+		mode = v1920x1080i_59Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+
+	case TVOUT_1080I_50:
+		mode = v1920x1080i_50Hz;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_720P_60_SBS_HALF:
+		mode = v1280x720p_60Hz_SBS_HALF;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+	case TVOUT_720P_59_SBS_HALF:
+		mode = v1280x720p_59Hz_SBS_HALF;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+	case TVOUT_720P_50_TB:
+		mode = v1280x720p_50Hz_TB;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+	case TVOUT_1080P_24_TB:
+		mode = v1920x1080p_24Hz_TB;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+	case TVOUT_1080P_23_TB:
+		mode = v1920x1080p_23Hz_TB;
+		video->colorimetry = HDMI_CLRIMETRY_709;
+		break;
+#endif
+
+	default:
+		mode = v720x480p_60Hz;
+		tvout_err("Not supported mode : %d\n", mode);
+	}
+
+	return mode;
+}
+
+static void s5p_hdmi_set_acr(struct s5p_hdmi_audio *audio, u8 *acr)
+{
+	u32 n = (audio->freq == 32000) ? 4096 :
+		(audio->freq == 44100) ? 6272 :
+		(audio->freq == 88200) ? 12544 :
+		(audio->freq == 176400) ? 25088 :
+		(audio->freq == 48000) ? 6144 :
+		(audio->freq == 96000) ? 12288 :
+		(audio->freq == 192000) ? 24576 : 0;
+
+	u32 cts = (audio->freq == 32000) ? 27000 :
+		(audio->freq == 44100) ? 30000 :
+		(audio->freq == 88200) ? 30000 :
+		(audio->freq == 176400) ? 30000 :
+		(audio->freq == 48000) ? 27000 :
+		(audio->freq == 96000) ? 27000 :
+		(audio->freq == 192000) ? 27000 : 0;
+
+	acr[1] = cts >> 16;
+	acr[2] = cts >> 8 & 0xff;
+	acr[3] = cts & 0xff;
+
+	acr[4] = n >> 16;
+	acr[5] = n >> 8 & 0xff;
+	acr[6] = n & 0xff;
+
+	tvout_dbg("n value = %d\n", n);
+	tvout_dbg("cts   = %d\n", cts);
+}
+
+static void s5p_hdmi_set_asp(u8 *header)
+{
+	header[1] = 0;
+	header[2] = 0;
+}
+
+static void s5p_hdmi_set_acp(struct s5p_hdmi_audio *audio, u8 *header)
+{
+	header[1] = audio->type;
+}
+
+static void s5p_hdmi_set_isrc(u8 *header)
+{
+}
+
+static void s5p_hdmi_set_gmp(u8 *gmp)
+{
+}
+
+static void s5p_hdmi_set_avi(
+	enum s5p_hdmi_v_mode mode, enum s5p_tvout_o_mode out,
+	struct s5p_hdmi_video *video, u8 *avi)
+{
+	struct s5p_hdmi_o_params		param = s5p_hdmi_output[out];
+	struct s5p_hdmi_v_frame			frame;
+
+	frame = s5p_hdmi_v_fmt[mode].frame;
+	avi[0] = param.reg.pxl_fmt;
+	avi[2] &= (u8)((~0x3) << 2);
+	avi[4] &= (u8)((~0x3) << 6);
+
+	/* RGB or YCbCr */
+	if (s5p_tvif_ctrl_private.curr_if == TVOUT_HDMI_RGB) {
+		avi[0] |= (0x1 << 4);
+		avi[4] |= frame.repetition;
+		if (s5p_tvif_ctrl_private.curr_std == TVOUT_480P_60_4_3) {
+			avi[2] |= HDMI_Q_DEFAULT << 2;
+			avi[4] |= HDMI_AVI_YQ_FULL_RANGE << 6;
+		} else {
+			avi[2] |= HDMI_Q_DEFAULT << 2;
+			avi[4] |= HDMI_AVI_YQ_LIMITED_RANGE << 6;
+		}
+	} else {
+		avi[0] |= (0x5 << 4);
+		avi[4] |= frame.repetition;
+		if (video->q_range == HDMI_Q_FULL_RANGE) {
+			tvout_dbg("Q_Range : %d\n", video->q_range);
+			avi[2] |= HDMI_Q_DEFAULT << 2;
+			avi[4] |= HDMI_AVI_YQ_FULL_RANGE << 6;
+		} else {
+			tvout_dbg("Q_Range : %d\n", video->q_range);
+			avi[2] |= HDMI_Q_DEFAULT << 2;
+			avi[4] |= HDMI_AVI_YQ_LIMITED_RANGE << 6;
+		}
+	}
+
+	avi[1] = video->colorimetry;
+	avi[1] |= video->aspect << 4;
+	avi[1] |= AVI_SAME_WITH_PICTURE_AR;
+#ifdef CONFIG_HDMI_14A_3D
+	avi[3] = (video->aspect == HDMI_PIC_RATIO_16_9) ?
+				frame.vAVI_VIC_16_9 : frame.vAVI_VIC;
+#else
+	avi[3] = (video->aspect == HDMI_PIC_RATIO_16_9) ?
+				frame.vic_16_9 : frame.vic;
+#endif
+	if (s5p_tvif_ctrl_private.curr_std == TVOUT_480P_60_4_3)
+		avi[3] = 0x1;
+
+	tvout_dbg(KERN_INFO "AVI BYTE 1 : 0x%x\n", avi[0]);
+	tvout_dbg(KERN_INFO "AVI BYTE 2 : 0x%x\n", avi[1]);
+	tvout_dbg(KERN_INFO "AVI BYTE 3 : 0x%x\n", avi[2]);
+	tvout_dbg(KERN_INFO "AVI BYTE 4 : %d\n", avi[3]);
+	tvout_dbg(KERN_INFO "AVI BYTE 5 : 0x%x\n", avi[4]);
+}
+
+static void s5p_hdmi_set_aui(struct s5p_hdmi_audio *audio, u8 *aui)
+{
+	aui[0] = audio->channel - 1;
+	if (audio->channel == 2) {
+		aui[1] = 0x0;
+		aui[2] = 0;
+		aui[3] = 0x0;
+	} else {
+		aui[1] = 0x0;
+		aui[2] = 0;
+		aui[3] = 0x0b;
+	}
+}
+
+static void s5p_hdmi_set_spd(u8 *spd)
+{
+	struct s5p_hdmi_ctrl_private_data *ctrl = &s5p_hdmi_ctrl_private;
+
+	memcpy(spd, ctrl->vendor, 8);
+	memcpy(&spd[8], ctrl->product, 16);
+
+	spd[24] = 0x1; /* Digital STB */
+}
+
+static void s5p_hdmi_set_mpg(u8 *mpg)
+{
+}
+
+static int s5p_hdmi_ctrl_audio_enable(bool en)
+{
+	if (!s5p_hdmi_output[s5p_hdmi_ctrl_private.out].reg.dvi)
+		s5p_hdmi_reg_audio_enable(en);
+
+	return 0;
+}
+
+#if 0 /* This function will be used in the future */
+static void s5p_hdmi_ctrl_bluescreen_clr(u8 cb_b, u8 y_g, u8 cr_r)
+{
+	struct s5p_hdmi_ctrl_private_data *ctrl = &s5p_hdmi_ctrl_private;
+
+	ctrl->blue_screen.cb_b	= cb_b;
+	ctrl->blue_screen.y_g	= y_g;
+	ctrl->blue_screen.cr_r	= cr_r;
+
+	s5p_hdmi_reg_bluescreen_clr(cb_b, y_g, cr_r);
+}
+#endif
+
+static void s5p_hdmi_ctrl_set_bluescreen(bool en)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+
+	ctrl->blue_screen.enable = en ? true : false;
+
+	s5p_hdmi_reg_bluescreen(en);
+}
+
+#ifndef CONFIG_HDMI_EARJACK_MUTE
+static void s5p_hdmi_ctrl_set_audio(bool en)
+#else
+void s5p_hdmi_ctrl_set_audio(bool en)
+#endif
+{
+	struct s5p_hdmi_ctrl_private_data       *ctrl = &s5p_hdmi_ctrl_private;
+
+	s5p_hdmi_ctrl_private.audio.on = en ? 1 : 0;
+
+	if (ctrl->running)
+		s5p_hdmi_ctrl_audio_enable(en);
+}
+
+static void s5p_hdmi_ctrl_set_av_mute(bool en)
+{
+	struct s5p_hdmi_ctrl_private_data       *ctrl = &s5p_hdmi_ctrl_private;
+
+	ctrl->av_mute = en ? 1 : 0;
+
+	if (ctrl->running) {
+		if (en) {
+			s5p_hdmi_ctrl_audio_enable(false);
+			s5p_hdmi_ctrl_set_bluescreen(true);
+		} else {
+			s5p_hdmi_ctrl_audio_enable(true);
+			s5p_hdmi_ctrl_set_bluescreen(false);
+		}
+	}
+
+}
+
+u8 s5p_hdmi_ctrl_get_mute(void)
+{
+	return s5p_hdmi_ctrl_private.av_mute ? 1 : 0;
+}
+
+#if 0 /* This function will be used in the future */
+static void s5p_hdmi_ctrl_mute(bool en)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+
+	if (en) {
+		s5p_hdmi_reg_bluescreen(true);
+		s5p_hdmi_ctrl_audio_enable(false);
+	} else {
+		s5p_hdmi_reg_bluescreen(false);
+		if (ctrl->audio.on)
+			s5p_hdmi_ctrl_audio_enable(true);
+	}
+}
+#endif
+
+void s5p_hdmi_ctrl_set_hdcp(bool en)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+
+	ctrl->hdcp_en = en ? 1 : 0;
+}
+
+static void s5p_hdmi_ctrl_init_private(void)
+{
+}
+
+static bool s5p_hdmi_ctrl_set_reg(
+		enum s5p_hdmi_v_mode mode, enum s5p_tvout_o_mode out)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct s5p_hdmi_packet			*packet = &ctrl->packet;
+
+	struct s5p_hdmi_bluescreen		*bl = &ctrl->blue_screen;
+	struct s5p_hdmi_color_range		*cr = &ctrl->video.color_r;
+	struct s5p_hdmi_tg			*tg = &ctrl->tg;
+#ifdef CONFIG_HDMI_14A_3D
+	u8 type3D;
+#endif
+
+#ifdef CONFIG_HDMI_14A_3D
+	s5p_hdmi_reg_bluescreen_clr(bl->b, bl->g, bl->r);
+#else
+	s5p_hdmi_reg_bluescreen_clr(bl->cb_b, bl->y_g, bl->cr_r);
+#endif
+	s5p_hdmi_reg_bluescreen(bl->enable);
+
+	s5p_hdmi_reg_clr_range(cr->y_min, cr->y_max, cr->c_min, cr->c_max);
+
+	s5p_hdmi_reg_acr(packet->acr);
+	s5p_hdmi_reg_asp(packet->h_asp, &ctrl->audio);
+#ifdef CONFIG_HDMI_14A_3D
+	s5p_hdmi_reg_gcp(s5p_hdmi_v_fmt[mode].frame.interlaced, packet->gcp);
+#else
+	s5p_hdmi_reg_gcp(s5p_hdmi_v_fmt[mode].frame.i_p, packet->gcp);
+#endif
+
+	s5p_hdmi_reg_acp(packet->h_acp, packet->acp);
+	s5p_hdmi_reg_isrc(packet->isrc1, packet->isrc2);
+	s5p_hdmi_reg_gmp(packet->gmp);
+
+
+#ifdef CONFIG_HDMI_14A_3D
+	if ((mode == v1280x720p_60Hz_SBS_HALF) ||
+		(mode == v1280x720p_59Hz_SBS_HALF))
+		type3D = HDMI_3D_SSH_FORMAT;
+	else if ((mode == v1280x720p_50Hz_TB) ||
+		(mode == v1920x1080p_24Hz_TB) || (mode == v1920x1080p_23Hz_TB))
+		type3D = HDMI_3D_TB_FORMAT;
+	else
+		type3D = HDMI_2D_FORMAT;
+
+	s5p_hdmi_reg_infoframe(&packet->vsi_info, packet->vsi, type3D);
+	s5p_hdmi_reg_infoframe(&packet->vsi_info, packet->vsi, type3D);
+	s5p_hdmi_reg_infoframe(&packet->avi_info, packet->avi, type3D);
+	s5p_hdmi_reg_infoframe(&packet->aui_info, packet->aui, type3D);
+	s5p_hdmi_reg_infoframe(&packet->spd_info, packet->spd, type3D);
+	s5p_hdmi_reg_infoframe(&packet->mpg_info, packet->mpg, type3D);
+#else
+	s5p_hdmi_reg_infoframe(&packet->avi_info, packet->avi);
+	s5p_hdmi_reg_infoframe(&packet->aui_info, packet->aui);
+	s5p_hdmi_reg_infoframe(&packet->spd_info, packet->spd);
+	s5p_hdmi_reg_infoframe(&packet->mpg_info, packet->mpg);
+#endif
+
+	s5p_hdmi_reg_packet_trans(&s5p_hdmi_output[out].trans);
+	s5p_hdmi_reg_output(&s5p_hdmi_output[out].reg);
+
+#ifdef CONFIG_HDMI_14A_3D
+	s5p_hdmi_reg_tg(&s5p_hdmi_v_fmt[mode]);
+#else
+	s5p_hdmi_reg_tg(&s5p_hdmi_v_fmt[mode].frame);
+#endif
+	s5p_hdmi_reg_v_timing(&s5p_hdmi_v_fmt[mode]);
+	s5p_hdmi_reg_tg_cmd(tg->correction_en, tg->bt656_en, true);
+
+	switch (ctrl->audio.type) {
+	case HDMI_GENERIC_AUDIO:
+		break;
+
+	case HDMI_60958_AUDIO:
+		s5p_hdmi_audio_init(PCM, 44100, 16, 0, &ctrl->audio);
+		break;
+
+	case HDMI_DVD_AUDIO:
+	case HDMI_SUPER_AUDIO:
+		break;
+
+	default:
+		tvout_err("Invalid audio type %d\n", ctrl->audio.type);
+		return -1;
+	}
+
+	s5p_hdmi_reg_audio_enable(true);
+
+	return 0;
+}
+
+static void s5p_hdmi_ctrl_internal_stop(void)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct s5p_hdmi_tg			*tg = &ctrl->tg;
+
+	tvout_dbg("\n");
+#ifdef CONFIG_HDMI_HPD
+	s5p_hpd_set_eint();
+#endif
+	if (ctrl->hdcp_en)
+		s5p_hdcp_stop();
+
+	s5p_hdmi_reg_enable(false);
+
+	s5p_hdmi_reg_tg_cmd(tg->correction_en, tg->bt656_en, false);
+}
+
+int s5p_hdmi_ctrl_phy_power(bool on)
+{
+	tvout_dbg("on(%d)\n", on);
+	if (on) {
+		/* on */
+		clk_enable(s5ptv_status.i2c_phy_clk);
+		// Restore i2c_hdmi_phy_base address
+		s5p_hdmi_phy_init(s5p_hdmi_ctrl_private.reg_mem[HDMI_PHY].base);
+
+		s5p_hdmi_phy_power(true);
+
+	} else {
+		/*
+		 * for preventing hdmi hang up when restart
+		 * switch to internal clk - SCLK_DAC, SCLK_PIXEL
+		 */
+		s5p_mixer_ctrl_mux_clk(s5ptv_status.sclk_dac);
+		if (clk_set_parent(s5ptv_status.sclk_hdmi,
+				s5ptv_status.sclk_pixel)) {
+			tvout_err("unable to set parent %s of clock %s.\n",
+				   s5ptv_status.sclk_pixel->name,
+				   s5ptv_status.sclk_hdmi->name);
+			return -1;
+		}
+
+		s5p_hdmi_phy_power(false);
+
+		clk_disable(s5ptv_status.i2c_phy_clk);
+		// Set i2c_hdmi_phy_base to NULL
+		s5p_hdmi_phy_init(NULL);
+	}
+
+	return 0;
+}
+
+void s5p_hdmi_ctrl_clock(bool on)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct s5p_tvout_clk_info		*clk = ctrl->clk;
+
+	tvout_dbg("on(%d)\n", on);
+	if (on) {
+		clk_enable(clk[HDMI_MUX].ptr);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_get();
+#endif
+		clk_enable(clk[HDMI_PCLK].ptr);
+
+		// Restore hdmi_base address
+		s5p_hdmi_init(s5p_hdmi_ctrl_private.reg_mem[HDMI].base);
+	} else {
+		clk_disable(clk[HDMI_PCLK].ptr);
+
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_put();
+#endif
+
+		clk_disable(clk[HDMI_MUX].ptr);
+
+		// Set hdmi_base to NULL
+		s5p_hdmi_init(NULL);
+	}
+}
+
+bool s5p_hdmi_ctrl_status(void)
+{
+	return s5p_hdmi_ctrl_private.running;
+}
+
+void s5p_hdmi_ctrl_stop(void)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+
+	tvout_dbg("running(%d)\n", ctrl->running);
+	if (ctrl->running) {
+		ctrl->running = false;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+		} else
+#endif
+		{
+			s5p_hdmi_ctrl_internal_stop();
+			s5p_hdmi_ctrl_clock(0);
+		}
+	}
+}
+
+int s5p_hdmi_ctrl_start(
+	enum s5p_tvout_disp_mode disp, enum s5p_tvout_o_mode out)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct s5p_hdmi_packet			*packet = &ctrl->packet;
+	struct s5p_hdmi_v_frame			frame;
+
+	enum s5p_hdmi_v_mode			mode;
+
+	ctrl->out = out;
+	mode = s5p_hdmi_check_v_fmt(disp);
+	ctrl->mode = mode;
+
+	tvout_dbg("\n");
+	if (ctrl->running)
+		s5p_hdmi_ctrl_internal_stop();
+	else {
+		s5p_hdmi_ctrl_clock(1);
+		ctrl->running = true;
+	}
+	on_start_process = false;
+	tvout_dbg("on_start_process(%d)\n", on_start_process);
+
+	frame = s5p_hdmi_v_fmt[mode].frame;
+
+	if (s5p_hdmi_phy_config(frame.pixel_clock, ctrl->video.depth) < 0) {
+		tvout_err("hdmi phy configuration failed.\n");
+		goto err_on_s5p_hdmi_start;
+	}
+
+
+	s5p_hdmi_set_acr(&ctrl->audio, packet->acr);
+	s5p_hdmi_set_asp(packet->h_asp);
+	s5p_hdmi_set_gcp(ctrl->video.depth, packet->gcp);
+
+	s5p_hdmi_set_acp(&ctrl->audio, packet->h_acp);
+	s5p_hdmi_set_isrc(packet->h_isrc);
+	s5p_hdmi_set_gmp(packet->gmp);
+
+	s5p_hdmi_set_avi(mode, out, &ctrl->video, packet->avi);
+	s5p_hdmi_set_spd(packet->spd);
+	s5p_hdmi_set_aui(&ctrl->audio, packet->aui);
+	s5p_hdmi_set_mpg(packet->mpg);
+
+	s5p_hdmi_ctrl_set_reg(mode, out);
+
+	if (ctrl->hdcp_en)
+		s5p_hdcp_start();
+
+	s5p_hdmi_reg_enable(true);
+
+#ifdef CONFIG_HDMI_HPD
+	s5p_hpd_set_hdmiint();
+#endif
+
+	return 0;
+
+err_on_s5p_hdmi_start:
+	return -1;
+}
+
+int s5p_hdmi_ctrl_constructor(struct platform_device *pdev)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct reg_mem_info		*reg_mem = ctrl->reg_mem;
+	struct s5p_tvout_clk_info		*clk = ctrl->clk;
+	struct irq_info			*irq = &ctrl->irq;
+	int ret, i, k, j;
+
+	for (i = 0; i < HDMI_NO_OF_MEM_RES; i++) {
+		ret = s5p_tvout_map_resource_mem(pdev, reg_mem[i].name,
+			&(reg_mem[i].base), &(reg_mem[i].res));
+
+		if (ret)
+			goto err_on_res;
+	}
+
+	for (k = HDMI_PCLK; k < HDMI_NO_OF_CLK; k++) {
+		clk[k].ptr = clk_get(&pdev->dev, clk[k].name);
+
+		if (IS_ERR(clk[k].ptr)) {
+			printk(KERN_ERR	"%s clk is not found\n", clk[k].name);
+			ret = -ENOENT;
+			goto err_on_clk;
+		}
+	}
+
+	irq->no = platform_get_irq_byname(pdev, irq->name);
+
+	if (irq->no < 0) {
+		printk(KERN_ERR "can not get platform irq by name : %s\n",
+					irq->name);
+		ret = irq->no;
+		goto err_on_irq;
+	}
+
+	s5p_hdmi_init(reg_mem[HDMI].base);
+	s5p_hdmi_phy_init(reg_mem[HDMI_PHY].base);
+
+	ret = request_irq(irq->no, irq->handler, IRQF_DISABLED,
+			irq->name, NULL);
+	if (ret) {
+		printk(KERN_ERR "can not request irq : %s\n", irq->name);
+		goto err_on_irq;
+	}
+
+	s5p_hdmi_ctrl_init_private();
+
+	/* set initial state of HDMI PHY power to off */
+	s5p_hdmi_ctrl_phy_power(1);
+	s5p_hdmi_ctrl_phy_power(0);
+
+	ret = s5p_hdcp_init();
+
+	if (ret) {
+		printk(KERN_ERR "HDCP init failed..\n");
+		goto err_hdcp_init;
+	}
+
+	return 0;
+
+err_hdcp_init:
+err_on_irq:
+err_on_clk:
+	for (j = 0; j < k; j++)
+		clk_put(clk[j].ptr);
+
+err_on_res:
+	for (j = 0; j < i; j++)
+		s5p_tvout_unmap_resource_mem(reg_mem[j].base, reg_mem[j].res);
+
+	return ret;
+}
+
+void s5p_hdmi_ctrl_destructor(void)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	struct reg_mem_info		*reg_mem = ctrl->reg_mem;
+	struct s5p_tvout_clk_info		*clk = ctrl->clk;
+	struct irq_info			*irq = &ctrl->irq;
+
+	int i;
+
+	if (irq->no >= 0)
+		free_irq(irq->no, NULL);
+
+	for (i = 0; i < HDMI_NO_OF_MEM_RES; i++)
+		s5p_tvout_unmap_resource_mem(reg_mem[i].base, reg_mem[i].res);
+
+	for (i = HDMI_PCLK; i < HDMI_NO_OF_CLK; i++)
+		if (clk[i].ptr) {
+			if (ctrl->running)
+				clk_disable(clk[i].ptr);
+			clk_put(clk[i].ptr);
+		}
+
+	s5p_hdmi_phy_init(NULL);
+	s5p_hdmi_init(NULL);
+}
+
+void s5p_hdmi_ctrl_suspend(void)
+{
+}
+
+void s5p_hdmi_ctrl_resume(void)
+{
+}
+
+#ifdef CONFIG_ANALOG_TVENC
+#ifndef CONFIG_VPLL_USE_FOR_TVENC
+static void s5p_tvenc_src_to_hdmiphy_on(void)
+{
+	s5p_hdmi_ctrl_clock(1);
+	s5p_hdmi_ctrl_phy_power(1);
+	if (s5p_hdmi_phy_config(ePHY_FREQ_54, HDMI_CD_24) < 0)
+		tvout_err("hdmi phy configuration failed.\n");
+	if (clk_set_parent(s5ptv_status.sclk_dac, s5ptv_status.sclk_hdmiphy))
+		tvout_err("unable to set parent %s of clock %s.\n",
+			   s5ptv_status.sclk_hdmiphy->name,
+			   s5ptv_status.sclk_dac->name);
+}
+
+static void s5p_tvenc_src_to_hdmiphy_off(void)
+{
+	s5p_hdmi_ctrl_phy_power(0);
+	s5p_hdmi_ctrl_clock(0);
+}
+#endif
+#endif
+
+/****************************************
+ * Functions for tvif ctrl class
+ ***************************************/
+static void s5p_tvif_ctrl_init_private(struct platform_device *pdev)
+{
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	/* add bus device ptr for using bus frequency with opp */
+	s5p_tvif_ctrl_private.bus_dev = dev_get("exynos-busfreq");
+#endif
+	s5p_tvif_ctrl_private.dev = &pdev->dev;
+}
+
+/*
+ * TV cut off sequence
+ * VP stop -> Mixer stop -> HDMI stop -> HDMI TG stop
+ * Above sequence should be satisfied.
+ */
+static int s5p_tvif_ctrl_internal_stop(void)
+{
+	tvout_dbg("status(%d)\n", s5p_tvif_ctrl_private.curr_if);
+	s5p_mixer_ctrl_stop();
+
+	switch (s5p_tvif_ctrl_private.curr_if) {
+#ifdef CONFIG_ANALOG_TVENC
+	case TVOUT_COMPOSITE:
+		s5p_sdo_ctrl_stop();
+		break;
+#endif
+	case TVOUT_DVI:
+	case TVOUT_HDMI:
+	case TVOUT_HDMI_RGB:
+		s5p_hdmi_ctrl_stop();
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+		} else
+#endif
+		{
+			s5p_hdmi_ctrl_phy_power(0);
+		}
+		break;
+
+	default:
+		tvout_err("invalid out parameter(%d)\n",
+			s5p_tvif_ctrl_private.curr_if);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void s5p_tvif_ctrl_internal_start(
+		enum s5p_tvout_disp_mode std,
+		enum s5p_tvout_o_mode inf)
+{
+	tvout_dbg("\n");
+	s5p_mixer_ctrl_set_int_enable(false);
+
+	/* Clear All Interrupt Pending */
+	s5p_mixer_ctrl_clear_pend_all();
+
+	switch (inf) {
+#ifdef CONFIG_ANALOG_TVENC
+	case TVOUT_COMPOSITE:
+		if (s5p_mixer_ctrl_start(std, inf) < 0)
+			goto ret_on_err;
+
+		if (0 != s5p_sdo_ctrl_start(std))
+			goto ret_on_err;
+
+		break;
+#endif
+	case TVOUT_HDMI:
+	case TVOUT_HDMI_RGB:
+	case TVOUT_DVI:
+		s5p_hdmi_ctrl_phy_power(1);
+
+		if (s5p_mixer_ctrl_start(std, inf) < 0)
+			goto ret_on_err;
+
+		if (0 != s5p_hdmi_ctrl_start(std, inf))
+			goto ret_on_err;
+		break;
+	default:
+		break;
+	}
+
+ret_on_err:
+	s5p_mixer_ctrl_set_int_enable(true);
+
+	/* Clear All Interrupt Pending */
+	s5p_mixer_ctrl_clear_pend_all();
+}
+
+int s5p_tvif_ctrl_set_audio(bool en)
+{
+	switch (s5p_tvif_ctrl_private.curr_if) {
+	case TVOUT_HDMI:
+	case TVOUT_HDMI_RGB:
+	case TVOUT_DVI:
+		s5p_hdmi_ctrl_set_audio(en);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void s5p_tvif_audio_channel(int channel)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	ctrl->audio.channel = channel;
+}
+
+void s5p_tvif_q_color_range(int range)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	if (range)
+		ctrl->video.q_range = HDMI_Q_FULL_RANGE;
+	else
+		ctrl->video.q_range = HDMI_Q_LIMITED_RANGE;
+	tvout_dbg("%s: Set Q range : %d\n", __func__, ctrl->video.q_range);
+}
+
+int s5p_tvif_get_q_range(void)
+{
+	struct s5p_hdmi_ctrl_private_data	*ctrl = &s5p_hdmi_ctrl_private;
+	tvout_dbg("%s: Get Q range : %d\n", __func__, ctrl->video.q_range);
+	if (ctrl->video.q_range == HDMI_Q_FULL_RANGE)
+		return 1;
+	else
+		return 0;
+}
+
+int s5p_tvif_ctrl_set_av_mute(bool en)
+{
+	switch (s5p_tvif_ctrl_private.curr_if) {
+	case TVOUT_HDMI:
+	case TVOUT_HDMI_RGB:
+	case TVOUT_DVI:
+		s5p_hdmi_ctrl_set_av_mute(en);
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int s5p_tvif_ctrl_get_std_if(
+		enum s5p_tvout_disp_mode *std, enum s5p_tvout_o_mode *inf)
+{
+	*std = s5p_tvif_ctrl_private.curr_std;
+	*inf = s5p_tvif_ctrl_private.curr_if;
+
+	return 0;
+}
+
+bool s5p_tvif_ctrl_get_run_state()
+{
+	return s5p_tvif_ctrl_private.running;
+}
+
+int s5p_tvif_ctrl_start(
+		enum s5p_tvout_disp_mode std, enum s5p_tvout_o_mode inf)
+{
+	tvout_dbg("\n");
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	if ((std == TVOUT_1080P_60) || (std == TVOUT_1080P_59)
+			|| (std == TVOUT_1080P_50)) {
+		dev_lock(s5p_tvif_ctrl_private.bus_dev,
+				s5p_tvif_ctrl_private.dev, BUSFREQ_400MHZ);
+	}
+#if defined(CONFIG_MACH_MIDAS)
+	else {
+		dev_lock(s5p_tvif_ctrl_private.bus_dev,
+			 s5p_tvif_ctrl_private.dev, BUSFREQ_133MHZ);
+	}
+#endif
+#endif
+	if (s5p_tvif_ctrl_private.running &&
+			(std == s5p_tvif_ctrl_private.curr_std) &&
+			(inf == s5p_tvif_ctrl_private.curr_if))	{
+		on_start_process = false;
+		tvout_dbg("%s() on_start_process(%d)\n",
+			__func__, on_start_process);
+		goto cannot_change;
+	}
+
+	s5p_tvif_ctrl_private.curr_std = std;
+	s5p_tvif_ctrl_private.curr_if = inf;
+
+	switch (inf) {
+	case TVOUT_COMPOSITE:
+	case TVOUT_HDMI:
+	case TVOUT_HDMI_RGB:
+	case TVOUT_DVI:
+		break;
+	default:
+		tvout_err("invalid out parameter(%d)\n", inf);
+		goto cannot_change;
+	}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+	} else
+#endif
+	{
+		/* how to control the clock path on stop time ??? */
+		if (s5p_tvif_ctrl_private.running)
+			s5p_tvif_ctrl_internal_stop();
+
+		s5p_tvif_ctrl_internal_start(std, inf);
+	}
+
+	s5p_tvif_ctrl_private.running = true;
+
+	return 0;
+
+cannot_change:
+	return -1;
+}
+
+void s5p_tvif_ctrl_stop(void)
+{
+	if (s5p_tvif_ctrl_private.running) {
+		s5p_tvif_ctrl_internal_stop();
+
+		s5p_tvif_ctrl_private.running = false;
+	}
+#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	dev_unlock(s5p_tvif_ctrl_private.bus_dev, s5p_tvif_ctrl_private.dev);
+#endif
+}
+
+int s5p_tvif_ctrl_constructor(struct platform_device *pdev)
+{
+#ifdef CONFIG_ANALOG_TVENC
+	if (s5p_sdo_ctrl_constructor(pdev))
+		goto err;
+#endif
+
+	if (s5p_hdmi_ctrl_constructor(pdev))
+		goto err;
+
+	s5p_tvif_ctrl_init_private(pdev);
+
+	return 0;
+
+err:
+	return -1;
+}
+
+void s5p_tvif_ctrl_destructor(void)
+{
+#ifdef CONFIG_ANALOG_TVENC
+	s5p_sdo_ctrl_destructor();
+#endif
+	s5p_hdmi_ctrl_destructor();
+}
+
+void s5p_tvif_ctrl_suspend(void)
+{
+	tvout_dbg("\n");
+	if (s5p_tvif_ctrl_private.running) {
+		s5p_tvif_ctrl_internal_stop();
+#ifdef CONFIG_VCM
+		s5p_tvout_vcm_deactivate();
+#endif
+	}
+
+}
+
+void s5p_tvif_ctrl_resume(void)
+{
+	if (s5p_tvif_ctrl_private.running) {
+#ifdef CONFIG_VCM
+		s5p_tvout_vcm_activate();
+#endif
+		s5p_tvif_ctrl_internal_start(
+			s5p_tvif_ctrl_private.curr_std,
+			s5p_tvif_ctrl_private.curr_if);
+	}
+}
+
+#ifdef CONFIG_PM
+void s5p_hdmi_ctrl_phy_power_resume(void)
+{
+	tvout_dbg("running(%d)\n", s5p_tvif_ctrl_private.running);
+	if (s5p_tvif_ctrl_private.running)
+		return;
+
+	s5p_hdmi_ctrl_phy_power(1);
+	s5p_hdmi_ctrl_phy_power(0);
+
+	return;
+}
+#endif
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout.c b/drivers/media/video/samsung/tvout/s5p_tvout.c
new file mode 100644
index 0000000..7407670
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout.c
@@ -0,0 +1,666 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Entry file for Samsung TVOut driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+
+#if defined(CONFIG_S5P_SYSMMU_TV)
+#include <plat/sysmmu.h>
+#endif
+
+#if defined(CONFIG_S5P_MEM_CMA)
+#include <linux/cma.h>
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+#include <plat/media.h>
+#include <mach/media.h>
+#endif
+
+#include "s5p_tvout_common_lib.h"
+#include "s5p_tvout_ctrl.h"
+#include "s5p_tvout_fb.h"
+#include "s5p_tvout_v4l2.h"
+
+#define TV_CLK_GET_WITH_ERR_CHECK(clk, pdev, clk_name)			\
+		do {							\
+			clk = clk_get(&pdev->dev, clk_name);		\
+			if (IS_ERR(clk)) {				\
+				printk(KERN_ERR				\
+				"failed to find clock %s\n", clk_name);	\
+				return -ENOENT;				\
+			}						\
+		} while (0);
+
+struct s5p_tvout_status s5ptv_status;
+bool on_stop_process;
+bool on_start_process;
+struct s5p_tvout_vp_bufferinfo s5ptv_vp_buff;
+#ifdef CONFIG_PM
+static struct workqueue_struct *tvout_resume_wq;
+struct work_struct tvout_resume_work;
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+static struct early_suspend s5ptv_early_suspend;
+static DEFINE_MUTEX(s5p_tvout_mutex);
+unsigned int suspend_status;
+static void s5p_tvout_early_suspend(struct early_suspend *h);
+static void s5p_tvout_late_resume(struct early_suspend *h);
+#endif
+bool flag_after_resume;
+
+#ifdef CONFIG_TVOUT_DEBUG
+int tvout_dbg_flag;
+#endif
+
+
+#ifdef CONFIG_HDMI_EARJACK_MUTE
+bool hdmi_audio_ext;
+
+/* To provide an interface fo Audio path control */
+static ssize_t hdmi_set_audio_read(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int count = 0;
+
+	printk(KERN_ERR "[HDMI]: AUDIO PATH\n");
+	return count;
+}
+
+static ssize_t hdmi_set_audio_store(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t size)
+{
+	char *after;
+	bool value = !strncmp(buf, "1", 1) ? true : false;
+
+	printk(KERN_ERR "[HDMI] Change AUDIO PATH: %d\n", (int)value);
+
+	if (value == hdmi_audio_ext) {
+		if (value) {
+			hdmi_audio_ext = 0;
+			s5p_hdmi_ctrl_set_audio(1);
+		} else {
+			hdmi_audio_ext = 1;
+			s5p_hdmi_ctrl_set_audio(0);
+		}
+	}
+
+	return size;
+}
+
+static DEVICE_ATTR(hdmi_audio_set_ext, 0660,
+	hdmi_set_audio_read, hdmi_set_audio_store);
+#endif
+
+static int __devinit s5p_tvout_clk_get(struct platform_device *pdev,
+				       struct s5p_tvout_status *ctrl)
+{
+	struct clk *ext_xtal_clk, *mout_vpll_src, *fout_vpll, *mout_vpll;
+
+	TV_CLK_GET_WITH_ERR_CHECK(ctrl->i2c_phy_clk, pdev, "i2c-hdmiphy");
+
+	TV_CLK_GET_WITH_ERR_CHECK(ctrl->sclk_dac, pdev, "sclk_dac");
+	TV_CLK_GET_WITH_ERR_CHECK(ctrl->sclk_hdmi, pdev, "sclk_hdmi");
+
+	TV_CLK_GET_WITH_ERR_CHECK(ctrl->sclk_pixel, pdev, "sclk_pixel");
+	TV_CLK_GET_WITH_ERR_CHECK(ctrl->sclk_hdmiphy, pdev, "sclk_hdmiphy");
+
+	TV_CLK_GET_WITH_ERR_CHECK(ext_xtal_clk, pdev, "ext_xtal");
+	TV_CLK_GET_WITH_ERR_CHECK(mout_vpll_src, pdev, "vpll_src");
+	TV_CLK_GET_WITH_ERR_CHECK(fout_vpll, pdev, "fout_vpll");
+	TV_CLK_GET_WITH_ERR_CHECK(mout_vpll, pdev, "sclk_vpll");
+
+#ifdef CONFIG_VPLL_USE_FOR_TVENC
+	if (clk_set_rate(fout_vpll, 54000000)) {
+		tvout_err("%s rate change failed: %lu\n", fout_vpll->name,
+			  54000000);
+		return -1;
+	}
+
+	if (clk_set_parent(mout_vpll_src, ext_xtal_clk)) {
+		tvout_err("unable to set parent %s of clock %s.\n",
+			  ext_xtal_clk->name, mout_vpll_src->name);
+		return -1;
+	}
+
+	if (clk_set_parent(mout_vpll, fout_vpll)) {
+		tvout_err("unable to set parent %s of clock %s.\n",
+			  fout_vpll->name, mout_vpll->name);
+		return -1;
+	}
+
+	/* sclk_dac's parent is fixed as mout_vpll */
+	if (clk_set_parent(ctrl->sclk_dac, mout_vpll)) {
+		tvout_err("unable to set parent %s of clock %s.\n",
+			  mout_vpll->name, ctrl->sclk_dac->name);
+		return -1;
+	}
+
+	/* It'll be moved in the future */
+	if (clk_enable(mout_vpll_src) < 0)
+		return -1;
+
+	if (clk_enable(fout_vpll) < 0)
+		return -1;
+
+	if (clk_enable(mout_vpll) < 0)
+		return -1;
+
+	clk_put(ext_xtal_clk);
+	clk_put(mout_vpll_src);
+	clk_put(fout_vpll);
+	clk_put(mout_vpll);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_TVOUT_DEBUG
+void show_tvout_dbg_flag(void)
+{
+	pr_info("hw_if/hdmi.c %s\n",
+		((tvout_dbg_flag >> DBG_FLAG_HDMI) & 0x1 ? "On" : "Off"));
+	pr_info("s5p_tvout_hpd.c %s\n",
+		((tvout_dbg_flag >> DBG_FLAG_HPD) & 0x1 ? "On" : "Off"));
+	pr_info("s5p_tvout_common_lib.h %s\n",
+		((tvout_dbg_flag >> DBG_FLAG_TVOUT) & 0x1 ? "On" : "Off"));
+	pr_info("hw_if/hdcp.c %s\n",
+		((tvout_dbg_flag >> DBG_FLAG_HDCP) & 0x1 ? "On" : "Off"));
+}
+
+void set_flag_value(int *flag, int pos, int value)
+{
+	if (value == 1) {
+		*flag |= (1 << pos);
+	} else {		/* value is 0 */
+		*flag &= ~(1 << pos);
+	}
+}
+
+static ssize_t sysfs_dbg_msg_show(struct class *class,
+				struct class_attribute *attr, char *buf)
+{
+	pr_info("sysfs_dbg_msg_show\n");
+	show_tvout_dbg_flag();
+	return sprintf(buf, "hw_if/hdmi.c %s\n"
+		"s5p_tvout_hpd.c %s\n"
+		"s5p_tvout_common_lib.h %s\n"
+		"hw_if/hdcp.c %s\n",
+		((tvout_dbg_flag >> DBG_FLAG_HDMI) & 0x1 ? "On" : "Off"),
+		((tvout_dbg_flag >> DBG_FLAG_HPD) & 0x1 ? "On" : "Off"),
+		((tvout_dbg_flag >> DBG_FLAG_TVOUT) & 0x1 ? "On" : "Off"),
+		((tvout_dbg_flag >> DBG_FLAG_HDCP) & 0x1 ? "On" : "Off"));
+}
+
+static ssize_t sysfs_dbg_msg_store(struct class *class,
+		struct class_attribute *attr, const char *buf, size_t size)
+{
+	enum tvout_dbg_flag_bit_num tvout_dbg_flag_bit;
+	int value;
+	int i;
+	char *dest[2];
+	char *buffer = (char *)buf;
+
+	pr_info("TVOUT Debug Message setting : ");
+	for (i = 0; i < 2; i++)
+		dest[i] = strsep(&buffer, ":");
+
+	if (strcmp(dest[0], "help") == 0) {
+		pr_info(
+			"bit3 : hw_if/hdmi.c\n"
+			"bit2 : s5p_tvout_hpd.c\n"
+			"bit1 : s5p_tvout_common_lib.h\n"
+			"bit0 : hw_if/hdcp.c\n"
+			"ex1)	echo 1010 > dbg_msg\n"
+			"	hw_if/hdmi.c On\n"
+			"	s5p_tvout_hpd.c Off\n"
+			"	s5p_tvout_common_lib.h On\n"
+			"	hw_if/hdcp.c Off\n"
+			"ex2)	echo hdcp:1 > dbg_msg\n"
+			"	hw_if/hdcp.c On\n"
+		);
+		return size;
+	}
+
+	if (strcmp(dest[0], "hdcp") == 0) {
+		tvout_dbg_flag_bit = DBG_FLAG_HDCP;
+	} else if (strcmp(dest[0], "tvout") == 0) {
+		tvout_dbg_flag_bit = DBG_FLAG_TVOUT;
+	} else if (strcmp(dest[0], "hpd") == 0) {
+		tvout_dbg_flag_bit = DBG_FLAG_HPD;
+	} else if (strcmp(dest[0], "hdmi") == 0) {
+		tvout_dbg_flag_bit = DBG_FLAG_HDMI;
+	} else if (strlen(dest[0]) == 5) {
+		for (i = 0; i < 4; i++) {
+			value = dest[0][i] - '0';
+			if (value < 0 || 2 < value) {
+				pr_info("error : setting value!\n");
+				return size;
+			}
+			set_flag_value(&tvout_dbg_flag, 3-i, value);
+		}
+		show_tvout_dbg_flag();
+		return size;
+	} else {
+		pr_info("Error : Debug Message Taget\n");
+		return size;
+	}
+
+	if (strcmp(dest[1], "1\n") == 0) {
+		value = 1;
+	} else if (strcmp(dest[1], "0\n") == 0) {
+		value = 0;
+	} else {
+		pr_info("Error : Setting value!\n");
+		return size;
+	}
+
+	set_flag_value(&tvout_dbg_flag, tvout_dbg_flag_bit, value);
+	show_tvout_dbg_flag();
+
+	return size;
+}
+
+static CLASS_ATTR(dbg_msg, S_IRUGO | S_IWUSR,
+		sysfs_dbg_msg_show, sysfs_dbg_msg_store);
+#endif
+
+static int __devinit s5p_tvout_probe(struct platform_device *pdev)
+{
+#if defined(CONFIG_S5P_MEM_CMA)
+	struct cma_info mem_info;
+	int ret;
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+	int mdev_id;
+#endif
+	unsigned int vp_buff_vir_addr;
+	unsigned int vp_buff_phy_addr = 0;
+	int i;
+
+#ifdef CONFIG_HDMI_EARJACK_MUTE
+	struct class *hdmi_audio_class;
+	struct device *hdmi_audio_dev;
+#endif
+
+#ifdef CONFIG_TVOUT_DEBUG
+	struct class *sec_tvout;
+	tvout_dbg_flag = 1 << DBG_FLAG_HPD;
+#endif
+	s5p_tvout_pm_runtime_enable(&pdev->dev);
+
+#if defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_VCM)
+	if (s5p_tvout_vcm_create_unified() < 0)
+		goto err;
+
+	if (s5p_tvout_vcm_init() < 0)
+		goto err;
+#elif defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_S5P_VMEM)
+	s5p_sysmmu_enable(&pdev->dev);
+	printk(KERN_WARNING "sysmmu on\n");
+	s5p_sysmmu_set_tablebase_pgd(&pdev->dev, __pa(swapper_pg_dir));
+#endif
+	if (s5p_tvout_clk_get(pdev, &s5ptv_status) < 0)
+		goto err;
+
+	if (s5p_vp_ctrl_constructor(pdev) < 0)
+		goto err;
+
+	/* s5p_mixer_ctrl_constructor must be called
+	   before s5p_tvif_ctrl_constructor */
+	if (s5p_mixer_ctrl_constructor(pdev) < 0)
+		goto err_mixer;
+
+	if (s5p_tvif_ctrl_constructor(pdev) < 0)
+		goto err_tvif;
+
+	if (s5p_tvout_v4l2_constructor(pdev) < 0)
+		goto err_v4l2;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	spin_lock_init(&s5ptv_status.tvout_lock);
+	s5ptv_early_suspend.suspend = s5p_tvout_early_suspend;
+	s5ptv_early_suspend.resume = s5p_tvout_late_resume;
+	s5ptv_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 4;
+	register_early_suspend(&s5ptv_early_suspend);
+	suspend_status = 0;
+#endif
+
+#ifdef CONFIG_TV_FB
+#ifndef CONFIG_USER_ALLOC_TVOUT
+	s5p_hdmi_phy_power(true);
+	if (s5p_tvif_ctrl_start(TVOUT_720P_60, TVOUT_HDMI) < 0)
+		goto err_tvif_start;
+#endif
+
+	/* prepare memory */
+	if (s5p_tvout_fb_alloc_framebuffer(&pdev->dev))
+		goto err_tvif_start;
+
+	if (s5p_tvout_fb_register_framebuffer(&pdev->dev))
+		goto err_tvif_start;
+#endif
+	on_stop_process = false;
+	on_start_process = false;
+#if !defined(CONFIG_CPU_EXYNOS4212) && !defined(CONFIG_CPU_EXYNOS4412)
+#if defined(CONFIG_S5P_MEM_CMA)
+	/* CMA */
+	ret = cma_info(&mem_info, &pdev->dev, 0);
+	tvout_dbg("[cma_info] start_addr : 0x%x, end_addr : 0x%x, "
+		  "total_size : 0x%x, free_size : 0x%x\n",
+		  mem_info.lower_bound, mem_info.upper_bound,
+		  mem_info.total_size, mem_info.free_size);
+	if (ret) {
+		tvout_err("get cma info failed\n");
+		goto err_tvif_start;
+	}
+	s5ptv_vp_buff.size = mem_info.total_size;
+	if (s5ptv_vp_buff.size < S5PTV_VP_BUFF_CNT * S5PTV_VP_BUFF_SIZE) {
+		tvout_err("insufficient vp buffer size\n");
+		goto err_tvif_start;
+	}
+	vp_buff_phy_addr = (unsigned int)cma_alloc
+	    (&pdev->dev, (char *)"tvout", (size_t) s5ptv_vp_buff.size,
+	     (dma_addr_t) 0);
+
+#elif defined(CONFIG_S5P_MEM_BOOTMEM)
+	mdev_id = S5P_MDEV_TVOUT;
+	/* alloc from bank1 as default */
+	vp_buff_phy_addr = s5p_get_media_memory_bank(mdev_id, 1);
+	s5ptv_vp_buff.size = s5p_get_media_memsize_bank(mdev_id, 1);
+	if (s5ptv_vp_buff.size < S5PTV_VP_BUFF_CNT * S5PTV_VP_BUFF_SIZE) {
+		tvout_err("insufficient vp buffer size\n");
+		goto err_tvif_start;
+	}
+#endif
+
+	tvout_dbg("s5ptv_vp_buff.size = 0x%x\n", s5ptv_vp_buff.size);
+	tvout_dbg("s5ptv_vp_buff phy_base = 0x%x\n", vp_buff_phy_addr);
+
+	vp_buff_vir_addr = (unsigned int)phys_to_virt(vp_buff_phy_addr);
+	tvout_dbg("s5ptv_vp_buff vir_base = 0x%x\n", vp_buff_vir_addr);
+
+	if (!vp_buff_vir_addr) {
+		tvout_err("phys_to_virt failed\n");
+		goto err_ioremap;
+	}
+
+	for (i = 0; i < S5PTV_VP_BUFF_CNT; i++) {
+		s5ptv_vp_buff.vp_buffs[i].phy_base =
+		    vp_buff_phy_addr + (i * S5PTV_VP_BUFF_SIZE);
+		s5ptv_vp_buff.vp_buffs[i].vir_base =
+		    vp_buff_vir_addr + (i * S5PTV_VP_BUFF_SIZE);
+	}
+#else
+	for (i = 0; i < S5PTV_VP_BUFF_CNT; i++) {
+		s5ptv_vp_buff.vp_buffs[i].phy_base = 0;
+		s5ptv_vp_buff.vp_buffs[i].vir_base = 0;
+	}
+#endif
+
+	for (i = 0; i < S5PTV_VP_BUFF_CNT - 1; i++)
+		s5ptv_vp_buff.copy_buff_idxs[i] = i;
+
+	s5ptv_vp_buff.curr_copy_idx = 0;
+	s5ptv_vp_buff.vp_access_buff_idx = S5PTV_VP_BUFF_CNT - 1;
+
+#ifdef CONFIG_TVOUT_DEBUG
+	tvout_dbg("Create tvout class sysfile\n");
+
+	sec_tvout = class_create(THIS_MODULE, "tvout");
+	if (IS_ERR(sec_tvout)) {
+		tvout_err("Failed to create class(sec_tvout)!\n");
+		goto err_class;
+	}
+
+	if (class_create_file(sec_tvout, &class_attr_dbg_msg) < 0) {
+		tvout_err("failed to add sysfs entries\n");
+		goto err_sysfs;
+	}
+#endif
+
+	flag_after_resume = false;
+#ifdef CONFIG_HDMI_EARJACK_MUTE
+	hdmi_audio_class = class_create(THIS_MODULE, "hdmi_audio");
+	if (IS_ERR(hdmi_audio_class))
+		pr_err("Failed to create class(hdmi_audio)!\n");
+	hdmi_audio_dev = device_create(hdmi_audio_class, NULL, 0, NULL,
+							"hdmi_audio");
+	if (IS_ERR(hdmi_audio_dev))
+		pr_err("Failed to create device(hdmi_audio_dev)!\n");
+
+	if (device_create_file(hdmi_audio_dev,
+		&dev_attr_hdmi_audio_set_ext) < 0)
+		printk(KERN_ERR "Failed to create device file(%s)!\n",
+			dev_attr_hdmi_audio_set_ext.attr.name);
+
+	hdmi_audio_ext = false;
+#endif
+
+	return 0;
+
+err_sysfs:
+	class_destroy(sec_tvout);
+err_class:
+err_ioremap:
+#if defined(CONFIG_S5P_MEM_CMA)
+	cma_free(vp_buff_phy_addr);
+#endif
+err_tvif_start:
+	s5p_tvout_v4l2_destructor();
+err_v4l2:
+	s5p_tvif_ctrl_destructor();
+err_tvif:
+	s5p_mixer_ctrl_destructor();
+err_mixer:
+	s5p_vp_ctrl_destructor();
+err:
+	return -ENODEV;
+}
+
+static int s5p_tvout_remove(struct platform_device *pdev)
+{
+#if defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_S5P_VMEM)
+	s5p_sysmmu_off(&pdev->dev);
+	tvout_dbg("sysmmu off\n");
+#endif
+	s5p_vp_ctrl_destructor();
+	s5p_tvif_ctrl_destructor();
+	s5p_mixer_ctrl_destructor();
+
+	s5p_tvout_v4l2_destructor();
+
+	clk_disable(s5ptv_status.sclk_hdmi);
+
+	clk_put(s5ptv_status.sclk_hdmi);
+	clk_put(s5ptv_status.sclk_dac);
+	clk_put(s5ptv_status.sclk_pixel);
+	clk_put(s5ptv_status.sclk_hdmiphy);
+
+	s5p_tvout_pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void s5p_tvout_early_suspend(struct early_suspend *h)
+{
+	tvout_dbg("\n");
+	mutex_lock(&s5p_tvout_mutex);
+	s5p_mixer_ctrl_set_vsync_interrupt(false);
+	s5p_vp_ctrl_suspend();
+	s5p_mixer_ctrl_suspend();
+	s5p_tvif_ctrl_suspend();
+	suspend_status = 1;
+	tvout_dbg("suspend_status is true\n");
+	mutex_unlock(&s5p_tvout_mutex);
+
+	return;
+}
+
+static void s5p_tvout_late_resume(struct early_suspend *h)
+{
+	tvout_dbg("\n");
+
+	mutex_lock(&s5p_tvout_mutex);
+
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	if (flag_after_resume) {
+		queue_work_on(0, tvout_resume_wq, &tvout_resume_work);
+		flag_after_resume = false;
+	}
+#endif
+	suspend_status = 0;
+	tvout_dbg("suspend_status is false\n");
+	s5p_tvif_ctrl_resume();
+	s5p_mixer_ctrl_resume();
+	s5p_vp_ctrl_resume();
+	s5p_mixer_ctrl_set_vsync_interrupt(s5p_mixer_ctrl_get_vsync_interrupt());
+	mutex_unlock(&s5p_tvout_mutex);
+
+	return;
+}
+
+void s5p_tvout_mutex_lock()
+{
+	mutex_lock(&s5p_tvout_mutex);
+}
+
+void s5p_tvout_mutex_unlock()
+{
+	mutex_unlock(&s5p_tvout_mutex);
+}
+#endif
+
+static void s5p_tvout_resume_work(void *arg)
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	mutex_lock(&s5p_tvout_mutex);
+#endif
+	s5p_hdmi_ctrl_phy_power_resume();
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	mutex_unlock(&s5p_tvout_mutex);
+#endif
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static int s5p_tvout_suspend(struct device *dev)
+{
+	tvout_dbg("\n");
+	return 0;
+}
+
+static int s5p_tvout_resume(struct device *dev)
+{
+	tvout_dbg("\n");
+#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
+	flag_after_resume = true;
+#else
+	queue_work_on(0, tvout_resume_wq, &tvout_resume_work);
+#endif
+	return 0;
+}
+#else
+static int s5p_tvout_suspend(struct device *dev)
+{
+	s5p_vp_ctrl_suspend();
+	s5p_mixer_ctrl_suspend();
+	s5p_tvif_ctrl_suspend();
+	return 0;
+}
+
+static int s5p_tvout_resume(struct device *dev)
+{
+	s5p_tvif_ctrl_resume();
+	s5p_mixer_ctrl_resume();
+	s5p_vp_ctrl_resume();
+	return 0;
+}
+#endif
+static int s5p_tvout_runtime_suspend(struct device *dev)
+{
+	tvout_dbg("\n");
+	return 0;
+}
+
+static int s5p_tvout_runtime_resume(struct device *dev)
+{
+	tvout_dbg("\n");
+	return 0;
+}
+#else
+#define s5p_tvout_suspend		NULL
+#define s5p_tvout_resume		NULL
+#define s5p_tvout_runtime_suspend	NULL
+#define s5p_tvout_runtime_resume	NULL
+#endif
+
+static const struct dev_pm_ops s5p_tvout_pm_ops = {
+	.suspend = s5p_tvout_suspend,
+	.resume = s5p_tvout_resume,
+	.runtime_suspend = s5p_tvout_runtime_suspend,
+	.runtime_resume = s5p_tvout_runtime_resume
+};
+
+static struct platform_driver s5p_tvout_driver = {
+	.probe = s5p_tvout_probe,
+	.remove = s5p_tvout_remove,
+	.driver = {
+		   .name = "s5p-tvout",
+		   .owner = THIS_MODULE,
+		   .pm = &s5p_tvout_pm_ops},
+};
+
+static char banner[] __initdata =
+	KERN_INFO "S5P TVOUT Driver v3.0 (c) 2010 Samsung Electronics\n";
+
+static int __init s5p_tvout_init(void)
+{
+	int ret;
+
+	printk(banner);
+
+	ret = platform_driver_register(&s5p_tvout_driver);
+
+	if (ret) {
+		printk(KERN_ERR "Platform Device Register Failed %d\n", ret);
+
+		return -1;
+	}
+#ifdef CONFIG_PM
+	tvout_resume_wq = create_freezable_workqueue("tvout resume work");
+	if (!tvout_resume_wq) {
+		printk(KERN_ERR "Platform Device Register Failed %d\n", ret);
+		platform_driver_unregister(&s5p_tvout_driver);
+		return -1;
+	}
+
+	INIT_WORK(&tvout_resume_work, (work_func_t) s5p_tvout_resume_work);
+#endif
+
+	return 0;
+}
+
+static void __exit s5p_tvout_exit(void)
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	mutex_destroy(&s5p_tvout_mutex);
+#endif
+	platform_driver_unregister(&s5p_tvout_driver);
+}
+
+late_initcall(s5p_tvout_init);
+module_exit(s5p_tvout_exit);
+
+MODULE_AUTHOR("SangPil Moon");
+MODULE_DESCRIPTION("S5P TVOUT driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_cec.c b/drivers/media/video/samsung/tvout/s5p_tvout_cec.c
new file mode 100644
index 0000000..82e9994
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_cec.c
@@ -0,0 +1,428 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_cec_ctrl.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * cec interface file for Samsung TVOut driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/poll.h>
+#include <linux/miscdevice.h>
+#include <linux/clk.h>
+#include <linux/sched.h>
+
+#include <plat/tvout.h>
+
+#include "hw_if/hw_if.h"
+#include "s5p_tvout_common_lib.h"
+
+#define CEC_IOC_MAGIC        'c'
+#define CEC_IOC_SETLADDR     _IOW(CEC_IOC_MAGIC, 0, unsigned int)
+
+#define VERSION   "1.0" /* Driver version number */
+#define CEC_MINOR 242   /* Major 10, Minor 242, /dev/cec */
+
+
+#define CEC_STATUS_TX_RUNNING       (1<<0)
+#define CEC_STATUS_TX_TRANSFERRING  (1<<1)
+#define CEC_STATUS_TX_DONE          (1<<2)
+#define CEC_STATUS_TX_ERROR         (1<<3)
+#define CEC_STATUS_TX_BYTES         (0xFF<<8)
+#define CEC_STATUS_RX_RUNNING       (1<<16)
+#define CEC_STATUS_RX_RECEIVING     (1<<17)
+#define CEC_STATUS_RX_DONE          (1<<18)
+#define CEC_STATUS_RX_ERROR         (1<<19)
+#define CEC_STATUS_RX_BCAST         (1<<20)
+#define CEC_STATUS_RX_BYTES         (0xFF<<24)
+
+
+/* CEC Rx buffer size */
+#define CEC_RX_BUFF_SIZE            16
+/* CEC Tx buffer size */
+#define CEC_TX_BUFF_SIZE            16
+
+#define TV_CLK_GET_WITH_ERR_CHECK(clk, pdev, clk_name)			\
+		do {							\
+			clk = clk_get(&pdev->dev, clk_name);		\
+			if (IS_ERR(clk)) {				\
+				printk(KERN_ERR				\
+				"failed to find clock %s\n", clk_name);	\
+				return -ENOENT;				\
+			}						\
+		} while (0);
+
+static atomic_t hdmi_on = ATOMIC_INIT(0);
+static DEFINE_MUTEX(cec_lock);
+struct clk *hdmi_cec_clk;
+
+static int s5p_cec_open(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+
+	mutex_lock(&cec_lock);
+	clk_enable(hdmi_cec_clk);
+
+	if (atomic_read(&hdmi_on)) {
+		tvout_dbg("do not allow multiple open for tvout cec\n");
+		ret = -EBUSY;
+		goto err_multi_open;
+	} else
+		atomic_inc(&hdmi_on);
+
+	s5p_cec_reset();
+
+	s5p_cec_set_divider();
+
+	s5p_cec_threshold();
+
+	s5p_cec_unmask_tx_interrupts();
+
+	s5p_cec_set_rx_state(STATE_RX);
+	s5p_cec_unmask_rx_interrupts();
+	s5p_cec_enable_rx();
+
+err_multi_open:
+	mutex_unlock(&cec_lock);
+
+	return ret;
+}
+
+static int s5p_cec_release(struct inode *inode, struct file *file)
+{
+	atomic_dec(&hdmi_on);
+
+	s5p_cec_mask_tx_interrupts();
+	s5p_cec_mask_rx_interrupts();
+
+	clk_disable(hdmi_cec_clk);
+	clk_put(hdmi_cec_clk);
+
+	return 0;
+}
+
+static ssize_t s5p_cec_read(struct file *file, char __user *buffer,
+			size_t count, loff_t *ppos)
+{
+	ssize_t retval;
+	unsigned long spin_flags;
+
+	if (wait_event_interruptible(cec_rx_struct.waitq,
+			atomic_read(&cec_rx_struct.state) == STATE_DONE)) {
+		return -ERESTARTSYS;
+	}
+	spin_lock_irqsave(&cec_rx_struct.lock, spin_flags);
+
+	if (cec_rx_struct.size > count) {
+		spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+
+		return -1;
+	}
+
+	if (copy_to_user(buffer, cec_rx_struct.buffer, cec_rx_struct.size)) {
+		spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+		printk(KERN_ERR " copy_to_user() failed!\n");
+
+		return -EFAULT;
+	}
+
+	retval = cec_rx_struct.size;
+
+	s5p_cec_set_rx_state(STATE_RX);
+	spin_unlock_irqrestore(&cec_rx_struct.lock, spin_flags);
+
+	return retval;
+}
+
+static ssize_t s5p_cec_write(struct file *file, const char __user *buffer,
+			size_t count, loff_t *ppos)
+{
+	char *data;
+
+	/* check data size */
+
+	if (count > CEC_TX_BUFF_SIZE || count == 0)
+		return -1;
+
+	data = kmalloc(count, GFP_KERNEL);
+
+	if (!data) {
+		printk(KERN_ERR " kmalloc() failed!\n");
+
+		return -1;
+	}
+
+	if (copy_from_user(data, buffer, count)) {
+		printk(KERN_ERR " copy_from_user() failed!\n");
+		kfree(data);
+
+		return -EFAULT;
+	}
+
+	s5p_cec_copy_packet(data, count);
+
+	kfree(data);
+
+	/* wait for interrupt */
+	if (wait_event_interruptible(cec_tx_struct.waitq,
+		atomic_read(&cec_tx_struct.state)
+		!= STATE_TX)) {
+
+		return -ERESTARTSYS;
+	}
+
+	if (atomic_read(&cec_tx_struct.state) == STATE_ERROR)
+		return -1;
+
+	return count;
+}
+
+#if 0
+static int s5p_cec_ioctl(struct inode *inode, struct file *file, u32 cmd,
+			unsigned long arg)
+#else
+static long s5p_cec_ioctl(struct file *file, unsigned int cmd,
+						unsigned long arg)
+#endif
+{
+	u32 laddr;
+
+	switch (cmd) {
+	case CEC_IOC_SETLADDR:
+		if (get_user(laddr, (u32 __user *) arg))
+			return -EFAULT;
+
+		tvout_dbg("logical address = 0x%02x\n", laddr);
+
+		s5p_cec_set_addr(laddr);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static u32 s5p_cec_poll(struct file *file, poll_table *wait)
+{
+	poll_wait(file, &cec_rx_struct.waitq, wait);
+
+	if (atomic_read(&cec_rx_struct.state) == STATE_DONE)
+		return POLLIN | POLLRDNORM;
+
+	return 0;
+}
+
+static const struct file_operations cec_fops = {
+	.owner   = THIS_MODULE,
+	.open    = s5p_cec_open,
+	.release = s5p_cec_release,
+	.read    = s5p_cec_read,
+	.write   = s5p_cec_write,
+#if 1
+	.unlocked_ioctl = s5p_cec_ioctl,
+#else
+	.ioctl   = s5p_cec_ioctl,
+#endif
+	.poll    = s5p_cec_poll,
+};
+
+static struct miscdevice cec_misc_device = {
+	.minor = CEC_MINOR,
+	.name  = "CEC",
+	.fops  = &cec_fops,
+};
+
+static irqreturn_t s5p_cec_irq_handler(int irq, void *dev_id)
+{
+
+	u32 status = 0;
+
+	status = s5p_cec_get_status();
+
+	if (status & CEC_STATUS_TX_DONE) {
+		if (status & CEC_STATUS_TX_ERROR) {
+			tvout_dbg(" CEC_STATUS_TX_ERROR!\n");
+			s5p_cec_set_tx_state(STATE_ERROR);
+		} else {
+			tvout_dbg(" CEC_STATUS_TX_DONE!\n");
+			s5p_cec_set_tx_state(STATE_DONE);
+		}
+
+		s5p_clr_pending_tx();
+
+		wake_up_interruptible(&cec_tx_struct.waitq);
+	}
+
+	if (status & CEC_STATUS_RX_DONE) {
+		if (status & CEC_STATUS_RX_ERROR) {
+			tvout_dbg(" CEC_STATUS_RX_ERROR!\n");
+			s5p_cec_rx_reset();
+
+		} else {
+			u32 size;
+
+			tvout_dbg(" CEC_STATUS_RX_DONE!\n");
+
+			/* copy data from internal buffer */
+			size = status >> 24;
+
+			spin_lock(&cec_rx_struct.lock);
+
+			s5p_cec_get_rx_buf(size, cec_rx_struct.buffer);
+
+			cec_rx_struct.size = size;
+
+			s5p_cec_set_rx_state(STATE_DONE);
+
+			spin_unlock(&cec_rx_struct.lock);
+
+			s5p_cec_enable_rx();
+		}
+
+		/* clear interrupt pending bit */
+		s5p_clr_pending_rx();
+
+		wake_up_interruptible(&cec_rx_struct.waitq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit s5p_cec_probe(struct platform_device *pdev)
+{
+	struct s5p_platform_cec *pdata;
+	u8 *buffer;
+	int irq_num;
+	int ret;
+
+	pdata = to_tvout_plat(&pdev->dev);
+
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdev);
+
+	/* get ioremap addr */
+	ret = s5p_cec_mem_probe(pdev);
+	if (ret != 0) {
+		printk(KERN_ERR  "failed to s5p_cec_mem_probe ret = %d\n", ret);
+		goto err_mem_probe;
+	}
+
+	if (misc_register(&cec_misc_device)) {
+		printk(KERN_WARNING " Couldn't register device 10, %d.\n",
+			CEC_MINOR);
+		ret = -EBUSY;
+		goto err_misc_register;
+	}
+
+	irq_num = platform_get_irq(pdev, 0);
+	if (irq_num < 0) {
+		printk(KERN_ERR  "failed to get %s irq resource\n", "cec");
+		ret = -ENOENT;
+		goto err_get_irq;
+	}
+
+	ret = request_irq(irq_num, s5p_cec_irq_handler, IRQF_DISABLED,
+		pdev->name, &pdev->id);
+	if (ret != 0) {
+		printk(KERN_ERR  "failed to install %s irq (%d)\n", "cec", ret);
+		goto err_request_irq;
+	}
+
+	init_waitqueue_head(&cec_rx_struct.waitq);
+	spin_lock_init(&cec_rx_struct.lock);
+	init_waitqueue_head(&cec_tx_struct.waitq);
+
+	buffer = kmalloc(CEC_TX_BUFF_SIZE, GFP_KERNEL);
+	if (!buffer) {
+		printk(KERN_ERR " kmalloc() failed!\n");
+		misc_deregister(&cec_misc_device);
+		ret = -EIO;
+		goto err_kmalloc;
+	}
+
+	cec_rx_struct.buffer = buffer;
+	cec_rx_struct.size   = 0;
+	TV_CLK_GET_WITH_ERR_CHECK(hdmi_cec_clk, pdev, "hdmicec");
+
+err_kmalloc:
+	free_irq(irq_num, &pdev->id);
+err_request_irq:
+err_get_irq:
+	misc_deregister(&cec_misc_device);
+err_misc_register:
+err_mem_probe:
+
+	return 0;
+}
+
+static int __devexit s5p_cec_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_cec_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int s5p_cec_resume(struct platform_device *dev)
+{
+	return 0;
+}
+#else
+#define s5p_cec_suspend NULL
+#define s5p_cec_resume NULL
+#endif
+
+static struct platform_driver s5p_cec_driver = {
+	.probe		= s5p_cec_probe,
+	.remove		= __devexit_p(s5p_cec_remove),
+	.suspend	= s5p_cec_suspend,
+	.resume		= s5p_cec_resume,
+	.driver		= {
+		.name	= "s5p-tvout-cec",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static char banner[] __initdata =
+	"S5P CEC Driver, (c) 2009 Samsung Electronics\n";
+
+static int __init s5p_cec_init(void)
+{
+	int ret;
+
+	printk(banner);
+
+	ret = platform_driver_register(&s5p_cec_driver);
+
+	if (ret) {
+		printk(KERN_ERR "Platform Device Register Failed %d\n", ret);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+static void __exit s5p_cec_exit(void)
+{
+	kfree(cec_rx_struct.buffer);
+
+	platform_driver_unregister(&s5p_cec_driver);
+}
+
+module_init(s5p_cec_init);
+module_exit(s5p_cec_exit);
+
+MODULE_AUTHOR("SangPil Moon");
+MODULE_DESCRIPTION("S5P CEC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.c b/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.c
new file mode 100644
index 0000000..dd69187
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.c
@@ -0,0 +1,183 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Common library file for SAMSUNG TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <linux/pm_runtime.h>
+
+#include "s5p_tvout_common_lib.h"
+
+#ifdef CONFIG_VCM
+#include <plat/s5p-vcm.h>
+#endif
+
+#ifdef CONFIG_VCM
+static atomic_t		s5p_tvout_vcm_usage = ATOMIC_INIT(0);
+
+static void tvout_tlb_invalidator(enum vcm_dev_id id)
+{
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (atomic_read(&s5p_tvout_vcm_usage) == 0) {
+		return (void)0;
+	}
+#endif
+}
+
+static void tvout_pgd_base_specifier(enum vcm_dev_id id, unsigned long base)
+{
+
+#if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
+	if (atomic_read(&s5p_tvout_vcm_usage) == 0) {
+		return (void)0;
+	}
+#endif
+}
+
+static struct s5p_vcm_driver s5ptv_vcm_driver = {
+	.tlb_invalidator = &tvout_tlb_invalidator,
+	.pgd_base_specifier = &tvout_pgd_base_specifier,
+	.phys_alloc = NULL,
+	.phys_free = NULL,
+};
+
+#endif
+
+
+#ifdef CONFIG_VCM
+static struct vcm	*s5p_vcm;
+
+int s5p_tvout_vcm_create_unified(void)
+{
+	s5p_vcm = vcm_create_unified((SZ_64M), VCM_DEV_TV,
+						&s5ptv_vcm_driver);
+
+	if (IS_ERR(s5p_vcm))
+		return PTR_ERR(s5p_vcm);
+
+	return 0;
+}
+
+int s5p_tvout_vcm_init(void)
+{
+	if (vcm_activate(s5p_vcm) < 0)
+		return -1;
+
+	return 0;
+}
+
+void s5p_tvout_vcm_activate(void)
+{
+	vcm_set_pgtable_base(VCM_DEV_TV);
+}
+
+void s5p_tvout_vcm_deactivate(void)
+{
+}
+
+
+#endif
+int s5p_tvout_map_resource_mem(
+		struct platform_device *pdev, char *name,
+		void __iomem **base, struct resource **res)
+{
+	size_t		size;
+	void __iomem	*tmp_base;
+	struct resource	*tmp_res;
+
+	tmp_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+
+	if (!tmp_res)
+		goto not_found;
+
+	size = (tmp_res->end - tmp_res->start) + 1;
+
+	tmp_res = request_mem_region(tmp_res->start, size, tmp_res->name);
+
+	if (!tmp_res) {
+		tvout_err("%s: fail to get memory region\n", __func__);
+		goto err_on_request_mem_region;
+	}
+
+	tmp_base = ioremap(tmp_res->start, size);
+
+	if (!tmp_base) {
+		tvout_err("%s: fail to ioremap address region\n", __func__);
+		goto err_on_ioremap;
+	}
+
+	*res = tmp_res;
+	*base = tmp_base;
+	return 0;
+
+err_on_ioremap:
+	release_resource(tmp_res);
+	kfree(tmp_res);
+
+err_on_request_mem_region:
+	return -ENXIO;
+
+not_found:
+	tvout_err("%s: fail to get IORESOURCE_MEM for %s\n", __func__, name);
+	return -ENODEV;
+}
+
+void s5p_tvout_unmap_resource_mem(
+		void __iomem *base, struct resource *res)
+{
+	if (base)
+		iounmap(base);
+
+	if (res) {
+		release_resource(res);
+		kfree(res);
+	}
+}
+
+/* Libraries for runtime PM */
+static struct device *s5p_tvout_dev;
+
+void s5p_tvout_pm_runtime_enable(struct device *dev)
+{
+	pm_runtime_enable(dev);
+
+	s5p_tvout_dev = dev;
+}
+
+void s5p_tvout_pm_runtime_disable(struct device *dev)
+{
+	pm_runtime_disable(dev);
+}
+
+void s5p_tvout_pm_runtime_get(void)
+{
+	pm_runtime_get_sync(s5p_tvout_dev);
+
+#ifdef CONFIG_VCM
+	atomic_inc(&s5p_tvout_vcm_usage);
+	if (atomic_read(&s5p_tvout_vcm_usage) == 1)
+		s5p_tvout_vcm_activate();
+#endif
+}
+
+void s5p_tvout_pm_runtime_put(void)
+{
+#ifdef CONFIG_VCM
+	if (atomic_read(&s5p_tvout_vcm_usage) == 1)
+		s5p_tvout_vcm_deactivate();
+
+	atomic_dec(&s5p_tvout_vcm_usage);
+#endif
+
+	pm_runtime_put_sync(s5p_tvout_dev);
+}
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.h b/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.h
new file mode 100644
index 0000000..e43b9c7
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.h
@@ -0,0 +1,268 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_common_lib.h
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Header file of common library for SAMSUNG TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _S5P_TVOUT_COMMON_LIB_H_
+#define _S5P_TVOUT_COMMON_LIB_H_
+
+#include <linux/stddef.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/interrupt.h>
+
+/*****************************************************************************
+ * This file includes declarations for TVOUT driver's common library.
+ * All files in TVOUT driver can access function or definition in this file.
+ ****************************************************************************/
+
+#define DRV_NAME	"TVOUT"
+
+#define tvout_err(fmt, ...)					\
+		printk(KERN_ERR "[%s] %s(): " fmt,		\
+			DRV_NAME, __func__, ##__VA_ARGS__)
+
+#define CONFIG_TVOUT_DEBUG
+
+#ifndef tvout_dbg
+#ifdef CONFIG_TVOUT_DEBUG
+#define tvout_dbg(fmt, ...)					\
+do {								\
+	if (unlikely(tvout_dbg_flag & (1 << DBG_FLAG_TVOUT))) {	\
+		printk(KERN_INFO "[%s] %s(): " fmt,		\
+			DRV_NAME, __func__, ##__VA_ARGS__);	\
+	}							\
+} while (0)
+#else
+#define tvout_dbg(fmt, ...)
+#endif
+#endif
+
+#define S5PTV_FB_CNT	2
+#define S5PTV_VP_BUFF_CNT	4
+#define S5PTV_VP_BUFF_SIZE	(4*1024*1024)
+
+#define to_tvout_plat(d) (to_platform_device(d)->dev.platform_data)
+
+#define HDMI_START_NUM 0x1000
+
+enum s5p_tvout_disp_mode {
+	TVOUT_NTSC_M = 0,
+	TVOUT_PAL_BDGHI,
+	TVOUT_PAL_M,
+	TVOUT_PAL_N,
+	TVOUT_PAL_NC,
+	TVOUT_PAL_60,
+	TVOUT_NTSC_443,
+
+	TVOUT_480P_60_16_9 = HDMI_START_NUM,
+	TVOUT_480P_60_4_3,
+	TVOUT_480P_59,
+
+	TVOUT_576P_50_16_9,
+	TVOUT_576P_50_4_3,
+
+	TVOUT_720P_60,
+	TVOUT_720P_50,
+	TVOUT_720P_59,
+
+	TVOUT_1080P_60,
+	TVOUT_1080P_50,
+	TVOUT_1080P_59,
+	TVOUT_1080P_30,
+
+	TVOUT_1080I_60,
+	TVOUT_1080I_50,
+	TVOUT_1080I_59,
+#ifdef CONFIG_HDMI_14A_3D
+	TVOUT_720P_60_SBS_HALF,
+	TVOUT_720P_59_SBS_HALF,
+	TVOUT_720P_50_TB,
+	TVOUT_1080P_24_TB,
+	TVOUT_1080P_23_TB,
+#endif
+	TVOUT_INIT_DISP_VALUE
+};
+
+#ifdef CONFIG_HDMI_14A_3D
+enum s5p_tvout_3d_type {
+	HDMI_3D_FP_FORMAT,
+	HDMI_3D_SSH_FORMAT,
+	HDMI_3D_TB_FORMAT,
+	HDMI_2D_FORMAT,
+};
+#endif
+
+enum s5p_tvout_o_mode {
+	TVOUT_COMPOSITE,
+	TVOUT_HDMI,
+	TVOUT_HDMI_RGB,
+	TVOUT_DVI,
+	TVOUT_INIT_O_VALUE
+};
+
+enum s5p_mixer_burst_mode {
+	MIXER_BURST_8 = 0,
+	MIXER_BURST_16 = 1
+};
+
+enum s5ptv_audio_channel {
+	TVOUT_AUDIO_2CH = 0,
+	TVOUT_AUDIO_5_1CH = 1,
+	TVOUT_AUDIO_2CH_VAL = 2,
+	TVOUT_AUDIO_5_1CH_VAL = 6,
+};
+
+enum s5ptvfb_data_path_t {
+	DATA_PATH_FIFO = 0,
+	DATA_PATH_DMA = 1,
+};
+
+enum s5ptvfb_alpha_t {
+	LAYER_BLENDING,
+	PIXEL_BLENDING,
+	NONE_BLENDING,
+};
+
+enum s5ptvfb_ver_scaling_t {
+	VERTICAL_X1,
+	VERTICAL_X2,
+};
+
+enum s5ptvfb_hor_scaling_t {
+	HORIZONTAL_X1,
+	HORIZONTAL_X2,
+};
+
+struct s5ptvfb_alpha {
+	enum s5ptvfb_alpha_t	mode;
+	int			channel;
+	unsigned int		value;
+};
+
+struct s5ptvfb_chroma {
+	int		enabled;
+	unsigned int	key;
+};
+
+struct s5ptvfb_user_window {
+	int x;
+	int y;
+};
+
+struct s5ptvfb_user_plane_alpha {
+	int		channel;
+	unsigned char	alpha;
+};
+
+struct s5ptvfb_user_chroma {
+	int		enabled;
+	unsigned char	red;
+	unsigned char	green;
+	unsigned char	blue;
+};
+
+struct s5ptvfb_user_scaling {
+	enum s5ptvfb_ver_scaling_t ver;
+	enum s5ptvfb_hor_scaling_t hor;
+};
+
+struct s5p_tvout_status {
+	struct clk *i2c_phy_clk;
+	struct clk *sclk_hdmiphy;
+	struct clk *sclk_pixel;
+	struct clk *sclk_dac;
+	struct clk *sclk_hdmi;
+	spinlock_t tvout_lock;
+};
+
+struct s5p_tvout_vp_buff {
+	unsigned int        phy_base;
+	unsigned int        vir_base;
+	unsigned int        size;
+};
+
+struct s5p_tvout_vp_bufferinfo {
+	struct s5p_tvout_vp_buff    vp_buffs[S5PTV_VP_BUFF_CNT];
+	unsigned int                copy_buff_idxs[S5PTV_VP_BUFF_CNT - 1];
+	unsigned int                curr_copy_idx;
+	unsigned int                vp_access_buff_idx;
+	unsigned int                size;
+};
+
+struct s5ptv_vp_buf_info {
+	unsigned int                buff_cnt;
+	struct s5p_tvout_vp_buff    *buffs;
+};
+
+struct reg_mem_info {
+	char		*name;
+	struct resource *res;
+	void __iomem	*base;
+};
+
+struct irq_info {
+	char		*name;
+	irq_handler_t	handler;
+	int		no;
+};
+
+struct s5p_tvout_clk_info {
+	char		*name;
+	struct clk	*ptr;
+};
+
+#ifdef CONFIG_TVOUT_DEBUG
+enum tvout_dbg_flag_bit_num {
+	DBG_FLAG_HDCP = 0,
+	DBG_FLAG_TVOUT,
+	DBG_FLAG_HPD,
+	DBG_FLAG_HDMI
+};
+
+extern int tvout_dbg_flag;
+#endif
+
+extern struct s5p_tvout_status s5ptv_status;
+
+extern int s5p_tvout_vcm_create_unified(void);
+
+extern int s5p_tvout_vcm_init(void);
+
+extern void s5p_tvout_vcm_activate(void);
+
+extern void s5p_tvout_vcm_deactivate(void);
+
+extern int s5p_tvout_map_resource_mem(
+		struct platform_device *pdev, char *name,
+		void __iomem **base, struct resource **res);
+extern void s5p_tvout_unmap_resource_mem(
+		void __iomem *base, struct resource *res);
+
+extern void s5p_tvout_pm_runtime_enable(struct device *dev);
+extern void s5p_tvout_pm_runtime_disable(struct device *dev);
+extern void s5p_tvout_pm_runtime_get(void);
+extern void s5p_tvout_pm_runtime_put(void);
+
+extern void s5p_hdmi_ctrl_clock(bool on);
+extern bool on_stop_process;
+extern bool on_start_process;
+extern struct s5p_tvout_vp_bufferinfo s5ptv_vp_buff;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+extern unsigned int suspend_status;
+extern int s5p_hpd_get_status(void);
+extern void s5p_tvout_mutex_lock(void);
+extern void s5p_tvout_mutex_unlock(void);
+#endif
+#ifdef CONFIG_PM
+extern void s5p_hdmi_ctrl_phy_power_resume(void);
+#endif
+
+#endif /* _S5P_TVOUT_COMMON_LIB_H_ */
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_ctrl.h b/drivers/media/video/samsung/tvout/s5p_tvout_ctrl.h
new file mode 100644
index 0000000..43043b4
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_ctrl.h
@@ -0,0 +1,132 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_ctrl.h
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Header file for tvout control class of Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef _S5P_TVOUT_CTRL_H_
+#define _S5P_TVOUT_CTRL_H_ __FILE__
+
+/*****************************************************************************
+ * This file includes declarations for external functions of
+ * TVOUT driver's control class. So only external functions
+ * to be used by higher layer must exist in this file.
+ *
+ * Higher layer must use only the declarations included in this file.
+ ****************************************************************************/
+
+#include "hw_if/hw_if.h"
+#include "s5p_tvout_common_lib.h"
+
+/****************************************
+ * for Mixer control class
+ ***************************************/
+extern void s5p_mixer_ctrl_init_fb_addr_phy(enum s5p_mixer_layer layer,
+		dma_addr_t fb_addr);
+extern void s5p_mixer_ctrl_init_grp_layer(enum s5p_mixer_layer layer);
+extern int s5p_mixer_ctrl_set_pixel_format(enum s5p_mixer_layer layer, u32 bpp, u32 trans_len);
+extern int s5p_mixer_ctrl_enable_layer(enum s5p_mixer_layer layer);
+extern int s5p_mixer_ctrl_disable_layer(enum s5p_mixer_layer layer);
+extern int s5p_mixer_ctrl_set_priority(enum s5p_mixer_layer layer, u32 prio);
+extern int s5p_mixer_ctrl_set_dst_win_pos(enum s5p_mixer_layer layer,
+		int dst_x, int dst_y, u32 w, u32 h);
+extern int s5p_mixer_ctrl_set_src_win_pos(enum s5p_mixer_layer layer,
+		u32 src_x, u32 src_y, u32 w, u32 h);
+extern int s5p_mixer_ctrl_set_buffer_address(enum s5p_mixer_layer layer,
+		dma_addr_t start_addr);
+extern int s5p_mixer_ctrl_set_chroma_key(enum s5p_mixer_layer layer,
+		struct s5ptvfb_chroma chroma);
+extern int s5p_mixer_ctrl_set_alpha(enum s5p_mixer_layer layer, u32 alpha);
+extern int s5p_mixer_ctrl_set_blend_mode(enum s5p_mixer_layer layer,
+		enum s5ptvfb_alpha_t mode);
+extern int s5p_mixer_ctrl_set_alpha_blending(enum s5p_mixer_layer layer,
+		enum s5ptvfb_alpha_t blend_mode, unsigned int alpha);
+extern int s5p_mixer_ctrl_scaling(enum s5p_mixer_layer,
+		struct s5ptvfb_user_scaling scaling);
+extern int s5p_mixer_ctrl_mux_clk(struct clk *ptr);
+extern void s5p_mixer_ctrl_set_int_enable(bool en);
+extern void s5p_mixer_ctrl_set_vsync_interrupt(bool en);
+extern bool s5p_mixer_ctrl_get_vsync_interrupt(void);
+extern void s5p_mixer_ctrl_clear_pend_all(void);
+extern void s5p_mixer_ctrl_stop(void);
+extern void s5p_mixer_ctrl_internal_start(void);
+extern int s5p_mixer_ctrl_start(enum s5p_tvout_disp_mode disp,
+		enum s5p_tvout_o_mode out);
+extern int s5p_mixer_ctrl_constructor(struct platform_device *pdev);
+extern void s5p_mixer_ctrl_destructor(void);
+extern void s5p_mixer_ctrl_suspend(void);
+extern void s5p_mixer_ctrl_resume(void);
+
+/* Interrupt for Vsync */
+typedef struct {
+	wait_queue_head_t	wq;
+	unsigned int		wq_count;
+} s5p_tv_irq;
+
+extern wait_queue_head_t s5ptv_wq;
+
+/****************************************
+ * for TV interface control class
+ ***************************************/
+extern int s5p_tvif_ctrl_set_audio(bool en);
+extern void s5p_tvif_audio_channel(int channel);
+extern void s5p_tvif_q_color_range(int range);
+extern int s5p_tvif_get_q_range(void);
+extern int s5p_tvif_ctrl_set_av_mute(bool en);
+extern int s5p_tvif_ctrl_get_std_if(
+		enum s5p_tvout_disp_mode *std, enum s5p_tvout_o_mode *inf);
+extern bool s5p_tvif_ctrl_get_run_state(void);
+extern int s5p_tvif_ctrl_start(
+		enum s5p_tvout_disp_mode std, enum s5p_tvout_o_mode inf);
+extern void s5p_tvif_ctrl_stop(void);
+
+extern int s5p_tvif_ctrl_constructor(struct platform_device *pdev);
+extern void s5p_tvif_ctrl_destructor(void);
+extern void s5p_tvif_ctrl_suspend(void);
+extern void s5p_tvif_ctrl_resume(void);
+
+extern u8 s5p_hdmi_ctrl_get_mute(void);
+extern void s5p_hdmi_ctrl_set_hdcp(bool en);
+
+extern int s5p_hpd_set_hdmiint(void);
+extern int s5p_hpd_set_eint(void);
+
+#ifdef CONFIG_HDMI_EARJACK_MUTE
+extern void s5p_hdmi_ctrl_set_audio(bool en);
+#endif
+
+/****************************************
+ * for VP control class
+ ***************************************/
+enum s5p_vp_src_color {
+	VP_SRC_COLOR_NV12,
+	VP_SRC_COLOR_NV12IW,
+	VP_SRC_COLOR_TILE_NV12,
+	VP_SRC_COLOR_TILE_NV12IW,
+	VP_SRC_COLOR_NV21,
+	VP_SRC_COLOR_NV21IW,
+	VP_SRC_COLOR_TILE_NV21,
+	VP_SRC_COLOR_TILE_NV21IW
+};
+
+extern void s5p_vp_ctrl_set_src_plane(
+		u32 base_y, u32 base_c, u32 width, u32 height,
+		enum s5p_vp_src_color color, enum s5p_vp_field field);
+extern void s5p_vp_ctrl_set_src_win(u32 left, u32 top, u32 width, u32 height);
+extern void s5p_vp_ctrl_set_dest_win(u32 left, u32 top, u32 width, u32 height);
+extern void s5p_vp_ctrl_set_dest_win_alpha_val(u32 alpha);
+extern void s5p_vp_ctrl_set_dest_win_blend(bool enable);
+extern void s5p_vp_ctrl_set_dest_win_priority(u32 prio);
+extern int s5p_vp_ctrl_start(void);
+extern void s5p_vp_ctrl_stop(void);
+extern int s5p_vp_ctrl_constructor(struct platform_device *pdev);
+extern void s5p_vp_ctrl_destructor(void);
+extern void s5p_vp_ctrl_suspend(void);
+void s5p_vp_ctrl_resume(void);
+
+#endif /* _S5P_TVOUT_CTRL_H_ */
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_fb.c b/drivers/media/video/samsung/tvout/s5p_tvout_fb.c
new file mode 100644
index 0000000..5a2ce5a
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_fb.c
@@ -0,0 +1,754 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_fb.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Frame buffer ftn. file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <linux/uaccess.h>
+
+#include "s5p_tvout_common_lib.h"
+#include "s5p_tvout_ctrl.h"
+#include "s5p_tvout_v4l2.h"
+
+#ifdef CONFIG_UMP_VCM_ALLOC
+#include "ump_kernel_interface.h"
+#endif
+
+#define S5PTVFB_NAME		"s5ptvfb"
+
+#define S5PTV_FB_LAYER0_MINOR	10
+#define S5PTV_FB_LAYER1_MINOR	11
+
+#define FB_INDEX(id)	(id - S5PTV_FB_LAYER0_MINOR)
+
+#define S5PTVFB_CHROMA(r, g, b)	\
+	(((r & 0xff) << 16) | ((g & 0xff) << 8) | ((b & 0xff) << 0))
+
+#define S5PTVFB_WIN_POSITION	\
+	_IOW('F', 213, struct s5ptvfb_user_window)
+#define S5PTVFB_WIN_SET_PLANE_ALPHA	\
+	_IOW('F', 214, struct s5ptvfb_user_plane_alpha)
+#define S5PTVFB_WIN_SET_CHROMA	\
+	_IOW('F', 215, struct s5ptvfb_user_chroma)
+#define S5PTVFB_WAITFORVSYNC \
+	_IO('F', 32)
+#define S5PTVFB_SET_VSYNC_INT \
+	_IOW('F', 216, u32)
+#define S5PTVFB_WIN_SET_ADDR	\
+	_IOW('F', 219, u32)
+#define S5PTVFB_SCALING	\
+	_IOW('F', 222, struct s5ptvfb_user_scaling)
+
+struct s5ptvfb_window {
+	int				id;
+	struct device			*dev_fb;
+	int				enabled;
+	atomic_t			in_use;
+	int				x;
+	int				y;
+	enum s5ptvfb_data_path_t	path;
+	int				local_channel;
+	int				dma_burst;
+	unsigned int			pseudo_pal[16];
+	struct s5ptvfb_alpha		alpha;
+	struct s5ptvfb_chroma		chroma;
+	int				(*suspend_fifo)(void);
+	int				(*resume_fifo)(void);
+};
+
+struct s5ptvfb_lcd_timing {
+	int	h_fp;
+	int	h_bp;
+	int	h_sw;
+	int	v_fp;
+	int	v_fpe;
+	int	v_bp;
+	int	v_bpe;
+	int	v_sw;
+};
+
+struct s5ptvfb_lcd_polarity {
+	int	rise_vclk;
+	int	inv_hsync;
+	int	inv_vsync;
+	int	inv_vden;
+};
+
+struct s5ptvfb_lcd {
+	int				width;
+	int				height;
+	int				bpp;
+	int				freq;
+	struct s5ptvfb_lcd_timing	timing;
+	struct s5ptvfb_lcd_polarity	polarity;
+
+	void				(*init_ldi)(void);
+};
+
+static struct mutex fb_lock;
+
+static struct fb_info *fb[S5PTV_FB_CNT];
+static struct s5ptvfb_lcd lcd = {
+	.width = 1920,
+	.height = 1080,
+	.bpp = 32,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 49,
+		.h_bp = 17,
+		.h_sw = 33,
+		.v_fp = 4,
+		.v_fpe = 1,
+		.v_bp = 15,
+		.v_bpe = 1,
+		.v_sw = 6,
+	},
+
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static int s5p_tvout_fb_wait_for_vsync(void)
+{
+	sleep_on_timeout(&s5ptv_wq, HZ / 10);
+
+	return 0;
+}
+
+static inline unsigned int s5p_tvout_fb_chan_to_field(unsigned int chan,
+						struct fb_bitfield bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf.length;
+
+	return chan << bf.offset;
+}
+
+static int s5p_tvout_fb_set_alpha_info(struct fb_var_screeninfo *var,
+				struct s5ptvfb_window *win)
+{
+	if (var->transp.length > 0)
+		win->alpha.mode = PIXEL_BLENDING;
+	else
+		win->alpha.mode = NONE_BLENDING;
+
+	return 0;
+}
+#if 0 /* This function will be used in the future */
+static int s5p_tvout_fb_map_video_memory(int id)
+{
+	enum s5p_mixer_layer layer;
+	struct s5ptvfb_window *win = fb[FB_INDEX(id)]->par;
+	struct fb_fix_screeninfo *fix = &fb[FB_INDEX(id)]->fix;
+
+	if (win->path == DATA_PATH_FIFO)
+		return 0;
+
+	fb[FB_INDEX(id)]->screen_base = dma_alloc_writecombine(win->dev_fb,
+			PAGE_ALIGN(fix->smem_len),
+			(unsigned int *) &fix->smem_start, GFP_KERNEL);
+
+	switch (id) {
+	case S5PTV_FB_LAYER0_MINOR:
+		layer = MIXER_GPR0_LAYER;
+		break;
+	case S5PTV_FB_LAYER1_MINOR:
+		layer = MIXER_GPR1_LAYER;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+	s5p_mixer_ctrl_init_fb_addr_phy(layer, fix->smem_start);
+
+	if (!fb[FB_INDEX(id)]->screen_base)
+		return -1;
+	else
+		tvout_dbg("[fb%d] dma: 0x%08x, cpu: 0x%08x,size: 0x%08x\n",
+			win->id, (unsigned int) fix->smem_start,
+			(unsigned int) fb[FB_INDEX(id)]->screen_base,
+			fix->smem_len);
+
+	memset(fb[FB_INDEX(id)]->screen_base, 0, fix->smem_len);
+
+	return 0;
+}
+#endif
+static int s5p_tvout_fb_set_bitfield(struct fb_var_screeninfo *var)
+{
+	switch (var->bits_per_pixel) {
+	case 16:
+		if (var->transp.length == 1) {
+			var->red.offset = 10;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 5;
+			var->blue.offset = 0;
+			var->blue.length = 5;
+			var->transp.offset = 15;
+		} else if (var->transp.length == 4) {
+			var->red.offset = 8;
+			var->red.length = 4;
+			var->green.offset = 4;
+			var->green.length = 4;
+			var->blue.offset = 0;
+			var->blue.length = 4;
+			var->transp.offset = 12;
+		} else {
+			var->red.offset = 11;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 6;
+			var->blue.offset = 0;
+			var->blue.length = 5;
+			var->transp.offset = 0;
+		}
+		break;
+
+	case 24:
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+
+	case 32:
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		var->transp.offset = 24;
+		break;
+	}
+
+	return 0;
+}
+
+static int s5p_tvout_fb_setcolreg(unsigned int regno, unsigned int red,
+				unsigned int green, unsigned int blue,
+				unsigned int transp, struct fb_info *fb)
+{
+	unsigned int *pal = (unsigned int *) fb->pseudo_palette;
+	unsigned int val = 0;
+
+	if (regno < 16) {
+		/* fake palette of 16 colors */
+		val |= s5p_tvout_fb_chan_to_field(red, fb->var.red);
+		val |= s5p_tvout_fb_chan_to_field(green, fb->var.green);
+		val |= s5p_tvout_fb_chan_to_field(blue, fb->var.blue);
+		val |= s5p_tvout_fb_chan_to_field(transp, fb->var.transp);
+
+		pal[regno] = val;
+	}
+
+	return 0;
+}
+
+static int s5p_tvout_fb_pan_display(struct fb_var_screeninfo *var,
+				struct fb_info *fb)
+{
+	dma_addr_t start_addr;
+	enum s5p_mixer_layer layer;
+	struct fb_fix_screeninfo *fix = &fb->fix;
+
+	if (var->yoffset + var->yres > var->yres_virtual) {
+		tvout_err("invalid y offset value\n");
+		return -1;
+	}
+
+	fb->var.yoffset = var->yoffset;
+
+	switch (fb->node) {
+	case S5PTV_FB_LAYER0_MINOR:
+		layer = MIXER_GPR0_LAYER;
+		break;
+	case S5PTV_FB_LAYER1_MINOR:
+		layer = MIXER_GPR1_LAYER;
+		break;
+	default:
+		tvout_err("invalid layer\n");
+		return -1;
+	}
+
+	start_addr = fix->smem_start + (var->xres_virtual *
+				(var->bits_per_pixel / 8) * var->yoffset);
+
+	s5p_mixer_ctrl_set_buffer_address(layer, start_addr);
+
+	return 0;
+}
+
+static int s5p_tvout_fb_blank(int blank_mode, struct fb_info *fb)
+{
+	enum s5p_mixer_layer layer = MIXER_GPR0_LAYER;
+
+	tvout_dbg("change blank mode\n");
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	switch (fb->node) {
+	case S5PTV_FB_LAYER0_MINOR:
+		layer = MIXER_GPR0_LAYER;
+		break;
+	case S5PTV_FB_LAYER1_MINOR:
+		layer = MIXER_GPR1_LAYER;
+		break;
+	default:
+		tvout_err("not supported layer\n");
+		goto err_fb_blank;
+	}
+
+	switch (blank_mode) {
+	case FB_BLANK_UNBLANK:
+		if (fb->fix.smem_start)
+			s5p_mixer_ctrl_enable_layer(layer);
+		else
+			tvout_dbg("[fb%d] no alloc memory for unblank\n",
+				fb->node);
+		break;
+
+	case FB_BLANK_POWERDOWN:
+		s5p_mixer_ctrl_disable_layer(layer);
+		break;
+
+	default:
+		tvout_err("not supported blank mode\n");
+		goto err_fb_blank;
+	}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 1;
+err_fb_blank:
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return -1;
+}
+
+static int s5p_tvout_fb_set_par(struct fb_info *fb)
+{
+	u32 bpp, trans_len;
+	u32 src_x, src_y, w, h;
+	struct s5ptvfb_window *win = fb->par;
+	enum s5p_mixer_layer layer = MIXER_GPR0_LAYER;
+
+	tvout_dbg("[fb%d] set_par\n", win->id);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	if (!fb->fix.smem_start) {
+#ifndef CONFIG_USER_ALLOC_TVOUT
+		printk(KERN_INFO " The frame buffer is allocated here\n");
+		/* s5p_tvout_fb_map_video_memory(win->id);*/
+#else
+		printk(KERN_ERR
+		"[Warning] The frame buffer should be allocated by ioctl\n");
+#endif
+	}
+
+	bpp = fb->var.bits_per_pixel;
+	trans_len = fb->var.transp.length;
+	w = fb->var.xres;
+	h = fb->var.yres;
+	src_x = fb->var.xoffset;
+	src_y = fb->var.yoffset;
+
+	switch (fb->node) {
+	case S5PTV_FB_LAYER0_MINOR:
+		layer = MIXER_GPR0_LAYER;
+		break;
+	case S5PTV_FB_LAYER1_MINOR:
+		layer = MIXER_GPR1_LAYER;
+		break;
+	}
+
+	s5p_mixer_ctrl_init_grp_layer(layer);
+	s5p_mixer_ctrl_set_pixel_format(layer, bpp, trans_len);
+	s5p_mixer_ctrl_set_src_win_pos(layer, src_x, src_y, w, h);
+	s5p_mixer_ctrl_set_alpha_blending(layer, win->alpha.mode,
+				win->alpha.value);
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+}
+
+static int s5p_tvout_fb_check_var(struct fb_var_screeninfo *var,
+					struct fb_info *fb)
+{
+	struct fb_fix_screeninfo *fix = &fb->fix;
+	struct s5ptvfb_window *win = fb->par;
+
+	tvout_dbg("[fb%d] check_var\n", win->id);
+
+	if (var->bits_per_pixel != 16 && var->bits_per_pixel != 24 &&
+		var->bits_per_pixel != 32) {
+		tvout_err("invalid bits per pixel\n");
+		return -1;
+	}
+
+	if (var->xres > lcd.width)
+		var->xres = lcd.width;
+
+	if (var->yres > lcd.height)
+		var->yres = lcd.height;
+
+	if (var->xres_virtual != var->xres)
+		var->xres_virtual = var->xres;
+
+	if (var->yres_virtual > var->yres * (fb->fix.ypanstep + 1))
+		var->yres_virtual = var->yres * (fb->fix.ypanstep + 1);
+
+	if (var->xoffset != 0)
+		var->xoffset = 0;
+
+	if (var->yoffset + var->yres > var->yres_virtual)
+		var->yoffset = var->yres_virtual - var->yres;
+
+	if (win->x + var->xres > lcd.width)
+		win->x = lcd.width - var->xres;
+
+	if (win->y + var->yres > lcd.height)
+		win->y = lcd.height - var->yres;
+
+	/* modify the fix info */
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+	fix->smem_len = fix->line_length * var->yres_virtual;
+
+	s5p_tvout_fb_set_bitfield(var);
+	s5p_tvout_fb_set_alpha_info(var, win);
+
+	return 0;
+}
+
+static int s5p_tvout_fb_release(struct fb_info *fb, int user)
+{
+	struct s5ptvfb_window *win = fb->par;
+
+	atomic_dec(&win->in_use);
+
+	return 0;
+}
+
+static int s5p_tvout_fb_ioctl(struct fb_info *fb, unsigned int cmd,
+			unsigned long arg)
+{
+	dma_addr_t start_addr;
+	enum s5p_mixer_layer layer;
+	struct fb_var_screeninfo *var = &fb->var;
+	struct s5ptvfb_window *win = fb->par;
+	int ret = 0;
+	void *argp = (void *) arg;
+
+	union {
+		struct s5ptvfb_user_window user_window;
+		struct s5ptvfb_user_plane_alpha user_alpha;
+		struct s5ptvfb_user_chroma user_chroma;
+		struct s5ptvfb_user_scaling user_scaling;
+		int vsync;
+	} p;
+
+	tvout_dbg("\n");
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	switch (fb->node) {
+	case S5PTV_FB_LAYER0_MINOR:
+		layer = MIXER_GPR0_LAYER;
+		break;
+	case S5PTV_FB_LAYER1_MINOR:
+		layer = MIXER_GPR1_LAYER;
+		break;
+	default:
+		printk(KERN_ERR "[Error] invalid layer\n");
+		goto err_fb_ioctl;
+	}
+
+	switch (cmd) {
+	case S5PTVFB_WIN_POSITION:
+		if (copy_from_user(&p.user_window,
+			(struct s5ptvfb_user_window __user *) arg,
+			sizeof(p.user_window)))
+			ret = -EFAULT;
+		else {
+			s5p_mixer_ctrl_set_dst_win_pos(layer, p.user_window.x,
+				p.user_window.y, var->xres, var->yres);
+		}
+		break;
+
+	case S5PTVFB_WIN_SET_PLANE_ALPHA:
+		if (copy_from_user(&p.user_alpha,
+			(struct s5ptvfb_user_plane_alpha __user *) arg,
+			sizeof(p.user_alpha)))
+			ret = -EFAULT;
+		else {
+			win->alpha.mode = LAYER_BLENDING;
+			win->alpha.value = p.user_alpha.alpha;
+			s5p_mixer_ctrl_set_alpha_blending(layer,
+				win->alpha.mode, win->alpha.value);
+		}
+		break;
+	case S5PTVFB_WIN_SET_CHROMA:
+		if (copy_from_user(&p.user_chroma,
+			(struct s5ptvfb_user_chroma __user *) arg,
+			sizeof(p.user_chroma)))
+			ret = -EFAULT;
+		else {
+			win->chroma.enabled = p.user_chroma.enabled;
+			win->chroma.key = S5PTVFB_CHROMA(p.user_chroma.red,
+						p.user_chroma.green,
+						p.user_chroma.blue);
+
+			s5p_mixer_ctrl_set_chroma_key(layer, win->chroma);
+		}
+		break;
+	case S5PTVFB_SET_VSYNC_INT:
+		s5p_mixer_ctrl_set_vsync_interrupt((int)argp);
+		break;
+	case S5PTVFB_WAITFORVSYNC:
+		s5p_tvout_fb_wait_for_vsync();
+		break;
+	case S5PTVFB_WIN_SET_ADDR:
+#if defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_UMP_VCM_ALLOC)
+		fb->fix.smem_start = ump_dd_dev_virtual_get_from_secure_id(
+		(unsigned int)argp);
+#else
+		fb->fix.smem_start = (unsigned long)argp;
+#endif
+		start_addr = fb->fix.smem_start + (var->xres_virtual *
+				(var->bits_per_pixel / 8) * var->yoffset);
+
+		s5p_mixer_ctrl_set_buffer_address(layer, start_addr);
+		break;
+	case S5PTVFB_SCALING:
+		if (copy_from_user(&p.user_scaling,
+			(struct s5ptvfb_user_scaling __user *) arg,
+			sizeof(p.user_scaling)))
+			ret = -EFAULT;
+		else
+			s5p_mixer_ctrl_scaling(layer, p.user_scaling);
+		break;
+	}
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+
+	return 0;
+err_fb_ioctl:
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return -1;
+
+}
+
+static int s5p_tvout_fb_open(struct fb_info *fb, int user)
+{
+	struct s5ptvfb_window *win = fb->par;
+	int ret = 0;
+
+	tvout_dbg("\n");
+	mutex_lock(&fb_lock);
+
+	if (atomic_read(&win->in_use)) {
+		tvout_dbg("do not allow multiple open for tvout framebuffer\n");
+		ret = -EBUSY;
+	} else
+		atomic_inc(&win->in_use);
+
+	mutex_unlock(&fb_lock);
+
+	return ret;
+}
+
+struct fb_ops s5ptvfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_check_var = s5p_tvout_fb_check_var,
+	.fb_set_par = s5p_tvout_fb_set_par,
+	.fb_blank = s5p_tvout_fb_blank,
+	.fb_pan_display = s5p_tvout_fb_pan_display,
+	.fb_setcolreg = s5p_tvout_fb_setcolreg,
+	.fb_ioctl = s5p_tvout_fb_ioctl,
+	.fb_open = s5p_tvout_fb_open,
+	.fb_release = s5p_tvout_fb_release,
+};
+
+static int s5p_tvout_fb_init_fbinfo(int id, struct device *dev_fb)
+{
+	struct fb_fix_screeninfo *fix = &fb[FB_INDEX(id)]->fix;
+	struct fb_var_screeninfo *var = &fb[FB_INDEX(id)]->var;
+	struct s5ptvfb_window *win = fb[FB_INDEX(id)]->par;
+	struct s5ptvfb_alpha *alpha = &win->alpha;
+
+	memset(win, 0, sizeof(struct s5ptvfb_window));
+
+	platform_set_drvdata(to_platform_device(dev_fb), fb[FB_INDEX(id)]);
+
+	strcpy(fix->id, S5PTVFB_NAME);
+
+	/* fimd specific */
+	win->id = id;
+	win->path = DATA_PATH_DMA;
+	win->dma_burst = 16;
+	win->dev_fb = dev_fb;
+	alpha->mode = LAYER_BLENDING;
+	alpha->value = 0xff;
+
+	/* fbinfo */
+	fb[FB_INDEX(id)]->fbops = &s5ptvfb_ops;
+	fb[FB_INDEX(id)]->flags = FBINFO_FLAG_DEFAULT;
+	fb[FB_INDEX(id)]->pseudo_palette = &win->pseudo_pal;
+	fix->xpanstep = 0;
+	fix->ypanstep = 0;
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	var->xres = lcd.width;
+	var->yres = lcd.height;
+	var->xres_virtual = var->xres;
+	var->yres_virtual = var->yres + (var->yres * fix->ypanstep);
+	var->bits_per_pixel = 32;
+	var->xoffset = 0;
+	var->yoffset = 0;
+	var->width = 0;
+	var->height = 0;
+	var->transp.length = 0;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+	fix->smem_len = fix->line_length * var->yres_virtual;
+
+	var->nonstd = 0;
+	var->activate = FB_ACTIVATE_NOW;
+	var->vmode = FB_VMODE_NONINTERLACED;
+	var->hsync_len = lcd.timing.h_sw;
+	var->vsync_len = lcd.timing.v_sw;
+	var->left_margin = lcd.timing.h_fp;
+	var->right_margin = lcd.timing.h_bp;
+	var->upper_margin = lcd.timing.v_fp;
+	var->lower_margin = lcd.timing.v_bp;
+
+	var->pixclock = lcd.freq * (var->left_margin + var->right_margin +
+				var->hsync_len + var->xres) *
+				(var->upper_margin + var->lower_margin +
+				var->vsync_len + var->yres);
+
+	tvout_dbg("pixclock: %d\n", var->pixclock);
+
+	s5p_tvout_fb_set_bitfield(var);
+	s5p_tvout_fb_set_alpha_info(var, win);
+
+	mutex_init(&fb_lock);
+
+	return 0;
+}
+
+int s5p_tvout_fb_alloc_framebuffer(struct device *dev_fb)
+{
+	int ret, i;
+
+	/* alloc for each framebuffer */
+	for (i = 0; i < S5PTV_FB_CNT; i++) {
+		fb[i] = framebuffer_alloc(sizeof(struct s5ptvfb_window),
+			dev_fb);
+		if (!fb[i]) {
+			tvout_err("not enough memory\n");
+			ret = -1;
+			goto err_alloc_fb;
+		}
+
+		ret = s5p_tvout_fb_init_fbinfo(i + S5PTV_FB_LAYER0_MINOR,
+						dev_fb);
+		if (ret) {
+			tvout_err("fail to allocate memory for tv fb\n");
+			ret = -1;
+			goto err_alloc_fb;
+		}
+
+#ifndef CONFIG_USER_ALLOC_TVOUT
+#if 0
+		if (s5p_tvout_fb_map_video_memory(i + S5PTV_FB_LAYER0_MINOR)) {
+			tvout_err("fail to map video mem for default window\n");
+			ret = -1;
+			goto err_alloc_fb;
+		}
+#endif
+#endif
+	}
+
+	return 0;
+
+err_alloc_fb:
+	for (i = 0; i < S5PTV_FB_CNT; i++) {
+		if (fb[i])
+			framebuffer_release(fb[i]);
+	}
+
+	return ret;
+}
+
+int s5p_tvout_fb_register_framebuffer(struct device *dev_fb)
+{
+	int ret, j, i = 0;
+
+	do {
+		ret = register_framebuffer(fb[0]);
+		if (ret) {
+			tvout_err("fail to register framebuffer device\n");
+			return -1;
+		}
+	} while (fb[0]->node < S5PTV_FB_LAYER0_MINOR);
+
+	for (i = 1; i < S5PTV_FB_CNT; i++) {
+		ret = register_framebuffer(fb[i]);
+		if (ret) {
+			tvout_err("fail to register framebuffer device\n");
+			ret = -1;
+			goto err;
+		}
+	}
+
+	for (i = 0; i < S5PTV_FB_CNT; i++)
+		tvout_dbg("fb[%d] = %d\n", i, fb[i]->node);
+
+	for (i = 0; i < S5PTV_FB_CNT; i++) {
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+#ifndef CONFIG_USER_ALLOC_TVOUT
+		s5p_tvout_fb_check_var(&fb[i]->var, fb[i]);
+		s5p_tvout_fb_set_par(fb[i]);
+#endif
+#endif
+	}
+
+	return 0;
+
+err:
+	for (j = 0; j < i; j++)
+		unregister_framebuffer(fb[j]);
+	return ret;
+}
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_fb.h b/drivers/media/video/samsung/tvout/s5p_tvout_fb.h
new file mode 100644
index 0000000..9f79bda
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_fb.h
@@ -0,0 +1,21 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_fb.h
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * frame buffer header file. file for Samsung TVOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _LINUX_S5P_TVOUT_FB_H_
+#define _LINUX_S5P_TVOUT_FB_H_
+
+#include <linux/fb.h>
+
+extern int s5p_tvout_fb_alloc_framebuffer(struct device *dev_fb);
+extern int s5p_tvout_fb_register_framebuffer(struct device *dev_fb);
+
+#endif /* _LINUX_S5P_TVOUT_FB_H_ */
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_hpd.c b/drivers/media/video/samsung/tvout/s5p_tvout_hpd.c
new file mode 100644
index 0000000..4f35a91
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_hpd.c
@@ -0,0 +1,672 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_hdmi_hpd.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * HPD interface function file for Samsung TVOut driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/miscdevice.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/poll.h>
+
+#include <plat/tvout.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#ifdef CONFIG_HDMI_SWITCH_HPD
+#include <linux/switch.h>
+#endif
+
+#include "s5p_tvout_common_lib.h"
+#include "hw_if/hw_if.h"
+
+#ifdef CONFIG_TVOUT_DEBUG
+#define HPDIFPRINTK(fmt, args...)					\
+do {									\
+	if (unlikely(tvout_dbg_flag & (1 << DBG_FLAG_HPD))) {		\
+		printk(KERN_INFO "[HPD_IF] %s: " fmt,			\
+			__func__ , ## args);				\
+	}								\
+} while (0)
+#else
+#define HPDIFPRINTK(fmt, args...)
+#endif
+
+#define HPDPRINTK(fmt, args...) \
+	printk(KERN_INFO "[HPD_IF] %s: " fmt, __func__ , ## args)
+
+#define VERSION         "1.2"	/* Driver version number */
+#define HPD_MINOR       243	/* Major 10, Minor 243, /dev/hpd */
+
+#define HPD_LO          0
+#define HPD_HI          1
+
+#define HDMI_ON		1
+#define HDMI_OFF	0
+
+#define RETRY_COUNT	50
+
+struct hpd_struct {
+	spinlock_t lock;
+	wait_queue_head_t waitq;
+	atomic_t state;
+	void (*int_src_hdmi_hpd) (void);
+	void (*int_src_ext_hpd) (void);
+	int (*read_gpio) (void);
+	int irq_n;
+#ifdef CONFIG_HDMI_SWITCH_HPD
+	struct switch_dev hpd_switch;
+#endif
+#ifdef CONFIG_HDMI_CONTROLLED_BY_EXT_IC
+	void (*ext_ic_control) (bool ic_on);
+#endif
+};
+
+static struct hpd_struct hpd_struct;
+
+static int last_hpd_state;
+static int last_uevent_state;
+atomic_t hdmi_status;
+atomic_t poll_state;
+
+static int s5p_hpd_open(struct inode *inode, struct file *file);
+static int s5p_hpd_release(struct inode *inode, struct file *file);
+static ssize_t s5p_hpd_read(struct file *file, char __user *buffer,
+			    size_t count, loff_t *ppos);
+static unsigned int s5p_hpd_poll(struct file *file, poll_table *wait);
+static long s5p_hpd_ioctl(struct file *file,
+			  unsigned int cmd, unsigned long arg);
+
+static const struct file_operations hpd_fops = {
+	.owner = THIS_MODULE,
+	.open = s5p_hpd_open,
+	.release = s5p_hpd_release,
+	.read = s5p_hpd_read,
+	.poll = s5p_hpd_poll,
+	.unlocked_ioctl = s5p_hpd_ioctl,
+};
+
+static struct miscdevice hpd_misc_device = {
+	HPD_MINOR,
+	"HPD",
+	&hpd_fops,
+};
+
+#ifdef CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+	static struct switch_dev g_audio_ch_switch;
+#endif
+
+static void s5p_hpd_kobject_uevent(void)
+{
+	char env_buf[120];
+#ifndef CONFIG_HDMI_SWITCH_HPD
+	char *envp[2];
+	int env_offset = 0;
+#endif
+	int i = 0;
+	int hpd_state = atomic_read(&hpd_struct.state);
+
+	HPDIFPRINTK("++\n");
+	memset(env_buf, 0, sizeof(env_buf));
+
+	if (hpd_state) {
+		while (on_stop_process && (i < RETRY_COUNT)) {
+			HPDIFPRINTK("waiting on_stop_process\n");
+			usleep_range(5000, 5000);
+			i++;
+		};
+	} else {
+		while (on_start_process && (i < RETRY_COUNT)) {
+			HPDIFPRINTK("waiting on_start_process\n");
+			usleep_range(5000, 5000);
+			i++;
+		};
+	}
+
+	if (i == RETRY_COUNT) {
+		on_stop_process = false;
+		on_start_process = false;
+		printk(KERN_ERR	"[ERROR] %s() %s fail !!\n", __func__,
+			hpd_state ? "on_stop_process" : "on_start_process");
+	}
+
+	hpd_state = atomic_read(&hpd_struct.state);
+	if (hpd_state) {
+		if (last_uevent_state == -1 || last_uevent_state == HPD_LO) {
+#ifdef CONFIG_HDMI_CONTROLLED_BY_EXT_IC
+			hpd_struct.ext_ic_control(true);
+			msleep(20);
+#endif
+#ifdef CONFIG_HDMI_SWITCH_HPD
+			hpd_struct.hpd_switch.state = 0;
+			switch_set_state(&hpd_struct.hpd_switch, 1);
+#else
+			sprintf(env_buf, "HDMI_STATE=online");
+			envp[env_offset++] = env_buf;
+			envp[env_offset] = NULL;
+			HPDIFPRINTK("online event\n");
+			kobject_uevent_env(&(hpd_misc_device.this_device->kobj),
+					   KOBJ_CHANGE, envp);
+#endif
+			HPDPRINTK("[HDMI] HPD event -connect!!!\n");
+			on_start_process = true;
+			HPDIFPRINTK("%s() on_start_process(%d)\n",
+				__func__, on_start_process);
+		}
+		last_uevent_state = HPD_HI;
+	} else {
+		if (last_uevent_state == -1 || last_uevent_state == HPD_HI) {
+#ifdef CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+			switch_set_state(&g_audio_ch_switch, (int)-1);
+#endif
+#ifdef CONFIG_HDMI_SWITCH_HPD
+			hpd_struct.hpd_switch.state = 1;
+			switch_set_state(&hpd_struct.hpd_switch, 0);
+#else
+			sprintf(env_buf, "HDMI_STATE=offline");
+			envp[env_offset++] = env_buf;
+			envp[env_offset] = NULL;
+			HPDIFPRINTK("offline event\n");
+			kobject_uevent_env(&(hpd_misc_device.this_device->kobj),
+					   KOBJ_CHANGE, envp);
+#endif
+			HPDPRINTK("[HDMI] HPD event -disconnet!!!\n");
+			on_stop_process = true;
+#ifdef CONFIG_HDMI_CONTROLLED_BY_EXT_IC
+			hpd_struct.ext_ic_control(false);
+#endif
+		}
+		last_uevent_state = HPD_LO;
+	}
+}
+
+static DECLARE_WORK(hpd_work, (void *)s5p_hpd_kobject_uevent);
+
+static int s5p_hpd_open(struct inode *inode, struct file *file)
+{
+	atomic_set(&poll_state, 1);
+
+	return 0;
+}
+
+static int s5p_hpd_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static ssize_t s5p_hpd_read(struct file *file, char __user *buffer,
+			    size_t count, loff_t *ppos)
+{
+	ssize_t retval;
+	unsigned long spin_flags;
+
+	spin_lock_irqsave(&hpd_struct.lock, spin_flags);
+
+	retval = put_user(atomic_read(&hpd_struct.state),
+			  (unsigned int __user *)buffer);
+
+	atomic_set(&poll_state, -1);
+	spin_unlock_irqrestore(&hpd_struct.lock, spin_flags);
+
+	return retval;
+}
+
+static unsigned int s5p_hpd_poll(struct file *file, poll_table * wait)
+{
+	poll_wait(file, &hpd_struct.waitq, wait);
+
+	if (atomic_read(&poll_state) != -1)
+		return POLLIN | POLLRDNORM;
+
+	return 0;
+}
+
+#define HPD_GET_STATE _IOR('H', 100, unsigned int)
+#define AUDIO_CH_SET_STATE _IOR('H', 101, unsigned int)
+
+#ifdef	CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+void hdmi_send_audio_ch_num(
+	int supported_ch_num, struct switch_dev *p_audio_ch_switch)
+{
+	printk(KERN_INFO	"%s() hdmi_send_audio_ch_num :: "
+		"HDMI Audio supported ch = %d",
+		__func__, supported_ch_num);
+	p_audio_ch_switch->state = 0;
+	switch_set_state(p_audio_ch_switch, (int)supported_ch_num);
+}
+#endif
+
+static long s5p_hpd_ioctl(struct file *file,
+			  unsigned int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case HPD_GET_STATE:
+		{
+			unsigned int *status = (unsigned int *)arg;
+			*status = atomic_read(&hpd_struct.state);
+
+			if (last_uevent_state == -1)
+				last_uevent_state = *status;
+
+			if (last_uevent_state != *status) {
+				on_start_process = false;
+				on_stop_process = false;
+				HPDIFPRINTK("%s() on_start_process, "
+					"on_stop_process = false" , __func__);
+			}
+
+			HPDIFPRINTK("HPD status is %s\n",
+				    (*status) ? "plugged" : "unplugged");
+			return 0;
+		}
+#ifdef	CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+	case AUDIO_CH_SET_STATE:
+		{
+			int supported_ch_num;
+			if (copy_from_user(&supported_ch_num,
+				(void __user *)arg, sizeof(supported_ch_num))) {
+				printk(KERN_ERR	"%s() -copy_from_user error\n",
+					__func__);
+				return -EFAULT;
+			}
+
+			printk(KERN_INFO	"%s() - AUDIO_CH_SET_STATE = 0x%x\n",
+				__func__, supported_ch_num);
+			hdmi_send_audio_ch_num(supported_ch_num,
+				&g_audio_ch_switch);
+			return 0;
+		}
+#endif
+	default:
+		printk(KERN_ERR "(%d) unknown ioctl, HPD_GET_STATE(%d)\n",
+		       (unsigned int)cmd, (unsigned int)HPD_GET_STATE);
+		return -EFAULT;
+	}
+
+}
+
+int s5p_hpd_set_hdmiint(void)
+{
+	/* EINT -> HDMI */
+
+	HPDIFPRINTK("\n");
+	irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_NONE);
+
+	if (last_hpd_state)
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 0);
+	else
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 0);
+
+	atomic_set(&hdmi_status, HDMI_ON);
+
+	hpd_struct.int_src_hdmi_hpd();
+
+	s5p_hdmi_reg_hpd_gen();
+
+	if (s5p_hdmi_reg_get_hpd_status())
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 1);
+	else
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 1);
+
+	return 0;
+}
+
+int s5p_hpd_set_eint(void)
+{
+	HPDIFPRINTK("\n");
+	/* HDMI -> EINT */
+	atomic_set(&hdmi_status, HDMI_OFF);
+
+	s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_PLUG);
+	s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_UNPLUG);
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 0);
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 0);
+
+	hpd_struct.int_src_ext_hpd();
+
+	return 0;
+}
+
+int s5p_hpd_get_status(void)
+{
+	int hpd_state = atomic_read(&hpd_struct.state);
+	return hpd_state;
+
+}
+
+static int s5p_hpd_irq_eint(int irq)
+{
+
+	HPDIFPRINTK("\n");
+
+	if (hpd_struct.read_gpio()) {
+		HPDIFPRINTK("gpio is high\n");
+		irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_LEVEL_LOW);
+		if (atomic_read(&hpd_struct.state) == HPD_HI)
+			return IRQ_HANDLED;
+
+		atomic_set(&hpd_struct.state, HPD_HI);
+		atomic_set(&poll_state, 1);
+
+		last_hpd_state = HPD_HI;
+		wake_up_interruptible(&hpd_struct.waitq);
+	} else {
+		HPDIFPRINTK("gpio is low\n");
+		irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_LEVEL_HIGH);
+		if (atomic_read(&hpd_struct.state) == HPD_LO)
+			return IRQ_HANDLED;
+
+		atomic_set(&hpd_struct.state, HPD_LO);
+		atomic_set(&poll_state, 1);
+
+		last_hpd_state = HPD_LO;
+
+		wake_up_interruptible(&hpd_struct.waitq);
+	}
+	schedule_work(&hpd_work);
+
+	HPDIFPRINTK("%s\n", atomic_read(&hpd_struct.state) == HPD_HI ?
+		    "HPD HI" : "HPD LO");
+
+	return IRQ_HANDLED;
+}
+
+static int s5p_hpd_irq_hdmi(int irq)
+{
+	u8 flag;
+	int ret = IRQ_HANDLED;
+	HPDIFPRINTK("\n");
+
+	/* read flag register */
+	flag = s5p_hdmi_reg_intc_status();
+
+	if (s5p_hdmi_reg_get_hpd_status())
+		s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_PLUG);
+	else
+		s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_UNPLUG);
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 0);
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 0);
+
+	/* is this our interrupt? */
+	if (!(flag & (1 << HDMI_IRQ_HPD_PLUG | 1 << HDMI_IRQ_HPD_UNPLUG))) {
+		printk(KERN_WARNING "%s() flag is wrong : 0x%x\n",
+		       __func__, flag);
+		ret = IRQ_NONE;
+
+		goto out;
+	}
+
+	if (flag == (1 << HDMI_IRQ_HPD_PLUG | 1 << HDMI_IRQ_HPD_UNPLUG)) {
+		HPDIFPRINTK("HPD_HI && HPD_LO\n");
+
+		if (last_hpd_state == HPD_HI && s5p_hdmi_reg_get_hpd_status())
+			flag = 1 << HDMI_IRQ_HPD_UNPLUG;
+		else
+			flag = 1 << HDMI_IRQ_HPD_PLUG;
+	}
+
+	if (flag & (1 << HDMI_IRQ_HPD_PLUG)) {
+		HPDIFPRINTK("HPD_HI\n");
+
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 1);
+		if (atomic_read(&hpd_struct.state) == HPD_HI)
+			return IRQ_HANDLED;
+
+		atomic_set(&hpd_struct.state, HPD_HI);
+		atomic_set(&poll_state, 1);
+
+		last_hpd_state = HPD_HI;
+		wake_up_interruptible(&hpd_struct.waitq);
+
+	} else if (flag & (1 << HDMI_IRQ_HPD_UNPLUG)) {
+		HPDIFPRINTK("HPD_LO\n");
+
+		s5p_hdcp_stop();
+
+		s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 1);
+		if (atomic_read(&hpd_struct.state) == HPD_LO)
+			return IRQ_HANDLED;
+
+		atomic_set(&hpd_struct.state, HPD_LO);
+		atomic_set(&poll_state, 1);
+
+		last_hpd_state = HPD_LO;
+
+		wake_up_interruptible(&hpd_struct.waitq);
+	}
+
+	schedule_work(&hpd_work);
+
+ out:
+	return IRQ_HANDLED;
+}
+
+/*
+ * HPD interrupt handler
+ *
+ * Handles interrupt requests from HPD hardware.
+ * Handler changes value of internal variable and notifies waiting thread.
+ */
+static irqreturn_t s5p_hpd_irq_handler(int irq, void *dev_id)
+{
+	irqreturn_t ret = IRQ_HANDLED;
+
+	/* check HDMI status */
+	if (atomic_read(&hdmi_status)) {
+		/* HDMI on */
+		HPDIFPRINTK("HDMI HPD interrupt\n");
+		ret = s5p_hpd_irq_hdmi(irq);
+		HPDIFPRINTK("HDMI HPD interrupt - end\n");
+	} else {
+		/* HDMI off */
+		HPDIFPRINTK("EINT HPD interrupt\n");
+		ret = s5p_hpd_irq_eint(irq);
+		HPDIFPRINTK("EINT HPD interrupt - end\n");
+	}
+
+	return ret;
+}
+
+#ifdef	CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+static irqreturn_t s5p_hpd_irq_default_handler(int irq, void *dev_id)
+{
+	u8 flag;
+
+	flag = s5p_hdmi_reg_intc_status();
+
+	if (s5p_hdmi_reg_get_hpd_status())
+		s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_PLUG);
+	else
+		s5p_hdmi_reg_intc_clear_pending(HDMI_IRQ_HPD_UNPLUG);
+
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_UNPLUG, 0);
+	s5p_hdmi_reg_intc_enable(HDMI_IRQ_HPD_PLUG, 0);
+
+	if (flag & (1 << HDMI_IRQ_HPD_PLUG))
+		HPDIFPRINTK("HPD_HI\n");
+	else if (flag & (1 << HDMI_IRQ_HPD_UNPLUG))
+		HPDIFPRINTK("HPD_LO\n");
+	else
+		HPDIFPRINTK("UNKNOWN EVENT\n");
+
+	return IRQ_HANDLED;
+}
+
+void mhl_hpd_handler(bool onoff)
+{
+	static int old_state;
+
+	if (old_state == onoff) {
+		printk(KERN_INFO	"%s() state is aready %s\n",
+			__func__, onoff ? "on" : "off");
+		return;
+	} else {
+		printk(KERN_INFO	"%s(%d), old_state(%d)\n",
+			__func__, onoff, old_state);
+		old_state = onoff;
+	}
+
+	if (onoff == true) {
+		enable_irq(hpd_struct.irq_n);
+		s5p_hdmi_reg_intc_set_isr(s5p_hpd_irq_handler,
+					  (u8) HDMI_IRQ_HPD_PLUG);
+	} else {
+		disable_irq_nosync(hpd_struct.irq_n);
+		s5p_hdmi_reg_intc_set_isr(s5p_hpd_irq_default_handler,
+					  (u8) HDMI_IRQ_HPD_PLUG);
+	}
+}
+EXPORT_SYMBOL(mhl_hpd_handler);
+#endif
+
+static int __devinit s5p_hpd_probe(struct platform_device *pdev)
+{
+	struct s5p_platform_hpd *pdata;
+	int ret;
+
+	if (misc_register(&hpd_misc_device)) {
+		printk(KERN_WARNING " Couldn't register device 10, %d.\n",
+		       HPD_MINOR);
+
+		return -EBUSY;
+	}
+
+	init_waitqueue_head(&hpd_struct.waitq);
+
+	spin_lock_init(&hpd_struct.lock);
+
+	atomic_set(&hpd_struct.state, -1);
+
+	atomic_set(&hdmi_status, HDMI_OFF);
+
+	pdata = to_tvout_plat(&pdev->dev);
+
+	if (pdata->int_src_hdmi_hpd)
+		hpd_struct.int_src_hdmi_hpd =
+		    (void (*)(void))pdata->int_src_hdmi_hpd;
+	if (pdata->int_src_ext_hpd)
+		hpd_struct.int_src_ext_hpd =
+		    (void (*)(void))pdata->int_src_ext_hpd;
+	if (pdata->read_gpio)
+		hpd_struct.read_gpio = (int (*)(void))pdata->read_gpio;
+#ifdef CONFIG_HDMI_CONTROLLED_BY_EXT_IC
+	if (pdata->ext_ic_control)
+		hpd_struct.ext_ic_control = pdata->ext_ic_control;
+#endif
+	hpd_struct.irq_n = platform_get_irq(pdev, 0);
+
+	hpd_struct.int_src_ext_hpd();
+	if (hpd_struct.read_gpio()) {
+		atomic_set(&hpd_struct.state, HPD_HI);
+		last_hpd_state = HPD_HI;
+	} else {
+		atomic_set(&hpd_struct.state, HPD_LO);
+		last_hpd_state = HPD_LO;
+	}
+
+#ifdef CONFIG_HDMI_SWITCH_HPD
+	hpd_struct.hpd_switch.name = "hdmi";
+	switch_dev_register(&hpd_struct.hpd_switch);
+#endif
+	irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_EDGE_BOTH);
+
+	ret = request_irq(hpd_struct.irq_n, (irq_handler_t) s5p_hpd_irq_handler,
+			  IRQF_DISABLED, "hpd", (void *)(&pdev->dev));
+
+	if (ret) {
+		printk(KERN_ERR "failed to install hpd irq\n");
+		misc_deregister(&hpd_misc_device);
+		return -EIO;
+	}
+#ifdef	CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
+	disable_irq(hpd_struct.irq_n);
+#endif
+
+	s5p_hdmi_reg_intc_set_isr(s5p_hpd_irq_handler, (u8) HDMI_IRQ_HPD_PLUG);
+	s5p_hdmi_reg_intc_set_isr(s5p_hpd_irq_handler,
+				  (u8) HDMI_IRQ_HPD_UNPLUG);
+
+	last_uevent_state = -1;
+
+#ifdef CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+	g_audio_ch_switch.name = "ch_hdmi_audio";
+	switch_dev_register(&g_audio_ch_switch);
+#endif
+	return 0;
+}
+
+static int __devexit s5p_hpd_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_HDMI_SWITCH_HPD
+	switch_dev_unregister(&hpd_struct.hpd_switch);
+#endif
+#ifdef CONFIG_LSI_HDMI_AUDIO_CH_EVENT
+	switch_dev_unregister(&g_audio_ch_switch);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_hpd_suspend(struct platform_device *dev, pm_message_t state)
+{
+	hpd_struct.int_src_ext_hpd();
+	return 0;
+}
+
+static int s5p_hpd_resume(struct platform_device *dev)
+{
+	if (atomic_read(&hdmi_status) == HDMI_ON)
+		hpd_struct.int_src_hdmi_hpd();
+
+	return 0;
+}
+#else
+#define s5p_hpd_suspend NULL
+#define s5p_hpd_resume NULL
+#endif
+
+static struct platform_driver s5p_hpd_driver = {
+	.probe = s5p_hpd_probe,
+	.remove = __devexit_p(s5p_hpd_remove),
+	.suspend = s5p_hpd_suspend,
+	.resume = s5p_hpd_resume,
+	.driver = {
+		   .name = "s5p-tvout-hpd",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static char banner[] __initdata =
+	"S5P HPD Driver, (c) 2009 Samsung Electronics\n";
+
+static int __init s5p_hpd_init(void)
+{
+	int ret;
+
+	printk(banner);
+
+	ret = platform_driver_register(&s5p_hpd_driver);
+
+	if (ret) {
+		printk(KERN_ERR "Platform Device Register Failed %d\n", ret);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+static void __exit s5p_hpd_exit(void)
+{
+	misc_deregister(&hpd_misc_device);
+}
+
+module_init(s5p_hpd_init);
+module_exit(s5p_hpd_exit);
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.c b/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.c
new file mode 100644
index 0000000..7af8a15
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.c
@@ -0,0 +1,1427 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * V4L2 API file for Samsung TVOOUT driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/version.h>
+#include <linux/slab.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+
+#include <linux/videodev2_exynos_camera.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+
+#include "s5p_tvout_common_lib.h"
+#include "s5p_tvout_ctrl.h"
+#include "s5p_tvout_v4l2.h"
+
+#if defined(CONFIG_S5P_SYSMMU_TV)
+#include <plat/sysmmu.h>
+#endif
+
+#ifdef CONFIG_UMP_VCM_ALLOC
+#include "ump_kernel_interface.h"
+#endif
+
+#ifdef CONFIG_VCM
+#include <plat/s5p-vcm.h>
+#endif
+
+#define MAJOR_VERSION	0
+#define MINOR_VERSION	3
+#define RELEASE_VERSION	0
+
+#if defined(CONFIG_S5P_SYSMMU_TV)
+#ifdef CONFIG_S5P_VMEM
+/* temporary used for testing system mmu */
+extern void *s5p_getaddress(unsigned int cookie);
+#endif
+#endif
+
+extern struct s5p_tvout_vp_bufferinfo s5ptv_vp_buff;
+
+#define V4L2_STD_ALL_HD				((v4l2_std_id)0xffffffff)
+
+#ifdef CONFIG_CPU_EXYNOS4210
+#define S5P_TVOUT_TVIF_MINOR			14
+#define S5P_TVOUT_VO_MINOR			21
+#else
+#define S5P_TVOUT_TVIF_MINOR			16
+#define S5P_TVOUT_VO_MINOR			20
+#endif
+
+#define V4L2_OUTPUT_TYPE_COMPOSITE		5
+#define V4L2_OUTPUT_TYPE_HDMI			10
+#define V4L2_OUTPUT_TYPE_HDMI_RGB		11
+#define V4L2_OUTPUT_TYPE_DVI			12
+
+#define V4L2_STD_PAL_BDGHI	(V4L2_STD_PAL_B|\
+				V4L2_STD_PAL_D|	\
+				V4L2_STD_PAL_G|	\
+				V4L2_STD_PAL_H|	\
+				V4L2_STD_PAL_I)
+
+#define V4L2_STD_480P_60_16_9	((v4l2_std_id)0x04000000)
+#define V4L2_STD_480P_60_4_3	((v4l2_std_id)0x05000000)
+#define V4L2_STD_576P_50_16_9	((v4l2_std_id)0x06000000)
+#define V4L2_STD_576P_50_4_3	((v4l2_std_id)0x07000000)
+#define V4L2_STD_720P_60	((v4l2_std_id)0x08000000)
+#define V4L2_STD_720P_50	((v4l2_std_id)0x09000000)
+#define V4L2_STD_1080P_60	((v4l2_std_id)0x0a000000)
+#define V4L2_STD_1080P_50	((v4l2_std_id)0x0b000000)
+#define V4L2_STD_1080I_60	((v4l2_std_id)0x0c000000)
+#define V4L2_STD_1080I_50	((v4l2_std_id)0x0d000000)
+#define V4L2_STD_480P_59	((v4l2_std_id)0x0e000000)
+#define V4L2_STD_720P_59	((v4l2_std_id)0x0f000000)
+#define V4L2_STD_1080I_59	((v4l2_std_id)0x10000000)
+#define V4L2_STD_1080P_59	((v4l2_std_id)0x11000000)
+#define V4L2_STD_1080P_30	((v4l2_std_id)0x12000000)
+
+#ifdef	CONFIG_HDMI_14A_3D
+#define V4L2_STD_TVOUT_720P_60_SBS_HALF	((v4l2_std_id)0x13000000)
+#define V4L2_STD_TVOUT_720P_59_SBS_HALF	((v4l2_std_id)0x14000000)
+#define V4L2_STD_TVOUT_720P_50_TB	((v4l2_std_id)0x15000000)
+#define V4L2_STD_TVOUT_1080P_24_TB	((v4l2_std_id)0x16000000)
+#define V4L2_STD_TVOUT_1080P_23_TB	((v4l2_std_id)0x17000000)
+#endif
+
+#define CVBS_S_VIDEO (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP| \
+	V4L2_STD_PAL | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
+	V4L2_STD_PAL_60 | V4L2_STD_NTSC_443)
+
+struct v4l2_vid_overlay_src {
+	void			*base_y;
+	void			*base_c;
+	struct v4l2_pix_format	pix_fmt;
+};
+
+static const struct v4l2_output s5p_tvout_tvif_output[] = {
+	{
+		.index		= 0,
+		.name		= "Analog  COMPOSITE",
+		.type		= V4L2_OUTPUT_TYPE_COMPOSITE,
+		.audioset	= 0,
+		.modulator	= 0,
+		.std		= CVBS_S_VIDEO,
+	}, {
+		.index		= 1,
+		.name		= "Digital HDMI(YCbCr)",
+		.type		= V4L2_OUTPUT_TYPE_HDMI,
+		.audioset	= 2,
+		.modulator	= 0,
+		.std		= V4L2_STD_480P_60_16_9 |
+				V4L2_STD_480P_60_16_9 | V4L2_STD_720P_60 |
+				V4L2_STD_720P_50
+				| V4L2_STD_1080P_60 | V4L2_STD_1080P_50 |
+				V4L2_STD_1080I_60 | V4L2_STD_1080I_50 |
+				V4L2_STD_480P_59 | V4L2_STD_720P_59 |
+				V4L2_STD_1080I_59 | V4L2_STD_1080P_59 |
+				V4L2_STD_1080P_30,
+	}, {
+		.index		= 2,
+		.name		= "Digital HDMI(RGB)",
+		.type		= V4L2_OUTPUT_TYPE_HDMI_RGB,
+		.audioset	= 2,
+		.modulator	= 0,
+		.std		= V4L2_STD_480P_60_16_9 |
+				V4L2_STD_480P_60_16_9 |
+				V4L2_STD_720P_60 | V4L2_STD_720P_50
+				| V4L2_STD_1080P_60 | V4L2_STD_1080P_50 |
+				V4L2_STD_1080I_60 | V4L2_STD_1080I_50 |
+				V4L2_STD_480P_59 | V4L2_STD_720P_59 |
+				V4L2_STD_1080I_59 | V4L2_STD_1080P_59 |
+				V4L2_STD_1080P_30,
+	}, {
+		.index		= 3,
+		.name		= "Digital DVI",
+		.type		= V4L2_OUTPUT_TYPE_DVI,
+		.audioset	= 2,
+		.modulator	= 0,
+		.std		= V4L2_STD_480P_60_16_9 |
+				V4L2_STD_480P_60_16_9 |
+				V4L2_STD_720P_60 | V4L2_STD_720P_50
+				| V4L2_STD_1080P_60 | V4L2_STD_1080P_50 |
+				V4L2_STD_1080I_60 | V4L2_STD_1080I_50 |
+				V4L2_STD_480P_59 | V4L2_STD_720P_59 |
+				V4L2_STD_1080I_59 | V4L2_STD_1080P_59 |
+				V4L2_STD_1080P_30,
+	}
+
+};
+
+#define S5P_TVOUT_TVIF_NO_OF_OUTPUT ARRAY_SIZE(s5p_tvout_tvif_output)
+
+static const struct v4l2_standard s5p_tvout_tvif_standard[] = {
+	{
+		.index	= 0,
+		.id	= V4L2_STD_NTSC_M,
+		.name	= "NTSC_M",
+	}, {
+		.index	= 1,
+		.id	= V4L2_STD_PAL_BDGHI,
+		.name	= "PAL_BDGHI",
+	}, {
+		.index	= 2,
+		.id	= V4L2_STD_PAL_M,
+		.name	= "PAL_M",
+	}, {
+		.index	= 3,
+		.id	= V4L2_STD_PAL_N,
+		.name	= "PAL_N",
+	}, {
+		.index	= 4,
+		.id	= V4L2_STD_PAL_Nc,
+		.name	= "PAL_Nc",
+	}, {
+		.index	= 5,
+		.id	= V4L2_STD_PAL_60,
+		.name	= "PAL_60",
+	}, {
+		.index	= 6,
+		.id	= V4L2_STD_NTSC_443,
+		.name	= "NTSC_443",
+	}, {
+		.index	= 7,
+		.id	= V4L2_STD_480P_60_16_9,
+		.name	= "480P_60_16_9",
+	}, {
+		.index	= 8,
+		.id	= V4L2_STD_480P_60_4_3,
+		.name	= "480P_60_4_3",
+	}, {
+		.index	= 9,
+		.id	= V4L2_STD_576P_50_16_9,
+		.name	= "576P_50_16_9",
+	}, {
+		.index	= 10,
+		.id	= V4L2_STD_576P_50_4_3,
+		.name	= "576P_50_4_3",
+	}, {
+		.index	= 11,
+		.id	= V4L2_STD_720P_60,
+		.name	= "720P_60",
+	}, {
+		.index	= 12,
+		.id	= V4L2_STD_720P_50,
+		.name	= "720P_50",
+	}, {
+		.index	= 13,
+		.id	= V4L2_STD_1080P_60,
+		.name	= "1080P_60",
+	}, {
+		.index	= 14,
+		.id	= V4L2_STD_1080P_50,
+		.name	= "1080P_50",
+	}, {
+		.index	= 15,
+		.id	= V4L2_STD_1080I_60,
+		.name	= "1080I_60",
+	}, {
+		.index	= 16,
+		.id	= V4L2_STD_1080I_50,
+		.name	= "1080I_50",
+	}, {
+		.index	= 17,
+		.id	= V4L2_STD_480P_59,
+		.name	= "480P_59",
+	}, {
+		.index	= 18,
+		.id	= V4L2_STD_720P_59,
+		.name	= "720P_59",
+	}, {
+		.index	= 19,
+		.id	= V4L2_STD_1080I_59,
+		.name	= "1080I_59",
+	}, {
+		.index	= 20,
+		.id	= V4L2_STD_1080P_59,
+		.name	= "1080I_50",
+	}, {
+		.index	= 21,
+		.id	= V4L2_STD_1080P_30,
+		.name	= "1080I_30",
+	},
+#ifdef CONFIG_HDMI_14A_3D
+	{
+		.index	= 22,
+		.id	= V4L2_STD_TVOUT_720P_60_SBS_HALF,
+		.name	= "720P_60_SBS_HALF",
+	},
+	{
+		.index	= 23,
+		.id	= V4L2_STD_TVOUT_720P_59_SBS_HALF,
+		.name	= "720P_59_SBS_HALF",
+	},
+	{
+		.index	= 24,
+		.id	= V4L2_STD_TVOUT_720P_50_TB,
+		.name	= "720P_50_TB",
+	},
+	{
+		.index	= 25,
+		.id	= V4L2_STD_TVOUT_1080P_24_TB,
+		.name	= "1080P_24_TB",
+	},
+	{
+		.index	= 26,
+		.id	= V4L2_STD_TVOUT_1080P_23_TB,
+		.name	= "1080P_23_TB",
+	},
+#endif
+};
+
+#define S5P_TVOUT_TVIF_NO_OF_STANDARD ARRAY_SIZE(s5p_tvout_tvif_standard)
+
+
+static const struct v4l2_fmtdesc s5p_tvout_vo_fmt_desc[] = {
+	{
+		.index		= 0,
+		.type		= V4L2_BUF_TYPE_PRIVATE,
+		.pixelformat	= V4L2_PIX_FMT_NV12,
+		.description	= "NV12 (Linear YUV420 2 Planes)",
+	}, {
+		.index		= 1,
+		.type		= V4L2_BUF_TYPE_PRIVATE,
+		.pixelformat	= V4L2_PIX_FMT_NV12T,
+		.description	= "NV12T (Tiled YUV420 2 Planes)",
+	},
+/* This block will be used on EXYNOS4210 */
+	{
+		.index		= 2,
+		.type		= V4L2_BUF_TYPE_PRIVATE,
+		.pixelformat	= V4L2_PIX_FMT_NV21,
+		.description	= "NV21 (Linear YUV420 2 Planes)",
+	}, {
+		.index		= 3,
+		.type		= V4L2_BUF_TYPE_PRIVATE,
+		.pixelformat	= V4L2_PIX_FMT_NV21T,
+		.description	= "NV21T (Tiled YUV420 2 Planes)",
+	},
+
+
+};
+
+
+static DEFINE_MUTEX(s5p_tvout_tvif_mutex);
+static DEFINE_MUTEX(s5p_tvout_vo_mutex);
+
+struct s5p_tvout_v4l2_private_data {
+	struct v4l2_vid_overlay_src	vo_src_fmt;
+	struct v4l2_rect		vo_src_rect;
+	struct v4l2_window		vo_dst_fmt;
+	struct v4l2_framebuffer		vo_dst_plane;
+
+	int				tvif_output_index;
+	v4l2_std_id			tvif_standard_id;
+
+	atomic_t			tvif_use;
+	atomic_t			vo_use;
+};
+
+static struct s5p_tvout_v4l2_private_data s5p_tvout_v4l2_private = {
+	.tvif_output_index	= -1,
+	.tvif_standard_id	= 0,
+
+	.tvif_use		= ATOMIC_INIT(0),
+	.vo_use			= ATOMIC_INIT(0),
+};
+
+static void s5p_tvout_v4l2_init_private(void)
+{
+}
+
+static int s5p_tvout_tvif_querycap(
+		struct file *file, void *fh, struct v4l2_capability *cap)
+{
+	strcpy(cap->driver, "s5p-tvout-tvif");
+	strcpy(cap->card, "Samsung TVOUT TV Interface");
+	cap->capabilities = V4L2_CAP_VIDEO_OUTPUT;
+	cap->version = KERNEL_VERSION(
+			MAJOR_VERSION, MINOR_VERSION, RELEASE_VERSION);
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_g_std(
+		struct file *file, void *fh, v4l2_std_id *norm)
+{
+	if (s5p_tvout_v4l2_private.tvif_standard_id == 0) {
+		tvout_err("Standard has not set\n");
+		return -1;
+	}
+
+	*norm = s5p_tvout_v4l2_private.tvif_standard_id;
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_s_std(
+		struct file *file, void *fh, v4l2_std_id *norm)
+{
+	int i;
+	v4l2_std_id std_id = *norm;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	for (i = 0; i < S5P_TVOUT_TVIF_NO_OF_STANDARD; i++) {
+		if (s5p_tvout_tvif_standard[i].id == std_id)
+			break;
+	}
+
+	if (i == S5P_TVOUT_TVIF_NO_OF_STANDARD) {
+		tvout_err("There is no TV standard(0x%08Lx)\n", std_id);
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		s5p_tvout_mutex_unlock();
+#endif
+		return -EINVAL;
+	}
+
+	s5p_tvout_v4l2_private.tvif_standard_id = std_id;
+
+	tvout_dbg("standard id=0x%X, name=\"%s\"\n",
+			(u32) std_id, s5p_tvout_tvif_standard[i].name);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_enum_output(
+		struct file *file, void *fh, struct v4l2_output *a)
+{
+	unsigned int index = a->index;
+
+	if (index >= S5P_TVOUT_TVIF_NO_OF_OUTPUT) {
+		tvout_err("Invalid index(%d)\n", index);
+
+		return -EINVAL;
+	}
+
+	memcpy(a, &s5p_tvout_tvif_output[index], sizeof(struct v4l2_output));
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_g_output(
+		struct file *file, void *fh, unsigned int *i)
+{
+	if (s5p_tvout_v4l2_private.tvif_output_index == -1) {
+		tvout_err("Output has not set\n");
+		return -EINVAL;
+	}
+
+	*i = s5p_tvout_v4l2_private.tvif_output_index;
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_s_output(
+		struct file *file, void *fh, unsigned int i)
+{
+	enum s5p_tvout_disp_mode	tv_std;
+	enum s5p_tvout_o_mode		tv_if;
+
+	if (i >= S5P_TVOUT_TVIF_NO_OF_OUTPUT) {
+		tvout_err("Invalid index(%d)\n", i);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	on_start_process = true;
+	s5p_tvout_v4l2_private.tvif_output_index = i;
+
+	tvout_dbg("output id=%d, name=\"%s\"\n",
+			(int) i, s5p_tvout_tvif_output[i].name);
+
+	switch (s5p_tvout_tvif_output[i].type) {
+	case V4L2_OUTPUT_TYPE_COMPOSITE:
+		tv_if =	TVOUT_COMPOSITE;
+		break;
+
+	case V4L2_OUTPUT_TYPE_HDMI:
+		tv_if =	TVOUT_HDMI;
+		break;
+
+	case V4L2_OUTPUT_TYPE_HDMI_RGB:
+		tv_if =	TVOUT_HDMI_RGB;
+		break;
+
+	case V4L2_OUTPUT_TYPE_DVI:
+		tv_if =	TVOUT_DVI;
+		break;
+
+	default:
+		tvout_err("Invalid output type(%d)\n",
+			s5p_tvout_tvif_output[i].type);
+		goto error_on_tvif_s_output;
+	}
+
+	switch (s5p_tvout_v4l2_private.tvif_standard_id) {
+	case V4L2_STD_NTSC_M:
+		tv_std = TVOUT_NTSC_M;
+		break;
+
+	case V4L2_STD_PAL_BDGHI:
+		tv_std = TVOUT_PAL_BDGHI;
+		break;
+
+	case V4L2_STD_PAL_M:
+		tv_std = TVOUT_PAL_M;
+		break;
+
+	case V4L2_STD_PAL_N:
+		tv_std = TVOUT_PAL_N;
+		break;
+
+	case V4L2_STD_PAL_Nc:
+		tv_std = TVOUT_PAL_NC;
+		break;
+
+	case V4L2_STD_PAL_60:
+		tv_std = TVOUT_PAL_60;
+		break;
+
+	case V4L2_STD_NTSC_443:
+		tv_std = TVOUT_NTSC_443;
+		break;
+
+	case V4L2_STD_480P_60_16_9:
+		tv_std = TVOUT_480P_60_16_9;
+		break;
+
+	case V4L2_STD_480P_60_4_3:
+		tv_std = TVOUT_480P_60_4_3;
+		break;
+
+	case V4L2_STD_480P_59:
+		tv_std = TVOUT_480P_59;
+		break;
+	case V4L2_STD_576P_50_16_9:
+		tv_std = TVOUT_576P_50_16_9;
+		break;
+
+	case V4L2_STD_576P_50_4_3:
+		tv_std = TVOUT_576P_50_4_3;
+		break;
+
+	case V4L2_STD_720P_60:
+		tv_std = TVOUT_720P_60;
+		break;
+
+	case V4L2_STD_720P_59:
+		tv_std = TVOUT_720P_59;
+		break;
+
+	case V4L2_STD_720P_50:
+		tv_std = TVOUT_720P_50;
+		break;
+
+	case V4L2_STD_1080I_60:
+		tv_std = TVOUT_1080I_60;
+		break;
+
+	case V4L2_STD_1080I_59:
+		tv_std = TVOUT_1080I_59;
+		break;
+
+	case V4L2_STD_1080I_50:
+		tv_std = TVOUT_1080I_50;
+		break;
+
+	case V4L2_STD_1080P_30:
+		tv_std = TVOUT_1080P_30;
+		break;
+
+	case V4L2_STD_1080P_60:
+		tv_std = TVOUT_1080P_60;
+		break;
+
+	case V4L2_STD_1080P_59:
+		tv_std = TVOUT_1080P_59;
+		break;
+
+	case V4L2_STD_1080P_50:
+		tv_std = TVOUT_1080P_50;
+		break;
+
+#ifdef CONFIG_HDMI_14A_3D
+	case V4L2_STD_TVOUT_720P_60_SBS_HALF:
+		tv_std = TVOUT_720P_60_SBS_HALF;
+		break;
+	case V4L2_STD_TVOUT_720P_59_SBS_HALF:
+		tv_std = TVOUT_720P_59_SBS_HALF;
+		break;
+	case V4L2_STD_TVOUT_720P_50_TB:
+		tv_std = TVOUT_720P_50_TB;
+		break;
+	case V4L2_STD_TVOUT_1080P_24_TB:
+		tv_std = TVOUT_1080P_24_TB;
+		break;
+	case V4L2_STD_TVOUT_1080P_23_TB:
+		tv_std = TVOUT_1080P_23_TB;
+		break;
+#endif
+	default:
+		tvout_err("Invalid standard id(0x%08Lx)\n",
+			s5p_tvout_v4l2_private.tvif_standard_id);
+		goto error_on_tvif_s_output;
+	}
+
+	s5p_tvif_ctrl_start(tv_std, tv_if);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+error_on_tvif_s_output:
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return -1;
+};
+
+static int s5p_tvout_tvif_cropcap(
+		struct file *file, void *fh, struct v4l2_cropcap *a)
+{
+	enum s5p_tvout_disp_mode std;
+	enum s5p_tvout_o_mode inf;
+
+	struct v4l2_cropcap *cropcap = a;
+
+	if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		tvout_err("Invalid buf type(%d)\n", cropcap->type);
+		return -EINVAL;
+	}
+
+	/* below part will be modified and moved to tvif ctrl class */
+	s5p_tvif_ctrl_get_std_if(&std, &inf);
+
+	switch (std) {
+	case TVOUT_NTSC_M:
+	case TVOUT_NTSC_443:
+	case TVOUT_480P_60_16_9:
+	case TVOUT_480P_60_4_3:
+	case TVOUT_480P_59:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 720;
+		cropcap->bounds.height = 480;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 720;
+		cropcap->defrect.height = 480;
+		break;
+
+	case TVOUT_PAL_M:
+	case TVOUT_PAL_BDGHI:
+	case TVOUT_PAL_N:
+	case TVOUT_PAL_NC:
+	case TVOUT_PAL_60:
+	case TVOUT_576P_50_16_9:
+	case TVOUT_576P_50_4_3:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 720;
+		cropcap->bounds.height = 576;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 720;
+		cropcap->defrect.height = 576;
+		break;
+
+	case TVOUT_720P_60:
+	case TVOUT_720P_59:
+	case TVOUT_720P_50:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 1280;
+		cropcap->bounds.height = 720;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 1280;
+		cropcap->defrect.height = 720;
+		break;
+
+	case TVOUT_1080I_60:
+	case TVOUT_1080I_59:
+	case TVOUT_1080I_50:
+	case TVOUT_1080P_60:
+	case TVOUT_1080P_59:
+	case TVOUT_1080P_50:
+	case TVOUT_1080P_30:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 1920;
+		cropcap->bounds.height = 1080;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 1920;
+		cropcap->defrect.height = 1080;
+		break;
+
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_720P_60_SBS_HALF:
+	case TVOUT_720P_59_SBS_HALF:
+	case TVOUT_720P_50_TB:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 1280;
+		cropcap->bounds.height = 720;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 1280;
+		cropcap->defrect.height = 720;
+		break;
+
+	case TVOUT_1080P_24_TB:
+	case TVOUT_1080P_23_TB:
+		cropcap->bounds.top = 0;
+		cropcap->bounds.left = 0;
+		cropcap->bounds.width = 1920;
+		cropcap->bounds.height = 1080;
+
+		cropcap->defrect.top = 0;
+		cropcap->defrect.left = 0;
+		cropcap->defrect.width = 1920;
+		cropcap->defrect.height = 1080;
+		break;
+#endif
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_wait_for_vsync(void)
+{
+	sleep_on_timeout(&s5ptv_wq, HZ / 10);
+
+	return 0;
+}
+
+const struct v4l2_ioctl_ops s5p_tvout_tvif_ioctl_ops = {
+	.vidioc_querycap	= s5p_tvout_tvif_querycap,
+	.vidioc_g_std		= s5p_tvout_tvif_g_std,
+	.vidioc_s_std		= s5p_tvout_tvif_s_std,
+	.vidioc_enum_output	= s5p_tvout_tvif_enum_output,
+	.vidioc_g_output	= s5p_tvout_tvif_g_output,
+	.vidioc_s_output	= s5p_tvout_tvif_s_output,
+	.vidioc_cropcap		= s5p_tvout_tvif_cropcap,
+};
+
+#define VIDIOC_HDCP_ENABLE		_IOWR('V', 100, unsigned int)
+#define VIDIOC_HDCP_STATUS		_IOR('V', 101, unsigned int)
+#define VIDIOC_HDCP_PROT_STATUS		_IOR('V', 102, unsigned int)
+#define VIDIOC_INIT_AUDIO		_IOR('V', 103, unsigned int)
+#define VIDIOC_AV_MUTE			_IOR('V', 104, unsigned int)
+#define VIDIOC_G_AVMUTE			_IOR('V', 105, unsigned int)
+#define VIDIOC_SET_VSYNC_INT		_IOR('V', 106, unsigned int)
+#define VIDIOC_WAITFORVSYNC		_IOR('V', 107, unsigned int)
+#define VIDIOC_G_VP_BUFF_INFO		_IOR('V', 108, unsigned int)
+#define VIDIOC_S_VP_BUFF_INFO		_IOR('V', 109, unsigned int)
+#define VIDIOC_S_AUDIO_CHANNEL		_IOR('V', 110, unsigned int)
+#define VIDIOC_S_Q_COLOR_RANGE		_IOR('V', 111, unsigned int)
+
+long s5p_tvout_tvif_ioctl(
+		struct file *file, unsigned int cmd, unsigned long arg)
+{
+	long ret = 0;
+	void *argp = (void *) arg;
+	int i = 0;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+
+	tvout_dbg("\n");
+
+	switch (cmd) {
+	case VIDIOC_INIT_AUDIO:
+		tvout_dbg("VIDIOC_INIT_AUDIO(%d)\n", (int) arg);
+
+/*		s5ptv_status.hdmi.audio = (unsigned int) arg; */
+
+		if (arg)
+			s5p_tvif_ctrl_set_audio(true);
+		else
+			s5p_tvif_ctrl_set_audio(false);
+
+		goto end_tvif_ioctl;
+
+	case VIDIOC_AV_MUTE:
+		tvout_dbg("VIDIOC_AV_MUTE(%d)\n", (int) arg);
+
+		if (arg)
+			s5p_tvif_ctrl_set_av_mute(true);
+		else
+			s5p_tvif_ctrl_set_av_mute(false);
+
+		goto end_tvif_ioctl;
+
+	case VIDIOC_G_AVMUTE:
+		s5p_hdmi_ctrl_get_mute();
+		goto end_tvif_ioctl;
+
+	case VIDIOC_HDCP_ENABLE:
+		tvout_dbg("VIDIOC_HDCP_ENABLE(%d)\n", (int) arg);
+
+/*		s5ptv_status.hdmi.hdcp_en = (unsigned int) arg; */
+
+		s5p_hdmi_ctrl_set_hdcp((bool) arg);
+		goto end_tvif_ioctl;
+
+	case VIDIOC_HDCP_STATUS: {
+		unsigned int *status = (unsigned int *)&arg;
+
+		*status = 1;
+
+		goto end_tvif_ioctl;
+	}
+
+	case VIDIOC_HDCP_PROT_STATUS: {
+		unsigned int *prot = (unsigned int *)&arg;
+
+		*prot = 1;
+
+		goto end_tvif_ioctl;
+	}
+
+	case VIDIOC_ENUMSTD: {
+		struct v4l2_standard *p = (struct v4l2_standard *)arg;
+
+		if (p->index >= S5P_TVOUT_TVIF_NO_OF_STANDARD) {
+			tvout_dbg("VIDIOC_ENUMSTD: Invalid index(%d)\n",
+					p->index);
+
+			ret = -EINVAL;
+			goto end_tvif_ioctl;
+		}
+
+		memcpy(p, &s5p_tvout_tvif_standard[p->index],
+			sizeof(struct v4l2_standard));
+
+		goto end_tvif_ioctl;
+	}
+
+	case VIDIOC_SET_VSYNC_INT:
+		s5p_mixer_ctrl_set_vsync_interrupt((int)argp);
+		goto end_tvif_ioctl;
+
+	case VIDIOC_WAITFORVSYNC:
+		s5p_tvout_tvif_wait_for_vsync();
+		goto end_tvif_ioctl;
+
+	case VIDIOC_G_VP_BUFF_INFO: {
+		struct s5ptv_vp_buf_info __user *buff_info =
+			(struct s5ptv_vp_buf_info __user *)arg;
+		struct s5p_tvout_vp_buff __user *buffs;
+		unsigned int tmp = S5PTV_VP_BUFF_CNT;
+		ret = copy_to_user(&buff_info->buff_cnt, &tmp, sizeof(tmp));
+		if (WARN_ON(ret))
+			goto end_tvif_ioctl;
+		ret = copy_from_user(&buffs, &buff_info->buffs,
+				     sizeof(struct s5p_tvout_vp_buff *));
+		if (WARN_ON(ret))
+			goto end_tvif_ioctl;
+		for (i = 0; i < S5PTV_VP_BUFF_CNT; i++) {
+			ret = copy_to_user(&buffs[i].phy_base,
+					   &s5ptv_vp_buff.vp_buffs[i].phy_base,
+					   sizeof(unsigned int));
+			if (WARN_ON(ret))
+				goto end_tvif_ioctl;
+			ret = copy_to_user(&buffs[i].vir_base,
+					   &s5ptv_vp_buff.vp_buffs[i].vir_base,
+					   sizeof(unsigned int));
+			if (WARN_ON(ret))
+				goto end_tvif_ioctl;
+			tmp = S5PTV_VP_BUFF_SIZE;
+			ret = copy_to_user(&buffs[i].size, &tmp, sizeof(tmp));
+			if (WARN_ON(ret))
+				goto end_tvif_ioctl;
+		}
+		goto end_tvif_ioctl;
+	}
+	case VIDIOC_S_VP_BUFF_INFO: {
+		struct s5ptv_vp_buf_info buff_info;
+		struct s5p_tvout_vp_buff buffs[S5PTV_VP_BUFF_CNT];
+		ret = copy_from_user(&buff_info,
+				     (struct s5ptv_vp_buf_info __user *)arg,
+				     sizeof(buff_info));
+		if (WARN_ON(ret))
+			goto end_tvif_ioctl;
+		ret = copy_from_user(buffs, buff_info.buffs, sizeof(buffs));
+		if (WARN_ON(ret))
+			goto end_tvif_ioctl;
+
+		if (buff_info.buff_cnt != S5PTV_VP_BUFF_CNT) {
+			tvout_err("Insufficient buffer count (%d, %d)",
+				  buff_info.buff_cnt, S5PTV_VP_BUFF_CNT);
+			ret = -EINVAL;
+			goto end_tvif_ioctl;
+		}
+		for (i = 0; i < S5PTV_VP_BUFF_CNT; i++) {
+			s5ptv_vp_buff.vp_buffs[i].phy_base = buffs[i].phy_base;
+			s5ptv_vp_buff.vp_buffs[i].vir_base =
+				(unsigned int)phys_to_virt(buffs[i].phy_base);
+			s5ptv_vp_buff.vp_buffs[i].size = buffs[i].size;
+			tvout_dbg("s5ptv_vp_buff phy_base = 0x%x, vir_base = 0x%8x\n",
+				  s5ptv_vp_buff.vp_buffs[i].phy_base,
+				  s5ptv_vp_buff.vp_buffs[i].vir_base);
+		}
+		goto end_tvif_ioctl;
+	}
+	case VIDIOC_S_AUDIO_CHANNEL: {
+		if (!arg)
+			s5p_tvif_audio_channel(TVOUT_AUDIO_2CH_VAL);
+		else
+			s5p_tvif_audio_channel(TVOUT_AUDIO_5_1CH_VAL);
+		/* TODO Runtime change
+		s5p_tvif_ctrl_stop();
+		if (s5p_tvif_ctrl_start(TVOUT_720P_60, TVOUT_HDMI) < 0)
+			goto end_tvif_ioctl; */
+		break;
+	}
+
+	case VIDIOC_S_Q_COLOR_RANGE: {
+		if ((int)arg != 0 && (int)arg != 1) {
+			printk(KERN_ERR "Quantaization range has wrong value!\n");
+			goto end_tvif_ioctl;
+		}
+
+		s5p_tvif_q_color_range((int)arg);
+		break;
+	}
+
+	default:
+		break;
+	}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return video_ioctl2(file, cmd, arg);
+
+end_tvif_ioctl:
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return ret;
+}
+
+
+static int s5p_tvout_tvif_open(struct file *file)
+{
+	mutex_lock(&s5p_tvout_tvif_mutex);
+
+	atomic_inc(&s5p_tvout_v4l2_private.tvif_use);
+
+	mutex_unlock(&s5p_tvout_tvif_mutex);
+
+	tvout_dbg("count=%d\n", atomic_read(&s5p_tvout_v4l2_private.tvif_use));
+
+	return 0;
+}
+
+static int s5p_tvout_tvif_release(struct file *file)
+{
+	tvout_dbg("count=%d\n", atomic_read(&s5p_tvout_v4l2_private.tvif_use));
+
+	mutex_lock(&s5p_tvout_tvif_mutex);
+
+	on_start_process = false;
+	on_stop_process = true;
+	tvout_dbg("on_stop_process(%d)\n", on_stop_process);
+	atomic_dec(&s5p_tvout_v4l2_private.tvif_use);
+
+	if (atomic_read(&s5p_tvout_v4l2_private.tvif_use) == 0)
+		s5p_tvif_ctrl_stop();
+
+	on_stop_process = false;
+	tvout_dbg("on_stop_process(%d)\n", on_stop_process);
+	mutex_unlock(&s5p_tvout_tvif_mutex);
+
+	return 0;
+}
+
+static struct v4l2_file_operations s5p_tvout_tvif_fops = {
+	.owner		= THIS_MODULE,
+	.open		= s5p_tvout_tvif_open,
+	.release	= s5p_tvout_tvif_release,
+	.ioctl		= s5p_tvout_tvif_ioctl
+};
+
+
+static int s5p_tvout_vo_querycap(
+		struct file *file, void *fh, struct v4l2_capability *cap)
+{
+	strcpy(cap->driver, "s5p-tvout-vo");
+	strcpy(cap->card, "Samsung TVOUT Video Overlay");
+	cap->capabilities = V4L2_CAP_VIDEO_OVERLAY;
+	cap->version = KERNEL_VERSION(
+				MAJOR_VERSION, MINOR_VERSION, RELEASE_VERSION);
+
+	return 0;
+}
+
+static int s5p_tvout_vo_enum_fmt_type_private(
+		struct file *file, void *fh, struct v4l2_fmtdesc *f)
+{
+	int index = f->index;
+
+	if (index >= ARRAY_SIZE(s5p_tvout_vo_fmt_desc)) {
+		tvout_err("Invalid index(%d)\n", index);
+
+		return -EINVAL;
+	}
+
+	memcpy(f, &s5p_tvout_vo_fmt_desc[index], sizeof(struct v4l2_fmtdesc));
+
+	return 0;
+}
+
+static int s5p_tvout_vo_g_fmt_type_private(
+		struct file *file, void *fh, struct v4l2_format *a)
+{
+	memcpy(a->fmt.raw_data,	&s5p_tvout_v4l2_private.vo_src_fmt,
+		sizeof(struct v4l2_vid_overlay_src));
+
+	return 0;
+}
+
+static int s5p_tvout_vo_s_fmt_type_private(
+		struct file *file, void *fh, struct v4l2_format *a)
+{
+	struct v4l2_vid_overlay_src	vparam;
+	struct v4l2_pix_format		*pix_fmt;
+	enum s5p_vp_src_color		color;
+	enum s5p_vp_field		field;
+	unsigned int			src_vir_y_addr;
+	unsigned int			src_vir_cb_addr;
+	int				y_size;
+	int				cbcr_size;
+	unsigned int			copy_buff_idx;
+
+#if defined(CONFIG_S5P_SYSMMU_TV)
+	unsigned long base_y, base_c;
+#endif
+	memcpy(&vparam, a->fmt.raw_data, sizeof(struct v4l2_vid_overlay_src));
+
+	pix_fmt = &vparam.pix_fmt;
+
+	tvout_dbg("base_y=0x%X, base_c=0x%X, field=%d\n",
+			(u32) vparam.base_y, (u32) vparam.base_c,
+			pix_fmt->field);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	/* check progressive or not */
+	if (pix_fmt->field == V4L2_FIELD_NONE) {
+		/* progressive */
+		switch (pix_fmt->pixelformat) {
+		case V4L2_PIX_FMT_NV12:
+			/* linear */
+			tvout_dbg("pixelformat=V4L2_PIX_FMT_NV12\n");
+
+			color = VP_SRC_COLOR_NV12;
+			break;
+
+		case V4L2_PIX_FMT_NV12T:
+			/* tiled */
+			tvout_dbg("pixelformat=V4L2_PIX_FMT_NV12T\n");
+			color = VP_SRC_COLOR_TILE_NV12;
+			break;
+		case V4L2_PIX_FMT_NV21:
+			/* linear */
+			color = VP_SRC_COLOR_NV21;
+			break;
+
+		case V4L2_PIX_FMT_NV21T:
+			/* tiled */
+			color = VP_SRC_COLOR_TILE_NV21;
+			break;
+
+		default:
+			tvout_err("src img format not supported\n");
+			goto error_on_s_fmt_type_private;
+		}
+
+		field = VP_TOP_FIELD;
+	} else if ((pix_fmt->field == V4L2_FIELD_TOP) ||
+			(pix_fmt->field == V4L2_FIELD_BOTTOM)) {
+		/* interlaced */
+		switch (pix_fmt->pixelformat) {
+		case V4L2_PIX_FMT_NV12:
+			/* linear */
+			tvout_dbg("pixelformat=V4L2_PIX_FMT_NV12\n");
+			color = VP_SRC_COLOR_NV12IW;
+			break;
+
+		case V4L2_PIX_FMT_NV12T:
+			/* tiled */
+			tvout_dbg("pixelformat=V4L2_PIX_FMT_NV12T\n");
+			color = VP_SRC_COLOR_TILE_NV12IW;
+			break;
+		case V4L2_PIX_FMT_NV21:
+			/* linear */
+			color = VP_SRC_COLOR_NV21IW;
+			break;
+
+		case V4L2_PIX_FMT_NV21T:
+			/* tiled */
+			color = VP_SRC_COLOR_TILE_NV21IW;
+			break;
+
+		default:
+			tvout_err("src img format not supported\n");
+			goto error_on_s_fmt_type_private;
+		}
+
+		field = (pix_fmt->field == V4L2_FIELD_BOTTOM) ?
+				VP_BOTTOM_FIELD : VP_TOP_FIELD;
+
+	} else {
+		tvout_err("this field id not supported\n");
+
+		goto error_on_s_fmt_type_private;
+	}
+
+	s5p_tvout_v4l2_private.vo_src_fmt = vparam;
+#if defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_UMP_VCM_ALLOC)
+	/*
+	 * For TV system mmu test using UMP and VCMM
+	 * vparam.base_y : secure ID
+	 * vparam.base_c : offset of base_c from base_y
+	 */
+	base_y = ump_dd_dev_virtual_get_from_secure_id((unsigned int)
+		vparam.base_y);
+	base_c = base_y + (unsigned long)vparam.base_c;
+	s5p_vp_ctrl_set_src_plane(base_y, base_c, pix_fmt->width,
+		pix_fmt->height, color, field);
+#elif defined(CONFIG_S5P_SYSMMU_TV) && defined(CONFIG_S5P_VMEM)
+	/*
+	 * For TV system mmu test
+	 * vparam.base_y : cookie
+	 * vparam.base_c : offset of base_c from base_y
+	 */
+	base_y = (unsigned long) s5p_getaddress((unsigned int)vparam.base_y);
+	base_c = base_y + (unsigned long)vparam.base_c;
+	s5p_vp_ctrl_set_src_plane(base_y, base_c, pix_fmt->width,
+		pix_fmt->height, color, field);
+#else
+	if (pix_fmt->priv) {
+		copy_buff_idx = s5ptv_vp_buff.copy_buff_idxs[s5ptv_vp_buff.curr_copy_idx];
+
+		if ((void *)s5ptv_vp_buff.vp_buffs[copy_buff_idx].vir_base == NULL) {
+			s5p_vp_ctrl_set_src_plane((u32) vparam.base_y, (u32) vparam.base_c,
+					pix_fmt->width, pix_fmt->height, color, field);
+		} else {
+			if (pix_fmt->pixelformat == V4L2_PIX_FMT_NV12T
+					|| pix_fmt->pixelformat == V4L2_PIX_FMT_NV21T) {
+				y_size = ALIGN(ALIGN(pix_fmt->width, 128) * ALIGN(pix_fmt->height, 32), SZ_8K);
+				cbcr_size = ALIGN(ALIGN(pix_fmt->width, 128) * ALIGN(pix_fmt->height >> 1, 32), SZ_8K);
+			} else {
+				y_size = pix_fmt->width * pix_fmt->height;
+				cbcr_size = pix_fmt->width * (pix_fmt->height >> 1);
+			}
+
+			src_vir_y_addr = (unsigned int)phys_to_virt((unsigned long)vparam.base_y);
+			src_vir_cb_addr = (unsigned int)phys_to_virt((unsigned long)vparam.base_c);
+
+			memcpy((void *)s5ptv_vp_buff.vp_buffs[copy_buff_idx].vir_base,
+					(void *)src_vir_y_addr, y_size);
+			memcpy((void *)s5ptv_vp_buff.vp_buffs[copy_buff_idx].vir_base + y_size,
+					(void *)src_vir_cb_addr, cbcr_size);
+
+			flush_all_cpu_caches();
+			outer_flush_all();
+
+			s5p_vp_ctrl_set_src_plane((u32) s5ptv_vp_buff.vp_buffs[copy_buff_idx].phy_base,
+					(u32) s5ptv_vp_buff.vp_buffs[copy_buff_idx].phy_base + y_size,
+					pix_fmt->width, pix_fmt->height, color, field);
+
+			s5ptv_vp_buff.curr_copy_idx++;
+			if (s5ptv_vp_buff.curr_copy_idx >= S5PTV_VP_BUFF_CNT - 1)
+				s5ptv_vp_buff.curr_copy_idx = 0;
+		}
+	} else {
+		s5p_vp_ctrl_set_src_plane((u32) vparam.base_y, (u32) vparam.base_c,
+				pix_fmt->width, pix_fmt->height, color, field);
+	}
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+
+error_on_s_fmt_type_private:
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return -1;
+}
+
+static int s5p_tvout_vo_g_fmt_vid_overlay(
+		struct file *file, void	*fh, struct v4l2_format *a)
+{
+	a->fmt.win = s5p_tvout_v4l2_private.vo_dst_fmt;
+
+	return 0;
+}
+
+static int s5p_tvout_vo_s_fmt_vid_overlay(
+		struct file *file, void *fh, struct v4l2_format *a)
+{
+	struct v4l2_rect *rect = &a->fmt.win.w;
+
+	tvout_dbg("l=%d, t=%d, w=%d, h=%d, g_alpha_value=%d\n",
+			rect->left, rect->top, rect->width, rect->height,
+			a->fmt.win.global_alpha);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	s5p_tvout_v4l2_private.vo_dst_fmt = a->fmt.win;
+
+	s5p_vp_ctrl_set_dest_win_alpha_val(a->fmt.win.global_alpha);
+	s5p_vp_ctrl_set_dest_win(
+		rect->left, rect->top,
+		rect->width, rect->height);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+}
+
+static int s5p_tvout_vo_g_crop(
+		struct file *file, void *fh, struct v4l2_crop *a)
+{
+	switch (a->type) {
+	case V4L2_BUF_TYPE_PRIVATE:
+		a->c = s5p_tvout_v4l2_private.vo_src_rect;
+		break;
+
+	default:
+		tvout_err("Invalid buf type(0x%08x)\n", a->type);
+		break;
+	}
+
+	return 0;
+}
+
+static int s5p_tvout_vo_s_crop(
+		struct file *file, void *fh, struct v4l2_crop *a)
+{
+	tvout_dbg("\n");
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	switch (a->type) {
+	case V4L2_BUF_TYPE_PRIVATE: {
+		struct v4l2_rect *rect =
+				&s5p_tvout_v4l2_private.vo_src_rect;
+
+		*rect = a->c;
+
+		tvout_dbg("l=%d, t=%d, w=%d, h=%d\n",
+				rect->left, rect->top,
+				rect->width, rect->height);
+
+		s5p_vp_ctrl_set_src_win(
+			rect->left, rect->top,
+			rect->width, rect->height);
+		break;
+	}
+	default:
+		tvout_err("Invalid buf type(0x%08x)\n", a->type);
+		break;
+	}
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+}
+
+static int s5p_tvout_vo_g_fbuf(
+		struct file *file, void *fh, struct v4l2_framebuffer *a)
+{
+	*a = s5p_tvout_v4l2_private.vo_dst_plane;
+
+	a->capability = V4L2_FBUF_CAP_GLOBAL_ALPHA;
+
+	return 0;
+}
+
+static int s5p_tvout_vo_s_fbuf(
+		struct file *file, void *fh, struct v4l2_framebuffer *a)
+{
+	s5p_tvout_v4l2_private.vo_dst_plane = *a;
+
+	tvout_dbg("g_alpha_enable=%d, priority=%d\n",
+			(a->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) ? 1 : 0,
+			a->fmt.priv);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+
+	s5p_vp_ctrl_set_dest_win_blend(
+		(a->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) ? 1 : 0);
+
+	s5p_vp_ctrl_set_dest_win_priority(a->fmt.priv);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+}
+
+static int s5p_tvout_vo_overlay(
+		struct file *file, void *fh, unsigned int i)
+{
+	tvout_dbg("%s\n", (i) ? "start" : "stop");
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_lock();
+#endif
+	if (i)
+		s5p_vp_ctrl_start();
+	else
+		s5p_vp_ctrl_stop();
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	s5p_tvout_mutex_unlock();
+#endif
+	return 0;
+}
+
+const struct v4l2_ioctl_ops s5p_tvout_vo_ioctl_ops = {
+	.vidioc_querycap		= s5p_tvout_vo_querycap,
+
+	.vidioc_enum_fmt_type_private	= s5p_tvout_vo_enum_fmt_type_private,
+	.vidioc_g_fmt_type_private	= s5p_tvout_vo_g_fmt_type_private,
+	.vidioc_s_fmt_type_private	= s5p_tvout_vo_s_fmt_type_private,
+
+	.vidioc_g_fmt_vid_overlay	= s5p_tvout_vo_g_fmt_vid_overlay,
+	.vidioc_s_fmt_vid_overlay	= s5p_tvout_vo_s_fmt_vid_overlay,
+
+	.vidioc_g_crop			= s5p_tvout_vo_g_crop,
+	.vidioc_s_crop			= s5p_tvout_vo_s_crop,
+
+	.vidioc_g_fbuf			= s5p_tvout_vo_g_fbuf,
+	.vidioc_s_fbuf			= s5p_tvout_vo_s_fbuf,
+
+	.vidioc_overlay			= s5p_tvout_vo_overlay,
+};
+
+static int s5p_tvout_vo_open(struct file *file)
+{
+	int ret = 0;
+
+	tvout_dbg("\n");
+
+	mutex_lock(&s5p_tvout_vo_mutex);
+
+	if (atomic_read(&s5p_tvout_v4l2_private.vo_use)) {
+		tvout_err("Can't open TVOUT TVIF control\n");
+		ret = -EBUSY;
+	} else
+		atomic_inc(&s5p_tvout_v4l2_private.vo_use);
+
+	mutex_unlock(&s5p_tvout_vo_mutex);
+
+	return ret;
+}
+
+static int s5p_tvout_vo_release(struct file *file)
+{
+	tvout_dbg("\n");
+
+	s5p_vp_ctrl_stop();
+
+	s5p_mixer_ctrl_disable_layer(MIXER_VIDEO_LAYER);
+
+	atomic_dec(&s5p_tvout_v4l2_private.vo_use);
+
+	return 0;
+}
+
+static struct v4l2_file_operations s5p_tvout_vo_fops = {
+	.owner		= THIS_MODULE,
+	.open		= s5p_tvout_vo_open,
+	.release	= s5p_tvout_vo_release,
+	.ioctl		= video_ioctl2
+};
+
+
+/* dummy function for release callback of v4l2 video device */
+static void s5p_tvout_video_dev_release(struct video_device *vdev)
+{
+}
+
+static struct video_device s5p_tvout_video_dev[] = {
+	[0] = {
+		.name		= "S5P TVOUT TVIF control",
+		.fops		= &s5p_tvout_tvif_fops,
+		.ioctl_ops	= &s5p_tvout_tvif_ioctl_ops,
+		.minor		= S5P_TVOUT_TVIF_MINOR,
+		.release	= s5p_tvout_video_dev_release,
+		.tvnorms	= V4L2_STD_ALL_HD,
+	},
+	[1] = {
+		.name		= "S5P TVOUT Video Overlay",
+		.fops		= &s5p_tvout_vo_fops,
+		.ioctl_ops	= &s5p_tvout_vo_ioctl_ops,
+		.release	= s5p_tvout_video_dev_release,
+		.minor		= S5P_TVOUT_VO_MINOR
+	}
+};
+
+int s5p_tvout_v4l2_constructor(struct platform_device *pdev)
+{
+	int i;
+
+	/* v4l2 video device registration */
+	for (i = 0; i < ARRAY_SIZE(s5p_tvout_video_dev); i++) {
+
+		if (video_register_device(
+				&s5p_tvout_video_dev[i],
+				VFL_TYPE_GRABBER,
+				s5p_tvout_video_dev[i].minor) != 0) {
+			tvout_err("Fail to register v4l2 video device\n");
+
+			return -1;
+		}
+	}
+
+	s5p_tvout_v4l2_init_private();
+
+	return 0;
+}
+
+void s5p_tvout_v4l2_destructor(void)
+{
+	mutex_destroy(&s5p_tvout_tvif_mutex);
+	mutex_destroy(&s5p_tvout_vo_mutex);
+}
diff --git a/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.h b/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.h
new file mode 100644
index 0000000..62a949c
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.h
@@ -0,0 +1,19 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_tvout_v4l2.h
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Video4Linux API header file. file for Samsung TVOut driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _S5P_TVOUT_V4L2_H_
+#define _S5P_TVOUT_V4L2_H_
+
+extern int s5p_tvout_v4l2_constructor(struct platform_device *pdev);
+extern void s5p_tvout_v4l2_destructor(void);
+
+#endif /* _LINUX_S5P_TVOUT_V4L2_H_ */
diff --git a/drivers/media/video/samsung/tvout/s5p_vp_ctrl.c b/drivers/media/video/samsung/tvout/s5p_vp_ctrl.c
new file mode 100644
index 0000000..d074da3
--- /dev/null
+++ b/drivers/media/video/samsung/tvout/s5p_vp_ctrl.c
@@ -0,0 +1,742 @@
+/* linux/drivers/media/video/samsung/tvout/s5p_vp_ctrl.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ *		http://www.samsung.com/
+ *
+ * Control class functions for S5P video processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include "hw_if/hw_if.h"
+#include "s5p_tvout_ctrl.h"
+
+#if defined(CONFIG_BUSFREQ)
+#include <mach/cpufreq.h>
+#endif
+
+#define INTERLACED	0
+#define PROGRESSIVE	1
+
+struct s5p_vp_ctrl_op_mode {
+	bool	ipc;
+	bool	line_skip;
+	bool	auto_toggling;
+};
+
+struct s5p_vp_ctrl_bc_line_eq {
+	enum s5p_vp_line_eq	eq_num;
+	u32			intc;
+	u32			slope;
+};
+
+struct s5p_vp_ctrl_rect {
+	u32 x;
+	u32 y;
+	u32 w;
+	u32 h;
+};
+
+struct s5p_vp_ctrl_plane {
+	u32			top_y_addr;
+	u32			top_c_addr;
+	u32			w;
+	u32			h;
+
+	enum s5p_vp_src_color	color_t;
+	enum s5p_vp_field	field_id;
+	enum s5p_vp_mem_type	mem_type;
+	enum s5p_vp_mem_mode	mem_mode;
+};
+
+struct s5p_vp_ctrl_pp_param {
+	bool				bypass;
+
+	bool csc_en;
+	enum s5p_vp_csc_type		csc_t;
+	bool				csc_default_coef;
+	bool				csc_sub_y_offset_en;
+
+	u32				saturation;
+	u8				contrast;
+	bool				brightness;
+	u32				bright_offset;
+	struct s5p_vp_ctrl_bc_line_eq	bc_line_eq[8];
+
+	/* sharpness */
+	u32				th_hnoise;
+	enum s5p_vp_sharpness_control	sharpness;
+
+
+	bool				default_poly_filter;
+
+	enum s5p_vp_chroma_expansion	chroma_exp;
+};
+
+struct s5p_vp_ctrl_mixer_param {
+	bool	blend;
+	u32	alpha;
+	u32	prio;
+};
+
+struct s5p_vp_ctrl_private_data {
+	struct s5p_vp_ctrl_plane	src_plane;
+	struct s5p_vp_ctrl_rect		src_win;
+
+	struct s5p_vp_ctrl_rect		dst_win;
+	struct s5p_vp_ctrl_op_mode	op_mode;
+
+	struct s5p_vp_ctrl_pp_param	pp_param;
+	struct s5p_vp_ctrl_mixer_param	mixer_param;
+
+	bool				running;
+
+	struct reg_mem_info		reg_mem;
+
+	struct s5p_tvout_clk_info	clk;
+	char				*pow_name;
+
+	struct device *dev;
+};
+
+static struct s5p_vp_ctrl_private_data s5p_vp_ctrl_private = {
+	.reg_mem = {
+		.name			= "s5p-vp",
+		.res			= NULL,
+		.base			= NULL
+	},
+
+	.clk = {
+		.name			= "vp",
+		.ptr			= NULL
+	},
+
+	.pow_name			= "vp_pd",
+
+	.src_plane = {
+		.field_id		= VP_TOP_FIELD,
+	},
+
+	.pp_param = {
+		.default_poly_filter	= true,
+		.bypass			= false,
+
+		.saturation		= 0x80,
+		.brightness		= 0x00,
+		.bright_offset		= 0x00,
+		.contrast		= 0x80,
+
+		.th_hnoise		= 0,
+		.sharpness		= VP_SHARPNESS_NO,
+
+		.chroma_exp		= 0,
+
+		.csc_en			= false,
+		.csc_default_coef	= true,
+		.csc_sub_y_offset_en	= false,
+	},
+
+	.running			= false
+};
+
+extern int s5p_vp_get_top_field_address(u32* top_y_addr, u32* top_c_addr);
+
+static u8 s5p_vp_ctrl_get_src_scan_mode(void)
+{
+	struct s5p_vp_ctrl_plane *src_plane = &s5p_vp_ctrl_private.src_plane;
+	u8 ret = PROGRESSIVE;
+
+	if (src_plane->color_t == VP_SRC_COLOR_NV12IW ||
+		src_plane->color_t == VP_SRC_COLOR_TILE_NV12IW ||
+		src_plane->color_t == VP_SRC_COLOR_NV21IW ||
+		src_plane->color_t == VP_SRC_COLOR_TILE_NV21IW)
+		ret = INTERLACED;
+
+	return ret;
+}
+
+static u8 s5p_vp_ctrl_get_dest_scan_mode(
+		enum s5p_tvout_disp_mode display, enum s5p_tvout_o_mode out)
+{
+	u8 ret = PROGRESSIVE;
+
+	switch (out) {
+	case TVOUT_COMPOSITE:
+		ret = INTERLACED;
+		break;
+
+	case TVOUT_HDMI_RGB:
+	case TVOUT_HDMI:
+	case TVOUT_DVI:
+		if (display == TVOUT_1080I_60 ||
+		   display == TVOUT_1080I_59 ||
+		   display == TVOUT_1080I_50)
+			ret = INTERLACED;
+		break;
+
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static void s5p_vp_ctrl_set_src_dst_win(
+		struct s5p_vp_ctrl_rect	src_win,
+		struct s5p_vp_ctrl_rect	dst_win,
+		enum s5p_tvout_disp_mode	disp,
+		enum s5p_tvout_o_mode	out,
+		enum s5p_vp_src_color	color_t,
+		bool ipc)
+{
+	struct s5p_vp_ctrl_op_mode *op_mode = &s5p_vp_ctrl_private.op_mode;
+
+	if (s5p_vp_ctrl_get_dest_scan_mode(disp, out) == INTERLACED) {
+		if (op_mode->line_skip) {
+			src_win.y /= 2;
+			src_win.h /= 2;
+		}
+
+		dst_win.y /= 2;
+		dst_win.h /= 2;
+	} else if (s5p_vp_ctrl_get_src_scan_mode() == INTERLACED) {
+		src_win.y /= 2;
+		src_win.h /= 2;
+	}
+
+	s5p_vp_set_src_position(src_win.x, 0, src_win.y);
+	s5p_vp_set_dest_position(dst_win.x, dst_win.y);
+	s5p_vp_set_src_dest_size(
+		src_win.w, src_win.h, dst_win.w, dst_win.h, ipc);
+}
+
+int s5p_vp_ctrl_get_src_addr(u32* top_y_addr, u32* top_c_addr)
+{
+	if (s5p_vp_ctrl_private.running)
+		s5p_vp_get_top_field_address(top_y_addr, top_c_addr);
+	else {
+		*top_y_addr = 0;
+		*top_c_addr = 0;
+	}
+
+	return 0;
+}
+
+static int s5p_vp_ctrl_set_src_addr(
+		u32 top_y_addr, u32 top_c_addr,
+		u32 img_w, enum s5p_vp_src_color color_t)
+{
+	if (s5p_vp_set_top_field_address(top_y_addr, top_c_addr))
+		return -1;
+
+	if (s5p_vp_ctrl_get_src_scan_mode() == INTERLACED) {
+		u32	bot_y = 0;
+		u32	bot_c = 0;
+
+		if (color_t == VP_SRC_COLOR_NV12IW ||
+				color_t == VP_SRC_COLOR_NV21IW) {
+			bot_y = top_y_addr + img_w;
+			bot_c = top_c_addr + img_w;
+		} else if (color_t == VP_SRC_COLOR_TILE_NV12IW ||
+				color_t == VP_SRC_COLOR_TILE_NV21IW) {
+			bot_y = top_y_addr + 0x40;
+			bot_c = top_c_addr + 0x40;
+		}
+
+		if (s5p_vp_set_bottom_field_address(bot_y, bot_c))
+			return -1;
+	}
+
+	return 0;
+}
+
+static void s5p_vp_ctrl_init_private(void)
+{
+	int i;
+	struct s5p_vp_ctrl_pp_param *pp_param = &s5p_vp_ctrl_private.pp_param;
+
+	for (i = 0; i < 8; i++)
+		pp_param->bc_line_eq[i].eq_num = VP_LINE_EQ_DEFAULT;
+}
+
+static int s5p_vp_ctrl_set_reg(void)
+{
+	int i;
+	int ret = 0;
+
+	enum s5p_tvout_disp_mode	tv_std;
+	enum s5p_tvout_o_mode		tv_if;
+
+	struct s5p_vp_ctrl_plane *src_plane = &s5p_vp_ctrl_private.src_plane;
+	struct s5p_vp_ctrl_pp_param *pp_param = &s5p_vp_ctrl_private.pp_param;
+	struct s5p_vp_ctrl_op_mode *op_mode = &s5p_vp_ctrl_private.op_mode;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+	} else
+#endif
+	{
+		s5p_tvif_ctrl_get_std_if(&tv_std, &tv_if);
+
+		s5p_vp_sw_reset();
+
+		s5p_vp_set_endian(TVOUT_BIG_ENDIAN);
+
+		s5p_vp_set_op_mode(
+			op_mode->line_skip, src_plane->mem_type,
+			src_plane->mem_mode, pp_param->chroma_exp,
+			op_mode->auto_toggling);
+
+		s5p_vp_set_field_id(src_plane->field_id);
+
+		s5p_vp_set_img_size(src_plane->w, src_plane->h);
+
+		s5p_vp_ctrl_set_src_addr(
+			src_plane->top_y_addr, src_plane->top_c_addr,
+			src_plane->w, src_plane->color_t);
+
+		s5p_vp_ctrl_set_src_dst_win(
+			s5p_vp_ctrl_private.src_win,
+			s5p_vp_ctrl_private.dst_win,
+			tv_std,
+			tv_if,
+			s5p_vp_ctrl_private.src_plane.color_t,
+			op_mode->ipc);
+
+		if (pp_param->default_poly_filter)
+			s5p_vp_set_poly_filter_coef_default(
+				s5p_vp_ctrl_private.src_win.w,
+				s5p_vp_ctrl_private.src_win.h,
+				s5p_vp_ctrl_private.dst_win.w,
+				s5p_vp_ctrl_private.dst_win.h,
+				op_mode->ipc);
+
+		s5p_vp_set_bypass_post_process(pp_param->bypass);
+		s5p_vp_set_sharpness(pp_param->th_hnoise, pp_param->sharpness);
+		s5p_vp_set_saturation(pp_param->saturation);
+		s5p_vp_set_brightness_contrast(
+				pp_param->brightness, pp_param->contrast);
+
+		for (i = VP_LINE_EQ_0; i <= VP_LINE_EQ_7; i++) {
+			if (pp_param->bc_line_eq[i].eq_num == i)
+				ret = s5p_vp_set_brightness_contrast_control(
+					pp_param->bc_line_eq[i].eq_num,
+					pp_param->bc_line_eq[i].intc,
+					pp_param->bc_line_eq[i].slope);
+
+			if (ret != 0)
+				return -1;
+		}
+
+		s5p_vp_set_brightness_offset(pp_param->bright_offset);
+
+		s5p_vp_set_csc_control(
+				pp_param->csc_sub_y_offset_en,
+				pp_param->csc_en);
+
+		if (pp_param->csc_en && pp_param->csc_default_coef) {
+			if (s5p_vp_set_csc_coef_default(pp_param->csc_t))
+				return -1;
+		}
+
+		if (s5p_vp_start())
+			return -1;
+
+	}
+
+	s5p_mixer_ctrl_enable_layer(MIXER_VIDEO_LAYER);
+
+	mdelay(50);
+
+	return 0;
+}
+
+static void s5p_vp_ctrl_internal_stop(void)
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+	} else
+#endif
+		s5p_vp_stop();
+
+	s5p_mixer_ctrl_disable_layer(MIXER_VIDEO_LAYER);
+}
+
+static void s5p_vp_ctrl_clock(bool on)
+{
+	if (on) {
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_get();
+#endif
+		clk_enable(s5p_vp_ctrl_private.clk.ptr);
+		// Restore vp_base address
+		s5p_vp_init(s5p_vp_ctrl_private.reg_mem.base);
+
+	} else {
+		clk_disable(s5p_vp_ctrl_private.clk.ptr);
+#ifdef CONFIG_ARCH_EXYNOS4
+		s5p_tvout_pm_runtime_put();
+#endif
+		// Set vp_base to NULL
+		s5p_vp_init(NULL);
+	}
+}
+
+
+
+void s5p_vp_ctrl_set_src_plane(
+		u32 base_y, u32 base_c,	u32 width, u32 height,
+		enum s5p_vp_src_color color, enum s5p_vp_field field)
+{
+	struct s5p_vp_ctrl_plane *src_plane = &s5p_vp_ctrl_private.src_plane;
+
+	src_plane->color_t	= color;
+	src_plane->field_id	= field;
+
+	src_plane->top_y_addr	= base_y;
+	src_plane->top_c_addr	= base_c;
+
+	src_plane->w		= width;
+	src_plane->h		= height;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	if (s5p_vp_ctrl_private.running) {
+		s5p_vp_set_img_size(width, height);
+
+		s5p_vp_set_field_id(field);
+		s5p_vp_ctrl_set_src_addr(base_y, base_c, width, color);
+
+		s5p_vp_update();
+	}
+}
+
+void s5p_vp_ctrl_set_src_win(u32 left, u32 top, u32 width, u32 height)
+{
+	struct s5p_vp_ctrl_rect *src_win = &s5p_vp_ctrl_private.src_win;
+
+	src_win->x = left;
+	src_win->y = top;
+	src_win->w = width;
+	src_win->h = height;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	if (s5p_vp_ctrl_private.running) {
+		enum s5p_tvout_disp_mode	tv_std;
+		enum s5p_tvout_o_mode		tv_if;
+
+		s5p_tvif_ctrl_get_std_if(&tv_std, &tv_if);
+
+		s5p_vp_ctrl_set_src_dst_win(
+			*src_win,
+			s5p_vp_ctrl_private.dst_win,
+			tv_std,
+			tv_if,
+			s5p_vp_ctrl_private.src_plane.color_t,
+			s5p_vp_ctrl_private.op_mode.ipc);
+
+		s5p_vp_update();
+	}
+}
+
+void s5p_vp_ctrl_set_dest_win(u32 left, u32 top, u32 width, u32 height)
+{
+	struct s5p_vp_ctrl_rect *dst_win = &s5p_vp_ctrl_private.dst_win;
+
+	dst_win->x = left;
+	dst_win->y = top;
+	dst_win->w = width;
+	dst_win->h = height;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	if (s5p_vp_ctrl_private.running) {
+		enum s5p_tvout_disp_mode	tv_std;
+		enum s5p_tvout_o_mode		tv_if;
+
+		s5p_tvif_ctrl_get_std_if(&tv_std, &tv_if);
+
+		s5p_vp_ctrl_set_src_dst_win(
+			s5p_vp_ctrl_private.src_win,
+			*dst_win,
+			tv_std,
+			tv_if,
+			s5p_vp_ctrl_private.src_plane.color_t,
+			s5p_vp_ctrl_private.op_mode.ipc);
+
+		s5p_vp_update();
+	}
+}
+
+void s5p_vp_ctrl_set_dest_win_alpha_val(u32 alpha)
+{
+	s5p_vp_ctrl_private.mixer_param.alpha = alpha;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	s5p_mixer_ctrl_set_alpha(MIXER_VIDEO_LAYER, alpha);
+}
+
+void s5p_vp_ctrl_set_dest_win_blend(bool enable)
+{
+	s5p_vp_ctrl_private.mixer_param.blend = enable;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	s5p_mixer_ctrl_set_blend_mode(MIXER_VIDEO_LAYER,
+			LAYER_BLENDING);
+}
+
+void s5p_vp_ctrl_set_dest_win_priority(u32 prio)
+{
+	s5p_vp_ctrl_private.mixer_param.prio = prio;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+		return;
+	}
+#endif
+	s5p_mixer_ctrl_set_priority(MIXER_VIDEO_LAYER, prio);
+}
+
+void s5p_vp_ctrl_stop(void)
+{
+	if (s5p_vp_ctrl_private.running) {
+		s5p_vp_ctrl_internal_stop();
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	if (suspend_status) {
+		tvout_dbg("driver is suspend_status\n");
+	} else
+#endif
+	{
+		s5p_vp_ctrl_clock(0);
+	}
+
+		s5p_vp_ctrl_private.running = false;
+#if defined(CONFIG_BUSFREQ) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+	exynos4_busfreq_lock_free(DVFS_LOCK_ID_TV);
+#endif
+	}
+}
+
+int s5p_vp_ctrl_start(void)
+{
+	struct s5p_vp_ctrl_plane *src_plane = &s5p_vp_ctrl_private.src_plane;
+	enum s5p_tvout_disp_mode disp;
+	enum s5p_tvout_o_mode out;
+
+	struct s5p_vp_ctrl_rect *src_win = &s5p_vp_ctrl_private.src_win;
+	struct s5p_vp_ctrl_rect *dst_win = &s5p_vp_ctrl_private.dst_win;
+
+	bool i_mode, o_mode; /* 0 for interlaced, 1 for progressive */
+
+	s5p_tvif_ctrl_get_std_if(&disp, &out);
+
+	switch (disp) {
+	case TVOUT_480P_60_16_9:
+	case TVOUT_480P_60_4_3:
+	case TVOUT_576P_50_16_9:
+	case TVOUT_576P_50_4_3:
+	case TVOUT_480P_59:
+		s5p_vp_ctrl_private.pp_param.csc_t = VP_CSC_SD_HD;
+		break;
+
+	case TVOUT_1080I_50:
+	case TVOUT_1080I_60:
+	case TVOUT_1080P_50:
+	case TVOUT_1080P_30:
+	case TVOUT_1080P_60:
+	case TVOUT_720P_59:
+	case TVOUT_1080I_59:
+	case TVOUT_1080P_59:
+	case TVOUT_720P_50:
+	case TVOUT_720P_60:
+		s5p_vp_ctrl_private.pp_param.csc_t = VP_CSC_HD_SD;
+		break;
+#ifdef CONFIG_HDMI_14A_3D
+	case TVOUT_720P_60_SBS_HALF:
+	case TVOUT_720P_59_SBS_HALF:
+	case TVOUT_720P_50_TB:
+	case TVOUT_1080P_24_TB:
+	case TVOUT_1080P_23_TB:
+		s5p_vp_ctrl_private.pp_param.csc_t = VP_CSC_HD_SD;
+		break;
+
+#endif
+
+	default:
+		break;
+	}
+
+	i_mode = s5p_vp_ctrl_get_src_scan_mode();
+	o_mode = s5p_vp_ctrl_get_dest_scan_mode(disp, out);
+
+	/* check o_mode */
+	if (i_mode == INTERLACED) {
+		if (o_mode == INTERLACED) {
+			/* i to i : line skip 1, ipc 0, auto toggle 0 */
+			s5p_vp_ctrl_private.op_mode.line_skip		= true;
+			s5p_vp_ctrl_private.op_mode.ipc			= false;
+			s5p_vp_ctrl_private.op_mode.auto_toggling	= false;
+		} else {
+			/* i to p : line skip 1, ipc 1, auto toggle 0 */
+			s5p_vp_ctrl_private.op_mode.line_skip		= true;
+			s5p_vp_ctrl_private.op_mode.ipc			= true;
+			s5p_vp_ctrl_private.op_mode.auto_toggling	= false;
+		}
+	} else {
+		if (o_mode == INTERLACED) {
+			/* p to i : line skip 0, ipc 0, auto toggle 0 */
+			if (dst_win->h > src_win->h &&
+			   ((dst_win->h << 16)/src_win->h < 0x100000))
+				s5p_vp_ctrl_private.op_mode.line_skip	= false;
+			/* p to i : line skip 1, ipc 0, auto toggle 0 */
+			else
+				s5p_vp_ctrl_private.op_mode.line_skip	= true;
+			s5p_vp_ctrl_private.op_mode.ipc			= false;
+			s5p_vp_ctrl_private.op_mode.auto_toggling	= false;
+		} else {
+			/* p to p : line skip 0, ipc 0, auto toggle 0 */
+			s5p_vp_ctrl_private.op_mode.line_skip		= false;
+			s5p_vp_ctrl_private.op_mode.ipc			= false;
+			s5p_vp_ctrl_private.op_mode.auto_toggling	= false;
+		}
+	}
+	src_plane->mem_type
+		= ((src_plane->color_t == VP_SRC_COLOR_NV12) ||
+			(src_plane->color_t == VP_SRC_COLOR_NV12IW) ||
+			(src_plane->color_t == VP_SRC_COLOR_TILE_NV12) ||
+			(src_plane->color_t == VP_SRC_COLOR_TILE_NV12IW)) ?
+			VP_YUV420_NV12 : VP_YUV420_NV21;
+
+	src_plane->mem_mode
+		= ((src_plane->color_t == VP_SRC_COLOR_NV12) ||
+			(src_plane->color_t == VP_SRC_COLOR_NV12IW) ||
+			(src_plane->color_t == VP_SRC_COLOR_NV21) ||
+			(src_plane->color_t == VP_SRC_COLOR_NV21IW)) ?
+			VP_LINEAR_MODE : VP_2D_TILE_MODE;
+
+	if (s5p_vp_ctrl_private.running)
+		s5p_vp_ctrl_internal_stop();
+	else {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		if (suspend_status) {
+			tvout_dbg("driver is suspend_status\n");
+		} else
+#endif
+		{
+#if defined(CONFIG_BUSFREQ) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)
+			if ((disp == TVOUT_1080P_60) || (disp == TVOUT_1080P_59)
+					|| (disp == TVOUT_1080P_50)) {
+				if (exynos4_busfreq_lock(DVFS_LOCK_ID_TV, BUS_L0))
+					printk(KERN_ERR "%s: failed lock DVFS\n", __func__);
+			}
+#endif
+			s5p_vp_ctrl_clock(1);
+		}
+		s5p_vp_ctrl_private.running = true;
+	}
+	s5p_vp_ctrl_set_reg();
+
+	return 0;
+}
+
+int s5p_vp_ctrl_constructor(struct platform_device *pdev)
+{
+	int ret = 0;
+
+	ret = s5p_tvout_map_resource_mem(
+		pdev,
+		s5p_vp_ctrl_private.reg_mem.name,
+		&(s5p_vp_ctrl_private.reg_mem.base),
+		&(s5p_vp_ctrl_private.reg_mem.res));
+
+	if (ret)
+		goto err_on_res;
+
+	s5p_vp_ctrl_private.clk.ptr =
+		clk_get(&pdev->dev, s5p_vp_ctrl_private.clk.name);
+
+	if (IS_ERR(s5p_vp_ctrl_private.clk.ptr)) {
+		tvout_err("Failed to find clock %s\n",
+			s5p_vp_ctrl_private.clk.name);
+		ret = -ENOENT;
+		goto err_on_clk;
+	}
+
+	s5p_vp_init(s5p_vp_ctrl_private.reg_mem.base);
+	s5p_vp_ctrl_init_private();
+
+	return 0;
+
+err_on_clk:
+	iounmap(s5p_vp_ctrl_private.reg_mem.base);
+	release_resource(s5p_vp_ctrl_private.reg_mem.res);
+	kfree(s5p_vp_ctrl_private.reg_mem.res);
+
+err_on_res:
+	return ret;
+}
+
+void s5p_vp_ctrl_destructor(void)
+{
+	if (s5p_vp_ctrl_private.reg_mem.base)
+		iounmap(s5p_vp_ctrl_private.reg_mem.base);
+
+	if (s5p_vp_ctrl_private.reg_mem.res) {
+		release_resource(s5p_vp_ctrl_private.reg_mem.res);
+		kfree(s5p_vp_ctrl_private.reg_mem.res);
+	}
+
+	if (s5p_vp_ctrl_private.clk.ptr) {
+		if (s5p_vp_ctrl_private.running)
+			clk_disable(s5p_vp_ctrl_private.clk.ptr);
+		clk_put(s5p_vp_ctrl_private.clk.ptr);
+	}
+}
+
+void s5p_vp_ctrl_suspend(void)
+{
+	tvout_dbg("running(%d)\n", s5p_vp_ctrl_private.running);
+	if (s5p_vp_ctrl_private.running) {
+		s5p_vp_stop();
+		s5p_vp_ctrl_clock(0);
+	}
+}
+
+void s5p_vp_ctrl_resume(void)
+{
+	tvout_dbg("running(%d)\n", s5p_vp_ctrl_private.running);
+	if (s5p_vp_ctrl_private.running) {
+		s5p_vp_ctrl_clock(1);
+		s5p_vp_ctrl_set_reg();
+	}
+}
diff --git a/drivers/media/video/samsung/ump/Kconfig b/drivers/media/video/samsung/ump/Kconfig
new file mode 100644
index 0000000..aaae26e
--- /dev/null
+++ b/drivers/media/video/samsung/ump/Kconfig
@@ -0,0 +1,51 @@
+
+#
+## S3C Multimedia Mali configuration
+##
+#
+# For UMP
+config VIDEO_UMP
+	bool "Enable UMP(Unified Memory Provider)"
+	default y
+	---help---
+		This enables UMP memory provider
+
+config UMP_VCM_ALLOC
+	depends on VIDEO_UMP && VCM
+	default y
+        bool "Enable ump-vcm(virtual contiguous memory) memory"
+        help
+          Use VCM(virtual-contiguous-memory) to allocate physical memory.
+
+choice
+depends on VIDEO_UMP
+prompt "UMP MEMEMORY OPTION"
+default UMP_OSMEM_ONLY 
+config UMP_DED_ONLY
+  bool "ump dedicated memory only"
+   ---help---
+       This enables UMP dedicated memory only option
+config UMP_OSMEM_ONLY
+   bool "ump OS memory only"
+   ---help---
+       This enables UMP OS memory only option
+config UMP_VCM_ONLY
+   bool "ump VCM memory"
+   ---help---
+       This enables UMP VCM memory only option
+
+endchoice
+config UMP_MEM_SIZE
+int "UMP Memory Size"
+   depends on VIDEO_UMP 
+   default "512"
+   ---help---
+       This value is dedicated memory size of UMP (unit is MByte).
+# For UMP_DEBUG
+config VIDEO_UMP_DEBUG
+	bool "Enables debug messages"
+	depends on VIDEO_UMP
+	default n
+	help
+	  This enables UMP driver debug messages.
+
diff --git a/drivers/media/video/samsung/ump/Makefile b/drivers/media/video/samsung/ump/Makefile
new file mode 100644
index 0000000..f429c40
--- /dev/null
+++ b/drivers/media/video/samsung/ump/Makefile
@@ -0,0 +1,94 @@
+#
+# Copyright (C) 2010 ARM Limited. All rights reserved.
+# 
+# This program is free software and is provided to you under the terms of the GNU General Public License version 2
+# as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+# 
+# A copy of the licence is included with the program, and can also be obtained from Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+
+ifeq ($(CONFIG_UMP_DED_ONLY),y)
+UMP_MEM_SIZE= $(CONFIG_UMP_MEM_SIZE)
+USING_MEMORY=0
+endif
+
+ifeq ($(CONFIG_UMP_OSMEM_ONLY),y)
+UMP_MEM_SIZE= $(CONFIG_UMP_MEM_SIZE)
+USING_MEMORY=1
+endif
+
+ifeq ($(CONFIG_UMP_VCM_ONLY),y)
+UMP_MEM_SIZE= $(CONFIG_UMP_MEM_SIZE)
+USING_MEMORY=2
+endif
+
+
+# For UMP Debug
+ifeq ($(CONFIG_VIDEO_UMP_DEBUG),y)
+DEFINES += -DDEBUG
+endif
+
+# Set up our defines, which will be passed to gcc
+DEFINES += -DKERNEL_BUILTIN=1
+DEFINES += -DMALI_USE_UNIFIED_MEMORY_PROVIDER
+DEFINES += -DUSING_MEMORY=$(USING_MEMORY)
+DEFINES += -DUMP_MEM_SIZE=$(UMP_MEM_SIZE)
+DEFINES += -DMALI_STATE_TRACKING=1
+
+UDD_FILE_PREFIX := drivers/media/video/samsung/ump/
+KBUILDROOT = 
+
+# linux build system integration
+
+obj-$(CONFIG_VIDEO_UMP)	+= ump.o
+
+# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
+# The ARM proprietary product will only include the license/proprietary directory
+# The GPL product will only include the license/gpl directory
+
+INCLUDES += \
+		-I$(UDD_FILE_PREFIX)\
+		-I$(UDD_FILE_PREFIX)common\
+		-I$(UDD_FILE_PREFIX)linux\
+		-I$(UDD_FILE_PREFIX)include\
+		-I$(UDD_FILE_PREFIX)linux/license/gpl/\
+		-I$(UDD_FILE_PREFIX)../mali/common\
+		-I$(UDD_FILE_PREFIX)../mali/linux
+
+OSKFILES+=\
+		$(KBUILDROOT)../mali/linux/mali_osk_atomics.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_locks.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_math.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_memory.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_misc.o 
+
+ump-y := \
+		$(KBUILDROOT)linux/ump_kernel_linux.o \
+		$(KBUILDROOT)linux/ump_kernel_memory_backend_os.o \
+		$(KBUILDROOT)linux/ump_kernel_memory_backend_dedicated.o \
+		$(KBUILDROOT)linux/ump_memory_backend.o \
+		$(KBUILDROOT)linux/ump_ukk_wrappers.o \
+		$(KBUILDROOT)linux/ump_ukk_ref_wrappers.o \
+		$(KBUILDROOT)linux/ump_osk_atomics.o \
+		$(KBUILDROOT)linux/ump_osk_low_level_mem.o \
+		$(KBUILDROOT)linux/ump_osk_misc.o \
+		$(KBUILDROOT)common/ump_kernel_common.o \
+		$(KBUILDROOT)common/ump_kernel_descriptor_mapping.o \
+		$(KBUILDROOT)common/ump_kernel_api.o \
+		$(KBUILDROOT)common/ump_kernel_ref_drv.o\
+		$(OSKFILES)
+
+ump-$(CONFIG_UMP_VCM_ALLOC) += \
+                $(KBUILDROOT)linux/ump_kernel_memory_backend_vcm.o \
+
+EXTRA_CFLAGS += $(INCLUDES) \
+		$(DEFINES) 
+		
+		
+# Get subversion revision number, fall back to 0000 if no svn info is available
+SVN_REV:=$(shell ((svnversion | grep -qv exported && echo -n 'Revision: ' && svnversion) || git svn info | sed -e 's/$$$$/M/' | grep '^Revision: ' || echo ${MALI_RELEASE_NAME}) 2>/dev/null | sed -e 's/^Revision: //')
+		
+EXTRA_CFLAGS += -DSVN_REV=$(SVN_REV)
+EXTRA_CFLAGS += -DSVN_REV_STRING=\"$(SVN_REV)\"
+		 
diff --git a/drivers/media/video/samsung/ump/Makefile.common b/drivers/media/video/samsung/ump/Makefile.common
new file mode 100644
index 0000000..4b5db24
--- /dev/null
+++ b/drivers/media/video/samsung/ump/Makefile.common
@@ -0,0 +1,17 @@
+#
+# Copyright (C) 2010 ARM Limited. All rights reserved.
+# 
+# This program is free software and is provided to you under the terms of the GNU General Public License version 2
+# as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+# 
+# A copy of the licence is included with the program, and can also be obtained from Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+
+UMP_FILE_PREFIX = ./drivers/video/samsung/ump
+
+SRC = 	$(UMP_FILE_PREFIX)/common/ump_kernel_common.c \
+	$(UMP_FILE_PREFIX)/common/ump_kernel_descriptor_mapping.c \
+	$(UMP_FILE_PREFIX)/common/ump_kernel_api.c \
+	$(UMP_FILE_PREFIX)/common/ump_kernel_ref_drv.c
+
diff --git a/drivers/media/video/samsung/ump/Makefile_backup b/drivers/media/video/samsung/ump/Makefile_backup
new file mode 100644
index 0000000..632cb0c
--- /dev/null
+++ b/drivers/media/video/samsung/ump/Makefile_backup
@@ -0,0 +1,80 @@
+#
+# Copyright (C) 2010 ARM Limited. All rights reserved.
+# 
+# This program is free software and is provided to you under the terms of the GNU General Public License version 2
+# as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+# 
+# A copy of the licence is included with the program, and can also be obtained from Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+BUILD		?= debug 
+USING_MALI400	?= 1 
+USING_ZBT	?= 0 
+USING_MMU	?= 1 
+USING_UMP	?= 1 
+CPU		?= vega1 
+CONFIG		?= marcopolo-vega1-m400
+
+
+# Set up our defines, which will be passed to gcc
+DEFINES += -DUSING_MALI400=$(USING_MALI400)
+DEFINES += -DUSING_ZBT=$(USING_ZBT)
+DEFINES += -DUSING_MMU=$(USING_MMU)
+DEFINES += -DUSING_UMP=$(USING_UMP)
+DEFINES += -DMALI_USE_UNIFIED_MEMORY_PROVIDER
+ifeq ($(BUILD), debug)
+DEFINES += -DDEBUG
+endif
+
+
+UMP_FILE_PREFIX := drivers/video/samsung/ump
+UDD_FILE_PREFIX := drivers/video/samsung/mali
+KBUILDROOT = 
+
+# linux build system integration
+
+obj-y += ump.o
+
+# For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
+# The ARM proprietary product will only include the license/proprietary directory
+# The GPL product will only include the license/gpl directory
+
+INCLUDES = \
+		-I$(UMP_FILE_PREFIX)\
+		-I$(UMP_FILE_PREFIX)/common\
+		-I$(UMP_FILE_PREFIX)/linux\
+		-I$(UMP_FILE_PREFIX)/include\
+		-I$(UMP_FILE_PREFIX)/linux/license/proprietary/\
+		-I$(UDD_FILE_PREFIX)/common\
+		-I$(UDD_FILE_PREFIX)/linux
+
+ump-y := \
+		$(KBUILDROOT)linux/ump_kernel_linux.o \
+		$(KBUILDROOT)linux/ump_kernel_memory_backend_os.o \
+		$(KBUILDROOT)linux/ump_kernel_memory_backend_dedicated.o \
+		$(KBUILDROOT)linux/ump_memory_backend.o \
+		$(KBUILDROOT)linux/ump_ukk_wrappers.o \
+		$(KBUILDROOT)linux/ump_ukk_ref_wrappers.o \
+		$(KBUILDROOT)linux/ump_osk_atomics.o \
+		$(KBUILDROOT)linux/ump_osk_low_level_mem.o \
+		$(KBUILDROOT)linux/ump_osk_misc.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_atomics.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_locks.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_memory.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_math.o \
+		$(KBUILDROOT)../mali/linux/mali_osk_misc.o \
+		$(KBUILDROOT)common/ump_kernel_common.o \
+		$(KBUILDROOT)common/ump_kernel_descriptor_mapping.o \
+		$(KBUILDROOT)common/ump_kernel_api.o \
+		$(KBUILDROOT)common/ump_kernel_ref_drv.o
+
+EXTRA_CFLAGS += $(INCLUDES) \
+		$(DEFINES) 
+		
+		
+# Get subversion revision number, fall back to 0000 if no svn info is available
+SVN_REV:=$(shell ((svnversion | grep -qv exported && echo -n 'Revision: ' && svnversion) || git svn info | sed -e 's/$$$$/M/' | grep '^Revision: ' || echo ${MALI_RELEASE_NAME}) 2>/dev/null | sed -e 's/^Revision: //')
+		
+EXTRA_CFLAGS += -DSVN_REV=$(SVN_REV)
+EXTRA_CFLAGS += -DSVN_REV_STRING=\"$(SVN_REV)\"
+		 
diff --git a/drivers/media/video/samsung/ump/arch b/drivers/media/video/samsung/ump/arch
new file mode 120000
index 0000000..a65a3fc
--- /dev/null
+++ b/drivers/media/video/samsung/ump/arch
@@ -0,0 +1 @@
+./arch-orion-m400
\ No newline at end of file
diff --git a/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h b/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h
new file mode 100644
index 0000000..014c4bb
--- /dev/null
+++ b/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARCH_CONFIG_H__
+#define __ARCH_CONFIG_H__
+
+#define ARCH_UMP_BACKEND_DEFAULT          0
+#define ARCH_UMP_MEMORY_ADDRESS_DEFAULT   0x2C000000
+#define ARCH_UMP_MEMORY_SIZE_DEFAULT 0x04000000
+
+#endif /* __ARCH_CONFIG_H__ */
diff --git a/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h.org b/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h.org
new file mode 100755
index 0000000..c92a32a
--- /dev/null
+++ b/drivers/media/video/samsung/ump/arch-marcopolo-vega1-m400/config.h.org
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARCH_CONFIG_H__
+#define __ARCH_CONFIG_H__
+
+/* Configuration for the EB platform with ZBT memory enabled */
+#define MALI_BASE_ADDR 0xf0000000
+#define GP_ADDR MALI_BASE_ADDR
+#define L2_ADDR MALI_BASE_ADDR+0x1000
+#define PMU_ADDR MALI_BASE_ADDR+0x2000
+#define GP_MMU_ADDR MALI_BASE_ADDR+0x3000
+#define PP_MMU_ADDR MALI_BASE_ADDR+0x4000
+#define PP_ADDR MALI_BASE_ADDR+0x8000
+
+// See 3-11 page in trm. It describes control register address map. cglee
+
+static _mali_osk_resource_t arch_configuration [] =
+{
+	{
+		.type = MALI400GP,
+		.description = "Mali-400 GP",
+		.base = GP_ADDR,
+		.irq = 18+32,
+		.mmu_id = 1
+	},
+	{
+		.type = MALI400PP,
+		.base = PP_ADDR,
+		.irq = 16+32,
+		.description = "Mali-400 PP 0",
+		.mmu_id = 2
+	},
+#if USING_MMU
+	{
+		.type = MMU,
+		.base = GP_MMU_ADDR,
+		.irq = 19+32,
+		.description = "Mali-400 MMU for GP",
+		.mmu_id = 1
+	},
+	{
+		.type = MMU,
+		.base = PP_MMU_ADDR,
+		.irq = 17+32,
+		.description = "Mali-400 MMU for PP 0",
+		.mmu_id = 2
+	},
+	{
+		.type = OS_MEMORY,
+		.description = "System Memory",
+		.size = 0x06000000,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE
+	},
+	{
+		.type = MEM_VALIDATION,
+		.description = "memory validation",
+		.base = 0x204e0000,
+		.size = 0x7B20000,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE |
+			_MALI_MMU_READABLE | _MALI_MMU_WRITEABLE
+	},
+#else
+	{
+		.type = MEMORY,
+		.description = "Dedicated Memory",
+		.base = 0x2E000000,
+		.size = 0x02000000,
+		.flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE |
+			_MALI_MMU_READABLE | _MALI_MMU_WRITEABLE
+	},
+#endif
+	{
+		.type = MALI400L2,
+		.base = L2_ADDR,
+		.description = "Mali-400 L2 cache"
+	},
+};
+
+#endif /* __ARCH_CONFIG_H__ */
diff --git a/drivers/media/video/samsung/ump/arch-orion-m400/config.h b/drivers/media/video/samsung/ump/arch-orion-m400/config.h
new file mode 100644
index 0000000..117cc6e
--- /dev/null
+++ b/drivers/media/video/samsung/ump/arch-orion-m400/config.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARCH_CONFIG_UMP_H__
+#define __ARCH_CONFIG_UMP_H__
+
+#define ARCH_UMP_BACKEND_DEFAULT          	USING_MEMORY
+#if (USING_MEMORY == 0) /* Dedicated Memory */
+#define ARCH_UMP_MEMORY_ADDRESS_DEFAULT   	0x2C000000
+#else
+#define ARCH_UMP_MEMORY_ADDRESS_DEFAULT   	0
+#endif
+
+#define ARCH_UMP_MEMORY_SIZE_DEFAULT 		UMP_MEM_SIZE*1024*1024
+#endif /* __ARCH_CONFIG_UMP_H__ */
diff --git a/drivers/media/video/samsung/ump/arch-pb-virtex5/config.h b/drivers/media/video/samsung/ump/arch-pb-virtex5/config.h
new file mode 100644
index 0000000..560eda9
--- /dev/null
+++ b/drivers/media/video/samsung/ump/arch-pb-virtex5/config.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARCH_CONFIG_H__
+#define __ARCH_CONFIG_H__
+
+#define ARCH_UMP_BACKEND_DEFAULT          0
+#define ARCH_UMP_MEMORY_ADDRESS_DEFAULT   0xC8000000
+#define ARCH_UMP_MEMORY_SIZE_DEFAULT 32UL * 1024UL * 1024UL
+
+#endif /* __ARCH_CONFIG_H__ */
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_api.c b/drivers/media/video/samsung/ump/common/ump_kernel_api.c
new file mode 100644
index 0000000..ddc9ef7
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_api.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_osk.h"
+#include "mali_osk_list.h"
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+#include "ump_kernel_interface.h"
+#include "ump_kernel_common.h"
+
+
+
+/* ---------------- UMP kernel space API functions follows ---------------- */
+
+
+
+UMP_KERNEL_API_EXPORT ump_secure_id ump_dd_secure_id_get(ump_dd_handle memh)
+{
+	ump_dd_mem * mem = (ump_dd_mem *)memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	DBG_MSG(5, ("Returning secure ID. ID: %u\n", mem->secure_id));
+
+	return mem->secure_id;
+}
+
+
+
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_create_from_secure_id(ump_secure_id secure_id)
+{
+	ump_dd_mem * mem;
+
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	DBG_MSG(5, ("Getting handle from secure ID. ID: %u\n", secure_id));
+	if (0 != ump_descriptor_mapping_get(device.secure_id_map, (int)secure_id, (void**)&mem))
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		DBG_MSG(1, ("Secure ID not found. ID: %u\n", secure_id));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	ump_dd_reference_add(mem);
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	return (ump_dd_handle)mem;
+}
+
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_get(ump_secure_id secure_id)
+{
+	ump_dd_mem * mem;
+
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	DBG_MSG(5, ("Getting handle from secure ID. ID: %u\n", secure_id));
+	if (0 != ump_descriptor_mapping_get(device.secure_id_map, (int)secure_id, (void**)&mem))
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		DBG_MSG(1, ("Secure ID not found. ID: %u\n", secure_id));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	return (ump_dd_handle)mem;
+}
+
+UMP_KERNEL_API_EXPORT unsigned long ump_dd_phys_block_count_get(ump_dd_handle memh)
+{
+	ump_dd_mem * mem = (ump_dd_mem*) memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	return mem->nr_blocks;
+}
+
+
+
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_phys_blocks_get(ump_dd_handle memh, ump_dd_physical_block * blocks, unsigned long num_blocks)
+{
+	ump_dd_mem * mem = (ump_dd_mem *)memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	if (blocks == NULL)
+	{
+		DBG_MSG(1, ("NULL parameter in ump_dd_phys_blocks_get()\n"));
+		return UMP_DD_INVALID;
+	}
+
+	if (mem->nr_blocks != num_blocks)
+	{
+		DBG_MSG(1, ("Specified number of blocks do not match actual number of blocks\n"));
+		return UMP_DD_INVALID;
+	}
+
+	DBG_MSG(5, ("Returning physical block information. ID: %u\n", mem->secure_id));
+
+	_mali_osk_memcpy(blocks, mem->block_array, sizeof(ump_dd_physical_block) * mem->nr_blocks);
+
+	return UMP_DD_SUCCESS;
+}
+
+
+
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_phys_block_get(ump_dd_handle memh, unsigned long index, ump_dd_physical_block * block)
+{
+	ump_dd_mem * mem = (ump_dd_mem *)memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	if (block == NULL)
+	{
+		DBG_MSG(1, ("NULL parameter in ump_dd_phys_block_get()\n"));
+		return UMP_DD_INVALID;
+	}
+
+	if (index >= mem->nr_blocks)
+	{
+		DBG_MSG(5, ("Invalid index specified in ump_dd_phys_block_get()\n"));
+		return UMP_DD_INVALID;
+	}
+
+	DBG_MSG(5, ("Returning physical block information. ID: %u, index: %lu\n", mem->secure_id, index));
+
+	*block = mem->block_array[index];
+
+	return UMP_DD_SUCCESS;
+}
+
+
+
+UMP_KERNEL_API_EXPORT unsigned long ump_dd_size_get(ump_dd_handle memh)
+{
+	ump_dd_mem * mem = (ump_dd_mem*)memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	DBG_MSG(5, ("Returning size. ID: %u, size: %lu\n", mem->secure_id, mem->size_bytes));
+
+	return mem->size_bytes;
+}
+
+
+
+UMP_KERNEL_API_EXPORT void ump_dd_reference_add(ump_dd_handle memh)
+{
+	ump_dd_mem * mem = (ump_dd_mem*)memh;
+	int new_ref;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	new_ref = _ump_osk_atomic_inc_and_read(&mem->ref_count);
+
+	DBG_MSG(4, ("Memory reference incremented. ID: %u, new value: %d\n", mem->secure_id, new_ref));
+}
+
+
+
+UMP_KERNEL_API_EXPORT void ump_dd_reference_release(ump_dd_handle memh)
+{
+	int new_ref;
+	ump_dd_mem * mem = (ump_dd_mem*)memh;
+
+	DEBUG_ASSERT_POINTER(mem);
+
+	/* We must hold this mutex while doing the atomic_dec_and_read, to protect
+	that elements in the ump_descriptor_mapping table is always valid.  If they
+	are not, userspace may accidently map in this secure_ids right before its freed
+	giving a mapped backdoor into unallocated memory.*/
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	new_ref = _ump_osk_atomic_dec_and_read(&mem->ref_count);
+
+	DBG_MSG(4, ("Memory reference decremented. ID: %u, new value: %d\n", mem->secure_id, new_ref));
+
+	if (0 == new_ref)
+	{
+		DBG_MSG(3, ("Final release of memory. ID: %u\n", mem->secure_id));
+
+		ump_descriptor_mapping_free(device.secure_id_map, (int)mem->secure_id);
+
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		mem->release_func(mem->ctx, mem);
+		_mali_osk_free(mem);
+	}
+	else
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	}
+}
+
+
+
+/* --------------- Handling of user space requests follows --------------- */
+
+
+_mali_osk_errcode_t _ump_uku_get_api_version( _ump_uk_api_version_s *args )
+{
+	ump_session_data * session_data;
+
+	DEBUG_ASSERT_POINTER( args );
+	DEBUG_ASSERT_POINTER( args->ctx );
+
+	session_data = (ump_session_data *)args->ctx;
+
+	/* check compatability */
+	if (args->version == UMP_IOCTL_API_VERSION)
+	{
+		DBG_MSG(3, ("API version set to newest %d (compatible)\n", GET_VERSION(args->version)));
+		args->compatible = 1;
+		session_data->api_version = args->version;
+	}
+	else if (args->version == MAKE_VERSION_ID(1))
+	{
+		DBG_MSG(2, ("API version set to depricated: %d (compatible)\n", GET_VERSION(args->version)));
+		args->compatible = 1;
+		session_data->api_version = args->version;
+	}
+	else
+	{
+		DBG_MSG(2, ("API version set to %d (incompatible with client version %d)\n", GET_VERSION(UMP_IOCTL_API_VERSION), GET_VERSION(args->version)));
+		args->compatible = 0;
+		args->version = UMP_IOCTL_API_VERSION; /* report our version */
+	}
+
+	return _MALI_OSK_ERR_OK;
+}
+
+
+_mali_osk_errcode_t _ump_ukk_release( _ump_uk_release_s *release_info )
+{
+	ump_session_memory_list_element * session_memory_element;
+	ump_session_memory_list_element * tmp;
+	ump_session_data * session_data;
+	_mali_osk_errcode_t ret = _MALI_OSK_ERR_INVALID_FUNC;
+	int secure_id;
+
+	DEBUG_ASSERT_POINTER( release_info );
+	DEBUG_ASSERT_POINTER( release_info->ctx );
+
+	/* Retreive the session data */
+	session_data = (ump_session_data*)release_info->ctx;
+
+	/* If there are many items in the memory session list we
+	 * could be de-referencing this pointer a lot so keep a local copy
+	 */
+	secure_id = release_info->secure_id;
+
+	DBG_MSG(4, ("Releasing memory with IOCTL, ID: %u\n", secure_id));
+
+	/* Iterate through the memory list looking for the requested secure ID */
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_MALI_OSK_LIST_FOREACHENTRY(session_memory_element, tmp, &session_data->list_head_session_memory_list, ump_session_memory_list_element, list)
+	{
+		if ( session_memory_element->mem->secure_id == secure_id)
+		{
+			ump_dd_mem *release_mem;
+
+			release_mem = session_memory_element->mem;
+			_mali_osk_list_del(&session_memory_element->list);
+			ump_dd_reference_release(release_mem);
+			_mali_osk_free(session_memory_element);
+
+			ret = _MALI_OSK_ERR_OK;
+			break;
+		}
+	}
+
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+ 	DBG_MSG_IF(1, _MALI_OSK_ERR_OK != ret, ("UMP memory with ID %u does not belong to this session.\n", secure_id));
+
+	DBG_MSG(4, ("_ump_ukk_release() returning 0x%x\n", ret));
+	return ret;
+}
+
+_mali_osk_errcode_t _ump_ukk_size_get( _ump_uk_size_get_s *user_interaction )
+{
+	ump_dd_mem * mem;
+	_mali_osk_errcode_t ret = _MALI_OSK_ERR_FAULT;
+
+	DEBUG_ASSERT_POINTER( user_interaction );
+
+	/* We lock the mappings so things don't get removed while we are looking for the memory */
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	if (0 == ump_descriptor_mapping_get(device.secure_id_map, (int)user_interaction->secure_id, (void**)&mem))
+	{
+		user_interaction->size = mem->size_bytes;
+		DBG_MSG(4, ("Returning size. ID: %u, size: %lu ", (ump_secure_id)user_interaction->secure_id, (unsigned long)user_interaction->size));
+		ret = _MALI_OSK_ERR_OK;
+	}
+	else
+	{
+		 user_interaction->size = 0;
+		DBG_MSG(1, ("Failed to look up mapping in ump_ioctl_size_get(). ID: %u\n", (ump_secure_id)user_interaction->secure_id));
+	}
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	return ret;
+}
+
+
+
+void _ump_ukk_msync( _ump_uk_msync_s *args )
+{
+	ump_dd_mem * mem = NULL;
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	ump_descriptor_mapping_get(device.secure_id_map, (int)args->secure_id, (void**)&mem);
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	if (NULL==mem)
+	{
+		DBG_MSG(1, ("Failed to look up mapping in _ump_ukk_msync(). ID: %u\n", (ump_secure_id)args->secure_id));
+		return;
+	}
+
+	/* Returns the cache settings back to Userspace */
+	args->is_cached=mem->is_cached;
+
+	/* If this flag is the only one set, we should not do the actual flush, only the readout */
+	if ( _UMP_UK_MSYNC_READOUT_CACHE_ENABLED==args->op )
+	{
+		DBG_MSG(3, ("_ump_ukk_msync READOUT  ID: %u Enabled: %d\n", (ump_secure_id)args->secure_id, mem->is_cached));
+		return;
+	}
+
+	/* Nothing to do if the memory is not caches */
+	if ( 0==mem->is_cached )
+	{
+		DBG_MSG(3, ("_ump_ukk_msync IGNORING ID: %u Enabled: %d  OP: %d\n", (ump_secure_id)args->secure_id, mem->is_cached, args->op));
+		return ;
+	}
+	DBG_MSG(3, ("_ump_ukk_msync FLUSHING ID: %u Enabled: %d  OP: %d\n", (ump_secure_id)args->secure_id, mem->is_cached, args->op));
+
+	/* The actual cache flush - Implemented for each OS*/
+	_ump_osk_msync( mem , args->op, (u32)args->mapping, (u32)args->address, args->size);
+}
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_common.c b/drivers/media/video/samsung/ump/common/ump_kernel_common.c
new file mode 100644
index 0000000..e5ff198
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_common.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_osk_bitops.h"
+#include "mali_osk_list.h"
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+#include "ump_ukk.h"
+#include "ump_kernel_common.h"
+#include "ump_kernel_descriptor_mapping.h"
+#include "ump_kernel_memory_backend.h"
+
+
+
+/**
+ * Define the initial and maximum size of number of secure_ids on the system
+ */
+#define UMP_SECURE_ID_TABLE_ENTRIES_INITIAL (128  )
+#define UMP_SECURE_ID_TABLE_ENTRIES_MAXIMUM (4096 )
+
+
+/**
+ * Define the initial and maximum size of the ump_session_data::cookies_map,
+ * which is a \ref ump_descriptor_mapping. This limits how many secure_ids
+ * may be mapped into a particular process using _ump_ukk_map_mem().
+ */
+
+#define UMP_COOKIES_PER_SESSION_INITIAL (UMP_SECURE_ID_TABLE_ENTRIES_INITIAL )
+#define UMP_COOKIES_PER_SESSION_MAXIMUM (UMP_SECURE_ID_TABLE_ENTRIES_MAXIMUM)
+
+struct ump_dev device;
+
+_mali_osk_errcode_t ump_kernel_constructor(void)
+{
+	_mali_osk_errcode_t err;
+
+	/* Perform OS Specific initialization */
+	err = _ump_osk_init();
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MSG_ERR(("Failed to initiaze the UMP Device Driver"));
+		return err;
+	}
+
+	/* Init the global device */
+	_mali_osk_memset(&device, 0, sizeof(device) );
+
+	/* Create the descriptor map, which will be used for mapping secure ID to ump_dd_mem structs */
+	device.secure_id_map_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0 , 0);
+	if (NULL == device.secure_id_map_lock)
+	{
+		MSG_ERR(("Failed to create OSK lock for secure id lookup table\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	device.secure_id_map = ump_descriptor_mapping_create(UMP_SECURE_ID_TABLE_ENTRIES_INITIAL, UMP_SECURE_ID_TABLE_ENTRIES_MAXIMUM);
+	if (NULL == device.secure_id_map)
+	{
+		_mali_osk_lock_term(device.secure_id_map_lock);
+		MSG_ERR(("Failed to create secure id lookup table\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	/* Init memory backend */
+	device.backend = ump_memory_backend_create();
+	if (NULL == device.backend)
+	{
+		MSG_ERR(("Failed to create memory backend\n"));
+		_mali_osk_lock_term(device.secure_id_map_lock);
+		ump_descriptor_mapping_destroy(device.secure_id_map);
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void ump_kernel_destructor(void)
+{
+	DEBUG_ASSERT_POINTER(device.secure_id_map);
+	DEBUG_ASSERT_POINTER(device.secure_id_map_lock);
+
+	_mali_osk_lock_term(device.secure_id_map_lock);
+	device.secure_id_map_lock = NULL;
+
+	ump_descriptor_mapping_destroy(device.secure_id_map);
+	device.secure_id_map = NULL;
+
+	device.backend->shutdown(device.backend);
+	device.backend = NULL;
+
+	ump_memory_backend_destroy();
+
+	_ump_osk_term();
+}
+
+/** Creates a new UMP session
+ */
+_mali_osk_errcode_t _ump_ukk_open( void** context )
+{
+	struct ump_session_data * session_data;
+
+	/* allocated struct to track this session */
+	session_data = (struct ump_session_data *)_mali_osk_malloc(sizeof(struct ump_session_data));
+	if (NULL == session_data)
+	{
+		MSG_ERR(("Failed to allocate ump_session_data in ump_file_open()\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	session_data->lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE, 0, 0);
+	if( NULL == session_data->lock )
+	{
+		MSG_ERR(("Failed to initialize lock for ump_session_data in ump_file_open()\n"));
+		_mali_osk_free(session_data);
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	session_data->cookies_map = ump_descriptor_mapping_create( UMP_COOKIES_PER_SESSION_INITIAL, UMP_COOKIES_PER_SESSION_MAXIMUM );
+
+	if ( NULL == session_data->cookies_map )
+	{
+		MSG_ERR(("Failed to create descriptor mapping for _ump_ukk_map_mem cookies\n"));
+
+		_mali_osk_lock_term( session_data->lock );
+		_mali_osk_free( session_data );
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	_MALI_OSK_INIT_LIST_HEAD(&session_data->list_head_session_memory_list);
+
+	_MALI_OSK_INIT_LIST_HEAD(&session_data->list_head_session_memory_mappings_list);
+
+	/* Since initial version of the UMP interface did not use the API_VERSION ioctl we have to assume
+	   that it is this version, and not the "latest" one: UMP_IOCTL_API_VERSION
+	   Current and later API versions would do an additional call to this IOCTL and update this variable
+	   to the correct one.*/
+	session_data->api_version = MAKE_VERSION_ID(1);
+
+	*context = (void*)session_data;
+
+	DBG_MSG(2, ("New session opened\n"));
+
+	return _MALI_OSK_ERR_OK;
+}
+
+_mali_osk_errcode_t _ump_ukk_close( void** context )
+{
+	struct ump_session_data * session_data;
+	ump_session_memory_list_element * item;
+	ump_session_memory_list_element * tmp;
+
+	session_data = (struct ump_session_data *)*context;
+	if (NULL == session_data)
+	{
+		MSG_ERR(("Session data is NULL in _ump_ukk_close()\n"));
+		return _MALI_OSK_ERR_INVALID_ARGS;
+	}
+
+	/* Unmap any descriptors mapped in. */
+	if (0 == _mali_osk_list_empty(&session_data->list_head_session_memory_mappings_list))
+	{
+		ump_memory_allocation *descriptor;
+		ump_memory_allocation *temp;
+
+		DBG_MSG(1, ("Memory mappings found on session usage list during session termination\n"));
+
+		/* use the 'safe' list iterator, since freeing removes the active block from the list we're iterating */
+		_MALI_OSK_LIST_FOREACHENTRY(descriptor, temp, &session_data->list_head_session_memory_mappings_list, ump_memory_allocation, list)
+		{
+			_ump_uk_unmap_mem_s unmap_args;
+			DBG_MSG(4, ("Freeing block with phys address 0x%x size 0x%x mapped in user space at 0x%x\n",
+			            descriptor->phys_addr, descriptor->size, descriptor->mapping));
+			unmap_args.ctx = (void*)session_data;
+			unmap_args.mapping = descriptor->mapping;
+			unmap_args.size = descriptor->size;
+			unmap_args._ukk_private = NULL; /* NOTE: unused */
+			unmap_args.cookie = descriptor->cookie;
+
+			/* NOTE: This modifies the list_head_session_memory_mappings_list */
+			_ump_ukk_unmap_mem( &unmap_args );
+		}
+	}
+
+	/* ASSERT that we really did free everything, because _ump_ukk_unmap_mem()
+	 * can fail silently. */
+	DEBUG_ASSERT( _mali_osk_list_empty(&session_data->list_head_session_memory_mappings_list) );
+
+	_MALI_OSK_LIST_FOREACHENTRY(item, tmp, &session_data->list_head_session_memory_list, ump_session_memory_list_element, list)
+	{
+		_mali_osk_list_del(&item->list);
+		DBG_MSG(2, ("Releasing UMP memory %u as part of file close\n", item->mem->secure_id));
+		ump_dd_reference_release(item->mem);
+		_mali_osk_free(item);
+	}
+
+	ump_descriptor_mapping_destroy( session_data->cookies_map );
+
+	_mali_osk_lock_term(session_data->lock);
+	_mali_osk_free(session_data);
+
+	DBG_MSG(2, ("Session closed\n"));
+
+	return _MALI_OSK_ERR_OK;
+}
+
+_mali_osk_errcode_t _ump_ukk_map_mem( _ump_uk_map_mem_s *args )
+{
+	struct ump_session_data * session_data;
+	ump_memory_allocation * descriptor;  /* Describes current mapping of memory */
+	_mali_osk_errcode_t err;
+	unsigned long offset = 0;
+	unsigned long left;
+	ump_dd_handle handle;  /* The real UMP handle for this memory. Its real datatype is ump_dd_mem*  */
+	ump_dd_mem * mem;      /* The real UMP memory. It is equal to the handle, but with exposed struct */
+	u32 block;
+	int map_id;
+
+	session_data = (ump_session_data *)args->ctx;
+	if (NULL == session_data)
+	{
+		MSG_ERR(("Session data is NULL in _ump_ukk_map_mem()\n"));
+		return _MALI_OSK_ERR_INVALID_ARGS;
+	}
+
+	/* SEC kernel stability 2012-02-17 */
+	if (NULL == session_data->cookies_map)
+	{
+		MSG_ERR(("session_data->cookies_map is NULL in _ump_ukk_map_mem()\n"));
+		return _MALI_OSK_ERR_INVALID_ARGS;
+	}
+
+	descriptor = (ump_memory_allocation*) _mali_osk_calloc( 1, sizeof(ump_memory_allocation));
+	if (NULL == descriptor)
+	{
+		MSG_ERR(("ump_ukk_map_mem: descriptor allocation failed\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	handle = ump_dd_handle_create_from_secure_id(args->secure_id);
+	if ( UMP_DD_HANDLE_INVALID == handle)
+	{
+		_mali_osk_free(descriptor);
+		DBG_MSG(1, ("Trying to map unknown secure ID %u\n", args->secure_id));
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	mem = (ump_dd_mem*)handle;
+	DEBUG_ASSERT(mem);
+	if (mem->size_bytes != args->size)
+	{
+		_mali_osk_free(descriptor);
+		ump_dd_reference_release(handle);
+		DBG_MSG(1, ("Trying to map too much or little. ID: %u, virtual size=%lu, UMP size: %lu\n", args->secure_id, args->size, mem->size_bytes));
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	map_id = ump_descriptor_mapping_allocate_mapping( session_data->cookies_map, (void*) descriptor );
+
+	if (map_id < 0)
+	{
+		_mali_osk_free(descriptor);
+		ump_dd_reference_release(handle);
+		DBG_MSG(1, ("ump_ukk_map_mem: unable to allocate a descriptor_mapping for return cookie\n"));
+
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	descriptor->size = args->size;
+	descriptor->handle = handle;
+	descriptor->phys_addr = args->phys_addr;
+	descriptor->process_mapping_info = args->_ukk_private;
+	descriptor->ump_session = session_data;
+	descriptor->cookie = (u32)map_id;
+
+	if ( mem->is_cached )
+	{
+		descriptor->is_cached = 1;
+		args->is_cached       = 1;
+		DBG_MSG(3, ("Mapping UMP secure_id: %d as cached.\n", args->secure_id));
+	}
+	else if ( args->is_cached)
+	{
+		mem->is_cached = 1;
+		descriptor->is_cached = 1;
+		DBG_MSG(3, ("Warning mapping UMP secure_id: %d. As cached, while it was allocated uncached.\n", args->secure_id));
+	}
+	else
+	{
+		descriptor->is_cached = 0;
+		args->is_cached       = 0;
+		DBG_MSG(3, ("Mapping UMP secure_id: %d  as Uncached.\n", args->secure_id));
+	}
+
+	_mali_osk_list_init( &descriptor->list );
+
+	err = _ump_osk_mem_mapregion_init( descriptor );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		DBG_MSG(1, ("Failed to initialize memory mapping in _ump_ukk_map_mem(). ID: %u\n", args->secure_id));
+		ump_descriptor_mapping_free( session_data->cookies_map, map_id );
+		_mali_osk_free(descriptor);
+		ump_dd_reference_release(mem);
+		return err;
+	}
+
+	DBG_MSG(4, ("Mapping virtual to physical memory: ID: %u, size:%lu, first physical addr: 0x%08lx, number of regions: %lu\n",
+	        mem->secure_id,
+	        mem->size_bytes,
+	        ((NULL != mem->block_array) ? mem->block_array->addr : 0),
+	        mem->nr_blocks));
+
+	left = descriptor->size;
+	/* loop over all blocks and map them in */
+	for (block = 0; block < mem->nr_blocks; block++)
+	{
+		unsigned long size_to_map;
+
+		if (left >  mem->block_array[block].size)
+		{
+			size_to_map = mem->block_array[block].size;
+		}
+		else
+		{
+			size_to_map = left;
+		}
+
+		if (_MALI_OSK_ERR_OK != _ump_osk_mem_mapregion_map(descriptor, offset, (u32 *)&(mem->block_array[block].addr), size_to_map ) )
+		{
+			DBG_MSG(1, ("WARNING: _ump_ukk_map_mem failed to map memory into userspace\n"));
+			ump_descriptor_mapping_free( session_data->cookies_map, map_id );
+			ump_dd_reference_release(mem);
+			_ump_osk_mem_mapregion_term( descriptor );
+			_mali_osk_free(descriptor);
+			return _MALI_OSK_ERR_FAULT;
+		}
+		left -= size_to_map;
+		offset += size_to_map;
+	}
+
+	/* Add to the ump_memory_allocation tracking list */
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_list_add( &descriptor->list, &session_data->list_head_session_memory_mappings_list );
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	args->mapping = descriptor->mapping;
+	args->cookie = descriptor->cookie;
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void _ump_ukk_unmap_mem( _ump_uk_unmap_mem_s *args )
+{
+	struct ump_session_data * session_data;
+	ump_memory_allocation * descriptor;
+	ump_dd_handle handle;
+
+	session_data = (ump_session_data *)args->ctx;
+
+	if (NULL == session_data)
+	{
+		MSG_ERR(("Session data is NULL in _ump_ukk_map_mem()\n"));
+		return;
+	}
+
+	/* SEC kernel stability 2012-02-17 */
+	if (NULL == session_data->cookies_map)
+	{
+		MSG_ERR(("session_data->cookies_map is NULL in _ump_ukk_map_mem()\n"));
+		return;
+	}
+
+	if (0 != ump_descriptor_mapping_get( session_data->cookies_map, (int)args->cookie, (void**)&descriptor) )
+	{
+		MSG_ERR(("_ump_ukk_map_mem: cookie 0x%X not found for this session\n", args->cookie ));
+		return;
+	}
+
+	DEBUG_ASSERT_POINTER(descriptor);
+
+	handle = descriptor->handle;
+	if ( UMP_DD_HANDLE_INVALID == handle)
+	{
+		DBG_MSG(1, ("WARNING: Trying to unmap unknown handle: UNKNOWN\n"));
+		return;
+	}
+
+	/* Remove the ump_memory_allocation from the list of tracked mappings */
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_list_del( &descriptor->list );
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	ump_descriptor_mapping_free( session_data->cookies_map, (int)args->cookie );
+
+	ump_dd_reference_release(handle);
+
+	_ump_osk_mem_mapregion_term( descriptor );
+	_mali_osk_free(descriptor);
+}
+
+u32 _ump_ukk_report_memory_usage( void )
+{
+	if(device.backend->stat)
+		return device.backend->stat(device.backend);
+	else
+		return 0;
+}
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_common.h b/drivers/media/video/samsung/ump/common/ump_kernel_common.h
new file mode 100644
index 0000000..c8b5541
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_common.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __UMP_KERNEL_H__
+#define __UMP_KERNEL_H__
+
+#include "ump_kernel_types.h"
+#include "ump_kernel_interface.h"
+#include "ump_kernel_descriptor_mapping.h"
+#include "ump_kernel_memory_backend.h"
+
+
+#ifdef DEBUG
+	extern int ump_debug_level;
+	#define UMP_DEBUG_PRINT(args) _mali_osk_dbgmsg args
+	#define UMP_DEBUG_CODE(args) args
+	#define DBG_MSG(level,args)  do { /* args should be in brackets */ \
+		((level) <=  ump_debug_level)?\
+		UMP_DEBUG_PRINT(("UMP<" #level ">: ")), \
+		UMP_DEBUG_PRINT(args):0; \
+		} while (0)
+
+	#define DBG_MSG_IF(level,condition,args) /* args should be in brackets */ \
+		if((condition)&&((level) <=  ump_debug_level)) {\
+		UMP_DEBUG_PRINT(("UMP<" #level ">: ")); \
+		UMP_DEBUG_PRINT(args); \
+		}
+
+	#define DBG_MSG_ELSE(level,args) /* args should be in brackets */ \
+		else if((level) <=  ump_debug_level) { \
+		UMP_DEBUG_PRINT(("UMP<" #level ">: ")); \
+		UMP_DEBUG_PRINT(args); \
+		}
+
+	#define DEBUG_ASSERT_POINTER(pointer) do  {if( (pointer)== NULL) MSG_ERR(("NULL pointer " #pointer)); } while(0)
+	#define DEBUG_ASSERT(condition) do  {if(!(condition)) MSG_ERR(("ASSERT failed: " #condition)); } while(0)
+#else /* DEBUG */
+	#define UMP_DEBUG_PRINT(args) do {} while(0)
+	#define UMP_DEBUG_CODE(args)
+	#define DBG_MSG(level,args) do {} while(0)
+	#define DBG_MSG_IF(level,condition,args) do {} while(0)
+	#define DBG_MSG_ELSE(level,args) do {} while(0)
+	#define DEBUG_ASSERT(condition) do {} while(0)
+	#define DEBUG_ASSERT_POINTER(pointer) do  {} while(0)
+#endif /* DEBUG */
+
+#define MSG_ERR(args) do{ /* args should be in brackets */ \
+	 _mali_osk_dbgmsg("UMP: ERR: %s\n" ,__FILE__); \
+	 _mali_osk_dbgmsg( "           %s()%4d\n", __FUNCTION__, __LINE__) ; \
+	 _mali_osk_dbgmsg args ; \
+	 _mali_osk_dbgmsg("\n"); \
+	} while(0)
+
+#define MSG(args) do{ /* args should be in brackets */ \
+		 _mali_osk_dbgmsg("UMP: "); \
+		 _mali_osk_dbgmsg args; \
+		} while (0)
+
+
+
+/*
+ * This struct is used to store per session data.
+ * A session is created when someone open() the device, and
+ * closed when someone close() it or the user space application terminates.
+ */
+typedef struct ump_session_data
+{
+	_mali_osk_list_t list_head_session_memory_list;  /**< List of ump allocations made by the process (elements are ump_session_memory_list_element) */
+	_mali_osk_list_t list_head_session_memory_mappings_list; /**< List of ump_memory_allocations mapped in */
+	int api_version;
+	_mali_osk_lock_t * lock;
+	ump_descriptor_mapping * cookies_map; /**< Secure mapping of cookies from _ump_ukk_map_mem() */
+} ump_session_data;
+
+
+
+/*
+ * This struct is used to track the UMP memory references a session has.
+ * We need to track this in order to be able to clean up after user space processes
+ * which don't do it themself (e.g. due to a crash or premature termination).
+ */
+typedef struct ump_session_memory_list_element
+{
+	struct ump_dd_mem * mem;
+	_mali_osk_list_t list;
+} ump_session_memory_list_element;
+
+
+
+/*
+ * Device specific data, created when device driver is loaded, and then kept as the global variable device.
+ */
+typedef struct ump_dev
+{
+	_mali_osk_lock_t * secure_id_map_lock;
+	ump_descriptor_mapping * secure_id_map;
+	ump_memory_backend * backend;
+} ump_dev;
+
+
+
+extern int ump_debug_level;
+extern struct ump_dev device;
+
+_mali_osk_errcode_t ump_kernel_constructor(void);
+void ump_kernel_destructor(void);
+int map_errcode( _mali_osk_errcode_t err );
+
+/**
+ * variables from user space cannot be dereferenced from kernel space; tagging them
+ * with __user allows the GCC compiler to generate a warning. Other compilers may
+ * not support this so we define it here as an empty macro if the compiler doesn't
+ * define it.
+ */
+#ifndef __user
+#define __user
+#endif
+
+#endif /* __UMP_KERNEL_H__ */
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.c b/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.c
new file mode 100644
index 0000000..5174839
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_kernel_common.h"
+#include "mali_osk.h"
+#include "mali_osk_bitops.h"
+#include "ump_kernel_common.h"
+#include "ump_kernel_descriptor_mapping.h"
+
+#define MALI_PAD_INT(x) (((x) + (BITS_PER_LONG - 1)) & ~(BITS_PER_LONG - 1))
+
+/**
+ * Allocate a descriptor table capable of holding 'count' mappings
+ * @param count Number of mappings in the table
+ * @return Pointer to a new table, NULL on error
+ */
+static ump_descriptor_table * descriptor_table_alloc(int count);
+
+/**
+ * Free a descriptor table
+ * @param table The table to free
+ */
+static void descriptor_table_free(ump_descriptor_table * table);
+
+ump_descriptor_mapping * ump_descriptor_mapping_create(int init_entries, int max_entries)
+{
+	ump_descriptor_mapping * map = _mali_osk_calloc(1, sizeof(ump_descriptor_mapping) );
+
+	init_entries = MALI_PAD_INT(init_entries);
+	max_entries = MALI_PAD_INT(max_entries);
+
+	if (NULL != map)
+	{
+		map->table = descriptor_table_alloc(init_entries);
+		if (NULL != map->table)
+		{
+			map->lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_READERWRITER, 0 , 0);
+			if ( NULL != map->lock )
+			{
+				_mali_osk_set_nonatomic_bit(0, map->table->usage); /* reserve bit 0 to prevent NULL/zero logic to kick in */
+				map->max_nr_mappings_allowed = max_entries;
+				map->current_nr_mappings = init_entries;
+				return map;
+			}
+			descriptor_table_free(map->table);
+		}
+		_mali_osk_free(map);
+	}
+	return NULL;
+}
+
+void ump_descriptor_mapping_destroy(ump_descriptor_mapping * map)
+{
+	descriptor_table_free(map->table);
+	_mali_osk_lock_term( map->lock );
+	_mali_osk_free(map);
+}
+
+int ump_descriptor_mapping_allocate_mapping(ump_descriptor_mapping * map, void * target)
+{
+ 	int descriptor = -1;/*-EFAULT;*/
+ 	_mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RW);
+ 	descriptor = _mali_osk_find_first_zero_bit(map->table->usage, map->current_nr_mappings);
+	if (descriptor == map->current_nr_mappings)
+	{
+		int nr_mappings_new;
+		/* no free descriptor, try to expand the table */
+		ump_descriptor_table * new_table;
+		ump_descriptor_table * old_table = map->table;
+		nr_mappings_new= map->current_nr_mappings *2;
+
+		if (map->current_nr_mappings >= map->max_nr_mappings_allowed)
+		{
+			descriptor = -1;
+			goto unlock_and_exit;
+		}
+
+		new_table = descriptor_table_alloc(nr_mappings_new);
+		if (NULL == new_table)
+		{
+			descriptor = -1;
+			goto unlock_and_exit;
+		}
+
+ 		_mali_osk_memcpy(new_table->usage, old_table->usage, (sizeof(unsigned long)*map->current_nr_mappings) / BITS_PER_LONG);
+ 		_mali_osk_memcpy(new_table->mappings, old_table->mappings, map->current_nr_mappings * sizeof(void*));
+		map->table = new_table;
+		map->current_nr_mappings = nr_mappings_new;
+		descriptor_table_free(old_table);
+	}
+
+	/* we have found a valid descriptor, set the value and usage bit */
+	_mali_osk_set_nonatomic_bit(descriptor, map->table->usage);
+	map->table->mappings[descriptor] = target;
+
+unlock_and_exit:
+	_mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RW);
+	return descriptor;
+}
+
+int ump_descriptor_mapping_get(ump_descriptor_mapping * map, int descriptor, void** target)
+{
+ 	int result = -1;/*-EFAULT;*/
+ 	DEBUG_ASSERT(map);
+ 	_mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RO);
+ 	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		*target = map->table->mappings[descriptor];
+		result = 0;
+	}
+	else *target = NULL;
+	_mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RO);
+	return result;
+}
+
+int ump_descriptor_mapping_set(ump_descriptor_mapping * map, int descriptor, void * target)
+{
+ 	int result = -1;/*-EFAULT;*/
+ 	_mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RO);
+ 	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		map->table->mappings[descriptor] = target;
+		result = 0;
+	}
+	_mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RO);
+	return result;
+}
+
+void ump_descriptor_mapping_free(ump_descriptor_mapping * map, int descriptor)
+{
+ 	_mali_osk_lock_wait(map->lock, _MALI_OSK_LOCKMODE_RW);
+ 	if ( (descriptor >= 0) && (descriptor < map->current_nr_mappings) && _mali_osk_test_bit(descriptor, map->table->usage) )
+	{
+		map->table->mappings[descriptor] = NULL;
+		_mali_osk_clear_nonatomic_bit(descriptor, map->table->usage);
+	}
+	_mali_osk_lock_signal(map->lock, _MALI_OSK_LOCKMODE_RW);
+}
+
+static ump_descriptor_table * descriptor_table_alloc(int count)
+{
+	ump_descriptor_table * table;
+
+	table = _mali_osk_calloc(1, sizeof(ump_descriptor_table) + ((sizeof(unsigned long) * count)/BITS_PER_LONG) + (sizeof(void*) * count) );
+
+	if (NULL != table)
+	{
+		table->usage = (u32*)((u8*)table + sizeof(ump_descriptor_table));
+		table->mappings = (void**)((u8*)table + sizeof(ump_descriptor_table) + ((sizeof(unsigned long) * count)/BITS_PER_LONG));
+	}
+
+	return table;
+}
+
+static void descriptor_table_free(ump_descriptor_table * table)
+{
+	_mali_osk_free(table);
+}
+
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.h b/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.h
new file mode 100644
index 0000000..319cc3b
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_descriptor_mapping.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_descriptor_mapping.h
+ */
+
+#ifndef __UMP_KERNEL_DESCRIPTOR_MAPPING_H__
+#define __UMP_KERNEL_DESCRIPTOR_MAPPING_H__
+
+#include "mali_osk.h"
+
+/**
+ * The actual descriptor mapping table, never directly accessed by clients
+ */
+typedef struct ump_descriptor_table
+{
+	u32 * usage; /**< Pointer to bitpattern indicating if a descriptor is valid/used or not */
+	void** mappings; /**< Array of the pointers the descriptors map to */
+} ump_descriptor_table;
+
+/**
+ * The descriptor mapping object
+ * Provides a separate namespace where we can map an integer to a pointer
+ */
+typedef struct ump_descriptor_mapping
+{
+	_mali_osk_lock_t *lock; /**< Lock protecting access to the mapping object */
+	int max_nr_mappings_allowed; /**< Max number of mappings to support in this namespace */
+	int current_nr_mappings; /**< Current number of possible mappings */
+	ump_descriptor_table * table; /**< Pointer to the current mapping table */
+} ump_descriptor_mapping;
+
+/**
+ * Create a descriptor mapping object
+ * Create a descriptor mapping capable of holding init_entries growable to max_entries
+ * @param init_entries Number of entries to preallocate memory for
+ * @param max_entries Number of entries to max support
+ * @return Pointer to a descriptor mapping object, NULL on failure
+ */
+ump_descriptor_mapping * ump_descriptor_mapping_create(int init_entries, int max_entries);
+
+/**
+ * Destroy a descriptor mapping object
+ * @param map The map to free
+ */
+void ump_descriptor_mapping_destroy(ump_descriptor_mapping * map);
+
+/**
+ * Allocate a new mapping entry (descriptor ID)
+ * Allocates a new entry in the map.
+ * @param map The map to allocate a new entry in
+ * @param target The value to map to
+ * @return The descriptor allocated, a negative value on error
+ */
+int ump_descriptor_mapping_allocate_mapping(ump_descriptor_mapping * map, void * target);
+
+/**
+ * Get the value mapped to by a descriptor ID
+ * @param map The map to lookup the descriptor id in
+ * @param descriptor The descriptor ID to lookup
+ * @param target Pointer to a pointer which will receive the stored value
+ * @return 0 on successful lookup, negative on error
+ */
+int ump_descriptor_mapping_get(ump_descriptor_mapping * map, int descriptor, void** target);
+
+/**
+ * Set the value mapped to by a descriptor ID
+ * @param map The map to lookup the descriptor id in
+ * @param descriptor The descriptor ID to lookup
+ * @param target Pointer to replace the current value with
+ * @return 0 on successful lookup, negative on error
+ */
+int ump_descriptor_mapping_set(ump_descriptor_mapping * map, int descriptor, void * target);
+
+/**
+ * Free the descriptor ID
+ * For the descriptor to be reused it has to be freed
+ * @param map The map to free the descriptor from
+ * @param descriptor The descriptor ID to free
+ */
+void ump_descriptor_mapping_free(ump_descriptor_mapping * map, int descriptor);
+
+#endif /* __UMP_KERNEL_DESCRIPTOR_MAPPING_H__ */
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_memory_backend.h b/drivers/media/video/samsung/ump/common/ump_kernel_memory_backend.h
new file mode 100644
index 0000000..d329bb5
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_memory_backend.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_memory_mapping.h
+ */
+
+#ifndef __UMP_KERNEL_MEMORY_BACKEND_H__
+#define __UMP_KERNEL_MEMORY_BACKEND_H__
+
+#include "ump_kernel_interface.h"
+#include "ump_kernel_types.h"
+
+
+typedef struct ump_memory_allocation
+{
+	void                    * phys_addr;
+	void                    * mapping;
+	unsigned long             size;
+	ump_dd_handle             handle;
+	void                    * process_mapping_info;
+	u32                       cookie;               /**< necessary on some U/K interface implementations */
+	struct ump_session_data * ump_session;          /**< Session that this allocation belongs to */
+	_mali_osk_list_t          list;                 /**< List for linking together memory allocations into the session's memory head */
+	u32 is_cached;
+} ump_memory_allocation;
+
+typedef struct ump_memory_backend
+{
+	int  (*allocate)(void* ctx, ump_dd_mem * descriptor);
+	void (*release)(void* ctx, ump_dd_mem * descriptor);
+	void (*shutdown)(struct ump_memory_backend * backend);
+	u32  (*stat)(struct ump_memory_backend *backend);
+	int  (*pre_allocate_physical_check)(void *ctx, u32 size);
+	u32  (*adjust_to_mali_phys)(void *ctx, u32 cpu_phys);
+	void *(*get)(ump_dd_mem *mem, void *args);
+	void (*set)(ump_dd_mem *mem, void *args);
+	void * ctx;
+} ump_memory_backend;
+
+ump_memory_backend * ump_memory_backend_create ( void );
+void ump_memory_backend_destroy( void );
+
+#endif /*__UMP_KERNEL_MEMORY_BACKEND_H__ */
+
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_ref_drv.c b/drivers/media/video/samsung/ump/common/ump_kernel_ref_drv.c
new file mode 100644
index 0000000..4dcbe21
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_ref_drv.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "mali_osk.h"
+#include "mali_osk_list.h"
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+
+#include "ump_kernel_interface_ref_drv.h"
+#include "ump_kernel_common.h"
+#include "ump_kernel_descriptor_mapping.h"
+
+#define UMP_MINIMUM_SIZE         4096
+#define UMP_MINIMUM_SIZE_MASK    (~(UMP_MINIMUM_SIZE-1))
+#define UMP_SIZE_ALIGN(x)        (((x)+UMP_MINIMUM_SIZE-1)&UMP_MINIMUM_SIZE_MASK)
+#define UMP_ADDR_ALIGN_OFFSET(x) ((x)&(UMP_MINIMUM_SIZE-1))
+static void phys_blocks_release(void * ctx, struct ump_dd_mem * descriptor);
+
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_create_from_phys_blocks(ump_dd_physical_block * blocks, unsigned long num_blocks)
+{
+	ump_dd_mem * mem;
+	unsigned long size_total = 0;
+	int map_id;
+	u32 i;
+
+	/* Go through the input blocks and verify that they are sane */
+	for (i=0; i < num_blocks; i++)
+	{
+		unsigned long addr = blocks[i].addr;
+		unsigned long size = blocks[i].size;
+
+		DBG_MSG(5, ("Adding physical memory to new handle. Address: 0x%08lx, size: %lu\n", addr, size));
+		size_total += blocks[i].size;
+
+		if (0 != UMP_ADDR_ALIGN_OFFSET(addr))
+		{
+			MSG_ERR(("Trying to create UMP memory from unaligned physical address. Address: 0x%08lx\n", addr));
+			return UMP_DD_HANDLE_INVALID;
+		}
+
+		if (0 != UMP_ADDR_ALIGN_OFFSET(size))
+		{
+			MSG_ERR(("Trying to create UMP memory with unaligned size. Size: %lu\n", size));
+			return UMP_DD_HANDLE_INVALID;
+		}
+	}
+
+	/* Allocate the ump_dd_mem struct for this allocation */
+	mem = _mali_osk_malloc(sizeof(*mem));
+	if (NULL == mem)
+	{
+		DBG_MSG(1, ("Could not allocate ump_dd_mem in ump_dd_handle_create_from_phys_blocks()\n"));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	/* Find a secure ID for this allocation */
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	map_id = ump_descriptor_mapping_allocate_mapping(device.secure_id_map, (void*) mem);
+
+	if (map_id < 0)
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		_mali_osk_free(mem);
+		DBG_MSG(1, ("Failed to allocate secure ID in ump_dd_handle_create_from_phys_blocks()\n"));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	/* Now, make a copy of the block information supplied by the user */
+	mem->block_array = _mali_osk_malloc(sizeof(ump_dd_physical_block)* num_blocks);
+	if (NULL == mem->block_array)
+	{
+		ump_descriptor_mapping_free(device.secure_id_map, map_id);
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		_mali_osk_free(mem);
+		DBG_MSG(1, ("Could not allocate a mem handle for function ump_dd_handle_create_from_phys_blocks().\n"));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	_mali_osk_memcpy(mem->block_array, blocks, sizeof(ump_dd_physical_block) * num_blocks);
+
+	/* And setup the rest of the ump_dd_mem struct */
+	_mali_osk_atomic_init(&mem->ref_count, 1);
+	mem->secure_id = (ump_secure_id)map_id;
+	mem->size_bytes = size_total;
+	mem->nr_blocks = num_blocks;
+	mem->backend_info = NULL;
+	mem->ctx = NULL;
+	mem->release_func = phys_blocks_release;
+	/* For now UMP handles created by ump_dd_handle_create_from_phys_blocks() is forced to be Uncached */
+	mem->is_cached = 0;
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	DBG_MSG(3, ("UMP memory created. ID: %u, size: %lu\n", mem->secure_id, mem->size_bytes));
+
+	return (ump_dd_handle)mem;
+}
+
+static void phys_blocks_release(void * ctx, struct ump_dd_mem * descriptor)
+{
+	_mali_osk_free(descriptor->block_array);
+	descriptor->block_array = NULL;
+}
+
+_mali_osk_errcode_t _ump_ukk_allocate( _ump_uk_allocate_s *user_interaction )
+{
+	ump_session_data * session_data = NULL;
+	ump_dd_mem *new_allocation = NULL;
+	ump_session_memory_list_element * session_memory_element = NULL;
+	int map_id;
+
+	DEBUG_ASSERT_POINTER( user_interaction );
+	DEBUG_ASSERT_POINTER( user_interaction->ctx );
+
+	session_data = (ump_session_data *) user_interaction->ctx;
+
+	session_memory_element = _mali_osk_calloc( 1, sizeof(ump_session_memory_list_element));
+	if (NULL == session_memory_element)
+	{
+		DBG_MSG(1, ("Failed to allocate ump_session_memory_list_element in ump_ioctl_allocate()\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+
+	new_allocation = _mali_osk_calloc( 1, sizeof(ump_dd_mem));
+	if (NULL==new_allocation)
+	{
+		_mali_osk_free(session_memory_element);
+		DBG_MSG(1, ("Failed to allocate ump_dd_mem in _ump_ukk_allocate()\n"));
+		return _MALI_OSK_ERR_NOMEM;
+	}
+
+	/* Create a secure ID for this allocation */
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	map_id = ump_descriptor_mapping_allocate_mapping(device.secure_id_map, (void*)new_allocation);
+
+	if (map_id < 0)
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		_mali_osk_free(session_memory_element);
+		_mali_osk_free(new_allocation);
+		DBG_MSG(1, ("Failed to allocate secure ID in ump_ioctl_allocate()\n"));
+		return - _MALI_OSK_ERR_INVALID_FUNC;
+	}
+
+	/* Initialize the part of the new_allocation that we know so for */
+	new_allocation->secure_id = (ump_secure_id)map_id;
+	_mali_osk_atomic_init(&new_allocation->ref_count,1);
+	if ( 0==(UMP_REF_DRV_UK_CONSTRAINT_USE_CACHE & user_interaction->constraints) )
+		 new_allocation->is_cached = 0;
+	else new_allocation->is_cached = 1;
+
+	new_allocation->backend_info = (void*)user_interaction->constraints;
+
+	/* special case a size of 0, we should try to emulate what malloc does in this case, which is to return a valid pointer that must be freed, but can't be dereferences */
+	if (0 == user_interaction->size)
+	{
+		user_interaction->size = 1; /* emulate by actually allocating the minimum block size */
+	}
+
+	new_allocation->size_bytes = UMP_SIZE_ALIGN(user_interaction->size); /* Page align the size */
+
+	/* Now, ask the active memory backend to do the actual memory allocation */
+	if (!device.backend->allocate( device.backend->ctx, new_allocation ) )
+	{
+		DBG_MSG(3, ("OOM: No more UMP memory left. Failed to allocate memory in ump_ioctl_allocate(). Size: %lu, requested size: %lu\n", new_allocation->size_bytes, (unsigned long)user_interaction->size));
+		ump_descriptor_mapping_free(device.secure_id_map, map_id);
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		_mali_osk_free(new_allocation);
+		_mali_osk_free(session_memory_element);
+		return _MALI_OSK_ERR_INVALID_FUNC;
+	}
+
+	new_allocation->ctx = device.backend->ctx;
+	new_allocation->release_func = device.backend->release;
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	/* Initialize the session_memory_element, and add it to the session object */
+	session_memory_element->mem = new_allocation;
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_list_add(&(session_memory_element->list), &(session_data->list_head_session_memory_list));
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	user_interaction->secure_id = new_allocation->secure_id;
+	user_interaction->size = new_allocation->size_bytes;
+	DBG_MSG(3, ("UMP memory allocated. ID: %u, size: %lu\n", new_allocation->secure_id, new_allocation->size_bytes));
+
+	return _MALI_OSK_ERR_OK;
+}
+
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_meminfo_set(ump_dd_handle memh, void* args)
+{
+	ump_dd_mem * mem;
+	ump_secure_id secure_id;
+
+	DEBUG_ASSERT_POINTER(memh);
+
+	secure_id = ump_dd_secure_id_get(memh);
+
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	if (0 == ump_descriptor_mapping_get(device.secure_id_map, (int)secure_id, (void**)&mem))
+	{
+		device.backend->set(mem, args);
+	}
+	else
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		DBG_MSG(1, ("Failed to look up mapping in ump_meminfo_set(). ID: %u\n", (ump_secure_id)secure_id));
+		return UMP_DD_INVALID;
+	}
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	return UMP_DD_SUCCESS;
+}
+
+UMP_KERNEL_API_EXPORT void *ump_dd_meminfo_get(ump_secure_id secure_id, void* args)
+{
+	ump_dd_mem * mem;
+	void *result;
+
+	_mali_osk_lock_wait(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+	if (0 == ump_descriptor_mapping_get(device.secure_id_map, (int)secure_id, (void**)&mem))
+	{
+		result = device.backend->get(mem, args);
+	}
+	else
+	{
+		_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+		DBG_MSG(1, ("Failed to look up mapping in ump_meminfo_get(). ID: %u\n", (ump_secure_id)secure_id));
+		return UMP_DD_HANDLE_INVALID;
+	}
+
+	_mali_osk_lock_signal(device.secure_id_map_lock, _MALI_OSK_LOCKMODE_RW);
+
+	return result;
+}
+
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_get_from_vaddr(unsigned long vaddr)
+{
+	ump_dd_mem * mem;
+
+	DBG_MSG(5, ("Getting handle from Virtual address. vaddr: %u\n", vaddr));
+
+	_ump_osk_mem_mapregion_get(&mem, vaddr);
+
+	DBG_MSG(1, ("Getting handle's Handle : 0x%8lx\n", mem));
+
+	return (ump_dd_handle)mem;
+}
+
diff --git a/drivers/media/video/samsung/ump/common/ump_kernel_types.h b/drivers/media/video/samsung/ump/common/ump_kernel_types.h
new file mode 100644
index 0000000..ca03dec
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_kernel_types.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __UMP_KERNEL_TYPES_H__
+#define __UMP_KERNEL_TYPES_H__
+
+#include "ump_kernel_interface.h"
+#include "mali_osk.h"
+
+/*
+ * This struct is what is "behind" a ump_dd_handle
+ */
+typedef struct ump_dd_mem
+{
+	ump_secure_id secure_id;
+	_mali_osk_atomic_t ref_count;
+	unsigned long size_bytes;
+	unsigned long nr_blocks;
+	ump_dd_physical_block * block_array;
+	void (*release_func)(void * ctx, struct ump_dd_mem * descriptor);
+	void * ctx;
+	void * backend_info;
+	int is_cached;
+} ump_dd_mem;
+
+
+
+#endif /* __UMP_KERNEL_TYPES_H__ */
diff --git a/drivers/media/video/samsung/ump/common/ump_osk.h b/drivers/media/video/samsung/ump/common/ump_osk.h
new file mode 100644
index 0000000..bd9254b
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_osk.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_osk.h
+ * Defines the OS abstraction layer for the UMP kernel device driver (OSK)
+ */
+
+#ifndef __UMP_OSK_H__
+#define __UMP_OSK_H__
+
+#include <mali_osk.h>
+#include <ump_kernel_memory_backend.h>
+#include <ump_uk_types.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+_mali_osk_errcode_t _ump_osk_init( void );
+
+_mali_osk_errcode_t _ump_osk_term( void );
+
+int _ump_osk_atomic_inc_and_read( _mali_osk_atomic_t *atom );
+
+int _ump_osk_atomic_dec_and_read( _mali_osk_atomic_t *atom );
+
+_mali_osk_errcode_t _ump_osk_mem_mapregion_init( ump_memory_allocation *descriptor );
+
+_mali_osk_errcode_t _ump_osk_mem_mapregion_map( ump_memory_allocation * descriptor, u32 offset, u32 * phys_addr, unsigned long size );
+
+void _ump_osk_mem_mapregion_term( ump_memory_allocation * descriptor );
+
+void _ump_osk_msync( ump_dd_mem * mem, ump_uk_msync_op op,  u32 start, u32 address, u32 size);
+
+void _ump_osk_mem_mapregion_get( ump_dd_mem ** mem, unsigned long vaddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/media/video/samsung/ump/common/ump_uk_types.h b/drivers/media/video/samsung/ump/common/ump_uk_types.h
new file mode 100644
index 0000000..2bac454
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_uk_types.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_uk_types.h
+ * Defines the types and constants used in the user-kernel interface
+ */
+
+#ifndef __UMP_UK_TYPES_H__
+#define __UMP_UK_TYPES_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Helpers for API version handling */
+#define MAKE_VERSION_ID(x) (((x) << 16UL) | (x))
+#define IS_VERSION_ID(x) (((x) & 0xFFFF) == (((x) >> 16UL) & 0xFFFF))
+#define GET_VERSION(x) (((x) >> 16UL) & 0xFFFF)
+#define IS_API_MATCH(x, y) (IS_VERSION_ID((x)) && IS_VERSION_ID((y)) && (GET_VERSION((x)) == GET_VERSION((y))))
+
+/**
+ * API version define.
+ * Indicates the version of the kernel API
+ * The version is a 16bit integer incremented on each API change.
+ * The 16bit integer is stored twice in a 32bit integer
+ * So for version 1 the value would be 0x00010001
+ */
+#define UMP_IOCTL_API_VERSION MAKE_VERSION_ID(2)
+
+typedef enum
+{
+	_UMP_IOC_QUERY_API_VERSION = 1,
+	_UMP_IOC_ALLOCATE,
+	_UMP_IOC_RELEASE,
+	_UMP_IOC_SIZE_GET,
+	_UMP_IOC_MAP_MEM,    /* not used in Linux */
+	_UMP_IOC_UNMAP_MEM,  /* not used in Linux */
+	_UMP_IOC_MSYNC,
+#ifdef CONFIG_ION_EXYNOS
+	_UMP_IOC_ION_IMPORT,
+#endif
+#ifdef CONFIG_DMA_SHARED_BUFFER
+	_UMP_IOC_DMABUF_IMPORT,
+#endif
+}_ump_uk_functions;
+
+typedef enum
+{
+	UMP_REF_DRV_UK_CONSTRAINT_NONE = 0,
+	UMP_REF_DRV_UK_CONSTRAINT_PHYSICALLY_LINEAR = 1,
+	UMP_REF_DRV_UK_CONSTRAINT_USE_CACHE = 128,
+} ump_uk_alloc_constraints;
+
+typedef enum
+{
+	_UMP_UK_MSYNC_CLEAN = 0,
+	_UMP_UK_MSYNC_CLEAN_AND_INVALIDATE = 1,
+	_UMP_UK_MSYNC_READOUT_CACHE_ENABLED = 128,
+} ump_uk_msync_op;
+
+/**
+ * Get API version ([in,out] u32 api_version, [out] u32 compatible)
+ */
+typedef struct _ump_uk_api_version_s
+{
+	void *ctx;      /**< [in,out] user-kernel context (trashed on output) */
+	u32 version;    /**< Set to the user space version on entry, stores the device driver version on exit */
+	u32 compatible; /**< Non-null if the device is compatible with the client */
+} _ump_uk_api_version_s;
+
+/**
+ * ALLOCATE ([out] u32 secure_id, [in,out] u32 size,  [in] contraints)
+ */
+typedef struct _ump_uk_allocate_s
+{
+	void *ctx;                              /**< [in,out] user-kernel context (trashed on output) */
+	u32 secure_id;                          /**< Return value from DD to Userdriver */
+	u32 size;                               /**< Input and output. Requested size; input. Returned size; output */
+	ump_uk_alloc_constraints constraints;   /**< Only input to Devicedriver */
+} _ump_uk_allocate_s;
+
+#ifdef CONFIG_ION_EXYNOS
+typedef struct _ump_uk_ion_import_s
+{
+	void *ctx;                              /**< [in,out] user-kernel context (trashed on output) */
+	int ion_fd;
+	u32 secure_id;                          /**< Return value from DD to Userdriver */
+	u32 size;                               /**< Input and output. Requested size; input. Returned size; output */
+	ump_uk_alloc_constraints constraints;   /**< Only input to Devicedriver */
+} _ump_uk_ion_import_s;
+#endif
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+struct ump_uk_dmabuf {
+	void		*ctx;
+	int		fd;
+	size_t		size;
+	uint32_t	ump_handle;
+};
+#endif
+
+/**
+ * SIZE_GET ([in] u32 secure_id, [out]size )
+ */
+typedef struct _ump_uk_size_get_s
+{
+	void *ctx;                              /**< [in,out] user-kernel context (trashed on output) */
+	u32 secure_id;                          /**< Input to DD */
+	u32 size;                               /**< Returned size; output */
+} _ump_uk_size_get_s;
+
+/**
+ * Release ([in] u32 secure_id)
+ */
+typedef struct _ump_uk_release_s
+{
+	void *ctx;                              /**< [in,out] user-kernel context (trashed on output) */
+	u32 secure_id;                          /**< Input to DD */
+} _ump_uk_release_s;
+
+typedef struct _ump_uk_map_mem_s
+{
+	void *ctx;                      /**< [in,out] user-kernel context (trashed on output) */
+	void *mapping;                  /**< [out] Returns user-space virtual address for the mapping */
+	void *phys_addr;                /**< [in] physical address */
+	unsigned long size;             /**< [in] size */
+	u32 secure_id;                  /**< [in] secure_id to assign to mapping */
+	void * _ukk_private;            /**< Only used inside linux port between kernel frontend and common part to store vma */
+	u32 cookie;
+	u32 is_cached;            /**< [in,out] caching of CPU mappings */
+} _ump_uk_map_mem_s;
+
+typedef struct _ump_uk_unmap_mem_s
+{
+	void *ctx;            /**< [in,out] user-kernel context (trashed on output) */
+	void *mapping;
+	u32 size;
+	void * _ukk_private;
+	u32 cookie;
+} _ump_uk_unmap_mem_s;
+
+typedef struct _ump_uk_msync_s
+{
+	void *ctx;            /**< [in,out] user-kernel context (trashed on output) */
+	void *mapping;        /**< [in] mapping addr */
+	void *address;        /**< [in] flush start addr */
+	u32 size;             /**< [in] size to flush */
+	ump_uk_msync_op op;   /**< [in] flush operation */
+	u32 cookie;           /**< [in] cookie stored with reference to the kernel mapping internals */
+	u32 secure_id;        /**< [in] cookie stored with reference to the kernel mapping internals */
+	u32 is_cached;        /**< [out] caching of CPU mappings */
+} _ump_uk_msync_s;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UMP_UK_TYPES_H__ */
diff --git a/drivers/media/video/samsung/ump/common/ump_ukk.h b/drivers/media/video/samsung/ump/common/ump_ukk.h
new file mode 100644
index 0000000..db48cd6
--- /dev/null
+++ b/drivers/media/video/samsung/ump/common/ump_ukk.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_ukk.h
+ * Defines the kernel-side interface of the user-kernel interface
+ */
+
+#ifndef __UMP_UKK_H__
+#define __UMP_UKK_H__
+
+#include "mali_osk.h"
+#include "ump_uk_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+_mali_osk_errcode_t _ump_ukk_open( void** context );
+
+_mali_osk_errcode_t _ump_ukk_close( void** context );
+
+_mali_osk_errcode_t _ump_ukk_allocate( _ump_uk_allocate_s *user_interaction );
+
+_mali_osk_errcode_t _ump_ukk_release( _ump_uk_release_s *release_info );
+
+_mali_osk_errcode_t _ump_ukk_size_get( _ump_uk_size_get_s *user_interaction );
+
+_mali_osk_errcode_t _ump_ukk_map_mem( _ump_uk_map_mem_s *args );
+
+_mali_osk_errcode_t _ump_uku_get_api_version( _ump_uk_api_version_s *args );
+
+void _ump_ukk_unmap_mem( _ump_uk_unmap_mem_s *args );
+
+void _ump_ukk_msync( _ump_uk_msync_s *args );
+
+u32 _ump_ukk_report_memory_usage( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UMP_UKK_H__ */
diff --git a/drivers/media/video/samsung/ump/include/ump_kernel_interface.h b/drivers/media/video/samsung/ump/include/ump_kernel_interface.h
new file mode 100644
index 0000000..ba81a07
--- /dev/null
+++ b/drivers/media/video/samsung/ump/include/ump_kernel_interface.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_interface.h
+ *
+ * This file contains the kernel space part of the UMP API.
+ */
+
+#ifndef __UMP_KERNEL_INTERFACE_H__
+#define __UMP_KERNEL_INTERFACE_H__
+
+
+/** @defgroup ump_kernel_space_api UMP Kernel Space API
+ * @{ */
+
+
+#include "ump_kernel_platform.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * External representation of a UMP handle in kernel space.
+ */
+typedef void * ump_dd_handle;
+
+/**
+ * Typedef for a secure ID, a system wide identificator for UMP memory buffers.
+ */
+typedef unsigned int ump_secure_id;
+
+
+/**
+ * Value to indicate an invalid UMP memory handle.
+ */
+#define UMP_DD_HANDLE_INVALID ((ump_dd_handle)0)
+
+
+/**
+ * Value to indicate an invalid secure Id.
+ */
+#define UMP_INVALID_SECURE_ID ((ump_secure_id)-1)
+
+
+/**
+ * UMP error codes for kernel space.
+ */
+typedef enum
+{
+	UMP_DD_SUCCESS, /**< indicates success */
+	UMP_DD_INVALID, /**< indicates failure */
+} ump_dd_status_code;
+
+
+/**
+ * Struct used to describe a physical block used by UMP memory
+ */
+typedef struct ump_dd_physical_block
+{
+	unsigned long addr; /**< The physical address of the block */
+	unsigned long size; /**< The length of the block, typically page aligned */
+} ump_dd_physical_block;
+
+
+/**
+ * Retrieves the secure ID for the specified UMP memory.
+ *
+ * This identificator is unique across the entire system, and uniquely identifies
+ * the specified UMP memory. This identificator can later be used through the
+ * @ref ump_dd_handle_create_from_secure_id "ump_dd_handle_create_from_secure_id" or
+ * @ref ump_handle_create_from_secure_id "ump_handle_create_from_secure_id"
+ * functions in order to access this UMP memory, for instance from another process.
+ *
+ * @note There is a user space equivalent function called @ref ump_secure_id_get "ump_secure_id_get"
+ *
+ * @see ump_dd_handle_create_from_secure_id
+ * @see ump_handle_create_from_secure_id
+ * @see ump_secure_id_get
+ *
+ * @param mem Handle to UMP memory.
+ *
+ * @return Returns the secure ID for the specified UMP memory.
+ */
+UMP_KERNEL_API_EXPORT ump_secure_id ump_dd_secure_id_get(ump_dd_handle mem);
+
+
+/**
+ * Retrieves a handle to allocated UMP memory.
+ *
+ * The usage of UMP memory is reference counted, so this will increment the reference
+ * count by one for the specified UMP memory.
+ * Use @ref ump_dd_reference_release "ump_dd_reference_release" when there is no longer any
+ * use for the retrieved handle.
+ *
+ * @note There is a user space equivalent function called @ref ump_handle_create_from_secure_id "ump_handle_create_from_secure_id"
+ *
+ * @see ump_dd_reference_release
+ * @see ump_handle_create_from_secure_id
+ *
+ * @param secure_id The secure ID of the UMP memory to open, that can be retrieved using the @ref ump_secure_id_get "ump_secure_id_get " function.
+ *
+ * @return UMP_INVALID_MEMORY_HANDLE indicates failure, otherwise a valid handle is returned.
+ */
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_create_from_secure_id(ump_secure_id secure_id);
+
+
+/**
+ * Retrieves the number of physical blocks used by the specified UMP memory.
+ *
+ * This function retrieves the number of @ref ump_dd_physical_block "ump_dd_physical_block" structs needed
+ * to describe the physical memory layout of the given UMP memory. This can later be used when calling
+ * the functions @ref ump_dd_phys_blocks_get "ump_dd_phys_blocks_get" and
+ * @ref ump_dd_phys_block_get "ump_dd_phys_block_get".
+ *
+ * @see ump_dd_phys_blocks_get
+ * @see ump_dd_phys_block_get
+ *
+ * @param mem Handle to UMP memory.
+ *
+ * @return The number of ump_dd_physical_block structs required to describe the physical memory layout of the specified UMP memory.
+ */
+UMP_KERNEL_API_EXPORT unsigned long ump_dd_phys_block_count_get(ump_dd_handle mem);
+
+
+/**
+ * Retrieves all physical memory block information for specified UMP memory.
+ *
+ * This function can be used by other device drivers in order to create MMU tables.
+ *
+ * @note This function will fail if the num_blocks parameter is either to large or to small.
+ *
+ * @see ump_dd_phys_block_get
+ *
+ * @param mem Handle to UMP memory.
+ * @param blocks An array of @ref ump_dd_physical_block "ump_dd_physical_block" structs that will receive the physical description.
+ * @param num_blocks The number of blocks to return in the blocks array. Use the function
+ *                   @ref ump_dd_phys_block_count_get "ump_dd_phys_block_count_get" first to determine the number of blocks required.
+ *
+ * @return UMP_DD_SUCCESS indicates success, UMP_DD_INVALID indicates failure.
+ */
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_phys_blocks_get(ump_dd_handle mem, ump_dd_physical_block * blocks, unsigned long num_blocks);
+
+
+/**
+ * Retrieves the physical memory block information for specified block for the specified UMP memory.
+ *
+ * This function can be used by other device drivers in order to create MMU tables.
+ *
+ * @note This function will return UMP_DD_INVALID if the specified index is out of range.
+ *
+ * @see ump_dd_phys_blocks_get
+ *
+ * @param mem Handle to UMP memory.
+ * @param index Which physical info block to retrieve.
+ * @param block Pointer to a @ref ump_dd_physical_block "ump_dd_physical_block" struct which will receive the requested information.
+ *
+ * @return UMP_DD_SUCCESS indicates success, UMP_DD_INVALID indicates failure.
+ */
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_phys_block_get(ump_dd_handle mem, unsigned long index, ump_dd_physical_block * block);
+
+
+/**
+ * Retrieves the actual size of the specified UMP memory.
+ *
+ * The size is reported in bytes, and is typically page aligned.
+ *
+ * @note There is a user space equivalent function called @ref ump_size_get "ump_size_get"
+ *
+ * @see ump_size_get
+ *
+ * @param mem Handle to UMP memory.
+ *
+ * @return Returns the allocated size of the specified UMP memory, in bytes.
+ */
+UMP_KERNEL_API_EXPORT unsigned long ump_dd_size_get(ump_dd_handle mem);
+
+
+/**
+ * Adds an extra reference to the specified UMP memory.
+ *
+ * This function adds an extra reference to the specified UMP memory. This function should
+ * be used every time a UMP memory handle is duplicated, that is, assigned to another ump_dd_handle
+ * variable. The function @ref ump_dd_reference_release "ump_dd_reference_release" must then be used
+ * to release each copy of the UMP memory handle.
+ *
+ * @note You are not required to call @ref ump_dd_reference_add "ump_dd_reference_add"
+ * for UMP handles returned from
+ * @ref ump_dd_handle_create_from_secure_id "ump_dd_handle_create_from_secure_id",
+ * because these handles are already reference counted by this function.
+ *
+ * @note There is a user space equivalent function called @ref ump_reference_add "ump_reference_add"
+ *
+ * @see ump_reference_add
+ *
+ * @param mem Handle to UMP memory.
+ */
+UMP_KERNEL_API_EXPORT void ump_dd_reference_add(ump_dd_handle mem);
+
+
+/**
+ * Releases a reference from the specified UMP memory.
+ *
+ * This function should be called once for every reference to the UMP memory handle.
+ * When the last reference is released, all resources associated with this UMP memory
+ * handle are freed.
+ *
+ * @note There is a user space equivalent function called @ref ump_reference_release "ump_reference_release"
+ *
+ * @see ump_reference_release
+ *
+ * @param mem Handle to UMP memory.
+ */
+UMP_KERNEL_API_EXPORT void ump_dd_reference_release(ump_dd_handle mem);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/** @} */ /* end group ump_kernel_space_api */
+
+
+#endif  /* __UMP_KERNEL_INTERFACE_H__ */
diff --git a/drivers/media/video/samsung/ump/include/ump_kernel_interface_ref_drv.h b/drivers/media/video/samsung/ump/include/ump_kernel_interface_ref_drv.h
new file mode 100644
index 0000000..3efe165
--- /dev/null
+++ b/drivers/media/video/samsung/ump/include/ump_kernel_interface_ref_drv.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_interface.h
+ */
+
+#ifndef __UMP_KERNEL_INTERFACE_REF_DRV_H__
+#define __UMP_KERNEL_INTERFACE_REF_DRV_H__
+
+#include "ump_kernel_interface.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Turn specified physical memory into UMP memory. */
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_create_from_phys_blocks(ump_dd_physical_block * blocks, unsigned long num_blocks);
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_get(ump_secure_id secure_id);
+UMP_KERNEL_API_EXPORT ump_dd_status_code ump_dd_meminfo_set(ump_dd_handle memh, void* args);
+UMP_KERNEL_API_EXPORT void *ump_dd_meminfo_get(ump_secure_id secure_id, void* args);
+UMP_KERNEL_API_EXPORT ump_dd_handle ump_dd_handle_get_from_vaddr(unsigned long vaddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __UMP_KERNEL_INTERFACE_REF_DRV_H__ */
diff --git a/drivers/media/video/samsung/ump/include/ump_kernel_interface_vcm.h b/drivers/media/video/samsung/ump/include/ump_kernel_interface_vcm.h
new file mode 100644
index 0000000..a784241
--- /dev/null
+++ b/drivers/media/video/samsung/ump/include/ump_kernel_interface_vcm.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_interface_vcm.h
+ */
+
+#ifndef __UMP_KERNEL_INTERFACE_VCM_H__
+#define __UMP_KERNEL_INTERFACE_VCM_H__
+
+#include <linux/vcm-drv.h>
+#include <plat/s5p-vcm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Turn specified physical memory into UMP memory. */
+struct ump_vcm {
+	struct vcm *vcm;
+	struct vcm_res  *vcm_res;
+	unsigned int dev_id;
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __UMP_KERNEL_INTERFACE_VCM_H__ */
diff --git a/drivers/media/video/samsung/ump/include/ump_kernel_platform.h b/drivers/media/video/samsung/ump/include/ump_kernel_platform.h
new file mode 100644
index 0000000..1b5af40
--- /dev/null
+++ b/drivers/media/video/samsung/ump/include/ump_kernel_platform.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_platform.h
+ *
+ * This file should define UMP_KERNEL_API_EXPORT,
+ * which dictates how the UMP kernel API should be exported/imported.
+ * Modify this file, if needed, to match your platform setup.
+ */
+
+#ifndef __UMP_KERNEL_PLATFORM_H__
+#define __UMP_KERNEL_PLATFORM_H__
+
+/** @addtogroup ump_kernel_space_api
+ * @{ */
+
+/**
+ * A define which controls how UMP kernel space API functions are imported and exported.
+ * This define should be set by the implementor of the UMP API.
+ */
+
+#if defined(_WIN32)
+
+#if defined(UMP_BUILDING_UMP_LIBRARY)
+#define UMP_KERNEL_API_EXPORT __declspec(dllexport)
+#else
+#define UMP_KERNEL_API_EXPORT __declspec(dllimport)
+#endif
+
+#else
+
+#define UMP_KERNEL_API_EXPORT
+
+#endif
+
+
+/** @} */ /* end group ump_kernel_space_api */
+
+
+#endif /* __UMP_KERNEL_PLATFORM_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/license/gpl/ump_kernel_license.h b/drivers/media/video/samsung/ump/linux/license/gpl/ump_kernel_license.h
new file mode 100644
index 0000000..17b930d
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/license/gpl/ump_kernel_license.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_license.h
+ * Defines for the macro MODULE_LICENSE.
+ */
+
+#ifndef __UMP_KERNEL_LICENSE_H__
+#define __UMP_KERNEL_LICENSE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define UMP_KERNEL_LINUX_LICENSE     "GPL"
+#define UMP_LICENSE_IS_GPL 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UMP_KERNEL_LICENSE_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/ump_ioctl.h b/drivers/media/video/samsung/ump/linux/ump_ioctl.h
new file mode 100644
index 0000000..50ef9df
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_ioctl.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __UMP_IOCTL_H__
+#define __UMP_IOCTL_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#include "../common/ump_uk_types.h"
+
+#ifndef __user
+#define __user
+#endif
+
+
+/**
+ * @file UMP_ioctl.h
+ * This file describes the interface needed to use the Linux device driver.
+ * The interface is used by the userpace UMP driver.
+ */
+
+#define UMP_IOCTL_NR 0x90
+
+
+#define UMP_IOC_QUERY_API_VERSION _IOR(UMP_IOCTL_NR, _UMP_IOC_QUERY_API_VERSION, _ump_uk_api_version_s)
+#define UMP_IOC_ALLOCATE  _IOWR(UMP_IOCTL_NR,  _UMP_IOC_ALLOCATE,  _ump_uk_allocate_s)
+#define UMP_IOC_RELEASE  _IOR(UMP_IOCTL_NR,  _UMP_IOC_RELEASE,  _ump_uk_release_s)
+#define UMP_IOC_SIZE_GET  _IOWR(UMP_IOCTL_NR,  _UMP_IOC_SIZE_GET, _ump_uk_size_get_s)
+#define UMP_IOC_MSYNC     _IOW(UMP_IOCTL_NR,  _UMP_IOC_MSYNC, _ump_uk_size_get_s)
+#ifdef CONFIG_ION_EXYNOS
+#define UMP_IOC_ION_IMPORT  _IOW(UMP_IOCTL_NR,  _UMP_IOC_ION_IMPORT, _ump_uk_ion_import_s)
+#endif
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+#define UMP_IOC_DMABUF_IMPORT  _IOW(UMP_IOCTL_NR,  _UMP_IOC_DMABUF_IMPORT,\
+					struct ump_uk_dmabuf)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UMP_IOCTL_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_linux.c b/drivers/media/video/samsung/ump/linux/ump_kernel_linux.c
new file mode 100644
index 0000000..69f55c5
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_linux.c
@@ -0,0 +1,472 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>            /* kernel module definitions */
+#include <linux/fs.h>                /* file system operations */
+#include <linux/cdev.h>              /* character device definitions */
+#include <linux/ioport.h>            /* request_mem_region */
+#include <linux/mm.h>                /* memory management functions and types */
+#include <asm/uaccess.h>             /* user space access */
+#include <asm/atomic.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+
+#include "arch/config.h"             /* Configuration for current platform. The symlinc for arch is set by Makefile */
+#include "ump_ioctl.h"
+#include "ump_kernel_common.h"
+#include "ump_kernel_interface.h"
+#include "ump_kernel_interface_ref_drv.h"
+#include "ump_kernel_descriptor_mapping.h"
+#include "ump_kernel_memory_backend.h"
+#include "ump_kernel_memory_backend_os.h"
+#include "ump_kernel_memory_backend_dedicated.h"
+#include "ump_kernel_license.h"
+
+#include "ump_osk.h"
+#include "ump_ukk.h"
+#include "ump_uk_types.h"
+#include "ump_ukk_wrappers.h"
+#include "ump_ukk_ref_wrappers.h"
+
+#ifdef CONFIG_ION_EXYNOS
+#include <linux/ion.h>
+extern struct ion_device *ion_exynos;
+struct ion_client *ion_client_ump = NULL;
+#endif
+
+/* Module parameter to control log level */
+int ump_debug_level = 3;
+module_param(ump_debug_level, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
+MODULE_PARM_DESC(ump_debug_level, "Higher number, more dmesg output");
+
+/* By default the module uses any available major, but it's possible to set it at load time to a specific number */
+int ump_major = 243;
+module_param(ump_major, int, S_IRUGO); /* r--r--r-- */
+MODULE_PARM_DESC(ump_major, "Device major number");
+
+/* Name of the UMP device driver */
+static char ump_dev_name[] = "ump"; /* should be const, but the functions we call requires non-cost */
+
+
+static struct dentry *ump_debugfs_dir = NULL;
+
+/*
+ * The data which we attached to each virtual memory mapping request we get.
+ * Each memory mapping has a reference to the UMP memory it maps.
+ * We release this reference when the last memory mapping is unmapped.
+ */
+typedef struct ump_vma_usage_tracker
+{
+	int references;
+	ump_dd_handle handle;
+} ump_vma_usage_tracker;
+
+struct ump_device
+{
+	struct cdev cdev;
+#if UMP_LICENSE_IS_GPL
+	struct class * ump_class;
+#endif
+};
+
+/* The global variable containing the global device data */
+static struct ump_device ump_device;
+
+
+/* Forward declare static functions */
+static int ump_file_open(struct inode *inode, struct file *filp);
+static int ump_file_release(struct inode *inode, struct file *filp);
+#ifdef HAVE_UNLOCKED_IOCTL
+static long ump_file_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+#else
+static int ump_file_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
+#endif
+static int ump_file_mmap(struct file * filp, struct vm_area_struct * vma);
+
+#ifdef CONFIG_VIDEO_MALI400MP_R2P3
+extern int map_errcode( _mali_osk_errcode_t err );
+#endif
+
+/* This variable defines the file operations this UMP device driver offer */
+static struct file_operations ump_fops =
+{
+	.owner   = THIS_MODULE,
+	.open    = ump_file_open,
+	.release = ump_file_release,
+#ifdef HAVE_UNLOCKED_IOCTL
+	.unlocked_ioctl   = ump_file_ioctl,
+#else
+	.ioctl   = ump_file_ioctl,
+#endif
+	.mmap    = ump_file_mmap
+};
+
+
+/* This function is called by Linux to initialize this module.
+ * All we do is initialize the UMP device driver.
+ */
+static int ump_initialize_module(void)
+{
+	_mali_osk_errcode_t err;
+
+	DBG_MSG(2, ("Inserting UMP device driver. Compiled: %s, time: %s\n", __DATE__, __TIME__));
+
+	err = ump_kernel_constructor();
+	if (_MALI_OSK_ERR_OK != err)
+	{
+		MSG_ERR(("UMP device driver init failed\n"));
+		return map_errcode(err);
+	}
+
+	MSG(("UMP device driver %s loaded\n", SVN_REV_STRING));
+	return 0;
+}
+
+
+
+/*
+ * This function is called by Linux to unload/terminate/exit/cleanup this module.
+ * All we do is terminate the UMP device driver.
+ */
+static void ump_cleanup_module(void)
+{
+#ifdef CONFIG_ION_EXYNOS
+	if (ion_client_ump)
+	    ion_client_destroy(ion_client_ump);
+#endif
+
+	DBG_MSG(2, ("Unloading UMP device driver\n"));
+	ump_kernel_destructor();
+	DBG_MSG(2, ("Module unloaded\n"));
+}
+
+
+
+static ssize_t ump_memory_used_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+        char buf[64];
+        size_t r;
+        u32 mem = _ump_ukk_report_memory_usage();
+
+        r = snprintf(buf, 64, "%u\n", mem);
+        return simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
+}
+
+static const struct file_operations ump_memory_usage_fops = {
+        .owner = THIS_MODULE,
+        .read = ump_memory_used_read,
+};
+
+/*
+ * Initialize the UMP device driver.
+ */
+int ump_kernel_device_initialize(void)
+{
+	int err;
+	dev_t dev = 0;
+	ump_debugfs_dir = debugfs_create_dir(ump_dev_name, NULL);
+	if (ERR_PTR(-ENODEV) == ump_debugfs_dir)
+	{
+			ump_debugfs_dir = NULL;
+	}
+	else
+	{
+		debugfs_create_file("memory_usage", 0400, ump_debugfs_dir, NULL, &ump_memory_usage_fops);
+	}
+
+	if (0 == ump_major)
+	{
+		/* auto select a major */
+		err = alloc_chrdev_region(&dev, 0, 1, ump_dev_name);
+		ump_major = MAJOR(dev);
+	}
+	else
+	{
+		/* use load time defined major number */
+		dev = MKDEV(ump_major, 0);
+		err = register_chrdev_region(dev, 1, ump_dev_name);
+	}
+
+	if (0 == err)
+	{
+		memset(&ump_device, 0, sizeof(ump_device));
+
+		/* initialize our char dev data */
+		cdev_init(&ump_device.cdev, &ump_fops);
+		ump_device.cdev.owner = THIS_MODULE;
+		ump_device.cdev.ops = &ump_fops;
+
+		/* register char dev with the kernel */
+		err = cdev_add(&ump_device.cdev, dev, 1/*count*/);
+		if (0 == err)
+		{
+
+#if UMP_LICENSE_IS_GPL
+			ump_device.ump_class = class_create(THIS_MODULE, ump_dev_name);
+			if (IS_ERR(ump_device.ump_class))
+			{
+				err = PTR_ERR(ump_device.ump_class);
+			}
+			else
+			{
+				struct device * mdev;
+				mdev = device_create(ump_device.ump_class, NULL, dev, NULL, ump_dev_name);
+				if (!IS_ERR(mdev))
+				{
+					return 0;
+				}
+
+				err = PTR_ERR(mdev);
+			}
+			cdev_del(&ump_device.cdev);
+#else
+			return 0;
+#endif
+		}
+
+		unregister_chrdev_region(dev, 1);
+	}
+
+	return err;
+}
+
+
+
+/*
+ * Terminate the UMP device driver
+ */
+void ump_kernel_device_terminate(void)
+{
+	dev_t dev = MKDEV(ump_major, 0);
+
+#if UMP_LICENSE_IS_GPL
+	device_destroy(ump_device.ump_class, dev);
+	class_destroy(ump_device.ump_class);
+#endif
+
+	/* unregister char device */
+	cdev_del(&ump_device.cdev);
+
+	/* free major */
+	unregister_chrdev_region(dev, 1);
+
+	if(ump_debugfs_dir)
+		debugfs_remove_recursive(ump_debugfs_dir);
+}
+
+/*
+ * Open a new session. User space has called open() on us.
+ */
+static int ump_file_open(struct inode *inode, struct file *filp)
+{
+	struct ump_session_data * session_data;
+	_mali_osk_errcode_t err;
+
+	/* input validation */
+	if (0 != MINOR(inode->i_rdev))
+	{
+		MSG_ERR(("Minor not zero in ump_file_open()\n"));
+		return -ENODEV;
+	}
+
+	/* Call the OS-Independent UMP Open function */
+	err = _ump_ukk_open((void**) &session_data );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MSG_ERR(("Ump failed to open a new session\n"));
+		return map_errcode( err );
+	}
+
+	filp->private_data = (void*)session_data;
+	filp->f_pos = 0;
+
+	return 0; /* success */
+}
+
+
+
+/*
+ * Close a session. User space has called close() or crashed/terminated.
+ */
+static int ump_file_release(struct inode *inode, struct file *filp)
+{
+	_mali_osk_errcode_t err;
+
+	err = _ump_ukk_close((void**) &filp->private_data );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		return map_errcode( err );
+	}
+
+	return 0;  /* success */
+}
+
+
+
+/*
+ * Handle IOCTL requests.
+ */
+#ifdef HAVE_UNLOCKED_IOCTL
+static long ump_file_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+#else
+static int ump_file_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+#endif
+{
+	int err = -ENOTTY;
+	void __user * argument;
+	struct ump_session_data * session_data;
+
+#ifndef HAVE_UNLOCKED_IOCTL
+	(void)inode; /* inode not used */
+#endif
+
+	session_data = (struct ump_session_data *)filp->private_data;
+	if (NULL == session_data)
+	{
+		MSG_ERR(("No session data attached to file object\n"));
+		return -ENOTTY;
+	}
+
+	/* interpret the argument as a user pointer to something */
+	argument = (void __user *)arg;
+
+	switch (cmd)
+	{
+		case UMP_IOC_QUERY_API_VERSION:
+			err = ump_get_api_version_wrapper((u32 __user *)argument, session_data);
+			break;
+
+		case UMP_IOC_ALLOCATE :
+			err = ump_allocate_wrapper((u32 __user *)argument, session_data);
+			break;
+#ifdef CONFIG_ION_EXYNOS
+		case UMP_IOC_ION_IMPORT:
+			err = ump_ion_import_wrapper((u32 __user *)argument, session_data);
+			break;
+#endif
+#ifdef CONFIG_DMA_SHARED_BUFFER
+		case UMP_IOC_DMABUF_IMPORT:
+			err = ump_dmabuf_import_wrapper((u32 __user *)argument,
+							session_data);
+			break;
+#endif
+		case UMP_IOC_RELEASE:
+			err = ump_release_wrapper((u32 __user *)argument, session_data);
+			break;
+
+		case UMP_IOC_SIZE_GET:
+			err = ump_size_get_wrapper((u32 __user *)argument, session_data);
+			break;
+
+		case UMP_IOC_MSYNC:
+			err = ump_msync_wrapper((u32 __user *)argument, session_data);
+			break;
+
+		default:
+			DBG_MSG(1, ("No handler for IOCTL. cmd: 0x%08x, arg: 0x%08lx\n", cmd, arg));
+			err = -EFAULT;
+			break;
+	}
+
+	return err;
+}
+
+#ifndef CONFIG_VIDEO_MALI400MP_R2P3
+#ifndef CONFIG_VIDEO_MALI400MP
+#ifndef CONFIG_VIDEO_MALI400MP_R3P0
+int map_errcode( _mali_osk_errcode_t err )
+{
+    switch(err)
+    {
+        case _MALI_OSK_ERR_OK : return 0;
+        case _MALI_OSK_ERR_FAULT: return -EFAULT;
+        case _MALI_OSK_ERR_INVALID_FUNC: return -ENOTTY;
+        case _MALI_OSK_ERR_INVALID_ARGS: return -EINVAL;
+        case _MALI_OSK_ERR_NOMEM: return -ENOMEM;
+        case _MALI_OSK_ERR_TIMEOUT: return -ETIMEDOUT;
+        case _MALI_OSK_ERR_RESTARTSYSCALL: return -ERESTARTSYS;
+        case _MALI_OSK_ERR_ITEM_NOT_FOUND: return -ENOENT;
+        default: return -EFAULT;
+    }
+}
+#endif
+#endif
+#endif
+
+/*
+ * Handle from OS to map specified virtual memory to specified UMP memory.
+ */
+static int ump_file_mmap(struct file * filp, struct vm_area_struct * vma)
+{
+	_ump_uk_map_mem_s args;
+	_mali_osk_errcode_t err;
+	struct ump_session_data * session_data;
+
+	/* Validate the session data */
+	session_data = (struct ump_session_data *)filp->private_data;
+	if (NULL == session_data || NULL == session_data->cookies_map->table->mappings)
+	{
+		MSG_ERR(("mmap() called without any session data available\n"));
+		return -EFAULT;
+	}
+
+	/* Re-pack the arguments that mmap() packed for us */
+	args.ctx = session_data;
+	args.phys_addr = 0;
+	args.size = vma->vm_end - vma->vm_start;
+	args._ukk_private = vma;
+	args.secure_id = vma->vm_pgoff;
+	args.is_cached = 0;
+
+	if (!(vma->vm_flags & VM_SHARED))
+	{
+		args.is_cached = 1;
+		vma->vm_flags = vma->vm_flags | VM_SHARED | VM_MAYSHARE  ;
+		DBG_MSG(3, ("UMP Map function: Forcing the CPU to use cache\n"));
+	}
+
+	DBG_MSG(4, ("UMP vma->flags: %x\n", vma->vm_flags ));
+
+	/* Call the common mmap handler */
+	err = _ump_ukk_map_mem( &args );
+	if ( _MALI_OSK_ERR_OK != err)
+	{
+		MSG_ERR(("_ump_ukk_map_mem() failed in function ump_file_mmap()"));
+		return map_errcode( err );
+	}
+
+	return 0; /* success */
+}
+
+/* Export UMP kernel space API functions */
+EXPORT_SYMBOL(ump_dd_secure_id_get);
+EXPORT_SYMBOL(ump_dd_handle_create_from_secure_id);
+EXPORT_SYMBOL(ump_dd_phys_block_count_get);
+EXPORT_SYMBOL(ump_dd_phys_block_get);
+EXPORT_SYMBOL(ump_dd_phys_blocks_get);
+EXPORT_SYMBOL(ump_dd_size_get);
+EXPORT_SYMBOL(ump_dd_reference_add);
+EXPORT_SYMBOL(ump_dd_reference_release);
+EXPORT_SYMBOL(ump_dd_meminfo_get);
+EXPORT_SYMBOL(ump_dd_meminfo_set);
+EXPORT_SYMBOL(ump_dd_handle_get_from_vaddr);
+
+/* Export our own extended kernel space allocator */
+EXPORT_SYMBOL(ump_dd_handle_create_from_phys_blocks);
+
+/* Setup init and exit functions for this module */
+//module_init(ump_initialize_module);
+arch_initcall(ump_initialize_module);
+module_exit(ump_cleanup_module);
+
+/* And some module informatio */
+MODULE_LICENSE(UMP_KERNEL_LINUX_LICENSE);
+MODULE_AUTHOR("ARM Ltd.");
+MODULE_VERSION(SVN_REV_STRING);
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_linux.h b/drivers/media/video/samsung/ump/linux/ump_kernel_linux.h
new file mode 100644
index 0000000..b93c814e
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_linux.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __UMP_KERNEL_H__
+#define __UMP_KERNEL_H__
+
+int ump_kernel_device_initialize(void);
+void ump_kernel_device_terminate(void);
+
+
+#endif /* __UMP_KERNEL_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.c b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.c
new file mode 100644
index 0000000..4e6c9b5
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+#include <linux/semaphore.h>
+#else /* pre 2.6.26 the file was in the arch specific location */
+#include <asm/semaphore.h>
+#endif
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/atomic.h>
+#include <linux/vmalloc.h>
+#include "ump_kernel_common.h"
+#include "ump_kernel_memory_backend.h"
+
+
+
+#define UMP_BLOCK_SIZE (256UL * 1024UL)  /* 256kB, remember to keep the ()s */
+
+
+
+typedef struct block_info
+{
+	struct block_info * next;
+} block_info;
+
+
+
+typedef struct block_allocator
+{
+	struct semaphore mutex;
+	block_info * all_blocks;
+	block_info * first_free;
+	u32 base;
+	u32 num_blocks;
+	u32 num_free;
+} block_allocator;
+
+
+static void block_allocator_shutdown(ump_memory_backend * backend);
+static int block_allocator_allocate(void* ctx, ump_dd_mem * mem);
+static void block_allocator_release(void * ctx, ump_dd_mem * handle);
+static inline u32 get_phys(block_allocator * allocator, block_info * block);
+
+
+
+/*
+ * Create dedicated memory backend
+ */
+ump_memory_backend * ump_block_allocator_create(u32 base_address, u32 size)
+{
+	ump_memory_backend * backend;
+	block_allocator * allocator;
+	u32 usable_size;
+	u32 num_blocks;
+
+	usable_size = (size + UMP_BLOCK_SIZE - 1) & ~(UMP_BLOCK_SIZE - 1);
+	num_blocks = usable_size / UMP_BLOCK_SIZE;
+
+	if (0 == usable_size)
+	{
+		DBG_MSG(1, ("Memory block of size %u is unusable\n", size));
+		return NULL;
+	}
+
+	DBG_MSG(5, ("Creating dedicated UMP memory backend. Base address: 0x%08x, size: 0x%08x\n", base_address, size));
+	DBG_MSG(6, ("%u usable bytes which becomes %u blocks\n", usable_size, num_blocks));
+
+	backend = kzalloc(sizeof(ump_memory_backend), GFP_KERNEL);
+	if (NULL != backend)
+	{
+		allocator = kmalloc(sizeof(block_allocator), GFP_KERNEL);
+		if (NULL != allocator)
+		{
+			allocator->all_blocks = kmalloc(sizeof(block_allocator) * num_blocks, GFP_KERNEL);
+			if (NULL != allocator->all_blocks)
+			{
+				int i;
+
+				allocator->first_free = NULL;
+				allocator->num_blocks = num_blocks;
+				allocator->num_free = num_blocks;
+				allocator->base = base_address;
+				sema_init(&allocator->mutex, 1);
+
+				for (i = 0; i < num_blocks; i++)
+				{
+					allocator->all_blocks[i].next = allocator->first_free;
+					allocator->first_free = &allocator->all_blocks[i];
+				}
+
+				backend->ctx = allocator;
+				backend->allocate = block_allocator_allocate;
+				backend->release = block_allocator_release;
+				backend->shutdown = block_allocator_shutdown;
+				backend->pre_allocate_physical_check = NULL;
+				backend->adjust_to_mali_phys = NULL;
+				backend->get = NULL;
+				backend->set = NULL;
+
+				return backend;
+			}
+			kfree(allocator);
+		}
+		kfree(backend);
+	}
+
+	return NULL;
+}
+
+
+
+/*
+ * Destroy specified dedicated memory backend
+ */
+static void block_allocator_shutdown(ump_memory_backend * backend)
+{
+	block_allocator * allocator;
+
+	BUG_ON(!backend);
+	BUG_ON(!backend->ctx);
+
+	allocator = (block_allocator*)backend->ctx;
+
+	DBG_MSG_IF(1, allocator->num_free != allocator->num_blocks, ("%u blocks still in use during shutdown\n", allocator->num_blocks - allocator->num_free));
+
+	kfree(allocator->all_blocks);
+	kfree(allocator);
+	kfree(backend);
+}
+
+
+
+static int block_allocator_allocate(void* ctx, ump_dd_mem * mem)
+{
+	block_allocator * allocator;
+	u32 left;
+	block_info * last_allocated = NULL;
+	int i = 0;
+
+	BUG_ON(!ctx);
+	BUG_ON(!mem);
+
+	allocator = (block_allocator*)ctx;
+	left = mem->size_bytes;
+
+	BUG_ON(!left);
+	BUG_ON(!&allocator->mutex);
+
+	mem->nr_blocks = ((left + UMP_BLOCK_SIZE - 1) & ~(UMP_BLOCK_SIZE - 1)) / UMP_BLOCK_SIZE;
+	mem->block_array = (ump_dd_physical_block*)vmalloc(sizeof(ump_dd_physical_block) * mem->nr_blocks);
+	if (NULL == mem->block_array)
+	{
+		MSG_ERR(("Failed to allocate block array\n"));
+		return 0;
+	}
+
+	if (down_interruptible(&allocator->mutex))
+	{
+		MSG_ERR(("Could not get mutex to do block_allocate\n"));
+		return 0;
+	}
+
+	mem->size_bytes = 0;
+
+	while ((left > 0) && (allocator->first_free))
+	{
+		block_info * block;
+
+		block = allocator->first_free;
+		allocator->first_free = allocator->first_free->next;
+		block->next = last_allocated;
+		last_allocated = block;
+		allocator->num_free--;
+
+		mem->block_array[i].addr = get_phys(allocator, block);
+		mem->block_array[i].size = UMP_BLOCK_SIZE;
+		mem->size_bytes += UMP_BLOCK_SIZE;
+
+		i++;
+
+		if (left < UMP_BLOCK_SIZE) left = 0;
+		else left -= UMP_BLOCK_SIZE;
+	}
+
+	if (left)
+	{
+		block_info * block;
+		/* release all memory back to the pool */
+		while (last_allocated)
+		{
+			block = last_allocated->next;
+			last_allocated->next = allocator->first_free;
+			allocator->first_free = last_allocated;
+			last_allocated = block;
+			allocator->num_free++;
+		}
+
+		vfree(mem->block_array);
+		mem->backend_info = NULL;
+		mem->block_array = NULL;
+
+		DBG_MSG(4, ("Could not find a mem-block for the allocation.\n"));
+		up(&allocator->mutex);
+
+		return 0;
+	}
+
+	mem->backend_info = last_allocated;
+
+	up(&allocator->mutex);
+
+	return 1;
+}
+
+
+
+static void block_allocator_release(void * ctx, ump_dd_mem * handle)
+{
+	block_allocator * allocator;
+	block_info * block, * next;
+
+	BUG_ON(!ctx);
+	BUG_ON(!handle);
+
+	allocator = (block_allocator*)ctx;
+	block = (block_info*)handle->backend_info;
+	BUG_ON(!block);
+
+	if (down_interruptible(&allocator->mutex))
+	{
+		MSG_ERR(("Allocator release: Failed to get mutex - memory leak\n"));
+		return;
+	}
+
+	while (block)
+	{
+		next = block->next;
+
+		BUG_ON( (block < allocator->all_blocks) || (block > (allocator->all_blocks + allocator->num_blocks)));
+
+		block->next = allocator->first_free;
+		allocator->first_free = block;
+		allocator->num_free++;
+
+		block = next;
+	}
+	DBG_MSG(3, ("%d blocks free after release call\n", allocator->num_free));
+	up(&allocator->mutex);
+
+	vfree(handle->block_array);
+	handle->block_array = NULL;
+}
+
+
+
+/*
+ * Helper function for calculating the physical base adderss of a memory block
+ */
+static inline u32 get_phys(block_allocator * allocator, block_info * block)
+{
+	return allocator->base + ((block - allocator->all_blocks) * UMP_BLOCK_SIZE);
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.h b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.h
new file mode 100644
index 0000000..fa4bdcc
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_dedicated.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_memory_backend_dedicated.h
+ */
+
+#ifndef __UMP_KERNEL_MEMORY_BACKEND_DEDICATED_H__
+#define __UMP_KERNEL_MEMORY_BACKEND_DEDICATED_H__
+
+#include "ump_kernel_memory_backend.h"
+
+ump_memory_backend * ump_block_allocator_create(u32 base_address, u32 size);
+
+#endif /* __UMP_KERNEL_MEMORY_BACKEND_DEDICATED_H__ */
+
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.c b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.c
new file mode 100644
index 0000000..323c13c
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+#include <linux/semaphore.h>
+#else /* pre 2.6.26 the file was in the arch specific location */
+#include <asm/semaphore.h>
+#endif
+
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/atomic.h>
+#include <linux/vmalloc.h>
+#include <asm/cacheflush.h>
+#include "ump_kernel_common.h"
+#include "ump_kernel_memory_backend.h"
+
+
+
+typedef struct os_allocator
+{
+	struct semaphore mutex;
+	u32 num_pages_max;       /**< Maximum number of pages to allocate from the OS */
+	u32 num_pages_allocated; /**< Number of pages allocated from the OS */
+} os_allocator;
+
+
+
+static void os_free(void* ctx, ump_dd_mem * descriptor);
+static int os_allocate(void* ctx, ump_dd_mem * descriptor);
+static void os_memory_backend_destroy(ump_memory_backend * backend);
+static u32 os_stat(struct ump_memory_backend *backend);
+
+
+
+/*
+ * Create OS memory backend
+ */
+ump_memory_backend * ump_os_memory_backend_create(const int max_allocation)
+{
+	ump_memory_backend * backend;
+	os_allocator * info;
+
+	info = kmalloc(sizeof(os_allocator), GFP_KERNEL);
+	if (NULL == info)
+	{
+		return NULL;
+	}
+
+	info->num_pages_max = max_allocation >> PAGE_SHIFT;
+	info->num_pages_allocated = 0;
+
+	sema_init(&info->mutex, 1);
+
+	backend = kmalloc(sizeof(ump_memory_backend), GFP_KERNEL);
+	if (NULL == backend)
+	{
+		kfree(info);
+		return NULL;
+	}
+
+	backend->ctx = info;
+	backend->allocate = os_allocate;
+	backend->release = os_free;
+	backend->shutdown = os_memory_backend_destroy;
+	backend->stat = os_stat;
+	backend->pre_allocate_physical_check = NULL;
+	backend->adjust_to_mali_phys = NULL;
+	backend->get = NULL;
+	backend->set = NULL;
+
+	return backend;
+}
+
+
+
+/*
+ * Destroy specified OS memory backend
+ */
+static void os_memory_backend_destroy(ump_memory_backend * backend)
+{
+	os_allocator * info = (os_allocator*)backend->ctx;
+
+	DBG_MSG_IF(1, 0 != info->num_pages_allocated, ("%d pages still in use during shutdown\n", info->num_pages_allocated));
+
+	kfree(info);
+	kfree(backend);
+}
+
+
+
+/*
+ * Allocate UMP memory
+ */
+static int os_allocate(void* ctx, ump_dd_mem * descriptor)
+{
+	u32 left;
+	os_allocator * info;
+	int pages_allocated = 0;
+	int is_cached;
+
+	BUG_ON(!descriptor);
+	BUG_ON(!ctx);
+
+	info = (os_allocator*)ctx;
+	left = descriptor->size_bytes;
+	is_cached = descriptor->is_cached;
+
+	if (down_interruptible(&info->mutex))
+	{
+		DBG_MSG(1, ("Failed to get mutex in os_free\n"));
+		return 0; /* failure */
+	}
+
+	descriptor->backend_info = NULL;
+	descriptor->nr_blocks = ((left + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)) >> PAGE_SHIFT;
+
+	DBG_MSG(5, ("Allocating page array. Size: %lu\n", descriptor->nr_blocks * sizeof(ump_dd_physical_block)));
+
+	descriptor->block_array = (ump_dd_physical_block *)vmalloc(sizeof(ump_dd_physical_block) * descriptor->nr_blocks);
+	if (NULL == descriptor->block_array)
+	{
+		up(&info->mutex);
+		DBG_MSG(1, ("Block array could not be allocated\n"));
+		return 0; /* failure */
+	}
+
+	while (left > 0 && ((info->num_pages_allocated + pages_allocated) < info->num_pages_max))
+	{
+		struct page * new_page;
+
+		if (is_cached)
+		{
+			new_page = alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_NORETRY | __GFP_NOWARN );
+		} else
+		{
+			new_page = alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_NORETRY | __GFP_NOWARN | __GFP_COLD);
+		}
+		if (NULL == new_page)
+		{
+			MSG_ERR(("UMP memory allocated: Out of Memory !!\n"));
+			break;
+		}
+
+		/* Ensure page caches are flushed. */
+		if ( is_cached )
+		{
+			descriptor->block_array[pages_allocated].addr = page_to_phys(new_page);
+			descriptor->block_array[pages_allocated].size = PAGE_SIZE;
+		} else
+		{
+			descriptor->block_array[pages_allocated].addr = dma_map_page(NULL, new_page, 0, PAGE_SIZE, DMA_BIDIRECTIONAL );
+			descriptor->block_array[pages_allocated].size = PAGE_SIZE;
+		}
+
+		DBG_MSG(5, ("Allocated page 0x%08lx cached: %d\n", descriptor->block_array[pages_allocated].addr, is_cached));
+
+		if (left < PAGE_SIZE)
+		{
+			left = 0;
+		}
+		else
+		{
+			left -= PAGE_SIZE;
+		}
+
+		pages_allocated++;
+	}
+
+	DBG_MSG(5, ("Alloce for ID:%2d got %d pages, cached: %d\n", descriptor->secure_id,  pages_allocated));
+
+	if (left)
+	{
+		MSG_ERR(("Failed to allocate needed pages\n"));
+		MSG_ERR(("UMP memory allocated: %d kB  Configured maximum OS memory usage: %d kB\n",
+				 (pages_allocated * _MALI_OSK_CPU_PAGE_SIZE)/1024, (info->num_pages_max* _MALI_OSK_CPU_PAGE_SIZE)/1024));
+
+		while(pages_allocated)
+		{
+			pages_allocated--;
+			if ( !is_cached )
+			{
+				dma_unmap_page(NULL, descriptor->block_array[pages_allocated].addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
+			}
+			__free_page(pfn_to_page(descriptor->block_array[pages_allocated].addr >> PAGE_SHIFT) );
+		}
+
+		up(&info->mutex);
+
+		return 0; /* failure */
+	}
+
+	info->num_pages_allocated += pages_allocated;
+
+	DBG_MSG(6, ("%d out of %d pages now allocated\n", info->num_pages_allocated, info->num_pages_max));
+
+	up(&info->mutex);
+
+	return 1; /* success*/
+}
+
+
+/*
+ * Free specified UMP memory
+ */
+static void os_free(void* ctx, ump_dd_mem * descriptor)
+{
+	os_allocator * info;
+	int i;
+
+	BUG_ON(!ctx);
+	BUG_ON(!descriptor);
+
+	info = (os_allocator*)ctx;
+
+	BUG_ON(descriptor->nr_blocks > info->num_pages_allocated);
+
+	if (down_interruptible(&info->mutex))
+	{
+		DBG_MSG(1, ("Failed to get mutex in os_free\n"));
+		return;
+	}
+
+	DBG_MSG(5, ("Releasing %lu OS pages\n", descriptor->nr_blocks));
+
+	info->num_pages_allocated -= descriptor->nr_blocks;
+
+	up(&info->mutex);
+
+	for ( i = 0; i < descriptor->nr_blocks; i++)
+	{
+		DBG_MSG(6, ("Freeing physical page. Address: 0x%08lx\n", descriptor->block_array[i].addr));
+		if ( ! descriptor->is_cached)
+		{
+			dma_unmap_page(NULL, descriptor->block_array[i].addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
+		}
+		__free_page(pfn_to_page(descriptor->block_array[i].addr>>PAGE_SHIFT) );
+	}
+
+	vfree(descriptor->block_array);
+}
+
+
+static u32 os_stat(struct ump_memory_backend *backend)
+{
+	os_allocator *info;
+	info = (os_allocator*)backend->ctx;
+	return info->num_pages_allocated * _MALI_OSK_MALI_PAGE_SIZE;
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.h b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.h
new file mode 100644
index 0000000..f924705
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_os.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_memory_backend_os.h
+ */
+
+#ifndef __UMP_KERNEL_MEMORY_BACKEND_OS_H__
+#define __UMP_KERNEL_MEMORY_BACKEND_OS_H__
+
+#include "ump_kernel_memory_backend.h"
+
+ump_memory_backend * ump_os_memory_backend_create(const int max_allocation);
+
+#endif /* __UMP_KERNEL_MEMORY_BACKEND_OS_H__ */
+
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.c b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.c
new file mode 100644
index 0000000..de7f212
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/* create by boojin.kim@samsung.com */
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+#include <linux/semaphore.h>
+#else /* pre 2.6.26 the file was in the arch specific location */
+#include <asm/semaphore.h>
+#endif
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/atomic.h>
+#include <linux/vmalloc.h>
+#include <asm/cacheflush.h>
+#include "ump_kernel_common.h"
+#include "ump_kernel_memory_backend.h"
+#include "ump_kernel_interface_ref_drv.h"
+#include "ump_kernel_memory_backend_vcm.h"
+#include "../common/ump_uk_types.h"
+#include <linux/vcm-drv.h>
+#include <plat/s5p-vcm.h>
+#include <linux/dma-mapping.h>
+
+#define UMP_REF_DRV_UK_VCM_DEV_G2D 12
+
+typedef struct ump_vcm {
+	struct vcm *vcm;
+	struct vcm_res  *vcm_res;
+	unsigned int dev_id;
+} ump_vcm;
+
+typedef struct vcm_allocator {
+	struct semaphore mutex;
+	u32 num_vcm_blocks;
+} vcm_allocator;
+
+static void ump_vcm_free(void* ctx, ump_dd_mem * descriptor);
+static int ump_vcm_allocate(void* ctx, ump_dd_mem * descriptor);
+static void *vcm_res_get(ump_dd_mem *mem, void* args);
+static void vcm_attr_set(ump_dd_mem *mem, void* args);
+static int vcm_mem_allocator(vcm_allocator *info, ump_dd_mem *descriptor);
+static void vcm_memory_backend_destroy(ump_memory_backend * backend);
+
+
+/*
+ * Create VCM memory backend
+ */
+ump_memory_backend * ump_vcm_memory_backend_create(const int max_allocation)
+{
+	ump_memory_backend * backend;
+	vcm_allocator * info;
+
+	info = kmalloc(sizeof(vcm_allocator), GFP_KERNEL);
+	if (NULL == info)
+	{
+		return NULL;
+	}
+	
+	info->num_vcm_blocks = 0;
+	
+
+	sema_init(&info->mutex, 1);
+
+	backend = kmalloc(sizeof(ump_memory_backend), GFP_KERNEL);
+	if (NULL == backend)
+	{
+		kfree(info);
+		return NULL;
+	}
+
+	backend->ctx = info;
+	backend->allocate = ump_vcm_allocate;
+	backend->release = ump_vcm_free;
+	backend->shutdown = vcm_memory_backend_destroy;
+	backend->pre_allocate_physical_check = NULL;
+	backend->adjust_to_mali_phys = NULL;
+	
+	backend->get = vcm_res_get;
+	backend->set = vcm_attr_set;
+
+
+	return backend;
+}
+
+/*
+ * Destroy specified VCM memory backend
+ */
+static void vcm_memory_backend_destroy(ump_memory_backend * backend)
+{
+	vcm_allocator * info = (vcm_allocator*)backend->ctx;
+#if 0
+	DBG_MSG_IF(1, 0 != info->num_pages_allocated, ("%d pages still in use during shutdown\n", info->num_pages_allocated));
+#endif
+	kfree(info);
+	kfree(backend);
+}
+
+/*
+ * Allocate UMP memory
+ */
+static int ump_vcm_allocate(void *ctx, ump_dd_mem * descriptor)
+{
+	int ret;		/* success */
+	vcm_allocator *info;
+	struct ump_vcm *ump_vcm;
+
+	BUG_ON(!descriptor);
+	BUG_ON(!ctx);
+
+	info = (vcm_allocator*)ctx;
+
+	ump_vcm = kmalloc(sizeof(struct ump_vcm), GFP_KERNEL);
+	if (NULL == ump_vcm)
+	{
+		return 0;
+	}
+
+	ump_vcm->dev_id = (int)descriptor->backend_info & ~UMP_REF_DRV_UK_CONSTRAINT_USE_CACHE;
+
+	if(ump_vcm->dev_id == UMP_REF_DRV_UK_CONSTRAINT_NONE) { 	/* None */
+		ump_vcm->dev_id = UMP_REF_DRV_UK_VCM_DEV_G2D; 	/* this ID is G2D */
+	}
+	else if(ump_vcm->dev_id == UMP_REF_DRV_UK_CONSTRAINT_PHYSICALLY_LINEAR) { /* Physical Linear */
+		return 0;
+	}
+	else {				/* Other VCM */
+		ump_vcm->dev_id -= 2;
+	}
+	
+	DBG_MSG(5, ("Device ID for VCM : %d\n", ump_vcm->dev_id));
+	ump_vcm->vcm = vcm_find_vcm(ump_vcm->dev_id);
+
+	if (!ump_vcm->vcm)
+	{
+		return 0;
+	}
+	descriptor->backend_info = (void*)ump_vcm;
+	
+	if (down_interruptible(&info->mutex)) {
+		DBG_MSG(1, ("Failed to get mutex in ump_vcm_allocate\n"));
+		return 0;	/* failure */
+	}
+
+	ret = vcm_mem_allocator(info, descriptor);
+	up(&info->mutex);
+
+	return ret;		/* success */
+}
+
+static int vcm_mem_allocator(vcm_allocator *info, ump_dd_mem *descriptor)
+{
+	unsigned long num_blocks;
+	int i;
+	struct vcm_phys *phys;
+	struct vcm_phys_part *part;
+	int size_total = 0;
+	struct ump_vcm *ump_vcm;
+
+	ump_vcm = (struct ump_vcm*)descriptor->backend_info;
+	
+	ump_vcm->vcm_res =
+	    vcm_make_binding(ump_vcm->vcm, descriptor->size_bytes,
+	    ump_vcm->dev_id, 0);
+
+	phys = ump_vcm->vcm_res->phys;
+	part = phys->parts;
+	num_blocks = phys->count;
+
+	DBG_MSG(5,
+		("Allocating page array. Size: %lu, VCM Reservation : 0x%x\n",
+		 phys->count * sizeof(ump_dd_physical_block),
+		 ump_vcm->vcm_res->start));
+
+	/* Now, make a copy of the block information supplied by the user */
+	descriptor->block_array =
+	    (ump_dd_physical_block *) vmalloc(sizeof(ump_dd_physical_block) *
+					      num_blocks);
+
+	if (NULL == descriptor->block_array) {
+		vfree(descriptor->block_array);
+		DBG_MSG(1, ("Could not allocate a mem handle for function.\n"));
+		return 0; /* failure */
+	}
+
+	for (i = 0; i < num_blocks; i++) {
+		descriptor->block_array[i].addr = part->start;
+		descriptor->block_array[i].size = part->size;
+
+		dmac_unmap_area(phys_to_virt(part->start), part->size, DMA_FROM_DEVICE);
+		outer_inv_range(part->start, part->start + part->size);
+
+		++part;
+		size_total += descriptor->block_array[i].size;
+		DBG_MSG(6,
+			("UMP memory created with VCM. addr 0x%x, size: 0x%x\n",
+			 descriptor->block_array[i].addr,
+			 descriptor->block_array[i].size));
+	}
+
+	descriptor->size_bytes = size_total;
+	descriptor->nr_blocks = num_blocks;
+	descriptor->ctx = NULL;
+
+	info->num_vcm_blocks += num_blocks;
+	return 1;
+}
+
+/*
+ * Free specified UMP memory
+ */
+static void ump_vcm_free(void *ctx, ump_dd_mem * descriptor)
+{
+	struct ump_vcm *ump_vcm;
+	vcm_allocator *info;
+
+	BUG_ON(!descriptor);
+	BUG_ON(!ctx);
+
+	ump_vcm = (struct ump_vcm*)descriptor->backend_info;
+	info = (vcm_allocator*)ctx;
+
+	BUG_ON(descriptor->nr_blocks > info->num_vcm_blocks);
+
+	if (down_interruptible(&info->mutex)) {
+		DBG_MSG(1, ("Failed to get mutex in ump_vcm_free\n"));
+		return;
+	}
+
+	DBG_MSG(5, ("Releasing %lu VCM pages\n", descriptor->nr_blocks));
+
+	info->num_vcm_blocks -= descriptor->nr_blocks;
+
+	up(&info->mutex);
+
+	DBG_MSG(6, ("Freeing physical page by VCM\n"));
+	vcm_destroy_binding(ump_vcm->vcm_res);
+	ump_vcm->vcm = NULL;
+	ump_vcm->vcm_res = NULL;
+
+	kfree(ump_vcm);
+	vfree(descriptor->block_array);
+}
+
+static void *vcm_res_get(ump_dd_mem *mem, void *args)
+{
+	struct ump_vcm *ump_vcm;
+	enum vcm_dev_id vcm_id;
+
+	ump_vcm = (struct ump_vcm*)mem->backend_info;
+	vcm_id = (enum vcm_dev_id)args;
+
+	if (vcm_reservation_in_vcm
+		(vcm_find_vcm(vcm_id), ump_vcm->vcm_res)
+		== S5PVCM_RES_NOT_IN_VCM)
+		return NULL;
+	else
+		return ump_vcm->vcm_res;
+}
+
+static void vcm_attr_set(ump_dd_mem *mem, void *args)
+{
+	struct ump_vcm *ump_vcm, *ump_vcmh;
+
+	ump_vcm = (struct ump_vcm*)args;
+
+	ump_vcmh = kmalloc(sizeof(struct ump_vcm), GFP_KERNEL);
+        if (NULL == ump_vcmh)
+	{
+		return;
+	}
+
+	ump_vcmh->dev_id = ump_vcm->dev_id;
+	ump_vcmh->vcm = ump_vcm->vcm;
+	ump_vcmh->vcm_res = ump_vcm->vcm_res;
+
+	mem->backend_info= (void*)ump_vcmh;
+
+	return;
+}
+
+
diff --git a/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.h b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.h
new file mode 100644
index 0000000..62f6d12
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_kernel_memory_backend_vcm.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_kernel_memory_backend_vcm.h
+ */
+
+#ifndef __UMP_KERNEL_MEMORY_BACKEND_VCM_H__
+#define __UMP_KERNEL_MEMORY_BACKEND_VCM_H__
+
+#include "ump_kernel_memory_backend.h"
+
+ump_memory_backend * ump_vcm_memory_backend_create(const int max_allocation);
+
+#endif /* __UMP_KERNEL_MEMORY_BACKEND_VCM_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/ump_memory_backend.c b/drivers/media/video/samsung/ump/linux/ump_memory_backend.c
new file mode 100644
index 0000000..f2a6bd6
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_memory_backend.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>            /* kernel module definitions */
+#include <linux/ioport.h>            /* request_mem_region */
+
+#include "arch/config.h"             /* Configuration for current platform. The symlink for arch is set by Makefile */
+
+#include "ump_osk.h"
+#include "ump_kernel_common.h"
+#include "ump_kernel_memory_backend_os.h"
+#include "ump_kernel_memory_backend_dedicated.h"
+#include "ump_kernel_memory_backend_vcm.h"
+
+/* Configure which dynamic memory allocator to use */
+int ump_backend = ARCH_UMP_BACKEND_DEFAULT;
+module_param(ump_backend, int, S_IRUGO); /* r--r--r-- */
+MODULE_PARM_DESC(ump_backend, "0 = dedicated memory backend (default), 1 = OS memory backend");
+
+/* The base address of the memory block for the dedicated memory backend */
+unsigned int ump_memory_address = ARCH_UMP_MEMORY_ADDRESS_DEFAULT;
+module_param(ump_memory_address, uint, S_IRUGO); /* r--r--r-- */
+MODULE_PARM_DESC(ump_memory_address, "The physical address to map for the dedicated memory backend");
+
+/* The size of the memory block for the dedicated memory backend */
+unsigned int ump_memory_size = ARCH_UMP_MEMORY_SIZE_DEFAULT;
+module_param(ump_memory_size, uint, S_IRUGO); /* r--r--r-- */
+MODULE_PARM_DESC(ump_memory_size, "The size of fixed memory to map in the dedicated memory backend");
+
+ump_memory_backend* ump_memory_backend_create ( void )
+{
+	ump_memory_backend * backend = NULL;
+
+	/* Create the dynamic memory allocator backend */
+	if (0 == ump_backend)
+	{
+		DBG_MSG(2, ("Using dedicated memory backend\n"));
+
+		DBG_MSG(2, ("Requesting dedicated memory: 0x%08x, size: %u\n", ump_memory_address, ump_memory_size));
+		/* Ask the OS if we can use the specified physical memory */
+		if (NULL == request_mem_region(ump_memory_address, ump_memory_size, "UMP Memory"))
+		{
+			MSG_ERR(("Failed to request memory region (0x%08X - 0x%08X). Is Mali DD already loaded?\n", ump_memory_address, ump_memory_address + ump_memory_size - 1));
+			return NULL;
+		}
+		backend = ump_block_allocator_create(ump_memory_address, ump_memory_size);
+	}
+	else if (1 == ump_backend)
+	{
+		DBG_MSG(2, ("Using OS memory backend, allocation limit: %d\n", ump_memory_size));
+		backend = ump_os_memory_backend_create(ump_memory_size);
+	}
+#ifdef CONFIG_UMP_VCM_ALLOC
+	else if (2 == ump_backend)
+	{
+		DBG_MSG(2, ("Using VCM memory backend, allocation limit: %d\n", ump_memory_size));
+		backend = ump_vcm_memory_backend_create(ump_memory_size);
+	}
+#endif
+
+	return backend;
+}
+
+void ump_memory_backend_destroy( void )
+{
+	if (0 == ump_backend)
+	{
+		DBG_MSG(2, ("Releasing dedicated memory: 0x%08x\n", ump_memory_address));
+		release_mem_region(ump_memory_address, ump_memory_size);
+	}
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_osk_atomics.c b/drivers/media/video/samsung/ump/linux/ump_osk_atomics.c
new file mode 100644
index 0000000..ef1902e
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_osk_atomics.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_osk_atomics.c
+ * Implementation of the OS abstraction layer for the UMP kernel device driver
+ */
+
+#include "ump_osk.h"
+#include <asm/atomic.h>
+
+int _ump_osk_atomic_dec_and_read( _mali_osk_atomic_t *atom )
+{
+	return atomic_dec_return((atomic_t *)&atom->u.val);
+}
+
+int _ump_osk_atomic_inc_and_read( _mali_osk_atomic_t *atom )
+{
+	return atomic_inc_return((atomic_t *)&atom->u.val);
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_osk_low_level_mem.c b/drivers/media/video/samsung/ump/linux/ump_osk_low_level_mem.c
new file mode 100644
index 0000000..17af2bd
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_osk_low_level_mem.c
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_osk_memory.c
+ * Implementation of the OS abstraction layer for the kernel device driver
+ */
+
+/* needed to detect kernel version specific code */
+#include <linux/version.h>
+
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+#include "ump_ukk.h"
+#include "ump_kernel_common.h"
+#include <linux/module.h>            /* kernel module definitions */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include <asm/memory.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+typedef struct ump_vma_usage_tracker
+{
+	atomic_t references;
+	ump_memory_allocation *descriptor;
+} ump_vma_usage_tracker;
+
+static void ump_vma_open(struct vm_area_struct * vma);
+static void ump_vma_close(struct vm_area_struct * vma);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+static int ump_cpu_page_fault_handler(struct vm_area_struct *vma, struct vm_fault *vmf);
+#else
+static unsigned long ump_cpu_page_fault_handler(struct vm_area_struct * vma, unsigned long address);
+#endif
+
+static struct vm_operations_struct ump_vm_ops =
+{
+	.open = ump_vma_open,
+	.close = ump_vma_close,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	.fault = ump_cpu_page_fault_handler
+#else
+	.nopfn = ump_cpu_page_fault_handler
+#endif
+};
+
+/*
+ * Page fault for VMA region
+ * This should never happen since we always map in the entire virtual memory range.
+ */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+static int ump_cpu_page_fault_handler(struct vm_area_struct *vma, struct vm_fault *vmf)
+#else
+static unsigned long ump_cpu_page_fault_handler(struct vm_area_struct * vma, unsigned long address)
+#endif
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	void __user * address;
+	address = vmf->virtual_address;
+#endif
+	MSG_ERR(("Page-fault in UMP memory region caused by the CPU\n"));
+	MSG_ERR(("VMA: 0x%08lx, virtual address: 0x%08lx\n", (unsigned long)vma, address));
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+	return VM_FAULT_SIGBUS;
+#else
+	return NOPFN_SIGBUS;
+#endif
+}
+
+static void ump_vma_open(struct vm_area_struct * vma)
+{
+	ump_vma_usage_tracker * vma_usage_tracker;
+	int new_val;
+
+	vma_usage_tracker = (ump_vma_usage_tracker*)vma->vm_private_data;
+	BUG_ON(NULL == vma_usage_tracker);
+
+	new_val = atomic_inc_return(&vma_usage_tracker->references);
+
+	DBG_MSG(4, ("VMA open, VMA reference count incremented. VMA: 0x%08lx, reference count: %d\n", (unsigned long)vma, new_val));
+}
+
+static void ump_vma_close(struct vm_area_struct * vma)
+{
+	ump_vma_usage_tracker * vma_usage_tracker;
+	_ump_uk_unmap_mem_s args;
+	int new_val;
+
+	vma_usage_tracker = (ump_vma_usage_tracker*)vma->vm_private_data;
+	BUG_ON(NULL == vma_usage_tracker);
+
+	new_val = atomic_dec_return(&vma_usage_tracker->references);
+
+	DBG_MSG(4, ("VMA close, VMA reference count decremented. VMA: 0x%08lx, reference count: %d\n", (unsigned long)vma, new_val));
+
+	vma_usage_tracker->descriptor->process_mapping_info = vma;
+
+	if (0 == new_val)
+	{
+		ump_memory_allocation * descriptor;
+
+		descriptor = vma_usage_tracker->descriptor;
+
+		args.ctx = descriptor->ump_session;
+		args.cookie = descriptor->cookie;
+		args.mapping = descriptor->mapping;
+		args.size = descriptor->size;
+
+		args._ukk_private = NULL; /** @note unused */
+
+		DBG_MSG(4, ("No more VMA references left, releasing UMP memory\n"));
+		_ump_ukk_unmap_mem( & args );
+
+		/* vma_usage_tracker is free()d by _ump_osk_mem_mapregion_term() */
+	}
+}
+
+_mali_osk_errcode_t _ump_osk_mem_mapregion_init( ump_memory_allocation * descriptor )
+{
+	ump_vma_usage_tracker * vma_usage_tracker;
+	struct vm_area_struct *vma;
+
+	if (NULL == descriptor) return _MALI_OSK_ERR_FAULT;
+
+	vma_usage_tracker = kmalloc(sizeof(ump_vma_usage_tracker), GFP_KERNEL);
+	if (NULL == vma_usage_tracker)
+	{
+		DBG_MSG(1, ("Failed to allocate memory for ump_vma_usage_tracker in _mali_osk_mem_mapregion_init\n"));
+		return -_MALI_OSK_ERR_FAULT;
+	}
+
+	vma = (struct vm_area_struct*)descriptor->process_mapping_info;
+	if (NULL == vma )
+	{
+		kfree(vma_usage_tracker);
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	vma->vm_private_data = vma_usage_tracker;
+	vma->vm_flags |= VM_IO;
+	vma->vm_flags |= VM_RESERVED;
+
+	if (0==descriptor->is_cached)
+	{
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	}
+	DBG_MSG(3, ("Mapping with page_prot: 0x%x\n", vma->vm_page_prot ));
+
+	/* Setup the functions which handle further VMA handling */
+	vma->vm_ops = &ump_vm_ops;
+
+	/* Do the va range allocation - in this case, it was done earlier, so we copy in that information */
+	descriptor->mapping = (void __user*)vma->vm_start;
+
+	atomic_set(&vma_usage_tracker->references, 1); /*this can later be increased if process is forked, see ump_vma_open() */
+	vma_usage_tracker->descriptor = descriptor;
+
+	return _MALI_OSK_ERR_OK;
+}
+
+void _ump_osk_mem_mapregion_term( ump_memory_allocation * descriptor )
+{
+	struct vm_area_struct* vma;
+	ump_vma_usage_tracker * vma_usage_tracker;
+
+	if (NULL == descriptor) return;
+
+	/* Linux does the right thing as part of munmap to remove the mapping
+	 * All that remains is that we remove the vma_usage_tracker setup in init() */
+	vma = (struct vm_area_struct*)descriptor->process_mapping_info;
+
+	vma_usage_tracker = vma->vm_private_data;
+
+	/* We only get called if mem_mapregion_init succeeded */
+	kfree(vma_usage_tracker);
+	return;
+}
+
+_mali_osk_errcode_t _ump_osk_mem_mapregion_map( ump_memory_allocation * descriptor, u32 offset, u32 * phys_addr, unsigned long size )
+{
+	struct vm_area_struct *vma;
+	_mali_osk_errcode_t retval;
+
+	if (NULL == descriptor) return _MALI_OSK_ERR_FAULT;
+
+	vma = (struct vm_area_struct*)descriptor->process_mapping_info;
+
+	if (NULL == vma ) return _MALI_OSK_ERR_FAULT;
+
+	retval = remap_pfn_range( vma, ((u32)descriptor->mapping) + offset, (*phys_addr) >> PAGE_SHIFT, size, vma->vm_page_prot) ? _MALI_OSK_ERR_FAULT : _MALI_OSK_ERR_OK;;
+
+		DBG_MSG(4, ("Mapping virtual to physical memory. ID: %u, vma: 0x%08lx, virtual addr:0x%08lx, physical addr: 0x%08lx, size:%lu, prot:0x%x, vm_flags:0x%x RETVAL: 0x%x\n",
+		        ump_dd_secure_id_get(descriptor->handle),
+		        (unsigned long)vma,
+		        (unsigned long)(vma->vm_start + offset),
+		        (unsigned long)*phys_addr,
+		        size,
+		        (unsigned int)vma->vm_page_prot, vma->vm_flags, retval));
+
+	return retval;
+}
+
+static u32 _ump_osk_virt_to_phys_start(ump_dd_mem * mem, u32 start, u32 address, int *index)
+{
+	int i;
+	u32 offset = address - start;
+	ump_dd_physical_block *block;
+	u32 sum = 0;
+
+	for (i=0; i<mem->nr_blocks; i++) {
+		block = &mem->block_array[i];
+		sum += block->size;
+		if (sum > offset) {
+			*index = i;
+			DBG_MSG(3, ("_ump_osk_virt_to_phys : index : %d, virtual 0x%x, phys 0x%x\n", i, address, (u32)block->addr + offset - (sum -block->size)));
+			return (u32)block->addr + offset - (sum -block->size);
+		}
+	}
+
+	return _MALI_OSK_ERR_FAULT;
+}
+
+static u32 _ump_osk_virt_to_phys_end(ump_dd_mem * mem, u32 start, u32 address, int *index)
+{
+	int i;
+	u32 offset = address - start;
+	ump_dd_physical_block *block;
+	u32 sum = 0;
+
+	for (i=0; i<mem->nr_blocks; i++) {
+		block = &mem->block_array[i];
+		sum += block->size;
+		if (sum >= offset) {
+			*index = i;
+			DBG_MSG(3, ("_ump_osk_virt_to_phys : index : %d, virtual 0x%x, phys 0x%x\n", i, address, (u32)block->addr + offset - (sum -block->size)));
+			return (u32)block->addr + offset - (sum -block->size);
+		}
+	}
+
+	return _MALI_OSK_ERR_FAULT;
+}
+
+static void _ump_osk_msync_with_virt(ump_dd_mem * mem, ump_uk_msync_op op, u32 start, u32 address, u32 size)
+{
+	int start_index, end_index;
+	u32 start_p, end_p;
+
+	DBG_MSG(3, ("Cache flush with user virtual address. start : 0x%x, end : 0x%x, address 0x%x, size 0x%x\n", start, start+mem->size_bytes, address, size));
+
+	start_p = _ump_osk_virt_to_phys_start(mem, start, address, &start_index);
+	end_p = _ump_osk_virt_to_phys_end(mem, start, address+size, &end_index);
+
+	if (start_index==end_index) {
+		if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE)
+			outer_flush_range(start_p, end_p);
+		else
+			outer_clean_range(start_p, end_p);
+	} else {
+		ump_dd_physical_block *block;
+		int i;
+
+		for (i=start_index; i<=end_index; i++) {
+			block = &mem->block_array[i];
+
+			if (i == start_index) {
+				if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE) {
+					outer_flush_range(start_p, block->addr+block->size);
+				} else {
+					outer_clean_range(start_p, block->addr+block->size);
+				}
+			}
+			else if (i == end_index) {
+				if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE) {
+					outer_flush_range(block->addr, end_p);
+				} else {
+					outer_clean_range(block->addr, end_p);
+				}
+				break;
+			}
+			else {
+				if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE) {
+					outer_flush_range(block->addr, block->addr+block->size);
+				} else {
+					outer_clean_range(block->addr, block->addr+block->size);
+				}
+			}
+		}
+	}
+	return;
+}
+
+void _ump_osk_msync( ump_dd_mem * mem, ump_uk_msync_op op, u32 start, u32 address, u32 size)
+{
+	int i;
+	u32 start_p, end_p;
+	ump_dd_physical_block *block;
+
+	DBG_MSG(3,
+		("Flushing nr of blocks: %u. First: paddr: 0x%08x vaddr: 0x%08x size:%dB\n",
+		 mem->nr_blocks, mem->block_array[0].addr,
+		 phys_to_virt(mem->block_array[0].addr),
+		 mem->block_array[0].size));
+
+#ifndef USING_DMA_FLUSH
+	if (address) {
+		if ((address >= start)
+		    && ((address + size) <= start + mem->size_bytes)) {
+			if (size >= SZ_64K) {
+				flush_all_cpu_caches();
+			} else if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE)
+				dmac_flush_range((void *)address,
+						 (void *)(address + size - 1));
+			else
+				dmac_map_area((void *)address, size,
+					      DMA_TO_DEVICE);
+#ifdef CONFIG_CACHE_L2X0
+			if (size >= SZ_1M)
+				outer_clean_all();
+			else
+				_ump_osk_msync_with_virt(mem, op, start, address, size);
+#endif
+			return;
+		}
+	}
+
+	if ((op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE)) {
+		if ((mem->size_bytes >= SZ_1M)) {
+			flush_all_cpu_caches();
+#ifdef CONFIG_CACHE_L2X0
+			outer_flush_all();
+#endif
+			return;
+		} else if ((mem->size_bytes >= SZ_64K)) {
+			flush_all_cpu_caches();
+#ifdef CONFIG_CACHE_L2X0
+			for (i = 0; i < mem->nr_blocks; i++) {
+				block = &mem->block_array[i];
+				start_p = (u32) block->addr;
+				end_p = start_p + block->size - 1;
+				outer_flush_range(start_p, end_p);
+			}
+#endif
+			return;
+		}
+	} else {
+		if ((mem->size_bytes >= SZ_1M)) {
+			flush_all_cpu_caches();
+#ifdef CONFIG_CACHE_L2X0
+			outer_clean_all();
+#endif
+			return;
+		} else if ((mem->size_bytes >= SZ_64K)) {
+			flush_all_cpu_caches();
+#ifdef CONFIG_CACHE_L2X0
+			for (i = 0; i < mem->nr_blocks; i++) {
+				block = &mem->block_array[i];
+				start_p = (u32) block->addr;
+				end_p = start_p + block->size - 1;
+				outer_clean_range(start_p, end_p);
+			}
+#endif
+			return;
+		}
+	}
+#endif
+
+	for (i = 0; i < mem->nr_blocks; i++) {
+		/* TODO: Find out which flush method is best of 1)Dma OR  2)Normal flush functions */
+		/*#define USING_DMA_FLUSH */
+#ifdef USING_DMA_FLUSH
+		DEBUG_ASSERT((PAGE_SIZE == mem->block_array[i].size));
+		dma_map_page(NULL,
+			     pfn_to_page(mem->block_array[i].
+					 addr >> PAGE_SHIFT), 0, PAGE_SIZE,
+			     DMA_BIDIRECTIONAL);
+		/*dma_unmap_page(NULL, mem->block_array[i].addr, PAGE_SIZE, DMA_BIDIRECTIONAL); */
+#else
+		block = &mem->block_array[i];
+		start_p = (u32) block->addr;
+		end_p = start_p + block->size - 1;
+		if (op == _UMP_UK_MSYNC_CLEAN_AND_INVALIDATE) {
+			dmac_flush_range(phys_to_virt(start_p),
+					 phys_to_virt(end_p));
+			outer_flush_range(start_p, end_p);
+		} else {
+			dmac_map_area(phys_to_virt(start_p), block->size,
+				      DMA_TO_DEVICE);
+			outer_clean_range(start_p, end_p);
+		}
+#endif
+	}
+}
+
+
+void _ump_osk_mem_mapregion_get( ump_dd_mem ** mem, unsigned long vaddr)
+{
+	struct mm_struct *mm = current->mm;
+	struct vm_area_struct *vma;
+	ump_vma_usage_tracker * vma_usage_tracker;
+	ump_memory_allocation *descriptor;
+	ump_dd_handle handle;
+
+	DBG_MSG(3, ("_ump_osk_mem_mapregion_get: vaddr 0x%08lx\n", vaddr));
+
+	down_read(&mm->mmap_sem);
+	vma = find_vma(mm, vaddr);
+	up_read(&mm->mmap_sem);
+	if(!vma)
+	{
+		DBG_MSG(3, ("Not found VMA\n"));
+		*mem = NULL;
+		return;
+	}
+	DBG_MSG(4, ("Get vma: 0x%08lx vma->vm_start: 0x%08lx\n", (unsigned long)vma, vma->vm_start));
+
+	vma_usage_tracker = (struct ump_vma_usage_tracker*)vma->vm_private_data;
+	if(vma_usage_tracker == NULL)
+	{
+		DBG_MSG(3, ("Not found vma_usage_tracker\n"));
+		*mem = NULL;
+		return;
+	}
+
+	descriptor = (struct ump_memory_allocation*)vma_usage_tracker->descriptor;
+	handle = (ump_dd_handle)descriptor->handle;
+
+	DBG_MSG(3, ("Get handle: 0x%08lx\n", handle));
+	*mem = (ump_dd_mem*)handle;
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_osk_misc.c b/drivers/media/video/samsung/ump/linux/ump_osk_misc.c
new file mode 100644
index 0000000..12066eb
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_osk_misc.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_osk_misc.c
+ * Implementation of the OS abstraction layer for the UMP kernel device driver
+ */
+
+
+#include "ump_osk.h"
+
+#include <linux/kernel.h>
+#include "ump_kernel_linux.h"
+
+/* is called from ump_kernel_constructor in common code */
+_mali_osk_errcode_t _ump_osk_init( void )
+{
+	if (0 != ump_kernel_device_initialize())
+	{
+		return _MALI_OSK_ERR_FAULT;
+	}
+
+	return _MALI_OSK_ERR_OK;
+}
+
+_mali_osk_errcode_t _ump_osk_term( void )
+{
+	ump_kernel_device_terminate();
+	return _MALI_OSK_ERR_OK;
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.c b/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.c
new file mode 100644
index 0000000..3e355c0
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_ukk_wrappers.c
+ * Defines the wrapper functions which turn Linux IOCTL calls into _ukk_ calls for the reference implementation
+ */
+
+
+#include <asm/uaccess.h>             /* user space access */
+
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+#include "ump_ukk.h"
+#include "ump_kernel_common.h"
+
+#if defined(CONFIG_ION_EXYNOS) || defined(CONFIG_DMA_SHARED_BUFFER)
+#include <linux/scatterlist.h>
+#include "ump_kernel_interface_ref_drv.h"
+#include "mali_osk_list.h"
+#ifdef CONFIG_ION_EXYNOS
+#include <linux/ion.h>
+#include "../../../../../gpu/ion/ion_priv.h"
+extern struct ion_device *ion_exynos;
+extern struct ion_client *ion_client_ump;
+#endif
+#ifdef CONFIG_DMA_SHARED_BUFFER
+#include <linux/dma-buf.h>
+#endif
+#endif
+
+/*
+ * IOCTL operation; Allocate UMP memory
+ */
+int ump_allocate_wrapper(u32 __user * argument, struct ump_session_data  * session_data)
+{
+	_ump_uk_allocate_s user_interaction;
+	_mali_osk_errcode_t err;
+
+	/* Sanity check input parameters */
+	if (NULL == argument || NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_allocate()\n"));
+		return -ENOTTY;
+	}
+
+	/* Copy the user space memory to kernel space (so we safely can read it) */
+	if (0 != copy_from_user(&user_interaction, argument, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_allocate()\n"));
+		return -EFAULT;
+	}
+
+	user_interaction.ctx = (void *) session_data;
+
+	err = _ump_ukk_allocate( &user_interaction );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		DBG_MSG(1, ("_ump_ukk_allocate() failed in ump_ioctl_allocate()\n"));
+		return map_errcode(err);
+	}
+	user_interaction.ctx = NULL;
+
+	if (0 != copy_to_user(argument, &user_interaction, sizeof(user_interaction)))
+	{
+		/* If the copy fails then we should release the memory. We can use the IOCTL release to accomplish this */
+		_ump_uk_release_s release_args;
+
+		MSG_ERR(("copy_to_user() failed in ump_ioctl_allocate()\n"));
+
+		release_args.ctx = (void *) session_data;
+		release_args.secure_id = user_interaction.secure_id;
+
+		err = _ump_ukk_release( &release_args );
+		if(_MALI_OSK_ERR_OK != err)
+		{
+			MSG_ERR(("_ump_ukk_release() also failed when trying to release newly allocated memory in ump_ioctl_allocate()\n"));
+		}
+
+		return -EFAULT;
+	}
+
+	return 0; /* success */
+}
+
+#ifdef CONFIG_ION_EXYNOS
+/*
+ * IOCTL operation; Import fd to  UMP memory
+ */
+int ump_ion_import_wrapper(u32 __user * argument, struct ump_session_data  * session_data)
+{
+	_ump_uk_ion_import_s user_interaction;
+	ump_dd_handle *ump_handle;
+	ump_dd_physical_block * blocks;
+	unsigned long num_blocks;
+	struct ion_handle *ion_hnd;
+	struct scatterlist *sg;
+	struct scatterlist *sg_ion;
+	unsigned long i = 0;
+
+	ump_session_memory_list_element * session_memory_element = NULL;
+	if (ion_client_ump==NULL)
+	    ion_client_ump = ion_client_create(ion_exynos, -1, "ump");
+
+	/* Sanity check input parameters */
+	if (NULL == argument || NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_allocate()\n"));
+		return -ENOTTY;
+	}
+
+	/* Copy the user space memory to kernel space (so we safely can read it) */
+	if (0 != copy_from_user(&user_interaction, argument, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_allocate()\n"));
+		return -EFAULT;
+	}
+
+	user_interaction.ctx = (void *) session_data;
+
+	/* translate fd to secure ID*/
+	ion_hnd = ion_import_fd(ion_client_ump, user_interaction.ion_fd);
+	sg_ion = ion_map_dma(ion_client_ump,ion_hnd);
+
+	blocks = (ump_dd_physical_block*)_mali_osk_malloc(sizeof(ump_dd_physical_block)*1024);
+	sg = sg_ion;
+	do {
+		blocks[i].addr = sg_phys(sg);
+		blocks[i].size = sg_dma_len(sg);
+		i++;
+		if (i>=1024) {
+			_mali_osk_free(blocks);
+			MSG_ERR(("ion_import fail() in ump_ioctl_allocate()\n"));
+			return -EFAULT;
+		}
+		sg = sg_next(sg);
+	} while(sg);
+
+	num_blocks = i;
+
+	/* Initialize the session_memory_element, and add it to the session object */
+	session_memory_element = _mali_osk_calloc( 1, sizeof(ump_session_memory_list_element));
+
+	if (NULL == session_memory_element)
+	{
+		_mali_osk_free(blocks);
+		DBG_MSG(1, ("Failed to allocate ump_session_memory_list_element in ump_ioctl_allocate()\n"));
+		return -EFAULT;
+	}
+
+	ump_handle = ump_dd_handle_create_from_phys_blocks(blocks, num_blocks);
+	if (UMP_DD_HANDLE_INVALID == ump_handle)
+	{
+		_mali_osk_free(session_memory_element);
+		_mali_osk_free(blocks);
+		DBG_MSG(1, ("Failed to allocate ump_session_memory_list_element in ump_ioctl_allocate()\n"));
+		return -EFAULT;
+	}
+
+	session_memory_element->mem = (ump_dd_mem*)ump_handle;
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_list_add(&(session_memory_element->list), &(session_data->list_head_session_memory_list));
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	ion_unmap_dma(ion_client_ump,ion_hnd);
+	ion_free(ion_client_ump, ion_hnd);
+
+	_mali_osk_free(blocks);
+
+	user_interaction.secure_id = ump_dd_secure_id_get(ump_handle);
+	user_interaction.size = ump_dd_size_get(ump_handle);
+	user_interaction.ctx = NULL;
+
+	if (0 != copy_to_user(argument, &user_interaction, sizeof(user_interaction)))
+	{
+		/* If the copy fails then we should release the memory. We can use the IOCTL release to accomplish this */
+
+		MSG_ERR(("copy_to_user() failed in ump_ioctl_allocate()\n"));
+
+		return -EFAULT;
+	}
+	return 0; /* success */
+}
+#endif
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+int ump_dmabuf_import_wrapper(u32 __user *argument,
+				struct ump_session_data  *session_data)
+{
+	ump_session_memory_list_element *session = NULL;
+	struct ump_uk_dmabuf ump_dmabuf;
+	ump_dd_handle *ump_handle;
+	ump_dd_physical_block *blocks;
+	struct dma_buf_attachment *attach;
+	struct dma_buf *dma_buf;
+	struct sg_table *sgt;
+	struct scatterlist *sgl;
+	unsigned long block_size;
+	/* FIXME */
+	struct device dev;
+	unsigned int i = 0, npages;
+	int ret;
+
+	/* Sanity check input parameters */
+	if (!argument || !session_data) {
+		MSG_ERR(("NULL parameter.\n"));
+		return -EINVAL;
+	}
+
+	if (copy_from_user(&ump_dmabuf, argument,
+				sizeof(struct ump_uk_dmabuf))) {
+		MSG_ERR(("copy_from_user() failed.\n"));
+		return -EFAULT;
+	}
+
+	dma_buf = dma_buf_get(ump_dmabuf.fd);
+	if (IS_ERR(dma_buf))
+		return PTR_ERR(dma_buf);
+
+	/*
+	 * check whether dma_buf imported already exists or not.
+	 *
+	 * TODO
+	 * if already imported then dma_buf_put() should be called
+	 * and then just return dma_buf imported.
+	 */
+
+	attach = dma_buf_attach(dma_buf, &dev);
+	if (IS_ERR(attach)) {
+		ret = PTR_ERR(attach);
+		goto err_dma_buf_put;
+	}
+
+	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+	if (IS_ERR(sgt)) {
+		ret = PTR_ERR(sgt);
+		goto err_dma_buf_detach;
+	}
+
+	npages = sgt->nents;
+
+	/* really need? */
+	ump_dmabuf.ctx = (void *)session_data;
+
+	block_size = sizeof(ump_dd_physical_block) * npages;
+
+	blocks = (ump_dd_physical_block *)_mali_osk_malloc(block_size);
+	sgl = sgt->sgl;
+
+	while (i < npages) {
+		blocks[i].addr = sg_phys(sgl);
+		blocks[i].size = sg_dma_len(sgl);
+		sgl = sg_next(sgl);
+		i++;
+	}
+
+	/*
+	 * Initialize the session memory list element, and add it
+	 * to the session object
+	 */
+	session = _mali_osk_calloc(1, sizeof(*session));
+	if (!session) {
+		DBG_MSG(1, ("Failed to allocate session.\n"));
+		ret = -EFAULT;
+		goto err_free_block;
+	}
+
+	ump_handle = ump_dd_handle_create_from_phys_blocks(blocks, i);
+	if (UMP_DD_HANDLE_INVALID == ump_handle) {
+		DBG_MSG(1, ("Failed to create ump handle.\n"));
+		ret = -EFAULT;
+		goto err_free_session;
+	}
+
+	session->mem = (ump_dd_mem *)ump_handle;
+
+	_mali_osk_lock_wait(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+	_mali_osk_list_add(&(session->list),
+			&(session_data->list_head_session_memory_list));
+	_mali_osk_lock_signal(session_data->lock, _MALI_OSK_LOCKMODE_RW);
+
+	_mali_osk_free(blocks);
+
+	ump_dmabuf.ump_handle = (uint32_t)ump_handle;
+	ump_dmabuf.size = ump_dd_size_get(ump_handle);
+
+	if (copy_to_user(argument, &ump_dmabuf,
+				sizeof(struct ump_uk_dmabuf))) {
+		MSG_ERR(("copy_to_user() failed.\n"));
+		ret =  -EFAULT;
+		goto err_release_ump_handle;
+	}
+
+	return 0;
+
+err_release_ump_handle:
+	ump_dd_reference_release(ump_handle);
+err_free_session:
+	_mali_osk_free(session);
+err_free_block:
+	_mali_osk_free(blocks);
+	dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
+err_dma_buf_detach:
+	dma_buf_detach(dma_buf, attach);
+err_dma_buf_put:
+	dma_buf_put(dma_buf);
+	return ret;
+}
+#endif
diff --git a/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.h b/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.h
new file mode 100644
index 0000000..7bd4660
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_ukk_ref_wrappers.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_ukk_wrappers.h
+ * Defines the wrapper functions which turn Linux IOCTL calls into _ukk_ calls for the reference implementation
+ */
+
+#ifndef __UMP_UKK_REF_WRAPPERS_H__
+#define __UMP_UKK_REF_WRAPPERS_H__
+
+#include <linux/kernel.h>
+#include "ump_kernel_common.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+int ump_allocate_wrapper(u32 __user * argument, struct ump_session_data  * session_data);
+
+#ifdef CONFIG_ION_EXYNOS
+int ump_ion_import_wrapper(u32 __user * argument, struct ump_session_data  * session_data);
+#endif
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+int ump_dmabuf_import_wrapper(u32 __user *argument,
+				struct ump_session_data  *session_data);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UMP_UKK_REF_WRAPPERS_H__ */
diff --git a/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.c b/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.c
new file mode 100644
index 0000000..8b73ca8
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_ukk_wrappers.c
+ * Defines the wrapper functions which turn Linux IOCTL calls into _ukk_ calls
+ */
+
+#include <asm/uaccess.h>             /* user space access */
+
+#include "ump_osk.h"
+#include "ump_uk_types.h"
+#include "ump_ukk.h"
+#include "ump_kernel_common.h"
+
+/*
+ * IOCTL operation; Negotiate version of IOCTL API
+ */
+int ump_get_api_version_wrapper(u32 __user * argument, struct ump_session_data * session_data)
+{
+	_ump_uk_api_version_s version_info;
+	_mali_osk_errcode_t err;
+
+	/* Sanity check input parameters */
+	if (NULL == argument || NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_get_api_version()\n"));
+		return -ENOTTY;
+	}
+
+	/* Copy the user space memory to kernel space (so we safely can read it) */
+	if (0 != copy_from_user(&version_info, argument, sizeof(version_info)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_get_api_version()\n"));
+		return -EFAULT;
+	}
+
+	version_info.ctx = (void*) session_data;
+	err = _ump_uku_get_api_version( &version_info );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MSG_ERR(("_ump_uku_get_api_version() failed in ump_ioctl_get_api_version()\n"));
+		return map_errcode(err);
+	}
+
+	version_info.ctx = NULL;
+
+	/* Copy ouput data back to user space */
+	if (0 != copy_to_user(argument, &version_info, sizeof(version_info)))
+	{
+		MSG_ERR(("copy_to_user() failed in ump_ioctl_get_api_version()\n"));
+		return -EFAULT;
+	}
+
+	return 0; /* success */
+}
+
+
+/*
+ * IOCTL operation; Release reference to specified UMP memory.
+ */
+int ump_release_wrapper(u32 __user * argument, struct ump_session_data  * session_data)
+{
+	_ump_uk_release_s release_args;
+	_mali_osk_errcode_t err;
+
+	/* Sanity check input parameters */
+	if (NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_release()\n"));
+		return -ENOTTY;
+	}
+
+	/* Copy the user space memory to kernel space (so we safely can read it) */
+	if (0 != copy_from_user(&release_args, argument, sizeof(release_args)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_get_api_version()\n"));
+		return -EFAULT;
+	}
+
+	release_args.ctx = (void*) session_data;
+	err = _ump_ukk_release( &release_args );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MSG_ERR(("_ump_ukk_release() failed in ump_ioctl_release()\n"));
+		return map_errcode(err);
+	}
+
+
+	return 0; /* success */
+}
+
+/*
+ * IOCTL operation; Return size for specified UMP memory.
+ */
+int ump_size_get_wrapper(u32 __user * argument, struct ump_session_data  * session_data)
+{
+	_ump_uk_size_get_s user_interaction;
+	_mali_osk_errcode_t err;
+
+	/* Sanity check input parameters */
+	if (NULL == argument || NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_size_get()\n"));
+		return -ENOTTY;
+	}
+
+	if (0 != copy_from_user(&user_interaction, argument, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_size_get()\n"));
+		return -EFAULT;
+	}
+
+	user_interaction.ctx = (void *) session_data;
+	err = _ump_ukk_size_get( &user_interaction );
+	if( _MALI_OSK_ERR_OK != err )
+	{
+		MSG_ERR(("_ump_ukk_size_get() failed in ump_ioctl_size_get()\n"));
+		return map_errcode(err);
+	}
+
+	user_interaction.ctx = NULL;
+
+	if (0 != copy_to_user(argument, &user_interaction, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_to_user() failed in ump_ioctl_size_get()\n"));
+		return -EFAULT;
+	}
+
+	return 0; /* success */
+}
+
+/*
+ * IOCTL operation; Return size for specified UMP memory.
+ */
+ int ump_msync_wrapper(u32 __user * argument, struct ump_session_data  * session_data)
+{
+	_ump_uk_msync_s user_interaction;
+
+	/* Sanity check input parameters */
+	if (NULL == argument || NULL == session_data)
+	{
+		MSG_ERR(("NULL parameter in ump_ioctl_size_get()\n"));
+		return -ENOTTY;
+	}
+
+	if (0 != copy_from_user(&user_interaction, argument, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_from_user() in ump_ioctl_msync()\n"));
+		return -EFAULT;
+	}
+
+	user_interaction.ctx = (void *) session_data;
+
+	_ump_ukk_msync( &user_interaction );
+
+	user_interaction.ctx = NULL;
+
+	if (0 != copy_to_user(argument, &user_interaction, sizeof(user_interaction)))
+	{
+		MSG_ERR(("copy_to_user() failed in ump_ioctl_msync()\n"));
+		return -EFAULT;
+	}
+
+	return 0; /* success */
+}
diff --git a/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.h b/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.h
new file mode 100644
index 0000000..4892c31
--- /dev/null
+++ b/drivers/media/video/samsung/ump/linux/ump_ukk_wrappers.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * 
+ * This program is free software and is provided to you under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
+ * 
+ * A copy of the licence is included with the program, and can also be obtained from Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/**
+ * @file ump_ukk_wrappers.h
+ * Defines the wrapper functions which turn Linux IOCTL calls into _ukk_ calls
+ */
+
+#ifndef __UMP_UKK_WRAPPERS_H__
+#define __UMP_UKK_WRAPPERS_H__
+
+#include <linux/kernel.h>
+#include "ump_kernel_common.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+int ump_get_api_version_wrapper(u32 __user * argument, struct ump_session_data * session_data);
+int ump_release_wrapper(u32 __user * argument, struct ump_session_data  * session_data);
+int ump_size_get_wrapper(u32 __user * argument, struct ump_session_data  * session_data);
+int ump_msync_wrapper(u32 __user * argument, struct ump_session_data  * session_data);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /* __UMP_UKK_WRAPPERS_H__ */
diff --git a/drivers/media/video/sr200pc20-p2.c b/drivers/media/video/sr200pc20-p2.c
new file mode 100644
index 0000000..6941e92
--- /dev/null
+++ b/drivers/media/video/sr200pc20-p2.c
@@ -0,0 +1,1544 @@
+/*
+ * Driver for SR200PC20 from Samsung Electronics
+ *
+ *  2Mp CMOS Image Sensor SoC with an Embedded Image Processor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+#include <media/sr200pc20_platform.h>
+
+#include "sr200pc20-p2.h"
+
+#define DELAY_SEQ               0xFF
+
+#define INIT_NUM_OF_REGS                (sizeof(front_init_50hz_regs) / sizeof(regs_short_t))
+#define INIT_VT_NUM_OF_REGS             (sizeof(front_init_vt_50hz_regs) / sizeof(regs_short_t))
+#define INIT_VT_15_NUM_OF_REGS             (sizeof(front_init_vt_15_50hz_regs) / sizeof(regs_short_t))
+#define PREVIEW_CAMERA_NUM_OF_REGS      (sizeof(front_preview_camera_50hz_regs) / sizeof(regs_short_t))
+
+#define SNAPSHOT_NORMAL_NUM_OF_REGS     (sizeof(front_snapshot_normal_regs) / sizeof(regs_short_t))
+
+#define WB_AUTO_NUM_OF_REGS	            (sizeof(front_wb_auto_regs) / sizeof(regs_short_t))
+#define WB_SUNNY_NUM_OF_REGS	        (sizeof(front_wb_sunny_regs) / sizeof(regs_short_t))
+#define WB_CLOUDY_NUM_OF_REGS	        (sizeof(front_wb_cloudy_regs) / sizeof(regs_short_t))
+#define WB_TUNSTEN_NUM_OF_REGS	        (sizeof(front_wb_tungsten_regs) / sizeof(regs_short_t))
+#define WB_FLUORESCENT_NUM_OF_REGS	    (sizeof(front_wb_fluorescent_regs) / sizeof(regs_short_t))
+
+#define EFFECT_NORMAL_NUM_OF_REGS	    (sizeof(front_effect_normal_regs) / sizeof(regs_short_t))
+#define EFFECT_NEGATIVE_NUM_OF_REGS	    (sizeof(front_effect_negative_regs) / sizeof(regs_short_t))
+#define EFFECT_SEPIA_NUM_OF_REGS	    (sizeof(front_effect_sepia_regs) / sizeof(regs_short_t))
+#define EFFECT_MONO_NUM_OF_REGS         (sizeof(front_effect_mono_regs) / sizeof(regs_short_t))
+
+#define EV_M4_NUM_OF_REGS	            (sizeof(front_ev_minus_4_regs) / sizeof(regs_short_t))
+#define EV_M3_NUM_OF_REGS	            (sizeof(front_ev_minus_3_regs) / sizeof(regs_short_t))
+#define EV_M2_NUM_OF_REGS	            (sizeof(front_ev_minus_2_regs) / sizeof(regs_short_t))
+#define EV_M1_NUM_OF_REGS	            (sizeof(front_ev_minus_1_regs) / sizeof(regs_short_t))
+#define EV_DEFAULT_NUM_OF_REGS	        (sizeof(front_ev_default_regs) / sizeof(regs_short_t))
+#define EV_P1_NUM_OF_REGS	            (sizeof(front_ev_plus_1_regs) / sizeof(regs_short_t))
+#define EV_P2_NUM_OF_REGS	            (sizeof(front_ev_plus_2_regs) / sizeof(regs_short_t))
+#define EV_P3_NUM_OF_REGS	            (sizeof(front_ev_plus_3_regs) / sizeof(regs_short_t))
+#define EV_P4_NUM_OF_REGS	            (sizeof(front_ev_plus_4_regs) / sizeof(regs_short_t))
+
+#define FPS_AUTO_NUM_OF_REGS	        (sizeof(front_fps_auto_regs) / sizeof(regs_short_t))
+#define FPS_7_NUM_OF_REGS	            (sizeof(front_fps_7_50hz_regs) / sizeof(regs_short_t))
+#define FPS_10_NUM_OF_REGS	            (sizeof(front_fps_10_50hz_regs) / sizeof(regs_short_t))
+#define FPS_15_NUM_OF_REGS	            (sizeof(front_fps_15_50hz_regs) / sizeof(regs_short_t))
+
+#define PATTERN_ON_NUM_OF_REGS	        (sizeof(front_pattern_on_regs) / sizeof(regs_short_t))
+#define PATTERN_OFF_NUM_OF_REGS	        (sizeof(front_pattern_off_regs) / sizeof(regs_short_t))
+
+static int sr200pc20_i2c_read_byte(struct i2c_client *client,
+							unsigned short subaddr,
+							unsigned short *data);
+
+static int sr200pc20_i2c_write_byte(struct i2c_client *client,
+							unsigned short subaddr,
+							unsigned short data);
+
+static int sr200pc20_i2c_read_word(struct i2c_client *client,
+							unsigned short subaddr,
+							unsigned short *data);
+
+static int sr200pc20_i2c_write_word(struct i2c_client *client,
+							unsigned short subaddr,
+							unsigned short data);
+
+static int sr200pc20_i2c_set_data_burst(struct i2c_client *client,
+								regs_short_t reg_buffer[],
+								int num_of_regs);
+
+static int sr200pc20_i2c_set_config_register(struct i2c_client *client,
+									regs_short_t reg_buffer[],
+									int num_of_regs,
+									char *name);
+
+#ifdef CONFIG_LOAD_FILE
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+
+#define MAX_REG_TABLE_LEN 3500
+#define MAX_ONE_LINE_LEN 500
+
+typedef struct
+{
+    char name[100];
+    char *location_ptr;
+} reg_hash_t;
+
+static char *front_regs_buf_ptr = NULL;
+static char *front_curr_pos_ptr = NULL;
+static char front_current_line[MAX_ONE_LINE_LEN];
+static regs_short_t front_reg_table[MAX_REG_TABLE_LEN];
+static int front_reg_num_of_element = 0;
+
+static reg_hash_t front_reg_hash_table[] =
+{
+	{"front_init_50hz_regs",                   NULL},
+	{"front_init_vt_50hz_regs",                NULL},
+	{"front_init_vt_15_50hz_regs",             NULL},
+	{"front_preview_camera_50hz_regs",         NULL},
+	{"front_init_60hz_regs",				  NULL},
+	{"front_init_vt_60hz_regs",				  NULL},
+	{"front_init_vt_15_60hz_regs",			  NULL},
+	{"front_preview_camera_60hz_regs",		  NULL},
+	{"front_snapshot_normal_regs",        NULL},
+	{"front_ev_minus_4_regs",             NULL},
+	{"front_ev_minus_3_regs",             NULL},
+	{"front_ev_minus_2_regs",             NULL},
+	{"front_ev_minus_1_regs",             NULL},
+	{"front_ev_default_regs",             NULL},
+	{"front_ev_plus_1_regs",              NULL},
+	{"front_ev_plus_2_regs",              NULL},
+	{"front_ev_plus_3_regs",              NULL},
+	{"front_ev_plus_4_regs",              NULL},
+	{"front_wb_auto_regs",                NULL},
+	{"front_wb_sunny_regs",               NULL},
+	{"front_wb_cloudy_regs",              NULL},
+	{"front_wb_tungsten_regs",            NULL},
+	{"front_wb_fluorescent_regs",         NULL},
+	{"front_effect_normal_regs",          NULL},
+	{"front_effect_negative_regs",        NULL},
+	{"front_effect_sepia_regs",           NULL},
+	{"front_effect_mono_regs",            NULL},
+	{"front_fps_auto_regs",               NULL},
+	{"front_fps_7_50hz_regs",                  NULL},
+	{"front_fps_10_50hz_regs",                 NULL},
+	{"front_fps_15_50hz_regs",                 NULL},
+	{"front_fps_7_60hz_regs",				  NULL},
+	{"front_fps_10_60hz_regs",				  NULL},
+	{"front_fps_15_60hz_regs",				  NULL},
+	{"front_pattern_on_regs",             NULL},
+	{"front_pattern_off_regs",            NULL},
+};
+
+static bool sr200pc20_regs_get_line(char *line_buf)
+{
+	int i;
+	char *r_n_ptr = NULL;
+
+	memset(line_buf, 0, MAX_ONE_LINE_LEN);
+
+	r_n_ptr = strstr(front_curr_pos_ptr, "\n");
+
+	if(r_n_ptr ) {
+		for(i = 0; i < MAX_ONE_LINE_LEN; i++) {
+			if(front_curr_pos_ptr + i == r_n_ptr) {
+				front_curr_pos_ptr = r_n_ptr + 1;
+				break;
+			}
+			line_buf[i] = front_curr_pos_ptr[i];
+		}
+		line_buf[i] = '\0';
+
+		return true;
+	} else {
+		if(strlen(front_curr_pos_ptr) > 0) {
+			strcpy(line_buf, front_curr_pos_ptr);
+			return true;
+		} else {
+			return false;
+		}
+	}
+}
+
+static bool sr200pc20_regs_trim(char *line_buf)
+{
+	int left_index;
+	int buff_len;
+	int i;
+
+	buff_len = strlen(line_buf);
+	left_index  = -1;
+
+	if(buff_len == 0)
+		return false;
+
+	/* Find the first letter that is not a white space from left side */
+	for(i = 0; i < buff_len; i++) {
+		if((line_buf[i] != ' ') && (line_buf[i] != '\t') && (line_buf[i] != '\n') && (line_buf[i] != '\r'))	{
+			left_index = i;
+			break;
+		}
+	}
+
+	if(left_index == -1) {
+		return false;
+	}
+
+	if((line_buf[left_index] == '\0') || ((line_buf[left_index] == '/') && (line_buf[left_index + 1] == '/')))	{
+		return false;
+	}
+
+	if(left_index != 0)	{
+		strcpy(line_buf, line_buf + left_index);
+	}
+
+	return true;
+}
+
+static int sr200pc20_regs_parse_table(void)
+{
+#if 0 /* Parsing a register format : {0x0000, 0x0000}, */
+	char reg_buf[7], data_buf[7];
+	int reg_index = 0;
+
+	reg_buf[6] = '\0';
+	data_buf[6] = '\0';
+
+    while(sr200pc20_regs_get_line(front_current_line))
+    {
+        if(sr200pc20_regs_trim(front_current_line) == false)
+        {
+            continue;
+        }
+
+        /* Check End line of a table.*/
+        if((front_current_line[0] == '}') && (front_current_line[1] == ';'))
+        {
+            break;
+        }
+
+        /* Parsing a register format : {0x0000, 0x0000},*/
+        if((front_current_line[0] == '{') && (front_current_line[1] == '0') && (front_current_line[15] == '}'))
+        {
+            memcpy(reg_buf, (const void *)&front_current_line[1], 6);
+            memcpy(data_buf, (const void *)&front_current_line[9], 6);
+
+            front_reg_table[reg_index].subaddr = (unsigned short)simple_strtoul(reg_buf, NULL, 16);
+            front_reg_table[reg_index].value = (unsigned int)simple_strtoul(data_buf, NULL, 16);
+
+            reg_index++;
+        }
+    }
+
+#else /* Parsing a register format : {0x00, 0x00}, */
+
+	char reg_buf[5], data_buf[5];
+	int reg_index = 0;
+
+	reg_buf[4] = '\0';
+	data_buf[4] = '\0';
+
+	while(sr200pc20_regs_get_line(front_current_line)) {
+		if(sr200pc20_regs_trim(front_current_line) == false)
+			continue;
+
+	/* Check End line of a table.*/
+	if((front_current_line[0] == '}') && (front_current_line[1] == ';'))
+		break;
+
+	/* Parsing a register format : {0x00, 0x00},*/
+	if((front_current_line[0] == '{') && (front_current_line[1] == '0') && (front_current_line[11] == '}'))	{
+		memcpy(reg_buf, (const void *)&front_current_line[1], 4);
+		memcpy(data_buf, (const void *)&front_current_line[7], 4);
+
+		front_reg_table[reg_index].subaddr = (unsigned short)simple_strtoul(reg_buf, NULL, 16);
+		front_reg_table[reg_index].value = (unsigned int)simple_strtoul(data_buf, NULL, 16);
+
+	reg_index++;
+	}
+	}
+#endif
+
+    return reg_index;
+}
+
+static int sr200pc20_regs_table_write(struct i2c_client *client, char *name)
+{
+	bool bFound_table = false;
+	int i, err = 0;
+
+	front_reg_num_of_element = 0;
+
+	for(i = 0; i < sizeof(front_reg_hash_table)/sizeof(reg_hash_t); i++) {
+		if(strcmp(name, front_reg_hash_table[i].name) == 0) {
+			bFound_table = true;
+
+			front_curr_pos_ptr = front_reg_hash_table[i].location_ptr;
+			break;
+		}
+	}
+
+	if(bFound_table) {
+		front_reg_num_of_element = sr200pc20_regs_parse_table();
+	} else {
+		cam_err("%s doesn't exist\n", name);
+		return -EIO;
+	}
+
+	err = sr200pc20_i2c_set_data_burst(client, front_reg_table, front_reg_num_of_element);
+	if(err < 0) {
+		cam_err(" ERROR! sr200pc20_i2c_set_data_burst failed\n");
+		return -EIO;
+	}
+
+	return err;
+}
+
+int sr200pc20_regs_table_init(void)
+{
+	struct file *filp;
+	char *dp;
+	long l;
+	loff_t pos;
+	int ret, i, retry_cnt;
+	mm_segment_t fs = get_fs();
+	char *location_ptr = NULL;
+	bool bFound_name;
+
+	cam_dbg("E\n");
+
+	set_fs(get_ds());
+#if defined (CONFIG_MACH_P2_REV02)
+	filp = filp_open("/mnt/sdcard/sr200pc20_regs-p2.h", O_RDONLY, 0);
+#else
+	filp = filp_open("/mnt/sdcard/sr200pc20_regs.h", O_RDONLY, 0);
+#endif
+	if(IS_ERR(filp)) {
+		cam_err("file open error\n");
+		return -EIO;
+	}
+	l = filp->f_path.dentry->d_inode->i_size;
+	cam_info("file size = %ld\n",l);
+
+	//msleep(50);
+	cam_dbg("Start vmalloc\n");
+	for(retry_cnt = 5; retry_cnt > 0; retry_cnt--) {
+		dp = kmalloc(l, GFP_KERNEL);
+		if(dp != NULL)
+			break;
+
+		msleep(50);
+	}
+	if(dp == NULL) {
+		cam_err("Out of Memory\n");
+		filp_close(filp, current->files);
+		return -ENOMEM;
+	}
+	cam_dbg("End vmalloc\n");
+
+	pos = 0;
+	memset(dp, 0, l);
+	cam_dbg("Start vfs_read\n");
+	ret = vfs_read(filp, (char __user *)dp, l, &pos);
+	if(ret != l) {
+		cam_err("Failed to read file\n");
+		vfree(dp);
+		filp_close(filp, current->files);
+		return -EINVAL;
+	}
+	cam_dbg("End vfs_read\n");
+
+	filp_close(filp, current->files);
+
+	set_fs(fs);
+
+	front_regs_buf_ptr = dp;
+
+	*((front_regs_buf_ptr + l) - 1) = '\0';
+
+	/* Make hash table to enhance speed.*/
+	front_curr_pos_ptr = front_regs_buf_ptr;
+	location_ptr = front_curr_pos_ptr;
+
+	for(i = 0; i < sizeof(front_reg_hash_table)/sizeof(reg_hash_t); i++) {
+		front_reg_hash_table[i].location_ptr = NULL;
+		bFound_name = false;
+
+		while(sr200pc20_regs_get_line(front_current_line)) {
+			if(strstr(front_current_line, front_reg_hash_table[i].name) != NULL) {
+				bFound_name = true;
+				front_reg_hash_table[i].location_ptr = location_ptr;
+				break;
+			}
+			location_ptr = front_curr_pos_ptr;
+		}
+
+		if(bFound_name == false) {
+			if(i == 0)	{
+				cam_err(" ERROR! Couldn't find the reg name in hash table\n");
+				return -EIO;
+			} else {
+				front_curr_pos_ptr = front_reg_hash_table[i-1].location_ptr;
+			}
+			location_ptr = front_curr_pos_ptr;
+
+			cam_err(" ERROR! Couldn't find the reg name in hash table\n");
+		}
+	}
+
+	cam_dbg("X\n");
+
+	return 0;
+}
+
+void sr200pc20_regs_table_exit(void)
+{
+	cam_dbg(" start\n");
+
+	if(front_regs_buf_ptr) {
+		vfree(front_regs_buf_ptr);
+		front_regs_buf_ptr = NULL;
+	}
+
+	cam_dbg(" done\n");
+}
+#endif
+
+static int sr200pc20_i2c_read_byte(struct i2c_client *client,
+                                     unsigned short subaddr,
+                                     unsigned short *data)
+{
+	unsigned char buf[2] = {0,};
+	struct i2c_msg msg = {client->addr, 0, 1, buf};
+	int err = 0;
+
+	if(!client->adapter) {
+		cam_err("ERROR! can't search i2c client adapter\n");
+		return -EIO;
+	}
+
+	buf[0] = (unsigned char)subaddr;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if(err < 0) {
+		cam_err(" ERROR! %d register read failed\n",subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 1;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if(err < 0) {
+		cam_err(" ERROR! %d register read failed\n",subaddr);
+		return -EIO;
+	}
+
+	*data = (unsigned short)buf[0];
+
+	return 0;
+}
+
+static int sr200pc20_i2c_write_byte(struct i2c_client *client,
+                                     unsigned short subaddr,
+                                     unsigned short data)
+{
+	unsigned char buf[2] = {0,};
+	struct i2c_msg msg = {client->addr, 0, 2, buf};
+	int err = 0;
+
+	if(!client->adapter) {
+		cam_err(" ERROR! can't search i2c client adapter\n");
+		return -EIO;
+	}
+
+	buf[0] = subaddr & 0xFF;
+	buf[1] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1)? 0 : -EIO;
+}
+
+static int sr200pc20_i2c_read_word(struct i2c_client *client,
+                                     unsigned short subaddr,
+                                     unsigned short *data)
+{
+	unsigned char buf[4];
+	struct i2c_msg msg = {client->addr, 0, 2, buf};
+	int err = 0;
+
+	if(!client->adapter) {
+		cam_err(" ERROR! can't search i2c client adapter\n");
+		return -EIO;
+	}
+
+	buf[0] = subaddr>> 8;
+	buf[1] = subaddr & 0xff;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if(err < 0) {
+		cam_err(" ERROR! %d register read failed\n", subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 2;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if(err < 0) {
+		cam_err(" ERROR! %d register read failed\n", subaddr);
+		return -EIO;
+	}
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return 0;
+}
+
+static int sr200pc20_i2c_write_word(struct i2c_client *client,
+                                     unsigned short subaddr,
+                                     unsigned short data)
+{
+	unsigned char buf[4];
+	struct i2c_msg msg = {client->addr, 0, 4, buf};
+	int err = 0;
+
+	if(!client->adapter) {
+		cam_err(" ERROR! can't search i2c client adapter\n");
+		return -EIO;
+	}
+
+	buf[0] = subaddr >> 8;
+	buf[1] = subaddr & 0xFF;
+	buf[2] = data >> 8;
+	buf[3] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1)? 0 : -EIO;
+}
+
+static int sr200pc20_i2c_set_data_burst(struct i2c_client *client,
+                                         regs_short_t reg_buffer[],
+					                 int num_of_regs)
+{
+	unsigned short subaddr, data_value;
+	int i, err = 0;
+
+	for(i = 0; i < num_of_regs; i++) {
+		subaddr = reg_buffer[i].subaddr;
+		data_value = reg_buffer[i].value;
+
+		switch(subaddr) {
+		case DELAY_SEQ:
+			cam_err("delay = %d\n",data_value*10);
+			msleep(data_value * 10);
+			break;
+		default:
+			err = sr200pc20_i2c_write_byte(client, subaddr, data_value);
+			if(err < 0) {
+				cam_err("i2c write fail\n");
+				return -EIO;
+			}
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int sr200pc20_i2c_set_config_register(struct i2c_client *client,
+                                         regs_short_t reg_buffer[],
+					                 int num_of_regs,
+					                 char *name)
+{
+	int err = 0;
+
+	cam_err("sr200pc20_i2c_set_config_register E: %s, %d\n",  name, err);
+
+#ifdef CONFIG_LOAD_FILE
+	err = sr200pc20_regs_table_write(client, name);
+#else
+	err = sr200pc20_i2c_set_data_burst(client, reg_buffer, num_of_regs);
+#endif
+
+	cam_err("sr200pc20_i2c_set_config_register X: %s, %d\n",  name, err);
+
+	return err;
+}
+
+static int sr200pc20_get_iso_speed_rate(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned short read_value;
+	int gain;
+	int isospeedrating = 0;
+
+	sr200pc20_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20_i2c_read_byte(client, 0xb0, &read_value);
+	gain = ((int)read_value * 100  / 32) + 50;
+
+	if (read_value < 125)
+		isospeedrating = 50;
+	else if (read_value < 175)
+		isospeedrating = 100;
+	else if (read_value < 250)
+		isospeedrating = 200;
+	else if (read_value < 375)
+		isospeedrating = 400;
+	else if (read_value < 550)
+		isospeedrating = 800;
+	else
+		isospeedrating = 1600;
+
+	cam_dbg("get iso = %d\n", isospeedrating);
+	return isospeedrating;
+}
+
+static int sr200pc20_get_shutterspeed(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	unsigned short read_value;
+	int cintr;
+	int ShutterSpeed = 0;
+
+	sr200pc20_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20_i2c_read_byte(client, 0x80, &read_value);
+	cintr = (int)read_value << 19;
+	sr200pc20_i2c_read_byte(client, 0x81, &read_value);
+	cintr += (int)read_value << 11;
+	sr200pc20_i2c_read_byte(client, 0x82, &read_value);
+	cintr += (int)read_value << 3;
+
+	cintr = cintr/24;
+	ShutterSpeed =  1000000/cintr;
+
+	cam_dbg("get shutterspeed = %d\n", ShutterSpeed);
+	return ShutterSpeed;
+}
+
+static int sr200pc20_get_exif(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+
+	state->exif.shutter_speed = 100;
+	state->exif.iso = 0;
+
+	/* Get shutter speed */
+	state->exif.shutter_speed = sr200pc20_get_shutterspeed(sd);
+
+	/* Get ISO */
+	state->exif.iso = sr200pc20_get_iso_speed_rate(sd);
+
+	cam_dbg("Shutter speed=%d, ISO=%d\n",state->exif.shutter_speed, state->exif.iso);
+	return 0;
+}
+
+static int sr200pc20_check_dataline(struct v4l2_subdev *sd, s32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+	int err = 0;
+
+	cam_info("DTP %s\n", val ? "ON" : "OFF");
+
+	if (val) {
+		cam_dbg("load sr200pc20_pattern_on\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_pattern_on_regs,
+										  PATTERN_ON_NUM_OF_REGS,
+										  "front_pattern_on_regs");
+	} else {
+		cam_dbg("load sr200pc20_pattern_off\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_pattern_off_regs,
+										  PATTERN_OFF_NUM_OF_REGS,
+										  "front_pattern_off_regs");
+	}
+	if (unlikely(err)) {
+		cam_err("fail to DTP setting\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int sr200pc20_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("reset preview\n");
+
+	cam_dbg("load sr200pc20_preview\n");
+	if(state->anti_banding == ANTI_BANDING_50HZ) {
+	err = sr200pc20_i2c_set_config_register(client,
+									front_preview_camera_50hz_regs,
+									PREVIEW_CAMERA_NUM_OF_REGS,
+									"front_preview_camera_50hz_regs");
+	} else {
+	err = sr200pc20_i2c_set_config_register(client,
+									front_preview_camera_60hz_regs,
+									PREVIEW_CAMERA_NUM_OF_REGS,
+									"front_preview_camera_60hz_regs");
+	}
+
+	if (state->check_dataline)
+		err = sr200pc20_check_dataline(sd, 1);
+	if (unlikely(err)) {
+		cam_err("fail to make preview\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int sr200pc20_set_preview_stop(struct v4l2_subdev *sd)
+{
+	int err = 0;
+	cam_info("do nothing.\n");
+
+	return err;
+}
+
+static int sr200pc20_set_capture_start(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = -EINVAL;
+
+	/* set initial regster value */
+	cam_dbg("load sr200pc20_capture\n");
+	err = sr200pc20_i2c_set_config_register(client,
+									front_snapshot_normal_regs,
+									SNAPSHOT_NORMAL_NUM_OF_REGS,
+									"front_snapshot_normal_regs");
+	if (unlikely(err)) {
+		cam_err("failed to make capture\n");
+		return err;
+	}
+	sr200pc20_get_exif(sd);
+	cam_info("Capture ConfigSync\n");
+	return err;
+}
+
+static int sr200pc20_set_sensor_mode(struct v4l2_subdev *sd,
+					struct v4l2_control *ctrl)
+{
+	struct sr200pc20_state *state = to_state(sd);
+
+	if ((ctrl->value != SENSOR_CAMERA) &&
+	(ctrl->value != SENSOR_MOVIE)) {
+		cam_err("ERR: Not support.(%d)\n", ctrl->value);
+		return -EINVAL;
+	}
+
+	/* We does not support movie mode when in VT. */
+	if ((ctrl->value == SENSOR_MOVIE) && state->vt_mode) {
+		state->sensor_mode = SENSOR_CAMERA;
+		cam_warn("ERR: Not support movie\n");
+	} else
+		state->sensor_mode = ctrl->value;
+
+	return 0;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_g_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	cam_dbg("E\n");
+	return 0;
+}
+
+static int sr200pc20_enum_framesizes(struct v4l2_subdev *sd, \
+					struct v4l2_frmsizeenum *fsize)
+{
+	struct sr200pc20_state *state = to_state(sd);
+
+	cam_dbg("E\n");
+
+	/*
+	 * Return the actual output settings programmed to the camera
+	 */
+	if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		fsize->discrete.width = state->capture_frmsizes.width;
+		fsize->discrete.height = state->capture_frmsizes.height;
+	} else {
+		fsize->discrete.width = state->preview_frmsizes.width;
+		fsize->discrete.height = state->preview_frmsizes.height;
+	}
+
+	cam_info("enum_framesizes: width - %d , height - %d\n",
+		fsize->discrete.width, fsize->discrete.height);
+
+	return 0;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_try_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	int err = 0;
+
+	cam_dbg("E\n");
+
+	return err;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_s_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	struct sr200pc20_state *state = to_state(sd);
+	u32 *width = NULL, *height = NULL;
+
+	cam_dbg("E\n");
+	/*
+	 * Just copying the requested format as of now.
+	 * We need to check here what are the formats the camera support, and
+	 * set the most appropriate one according to the request from FIMC
+	 */
+#ifdef NEW_CAM_DRV
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	state->req_fmt.priv = fmt->field;
+#else
+	memcpy(&state->req_fmt, &fmt->fmt.pix, sizeof(fmt->fmt.pix));
+#endif
+
+	switch (state->req_fmt.priv) {
+	case V4L2_PIX_FMT_MODE_PREVIEW:
+		width = &state->preview_frmsizes.width;
+		height = &state->preview_frmsizes.height;
+		break;
+
+	case V4L2_PIX_FMT_MODE_CAPTURE:
+		width = &state->capture_frmsizes.width;
+		height = &state->capture_frmsizes.height;
+		break;
+
+	default:
+		cam_err("ERR(EINVAL)\n");
+		return -EINVAL;
+	}
+
+	if ((*width != state->req_fmt.width) ||
+		(*height != state->req_fmt.height)) {
+		cam_err("ERR: Invalid size. width= %d, height= %d\n",
+			state->req_fmt.width, state->req_fmt.height);
+	}
+
+	return 0;
+}
+
+static int sr200pc20_set_frame_rate(struct v4l2_subdev *sd, u32 fps)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int err = 0;
+
+	cam_info("frame rate %d\n\n", fps);
+
+	switch (fps) {
+	case 7:
+		if(state->anti_banding == ANTI_BANDING_50HZ) {
+		cam_dbg("load front_fps_7_50hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_7_50hz_regs,
+										  FPS_7_NUM_OF_REGS,
+										  "front_fps_7_50hz_regs");
+		} else {
+		cam_dbg("load front_fps_7_60hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_7_60hz_regs,
+										  FPS_7_NUM_OF_REGS,
+										  "front_fps_7_60hz_regs");
+		}
+		break;
+	case 10:
+		if(state->anti_banding == ANTI_BANDING_50HZ) {
+		cam_dbg("load front_fps_10_50hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_10_50hz_regs,
+										  FPS_10_NUM_OF_REGS,
+										  "front_fps_10_50hz_regs");
+		} else {
+		cam_dbg("load front_fps_10_60hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_10_60hz_regs,
+										  FPS_10_NUM_OF_REGS,
+										  "front_fps_10_60hz_regs");
+		}
+		break;
+	case 15:
+		if(state->anti_banding == ANTI_BANDING_50HZ) {
+		cam_dbg("load front_fps_15_50hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_15_50hz_regs,
+										  FPS_15_NUM_OF_REGS,
+										  "front_fps_15_50hz_regs");
+		} else {
+		cam_dbg("load front_fps_15_60hz_regs\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_15_60hz_regs,
+										  FPS_15_NUM_OF_REGS,
+										  "front_fps_15_60hz_regs");
+		}
+		break;
+	default:
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_fps_auto_regs,
+										  FPS_AUTO_NUM_OF_REGS,
+										  "front_fps_auto_regs");
+		break;
+	}
+	if (unlikely(err < 0)) {
+		cam_err("i2c_write for set framerate\n");
+		return -EIO;
+	}
+
+	return err;
+}
+
+static int sr200pc20_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+
+	cam_dbg("E\n");
+
+	return err;
+}
+
+static int sr200pc20_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+	u32 fps = 0;
+	struct sr200pc20_state *state = to_state(sd);
+
+	if (!state->vt_mode)
+		return 0;
+
+	cam_dbg("E\n");
+
+	fps = parms->parm.capture.timeperframe.denominator /
+			parms->parm.capture.timeperframe.numerator;
+
+	if (fps != state->set_fps) {
+		if (fps < 0 && fps > 15) {
+			cam_err("invalid frame rate %d\n", fps);
+			fps = 15;
+		}
+		state->req_fps = fps;
+
+		if (state->initialized) {
+			err = sr200pc20_set_frame_rate(sd, state->req_fps);
+			if (err >= 0)
+				state->set_fps = state->req_fps;
+		}
+
+	}
+
+	return err;
+}
+
+static int sr200pc20_control_stream(struct v4l2_subdev *sd, stream_cmd_t cmd)
+{
+	int err = 0;
+
+	switch (cmd) {
+	case STREAM_START:
+		cam_warn("WARN: do nothing\n");
+		break;
+
+	case STREAM_STOP:
+		cam_dbg("stream stop!!!\n");
+		break;
+	default:
+		cam_err("ERR: Invalid cmd\n");
+		break;
+	}
+
+	if (unlikely(err))
+		cam_err("failed to stream start(stop)\n");
+
+	return err;
+}
+
+static int sr200pc20_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("E\n");
+
+	/* set initial regster value */
+#ifdef CONFIG_LOAD_FILE
+	err = sr200pc20_regs_table_init();
+	if(err < 0)
+	{
+		cam_err("sr200pc20_regs_table_init failed\n");
+		return -ENOIOCTLCMD;
+	}
+#endif
+
+	cam_dbg("sr200pc20_init: anti_banding = %d\n", state->anti_banding);
+
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			if(state->anti_banding == ANTI_BANDING_50HZ) {
+			cam_info("load camera common 50hz setting\n");
+			err = sr200pc20_i2c_set_config_register(client,
+											  front_init_50hz_regs,
+											  INIT_NUM_OF_REGS,
+											  "front_init_50hz_regs");
+			} else {
+			cam_info("load camera common 60hz setting\n");
+			err = sr200pc20_i2c_set_config_register(client,
+											  front_init_60hz_regs,
+											  INIT_NUM_OF_REGS,
+											  "front_init_60hz_regs");
+			}
+		} else {
+			if(state->anti_banding == ANTI_BANDING_50HZ) {
+			cam_info("load camera WIFI VT call 50hz setting\n");
+			err = sr200pc20_i2c_set_config_register(client,
+											  front_init_vt_15_50hz_regs,
+											  INIT_VT_15_NUM_OF_REGS,
+											  "front_init_vt_15_50hz_regs");
+			} else {
+			cam_info("load camera WIFI VT call 60hz setting\n");
+			err = sr200pc20_i2c_set_config_register(client,
+											  front_init_vt_15_60hz_regs,
+											  INIT_VT_15_NUM_OF_REGS,
+											  "front_init_vt_15_60hz_regs");
+			}
+		}
+	} else {
+		if(state->anti_banding == ANTI_BANDING_50HZ) {
+		cam_info("load recording 50hz setting\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_init_vt_50hz_regs,
+										  INIT_VT_NUM_OF_REGS,
+										  "front_init_vt_50hz_regs");
+		} else {
+		cam_info("load recording 60hz setting\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										  front_init_vt_60hz_regs,
+										  INIT_VT_NUM_OF_REGS,
+										  "front_init_vt_60hz_regs");
+		}
+	}
+	if (unlikely(err)) {
+		cam_err("failed to init\n");
+		return err;
+	}
+
+	/* We stop stream-output from sensor when starting camera. */
+	err = sr200pc20_control_stream(sd, STREAM_STOP);
+	if (unlikely(err < 0))
+		return err;
+	msleep(150);
+
+	if (state->vt_mode && (state->req_fps != state->set_fps)) {
+		err = sr200pc20_set_frame_rate(sd, state->req_fps);
+		if (unlikely(err < 0))
+			return err;
+		else
+			state->set_fps = state->req_fps;
+	}
+
+	state->initialized = 1;
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int sr200pc20_s_config(struct v4l2_subdev *sd,
+		int irq, void *platform_data)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct sr200pc20_state *state = to_state(sd);
+	struct sr200pc20_platform_data *pdata;
+
+	cam_dbg("E\n");
+
+	state->initialized = 0;
+	state->req_fps = state->set_fps = 8;
+	state->sensor_mode = SENSOR_CAMERA;
+
+	pdata = client->dev.platform_data;
+
+	if (!pdata) {
+		cam_err("no platform data\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	if (!(pdata->default_width && pdata->default_height)) {
+		state->preview_frmsizes.width = DEFAULT_PREVIEW_WIDTH;
+		state->preview_frmsizes.height = DEFAULT_PREVIEW_HEIGHT;
+
+	} else {
+		state->preview_frmsizes.width = pdata->default_width;
+		state->preview_frmsizes.height = pdata->default_height;
+	}
+	state->capture_frmsizes.width = DEFAULT_CAPTURE_WIDTH;
+	state->capture_frmsizes.height = DEFAULT_CAPTURE_HEIGHT;
+
+	cam_dbg("preview_width: %d , preview_height: %d, "
+		"capture_width: %d, capture_height: %d",
+		state->preview_frmsizes.width, state->preview_frmsizes.height,
+		state->capture_frmsizes.width, state->capture_frmsizes.height);
+
+	state->req_fmt.width = state->preview_frmsizes.width;
+	state->req_fmt.height = state->preview_frmsizes.height;
+	if (!pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_FMT;
+	else
+		state->req_fmt.pixelformat = pdata->pixelformat;
+
+	return 0;
+}
+
+static int sr200pc20_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	int err = 0;
+
+	cam_info("stream mode = %d\n", enable);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->sensor_mode == SENSOR_CAMERA) {
+			if (state->check_dataline)
+				err = sr200pc20_check_dataline(sd, 0);
+			else
+				err = sr200pc20_control_stream(sd, STREAM_STOP);
+		}
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		/* The position of this code need to be adjusted later */
+		if (state->sensor_mode == SENSOR_CAMERA) {
+			if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE)
+				err = sr200pc20_set_capture_start(sd);
+			else
+				err = sr200pc20_set_preview_start(sd);
+		}
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_dbg("do nothing(movie on)!!\n");
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_dbg("do nothing(movie off)!!\n");
+		break;
+
+	default:
+		cam_err("ERR: Invalid stream mode\n");
+		break;
+	}
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR: faild\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int sr200pc20_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("ctrl->id : %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		ctrl->value = state->exif.shutter_speed;
+		break;
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+	default:
+		cam_err("no such control id %d\n",
+				ctrl->id - V4L2_CID_PRIVATE_BASE);
+		break;
+	}
+
+	return err;
+}
+
+static int sr200pc20_set_brightness(struct v4l2_subdev *sd, struct v4l2_control *ctrl) {
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_dbg("E\n");
+
+	if (state->check_dataline)
+		return 0;
+
+	switch (ctrl->value) {
+	case EV_MINUS_4:
+		cam_dbg("load sr200pc20_bright_m4\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_minus_4_regs,
+										EV_M4_NUM_OF_REGS,
+										"front_ev_minus_4_regs");
+		break;
+	case EV_MINUS_3:
+		cam_dbg("load sr200pc20_bright_m3\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_minus_3_regs,
+										EV_M3_NUM_OF_REGS,
+										"front_ev_minus_3_regs");
+		break;
+	case EV_MINUS_2:
+		cam_dbg("load sr200pc20_bright_m2\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_minus_2_regs,
+										EV_M2_NUM_OF_REGS,
+										"front_ev_minus_2_regs");
+		break;
+	case EV_MINUS_1:
+		cam_dbg("load sr200pc20_bright_m1\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_minus_1_regs,
+										EV_M1_NUM_OF_REGS,
+										"front_ev_minus_1_regs");
+		break;
+	case EV_DEFAULT:
+		cam_dbg("load sr200pc20_bright_default\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_default_regs,
+										EV_DEFAULT_NUM_OF_REGS,
+										"front_ev_default_regs");
+		break;
+	case EV_PLUS_1:
+		cam_dbg("load sr200pc20_bright_p1\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_plus_1_regs,
+										EV_P1_NUM_OF_REGS,
+										"front_ev_plus_1_regs");
+		break;
+	case EV_PLUS_2:
+		cam_dbg("load sr200pc20_bright_p2\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_plus_2_regs,
+										EV_P2_NUM_OF_REGS,
+										"front_ev_plus_2_regs");
+		break;
+	case EV_PLUS_3:
+		cam_dbg("load sr200pc20_bright_p3\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_plus_3_regs,
+										EV_P3_NUM_OF_REGS,
+										"front_ev_plus_3_regs");
+		break;
+	case EV_PLUS_4:
+		cam_dbg("load sr200pc20_bright_p4\n");
+		err = sr200pc20_i2c_set_config_register(client,
+										front_ev_plus_4_regs,
+										EV_P4_NUM_OF_REGS,
+										"front_ev_plus_4_regs");
+		break;
+	default:
+		cam_err("ERR: invalid brightness(%d)\n", ctrl->value);
+		return err;
+		break;
+	}
+
+	if (unlikely(err < 0)) {
+		cam_err("ERR: i2c_write for set brightness\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int sr200pc20_check_dataline_stop(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	extern int sr200pc20_power_reset(void);
+
+	cam_warn("Warning: do nothing!!\n");
+	return err;
+
+	//sr200pc20_write(client, 0xFCFCD000);
+	//sr200pc20_write(client, 0x0028D000);
+	//sr200pc20_write(client, 0x002A3100);
+	//sr200pc20_write(client, 0x0F120000);
+
+	//	err =  sr200pc20_write_regs(sd, sr200pc20_pattern_off,	sizeof(sr200pc20_pattern_off) / sizeof(sr200pc20_pattern_off[0]));
+	cam_dbg("sensor reset\n");
+#if defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_TARGET_LOCALE_EUR) || defined(CONFIG_TARGET_LOCALE_HKTW) || defined(CONFIG_TARGET_LOCALE_HKTW_FET) || defined(CONFIG_TARGET_LOCALE_USAGSM)
+        // dont't know where this code came from - comment out for compile error
+        // sr200pc20_power_reset();
+ #endif
+ if(state->anti_banding == ANTI_BANDING_50HZ) {
+ cam_info("load camera common 50hz setting\n");
+ err = sr200pc20_i2c_set_config_register(client,
+								   front_init_50hz_regs,
+								   INIT_NUM_OF_REGS,
+								   "front_init_50hz_regs");
+ } else {
+ cam_info("load camera common 60hz setting\n");
+ err = sr200pc20_i2c_set_config_register(client,
+								   front_init_60hz_regs,
+								   INIT_NUM_OF_REGS,
+								   "front_init_60hz_regs");
+ }
+
+	state->check_dataline = 0;
+	/* mdelay(100); */
+	return err;
+}
+
+static int sr200pc20_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	/* struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	struct sr200pc20_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("ctrl->id : %d, value=%d\n", ctrl->id - V4L2_CID_PRIVATE_BASE,
+	ctrl->value);
+
+	if ((ctrl->id != V4L2_CID_CAMERA_CHECK_DATALINE)
+	&& (ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE)
+	&& (ctrl->id != V4L2_CID_CAMERA_VT_MODE)
+	&& (ctrl->id != V4L2_CID_CAMERA_ANTI_BANDING)
+	&& (!state->initialized)) {
+		cam_warn("camera isn't initialized\n");
+		return 0;
+	}
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAM_PREVIEW_ONOFF:
+		if (ctrl->value)
+			err = sr200pc20_set_preview_start(sd);
+		else
+			err = sr200pc20_set_preview_stop(sd);
+		cam_dbg("V4L2_CID_CAM_PREVIEW_ONOFF [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAM_CAPTURE:
+		err = sr200pc20_set_capture_start(sd);
+		cam_dbg("V4L2_CID_CAM_CAPTURE\n");
+		break;
+
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = sr200pc20_set_brightness(sd, ctrl);
+		cam_dbg("V4L2_CID_CAMERA_BRIGHTNESS [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		cam_dbg("check_dataline = %d\n", state->check_dataline);
+		err = 0;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = sr200pc20_set_sensor_mode(sd, ctrl);
+		cam_dbg("sensor_mode = %d\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_DATALINE_STOP:
+		err = sr200pc20_check_dataline_stop(sd);
+		break;
+
+	case V4L2_CID_CAMERA_FRAME_RATE:
+		cam_dbg("do nothing\n");
+		break;
+
+	case V4L2_CID_CAMERA_ANTI_BANDING:
+		state->anti_banding = ctrl->value;
+		cam_dbg("anti_banding = %d\n", state->anti_banding);
+		err = 0;
+		break;
+
+	default:
+		cam_err("ERR(ENOIOCTLCMD)\n");
+		/* no errors return.*/
+		err = 0;
+	}
+
+	cam_dbg("X\n");
+	return err;
+}
+
+static const struct v4l2_subdev_core_ops sr200pc20_core_ops = {
+	.init = sr200pc20_init,		/* initializing API */
+	.g_ctrl = sr200pc20_g_ctrl,
+	.s_ctrl = sr200pc20_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops sr200pc20_video_ops = {
+	/*.s_crystal_freq = sr200pc20_s_crystal_freq,*/
+#ifdef NEW_CAM_DRV
+	.g_mbus_fmt = sr200pc20_g_mbus_fmt,
+	.s_mbus_fmt = sr200pc20_s_mbus_fmt,
+#else
+	.g_fmt	= sr200pc20_g_fmt,
+	.s_fmt	= sr200pc20_s_fmt,
+#endif
+	.s_stream = sr200pc20_s_stream,
+	.enum_framesizes = sr200pc20_enum_framesizes,
+	/*.enum_frameintervals = sr200pc20_enum_frameintervals,*/
+#ifdef NEW_CAM_DRV
+	/* .enum_mbus_fmt = sr200pc20_enum_mbus_fmt, */
+	.try_mbus_fmt = sr200pc20_try_mbus_fmt,
+#else
+	/*.enum_fmt = sr200pc20_enum_fmt,*/
+	.try_fmt = sr200pc20_try_fmt,
+#endif
+	.g_parm	= sr200pc20_g_parm,
+	.s_parm	= sr200pc20_s_parm,
+};
+
+static const struct v4l2_subdev_ops sr200pc20_ops = {
+	.core = &sr200pc20_core_ops,
+	.video = &sr200pc20_video_ops,
+};
+
+ssize_t sr200pc20_camera_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	char *cam_type = "SILICONFILE_SR200PC20";
+	cam_info("%s\n", __func__);
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static DEVICE_ATTR(camera_type, S_IRUGO, sr200pc20_camera_type_show, NULL);
+
+/*
+ * sr200pc20_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int sr200pc20_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	struct sr200pc20_state *state = NULL;
+	struct v4l2_subdev *sd = NULL;
+	int err = 0;
+
+	cam_dbg("E\n");
+
+	state = kzalloc(sizeof(struct sr200pc20_state), GFP_KERNEL);
+	if (state == NULL)
+		return -ENOMEM;
+
+	sd = &state->sd;
+	strcpy(sd->name, SR200PC20_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &sr200pc20_ops);
+
+	err = sr200pc20_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+	if (device_create_file(&client->dev, &dev_attr_camera_type) < 0) {
+		cam_warn("failed to create device file, %s\n",
+				dev_attr_camera_type.attr.name);
+	}
+	cam_dbg("probed!!\n");
+
+	return 0;
+}
+
+static int sr200pc20_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct sr200pc20_state *state = to_state(sd);
+
+	cam_dbg("E\n");
+
+	state->initialized = 0;
+
+	device_remove_file(&client->dev, &dev_attr_camera_type);
+	v4l2_device_unregister_subdev(sd);
+	kfree(to_state(sd));
+	return 0;
+}
+
+static const struct i2c_device_id sr200pc20_id[] = {
+	{ SR200PC20_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, sr200pc20_id);
+
+static struct i2c_driver v4l2_i2c_driver = {
+	.driver.name	= SR200PC20_DRIVER_NAME,
+	.probe		= sr200pc20_probe,
+	.remove		= sr200pc20_remove,
+	.id_table	= sr200pc20_id,
+};
+
+static int __init v4l2_i2c_drv_init(void)
+{
+	pr_info("%s: %s called\n", __func__, SR200PC20_DRIVER_NAME); /* dslim*/
+	return i2c_add_driver(&v4l2_i2c_driver);
+}
+
+static void __exit v4l2_i2c_drv_cleanup(void)
+{
+	pr_info("%s: %s called\n", __func__, SR200PC20_DRIVER_NAME); /* dslim*/
+	i2c_del_driver(&v4l2_i2c_driver);
+}
+
+module_init(v4l2_i2c_drv_init);
+module_exit(v4l2_i2c_drv_cleanup);
+
+MODULE_DESCRIPTION("SR200PC20 ISP driver");
+MODULE_AUTHOR("DongSeong Lim<dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/sr200pc20-p2.h b/drivers/media/video/sr200pc20-p2.h
new file mode 100644
index 0000000..529558f
--- /dev/null
+++ b/drivers/media/video/sr200pc20-p2.h
@@ -0,0 +1,119 @@
+/*
+ * Driver for SR200PC20 2M ISP from Samsung
+ *
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __SR200PC20_H
+#define __SR200PC20_H
+
+#include <linux/types.h>
+
+#define SR200PC20_DRIVER_NAME	"SR200PC20"
+
+#define NEW_CAM_DRV
+
+typedef enum {
+	STREAM_STOP,
+	STREAM_START,
+} stream_cmd_t;
+
+struct sr200pc20_framesize {
+	u32 width;
+	u32 height;
+};
+
+struct sr200pc20_exif {
+	u32 shutter_speed;
+	u16 iso;
+};
+
+
+/*
+ * Driver information
+ */
+struct sr200pc20_state {
+	struct v4l2_subdev sd;
+	/*
+	 * req_fmt is the requested format from the application.
+	 * set_fmt is the output format of the camera. Finally FIMC
+	 * converts the camera output(set_fmt) to the requested format
+	 * with hardware scaler.
+	 */
+	struct v4l2_pix_format req_fmt;
+	struct sr200pc20_framesize preview_frmsizes;
+	struct sr200pc20_framesize capture_frmsizes;
+	struct sr200pc20_exif exif;
+
+	enum v4l2_sensor_mode sensor_mode;
+	s32 vt_mode;
+	s32 check_dataline;
+	u32 req_fps;
+	u32 set_fps;
+	u32 initialized;
+	u32 anti_banding;
+};
+
+static inline struct sr200pc20_state *to_state(struct v4l2_subdev *sd) {
+	return container_of(sd, struct sr200pc20_state, sd);
+}
+
+/* #define CONFIG_CAM_DEBUG */
+#define cam_warn(fmt, ...)	\
+	do { \
+		printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_err(fmt, ...)	\
+	do { \
+		printk(KERN_ERR "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#define cam_info(fmt, ...)	\
+	do { \
+		printk(KERN_INFO "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+
+#ifdef CONFIG_CAM_DEBUG
+#define cam_dbg(fmt, ...)	\
+	do { \
+		printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__); \
+	} while (0)
+#else
+#define cam_dbg(fmt, ...)
+#endif /* CONFIG_CAM_DEBUG */
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return (ret); } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+	if (unlikely(condition)) { \
+		cam_err("%s: ERROR, " fmt, __func__, ##__VA_ARGS__); \
+		return ret; \
+	}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+/************ driver feature ************/
+#define sr200pc20_USLEEP
+/* #define CONFIG_LOAD_FILE */
+
+typedef struct regs_array_type {
+    unsigned short subaddr;
+    unsigned short value;
+} regs_short_t;
+
+#if 1 /*defined (CONFIG_MACH_P2_REV02)*/
+#include  "sr200pc20_regs-p2.h"
+#else
+#include  "sr200pc20_regs.h"
+#endif
+
+#endif /* __SR200PC20_H */
diff --git a/drivers/media/video/sr200pc20.c b/drivers/media/video/sr200pc20.c
new file mode 100644
index 0000000..bb752d8
--- /dev/null
+++ b/drivers/media/video/sr200pc20.c
@@ -0,0 +1,1415 @@
+/*
+ * Driver for SR200PC20 from Samsung Electronics
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+#include <media/sr200pc20_platform.h>
+#include "sr200pc20.h"
+
+static const struct sr200pc20_fps sr200pc20_framerates[] = {
+	{ I_FPS_0,	FRAME_RATE_AUTO },
+	{ I_FPS_7,	FRAME_RATE_7 },
+	{ I_FPS_10,	10 },
+	{ I_FPS_12,	12 },
+	{ I_FPS_15,	FRAME_RATE_15 },
+	{ I_FPS_25,	FRAME_RATE_25 },
+};
+
+static const struct sr200pc20_regs reg_datas = {
+	.ev = {
+		SR200PC20_REGSET(GET_EV_INDEX(EV_MINUS_4),
+					front_ev_minus_4_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_MINUS_3),
+					front_ev_minus_3_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_MINUS_2),
+					front_ev_minus_2_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_MINUS_1),
+					front_ev_minus_1_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_DEFAULT),
+					front_ev_default_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_PLUS_1), front_ev_plus_1_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_PLUS_2), front_ev_plus_2_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_PLUS_3), front_ev_plus_3_regs),
+		SR200PC20_REGSET(GET_EV_INDEX(EV_PLUS_4), front_ev_plus_4_regs),
+	},
+	.blur = {
+		SR200PC20_REGSET(BLUR_LEVEL_0, front_vt_pretty_default),
+		SR200PC20_REGSET(BLUR_LEVEL_1, front_vt_pretty_1),
+		SR200PC20_REGSET(BLUR_LEVEL_2, front_vt_pretty_2),
+		SR200PC20_REGSET(BLUR_LEVEL_3, front_vt_pretty_3),
+	},
+	.fps = {
+		SR200PC20_REGSET(I_FPS_0, front_fps_auto_regs),
+		SR200PC20_REGSET(I_FPS_7, front_fps_7_regs),
+		SR200PC20_REGSET(I_FPS_10, front_fps_10_regs),
+		SR200PC20_REGSET(I_FPS_15, front_fps_15_regs),
+		SR200PC20_REGSET(I_FPS_25, front_fps_24_regs),
+	},
+	.preview_start = SR200PC20_REGSET_TABLE(front_preview_camera_regs),
+	.capture_start = SR200PC20_REGSET_TABLE(front_snapshot_normal_regs),
+	.init = SR200PC20_REGSET_TABLE(front_init_regs),
+	.init_vt = SR200PC20_REGSET_TABLE(front_init_vt_regs),
+	.init_recording = SR200PC20_REGSET_TABLE(front_init_recording_regs),
+	.dtp_on = SR200PC20_REGSET_TABLE(front_pattern_on_regs),
+	.dtp_off = SR200PC20_REGSET_TABLE(front_pattern_off_regs),
+};
+
+#ifdef CONFIG_LOAD_FILE
+static int loadFile(void)
+{
+	struct file *fp = NULL;
+	struct test *nextBuf = NULL;
+
+	u8 *nBuf = NULL;
+	size_t file_size = 0, max_size = 0, testBuf_size = 0;
+	ssize_t nread = 0;
+	s32 check = 0, starCheck = 0;
+	s32 tmp_large_file = 0;
+	s32 i = 0;
+	int ret = 0;
+	loff_t pos;
+
+	mm_segment_t fs = get_fs();
+	set_fs(get_ds());
+
+	BUG_ON(testBuf);
+
+	fp = filp_open(TUNING_FILE_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("file open error\n");
+		return PTR_ERR(fp);
+	}
+
+	file_size = (size_t) fp->f_path.dentry->d_inode->i_size;
+	max_size = file_size;
+
+	cam_dbg("file_size = %d\n", file_size);
+
+	nBuf = kmalloc(file_size, GFP_ATOMIC);
+	if (nBuf == NULL) {
+		cam_dbg("Fail to 1st get memory\n");
+		nBuf = vmalloc(file_size);
+		if (nBuf == NULL) {
+			cam_err("ERR: nBuf Out of Memory\n");
+			ret = -ENOMEM;
+			goto error_out;
+		}
+		tmp_large_file = 1;
+	}
+
+	testBuf_size = sizeof(struct test) * file_size;
+	if (tmp_large_file) {
+		testBuf = (struct test *)vmalloc(testBuf_size);
+		large_file = 1;
+	} else {
+		testBuf = kmalloc(testBuf_size, GFP_ATOMIC);
+		if (testBuf == NULL) {
+			cam_dbg("Fail to get mem(%d bytes)\n", testBuf_size);
+			testBuf = (struct test *)vmalloc(testBuf_size);
+			large_file = 1;
+		}
+	}
+	if (testBuf == NULL) {
+		cam_err("ERR: Out of Memory\n");
+		ret = -ENOMEM;
+		goto error_out;
+	}
+
+	pos = 0;
+	memset(nBuf, 0, file_size);
+	memset(testBuf, 0, file_size * sizeof(struct test));
+
+	nread = vfs_read(fp, (char __user *)nBuf, file_size, &pos);
+	if (nread != file_size) {
+		cam_err("failed to read file ret = %d\n", nread);
+		ret = -1;
+		goto error_out;
+	}
+
+	set_fs(fs);
+
+	i = max_size;
+
+	printk("i = %d\n", i);
+
+	while (i) {
+		testBuf[max_size - i].data = *nBuf;
+		if (i != 1) {
+			testBuf[max_size - i].nextBuf = &testBuf[max_size - i + 1];
+		} else {
+			testBuf[max_size - i].nextBuf = NULL;
+			break;
+		}
+		i--;
+		nBuf++;
+	}
+
+	i = max_size;
+	nextBuf = &testBuf[0];
+
+#if 1
+	while (i - 1) {
+		if (!check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data
+								== '/') {
+						check = 1;/* when find '//' */
+						i--;
+					} else if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1;/* when find '/ *' */
+						i--;
+					}
+				} else
+					break;
+			}
+			if (!check && !starCheck) {
+				/* ignore '\t' */
+				if (testBuf[max_size - i].data != '\t') {
+					nextBuf->nextBuf = &testBuf[max_size-i];
+					nextBuf = &testBuf[max_size - i];
+				}
+			}
+		} else if (check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if(testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '*') {
+						starCheck = 1; /* when find '/ *' */
+						check = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+
+			 /* when find '\n' */
+			if (testBuf[max_size - i].data == '\n' && check) {
+				check = 0;
+				nextBuf->nextBuf = &testBuf[max_size - i];
+				nextBuf = &testBuf[max_size - i];
+			}
+
+		} else if (!check && starCheck) {
+			if (testBuf[max_size - i].data == '*') {
+				if (testBuf[max_size-i].nextBuf != NULL) {
+					if (testBuf[max_size-i].nextBuf->data == '/') {
+						starCheck = 0; /* when find '* /' */
+						i--;
+					}
+				} else
+					break;
+			}
+		}
+
+		i--;
+
+		if (i < 2) {
+			nextBuf = NULL;
+			break;
+		}
+
+		if (testBuf[max_size - i].nextBuf == NULL) {
+			nextBuf = NULL;
+			break;
+		}
+	}
+#endif
+
+#if 0 // for print
+	printk("i = %d\n", i);
+	nextBuf = &testBuf[0];
+	while (1) {
+		//printk("sdfdsf\n");
+		if (nextBuf->nextBuf == NULL)
+			break;
+		printk("%c", nextBuf->data);
+		nextBuf = nextBuf->nextBuf;
+	}
+#endif
+
+error_out:
+
+	if (nBuf)
+		tmp_large_file ? vfree(nBuf) : kfree(nBuf);
+	if (fp)
+		filp_close(fp, current->files);
+	return ret;
+}
+#endif
+
+static int __used sr200pc20_i2c_read_byte(struct i2c_client *client,
+					u16 subaddr, u16 *data)
+{
+	u8 buf[2] = {0,};
+	struct i2c_msg msg = {client->addr, 0, 1, buf};
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = (u8)subaddr;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to write %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 1;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to read %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	*(u8 *)data = buf[0];
+
+	return 0;
+}
+
+static int __used sr200pc20_i2c_write_byte(struct i2c_client *client,
+					u16 subaddr, u16 data)
+{
+	u8 buf[2] = {0,};
+	struct i2c_msg msg = {client->addr, 0, 2, buf};
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr & 0xFF;
+	buf[1] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1)? 0 : -EIO;
+}
+
+static int __used sr200pc20_i2c_read_word(struct i2c_client *client,
+					u16 subaddr, u16 *data)
+{
+	u8 buf[4];
+	struct i2c_msg msg = {client->addr, 0, 2, buf};
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr>> 8;
+	buf[1] = subaddr & 0xff;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to write %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 2;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to read %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return 0;
+}
+
+static int __used sr200pc20_i2c_write_word(struct i2c_client *client,
+					u16 subaddr, u16 data)
+{
+	u8 buf[4];
+	struct i2c_msg msg = {client->addr, 0, 4, buf};
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr >> 8;
+	buf[1] = subaddr & 0xFF;
+	buf[2] = data >> 8;
+	buf[3] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1)? 0 : -EIO;
+}
+
+static int sr200pc20_i2c_set_data_burst(struct v4l2_subdev *sd,
+					const regs_short_t reg_buffer[],
+					u32 num_of_regs)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 subaddr, data_value;
+	int i, err = 0;
+
+	for (i = 0; i < num_of_regs; i++) {
+		subaddr = reg_buffer[i].subaddr;
+		data_value = reg_buffer[i].value;
+
+		switch(subaddr) {
+		case DELAY_SEQ:
+			debug_msleep(sd, data_value * 10);
+			break;
+		default:
+			err = sr200pc20_i2c_write_byte(client, subaddr, data_value);
+			if (unlikely(err < 0)) {
+				cam_err("%s: ERROR, failed to"
+					"write reg(0x%02X, 0x%02X).err=%d\n",
+					__func__, subaddr, data_value, err);
+				return -EIO;
+			}
+			break;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_LOAD_FILE
+static int sr200pc20_write_regs_from_sd(struct v4l2_subdev *sd, u8 s_name[])
+{
+
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct test *tempData = NULL;
+
+	int ret = -EAGAIN;
+	regs_short_t temp;
+	u32 delay = 0;
+	u8 data[11];
+	s32 searched = 0, pair_cnt = 0, brace_cnt = 0;
+	size_t size = strlen(s_name);
+	s32 i;
+
+	cam_trace("E size = %d, string = %s\n", size, s_name);
+	tempData = &testBuf[0];
+	while (!searched) {
+		searched = 1;
+		for (i = 0; i < size; i++) {
+			if (tempData->data != s_name[i]) {
+				searched = 0;
+				break;
+			}
+			tempData = tempData->nextBuf;
+		}
+		tempData = tempData->nextBuf;
+	}
+	/* structure is get..*/
+
+	while (1) {
+		if (tempData->data == '{') {
+			dbg_setfile("%s: found big_brace start\n", __func__);
+			tempData = tempData->nextBuf;
+			break;
+		} else
+			tempData = tempData->nextBuf;
+	}
+
+	while (1) {
+		while (1) {
+			if (tempData->data == '{') {
+				/* dbg_setfile("%s: found small_brace start\n", __func__); */
+				tempData = tempData->nextBuf;
+				break;
+			} else if (tempData->data == '}') {
+				dbg_setfile("%s: found big_brace end\n", __func__);
+				return 0;
+			} else
+				tempData = tempData->nextBuf;
+		}
+		
+		searched = 0;
+		pair_cnt = 0;
+		while (1) {
+			if (tempData->data == 'x') {
+				/* get 10 strings.*/
+				data[0] = '0';
+				for (i = 1; i < 4; i++) {
+					data[i] = tempData->data;
+					tempData = tempData->nextBuf;
+				}
+				data[i] = '\0';
+				/* dbg_setfile("read HEX: %s\n", data); */
+				if (pair_cnt == 0) {
+					temp.subaddr = simple_strtoul(data, NULL, 16);
+					pair_cnt++;
+				} else if (pair_cnt == 1) {
+					temp.value = simple_strtoul(data, NULL, 16);
+					pair_cnt++;
+				}
+			} else if (tempData->data == '}') {
+				/* dbg_setfile("%s: found small_brace end\n", __func__); */
+				tempData = tempData->nextBuf;
+				/* searched = 1; */
+				break;
+			} else
+				tempData = tempData->nextBuf;
+
+			if (tempData->nextBuf == NULL)
+				return -1;
+		}
+
+		if (searched)
+			break;
+
+		if ((temp.subaddr & 0xFF) == 0xFF) {
+			delay = (temp.value & 0xFF) * 10;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+		/* cam_err("Write: 0x%02X, 0x%02X\n",
+				(u8)(temp.subaddr), (u8)(temp.value)); */
+		ret = sr200pc20_i2c_write_byte(client, temp.subaddr, temp.value);
+
+		/* In error circumstances */
+		/* Give second shot */
+		if (unlikely(ret)) {
+			dev_info(&client->dev,
+					"sr200pc20 i2c retry one more time\n");
+			ret = sr200pc20_i2c_write_byte(client, temp.subaddr, temp.value);
+
+			/* Give it one more shot */
+			if (unlikely(ret)) {
+				dev_info(&client->dev,
+						"sr200pc20 i2c retry twice\n");
+				ret = sr200pc20_i2c_write_byte(client, temp.subaddr, temp.value);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+static int sr200pc20_set_from_table(struct v4l2_subdev *sd,
+				const char *setting_name,
+				const struct sr200pc20_regset_table *table,
+				int table_size, int index)
+{
+	int err = 0;
+
+	/* cam_dbg("%s: set %s index %d\n",
+		__func__, setting_name, index);*/
+	if ((index < 0) || (index >= table_size)) {
+		cam_err("%s: ERROR, index(%d) out of range[0:%d]"
+			"for table for %s\n", __func__, index,
+			table_size, setting_name);
+		return -EINVAL;
+	}
+
+	table += index;
+	if (unlikely(!table->reg)) {
+		cam_err("%s: ERROR, reg = NULL\n", __func__);
+		return -EFAULT;
+	}
+
+#ifdef CONFIG_LOAD_FILE
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__, setting_name,
+						table->name);
+	return sr200pc20_write_regs_from_sd(sd, table->name);
+#else
+	err = sr200pc20_i2c_set_data_burst(sd, table->reg, table->array_size);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, fail to write regs(%s), err=%d\n",
+			__func__, setting_name, err);
+		return -EIO;
+	}
+
+	return 0;
+#endif
+}
+
+static inline int sr200pc20_get_iso(struct v4l2_subdev *sd, u16 *iso)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	/* u16 iso_gain_table[] = {10, 18, 23, 28};
+	u16 iso_table[] = {0, 50, 100, 200, 400}; */
+	u16 read_value = 0, gain = 0;
+
+
+	sr200pc20_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20_i2c_read_byte(client, 0xb0, &read_value);
+	gain = (read_value * 100  / 32) + 50;
+
+	if (read_value < 125)
+		*iso = 50;
+	else if (read_value < 175)
+		*iso = 100;
+	else if (read_value < 250)
+		*iso = 200;
+	else if (read_value < 375)
+		*iso = 400;
+	else if (read_value < 550)
+		*iso = 800;
+	else
+		*iso = 1600;
+
+	cam_dbg("gain=%d, ISO=%d\n", gain, *iso);
+
+	return 0;
+}
+
+static int sr200pc20_get_expousretime(struct v4l2_subdev *sd,
+					u32 *exp_time)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 read_value = 0;
+	u32 cintr = 0;
+
+	sr200pc20_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20_i2c_read_byte(client, 0x80, &read_value);
+	cintr = read_value << 19;
+	sr200pc20_i2c_read_byte(client, 0x81, &read_value);
+	cintr |= read_value << 11;
+	sr200pc20_i2c_read_byte(client, 0x82, &read_value);
+	cintr |= read_value << 3;
+
+	*exp_time =  cintr / 24; /* us */
+
+	return 0;
+}
+
+static int sr200pc20_get_exif(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	u32 exposure_time = 0;
+
+	/* Get exposure-time */
+	state->exif.exp_time_den = 0;
+	sr200pc20_get_expousretime(sd, &exposure_time);
+	state->exif.exp_time_den = 1000000 / exposure_time;
+	cam_dbg("exposure time=%dus\n", exposure_time);
+
+	/* Get ISO */
+	state->exif.iso = 0;
+	sr200pc20_get_iso(sd, &state->exif.iso);
+
+	cam_dbg("get_exif: exp_time_den=%d, ISO=%d\n",
+		state->exif.exp_time_den, state->exif.iso);
+	return 0;
+}
+
+#ifdef SUPPORT_FACTORY_TEST
+static int sr200pc20_check_dataline(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EIO;
+
+	if (state->pdata->is_mipi)
+		return 0;
+
+	cam_info("DTP %s\n", val ? "ON" : "OFF");
+
+	if (val)
+		err = sr200pc20_set_from_table(sd, "dtp_on",
+				&state->regs->dtp_on, 1, 0);
+	else
+		err = sr200pc20_set_from_table(sd, "dtp_off",
+				&state->regs->dtp_off, 1, 0);
+
+	CHECK_ERR_MSG(err, "fail to DTP setting\n");
+	return 0;
+}
+#endif
+
+static int sr200pc20_check_sensor_status(struct v4l2_subdev *sd)
+{
+
+	/*struct i2c_client *client = v4l2_get_subdevdata(sd);*/
+	/*u16 val_1 = 0, val_2 = 0;
+	int err = -EINVAL; */
+
+#if 1 /* DSLIM */
+	cam_warn("check_sensor_status: WARNING, Not implemented!!\n\n");
+	return 0;
+#else
+
+	err = sr200pc20_read_reg(sd, 0x7000, 0x0132, &val_1);
+	CHECK_ERR(err);
+	err = sr200pc20_read_reg(sd, 0xD000, 0x1002, &val_2);
+	CHECK_ERR(err);
+
+	cam_dbg("read val1=0x%x, val2=0x%x\n", val_1, val_2);
+
+	if ((val_1 != 0xAAAA) || (val_2 != 0))
+		goto error_occur;
+
+	cam_info("Sensor ESD Check: not detected\n");
+	return 0;
+#endif
+error_occur:
+	cam_err("%s: ERROR, ESD Shock detected!\n\n", __func__);
+	return -ERESTART;
+}
+
+static inline int sr200pc20_check_esd(struct v4l2_subdev *sd)
+{
+	int err = -EINVAL;
+
+	err = sr200pc20_check_sensor_status(sd);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int sr200pc20_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (state->first_preview) {
+		state->first_preview = 0;
+#ifdef SUPPORT_FACTORY_TEST
+		if (state->check_dataline) {
+			err = sr200pc20_check_dataline(sd, 1);
+			CHECK_ERR(err);
+		}
+#endif
+		return 0;
+	}
+
+	cam_info("set_preview_start\n");
+
+	err = sr200pc20_set_from_table(sd, "preview_start",
+		&state->regs->preview_start, 1, 0);
+	CHECK_ERR_MSG(err, "fail to make preview\n")
+
+	return 0;
+}
+
+static int sr200pc20_set_capture_start(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_capture_start\n");
+
+	err = sr200pc20_set_from_table(sd, "capture_start",
+			&state->regs->capture_start, 1, 0);
+	CHECK_ERR_MSG(err, "failed to make capture\n");
+
+	sr200pc20_get_exif(sd);
+
+	return err;
+}
+
+static int sr200pc20_set_sensor_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20_state *state = to_state(sd);
+
+	switch (val) {
+	case SENSOR_MOVIE:
+		if (state->vt_mode) {
+			state->sensor_mode = SENSOR_CAMERA;
+			cam_warn("%s: WARNING, Not support movie in vt mode\n",
+				__func__);
+			break;
+		}
+		/* We do not break. */
+	case SENSOR_CAMERA:
+		state->sensor_mode = val;
+		break;
+	default:
+		cam_err("%s: ERROR: Not support mode.(%d)\n",
+			__func__, val);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sr200pc20_init_regs(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 read_value = 0;
+	int err = -ENODEV;
+
+	err = sr200pc20_i2c_write_byte(client, 0x03, 0x00);
+	if (unlikely(err < 0))
+		return -ENODEV;
+
+	sr200pc20_i2c_read_byte(client, 0x04, &read_value);
+	if (likely(read_value == SR200PC20_CHIP_ID))
+		cam_info("Sensor ChipID: 0x%02X\n", SR200PC20_CHIP_ID);
+	else
+		cam_info("Sensor ChipID: 0x%02X, unknown chipID\n", read_value);
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_g_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	cam_trace("E\n");
+	return 0;
+}
+
+static int sr200pc20_enum_framesizes(struct v4l2_subdev *sd, \
+					struct v4l2_frmsizeenum *fsize)
+{
+	struct sr200pc20_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	/*
+	 * Return the actual output settings programmed to the camera
+	 */
+	if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		fsize->discrete.width = state->capture_frmsizes.width;
+		fsize->discrete.height = state->capture_frmsizes.height;
+	} else {
+		fsize->discrete.width = state->preview_frmsizes.width;
+		fsize->discrete.height = state->preview_frmsizes.height;
+	}
+
+	cam_info("enum_framesizes: width - %d , height - %d\n",
+		fsize->discrete.width, fsize->discrete.height);
+
+	return 0;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_try_mbus_fmt(struct v4l2_subdev *sd,
+			struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	return err;
+}
+
+#ifdef NEW_CAM_DRV
+static int sr200pc20_s_mbus_fmt(struct v4l2_subdev *sd,
+				struct v4l2_mbus_framefmt *fmt)
+#else
+static int sr200pc20_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+#endif
+{
+	struct sr200pc20_state *state = to_state(sd);
+	u32 *width = NULL, *height = NULL;
+
+	cam_trace("E\n");
+	/*
+	 * Just copying the requested format as of now.
+	 * We need to check here what are the formats the camera support, and
+	 * set the most appropriate one according to the request from FIMC
+	 */
+#ifdef NEW_CAM_DRV
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	state->req_fmt.priv = fmt->field;
+#else
+	memcpy(&state->req_fmt, &fmt->fmt.pix, sizeof(fmt->fmt.pix));
+#endif
+
+	switch (state->req_fmt.priv) {
+	case V4L2_PIX_FMT_MODE_PREVIEW:
+		width = &state->preview_frmsizes.width;
+		height = &state->preview_frmsizes.height;
+		break;
+
+	case V4L2_PIX_FMT_MODE_CAPTURE:
+		width = &state->capture_frmsizes.width;
+		height = &state->capture_frmsizes.height;
+		break;
+
+	default:
+		cam_err("%s: ERROR, inavlid FMT Mode(%d)\n",
+			__func__, state->req_fmt.priv);
+		return -EINVAL;
+	}
+
+	if ((*width != state->req_fmt.width) ||
+		(*height != state->req_fmt.height)) {
+		cam_err("%s: ERROR, Invalid size. width= %d, height= %d\n",
+			__func__, state->req_fmt.width, state->req_fmt.height);
+	}
+
+	return 0;
+}
+
+static int sr200pc20_set_frame_rate(struct v4l2_subdev *sd, s32 fps)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EIO;
+	int i = 0, fps_index = -1;
+
+	cam_info("set frame rate %d\n", fps);
+
+	for (i = 0; i < ARRAY_SIZE(sr200pc20_framerates); i++) {
+		if (fps == sr200pc20_framerates[i].fps) {
+			fps_index = sr200pc20_framerates[i].index;
+			state->fps = fps;
+			state->req_fps = -1;
+			break;
+		}
+	}
+
+	if (unlikely(fps_index < 0)) {
+		cam_err("%s: WARNING, Not supported FPS(%d)\n", __func__, fps);
+		return 0;
+	}
+
+	if (state->sensor_mode != SENSOR_MOVIE) {
+		err = sr200pc20_set_from_table(sd, "fps", state->regs->fps,
+			ARRAY_SIZE(state->regs->fps), fps_index);
+		CHECK_ERR_MSG(err, "fail to set framerate\n")
+	}
+
+	return 0;
+}
+
+static int sr200pc20_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	return err;
+}
+
+static int sr200pc20_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+	int err = 0;
+	struct sr200pc20_state *state = to_state(sd);
+
+	state->req_fps = parms->parm.capture.timeperframe.denominator /
+			parms->parm.capture.timeperframe.numerator;
+
+	cam_dbg("s_parm fps=%d, req_fps=%d\n", state->fps, state->req_fps);
+
+	if ((state->req_fps < 0) || (state->req_fps > 30)) {
+		cam_err("%s: ERROR, invalid frame rate %d. we'll set to %d\n",
+				__func__, state->req_fps, DEFAULT_FPS);
+		state->req_fps = DEFAULT_FPS;
+	}
+
+	if (state->initialized) {
+		err = sr200pc20_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+static int sr200pc20_wait_steamoff(struct v4l2_subdev *sd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	struct sr200pc20_stream_time *stream_time = &state->stream_time;
+	s32 elapsed_msec = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(!(state->pdata->is_mipi & state->need_wait_streamoff)))
+		return 0;
+
+	do_gettimeofday(&stream_time->curr_time);
+
+	elapsed_msec = GET_ELAPSED_TIME(stream_time->curr_time, \
+				stream_time->before_time) / 1000;
+
+	if (state->pdata->streamoff_delay > elapsed_msec) {
+		cam_info("stream-off: %dms + %dms\n", elapsed_msec,
+			state->pdata->streamoff_delay - elapsed_msec);
+		debug_msleep(sd, state->pdata->streamoff_delay - elapsed_msec);
+	} else
+		cam_info("stream-off: %dms\n", elapsed_msec);
+
+	state->need_wait_streamoff = 0;
+
+	return 0;
+}
+
+static int sr200pc20_control_stream(struct v4l2_subdev *sd, u32 cmd)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (unlikely(cmd != STREAM_STOP))
+		return 0;
+
+	cam_info("STREAM STOP!!\n");
+	err = 0;
+	CHECK_ERR_MSG(err, "failed to stop stream\n");
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	do_gettimeofday(&state->stream_time.before_time);
+	state->need_wait_streamoff = 1;
+#else
+	debug_msleep(sd, state->pdata->streamoff_delay);
+#endif
+	return 0;
+}
+
+static int sr200pc20_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	err = sr200pc20_init_regs(sd);
+	CHECK_ERR_MSG(err, "failed to indentify sensor chip\n");
+
+	/* set initial regster value */
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			cam_info("load camera common setting\n");
+			err = sr200pc20_set_from_table(sd, "init",
+					&state->regs->init, 1, 0);
+		} else {
+			cam_info("load camera WIFI VT call setting\n");
+			err = sr200pc20_set_from_table(sd, "init_vt",
+					&state->regs->init_vt, 1, 0);
+		}
+	} else {
+			cam_info("load recording setting\n");
+			err = sr200pc20_set_from_table(sd, "init_recording",
+					&state->regs->init_recording, 1, 0);
+	}
+	CHECK_ERR_MSG(err, "failed to initialize camera device\n");
+
+	state->first_preview = 1;
+	state->initialized = 1;
+
+	if (state->req_fps >= 0) {
+		err = sr200pc20_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int sr200pc20_s_config(struct v4l2_subdev *sd,
+		int irq, void *platform_data)
+{
+	struct sr200pc20_state *state = to_state(sd);
+#ifdef CONFIG_LOAD_FILE
+	int err = 0;
+#endif
+
+	if (!platform_data) {
+		cam_err("%s: ERROR, no platform data\n", __func__);
+		return -ENODEV;
+	}
+	state->pdata = platform_data;
+	state->dbg_level = &state->pdata->dbg_level;
+
+	state->initialized = 0;
+	state->fps = 0;
+	state->req_fps = -1;
+	state->sensor_mode = SENSOR_CAMERA;
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	if (!(state->pdata->default_width && state->pdata->default_height)) {
+		state->default_frmsizes.width = DEFAULT_PREVIEW_WIDTH;
+		state->default_frmsizes.height = DEFAULT_PREVIEW_HEIGHT;
+	} else {
+		state->default_frmsizes.width = state->pdata->default_width;
+		state->default_frmsizes.height = state->pdata->default_height;
+	}
+
+	state->preview_frmsizes.width = state->default_frmsizes.width;
+	state->preview_frmsizes.height = state->default_frmsizes.height;
+	state->capture_frmsizes.width = DEFAULT_CAPTURE_WIDTH;
+	state->capture_frmsizes.height = DEFAULT_CAPTURE_HEIGHT;
+
+	cam_dbg("Default preview_width: %d , preview_height: %d, "
+		"capture_width: %d, capture_height: %d",
+		state->preview_frmsizes.width, state->preview_frmsizes.height,
+		state->capture_frmsizes.width, state->capture_frmsizes.height);
+
+	state->req_fmt.width = state->preview_frmsizes.width;
+	state->req_fmt.height = state->preview_frmsizes.height;
+	if (!state->pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_FMT;
+	else
+		state->req_fmt.pixelformat = state->pdata->pixelformat;
+
+#ifdef CONFIG_LOAD_FILE
+	err = loadFile();
+	CHECK_ERR_MSG(err, "failed to load file ERR=%d\n", err)
+#endif
+
+	return 0;
+}
+
+static int sr200pc20_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("s_stream: mode = %d\n", enable);
+
+	BUG_ON(!state->initialized);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->sensor_mode == SENSOR_CAMERA) {
+#ifdef SUPPORT_FACTORY_TEST
+			if (state->check_dataline)
+				err = sr200pc20_check_dataline(sd, 0);
+			else
+#endif
+				if (state->pdata->is_mipi)
+					err = sr200pc20_control_stream(sd,
+							STREAM_STOP);
+		}
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		if ((state->sensor_mode == SENSOR_CAMERA)
+		    && (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE))
+			err = sr200pc20_set_capture_start(sd);
+		else
+			err = sr200pc20_set_preview_start(sd);
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_dbg("%s: do nothing(movie on)!!\n", __func__);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_dbg("%s: do nothing(movie off)!!\n", __func__);
+		break;
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	case STREAM_MODE_WAIT_OFF:
+		err = sr200pc20_wait_steamoff(sd);
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR, Invalid stream mode %d\n",
+					__func__, enable);
+		err = -EINVAL;
+		break;
+	}
+
+	CHECK_ERR_MSG(err, "stream on(off) fail")
+
+	return 0;
+}
+
+static int sr200pc20_set_exposure(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_exposure: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if ((val < EV_MINUS_4) || (val >= EV_MAX_V4L2)) {
+		cam_err("%s: ERROR, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = sr200pc20_set_from_table(sd, "ev", state->regs->ev,
+		ARRAY_SIZE(state->regs->ev), GET_EV_INDEX(val));
+	CHECK_ERR_MSG(err, "i2c_write for set brightness\n")
+
+	return 0;
+}
+
+static int sr200pc20_set_blur(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_blur: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if (unlikely(val < BLUR_LEVEL_0 || val >= BLUR_LEVEL_MAX)) {
+		cam_err("%s: ERROR, invalid blur(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = sr200pc20_set_from_table(sd, "blur", state->regs->blur,
+		ARRAY_SIZE(state->regs->blur), val);
+	CHECK_ERR_MSG(err, "i2c_write for set blur\n")
+
+	return 0;
+}
+
+static int sr200pc20_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("g_ctrl: id = %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		ctrl->value = state->exif.exp_time_den;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+
+	default:
+		cam_err("%s: ERROR, no such control id %d\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	return err;
+}
+
+static int sr200pc20_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct sr200pc20_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("s_ctrl: id = %d, value=%d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if ((ctrl->id != V4L2_CID_CAMERA_CHECK_DATALINE)
+	    && (ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE)
+	    && ((ctrl->id != V4L2_CID_CAMERA_VT_MODE))
+	    && (!state->initialized)) {
+		cam_warn("%s: WARNING, camera not initialized\n", __func__);
+		return 0;
+	}
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = sr200pc20_set_exposure(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_BRIGHTNESS [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		err = sr200pc20_set_blur(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_VGA_BLUR [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = sr200pc20_set_sensor_mode(sd, ctrl->value);
+		cam_dbg("sensor_mode = %d\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = sr200pc20_check_esd(sd);
+		break;
+
+#ifdef SUPPORT_FACTORY_TEST
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		cam_dbg("check_dataline = %d\n", state->check_dataline);
+		err = 0;
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR, not supported ctrl-ID(%d)\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/* no errors return.*/
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops sr200pc20_core_ops = {
+	.init = sr200pc20_init,		/* initializing API */
+	.g_ctrl = sr200pc20_g_ctrl,
+	.s_ctrl = sr200pc20_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops sr200pc20_video_ops = {
+	/*.s_crystal_freq = sr200pc20_s_crystal_freq,*/
+#ifdef NEW_CAM_DRV
+	.g_mbus_fmt = sr200pc20_g_mbus_fmt,
+	.s_mbus_fmt = sr200pc20_s_mbus_fmt,
+#else
+	.g_fmt	= sr200pc20_g_fmt,
+	.s_fmt	= sr200pc20_s_fmt,
+#endif
+	.s_stream = sr200pc20_s_stream,
+	.enum_framesizes = sr200pc20_enum_framesizes,
+	/*.enum_frameintervals = sr200pc20_enum_frameintervals,*/
+#ifdef NEW_CAM_DRV
+	/* .enum_mbus_fmt = sr200pc20_enum_mbus_fmt, */
+	.try_mbus_fmt = sr200pc20_try_mbus_fmt,
+#else
+	/*.enum_fmt = sr200pc20_enum_fmt,*/
+	.try_fmt = sr200pc20_try_fmt,
+#endif
+	.g_parm	= sr200pc20_g_parm,
+	.s_parm	= sr200pc20_s_parm,
+};
+
+static const struct v4l2_subdev_ops sr200pc20_ops = {
+	.core = &sr200pc20_core_ops,
+	.video = &sr200pc20_video_ops,
+};
+
+/*
+ * sr200pc20_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int sr200pc20_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	struct sr200pc20_state *state = NULL;
+	struct v4l2_subdev *sd = NULL;
+	int err = -EINVAL;
+
+	state = kzalloc(sizeof(struct sr200pc20_state), GFP_KERNEL);
+	CHECK_ERR_COND_MSG(!state, -ENOMEM, "fail to get memory(state)\n");
+
+	mutex_init(&state->ctrl_lock);
+
+	sd = &state->sd;
+	strcpy(sd->name, SR200PC20_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &sr200pc20_ops);
+
+	err = sr200pc20_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+	printk(KERN_DEBUG "%s %s: driver probed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static int sr200pc20_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct sr200pc20_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	state->initialized = 0;
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(state);
+
+#ifdef CONFIG_LOAD_FILE
+	if (testBuf) {
+		large_file ? vfree(testBuf) : kfree(testBuf);
+		large_file = 0;
+		testBuf = NULL;
+	}
+#endif
+
+	printk(KERN_DEBUG "%s %s: driver removed!!\n",
+		dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static const struct i2c_device_id sr200pc20_id[] = {
+	{ SR200PC20_DRIVER_NAME, 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, sr200pc20_id);
+
+static struct i2c_driver v4l2_i2c_driver = {
+	.driver.name	= SR200PC20_DRIVER_NAME,
+	.probe		= sr200pc20_probe,
+	.remove		= sr200pc20_remove,
+	.id_table	= sr200pc20_id,
+};
+
+static int __init v4l2_i2c_drv_init(void)
+{
+	pr_info("%s: %s called\n", __func__, SR200PC20_DRIVER_NAME); /* dslim*/
+	return i2c_add_driver(&v4l2_i2c_driver);
+}
+
+static void __exit v4l2_i2c_drv_cleanup(void)
+{
+	pr_info("%s: %s called\n", __func__, SR200PC20_DRIVER_NAME); /* dslim*/
+	i2c_del_driver(&v4l2_i2c_driver);
+}
+
+module_init(v4l2_i2c_drv_init);
+module_exit(v4l2_i2c_drv_cleanup);
+
+MODULE_DESCRIPTION("SR200PC20 ISP driver");
+MODULE_AUTHOR("DongSeong Lim<dongseong.lim@samsung.com>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/video/sr200pc20.h b/drivers/media/video/sr200pc20.h
new file mode 100644
index 0000000..8101c2a
--- /dev/null
+++ b/drivers/media/video/sr200pc20.h
@@ -0,0 +1,275 @@
+/*
+ * Driver for SR200PC20 2M ISP from Samsung
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __SR200PC20_H
+#define __SR200PC20_H
+
+#include <linux/types.h>
+
+#define SR200PC20_DRIVER_NAME	"SR200PC20"
+
+/************************************
+ * FEATURE DEFINITIONS
+ ************************************/
+/* #define SR200PC20_USLEEP */
+/* #define CONFIG_LOAD_FILE */
+#define SUPPORT_FACTORY_TEST
+#define NEW_CAM_DRV
+
+/** Debuging Feature **/
+#define CONFIG_CAM_DEBUG
+#define CONFIG_CAM_TRACE /* Enable it with CONFIG_CAM_DEBUG */
+/***********************************/
+
+#define TAG_NAME	"["SR200PC20_DRIVER_NAME"]"" "
+#define cam_err(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_warn(fmt, ...)	\
+	printk(KERN_WARNING TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_info(fmt, ...)	\
+	printk(KERN_INFO TAG_NAME fmt, ##__VA_ARGS__)
+
+#if defined(CONFIG_CAM_DEBUG)
+#define cam_dbg(fmt, ...)	\
+	printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_DEBUG) \
+			printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__); \
+	} while (0)
+#endif /* CONFIG_CAM_DEBUG */
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_TRACE)
+#define cam_trace(fmt, ...)	cam_dbg("%s: " fmt, __func__, ##__VA_ARGS__);
+#else
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_TRACE) \
+			printk(KERN_DEBUG TAG_NAME "%s: " fmt, \
+				__func__, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return (ret); } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+	if (unlikely(condition)) { \
+		cam_err("%s: ERROR, " fmt, __func__, ##__VA_ARGS__); \
+		return ret; \
+	}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+
+
+enum stream_cmd {
+	STREAM_STOP,
+	STREAM_START,
+};
+
+enum sr200pc20_fps_index {
+	I_FPS_0,
+	I_FPS_7,
+	I_FPS_10,
+	I_FPS_12,
+	I_FPS_15,
+	I_FPS_25,
+	I_FPS_30,
+	I_FPS_MAX,
+};
+#define DEFAULT_FPS	15
+
+struct sr200pc20_framesize {
+	u32 width;
+	u32 height;
+};
+
+struct sr200pc20_fps {
+	u32 index;
+	u32 fps;
+};
+
+struct sr200pc20_exif {
+	u16 exp_time_den;
+	u16 iso;
+	u32 shutter_speed;
+};
+
+struct sr200pc20_stream_time {
+	struct timeval curr_time;
+	struct timeval before_time;
+};
+
+#define GET_ELAPSED_TIME(cur, before) \
+		(((cur).tv_sec - (before).tv_sec) * USEC_PER_SEC \
+		+ ((cur).tv_usec - (before).tv_usec))
+
+typedef struct regs_array_type {
+	u16 subaddr;
+	u16 value;
+} regs_short_t;
+
+#ifdef CONFIG_LOAD_FILE
+struct sr200pc20_regset_table {
+	const regs_short_t	*reg;
+	int			array_size;
+	char			*name;
+};
+
+#define SR200PC20_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+
+#define SR200PC20_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+#else
+struct sr200pc20_regset_table {
+	const regs_short_t	*reg;
+	int			array_size;
+};
+
+#define SR200PC20_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+
+#define SR200PC20_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+#endif
+
+#define EV_MIN_VLAUE	EV_MINUS_4
+#define GET_EV_INDEX(EV)	((EV) - (EV_MIN_VLAUE))
+
+struct sr200pc20_regs {
+	struct sr200pc20_regset_table ev[GET_EV_INDEX(EV_MAX_V4L2)];
+	struct sr200pc20_regset_table blur[BLUR_LEVEL_MAX];
+	/* struct sr200pc20_regset_table capture_size[SR200PC20_CAPTURE_MAX];*/
+	struct sr200pc20_regset_table preview_start;
+	struct sr200pc20_regset_table capture_start;
+	struct sr200pc20_regset_table fps[I_FPS_MAX];
+	struct sr200pc20_regset_table init;
+	struct sr200pc20_regset_table init_vt;
+	struct sr200pc20_regset_table init_vt_wifi;
+	struct sr200pc20_regset_table init_recording;
+	struct sr200pc20_regset_table get_light_level;
+	struct sr200pc20_regset_table stream_stop;
+	struct sr200pc20_regset_table dtp_on;
+	struct sr200pc20_regset_table dtp_off;
+};
+
+/*
+ * Driver information
+ */
+struct sr200pc20_state {
+	struct v4l2_subdev sd;
+	struct sr200pc20_platform_data *pdata;
+	/*
+	 * req_fmt is the requested format from the application.
+	 * set_fmt is the output format of the camera. Finally FIMC
+	 * converts the camera output(set_fmt) to the requested format
+	 * with hardware scaler.
+	 */
+	struct v4l2_pix_format req_fmt;
+	struct sr200pc20_framesize default_frmsizes;
+	struct sr200pc20_framesize preview_frmsizes;
+	struct sr200pc20_framesize capture_frmsizes;
+	struct sr200pc20_exif exif;
+	struct sr200pc20_stream_time stream_time;
+	const struct sr200pc20_regs *regs;
+	struct mutex ctrl_lock;
+
+	enum v4l2_sensor_mode sensor_mode;
+	s32 vt_mode;
+	s32 req_fps;
+	s32 fps;
+	u8 *dbg_level;
+
+	u32 check_dataline:1;
+	u32 need_wait_streamoff:1;
+	u32 first_preview:1;
+	u32 initialized:1;
+};
+
+static inline struct sr200pc20_state *to_state(struct v4l2_subdev *sd) {
+	return container_of(sd, struct sr200pc20_state, sd);
+}
+
+static inline void debug_msleep(struct v4l2_subdev *sd, u32 msecs)
+{
+	cam_dbg("delay for %dms\n", msecs);
+	msleep(msecs);
+}
+
+/*********** Sensor specific ************/
+#define DELAY_SEQ               0xFF
+#define SR200PC20_CHIP_ID	0x92
+
+
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+struct test {
+	u8 data;
+	struct test *nextBuf;
+};
+static struct test *testBuf;
+static s32 large_file;
+
+#define TEST_INIT	\
+{			\
+	.data = 0;	\
+	.nextBuf = NULL;	\
+}
+#if 0
+#define dbg_setfile(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define dbg_setfile(fmt, ...)
+#endif /* 0 */
+
+#ifdef CONFIG_VIDEO_SR200PC20_P2
+#define TUNING_FILE_PATH "/mnt/sdcard/sr200pc20_regs-p2.h"
+#elif defined(CONFIG_VIDEO_SR200PC20_P4W)
+#define TUNING_FILE_PATH "/mnt/sdcard/sr200pc20_regs-p4w.h"
+#else
+#define TUNING_FILE_PATH NULL
+#endif /* CONFIG_VIDEO_SR200PC20_P2 */
+
+#endif /* CONFIG_LOAD_FILE */
+
+#ifdef CONFIG_VIDEO_SR200PC20_P2
+#include  "sr200pc20_regs-p4w.h"
+/* #include  "sr200pc20_regs-p2.h" */
+#else
+#include  "sr200pc20_regs-p4w.h"
+#endif
+
+#endif /* __SR200PC20_H */
+
diff --git a/drivers/media/video/sr200pc20_regs-p2.h b/drivers/media/video/sr200pc20_regs-p2.h
new file mode 100644
index 0000000..f72b372
--- /dev/null
+++ b/drivers/media/video/sr200pc20_regs-p2.h
@@ -0,0 +1,7125 @@
+/*
+ * Driver for SR200PC20 2M ISP from Samsung
+ *
+ * Copyright (C) 2011,
+ * DongSeong Lim<dongseong.lim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __SR200PC200_REGS_P2_H__
+#define __SR200PC200_REGS_P2_H__
+
+#include <linux/types.h>
+
+/*
+ * sr200pc20 register configuration for combinations of initialization
+ */
+/* 2M parallel setting-common from PARTRON */
+/*******************************************************
+* Name		: SR200PC20 Initial Setfile
+* PLL mode	: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS		: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by	: emine
+* Date		: 2011.09.21
+* History	:
+*******************************************************/
+//==========================================================
+//	CAMERA INITIAL for Self Camera(Variable Frame)
+//==========================================================
+regs_short_t front_init_50hz_regs[] = {
+
+/////// Start Sleep ///////
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //PLLx2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, //AE off 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //AWB off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x19}, //Vsync Active High B:[3]
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x90},
+#else
+{0x11, 0x92},
+#endif
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa}, //ESD Check Register
+{0x0c, 0xaa}, //ESD Check Register
+{0x0d, 0xaa}, //ESD Check Register
+
+{0x20, 0x00},
+{0x21, 0x02},  //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank_360
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x58}, //Flick Stop 50hz
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0c}, //BLC_TIME_TH_ON
+{0x91, 0x0c}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826 Ãß°¡
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0c}, //DCDC_TIME_TH_ON
+{0xd5, 0x0c}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02}, //For Preview
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a}, //77
+{0x62, 0x74}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00}, //For Preview
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+//only for Preview DPC 
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+//only for Preview DPC 
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+//only for Preview DPC 
+{0xd7, 0xff},
+
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0xff},
+{0x2b, 0xf4},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70}, //6c
+{0x71, 0x82}, //82(+8)
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24}, //24
+{0x79, 0x48}, // Y Target 70 => 25, 72 => 26 //
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps
+{0x84, 0x5f},
+{0x85, 0x90},
+
+{0x86, 0x01}, //EXPMin 6000.00 fps
+{0x87, 0xf4},
+
+{0x88, 0x05}, //EXP Max 8.33 fps
+{0x89, 0x7e},
+{0x8a, 0x40},
+
+{0x8B, 0x75}, //EXP100, PLLx2 Mclk24
+{0x8C, 0x30},
+
+{0x8D, 0x61}, //EXP120, PLLx2 Mclk24
+{0x8E, 0xa8},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps, PLLx2 Mclk24
+{0x9d, 0x70},
+
+{0x9e, 0x01}, //EXP Unit, PLLx2 Mclk24
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x40},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x9c}, //AE on 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x0a},//NEED Delay 100ms//
+
+};
+
+regs_short_t front_init_60hz_regs[] = {
+
+/////// Start Sleep ///////
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //PLLx2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x0c}, //AE off 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //AWB off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x19}, //Vsync Active High B:[3]
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x90},
+#else
+{0x11, 0x92},
+#endif
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa}, //ESD Check Register
+{0x0c, 0xaa}, //ESD Check Register
+{0x0d, 0xaa}, //ESD Check Register
+
+{0x20, 0x00},
+{0x21, 0x02},  //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank_360
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x44}, //Flick Stop 60hz
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0f}, //BLC_TIME_TH_ON
+{0x91, 0x0f}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826 Ãß°¡
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0f}, //DCDC_TIME_TH_ON
+{0xd5, 0x0f}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02}, //For Preview
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a}, //77
+{0x62, 0x74}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00}, //For Preview
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+//only for Preview DPC 
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+//only for Preview DPC 
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+//only for Preview DPC 
+{0xd7, 0xff},
+
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0xff},
+{0x2b, 0xf4},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70}, //6c
+{0x71, 0x82}, //82(+8)
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24}, //24
+{0x79, 0x48}, // Y Target 70 => 25, 72 => 26 //
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 30.00 fps
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01}, //EXPMin 6000.00 fps
+{0x87, 0xf4},
+
+{0x88, 0x05}, //EXP Max 8.00 fps
+{0x89, 0xb8},
+{0x8a, 0xd8},
+
+{0x8B, 0x75}, //EXP100, PLLx2 Mclk24
+{0x8C, 0x30},
+
+{0x8D, 0x61}, //EXP120, PLLx2 Mclk24
+{0x8E, 0xa8},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps, PLLx2 Mclk24
+{0x9d, 0x70},
+
+{0x9e, 0x01}, //EXP Unit, PLLx2 Mclk24
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x40},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x8c}, //AE on 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x0a},//NEED Delay 100ms//
+
+};
+
+//==========================================================
+//	CAMERA INITIAL for Self Recording 24 Fixed Frame
+//==========================================================
+regs_short_t  front_init_vt_50hz_regs[] = {
+
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, //AE off 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x1b}, //Vsync Active High B:[3]
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x94},
+#else
+{0x11, 0x96},
+#endif
+
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank 352
+{0x41, 0x60},
+{0x42, 0x00}, //Vblank 20
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x04}, //BLC_TIME_TH_ON
+{0x91, 0x04}, //BLC_TIME_TH_OFF
+{0x92, 0xb0}, //BLC_AG_TH_ON
+{0x93, 0xa8}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x04}, //DCDC_TIME_TH_ON
+{0xd5, 0x04}, //DCDC_TIME_TH_OFF
+{0xd6, 0xb0}, //DCDC_AG_TH_ON
+{0xd7, 0xa8}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00}, //Setting For Camcorder 24
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x67}, //Setting For Camcorder 24
+{0x61, 0x7a}, //77
+{0x62, 0x79}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x0f}, //Setting For Camcorder 24
+{0x21, 0x0f}, //Setting For Camcorder 24
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d}, //Setting For Camcorder 24
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0xfd}, //Setting For Camcorder 24
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x1c},
+{0x73, 0x32},
+{0x74, 0x54},
+{0x75, 0x70},
+{0x76, 0x87},
+{0x77, 0x9a},
+{0x78, 0xaa},
+{0x79, 0xb9},
+{0x7a, 0xc4},
+{0x7b, 0xcf},
+{0x7c, 0xd8},
+{0x7d, 0xe0},
+{0x7e, 0xe9},
+{0x7f, 0xf0},
+{0x80, 0xf7},
+{0x81, 0xfc},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},
+{0x79, 0x49},
+{0x7a, 0x23},
+{0x7b, 0x22},
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps
+{0x84, 0x5f},
+{0x85, 0x6c},
+
+{0x86, 0x01}, //EXPMin 10204.08 fps
+{0x87, 0x26},
+
+{0x88, 0x01}, //EXP Max 25.00 fps
+{0x89, 0xd4},
+{0x8a, 0x90},
+
+{0x8B, 0x75}, //EXP100
+{0x8C, 0x24},
+
+{0x8D, 0x61}, //EXP120
+{0x8E, 0x9e},
+
+{0x91, 0x01}, //EXP Fix 23.93 fps
+{0x92, 0xe9},
+{0x93, 0xcf},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x0e}, //EXP Limit 784.93 fps
+{0x9d, 0xee},
+
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0x26},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xb8},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x20},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x9c}, //AE on 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+regs_short_t  front_init_vt_60hz_regs[] = {
+
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x0c}, //AE off 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x1b}, //Vsync Active High B:[3]
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x94},
+#else
+{0x11, 0x96},
+#endif
+
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank 352
+{0x41, 0x60},
+{0x42, 0x00}, //Vblank 20
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x05}, //BLC_TIME_TH_ON
+{0x91, 0x05}, //BLC_TIME_TH_OFF
+{0x92, 0xb0}, //BLC_AG_TH_ON
+{0x93, 0xa8}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x05}, //DCDC_TIME_TH_ON
+{0xd5, 0x05}, //DCDC_TIME_TH_OFF
+{0xd6, 0xb0}, //DCDC_AG_TH_ON
+{0xd7, 0xa8}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00}, //Setting For Camcorder 24
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x67}, //Setting For Camcorder 24
+{0x61, 0x7a}, //77
+{0x62, 0x79}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x0f}, //Setting For Camcorder 24
+{0x21, 0x0f}, //Setting For Camcorder 24
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d}, //Setting For Camcorder 24
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0xfd}, //Setting For Camcorder 24
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x1c},
+{0x73, 0x32},
+{0x74, 0x54},
+{0x75, 0x70},
+{0x76, 0x87},
+{0x77, 0x9a},
+{0x78, 0xaa},
+{0x79, 0xb9},
+{0x7a, 0xc4},
+{0x7b, 0xcf},
+{0x7c, 0xd8},
+{0x7d, 0xe0},
+{0x7e, 0xe9},
+{0x7f, 0xf0},
+{0x80, 0xf7},
+{0x81, 0xfc},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},
+{0x79, 0x49},
+{0x7a, 0x23},
+{0x7b, 0x22},
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 30.00 fps
+{0x84, 0x86},
+{0x85, 0x78},
+
+{0x86, 0x01}, //EXPMin 10204.08 fps
+{0x87, 0x26},
+
+{0x88, 0x01}, //EXP Max 24.00 fps
+{0x89, 0xe8},
+{0x8a, 0x16},
+
+{0x8B, 0x75}, //EXP100
+{0x8C, 0x24},
+
+{0x8D, 0x61}, //EXP120
+{0x8E, 0x9e},
+
+{0x91, 0x01}, //EXP Fix 23.93 fps
+{0x92, 0xe9},
+{0x93, 0xcf},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x0e}, //EXP Limit 784.93 fps
+{0x9d, 0xee},
+
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0x26},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xb8},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x20},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x8c}, //AE on 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+//==========================================================
+//	CAMERA INITIAL for VT 15 Fixed Frame
+//==========================================================
+regs_short_t  front_init_vt_15_50hz_regs[] = {
+/////// Start Sleep ///////
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, //AE off 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x19}, //Vsync Active High B:[3]
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x94},
+#else
+{0x11, 0x96},
+#endif
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x02}, //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank_360
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x06}, //BLC_TIME_TH_ON
+{0x91, 0x06}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x06}, //DCDC_TIME_TH_ON
+{0xd5, 0x06}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02}, //For Preview
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a}, //77
+{0x62, 0x79}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x09},
+{0x3a, 0x06},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x12},
+{0x46, 0x10},
+{0x47, 0x10},
+
+//Dark2 D-LPF th
+{0x48, 0x90},
+{0x49, 0x40},
+{0x4a, 0x80},
+{0x4b, 0x13},
+{0x4c, 0x10},
+{0x4d, 0x11},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x30},
+{0x50, 0x80},
+{0x51, 0x13},
+{0x52, 0x10},
+{0x53, 0x13},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xa0},
+{0x49, 0x90},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x60},
+{0x54, 0xc0},
+{0x55, 0xc0},
+{0x56, 0xc0},
+{0x57, 0x80},
+
+//Dark2 th
+{0x58, 0x90},
+{0x59, 0x40},
+{0x5a, 0xd0},
+{0x5b, 0xd0},
+{0x5c, 0xe0},
+{0x5d, 0x80},
+
+//Dark3 th
+{0x5e, 0x88},
+{0x5f, 0x40},
+{0x60, 0xe0},
+{0x61, 0xe0},
+{0x62, 0xe0},
+{0x63, 0x80},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00}, //For Preview
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+//only for Preview DPC 
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+//only for Preview DPC 
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+//only for Preview DPC 
+{0xd7, 0xff},
+
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x10},
+{0x57, 0x13},
+{0x58, 0x12},
+{0x59, 0x0c},
+{0x5a, 0x0f},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x08},
+{0x63, 0x08},
+{0x64, 0x08},
+{0x65, 0x06},
+{0x66, 0x06},
+{0x67, 0x06},
+
+//Dark2 Edge
+{0x68, 0x07},
+{0x69, 0x07},
+{0x6a, 0x07},
+{0x6b, 0x05},
+{0x6c, 0x05},
+{0x6d, 0x05},
+
+//Dark3 Edge
+{0x6e, 0x07},
+{0x6f, 0x07},
+{0x70, 0x07},
+{0x71, 0x05},
+{0x72, 0x05},
+{0x73, 0x05},
+
+//2DY
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x0a},
+{0x32, 0x1f},
+{0x33, 0x33},
+{0x34, 0x53},
+{0x35, 0x6c},
+{0x36, 0x81},
+{0x37, 0x94},
+{0x38, 0xa4},
+{0x39, 0xb3},
+{0x3a, 0xc0},
+{0x3b, 0xcb},
+{0x3c, 0xd5},
+{0x3d, 0xde},
+{0x3e, 0xe6},
+{0x3f, 0xee},
+{0x40, 0xf5},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x17},
+{0x73, 0x2f},
+{0x74, 0x53},
+{0x75, 0x6c},
+{0x76, 0x81},
+{0x77, 0x94},
+{0x78, 0xa4},
+{0x79, 0xb3},
+{0x7a, 0xc0},
+{0x7b, 0xcb},
+{0x7c, 0xd5},
+{0x7d, 0xde},
+{0x7e, 0xe6},
+{0x7f, 0xee},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x3a, 0xde},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70}, //6c
+{0x71, 0x82}, //82(+8)
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24}, //24
+{0x79, 0x48}, // Y Target 70 => 25, 72 => 26 //
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps
+{0x84, 0x5f},
+{0x85, 0x90},
+
+{0x86, 0x01}, //EXPMin 6000.00 fps
+{0x87, 0xf4},
+
+{0x88, 0x02}, //EXP Max 16.67 fps
+{0x89, 0xbf},
+{0x8a, 0x20},
+
+{0x8B, 0x75}, //EXP100, PLLx2 Mclk24
+{0x8C, 0x30},
+
+{0x8D, 0x61}, //EXP120, PLLx2 Mclk24
+{0x8E, 0xa8},
+
+{0x91, 0x03}, //EXP Fix 14.91 fps
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps, PLLx2 Mclk24
+{0x9d, 0x70},
+
+{0x9e, 0x01}, //EXP Unit, PLLx2 Mclk24
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x40},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x9c}, //AE on 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+regs_short_t  front_init_vt_15_60hz_regs[] = {
+/////// Start Sleep ///////
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x0c}, //AE off 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x19}, //Vsync Active High B:[3]
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x94},
+#else
+{0x11, 0x96},
+#endif
+{0x12, 0x00}, //Pclk Falling Edge B:[2]
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x02}, //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank_360
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x08}, //BLC_TIME_TH_ON
+{0x91, 0x08}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x08}, //DCDC_TIME_TH_ON
+{0xd5, 0x08}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02}, //For Preview
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a}, //77
+{0x62, 0x79}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x09},
+{0x3a, 0x06},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x12},
+{0x46, 0x10},
+{0x47, 0x10},
+
+//Dark2 D-LPF th
+{0x48, 0x90},
+{0x49, 0x40},
+{0x4a, 0x80},
+{0x4b, 0x13},
+{0x4c, 0x10},
+{0x4d, 0x11},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x30},
+{0x50, 0x80},
+{0x51, 0x13},
+{0x52, 0x10},
+{0x53, 0x13},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xa0},
+{0x49, 0x90},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x60},
+{0x54, 0xc0},
+{0x55, 0xc0},
+{0x56, 0xc0},
+{0x57, 0x80},
+
+//Dark2 th
+{0x58, 0x90},
+{0x59, 0x40},
+{0x5a, 0xd0},
+{0x5b, 0xd0},
+{0x5c, 0xe0},
+{0x5d, 0x80},
+
+//Dark3 th
+{0x5e, 0x88},
+{0x5f, 0x40},
+{0x60, 0xe0},
+{0x61, 0xe0},
+{0x62, 0xe0},
+{0x63, 0x80},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00}, //For Preview
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+//only for Preview DPC 
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+//only for Preview DPC 
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+//only for Preview DPC 
+{0xd7, 0xff},
+
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x10},
+{0x57, 0x13},
+{0x58, 0x12},
+{0x59, 0x0c},
+{0x5a, 0x0f},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x08},
+{0x63, 0x08},
+{0x64, 0x08},
+{0x65, 0x06},
+{0x66, 0x06},
+{0x67, 0x06},
+
+//Dark2 Edge
+{0x68, 0x07},
+{0x69, 0x07},
+{0x6a, 0x07},
+{0x6b, 0x05},
+{0x6c, 0x05},
+{0x6d, 0x05},
+
+//Dark3 Edge
+{0x6e, 0x07},
+{0x6f, 0x07},
+{0x70, 0x07},
+{0x71, 0x05},
+{0x72, 0x05},
+{0x73, 0x05},
+
+//2DY
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, //2d
+{0x60, 0x24}, //26
+{0x70, 0x28}, //2d
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x0a},
+{0x32, 0x1f},
+{0x33, 0x33},
+{0x34, 0x53},
+{0x35, 0x6c},
+{0x36, 0x81},
+{0x37, 0x94},
+{0x38, 0xa4},
+{0x39, 0xb3},
+{0x3a, 0xc0},
+{0x3b, 0xcb},
+{0x3c, 0xd5},
+{0x3d, 0xde},
+{0x3e, 0xe6},
+{0x3f, 0xee},
+{0x40, 0xf5},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x17},
+{0x73, 0x2f},
+{0x74, 0x53},
+{0x75, 0x6c},
+{0x76, 0x81},
+{0x77, 0x94},
+{0x78, 0xa4},
+{0x79, 0xb3},
+{0x7a, 0xc0},
+{0x7b, 0xcb},
+{0x7c, 0xd5},
+{0x7d, 0xde},
+{0x7e, 0xe6},
+{0x7f, 0xee},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x3a, 0xde},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70}, //6c
+{0x71, 0x82}, //82(+8)
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24}, //24
+{0x79, 0x48}, // Y Target 70 => 25, 72 => 26 //
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 30.00 fps
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01}, //EXPMin 6000.00 fps
+{0x87, 0xf4},
+
+{0x88, 0x03}, //EXP Max 15.00 fps
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x8B, 0x75}, //EXP100, PLLx2 Mclk24
+{0x8C, 0x30},
+
+{0x8D, 0x61}, //EXP120, PLLx2 Mclk24
+{0x8E, 0xa8},
+
+{0x91, 0x03}, //EXP Fix 14.91 fps
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps, PLLx2 Mclk24
+{0x9d, 0x70},
+
+{0x9e, 0x01}, //EXP Unit, PLLx2 Mclk24
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x40},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, //33 //44
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f,	0x5c},
+{0x90,	0x5b},
+{0x91,	0x57},
+{0x92,	0x4f},
+{0x93,	0x43},
+{0x94,	0x3e},
+{0x95,	0x34},
+{0x96,	0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x8c}, //AE on 60hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+regs_short_t front_preview_camera_50hz_regs[] = {
+
+{0x03, 0x00}, //Sleep On
+{0x01, 0xf9},
+
+{0x0e, 0x03}, //Pll off
+
+{0x03, 0x20}, //page 20
+{0x18, 0x30}, //for Preview
+{0x10, 0x1c}, //AE off 50hz
+
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+{0x03, 0x00},
+{0x10, 0x19},
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x90},
+#else
+{0x11, 0x92},
+#endif
+
+{0x20, 0x00},
+{0x21, 0x02}, //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x42, 0x00}, //VBlank
+{0x43, 0x58}, //88
+
+//Page10
+{0x03, 0x10},
+{0x3f, 0x02},
+{0x60, 0x6b},
+
+//Page12
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+{0x90, 0x00},
+
+//only for Preview DPC 
+{0xd2, 0x17},
+{0xd5, 0x0f},
+{0xd7, 0xff},
+
+//Page13
+{0x03, 0x13},
+{0x80, 0x00},
+
+{0x03, 0x20},
+{0x10, 0x9c}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9}, //AWB ON
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL ON
+{0x0e, 0x73}, // x2
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00}, //Sleep Off
+{0x01, 0xf8},
+
+{0xff, 0x28}, //400ms
+
+};
+
+regs_short_t front_preview_camera_60hz_regs[] = {
+
+{0x03, 0x00}, //Sleep On
+{0x01, 0xf9},
+
+{0x0e, 0x03}, //Pll off
+
+{0x03, 0x20}, //page 20
+{0x18, 0x30}, //for Preview
+{0x10, 0x0c}, //AE off 60hz
+
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+{0x03, 0x00},
+{0x10, 0x19},
+
+#if 1 /* defined(CONFIG_MACH_P2_REV02) */
+{0x11, 0x90},
+#else
+{0x11, 0x92},
+#endif
+
+{0x20, 0x00},
+{0x21, 0x02}, //modify 20110929 0x04->0x02
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+{0x42, 0x00}, //VBlank
+{0x43, 0x44}, //68
+
+//Page10
+{0x03, 0x10},
+{0x3f, 0x02},
+{0x60, 0x6b},
+
+//Page12
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+{0x90, 0x00},
+
+//only for Preview DPC 
+{0xd2, 0x17},
+{0xd5, 0x0f},
+{0xd7, 0xff},
+
+//Page13
+{0x03, 0x13},
+{0x80, 0x00},
+
+{0x03, 0x20},
+{0x10, 0x8c}, //AE on 60hz
+
+{0x03, 0x22},
+{0x10, 0xe9}, //AWB ON
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL ON
+{0x0e, 0x73}, // x2
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00}, //Sleep Off
+{0x01, 0xf8},
+
+{0xff, 0x28}, //400ms
+
+};
+
+regs_short_t front_snapshot_normal_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+
+{0x0e, 0x03}, //PLL Off
+
+{0x03, 0x22}, //Page 22
+{0x10, 0x69}, //AWB Off
+
+{0x03, 0x00},
+{0x10, 0x08},
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x0a}, //modify 20110929 0x0c->0x0a
+{0x22, 0x00},
+{0x23, 0x0a}, //modify 20110929 0x14->0x0a
+
+//Page10
+{0x03, 0x10},
+{0x3f, 0x00},
+{0x60, 0x67},
+
+//Page12
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+{0x90, 0x5d},
+
+//only for Preview DPC Off
+{0xd2, 0x67},
+{0xd5, 0x02},
+{0xd7, 0x18},
+
+//Page13
+{0x03, 0x13},
+{0x80, 0xfd},
+
+//Page0
+{0x03, 0x00},
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL ON
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8}, //Sleep Off
+
+{0xff, 0x03},  //Increase from 30ms
+};
+
+regs_short_t front_ev_minus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0xd0},
+};
+
+regs_short_t front_ev_minus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0xc0},
+};
+
+regs_short_t front_ev_minus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0xb0},
+};
+
+regs_short_t front_ev_minus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0xa0},
+};
+
+regs_short_t front_ev_default_regs[] = {
+{0x03, 0x10},
+{0x40, 0x00},
+};
+
+regs_short_t front_ev_plus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0x20},
+};
+
+regs_short_t front_ev_plus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0x30},
+};
+
+regs_short_t front_ev_plus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0x40},
+};
+
+regs_short_t front_ev_plus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_wb_auto_regs[] = {
+{0x03, 0x22},
+{0x11, 0x2e},  	//awbctrl2
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+};
+
+regs_short_t front_wb_sunny_regs[] = {
+{0x03, 0x22},
+{0x11, 0x2c},
+{0x80, 0x52},
+{0x81, 0x20},
+{0x82, 0x27},
+{0x83, 0x58},
+{0x84, 0x4d},
+{0x85, 0x2c},
+{0x86, 0x22},
+};
+
+regs_short_t front_wb_cloudy_regs[] = {
+{0x03, 0x22},
+{0x11, 0x2c},
+{0x80, 0x71},//71 //R
+{0x81, 0x20},//1e //G //1b
+{0x82, 0x20},//1f //B 1c
+{0x83, 0x72},//72 // Rmax 6f
+{0x84, 0x6e},//70 70 // Rmin 68
+{0x85, 0x21},//20 // Bmax 1b
+{0x86, 0x1f},//1e // Bmin 16
+};
+
+regs_short_t front_wb_tungsten_regs[] = {
+{0x03, 0x22},
+{0x11, 0x2c},
+{0x80, 0x20},
+{0x81, 0x20},
+{0x82, 0x58},
+{0x83, 0x23},
+{0x84, 0x1f},
+{0x85, 0x58},
+{0x86, 0x52},
+};
+
+regs_short_t front_wb_fluorescent_regs[] = {
+{0x03, 0x22},
+{0x11, 0x2c},
+{0x80, 0x3d},
+{0x81, 0x20},
+{0x82, 0x4a},
+{0x83, 0x42},
+{0x84, 0x3c},
+{0x85, 0x51},
+{0x86, 0x47},
+};
+
+regs_short_t front_effect_normal_regs[] = {
+{0x03, 0x10},
+{0x11, 0x03},
+{0x12, 0x30},
+{0x44, 0x80},
+{0x45, 0x80},
+};
+
+regs_short_t front_effect_negative_regs[] = {
+{0x03, 0x10},
+{0x11, 0x03},
+{0x12, 0x38},
+{0x13, 0x08},
+{0x44, 0x80},
+{0x45, 0x80},
+};
+
+regs_short_t front_effect_sepia_regs[] = {
+{0x03, 0x10},
+{0x11, 0x03},
+{0x12, 0x33},
+{0x13, 0x08},
+{0x44, 0x70},
+{0x45, 0x98},
+};
+
+regs_short_t front_effect_mono_regs[] = {
+{0x03, 0x10},
+{0x11, 0x03},
+{0x12, 0x33},
+{0x13, 0x08},
+{0x44, 0x80},
+{0x45, 0x80},
+};
+
+regs_short_t front_fps_auto_regs[] = {
+};
+
+regs_short_t front_fps_7_50hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x0e}, //BLC_TIME_TH_ON
+{0x91, 0x0e}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x0e}, //DCDC_TIME_TH_ON
+{0xd5, 0x0e}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x06}, //EXP Max 07.14 fps
+{0x89, 0x68},
+{0x8a, 0xa0},
+
+{0x91, 0x06}, //EXP Fix 07.00 fps
+{0x92, 0x89},
+{0x93, 0xd4},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_10_50hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x09}, //BLC_TIME_TH_ON
+{0x91, 0x09}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x09}, //DCDC_TIME_TH_ON
+{0xd5, 0x09}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x04}, //EXP Max 11.11 fps
+{0x89, 0x1e},
+{0x8a, 0xb0},
+
+{0x91, 0x04}, //EXP Fix 10.00 fps
+{0x92, 0x93},
+{0x93, 0xe0},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_15_50hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x06}, //BLC_TIME_TH_ON
+{0x91, 0x06}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x06}, //DCDC_TIME_TH_ON
+{0xd5, 0x06}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x02}, //EXP Max 16.67 fps
+{0x89, 0xbf},
+{0x8a, 0x20},
+
+{0x91, 0x03}, //EXP Fix 14.91 fps
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_7_60hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x11}, //BLC_TIME_TH_ON
+{0x91, 0x11}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x11}, //DCDC_TIME_TH_ON
+{0xd5, 0x11}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x0C}, //AE off 60hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x06}, //EXP Max 7.06 fps
+{0x89, 0x7c},
+{0x8a, 0x28},
+
+{0x91, 0x06}, //EXP Fix 07.00 fps
+{0x92, 0x89},
+{0x93, 0xd4},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C}, //AE on 60hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_10_60hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x0b}, //BLC_TIME_TH_ON
+{0x91, 0x0b}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x0b}, //DCDC_TIME_TH_ON
+{0xd5, 0x0b}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x0C}, //AE off 60hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x04}, //EXP Max 10.91 fps
+{0x89, 0x32},
+{0x8a, 0x38},
+
+{0x91, 0x04}, //EXP Fix 10.00 fps
+{0x92, 0x93},
+{0x93, 0xe0},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C}, //AE on 60hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_15_60hz_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68},
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x08}, //BLC_TIME_TH_ON
+{0x91, 0x08}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x08}, //DCDC_TIME_TH_ON
+{0xd5, 0x08}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x0C}, //AE off 60hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x03}, //EXP Max 15.00 fps
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x91, 0x03}, //EXP Fix 14.91 fps
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps
+{0x9d, 0x70},
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C}, //AE on 60hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_vt_auto_regs[] = {
+};
+
+regs_short_t front_fps_vt_7_regs[] = {
+};
+
+regs_short_t front_fps_vt_10_regs[] = {
+};
+
+regs_short_t front_fps_vt_15_regs[] = {
+};
+
+regs_short_t front_pattern_on_regs[] =  {
+{0x03, 0x00},
+{0x50, 0x05},
+};
+
+regs_short_t front_pattern_off_regs[] =  {
+{0x03, 0x00},
+{0x50, 0x00},
+};
+
+
+#endif /* __SR200PC20_REGS_H */
diff --git a/drivers/media/video/sr200pc20_regs-p4w.h b/drivers/media/video/sr200pc20_regs-p4w.h
new file mode 100644
index 0000000..2c9503e
--- /dev/null
+++ b/drivers/media/video/sr200pc20_regs-p4w.h
@@ -0,0 +1,3703 @@
+/*
+ * Driver for SR200PC20 2M ISP from Samsung
+ * Latest version: 11/11/23
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: DongSeong Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __SR200PC20_REGS_H
+#define __SR200PC20_REGS_H
+
+#include <linux/types.h>
+
+/*
+ * sr200pc20 register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name: SR200PC20 Initial Setfile
+* PLL mode: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by: ZEROHOY
+* Date: 2011.03.07
+* History:
+*******************************************************/
+regs_short_t front_init_regs[] = {
+/////// Start Sleep ///////
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, /* PLLx2 */
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, /* AE off 50hz */
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, /* AWB off */
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x11}, /* Vsync Active High B:[3] */
+{0x11, 0x90},
+{0x12, 0x04}, /* Pclk Falling Edge B:[2] */
+
+{0x0b, 0xaa}, /* ESD Check Register */
+{0x0c, 0xaa}, /* ESD Check Register */
+{0x0d, 0xaa}, /* ESD Check Register */
+
+{0x20, 0x00},
+{0x21, 0x02},  /* modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a}, /* modify 20110929 0x14->0x0a */
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank_360
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x58}, /* Flick Stop 50hz */
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0c}, //BLC_TIME_TH_ON
+{0x91, 0x0c}, //BLC_TIME_TH_OFF 
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826 Ãß°¡
+{0x52, 0x01}, //0x03 --> 0x01 (by À±Ã¥ÀÓ´Ô, 20100513)
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0c}, //DCDC_TIME_TH_ON
+{0xd5, 0x0c}, //DCDC_TIME_TH_OFF 
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02}, //For Preview
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a}, //77
+{0x62, 0x73}, /*77*/
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00}, /* For Preview */
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+/* only for Preview DPC */
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+/* only for Preview DPC */
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+/* only for Preview DPC */
+{0xd7, 0xff},
+
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2 
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1 
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor 
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3 
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28}, /* 2d */
+{0x60, 0x24}, /* 26 */
+{0x70, 0x28}, /* 2d */
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/* GGMA Default */
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x55},
+{0x35, 0x72},
+{0x36, 0x8c},
+{0x37, 0x9d},
+{0x38, 0xad},
+{0x39, 0xbb},
+{0x3a, 0xc8},
+{0x3b, 0xd2},
+{0x3c, 0xdb},
+{0x3d, 0xe3},
+{0x3e, 0xea},
+{0x3f, 0xf1},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+/* RGMA */
+{0x50, 0x00},
+{0x51, 0x09},
+{0x52, 0x1f},
+{0x53, 0x37},
+{0x54, 0x5b},
+{0x55, 0x78},
+{0x56, 0x91},
+{0x57, 0xa4},
+{0x58, 0xb5},
+{0x59, 0xc1},
+{0x5a, 0xcb},
+{0x5b, 0xd5},
+{0x5c, 0xde},
+{0x5d, 0xe6},
+{0x5e, 0xed},
+{0x5f, 0xf1},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+/* BGMA */
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0xff},
+{0x2b, 0xf4},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x72}, /* 6c */
+{0x71, 0x84}, /* 84(+10) */
+
+{0x76, 0x43},
+{0x77, 0x04},
+{0x78, 0x24}, //24
+{0x79, 0x49}, /* Y Target 70 => 25, 72 => 26 */
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps 
+{0x84, 0x5f},
+{0x85, 0x90},
+
+{0x86, 0x01}, //EXPMin 6000.00 fps
+{0x87, 0xf4},
+
+{0x88, 0x05}, //EXP Max 8.33 fps 
+{0x89, 0x7e},
+{0x8a, 0x40},
+
+{0x8B, 0x75}, //EXP100, PLLx2 Mclk24 
+{0x8C, 0x30},
+
+{0x8D, 0x61}, //EXP120, PLLx2 Mclk24 
+{0x8E, 0xa8},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps, PLLx2 Mclk24 
+{0x9d, 0x70},
+
+{0x9e, 0x01}, //EXP Unit, PLLx2 Mclk24 
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x40},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51},
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x9c}, /* AE on 50hz */
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x32}, /* NEED Delay 500ms */
+};
+
+
+//==========================================================
+/* CAMERA INITIAL for Self Recording 24 Fixed Frame */
+//==========================================================
+regs_short_t front_init_recording_regs[] = {
+
+{0x01, 0xf9}, //sleep on
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0xf8}, //sleep off
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0xf9}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+
+{0x01, 0xfb},
+{0x01, 0xf9},
+
+/////// PAGE 20 ///////
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, //AE off 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+
+//Initial Start
+/////// PAGE 0 START ///////
+{0x03, 0x00},
+{0x10, 0x13},  /* vsync active high, org {0x10, 0x19},*/
+
+/* P4W 0 rotation */
+{0x11, 0x94},
+
+{0x12, 0x04}, /* catch timing, org {0x12, 0x00}, */
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01}, //Hblank 352
+{0x41, 0x60},
+{0x42, 0x00}, //Vblank 20
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x04}, //BLC_TIME_TH_ON
+{0x91, 0x04}, //BLC_TIME_TH_OFF
+{0x92, 0xb0}, //BLC_AG_TH_ON
+{0x93, 0xa8}, //BLC_AG_TH_OFF
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/////// PAGE 0 END ///////
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG//
+{0x19, 0x00},
+{0x1a, 0x39}, //Double_AG/ 38 ->39
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x51, 0x03}, //20110826
+{0x52, 0x01}, //0x03 --> 0x01
+{0x53, 0xc1}, //20110818 Ãß°¡
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x04}, //DCDC_TIME_TH_ON
+{0xd5, 0x04}, //DCDC_TIME_TH_OFF
+{0xd6, 0xb0}, //DCDC_AG_TH_ON
+{0xd7, 0xa8}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/////// PAGE 2 END ///////
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+/////// PAGE 3 END ///////
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00}, //Setting For Camcorder 24
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x67}, //Setting For Camcorder 24
+{0x61, 0x7a}, //77
+{0x62, 0x79}, //77
+{0x63, 0x50}, // Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x7a}, //7e
+{0x6d, 0x80}, //8e
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+//Dark1 D-LPF th
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+//Dark2 D-LPF th
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+//Dark3 D-LPF th
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/////// PAGE 11 END ///////
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x0f}, //Setting For Camcorder 24
+{0x21, 0x0f}, //Setting For Camcorder 24
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+//Dark2 th
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+//Dark3 th
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d}, //Setting For Camcorder 24
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+//Dont Touch register
+{0xc5, 0x30},//55->48
+{0xc6, 0x2a},//48->40
+/////// PAGE 12 END ///////
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+//Dark2 Edge
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+//Dark3 Edge
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+//2DY
+{0x80, 0xfd}, //Setting For Camcorder 24
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/////// PAGE 13 END ///////
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x80}, //X
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x3e},
+{0x50, 0x28},
+{0x60, 0x24},
+{0x70, 0x28},
+/////// PAGE 14 END ///////
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x46}, //CMCOFSGH
+{0x15, 0x36}, //CMCOFSGM
+{0x16, 0x26}, //CMCOFSGL
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+//CMC POFS
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/////// PAGE 15 END ///////
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x1c},
+{0x73, 0x32},
+{0x74, 0x54},
+{0x75, 0x70},
+{0x76, 0x87},
+{0x77, 0x9a},
+{0x78, 0xaa},
+{0x79, 0xb9},
+{0x7a, 0xc4},
+{0x7b, 0xcf},
+{0x7c, 0xd8},
+{0x7d, 0xe0},
+{0x7e, 0xe9},
+{0x7f, 0xf0},
+{0x80, 0xf7},
+{0x81, 0xfc},
+{0x82, 0xff},
+/////// PAGE 16 END ///////
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+/////// PAGE 17 END ///////
+
+/////// PAGE 20 START ///////
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d}, //20100305 ad->0d
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},
+{0x79, 0x49},
+{0x7a, 0x23},
+{0x7b, 0x22},
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps
+{0x84, 0x5f},
+{0x85, 0x6c},
+
+{0x86, 0x01}, //EXPMin 10204.08 fps
+{0x87, 0x26},
+
+{0x88, 0x01}, //EXP Max 25.00 fps
+{0x89, 0xd4},
+{0x8a, 0x90},
+
+{0x8B, 0x75}, //EXP100
+{0x8C, 0x24},
+
+{0x8D, 0x61}, //EXP120
+{0x8E, 0x9e},
+
+{0x91, 0x01}, //EXP Fix 23.93 fps
+{0x92, 0xe9},
+{0x93, 0xcf},
+
+{0x98, 0x9d}, //9d
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x0e}, //EXP Limit 784.93 fps
+{0x9d, 0xee},
+
+{0x9e, 0x01}, //EXP Unit
+{0x9f, 0x26},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xb8},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x40},
+{0xc9, 0x20},
+/////// PAGE 20 END ///////
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32}, /* 33, 44 */
+{0x42, 0x22}, //22 //43
+{0x43, 0xf0}, //f6
+{0x44, 0x44}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36}, //3a
+
+{0x83, 0x5e}, //5e
+{0x84, 0x21}, //24
+{0x85, 0x51}, //54
+{0x86, 0x20}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x29}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39},
+{0x8d, 0x34},
+{0x8e, 0x29}, //2c
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xb0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+/////// PAGE 22 END ///////
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x9c}, //AE on 50hz
+
+/////// PAGE 22 ///////
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/////// PAGE 0 ///////
+{0x03, 0x00},
+{0x0e, 0x03},
+{0x0e, 0x73},
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+//==========================================================
+/* CAMERA INITIAL for VT Preview 15 Fixed Frame (VGA SETTING) */
+//==========================================================
+regs_short_t front_init_vt_regs[] = {
+	/////// Start Sleep ///////
+	{0x01, 0xf9}, //sleep on
+	{0x08, 0x0f}, //Hi-Z on
+	{0x01, 0xf8}, //sleep off
+
+	{0x03, 0x00}, //Dummy 750us
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+
+	{0x0e, 0x03}, //PLL On
+	{0x0e, 0x73}, //x2
+
+	{0x03, 0x00}, //Dummy 750us
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+
+	{0x0e, 0x00}, //PLL off
+	{0x01, 0xf9}, //sleep on
+	{0x08, 0x00}, //Hi-Z off
+
+	{0x01, 0xfb},
+	{0x01, 0xf9},
+
+	/////// PAGE 20 ///////
+	{0x03, 0x20}, //page 20
+	{0x10, 0x1c}, /* AE off 50hz */
+
+	/////// PAGE 22 ///////
+	{0x03, 0x22}, //page 22
+	{0x10, 0x69}, //awb off
+
+
+	//Initial Start
+	/////// PAGE 0 START ///////
+	{0x03, 0x00},
+	{0x10, 0x11},  /* vsync active high, org {0x10, 0x19},*/
+
+	/* P4W 0 rotation */
+	{0x11, 0x94},
+
+	{0x12, 0x04}, /* catch timing, org {0x12, 0x00}, */
+
+	{0x0b, 0xaa},
+	{0x0c, 0xaa},
+	{0x0d, 0xaa},
+
+	{0x20, 0x00},
+	{0x21, 0x02}, /* modify 20110929 0x04->0x02 */
+	{0x22, 0x00},
+	{0x23, 0x0a}, /* modify 20110929 0x14->0x0a */
+
+	{0x24, 0x04},
+	{0x25, 0xb0},
+	{0x26, 0x06},
+	{0x27, 0x40},
+
+	{0x28, 0x0c},
+	{0x29, 0x04},
+	{0x2a, 0x02},
+	{0x2b, 0x04},
+	{0x2c, 0x06},
+	{0x2d, 0x02},
+
+	{0x40, 0x01}, //Hblank_360
+	{0x41, 0x68},
+	{0x42, 0x00},
+	{0x43, 0x14},
+
+	{0x45, 0x04},
+	{0x46, 0x18},
+	{0x47, 0xd8},
+
+	//BLC
+	{0x80, 0x2e},
+	{0x81, 0x7e},
+	{0x82, 0x90},
+	{0x83, 0x00},
+	{0x84, 0x0c},
+	{0x85, 0x00},
+	{0x90, 0x06}, /* BLC_TIME_TH_ON */
+	{0x91, 0x06}, /* BLC_TIME_TH_OFF */
+	{0x92, 0xd8}, /* BLC_AG_TH_ON */
+	{0x93, 0xd0}, /* BLC_AG_TH_OFF */
+	{0x94, 0xff},
+	{0x95, 0xff},
+	{0x96, 0xdc},
+	{0x97, 0xfe},
+	{0x98, 0x38},
+
+	//Dark BLC
+	{0xa0, 0x00},
+	{0xa2, 0x00},
+	{0xa4, 0x00},
+	{0xa6, 0x00},
+
+	//Normal BLC
+	{0xa8, 0x43},
+	{0xaa, 0x43},
+	{0xac, 0x43},
+	{0xae, 0x43},
+
+	//OutDoor  BLC
+	{0x99, 0x43},
+	{0x9a, 0x43},
+	{0x9b, 0x43},
+	{0x9c, 0x43},
+	/////// PAGE 0 END ///////
+
+	/////// PAGE 2 START ///////
+	{0x03, 0x02},
+	{0x12, 0x03},
+	{0x13, 0x03},
+	{0x16, 0x00},
+	{0x17, 0x8C},
+	{0x18, 0x4c}, /* Double_AG*/
+	{0x19, 0x00},
+	{0x1a, 0x39}, /* Double_AG/ 38 ->39*/
+	{0x1c, 0x09},
+	{0x1d, 0x40},
+	{0x1e, 0x30},
+	{0x1f, 0x10},
+
+	{0x20, 0x77},
+	{0x21, 0xde},
+	{0x22, 0xa7},
+	{0x23, 0x30}, /* CLAMP */
+	{0x27, 0x3c},
+	{0x2b, 0x80},
+	{0x2e, 0x00},
+	{0x2f, 0x00},
+	{0x30, 0x05}, /*For Hi-253 never no change 0x05 */
+
+	{0x50, 0x20},
+	{0x51, 0x03}, /* 20110826 */
+	{0x52, 0x01}, /* 0x03 --> 0x01 */
+	{0x53, 0xc1}, /* 20110818 added */
+	{0x55, 0x1c},
+	{0x56, 0x11},
+	{0x5d, 0xa2},
+	{0x5e, 0x5a},
+
+	{0x60, 0x87},
+	{0x61, 0x99},
+	{0x62, 0x88},
+	{0x63, 0x97},
+	{0x64, 0x88},
+	{0x65, 0x97},
+
+	{0x67, 0x0c},
+	{0x68, 0x0c},
+	{0x69, 0x0c},
+
+	{0x72, 0x89},
+	{0x73, 0x96},
+	{0x74, 0x89},
+	{0x75, 0x96},
+	{0x76, 0x89},
+	{0x77, 0x96},
+
+	{0x7c, 0x85},
+	{0x7d, 0xaf},
+	{0x80, 0x01},
+	{0x81, 0x7f},
+	{0x82, 0x13},
+	{0x83, 0x24},
+	{0x84, 0x7d},
+	{0x85, 0x81},
+	{0x86, 0x7d},
+	{0x87, 0x81},
+
+	{0x92, 0x48},
+	{0x93, 0x54},
+	{0x94, 0x7d},
+	{0x95, 0x81},
+	{0x96, 0x7d},
+	{0x97, 0x81},
+
+	{0xa0, 0x02},
+	{0xa1, 0x7b},
+	{0xa2, 0x02},
+	{0xa3, 0x7b},
+	{0xa4, 0x7b},
+	{0xa5, 0x02},
+	{0xa6, 0x7b},
+	{0xa7, 0x02},
+
+	{0xa8, 0x85},
+	{0xa9, 0x8c},
+	{0xaa, 0x85},
+	{0xab, 0x8c},
+	{0xac, 0x10},
+	{0xad, 0x16},
+	{0xae, 0x10},
+	{0xaf, 0x16},
+
+	{0xb0, 0x99},
+	{0xb1, 0xa3},
+	{0xb2, 0xa4},
+	{0xb3, 0xae},
+	{0xb4, 0x9b},
+	{0xb5, 0xa2},
+	{0xb6, 0xa6},
+	{0xb7, 0xac},
+	{0xb8, 0x9b},
+	{0xb9, 0x9f},
+	{0xba, 0xa6},
+	{0xbb, 0xaa},
+	{0xbc, 0x9b},
+	{0xbd, 0x9f},
+	{0xbe, 0xa6},
+	{0xbf, 0xaa},
+
+	{0xc4, 0x2c},
+	{0xc5, 0x43},
+	{0xc6, 0x63},
+	{0xc7, 0x79},
+
+	{0xc8, 0x2d},
+	{0xc9, 0x42},
+	{0xca, 0x2d},
+	{0xcb, 0x42},
+	{0xcc, 0x64},
+	{0xcd, 0x78},
+	{0xce, 0x64},
+	{0xcf, 0x78},
+	{0xd0, 0x0a},
+	{0xd1, 0x09},
+	{0xd4, 0x06}, /* DCDC_TIME_TH_ON */
+	{0xd5, 0x06}, /* DCDC_TIME_TH_OFF */
+	{0xd6, 0xd8}, /* DCDC_AG_TH_ON */
+	{0xd7, 0xd0}, /* DCDC_AG_TH_OFF */
+	{0xe0, 0xc4},
+	{0xe1, 0xc4},
+	{0xe2, 0xc4},
+	{0xe3, 0xc4},
+	{0xe4, 0x00},
+	{0xe8, 0x80},
+	{0xe9, 0x40},
+	{0xea, 0x7f},
+
+	{0xf0, 0x01},
+	{0xf1, 0x01},
+	{0xf2, 0x01},
+	{0xf3, 0x01},
+	{0xf4, 0x01},
+
+	/////// PAGE 2 END ///////
+
+	/////// PAGE 3 ///////
+	{0x03, 0x03},
+	{0x10, 0x10},
+	/////// PAGE 3 END ///////
+
+	/////// PAGE 10 START ///////
+	{0x03, 0x10},
+	{0x10, 0x03}, // CrYCbY // For Demoset 0x03
+	{0x12, 0x30},
+	{0x20, 0x00},
+	{0x30, 0x00},
+	{0x31, 0x00},
+	{0x32, 0x00},
+	{0x33, 0x00},
+
+	{0x34, 0x30},
+	{0x35, 0x00},
+	{0x36, 0x00},
+	{0x38, 0x00},
+	{0x3e, 0x58},
+	{0x3f, 0x02}, //For Preview
+
+	{0x40, 0x80},
+	{0x41, 0x00},
+
+	{0x60, 0x6b},
+	{0x61, 0x7a}, //77
+	{0x62, 0x79}, //77
+	{0x63, 0x50}, // Double_AG 50->30
+	{0x64, 0x41},
+
+	{0x66, 0x42},
+	{0x67, 0x20},
+
+	{0x6a, 0x80}, //8a
+	{0x6b, 0x84}, //74
+	{0x6c, 0x7a}, //7e
+	{0x6d, 0x80}, //8e
+
+	/////// PAGE 11 START ///////
+	{0x03, 0x11},
+	{0x10, 0x7f},
+	{0x11, 0x40},
+	{0x12, 0x0a}, // Blue Max-Filter Delete
+	{0x13, 0xbb},
+
+	{0x26, 0x31}, // Double_AG 31->20
+	{0x27, 0x34}, // Double_AG 34->22
+	{0x28, 0x0f},
+	{0x29, 0x10},
+	{0x2b, 0x30},
+	{0x2c, 0x32},
+
+	//Out2 D-LPF th
+	{0x30, 0x70},
+	{0x31, 0x10},
+	{0x32, 0x58},
+	{0x33, 0x09},
+	{0x34, 0x06},
+	{0x35, 0x03},
+
+	//Out1 D-LPF th
+	{0x36, 0x70},
+	{0x37, 0x18},
+	{0x38, 0x58},
+	{0x39, 0x09},
+	{0x3a, 0x06},
+	{0x3b, 0x03},
+
+	//Indoor D-LPF th
+	{0x3c, 0x80},
+	{0x3d, 0x18},
+	{0x3e, 0x80},
+	{0x3f, 0x0c},
+	{0x40, 0x09},
+	{0x41, 0x06},
+
+	/*Dark1 D-LPF th */
+	{0x42, 0x80},
+	{0x43, 0x18},
+	{0x44, 0x80},
+	{0x45, 0x12},
+	{0x46, 0x10},
+	{0x47, 0x10},
+
+	/*Dark2 D-LPF th */
+	{0x48, 0x90},
+	{0x49, 0x40},
+	{0x4a, 0x80},
+	{0x4b, 0x13},
+	{0x4c, 0x10},
+	{0x4d, 0x11},
+
+	/*Dark3 D-LPF th */
+	{0x4e, 0x80},
+	{0x4f, 0x30},
+	{0x50, 0x80},
+	{0x51, 0x13},
+	{0x52, 0x10},
+	{0x53, 0x13},
+
+	{0x54, 0x11},
+	{0x55, 0x17},
+	{0x56, 0x20},
+	{0x57, 0x01},
+	{0x58, 0x00},
+	{0x59, 0x00},
+
+	{0x5a, 0x18},
+	{0x5b, 0x00},
+	{0x5c, 0x00},
+
+	{0x60, 0x3f},
+	{0x62, 0x60},
+	{0x70, 0x06},
+	/////// PAGE 11 END ///////
+
+	/////// PAGE 12 START ///////
+	{0x03, 0x12},
+	{0x20, 0x00},
+	{0x21, 0x00},
+
+	{0x25, 0x00}, //0x30
+
+	{0x28, 0x00},
+	{0x29, 0x00},
+	{0x2a, 0x00},
+
+	{0x30, 0x50},
+	{0x31, 0x18},
+	{0x32, 0x32},
+	{0x33, 0x40},
+	{0x34, 0x50},
+	{0x35, 0x70},
+	{0x36, 0xa0},
+
+	//Out2 th
+	{0x40, 0xa0},
+	{0x41, 0x40},
+	{0x42, 0xa0},
+	{0x43, 0x90},
+	{0x44, 0x90},
+	{0x45, 0x80},
+
+	//Out1 th
+	{0x46, 0xb0},
+	{0x47, 0x55},
+	{0x48, 0xa0},
+	{0x49, 0x90},
+	{0x4a, 0x90},
+	{0x4b, 0x80},
+
+	//Indoor th
+	{0x4c, 0xb0},
+	{0x4d, 0x40},
+	{0x4e, 0x90},
+	{0x4f, 0x90},
+	{0x50, 0xa0},
+	{0x51, 0x80},
+
+	//Dark1 th
+	{0x52, 0xb0},
+	{0x53, 0x60},
+	{0x54, 0xc0},
+	{0x55, 0xc0},
+	{0x56, 0xc0},
+	{0x57, 0x80},
+
+	//Dark2 th
+	{0x58, 0x90},
+	{0x59, 0x40},
+	{0x5a, 0xd0},
+	{0x5b, 0xd0},
+	{0x5c, 0xe0},
+	{0x5d, 0x80},
+
+	//Dark3 th
+	{0x5e, 0x88},
+	{0x5f, 0x40},
+	{0x60, 0xe0},
+	{0x61, 0xe0},
+	{0x62, 0xe0},
+	{0x63, 0x80},
+
+	{0x70, 0x15},
+	{0x71, 0x01}, //Don't Touch register
+
+	{0x72, 0x18},
+	{0x73, 0x01}, //Don't Touch register
+
+	{0x74, 0x25},
+	{0x75, 0x15},
+
+	{0x80, 0x20},
+	{0x81, 0x40},
+	{0x82, 0x65},
+	{0x85, 0x1a},
+	{0x88, 0x00},
+	{0x89, 0x00},
+	{0x90, 0x00}, /* For Preview */
+
+	//Dont Touch register
+	{0xD0, 0x0c},
+	{0xD1, 0x80},
+
+	/* only for Preview DPC */
+	{0xD2, 0x17},
+
+	{0xD3, 0x00},
+	{0xD4, 0x00},
+
+	/* only for Preview DPC */
+	{0xd5, 0x0f},
+
+	{0xD6, 0xff},
+
+	/* only for Preview DPC */
+	{0xd7, 0xff},
+
+	//End
+	{0x3b, 0x06},
+	{0x3c, 0x06},
+
+	/* Dont Touch register */
+	{0xc5, 0x30},/* 55->48 */
+	{0xc6, 0x2a},/* 48->40 */
+	/////// PAGE 12 END ///////
+
+	/////// PAGE 13 START ///////
+	{0x03, 0x13},
+	//Edge
+	{0x10, 0xcb},
+	{0x11, 0x7b},
+	{0x12, 0x07},
+	{0x14, 0x00},
+
+	{0x20, 0x15},
+	{0x21, 0x13},
+	{0x22, 0x33},
+	{0x23, 0x05},
+	{0x24, 0x09},
+
+	{0x25, 0x0a},
+
+	{0x26, 0x18},
+	{0x27, 0x30},
+	{0x29, 0x12},
+	{0x2a, 0x50},
+
+	//Low clip th
+	{0x2b, 0x02},
+	{0x2c, 0x02},
+	{0x25, 0x06},
+	{0x2d, 0x0c},
+	{0x2e, 0x12},
+	{0x2f, 0x12},
+
+	//Out2 Edge
+	{0x50, 0x10},
+	{0x51, 0x14},
+	{0x52, 0x12},
+	{0x53, 0x0c},
+	{0x54, 0x0f},
+	{0x55, 0x0c},
+
+	//Out1 Edge
+	{0x56, 0x10},
+	{0x57, 0x13},
+	{0x58, 0x12},
+	{0x59, 0x0c},
+	{0x5a, 0x0f},
+	{0x5b, 0x0c},
+
+	//Indoor Edge
+	{0x5c, 0x0a},
+	{0x5d, 0x0b},
+	{0x5e, 0x0a},
+	{0x5f, 0x08},
+	{0x60, 0x09},
+	{0x61, 0x08},
+
+	//Dark1 Edge
+	{0x62, 0x08},
+	{0x63, 0x08},
+	{0x64, 0x08},
+	{0x65, 0x06},
+	{0x66, 0x06},
+	{0x67, 0x06},
+
+	//Dark2 Edge
+	{0x68, 0x07},
+	{0x69, 0x07},
+	{0x6a, 0x07},
+	{0x6b, 0x05},
+	{0x6c, 0x05},
+	{0x6d, 0x05},
+
+	//Dark3 Edge
+	{0x6e, 0x07},
+	{0x6f, 0x07},
+	{0x70, 0x07},
+	{0x71, 0x05},
+	{0x72, 0x05},
+	{0x73, 0x05},
+
+	//2DY
+	{0x80, 0x00},
+	{0x81, 0x1f},
+	{0x82, 0x05},
+	{0x83, 0x31},
+
+	{0x90, 0x05},
+	{0x91, 0x05},
+	{0x92, 0x33},
+	{0x93, 0x30},
+	{0x94, 0x03},
+	{0x95, 0x14},
+	{0x97, 0x20},
+	{0x99, 0x20},
+
+	{0xa0, 0x01},
+	{0xa1, 0x02},
+	{0xa2, 0x01},
+	{0xa3, 0x02},
+	{0xa4, 0x05},
+	{0xa5, 0x05},
+	{0xa6, 0x07},
+	{0xa7, 0x08},
+	{0xa8, 0x07},
+	{0xa9, 0x08},
+	{0xaa, 0x07},
+	{0xab, 0x08},
+
+	//Out2 
+	{0xb0, 0x22},
+	{0xb1, 0x2a},
+	{0xb2, 0x28},
+	{0xb3, 0x22},
+	{0xb4, 0x2a},
+	{0xb5, 0x28},
+
+	//Out1 
+	{0xb6, 0x22},
+	{0xb7, 0x2a},
+	{0xb8, 0x28},
+	{0xb9, 0x22},
+	{0xba, 0x2a},
+	{0xbb, 0x28},
+
+	//Indoor 
+	{0xbc, 0x25},
+	{0xbd, 0x2a},
+	{0xbe, 0x27},
+	{0xbf, 0x25},
+	{0xc0, 0x2a},
+	{0xc1, 0x27},
+
+	//Dark1
+	{0xc2, 0x1e},
+	{0xc3, 0x24},
+	{0xc4, 0x20},
+	{0xc5, 0x1e},
+	{0xc6, 0x24},
+	{0xc7, 0x20},
+
+	//Dark2
+	{0xc8, 0x18},
+	{0xc9, 0x20},
+	{0xca, 0x1e},
+	{0xcb, 0x18},
+	{0xcc, 0x20},
+	{0xcd, 0x1e},
+
+	//Dark3 
+	{0xce, 0x18},
+	{0xcf, 0x20},
+	{0xd0, 0x1e},
+	{0xd1, 0x18},
+	{0xd2, 0x20},
+	{0xd3, 0x1e},
+	/////// PAGE 13 END ///////
+
+	/////// PAGE 14 START ///////
+	{0x03, 0x14},
+	{0x10, 0x11},
+
+	{0x14, 0x80}, // GX
+	{0x15, 0x80}, // GY
+	{0x16, 0x80}, // RX
+	{0x17, 0x80}, // RY
+	{0x18, 0x80}, // BX
+	{0x19, 0x80}, // BY
+
+	{0x20, 0x80}, //X
+	{0x21, 0x80}, //Y
+
+	{0x22, 0x80},
+	{0x23, 0x80},
+	{0x24, 0x80},
+
+	{0x30, 0xc8},
+	{0x31, 0x2b},
+	{0x32, 0x00},
+	{0x33, 0x00},
+	{0x34, 0x90},
+
+	{0x40, 0x3e},
+	{0x50, 0x28}, /*2d */
+	{0x60, 0x24}, /*26 */
+	{0x70, 0x28}, /*2d */
+	/////// PAGE 14 END ///////
+
+	/////// PAGE 15 START ///////
+	{0x03, 0x15},
+	{0x10, 0x0f},
+
+	//Rstep H 16
+	//Rstep L 14
+	{0x14, 0x46}, //CMCOFSGH
+	{0x15, 0x36}, //CMCOFSGM
+	{0x16, 0x26}, //CMCOFSGL
+	{0x17, 0x2f}, //CMC SIGN
+
+	//CMC
+	{0x30, 0x8f},
+	{0x31, 0x59},
+	{0x32, 0x0a},
+	{0x33, 0x15},
+	{0x34, 0x5b},
+	{0x35, 0x06},
+	{0x36, 0x07},
+	{0x37, 0x40},
+	{0x38, 0x87}, //86
+
+	//CMC OFS
+	{0x40, 0x94},
+	{0x41, 0x20},
+	{0x42, 0x89},
+	{0x43, 0x84},
+	{0x44, 0x03},
+	{0x45, 0x01},
+	{0x46, 0x88},
+	{0x47, 0x9c},
+	{0x48, 0x28},
+
+	//CMC POFS
+	{0x50, 0x02},
+	{0x51, 0x82},
+	{0x52, 0x00},
+	{0x53, 0x07},
+	{0x54, 0x11},
+	{0x55, 0x98},
+	{0x56, 0x00},
+	{0x57, 0x0b},
+	{0x58, 0x8b},
+
+	{0x80, 0x03},
+	{0x85, 0x40},
+	{0x87, 0x02},
+	{0x88, 0x00},
+	{0x89, 0x00},
+	{0x8a, 0x00},
+	/////// PAGE 15 END ///////
+
+	/////// PAGE 16 START ///////
+	{0x03, 0x16},
+	{0x10, 0x31},
+	{0x18, 0x5e},// Double_AG 5e->37
+	{0x19, 0x5d},// Double_AG 5e->36
+	{0x1a, 0x0e},
+	{0x1b, 0x01},
+	{0x1c, 0xdc},
+	{0x1d, 0xfe},
+
+	//GMA Default
+	{0x30, 0x00},
+	{0x31, 0x0a},
+	{0x32, 0x1f},
+	{0x33, 0x33},
+	{0x34, 0x53},
+	{0x35, 0x6c},
+	{0x36, 0x81},
+	{0x37, 0x94},
+	{0x38, 0xa4},
+	{0x39, 0xb3},
+	{0x3a, 0xc0},
+	{0x3b, 0xcb},
+	{0x3c, 0xd5},
+	{0x3d, 0xde},
+	{0x3e, 0xe6},
+	{0x3f, 0xee},
+	{0x40, 0xf5},
+	{0x41, 0xfc},
+	{0x42, 0xff},
+
+	{0x50, 0x00},
+	{0x51, 0x08},
+	{0x52, 0x1e},
+	{0x53, 0x36},
+	{0x54, 0x5a},
+	{0x55, 0x75},
+	{0x56, 0x8d},
+	{0x57, 0xa1},
+	{0x58, 0xb2},
+	{0x59, 0xbe},
+	{0x5a, 0xc9},
+	{0x5b, 0xd2},
+	{0x5c, 0xdb},
+	{0x5d, 0xe3},
+	{0x5e, 0xeb},
+	{0x5f, 0xf0},
+	{0x60, 0xf5},
+	{0x61, 0xf7},
+	{0x62, 0xf8},
+
+	{0x70, 0x00},
+	{0x71, 0x08},
+	{0x72, 0x17},
+	{0x73, 0x2f},
+	{0x74, 0x53},
+	{0x75, 0x6c},
+	{0x76, 0x81},
+	{0x77, 0x94},
+	{0x78, 0xa4},
+	{0x79, 0xb3},
+	{0x7a, 0xc0},
+	{0x7b, 0xcb},
+	{0x7c, 0xd5},
+	{0x7d, 0xde},
+	{0x7e, 0xe6},
+	{0x7f, 0xee},
+	{0x80, 0xf4},
+	{0x81, 0xfa},
+	{0x82, 0xff},
+	/////// PAGE 16 END ///////
+
+	/////// PAGE 17 START ///////
+	{0x03, 0x17},
+	{0x10, 0xf7},
+	/////// PAGE 17 END ///////
+
+	/////// PAGE 20 START ///////
+	{0x03, 0x20},
+	{0x11, 0x1c},
+	{0x18, 0x30},
+	{0x1a, 0x08},
+	{0x20, 0x05},
+	{0x21, 0x30},
+	{0x22, 0x10},
+	{0x23, 0x00},
+	{0x24, 0x00},
+
+	{0x28, 0xef},
+	{0x29, 0x0d}, //20100305 ad->0d
+	{0x2a, 0x03},
+	{0x2b, 0xf5},
+
+	{0x2c, 0xc2},
+	{0x2d, 0xff},
+	{0x2e, 0x33},
+	{0x30, 0xf8},
+	{0x32, 0x03},
+	{0x33, 0x2e},
+	{0x34, 0x30},
+	{0x35, 0xd4},
+	{0x36, 0xfe},
+	{0x37, 0x32},
+	{0x38, 0x04},
+	{0x3a, 0xde},
+	{0x3c, 0xde},
+
+	{0x50, 0x45},
+	{0x51, 0x88},
+
+	{0x56, 0x03},
+	{0x57, 0xf7},
+	{0x58, 0x14},
+	{0x59, 0x88},
+	{0x5a, 0x04},
+
+	{0x60, 0xaa},
+	{0x61, 0xaa},
+	{0x62, 0xaa},
+	{0x63, 0xaa},
+	{0x64, 0xaa},
+	{0x65, 0xaa},
+	{0x66, 0xab},
+	{0x67, 0xEa},
+	{0x68, 0xab},
+	{0x69, 0xEa},
+	{0x6a, 0xaa},
+	{0x6b, 0xaa},
+	{0x6c, 0xaa},
+	{0x6d, 0xaa},
+	{0x6e, 0xaa},
+	{0x6f, 0xaa},
+
+	{0x70, 0x70}, /* 6c */
+	{0x71, 0x82}, //82(+8)
+
+	{0x76, 0x43},
+	{0x77, 0x02},
+	{0x78, 0x24}, /* 24 */
+	{0x79, 0x48}, /* Y Target 70 => 25, 72 => 26 */
+	{0x7a, 0x23}, /* 23 */
+	{0x7b, 0x22}, /* 22 */
+	{0x7d, 0x23},
+
+	{0x83, 0x01}, /* EXP Normal 33.33 fps */
+	{0x84, 0x5f},
+	{0x85, 0x90},
+
+	{0x86, 0x01}, //EXPMin 6000.00 fps
+	{0x87, 0xf4},
+
+	{0x88, 0x02}, /* EXP Max 16.67 fps */
+	{0x89, 0xbf},
+	{0x8a, 0x20},
+
+	{0x8B, 0x75}, /* EXP100, PLLx2 Mclk24 */
+	{0x8C, 0x30},
+
+	{0x8D, 0x61}, /* EXP120, PLLx2 Mclk24 */
+	{0x8E, 0xa8},
+
+	{0x91, 0x03}, /* EXP Fix 14.91 fps */
+	{0x92, 0x12},
+	{0x93, 0x22},
+
+	{0x98, 0x9d}, //9d
+	{0x99, 0x45},
+	{0x9a, 0x0d},
+	{0x9b, 0xde},
+
+	{0x9c, 0x17}, /* EXP Limit 500.00 fps, PLLx2 Mclk24 */
+	{0x9d, 0x70},
+
+	{0x9e, 0x01}, /*  EXP Unit, PLLx2 Mclk24 */
+	{0x9f, 0xf4},
+
+	{0xb0, 0x18},
+	{0xb1, 0x14},
+	{0xb2, 0xe0},
+	{0xb3, 0x18},
+	{0xb4, 0x1a},
+	{0xb5, 0x44},
+	{0xb6, 0x2f},
+	{0xb7, 0x28},
+	{0xb8, 0x25},
+	{0xb9, 0x22},
+	{0xba, 0x21},
+	{0xbb, 0x20},
+	{0xbc, 0x32},
+	{0xbd, 0x32},
+
+	{0xc0, 0x10},
+	{0xc1, 0x2b},
+	{0xc2, 0x2b},
+	{0xc3, 0x2b},
+	{0xc4, 0x08},
+
+	{0xc8, 0x40},
+	{0xc9, 0x40},
+	/////// PAGE 20 END ///////
+
+	/////// PAGE 22 START ///////
+	{0x03, 0x22},
+	{0x10, 0xfd},
+	{0x11, 0x2e},
+	{0x19, 0x01}, // Low On //
+	{0x20, 0x10},
+	{0x21, 0x80},
+	{0x24, 0x01},
+	//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+	{0x30, 0x80},
+	{0x31, 0x80},
+	{0x38, 0x11},
+	{0x39, 0x34},
+	{0x40, 0xf3},
+
+	{0x41, 0x32}, /* 33 //44 */
+	{0x42, 0x22}, /*22 //43 */
+	{0x43, 0xf0}, /*f6 */
+	{0x44, 0x44}, /*44 */
+	{0x45, 0x44}, /*33 */
+	{0x46, 0x00},
+	{0x50, 0xb2},
+	{0x51, 0x81},
+	{0x52, 0x98},
+
+	{0x80, 0x38},
+	{0x81, 0x20},
+	{0x82, 0x36}, /* 3a */
+
+	{0x83, 0x5e}, //5e
+	{0x84, 0x21}, /* 24 */
+	{0x85, 0x51}, /* 54 */
+	{0x86, 0x20}, //24 //22
+
+	{0x87, 0x49},
+	{0x88, 0x39},
+	{0x89, 0x37}, //38
+	{0x8a, 0x29}, //2a
+
+	{0x8b, 0x41}, //47
+	{0x8c, 0x39},
+	{0x8d, 0x34},
+	{0x8e, 0x29}, //2c
+
+	{0x8f, 0x5c},
+	{0x90, 0x5b},
+	{0x91, 0x57},
+	{0x92, 0x4f},
+	{0x93, 0x43},
+	{0x94, 0x3e},
+	{0x95, 0x34},
+	{0x96, 0x2c},
+	{0x97, 0x23},
+	{0x98, 0x20},
+	{0x99, 0x1f},
+	{0x9a, 0x1f},
+
+	{0x9b, 0x77},
+	{0x9c, 0x66},
+	{0x9d, 0x48},
+	{0x9e, 0x38},
+	{0x9f, 0x30},
+
+	{0xa0, 0x60},
+	{0xa1, 0x34},
+	{0xa2, 0x6f},
+	{0xa3, 0xff},
+
+	{0xa4, 0x14}, //1500fps
+	{0xa5, 0x2c}, // 700fps
+	{0xa6, 0xcf},
+
+	{0xad, 0x40},
+	{0xae, 0x4a},
+
+	{0xaf, 0x28},  // low temp Rgain
+	{0xb0, 0x26},  // low temp Rgain
+
+	{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+	{0xb4, 0xea},
+	{0xb8, 0xb0}, /* a2: b-2, R+2  //b4 B-3, R+4 lowtemp */
+	{0xb9, 0x00},
+	/////// PAGE 22 END ///////
+
+	/////// PAGE 20 ///////
+	{0x03, 0x20},
+	{0x10, 0x9c}, /* AE on 50hz */
+
+	/////// PAGE 22 ///////
+	{0x03, 0x22},
+	{0x10, 0xe9},
+
+	/////// PAGE 0 ///////
+	{0x03, 0x00},
+	{0x0e, 0x03},
+	{0x0e, 0x73},
+
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+	{0x03, 0x00},
+
+	{0x03, 0x00},
+	{0x01, 0xf8},
+
+	{0xff, 0x28},/* NEED Delay 400ms */
+};
+
+regs_short_t front_preview_camera_regs[] = {
+
+{0x03, 0x00}, //Sleep On
+{0x01, 0xf9},
+
+{0x0e, 0x03}, //Pll off
+
+{0x03, 0x20}, //page 20
+{0x18, 0x30}, //for Preview
+{0x10, 0x1c}, //ae off//ae off_50Hz
+
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+{0x03, 0x00},
+{0x10, 0x11},
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x02},
+{0x22, 0x00},
+{0x23, 0x0a},
+
+{0x42, 0x00}, //VBlank 
+{0x43, 0x58}, //88
+
+//Page10
+{0x03, 0x10},
+{0x3f, 0x02},
+{0x60, 0x6b},
+
+//Page12
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+{0x90, 0x00},
+
+/* only for Preview DPC */
+{0xd2, 0x17},
+{0xd5, 0x0f},
+{0xd7, 0xff},
+
+//Page13
+{0x03, 0x13},
+{0x80, 0x00},
+
+{0x03, 0x20},
+{0x10, 0x9c},//AE ON
+
+{0x03, 0x22},
+{0x10, 0xe9}, //AWB ON
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL ON
+{0x0e, 0x73}, // x2
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00}, //Sleep Off
+{0x01, 0xf8},
+
+{0xff, 0x28}, //400ms
+};
+
+regs_short_t front_snapshot_normal_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+
+{0x0e, 0x03}, //PLL Off
+
+{0x03, 0x22}, //Page 22
+{0x10, 0x69}, //AWB Off
+
+{0x03, 0x00},
+{0x10, 0x00},
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x0a},
+{0x22, 0x00},
+{0x23, 0x0a},
+
+//Page10
+{0x03, 0x10},
+{0x3f, 0x00},
+{0x60, 0x67},
+  
+//Page12
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+{0x90, 0x5d},
+  
+/* only for Preview DPC Off */
+{0xd2, 0x67},
+{0xd5, 0x02},
+{0xd7, 0x18},
+
+//Page13
+{0x03, 0x13},
+{0x80, 0xfd},
+
+/* Page0 */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL ON
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8}, //Sleep Off
+
+{0xff, 0x03},  //Increase from 30ms
+};
+
+regs_short_t front_ev_minus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0xd0},
+};
+
+regs_short_t front_ev_minus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0xc0},
+};
+
+regs_short_t front_ev_minus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0xb0},
+};
+
+regs_short_t front_ev_minus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0xa0},
+};
+
+regs_short_t front_ev_default_regs[] = {
+{0x03, 0x10},
+{0x40, 0x00},
+};
+
+regs_short_t front_ev_plus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0x20},
+};
+
+regs_short_t front_ev_plus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0x30},
+};
+
+regs_short_t front_ev_plus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0x40},
+};
+
+regs_short_t front_ev_plus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_default[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_1[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_2[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_3[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_fps_auto_regs[] = {
+};
+
+regs_short_t front_fps_7_regs[] = {
+/* fixed 7 fps */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68}, 
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x0e}, //BLC_TIME_TH_ON
+{0x91, 0x0e}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x0e}, //DCDC_TIME_TH_ON
+{0xd5, 0x0e}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x06}, //EXP Max 07.14 fps
+{0x89, 0x68},
+{0x8a, 0xa0},
+
+{0x91, 0x06}, //EXP Fix 07.00 fps
+{0x92, 0x89},
+{0x93, 0xd4},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps 
+{0x9d, 0x70}, 
+{0x9e, 0x01}, //EXP Unit 
+{0x9f, 0xf4}, 
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/* NEED Delay 400ms */
+};
+
+regs_short_t front_fps_10_regs[] = {
+/* fixed 10 fps */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68}, 
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x09}, //BLC_TIME_TH_ON
+{0x91, 0x09}, //BLC_TIME_TH_OFF
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x09}, //DCDC_TIME_TH_ON
+{0xd5, 0x09}, //DCDC_TIME_TH_OFF
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x04}, //EXP Max 11.11 fps
+{0x89, 0x1e},
+{0x8a, 0xb0},
+
+{0x91, 0x04}, //EXP Fix 10.00 fps
+{0x92, 0x93},
+{0x93, 0xe0},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps 
+{0x9d, 0x70}, 
+{0x9e, 0x01}, //EXP Unit 
+{0x9f, 0xf4}, 
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_fps_15_regs[] = {
+/* fixed 15 fps */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x11, 0x90},
+
+{0x40, 0x01}, //Hblank 360
+{0x41, 0x68}, 
+{0x42, 0x00}, //Vsync 20
+{0x43, 0x14},
+
+{0x90, 0x06}, //BLC_TIME_TH_ON
+{0x91, 0x06}, //BLC_TIME_TH_OFF 
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+
+{0x03, 0x02}, //PAGE 2
+{0xd4, 0x06}, //DCDC_TIME_TH_ON
+{0xd5, 0x06}, //DCDC_TIME_TH_OFF 
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x02}, //EXP Max 16.67 fps
+{0x89, 0xbf},
+{0x8a, 0x20},
+
+{0x91, 0x03}, //EXP Fix 14.91 fps
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17}, //EXP Limit 500.00 fps 
+{0x9d, 0x70}, 
+{0x9e, 0x01}, //EXP Unit 
+{0x9f, 0xf4}, 
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+
+};
+
+regs_short_t front_fps_24_regs[] = {
+/* fixed 24 fps */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x0e, 0x03}, //PLL Off
+{0x10, 0x1b}, //Vsync Active High B:[3]
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x40, 0x01}, //Hblank 352
+{0x41, 0x60}, 
+{0x42, 0x00}, //Vblank 20
+{0x43, 0x14}, 
+
+{0x90, 0x04}, //BLC_TIME_TH_ON
+{0x91, 0x04}, //BLC_TIME_TH_OFF 
+{0x92, 0xb0}, //BLC_AG_TH_ON
+{0x93, 0xa8}, //BLC_AG_TH_OFF
+
+{0x03, 0x02},
+{0xd4, 0x04}, //DCDC_TIME_TH_ON
+{0xd5, 0x04}, //DCDC_TIME_TH_OFF 
+{0xd6, 0xb0}, //DCDC_AG_TH_ON
+{0xd7, 0xa8}, //DCDC_AG_TH_OFF
+
+{0x03, 0x10},
+{0x3f, 0x00}, //Setting For Camcorder 24
+{0x60, 0x67}, //Setting For Camcorder 24
+
+{0x03, 0x12},
+{0x20, 0x0f}, //Setting For Camcorder 24
+{0x21, 0x0f}, //Setting For Camcorder 24
+
+{0x90, 0x5d}, //Setting For Camcorder 24
+
+{0x03, 0x13},
+{0x80, 0xfd}, //Setting For Camcorder 24
+
+{0x03, 0x20},
+{0x10, 0x1C}, //AE off 50hz
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+{0x79, 0x49},
+
+{0x86, 0x01}, //EXPMin 10204.08 fps
+{0x87, 0x26}, 
+
+{0x88, 0x01}, //EXP Max 25.00 fps 
+{0x89, 0xd4}, 
+{0x8a, 0x90}, 
+
+{0x8B, 0x75}, //EXP100 
+{0x8C, 0x24}, 
+
+{0x8D, 0x61}, //EXP120 
+{0x8E, 0x9e}, 
+
+{0x91, 0x01}, //EXP Fix 23.93 fps
+{0x92, 0xe9}, 
+{0x93, 0xcf}, 
+
+{0x9c, 0x0e}, //EXP Limit 784.93 fps 
+{0x9d, 0xee}, 
+{0x9e, 0x01}, //EXP Unit 
+{0x9f, 0x26}, 
+
+{0x03, 0x20},
+{0x10, 0x9C}, //AE on 50hz
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL Off
+{0x0e, 0x73}, //PLL ON x2
+
+{0x03, 0x00}, //Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},//NEED Delay 400ms//
+};
+
+regs_short_t front_pattern_on_regs[] =  {
+{0x03, 0x00},
+{0x50, 0x05},
+};
+
+regs_short_t front_pattern_off_regs[] =  {
+{0x03, 0x00},
+{0x50, 0x00},
+};
+
+
+#endif /* __SR200PC20_REGS_H */
diff --git a/drivers/media/video/sr200pc20m.c b/drivers/media/video/sr200pc20m.c
new file mode 100644
index 0000000..5d12805
--- /dev/null
+++ b/drivers/media/video/sr200pc20m.c
@@ -0,0 +1,1427 @@
+/*
+ * Driver for SR200PC20M from Samsung Electronics
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#ifdef CONFIG_VIDEO_SAMSUNG_V4L2
+#include <linux/videodev2_exynos_camera.h>
+#endif
+#include <media/sr200pc20m_platform.h>
+#include "sr200pc20m.h"
+
+extern struct class *camera_class;
+struct device *sr200pc20m_dev;
+
+static const struct sr200pc20m_fps sr200pc20m_framerates[] = {
+	{I_FPS_0, FRAME_RATE_AUTO},
+	{I_FPS_7, FRAME_RATE_7},
+	{I_FPS_10, 10},
+	{I_FPS_12, 12},
+	{I_FPS_15, FRAME_RATE_15},
+	{I_FPS_25, FRAME_RATE_25},
+};
+
+static const struct sr200pc20m_regs reg_datas = {
+	.ev = {
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_MINUS_4),
+				 front_ev_minus_4_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_MINUS_3),
+				 front_ev_minus_3_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_MINUS_2),
+				 front_ev_minus_2_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_MINUS_1),
+				 front_ev_minus_1_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_DEFAULT),
+				 front_ev_default_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_PLUS_1), front_ev_plus_1_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_PLUS_2), front_ev_plus_2_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_PLUS_3), front_ev_plus_3_regs),
+	       SR200PC20M_REGSET(GET_EV_INDEX(EV_PLUS_4), front_ev_plus_4_regs),
+	       },
+	.blur = {
+		 SR200PC20M_REGSET(BLUR_LEVEL_0, front_vt_pretty_default),
+		 SR200PC20M_REGSET(BLUR_LEVEL_1, front_vt_pretty_1),
+		 SR200PC20M_REGSET(BLUR_LEVEL_2, front_vt_pretty_2),
+		 SR200PC20M_REGSET(BLUR_LEVEL_3, front_vt_pretty_3),
+		 },
+	.fps = {
+		SR200PC20M_REGSET(I_FPS_0, front_fps_auto_regs),
+		SR200PC20M_REGSET(I_FPS_7, front_fps_7_regs),
+		SR200PC20M_REGSET(I_FPS_10, front_fps_10_regs),
+		SR200PC20M_REGSET(I_FPS_15, front_fps_15_regs),
+		SR200PC20M_REGSET(I_FPS_25, front_fps_24_regs),
+		},
+	.preview_start = SR200PC20M_REGSET_TABLE(front_preview_camera_regs),
+	.capture_start = SR200PC20M_REGSET_TABLE(front_snapshot_normal_regs),
+	.init = SR200PC20M_REGSET_TABLE(front_init_regs),
+	.init_vt = SR200PC20M_REGSET_TABLE(front_init_vt_regs),
+	.init_recording = SR200PC20M_REGSET_TABLE(front_init_recording_regs),
+	.dtp_on = SR200PC20M_REGSET_TABLE(front_pattern_on_regs),
+	.dtp_off = SR200PC20M_REGSET_TABLE(front_pattern_off_regs),
+};
+
+#ifdef CONFIG_LOAD_FILE
+static int loadFile(void)
+{
+	struct file *fp = NULL;
+	struct test *nextBuf = NULL;
+
+	u8 *nBuf = NULL;
+	size_t file_size = 0, max_size = 0, testBuf_size = 0;
+	ssize_t nread = 0;
+	s32 check = 0, starCheck = 0;
+	s32 tmp_large_file = 0;
+	s32 i = 0;
+	int ret = 0;
+	loff_t pos;
+
+	mm_segment_t fs = get_fs();
+	set_fs(get_ds());
+
+	BUG_ON(testBuf);
+
+	fp = filp_open(TUNING_FILE_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp)) {
+		cam_err("file open error\n");
+		return PTR_ERR(fp);
+	}
+
+	file_size = (size_t) fp->f_path.dentry->d_inode->i_size;
+	max_size = file_size;
+
+	cam_dbg("file_size = %d\n", file_size);
+
+	nBuf = kmalloc(file_size, GFP_ATOMIC);
+	if (nBuf == NULL) {
+		cam_dbg("Fail to 1st get memory\n");
+		nBuf = vmalloc(file_size);
+		if (nBuf == NULL) {
+			cam_err("ERR: nBuf Out of Memory\n");
+			ret = -ENOMEM;
+			goto error_out;
+		}
+		tmp_large_file = 1;
+	}
+
+	testBuf_size = sizeof(struct test) * file_size;
+	if (tmp_large_file) {
+		testBuf = (struct test *)vmalloc(testBuf_size);
+		large_file = 1;
+	} else {
+		testBuf = kmalloc(testBuf_size, GFP_ATOMIC);
+		if (testBuf == NULL) {
+			cam_dbg("Fail to get mem(%d bytes)\n", testBuf_size);
+			testBuf = (struct test *)vmalloc(testBuf_size);
+			large_file = 1;
+		}
+	}
+	if (testBuf == NULL) {
+		cam_err("ERR: Out of Memory\n");
+		ret = -ENOMEM;
+		goto error_out;
+	}
+
+	pos = 0;
+	memset(nBuf, 0, file_size);
+	memset(testBuf, 0, file_size * sizeof(struct test));
+
+	nread = vfs_read(fp, (char __user *)nBuf, file_size, &pos);
+	if (nread != file_size) {
+		cam_err("failed to read file ret = %d\n", nread);
+		ret = -1;
+		goto error_out;
+	}
+
+	set_fs(fs);
+
+	i = max_size;
+
+	printk("i = %d\n", i);
+
+	while (i) {
+		testBuf[max_size - i].data = *nBuf;
+		if (i != 1) {
+			testBuf[max_size - i].nextBuf =
+			    &testBuf[max_size - i + 1];
+		} else {
+			testBuf[max_size - i].nextBuf = NULL;
+			break;
+		}
+		i--;
+		nBuf++;
+	}
+
+	i = max_size;
+	nextBuf = &testBuf[0];
+
+#if 1
+	while (i - 1) {
+		if (!check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size - i].nextBuf != NULL) {
+					if (testBuf[max_size - i].nextBuf->data
+					    == '/') {
+						check = 1; /* when find '//' */
+						i--;
+					} else if (testBuf[max_size - i].
+						   nextBuf->data == '*') {
+						starCheck = 1; /* when find '/ *' */
+						i--;
+					}
+				} else
+					break;
+			}
+			if (!check && !starCheck) {
+				/* ignore '\t' */
+				if (testBuf[max_size - i].data != '\t') {
+					nextBuf->nextBuf =
+					    &testBuf[max_size - i];
+					nextBuf = &testBuf[max_size - i];
+				}
+			}
+		} else if (check && !starCheck) {
+			if (testBuf[max_size - i].data == '/') {
+				if (testBuf[max_size - i].nextBuf != NULL) {
+					if (testBuf[max_size - i].nextBuf->
+					    data == '*') {
+						starCheck = 1; /* when find '/ *' */
+						check = 0;
+						i--;
+					}
+				} else
+					break;
+			}
+
+			/* when find '\n' */
+			if (testBuf[max_size - i].data == '\n' && check) {
+				check = 0;
+				nextBuf->nextBuf = &testBuf[max_size - i];
+				nextBuf = &testBuf[max_size - i];
+			}
+
+		} else if (!check && starCheck) {
+			if (testBuf[max_size - i].data == '*') {
+				if (testBuf[max_size - i].nextBuf != NULL) {
+					if (testBuf[max_size - i].nextBuf->
+					    data == '/') {
+						starCheck = 0; /* when find '* /' */
+						i--;
+					}
+				} else
+					break;
+			}
+		}
+
+		i--;
+
+		if (i < 2) {
+			nextBuf = NULL;
+			break;
+		}
+
+		if (testBuf[max_size - i].nextBuf == NULL) {
+			nextBuf = NULL;
+			break;
+		}
+	}
+#endif
+
+#if 0
+	printk("i = %d\n", i);
+	nextBuf = &testBuf[0];
+	while (1) {
+		printk("sdfdsf\n");
+		if (nextBuf->nextBuf == NULL)
+			break;
+		printk("%c", nextBuf->data);
+		nextBuf = nextBuf->nextBuf;
+	}
+#endif
+
+ error_out:
+
+	if (nBuf)
+		tmp_large_file ? vfree(nBuf) : kfree(nBuf);
+	if (fp)
+		filp_close(fp, current->files);
+	return ret;
+}
+#endif
+
+static int __used sr200pc20m_i2c_read_byte(struct i2c_client *client,
+					   u16 subaddr, u16 *data)
+{
+	u8 buf[2] = { 0, };
+	struct i2c_msg msg = { client->addr, 0, 1, buf };
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = (u8) subaddr;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to write %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 1;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to read %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	*(u8 *) data = buf[0];
+
+	return 0;
+}
+
+static int __used sr200pc20m_i2c_write_byte(struct i2c_client *client,
+					    u16 subaddr, u16 data)
+{
+	u8 buf[2] = { 0, };
+	struct i2c_msg msg = { client->addr, 0, 2, buf };
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr & 0xFF;
+	buf[1] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1) ? 0 : -EIO;
+}
+
+static int __used sr200pc20m_i2c_read_word(struct i2c_client *client,
+					   u16 subaddr, u16 *data)
+{
+	u8 buf[4];
+	struct i2c_msg msg = { client->addr, 0, 2, buf };
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr >> 8;
+	buf[1] = subaddr & 0xff;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to write %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	msg.flags = I2C_M_RD;
+	msg.len = 2;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, failed to read %d register\n",
+			__func__, subaddr);
+		return -EIO;
+	}
+
+	*data = ((buf[0] << 8) | buf[1]);
+
+	return 0;
+}
+
+static int __used sr200pc20m_i2c_write_word(struct i2c_client *client,
+					    u16 subaddr, u16 data)
+{
+	u8 buf[4];
+	struct i2c_msg msg = { client->addr, 0, 4, buf };
+	int err = 0;
+
+	if (unlikely(!client->adapter)) {
+		cam_err("%s: ERROR, can't search i2c client adapter\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	buf[0] = subaddr >> 8;
+	buf[1] = subaddr & 0xFF;
+	buf[2] = data >> 8;
+	buf[3] = data & 0xFF;
+
+	err = i2c_transfer(client->adapter, &msg, 1);
+
+	return (err == 1) ? 0 : -EIO;
+}
+
+static int sr200pc20m_i2c_set_data_burst(struct v4l2_subdev *sd,
+					 const regs_short_t reg_buffer[],
+					 u32 num_of_regs)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 subaddr, data_value;
+	int i, err = 0;
+
+	for (i = 0; i < num_of_regs; i++) {
+		subaddr = reg_buffer[i].subaddr;
+		data_value = reg_buffer[i].value;
+
+		switch (subaddr) {
+		case DELAY_SEQ:
+			debug_msleep(sd, data_value * 10);
+			break;
+		default:
+			err =
+			    sr200pc20m_i2c_write_byte(client, subaddr,
+						      data_value);
+			if (unlikely(err < 0)) {
+				cam_err("%s: ERROR, failed to"
+					"write reg(0x%02X, 0x%02X).err=%d\n",
+					__func__, subaddr, data_value, err);
+				return -EIO;
+			}
+			break;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_LOAD_FILE
+static int sr200pc20m_write_regs_from_sd(struct v4l2_subdev *sd, u8 s_name[])
+{
+
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct test *tempData = NULL;
+
+	int ret = -EAGAIN;
+	regs_short_t temp;
+	u32 delay = 0;
+	u8 data[11];
+	s32 searched = 0, pair_cnt = 0, brace_cnt = 0;
+	size_t size = strlen(s_name);
+	s32 i;
+
+	cam_trace("E size = %d, string = %s\n", size, s_name);
+	tempData = &testBuf[0];
+	while (!searched) {
+		searched = 1;
+		for (i = 0; i < size; i++) {
+			if (tempData->data != s_name[i]) {
+				searched = 0;
+				break;
+			}
+			tempData = tempData->nextBuf;
+		}
+		tempData = tempData->nextBuf;
+	}
+	/* structure is get.. */
+
+	while (1) {
+		if (tempData->data == '{') {
+			dbg_setfile("%s: found big_brace start\n", __func__);
+			tempData = tempData->nextBuf;
+			break;
+		} else
+			tempData = tempData->nextBuf;
+	}
+
+	while (1) {
+		while (1) {
+			if (tempData->data == '{') {
+				/* dbg_setfile("%s: found small_brace start\n", __func__); */
+				tempData = tempData->nextBuf;
+				break;
+			} else if (tempData->data == '}') {
+				dbg_setfile("%s: found big_brace end\n",
+					    __func__);
+				return 0;
+			} else
+				tempData = tempData->nextBuf;
+		}
+
+		searched = 0;
+		pair_cnt = 0;
+		while (1) {
+			if (tempData->data == 'x') {
+				/* get 10 strings. */
+				data[0] = '0';
+				for (i = 1; i < 4; i++) {
+					data[i] = tempData->data;
+					tempData = tempData->nextBuf;
+				}
+				data[i] = '\0';
+				/* dbg_setfile("read HEX: %s\n", data); */
+				if (pair_cnt == 0) {
+					temp.subaddr =
+					    simple_strtoul(data, NULL, 16);
+					pair_cnt++;
+				} else if (pair_cnt == 1) {
+					temp.value =
+					    simple_strtoul(data, NULL, 16);
+					pair_cnt++;
+				}
+			} else if (tempData->data == '}') {
+				/* dbg_setfile("%s: found small_brace end\n", __func__); */
+				tempData = tempData->nextBuf;
+				/* searched = 1; */
+				break;
+			} else
+				tempData = tempData->nextBuf;
+
+			if (tempData->nextBuf == NULL)
+				return -1;
+		}
+
+		if (searched)
+			break;
+
+		if ((temp.subaddr & 0xFF) == 0xFF) {
+			delay = (temp.value & 0xFF) * 10;
+			debug_msleep(sd, delay);
+			continue;
+		}
+
+		/* cam_err("Write: 0x%02X, 0x%02X\n",
+		   (u8)(temp.subaddr), (u8)(temp.value)); */
+		ret =
+		    sr200pc20m_i2c_write_byte(client, temp.subaddr, temp.value);
+
+		/* In error circumstances */
+		/* Give second shot */
+		if (unlikely(ret)) {
+			dev_info(&client->dev,
+				 "sr200pc20m i2c retry one more time\n");
+			ret =
+			    sr200pc20m_i2c_write_byte(client, temp.subaddr,
+						      temp.value);
+
+			/* Give it one more shot */
+			if (unlikely(ret)) {
+				dev_info(&client->dev,
+					 "sr200pc20m i2c retry twice\n");
+				ret =
+				    sr200pc20m_i2c_write_byte(client,
+							      temp.subaddr,
+							      temp.value);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+static int sr200pc20m_set_from_table(struct v4l2_subdev *sd,
+				     const char *setting_name,
+				     const struct sr200pc20m_regset_table
+				     *table, int table_size, int index)
+{
+	int err = 0;
+
+	/* cam_dbg("%s: set %s index %d\n",
+	   __func__, setting_name, index); */
+	if ((index < 0) || (index >= table_size)) {
+		cam_err("%s: ERROR, index(%d) out of range[0:%d]"
+			"for table for %s\n", __func__, index,
+			table_size, setting_name);
+		return -EINVAL;
+	}
+
+	table += index;
+	if (unlikely(!table->reg)) {
+		cam_err("%s: ERROR, reg = NULL\n", __func__);
+		return -EFAULT;
+	}
+#ifdef CONFIG_LOAD_FILE
+	cam_dbg("%s: \"%s\", reg_name=%s\n", __func__, setting_name,
+		table->name);
+	return sr200pc20m_write_regs_from_sd(sd, table->name);
+#else
+	err = sr200pc20m_i2c_set_data_burst(sd, table->reg, table->array_size);
+	if (unlikely(err < 0)) {
+		cam_err("%s: ERROR, fail to write regs(%s), err=%d\n",
+			__func__, setting_name, err);
+		return -EIO;
+	}
+
+	return 0;
+#endif
+}
+
+static inline int sr200pc20m_get_iso(struct v4l2_subdev *sd, u16 * iso)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	/* u16 iso_gain_table[] = {10, 18, 23, 28};
+	   u16 iso_table[] = {0, 50, 100, 200, 400}; */
+	u16 read_value = 0, gain = 0;
+
+	sr200pc20m_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20m_i2c_read_byte(client, 0xb0, &read_value);
+	gain = (read_value * 100 / 32) + 50;
+
+	if (read_value < 125)
+		*iso = 50;
+	else if (read_value < 175)
+		*iso = 100;
+	else if (read_value < 250)
+		*iso = 200;
+	else if (read_value < 375)
+		*iso = 400;
+	else if (read_value < 550)
+		*iso = 800;
+	else
+		*iso = 1600;
+
+	cam_dbg("gain=%d, ISO=%d\n", gain, *iso);
+
+	return 0;
+}
+
+static int sr200pc20m_get_expousretime(struct v4l2_subdev *sd, u32 * exp_time)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 read_value = 0;
+	u32 cintr = 0;
+
+	sr200pc20m_i2c_write_byte(client, 0x03, 0x20);
+	sr200pc20m_i2c_read_byte(client, 0x80, &read_value);
+	cintr = read_value << 19;
+	sr200pc20m_i2c_read_byte(client, 0x81, &read_value);
+	cintr |= read_value << 11;
+	sr200pc20m_i2c_read_byte(client, 0x82, &read_value);
+	cintr |= read_value << 3;
+
+	*exp_time = cintr / 24;	/* us */
+
+	return 0;
+}
+
+static int sr200pc20m_get_exif(struct v4l2_subdev *sd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	u32 exposure_time = 0;
+
+	/* Get exposure-time */
+	state->exif.exp_time_den = 0;
+	sr200pc20m_get_expousretime(sd, &exposure_time);
+	state->exif.exp_time_den = 1000000 / exposure_time;
+	cam_dbg("exposure time=%dus\n", exposure_time);
+
+	/* Get ISO */
+	state->exif.iso = 0;
+	sr200pc20m_get_iso(sd, &state->exif.iso);
+
+	cam_dbg("get_exif: exp_time_den=%d, ISO=%d\n",
+		state->exif.exp_time_den, state->exif.iso);
+	return 0;
+}
+
+#ifdef SUPPORT_FACTORY_TEST
+static int sr200pc20m_check_dataline(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EIO;
+
+	if (state->pdata->is_mipi)
+		return 0;
+
+	cam_info("DTP %s\n", val ? "ON" : "OFF");
+
+	if (val)
+		err = sr200pc20m_set_from_table(sd, "dtp_on",
+						&state->regs->dtp_on, 1, 0);
+	else
+		err = sr200pc20m_set_from_table(sd, "dtp_off",
+						&state->regs->dtp_off, 1, 0);
+
+	CHECK_ERR_MSG(err, "fail to DTP setting\n");
+	return 0;
+}
+#endif
+
+static int sr200pc20m_check_sensor_status(struct v4l2_subdev *sd)
+{
+
+	/*struct i2c_client *client = v4l2_get_subdevdata(sd); */
+	/*u16 val_1 = 0, val_2 = 0;
+	   int err = -EINVAL; */
+
+#if 1				/* DSLIM */
+	cam_warn("check_sensor_status: WARNING, Not implemented!!\n\n");
+	return 0;
+#else
+
+	err = sr200pc20m_read_reg(sd, 0x7000, 0x0132, &val_1);
+	CHECK_ERR(err);
+	err = sr200pc20m_read_reg(sd, 0xD000, 0x1002, &val_2);
+	CHECK_ERR(err);
+
+	cam_dbg("read val1=0x%x, val2=0x%x\n", val_1, val_2);
+
+	if ((val_1 != 0xAAAA) || (val_2 != 0))
+		goto error_occur;
+
+	cam_info("Sensor ESD Check: not detected\n");
+	return 0;
+#endif
+ error_occur:
+	cam_err("%s: ERROR, ESD Shock detected!\n\n", __func__);
+	return -ERESTART;
+}
+
+static inline int sr200pc20m_check_esd(struct v4l2_subdev *sd)
+{
+	int err = -EINVAL;
+
+	err = sr200pc20m_check_sensor_status(sd);
+	CHECK_ERR(err);
+
+	return 0;
+}
+
+static int sr200pc20m_set_preview_start(struct v4l2_subdev *sd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (state->first_preview) {
+		state->first_preview = 0;
+#ifdef SUPPORT_FACTORY_TEST
+		if (state->check_dataline) {
+			err = sr200pc20m_check_dataline(sd, 1);
+			CHECK_ERR(err);
+		}
+#endif
+		return 0;
+	}
+
+	cam_info("set_preview_start\n");
+
+	err = sr200pc20m_set_from_table(sd, "preview_start",
+					&state->regs->preview_start, 1, 0);
+	CHECK_ERR_MSG(err, "fail to make preview\n")
+
+	    return 0;
+}
+
+static int sr200pc20m_set_capture_start(struct v4l2_subdev *sd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_capture_start\n");
+
+	err = sr200pc20m_set_from_table(sd, "capture_start",
+					&state->regs->capture_start, 1, 0);
+	CHECK_ERR_MSG(err, "failed to make capture\n");
+
+	sr200pc20m_get_exif(sd);
+
+	return err;
+}
+
+static int sr200pc20m_set_sensor_mode(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+
+	switch (val) {
+	case SENSOR_MOVIE:
+		if (state->vt_mode) {
+			state->sensor_mode = SENSOR_CAMERA;
+			cam_warn("%s: WARNING, Not support movie in vt mode\n",
+				 __func__);
+			break;
+		}
+		/* We do not break. */
+	case SENSOR_CAMERA:
+		state->sensor_mode = val;
+		break;
+	default:
+		cam_err("%s: ERROR: Not support mode.(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sr200pc20m_init_regs(struct v4l2_subdev *sd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	u16 read_value = 0;
+	int err = -ENODEV;
+
+	err = sr200pc20m_i2c_write_byte(client, 0x03, 0x00);
+	if (unlikely(err < 0))
+		return -ENODEV;
+
+	sr200pc20m_i2c_read_byte(client, 0x04, &read_value);
+	if (likely(read_value == SR200PC20M_CHIP_ID))
+		cam_info("Sensor ChipID: 0x%02X\n", SR200PC20M_CHIP_ID);
+	else
+		cam_info("Sensor ChipID: 0x%02X, unknown chipID\n", read_value);
+
+	state->regs = &reg_datas;
+
+	return 0;
+}
+
+static int sr200pc20m_enum_framesizes(struct v4l2_subdev *sd,
+				      struct v4l2_frmsizeenum *fsize)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	/*
+	 * Return the actual output settings programmed to the camera
+	 */
+	if (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE) {
+		fsize->discrete.width = state->capture_frmsizes.width;
+		fsize->discrete.height = state->capture_frmsizes.height;
+	} else {
+		fsize->discrete.width = state->preview_frmsizes.width;
+		fsize->discrete.height = state->preview_frmsizes.height;
+	}
+
+	cam_info("enum_framesizes: width - %d , height - %d\n",
+		 fsize->discrete.width, fsize->discrete.height);
+
+	return 0;
+}
+
+static int sr200pc20m_s_mbus_fmt(struct v4l2_subdev *sd,
+				 struct v4l2_mbus_framefmt *fmt)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	u32 *width = NULL, *height = NULL;
+
+	cam_trace("E\n");
+	/*
+	 * Just copying the requested format as of now.
+	 * We need to check here what are the formats the camera support, and
+	 * set the most appropriate one according to the request from FIMC
+	 */
+#ifdef NEW_CAM_DRV
+	v4l2_fill_pix_format(&state->req_fmt, fmt);
+	state->req_fmt.priv = fmt->field;
+#else
+	memcpy(&state->req_fmt, &fmt->fmt.pix, sizeof(fmt->fmt.pix));
+#endif
+
+	switch (state->req_fmt.priv) {
+	case V4L2_PIX_FMT_MODE_PREVIEW:
+		width = &state->preview_frmsizes.width;
+		height = &state->preview_frmsizes.height;
+		break;
+
+	case V4L2_PIX_FMT_MODE_CAPTURE:
+		width = &state->capture_frmsizes.width;
+		height = &state->capture_frmsizes.height;
+		break;
+
+	default:
+		cam_err("%s: ERROR, inavlid FMT Mode(%d)\n",
+			__func__, state->req_fmt.priv);
+		return -EINVAL;
+	}
+
+	if ((*width != state->req_fmt.width) ||
+	    (*height != state->req_fmt.height)) {
+		cam_err("%s: ERROR, Invalid size. width= %d, height= %d\n",
+			__func__, state->req_fmt.width, state->req_fmt.height);
+	}
+
+	return 0;
+}
+
+static int sr200pc20m_set_frame_rate(struct v4l2_subdev *sd, s32 fps)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EIO;
+	int i = 0, fps_index = -1;
+
+	cam_info("set frame rate %d\n", fps);
+
+	for (i = 0; i < ARRAY_SIZE(sr200pc20m_framerates); i++) {
+		if (fps == sr200pc20m_framerates[i].fps) {
+			fps_index = sr200pc20m_framerates[i].index;
+			state->fps = fps;
+			state->req_fps = -1;
+			break;
+		}
+	}
+
+	if (unlikely(fps_index < 0)) {
+		cam_err("%s: WARNING, Not supported FPS(%d)\n", __func__, fps);
+		return 0;
+	}
+
+	if (state->sensor_mode != SENSOR_MOVIE) {
+		err = sr200pc20m_set_from_table(sd, "fps", state->regs->fps,
+						ARRAY_SIZE(state->regs->fps),
+						fps_index);
+		CHECK_ERR_MSG(err, "fail to set framerate\n")
+	}
+
+	return 0;
+}
+
+static int sr200pc20m_g_parm(struct v4l2_subdev *sd,
+			     struct v4l2_streamparm *parms)
+{
+	int err = 0;
+
+	cam_trace("E\n");
+
+	return err;
+}
+
+static int sr200pc20m_s_parm(struct v4l2_subdev *sd,
+			     struct v4l2_streamparm *parms)
+{
+	int err = 0;
+	struct sr200pc20m_state *state = to_state(sd);
+
+	state->req_fps = parms->parm.capture.timeperframe.denominator /
+	    parms->parm.capture.timeperframe.numerator;
+
+	cam_dbg("s_parm fps=%d, req_fps=%d\n", state->fps, state->req_fps);
+
+	if ((state->req_fps < 0) || (state->req_fps > 30)) {
+		cam_err("%s: ERROR, invalid frame rate %d. we'll set to %d\n",
+			__func__, state->req_fps, DEFAULT_FPS);
+		state->req_fps = DEFAULT_FPS;
+	}
+
+	if (state->initialized) {
+		err = sr200pc20m_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+static int sr200pc20m_wait_steamoff(struct v4l2_subdev *sd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	struct sr200pc20m_stream_time *stream_time = &state->stream_time;
+	s32 elapsed_msec = 0;
+
+	cam_trace("E\n");
+
+	if (unlikely(!(state->pdata->is_mipi & state->need_wait_streamoff)))
+		return 0;
+
+	do_gettimeofday(&stream_time->curr_time);
+
+	elapsed_msec = GET_ELAPSED_TIME(stream_time->curr_time,
+					stream_time->before_time) / 1000;
+
+	if (state->pdata->streamoff_delay > elapsed_msec) {
+		cam_info("stream-off: %dms + %dms\n", elapsed_msec,
+			 state->pdata->streamoff_delay - elapsed_msec);
+		debug_msleep(sd, state->pdata->streamoff_delay - elapsed_msec);
+	} else
+		cam_info("stream-off: %dms\n", elapsed_msec);
+
+	state->need_wait_streamoff = 0;
+
+	return 0;
+}
+
+static int sr200pc20m_control_stream(struct v4l2_subdev *sd, u32 cmd)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	if (unlikely(cmd != STREAM_STOP))
+		return 0;
+
+	cam_info("STREAM STOP!!\n");
+	err = 0;
+	CHECK_ERR_MSG(err, "failed to stop stream\n");
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	do_gettimeofday(&state->stream_time.before_time);
+	state->need_wait_streamoff = 1;
+#else
+	debug_msleep(sd, state->pdata->streamoff_delay);
+#endif
+	return 0;
+}
+
+static int sr200pc20m_init(struct v4l2_subdev *sd, u32 val)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_trace("E\n");
+
+	err = sr200pc20m_init_regs(sd);
+	CHECK_ERR_MSG(err, "failed to indentify sensor chip\n");
+
+	/* set initial regster value */
+	if (state->sensor_mode == SENSOR_CAMERA) {
+		if (!state->vt_mode) {
+			cam_info("load camera common setting\n");
+			err = sr200pc20m_set_from_table(sd, "init",
+							&state->regs->init, 1,
+							0);
+		} else {
+			cam_info("load camera WIFI VT call setting\n");
+			err = sr200pc20m_set_from_table(sd, "init_vt",
+							&state->regs->init_vt,
+							1, 0);
+		}
+	} else {
+		cam_info("load recording setting\n");
+		err = sr200pc20m_set_from_table(sd, "init_recording",
+						&state->regs->init_recording, 1,
+						0);
+	}
+	CHECK_ERR_MSG(err, "failed to initialize camera device\n");
+
+	state->first_preview = 1;
+	state->initialized = 1;
+
+	if (state->req_fps >= 0) {
+		err = sr200pc20m_set_frame_rate(sd, state->req_fps);
+		CHECK_ERR(err);
+	}
+
+	return 0;
+}
+
+/*
+ * s_config subdev ops
+ * With camera device, we need to re-initialize
+ * every single opening time therefor,
+ * it is not necessary to be initialized on probe time.
+ * except for version checking
+ * NOTE: version checking is optional
+ */
+static int sr200pc20m_s_config(struct v4l2_subdev *sd,
+			       int irq, void *platform_data)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+#ifdef CONFIG_LOAD_FILE
+	int err = 0;
+#endif
+
+	if (!platform_data) {
+		cam_err("%s: ERROR, no platform data\n", __func__);
+		return -ENODEV;
+	}
+	state->pdata = platform_data;
+	state->dbg_level = &state->pdata->dbg_level;
+
+	state->initialized = 0;
+	state->fps = 0;
+	state->req_fps = -1;
+	state->sensor_mode = SENSOR_CAMERA;
+
+	/*
+	 * Assign default format and resolution
+	 * Use configured default information in platform data
+	 * or without them, use default information in driver
+	 */
+	if (!(state->pdata->default_width && state->pdata->default_height)) {
+		state->default_frmsizes.width = DEFAULT_PREVIEW_WIDTH;
+		state->default_frmsizes.height = DEFAULT_PREVIEW_HEIGHT;
+	} else {
+		state->default_frmsizes.width = state->pdata->default_width;
+		state->default_frmsizes.height = state->pdata->default_height;
+	}
+
+	state->preview_frmsizes.width = state->default_frmsizes.width;
+	state->preview_frmsizes.height = state->default_frmsizes.height;
+	state->capture_frmsizes.width = DEFAULT_CAPTURE_WIDTH;
+	state->capture_frmsizes.height = DEFAULT_CAPTURE_HEIGHT;
+
+	cam_dbg("Default preview_width: %d , preview_height: %d, "
+		"capture_width: %d, capture_height: %d",
+		state->preview_frmsizes.width, state->preview_frmsizes.height,
+		state->capture_frmsizes.width, state->capture_frmsizes.height);
+
+	state->req_fmt.width = state->preview_frmsizes.width;
+	state->req_fmt.height = state->preview_frmsizes.height;
+	if (!state->pdata->pixelformat)
+		state->req_fmt.pixelformat = DEFAULT_FMT;
+	else
+		state->req_fmt.pixelformat = state->pdata->pixelformat;
+
+#ifdef CONFIG_LOAD_FILE
+	err = loadFile();
+	CHECK_ERR_MSG(err, "failed to load file ERR=%d\n", err)
+#endif
+	    return 0;
+}
+
+static int sr200pc20m_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = 0;
+
+	cam_info("s_stream: mode = %d\n", enable);
+
+	switch (enable) {
+	case STREAM_MODE_CAM_OFF:
+		if (state->sensor_mode == SENSOR_CAMERA) {
+#ifdef SUPPORT_FACTORY_TEST
+			if (state->check_dataline)
+				err = sr200pc20m_check_dataline(sd, 0);
+			else
+#endif
+			if (state->pdata->is_mipi)
+				err = sr200pc20m_control_stream(sd,
+								STREAM_STOP);
+		}
+		break;
+
+	case STREAM_MODE_CAM_ON:
+		if ((state->sensor_mode == SENSOR_CAMERA)
+		    && (state->req_fmt.priv == V4L2_PIX_FMT_MODE_CAPTURE))
+			err = sr200pc20m_set_capture_start(sd);
+		else
+			err = sr200pc20m_set_preview_start(sd);
+		break;
+
+	case STREAM_MODE_MOVIE_ON:
+		cam_dbg("%s: do nothing(movie on)!!\n", __func__);
+		break;
+
+	case STREAM_MODE_MOVIE_OFF:
+		cam_dbg("%s: do nothing(movie off)!!\n", __func__);
+		break;
+
+#ifdef CONFIG_VIDEO_IMPROVE_STREAMOFF
+	case STREAM_MODE_WAIT_OFF:
+		err = sr200pc20m_wait_steamoff(sd);
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR, Invalid stream mode %d\n",
+			__func__, enable);
+		err = -EINVAL;
+		break;
+	}
+
+	CHECK_ERR_MSG(err, "stream on(off) fail")
+
+	    return 0;
+}
+
+static int sr200pc20m_set_exposure(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_exposure: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if ((val < EV_MINUS_4) || (val >= EV_MAX_V4L2)) {
+		cam_err("%s: ERROR, invalid value(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = sr200pc20m_set_from_table(sd, "ev", state->regs->ev,
+					ARRAY_SIZE(state->regs->ev),
+					GET_EV_INDEX(val));
+	CHECK_ERR_MSG(err, "i2c_write for set brightness\n")
+
+	    return 0;
+}
+
+static int sr200pc20m_set_blur(struct v4l2_subdev *sd, s32 val)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = -EINVAL;
+
+	cam_info("set_blur: val=%d\n", val);
+
+#ifdef SUPPORT_FACTORY_TEST
+	if (state->check_dataline)
+		return 0;
+#endif
+	if (unlikely(val < BLUR_LEVEL_0 || val >= BLUR_LEVEL_MAX)) {
+		cam_err("%s: ERROR, invalid blur(%d)\n", __func__, val);
+		return -EINVAL;
+	}
+
+	err = sr200pc20m_set_from_table(sd, "blur", state->regs->blur,
+					ARRAY_SIZE(state->regs->blur), val);
+	CHECK_ERR_MSG(err, "i2c_write for set blur\n")
+
+	    return 0;
+}
+
+static int sr200pc20m_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("g_ctrl: id = %d\n", ctrl->id - V4L2_CID_PRIVATE_BASE);
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_EXIF_EXPTIME:
+		ctrl->value = state->exif.exp_time_den;
+		break;
+
+	case V4L2_CID_CAMERA_EXIF_ISO:
+		ctrl->value = state->exif.iso;
+		break;
+
+	default:
+		cam_err("%s: ERROR, no such control id %d\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	return err;
+}
+
+static int sr200pc20m_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct sr200pc20m_state *state = to_state(sd);
+	int err = 0;
+
+	cam_dbg("s_ctrl: id = %d, value=%d\n",
+		ctrl->id - V4L2_CID_PRIVATE_BASE, ctrl->value);
+
+	if ((ctrl->id != V4L2_CID_CAMERA_CHECK_DATALINE)
+	    && (ctrl->id != V4L2_CID_CAMERA_SENSOR_MODE)
+	    && ((ctrl->id != V4L2_CID_CAMERA_VT_MODE))
+	    && (!state->initialized)) {
+		cam_warn("%s: WARNING, camera not initialized\n", __func__);
+		return 0;
+	}
+
+	mutex_lock(&state->ctrl_lock);
+
+	switch (ctrl->id) {
+	case V4L2_CID_CAMERA_BRIGHTNESS:
+		err = sr200pc20m_set_exposure(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_BRIGHTNESS [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VGA_BLUR:
+		err = sr200pc20m_set_blur(sd, ctrl->value);
+		cam_dbg("V4L2_CID_CAMERA_VGA_BLUR [%d]\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_VT_MODE:
+		state->vt_mode = ctrl->value;
+		break;
+
+	case V4L2_CID_CAMERA_SENSOR_MODE:
+		err = sr200pc20m_set_sensor_mode(sd, ctrl->value);
+		cam_dbg("sensor_mode = %d\n", ctrl->value);
+		break;
+
+	case V4L2_CID_CAMERA_CHECK_ESD:
+		err = sr200pc20m_check_esd(sd);
+		break;
+
+#ifdef SUPPORT_FACTORY_TEST
+	case V4L2_CID_CAMERA_CHECK_DATALINE:
+		state->check_dataline = ctrl->value;
+		cam_dbg("check_dataline = %d\n", state->check_dataline);
+		err = 0;
+		break;
+#endif
+	default:
+		cam_err("%s: ERROR, not supported ctrl-ID(%d)\n",
+			__func__, ctrl->id - V4L2_CID_PRIVATE_BASE);
+		/* no errors return. */
+		break;
+	}
+
+	mutex_unlock(&state->ctrl_lock);
+
+	cam_trace("X\n");
+	return 0;
+}
+
+static const struct v4l2_subdev_core_ops sr200pc20m_core_ops = {
+	.init = sr200pc20m_init,	/* initializing API */
+	.g_ctrl = sr200pc20m_g_ctrl,
+	.s_ctrl = sr200pc20m_s_ctrl,
+};
+
+static const struct v4l2_subdev_video_ops sr200pc20m_video_ops = {
+	/*.s_crystal_freq = sr200pc20m_s_crystal_freq, */
+	.s_mbus_fmt = sr200pc20m_s_mbus_fmt,
+	.s_stream = sr200pc20m_s_stream,
+	.enum_framesizes = sr200pc20m_enum_framesizes,
+	/*.enum_frameintervals = sr200pc20m_enum_frameintervals, */
+	/* .enum_mbus_fmt = sr200pc20m_enum_mbus_fmt, */
+	/*.enum_fmt = sr200pc20m_enum_fmt, */
+	.g_parm = sr200pc20m_g_parm,
+	.s_parm = sr200pc20m_s_parm,
+};
+
+static const struct v4l2_subdev_ops sr200pc20m_ops = {
+	.core = &sr200pc20m_core_ops,
+	.video = &sr200pc20m_video_ops,
+};
+
+ssize_t sr200pc20m_camera_type_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct sr200pc20m_state *state = dev_get_drvdata(dev);
+
+	char *cam_type;
+	cam_info("%s\n", __func__);
+
+	cam_type = "SF_SR200OC20M";
+
+	return sprintf(buf, "%s\n", cam_type);
+}
+
+static DEVICE_ATTR(front_camtype, S_IRUGO, sr200pc20m_camera_type_show, NULL);
+
+/*
+ * sr200pc20m_probe
+ * Fetching platform data is being done with s_config subdev call.
+ * In probe routine, we just register subdev device
+ */
+static int sr200pc20m_probe(struct i2c_client *client,
+			    const struct i2c_device_id *id)
+{
+	struct sr200pc20m_state *state = NULL;
+	struct v4l2_subdev *sd = NULL;
+	int err = -EINVAL;
+
+	state = kzalloc(sizeof(struct sr200pc20m_state), GFP_KERNEL);
+	CHECK_ERR_COND_MSG(!state, -ENOMEM, "fail to get memory(state)\n");
+
+	mutex_init(&state->ctrl_lock);
+
+	sd = &state->sd;
+	strcpy(sd->name, SR200PC20M_DRIVER_NAME);
+
+	/* Registering subdev */
+	v4l2_i2c_subdev_init(sd, client, &sr200pc20m_ops);
+
+	err = sr200pc20m_s_config(sd, 0, client->dev.platform_data);
+	CHECK_ERR_MSG(err, "fail to s_config\n");
+
+	printk(KERN_DEBUG "%s %s: driver probed!!\n",
+	       dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static int sr200pc20m_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct sr200pc20m_state *state = to_state(sd);
+
+	cam_trace("E\n");
+
+	state->initialized = 0;
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(state);
+
+#ifdef CONFIG_LOAD_FILE
+	if (testBuf) {
+		large_file ? vfree(testBuf) : kfree(testBuf);
+		large_file = 0;
+		testBuf = NULL;
+	}
+#endif
+
+	printk(KERN_DEBUG "%s %s: driver removed!!\n",
+	       dev_driver_string(&client->dev), dev_name(&client->dev));
+	return 0;
+}
+
+static const struct i2c_device_id sr200pc20m_id[] = {
+	{SR200PC20M_DRIVER_NAME, 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, sr200pc20m_id);
+
+static struct i2c_driver sr200pc20m_i2c_driver = {
+	.driver.name = SR200PC20M_DRIVER_NAME,
+	.probe = sr200pc20m_probe,
+	.remove = sr200pc20m_remove,
+	.id_table = sr200pc20m_id,
+};
+
+static int __init sr200pc20m_mod_init(void)
+{
+
+	if (!sr200pc20m_dev) {
+		sr200pc20m_dev =
+		    device_create(camera_class, NULL, 0, NULL, "front");
+		if (IS_ERR(sr200pc20m_dev)) {
+			cam_err("failed to create device m5mo_dev!\n");
+			return 0;
+		}
+		if (device_create_file
+		    (sr200pc20m_dev, &dev_attr_front_camtype) < 0) {
+			cam_err("failed to create device file, %s\n",
+				dev_attr_front_camtype.attr.name);
+		}
+	}
+
+	pr_info("%s: %s called\n", __func__, SR200PC20M_DRIVER_NAME);
+	return i2c_add_driver(&sr200pc20m_i2c_driver);
+}
+
+static void __exit sr200pc20m_mod_exit(void)
+{
+	pr_info("%s: %s called\n", __func__, SR200PC20M_DRIVER_NAME);
+	i2c_del_driver(&sr200pc20m_i2c_driver);
+	if (camera_class)
+		class_destroy(camera_class);
+}
+
+module_init(sr200pc20m_mod_init);
+module_exit(sr200pc20m_mod_exit);
+
+MODULE_DESCRIPTION("SR200PC20M ISP driver");
+MODULE_AUTHOR("DongSeong Lim<dongseong.lim@samsung.com>");
+MODULE_AUTHOR("Roen Lee<doo.hwan.lee@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/sr200pc20m.h b/drivers/media/video/sr200pc20m.h
new file mode 100644
index 0000000..1a42088
--- /dev/null
+++ b/drivers/media/video/sr200pc20m.h
@@ -0,0 +1,269 @@
+/*
+ * Driver for SR200PC20M 2M ISP from Samsung
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: dongseong.lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __SR200PC20M_H
+#define __SR200PC20M_H
+
+#include <linux/types.h>
+
+#define SR200PC20M_DRIVER_NAME	"SR200PC20M"
+
+/************************************
+ * FEATURE DEFINITIONS
+ ************************************/
+/* #define SR200PC20M_USLEEP */
+/* #define CONFIG_LOAD_FILE */
+#define SUPPORT_FACTORY_TEST
+#define NEW_CAM_DRV
+
+/** Debuging Feature **/
+#define CONFIG_CAM_DEBUG
+#define CONFIG_CAM_TRACE	/* Enable it with CONFIG_CAM_DEBUG */
+/***********************************/
+
+#define TAG_NAME	"["SR200PC20M_DRIVER_NAME"]"" "
+#define cam_err(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_warn(fmt, ...)	\
+	printk(KERN_WARNING TAG_NAME fmt, ##__VA_ARGS__)
+#define cam_info(fmt, ...)	\
+	printk(KERN_INFO TAG_NAME fmt, ##__VA_ARGS__)
+
+#if defined(CONFIG_CAM_DEBUG)
+#define cam_dbg(fmt, ...)	\
+	printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define cam_dbg(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_DEBUG) \
+			printk(KERN_DEBUG TAG_NAME fmt, ##__VA_ARGS__); \
+	} while (0)
+#endif				/* CONFIG_CAM_DEBUG */
+
+#if defined(CONFIG_CAM_DEBUG) && defined(CONFIG_CAM_TRACE)
+#define cam_trace(fmt, ...)	cam_dbg("%s: " fmt, __func__, ##__VA_ARGS__);
+#else
+#define cam_trace(fmt, ...)	\
+	do { \
+		if (*to_state(sd)->dbg_level & CAMDBG_LEVEL_TRACE) \
+			printk(KERN_DEBUG TAG_NAME "%s: " fmt, \
+				__func__, ##__VA_ARGS__); \
+	} while (0)
+#endif
+
+#define CHECK_ERR_COND(condition, ret)	\
+	do { if (unlikely(condition)) return (ret); } while (0)
+#define CHECK_ERR_COND_MSG(condition, ret, fmt, ...) \
+	if (unlikely(condition)) { \
+		cam_err("%s: ERROR, " fmt, __func__, ##__VA_ARGS__); \
+		return ret; \
+	}
+
+#define CHECK_ERR(x)	CHECK_ERR_COND(((x) < 0), (x))
+#define CHECK_ERR_MSG(x, fmt, ...) \
+	CHECK_ERR_COND_MSG(((x) < 0), (x), fmt, ##__VA_ARGS__)
+
+enum stream_cmd {
+	STREAM_STOP,
+	STREAM_START,
+};
+
+enum sr200pc20m_fps_index {
+	I_FPS_0,
+	I_FPS_7,
+	I_FPS_10,
+	I_FPS_12,
+	I_FPS_15,
+	I_FPS_25,
+	I_FPS_30,
+	I_FPS_MAX,
+};
+#define DEFAULT_FPS	15
+
+struct sr200pc20m_framesize {
+	u32 width;
+	u32 height;
+};
+
+struct sr200pc20m_fps {
+	u32 index;
+	u32 fps;
+};
+
+struct sr200pc20m_exif {
+	u16 exp_time_den;
+	u16 iso;
+	u32 shutter_speed;
+};
+
+struct sr200pc20m_stream_time {
+	struct timeval curr_time;
+	struct timeval before_time;
+};
+
+#define GET_ELAPSED_TIME(cur, before) \
+		(((cur).tv_sec - (before).tv_sec) * USEC_PER_SEC \
+		+ ((cur).tv_usec - (before).tv_usec))
+
+typedef struct regs_array_type {
+	u16 subaddr;
+	u16 value;
+} regs_short_t;
+
+#ifdef CONFIG_LOAD_FILE
+struct sr200pc20m_regset_table {
+	const regs_short_t *reg;
+	int array_size;
+	char *name;
+};
+
+#define SR200PC20M_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+
+#define SR200PC20M_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+		.name		= #y,			\
+}
+#else
+struct sr200pc20m_regset_table {
+	const regs_short_t *reg;
+	int array_size;
+};
+
+#define SR200PC20M_REGSET(x, y)		\
+	[(x)] = {					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+
+#define SR200PC20M_REGSET_TABLE(y)		\
+	{					\
+		.reg		= (y),			\
+		.array_size	= ARRAY_SIZE((y)),	\
+}
+#endif
+
+#define EV_MIN_VLAUE	EV_MINUS_4
+#define GET_EV_INDEX(EV)	((EV) - (EV_MIN_VLAUE))
+
+struct sr200pc20m_regs {
+	struct sr200pc20m_regset_table ev[GET_EV_INDEX(EV_MAX_V4L2)];
+	struct sr200pc20m_regset_table blur[BLUR_LEVEL_MAX];
+	/*struct sr200pc20m_regset_table capture_size[SR200PC20M_CAPTURE_MAX];*/
+	struct sr200pc20m_regset_table preview_start;
+	struct sr200pc20m_regset_table capture_start;
+	struct sr200pc20m_regset_table fps[I_FPS_MAX];
+	struct sr200pc20m_regset_table init;
+	struct sr200pc20m_regset_table init_vt;
+	struct sr200pc20m_regset_table init_vt_wifi;
+	struct sr200pc20m_regset_table init_recording;
+	struct sr200pc20m_regset_table get_light_level;
+	struct sr200pc20m_regset_table stream_stop;
+	struct sr200pc20m_regset_table dtp_on;
+	struct sr200pc20m_regset_table dtp_off;
+};
+
+/*
+ * Driver information
+ */
+struct sr200pc20m_state {
+	struct v4l2_subdev sd;
+	struct sr200pc20m_platform_data *pdata;
+	/*
+	 * req_fmt is the requested format from the application.
+	 * set_fmt is the output format of the camera. Finally FIMC
+	 * converts the camera output(set_fmt) to the requested format
+	 * with hardware scaler.
+	 */
+	struct v4l2_pix_format req_fmt;
+	struct sr200pc20m_framesize default_frmsizes;
+	struct sr200pc20m_framesize preview_frmsizes;
+	struct sr200pc20m_framesize capture_frmsizes;
+	struct sr200pc20m_exif exif;
+	struct sr200pc20m_stream_time stream_time;
+	const struct sr200pc20m_regs *regs;
+	struct mutex ctrl_lock;
+
+	enum v4l2_sensor_mode sensor_mode;
+	s32 vt_mode;
+	s32 req_fps;
+	s32 fps;
+	u8 *dbg_level;
+
+	u32 check_dataline:1;
+	u32 need_wait_streamoff:1;
+	u32 first_preview:1;
+	u32 initialized:1;
+};
+
+static inline struct sr200pc20m_state *to_state(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct sr200pc20m_state, sd);
+}
+
+static inline void debug_msleep(struct v4l2_subdev *sd, u32 msecs)
+{
+	cam_dbg("delay for %dms\n", msecs);
+	msleep(msecs);
+}
+
+/*********** Sensor specific ************/
+#define DELAY_SEQ               0xFF
+#define SR200PC20M_CHIP_ID	0x92
+
+#ifdef CONFIG_LOAD_FILE
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+struct test {
+	u8 data;
+	struct test *nextBuf;
+};
+static struct test *testBuf;
+static s32 large_file;
+
+#define TEST_INIT	\
+{			\
+	.data = 0;	\
+	.nextBuf = NULL;	\
+}
+#if 0
+#define dbg_setfile(fmt, ...)	\
+	printk(KERN_ERR TAG_NAME fmt, ##__VA_ARGS__)
+#else
+#define dbg_setfile(fmt, ...)
+#endif				/* 0 */
+
+#ifdef CONFIG_MACH_S2PLUS
+#define TUNING_FILE_PATH "/mnt/sdcard/sr200pc20m_regs-s2plus.h"
+#else
+#define TUNING_FILE_PATH "/mnt/sdcard/sr200pc20m_regs.h"
+#endif				/* CONFIG_VIDEO_SR200PC20M */
+
+#endif				/* CONFIG_LOAD_FILE */
+
+#ifdef CONFIG_MACH_S2PLUS
+#include  "sr200pc20m_regs-s2plus.h"
+#else
+#include  "sr200pc20m_regs.h"
+#endif
+
+#endif				/* __SR200PC20M_H */
diff --git a/drivers/media/video/sr200pc20m_regs-s2plus.h b/drivers/media/video/sr200pc20m_regs-s2plus.h
new file mode 100644
index 0000000..b2b18f3
--- /dev/null
+++ b/drivers/media/video/sr200pc20m_regs-s2plus.h
@@ -0,0 +1,4168 @@
+/*
+ * Driver for SR200PC20M 2M ISP from Samsung
+ * Latest version: 11/11/23
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: DongSeong Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __SR200PC20M_REGS_H
+#define __SR200PC20M_REGS_H
+
+#include <linux/types.h>
+
+/*
+ * sr200pc20m register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name: SR200PC20M Initial Setfile
+* PLL mode: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by: ZEROHOY
+* Date: 2011.03.07
+* History:
+*******************************************************/
+regs_short_t front_init_regs[] = {
+/* Self-Cam -continuous*/
+/* CAMERA INITIAL for Self Camera(Variable Frame)*/
+
+{0x01, 0xf9},/* sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/* sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/* page 20 */
+{0x10, 0x0c},/* AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/* page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/* Initial Start */
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x11},/* Vsync Active High B:[3] , Sub1/2 + Preview 1mode */
+{0x11, 0x90},
+{0x12, 0x04},/* Pclk Falling Edge B:[2] *//* 1016 0x04->0x00 */
+
+{0x0b, 0xaa},/* ESD Check Register */
+{0x0c, 0xaa},/* ESD Check Register */
+{0x0d, 0xaa},/* ESD Check Register */
+
+{0x20, 0x00},
+{0x21, 0x02},/* modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/* modify 20110929 0x14->0x0a */
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/* Hblank_360 */
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x44},/* Flick Stop 60hz */
+{0x44, 0x09},/* VSCLIP */
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0f},/* BLC_TIME_TH_ON */
+{0x91, 0x0f},/* BLC_TIME_TH_OFF */
+{0x92, 0xd8},/* BLC_AG_TH_ON */
+{0x93, 0xd0},/* BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/* Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/* Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30},/* CLAMP */
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/* For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/* 20110826 Ãß°¡ */
+{0x52, 0x01},/* 0x03 --> 0x01 */
+{0x53, 0xc1},/* 20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0f},/* DCDC_TIME_TH_ON */
+{0xd5, 0x0f},/* DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/* DCDC_AG_TH_ON */
+{0xd7, 0xd0},/* DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY 03 00 */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02},/* For Preview */
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a},/* 77 */
+{0x62, 0x72},/* 77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/* 8a */
+{0x6b, 0x84},/* 74 */
+{0x6c, 0x7a},/* 7e */
+{0x6d, 0x80},/* 8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0f},
+{0x46, 0x0c},
+{0x47, 0x0b},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x88},
+{0x49, 0x2c},
+{0x4a, 0x80},
+{0x4b, 0x0f},
+{0x4c, 0x0c},
+{0x4d, 0x0b},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x23},
+{0x50, 0x80},
+{0x51, 0x0f},
+{0x52, 0x0c},
+{0x53, 0x0c},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+
+{0x25, 0x00},/* 0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x50},
+{0x54, 0xa8},
+{0x55, 0xa8},
+{0x56, 0xb0},
+{0x57, 0x7b},
+
+/*Dark2 th*/
+{0x58, 0xa0},
+{0x59, 0x40},
+{0x5a, 0xb8},
+{0x5b, 0xb8},
+{0x5c, 0xc8},
+{0x5d, 0x7b},
+
+/*Dark3 th*/
+{0x5e, 0x9c},
+{0x5f, 0x40},
+{0x60, 0xc0},
+{0x61, 0xc0},
+{0x62, 0xc8},
+{0x63, 0x7b},
+
+{0x70, 0x15},
+{0x71, 0x01},/* Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/* Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00},/* For Preview */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+/*only for Preview DPC*/
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+/*only for Preview DPC*/
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+/*only for Preview DPC*/
+{0xd7, 0xff},
+
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/* 55->48 */
+{0xc6, 0x2a},/* 48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+
+{0x03, 0x13},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x09},
+{0x63, 0x09},
+{0x64, 0x09},
+{0x65, 0x07},
+{0x66, 0x07},
+{0x67, 0x07},
+
+/*Dark2 Edge*/
+{0x68, 0x08},
+{0x69, 0x08},
+{0x6a, 0x08},
+{0x6b, 0x06},
+{0x6c, 0x06},
+{0x6d, 0x06},
+
+/*Dark3 Edge*/
+{0x6e, 0x08},
+{0x6f, 0x08},
+{0x70, 0x08},
+{0x71, 0x06},
+{0x72, 0x06},
+{0x73, 0x06},
+
+/*2DY*/
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80},/* X */
+{0x21, 0x80},/* Y */
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/* 2d */
+{0x60, 0x22},/* 26 */
+{0x70, 0x26},/* 2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46},/* CMCOFSGH */
+{0x15, 0x36},/* CMCOFSGM */
+{0x16, 0x26},/* CMCOFSGL */
+{0x17, 0x2f},/* CMC SIGN */
+
+ /*CMC*/ {0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x58},
+{0x20, 0x05},
+{0x21, 0x00},
+{0x22, 0x01},
+{0x23, 0xe0},
+{0x24, 0x00},
+{0x25, 0x04},
+{0x26, 0x00},
+{0x27, 0x04},
+{0x28, 0x05},
+{0x29, 0x04},
+{0x2a, 0x01},
+{0x2b, 0xe4},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x46},
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d},/* 20100305 ad->0d */
+{0x2a, 0xff},
+{0x2b, 0xf4},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70},/* 6c */
+{0x71, 0x82},/* 82(+8) */
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},/* 24 */
+{0x79, 0x48},/* Y Target 70 => 25, 72 => 26 */
+{0x7a, 0x23},/* 23 */
+{0x7b, 0x22},/* 22 */
+{0x7d, 0x23},
+
+{0x83, 0x01},/* EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01},/* EXPMin 6000.00 fps */
+{0x87, 0xf4},
+
+{0x88, 0x05},/* EXP Max 8.00 fps */
+{0x89, 0xb8},
+{0x8a, 0xd8},
+
+{0x8B, 0x75},/* EXP100, PLLx2 Mclk24 */
+{0x8C, 0x30},
+
+{0x8D, 0x61},/* EXP120, PLLx2 Mclk24 */
+{0x8E, 0xa8},
+
+{0x98, 0x9d},
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17},/* EXP Limit 500.00 fps, PLLx2 Mclk24 */
+{0x9d, 0x70},
+
+{0x9e, 0x01},/* EXP Unit, PLLx2 Mclk24 */
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},/* Low On */
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500,  7f New Lock Cond & New light stable */
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/* 33 */
+{0x42, 0x22},/* 22 */
+{0x43, 0xf0},/* f6 */
+{0x44, 0x44},/* 44 */
+{0x45, 0x44},/* 33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/* 3a */
+
+{0x83, 0x5e},/* 5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/* 24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/* 38 */
+{0x8a, 0x29},/* 2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/* 2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/* 1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/* 0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+/*0x17cc*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:0x02, 48MHz:0x03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x0a},/* NEED Delay 100ms */
+};
+
+/*==================================================*/
+/* CAMERA INITIAL for Self Recording 24 Fixed Frame */
+/*==================================================*/
+regs_short_t front_init_recording_regs[] = {
+/* Recording 25fps Anti-Flicker 60Hz END of Initial */
+/* CAMERA INITIAL for Self Recording 24 Fixed Frame */
+{0x01, 0xf9},/*sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/*sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/*page 20 */
+{0x10, 0x0c},/*AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/*page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/*Initial Start*/
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x03},/* Vsync Active High B:[3] , Sub1/2 + Preview 1 */
+{0x11, 0x94},
+{0x12, 0x04},/* Pclk Falling Edge B:[2]  1016 0x04->0x00 */
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/*Hblank 352 */
+{0x41, 0x60},
+{0x42, 0x00},/*Vblank 20 */
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x05},/*BLC_TIME_TH_ON */
+{0x91, 0x05},/*BLC_TIME_TH_OFF */
+{0x92, 0xb0},/*BLC_AG_TH_ON */
+{0x93, 0xa8},/*BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/*Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/*Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, /*CLAMP*/ {0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/*For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/*20110826 */
+{0x52, 0x01},/*0x03 --> 0x01 */
+{0x53, 0xc1},/*20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x05},/*DCDC_TIME_TH_ON */
+{0xd5, 0x05},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xb0},/*DCDC_AG_TH_ON */
+{0xd7, 0xa8},/*DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00},/*Setting For Camcorder 24 */
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x67},/*Setting For Camcorder 24 */
+{0x61, 0x7a},/*77 */
+{0x62, 0x79},/*77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/*8a */
+{0x6b, 0x84},/*74 */
+{0x6c, 0x7a},/*7e */
+{0x6d, 0x80},/*8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+{0x20, 0x0f},/*Setting For Camcorder 24 */
+{0x21, 0x0f},/*Setting For Camcorder 24 */
+
+{0x25, 0x00},/*0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+/*Dark2 th*/
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+/*Dark3 th*/
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01},/*Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/*Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d},/*Setting For Camcorder 24 */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/*55->48 */
+{0xc6, 0x2a},/*48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+{0x03, 0x13},
+/*Edge*/
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+/*Dark2 Edge*/
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+/*Dark3 Edge*/
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+/*2DY*/
+{0x80, 0xfd},/*Setting For Camcorder 24 */
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80}, /*X*/ {0x21, 0x80}, /*Y*/ {0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/*2d */
+{0x60, 0x22},/*26 */
+{0x70, 0x26},/*2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46}, /*CMCOFSGH*/
+{0x15, 0x36}, /*CMCOFSGM*/
+{0x16, 0x26}, /*CMCOFSGL*/
+{0x17, 0x2f}, /*CMC SIGN */
+
+/*CMC*/
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x1c},
+{0x73, 0x32},
+{0x74, 0x54},
+{0x75, 0x70},
+{0x76, 0x87},
+{0x77, 0x9a},
+{0x78, 0xaa},
+{0x79, 0xb9},
+{0x7a, 0xc4},
+{0x7b, 0xcf},
+{0x7c, 0xd8},
+{0x7d, 0xe0},
+{0x7e, 0xe9},
+{0x7f, 0xf0},
+{0x80, 0xf7},
+{0x81, 0xfc},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x58},
+{0x20, 0x02},
+{0x21, 0x80},
+{0x22, 0x01},
+{0x23, 0xe0},
+{0x24, 0x00},
+{0x25, 0x03},
+{0x26, 0x00},
+{0x27, 0x04},
+{0x28, 0x02},
+{0x29, 0x83},
+{0x2a, 0x01},
+{0x2b, 0xe4},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x25},
+
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d},/*20100305 ad->0d */
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},
+{0x79, 0x49},
+{0x7a, 0x23},
+{0x7b, 0x22},
+{0x7d, 0x23},
+
+{0x83, 0x01},/*EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0x78},
+
+{0x86, 0x01},/*EXPMin 10204.08 fps */
+{0x87, 0x26},
+
+{0x88, 0x01},/*EXP Max 24.00 fps */
+{0x89, 0xe8},
+{0x8a, 0x16},
+
+{0x8B, 0x75},/*EXP100 */
+{0x8C, 0x24},
+
+{0x8D, 0x61},/*EXP120 */
+{0x8E, 0x9e},
+
+{0x91, 0x01},/*EXP Fix 23.93 fps */
+{0x92, 0xe9},
+{0x93, 0xcf},
+
+{0x98, 0x9d},/*9d */
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x0e},/*EXP Limit 784.93 fps */
+{0x9d, 0xee},
+
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0x26},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xb8},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500, 7f New Lock Cond & New light stable*/
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/*33 */
+{0x42, 0x22},/*22 */
+{0x43, 0xf0},/*f6 */
+{0x44, 0x44},/*44 */
+{0x45, 0x44},/*33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/*3a */
+
+{0x83, 0x5e},/*5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/*24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/*38 */
+{0x8a, 0x29},/*2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/*2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/*1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/*0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x81},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0c},
+{0x1d, 0x0f},
+{0x1e, 0x05},
+{0x1f, 0x05},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x03},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x03},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x11, 0x94},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+/*============================================================*/
+/* CAMERA INITIAL for VT Preview 15 Fixed Frame (VGA SETTING) */
+/*============================================================*/
+regs_short_t front_init_vt_regs[] = {
+/* SKT-VT - continuous */
+{0x01, 0xf9},/* sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/* sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/* page 20 */
+{0x10, 0x0c},/* AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/* page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/* Initial Start */
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x10},/* Vsync Active High B:[3] , Sub1/2mode */
+{0x11, 0x94},
+{0x12, 0x04},/* Pclk Falling Edge B:[2] */
+
+{0x0b, 0xaa},/* ESD Check Register */
+{0x0c, 0xaa},/* ESD Check Register */
+{0x0d, 0xaa},/* ESD Check Register */
+
+{0x20, 0x00},
+{0x21, 0x0a},/* modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/* modify 20110929 0x14->0x0a */
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/* Hblank_360 */
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x44},/* Flick Stop 60hz */
+{0x44, 0x09},/* VSCLIP */
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0e},/* BLC_TIME_TH_ON */
+{0x91, 0x0e},/* BLC_TIME_TH_OFF */
+{0x92, 0xd8},/* BLC_AG_TH_ON */
+{0x93, 0xd0},/* BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/* Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/* Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30},/* CLAMP */
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/* For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/* 20110826 Ãß°¡ */
+{0x52, 0x01},/* 0x03 --> 0x01 */
+{0x53, 0xc1},/* 20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0e},/* DCDC_TIME_TH_ON */
+{0xd5, 0x0e},/* DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/* DCDC_AG_TH_ON */
+{0xd7, 0xd0},/* DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02},/* For Preview */
+
+{0x40, 0x80},
+{0x41, 0x2c},
+
+{0x60, 0x6b},
+{0x61, 0x7a},/* 77 */
+{0x62, 0x72},/* 77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/* 8a */
+{0x6b, 0x84},/* 74 */
+{0x6c, 0x7a},/* 7e */
+{0x6d, 0x80},/* 8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0f},
+{0x46, 0x0c},
+{0x47, 0x0b},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x88},
+{0x49, 0x2c},
+{0x4a, 0x80},
+{0x4b, 0x0f},
+{0x4c, 0x0c},
+{0x4d, 0x0b},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x23},
+{0x50, 0x80},
+{0x51, 0x0f},
+{0x52, 0x0c},
+{0x53, 0x0c},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+
+{0x25, 0x00},/* 0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x50},
+{0x54, 0xa8},
+{0x55, 0xa8},
+{0x56, 0xb0},
+{0x57, 0x7b},
+
+/*Dark2 th*/
+{0x58, 0xa0},
+{0x59, 0x40},
+{0x5a, 0xb8},
+{0x5b, 0xb8},
+{0x5c, 0xc8},
+{0x5d, 0x7b},
+
+/*Dark3 th*/
+{0x5e, 0x9c},
+{0x5f, 0x40},
+{0x60, 0xc0},
+{0x61, 0xc0},
+{0x62, 0xc8},
+{0x63, 0x7b},
+
+{0x70, 0x15},
+{0x71, 0x01},/* Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/* Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d},/* For SK VT */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+/*only For SK VT */
+{0xD2, 0x67},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+/*only For SK VT */
+{0xd5, 0x02},
+
+{0xD6, 0xff},
+
+/*only For SK VT */
+{0xd7, 0x18},
+
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/* 55->48 */
+{0xc6, 0x2a},/* 48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+{0x03, 0x13},
+/*Edge*/
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x09},
+{0x63, 0x09},
+{0x64, 0x09},
+{0x65, 0x07},
+{0x66, 0x07},
+{0x67, 0x07},
+
+/*Dark2 Edge*/
+{0x68, 0x08},
+{0x69, 0x08},
+{0x6a, 0x08},
+{0x6b, 0x06},
+{0x6c, 0x06},
+{0x6d, 0x06},
+
+/*Dark3 Edge*/
+{0x6e, 0x08},
+{0x6f, 0x08},
+{0x70, 0x08},
+{0x71, 0x06},
+{0x72, 0x06},
+{0x73, 0x06},
+
+/*2DY*/
+{0x80, 0xfd},/*only For SK VT */
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80},/* X */
+{0x21, 0x80},/* Y */
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/* 2d */
+{0x60, 0x22},/* 26 */
+{0x70, 0x26},/* 2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46},/* CMCOFSGH */
+{0x15, 0x36},/* CMCOFSGM */
+{0x16, 0x26},/* CMCOFSGL */
+{0x17, 0x2f},/* CMC SIGN */
+
+ /*CMC*/ {0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x98},
+{0x20, 0x05},
+{0x21, 0x00},
+{0x22, 0x03},
+{0x23, 0xc0},
+{0x24, 0x00},
+{0x25, 0x04},
+{0x26, 0x00},
+{0x27, 0x08},
+{0x28, 0x05},
+{0x29, 0x04},
+{0x2a, 0x03},
+{0x2b, 0xc8},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x46},
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x04},
+
+{0x28, 0xef},
+{0x29, 0x0d},/* 20100305 ad->0d */
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70},/* 6c */
+{0x71, 0x82},/* 82(+8) */
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},/* 24 */
+{0x79, 0x48},/* Y Target 70 => 25, 72 => 26 */
+{0x7a, 0x23},/* 23 */
+{0x7b, 0x22},/* 22 */
+{0x7d, 0x23},
+
+{0x83, 0x01},/* EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01},/* EXPMin 6000.00 fps */
+{0x87, 0xf4},
+
+{0x88, 0x05},/* EXP Max 8.57 fps */
+{0x89, 0x57},
+{0x8a, 0x30},
+
+{0x8B, 0x75},/* EXP100, PLLx2 Mclk24 */
+{0x8C, 0x30},
+
+{0x8D, 0x61},/* EXP120, PLLx2 Mclk24 */
+{0x8E, 0xa8},
+
+{0x91, 0x05},/* EXP Fix 8.00 fps */
+{0x92, 0xb8},
+{0x93, 0xd8},
+
+{0x98, 0x9d},
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17},/* EXP Limit 500.00 fps, PLLx2 Mclk24 */
+{0x9d, 0x70},
+
+{0x9e, 0x01},/* EXP Unit, PLLx2 Mclk24 */
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},/* Low On */
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500,  7f New Lock Cond & New light stable */
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/* 33 */
+{0x42, 0x22},/* 22 */
+{0x43, 0xf0},/* f6 */
+{0x44, 0x44},/* 44 */
+{0x45, 0x44},/* 33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/* 3a */
+
+{0x83, 0x5e},/* 5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/* 24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/* 38 */
+{0x8a, 0x29},/* 2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/* 2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/* 1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/* 0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x01 -> 0x00 not Continues */
+/*0x17cc*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},/* NEED Delay 400ms */
+};
+
+regs_short_t front_preview_camera_regs[] = {
+{0x03, 0x00},/*Sleep On */
+{0x01, 0xf9},
+
+{0x03, 0x20},/*page 20 */
+{0x18, 0x30},/*for Preview */
+{0x10, 0x0c},/*AE off 60hz */
+
+{0x03, 0x22},/*page 22 */
+{0x10, 0x69},/*awb off */
+
+{0x03, 0x00},
+{0x10, 0x11},
+
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x02},/*modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/*modify 20110929 0x14->0x0a */
+
+{0x42, 0x00},/*VBlank */
+{0x43, 0x44},/*68 */
+
+/*Page10*/
+{0x03, 0x10},
+{0x3f, 0x02},
+{0x60, 0x6b},
+
+/*Page12*/
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+{0x90, 0x00},
+
+/*only for Preview DPC */
+{0xd2, 0x17},
+{0xd5, 0x0f},
+{0xd7, 0xff},
+
+/*Page13*/
+{0x03, 0x13},
+{0x80, 0x00},
+
+/*Page18*/
+{0x03, 0x18},
+{0x10, 0x07},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+/*0x17cc,*/ /*MHSHIM*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x01},
+{0x36, 0x03},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},/*AWB ON */
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},/*Sleep Off */
+{0x01, 0xf8},
+
+{0xff, 0x28},/*400ms */
+};
+
+regs_short_t front_snapshot_normal_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+
+{0x03, 0x22},/*Page 22 */
+{0x10, 0x69},/*AWB Off */
+
+{0x03, 0x00},
+{0x10, 0x00},
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x0a},/*modify 20110929 0x0c->0x0a */
+{0x22, 0x00},
+{0x23, 0x0a},/*modify 20110929 0x14->0x0a */
+
+/*Page10*/
+{0x03, 0x10},
+{0x3f, 0x00},
+{0x60, 0x67},
+
+/*Page12*/
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+{0x90, 0x5d},
+
+/*only for Preview DPC Off*/
+{0xd2, 0x67},
+{0xd5, 0x02},
+{0xd7, 0x18},
+
+/*Page13*/
+{0x03, 0x13},
+{0x80, 0xfd},
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x00},/* Scaling Off */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x81},
+{0x70, 0x85},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0c},
+{0x1d, 0x0f},
+{0x1e, 0x05},
+{0x1f, 0x05},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x80},/*1600x1200 MiPi OutPut */
+{0x31, 0x0c},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x03},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x03},/*drivability 24MHZ:02, 48MHz:03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/*Page0*/
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},/*Sleep Off */
+
+{0xff, 0x03},/*Increase from 30ms */
+};
+
+regs_short_t front_ev_minus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0xd0},
+};
+
+regs_short_t front_ev_minus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0xc0},
+};
+
+regs_short_t front_ev_minus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0xb0},
+};
+
+regs_short_t front_ev_minus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0xa0},
+};
+
+regs_short_t front_ev_default_regs[] = {
+{0x03, 0x10},
+{0x40, 0x00},
+};
+
+regs_short_t front_ev_plus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0x20},
+};
+
+regs_short_t front_ev_plus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0x30},
+};
+
+regs_short_t front_ev_plus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0x40},
+};
+
+regs_short_t front_ev_plus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_default[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_1[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_2[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_3[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_fps_auto_regs[] = {
+};
+
+regs_short_t front_fps_7_regs[] = {
+/* Fixed 7fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x11},/*BLC_TIME_TH_ON */
+{0x91, 0x11},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x11},/*DCDC_TIME_TH_ON */
+{0xd5, 0x11},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x06},/*EXP Max 7.06 fps */
+{0x89, 0x7c},
+{0x8a, 0x28},
+
+{0x91, 0x06},/*EXP Fix 07.00 fps */
+{0x92, 0x89},
+{0x93, 0xd4},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_fps_10_regs[] = {
+/*  Fixed 10fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x0b},/*BLC_TIME_TH_ON */
+{0x91, 0x0b},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x0b},/*DCDC_TIME_TH_ON */
+{0xd5, 0x0b},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x04},/*EXP Max 10.91 fps */
+{0x89, 0x32},
+{0x8a, 0x38},
+
+{0x91, 0x04},/*EXP Fix 10.00 fps */
+{0x92, 0x93},
+{0x93, 0xe0},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_fps_15_regs[] = {
+/* Fixed 15fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x08},/*BLC_TIME_TH_ON */
+{0x91, 0x08},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x08},/*DCDC_TIME_TH_ON */
+{0xd5, 0x08},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x03},/*EXP Max 15.00 fps */
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x91, 0x03},/*EXP Fix 14.91 fps */
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+
+};
+
+regs_short_t front_fps_24_regs[] = {
+/* Need to add Fixed 24fps Mode */
+/* Temporary setting, Fixed 15fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x08},/*BLC_TIME_TH_ON */
+{0x91, 0x08},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x08},/*DCDC_TIME_TH_ON */
+{0xd5, 0x08},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x03},/*EXP Max 15.00 fps */
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x91, 0x03},/*EXP Fix 14.91 fps */
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP->HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_pattern_on_regs[] = {
+{0x03, 0x00},
+{0x50, 0x05},
+};
+
+regs_short_t front_pattern_off_regs[] = {
+{0x03, 0x00},
+{0x50, 0x00},
+};
+
+#endif/* __SR200PC20M_REGS_H */
diff --git a/drivers/media/video/sr200pc20m_regs.h b/drivers/media/video/sr200pc20m_regs.h
new file mode 100644
index 0000000..b2b18f3
--- /dev/null
+++ b/drivers/media/video/sr200pc20m_regs.h
@@ -0,0 +1,4168 @@
+/*
+ * Driver for SR200PC20M 2M ISP from Samsung
+ * Latest version: 11/11/23
+ *
+ * Copyright (c) 2011, Samsung Electronics. All rights reserved
+ * Author: DongSeong Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __SR200PC20M_REGS_H
+#define __SR200PC20M_REGS_H
+
+#include <linux/types.h>
+
+/*
+ * sr200pc20m register configuration for combinations of initialization
+ */
+/* 2M mipi setting-common from PARTRON */
+/*******************************************************
+* Name: SR200PC20M Initial Setfile
+* PLL mode: MCLK=24MHz / SYSCLK=28MHz / PCLK=48MHz
+* FPS: VGA 7.5~15fps / UXGA 7.5fps / recording 25fps
+* Made by: ZEROHOY
+* Date: 2011.03.07
+* History:
+*******************************************************/
+regs_short_t front_init_regs[] = {
+/* Self-Cam -continuous*/
+/* CAMERA INITIAL for Self Camera(Variable Frame)*/
+
+{0x01, 0xf9},/* sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/* sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/* page 20 */
+{0x10, 0x0c},/* AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/* page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/* Initial Start */
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x11},/* Vsync Active High B:[3] , Sub1/2 + Preview 1mode */
+{0x11, 0x90},
+{0x12, 0x04},/* Pclk Falling Edge B:[2] *//* 1016 0x04->0x00 */
+
+{0x0b, 0xaa},/* ESD Check Register */
+{0x0c, 0xaa},/* ESD Check Register */
+{0x0d, 0xaa},/* ESD Check Register */
+
+{0x20, 0x00},
+{0x21, 0x02},/* modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/* modify 20110929 0x14->0x0a */
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/* Hblank_360 */
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x44},/* Flick Stop 60hz */
+{0x44, 0x09},/* VSCLIP */
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0f},/* BLC_TIME_TH_ON */
+{0x91, 0x0f},/* BLC_TIME_TH_OFF */
+{0x92, 0xd8},/* BLC_AG_TH_ON */
+{0x93, 0xd0},/* BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/* Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/* Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30},/* CLAMP */
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/* For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/* 20110826 Ãß°¡ */
+{0x52, 0x01},/* 0x03 --> 0x01 */
+{0x53, 0xc1},/* 20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0f},/* DCDC_TIME_TH_ON */
+{0xd5, 0x0f},/* DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/* DCDC_AG_TH_ON */
+{0xd7, 0xd0},/* DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY 03 00 */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02},/* For Preview */
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x6b},
+{0x61, 0x7a},/* 77 */
+{0x62, 0x72},/* 77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/* 8a */
+{0x6b, 0x84},/* 74 */
+{0x6c, 0x7a},/* 7e */
+{0x6d, 0x80},/* 8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0f},
+{0x46, 0x0c},
+{0x47, 0x0b},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x88},
+{0x49, 0x2c},
+{0x4a, 0x80},
+{0x4b, 0x0f},
+{0x4c, 0x0c},
+{0x4d, 0x0b},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x23},
+{0x50, 0x80},
+{0x51, 0x0f},
+{0x52, 0x0c},
+{0x53, 0x0c},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+
+{0x25, 0x00},/* 0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x50},
+{0x54, 0xa8},
+{0x55, 0xa8},
+{0x56, 0xb0},
+{0x57, 0x7b},
+
+/*Dark2 th*/
+{0x58, 0xa0},
+{0x59, 0x40},
+{0x5a, 0xb8},
+{0x5b, 0xb8},
+{0x5c, 0xc8},
+{0x5d, 0x7b},
+
+/*Dark3 th*/
+{0x5e, 0x9c},
+{0x5f, 0x40},
+{0x60, 0xc0},
+{0x61, 0xc0},
+{0x62, 0xc8},
+{0x63, 0x7b},
+
+{0x70, 0x15},
+{0x71, 0x01},/* Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/* Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x00},/* For Preview */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+/*only for Preview DPC*/
+{0xD2, 0x17},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+/*only for Preview DPC*/
+{0xd5, 0x0f},
+
+{0xD6, 0xff},
+
+/*only for Preview DPC*/
+{0xd7, 0xff},
+
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/* 55->48 */
+{0xc6, 0x2a},/* 48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+
+{0x03, 0x13},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x09},
+{0x63, 0x09},
+{0x64, 0x09},
+{0x65, 0x07},
+{0x66, 0x07},
+{0x67, 0x07},
+
+/*Dark2 Edge*/
+{0x68, 0x08},
+{0x69, 0x08},
+{0x6a, 0x08},
+{0x6b, 0x06},
+{0x6c, 0x06},
+{0x6d, 0x06},
+
+/*Dark3 Edge*/
+{0x6e, 0x08},
+{0x6f, 0x08},
+{0x70, 0x08},
+{0x71, 0x06},
+{0x72, 0x06},
+{0x73, 0x06},
+
+/*2DY*/
+{0x80, 0x00},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80},/* X */
+{0x21, 0x80},/* Y */
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/* 2d */
+{0x60, 0x22},/* 26 */
+{0x70, 0x26},/* 2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46},/* CMCOFSGH */
+{0x15, 0x36},/* CMCOFSGM */
+{0x16, 0x26},/* CMCOFSGL */
+{0x17, 0x2f},/* CMC SIGN */
+
+ /*CMC*/ {0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x58},
+{0x20, 0x05},
+{0x21, 0x00},
+{0x22, 0x01},
+{0x23, 0xe0},
+{0x24, 0x00},
+{0x25, 0x04},
+{0x26, 0x00},
+{0x27, 0x04},
+{0x28, 0x05},
+{0x29, 0x04},
+{0x2a, 0x01},
+{0x2b, 0xe4},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x46},
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d},/* 20100305 ad->0d */
+{0x2a, 0xff},
+{0x2b, 0xf4},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70},/* 6c */
+{0x71, 0x82},/* 82(+8) */
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},/* 24 */
+{0x79, 0x48},/* Y Target 70 => 25, 72 => 26 */
+{0x7a, 0x23},/* 23 */
+{0x7b, 0x22},/* 22 */
+{0x7d, 0x23},
+
+{0x83, 0x01},/* EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01},/* EXPMin 6000.00 fps */
+{0x87, 0xf4},
+
+{0x88, 0x05},/* EXP Max 8.00 fps */
+{0x89, 0xb8},
+{0x8a, 0xd8},
+
+{0x8B, 0x75},/* EXP100, PLLx2 Mclk24 */
+{0x8C, 0x30},
+
+{0x8D, 0x61},/* EXP120, PLLx2 Mclk24 */
+{0x8E, 0xa8},
+
+{0x98, 0x9d},
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17},/* EXP Limit 500.00 fps, PLLx2 Mclk24 */
+{0x9d, 0x70},
+
+{0x9e, 0x01},/* EXP Unit, PLLx2 Mclk24 */
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},/* Low On */
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500,  7f New Lock Cond & New light stable */
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/* 33 */
+{0x42, 0x22},/* 22 */
+{0x43, 0xf0},/* f6 */
+{0x44, 0x44},/* 44 */
+{0x45, 0x44},/* 33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/* 3a */
+
+{0x83, 0x5e},/* 5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/* 24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/* 38 */
+{0x8a, 0x29},/* 2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/* 2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/* 1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/* 0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+/*0x17cc*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:0x02, 48MHz:0x03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x0a},/* NEED Delay 100ms */
+};
+
+/*==================================================*/
+/* CAMERA INITIAL for Self Recording 24 Fixed Frame */
+/*==================================================*/
+regs_short_t front_init_recording_regs[] = {
+/* Recording 25fps Anti-Flicker 60Hz END of Initial */
+/* CAMERA INITIAL for Self Recording 24 Fixed Frame */
+{0x01, 0xf9},/*sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/*sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/*page 20 */
+{0x10, 0x0c},/*AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/*page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/*Initial Start*/
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x03},/* Vsync Active High B:[3] , Sub1/2 + Preview 1 */
+{0x11, 0x94},
+{0x12, 0x04},/* Pclk Falling Edge B:[2]  1016 0x04->0x00 */
+
+{0x0b, 0xaa},
+{0x0c, 0xaa},
+{0x0d, 0xaa},
+
+{0x20, 0x00},
+{0x21, 0x04},
+{0x22, 0x00},
+{0x23, 0x06},
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/*Hblank 352 */
+{0x41, 0x60},
+{0x42, 0x00},/*Vblank 20 */
+{0x43, 0x14},
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x05},/*BLC_TIME_TH_ON */
+{0x91, 0x05},/*BLC_TIME_TH_OFF */
+{0x92, 0xb0},/*BLC_AG_TH_ON */
+{0x93, 0xa8},/*BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/*Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/*Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, /*CLAMP*/ {0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/*For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/*20110826 */
+{0x52, 0x01},/*0x03 --> 0x01 */
+{0x53, 0xc1},/*20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x05},/*DCDC_TIME_TH_ON */
+{0xd5, 0x05},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xb0},/*DCDC_AG_TH_ON */
+{0xd7, 0xa8},/*DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00},/*Setting For Camcorder 24 */
+
+{0x40, 0x80},
+{0x41, 0x00},
+
+{0x60, 0x67},/*Setting For Camcorder 24 */
+{0x61, 0x7a},/*77 */
+{0x62, 0x79},/*77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/*8a */
+{0x6b, 0x84},/*74 */
+{0x6c, 0x7a},/*7e */
+{0x6d, 0x80},/*8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0c},
+{0x46, 0x09},
+{0x47, 0x06},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x80},
+{0x49, 0x18},
+{0x4a, 0x80},
+{0x4b, 0x0c},
+{0x4c, 0x09},
+{0x4d, 0x06},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x18},
+{0x50, 0x80},
+{0x51, 0x0c},
+{0x52, 0x09},
+{0x53, 0x06},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+{0x20, 0x0f},/*Setting For Camcorder 24 */
+{0x21, 0x0f},/*Setting For Camcorder 24 */
+
+{0x25, 0x00},/*0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x40},
+{0x54, 0x90},
+{0x55, 0x90},
+{0x56, 0xa0},
+{0x57, 0x78},
+
+/*Dark2 th*/
+{0x58, 0xb0},
+{0x59, 0x40},
+{0x5a, 0x90},
+{0x5b, 0x90},
+{0x5c, 0xa0},
+{0x5d, 0x78},
+
+/*Dark3 th*/
+{0x5e, 0xb0},
+{0x5f, 0x40},
+{0x60, 0x90},
+{0x61, 0x90},
+{0x62, 0xa0},
+{0x63, 0x78},
+
+{0x70, 0x15},
+{0x71, 0x01},/*Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/*Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d},/*Setting For Camcorder 24 */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/*55->48 */
+{0xc6, 0x2a},/*48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+{0x03, 0x13},
+/*Edge*/
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x0a},
+{0x63, 0x0b},
+{0x64, 0x0a},
+{0x65, 0x08},
+{0x66, 0x09},
+{0x67, 0x08},
+
+/*Dark2 Edge*/
+{0x68, 0x0a},
+{0x69, 0x0b},
+{0x6a, 0x0a},
+{0x6b, 0x08},
+{0x6c, 0x09},
+{0x6d, 0x08},
+
+/*Dark3 Edge*/
+{0x6e, 0x0a},
+{0x6f, 0x0b},
+{0x70, 0x0a},
+{0x71, 0x08},
+{0x72, 0x09},
+{0x73, 0x08},
+
+/*2DY*/
+{0x80, 0xfd},/*Setting For Camcorder 24 */
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80}, /*X*/ {0x21, 0x80}, /*Y*/ {0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/*2d */
+{0x60, 0x22},/*26 */
+{0x70, 0x26},/*2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46}, /*CMCOFSGH*/
+{0x15, 0x36}, /*CMCOFSGM*/
+{0x16, 0x26}, /*CMCOFSGL*/
+{0x17, 0x2f}, /*CMC SIGN */
+
+/*CMC*/
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x1c},
+{0x73, 0x32},
+{0x74, 0x54},
+{0x75, 0x70},
+{0x76, 0x87},
+{0x77, 0x9a},
+{0x78, 0xaa},
+{0x79, 0xb9},
+{0x7a, 0xc4},
+{0x7b, 0xcf},
+{0x7c, 0xd8},
+{0x7d, 0xe0},
+{0x7e, 0xe9},
+{0x7f, 0xf0},
+{0x80, 0xf7},
+{0x81, 0xfc},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x58},
+{0x20, 0x02},
+{0x21, 0x80},
+{0x22, 0x01},
+{0x23, 0xe0},
+{0x24, 0x00},
+{0x25, 0x03},
+{0x26, 0x00},
+{0x27, 0x04},
+{0x28, 0x02},
+{0x29, 0x83},
+{0x2a, 0x01},
+{0x2b, 0xe4},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x25},
+
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00},
+
+{0x28, 0xef},
+{0x29, 0x0d},/*20100305 ad->0d */
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x7a},
+{0x71, 0x80},
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},
+{0x79, 0x49},
+{0x7a, 0x23},
+{0x7b, 0x22},
+{0x7d, 0x23},
+
+{0x83, 0x01},/*EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0x78},
+
+{0x86, 0x01},/*EXPMin 10204.08 fps */
+{0x87, 0x26},
+
+{0x88, 0x01},/*EXP Max 24.00 fps */
+{0x89, 0xe8},
+{0x8a, 0x16},
+
+{0x8B, 0x75},/*EXP100 */
+{0x8C, 0x24},
+
+{0x8D, 0x61},/*EXP120 */
+{0x8E, 0x9e},
+
+{0x91, 0x01},/*EXP Fix 23.93 fps */
+{0x92, 0xe9},
+{0x93, 0xcf},
+
+{0x98, 0x9d},/*9d */
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x0e},/*EXP Limit 784.93 fps */
+{0x9d, 0xee},
+
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0x26},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xb8},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500, 7f New Lock Cond & New light stable*/
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/*33 */
+{0x42, 0x22},/*22 */
+{0x43, 0xf0},/*f6 */
+{0x44, 0x44},/*44 */
+{0x45, 0x44},/*33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/*3a */
+
+{0x83, 0x5e},/*5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/*24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/*38 */
+{0x8a, 0x29},/*2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/*2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/*1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/*0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x81},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0c},
+{0x1d, 0x0f},
+{0x1e, 0x05},
+{0x1f, 0x05},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x03},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x03},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x11, 0x94},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+/*============================================================*/
+/* CAMERA INITIAL for VT Preview 15 Fixed Frame (VGA SETTING) */
+/*============================================================*/
+regs_short_t front_init_vt_regs[] = {
+/* SKT-VT - continuous */
+{0x01, 0xf9},/* sleep on */
+{0x01, 0xfb},/* sleep on */
+{0x01, 0xf9},/* sleep on */
+{0x08, 0x20},/* sleep on */
+{0x0a, 0x3f},/* sleep on */
+
+/* PAGE 20 */
+{0x03, 0x20},/* page 20 */
+{0x10, 0x0c},/* AE off 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},/* page 22 */
+{0x10, 0x69},/* AWB off */
+
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+
+{0x03, 0x13},
+{0x10, 0xcb},
+
+/* Initial Start */
+/* PAGE 0 START */
+{0x03, 0x00},
+{0x10, 0x10},/* Vsync Active High B:[3] , Sub1/2mode */
+{0x11, 0x94},
+{0x12, 0x04},/* Pclk Falling Edge B:[2] */
+
+{0x0b, 0xaa},/* ESD Check Register */
+{0x0c, 0xaa},/* ESD Check Register */
+{0x0d, 0xaa},/* ESD Check Register */
+
+{0x20, 0x00},
+{0x21, 0x0a},/* modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/* modify 20110929 0x14->0x0a */
+
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40},
+
+{0x28, 0x0c},
+{0x29, 0x04},
+{0x2a, 0x02},
+{0x2b, 0x04},
+{0x2c, 0x06},
+{0x2d, 0x02},
+
+{0x40, 0x01},/* Hblank_360 */
+{0x41, 0x68},
+{0x42, 0x00},
+{0x43, 0x44},/* Flick Stop 60hz */
+{0x44, 0x09},/* VSCLIP */
+
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+ /*BLC*/ {0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0e},/* BLC_TIME_TH_ON */
+{0x91, 0x0e},/* BLC_TIME_TH_OFF */
+{0x92, 0xd8},/* BLC_AG_TH_ON */
+{0x93, 0xd0},/* BLC_AG_TH_OFF */
+{0x94, 0xff},
+{0x95, 0xff},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+/*Dark BLC*/
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+/*Normal BLC*/
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+/*OutDoor  BLC*/
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+/* PAGE 0 END */
+
+/* PAGE 2 START */
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c},/* Double_AG */
+{0x19, 0x00},
+{0x1a, 0x39},/* Double_AG 38 ->39 */
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30},/* CLAMP */
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x00},
+{0x2f, 0x00},
+{0x30, 0x05},/* For Hi-253 never no change 0x05 */
+
+{0x50, 0x20},
+{0x51, 0x03},/* 20110826 Ãß°¡ */
+{0x52, 0x01},/* 0x03 --> 0x01 */
+{0x53, 0xc1},/* 20110818 Ãß°¡ */
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0e},/* DCDC_TIME_TH_ON */
+{0xd5, 0x0e},/* DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/* DCDC_AG_TH_ON */
+{0xd7, 0xd0},/* DCDC_AG_TH_OFF */
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+{0xf0, 0x01},
+{0xf1, 0x01},
+{0xf2, 0x01},
+{0xf3, 0x01},
+{0xf4, 0x01},
+
+/* PAGE 2 END */
+
+/* PAGE 3 */
+{0x03, 0x03},
+{0x10, 0x10},
+/* PAGE 3 END */
+
+/* PAGE 10 START */
+{0x03, 0x10},
+{0x10, 0x01},/* CrYCbY */
+{0x12, 0x30},
+{0x20, 0x00},
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x02},/* For Preview */
+
+{0x40, 0x80},
+{0x41, 0x2c},
+
+{0x60, 0x6b},
+{0x61, 0x7a},/* 77 */
+{0x62, 0x72},/* 77 */
+{0x63, 0x50},/* Double_AG 50->30 */
+{0x64, 0x80},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80},/* 8a */
+{0x6b, 0x84},/* 74 */
+{0x6c, 0x7a},/* 7e */
+{0x6d, 0x80},/* 8e */
+
+/* PAGE 11 START */
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a},/* Blue Max-Filter Delete */
+{0x13, 0xbb},
+
+{0x26, 0x31},/* Double_AG 31->20 */
+{0x27, 0x34},/* Double_AG 34->22 */
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+/*Out2 D-LPF th*/
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+/*Out1 D-LPF th*/
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x20},
+{0x3a, 0x1f},
+{0x3b, 0x03},
+
+/*Indoor D-LPF th*/
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0x80},
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+/*Dark1 D-LPF th*/
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0x80},
+{0x45, 0x0f},
+{0x46, 0x0c},
+{0x47, 0x0b},
+
+/*Dark2 D-LPF th*/
+{0x48, 0x88},
+{0x49, 0x2c},
+{0x4a, 0x80},
+{0x4b, 0x0f},
+{0x4c, 0x0c},
+{0x4d, 0x0b},
+
+/*Dark3 D-LPF th*/
+{0x4e, 0x80},
+{0x4f, 0x23},
+{0x50, 0x80},
+{0x51, 0x0f},
+{0x52, 0x0c},
+{0x53, 0x0c},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x18},
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+/* PAGE 11 END */
+
+/* PAGE 12 START */
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+
+{0x25, 0x00},/* 0x30 */
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+/*Out2 th*/
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+/*Out1 th*/
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xb0},
+{0x49, 0xb0},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+/*Indoor th*/
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+/*Dark1 th*/
+{0x52, 0xb0},
+{0x53, 0x50},
+{0x54, 0xa8},
+{0x55, 0xa8},
+{0x56, 0xb0},
+{0x57, 0x7b},
+
+/*Dark2 th*/
+{0x58, 0xa0},
+{0x59, 0x40},
+{0x5a, 0xb8},
+{0x5b, 0xb8},
+{0x5c, 0xc8},
+{0x5d, 0x7b},
+
+/*Dark3 th*/
+{0x5e, 0x9c},
+{0x5f, 0x40},
+{0x60, 0xc0},
+{0x61, 0xc0},
+{0x62, 0xc8},
+{0x63, 0x7b},
+
+{0x70, 0x15},
+{0x71, 0x01},/* Don't Touch register */
+
+{0x72, 0x18},
+{0x73, 0x01},/* Don't Touch register */
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d},/* For SK VT */
+
+/*Dont Touch register*/
+{0xD0, 0x0c},
+{0xD1, 0x80},
+
+/*only For SK VT */
+{0xD2, 0x67},
+
+{0xD3, 0x00},
+{0xD4, 0x00},
+
+/*only For SK VT */
+{0xd5, 0x02},
+
+{0xD6, 0xff},
+
+/*only For SK VT */
+{0xd7, 0x18},
+
+/*End*/
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+/*Dont Touch register*/
+{0xc5, 0x30},/* 55->48 */
+{0xc6, 0x2a},/* 48->40 */
+/* PAGE 12 END */
+
+/* PAGE 13 START */
+{0x03, 0x13},
+/*Edge*/
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+/*Low clip th*/
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+/*Out2 Edge*/
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+/*Out1 Edge*/
+{0x56, 0x0f},
+{0x57, 0x12},
+{0x58, 0x12},
+{0x59, 0x09},
+{0x5a, 0x0c},
+{0x5b, 0x0c},
+
+/*Indoor Edge*/
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+/*Dark1 Edge*/
+{0x62, 0x09},
+{0x63, 0x09},
+{0x64, 0x09},
+{0x65, 0x07},
+{0x66, 0x07},
+{0x67, 0x07},
+
+/*Dark2 Edge*/
+{0x68, 0x08},
+{0x69, 0x08},
+{0x6a, 0x08},
+{0x6b, 0x06},
+{0x6c, 0x06},
+{0x6d, 0x06},
+
+/*Dark3 Edge*/
+{0x6e, 0x08},
+{0x6f, 0x08},
+{0x70, 0x08},
+{0x71, 0x06},
+{0x72, 0x06},
+{0x73, 0x06},
+
+/*2DY*/
+{0x80, 0xfd},/*only For SK VT */
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+/*Out2*/
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+/*Out1*/
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+/*Indoor*/
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+/*Dark1*/
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+/*Dark2*/
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+/*Dark3*/
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+/* PAGE 13 END */
+
+/* PAGE 14 START */
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80},/* GX */
+{0x15, 0x80},/* GY */
+{0x16, 0x80},/* RX */
+{0x17, 0x80},/* RY */
+{0x18, 0x80},/* BX */
+{0x19, 0x80},/* BY */
+
+{0x20, 0x80},/* X */
+{0x21, 0x80},/* Y */
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x37},
+{0x50, 0x26},/* 2d */
+{0x60, 0x22},/* 26 */
+{0x70, 0x26},/* 2d */
+/* PAGE 14 END */
+
+/* PAGE 15 START */
+{0x03, 0x15},
+{0x10, 0x0f},
+
+/*Rstep H 16*/
+/*Rstep L 14*/
+{0x14, 0x46},/* CMCOFSGH */
+{0x15, 0x36},/* CMCOFSGM */
+{0x16, 0x26},/* CMCOFSGL */
+{0x17, 0x2f},/* CMC SIGN */
+
+ /*CMC*/ {0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87},
+
+/*CMC OFS*/
+{0x40, 0x94},
+{0x41, 0x20},
+{0x42, 0x89},
+{0x43, 0x84},
+{0x44, 0x03},
+{0x45, 0x01},
+{0x46, 0x88},
+{0x47, 0x9c},
+{0x48, 0x28},
+
+/*CMC POFS*/
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x00},
+{0x85, 0x80},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+/* PAGE 15 END */
+
+/* PAGE 16 START */
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},/* Double_AG 5e->37 */
+{0x19, 0x5d},/* Double_AG 5e->36 */
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+/*GMA Default*/
+{0x30, 0x00},
+{0x31, 0x08},
+{0x32, 0x1c},
+{0x33, 0x32},
+{0x34, 0x54},
+{0x35, 0x70},
+{0x36, 0x87},
+{0x37, 0x9a},
+{0x38, 0xaa},
+{0x39, 0xb9},
+{0x3a, 0xc4},
+{0x3b, 0xcf},
+{0x3c, 0xd8},
+{0x3d, 0xe0},
+{0x3e, 0xe9},
+{0x3f, 0xf0},
+{0x40, 0xf7},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x08},
+{0x52, 0x1e},
+{0x53, 0x36},
+{0x54, 0x5a},
+{0x55, 0x75},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x0b},
+{0x72, 0x1a},
+{0x73, 0x37},
+{0x74, 0x58},
+{0x75, 0x70},
+{0x76, 0x86},
+{0x77, 0x99},
+{0x78, 0xa9},
+{0x79, 0xb7},
+{0x7a, 0xc3},
+{0x7b, 0xcf},
+{0x7c, 0xd9},
+{0x7d, 0xe1},
+{0x7e, 0xe8},
+{0x7f, 0xef},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+/* PAGE 16 END */
+
+/* PAGE 17 START */
+{0x03, 0x17},
+{0x10, 0xf7},
+/* PAGE 17 END */
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x98},
+{0x20, 0x05},
+{0x21, 0x00},
+{0x22, 0x03},
+{0x23, 0xc0},
+{0x24, 0x00},
+{0x25, 0x04},
+{0x26, 0x00},
+{0x27, 0x08},
+{0x28, 0x05},
+{0x29, 0x04},
+{0x2a, 0x03},
+{0x2b, 0xc8},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x46},
+/* PAGE 18 END */
+
+/* PAGE 20 START */
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x05},
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x04},
+
+{0x28, 0xef},
+{0x29, 0x0d},/* 20100305 ad->0d */
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x2c, 0xc2},
+{0x2d, 0xff},
+{0x2e, 0x33},
+{0x30, 0xf8},
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+{0x39, 0x22},
+{0x3a, 0xde},
+{0x3b, 0x22},
+{0x3c, 0xde},
+
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+{0x60, 0xaa},
+{0x61, 0xaa},
+{0x62, 0xaa},
+{0x63, 0xaa},
+{0x64, 0xaa},
+{0x65, 0xaa},
+{0x66, 0xab},
+{0x67, 0xEa},
+{0x68, 0xab},
+{0x69, 0xEa},
+{0x6a, 0xaa},
+{0x6b, 0xaa},
+{0x6c, 0xaa},
+{0x6d, 0xaa},
+{0x6e, 0xaa},
+{0x6f, 0xaa},
+
+{0x70, 0x70},/* 6c */
+{0x71, 0x82},/* 82(+8) */
+
+{0x76, 0x43},
+{0x77, 0x02},
+{0x78, 0x24},/* 24 */
+{0x79, 0x48},/* Y Target 70 => 25, 72 => 26 */
+{0x7a, 0x23},/* 23 */
+{0x7b, 0x22},/* 22 */
+{0x7d, 0x23},
+
+{0x83, 0x01},/* EXP Normal 30.00 fps */
+{0x84, 0x86},
+{0x85, 0xa0},
+
+{0x86, 0x01},/* EXPMin 6000.00 fps */
+{0x87, 0xf4},
+
+{0x88, 0x05},/* EXP Max 8.57 fps */
+{0x89, 0x57},
+{0x8a, 0x30},
+
+{0x8B, 0x75},/* EXP100, PLLx2 Mclk24 */
+{0x8C, 0x30},
+
+{0x8D, 0x61},/* EXP120, PLLx2 Mclk24 */
+{0x8E, 0xa8},
+
+{0x91, 0x05},/* EXP Fix 8.00 fps */
+{0x92, 0xb8},
+{0x93, 0xd8},
+
+{0x98, 0x9d},
+{0x99, 0x45},
+{0x9a, 0x0d},
+{0x9b, 0xde},
+
+{0x9c, 0x17},/* EXP Limit 500.00 fps, PLLx2 Mclk24 */
+{0x9d, 0x70},
+
+{0x9e, 0x01},/* EXP Unit, PLLx2 Mclk24 */
+{0x9f, 0xf4},
+
+{0xb0, 0x18},
+{0xb1, 0x14},
+{0xb2, 0xe0},
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x32},
+{0xbd, 0x32},
+
+{0xc0, 0x10},
+{0xc1, 0x2b},
+{0xc2, 0x2b},
+{0xc3, 0x2b},
+{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x80},
+/* PAGE 20 END */
+
+/* PAGE 22 START */
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01},/* Low On */
+{0x20, 0x10},
+{0x21, 0x80},
+{0x24, 0x01},
+/*0x2500,  7f New Lock Cond & New light stable */
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+{0x40, 0xf3},
+
+{0x41, 0x32},/* 33 */
+{0x42, 0x22},/* 22 */
+{0x43, 0xf0},/* f6 */
+{0x44, 0x44},/* 44 */
+{0x45, 0x44},/* 33 */
+{0x46, 0x00},
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x38},
+{0x81, 0x20},
+{0x82, 0x36},/* 3a */
+
+{0x83, 0x5e},/* 5e */
+{0x84, 0x22},/* 24 21 22 Spec AWB H modify */
+{0x85, 0x4f},/* 54 51 4f Spec AWB H modify */
+{0x86, 0x20},/* 24 */
+
+{0x87, 0x48},
+{0x88, 0x38},
+{0x89, 0x37},/* 38 */
+{0x8a, 0x29},/* 2a */
+
+{0x8b, 0x40},/* 47 */
+{0x8c, 0x38},
+{0x8d, 0x34},
+{0x8e, 0x29},/* 2c */
+
+{0x8f, 0x5c},
+{0x90, 0x5b},
+{0x91, 0x57},
+{0x92, 0x4f},
+{0x93, 0x43},
+{0x94, 0x3e},
+{0x95, 0x34},
+{0x96, 0x2c},
+{0x97, 0x23},
+{0x98, 0x20},
+{0x99, 0x1f},
+{0x9a, 0x1f},
+
+{0x9b, 0x77},
+{0x9c, 0x66},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14},/* 1500fps */
+{0xa5, 0x2c},/* 700fps */
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},/* low temp Rgain */
+{0xb0, 0x26},/* low temp Rgain */
+
+{0xb1, 0x00},/* 0x20 -> 0x00 0405 modify */
+{0xb4, 0xea},
+{0xb8, 0xa1},/* a2: b-2, R+2  b4 B-3, R+4 lowtemp b0 a1 Spec AWB A modify */
+{0xb9, 0x00},
+/* PAGE 22 END */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x01 -> 0x00 not Continues */
+/*0x17cc*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/* PAGE 20 */
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+/* PAGE 22 */
+{0x03, 0x22},
+{0x10, 0xe9},
+
+/* PAGE 0 */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},
+
+{0xff, 0x28},/* NEED Delay 400ms */
+};
+
+regs_short_t front_preview_camera_regs[] = {
+{0x03, 0x00},/*Sleep On */
+{0x01, 0xf9},
+
+{0x03, 0x20},/*page 20 */
+{0x18, 0x30},/*for Preview */
+{0x10, 0x0c},/*AE off 60hz */
+
+{0x03, 0x22},/*page 22 */
+{0x10, 0x69},/*awb off */
+
+{0x03, 0x00},
+{0x10, 0x11},
+
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x02},/*modify 20110929 0x04->0x02 */
+{0x22, 0x00},
+{0x23, 0x0a},/*modify 20110929 0x14->0x0a */
+
+{0x42, 0x00},/*VBlank */
+{0x43, 0x44},/*68 */
+
+/*Page10*/
+{0x03, 0x10},
+{0x3f, 0x02},
+{0x60, 0x6b},
+
+/*Page12*/
+{0x03, 0x12},
+{0x20, 0x00},
+{0x21, 0x00},
+{0x90, 0x00},
+
+/*only for Preview DPC */
+{0xd2, 0x17},
+{0xd5, 0x0f},
+{0xd7, 0xff},
+
+/*Page13*/
+{0x03, 0x13},
+{0x80, 0x00},
+
+/*Page18*/
+{0x03, 0x18},
+{0x10, 0x07},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+/*0x17cc,*/ /*MHSHIM*/
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x01},
+{0x36, 0x03},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x20},
+{0x10, 0x8c},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},/*AWB ON */
+
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},/*Sleep Off */
+{0x01, 0xf8},
+
+{0xff, 0x28},/*400ms */
+};
+
+regs_short_t front_snapshot_normal_regs[] = {
+{0x03, 0x00},
+{0x01, 0xf9},
+
+{0x03, 0x22},/*Page 22 */
+{0x10, 0x69},/*AWB Off */
+
+{0x03, 0x00},
+{0x10, 0x00},
+{0x11, 0x90},
+
+{0x20, 0x00},
+{0x21, 0x0a},/*modify 20110929 0x0c->0x0a */
+{0x22, 0x00},
+{0x23, 0x0a},/*modify 20110929 0x14->0x0a */
+
+/*Page10*/
+{0x03, 0x10},
+{0x3f, 0x00},
+{0x60, 0x67},
+
+/*Page12*/
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+{0x90, 0x5d},
+
+/*only for Preview DPC Off*/
+{0xd2, 0x67},
+{0xd5, 0x02},
+{0xd7, 0x18},
+
+/*Page13*/
+{0x03, 0x13},
+{0x80, 0xfd},
+
+/* PAGE 18 START */
+{0x03, 0x18},
+{0x10, 0x00},/* Scaling Off */
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x81},
+{0x70, 0x85},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0c},
+{0x1d, 0x0f},
+{0x1e, 0x05},
+{0x1f, 0x05},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x80},/*1600x1200 MiPi OutPut */
+{0x31, 0x0c},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x03},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x03},/*drivability 24MHZ:02, 48MHz:03 */
+/*0x17c4,*/ /*MHSHIM*/
+/*0x17c0,*/ /*MHSHIM*/
+/*0x1700,*/ /*MHSHIM*/
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+/*Page0*/
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00},
+{0x01, 0xf8},/*Sleep Off */
+
+{0xff, 0x03},/*Increase from 30ms */
+};
+
+regs_short_t front_ev_minus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0xd0},
+};
+
+regs_short_t front_ev_minus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0xc0},
+};
+
+regs_short_t front_ev_minus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0xb0},
+};
+
+regs_short_t front_ev_minus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0xa0},
+};
+
+regs_short_t front_ev_default_regs[] = {
+{0x03, 0x10},
+{0x40, 0x00},
+};
+
+regs_short_t front_ev_plus_1_regs[] = {
+{0x03, 0x10},
+{0x40, 0x20},
+};
+
+regs_short_t front_ev_plus_2_regs[] = {
+{0x03, 0x10},
+{0x40, 0x30},
+};
+
+regs_short_t front_ev_plus_3_regs[] = {
+{0x03, 0x10},
+{0x40, 0x40},
+};
+
+regs_short_t front_ev_plus_4_regs[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_default[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_1[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_2[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_vt_pretty_3[] = {
+{0x03, 0x10},
+{0x40, 0x50},
+};
+
+regs_short_t front_fps_auto_regs[] = {
+};
+
+regs_short_t front_fps_7_regs[] = {
+/* Fixed 7fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x11},/*BLC_TIME_TH_ON */
+{0x91, 0x11},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x11},/*DCDC_TIME_TH_ON */
+{0xd5, 0x11},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x06},/*EXP Max 7.06 fps */
+{0x89, 0x7c},
+{0x8a, 0x28},
+
+{0x91, 0x06},/*EXP Fix 07.00 fps */
+{0x92, 0x89},
+{0x93, 0xd4},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_fps_10_regs[] = {
+/*  Fixed 10fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x0b},/*BLC_TIME_TH_ON */
+{0x91, 0x0b},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x0b},/*DCDC_TIME_TH_ON */
+{0xd5, 0x0b},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x04},/*EXP Max 10.91 fps */
+{0x89, 0x32},
+{0x8a, 0x38},
+
+{0x91, 0x04},/*EXP Fix 10.00 fps */
+{0x92, 0x93},
+{0x93, 0xe0},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_fps_15_regs[] = {
+/* Fixed 15fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x08},/*BLC_TIME_TH_ON */
+{0x91, 0x08},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x08},/*DCDC_TIME_TH_ON */
+{0xd5, 0x08},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x03},/*EXP Max 15.00 fps */
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x91, 0x03},/*EXP Fix 14.91 fps */
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP -> HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+
+};
+
+regs_short_t front_fps_24_regs[] = {
+/* Need to add Fixed 24fps Mode */
+/* Temporary setting, Fixed 15fps Mode */
+{0x03, 0x00},
+{0x01, 0xf9},
+{0x11, 0x90},
+
+{0x40, 0x01},/*Hblank 360 */
+{0x41, 0x68},
+{0x42, 0x00},/*Vsync 20 */
+{0x43, 0x14},
+
+{0x90, 0x08},/*BLC_TIME_TH_ON */
+{0x91, 0x08},/*BLC_TIME_TH_OFF */
+{0x92, 0xd8},/*BLC_AG_TH_ON */
+{0x93, 0xd0},/*BLC_AG_TH_OFF */
+
+{0x03, 0x02},/*PAGE 2 */
+{0xd4, 0x08},/*DCDC_TIME_TH_ON */
+{0xd5, 0x08},/*DCDC_TIME_TH_OFF */
+{0xd6, 0xd8},/*DCDC_AG_TH_ON */
+{0xd7, 0xd0},/*DCDC_AG_TH_OFF */
+
+{0x03, 0x20},
+{0x10, 0x0C},/*AE off 60hz */
+
+{0x03, 0x22},
+{0x10, 0x69},
+
+{0x03, 0x20},
+{0x2a, 0x03},
+{0x2b, 0xf5},
+
+{0x88, 0x03},/*EXP Max 15.00 fps */
+{0x89, 0x0d},
+{0x8a, 0x40},
+
+{0x91, 0x03},/*EXP Fix 14.91 fps */
+{0x92, 0x12},
+{0x93, 0x22},
+
+{0x9c, 0x17},/*EXP Limit 500.00 fps */
+{0x9d, 0x70},
+{0x9e, 0x01},/*EXP Unit */
+{0x9f, 0xf4},
+
+{0x03, 0x20},
+{0x10, 0x8C},/*AE on 60hz */
+
+{0x03, 0x22},
+{0x10, 0xe9},
+
+{0x03, 0x00},
+{0x11, 0x94},
+
+/* PAGE 48 START*/
+{0x03, 0x48},
+
+/* PLL Setting */
+{0x70, 0x05},
+{0x71, 0x30},/*MiPi Pllx2 */
+{0x72, 0x85},
+{0x70, 0xa5},/* PLL Enable */
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x03, 0x48},
+{0x70, 0x95},/* CLK_GEN_ENABLE */
+
+/* MIPI TX Setting */
+{0x11, 0x00},/* 20111013 0x10 continuous -> 0x00 not Continuous */
+{0x10, 0x1c},
+{0x12, 0x00},
+{0x14, 0x30},/*0x1470, *//* 20111013 0x00 -> 0x30 Clock Delay */
+{0x16, 0x04},/* 1016 0x04->0x05 */
+
+{0x19, 0x00},
+{0x1a, 0x32},
+{0x1b, 0x17},
+{0x1c, 0x0e},
+{0x1d, 0x0f},
+{0x1e, 0x04},
+{0x1f, 0x04},
+{0x20, 0x00},
+
+{0x23, 0x01},
+{0x24, 0x1e},
+{0x25, 0x00},
+{0x26, 0x00},
+{0x27, 0x01},
+{0x28, 0x00},
+{0x2a, 0x06},
+{0x2b, 0x40},
+{0x2c, 0x04},
+{0x2d, 0xb0},
+
+{0x30, 0x00},/*640x480 MiPi OutPut */
+{0x31, 0x05},
+
+/*0x3040, 800x600 MiPi OutPut*/
+/*0x3106,*/
+
+{0x32, 0x06},
+{0x33, 0x0a},
+{0x34, 0x02},/*CLK LP->HS Prepare time 24MHz:0x02, 48MHz:0x03 */
+{0x35, 0x03},
+{0x36, 0x01},
+{0x37, 0x07},
+{0x38, 0x02},
+{0x39, 0x02},/*drivability 24MHZ:02, 48MHz:03 */
+{0x50, 0x00},
+/* PAGE 48 END*/
+
+{0x03, 0x00},
+{0x03, 0x00},/*Dummy 750us */
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x01, 0xf8},
+
+{0xff, 0x28},/*NEED Delay 400ms */
+};
+
+regs_short_t front_pattern_on_regs[] = {
+{0x03, 0x00},
+{0x50, 0x05},
+};
+
+regs_short_t front_pattern_off_regs[] = {
+{0x03, 0x00},
+{0x50, 0x00},
+};
+
+#endif/* __SR200PC20M_REGS_H */
diff --git a/drivers/media/video/v4l2-common.c b/drivers/media/video/v4l2-common.c
index 06b9f9f..92bc5ba 100644
--- a/drivers/media/video/v4l2-common.c
+++ b/drivers/media/video/v4l2-common.c
@@ -582,6 +582,32 @@ int v4l_fill_dv_preset_info(u32 preset, struct v4l2_dv_enum_preset *info)
 		{ 1920, 1080, "1080p@30" },	/* V4L2_DV_1080P30 */
 		{ 1920, 1080, "1080p@50" },	/* V4L2_DV_1080P50 */
 		{ 1920, 1080, "1080p@60" },	/* V4L2_DV_1080P60 */
+		{ 720,  480, "480p@60" },	/* V4L2_DV_480P60 */
+		{ 1920, 1080, "1080i@59.94" },	/* V4L2_DV_1080I59_94 */
+		{ 1920, 1080, "1080p@59.94" },	/* V4L2_DV_1080P59_94 */
+		{ 1280, 720, "720p@60_fp" },		/* V4L2_DV_720P60_FP */
+		{ 1280, 720, "720p@60_sb_half" },	/* V4L2_DV_720P60_SB_HALF */
+		{ 1280, 720, "720p@60_tb" },		/* V4L2_DV_720P60_TB */
+		{ 1280, 720, "720p@59_94_fp" },		/* V4L2_DV_720P59_94_FP */
+		{ 1280, 720, "720p@59_94_sb_half" },	/* V4L2_DV_720P59_94_SB_HALF */
+		{ 1280, 720, "720p@59_94_tb" },		/* V4L2_DV_720P59_94_TB */
+		{ 1280, 720, "720p@50_fp" },		/* V4L2_DV_720P50_FP */
+		{ 1280, 720, "720p@50_sb_half" },	/* V4L2_DV_720P50_SB_HALF */
+		{ 1280, 720, "720p@50_tb" },		/* V4L2_DV_720P50_TB */
+		{ 1920, 1080, "1080p@24_fp" },		/* V4L2_DV_1080P24_FP */
+		{ 1920, 1080, "1080p@24_sb_half" },	/* V4L2_DV_1080P24_SB_HALF */
+		{ 1920, 1080, "1080p@24_tb" },		/* V4L2_DV_1080P24_TB */
+		{ 1920, 1080, "1080p@23_98_fp" },	/* V4L2_DV_1080P23_98_FP */
+		{ 1920, 1080, "1080p@23_98_sb_half" },	/* V4L2_DV_1080P23_98_SB_HALF */
+		{ 1920, 1080, "1080p@23_98_tb" },	/* V4L2_DV_1080P23_98_TB */
+		{ 1920, 1080, "1080i@60_sb_half" },	/* V4L2_DV_1080I60_SB_HALF */
+		{ 1920, 1080, "1080i@59_94_sb_half" },	/* V4L2_DV_1080I59_94_SB_HALF */
+		{ 1920, 1080, "1080i@50_sb_half" },	/* V4L2_DV_1080I50_SB_HALF */
+		{ 1920, 1080, "1080p@60_sb_half" },     /* V4L2_DV_1080P60_SB_HALF */
+		{ 1920, 1080, "1080p@60_tb" },		/* V4L2_DV_1080P60_TB */
+		{ 1920, 1080, "1080p@30_fp" },		/* V4L2_DV_1080P30_FP */
+		{ 1920, 1080, "1080p@30_sb_half" },	/* V4L2_DV_1080P30_SB_HALF */
+		{ 1920, 1080, "1080p@30_tb" },		/* V4L2_DV_1080P30_TB */
 	};
 
 	if (info == NULL || preset >= ARRAY_SIZE(dv_presets))
diff --git a/drivers/media/video/v4l2-ctrls.c b/drivers/media/video/v4l2-ctrls.c
index 2412f08..8a34b2d 100644
--- a/drivers/media/video/v4l2-ctrls.c
+++ b/drivers/media/video/v4l2-ctrls.c
@@ -216,6 +216,12 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
 		"75 useconds",
 		NULL,
 	};
+	static const char * const tune_deemphasis[] = {
+		"No Preemphasis",
+		"50 useconds",
+		"75 useconds",
+		NULL,
+	};
 
 	switch (id) {
 	case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ:
@@ -256,6 +262,8 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
 		return colorfx;
 	case V4L2_CID_TUNE_PREEMPHASIS:
 		return tune_preemphasis;
+	case V4L2_CID_TUNE_DEEMPHASIS:
+		return tune_deemphasis;
 	default:
 		return NULL;
 	}
@@ -389,6 +397,11 @@ const char *v4l2_ctrl_get_name(u32 id)
 	case V4L2_CID_TUNE_POWER_LEVEL:		return "Tune Power Level";
 	case V4L2_CID_TUNE_ANTENNA_CAPACITOR:	return "Tune Antenna Capacitor";
 
+	/* FM Radio Tuner control */
+	/* Keep the order of the 'case's the same as in videodev2.h! */
+	case V4L2_CID_FM_RX_CLASS:	return "FM Radio Tuner Controls";
+	case V4L2_CID_TUNE_DEEMPHASIS:	return "De-emphasis settings";
+
 	default:
 		return NULL;
 	}
@@ -452,6 +465,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
 	case V4L2_CID_EXPOSURE_AUTO:
 	case V4L2_CID_COLORFX:
 	case V4L2_CID_TUNE_PREEMPHASIS:
+	case V4L2_CID_TUNE_DEEMPHASIS:
 		*type = V4L2_CTRL_TYPE_MENU;
 		break;
 	case V4L2_CID_RDS_TX_PS_NAME:
@@ -462,6 +476,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
 	case V4L2_CID_CAMERA_CLASS:
 	case V4L2_CID_MPEG_CLASS:
 	case V4L2_CID_FM_TX_CLASS:
+	case V4L2_CID_FM_RX_CLASS:
 		*type = V4L2_CTRL_TYPE_CTRL_CLASS;
 		/* You can neither read not write these */
 		*flags |= V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_WRITE_ONLY;
diff --git a/drivers/media/video/v4l2-fh.c b/drivers/media/video/v4l2-fh.c
index 717f71e..8635011 100644
--- a/drivers/media/video/v4l2-fh.c
+++ b/drivers/media/video/v4l2-fh.c
@@ -32,6 +32,8 @@
 int v4l2_fh_init(struct v4l2_fh *fh, struct video_device *vdev)
 {
 	fh->vdev = vdev;
+	/* Inherit from video_device. May be overridden by the driver. */
+	fh->ctrl_handler = vdev->ctrl_handler;
 	INIT_LIST_HEAD(&fh->list);
 	set_bit(V4L2_FL_USES_V4L2_FH, &fh->vdev->flags);
 	fh->prio = V4L2_PRIORITY_UNSET;
diff --git a/drivers/media/video/v4l2-ioctl.c b/drivers/media/video/v4l2-ioctl.c
index 69e8c6f..f3e2cc7 100644
--- a/drivers/media/video/v4l2-ioctl.c
+++ b/drivers/media/video/v4l2-ioctl.c
@@ -1418,7 +1418,9 @@ static long __video_do_ioctl(struct file *file,
 	{
 		struct v4l2_queryctrl *p = arg;
 
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_queryctrl(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_queryctrl(vfd->ctrl_handler, p);
 		else if (ops->vidioc_queryctrl)
 			ret = ops->vidioc_queryctrl(file, fh, p);
@@ -1438,7 +1440,9 @@ static long __video_do_ioctl(struct file *file,
 	{
 		struct v4l2_control *p = arg;
 
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_g_ctrl(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_g_ctrl(vfd->ctrl_handler, p);
 		else if (ops->vidioc_g_ctrl)
 			ret = ops->vidioc_g_ctrl(file, fh, p);
@@ -1470,12 +1474,17 @@ static long __video_do_ioctl(struct file *file,
 		struct v4l2_ext_controls ctrls;
 		struct v4l2_ext_control ctrl;
 
-		if (!vfd->ctrl_handler &&
+		if (!(vfh && vfh->ctrl_handler) && !vfd->ctrl_handler &&
 			!ops->vidioc_s_ctrl && !ops->vidioc_s_ext_ctrls)
 			break;
 
 		dbgarg(cmd, "id=0x%x, value=%d\n", p->id, p->value);
 
+		if (vfh && vfh->ctrl_handler) {
+			ret = v4l2_s_ctrl(vfh->ctrl_handler, p);
+			break;
+		}
+
 		if (vfd->ctrl_handler) {
 			ret = v4l2_s_ctrl(vfd->ctrl_handler, p);
 			break;
@@ -1501,7 +1510,9 @@ static long __video_do_ioctl(struct file *file,
 		struct v4l2_ext_controls *p = arg;
 
 		p->error_idx = p->count;
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_g_ext_ctrls(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_g_ext_ctrls(vfd->ctrl_handler, p);
 		else if (ops->vidioc_g_ext_ctrls && check_ext_ctrls(p, 0))
 			ret = ops->vidioc_g_ext_ctrls(file, fh, p);
@@ -1515,10 +1526,13 @@ static long __video_do_ioctl(struct file *file,
 		struct v4l2_ext_controls *p = arg;
 
 		p->error_idx = p->count;
-		if (!vfd->ctrl_handler && !ops->vidioc_s_ext_ctrls)
+		if (!(vfh && vfh->ctrl_handler) && !vfd->ctrl_handler &&
+				!ops->vidioc_s_ext_ctrls)
 			break;
 		v4l_print_ext_ctrls(cmd, vfd, p, 1);
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_s_ext_ctrls(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_s_ext_ctrls(vfd->ctrl_handler, p);
 		else if (check_ext_ctrls(p, 0))
 			ret = ops->vidioc_s_ext_ctrls(file, fh, p);
@@ -1529,10 +1543,13 @@ static long __video_do_ioctl(struct file *file,
 		struct v4l2_ext_controls *p = arg;
 
 		p->error_idx = p->count;
-		if (!vfd->ctrl_handler && !ops->vidioc_try_ext_ctrls)
+		if (!(vfh && vfh->ctrl_handler) && !vfd->ctrl_handler &&
+				!ops->vidioc_try_ext_ctrls)
 			break;
 		v4l_print_ext_ctrls(cmd, vfd, p, 1);
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_try_ext_ctrls(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_try_ext_ctrls(vfd->ctrl_handler, p);
 		else if (check_ext_ctrls(p, 0))
 			ret = ops->vidioc_try_ext_ctrls(file, fh, p);
@@ -1542,7 +1559,9 @@ static long __video_do_ioctl(struct file *file,
 	{
 		struct v4l2_querymenu *p = arg;
 
-		if (vfd->ctrl_handler)
+		if (vfh && vfh->ctrl_handler)
+			ret = v4l2_querymenu(vfh->ctrl_handler, p);
+		else if (vfd->ctrl_handler)
 			ret = v4l2_querymenu(vfd->ctrl_handler, p);
 		else if (ops->vidioc_querymenu)
 			ret = ops->vidioc_querymenu(file, fh, p);
diff --git a/drivers/media/video/v4l2-mem2mem.c b/drivers/media/video/v4l2-mem2mem.c
index 3b15bf5..5363f4d 100644
--- a/drivers/media/video/v4l2-mem2mem.c
+++ b/drivers/media/video/v4l2-mem2mem.c
@@ -38,7 +38,8 @@ module_param(debug, bool, 0644);
 #define TRANS_QUEUED		(1 << 0)
 /* Instance is currently running in hardware */
 #define TRANS_RUNNING		(1 << 1)
-
+/* Instance is stopped */
+#define TRANS_STOPPED		(1 << 2)
 
 /* Offset base for buffers on the destination queue - used to distinguish
  * between source and destination buffers when mmapping - they receive the same
@@ -182,6 +183,34 @@ static void v4l2_m2m_try_run(struct v4l2_m2m_dev *m2m_dev)
 }
 
 /**
+ * v4l2_m2m_get_next_job() - find the remainging job and run it if it's
+ * different from previous job.
+ */
+void v4l2_m2m_get_next_job(struct v4l2_m2m_dev *m2m_dev, struct v4l2_m2m_ctx *m2m_ctx)
+{
+	unsigned long flags;
+	struct v4l2_m2m_ctx *cm2m_ctx, *tm2m_ctx, *next_job = NULL;
+
+	spin_lock_irqsave(&m2m_dev->job_spinlock, flags);
+	list_for_each_entry_safe(cm2m_ctx, tm2m_ctx, &m2m_dev->job_queue, queue) {
+		if (cm2m_ctx->job_flags & TRANS_STOPPED)
+			list_del_init(&cm2m_ctx->queue);
+	}
+	m2m_ctx->job_flags &= ~TRANS_STOPPED;
+	spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags);
+
+	if (!list_empty(&m2m_dev->job_queue)) {
+		next_job = list_first_entry(&m2m_dev->job_queue, struct v4l2_m2m_ctx,
+					    queue);
+		if ((next_job != m2m_dev->curr_ctx) && (m2m_dev->curr_ctx != NULL)) {
+			m2m_dev->curr_ctx = NULL;
+			v4l2_m2m_try_run(m2m_dev);
+		}
+	}
+}
+EXPORT_SYMBOL(v4l2_m2m_get_next_job);
+
+/**
  * v4l2_m2m_try_schedule() - check whether an instance is ready to be added to
  * the pending job queue and add it if so.
  * @m2m_ctx:	m2m context assigned to the instance to be checked
@@ -389,6 +418,7 @@ int v4l2_m2m_streamoff(struct file *file, struct v4l2_m2m_ctx *m2m_ctx,
 {
 	struct vb2_queue *vq;
 
+	m2m_ctx->job_flags |= TRANS_STOPPED;
 	vq = v4l2_m2m_get_vq(m2m_ctx, type);
 	return vb2_streamoff(vq, type);
 }
diff --git a/drivers/media/video/videobuf-core.c b/drivers/media/video/videobuf-core.c
index de4fa4e..b457c8b 100644
--- a/drivers/media/video/videobuf-core.c
+++ b/drivers/media/video/videobuf-core.c
@@ -335,6 +335,9 @@ static void videobuf_status(struct videobuf_queue *q, struct v4l2_buffer *b,
 	case V4L2_MEMORY_OVERLAY:
 		b->m.offset  = vb->boff;
 		break;
+	case V4L2_MEMORY_DMABUF:
+		/* DMABUF is not handled in videobuf framework */
+		break;
 	}
 
 	b->flags    = 0;
@@ -411,6 +414,7 @@ int __videobuf_mmap_setup(struct videobuf_queue *q,
 			break;
 		case V4L2_MEMORY_USERPTR:
 		case V4L2_MEMORY_OVERLAY:
+		case V4L2_MEMORY_DMABUF:
 			/* nothing */
 			break;
 		}
diff --git a/drivers/media/video/videobuf2-cma-phys.c b/drivers/media/video/videobuf2-cma-phys.c
new file mode 100644
index 0000000..279b61e
--- /dev/null
+++ b/drivers/media/video/videobuf2-cma-phys.c
@@ -0,0 +1,692 @@
+/* linux/drivers/media/video/videobuf2-cma-phys.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * CMA-phys memory allocator for videobuf2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/cma.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/file.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-buf.h>
+
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-memops.h>
+
+#include <asm/cacheflush.h>
+
+#define SIZE_THRESHOLD SZ_1M
+
+struct vb2_cma_phys_conf {
+	struct device		*dev;
+	const char		*type;
+	unsigned long		alignment;
+	bool			cacheable;
+};
+
+struct vb2_cma_phys_buf {
+	struct vb2_cma_phys_conf		*conf;
+	dma_addr_t			dma_addr;
+	unsigned long			size;
+	struct vm_area_struct		*vma;
+	/* fd exported from this buf object. */
+	int				export_fd;
+	/* dma buf exported from this buf object. */
+	struct dma_buf			*export_dma_buf;
+	struct dma_buf_attachment	*db_attach;
+	atomic_t			refcount;
+	struct vb2_vmarea_handler	handler;
+	bool				cacheable;
+};
+
+struct vb2_cma_phys_db_attach {
+	struct vb2_dc_buf		*buf;
+	struct dma_buf_attachment	db_attach;
+};
+
+static void vb2_cma_phys_put(void *buf_priv);
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+static int cma_phys_attach(struct dma_buf *dmabuf, struct device *dev,
+				struct dma_buf_attachment *attach)
+{
+	/* TODO */
+
+	return 0;
+}
+
+static void cma_phys_detach(struct dma_buf *dmabuf,
+				struct dma_buf_attachment *attach)
+{
+	/* TODO */
+
+	/*
+	 * when vb2_cma_phys_export_dmabuf() is called, file->f_count of this
+	 * dmabuf will be increased by dma_buf_get() so drop the reference here.
+	 */
+	dma_buf_put(dmabuf);
+}
+
+static struct sg_table *
+	cma_phys_map_dmabuf(struct dma_buf_attachment *attach,
+				enum dma_data_direction direction)
+{
+	struct vb2_cma_phys_buf *buf = attach->dmabuf->priv;
+	struct sg_table *sgt;
+	int ret;
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		printk(KERN_ERR "failed to allocate sg table.\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
+	if (ret < 0) {
+		printk(KERN_ERR "failed to allocate scatter list.\n");
+		kfree(sgt);
+		sgt = NULL;
+		return ERR_PTR(-ENOMEM);
+	}
+
+	sg_init_table(sgt->sgl, 1);
+	sg_dma_len(sgt->sgl) = buf->size;
+	sg_set_page(sgt->sgl, pfn_to_page(PFN_DOWN(buf->dma_addr)),
+			buf->size, 0);
+	sg_dma_address(sgt->sgl) = buf->dma_addr;
+
+	/*
+	 * increase reference count of this buf object.
+	 *
+	 * Note:
+	 * alloated physical memory region is being shared with others so
+	 * this region shouldn't be released until all references of this
+	 * region will be dropped by vb2_cma_phys_unmap_dmabuf().
+	 */
+	atomic_inc(&buf->refcount);
+
+	return sgt;
+}
+
+static void cma_phys_unmap_dmabuf(struct dma_buf_attachment *attach,
+					struct sg_table *sgt,
+					enum dma_data_direction dir)
+{
+	struct vb2_cma_phys_buf *buf = attach->dmabuf->priv;
+
+	sg_free_table(sgt);
+	kfree(sgt);
+	sgt = NULL;
+
+	if (atomic_read(&buf->refcount) <= 9)
+		BUG();
+
+	atomic_dec(&buf->refcount);
+}
+
+static void cma_phys_release(struct dma_buf *dmabuf)
+{
+	struct vb2_cma_phys_buf *buf = dmabuf->priv;
+
+	/*
+	 * vb2_cma_phys_release() call means that file object's f_count is
+	 * 0 and it calls vb2_cma_phys_put() to drop the reference that it
+	 * had been increased at vb2_cma_phys_export_dmabuf().
+	 */
+	if (buf->export_dma_buf == dmabuf) {
+		buf->export_fd = -1;
+		buf->export_dma_buf = NULL;
+
+		/*
+		 * drop this buf object reference to release allocated buffer
+		 * and resource.
+		 */
+		vb2_cma_phys_put(buf);
+	}
+}
+
+static struct dma_buf_ops cma_phys_dmabuf_ops = {
+	.attach		= cma_phys_attach,
+	.detach		= cma_phys_detach,
+	.map_dma_buf	= cma_phys_map_dmabuf,
+	.unmap_dma_buf	= cma_phys_unmap_dmabuf,
+	.release	= cma_phys_release,
+};
+#else
+#define cma_phys_attach		NULL
+#define cma_phys_detach		NULL
+#define cma_phys_map_dmabuf	NULL
+#define cma_phys_unmap_dmabuf	NULL
+#define cma_phys_release	NULL
+#endif
+
+static void *vb2_cma_phys_alloc(void *alloc_ctx, unsigned long size)
+{
+	struct vb2_cma_phys_conf *conf = alloc_ctx;
+	struct vb2_cma_phys_buf *buf;
+
+	buf = kzalloc(sizeof *buf, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	buf->dma_addr = cma_alloc(conf->dev, conf->type, size, conf->alignment);
+	if (IS_ERR((void *)buf->dma_addr)) {
+		printk(KERN_ERR "cma_alloc of size %ld failed\n", size);
+		kfree(buf);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	buf->conf = conf;
+	buf->size = size;
+	buf->cacheable = conf->cacheable;
+
+	buf->handler.refcount = &buf->refcount;
+	buf->handler.put = vb2_cma_phys_put;
+	buf->handler.arg = buf;
+
+	atomic_inc(&buf->refcount);
+
+	return buf;
+}
+
+static void vb2_cma_phys_put(void *buf_priv)
+{
+	struct vb2_cma_phys_buf *buf = buf_priv;
+
+	if (atomic_dec_and_test(&buf->refcount)) {
+		cma_free(buf->dma_addr);
+		kfree(buf);
+	}
+}
+
+static void *vb2_cma_phys_cookie(void *buf_priv)
+{
+	struct vb2_cma_phys_buf *buf = buf_priv;
+
+	return (void *)buf->dma_addr;
+}
+
+static unsigned int vb2_cma_phys_num_users(void *buf_priv)
+{
+	struct vb2_cma_phys_buf *buf = buf_priv;
+
+	return atomic_read(&buf->refcount);
+}
+
+/**
+ * vb2_cma_mmap_pfn_range() - map physical pages to userspace
+ * @vma:	virtual memory region for the mapping
+ * @dma_addr:	starting dma address of the memory to be mapped
+ * @size:	size of the memory to be mapped
+ * @vm_ops:	vm operations to be assigned to the created area
+ * @priv:	private data to be associated with the area
+ *
+ * Returns 0 on success.
+ */
+int vb2_cma_phys_mmap_pfn_range(struct vm_area_struct *vma,
+				unsigned long dma_addr,
+				unsigned long size,
+				const struct vm_operations_struct *vm_ops,
+				void *priv)
+{
+	int ret;
+
+	size = min_t(unsigned long, vma->vm_end - vma->vm_start, size);
+
+	ret = remap_pfn_range(vma, vma->vm_start, dma_addr >> PAGE_SHIFT,
+				size, vma->vm_page_prot);
+	if (ret) {
+		printk(KERN_ERR "Remapping memory failed, error: %d\n", ret);
+		return ret;
+	}
+
+	vma->vm_flags		|= VM_DONTEXPAND | VM_RESERVED;
+	vma->vm_private_data	= priv;
+	vma->vm_ops		= vm_ops;
+
+	vma->vm_ops->open(vma);
+
+	printk(KERN_DEBUG "%s: mapped dma addr 0x%08lx at 0x%08lx, size %ld\n",
+			__func__, dma_addr, vma->vm_start, size);
+
+	return 0;
+}
+
+static int vb2_cma_phys_mmap(void *buf_priv, struct vm_area_struct *vma)
+{
+	struct vb2_cma_phys_buf *buf = buf_priv;
+
+	if (!buf) {
+		printk(KERN_ERR "No buffer to map\n");
+		return -EINVAL;
+	}
+
+	if (!buf->cacheable)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	return vb2_cma_phys_mmap_pfn_range(vma, buf->dma_addr, buf->size,
+					   &vb2_common_vm_ops, &buf->handler);
+}
+
+static void *vb2_cma_phys_get_userptr(void *alloc_ctx, unsigned long vaddr,
+				 unsigned long size, int write)
+{
+	struct vb2_cma_phys_buf *buf;
+
+	buf = kzalloc(sizeof *buf, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	printk(KERN_DEBUG "[%s] dma_addr(0x%08lx)\n", __func__, vaddr);
+	buf->size = size;
+	buf->dma_addr = vaddr;	/* drv directly gets dma addr. from user. */
+
+	return buf;
+}
+
+static void vb2_cma_phys_put_userptr(void *mem_priv)
+{
+	struct vb2_cma_phys_buf *buf = mem_priv;
+
+	if (!buf)
+		return;
+
+	kfree(buf);
+}
+
+static void *vb2_cma_phys_vaddr(void *mem_priv)
+{
+	struct vb2_cma_phys_buf *buf = mem_priv;
+	if (!buf)
+		return 0;
+
+	return phys_to_virt(buf->dma_addr);
+}
+
+static void vb2_cma_phys_map_dmabuf(void *mem_priv)
+{
+	struct vb2_cma_phys_buf *buf = mem_priv;
+	struct dma_buf *dmabuf;
+	struct sg_table *sg;
+	enum dma_data_direction dir;
+
+	if (!buf || !buf->db_attach)
+		return;
+
+	WARN_ON(buf->dma_addr);
+
+	dmabuf = buf->db_attach->dmabuf;
+
+	/* TODO need a way to know if we are camera or display, etc.. */
+	dir = DMA_BIDIRECTIONAL;
+
+	/* get the associated sg for this buffer */
+	sg = dma_buf_map_attachment(buf->db_attach, dir);
+	if (!sg)
+		return;
+
+	/*
+	 *  convert sglist to dma_addr:
+	 *  Assumption: for dma-contig, dmabuf would map to single entry
+	 *  Will print a warning if it has more than one.
+	 */
+	if (sg->nents > 1)
+		printk(KERN_WARNING
+			"dmabuf scatterlist has more than 1 entry\n");
+
+	buf->dma_addr = sg_dma_address(sg->sgl);
+	buf->size = sg_dma_len(sg->sgl);
+
+	/* save this sg in dmabuf for put_scatterlist */
+	dmabuf->priv = sg;
+}
+
+static void vb2_cma_phys_unmap_dmabuf(void *mem_priv)
+{
+	struct vb2_cma_phys_buf *buf = mem_priv;
+	struct dma_buf *dmabuf;
+	struct sg_table *sg;
+
+	if (!buf || !buf->db_attach)
+		return;
+
+	WARN_ON(!buf->dma_addr);
+
+	dmabuf = buf->db_attach->dmabuf;
+	sg = dmabuf->priv;
+
+	/*
+	 * Put the sg for this buffer:
+	 */
+	dma_buf_unmap_attachment(buf->db_attach, sg, DMA_FROM_DEVICE);
+
+	buf->dma_addr = 0;
+	buf->size = 0;
+}
+
+#ifdef CONFIG_DMA_SHARED_BUFFER
+static int vb2_cma_phys_export_dmabuf(void *alloc_ctx, void *buf_priv,
+					int *export_fd)
+{
+	struct vb2_cma_phys_buf *buf = buf_priv;
+	unsigned int flags = O_RDWR;
+
+	buf->export_dma_buf = dma_buf_export(buf, &cma_phys_dmabuf_ops,
+						buf->size, 0600);
+	if (!buf->export_dma_buf)
+		return PTR_ERR(buf->export_dma_buf);
+
+	/* FIXME!!! */
+	flags |= O_CLOEXEC;
+
+	buf->export_fd = dma_buf_fd(buf->export_dma_buf, flags);
+	if (buf->export_fd < 0) {
+		printk(KERN_ERR "fail to get fd from dmabuf.\n");
+		dma_buf_put(buf->export_dma_buf);
+		return buf->export_fd;
+	}
+
+	/*
+	 * this buf object is referenced by buf->export_fd so
+	 * the object refcount should be increased. thereafter,
+	 * when vb2_cma_phys_put() is called, it will be decreased again.
+	 */
+	atomic_inc(&buf->refcount);
+
+	*export_fd = buf->export_fd;
+
+	return 0;
+}
+#else
+#define vb2_cma_phys_export_dmabuf	NULL
+#endif
+
+static void *vb2_cma_phys_attach_dmabuf(void *alloc_ctx, struct dma_buf *dbuf)
+{
+	struct vb2_cma_phys_conf *conf = alloc_ctx;
+	struct vb2_cma_phys_buf *buf;
+	struct dma_buf_attachment *dba;
+
+	buf = kzalloc(sizeof *buf, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	/* create attachment for the dmabuf with the user device */
+	dba = dma_buf_attach(dbuf, conf->dev);
+	if (IS_ERR(dba)) {
+		printk(KERN_ERR "failed to attach dmabuf\n");
+		kfree(buf);
+		return dba;
+	}
+
+	buf->conf = conf;
+	buf->size = dba->dmabuf->size;
+	buf->db_attach = dba;
+	buf->dma_addr = 0; /* dma_addr is available only after acquire */
+
+	return buf;
+}
+
+static void vb2_cma_phys_detach_dmabuf(void *mem_priv)
+{
+	struct vb2_cma_phys_buf *buf = mem_priv;
+
+	if (!buf)
+		return;
+
+	if (buf->dma_addr)
+		vb2_cma_phys_unmap_dmabuf(buf);
+
+	/* detach this attachment */
+	dma_buf_detach(buf->db_attach->dmabuf, buf->db_attach);
+	buf->db_attach = NULL;
+
+	kfree(buf);
+}
+
+const struct vb2_mem_ops vb2_cma_phys_memops = {
+	.alloc		= vb2_cma_phys_alloc,
+	.put		= vb2_cma_phys_put,
+	.cookie		= vb2_cma_phys_cookie,
+	.mmap		= vb2_cma_phys_mmap,
+	.get_userptr	= vb2_cma_phys_get_userptr,
+	.put_userptr	= vb2_cma_phys_put_userptr,
+	.map_dmabuf	= vb2_cma_phys_map_dmabuf,
+	.unmap_dmabuf	= vb2_cma_phys_unmap_dmabuf,
+	.export_dmabuf	= vb2_cma_phys_export_dmabuf,
+	.attach_dmabuf	= vb2_cma_phys_attach_dmabuf,
+	.detach_dmabuf	= vb2_cma_phys_detach_dmabuf,
+	.num_users	= vb2_cma_phys_num_users,
+	.vaddr		= vb2_cma_phys_vaddr,
+};
+EXPORT_SYMBOL_GPL(vb2_cma_phys_memops);
+
+void *vb2_cma_phys_init(struct device *dev, const char *type,
+			unsigned long alignment, bool cacheable)
+{
+	struct vb2_cma_phys_conf *conf;
+
+	conf = kzalloc(sizeof *conf, GFP_KERNEL);
+	if (!conf)
+		return ERR_PTR(-ENOMEM);
+
+	conf->dev = dev;
+	conf->type = type;
+	conf->alignment = alignment;
+	conf->cacheable = cacheable;
+
+	return conf;
+}
+EXPORT_SYMBOL_GPL(vb2_cma_phys_init);
+
+void vb2_cma_phys_cleanup(void *conf)
+{
+	if (conf)
+		kfree(conf);
+	else
+		printk(KERN_ERR "fail to cleanup\n");
+}
+EXPORT_SYMBOL_GPL(vb2_cma_phys_cleanup);
+
+void **vb2_cma_phys_init_multi(struct device *dev,
+			  unsigned int num_planes,
+			  const char *types[],
+			  unsigned long alignments[],
+			  bool cacheable)
+{
+	struct vb2_cma_phys_conf *cma_conf;
+	void **alloc_ctxes;
+	unsigned int i;
+
+	alloc_ctxes = kzalloc((sizeof *alloc_ctxes + sizeof *cma_conf)
+				* num_planes, GFP_KERNEL);
+	if (!alloc_ctxes)
+		return ERR_PTR(-ENOMEM);
+
+	cma_conf = (void *)(alloc_ctxes + num_planes);
+
+	for (i = 0; i < num_planes; ++i, ++cma_conf) {
+		alloc_ctxes[i] = cma_conf;
+		cma_conf->dev = dev;
+		cma_conf->type = types[i];
+		cma_conf->alignment = alignments[i];
+		cma_conf->cacheable = cacheable;
+	}
+
+	return alloc_ctxes;
+}
+EXPORT_SYMBOL_GPL(vb2_cma_phys_init_multi);
+
+void vb2_cma_phys_cleanup_multi(void **alloc_ctxes)
+{
+	if (alloc_ctxes)
+		kfree(alloc_ctxes);
+	else
+		printk(KERN_ERR "fail to cleanup_multi\n");
+}
+EXPORT_SYMBOL_GPL(vb2_cma_phys_cleanup_multi);
+
+void vb2_cma_phys_set_cacheable(void *alloc_ctx, bool cacheable)
+{
+	((struct vb2_cma_phys_conf *)alloc_ctx)->cacheable = cacheable;
+}
+
+bool vb2_cma_phys_get_cacheable(void *alloc_ctx)
+{
+	return ((struct vb2_cma_phys_conf *)alloc_ctx)->cacheable;
+}
+
+static void _vb2_cma_phys_cache_flush_all(void)
+{
+	flush_cache_all();	/* L1 */
+	smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+	outer_flush_all();	/* L2 */
+}
+
+static void _vb2_cma_phys_cache_flush_range(struct vb2_cma_phys_buf *buf,
+					    unsigned long size)
+{
+	phys_addr_t start = buf->dma_addr;
+	phys_addr_t end = start + size - 1;
+
+	if (size > SZ_64K ) {
+		flush_cache_all();	/* L1 */
+		smp_call_function((smp_call_func_t)__cpuc_flush_kern_all, NULL, 1);
+	} else {
+		dmac_flush_range(phys_to_virt(start), phys_to_virt(end));
+	}
+
+	outer_flush_range(start, end);	/* L2 */
+}
+
+int vb2_cma_phys_cache_flush(struct vb2_buffer *vb, u32 num_planes)
+{
+	struct vb2_cma_phys_buf *buf;
+	unsigned long size = 0;
+	int i;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		if (!buf->cacheable) {
+			pr_warning("This is non-cacheable buffer allocator\n");
+			return -EINVAL;
+		}
+
+		size += buf->size;
+	}
+
+	if (size > (unsigned long)SIZE_THRESHOLD) {
+		_vb2_cma_phys_cache_flush_all();
+	} else {
+		for (i = 0; i < num_planes; i++) {
+			buf = vb->planes[i].mem_priv;
+			_vb2_cma_phys_cache_flush_range(buf, size);
+		}
+	}
+
+	return 0;
+}
+
+int vb2_cma_phys_cache_inv(struct vb2_buffer *vb, u32 num_planes)
+{
+	struct vb2_cma_phys_buf *buf;
+	phys_addr_t start;
+	size_t size;
+	int i;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		start = buf->dma_addr;
+		size = buf->size;
+
+		if (!buf->cacheable) {
+			pr_warning("This is non-cacheable buffer allocator\n");
+			return -EINVAL;
+		}
+
+		dmac_unmap_area(phys_to_virt(start), size, DMA_FROM_DEVICE);
+		outer_inv_range(start, start + size);	/* L2 */
+	}
+
+	return 0;
+}
+
+int vb2_cma_phys_cache_clean(struct vb2_buffer *vb, u32 num_planes)
+{
+	struct vb2_cma_phys_buf *buf;
+	phys_addr_t start;
+	size_t size;
+	int i;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		start = buf->dma_addr;
+		size = buf->size;
+
+		if (!buf->cacheable) {
+			pr_warning("This is non-cacheable buffer allocator\n");
+			return -EINVAL;
+		}
+
+		dmac_unmap_area(phys_to_virt(start), size, DMA_TO_DEVICE);
+		outer_clean_range(start, start + size - 1);	/* L2 */
+	}
+
+	return 0;
+}
+
+/* FIXME: l2 cache clean all should be implemented */
+int vb2_cma_phys_cache_clean2(struct vb2_buffer *vb, u32 num_planes)
+{
+	struct vb2_cma_phys_buf *buf;
+	unsigned long t_size = 0;
+	phys_addr_t start;
+	size_t size;
+	int i;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		if (!buf->cacheable) {
+			pr_warning("This is non-cacheable buffer allocator\n");
+			return -EINVAL;
+		}
+
+		t_size += buf->size;
+	}
+
+	if (t_size > (unsigned long)SIZE_THRESHOLD) {
+		for (i = 0; i < num_planes; i++) {
+			buf = vb->planes[i].mem_priv;
+			start = buf->dma_addr;
+			size = buf->size;
+
+			dmac_unmap_area(phys_to_virt(start), size, DMA_TO_DEVICE);
+		}
+	} else {
+		for (i = 0; i < num_planes; i++) {
+			buf = vb->planes[i].mem_priv;
+			start = buf->dma_addr;
+			size = buf->size;
+
+			dmac_unmap_area(phys_to_virt(start), size, DMA_TO_DEVICE);
+			outer_clean_range(start, start + size - 1);	/* L2 */
+		}
+	}
+
+	return 0;
+}
+
+MODULE_AUTHOR("Jonghun, Han <jonghun.han@samsung.com>");
+MODULE_DESCRIPTION("CMA-phys allocator handling routines for videobuf2");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/videobuf2-core.c b/drivers/media/video/videobuf2-core.c
index 3015e60..7fd706a 100644
--- a/drivers/media/video/videobuf2-core.c
+++ b/drivers/media/video/videobuf2-core.c
@@ -48,18 +48,32 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb,
 {
 	struct vb2_queue *q = vb->vb2_queue;
 	void *mem_priv;
-	int plane;
+	int plane, ret, export_fd = 0;
 
 	/* Allocate memory for all planes in this buffer */
 	for (plane = 0; plane < vb->num_planes; ++plane) {
 		mem_priv = call_memop(q, plane, alloc, q->alloc_ctx[plane],
 					plane_sizes[plane]);
-		if (IS_ERR_OR_NULL(mem_priv))
+		if (IS_ERR_OR_NULL(mem_priv)) {
+			ret = -ENOMEM;
 			goto free;
+		}
 
 		/* Associate allocator private data with this plane */
 		vb->planes[plane].mem_priv = mem_priv;
 		vb->v4l2_planes[plane].length = plane_sizes[plane];
+
+		if (q->memory == V4L2_MEMORY_DMABUF) {
+			ret = call_memop(q, plane, export_dmabuf,
+						q->alloc_ctx[plane],
+						mem_priv, &export_fd);
+			if (ret < 0) {
+				dprintk(1, "failed to export buf to dmabuf.\n");
+				goto free;
+			}
+
+			vb->v4l2_planes[plane].m.fd = export_fd;
+		}
 	}
 
 	return 0;
@@ -68,7 +82,7 @@ free:
 	for (; plane > 0; --plane)
 		call_memop(q, plane, put, vb->planes[plane - 1].mem_priv);
 
-	return -ENOMEM;
+	return ret;
 }
 
 /**
@@ -107,6 +121,27 @@ static void __vb2_buf_userptr_put(struct vb2_buffer *vb)
 }
 
 /**
+ * __vb2_buf_dmabuf_put() - release memory associated with
+ * a DMABUF shared buffer
+ */
+static void __vb2_buf_dmabuf_put(struct vb2_buffer *vb)
+{
+	struct vb2_queue *q = vb->vb2_queue;
+	unsigned int plane;
+
+	for (plane = 0; plane < vb->num_planes; ++plane) {
+		void *mem_priv = vb->planes[plane].mem_priv;
+
+		if (mem_priv) {
+			call_memop(q, plane, detach_dmabuf, mem_priv);
+			dma_buf_put(vb->planes[plane].dbuf);
+			vb->planes[plane].dbuf = NULL;
+			vb->planes[plane].mem_priv = NULL;
+		}
+	}
+}
+
+/**
  * __setup_offsets() - setup unique offsets ("cookies") for every plane in
  * every buffer on the queue
  */
@@ -167,8 +202,9 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum v4l2_memory memory,
 		vb->v4l2_buf.type = q->type;
 		vb->v4l2_buf.memory = memory;
 
-		/* Allocate video buffer memory for the MMAP type */
-		if (memory == V4L2_MEMORY_MMAP) {
+		/* Allocate video buffer memory for the MMAP and DMABUF type */
+		if (memory == V4L2_MEMORY_MMAP ||
+					memory == V4L2_MEMORY_DMABUF) {
 			ret = __vb2_buf_mem_alloc(vb, plane_sizes);
 			if (ret) {
 				dprintk(1, "Failed allocating memory for "
@@ -220,6 +256,8 @@ static void __vb2_free_mem(struct vb2_queue *q)
 		/* Free MMAP buffers or release USERPTR buffers */
 		if (q->memory == V4L2_MEMORY_MMAP)
 			__vb2_buf_mem_free(vb);
+		if (q->memory == V4L2_MEMORY_DMABUF)
+			__vb2_buf_dmabuf_put(vb);
 		else
 			__vb2_buf_userptr_put(vb);
 	}
@@ -260,7 +298,8 @@ static void __vb2_queue_free(struct vb2_queue *q)
  * __verify_planes_array() - verify that the planes array passed in struct
  * v4l2_buffer from userspace can be safely used
  */
-static int __verify_planes_array(struct vb2_buffer *vb, struct v4l2_buffer *b)
+static int __verify_planes_array(struct vb2_buffer *vb,
+					const struct v4l2_buffer *b)
 {
 	/* Is memory for copying plane information present? */
 	if (NULL == b->m.planes) {
@@ -303,6 +342,14 @@ static int __fill_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b)
 		 */
 		memcpy(b->m.planes, vb->v4l2_planes,
 			b->length * sizeof(struct v4l2_plane));
+
+		if (q->memory == V4L2_MEMORY_DMABUF) {
+			unsigned int plane;
+
+			for (plane = 0; plane < vb->num_planes; ++plane)
+				b->m.planes[plane].m.fd =
+						vb->v4l2_planes[plane].m.fd;
+		}
 	} else {
 		/*
 		 * We use length and offset in v4l2_planes array even for
@@ -314,6 +361,8 @@ static int __fill_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b)
 			b->m.offset = vb->v4l2_planes[0].m.mem_offset;
 		else if (q->memory == V4L2_MEMORY_USERPTR)
 			b->m.userptr = vb->v4l2_planes[0].m.userptr;
+		else if (q->memory == V4L2_MEMORY_DMABUF)
+			b->m.fd = vb->v4l2_planes[0].m.fd;
 	}
 
 	/*
@@ -429,6 +478,21 @@ static bool __buffers_in_use(struct vb2_queue *q)
 }
 
 /**
+ * __verify_dmabuf_ops() - verify that all memory operations required for
+ * DMABUF queue type have been provided
+ */
+static int __verify_dmabuf_ops(struct vb2_queue *q)
+{
+	if (!(q->io_modes & VB2_DMABUF) || !q->mem_ops->attach_dmabuf
+			|| !q->mem_ops->detach_dmabuf
+			|| !q->mem_ops->map_dmabuf
+			|| !q->mem_ops->unmap_dmabuf)
+		return -EINVAL;
+
+	return 0;
+}
+
+/**
  * vb2_reqbufs() - Initiate streaming
  * @q:		videobuf2 queue
  * @req:	struct passed from userspace to vidioc_reqbufs handler in driver
@@ -463,6 +527,7 @@ int vb2_reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req)
 	}
 
 	if (req->memory != V4L2_MEMORY_MMAP
+			&& req->memory != V4L2_MEMORY_DMABUF
 			&& req->memory != V4L2_MEMORY_USERPTR) {
 		dprintk(1, "reqbufs: unsupported memory type\n");
 		return -EINVAL;
@@ -492,6 +557,11 @@ int vb2_reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req)
 		return -EINVAL;
 	}
 
+	if (req->memory == V4L2_MEMORY_DMABUF && __verify_dmabuf_ops(q)) {
+		dprintk(1, "reqbufs: DMABUF for current setup unsupported\n");
+		return -EINVAL;
+	}
+
 	if (req->count == 0 || q->num_buffers != 0 || q->memory != req->memory) {
 		/*
 		 * We already have buffers allocated, so first check if they
@@ -658,7 +728,7 @@ EXPORT_SYMBOL_GPL(vb2_buffer_done);
  * __fill_vb2_buffer() - fill a vb2_buffer with information provided in
  * a v4l2_buffer by the userspace
  */
-static int __fill_vb2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b,
+static int __fill_vb2_buffer(struct vb2_buffer *vb, const struct v4l2_buffer *b,
 				struct v4l2_plane *v4l2_planes)
 {
 	unsigned int plane;
@@ -695,6 +765,11 @@ static int __fill_vb2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b,
 					b->m.planes[plane].length;
 			}
 		}
+		if (b->memory == V4L2_MEMORY_DMABUF) {
+			for (plane = 0; plane < vb->num_planes; ++plane)
+				v4l2_planes[plane].m.fd =
+						b->m.planes[plane].m.fd;
+		}
 	} else {
 		/*
 		 * Single-planar buffers do not use planes array,
@@ -709,6 +784,8 @@ static int __fill_vb2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b,
 			v4l2_planes[0].m.userptr = b->m.userptr;
 			v4l2_planes[0].length = b->length;
 		}
+		if (b->memory == V4L2_MEMORY_DMABUF)
+			v4l2_planes[0].m.fd = b->m.fd;
 	}
 
 	vb->v4l2_buf.field = b->field;
@@ -806,14 +883,117 @@ static int __qbuf_mmap(struct vb2_buffer *vb, struct v4l2_buffer *b)
 }
 
 /**
+ * __qbuf_dmabuf() - handle qbuf of a DMABUF buffer
+ */
+static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b)
+{
+	struct v4l2_plane planes[VIDEO_MAX_PLANES];
+	struct vb2_queue *q = vb->vb2_queue;
+	void *mem_priv;
+	unsigned int plane;
+	int ret;
+
+	/* Verify and copy relevant information provided by the userspace */
+	ret = __fill_vb2_buffer(vb, b, planes);
+	if (ret)
+		return ret;
+
+	for (plane = 0; plane < vb->num_planes; ++plane) {
+		struct dma_buf *dbuf = dma_buf_get(planes[plane].m.fd);
+
+		if (IS_ERR_OR_NULL(dbuf)) {
+			dprintk(1, "qbuf: invalid dmabuf fd for "
+					"plane %d\n", plane);
+			ret = PTR_ERR(dbuf);
+			goto err;
+		}
+
+		/* this doesn't get filled in until __fill_vb2_buffer(),
+		 * since it isn't known until after dma_buf_get()..
+		 */
+		planes[plane].length = dbuf->size;
+
+		/* Skip the plane if already verified */
+		if (dbuf == vb->planes[plane].dbuf) {
+			dma_buf_put(dbuf);
+			continue;
+		}
+
+		dprintk(3, "qbuf: buffer descriptor for plane %d changed, "
+				"reattaching dma buf\n", plane);
+
+		/* Release previously acquired memory if present */
+		if (vb->planes[plane].mem_priv) {
+			call_memop(q, plane, detach_dmabuf,
+					vb->planes[plane].mem_priv);
+			dma_buf_put(vb->planes[plane].dbuf);
+		}
+
+		vb->planes[plane].mem_priv = NULL;
+
+		/* Acquire each plane's memory */
+		mem_priv = q->mem_ops->attach_dmabuf(
+				q->alloc_ctx[plane], dbuf);
+		if (IS_ERR(mem_priv)) {
+			dprintk(1, "qbuf: failed acquiring dmabuf "
+					"memory for plane %d\n", plane);
+			ret = PTR_ERR(mem_priv);
+			goto err;
+		}
+
+		vb->planes[plane].dbuf = dbuf;
+		vb->planes[plane].mem_priv = mem_priv;
+	}
+
+	/*
+	 * TODO this pins the buffer (dma_buf_map_attachment()).. but
+	 * really we want to do this just before DMA, not when the
+	 * buffer is queued..
+	 */
+	 call_memop(q, plane, map_dmabuf, vb->planes[plane].mem_priv);
+
+	/*
+	 * Call driver-specific initialization on the newly acquired buffer,
+	 * if provided.
+	 */
+	ret = call_qop(q, buf_init, vb);
+	if (ret) {
+		dprintk(1, "qbuf: buffer initialization failed\n");
+		goto err;
+	}
+
+	/*
+	 * Now that everything is in order, copy relevant information
+	 * provided by userspace.
+	 */
+	for (plane = 0; plane < vb->num_planes; ++plane)
+		vb->v4l2_planes[plane] = planes[plane];
+
+	return 0;
+err:
+	/* In case of errors, release planes that were already acquired */
+	__vb2_buf_dmabuf_put(vb);
+
+	return ret;
+}
+
+/**
  * __enqueue_in_driver() - enqueue a vb2_buffer in driver for processing
  */
 static void __enqueue_in_driver(struct vb2_buffer *vb)
 {
 	struct vb2_queue *q = vb->vb2_queue;
+	void *privs[VIDEO_MAX_PLANES];
+	int plane;
 
 	vb->state = VB2_BUF_STATE_ACTIVE;
 	atomic_inc(&q->queued_count);
+
+	for (plane = 0; plane < vb->num_planes; plane++)
+		privs[plane] = vb->planes[plane].mem_priv;
+
+	call_memop(q, plane, sync_to_dev, q->alloc_ctx, privs, vb->num_planes,
+			vb->v4l2_buf.type);
 	q->ops->buf_queue(vb);
 }
 
@@ -875,6 +1055,8 @@ int vb2_qbuf(struct vb2_queue *q, struct v4l2_buffer *b)
 		ret = __qbuf_mmap(vb, b);
 	else if (q->memory == V4L2_MEMORY_USERPTR)
 		ret = __qbuf_userptr(vb, b);
+	else if (q->memory == V4L2_MEMORY_DMABUF)
+			ret = __qbuf_dmabuf(vb, b);
 	else {
 		WARN(1, "Invalid queue type\n");
 		return -EINVAL;
@@ -1046,6 +1228,7 @@ EXPORT_SYMBOL_GPL(vb2_wait_for_all_buffers);
 int vb2_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool nonblocking)
 {
 	struct vb2_buffer *vb = NULL;
+	int plane;
 	int ret;
 
 	if (q->fileio) {
@@ -1070,8 +1253,27 @@ int vb2_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool nonblocking)
 		return ret;
 	}
 
+	/*
+	 * TODO this unpins the buffer (dma_buf_unmap_attachment()).. but
+	 * really we want to do this just after DMA, not when the
+	 * buffer is dequeued..
+	 */
+	if (q->memory == V4L2_MEMORY_DMABUF)
+		for (plane = 0; plane < vb->num_planes; ++plane)
+			call_memop(q, plane, unmap_dmabuf,
+					vb->planes[plane].mem_priv);
+
 	switch (vb->state) {
 	case VB2_BUF_STATE_DONE:
+		{
+			void *privs[VIDEO_MAX_PLANES];
+
+			for (plane = 0; plane < vb->num_planes; plane++)
+				privs[plane] = vb->planes[plane].mem_priv;
+
+			call_memop(q, plane, sync_from_dev, q->alloc_ctx, privs,
+					vb->num_planes, vb->v4l2_buf.type);
+		}
 		dprintk(3, "dqbuf: Returning done buffer\n");
 		break;
 	case VB2_BUF_STATE_ERROR:
diff --git a/drivers/media/video/videobuf2-dma-contig.c b/drivers/media/video/videobuf2-dma-contig.c
index a790a5f..071a3bf 100644
--- a/drivers/media/video/videobuf2-dma-contig.c
+++ b/drivers/media/video/videobuf2-dma-contig.c
@@ -13,6 +13,8 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-buf.h>
 
 #include <media/videobuf2-core.h>
 #include <media/videobuf2-memops.h>
@@ -24,25 +26,32 @@ struct vb2_dc_conf {
 struct vb2_dc_buf {
 	struct vb2_dc_conf		*conf;
 	void				*vaddr;
-	dma_addr_t			paddr;
+	dma_addr_t			dma_addr;
 	unsigned long			size;
 	struct vm_area_struct		*vma;
+	struct dma_buf_attachment	*db_attach;
 	atomic_t			refcount;
 	struct vb2_vmarea_handler	handler;
 };
 
+struct vb2_dc_db_attach {
+	struct vb2_dc_buf		*buf;
+	struct dma_buf_attachment	db_attach;
+};
+
 static void vb2_dma_contig_put(void *buf_priv);
 
 static void *vb2_dma_contig_alloc(void *alloc_ctx, unsigned long size)
 {
 	struct vb2_dc_conf *conf = alloc_ctx;
 	struct vb2_dc_buf *buf;
+	/* TODO: add db_attach processing while adding DMABUF as exporter */
 
 	buf = kzalloc(sizeof *buf, GFP_KERNEL);
 	if (!buf)
 		return ERR_PTR(-ENOMEM);
 
-	buf->vaddr = dma_alloc_coherent(conf->dev, size, &buf->paddr,
+	buf->vaddr = dma_alloc_coherent(conf->dev, size, &buf->dma_addr,
 					GFP_KERNEL);
 	if (!buf->vaddr) {
 		dev_err(conf->dev, "dma_alloc_coherent of size %ld failed\n",
@@ -69,7 +78,7 @@ static void vb2_dma_contig_put(void *buf_priv)
 
 	if (atomic_dec_and_test(&buf->refcount)) {
 		dma_free_coherent(buf->conf->dev, buf->size, buf->vaddr,
-				  buf->paddr);
+				  buf->dma_addr);
 		kfree(buf);
 	}
 }
@@ -78,7 +87,7 @@ static void *vb2_dma_contig_cookie(void *buf_priv)
 {
 	struct vb2_dc_buf *buf = buf_priv;
 
-	return &buf->paddr;
+	return &buf->dma_addr;
 }
 
 static void *vb2_dma_contig_vaddr(void *buf_priv)
@@ -106,7 +115,9 @@ static int vb2_dma_contig_mmap(void *buf_priv, struct vm_area_struct *vma)
 		return -EINVAL;
 	}
 
-	return vb2_mmap_pfn_range(vma, buf->paddr, buf->size,
+	WARN_ON(buf->db_attach);
+
+	return vb2_mmap_pfn_range(vma, buf->dma_addr, buf->size,
 				  &vb2_common_vm_ops, &buf->handler);
 }
 
@@ -115,14 +126,14 @@ static void *vb2_dma_contig_get_userptr(void *alloc_ctx, unsigned long vaddr,
 {
 	struct vb2_dc_buf *buf;
 	struct vm_area_struct *vma;
-	dma_addr_t paddr = 0;
+	dma_addr_t dma_addr = 0;
 	int ret;
 
 	buf = kzalloc(sizeof *buf, GFP_KERNEL);
 	if (!buf)
 		return ERR_PTR(-ENOMEM);
 
-	ret = vb2_get_contig_userptr(vaddr, size, &vma, &paddr);
+	ret = vb2_get_contig_userptr(vaddr, size, &vma, &dma_addr);
 	if (ret) {
 		printk(KERN_ERR "Failed acquiring VMA for vaddr 0x%08lx\n",
 				vaddr);
@@ -131,7 +142,7 @@ static void *vb2_dma_contig_get_userptr(void *alloc_ctx, unsigned long vaddr,
 	}
 
 	buf->size = size;
-	buf->paddr = paddr;
+	buf->dma_addr = dma_addr;
 	buf->vma = vma;
 
 	return buf;
@@ -148,6 +159,110 @@ static void vb2_dma_contig_put_userptr(void *mem_priv)
 	kfree(buf);
 }
 
+static void vb2_dma_contig_map_dmabuf(void *mem_priv)
+{
+	struct vb2_dc_buf *buf = mem_priv;
+	struct dma_buf *dmabuf;
+	struct sg_table *sg;
+	enum dma_data_direction dir;
+
+	if (!buf || !buf->db_attach)
+		return;
+
+	WARN_ON(buf->dma_addr);
+
+	dmabuf = buf->db_attach->dmabuf;
+
+	/* TODO need a way to know if we are camera or display, etc.. */
+	dir = DMA_BIDIRECTIONAL;
+
+	/* get the associated sg for this buffer */
+	sg = dma_buf_map_attachment(buf->db_attach, dir);
+	if (!sg)
+		return;
+
+	/*
+	 *  convert sglist to paddr:
+	 *  Assumption: for dma-contig, dmabuf would map to single entry
+	 *  Will print a warning if it has more than one.
+	 */
+	if (sg->nents > 1)
+		printk(KERN_WARNING
+			"dmabuf scatterlist has more than 1 entry\n");
+
+	buf->dma_addr = sg_dma_address(sg->sgl);
+	buf->size = sg_dma_len(sg->sgl);
+
+	/* save this sg in dmabuf for put_scatterlist */
+	dmabuf->priv = sg;
+}
+
+static void vb2_dma_contig_unmap_dmabuf(void *mem_priv)
+{
+	struct vb2_dc_buf *buf = mem_priv;
+	struct dma_buf *dmabuf;
+	struct sg_table *sg;
+
+	if (!buf || !buf->db_attach)
+		return;
+
+	WARN_ON(!buf->dma_addr);
+
+	dmabuf = buf->db_attach->dmabuf;
+	sg = dmabuf->priv;
+
+	/*
+	 * Put the sg for this buffer:
+	 */
+	dma_buf_unmap_attachment(buf->db_attach, sg, DMA_FROM_DEVICE);
+
+	buf->dma_addr = 0;
+	buf->size = 0;
+}
+
+static void *vb2_dma_contig_attach_dmabuf(void *alloc_ctx, struct dma_buf *dbuf)
+{
+	struct vb2_dc_conf *conf = alloc_ctx;
+	struct vb2_dc_buf *buf;
+	struct dma_buf_attachment *dba;
+
+	buf = kzalloc(sizeof *buf, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	/* create attachment for the dmabuf with the user device */
+	dba = dma_buf_attach(dbuf, conf->dev);
+	if (IS_ERR(dba)) {
+		printk(KERN_ERR "failed to attach dmabuf\n");
+		kfree(buf);
+		return dba;
+	}
+
+	buf->conf = conf;
+	buf->size = dba->dmabuf->size;
+	buf->db_attach = dba;
+	buf->dma_addr = 0; /* dma_addr is available only after acquire */
+
+	return buf;
+}
+
+static void vb2_dma_contig_detach_dmabuf(void *mem_priv)
+{
+	struct vb2_dc_buf *buf = mem_priv;
+
+	if (!buf)
+		return;
+
+	if (buf->dma_addr)
+		vb2_dma_contig_unmap_dmabuf(buf);
+
+	/* detach this attachment */
+	dma_buf_detach(buf->db_attach->dmabuf, buf->db_attach);
+	buf->db_attach = NULL;
+
+	kfree(buf);
+}
+
 const struct vb2_mem_ops vb2_dma_contig_memops = {
 	.alloc		= vb2_dma_contig_alloc,
 	.put		= vb2_dma_contig_put,
@@ -156,6 +271,10 @@ const struct vb2_mem_ops vb2_dma_contig_memops = {
 	.mmap		= vb2_dma_contig_mmap,
 	.get_userptr	= vb2_dma_contig_get_userptr,
 	.put_userptr	= vb2_dma_contig_put_userptr,
+	.map_dmabuf	= vb2_dma_contig_map_dmabuf,
+	.unmap_dmabuf	= vb2_dma_contig_unmap_dmabuf,
+	.attach_dmabuf	= vb2_dma_contig_attach_dmabuf,
+	.detach_dmabuf	= vb2_dma_contig_detach_dmabuf,
 	.num_users	= vb2_dma_contig_num_users,
 };
 EXPORT_SYMBOL_GPL(vb2_dma_contig_memops);
diff --git a/drivers/media/video/videobuf2-ion.c b/drivers/media/video/videobuf2-ion.c
new file mode 100644
index 0000000..00d6017
--- /dev/null
+++ b/drivers/media/video/videobuf2-ion.c
@@ -0,0 +1,755 @@
+/* linux/drivers/media/video/videobuf2-ion.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Implementation of Android ION memory allocator for videobuf2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/file.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/highmem.h>
+
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-memops.h>
+#include <media/videobuf2-ion.h>
+
+#include <asm/cacheflush.h>
+
+#include <plat/iovmm.h>
+#include <plat/cpu.h>
+
+extern struct ion_device *ion_exynos; /* drivers/gpu/ion/exynos/exynos-ion.c */
+
+struct vb2_ion_context {
+	struct device		*dev;
+	struct ion_client	*client;
+	unsigned long		alignment;
+	long			flags;
+};
+
+struct vb2_ion_buf {
+	struct vm_area_struct		**vmas;
+	int				vma_count;
+	struct vb2_ion_context		*ctx;
+	struct vb2_vmarea_handler	handler;
+	struct ion_handle		*handle;
+	void				*kva;
+	unsigned long			size;
+	atomic_t			ref;
+	bool				cached;
+	struct vb2_ion_cookie		cookie;
+};
+
+#define ctx_cached(ctx) (!(ctx->flags & VB2ION_CTX_UNCACHED))
+#define ctx_iommu(ctx) (!!(ctx->flags & VB2ION_CTX_IOMMU))
+
+void vb2_ion_set_cached(void *ctx, bool cached)
+{
+	struct vb2_ion_context *vb2ctx = ctx;
+
+	if (cached)
+		vb2ctx->flags &= ~VB2ION_CTX_UNCACHED;
+	else
+		vb2ctx->flags |= VB2ION_CTX_UNCACHED;
+}
+EXPORT_SYMBOL(vb2_ion_set_cached);
+
+int vb2_ion_set_alignment(void *ctx, size_t alignment)
+{
+	struct vb2_ion_context *vb2ctx = ctx;
+
+	if ((alignment != 0) && (alignment < PAGE_SIZE))
+		return -EINVAL;
+
+	if (alignment & ~alignment)
+		return -EINVAL;
+
+	if (alignment == 0)
+		vb2ctx->alignment = PAGE_SIZE;
+	else
+		vb2ctx->alignment = alignment;
+
+	return 0;
+}
+EXPORT_SYMBOL(vb2_ion_set_alignment);
+
+void *vb2_ion_create_context(struct device *dev, size_t alignment, long flags)
+{
+	struct vb2_ion_context *ctx;
+	int ret;
+	unsigned int heapmask = ION_HEAP_EXYNOS_USER_MASK;
+
+	/* ion_client_create() expects the current thread to be a kernel thread
+	 * to create a new ion_client
+	 */
+	WARN_ON(!(current->group_leader->flags & PF_KTHREAD));
+
+	if (flags & VB2ION_CTX_PHCONTIG)
+		heapmask |= ION_HEAP_EXYNOS_CONTIG_MASK;
+	if (flags & VB2ION_CTX_VMCONTIG)
+		heapmask |= ION_HEAP_EXYNOS_MASK;
+
+	 /* non-contigous memory without H/W virtualization is not supported */
+	if ((flags & VB2ION_CTX_VMCONTIG) && !(flags & VB2ION_CTX_IOMMU))
+		return ERR_PTR(-EINVAL);
+
+	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return ERR_PTR(-ENOMEM);
+
+	ctx->dev = dev;
+	ctx->client = ion_client_create(ion_exynos, heapmask, dev_name(dev));
+	if (IS_ERR(ctx->client)) {
+		ret = PTR_ERR(ctx->client);
+		goto err_ion;
+	}
+
+	if (flags & VB2ION_CTX_IOMMU) {
+		ret = iovmm_setup(dev);
+		if (ret)
+			goto err_iovmm;
+	}
+
+	vb2_ion_set_alignment(ctx, alignment);
+	ctx->flags = flags;
+
+	return ctx;
+
+err_iovmm:
+	ion_client_destroy(ctx->client);
+err_ion:
+	kfree(ctx);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(vb2_ion_create_context);
+
+void vb2_ion_destroy_context(void *ctx)
+{
+	struct vb2_ion_context *vb2ctx = ctx;
+
+	ion_client_destroy(vb2ctx->client);
+	iovmm_cleanup(vb2ctx->dev);
+	kfree(vb2ctx);
+}
+EXPORT_SYMBOL(vb2_ion_destroy_context);
+
+void *vb2_ion_private_alloc(void *alloc_ctx, size_t size)
+{
+	struct vb2_ion_context *ctx = alloc_ctx;
+	struct vb2_ion_buf *buf;
+	struct scatterlist *sg;
+	int ret = 0;
+
+	buf = kzalloc(sizeof(*buf), GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	size = PAGE_ALIGN(size);
+
+	buf->handle = ion_alloc(ctx->client, size, ctx->alignment,
+				ion_heapflag(ctx->flags));
+	if (IS_ERR(buf->handle)) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	buf->cookie.sg = ion_map_dma(ctx->client, buf->handle);
+	if (IS_ERR(buf->cookie.sg)) {
+		ret = -ENOMEM;
+		goto err_map_dma;
+	}
+
+	buf->ctx = ctx;
+	buf->size = size;
+	buf->cached = ctx_cached(ctx);
+
+	sg = buf->cookie.sg;
+	do {
+		buf->cookie.nents++;
+	} while ((sg = sg_next(sg)));
+
+	buf->kva = ion_map_kernel(ctx->client, buf->handle);
+	if (IS_ERR(buf->kva)) {
+		ret = PTR_ERR(buf->kva);
+		buf->kva = NULL;
+		goto err_map_kernel;
+	}
+
+	if (ctx_iommu(ctx)) {
+		buf->cookie.ioaddr = iovmm_map(ctx->dev,
+						buf->cookie.sg, 0, size);
+		if (!buf->cookie.ioaddr) {
+			ret = -EFAULT;
+			goto err_ion_map_io;
+		}
+	}
+
+	return &buf->cookie;
+
+err_ion_map_io:
+	ion_unmap_kernel(ctx->client, buf->handle);
+err_map_kernel:
+	ion_unmap_dma(ctx->client, buf->handle);
+err_map_dma:
+	ion_free(ctx->client, buf->handle);
+err_alloc:
+	kfree(buf);
+
+	return ERR_PTR(ret);
+}
+
+void vb2_ion_private_free(void *cookie)
+{
+	struct vb2_ion_buf *buf =
+			container_of(cookie, struct vb2_ion_buf, cookie);
+	struct vb2_ion_context *ctx;
+
+	if (WARN_ON(IS_ERR_OR_NULL(cookie)))
+		return;
+
+	ctx = buf->ctx;
+	if (ctx_iommu(ctx))
+		iovmm_unmap(ctx->dev, buf->cookie.ioaddr);
+
+	ion_unmap_kernel(ctx->client, buf->handle);
+	ion_unmap_dma(ctx->client, buf->handle);
+	ion_free(ctx->client, buf->handle);
+
+	kfree(buf);
+}
+
+static void vb2_ion_put(void *buf_priv)
+{
+	struct vb2_ion_buf *buf = buf_priv;
+
+	if (atomic_dec_and_test(&buf->ref))
+		vb2_ion_private_free(&buf->cookie);
+}
+
+static void *vb2_ion_alloc(void *alloc_ctx, unsigned long size)
+{
+	struct vb2_ion_buf *buf;
+	void *cookie;
+
+	cookie = vb2_ion_private_alloc(alloc_ctx, size);
+	if (IS_ERR(cookie))
+		return cookie;
+
+	buf = container_of(cookie, struct vb2_ion_buf, cookie);
+
+	buf->handler.refcount = &buf->ref;
+	buf->handler.put = vb2_ion_put;
+	buf->handler.arg = buf;
+	atomic_set(&buf->ref, 1);
+
+	return buf;
+}
+
+void *vb2_ion_private_vaddr(void *cookie)
+{
+	if (WARN_ON(IS_ERR_OR_NULL(cookie)))
+		return NULL;
+
+	return container_of(cookie, struct vb2_ion_buf, cookie)->kva;
+}
+
+/**
+ * _vb2_ion_get_vma() - lock userspace mapped memory
+ * @vaddr:	starting virtual address of the area to be verified
+ * @size:	size of the area
+ * @vma_num:	number of returned vma copies
+ *
+ * This function will go through memory area of size @size mapped at @vaddr
+ * If they are contiguous, the virtual memory area is locked, this function
+ * returns the array of vma copies of the given area and vma_num becomes
+ * the number of vmas returned.
+ *
+ * Returns 0 on success.
+ */
+static struct vm_area_struct **_vb2_ion_get_vma(unsigned long vaddr,
+					unsigned long size, int *vma_num)
+{
+	struct mm_struct *mm = current->mm;
+	struct vm_area_struct *vma, *vma0;
+	struct vm_area_struct **vmas;
+	unsigned long prev_end = 0;
+	unsigned long end;
+	int i;
+
+	end = vaddr + size;
+
+	down_read(&mm->mmap_sem);
+	vma0 = find_vma(mm, vaddr);
+	if (!vma0) {
+		vmas = ERR_PTR(-EINVAL);
+		goto done;
+	}
+
+	for (*vma_num = 1, vma = vma0->vm_next, prev_end = vma0->vm_end;
+		vma && (end > vma->vm_start) && (prev_end == vma->vm_start);
+				prev_end = vma->vm_end, vma = vma->vm_next) {
+		*vma_num += 1;
+	}
+
+	if (prev_end < end) {
+		vmas = ERR_PTR(-EINVAL);
+		goto done;
+	}
+
+	vmas = kmalloc(sizeof(*vmas) * *vma_num, GFP_KERNEL);
+	if (!vmas) {
+		vmas = ERR_PTR(-ENOMEM);
+		goto done;
+	}
+
+	for (i = 0; i < *vma_num; i++, vma0 = vma0->vm_next) {
+		vmas[i] = vb2_get_vma(vma0);
+		if (!vmas[i])
+			break;
+	}
+
+	if (i < *vma_num) {
+		while (i-- > 0)
+			vb2_put_vma(vmas[i]);
+
+		kfree(vmas);
+		vmas = ERR_PTR(-ENOMEM);
+	}
+
+done:
+	up_read(&mm->mmap_sem);
+	return vmas;
+}
+
+static void *vb2_ion_get_userptr(void *alloc_ctx, unsigned long vaddr,
+				 unsigned long size, int write)
+{
+	struct vb2_ion_context *ctx = alloc_ctx;
+	struct vb2_ion_buf *buf = NULL;
+	int ret = 0;
+	struct scatterlist *sg;
+	off_t offset;
+
+	buf = kzalloc(sizeof *buf, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	buf->handle = ion_import_uva(ctx->client, vaddr, &offset);
+	if (IS_ERR(buf->handle)) {
+		if (PTR_ERR(buf->handle) == -ENXIO) {
+			int flags = ION_HEAP_EXYNOS_USER_MASK;
+
+			if (write)
+				flags |= ION_EXYNOS_WRITE_MASK;
+
+			buf->handle = ion_exynos_get_user_pages(ctx->client,
+							vaddr, size, flags);
+			if (IS_ERR(buf->handle))
+				ret = PTR_ERR(buf->handle);
+		} else {
+			ret = -EINVAL;
+		}
+
+		if (ret) {
+			pr_err("%s: Failed to retrieving non-ion user buffer @ "
+				"0x%lx (size:0x%lx, dev:%s, errno %ld)\n",
+				__func__, vaddr, size, dev_name(ctx->dev),
+					PTR_ERR(buf->handle));
+			goto err_import_uva;
+		}
+
+		offset = 0;
+	}
+
+	buf->cookie.sg = ion_map_dma(ctx->client, buf->handle);
+	if (IS_ERR(buf->cookie.sg)) {
+		ret = -ENOMEM;
+		goto err_map_dma;
+	}
+
+	sg = buf->cookie.sg;
+	do {
+		buf->cookie.nents++;
+	} while ((sg = sg_next(sg)));
+
+	if (ctx_iommu(ctx)) {
+		buf->cookie.ioaddr = iovmm_map(ctx->dev, buf->cookie.sg,
+						offset, size);
+		if (!buf->cookie.ioaddr) {
+			ret = -EFAULT;
+			goto err_ion_map_io;
+		}
+	}
+
+	buf->vmas = _vb2_ion_get_vma(vaddr, size, &buf->vma_count);
+	if (IS_ERR(buf->vmas)) {
+		ret = PTR_ERR(buf->vmas);
+		goto err_get_vma;
+	}
+
+	buf->kva = ion_map_kernel(ctx->client, buf->handle);
+	if (IS_ERR(buf->kva)) {
+		ret = PTR_ERR(buf->kva);
+		buf->kva = NULL;
+		goto err_map_kernel;
+	}
+
+	if ((pgprot_noncached(buf->vmas[0]->vm_page_prot)
+				== buf->vmas[0]->vm_page_prot)
+			|| (pgprot_writecombine(buf->vmas[0]->vm_page_prot)
+				== buf->vmas[0]->vm_page_prot))
+		buf->cached = false;
+	else
+		buf->cached = true;
+
+	buf->cookie.offset = offset;
+	buf->ctx = ctx;
+	buf->size = size;
+
+	return buf;
+
+err_map_kernel:
+	while (buf->vma_count-- > 0)
+		vb2_put_vma(buf->vmas[buf->vma_count]);
+	kfree(buf->vmas);
+err_get_vma:
+	if (ctx_iommu(ctx))
+		iovmm_unmap(ctx->dev, buf->cookie.ioaddr);
+err_ion_map_io:
+	ion_unmap_dma(ctx->client, buf->handle);
+err_map_dma:
+	ion_free(ctx->client, buf->handle);
+err_import_uva:
+	kfree(buf);
+
+	return ERR_PTR(ret);
+}
+
+static void vb2_ion_put_userptr(void *mem_priv)
+{
+	struct vb2_ion_buf *buf = mem_priv;
+	struct vb2_ion_context *ctx = buf->ctx;
+	int i;
+
+	if (ctx_iommu(ctx))
+		iovmm_unmap(ctx->dev, buf->cookie.ioaddr);
+
+	ion_unmap_dma(ctx->client, buf->handle);
+	if (buf->kva)
+		ion_unmap_kernel(ctx->client, buf->handle);
+
+	ion_free(ctx->client, buf->handle);
+
+	for (i = 0; i < buf->vma_count; i++)
+		vb2_put_vma(buf->vmas[i]);
+
+	kfree(buf->vmas);
+	kfree(buf);
+}
+
+static void *vb2_ion_cookie(void *buf_priv)
+{
+	struct vb2_ion_buf *buf = buf_priv;
+
+	if (WARN_ON(!buf))
+		return NULL;
+
+	return (void *)&buf->cookie;
+}
+
+static void *vb2_ion_vaddr(void *buf_priv)
+{
+	struct vb2_ion_buf *buf = buf_priv;
+
+	if (WARN_ON(!buf))
+		return NULL;
+
+	return buf->kva;
+}
+
+static unsigned int vb2_ion_num_users(void *buf_priv)
+{
+	struct vb2_ion_buf *buf = buf_priv;
+
+	if (WARN_ON(!buf))
+		return 0;
+
+	return atomic_read(&buf->ref);
+}
+
+static int vb2_ion_mmap(void *buf_priv, struct vm_area_struct *vma)
+{
+	struct vb2_ion_buf *buf = buf_priv;
+	unsigned long vm_start = vma->vm_start;
+	unsigned long vm_end = vma->vm_end;
+	struct scatterlist *sg = buf->cookie.sg;
+	unsigned long size;
+	int ret = -EINVAL;
+
+	if (buf->size  < (vm_end - vm_start))
+		return ret;
+
+	if (!buf->cached)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	size = min_t(size_t, vm_end - vm_start, sg_dma_len(sg));
+
+	ret = remap_pfn_range(vma, vm_start, page_to_pfn(sg_page(sg)),
+				size, vma->vm_page_prot);
+
+	for (sg = sg_next(sg), vm_start += size;
+			!ret && sg && (vm_start < vm_end);
+			vm_start += size, sg = sg_next(sg)) {
+		size = min_t(size_t, vm_end - vm_start, sg_dma_len(sg));
+		ret = remap_pfn_range(vma, vm_start, page_to_pfn(sg_page(sg)),
+						size, vma->vm_page_prot);
+	}
+
+	if (ret)
+		return ret;
+
+	if (vm_start < vm_end)
+		return -EINVAL;
+
+	vma->vm_flags		|= VM_DONTEXPAND;
+	vma->vm_private_data	= &buf->handler;
+	vma->vm_ops		= &vb2_common_vm_ops;
+
+	vma->vm_ops->open(vma);
+
+	return ret;
+}
+
+const struct vb2_mem_ops vb2_ion_memops = {
+	.alloc		= vb2_ion_alloc,
+	.put		= vb2_ion_put,
+	.cookie		= vb2_ion_cookie,
+	.vaddr		= vb2_ion_vaddr,
+	.mmap		= vb2_ion_mmap,
+	.get_userptr	= vb2_ion_get_userptr,
+	.put_userptr	= vb2_ion_put_userptr,
+	.num_users	= vb2_ion_num_users,
+};
+EXPORT_SYMBOL_GPL(vb2_ion_memops);
+
+void vb2_ion_sync_for_device(void *cookie, off_t offset, size_t size,
+						enum dma_data_direction dir)
+{
+	struct vb2_ion_cookie *vb2cookie = cookie;
+	struct vb2_ion_context *ctx =
+			container_of(cookie, struct vb2_ion_buf, cookie)->ctx;
+	struct scatterlist *sg;
+
+	for (sg = vb2cookie->sg; sg != NULL; sg = sg_next(sg)) {
+		if (sg_dma_len(sg) <= offset)
+			offset -= sg_dma_len(sg);
+		else
+			break;
+	}
+
+	if (WARN_ON(sg == NULL)) /* Too big offset */
+		return;
+
+	while ((size != 0) && (sg != NULL)) {
+		size_t sg_size;
+
+		sg_size = min_t(size_t, size, sg_dma_len(sg) - offset);
+		dma_map_page(ctx->dev, sg_page(sg) + PFN_DOWN(offset),
+				offset & ~PAGE_MASK, sg_size, dir);
+
+		offset = 0;
+		size -= sg_size;
+		sg = sg_next(sg);
+	}
+
+	WARN_ON(size != 0); /* Too big size */
+}
+EXPORT_SYMBOL_GPL(vb2_ion_sync_for_device);
+
+void vb2_ion_sync_for_cpu(void *cookie, off_t offset, size_t size,
+						enum dma_data_direction dir)
+{
+	struct vb2_ion_cookie *vb2cookie = cookie;
+	struct vb2_ion_context *ctx =
+			container_of(cookie, struct vb2_ion_buf, cookie)->ctx;
+	struct scatterlist *sg;
+
+	for (sg = vb2cookie->sg; sg != NULL; sg = sg_next(sg)) {
+		if (sg_dma_len(sg) <= offset)
+			offset -= sg_dma_len(sg);
+		else
+			break;
+	}
+
+	if (WARN_ON(sg == NULL)) /* Too big offset */
+		return;
+
+	while ((size != 0) && (sg != NULL)) {
+		size_t sg_size;
+
+		sg_size = min_t(size_t, size, sg_dma_len(sg) - offset);
+		dma_unmap_page(ctx->dev, sg_phys(sg) + offset, sg_size, dir);
+
+		offset = 0;
+		size -= sg_size;
+		sg = sg_next(sg);
+	}
+
+	WARN_ON(size != 0); /* Too big size */
+}
+EXPORT_SYMBOL_GPL(vb2_ion_sync_for_cpu);
+
+static void flush_entire_dcache(void *p)
+{
+	flush_cache_all();
+}
+
+int vb2_ion_cache_flush(struct vb2_buffer *vb, u32 num_planes)
+{
+	int i;
+	size_t sz = 0;
+	struct vb2_ion_buf *buf;
+	enum dma_data_direction dir;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		if (!buf->cached)
+			continue;
+
+		sz += buf->size;
+	}
+
+	if (sz >= SZ_2M) { /* performance tuning */
+		smp_call_function(&flush_entire_dcache, NULL, 1);
+		outer_flush_all();
+		return 0;
+	}
+
+	dir = V4L2_TYPE_IS_OUTPUT(vb->v4l2_buf.type) ?
+					DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+	while (num_planes-- > 0) {
+		struct scatterlist *sg;
+		off_t start_off;
+		int num_pages;
+		struct page *page;
+
+		buf = vb->planes[num_planes].mem_priv;
+		if (!buf->cached)
+			continue;
+
+		sg = buf->cookie.sg;
+		start_off = buf->cookie.offset;
+		sz = buf->size;
+
+		while (sg && (start_off >= sg_dma_len(sg))) {
+			start_off -= sg_dma_len(sg);
+			sg = sg_next(sg);
+		}
+
+		for (; (sg != NULL) && (sz > 0); sg = sg_next(sg)) {
+			int pages_to_pass;
+			void *addr;
+			bool kmapped = false;
+
+			start_off += sg->offset;
+
+			num_pages = PFN_DOWN(
+				PAGE_ALIGN(sg_dma_len(sg) + sg->offset));
+			pages_to_pass = PFN_DOWN(
+					round_down(start_off, PAGE_SIZE));
+			num_pages -= pages_to_pass;
+
+			page = sg_page(sg) + pages_to_pass;
+			start_off &= ~PAGE_MASK;
+
+			for (i = 0; (i < num_pages) && (sz > 0); i++, page++) {
+				size_t szflush;
+
+				szflush = min_t(size_t,
+						PAGE_SIZE - start_off, sz);
+
+				addr = page_address(page);
+				if (!addr) {
+					addr = kmap_atomic(page);
+					kmapped = true;
+				}
+
+				dmac_map_area(addr + start_off, szflush, dir);
+
+				if (dir == DMA_TO_DEVICE)
+					outer_clean_range(
+						page_to_phys(page) + start_off,
+						page_to_phys(page) + szflush);
+				else
+					outer_inv_range(
+						page_to_phys(page) + start_off,
+						page_to_phys(page) + szflush);
+
+				if (kmapped) {
+					kunmap_atomic(addr);
+					kmapped = false;
+				}
+
+				sz -= szflush;
+				start_off = 0;
+			}
+		}
+
+		WARN_ON(sz > 0);
+	}
+
+	return 0;
+}
+
+int vb2_ion_cache_inv(struct vb2_buffer *vb, u32 num_planes)
+{
+	struct vb2_ion_buf *buf;
+	int i;
+
+	for (i = 0; i < num_planes; i++) {
+		buf = vb->planes[i].mem_priv;
+		if (!buf->cached)
+			continue;
+
+		vb2_ion_sync_for_device(&buf->cookie, buf->cookie.offset,
+						buf->size, DMA_FROM_DEVICE);
+	}
+
+	return 0;
+}
+
+void vb2_ion_detach_iommu(void *alloc_ctx)
+{
+	struct vb2_ion_context *ctx = alloc_ctx;
+
+	if (!ctx_iommu(ctx))
+		return;
+
+	iovmm_deactivate(ctx->dev);
+}
+EXPORT_SYMBOL_GPL(vb2_ion_detach_iommu);
+
+int vb2_ion_attach_iommu(void *alloc_ctx)
+{
+	struct vb2_ion_context *ctx = alloc_ctx;
+
+	if (!ctx_iommu(ctx))
+		return -ENOENT;
+
+	return iovmm_activate(ctx->dev);
+}
+EXPORT_SYMBOL_GPL(vb2_ion_attach_iommu);
+
+MODULE_AUTHOR("Jonghun,	Han <jonghun.han@samsung.com>");
+MODULE_DESCRIPTION("Android ION allocator handling routines for videobuf2");
+MODULE_LICENSE("GPL");